901713B_Sigma_6_Reference_Man_Jun71 901713B Sigma 6 Reference Man Jun71
901713B_Sigma_6_Reference_Man_Jun71 901713B_Sigma_6_Reference_Man_Jun71
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•
Xerox SIGMA 6 Computer
Reference Manual
...
.~I
XEROX SIGMA 6 INSTRUCTIONS
Mnemonic
Code
In$truction Nome
Page
LB
LH
L':I
LD
LCH
LAH
LCW
LAW
LCD
LAD
LS
LM
LCFI
LCF
XW
STB
STH
STW
STD
STS
STM
STCF
22
72
52
32
12
5,0.
5B
3,0.
3B
1,0.
IB
4,0.
2,0.
02
70
46
75
55
35
15
47
2B
74
.
Load Immediate
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Load
Byte
Hallward
Ward
Doubleword
Complement Hallward
Absolute Hallward
Complement Word
Absolute Word
Complement Doubleward
Absolute Doubleword
Selective
Multiple
Load Conditions and Floating Control Immediate
Load Condition. and Floating Control
Exchange Word
Store Byt.
Store Hallward
Store Word
Store Doubleword
Store Selective
Store Multiple
Store Condition. and Floating ConlJol
32
32
32
32
32
33
33
33
33
33
34
34
35
35
35
36
36
36
36
36
36
37
37
6B
20
50
30
10
58
38
18
23
57
37
56
36
66
73
53
33
Add Immediate
Add Hallward
Add Word
Add Doub leward
Subtract Hallward
Subtract Word
Subtract Doubleward
Multiply Immediate
Multiply Hallward
Multiply Word
Divide Hallward
Divide Word
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Add Short
Add Long
Subtract Short
Subtract Long
Multiply Short
Multiply Long
Divide Shart
Divide Long
51
51
51
52
52
52
52
52
7E
7F
79
78
7B
7A
70
7C
76
77
Decimal
Decimal
Decimal
Decimal
Decimal
Load
Store
Add
Subtract
Multiply
56
56
57
57
57
DECIMAL
DL
DST
DA
OS
OM
DO
DC
DSA
PACk
UNPk
31
39
39
PUSH DOWN
40
40
40
40
41
41
41
42
42
42
PSW
PLW
PSM
PLM
MSP
37
Analyze
Interpret
3D
10
3C
IC
3F
IF
3E
IE
FAS
FAL
FSS
FSL
FMS
FML
FDS
FDl
MIS
CBS
TBS
HBS
EBS
FIXED-POINT ARITHMETIC
AI
AH
AW
AD
SH
SW
SO
MI
MH
MW
DH
OW
AWM
MTB
MTH
MTW
~
Decima I Oi vide
Decimal Compar.
Decimal Shift Aritlvnetic
Pock Decimal Digits
58
58
58
Unpack Decimal Digits
59
59
61
60
.1
40
63
Move Byte String
Compare Byte String
Translate Byte String
Tran. late and Test Byte String
Edit Byte String
61
62
63
63
64
09
Push Word
Pull Word
Push Mu hiple
Pull Multiple
Modify Stock Pointer
69
69
70
70
71
Execut.
Branch on Condition. Set
Branch on Conditions Reset
Branch on Incrementing Regist.r
73
73
73
73
Branch on Decrementing Regist.r
Branch and Link
7.
74
Calli
Call 2
Call 3
Call.
n
n
n
n
BYTE STRING
ANALYZE/ INTERPRET
ANLZ
INT
Instruction Nome
FLOATING-POINT ARITHMETIC (!!I!!ionol)
LOAD STORE
LI
Code
Mnemonic
Add Word 10 Memory
Modify and Test Byte
Modily and Te.t Hallward
Mod ily and Te.t Word
43
43
43
Compore Immediat.
44
44
45
45
45
45
46
46
44
08
OB
OA
13
EXECUTE/BRANC H
EXU
BeS
BeR
BIR
BDR
BAL
67
69
68
65
64
6A
COMPARISON
CI
CB
CH
CW
CD
CS
CLR
CLM
21
71
51
31
II
45
39
19
Compore
Compare
Compare
Compare
Byte
Halfword
Word
Doubleward
Compare Selective
Compare with Limits in Register
Con:'pore with Limits in Memory
LOGICAL
OR
EOR
AND
49
48
4B
OR Word
Exclu.ive OR Ward
AND Word
46
46
46
SHIFT
S
SF
25
24
Shilt
Shift Floating
...
29
28
Convert by Addition
Convert by Subtroc.tion
CALI
CAL2
CAL3
CAL.
04
05
06
07
CONTROL (prIvileged)
LPSD
XPSD
LRP
MIN:.
WAIT
RD
WD
OE
OF
2F
6F
2E
6C
60
Load Program Slotu. Doubleward
Exchange Program Status Doubleword
73
Load
75
75
77
'II
'II
Regilter Pointer
Move 10 Memory Control
Wait
Rood Direct
Write Direct
.7
INPUT/OUTPUT (prIvileged)
49
50
SIO
HIO
TlO
TDV
AIO
CONVERSION
CVA
CVS
CALL
4C
4F
.0
4E
6E
73
Start Input/ Output
Halt Input/ Output
Test Input/ Output
83
86
86
Telt Device
87
87
Acknowledge Input/ Output Interrupt
XEROX
Xerox SIGMA 6 Computer
Reference Manual
90 17 138
June
© 1970. 1971. Xerox Corporation
1971
File No.: 1X13
XL47, Rev. 0
Printed in U.S.A.
REVISION
This publication is a revision of the Xerox SIGMA 6 Computer Reference Manual, 90 17 13A, and describes the
new SIGMA 6 Computer System features. Changes to the previous manual are indicated by a vertical line in the
margin of the affected page.
RELATm PUBLICATIONS
Publication No.
Xerox Sigma Glossary of Computer Terminology
90 09 57
Xerox Meta-Symbol/LN,OPS Reference Manual
900952
Xerox Symbol/lN,OPS Reference Manual
90 1790
Xerox Macro-Symbol/LN,OPS Reference Manual
90 1578
Manual Type Codes: SP - batch processing, LN - language, OPS - operations, RBP - remote batch processing,
RT - real-time, SM - system management, 15 - time-sharing, UT - utilities.
All SPECIFICATIONS SUBJECT TO CHANGE WITHOUT NOTICE
ii
CONTENTS
1.
2.
Introduction
General Characteristics
Standard and Optional Features
Real-Time Features
General-Purpose Features
Time-Sharing Features
Multiuse Features
1
1
4
4
5
6
6
SIGMA 6 SYSTEM ORGANIZATION
8
Information Format
Core Memory
Dedicated Memory Locations
Information Boundaries
Computer Modes
Master Mode
Slave Mode
CPU Fast Memory
Central Processing Unit
General Registers and Register Block Pointer_
Memory Control Storage
Memory Map and Acc.ess Protection
Instruction Format
Immediate Operand
Memory Reference Addresses
Memory Address Control
Memory Map and Access Protection
Memory Write Locks
Program Status Doubleword
Interrupt System
Internal Interrupts
External Interrupts
States of an Interrupt Level
Control of the Interrupt System
Time of Interrupt Occurrences
Singl e-Instruction Interrupts
Trap System
Nonallowed Operation Trap
Unimplemented Instruction Trap
Push-Down Stack Limit Trap
Fixed-Point Overflow Trap
Floating-Point Arithmetic Fault Trap
Decimal Arithmetic Fault Trap
Watchdog Timer Runout Trap
Call Instruction Traps
3.
Unimplemented Floating-Point Instructions _ _
Floating-Point Add and Subtract
Floating-Point Multiply and Divide
Condition Codes for floating-Potnt
Instructions _ _ _ _ _ _ _ _ _ _ _ _
Deci mal Instructions
Packed Decimal Numbers
Zoned Decimal Numbers
Decimal Accumulator
Decimal Instruction Format
Illegal Digit and Sign Detection
Overflow Detection
Decimal Instruction Nomenclature
Condition Code Settings
Byte-String Instructions
Push-Down Instructions
Stack Pointer Doubleword
Push-Down Condition Code Settings
Execute/Branch Instructions
Ca II Instructi ons
Control Instructions
Program Status Doubleword
Loadi ng the Memory Map
Loadi ng the Access Protection Controls
Loadi ng the Memory Wri te Protecti on Locks __
Interruption of MMC
Read Direct Internal Computer Control
(Mode 0) _ _ _ _ _ _ _ _ _ _ _
SIGMA 6 SYSTEM
8
8
8
8
9
9
9
9
10
11
11
11
11
12
12
14
14
15
17
18
18
20
20
21
21
22
22
22
'24
25
25
26
26
26
27
INSTRUCTION REPERTOIRE
28
Load/Store Instructions _ _ _ _ _ _ _ _ _ _
Anal yze/Interpret Instructions
Fixed-Point Arithmetic Instructions
Comparison Instructions
Logical Instructions
Sh ift Instructions
Floating-Point Shift
Conversion Instructions
Floating-Point Arith'metic Instructions
Floating-Point Numbers
31
37
39
44
46
47
48
49
50
50
4.
5.
52
52
52
53
54
55
55
55
55
55
55
56
56
60
67
68
68
72
74
75
75
78
78
79
79
80
Write Direct Internal Computer Control
(Mode 0)
Write Direct, Interrupt Control (Mode 1) _ _ _
Input/Output Instructions
I/O Address
I/O Unit Address Assignment
I/O Status Response
Status Information for SIO
81
81
82
82
82
82
83
IN PUT/OUTPUT OPERA TIO NS
89
lOP Command Doublewords
Order
Memory Byte Address
Flags
Byte Count
90
90
91
91
92
OPERATOR CONTROLS
93
Processor Control Panel
POWER
CPU RESET/CLEAR
I/O RESET
LOAD
UNIT ADDRESS
SYSTEM RESET/CLEAR
NORMAL MODE
RUN
WAIT
93
93
93
94
94
94
94
94
94
94
iii
INTERRUPT
PROGRAM STATUS DOUBLEWORD
INSERT
INSTR ADDR
ADDR STOP
SE LECT ADDRESS
STORE
DISPLAY
DATA
COMPUTE
CON TROL MODE
MEMORY FAULT
ALARM
AUDIO
WATCHDOG TIMER
INTERLEAVE SELECT
PARITY ERROR MODE
PHASES
RE GISTER SELECT
SENSE
CLOCK MODE
Loading Operation
Load Procedure
Load Operation Details
94
94
94
95
95
96
96
96
96
96
97
97
97
97
97
97
97
98
98
98
98
98
98
99
135
INDEX
APPENDIXES
A.
iv
REFERENCE TABLES
100
XDS Standard Symbols and Codes
XDS Standard Character Sets
Control Codes
Special Code Properties
XDS Standard 8-Bit Computer Codes
(EBCDIC)
XDS Standard 7-Bit Communication Codes
(ANSCII)
XDS Standard Symbol-Code Correspondences _ _
Hexadecimal Arithmetic
Addition Table
Multiplication Table
Table of Powers of Sixteenl0
Table of Powers of Ten16
Hexadecimal-Decimal Integer Conversion
Table
Hexadecimal-Decimal Fraction Conversion
Table
Table of Powers of Two
Mathematical Constants
100
100
100
100
B.
REFERENCE DIAGRAMS
Notes on Basic SIGMA 6 Instruction Execution
Cycle
Basic SIGMA 6 Instruction Execution Cycle _ _
Floati ng-Point Instruction Execution
Floating-Point Multiplication and Division __
Floating-Point Addition and Subtraction _ _ _
Floating-Point Shift
Edit Byte String Instruction Execution
1.
119
1
122
122
123
124
125
C.
SIGMA 6 INSTRUCTIONS (MNEMONICS)
126
D.
INSTRUCTION TIMING
128
FIGURES
SIGMA 6 Computer System
v
1.
A Typical SIGMA 6 System
2
2.
Information Boundaries
9
3.
SIGMA 6 Central Processing Unit
10
4.
Index Displacement Alignment
14
5.
Generati on of Actua I Memory Addresses
16
6.
Typical Interrupt Priority Chain
7.
Operational States of an In~errupt Level
~
8.
Processor Control Panel
93
101
101
102
106
106
106
107
107
108
114
118
118
TABLES
1.
SIGMA 6 Dedicated Memory Locations
SIGMA 6 Interrupt Locations
3. Summary of SIGMA 6 Trap System
4. Glossary of Symbolic Terms
5. ANALYZE Table for SIGMA 6 Operation Codes_
6. Floating-Point Number Representation
7. Condition Code Settings for Floating-Point
Instructions
8. Status Bits for I/O Instructions
9. Program Status Doubleword Display
D-1. Basic Instruction Timing
D-2. Additional Instruction Timing
2.
'l
19
23
30
38
51
53
84
95
129
133
·
6 Computer
Sigma
1. SIGMA 6 SYSTEM
INTRODUCTION
The SIGMA 6 computer system can concurrently process
operations for business, engineering/scientific, and generalpurpose applications. The basic system consists of a central
processor, 32, 768 words of memory, and independent, multiplexed I/O capability. It is easily expandable by adding
memory units, input/output processors, and peripheral devices. Figure 1 shows a typical SIGMA 6 system.
A SIGMA 6 system consists of the following major elements:
•
A memory consisting of up to four magnetic core storage
units.
•
A central processor unit {CPU} that addresses core memory, fetches and stores information, performs arithmetic
and logical operations, sequences and controls instruction execution, and controls the exchange of information
between core memory and other elements of the system.
•
An i nput/output system cor.troll ed by one or more i nput/
output processors {lOPs}, each providing data transfer
between core memory and peripheral devices. The lOPs
have separate access to core memory which are independent of the CPU. They operate asynchronously
and simultaneously with the CPU.
GENERAL CHARACTERISTICS
A SIGMA 6 computer system has features and operating
characteristics that permit efficient functioni ng in realtime, general-purpose, time-sharing, and multiuse computing
envi ronments:
•
•
Word-oriented memory {32-bit word plus parity bit}
which can be addressed and altered as byte (8-bit),
halfword {2-byte}, word {4-byte}, and doubleword
(8-byte) quantities.
•
•
•
Sixteen general-purpose registers, expandable (in
blocks of 16) to 512 to reduce transfer of data into and
out of registers in a multiuse environment.
•
Hardware memory mapping, which obviates the problem
of memory fragmentation and provides dynamic program
relocation.
•
Selective memory access protection with four modes for
system and information security and protection.
•
Selective memory-write protection.
•
Watchdog timer, assuring nonstop operation.
•
Real-time priority interrupt system with automatic identification and priority assignment, fast response time,
and up to 235 levels that can be individually armed,
enabled, and triggered by program control.
•
Interrupti bi Ii ty of long i nstructi ons, guarantee i ng fast
response to interrupts.
•
Automatic traps, for error conditions and for simulation
of optional instructions not physically implemented, all
under program control.
•
Power fai I-safe, for automatic, safe shutdown in the
event of a power failure.
•
Multiple interval timers, with a choice of resolutions
for independent time bases.
•
Privileged instruction logic {master/slave modes}, for
concurrent, time-shared operati on.
•
Complete instruction set including:
•
Byte, halfword, word, and doubleword operations.
•
Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
the normal instruction format.
•
Multiple register operations.
•
Fixed-point arithmetic operations in halfword,
word, and doubleword modes.
•
Optional floating-point hardware operations, in
short and long formats, with significance, zero,
and normalization control and checking, all under
program control.
Displacement index registers, automatically selfadjusting for all data sizes.
•
Full complement of logical operations {AND, OR,
exclusive OR}.
Immediate addressing' of operands, for greater storage
efficiency and increased speed.
•
Comparison operations, including compare between
limits {with limits in memory or in registers}.
Full parity checking for both CPU/memory and input/
output operations.
Memory expandable from 32,768 to 131,072 words
{131 ,072 to 524,288 bytes} in increments of 16,384 words.
•
•
Direct addressing of the entire core memory, within the
primary instruction word and without the need for base
registers, indirect addressing, or indexing.
Indirect addressing, with or without postindexing.
SIGMA 6 System
CENTRAL PROCESSOR UNIT
(CPU)
Standard Features:
•
Decimal arithmetic unit
•
Memory mop
•
•
•
•
•
•
Access protection
Memory write protection
Two register blocks
Power fail-safe
Two reol-time clacks
External interface (direct
VOl
Optional Features:
•
Two additional real-time clacks
30 additional register blocks
Floating-point arithmetic
External priarity interrupt system
(up to 224 levels)
•
•
•
MEMl:: - --- - - - - r=---=-~:-eM-:1-uNiT - - -1
I
Standard Features:
I
I
I
•
•
•
I
I
I
I
I
I
16,384 or
32,768 words
Two ports (multiaccess)
Two-way interleaving
Four-woy interleaving
Parity checking
•
I
Optional Features:
•
Four additional ports
•
Memory system expandable by
adding up to three additional
32K memory units
I
Standard Features:
I
32,768 words
Two ports (multiocess)
Two-way interleaving
Four-way interleaving
Parity checking
I
Optional Features:
I
•
:
Four odditional ports
L--.---T'""""'-----'
'--___.==.
.==.=..:.r..............•.....................•...•...•....••........•.•....••.•.•.!
.::.:=.~.=.=.=.===
:
I
:
I
...-_ _ _ _ _-..1._ _ _ _:..'_--. - - - - - - - - - - - - - - - - - - - .
r - MIOP EXPANsION OPTION-
MUlTIPLEXING INPUT/OUTPUT
PROCESSOR (MIOP)
Standard Features:
•
•
•
•
•
One device controller
per subchonnel
ISDIENVGICLEE UNIT II ··· IMULTI~UNIT
DEVICE
IE£!'I~~L!RJ
I
I..-
T -I
r-----,
DEVICE..JI
Ir -t'-1/0
____
Ii/O~VlC~ .
L.. _ _ _ _ "
I
L fiiO
I
•
I
I
I
I
~------,
I
I
r.--1-~
r-J.--, r-J--,
I DEVICE
I
I DEVICE
I
ICONTROlLERI' • 'ICONTROLLERI
L_,---i
L..;.-T- .....
L_,_-J
I
I
r--L-,~_J-:1
I
rVODEvlcE]
I~ L~
__
~O ~~~
lYO
~~~
.
(Up 10
:
pl
--------------Standard-$PMd peripheral devices - - - - - - - - - - - -.....
1- High-speed peripheral devices -I
Note: Standard units and pracessan are shown enclosed with solid barder lines. Optional units, processors, device contrallen,
- - and devices are enclosed with clashed barder lines. Standard and optional features within a unit or processor are as listed.
Figure 1.
General Characteristics
I
Ll~de~ces) J
~~e~~J
2
32 device control/en
L-I.-Vo DeVICE!
1I
DEViCE
. , (Up to
I
L--r-------J
I
I
I
I
--:1
I MULTI-UNIT I
I DEVICE
I . • '1 DEVICE
I
I CONTROLLERJ
I CONTROLLER I
I SINGLE UNIT I
I
I
I
r.- J
I
Accommodates:
One device contraller
I
I
~~~O'!:!:E.!J
~V~ J
I
subchannel
L __per,_____
,__
I
r.:-.J.._:j
Single-byte interface
Four-byte interface
I
Accommodates:
Accommodates:
I
Stondard Features:
I
Two additional groups aF eight
subchonnels
Two additional groups of eight
subchannels
_..l-:::-1
One group of eight subchannels
Single-byte interface
Optional Features:
Optianal Features:
[1/0
I
I
Standard Features:
One group of eight subchonnels
Single-byte interface
Four-byte interface
r;:--1--,
r - -smcroRi~puT/OUTPUT-1
Il
PROCESSOR (SlOP)
I
-,
(ONE PER MIOP)
A Typical SIGMA 6 System
•
Call instructions permitting up to 64 dynamically
variable, user-defined instructions, and permitting
a program to gain access to operating system functions without operating system intervention.
•
Decimal hardware operations, including arithmetic, edit, and pack/unpack.
•
•
•
•
•
Push-down stack operations (hardware implemented) of single or multiple words, with automatic limitchecking, for dynamic space allocation,
subrouti ne communication, and recursive routine
capabi I ity.
•
Automatic conversion operations, including binary/
BCD and any other weighted-number systems.
An analyze instruction, for facilitating effective
address computation.
•
An interpret instruction, for increased speed of
interpretive programs.
•
Shift operations (left and right) or word or doubleword, including logical, circular, arithmetic, and
floating-point modes.
•
Allows the transfer of a 32-bit data word between
an affected regi ster and an external devi ce. In add ition, a 16-bit address is transferred for selection and
control purposes. Each transfer is under direct
program control.
•
Is used for the attachment of external units to the
direct I/O interface. External units may be Xerox
external interrupts, Xerox system interface units,
or nonstandard special equipment.
Comprehensive complement of modular software:
•
Expands in capabi I i ty and speed as system grows.
•
Basic system programming support: "Stand-Alone"
Systems and Basic Control Monitor (BCM).
•
Operating systems: Real-time Batch Monitor
(RBM), Batch Processing Monitor (BPM), Batch
Time-Sharing Monitor (BTM), Universal TimeSharing System (UTS), and Xerox Operating System (XOS). When larger computing capacity is
required, UTS and XOS users can expand to the
Xerox SIGMA 9 Computer.
•
Language processors that include: FORTRAN IV -H,
Extended Xerox FORTRAN IV, Xerox ANS COBOL,
BASIC, FLAG, Symbol, Macro-Symbol, MetaSymbol; also, utilities and applications software
for both commercial and scientific users, e. g. ,
Data Management System (DMS), General ized
Sort and Merge, Manage, 140 1 Simulator, Functional Mathematical Programming System (FMPS),
FMPS Matrix Generator/Report Writer (GAMMA3),
Simulation Language (SL-l), General Purpose Discrete Simulation package (GPDS), Circuit
Analysis Systems (CIRC-AC, CIRC-DC), etc.
Independently operating input/output system with the
following features:
•
Direct input/output of a full word, without the
use of a channel.
•
Up to eight input/output processors (lOPs).
•
Multiplexor input/output processors (MIOPs) for
simultaneous operation of up to 24 devices per
lOP.
•
MIOP expansion option for simultaneous operation
of up to 24additional devices, and includes conflictresolving circuitry that allows it to share a memory
bus with an MIOP.
•
Selector input/output processors (SlOPs) (8 or 32
bits wide}for data transfer rates approaching 4 mi IIi on bytes per second.
•
Up to 32 device controllers can be connected to
each SlOP.
•
Both data and command chaining, for gather-read
and scatter-write operations.
•
Up to 32,000 output control signals and input test
signals.
External interface feature that:
•
Provides an exter-nal interface for the attachment of
external equipment to a SIGMA 6 computer via the
Direct I/O system (Write Direct/Read Direct).
•
Standard and special-purpose peripheral equipment
includes:
•
Rapid Access Data (RAD) fi les: Capacities to
6.2 million bytes per unit; transfer rates to 3 -million bytes per second; average access times from
17 mi lIiseconds.
•
Magnetic tape units: 7-track and 9-track systems, IBM-compatible; high-speed units operate
at 150 inches per second wi th transfer rates up
to 120,000 bytes per second; and other units
operate at 37.5 inches per second with transfer
rates up to 20,800 bytes per second and at 75 inches
per second with transfer rates up to 60,000 bytes
per second.
•
Displays: Graphic display has standard character
generator, vector generator, and close-ups, as
well as I ight pen and alphanumeric/function keyboard with a display rate of up to 100,000 characters per sec ond.
General Characteristics
3
•
•
•
•
•
•
Card equipment: Reading speeds of up to 1500 cards
per minute; punching speeds of up to 300 cards per
minute; intermixed binary and EBCDIC card codes.
A SIGMA 6 system may have the following optional features:
•
Two additional real-time clocks
Line printers: Fully buffered, with speeds of up
to 1500 lines per minute; 132 print positions with
64 characters.
•
Up to 30 additional register blocks
•
Floating-point arithmetic unit
Keyboard/printers: Ten characters per second;
also available with integral paper tape reader
(20 characters per second) and punch (10 characters per second).
•
Up to 224 external priority interrupts
•
Up to four additional memory ports
•
Up to three additional Multiplexor I/O Processors
(MIOPs)
•
Up to two additional groups of eight multiplexor subchannels with each MIOP
•
MIOP expansion option for each MIOP with 4-byte
interface and one group of eight subchannels
•
Selector Input/Output Processor (SlOP) with 4-byte
interface
Paper tape equipment: Readers with speeds of up
to 300 characters per second; punches with speeds
of up to 120 characters per second.
Graph plotters: Digital incremental, providing
drift-free plotting in two axes in up to 300 steps
per second at speeds from 30 mm to 3 inches per
second.
Data communications equipment: A complete line
of character- and message-oriented equipment to
connect remote user terminals to the computer system via common carrier lines and local terminals
directly.
STANDARD AND OPTIONAL FEATURES
A basic SIGMA 6 system has the following standard
features:
•
A CPU that includes:
•
•
•
•
Decimal arithmetic unit
Memory map with access protection
Memory write protection
Watchdog timer
•
•
•
Two register blocks
•
•
•
•
Memory parity interrupt
Two real-time clocks
Power fa ii-safe
Input/output interrupt
Control pane I interrupt
External interface (Direct I/O)
•
32,768 words of main memory with two ports
•
Multiplexor Input/Output Processor with eight subchannels and 4-byte interface feature.
4
Standard and Opti ona I/Rea 1- Ti me Features
I
REAL-TIME FEATURES
Real-time appl ications are characterized by a need for hardware that provides quick response to an external environment,
enough speed to keep up with the real-time process and sufficient input/output flexibility to handle a variety of data
types at varying speeds. The SIGMA 6 system includes provisions for the following real-time computing features.
Multi level, True Priority Interrupt System. The real-time
oriented SIGMA 6 system provides for quick response to interrupts bymeans of up to 224 external interrupt levels. The
source of each interrupt is automatically identified and responded to according to its priority. For further flexibility
each level can be individually disarmed (to discontinue accepting inputs to it) and disabled (to defer responding to it).
Use of the disarm/disable feature makes programmed dynam;c
reassignment of priorities quick and easy, even while a realtime process is in progress. In establishing a configuration for
the system, each group of 16 interrupt levels can have its
priority assigned in different ways in order to meet the specific needs of the problem; the way in which interrupt levels
are programmed is not affected by the pri ority assignment.
Programs that deal with interrupts from specially designed
equipment sometimes must be checked out before that
equipment is actually available. To permit simulating this
special equipment, any SIGMA 6 interrupt level can be
triggered by the CPU itself through exec uti on of a si ngle
instruction. This capability is also useful in establishing a
hierarchy of responses. For example, in responding to a
high-priority interrupt, after the urgent processing is completed, it may be desirable to assign a lower priority to the
rema i n i ng porti on in order to respond to other cri ti ca I i nterrupt levels. The interrupt routine can accomplish this by
triggering a lower-priority level, which processes the remaining data only after other interrupts have been handled.
I
Nonstop Operation. When connected to special devices
(on a ready-resume basis), the computer can sometimes
become excessively delayed if the special device does not
respond quickly. A built-in watchdog timer assures that
the SIGMA 6 computer cannot be delayed for an excessive length of time.
Real-Time Clocks. Many real-time functions must be timed
to occur at specific instants. Other timing information is
also needed - elapsed time since a given event, for example,
or the current time of day. SIGMA 6 can contain two (or
four) real-time clocks with varying degrees of resolution
(1/60 second or V8 mi lIisecond, for example) to meet these
needs. These clocks also allow easy handling of separate
time bases and relative time priorities.
Rapid Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve the current operating environment, for continuance
later, whi Ie setting up the new environment. This changing
of environments must be done quickly, with a minimum of
II overhead II costs in time.
In SIGMA 6, each one of up to
32 blocks of general-purpose arithmetic registers can, if
desired, be assigned to a specific environment. All relevant information about the current environment (instructi on
address, current genera I regi s"er block, memory-protecti on
key, etc.) is kept in a 64-bit program status doubleword
(PSD). A single instruction stores the current PSD anywhere in memory and loads a new one from memory to establish a new environment, which includes information
identifying a new block of general-purpose registers. A
SIGMA 6 system can thus preserve and change its operating
environment completely through the execution of a single
i nstructi on.
Simultaneous I/O Channel Operation. The use of a multiplexor input/output processor (MIOP) or MIOP expansion
option permits up to 24 channels with standard-speed devices to operate concurrently; the addition of more MIOPs
increases this throughput.
High-Speed Channel Operation. The use of the selector
input/output processor (SlOP) permits very high-speed data
transfer - up to one 32-bit word per memory cycle. To
meet special needs, data size can be 8 or 32 bits wide.
Memory Protection. Both foreground (real-time) and background programs can be run concurrently ina SIGMA 6
system, because a foreground program is protected against
destructi on by on unchecked background program. Memory write-protection guarantees that protected areas of
memory can be written into only under predefined conditions. Under operating system control, the memory
access-protection feature also prevents accessing of memory for specified combinations of reading, writing, and
instruction acquisition.
Variable Precision Arithmetic. Much data encountered in
real-time systems are 16 bits or less. To permit this length
of data to be processed efficiently, SIGMA 6 provides halfword arithmetic operations in addition to fullword operations. Doubleword arithmetic operations (for extended
precision) are also included.
Direct Data Input/Output. For handl ing asynchronous I/O,
a 32-bit word can be transferred directly to or from a
general-purpose register, so that an I/O channel need not
be occupied with relatively infrequent transmissions.
Interleave/Overlap. To increase processing speeds, memory banks overlap cycles automatically wherever possible.
Core memory addresses can be interleaved modul0-2 or
modul0-4 on a bank basis to increase the probability of
overlapping.
GENERAL-PURPOSE FEATURES
General-purpose computing applications are characterized
primari Iy by an emphasis on computation and internal data
handling. Many operations are performed in floating-point
format and on strings of characters. Other typical characteristics include decimal arithmetic operations, the need to
convert binary numbers into decimal (for printing or display),
and considerable input/output at standard speeds. The
SIGMA 6 system includes the following general-purpose
computer features.
Floating-Point Hardware (optional). Floating-point instructions are avai lable in both short (32-bit) and long
(64-bit) formats. Under program control, the user can
select optional zero checking, normalization, and significance checking (which causes the computer to trap when a
post opera.tion shift of more than two hexadecimal places
occurs in the fraction of a floating-point number). The
significance checki ng feature permits the use of the short
floating-point format (for high processing speed and storage
economy) and the use of the ·Iong format when loss of
significance is detected.
Decimal Arithmetic Hardware. Decimal arithmetic instructions operate on up to 31 digits plus sign. This instruction
set also includes pack/unpack instructions (for converting to/
from the packed format of two digits per byte) and a generalized edit instruction (for zero suppression, check protection,
and formatting byte information with punctuation to displc:y
or print it).
Indirect Addressing. This feature provides for simple table
linkages and permits the user to keep data sections of
his program separate from procedure sections for ease of
maintenance.
Displacement Indexing. The technique of indexing by
means of a IIfloating li displacement permits the user to
access the desired unit of data without the need to consider its size. The index registers automatically align
themselves appropriately; thus, the same index register
can be used on arrays with different data sizes. For exomple, in a matrix multiplication of any array of fullword,
single-precision, fixed-point numbers, the results can be
stored in a second array as double-precision numbers, using
the same index quantity for both arrays. If an index register contains the value of k, then the user always accesses
the kth element, whether it is a byte, halfword, word, or
doublaword. Incrementing by various quantities according
to data size is not required; instead, incrementing is always
General-Purpose Features
5
by units in a continuous array table no matter which size
of data element is used.
Powerful Instruction Set. The availability of more than
100 major instructi ons results in programs that are short,
rapidly assembled, and quickly executed.
Translate Instruction. This instruction permits rapid translation between any two 8-bit codes (such as EBCDIC to
ANSCII); thus data from a variety of input sources can be
easi Iy handled and reconverted for output.
Conversion Instructions. Two generalized conversion instructions provide for bidirectional conversions between
internal binary and any other weighted number system,
including BCD.
Call Instructions. Four instructions permit handling up to
64 user-defined subroutines (as if they were built-in
machine instructions) and gaining access to specified operating system services without requiring its intervention.
Interpret Instruction. This instruction simplifies and speeds
interpretive operations such as compi Iing, thus reducing the
space and time requirements for compilers.
Four-Bit Condition Code. This feature simplifies the
checking of results by automatically providing information
on almost every instruction execution (including indicators
for overflow, underflow, zero, minus, and plus, as appropriate) without requiring an extra instruction execution.
TIME -SHARING FEATURES
Time-sharing is the abi lity of a computer system to share
its resources among many users at the same time. Each
user may perform a different task that requires a different
share of the avai lable resources and, in many instances,
each may be on-line in an interactive ("conversational")
mode with the computer. Other users may enter work to be
batch processed. The SIGMA 6 system provides for the following time-sharing computer features.
Rapid Context Saving. When changing from one user to
another, the operating environment can be switched quickly
and easi Iy. Stack-manipulating instructi ons permit from
one to 16 general-purpose registers to be stored in a pushdown stack by a single instruction - with automatic updating
of stack status information - and to be retrieved (again, by
a single instruction) when needed. The current program
status doubleword (which contains the entire description of
the current user's environment and mode of operation) can
be stored anywhere in memory and a new program status
doubleword loaded, all with a single instruction.
Multiple Register Blocks. The optional avai lability of up
to 32 blocks of 16 general-purpose registers further improves
response time by reducing the need to store and load register blocks. As needed, ea~h user can be assigned a distinct
block; the program status doubleword automatically points
to the currently appl icable register block.
6
Time-Sharing/Multiuse Features
User Protection. The slave mode of operati on restricts each
user to his own set of instructions while reserving to the
operating system those instructions that could, if used in- ~
correctly, destroy another user's prog:am. A memory acce~
protection system prevents any user from accessing storage
areas other than those assigned to him. This access protection permits the user to access certain areas for reading only,
such as those containing public subroutines, whi Ie preventing
him from reading, writing, or accessing instructions in areas
set aside for other users.
Storage Management. SIGMA 6 memories are available in
seven sizes (from 32,768 to 131,072 words) to provide the capacity needed, while assuring potential for expansion. To
assure efficient use of available memory, the memory map
hardware permits storing a user's program in fragments (as
small as 512 words) wherever space is available; yet, all
fragments appear as a single, contiguous block of storage at
execution time. The memory map also automatically and
dynamically handles program relocation, so that the program appears to be stored in a standard way at execution
time (even though it may actually be stored in a different
set of locations each time it is brought into memory). The
memory map for the full-sized SIGMA 6 memory is provided
no matter how sma II the actua I memory may be. Th us, the
system can always address a virtual memory of 131,072 words
regardless of physical memory size.
I'
Input/Output Capability. Sigma 6 can control up to eight I
input/output processors (of two types) in various combinations. Each multiplexor I/O processor or MIOP expansiort-"
option can have up to 24 standard-speed I/O channels operating simu Itaneously; selector I/O processors can have any
one of up to 32 high-speed I/O devices operating on each
processor. The I/O processors operate semi-independently
of the central processor, leaving it free to provide faster
response to overall system needs.
Nonstop Operation. A watchdog timer assures that the
system conti nues to operate even if certain special I/O
capabilities are used with special devices that can cause
delays or halts if they fail. Multiple real-time clocks with
varying resolutions permit establishing several independent
time bases, thus allowing flexible allocation of time slices
to each user.
MULTIUSE FEATURES
As implemented in the SIGMA 6 system, II multi use II combines two or more computer applicati on areas. The most
difficult computing problems are associated with real-time
applications. Simi larly, the most difficult multiuse problems are associated with time-sharing applications that
include one or more real-time processes. SIGMA 6 system design is especially suited for a mixture of applications in a multiuse environment. Many of the hardware
features that are required for specific application areas
are equally useful in others, although in different ways.
This multiple capabi lity makes SIGMA 6 particularly effectiv.", for multiuse applications. The major SIGMA 6 multiuse
computer features are:
Priority Interrupt. In a multiuse environment, many elements operate asynchronously. Thus, a true pri ority i nterrupt system is essential. It allows the computer system
to respond quickly {and in proper order} to the many demands made on it, without the high overhead cost of
compl icated programming, lengthy execution time, and
extensive storage allocations.
Quick Response. The many features that combine to produce a quick-response system - multiple register blocks,
quick context saving, push-pull operations - benefit all
users because more of the computer's resources are available for useful work.
Memory Protection. The memory protection features protect
each user from every other user and also guarantee the
integrity of programs that are essential to critical real-time
applications.
Input/Output. Because of its wide range of capacities
and speeds (with and without channels), the SIGMA 6
I/O system simultaneously satisfies the needs of many
different application areas economically, both in terms of
equipment and of programming.
Instruction Set. The large SIGMA 6 instruction set provides the computational and data-handling capabilities
required for widely differing application areas; therefore,
each user's program length (thus running time) is decreased
and the speed of obtaining results is increased.
Multiuse Features
7
2. SIGMA 6 SYSTEM ORGANIZATION
The primary el ements in a basic SIGMA 6 system - a centrai
processor, core memory, and input/output processor - are
all designed around a central, double bus structure.
Each primary element of the system operates asynchronously
and semi -independently, automatically overlapping the operation of the other elements (when circumstances permit)
for greater speed. The basic configuration can be expanded
merely by increasing the number of core memory units
(up to four), increasing the number of buses (up to six),
increasing the number of input/output processors (up to
eight), or by increasing the number of central processors.
INFORMATION FORMAT
The basic element of SIGMA 6 information is a 32-bit word,
in which the bit positions are numbered from 0 through 31,
as follows:
A SIGMA 6 word can be divided into two 16-bit parts
(called halfwords) in which the bit positions are numbered
from 0 through 15, as follows:
Byte 1
Byte 2
SIGMA 6 core memory systems use a 32-bit word (four 8-bit
bytes) plus a parity bit as the basic unit of information, All
of memory is directly addressable by the CPU (except for
memory locations 0 through 15)and by the lOPs. The SIGMA6
addressing capabi lity accommodates a maximum memory size
of 131, 072 words (524,288 bytes). Core memory is modular
and is available in increments of 16, 384 words (65,536 bytes),
The main memory for SIGMA 6 is physically organized as a
group of "units", A memory unit is the smallest, logically
complete part of the system. It is the smallest port that
can be logically isolated from the rest of the memory system. A memory unit may consist of up to two physical
memory banks. Each memory bank operates independently
and asynchronously with respect to each other. 128K words
of main memory is comprised of four memory units. The
memory is word, halfword, and byte addressable for both
reading and writing. Each memory unit has a set of "ports"
that are common to both banks within the unit; that is,
all ports in a given memory unit give access to the bonks
within that unit. The basic system is provided with two
ports, expandable to six.
The memory system has 2-way interleaving capabi lity within
a unit and 4-way interleaving between two adjacent units.
Interleaving increases the probabi lity that a processor can
gain access to a given memory bonk without encountering
interference from other processors: A multiple bonk system
increases the probability that successive memory accesses
may be overlapped. In combination, these two features
provide the SIGMA 6 system with effective memory cycle
times of a fraction of the individual bonk cycle times.
A SIGMA 6 word can also be divided into four 8-bit parts
(called bytes) in which the bit positions are numbered from
o through 7, as follows:
Byte 0
CORE MEMOR't'
Byte 3
DEDICATED MEMORY LDCATIONS
Memory locations 0 through 319 are reserved by standard
XDS software for dedicated purposes as shown in Table 1.
Two SIGMA 6 words can be combined to form a 64-bit
element (called a doubleword) in which the bit positions
are numbered from 0 through 63, as follows:
INFORMATION BOUNDARIES
I
:
least
si9ni~cant ward:
d 52
I
SIGMA 6 instructions assume that bytes, halfwords, and
doublewords are located in storage according to the
following boundary conventions:
1.
A byte is located in bit positions 0 through 7, 8
through 15, 16 through 23, or 24 through 31 of a word.
Four bits of information can be expressed as a single hexadecimal digit. A byte can be expressed as a 2-digit hexadecimal number, a halfword as a 4-digit hexadecimal
number, a word as an 8-digit hexadecimal number, and a
doubleword as a 16-digit hexadecimal number. In this
reference manual, a hexadecimal number is displayed as
a string of hexadecimal digits enclosed by single quotation
marks and preceded by the letter X". For example, the
binary number 01011010 is expressed hexadecimally as
2.
A halfword is located in bit positions 0 through 15 or
16 through 31 of a word.
3.
A doubleword is located such that bits 0 through 31 of
the doubleword are contained within an even-numbered
word, and bits 32 through 63 of the same doubleword
must be contained within the next consecutive (oddnumbered) word.
X ' 5A',
The various information boundaries are illustrated in Figure 2.
32 33 34 35136 37 38 39 40 41 42 43144 45 46 47 48 49 50 5
II
8
51 GMA 6 System Organization
53 54 55 56 57 58 59160 61 62 63
i
Doubleword
I
I
Doubleword
I
.•
I
I
Word (even address)
!
i
I
Halfword 1
Halfword 0
Halfword 0
Word (odd address)
Word (even address)
Word (odd address)
Halfword 1
Halfword 0
Hal fword 1
Halfword 0
Halfword 1
1
I
I
iI
: Byte 01 Byte 1 Byte 21 Byte 3 Byte 0 1 Byte 1 Byte 2/ Byte 3 Byte 0 / Byte 1 Byte 2\ Byte 3 Byte 0 Byte 1 Byte 2[ Byte 3!
Figure 2.
Table 1.
SIGMA 6 Dedicated Memory Locations
Location
Hexadecimal
Decimal
0
Information Boundaries
Function
0
Addresses of general registers
15
F
16
10
COMPUTER MODES
The SIGMA 6 computer operates in either the master mode
or the slave mode. The mode of operation is determined
by the state of the master/slave mode control bit in the
arithmetic and control unit.
MASTER MODE
Reserved for future use
31
1F
32
33
20
21
34
22
41
29
42
2A
63
3F
64
40
Cpu/Iop communication
Program stored by LOAD
switch on the processor panel
SLAVE MODE
First record read from periphera device during a load
operation
Traps (see Table 3)
79
4F
80
50
87
57
88
58
91
5B
92
93
5C
5D
Input/output interrupt level/
94
95
5E
5F
Reserved for future use
96
60
t
External interrupt level/
tSee Table 2
13F
The slave mode is the problelT)-solving mode of the computer. In this mode, "privileged" instructions are prohibited. Privileged instructions are those relating to input/
output and to changes in the basic control state of the computer. All privileged instructions are performed in the
master mode only. Any attempt by a program to execute a
privileged instruction while the computer is in the slave
mode results in a return of control to the resident executive program.
Override interrupt levels t
Counter interrupt level/
319
The master mode is the basic operating mode of the
computer. In this mode, all SIGMA 6 instructions are
permissible. It is assumed that there is a resident executive program (operating in the master mode) that controls
and supports the other programs operating in the master
or slave mode.
The master/slave mode control bit can be changed only
when the computer is in the master mode; thus, a slave program cannot directly change the computer mode from slave
to master. However, the slave program can gain direct
access to certain executive program operations by means
of call instructions. The operations available through
call instructions are established by the resident executive program.
CPU FAST MEMORY
Several high-speed integrated circuit memories may be
used in the SIGMA 6 CPU. These memories are capable of delivering information to (or receiving information from) the arithmetic and control unit simultaneously
with the operation of core memory. These memories
are not accessible to any other unit in a SIGMA 6
system.
Computer Modes/CPU Fast Memory
9
CENTRAL PROCESSING UNIT
This section describes the organization and operation of
the SIGMA 6 central processing unit in terms of information processing and program control, instruction and data
formats, indirect addressing and indexing, memory mapping
and protection, overflow and trap conditions, and interrupt control. Basically, the SIGMA 6 CPU consists of
a fast memory and an arithmetic and control unit (see
Figure 3).
CPU fAST MEMORY
ARITHMETIC AND CONTROL UNIT
GENERAL REGISTER BLOCK (nPiCALI
INSTRUCTION REGISTER
o
o I....________~
1~:n~:n~§I~&~m~@~@~@~Th~~@~%~~@~@~ru~w~M~a~
2
3
III I III I
I
8
lil!!:i!!!i:[!I[ttlllIililili!il@ttilIi!illi:it}!ttitl:1!~@!IMI1!@!!i!i!Ii!i!{fi!1
1?:::Iffl:::l:::Ijljl!i!ill:iImt:1:::I1~iI::fliJi::~l:lIllIlllIIiIi}}tIIl
5
1:}I: :i: t: :~l: i ~: i i i:i~i lili il!il :l\l\l liIlili~il:~i~i~\1!1:1\~\1lI1l1l1ltjl :l:l j:lt tl:l:tlt: 1
General Register Designator
11
ITIJ
Index
~ Registers
Operation Code Field
7
ITTIJ
1:~~:::::fII:J:~:lJlI:l:jiI:Il~:~:~::II:1I::ililil:::lilmI1lljIIlllll\llllllItm!ililti::1
4
Indirect Address Flag
o
12
Index Register Designator
,.
Reference Address Field
11111111111111111111
15
.....~--...-jt~
6 1:::t:!!I:t:I:I:Iiili!11!il!lljlIll\illllllllilttIi:lilIJliti!tI::1il!:::!Illl!tl!lH
7
31
I..
f))))))):))))!)!!i~!:r!I:l)ijl)l)!)~!)ljl)~I!!!lj~~IIjjjljljj!j!j!j)))))jI)I!lj:)))I1)!1!Iijj)~1!~~))liI)j)lI!J
•
~
I
a
]
9
Priority Interrupt System
10
Write Direct
PROGRAM STATUS DOUBLEWORD
11
12
o
Condition Code
3
ITTI
31-digit
Decimal
Accumulator
14
15
rrrn
~------------------~ ~
13
o
S
Flooting-point Mode Control
7
Master/Slave Mode Control
o
~------------------~3' ~
Memory Map Control
9
OJ
MEMORY CONTROL STORAGE
Memory Map
Arithmetic Trap Masks
10 \I
Instructian Address
111111111111111111
I - 256 a-bit page addresses ---t
IS
Memory Access Protection
III1I111I1111
~ ~--+-I""-'-II"""'-II
I--- 256 2-bit access codes ~
II1II1III1I11 ~~~II~III
l---- 256 2-bit write locks ---I
Figure 3.
Central Processing Unit
31
OJ
OTI
-
Write Key
343S
Memory Write Protection
10
I
To/From
Core Memory
To/From
I/O Processors
• Read/Write
Direct
__ Interrupts
.•
37
I
Interrupt Inh ibits
39
III
III
ss
Register Block Pointer
59
SIGMA 6 Central Processing Unit
I
I
I
--
GENERAL REGISTERS AND REGISTER BLOCK POINTER
A register block is a high-speed memory consisting of sixteen 32-bit words contained in the basic SIGMA 6 CPU for
general-purpose register usage. A SIGMA 6 contains two
such register blocks (expandable to 32), and a 5-bit control
field (called the register block pointer) in the arithmetic
and control unit selects the block currently available to
a program. The 16 general registers selected by the
register block pointer are referred to as the current register
'block. The register block pointer can be changed only
when the computer is in the master mode; thus, a slave
program cannot change the register block pointer.
Each general register in a current register block is identified
by a 4-bit code in the range 0000 through 1111 (0 through 15
in decimal, or X'O' through X'F' in hexadecimcl notation).
Any general register can be used as a fixed-point accumulator, floating-point accumulator, temporary storage, or can
contain control information such as a data address, count,
pointer, etc. Any (or all) of general registers 1 through 7
can be used as index registers. Registers 12 through 15 are
used as a decimal accumulator that is capable of containing
31 decimal digits plus sign. The use of registers 12 through 15
is automatic when a decimal instruction is executed; however, these registers may be used for other purposes by instructions not in the decimal instruction set.
MEMORY CONTROL STORAGE
Three high-speed integrated-circuit memories are avai 1able for storage of a memory map, a set of memory accessprotection codes, and a set of memory write-protection
codes, all of which can be changed only when the computer
is in the master mode.
MEMORY MAP AND ACCESS PROTECTION
The memory map feature includes high-speed memories for
both the memory map and the access-protection codes. Use
of the map is determined by the state of the memory map
control bit in the arithmetic and control unit.
Memory Map. Two terms are essential to a proper understanding of the memory mapping concept: virtual address
(Jnd actua I address.
A virtual address is a value used by a machine-level program to designate the location of an instruction, the location of an element of data, the location of a data address
(indirect address), or to designate an explicit quantity,
such as a count. Normally, virtual addresses are derived
from programmer-suppl ied labels through an assembly (or
compi lation) process followed by a loading process. Virtual
addresses maya Iso be computed during a program's execution. Thus, virtual addresses include all instruction addresses, data addresses, indirect addresses, and addresses
used as counts within a s~ored program, as well as those
addresses computed by the program.
An actual address is a value used by the CPU t:. access memory for storage or retrieval of information, as required b>, tl1e
execution sequence of an instruction. Thus, actual addresses
designate wired-in hardware storage locations.
When the memory map is not in effect in a SIGMA 6 computer, as determined by the memory map control bit, all
virtual address values above 15 are used by the CPU as actual addresses. Virtual addresses in the range 0 through 15
are always used by the CPU as general register addresses
rather than as core memory addresses. Thus, for example,
if an instruction uses a virtual address of 5 as the address
where a result is to be stored, the result is stored in general
register 5 in the current register block instead of in core
memory location 5.
When the computer is operating with the memory map, virtual addresses in the range 0 through 15 are sti II used as
general register addresses. However, all virtual addresses
above 15 are transformed into actual addresses, by replacing
the high-order portion of the virtual address with a value obtained from the memory map. The memory map replacement
process is descri bed in the secti on II Memory Address Control" .
Memory Access Protection. When the computer is operati ng in the slave mode with the memory map, the accessprotection codes determine whether or not the program may
access instructions from, read from, or write into specific
regions of the virtual address continuum (virtual memory).
If the slave program attempts to access a region of virtual
memory that is so protected, program control is returned to
the executive program. (The access-protection codes are
described in the section "Memory Address Control".)
MEMORY WRITE PROTECTION
The memory write-protection feature operates independently
of the memory map and access protection. The memory
write-protection feature includes the high-speed memory
for the memory write locks. These locks operate in conjunction with a 2-bit field, called the write key, in the
arithmetic and control unit. The locks and the key determine whether or not the program (slave or master) may
alter the contents of specific regions of core memory as
accessed by actual addresses. The write key can be changed
only when the computer is in the master mode; thus the current write key cannot be changed by a slave program. (The
functions of the locks and key are described in the section
"Memory Address Control".)
INSTRUCTION FORMAT
The normal SIGMA 6 memory-addressing instruction has the
following format:
*
This bit position indicates whether or not indirect addressing is to be performed. Indirect
addressing is performed (one level only) if this
Instruction Format
11
bit position contains a 1, and is not performed
if this bit position contains a 0.
Operation
This 7-bit field contains the code that designates the operation to be performed.
R
This 4-bit field designates any of the 16 registers of the current register block as an operand
source, result destination, or both.
x
This 3-bit field designates anyone of registers
1-7 of the current register block as an index
register. X =0 designates no indexing; hence,
register cannot be used as an index register.
°
Reference
address
This 17-bit field contains the initial virtual address of the instruction operand. Although the
contents of this field is always, in itself, a word
address, the reference address field allows any
word, doubleword, left halfword, or leftmost
byte within a word in memory to be directly
addressed. Halfword and byte operations require additional address bits for halfwords and
bytes that do not begin on a word boundary.
Thus, to address the second halfword of a word,
the X fi~ld of the instruction must designate a
register that contains a 1 in its low-order bit
position. To address bytes 1, 2, or 3 of a word,
the X field of the instruction must designate a
register that contains 01, 10, or 11, respectively, in its two low-order bit positions. See
II Indexing and Index Registers" for a more complete description of the SIGMA 6 indexing
process.
Some SIGMA 6 instructions are ofthe immediate-addressing
type. The format of these instructions provides for an
operand within the instruction word itself, as shown below.
The functions of the Operation and Rfields are identical to
those of the normal instruction format.
°
This bit position is shown coded with a 0 because indirect addressing cannot be used with
this type of instruction. If indirect addressing
is attempted, the computer treats the instruction as a nonexistent instruction.
Operand
This field contains an operand that is 20 bits in
Iength, with negative numbers represented in
two's-complement form.
There are several methods by which an instruction word
may specify the source of an operand or the destination of
a result. These methods are explained below.
IMMEDIATE OPERAND
The operation code of an i'mmediate operand instruction
spec i fi es that an operand is to be found in the operand
field (bit positions 12-31) of the instruction word itself,
12
Instructi on Format
and not in a general register or core memory location. The
operand field of this type of instruction cannot be modified
by indexing. The following SIGMA 6. instructions are of
the immediate operand type:
Instruc ti on Name
Mnemonic
load Immediate
LI
29
load Conditions and Floating
Control Immediate
LCFI
32
Add Immediate
AI
36
Mul tipl y Immediate
MI
38
CI
41
Compare Immediate
Page
The byte string instructions are similar to those of the
. immediate operand type in that they cannot be modified
by indexing. However, the operand field of these instructions contains a byte address displacement (or a byte
address) that is a virtual address subject to modification by
the memory map. If an immediate or byte string instruction
is indirectl y addressed, it is treated as a nonexistent instruction by the computer.
MEMORY REFERENCE ADDRESSES
°
Core memory locations through 15 are not accessible to
the programm~r because memory addresses through 15 are
reserved as register designators for "register-to-register"
operations. Thus, an instruction can treat any register of
the current register block as if it were a location in core
memory. Furthermore, the register block can be used to
hold an instruction (or a series of up to 16 instructions) for
execution just as jf the instruction (or instructions) were in
core memory. The only restriction upon the use of the
register block for instruction storage is:
°
If an instruction accessed from a general register uses
the R field of the instruction word to designate the
next higher-numbered register and execution of the
instruction would alter the contents of the register so
designated, the contents of that register should not be
used as the next instruction in sequence because the
operation of the instruction in the affected register
would be unpredictable.
In the maximum core memory configuration (131,072 words),
memory addresses II wrap around" with address (general
register 0) being the next consecutive memory address after
X I1FFFFI(131,071). Core memory location 16 follows general register 15 as the next location in ascending sequence.
°
Direct Reference Address. If neither indirect addressing
nor indexing is called for by the instruction, the reference
address field of the instruction is a direct reference address.
Indirect Reference Address. If indirect addressing is called
forbythe instruction (a 1 in bit position 0 of the instruction
word), the reference address field is used to access a word
location that contains the direct reference address in bit
positions 15-31. Tile direct reference address then replaces the indirect reference address. Indirect addressing
is limited to one level; only the reference address field of
the indirect word is significant.
Index Reference Address. If indexing is called for by the
instruction (a nonzero value in bit positions 12-14 of the
instruction), the direct reference address is modified by
addition of the displacement value in the general register
(index) called for by the instruction (after scaling the displacement according to the instruction type). This final
reference address value (after indirect addressing, indexing, or both) is defined as the effective address of the
instruction. If indirect addressing and indexing are both
called for in an instruction, the index displacement is not
used to modi fy the indi rect reference address, but is used
to modify the direct reference obtained from the loca~
tion pointed to by the indirect reference address. ThiS
method of indexing after indirect addressing is called
postindexing.
Register Address. If any instruction produces a virtual address that is a memory reference (i. e., a direct, indirect
or indexed reference address) in the range 0 through 15,
the CPU does not attempt to read from or write into core
memory. Instead,the 4 low-order bits of the reference
address are used as a general register address, and the genera I register (of the current register block) corresponding to
this address is used as the operand location or result destination. Thus, the instruction can use any register in the
current register blockasthe source of an operand, thelocation ofa direct address, or the destination of a result. Such
usage is referred to as a IIregister-to-register ll operation.
Actual Address. An actual address is the address value
actually used by the CPU to access core memory. If the
computer is not operating with the memory map, all virtual
addresses above 15 automatically become actual addresses.
However, if the computer is operating in the memory map
mode, all virtual addresses above 15 are transformed (usually
into alternate addresses in a different memory page) by the
memory map, and these then become actual addresses. Virtual addresses below 16 are never transformed by the memory map and thus always refer to a general register for
a register-to-register operation.
Effective Address. The effective address is defined as the
final virtual address computed for an instruction. The
effective address is usually used as the virtual address of
an operand location or result destination. However, some
instructions do not use the effective address as a location
reference; instead, the effective address is used to control
the operation of the instruction (as in a shift instruction),
to designate the address of an input/output device (as in
an input/output instruction), or to designate a specific
element of the system (as in a READ DIRECT or WRITE
DIRECT instruction).
Effective Location. An effective location is defined to be
the actual location(in core memory or in the current register block) that is to receive the result of a memoryreferencing instruction, and is referred to by means of an effective address. Because an effective address can be either
an actual address or a virtual address, this definition of an
effective location assumes, where applicable, the transformation of vi rtual addresses into ac tual address.
Effective Operand. An effective operand is defined to be
the contents of an actual location (in core memory or in
the current register block) that is to be used as an operand
by a memory-referencing instruction, and is referred to by
means of an effective address. This definition of an effective operand also presupposes the transformation of virtual address into actual addresses.
ADDRESS MODI FICA nON
Indirect Addressing. The 7-bit operation code field of the
SIGMA 6 instruction word format provides for up to 128 instruction operation codes, nearl y all of which can use i ndirect addressing (the exceptions, already mentioned, are the
immediate and byte string instructions). The indirect addressing operation is limited to one level, as called for by
the indirect address bit (bit position 0) of the instruction
word. Indirect addressing does not proceed to further levels,
regardless of the contents of the word location pointed to by
the reference address field of the instruction. Indirect addressing occurs before indexing; that is, the 17-bit reference
address field of the instruction is used to obtain a word, and
the 17 low-order bits of the word thus obtained effectively
replace the initial reference address field; then, indexing
is carried out according to the operation code of the
instruction.
Indexing aAd Index Registers. The X field of the normal
instruction format permits anyone of registers 1 through 7
in the current register block to be designated as an index
register. The contents of this r~gister are then treated as
a displacement value.
Figure 4 shows how the indexing operation takes place. As
the instruction is brought from memory, it is loaded into a
34-bit instruction register that initially contains OIS in the
two low-order bi t posi ti ons (32 and 33). The di splacement val ue
from the index register is then aligned with the instruction
register (as an integer) according to the addressing type of
the instruction. That is; if it is a byte operation, the displacement is lined up so that its low-order bit is aligned
with the least significant bit of the 34-bit instruction register. The displacement is shifted one bit to the left of this
position for a halfword operation, two bits to the left for a
word operation, and three bits to the left for a doubleword
operation. An addition process then takes place to develop
a 19-bit address, which is referred to as the effective address of the instruction. High-order bits of the 32-bit displacement field are ignored in the development of th is
effective address (i. e., the 15 high-order bits are ignored
for word operations, the 25 high-order bits are ignored for
shift operations, and the 16 high-order bits are ignored for
doubleword operations). However, the displacement value
can cause the effective address to be less than the initial
reference address within the instruction if the displacement
value contains a sufficient number of high-order lis (i. e. ,
if the displacement is a negative integer in twols complement form).
The effective address of an instruction is always a 19-bit byte
address value; however, this va lue is automati cally ad justed
Instruction Format
13
Instruction in memory:
Instruction in instruction register:
Byte operation indexing alignment:
Halfword operation indexing alignment:
Word operation indexing alignment:
Shift operation indexing alignment:
Doubleword operation
indexing alignment:
Effective virtual address:
Figure 4.
Index Displacement Alignment
to the SIGMA 6 information boundary conventions. Thus,
for halfword operations, the low-order bit of the effective
halfword address is 0; for word operations, the two low-order
bits of the effective word address are OIS; and for doubleword
operations, the 3 low-order bits of the effective doubleword
address are 0 1 s.
If no indexing is used with a byte operation, the effective
byte is the first byte (bit positions 0-7) of a word location;
if no indexing is used with a halfword operation, the effective halfword is the first halfword (bit positions 0-15) of a
word location. A doubleword operation always involves a
word at an even-numbered word address and the word at the
next sequential (odd-numbered) word address. If an oddnumbered word location is specified for a doubleword operation, the low-order bit of the effective address field (bit
position 31) is automatically forced to O. Thus, an oddnumbered word address (referring to the middle of a doubleword) designates the same doubleword as an even-numbered
word address, when used for a doubleword operation.
the memory map and the memory write locks. The memory map provides for dynamic relocatabi lity of programs
and for access protection through inhibitions imposed on
slave mode programs. The memory write locks provide memory write protection for both master and slave mode programs.
MEMORY MAP AND ACCESS PROTECTION
The memory map can be represented as a series of 256 a-bit
registers, each of which contains an a-bit actual memory
page address code for a specific 512-word page of virtual
addresses, and a series of 256 2-bit registers, each of which
contains a 2-bit access control code for a specific 512-word
page of virtual addresses. (The access control codes are applicable only to programs operating in the slave mode with
the memory map. )
The memory page address codes are assigned to pages of virtual addresses as follows:
I
I
Memory page X Memory page K
MEMORY ADDRESS CONTROL
With a SIGMA 6 computer,' two methods are avai lable for
control Ii ng the use of core memory by a program; they are
14
Memory Address Control
Vi rtua I addresses
X'lO'_X'lFF '
(virtual page 0)
I~ ~ I
Memory page N
Virtual addresses Virtual addresses
X'200'-X ' 3FF'
Xil FEOO'-X'l FFFF'
(virtual page l)
(virtual page 255)
I
The access control codes are assigned as follows:
I I I IHI I I
AC
AC
AC
AC
AC
·Virtual addressts +Vi r tua I ~ddresses
1
I
I
X'lFEOOI-XllFFFF'
X 600 ' - X 7FF 1
Vi rtua I addresses
(virtual page 255)
XI4001-X I5FF'
Virtual addresses
Virtual addresses
XI2001-X I3FF'
XllFCOOI-XllFDFF'
Vi rtua I addresses
XllOI-XllFF'
(virtual page 0)
1
The memory page addresses and access control codes can
be changed only by the privileged instruction MOVE
TO MEMORY CONTROL (see "Control Instructions").
When the CPU is operating in the mapping mode, all memory references used by the program (including instruction addresses) whether direct, indirect, or indexed, are referred to
as virtual addresses. Virtual addresses in the range 0 through
15 are not used to address core memorYi instead, the 4 loworder bits of the virtual address comprise a general register
address. However, if an instruction produces a virtual address greater than 15, the 8 h~gh-order bits of the virtual
address are used to obtain the appropriate memory page address and access control codes. For example, if the 8 highorder bits of the virtual address are 0000 0000, the first page
address code and the first access control code are used; if
the 8 high-order bits of the virtual address are 0000 0001,
the second page address and access control codes are used;
and so on, through the 256th page address and control codes.
Thus, each 512-word page of virtual addresses is associated
wi th its own memory page address and access control codes.
When the memory map is accessed, the CPU performs a test
to determine whether or not there are any inhibitions on using
the virtual address by a slave program. (If the CPU is in the
master mode, this test is not performed.) The 2-bit access
control code is interpreted as follows:
AC Function
00
The slave program can write into, read from, or access
instructions from this page of virtual addresses.
01
The slave program cannot write into, but can read from
or access instructions from this page of virtual addresses.
10
The slave program cannot write into or access instructions from, but can read from this page of virtual addresses.
11
The slave program is denied any access to this page of
virtual addresses.
If the instruction being executed by the slave program fails
this test, the instruction execution is aborted and the computer traps to location X 140 ', the "nonallowed operation"
trap (see II Trap System").
If the instruction being executed by the slave program passes
this test (or the CPU is in the master mode), the page address
bits in the accessed byte of the memory map replace the 8
high-order bits of the virtual address, to produce the actua I
address of the core memory location to be used by the instruction.
If the page address bits in the accessed byte of the memory
map are all O'S, and when combined with 9 low-order bits
of the virtual address, an actual address is produced that
corresponds to a word address in the range 0 throug h 15,
the corresponding general register in the current register
block is not accessed. In this one particular instance, a
word address in the range 0 through 15 corresponds to actual
core memory locations rather than general registers.
Figure 5 illustrates the address modification and mapping
process for an indirectly addressed, indexed, halfword
operation. As the figure shows, word address 1 is the
contents of the reference address field in the instruction
stored in memory. The instruction is brought into the instruction register, and word address 1 (assumed to be greater
than 15) is converted from a virtual address to an actuol address by the memory map. The 17 low-order bi ts of the core
memory location pointed to by word address I, labeled word
address 2, then replaces word address 1 in the instruction register. The index register designated in the X field of the instruction is then aligned for incrementing at the halfwordaddress level, the final virtual (effective) address is formed,
and the effective address (assumed to be greater than 15) is
also transformed, through the memory map. The final 19bit core l1)emory address, which automatically contains a
low-order 0, is then used to access the halfword to be used
as an operand for the instruction.
MEMORY WRITE LOCKS
The access control bits in the memory map provide access
protection, through inhibitions imposed on slave programs.
However, this protection is only available when the memory
map is in effect, and is only operative with respect to slave
programs. A memory protection feature, independent of the
memory map, is provided by a lock and key technique. A
2-bit write-protect lock (WL) is provided for each 512word page of actual core memory addresses. The writeprotect locks consist of 256 2-bit write locks, each assigned to a 512-word page of actual addresses as follows:
I I I I I
WL
WL
WL
WL
•
WL
I~ ~ WL
I
I I
WL
+.
Actua I addresses
Actual addresses
X I600 1-X'7FF'
X'I FEOOI-XIIFFFF'
Actual addresses
(memory page 255)
XI4001-X I5FF'
Actual addresses
Actual addresses
XI2001-X I3FF'
XIIFCOOI-XIIFDFF'
Actual addresses
0-XI1FF'
(memory page 0)
1
I
The write-protect locks can be changed on Iy by the execution of the privileged instruction MOVE TO MEMORY CONTROL (see Control Instructions).
Memory Address Control
15
Instruction in memory:
Instruction in instruction register:
The 8 high -order bi ts of the reference address are
replaced with page address Z from memory map:
Actual address of memory location
that contains the direct address:
Di rect address in memory:
Indirect addressing replaces reference
address wi th di rect address:
II I I
Halfword operation indexing alignment:
II II
Effective virtual address:
The 8 high-order bits of the effective address are
replaced with page address N from memory map:
Final memory address, which is the actual address of
halfword location containing the effective halfword:
Figure 5.
Generation of Actual Memory Addresses
The write-key (a 2-bit field in the arithmetic and control
unit) works in conjunction with the lock storage to determine whether or not the program (whether slave or master)
can write into a specific page of core memory locations.
The keys and locks control access for wri ti ng, accordi ng to
the following rules:
A lock value of 00 means that the corresponding memory page is "unlocked"; write access to that page is
permitted independent of the key value.
A key value of 00 is a "skeleton ll key that wi II open
any locki thus, write access to any memory page is
permitted independent of its lock value.
A lock value other than 00 for a memory page permits
write access to that page only if the key value is
identical to the lock value.
16
Memory Address Control
Thus, a program can write into a given memory page if
the lock value is 00, if the key value is 00, or if the key
value matches the lock value.
Note that the memory access protection feature is provided with the memory map and operates on virtual addresses, whereas the memory write proctection feature
operates on actual memory addresses. Thus, if the access protection feature is invoked (that is, the CPU is
in the slave mode and is using the memory map), the access
protection codes are examined at the time the virtual address is converted into an actual address. Then, the locks
and keys are examined to determine whether or not the
program (master or slave) is a lIowed to alter the content<
of the core memory location corresponding to the final
actual address. If an instruction attempts to write into
a write-protected memory page, the computer aborts
the instruction, and traps to location X'40', which is
the "nonallowed operation" trap (see Trap System).
Designation
the generation of zero results, and the normalization of the results of floating-point additions and
subtractions, respectively. (The floating-point
mode controls are described in Chapter 3, "Floating-point Instructions".) Any program (slave or
master) can change the state of the current floatingpoint mode controls by executing either the instruction LCFI or the instruction LCF; any program can
store the current state of the current floatingpoint mode controls by executing the instruction
STCF.
PROGRAM STATUS DOUBLEWORD
The critical control conditions of the SIGMA 6 CPU can be
defined by 64 bits of information. These 64 bits are
collectively referred to as the current program statusdoubleword (PSD). The current PSD can be considered as a 64bit internal CPU register, although it actually exists as a
collection of separate registers and flip-flops. When stored
in memory, the PSD is always in the following format:
Designation
CC
MS
Master/slave mode control. The computer is in
the master mode when this bit is a 0; it is in the
slave mode when this bit is a 1. The master/slave
mode control cannot di rectly be changed by a slave
program; however, a master mode program can change
the control by executing either the instruction LOAD
PROGRAM STATUS DOUBLEWORD (LPSD) or the instruction EXCHANGE PROGRAM STATUS DOUBLEWORD (XPSD). These two privi leged instructions
are described in Chapter 3, "Control Instructions".
MM
Memory map control. The memory map is in effect when this bit is a 1; it is not in effect
when this bit is O. The memory map control
cannot be changed by a slave program. A mas'ter mode program can change the memory map
control by executing either the instruction LPSD
or the instruction XPSD.
DM
Decimal mask. The decimal arithmetic trap (see
"Trap System") is in effect when this bit is a 1;
the trap is not in effect when this bit is a O. The
conditions that can cause a decimal arithmetic
trap are described in Chapter 3, "Decimal Instructions". The decimal trap mask cannot be
changed by a slave program; a master mode program can change the mask by executi ng either the
instruction LPSD or the instruction XPSD.
AM
Arithmetic mask. The fixed-point arithmetic overflow trap is in effect when this bit is a 1; the trap
is not in effect when this bit is a O. The instructions that can cause fixed-point overflow are
described in the section "Trap System". The arithmetic trap mask cannot be changed by a slave program;
a master mode program can change the mask by executing either the instruction LPSD or the instruction
XPSD.
IA
Instruction address. This 17-bit field contains the
virtual address of the next instruction to be executed.
WK
Write key. This field contains the 2-bit key used
in conjunction with the memory protection feature. A slave program cannot change the current write key; a master mode program can change
the write key by executing either the instruction
LPSD or the instruction XPSD.
Functi on
Condition code. T~is generalized 4-bit code indicates the nature of the results of an instruction.
The significance of the condition code bits depends
on the particular instruction iust executed. After
an instruction is executed, the instructions BRANCH
ON CONDITIONS SET (BCS) and BRANCH ON
CONDITIONS RESET (BCR) can be.used, singly
or in combination, to test for a particular condition code setting (these instructionsaredescribed
in Chapter 3, "Execute/Branch Instructions").
In some operations, only a portion of the condition
code is involved; thus, the term CC 1 refers to the
first bit of the condition code, CC2 to the second
bit, CC3 to the third bit, and CC4 to the fourth
bit. Any program (slave or master mode) can change
the current value of the condition code by executing
either the instruction LOAD CONDITIONS AND
FLOATING CONTROL IMMEDIATE (LCFI) or the
instruction LOAD CONDITIONS AND FLOATING CONTROL (LCF); any program can store
the current condition code by executing STORE
CONDITIONS AND FLOATING CONTROL
(STCF). These instructions are described in
Chapter 3, "Load/Store Instructions".
FS
Floating significance mode control
FZ
Floating zero mode control
FN
Floating normal ize mode control
The three floating-point mode bits (FS, FZ, and
FN) control t~e operation of the computer with
respect to floating-point significance checking,
Function
Program Status Doub Ieword
17
il
Designation
Function
CI
Counter interrupt group inhibit.
II
Input/output interrupt group inhibit.
EI
External interrupt group inhibit.
The three inhibit bits (CI, II, and EI) determine
whether an interrupt can occur. The functions of
the interrupt inhibits are described in the section
"Interrupt System". A slave program cannot change
the state of the interrupt inhibits; a master mode
program can change the interrupt inhibits by executing LPSD, X PSD, or the instruction WRITE DIRECT (WD). The WD instruction is described in
Chapter 3, "Control Instructions ".
Register pointer. This 5-bit field selects one of
the 32 possible blocks of general-purpose registers
as the current register block. A slave program
cannot change the register pointer; a master mode
program can change the register pointer by executing LPSD, XPSD, or the instruction LOAD REGISTER POINTER (LRP). The LRP instruction is described in Chapter 3, "Control Instructions".
INTERRUPT SYSTEM
The SIGMA 6 priority interrupt system is an improved version of the system used successfully in XDS 900/9300 series
computers. Up to 237 external and internal interrupt levels
are normally available, each with a unique location (see
Table 2) assigned in core memory, each with a unique priority, and (except for the Power on and Power off interrupt
levels) each capabl e of being sel ectively armed and/or
enabled by the CPU. Also, any interrupt level can be
"triggered II by the CPU (suppl ied with a signal at the same
physical point where the signal from the external source
would enter the interrupt level). The triggering of an interrupt permits the te~,ting of special systems programs before
the special systems equipment is actually attached to the
computer, and also permits an interrupt-servicing routine to
defer a portion of the processing associated with an interrupt level by processing the urgent portion of an interruptservicing routine, triggering a lower-priority level (for a
routine that handles the less-urgent part), then clearing the
high-priority interrupt level so that other interrupts may be
processed before the deferred interrupt.
SIGMA6interruptleveisarearranged in groups that are connected in a predetermined priority chain by groups of levels.
The priority of each level within a group is fixed; the first
level has the highest priority and the last level has the lowest. The user has the option of ordering a machine with a
priority chain starting with the override group and connecting all remaining groups in any sequence. This allows
the user to establish external interrupts above, between, or
below the counter and input/output groups of internal interrupts. Figure 6 illustrates this with a configuration that
c typical user might establish; where (after the override
group) the counter group of internal interrupts is given
18
Interrupt System
the second-highest priori ty, followed by the first group of external interrupts, then the input/output group of internal i nterrupts, and finally all succeeding groups of external interrupts.
1st Priority
Override
Interrupts
4
2nd Priority
---
Counter
Interrupts
3rd Priority
Externa I Interrupts Group 2
4th Priority
~
I nput/Output
Interrupts
4
5th Priority
Externa I Interrupts Group 3
Figure 6.
r.
Typical Interrupt Priority Chain
INTERNAL INTERRUPTS
The three groups of internal interrupts include standard
interrupts that are normally supplied with a SIGMA 6
system, as well as power fail-safe and the additional
counter interrupts.
OVERRIDE GROUP (Locations X'50' to X'56')
This group of seven interrupt levels always has the highest priority in a SIGMA 6 system. The power fail-safe
feature inc Iudes the Power on and Power off interrupt
levels. A system can have two or four count-pulse interrupt levels that are triggered by pulses from clock sources.
Counter 4 has a constant frequency of 500 Hz; counters 1,
2, and 3 can be individually set to any of five manually
switchable frequencies - the commercial line frequency,
500 Hz, 2 kHz, 8 kHz, and a user-supplied external signal -:- that may be different for each counter. (All counter
frequenci es are synchronous except for the line frequency
and the signal supplied by the user.) Each of the countpulse interrupt locations must contain one of the modify and
test instructions (MTB, MTH, or MTW). Counter 4 uses the
mapped location if map is currently invoked in the PSD.
The results of any other instruction are unpredictable when
the instruction is executed as the result of a count-pulse
interrupt level advancing to the active state. When the
modification (of the effective byte, halfword, or word)
causes a zero result, the appropriate counter-equafs-zero
interrupt (see "Counter-Equals-Zero Group") is triggered.
The override group also includes a memory parity interrupt
level that is triggered whenever a memory parity error is
reported to the CPU.
Table 2.
Location
Dec. Hex.
WRITE DIRECT
Register bitt
SIGMA 6 Interrupt Locations
Function
Availabi lity
Power on ttt
Power offttt
Counter 1 count pulse
Counter 2 count pulse
Counter 3 count pu Ise
Counter 4 count pulse
Memory Pari ty
Reserved for future use
80
81
82
83
84
85
86
87
50
51
52
53
54
55
56
57
none
88
89
90
91
58
59
5A
5B
22
23
24
25
Counter
Counter
Counter
Counter
1 zero
2 zero
3 zero
4 zero
optional
(as a set)
92
93
94
95
5C
5D
5E
5F
26
27
Input/Output
Control Panel
Reserved for future use
Reserved for future use
standard
96
60
16
16
17
18
19
20
111
6F
31
112
70
16
127
7F
optional
(as a set)
120
standard
X'O'
CI
standard
II
External Group 2
X'2'
External Group 3
X'3'
EI ,
16
12F
31
304
130
16
13F
none
31
303
319
WRITE DIRECT
Group code tt
none
standard
optional
288
PSD
Inhibit
External Group 14
X'E'
External Group 15
X'F'
31
t When the privileged instruction WRITE DIRECT is used in the interrupt control mode to operate on interrupt levels, the
interrupt levels are sel ected by specific bit positions in register R. The numbers in this column indicate the bit position
in register R that corresponds to the various interrupt levels.
tt The numbers in this column indicate the group codes (for use with WRITE DIRECT) of the various interrupt levels.
tttThese interrupts can not be disarmed, disabled, nor inhibited.
COUNTER-EQUALS-ZERO GROUP
(Locations X'58' to X'SB')
Each interrupt level in the counter-equals-zero group (called
a counter-equals-zero interrupt) is associated with a countpulse interrupt in the override group. When the execution of
a modify and test instruction in the count-pulse interrupt 10cation causes a zero result in the effective byte, halfword, or
word location, the corresponding counter-equals-zero interrupt is tri ggered. The counter-equa Is-zero interrupts can be
inhibited or permitted asa group. If bit position 37 (CI) of the
current program status doubleword contains a 0, the counterequals-zero interrupts are allowed to interrupt the program being executed. However, if the CI bit is a 1, the counterequals-zero interrupts are notal lowed to interruptthe program.
I
INPUT/OUTPUT GROUP (Locations X'SC' and X'5D')
This interrupt group includes two standard interrupts: the I/O
interrupt and the control panel interrupt. The I/O interrupt
Interrupt System
19
level accepts interrupt signals from the standard I/o
system. The I/o interrupt location is assumed to contain
an EXCHANGE PROGRAM STATUS DOUBLEWORD (XPSD)
instruction that transfers program control to a routine for
servicing all I/O interrupts. The I/O routine then contains
an ACKNOWLEDGE I/o INTERRUPT (AIO) instruction that
identifies the source and reason for the interrupt.
The control panel interrupt level is connected to the INTERRUPT buttons on the processor control panel. The control
panel interrupt level can thus be triggered by the computer
operator, allowing him to initiate a specific routine.
The interrupts in the input/output group can be inhibited or
permitted by means of bit position 38 (II) of the program
status doubleword. If II is a 0, the interrupts in the I/O
group are allowed to interrupt the program being executed.
However, if the II bit is a 1, the interrupts are inhibited
from interrupting the program.
POWER FAIL-SAFE FEATURE
The two power fail-safe interrupt levels, which cannot be
disabled, disarmed, or inhibited, are used to enter routines
that save and restore volatile information (e. g., registers,
interrupt environment, etc.) in case of primary powerfailure.
When primary voltage drops below safe limits, the power off
interrupt is triggered. Typically, a power off routine stores
volati Ie information in main memory to faci litate recovery,
halts all I/O operations, and ends in a waiting state. When
primary power returns to safe limits, the power on interrupt
is triggered. Typically, a power on routine restores information from main memory and prepares to resume processing.
(Note: When power is restored, software timeouts for I/O
operations may occur.) Because the power on interrupt has
a hi gher priority than the power off interrupt (see Table 2),
a power failure cannot interrupt a power on routine before
the system is restored to a predi ctab Ie state (registers
restored, etc.). Since main frame power supplies maintain
voltages for five milliseconds after detecting an imminent
power failure, the total time of the power on and power off
routines must be less than five mi Iliseconds.
External
Input
Trigger
Input
:
~
Active, waiting, or
d;sarmed stale
I
A SIGMA 6 system can contain up fl.' 14 groups of optional
interrupt levels, with 161evels in each group. As shown in
Figure 6, the groups can be connected in any priority sequence.
All external interrupts can be inhibited or permitted by means
of bit position 39 (EI) of the program status doubleword. If
EI is a 0, external interrupts are allowed to interrupt the
program; however, if EI is a 1, all external interrupts are
inhibited from interrupting the program.
STATES OF AN INTERRUPT LEVEL
A SIGMA 6 interrupt level is mechanized by means of three
flip-flops. Two of the flip-flops are used to define any of
four mutually exclusive states: disarmed, armed, waiting,
and active. The third flip-flop is used as a level-enable.
The various states and the conditionscausing them to change
state (see Figure 7) are described in the following paragraphs.
DISARMED
When an interrupt level is in the disarmed state, no signal
to that interrupt level is admitted; that is, no record is retained of the existence of the signal, nor is any program
interrupt caused by it at any time.
ARMED
When an interrupt level is in the armed state, it can accept
and remember an interrupt signal. The receipt of such a signal advances the interrupt level to the waiting state.
WAITING
When an interrupt level in the armed state receives an interrupt signal, it advances to the waiting state, and remains
r---------------------I
~:
----0
Armed state
1-.
EXTERNAL INTERRUPTS
:
I
I
---------------------~
O;sabled stale
Remember
interr~pt
Enabled state
WAITING STATE
Group n
inhibit = 1
on
off
Group n
inhibit = 0
--------------------------------------------- I
Note: The armed, disarmed, waiting, and active states are controlled by two flip-flops and the enabled/disabled I states are controlled by
the level-enable flip-flop.
Figure 7.
20
Interrupt System
Operational States of an Interrupt Level
in the waiting state unti I it is allowed to advance to the
active state. If the level-enable flip-·flop is off, the interrupt level can undergo all state changes except that of
moving from the waiting to the active state. Furthermore,
if this flip-flop is off, the interrupt level is completely removed from the chain that determines the priority of access
to the CPU. Thus, an interrupt level in the waiting state
with its level-enable in the off condition does not prevent
an enabled, waiting interrupt of lower priority from moving
to the acti ve state.
interrupt-servicing routine cannot be interrupted by a
lower-priority interrupt as long as it remains in the active
state. Normally, the interrupt servicing routine clears its
interrupt and transfers program contro I back to the poi nt of
interrupt by means of an LPSD instruction with the same
effective address as the XPSD instruction in the interrupt
location.
CONTROL OF THE INTERRUPT SYSTEM
When an interrupt level is in the waiting state, the following conditions must all exist simultaneously before the level
advances to the active state.
1.
The level must be enabled (i. e., its level-enable flipflop must be set to 1).
2.
The CPU must be at an interruptible point in the execution of a program.
3.
The group inhibit (CI, II, or EI, if applicable) must be
a
4.
O.
No higher-priority interrupt level is in the active state
or is in the waiting sto4-e and totally enabled (i. e. ,
enabled and not inhibited).
ACTIVE
When an interrupt meets all of the conditions necessary to
permit it to move from the waiting state to the active state,
it is permitted to do so by being acknowledged by the computer, which then executes the contents of the assigned interrupt location as the next instruction. The instruction
address portion of the program status doubleword remains
unchanged until the instruction in the interrupt location is
executed.
The instruction in the interrupt location must be one of the
following: XPSD, MTB, MTH, or MTW. If the execution of
any other instruction in an interrupt location attempted as
the result of an interrupt level advancing to the active
state, the results of the instruction are unpredictable.
The use of the privi leged instruction XPSD in an interrupt
location permits an interrupt-servicing routine to save the
entire current machine environment and establish a new
environment. If working registers are needed by the
routine and additiona I register blocks are avai lable, the
contents of the current register block can be saved automatically with no time loss. This is accomplished by changing the value of the register pointer, which results in the
assignment of a new block of 16 registers to the routine.
An interrupt level remains in the active state unti I it is
cleared (removed from the active state) by the execution
of the LPSD instruction or the WD instruction. An interruptservicing routine can itself be interrupted whenever a
higher-priority interrupt level meets all of the conditions for becoming active; and then continued after the
higher-priority interrupt is cleared. However, an
The SIGMA 6 system has two points of interrupt control.
One point of interrupt control is at the individual interrupt
level. The WD instruction can be used to individually arm,
disarm, enable, disable, or trigger any interrupt level except for the power fail-safe interrupts (which are always
armed, always enabled, and cannot be triggered).
The second point of interrupt control is achieved by means
of the interrupt inhibits (CI, II, and EI) in the program status
doubleword. If an interrupt inhibit is set to 1, all interrupt
levels in the corresponding group are effectively disabled;
i. e., no interrupt in the group may advance from the waiting state to the active state and the group is removed from
the interrupt recognition priority chain. Thus, a waiting,
enabled interrupt level (in a group that is not inhibited) is
not prevented from interrupting the program by a higherpriority,' waiting, enabled interrupt level in a group that is
inhibited. However, if an interrupt group is inhibited whi Ie
a level in that group is in the active state, no lower-priority
interrupt level may advance to the active state.
nME OF INTERRUPT OCCURRENCES
The SIGMA 6 CPU permits an interrupt to occur during the
following time intervals (related to the execution cycle of
an instruction) providing the control panel COMPUTE switch
is in the RUN position and no "halt" condition exists:
1.
Between instructions: An interrupt is permitted between
the completion of any instruction and the initiation of
the next instruction.
2.
Between the initiation of an instruction and memory or
register modification: For some instructions, an interrupt
is permitted after an instruction has been in process and
up to the point in time when a memory location or a general
register is modified. If an interrupt occurs during this time
interval, the instruction is aborted, the instruction address
portion ofthe program status doubl eword remai ns poi nti ng
tothe interrupted instruction, and the instruction in the interrupt location is executed. After the interrupt-servi c i ng
routine has been processed, program control is returned to
the interrupted instruction, and the interrupted instruction
is then reinitialized. Most instru.:tions have such a short
execution time that they are not abortable by an interrupt;
thus, an interrupt normal I y occurs onl y before or after an
instruction execution.
Interrupt System
21
3.
When a modify and test instruction is executed in a countpulse interrupt location, all of the above conditions appl~
in addition to the following: If the resultant value in the
effective location is zero, the corresponding counterequals-zero interrupt is triggered.
Between instruction iterations: An interrupt is also
permitted to occur during the execution of the following multiple-operand instructions:
Move Byte String (MBS)
Compare Byte String (CBS)
Translate Byte String (TBS)
Translate and Test Byte String (TTBS)
Edit Byte String (EBS)
Decimal Multiply (OM)
Decimal Divide (00)
Move tt::) Memory Control (MMC)
TRAP SYSTEM
When a condition that is to result in an interrupt is
sensed, a signal is sent to an interrupt level. If that
level is "armed" it advances to the waiting state. When
all of the conditions for its acknowledgment have been
achieved, the interrupt level eventually advances to the
active state, where it finally causes the computer to take
an instruction from a specific location in memory. The computer may execute many instructions between the time that
the interrupt requesting condition is sensed and the time that
the actual interrupt acknowledgment occurs. However, detecting any of the conditions listed in Table 3 results in a
trap (the immediate execution of the instruction in a unique
location in memory).
The control and intermediate results of these instructions reside in registers and memory; thus, the instruction can be
interrupted between the completion of one iteration (operand execution cycle) and the point in time (during the next
iteration) when a memory location or register is modified.
If an interrupt occurs during this time, the current iteration
is aborted and the instruction address portion of the program
status doubleword remains pointing to the interrupted instruction. After the interrupt-servicing routine is completed, the
instruction continues from the point at which it was interrupted and does not begin anew.
SINGLE-INSTRUCTION INTERRUPTS
A s ingle- instruction interrupt is a situation where an interrupt
level is activated, the current program is interrupted, the singleinstruction in the interrupt location is executed, the interrupt
level is automatically cleared and armed, and the interrupted
program continues without be ing disturbed or delayed (except
for the time required for the singl e-instruction).
If any of the following instructions is executed in any interrupt location, then that interrupt automaticall y becomes
a single-instruction interrupt.
Instruction Name
Mnemonic
Modify and Test Byte
MTB
Modify and Test Halfword
MTH
Modify and Test Word
MTW
The modify and test instruction modifies the effective byte,
halfword, or word (as described in the section "Fixed-point
Arithmetic Instructions") but the current condition code remains unchanged (even if overflow occurs). The effective
address ofa modify and test instruction in an interrupt location (except counter 4) is always treated as an actual
address, regardless of whether or not the memory map is
currently being used. Counter 4 uses the mapped location if
map is currently invoked in the PSD. The execution of a
modify and test instruction in an interrupt location, including
mapped and unmapped counter 4, is independent of the
memory access protection codes and the write-protection
locks; thus, a memory protection violation trap cannot
occur (a nonexistent memory address wi II cause an unpredictable operation). Also, the fixed-point overflow trap
cannot occur as the result of overflow caused by executing
MTH or MTW in an interrupt location.
The execution of a modify and test instruction in an interrupt
location automatically clears and arms the corresponding interrupt level, allowing the interrupted program to continue.
22
Trap System
When a trap condition occurs, the CPU sets the trap state. Depending on the type of trap, the instruction currently being executed by the CPU mayor may not be carried to completion. In
any event, the instruction is terminated with a trap sequence.
~ In this sequ~nce, the instruction address (IA) portion of the
program status doubleword (PSD), which has already been
incremented by 1, is decremented by 1 and then the instruc
tion in the location associated wi th the trap is executed.
An interrupt acknowledgment cannot occur unti I the execution of the instruction in the trap location is completed. The
instruction in the trap focation must be an XPSO instruction;
if the execution of any other instruction in a trap location
is attempted as the resul t of a trap activation, the results of
the instruction are unpredictable. The detai led operation of
XPSD is described in Chapter 3, II Control Instructions".
I
The XPSO instruction in a trap location is accessed without
using the memory map, regardless of whether or not the memory map is in effect when the trap condition occurs. Also,
no memory protection violation or privileged instruction
violation can occur as a result of either accessing or executing an XPSO instruction in a trap location. Table 3
summarizes the description of the trap system.
NONALLOWED OPERATION TRAP
The occurrence of one of the nona II owed operations always
causes the computer to abort the instruction being executed (at the time that the nona II owed operation is detected)
and to immediately execute the instruction in trap location
X'40'.
NONEXISTENT INSTRUCTION
Any instruction that is neither standard nor optional on
SIGMA 6 is defined as nonexistent (this incl udes immediate
addressin"g instructions that are indirectly addressed). If
execution of a nonexistent instruction is attempted, the
computer traps to location X ' 40 ' at the time the instruction
is decoded. The operation of the XPSD instruction in trap
Table 3.
Location
Dec. Hex.
64
40
Summary of SIGMA 6 Trap System
Function
PSD
Mask Bit
Nonallowed operation
none
Time of Occurrence
Spec ial Action During XPSD
1. Nonexistent instruction
Instruction decoding
Set CCl after new CC is
loaded from memory. If bit
9 of XPSD is 1, add 8 to
the new instruction address
value loaded from memory.'
2. Nonexistent memory
address
Prior to memory access
Set CC2 after new CC is
loaded from memory. If bit
9 of XPSD is 1, add 4 to
the new instruction address
value loaded from memory.
3. Privileged instruction
in slave mode
Instruction decoding
Set CC3 after new CC is
loaded from memory. If bit
9 of XPSD is 1, add 2 to
the new instruction address
value loaded from memory.
4. Memory protection
Prior to memory access
Set CC4 after new CC is loaded
from memory. If bit 9 of XPSD is
1, add 1 to the new instruction
address value loaded from memory.
65
41
Unimplemented instruction
none
Instruction decoding
none
66
42
Push-down stac k lim it
reached
TW, TSt
At the time of stack limit
detection
none
67
43
Fixed-point arithmetic
overflow
AM
For al I instructions except DW none
and D H, trap occurs after completion of instruction. For DW
and D H, instruction is aborted
with memory, regi sters, CC 1,
CC3, CC4 unchanged.
68
44
Floating-point fault
1. Characteristic overflow
none
none
2. Divide by zero
none
At time of fault detection; the
condition code is set to indicate the reason for the trap
3. Significance check
FS, FZ,
FN
69
45
Decimal arithmetic fault
DM
At time of fault detection; the
condition code is set to indicate the reason for the trap
none
70
46
Watchdog timer runout
none
At time of runout
none
72
48
CALL 1
none
Instruction decoding
73
49
CALL 2
none
Instruction decoding
74
4A
CALL 3
none
Instruction decoding
75
4B
CALL 4
none
Instruction decoding
76
4C
The R fi el d of the CA LL i nstruction is ORed into new CC settings loaded from memory. If
bit 9 of XPSD is 1, the R field
of the CALL instruction is added to the new instruction address value loaded from memory.
Reserved
79
~
4F
_ _~~_ _~_ _ _ _ _ _~~_ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ L ' . _ _ _ • _ _ _ _ _•_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
tThe TW and TS mask bits are contained within the stack pointer doubleword for each push-down stack.
Trap System
23
location X'40' (with respect to the condition code and
instruction add~ess portions of the PSD) is as follows:
1.
Store the current PSO. The condition code stored is
that which existed at the end of the instruction executed immediately prior to the nonexistent instruction.
2.
Load the new PSD. The current PSD is replaced by the
contents of the doubleword location following the doubleword location in which the current PSD was stored.
3.
Modify the new PSD:
a.
Set CCl to 1 (CC2, CC3, and CC4 remain set at
the values loaded from memory).
b.
Ifbitposition90fXPSDcontainsal, the instruction
address loaded from memory is incremented by S. If
bit position 9 of XPSD contains a 0, the instruction
address remai ns at the value loaded from memory.
NONEXISTENT MEMORY ADDRESS
Any attempt to access a nonex istent memory address causes a
trap to location X '40' at the time of the request for memory
service. A nonexistent memory address condition is detected
by memory on the basis of the actual address presented to it.
If the CPU is currently using the memory map, the virtual address wi II already have been modified by the memory map to
generate an actual (but nonexistent) address. The operation
of XPSD in trap location X'40' is as follows:
1.
Store the current PSD.
2.
Load the new PSD.
3.
Modify the new PSD:
a.
Set CC2 to 1 (CC1, CC3, and CC4 remain set at
the values loaded from memory).
b.
Ifbitposition90fXPSDcontainsa 1, the instruction
address loaded from memory is incremented by4. If
bit position 9 of XPSD contains a 0, the instruction
address remains at the value loaded from memory.
The operation codes, OC, aD, 2C, 20, and their indirectly
addressed forms, SC, SO, AC, AD, are both nonexistent
and privileged. If one of these operation codes is used
I
while the CPU is in the slave state, both CCl and CC3 wi~
be set to )'s after the new PSD has been loaded, and if bit
position 9 of XPSD contains a 1, the instruction address
loaded from memory is incremented by 10.
MEMORY PROTECTION VIOLATION
A memory protection violation can occur either because of
a memory map access control bit violation (by a slave program using the memory map) or because of a memory
write lock violation (by either a slave or a master mode
program). When either memory protection violation occurs,
the CPU aborts execution of the current instruction (without changing protected memory) and traps to location X'40'.
The operation of the XPS D in trap location X'40' is as
follows:
1.
Store the current PSD,
2.
Load the current PSO.
3.
Modify the new PSD:
a.
Set CC4 to 1 (CC 1, CC2, and CC3 remain at the
values loaded from memory.
b.
If bit position 9 of XPSD contains a 1, the instrucl
ti on address loaded from memory is incremented
by 1. If bit position 9 of XPSD contains a a, the
instruction address remains at the value loaded
from memory.
An attempt to access a memory location that is both protected and nonexistent causes both CC2 and CC4 to be set
to lis after the new PSD has been loaded, and if bit position 9 of XPSD contains a 1, the instruction address loaded
from memory is incremented by 5.
PRIVILEGED INSTRUCTION IN SLAVE MODE
An attempt to execute a privileged instruction while the
CPU is in the slave mode causes a trap to location X1 40 ' at
the time of instruction decoding. The operation of XPSD
in trap location X 140 ' is as follows:
UNIMPLEMENTED INSTRUCTION TRAP
There is one SIGMA 6 optional instruction group.
the floating-point option.
This is
The floating-point option includes the following instructions:
1.
Store the current PSD.
2.
Load the new PSD.
3.
Modify the new PSD.
a.
b.
24
Set CC3 to 1 (CC1, CC2, and CC4 remain at the
val ues loaded from memory).
If bi t position 9 of XPSD contains a 1, the instruction address loaded from memory is incremented
by 2. If bit position 9 of XPSD contains a 0, the
instruction address remains at the value loaded
from memory.
Trap System
Instruction Name
Mnemonic
Operation Code
Floating Add Short
FAS
X ' 3D'
Floating Add Long
FAL
X'ID'
FI oati ng Subtract Short
FSS
X ' 3C'
Floating Subtract Long
FSL
X'lC'
Floating Multiply Short
FMS
X'3F'
Floating Multiply Long
FML
X'lF'
Floating Divide Short
FDS
X'3E'
Floating Divide Long
FDL
X'lE'
If an attempt is made to execute an instruction (directly or
indirectly addressed) in this group when the floating-point
option is not implemented, the computer traps to location
X'41'. The operation of the XPSD in trap location X'41'
is as follows:
1.
2.
Store the current PSD. The condition code stored is
that which existed at the end of the instruction immediately prior to the unimplemented instruction.
Load the new PSD. The condition code and the instruction address portions of the PSD remain at the
values loaded from memory.
PUSH-DOWN STACK LIMIT TRAP
Push-down stack overflow or underflow can occur during
execution of any of the following instructions:
Instruction Name
Mnemonic
Push Word
PSW
Pull Word
PLW
Push Multiple
PSM
Pull Multiple
PLM
Modify Stack Pointer
MSP
During the execution of any stack-manipulating instruction
(see Push-down Instructions) the stack is either pushed
(words added to stack) or pulled (words removed from
stack). In either case, the space count and word count
fields of the stack pointer doubleword are tested prior
to moving any words. If execution of the instruction
would cause the space count to become less than 0 or
greater than 2 15 _1, the instruction is aborted with memory and registers unchanged; then, if bit 32 (TS) of the
stack pointer doubleword is 0, the CPU traps to location X'42'. If execution of the instruction would cause
the word count to become less than 0 or greater than
2 15 -1, the i nstructi on is aborted wi th memory and regi sters
unchanged; then, if bit 48 (TW) of the stack pointer
doubleword is a 0, the CPU traps to location X'42'. If
trapping does occur, the condition code remains at the
value it had immediately prior to the instruction that caused
the trap. When trapping is inhibited, either CCl or CC3
is set to 1 (or both CCI and CC3 are set to l's) to indicate
the reason for aborti ng the i nstructi on. The stack poi nter
doubleword, memory, and registers are modified only if the
instruction is successfully executed. The execution of
XPSD in trap location X'42' is as follows:
1.
2.
Store the current PSD. The condition code stored is
that which existed immediately prior to the execution
of the aborted push-down instruction.
Load the new PSD.' The condition code and instruction
address portions of the PSD remain at the values loaded
from memory.
fiXED-POINT OVERflOW TRAP
Fixed-point overflow can occur for any of the following
instructions:
Instruction Name
Mnemonic
Load Complement Word
Load Absolute Word
Load Complement Doubleword
Load Absol ute Doubleword
Add Immedi ate
Add Ha Ifword
Add Word
Add Doubleword
Subtract Halfword
Subtract Word
Subtract Doublword
Divide Halfword
Divide Word
Add Word to Memory
Modify and Test Halfword
Modify and Test Word
LCW
LAW
LCD
LAD
AI
AH
AW
AD
SH
SW
SD
DH
DW
AWM
MTH
MTW
Except for the instructions DIVIDE HALFWORD (DH) and
DIVIDE WORD (DW), the instruction execution is allowed
to proceed to completion, CC2 is set to 1 and CC3 and
CC4 represent the actual result (0, -, or +) after overflow.
If the fixed-point arithmetic trap mask (bit 11 of PSD) is a
1, the CPU traps to location X'43' instead of executing the
next instruction in sequence.
For OW and DH, the instructi,on execution is aborted without changing any registers and CC2 is set to 1; but CCl,
CC3, and CC4 remain unchanged from their values at the
end of the instruction immediately prior to the OW or DH.
If the fixed-point arithmetic trap mask is a 1, the CPU traps
to location X'43' instead of executing the next instruction
in sequence.
1.
Store the current PSD. If the instruction causing the
trap was an instruction other than DW or DH, the
stored condition code t is interpreted as follows:
CCl tt CC2 CC3
o
CC4 Meaning
o
o
resu It after overff ow is
negative
o
o
result after overflow is zero
result after overflow is
positive
no carry from bit position 0
carry from bit position 0
t A hyphen (-) indicates that the condition code bit is not
affected by the condition given under the "Meaning"
heading.
ttCCl remains unchanged for the instructions LCW, LAW,
LCD, and LAD.
Trap System
25
FS = 1 and FN = 0), or a postnormalization shift of m
more than two hexadecimal places (with FS = 1 and
FN = 0), the stored condition code is interpreted as
follows:
If the instruction causing the trap was DW or DH, the
stored condition code is interpreted as fol lows:
CCI
CC2 CC3
CC4 Meaning
CCI
overflow
2.
Load the new PSD. The condition code and instruction address portions of the PSD remain at the value
loaded from memory.
FLOATING-POINT ARITHMETIC FAULT TRAP
Floating-point fault detection is performed after the operation called for by the instruction code is performed, but before any results are actually loaded into the general registers;
thus, the floating-point operation that causes an arithmetic
fault is notcarried to completion (in the sense that the original contents of the general registers remain unchanged).
Instead, the computer traps to location X ' 44 1 with the current condition code indicating the reason for the trap. A
characteristic overflow or an attempt to divide by zero always results in a trap condition; a significance check or a
characteristic underflow result in a trap condition only if
the floating-point mode controls (FS, FZ, and FN) in the
program status doubleword are set to the appropriate state.
If a floating-point instruction causes a trap, the execution
of XPSD in trap location X' 44 1 is as follows:
1.
Store the current PS D. If division is attempted with a
zero divisor or if characteristic overflow occurs, the
stored condition code is interpreted as follows:
CC2 CC3 CC4 Meaning
0
0
0
0
0
2.
0
zero result of addition or
subtraction
more than 2 postnormal izing
shifts, negative result
0
more than 2 postnormalizing
shifts, positive result
Load the new PSD. The condition code and instruction
address portions of the PSD remain at the values loaded
from memory.
DECIMAL ARITHMETIC FAULT TRAP
When either of two decimal fault conditions occur (see
Decimal Instructions), the normal sequencing of instruction
execution is halted, CCI and CC2 are set according to the
reason for the fault condition, and CC3, CC4, memory, and
the decimal accumulator remain unchanged by the instruction. If the decimal arithmetic trap mask (bit position 10
of PSD) is a 0, the instruction execution sequence continues
with the next instruction (in sequence) at the time of fault
detection; however, if the decimal arithmetic trap mask bit
is a 1, the computer traps to location X'45 1 at the time of
fault detection.
The execution of XPSD in trap location X'45 1 is as follows:
CCl
CC2 CC3 CC4 Meaning
0
0
0
0
0
divide by zero
CC2 CC3 CC4 Meaning
o
characteristic overflow, positive result
If none of the above condi tions occurs, but characteristic underflow occurs with the floating zero (FZ) mode
bit set to 1, the stored condition code is interpreted
as follows:
Store the current PSD. The stored condition code is
interpreted as fo II ows :
CCI
characteristic overflow, negative result
0
0
1.
all digits legal and overflow
o
2.
illegal digit detected
Load the new PSD. The condition code and instruction
"address portions of the PSD remain at the values loaded
from memory.
WATCHDOG TIMER RUNOUT TRAP
CCI
CC2 CC3 CC4 Meaning
characteristic underflow, negative result
0
0
characteristic underflow, positive result
If none of the above conditions occurs, but an addition
or subtraction results in either a zero resul t (with
26
Trap System
The instruction watchdog timer insures that the CPU must
periodically reach interruptible points of operation in the
execution of instructions. An interruptible point is a time
during the execution of a program when an interrupt request
(if present) would be acknowledged. Interruptible points
occur at the end of every instruction and during the execution of some instructions (such as the byte string group). The
watchdog timer measures elapsed time from the last interruptible point. If the maximum allowable time has been
reached before the next time that an interrupt could be
recognized, the current instruction is aborted and the
watchdog timer runout trap is activated. Except for a nonexistent address used with READ DIRECT (RD) or WRITE
DIRECT (WD) instructions, programs trapped by the watchdog timer cannojo (in general) be continued. Execution of
XPSD in trap location X'46' is as follows:
1.
Store the current PSD. The stored condition code is,
in general, meaningless.
1.
Store the current PS D. The stored condi ti on code is
that which existed at the end of the instruction immediately prior to the call instruction.
2.
Load the new PSD.
3.
Modify the new PSD.
a.
The R field of the cal I instruction is logically
ORed with the condition code value loaded from
memory, and the result is loaded into the condition code.
b.
CAll INSTRUCTION TRAPS
If bit 9 of XPSD contains a 1, the R field of the
call instruction is added to the instruction address
loaded from memory.
The four call instructions (CAll, CAL2, CAL3, and CAL4)
cause the computer to trap to location X'48' (for CAll)
If bit 9 of XPSD containa a 0, the instruction address remains at the value loaded from memory.
2.
Load the new PSD. The instruction address portion of
the PSD remains at the values loaded from memory;
however, the resulting condition code is, generally,
meaningless.
X'49' (for CAL2), X'4A' (for CAL3), or X'4B' (for CAL4l.
Execution of XPSD in the trap location is as follows:
Trap System
27
3. INSTRUCTION REPERTOIRE
This section describes all SIGMA 6 instructions, grouped
in the following functional classes:
d.
Doubleword index alignment: the reference addre~
field of the instruction {plus the displacement valuel
can be used to address any doubleword in core memoryor in the current block of general registers. The
addressed doubleword is automatically located
within doubleword storage boundaries.
e.
Immediate operand: the instruction word contains
an operand value used as part of the instruction
execution. If indirect addressing is attempted
with this type of instruction (i.e., bit 0 of the
instruction word is a 1), the instruction is treated
as a nonexistent instruction, in which case the
computer unconditionally aborts execution of the
instruction (at the time of operation code decoding)
a nd traps to Iocat i on X 140 1, the nona /I owed
operation" trap. Indexing does not apply to this
type of instruction.
Page
28
34
36
41
43
1. Load and Store
2. Analyze and Interpret
3. Fixed-Point Arithmetic
4. Comparison
5. Logical
6. Shift
7. Conversion
8. Floating-Point Arithmetic (optional)
9. Decimal
10. Byte String
11. Push Down
12. Execute and Branch
13. Call
14. Control
15. Input/Output
44
46
47
51
57
64
69
71
72
79
II
f.
SIGMA 6 instructions are described in the following format:
MNEMONIC CD INSTRUCTION NAME
®
(Addressing type @, Optional 0
Privi leged @, Interrupt Action®)
Description
Affected
4.
If the instruction is not in the standard SIGMA 6 instruction set, it is labeled "optional". If execution of
an optional instruction is attempted on a computer in
which the instruction is not implemented, the computer
unconditionally aborts execution of the instruction (at
the time of operation code decoding) and traps to location X ' 41 1 , which is the "unimplemented instruction
trap".
5.
If the instruction is not executable while the computer
is in the slave mode, it is labeled "privileged". If
execution of a privileged instruction is attempted whi Ie
the computer is in the slave mode, the computer unconditionally aborts execution of the instruction (at
the time of operation code decoding) and traps to 10.cation X'40'.
6.
If the instruction can be successfully resumed after its
execution sequence has been interrupted by an interrupt
acknowledgment, the instruction is labeled "continue
after interrupt". Otherwise, the instruction is either
completed or the instruction is aborted and then restarted after the interrupt is cleared. In the case of
the "continue after interrupt" instructions, certain general registers contain intermediate results or control
information that allows the instruction to continue
properly. In the case of aborted instructions, all affected registers are restored to the values they contained immediately before the aborted instruction was
begun.
®
0
Trap @)
Symbol ic notation ®
Condition Code Settings@
Trap Action@
Example@
1.
MNEMONIC is the code used by the SIGMA 6 assemblers to produce the instruction IS basic operation code.
2.
INSTRUCTION NAME is the instruction's descriptive
title.
3.
The instruction's addressing type is one of the following:
28
a.
Byte index alignment: the reference address field
of the instruction (plus the displacement value) can
be used to address a byte in core memory or in the
current block of general registers.
b.
Halfword index alignment: the reference address
field of the instruction (plus the displacement value)
can be used to address a halfword in core memory
or in the current block of general registers.
c.
Word index alignment: the reference address field
of the instruction (plus the displacement value) can
be used to address any word in core memory or in
the current b lock of general registers.
Instruction Repertoire
Immediate displacement: the instruction word contains an address displacement used as part of the
instruction execution. If indirect addressing is attempted wi th th i s type of instruct i on, the computer
treats the instruction as a nonexistent instruction,
in wh i ch case the computer uncond i ti ona /I y aborts
execution of the instruction (at the time of operation code decoding) and traps to location X'40'.
Inde'xing does not apply to this type of instruction.
7.
Instruction format;
a.
Indirect addressing -If bit position 0 of the instruction format contains an asterisk (*), the instruction can uti Iize indirect addressing; however,
if bit position 0 of the instruction format contains
a 0, the instruction is of the immediate addressing
type, which is treated as a nonexistent instruction
if indirect addressing is attempted (resulting in a
trap to location XI401).
b.
Operation code - The operation code field (bit
positions 1-7) of the instruction is shown in hexadecimal notation.
c.
R field - If the register address field (bit positions
8-11) of the instruction format contains the character "R", the instruction can specify any register
in the current block of general registers as an operand source, result destination, or both; otherwise,
the function of this field is determined by the instruction.
d.
e.
f.
X field - If the index register address field (bit
positions 12-14) of the instruction format contains
the character II X" , the instruction can specify
indexing with anyone of registers 1 through 7
in the current block of general registers; otherwise, the function of this field is determined by
the instruction.
Reference address field - Normally, the reference
address field (bit positions 15-31) of the instruct ion format is used as the in Hia I address va lue for
an instruction operand. For instructions of the immediate addressing type, the effective address of
the instruction is not used to access an operand;
instead, the effective address itself is used as an
operand. In these cases, the function of the effective address is represented in the lower half of
the reference address field in the instruction format diagram.
Value field - In some fixed-point arithmetic instructions, bit positions 12-31 of the instruction
format contain the word "value". This field is
treated as a 20-bit integer, with negative integers represented in twols complement form.
g.
Displacement field - In the byte string instructions,
bit positions 12-31 of the instruction format contain the word "displacement. II In the execution
of the instruction, this field is used to modify the
source address of an operand, the destination address of a result, or both.
h.
Ignored fields - In the instruction format diagrams,
any area that is shaded represents a field or bit position that is ignored by the computer (i. e., the content of the shaded field or bit has no effect on instruction execution) but should be coded with O's so as to
preclude conflict with possible modifications.
In any format diagram of a general register or memory word modified by an instruction, a shaded area
represents a field' whose content is indeterminate
after execution of the instruction.
8. The description of the instruction defines the operations
performed by the computer in response to the instruction
configuration depicted by the instruction format diagram.
Any instruction configuration that causes an unpredictable result is so specified in the description.
9. All programmable registers and storage areas that can be
affected by the instruction are Iisted (symbol ically) after
the word II Affected". The instruction address portion of
the program status doubleword is considered to be affected only if a branch condition can occur as a resul t
of the instruction execution, since the instruction address is updated (incremented by 1) as part of every instruction execution.
10. All trap conditions that may be invoked by the execution of the instruction are Iisted after the word liT rap".
SIGMA 6 trap locations are summarized in the section
liT rap System".
11. The symbol ic notation presents the instruction operation
as a seri es of general i zed symboli c statements. The symbolic terms used in the notation are defined in Table 4.
12. Condition Code settings are given for each instruction
that affects the condition code. A 0 or a 1 under any
of columns 1, 2, 3, or 4 indicates that the instruction
causes a 0 or 1 to be placed in Cel, CC2, CC3, or
CC4, respectivel y, for the reasons given. If a hyphen
(-) appears in columns 1, 2, 3, or 4, that portion of the
condition code is not affected by the reason given for
the condition code bit{s) containing a 0 or 1. For example, the following condition code settings are given
for a comparison instruction:
2
3
4
Result of comparison
0
0
equal
0
register operand is arithmetically
less than effective operand
0
0
register operand is arithmetically
greater than effective operand
the logical product (AND) of the
two operands is zero
the logical product of the two
operands is nonzero
CC1 is unchanged by the instruction. CC2 indicates
whether or not the two operands have 11 sin corres. ponding bit positions, regardless of their arithmetic
relationship. Ce3 and Ce4 are set according to the
arithmetic relationship of the two operands, regardless of whether or not the two operands have lis in
corresponding bit positions. For example, if the
register operand is arithmetically less than the effective operand and the two operands both have l's in at
least one corresponding bit position, the condition
code setting for the comparison instruction is:
2
3
4
o
The .above statements about the condition code are valid
only if no trap occurs before the successful completion of
Instruction Repertoire
29
the instruction execution cycle. If a trap does occur
during the instruction execution, the condition code
is normally reset to the value it contained before the
instruction was started, and then the appropriate trap
location is activated.
13. Actions taken by the computer for those trap conditions that may be invoked by the execution of
the instruction are described. The description
includes the criteria for the trap condition, any
controlling trap mask or inhibit bits, and the action
taken by the computer. In order to avoid unnecessary
repetition, the two trap conditions that apply to all
Table 4.
Meaning
()
Contents of.
AM
Fixed-point arithmetic trap mask - bit 11 of
the program status doubleword. If this bit is
a 1, the computer traps to location X ' 43 1 after
executing an instruction that causes fixedpoint overflow; if this bit is a 0, the computer
does not trap to location X'43 1•
Term
Instruction register - the internal CPU register
used to hold instructions obtained from memory
whi Ie they are being decoded.
Ru 1
x
General register address value - the 4-bit contents of bit positions 8-11 (the R field) of an instruction word, also expressed symbolically as
(1)8-11' In the instruction descriptions, register R is the general register (of the current
register block) that corresponds to the R field
add ress va Iue •
Odd register address value - register Ru 1 is the
general register pointed to by the value obtained
by logically ORing 0001 into the address value
for register R. Thus, if the R field of an instruction contains an even value, Ru 1 = R + 1, and if
the R field contains an odd value, Ru 1 = R.
EVA
30
EBL
Effective byte location - the byte location
pointed to by the effective virtual address of
an instruction for a byte operation.
EB
Effective byte - the 8-bit contents of the
effective byte location, or (EBL).
EHL
Effective halfword location - the halfword location pointed to by the effective virtual addressof an instruction fora halfword operation.
EH
Effective halfword - the 16-bit contents of
the effective halfword location, or (EHL).
EWL
Effective word location - the word location
pointed to by the effective virtual address of
an instruction for a word operation.
EW
Effective word - the 32-bit contents of the
effective word location, or (EWL).
EDL
Effective doubleword location - the doubleword location pointed to by the effective
virtual address of an instruction for a doubleword operation. If an odd-numbered word location is specified for a doubleword operation,
the low-order bit of the effective address field
(bit position 31) is automatically forced to 0.
Thus, an odd-numbered word address (referring
to the middle of a doubleword) designates the
same doubleword as an even-numbered word
address, when used for a doubleword operation.
ED
Effective doubleword - the 64-bit contents of
the effective doubleword location, or (EDL).
CC
Condition code - a 4-bit value (whose bit
positions are labeled CC 1, CC2, CC3, and
CC4) that is establ ished as part of the execution of most SIGMA 6 instructions.
FN
Floating normal ize mode control - bit 7 of the
program status doubleword. If this bit is a 0,
the results of floating-point additions and
subtractions are to be normalized; if this bit
is a 1, the results Clre not normalized.
t-
Reference address - the contents of bit positions
15-31 of an instruction word. This 17-bit field
is capable of directly addressing any general
register in the current register block (by using
a value in the range 0-15) or any word in core
memory in the address range 16 through 131,07l.
This address value is the initial address value for
any subsequent address computations, memory
mapping, or both computation and mapping.
Effective vIrtual address - the virtual address
value obtained as a result of indirect addressing
and/or indexing.
This address value is
Instruction Repertoire
Meaning
independent of the program1s actual location
in core memory, and is the final address value
before memory mapping is performed.
Index register address value - the 3-bit contents
of bit positions 12-14 (the X field) of an instruction word. If X = for an instruction, no indexing is performed. If X a for an instruction, indexing is performed (after indirect addressing if
indirect addressing is called for) with general
register X in the current register block.
°
RA
14. Some instruction descriptions provide one or more
examples to illustrate the results of the instruction.
These examples are intended onl y to show how the
instructions operate, and not to demonstrate their
full capability. Within the examples, hexadecimal
notation is used to represent the contents of general
registers and storage locations {condition code settings are shown in binary notation. The character "x"
is used to indicate irrelevant or ignored information.
Glossary of Symbolic Terms
Term
R
instructions (i. e., nonallowed operations and
watchdog timer runout) are not described for each
instruction.
I
Table 4.
Glossary of Symbolic Terms (cont.)
Term
Meaning
FS
Floating significance mode control - bit 5 of
the program status doubleword. If this bit is
a 1, the computer traps to location X'44'
when more than two hexadecimal places of
postnormalization shifting are required for a
floating-point addition or subtraction; if this
bit is 0, no significance checking is performed.
FZ
Term
Floating zero mode control - bit 6 of the program status doubleword. If this bit is a 1, the
computer traps to location X'44' when either
characteristic underflow or a zero result occurs
for a floating-point multiplication or division;
if this bit is a 0, characteristic underflow and
zero resu I ts are treated as normal conditions.
IA
Instruction address - the 17-bit value that defines the virtual address of an instruction
immediately prior to the time that the instruction is executed.
X'n'
Hexadecimal qual ifier - a hexadecimal value
{n} is an unsigned string of hexadecimal digits
(O through 9 and A through F) surrounded by
LOAD/STORE INSTRUCTIONS
The following load/store instructions are implemented in
SI GMA 6 computers:
Instruction Name
Load Immediate
Load Byte
Load Ha Ifword
Load Word
Load Doubleword
Load Complement Halfword
Load Absolute Halfword
Load Complement Word
Load Absolute Word
Load Complement Doubleword
Load Absolute Doubleword
Load Selective
Load Multiple
Load Conditions and Floating Control
Immediate
Load Conditions and Floating Control
Exchange Word
Store Byte
Store Halfword
Store Word
Store Doubleword
Store Selecti ve
Store Multiple
Store Conditions and Floating Controls
Mnemonic
LI
LB
LH
LW
LD
LCH
Meaning
single quotation marks and preceded by the
qualifier "X" (for example, 7B0
is writ16
ten X'7BO'.
AND (Iogi cal product, where 0 nO;::: 0,
1 = 0, 1 n 0 = 0, and 1 n 1 = 1).
n
on
OR (logical inclusive OR, where 0 u 0 = 0,
1 u 0 ;::: 1, and 1 u 1 ;::: 1).
u
o u 1 = 1,
EOR {logical exclusive OR, where 0 @ 0
1 ;::: 1, 1@ 0;::: 1, and 1 @ 1 ;::: O}.
o@
Sign extension - some SIGMA 6 instructions
operate on two operands of different lengths;
the two operands are made equal in length by
extending the sign of the shorter operand by
the required number of bit positions. For positive operands, the result of sign extension is
high-order O's prefixed to the operand; for
negative operands, high-order l's are prefi xed
to the operand. This sign extension process is
performed after the operand is accessed from
memory and before the operation called for by
the instruction code is performed.
SE
Load instructions load the information indicated into one of
the genera~ registers in the current register block. Load
instructions do not affect core memory storage; however,
nearly all load instructions provide a condition code setting
that indicates the following inf9rmation about the contents
of the affected general register(s) after the instruction is
successfully completed:
Condition code settings:
2
3
4
------
o
LAH
LS
LM
STCF
SIGMA 6 load and store ihstructions operate with information fields of byte, halfword, word, and daubleword lengths.
o
Result
zero - the result in the.affected register{s)
is all O's.
negative - register R contains a 1 in bit
position O.
o
LAD
XW
STB
STH
STW
STD
STS
STM
0
o
LCW
LAW
LCD
LCFI
LCF
= 0,
positive - register R contains a 0 in bit
position 0, and at least one 1 appears in
the remainder of the affected register(s}
(or appeared during execution of the current instruction.)
no fixed-point overflow - the result in
the affected register{s} is arithmetica II y
correct.
fixed-point overflow - the result in the
affected register(s) is arithmetically
incorrect.
Store instructions affect only that portion of memory storage
that corresponds to the length of the information field specified by the operation code of the instruction; thus, register
byte<; are stored in memory byte locations, register halfwords
in memory halfword locations, register words in memory
Load/Store Instructions
31
word locations, and register doublewords in memory doubleword locations. Store instructions do not affect the contents
of the general register specified by the R field of the instruction, unless the same register is also specified by the effective virtual address of the instruction.
II
o
LOAD IMMEDIATE
(Immediate operand)
Condition code settings:
2
.LW
3
4
Result in R
0
0
1
0
1
0
zero
negative
positive
LOAD WORD
(Word index al ignment)
1
LOAD IMMEDIATE extends the sign of the value field (bit
position 12 of the instruction ward) 12 bit positions to the
left and then loods the 32-bit result into register R.
Affected: (R), CC3, CC4
(I)12-31SE R
Conditi on code setti ngs:
2
3
4
Result in R
0
0
0
1
0
zero
negative
positive
If LI is indirectly addressed, it is treated as a nonexistent
instruction, in .which case the computer unconditionally
aborts execution of the instruction (at the time of operation code decoding) and traps to location X' 40' with the
contents of register R and the condition code unchanged.
LB
LOAD BYTE
(Byte index alignment)
LOAD BYTE loads the effective byte into bit positions 24-31
of register R and clears bit positions 0-23 of the reg ister to
allOls.
Affected: (R), CC3, CC4
EB R24 - 31 ; 0 RO- 23
LOAD WORD loads the effective word into register R.
Affected: (R),CC3,CC4
EW R
Condition code settings:
2
4
3
o o
o
1
LH
.LD
Affected: (R),CC3,CC4
EHSE
32
R
Load/Store Instructions
o
o
0
1
0
zero
negative
positive
LOAD DOUBLEWORD
(Doubleword index alignment)
If R is an odd value, the result in register R is the 32 highorder bits of the effective doubleword. The condition code
settings are based on the effective doubleword, rather than
the final result in register R (see Example 3, below).
Affected: (R),(Ru 1),CC3,CC4
ED Rul; ED _ O 31
32 63
Condition code settings:
2
zero
nonzero
LOAD HALFWOR D extends the sign of the effective halfword 16 bit positions to the left and then loads the 32-bit
result into register R.
Result in R
LOAD DOUBLEWORD loads the 32 low-order bits of the effective doubleword into register Ru 1 and then loads the 32
high-order bits of the effective douhleword into register R.
Result in R
LOAD HALFWORD
(Halfword index alignment)
4
1
Condition code settings:
2
3
R
3
4
Effective doubleword
o
o
0
1
1
0
zero
negative
positive
Example 1, even R field value:
Before execution
ED
(R)
(Ru 1)
CC
After execution
X 1 0123456789ABCDEF ' X ' 0123456789ABCDEF I
xxxxxxxx
X1 01234567 1
xxxxxxxx
X' 89ABCDEF '
xxx x
xx 10
Example 2, odd R field value:
ED
(R)
CC
X ' 0123456789ABCDEF'
xxxxxxxx
xxxx
X' 0123456789ABCDEF'
X' 01234567 1
xx 10
Condi tion code settings:
Example 3, odd R field value:
X'00000000 I 2345678'
X' 00000000'
X 00000000 12345678'
ED
I
(R)
CC
~
LCH
xxxxxxxx
xxxx
xxlO
LOAD COMPLEMENT HALFWORD
(Halfword index alignment)
2
3
4
Result in R
0
0
0
0
0
0
1
0
1
0
zero
negative
positive
no fixed-point overflow
fixed-point overflow
1
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X '43 ' after execution of LOAD COMPLEMENT WOR D; otherwise, the computer executes the next instruction in sequence.
LOAD COMPLEMENT HALFWORD extends the sign of the
effective halfword 16 bit positions to the left and then loads
the 32-bit two's complement of the result into register R.
(Overflow cannot occur. )
LAW
LOAD ABSOLUTE WORD
(Word index 01 ignment)
Affected: (R),CC3,CC4
~~HSEJ
- R
Condition code settings:
2
3
4
Resu I tin R
o
o
O·
I
0
zero
negative
positive
I
If the effective word is positive, LOAD ABSOLUTE WORD
loads the effective word into register R. If the effective
word is negative, LAW loads the 32-bit two's complement
of the effective word into register R. Fixed-point overflow
occurs if the effective word is -231 (X '80000000 ' ), in which
case the result in register R is _2 31 and CC2 is set to 1;
otherwise, CC2 is reset to O.
LOAD ABSOLUTE HALFWORD
(Halfword index alignment)
LAH
Affected: (R),CC2,CC3,CC4
Trap: Fixed-point overflow
IEWI-· R
Condition code settings:
If the effective halfword is positive, LOAD ABSOLUTE
HALFWORD extends the sign of the effective halfword 16
bit positions to the left and then loads the 32-bit result in
register R. If the effective halfword is negative, LAH extends the sign of the effective halfword 16 bit positions to
the left and then loads the 32-bit two's complement of the
result into register R. (Overflow cannot occur.)
Affected: (R),CC3,CC4
IEH SEI --
R
2
3
4
Result in R
0
0
0
0
zero
nonzero
no fixed-point overflow
fixed-point overflow (sign bit on)
1
0
1
0
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X'43 ' afterexecution of LOAD ABSOLUTE WORD; otherwise, the computer executes the next instruction in sequence.
Condition code settings:
2
3
4
Resu Itin R
o
0
0
zero
nonzero
1
LCW
LCD
LOAD COMPLEMENT WORD
(Word index alignment)
LOAD COMPLEMENT WORD loads the 32-bit two's complement of the effective word into register R. Fixed-point
overflow occurs if the effective word is _2 31 (X 'BOOOOOoo"
in which case the result in register R is -2 31 and CC2 is set
to 1; otherwise, CC2 is reset to O.
Affected: (R),CC2,CC3, CC4
-EW -
R
Trap: Fixed-point overflow.
LOAD COMPLEMENT DOUBLEWORD
(Doubleword index alignment)
LOAD COMPLEMENT DOUBLEWORD forms the 64-bit two's
complement of the effective doubleword, loads the 32 loworder bits of the result into register Ru I, and then loads the
32 high-order bits of the result into register R.
If R is an odd value, the result in register R is the 32 highorder bits of the two's complemented doubleword. The condition code settings are based on the two IS complement of
the effective doubleword, rather than the final result in
register R.
Fixed-point overflow occurs if the effective doubleword is
-263 (X '8000000000000000 '), in which case the result in
Load/Store Instructions
33
registers Rand Rul is -2 63 and CC2 is set to 1; otherwise,
CC2 is reset to O.
registers Rand Ru 1 is -2 63 and CC2 is set to 1; otherwise,
CC2 is reset to O.
Affected: (R), (Ru1 ),CC2,
Trap: Fixed -point overflow
CC3,CC4
[-ED] 32-63 Ru 1; [-ED]O_31 R
Affected: (R),(Ru 1),CC2,
CC3,CC4
IED1 _
Rul; 1ED10_31 32 63
Condition code settings:
Cond i ti on code setti ngs:
2
3
4
Two's complement of effective doubleword
0
0
0
0
1
0
zero
negative
positive
no fixed-point overflow
fixed-point overflow
0
0
1
0
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X'43' after execution of LOAD COMPLEMENT DOUBLEWORD; otherwise,
the computer executes the next instruction in sequence.
ED
(R)
(Ru 1)
CC
After execution
X'0123456789ABCDEF'
xxxxxxxx
xxxxxxxx
xxxx
X '0123456789ABC DEF'
X'FEDCBA98'
X '76543211'
xOOl
Example 2, odd R field value:
ED
(R)
CC
X'0123456789ABCDEF'
xxxxxxxx
xxxx
LAD
LOAD ABSOLUTE DOUBLEWORD
(Doubleword index al ignment)
X'0123456789ABCDEF'
X'FEDCBA98'
xOOl
3
4
Absolute value of effective doubleword
0
0
1
0
0
zero
nonzero
no fixed-point overflow
fixed-point overflow (sign bit on)
0
1
0
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X'43' after execution of LOAD ABSOLUTE DOUBLEWORDi otherwise, the
computer executes the next instruction in sequence.
Example 1, even R field value:
ED
(R)
(Ru 1)
CC
Before execution
After execution
X'0123456789ABCDEF'
xxxxxxxx
xxxxxxxx
xxxx
X'0123456789ABCDEF'
X'01234567'
X'89ABCDEF'
xOl0
Example 2, even R field value:
ED
(R)
(Ru 1)
CC
X'FEDCBA9876543210'
xxxxxxxx
xxxxxxxx
xxx x
X'FEDCBA9876543210'
X'01234567'
X'89ABCDFO'
x010
Example 3, odd R field value:
ED
(R)
CC
LS
If the effective doubleword is positive, LOAD ABSOLUTE
DOUBLEWORD loads the 32 low-order bits of the effective
doubleword into register Ru 1, and then loads the 32 highorder bits of the effective doubleword into register R. If R
is an odd value, the result in register R is the 32 high-order
bits of the effective doubleword. The condition code settings
are based on the effective doubleword, rather than the fina'!
result in register R.
R
2
Example 1, evenR field value:
Before execution
Trap: Fixed-point overflow.
X'0123456789ABCDEF'
xxxxxxxx
xxxx
X '0123456789ABCDEF'
X'01234567'
xOl0
LOAD SELECTIVE
(Word index alignment
Register Ru1 contains a 32-bit mask. If R is an even value,
LOAD SELECTIVE loads the effective word into register R
in those bit positions selected by a 1 in correspondi ng bit
positions of register Ru 1. The contents of register R are not
affected in those bit positions selected by a 0 in corresponding bit positions of register Ru 1.
If the effective doubleword is negative, LAD forms the
64-bit two's complement of the effective doubleword, loads
the 32 low-order bits of the two's complemented doubleword
into register Ru 1, and then loads the 32 high-order bits of the
two's complemented doubleword into register R. If R is an
odd value, the result in register R is the 32 high-order bits
of the two's complemented doubleword. The condition code
settings are based on the two's complement of the effective
doubleword, rather than the final result in register R.
Affected:
Fixed-point overflow occurs if the effective doubleword is
_~3 (X'8000000000000000'), in which case the result in
If R is even, [EWn(RulUu[(R)n(Rul)]-R
If R is odd, EWn(R)-R
34
Load/Store Instructions
If R is an odd value, LS logically ANDs the contents of
register R with the effective word and loads the result into
register R. If corresponding bit positions of register Rand
the effective word both contain l's, a 1 remains in register
Ri otherwise, a 0 is placed in the corresponding bit position
of register R.
(R), CC3, CC4
If the effective virtual address of the LM instruction is in
the range 0 through 15, then the words to be 'oaded are
taken from the general registers rather than from core memory. In this case the results will be unpredictable if any of
the source registers are also used as destination registers.
Condition code settings:
2
3
4
Resul t in R
o
0
zero
o
bit 0 of register R is a
o
bit 0 of register R is a 0 and bit positions
1-31 of register R contain at least one 1
LeFt
LOAD CONDITIONS AND FLOATING
CONTROL IMMEDIATE
(Immediate operand)
Example 1, even R field value:
EW
(Ru 1)
(R)
CC
Before execution
After execution
X' 01234567'
X'FFOOFFOO'
X'01234567'
X' FFOOFFOO'
xxxxxxxx
xxxx
X'01xx45xx'
xx10
Example 2, odd R field value:
Before execution
After execution
EW
(R)
CC
X'89ABCDEF'
X' FOFOFOFO'
X'89ABCDEF'
X' 80AOCOEO'
xxOl
LM
LOAD MULTIPLE
0Nord index alignment)
xxxx
If bit position 10 of the instruction word contains a 1, LOAD
CONDITIONS AND FLOATING CONTROL IMMEDIATE
loads the contents of bit positions 24 through 27 of the instruction word into the condition code; however, if bit 10
is 0, the condition code is not affected.
If bit position 11 of the instruction word contains a 1, LCFI
loads the contents of bit positions 29 through 31 of the instruction word into the floating significance (FS), floating
zero (FZ), and floating normalize (FN) mode control bits,
respectivel y (in the program status doubl eword); however,
if bit 11 is 0, the FS, FZ and FN control bits are not affected. The functions of the floating-point control bits
are described in the section "Floating-point Instructions".
Affected: CC, FS, FZ, FN
If (1)10 = 1, (1)24-27 LOAD MULTIPLE loads a sequential set of words into a sequential set of registers. The set of words to be loaded begi ns wi th the word poi nted to by the effecti ve address of LM,
and the set of registers begins with register R. The set ofregisters is treated modulo 16 (i. e., the next register loaded
after register 15 is register 0 in the current register block).
The number of words to be loaded into the general registers
is determined by the value of the condition code immediately
before the execution of LM. (The desired value of the condition code can be set with LCF or LCFI.) An initial val ue
of 0000 for the condition code causes 16 consecutive words
to be loaded into the register block.
Affected: (R) to (R+CC-l)
(EWL) -R, (EWL+1) - R+l, ... , (EWL +CC-1) -R+CC-l
If the instruction starts loading words from an accessible
region of memory and then crosses into an inaccessible memory region, either the memory protection trap or the nonexistent memory address trap can occur. In either case, the
trap is activated with the condition code unchanged from
the value it contained before the execution of LM. The effecti ve address of the instruction permits the trap routine to
compute how many registers have been loaded. Since it is
permissible to use indirect addressing or indexing through a
general register, or even to execute an instruction located
in a general register,. a trapped LM instruction may have
already overwritten the index, direct address, or the LM
instruction itself, thus destroying any possibility of continuing the program successfully. If such programming must
be done, it is advisable ,that the register containing the direct address, index displacement, or instruction be the last
register loaded by the LM instruction.
CC
If (1)10 =·0, CC is not affected
If (1)11 = 1, (1)29-31 - - FS, FZ, FN
If (1)11 = 0, FS, FZ, and FN n,ot affected
Condition code settings, if (I) 10 = 1:
2
3
4
If LCFI is indirectly addressed, it is treated as a nonexistent instruction, in which case the computer unconditionally aborts execution of instruction (at the time of operation
code decoding) and traps to location X'40' with the condition code unchanged.
LCF
LOAD CONDITIONS AND FLOATING
CONTROL
(Byte index 01 ignment)
If bit position 10 of the instruction word contains a 1, LOAD
CONDITIONS AND FLOATING CONTROL loads bits 0
through 3 of the effective byte into the condition code; however, if bit 10 is 0, the condition code is not affected.
If bit position 11 of the instruction word contains a 1, LCF
loads bits 5 through 7 of the effective byte into the floating
significance (FS), floating zero (FZ), and floating normalize
(FN) mode control bits, respectively; however, if bit 11 is
0, the FS, FZ and FN control bits are not affected. The
Load/Store Instructions
35
functions of the floating-point mode control bits are described in the section "Floating-point Instructions".
STW
STORE WORD
(Word index alignment)
Affected: CC, FS, FZ, FN
If (1)10 = I, EB O_ - - CC
3
If (1)10 = 0, CC not affected
If (1)11
If (1)11
= I,
= 0,
EB _ FS, FZ, FN
5 7
FS, FZ, FN not affected
Condition code setti ngs, if (1)10
2
3
= 1:
STORE WOR D stores the contents of register R into the effective word location.
Affected: (EWl)
(R) EWl
STD
4
STORE DOUBlEWORD
(Doubleword index alignment)
{EB)2
XW
EXCHANGE WORD
(Word index alignment)
EXCHANGE WORD exchanges the contents of register R
with the contents of the effective word location.
Affected: (R),(EWl),CC3,CC4
(R) (EWl)
STORE DOU BlEWORD stores the contents of register R into the
32 high-order bit positions of the effectivedoubleword location and then stores the contents of register Ru 1 into the 32 loworder bit positions of the effective doubleword location.
Affected: (EDl)
(R) EDl _ ; (Ru1) O 31
3
0
0
1
4
0
1
0
Result in R
(R)
(Ru I)
(EDl)
zero
negative
positive
=
Before execution
After execution
X ' 01234567'
X ' 89ABCDEF'
xxxxxxxxxxxxxxxx
X '01234567 1
X'89ABCDEF'
X ' 0123456789ABCDEF'
Example 2, odd R field value:
STORE BYTE
(Byte index alignment)
ST8
_
32 63
Example I, even R field value:
Condition code settings:
2
EDl
(R)
X ' 89ABCDEF'
(EDl) = xxxxxxxxxxxxxxxx
STS
STORE BYTE stores the contents of bit positions 24-31 of
register R into the effective byte location.
X'89ABCDEF'
X '89ABC DEF89ABC DEF'
STORE SELECTIVE
0/Vord index alignment)
Affected: (EBl)
(R)24-31
STH
-
EBl
STORE HAlFWORD
(Halfword index alignment)
STORE HAlFWORD stores the contents of bit positions 16-31
of register R into the effective halfword location. If the information in register R exceeds halfword data limits, CC2 is
set to 1; otherwise, CC2 is reset to O.
EHl
Condition code settings:
2
o
3
4
-
EWl
Example 1, even R field value:
Information in R
(R) 0 _ 16 ~ a II 0' s or all 1 Is
(R)0-16
36
IfR isan odd value, STS logically inclusiveORs the contents
of register R with the effective word and stores the result
into the effective word location. The contents of register
R are not affected.
Affected: (EWl)
If R is even, [(R)n(Ru 1)] u [EWn(~)]
If R is odd, (R) u EW EWl
Affected: (EHl),CC2
(R)16-31 -
Register Ru1 contains a 32-bit mask. If R is an even value,
STORE SELECTIVE stores the contents of register R into the
effective word location in those bit positions sel·ected by a I
in corresponding bit positions of register Ru 1; the effective
word remains unchanged in those bit positions selected by a
o in corresponding bit positions of register Rul.
:I all
load/Store Instructions
O's or all l's
(R)
(Ru 1)
EW
Before execution
After execution
XI 12345678 1
XI FOFOFOFO'
xxxxxxxx
XI 12345678'
XI FOFOFOFO '
X'1x3x5x7x '
Example 2, odd R field value:
Before execution
After executi on
(R)
EW
X'OOFFOOFF '
XI 12345678 1
X'OOFFOOFP
XI 12FF56FP
STM
STORE MULTIPLE
(Word index alignment)
Affected: (EBL)
(PSD)O_7 EBL
ANALYZE/INTERPRET INSTRUCTIONS
ANLZ
o )
STORE MULTIPLE stores the contents of a sequential set of
registers into a sequential set of word locations. The set of
locations begins with the location pointed to by the effective
word address of STM, and the set of registers begins with
register R. The set of registers is treated modulo 16 (i.e.,
the next sequential register after register 15 is register 0).
The number of registers to be stored is determined by the
value of the condition code immediately before execution
of STM. (The condition code can be set to the desired value before execution of STM with LCF or LCFI.) An initial
va lue of 0000 for the condition code causes 16 general registers to be stored.
Affected: (EW L)to (EWL + CC-1)
(R) --EWL, (R+ 1)-EWL+ 1, ... , (R+CC-l)- EWL+CC-l
If the instruction starts stori ng words into an accessible region
of the memory and then crosses into an inaccessible memory
region, either the memory protection trap or the nonexistent
memory address trap can occur. In either case, the trap is
activated with the condition code unchanged from the value
it contained before the execution of STM. The effective
address of the instruction permits the trap routine to compute how many words of memory have been changed. Since
it is permissible to use indirect addressing through one of
the affected locations, or even to execute an instruction located in one of the affected locations, a trapped STM
instruction may have al ready overwritten the direct address,
or the STM instruction itself, thus destroying any possibil ity
of continuing the program successfully. If such programming
must be done, it is advisabl e that the direct address, or the
STM instruction, occupy the last location in which the contents of a register are to be stored by the STM instruction.
If the effective virtual address of the STM instruction is in
the range 0 through 15, then the registers indicated by the
R field of the STM instruction are stored in the general registers rather than in core memory. In this case the resul ts
will be unpredictable if any of the source registers are also
used as destination registers.
STCF
STORE CONDITIO NS AND FLOATING CONTROL
(Byte index alignment)
STORE CONDITIONS AND FLOATING CONTROL stores
the current condition code and the current values of the
floating significance (FS), floating zero (FZ), and floating
normalize (FN) mode cOr:ltrol bits of the program status
doubleword into the effective byte location as follows:
ANALYZE
(Word index alignment)
The ANALYZE instruction treats the effective word as a
SIGMA 6 instruction and calculates the effective virtual
address that would be generated by the instruction if the
instruction were to be executed. ANALYZE produces an
answer to the question, "What effective vi rtual address
would be used by the instruction located at N if it were
executed now?" The ANALYZE instruction determines
the addressing type of the "analyzed" instruction, calculates its effective virtual address (if the instruction is not
an immediate-operand instruction), and loads the effective
virtual address into register R as a displacement value
(the condition code settings for the ANALYZE instruction
indicate the addressing type of the anal yzed instruction).
The nonexistent instruction, the privileged instruction violation, and the unimplemented instruction trap conditions
can never occur during execution of the ANLZ instruction.
However, either the nonexistent memory address condition
or the memory protection violation trap condition (or both)
can occur as a result of any memory access initiated by the
ANLZ instruction. If either of these trap conditions occur,
the instruction address stored by an XPSD in trap location
X ' 40 ' is always the virtual address of the ANLZ instruction.
The detailed operation of ANAL YZE is as follows:
1.
The contents of the locarion pointed to by the effective
virtual address of the ANLZ instruction is obtained. This
effective word is the instruction to be analyzed. From (1
memory-protection viewpoint, the instruction (to be analyzed) is treated as an operand of the ANLZ instruction;
that is, the analyzed instruction may be obtained from
any memory area to which the program has read access.
2a. If the operation code portion of the effective word specifies an immediate-addressing instruction type, the
condition code is set to indicate the addressing type,
and instruction execution proceeds to the next instruc,,"
tion in sequence after ANLZ. The original contents of
register R are not changed when the analyzed instruction is of the immediate-addressing type.
2b. If the operation code portion of the effective word specifies a reference-addressing instruction type, the condition code is set to indicate the addressing type of the
analyzed instruction and the effective address of the
analyzed instruction is computed (using all of the normal
address computation rules). If bit 0 of the effective word
is a 1, the contents of the memory locat;on specified by
bits 15-31 of the effective word are obtained and then
Analyze/Interpret Instructions
37
used as a di rect address. The nonallowed operation
trap (memory protection violation or nonexistent memory
address) can occur as a resu I t of the memory access. Indexingisalwaysperformed{with an index register in the
current register block) if bits 12-14 of the analyzed instruction are nonzero. The effective virtual address of
the analyzed instruction is aligned as an integer displacement val ue and loaded into register R, according to the instruction addressing type, as follows:
Table 5.
X'n l
Byte Addressing:
Halfword Addressing:
Word Addressing:
Doubleword Addressing:
Operation codes and mnemonics for the SIGMA 6 instruction set are shown in Table 5. Circled numbers in the table
indicate the condition code val ue (decimal) available to the
next instruction after ANALYZE when a direct-addressing
operation code in the corresponding addressing type is analyzed.
Affected:
(R), CC
Condition code settings:
2
a
a
a
1
1
1
3
a
a
1
a
a
a
1
4
Instruction addressi ng type
a
1
a
a
1
a
byte
immediate byte
halfword
word
immediate, word
doubleword
direct addressing (EWO = 0)
indirect addressing (EWO = 1)
X'OO'+n
X120'+n
X'40'+n
X'60'+n
00
01
02
03
-
AI
CI
TTBS
TBS
CBS
MBS
LCFI®
LI
-
MI
04
05
06
07
CAll
CAL2
CAL3
CAL4
SF
S
-
08
09
OA
OB
PLW
PSW
PLM
PSM
CVA
LM
STM
OC
OD
OE
OF
LPSD @
XPSD
10
11
12
13
AD
CD
LD
MSP
INTERPRET
(Word index alignment)
-
EOR
OR
LS
AND
BCR
BCS
BAL
INT
WAIT
LRP
SIO
TIO
TDV
HIO
RD
WD
AIO
MMC
AW
CW
lW
MTW
AH
CH
lH
MTH
LCF
CB
LB
MTB
-
-
-
STCF
STD
STH
DH
MH
STB
PACK 0
UNPK
CVS
®
-
-
14
15
16
17
-
-
STW
DW
MW
18
19
1A
1B
SD
CLM
LCD
LAD
SW
CLR
LCW
LAW
IC
ID
1E
IF
FSL
FAL
FDL
FMl
FSS
FAS
FDS
FMS
SH
LCH
LAH
--
-
EXU
®
DS
DA
DD
DM
DSA
DC
DL
DST
loads OIS into bit positions 0-15 of register R (bits 4-15
of the effective word are ignored in this case).
Affected: (R), (Ru 1), CC
O3
EW 4._ 15 -
2
Analyze/Interpret Instructions
0
-
CC
R20 - 31 ; 0 -
RO- 19
Rul _ ; 0 _
16 3I
16 31
Condition code settings:
38
EBS
BDR
BIR
AWM
EW
INTERPRET loads bits 0-3 of the effective word into the
conditi on code, loads bits 4-15 of the effective word
into bit positions 20-31 of register R (and loads a's into
the remai nder of register R), and then loads bits 16-31
of the effective word into bit positions 16-31 of register
Ru 1 (and loads a's into bit positions 0-15 of register Ru 1).
If R is an odd val ue, I NT loads bits 0-3 of the effective
word int0 the condition code, loads bits 16-31 of the effective word into bit positions 16-31 of register R, and
CD -
-
ANLZ
CS
XW
STS
EW _
INT
ANA LYZE Table for SIGMA 6 Operation Codes
3
RuI _
O 15
4
EWO
Example 1, even R field value:
EW
(R)
(Ru 1)
CC
Before execution
After execution
X I12345678 I
xxxxxxxx
xxxxxxxx
xxxx
X I 12345678'
X 100000234'
X'00005678'
0001
2
FIXED-POINT ARITHMETIC INSTRUCTIONS
The following fixed-point arithmetic instructionsare included
as a standard feature of the SIGMA 6 computer:
Instruction Name
Mnemonic
Add Immediate
Add Halfword
Add Word
Add Doubleword
Subtract Halfword
Subtract Word
Subtract Doubl eword
Multiply Immediate
Multiply Halfword
Multiply Word
Divide Hal fword
Divide Word
Add Word to Memory
Modify and Test Byte
Modify and Test Halfword
Modify and Test Word
AI
AH
AW
AD
SH
SW
SO
MI
MH
MW
DH
OW
AWM
MTB
MTH
MTW
The fixed-point arithmetic instruction set performs binary
addition, subtraction, multiplication, and division with
integer operands that may bf; data, addresses, index values,
or counts. One operand may be either in the instruction
word i tsel f or may be in one or two of the current general
registers; the second operand may be either in core memory
or in one or two of the current general reg isters. For most
of these instructions, both operands may be in the same
gen era I reg i ster, thus perm i tti ng the doubl i ng, squari ng, or
clearing the contEmts of a register by using a reference
address value equal to the R field value.
All fixed-point arithmetic instructions provide a condition
code setting that indicates the folJowing information about
the result of the operation called for by the instruction:
3
4
o
Result
no carry - For an add or subtract i nstruction, there was no carry of a I-bit out of
the high-order (sign) bit position of the
result.
carry - For an add or subtract instruction,
there was a l-bit carry out of the sign bit
position of the result. (Subtracting zero
will always produce carry.)
AI
ADD IMMEDIATE
(Immediate operand)
The value field (bit positions 12-31 of the instruction word)
is treated as a 20-bit, two's complement integer. ADD
IMMEDIATE extends the sign of the value field (bit position
12 of the instruction word) 12 bit positions to the left, adds
the resulting 32-bit value to the contents of register R, and
loads the sum into register R.
Affected: (R), CC
Trap: Fixed-point overflow
(R) + (I) 12-31SE - - R
Condition code settings:
2
o
o
3
4
Result in R
o
o
0
1
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
o
If AI is indirectly addressed, it is treated as a nonexistent
Condition code settings:
2
3
4
Resul t
o
0
zero - The result in the specified general
register{s) is all zeros.
o
negative - The instruction has produced a
fixed-point negative result.
o
o
positive - The instruction has produced a
fixed-poi nt posi ti ve resu It.
fixed-point overflow has not occurred
during execution of an add, subtract, or
divide instruction, and the result is
correct.
fixed-point overflow has occurred during
execution of an add, subtract, or di vide
instruction. For addition and subtraction,
the incorrect result is loaded into the
designated register{sL For a divide instruction, the designated register(s), and
CC1, CC3, and CC4 are not affected.
instruction, in which case the computer unconditionally
aborts execution of the instruction {at the time of operation
code decoding) and traps to location X'40' with the contents
of register R and the condition code unchanged.
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X'43' after
loading the sum into register R; otherwise, the computer
executes the next instruction in sequence.
AH
AOD HALFWORD
(Halfword index 01 ignment)
ADD· HALFWORD extends the sign· of the effective hal ~ord
16 bit positions to the left (to form a 32-bit word in which
bit positions 0-15 contain the sign of the effective halfword),
adds the 32-bit result to the contents of register R, and loads
the sum into register R.
Affected: (R), CC
(R) + EHSE - - R
Trap: Fixed-point overflow
Fixed-Point Arithmetic Instructions
39
2
Condition code settings:
_---.:2::....-_3_ _
4
o
o
1
0
1
0
o
o
1
1
Resu It in R
zero
negative
positive
no fi xed-poi nt overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
If C C2 is set to 1 and the fi xed-poi nt ari thmetic trap mask
is 1, the computer traps to location X 143 1 after loading the
sum into regi ster R; otherwise, the computer executes the
next instruction in sequence.
ADD WORD
(Word index alignment)
AW
o
Condition code settings:
3
4
Result in R
o
o
0
1
0
zero
negative
positive
n() fixed-point overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
o
1
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X ' 43 1 after
loading the sum into registers Rand Ru1; otherwise, the
computer executes the next instruction in sequence.
Example 1, even R field value:
ED
(R)
(Ru 1)
CC
ADD DOUBlEWORD
(Doubleword index alignment)
ADD DOUBlEWORD adds the effective doubleword to the
contents of registers Rand Ru 1 (treated as a single, 64-bit
register); loads the 32 low-order bits of the sum into register Ru1 and then loads the 32 high-order bits of the sum
into register R. R must be an even value; if R is an odd
value, the result in register R is unpredictable.
Affected: (R), (Ru 1), CC
(R,Ru1) + ED--R,Rul
After execution
X' 33333333EEEEEEEE '
X' 33333333EEEEEEEE '
X 144444445 1
X1222222211
0010
X ' 11111111 1
X' 33333333 1
xxxx
SUBTRACT HAlFWORD
(Halfword index al ignment)
Affected: (R), CC
-EH
+ (R)-R
SE
Trap: Fixed-point overflow
Condition code settings:
2
o
3
4
Result in R
o
o
0
zero
negative
positive
no fixed-poi nt overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
1
1
0
1
o
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM)" is a 1, the computer traps to location X ' 43 1 after
loading the sum into register R; otherwise, the computer
executes the next instruction in sequence.
SW
SUBTRACT WORD
'YVord index 01 ignment)
Trap: Fixed-point overflow
3
4
_Resu It in R, Ru 1
SUBTRACT WORD forms the two1s complement of the effective word, adds that complement to the contents of register
R, and loads the sum into register R.
o
0
zero
negative
Affected: (R), CC
-EW + (R)-- R
Condition code settings:
o
40
Before execution
SUBTRACT HAlFWORD extends the sign of the effective
halfword 16 bit positions to the left (to form a 32-bit word
in which bit positions 0-15 contain the sign of the effective halfword), forms the two1s complement of the resulting
word, adds the complemented word to the contents of register R, and loads the sum into register R.
(AM) is a 1, the computer traps to location X' 43 1 after
loading the sum into register R; otherwise, the computer
executes the next instruction in sequence.
2
positive
no fixed-point ove:-flow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
1
If CC2 is set to 1 and the fixed-point arithmetic trap mask
AD
o
Trap: Fixed-point overflow
Affected: (R), CC
(R) + EW- R
1
Result in R, Ru1
1
ADD WORD adds the effective word to the contents of register R and loads the sum into register R.
o
4
o
SH
2
3
Fixed-Point Arithmetic Instructions
Trap: Fixed-point overflow
If R is an odd value, the result in register R is the 32 low-
Condition code settings:
2
3
4
Result in R
o
o
zero
negative
positive
no fi xed-poi nt overflow
fixed-poi nt overflow
no corry from bit position 0
corry from bit position 0
o
o
1
1
o
1
o
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X '43 1 after
order bits of the product. Thus, in order to generate a 64bit product, the R field of the instruction must be even and
the multiplicand must be in register R+1. The conditioncode
settings are based on the 64-bit product formed duri ng instruction execution, rather than on the final contents of
register R. Overflow cannot occur.
Affected: (R), (Ru1), CC2, CC3, CC4
(Rul) x (1)12-31 SE Condition code setti ngs:
2
loading the sum into register R; otherwise, the computer
executes the next instruction in sequence.
so
R, Ru1
3
4
64-bit product
o
o
o
zero
negative
o
SUBTRACT DOUBLEWORD
(Doubleword index alignment)
o
positive
resul t is correct, as represented in register Ru 1
result is not correctly representable in
register Ru 1 alone
SUBTRACT DOUBlEWORD forms the 64-bit twols complement of the effective doubleword, adds the complemented
doubleword to the contents of registers Rand Ru1 (treated
as a single, 64-bit register), loads the 32 low-order bits
of the sum into register Ru1 and loads the 32 high-or.der bits
of the sum into register R. R must be on even value; if R is
an odd value, the result in register R is unpredictable.
Affected: (R),(Rul),CC
-ED + (R, Ru1)--R, Ru1
Trap: Fixed-point overflow
If MI is indirectly addressed, it is treated as a nonexistent
instruction, in which case the computer unconditionally
aborts execution of the instruction (at the time of operation code decoding) and traps to location X ' 40 ' with the
contents of register R, register Ru 1, and the condition code
unchanged; otherwi se, the computer executes the next i nstruction° in sequence.
Example 1, even R field value:
Condition code settings:
Before executi on
2
o
i
o
3
4
Result in R, Ru1
o
o
o
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
1
o
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X I43 1 after the
result is loaded into registers Rand Ru1; otherwise, the computer executes the next instruction in sequence.
MI
MULTIPLY IMMEDIA TE
(Immediate operand)
The value field (bit positions 12-31 of the instructions word)
is treated as a 20-bit, twols complement integer. MUlTIPLY IMMEDIATE extends the sign of the value field (bit
position 12) of the instruction word 12 bit positions to the
left and multiplies the resulting 32-bit value by the contents of register Ru 1, then loads the 32 high-order bits of
the product into register R, and then loads the 32 loworder bits of the product into register Rul.
After execution
(1)12-31 = X?OOOOI
X?OOOOI
(R)
xxxxxxxx
X 100007000 1
(Ru 1)
X 110001000 1
X?OOOOOOOI
CC
xxxx
xll 0
Example 2, odd R field value:
1
1
(1)12-31= X 01234
X ' 01234 1
(R)
X 1000300021
X '369C2468I
CC
xxxx
xOlO
MH
MULTIPLY HAlFWORD
(Halfword index al ignment)
MULTIPLY HALFWORD multiplies the contents of bit positions 16-31 of register R by the effective halfword (with
both halfwords treated as signed, twols complement integers) and stores the product in register Ru1 (overflow cannot occur). If R is an even value, the original multiplier
in register R is preserved, allowi ng repetitive halfword
multiplication with a constant multiplier; however, if R is
Fixed-Point Arithmetic Instructions
41
an odd value, the product is loaded into the same register.
Overflow cannot occur.
OH
DIVIDE HALFWORD
(Halfword index alignment)
Affected: (Rul), (C3, CC4
(R)16-31 x EH - - Rul
Condition code settings:
2
3
4
a a
a 1
a
DIVIDE HALFWORD divides the contents of register R (treated
as a 32-bit fixed-point integer) by the effective hal fword
and loads the quotient into register R. If the absolute value
of the quotient cannot be correctly represented in 32 bits,
fixed-point overflow occurs; in which case CC2 is set to 1
and the contents of register R, and CC1, CC3, and CC4
are unchanged.
ResultinRul
zero
negative
positive
Example 1, even R field value:
EH
(R)
(R u 1)
CC
Before execution
After execution
X'FFFF '
X 'xxxxOOOA I
xxxxxxxx
xxxx
X'FFFF '
X I xxxxOOOA I
X ' FFFFFFF6 1
xx01
Affected: (R), CC2, CC3,
CC4
(R)~ E H - R
Condition code settings:
2
X'FFFF '
X I xxxxOOOA I
xxxx
EH
CC
3
4
a a a
0
a 1
a 1 a
Example 2, odd R field value:
(R)
Trap: Fixed-point overflow
X'FFFF '
X ' FFFFFFF6 1
xx01
Result in R
zero quotient, no overflow
negative quotient, no overflow
positive quotient, no overflow
fixed-point overflow
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X ' 43 1 with the
contents of register R, CC1, CC3, and CC4 unchanged.
MW
MULTIPLY WORD
(Word index al ignment)
MUL TIPL Y WORD multipl ies the contents of register Ru 1 by
the effective word, loads the 32 high-order bits of the product into register R and then loads the 32 low-order bits of
the product into register Rul (overflow cannot occur).
If R is an odd value, the result in register R is the 32 loworder bits of the product. Thus, in order to generate a 64bit product, the R field of the instruction must be even and
the multiplicand must be in register R+1. The condition
code settings are based on the 64-bit product formed during
instruction execution, rather than on the final contents of
register R.
Affected: (R),(Rul),CC
(Ru 1) x EW - - - + R, Ru 1
Condition code settings:
2
3
4
64-bit product
a
0
zero
a
negative
a
a
positive
result is correct, as represented in register Ru 1
result is not correctly representable in
register Rul alone
42
Fixed-Point Arithmetic Instructions
ow
DIVIDE WORD
(Word index al ignment)
DIVIDE WORD divides the contents of registers Rand Ru 1
(treated as a 64-bit fixed-point integer) by the effective
word, loads the integer remainder into register R and then
loads the integer quotient into register Ru 1. If a nonzero
reml..li nder occurs, the remai nder has the same sign as the
dividend (original contents of register R). If R is an odd
value, DW forms a 64-bit register operand by extending
the sign of the contents of register R 32 bit positions to the
left, then divides the 64-bit register operand by the effective word, and loads the quotient into register R. In this
case, the remainder is lost and only the contents of register
R are affected.
If the absolute value of the quotient cannot be correctly
represented in 32 bits, fixed-point overflow occurs; in
which case, CC2 is set to 1 and the contents of register R,
register Rul, CC1, CC3, and CC4 remain unchanged; otherwise, CC2 is reset to 0, CC3 and CC4 reflect the quotient
in register Ru1, and CCl is unchanged.
Affected: (R), (Rul), CC2
Trap: Fixed-point overflow
CC3, CC4
(R, Rul) -;- E W - R (remainder), Ru1 (quotient)
Condition code settings:
2
3
4
o a a
o a
Resul tin Ru1
zero quotient, no overflow
negative quotient, no overflow
violation cannot occur in this case; however, a memory
read-protection violation can occur.
Condition code seHings:
2
3
o
4
Result in Rul
o
positive quotient, no overflow
fixed-point overflow
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X ' 43 1 with the
original contents of register R, register Ru1, CCl, CC3, and
CC4 unchanged; otherwise, the computer executes the next
instruction in sequence.
AWM
ADD WORD TO MEMORY
(Word index al ignment)
ADD WORD TO MEMORY adds the contents of register R to
the effective word and stores the sum in the effective word
location. The sum is stored regardless of whether or not
overflow occurs.
Affected: (EWL), CC
EW + (R)-- EWL
Affected: CC if (1)8-11
OJ
(EBL) and CC if (1)8-11
If (1)8-11
f
If (1)8-11
= 0,
I
0
0, EB + (1)8-11 SE-- EBL and set CC
test byte and set CC
Condition code settings:
2
3
4
Result in EBL
0
0
0
1
0
0
zero
nonzero
no carry from byte
corry from byte
0
1
If MTB is executed in an interrupt location, the condition
code is not affected (see Chapter 2, "Single-Instruction
Interrupts") .
MTH
Trap: Fixed-point overflow
MODIFY AND TEST HALFWORD
(Halfword index alignment)
Condition code settings:
234
o
o
o
o
0
1
0
1
Result in EWL
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from bit position 0
carry from bit position 0
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the computer traps to location X ' 43 1 after the
result is stored in the effective word location; otherwise,
the computer executes the next instruction in sequence.
MTB
MODIFY AND TEST BYTE
(Byte index alignment)
If the value of the R field is nonzero, the high-order bit of
the R field (bit position 8 of the instruction word) is extended
12 bit positions to the left, to form a halfword with bit positions 0-11 of that halfword equal to the high-order bit of the
R field. This halfword is added to the effective halfword and
then (if no memory protectior violation occurs) the sum is
stored in the effective halfword location and the condition
code is set according to the value of the resultant halfword.
The sum is stored regardless of whether or not overflow occurs. This process allows modification of a halfword by any
number in the range -8 through +7, foil owed by a test.
If tile value of the R field is zero, the effective halfword is
tested for being a zero, negative, or positive value. The
condition code is set, according to the result of the test,
but the effective halfword is not affected. A memory writ€:protection violation cannot occur in this case; however, a
memory read-protection violation can occur.
Affected: CC if (1)8-11
If the value of R field is nonzero, the high-order bit of the
R field (bit position 8 of the instruction word) is extended
4 bit positions to the left, to form a byte with bit positions 0-4 of that byte equal to the high-order bit of the
R field. This byte is added to the effective byte and then
(if no memory protection violation occurs) the sum is stored
in the effective byte location and the condition code is set
according to the value of the resultant byte. This process
al lows modification of a byte by any number in the range
-8 through +7, fol lowed by a test.
Trap: Fixed-poi nt overflow
(EHL) and CC if (1)8-11
If (1)8-11
= 0,
If (1)8-11
f
f
0
test halfword and set CC
0, EH + (1)8-11 SE-- EHL and set CC
Condition code settings:
2
3
4
Result in EHL
o
0
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from hal fword
carry from hal fword
o
1
If the value of the R field is zero, the effective byte is
tested for being a zero or nonzero value. The condition
code is set according to the result of the test, but the
effective byte is not affected. A memory write-protection
= 0;
o
1
o
1
1
0
Fixed-Point Arithmetic Instructions
43
If CC2 is set to 1 and the fixed-point arithmetic trap
mask (AM) is a 1, the computer traps to location X'43'
after the result is stored in the effective halfword location; otherwise, the computer executes the next instruction in sequence. However, if MTH is executed in an
interrupt location, the condition code is not affected
and no fixed-point overflow trap can occur (see "SingleInstruction Interrupts").
MTW
MODIFY AND TEST WORD
(Word index alignment)
If the value of the R field is nonzero, the high-order
bit of the R field (bit position 8 of the instruction
word) is extended 28 bit positions to the left, to form
a word with bit positions 0-27 of that word equal to
the high-order bit of the R field. This word is added
to the effective word and then (if no memory protection violation occurs) the sum is stored in the effective
word location and the condition code is set according
to the value of the resultant word. The sum is stored
regardless of whether or not overflow occurs. This
process allows modification of a word by any number
in the range -8 through +7, followed by a test.
If the value of the R field is zero, the effective word
is tested for being a zero, negative, or positive value.
The condition code is set according to the result of the
test, but the effective word is not affected. A memory
write-protection violation cannot occur in this case;
however, a memory read-protection violation can occur.
Affected: CC if (1)8-11
= 0;
Trap: Fixed-point overflow
(EWL) and CC if (1)8-11
f
COMPARISON INSTRUCTIONS
The following comparison instructions are available to
SIGMA 6 computers:
Instruction Name
Mnemonic
Compare
Compare
Compare
Compare
Compare
Compare
Compare
Compare
CI
CB
CH
CW
CD
CS
f
COMPARE IMMEDIATE
(Immediate operand)
(I
COMPARE IMMEDIATE extends the sign of the value field
(bit position 12) of the instruction word 12 bit positions to
the left, compares the 32-bit result with the contents of register R (with both operands treated as signed fixed-point
quantities), and then sets the condition code according to
the results of the comparison.
Affected: CC2, CC3, CC4
(R) : (1)12-31 SE
Cond ition code setti ngs:
2
0
3
4
Result in EWL
o
o
0
zero
negative
positive
no fixed-point overflow
fixed-point overflow
no carry from word
carry from word
1
o
o
1
1
0
If CC2 is set to 1 and the fixed-point arithmetic trap
mask (AM) is a 1, the computer traps to location X'43'
after the result is stored in the effective word location;
otherwise, the computer executes the next instruction
in sequence. However, if MTVV is executed in an
interrupt location, the condition code is not affected
and no fixed-point overflow trap can occur (see IISingleInstruction Interrupts ll ) .
44
Comparison Instructions
3
4
Result of Comparison
o
0
equal
o
0, EW + 18 _ 11 SE -EWL and set CC
register value less than immediate value
o
Condition code settings:
2
ClR
ClM
All SIGMA 6 comparison instructions produce a condition
code setting which is indicative of the results of the comparison, without affecting the effective operand in memory
and without affecting the contents ofthedesignated register.
If (1)8-11 = 0, test word and set CC
If (1)8-11
Immediate
Byte
Halfword
Word
Doubleword
Selective
With Limits in Register
With Limits in Memory
o
register value greater than immediate
value
no I-bits compare, (R) n (I) 12-32SE = 0
one or more I-bits compare,
(R) n (I)12-32SE
f
0
If CI· is indirectl y addressed, it is treated as a nonexistent
instruction, in which case the computer unconditionally
aborts execution of the instruction (at the time of operation
code decoding) and then traps to location X'40' with the
condition code unchanged.
CB
COMPARE BYTE
(Byte index al ignment)
COMPARE BYTE compares the contents of bit positions
24-31 of register R with the effective byte (with both bytes
treated as positive integer magnitudes) and sets the condition code according to the results of the comparison.
2
Affected:
o
CC2, CC3, CC4
Condition code settings:
3
4
Result of Comparison
o
o
equal
o
1
register byte less than effective byte
o
register byte greater than effective byte
o
no l-bits compare, (R)24-31 n EB = 0
one or more l-bits compare,
(R)24-31 n EB -I 0
CH
4
Result of Comparison
o
reg i ster word greater than effect i ve word
no 1-bits compare, (R) n EW = 0
one or more l-bits compare, (R) n EVv fa
1
(R)24-31 : EB
2
3
COMPARE HALFWORD
(Halfword index alignment)
COMPARE HALFWORD extends the sign of the effective hal fword 16 bit positions to the I eft, then compares the resultant
32-bit word with the contents of register R (with both words
treated as signed, fixed-poin l quantities) and sets the condition code according to the results of the comparison.
COMPARE DOUBLEWORD
(Doubleword index alignment)
CD
COMPARE DOUBLEVvORD compares the effective doubleword with the contents of registers Rand Ru 1 (with both
doublewords treated as signed, fixed-point quantities) and
sets the condition code accordi ng to the resul ts of the comparison. If the R field of CD is an odd value, CD forms a
64-bit register operand (by duplicating the contents of register R for both the 32 high-order bits and the 32 low-order
bits) and compares the effective doubl eword with the 64-bi t
register operand. The condition code settings are based on
the 64-bit comparison.
Affected: CC3, CC4
(R, Ru 1) : ED
Condition code settings:
2
Affected: CC2, CC3, CC4
(R) : EHSE
3
4
Result of Comparison
0
0
equal
{)
register doubleword less than effective
doubleword
Condition code settings:
2
3
4
Result of Comparison
o
o
0
equal
register word less than effective halfword wi th si gn extended
o
o
no 1-b its compare, (R) n EH SE = 0
COMPARE WORD
(Word index alignment)
COMPARE WORD compares the contents of register R with
the effective word, with both words treated as signed fixedpoi nt quantities, and sets the condition code according to
the results of the comparison.
Affected: CC2, CC3, CC4
(R) : EW
Condition code setti ngs:
2
3
4
-----o 0
o
cs
register dou91eword greater than effective
doubleword
COMPARE SELECTIVE
(Word index alignment)
register word greater than effective
halfword with sign extended
one or more 1-bits compare,
(R) n EHSEfO
CW
0
Result of Comparison
equal
register word less than effective word
COMPARE SELECTIVE compares the contents of register R
with the effective word in only those bit positions selected by
a 1 in corresponding bit positions of register Ru 1 (mask). The
contentsof register R and the effective word are ignored in
those bit positions designated by a 0 in corresponding bit
positions of register Ru 1. The selected contents of register R
and the effective word are treated as positive integer magnitudes, and the condition code is set according to the result of the comparison. If the R field of CS is an odd value,
CS compares the contents of register R wi th the logical product (AND) of the effective word and the contents of regi ster R.
Affected: CC3,CC4
If R is even: (R) n(Ru 1) : EW n(Ru 1)
If R is odd: (R) : EW n(R)
Condition code settings:
2
3
4
Results of Comparison under Mask in Rul
o
o
0
1
1
0
equal
register word less than effective word
register word greater than effective word
(if R is even)
Comparison Instructions
45
ClR
All logical operations are performed bit by corresponding
bit between two operands; one operar d is in register Rand
the other operand is the effective word. The result of the
logical operation is loaded into register R.
39
~
!
2
J!4
5
COMPARE WITH LIMITS IN REGISTERS simultaneously compares the effective word with the contents of register Rand
with the contents of register Ru 1 (with all three words treated
as signed fixed-point quantities), and sets the condition
code according to the results of the comparisons.
Affected: CC
(R) : EW, (Ru 1) : EW
2
3
4
Result of Comparison
o
o
0
1
0
contents
contents
contents
contents
contents
contents
1
o
J
o
elM
OR
of
of
of
of
of
of
R equal to effective word
R less than effective word
R greater than effecti ve word
Ru 1 equal to effecti ve word
Ru 1 less than effective word
Ru 1 greater than effective word
OR WORD
(Word index alignment)
I
2
Condition code setti ngs:
2
3
4
Result of Com~arison
0
0
contents of R equal to most significant
word, (R) = ED _
O 31
word, (R)
0
0
0
2
I~
" " n"" " "
vl~ ~
i
• "
4
Resul t in R
o
0
zero
bit 0 of register R is a 1
Obit 0 of register R is a 0 and bit positions
1-31 of register R contain at least one 1
o
I
EXCLUSIVE OR WORD
(Word index alignment)
2
EXCLUSIVE OR WORD I ogical/y exclusive ORs the effective
word into register R. If corresponding bits of register Rand
the effective word are di fferent, a 1 is placed in the corresponding bit position of register R; if the contents of the
corr<:!sponding bit positions are alike, a 0 is placed in the
corresponding bit position of register R. The effective word
is not affected.
Affected: (R), CC3, CC4
(R)@EW--- R, where O@O = 0, 0@1 = 1,
1@0=1, 1@1=0
Condition code settings:
2
contents of R greater than most significant word, (R) > ED _
O 31
3
4
Result in R
o
o
0
zero
bit 0 of register R is a 1
Obit 0 of register R is a 0 and bit positions
1-31 of register R conta in at least one 1
contents of R equal to least significant
AND
AND WORD
0/'Iord index alignment)
contents of R less than least significant
0
word, (R)
0
46
3
o
< ED 0-31
word, (R) = ED 32-63
I X I : Referenc~ address
Condition code settings:
contents of R less than most significant
0
R
• '" " " " " " " " " ..
Affected: (R), CC3, CC4
(R) u EW R, where 0 u 0 = 0, 0 u 1 = 1, 1 u 0 = 1, 1 u 1 = 1
EOR
Affected: CC
(R) = ED _ ; (R) : ED O 31
32 63
"
OR WORD logically ORs the effective word into register R.
If corresponding bits of register R and the effective word are
both 0, a 0 remains in register R; otherwise, a 1 is placed in
the corresponding bit position of register R. The effective
word is not affected.
COMPARE WITH LIMITS IN MEMORY
(Doubleword index alignment)
COMPARE WITH LIMITS IN MEMORY simultaneously compares the contents of register R with the 32 high-order bits
of the effective doubleword and with the 32 low-order bits
of the effective doubleword, with all three words treated
as 32-bit signed quantities, and sets the condition code
according to the results of the comparisons.
I
49
o
Condition code settings:
o
o
LOGICAL INSTRUCTIONS
COMPARE WITH LIMITS IN REGISTERS
(Word index alignment)
< ED 32-63
contents' of R greater than Ieast significant word, (R) > ED _
32 63
Logical Instructions
o
I
2
AND WORD logically ANDs the effective word into register
R. If corresponding bits of register R and the effective word
ale bath 1, a 1 remains in register R; otherwise, a 0 is
placed in the corresponding bit position of register R. The
effecti ve word is not affected.
Affected: (R), CC3, CC4
(R) n EW - - R, where 0 n 0
1 n0
I
= 0,
= 0,
0 n1
1 n1
= 0,
=1
Condition code settings:
2
3
4
Result in R
0
0
zero
0
bit 0 of register R is a
0
bit 0 of register R is a 0 and bit positions
1-31 of register R contain at least one 1
SHIFT INSTRUCTIONS
The instruction format for logical, circular, and arithmetic
shift operations is:
s
integer, with the high-order bit (bit position 25) as the sign
(negative integers are represented in two's complement form).
A positive shift count causes a left shift of C bit positions.
A negative shift count causes a right shift of Ic bit positions. The value of C is within the range: -64: C :: +63.
All double-register shift operations require an even value for
the R field of the instruction, and treat registers Rand Rul
as a 64-bit register with the high-order bit (bit position Oaf
register R) as the sign for the entire register. If the R field
of SHIFT is an odd value and a double-register shift operation is specified, a register doubleword is formed by duplicating the contents of register R for both the 32 high-order
bits and the 32 low-order bits of the doubleword. The shift
operation is then performed and the 32 high-order bits of the
result are loaded into register R.
Overflow occurs (on left shifts only) whenever the value of
the sign bit (bit position 0 of register R) changes. At the
completion of logical left, circular left, and arithmetic left
shifts, the condition code is set as follows:
SHIFT
(Word index 01 ignment)
2
3
4
o
If neither indirect addressing nor indexing is called for in
the instruction SHIFT, bit positions 21-23 of the reference
address fi eld determine the type, and bit positions 25-31
determine the direction and amount of the shift. If only indirect addressing is called for in the instruction, bits 15-31
of the instruction are used to access the indirect word and
then bits 21-31 of the indirect word determine the type,
direction, and amount of the shift. If only indexing is
called for in the instruction, bits 21-23 of the instruction
word determine the type of shift; the direction and amount
of shift are determined by bits 25-31 of the instruction plus
bits 25-31 of the specified index register. If both indirect
addressing and indexing are called for in the instruction,
bits 15-31 of the instruction are used to access the indirect
word and then bits 21-23 of the indirect word determine the
type of shift; the direction and amount of the shiftare determined by bits 25-31 of the indirect word plus bits 25-31 of
the specified index register.
Bit positions 15-20 and 24 of the effective virtual address
are ignored. Bit positions 21, 22 and 23 of the effective
virtual address determine the type of shift, as follows:
21
22
23
Shift Type
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Logical, single register
Logical, double register
Circular, single register
Circular, double register
Arithmetic, single register
Arithmetic, double register
Undefined
Undefined
Bit positions 25 through 31 of the effective virtual address are
a shift count that determines the direction and amount of the
shift. Theshiftcount(C} is treated asa7-bit signed binary
Result of Shift
even number of l's shifted off left end of
register R
odd number of l's shifted off I eft end of
register R
o
no overflow on left shift
overflow on left shift
At the completion of logical right, circular right, and arithmetic right shifts, the condition code is set as follows:
234
o
0
Logica I Shift, Single Register
If the shift count, C, is positive, the contents of register R
are shifted left C places, with O's copied into vacated bit
positions on the right. (Bits shifted past RO are lost.) If C
is negative, the contents of register R are shifted right IC
places, with O's copied into vacated bit positions on the
left.· (Bits shifted past R31 are lost.)
I
Affected: (R), CC1, CC2
Logical Shift, Double Register
If the shift count, C, is positive, the contents of registers
Rand Ru 1 are shifted left C places, with O's copied into
vacated bit positions on the right. Bits shifted past bit position 0 of register Ru1 are copied into bit position 31 of register R. (Bits shifted past RO are lost.) If C is negative, the
contents of registers Rand Ru 1 are shifted right IC I places,
Shift Instructions
47
with OIS copied into vacated bit positions on the left. Bits
shifted past bit position 31 of register R are copied into bit
position a of register Ru 1. (Bits sh ifted past Ru 131 are lost.)
Affected: (R), (Ru1), CC1, CC2
Circular Shift, Single Register
FLOATING-POINT SHifT
See "Floating-Point Arithmetic Instructions" for a definition
of floating-point numbers. The forma~ for the floating-poinj
shift instruction is:
SF
If the shift count, C, is positive, the contents of registerR
are shifted left C places. Bits shifted past bit position 0
are copied into bit position 31. (No bits are lost.) If C
is negative, the contents of register R are shifted right ICI
places. Bits shifted past bit position 31 are copied into
bit position O. (No bits are lost.)
Affected: (R),CC1,CC2
Circular Shift, Double Register
If the shift count, C is positive, the contents of registers
Rand Ru 1 are shifted left C places. Bits shifted past bit
position a of register R are copied into bit position 31 of
register Ru1. (No bits are lost.) If C is negative, the
contents of registers Rand Ru1 are shifted right
places.
Bits shifted past bit position 31 of register Ru1 are copied
into bit position a of register R. (No bits are lost.)
Ici
Affected: (R), (Ru1), CC1, CC2
Arithmetic Shift, Single Register
If the shift count, C, is positive, the contents of register
R are shifted left C places, with O's copied into vacated
bit positions on the right. (Bits shifted past RO are lost.)
If C is negative, the contents of register R are shifted right
places, with the contents of bit position 0 copied into
vacated bit positions on the left. (Bits sh ifted past R31 are
lost. )
Ic I
If indirectaddressing or indexing is called for in the instruction
word, the effective virtual address is computed as for the instruction SHIFT except that bit position 23 of the effective
virtual address determines the type ofshift. Ifbit 23 is aO, the
contents of register R are treated as a short-format floatingpoint number; if bit 23 is a 1, the contents of registers Rand
Ru1 are treated as a long-format floating-point number.
The shift count, C, in bit positions 25 through 31 of the
effective virtual address determines the amount and direction of the shift. The shift count is treated as a 7-bit
signed binary integer, with the high-order bit (bit position
25) as the sign (negative integers are represented in twols
compl ement form).
The absolute value of the shift count determines the number
of hexadecimal digit positions the floating-point number is
to be shifted. If the shift count is positive, the floatingpoint number"is shifted left; if the count is negative, the
number is shifted right.
SHIFT FLOATING loads the floatLng-point number from the
register(s) specified by the R field of the instruction into a
set of internal registers. If the number is negative, it is
two's complemented. A record of the original sign is retained. The floating-point number is then separated into
a characteristic and a fraction, and CCl and CC2 are both
reset to O's.
A positive shift count produces the following left shift
operations:
1.
If the fraction is normalized (i.e., is less than 1 and is
equal to or greater than 1/16), or the fraction is all
O's, CC1 is set to 1.
2.
If the fraction field is all O's, the entire floating-point
number is set to all O's (true zero), regardless of the
sign and the characteristic of the original number.
3.
If the fraction is not normalized, the fraction field is
shifted 1 hexadecimal digit position (4 bit positions) to
the left and the characteristic field is decremented by
1. Vacated digit positions at the right of the fraction
are filled with hexadecimal O's.
Affected: (R), CC1, CC2
Arithmetic Shift, Double Register
If the shift count, C, is positive, the contents of registers
Rand Ru1 are shifted left C places, with O's copied into
vacated bit positions on the right. Bits shifted past bit
position a of register Ru 1 are copied into bit position 31
of register R. (Bits shifted past RO are lost.) If C is negative, the contents of registers Rand Ru 1 are shifted right ICI
places, with the contents of bit position a of register R
copied into vacated bit positions on the left. Bits shifted
past bit position 31 of register R are copied into bit position a of register Rul. (Bits shifted past Ru1 31 are lost.)
Affected: (R), (Ru1), CC1, CC2
48
Shift Instructions
SHIFT FLOATING
(Word index al ignment)
If the characteristic field underflows (i.e., is all lis
as the result of being decremented), CC2 is set to 1.
However, if the characteristic field does not underflow, the shift process (shift fraction, and decrement
characteristic) continues until the fraction is normalized, until the characteristic field underflows, or
until the fraction is shifted left C hexadecimal digit
positions, whichever occurs first. (Any two, or all
three, of the terminating conditions can occur
simultaneously. )
4.
5
At the completion of the left shift operation, the f1oatingpoint result is loaded back into the general register{s).
If the number was originall y negative, the two's compi ement of the resul tant number is loaded into the general register{s}.
The condition code settings following a floating-point
left shift are as follows:
2
3
4
Result
o
o
o
true zero (all O's)
negative
o
o
o
positive
C digits shifted (fraction unnormalized, no characteristic underflow)
fraction normalized {includes true
zero}
Floating Shift, Single Register
The short-format floating-point number in register R is shifted
according to the rules established above for floating-point
shift operations.
Affected: {R},
cc
Floating Shift, Double Register
The long-format floating-point number in registers Rand Rul
is shifted according to the rules established above for floatingpoint shift operations. (If the R field of the instruction word
is an odd value, a long-format floating-point number is generated by duplicating the contents of register R, and the 32
high-order bits of the result are loaded into register R.)
Affected: (R), (Ru 1 ),
cc
characteristic underflow
CONVERSION INSTRUCTIONS
A negative shift count produces the following right shift operations (again assuming that negative numbers are two's
complemented before and atter the shift operation):
The following two conversion instructions are provided by the
SI GMA 6 computer:
1.
The fraction field is shifted 1 hexadecimal digit position to the right and the characteristic field is incremented by 1. Vacated digit positions at the left are
filled with hexadecimal O's.
Instruction Name
Mnemonic
Convert by Addition
Convert by Subtraction
CVA
CVS
If the characteristic field overflows (i.e., is all O's as
These two conversion instructions can be used to accompl ish
bidirectional translation betw~en binary code and any other
weighted binary code, such as BCD.
2.
the result of being incremented), CC2 is set to 1. However, if the characteristic field does not overflow, the
shift process {shift fraction, and increment characteristic} conti nues unti I the characteristic field overflows
or until the fraction is shifted right
hexadecimal
digit positions, whichever occurs first. (Both terminating conditions can occur simultaneously.)
Ici
3.
If the resultant fraction field is all O's, the entire
floating-point number is set to all O's {true zero}, regardless of the sign and the characteristic of the original number.
4.
At the completion of the right shift operation, the
floating-point result is loaded back into the general
register{s}. If the number was originally negative, the
two's complement of the resultant number is loaded
into the general register{s}.
5.
3
4
Resul t
If an interrupt or memory protection violation trap occurs during
the execution of either instruction, the instruction sequence is
aborted (without having changed the contents of register R or
Ru 1) and restarted {at the beg inning of the instruction sequence}
after the interrupt or trap routine is processed.
o
o
o
true zero {all zeros}
eVA
The condition code settings following a floating-point
right shift are as follows:
2
negative
o
o
o
0
The effective addresses of the instructions CONVERT BY
ADDITION and CONVERT BY SUBTRACTION each point
to the starting location of a conversion table of 32 words,
containing weighted values for each bit position of register
Rul. The 32 words of the conversion table are considered to
be 32-bit positive quantities, and are referred to as conversion values. The intermediate results of these instructions
are accumulated in internal CPU registers unti I the i nstruction is completed; the result is then loaded into the appropriate general register. Both instructions use a counter (n)
that is set to 0 at the beginning of the instruction execution
and is incremented by 1 with each iteration, unti I a total of
32 iterations have been performed.
CONVERT BY ADDITION
0/Vord index alignment)
positive
I
IC digi ts shifted (no characteristic
overflow)
characteri sti c overfl ow
CONVERT BY ADDITION initially clears the internal A register and sets an i nterna I counter (n) to O. If bit position n
Conversion Instructions
49
of register Ru1 contains a 1, CVA adds the nth conversion
value (contents of the word location pointed to by the effective address plus n) to the contents of the A register,
accumulates the sum in the A register, and increments n
by 1. If bit position n of register Ru1 contains a 0, CVA
only increments n. If n is less than 32 after being incremented, the next bit position of register Ru 1 is examined,
and the addition process continues through n equal to 31;
the result is then loaded into register R. If, on any iteration, the sum has exceeded the value 2 32 -1, CCl is set to
1; otherwise, CC 1 is reset to O.
If n < 32, repeat; otherwise, (A) - - R, (B) conti nue to the next instruction
Condition code settings:
2
n
If n
= 0,
Result in Ru 1
0
0
zero
repeat; otherwise, (A) next instruction
0
bit 0 of register Ru 1 is a 0 and bit positions 1-31 of register Ru 1 contain at
least one 1
The following floating-point arithmetic instructions are
available as optional SIGMA 6 instructions:
234
0
Instruction Name
Mnemonic
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
FAS
FAL
FSS
FSL
FMS
FML
FDS
FDL
R and continue to
Condition code settings:
ResultinR
zero
bit 0 of register R is a 1
Add Short
Add Long
Subtract Short
Subtract Long
Multiply Short
Multiply Long
Divide Short
Divide Long
Obit 0 of register R is a 0 and bit positions
1-31 of register R contain at least one 1
o
sum is correct (less than 2 32 )
sum is greater than 2 32 - 1
cvs
bit 0 of register Ru 1 is a 1
then n + 1 - - n
< 32,
o
o
4
FLOATING-POINT ARITHMETIC INSTRUCTIONS
If (Rul) = 1, then (EWL + n) + (A) - A , n + 1 - n
n
3
0
Affected: (R), CC1, CC3, CC4
o --A, 0 - - n
If (Ru 1)
Ru 1 and
CO NVERT BY SUBTRACTION
0Nord index al ignment)
CONVERT BY SUBTRACTION loads the internal A register
with the contents of register R, clears the internal B register, Old sets an internal counter (n) to O. All conversion
val ues are considered to be 32-bit positive quantities. If
the nth conversion value (the contents of the word location
pointed to by the effective address plus n) is equal to or less
than the current contents of the A register, CVS increments
n by 1, adds the two's complement of the nth conversion
value to the contents of the A register, stores the sum in
the A register, and stores a 1 in bit position n of the B regi ster. If the nth conversi on val ue is greater than the current
contents of the A register, CVS only increments n by 1. If
n is I ess than 32 after bei ng incremented, the next conversion value is compared and the process continues through
n equal to 31; the remainder in the A register is loaded into
register R, and the converted quantity in the B register is
loaded into register Rul.
FLOATING-POINT NUMBERS
SIGMA 6 accommodates two number formats for floatingpoint arithmetic: short and long. A short-format floatingpoint number consists of a sign (bit 0), a biased t , base 16
exponent, which is called a characteristic (bits 1-7), and
a six-digit hexadecimal fraction (bits 8-31). A long-format
floating-point number consists of a short-format floatingpoint number followed by an additional eight hexadecimal
digits of fractional significance and occupies a doubl eword
memory location or an even-odd pair of general registers.
A SIGMA 6 floating-point number (N) has the following
formct:
A floQting-point number (N) has the following formal
defi nition:
1.
N
=F x
16 C -64 where F
= 0 or
16- 6 :s IF l::s 1 (short format) or
16- 14 :s IFI::s 1 (long format)
and O::s C ::s 127
Affected: (R), (Rul), CC3, CC4
(R) --- A, 0 --B, 0 - - n
If (EWL + n) :s (A) then A - (EWL + n) - - A,
1 - - Bn, n + 1 - - n .
If (EWL + n)
50
> (A)
then n + 1 - - n
Floating-Point Arithmetic Instructions
tThe bias value of 4016 is added to the exponent for the
purpose of making it possible to compare the absolute magnitude of two numbers, i. e., without reference to a sign
bit. This manipulation effectively removes the sign bit,
making each characteristic a 7-bit positive number.
2.
3.
5.
SIGMA 6 contains three mode control bits that are used to
qualify floating-point operations. These mode control bits
are identified as FS (floating significance), FZ (floating
zero), and FN (floating normalize), and are contained
in bit positions 5, 6, and 7, respectively, of the program
status doubleword (PSD 5 -7)'
The_ floating-point mode is established by setting the three
floating-point mode control bits. This can be performed by
any of the following instructions:
<1
A negative floclting-point number is the two's compl ement of its positive representation.
By this definition, a floating-point number of the form
1xxx xxxx 11 11 0000 . .. 0000
1xxx xxxx 0000 0000 . •• 0000
is illegal and, whenever gf'nerated by floating-point instructions, is converted to the form
1yyy yyyy 1111 0000 . .. 0000
+(16 -3)(209/256)
+ (16 -63)(2047/4096)
+(16 -64) (1 /16)
a (called
true zero)
Load Conditions and Floating Control
Immediate
LCFI
Load Program Status Doubleword
LPSD
Exchange Program Status Doubleword
XPSD
Instruction Name
Mnemonic
Store Conditions and Floating Control
STCF
Exchange Program Status Doubleword
XPSD
Floating-Point Number Representation
±
+(16+ )(5/16)
LCF
Short Floating -point Format
Dec imal Number
3
. Load Conditions and Floating Control
The floating-point mode control bits are stored by executi ng
either of the following instructions:
is normal ized, and a floating-point number of the form
+(16+63)(1-2 -24)
Mnemonic
Instruction Name
A negative floating-point number is normal ized if and
onl y if its two's compl ement is a normal ized positive
number.
Table 6.
a
a
a
a
a
a
Table 6 contains
MODES OF OPERATION
A positive floating-point number is normal ized if and
onl y if the fraction is contained in the interval
1/16 sF
4.
where yy ... y is 1 less than xx ... x.
examples of floating-point numbers.
Apositivefloating-pointnumberwith a fraction of zero
and a characteristi c of zero is a IItrue ll zero. A positive
floating-point number with a fraction of zero and a nonzerO characteristic is an lIabnormal ll zero. For floatingpoint multipl ication and division, an abnormal zero is
treated as a true zero. However, for addition and
subtraction, an abnormal zero is treated the same as
any nonzero operand.
F
C
111
Hexadecimal Value
1111
1111 1111 1111
1111
1111
7F
FFFFFF
100 0011
0101 0000 0000 0000 0000 0000
43
500000
all
1101 0001 0000 0000 0000 0000
3D
Dl0000
1101
1111
000 0001
0111
1111 1111 0000 0000 0000
01
7FFOOO
000 0000
0001 0000 0000 0000 0000 0000
00
100000
000 0000
0000 0000 0000 0000 0000 0000
00
000000
-(16 -64)(1/16)
1
111
1111
1111 0000 0000 0000 0000 0000
FF
FOOOOO
-(16 -63)(2047/4096)
1
111
1110
1000 0000 0001 0000 0000 0000
FE
801000
-( 16 -3) (209/256)
3
-( 16+ )(5/16)
_(16+ 63 )(1_2 24 )
1
100 0010
0010 1111 0000 0000 0000 0000
C2
2 FOOOO
1
all
1100
1011 0000 0000 0000 0000 0000
BC
BOOOOO
1
000 0000
0000 0000 0000 0000 0000 0001
80
000001
Spec ia I Case:
e
-(16 )(l)
e 1
-(16 + )(1/16)
1
is changed to
e
0000 0000 0000 0000 0000 0000
--
1
e + 1
1111 0000 0000 0000 0000 0000
whenever generated as the result of a floating-.point instruction.
Floating-Point Arithmetic Instructions
51
UNIMPLEMENTED FLOATING-POINT INSTRUCTIONS ~S
set equal to true zero, the condition code is
set to 1000, and the computer executes the
next instruction in sequence. If more than
two hexadecimal place~ of postnormalization
shifting are required one characteristic under ....
flow does not occur, the condition code is set
to 1010 if the result is positive, or to 1001 if
the result is negative; then, the computer executes the next instruction in sequence.
(Exception: if characteristic underflow occurs
with FS = 0, FZ determines the resultant action.)
If the optional floating-point instruction set is not implemented in the computer and execution of a floating-point
arithmetic instruction is attempted, the computer unconditi onall y aborts execution of the instruction (at the time of
operation code decoding). The computer then traps to location X ' 41 1 , with the contents of the condition code and
all general registers unchanged. Location X'41' is the
"unimplemented instruction" trap location.
FLOA TlNG·-POINT ADD AND SUBTRACT
FS
=1
The floating normalize (FN), floating zero (FZ), and floati ng
significance (FS) mode control bits determine the operation of
floating-point addition and subtraction (if characteristic
overflow does not occur) as follows:
FN Floating normalize:
FN = a The results of additions and subtractions are
to be postnormalized. If characteristic underflow occurs, if the result is zero, or if more
than two postnormalization hexadecimal shifts
are required, the setti ngs for FZ and FS determine the resultant action. If none of the
above conditions occur, the condition code
is set to 0010 if the result is positive or to
0001 if the result is negative.
FN = 1
FZ
Floating zero: (applies only if FN
FZ = a
FZ = 1
FS
a
If characteristic overflow occurs, the CPU always traps to
location X'44' with the general registers unchanged and the
condition code set to 0110 if the result is positive, or to
0101 if the result is negative.
FLOATING-POINT MULTIPLY AND DIVIDE
The floating zero (FZ) mode control bit alone determines
the operation of floating-point multiplication and division
(if characteristic overflow does nqt occur and division by
zero is not attempted) as follows:
FZ Floating zero:
FZ
=a
If the final result of a multiplication or division operation cannot be expressed in normalized form because of the characteristic being
reduced below zero, underflow has occurred.
If underflow occurs, the result is set equal to
true zero and the condition code is set to 1100.
If underflow does not occur, the condition code
is set to 0010 if the result is positive, to 0001
if the result is negative, orto 0000 if the result
is zero.
FZ
=1
Underflow causes the computer to trap to location X'44' with the contents of the general
registers unchanged. The condition code is
set to 1110 if the result is positive, or to 1101
if the result is negative. If underflow does
not occur, the resultant action is the same
as that for FZ = O.
= 0)
If the final result of an addition or subtraction operation cannot be expressed in normalized form because of the characteristic being
reduced below zero, underflow has occurred,
in which case the result is set equal to true
zero and the condition code is set to 1100.
(Exception: if a trap results from significance
checking with FS = 1 and FZ = 0, an underflow generated in the process of postnormalizing is ignored.)
Characteristi c underflow causes the computer
to trap to Iocati on X '44' with the contents of
the general registers unchanged. If the result
is positive, the condition code is set to 1110.
If the result is negative, the condition code
is set to 110 1.
Floating significance: (applies only if FN = 0)
FS -=
52
Inhibit postnormalization of the results of additions and subtractions. The settings of FZ
and FS have no effect on the i nstructi on operation. If the result is zero, the result is
set to true zero and the condition code is set
to 0000. If the result is positive, the condition code is set to 0010. If the result is
negative, the condition code is set to 0001.
Inhibit signifi-ance trap. If the result of an
addition or subtraction is zero, the result is
Floating-Point Arithmetic Instructions
The computer traps to location X'44' if more
than two hexadecimal places of postnormalization shifting are required or if the result is
zero. The condition code is set to 1000 if the
result is zero, to 1010 if the result is positive,
or to 1001 if the result is negative; however,
the contents of the general registers are not
changed. (Exception: if a trap results from
characteristic underflow wi th FZ = 1, the results of significance testing are ignored.)
If the divisor is zero in a floating-point division, the computer always traps to location X'44' with the general registers unchanged and the condition code set to 01 00. If
characteristic overflow occurs, the computer al ways traps
to location X'44' with the general registers unchanged and
the condition code set to 0110 if the result is positive, or
to 0101 if the resu It is negative.
FAl
CONDITION CODES FOR FLOATING-POINT INSTRUCTIONS
The condition code settings for floating-point instructions
are summarized in Table 7. The following provisions apply
to all floating-point instructions:
1.
The effective doubleword and the contents of registers Rand
Ru1 are loaded into a set of internal registers.
Underflow and overflow detection apply to the final
characteristic, not to any lIintermediate ll value.
2.
If a floating-point operation results in a trap, the
original contents of all general registers remain
unchanged.
3.
All shifting and truncation are performed on absolute
magnitudes. If the fraction is negative, then the two's
complement is formed after shifting or truncation.
FAS
The operation of FAL is identical to that of F LOA TIN G ADD
SHORT (FAS) except that the fractions to be added are each
14 hexadecimal digits long, guard digits are not appended
to the fractions, and R must be an even value for correct results. If no floating-point arithmetic fault occurs, the sum
is loaded into registers Rand Ru1 as a long-format floatingpoint number.
Traps: Unimplemented instruction, floatingpoint arithmetic fault
Affected: (R), (Ru1), CC
(R, Ru1) + ED R, Ru1
FLOATING ADD SHORT
(Word index al ignment, optional)
FSS
The effective word and the contents of register R are loaded
into a set of internal registprs and a low-order hexadecimal
zero (guard digit) is appended to both fractions, extending
them to seven hexadecimal digits each. FAS then forms the
floating-point sum of the two numbers. If no floating-point
arithmetic fault occurs, the sum is loaded into register R as
a short-format fl oati ng-poi nt number.
Affected: (R), CC
(R) + EW-R
FLOATING ADD LONG
(Doubleword index al ignment, optional)
FLOATING SUBTRACT SHORT
(Word index alignment, optional)
The effective word and the contents of register R are loaded
into a set of i nterna I registers.
FLOATING SUBTRACT SHORT forms the two's complement
of the effective word and then operates identicall y to
FLOATING ADD SHORT (FAS). If no floating-point arithmetic fault occurs, the difference is loaded into register R
as a short-format fl oati ng-poi nt number.
Traps: Unimplemented instruction, floatingpoint arithmetic fault
Affected: (R), CC
(R) - EW-R
; Traps: Unimplemented instruction, floatingpoint arithmetic fault
Table 7. Condition Code Settings for Floating-Point Instructions
Condition Code
Mean i ng if no trap to location X'44 t occurs
1
2
3
4
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
*(l)
*
*
0
0
0
0
0
0
-A + A
1
N
1
0
N >0
1
1
0
0
1
0
underflow with FZ=O and no trap by FS=l
1
*
*
~I :
1
1
1
1
1
1
0
A x 0, O/A, or -A + ACD with FN=l
N <0
N >0
Notes: CD
-
I
I
norma I
results
Meaning if trap to location X'44' occurs
*(l)
*
*
div ide by zero
overflow, N < 0
overflow, N > 0
<
CD
°I> 2
postnorma'-l FS=O, FN=O, and
izing shifts
no underflow
CD
-A + A
N <0
N >0
I
I
always trapped
> 2 postnormalizing shifts
*
underflow, N < 0
underflow, N >0
l
I
FS=l, FN=O, and no
underflow with FZ= 1
FZ=l
result ~et to true zero
(l) 11*11 indicates impossible configurations
@ applies to add and subtract only where FN=O
Floating-Point Arithmetic Instructions
53
FSL
FLOATING SUBTRACT LONG
(Doubleword index 01 ignment, optional)
Affected: (R), (Ru 1), CC
(R, Ru 1) x ED R, Ru 1
FDS
Traps: Un implemented instruction, floatingpoint arithmetic faull
FLOA TING DIVIDE SHORT
0Nord index al ignment, optional)
The effective doubleword and the contents of registers Rand
Ru 1 are loaded into a set of internal registers.
3E
FLOATING SUBTRACT LONG forms the two·s complement
of the effective doubleword and then operates identically
to FLOATING ADD LONG (FAL). If no floating-point
arithmetic fault occurs, the difference is loaded into registers Rand Ru 1 as a long-format floating-point number.
Affected: (R), (Ru 1), CC
(R, Rul) - ED - R , Rul
FMS
Traps: Unimplemented instruction, f/oatingpoint arithmetic fault
o
1
1
78,9
1011 12
1~
14 15 16 17 18 19120 21222324 25262712829 30 31
The effective word (divisor) and the contents of register R
(dividend) are loaded into a set of internal registers and both
numbers are then prenormal ized (if necessary). FLOATING
DIVIDE SHORT then forms a floating-point quotient with a
6-digit, normal ized hexadecimal fraction. If no floatingpoint arithmetic fault occurs, the quotient is loaded into
. register R as a short-format floating-point number.
Affected: (R), CC
(R) + EW R
Traps: Unimplemented instruction, floatingpoint arithmetic faul t
FLOATING MULTIPLY SHORT
(Word index al ignment, optional)
FDL
o
2
FLOATING DIVIDE LONG
(Doubleword index alignment, optional)
2
The effective word (multipl ier) and the- contents of register
R (mul tipl icand) are loaded into a set of internal registers,
and both numbers are then prenormal ized (if necessary).
The product of the fractions contains 12 hexadecimal digits.
If no floating-point arithmetic fault occurs, the product is
loaded into register R as a properly truncated short-format
floating-point number.
The result of floating-mul tiply is always postnormal ized.
At most, one place of postnormalizing shift may be required.
Truncation takes place after postnormal ization.
Affected: (R), CC
(R) x EW R
Traps: Unimplemented ins tru cti on, fI oat i ngpointarithmetic fault
The effective doubleword (divisor) and the contents of registers Rand Ru 1 (dividend) are loaded into a set of internal
registers. FLOATING DIVIDE LONG then operates identically to FLOATING DIVIDE SHORT (FDS), except that the
divisor, dividend, and quotient fractions are each 14 hexadecimal digits long, and R must be an even value for correct
results. If no floating-point arithmetic fault occurs, the
quotient is loaded into registers Rand Ru 1 as a long-format
floating-point number.
Affected: (R), (Ru 1), CC
(R, Rul) + ED R, Rul
Traps: Unimplemented instruction, floatingpoint arithmetic faul t
DECIMAL INSTRUCTIONS
FML
FLOATING MULTIPLY LONG
(Doubleword index alignment, optional)
The effective doubreword (multiplier) and the contents of
registers Rand Ru 1 (multiplicand) are loaded into a set of
internal registers. FLOATING MULTIPLY LONG then
operates identically to FLOA TING MULTIPLY SHORT (FMS),
except that the mul tipl ier and the multiplicand fractions are
each 14 hexadecimal digits long, the product fraction is 28
hexadecimal digits long, and R must be an even value for
correct results. If no floating-point arithmetic fault occurs,
the postnormalized product is truncated to a long-format
floating-point number and loaded into registers Rand Ru 1.
54
Decimal Instructions
The fallowing instructions comprise the standard decimal instruction set:
Instruction Name
Mnemonic
Decimal Load
Decimal Store
Decimal Add
Decimal Subtract
Decimal Multiply
Decimal Divide
Decimal Compare
Decimal Shift Arithmetic
Pack Decimal Digits
Unpack Decimal Digits
Edit Byte String (described under
Byte String Instructions)
DL
DST
DA
DS
DM
DD
DC
DSA
PACK
UNPK
EBS
PACKED DECIMAL NUMBERS
All SIGMA 6 decimal arithmetic instructions operate on
packed decimal numbers, each consisting of from 1 to 31
decimal digits (in absolute form) plus a decimal sign. A
decimal digit is a 4-bit code in the range 0000 through 1001,
where 0000 = 0, 0001 = 1, 0010 = 2, 0011 = 3, 0100 = 4,
0101 = 5, 0110 = 6, 0111 = 7, 1000 = 8, and 1001 = 9. A
positive decimal sign is a 4-bit code of the form: 1010(X'A'~
1100(X'C}, 1110(X ' E' ), or 1111 (X'F"). A negative decimal
sign is a 4-bit code of the form: 1011 (X'B') or 1101 (X'D').
However, the decimal sign codes generated for the result of
a decimal instruction are: 1100 (XlC') for positive results,
and 1101 (X'D') for negative results. The format of packed
decimal numbers is:
II
I sign
digit
o
1
2
3
4
5
6
7
I
For the decimal arithmetic instructions, a packed decimal
number must occupy an integral number (1 through 16) of
consecutive bytes. Thus, a decimal number must contain an
odd number of decimal digits, the high-order digit (zero or
nonzero) of the number must be in bit positions 0-3 of the
first byte, the decimal sign must be in bit positions 4-7 of
the last byte, and all decimal digits and the decimal sign
must be 4-bit codes of the fc-rm described above.
ZONED DECIMAL NUMBERS
The indirect address bit (position a), the operation code
(positions 1-7), the index field (12-14), and the reference
address field (15-31) all have the same functions for the
decimal instructions as they do for any other SIGMA 6 byte
addressing instruction. However, bit positions 8-11 of the
instruction word do not refer to a general register; instead,
the contents of this field (designated by the character ilL")
designate the length, in bytes, of a packed decimal number. (If L = 0, a length of 16 bytes is assumed.)
ILLEGAL DIGIT AND SIGN DETECTION
Prior to executing any decimal instruction, the computer
checks all decimal operands for the presence of illegal decimal digits or illegal decimal signs. For all decimal arithmetic instructions except DECIMAL MULTIPLY and DECIMAL DIVIDE, an illegal decimal digit is a sign code (i. e.,
in the range X'A ' through X'F') that appears anywhere except in bit positions 4-7 of the least significant byte (the
sign position) of the packed decimal number; an illegal
decimal sign is a digit code (i. e., in the range X'O' through
X ' 9 1) that appears in the sign position of the packed decimal number.
For the instructions DECIMAL MULTIPLY and DECIMAL
DIVIDE, the effective decimal operand is checked for
illegal digits or signs as above. However, the operand in
the decimal accumulator is checked to verify that there is
at least one legal decimal sign code somewhere in the number. (This type of check is a result of the interruptibility
of these instructions, which may leave the decimal accumulatorwith a partially-completed result containing an internal
sign code.)
In zoned decimal format, a single decimal digit is contained
within bit positions 4-7 of a byte, and bit positions 0-3 of
the byte are referred to as the "zone" of the decimal digit.
A zoned decimal number consists of from 1 to 31 bytes, with
the decimal sign appearing as the zone for the last byte, as
follows:
If an illegal digit or sign is detected, the computer uncon-
A decimal number can be converted from zoned to packed
format by means of the instruction PACK DECIMAL DIGITS.
A decimal number can be converted from packed to zoned
format by means of the instruction UNPACK DECIMAL
DIGITS.
ditionally aborts the execution of the instruction (at the
time that the illegal digit or sign is detected), sets CC 1 to 1
and -esets CC2 to O. If the decimal arithmetic faul t trap
mask (bit position 10 of the program status doubleword)
is a 0, the computer then executes the next instruction in
sequence; however, if the decimal arithmetic fault trap
mask (PSDlO) is a 1, the computer traps to location X'4S'.
In either case, the contents of the decimal accumulator,
the effective deci mal operand, CC3, and CC4 remain
unchanged.
DECIMAL ACCUMULATOR
OVERfLOW DETECTION
All decimal arithmetic instructions imply the use of registers
12 through 15 of the current register bank as the decimal accumulator, and registers 12 through 15 are treated as a single
16-byte register. The entire decimal accumulator is used in
every decimal arithmetic instruction.
Arithmetic overflow can occur during execution of the following decimal instructions:
DECIMAL INSTRUCTION FORMAT
DECIMAL ADD: overflow occurs when the sum of the two
decimal numbers exceeds the 31-digit ca)acity of the
decimal accumulator (+ 10 31 - 1 to - 10 3 + 1).
The general format of a decimal instruction is as follows:
DECIMAL SUBTRACT: overflow occurs when the difference
between the two decimal numbers exceeds the 31-digit
capacity of the decimal accumulator.
Decimal Instructions
55
DECIMAL DIVIDE: overflow occurs either when the divisor
is zero, or when the dividend is greater than 14 digits in
length and the absolute value of the significant digits to
the left of the 15th digit position (counting from the right)
is greater than or equal to the absolute value of the
divisor.
If arithmeti c overflow occurs during execution of DECIMAL
ADD, DECIMAL SUBTRACT, or DECIMAL DIVIDE, the computer unconditionally aborts execution of the instruction (at
the time of overflow detection), resets CC 1 to 0, and sets'
CC2 to 1. Then, if the decimal arithmetic fault trap mask
(PSD 10) is a 1, the computer traps to location X'45'; if the
decimal arithmetic fault trap mask is a 0, the computer executes the next instruction in sequence. In either case, the
contents of the decimal accumulator, memory storage, CC3,
and CC4 remain unchanged.
DECIMAL INSTRUCnON NOMENClATURE
For the purpose of abbreviating the instruction descriptions
to follow, the symbol ic term IIDECA" is used to represent
the decimal accumulator, and the symbolic term IIEDO II is
used to represent the effective decimal operand of the instruction. For the instructions DECIMAL LOAD, DECIMAL
ADD, DECIMAL SUBTRACT, DECIMAL MULTIPLY, DECIMAL DIVIDE, and DECIMAL COMPARE, the effective decimal operand is a packed decimal number that is IILII bytes
in length, where L is the numeric value of bit positions 8-11
of the instruction word, and a val ue of a for L designates
16 bytes. The effective byte addresses of these instructions
point to the byte location that contains the most significant
byte (high-order digits) of the decimal number, and the effective byte address pi us L-l (where L = a = 16) points to
the least significant byte (low-order digit and sign) of the
dec imal number. Thus, for these instructions, the effective
decimal operand (EDO) is the contents of the byte string
that begins with the effective byte location, is L bytes in
Iength, and ends with the effective byte location plus L-l .
CONDITION CODE SETTINGS
All decimal instructions provide condition code settings,
using CCI toindicate whether or not an illegal digit or sign
has been detected, and CC2 to indicate whether or not overflow has occurred. Most (but notall) of the decimal instructions provide condition code settings, using CC3 and CC4 to
indicate whether the decimal number in the decimal accumulator is zero, negative, or positive, as follows:
CC3 CC4
Result in DECA
a
zero - the decimal accumulator contains a
positive or negative decimal sign code in the
4 low-order bit positions; the remainder of
the decimal accumulator contains all a's.
a
56
a
negative - the deci mal accumulator contains
a negative decimal sign code in the 4 loworder bit positions; the remainder of the decimal accumulator contains at least one nonzero
decimal digit.
Decimal Instructions
CC3 CC4
positive - the decimal accumulator contains
a positive dec imal sign code in the 4 loworder bit positions; the remainder of the decimal accumulator contains at least one
nonzero decimal digit.
a
DL
Result in DECA
DECIMAL LOAD
(Byte index alignment)
If no illegal digit or illegal sign is detected in the effective
decimal operand, DECIMAL LOAD expands the effective
decimal operand to 16 bytes (31 digits + sign) by appending
high-order D's, and then loads the expanded decimal number into the decimal accumulator. If the result i., the decimal
accumulator is zero, the converted sign remains unchanged.
Affected: (DECA), CC
Traps: Deci mal arithmetic
(EBL to EBL + L-I) - - DECA
Condition code settings:
2
3
4
illegal digit or sign detected, instruction
aborted
a
a
a
a
a
a
a
a
a
CST
Result in DECA
·0
zero
negative
a
positive
I
no illegal digit or illegal
sign detected, instruct i on
completed
DECIMAL STORE
(Byte index al ignment)
If no illegal digit or sign is detected in the decimal accumulator, DECIMAL STORE stores the low-order L bytes
of the decimal accumulator into memory from the effective byte location to the effective byte location plus L-l.
If the decimal accumulator contains more significant information than is actually stored (i. e., at least one nonzero digit was not stored), CC2 is set to I; otherwise
CC2. is reset to O. If the result in memory is zero, the
converted sign remains unchanged.
Affected: (EBL to EBL + L-l),
CC1, CC2
Traps: Decimal arithmetic
(DECA) low-order bytes - - EBL to EBL + L-l
Condition code setti ngs:
2
a
3
4
Result of DST
illegal digit or sign detected, instruction
aborted
2
o
3
4
o
Result of DST
all significant in_j
formation stored
no illegal digit or
illegal sign detecsome significant
ted, i nstructi on
information not
completed
stored
o
CCl is reset to 0, CC2 is set to 1, and the instruction is
aborted with the contents of the previous decimal accumulator, CC3 and CC4 unchanged.
Affected: (DECA), CC
(DECA) - EDO - - DEC A
Condition code settings:
2
OA
DECIMAL ADD
(Byte index 01 ignment)
mal operand or in the decimal accumulator, DECIMAL ADD
expands the effective decimal operand to 16 bytes (31 digits
plus sign) by appE~nding high-order O's, algebraically adds
the expanded decimal number to the contents of the entire
decimal accumulator, and then loads the sum into the decimal accumulator. If the result in the decimal accumulator
is zero, the resulting sign is forced to the positive form.
Overflow occursifthesum exceeds thecapacityof the decimal accumulator (i. e. , if the absolute value of the sum is equal
to or greater than 1031 ), inwhich case CC1 is reset to 0, CC2
is set to 1, and the instruction aborted with the previous contents of the decimal accumulator, CC3 and CC4 unchanged.
Affected: (DECA), CC
(DECA) + EDO DECA
Traps: Decimal arithmetic
Condition code settings:
2
3
4
0
0
instruction aborted
overflow
0
0
0
0
0
0
0
0
OS
Result in DECA
illegal digit or
sign detected
0
0
zero
)
negative
positive
3
4
0
If no i II ega I di git or sign is detected in the effecti ve dec i-
no illegal digit or sign
detected, no overflow,
instruction completed
DECIMAL SUBTRACT
(Byte index 01 ignment)
If no illegal digit or sign is detected in the effective decimal operand or in the decimal accumulator, DECIMAL SUBTRACT expands the effective decimal operand to 16 bytes
(31 digits plus sign) by appending high-order O's, algebraically subtracts the expanded decimal number from the contents of the entire decimal accumulaTor, and then loads the
difference into the decimal accumulator. If the result in the
decimal accumulator is zero, the resulting sign is forced to
the positive form.
Overfl ow occurs if the <:Ji fference exceeds the capac i ty of
the decimal accumulator (i.e., if the absolute value of the
difference is equal to or greater then 10 31 ), in which case
Traps: Decimal arithmetic
illegal digit or
sign detected
a
a a a a
a a a
a a
0
OM
Result in DECA
i nstructi on aborted
overflow
zero
negative
positive
} no illegal digit or sign detected, no overflow, instruction completed
DECIMAL MU LTIPL Y
(Byte index 01 ignment, continue after interrupt)
If no illegal digit or sign is detected in the effective dec imal operand and there is at least one decimal sign in the
decimal accumulator, DECIMAL MULTIPLY multiplies the
effective decimal operand (multiplicand) by the entire
contents of the decimal accumu~ator (multiplier) and then
loads th~ product into the decimal accumulator. If the
result in the decimal accumulator is zero, the resulting
sign is forced to the positive form.
No overflow can occur; how~ver, an indeterminate result
occurs (with an incorrect condition code indication, and
with no trap activation) if any of the following conditions
are not satisfied before the initial execution of DECIMAL
MULTIPLY:
1.
The 4 low-order bit positions of the decimal accumulator must contain the sign of the multiplier.
2.
The 16 high-order digit positions of the decimal accumulator (i .e., general registers 12 and 13) must contain
all O's.
3.
The effective decimal operand must not exceed 15 decimal digits (i. e., the value of L must not exceed 8).
This instruction can be interrupted during the course of its
exec;ution, and then be resumed, without producing an erroneous product (provided that the contents of the decimal
accumulator are not altered between the interruption and
continuation). Actually, the instruction is reexecuted,
but since there is no initializing phase, it begins with the
same iteration that was started prior to the interrupt.
Affected: (DECA), CC
(DECA) x EDO DECA
Traps: Decimal arithmetic
Condition code settings:
234
Result in DECA
illegal digit or sign detected, instruction aborted
Decimal Instructions
57
2
3
4
a a a a
a 0 a
a
a a
Result in DECA
zero
negative
positive
DC
} no illegal digit or sign
detected, i nstructi on
completed
DECIMAL DIVIDE
(Byte index al ignment, continue after interrupt)
DO
If there is no illegal digit or sign in the effe~tive decimal operand and if there is at least one decimal sign in
the dec imal accumulator, DECIMAL DIVIDE divides the
contents of the decimal accumulator (dividend) by the effective decimal operand (divisor). Then, if no overflow
has occurred, the computer loads the quotient (15 decimal
digits plus sign) into the 8 low-order bytes of the decimal
accumulator (registers 14 and 15), and loads the remainder
(also 15 decimal digits plus sign) into the 8 high-order bytes
of the dec imal accumulator (registers 12 and 13). The sign
of the remai nder is the same as that of the original dividend.
If the quotient is zero, the sign of the quotient is forced to
the positive form.
Overflow can occur if any of the following conditions are
not satisfied before the initial execution of DECIMAL
DIVIDE:
If there is no illegal digit or illegal sign in the effective
decimal operand or in the decimal accumulator, DECIMAL
COMPARE expands the effective decimal operand to 16
bytes (31 digits plus sign) by appending high-order OIS, algebraical Iy compares the expanded decimal number to the
contents of the entire dec imal accumulator, and sets CC3
and CC4 according to the result of the comparison (a positive zero compares equal to a negative zero).
The divisor must not be zero.
2.
The length of the divisor must not be greater than 15
decimal digits (i.e., the value of L must not exceed 8.)
3.
If the length of the dividend is greater than 15 decimal
digits, the absolute value of the significant di gits to
the left of the 15th digit position (i.e., those digits in
registers 12 and 13) must be less than the absolute value
of the divisor.
This instruction can be interrupted during the course of its
execution, and can then be resumed without producing an
erroneous result (provided that the contents of the decimal
accumulator are not altered between interruption and continuation). Actually, the instruction is reexecuted, but
since there is no initializing phase, it begins with the same
iteration that was started prior to the interrupt.
Condition code settings:
2
3
4
a
a
a a a a
a 0 a
0
a 0
a
58
zero quotient
I
negative quotient
positive quotient
Decimal Instructions
Result of comparison
I
illegal digit or sign detected, instruction
aborted
0
a
0
0
0
a
0
0
0
(DECA) equals EDO
(DECA) less than EDO
0
(DECA) greater than
EDO
no illegal digit
or sign detected,
instruction completed
DECIMAL SHIFT ARITHMETIC
(Byte index alignment)
Reference address
If no illegal digit or sign is detected in the decimal accumulator, DECIMAL SHIFT ARITHMETIC arithmetically shifts
the contents of the decimal accumulator (excluding the
decimal sign), with the direction and amount of the shift
determined by the effective virtual address of the instruction. If the result in the decimal accumulator is zero, the
resulting sign remains unchanged.
no illegal digit or
sign detected, no
overflow, instruction completed
The shift count, C, is treated as a 16-bit signed binary integer, with negative integers in twols complement form.
If the shift count is positive, the contents of the decimal
accumulator are shifted left C decimal digit positions; if
the shift count is negative, the contents ::If the decimal
Result in DECA
overflow
4
instruction aborted
Traps: Decimal arithmetic
illegal digit or
sign detected
3
If no indirect addressing or indexing is used with DSA, the
shift count C is the contents of bit positions 16-31 of the
instruction word. If only indirect addressing is used with
DSA, the shift count is the contents of bit positions 16-31
of the word pointed to by the indirect address in the
instruction word. If indexing only is used with DSA, the
shift count is the contents of bit positions 16-31 of the
instruction word plus the contents of bit positions 14-29
of the designated index register (bits 0-13, 30, and 31 of
the index are ignored). If indirect addressing and indexing
are both used with DSA, the shift count is the sum of the
contents of bit positions 16-31 of the word pointed to by
the indirect address and the contents of bit positions 14-29
of the designated index register.
Condition code settings:
2
Traps: Decimal arithmetic
Affected: CC
(DECA) : EDO
DSA
1.
Affected: (DECA), CC
(DECA)';- EDO DECA
DECIMAL COMPARE
(Byte index al ignment)
}
accumulator are shifted right -C decimal digit positions. In
either case, the decimal sign is not shifted, vacated decimal digit positions are filled with OIS, and any digits shifted
out of the decimal accumulator are lost, Although the range
of possible values for C is 2 -15 ~ C ~ 2 5_ 1, a shift account
greater than +31 or less than -31 is interpreted as a shift
count of exactly +31 or -31.
If any nonzero decimal digit is shifted out of the decimal
accumulator during a left shift, CC2 is set to 1; otherwise,
CC2 is reset to O. CC2 is unconditionally reset to 0 at the
completion of a right shift.
Affected: (DECA),
cc
3
4
o
o
o
o
o o
o
PACK
2
3
4
0
0
0
0
Result in DECA
0
0
illegal di git or sign detected, instruction
aborted
Example 1, L == 6:
negative
positive
right shift or no nonzero dir:;it shifted out
of DECA on I eft shi ft
no illegal digit
or sign detected,
instruction
completed
1 or more nonzero
digit{s) shifted out
of DECA on left shift
PACK DECIMAL DIGITS
(Byte index al ignment, continue after interrupt)
PACK DECIMAL DIGITS converts the effective decimal
operand (assumed t·o be in zoned format) into a packed
decimal number and, if necessary, appends sufficient highorder OIS to produce a decimal number that is 16 bytes (31
decimal digits plus sign) in length. The zone (bits 0-3) of
the low-orderdigitof the effective decimal operand is used
to select the sign code for the packed decimal number; all
other zones are ignored in forming the packed decimal
number. If no illegal digit or sign appears in the packed
decimal number, it is then loaded into the decimal accumulator. If the result in the decimal accumulator is zero,
the resulting sign remains unchanged.
The L field of this instruction specifies the length, in bytes,
of the resultant packed decimal number in the decimal accumulator; therefore, the length of the effective decimal operand is 2L-1 bytes (where L :-= 0 implies a length of 31 bytes
for the effective decimal operand).
This instruction can be interrupted during the course of its
execution, and can then be resumed without producing an
erroneous result {provided that the contents of the decimal
accumu lator are not .al tered between interruption and continuation}. Actually, the instruction is re-executed, but
Result in DECA
illegal digit or sign detected, instruction
aborted
0
0
o
o
Condition code settings:
0
zero
Traps: Decimal arithmetic
packed (EBL to EBL + 2L - 2 ) - DECA
0
o o
cc
Affected: (DECA),
Traps: Decimal arithmetic
Condition code setti ngs:
2
since there is no initializing phase, it begins with the
same iteration that was started prior to the interrupt.
zero
negati ve
0
positive
} no illegal digit or sign
detected, instruction
completed
Before exec uti on
After execution
EDO
X'FOFIF2F3
F4F5F6F7
F8F9FO I
X'FOF1 F2F3
F4F5F6F7
F8F9FO I
(DECA)
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
X'OOOOOOOO
00000000
00000123
4567890('
CC
xxxx
0010
Example 2, L = 6:
EDO
X'000938F7
E655B483
02Fl BOI
X'OO0938F7
E655B483
02Fl BOI
(DECA)
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
X'OOOOOOOO
00000000
00000987
6543210D I
CC
xxxx
0001
UNPK
UNPACK DECIMAL DIGITS
(Byte index al ignrnent, continue after interrupt)
If no illegal digit or sign is detected in the decimal accumulator (assumed to be in packed decimal format), UNPACK
DECIMAL DIGITS converts the contents of the low-order L
bytes of the decimal accumulator to zoned decimal format
and stores the result, as a byte string, from the effective byte
location to the effective byte location plus 2L-2. The contents of the 4 low-order bit positions of the decimal accumulator are used to select the sign code for the last digit of
the string; a zone of 1111 (XI FI) is used for all other digits.
The contents of the decimal accumulator remain unchanged,
and only 2L-l bytes of memory are altered. If the decimal
Decimal Instructions
59
accumulator contains more significant information than is
actually unpacked and stored, CC2 is set to 1; otherwise
eC2 is reset to O. If the result in memory is zero, the
resulting sign remains unchanged.
This instruction can be interrupted during the course of its
execution, and can then be resumed without producing an
erroneous result (provided that the contents of the decimal
accumu lator are not altered between interruption and conti nuation). Actually, the instruction is re-executed, but
since there is no initializing phase, it begins with the same
iteration that was started prior to the interrupt.
Affected: (EBl to EBl + 2l -2),
Cel, CC2
Traps: Decimal arithmetic
zoned (DECA)- EBl to EBl + 2l -2
Condition code settings:
2
o
3
4
Result of UNPK
o
illegal digit or sign detected, instruction
aborted
0
all significant information zoned and
stored
o
some significant
information not
zoned and stored
no illegal digit
or sign detected,
i nstructi on completed
Example 1, l = 10:
Before execution
After execution
(DECA)
X '00000000
00000001
23456789
0123456D'
X '00000000
00000001
23456789
0123456D'
EDO
xxx xxx xx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxx
X'FOFOFOF1
F2F3F4F5
F6F7F8F9
FOF1F2F3
F4F5D6'
ce
xxxx
OOxx
EDO
xxxxxxxx
xxxxxxxx
X'FOFOFOFl
FOFOC4'
CC
xxxx
01xx
BYTE -STRING INSTRUCTIONS
Five instructions provide for the manipulation of strings
of consecutive bytes. These instructions are standard
with the SIGMA 6 computer. The byte string instructions and their mnemonic codes are as follows:
Instruction Name
Mnemonic
Move Byte String
Compare Byte String
Translate Byte String
Translate and Test Byte String
Edit Byte String
MBS
CBS
TBS
TTBS
EBS
These instructions are in the immediate displacement class,
are memory-to-memory operations, and proceed one byte
at a time (except for the instruction MOVE BYTE STRING,
which proceeds four bytes at a time under certain conditions). These operations are under the control of information that must be loaded into certain general registers before
the instruction is executed; hence, they may be interrupted
after any individual byte operation. The general format for
the information in the instruction word and in the general
registers is as· follows:
Instructi on word:
Contents of register R:
Contents of reg i ster Ru 1:
Example 2, l = 8:
(DECA) =
EDO
ee
X '00000000
23000000
10001234
0012345C'
X '00000000
23000000
10001234
0012345C'
xxxxxx.xx
xxxxxxxx
xxxxxxxx
xxxxxx
X'F1FOFOFO
F1F2F3F4
FOFOF1F2
F3F4C5'
xxxx
01xx
Example 3, l = 4:
(DECA) =
60
X '00001 001
00001002
00001003
0001004F'
Byte-String Instructions
X'00001001
00001002
00001003
0001004F'
Designation
Function
Operation
The 7-bit operation code of the instruction. (If any byte string instruction is
indirectly addressed, the computer traps
to location X'40' at the time of operation code decoding. )
R
The 4-bit field that identifies register R
of the current general register bank.
Displacement
A 20-bit field that contains a signed byte
displacement value, used to form an effecti ve byte address. The displacement
value is right-justified in the 20-bit fiel # # 035 END
The new condition code is: 1011
Fxampl e 2, before execution:
The initial conditions are identical to example 1, except
that the contents of the decimal information field are:
06 54 32 1Example 2, after execution:
The instruction word and the decimal field are unchanged
The new contents of registers 6 and 7 are identical to those
given for example 1
The new contents of the destination byte string are
*6,543.2115CR
The new contents of register 1 are: X 'xxx020l3'
PUSH-DOWN INSTRUCTIONS
The term "push-down processing" refers to the programming
technique (used extensively in recursive routines) of storing
the context of a calculation in memory, proceeding with a
new set of information, and then activating the previously
stored information. Typically, this process involves a reserved area of memory (stack) into which operands are
pushed (stored) and from which operands are pulled
{loaded} on a lost-in, first-out basis. The SIGMA 6 computer
Push-Down Instructions
67
provides for simplified and efficient programming of pushdown processing by means of the following instructions:
Instruction Name
Mnemonic
Push Word
Pull Word
Push Multiple
Pull Multiple
Modify Stack Poi nter
PSW
PLW
PSM
PLM
MSP
However, this trap action can be selectively inhibited by
setting either (or both) of the trap inhibit bits in the SPD to 1.
Bit position 32 of the SPD, referred h as the trap-on-spac8
(TS) inhibit bit, determines whether 0\ not the computer is
to trap to location X'421 as a result of impending overflow
or underflow of the space count (SPD33-47), as follows:
TS
Space count overflow/underflow action
o
If the execution of a pull instruction would cause the
space count to exceed 2 15 -1, or if the execution of a
push instruction would cause the space count to be less
than 0, the computer traps to location X'421 with the
condition code unchanged.
STACK POINTER DOUBLEWORD
Each of these instructions operates with respect to a memory
stack that is defined by a doubleword located at the effective address of the instruction. This doubleword, referred
to as a stack pointer doubleword (SPD), has the following
structure:
Instead of trapping to location X'42', the computer
sets CCl to 1 and then executes the next instruction
in sequence.
Bit position 48 of the SPD, referred to as the trap-on-word
(TW) inhibit bit, determines whether or not the computer is
to trap to location X'42' as a result of impending overflow
or underflow of the word count (SPD49-63)' as follows:
TW Word count overflow/underflow action
o
Bit positions 15 through 31 of the SPD contain a 17-bit address field that points to the location of the word currently
at the top (highest-numbered address) of the operand stack
in a push operation, the top-of-stack address is incremented
by 1 and then an operand in a general register is pushed
(stored) i~to that'location, thus becoming the contents of
the new top of the stack; the contents of the previous top of
the stack remain unchanged. In a pull operation, the contents of the current top of the stack are pulled (loaded) into
a general register and then the top-of-stack address is decremented by 1; the previ ous contents of the stack remain unchanged.
Bit positions 33 through 47 of the SPD, referred to as the
space count, contai n a 15-bit count (0 to 32,767) of the
number of word locations currently available in the region
of memory allocated to the stack. Bit positions 49 through
63 of the SPD, referred to as the word count, contai n a 15bit count (0 to 32,767) of the number of words currently in
the stack. In a push operation, the space count is decremented by 1 and the word count is incremented by 1; ina
pull operation, the space count is incremented by 1 and the
word count is decremented by 1. At the beginning of all
push-down instructions, the space count and the word count
are each tested to determi ne whether or not the i nstructi on
would cause either count field to be incremented above the
upper I imit of 2 15 -1 (32,767), or to be decremented below
the lower limit of O. If execution of the push-down instruction would cause either count limit to be exceeded, the
computer unconditionally aborts execution of the instruction, with the stack, the stack pointer doubleword, and the
contents of general registers unchanged. Ordinarily, the
computer traps to location X ' 42 1 after aborting a push-down
instruction because of impending stack limit overflow or
underflow, and with the condition code unchanged from the
value it contained before execution of the instruction.
68
Push-Down Instructions
If the execution of a push instructi on would cause the
word count to exceed 2 15 _1, or if the execution of a
pull instruction would cause the word count to be less
than 0, the computer traps to location X'421 with the
condition code unchanged.
Instead of trapping to location X ' 42 1, the computer
sets CC3 to 1 and then executes the next instruction
in sequence.
PUSH-DOWN CONDITION CODE SETTINGS
If the execution of a push-down instruction is attempted and
the computer traps to location X ' 42 1, the condition code remains unchanged from the value it contained immediately
before the instruction was executed.
If the execution of a push-down instruction is attempted and
the instruction is aborted because of impending stack limit
overflow or underflow (or both) but the push-down stack
limit trap is inhibited by one (or both) of the inhibits (TS
and TW), then, eCl or CC3 is set to 1 (or both are set to
lis) to indicate the reason for aborti ng the push-down i nstruction, as follows:
2
3
o
4
Reason for abort
impending overflow of word count on a
push operation or impending underflow
of word count on a pull operation. The
push-down stack limit trap was inhibi ted
by the TW bit (SPD 48)
o
impending overflow of space count on a
pull operation or impending underflow
of space count on a push operation. The
push-down stack limit trap was inhibited
by the TS bit (SPD )
32
2
3
4
Reason for abort
impending overflow of word count and
underflow of space count on a push operation or impending overflow of space
count and underflow of word count on
a pull operation. The push-down stack
limit trap was inhibited by both the TW
and the TS bits
4.
The condition code is set to reflect the new status of
the space count.
Affected: (SPD), (TSA+1),
CC
(SPD)15_31 + 1 - - SPD 15 _ 31
(R) -
(SPD
_ )
15 31
(SPD)33_47 - 1 - - SPD 33 _47
If a push-down instruction is successfully executed, CC1
(SPD)49-63 + 1 -
and CC3 are reset to 0 at the completion af the instruction.
Also, CC2 and CC4 are independently set to indicate the
current status of the space count and the word count, respectivel y, as follows:
Condition code settings:
2
3
4
------o
0
o
Status of space and word counts
the current space count and the current
word count are both greater than zero
the current space count is greater than
zero, but the current word count is zero,
indicating that the stack is now empty.
If the next operation on the stack is a
pull instruction, the instruction wi II be
aborted
o
0
Result of PSW
0
0
0
space count is greater
than 0
0
0
space count is now 0
0
word count = 2 15 _1,
TW = 1
0
space count
TS = 1
0
0
PUSH WORD
(Doubleword index al ignment)
PUSH WORD stores the contents of register R into the pushdown stack defined by the stack pointer doubleword located
at the effective doubleword address of PSW. If the push
operation can be successfully performed, the instruction
operates as follows:
The current top-of-stack address (SPD15-31) is incremented by 1, to point to the new top-of-stack
location.
2.
The contents of register R are stored in the location
poi nted to by the new top-of-stack address.
3.
The space count (SPD33-47) is decremented by 1 and
the word count (SPD49-63) is incremented by 1.
I
instruct i on
completed
= 0,
space count = 0, word
count = 0, TS = 1
°
PlW
1.
4
0
If the computer does not trap to location X 1421 as a result
PSW
3
0
0
SPD 49-63
2
the currert word count is greater than
zero, but the current space count is zero,
indicating that the stack is now full. If
the next operation on the stack is a push
i nstructi on, the i nstructi on wi II be aborted
of impending stack limit overflow/underflow, CC2 and
CC4 indicate the status of the space and word counts at
the termination of the push-down instruction, regardless
of whether or not the space and word counts were actually
modified by the instruction. In the following descriptions
of the push-down instruction, only those condition codes
are given that can actual I y be produced by the instruction,
provided the computer does not trap to location X1421.
Trap: push-down stack limit
instruction
aborted
word count = 2 15 _1,
space count = 0,
TW = 1, and TS=l
PULL WORD
(Doubleword index alignment)
PULL WORD loads register R with the word currently at the
top of the push-down stack defined by the stack pointer
doubleword located at the effective doubleword address of
PLW. If the pull operation can be performed successfully,
the instruction operates as follows:
1.
Register R is loaded with the contents of the location
pointed to by the current top-of-stack address
(SPD 15-31).
2.
The current top-of-stack address is decremented by 1,
to point to the new top-of-stack location.
3.
The space count (SPD33-47) is incremented by 1 and
the word count (SPD49-63) is decremented by 1.
4.
The condition code is set to reflect the status of the
new word count.
Affected: (SPD), (R), CC
((SPD)15_31) (SPD)33_47 + 1 -SPD
Trap: Push-down stack limit
Ri (SPD)15_31 -1 SPD 33 _4 i
SPD 15 _ 31
(SPD 49-63- 1
49 63
Push-Down Instructions
69
Condition code settings:
0
2
3
4
Result of PLW
0
0
0
word count is greoter
than 0
0
0
0
0
0
I
word count is now 0
Condition code settings:
instruction
completed
2
3
4
Resu I t of PSM
°
0
0
0
spoce count>
0
0
space count =
0
0
0
word count + ec> 2 15 _1,
TW = 1
0
space count 2 15 _1,
TS = 1, and TW = 1
0
space count = 0, TS = 1
OB
i
2
PUSH MULTIPLE stores the contents of a sequential set of
general registers into the push-down stack defined by the
stack pointer doubleword located at the effective doubleword address of PSM. The condition code is assumed to
contai n a count of the number of regi sters to be pushed i nto the stack. (An initial value of 0000 for the condition
code specifies that all 16 general registers are to be pushed
into the stack.) The registers are treated as a circular set
(with register 0 following register 15) and the first register
to be pushed into the stack is register R. The last register
to be pushed into the stack is register R+ CC -1, and the
contents of this register become the contents of the new
top-of-stack location.
If there is sufficient space in the stack for all of the specified registers, PSM operates as follows:
1.
The contents of registers R to R+ CC -1 are stored in
an ascending sequence, beginning with the location
pointed to by the current top-of-stack address
(SPD15-31) plus 1 and ending with the current topof-stack address pi us Cc.
2.
The current top-of-stack address is incremented by the
value of CC, to point to the new top-of-stack location.
3.
The space count (SPD 33 - 47 ) is decremented by the
value of CC and the word count is incremented by
the value of CC.
4.
space count = Of word
count + ec > 2 5-1,
TS = 1, and TW = 1
If the instruction starts storing words into an accessible region of memory and then crosses into an inaccessible memory
region, either the memory protection trap or the nonexistent
memory address trap can occur. In ei ther case, the trap is
activated with the condition code unchanged from the val ue
it contained before the execution of PSM. The effective address of the instruction permits the trap routine to compute
how many words of memory have been changed. Since it is
permissible to use indirect addressing through one of the affected locations, or even to execute an instruction located
in one of the affected locations; a trapped PSM instruction
may have already overwritten the direct address, or the
PSM instruction itself, thus destroying any possibility of
continuing the program successfully. If such programming
must be done, it is advisable that the direct address, or the
PSM instruction, occupy the last location in which the contents of a register are to be stored by the PSM instruction.
If the address of the elements within the stack (pointed to
by the top-of-stack address) is in the range 0 through 15,
then the registers indicated by the R field of the PSM instruction are stored in the general registers rather than in
core memory. In this case the results wi /I be unpredictable
if any source registers are also used as destination registers.
PLM
PULL MULTIPLE
(Doubleword index alignment)
The condition code is set to reflect the new status of
the space count.
Affected: (SPD), (TSA+1)to
(TSA+CC), CC
Trap: Push-down stack limit
(R)-(SPD)15_31 + 1 ... (R+CC-l)-(SPD)15_31+ CC
(SPD)15_31+ CC (SPD )33-47- CC -
SPD 15 _31
SPD 33_47
(SPD)49_63+CC-SPD 49-63
70
instruction
aborted
space count = 0, word
count = 0, TS = 1
0
o
instruction
completed
space count 0
= 0,
TW
=1
space count = 0, word
count 2 -1,
TS = 1
15
space count + CC >2 -1,
word count 2 -1,
word count = 0, TS = 1,
and TW = 1
Bit positions 16 through 31 of register R are treated as a
signed integer, with negative integers in f"'NCls complement
form (i. e., a fixed-point halfword). The modifier is algebraicallyadded to the top-of-stack address, subtracted from
the space count, and added to the word count in the stack
pointer doubleword. If, as a result of MSP, either the space
count or the word count would be decreased below 0 or increased above 2 15 _1, the instruction is aborted. Then, the
computer either traps to location X ' 42 1 or sets the condition
code to refl ect the reason for aborti ng, dependi ng on the
stack limit trap inhibits.
If the modification of the stack pointer doubleword can be
successfully performed, MSP operates as follows:
instruction
aborted
If the instruction starts loading from an existent region of
memory and then crosses a memory page boundary into an
inaccessible memory region, either the memory protection
trap or the nonexistent' memory address trap can occur. In
either case, the trap is activated with the condition code
1.
The modifier in register R is algebraically added to the
current top-of-stack address (SPD}J 5-31, to poi nt to a
new top-of-stack location. (If the modifier is negative,
it is extended to 17 bits byappending a high-order 1.)
2.
The modifier is algebraically subtracted from the current space count (SPD 33 - 47 ) and the result becomes
the new space count.
3.
The modifier is algebraically added to the current word
count {SPD49-63} and the result becomes the new word
count.
4.
The condition code is set to reflect the new status of
the new space count and new word count.
Affected: (SPD), CC
Trap: Push-down stack limit
Push-Down Instructions
71
computer traps to location X '40 ' if the actual address of
the instruction is nonexistent or instruction-access protected. If the instruction address ;s existent and is
not instruction-access protected, tht: instruction is accessed and the instruction address portion of the program
status doubleword is incremented by 1, so that it now contains the virtual address of the next instruction in sequence
(referred to as the updated instruction address).
(SPD)15_31 + (R)16-31SE -SPD 15 _ 31
(SPD)33_47 - (R)16-31 - - SPD 33 _47
(SPD)49_63 + (R)16-31 -
SPD 49-63
Condition code settings:
2
3
4
a a a a
Result of MSP
space count > 0,
word count> 0
a
space count> 0,
word count = 0
a
a a
space count:::: 0,
word count> 0
a
a
space count = 0,
word count = 0,
modifier = a
a
0
instruction
completed
If CC1, or CC3, or both CC1 and CC3 are lis after execution of MSP, the instruction was aborted but the pushdown stack limit trap was inhibited by the trap-an-space
inhibit (SPD32), by the trap-on-word inhibit (SPD48), or
both. The condition code is set to reflect the reason for
aborting as follows:
2
3
4
Status of space count and word count
a
word count > 0
word count
a
o =::
If a trap condition occurs during the execution sequence of
any instruction, the computer decrements the updated instruction address by 1 and then traps to the location assigned
to the trap condition. If neither a trap condition nor a
satisfied branch condition occurs during the execution of an
instruction, the next instruction is accessed from the location
pointed to by the updated instruction address. Ifa satisfied
branch condition occurs during the execution of a branch
instruction (and no trap condition occurs), the next instruction is accessed from the location pointed to by the effective address of the branch instruction. Thus, during execution of a branch instruction, the updated instruction address
is decremented, unchanged, or replaced, as determi ned by
the following critera:
1.
=0
a
space cou nt
>0
space count
=0
a =::
space count - modifier =:: 2 15 -1
space count - modifier < 0, and TS = 1
or space count - modifier> 215 -1
TS = 1
The branch instruction is indirectly addressed, but
the address of the location containing the direct
address is either nonexistent or unavailable to the
slave program for read access.
b.
The branch instruction is unconditional (or the
branch is conditional and the condition for the
branch is satisfied), but the effective address of
the branch instruction is unavailable to the slave
program for instruction access.
c.
The effective address of any branch instruction
{conditional or unconditional} is nonexistent.
If any of the above situations occur, the computer
aborts execution of the branch instruction, decrements
the updated instruction address by 1, and traps to location X1401. In this case, the instruction address value
(IA) stored by the XPSD instruction in location X I 40 1 is
the address of the aborted branch instruction.
EXECUTE/BRANCH INSTRUCTIONS
The EXECUTE instruction can be used to insert another instruction into the program sequence, and the branch instructions can be used to alter the program sequence, either
unconditionally or conditionall y. If a branch is unconditiona (or conditional and the branch condition is satisfied),
the instruction pointed to by the effective address of the
branch instruction is normally the next instruction to be
executed. If a branch is conditional and the condition for
the branch is not satisfied, the next instruction is normall y
taken from the next location, in ascending sequence, after
the branch instruction.
Prior to the time that an in~truction is accessed from memory
for execution, bit positions 15-31 of the program status
doubleword contain the virtual address of the instruction,
referred to as the instruction address. At this time, the
72
a.
word count + modifier =:: 2 15 _1
word count + modifier < 0, and TW = 1
or word count + modifier> 215 _1 and
TW = 1
a
Trap condition. A nonal/owed operation trap condition
can occur during execution of a branch instruction, but
onl y if an attempt is made to access ei ther a nonexistent memory address or an address that is not avai I abl e
to the slave program for instruction access. The trap
condition occurs in the following situations:
Execute/Branch Instructions
2.
No branch condition. If the branch instruction is conditional, the condition for the branch is not satisfied,
and no trap condition occurs, the updated instruction
address remains unchanged. Then, instruction execution proceeds with the instruction pointed to by the
updated instruction address.
3.
Branch condition. If the branch instruction is unconditional (or if the branch instruction is conditional and
the condition for the branch is satisfied) and no trap
condition occurs, the updated instruction address is
replaced by the effective virtual address of the branch
instruction. Then, instruction execution proceeds with
the instruction pointed to by the effective virtual address of the branch instruction.
EXU
Affected: (IA) if CC n RIO
EXECUTE
\.Word index alignment)
If CC n (1)8_11 /0, EVA
If CC n (1)8-11
EXECUTE causes the computer to access the instruction in
the location pointed to by the effective address of EXU and
execute the subject instruction. The execution of the subject instruction, including the processing of trap and interrupt conditions, is performed exactly as if the subject
instruction were initially accessed instead of the EXU instructi on. If the subj ect instruction is another EXU, the
computer executes the subject instruction pointed to by the
effective address of the second EXU as described above.
Such "chains" of EXECUTE instructions may be of any length,
and are processed (without affecting the updated instruction
address) until an instruction other than EXU is encountered.
After the final subject instruction is executed, instruction
execution proceeds with the next instruction in sequence
after the initial EXU (unless the subject instruction is an
LPSD or XPSD instruction, or is a branch instruction and
the branch condition is satisfied).
If an interrupt activation occurs between the beginning of
an EXU instruction (or chain of EXU instructions) and the
last interruptible point in the subject instruction, the computer processes the interrupt-servicing routine for the active interrupt I evel and then returns program control to the
EXU instruction (or the intial instruction of a chain of
EXU instructions), which is started anew. Note that a program is interruptible after every instruction access, including accesses made with the EXU instruction, and the interruptibility of the subject instruction is the same as the
normal interruptibility for that instruction.
If a trap condition occurs between the beginning of an EXU
instruction (or chain of EXU instructions) and the completion
of the subject instruction, the computer traps to the appropriate trap location. The instruction address stored by the
XPSD instruction in the trap location is the address of the
EXU instruction (or the initial instruction of a chain of
EXU instructions).
Affected: Determi ned by
subject instruction
Traps: Determined by
subject instruction
Condition code settings: Determined by subject instruction
BCS
BRANCH ON CONDITIONS SET
(V%rd index alignment)
BRANCH ON CONDITIONS SET forms the logical product
(AND) of the R field of the instruction word and the current
condition code. If the logical product is nonzero, the
branch condition is satisfied and instruction execution proceeds with the instruction pointed to by the effective address of the BCS instru~tion. However, if the logical
product is zero, the br:anch condition is unsatisfied and
instruction execution then proceeds with the next instruction in normal sequence.
= 0,
_ --- IA
15 31
IA not affected
If the R field of BCS is 0, the next instruction to be executed after BCS is always the next instruction in ascending
sequence, thus effectively producing a "no operation"
instruction.
BCR
BRANCH ON CONDITIONS RESET
N'/ord index alignment)
BRANCH ON CONDITIONS RESET forms the logical product (AND) of the R field of the instruction word and the
current condition code. If the logical product is zero, the
branch condition is satisfied and instruction execution then
proceeds with the instruction pointed to by the effective address of the BCR instruction. However, if the logical product is nonzero, the branch condition is unsatisfied and instruction execution then proceeds with the next instruction
in normal sequence.
Affected: (IA) if CC n R = 0
If CC n (1)8-11 = 0, EVA 15 _ 31
IF CC n (1)8-11
10,
IA
IA not affected
If the R field of BCR is 0, the 'next instruction to be executed after BCR is always the instruction located at the effective address of BCR, thus effectively producing a "branch
unconditional! y" instruction.
BIR
BRANCH ON INCREMENTING REGISTER
N'/ord index alignment)
BRANCH ON INCREMENTING REGISTER computes the
effective virtual address (EVA) and then increments the
contents of general regi ster R by 1. If the resul t is a negative value, the branch condition is satisfied and instruction
execution then proceeds with the instruction pointed to by
the effective address of the BIR instruction. However, if
the result is zero or a positive value, the branch condition
is not satisfied and instruction execution proceeds with the
next instruction in normal sequence.
Affected: (R), (IA)
(R) + 1 - R
If (R)O = 1, EVA 15 - 31 - I A
If (R)O
= 0,
IA not affected
If the effective address of BIR is unavailable to the slave
program for instruction access and the branch condition is
satisfied, or if the effective address of BIR is nonexistent,
Execute/Branch Instructions
73
the computer aborts execution of the BIR instruction and
traps to location X'40'. In this case, the instruction address
stored by the XPSD instruction in location X ' 40 ' is the virtual address of the aborted BIR instruction. If the computer
traps because of instruction access protection, register R will
contain the value that existed just before the BIR instruction.
the computer aborts execution of the BAL instruction (after
loading the updated instruction address into register R) and
traps to location X 140'. In thi s case, the instruction address stored by the XPSD instruction in location X ' 40 ' is
the virtual address of the BAL instruction.
BRANCH ON DECREMENTING REGISTER
0/Vord index alignment)
BDR
CALL INSTRUCTIONS
Each of the four call instructions causes the computer to
trap to a specific location for the next instruction in sequence. The four cal I instructions, their mnemonics, and
the locations to which the computer traps are:
BRANCH ON DECREMENTI NG REGISTER computes the
effective virtual address (EVA) and then decrements the
contents of general register R by 1. If the result is a positi ve val ue, the branch condition is satisfied and instruction
execution then proceeds with the instruction pointed to by
the effective address of the BDR instruction. However, if
the result is zero or a negative value, the branch condition
is unsatisfied and instruction execution proceeds with the
next instruction in normal sequence.
Affected: (R), (IA)
(R) - 1 - R
If (R)O
=0
if (R)O
= 1 or
and (R)1-31 ,0, EVA 15 -31 (R)
= 0,
IA
IA not affected
If the effective address of BDR is unavailable to the slave
program for instruction access and the branch condition is
satisfied, or if the effective address of BDR is nonexistent,
the computer aborts execution of the BDR instruction and
traps to location X ' 40 ' • In this case, the instruction address
stored by the XPSD instruction in location X' 40 ' is the virtua I address of the aborted BDR instruction. If the computer
traps because of instruction access protection, register R will
contain the value that existed just before the BDR instruction.
BAl
BRANCH AND LINK
0/Vord index alignment)
BRANCH AND LINK determines the effective virtual address, loads the updated instruction address (the virtual address of the next instruction in normal sequence after the
BAL instruction) into bit positions 15-31 of general register R, clears bit positions 0-14 of register R to Dis and then
replaces the updated instruction address with the effective
virtual address. Instruction execution proceeds with the
instruction pointed to by the effective address of the BAL
instruction.
Affected: (R), (IA)
Instruction Name
Mnemonic
Trap Location
CALL
CALL
CALL
CALL
CAll
CAL2
CAL3
CAL4
X ' 48 1
X ' 49 1
X '4A '
X ' 4B '
1
2
3
4
Each of these four trap locations must contain an EXCHANGE
PROGRAM STATUS DOUBLEWORD (XPSD) instruction. Execution of XPSD in the trap location for a call instruction is
described under the XPSD instruction. If the XPSD instruction is coded with bit position 9 set to 1, the next instructi on (executed after the XPSD) is taken from one of 16 possible locations, as designated by the value in the R field of
the call instruction. Each of the 16 locations may contain
an i nstructi on that causes the computer to branch to a specific routine; thus, the four call instructions can be used to
enter any of as many as 64 unique routines.
CAll
CALL 1
(Word index alignment)
CALL 1 causes the computer to trap to location X 148 1 •
CAl2
CALL 2
0/Vord index alignment)
CALL 2 causes the computer to trap to location X'49 1.
CAl3
o
I
CALL 3
(Word index alignment)
2
CALL 3 causes the computer to trap to location X'4A'.
CAl4
CALL 4
0/Vord index alignment)
If the effective address of BAL is either nonexistent or is
unavai labl e to the slave program for instruction access,
74
Call Instructions
CALL 4 causes the computer to trap to location X '4B '.
CONTROL INSTRUCTIONS
1.
If bit position S (LP) of LPSD contains a 1, bits 55
through 59 of th e current program status doubl eword
(register pointer) are replaced by bits 55 through S9
of the effective doublewordi if bit S of LPSD is a 0,
the current register pointer value remains unchanged.
2.
If bit position 10 (CL) of LPS D contains a 1, the
highest-priority interrupt level currently in the active
state is cleared (i. e., reset to either the armed state
or the disarmed state); the interrupt level is armed if
bit 11 of LPSD (AD) is a 1, or is disarmed if bit 11 of
LPSD is O. If bit 10 of LPSD is a 0, no interrupt level
is affected in any way, regardless of whether bit 11
of LPSD is 1 or O. (Interrupt levels are described in
detail under "Interrupt System" in Chapter 2.
The following privileged instructions are used to control
the basic operating conditions of the SIGMA 6 computer:
Instruction Name
Mnemonic
Load Program Status Doubl eword
Exchange Program Status Doubl eword
Load Register Pointer
Move to Memory Control
Wait
Read Direct
Write Direct
LPSD
XPSD
LRP
MMC
WAIT
RD
WD
If execution of any control instruction is attempted while
the computer is in the slave mode (i.e., while bit 8 of the
current program status doubl eword is a 1), the computer unconditionally aborts execution of the instruction (at the time
of operation code decoding) and traps to location X'40'.
PROGRAM STATUS OOUBl£WORD
The SIGMA 6 program status doubleword has the following
structure when stored in memory:
Those portions of the effective doubleword that correspond
to undefined fields in the program status doubleword are
ignored.
Affected: (PSD), interrupt system if (1)10 = 1
ED _ CC; ED _ FS, FZ, FN
5 7
O3
EDS-MS; ED --MM
9
ED
10
- - DM; ED
11
-
AM
Bit
DesigPosition nation Function
_ IAi ED _
-WK
34 35
15 31
ED _ CI, II, Eli If (I)S = 1, ED _ RP
55 59
37 39
If (1)10 = 1 and (1)11 = 1, clear and arm interrupt
0-3
If (1)10 = 1 and (1)11 = 0, c1~ar and disarm interrupt
ED
5
6
7
8
9
CC
FS
FZ
FN
MS
MM
10
OM
11
15-31
34,35
37
AM
IA
WK
CI
38
II
,39
1 ·55-59
EI
RP
Condition code
Floating significance mask
Floating zero mask
Floating normalize mask
Master/Slave mode control
Memory Map mode control
Decimal arithmetic trap mask
Fixed-point arithmetic overflow trap mask
Instruction address
Write key
Counter interrupt group inhibit
I/O interrupt group inhibit
External interrupt inhibit
Register pointer
The detai led functions of the various portions of the SIGMA 6
program status doubleword are described under II Program
Status Doubleword" in Chapter 2.
LPSD
XPSD
EXCHANGE PROGRAM STATUS DOUBLEWORD stores the
entire program status doubleword and then replaces the current program status doubleword with a new program status
doubleword.
Use of the memory map in interpreting the XPSD instruction
address depends on the combined settings of bit 9 of the
current PSD and bit 10 of the XPSD instruction, and on
whether or not the XPSD is executed in an interrupt or trap
location as the result of an interrupt or trap:
1.
If the XPSD instruction is executed in an interrupt or
trap location, the map is used to interpret the indirect
reference address and the effective address if, and only
if, a 1 is contained in bit positions 9 (MM) of the current PSD and 10 (MP) of XPSD.
2.
The same logic applies with one exception when the
instruction is not executed in an interrupt or trap location. The exception is that if the program is in the
mapping mode (PSD 9 = 1), the map is used to interpret
the indirect reference address regardless of the state
of XPSD lO •
LOAD PROGRAM STATUS DOUBLEWORD
(Doubleword index alignment, privileged)
LOAD PROGRAM STATUS DOUBLEWORD replaces bits 0
through 39 of the current program status doubleword with
bits 0 through 39 of the effective doubleword. The following conditional operations are also performed:
EXCHANGE PROGRAM STATUS DOU BLEWORD
(Doubleword index alignment, privileged)
Control Instructions
75
and bits 37 through 39 of the second effective doubleword.
These conditions are summarized in the truth table shown
below. General information on memory addressing is contained in Chapter2 under "Memory Control Storage", "Memory Reference Addresses", and IIMemory Address Control II.
XPSD 10
PSD9
1
1
0
1
0
0
XPSD Address Type
Map?
Ind. Ref. Addr.
Effect. Addr.
Ind. Ref. Addr.
Effect. Addr.
Ind. Ref. Addr.
Effect. Addr.
Ind. Ref. Addr.
Effect. Addr.
yes
yes
no
no
no
no
no
no
Bit
Position Designation
Function
37
CI
Counter interrupt inhibit
38
II
VO
39
EI
External interrupt inhibit
interrupt inhibit
If any (or all) of bits 37, 38, or 39 of the second effective doubleword are OIS, the corresponding bits in the
current program status doubleword remain unchanged;
if any (or all) of bits 37, 38, or 39 of the second effective doubleword are ]Is, the corresponding bits in the
current program status doubl eword are set to lis. See
page 19 for a detai I ed discussion of the interrupt inhibits.
I yes t
tllYes li only if XPSD not executed in an interrupt or
trap location.
4.
The current program status doubleword is stored in the doubleword location pointed to by the effective address of XPSD
in the following form:
If bit position 8 (LP) of XPSD contains a I, bits 55-59 of
the current program status doubleword (register pointer)
are replaced by bits 55 through 59 of the second effective doubleword; if bit 8 of XPSD is a 0, the current
register pointer value remains unchanged.
The following additional operations are performed on the new
program status doubleword if, and only if the XPSD is being
executed as the result of a nonallowed operation (trap to location X'40') or a call instruction (trap to location X'48',
X 149 1, X'4A', or XI4BI):
The current program status doubleword is replaced by a new
program status doubleword as follows:
1.
2.
3.
76
The effective address of XPSD is incremented by 2, so
that it points to the next doubleword location. The address thus generated is subject to the same mapping consideration as the original effective address {i.e., mapping
is performed with the new address if bit 10 of XPSD is
,a 1 and bit 9 of the current program status doubl eword
is also a 1; otherwise, mapping is not performed}. The
contents of the next doubleword location are referred
to as the second effective doubleword, or ED2.
1.
Nonallowed operations - the following additional functions are performed when XPSD is being executed as a
resul t of a trap to location X1 40 1 :
a.
Nonexistent instruction - if the reason for the trap
condition is an attempt to execute a nonexistent instruction, bit position 0 of the new program status
doubleword (CC I) is set to 1. Then, if bit 9 (AI)
of XPSD is a I, bit positions 15-31 of the new program status doubleword (next instrucHon address)
are incremented by 8.
b.
Nonexistent memory address - if the reason for the
trap condition is an attempt to access or write into
a nonexistent memory region, bit position 1 of the
new program status doubl eword (CC2) is set to 1.
Then, if bit 9 of XPSD is a I, the instruction address portion of the new program status doubl eword
is incremented by 4.
c.
Privileged instruction violation - if the reason for
the trap condition is an attempt to execute a privileged instruction while the computer is in the slave
mode, bit position 2 of the new program statusdoubleword (CC3) is set to 1. Then, if bit position 9 of
XPSD is 1, the instruction address portion of the new
program status doubleword is incremented by 2.
d.
Memory protection violation - if the reason for the
trap condition is an attempt to read from or write into
a memory reg ion to wh i ch the program does not have
proper access, bit position 3 of the new program status
doubleword (CC4) is set to 1. Then, if bit 9 of XPSD
is a 1, the instruction address portion of the new
program status doubleword is incremented by 1.
Bits 0 through 35 of the current program status doubleword are unconditionally replaced by bits 0 through 35
of the second effective doubl eword. The affected portions of the program status doubleword are:
Bit
Position Designation
Function
0-3
CC
Condition code
5-7
FS, FZ, FN
Floating control
8
MS
Master/slave mode control
9
MM
Mapping mode control
10
DM
Decimal arithmetic trap mask
11
AM
Fixed-point arithmetic trap mask
15-31
IA
Instruction address
34-35
WK
'Write key
A logical inclusive OR is performed between bits 37
through 39 of the current program status doubleword
Control Instructions
There are certain circumstances under which two of the
above nonal/owed operations can occur simultaneously.
The following operation codes (including their counterparts) are considered to be both nonexistent and privileged: XIOC, XIOD I, XI2C, and XI2DI. If any one of
these operation codes is used as an instruction while
the computer is in the slave mode, CC 1 and CC3 are
both set to lis; if bit 9 of XPSD is a 1, the instruction
address portion of the new program status doubl eword is
incremented by 10. If an attempt is made to access or
write into a memory region that is both nonexistent and
prohibited to the program by means of the memory control feature, CC2 and CC4 are both set to lis; if bit 9
of XPSD is a 1, the instruction address of the new program status doubleword is incremented by 5.
2.
C::III instructions - the following additional functions
are performed when XPSD is being executed as a resu It
of a trap to location X' 48 1 , X 1 49 1, XI4AI, or XI4BI:
a:
The R field of the call instruction causing the
trap is logically inclusively ORed into bit positions 0-3 (CC) of the new PSD.
b.
If bit position 9 of XPSD contains a 1, the R field
of the call instructi-:>n causing the trap is added
to the instruction address portion of the new PSD.
If bit position 9 of XPSD contains a 0, the instruction address portion of the new PSD always remains at the value
establ ished by the second effective doubleword. Bit position 9 of XPSD is effective only if the instruction is being
executed as the resul t of a nonall owed operati on trap or a
call instruction trap. Bit position 9 of XPSD must be coded
with a 0 in all other cases; otherwise, the resul ts of the
XPSD instruction are undefined.
Affected: (EDL), (PSD)
If (I) 10
= 1,
effect i ve address is vi rtua I
If (1)10 = 0, effective address is actual
PSD-EDL
ED2 0 _ 3 ED28 -
CC; ED25_7 MS; ED29 -
FS, FZ, FN
MM
WK
34 _35 ED2 37 _39 u CI, II, EI - C I , II, EI
If (1)8 = 1, ED255 _ RP
59
IA; ED2
If (1)8 = 0, RP not affected
If nonexistent instruction, 1 IA + 8 - I A
If nonexi stent memory address, 1 IA + 4 - I A
If (1)9
LRP
CC1 then, if (1)9
= 1,
CC2 then, if (1)9 = 1,
If privileged instruction violation, 1 - CC3 then,
if (1)9 = 1, IA + 2 IA
If memory protection violation, 1 - - CC4 then, if (1)9 = 1,
IA + 1 - - IA
= 0,
fA not affected
LOAD REGISTER POINTER
(Word index al ignment, privi leged)
LOAD REGISTER POINTER loads bits 23 through 27 of the
effective word into the register pointer (RP) portion of the
current program status doubleword. Bit positions 0 through
22 and 28 through 31 of the effective word are ignored, and
no other portion of the program status doubleword is affected.
If the register pointer is loaded with a value that points to a
nonexistent block of general reg isters, the computer subsequentl y generates either all 1's or all OIS as the contents of
the nonexistent block of general registers, whenever an instruction designates a general register by means of the R field
or the reference address field.
Affected: RP
EW23-27-RP
MMC
MOVE TO MEMORY CONTROL
0Nord index al ignment, privi leged, continue
. after interrupt)
MOVE TO MEMORY CONTROL loads a string of one or
more words into one of the three blocks of memory control
registers (memory control registers are described under
"Memory Address Control" in Chapter 2). Bitpositions 12-14
of MMC are not used as an index register address; instead,
they are used to specify which block of memory control registers is to be loaded, as follows:
Bit positi on
12 13 14
Function
100
1
0
001
Load memory map block addresses
Load access protection
Load memory write protection locks
o
ED2 10 - - DM; ED211 - - AM
ED2 15 _31 -
If call instruction, CC u CALLS-11 - - CC then,
if (1)9 = 1, fA + C ALL 8- 11 - - fA
If bit positions 12-14 of MMC contain either a" OIS or more
than a single 1, the instruction produces an undefined result.
Also, if an attempt is made to load unimplemented memory
control storage, the contents of the general regi sters specified by the MMC instruction are undefined at the completion
of the instruction, and the implemented memory control storage (if any) is not affected.
Bit positions 15-31 (reference address field) of MMC are ignored insofar as the operation of the instruction is concerned,
and the results of the instruction are the same whether or not
MMC is indirectly addressed.
The R field of MMC designates an even-odd pair of general
registers (R and Ru 1) that are used to control the Ioadi ng of
Control Instructions
77
the specified bank of memory control registers. Registers R
and Ru 1 are assumed to contain the following information:
Each word of the memory map control image is assumed to
be in the following format:
Register R:
MEMORY MAP LOADING PROCESS
Reg; ster Ru 1 :
Bit positions 15 through 31 of register R contain the virtual
address of the first word of the control image to be loaded
into the specified block of memory control registers. Bit
positions 0 through 7 of register Ru 1 contain a count of the
number of words to be loaded. If bits 0-7 of register Ru 1
are initially all OIS, a word count of 256 is implied.)
Bit positions 15 through 22 of register Ru 1 point to the beginning of the memory region controlled by the registers to
be loaded. The significance of this field is different for the
3 modes of MMC.
The R field of the MMC instruction must be an even value
for proper operation of the instruction; if the R field of MMC
is an odd value, the operation of the instruction is undefined.
If MCC is ind irectly addressed and the indirect reference address is nonexistent, the nonallowed operation trap (location
X'401) is activated. The effective vi rtual address of the MMC
instruction however, is not used as a memory reference (thus
does not affect the normal operation of the instruction).
Bit positions 15-22 of register Ru 1 initially points to the first
512-word page of virtual addresses that is to be controlled
by the map image being loaded. MMC moves the map image
into the memory map control registers one word at a time, thus
loading the page address for four consecutive memory map
registers with each image wurd. As each word is loaded into
the memory map, the virtual address of the image area is incremented by 1, the word count is decremented by 1, and the
value in bit positions 15-22 of register Ru 1 is incremented by
4; th is process continues unti I the word count is reduced to O.
When the loading process is completed, bit positions 15-31 of
register R contain a value equal to the sum of the initial map
image address plus the initial word count. Also, bit positions
0-7 of register Ru1 contain all OIS, and bit positions 15-22 of
register Ru 1 contain a value equal to the sum of the initial
contents plus 4 times the initial word count.
LOADING THE ACCESS PROTECTION CONTROLS
The following diagrams represent the configurations of MMC,
register R, and register Ru 1 that are required to load the access protection controls:
The instruction format is:
Affected: (R), (Ru 1), memory control storage
LOADING THE MEMORY MAP
The contents of reg ister Rare:
The following diagrams represent the configuration of MMC,
register R, and register Ru 1 that are required to load the
memory map:
The instruction format is:
a
I
2
The contents of register Rare:
The contents of register Ru 1 are:
MEMORY MAP CONTROL IMAGE
The initial address value in bit positions 15-31 of register R
is the vi rtual address of the first word of the memory map
control image. The word length of the control image to be
loaded is specified by the initial count in bit posiTions 0-7
of reg i ster Ru 1. A word count of 64 is suffi c i ent to load the
entire block of memory map control registers. The memory map
control registers are treated as a circular set, with the first
register following the last; thus, a word count greater than
64 causes the first registers loaded to be overwritten.
78
The contents of reg ister Ru 1 are:
Control Instructions
ACCESS PROTECTION CONTROL IMAGE
The initial address value in register R is the virtual address
of the fi rst word of the access control image, and the word
length of the first control image is specified by the initial
count in register Ru 1. A word count of 16 is sufficient to
load the entire block of access protection control registers.
The access protection control registers are treated as a circular set, with the first register following the last; thus, a
word count greater than 16 causes the first registers loaded
to be overwritten. Each word of the access control image
is assumed to be in the following format:
ACCESS CONTROL LOADING PROCESS
Bit positions 15-20 of register Ru 1 initially point to the first
512-word page of virtual addresses that is to be controlled
by the access control image. MMC moves the access control image into the access control registers one word at a
ti me, thus loading th2 controls for 16 consecutive 512-word
pages with each image word. As each word is loaded, the
virtual address of the control image is incremented by 1,
the word count is decremented by 1, and the value in bit
positions 15-20 of register Ru1 is incremented by 4; this
process continues until the word count is reduced to O. When
the loading process is completed, register R contains a value
equal to the sum of the initial control image address plus the
in itial word count. Also, the final word count is 0, and bit positions 15-20 of register Ru 1 contain a value equal to the sum
of the initial contents plus 4 times the initial word count.
LOADING THE MEMORY WRITE PROTECTION LOCKS
The following diagrams represent the configuration of MMC,
register R, and register Ru 1 that are required to load the
memory write protection locks:
the sum of the initial lock image address plus the initial
word count. Also, the final word count is 0, and bit positions 15-20 of register Rul contain a value equal to the sum
of the initial contents plus 4 times the initial word count.
INTERRUPTION Of MMC
The execution of MMC can be interrupted after each word
of the control image has been moved into the specified control register. Immediatel y prior to the time that the instruction in the interrupt (or trap) location is executed, the
instruction address portion of the program status doubleword
contains the virtual address of the MMC instruction, register
R contains the virtual address of the next word of the control
image to be loaded, and register Ru1 contains a count of the
number of control image words remaining to be moved and a
value pointing to the next memory control register to be
loaded.
The instruction format is:
WAIT
WAIT
0/Vord index alignment, privileged)
The contents of register Rare:
The contents of register Ru 1 are:
MEMORY LOCK CONTROL IMAGE
The initial address value in register R is the virtual address
of the first word of the memory lock control image, and word
length of the image is specified by the initial count in register Ru1. A word count of 16 is sufficient to load the entire block of memory locks. The memory lock registers are
treated as a circular set, with the register for memory addresses 0 through X 11 FF' immediately following the register
for memory addresses X 11 FEOOI through X 11 FFFF I; thus, a
word count greater than 16 causes the first registers loaded
to be overwritten. Each word of the lock image is assumed
to be in the following format:
MEMORY LOCK LOADING PROCESS
Bit positions 15-20 of register Ru1 initially point to the first
512-word page of actual core memory addresses that is to
be controlled by the memory lock image. MMC moves the
lock image into the lock registers 1 word at a time, thus
loading the locks for 16 consecutive 512-word pages with
each image word. As each word is loaded, the virtual address of the lock image is incremented by 1, the word count
is decremented by 1, and the value in bit positions 15 -20
of register Ru1 is incremented by 4; this process continues
until the word count is "reduced to O. When the loading
process is completed, register R contains a va lue equal to
WAIT causes the CPU to cease all operations until an interrupt activation occurs, or unti I the computer operator manuall y moves the COMPUTE switch {on the processor control
panel or on the free-standing console} from the RUN position to IDLE and then back to RUN. The instruction address porti on of the PSD is updated before the computer
begins waiting; therefore, while the CPU is waiting, the
INSTRUCTION ADDRESS indicators contain the virtual address of the next location in ascending sequenceafterWAIT
and the contents of the next location are displayed in the
DISPLAY indicators {on the processor control panel and on
the free-standing console}. If any input/output operations
are bei ng performed when WAIT is executed, the operations
proceed to their normal termination.
When an interrupt activation occurs while the CPU is waiting, the computer processes the interrupt-servicing routine.
Normally, the interrupt-servicing routine begins with an
XPSD instruction in the interrupt location, and ends with
an LPSD instruction at the end of the routi nee After the
LPSD instruction is executed, the next instruction to be
executed in the interrupted program is the next i nstructi on
in sequence after the WAIT instruction. If the interrupt is
to a single-instruction interrupt location, the instruction
in the interrupt location is executed and then instruction
execution proceeds with the next instruction in sequence
after the WAIT instruction. When the COMPUTE switch
is moved from RUN to IDLE and back to RUN while the
CPU is waiting, instruction execution proceeds with the
next instruction in sequence after the WAIT instruction.
If WAIT is indirectly addressed and the indirect reference
address is nonexistent, the nonallowed operation trap {location X1401} is activated. The effective virtual address of
the WAIT instruction, however, is not used as a memory
reference (thus does not affect the normal operation of the
i nstructi on).
Control Instructions
79
READ DIRECT
(Word index alignment, privileged)
RD
The CPU is capable of directly communicating with other
elements of the SIGMA 6 system, as well as performing internal control operations, by means of the READ DIRECT/
WRITE DIRECT (RD/WD) lines. The RD/WD lines consist
of 16 address lines, 32 data lines, 2 condition code lines,
and various control lines, that are connected to various
CPU circuits and to special systems equipment.
READ DIRECT causes the CPU to present bits 16 through 31
of the effective virtual address to other elements of the
SIGMA 6 system on the RD/WD address lines. Bits 16-31
of the effective virtual address identify a specific element
of the SIGMA 6 system that is expected to return information (2 condition code bits plus a maximum of 32 data bits)
to the CPU. The significance and number of data bits returned to the CPU depend on the selected element. If the
R field of RD is nonzero, up to 32 bits of the returned data
are loaded into genera I register R; however, if the R field
of RD is 0, the returned data is ignored and genera I regis, . ter 0 is not changed. The condition code is set by the addressed element, regardless of the value of the R field.
READ AND RESET MEMORY FAULT INDICATORS
Each core memory module is associated with a MEMORY FAULT
indicator that is turned on whenever a memory parity or over-I
temperature condition occurs. The following configuration
of RD is used to record and reset the MEMORY FAULT indicators.
If the R field of RD is nonzero, bit positions 0-23 of register
R are reset to all O·s, bit positions 24-31 are set according
to the current states of the MEMORY FAULT indicators, and
all MEMORY FAULT indicators are reset. If a bit position
in register R is set to 1, a memory fault has been detected
in the corresponding core memory module. If the R field of
RD is 0, the MEMORY FAULT indicators and the contents
of register 0 remain unchanged (although the condition code
is still set to the value of the SENSE switches). The MEMORY FAULT indicators are also reset by means of the SYS
RESET/CLEAR switch on the processor control panel.
Affected: (R),CC,MEMORY FAULT Indicators
WD
WRITE DIRECT
(Word index 01 ignment, privileged)
Bits 16-19 of the effective virtual address of RD determine
the mode of the RD instruction, as follows:
Bit Position
16 17 18
19
Mode
000
o
o
o
o
1
Internal computer control
Unassigned
XDS testers
0
0
0
0
1
1
o
1 } Assigned to various groups of standard
XDS products
o
1
Spec ial systems control (for customer use
with specially designed equipment)
If bits 16-19 of the effecti ve vi rtua I address are nonzero
(mode 1 through mode F), CC 1 and CC2 are set to zero and
CC3 and CC4 are set according to the state of the two condition code I ines from the external device.
READ DIRECT INTERNAL COMPUTER CONTROL (MODE 0)
In this mode, the condition code is unconditionally set according to the states of the four SENSE switches on the processor control panel. If a particular SENSE switch is set,
the corresponding bit of the condition code is set to 1; if a
SENSE switch is reset, the corresponding bit of the condition code is set to 0 (see "SENSE" in chapter 5).
READ SENSE SWITCHES
The following configuration of RD can be used to read the
control panel SENSE switches:
In th is case, only the condition code is affected.
80
Control Instructions
WRITE DIRECT causes the CPU to present bits 16 through 31
of the effective virtual address to other elements of the SIGMA 6 system on the RD/WDaddress lines(see READ DIRECT).
Bits 16-31 of the effective virtua I address identify a specific
element of the SIGMA 6 system that is to receive control information from the CPU. If the R fie Id of WD is nonzero,
the 32-bit contents of register R are transmitted to the specified element on the RD;WD data lines. If the R field of
WD is 0, 32 O·s are transmitted to the specified element (instead of the contents of register 0). The condition code is
set by the addressed element, regardless of the value of the
R field.
Bits 16-19 of the effective virtual address determine the
mode of the WD instruction, as follows:
Bit Position
16 17 18
000
000
o 0 1
001
19
Mode
o
Internal computer control
Interrupt control
XDS testers
1
o
1
o
1
}
ASSigned to various groups of standard
XDS products
Special systems control (for customer use
with specially designed equipment)
If bits 16-19 of the effective virtual address are nonzero
(mode 1 through mode F), CC 1 and CC2 are set to zero and
CC3 and CC4 are set according to the state of the two condition code lines from the external device.
I
WRITE DIRECT INTERNAL COMPUTER CONTROL (MODE 0)
In this mode, the condition code is unconditionally set
accordi ng to the states of the four SE NSE switches on the
processor control panel. If a particular SENSE switch is
set, the corresponding bit of the condition code is set to 1;
if a SENSE switch is reset, the corresponding bit of the
condition code is reset to 0 (see "SENSE" in Chapter 5).
SET INTERRUPT INHIBITS
The following configuration of WD can be used to set the
interrupt inhibits (bit positions 37-39 of the PSD).
A logical inclusive OR is performed between bits 29-31 of
the effective virtual address and bits 37-39 of the PSD. If
any (or all) of bits 29-31 of the effective virtual address are
l's, the corresponding inhibit bits in the PSD are set to l's;
the current state of an inhibit bit is not affected if the corresponding bit position of the effective virtual address contains a O.
TOGGLE PROGRAM-CONTROLLED-FREQUE NCY
FLIP-FLOP
The following configuration of WD is used to "toggle" the
CPU program-controlled-frequency (PCF) flip-flop:
The output of the PCF flip-flop is transmitted to the computer
speaker through the AUDIO switch on the maintenance secti on
of the processor control pane I. If the PCF fI i p-fl op is reset whe n
the above configuration of WD is executed, the WD instruction
sets the PCF fI ip-floPi if the PCF fI ip-flop was previ ously set,
the WD instruction resets it. A program can thus generate a
desired frequency by toggling (setting and resetting) the PCF
fl ip-flop at the appropriate rate. Execution of the above
configuration of WD also resets the ALARM indicator.
WRITE DIRECT, INTERRUPT CONTROL (MODE 1)
The following configuration of WD is used to set and reset
the various states of the individual interrupt levels within
the CPU interrupt system:
RESET INTERRUPT INHIBITS
The following configuration .)f WD can be used to reset the
interrupt inhibits:
If any (or all) of bits 29-31 of the effective virtual address
are l's the corresponding inhibit bits in the PSD are reset to
O's; the current state of an inhibit bit is not affected if a
corresponding bit position of the effective virtual address
contains a O.
SET ALARM INDICATOR
The following configuration of WD is used to set the ALARM
indicator on the maintenance section of the processor control panel:
Bits 28 through 31 of the effective address specify the identification number (see Table 2) of the group of interrupt
levels to .be controlled by the WD instruction.
The R field of the WD instruction specifies ageneral register
that contains the selection bits for the individual interrupt
levels, excluding Power on/Power off, within the specified
group (see Table2). Bit position 160f register R contains the
selection bit for the highest-priority (lowest-numbered) interrupt level within the group, and bit position 31 of register R
contains the selection bit for the lowest-priority (h ighestnumbered) interrupt level within the group. Each interrupt
level in the designated group is operated on according to the
function code specifiedbybits21 through 23 of the effective
address of WD. The codes and their associated functions are as
follows:
Code
Function
If the COMPUTE switchontheprocessorcontrol panel isinthe
000
Undefi ned
RUN position and the AUDIO switch on the maintenance section of the processor control panel is in the ON position, a
WOO-Hz signal is transmi tted to the computer speaker. The
signal may be interrupted by moving the COMPUTE switch
to the IDLE position, by moving the AUDIO switch to the
OFF position, or by resetting the ALARM indicator.
OOlt
Disarm all levels selected by a 1; all levels selected
by a 0 are not affected.
OlOt
Arm and enable all levels selected by a 1; all level s
selected by a 0 are not affected.
Ollt
Arm and disable al/ levels selected by a 1; all levels
selected by a 0 are not affected.
100
Enable all levels selected by a 1; all levels selected
by a 0 are not affected.
101
Disable all levels selected by a 1; all levels selected
by a 0 are not affected.
RESET ALARM INDICATOR
The following configuration of WD is used to reset the
ALARM indicator:
The ALARM indicator is.also reset by means of either the CPU
RESET/CLEAR switch or the SYS RESET/CLEAR switch on the
processor control panel.
t These codes c Iear the current interrupt, i. e. remove from
the active or waiting state all levels selected by a 1 (see
Figure 7).
I
Control Instructions
81
Code
Function
110
Enable ali levels selected by a 1 and disable all
levels selected by a O.
111
Trigger all levels selected by a 1. All such levels
that are currently armed advance to the waiting state.
Bit positions 25 through 31 of the I/O address contain a
3-bit device controller code (DC) in bit positions 25-27
and a 4-bit device code (Device) in bit positions 28-31.
This form of I/O address is used for device controllers (such
as magnetic tape and rapid access data file controllers) that
control information exchange with only one device at a time
(out of a set of as many as 16 devices).
INPUTjOUTPUT INSTRUCTIONS
Standard" SIGMA 6 I/O refers to the normal I/O system
consisting of input/output processors, device controllers,
and devices. This system handles normal communications
with standard peripherals such as printers, disks, tapes,
and so forth. When dealing with standard I/O operations,
the CPU uses the following five instructions:
110 UNIT ADDRESS ASSIGNMENT
II
Instruction Name
Mnemonic
Start Input/Output
Halt Input/Output
Test Input/Output
Test Device
Acknowledge Input/Output Interrupt
SIO
HIO
TIO
TOY
AIO
If execution of any input/output instruction is attempted while
the computer is in the slave mode (i. e. , whi Ie bit a of the
current program status doubleword is a 1), the computer uncondi tiona II y aborts execution of the instruction (at the time
of operation code decoding) and traps to location X '40'.
Device controller numbers are normally assigned to a multiplexor lOP in numerical sequence, beginning with zero and
continuing through the highest number recognized by the lOP
(i. e., X,]', X'fi, X'17', or X'lF'). In the case of multiunit
device controllers, the device controller number must be in the
range X '0' through X '7' because the I/O address field structure
allows fora 3-bit multiunitdevice controller number. In the
case of si ngle-unit device controllers, any of the avai lable
numbers in the range X'O' through X'lF' may be assigned to
the device controller, providi ng that the Same number has not
already been assigned to a multiunit device controller. For
example, if device controller number X '0' is assigned to a
magnetic tape unit controller, the number X'O' cannot also
be used for a card reader (although the coding of the I/O
address field would be different in bit position 24). The I/O
address codes used by standard XDS software are
I/O address
Peripheral device designation
x'oao'
. lOP 0, devi ce controller 0, magnetic tape
unit 0
The device to be operated on by an I/O instruction is selected
by the effective virtual address of the I/O instruction itself.
Indirect addressing and/or indexing are performed, as for
other word-addressing instructions, to compute the effective
virtual address of the I/O instruction. However, the effecti ve address is not used as a memory reference (i. e., not
subject to memory mapping). For the SIO, HIO, TIO, and
TDY instructions, the 11 low-order bits of the effective virtualaddress constitute an I/O address. FortheAIOinstruction, the device causing the interrupt returns its 11-bit I/O
address as part of the response to the AIO instruction.
X'Oal'
lOP 0, device controller 0, magnetic tape
unit 1
X'Oa7'
lOP 0, device controller 0, magnetic tape
unit 7
X'OOl'
lOP 0, device controll er 1, keyboard/printer
X'002'
lOP 0, device controller 2, line pri nter
X'003'
lOP 0, device controller 3, card reader
An I/O address occupies bit positions 21 through 31 of the
effective virtual address, with bits 21, 22, and230ftheI/0
address specifying one of eight possible lOPs that can be controlled by a CPU. The remainder of the I/O address is factored
into one of two forms, depending on bit 24, as follows:
X'004'
lOP 0, device controll er 4, card punch
X'005'
lOP 0, device controller 5, paper tape
reader/punch
110 ADDRESSES
Case I: Single-unit device controllers (bit 24 is 0)
Bits 25 through 31 of the I/O address (DC/Device) constitute a single code specifying a particular combination of
devi ce controller and device. Normally these codes refer
to devi ce controllers that drive only a single device, such
as card readers, card punches, line pri nters, etc.
Case II: Multiunit device controllers (bit 24 is 1)
82
Input/Output Instructi ons
110 STATUS RESPONSE
All I/O instructions result in the setting of condition code
CC1 and CC2 to denote the nature of the I/o response.
The R field of the I/O instruction specifies one of the general registers that is to accept additional I/O response information during the execution of an I/O instruction. In
some situations, the programmer may want two sets of response information loaded into the general registers, while
in other situations he may want only one set, or even no
information loaded into a general register. This control is
achieved by coding the R field of the I/O instruction. One
set of response information is loaded into register R and another set may be loaded into register Rul. If the R field is
an even, nonzero number, registers Rand R + 1 are each
loaded with response information. If the R field specifies
an odd-numbered general register, then only register R is
loaded with response information. However, if the R field
is 0, Rand Rul are not loaded with response information.
Also, if RI- 0 and CCl is set to 1 as a result of the operation, no status information is returned to Rand Rul. The
I/O response information loaded into the general register
for 510, HIO, TIO, and TDV instructions is in the following
format:
Word into register R
Word into regi ster Ru 1
and the device is started 0. e., advanced to the "busy"
condition). If the 510 is accepted, the first command
doubleword address is loaded into the IOPcommand address
counter associated with the device controller specified by
the I/O address of the 510 instruction. Then, if the device
is in the "automatic" mode, it requests an order from the
lOP. The lOP loads the first command doubleword of the
1/0 command list into its appropriate regi sters and transmits
the order to the device.
The CPU condition code provides an indication of whether
the I/O address specified by the 510 instruction was or was
nC;;t recognized by the I/O system and whether the 510 instruction was or was not accepted by the device (i. e., whether
the device did or did not advance to the "busy" condition).
The condition code settings for 510 are:
Current Command Doubleword Address. After the addressed
devi ce has received an order, this field contai ns the 16
high-order bits of the core memory address for the command
doubleword (see "IOP Command Doublewords ll ) currently
being processed for the addressed device.
1
234
Resul t
o
o
0
I/O address recognized and 510 accepted
I/O address recognized but 510 not
accepted
o
lOP address recognized but device controller either is attached to a "busy"
selector lOP that cannot return status at
this time or, for specific device controll ers, is currentl y "busy" wi th another
devi ceo No status informati on is returned
to general registers.
Status. The meaning of this field depends on the particular
I/O instruction being execu+-ed and upon the selected I/O
device (see Table 8).
Byte Count. After the addressed device has received an
order, this field contains a caunt of the number of bytes yet
to be transmitted to or from memory by the operation called
for by the order.
I/O address not recognized and 510 not
accepted; no status i nformati on is returned
to general registers.
See the AIO instruction description for the format of I/O
response i nformati on for AIO.
510
START INPUT/OUTPUT
\:'Nord index alignment, privileged)
START INPUT/OUTPUT is used to initiate an input or output operation with the device selected by the I/O address
(bits 21-31 of the effective vi rtua I address of the instruction).
510 utilizes data in general register 0, which is assumed
to have the following content when 510 is executed.
STATUS INFORMATION FOR SIO
In the event that the 510 instruction was not accepted
(i. e., CC 1 = 0 and CC2 = 1), the status information returned
as a part of the I/O response provides indications of Nhy
the 510 instruction was not accepted. If the 510 instruction
has been coded with an R field value of 0, or if CCI (as a
result of the execution of this instruction) is a I, only the
condition code settings are available. If the R field value
is odd, register R contains the fol lowing information:
Bit
Position Function
o
General register 0 is temporarily dedicated during the execution of an 510 instruction to specify the starting doubleword address for the lOP command list. The doubleword
address in register 0 is the 16 high-order bits of a memory
address; thus, the address in register 0 always specifies an
even-numbered word location. (The lOP command list is
described in "10P Command Doublewords", Chapter 4.)
If I/O address recogniti.on exists in the I/O system, and the
device controller and device are in the "ready" condition
and no interrupt condition is pending, the 510 is accepted
Interrupt pendingj if this bit is 1, the addressed
device has requested an interrupt and the interrupt has not been acknowledged by an AIO instruction. I/O interrupts can be achieved by coding
of the flag portion of the I/O command doubleword. I/O interrupts can also be achieved by using
M modifiers in the basic order to the device (M bits
in the Order portion of the command doubleword).
In either case, the device wil I not accept a new
SIO instruction until the interrupt-pending condition is cleared (i.e., the condition code settings
for the SIO instruction will indicate IISIO not
accepted ll if the interrupt-pending condition is
present in the addressed device.
Input/Output Instructions
83
Table 8.
Status Bits for I/O Instructions
Posi tion and State in Register Ru 1
Device Status Byte
2
3
- 0 0
-
0
-
0
1
1
1
0
4
Operational Status Byte
5
7
6
8
9
10 11
12 13 14 15
-
-
- -
1
-
0
1
-
00-
-
0
Significance for
SIO, HIO, and TIO
interrupt pendi ng
device ready
devi ce not operational
device unavailable
device busy
de vi ce manua I
device automatic
device unusual end
device controller ready
device controller not operational
device controller unavailable
device controller busy
unassigned
1
1 0
1 1
- 0
incorrect length
transmission data error
transmission memory error
memory address error
lOP memory error
lOP control error
lOP halt
Selector lOP busy
Position and State in Register R
Device Status Byte
o
2 3
4
Operational Status Byte
5
6
7
8
9
10 11
12 13 14 15
Significance for AIO
unique to the device and
the devi ce controller
incorrect length
transmission data error
zero byte count interrupt
channel end interrupt
unusual end interrupt
-
0
o : }
84
Input/Output Instructi ons
unassigned
Significance
for TOV
unique to the
device and the
device controller
1
same as for
SIO, HIO, and
TIO
j
Bit
Position Function
1, 2
3
Devi ce condition: if bits 1 and 2 are 00 (device
"ready II), all devi ce conditions required for proper
operation are satisfied. If bits 1 and 2 are 01
(devi ce "not operational II), the addressed device
has developed some condition that will not allow
it to proceed; in either case, operator intervention
is usually required. If bits 1 and 2 are 10 (device
IIUnavailable ll ), the device has more than one
channel of communication avai lable and it is engaged in an operation controlled by a controller
other than the one specified by the I/O address.
If bits 1 and 2 are 11 (device IIbusyll), the device
has accepted a previous SIO instruction and is already engaged in an I/O operation.
Device mode: if this bit is 1, the device is in the
lIautomatic ll mode; if this bit is 0, the device is
in the IImanual li mode and requires operator intervention. This bit can be used in conjunction with
bits 1 and 2 to determine the type of action requ ired. For exam pi e, assume that a card reader
is abl e to operate, but no cards are in the hopper.
The card reader wvuld be in state 000 (device
IIreadyll, but manual intervention required), where
the state is indicated by bits 1, 2, and 3 of the
I/o status response. If the operator subsequently
loads the card hopper and presses the card reader
START switch, the reader would advance to state
001 (device IIreadyll and in automatic operation).
If the card reader is instate 000 when an SIO i nstruction is executed, the SIO would be accepted
by the reader and the reader would advance to
state 110 (device IIbusyll, but operator intervention
required). Should the operator then place cards
in the hopper and press the START switch, the card
reader state would advance to 111 (device IIbusy"
and in automatic operation), and the input operation would proceed. Should the card reader subsequently become empty (or the operator press the
STOP switch) and command chaining is being used
to read a number of cards, the card reader would
return to state 110. If the card reader is instate
001 when an SIO instruction is executed, the
reader advances to state 111, and the input'operation continues as normal. Should the hopper subsequently become empty (or should the operator
press the card reader STOP switch) and command
chaining is being used to read a number of cards,
the reader would go to state 110 unti I the operator
corrected the situation.
4
Unusual end: if this bit is 1, the previous I/O operation terminated in an II unusual end ll condition.
These conditions vary from device to device (see
the applicable peripheral reference manual).
5,6
Device controller condition: if bits 5and 6 are 00
(device controller "readyll), all device controller
conditions required for its proper operation are
satisfied. If bits 5 and 6 are 01 (device controller
Bit
Position Function
5,6
(cont.)
II not operational"), some condition has developed
that does not allow it to operate properly. In
either case, operator i nterventi on is usually requi red. If bits 5 and 6 are 10 (device controller
"unavailable"), the device controller is currently
engaged in an operation controlled by an lOP
other than the one addressed by the I/O instruction.
If bits 5 and 6 are 11 (device controller "busy"),
the device controller has accepted a previ ous
SIO instruction and is currently engaged in performing an operati on for the addressed lOP.
7
Reserved
8
Incorrect length: if this bit is 1, an incorrect
length condition has been detected during the
previous operation. Incorrect length is caused
by a channel end (or end of record) condition
occurring before the device controller has received a IIcount done" signal from the lOP, or is
caused by the de vi ce controller recei vi ng a count
done signal before channel end (or end of record);
e. g., count done before 80 columns have been
read from a card. Normally, a count done signal
is sent to the device controller by the lOP to indicate that the byte count associated with the
current operati on has been reduced to zero. The
lOP is capable of suppressing an error condition on
incorrect length, since there are many situations
in which incorrect le.ngth is a legitimate situation
and not a true error condition. Incorrect length is
suppressed as an error by coding the SIL flag (a 1
in bit 38) of the lOP command doubleword (see
IIFlags ll , Chapter 4). At the end of the execution
of an I/O command list, this status bit is 1 if an
incorrect length condition occurred anywhere in
the command list, regardless of the coding of the
SIL flag.
9
Transmission data error: this bit is set to 1 if the
lOP or device controller has detected a parity
error or data overrun in the transmitted information. At the end of an execution of an I/O command list, this status bit is 1 if a transmission data
error occurred anywhere in the command list.
10
Transmission memory error: this bit is set to 1 if
a memory parity error has occurred during a data
input/output operation. A parity error is detected
on any output operation and on partial-word input
operations. At the end of an execution of an I/O
command list, this status bit is 1 if a transmission
memory error occurred anywhere in the command
list. A device halt occurs only if the HTE flag
in the lOP command doubleword is set to 1 (see
ll
II Flags , Chapter 4).
11
Memory address error: a nonexi stent memory address
has been encountered on ei ther data or commands.
Operation is terminated with an II unusual end".
Input/Output Instructions
85
The status information returned for HIO has the same interpretation as that returned for the instruction SIO and
shows the I/O status at the time cf the halt. The count
information shows the number of byies remaining to be
transmitted at the time of the halt. If the R field of HIO
is an even value and not 0, the condition code is set, register R+l is loaded as shown above, and register R contains
the following information:
Bi t
Posi tion Function
12
lOP memory error: if a memory parity error has
occurred while the lOP was fetching a command,
this bit is set to 1. Operation is terminated with
an "unusual end".
13
lOP control error: this bit is set to 1 if the lOP
has encountered two successive TRANSFER IN
CHANNEL commands.
14
lOP halt: this bit is set to 1 if the lOP has issued
a halt order to the addressed I/O device because
of an error condition.
15
Selector lOP busy: this bit is set to 1 if a selector
lOP is addressed by the I/O instruction and the
selector lOP is currently in use by some I/O device. The selector lOP is considered to be in use
from the time that a device accepts an S10 instruction until the operation is completed.
16-31
Byte count: a count of the number of bytes yet to
be transmitted to or from memory in the operation
called for by the current command doubleword.
The current command doubleword address has the same interpretation as that for the instruction SIO.
Affected: (R), (Rul), CC1,CC2
Condition code settings:
2
o
o
If the R field value of the SIO instruction is even and not
0, the condition code and register R+ 1 contain the informa-
0
3
4
Result of HIO
VA address recognized and device controll er is not "busy II •
VA
address recognized but device controllerwas "busy"at the time of the halt.
VA
address not recognized.
tion described above and register R contains the following
information:
TlO
TEST INPUT/OUTPUT
0/Vord index alignment, privileged)
Bit
Position Function
16-31
Current command doubl eword address: the 16
high-order bits of the core memory address from
which the command doubleword for the I/O operation currently being processed by the addressed
device controller was fetched.
HIO
HALT INPUT/OUTPUT
0/Vord index al ignment, privi leged)
HALT IN PUT/OUTPUT causes the addressed device to immediately halt its current operation (perhaps improperly, in
the case of magneti c tape un j ts, when the devi.ce is forced to
stop at other than interrecord gap). If the device is in an
interrupt-pending condition, the condition is cleared.
If the R field of the HIO instruction is a or if no I/O address recognition exists, no general registers are affected,
but the condition code is set. If the R field is an odd
value, the condition code is set and the following information is loaded into register R.
I
0',
86
,I."
St~tus
I
,",. '""I"""""" ....
Input/Output Instructions
~ount
I~"""""u"I~~~,,
Byte
I
TEST INPUT/OUTPUT is used to make an inquiry on the
status of data transmission. The operation of the selected
lOP, device controller, and device are not affected, and
no operations are initiated or terminated by this instruction.
The responses to TIO provide the program with the information necessary to determine the current status of the device,
device controller, and lOP, the number of bytes remaining
to be transmitted to or from memory in the operation, and
the present point at which the lOP is operating in the command list. If the R field of the TIO instruction is 0, or if
CC 1 (as a result of the execution of this instruction) is a 1,
no general registers are affected, but the condition code is
set. If the R field of TIO is an odd value, the condition
code is set and the I/O status and byte count are loaded
into register R as follows:
The status i nformati on has the same i nterpretati on as the
status information returned for the instruction SID and shows
the I/O status at the time of sampling.
The count information shows the number of bytes remaining
to be transmitted at the time of sampling. If the R field of
the TIO instruction is an even value and not 0, the
condition code is set, register R + 1 is loaded as shown
above, and register R is loaded as follows:
The current command doubleword address has the same interpretation as for the instruction 510.
The count information shows the number of bytes remaining
to be transmitted in the current operation at the time of the
TDV instruction. If the value of the R field of TDV is an
even value and not 0, the condition code is set, register
R + 1 is loaded as shown above, and register R is loaded as
follows:
Affected: (R), (Ru1), CC1,CC2
Condition code settings:
2
o
3
4
Result of TIO
The current command doubl eword address has the same interpretation as for the instruction 510.
Affected: (R), (Ru 1), CC 1
Condition code settings:
0
I/O address recognized and acceptable
SIO is currently possible.
o
I/O address recognized but acceptable
SIO is not currentl y possible.
o
2
3
4
a a
I/O address recognized.
o
I/O address recognized and devicedependent condi ti on is present.
lOP address recognized but device controller either is attached to a "busy"
sel ector lOP that cannot return status at
this time or, for specific device controllers, is currently "busy" with another
device. No status information is returned
to general registers.
a
lOP address recognized but device controller either is attached to a "busy"
selector lOP that cannot return status at
this time or, for specific device controllers, is currently "busy" with another
device. No status information is returned
to general registers.
1/0 address not recogn i zed; no status information is returned to general registers.
I/O address not recognized; no status information is returned togeneral registers.
TDV
TEST DEVICE
(Word index alignment, privileged)
TEST DEVICE is used to provide information about a device
other than that obtainable by means of the TIO instruction.
The operation of the selected lOP, device controller, and
device is not affected, and no operations are initiated or
terminated. The responses to TDV provide the program with
information giving details on the condition of the selected
device, the number of bytes remaining to be transmitted to
or from memory in the current operation, and the present
point at which the lOP is operating in the command list.
If the R field of the TDV instruction is 0, or if CC 1 (as a
result of the execution of this instruction) is a 1, the condition code is set, but no general registers are affected.
If the R field of TDV is an odd value, the condition code
is set and the device status and byte count are loaded into
register R as follows:
Bit
Position Function
0-7
Unique to the device and device controller.
8-15
Same as for bits 8-15 of the status information for
instruction 510.
Result of TDV
AIO
ACKNOWLEDGE INPUT/OUTPUT INTERRUPT
0/Vord index al ignment, privi leged)
AIO is used to acknowledge an input/output interrupt and to
identify what I/O unit is causing the interrupt and why. Bits
21,22, and 23 of the effective virtual address of the AIO instruction (the 10 P portion of the I/o sel ection code field)
specify the type of interrupt being acknowl edged. These bits
should be coded 000 to specify the standard I/O system interrupt
acknowl edgement (other codi ngs of these bits are reserved for
use with special I/o systems). The remainder ofthe I/o seIection code field (bit positions 24-31) has no other use in the
standard I/o interrupt acknowledgement because the identificationoftheinterruptsourceis one of the responses of the
standard I/o system to the AIO instruction.
Standard I/O system interrupts can be initiated for the following conditions:
Condition
Interrupt t
prerequi si te
Status
bit set
Zero byte count
IZC= 1
10
Channel end
ICE = 1
11
t rzc , ICE, IUE, HTE, and SIL refer to flag bits in the lOP
command doublewords (see Chapter 4).
Input/Output Instructions
87
Condition
Interrupt
.. t
prerequi Sl te
Status
bit set
Bit
Position Function
Transmission memory error
I UE = 1, HTE = 1
12
Incorrect length
I UE = 1, HTE = 1
and SIL=O
8, 12
8
(cont.)
Memory address error (lOP
memory error or lOP control error)
IUE= 1
12
Transmission data error
IUE = 1, HTE = 1
9, 12
Unusual end
IUE= 1
12
lOP halt
IUE= 1
12
When a device interrupt condition occurs, the lOP forwards
the request to the CPU interrupt system I/O interrupt level.
If this interrupt level is armed, enabled, and not inhibi ted
(see Chapter 2, II Control of the Interrupt System"), the CPU
eventually acknowledges the interrupt request and executes
the XPSD instruction in core memory location X'5C, which
leads to the execution of an AIO instruction.
For the purpose of acknowledging standard I/O interrupts,
the lOPs, device controllers, and devices are connected in
a preestablished priority sequence that is customer-assigned
and is independent of the physical locations of the portions
of the I/O system in a particular installation.
If the R field of the AIO instruction is 0 or if no device interrupt request is present, the condition code is set but the
general register is not affected. If the R field of AIO is
not 0, the condition code is set and register R is loaded
with the following information:
Bit
Position Function
0-7
Unique to the device and the device controller.
8
Incorrect length: if this bit is I, an incorrect
length condition has been signaled to the lOP
by the device controller during the previous
operation.
Incorrect I ength is suppressed as on error by
coding the SIL flag (0 1 in bit 38) of the command
doubleword. At the end of the execution of on
I/O command list, this status bit is 1 if on incorrect length condition occurred anywhere in the
command I ist, regardless of the coding of the SIL fI ago
9
Transmission data error: this bit is set to 1 if the
lOP or device controller has detected a parity error or data overrun in the transmitted information.
10
Zero byte count interrupt: if this bit is 1, the byte
count for the operation being performed by the interrupting device has been reduced to 0, and the
interrupt at zero byte count (IZC) flag in the command doubleword for the operation was coded with
a1.
11
Channel end interrupt: if this bit is 1, the device
controller has signaled channel end to the lOP,
and the interrupt at channel end (ICE) flag in the
command doubleword for the operation was coded
with a 1.
12
lOP unusual end interrupt: if this bit is 1, the lOP
has originated the interrupt as a result of a fault or
unusual condition reported by the device.
13-20
Reserved
21-31
I/O address: this field identifies the highestpriority devi ce requesting on interrupt. Bit positions 21-23 identify the lOP. If bit 24 is 0, bits
25-31 constitute a common device controller and
device code; if bit 24 is 1, bits 25-27 constitute
a device controller code and bits 28-31 identify a
device attached to that device controller.
The AIO instruction resets the interrupt request signal from
the highest priority I/O device requesting interrupt service
(i. e., the device identified above in bits 21-31).
Affected: (R), CC1, CC2
Condition code settings:
2
o
t IZC, ICE, IUE, HTE, and SIL refer to flag bits in the lOP
command doublewords (see Chapter 4).
88
Input/Output Instructions
o
0
3
4
Result of AIO
normal interrupt recognition.
unusual interrupt recognition.
no interrupt recognition.
4. INPUT jOUTPUT OPERATIONS
In a SIGMA 6 system, input/output operations are primari I y under control of one or more input/output processors
(lOPs). This allows the CPU to concentrate on program
execution, free from the time-consuming details of I/o operations. Any I/O events that require CPU intervention are
brought to its attenti on by means of the interrupt system.
In the following discussion, the terminology conventions
used are that the CPU executes instructions, the lOP executes commands, and the device controllers and/or I/O
devices execute orders. To illustrate, the CPU will execute the START INPUT/OUTPUT {SIO} instruction to initiate an I/O operation. During the course of an I/O operation, the lOP might issue a command called Control, to
transmi t a byte to a device controll er or I/O device that
interprets the byte as an order, such as Rewi nd.
The SIGMA 6 CPU plays a minor role in the execution
of an I/o operation. The CPU-executed program is responsible for creating and storing the command I ist (prepared
prior to the initiation of any I/O operation) and for supplying the lOP with a pointer to the first command in the I/O
command list. Most of the communication between the CPU
and the I/O system is carried out through memory.
The following is an example of the sequence of events that
occurs during an I/O operati on:
1.
A CPU-executed program writes a sequence of I/O
commands in core memory.
2.
TheCPU executes the instruction START INPUT/OUTPUT
and furnishes the lOP with an 11-bitl/Oaddress (dessignating the device to be started) and a 16-bit first
command address (designating the actual core memory
doubleword location where the first command for this
device is located). At this point, either the device is
started (if in the "ready" condition with no device interrupt pending) or an instruction rei ect occurs. The
CPU is informed by condition code settings as to which
of the two al ternatives has occurred. If the START I/O
instruction is accepted, the command counter portion
of the lOP register associated with the designated device.controller is loaded with the first command address.
Assuming that the SIO instruction is accepted, from this
time until the full sequence of I/o commands has been
executed, the moin program of the CPU need play no
role in the I/O operation-. At any time, however, it
mayobtain status information on the progress of the l/O
operation without interfering with the operation.
3.
The device is now in the "busy" condition. When the
device determines that it has the highest priority for
access to the lOP, it requests service from the lOP
with a service call. The lOP obtains the address of
the first command doubl eword of the I/O sequence
{from the command counter asssociated with this de-vice}. The lOP then fetches the I/O command
doubleword from core memory, loads the doubleword
into another register associated with the device, and
transmits the first order (extracted from the command
doubl eword) to the device.
4.
Each command counter contains the memory address of
the current I/O command in the sequence far its device. When the device requires further servicing, it
makes a request to the lOP, which then repeats a process similar to that of step 3.
5.
If a data transmi ssi on order has been sent to a device, control of the transmission residesin thedevice. Aseachcharacter is obtained by the I/Odevice, the lOP is signaled
that data is available. The lOP uses the information
stored in its own registers to control the information
interchange between the I/o device and the memory, on
either a word-by-word or character-by-character
basis, depending on the nature of the device.
SIGMA 6 lOPs operate independentl y after they have been
started by the central processor. They automatically pick
up a chain of one Of" more commands from core memory and
then execute these commands until the chain is completed.
The multiplexor input/output processor (MIOP), or MIOP
expansion option (wh ich includes confl iet-resolving circuitry
to permit it to share a memory bus), can simultaneously
operate up to 24 device controllers. Each device controller
is assigned its own channel and chain of I/o commands. The
seleetor input/output processor (SlOP) can handle any of up
to 32 high-speed device controllers at rates up to the full
speed of the core memory (one 32-bit word/cycle).
The flexible SIGMA 6 I/o structure permits both command
chaining (making possible multiple-record operations) and
data chaining (making possible scatter-read and gatherwrite operations) without intervening CPU control. Command chaining refers to the execution of a sequence of I/O
commands, under control of an lOP, on more than one
physical record. Thus, a new command must be issued for
each physical record even if the operation tobe performed
for a record is the same as that performed for the previous
record. Data chaining refers to the execution of a sequence
of I/O commands, under control of an lOP, that gather (or
scatter) information within one physical record from {or to}
more than one region of memory. Thus, a new command
must be issued for each portion of a physical record when
the data associated with that physical record appears {or is
to appear} in noncontiguous locations in memory. For
example, if information in specific columns of two cards in
a file are to be stored in specific regions of memory, the
I/o command I ist might appear as follows:
1.
Read card, store col umns 1-10, data cha in
2.
Store columns 11-60, data chain
3.
Store columns 61-80, command chain (end of data
chain)
4.
Read card, store col umns 1-40, data chain
5.
Store columns 41-80 {end of command chain, end of
data chain}
Input/Output Operations
89
I
6.
When all information exchanges called for by a single
I/o command doubl eword have been compl eted, the
lOP uses the command counter to obtain the next command doubl eword for execution. This process continues
until all such command doubl ewords associated with the
I/O sequence have been executed.
lOP COMMAND DOUBLEWORDS
All lOP command doublewords (except Transfer in Channel
and Stop) are assumed to be in the following format:
ORDER
Bit positions 0 through 7 of the command doubleword contain the I/O order for the device controller or device. The
I/o orders are shown below. t Bits represented by the letter',
"M" specify orders or special conditions to the device and
are unique for each type of device.
Bit positions
o 1 234 5 6 7
Order
MMMMM M 0
MMMMM Ml
MMMMM M 1
M M M M 0 1 0
MMMMl 1 0
Write
Read
Control
Sense
Read Backward
1
o
1
o
o
Write. The Write order causes the device controll er to initiate an output operation. Bytes are read in an ascending
sequence from the memory location specified by the memory
byte address field of the command doubl eword. The output
operation continues until thedevice signals "channel end",
or until the byte count is reduced to 0 and no further data
chaining is specified. Channel end occurs when the device
has received all information associated with the output operation, has completed all checks, and no longer requires
the use oflOPfacilities for the operation. Data chaining
is described on the following page.
Read. The Read order causes the device controller to initiate an input operation. Bytes are stored in core memory in
an ascending sequence, beginning at the location specified
by the memory byte address field of the command doubleword. The input operation continues until the device signals
channel end, or until the byte count is reduced to 0 and no
further data chaining is specified. Channel end occurs when
the device has transmitted all information associated with
the input operation and no longer requires the use of lOP
faci Ii ti es for the operati on.
tNot all I/o devices recbgnize all these orders. See the
particular XDS SIGMA peripheral reference manual for
orders appl icable to that device.
90
lOP Command Doublewords
Control. The Control order is used to initiatespecial operations by the device. For magnetic tape, it is used to issue
orders such as rewind, backspace record, backspace fi Ie,
etc. Most orders can be specified ':>y the M bits of the
Control order; however, if additional information is required for a particular operation (e.g., the starting address of a disk-seek), the memory byte address field of the
command doubleword specifies the starting address of the
bytes that are to be transmitted to the device controller for
the additional information. When all bytes necessary for
the operation have been transmitted, the device controller
signals channel end.
Sense. The Sense order causes the device to transmit one or
more bytes of information, describing its current state. The
bytes are stored in core memory in an ascending sequence,
beginning with the address specified by the memory byte address field ofthecommanddoubleword. The number of bytes
transmitted is a function of the device and the condition it
describes. The Sense order can be used to obtain the current sector address from a disk unit.
Read Backward. The Read Backward order (for devices that
can execute it) causes the device to be started in reverse,
and bytes to be transmitted to the lOP for storage into core
memory in a descending sequence, beginning at the location
specified by the memory byte address field of the command
doubleword. In all other respects, Read Backward is identical to Read, inc! uding reducing the byte count with each
byte transm itted.
The Transfer in Channel command doub leword is assumed to
be in the following format:
Transfer in Channel. The Transfer in Channel command is executedwithin the lOP, and it has no direct effect on any of
the I/o system el eme"ts externa I to the addressed lOP. The
primary purpose of Transfer in Channel is to perm it branching within the command list so that the lOP can, for example, repeatedly transmit the same set of information a number of times. When the lOP executes Transfer in Channel,
it loads the command counter for the device controller it is
currently servicing with the command doubleword address
field of the Transfer in Channel command, loads the new
command doubleword specified by this address into the lOP
registers associated with the device controller, and then
executes the new command. (Bit positions 0-3, and 32-63
of the command doubleword for Transfer in Channel are ignored.) Transfer in Channel thus allows a command list to
be broken into noncontiguous groups of commands. When
used in conjunction with command chaining, Transfer in
Channel facilitates the control of devices such as unbuffered
card punches or unbuffered line printers. The current flags
(see "Flags" below) are not al tered during th is command;
thus the type of chain ing called for in the previous command doubleword is retained until changed by a command
doubleword following Transfer in Channel.
For example, assume that it is desired to present the same
card image twelve times to an unbuffered card punch. The
punch counts the number of times that a record is presented
to it and, when twelve rows have been punched, it causes
the lOP to sk ip the command it would be executing next.
Thus, a command list for punching two cards might look
Iike the following example.
Location
A
Command
Punch row for card 1, command chain
Transfer in Channel to A
B
Punch row for card 2, command chain
primarily used to terminate a command chain for an
unbuffered device, as illustrated in the example given for
Transfer in Channel.
MEMORY
am
ADDRESS
For all I/O commands (except Transfer in Channel and
Stop), bit positions 13-31 of the command doubleword
provide for a 19-bit core memory byte address, designating the memory location for the next byte of data.
For the Write, Read, and Control orders, this field (as
stored in an lOP register) is incremented by 1 as each
byte is transmitted to the I/o operation; for the Read
Backward order, the field is decremented by 1 as each
byte is transmitted.
Transfer in Channel to B
Stop
The Transfer in Channel command a Iso can be used in conjunction with data chaining. As one example, consider a
si tuation often encountered in data acquisition appl ications,
where data is transmitted in extremely long, continuous
streams. In this case, the data can be stored alternately in
two or more buffer storage areas so that computer processing
can be carried out on the data in one buffer whileadditional
data is being input into the other buffer. The command list
for such an application might look like the following example.
Location
A
FlAGS
For all I/o commands (except Transfer in Channel and
Stop) bit positions 32-39 of the command doubleword
provide the lOP with eight flags that specify how to
handle chaining, error, and interrupt situations. The
functions of these flags are:
Bit
Position
32 (DC)
Data chain. If this flag is 1, data chaining is
called for when the current byte count is reduced
to o. The next command doub Ieword is fetched
and loaded into the lOP register associated with
the device controller, but the new order code is
not passed out to the device controller; thus, the
operation called for by the previous order is continued. (Except for Transfer in Channel, the
new command doubleword is used only to supply
a new memory address, a new count, and new
flags.) If the data chain flag is 0, no further
data chaining is called for. Channel end is initiated either by the device running out of information, or by the byte count being reduced to
O. At channel end, the device may accept a
new SIO instruction, providing that a device
interrupt is not pending as a result of coding the
IZC (bit 33), ICE (bit 35), or IUE (bit 37) flags,
and no fault condition exists.
33 (IZC)
Interrupt at zero byte count. If th is flag is 1,
the lOP requests an interrupt at location X'5C'
when the byte count of th is command doub leword (as stored in the lOP register) is reduced
to O. An Ala instruction executed after the
interrupt is acknowledged results in a 1 in bit
position 10 of register R, to indicate the reason
for the interrupt.
34(CC)
Command chain. If this flag is 1, command
chaining is called for when channel end occurs.
If the previous operation did not terminate with
an "unusual end" condition, the next command
doubleword is fetched and loaded into the lOP
register associated with the device controller,
Command
Read data, store in buffer 1, data chain
Store in buffer 2, data chain
Transfer in Channel to A
If the lOP encounters two successive Transfer in Channel
commands, this is considered an lOP control error, resulting in the lOP setting the lOP control error status bit and
issuing an "lOP halt" signal to the device controller. The
lOP then halts further servicing of this command list.
The Stop command doubleword is assumed to be in the following format:
Stop. The Stop command causes certain devices to stop,
generate a channel end condition, and also request an interrupt at location X'5C' if bit 0 in the Stop command is a
1. An Ala instruction executed after the interrupt is acknowledged results in a 1 in bit position 7 of register R, to
ind icate the reason for the interrupt. (Bit positions 32-39
of the command double~ord for Stop must be zero; bit positions 8-31 and 40-63 are ignored). The Stop command is
Function
lOP Command Doublewords
91
Bit
Position
Function
Bit
Position
and the new order code is passed out to the device controller. If the CC flag is 0, no further
command chaining is called for. If both data
chaining and command chaining are called for in
the same command doubleword, data chaining
occurs if the byte count is reduced to 0 before
channel end, and command chaining occurs if
the channel end occurs before the byte count is
reduced to O.
35 (ICE)
36 (HTE)
The HTE flag must be coded identically in every
command doubleword associated with the same·
physical record. Th is means that when data
chaining occurs, the HTE flag in the new lOP
command doubleword must be the same as the
HTE flag in the previous lOP command doubleword. This restriction applies to data chaining
only, and not to command chaining.
37 (IUE)
38 (SIL)
92
and the lOP performs as spucified by the HTE and
IUE flags. Incorrect length is caused by a channel
end condition occurring before the device controller has received a count-done signal from the lOP,
or is caused by the device controller rece ivi ng a
count-done signal before end of record; e. g. ,
count-done before 80 columns have been read
from a card. Normally, a count-done signal is
sent to the device controller by the 10 P to i ndi-I
cate that all data transfer associated with the current operation has been completed. The lOP is
capable of suppressing an error condition on incorrect length, since there are many situations in
which incorrect length is a legitimate condition
and not a true error.
Interrupt at channel end. If this flag is 1, the
lOP requests an interrupt at locationX'5C' when
channel end occurs for the operation being controlled by this command doubleword. An AIO
instruction executed after the interrupt is acknowledged results in a 1 in bit position 11 of the
status information, to indicate the reason for the
interrupt. If the ICE flag is 0, no interrupt is
requested.
Halt on transmission error. If this flag is 1, any
error condition (transmission data error, transmission memory error, incorrect length error)
detected in the device controller or lOP results
in halting the I/o operation being controlled by
this command doubleword. If the HTE flag is 0,
an error condi tion does not cause the I/o operation to halt, although the error conditions are
recorded in the lOP register and returned as
part of the status information for the instructions
510, HIO, and TIO.
Interrupt on unusua I end. If th is flag is 1, the
device controller requests an interrupt at location X'5C' to be triggered when an II un usuaI
end" condition is encountered. When an
"unusual end" condition is signaled to the lOP,
further servicing of the commands for that device
is suspended. An AIO instruct ion executed after
the interrupt is acknowledged results in a 1 in
bit position 12 of register R, (status information)
to indicate the reason for the interrupt. If the
IUE flag is 0, no interrupt is requested.
Suppress incorrect length. If th is flag is 1, an
incorrect length indication is not to be classified
as an errorby the lOP, although the lOP retains
the incorrect length indi cation and provides an
indicator (bit 8 of the status response for 510,
HIO, and TIO) t~ the program. If the SIL flag
is 0, an incorrect length is considered an error
lOP Command Doublewords
Function
The SIL flag must be coded identically in every
command doubleword associated with the same
physical record. This means that when data
chaining occurs, the 51L flag in -the new lOP
command doubleword must be the same as the SIL
flag in the previous lOP command doubleword.
This restriction applies to data chaining only,
and not to command chaining.
39 (S)
5kip. If this flag is 1, the input operation
(Read or Read Backward) controlled by this comm~nd doubleword continues normally, except
that no information is stored in memory. When
used in conjunction with data chaining, the skip
operation provides the capability for selective
reading of portions of a record.
If the 5 flag is 1 for an output (Write) operation,
the lOP does not access memory, but transmits
zeros as data instead (i. e., the 10 P transmits
the number of X'OO' bytes specified in the byte
count of the command doubleword). This allows
a program to punch a blank card (by usi ng the 5
bit and a Punch Binary order with a byte count
of 120) without requiring memory access for data.
If the 5 flag is 0, the I/O operation proceeds
normally.
am
COUNT
For all commands (except Transfer in Channel and Stop)
bit positions 48-63 of the command doubleword provide
for a 16-bi t count of the number of bytes to be transmitted in the I/O operation; thus, 1 to 65,536 bytes
(16,384 words) can be specified for transfer before command chaining or data chaining is required. This field
(as stored in an lOP register) is decremented for each
byte transmitted in the I/O operation; thus, it always
contains a count of the number of bytes to be transmitted
to and from memory, and this count is returned as part of
the response information for the instructions, 510, HIO,
TIO, and TDV. An initial byte count of 0 is interpreted
as 65,536 bytes.
5. OPERATOR CONTROLS
The standard SIGMA 6 system has a processor control panel
(PCP) mounted on one of the central processor cabinets.
This panel serves as an operator's control center.
CPU RESET/CLEAR
The CPU RESET/CLEAR switch is used to initialize the central processor. When this switch is pressed, the following
operations are performed:
PROCESSOR CONTROL PANEL
The processor control panel (see Figure 7) has two distinct
functional s'ections. The upper section (labeled MAINTENANCE SECTION) is reserved for maintenance controls and
indicators, and the lower section contains the controls and
indicators for the computer operator.
POWER
The POWER switch controls all AC p,ower to the central
processor and to all units under its direct control. The
POWER switch is unl ighted when the AC power is off, and
is lighted when AC power is on. The POWER switch is
always operative.
1.
All interrupt levels are reset to the disarmed and disabled state.
2.
The ALARM, WRITE KEY, INTRPT INHIBIT, POINTER,
CONDITION CODE, FLOAT MODE, MODE, and
TRAP indicators are all reset to O's (turned off).
3.
The INSTRUCTION ADDRESS indicators are set to
X'25'.
4.
The DISPLAY indicators are set to X '02000000', which
is a LOAD CONDITIONS AND FLOATING CONTROLS IMMEDIATE (LCFI) with an R field of 0 to produce a "no operation" instruction.
- - - - - - - - - - - - - - - - - - - - - MAn.. 1[~A.'i(~ "S".fCTlQN - - - - - - - - -_ _ _ _ _ _ _ _ _ __
--M£MO~YfA;;'i.f--
••••••••
CDl CDl [XXX) tll
v
!::.
, - ,-.........,
'it
______
~tl~'_f
AI.>;;"';'~,
.-.... - . - . - -.. -... - - - - - -
'.
( t i J " I I i 1( XI X)[ XI I It XII )(' X, )[ II ,,, XXI)
Figure 8,
Processor Control Panel
Operator Controls
93
The C PU RESET/CLEAR switch does not affect any operations
that may be in process in the standard input/output system.
The CPU RESET/CLEAR switch is also used in conjucntion
with theSYS RESET/CLEAR switch to clear core memory
(Le., reset memory to all OIS). The two switches are interlocked so that both must be pressed simultaneously for the
memory clear operation to occur. The memory clear operation does not affect any general register - core memory
locations 0 through 15 are cleared instead. Also the clear
operation does not affect the memory control storage (write
locks). Note that pressing the SYS RESET/CLEAR switch
affects the I/O system and the MEMORY FAULT indicators.
3.
The PARITY ERROR MODE switch is in the CONT
(continue) position
4.
The CLOCK MODE switch is in the CONT (continuouilii
position
5.
All logic power margins are "normal"
If any of the above conditions is not satisfied, the NORMAL
MODE indicator is unlighted.
RUN
The RUN indicator is lighted when the COMPUTE switch is
in the RUN position and no halt condition exists.
I/O RESET
The I/O RESET switch is used to initialize the input/
output system. When the switch is pressed, all peripheral devices under control of the central processor are
reset to the "ready" condition, and all status, interrupt, and
control indicators in the input/output system are reset. The
I/o RESET switch does not affect any operations that may
be processed in the central processor.
LOAD
The LOAD switch initializes memory for an input operation
that uses the peripheral unit selected by the UNIT ADDRESS
switches. The detailed operation of the loading process is
described in the section "Loading Operation".
UNIT ADDRESS
The three UNIT ADDRESS switches are used to select the
peripheral unit to be used in the loading process. The left
switch has eight positions, numbered 0 through 7, designating an input/output processor. The center and right
switches each have 16 positions, numbered 0 through F
(hexadecimal) that designate a device controller/device
under the control of the lOP.
SYSTEM RESET/CLEAR
The SYS RESET/CLEAR switch is used to reset all controls
and indicators in the SIGMA6 system. Pressing this switch
causes the computer to perform all operations described for
the CPU RESET/CLEAR switch, perform all operations described for the I/O RESET switch, initialize the memory
control logic, and reset the MEMORY FAULT indicator.
The SYS RESET/CLEAR switch is also used in conjunction
with the CPU RESET/CLEAR switch to reset core memory
to OIS.
NORMAL MODE
The NORMAL MODE indicator is lighted when all the following conditions are satisfied:
1.
The WATCHDOG TIMER switch is in the NORMAL
position
2.
The INTERLEAVE SELECl switch is in the NORMAL
position
94
Processor Control Panel
WAIT
The WAIT indicator is I ighted when any of the following
halt conditions exist:
1.
The computer is executing a WAIT instruction.
2.
The program is stopped because of the ADDRESS STOP
switch.
3.
The computer is halted because of the PARITY ERROR
MODE switch.
INTERRUPT
The INTERRUPT switch is used by the operator to activate
the control panel interrupt. If the control panel interrupt
(level X I5DI) is armed when the INTERRUPT switch is
pressed, a single pulse is transmitted to the interrupt level,
advancing it to the waiting state. The INTERRUPT switch is
lighted when the control pone" interrupt level is in the
waiting state, and remains lighted until the interrupt level
advances to the active state (at which time the INTERRUPT
switch is turned off). If the control panel interrupt level
is disarmed (or already in the active state) when the INTERRUPT switch is pressed, no computer or control panel action
occurs. If the control panel interrupt level advances to the
waiting state and the level is disabled, the INTERRUPT
switch remains lighted until the level is either enabled and
allowed to advance to the active state or is returned to the
armed or disarmed state. The INTERRUPT switch is always
operative on the processor control panel.
PROGRAM STATUS DOUBLEWORD
Two rows of binary indicators are used to display the current program status doubleword (PSD). For the convenience
of use and display, the second portion of the PSD, labeled
PSW2, is arranged above the first portion, labeled PSW1.
The PSD display consists of the indicators shown in Table 9.
INSERT
The INSERT switch is used to make changes in the program
status doubleword. The switch is inactive in the center
position and is momentary in the upper (PSW2) and lower
(PSW1) positions. When the INSERT switch is moved to the
Table 9.
PSW2
PSW1
Program Status Doubleword Display
PSD
Des ignat ion
Indicator
Function
PSD Bit
Posiiton
WRITE KEY
Write key
34-35
WK
INTRPT INHIBIT
CTR
I/O
EXT
Interrupt i nhi bits
Counter interrupt group inhibit
Input/output interrupt group inhibit
External interrupts inhibit
37-39
37
38
39
CI, II, EI
CI
POINTER
Register block pointer
55-59
RP
CONDITION CODE
Condition code
0-3
CC
FLOAT MODE
SIG
ZERO
NRMZ
Floating-point mode controls
Significance trap mask
Zero trap mask
Norma I i ze mask
5-7
5
6
7
FS, FZ, FN
FS
FZ
FN
MODE
SLAVE
MAP
Machine state/memory map controls
Master/slave mode control
Memory map control
8-9
8
9
MS,MM
MS
MM
TRAP
DEC
ARITH
Arithmetic trap masks
Decimal arithmetic fault trap mask
Fixed-point arithmetic overflow trap mask
10, 11
10
11
DM, AM
DM
AM
INSTRUCTION I.DDRESS
Address of next instruction to be executed
15-31
IA
PSWl or PSW2 position, the corresponding indicators in the
program status doubleword are altered (or unchanged, according to current state of the 32 DATA switches below the
DISPLAY indicators).
2.
II
EI
Using the new value of the INSTRUCTION ADDRESS
indicators, the contents of the location pointed to by
the INSTRUCTION ADDRESS is displayed in the DISPLAY i nd i cators.
INSTR ADDR
ADDR STOP
The INSTR ADDR (instruction address) switch is inactive in
the center position; the upper position (HOLD) is latching
and the lower position (INCREMENT) is momentary. When
the switch is placed in the HOLD position, the normal process of incrementing the instruction address portion of the
program status doubleword with each instruction execution
in inhibited. If the COMPUTE switch is placed in the RUN
position while the INSTRADDR switch is at HOLD, the instruction in the location pointed to by the value of the INSTRUCTION ADDRESS indicators is executed, repeatedly,
with the INSTRUCTION ADDRESS indicators remaining unchanged. If the COMPUTE switch is moved to the STEP
position while the INSTR ADDR switch is at HOLD, the instruction is executed once each time the COMPUTE switch
is moved to STEP; the INSTRUCTION ADDRESS indicators
remain unchanged unless the instruction is LPSD, XPSD, or
a branch instruction with the branch condition satisfied.
The ADDR STOP (address stop) switch is used (with the
COMPUTE switch in the RUN position) to cause the central
processor to establ ish a halt condition and turn on the WAIT
indicator whenever the CPU accesses the memory location
whose address is equal to the SELECT ADDRESS value.
The foil owing operations are performed each time the
INSTR ADDR switch is moved from the center position to
the INCREMENT position:
1.
The current value of the INSTRUCTION ADDRESS
indicators is incremented by 1.
When the halt condition occurs, the instruction in the location pointed to by the INSTRUCTION ADDRESS indicators
appears in the DISPLAY indicators. The displayed instruc- .
tion is the one that would have been executed next, had
the halt condition not occurred. If the halt condition is
caused by an instruction access, the value of the INSTRUCTION ADDRESS indicators (at the time of the halt)
is equal to the SELECT ADDRESS value. If the halt condition is caused by execution of an instruction with an indirect reference address equal to the SELECT ADDRESS
value (i .e., by a direct address fetch), is caused by an instruction operand fetch, or is caused by an unsatisfi ed
conditional branch instruction whose effective address is
equal to the SELECT ADDRESS value, the value of the
INSTRUCTION ADDRESS indicators (at the time of the
halt) is 1 greater than the address of the instruction that
referenced the SELECT ADDRESS value.
Processor Control Pane I
95
If an interrupt or tr'::lp condi ti on is detected after the ADDRESS STOP halt condition is detected and before the CPU
reaches the normal ADDRESS STOP halt phase, the CPU
executes the instruction in the appropriate interrupt or trap
location and then enters the ADDRESS STOP halt phase. In
this case; the value of the INSTRUCTION ADDRESS indicators (at the time of the halt) is equal to the address of the
next instruction in logical sequence after the instruction in
the rnterrupt or trap location.
The ADDRESS STOP halt condition is reset when the COMPUTE switch is moved from RUN to IDLE; if the COMPUTE
switch is then moved back to RUN (or to STEP), the instructi on shown in the DISPLAY indicators is the next instruction
executed.
is latching in both the upper (1) and lower (0) positions. In
the center position, aDATAswitchrepresentsnochange, in
the upper or lower position it represents a 1 orO, respectively.
The single DATA switch is used to d,l)nge the state of the
DISPLAY indicators. The switch is inactive in the center
position and is momentary in the CLEAR and ENTER positions. When the switch is moved to the CLEAR position, all
the DISPLAY indicators are reset (turned off). When the
switch is moved to the ENTER position, the display indi cators are not affected in those positions corresponding to
DATA switches that are in the center position, but if a
DATA switch is in the 1 or position, that value is inserted into the correspondi ng i ndic ator.
°
SELECT ADDRESS
The SE LECT ADDRESS switches select the address at which
a program is to be hal ted (when used in conjunction with
the ADDR STOP switch), select the address of a location
to be altered (when used in conjunction with the STORE
swi tch), and sel ect the address of a word to be displayed
(when used in conjunction with the DISPLAY switch). Each
SELECT ADDRESS switch represents a 1 when it is in the
upper position, a'1d represents a
in the lower position.
°
STORE
The STORE switch is used to alter the contents of a general
register or a memory location. The switch is inactive in the
center position and is momentary in the INSTR ADDR and
SELECT ADDR positions. When the switch is moved to the
INSTR AD DR position, the current value of the DISPLAY indicators is stored in the location pointed toby the INSTRUCTION ADDRESS indicators; when the switch is moved tothe
SELECT ADDR position, the current value of the DISPLAY
indicators is stored in the location pointed to by the SELECT ADDRESS switches.
COMPUTE
The COMPUTE switch is used to control the execution of
instructions. The center position (IDLE) and the upper position (RUN) are both latching, and the lower position
(STEP) is momentary. When the COMPUTE switch is in the
IDLE position, all other control panel switches are operative
and the ADDRESS STOP halt and the WAIT instruction halt
conditions are reset (cleared). If the computer is in a halt
condition as a result of a memory parity error, moving the
COMPUTE switch to IDLE does not clear the memory parity
halt condition. This condition can be cleared only by pressing the SYS RESET/CLEAR switch.
When the COMPUTE switch is moved from IDLE to RUN,
the RUN indicator is lighted and the computer begins to
execute instructions (at machine speed) as follows
1.
The current setting of the DISPLAY indicators is taken
as the next instruction to be executed, regardl ess of
the contents of the location pointed to by the current
value of the INSTRUCTION ADDRESS indicators.
2.
The value of the INSTRUCTION ADDRESS indicators
is incremented by 1 unless the instruction in the DISPLAY indicators was LPSD, XPSD, or a branch instruction and the branch should occur (in which case the
INSTRUCTION ADDRESS indicators are set to the value
established by the LPSD, XPSD, or branch instruction).
3.
Instruction execution continues with the instruction in
the location pointed to by the new value of the INSTRUCTION ADDRESS indi cators.
DISPlAY
The DISPLAY switch is used to display the contents of a
general register or memory location. The switch is inactive
in the center position and is momentary in the INSTR ADDR
and SELECT ADDR positions. When the switch is moved to
the INSTR ADDR or SELECT ADDR position, the word in the
location pointed to by the indicators or switches, respectively, is loaded into the instruction register and displayed
with the DISPLAY indicators.
The 32 DISPLAY indicators are used to display a computer
word, when used together with the INSTR ADDR, STORE,
DISPLAY, and DATA switches. The DISPLAY indicators
represent the current contents of the internal CPU instructi on reg i ster.
When the COMPUTE switch is in the RUN position, the
only switches that are operative are the POWER switch, the
INTERRUPT switch, the ADDR STOP switch, the INSTR
ADDR switch (in the HOLD position), and the switches in
the maintenance section.
Each time the COMPUTE switch is moved from the IDLE to
the STEP position, the following operations occur:
1.
The current setting of the DISPLAY indicators is taken
as an instruction, and thesingle instruction is executed.
2.
The current value of the INSTRUCTION ADDRESS indicators is incremented by 1 unless the "stepped" instruction was LPSD, XPSD, or branch instruction and the
branch should occur (in which case the INSTRUCTION
ADDRESS indicators are set to the value establ ished by
the LPSD, X PSD, or branch i nstructi on).
DATA
The 32 DATA switches beneath the DISPLAY indicators are
u sed to al ter the contents of the program status doubl eword
(when used in conjunction wIth the INSERT switch) and to
alter the value of the DI.SPLAY indicators (when used in
conjunction with the single DATA switch). Each of the
32 DATA switches is inactive in the center position arld
96
Processor Control Panel
3.
The instruction in the location pointed to by the new
value of the INSTRUCTION ADDRESS indicator is
displayed in the DISPLAY indicators.
If an instruction is being stepped (executed by moving the
COMPUTE switch from IDLE to STEP), all interrupt levels
are temporarily inhibited while the instruction is being
executed; however, a trap condition can occur whi Ie the
instruction is being executed. In this case, the XPSD instruction in the appropriate trap location is executed as if
the COMPUTE switch were in the RUN position. Thus, if
a trap condition ( ) + I $ *
%
XDS Standard 8-Bit Computer Codes (EBCDIC)
XDS Standard 7-Bit Communication Codes (ANSCII)
#
@
63-character set: same as above plus
I
?
--,
XDS Standard Symbol-Code Correspondences
89-character set: same as 63-character set plus
lowercase letters
Hexadecimal Arithmetic
Addition Table
Multiplication Table
Tab Ie of Powers of Si xteen 10
Table of Powers of Ten 16
2.
ANSCII
64-character set: uppercase letters, numerals, space,
and !
$ % &
()
* + ,
/ \
< >? @
[]
Hexadecimal-Decimal Integer Conversion Table
/'\.
#
Hexadec ima I-Dec ima I Fraction Conversion Table
95-character set: same as above plus lowercase letters
and { }
Table of Powers of Two
Mathematical Constants
CONTROL CODES
XDSSTANDARDSYMBOLSANDCODES
The symbol and code standards described in this publication
are opplicable to all XDS products, both hardware and software. They may be expanded or altered from time to time
to meet changing reqcirements.
The symbols Iisted here incl ude two types: graphic symbols
and control characters. Graphic symbols are displayable
and printable; control characters are not. Hybrids are SP,
the symbol for a blank space; and DEL, the delete code,
which is not considered a control command.
Three types of code are shown: (1) the 8-bit XDS Standard
Computer Code, i.e., the XDS Extended Binary-CodedDecima I Interchange Code (EBCDIC); (2) the 7-bit American
National Standard Code for Information Interchange (ANSCIl);
and (3) the XDS standard card code.
100
Appendix A
In addition to the standard character sets listed above, the
XDS symbol repertoire includes 37 control codes and the
hybrid code DEL (hybrid code SP is considered part of all
character sets). These are I isted in the table titled XDS
Standard Symbol-Code Correspondences.
SPECIAL CODE PROPERTIES
The following two properties of all XD S standard codes wi /I
be retained for future standard code extensions:
1.
All control codes, and only the control codes, have
their two high-order bits equal to "00". DEL is not
considered a control code.
2.
No two graphic EBCDIC codes have their seven loworder bi ts equa I.
XDS STANDARD 8-BIT CIIt1PUTER CODES (EBCDIC)
Most :;'1:1'" ,.. uno Digits
Hexadec imal
.~
1£5
I~
3
0
1
2
Binary
0000 0001
0
0000
NUL OLE
ds
I
0001
SOH DCl
ss
2
0010
STX
DC2
fs
3
0011
ETX
DC3
4
0100
EOT
DC4
5
0101
6
OliO
HT
4
3
SP
BEL
si
1000
IE~ ~AN
9
1001
ENQ EM
A
1010
INAK SUB
B
lOll
~ ~~ ~
~
~Z ~ ~
_1
S
C
1100
FF
FS
<
0
1101
CR
GS
(
)
E
1110
SO
RS
+
;
US
I2
F
1111
.
SI
ESC
,
%
.Z
B
C
lOll
D
1100 1101
E
F
1110 1111
~
~~~~
.
VT
NOTES:
A
1000 1001 1010
.:~ ;~;;'
I
9
8
~~~~
Iv>
]
-
/l,
r" .",
ETB
~ 8
7
~~ / ~
~~ ~~
~~ ~ ~
~~ ~~
NL
0111
6
0010 0011 0100 0101 OliO 0111
ACK SYN
7
5
0
j
k
b
s
\1
A
J
{ 1
B
K
S
2
C
l
T
3
1
I
t
d
m
u
[ 1
0
M
U
4
] 1
E
N
V
5
t
F
0
W
6
I
e
n
v
f
0
w
g
p
x
G
P
X
7
h
q
y
H
Q
Y
8
i
r
z
I
R
Z
9
~
~~~~
@
'{'" r", "" "'.'1.
1;,,, ,,,,,.....~:iiJ~e,d,~
Wi ~ ~ ~
,
?
"
I --.
I
,
=
The characters i 1 - . appear in the XDS
63- and 59-character EBCDIC sets but not
in either of the xes ANSCII-based sets.
However, XDS software translates the characters t
into ANSCII characters
as follows:
c
:
>
l []
The characters - \ {
are ANSCII
characters that do not appear in any of the
XDS EBCDIC-based character sets, though
they are shown in the EBCDIC table.
~~~~
~~~~
~~~
,
ANSCII
EBCDIC
\ (6-0)
: (7-12)
-
(7-14)
The EBCDIC control codes in columns 0
and I and their binary representation are
exactly the some os those in the ANSCII
table, except for two interchanges: LF/NL
with NAK, and HT with ENQ.
Characters enclosed in heavy lines are
included only in the XDS standard 63and 59-character EBCDIC sets.
These characters are included only in the
XDS standard 89-chorocter EBCDIC set.
XDS STANDARD 7-81T COMMUNICATION CODES (ANSCII) 1
Most Significant Digits
Decimal
rows)
(col's.)-
I
2
1
Binary
0
0000
NUL DLE
SP
I
0001
SOH DCI
!
2
0010
STX
DC2
II
3
0011
ETX
4
3
4
7
6
5
1 Most significant bit, added for 8-bit format, is either 0 or even parity.
xOOO xOOI xOIO xOll xlOO xlOI xll0 xiii
5
0
@
P
,
I
A
Q
a
q
Columns 0-1 are control codes.
P
Columns 2-5 correspond to the XDS 64-character ANSCII set.
Columns 2-7 correspond to the XDS 95-character ANSCII set.
2
B
R
b
r
DC3
,
3
C
S
c
s
0100
EOT DC4
S
4
0
T
d
t
is
5
0101
ENQ NAK
%
5
E
U
e
u
is
6
0110
ACK SYN
/l,
6
F
V
f
v
7
G
W
g
w
'0.
0
C
0
~
1
0
4
On many current teletypes, the symbol
is
(5-14)
(5-15)
ESC or ALTMODE control (7-14)
and none of the symbols appearing in columns 6-7 are provided. Except for the three
symbol differences noted above, therefore, such teletypes provide all the characters in
the XDS 64-character ANSCII set. (The XDS 7015 Remote Keyboard Printe( provides the
64-character ANSCII set also, but prints ..... as /I .)
7
0111
BEL
ETB
.
'c01 8
1000
BS
CAN
(
8
H
X
h
X
S
9
1001
HT
EM
)
I
Y
i
Y
(2-1)
1010
LF
NL
is
10
SUB
.
9
:
J
Z
j
z
is
(5-11)
11
1011
VT
ESC
+
;
K
[ 5
k
{
is
(5-13)
is
(5-14)
v;
~
12
1100
FF
FS
,
13
1101
CR
GS
-
14
1110
SO
RS
15
1111
SI
US
'---"
/
On the XDS 7670 Remote Batch Terminal, the symbol
<
L
\
I
I
I
=
M
] 5
m
l
>
N
n
-
?
0
0
DEL
4 ..... 5
-
4
4
and none of the symbols appearing in columns 6-7 are provided. Except for the four symbol
differences noted above, therefore, this terminal provides all the characters in the XDS 64character ANSCII set.
,
~ndix
A
101
XDS STANDARD SYMBOL -CODE CORRESPONDENCES
EBCDICt
Hex. Dec.
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
0
1
2
3
4
5
6
Symbol
Card Code
Meaning
Remarks
00 through 23 and 2F are control codes.
8
9
10
11
12
13
14
15
NUL
SOH
STX
ETX
EOT
HT
ACK
BEL
B50rEOM
ENQ
NAK
VT
FF
CR
50
51
12-0-9-8-1
12-9-1
12-9-2
12-9-3
12-9-4
12-9-5
12-9-6
12-9-7
12-9-8
12-9-8-1
12-9-8-2
12-9-8-3
12-9-8-4
12-9-8-5
12-9-8-6
12-9-8-7
0-0
0-1
0-2
0-3
0-4
0-9
0-6
0-7
0-8
0-5
1-5
O-Ii
0-12
0-13
0-14
0-15
null
start of header
start of te~d
end of t~t
end of transmission
hori zontGJ tab
acknowledge (positive)
bell
backspace or end of message
enquiry
negative acknowledge
vertical tab
form feed
carriage return
shift out
shift in
10
11
12
13
14
15
16
17
18
19
lA
1B
1C
10
1E
IF
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DlE
DCl
DC2
DC3
DC4
IF or Nl
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
12-11-9-8-1
11-9-1
11-9-2
11-9-3
11-9-4
11-9-5
11-9-6
11-9-7
11-9-8
11-9-8-1
11-9-8-2
11-9-8-3
11-9-8-4
11-9-8-5
11-9-8-6
11-9-8-7
1-0
1-1
1-2
1-3
1-4
0-10
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15
data link escape
device control 1
devi ce control 2
device control 3
device control 4
line feed or new line
sync
end of transmission block
cancel
end of medium
substitute
escape
fi Ie separator
group separator
record separator
unit separator
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
7
ds
ss
fs
si
11-0-9-8-1
0-9-1
0-9-2
0-9-3
0-9-4
0-9-5
0-9-6
0-9-7
0-9-8
0-9-8-1
0-9-8-2
0-9-8-3
0-9-8-4
0-9-8-5
0-9-8-6
0-9-8-7
12-11-0-9-8-1
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-8-1
9-8-2
9-8-3
9-8-4
9-8-5
9-8-6
9-8-7
tHexadecimal and dec"imal notation.
tt Decimal
102
AN scutt
notation (column-row).
Appendix A
digit selector
significance start
field separation
immediate significance start
EOM is used only onXD5 Keyboord/
Printers Models 7012, 7020, 8091,
and 8092.
Replaces characters with parity error.
20 through 23 are used with
Sigma EDIT BYTE STRING (EBS)
instruction - not input/output control codes.
24 through 2E are unassigned.
30 through 3F are unassigned.
XDS STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)
E8CDICt
Hex. Dec.
40
41
42
43
44
45
46
47
48
49
4A
48
4C
4D
4E
4F
64
65
66
67
68
69
70
71
72
73
74
75
76
50
51
52
53
54
55
56
57
58
59
SA
58
5C
5D
5E
5F
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
60
61
62
63
64
65
66
67
68
69
6A
68
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
78
7C
7D
7E
7F
77
78
79
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Symbol
Card Code
ANSClI
SP
blank
12-0-9-1
12-0-9-2
12-0-9-3
12-0-9-4
12-0-9-5
12-0-9-6
12-0-9-7
12-0-9-8
12-8-1
12-8-2
12-8-3
12-8-4
12-8-5
12-8-6
12-8-7
2-0
i
or '
<
(
+
I or
I
I
8.
!
$
*
)
;
- or -,
/
......
,
%
-
>
?
II
@
I
=
"
Meaning
Remarks
blank
41 through 49 wi II not be assigned.
12
12-11-9-1
12-11-9-2
12-11-9-3
12-11-9-4
12-11-9-5
12-11-9-6
12-11-9-7
12-11-9-8
11-8-1
".1-8-2
11-8-3
11-8-4
11-8-5
11-8-6
11-8-7
6-0
2-14
3-12
2-8
2-11
7-12
cent or accent grave
period
less than
left parenthesis
plus
vertical bar or broken bar
2-6
ampersand
Accent grove used for left single
quote. On model 7670, \ not
available, and i:: ANSCII 5-11.
On Model 7670, : not available,
and I :: ANSCII 2-1.
51 through 59 will not be assigned.
11
0-1
11-0-9-2
11-0-9-3
11-0-9-4
11-0-9-5
11-0-9-6
11-0-9-7
11-0-9-8
0-8-1
12-11
0-8-3
0-8-4
0-8-5
0-8-6
0-8-7
12-11-0
12-11-0-9-1
12-11-0-9-2
12-11-0-9-3
12-11-0-9-4
12-11-0-9-5
12-11-0-9-6
12-11-0-9-7
12-11-0-9-8
8-1
8-2
8-3
8-4
8-5
8-6
8-7
tt
2-1
2-4
2-10
2-9
3-11
7-14
exclamation point
dollars
asterisk
right parenthesis
semicolon
tilde or logical not
2-13
2-15
minus, dash, hyphen
slosh
On Model 7670, ! is I.
On Model 7670, - is not available,
and -. :: ANSCII 5-14.
62 through 69 wi II not be assigned.
5-14
2-12
2-5
5-15
3-14
3-15
circumflex
comma
percent
underline
greater than
question mark
On Model 7670 ~ is""'.
7015 ...... is " (caret).
On Model
Underline is sometimes called "break
character"; may be printed along
bottom of character line.
70 through 79 wi II not be assigned.
I
3-10
2-3
4-0
2-7
3-13
2-2
colon
number
at
apostrophe (right single quote)
equals
quotation mark
tHexadecimal and decimal notation.
ttDecimal notation (c.,fumn-row).
Appendix A
103
XDS STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)
EBCDIC t
Hex. Dec.
80
81
82
83
84
85
86
87
88
89
8A
88
8C
80
8E
8F
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
90
91
92
93
94
95
96
97
98
99
9A
98
90
9E
9F
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
BO
Bl
B2
B3
B4
B5
B6
B7
B8
89
BA
BB
BC
BD
8E
BF
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
9C
Symbol
a
b
c
d
e
f
g
h
i
j
k
I
~
n
0
p
q
r
s
t
u
v
w
x
y
z
\
t
J
[
]
Card Code
12-0-8-1
12-0-1
12-0-2
12-0-3
12-0-4
12-0-5
12-0-6
12-0-7
12-0-8
12-0-9
12-0-8-2
12-0-8-3
12-0-8-4
12-0-8-5
12-0-8-6
12-0-8-7
12-11-8-1
12-11-1
12-11-2
12-11-3
12-11-4
12-11-5
12-11-6
12-11-7
12-11-8
12-11-9
12-11-8-2
12-11-8-3
12-11-8-4
12-11-8-5
12-11-8-6
12-11-8-7
11-0-8-1
11-0-1
11-0-2
11-0-3
11-0-4
11-0-5
11-0-6
11-0-7
11-0-8
11-0-9
11-0-8-2
11-0-8-3
11-0-8-4
11-0-8-5
11-0-8-6
11-0-8-7
12-11-0-8-1
12-11-0-1
12-11-0-2
12-11-0-3
12-11-0-4
12-11-0-5
12-11-0-6
12-11-0-7
12-11-0-8
12-11-0-9
12-11-0-8-2
12-11 -0-8-3
12-11-0-8-4
12-11-0-8-5
12-11-0-8-6
12-11-0-8-7
tHexadecimal and deci.mal notation.
ttDecimal notation (column-row).
104
Appendi X A
ANSCU
tt
Meaning
Remarks
80 is unassigned.
81-89, 91-99, A2-A9 comprise the
lowercase alphabet. Available
only in XDS standard 89- and 95character sets.
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
8A through 90 are unassigned.
6-10
6-11
6-12
6-13
6-14
6-15
7-0
7-1
7-2
9A through AI are unassigned.
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
AA through
5-12
7-11
7-13
5-11
5-13
backslash
left brace
right brace
left bracket
right bracket
eo are
unassigned.
On Model 7670, ~ is i.
On Model 7670, is!.
B6 through SF are unassigned.
XDS STANDARD SYMBOL-CODE CORRESPONDENCES (cont.)
EBCDICt
Hex. Dec.
192
CO
193
Cl
194
C2
195
C3
196
C4
197
C5
198
C6
199
C7
200
C8
201
C9
CA 202
203
CB
204
CC
CD 205
206
CE
207
CF
DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
224
225
226
227
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
FE
FF
2L8
229
230
231
232
233
234
235
236
237
238
239
Symbol
A
B
C
D
E
F
G
H
I
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
X
Y
Z
0
1
2
3
4
5
6
7
8
9
DEL
Card Code
12-0
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-0-9-8-2
12-0-9-8-3
12-0-9-8-4
12-0-9-8-5
12-0-9-8-6
12-0-9-8-7
11-0
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
12-11-9-8-2
12-11-9-8-3
12-11-9-8-4
12-11-9-8-5
12-11-9-8-6
12-11-9-8-7
0-8-2
11-0-9-1
0-2
0-3
0-4
0-5
0-6
0-7
0-8
0-9
11-0-9-8-2
11-0-9-8-3
11-0-9-8-4
11-0-9-8-5
11-0-9-8-6
11-0-9-8-7
0
1
2
3
4
5
6
7
8
9
12-11-0-9-8-2
12-11-0-9-8-3
12-11-0-9-8-4
12-11-0-9-8-5
12-11-0-9-8-6
12-11-0-9-8-7
ANScn tt
Meaning
Remarks
CO is unassigned.
Cl-C9, DI -D9, E2-E9 comprise the
uppercase alphabet.
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
CA through CF will not be assigned.
DO is unassigned.
4-10
4-11
4-12
4-13
4-14
4-15
5-0
5-1
5-2
DA through DF will not be assigned.
EO, E1 are unassigned.
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
EA through EF will not be assigned.
3-0
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
FA through FE will not be assigned.
delete
Special - neither graphic nor control symbol.
tHexadecimal and decimal notation.
ttDecimal notation (c~lumn-row).
Appendi X A
105
HEXADECIMAL ARITHMETIC
ADDITION TABLE
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
1
02
03
04
05
06
07
08
09
OA
OS
DC
00
OE
OF
10
2
03
04
05
06
07
08
09
OA
OB
DC
00
OE
OF
10
11
3
04
05
06
07
08
09
OA
OB
DC
00
OE
OF
10
11
12
4
05
06
07
08
09
OA
OB
DC
00
OE
OF
10
11
12
13
5
06
07
08
09
OA
OB
DC
00
OE
OF
10
11
12
13
14
6
07
08
09
OA
OB
DC
00
OE
OF
10
11
12
13
14
15
7
08
09
OA
OB
DC
00
OE
OF
10
11
12
13
14
15
16
8
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
9
OA
OB
DC
OD
OE
OF
10
11
12
13
14
15
16
17
18
A
OB
DC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
B
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
C
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
0
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
E
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
MULTIPLICATION TABLE
106
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
2
04
06
08
OA
DC
OE
10
12
14
16
18
1A
1C
1E
3
06
09
DC
OF
12
15
18
1B
1E
21
24
27
2A
2D
4
08
OC
10
14
18
1C
20
24
28
2C
30
34
38
3C
5
OA
OF
14
19
1E
23
28
20
32
37
3C
41
46
4B
6
OC
12
18
1E
24
2A
30
36
3C
42
48
4E
54
5A
7
OE
15
1C
23
2A
31
38
3F
46
4D
54
5B
62
69
8
10
18
20
28
30
38
40
48
50
58
60
68
70
78
9
12
1B
24
20
36
3F
48
51
5A
63
6C
75
7E
87
A
14
1E
28
32
3C
46
50
5A
64
6E
78
82
8C
96
B
16
21
2C
37
42
4D
58
63
6E
79
84
8F
9A
A5
C
18
24
30
3C
48
54
60
6C
78
84
90
9C
A8
B4
D
1A
27
34
41
4E
5B
68
75
82
8F
9C
A9
B6
C3
E
1C
38
46
54
62
70
7E
8C
9A
A8
B6
C4
02
F
1E
2A
20 .
3C
4B
5A
69
78
87
96
A5
B4
C3
D2
E1
Appendix A
TABLE OF POWERS OF SIXTEEN II
n
o
16
0.10000 00000 00000 00000 x
10
0.62500 00000 00000 00000 x
10-
10- 2
10- 3
256
2
0.39062 50000 00000 00000
x
4 096
3
0.24414 06250 00000 00000
x
65 536
4
0.15258 78906 25000 00000
x
1 048 576
5
0.95367 43164 06250 00000
x
16 777 216
6
0.59604 64477 53906 25000 x
10-
268 435 456
7
0.37252 90298 46191
40625
x
4 294 967 296
8
0.23283 06436 53869 62891
x
68 719 476 736
9
0.14551
91522 83668 51807
x
x
10- 8
9
1010
1012
1013
1014
1015
1016
1018
10-
1 099 511
627 776
10
0.90949 47017 72928 23792
186 044 416
11
0.56843 41886 08080
474 976 710 656
12
0.35527
4 503 599 627 370 496
13
0.22204 46049 25031
72 057 594 037 927 936
14
0.13877 78780 78144 56755 x
15
0.86736
17 592
281
1 152 921
1
504 606 846 976
14870 x
13678 80050 09294 x
30808
17379 88403 54721
x
x
10- 4
10- 6
7
TABLE OF POWERS OF TEN 16
o
A
1.0000
0000
0000
0000
0.1999
9999
9999
999A
64
2
0.28F5
C28F
5C28
F5C3
x
3E8
3
0.4189
374B
C6A7
EF9E
x
16- 1
16- 2
2710
4
0.680B
8BAC
710C
B296
x
16- 3
86AO
5
0.A7C5
AC47
1B47
8423
x
16- 4
F
4240
6
0.10C6
F7 AO
B5E 0
8037
x
16- 4
98
9680
7
0.1 A07
F 29 A
BCAF
4858
x
5F5
E100
8
0.2AF3
1 DC4
61 1 8
73BF
x
3B9A
CAOO
9
0.44B8
2FAO
9B5A
52CC
x
2
540B
E400
10
0.6 OF 3
7F67
5EF6
EAOF
x
16- 7
16- 8
17
4876
E800
11
O.AFE B
F FOB
CB24
AAFF
x
16- 9
E8
D4A5
1000
12
0.1197
9981
2DEA
1 119
x
918
4E72
AOOO
13
0.lC25
C268
4976
81C2
x
5AF3
107A
4000
14
0.2009
370 D
4257
3604
x
3
807E
A4C6
8000
15
0.480E
BE7B
9D58
566D
x
23
86F2
6FC1
0000
16
0.734A
CA5 F
6226
FOAE
x
163
4578
5 D8A
0000
17
0.B877
AA32
36A4
B449
x
DEO
B6B3
A764
0000
18
0.1272
5 DD1
D243
ABA1
x
8AC7
2304
89E8
0000
19
0.1083
C94F
B6D2
AC35
x
16- 5
16-6
16- 9
16- 10
16 -11
16- 12
16- 13
16- 14
16- 14
16- 15
Appendix A
107
HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE
The table below provides for direct conversions between hexadecimal integers in the range O-FFF and decimal integers in
the range 0-4095. For conversion of larger integers, the
table values may be added to the following figures:
Hexadecimal
Decimal
Hexadecima I
Decimal
01000
02 000
03 000
04 000
05 000
06 000
07 000
08 000
09 000
OA 000
OB 000
OC 000
00000
OE 000
OF 000
10 000
11000
12000
13000
14000
15 000
16000
17 000
18000
19000
lA 000
lB 000
lC 000
10000
IE 000
IF 000
4 096
8 192
12 288
16 384
20480
24576
28672
32768
36864
40960
45056
49 152
53 248
57344
61440
65536
69632
73728
77 824
81 920
86 016
90 112
94208
98304
102400
106496
110 592
114688
118784
122 880
126 976
20000
30000
40000
50000
60000
70000
80000
90000
AO 000
BO 000
CO 000
DO 000
EO 000
FO 000
100000
200000
300000
400000
500000
600 000
700000
800 000
900 000
AOO 000
BOO 000
COO 000
000 000
EOO 000
FOO 000
1 000 000
2000 000
131072
196608
262 144
327680
393 216
458752
524 288
589824
655 360
720896
786 432
851 968
917 504
983040
1 048576
2 097 152
3 145 728
4 194304
5 242 880
6 291 456
7 340 032
8388608
9437 184
10485 760
11 534 336
12582912
13631 488
14680064
15728640
16777 216
33554432
Hexadecimal fractions may be converted to decimal fractions
as follows:
1.
Express the hexadecimal fraction as an integer times
16-n, where n is the number of significant hexadecimal
places to the right of the hexadecimal point.
O. CA9BF3 16 = CA9 BF3 16 x 16-6
2.
Find the decimal equivalent of the hexadecimal integer
CA9 BF3
3.
16
= 13 278 195
10
Multiply the decimal equivalent by 16-n
13 278 195
x 596 046 448 x 10- 16
0.791 442096
10
Decimal fractions may be converted to hexadecimal fractions
by successively multiplying the dec imal fraction by 16 ,
10
After each multiplication, the integer portion is removea to
form a hexadecimal fraction by bui Iding to the right of the
hexadecimal point. However, since decimal arithmetic is
used in this conversion, the integer portion of each product
must be converted to hexadecimal numbers.
Example: Convert 0.895lD to its hexadecimal equivalent
0.895
16
------@.320
~
,.-----@.120
~
Z
0.E51 E ..
·----@.720
16
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
000
010
020
030
0000
0016
0032
0048
0001
0017
0033
0049
0002
0018
0034
0050
0003
0019
0035
0051
0004
0020
0036
0052
0005
0021
0037
0053
0006
0022
0038
0054
0007
0023
0039
0055
0008
0024
0040
0056
0009
0025
0041
0057
0010
0026
0042
0058
0011
0027
0043
0059
0012
0028
0044
0060
0013
0029
0045
0061
0014
0030
0046
0062
0015
0031
0047
0063
040
050
060
070
0064
0080
0096
0112
0065
0081
0097
0113
0066
0082
0098
0114
0067
0083
0099
0115
0068
0084
0100
0116
0069
0085
OlDl
0117
0070
0086
0102
0118
0071
0087
0103
0119
0072
0088
0104
0120
0073
0089
0105
0121
0074
0090
0106
0122
0075
0091
OlD7
0123
0076
0092
0108
0124
0077
0093
0109
0125
0078
0094
0110
0126
0079
0095
0111
0127
080
090
OAO
OBO
0128
0144
0160
0176
0129
0145
0161
0177
0130
0146
0162
0178
0131
0147
0163
0179
0132
0148
0164
0180
0133
0149
0165
0181
0134
0150
0166
0182
0135
0151
0167
0183
0136
0152
0168
0184
0137
0153
0169
0185
0138
0154
0170
0186
0139
0155
0171
0187
0140
0156
0172
0188
0141
0157
0173
0189
0142
0158
0174
0190
0143
0159
0175
0191
OCO
000
OEO
OFO
0192
0208
0224
0240
0193
0209
0225
0241
0194
0210
0226,
0242
0195
0211
0227
0243
0196
0212
0228
0244
0197
0213
0229
0245
0198
0214
0230
0246
0199
0215
0231
0247
0200
0216
0232
0248
0201
0217
0233
0249
0202
0218
0234
0250
0203
0219
0235
0251
0204
0220
0236
0252
0205
0221
0237
0253
0206
0222
0238
0254
0207
0223
0239
0255
108
Appendi x A
HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)
0
1
2
A
D
F
3
4
5
6
7
8
9
0259
0275
0291
0307
0260
0276
0292
0308
0261
0277
0293
0309
0262
0278
0294
0310
0263
0279
0295
0311
0264
0280
0296
0312
0265
0281
0297
0313
0266 0267
0282 0283
0298 0299
0314 0315
0268
0284
0300
0316
0269 0270
0285 0286
0301 0302
0317 0318
0324 0325
0340 0341
0356 0357
0372 0373
0326
0342
0358
0374
0327
0343
0359
0375
0328
0344
0360
0376
0329
0345
0361
0377
0330 0331
0346 0347
0362 0363
0378 0379
0332
0348
0364
0380
0333 0334 0335
0349 0350 0351
0365 0366 0367
0381 0382 0383
B
C
E
100
110
120
130
0256 0257 0258
0272 0273 0274
0288 0289 0290
0304 0305 0306
140
150
160
170
0320
0336
0352
0368
0321
0337
0353
0369
0322 0323
0338 0339
0354 0355
0370 0371
180
190
lAO
lBO
0384
0400
0416
0432
0385
0401
0417
0433
0386
0402
0418
0434
0387
0403
0419
0435
0388
0404
0420
0436
0389
0405
0421
0437
0390
0406
0422
0438
0391
0407
0423
0439
0392
0408
0424
0440
0393
0409
0425
0441
0394
0410
0426
0442
0395
0411
0427
0443
0396 0397
0412 0413
0428 0429
0444 0445
0398
0414
0430
0446
0399
0415
0431
0447
lCO
lDO
lEO
lFO
0448
0464
0480
0496
0449
0465
0481
0497
0450
0466
0482
0498
0451
0467
0483
0499
0452
0468
0484
0500
0453
0469
0485
0501
0454
0470
0486
0502
0455
0471
0487
0503
0456
0472
0488
0504
0457
0473
0489
0505
0458
0474
0490
0506
0459
0475
0491
0507
0460
0476
0492
0508
0461
0477
0493
0509
0462
0478
0494
0510
0463
0479
0495
0511
200
210
220
230
0512
0528
0544
0560
0513
0529
0545
0561
0514 0515
0530 J531
0546 0547
0562 0563
0516 0517 0518
0532 0533 0534
0548 0549 0550
0564 0565 0566
0519
0535
0551
0567
0520
0536
0552
0568
0521
0537
0553
0569
0522
0538
0554
0570
0523
0539
0555
0571
0524
0540
0556
0572
0525 0526
0541 0542
0557 0558
0573 0574
0527
0543
0559
0575
240
250
260
270
0576
0592
0608
0624
0577
0593
0609
0625
0578
0594
0610
0626
0580 0581 0582 0583
0596 0597 0598 0599
0612 0613 0614 0615
0628 0629 0630 0631
0584
0600
0616
0632
0585
0601
0617
0633
0586 0587
0602 0603
0618 0619
0634 0635
0588
0604
0620
06,36
0589
0605
0621
0637
0590
0606
0622
0638
0591
0607
0623
0639
280
290
2AO
2BO
0640
0656
0672
0688
0641
0657
0673
0689
0642 0643
0658 0659
0674 0675
0690 0691
0655
0671
0687
0703
2CO
2DO
2EO
2FO
0704
0720
0736
0752
300
310
320
330
0579
0595
0611
0627
0271
0287
0303
0319
0645
0661
0677
0693
0646
0662
0678
0694
0647
0663
0679
0695
0648
0664
0680
0696
0649
0665
0681
0697
0650 0651
0666 0667
0682 0683
0698 0699
0652
0668
0684
0700
0653
0669
0685
0701
0654
0670
0686
0702
0705 0706 0707
0721 0722 0723
0737 0738 0739
0753 0754 0755
0708 0709
0724 0725
0740 0741
0756 0757
0710
0726
0742
0758
0711
0727
0743
0759
0712
0728
0744
0760
0713
0729
0745
0761
0714
0730
0746
0762
0715
0731
0747
0763
0716
0732
0748
0764
0717
0733
0749
0765
0718 0719
0734 0735
0750 0751
0766 0767
0768
0784
0800
0816
0769
0785
0801
0817
0770
0786
0802
0818
0771
0787
0803
0819
0772 0773 0774
0788 0789 0790
0804 0805 0806
0820 0821 0822
0775
0791
0807
0823
0776
0792
0808
0824
0777
0793
0809
0825
0778
0794
0810
0826
0779
0795
0811
0827
0780
0796
0812
0828
0781
0797
0813
0829
0782
0798
0814
0830
0783
0799
0815
0831
340
350
360
370
0832
0848
0864
0880
0833
0849
0865
0881
0834
0850
0866
0882
0835
0851
0867
0883
0836 0837 0838 0839
0852 0853 0854 0855
0868 0869 0870 0871
0884 0885 0886 0887
0840
0856
0872
0888
0841
0857
0873
0889
0842
0858
0874
0890
0843
0859
0875
0891
0844
0860
0876
0892
0845
0861
0877
0893
0846
0862
0878
0894
0847
0863
0879
0895
380
390
3AO
3BO
0896
0912
0928
0944
0897
0913
0929
0945
0898
0914
0930
0946
0899
0915
0931
0947
0900
0916
0932
0948
0904
0920
0936
0952
0905
0921
0937
0953
0906 0907
0922 0923
0938 0939
0954 0955
0908
0924
0940
0956
0909
0925
0941
0957
0910
0926
0942
0958
0911
0927
0943
0959
3CO
3DO
3EO
3FO
0960 0961 0962 0963
0976 0977 0978 0979
0992 0993 0994 0995
1008 1009 IJIO 1011
0644
0660
0676
0692
0901
0917
0933
0949
0902
0918
0934
0950
0903
0919
0935
0951
0964 0965 0966 0967
0980 0981 0982 0983
0996 0997 0998 0999
1012 1013 1014 1015
0968 0969 0970 0971
0984 0985 0986 0987
1000 .1001 1002 1003
1016 1017 1018 1019
0972 0973 0974 0975
0988 0989 0990 0991
1004 1005 1006 1007
1020 1021 1022 1023
Appendi x A
109
HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)
110
0
1
2
3
4
400
410
420
430
1024
1040
1056
1072
1025
1041
1057
1073
1026
1042
1058
1074
1027
1043
1059
1075
1028
1044
1060
1076
440
450
460
470
1088
1104
1120
1136
1089
1105
1121
1137
1090
1106
1122
1138
1091
1107
1123
1139
480
490
4AO
480
1152
1168
1184
1200
1153
1169
1185
1201
1154
1170
1186
1202
4(0
400
4EO
4FO
1216
1232
1248
1264
1217
1233
1249
1265
500
510
520
530
1280
1296
1312
1328
540
550
560
570
7
8
9
A
B
C
0
E
F
1029 1030
1045 1046
1061 1062
1077 1078
1031
1047
1063
1079
1032
1048
1064
lOBO
1033
1049
1065
1081
1034
1050
1066
1082
1035
1051
1067
1083
1036
1052
1068
1084
1037
1053
1069
1085
1038
1054
1070
1086
1039
1055
1071
1087
1092
1108
1124
1140
1093
1109
1125
1141
1094
1110
1126
1142
1095
1111
1127
1143
1096
1112
1128
1144
1097
1113
1129
1145
1098
1114
1130
1146
1099
1115
1131
1147
1100
1116
1132
1148
1101
1117
1133
1149
1102
1118
1134
1150
1103
1119
1135
1151
1155
1171
1187
1203
1156
1172
1188
1204
1157
1173
1189
1205
1158
1174
1190
1206
1159
1175
1191
1207
1160
1176
1192
1208
1161 1162
1177 1178
1193 1194
1209 1210
1163
1179
1195
1211
1164
1180
1196
1212
1165
1181
1197
1213
1166
1182
1198
1214
1167
1183
1199
1215
1218
1234
1250
1266
1219
1235
1251
1267
1220
1236
1252
1268
1221
1237
1253
1269
1222
1238
1254
1270
1223
1239
1255
1271
1224
1240
1256
1272
1225
1241
1257
1273
1226
1242
1258
1274
1227
1243
1259
1275
1228
1244
1260
1276
1229
1245
1261
1277
1230
1246
1262
1278
1231
1247
1263
1279
1281
1297
1313
1329
1282
1298
1314
1330
1283
1299
1315
1331
1284
1300
1316
1332
1285
1301
1317
1333
1286
1302
1318
1334
1287
1303
1319
1335
1288
1304
1320
1336
1289 1290
1305 1306
1321 1322
1337 1338
1291
1307
1323
1339
1292
1308
1324
1340
1293
1309
1325
1341
1294
1310
1326
1342
1295
1311
1327
1343
1344
1360
1376
1392
1345
1361
1377
1393
1346
1362
1378
1394
1347
1363
1379
1395
1348
1364
1380
1396
1349
1365
1381
1397
1350
1366
1382
1398
1351
1367
1383
1399
1352
1368
1384
1400
1353 1354
1369 1370
1385 1386
1401 1402
1355
1371
1387
1403
1356
1372
1388
1404
1357
1373
1389
1405
1358
1374
1390
1406
1359
1375
1391
1407
580
590
SAO
5BO
1408
1424
1440
1456
1409
1425
1441
1457
1410
1426
1442
1458
1411
1427
1443
1459
1412
1428
1444
1460
1413
1429
1445
1461
1414
1430
1446
1462
1415
1431
1447
1463
1416
1432
1448
1464
1417 1418
1433 1434
1449 1450
1465 1466
1419
1435
1451
1467
1420
1436
1452
1468
1421
1437
1453
1469
1422
1438
1454
1470
1423
1439
1455
1471
5(0
5DO
5EO
5FO
1472
1488
1504
1520
1473
1489
1505
1521
1474
1490
1506
1522
1475
1491
1507
1523
1476
1492
1508
1524
1477
1493
1509
1525
1478
1494
1510
1526
1479
1495
1511
1527
1480
1496
1512
1528
1481
1497
1513
1529
1482
1498
1514
1530
1483
1499
1515
1531
1484
1500
1516
1532
1485
1501
1517
1533
1486
1502
1518
1534
1487
1503
1519
1535
600
610
620
630
1536
1552
1568
1584
1537
1553
1569
1585
1538
1554
1570
1586
1539
1555
1571
1587
1540
1556
1572
1588
1541
1557
1573
1589
1542
1558
1574
1590
1543
1559
1575
1591
1544
1560
1576
1592
1545
1561
1577
1593
1546
1562
1578
1594
1547
1563
1579
1595
1548
1564
1580
1596
1549
1565
1581
1597
1550
1566
1582
1598
1551
1567
1583
1599
640
650
660
670
1600
1616
1632
1648
1601
1617
1633
1649
1602
1618
1634
1650
1603
1619
1635
1651
1604
1620
1636
1652
1605
1621
1637
1653
1606
1622
1638
1654
1607
1623
1639
1655
1608
1624
1640
1656
1609 1610
1625 1626
1641 1642
1657 1658
1611
1627
1643
1659
1612
1628
1644
1660
1613
1629
1645
1661
1614
1630
1646
1662
1615
1631
1647
1663
680
690
6AO
6BO
1664
1680
1696
1712
1665
1681
1697
1713
1666
1682
1698
1714
1667
1683
1699
1715
1668
1684
1700
1716
1669
1685
1701
1717
1670
1686
1702
1718
1671
1687
1703
1719
1672
1688
1704
1720
1673 1674
1689 1690
1705 1706
1721 1722
1675
1691
1707
1723
1676
1692
1708
1724
/677 1678
1693 1694
1709 1710
1725 1726
1679
1695
1711
1727
6(0
600
6EO
6FO
1728
1744
1760
1776
1729
1745
1761
1777
1730
1746
1762
1778
1731
1747
1763
1779
1732
1748
1764
1780
1733
1749
1765
1781
1734
1750
1766
1782
1735
1751
1767
1783
1736
1752
1768
1784
1737
1753
1769
1785
1739
1755
1771
1787
1740
1756
1772
1788
1741
1757
1773
1789
1743
1759
1775
1791
Appendix A
5
6
1738
1754
1770
1786
1742
1758
1774
1790
HEXADECIMAL-DECIMAL INTEGER CONYERSION TABLE (cant.)
0
1
2
3
4
5
8
9
A
B
C
D
E
F
700
710
720
730
1792
1808
1824
1840
1793
1809
1825
1841
1794
1810
1826
1842
1795
1811
1827
1843
1796
1812
1828
1844
1797
1813
1829
1845
1800
1816
1832
1848
1801
1817
1833
1849
1802
1818
1834
1850
1803
1819
1835
1851
1804
1820
1836
1852
1805
1821
1837
1853
1806
1822
1838
1854
1807
1823
1839
1855
740
750
760
770
1856
1872
1888
1904
1857 1858
1873 1874
1889 1890
1905 1906
1859
1875
1891
1907
1860
1876
1892
1908
1861 1862 1863
1877 1878 1879
1893 1894 1895
1909 1910 1911
1864 1865 1866 1867
1880 1881 1882 1883
1896 1897 1898 1899
1912 1913 1914 1915
1868
1884
1900
1916
1869
1885
1901
1917
1870
1886
1902
1918
1871
1887
1903
1919
780
790
7AO
7BO
1920
1936
1952
1968
1921 1922
1937 1938
1953 1954
1969 1970
1923
1939
1955
1971
1924
1940
1956
1972
1925
1941
1957
1973
1926 1927
1942 1943
1958 1959
1974 1975
1928 1929 1930 1931
1944 1945 1946 1947
1960 1961 1962 1963
1976 1977 1978 1979
1932 1933
1948 1949
1964 1965
1980 1981
1934
1950
1966
1982
1935
1951
1967
1983
7CO
7DO
7EO
7FO
1984 1985 1986 1987
2000 2001 2002 2003
2016 2017 2018 2019
2032 2033 2034 2035
1988 1989 1990 1991
2004 2005 2006 2007
2020 2021 2022 2023
2036 2037 2038 2039
1992
2008
2024
2040
1993 1994 1995
2009 2010 2011
2025 2026 2027
2041 2042 2043
1996 1997
2012 2013
2028 2029
2044 2045
1998 1999
2014 2015
2030 2031
2046 2047
800
810
820
830
2048 2049
2064 2065
2080 2081
2096 2097
2050 2051
2066 2067
2082 2083
2098 2099
2052
2068
2084
2100
2053
2069
2085
2101
2054
2070
2086
2102
2055
2071
2087
2103
2056 2057
2072 2073
2088 2089
2104 2105
2058
2074
2090
2106
2059
2075
2091
2107
2060 2061
2076 2077
2092 2093
2108 2109
2062
2078
2094
2110
840
850
860
870
2112
2128
2144
2160
2114 2115
2130 2131
2146 2147
2162 2163
2116
2132
2148
2164
2117
2133
2149
2165
2118
2134
2150
2166
2119
2135
2151
2167
2120 2121 2122
2136 2137 2138
2152 2153 2154
2168 2169 2170
2123
2139
2155
2171
2124
2140
2156
2.172
880
890
8AO
8BO
2176 2177 2178
2192 2193 2194
2208 2209 2210
2224 2225 2226
2179
2195
2211
2227
2180
2196
2212
2228
2181
2197
2213
2229
2182
2198
2214
2230
2183
2199
2215
2231
2184
2200
2216
2232
2187
2203
2219
2235
2188 2189
2204 2205
2220 2221
2236 2237
8CO
8DO
8EO
8FO
2240
2256
2272
2288
2241
2257
2273
2289
2242
2258
2274
2290
2243
2259
2275
2291
2244
2260
2276
2292
2245
2261
2277
2293
2246
2262
2278
2294
2247
2263
2279
2295
2248 2249
2264 2265
2280 2281
2296 2297
2250 2251
2266 2267
2282 2283
2298 2299
2252
2268
2284
2300
2253 2254 2255
2269 2270 2271
2285 2286 2287
2301 2302 2303
900
910
920
930
2304 2305
2320 2321
2336 2337
2352 2353
2306
2322
2338
2354
2307
2323
2339
2355
2308
2324
2340
2356
2309
2325
2341
2357
2310
2326
2342
2358
2311
2327
2343
2359
2312
2328
2344
2360
2314
2330
2346
2362
2316
2332
2348
2364
2317 2318
2333 2334
2349 2350
2365 2366
940
950
960
970
2368
2384
2400
2416
2369
2385
2401
2417
2370 2371
2386 2387
2402 2403
2418 2419
2372
2388
2404
2420
2373
2389
2405
2421
2374
2390
2406
2422
2375
2391
2407
2423
2376 2377 2378 2379
2392 2393 2394 2395
2408 2409 2410 2411
2424 2425 2426 2427
980
990
9AO
9BO
2432 2433
2448 2449
2464 2465
2480 2481
2434 2435
2450 2451
2466 2467
2482 2483
2436
2452
2468
2484
2437
2453
2469
2485
2438
2454
2470
2486
2439
2455
2471
2487
2440
2456
2472
2488
2441
2457
2473
2489
2442
2458
2474
2490
9CO
9DO
9EO
9FO
2496 2497 2498 2499
2512 2513 2514 2515
2528 2529 2530 2531
2544 2545 L546 2547
2500
2516
2532
2548
2501
2517
2533
2549
2502
2518
2534
2550
2503
2519
2535
2551
2504
2520
2536·
2j52
2505
2521
2537
2553
2506
2522
2538
2554
2113
2129
2145
2161
6
7
1798 1799
1814 1815
1830 1831
1846 1847
2185
2201
2217
2233
2313
2329
2345
2361
2186
2202
2218
2234
2315
2331
2347
2363
2125
2141
2157
2173
2063
2079
2095
2111
2126 2127
2142 2143
2158 2159
2174 2175
2190
2206
2222
2238
2191
2207
2223
2239
2319
2335
2351
2367
2380 2381
2396 2397
2412 2413
2428 2429
2382 2383
2398 2399
2414 2415
2430 2431
2443
2459
2475
2491
2444 2445
2460 2461
2476 2477
2492 2493
2446
2462
2478
2494
2447
2463
2479
2495
2507
2523
2539
2555
2508
2524
2540
2556
2509
2525
2541
2557
2510
2526
2542
2558
2511
2527
2543
2559
Appendix A
111
HEXADECIMAL-DECIMAL INTEGER CONVERSiON TABLE (cant.)
1
0
112
2
3
4
5
6
7
8
9
2569
2585
2601
2617
A
B
C
D
E
F
2572
2588
2604
2620
2573
2589
2605
2621
2574
2590
2606
2622
2575
2591
2607
2623
2636 2637 2638
2652 2653 2654
2668 2669 2670
2684 2685 2686
2639
2655
2671
2687
AOO
Al0
A20
A30
2560 2561
2576 2577
2592 2593
2608 2609
2562
2578
2594
2610
2563
2579
2595
2611
2564
2580
2596
2612
2565
2581
2597
2613
2566 2567
2582 2583
2598 2599
2614 2615
2568
2584
2600
2616
A40
A50
A60
A70
2624 2625
2640 2641
2656 2657
2672 2673
2626 2627
2642 2643
2658 2659
2674 2675
2628
2644
2660
2676
2629
2645
2661
2677
2630 2631
2646 2647
2662 2663
2678 2679
2632 2633 2634
2648 2649 2650
2664 2665 2666
2680 2681 2682
A80
A90
AAO
ABO
2688
2704
2720
2736
2689
2705
2721
2737
2690
2706
2722
2738
2691
2707
2723
2739
2692
2708
2724
2740
2693
2709
2725
2741
2694 2695
2710 2711
2726 2727
2742 2743
2696 2697
2712 2713
2728 2729
2744 2745
2698 2699
2714 2715
2730 2731
2746 2747
2700
2716
2732
2748
2701
2717
2733
2749
2702 2703
2718 2719
2734 2735
2750 2751
ACO
ADO
AEO
AFO
2752
2768
2784
2800
2753 2754
2769 2770
2785 2786
2801 2802
2755
2771
2787
2803
2756
2772
2788
2804
2757
2773
2789
2805
2758 2759
2774 2775
2790 2791
2806 2807
2760 2761 2762 2763
2776 2777 2778 2779
2792 2793 2794 2795
2808 2809 2810 2811
2764
2780
2796
2812
2765
2781
2797
2813
2766
2782
2798
2814
BOO
BlO
B20
B30
2816
2832
2848
2864
2817 2818
2833 2834
2849 2850
2865 2866
2819
2835
2851
2867
2820
2836
2852
2868
2821
2837
2853
2869
2822
2838
2854
2870
2823
2839
2855
2871
2824
2840
2856
2872
B40
B50
B60
B70
2880
2896
2912
2928
2881 2882
2897 2898
2913 2914
2929 2930
2883
2899
2915
2931
2884
2900
2916
2932
2885
2901
2917
2933
2886
2902
2918
2934
2887
2903
2919
2935
2888 2889 2890 2891
2904 2905 2906 2907
2920 2921 2922 2923
2936 2937 2938 2939
2892
2908
2924
2940
B80
B90
BAO
BBO
2944
2960
2976
2992
2945
2961
2977
2993
2946
2962
2978
2994
2947
2963
2979
2995
2948
2964
2980
2996
2949
2965
2981
2997
2950
2966
2982
2998
2951
2967
2983
2999
2952
2968
2984
3000
2953 2954 2955
2969 2970 2971
2985 2986 2987
3001 3002 3003
2956 2957 2958 2959
2972 2973 2974 2975
2988 2989 2990 2991
3004 3005 3006 3007
BCO
BOO
BEO
BFO
3008
3024
3040
3056
3009
3025
3041
3057
3010 3011
3026 3027
3042 3043
3058 3059
3012 3013 3014
3028 3029 3030
3044 3045 3046
3060 3061 3062
3015
3031
3047
3063
3016
3032
3048
3064
3017
3033
3049
3065
3018
3034
3050
3066
3019
3035
3051
3067
3020
3036
3052
3068
3021
3037
3053
3069
COO
Cl0
C20
C30
3072
3088
3104
3120
3073
3089
3105
3121
3074 3075
3090 3091
3106 3107
3122 3123
3076 3077
3092 3093
3108 3109
3124 3125
3078
3094
3110
3126
3079
3095
3111
3127
3080
3096
3112
3128
3081
3097
3113
3129
3082
3098
3114
3130
3083
3099
3115
3131
3084
3100
3116
3132
3085 3086
3101 3102
3117 3118
3133 3134
C40
C50
C60
C70
3136
3152
3168
3184
3137
3153
3169
3185
3138
3154
3170
3186
3140
3156
3172
3188
3142
3158
3174
3190
3143
3159
3175
3191
3144
3160
3176
3192
3145
3161
3177
3193
3146
3162
3178
3194
3147
3163
3179
3195
3148
3164
3180
3196
3149
3165
3181
3197
3150 3151
3166 3167
3182 3i83
3198 3199
C80
C90
CAO
CBO
3200 3201
3216 3217
3232 3233
3248 3249
3204 3205 3206 3207
3220 3221 3222 3223
3236 3237 3238 3239
3252 3253 3254 3255
3208
3224
3240
3256
3209
3225
3241
3257
3210
3226
3242
3258
3211
3227
3243
3259
3212
3228
3244
3260
3213
3229
3245
3261
3214
3230
3246
3262
3215
3231
3247
3263
CCO
COO
CEO
CFO
3264 3265 3266
3280 3281 3282
3296 3297 3298
3312 3313 3314
3272
3288
3304
3320
3273
3289
3305
3321
3274 3275
3290 3291
3306 3307
3322 3323
3276
3292
3308
3324
3277
3293
3309
3325
3278
3294
3310
3326
3279
3295
3311
3327
Appendix A
3139
3155
3171
3187
3202 3203
3218 3219
3234 3235
3250 3251
3267
3283
3299
3315
3268
3284
3300
3316
3141
3157
3173
3189
3269
3285
3301
3317
3270
3286
3302
3318
3271
3287
3303
3319
2570 2571
2586 2587
2602 2603
2618 2619
2635
2651
2667
2683
2825 2826 2827
2841 2842 2843
2857 2858 2859
2873 2874 2875
2767
2783
2799
2815
2828 2829 2830 2831
2844 2845 2846 2847
2860 2861 2862 2863
2876 2877 2878 2879
2893
2909
2925
2941
2894
2910
2926
2942
2895
2911
2927
2943
3022 3023
3038 3039
3054 3055
3070 3071
3087
3103
3119
3135
HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cant.)
0
2
3
4
D
3:~~
6
7
8
9
A
B
C
3334
3350
3366
3382
3335
3351
3367
3383
3336
3352
3368
3384
3337
3353
3369
3385
3338
3354
3370
3386
3339
3355
3371
3387
3340
3356
3372
3388
3341 3342
3357 3358
3373 3374
3389 3390
3359 ,
3375 I
3391
3402
3418
3434
3450
3403
3419
3435
3451
3404
3420
3436
3452
3405 3406
3421 3422
3437 3438
3453 3454
3407
3423
3439
3455
3465 3466 3467
3480 3481 3482 3483
3496 3497 3498 3499
3512 3513 3514 3515
3468
3484
3500
3516
3469
3485
3501
3517
3470
3486
3502
3518
3471
3487
3503
3519
3532 3533 3534
3548 3549 3550
3564 3565 3566
3580 3581 3582
3535
5
E
000
D10
D20
D30
3328
3344
3360
3376
3329
3345
3361
3377
3330
3346
3362
3378
3331
3347
3363
3379
3332 3333
3348 3349
3364 3365
3380 3381
D40
3392
3408
3424
3440
3393
3409
3425
3441
3394
3410
3426
3442
3395
3411
3427
3443
3396
3412
3428
3444
3397
3413
3429
3445
3398 3399
3414 3415
3430 3431
3446 3447
3400 3401
3416 3417
3432 3433
3448 3449
3456 3457
3472 3473
3488 3489
3504 3505
3458
3474
3490
3506
3459
3475
3491
3507
3460 3461
3476 3477
3492 3493
3508 3509
3462 3463
3478 3479
3494 3495
3510 3511
3464
3520 3521
3536 3537
3552 3553
3568 3569
3522
3538
3554
3570
3523
3539
3555
3571
3524 3525
3540 3541
3556 3557
3572 3573
3526 3527
3542 3543
3558 3559
3574 3575
3529
3545
3561
3577
3584
3600
3616
3632
3586
3602
3618
3634
3587
3603
3619
3528
3544
3560
3576
......... -..
3592
3608
3624
3640
3594
3610
3626
3642
3595
3611
3627
3643
3596 3597
3612 3613
3628 3629
3644 3645
3648 3649 3650
3664 3665 3666
3680 3681 3682
3696 3697 3698
3659
3675
3691
3707
3660
3676
3692
3708
3661 3662 ..5663
3677 3678 3679
3693 3694 3695
3709 3710 3?1 i
DSO
D60
D70
080
D90
DAO
DBO
DCO
ODO
nEO
DFO
-
....... ......~-~.-.~~-"'-.-.-----
EGO
1:10
EiO
E30
tAO
E.50
[60
E70
I
E80
I E90
I EAO
ESO
3530
3546
3562
3578
3531
3547
3563
3579
~-.--.,.~-------.
I
3551
3567
3583
r'=i~90
3598 J_"
, i
3614 3615 i
3630 3631 I
3646
:3635
3588
3604
3620
3636
3589
3605
3621
3637
3606
3,,22
3638
3591
3607
3623
3639
3651
3667
3683
3699
3652 3653
3668 3669
3684 3685
3700 3701
3654
3670
3686
3702
3655
3671
3687
3703
3656
3672
3688
3704
3657 3658
3673 3674
3689 3690
3705 3706
37i3 3714 3715
3728 3729 3730 3731
3744 3745 3746 3747
3760 3761 3762 3763
3716 3717
3732 3733
3748 3749
3764 3765
3718
3734
3750
3766
3719
3735
3751
3767
3720
3736
37.52
3768
3721
3737
3753
3769
3722 3723
3738 3739
3754 3755
3770 3771
3724
3740
3756
3772
3725
3741
3757
3773
3726
3742
3758
3774
3727
3743
3759
3775
3585
3601
3617
3633
I 3712
3590
3593
3609
3625
3641
~c471
EEO
EFO
3776
3792
3808
3824
3777
3793
3809
3825
3778
3794
3810
3826
3779
3795
3811
3827
3780
3796
3812
3828
3781
3797
3813
3829
3782
3798
3814
3830
3783
3799
3815
3831
3784
3800
3816
3832
3785
3801
3817
3833
3786
3802
3818
3834
3787
3803
3819
3835
3788
3804
3820
3836
3789
3805
3821
3837
3790
3806
3822
3838
3791
3807
3823
3839
FOO
FlO
F20
F30
3840
3856
3872
3888
3841
3857
3873
3889
3842
3858
3874
3890
3843
3859
3875
3891
3844
3860
3876
3892
3845 3846
3861 3862
3877 3878
3893 3894
3847
3863
3879
3895
.3848
3864
3880
3896
3849
3865
3881
3897
3850
3866
3882
3898
3851
3867
3883
3899
3852 3853
3868 3869
3884 3885
3900 3901
3854
3870
3886
3902
3855
3871
3887
3903
F40
F50
F60
F70
3904
3920
3936
3952
3905
3921
3937
3953
3906
3922
3938
3954
3907
3923
3939
3955
3908 3909 3910
3924 3925 3926
3940 3941 3942
3956 3957 3958
3911
3927
3943
3959
3912
3928
3944
3960
3913
3929
3945
3961
3914
3930
3946
3962
3915
3931
3947
3963
3916
3932
3948
3964
3917
3933
3949
3965
3918
3934
3950
3966
3919
3935
3951
3967
F80
F90
FAO
FBO
3968
3984
4000
4016
3969
3985
4001
4017
3970
3986
4002
4018
3971
3987
4003
4019
3972
3988
4004
4020
3973
3989
4005
4021
3974 3975
3990 3991
4006 4007
4022 4023
3976
3992
4008
4024
3977
3993
4009
4025
3978
3994
4010
4026
3979
3995
4011
4027
3980
3996
4012
4028
3981 3982 3983
3997 3998 3999
4013 4014 4015
4029 4030 4031
I FCO
FDO
FEO
FFO
4032
4048
4064
4080
4033
4049
4065
4081
4034
4050
4066
4082
4035
4051
4067
4083
4036
4052
4068
4084
4037
4053
4069
4085
4038 4039
4054 4055
4070 4071
4086 4087
4040
4056
4072
4088
4041
4057
4073
4089
4042
4058
4074
4090
4043
4059
4075
4091
4044
4060
4076
4092
4045 4046 4047
4061 4062 4063
4077 4078 4079
4093 4094 4095
I ECO
EDO
I
I
Appendix A
"
I
1
113
HEXADECIMAl~DECIMAl FRACTION
CONVERSION TABLE
i~nc. i
DeC;'Tl0i
~exadec;mc!
DecimG!
uec;ma!
~'-It?''.-odec
____________________
~______________________
~~______________________
Hexodec imo I
~____________
,DeClflloi
_________ J
Hexadecimal
.ooaoo 00000
.OD 0000 00
.Of 0000 00
.or 00 00 0G
.0156250000
.01953 i 2500
.02343 75000
.02734 37500
.03125 00000
.035! 5 62500
.03°06 25000
.04296 87500
.04687 50000
.05078 12500
.05468 75000
.05859 37500
.40 000000
.41 000000
,42 000000
.43 0000 JO
.4~ 0000 00
.45 CO 00 OC
.46 000000
.4::' 00 00 00
.48 000000
.49 00 00 00
AA OC 00 00
.4B 000000
.4C 000000
.4D 00 00 00
AE 00 OC 00
AF 0000 00
.29296
.29687
.30078
.30468
.30859
.10 0000 00
11 000000
1'1 000000
.: :3 00 00 00
. '" C:O 00 00
· 15 000000
.!t. 00 OC 00
17 00 00 00
.18 00 00 00
.19 00 00 00
.iA 000000
· ; b 000000
.J( 0000 00
.lD 000000
.1 E 000000
· iF 0000 00
.06250 00000
.0664062500
.07031 25000
,0 7 42 1 87500
.07812 50000
.082C3 12500
.08593 75000
.08984 37500
.09375 00000
.09765 62500
· iOl5c) 25000
.10546 87500
.10937 50000
.11328 J2500
.1171875000
• J 21 09 37500
.20 CO 00 00
.21 00 00 00
Ii
.~2 GC 00 00
I
!j .LJ 00 00 00
24 00 00 OC
I
.25 00 00 00
.26 000000
27 000000
.28 00 00 00
29 00 00 00
.2t.. 0000 00
.n 000000
II .2C 0000 00
I .20 0000 00
.2E 000000
.2F 000000
· 12500 00000
.12890 62500
.13281 25000
.13671 87500
.14062 50000
· 14453 I 2500
.14843 75000
· i5234 37500
· 15625 00000
.160156250n
.16406 25000
.16n687500
· 17 j 87 50000
.17578 12500
.17968 75000
.18359 37500
.30 0000 00
.31 00 00 00
.32 00 00 00
~"
• .j.)
0000 00
.34 00 00 00
.35 000000
.36 000000
.37 000000
.38 000000
.39 000000
.3A 000000
.36 000000
.3C 00 00 00
.30 000000
.3E 000000
.3F 00 00 00
.18750 00000
· i9140 62500
· I 953 1 25000
.1992 i 87500
.20312 50000
.20703 12500
.21093 75000
.21484 37500
.21875 00000
.22265 62500
.22656 25000
.23046 87500
.23437 50000
.23828 12500
.24218 75000
.24609 37500
.0(; 0000 OJ
.0 : 000000
..,
..... ' ... 000008
.02 eye 00 00
,l)4 ')00000
.0'; 000000
.06 0000 00
.07 00 OC 00
.08 0000 (Ii)
.09 00 00 00
.0/\ ')0 00 00
(~
J)a 00 00 OC
.oc
"
0000 OC
.
~..,
I
I
I
114
.003QO 6:::500
.00781 25000
01 1 7187500
Appendix A
!
I
II
I
I
I
Ii
!
I
!
II
I
j
1
I
I
75000
37500
00000
62500
25000
87500
50000
12500
75000
37500
.80 000000
.8! 000000
. 8~'
£
000000
.83 000000
,84 000000
.85 00 00 00
.86 0000 00
.87 00 00 00
.88 000000
.89 00 00 00
.8A 00 00 00
.8B OC 00 00
.8C 00 00 00
.80 00 00 00
.8E 00 OC 00
.8F 000000
.53515 62500
.53906 25000
.54296 87500
.54687 50000
.55078 12500
.55468 75000
.55859 37500
00 00 00
0000 00
0000 00
000000
000000
000000
00 00 00
0000 00
0000 00
00 00 00
0000 00
0000 00
00 00 00
.Ct 000000
.CF 00 00 00
.50 000000
.5l 00 CO 00
.52 000000
.53 00 00 00
.54 000000
.55 000000
.56 0000 ('0
.57 000000
.58 0000 CO
.59 00 00 00
.5A 0000 00
.58 00 00 00
.5C 00 00 00
.50 0000 00
.5E 000000
.5F 00 00 00
.31250 00000
.31040 62500
.32031 25000
.32421 87500
.3281250000
.33203 12500
.33593 75000
.33984 37500
.34375 00000
.34765 62500
.35156 25000
.35546 87500
.35937 50000
.36328 12500
.36718 75000
.3710937500
.90 0000 00
.9 1 0000 00
.92 00 00 00
.93 00 00 00
.94 0000 00
.95 00 00 00
.96 00 00 00
.97 0000 00
.98 0000 00
.99 0000 00
.9A 000000
.9B 00 00 00
.9C 000000
.90 00 00 dO
.9E 0000 00
.9F 0000 00
.56250 00000
.56640 62500
.5703! 25000
.57421 87500
.57812 50000
.58203 12500
.5859375000
.58984 37500
.59375 00000
.59765 62500
,60156 25000
.60546 87500
.60937 50000
.6 j 328 12500
.6171875000
.62109 37500
.00 000000
.D1 00 0000
.D2 000000
.03 0000 00
.D4 0000 00
.D5 0000 00
.D6 00 00 00
.D7 00 00 00
.08 0000 oe
.D9 00 00 00
.DA 00 00 00
.06 0000 00
.DC 00 00 00
.DD 000000
.DE 00 00 00
.DF 00 00 OC
.60 000000
.61 000000
.62 000000
.63 000000
.64 000000
.65 000000
.66 00 00 00
.67 0000 GO
.68 000000
.69 000000
.6A 0000 00
.6S 000000
.6C 00 00 00
.60 000000
.6E 000000
.6F 00 00 OC-
.37500
.37890
.38281
.38671
.39062
.39453
.39843
.40234
.40625
.401015
.41406
.401796
.42187
.402578
.42968
.403359
.AO
,AI
.A2
.A3
.A4
.A5
.A6
.A7
.A8
.A9
.AA
.AB
.AC
.AD
.AE
.AF
0000
0000
0000
00 00
00 00
00 00
00 00
00 00
0000
00 00
00 00
00 00
0000
00 00
00 00
00 00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.62500 00000
.6 289062500
.63281 25000
.63671 87500
.64062 50000
.64453 12500
.64843 75000
.65234 37500
.65625 00000
.66015 62500
.66406 25000
.66796 87500
.67187 50000
.67578 12500
.67968 75000
.68359 37500
.. EO 000000
EI 00 00 00
i .E2 00 0000
.E3 0000 00
.E4 000000
.E5 00 00 00
.E6 00 00 00
.E7 000000
.E8 00 00 00
.E9 00 00 00
.EA 00 00 00
.EB 00 00 00
.EC 00 00 00
.ED 000000
.EE 00 00 00
.EF 00 00 00
.70 00 00 00
.71 000000
.72 0000 00
.73 00 00 00
.74 0000 00
.75 00 00 00
.76 00 00 00
.77 00 00 00
.78 000000
.79 00 00 00
.7A 00 00 00
.7S 0000 00
.7C 00 00 00
.70 00 00 00
.7E 00 00 00
.7F 00 00 00
.43750 00000
.44140 62500
.404531 25000
.44921 87500
.40531 2 50000
.405703 12500
.46093 75000
.46484 37500
.46875 00000
.407265 62500
.47656 25000
.408046 87500
.48437 50000
.408828 12500
.409218 75000
.409609 37500
.BO
.Bl
.B2
.B3
000000
00 00 00
00 00 00
00 00 00
00 00 00
0000 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
.68750 00000
.6914062500
.69531 25000
.69921 87500
.7031 2 50000
.70703 12500
.7109375000
.71484 37500
.71875 00000
.7226562500
.72656 25000
.73046 87500
.73437 50000
.73828 12500
.7421875000
.74609 37500
.25000 00000
.25390
.25781
.26171
.26562
62500
25000
87500
50000
.26'i'53 12500
.27343
.27734
.281 25
.28515
.28906
00000
62500
25000
87500
50000
12500
75000
37500
00000
62500
25000
87500
50000
i 2500
75000
37500
I
I
.B4
.B5
.86
.B7
.B8
.B9
.BA
.BB
.BC
.BD
.BE
.BF
00
00
.50000 00000
.50390 62500
.5078] 25000
.51171 87500
.5156250000
.51953 : 2500
.52343 75000
.52734 37500
.CO
.Cl
.(2
.C3
.C4
.C5
.C6
.C7
.(8
.C9
.CA
.CB
.CC
.CD
.5312.5 00000
0000 00
I
I
!
I
II
.FO
.F I
.F2
.F3
.F4
.F5
.F6
.F7
.F8
.F9
.FA
.fB
.Fe
.FD
.FE
.FF
000000
00 00 00
00 00 00
000000
000000
00 00 00
000000
00 00 00
0000 OG
000000
000000
000000
00 00 00
0000 00
0000 00
0000 00
.75000 OOO{)(j
.75390
i!
I
62S~(;
.75i81 25C0:::
.76',71 87500
./6562 SOOtY':,
.76953 i 2)0']
.77343 75000
.7T' 34 3750(;
.781 25 00000
.78515 62500
.78906 2500C
.79296 87500
.79687 50000
.80078 12500
.80468 75C.(;0
.8085937500
.8 J 250 00000
.8164062500
.82031 25000
.82421 8750G
. g231 2 50000 I
.83203 12500
.83593 75000
.83984 37500 l
.84375 00000
.84765 62500
.85 i 56 25000
.85546 87500 .
.85937 50000
.86328 12500
I
I
II
.8671875000
.871 09 37500
.87500 00000
.8 7890 62500
.88281 25000
.88671 87500
.89062 50000
.89453 12500
.89843 75000
.90234 37500
.906 25 00000
.91015 62500
.9 ! 406 25000
.9179687500
.92 i 87 50000
.92578 12500
.92968 75000
.93359 37500
.93750
.94140
.94531
.94921
.95312
.95703
.96093
.96484
.96875
.97265
.97656
.98046
.98437
.98828
.99218
.99609
00000
62500
25000
87500
50000
12500
75000
37500
00000
62500
25000
87500
50000
12500
75000
37500
I
HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cant.)
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
.0000
.0001
.0002
.0003
.0004
.0005
.0006
.0007
.00 08
.0009
.OOOA
.OOOB
.OOOC
.OOOD
.OOOE
.00 OF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00 00
00 00
0000
.00000 00000
.00001 52587
.00003 05175
.0000457763
.00006 10351
.00007 62939
.00009 15527
.0001068115
.00012 20703
.00013 73291
.00015 25878
.00016 78466
.00018 31054
.0001983642
.00021 36230
.00022 88818
.0040
.0041
.0042
.0043
.0044
.0045
.0046
.0047
.0048
.0049
.004A
.004B
.004C
.004D
.004E
.004F
0000
0001)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.0009765625
.00099 18212
.00100 70800
.00102 23388
.00103 75976
.001 05 28564
.00106 81152
.00108 33740
.0010986328
.00111 38916
.00112 91503
.0011444091
.00115 96679
.00117 49267
.0011901855
.0012054443
.0080
.0081
.0082
.0083
.0084
.0085
.0086
.0087
.0088
.0089
.008A
.008B
.008C
.0080
.008E
.008F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00 00
0000
00 00
0000
0000
.00195 31250
.00196 83837
.00198 36425
.0019989013
.00201 41601
.00202 94189
.00204 46 777
.00205 99365
.00207 51953
.00209 04541
.00210 57128
.0021209716
.00213 62304
.00215 14892
.0021667480
.00218 20068
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
CO 0000
ClOD 00
C2 0000
C3 0000
C4 00 00
C5 0000
C6 0000
C7 00 00
C8 0000
C9 0000
CA 00 00
CB 0000
CC 00 00
CD 00 00
CE 0000
CF 00 00
.00292 96875
.00294 49462
.00296 02050
.00297 54638
.00299 07225
.0030059814
.00302 12402
.00303 64990
.00305 17578
.00306 70166
.00308 22753
.00309 75341
.00311 27929
.0031 2 8051 7
.00314 33105
.00315 85693
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
10
11
12
13
14
15
16
17
18
19
lA
1B
lC
1D
lE
1F
0000
0000
0000
0000
0000
0000
00 00
00 00
00 00
0000
0000
0000
0000
0000
00 00
0000
.00024
.00025
.00027
.00028
.00030
.00032
.00033
.00035
.00036
.00038
.00039
.00041
.00042
.00044
.00045
.00047
41406
93994
46582
99169
51757
04345
56933
09521
62109
14697
6728.)
19873
72460
25048
77636
30224
.0050
.0051
.0052
.0053
.0054
.0055
.0056
.0057
.0058
.00 S9
.005A
.005B
.005C
.005D
.005E
.005F
0000
0000
0000
0000
0000
0000
0000
00 00
0000
0000
0000
0000
0000
0000
0000
0000
.0012207031
.0012359619
.00125 12207
.00126 64794
.00128 17382
.0012969970
.00131 22558
.0013275146
.0013427734
.00135 80322
.00137 32910
.0013885498
.00140 38085
.00141 90673
.00143 43261
.00144 95849
.0090
.0091
.0092
.0093
.0094
.0095
.0096
.0097
.0098
.0099
.009A
.009B
.009C
.00 90
.009E
.009F
0000
0000
0000
0000
0000
0000
00 00
0000
0000
0000
00 00
00 00
00 00
00 pO
0000
00 00
.00219 72656
.00221 25244
.00222 77832
.00224 30419
.00225 83007
.00227 35595
.00228 88183
.00230 40771
.00231 93359
.00233 45947
.00234 98535
.00236 51123
.00238 03710
.0023956298
.00241 08886
.00242 61474
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
DO
Dl
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
0000
0000
00 DC
00 00
0000
0000
0000
00 00
0000
00 00
00 00
0000
00 00
0000
0000
0000
.00317 38281
.00318 90869
.00320 43457
.00321 96044
.00323 48632
.00325 01220
.00326 53808
.00328 06396
.0032958984
.00331 11572
.00332 64160
.00334 16748
.00335 69335
.00337 21923
.00338 74511
.00340 27099
.00 20
.00 21
.0022
.0023
.00 24
.0025
.0026
.0027
.0028
.00 29
.002A
.002B
.002C
.00 2D
.00 2E
.002F
0000
0000
0000
0000
0000
0000
0000
0000
00 00
0000
0000
0000
0000
0000
0000
0000
.0004d 82812
.00050 35400
.00051 87988
.00053 40576
.000S493164
.00056 45751
.00057 98339
.00059 50927
.00061 03515
.00062 56103
.00064 08691
.00065 61279
.00067 13867
.00068 66455
.00070 19042
.00071 71630
.0060
.0061
.0062
.0063
.0064
.0065
.0066
.0067
.0068
.0069
.006A
.006B
.006C
.006D
.006E
.006F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00146 48437
.00148 01025
.0014953613
.00151 06201
.0015258789
.00154 11376
.0015563964
.00157 16552
.0015869140
.00160 21728
.00161 74316
.00163 26904
.0016479492
.00166 32080
.00167 84667
.0016937255
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
AD
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
0000
0000
0000
00 00
0000
0000
00 00
0000
0000
0000
00 00
0000
0000
00 00
0000
0000
.00244
.00245
.00247
.00248
.00250
.00251
.00253
.00254
.00256
.00257
.00259
.00260
.00262
.00263
.00265
.00267
14062
66650
19238
71826
24414
77001
29589
82177
34765
87353
39941
92529
45117
97705
50292
02880
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
EO
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00 00
0000
0000
00 00
0000
.00341
.00343
.00344
.00346
.00347
.00349
.00350
.00352
.00354
.00355
.00357
.00358
.00360
.00361
.00363
.00364
.0030
.0031
.0032
.0033
.0034
.0035
.0036
.0037
.0038
.0039
.003A
.003B
.003C
.00 3D
.00 3E
.003F
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00073 24218
.00074 76806
.00076 29394
.00077 81982
.00079 34570
.00080 87158
.00082 39746
.00083 92333
.00085 44921
.00086 97509
.00088 50097
.00090 02685
.00091 55273
.00093 07861
.00094 60449
.00096 13037
.0070
.0071
.0072
.0073
.0074
.0075
.0076
.0077
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00170 89843
.00172 42431
.0017395019
.00175 47607
.00177 00195
.00178 52783
.00180 05371
.00181 57958
.00183 10546
.0018463134
.00186 15722
.0018768310
.00189 20898
.00190 73486
.00192 26074
.00193 78662
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.0026855468
.00270 08056
.00271 60644
.00273 13232
.0027465820
.00276 18408
.00277 70996
.00279 23583
.0028076171
.00282 28759
.0028381347
.00285 33935
.00286 86523
.00288 39111
.00289 91699
.00291 44287
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
FO
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
.00366 21093
.00367 73681
.00369 26269
.00370 78857
.00372 31445
.00373 84033
.00375 36621
.00376 89208
.00378 41796
.00379 94384
.00381 46972
.00382 99560
.0038452148
.00386 04736
.00387 57324
.0038909912
.001'8
.0079
.007A
.007B
.007C
.0070
.007E
.007F
Appendix A
79687
32275
84863
37451
90039
42626
95214
47802
00390
52978
05566
58154
10742
63330
15917
68505
115
HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cant.)
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
,00 00 00
.0000 01
.00 00 02
.00 00 03
.00 00 04
.00 00 05
.00 00 06
.000007
.00 00 08
.00 00 09
.00 00 OA
.00 00 OB
.00 00 OC
.00 00 aD
.00 00 OE
.0000 OF
00
00
00
00
00
00
00
00
00
00
00
00
OC
00
00
00
· 00000 00000
.00000 00596
.00000 01 J 92
.00000 01788
.00000 02384
.00000 02980
.00000 03576
.00000 04 J 72
.00000 04768
,00000 05364
.00000 as 960
.0000006556
.00000 07152
.00000 07748
.00000 08344
.00000 08940
.0000 40
.00 00 41
.00 00 42
.00 00 43
.00 00 44
.00 00 45
.00 00 46
.00 00 47
.00 0048
.0000 49
.00004A
.0000 4B
.00004C
.00004D
.00004E
.00004F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 38146
.00000 38743
.00000 39339
.00000 39935
.00000 40531
.00000 41127
.00000 41723
.00000 4231 9
.00000 42915
· 00000 43511
· 00000 44107
.00000 44703
.00000 45299
.00000 45895
.00000 46491
.00000 47087
.00 00 80
.00 00 81
.00 00 82
.0000 83
.00 00 84
.00 00 85
.00 00 86
.00 00 87
.00 00 88
.00 00 89
.00 00 8A
.00 00 8B
.00 00 8C
.00 00 8D
.00 00 8E
.00 00 8F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 76293
.00000 76889
· 00000 77486
.00000 78082
.00000 78678
.00000 79274
.00000 79870
.00000 80466
.0000081062
.00000 81658
.00000 82254
.00000 82850
· 00000 83446
.00000 84042
.00000 84638
.00000 85234
.0000 co
.00 00 Cl
.00 00 C2
.0000 C3
.00 00 (4
.0000 C5
.0000 C6
.00 00 C7
.0000 C8
.0000 C9
.00 00 CA
.00 00 CB
.00 00 CC
.00 00 CD
.00 00 CE
.00 00 CF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
· 0000 1 14440
.00001 15036
.00001 15633
.00001 16229
.00001 16825
.00001 17421
.00001 18017
.00001 18613
.00001 19209
.0000 I 19805
.00001 20401
.00001 20997
,0000 1 21 593
.00001 22189
.0000 1 22785
.00001 23381
.000010
.00 00 11
.00 00 12
.00 00 13
.0000 14
,00 00 15
.00 00 16
.00 00 17
.0000 18
.0000 19
.0000 1A.
.00 00 1B
.00 00 1C
.0000 1 D
.00 00 1E
.00 00 IF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
00000
.00000
·00000
.00000
.00000
,00000
.00000
.00000
.00000
.00000
.00000
·00000
.00000
.00000
09536
10 132
10728
11324
1 1920
12516
13113
13709
14305
14901
15497
16093
16689
I 7285
17881
18477
.00 00 50
.00 00 51
.00 0052
.00 00 53
.00 00 54
.00 00 55
.00 00 56
.000057
.000058
.0000 59
.00005A
.00 00 5B
.00 00 5C
.00 0050
.00 00 5E
.00 00 5F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
.00000
.00000
.00000
·00000
.00000
· 00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
47683
48279
48875
49471
50067
50663
51259
51856
52452
53048
53644
54240
54836
55432
56028
56624
.00 0090
.00 0091
.00 00 92
.00 00 93
.00 00 94
.00 0095
.00 0096
.00 00 97
.00 0098
.00 00 99
.00 00 9A
.00 00 9B
.00 00 9C
.0000 9D
.00 00 9E
.00 00 9F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
.00000
.00000
.00000
· 00000
.00000
·00000
.00000
.00000
.00000
.09000
.00000
.00000
.00000
· 00000
85830
86426
87022
87618
88214
8881 0
89406
90003
90599
91195
91791
92387
92983
93579
94175
94771
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
DO 00
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00001 23977
.00001 24573
.0000 1 25169
.00001 25765
·0000 1 2636 1
.00001 26957
.0000 1 27553
.00001 28149
·00001 28746
.00001 29342
.00001 29938
.00001 30534
.0000 1 311 30
.00001 31726
.00 00 20
.00 00 21
.00 00 22
.0000 23
.0000 24
.0000 25
.00 00 26
.0(1 00 27
.00 00 28
.00 00 29
00002A
.00002B
.00 00 2C
.0000 2D
.00 00 2E
.00002F
00
00
.00000
.00000
· 00000
.00000
·00000
.00000
.00000
.00000
.00000
.00000
,00000
.00000
.00000
.00000
.00000
.00000
19073
19669
20265
20861
21 457
22053
22649
23 245
23841
24437
25033
25629
26226
20822
27418
28014
.00 00 60
.00 00 61
.00 00 62
.00 0063
.00 00 64
.00 00 65
.00 00 66
.0000 67
.000068
.00 00 69
.00006A
.00006B
.00 00 6C
.00 00 6D
.00006E
.00 00 6F
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000 57220
.0000057816
.00000 58412
· 00000 59008
· 00000 59604
.00000 60200
.00000 60796
.00000 61392
· 00000 61 988
.00000 62584
.00000 631 80
.00000 63776
.00000 64373
.00000 64969
.00000 65565
.00000 66161
.00 00
.0000
.0000
.00 00
.00 00
.00 00
.0000
.0000
.00 00
.0000
.00 00
,0000
.00 00
.00 00
.00 00
.00 00
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001
95367
95963
96559
97155
97751
98347
98943
99539
00135
00731
01327
01923
02519
03116
03712
04308
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
· 00000
.00000
.00000
.00000
.00000
.00000
.OCOOO
.00000
.00000
.00000
.00000
.0000(';
.()OOOO
.00000
.COOOO
286 10
29206
29802
30398
30994
31590
32186
32782
33378
33974
34570
35 166
35762
36358
369)4
.00 0070
.0000 71
.00 00 72
.00 00 73
.00 00 74
.00 00 75
.0000 76
.00 00 77
.00 00 78
.00 00 7'1
.00 00 7,6..
.00 00 73
.00 00 i'C
,'X) 00 7D
.00 00 7E
00
00
00
00
00
00
00
00
00
00
GO
00
00
00
00
00
00
00
00
00
00
00
00
00
ce,
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.0000
.00 00
.0000
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
•• _._~l_;J_f=_,)~_._..c_:o._o.c_,·_;._3:'_'~_:::1:_)_.LGCJ 00 IF
.00000 66757
.00000 67353
.00000 67949
.00000 68545
.00000 69141
.00000 69737
.00000 70333
.00000 70929
.00000 71525
. 00000 72121
.00000 7271 7
.00000 73313
.00000 73909
· 00000 74505
.00000 75101
.00000 75697
.0000 1 43051
.00 00 FO 00
· 0000 1 04904
00001 43647
.00 00 Fl 00
.00001 05500
.00001 44243
.00 00 F2 00
.0000 1 06096
.00001 44839
.0000 F3 00
.00001 06692
.0000 F4 00
· 0000 I 45435
· 00001 07288
.00001 46031
.00 00 F5 00
.00001 07884
.0000 I 46627
.00 00 F6 00
.00001 08480
.00001 47223
.00 GO F7 00
.00001 09076
.00001 47819
j .00 00 F8 00
.00001 09672
.00001 48415
.00001 10268
. .0000 F9 00
/)0001 490 11
.00 00 FA 00
.00001 !O864
.00001 49607
.00001 11460
.00 00 FB 00
.00001 50203
.00001 12056
.0000 FC 00
.0000 I :::0799
.00001 12652
.0000 FD 00
.0000 1 5135
.0000 1 13248
I'
.00 00 FE 00
.OOOOFF
00
,OGCI()l ~1)91
.:)000113844
---L ___
.-____
,__.___
.000030
.00 00 31
.00 00 32
,00 00 33
.000034
.00 00 35
.000036
.00 00 37
.00 00 38
.0(\ 00 39
,co
00
00
00
00
00
00
00
00
00
00
00
00
00
00
OC
00
00
00
00
00
00
00
00
00
:")0 3.4. 1)0
JJ 00 3C 00
,~~ GO :: D GO
.,,:0 CO 2E 00
116
Appendix A
I
I
II
I
.1
,'jC
I)oJ
~,',vo"
.
SD 00
BE 00
BF 00
Dl 00
.00001 32322
.0000 1 32918
.00001 33514
.0000 1 341 1a
.00001 34706
.00001 35302
.00001 35898
.00001 36494
.00001 37090
.00001 37686
.00001 38282
.00001 38878
.00001 39474
,00001 40070
· JOOO 1 40666
.00001 41263
.00001 41 859
.00001 42455
I
I
I
1
r_
HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)
Hexadec ima I
Decimal
Hexadecimal
Decimal
Hexadecimal
Decimal
Hexadec'mal
Decimal
.00000000
.00000001
.00000002
.00000003
.00000004
.00000005
.00000006
.00000007
.00000008
.00000009
.00 0000 OA
.000000 DB
.000000 DC
.OOOOOOOD
.000000 DE
.000000 OF
.00000 00000
.00000 00002
.00000 00004
.00000 00006
.00000 00009
.00000 0001 I
.00000 000 I 3
.00000 00016
.00000 00018
.00000 00020
.0000000023
.00000 00025
.0000000027
.0000000030
.0000000032
.00000 00034
.00000040
.00000041
.00000042
.00000043
.00000044
.00000045
.00000046
.00000047
.00000048
.00000049
.0000 00 4A
.0000004B
.00 00 00 4C
.0000004D
.0000004E
.0000004F
.00000 00149
.00000 00151
.00000 00 153
.00000 00155
.00000 00158
.00000 00 160
.0000000162
.00000 00 165
.0000000167
.0000000169
.00000 00172
.0000000174
.00000 00176
.00000 00179
.0000000181
.00000 00183
.00000080
.00000081
.00000082
.00000083
.00000084
.00000085
.00 00 00 86
.00 000087
.00000088
.00000089
.0000008A
.00 00 008B
.0000008C
.0000008D
.000000 8E
.0000008F
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
00298
00300
00302
00305
00307
00309
00311
00314
00316
00318
00321
00323
00325
00328
00330
00332
.00 00 00
.000000
.000000
.0000 00
.0000 00
.000000
.00 00 00
.000000
.000000
.000000
.0000 00
.0000 00
.000000
.0000 00
.000000
.0000 00
CO
Cl
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
.00000 0044 7
.00000 0044 9
.00000 00451
.00000 00454
.00000 00456
.00000 00458
.00000 0046 1
.00000 0046 3
.00000 00465
.00000 0046 7
.00000 00470
.0000000472
.00000 00474
.00000 00477
.00000 00479
.00000 0048 I
.00000010
.OC 00 00 II
.000000 12
.000000 13
.000000 14
.000000 15
.00000016
.000000 17
.000000 18
.000000 19
.OOOOOOIA
.000000 1B
.OOOOOOIC
.000000 1D
.000000 1E
.000000 1F
.0000000037
.00000 00039
.00000 00041
.00000 00044
.00000 00046
.00000 00048
.00000 0005 I
.00000 00053
.00000 00055
.0000000058
.00000 00060
.00000 0006 2
.00000 00065
.00000 00067
.00000 0006 9
.0000000072
.00000050
.00000051
.00000052
.00000053
.00000054
.00000055
.00000056
.00000057
.00000058
.00000059
.00 00 00 5A
.00 00 00 5B
.00 0000 5C
.00 00 00 5D
.00 00 00 5E
.0000005F
.00000 00 186
.00000 00 188
.00000 00 190
.00000 00193
.00000 00195
.00000 001 97
.00000 00200
.00000 00202
.00000 00204
.00000 00207
.00000 00209
.00000 00211
.00000 00214
.00000 00216
.00000 00218
.0000000221
.00000090
.00000091
.00000092
.00000093
.00000094
.00000095
.00000096
.00000097
.00000098
.00000099
.00 00 00 9A
.00 0000 9B
.000000 ric
.0000009D
.0000009E
.0000 00 9F
.00000 00335
.00000 00337
.00000 00339
.00000 00342
.00000 00344
.00000 00346
.0000000349
.00000 0035 I
.00000 00353
.00000 00356
.0000000358
.00000 00360
.00000 00363
.00000 00365
.00000 00367
.00000 00370
.000000
.000000
.000000
.000000
.00 00 00
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
00
DI
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
.00000 00484
.00000 00486
.0000000488
.00000 00491
.00000 00493
.00000 00495
.00000 004 98
.00000 00500
.0000000502
.00000 00505
.00000 00507
.00000 00509
.00000 0051 2
.00000 00514
.00000 0051 6
.00000 0051 9
.00000020
.000000 21
.000000 22
.00000023
.00000024
.000000 25
.00000026
.000000 27
.00000028
.00000029
.000000 2A
.0000002B
.0000002C
.0000002D
.0000002E
.0000002F
.00000 00074
.00000 00076
.00000 00079
.00000 00081
.00000 00083
.00000 00086
.00000 00088
.00000 00090
.00000 00093
.00000 00095
.00000 00097
.00000 00 100
.0000000102
.00000 001 04
.00000 001 07
.00000 00109
.00000060
.00000061
.00000062
.00000063
.00000064
.00000065
.00000066
.00000067
.00000068
.00000069
.00 00 00 6A
.0000006B
.00 00 00 6C
.0000006D
.0000006E
.0000006F
.00000 00223
.00000 00225
.00000 00228
.00000 00230
.00000 00232
.00000 00235
.00000 00237
.00000 00239
.00000 00242
.00000 00244
.00000 00246
.00000 00249
.00000 00251
.0000000253
.00000 00256
.00000 00258
.000000 AD
.000000 AI
.000000 A2
.000000 A3
.000000 A4
.000000 A5
.000000 A6
.000000 A7
.000000 A8
.000000 A9
.000000 AA
.000000 AB
.000000 AC
.000000 AD
.000000 AE
.000000 AF
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
00372
00374
00377
00379
00381
00384
00386
00388
00391
00393
00395
00398
00400
00402
00405
00407
.000000
.000000
.000000
.0000 00
.000000
.000000
.0000 00
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
EO
EI
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
.00000 00521
.00000 00523
.00000 00526
.00000 00528
.00000 00530
.00000 00533
.0000000535
.00000 00537
.00000 00540
.00000 00542
.00000 00544
.00000 00547
.00000 00549
.00000 0055 I
.00000 00554
.00000 00556
.00000030
.00000031
.00000032
.00000033
.00000034
.00000035
.00000036
.00000037
.00000038
.00000039
.0000003A
.0000003B
.0000003C
.0000003D
.000000.3E
.00 00 00 3F
.00000 00111
.0000000114
.0000000116
.00000 00118
.00000 00121
.00000 00123
.00000 001 25
.00000 00 128
.00000 001 30
.0000000132
.00000 001 35
.0000000137
.00000 00139
.0000000142
.00000 00144
.00000 00 I 46
.00000070
.00000071
.00000072
.00000073
.00000074
.00 00 00 75
.00000076
.000000 77
.00000078
.00000079
.0000 00 7A
.0000007B
.00 00 00 7C
.0000007D
.0000007E
.0000007F
.0000000260
.00000 00263
.00000 00265
.00000 00267
.00000 00270
.00000 00272
.0000000274
.00000 00277
.00000 00279
.00000 00281
.00000 00284
.00000 00286
.00000 00288
.00000 00291
.00000 00293
.00000 00295
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.00000 00409
.00000 0041 2
.00000 004 14
.00000 00416
.00000 0041 9
.00000 00421
.00000 00423
.00000 00426
.00000 00428
.00000 00430
.00000 00433
.0000000435
.00000 00437
.00000 00440
.00000 0044 2
.00000 00444
.000000
.000000
.000000
.000000
.000000
.OC 00 00
.000000
.000000
.000000
.000000
.000000
.000000
.000000
.00 0000
.000000
.000000
FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
BO
Bl
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Appendix A
00558
0056 I
00563
00565
00568
00570
00572
00575
00577
00579
00582
00584
00586
00589
00591
00593
117
TABLE OF POWERS OF TWO
n
MATHEMATICAL CONSTANTS
n
2
n 2I
2
4
8
16
32
64
128
256
512
I 024
2 048
"
8
16
32
1
2
4
9
096
192
384
768
0 1.0
1 0.5
2 0.25
3 0.125
4 0.062 5
5 0.031 25
6 0.015 625
7 0.007 812 5
906
953
976
488
25
125
562 5
281 25
0.000
0.000
0.000
0.000
244
122
061
030
140
070
035
517
12
13
14
15
Decimal Value
3.1" 159 26535 89793
3.243F
IT-I
0.31830 98861 83790
0.517C
C1B7
.JW
1.772"5 38509 05516
I.C5BF
891C
625
312 5
156 25
578 125
65
131
262
524
536
072
144
288
16 0.000 015 258 789
17 0.000 007 629 394
18 0.000 003 814 697
19 0.000 001 907 348
062
531
265
632
5
25
625
812 5
I
2
4
8
048
097
194
388
576
152
304
608
20
21
22
23
0.000
0.000
0.000
0.000
000
000
000
000
953
476
238
119
674
837
418
209
316
158
579
289
406
203
101
550
25
125
562 5
781 25
16
33
67
134
777
554
108
217
216
432
864
728
24
25
26
27
0.000
0.000
0.000
0.000
000
000
000
000
059
029
014
007
604
802
901
450
644
322
161
580
775
387
193
596
390
695
847
923
625
312 5
656 25
828 125
268
536
I 073
2 147
435
870
741
483
456
912
824
648
28
29
30
31
0.000
0.000
0.000
0.000
000
000
000
000
003
001
000
000
725
862
931
465
290
645
322
661
298
149
574
287
461
230
615
307
914
957
478
739
062
031
515
257
5
25
625
812 5
4
8
17
34
294
589
179
359
967
934
869
738
296
592
184
368
32
33
34
35
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
232
116
058
029
830
415
207
103
643
321
660
830
653
826
913
456
869
934
467
733
628
814
407
703
906
453
226
613
25
125
562 5
281 25
68
137
274
549
719
438
877
755
476
953
906
813
736
472
944
888
36
37
38
39
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
014
007
003
001
551
275
637
818
915
957
978
989
228
614
807
403
366
183
091
545
851
425
712
856
806
903
951
475
640
320
660
830
625
312 5
156 25
078 125
I
2
4
8
099
199
398
796
511
023
046
093
627
255
511
022
776
552
104
208
40
41
42
43
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
909
454
227
113
494
747
373
686
701
350
675
837
772
886
443
721
928
464
232
616
237
118
059
029
915
957
478
739
039
519
759
379
062
531
765
882
5
25
625
812 5
17
35
70
140
592
184
368
737
186
372
744
488
044
088
177
355
416
832
664
328
44
45
46
47
0.000
0.000
0.000
0.000
000
000
000
000
000
000
000
000
000
000
000
000
056
028
014
007
843
421
210
105
418
709
854
427
860
430
715
357
808
404
202
601
014
007
003
001
869
434
717
858
689
844
422
711
941
970
485
242
406
703
351
675
281
562
1 125
2 251
474
949
899
799
976
953
906
813
710
421
842
685
656
312
624
248
48 0.000 000 000 000
49 0.000 000 000 000
50 0.000 000 000 000
51 0.000 000 000 000
003
001
000
000
552
776
888
444
713
356
178
089
678 800
839 400
419 700
209850
500
250
125
062
929
464
232
616
355
677
338
169
621
810
905
452
337 890
668 945
334 472
667236
625
312 5
656 25
328 125
InIT
1.1«72 98858 "9400
1.2500
CMBF
2.71828 18284 590t45
2.B7El
5163
0.36787 9«11 71«2
0.5E20
5809
..Je
1.64872 12707 00128
I.A612
98E2
loglOe
0.43429 44819 03252
0.6F20
EC55
log2 e
1.«269
1]15"
7653
-1
0.57721 56649 01533
0.93C"
67E4
-0.54953 93129 81645
-0.8CAE
9BCl
.J2
1.41421 35623 73095
1.6A09
E668
In 2
0.69314 71805 59945
O.BI72
17F8
logl02
0.30102 99956 63981
0.4010
40"2
..JlO
3.16227 76601 68379
3.298B
075C
In 10
2.30258 "0929 94Q.46
2. "D76
3777
25
125
562 5
781 25
599
199
398
797
627
254
509
018
370
740
481
963
496
992
984
968
52 0.000 000 000
53 0.000 000 000
54 0.000 000 000
55 0.000 000 000
000
000
000
000
000
000
000
000
222
II I
055
027
044
022
511
755
604 925
302 462
151 231
575615
031 308
515 654
257827
628 913
084
042
021
510
726
363
181
590
333 618
166 809
583404
791 702
164
082
541
270
062
031
015
507
5
25
625
812 5
72
144
288
576
057
115
230
460
594
188
376
752
037
075
151
303
927
855
711
423
936
872
744
488
56 0.000 000 000
57 0.000 000 000
58 0.000 000 000
59 0.000 000 000
000
000
000
000
000
000
000
000
013
006
003
001
877
938
469
734
787 807
893 903
446951
723 475
814 456
907 228
953614
976 807
755
377
188
094
295
647
823
411
395
697
848
924
851
925
962
481
135
567
783
391
253
626
813
906
906
953
476
738
25
125
562 5
281 25
152
305
611
223
921
843
686
372
504
009
018
036
606
213
427
854
846
693
387
775
976 60 0.000
952 61 0.000
904 62 0.000
808 63 '0.000
000
000
000
000
000
000
000
000
000
000
000
000
867
433
216
108
361 737 988 403
680 868 994201
840 434 497 100
420217248 550
547
773
886
443
205
602
801
400
962 240
981 120
490 560
745280
695
347
173
086
953
976
988
994
369
684
342
171
140
570
285
142
118
Appendix A
88963
Y
503
007
014
028
000
000
000
000
~
InY
4
9
18
36
000
000
000
000
6A89
e
e
8 0.003
9 0.00 I
10 0.000
11 0.000
Hexadecimal Value
Constant
625
312 5
156 25
578 125
APPENDIX B. REFERENCE DIAGRAMS
This appendix contains flow diagrams that are intended to
illustrate the major operations involved during the execution of instructions by the SIGMA 6 computer. The flow
diagrams are not intended to depict actual computer operati ons and sequences, but the operations and sequences
shown are valid representations of the internal computer
operations. The symbolic notation used in the flow diagrams is consistent with that used in other portions of this
reference manual. The symbolic terms used are:
Term
Meaning
A
An internal CPU register used to hold an operand
obtained from the general register that is specified by the R field value in the instruction word.
AC
Access control code - the code used to determine
whether or not a slave program operating with
the memory map may read from, access instruction from, or write into a specific page of virtual
addresses.
ADDR
Address - any virtua I address.
B
An internal CPU register used to hold an operand
obtained from the ~eneral register that is specified by the value produced by performing a logicalOR between the R field of the instruction and
the va lue 1.
C
An interna I CPU register used to hold an immediate
operand obtained from the instruction, or a byte,
halfword, or word operand obtained from the memory (or general register) location specified by
the effective address of the instruction. For
doubleword operations, this register holds the 32
high-order bits of the effective doubleword.
D
An internal CPU register used to hold the32 loworder bits of the effective doubleword in a doubleword operation.
EB
Effective byte.
EBL
Effective byte location.
ED
Effective doubleword
EDL
Effective doubl eword location.
EH
Effective halfword.
EHL
Effective ha Ifword location.
EW
Effective word.
EWL
Effective word location.
Instruction register.
IA
Instruction address.
IRA
Indi rec t reference address.
MA
Memory Address - an actua I core memory address.
OP
Operation code - bits 1-7 of an instruction word.
R
General register address value.
TCC
Trap condition code - the code that is used during
the EXCHANGE PROGRAM STATUS DOUBLEWORD (XPSD) instruction.
TYPE
Memory access type - the following values are
used to indicate the reason for accessing memory:
o=
write
1 = instruction read
2 = operand read
WK
Write key
WL
Write lock
X
Index register designator.
NOTES ON BASIC SIGMA 6 INSTRUCTION
EXECUTION CYCLE
The hexagonal elements in the flow diagram labeled
"Memory Contro I" refer to th~ memory request process
shown at the right of the basic flow diagram. The memory
request process is represented as a subrouti ne with two inputs:
an address value (ADDR) and a memory access TYPE, separated by a slash, that correspond to the values shown in the
"Memory Control II elements of the basic flow diagram.
The circular entry point labeled "TRAP" is a continuation
of the circular exit points labeled "Trap X'n''', where n is
the appropriate trap location.
The triangular entry point labeled "EXU" indicates the
point in the basic flow diagram at which an instruction
(being executed as an operand of the EXECUTE instruction)
is started.
The triangular entry point labeled "ANLZ" indicates the
point in the basic flow diagram at which the effective address computation for the instruction being analyzed is
started; the triangular exit points indicate the completion
of the effective address calculation.
Appendix B
119
BASIC SIGMA 6 INSTRUCTION EXECUTION CYCLE
(1)15-33' (X)13-31- '15-331------,
EB -
C 2 4-31
0 - C0-23
0- 0
EW-C
0-0
120
Appendix B
BASIC SIGMA 6 INSTRUCTION EXECUTION CYCLE (cont.)
o
yes
Appendix B
121
FLOATlNG- POINT INSTRUCTION EXECUTION
FLOAnNG-POINT MULnpUCAnON AND DIVISION
yes
no
no
122
Appendix B
FLOATING-POINT ADDITION AND SUBTRACTION
Right shift number with
smaller characteristic and
increment its characteristic by 1 far each hex
place shifted until the
characteristics of the numben are equal
X'5'- CC
yes
yes
<
pastnarmalization ~_ _.....;..:......_ _....
required mare than
2 hex shifts?
no
Appendix B
123
FLOATING-POINT SHIFT
yes
yes
RIGHT SHIFT
lEFT SHIFT
no
yes
Shift fraction risht 1 hex place,
fill vacated bit pcIIitions on the
left with O's, increment characteristic field by I, and increment shift caunt by one.
Shift fraction left 1 hex place,
fill vacated bit position on the
right with O's, decrement characteristic field by I, and decrement shift count by I.
Form the 2's complement of the final
floating-point number
0-Ce3
I-CC4
124
Appendix B
EDIT BYTE STRING INSTRUCTION EXECUTION
Fill - (R)O_7
SA
= (R)I3-31
0=(1)12_31
C
DA
= (Ru 1)0-7
= (Ru 1)13-31
= byte buffer
= byte buffer
II = digit buffer
d. = X'2O'
•• ~ X'21'
h = X'22'
.i = X'23'
a
IJ
Appendix B
125
APPENDIX C. SIGMA 6 INSTRUCTIONS (MNEMONICS)
126
Mnemonic
Code
Instruction Name
Addressing Type
Page
AD
AH
AI
AIO
AND
ANLZ
AW
AWM
BAL
BCR
BCS
BDR
BIR
CALl
CAL2
CAL3
CAL4
CB
CBS
CD
CH
CI
CLM
CLR
CS
CVA
CVS
CW
DA
DC
DD
DH
DL
DM
OS
OSA
DST
DW
EBS
EOR
EXU
FAL
FAS
FDL
FDS
FML
FMS
FSL
FSS
HIO
INT
LAD
LAH
LAW
LB
LCD
LCF
10
50
20
6E
4B
44
30
66
6A
68
69
64
65
04
05
06
07
71
60
11
51
21
19
39
45
29
28
31
79
70
7A
56
7E
7B
78
7C
7F
36
63
48
67
10
3D
lE
3E
IF
3F
1C
3C
4F
6B
1B
5B
3B
72
1A
70
Add Ooubleword
Add Halfword
Add Immediate
Acknowl edge I/O Interrupt (pri vi I eged)
AND Word
Analyze
Add Word
Add Word to Memory
Branch and Link
Branch on Conditions Reset
Branch on Conditions Set
Branch on Decrementing Register
Branch on Incrementing Register
Call 1
Call 2
Call 3
Cal14
Compare Byte
Compare Byte String
Compare Doubleword
Compare Halfword
Compare Immediate
Compare with Limits in Memory
Compare with Limits in Register
Compare Selective
Convert by Addition
Convert by Subtraction
Compare Word
Decimal Add
Decimal Compare
Decimal Divide
Divide Halfword
Decimal Load
Decimal Multiply
Decima I Subtract
Decimal Shift Arithmetic
Decimal Store
Divide Word
Edit Byte String
Exclusive OR Word
Execute
Floating Add Long
Floating Add Short
Floating Divide Long
Floating Divide Short
optional
Floating Multiply Long
Floating Multiply Short
Floating Subtract Long
Floating Subtract Short
Halt Input/Output (privileged)
Interpret
Load Absolute Doubleword
Load Absolute Halfword
Load Absolute Word
Load Byte
Load Complement Doubleword
Load Conditions and Floating Control
Daub Ieword
Halfword
Immediate, word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Byte
Immediate, byte
Doubleword
Halfword
Immediate, word
Doubleword
Word
Word
Word
Word
Word
Byte
Byte
Byte
Halfword
Byte
Byte
Byte
Byte
Byte
Word
Immediate, byte
Word
Word
Doubleword
Word
Doubleword
Word
Doubleword
Word
Doubleword
Word
Word
Word
Doubleword
Halfword
Word
Byte
Doubleword
Byte
40
39
39
87
Appendix C
46
37
40
43
74
73
73
74
73
74
74
74
74
44
62
45
45
44
46
46
45
49
50
45
57
58
58
42
56
57
57
58
56
42
64
46
73
53
53
54
54
54
54
54
53
86
38
34
33
33
32
33
35
SIGMA 6 INSTRUCTIONS (MNEMONICS) (cont.)
Mnemonic
Code
Instruction Name
Addressing Type
Page
lCFI
02
lCH
lCW
lD
lH
LI
lM
lPSD
lRP
lS
lW
MBS
MH
MI
MMC
MSP
MTB
MTH
MTW
MW
OR
PACK
PlM
PlW
PSM
PSW
RD
S
SD
SF
SH
SIO
STB
STCF
STD
STH
STM.
STS
STW
SW
TBS
TDV
TIO
TTBS
UNPK
WAIT
WD
XPSD
XW
5A
3A
12
52
22
2A
OE
2F
4A
32
61
57
23
6F
13
73
53
33
37
49
76
OA
08
OB
09
6C
25
18
24
58
4C
75
74
15
55
28
47
35
38
41
4E
40
40
77
2E
60
OF
46
load Conditions and Floating
Control Immediate
load Complement Halfword
load Complement Word
load Doubleword
load Halfword
load Immediate
load Multiple
load Program ~tatus Doubleword }
privileged
load Register Pointer
load Selective
load Word
Move Byte String
Multiply Halfword
Multiply Immediate
Move to Memory Control (pri v iI eged)
Modify Stack Pointer
Mod ify and Test Byte
Modify and Test Halfword
Modify and Test Word
Multiply Word
OR Word
Pack Decimal Dig its
Pull Multiple
Pull Word
Push Multiple
Push Word
Read Direct (privileged)
Shift
Subtract Doubleword
Shift Floating
Subtract Halfword
Start Input/Output (privileged)
Store Byte
Store Conditions and Floating Control
Store Doubleword
Store Halfword
Store Multiple
Store Selective
Store Word
Subtract Word
Translate Byte Stri ng
Test Device
} privileged
Test Input/Output
Translate and Test Byte String
Unpack Decimal Digits
Wait
- }
Write Direct
privileged
Exchange Program Status Doubleword
Exchange Word
Immediate, word
Halfword
Word
Ooubleword
Halfword
Immediate, word
Word
Ooubleword
Word
Word
Word
Immediate, byte
Halfword
Immediate, word
Word
Ooubleword
Byte
Halfword
Word
Word
Word
Byte
Word
Word
Word
Word
Word
Word
Ooubleword
Word
Halfword
Word
Byte
Byte
Doubleword
Halfword
Word
Word
Word
Word
Immediate, byte
Word
Word
Immediate, byte
Byte
Word
Word
Doubleword
Word
35
33
33
32
32
32
35
75
77
34
32
61
41
41
77
71
43
43
44
42
46
59
70
69
70
69
80
47
41
48
40
83
36
37
36
36
37
36
36
40
63
87
86
63
59
79
80
75
36
Appendix C
127
APPENDIX D. INSTRUCTION TIMING
This appendix shows the timing (in microseconds) for
executing individual SIGMA 6 computer instructions under
a variety of circumstances. All of the times are based on
the assumption that whenever the CPU requests a service
cycle from a parti cular memory bank, it never has to wait
for such service due to other devices (such as lOPs) that
are connected to that memory bank.
execution times for some of the possible combinations of
memory bank configuration, data placement, and instruction type, where
MAX = Time with no memory overlap (i. e., all sequential memory accesses come from the same
bank)
MIN = Time with complete memory overlap (i. e. I all
sequential memory accesses come from a bank
not currently busy, that is, the bank being
accessed is not being used by the CPU or any
external lOP)
Execution times depend not only on the nature of the specific
instructions, but also on the configuration of memory banks
in the system, and the placement of instructions and operands.
The following table provides a means of estimating instruction
Average Instruction Execution Time
Memory Bank Configuration
Instructions that utilize
byte., ha Ifword,
and word addressing
Instructions that uti Iize
doubleword
addressing
A II instructions and operands are in the same
memory bank
MAX
MAX
All instructions are in one memory bank and all
operands are in a different memory bank
MIN
A II instructions and operands are in two interleaved memory banks
1/2 MAX + 1/2 MIN
1/4 MAX + 3/4 MIN
A II instructions and operands are in four interleaved memory banks
1/4 MAX + 3/4 MIN
1/8 MAX + 7/8 MIN
All instructions are in one memory bonk and all
operands are in two interleaved memory banks.
(Both operand memory banks are different from
instruction memory bank.)
Basic timing information is summarized in the following two
tables. A dash entry for any item indicates a non-applicable
or impossible condition for the instruction. Special notes
(identified by numbers in the II Notes" column are given at
the end of the table to which they apply. Table D-1 shows
the execution times for instructions under the most common
conditions that the user can expect to encounter in his program. Table D-2 shows the additional times that must be
added to the basic times if (1) the instruction performs a
register-to-register operation (i. e., accesses one or more
of the genera I registers for an operand(s) or a direct address}
or (2) the register pointer in the current program status
doubleword selects one of the register blocks in the range
from X I 4 1 through X l l P (4 through 31 decimal).
The times given in Table D-2, where the instruction performs a register-to-register operation, assume the following
conditions.
1.
The CPU is operating in the mapping mode with one
memory bank so that no memory overlap occurs.
2.
All instructions are in core memory.
128
1,12 MAX + 1/2 MIN
Appendix D
MIN
MIN
3.
In the case of an instruction with a direct address, its
operand is in one or more of the general registers. For
a push-down instruction with a direct address, however,
its stack pointer doubleword is in the general registers
and the stack is in core memory.
4.
In the case of an instruction with an indirect address,
the indirect reference is to one of the general registers,
which contains the direct address of the operand. The
resultant virtual address is assumed to be a core memory
address. For a push-down instruction with an indirect
address, therefore, both the stack pointer doubleword
and the stack are assumed to be in core memory.
The timing data given below are for a typical system. A
specific CPU may vary by up to ±1O% of the times shown.
For Jarge core memory configurations, an additional. 1 I-Isec
per memory access may be encountered due to added cable
lengths.
Table D-1.
Basic Instruction Timing
No Memory Overlap
Maximum Memory Overla)
Notes
Mnemonics
Indirect
Direct
No
Index
No
Index
+,----t---- -
I"dex
Index
Indirect
Direct
No
Index
Index
No
Index
-
R~ 0
AID
--------.------ -
6. 1
AND
-.32 .
~_ _ _ _ .,-___
AW
6. 1
..
_2_.6____2_9
No
Index
2
:.-6
6. I
~~-~~-~:
2.0
6. I
2.7
6.7
2.9__
6.7
U
..,
~.! __
I
f_-2.O
2.7
2.9
3.3
3. :
3.8
2.4
4.0
3.0
4.4
3.0
2
..
-------. r--------~ ..----i---------..--- - r - - - . - - - - l - - - - - _ + - - - - - - - . - f - - 2.0
2.3
1.0
1.7
2.0
2.4
Indirect
Direct
Index
No
Index
Index
No
Index
3.6
2.5
3.2
3.4
I
Index
3.8
_:::-~~ ~:~(~~-;;-~-+
::
,
6. I
6. 1
6.7
-'~2i3:.
'.1
,
6.7
2.6
•.•
i
6. I
6. 1
t
:~
/3.6
2.3
3.8
2.9
4.2_
2.9
1.6
1.8
2.3
3.3
0.9
1.5
1.8
2.9
2.3
____ __
~
2.6
3.9
2.8
2.9
<.S_
_~ _ _:~_r-_2.~___ ~_-+~~~
3.6
6.7
'.1
1.4
2.2
I 2.2
2.8
----+-------
6.7
2
--31..5 ---+-3 . : _ . _ 2.4
2
i
1------- f__-
2.2
.-
BCR
branch
1.0
Ii
BCR
no branch
2.0
~._6____
3._0_ _+-3-.-3-+--2-.-1--+--2-.8----3.-1-~-3-.-5--~_1_._9_~-2-.5----2.-8-_+-3-.-1--~-2-.-0-_+-2-.-7----2-.9-_+-3._3_~
BCS
branch
1.0
!I
-------T------------- ;
1.6
4_~-3.-0-.--3. 3
~~ __ -~~~--~~--~--
.._____~3-.-3-+_ •. 1
------r-32·.-03---L=-2·.~3---=--2·.99---~2·.-92
Index
No
Index
__1>---2-.
._---_.-+------1,--
6.7
03-13~.69 ---~ . 93 I
2.0
---BAA"!l~-
6. 7
Indirect
Direct
Index
~-~- ~~--- ~~--+--4.-2--+--2-.-9--+- 3_._7____3_._9_+-_4_.3_
.~----_+-------r----:-:-o-------4·-R--iO=::-~~9
.
7.' ::::
Map
No Map
Map
No Map
0.9
--------+---~------.~----~--_+------+_--_+---+_------~--~
no branch·
BCS
2.0
2.0
o. 9
1. 5
3.0
3.3
2.1
2.8
3.1
3.5
1. 9
i 2.5
2. 8
3. 1
2.0
2. 7
2.9
3.3
1. 7
2.4
2.4
1. 4
1. 8
2.4
2.5
1. 4
1. 7
2.3
2.3
1.4
1.8
2.3
2."
2.3
1.0
1.7
2.0
2.4
1. 8
2. 2
o. 9
i
J
1. 4
BDR
branch
----- BDR
no branch
J
1.6
2.6
~---~.------I__--+_------------~--_4---+_------__I-----~--~----------------1----
1. 6
2.3
1.8
----------+----~
---+---------+-----4---+_-------If_---~---f_------_+----I__---_+-------+---~
2.4
2.-
3.4
3.4
2.5
2.9
3.5
3.6
2.3
12.6
3.2
3.2
2.4
2.8
3.4
i'
3.4
~-----~------~---~-------------+----+-------
!~ ____ b_ro_nc_~____ ~~~~-~.!-------~~~---2-.4---_+-1.-4-_+--1.-8----2-._4_+-_2_.5_---t_1_.4_--+!_1._7_.__2_._3_+_2_.3__---t_1_.4_-+_1._8___
BIR
2.3
i
2.4
~ ---3.-4-l~.4
2.5
2.9
3.5
3.6
2.3
2.6
3.2
3.2
2.4
2.8
3.4
I
3.4
__ ~ _--+-=:-~_~_3___ 3.3
3.3
3.3
3.3
3.3
3. 2
3.2
3. 2
3.2
3.2
3.2
3.2
I
3.2
3.3
1.4
2.0
2.3
2.6
1.5
2.2
2.4
no branch
CAL 1-4
2. 4
r--~~--f-------r-~.-~CBS
2
-t' ~~-- -~-- -~~-f_~-
.j:~N
--
2.9
3.6
~___
2._9_
+::~N
+;:~N
2.9
+::~N
r-------f-------I-----+----------f_--I----i----------------if_----+------ii-------~---_t---_+_------i__-__I
CD
3.4
3.8
3.6
2.5
3.2
3.9
4.2
2.9
3.7
2.4
3.0
3.3
3.9
4.3
- - - - - f - - - - - - - - + - - - - - f - - - - - - - - f - - - _ + - - - t - - - - - - _ + - - ----+-----+-------I--------t
2.4
2.9
1.5
2.2
2.9
3.2
2.0
2.7
2.9
3.3
1.4
12.0
2.3
2.6
t---.---r-------~--
CH
2.0
2.6
r-------I-----
CI
:--__
1. 9
~;:;,--- ~--,~--
~--=
~ ___~__
_
~L~:~
3.0
17.1
tD.6N
117.1
! .Q.6N
DA
DC
-~~.----_+_----!__-------_+---~
--
1.9
>-;:;-- -;;--;:;- .;-- -, . 7,- - 3:3- 3.'
17.6
~0.6N
17.6
+0.6N
f_----- .-35. 2
17.1
+0.7N
17.1
+O.7N
~0.7N
17.8
38.4
38.5
f---~--f__---~- - -.. - ---
17.8
+0.7N
f-------
17.1
+O.5N
17.1
+O.5N
17.3
to.6N
- - - - - - - - - - - - - ..
17.3
17.3
17.2
17.2
.0.7N
+O.7N
+O.6N
+O.6N
- - - f-----"1i-----------+-----I
36.7
36.6
33. 7
36. 8
36.7
33.2
1.4
2.0
2.3
2.6
1.5
2.2
2.4
2.9
20.6
20.6
19.2
19.2
20.0
20.0
19.4
19.4
::.:O--r~:~--;~:-:-~--- ~::~~ _:_:~ -~~:-7- ~::D ~::o ~::D ~::o ~::D
20.6
+0.30
20.6
+0.30
::::0
+0.30
+0.30
~::o I ~::~D 12.8 , 12.8
-'0.30
+0.30
+0.30 I+0.30
-----+-----1
30.8
+O.8K
31.4
+O.8K
31.4
+0.8K
11:S---
12.5
19.2
I .0.30
20.0
.0.30
20.0
+0.30
19.4
+0.30
---~---.----------
.!:!..__
19.4
+0.30
+0.30
+0.30
33. 7
-----------
+0.30
+0.3D
+0.30
12.4
113.0
13.4
~113.7
12.4
30.8
31.4
31.4
+0. 8K ____ ~~__ +0.8K
13.2
13.4
13.8
29.7
+0.8K
j29.7
+O.8K
30.3
+O.8K
.
30.3
+O.8K
30.8
+O.8K
::A
-- - -
oST
6
~.:3~Nti+~._~__~.30_+~~~~ ,~._3~_ +O.~__ +~~~__
612
__ ~_4~N
61.2
61.8
\' 61.8
62.3
~._4~~ _~_~~~_ ~~~4D~ ~~4~
62.3
62.9
62.9
61.2
12.0
to. 70
11.3
+0.7D
61.2
61.8
61.8
.~~~_ ~_~_~~o~ _+O.4~~ ~~~~~:~~ __ ~4DN
-t
12.0
+O.7D
11.3
+0.70
12.1
.0. 70
12.5
+0.3~___ ~~-~--tO.3~-~~-~~---~~--~0.30-- ~0.3~ __
~------+-------------._i---- ---- -------- -.--- .. - - - - - - - , - - - - -
/".3
i .0.70
13.7
+0.30
-- ~:o ~-:O~§.!O-~!O- _~~c:~o_~:o_ ~:o
11.3
+0. 70
I
~U- Q-0---~3 ~---~~-1--13.3
~--- - 4 - - ~~~~--_r~~;----1-2~~--11~4--~- -~;~~--tl~·~--~-;~-- 12.5~;~;--~~~~--~~~--- ~2~;-- --;-~
OM
___
3.8
33. 2
38.4
~-------
~:~_~~ __ f_--2..:~
+0:
______________
3.4
3.3
------.------ -.---.
29.7
l29.7
30.3
30.3
30.8
___ .. _________ ~. 8K _ ~~.~~ __
8K .. ~ I~:~~__ +0.8K
DH
3.2
17.3
.0.6N
-------+-----------'--------- ------- - - - - - - - . - - - - - - - ----.- - . - - - - -
----------
2.5
3-.-1--_+--1-.8---+-2.-6-----2-.-8--+-3-.-2--1
2.9
----f~
19.2
---_._--
I --
. 4~~ ~·-=-_~_+2~ ____ ~~__ ~~_f_~-~-~~8---- ~~_~--~--.-7----3-.-9---+--4.-3---I
___2.0_!_~~ ___
-
1. 8
38.5
--- -- -
CW
- -
_~__~___ ~ ____~. ~ _ _2~_ ~.~3____ ~~_____ ~~_
------ --------+-----------34. 7
i 34. 7
35. 2
CVS
---_.-
DO
'l' ,-
~=;. 0 _t6_~~2. 9_
CVA
- - - - - -----
r3.'3
i
2.0
12.1
+0.70
62.3
+0.4oN
62.3
+O.4DN
62.9
+O.4oN
62.9
+O.4DN
:·:0 ::0 ::0 ::0 ::0 ::0 ::0 ::0
-------< - - - - - - - - - - - - - - - - I
----------------~-
11.3
+0. 70
11.3
+0.70
11.3
+0.70
12.0
+0.70
12.0
to. 70
11.3
+0. 7D
12.1
+0.70
I 12.1
I +0.7D
Appendix D
129
Table D-1.
Basic Instruction Timing (cont. )
No Memory Overlap
Maximum Memory Ovedop
No Map
- - - --Direct
Indirect
Direct
f---- - r - - - -- - - r'
No
No
No
Mop
No Mop
Mop
-- - - - - - - - - - r-----------,.--------i
Indirect
Direct
Indirect
Direct
Indirect
---- - - - - - - ----_t----.----\
No
No
No
No
No
Index
Index
--."'--
i
DW
13.8
:;5 _-_ ~j" '-__
EOR
_
EXU
19
-
1.8
2.~ _ _ 2.~+
1.
1.6
3.0
I.B .__ 2.5
2.~
31
14
2.2,2.2
18
22
2.4
I
t
-
1
20
23
126
15
2 2
2 4
2.9
1.6
2.1
2.2
1.3
1.8
2 2
2.4
r
~---~~---+----+----.~--~
I:: -- ,:; ,:; ,::' ,:: ,:: ,:: ,:; !,:L ,:; ,:: ,:: ,::
j~:-:~:
_!~LtYPir.alj'12
FASmin
------
r
I
FAS max
5.0
5.5 ___ ~___ ~ ___ ~~r-~.7
6.0
10
3.3
3.9
4.2
4.2
11
B.2
8.9
9.1
4.6
3.3
4.0
B.2
9.0
--- - - "
--.--.- ·----1
_~~ty~~co~J~2
9.5
-. ---.---- -----.-----.
__ ~O__
4.6
4.9
5.3
FDLmin
113,14
254
261
26.4
126.7
FDL
r1I-
34 7
r- 35 ..
12 4
r;3 ;---
6.4
5.0
4.7
3.3
------1---9. I
9.6
B.2
~---r--"
4._0__ ~_4.7
5.5
5.9
3.9
4.2
----- .---8.9
9. I
,::--'~~-+-I-:-.--:--t-I-:-'~---I
6.1
5.1
5.7
6.0
6.4
4.6
3.3
4.0
4.2
4.7
9.5
8.2
9.0
9. I
9.6
-----.-.-----t----.,.---f----+---_+_--~
4.9
5.4
4.0
4.6
4.9
5.3
4.0
4.7
4.9
27.0
26.B
25.4
26.1
26.-4
26.7
25.5
261
270
- -35.4
36.3
36.1
34.7
35.4
35.7
36.0
- -13.4
:-;;...--
5.4
-.-f---
ma~-
FDS min
f-- -
13,14
I
-
35 7
13~
~I 36.0
255
34 B
-~3- 7 -- -~2
4
26.1
r-~~:~"-- t~=~-~-!~~6- ~~;---~~-- _17-;~= ~~.-;FMlmin
13,14
9.1
f - - .--- --.- - - - -
.
9.8
10.0
10.4
9.2
13. B -.. 12.4
-;7.6
17.6
IB.-;;-
10.0
10.2
10.6
13.3 - -
~3~~T
16.61-;.~-- -;~~--9.1
9.8
10.0
34.8-- 35:4
36:3t36~I--
~2.-i-- ;3~.4--- 13:~-
13.7
26B
-tru--
-1-7-.9--+--16-.·-6-+-17-.-6-+-1-7-.6--t-I-B-.O- - I
10.4
9.2
10.0
10.2110.6
----t--__j----t----+--__jc----+_---~r_---_+_--_t---+----
- - - ----- -----
14.7
15.4
15.6
16.0
14.8
15.6
IS.8
16.2
14.7
15.4
15.6
16.0
14.8
15.6
15.8
16.2
- - - -..-- .... - - . - - - - - - + - - - + _ - - - + - - - - I , - - - + _ - - - - t - - - f - - - - + - - - + - - - f - - - - + - - - - f - - - + - - - - + - -....-+----1
2
FMLmox"
f----.--
::~ ~;;j ~,,,-::. ..~_:_.-_.
~~~__
I 10
F5lmax
fil
__
:_~
_+-.:__:
+-_:_:_:_+-.1_:_::--+-::-:-+-:-:-:-_+-:-:-:-_+_1-:-::_ _ +_:._.:_.+_:_:_:_+ __:_:_:_+-1_:
__: 0_
:_+_::_:_+_:_:_:_+1_:_:
~-4-.-1-+_-4-.-7-~-5-.0-_+_-5.-3-~-4-.-2-~-4-.-9-4--S-.-1._t--_5._5_-+_4_._I_+_-4-.-7-t---5-.0-~-S-.3--+-4-.--2 ~_4_._9_+_-5-.I-_t-S-.-5--I
13.7
14.2
14.6
14.8
13.8
14.4
14.7
15.1
13.7
14.2
14.6
14.8
13.8
14.4
14.7
IS.I
~;yp.;~'t_'2~=-_. ~.-.~--5-.5--+-5-.-9-+-6.-.-1-4_-5-.-1-_+_-5-.7-_+-6.-0-+-6_._4_~-5-.-0-+_-5-.5-+-5.-9-+_-6-.-1-~-5-.-1-_+_-5-.7-_t-6._0 _+-6-.-4-~
-
~min
_
~ _ _ .. _~~--+_-4.-2-~-4-.-6-;--3-.-3-+_-4-.0-_+-4.-2-_r-4-.-7_-r. _3_._3_ _+_-3-.9-~-4.-2-+-4-.-6-+-3-.-3. --+_-4-.0-_t-4-.2_-+_4_._7_-1
__
F5S mox
I 11
8.2
8.9
9. I
9.5
8.2
9.0
9. I
9.6
8.2
8.9
9. I
9. 5
8.2
9.0
9. I
9.6
f__---_+-------- - - - - -..----~--~----_+---+---_+---;---1_--_+_--_+---+_--_;---t__--+_--_+-----1
FSS typical 12
4.0
4.6
4.7
4.9
4.9
5.3
4.0
4.0
4.6
4.9
5.3
4.0
4.7
4.9
5.4
5.4
- -- ~----4------+_----_+----~f------_r----_+----~r-----~------~----+_----_+------~----~
r--'HIO
R = even,/O 9.7
9.7
10.3
10.3
9.7
9.7
9.4
9.5
10.. 3
10.3
9.4
10.0
10.0
9.5
10. I
10. I
~-.-
.. -
--
-+-----1--.--
------.-.-
HIO
R = odd
- - - - r'--'--'-HIO
R= 0
8.3
f-----
7. I
8.3
- - - . --
7. I
8.9
8.9
8.3
8.3
8. 9
8.9
8.3
8.3
8.9
8.9
8.3
8.9
8.3
8.9
-f-.---+_---_t---f---_t----f----;----+---_+----+_------if__---+---_+-----f__---I
7.7
7.7
7. I
7. I
7.7
7. I
7.7
7.7
7. I
7.7
7.7
7.7
7. I
7. I
-----------+--------+-----r-----~----_r----_t------f__----1_----1_----~------i-----,f__----+_----_t----_+------+-----1------1
INT
2.4
3.0
3.4
3.6
2.5
3.2
3.4
3.8
2.3
2.9
3.2
3.5
2.4
3. I
3.3
LAD
3.4
4.0
4.3
4.6
3.4
4.2
4.4
4.8
3. I
3.7
4.0
4.3
3.2
3.9
4.2
4.6
2.0
2.6
2.9
3.2
2.0
2.7
2.9
3.3
1.8
2.4
2.7
3.0
1.8
2.5
2.7
3. I
2.0
2.6
2.9
3.2
2.0
2..7
2.9
3.3
1.8
2.4
2.7
3.0
1.8
2.5
2.7
3. I
2.0
2.6
2.9
3.2
2.0
2.7
2.9
3.3
1.8
2.4
2. 7
3.0
1.8
2.5
2.7
i
LAH
LAW
LB
l
1
~------
LCD
3..7
3. I
--------T-----+_----_1----~f__----_r----_1------~----_+------~----+_----4-----_+------~----+------t__----~----~
LCF
2.9
3.6
3.9
4.2
2.9
3.7
3.9
4.3
2.4
3.0
3.3
3.6
2.S
3.2
3.4
3.8
2.0
2.6
2.9
3.2
2.0
2.7
2.9
3.3
1.8
2.4
2.7
3.0
1.8
2.5
2.7
3.1
LCFI
1.3
LCH
2.0
2.6
2.9
3.2
2.0
2.7
2.9
3.3
1.8
2.4
2.7
3.0
1.8
2.5
2.7
3.1
LCW
2.0
2.6
2.9
3.2
2.0
2.7
2.9
3. 3
1.8
2.4
2.7
3.0
1.8
2.5
2.7
3.1
LD
2.9
3.6
3.9
4.2
2.9
3.7
3.9
4.3
2.4
3.0
3.3
3.6
2.5
3.2
3.4
3.8
1.4
1.3
1.4
f----------4--------i-----1------~----_+------r-----1_----__jf__----r_----~----_+------r_----_r------r_----~---_+------+_----1
LH
2.0
Ll
1.3
LM
15
2.3
+1.0N
2.6
2.9
3.2
2.0
2.7
2.9
3.3
1.4
2.3
+LON
3.0
+1. ON
3.0
+1.0N
2.4
+1. IN
1.8
2.4
2.7
3.0
2.4
+1. IN
3.0
+1.IN
3.0
+1. IN
2.2
+1.0N
1.8
2.5
2.7
3.1
2.3
+I.IN
2.8
+LIN
2.8
+LIN
1.4
1.3
2. 2
+1. ON
2.8
+1. ON
2.8
+1. ON
2.3
+1. IN
f-----.----.---------r-----r-----+----_+------+------+------f-----+_----_t------f------+_-----+------+----_r----__if__----~----~
lPSD
4.4
4.4
5.0
5.0
4.7
4.7
5.2
5.2
5.0
5.0
4.7
4.7
5.2
5.2
3.4
2.3
3.0
3.2
3.6
~------------1-----1-----__ir_----+_-----~----__i~----_r----_+------r_----4_----_+--
LRP
130
2. 2
Appendix D
2.8
3. I
3.4
2. 3
3.0
3. 2
3.6
2. 2
2.8
3. I
Table D-l.
Basic Instruction Timing (cont. )
No Memory Overlap
Maximum Memory Over;"p
No Map
Notes
Mnemonics
Direct
Indirect
No - - , -
No
Index
3.4
;~: ~N
MBS byte
4.2
+3,4N
Index
Index
Index
Index
--:;;---
Index
Index
--
--- --- ---
I - -
4.4
to.8N
- -
,
- -
Index
- -
4.3
t3.4N
4. 2
to. aN
3,4
-;.-; --
3.8
MH
4.8
4.4
4.7
~M-M_:-:--+R-I-O--~~
5.3
3.1
+3. IN
4.8
3.8
5.1
---
ii
- -
I
------+
3.9
4.7
4.9
5.3
!
-------+---------+----
I
3.1
+3. ON
t
~;gl~-~~-----;r---:-:-~---'~--:-:-~--~---~-~----~-:-:-~-:-:-:-~-:-:-:-~-:-::---+:-:-::--+il--:-:-~! !
--c---
~:_:_- :~-(::-=tIl~:--tit:___~c~~_ :: :: :: :~t::
. _M_:__:_: __
I'
5.1
3.0
+2.9N
----+--
r-
---t--
4.4
to.8N
-------
3.~-
2.4'
-------
5.0
- - - - - - . - - - c-------- - - - - -
i
-;-;
4.3
+3.4N
-----------c--.-.---
5.1
-===±::::===--==+=====1
-;~- ~~-
------
4.9
- - - - - - - - - - f - - - --
MI
5.0
I - - - - - - - + - - - - + - - -~~- --3.0
MMC
15
+3.0N
Index
3.3~±tt±i5
39
4.2
+3.4N
3.9
5. I
I Index : Index
Index
2.6
- -
--1------ ---~'----+-----~I-
Indirect
-N~-T--
Index
--- - - - -
- -
t
3.7
- - --
-- - - - - -- - -
Direct
,-------N--;;-- ----f---N;;--i--- ---
No
--f---
Indirect
3.7
2.6
3.3
3.5
3.9
2.5
3.1
3. 0-- -~;_r__;-;_ ~- ~ r-~7- ~-
-----r----+-----
MBS word
Direct
No
--- - -
2.5
3.1
---------;r--1.-8-- "2.~-
LW
Indirect
No
Map
No Map
Direct
IndeXr~ndex
Index
- - c-- - -
lS
Map
:_:__-+_:_:_--.i_:_:__
_:___-+
4.1
~-:_'~:~ -i
+
I; _ : _ :
____-_:',
MTW
RIO
3.8
,4.2
MTW
R~ 0
3.4
3.8
6.0
6.5
MW
2.2
2.4
2_ 8
12 . 0
itO.6N
; 12.8
+0.6N
12.8
+0 6N
OR
PACK
16
1--_ _ _ _+--____ +-tO_._6_~_ .._
PLM
+~.~N_l~.:.6-~_+ ':?..:.6f\J._~~~~_+ to.6N
,.. -1-1------,;:-t'::15
10.0
10.0110.8110.8
+1 ON l1.0N I t1.0N ! 'LON
,
10.5110.5
+1 IN
t1.1N
to.6N
to.6N
12.0
+O.6N
+0.6N
to.6N
i +0.6N
11.!
+1. IN
11.1
+1 IN
9.5
+ION
9.5
+10N
10.0
+10N
I
'~----1--
i10.0
+1 ON
i'
12.0
to.6N
1
10.2
+1.0N
i 10.2
: +1.0N
+---~
, 10.7
-1. IN
~:--+5 -_'::_-'~~-
~-11~~--~;;- ~~:---~~-+I~:-+~::: -f~~-~~~ :1:.: I~::
I------Jt---------
T1.0N
PSW!
+I~_ r~:-~~ ~~_~~~I ON
9.8
i 9.8
110.5
i 10.5
I
...r--------RO- ---.-+j-nt-e-rn-a-,- - t 2:'
external
RO
17
S left
18
2.8
2.5
_+
1}8
I
Srih,
9
50
118
2.1
L--- _~._:N__
i
.. G
SF If
ISingle
9.3
9.3
3. 1
2.5
3 ,4
2.8
3. 1
3.4
I
2.83,4
2.8!
1
+1.0N
9,8
9.8
9.8
; 9.9
: 10.5
[10.5
2.5
3. 1
3. 1
2.5: 2 5
: 3. 1
I
3 I
2.8
1 3.4
3. 4
2.8
I
3.4
1
i
2.8
: 3_4
~:~~--I +_0~4~_c--::<>,4~_11:0,4~_ _tO'4N _~4~_+~:_~_1 to.~~ ~~:~~--+_'~~~~_~_:I'J
2.2
i
2.2
2.8
2.8
2. I
2.8
1
2. 8
2.2
1 2. 2
2.9
2.9
2.1
1
2. I
I 2.7
2. 1
1
'"
to_'.~~__ ~~2~_li.02N"'. 2N . r : ' N . - c:C·.2N- ."'~_ ~"'-t
3.6
2.6
,0.2N
10.9
10.9
II:::
+1.0~~:
+0.8N
I
i .1.0N
10.7
+1. 1 N
I
2.7
2.1
2.8
2.2
i
2.1
!
2.2
: 2.7
+1.0N
: +O,4N
!
2.7
-~~~-J:-~:-~r:..- -~~~--t.~~~~r:.- _~~~ _~~~_(~.~~_++O:-~r:.--, ~~ _I~_ ~~_+_~~-~O~~-j~
+2.1
2.9
to.8N
10.~~
2.5
_
I to.8N
+1. ON
1- 3~ ~-, I
3.4
+O.9N
+1.0N
3. 1
+0.41''---t-0~~I'~__L~.4N__ L- ~:4N
2. I
I 2. I
I 2.7 I 2.7
r---------L---- .0. I~__ ~ +O~~N__
j +1.0N
I
3.9
4.2
2.6
3.2
" ' . " ' , 0 . 2N
3.2
I'0.2N
I
2.9
3.7
2.7
2.7
'0. 2'#tO.2N
2"
3.9
4.3
2.4
3.0
3.3
+0.2N
3.3
+0.2N
2.6
-+{).2N
2.6
+0.2N
4.7
4.7
4.0
4.0
4.6
to.6N
4.6
to.6N
3.8
+O.6N
3.8
to.6N
,
2. 8
~. 2N
I 3.3
"'. " ' _ : 0 '"
3.6
2.5
3.2
+0.2N
2.7
to.2N
4.6
4.6
~~_:~ ____~~+ +{).2N_ TO.2N
4.
+0.2N
I 3.2
J +0. 2N
i ,0. 2N
3.2
'I
l
2.7
+0. 2N
12.9
,"'. 2N
12.9
~
i
3.4
!
!
3.3
I
iTO. 2N
3.8
3.3
+O.2N
~~--i;j;~~
+~:_:N ~-~~_l_:-,~-._-.-r_~. ;~=l:N_£:;~J:cl~J:-c:rrN-c-~:N
+_~:~N_·t~;N- ~:NI i'~~N1
I
I
4. I ~.~_~- ~:~N
_
SF left
double
SF . h
rig t
Idouble
r---~--
::
510
STB
119
3.8
+0.6N
3.8
to.6N
4.6
~~~
u.6
_ +O.2N __
4.4
to.6N
4.4
+O.6N
I
4. I
4.
+~~:~---t' +~3_~. __ ~!~_ ~O..:~
3.9
to.6N
I
3.9
to.6N
4.4
to.6N
4.4
+{).6N
3.9
to.6N
::::",~':: 1: :~jl_~=_;:~l'~ :~ ~~[:T~;f; J;~;_ci~ ~~±--i;-;,:- ':
'R~O
_ _ 7.1
3.0
'sTcF'-- ------ -3.-0
5TD
'.,
II
4.0
4.0
to.2N ___to.2~_
7.1
~~
3.0;
3.6
3.0
3:6---1-3.'6--
3.-6----;.6
____ 7.7 ___
13.6
7.1
3.1
r-~:-~---l~:~ I~__ ~~__+~~
3.1
3.7
3.7
2.9
2.9
i .0.2N
I
3.9
i to.6N
4. I
,4. 7
+0.2N! +O.2N
4 . 6 , 4.6
,to.6N I TO.6N
::-1 : : : :
_7.7
7.7
7.1
7.1-+-;~~~
3.5
13.5
3.0
3.1
3.0
3. I
i
-3.I--~-- '---3.7-- -3. i- c--- 2. 9 --~+i5I3. 5
3.I,! 3.7
3.6!-~
-~~~---t 4.-;-·3.-;----;~;---~~_;_--___z;-- 3.2-;;-1-~;-l--;-·7-- -;.-5----r--;-~- r---;~;-j--;:-;-
Appendix D
131
Table D-l.
~ I
I ''',,~..,onics'
Basic Instruction Timing (cont.)
~------------~--------~~~--M-a-x-im-u_m_M_e~m-or-y-O-v-e-rla-p----------------~
D-;"~;_~C~_op Ind;~-'----Di-re-c-t--M-,a,p--In-di-re-c-t----+--D-j-re-c-t--N-O~--dj-r-e-C-'----t----D;-re-c-'--M-rap---In-di-re--c-,- - _N_o_M_e_m,o_'y_o_v_e_rl_ap____
Noles
I
- -
-- N-;;-- ------f--~,-
No
No
No
No
No
No
Index
Index
Index
Index
Index
Index
Index
Index
Index
Index
Index
Index
Index
Inde"
Index
Index
3.0
3.0
3.6
3.6
3.1
3.1
3.7
3.7
2.8
2.8
3.5
3_9
3.0
3.0
3.6
4.0
2.2
,1.0N
2.2
+1.0N
2.-S
+1. ON
2.8
tl.ON
2. 1
+
1.3
1.3
0.9
0.7
1.6
1.3
FSL
2.3
1.6
1.5
1.5
0.4
0.3
O.B
0.6
1.5
0.8
1.5
1.5
0.4
0.3
0.8
0.6
1.5
1.5
0.6
0.6
0.9
0.9
r--------1---+--_1--+_-~~-;_---_+---;---~----_+--_;
AW
1.2
0.5
1.2
1.3
0.4
0.3
0.8
0.6
FSS
A'V/M
2.2
1.6 ' 1.3
1.3
0.4
0.3
0.8
0.6
HIO
t---.--I------+---+----+--+---+------jf----+---t---~I-__I
BAl
OJ
0.7
1.4
1.4
0.4
0.4
0.7
0.7
INT
1.4
0.7
1.4
1.4
0.4
0.3
0.8
0.6
1.3
0.7
1.3
1.4
0.3
0.3
0.7
0.6
LAD
2.3
1.5
1.3
1.3
0.4
D.3
0.8
0.6
LAH
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
0.3
0.3
0.7
0.6
LAW
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
LB
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
0.3
0.3
0.7
0.6
LCD
2.2
1.4
1.2
1.2
0.4
0.3
O.B
0.6
LCF
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
BCR
branch
BCR
no blanch
2.1
1.9
1.3
1.3
BCS
branch
1.3
0.7
1.3
1.4
BCS
no branch
2.5
1.9
1.3
1.3
BDR
blanch
1.4
0.9
1.4
1.4
BDR
nob,allch
BIR
branch
.'-'--- - - -- -
I
- - ----- ----..--+----_+--+_--+----1
2.4
2.1
1.2
1.3
1.4
0.9
1.4
1.4
0.3
0.3
0.7
0.6
LCFI
0.1
--------+------4----~--_+-----~--_1~----~--~----~----+_--~
BIR
no branch
2.4
2.1
CAL
1,2,3,4
1.3
1.4
0.4
0.4
0.7
0.7
1.3
1.3
0.4
0.3
0.8
0.6
LCH
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
LCW
1.2
0.5
1.3
1.4
0.4
0.3
O.B
0.6
-----.-i----+_-_1--~--_+--;_---.~I--_+_---+_--+_--~
CB
CBS
1.2
1.4
1.3
24
0.6
0.6
0.7/'J
LO
2.2
1.4
1.2
1.2
0.4
0.3
0.8
0.6
LH
1.2
0.5
1.3
1.4
0.4
0.3
0.8
0.6
1------
CD
, 22
1.4
1.2!'2
0.4
0.3
0.8
0.6
r-C-H----+-·-----t--l:-3-4--0.-6-+--1.-3-4--'-.2-+------+--0-.4-+--0.-3-+--0-.8--r-O-.6~
LI
0.1
~-----+----~---+---~---~--.----+-----+---+---------
LM
0.8N
r--.--- -----+----t--f---+---- -.--~--.+----+----~--~
0.8N
1.3
1.3
0.4
0.4
0.7
0.7
LPSO
I.B
1.8
1.5
1.5
0.4
0.3
0.8
0.6
~-C-LM-----+_---_~-I-.-5_+-1-.-2~_I-.-2-_i-1.--2-+__----+--0-.4-+--0._3_+__0-.8--r-0-.6~
LRP
1.5
0.7
1.5
1.5
0.4
0.4
0.7
0.7
~-C-LR-__+_-----t--l-._3__+-0-._7-+-_i-.4-- i 1.4
1.5
0.8
1.5
1.5
0.5
0.4
1.0
0.7
1.4
0.7
1.5
'.5
0.4
0.3
O.B
0.7
0.3
0.8
0.6
0.6
0.9
0.9
0.4
CI
0.4
0.3
O.B
0.6
LS
0.4
0.3
0.8
0.6
LW
0.4
0.4
0.7
0.7
MBS
27
0.2N
28
0.3N
CVA
30
1.4
I 1.3
I 1.4
CVS
30
1.4
1.4
0.4
0.4
0.7
1.4
CS
0.7
1.3
0.7
MBS
CW
1.3
0.6
1.3
1.3
0.4
0.3
0.8
0.6
MH
OA
0.10
0.10
1.5
1.5
0.4
0.4
0.7
0.7
MI
DC
0.10
0.10
1.5
1.5
0.4
0.4
0.7
0.7
MMC
1.5
0.6
0.8
1.5
1.5
0.4
0.4
0.8N
0.6
~---+_--~--+_-~-·--+_--+---·~-~---+_--~c---
~-D-D--~~----+_-3.-5-+-3-.-5+-1-.5-.t-l-.)---~-----1-0-.-4-+-_0_.4~f--O.-7_+-0.-7~
DH
1.5
0.7
1.4
1.4
0.4
0.3
0.8
0.6
MSP
MTB
RIO
3.5
3.5
1.5
1.5
0.4
0.4
0.7
0.7
2.1
1.4
1.5
1.5
0.4
0.3
0.8
0.6
0.4
0.3
0.8
0.6
0.4
0.3
0.8
0.6
DL
0.10
0.10
1.5
1.5
0.4
0.4
0.7
0.7
MTB
R=O
1.5
0.8
i.5
1.5
OM
3.5
3.5
1.5
j
.5
0.4
0.4
0.7
0.7
MTH
RIO
2.1
1.4
1.5
1.5
OS
O.lD
0.10
1.5
1.5
0.4
0.4
0.7
OJ
MTH
R=O
1.5
0.8
1.5
1.5
MTW
RIO
2.4
1.7
'.5
1.5
R=O
1.5
0.8
1.5
1.5
1.5
0.8
1.5
1.5
0.4
0.3
0.8
0.6
1.5
1.5
0.4
0.3
0.8
0.0
I------~----+--+--_+_--+_--t-----~--+---+--~-~
o
1.4
L4
OSA
-------+----+---+----+--- ---0.30 0.30
1.5
1 .5
DST
ow
EBS
1.5
25
0.8
1.4
1.4
0.7
1.4
1.5
0.4
0.4
0.7
0.7
---I-----+-------1~-_+-__I
OAN
0.4
0.4
0.7
0.7
MTW
0.4
0.3
0.8
0.6
MW
0.3
0.8
0.6
OR
0.3
1.4
0.7
~------+_----_r----+_--_+----t---_+------+---_+----+_----~---
EOR
1.4
0.4
PACK
O.2N
0.2N
1.5
3.2
3.2
1.1
~.-~r_.--~--_+----+_-_+--~f--_+_---+--_1--__i
EXU
26
1.5
0.7
1.5
1.5
26
0.4
0.3
0.8
0.6
PLM
'.5
0.4
0.4
0 .1-,
0.7
1.1
0.4
0.4
0.7
0.7
Appendi X D
133
Table D-2.
!
I
II:'
!
r
Register pointer selects
register block X'4' _ X'IF'
"t"Si,tt"l·tc-reg ster Operotions
,\,kerno',"c
.
"Jt~s I
Additional Instruction Timing (cant.)
(Add to times in Table D-O
-Dj·;~;-;-l-nd-il-·c-cl-+-----r--D-i-re-c-t-~-'n-d-ir-e-ct-'"
'j-;; l~n-:-ex
No
Index
Notes
No
Index
No
Index
~I-::;'.' -~t~1 :;_0_+_-In-:d-:-X.r_-:-:_t_- _+-In-:d-~,-t- :-: - -;rl-~-i-x-t- :.-:;-t
-l:t:
:
:~ -+----+--:-::--+-O-O:-:_+-::-:_+-:-::.~
--~--- --~---+- -t----+----t---I----+--__if-----f
,-- c SF
SH
2,2
1.4
1.2
1.2
1.5
0
Notes:
0.5
1.4
1.4
0.4
1.0
0.7
0.6
0.6
0.8
0.6
1.5
L3
1.2
SlW
O.B
0.9
1.4
1.5
0.3
0.3
SW
1.2
0.5
1.3
1.4
0.4
0.3
TSS
l.8N
-
--
--
--
--
--
--
0.6
TOV
0
0
1.5
1.5
0.6
0.6
0.9
0.9
0.4
0.4
07
0.7
TIO
0
0
1.5
1.5
0.6
0.6
0.9
0.9
0.6
+
u
I
I
I
I
I
I ~
I
I ~
I 4
PLEASE FOLD AND TAPENOTE: U. S. Postal Service will not deliver stapled forms
1C~
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c
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C
NO POSTAGE
NECESSARY
IF MAILED
IN THE
UNITED STATES
u
BUSINESS REPLY MAIL
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POSTAGE WILL BE PAID BY ADDRESSEE
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ATTN: PROGRAMMING PUBLICATIONS
u.
~
c:
2
~S
c(
Q
-l
o
...
Honeywell
XEROX SIGMA 6 INSTRUCtiONS (OPERATION CODES)
Code
Mnemonic
Instruction Nome
~
Code
Mnemonic
Instruc tion Nane
02
04
05
LCFI
CALI
CAL2
CAL3
CAL4
PLW
PSW
PLM
PSM
LPSD
XPSD
load Conditions ond Flooting Control Immediate
Call I
Call 2
Call 3
Call 4
Pull Word
Push Word
Pull Multiple
Push Multiple
load Program Status Doubleword
} privileged
Exchange Program Status Doubteword
35
74
74
74
74
69
69
71
71
75
75
44
45
46
47
48
49
4A
48
Analyze
Compore Selective
Exchange Word
Store Selective
40
4E
4F
ANLZ
CS
XW
STS
EOR
OR
LS
AND
S10
TlO
TDV
HIO
Stort Input/ output}
Test Input/ Output
Test Device
Halt Input/ Output
AD
CD
Add Dou b leword
Compore Doubleword
Lood Doubleword
Modify Stock Pointer
40
50
51
52
53
55
56
57
58
SA
5B
AH
CH
LH
MTH
STH
DH
MH
SH
LCH
LAH
Add Ha If word
Compore Ho I Fword
Lood Halfword
Modify ond Test Holfward
Store Hoi fword
Divide Halfword
Multiply Holfword
Subtract Halfword
Load Complement Halfword
Lood Absolute Halfword
39
60
61
63
Compare Byte String
Move Byte 5tri"9
Edit Byte String
32
41
65
CBS
MBS
EBS
BDR
BIR
AWM
EXU
BCR
BCS
8AL
INT
RD
WD
AIO
MMC
06
07
08
09
OA
OB
OE
OF
10
II
12
13
15
18
19
IA
IB
lC
10
IE
IF
20
21
22
23
24
25
28
29
2A
2B
2E
2F
30
31
32
33
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
LD
MSP
STD
SO
CLM
LCD
LAD
FSL
FAL
FDL
FML
45
32
71
Store Doubleword
Subtract Doubleword
Compore with limits in Memory
Lood Complement DO
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