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Xerox 550 Computer

Reference Manual

90 30 77A

Xerox Corporation
701 South Aviation Boulevard
EI Segundo, California 90245
213 679-4511

XEROX

Xerox 550 Computer

Reference Manual

FIRST EDITION
90 30 77A

February 1974

Price: $6.50

Printed In

~.S.A.

RELATED PUBLICATIONS
Title

Publication No.

Xerox Symbol/LN,OPS Reference Manual

90 1790

Xerox Meta-Symbol/LN,OPS Reference Manual

900952

Xerox Macro-Symbol/LN,OPS Reference Manual

90 1578

Manual Content Codes; BP - batch processing, LN - language, OPS - operations, RP - remote processing,
RT - real-time, SM - system management, TS - time-sharing, UT - utilities.

CONTENTS
l.

Instruction Exception Trap
Power On Trap
Power Off Trap
Processor Detected Fau It Flag
Register Altered Bit

XEROX 550 COMPUTER SYSTEM
Introduct i on
General Characteristics
Standard and Opti ona I Features
Genera 1- Purpose Fea tures
Time-Sharing Features
Rea 1- Time Features
Multiuse Features
Multiprocessor Features
Multiprocessor Interlock
Multiport Memory System
Manual Partitioning Capability
Multiprocessor Control Function
Shared Input/Output

1
1
3
3
4
5
6
6
6
7
7
7
7

SYSTEM ORGANIZATION

Processor C Ius ters
System Control Processor
Basic Processor
General Registers
Memory Control Storage
Computer Modes
Information Format
Information Boundaries
Instruction Register
Main Memory
Memory Unit
Maintainability and Performance
Virtual and Real Memory
Types of Addressing
Memory Address Control
Program Status Words
Centra Iized Interrupts
States of an Interrupt Level
Dialogue Between the Basic Processor and
the Interrupt System During an InterruptEntering Sequence
Dialogue During an Interrupt-Exiting
Sequence
Physical Organization
Interrupt Groups
Control of the Interrupt System
Single-Instruction Interrupts
Trap System
Trap Entry Sequence
Trap Addressing
Trap Condition Code
Nonallowed Operation Trap
Push-Down Stack Limit Trap
Fixed-Point Overflow Trap
Floating-Point Arithmetic Fault Trap
Watchdog Timer Runout Trap
Programmed Trap
CALL Instruction Trap
Hardware Error Trap

8
8
8
8
11

11
12
13
13
14
14
16
17
19
26
28
30
30

32
32
32
32
35
36

36
36
36
39
39

40
41
42
42
43
43
43

43
44
44
44
45

INSTRUCTION REPERTOIRE

Load/Store Instructions
LI
LB
LH
LW
LD
LCH
LAH
LCW
LAW
LCD
LAD
LAS
LS
LM
LCFI
LCF
LVAW
XW
STB
STH
STW
STD
STS
STM
STCF
Ana Iyze/Interpret Instructions
ANLZ
INT
Fixed-Point Arithmetic Instructions
AI
AH
AW
AD
SH
SW
SD
MI
MH
MW
DH
DW
AWM
MTB
MTH
MTW
Comparison Instructions
CI
CB

48
49
49
49
49
50
50
50
51
51
51
52
52
53
53
53
54
54
54
54

55
55
55
55
55
56
56
56
58
58
59
59
60
60
61
61
61
62
62
63
63
63
64
64
64
65
65
66
66

iii

CH
CW
CD
CS
CLR
CLM
Logical Instructions
OR
EOR
AND
Shift Instructions
S
Floating-Point Shift
SF
Convers ion Instruc t ions
CVA
CVS
Floating-Point Arithmetic Instructions
Floating-Point Numbers
Floating-Point Add and Subtract
Floating-Point Multiply and Divide
Condition Codes for Floating- Point
Instructions
FAS
FAL
FSS
FSL
FMS
FML
FDS
FDL
Push-Down Instructions (Non-Privi leged)
Stack Pointer Doubleword (SPD)
Push-Down Condition Code Settings
PSW
PLW
PSM
PLM
MSP
Push-Down Instructions (Privileged)
Status Stack Pointer Doubleword
PSS
PLS
I='VOl""II ... 'O

/1lLoll"""."",
... ,...,It"'l_~• 1_,..J.
.... _ ... : __ r
.llloJlIIV ....... ,VII.)

77
77
77
78
78
79
79
79
79
79
79
80
81
81
82
83
83
84
84
87
88
UI'

Nonallowed Operation Trap During
Execution of Branch Instruction
EXU
BCS
BCR
BIR
BDR
BAL
CALL Instructions
CAll
CAL2
CAL3

90
90
91
91
91
91
92
92
92
92
92

CAL4

_ " " ..... "'1_/

Control Instructions
Program Status Words
LPSD
XPSD
LRP
Mly",C

Loading the Memory Map
98
LMAP
98
LMAPRE
98
Loading the Access Protection Controls
98
99
Memory Write Protection Locks
LLOCKS
99
LLOCKSE
99
100
Interrupti on of MMC
Memory Access Traps by MMC Instruction _ _ 100
LRA
100
LMS
101
WAIT
103
RD
103
Read Direct, Internal Basic Processor
Control (Mode 0)
104
Read Direct, Interrupt Control (Mode 1} _ _ 105
Read Direct (Mode 9)
105
WD
1W
Write Direct, Internal Basic Processor
Control (Mode 0)
108
Write Direct, Interrupt Control (Mode 1} _ _ 109
Input/Output Instructions
110
Overall Characteristics
110
I/O Status Information
110
SIO
118
no
119
TDV
120
HIO
121
RIO
122
POLP
122
POLR
122
AIO
123

66
67
67
67
67
68
68
68
68
69
69
69
71
71
72
73
73
73
74
75
77

93
93
93
93
94
96
97

INPUT/OUTPUT OPERATIONS

125

External DIO Interface
Multiplexor Input/Output Processor (MIOP)_ _
Device Controllers
Input/Output Processor (lOP) Fundamentals _ _
Command List
Operational IOCD
1/0 Opera ti on Phases
Preparation Phase
Initiation Phase
Fetching Phase
Executi on Phase
Termination Phase

125
125
125
126
126
126
131
131
131
131
132
134

OPERATIONAL CONTROL

135

External Control Subsystem _ _ _ _ _ _ _ _
Centra Ii zed System Control
Controi Console Devices
Control Commands
Operator Control Commands
ZCI
ZcSSW
ZCSS#
ZCLDN###lf ___________

135
135
135
136
136
137
137
137
137

ZCRSY
ZCRBP
ZCRIO
ZCHLT
ZCRUN
Diagnostic Control Commands
pc

/
+
M
L
R
I
RUB OUT
S
G
X
Maintenance Control Commands
ZC CLK

J6'

ZcC##
ZCE##
ZCKIL
ZCMMO
Z CMM1
Z CMM2
Z CMM3
Z CMM4
Z CMM5
Z CMM6
Z CMM7
Z CMM8
Z CMM9
L~MMA

ZCLDS####
ZCLDT
ZCT
System Control Panel
Operating Procedures and Information

138
138
138
138
139
139
139
139
139
139
139
140
140
140
140
140
141
141
141
141
142
142
142
142
142
143
143
143
143
143
143
144
144
144
i44
144
144
144
144
147

Standard 7-Bit Communication Codes (ANSCII)_
Standard Symbol-Code Correspondences
Hexadecimal Arithmetic
Addition Table
Multiplication Table
Table of Powers of SixteenlO
Table of Powers of Ten16
Hexadecimal-Decimal Integer Conversion
Table
Hexadecimal-Decimal Fraction Conversion
Table
Table of Powers of Two
Mathematical Constants

169
173
173

GLOSSARY OF SYMBOLIC TERMS

174

FAULT STATUS REGISTERS

177

SYSTEM CONFIGURATION CONTROL

150

Configuration Control Panel (CCP)

150

A Xerox 550 Computer System

The Bas ic Processor

Information Boundaries

Main Memory

Addressing Logic

Index Displacement AI ignment (Real and
Vi rtua I Addressing Modes)

Generation of Actua I Addresses Indirect,
Virtual Addressing

Index Displacement Alignment (RealExtended Addressing)

Generation of Effective Virtual Address
(Indirect Real-Extended Addressing)

10. Operationa I States of an Interrupt Level

1l. Interrupt Priority Chain

12. Typical 28-Word Portion of Memory Stack
for PSS and PLS

APPENDIXES
A.

163

FIGURES

8.
6.

156
157
161
161
161
162
162

13. Formats of I/O Instructions

111

REFERENCE TABLES

155

14. Bootstrap Loader

138

Standard Symbo Is and Codes
Standard Character Sets
Control Codes
Special Code Properties
Standard 8-Bit Computer Codes (EBCDIC)

155
155
155
155
156

15. System Control Panel

145

16. Chassis Physical Configuration

151

17. Sample Rows of CCP Switches

151
v

15.

TABLES
1.

Device Status Byte (Register R or Ru1)
(510, no, and HIO only)

114

Basic Processor Operating Modes and
Addressing Cases

16.

Operational Status Byte (Register Ru 1)

115

Interrupt Locations

17.

Status Response Bits for I/O Instructions

116

Summary of Trap Locations

18.

lOP Status Byte

117

TCC Setting for Instruction Exception Trap X'4D~ 44

19.

Status Response Bits for AIO Instruction

118

Registers Changed at Time of a Trap Due to an
Operand Access

20.

I/O Address (AIO Response)

118

45
21.

Event Messages

136

ANALYZE Table for Operation Codes

56
22.

Diagnostic Control (P-Mode) Commands

140

Floating-Point Number Representation

75
23.

Condition Code Settings for Floating-Point
Instructions

Bit Assignments and Description, Processor
Control Word, Register Q30 (X'l E')

148

Bit Assignments, Address Compare Register
Q31 (X1'F')

149

Functions of Processor Cluster Configuration
Control Panel Row

152

Functions of Memory Unit Configuration
Control Panel Row

153

78
24.

Status Word 0

102

10.

Status Word 1

103

11.

Read Direct Mode 9 Status Word

105

12.

Chassis Type Assignments

106

13.

Description of I/o Instructions

111

C-1. Fault Status Registers

177

14.

I/o Status Information (Register R)

113

C-2. Memory Unit Status Register

178

25.

26.

1. XEROX 550 COMPUTER SYSTEM
GENERAL CHARACTERISTICS

INTRODUCTION
The Xerox 550 general-purpose, digital, computer system
accommodates a variety of scientific, business, real-time,
and time-sharing applications. A system includes system
control, basic processor, I/O processor, and main memory
(up to 256K words) with two ports. Each major system
element performs asynchronously wi th respect to other
elements.
The basic system can be readi Iy expanded. Memory access
paths can be increased from the basic two ports to a maximum of six ports. Input/output capabi Iity can be increased
by adding more input/output processors (lOPs), device controllers, and peripheral devices.

The following system features and characteristics permit
efficient operation in general-purpose, multiprocessor,
time-sharing, real-time, and multiuse environments:
•

Word-oriented memory (32-bit word plus parity bit
per byte) that can be addressed and altered as byte
(8-bit), halfword (2-byte), word (4-byte), and doubleword (8-byte) quantities.

•

Memory expandable to 256K words (K == 1024) in modular units of 16K words each.

•

Indirect addressing with or without postindexing.

•

Displacement index registers, automatically selfadjusting for all data sizes.

•

Immediate operand instructions for greater storage
efficiency and increased speed.

•

Four blocks of 16 general-purpose registers for addressing, indexing, and accumulating. Multiple registers
permit rapid context switching.

•

Hardware memory mapping, which virtually eliminates
memory fragmentation and provides dynamic program
relocation.

•

Memory access protection for system aOO informaTion
security and protection.

•

Memory write protection within memory units to prevent
inadvertent destruction of critical areas of memory from
any processor cluster.

•

Watchdog timer to assure nonstop operation.

•

Real-time priority interrupt system with automatic identification and priority assignment, fast response time,
and 14 internal and up to 48 external levels that can
be individually armed, enabled, and triggered by
program control.

•

Instructions with long execution times can be interrupted.

•

Automatic traps for error or fault conditions, with
masking capability and maximum recoverability, under
program control.

•

Power fail-safe for automatic shutdown and resumption
of processing in event of power fai lure.

•

Multiple interval timers with a choice of resolutions
for independent ti me bases.

•

Privileged instruction logic for program integrity in
multiuse environments.

The basic processor (BP) has an extensive instruction set
that includes floating-point instructions.
The multiaccess memory units, with interleaving, afford a
high level of system performance. Main memory can be
expanded in 16K word increments to a maxi mum of 256K
words. Address interleaving may be performed between
memory units of like size. The number of ports to each
memory unit can be expanded to allow independent access to memory by up to six "processor clusters" (i.e.,
functional groups).
Processor clusters are the grouping of two or more functions
{such as a basic processor, an I/O processor, and interfaces} on a common bus. Clustering permits processors to
share common faci Ii ti es, e. g., buses and memory i nterfaces. Therefore, the hardware is Iess redundant, hence
less complex, resulting in more reliabi lity at a lower cost.
There are multiple combinations of functional groups from
which to select.
Existing Sigma 5-9 programs may be run on the system.
The upward compati bi Ii ty of the comprehensi ve, modular software (assemblers, compilers, mathematical and
utility routines, and application packages) eliminates
reprogramming.
Features have been incorporated in this design to enhance
overall system reliability, maintainability, and availability.
Centralized switches for system repartitioning may permit
faulty units, or an entire subsystem, to be isolated for diagnosis or repair whi Ie the primary system continues operation.
Parity checking is performed on each byte of information
for most system interfaces and internal control signals. Most
failed instructions are automatically retried, and uninterrupted processing continues. The only apparent effect may
be an entry in the error log. In the event an error is irrecoverable, there are error storage registers that return complete data on the fault and the status of the system at
that point.

Xerox 550 Computer System

•

Extensive instruction set that includes:
•

Byte, halfword, word, and doubleword operations.

•

Use of all memory-referencing instructions for
register-to-register operations, with or without
indirect addressing and postindexing, and within
normal instruction format.

Address stop feature that permits operator or maintenance personnel to:
Stop on any instruction address.

Multiple register operations.

Stop on any memory reference address.

•

Fixed-point integer arithmetic operations in halfword, word,· and doubleword modes.

Stop when any word in a selected page of
memory is referenced.

•

Immediate operand instructions.

•

Floating-point hardware operations in short and
long formats with significance, zero, and normalization control and checking, all under full program control.

•

Full complement of logical operations (AND, OR,
exclusive OR).

•

Comparison operations, including compare between
limits (with limits in memory or in registers).

•

Call instructions that permit up to 64 dynamically
variable, user-defined instructions, and allow a
program access to operating system functions without operating system intervention.

•

Push-down stack operations (hardware implemented) of single or multiple words, with automatic limit checking, for dynamic space allocation, subroutine communication, and recursive
routi ne capabi Ii ty.

•

Traps that provide for detection of a variety of
fault conditions, designed to enable a high degree
of system recoverabi I i ty.

•

Partitioning features that enable system reconfiguration via a centralized Configuration Control Panel. Units may be partitioned from the
system by selectively disabling them from buses
(assuming other system facilities can handle the
additional load). Thus, faulty units, processors,
devices, or an alternate system can be isolated
from the operational system to enable diagnosis
or repair while the primary system continues
operation.

Independently operating I/o system with the following
features:

Automatic conversion operations, including binary/
BCD and any other weighted-number systems.

Direct input/output (READ DIRECT, W.UTE DIRECT
instructions) for transfer of 32-bit words between
the specified general register and an external device; a 16-bit address is transferred for selection
and control purposes; and each transfer is under
direct program control.

•

Up to five independent I/O processor clusters (restricted only by the maximum number of 6 ports).

Analyze instruction that facilitates effective
address computati on.

•

Multiplexor I/O processors (MIOPs) (up to 3 per
each providing for simuitaneous operation of up to 16 devices per processor.

•

Data chaining for gather-read and scatter-write
operati ons.

•

Command chaining for multiple record operations.

•

Write lock protect feature within memory unit
for positive protection from all processors storing
into memory.

Interpret instruction that increases speed of interpretive programs.

•

Shift operations (left and right) of word or doubleword, including logical, circular, arithmetic,
searching shift, and floating-point modes.

Built-in reliability and maintainability features that
include:

I/O ciuster),

Extensive error logging. When a fault is detected,
system status and fault information ale available

for program retrieval and logging for subsequent
analysis.
•

•

detection and location capability to permit the
operati ng system or diagnostic program to quickly
determine a faulty unit.

Full parity checking on all data and addresses
communicated in either direction on buses between memory units and processors, providing fault

General Characteristics

Comprehensive modular software that is program compatible with Sigma 5-9 computers:
•

Expands in capability and speed as system grows.

•

Operati ng system: Control Program Real-Time
(CP-R).

•

Language processors and utilities and applications
software for both commercial and sci entific users.

•

Peripheral equipment includes:
•

•

Card equipment: Reading speeds up to 1500 cards
per minute; punching speed of 100 cards per minute; intermixed binary and EBCDIC card codes.
Line printers: Fully buffered with speeds up to
1250 lines per minute; 132 print positions with
character sets containing 64 or 95 characters.
Magnetic tape units: 9-track systems, single or
dual density (1600 or 800/1600 BPI), industrycompatible; high-speed, automatic loading units
operating at 125 inches per second with transfer rates up to 200,000 bytes per second; and
at 75 inches per second wi th transfer rates up
to 120,000 bytes per second.
Rapid Access Data (RAD) and disk files: RAD
capacity of 2.9 million bytes, with a transfer
rate of 750,000 bytes per second; disk capacities in increments of 49 million bytes per unit
wi th a transfer rate of 312,500 bytes per second.

•

Keyboard printers: 10 characters per second.

•

Data communications equipment: Complete line
of character-oriented, message-oriented, and
procedure-oriented equipment to connect remote
user terminals (including remote batch) to the
computer center via common carrier lines and
local terminals directly.

•
•

A system control processor that inc ludes:

•

Real-time clocks (4)

•

Internal interrupts (14)

•
•
•
•
•

Power fail-safe detection
External Control Subsystem (ECS)
System Control Panel (SCP)
Configuration Control Panel (CCP)
Local and remote assist facility

Error detecti on fac iI i ti es
Diagnostics

A system may have the following optional features:
•

•

System Control Processor options:
•

Up to 48 external priori ty interrupts (in groups
of 12)

•

External Direct Input/Output interface (010)

Memory options:

•

Up to 4 additional access ports (in sets of 2).

STANDARD AND OPTIONAL FEATURES
A basic system has the following standard features:
•

•

A basic processor (BP) that includes:
•

Full instruction set

•

Memory map with access protection

•

Multiplexor Input/Output Processor (MIOP) with:
•

16 subchannels

•

1- or 4-byte interface

•

Input/Output Adapter

•

Input/Output opti ons:
•

t
Multiple I/O clusters •
•

Up to 3 additional MIOPs, each with 16 subc hanne Is, per cluster.

•

One Input/Output Adapter (for one MIOP)
per cluster.

GENERAL-PURPOSE FEATURES
General-purpose computing applications are characterized
by emphasis on computation and internal data handling.

Memory unit that includes:
•

Dua I port access

•

Memory write lock protection

tThe aggregate of processor clusters is restricted by the maximum memory port limitation of 6.

Standard and Optional Features/General-Purpose Features

Many operations are performed in floating-point format.
Other typical characteristics include high system input/
output transfer rates.

Interpret Instruction. The Interpret instruction simplifies
and speeds interpretive operations such as compilation, thus
reducing space and time requirements for compilers and
other interpretive systems.

General-purpose features are described in the following
paragraphs.

Floating-Point Hardware. Both short (32-bit) and long
(64-bit) formats are avai lable in the floating-point instructions. Under program control, the user may select
optional zero checking, normalization, floating-point
rounding and significance checking. Significance checking permits use of short floating-point format for high processing speed and storage economy and of long floatingpoint format when loss of significance is detected.

Indirect Addressing. Indirect addressing facilitates table
linkages and permits keeping data sections of a program
separate from procedure sections for ease of maintenance.

Displacement Indexing. Indexing by means of a IIfloating ll displacement permits accessing a desired unit of
data without considering its size. The index registers
automatically align themselves appropriately; thus, the
same index register may be used on arrays with different
data sizes. For example, in a matrix multiplication of
any array of full word, single-precision, fixed-point
numbers, the results may be stored in a second array as
double-precision numbers, using the same index quantity
for both arrays. If an index register contains the value
of k, then the user always accesses the kth element,
whether it is a byte, halfword, word, or doubleword.
Incrementing by various quantities according to data size
is not required; instead, incrementing is always by units
in a continuous array table regardless of the size of data
element used.

Instruction Set. The instructions permit short, highly
optimized programs to be written. These are rapidly
assembled and minimize both program space and execution time.

Conversion Instructions. Two generalized conversion instructions provide for bidirectional conversions between
internal binary and any other weighted number system,
including BCD.

Call Instructions. These four instructions permit handling
up to 64 user-defined subroutines, as if they were bui It-in
machine instructions. Call instructions also gain access to
specified operating system services without requiring its
intervention.

Time-Shari ng Features

Four-Bit Condition Code. Checking results is simpl ified by
automatically providing information on almost every instruction execution, including indicators for overflow, underflow, zero, minus, and plus, as appropriate, without
requiring an extra instruction execution.

Direct Input/Output (DIO). Direct input/output facilitates in-line program control of asynchronous or specialpurpose devices. This feature permits information to be
transmitted directly to or from general-purpose registers.

Multiplexor In ut/Output Processor (MIOP). Once initialized, I 0 processors operate independently of the
basic processor, freeing it to provide faster response to
system needs. An MIOP requires minimal interaction
with the basic processor. I/O command doublewords permit both command chaining and data chaining without
intervening basic processor cO:ltrol. I/o equipment speeds
range from slow rates involving human interaction (teletypewriter, for example) to transfer rates of rotating memory devices of over 750, 000 bytes per second. Peripheral controllers attached to an MIOP may be operated
simultaneously.

TIME-SHARING FEATURES
Time-sharing is the ability of a system to share its total
resources among many users at the same time. Each user
may be performing a different task, requiring a different
share of the available resources. Some users may be online in an interactive, IIconversationalli mode with the
basic processor whiie other users may be entering work to
be processed that requires only final output.

Time-sharing features are described in the following
paragraphs.

Rapid Context Saving. When changing from one user to
another, the operating environment can be switched quickly
and easi Iy. Stack-manipulating instructions permit storing
in a push-down stack of 1 to 16 general-purpose registers by
(1 single instruction,
Stack status is updated automat!ca!!y
and information in the stack can be retrieved when needed
(also, by a single instruction). The current program status
words, which contain the entire description of the current
user's environment and mode of operation, may be stored
anywhere in memory, and new program status words may be
loaded, all with a single instructi on.

Multiple Register Blocks. The availability of four blocks
of 16 general-purpose registers improves response time by
reducing the need to store and load register blocks. A
distinct block may be assigned for different functions as
needed; the program status words automatically select the
applicable register block.

To minimize the effect of transient errors, automatic retry
of failed instructions is performed.

User Protection. The slave mode feature restricts each user
to his own set of instructions while reserving to the operating system certain "privileged" (master mode) instructions
that could destroy another user's program if used incorrectly. Also, a memory access - protection feature prevents a user from accessi ng any storage areas other than
those assigned to him. It permits him to access certain areas
for reading only, such as those containing publ ic subroutines, whi Ie preventing him from reading, writing, or accessing instructions in areas set aside for other users.

Real-time applications are characterized by a need for:
(1) hardware that provides quick response to an external
environment; (2) speed that is sufficient to keep up with
the real-time process itself; (3) input/output flexibility to
handle a wide variety of data types at different speeds;
and (4) reliability features to minimize irreplaceable lost
time.

Storage Management. Main memory is expandable to 256K
(K = 1024) words. To make efficient use of available memory, the memory map hardware permits storing a user's program in fragments as sma II as a page of 512 words, wherever
space is available; yet all fragments appear as a single,
contiguously addressable block of storage at execution time.
The memory map also automatically handles dynamic program relocation so that the program appears to be stored in
a standard way at execution time, even though it may actually be stored in a different set of locations each time it
is brought into memory. The memory map provides the
ability to locate any 128K-word virtual program in the basic
processor's logical addressing space. Thus, the system can
always address a virtual memory of 128K words regardless
of physical memory size.

Input/Output Capability. Time-sharing input/output requirements are handled by the same general-purpose input/
output capabi lities described under" General-Purpose
Features".

Nonstop operation. A "watchdog" timer assures that the
system continues to operate even in case of halts or delays due to failure of special I/O devices. Multiple
real-time clocks with varying resolutions permit independent time bases for flexible allocation of time slices to
each user.

Reliability, Maintainability, Availability. Since timesharing systems have many on-line users needing immediate
system response, "downtime" defeats time sharing's primary
purpose. Pooling of resources along with flexible reconfiguration control ensures a high level of continuous avai 1abi lity. Configuration controls are provided to switch the
load from one unit to another in the event of a failure with
no loss of functional capabi lity, only capacity. In addition, a nonworking subset of the total system may be
logically isolated (partitioned) so that maintenance may
proceed on the subset whi Ie the remainder of the system
conti nues to operate.

REAL-TIME FEATURES

Multilevel, Priority Interrupt System. The real-timeoriented system provides rapid response to external interrupt
levels. Each interrupt is automatically identified and responded to according to its priority. For further flexibility,
each level can be individually disarmed (to discontinue input acceptance) and disabled (to defer responses). Use of
the disarm/disable feature makes programmed dynamic reassignment of priorities quick and easy, even while a realti me process is in progress.
Programs involving interrupts from specially designed equipment often require checkout before the equipment is actually
available. To permit simulating this special equipment, any
external interrupt level can be "triggered" by the basic
processor through execution of a single instruction. This
capability is also useful in establishing a modified hierarchy
cf !"esp~!"!ses. F~!" ex!:!!'!'!p!e, ;~ !"e5p0l"!d i l"!2 to (1 hi2h-pri(")rity
interrupt, after the urgent processing is completed, it may
be desirable to assign a lower priority to the remaining portion so that the interrupt routine is free to respond to other
critical stimuli. The interrupt routine can accomplish this
by triggering a lower-priority level, which processes the
remaining data only after other interrupts have been handled.
READ DIRECT and WRITE DIRECT instructions (described in
Chapter 3) allow the program to completely interrogate,
preserve, and alter the condition of the interrupt system at
any time and to restore that system at a later time.

Nonst
Operation. When connected to special devices
(on a ready resume basis), the basic processor may be excessively delayed if the specific device does not respond
quickly. As in the time-sharing environment, the built-in
watchdog timer assures that the basic processor cannot be
delayed for an excessive length of time.

Real-Time Clocks. Many real-time functions must be timed
to occur at specific instants. Other timing information isalso
needed - for example, elapsed time since a given event, or
the current time of day. The computer system can contain
up to four real-time clocks with varying degrees of resolution to meet these needs. These clocks also allow easy handling of separate time bases and relative time priorities.

Real-Time Features

Rapid Context Switching. When responding to a new set of
interrupt-initiated circumstances, a computer system must
preserve the current operating environment, for continuance
later, while setting up the new environment. This changing
of environments must be done quickly, with a minimum of
II overhead"
time costs. Anyone of the four blocks of
generar-purpose arithmetic registers can, if desired, be assigned to a specific environment. All relevant information
about the current environment (instruction address, current
general register block, memory-protection key, etc.) is
kept in the program status words. A single instruction
stores the current program status words anywhere in memory
and loads new ones from memory to establish a new environment, which includes information identifying a new
block of general-purpose registers. Thus, the system's
operating environment can be preserved and changed completely through the execution of a single instruction.

Priority Interrupt System. In a multiuse environment, many
elements operate simulatneously and asynchronously. Thus,
an efficient priority interrupt system is essential. It allows
the computer system to respond quickly, and in proper order, to the many demands made on it, with attendant improvements in resource efficiency.

Memory Protection. Both foreground (real-time) and background can run concurrently in the system because a foreground program is protected against destruction by an unchecked background program. Under operating system
control, the memory access-protection feature prevents
accessing memory for specified combinations of reading,
writing, and instruction acquisition.

Input/Output. Because of the wide range of capacities and
speeds, the I/O system simultaneously satisfies the needs of
many different appl ication areas economically, both in
terms of equipment and programming.

Variable Precision Arithmetic. Much of the data encountered in real-time systems are 16 bits or less. To process
this data efficiently, both halfword and fullword arithmetic
operations are provided. For extended precision, doubleword arithmetic operations are also included.
Direct Input/Output. For handling asynchronous I/O, a
32-bi t word can be transferred di rectly between any genera 1purpose register and external devices.
Reliability, Maintainability, Availability. The capabilities described in the section, .. Time-Sharing Features"
apply equally to the real-time environment.

Quick Response. The many features that combine to produce a quick-response system (multiple register blocks,
rapid context saving, multiple push-pull operations) benefit
a II users because more of the system's resources are readily
available at any instant.
Memory Protecti on. The memory protecti on features protect
each user from every other user and guarantee the integrity
of programs essential to critical real-time applications.

Instruction Set. The comprehensive instruction set provides
the computational and data-handling capabilities required
for widely differing application areas; therefore, each user's
program length and running time is minimized, and the
throughput is maximized.

MULTIPROCESSOR FEATURES
System design readi Iy permits expansion to shared memory
in a multiprocessor system. The system can contain a combination of functional clusters, each of which in turn may
contain multiple processors. The total number of clusters
is restricted to the maximum port limitation of six. All processors ina system may share common memory.
The following paragraphs describe the major multiprocessor
features of the system.

MULTIUSE FEATURES
MULTIPROCESSOR INTERLOCK
As implemented in this system, IImultiuse" combines two or
more application areas. The real-time application is the
most difficult general computing task because of its severe
requirements. Similarly, another difficult multiuse task is
a time-sharing application that includes one or more realtime processes. Because the system is designed on a realtime base, it is qualified for a mixture of applications in a
multiuse environment. Many hardware features that prove
valuable for certain application areas are equally useful in
others, although in different ways. This multiple capabi Iity makes the system particularly effective in multiuse applications.
The major multiuse features are described in the followi ng paragraphs.

Muitiuse Features/Multiprocessor Features

In a multiprocessor system, the basic processors often need
exclusive control of a system resource. This resource may
be a region of memory, a particular peripheral device, or,
in some cases, a specific software process. There isa special
instruction to provide this required multiprocessor interlock.
This special instruction, LOAD AND SET, unconditionally
sets a Ill" bit inthe sign position of the referenced memory
location during the restore cycle of the memory operation.
If this bit had been previously set by another processor, the
interlock is said to be "set" and the testing program proceeds to another task. On the other hand, if the sign bit
of the tested location is a zero, the resource is allocated
to the testing processor, and simultaneously the interlock
is set for any other processor.

MULTIPORT MEMORY SYSTEM
The system has growth capabi I i ty of up to 6 ports per
memory unit. A memory unit may contain 16K or 32K words.
This architecture allows flexibility in growth patterns
and provides high memory bandwidth, essential to multiprocessor systems.

and special purpose units such as analog to digital
converters.
2.

Central control of system partitioning.

Centralized interrupt system, providing capability for
the operating system to use interrupts to schedule tasks
independently of the number of basic processors present ina system.

Processor to processor communication via processor
buses.

MANUAL PARTITIONING CAPABILITY
Manual partitioning capability is afforded for all system
units. Thus, besides the primary advantage of increased
throughput, a secondary advantage of a multiprocessor
system is the "fail-soft" ability. Given a duplicate unit,
any unit can be partitioned by selectively disabling it from
the system buses. Depending on the type of failing unit,
the system will be operable, with some degree of degraded
performance. An alternate processor bus with dual system
capabilities can be provided.

MULTIPROCESSOR CONTROL FUNCTION
A multiprocessor control function is provided on all multiprocessor systems. This function provides these basic features:
1.

Control of the External Direct Input/Output bus (External 010), used for controlling system maintenance

SHARED INPUT/OUTPUT
In a multiprocessor system, any basic processor may direct
I/O actions to any I/O processor. Specifically, any basic
processor can issue an SIO, TIO, TOY, or HIO instruction to begin, test, or stop any I/O process. However,
the II end-action" sequence of the I/O process is directed
to one of the basi c processors in the system by the System
Control Processor. This feature (accomplished by setting
a pair of configuration control switches) allows dedicating
I/O end-action tasks to a single processor and avoids conflict resolution problems.

Multiprocessor Features

2. SYSTEM ORGANIZATION
The elements of this computer system include a basic
processor (BP), input/output processors (lOPs), memory, I/O
device controllers, and devices (see Figure 1). The processors and interfaces clustered into functional groups, interconnected via buses and controlled from a Configuration
Control Panel and a System Control Processor. Elements
within a processor cluster share an access path for intracluster communications. Thus, the total computer system can
be viewed functionally as a group of program-controlled
processor clusters communicating with each other and a
common memory. Each processor cluster operates asynchronously and semi-independently, automatically overlapping the operation of elements within as well as the
operation of other processor clusters for greater speed (when
circumstances permit).

PROCESSOR CLUSTERS
Processors (basic processor and MIOP, for example) are
grouped functionally along with a Memory Interface (MI)
and a Processor Interface (PI) into a processor cluster. Elements within a processor cluster share an access path (the
cluster bus) to the Memory Interface, which connects to the
memory system via a memory bus. The Memory Interface
resolves contention problems and controls use of the cluster
bus by the elements in the cluster.
A processor communicates with processors in other processor
clusters through the Processor Interface, which connects directly to a processor bus. Via the processor bus, any processor can communicate with or control any other processor
anywhere in the system configuration.
Note: Although two processor buses are provided, a Processor Interface can be connected to one or the
other of the processor buses, but not to both at the
same time.
Within a basic processor-MIOP processor cluster, the basic
processor primari Iy performs overa" control and data reduction tasks whereas the MIOP performs the task associated
with the exchange of digital information between main
memory and selected peripheral devices. The MIOP communicates with device controllers via the I/o bus, which
connects to the Controller Interface (CI).

SYSTEM CONTROL PROCESSOR
The System Control Processor performs these primary functions in the overall system:
1•

System control.

External Control Subsystem.

System Organization

Internal and external interrupt processing.

External and certain internal direct I/O (DIO) control.

It provides these major interfaces with other parts of the
system:

System console interface.

System control bus interface.

Processor bus interface.

Internal and external interrupt interfaces.

External and certain internal DIO interfaces.

System clock interface.

In addition to these major interfaces it provides paths for
other signals including system reset, 1.024 MHz clock,
power on/power off trap requests, and external real-time
clocks.
Figure 1 shows the interconnection of a System Control Processor to processor c Ius ters v ia a processor bus as we II as i nterconnection to the system console, external Direct Input/
Output (DIO), and external interrupts.

BASIC PROCESSOR
This section describes the organization and operation of the
basic processor in terms of instruction and data formats, information processing, and program control. The basic processor comprises a fast memory and an arithmetic and control
unit as functionally shown in Figure 2.
.hi9Je: Functionally associated with the basic processor but
physically located elsewhere are a memory map,
memory access protection codes, and memory write
protection codes. Memory control storage for the
memory map and access codes is located in the Memory Interface, and the memory control storage for
the write protection codes (write locks) is located
in the memory. These functions are described in
"Memory System", later in this chapter.

GENERAL REGISTERS
A fast (integrated circuit) memory consisting of ninety-six
32-bit registers is used wi th in the basic processor. A group
of 24 registers is referred to as a register block; thus, a
basic processor contains four register blocks. A 2-bit control field (called a register block pointer) in the program
status words (PSWs) selects the register block currently

Memory
Unit

Memory
Urut

System
Control
Console

I
I
I

System
Control
Processor

(Basic)

r---

Processor
Interface

____ I~

r-..L --,

I
I
I

rocessoq BUS 1fT

T]"

II:' ......

. . . . . . .-

MIOP

:
r ........

"I
.-J

I
I
MIOP

I
I

Ex terna I Interrupts
0
................ "- .... T ......... --.: .......... I
. , , " " . . . ..., . . . . . . . . . . . . . . . . . . _ .

LC~o~J

Processor
Interface

Basic
Processor

I
I

Memory
Interface

I
I

-,
I

Cluster (I/O)

I
I
I

I
I

r - ,..-..,

Pr"o~;----

L_[_J
I

Processor ,Bus #1

I
II

System
Control

r
I

Memory
Interface

System
Control
Processor

~~ss;;;:--------'

I Cluster

Memory
Unit

I ..... 1& ............
11:'
...... - . -

...... "'"

...J

DIO Bus

Device
Controller

Communications
. - - - - - 1 Interface

Line
Adapter

Comm.
Lines

Line
Adapter

Comm.
Lines

Device
Controller

Dual Access Option

Figure 1. A Xerox 550 Computer System

Basic Processor

FAST MEMORY

ARITHMETIC AND CONTROL UNIT

GENERAL REGISTER BLOCK (TYPICAL)

ol~

INSTRUCTION REGISTER

______________~

Indirect Access Flag

1 I.I:::::::.:::::}:=:::······ ':):::::fff::::rrttr::::t:ttt···:::::\::tt::tl

III II II I Operation Code Field
1

[]]]J

2 1:=: :": : : : : ': :::::::r:t:::::ttI:::::I:::t:::::::I:::.::I:}::::·::::::::t:':::I:I::i'::::::]

ITO

3 1'.::I::::::::::r:::::::=:,: .::::f:::Im:tt:::fIttt::\:t:II:t:::::::!::::'j':·::II!::::::!::1

4 II:::::.:::::--::::::::!:}f::: :tI:·:,:::::::!::=::::::·,!:::!:!:::':::'I:\::I::.:.:!!:.:. :.: : : .•:• !:.::::::.]

Index
Registers

General Register Designator

Index Register Designator

Reference Address Field

IIII1111111111111111

.......- -.....

•

Memory
I/O Processors I

•

Read/Write Direct

•

i:::.::::i:.:::·''):;:::::.::'::i:::::i:::::::::·::::::::::

•

::::?:ff.?::ftt:·::::::::::::f:::D::::ul.
PROGRAM STATUS WORDS

[[OJ
o

ITO

Floating-point Mode Control

o
o

~I________________~

Condition Code

Master/Slave Mode Control

~I________________~

13~1

Memory Map Control

________________~

Arithmetic Trap Masks

1011

14 '-'_ _ _ _ _ _ _ _ _~

Instruction

Id I III I II I I I II I I I I !ddress
15

_________. . .

'-I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

191~_______________. . .
20 ~I

_______________. . .

211~______________.....

Interrupt Inhibits

5859

Reserved

Mode Altered Control

Figure 2. The Basic Processor

Basic Processor

Write Key

[[IJ
37

17 I~

• Access Protecti on •

______________~
9~1______________~
10~1________________~
12

tv\apping

•

8~1

Interrupts

Extended
Displacement

avai lable to a program. The register block pointer can be
changed when the basic processor is in the master mode or
the master-protected mode. Only the first 16 general registers of a register block may be used by programs; the last
eight are reserved.
Each of the first 16 general registers in a register block is
identifi ed by a 4-bi t code in the range 0000 2 through 11112
{O through 15 in decimal notation, or X'O' through X'F' in
hexadecimal notation}. Any or" these 16 registers can be
used as a fixed-point temporary data storage location, or
to contain control information such as a data address, .count,
pointer, etc. General registers 1 through 7 can be used
as index registers.

When the memory map is not in effect, all virtual address
values above 1510 are used by the memory as actual addresses. Virtual addresses 0 through 15 are alwayst used by
the basic processor as general register addresses rather than
as memory addresses. For example, if an instruction uses
virtual address 5 to address the location where a result is
to be stored, the basic processor stores that result in general register 5 in the current register block instead of in
memory location 5.
When the basic processor is operating with the memory map
in effect, virtual addresses 0 through 15 are still used as
general register addresses. Virtual addresses above 15 are
transformed into actual addresses by replacing the highorder portion of the virtual address with a value obtained
from the memory map. (The memory map address replacement process is described in "Memory Address Control ",
later in this chapter.)

MEMORY CONTROL STORAGE
The memory control storage for the memory map and the
associated memory access protection codes are contained
in the Memory Interface (MI). Memory control storage for
the 4-bit write locks are contained in the memory units.
Memory control storage can be modified when the basic
processor is in the master mode or the master-protected
mode.

MEMORY MAP
Two terms are essential in understanding the memory mapping concept: actual (i. e., absolute or real) address and
'!h·t~d 0dd!"ess.
An actual address is used within the memory unit (memory
address registers) to access a specific, physical memory location for storage or retrieval of information as required by
the execution sequence of an instruction. Actual addresses
are fixed and are dependent on the wired-in hardware.
A virtual address refers to a logical location as required by
an individual program. Like an actual address, a virtual
address may designate a location that contains a program
instruction, an element of data, a data address (indirect
address), or it may also be an explicit quantity. Normally,
virtual addresses are derived from programmer-supplied
labels through an assembly (or compi lation) process followed
by a loading process. Virtual addresses m~y also be computed during a program's execution. Virtual addresses include all instruction addresses, indirect addresses, and
addresses used as counts within a stored program, as well as
those instructions computed by the program. (See "Virtual
and Real Memory", later in this chapter.)
Memory mapping transforms virtual addresses as seen by the
individual program into actual addresses as seen by the
memory system. Thus, when the memory map is in effect,
any program can be broken into 512-word pages and dynamically relocated throughout memory in whatever pages
of space are avai lable.

MEMORY ACCESS PROTECTION
When the basic processor is operating with the memory map
in the slave mode or the master-protected mode, the access
protection codes determine whether the program may access
instructions from, read from, or write into specific regions
of the virtual address continuum (virtual memory). If the
slave mode or master-protected f}1ode program attempts to
access a protected region of virtua I memory, a trap occurs
(see "Memory Address Control ", "Virtual and Real Memory", and "Trap System", later in this chapter).

MEMORY WRITE PROTECTION
The memory write-protection feature operates independently
of access protection and the memory map. The 4-bit write
lock operates in conjunction with a 4-bit field, called the
write key, in bits 32-35 of the Program Status Words (PSWs).
The lock and the key de term i ne whether any program may
alter any word of main memory. The write key can be
changed when the basic processor is in the master mode or
the master-protected mode. (The functions of the write
lock and key are described in "Memory Address Control ",
later in this chapter.)

COMPUTER MODES
The basic processor operates in one of three modes: master,
master-protected, or slave. The operation mode is determined by the setting of three bits (bits 8, 9, and 61) of the
Program Status Words (PSWs). (See "Program Status Words",
later in this chapter.) Additionally, the basic processor
operates in a mapped mode or an unmapped mode.

Except for the READ DIRECT (RD)/WRITE DIRECT 0/VD) instructions which can read from and store into these locations.
Basi c Processor

MASTER MODE
The master/slave control bit (bit 8 of the PSWs) must contain a zero for the basic processor to operate in master
mode. In this mode the basic processor can perform all of
its control functions and can modify any part of the system.
The restrictions upon the basic processor1s operations in this
mode are those imposed by the write locks on certain protected parts of memory. It is assumed that there is a resident operating system (operating in the master mode) that
con tro Is and supports the opera ti on of other programs (wh i ch
may be in the master, master-protected, or slave mode).

high-order bits contain zeros. The memory map always maps
17-bit virtual addresses into 20-bit real addresses (see
"Memory Address Control ", later in this chapter for a discussion of how the map is used).
UNMAPPED MODE
When the basic processor is operating in the unmapped mode,
there is a direct one-to-one relationship between the effective virtual address of each instruction and the actual address used to access main memory. (See "Real Addressing",
later in this chapter.)

MASTER-PROTECTED MODE

INFORMATION FORMAT
The master-protected mode of operation provides additional
protection for programs that operate in the master mode. The
master-protected mode occurs when the basic processor is
operating in the master mode with the memory map in effect
and the mode altered control bit (bit 61 of the PSWs)is on.
In this mode the memory protection violation trap occurs
(location X 140 1, with CC4 = 1), as it does in all mapped
slave programs, if a program makes a reference to a virtual
page to which access is prohibited by the current setti ng of
the access protection codes.

Nomenclature associated with digital information within the
computer system is based on functional and/or physical attributes. A "word" may be either a 32-bit instruction word
or a 32-bit data word.
The bit positions of a word are numbered from 0 through 31
as follows:

SLAVE MODE
The slave mode of operation is the problem-solving mode
of the basic processor. In this mode, access protection
codes apply to the slave mode program if mapping is in effect, and all "privi leged" operations are prohibited. Privileged operations are those relating to input/output and to
changes in the fundamental control state of the basic processor. All privi leged operations are performed in the
master or master-protected mode by a group of privileged
instructions. Any attempt by a program to execute a privi leged instruction whi Ie the basic processor is in the slave
mode results in a trap. The master/sla·:e mode control bit
(bit 8 of the PSWs) can be changed when the basic processor
is in the master or master-protected mode. Nevertheless,
a slave mode program can gain direct access to certain executive program operations by means of CAll instructions.
The operations available through CAll instructions are established by the resident operating system.

A word can be divided into two 16-bit parts (halfwords) in
which the bit positions are numbered from 0 through 15 as
follows:

A word can also be divided into four 8-bit parts (bytes) in
which the bit positions are numbered 0 through 7 as follows:

Two words can be combined to form a 64-bit element (a
doubleword) in which the bit positions are numbered 0
through 63 as follows:

MAPPED MODE
Although the memory map is located in the Memory Interface (MI), it functions as part of the basic processor. The
basic processor communicates with memory through the MI.
Mapping is effective for all the words of real memory, and
is invoked when bit 9 (MM) of the PSWs contains a one.
Memory mopping generates rea! page addresses from v:rtuc!
addresses. The memory map can be loaded with either
11-bit real page addresses or 8-bit real page addresses by
means of the MOVE MEMORY CONTROL (MMC) privi leged
instruction (see Chapter 3, "Control Instructions "). Elevenbit rea I page addresses are always provided for in the map,
thus if 8-bit real page addresses are generated, the three

Basic Processor

In fixed-point binary arithmetic each element of information
represents numerical data as a signed integer (bil 0 represents the sign, remaining bits represent the magnitude, and
the binary point is assumed to be just to the right of the
least significant or rightmost bit). Negative values are
represented in two1s complement form. Other formats required for floating-point and decimal instructions are described in Chapter 3.

INFORMATION BOUNDARIES

A halfword is located in bit positions 0 through 15 and
16 through 31 of a word.

Basic processor instructions assume that bytes, halfwords,
and doublewords are located in main memory according to
the following boundary conventions:

A doubleword is located such that bit positions 0 through
31 are contained within an even-numbered word, and
bit positions 32 through 63 are contained within the
next consecutive word (which is odd-numbered).

A byte is located in bit positions 0 through 7, 8
through 15, 16 through 23, and 24 through 31 of a
word.

Figure 3 illustrates these boundaries.

Doubleword

Doubleword
Word (even address)
Halfword 0

Halfword 1

Word (odd address)
Halfword 0

Halfword 1

Word (even address)
Halfword 0

Halfword 1

Word (odd address)
Halfword 0

Halfword 1

Byte 0 IByte 1 Byte 21Byte 3 Byte 0 Byte 1 Byte 21Byte 3 Byte 0 IByte 1 Byte 21Byte 3 Byte 0IByte 1 Byte 21 Byte 3

Figure 3. Information Boundaries

INSTRUCTION REGISTER

processor is currently executing. The format and fields of
the two general types of instructions (memory reference and
immediate operand) are described below. Specific formats
for each instruction are given in Chapter 3.

Bits

Descri pti on

8-11

current register block as an operand source, result
destination, or both.

(cont. )

12-14

X field. This 3-bit field designates one of general
registers 1-7 of the current register block as an
index register. If X contains zero, indexing wi II
not be performed; hence register 0 cannot be used
as an index register. (See "Address Modification
Example: Indexing (Real and Virtual Addressing)",
later in this chapter for a description of the
i ndexi ng process. )

15-31

Reference address. This 17-bit field normally contains the reference address of the instruction operand. The reference address is translated into an
effective virtual address in accordance with the
addressing type (real, real extended, or virtua I)
and the address modification requied (direct/
indirect or indexing). (See "Memory Reference
Addresses" later in this chapter. )

MEMORY REFERENCE INSTRUCTIONS
Instructions that make reference to an operand in main memory may have the following format:

Bits

Description

Indirect addressing. One level of indirect addressing is performed only if this bit position contains a one.

1-7

Operation code. This 7-bit field contains the code
that designates the operation to be performed. See
the inside front and back covers for complete listings of operation codes.

IMMEDIATE OPERAND INSTRUCTIONS

R field. For most instructions this 4-bit field designates one of the first 16 general registers of the

Immediate operand type instructions are particularly efficient because the required operand is contained within the

8-11

Bas i c Processor

instruction word. Hence, memory reference, indirect
addressing, and indexing are not required.

The following sections describe the organization and operation of the memory system. Also described are the various
modes and types of addressing, including indexing.

Bits

Description

Bit position 0 must be coded with a zero. If it
contains a one, the instruction is interpreted as
being nonexistent. (See "Trap System", later in
this chapter.)

1-7

possible clock and power sources. Memory units may contain two, four, or six ports, which have a fixed priority
order for the resolution of contention problems.

Operation code. This 7-bit field contains the code
that designates the operation to be performed.
When the basi c processor encounters any i mmediate operand operation, it interprets bits 12-31 of
the instruction word as an operand. These are the
immediate operand operation codes:
Operation
Code

Instruction
Name

X'02'

Load Conditions
and Floating Control Immediate

LCFI

X'20'

Add Immediate

X'21'

Compare Immediate

X'22'

Load Immediate

X'23'

Multiply Immediate

Mnemonic

MEMORY UNIT
Main memory is divided physically and logically into one
to eight module assemblies called memory units. Because
the memory unit is a logical component that contains all the
functions available in the entire memory, the minimum memory is one memory unit. The minimum storage capacity per
memory unit is 16K words; the maximum is 32K words. A
memory location stores a word of 36 bits; the first 32 bits are
information and the last 4 are byte parity bits (the latter
being unavailable to the program). Each memory unit comprises a specific storage capacity, drive and sense circuits,
a set of operational registers (address, data, and status), a
set of write lock control registers for 32K words of memory,
and a timing and control unit.
CORE MEMORY MODULES
Core memory modules (CMMs) provide a storage faci lity of
standard modules (see Figure 4).
MEM ORY DRIVER

8-11

12-31

R field. This 4-bit field designates one of the
first 16 general registers in the current general
register block. The register may contain another
operand and/or be designated as the register in
which the results of the operation are to be
stored or accumulated.
Operand. This 20-bit field contains the immediate operand. Negative numbers are represented
in two's complement form. For arithmetic operations bit 12 (the sign bit) is extended by duplication to the left through bit position 0 to form a
32-bit operand.

The memory driver in each memory unit performs all memory
operations except storage (provided for by the CMMs) and
the few operations performed by the ports. The major functions of the memory driver are:
1•

Store address word.

Store data-in and data-out words during memory
cycles.

Store write locks in special memory (other than CMMs).

Perform parity generation and checking on address and
memory bus data words, and on core memory module
words.

Generate and store status words.

Control and time all transfers of address words, data
words, status words, write locks, and write key among
the ports, CMM, and the storage registers.

Centre! end time o!! date, pcr:f';1 and control signals

MAIN MEMORY
The memory system comprises memory units, memory interfaces (MIs), and memory buses. Figure 4 illustrates the relationships among these components.
The primary technology for main memory is magnetic core.
The maximum physical storage is 256Kwords. Memory units
can be interleaved on a two-way interleave basis. Each
memory unit is provided with a set of starting address
switches on the Configuration Control Panel (see Chapter 6)
together witha two-position switch that selects one of two

Main Memory

issued to the memory bus.
8.

Accept one of two or more simultaneous memory requests on the basis of port positional priority and other
priority status information such as "high priority" and
"memory reserved ".

(Maximum
of eight)
Core
Memory
Modules
(CMM)
Memory
Unit

Core
Memory
Modules
(CMM)
Memory
Unit

Memory
Driver
(MD)

Core
Memory
Modules
(CMM)
Memory
Unit

Memory
Driver
(MD)

P P P P P P

1 2 3 4 5 6

Memory Bus 1

Memory Bus 2

,---i---llI

--,

r--

Memory
Interface

Basic
Processor

I
I

•

....en
u

en
::l

L-

::l

t---

MIOP

..--

Memory
Interface

I
I
I

r--

I
I
Processor
Cluster

L-

....ena>

::l

U
I--

MIOP

I
'---

Processor
Interface

Processor
Cluster

r
Processor
Interface

I
I
I

L ______ --.J

To Processor Bus(es)

Figure 4. Main Memory

Main Memory

PORTS AND MEMORY BUSES
A memory unit may contain two, four, or six ports, which
have a fixed priority order for the resolution of access contention. Each port allows the memory unit to communicate
via a memory bus with a different external system (i.e., a
processor cluster), which communicates with the memory bus via the Memory Interface (MI) (see Figure 4). Ports
are numbered from 1 (top priority) to 6 (lowest priority).
The selection logic is biased to select port 1 (the fast port)
whenever the memory is quiescent. Thus performance is
improved for the Memory Interface (MI) connected to that
port, and hence to the processors connected to that MI.
A memory reserve function insures proper execution of instructions that require guaranteed re-access to a memory
locati on before a second processor can access it.
Each port is equipped with an inhibit function that can
be activated from the Configuration Control Panel (see
Chapter 6).

access to a given memory location without encountering
interference from another processor that is making sequentia I requests.
Two memory units of the same size can be two-way interleaved. Both memory units transform an incoming address,
as follows:
Size of Each
Memory Unit

Address Bits
Interchanged

32K
16K

16 and 31
17 and 31

As a result of the address transformation, even incoming addresses are assigned to one memory unit and odd incoming
addresses to the other. Note that the incoming address (untransformed) is stored in the status register of the accessed
unit in each cycle and is avai lable as are other types of dynamic status information. (Interleaved memory units have
two status registers, one in each of the un its.)

Other major functions performed by the ports are:
MEMORY UNIT STARTING ADDRESS
1.

Address recognition.

Address interleaving.

The memory system is bui It up by interconnection of identically numbered ports of all memory units. Each interconnecting cable is called a memory bus, wh ich is dedicated
to a single processor cluster (see Figure 4).

PORT PRIORITY
The multiport structure allows two simul taneous requests for
memory to be processed immediately if the requests are
received on different ports for different memory units, and
neither memory unit is busy. If a requested memory unit
is busy or receives simultaneous requests, the memory port
logic selects the highest priority request first.
Normally, all ports in a memory unit operate on the fixed
priority basis (the fast port has the highest priority and the
highest-numbered normal port the lowest). Thus, if a single
memory unit simultaneously receives requests on port 2 and
port 4, port 2 has first access to the memory unit.
Each port also has associated with it a high-priority line
which, upon receiving a high-priority request, raises the
port's priority above that of all other ports except for any
higher priority port, which also has a high-priority request
on its line.

Each memory unit is individually identified by starting address switches located on the Configuration Control Panel
(see Chapter 6). These switches define the range of addresses the memory unit responds to when servicing memory
requests. All addresses, including the starting address, for
a given memory unit are the same for all ports in that unit;
that is, the address of a given word remains the same regard less of the port used to access the word. The starti ng
address of a memory unit must be on a boundary equal to a
multiple of the size of the memory unit when two memory
units (of the same size) are interleaved. The starting address of one memory unit must be a multiple of the size of
the two memory units together; the second memory unit must
have a starting address higher than that of its companion by
its own size. Another way to say this is that the starting
address for the combined units must be on a boundary equal
to a multiple of the total size of the interleaved assembly.

MAINTAINABILITY AND PERFORMANCE
Memory maintainability is enhanced by the following
features:
1.

Error detection. Each memory unit senses and remembers parity errors in the CMM data as well as parity
errors in the address word or the memory bus data, port
selection errors, CMM selection error, and undefined
operations. This status information is available to diagnostic programs to facilitate error localization in
space and time of occurrence. The memor; unit senses
and reports, but does not remember (for diagnostic purposes) a write lock violation.

Modularity. For ease of replacement, the logic and storage circuitry is packaged on modules that are removable
from backpanelswithoutrequiring cable disconnections.

MEMORY INTERLEAVING
Memory interleaving is a hardware feature that distributes
sequential addresses into two independently operating memory units. Interleaving increases the probability that
a processor (i.e., basic processor or MIOP) can gain

Main Memory

Diagnostic logic. Each memory driver module carries
logic used exclusively for localizing faulty elements
in that module. The benefit derived from this diagnostic logic depends on such external factors as the accessibility to a module tester.

first 16 registers of the current register block as if it were
a location in main memory. Furthermore, the register block
can hold an instruction (or a series of as many as 16 instructions) for execution just as though the instruction (or instructi ons) were in ma in memory.
The following terms are used in the various types of addressing described in subsequent sections. See also Figure 5,
wh ich illustrates the control and data flow during address
generation.

Memory system performance depends on these factors;
1.

Access time of memory unit.

Cycle time of memory unit.

Type of cycle requested.

Number of memory units.

Interleaving.

Type of port (fast or norma I) selected.

Self or mutual interference between memory requests.

1•

Instructi on Address. Th is is the address of the next
instruction to be executed. For real, real-extended,
and virtual addressing the 17-bit instruction address is
contained within bits 15-31 of the program status words
(PSWs) •

Reference Address. This is the 17-bit or 20-bit address
associated with any instruction (except that in a trap
or interrupt location that has a 0 in bit position 10).
For real, real extended, direct, and virtual addressing,
the reference address is the address contained within
bits 15-31 of the instruction itself.

All these factors characterize not only memory performance
but a Iso system performance.

The reference address may be modified by using indirect
addressing, indexing, and memory mapping. A reference address becomes an effective virtual address after
the indirect addressing and/or postindexing (if required) is performed.

Port access time and cycle time are essential memory speed
characteristics pertaining to CMM operations.
1.

Port access time. This is the time interval measured
between the clock pulse that transmits an address word
from the Memory Interface (MI) to an idle memory unit
and the clock pulse that translates a memory word from
the same memory unit to the MI.
-

I..

,...

I._

1.1

20-Bit Trap or Interrupt Reference Address. If bit position 10 of any instruction in a trap or interrupt location
contains a 0, bits 12-31 of that instruction are used as
a 20-bit reference address. This 20-bit reference addi-c55 Cuii be ,li0difie:d vii~,- by \,;:;;ii9 ;iid;~~ct Gddr~~:;
ing. This 20-bit reference address cannot be indexed
or mapped. (See IIInterrupt and Trap Entry Addressing",
later in this chapter.)

Direct Reference Address. If neither indirect addressing nor indexing is called for by the instruction (i.e.,
if bit 0 and the X field contain zero), the reference
address of the instruction (as defined above) becomes
the effective virtual address. Direct addressing may
be used during real, virtual, or real extended addressing modes, including trap and interrupt operations. Direct addressing during virtual addressing does not preclude memory mapping.

Indirect Reference Address. The 7-bit operation code
field of the instruction word format provides for as many
as 128 instruction operation codes, nearly all of which
can use indirect addressing (except immediate-operand
and byte-string instructions). If the instruction calls
for indirect addressing (bit position 0 contains a 1), the
reference address (as defined above) is used to access a
word location that contains the direct reference address
in bit positions 15-31, or bit positions 12-31 for certain
real extended addressing operations. The indirect addressing operation is limited to one level, regardless of
the contents of the word location pointed to by the reference address field of the instruction. Indirect addressing occurs before indexing; that is, the 17-bit

'-ycte TIme. '-ycte TIme aepenas on rne ope'Uliun [}~ing performed and on the sequence of operation. Cycle
time determines the maximum rate at which a memory
un it can accept requests.

VIRTUAL AND REAL MEMORY
Virtual memory is the address space available to an individual program. The maximum size of virtual memory is
128K words, broken into as many as 256 pages of 512 words
each distributed throughout the available pages of real
memory.
Real memory corresponds to the physical memory, and its size
is equal to the total number of words contained within all
memory units in the system. The size of real memory ranges
from a minimum of 16K words to a maximum of 256K words.
Note: Real memory address space is 1 million words.

MEMORY REFERENCE ADDRESS
Memory locations 0 through 15 are not normally accessible
to the programmer because their memory addresses are reserved as register designators for "register-te-register ll operations. Nevertheless an instruction treats any of the

Main Memory

Fetch contents of register.

yes

Add 16-19 bit index to
17-bit reference address;
17-19 bit arithmetic.

Add 20-22 bit index to
17-bit direct reference
address or 20-bit indirect
reference address; 20-22
bit arithmetic.

Fetch contents of register.

Fetch contents of 20-bit
rea I address. If wr ite
operation, trap on writeprotect violation.

0~
(

END

)
Figure 5. Addressing Logic

Main Memory

,V,op to 20-bit real address. Trap on access
protect violation if in
slave or master-protected
modes.

reference address field of the instruction is used to
obtain a word, and the 17 or 20 low-order bits of the
word thus obtained effectively replace the initial reference address field; then indexing is carried out according to the operation code of the instruction. See
Figures 7 and 9, later in this chapter.
6.

Index Reference Address. If indexing is called for in
the instruction (a value other than zero in bits 12-14
of the instruction), the direct or indirect reference address is modified by addition of the displacement value
in the general register (index) called for by the instruction (after scaling the displacement according to the
instruction type). This final reference address value
(after indirect addressing, indexing, or both) is defined
as the effective virtual address of the instruction. Indexing after indirect addressing is ,ca lied postindexing.
See also Figures 7 and 9, later in this chapter.

11. Effective Location. An effective location is defined
as the actual location (in main memory or in the current
register block) that is to receive the result of a memoryreferencing instruction, and is referenced by means of
an effective address. Because an effective address
may be either an actual address or a virtual address,
when applicable, this definition of an effective location assumes the transformation of a virtual address into
an actua I address.
12. Effective Operand. An effective operand is defined
as the contents of an actual location (in main memory
or in the current register block) that is to be used as
an operand by a memory-referencing instruction, and
is referred to by means of an effective address. This
also presupposes the transformation of a virtual address
into an actual address.

Displacements. Displacements are the 16- to 22-bit
values used in index registers and by byte-string instructions to generate effective addresses of the appropriate size (byte, halfword, word, .or doubleword).
Register Address. If any instruction provides a virtual
address that is a memory reference (i.e., a direct,
indirect, or indexed reference address) in the range 0
through 15, the basic processordoesnotattempt to read
from or write into main memory locations 0 through 15.
Instead, the four low-order bits of the reference address are used as a general register address and the general register corresponding to this address is used as the
operand location or result destination. Thus, the instruction can use any of the first 16 registers in the current register block as the source of an operand, the
location of a direct address, or the destination of a resuit. Such usage is called a "register-to-register"
operation.
Actual Address. This is the address value actually used
by the basic processor to access main memory via the
memory address register (see Figure 5). If the effective
virtual address is in the range 0 through 15 (X'O through
X'F'), one of the first 16 general registers in the current register block is being addressed. If the basic processor is operating in the virtual addressing mode, all
addresses greater than 15 (X'F') are transformed (usually
into addresses in a different memory page) by the memory map into actual addresses. Contrarily, if the basic
processor is operating in either real or oreal extended
mode, no transformation via the memory map takes place.

10. Effective Address. The effective address is defined as
the final virtual address computed for an instruction.
Note, however, that some instructions do not use the
effective address as a location reference; instead, the
effective address is used to control the operation of
the instruction (as in a shift instruction), to designate
the address of an input/output device (as in an input/
output instruction), or to designate a specific element
of the system (as in a READ DIRECT or WRITE DIRECT
instruction) •

TYPES OF ADDRESSING
Except for the special type of addressing performed by some
interrupt and trap instructions, all addressing within the
computer system is real, real extended, or virtual.

REAL ADDRESSING
In real addressing, a one-to-one relationship prevai Is between the effective virtual address of each instruction
and the actual address used to access main memory. Real
addressing has these characteristics:
1.

Each reference address is a 17-bit word address.

The reference address may be direct or indirect, with
or without postindexing.

Displacements associated with indexing are automatically aligned, as required, using the full 32-bit contents
of the index register. The final result is truncated to
the left of the high-order bit of the original 17-bit reference address, and the effective real address is a
16-bit doubleword address, 17-bit word address, la-bit
ha Ifword address, or a 19-b it byte address.

If indirect addressing is invoked, the 17-bit reference
address in the instruction word is used to access the indirect address word in memory. ThQ low-order 17 bits
of this word then replace the reference address of the
instruction word in the calculations described in (3),
above.

Memory mapping and memory access protection are
never invoked.

Memory write protection is automatically invoked.

Leading zeros are automatically appended to the effective address to generate an actual word address as required by the main memory.

Main Memory

Real addressing is allowed in master mode and in slave
mode, and is specified when bit positions 9 and 61 of
the PSWs both contain zero.

VIRTUAL ADDRESSING
Virtua I addressing uses the memory map to determine the
actual address to be associated with a particular reference
address of each instruction. Virtual addressing differs from
real addressing in that there is normally no exact relationship between the effective virtual address and the actual
address. These are the characteristics of virtual addressing:
1.

Each reference address is a 17-bit address.

The reference address may be direct or indirect, with
or without postindexing.

Displacements associated with indexing are automatically aligned, as required, using the full 32-bit
contents of the index register. The final result is
truncated to the left of the high-order bit of the
original 17-bit reference address, and the effective
virtual address is a 16-bit doubleword address, 17-bit
word address, 18-bit halfword address, or a 19-bit byte
address.

Virtua I memory access protection is always invoked.
If the access protection code is invalid, the instruction
aborts and traps to location X 140 1• (See "Trap System",
later in this chapter.)

Memory mapping translates the 8 most significant bits
of the effective virtual address (the page portion) into
an l1-b i t page address. Th is page address is concatenated with the 9 least significant bits of the reference
address. The resultant 20-bit word address is the actual
address used to access memory. This feature permits
anyone user at any given time to have a virtual memory of as many as 128K words (256 pages) located
throughout real (actual) memory comprising as many
as 256K words (512 pages). Although virtual memory
may be physically fragmented, it is logically contiguous.
Note that Sigma 6/1 programs may run on this computer
system without requiring change to the mapping structure. The memory map is loaded with 8-bit page addresses (the 3 high-order bits of the ll-bit real page
address are reset to zeros). The most significant 8 bits
of the effective virtual address are then translated into
the designated 8-bit page address.

The rnemory write-protection featl.!re !5 !n'loked for the
actual address in real memory.

Virtual addressing may be used in all modes (master,
master-protected, and slave) and is specified when
bit 9 of the PSWs contains a one.

Main Memory

ADDRESS MODIFICATION EXAMPLE: INDEXING
(REAL AND VIRTUAL ADDRESSING)
Figure 6 shows how the indexing operation takes place during real and virtual addressing operations. The instruction
is brought from memory and loaded into a 34-bit instruction
register that initially contains zeros in the two low-order
bit positions (32 and 33). The displacement value from the
index register is then aligned with the instruction register
(as an integer) according to the address type of the instruction; that is, if it is a byte operation, the low-order bit of
the displacement is aligned with the least significant bit of
the 34-bit instruction register (bit position 34). The displacement is then shifted one bit to the left of this position
for a halfword operation, two bits to the left for a word
operation, and three bits to the left for a doubleword operation. An addition process then takes place to develop a
19-bit address, referred to as the effective address of the
instruction. High-order bits of the 32-bit displacement are
ignored in the devdopment of this effective address (i .e.,
the 15 high-order bits are ignored for word operations, the
25 high-order bits are ignored for shift operations, and the
16 high-order bits are ignored for doubleword operations).
The displacement value, however, can cause the effective
address to be less than the initial reference address (within
the instruction) if the displacement value contains a sufficient number of high-order lis (i .e., if the displacement
value is a negative integer in two1s complement form).

The effective virtual address of an instruction is always a
19-bit byte address value. This value, however, is automatically adjusted to the information boundary conventions.
Thus, for halfword operations the low-order bit of the effective halfword address is zero; for word operations the two
low-order bits of the effective word address are zeros; and
for doubleword operations the three low-order bits of the
effective doubleword address are zeros.

In a byte operation with no indexing, the effective byte
is the first byte (byte 0 in bit positions 0-7) of a word location; in a halfword operation with no indexing, the effective halfword is the first halfword (halfword 0 in bit
positions 0-15) of a word location. A doubleword operation always involves a word at an even numbered address
and the word at the next sequential (which is odd numbered)
word address. Thus, if an odd numbered word location
is specified for a doubleword operation, the low-order bit of
the effective address field (bit position 31) is automatically
forced to zero. This means that in a doubleword operation
an odd numbered word (reference) address designates the
same doubleword as the next lower even numbered word
address.

In the real addressing mode, the 19-bit effective virtual
address is concatenated with 3 leading zeros to form a
22-b it actua I address. In the virtua I addressi ng mode,
the 8 most significant bits of the 19-bit virtual address
are mapped (using the memory map) into the 11-bit actual
page address, thus forming a 22-bit actual address.

Instruction in memory:

Instruction in instruction register:

I IIII
Byte operation indexing alignment:

Halfword operation indexing alignment:

Word operation indexing alignment:

Shift operation indexing alignment:

Doubleword operation indexing alignment:

Effective virtual address:

Figure 6. Index Displacement AI ignment (Real and Virtual Addressing Modes)

ADDRESS MODIFICATION EXAMPLE: INDIRECT,
INDEXED HALFWORD (VIRTUAL ADDRESSING)
Figure 7 i "ustrates the address modification and mapping
process for an indirectly addressed, indexed, halfword operation. As shown, reference address 1 is the content of
the reference address field in the instruction stored in memory. The instruction is brought into the instruction register,
and if the value of the reference address field is greater
than 15, the memory map converts the 19-bit effective virtual address into a 22-bit actual address. The 17 low-order
bits of the main memory location pointed to by the actual
address, labeled reference address 2, then replaces reference address 1 in the instruction register. The index register
designated by the X field of the instruction is subsequently
aligned for incrementing at the halfword-address level. The
final effective virtual address is formed by the address generator, and if the value of the reference address is greater
than 15, the effective virtual address is transformed through
the memory map into an actual address. The resultant 22-bit
actual (main memory) address, which automatically contains
a low-order 0, is then used to access the halfword to be
used as the operand for the instruction.

Note that for the real addressing mode, the modifications
required for indirect, indexed halfword operation are the
same with one exception: reference address 1 and the final
effective address are concatenated with three leading zeros
(as opposed to being transformed by the memory map).

REAL-EXTENDED ADDRESSING
Real-extended addressing is simi lar to real addressing in that
a direct relationship exists between the effective virtual address of each instruction and the actual address. The function of real-extended addressing is to facilitate operations
in a memory system larger than 128K words.

Note:

Instructions and indirect addresses that involve
real-extended address calculations must themselves
reside in the first 128K words of memory (or in the
general registers), although they in turn may ultimately access operands in locations beyond the first
128K words of memory.

Main Memory

Instruction in memory:

Instruction in instruction registers:

The 8 high-order bits of the reference address are
replaced with ll-bit page address Z from memory map:

Actual address of memory location that contains
the direct address:

~------~~------~'r~------~~~----~
22-bit actual address

17-bit direct address in memory:

III
Indi rect addressing replaces reference address
with direct address:

Halfword operation indexing alignment:

IIII

Effective virtual address:

I. III ~-~it ~i~t~al,.lh.?I!~o!~
~d~r:s:-'
t t t t t t
IK KKK KKK K T

r t

ItUI

15116 17 18 19120 21 22 23124 25 26 27128 29 30 313233

The 8 high-order bits of the effective address are
replaced with ll-bit page address N from memory map:

Final memory address, which is the actual address of
halfword location containing the effective halfword:

Figure 7. Generation of Actual Addresses Indirect, Virtual Addressing

Ma i n Memory

Real-extended addressing is specified when PSWs bit
location 9 contains zero and PSWs bit location 61 contains
one. In real-extended addressing, the 17-bit reference
address in the instruction word is expanded to a 20-bit reference address by the appendage of 3 bit positions to the
left of the reference address (see Figure 8). If indexing or
indirect addressing are not specified in the instruction,
these 3 bit positions contain zeros. Otherwise, address
calculations are performed in this manner: If indexing is
specified (X field in the instructi-on contains a value other
than zero), the contents of the specified index register are
properly al igned with respect to the 17-bit reference address according to the general alignm~nt rules. Arithmetic
on the aligned quantities then takes place using the full
32-bit contents of the index register. The final result is
truncated 3 bits to the left of the original 17-bit reference address, these 3 bi ts having been acqui red from
the index register plus any carry resulting from the addition

of the 17-bit reference address with the index register
contents,
If the instruction specifies indirect addressing (bit position 0
contains one), the 17 bit reference address is used to access an indirect word in memory. The low-order 20 bits of
the indirect word then replace the 17-bit reference address
from the instruction. If indexing is also specified, the
appropriate alignment of the 32-bit contents of the index
register is then made and the addition operation performed.
The result is truncated to the left of the 20-bit operand obtained from the indirect address word.
In real-extended addressing, 20-bit address calculations
actually encompass 22-, 21-, 20-, and 19-bitcalculations,
respectively, for byte, halfword, word, and doubleword
alignments (see Figures 8 and 9).

Instruction in memory:

information used by address
generator:

Indexed
not indexed

I IIII
Byte operation indexing alignment:

22-bii displacement ;alue

Halfword operation indexing alignment:

Word operation indexing al ignment:

Shift operation indexing alignment:

Doubleword operation indexing alignment:

20-bit effective address:

Figure 8. Index Displacement Alignment (Real-Extended Addressing)

Main Memory

Instruction in memory:
o

Instruction in instruction register:

Indi rect reference addresses:

Contents of indirect reference address:

Address used if bit 0

= 1:

Displacement aligned for halfword indexing:

Final effective address:

Figure 9. Generation of Effective Virtual Address (Indirect Real-Extended Addressing)

The stack pointer doubJeword for push-down instructions
contains a 2O-bit word address for the top of stack address
field; as shown in the following format:

During real-extended addressing memory write protection
is invoked.
Table 1 summarizes the addressing characteristics.

Me i n Memory

Table 1. Basic Processor Operating Modes and Addressing Cases
PSW BIT
MS MM

Mode and Addressing Characteristics

Master mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).

Slave mode, unmapped, 17-bit calculations, real addressing (128K words, maximum).

Master mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction reference
address (instructions and indirect words in first 128K words only), indexed and indirect addresses are
20 bits.

Slave mode, unmapped, 20-bit calculations, real-extended addressing, 17-bit instruction reference
address (instructions and indirect words in first 128K words only), indexed and indirect addresses are
20 bits.

Master mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to
1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-order
zeros for all pages) .•

Slave mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum), map to
1M words, real (Sigma 6/7 map to first 128K words by virtue of loading map with three high-order
zeros for a II pages).
Master-protected mode, mapped, 17-bit calculations, virtual addressing (128K words, maximum),
map to 1M words, real (access protection invoked).

INTERRUPT AND TRAP ENTRY ADDRESSING

t-ormat ,:

An instruction residing in an interrupt location (see "Centra Iized Interrupt System" later in this chapter) and executed as the di rect resu It of an interrupt sequence is defi ned
as an interrupt instruction. Both conditions must be true
simultaneously. Thus an instruction in an interrupt location
is not an interrupt instruction if it is executed as the result
of a program branch to the interrupt location under normal
program control. The only valid interrupt instructions are
XPSD, PSS, MTW, MTH, and MTB.

Format 2:

Similarly, a trap instruction (see "Trap System", later in
this chapter) is defined as an instruction in a trap location
executed as a direct result of a trap condition. The only
valid trap instructions are XPSD and PSS.

Format 1 is used in these circumstances:
1.

Bit position 10 (AT) of the XPSD contains zero. In this
format the reference address is a 20-bit actual address
(i .e., no mapping). Note that this is true regardless
of whether the instruction is in a trap, interrupt, or
normal location and independent of the mode (mapped,
unmapped, real-extended) of the current PSWs. If indirect addressing is specified, the indirect word contains a 20-bit address with exactly the same properties.

Bit position 10 (AT) of the X PSD contains one, the instruction is in a trap or interrupt location, the instruction
is being executed as the result of a trap or interrupt,
and the current mode of the PSWs is not rea I-extended.
In this format, the reference address is a 20-bit actual

XPSD Address Calculations. Address calculations associated with XPSD instructions deviate from the standard
forms. Two basic formats are used in XPSD instructions,
depending on whether subjective or objective addressing
is being used.
Bit 10 of the XPSD instruction is the addressing type (AT)
designator. In the circumstances described below, it designates whether the reference address in the XPSD instruction is to be considered unconditionally as a 20-bit real
address or whether the current mode of addressing ca Iculati ons is to be appl ied to it.

Main Memory

address if PSWs bit 9 is zero (no map), or a 20-bit
virtual address if PSWs bit 9 is one (map). If indirect
addressing is specified, the indirect word contains a
20-bit address with exactly the same properties.

Format 2:

Format 2 is used in all other circumstances, namely:
1.

Bit position 10 (AT) contains a one, and
a.

The XPSD is not being executed as the result of a
trap or interrupt, or

It is in a trap or interrupt location, is being executed as the result of a trap or interrupt, but the
current mode of the PSWs is real-extended.

In these cases, all of the normal rules of address calculations hold, i.e., indirect, index, and map.

PSS Address Calculations. PUSH STATUS (PSS) address calculations are simi lar to but simpler than those for the X PSD
instruction. Two basic formats are used:

Format 1 is used when the modify and test instruction is executed in an interrupt or trap location as a result of an
interrupt or trap sequence. When used as an interrupt instruction, the MTW, MTH, or MTB instruction uses the 20-bit
reference address as a real address (except counter 4), without indexing or mapping. Interrupt Counter 4 uses the map
if mapping is called for. Access protect and write lock
violations are not active.
When used as a trap instruction, the MTW, MTH, or MTB
instruction uses the 20-bit address without indexing; if the
PSWs specify mapping, however, the map is used, with
bits 12-14 of the address ignored.
Format 2 is used when the modify and test instruction is executed in the normal course of program execution. Addressing in this case is completely standard, including indexing
and indirect addressing.

Format 1:
RD and WD Address Calculations. The final output address
for a READ DIRECT (RD) or a WRITE DIRECT (WD) instruction is the low-order 16 bits of the effective virtual address.
If indexing is specified in the instruction, the low-order
17 bits of the instruction are modified by the indexing operation, and the resultant 17-bit address is truncated to
16 bits and transmitted as the final address. No mapping
takes place.

Format 2:

Format 1 is used when the PSS is executed in an interrupt or
trap locati on as a resu I t of an interrupt or trap sequence.
No indexing is possible because its designator field is preempted by the reference address. Indirect addressing is permitted with the same constraint against indexing; the indirect
address word contains a 20-bit real address with precisely
the same properties as the reference address. In the case
of a trap instruction, the 20-bit reference address can be
either a reo I oddre5s or a virtua! address accordlng to the
value in PSWs bit position 9.

If indirect addressing is specified in the instruction, the indirect address word is generated in the standard manner according to the mode bits in the PSWs. Thus mapping will
occur if it is specified in the PSWs. If indexing is also specified, the indirect address in the indirect word is modified
by the indexing operation and the resultant address is truncated to 16 bits and transmitted as the final address.

Format 2 is used when the PSS instruction is executed in
the course of normal program execution. Addressing in this
case is completely standard, including indexing and indirect addressing.

Two methods of program control of main memory are the
memory map and the memory locks. The memory map provides for dynamic relocation of programs and for access
protection through inhibitions imposed on slave or masterprotected mode programs. Access protection violations in
either mode are trapped to location X'40'. The memory
locks provide memory write protection for all modes of programs throughout a I I rea I memory. The memory locks apply
to input/output operations as well as basic processor operations. This protection is effective at the page level, is for
reai addresses, and is operative in addition to the protection
provided virtual addresses at the page level. Memory protection violations in any mode are trapped to location X'40' .

During the execution of the PSS instruction the interrupt
stack pointer is accessed from real memory locations Oand 1.
The interrupt stack address therein is a real 20-bit address
with no indexing or mapping used.

tvHW, MTH, uno MTS Addre:>:> Calculations. iwo basic
formats are used in modify and test instructions:

MEMORY ADDRESS CONTROL

Format 1:
Note:
2i 2, 2J,24 2) 20 2.;';28 29

Main Memory

A WD instruction used to write into main memory locations a through 31 is not subject to write
protection.

MEMORY MAPPING AND ACCESS PROTECTION
The memory map is physically an array of 256 l1-bit registers. The array resides in the Memory Interface (MI) of
the processor cluster containing the basic processor. Each
register has an 8-bit address (that corresponds to an 8-bit
virtual page address) and contains an ll-bit actual page
address for a specific 512-word page of memory. Mapping
always transforms a 17-bitvirtual address into a 20-bit real
address.
The actual page addresses are assigned to pages of virtual
addresses in this manner:
Actual page X
(11 bits)

Actual page K
(11 bits)

Vi rtua I addresses Vi rtua I addresses
X ' lO'-X'l FF'
X '200'-X ' 3FF'
(virtual page 0) (virtual page 1)

Ac tua I page N
(11 bits)
Virtual addresses
XI 1FEOO 1- XI 1 FFFF1
(virtual page 255)

Just prior to a memory reference, the most significant 8 bits
of a 17-bit virtual address are used as the address of an
element of the map array. The 11 bits contained within
that element are then used in conjunction with the loworder 9 bits of the 17-bit virtual address to produce a
20-bit actua I address.
Sigma 6/7 compatible mapping is accomplished by loading
the map with 8-bit address elements (instead of 11-bit address elements) via the MOVE TO MEMORY CONTROL
(MMC) instruction. The 8 bits are stored in the low-order
8 bits of each map element and the 3 high-order bit positions are reset to zero. Thus the map will always relocate
to the same address in the first 128K words of real memory
and be compatible for Sigma 6/7 programs.
Associated with the memory map feature is another array
of 256 2-bit registers, also located in the Memory Interface. Each register contains a 2-bit access control code
for a specific 512-word page of virtual addresses. The
access-protection code indicates the allowed use or availability of the corresponding page of virtual memory. Access
protection applies to all pages of the virtual address space
of the active program, and is only active when the memory
map is invoked.

Vi rtual addresses
X'600 '-X'7FF'
Virtual addresses
X'400'-X ' 5FF'
Virtual addresses
X'200'-X'3FF'
Virtual addresses
X'10'-X'lFF'
(Virtual page 0)

Virtual
addresses
X'lFEOO'X'l FFFF'
(virtual
page 255)
Virtual
addresses
X'lFCOO'X'lFDFF'

The memory page address and access-control codes can
be changed only by use of the privileged MMC instruction
(see Chapter 3, "Control Instructions).
Access protection is in effect whenever the memory map is
in effect (PSWs 9 = 1) and the basic processor is operating
in the slave mode (PSWs 8 = 1) or in the master-protected
mode (PSWs61 =1). Access protection is not in effect
when the basic processor is operating in the master mode.
When the memory map is in effect, all memory references
used by the program (including instruction addresses) whether
direct, indirect, or indexed, are referred to as virtual addresses. Virtual addresses in the range 0 through 15 are
not used to address main memory; instead the 4 low-order
bits of the virtual address comprise a general register address. If, however, an instruction produces a virtual address greater than 15, the 8 high-order bits of the virtual
address are used to obtain the appropriate l1-bit actual
memory page address and 2-bit access control codes. For
example, if the 8 high-order bits of the virtual address are
0000 0000, the first page address code and the first access
control code are used; if the 8 high-order bits of the virtual
address are 0000 0001, the second page address code and
the second access control code are used, etc., through the
256th page address and access control codes. Thus each
512-word page of virtual addresses is associated with its
own memory page address and access control codes.
When the memory map is accessed during a slave mode or
master-protected mode program, the basic processor determines whether there are any inhibitions to using the virtual
address.
These are the four types of access protection codes:
00

A slave mode or master-protected mode program
can write into, read from, or access instructions
from this page of virtual address.

A slave mode or master-protected mode program
cannot write into this page of virtual addresses;
it can, however, read from or access instructions
from this page of virtual addresses.

A slave mode or master-protected mode program
cannot write into or access instructions from this
page of virtual addresses; it can, however, read
from this page of virtual addresses.

A slave mode or master-protected mode program
is denied any access to this page of virtua I
addresses.

If the instruction being executed by the slave or masterprotected program fai Is the foregoing test, the instruction
is aborted and the basic processor traps to location X '40 1 ,
the "non-allowed operation" trap (see "Trap System", later
in this chapter).
Contrarily, if the instruction being executed by the slave
mode or master-protected mode program passes this test (or
if the basic processor is operating in the master mode), the

Main Memory

ll-bit page address in the accessed element of the memory
map array replaces the 8 high-order bits of the virtual address to produce the actual address of the main memory location to be used by the instruction (20-bit word address
that is automatically adjusted as required for doubleword,
halfword, or byte operation). See Figure 7.
Note: If the ll-bit page address in the accessed element
of the memory map is all zeros, and an actual address is produced that corresponds to a word address
in the range 0 through 15, when the ll-bit page
address is combined with the 9 low-order bits of the
virtual address, the corresponding general register
in the current register block is not accessed. In
this one particular instance a word address in the
range 0 through 15 corresponds to an actual main
memory location rather than a general register.

REAL MEMORY WRITE LOCKS
Additional memory protection, independent of the access
protection, is provided by a write lock and key technique.
A 4-bit write protect lock (WL) is provided for each 512word page of actual memory. Thus, for the maximum lMword real memory there would be 2048 4-bit write locks.
Write locks are assigned to pages of actual addresses as
follows:

Actual addresses
X'600'-X'7FF'
Actual addresses
X'400'-X'5FF'
Actual addresses
X'200'-X'3FF'
Actual addresses
O-X'lFF'
(memory page 0)

Actual
addresses
X'l FEOO'X'l FFFF'
(memory
page 255)
Actual
addresses
X'lFCOO'X'lFDFF'

A key value of 0000 is a "skeleton" key that will open
any lock; thus write access to any memory page is permitted independent of its lock value.

A lock value other than 0000 for a memory page permits write access to that page only if the key value
(other than 0000) is identical to the lock value.

Thus a program can write into a given memory page if the
lock value is 0000, if the key value is 0000, or if the key
value matches the lock value.
Note:

The memory access protection feature operates during virtua I addressing modes and on virtua I addresses,
whereas the memory write protection feature always
operates on actual memory addresses. Thus, if the
memory access protection feature is invoked (that
is, if the basic processor is operating in the slave
mode or the master-protected mode and is using the
memory map), the access protection codes are examined when the virtual address is converted into
an actual address. Then the lock and key are examined to determine whether the program (master,
master-protected, or slave mode) is allowed to alter
the contents of themainmemory location corresponding to the final actual address. If an instruction attempts to write into a write-protected memory page,
the basic processor aborts the instruction, and traps
to location X '40', the "nonallowed operation" trap
(see "Trap System ", later in this chapter). If an
I/O procedure attempts to write into a writeprotected memory page, the write lock violation bit
in the lOP status byte is set, and can be tested by
the AIO, no, and TDV instructions.

PROGRAM STATUS WORDS
The critical control conditions of the basic processor are defined within 64 bits of information collectively referred to
as the program status words (PSWs). The current PSWs may
be considered as one 64-bit internal basic processor register,
although they actually exist as a collection of separate n~g
isters and flip-flops (see Figure 2 appearing earlier in this
chapter). When stored in memory, the PSWs have the following format:

The write protect locks can be changed only by executing
the privileged instruction MOVE TO MEMORY CONTROL
(see Chapter 3, "Control Instructions").
The write key (a 4-bit field in the PSWs for any operating
program, or in the command doubleword for I/O operations)
works in conjunction with the write lock to determine
whether any program (slave, master-protected, or master
mode) can write into a specific page of main memory iocations. The write key and lock control access for writing
according to these rules:

A lock value of 0000 means that the corresponding
memory page is unlocked; write access to that page is
permitted independent of the key value.
Main Memory

They may be optionally followed byan additional two words
with the following format:

.:,

Designation

Function

Condition code. This generalized 4-bit code
indicates the nature of the results of an
instruction. The significance of the condition
code bits depends upon the particular instruction just executed. After an instruction is
executed, the BRANCH ON CONDITIONS
SET (BCS) and BRANCH ON CONDITIONS
RESET (BCR) instructions can be used singly
or in combination to test for a particular condition code setting. (These instructions are
described in Chapter 3, "Execute/Branch
Instructi ons ").

In some operations only a portion of the condition code is involved; thus, the term CCl
refers to the first bit of the condition code,
CC2 to the second bit, and CC3 and CC4,
respectively, to the third and fouTth bits.
Any program can change the current value
of the condition code by executing either
the LOAD CONDITIONS AND FLOATING
CONTROL IMMEDIATE (LCFI) or the LOAD
CONDITIONS AND FLOATING CONTROL
(LCF) instruction. Any program can store
the current condition code by executing
the STORE CONDITIONS AND FLOATING
CONTROL (STCF) instruction. These instructions are described in Chapter 3, II Load/Store
Instructions".

Floating round mode control (see FN below).

Floating significance mode control (see FN
below).

Floating zero mode control (see FN below).

Floating normalize mode control. The four
floating-point mode control bits (FR, FS, FZ,
and FN) control the operation of the basic
processor with respect to invoking the roundoff mode of floating-point calculations,
checking floating-point significance, generating zero results, and normalizing the
results of floating-point additions and subtractions, respectively. (The floating-point
mode controls are described in Chapter 3,
II Floating-Point Instructions".)
Any program
can change the state of the current floatingpoint mode controls by executing either the
LCFI or the LCF instruction. Any program

De~gnaHon

FuncHon

FN (cont.)

can store the current state" of the current
floating-point mode controls by executing the
STCF instruction.

Master/slave mode control. The basic processor is in the master mode when this bit and
the mode altered bit (bit 61) both contain
zero; it is in the slave mode when this bit
contains one. (See MS for a description of
master-protected mode.) A master mode or
master-protected mode program can change
this mode control bit by executing the
LOAD PROGRAM STATUS WORDS (LPSD),
EXCHANGE PROGRAM STATUS WORDS
(XPSD), PUSH STATUS (PSS), or PULL STATUS
(PLS) instruction. These privi leged instructions are described in Chapter 3, "Control
Instructions" •

Memory map control. The memory map is in
effect when this bit position contains a one.
A master mode or master-protected mode program can change the memory map control by
executing an LPSD, XPSD , PSS, or PLS
instruction.

Arithmetic mask. The fixed-point arithmetic
overflow trap is permitted to occur when this
bit contains one. The instructions that can
cause fixed-point overflow are described in
the section "Trap System", later in this chapter. The arithmetic trap mask can be changed
by a master mode or master-protected mode
program executing an LPSD, XPSD, PSS, or
PLS instruction.

Instruction address. This 17-bit field contains
the virtual address of the next instruction to
be executed.

Write key. This field contains the 4-bit key
used in conjunction with a write lock in the
memory write protection feature. A master
mode or master-protected mode program can
change the value of the write key by executing an LPSD, XPSD, PSS, or PLS instruction.

Counter interrupt group inhibit (see El, below).

Input/output interrupt group inhibit (see El,
below).

External interrup group inhibit. The three interrupt group inhibit bits (CI, II, and EI)
determine whether certain interrupts are
Main Memory

Designation

Function

EI (cont. )

allowed to occur. The function of these group
interrupt inhibits are described in "Centra 1ized Interrupt System", later in this chapter.
A master mode or master-protected mode program can change the group interrupt inhibits
by executing an LPSD, XPSD, PSS, PLS, or
WRITE DIRECT 0ND) instruction. These privi leged instructions are described in Chapter 3, "Control Instructions".

Register pointer. This 2-bit field selects one
of the 4 possible blocks of general-purpose
registers as the current register block. A
master or master-protected mode program can
change the register pointer by executing
LPSD, XPSD, PSS, PLS, or the LOAD REGISTER POINTER (LRP) instruction. LRP is
described in Chapter 3, under "Control
Instructions" .

Register altered bit. When a trap occurs,
this bit is set to one when any general register or location in memory has been altered
in the execution or partial execution of the
instruction that caused the trap.

Mode altered. This bit is used to invoke both
the master-protected mode of operation and
the real-extended addressing mode). Table 1
details the function of the setting of this bit
in conjunction with the setting of the MS
(bit 8)and MM (bit 9) fields. The bits are set
by an LPSD, XPSD, PSS, or PLS instruction.

Memory protection violation address. If the
X PSD instruction is being executed in a trap
routine as a result of a memory protection
violation and the SP bit in theXPSD is a one,
the effective virtual address causing the
violation is stored in the fourth word. This
storage may be invoked so that memory protection violations can be recorded.

When all the conditions for acknowledging the interrupt
have been achieved, the basic processor stops executing
the current program and executes the instruction in the corresponding interrupt location. After the basic processor has
successfully accessed the interrupt instruction, it advances
the interrupt level to the active state. The basic processor
may actually execute many program instructions between
the time that the interrupt-requesting condition is sensed
and the time that the actual interrupt acknowledgment occurs. After the interrupt is completely processed, the basic
processor returns to the interrupted program and resumes its
execution.

STATES OF AN INTERRUPT LEVEL
An interrupt level is mechanized by means of three flipflops. Two flip-flops are used to define four mutually exclusive ~tates: disarmed, armed, waiting, and active. The
third flip-flop provides the disabled/enabled function and
is independent of the defined state. The various states and
the conditions of interrupt levels are described in the following paragraphs. Figure 10 conceptually illustrates the
operational state changes of a typical interrupt level.

DISARMED
When an interrupt level is in the disarmed state, no signal
is admitted to that interrupt level; that is, the level neither
accepts nor remembers an interrupt event, nor is any program interrupt caused by it at any time.

Although an interrupt level can change from any state to
the disarmed state, only a special form of the WRITE DIRECT
instruction (WD) can cause a disarmed level to change to
another state. The WD instruction is described in Chapter 3, IIControl Instructions II.

ARMED
When an interrupt level is in the armed state, it can accept
and remember an interrupt signal. The receipt of such a signal advances the interrupt level to the waiting state where
it remains unti I it is allowed to advance to the active state.
A special form of the WD instruction can cause an armed
level to be advanced di rectly to the active state.

A level can change from any state to the armed state.

CENTRALIZED INTERRUPTS
The system includes a single, centralized interrupt feature.

WAITING

~~, I interrupts are terminated in the System Control Pro-

cessor. The System Control Processor is described earl ier
and also in Chapters 5 and 6.
When a condition that will result in an interrupt is sensed,
a signal is sent to the corresponding interrupt level. If
that level is "armed", it advances to the waiting state.

Centralized Interrupts

For an interrupt level to be in the waiting state, that level
must have been previously armed and received an interrupt
signal. The signal may have been generated externally,
internally, or have resulted from a WD operation. Any
signals received by an interrupt level already in the waiting
state are ignored.

Interrupt
State
Disarmed

FF Configuration

Source of
Change Signal

level
Enable

Basic Processor

Armed

[$
[$

Basic Processor
or External Signal

III'

Waiting

Bas i c Processor

Interrupt Timing

Active

Group Inhibit off

No higher-priority level active,
or waiting and enabled

Figure 10. Operational States of an Interrupt level

When an interrupt level is in the waiting state, the following conditions must all exist simultaneously before the level
advances to the active state:
1.

The level must be enabled (i .e., its enable/disable
fl ip-flop must be set to one).

The group inhibit (CI, II, or EI, if appl icable) must be
zero.

Generally, if the enable/disable flip-flop is off (level is
disabled), the interrupt level can undergo all state changes
except that of moving from the waiting to the active state
(see excepti on case, be low). Furthermore, if the interrupt
level is disabled, it is completely removed from the chain
that determines the priority of access to the basic processor.
Thus a disabled interrupt level in the waiting state does not
prevent an enabled, waiting interrupt level of lower priority
from moving to the active state.

No higher-priority interrupt level is in the active
state, or is in the waiting state, enabled, and not
inhibited.

Note this exception to the foregoing description: Although
generally no interrupt level can move from the waiting state
to the active state un less it is enabled, a specia I form of the
WD instruction can move a waiting level to the active state
whether or not the level is enabled.

The basic processor must be at an interruptible point
in the execution of a program.

ACTIVE

Note that one or more interrupt levels of higher priority can
also be in the waiting state if they are disabled, inhibited,
or both disabled and inhibited.

After the basic processor has successfully accessed !"he interrupt instruction, then the interrupting level advances to
the active state. When all the conditions for acknowledgment have been achieved, the interrupt level causes the
Central ized Interrupts

basic processor to execute the contents of the assigned
interrupt location as the next instruction. (Interrupt locations are defined in "Physical Organization ll , later in this
chapter.) The instruction address portion of the program status words (PSWs) remains unchanged until the instruction in
the interrupt location is executed.
The instruction in the interrupt location must be one of the
following: XPSD, PSS, MTS, MTH, or MTW. If the execution of any other instruction in an interrupt location is attempted as the result of an interrupt level advancing to the
conditions for acknowledgment, an instruction exception
trap occurs.
The use of the privileged instruction XPSD or PSS in an interrupt location permits an interrupt-servicing routine to
save the entire current machine environment. If working
registers are needed by the routine and additional register
blocks are avai lable, the contents of the current register
block can be saved automatically with no time loss. This
is accomplished by changing the value of the register pointer
(using the LOAD REGISTER POINTER instruction), which
results in the assignment of a new block of 24 registers to
the routine. The instruction LOAD REGISTER POINTER
(LRP) is described in Chapter 3, "Control Instructions ll •

transmission is delayed unti I the new inhibit states of the
basic processor are known; these states are transmitted to
the interrupt system so the latter can record the new basic
processor status.

DIALOGUE DURING AN INTERRUPT-EXITING SEQUENCE
When the basic processor exits an interrupt-servicing routine, it must notify the interrupt system to move the interrupt
level associated with that routine from the active state to
either the armed or disarmed state. To do this it must gain
access to the processor bus and the interrupt system, either
of which may be busy at the time access is requested. When
communication with the interrupt system is established, the
basic processor transmits information for setting the level
state to armed or disarmed, and new inhibit states it has assumed as a result of the exit operation.

PHYSICAL ORGANIZATION
An interrupt level remains in the active state unti I it is
cleared (removed from the active state and returned to the
disarmed or armed state) by the execution of the LPSD, PLS,
or WD instruction. An interrupt-servicing routine can itself
be interrupted (whenever a higher priority interrupt level
meets all the conditions for becoming active) and then continued (after the higher priority interrupt is cleared). However, an interrupt-servicing routine cannot be interrupted
by an interrupt of the same or lower priority as long as the
higher priority interrupt level remains in the active state.
Any signals received by an interrupt level in the active
state are ignored. Norma lIy, the interrupt-servicing routine clears its interrupt level and transfers program control
back to the point of interrupt by means of an LPSD instruction with the same effective address as the XPSD instruction in the interrupt location.

DIALOGUE BETWEEN THE BASIC PROCESSOR AND
THE INTERRUPT SYSTEM DURING AN INTERUPTENTERING SEQUENCE
When an interrupt level is ready to be moved to the active
state, a dialogue takes place between the interrupt system
and the basic processor. This dialogue takes place over the
processor bus and involves the Processor Interface (PI) associated with the processor cluster of which the basic processor is a member. When the processor bus becomes available
and the b(lsic processor is at an interruptible point, the interrupt system transmits the interrupt address to the basic
processor. It initiates its interrupt actions (i.e., executes
the instruction in the interrupt location and services the
interrupt at the appropriate time to avoid race conditions,
and communicates with the interrupt system with an indication to move the level to the active state. This latter

Centralized Interrupts

Up to 62 interrupt levels are avai lab Ie, each with a unique
location (see Table 2) assigned in the System Control Processor, and with a unique priority. The basic processor can
selectively arm, enable, or arm and enable any interrupt
level. The basic processor can also IItrigger" any interrupt
level (supply a signal at the same physical point where the
signal from the external source would enter the interrupt
level). The triggering of an interrupt permits testing special systems programs before the special systems equipment
is avai lable. The basic processor also permits an interruptservicing routine to defer a portion of the processing associated with an interrupt level by processing the urgent
portion of an interrupt-servicing routine, triggering a lower
priority level (for a routine that handles the less urgent
part), then clearing the high-priority interrupt level so that
other interrupts can occur before the deferred interrupt response is processed.

INTERRUPT GROUPS
Interrupt levels are organized in standard group configurations that are connected in a predetermined and fixed priority chain (see Table 2 and Figure 11). The priority of each
level within a group is fixed; the first level has the highest
priority and the last level has the lowest.

INTERNAL INTERRUPTS
Standard internal interrupts are provided with the system
and include all group D levels (internal override, counterequa Is-zero, and I/O).

Table 2. Interrupt Locations
Address
Dec

DIO Address
PSWs
Inhibit

Hex

Function

85
86
87

52
53
54
55
56
57

Counter 1 count
Counter 2 count
Counter 3 count
Counter 4 count
Processor faul t
Memory Fault

112
113
114
115
116
117
118
119
120
121
122
123

70
71
72
73
74
75
76
77
78
79
7A
7B

External group 3
(first 12 levels)

CounterEquals-Zero

88
89
90
91

58
59
5A
5B

Counter
Counter
Counter
Counter

I/O

92
93
94
95

5C
5D
5E
5F

Input/Output
Contro I pane I
Reserved
Reserved

Group

82
83

Internal
Override

External
Override
(optional)

External
Group 2
(optional)

1
2
3
4

pulse
pulse
pulse
pulse

none

zero
zero
zero
zero

External
Group 4
(optional)

128

144

16
17
18
19
20
21

16
17
18
19
20
21
22
23
24
25
26
27

22
23
24
25

26
27
28
29

16
External group 4
(first 12 levels)

139

16
Externa I group 2
(first 12 levels)

107

Group

4
27

I
I

External
Group 5
(optional)

I
I
!

155

16
Externa I group 5
(first 12 levels)

I
I

5
27

Centra I i zed Interrupts

1st Priority
Internal
Override
Interrupts

4th Priority
I/o Interrupts

3rd Priority

2nd Priority

CounterEquals-Zero
Interrupts

External
Override
Interrupts

6th Priority

5th Priority

External
Group 4
Interrupts

External
Group 2
Interrupts

7th Priority
External
Group 5
Interrupts

Figure 11. Interrupt Priority Chain
Internal Override Group (Locations X I52 1 through X I571).
The six interrupt levels of this group always have the highest
priority in the system. The four count-pulse interrupt levels
are triggered by pulses from clock sources. Counter 4 has
a constant frequency of 500 Hz. Counters 1, 2, and 3 can
be individua IIy set to any of four manually switchable frequencies - the commercial line frequency, 500 Hz, 2000 Hz,
or a user-supplied external signal - that may be different
for each counter. Each of the count pulse interrupt locations must contain one of the modify and test instructions
(MTB, MTH, or MTW), an XPSD, or a PSS instruction.
When the modification (of the effective byte, halfword, or
word) causes a zero result, the appropriate counter-equalszero interrupt level (see IICounter-Equals-Zero Groupll) is
triggered.

Note: Count pulse interrupt level 4 is a subjective time
counter with the following special attribute: When
the instruction in location X 155 1 is executed as the
result of an interrupt, it must be an MTB, MTH, or
MTW; otherwise, an instruction exception trap
(X I40 I) will occur.

The internal override group also contains a processor fault
and a memory fault interrupt level. Both locations norma lIy
contain an XPSD or a PSS instruction. The processor fault
interrupt level is triggered by a signal when certain fault
conditions are detected. A POLR instruction must be used
to reset the fault. The memory fault interrupt level is

Centralized Interrupts

triggered by a signal that the memory generates when it
detects certain fault conditions. An LMS instruction must
be used to reset the fault. (See IITrap System ll later in
this chapter for further information on processor and memory
faults.)
Counter-Equals-Zero Group (Locations X 158 1through X 15B I).
Each interrupt level in the counter-equa Is-zero group is associated with a corresponding count-pulse interrupt level in
the internal override group. When the execution of a modify and test instruction in the count-pulse interrupt location
causes a zero result in the effective byte, halfword, or word
location, the corresponding counter-equals-zero interrupt
level is triggered. The counter-equals-zero interrupt locations normally cO':!tain an XPSD or a PSS instruction and
they can be inhibited or permitted as a group. If bit 37
(CI) of the current PSW contains a zero, the counter-equalszero interrupt levels are allowed to interrupt the program
being executed. If the CI bit contains a one, the counterequals-zero interrupt levels are inhibited from being allowed
to interrupt the program. These interrupt levels wait until
the CI bit is reset to zero and then interrupt the program according to priority.
Input/Output Group (Locations X I5C through X I5FI). This
interrupt group comprises the input/output (I/O) interrupt
level, the control panel interrupt level, and two levels reserved for future use. The I/O interrupt level accepts interrupt signals from the I/O system. The I/O interrupt location

is assumed to contain an XPSD or a PSS instruction that
transfers program control to a routine for servicing all I/o
interrupts. The I/o routine should contain an ACK NOWLEDGE I/o INTERRUPT (AIO) instruction that identifies the
source and reason for the interrupt. (The AIO instruction is
discussed in Chapter 3 "Input/Output Instructions II . )
The control panel interrupt level is activated from the operator's console. This location normally contains an X PSD
or a PSS instruction. The opera"tor can thus trigger this interrupt level to initiate a specific routine.
The interrupt levels in the I/O group-can be inhibited or
permitted by means of bit position 38 (II) of the PSWs.
If II is reset to zero, interrupt signals affecting the I/o
group interrupt levels are allowed to interrupt the program
being executed. If the II bit is set to one, interrupt
signals in this group are inhibited from interrupting the
program.

level in an uninhibited group from interrupting the program.
However, if an interrupt group is inhibited while a level in
that group is in the active state, no lower priority interrupt
level can advance to the active state.
Note also this special case: When the processor detected
fault (PDF) flag is set to 1 (see "Processor Detected Faults",
later in this chapter), the processor fault, memory fault,
and count pulse interrupts are automatically inhibited.
The second point of interrupt control is at the individual
interrupt level. The basic processor can interact with any
interrupt level by means of special modes of the RD and WD
instructions (described in Chapter 3, IControIInstructions").
For this purpose, the interrupt levels are organized into the
following DIO address groups (see last two columns in
Table 2):
1.

The 14 levels of internal interrupts {internal override
group, counter-equals-zero group, and I/O group} are
designated as group code 0 in bits 28-31 of the effective address of the RD or WD instruction.

The 12 levels of each group of external interrupts are
designated as group codes 2, 3, 4, and 5. That is,
external group 2 is designated group code 2, external
group 3 is designated group code 3, etc.

There is no group code 1.

EXTERNAL INTERRUPTS
A system can contain 4 optional groups of external interrupt levels. The external override group, group 3, contains
the first 12 external interrupt levels. External groups 2,
4, and 5 each contain 12 external interrupt levels. (See
Table 2 and Figure 11.) External levels may be triggered
by external sources or via WD instructions, while internal
levels may be triggered by internal sources or via WD
instructions.
All external interrupt levels normally contain XPSD or PSS
:_,." ..... _"': __ ,.. _"';',J ___

"''''''uw'''''''w' \oA""" .... _ ••

h_ :_l.-.:h: . . .o,...J
..., ...... "'1.,'...",_-

h", rnonnt: nt
_. ,...._11 ..•.. _- _, ... __ .. __ .

"",. n..o.rn"l:f-+.orl

the setting of bit position 39 (EI) of the program status words.

If EI contains a zero, external interrupts are allowed to interrupt a program; if EI contains a one, all externa I interrupts are inhibited from interrupting the program.

NUMBER OF INTERRUPT GROUPS
The 14 internal interrupt levels are standard in every system
and all external levels are optional. The addition of the
external groups (12 levels per group) raises the number of
interrupt levels to a maximum of 62.

The addressing of an individual interrupt level within its
DIO group of 12 or 14 is accomplished by an assignedselection bit within the low-order 16-bit positions of the R register designated in the RD or WD instruction (see last
column in Table 2).
The WD instruction can individually arm, disarm, enable,
disable, or trigger (move to the active state) any interrupt
level. The RD instruction can determine which interrupt
levels within a selected DIO group are in the armed or
waiting state, waiting or active state, or are enabled.

TIME OF INTERRUPT OCCURRENCES

CONTROL OF THE INTERRUPT SYSTEM
The system has two points of interrupt control. One point
of interrupt control is achieved by means of the interrupt
inhibit bits (CI, II, and EI) in the program status words (PSWs).
The basic processor is inhibited from interrupting a program
if the interrupt inhibit bit for a corresponding class of interrupt levels is set to one, that is, no interrupt level in the
inhibited group can advance from the waiting state to the
active state, and the entire group is disabled (removed from
the interrupt recognition priority chain). Consequently, a
waiting, enabled, interrupt level in an inhibited group does
not prevent a lower priority, waiting, enabled interrupt

The basic processor permits an interrupt to occur during the
following time intervals (related to the execution cycle of
an instruction) provided the SCP basic processor (BP) status indicators are either in the RUN or WAIT condition:
1.

Between instructions an interrupt is permitted between
the completion of any instruction and the initiation of
the nex t i nstructi on.

Between instruction initiations an interrupt is also permitted to occur during the execution of the following
multiple-operand instruction:
MOVE TO MEMORY CONTROL (MMC)

Central ized Interrupts

The control and immediate results of this instruction reside
in registers and memory; thus, the instruction can be
interrupted between the completion of one iteration (operand execution cycle) and that time (during the next iteration) when a memory location or register is modified. If an
interrupt occurs during this time, the current iteration is
aborted and the instruction address portion of the program
status words (PSWs) remains pointing to the interrupted instruction. After the interrupt-servicing routine is completed, the instruction continues, from the point at which it
was interrupted and does not begin anew.

TRAP SYSTEM
A trap is similar to an interrupt in that when a trap condition occurs, program execution automatically branches to a
predesignated location. A trap differs from an interrupt in
that a trap location must contain an XPSD or PSS instruction. The time of trap occurrence can vary: The instruction in the trap location can be executed immediately (i .e.,
the current instruction in the program being executed is
aborted), or when the current instruction has been partially
executed, or upon completion of the current instruction.
The trap instruction is not held in abeyance by higher priority traps, whereas interrupts possibly may not be processed
before an entire sequence of instructions is executed.

SINGLE-INSTRUCTION INTERRUPTS
A single-instruction interrupt occurs in this situation: an
interrupt level is activated, the current program is interrupted, the single instruction in the interrupt location is
executed, the interrupt level is automatically cleared and
armed, and the interrupted program continues without being
disturbed or delayed (except for the time required to execute the single instruction).

If any of the following instructions is executed in any interrupt location, then the corresponding interrupt is automatically a single-instruction interrupt:
MODIFY AND TEST BYTE (MTB)
MODIFY A ND TEST HALFWORD (M TH)
MODIFY AND TEST WORD (MTW)

A modify and test instruction modifies the effective byte,
halfword, or word (as described in Chapter 3, "Fixed-Point
Arithmetic Instructions") but the current condition code remains unchanged (even if overflow occurs). The effective
address of a modify and test instruction in an interrupt location (except counter 4) is always treated as an actual address, regardless of whether the memory map is currently
being used. Counter 4 uses the mapped location if mopping
is currently invoked (as specified in the PSWs). The execution of a modify and test instruction in an interrupt
location, including mapped and unmapped counter 4, is independent of the virtual memory access-protection code
and the real memory write lock; thus, a memory protection
violation trap cannot occur as the resultof overflow caused
by executing MTH or MTW in an interrupt location.

TRAP ENTRY SEQUENCE
A trap entry sequence begins when the basic processor detects the trap condition and ends when the new program status words (PSWs) have successfully replaced the old PSWs.
Detection of any condition (function) listed in Table 3,
which summarizes the trap system, results in a trap to a
unique location in memory. When a trap condition occurs,
the basic processor sets the trap state. The operation the
basic processor is currently performing mayor may not be
carried to completion, depending on the type of trap and
the opera tion bei ng performed. In any event, the program
instruction is terminated with a trap sequence (branch to the
appropriate trap location). During this sequence the program counter is not advanced; instead, the X PSD instruction
in the trap location is executed. If any interrupt level is
ready to move to the active state at the same time an XPSD
trap instruction is in process, the interrupt acknowledgment
will not occur until the XPSD trap instruction is completed.
Should a trap location not contain an XPSD or PSS instruction, a second trap sequence is immediately invoked (see
"Instruction Exception Trap" later in this chapter).

TRAP ADDRESSING
Trap addressing is described under "Interrupt and Trap Entry
Addressing II •

TRAP MASKS
The execution of a modify and test instruction in an interrupt
location automatically clears and arms the corresponding interrupt level, allowing the interrupted program to continue.

When a modify and test instruction is executed in a countpulse interrupt location, all of the above conditions apply
as well as the following: If the resultant value in the effective location is zero, the corresponding counter-equalszero interrupt is triggered.

Trap System

The programmer may mask the four trap conditions described
below in the program status words (PSWs) or the stack pointer
doubleword, as appropriate; other traps cannot be masked.

The push-down stack limit trap is masked within the
stack pointer doubleword for each individual stack.

The fixed-point overflow trap is masked in bit position 11 (AM) of the PSWs. If this bit position contains
a zero, the trap is allowed to occur; if bit 11 contains

Table 3.
Locations
Dec.

Hex.

Function

Nonallowed operation

Summary of Trap Locations

PSWs
Mask Bit

Time of Occurrence

Trap Condition Code

Nonexi stent
instruction

None

At instruction decode.

Set TCCl t

Nonexistent memory address

None

Prior to memory access.

Set TCC2

Privi leged instruction in slave mode

None

At instruction decode.

Set TCC3

Memory protection
violation

None

Prior to memory access.

Set TCC4

Write lock violation

None

Prior to memory access.

Set TCC3, TCC4

Reserved

Push-down stack limit
reached

TW, TS
(in stack
pointer)

At the time of stack limit detection.
(The aborted pushdown instruction
does not change memory, registers,
or the condition code.)

None

Fixed-point arithmetic
overflow

For all instructions except DWand
DH, trap occurs after completion of
instruction. For DW and DH, instruction is aborted with memory, register,
CC1, CC3, and CC4 unchanged.

None

Floating-point arithmetic fault

At detection.

Characteristi c
overflow

None

Divide by zero

None

Significance check

FS, FZ, FN

Reserved

Watchdog timer runout

None

{ (The flooting-point instruction is
aborted without changing any registers. The condition code is set to
indicate the reason for the trap. )

At runout.
set. )

(The PDFtt flag wi II be

None
None
None

Set TCC2 if basic
processor using processor bus;
set TCC3 if basic
processor using memory bus; and
set TCC4 if basic processor using DIO bus.

Programmed trap

None

Interruptible point reached upon
completion of WD.

None

tSee IITrap Condition Code ll , later in this chapter.
ttSee IIProcessor Detected Faults ll , later in this chapter.

Trap System

Table 3.
Locations

Summary of Trap Locations (cont.)

Dec.

Hex.

Function

PSWs
Mask Bit

Time of Occurrence

Trap Condition Code

CALLl

None

At instruction decode.

Equal to R field of
CALL instruction.

CALL2

None

At instruction decode.

Equal to R field of
CALL instruction.

CALL3

None

At instruction decode.

Equal to R field of
CALL instruction.

CALL4

None

At instruction decode.

Equal to R field of
CALL instruction.

Hardware error trap

None

At time of basic processor detection (the PDFt flag wi II be set).

TCC1, 2, 3

TCC4 = 0 if parity
error on general register or internal control regi ster
TCC4 = 1 if other
hardware errors.
77

Instruction exception trap

None

(The PDFt flag wi II be set.)

Set TCC3 if MMC
configuration illegal;
set TCC = X'C' if
trap or interrupt sequence with illegal
instruction;
set TCC = X'F' if
trap or interrupt sequence and processor
detected fau I t;

I
78

Reserved

Power on

Interruptible point.

Power off

Interruptible point.

tSee "Processor Detected Faults", later in this chapter.

Trap System

set TCC4 if !nvalid
register designation
{odd register on AD,
SD, FAL, FSL, FML,
FDL.

a zero, the trap is not allowed to occur. AM can be
masked by operator intervention, or by execution of
the XPSD, PSS, PLS, or LPSD privi leged instructions.
3.

The floating-point significance check trap is masked
by a combination of the floating significance (FS),
floating zero (FZ), and floating normalize (FN) mode
control bits in the PSWs (see IIFloating-Point Arithmetic Fault Trapll, later in this chapter). FS, FZ, and
FN can be set or cleared by'the execution of any of
the following instructions:
LOAD CONDITIONS AND FLOATING CONTROL (LCF)
LOAD CONDITIONS AND FLOATING CONTROL IMMEDIATE (LCFI)
EXCHANGE PROGRAM STATUS WORDS (XPSD)

to immediately execute the XPSD or PSS instruction in
trap location X'40'. A nonallowed operation cannot be
masked.

NONEXISTENT INSTRUCTION
Any instruction that is not standard is defined as nonexistent. This includes immediate operand instructions that
specify indirect addressing (a one in bit 0 of the instruction).
If a nonexistent instruction is detected, the basic processor
traps to location X 140' when the nonexistent instruction is
decoded. No general registers or memory locations are
changed; the PSWs point to the instruction trapped. With
respect to the condition code and instruction address fields
of the program status words, the operation of the XPSD or
PSS in location X ' 40 ' is as follows:
1.

Store the current PSWs. The condition codes stored are
those that existed at the end of the last instruction
prior to the nonexistent instruction.

Store the 16 general registers of the current register
block if instruction in trap location is a PSS.

Load the new PSWs.

Modify the new PSWs.

LOAD PROGRAM STATUS WORDS (LPSD)
PUSH STATUS (PSS)
PULL STATUS (PLS)

TRAP CONDITION CODE
For the push-down stack limit trap, fixed-point overflow
trap, floating-point fault trap, and decimal fault trap, the
normal condition code register (CC1-CC4) is loaded with
more detai led information about the trap condition just
before the trap occurs. These condition codes are saved as
part of the old program status words when the XPSD or PSS
instruction is executed in response to the trap.
For the nonallowed operation trap, watchdog timer runout
trap, hardware error trap, instruction exception trap, and
CALL trap, a special register (trap condition codes TCC1TCC4) is loaded just before the trap occurs. When the
XPSD or PSS instruction is executed in response to the trap,
this register is added to the new program address if bit 9
(MM) contains a one; TCC1-TCC4 are also logically ORed
with the condition code bits (CC 1-CC4) of the new PSWs
when loading CC1-CC4. See also IIInstruction Exception
Trap" later in this chapter for more information on the trap
condition code.

Set CC 1 to one. The other condition code bits
remain unchanged from the vaiues ioooea from
memory.

If bit position 9 (AI) of the XPSD or PSS instruction contai ns a one, the program counter is incremented by eight. If AI contains a zero, the
program counter remains unchanged from the value
loaded from memory.

NONEXISTENT MEMORY ADDRESS
Any attempt to access a nonexistent memory address causes
a trap to location X'40 ' at the time of the request for memory service. A nonexistent memory address condition is
detected when an actual address is presented to the memory
system. If the basic processor is in the map mode, the
program address wi 1/ already have been modified by the
memory map to generate an actual (but nonexistent) address. (See Table 5 for possible changes to registers and
memory locations later in this chapter.) The operation of
the XPSD or PSS in location X'40' is as follows:

NONALLOWED OPERATION TRAP
The attempt to perform a nonallowed operation always
causes the basi c processor to abort the instruction being
executed when the nonallowed operation is detected and

Store the current PSWs.

Store general registers if PSS.

Trap System

Load the new PSWs.

Modify the new PSWs.
a.

Set CC2 to one. The other condition code bits
remain unchanged from the values loaded from
memory.

If bit position 9 (AI) of the XPSD or PSS instruction contains a one, the program counter is incremented by four. If AI contains a zero, the program
counter remains unchanged from the value loaded
from memory.

Load the new PSWs.

Modify the new PSWs.
a.

Set CC4 to one. The other condition code bits
remain unchanged from the values loaded from
memory.

If bit position 9 (AI) of the XPSD or PSS contains
a one, the program counter is incremented by one.
If AI contains a zero, the program counter remains
unchanged from the value loaded from memory.

WRITE LOCK VIOLATION
PRIVILEGED INSTRUCTION IN SLAVE MODE
An attempt to execute a privi leged instruction whi Ie the
basic processor is in the slave mode causes a trap to location X'40' before the privi leged operation is performed.
No general registers or memory locations are changed, and
the PSWs point to the instruction trapped. The operation
of the XPSD or PSS in trap location X'40' is as follows:

Store the current PSWs.

Store genera I registers if PSS.

Set CC3 to one. The other condition code bits
remain unchanged from the values loaded from
memory.

MEMORY PROTECTION VIOLATION
A memory protection violation occurs because of a memory
map access control bit violation (by a program executed
in slave mode or master-protected mode using the memory map). When memory protection violation occurs, the
basic processor aborts execution of the current instruction
without changing protected memory and traps to location
X'40'. Refer to Table 5 for possible changes to registers
and memory locations. (The virtual page address that caused
the vio!ation;$ in the fouith PSW v"oid.) The operation of
the XPSD or PSS in trap location X'40' is as fol lows:

Store the current PSWs.

Store general registers if PSS.

Load the new PSWs.

Modify the new PSWs.
a.

Set CC3 and CC4 to ones. The other condition
code bits remain unchanged from the values loaded
from memory.

If bit position 9 (AI) of the XPSD or PSS contains
a one, the program counter is incremented by
three. If Al contains a zero, the program counter
remains unchanged from the value loaded from
memory.

If bit position 9 (AI) of the XPSD or PSS contains
a one, the program counter is implemented by two.
If AI contains a zero, the program counter remains
unchanged from the values loaded from memory.

Load the new PSWs.
a.

A memory write lock violation occurs when an instruction
(program in master, master-protected,. or slave mode) tries
to alter the contents of a write-protected memory page. If
a write lock violation occurs, the basic processor aborts execution of the current instruction without changing protected
memory and traps to location X '40'. (Refer to Table 5 for
possible changes to registers and memory locations.) (The
virtual page address that caused the violation is the fourth
PSW word.) The operation of the X PSD or PSS in trap location X 140 1 is as follows:

PUSH-DOWN STACK LIMIT TRAP
Push-down stack overflow or underflow can occur during
execution of any of the following instructions:

Instructi on

Mnemonic

Push Word

PSW

Pull Word

PLW

Store the current PSWs.

Store general registers if PSS.

Trap System

Operation
Code

Instruction

Mnemonic

Operation
Code

Instruction

Mnemonic

Operation
Code

Push Multiple

PSM

X'OB '

Load Complement Word

LCW

X ' 3A '

Pull Multiple

PLM

X'OA'

Load Comp lement Doub Ieword

LCD

X ' 1A'

X ' 50 '

Modify Stack Pointer

X' 13 1

Add Halfword

MSP

Subtract Halfword

X '58 1

Divide Halfword

X ' 56 1

Add Immediate

X ' 20 '

Add Word

X ' 30 '

Subtract Word

Divide Word

X ' 38 1
X ' 36 1

Add Doubleword

X'10 '

Subtract Doub leword

Modify and Test Halfword

MTH

Modify and Test Word

MTW

X ' 18 1
X ' 53 1
X '33 1

Add Word to Memory

AWM

X '66 1

During the execution of any stack-manipulating instruction
(see Chapter 3, II Push-down Instructi ons II), the stack is
either pushed (words added to stack) or pulled (words removed from stack). In either case, the space (S) and words
0N) fields of the stack pointer doubleword are tested prior
to moving any words. If execution of the instruction would
cause the space (S) field to become les·s than 0 or greater
than 2 15 _1, the instruction is aborted with memory and
registers unchanged. If TS (bit 32) of the stack pointer
doubleword is set to 0, the basic processor traps to location
X'421. If TS is set to 1, the trap is inhibited and the basic
processor processes the next instruction. If execution of
the instruction would cause the words 0N) field to become
less than 0 or greater than 2 15 _1, the instruction is aborted
with memory and registers unchanged. If TW (bit 48) of
the stack pointer doubleword is set to 0, the basic processor
traps to location X'421. If the TW is set to 1, the trap is
inhibited and the basic processor processes the next instruction. If trapping is inhibited, CC 1 or CC3 is set to 1 to
indicate the reason for aborting the instruction. The stack
pointer doubleword, memory, and registers are modified
only if the instruction is successfully executed.

If a push-down instruction traps, the execution of XPSD or
PSS in trap location X' 42 1 is as follows:
1.

Store the current PSWs. The condition codes that are
stored are those that existed prior to execution of the
aborted push-down instruction.

Store general registers if PSS.

Load the new PSWs. The condition code and instruction address portions of the PSWs remain at the value
loaded from memory.

Except for the instructions DIVIDE HALFWORD (DH) and
DIVIDE WORD (OW), instruction execution is allowed to
proceed to completion. CC2 is set to 1 and CC3 and CC4
represent the actual result (0, -, or +) after overflow.
If the fixed-point arithmetic trap mask (bit 11 of PSWs) is
a 1, the basic processor traps to location X 143 1 instead of
executing the next instruction in sequence.
For DWand DH, the instruction execution is aborted without changing any register, and CC2 is set to 1; CC 1, CC3,
and CC4 remain unchanged from their values at the end of
the instruction immediately prior to the DW or DH. If the
fixed-point arithmetic trap mask is a 1, the basic processor
traps to location X ' 43 1instead of executing the next instruction in sequence.
The execution of X PSD or PSS in trap location X 143 1 is as
follows:
1.

Store the current PSWs. (Store genera I registers if PSS.)
If the instruction trapped was any instruction other than
DW or DH, the stored condition code is interpreted as
follows:
CC 1t
_tt

Overflow can occur for any of the following instructions:

Mnemonic

Load Absolute Word

LAW

Load Absolute Doubleword

LAD

FIXED-POINT OVERFLOW TRAP

Instruction

CC2 CC3 CC4 Meaning

Operation
Code

X' 1B '

Result after overflow is zero.
Result after overflow is
negative.

Result after overflow is
positive.

tcc 1 remains unchanged for instructions LCW, LAW, LCD,
and LAD.
tt A hyphen indicates that the condition code bits are not affected by the condition given under the "Meaning II heading.
Trap System

CClt

CC2 CC3 CC4 Meaning

If none of the above condi tions occurred but characteristic underflow occurs with floating zero mode
bit (FZ) = 1, the stored condition code is interpreted
as follows:

No carry out of bit 0 of the
adder (add and subtract instructions only).

CCl

Carry out of bit 0 of the
adder (add and subtract instructions only).

CC2 CC3 CC4 Meaning

If the instruction trapped was a OW or DH, the stored

condition code is interpreted as follows:
CCl

Characteri sti c underflow,
positive result.

CC2 CC3 CC4 Meaning

If none of the above conditions occurred but an addition or subtraction results in either a zero result (with
FS = 1 and FN = 0), or a postnormalization shift of
more than two hexadecimal places (with FS = 1 and
FN = 0), the stored condition code is interpreted as
follows:

Overflow
2.

Characteristic underflow,
negative result.

Load the new PSWs. The condition code and instruction address portions of the PSWs remain at the value
loaded from memory.

CCl

FLOATING-POINT ARITHMETIC FAULT TRAP
Floating-point fault detection is performed after the operation called for by the instruction code is performed, but
before any results are loaded into the general registers.
Thus, a floating-point operation that causes an arithmetic
fault is not carried to completion in that the original contents of the genera I reg isters are unchanged.

Instead, the basic processor traps to location X ' 44 with the
current condition code indicating the reason for the trap.
A characteristic overflow or an attempt to divide by zero
always results in a trap condition. A significance check or
a characteristic underflow results in a trap condition only
if the floating-point mode controls (FS, FZ, and FN) in the
current program status words are set to the appropriate state.

CC2 CC3 CC4 Meaning

Zero result of addition or
subtraction.
More than two postnormalizing shifts, negative result.

More than two postnormalizing shifts, positive result.

Load the new PSWs. The condition code and instruction address portions of the PSWs remain at the values
loaded from memory.

If a floating-point instruction traps, the execution of XPSD
or PSS in trap location X'44 1 is as follows:
1.

Store the current PSWs. (Store general registers if
r:>:>.)
if division is aTtempted with a zero divisor or
if characteristic overflow occurs, the stored condition
code is interpreted as follows:
CCl

CC2 CC3 CC4 Meaning

Zero divisor.
Characteristic overflow,
negative result.

Characteristic overflow,
positive result.

WATCHDOG TIMER RUNOUT TRAP
The watchdog timer monitors and controls the maximum
amount of basic processor time each instruction can take.
The timer is normally in operation at all times and is initialized at the beginning of each instruction. If the instruction
is not completed by the time the watchdog timer has completed its count, the instruction is aborted, TCCl is set to 0,
and a trap occurs immediately to location X ' 46 I • Additional
information as to probable cause of delay is provided:
TCC2 is set if the basic processor was using the processor
bus, TCC3 is set if the basic processor was using the memory
bus, TCC4 is set if the basic processor was using the DIO
bus. The register altered flag of the PSWs is also set if any
register or main memory !occt:on has beeil changed Vvheii
the trap occurred.

tCCl remains unchanged for instructions LCW, LAW, LCD,
and LAD.
ttA hyphen indicates that the condition code bits are not affected by the condition given under the "Meaning"heading.

Trap System

A watchdog timer runout is considered a basic processor
fault and the PDF is set. (See II Processor Detected Fault
Flag", later in this chapter.)

PROGRAMMED TRAP
The programmed trap occurs at instruction interruptible
point. It is set by a WRITE DIRECT 0ND). See Chapter 3.
The basic processor traps to location X'47'.

CALL INSTRUCTION TRAP
The four CALL instructions (CAll, CAL2, CAL3, and CAL4)
cause the basic processor to trap tp location X'48' (for
CAll), X'49' (for CAL2), X'4A' (for CAL3), or X'4B' (for
CAL4). Execution of the XPSD or PSS instruction in the
trap location is as follows:

Store the current PSWs. The stored condition code bits
are those that existed prior to the CALL instruction.

status register must be read with the LMS instruction. The
fault status register bit settings for processors and interfaces
are given in Appendix C, Table C-1. The fault status register bit settings for the memory unit are given in Appendix C, Table C-2.

If the basic processor detects or receives a report of a hardware error, it attempts automatic retry of the current instruction. If retry is unsuccessful, the basic processor traps
to location X'4C'. If retry is successful, the basic processor
resumes execution of the next instruction in the program,
the Processor Fault Interrupt (PFI) and the "successful instruction retry" bit (bit position 11) in the Basic Processor
Fault Status Register are set to 1. There is automatic instruction retry only for hardware errors that would otherwise
result in a basic processor trap to location X'4C'. Automatic instruction retry is inhibited if:
1.

The current instruction is being executed as a trap or
interrupt instruction;

The Register Altered bit (bit position 60) of the current PSWs is set to 1 at the time of detection of the
hardware error; or

The Retry Inhibit bit (bit position 0) in the basic processor control register is set to 1.

Store the general registers in PSS.

Load the new PSWs.

Modify the new PSWs.
a.

The R Field of the CALL instruction is logically
ORed with the condition code register as loaded
from memory.

If bit 9 (AI) of XPSD or PSS contains a 1, the R
field of the CALL instruction is added to the program counter. If AI contains a 0, the program
counter remains unchanged from the value loaded
from memory.

Note:

INSTRUCTION EXCEPTION TRAP
The instruction exception trap occurs whenever the basic
processor detects a set of operati ons that are ca II ed for in
an instruction but cannot be executed because of either a
hardware restri ction or a previous event.

Return from a CALL trap will be to the trapping
i nstructi on + 1.
The different conditions that cause the instruction exception
trap are:

A processor-detected fault that occurs during the execution of an interrupt or trap entry sequence. An
interrupt or trap entry sequence is defined as the sequence of events that consists of: (a) initiating an
interrupt or trap; (b) accessing the instruction in the
interrupt or trap location; and (c) executing that instruction, including the exchange of the program
status words, if required. Note that instructions executed as a result of the interrupt or trap location are
not considered part of the entry sequence.

An illegal instruction is found in the trap (not XPSD or
PSS) or interrupt (not XPSD, PSS, MTB, MTH, MTW) location when executing a trap or interrupt sequence.

Bit positions 12-14 of the MOVE TO MEMORY CONTROL (MMC) instruction are interpreted as an illegal

HARDWARE ERROR TRAP
A hardware error trap occurs when either'a parity or a sequence check fault error is detected by a memory unit, basic
processor, or any processor communicating with the basic
processor, resulting in a basic processor trap to location
X'4C'. The Trap Condition Code bits (TCCs) are set to
X'OOOl' for all hardware fault conditions except general
register and control register parity errors, where the TCCs
are set to X'OOOQ'.

To determine which of the possible detectable errors is responsible for the hardware error trap, the fault status registers of the various processors in the system must be polled
with either the POLP or POLR instruction; the memoris

Trap System

configuration. This is, any configuration other than
100, 010, 101, 001, or 011.

The set of operations, primarily doubleword instructions, that yield an unpredictable result when an incorrect register is specified; this type of fault is called
"invalid register designation" and includes the follow..
•
II t
Ing instructions •

POWER ON TRAP
Power On causes the basi c processor to reset and then trap
to location X '50 ' . This wi II occur only following restoration
of power after an interruption of less than 500 mi Iliseconds.

POWER OFF TRAP

Odd Register Specified

Power Off occurs at interruptible point. As source power is
going off, the basic processor traps to location X' 51 1 and
allows sufficient time for storage of information before the
system becomes inoperable.

Add Doubleword (AD)
Subtract Doubleword (SD)
Floating Add Long (FAL)
Floating Subtract Long (FSL)

PROCESSOR DETECTED FAULT FLAG
The Processor Detected Fault (PDF) flag aids in solving a
multiple error problem. Most traps occur because of a dynamic programming consideration (i. e., overflow, attempted
division by zero, incorrect use of an instruction or address,
etc.) and recovery is easi Iy handled by another software
subroutine. However, with certain classes of errors, if a
second error occurs while the basi c processor is attempting
to recover from the first error, unpredictable results occur.
Included in this class of traps are the hardware error trap,
some cases of the instruction exception trap, and the watchdog timer runout trap. Upon the first occurrence of this
type of trap, the PDF flag is set.

Floating Multiply Long (FML)
Floating Divide Long (FDL)
Move to Memory Control (MMC)

TRAP CONDITION CODE
The Trap Condition Code (TCC) differentiates between the
different fault types. Table 4 shows the settings of the TCC
for the various faults that may be detected during a trap or
interrupt entry sequence.
Table 4.

TCC Setting for Instruction Exception
Trap X'4D '

Fault Type

TCC

Trap or interrupt sequence and
processor-detected fault.

1 1 1 1

Trap or interrupt sequence wi th
invalid instruction.

When the PDF flag is set, the processor fault interrupt, the
memory fault interrupt, and count pulse interrupts are automatically inhibited. The other interrupts mayor may not
be inhibited as specified by the program status words, which
are loaded when the trap entry X PSD or PSS is executed.
The PDF flag is normally reset by the last instruction of a
trap routine, which is an LPSD or PLS instruction having
bit 10 equal to 0 and bit 11 equal to 1.

If a second PDF is detected before the PDF flag is reset, the

1 1 0 0

basic processor IIhangs up" until the PDF flag is reset either
by the operator entering the command for RESET BASIC
PROCESSOR or RESET SYSTEM on the operator's console.
This reset wi" cause the following actions:

MMC configuration invalid.

0 0 1 0

Invalid register designation

0 0 0 1

tllInvalid register designation" faults do not set the PDF
flag.

Trap System

The processor fault status register is cleared.

The PDF flag is cleared and the processor fault interrupt generated flag is cleared.

The PSWs are cleared to zero except that the instruction address is set to location X'26 1 •

The basic processor will begin execution with the instruction contained in location X'26 1 •

REGISTER ALTERED BIT
Complete recoverability after a trap may require that no
main memory location, no fast memory register, and no
part (or flags) of the PSWs be changed when the trap occurs.
If any of these registers or flags are changed, the Register
Altered bit (60) of the old PSWs is set to 1 and is saved by
the trap XPSD.
Changes to CC1-CC4 cause the Register Altered bit to be
set only if the instruction requires these condition code bits
as subsequent inputs.
Traps caused by conditions detected during operand fetch
and store memory cycles, such as nonexistent memory,

Table 5.

access protection violation, and memory parity error may
or may not leave registers, memory, and PSWs unchanged,
depending on when they occur during instruction execution. Generally, these traps are recoverable. This
is done by checking for protection violations and nonexistent memory at the beginning of execution in case
of a multiple operand access instruction, restoring the
original register contents if execution cannot be completed because of a trap, and not loading the first word of
the PSWs unti I a possible trap condition due to access of
the second word could have been detected. Table 5 contains a list of instructions and indicates for these instructions
what registers, memory locations, and bits of the PSWs, if
any, have been changed when a trap due to an operand access memory cycle occurs.

Registers Changed at Time of a Trap Due to an Operand Access

Instructions

Changes

AI, CI, LCFI, LI, MI

Immediate type, no operand access.

CALl-CAL4, SF, S, WAIT, RD, WD, RIO,
POLR, POLP

No operand access.

LRA

Has operand access but traps are suppressed; register bits and
condition codes are set instead.

LB, LCF, LRP, CB
LH, LAH, LCH, AH, SH, MH, DH, CH
LW, LAW, LCW, AW, SW, MW, DW, CW

No operand store, registers and PSWs unchanged when trap
due to operand fetch. CC 1-4 may be changed but are not
used as input to any of these instructions.

LD, LAD, LCD, AD, SD, CD, CLM, CLR
EaR, OR, AND, LS, INT, CS
FAS, FSS, FMS, FDS, FAL, FSL, FML, FDL

Registers and memory are preserved, condition codes may be
changed but are not used as input to these instructions.

AWM, XW, STS, MTB, MTH, MTW
STB, STCF, STH, STW, LAS

Memory wi II be altered and the Register Altered bit set.

EXU, BCR, BCS
BAL, BDR, BIR

If the branch condition is true (always for EXU and BAL) and
a trap occurs due to access of the indirect address or of the
next (branched to or executed) instruction, the register used
is left unchanged and the program address saved in the PSWs
is the address of the branch or execute instruction.

LM, STM, PLM, PSM, STD

Registers and memory may be changed and the Register Altered
bit set.

CVA, CVS

If a trap occurs, the instruction wi II be aborted before altering
registers. CC 1-4 may be changed but not used as input to any
of these instructions.

XPSD, LPSD, PSS, PLS

If a trap occurs due to storing the old PSWs or fetching the
new PSWs, the instruction is aborted before changing the old
PSWs.

SIO,

no,

If trap occurs, the instruction wi" be aborted without altering

TDY, HIO, Ala, RIO

condition codes, registers, or memory.
*ANLZ

An indirect ANALYZE instruction executed in the masterprotected mode wi II trap. No registers are altered.

Trap System

3. INSTRUCTION REPERTOIRE
This chapter describes the instructions, grouped in the
following functional classes:

load and Store

Ana Iyze and Interpret

Fixed-Point Arithmetic

Comparison

logical

Shift

Conversion

Floating-Point Arithmetic

Push Down

The instruction IS addressing type is one of the following:
a.

Byte index alignment: the reference address field
of the instruction (plus the displacement value)
can be used to address a byte in main memory or
in the current block of general registers.

Halfword index alignment: the reference address
field of the instruction (plus the displacement
value) can be used to address a halfword in main
memory or in the currentblockofgeneral registers.

Word-index alignment: the reference address field
of the instruction (plus the displacement value)
can be used to address any word in mai n memory
or in the current block of general registers.

Doubleword index alignment: the reference address field of the instruction {plus the displacement
value} can be used to address any doubleword in
main memory or in the current block of general
registers. The addressed doubleword is automatica"y located within doubleword storage
boundaries. (The low order bit of the reference
address is ignored.)

Immediate operand: the instruction word contains
an operand value used as part of the instruction
execution. If indirect addressing is attempted
with this type of instruction (i. e., bit 0 of the
instruction word is a 1), the instruction is treated
as a nonexistent instruction, and the basi c processor
unconditiona"yaborts execution of the instruction
(at the time of operation code decoding) and traps
to location X I 40', the "nonallowed operation"
trap. Indexing does not apply to this type of
instruction.

Immediate displacement: the instruction word
contains an address displacement used as part of
the instruction execution. If indirect addressing
is attempted with this type of instruction, the basic
processor treats the instruction as a nonexistent instruction, and it unconditionally aborts execution
of the instruction (at the time of operation code
decoding) and traps to location X'40'. Indexing
does not apply to this type of instruction.

10. Execute and Branch

11. Call
12. Control (privi leged)
13. Input/Output (privileged)

Instructions are described in the following format:

MNEMONICCD

INSTRUCTION NAME@
(Addressi ng Type@, Pri v i Ieged@ ,
Interrupt Action@)

01234567

Descriptionddress

10 11 12 13 14 15 16 17 18 19120 21 22 23 24 25 26 27128 29 30 31

Affected: (R)
EVA - R

Note:
If LCFI is indirectly addressed, it is treated as a nonexistent
instruction, in which case the computer unconditionally
aborts execution of the instruction (at the time of operation
code decoding) and traps to location X'40' with the condition code unchanged.

LOAD CONDITIONS AND FLOATING
CONTROL
(Byte index alignment)

15 31 ,

O-R _
O 14

Condition code is not affected by LVAW.

EXCHANGE WORD
(Word index alignment)

EXCHANGE WORD exchanges the contents of register R
wi th the contents of the effecti ve word location.
Affected: (R), (EWL), CC3, CC4
(R)-(EWL)

If bit position 10 of the instruction word contains a 1,

LOAD CONDITIONS AND FLOATING CONTROL loads
bits through 3 of the effective byte into the condition
code; however, if bit 10 is 0, the condition code is not
affected.

Condition code settings:
2

- If bit position 11 of the instruction word contains a 1, LCF
loads bits 4 through 7 of the effective byte into the floating
round (FR), floating significance (FS), floating zero (FZ),
and floating normalize (FN) mode control bits, respectively;
however, if bit 11 is 0, the FR, FS, FZ, and FN control
bits are not affected. The functions of the floating-point
mode control bits are described in the section "FloatingPoint Arithmetic Instructions".

- -

°°
°
°

STB

Result in R
Zero
Negative
Positive

STORE BYTE
(Byte index alignment)

Affected: CC, FR, FS, FZ, FN

If 0)10 = 1, EB _ -CC
O3
If (1) 10 = 0, CC not affected

STORE BYTE stores the contents of bit positions 24-31 of
register R into the effective byte location.

If (1)11 = 1, EB4-7 -

Affected: (EBL)

If (I) 11

= 0,

FR, FS, FZ, FN

FR, FS, FZ, FN not affected

Load/Store Instructions

LOAD VIRTUAL ADDRESS WORD loads bit positions 15-31
of register R with the effective virtual word address of the
instruction whi Ie bit positions 0-14 of register R are cleared
to zero.

(1)27

(1)24

LCF

(EB) 1

(R)24-31 -

EBL

STH

STORE HALFWORD
(Halfword index alignment)

Example 2, odd R field value:
Before execution

After execution

xxxxxxxxxxxxxxxx

X'89ABCDEF89ABCDEP

(R)
STORE HALFWORD stores tile contents of bit positions 16-31
of register R into the effective halfword location. If the
information in register R exceeds halfword data limits, CC2
is set to 1; otherwise, CC2 is reset·to O.

(EDL) =

STS

STORE SE LECTNE
(Word index alignment)

Affected: (EHL), CC2
(R)16-31- EHL
Condition code settings:
2
-

STW

Informati on in R
(R)0-16

= all O's or all l's.

(R)0-16

Register Ru 1 contains a 32-bit mask. If R is an even value,
STORE SE LECTIVE stores the contents of register R into the
effective word location in those bit positions selected by
a 1 in corresponding bit positions of register Ru1; the effective word remains unchanged in those bit positions selected
by a 0 in corresponding bit positions of register Rul.

all O's or all l's.
If R is an odd value, STS logically inclusive ORs the contents of register R with the effective word and stores the
result into the effective word location. The contents of
register R are not affected.

STORE WORD
(Word index al.ignment)

Affected: (EWL)
o

If R is even, [(R)n(Rul)] u [EWn(Rul)] - - EWL
STORE WORD stores the contents of register R into the effective word location.

If R is odd, (R) u EW -

Affected: (EWL)

Example 1, even R field value:

(R) -EWL

STO

STORE DOUBLEWORD
(Doubleword index alignment)

EWL

Before executi on

After execution

(R)

X'12345678'

(Ru1 )

X' FOFOFOFO'

xxxxxxxx

X'lx3x5x7x'

Example 2, odd R field value:
STORE DOUBLEWORD stores the contents of register R into
the 32 hi gh-order bi t positions of the effecti ve doubleword
location and then stores the contents of register Ru 1 into
the 32 low-order bit positions of the effective doubleword
location.

Before execution

After execution

(R)

X'OOFFOOFF'

X'OOFFOOFF '

X'12345678'

C' 12FF56FF'

Affected: (EDL)
(R)·-- EDL _ ; (RuH O 31

EDL

_
32 63

STM

STORE MULTIPLE
(Word index alignment)

Example 1, even R field value:
Before execution

After execution

(R)

X'01234567'

(Ru1 )

X'89ABCDEF'

X' 89ABCDEF'

xxxxxxxxxxxxxxxx

X'O 123456789ABCDEF'

(EDL)

STORE MULTIPLE stores the contents of a sequential set of
registers into a sequential set of word locations. The set of
locations begins with the location pointed to by the effective
word address of STM, and the setof registers begins with register R. The set of registers is treated modulo 16 (i. e. f the

Load/Store Instructions

next sequential register after register 15 is register 0). The
number of registers to be stored is determined by the value
of the condition code immediately before execution of STM.
(The condition code can be set to the desired value before
execution of STM with LCF or LCFI.) An initial value
of 0000 for the condition code causes 16 general registers
to be stored.

Table 6.
Xln l

ANALYZE Table for Operation Codes

XIOOI+n

X' 20 ' +n

X ' 40 ' +n

X ' 60 ' +n

AI
CI

=CD
-

01
02
03

04
05

SF
S
LAS

CAll
CAL2
CAL3
CAL4

08
09
OA
OB

PLW
PSW
PLM
PSM

CYS

OC
OD
OE
OF

LCFICV

Affected: (EWL) to (EWL+CC-l)
(R)-EWL, (R+l)- EWL+1, ... , {R+CC-l)-EWL+CC-1

ANLZ
CS
XW
STS

BDR
BIR
AWM
EXU

CYA tt
LM@
STM

EOR
OR
LS
AND

BCR
BCS
BAL
INT

t
PLS
psst
LPSDt@tt
t
XPSD

LRAt
LMst
WAITt
LRPt

SlOt
not
TDyt
HIOt

RDt
WDt
AIOt
t
MMC

AD
CD
LD
MSP

SW
CW
LW
MTW

AH
CH
LH
MTH

LCF
CB
LB
MTB

14
15
16
17

STCF
STB

LYAW
STW
DW
MW

18
19
1A
1B

SD
CLM
LCD
LAD

SW
CLR
LCW
LAW

06
The STM instruction may cause a trap if its operation extends into a page of memory that is protected by the access
protection codes or the write locks. A trap may also occur
if the operation extends into a nonexistent memory region.
If the effective virtual address of the STM instruction is in
the range 0 through 15, then the registers indicated by the
R field of the STM instruction are stored in the general registers rather than main memory. In this case, the results
will be unpredictable if any of the source registers are also
used as destination registers.

STCF

STORE CONDITIONS AND FLOATING
CONTROL
(Byte index alignment)

10
11
12
13

STORE CONDITIONS AND FLOATING CONTROL stores
the current condition code and the current value of the
floating round (FR), floating significance (FS), floating
zero (FZ), and floating normalize (FN) mode control bits
of the program status words into the effective byte location
as follows:

Affected: (EBL)

I
Reference address

A I

rAt"
rM~

lE
IF

FDL
FML

FDS
FMS

LCH
LAH

10 11 12 13 14 15116 17 18 19120 2' 22 23/24 25 26 27/28 29 30 31

ANALYZE evaluates the effective word as an instruction.
The ANALYZE instruction always sets the condition codes
to indicate the addressing type of the analyzed instruction
(see condition code settings and Table 6). Except when

FSS

rML

tt Decimal value of condition code settings when analyzed instruction calls for direct addressing. If analyzed instruction calls for indirect addressing, add 2
to the va Iue shown.

ANALYZE
(Word index alignment)

II
R " X !
o

FSL

STH
DHG)tt

tp··1
.
nVI ege d·inS t ruchons.

ANALVZE/INTERPRET INSTRUCTIONS
ANLZ

1C
,1"'\

(PSWs)0_7 -EBL

STD

Anaiyze/lnterpret Instructions

the analyzed instruction is an immediate operand instruction, an effective virtual address for the analyzed
instruction is also calculated and loaded into register R.

The nonexistent instruction, the privi leged instruction
violation, and the unimplemented instruction trap conditions
can never occur during execution of the AN LZ instruction.
However, either the nonexistent memory address condition
or the memory protection violation trap condition (or both)
can occur as a result of any memory access initiated by the
ANLZ instruction. If either of these trap conditions occurs,
the instruction address stored by an XPSD in trap location
X' 40 ' is always the virtual address of the AN LZ instruction.

Halfword Addressing: MA=l, MM=O

The detai led operation of ANALYZE is as follows:

Word Addressing: MA=l, MM=O

The contents of the location pointed to by the effective
virtual address of the AN LZ instruction is obtained.
This effective word is the instruction to be analyzed.
From a memory-protection viewpoint, the instruction
(to be analyzed) is treated as an operand of the ANLZ
instruction; that is, the analyzed instruction may be
obtained from any memory area to which the program
has read access.

Word Addressing: MA=O

Doubleword Addressing: MA=O

Doubleword Addressing: MA=l, MM=O
2.

If the operation code portion of the effective word
specifies an immediate-addressing instruction type, the
condition code is set to indicate the addressing type,
and instruction execution proceeds to the next instruction in sequence after AN LZ. The original contents of register R are not changed when the analyzed
instruction is of the immediate-addressing type.
If the operation code portion of the effective word
specifies a reference-addressing instruction type, the
condition code is set to indicate the addressing type
of the analyzed instruction and the effective address
of the analyzed instruction is computed (using all of
Tne normai address compuTaTion ruies). if biT 0 of tne
effective word is a 1, the contents of the memory location specified by bits 15-31 of the effective word
are obtained and then used as a direct address. The
nonallowed operation trap (memory protection violation or nonexistent memory address) can occur as a
result of the memory access. Indexing is always performed (with an index register in the current register
block) if bits 12-14 of the analyzed instruction are
nonzero. During real extended addressing, the effective virtual address of the analyzed instruction is
aligned as an integer displacement value and loaded
into register R, according to the instruction addressing
type, as follows:

When the ANALYZE instruction is executed in the masterprotected mode and a trap condition occurs, it traps only
on an indirect ANALYZE. Otherwise, instead of trapping
it completes its execution by storing in register R the address that would have caused the instruction to trap. Since
the mode is master-protected, the access protection codes
wi II apply to the interpretation of addresses. If a slave
mode program is trapped because an instruction has referenced protected memory, the ANALYZE instruction in the
master-protected mode can determine which address aCTuai iy
caused the trap.
To aid the interpreting program, when operating in the
master-protected mode, the AN LZ instruction uses bits 1, 2,
and 3 of register R to indicate which memory access initiated
by the AN LZ would have trapped. The meaning of the possible codes in register R(1-3) is as follows:
Register R Bits
R1

Meaning

Successful generation of the effective virtual
address of the analyzed instruction. The CCs
are set to the addressing type of the analyzed
instruction and R(10-31) contain the effective
virtual address of the analyzed instruction
aligned as an integer displacement value according to the instruction addressing type.

Byte Addressing: MA=O

Byte Addressing: MA=l, MM=O

Halfword Addressing: MA=O

The indirect reference of the analyzed instruction would have trapped because it was either
nonexistent, memory protected, or had a
parity error. The CCs are set to the addressing type of the analyzed instruction and
R(10-31) contain the virtual address of the indirect reference of the analyzed instruction
aligned as a word displacement.

Ana Iyze/Interpret Instructions

Meaning

The effective virtual address of the AN lZ
instruction would have trapped because it was
either nonexistent, memory protected, or had
a parity error. The CCs are indeterminate
since the instruction to be analyzed may not
have been fetched (nonexistent memory).
R(l0-3l) contain the effective virtual address
of the AN lZ i nstructi on a Ii gned as a word
displacement.

If no trap condition occurs, ANlZ will execute normally
and return the effective address of the instruction analyzed.

effective word into bit positions 20-31 of register R (and
clears the remaining bits of register R). If R is an odd value,
INT loads bits 0-3 of the effective word into the condition
code, loads bits 16-31 of the effective word into bit positions 16-31 of register R, and loads OIS into bit positions 0-15 of register R (bits 4-15 of the effective word are
ignored in this case).
Affected: (R), (Ru1), CC
EW _ -CC
O3
EW4 _15 _R20_31iO- RO- 19
EW 16-31- Ru116_31iO -

Table 6 shows the instruction set as a 4 by 32 matrix {arranged as a function of the operation code}. This table also
shows how the instruction set is divided into six groups as
a function of the addressing type (delineated by heavy
lines). For example, if the operation code of the analyzed
instruction is either X' 02 1 , X' 20', X' 21 1 , X ' 22 1 , or X' 23 1 ,
then CCI is set to 1, CC2 is set to 0, CC3 is set to 0 (when
analyzed instruction specifies direct addressing), and CC4
is set to 1. The decimal equivalent of the condition code
setting for this group of immediate, word addressing type of
instructions is shown as a 9 within a circle. The decimal
equivalents of the candition code settings for the other
five groups are shown in the same manner. If the analyzed
instruction calls for indirect addressing, CC3 is always set
to a 1 and the decimal value of the condition code setting
shown in Table 6 should be increased by 2.
Affected: (R), CC

Ru1 0 _ 15

Condition code settings:

Example 1, even R field value:
Before execution

After execution

XI 12345678 1

(R)

xxxxxxxx

XI 00000234 1

(Ru 1) = xxxxxxxx

XI000056 78 1

xxxx

0001

Condition code settings:
2

Instruction addressing type

Byte

Halfword

Word

Immediate, word

Doubleword

Direct addressing (EWO

Indirect addressing (EWO = 1)

0
0
0

I"'"'

OB
2

3 14

I _ I

I{
9

I
X I

I
Reference address

Mnemonic

Add Immediate

Add Halfword

Add Word

Add Doubleword

Subtract Halfword

Subtract Word

Subtract Doubleword

iviuitipiy immediate

Multiply Halfword

Multiply Word

Divide Halfword

10 11 12 13 14 15116 17 18 19120 21 22 23124 25 26 27128 29 30 31

INTERPRET loads bits 0-3 of the effective word into the
condition code, loads bits 16-31 of the effective word into
bit positions 16-31 of register Ru1 (and loads OIS into bit
positions 0-15 of register Ru1, loads bits 4-15 of the

Instruction Name

= 0)

INTERPRET
(Word index alignment)

I .I
1

The fixed-point arithmetic instructions are:

Immediate, byte

INT

FIXED-POINT ARITHMETIC INSTRUCTIONS

Fixed-Point Arithmetic Instructions

Instruction Name

Mnemonic

Divide Word

Add Word to Memory

AWM

Modi fy and Test Byte

MTS

Modify and Test Halfword

MTH

Modify and Test Word

MTW

ADD IMMEDIATE
{Immediate operand}
20

The fixed-point arithmetic instruction set performs binary
addition, subtraction, multiplication, and division with
integer operands that may be data, addresses, index values,
or counts. One operand may be either in the instruction
word itself or may be in one or two of the current general
registers; the second operand may be either in main memory
or in one or two of the current general registers. For most
of these instructions, both operands may be in the same
general register, thus permitting the doubling, squaring,
or clearing the contents of a register by using a reference
address value equal to the R field value.
All fixed-point arithmetic instructions provide a condition
code setti ng that i ndi cates the fo Ilowi ng information about
the result of the operation called for by the instruction:

The value field (bit positions 12-31 of the instruction word)
is treated as a 20-bit, two's complement integer. ADD
IMMEDIATE extends the sign of the value field (bit position 12 of the instruction word) 12 bit positions to the left,
adds the resulting 32-bit value to the contents of register R,
and loads the sum into regi ster R.
Affected: (R), CC
(R) + (I)12-31SE -

Condition code settings:
2

Result in R

Zero

Negative

o
- 0

Result

·Zero - the result in the specified general
register(s) is all zeros.

Positive
No fixed-point overflow
Fixed-point overflow

Condition code settings:
2

Trap: Fixed-point overflow,
or nonexistent instruction if bit 0 is a 1.

No carry from bit position 0
-

l.nrrv
frnm
hit
noc;itinn 0
- I
- ,--

If AI is indirectly addressed, it is treated as a nonexistent
-

Negative - the instruction has produced a
fixed-point negative result.

Positive - the instruction has produced a
positi ve resu It.

instruction, in which case the BP unconditionally aborts
execution of the instruction (at the time of operation code
decoding) and traps to location X'40' with the contents of
register R and the condition code unchanged.

fj xed -po in t

- 0

Fixed-point overflow has not occurred during
execution of an add, subtract, or divide instruction, and the result is correct.
Fixed-point overflow has occurred during
execution of an add, subtract, or divide instruction. For addition and subtraction, the
incorrect result is loaded into the designated
register{s}. For a divide instruction, the
designated register(s), and CC1, CC3, and
CC4 are not affected.

No carry - for an add or subtract instruction,
there was no carry of a l-bit out of the highorder (sign) bit position of the result.
-

Carry - for an add or subtract instruction,
there was a l-bit carry out of the sign bit
position of the result. (Subtracting zero wi II
a Iways produce carry. )

If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.

ADD HALFWORD
(Halfword index alignment)

ADD HALFWORD extends the sign of the effective halfword
16 bit positions to the left (to form a 32-bit word in which
bit positions 0-15 contain the sign of the effective halfword), adds the 32-bit result to the contents of register R,
and loads the sum into register R.
Affected: (R), CC

Trap: Fixed-point overflow

(R) + EHSE-R
Fixed-Point Arithmetic Instructions

Condition code settings:
2

Result in R

0 0

Zero

Negative

- 0

Positive
No fixed-point overflow
Fixed-point overflow

ADD DOUBlEWORD
(Doub/eword index alignment)

ADD DOUBlEWORD adds the effective doubleword to the
contents of registers Rand Ru1 (treated as a single, 64-bit
register); loads the 32 low-order bits of the sum into regi ster Ru 1 and then loads the 32 high -order bits of the sum
into register R. R must be an even value; if R is an
odd value, the BP traps with the contents in register R
unchanged.

No carry from bit position 0
Carry from bit position 0

Affected: (R), (Ru 1), CC
(R, Ru1) + ED -

Trap: Fixed-pointoverf/ow,
instruction exception

R, Ru1

If CC2 is set to 1 and the fixed-point arithmetic trap mask
is 1, the BP traps to location X ' 43 1 after loading the
sum into regi ster R; otherwise, the BP executes the next
instruction in sequence.

Condition code settings:

ADD WORD
0/Vord index alignment)

0 0

Zero

Negative

0
o

- 0

Positive
No fixed-point overflow

ADD WORD adds the effective word to the contents of register R and loads the sum into register R.

Fixed-point overflow

o
Affected: (R), CC

Result in R, Ru1

No carry from bit position 0

Trap: Fixed-point overflow
Carry from bit position 0

(R) + EW-R
Condition code settings:
2

0 0

Zero

Negative

Result in R

Positive
No fixed-point overflow

If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X ' 43 1 after loading
the sum into registers Rand Ru1; otherwise, the BP executes the next instruction in sequence.
The R field of the AD instruction must be an even value for
proper operation of the instruction; if the R fie Id of AD is
an odd value, the instruction traps to location X'4D',
instruction exception trap.
Example 1, even R field value:

Fixed-point overflow

No carry from bi t posi tion 0

Before execution

After execution

X ' 33333333EEEEEEEE'

X'33333333EEEEEEEE '

(R)

X l ll 11 11 111

X144444445 1

(Ru 1)

X'33333333 1

X' 22222221 '

xxxx

0010

Carry from bit position 0

If CC2 is set to T and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43 1 after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.

Fixed-Point Arithmetic Instructions

SUBTRACT HALFWORD
(Halfword index alignment)

SUBTRACT HALFWORD extends the sign of the effective
halfword 16 bit positions to the left (to form a 32-bit word
in which bit positions 0-15 contain the sign of the effective halfword), forms the two's cQmplement of the resulting
word, adds the complemented word to the contents of register R, and loads the sum into register R.

Result in R

Positive

No fixed-point overflow

Fixed-point overflow

o - - -

No carry from bit position 0
Carry from bit position 0

If CC2 is set to 1 and the fixed-point arithmetic trap mask
Affected: (R), CC
-EH

Trap: Fixed-point overflow

+ (R)-R

Condition code settings:
2

Resu It in R

Zero

Negative

Positive
No fixed-point overflow
Fixed-point overflow

o -

No carry from bit position 0
-

(AM) is a 1, the BP traps to location X'43' after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.

Carry from bit position 0

SUBTRACT DOUBLEWORD
(Doubleword index alignment)

'SUBTRACT DOUBLEWORD forms the 64-bit two's complement of the effective doubleword, adds the complemented
doubleword to the contents of registers Rand Ru1 (treated
as a single, 64-bit register), loads the 32 low-order bits of
the sum into register Ru 1 and loads the 32 hi gh -order bits
of the sum into register R.
Affected: (R), (Rul), CC
-ED + (R, Ru1) -

Trap: Fixed-point overflow,
instruction exception

R, Ru1

Condition code settings:
If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after loading
the sum into register R; otherwise, the BP executes the
next instruction in sequence.

Result in R, Ru1

Zero

- 0

SUBTRACT WORD
(Word index alignment)

- 0
o

Negative

Positive

No fixed-point overflow

314567891011121314151617181912021222324252627128293031

Fixed-point overflow
SUBTRACT WORD forms the two's complement of the effective word, adds that complement to the contents of register R, and loads the sum into register R.
Affected: (R), CC

o -

No carry from bit position 0

Carry from bit position 0

Trap: Fixed-point overflow

If CC2 is set to 1 and the fixed-point arithmetic trap mask
-EW + (R)-R
Condition code settings:
2

Resu It in R

Zero

Negative

(AM) is a 1, the BP traps to location X' 43 1 after the result is loaded into registers Rand Ru1; otherwise, the BP
executes the next instruction in sequence.
The R field of the SD instruction must be an even value for
proper operation of the instruction; if the R field of SD is
an odd value, the instruction traps to location X'4D',
instruction exception trap; the contents in register R remain
unchanged.

Fixed-Point Arithmetic Instructions

Example 2, odd R field value:

MULTIPLY IMMEDIATE
(Immediate operand)

The value field (bit positions 12-31 of the instruction word)
is treated as a 20-bit, two's complement integer. MULTIPLY
IMMEDIATE extends the sign of the value field (bit position 12) of the instruction word 12 bit positions to the left
and multiplies the resulting 32-bit value by the contents
of register Ru1, then loads the 32 high-order bits of the
product into register R, and then loads the 32 low-order
bits of the product into register Ru 1.

If R is an odd value, the result in register R is the 32 loworder bits of the product. Thus, in order to generate a
64-bit product, the R field of the instruction must be even
and the multiplicand must be in register R+1. The condition code settings are based on the 64-bit product formed
during instruction execution, rather than on the final contents of register R. Overflow cannot occur.
Affected: (R), (Ru 1), CC2,
CC3, CC4

Trap: Nonexistent instruction if bit 0 is a 1.

(Rul) x (I)12-31SE - R , Ru1

Before execution

After execution

(1)12-31

X'01234'

(R)

X'00030002'

X'369C2468'

xxxx

x010

MULTIPLY HALFWORD
(Halfword index alignment)

MULTIPLY HALFWORD multipl ies the contents of bit positions 16-31 of register R by the effective halfword (with
both halfwords treated as signed, two's complement integers) and stores the product in register Ru 1 (overflow cannot
occur). If R is an even value, the original multiplier
in register R is preserved, allowing repetitive halfword
r:nultiplication with a constant multiplier; however, if R is
an odd value, the product is loaded into the same register.
Overflow cannot occur.
Affected: (Rul), CC3, CC4

Condition code settings:
2

64-bi t product

Zero.

(R)16-31 x EH -Ru1
Condition code settings:

o
o

Result in Ru1

Zero

Positive
Result is correct, as represented in register Ru 1.
Result is not correctly representable in register Ru 1 alone.

If MI is indirectly addressed, it is treated as a nonexistent
instruction, in which case the BP unconditionally aborts
execution of the instruction (at the time of operation code
decoding) and traps to location X'40' with the contents
of register R, register Ru 1, and the condition code unchanged; otherwise, the BP executes the next instruction
in sequence.
Example 1, even R field value:
Before execution

After execution

X'70000'

(R)

xxxxxxxx

X' 00007000'

(Ru 1)

X'10001000'

xxxx

(I) 12-31

2
Negative.

Negative

Positive

Example 1, even R fieid value:

X'FFFF'

(R)

X' xxxxOOOA'

X' xxxxOOOA '

(Ru 1)

xxxxxxxx

X'FFFFFFF6'

xxxx

xx01

Example 2, odd R field value:
Before execl)tion

After execution

X'FFFF'

X' 70000000'

(R)

X' xxxxOOOA '

X'FFFFFFF6'

x110

xxxx

xxOl

Fixed-Point Arithmetic Instructions

MULTIPLY WORD
0/'Iord index alignment)

MULTIPLY WORD multiplies the contents of register Rul
by the effective word, loads the 32 high-order bits of
the product into register R and then loads the 32 loworder bits of the product into register Rul {overflow cannot
occur}.

Condition code settings:
2

Result in R

Zero quotient, no overflow.

Negative quotient, no overflow.

- 0

Positi ve quoti ent, no overflow.
Fixed-point overflow.

If CC2 is set to 1 and the fixed-point arithmetic trap mask
If R is odd value, the result in register R is the 32 loworder bits of the product. Thus, in order to generate a
64-bit product, the R field of the instruction must be even
and the multiplicand must be in register R+l. The condition code settings are based on the 64-bit product formed
during instruction execution, rather than on the final contents of register R.

(AM) is a 1, the BP traps to location XI 43 1 with the contents of register R, CC1, CC3, and CC4 unchanged.

DIVIDE WORD
(yVord index alignment)

Affected: (R), (Ru 1), CC
DIVIDE WORD divides the contents of registers Rand Ru 1
(treated as a 64-bit fixed-point integer) by the effective
word, loads the integer remainder into register R and then
loads the integer quotient into register Rul. If a nonzero
remainder occurs, the remainder has the same sign as the
dividend (original contents of register R). If R is an odd
value, DW forms a 64-bit register operand by extending
the sign of the contents of register R 32 bit positions to the
left, then divides the 64-bit register operand by the effective word, and loads the quotient into register R. In this
case, the remainder is lost and only the contents of register R are affected.

(Rul) x EW-R, Rul
Condi ti on code setti ngs:
2

64-bi t product

Zero.

Negative.

Positive.

If the absolute value of the quotient cannot be correctly
-

Result is correct, as represented in register Ru 1.

Result is not correctly representable in register Rul alone.

DIVIDE HALFWORD
(Halfword index alignment)

represented in 32 bits, fixed-point overflow occurs; in
which case CC2 is set to 1 and the contents of register R,
register Rul, CC1, CC3, and CC4 remain unchanged;
otherwise, CC2 is reset to 0, CC3 and CC4 reflect the
quoti ent in regi ster Ru 1, and CC 1 is unchanged.
Affected: (R), (Rul), CC2
CC3,CC4

Trap: Fixed-point overflow

(R, Rul) -:- EW- R (remainder), Rul (quotient)
Condition code settings:

DIVIDE HALFWORD divides the contents of register R
(treated as a 32-bit fi xed-point integer) by the effective
halfword and loads the quotient into register R. If the
absolute value of the quotient cannot be correctly represented in 32 bits, fixed-point overflow occurs; in which
case CC2 is set to 1 and the contents of register R, and
CC1, CC3, and CC4 are unchanged.
Affected: (R), CC2, CC3, CC4
(R) -:- EH-R

Resu Itin Ru 1

Zero quotient, no overflow.

- 0 0
- 0

Negative quotient, no overflow.

0 Positive quotient, no overflow.
Fixed-point overflow.

Trap: Fixed-pointoverflow

If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location XI 43 1 with the
Fixed-Point Arithmetic Instructions

original contents of register R, register Rul, CC1, CC3,
and CC4 unchanged; otherwise, the BP executes the next
instruction in sequence.

AWM

ADD WORD TO MEMORyt
0/Vord index alignment)

the R field. This byte is added to the effective byte and
then (if no memory protection violation occurs) the sum is
stored in the effective byte location and the condition code
is set according to the value of the resultant byte. This
process allows modification of a byte by any number in the
range -8 through +7, followed by a test.

If the value of the R field is zero, the effective byte is

ADD WORD TO MEMORY adds the contents of register R
to the effective word and stores the sum in the effective
word location. The sum is stored regardless of whether or
not overflow occurs.
Affected: (EWL), CC

tested for being a zero or nonzero value. The condition
code is set according to the result of the test, but the
effective byte is not affected. A memory write-protection
vioiation cannot occur in this case; however, a memory
read-protection violation can occur.
Affected: CC if (1)8-11 -I 0
(EBL) and CC if (1)8-11

If (1)8_11/0, EB + (1)8-11 SE -

EBL and set CC

Trap: Fixed-pointoverflow

EW + (R)-EWL

If (1)8-11

= 0,

test byte and set CC

Condition code settings:
2

Result in EWL

Zero

Negative

o
- 0

Positive
No fixed-point overflow

Condition code settings:

Result in EBL

Zero

Nonzero

- 0

No carry from byte
-

Fixed-point overflow

No carry from bit position 0
-

Carry from bit position 0

Carry from byte

If MTB is executed in an interrupt or trap location, the
condition code is not affected and a 20-bit reference address is used, as descri bed under "Interrupt and Trap Entry
Addressing II, Chapter 2.

If CC2 is set to 1 and fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after the result is stored in the effective word location; otherwise, the
BP executes the next instruction in sequence.

MTB

MODIFY AND TEST BYTE t
(Byte index alignment)

Note: All "Modify and Test" instructions in interrupt locations other than Counter 4 use real, or real extended,
addressing mode. Counter 4 uses virtual addressing
mode.

H
If the value of the R field is nonzero, the high-order bit of
the R field (bit position 8 of the instruction word) is extended 4 bit positions to the left, to form a byte with bit
positions 0-4 of that byte equal to the high-order bit of

tThis instruction requires two memory references to the same
location for its execution. To preclude other processors
from accessing the effective location during this time, the
memory unit containing the effective location is reserved
(not accessible to other processors) unti I the instruction is
completed.

Fixed-Point Arithmetic Instructi ons

MODIFY AND TEST HALFWORD t
(Halfword index alignment)

MTH

3 14

10 11

12 13 ·14 15 16 17 18 19! 20 21 22 23 24 25 26 27128 29 30 31

If the value of the R field is nonzero, the high-order bit
of the R field (bit position 8 of the instruction word) is extended 12 bit positions to the left, to form a halfword with
bit positions 0-11 of that halfword equal to the high-order
bit of the R field. This halfword is added to the effective
halfword and then (if no memory protection violation occurs) the sum is stored in the effective halfword location
and the condition code is sP,t according to the value of the
resultant halfword. The sum is stored regardless of whether
or not overflow occurs. This process allows modification of
a halfword by any number in the range -8 through +7, followed by a test.

If the value of the R field is zero, the effective halfword
is tested for being a zero, negative, or positive value.
The condition code is set, according to the result of the
test, but the effective halfword is not affected. A memory
write-protection violation cannot occur in this case; however, a memory read-protection violation can occur.
Affected: CC if (1)8-11 = 0;

Trap: Fixed-pointoverflow

(EHL) and CC if (1)8-11/0
If (1)8-11

= 0,

test ha Ifword and set CC

If (1)8-11/0, EH + (I)8-11SE -EHL and set CC

of the R field. This word is added to the effective word
and then (if no memory protection violation occurs) the
sum is stored in the effective word location and condition
code is set according to the value of the resultant word.
The sum is stored regardless of whether or not overflow
occurs. This process allows modification of a word by
any number in the range -8 through +7, followed by
a test.

If the value of the R field is zero, the effective word is
tested for being a zero, negative, or positive value. The
condition code is set according to the result of the test,
but the effective word is not affected. A memory writeprotection violation cannot occur in this case; however,
a memory read-protection violation can occur.

Condition code settings:
Trap: Fixed-pointoverflow

Affected: CC if (1)8-11 = 0;
2

3 4

Result in EH L

(EWL) and CC if (1)8-11

Zero
Negative

If (1)8-11

= 0,

test word and set CC

If (1)8-11

10,

EW + 18-11 SE -

EWL and set CC

Positive
Condition code settings:

No fixed-point overflow
Fixed-point overflow

3 4

Zero

No carry from halfword
-

Negative

Carry from halfword
0

If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after the re-

sult is stored in the effective halfword location; otherwise,
the BP executes the next instruction in sequence.

If MTH is executed in an interrupt or trap location, the
condition code is not affected and a 20-bit reference address is used, as described under "Interrupt and Trap Entry
Addressi ng", Chapter 2.

MTW

Result in EWL

MODIFY AND TEST WORD
(Word index alignment)

If the value of the R field is nonzero, the high-order bit
of the R fie Id (bit position 8 of the instruction word) is
extended 28 bit positions to the left, to form a word with
bit positions 0-27 of that word equal to the high-order bit

Positive
No fixed-point overflow
Fixed-point overflow

No carry from word
Carry from word

If CC2 is set to 1 and the fixed-point arithmetic trap mask
(AM) is a 1, the BP traps to location X'43' after the result is stored in the effective word location; otherwise, the
BP executes the next instruction in sequence.
If MTW is executed in an interrupt or trap location, the
condition code is not affected and a 20-bit reference address is used, as described under "Interrupt and Trap Entry
Addressing", Chapter 2.

COMPARISON INSTRUCTIONS
The comparison instructions are:
tThis instruction requires two memory references to the same
location for its execution. To preclude other processors
from accessing the effective location during this time, the
memory unit containing the effecti ve location is reserved
{not accessible to other processors} unti I the instruction is
completed.

Instruction Name

Mnemonic

Compare Immedi ate

Compare Byte

Comparison Instructions

Instruction Name

Mnemonic

Compare Halfword

Compare Word

Compare Doub Ieword

Compare Selective

Compare With Limits in Register

CLR

Compare With Limits in Memory

CLM

COMPARE BYTE
(Byte index alignment)

COMPARE BYTE compares the contents of bit positions 24-31
of register R with the effective byte (with both bytes treated
as positive integer magnitudes) and sets the condition code
accordi ng to the resu Its of the compari son.
Affected: CC2, CC3, CC4
(R)24-3I : EB

All comparison instructions produce a condition code
setting which is indicative of the results of the comparison, without affecting the effective operand in memory and wi thout affecti ng the contents of the desi gnated
register.

Condition code settings:
2

Result of Comparison

Equal.

COMPARE IMMEDIATE
(Immediate operand)

o
-

COMPARE IMMEDIATE extends the sign of the value field
(bi t posi tion 12) of the instruction word 12 bi t posi ti ons to
the left, compares the 32-bit result with the contents of
register R (with both operands treated as signed fixed-point
quantities), and then sets the condition code according to
the results of the comparison.
Affected: CC2, CC3, CC4

Trap: Nonexistent instruction if bit 0 is a 1.

(R) : (I)12-31SE

Condition code settings:

2 3

Resu it of Com pari son

Equal.

One or more I-bits compare,
(R)24-31 n EB

10.

COMPARE HALFWORD
(Halfword index alignment)

H
o

COMPARE HALFWORD extends the sign of the effective
halfword 16 bit positions to the left, then compares the
resultant 32-bit word with the contents of register R (with
both words treated as signed, fixed-point quantities) and
sets the condition code according to the results of thp.
comparison.
Affected: CC2, CC3, CC4

o
-

(R) : EHSE
Register value greater than immediate value.
No 1-bits compare, (R) n (I) 12-325 E = O.
One or more 1-bi ts compare,
(R) n (I) 12-32SE 10.

If CI is indirectly addressed, it is treated as a nonexistent
instruction, in which case the basic processor unconditionally aborts execution of the instruction (at the time of
operation code decoding) and then traps to location X'40'
with the condition code unchanged.

Comparison Instructions

Condition code settings:
2

Result of Comparison

... '-I v

t:_ .. ~1

.......

- a

Condition code settings:

Result of Comparison
No l-bits compare, (R) n EHSE =

- a

COMPARE WORD compares the contents of register R with
the effective word, with both words treated as signed fixedpoint quantiti es, and sets the condition code according to
the resu Its of the compari son.
Affected: CC2, CC3, CC4

(R) : EW

Condition code settings:
2

a a

Equal.

a
- a

Result of Comparison

COMPARE SELECTIVE

COMPARE SE LECTIVE compares the contents of register R
with the effective v;ord in on Iy those bit positions selected
by a 1 in corresponding bit positions of register Rul (mask).
The contents of register R and the effective word are ignored
in those bit positions designated by a a in corresponding bit
positions of register Rul. The selected contents of register R
and the effective word are treated as positive integer magnitudes, and the condition code is set according to the result of the comparison. If the R fieldof CS is an odd value;
CS compares the contents of register R with the logical
product (AND) of the effective word and the contents of
register R.

If R is odd: (R): EW n (R)
Condition code settings:

Equal.

- a

a
COMPARE DOUBLEWORD compares the effective doubleword with the contents of registers Rand Rv 1 (with both
doublewords treated as signed, fixed-point quantities)
and sets the condi ti on code accordi ng to the resu Its of the
comparison. If the R field of CD is an odd value, CD forms
a 64-bit register operand (by duplicating the contents of
register R for both the 32 high-order bits and the 32 loworder bits) and compares the effective doubleword with the
64-bit register operand. The condition code settings are
based on the 64-bit comparison.

(R, Rul) : ED

Resu I ts of Compari son under Mask in Ru 1

- a a
COMPARE DOUBLEWORD

Affected: CC3, CC4

If R is even: (R) n (Rul) : EW n (Rul)

One or more l-bits compare, (R) n EW I

Equal.

Affected: CC3, CC4

Result of Comparison

COMPARE WORD
(Word index alignment)

a a

One or more l-bits compare,
(R) n EHSE I

CLR

COMPARE WITH LIMITS IN REGISTERS
(Word index alignment)

H
o

COMPARE WITH LIMITS IN REGISTERS simultaneously
compares the effective word with the contents of register R
and with the contents of register Rul (with all three words
treated as signed fixed-point quantities), and sets the condition code according to the results of the comparisons.
Affected: CC

(R) : EW, (Rul) : EW

Comparison Instructions

Condition code settings:
2

Result of Comparison

Contents of R equal to effective word.

Contents of R greater than effective word.

o 0

Contents of Ru 1 equa I to effecti ve word.

Contents of Ru 1 less than effective word.

Contents of Ru1 greater than effective word.

elM

OR WORD
(Word index alignment)

Contents of R less than effective word.

the other operand is the effective word. The result of the
logical operation is loaded into register R.

COMPARE WITH LIMITS IN MEMORY
(Doubleword index alignment)

OR WORD logically ORs the effective word into register R.
If corresponding bits of register R and the effective word
are both 0, a 0 remains in register R; otherwise, a 1 is
placed in the corresponding bit position of register R. The
effective word is not affected.
Affected: (R), CC3, CC4

= 0, 0 u 1 = 1, 1 u 0 = 1,
1u 1= 1

R, where 0 u 0

(R) u EW -

Condition code settings:
COMPARE WITH LIMITS IN MEMORY simultaneously compares the contents of register R with the 32 high-order bits
of the effective doubleword and with the 32 low-order bits
of the effective doubleword, with all three words treated
as 32-bit signed quantities, and sets the condition code
according to the results of the comparisons.

0 0

Zero.

Bit 0 of register R is a 1.

Affected: CC

Result in R

Bit 0 of register R is a 0 and bit positions 1-31
of register R contain at least one 1.

(R) : ED _ ; (R) : ED -63
32
O 31
Condition code settings:
2

Result of Comparison

Contents of R equal to most signifi cant word,
(R) = ED _ '
O 31

Contents of R less than most significant word,
(R) < ED _ '

O 31

o
o

Contents of R greater than most significant
word, (R) > ED _ '
O 31

Contents of R equal to least significant word,
(R) = ED _ .
32 63

Contents of R less than least significant word,
(R) < ED _ .
32 63

Contents of R greater than least significant
word, (R) > ED _ .
32 63

LOGICAL INSTRUCTIONS
All logical operations are performed bit by corresponding
bit between two operands; one operand is in register Rand

Log i co I Instru ct i ons

EOR

EXCLUSIVE OR WORD
(Word index alignment)

EXCLUSIVE OR WORD logically exclusive ORs the effective word into register R. If corresponding bits of register R and the effective word are different! a 1 is placed in
the corresponding bit position of register R; if the contents
of the corresponding bit positions are alike, a 0 is placed
in the corresponding bit position of register R. The effective word is not affected.
Affected: (R), CC3, CC4
(R) (Q) EW--R
Condition code settings:
2

Resu It in R

Zero.

Bit 0 of register R is a 1.
OBit 0 of register R is a 0 and bit positions 1-31
of register R contain at least one 1.

AND WORD
rylord index alignment)

AND

AND WORD logically ANDs the effective word into register R. If corresponding bits of register R and the effecti ve word are both 1, a 1 remains in register R; otherwise,
a 0 is placed in the corresponding bit position of register R.
. The effective word is not affected.

amount of the shift are determined by bits 25-31 of the
indirect word plus bits 25-31 of the specified index register.
The effective address does not reference memory. Bit
positions 15-20 and 24 of the effective virtual address are
ignored. Bit positions 21, 22, and 23 of the effective
virtual address determine the type of shift, as follows:
21

Shift Type

logical, single register

Affected: (R), CC3, CC4

(R) n EW-R

Condition code settings:
2

0 0

Zero.

Bit 0 of register R is a 1.

SHIFT INSTRUCTIONS
The instruction format for logical, circular, arithmetic,
nnrl
ic:·
- .. - "on,.,..h;nn
--_. -·····v "hift
_..... t"Ino,.ntit"lnc:
-r-' ---._ .. - .--

SHIFT
(Word index alignment)

If neither indirect addressing nor indexing is called for in
the instruction SHIFT, bit positions 21-23 of the reference
address field determine the type, and bit positions 25-31
determine the direction and amount of the shift.

If only indirect addressing is called for in the instruction,
bits 15-31 of the instruction are used to access the indirect
word and then bits 21-23 and 25-31 of the -indirect word
determine the type, direction, and amount of the shift.

If both indirect addressing and indexing are called for in
the instruction, bits 15-31 of the instruction are used to
access the indirect word and then bits 21-23 of the indirect word determine the type of shift; the direction and

Arithmetic, single register
Ari thmeti c, double register

0
0

Searching, single register
Searching, double register

Bit positions 25 through 31 of the effective virtual address
are a shift count that determines the direction and amount
of the shift. The shift count (C) is treated as a 7-bit
signed binary integer, with the high-order bit (bit position 25) as the sign (negative integers are represented in
twols complement form). A positive shift count causes a
left shift of C bit positions. A negative shift count causes
a right shift of Ici bit positions. The value of C is within
the range: -64 ~ C S: +63.
All double-register shift operations require an even value
for the R field of the instruction, and treat registers Rand
Rul as a 64-bit register with the high-order bit (bit position 0 of register R) as the sign for the entire register. If
the R field of SHIFT is an odd value and a double-register
shift operation is specified, a register doubleword is formed
by duplicating the contents of register R for both the
32 high-order bits and the 32 low-order bits of the doubleword. The shift operation is then performed and the
32 high-order bits of the result are loaded into register R.
Overflow occurs (on left shifts only) whenever the value of
the sign bit (bit position 0 of register R) changes. At the
completion of logical left, circular left, arithmetic left, and
searching left shifts, the condition code is set as follows:
2

If only indexing is called for in the instruction, bits 21-23
of the instruction word determine the type of shift; the
direction and amount of shift are determined by bits 25-31
of the instruction plus bits 25-31 of the specified index
register.

Circular, single register
Circular, double register

Result in R

Bit 0 of register R is a 0 and bit positions 1-31
of register R contain at least one 1.

logical, double register

Result of Shift
Even number of lis shifted off left end of
register R.
Odd number of lis shifted off left end of
register Rt.

tNot applicable for searching shift.

Shift Instructions

2
-

Circular Shift, Double Register

Result of Shift
No overflow on left shift.
Overflow on left shift.

If the shift count, C, is positive, the contents of registers R
Searching shift terminated with

Ro equal

to 1.

At the completion of right shifts, the condition code is set
as follows:

2 3

and Ru 1 are shifted left C places. Bits shifted past bit
position 0 of register R are copied into bit position 31
of register Ru 1. (No bits are lost.) If C is negative, the
contents of registers Rand Ru 1 are shifted right Ici places.
Bits shifted past bit position 31 of register Ru 1 are copied
into bit position 0 of register R. (No bits are lost.)
Affected: (R), (Rul), CCl, CC2

Logical Shift, Single Register

Arithmetic Shift, Single Register

If the shift count, C, is positive, the contents of register R
are shifted left C places, the O's copied into vacated bit
positions on the right. (Bits shifted past RO are lost.) If C
is negative, the contents of register R are shifted right Ici
places, with O's copied into vacated bit positions on the
left. (Bits shifted past R31 are lost.)

If the shift count, C, is positive, the contents of register R
are shifted left C places, with O's copied into vacated bit
positions on the right. (Bits shifted past RO are lost.) If C
is negative, the contents of register R are shifted right· lei
places, with the contents of bit position 0 copied into vacated bit positions on the left. (Bits shifted past R31
are lost.)

Affected: (R), CCl, CC2

Affected: (R), cc 1, CC2

Logical Shift, Double Register
Arithmetic Shift, Double Register

If the shift count, C, is positive, the contents of registers
Rand Rul are shifted left C places, with O's copied into
vacated bit positions on the right. Bits shifted past bit
position 0 of register Ru 1 are copied into bit position 31
of register R. (Bits shifted past RO are lost.) If C is negative, the contents of registers Rand Ru 1 are shifted right
Ici places with O's copied into vacated bit positions on the
left. Bits shifted past bit position 31 of register Rare
copied into bit position 0 of register Ru1. (Bits shifted
past Ru 131 are lost.)

If the shift count, C, is positive, the contents of register R
and Rul are shifted left C places, with O's copied into vacated bit positions on the right. Bits shifted past bit position 0 of register Rul are copied into bit position 31 of
register R. (Bits shifted past RO are lost.) If C is negative,
the contents of registers Rand Ru 1 are shifted right Ici
thp._ contp.ntc;
noc;ition 0- of
R
.'olacp.s_ with
...
... - .. -- of
-" hit
-.- ,---.'._"
_ . rpnidpr
. _.;;;J.-._' ...
--~

copied into vacated bit positions on the left. Bits shifted
past bit position 31 of register R are copied into bit position 0 of register Ru1. (Bits shifted past Ru131 are lost.)

Affected: (R), (Ru 1), CC 1, CC2
Affected: (R), (Ru 1), CC 1, CC2
Circular Shift, Single Register
Searching Shift, Single Register

If the shift count, C, is positive, the contents of register R
aie shifted left C places. Bits shifted post bit positio(1 0
are copied into bit position 31. (No bits are lost.) If C
is negative, the contents of register R are shifted right
Ici places. Bits shifted past bit position 31 are copied
into bit position O. (No bits are lost.)
Affected: (R), CCl, CC2

Shift Instructions

The :)eur(;hing ~hift is circuiar in either direction. if the
shift count, C, is positive, the contents of register Rare
shifted left C bit positions or until a 1 appears in bit position O. If C is negative, the contents are shifted right Ici
positions or unti I a 1 appears in bit position O. When the
shift is terminated, the remaining count is stored in register 1, which is dedicated to the searching shift instruction.

Bits 0-24 of register 1 are cleared and the remaining count
is loaded into bits 25-31. If the initial contents of bit 0
is equal to 1, then no bits are shifted by the instruction.
In this case the original count in the instruction is stored
in register 1.
Searching shift causing a change in bit position 0 causes
CC2 to be set to 1. If bit posi tion 0 is not changed during
a searching shift, CC2 is cleared. CC4 is set to 1 if the
shift is terminated with a 1 in bit position O.
Affected: (R), (Rl), CC2, CC4

If direct addressing and indexing are called for in the
instruction, bit 23 of the reference address (not affected
by subsequent indexing) determines the type of shift.
Bits 25-31 of the reference address plus bits 25-31 of the
specified indexed register determine the direction and
amount of the shift.
If indirect addressing and indexing are called for in the instruction, bits 15-31 of the reference address are used to
access the indirect word. Bit 23 of the indirect word (not
affected by subsequent indexing) determines the type of
shift. Bits 25-31 of the indirect address plus bits 25-31 of
the specified index register determine the direction and
amount of the shift.

Searching Shift, Double Register

The searching shift is circular in either direction. If the
shift count, C, is positive, the contents of registers Rand
Ru1 are shifted left C bit positions or until a 1 appears in
bit posi tion 0 of register R. If C is negative, the contents
are shifted right lei posi tions or unti I a 1 appears in bit
posi tion O. When the shift is terminated, the remaining
count is stored in register 1, which is dedicated to the
searching shift instruction. Bits 0-24 of register 1 are
cleared and the remaining count is loaded into bits 25-31.
Searching shift causing a change in bit position 0 causes
CC2 to be set to 1. If bit position 0 is not changed during
a searching shift, CC2 is cleared. CC4 is set to 1 if the
shift is terminated with a 1 in bit position O.
Affected: (R), (Rul), (Rl), CC2, CC4

The shift count, C, in bit positions 25-31 of the effective
virtual address determines the amount and direction of
the shift. The shift count is treated as a 7-bit signed
binary integer, with the high-order bit (bit position 25) as
the sign (negative integers are represented in twols complement form).
The absolute value of the shift count determines the number
of hexadecimal digit positions the floating-point number is
to be shifted. If the shift count is positive, the floatingpoint number is shifted left; if the count is negative, the
number is shifted right.
SHIFT FLOATING loads the floating-point number from the
register(s) specified by the R field of the instruction into a
set of internal registers. If the number is negative, it
is twols complemented. A record of the original sign is
retained. The floating-point number is then separated into
a characteristic and a fraction, and CCl and CC2 are both
reset to OIS.
A positive shift count produces the following left shift
operations:

FLOATING-POINT SHIFT
Floating-point numbers are defined in the "FloatingPoint Arithmetic Instructions" section. The format for the
floating-point shift instruction is:

SHIFT FLOATING
0/lord index alignment)

If direct addressing and no indexing is called for in the instruction SHIFT FLOATING, bit position 23 of the reference
address field determines the type {long or short format} of
shift, and bit positions 25-31 determine the direction and
amount of the shift.
If indirect addressing and no indexing is called for in the
instruction, bit positions 15-31 of the instruction are used
to access the indirect word and then bit positions 23 and
25-31 of the indirect word determine the type, direction,
and amount of the shift.

If the fraction is normalized (i. e., is less than 1 and
is equal to or greater than 1/16), or the fraction is
a" OIS, CCl is set to 1.

If the fraction field is all OIS, the entire floating-point
number is set to all OIS ("true" zero), regardless of the
sign and the characteristic of the original number.

If the fraction is not normalized, the fraction field is
shifted 1 hexadecimal digit position (4 bit positions) to
the left and the characteristic field is decremented
by 1. Vacated digit positions at the right of the fraction are fi lIed with hexadecimal OIS.
If the characteristi c fie Id underflows (i. e., is all lis
as the result of being decremented), CC2 is set to l.
However, if the characteristic field does not underflow, the sh ift process (sh ift fracti on, and decrement characteristic) continues until the fraction is
normalized, unti I the characteristic field underflows,
or unti I the fraction is shi fted left C hexadeci ma I
digit positions, whichever occurs first. (Any two,
or all three, of the terminating conditions can occur
simultaneously. )

Shift Instructions

At the completion of the left shift operation, the
floating-point result is loaded back into the general
register{s}. If the number was origina"y negative, the
twols complement of the resultant number is loaded
into the general register {s}.

The condition code settings following a floating-point
left shift are as follows:

Result

"True" zero (all OIS).

Result

Positive.

IC/

digits shifted (no characteri sti c
overflow).
Characteristi c overflow.

Floating Shift, Single Register

Negative.

o
o 0

Positive.
C digits shifted (fraction unnormalized,
no characteristic underflow).

Fraction normalized {includes "true"
zero}.

Characteristic underflow.

A negative shift count produces the following right shift
operations (again assuming that negative numbers are twols
complemented before and after the shift operation):

The fraction field is shifted 1 hexadecimal digit position to the right and the characteristic field is incremented by 1. Vacated digit positions at the left are
fi lIed with hexadecimal OIS.

If the characteristic field overflows (i. e., is all OIS as
the result of being incremented), CC2 is set to 1.
However, if the characteristic field does not overflow,
the shift process (shift fraction, and increment characteristic) continues until the characteristic field
overflows or unti I the fraction is shifted right lei hexadecimal digit positions, whichever occurs first. (Both
terminating conditions can occur simultaneously.)

If the resultant fraction field is all OIS, the entire
floating-point number is set to all OIS C'true" zero),
regardless of the sign and the characteristic of the
original number.
At the completion of the right shift operation, the
floating-point result is loaded back into the general
register{s}. If the number was originally negative,
the twols complement of the resu Itant number is loaded
into the general register(s}.
The condition code settings following a floating-point

The short-format floating-point number in register R is
shifted according to the rules established above for floatingpoint shift operations.
Affected: {R}, CC

Floating Shift, Double Register

The long-format floating-point number in registers Rand
Ru 1 is shifted according to the rules established above for
floating-point shift operations. (If the R field of the instruction word is an odd value, a long-format f/oatingpoint number is generated by duplicating the contents of
register R, and the 32 high-order bits of the result are
loaded into register R. )
Affected: {R}, (Rul), CC

CONVERSION INSTRUCTIONS
The conversion instructions are:
Instruction Name

Mnemo'nic

Convert by Addition

CVA

Convert by Subtraction

CVS

These two conversion instructions can be used to accomplish bidirectional translation between binary code and any
other weighted binary code, such as BCD.

dght sh:ft are as fe! !ews:
2

Result

"True" zero (all zeros).

- 0
72

Negative.

Conversion Instructions

The effective addresses of the instructions CONVERT BY
ADDITION and CONVERT BY SUBTRACTION each point
to the starting location of a conversion table of 32 words,
containing weighted values for each bit position of register Ru 1. The 32 words of the conversion table are considered to be 32-bit positive quantities, and are referred

to as conversion volues. The intermediate results of these
instructions are accumulated in internal basic processor
registers unti I the instruction is completed; the result is
then loaded into the appropriate general register. Both
instructions use a counter ~n) that is set to 0 at the beginning
of the instruction execution and is incremented by 1 with
each iteration, unti I a total of 32 iterations has been
performed.

If a memory parity or protection violation trap occurs during the execution of either instruction, the instruction sequence is aborted (without having changed the contents of
register R or Rul) and may be restarted (at the beginning of
the instruction sequence) after the trap routine is processed.

eVA

CONVERT BY ADDITION
rNord index alignment)

CONVERT BY ADDITION initially clears the internal A register and sets an internal counter (n) to O. If bit position n
of register Rul contains a 1, CVA adds the nth conversion
value (contents of the word location pointed to by the effective address plus n) to the contents of the A register,
accumulates the sum in the A register, and increments n
by 1. If bit position n of register Ru1 contains a 0, CVA
only increments n. If n is less than 32 after being incremented, the next bit position of register Rul is examined,
and the addition process continues through n equal to 31;
the result is then loaded into register R. If, on any itera.•.•
i
• • .1
1
,.,1?_1 ,..,..,.
•
Tlon, rne sum nas exceeaea rne vUlue , L - - . , \,,\,,1 I~ ~el
to 1; otherwise, CCl is reset to O.
Affected: (R), CC1, CC3, CC4

evs

CONVERT BY SUBTRACTION loads the internal A register
with the contents of register R, clears the internal B register, and sets an internal counter (n) to O. All conversion
values are considered to be 32-bit positive quantities. If
the nth conversion value (the contents of the word location
pointed to by the effective address plus n). is equal to or
less than the current contents of the A register, CVS increments n by 1, adds the two's complement of the nth conversion value to the contents of the A register, stores the
sum in the A register, and stores a 1 in bit position n of the
B register. If the nth conversion value is greater than the
current contents of the A register, CVS only increments n
by 1. If n is less than 32 after being incremented, the
next conversion value is compared and the process continues through n equal to 31; the remainder in the A register is loaded into register R, and the converted quantity
in the B register is loaded into register Ru1.
Affected: (R), (Rul), CC3, CC4
(R)-A, O-B, O-n

If (EWL + n) $ (A) then A - (EWL + n) - A ,
l - B ,n + 1 - n
n

If (EWL + n)
Tt'

/')1"\

1I11 ..... uL,

> (A)

then n + 1 - n

_ . . ___ L .
_LL __ .. • __
1~tx='UljVIIl~lyyl;)<::,

IA\~D

\r'./

''',

ID\

D •• 1

\U/-',\U.

continue to the next instruction.
Condition code settings:

O-A,O-n

If (Rul) =1, then (EWL + n) + (A) -A, n + 1 - n
n

If (Ru1) =0, then n + 1 - n

If n < 32, repeat; otherwise, (A) next instruction.

CONVERT BY SUBTRACTION
rNord index alignment)

R and continue to

Result in Rul

Zero.

Bit 0 of register Ru 1 is a 1.

BitOofregisterRu1 is a 0 and bit positions 1-31 of register Ru 1 contain at least
one 1.

Condition code settings:
2

Resu It in R

Zero.

. FLOATING-POINT ARITHMETIC INSTRUCTIONS
-

The floating-point arithmetic instructions are:
O B i t 0 of register R is a 1.
Instruction Name

Mnemonic

Floating Add Short

FAS

Sum is correct (less than ~2).

Floating Add Long

FAL

Sum is greater than ~2_1.

Floating Subtract Short

FSS

OBit 0 of register R is a 0 and bit positions 1-31
of register R contain at least one 1.

o - - -

Floating-Point Arithmetic Instructions

Instruction Name

Mnemonic

Floating Subtract Long

FSL

Floating Multiply Short

FMS

Floating Multiply Long

FML

Floating Divide Short

FDS

Floating Divide Long

FDL

for addition and subtraction, an abnormal zero is
treated the same as any nonzero operand.

A positive floating-point number is normalized if and
only if the fraction is contained in the interval
1/16 $ F < 1

A negative floating-point number is the two's complement of its positive representation.

A negative floating-point number is normalized if and
only if its two's complement is a normalized positive
number.

FLOATING-POINT NUMBERS
By this definition, a floating-point number of the form
Two number formats are accommodated for floating-point
arithmetic: short and long. A short-format floating-point
number consists of a sign (bit 0), a biased t , base 16 exponent, which is called a characteristic (bits 1-7), and a
six-digit hexadecimal fraction (bits 8-31). A long-format
floating-point number consists of a short-format floatingpoint number followed by an additional eight hexadecimal
digits of fractional significance, and occupies a doubleword memory location or an even-odd pair of general
registers.

1xxx xxxx 1111 0000 . .. 0000
is normalized, and a floating-point number of the form
1xxx xxxx 0000 0000 . .. 0000
is illegal and, whenever generated by floating-point instructions, is converted to the form
1yyy yyyy 1111 0000 . .. 0000

A floating-point number (N) has the following format:
where yy ... y is 1 less than xx •.• x.
examples of floating-point numbers.

1+1
- Character-I
istic (C)
6

314

: Fraction (F) :

1011112 13 14 15 16 17 18 19120 2122 23 242526271282930 31

A floating-point number (N) has the following formal
definition:

N
16
16

=F x
-6

where F = 0 or

$IFI $ 1 (short format) or

- i4

$IFI $ 1 (long format)

and 0 $ C
2.

C-64

Table 7 contains

127.

A positive floating-point number with a fraction of
zero and a characteristic of zero is a "true" zero.
A positive floating-point number with a fraction of
zero and a nonzero characteristic is an "abnormal"
zero. For floating-point multiplication and division,
an abnormal zero is treated as a true zero. However,

Modes of Operation
There are four mode control bits that are used to qualify
floating-point operations. These mode control bits are
identified as FR (floating round), FS (floating significance),
FZ (floating zero), and FN (floating normalize); they are
contained in bit positions 4, 5, 6, and 7, respectively, of
the program status words (PSWs4_7).
The floating-point mode is established by setting the four
floating-point mode control bits. This can be performed by
any of the following instructions:
Instruction Name

Mnemonic

Load Conditions and Floating Contro I

LCF

Load Conditions and Floating Control
Immediate

LCFI

Load Program Status Words

LPSD

Exchange Program Status Words

XPSD

The floating-point mode control bits are stored by executing either of the:: following insrrucrions:
tThe bias value of 4016 is added to the exponent for the
purpose of making it possible to compare the absolute magnitude of two numbers, i. e., without reference to a sign
bit. This manipulation effectively removes the sign bit,
making each characteristic a 7-bit positive number.

Floating-Point Arithmetic Instructions

Instruction Name

Mnemonic

Store Conditions and Floating Control

STCF

Exchange Program Status Words

XPSD

Table 7.

Floating-Point Number Representation
Short Floating-Point Format

Decimal Number

+(16 +63)(1_2- 24 )

111

1111

FFFFFF

+(16 +3)(5/16)

100

0011

0101

0000

500000

3
+(16- )(209/256)

011

1101

0001

0000

Dl0000

+(16 -63)(2047/4096)

000

0001

0111

1111

0000

7FFooo

Hexadecimal Value

+(16-

)(1/16)

000

0000

0001

0000

100000

000

0000

000000

111

1111

0000

FOOooO

-(16 -63)(2047/4096)

111

1110

1000

0000

0001

0000

801000

3
-( 16- )(209/256)

100

0010

1111

0000

C2 2 FOooO

3
-(16+ )(5/16)

011

1100

1011

0000

BC BooooO

-(16+63)(1_2 24 )

000

0000

0001

0000

e +1

1111

0000

o (called
-(16-

true zero)

)(1/16)

000001

Special Case
e
-(16 )(1 )

is changed to
1
_(16 e + )(1/16)

whenever generated as the result of a floating-point instruction.

FLOAllNG-POINT ADD AND SUBTRACT

FR = 0

No rounding specified (truncation).

The floating round (FR), floating normalize (FN), floating
zero (FZ), and floating significance (FS) mode control
bits determine the operation of floating-point addition
and subtraction (if characteristic overflow does not occur)
as follows:

FR = 1

The results of additions and subtractions are
to be rounded. Each value associated with
the operation (i. e., augend, addend, and
intermediate result of an add) is extended by
the hardware to include one guard digit.
(Short-format values are extended into bit
positions 32-35 and long-format values are
extended into bit positions 64-67.) Contents
of guard digits may be affected during prealignment, computation, or postnormalization.
Rounding is performed by evaluating the guard
digit of the intermediate result after any required postnormalization. If the value of the
guard digit is 0-7, the other digits are not
modified. If the value of the guard digit
is 8-F, the value contained within the other
digits is incremented by one.

Floating round:

Note: The floating round faci lity is avai lable only in
- - the hardware floating-point. In the absence
of this feature, the floating-point subroutines
offer on Iy truncation; hence, to guarantee
hardware and software identical results, FR
(bit 4 of PSWs) must be zero.

Floating-Point Arithmetic Instructions

and FS have no effect on the instruction
operation. If the result is zero, the result
is set to II true II zero and the condition code
is set to 0000. If the result is positive, the
condition code is set to 0010. If the result is negative, the condition code is set
to 0001.

The following table shows the possible cases:
Pos tno rma Ii za ti on

Pre-alignment
(exponents

Scale
Answer
Left

Scale
Answer
Right

Guard Digit Action

(Guard di git = O. )

Round on guard digit. 0

Overflow, N

Overflow, N >0

-A + A(f)

@[:

a/A, or -A + A(f) with FN= I )
Normal
resu Its

*
*

Divide by zero

<0
}

> 2 Pos t norma I0 0
h0ft
IZlngs I S

)

Always trapped

-A +A

rs=

FS=O
FN = 0, and
no underflow

N < 0) > 2 PostnormaldI' FN=O
d '
. .
.
an no un er-

N>O

Underflow with FZ=O and no trap by FS= 10

Underflow,

Underflow, N >0

Notes:

(j)

Result set to "true" zero

"*,, indicates impossible configurations

IZlng shifts

N >0

N < a}

flow with FZ= 1

FZ= 1

® Applies to add and subtract only where FN = 0

The R field of the FAL instruction must be an even value
for proper operation of the instruction; if the R field of FAl
is an odd value, the instruction traps to location X'4D',
instruction exception trap.

FSL

lC
o

FSS

FLOATING SUBTRACT SHORT
rNord index alignment)

3ci

0123145678

R
9

I X I:

Referenc~ address

1011121314151617181912021222324252627128293031

FLOATING SUBTRACT SHORT forms the two's complement
of the effective word and then operates identically to
FLOATING ADD SH ORT (FAS), If no flo(lting-po!n t
arithmetic fault occurs, the difference is loaded into register R as a short-format floating-point number.
Trap: Floating-point arithmetic fault

(R) - EW- R

Floating-Point Arithmetic Instructions

I
718

Reference address

10 11112 13 14 115116 17 18 1912021 22 23124 25 26 27128 29 30 31'

The effective doubleword and the contents of registers R
and Ru 1 are loaded into a set of internal registers.

The effective word and the contents of register R are loaded
into a set of internal registers.

Affected: (R), CC

FLOATING SUBTRACT LONG
(Doubleword index alignment)

FLOATING SUBTRACT LONG forms the two's complement of the effective doubleword and then operates identically to FLOATING ADD LONG (FAL). If no floatingpoint arithmetic fault occurs, the difference is loaded into
registers Rand Ru 1 as a long-format floating-point number.
Affected:

(R), (Ru 1), CC

(R, Rul) - ED - R , Ru1

Trap: Floating-point arithmetic fault, instruction exception

The R field of the FSL instruction must be an even value for
proper operation of the instruction; if the R field of FSL is
an odd value, the instruction traps to location X'4D',
instruction exception trap.

FMS

FLOATING MULTIPLY SHORT
(Word index alignment)

The effective word (multiplier) and the contents of register R
(multiplicand) are loaded into a set of internal registers,
and both numbers are then prenormalized (if necessary). A
normalized 6-digit product is produced, appended by a
guard digit. If FR equals 1, and the guard digit contains 8
or greater, the fraction is incremented. If no floatingpoint arithmetic fault occurs, the product is loaded into
register R as a short-format floating-point number.
Affected: (R), CC
(R) x EW-R

Trap: Floating-point arithmetic fault

FDL

FLOATING DNIDE LONG
(Doubleword index alignment)

The effective doubleword (divisor) and the contents of
registers Rand Ru 1 (dividend) are loaded into a set of
internal registers. F LOA TING DIVIDE LONG then operates identically to FLOATING DIVIDE SHORT (FDS),
except that the operands are each 14 hexadecimal digits
long. R must be an even value for correct results. If
no floating-point arithmetic fault occurs, the quotient is
loaded into registers Rand Ru 1 as a long-format floatingpoint number.
Affected: (R), (Ru 1), CC
(R, Rul) + ED -

FML

FLOATING MULTIPLY LONG
(Doubleword index alignment)

The effective doubleword (multiplier) and the contents of
registers Rand Ru1 (multiplicand) are loaded into a set of
internal registers. {FLOATING MULTIPLY LONG then
operates identically to FLOATING MULTIPLY SHORT
(FMS), except that the operands are each 14 hexadecimal
digits long. R must be an even value for correct results.
If no floating-point a,rithmetic fault occurs, the product is
loaded into registers Rand Ru 1 as a long-format floating-

(R, Ru1) x ED - R , Ru1

Trap: Floating-point arithmetic fault, instruction exception

The R field of the FML instruction must be an even value
for proper operation of the instruction; if the R field of
FML is an odd value, the instruction traps to location X ' 4D',
instruction exception trap.

FDS

FLOATING DIVIDE SHORT
(Word index alignment)

The effective word (divisor) and the contents of register R
(dividend) are loaded into a set of internal registers and
both numbers are then prenormalized (if necessary). A
normalized 6-digit quotient is produced, appended by a
guard digit. If FR equals 1, and the guard digit contains 8
or greater, the fraction is incremented. If no floatingpoint arithmetic fault occurs, the quotient is loaded into
register R as a short-format floating-point number.
Affected: (R), CC
(R)

+ EW-R

Trap: Floating-point arithmetic fault

Floating'~point arithmetic fault, instruction exception

The R field of the FDL instruction must be an even value
for proper operation of the instruction; if the R field ofFDL
is an odd value, the instruction traps to location X 14D 1
i'nstruction exception trap.

PUSH-DOWN INSTRUCTIONS (NON-PRIVILEGED)
The term "push-down processing" refers to the programming
technique (used extensively in recursive routines) of storing
the context of a calculation in memory, proceeding with a
npw c;pt (If i nfnrmnti nn

...,..:. ...
. .+. ...........
. _ ••• hor
__ ••

t"~

Affected: (R), (Ru 1), CC

R, Rul

Trap:

nnrl thpn ncti vnti n9 thp. prp.vi Oiled),

stored information. Typically, this process involves a reserved area of memory (stack) into which operands are
pushed (stored) and from which operands are pulled (loaded)
on a last-in, first-out basis. The basic processor provides for simplified and efficient programming of pushdown processing by means of the following non-privi leged
instructions:
Instruction Name

Mnemonic

Push Word

PSW

Pull Word

PLW

Push Multiple

PSM

Pull Multiple

PLM

fv\odify Stack Pointer

MSP

STACK POINTER DOUBLEWORD (SPD)
Each non-privileged push-down instruction operates with
respect to a memory stack that is defined by a doubleword

Push-Down Instructions (Non-Privi leged)

located at effective address of the instruction.
This
doubleword, referred to as a stack pointerdoubleword (SPD),
has the following structure:

Bit positions 15 through 31 of the SPD contain a 17-bit
address field t that points to the location of the word currently at the top (highest-numbered address) of the operand stack. In a push operation, the top-of-stack address
is incremented by 1 and then an operand in a general register is pushed (stored) into that location, thus becoming
the contents of the new top of the stack; the contents of
the previous top of the stack remain unchanged. In a pull
operation, the contents of the current top of the stack are
pulled (loaded) into a general register and then the topof-stack address is decremented by 1; the contents of the
stack remain unchanged.

Bit positions 33 through 47 of the SPD, referred to as the
space count, contain a 15-bit count (0 to 32,767) of the
number of word locations currently avai lable in the region
of memory allocated to the stack. Bit positions 49 through 63
of the SPD, referred to as the word count, contain a 15-bit
count (0 to 32,767) of the number of words currently in the
stack. In a push operation, the space count is decremented
by 1 and the worcl count is incremented by 1; in a pull operation, the space count is incremented by 1 and the word
count is decremented by 1. At the beginning of all nonprivi leged push-down instructions, the space count and the
word count are each f'ested to determine whether the instruction would cause either count field to be incremented above
the upper limit of 2 15 _1 (32,767), or to be decremented
beiow the iower iimit of O. if execution of the push-down
instruction would cause either count limit to be exceeded,
the basic processor unconditionally aborts execution of the
instruction, with the stack, the stack pointer doubleword,
and the contents of general registers unchanged. Ordinarily,
the basic processor traps to location X' 42 1 after aborting
a push-down instruction because of impending stack limit
overflow or underflow, and with the condition code unchanged from the value it contained before execution of
the instruction.

Bit position 32 of the SPD, referred to as the trap-on-space
(TS) inhibit bit, determines whether the basic processor will
trap to location X' 42 1 as a result of impending overflow or
underflow of the space count (SPD .;.47)' as follows:
33
TS

Space count overflow/underflow action

If the execution of a pull instruction would cause the
space count to exceed 2 15- 1, or if the executi on of a
push instruction would cause the space count to be
less than 0, the basic processor traps to location X' 42 1
with the condition code unchanged.
Instead of trapping to location X'421, the basic processor sets CCl to 1 and then executes the next instruction in sequence.

Bit position 48 of the SPD, referred to as the trap-on-word
(TW) inhibit bit, determines whether the basic processor
traps to location X' 42 1 as a result of impending overflow
or underflow of the word count (SPD 49-63)' as fo.llows:
TW

Word count overflow/underflow action

If the execution of a push instruction would cause the
word count to exceed 2 15 - 1, or if the execution of
a pull instruction would cause the word count to be
less than 0, the basic processor traps to location X' 42 1
with the condition code unchanged.
Instead of trapping to location X'421, the basic processor sets CC3 to 1 and then executes the next
instruction in sequence.

PUSH-DOWN CONDITION CODE SEnlNGS

If the execution of a push-down instruction is attempted
and the basi c processor traps to locati on X'421, the condition code remains unchanged from the value it contained
immediately before the instruction was executed.
If the execution of a push-down instruction is attempted and
the instruction is aborted because of impending stack iimit
overflow or underflow (or both) but the push-down stack
limit trap is inhibited by one (or both) of the inhibits (TS
and TW), then, CCl or CC3 is set to 1 (or both are set
to lis) to indicate the reason for aborting the push-down
instruction, as follows:
2

Impending overflow of word count on a push
operation or impending underflow of word
count on a pull operation. The push-down
stack limit trap was inhibited by the TW
bit (SPD 48)'

However, this trap action can be selectively inhibited by
setting either (or both) of the trap inhibit bits in the
SPD to 1.

o t

For real extended mode of addressing this is a 20-bit
field (12-31); for real and virtual addressing modes it is a
17-bit field (15-31),

Push-Down Instructions (Non-Privi leged)

Reason for abort

Impending overflow of space count on a pull
operation or impending underflow of space
count on a push operation. The push-down
stack limit trap was inhibited by the TS bit
(SPD 32)·

Reason for abort

Impending overflow of word count and underflow of space count on a push operati on or
impending overflow of space count and underflow of word count on a pull operation. The
push-down stack limit trap was inhibited by
both the TW and the TS bits.

The space count (SPD33-47) is decremented by 1 and
the word count (SPD49-63) is incremented by 1.

The condition code is set to reflect the new status of
the space count.

Affected: (SPD), (TSA+1), CC
(SPD)15_31 + 1 -

If a push-down instruction is successfully executed, CC1
and CC3 are reset to 0 at the completion of the instruction. Also, CC2 and CC4 are independently set to indicate the current status of the space count and the word
count, respectively, as follows:

(R) -

{SPD

Status of space and word counts

The current space count and the current word
count are both greater than zero.

0 -

The current space count is greater than zero,
but the current word count is zero, indicating
that the stack is now empty. If the next operation on the stack is a pull instruction, the
instruction wi II be aborted.
0

The current word count is greater than zero,
but the current space count is zero, indi cating that the stack is now full. If the next operation on the stack is a push instruction, the
instruction wi II be aborted.

If the basic processor does not trap to location X' 42 1 as a
result of impending stack limit overflow/underflow, CC2
nn~ ("("4 in~ir.ntp thp c:tntlls of thf! soace and word counts
at the termin~tion of the push-down instruction, regardless
of whether the space and word counts were actually modified by the instruction. In the following descriptions of
the push-down instructions, condition code settings given
are only those that can be produced by the instruction,
provided that the basi c processor does not trap to location X'421.
-- • • -

PSW

-----.

-- -

SPD 15 _31 t

_ )t
15 31

{SPD)33_47- 1 (SPD)49-63 + 1 -

Trap: Push-down stack limit

SPD 33 _47
SPD 49-63

Condition code settings:

2 3

Result of PSW

Space count is greater
than O.
Space count is now O.

0 0

0
0

Word count
TW = 1.

Space count
TS = 1.

}

= 2 15 _1 ,
= 0,

Space count = 0, word
count = 0, TS = 1.

Instruction
completed

Instruction
aborted

PLW

Word count = 2 15 _1 ,
space count = 0,
TW = 1, and TS = 1.

PULL WORD
(Doubleword index alignment)

PUSH WORD
(Doubleword index alignment)

PUSH WORD stores the contents of register R into the pushdown stack defined by the stack pointer doubleword located
at the effective doubleword address of PSW. If the push operation can be successfully performed, the instruction operates as follows:

The current top-of-stack address (SPD 15 _31 )t is incremented by 1 to point to the new top-of-stack location.

The contents of register R are stored in the location
pointed to by the new top-of-stack address.

t For rea I extended mode of addressi ng th i sis a 20-bi t
field (12-31); for real and virtual addressing modes it is
a 17-bit field (15-31).

PULL WORD loads register R with the word currently at the
top of the push-down stack defined by the stack pointer
doubleword located at the effective doubleword address
of PLW. If the pull operation can be performed successfully,
the instruction operates as follows:

The current top-of-stack address is decremented by 1,
to point to the new top-of-stack location.

tFor real extended mode of addressing this is a 20-bit
field (12-31); for real and virtual addressing modes it is
a 17-bit field (15-31).
Push-Down Instructions (Non-Privileged)

The space count (SPD33-47) is incremented by 1 and
the word count (SPD49-63) is decremented by 1.

The condition code is set to reflect the status of the
new word count.

Affected: (SPD), (R),

The contents of registers R to R = CC - 1 are stored in
ascending sequence, beginning with the location
tion pointed to by the current top-of-stack address
(SPD15-31)t plus 1 and ending with the current topof-stack address plus CC.

The current top-of-stack address is incremented by the
value of CC, to point to the new top-of-stack location.

The space count (SPD33-47) is decremented by the
value of CC and the word count is incremented by the
value of CC.

The condition code is set to reflect the new status of
the space count.

Trap: Push-down stack limit

(SPD)15_31- R; (SPD)15_31- 1 (SPD)33_47 + 1 -

If there is sufficient space in the stack for all of the
specified registers, PSM operates as follows:

SPD

_ t
15 31

SPD 33 _4 i

(SPD)49_63- 1 -SPD 49-63

Condition code settings:

Affected: (SPD), (TSA+1) to
(TSA+CC), CC

Result of PLW

Word count is greater
than O.

Word COlKlt is now O.

Instruction
completed

(R)-(SPD)15_31 + 1. .. (R+CC-l)-(SPD)t
(SPD)15_31+CC -SPD

(SPD)49-63 +C C -

Space count = 0,
word count = 0, TW = 1.

Condition code settings:

Space count = 2
TS = 1.

-1,

Instruction
aborted

15
Space count = 2 -1,
word count = 0, TS = 1,
and TW = 1.

Push-Down Instructi ons (Non-Privi Ieged)

Result of PSM

000

Space count = O.

Wordcount+CC>2 15 _1,
TW = 1.

Space count

o 0

= 1.

Space count < CC, word
count + CC > 2 15 _1
TS = 1, and TW = 1.
Space count = 0, TS

Instructi on
aborted

= 1.

Space count = 0, word
count = 0, TS = 1.

< CC,

Instruction
completed

Sp(1ce count < CC, word
count = 0, TS = 1.

SPD 49-63

Space count> O.

PUSH MULTIPLE
(Doubleword index alignment)

PUSH MULTIPLE stores the contents of a sequential set of
general registers into the push-down stack defined by the
stack pointer doubleword located at the effective doubleword address of PSM. The condition code must contain
a count of the number of registers to be pushed into the
stack. (An initial value of 0000 for the condition code
specifies that all 16 general registers are to be pushed
into the stack.) The registers are treated as a circular set
(with register 0 following register 15) and the first register
to be pushed into the stack is register R. The last register
to be pushed in to the stack is register R + CC -1, and the
contents of this register become the contents of the new
top-of-stack location.

_ t
15 31

o 0 0 0

o
PSM

_ +CC
15 31

(SPD)33_47-CC -SPD 33 _47

Word count = 0, TW = 1.

Trap: Push-down stack limit

Space count = 0, word
count + CC > 2 15 _1,
TS = 1, and TW = 1.

For real extended mode of addressing this is a 20-bit
field (12-31); for real and virtual addressing modes it is a
17-bit field (15-31).

If the instruction operation extends into a memory page
protected either by the access protection codes or write
locks, the memory protection trap can occur. If the operation extends into a memory region that is physically not
present, the nonexistent memory address trap can occur.

Condition code settings:
2

then the registers indicated by the R field of the PSM instruction are stored in the general, registers rather than in
main memory. In this case the resultswill be unpredictable if
any source registers are also used as destination registers.

0 0

PLM

0 0

PULL MULTIPLE loads a sequential set of general registers
from the push-down stack defined by the stack pointer
doubleword located at the effective doubleword address of
PLM. The condition code must contain a count of the number of words to be pulled from the stack. (An initial value
of 0000 for the condition code specifies that 16 words are
to be pulled from the stack.) The registers are treated as a
circular set (with register 0 following register lS), the first
register to be loaded from the stack is register R+CC-l, and
the contents of the current top-of-stack location becomes
the contents of this register. The last register to be loaded
is register R.

Registers R+CC-l to register R are loaded in descending sequence, beginning with the contents of the location pointed to by the current top-of-stack address
{SPD1S-31)t and ending with the contents of the location pointed to by the current top-of-stack address
minus CC-l.

The current top-of-stack address is decremented by the
value ofCC, to point to the new top-of-stack location.

The space count (SPD33-47) is incremented by the
value of CC and the word count is decremented by the
value of CC.

The condition code is set to reflect the new status of
the word count.

-Icc -

11) -

< CC,

Word count
TW = 1

= 0,

0 0

Instructi on
completed

Space count = 0,
word count < CC,
TW = 1

Space count + CC > 2
TS = 1

Instruction
aborted
lS

-1,

lS
Space count + CC > 2 -1,
word count < CC, TS = 1,
and TW = 1
lS
Space count + CC > 2 -1,
word count = 0, TS = 1,
and TW = 1

If the instruction operation extends into a memory page
protected either by the access protection codes or write
locks, the memory protection trap can occur. If the
operation extends into a memory region that is physically
not present, the nonexistent memory address trap can
occur.

If the address of the elements within the stack (pointed to
by the top-of-stack address) is in the range 0 through lS,
then the words to be loaded are taken from the general
registers rather than from main memory. In this case, the
results will be unpredictable if any of the source registers
are also used as destination registers.

MODIFY STACK POINTER
(Doubleword index alignment)

Trap: Push-down stack limit

{(SPD)lS-31t-R +CC -1, ... ,
((SPDhs-31

Word count
TW = 1

Space count = 0,
word count = 0,
TW = 1

MSP

Affected: (SPD), (R+CC-l)
to (R), CC

Word count = 0

If there is a sufficient number of words in the stack to load
all of the specified registers, PLM operates as follows:

Result of PLM

0 0 0 0 Word count> 0

If the address of the elements within the stack (pointed to
by the top-of-stack address) is in the range 0 through lS,

PULL MULTIPLE
(Doubleword index alignment)

MODIFY STACK POINTER modifies the stack pointer
doubleword, located at the effective doubleword address
of MSP by the contents of register R. Register R must have
the following format:

(SPD)lS-31 - CC- SPD 1S_31 t
(SPD b3-47 + CC -

SPD33-47

{SPD)49-63 - CC -

SPD49-63
Push-Down Instructions (Non-Privi leged)

Bit positions 16 through 31 of register R are treated as a
signed integer, with negative integers in two's complement
form (i. e., a fixed-point halfword). The modifier is algebraically added to the top-of-stack address, subtracted
from the space count, and added to the word count in the
stack pointer doubleword. If, as a result of MSP, either
the space count or the word count would be decreased below 0 or increased above 2 15 _1, the instruction is aborted.
Then, the basic processor either traps to location X'42' or
sets the condition code to reflect the reason for aborting,
depending on the stack limit trap inhibits.

If CC 1, or CC3, or both CC 1 and CC3 are l's after
execution of MSP, the instruction was aborted but the pushdown stack limit trap was inhibited by the trap-on-space
inhibit (SPD32), by the trap-on-word inhibit (SPD4S), or
both. The condition code is set to reflect the reason for
aborting as follows:
2

Status of space and word counts

Word count> O.
Word count

If the modification of the stack pointer doubleword can be
successfully performed, MSP operates as follows:

The modifier in register R is algebraica"y added to the
current top-of-stack address (SPD15-31)t, to point to
a new top-of-stack location. (If the modifier is negative, it is extended to 17 bits by appending a highorder 1.)

The modifier is algebraica"y subtracted from the current space count (SPD33-47) and the result becomes
the new space count.

The modifier is algebraically added to the current
word count (SPD49-63) and the result becomes the new
word count.

The condition code is set to reflect the new status of
the new space count and new word count.

Trap: Push-down stack limit

(SPD)15_31 + (R)16_31SE- SPD 15_31

SPD 33 _47

(SPD)33_47 - (R)16-31 -

count + modifier

_1.

Word count + modifier < 0, and TW = 1 or
word count + modi fi er > 2 15 _1, and TW = 1.

Space count> O.

Space count

= O.

o - - - 0~spacecount-modifier<215_1.
-

Affected: (SPD), CC

~ word

= O.

Space count - modifier < 0, and TS = 1 or
space count - modifier> 2 15 _1, and TS = 1.

PUSH-DOWN INSTRUCTIONS (PRIVILEGED)
The computer has two privi leged push-down instructions:
PUSH STATUS (PSS) and PULL STATUS (PLS). These two instructions and a Status Stack Pointer Doubleword foci litate
the storing (pushing) or loading (pulling) of a particular
environment (contents of 16 general registers and Program
Status Words) into or out of a memory stack.

(SPD)49_63 + (R)16-31- SPD 49-63

STATUS STACK POINTER DOUBLEWORD
Condition code settings:
The Status Stack Pointer Doubleword (SSPD) always resides
2 3

4
0

:r. rce!

Result of MSP

rn6iiiCi}l

locations 0 and 1 and is dedicated

for

PSS

and PLS instructions. The format of parameters contained
within the Status Stack Pointer Doubleword are as follows:

Space count> 0,
word count> O.

Real Memory Location 0:
000

Space count> 0,
word count = O.
Instruction completed

o
o

Space count = 0,
word count> O.

Real Memory Location 1:

Space count = 0,
word count = 0,
__ ...1:&:
I.'VU"

I ~I

()

TOP OF STACK ADDRESS
t For real extended mode of addressing this is a 20-bit
field (12-31); for real and virtual addressing modes it is a
17-bit field (15-31).

Push- Down Instructions (Privi leged)

The Top of Stack Address (TSA) is always a 20-bit real memory word address and is never mapped. Depending upon

programming considerations, the initial TSA is a specific
value either as the result of a Mode 0, WRITE DIRECT
instruction or as the result of a PSS or PLS instruction, as
described below.
During each PSS instruction, the memory stack is accessed
28 times and the TSA is incremented by 1 before each access.
The first memory stack location accessed has a relative address equal to the initial TSA plus 1, ... , and the 28th memory stack location accessed has ci relative address equal to
the initial TSA plus 28. Although 28 memory stack locations are accessed in an ascending sequence, only 20 locations (as selected by the hardware) wi II contain the basic
processor environment. Eight locations' (whose contents are
designated as "indeterminate", in Figure 12) are reserved
and must not be used.
For each PLS instruction, access to the memory stack is
contingent upon the Word Count as described subsequently.
If access is permitted, the memory stack is accessed 28 times
and the TSA is decremented by 1 after each access. The
first memory stack location accessed by a PLS instruction
has a relative address equal to the initial TSA, the second
memory stack location accessed has a relative address equal
to the initial TSA minus 1, ... , and the 28th memory stack
location accessed has a relative address e'-'val to the initial
TSA minus 27. Although 28 memory stack "locations are
accessed in a descending sequence, the hardware selects
and pulls the contents of only 20 locations containing valid
information, as shown in Figure 12, and loaded into the
general registers and PSWs. The contents of eight locations
designated as indeterminate are ignored.
If the terminal (last) TSA for a PSS or PLS instruction is
not modified by a Mode 0 WRITE DIRECT instruction, it
may be used as the initial TSA for a subsequent PSS or PLS
instruction. Each PSS instruction causes the memory stack
to be increased by 28 word locations and each PLS instruction causes the memory stack to be decreased by 28 word
locations. The information is pushed and pulled on a last-in,
fi rst-out basi s.
Note:

The PLS instruction is contingent upon the Word
Count value, as described below.

appropriate memory stack locations as specified by the
TSA; however, subsequent values of the Space Count are
indeterminate.
During a PLS instruction, the Space Count is incremented
by 1 for each word pulled from the memory stack. If the
Space Count is incremented beyond a value of 32,767, bit
position 32 is set to 1 (signifying an overflow condition);
however, the PLS instruction continues (i. e., no trapping
occurs).

Note:

Once bit position ~2 has been set to a 1, it can be
reset to a 0 only by executing a Mode 0, WRITE
DIRECT instruction. That is, bit position 32 can
not be reset to a 0 by the decrementing process performed during a PSS instruction.

WORD COUNT
The Word Count field (bit positions 49-63) of the Status
Stack Pointer Doubleword is a 15-bit counter that may contain a value of 0 through 32,767. Depending upon programming considerations, the initial Word Count is a
specific value either as the result of executing a Mode 0,
WRITE DIRECT instruction or as the result of executing a
PSS or PLS instruction.
During a PSS instruction, the Word Count is incremented
by 1 for each word pushed into the memory stack. Thus,
the terminai Word Count for a PSS instruction exceeds the
initial Word Count by 28. If the Word Count value
exceeds 32,767, bit position 48 is set to a 1 (signifying
that an overflow condition has occurred); however, the
PSS instruction continues the stacking operation (i. e., no
trapping occurs).
If the initial Word Count for a PLS instruction is equal to
or greater than 28, the Word Count is decremented by 1 for
each word pulled from the memory stack and the terminal
Word Count will be 28 less than the initial Word Count.
Note that if bit position 48 was set to a 1 by a PSS instruction previously, it can not be reset to a 0 by the decrementing performed during a PLS instruction.

SPACE COUNT
The Space Count field (bit positions 33-47) of the Status
Stack Pointer Doubleword is a 15-bit counter that may contain a value of 0 through 32,767. Depending upon programming considerations, the initial Space Count is a
specific value e. ther as the result of executing a Mode 0,
WRITE DIRECT instruction or a PLS or PSS instruction.
During a PSS instruction, the Space Count is decremented
by 1 for each word pushed into the memory stack. If the
Space Count is decremented to a value of zero before all
the words have been pushed, the PSS instruction continues
(i. e., no trapping occurs). The environment is stored into

If the initial Word Count for a PLS instruction is equal to
zero, the parameters within the Status Stack Pointer Doubleword are neither effective nor affected by the PLS il)struction. However, default PSWs are loaded from real memory
locations 2 and 3.

If the initial Word Count for a PLS instruction is less than 28
and not equal to zero, the other parameters of the Status
Stack Pointer Doubleword are not effective and none of the
parameters are affected by the PLS instruction. Instead the
BP traps to location X' 4D' (instruction exception trap) and
TCC2 is set.
Push-Down Instructions (Privileged)

PSS Operations

PLS Operations

initial TSA -

(RO)

-27

(R1)

-26

(R2)

-25

(R3)

-24

(R4)

-23

(R5)

-22

(R6)

-21

(R7)

-20

(R8)

-19

+10

(R9)

-18

+11

(RlO)

-17

+12

(Rll )

-16

+13

(R12)

-15

+14

(R13)

-14

+15

(R14)

-13

+16

(R15)

-12

+17

-11

+18

-10

+19

-9

+20

-8

+21

-7

+22

-6

+23

-5

terminal TSA = initial TSA-28

+24
+25

(PSW1)

-3

+26

(PSW2)

-2

+27

(PSW3)

initial TSA +28

(PSW4)

-1
-

initial TSA

tAs a function of the hardware, the contents of these 8 locations are indeterminate after a PSS instruction and ignored by a PLS instruction. These
locations are reserved for future enhancements and must not be used.

Figure 12.

Typical 28-Word Portion of Memory Stack for PSS and PLS

Push-Down Instructions (Privileged)

PSS

PUSH STATUS

(Doubleword index alignment, privi leged)

PUSH STATUS loads new Program Status Words from an effective doubleword location and stores the current environment (current Program Status Words and contents of all
16 general registers) into a memory stack, as defined by the
Status Stack Pointer Doubleword. Note that the reference
address points to the memory location of the new PSWs.
The PSS instruction is used for three types of operations:
as a normal instruction in an ongoing program; as an interrupt instruction; and as a trap instruction. The effective
address of a PSS instruction is generated in one of the
following ways:
PSS - normal instruction (see first instruction diagram)
When a PSS instruction is encountered in the course of
execution of normal programs, the effective address is
generated according to the rules for addressing then in
effect as described by the currently active PSWSi that is, the
basic processor is operating in real, real extended, or virtual
addressing mode. The flags in bit positions 9 and 10 have
no effect and must be coded as zeros.

Depending upon the type of addressing, the reference
address of the PSS instruction is converted into an effective
virtual doubleword address, as described under IIpSS Address
Calculations", in Chapter 2. Except for the Register Block
Pointer field (bit positions 56-59) and the interrupt group
inhibit bits (bit positions 37, 38, and 39), the contents of
the effective location are always loaded as the new PSWs.
If the LP flag (bit 8 of the PSS instruction) is a 1, the
Register Block Pointer of the new PSWs is also loaded. If
the LP flag is a 0, the old Register Block Pointerisretained.
The interrupt group inhibit bits of the new PSWs are "ORed ll
with the corresponding bits of the old PSWs.
The current environment (comprised of 20 words) is stored
in memory stack locations having the following relative
addresses: initial TSA+1 through initial TSA+16, initial
TSA+25, and initial TSA+26. Memory stack locations
having relative addresses of init'ial TSA+17 through initial
TSA+24, initial TSA+27, and initial TSA+28 are reserved
and the contents are indeterminate.
The parameters of the Status Stack Pointer Doubleword (as
contained within working registers) are appropriately mod, ifi ed to reflect the progress of the PSS instruction and
conditions of the memory stack (i. e., the TSA and Word
Count are incremented and the Space Count is decremented
for each memory word location accessed, as described under
Status Stack Pointer Doubleword).
If the Word Count exceeds 32,767 (maximum count for
bits 49-63) or if the Space Count is reduced to zero before
the PSS instruction is completed, the stacking operations
continue until 28 words have been pushed (i. e., no trapping
'I".
,,..
._. An-_
occurs). VVnen me vvora ~ounr exceeas ';>£, l U I , or I 'TO I~
set to a 1. Attempting to decrement the Space Count below
zero causes the Space Count to become indeterminate.
. . . . . . . 1

PSS - interrupt instruction (see second instruction diagram)
A PSS instruction (in an interrupt location) executed as a
result of an interrupt is called an interrupt instruction. In
the interrupt execution sequence, the 20-bit reference
address is always real, independent of the map invoking
bit in the PSWs. There is no indexing possible since the
designator field is preempted by the reference address.
Indirect addressing is permitted with precisely the same
constraints. The indirect address word contains a 20-bit
real address with the same properties as the reference address described above. The flags in bit positions 9 and 10
have no effect and must be coded as zeros.

I"\n~'~

Affected: (PSWs), CC, Memory Stack, Status Stack Pointer
Doubleword.

(PSWs) and CC:
EDO_3-CCi
ED4-7- FR, FS, FZ, FN;
ED8-MS;
ED9-MMi

PSS - trap instruction (see second instruction diagram)

ED10-DM;
EDll-AMi

A PSS instruction (in a trap location) executed as a result
of a trap entry operation is called a trap instruction. In a
trap execution sequence, the 20-bit reference address may be
either a real address or a virtual address according to the
map invoking bit in the PSWs. There is no indexing possible since the index field is used for addressing. If indirect
addressing is specified, the effective address is generated
according to the rules for addressing then in effect as described by the currently active PSWs. Bit positions 9 and 10
must be coded as zeros.

ED15-31 -IAi
ED32-35-WKi
ED37-39 u CI, II, EI CI, II, EI
(Note: IIU" represents inclusive OR. )
EQ56-59- RP only if (IS) = 1
ED60-RA
ED61-MA
Push-Down Instructions (Privi leged)

Memory Stack:
(General Register n) (initial TSA+{n+ 1) where n has
ascending values from 0 through 15.
PSW1 -

(initial TSA+25)

PSW2 -

(initial TSA+26)

Status Stack Pointer Doubleword:
TSA+1 TSA unti I terminal TSA=initial TSA+28;
Word Count + 1 - Word Count unti I terminal Word
Count = initial Word Count + 28, (if Word Count>
32,767, set bit 48 to 1);
Space Count - 1 - Space Count until terminal Space
Count = initial Space Count - 28 (if Space Count = 0,
Space Count - 1 is indeterminate).

PLS

The clearing and arming or disarming the highest priority
interrupt level currently active is dependent upon the
coding of the CL and AD flags (bit positions 10 and 11,
respectively) of the PLS instruction. Jf the CL flag is a 0,
the interrupt level is not affected. If the CL flag is a 1
and the AD flag is a 0, the interrupt level is set to the disarmed state. If the CL flag is a 1 and the AD flag is a 1,
the interrupt level is set to the armed state. Note that if
the interrupt level is to be modified (CL flag is set to a 1),
the instruction may be delayed unti I the interrupt system is
available.
Summary description of CL and AD flags and effect on interrupt level and PDF flag follows:
Bit Positions
10 (CL)

11 (AD)

Function

PULL STATUS (nonaddressing, privi leged)

PULL STATUS, in conjunction with the Status Stack Pointer
Doubleword, may cause one or more of the following functions to be performed:
.
1.

Selectively load a new environment (PSWs and 16 general registers) from the memory stack; or,

Selectively load default PSWs from dedicated memory
locations; and,

Selectively clear and arm or clear and disarm the
highest priority level currently in the active state.

If the initial Word Count of Status Stack Pointer Doubleword
is equal to or greater than 28, a new environment is
loaded from the memory stack. Twenty eight memory stack
I __

11, EI) are generated by "ORing" the old CI, II, EI bits
with the contents of bits 37, 38, and 39 of the PSWs as
pulled from the memory stack.

~~:

IV,,"YIIVII;) ""'Ie;;

___

~~~~..J

..J~~_~_..J:_~

~~_

\",n... \..o'C;);)CU

III

""C;;';»""CII\..lIlI~

;)'C'"fUCII"",,C,

•• ____

No effect upon interrupt level
or PDF flag.
Reset PDF flag

Clear and disarm interrupt level

Clear and arm interrupt level

If the initial Word Count is zero! default PSWs are loaded
from real memory locations 2 and 3 and the other parameters
of the Status Stack Pointer Doubleword are not effective
and no parameters are affected.
Portions of the new PSWs (interrupt inhibit group bits and
the Register Block Pointer) may be selected or generated in
the following manner:

~~~_~:_~

"1\".I111I1~

If the LP flag (bit 8) of the PSL instruction is a 1, the new

at a location having an address equal to the initial TSA
(part of the Status Stack Pointer Doubleword). The hardware selects and loads the contents of 20 memory locations
into the general registers and as the PSWs (i. e., the contents of locations having relative addresses of initial TSA-2,
initial TSA-3, and initial TSA-12 through initial TSA-27).
The contents of 10 memory stack locations (having relative
addresses equal to initial TSA, initial TSA-1, and initial
TSA-4 through initial TSA-ll) are ignored.

The CI, II, and EI bits of the old PSWs are "ORed" with
the contents of bit positions 37, 38, and 39 of the default
PSWs to generate the CI, II, and EI bits of the new PSWs.

Portions of the new PSWs are dependent upon the LP flag
(bit 8) of the PLS instruction as well as the interrupt group
inhibit bits of the old PSWs and the PSWs as pulled from
the memory stack. If the LP flag is a 1, a new Register
Block Pointer (as pulled from the memory stack) is loaded
as part of the new PSWs. If the LP flag is a 0, the old Register Block Pointer is retained as the Register Block Pointer
for the new PSWs. The new interrupt group inhibit bits (CI,

Depending upon the coding of the CL and AD flags (bit
positions 10 and 11: respectively) of the PLS instruction;
the highest priority interrupt level currently in the active
state may be modified. If the CL flag is a 0, the interrupt
level is not affected. If the CL flag is ') 1 and the AD flag
is a 0, the interrupt level is cleared and placed into the
disarmed state. If the CL flag is a 1 and the AD flag is
a 1, the interrupt level is cleared and placed into the

Push-Down Instructions (Privileged)

Register Block Pointer will be as obtained from the default
PSWs. If the LP flag is a 0, the Register Block Pointer of
the old PSWs is retained as the Register Block Pointer for
the new PSWs.

armed state. Note that if the interrupt level is to be
modified (i. e., the CL flag is a 1), the instruction may be
delayed unti I the interrupt system is avai lab Ie.

Note:

A summary description of the action on the interrupt level
as a function of the CL and AD flag is as follows:
Bit Positions
10 (CL)

11 (AD)

Function
No effect upon interrupt level
or PDF flag
Reset PDF flag

Clear and disarm interrupt level
Clear and arm interrupt level

If the word count ~ 28, the effective doubleword
(ED) is pulled from memory stack locations (relative addresses initial TSA-24 and initial TSA+l).
If the word count=O, the ED is pulled from real
memory locations 2 and 3.

Status Stack Pointer Doubleword: (Only if initial Word
Count ~ 28)
TSA-1 -TSA until terminal TSA = initial TSA-28;
Word Count - 1 Word Count unti I terminal Word.
Count = initial Word Count - 28 (if initial Word Count
> 32,767, bit 48 not affected); and,
Space Count + 1 Space Count unti I terminal Space
Count = initial Space Count + 28 (if Space Count
> 32,767, then set bi t 32 to 1).
Interrupt System:

If the initial Word Count within the Status Stack Pointer
Doubleword is less than 28 and not equal to 0, the basic
processor traps to location XI 4D 1 (instruction exception
trap) without loading any new status or affecting the parameters of the Status Stack Pointer Doubleword and the
TCC2 bit is set to 1.
Affected: If word count ~ 28,
(PSWs), CC,
Status Stack Pointer
Doubleword
Interrupt System if
(1)10=1.

If (1)10

If (1)10
level.

Traps: Instruction exception, if word count
is less than 28 and
not 0; nonexistent
instruction if
bit 0=1.

if word count = 0, (PSWs), CC, and inTerrupT
System, if I(lOt 1.
(PSWs) and CC

= 1 and

(1)11

= 1,

= 1 and

(1)11 = 0, clear and disarm interrupt

clear and arm interrupt

level.

EXECUTE/BRANCH INSTRUCTIONS
The following instructions can cause the basic processor to
exeCUTe inSTrucTions in an order oTher Than Thor or sequentially ascending instruction addresses:
Instruction Name

Mnemonic

ED _ -CC;
O3

Execute

EXU

EDS_7 -

Branch on Conditions Set

BCS

ED -MS;

Branch on Conditions Reset

BCR

ED -MM;
9

Branch on Incrementing Register

BIR

Branch on Decrementing Register

BDR

Branch and Li nk

BAL

FS, FZ, FN;

ED
ED

lO
ll

DM;

-AM;

_ 1S 31

IA;

_ -WK
32 3S

ED37-39 u CI, II, EI CI, II, EI
(Note: IIU represents inclusive OR.)
Il

ED
ED
ED

_ S6 S9

60
61

-RA
-MA

RP only if (1)8 = 1

The EXECUTE instruction can be used to insert another instruction into the program sequence, and the branch instructions can be used to alter the program sequence, either
unconditionally or conditionally. If a branch is unconditional (or conditional and the branch condition is satisfied),
the instruction pointed to by the effective address of the
branch instruction is normally the next instruction to be
executed. If a branch is conditional and the condition
for the branch is not satisfied, the next instruction is normally taken from the next location, in ascending sequence,
after the branch instruction.

Execute/Branch Instructions

NONALLOWED OPERATION TRAP DURING EXECUTION
OF BRANCH INSTRUCTION
The next instruction after a branch instruction may reside
in two possible places: the location following the branch
instruction or a location designated by the branch instruction. Either of these two locations may be in a protected
memory region or in a region that is physically nonexistent.
The execution of the branch does not cause a trap un less
the instruction that is actually to follow the branch instruction is in a protected or nonexistent memory region. Traps
do not occur because of any anticipation on the part of the
hardware.

In the real extended addressing mode, a 20-bit address may
be used as a branch address via indexing or indirect addressing. If such a branch address, (A), is beyond the first
128K of real memory, the instruction at (A) will be executed,
but the next instruction address will be (A+l) in the original
128K block unless (A) contains a branch instruction. Note
that with this exception all instructions executed in the
real extended addressing mode must lie in the first 128K of
rea I memory.

EXU

EXECUTE
(word index alignment)

A nonallowed operation trap condition during execution of
a branch instruction wi II occur for the following reasons:
1.

The branch instruction is indirectly addressed and the
branch conditions are satisfied, but the address of the
location containing the direct address is either nonexistent or unavai lable for read access to the program
in the slave mode.
The branch instruction is unconditional (or the branch
is conditional and the condition for the branch is satisfied), but the effective address of the branch instruction is either nonexistent or unavai lable for instruction
or read access to the program (in slave or masterprotected mode).

If either of the above situations occurs, the basic processor
aborts execution of the branch instruction and executes a
nonallowed operation trap.

Prior to the time that an instruction is accessed from memory for execution, bit positions 15-31 of the program status
words contain the virtual address of the instruction, referred
to as the instruction address. At this time, the basic processor traps to location X ' 40 ' if the actual address of the
instruction is nonexistent or instruction-access protected,
If the instruction address is existent and is not instructionaccess protected, the instruction is accessed and the instruction address portion of the program status words is
incremented by 1, so that it now contains the virtual address
of the next instruction in sequence (referred to as the updated instruction address).

EXECUTE causes the basic processor to access the instruction
in the location pointed to by the effective address of EXU
and execute the subject instruction. The execution of the
subject instruction, including the processing of trap and
interrupt conditions, is performed exactly as if the subject
instruction were initially accessed instead of the EXU instruction. If the subject instruction is another EXU, the
basic processor executes the subject instruction pointed to
by the effective address of the second EXU as described
above. Such "chains" of EXECUTE instructions may be of
any length, and are processed (without affecting the updated
instruction address) until an instruction other than EXU is
encountered. After the final subject instruction is executed,
instruction execution proceeds with the next instruction in
sequence after the initial EXU (unless the subject instruction is an LPSD or XPSD instruction, or is a branch instruction and the branch condition is satisfied).

If an interrupt activation occurs between the beginning of
an EXU instruction (or chain of EXU instructions) and the
last interruptible point in the subject instruction, the BP
processes the interrupt-servicing routine for the active
interrupt level and then returns program control to the EXU
instruction (or the initio! instruct:cn of a chain of EXU
instructions), which is started anew. Note that a program
is interruptible after every instruction access, including accesses made with the EXU instruction, and the interruptibi lity of the subject instruction is the same as the normal
interruptibility for that instruction.
If a trap condition occurs between the beg inn ing of an EXU

If a trap condition occurs during the execution sequence of
any instruction, the basi c processor decrements the updated
instruction address by 1 and then traps to the location assigned to the trap condition. If neither a trap condition
r10r a satisfied branch condition occurs during the eXecutiOI'
of an instruction, the next instruction is accessed from the
location Pointed to by the updated instruction address. If
a satisfied branch condition occurs during the execution of
a branch instruction (and no trap condition occurs), the
next instruction is accessed from the location pointed to by
the effective address of the branch instruction.

Execute/Branch Instructions

instruction (or chain of EXU instructions) and the completion of the subject instruction, the basic processor traps to
the appropriate trap location. The instruction address stored
by the XPSD instruction in the trap location is the address
of the EXU instruction (or the initial instruction of a chain
of EXU instructions).
Affected: Determined by
subject instruction

Traps: Determined by
subject instruction

Condition code settings: Determined by subject instruction.

BCS

BRANCH ON CONDITIONS SET
(Word index alignment)

BRANCH ON CONDITIONS SET forms the logical product
(AND) of the R field of the instruction word and the current
condition code. If the logical product is nonzero, the
branch condition is satisfied and instruction execution proceeds with the instruction pointed to by the effective address of the BCS instruction. However, if the logical product is zero, the branch condition is unsatisfi ed and instruction execution then proceeds with the next instruction in
normal sequence.

BIR

BRANCH ON INCREMENTING REG ISTER
(Word index alignment)

BRANCH ON INCREMENTING REGISTER computes the
effective virtual address and then increments the contents
of general register R by 1. If the result is a negative value,
the branch condition is satisfied and instruction execution
then proceeds with the instruction pointed to by the effective address of the BIR instruction. However, if the result
is zero or a positive va lue, the branch condition is not satisfied and instruction execution proceeds with the next instruction in normal sequence.
Affected: (R), (IA)

(R) + 1 -

Affected: (IA) if CC n R f 0
If CC n (1)8-11

"10,

EVA 15-31 -

If CC n (I)8-11

= 0,

IA not affected

If the R field of BCS is 0, the next instruction to be executed after BCS is always the next instruction in ascending
sequence, thus effectively producing a "no operation"
instruction.

BCR

If (R)O

= 1,

EVA 15 _31 -IA

If {R)O

= 0,

IA not affected

BRANCH ON CONDITIONS RESET
(Word index ailgnment)

If the branch condition is satisfied and if the effective address of BIR is either unavailable to the program (slave or
master-protected mode) for instruction access or is nonexistent, the basic processor aborts execution. of the BIR
instruction and traps to location X'40'. In this case, the
instruction address stored by the XPSD instruction in location X'40' is the virtual address of the aborted BIR instruction. If the basic processor traps because of instruction
access protection, register R will contain the value that
eXisted rust before the BIK execution (I.e., updated instruction address). If a memory parity error occurs due to the
accessing of the instruction to whi ch the program is branching, the basic processor aborts execution of the BIR and
traps to location X' 4C' with register R unchanged.

BOR
BRANCH ON CONDITIONS RESET forms the logical product (AND) of the R field of the instruction word and the
current condition code. If the logical product is zero, the
branch condition is satisfied and instruction execution then
proceeds with the instruction pointed to by the effective
address of the BCR instruction. However, if the logical
product is nonzero, the branch condition is unsatisfied and
instruction execution then proceeds with the next instruction in normal sequence.

Affected: (IA) if CC n R = 0
If CC n (I)8-11

= 0,

EVA 15-13 -

If CC n (I)8-11

10,

IA not affected

BRANCH ON DECREMENTING REGISTER
(Word index alignment)

BRANCH ON DECREMENTING REGISTER computes the
effective virtual address and then decrements the contents
of general register R by 1. If the result is a positive value,
the branch condition is satisfied and instruction execution
then proceeds with the instruction pointed to by the effective address of the BDR instruction. However, if the result
is zero or a negative value, the branch condition is unsatisfied and instruction execution proceeds with the next instruction in normal sequence.
Affected: (R), (IA)

If the R field of BCR is 0, the next instruction to be executed after BCR is always the instruction located at the
effective address of BCR, thus effectively producing a
"branch unconditionally" instruction.

(R) - 1 -

If {R)O = 0 and {R)1-31
If (R)O

= 1 and

(R)

= 0,

10,

EVA 15 _31 -

IA not affected
Execute/Branch Instructions

If the effective address of BDR is unavailable to the program
(slave or master-protected mode) for instruction access and
the branch condition is satisfied, or if the effective address
of BDR is nonexistent, the basi c processor aborts execution
of the BDR instruction and traps to location X'40'. In this
case, the instruction address stored by the XPSD instruction
in location X'40' is the virtual address of the aborted BDR
instruction. If the basic processor traps because of instruction access protection, register Rwi" contain the value that
existed just before the BDR instruction. If a memory parity
error occurs due to the accessing of the instruction to whi ch
the program is branching, the basic processor aborts execution of the BDR and traps to location X'4C' with register R
unchanged.

BAL

BRANCH AND LINK
(Word index alignment)

BRANCH AND LINK determines the effective virtual address, loads the updated instruction address (the virtual address of the next instruction in normal sequence after the
BAL instruction) into bit positions 15-31 of general register R, clears bit positions 0-14 of register R to O's and then
replaces the updated instruction address with the effective
virtual address. Instruction execution proceeds with the
instruction pointed to by the effective address of the BAL
instruction.

CALL INSTRUCTIONS
Each of the four CALL instructions causes the basic processor
to trap to a specific location for the next instruction in sequence. The four CALL instructions, their mnemonics, and
the locations to wh i ch the basi c processor traps are:
Instruction
Name

Mnemonic

Trap
Location

CALL 1

CAll

X'48'

CALL 2

CAL2

X'49'

CALL 3

CAL3

X'4A'

CALL 4

CAL4

X'4B'

Each of these four trap locations must contain an EXCHANGE
PROGRAM STATUS WORDS (XPSD) instruction. Execution
of XPSD in the trap location for a CA lL instruction is described under "Control Instructions, XPSD Exchange Program Status Words". If the XPSD instruction is coded with
bit position 9 set to 1, the next instruction (executed after
the XPSD) is taken from one of 16 possible locations, as
designated by the value in the R field of the CALL instruction. Each of the 16 locations may contain an instruction
that causes the basic processor to branch to a specific
routine; thus, the four CALL instructions can be used to
enter any of as many as 64 unique routines.
The effective address of either a direct or indirect CALL
instru ction is not used for a memory referen ce and I therefore, cannot cause a trap.

CALI
The BAL instruction in real extended addressing will store
the full address of the next instruction in the specified R
register. Positions 0-9 of the specified register wi" be set
equal to zero.

CALL 1 causes the basic processor to trap to location X'48'.

Affected: (R) I (IA)
IA -

R15 - 31 ; 0 -

RO-l~ EVA 15 _31 -

If the effective address of BAL is unavailable to the program
(slave or master-protected mode) for instruction access and
the branch condition is satisfied, or if the effective address
of BAL is nonexistent, the basic processor aborts execution
of the BA L instruction and traps to location X'40' (nonallowed
operation trap). In this case, the instruction address stored
by the XPSD instruction in location X'40' is the virtual address of the aborted BAL instruction. If the basic processor
traps because of instruction access protection, register Rwill
contain the updated instruction address. If a memory parity
error occurs due to the accessing of the instruction to which
the program is branching, the basic processor aborts execution of the BA L and traps to location X'4C' with register R
changed to the updated instruction address.

CALL 1
(Word index alignment)

Call Instruct; ons

CAL2

CALL 2
(Word index alignment)

CALL 2 causes the basic processor to trap to location X'49'.

CAL3

CA.LL 3
(Word index alignment)

CA LL 3 causes the basi c processor to trap to location X '4A',

CAL4

CALL 4
(Word index al ignment)

Bit
Position

Designation

Master/slave mode control

Memory map mode control

Fixed-point arithmetic
overflow trap mask

15-31

Instruction address

32-35

Write key

Counter interrupt group
inhibit

I/O interrupt group inhibit

External interrupt inhibit

CALL 4 causes the basic processor to trap to location X'4B'.

CONTROL INSTRUCTIONS
The following privileged instructions are used to control the
basic operating conditions of the basic processor:
Mnemonic

Instruction Name

Function

Load Program Status Words

LPSD

58-59

Regi ster pointer

Exchange Program Status Words

XPSD

Load Register Pointer

LRP

Mode altered

Move to Memory Contro I

MMC

Load Real Address

LRA

Load Memory Status

LMS

Wait

WAIT

Read Direct

Write Direct

The detailed functions of the various portions of the program status words are described in Chapter 2, .. Program
Status Words".

LPSD
If execution of any control instruction is attempted while
the basic processor is in the slave mode (i. e., while bit 8
of the current program status words is a 1), the basic processor unconditionally traps to iocation X i 4-0' prior to
executing the instruction.

PROGRAM STATUS WORDS
Program status words have the following structure when
stored in memory:

LOAD PROGRAM STATUS WORDS
(Doubleword index alignment, privileged)

LOAD PROGRAM STATUS WORDS replaces bits othrough 39,
60 and 61 of the current program status words with bits 0
through 39, 60 and 61 of the effective doubleword.
Control bits used in the LPSD instruction are:
Bit
Position

Designation

Control Function

Load pointer control

Clearing of interrupt level

Armed/disarmed state

The following conditional operations are performed:
Bit
Position

Designation

If bit position 8 (LP) of LPSD contains a 1, bits 56
through 59 (register pointer) of the current program
status words are replaced by bits 56 through 59 of the
effective doubleword; if bit 8 of LPSD is a 0, the current register pointer value remains unchanged.

If. bit position 10 (CL) of LPSD contains a 1, the highest
priority interrupt level currently in the active state is
cleared (i. e., reset to either the armed state or the disarmed state); the interrupt level is armed if bit 11 (AD)

Function

0-3

Condition code

Floating round

Floating significance mask

Floating zero mask

Floating normal ize mask

Control Instructi ons

of lPSD is a 1, or is disarmed if bit 11 of lPSD is a O.
If bit 10 of lPSD is a 0, no interrupt level is affected
in any way, regardless of whether bit 11 of lPSD is 1
or O. If bit 10 of the lPSD is a 0 and bit 11 of lPSD
is 1, the PDF flag is cleared. (Interrupt levels are described in detai I in Chapter 2, "Interrupt System". )

load pointer
control

All XPSDs

Clear and arm interrupt level.

Address Increment

Trap XPSD

Clear PDF flag.

Addressing type

All XPSDs

No control action.

The effective address of an XPSD instruction is generated
in one of the following ways:

The PDF flag is normally reset by the last instruction
of a trap routine, which is an lPSD instruction having
bit 10 equal to 0 and bit 11 equal to 1.

Affected: (PSWs), interrupt system if (I) 10

CC; ED _ 5 7

-MS· ED '
9

EDll -

AM;

_
15 31

IA; ED

_
37 39

CI, II, EI; if (1)8 = 1, ED

WK;

XPSD (interrupt instruction)
_
56 59

1 and (1) 11 = 1, clear and arm interrupt

If (1) 10

If (1)10

= 1 and (I}ll = 0,

clear and disarm interrupt

EXCHANGE PROGRAM STATUS WORDS
{Doubleword index alignment, privileged}

EXCHANGE PROGRAM STATUS WORDS stores the currently active PSWs in the doubleword location addressed by
the effective address of the XPSD instruction. The following doubleword is then accessed from memory and loaded
into the active PSWs registers.

Control Instructi ons

When an XPSD instruction is encountered in the course of
execution of norma I programs, the AT· (bit 10) of the instruction determines the type of addressing to be used.

If AT = 1, the reference address is 17 bits (15-31). Address
calculations are according to standard addressing rules as
determined by the current PSWs. Indexing and indirect addressing are allowed.

MM·
'

_ 32 35

XPSD (normal instruction)

If AT = 0, the reference address is 20 bits (12-31). Indexing is not allowed. Indirect addressing is allowed with the
same constraints as the reference address. Addressing is
always real, independent of the current PSWs.

FS,FX,FN;

XPSD

Where used

These portions of the effective doubleword that correspond
to undefined fields in the program status words are ignored.

Control
Function

8
Clear and disarm interrupt level.

ED _ O3

Designation

Function

Control bits used in the XPSD instructions are:
Bit
Position

Bit position
10 {Cl}
11 {AD}

The XPSD instruction is used for three distinct types of
operations: as a norma I instruction in an ongoing program;
as an interrupt instruction; and as a trap instruction.

An XPSD instruction (in an interrupt location) executed as
a result of an interrupt is called an interrupt instruction.
The type of addressing to be used is determined by the basic
processor mode and the AT (bit 1O) of the instruction.
In the extended addressing mode (MA = 1 and MM = 0), the
AT bit is used to determine the type of addressing to be
used. If AT = 0, the referen ce address is 20 bits (12-31).
Indexing is not allowed. Indirectaddressing is allowed with
the same constraints as the reference address. Addressing is
always real, independent of the current PSWs. If AT = 1,
the reference address is 17 bits (15-31). Address calculations are according to standard addressing rules as determined by the current PSWs. Indexing and indirect addressing
are allowed.
When the addressing mode is not extended addressing, the
reference address is 20 bits (12-31). If AT = 0, indexing
is not allowed. Indirect addressing is allowed with the
same constraints as the reference address. Addressing is
always real, independent of the current PSWs. If AT = 1,
the 20-bit reference address is subject to PSWs bit 9,
as is the contents of the indirect address if indirect is
specified.

memory control feature, CC2 and CC4 are both
set to lis; if bit 9 of XPSD is a 1, the instruction
address of the new program status words is incremented by 5.

XPSD (trap instruction)
An XPSD instruction (in a trap location) executed as a result
of a trap entry operation is called a trap instruction. Addressing is the same as for the interrupt XPSD (see above).
2.
The following additional operations are performed on the
new program status words if, and only if, the XPSD is being
executed as the result of a nonallowed operation (trap to
location X ' 40 ' ) or a CAll instruction (trap to location X ' 48 I ,
X ' 49', X' 4A', or X'4B'):
1.

CALL instructions - the following additional functions
are performed when XPSD is being executed as a result of a trap to location X'48 1 , X'49 1 , X' 4A', or
X'4B'.
a.

The R field of the CALL instruction causing the
trap is logically inclusively ORed into bit positions 0-3 (CC) of the new PSWs.

If bit position 9 of XPSD contains a 1, the R field
of the CALL instruction causing the trap is added
to the instruction address portion of the new PSWs.

Nonallowed operations - the following additional functions are performed when XPSD is being executed as a
result of a trap to location X' 40':
a.

Nonexistent instruction - if the reason for the trap
condition is an attempt to execute a nonexistent
instruction, bit position Oof the new program status
words (CC 1) is set to 1. Then, if bit 9 (AI) of
XPSD is a 1, bit positions 15-31 of the new program status words (next instruction address) are
incremented by 8.

Nonexistent memory address - if the reason for the
trap condition is an attempt to access or write into
a nonexistent memory region, bit position 1 of the
new program status words (CC2) is set to 1. Then,
if bit 9 of XPSD is a 1, the instruction address portion ofthe new program status words is incremented
by 4.
Privileged instruction violation - if the reason for
the trap condition is an attempt to execute a privileged instruction while the basic processor is in
the slave mode, bit position 2 of the new program
status words (CC3) is set to 1. Then, if bit position Oof XPSD is 1, the instruction address portion
of the new program status words is incremented by 2.
Memory protection violation - if the reason for the
trap condition is an attempt to read from or write
into a memory region to which the program does
not have proper access, bit position 3 of the new
program status words (CC4) is set to 1. Then, if
bit 9 of XPSD is a 1, the instruction address portion of the new program status words is incremented
by 1.

Watchdog timer, parity error, or instruction exception
trap - the following additional functions are performed
when XPSD is being executed as a result of a trap to
location X'46 I, X'4C', or X'4D', respectively.
a.

The contents of TCC 1-4 are logically inclusively
ORed into bit positions 0-3 (CC) of the new PSWs.

If bit position 9 of XPSD contains a 1, the contents
of TCC 1-4 are added to the instruction address
portion of the new PSWs.

If bit position 9 of XPSD contains a 0, the instruction address portion of the new PSWs always remains at the vaiue
established by the second effective doubleword. Bit position 9 of XPSD is effective only if the instruction is being
executed as the result of a nonal lowed operation, CALL
instruction watchdog timer, parity error, or instruction exception trap. Bit position 9 of XPSD must be coded with a
o in all other cases; otherwise, the results of the XPSD
instruction are undefined.
The current program status words are stored in the doubl eword location pointed to by the effective address of XPSD
in the following form:

Program Status Words
There are certain circumstances under which two
of the above nonal lowed operations can occur
simultaneously. The following operation codes
(including their counterparts) are considered to be
bothnonexistentandprivileged: XIOC I and X'OD'.
If either of these operation codes is used as an instruction while the basic processor is in the slave
or master-protected mode, CC 1 and CC3 are both
set to lis; if bit 9 of XPSD is a 1, the instruction
address portion of the new program status words is
incremented by 10. If an attempt is made to access
or write into a memory region that is both nonexistent and prohibited to the program by means of the

The current program status words (as illustrated above) are
replaced by new program status words as described below.
1.

The effective address of XPSD is incremented by 2 so
that it points to the next doubleword location. The
contents of the next doubleword location are referred
to as the second effective doubleword, or ED2.
Control Instructions

Bits 0-35, 60, and 61 of the current program status
words are unconditionally replaced by bits 0-35, 60,
and 61 of the second effective doubleword. The affected
portions of the program status words are:

Bit
Position
0-3

Designati on

Function
Condi ti on code

FR, FS, FZ,
FN

Floating control

Master/slave mode control

Mapping mode control

Fixed-point arithmetic trap
mask

15-31

Instructi on address (real or
vi rtual)

32-35

Write key

Mode altered

A logical inclusive OR is performed between bits 37
through 39 of the current program status words and
bits 37 through 390f the second effective doubleword.
Bit
Position

Designation

Function

Counter interrupt inhibit

I/O interrupt inhibit

External interrupt inhibit

it any (or a i i) of bits 37, 38, or 39 of the second effective doubleword are O's, the corresponding bits in
the current program status words remain unchanged; if
any (or all) of bits 37, 38, or 39 of the second effective doubleword are l's, the corresponding bits in the
current program status words are set to l's. See "Interrupt System", Chapter 2, for a detailed discussion
of the interrupt inhibits.

If bit position 8 (LP) of XPSD contains a 1, bits 58
and 59 (register pointer) of the current program status
words are replaced by bits 58 and 59 of the second
effective doubleword; if bit 8 of XPSD is a 0, the current register pointer value remains unchanged.

Affected: (EDL), (PSWs)

If (I) 10 = 1, trap or interrupt instructions only, effective
address is subject to current active addressing mode.
96

PSD -

EDL

ED2 _ -CC; ED24_7 0 3

4-7

If (I) 10 = 0, trap or interrupt instructions only, effective
address is independent of current active addressing mode.

Controi Tnstructions

ED28 -

MS; ED29 AM; ED

ED211 ED232-35 ED2 37 _

FR,FS,FZ,FN

_
15 31

u CI,II,EI -

If (1)8 = 1, ED2

CI,II,EI

_
58 59

If (1)8 = 0, RP not affected

If nonexistent instruction, 1 IA+8-IA

CC 1 then, if (1)9 = 1,

If nonexistent memory address, 1 {I)9 = 1, IA + 4 IA

CC2 then, if

If privileged instruction violation, 1 (1)9 = 1, IA + 2 IA

If memory protection violation, 1 IA + 1 IA

CC3 then, if

CC4 then, if {I)9 = 1,

If CALL instruction, CC u CALL _
8 11
{I)9 = 1, IA + CALL 8 _
IA
11

CC then, if

If (1)9 = 0, IA not affected
If watchdog timer, parity error, or instruction exception
trap, ED20 _3 u TCCl-4 -CCl-4 then, if (1)9= 1,
IA + TCCl-4 IA

LRP

LOAD REGISTER POINTER
(Word index alignment, privileged)

LOAD REGISTER POINTER loads bits 24-27 of the effective
word into the register pointer {RP} portion of the current
program status words. Bit positions
through 23 and 28
through 31 of the effective word are ignored, and no other
portion ofthe program status words is affected. If the LOAD
REG ISTER POINTER instruction attempts to load the register
pointer with a vaiue that points to a nonexistent biock of
general registers, the basi c processor traps to location X'4D'.

Affected: RP
EW

_
24 27

Trap: Instruction exception
RP

MOVE TO MEMORY CONTROL INSTRUCTIONS
The following instructions may be used to selectively move
a string of control words from a control image area to specified memory control registers:

Normally, bit positions 15-31 may be ignored insofar as the
operation of the MMC instruction is concerned. The results
of the instruction are the same whether MMC is indirectly
or directly addressed. However, if MMC is indirectly addressed and the indirect reference address is nonexistent,
the nonallowed operation trap (location X' 40 ' ) is activated.

Instruction Name

Mnemonics

Move to Memory Control

MMC

Load Map (8-bit format)

LMAP

Load Map (11-bit format)

LMAPRE

Load Protection Code

LPC

Depending upon the type of addressing, the contents of
register R may be as follows:

Load Locks (2-bit format)

LLOCKS

If MA

= 0,

Load Locks (4-bit format)

LLOCKSE

If MA

= 1 and

MMC

MOVE TO MEMORY CONTROL
(Word index alignment, privileged, continue
after interrupt)

The MMC instruction may be used to perform any move to
memory control operation. Depending upon the type and
format of the control image, the move to memory control
operation may be performed either by an MMC instruction
with a specific value in the control field (bit position 12-14)
or by a special purpose instruction (i. e., LMAP, LMAPRE,
LPC, LLOCKS, or LLOCKSE), as shown below:
Type and format of
control image to be
loaded

Alternate
Instruction
Mnemonic

Memory write protection
locks (2-bit format)

LLOCKS

Memory write protection
locks (4-bit format)

LLOCKSE

Access protection
(always 2-bit format)

LPC

Memory map (8-bit
format)

LMAP

Memory map (ll-bit
format)

LMAPRE

Control Field of
MMC instruction:
Bit positions
12

contents of register Rare:

= 0,

the contents of register Rare:

In either case, the Control Image Address is the virtual address of a control word within the control image area to be
loaded into a block of memory control registers, as specified
by the contents of register Ru 1.
Depending upon the type of control image being loaded,
the contents of register Ru 1 may be in one of the following
three formats:
For loading memory map image (either 8-bit or 11-bit format), contents of register Ru 1 are:

The R field, which must be coded with an even value, designates an even-odd pair of general registers (R and Ru1)
that contain additional control information required by the
MMC instruction. If the R field is coded with an odd value
a trap to location X'4D' (instruction exception trap) occurS.

Attempting to execute an MMC instruction with any code
other than the five shown above causes the instruction to
trap to location X' 4D' (instruction exception trap).

For loading 4-bit write lock images, contents of register
Ru1 are:

For loading access protection or 2-bit write lock images,
contents of register Ru 1 are:

The Count field (bit positions 0-7) specifies the' numberof
words to be loaded from the control image area. If the
initial word count is zero, a word count of 256 is implied.
Control Instructions

The Control Start field (bit positions 15-20, 21, or 22)
points to the beginning of the memory region controlled by
the registers to be loaded. The significance of this field
is different for the 5 modes of MMC operations and is described within each mode below.
Affected: (R), (Ru 1),
memory control
storage

Traps: Instruction exception,
nonallowed operation.

For either memory map format and either type of addressing,
the contents of register Ru 1 are:

MEMORY MAP LOADING PROCESS
The initial map image address (in register R) is the virtual
address of the first word of the memory map control image.

LOADING THE MEMORY MAP

CONTROL IMAGE
Each word of the memory map control image contains either
four 8-bit page addresses or two 11-bit extended page addresses, as illustrated below:

The initial count, as contained in register Ru 1 specifies the
word length of the control image to be loaded. A word
count of 64 (for 8-bit format) or 128 (for ll-bit format) is
sufficient to load an entire block of 256 memory map control registers. The memory map control registers are treated
as a circular set, with the first register following the last;
thus, a word count greater than 64 (8-bit format) or 128
(ll-bit format) causes the first registers to be overwritten.

Typi cal memory map control image word (8-bit format):

Typical memory map control image word (ll-bit format):

Depending upon the memory map control image format, the
instruction format is one of the following:

LMAP

LOAD MAP

LMAPRE

(~-bit

format)

LOAD MAP REAL EXTENDED (11-bit format)

The initial value of the control start field of register Ru 1
points to the first page (512 words) of virtual addresses that
are to be controlled by the memory map control image being
loaded. The memory map control image is loaded into the
memory map control registers one word at a time. As the
contents of each word are loaded into either two orfourmemory map control registers, the map image address is incremented by 1, the word count is decremented by 1, and the
value in the control start field is incremented either byfour
(if the memory map control image is in the 8-bit format)
or by two (if the memory map control image is in the l1-bit
format). The loading process continues until the word count
is reduced to zero.
When the load process is completed, the map image address
of register R contains a value equal to the sum of the initial
map image address plus the initial word count, the word
count of register Ru 1 has a va lue of zero, and the control
start field of register Ru 1 contains a value equal to the sum
of the initial contents plus four or two times the initial
word count.

LOADING THE ACCESS PROTECTION CONTROLS

Depending upon the type of addressing, the format of register R contents is one of the following:
IfMA=O;

Map lmag:e Address

If ,AI-A = 1 and MM = 0;

CONTROL IMAGE
Each access protection control image word contains sixteen
2-bit fields; or, the access protection codes for 16 consecutive pages of virtual memory. Thus, the access protection
control image for 128K word (256 page) virtual memory is
contained within 16 contiguous memory locations, designated as the access protection control image area.
The fermat of c typical access protection control image

word is:

Map

Control Instructions

~age Real Exte~ded Address

MEMORY WRITE PROTECTION LOCKS

The instruction format for loading the access protection
code is:

CONTROL IMAGE

Depending upon the type of addressing, the format of register R contents is one of the following:

Each write lock control image word may contain either
eight 4-bit write lock images or sixteen 2-bit write lock
images, as illustrated below:
Typical write locks image word (4-bit format);

IfMA=O;

If MA

= 1 and

Typical write locks image word (2-bit format);

= 0;

For eithertype of addressing, the contents of register Ru 1 are:

ACCESS PROTECTION LOADING PROCESS
The initial access protection control image address in register R is the virtual address of the first word of the access
protection control image.
The initial count in register Ru1 specifies the word length of
~he c~!"!~:-d !m!:!ge t~ be !0!:!clecl ,A """rd ~ount of 16 ic; c;uf-

fi cient to load the entire block of 256 access protection control registers. The access protection control registers are
treated as a circular set, with the first register fol lowing the
last; thus, a word count greater than 16 causes the first registers loaded to be overwritten.
The initial value of the control start field of register Ru 1
points to the first page (512 words) of virtual addresses that
are to be controlled by the access protection control image
being loaded. The access protection control image is loaded
into the access control registers one word at a time, thus
loading the control registers for 16 consecutive pages with the
contents of each image word. As each image word is loaded,
the access protection control image address is incremented
by 1, the word count is decremented by 1, and the value in
the control start field is incremented by 4. The loading
process continues until the word count is reduced to O.

The number of words required to define the memory write
locks control image is dependent upon the format of the
write lock images and the number of write lock registers to
be loaded by a single MMC instruction. (For example, if
the write lock images are of the 4-bit format and the memory
system is maximum size (1,024,000 words or 2048 pages)
with 2048 write lock control registers, the control image
may be defined by 256 words (i. e., 256 words times 8 write
lock images per word is equal to 2048 write lock images or
one write lock image per each write lock control register).
If the write lock images are of the 2-bit format and the
memory size is the same, as described above, the control
image may be defined by 128 words.
The instruction format for loading 2-bit write lock images is:

LLOCKS

LOAD LOC KS (2-bit format)

The instruction format for loading 4-bit write lock images is:

LLOCKSE

LOAD LOC KS (4-bit format)

If MA = 0, the contents of register Rare:

When the loading process is completed, the parameters contained within registers Rand Ru1 have the following values!
Access protection
control image address =initial access protection control
image address plus the initial word
count.
Count

lock

If MA

= 1 and

= 0,

lmag~ Address

the contents of register Rare:

= O.

Control Start =

initial contents plus 4 times the
initial word count.

Control Instructions

When loading 2-bit write lock images, the contents of
register Ru1 are:

When loading 4-bit write lock images, the contents of register Ru1 are:

initial value plus the initial value word count and the value
of the 9- or lO-bit control start field is equal to its initial
value plus 4 times the initial word count.
The memory write lock registers are treated as a circular
set, with the reg ister for memory addresses X IOI_X I 1FF I (first
page) immediately following the register for memory addresses X'FFEOO'-X'FFFFF' (last page). Overwriting the
first registers occurs when 2-bit write lock images are being
processed and the word count is greater than 128.

INTERRUPTION OF MMC
LOADING PROCESS
Depending upon the addressing mode of the basic processor,
the contents of register R are interpreted as either a 17-bit
or a 20-bit virtual address of an image word within the
memory write locks control image area (source of write lock
images). The initial lock image address points to the first
image word. After the contents of the image word (either 8
or 16 write lock images) are loaded into an equivalent number of write lock registers, the lock image address is incremented by one. Thus, successive image words are accessed
in an ascending sequence.
Depending upon the instruction format, the hardware appends
either one or two low order zeros, as necessary, to convert
the 9-bit or lO-bit control start field into an 11-bit real
page address. In addition to being the real page address
of 512 consecutive memory word locations, the value of the
11-bit control start field is also the address of the associated
write lock control register. The value of the control start
field at the time the image word is accessed is the address
of the first of either 8 or 16 write lock control registers
that will be loaded by the write lock images contained
within one image word. When all of the write lock images
of a given word have been loaded into either 8 or 16 write
lock control registers, the val ue of the 9-bit or lO-bit control start field is incremented by 4. (Note that this is equivalent to incrementing the value of the effective 11-bit
field by a value of either 8 or 16, the number of control
registers loaded.)

The execution of MMC can be interrupted after each word
of the control image has been moved into the specified control register. Immediately prior to the time that the instruction in the interrupt or trap location is executed, the instruction address portion of the program status words contains the
virtual address of the MMC instruction, register R contains
the virtual address of the next word of the control image to
be loaded, and register Ru 1 contains a count of the number
of control image words remaining to be moved and a value
pointing to the next memory control register to be loaded.
After interrupt, the MMC instruction may be resumed from
the point it was interrupted.

MEMORY ACCESS TRAPS BY MMC INSTRUCTION
A trap during execution of the MMC instruction can occur
if the pages containing the control images are nonexistent
or are protected in the master-protected mode. The registers Rand Ru 1 may be a Itered for the above case. If a
parity error should occur during access of a control image
word, the MMC instruction wi" trap with the Register Altered
indicator set indicating that a change has been made to the
memory control registers. The registers Rand Ru 1 will be
restored to their initial values, prior to the point at which
the trap occurred.

LRA
The count field of register Ru1 specifies the number of image
words, and indirectly the number of write lock images to be
loaded. Depending upon the instruction format, each image
word is interpreted as containing either eight 4-bit write
lock images or sixteen 2-bit write lock images. In the case
of 2-bit write lock images, the hardware appends two high
order zeros to each image as it is loaded into the 4-bit control register. Thus, the number of write lock control registers loaded is always either 8 or 16 times the initial value
of the count field.

If the :nitia! "/c!ue of the count field

is zero, it is interpreted to be 256 words. During the loading operation, the count field is decremented by one after
the contents of each image word are loaded into the appropriate number of control registers. The loading operation
continues until the word count is reduced to zero. At that
time, the vallie of the lock image address is equol to its

100

Control Instructions

LOAD REAL ADDRESS
0Nord index al ignment, privileged)

LOAD REAL ADDRESS converts the address portion of the
effective '.vOid into a real byte, halfword, word, or doubleword address {as specified byCC1 and CC2at the beginning
of the LRA instruction} and loads that real address and status
information (as listed below) into register R. Upon completion of the LRA instruction, additional information pertaining to the LRA instruction or to the real address is provided
vio the conditio,., code.

Prior to executing an LRA instruction, CC 1 and CC2 must
be set to an appropriate value {as shown below}.

Results in R register

CC1

CC2

Type of real address to be generated

Address in R is an effective virtual address
{address of a general register}.

Byte (22 bits)

Note:

Halfword {21 bits}

Word (20 bits)

0
o the memory loc-ation specified by the gener1
1 ated address.
1

Doubleword (19 bits)
The effective virtual address for the LRA instruction itself
may be generated in a normal manner (i. e., indirect addressing, indexing, and/or mapping, as applicable, may be
specified and performed) with all standard trapping conditions in effect.
The address loaded into the R register is dependent upon
the value of the address portion of the effective word. Ifthe
address portion of the effective word is equal to or greater
than 16, it is converted (mapped) into a 19, 20, 21, or 22-bit
real address, as specified by CC 1 and CC2.
Note:

Converting an effective virtual address into a real
address by mapping is performed independently of
the state of the map bit in the current PSWs.

Condition code setting 11-- and 1100
may be distinguished in the software
by examining the address {bits 1O-31}.

Access protect code for the page containing

Note: This instruction requires two memory references to
the same location for its execution. To preclude
other processors from accessing the effective location during this time, the memory unit containing
the effective location is reserved {not accessible to
other processors} until the LRA instruction is
completed.

LMS

LOAD MEMORY STATUS
(Word index al ignment, privileged)

If the address portion of the effective word is less than 16,
it is not mapped into a real address. Instead, a 19, 20, 21,
or 22-bit effective virtual address is generated, as specified
by CC 1 and CC2.
In either case a 19, 20, 21, or 22-bit real or effective virtual address is loaded into a corresponding number of low
order bit positions of the R register {i. e., the least significant bit of the address is always loaded into bit position 31
of register R}. Except for bit positions reflecting status information, all high order bit positions within register Rare
set to zero. Contents of the various bit positions of register R after an LRA instruction are as follows:
Bits

Contents

0-9

Reserved; always set to O.

10-31

Real or eff~ctive virtual address. For 21-, 20-,
and 19-bit addresses, as specif,ied by initial value
of CC 1 and CC2, bit positions 10, 11, and 12
will be set to zeros, as required.

LOAD MEMORY STATUS is used to determine memory unit
status and/or to perform diagnostic action on a memory un it.
The effective address is used to determine the memory unit.
The condition code setting immediately before execution
determines the diagnostic action to be performed. The effective address always references memory even if it is less
than 16. The condition code can be set to the desired value
before execution of LMS with the LCF or LCFI in§tructions.
Register R is loaded with the result of the action. The
condition code is set at the conclusion of execution to
reflect the status of the word loaded (if any).
. Affected: (R), CC

Affected: {R),CC

Initial condition code settings:
2

LMS Action

Read and set - causes the same action as the
LOAD AND SET (LAS) instruction, except for
condition code settings. Normal traps are
allowed inclUding write protect.

Condition code settings:

Results in R register

No abnormal condition.

Address in R is real but for a nonexistent
memory location.

Trap: See "Trap System II,
Chapter 2.

Read and inhibit parity - loads the effective
word into R. If a memory parity error is detected, the memory does nottake a IIsnapshot"
or generate a Memory Fault Interrupt (MFI).
Control Instructions

101

LMS Action
It does, however, generate the Memory Parity
Error signal. The basic processor inhibits the
trap that would ordinarily occur for the memory parity error.

o
o

0
0

o
o

Reserved

Power status

8-9

Memory type

Port 1 enabled

Reserved.

Port 2 enabled

Reserved.

Port 3 ena bl ed

Port 4 enabled

Port 5 ena bl ed

Port 6 enabled

Port 1 servi ced

Port 2 serviced

Port 3 serviced

Port 4 serviced

Port 5 serv iced

Port 6 serv iced

Uncorrectable memory unit error

Memory module selection error

Address parity error

Data in parity error

Write lock parity error

Port selection error

Undefined operation

Control error

Multiple error

Ports

Read write lock - loads a pair of 4-bit write
locks into byte 3 of R (bits 24-31) and 0 in all
other bit positions of R. The write lock stored
in bits 24-27 is stored in the memory system1s
Write Lock memory at the location corresponding to bits 17-21 of the effective address,
bit 22=0. The write lock stored in bits 28-31
corresponds to bits 17-21 of the effective address, bit 22=1.

Memory fau It
types

Read status word ot - loads status word 0 into
R (see Table 9).

Read status word 1t - loads status word 1 into
R (see Table 10).
Reserved.

Comments

Memory un it error cod e

Reserved.
0

Bits

2-7

Write write lock - stores byte 3 of the data
word sent to memory as a pair of write locks
in the memory system's Write Lock memory at
a location corresponding to bits 17-21 of the
effective address, bit 22=0 (for data bits 24-27)
and bits 17-21 of the effective address, bit 22=1
(for data bits 28-31).
0

Field

Clear memory - stores zero in the memory
location specified by the address.
Reserved.

Table 9. Status Word 0

Read status word 0 and clear.
Reserved.

Write double error - stores an arbitrary word
into a specified memory location, with two
differences compared to a normal Write Word
instruction: (1) Byte 3 in memory is forced to
zero; (2) the arbitrary word is stored in memory
with an intentional wrong parity; on a subsequent read of that word, the memory issues
the parity error signal.

For "read and inhibit parity" operations, the status of the
word loaded (if any) is stored in the condition code bits at
the conclusion of execution as follows:
CC i: Memory Parity Error (from memory)

Reserved.
CC2: Data Bus Check (from CPU)
Condition code settings after execution.
CC3: Parity Bit (from memory)
t Primarily of diagnostic concern.
102

Control Instructions

CC4: 0

Table 10. Status Word 1
Field

Bits
0
1-3

Comments
Interleave switch ON
Memory unit size:
000
001
010·
011
100
101
110
111

4-6
Starting
Address

WAIT

8K
16K
24K
32K
40K
48K

single-instruction interrupt location, the instruction in the
interrupt location is executed and then instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction. When the basic processor execution mode
is changed from RUN mode to IDLE mode and back to RUN
while the basic processor is waiting, instruction execution
proceeds with the next instruction in sequence after the
WAIT instruction.

Affected: PC

56K
64K

Memory unit number (binary code)

Starting address bit 12

Starting address bit 13

Starting address bit 14

Starting address bit 15

Starting address bit 16

Starting address bit 17

Starting address bit 18

Reserved

15-31

Address received, bits 15-31

WAIT
(Word index al ignment, privileged)

WAIT causes the basic processor to cease all operations until
an interrupt activation occurs, or until the operator puts
the basic processor in the IDLE mode and then back to RUN
(see Chapter 5). The instruction address portion of the PSWs
is updated before the basic processor begins waiting; therefore, while it is waiting, the INSTRUCTION ADDRESS indicators contain the virtual address of the next location in
ascending sequence after WAIT and the contents in the next
location are displayed in the DISPLAY indicators on the
processor control console. If any input/output operations
are being performed when WAIT is executed, the operations
proceed to their normal termination.

If WAIT is indirectly addressed and the indirect reference
address is nonexistent, the nonallowed operation trap to
location X'40' will not occur. The effective virtual address
of the WAIT instruction, however, is not used as a memory
reference (thus does not affect the norma I operation of the
instruction).

READ DIRECT
(Word index alignment, privileged)

The basic processor is capable of directly communicating
with other elements of the system, as well as performing
internal control operations, by means of the READ DIRECT /
WRITE DIRECT (RD/WD) lines. The RD/WD lines consist of
16 address lines, 32 data lines, two condition code lines,
and various control lines that are connected to various basic
processor circuits and to special system equipment.
READ DIRECT causes bits 16 through 31 of the effective
virtual address to be presented to other elements of the system on the RD/WD address lines. Bits 16-31 of the effective
virtual address identify a specific elementof the system that
is expected to return information (two condition code bits
plus a maximum of 32 data bits) to the basic processor. The
sign ifi cance and number of data bits returned depend on the
selected element. If the R field of RD is nonzero, up to
32 bits of the returned data are loaded into general register R; however, if the R field of RD is 0, the returned data
is ignored and general register 0 is not changed. Bits CC3
and CC4 of the condition code are set by the addressed
element, regardless of the value of the R field.
Bits 16-19 of the effective virtual address of RD determine
the mode of the RD instruction, as follows:
Bit Position

When an interrupt activation occurs while the basic processor is waiting, it processes the interrupt-servicing routine.
Normally, the interrupt-servicing routine begins with an
XPSD instruction in the interrupt location, and ends with
an LPSD instruction at the end of the routine. After the
LPSD instruction is executed, the next instruction to be executed in the interrupted program is the next instruction in
sequence after the WAIT instruction. If the interrupt is to a

16 17 18 19

Mode

Interna I basi c processor control.

0 0 0

000

Interrupt control.

000

Xerox testers.
Control Instructions

103

16 17 18 19

o 0

READ INTERRUPT INHIBITS

Unassigned.

The following configuration of RD can be used to read the
contents of the interrupt inhibit field:

Special systems control (for customer use
with specially designed equipment).

If bits 16-19 select mode 2 through mode F, CC 1 and CC2
are set to zero and CC3 and CC4 are set according to the
state of the two condition code lines from the external
device.

READ DIRECT, INTERNAL BASIC PROCESSOR
CONTROL (MODE 0)
In this mode, the basic processor is able to read the sense
switches, the basic processor address, and the interrupt inhibit bits of the PSWs as follows:

If the R field of RD is nonzero, the contents of the interrupt
inhibit field (bits 37, 38, 39) of the program status words
are transferred to the least significant 3 bits of the specified R register (bits 29, 30, 31). The remainder of the R
register (bits 0-28) is cleared to zeros.

Affected: (R)
(PSWs)37_39 -

R29 - 31

0 - RO- 28
READ SENSE SWITCHES
The following configuration of RD can be used to read the
four SENSE switches in the System Control Processor:

Note that a copy of the interrupt inhibits is retained in the
Interrupt Status Register in the Processor Interface associated
with each basic processor.

LOAD FROM LOW MAIN MEMORY

If a parti cular SENSE switch is set, the corresponding bit of
the condition code is set to 1; if a SENSE switch is zero,
the corresponding bit of the condition code is set to 0 (see
IIRead Sense Switches II in Chapter 5).
In this case, only the condition code is affected.

READ BASIC PROCESSOR
The following RD configuration is used to read the basic
processor's address:

The instruction allows reading the contents of real memory
locations 0-31 (locations 0-15 shadowed by the general
purpose registers). This allows access to the Status Stack
pointer Doubleword in locations 0-1 and the default Program Status Words (Interrupt Stack is empty) in locations 2-4.

If the R field is nonzero, the contents of the main memory
locution identifieJ by bits 27-31 Ore loaded infO R.
Affected: (R)
EW-R

If the R field is nonzero, the cluster number in which the
basic processor resides is obtained from the associated processor interface and loaded into register R bits 21-23. All
other bits in the register are cleared to zero.

READ INTERNAL CONTROL REGISTERS
The following configuration of RD is used to read the contents of internal control (or Q) registers:
t i l

iiI

Affected: (R)
Cluster Address -

R 21 23

0 - R - 20 and R 24 31
O

104

Control Instructions

If the R field of the RD instruction is nonzero, the contents
of the internal control register, as specified by the IIQ Address ll field of the instruction (bit positions 27-31), ore

loaded into register R. Although the Q address field permits
any of 32 addresses to be specifi ed, only the following may
be used:
Q Address

Contents

X'lD'

(Bits 0-13) - Reserved
{ (Bits 14-31) - "Branch from" Program
Counter

X'lE'

(Bits 0-7) - Reserved
{ (Bits 8-31) - Load Device Address

contains the indi cator bit for the lowest priority interrupt
level within the group. For assignments in Group X'O', see
Table 11. Each interrupt level in the designated group is
sensed according to the function code specified by bits 21
through 23 of the effective address of RD. The codes and
their associated functions are as follows:
Code

Function

001

Read Armed or Waiting State. Set to 1 the bits in
the selected register which correspond to interrupt
levels in this group that are in either the armed or
the waiting state. Reset all other bits to zero.

010

Read Waiting or Active State. Set to 1 the bits
in the selected register which correspond to each
interrupt level in this group that is in either the
waiting or the active state. Reset all other bits
to zero.

100

Read Enabled. Set to 1 the bits in the selected
register which correspond to each interrupt level
in this group which is enabled. Reset all other
bits to zero.

All other Q addresses from X'OO' - X'lF' are reserved.
Affected: (R)
EW-R

READ DIRECT, INTERRUPT CONTROL (MODE 1)
The following configuration of RD is used to control the
sensing of the various states of the individual interrupt
levels within the basic processor interrupt system:

READ DIRECT (MODE 9)
Bits 28 through 3·1 of the effective address specify the identification number of the group of interrupt levels to be controlled by the READ DIRECT instruction.
Thp R fiplrJ of thp RD instruction specifies a general register
that will contain the bits sensed from the individual interrupt levels within a specified group. For external interrupt
groups, bit position 16 of register R contains the appropriate
indi cator bit for the highest priority (lowest number) interrupt level within the group and bit position 31 of register R

READ CONFIGURATION CONTROL PANEL

The mode 9 instruction reads the state of the Configuration
Control Panel for the addressed cluster or unit. Physi cal
addresses are assigned at the time of system configuration.
The returned status to Register Ris shown in Tables 11 and 12.

Table 11. Read Direct Mode 9 Status Word
RD Status Word
Bit No.

Basic Processor Cluster

Memory Unit 1

System Select

Clock Select

Processor CI uster Address 22

Unit No. 22

Processor Cluster Address 21

Unit No. 21

Processor Cluster Address 20

Unit No. 20

BP Enable

Port Enab Ie 1

MIOP Enable

Port Enab Ie 2

DIO Enable

Port Enable 3

Control Instructions

105

Table 11.
RD Status Word
Bit No.

Read Direct Iv\ode 9 Status Word (cont.)

Basic Processor Cluster

Memory Uni t 1

Not Assigned

Port Enable 4

ALTSEL

Port Enable 5

FSELA

Port Enable 6

FSELBO

Not Assigned

FSELBI

Not Assigned

Real Time Clock 1-S0

Interleave Enable

Real Time Clock 1-S1

Starting Address S12

Real Time Clock 2-S0

Starting Address S13

Real Time Clock 2-S1

Starti ng Address S14

Real Time Clock 3-S0

Starting Address S15

Real Time Clock 3-S1

Starting Address S16

Subj ective Time Clock

-so

Starting Address S17

Subjective Time Clock -S 1

Starting Address S18

External Interrupt Group 2 Option Absent

Not Assigned

External Interrupt Group 3 Option Absent

Not Assigned

External Interrupt Group 4 Option Absent

Not Assigned

External Interrupt Group 5 Option Absent

Not Assigned

tChassis Type-24

Chassis Type-23

Chassis Type-2 3

Chassis Type-22

Chassis Type-2 1

Chassis Type-22
Chassis Type-2 1

Chassis Type-20

Chassis Type-2 0

t See Chassi s Type Tabl e .
I

Table 12. Chassis Type Assignments
Chassis Type
Processor Clusters

Reserved

Basi c Processor Cluster

Reserved

I/O Expansion Cluster

Reserved

1
1

106

Control Instructions

Configuration Information

Table 12. Chassis Type Assignments (cont.)
Chassis Type
Control Ier CI usters

Memory Units

Reserved

Controller Cluster Type 3

Reserved

Memory Uni t Type 1

Reserved

Not available

Reserved

1'\

D ______ ..1

,
I

''l.C;)CIYCU

Reserved

WRITE DIRECT
(Word index alignment, privileged)

WRITE DIRECT causes bits 16-31 of the effective virtual address to be presented to other elements of the system on the
RD/vVD address Iines (see READ DIRECT). Bits 16-31 of the
effective virtual address identify a specific element of the
system that is to receive control information from the basic
processor. If the R field of WD is nonzero, the 32-bit contents of register R are transmitted to the specified element
on the RD/WD data lines. If the R field of WD is 0, 32 O's
are transmitted to the specified element (instead of the contents of register 0). The specified element may return
information to set the condition code.

Configuration Information

Bits 16-19 of the effective virtual address determine the
mode of the WD instruction as follows:
16

Mode

Internal basi c processor control.

Interrupt control.
0

Xerox testers.

}

Unassigned.

Special systems control (for customer use
with specially designed equipment).

If bits 16-19select mode 2 through mode F, CCl andCC2 are
set to zero and CC3 and CC4are set according to the state of
the two condition code lines from the external device.

Control Instructions

107

WRITE DIRECT. INTERNAL BASIC PROCESSOR
CONTROL (MODE 0)
LOAD SE NSE SWITCHES
The following configuration of WDcan be used to load the
sense switches in the System Control Processor:

If the processor is in the RUN mode and the AUDIO switch
on the maintenance section of the processor control panel
is in the ON position, a 100o-Hz signal is transmitted to
the basic processor speaker. The signal may be interrupted
by changing from RU N mode to IDLE mode, by moving the
AUDIO switch to the OFF position, or by resetting the
ALARM indicator.
RESET ALARM INDICATOR

If the R field is nonzero, bitsOthrough30f RegisterRwill be
loaded into sense switches 1 through 4 in the System Control
Processor. IftheRfield is zero, sense switches will be reset
to zeros. (See the section "SystemControl Panel II in Chapter 5. )
SET INTERRU PT INHIBITS
The following configuration of WD can be used to set the
interrupt inhibits (bit positions 37-39 of the PSWs):

A logical inclusive OR is performed between bits 29-31 of the
effective virtual address and bits 37-39 of the PSWs. If any
(or a II) of bits 29-31 of the effecti ve vi rtua I address are l's,
the corresponding inhibit bits in the PSWs are set to 1's; the
currentstate of an inhibit bit is not affected if a corresponding bit position of the effective virtual address contains a O.
Note that a copy of the Interrupt Inhibits is retained in the
Interrupt Status Register in the Processor Interface associated
with each basi c processor.
RESET INTERRUPT INHIBITS
The following configuration of WD can be used to reset the
interrupt inhibits:

The following configuration of WD is used to reset the
ALARM indicator:

The ALARM indicator is also reset by either the RESET BP
or the RESET SYSTEM Command entered from the operator's
contro I conso Ie.
TOGGLE PROGRAM-CONTROLLED-FREQUENCY
FLIP-FLOP
The following configuration ofWD is used to set and reset the
basic processor program-control led-frequency (PCF) flip-flop:

The output of the PCF fli p-flop is transmitted to the basic
processor speaker through the AUDIO switch on the maintenance section of the System Control Panel. If the PCF
flip-flop is reset when the above configuration of WD is
executed, the WD instruction sets the PCF flip-flop; if the
PCF flip-flop was previously set, the WD instruction resets
it. A program can thus generate a desired frequency by
setting and resetting the PCF fl ip-flop at the appropriate
rate. Execution of the above configuration of WD also
resets the ALARM i ndi cator •
LOAD INTERRU PT INHIBITS

If any (or all) of bits 29-31 of the effective virtual address
are 1's; the corresponding inhibit bits in the PSWs are reset
to O's; the current state of an inhibit bit is not affected if
a corresponding bit position of the effective virtual address
contains a O.
Note that a copy of the Interrupt Inhibits is retained in the
Interrupt Status Register in the Processor Interface associated with each basic processor.

The following configuration of WD can be used to transfer
the contents of the spec ified R reg ister (R29-31) to the
Interrupt Inhibit fie Id (PSWs _ ).
37 39

Affected: (PSWs
(R 29 - 31 ) -

_ )
37 39

PSWs37 -39

SET ALARM INDICATOR
TURN ON MODE ALTERED FLAG
The following configuration ofWDis used to set theALARM
indicator on the maintenance section of the processor control panel:

108

Contro I Instructions

The following configuration of WD is used to set the Mode
Altered Flag (PSWs 61) to 1:

TURN OFF MODE ALTERED FLAG

If the R field is zero, the specified register is loaded with
all zeros.

The following configuration of WD is used to reset the Mode
Altered Flag (PSWs 61) to 0:

Affected: (E L)

(R) -

(EL)

WRITE DIRECT, INTERRUPT CONTROL (MODE 1)

STORE IN LOW MAIN MEMORY

The following configuration of WD is used to set and reset
the various states of the individual interrupt levels within
the basi c processor interrupt system:

This instruction writes into main memory locations 0-31
(locations 0-15 shadowed by the general purpose registers
and reserved locations). This allows storing or changing the
Status Stack Pointer Doubleword in locations 0-1 and the
default Program Status Words (Status Stack is empty) in
locations 2 through 4.
If the R fi e Id is non zero, the contents of Rare stored in the
main memory location identified by bits 27-31.
TRAP TO LOCATION X ' 47 1

This instruction causes the basic processors to trap to location X1471.

Bits 28-31 of the effective address specify the identification
number (see Table 11) of the group of interrupt levels to be
controlled by the WD instruction.
The Rfield of the WD instruction specifies a general register
that contains the selection bits for the individual interrupt
levels within the specified group. For external interrupt
groups, bit 16 of register R contains the selection bit for
the highest-priority (lowest-numbered) interrupt level within
the group, and bit310f register Rcontains the selection bit
for the lowest-priority (highest-numbered) interrupt level
within the group. For assignments in GroupX101, see Table 11.
Except for Power on/Power off interrupt levels, which can

A
1\

.. 1..._ D ____ ~~ __ D.. ~

__ :~_..J 1... .... I...~ :_: .. :_ .. : __ 1..._:_

IIII~

III

'I.~

I.;J

1'Yo',;)v,,",

IIV"",,,v..l'.;JV'

U,",.;J

II.v

. . . . ,.\"AI ••• ~

"""",,,",,'v

processor (or the associated PI). This line, when true, causes
the basi c processors to trap to X 1471 (including the one that
executes the instruction).
WRITE INTO INTERNAL CONTROL REGISTER

IIVI

I...~

..J:~_I...I_..J

...,"'"

'-I •

.;Juu.vu,

..J:~

____ ..J

UlaUllllCU,

:_I...~I...:

IIII"IJ'I~U,

.. _..1

___ I...

1 ____ 1 :_

.. L_

C\.I\,... II

I'C;;VIIIW'I

Ille

'11

designated group is operated on according to the function
code specified by bits 21-23 of the effective address ofWD.
The codes and their associated functions are as follows:
Code

Function

000

Set active all selected levels currently in the
armed or waiting states.

The following configuration of WD is used to write into the
internal control (or Q) registers:

Disarm all levels selected by a 1; all levels selected by a 0 are not affected.
Arm and enable all levels selected by a 1; all
levels selected by a 0 are not affected.
Arm and disable all levels selected by a 1; all
levels selected by a 0 are not affected.

If the R field is nonzero, the contents of register Rare
loaded in the control register, as specified by the IIQ Address" field (bit positions 27-31) of the WD instruction.
Except for the four Q addresses listed below, all other addresses are reserved:

100

Enable all levels selected by a 1; all levels selected by a 0 are not affected.

101

Disable all levels selected bya l;all levels selected by a 0 are not affected.

Q Address

Significance

110

Enable all levels selected by a 1 and disable all
levels selected by a O.

X ' 1D '

(Bits 00-13) - Reserved.
(Bits 14-31) - Write into the "Branch
{
From" program counter.

111

Trigger all levels selected by a 1. All such levels
that are currentlyarmed advance to waiting state.

X ' 1E '

(Bits 00 through 07) - Reserved.
{ (Bits 08 through 31) - Write into the "Load
Device Address" register.

tThese codes clear the current interrupts, i. e. I remove from
the active or waiting state all levels selected by a 1 (see
Figure 12).

Control Instructions

109

INPUTjOUTPUT INSTRUCTIONS
The I/O instruction set is comprised of eight instructions,
as listed below.

Instruction Name

Mnemonic

Start Input/Output

SIO

Test Input/Output

TIO

Test Device

TDY

Halt Input/Output

HIO

Reset Input/Output

RIO

Poll Processor

POLP

Poll and Reset Processor

POLR

Acknowl edge Input/Output Interrupt

AIO

OVERALL CHARACTERISTICS
All I/O instructions are privi leged and can be performed
only when the basic processor (BP) is in either the master
or master-protected mode. If the BP attempts to execute
an I/o instruction when it is in the slave mode (bit 8 of
the current PSW is a 1), the instruction is aborted at the
time the operation code is decoded and the BP traps to location X ' 40 ' • Programs operating in the slave mode must
request I/O services from the System Monitor.
At the end of every I/O instruction, the condition code
bits represent a summary description of the results of the
I/O operation and conditions within the addressed I/O
subsystem. Specific condition code settings and meanings
(unique for each I/O instruction) are contained in the detailed description for each I/o instruction.
All I/O instructions, except RIO, may request detailed
I/O status information. The type and amount of I/O status
information that may be requested is determined by the operation code and the R field of the I/O instruction. The
R field also designates which general register{s) is to be
loaded with the requested information. (Refer to I/O Status
Informati on for further detai Is. )
I/O instructions are similar to other word-addressing instructions in that bits 15-31 may be modified by indirect
addressing and/or indexing. However, the final value of
the~e bits is r.ct used as en effect;vc \ditua! addieSS for
memory reference. Instead, depending upon the I/o instructi on, these bi ts are used as an extensi on to the operation code field, as an I/O address to select a particular
I/O subsystem, or they may be reserved. Further detai Is
of I/O instructions are illustrated in Figure 13 and described in Table 13.

110

Input/Output Instructions

1/0 STATUS INFORMATION
SIO, TIO, TDY, AND HIO INSTRUCTIONS
If the R field is coded with a 0, no status information is requested nor loaded. If the R field is odd, one word of status
information is requested to be loaded into register R as specified by the R field. If the R field is even (not zero), two
words of status information are requested to be loaded into
registers Rand Ru 1.
The following I/O status information may be loaded into
register R only when the R field is coded with an even
(nonzero) value.

The significance of each bit within register R is described
in Table 14.
The following I/O status information may be loaded into
register R if the R field is odd, or into register Ru 1 if the
R field is even and not zero.
The format of information within the specified general register (R or Ru1) is shown below.

Device Status Byte. These eight bits (0-7) when loaded
into the specified general register provide status information
pertaining to the addressed device and device controller or
lOP. The significance of each bit when requested by an
SIO, TIO, and HIO instruction is described in Table 15.
The significance of these bits when requested by a TDY instruction is different and is described in the applicable
peripheral device reference manual.
Operational Status Byte. Bits 8-15 of the specified general register (R or Ru1) indicate either the presence (1) or
absence (0) of various errors which may have occurred
during an I/o operation. The significance of the individual bits within the operational status byte are described
in Table 16.
Table 17 is the summary description of the Device Status
Byte and the Operational Status Byte.
Byte Count. Bits 16-31 of register Ru1 indicate the number of bytes that have to be transmitted to or from memory in the operation called for by the current I/o command
doub Ieword •
RIO INSTRUCTION
No status information is returned to the general registers
for an RIO instruction (the R field is ignored). Only condition code bits (CCl - CC3) are set to reflect the I/o
condi ti ons.

* 1
Operation Code
R
I· X
Reference Address
I Initial I/O
'-.
I --L.._ _ _ _ _ _ _---L_ _ _ _---1...._ _ _..I..---:::::--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......a Instruction

II
*

Operation Code

I!~~:::~:::~;-

I/O Address

'-·--L.·----------L--------1...---~-~~----~~--------------~·in9

Operation Code
(Hexadecimal)

Mnemonic

15017 18

and/or
indexing

23 24

20 21

SIO

DCA

TIO

000
DCA
000
DCA
000

TDY

HIO

000

RIO

001

POLP

010

POLR

011

AlO

000

(2)

o
0)

27 28
000

DCA
DA
DCA
DA
DCA
DA
DCA

Portions of a word format that are shaded represent bits that are reserved (after the I/O address is generated) and
must be coded with zeros to ensure program compatibility with possible enhancements to software and/or hardware.
aCE = operation code field extension; CA
DA = device address.

= cluster address;

= unit address;

DCA

= device controller address;

To address a single-unit device controller, bit 24 must be a 0; to address a multiunit device controller, bit 24
must be a 1.
Figure 13. Formats of I/O Instructions

Table 13. Description of I/O Instructions
Bit
Position

Applicable Instructions
(Mnemonics)

All I/O instructions

If this bit is a 1, bits 15-31 of the initial
direct addressing.

1-7

SIO, TIO, TDV, and AlO

For these four instructions, the operation code uniquely defines the I/O operation that is to be performed.

HIO, RIO, POLP, and
POLR

Within bit positions 1-7, these four instructions all have the same operation
code (X I 4F'). The instructions are differentiated by using bits 15, 16, and 17
as an extension of the operation code field.

SIO, TIO, TDV, and HIO

The value of the R field specifies how much status information is requested
from the addressed I/O subsystem (lOP, device controller, and device) and
into which general register{s) the status information is to be loaded. If the
value of the R field is even and not 0, two words of status information are requested to be loaded into registers Rand Ru 1. If the value of the R field is odd,
one word of status information is requested to be loaded into register R.

RIO

Although the R field is not used by the RIO instruction, the R field may be
coded with any value as required by the program.

8-11

Function and/or Description

I/o instruction are

modified by in-

Input/Output Instructions

111

Table 13.

Description of I/O Instructions (cont.)

Bit
Position

Applicable Instructions
(Mnemonics)

8- 11

POLP and POLR

This field specifies which general register (including register 0) is to receive
processor (MIOP, RMP, BP, MI, PI, or System Control Processor) fault information.

AIO

If the R field is a, no status information is requested. If the"R field is not a, the
designated general register is to be loaded with the requested status information.

12-14

All I/O instructions

The X field may be used to specify indexing.

15-17

510, TIO, TDV, and AIO

After the I/O address is generated, these bits are reserved and must be coded
with zeros.

HIO, RIO, POLP, and
POLR

These bits are an extension to the operation code field (bits 1-7) and permit
each of these instructions to be uniquely defined.

Function and/or Description

(cont.)

Note that these bits are subject to modifications due to indirect addressing or
indexing. The final configuration of these bits must be as shown below:
HIO = 000

= 001
= OlO

RIO
POLP

POLR =
18-31

all

The I/O address (after any indirect addressing and/or indexing) is contained
within these bits. Depending upon the I/O instruction, the required I/O
address may be compri sed of (1) a cluster address; (2) a cluster address and a
unit address; (3) a cluster address, a unit address, and a device controller
address; or (4) a cluster address, a unit address, a device controller address,
and a devi ce address.

All I/o instructions
(except AIO)

Subfields of the final I/o address field are described below.
f----- -

~-------

-" -

All I/O instructions
(except AIO)

-f-- -

112

The assignment of addresses is mutually exclusive, that is, no two units
may have the same address.

Bits 18-20 represent a cluster address.

Bits 21-23 represent a unique unit within that cluster. Since all processor
clusters contain as a minimum a Processor Interface (PI) unit and a memory
interface (MI) unit, the address (llO) 21-23 and (111) 21-23 have been
preassigned to these units.

---

AIO

After the I/o address is generated, these bits are reserved and must be coded

510, TIO, TDV, and HIO

If the I/O instruction is addressed to a single-unit device controller, this bit
must be coded as a O. If the I/O instruction is addressed to a multiunit device
controller, this bit must be coded as a 1. Note that bit 24 is not considered
as part of the device controller address.

Input/Output Instructions

These bits constitute the cluster address (CA) and the unit address (UA) field
of an I/o instruction. Cluster and unit addresses may be assigned in the
following manner:

c----------------------

Table 13.
Bit
Position

Applicable Instructions
(Mnemonics)

Function and/or Description

RIO, POLP, POLR, and AIO

After the I/O address is generated, this bit is reserved and must be coded
with a zero.

(cont.)
---

f------

Description of I/O Instructions (cont.)

----

- - - - - - - - - -

-------

If the I/o instruction is addressed to a single-unit device controller (bit 24
is a 0), bits 25-31 represent one of 16 possible device controller addresses
(X1001 - X10FI). There is no need to specify a device address.

SIO, no, TDY, and HIO

_If the I/O instruction is addressed to a multiunit (e. g., magnetic tape) device
controller (bit 24 is a 1), bits 25-27 represent one of eight possible device
controller addresses (X101 - X?I) and bits 28-31 represent one of 16 possible
device addresses (X101 - XIP).
Device controller addresses assigned to controllers within the same I/O channel (e. g., MIOP), must be mutually exclu~;ve. Note that bit 24, which must
be a 0 when addressing a single-unit device controller and a 1 when addressing
a multiunit device controller, is not considered a part of the decive controller
address. Thus, for example, if the device controller address X101 is assigned
to a multiunit device controller within an MIOP, no other device controller
(single or multiunit) within that MIOP may have an address of X101.

-- -

RIO, POLP, POLR, and AIO

Table 14. I/o Status Information (Register R)
Bit
Position

Significance

Reserved

---

Table 14. I/O Status Information (Register R) (cont.)
Bit
Position

Bus Check Fault (BCF).

After the I/O address is generated, these bits are reserved and must be coded
with zeros.

This bit is set to 1

Significance
Memory Interface Error (MIE). lOP Halt
condition is the same as a Bus Check Fault.

4-12

Reservel

13-31

Current Command Doubl eword Address. The
19 high-order bits of the main memory address
from which the command doubleword for the
I/O operation currently bei ng processed by
the addressed I/O subsystem is fetched.

if a discrepancy exists between the parity
error status in the memory unit and the lOP
when an lOP is performing a main memory
read cyc Ie. If the error occurs wh i Ie accessing data then the device halt. is controlled
by the Halt-on-Transmission-Error flag (bit
position 36 of an I/O command doubleword).
If the error occurs whi Ie fetching a command, the operation is terminated immediatey with an "unusual end".

Control Check Fault (CCF). This bit is set
to 1 when a parity error occurs during a subchannel read operation within the MIOP.
The operation terminates immediately with
I an "unusual end".

tTo ensure program compatibility with possible software
and/or hardware enhancements, it is recommended that
reserved bi ts be treated as i ndetermi nate and not used
(i. e. I masked).
ttThe lOP unconditionally sets the Processor Fault Indicator (PFI) whenever a Bus Check Fault, Control Check
Fault, Control Memory Fault, or Memory Interface Error
occurs. The lOP fault status register isset with status information as listed under the POLP or POLR instructions.

Input/Output Instructions

113

Table 15.

Bit
Position

Table 15.

Device Status Byte (Register R or Ru1)
(SIO, no, and HIO only)

Significance
Interrupt Pending. This bit is set to a 1 if
the addressed device has requested an interrupt that has not been acknowledged by the
BP with an AIO instruction. If this bit is
a 1, the current SIO instruction is not accepted. Condition code bits are set to reflect this action and any requested status
information is loaded into the designated
general register(s). SIO instructions will not
be accepted unti I the interrupt pending condition is cleared.

Bit
Position

o
(cont. )

Appropriate flag(s) (IZC, ICE, and/or
IUE; bit positions 33, 35, and 37, respectively) within the I/O command
doubleword must be set to 1.

The flagged event (byte count reduced
to zero for the IZC flag, II channel end ll
condition for the ICE flag, or lIunusual
end ll condition for the IUE flag) must
occur.

lOP may signal device controller to
raise interrupt without examining interrupt flags, if:
a.

A connection address error is
detected.

Any error is detected when lOP is
accessing an 10eD.

For case a, no interrupt status wi II be
set in response to an AlO.
For case b, an IUE signal is sent back
in response to an AIO.
An I/o interrupt may also be requested by
certain devices via M modifier bits within
the basic order for that device (see Operational Command Doublewords).
A BP wi II respond to an interrupt request
from a particular I/o subsystem if (1) the
I/O interrupt level (X '5C') is armed,

114

Input/Output Instructions

Significance
enabled, and not inhibited; and (2) that
there is no higher priority interrupt level
in the active or waiting state.

1,2

Device Condition. If bits 1 and 2 are 00
(device IIreadyll), all device conditions required for proper operation are satisfied.
If bits 1 and 2 are 01 (device IInot operational ll ), the addressed device has developed
some condition that will not allow it to proceed; in either case, operator intervention
is usually required. If bits 1 and 2 are 10
(device II unavailable ll ), the device has more
than one channel of communication available and it is engaged in an operation controlled by a controller other than the one
specified by the I/o address. If bits 1 and 2
are 11 (device II busyll), the device has accepted a previous SIO instruction and is already engaged in an I/O operation.

Device Mode. If this bit is 1, the device
is in the lIautomatic ll mode; if this bit is 0,
the device is in the IImanual" mode and
requires operator intervention. This bit can
be used in conjunction with bits 1 and 2 to
determine the type of action required. For
example, assume that a card reader is able
to ·operate, but no cards are in the hopper.
The card reader would be in state 000 (device II ready II , but manual intervention required), where the state is indicated by
bits 1, 2, and 3 of the I/O status response.
If the operator subsequently loads the card
hopper and presses the card reader START
switch; the reader would advance to state 001
(device "ready" and in automatic operation).
If the card reader is in state 000 when an
SIO instruction is executed, the SIO would
be accepted by the reader and the reader
would advance to state 110 (device II busyll,
but operator intervention required). Should
the operator then place cards in the hopper
and press the START switch, the card reader
state would advance to 111 (device II busyll
and in "automatic ll mode), and the input
operation would proceed. Should the card
reader subsequently become empty (or the
ope;ator press the STOP switch) and command chaining is being used to read a number of cards, the card reader wou Id return to
state 110. If the card reader is in state 001
when an SIO instruction is executed, the
reader advances to state 111, and the input

Normally, before a device can request an
interrupt, the following conditions must
prevail:
1.

Device Status Byte (Register R or Ru1)
(SIO, no, and HIO only) (cont.)

Table 16. Operational Status Byte (Register Ru1)

Table 15. Device Status Byte (Register R or Ru1)
(SIO, TIO, and HIO only) (cont.)
Bit
Position

Bit
Position

8
3
(cont. )

operation continues as normal. Should the
hopper subsequently become empty (or should
the operator press the card reader STOP
switch) and command chaining is being used
to read a number of cards, the reader would
go to state 110 unti I the operator corrected
the situation.

Unusual End. If this bit is a 1, the previous I/O operation terminated in an " un usual end". Unusual end conditions occur
for various reasons that are unique to each
device (refer to appl icable periphera I reference manua I for further deta iI s) •

5,6

Device Controller or lOP Condition. The
function of these two bits is dependent
upon the type of lOP addressed by the
I/o instruction.

MIOP Operations: If bits 5 and 6 are 00
(device controller "ready"), all device
controller conditions required for its proper
operation are satisfied. If bits 5 and 6
are 01 (device controller "not operational"), some condition has developed
that does not allow it to operate properl y . Operator i ntervent i on is usua II y required. If bits 5 and 6 are 10 (device
controller "unavailable"), the device controller is currently engaged in an operation
controlled by an lOP other than the one
addressed by the I/O instruction. If bits 5
and 6 are 11 (device controller "busy"),
the device controller has accepted a previous SIO instruction and is currently engaged in performing an operation for the
addressed lOP.

Significance

Reserved. To ensure program compatibility
with possible software and/or hardware
enhancements, it is recommended that this
bit be treated as indeterminate and not
used (i. e., masked).

Incorrect Length. This bit is set to 1 if an
incorrect length condition occurred within
the responding subchannel. An incorrect
length condition is caused by a "channel
end" (or end of record) condition occurring
before the device controller has a "count
done" signal from the lOP (indicating that
the byte count has been reduced to zero), or
is caused by the device controller receiving
a count done signal before channel end (or
end of record): e. g., count done before
80 columns have been read from a card.
When set to a 1, the incorrect length bit,
by itself, always signifies that an incorrect
length condition has occurred. If the SIL flag
(bit 38 of the I/O command doubleword) is
coded with a 0, the detected incorrect length
condi ti on is to be interpreted as an error condition. If the SIL flag is coded with a 1, the
detected. incorrect length condition is to be
interpreted as a nonerror condition. If an incorrect length condition is to result in a device halt, the SIL flag must be coded with
a 0 and the HTE flag (bit 36 of the I/O command doubleword) must be coded with a 1.

Transmission Data Error. This bit is set to 1
if the device controller or lOP detected a
parity error or daTa overrun in Tne Transmittal information. A device halt occurs as a
result of a transmission data error only if the
HTE flag of the I/o command doubleword is
coded with a 1.

Transmission Memory Error. This bit is set to 1
if a memory parity error was detected during
a data input/output operation. A device halt
occurs as a result of a transmission memory
error only if the HTE flag of the I/O command doubleword is coded with a 1.

Memory Address Error. This bit is set to 1 if
a nonexistent memory address is detected
during a chaining operation or a data input/
output operation. This bit is cleared during
a successful SIO or HIO.

lOP Memory Error. This bit is set to 1 if the
lOP detects a memory parity error while
fetching a command. The bit is cleared during a successful SIO or HIO.

lOP Control Error. This bit is set to 1 if the
lOP detects two successive Transfer in Channel commands. The bit is cleared during a
successful SIO or HIO.

Input/Output Instructions

115

Table 16. Operational Status Byte (Register Ru 1) (cont.)
Bit
Position
14

Significance
lOP Halt. This bit is set to 1 if an error condition is detected which causes the lOP to
issue a halt order to the addressed I/O device. Error conditions which may cause
an lOP halt (independent of the HTE flag
within the I/o command doubleword) are:

Table 16. Operational Status Byte (Register Ru1) (cont.)
Bit
Position

Significance

14
(cont.)

Error conditions which may cause an lOP halt
only if the HTE flag is coded with a 1 are:

Bus check fault that occurs while fetching a command

Control check fault

Memory address error

lOP memory error

lOP contfol error

Bus check fault that occurs whi Ie fetching data

Transmission memory error

Transmission data error

Incorrect length conditi on occurri ng
while the SIL flag is coded with a O.

An lOP halt condition causes the current
operation to terminate immediately as an
ll
II unusua I end •

This bit is set to a 1 if a Write Lock Violation
(WLV) occurs.

Table 17. Status Response Bits for I/O Instructions
Position and State in Register Ru 1
Operational Status Byte

Device Status Byte

2 3

0 0 -

5 6 7

10 11

12 13 14 15

Significance for
SIO, HIO, and TIO
interrupt pending
device ready
device not operational
device unavai lable
device busy
device manual
devi ce automati c

101 1

8 9

0
1
-

0 0 -

0 1
101 1

device unusual end
device controller ready
device controller not operational
device controller unavailable
device controller busy
reserved

Significance
for TDV

unique to the
device and
the device
controller

incorrect length
transmission data error
tronsmission memory error

memory address error
lOP memory error
lOP control error
lOP halt
write lock violation

116

Input/Output Instructions

same as for
SIO, HIO,
and TIO

POLP and POLR INSTRUCTIONS
The R field of these two instructions always specifiesa general register (including register 0) that may receive up to
16 bits of fault status information from an addressed BP or
MIOP. Each bit indicates the presence (1) or absence (O)
of a specific fault condition within the polled processor
(as listed in Table C-1). Note that the information
represented by a particular bit is also dependent upon
the type of processor polled (e. g., bit 18 may indicate a
memory parity error in the BP or a control check fault
within an MIOP).

Table 18. lOP Status Byte (cont.)
Bit
Position

8
(cont. )

For this instruction, if the R field has a value of 0, no
status information is requested nor loaded. If the R field
has a value of X l l 1 through X'F', the specified register may
receive one word of I/o information pertaining to an I/O
interrupt.

Transmission Data Error. This bit is set to 1
if, since the last accepted SIO instruction
addressed to this subchannel, the device controller or lOP detected a parity error or data
overrun in the transmitted information. A
device halt occurs as a result of a transmission
data error only if the HTE flag of the I/o
command doubleword is coded with a 1.

Zero Byte Count Interrupt. This bit is set to 1
if the interrupt on zero byte count flag is 1
and zero byte count is detected.

Channel End Interrupt. This bit is set to 1 if
the interrupt at channel end flag is 1 and
"channel end" is reported by the device to
the lOP.

Unusual End Interrupt. This bit is set to 1 if
the interrupt at unusual end flag is 1 and unusual end is reported by the device to the
lOP, or if the lOP halt is signaled to the devi ce control Ier by the lOP.

Write Lock Violation. This bit is set to 1 if
the memory signaled a Write Lock Violation
in the course of transmitting information from
the device to the memory. If the HTE flag
and the I UE flag are set, the operati on wi II
terminate with an "unusual end".

Reserved.

Device and Device Controller Status Byte. Bits 0-7 of the
status word obtained by an AIO instruction from a responding I/O subsystem are unique to the device and device
controller. These bits are described in the applicable peripheral device reference manual.

Table 19 is a summary description of the Device/Device
Controller Status Byte and the lOP Status Byte.
Bits 16-18. These bits of the AIO response are reserved.
To ensure program compatibility with any enhancements
{software and/or hardware}, it is recommended that these
bits be treated as indeterminate and not used (i. e., masked).

the byte count has been reduced to zero), or
is caused by the device controller receiving
a count done signal before channel end (or
end of record): e. g., count done before 80
columns have been read from a card.
When set to a 1, the incorrect length bit, by
itself, always signifies that an "incorrect
length" condition has occurred. If the SIL
flag (bit 38 of the I/O command doubleword)
is coded with a 0, the detected incorrect
length condition is to be interpreted as an
error condition. If the SIL flag is coded with
a 1, the detected incorrect length condition
is to be interpreted as a nonerror condition.
If an incorrect length condition is to result in
a device halt, the SIL flag must be coded with
a 0 and the HTE flag (bit 36 of the I/O command doubleword) must be coded with a 1.

Ala INSTRUCTION

lOP Status Byte. Bits 8-15 indicate the presence (1) or
absence {O} of various operation errors and interrupts that
may have occurred during an I/O operation. The functions
of individual bits within the lOP Status Byte are described
in Table 18.

Significance

Table 18. lOP Status Byte
Bit
Position
8

Significance
Incorrect Lenlilth. This bit is set to 1 if an
incorrect length condition occurred within
the responding subchannel. An incorrect
length condition is caused by a "channel
end ll (or end of record) condition occurring
before the device controller has a "count
done" signal from the lOP (indicating that

Input/Output Instructions

117

Table 19. Status Response Bits for AIO Instruction
Position and State in Register R
Device Status Byte

Operational Status Byte

8 9

2 3

4 5 6 7

10 11

12 13 14 15

Significance

unique to the device and
the device controller

incorrect length
transmission data error
zero byte count interrupt
channel end interrupt
unusual end interrupt
write lock violation
reserved
reserved

I/O Address. Depending upon the type of device controller responding to the AIO instruction, the I/O address
may be comprised either ofa processor address and a singleunit device controller address or a processor address, a
multiunit device controller address, and a device address.
The subfields of the I/O address are described in Table 20.
Table 20. I/O Address (AlO Response)
Bit
Position

Significance

18-20

This field contains the cluster address.

21-23

This field contains the unit address.

24-27

This field contains all ones.

28-31

This field contains the device address.

START INPUT/OUTPUT performs the following:

Attempts to initiate an input or output operation whether an I/o operation is started or not is dependent
upon conditions within the addressed I/O subsystem
(see meanings of condition code settings).

Specifies which lOP, channel, device controller, and
input/output device is to be selected (bits 18-31 of
the effective virtual address of the instruction word).

Specifies the address of the first command doubleword
for the subsequent I/O operation (bits 13-31 of genprnl
rpniC:+pr m
-- -- - -;::;r-- -- -,.

Specifies how much additional status information is to
be returned from the I/O system (R field, bits 8-11 of
instruction word).

Specifies which general registers are to be loaded with
the requested status information (R fjeld, bits 8-11, of
i nstructi on word).

Instruction Register

Set MIOP in test mode by using device controller address X'3F' or X'7F'. Note that device controller
addresses X'3F' and X'7F' are prohibited for normal
opeiation.

Genera I Reg i ster 0

General register 0 is temporarily dedicated during SIO instruction execution and must contain the doubleword memory address of the first command doubleword specifying the
operation to be started. The required address information
must be in general register 0 when the SIO is executed.

SIO

118

START INPUT/OUTPUT
(Word index alignment, privileged)

Input/Output Instructi ons

Status information for an SIO instruction isalways returned
via condition code bits. Additional information may be
requested and returned via the general registers as specified by the R field of the SIO instruction. However, the
return of the additional information is dependent upon
conditions encountered within the addressed I/O subsystem
(see meanings of condition code settings).

2 3 4

Meaning

I/O address not recognized, SIO not accepted, and status information returned to
genera I reg i sters is incorrect.

1 1 1 0

Incoming parity error detected by processor
and SIO aborted. No status information returned to general registers.

If the R field is coded with a 0, no additional status information is requested.
If the R field is coded with an odd value, one word of
status information is requested to be loaded into register R.
The format of this information is as follows:

If the R field is coded with an even (nonzero) value, two
words of status information are requested. The format of
information within register Ru1 is as shown above. The
format of information within register R is as follows:

If CC4 = 1, the MIOP is in test mode and the meaning of.
the condition code during an SIO is:
2 3 4

Meaning

Set test mode is successful.

Set test mode is successful, but a Bus Check
Fault was detected.

TID

1*1

TEST INPUT/OUTPUT
(Word index alignment, privileged)

0123145

These responses provide the program with information necessary to determine the current status of the addressed I/O
subsystem. The byte count field indicates the number of
bytes that are to be transmitted to or from memory in the
operation called for by the current command doubleword.
The other fields are described in Tables 14 -17.
Affected: (R), (Rul), CC

The meaning of the condition code bits during an SIO instruction is:

2 3 4

Meaning

0 0 0

I/o address recognized, SIO accepted, and
status information in general registers is
correct.

TEST INPUT/OUTPUT is used to make an inquiry on the
status of data transmission. The operation of the selected
lOP, device controller, and device is not affected, and
no operations are initiated or terminated by this instruction.
The responses to no provide the program with the information necessary to determine the current status of the device,
device controller, and lOP, the number of bytes remaining
to be transmitted into or from main memory in the operation,
and the present point at which the lOP is operating in the
command list.

If the R field of the TIO instruction is 0, no general
registers are affected, but the condition code is set.
If the R field of TIO is an odd value, the condition code
is set and the I/O status and byte count are loaded into
register R as follows:

Not possi;;le.

Not possible.

1 0 0

I/O address recognized, SIO not accepted
because device controller or device is busy,
and status information in general registers is
correct.

Not possible.

0 0

Not possible.

1 0

Pari ty error detected on returned status and/or
condition code. The result of the SIO is
indeterminate.

If the R field of the TIO instruction is an even value and
not 0, the condition code is set, register Ru1 is loaded as
shown above, and register R is loaded as follows:

Refer to Tables 14-17 for functions of individual bits within
status words.
Affected: (R), (Ru1), CC

Input/Output Instructions

119

If CC4 ::: 0, the MIOP is in a normal mode of operation and
the meaning of the condition code during a no is:

2 3 4

Meaning

0 0 0

I/O address recognized, acceptable SIO is
currently possible, and status information in
general registers is correct.

Not possible.

I/O address recognized but acceptable SIO
is not currently possible because device controller or device is busy. Status information
in general registers is correct.

1 1 0

Not possible.

0 0

Not possible.

1 0

Pari ty error detected on returned status and/
or condition code. The result of the no is
indeterminate.

1 1 0 0

I/O address not recognized, no not accepted, and status information returned to
general registers is incorrect.

1 1 1 0

Incoming parity error detected by processor
and no aborted. No status information returned to general registers.

If CC4 ::: 1, the MIOP is in the test mode and the meaning
of the condition code during a no is:

TEST DEVICE is used to provide information about a device other than that obtained by means of the no instruction. The operation of the selected lOP, device
controller, and device is not affected, and no operations are initiated or terminated. The responses to TDV
provide the program with information giving details on
the condition of the selected device, the number of bytes
remaining to be transmitted in the current operation, and
the present point at which the lOP is operating in the
command list.

If the R field of the TDV instruction is 0, the condition
code is set, but no general registers are affected.

If the R field of TDV is an odd value, the condition code
is set and the device status and byte count are loaded into
register R as follows:

If the value of the R field of TDY is an even value and
not 0, the condition code is set, register Rul is loaded as
shown above, and register R is loaded as follows:

Refer to the applicable peripheral reference manual for description of Deyice Status Byte. Refer to Tables 16 and 17
for functions of other bits within status words.
Affected: (R), (Rul), CC

2 3 4
000

Meaning
Unit is performing an Order Out operation.

If CC4

= 0,

the MIOP is in a normal mode of operation and

thp
mpnninn nf th",
rnn,.Hti,...n
rl'V'l",
...4 .. rinn n
••• ••• _ - ••••• ;;;1 - '
••• - _ . , - •• ' - "
- - - - - _ . "'>:} -

Unit is performing an Order In operation.

Unit is performing a Data Out operation.

Pari ty error detected by Processor Interface
on returned status and/or condition code.
The result of the no is indeterminate.

Unit is performing a Data In operation.
BCF detected while unit performing a Data In
operation.

TOV

120

TEST DEVICE
(Word index alignment, privileged)

Input/Output Instructions

Tnv
• -

ie: •

••

2 3 4

Meaning

0 0 0

I/O address recognized, no device-dependent
condition present, and status information in
general registers is correct.

0 1 0

Not possible.

0 1 1

Not possible.

1 0 0

I/O address recognized and device-dependent
condition is present or device controller is in
test mode.

1 1 0

Not possible.

2 3 4

If the R field is an odd value, the condition code is set and
the following information is loaded into register R.

Meaning

0 0

Not possible.

1 0

Parity error detected on returned status and/or
condition code. The result of the TDV is
indeterminate.

1 1 0 0

I/O address not recognized, TDV not accepted,
and status information returned to the general
registers is incorrect.

1 1 1 0

Incoming parity error detected by processor
and TDV aborted. No status information returned to general registers.

If CC4 = 1, the MIOP is in the test mode and the meaning
of the condition code during a TDV is:

2 3 4

Meaning

000

Unit is performing an Order Out operation.

Unit is performing an Order In operation.

Unit is performing a Data Out operation.

Pari ty error detected by Processor Interface
on returned status and/or condition code. The
result of the TDV is indeterminate.

Unit is performing a Data In operation.
nrt:............
...I~~",_~""...I , .. k.: I"" 11,..:+ norf"'rrn:,.. ........
.,"""
-'-1'._- ........ - _.... r-... _· ...... v -

This information shows the status of the addressed I/o subsystem at the time of the halt. The byte count field shows
the number of bytes remaining to be transmitted to or from
memory. Other fields are described in Table 14-17.
The HIO instruction must have zeros in bit positions 15, 16,
and 17 to differentiate it from the RIO, POLP, and POLR
,instructions, which also have X ' 4F' as an operation code
(bits 1-7).
Affected: (R), (Ru1), CC

If CC4 = 0, the MIOP is in a normal mode of operation and
the meaning of the condition code during an HIO instructi on is:

2 3 4

Meaning

0 0 0

I/o address .recognized, HIO accepted, device controller not busy at time of HIO,
and status information in general registers is
correct.

Not possible.

1 0 0

I/o address recognized, HIO accepted, and
device controller busy at the time of the HIO,
and status information is correct.

Not possible.

000

Not possible.

010

Pari ty error detected on returned status and/or
condition code. The result of the HIO is
i ndeterm i nate.

f) .... fn --Tn
-_.-

operation.

HID

If the R field of HIO is an even value and not 0, the condition code is set, register Ru1 is loaded as shown above,
and register R contains the following information.

HALT INPUT/OUTPUT
0Nord index alignment, t privileged)

HALT INPUT/OUTPUT causes the addressed device to immediately halt its current operation (perhaps improperly,
in the case of magnetic tape units, when the device is
forced to stop at other than an interrecord gap). If the
device is in an interrupt-pending condition, the condition
is cleared.
.
If the R field of the HIO instruction is 0, the condition
code is set, but no general registers are affected.

tWhen indexing operation code 4F instructions (HIO, RIO,
POLP, POLR), the programmer must make certain that the
summation of the contents of the index register and the I/o
address (bits 18-31 of the instruction word) does not affect
bits 15-17. When indirect addressing is used, the contents
of the indirect address location (bits 15, 16, and 17) must
specify the desired operation code extension.

1 1 0 0

I/o address not recognized, HIO not accepted,
and no status information returned to general
registers.

1 1 1 0

Incoming parity error detected by processor
and HIO aborted. No status information returned to general registers.

Input/Output Instructions

121

If CC4 = 1, the MIOP is in the test mode and the meaning
of the condition code during an HIO is:
2 3 4

Condition code settings are as shown below:

o
000

Unit is performing an Order Out operation.

010

Unit is performing an Order In operation.

Unit is performing a Data Out operation.

Processor Interface detected parity error on returned status and/or condition code. The result of the HIO is indeterminate.

2 3 4

Meaning

0 0 -

I/O address recognized.

Meaning

1 0 1 -

Parity error detected on returned status and/or
condition code. The result of the RIO is
indeterminate.

1 1 0 -

I/O address not recognized.

POLP

POLL PROCESSOR

0/'Iord index alignment, t privileged)

Unit is performing a Data In operation.
BCF detected whi Ie unit performing a Data In
operation.

RIO

RESET INPUT/OUTPUT

POLL PROCESSOR causes the addressed unit to return unit
fau It status in bi ts 16-31 of reg i ster Rtt. Th is status i nformation is unit dependent (see Appendix C, Table C-l).

0/'Iord index alignment, t privileged)
In addition to the operation code of X'4F', bits 15, 16,
and 17 must be coded as 010, respectively.
Affected: (R), CC1, CC2, CC3
RESET INPUT/OUTPUT causes the selected lOP to generate
an I/O reset signal to all devices attached to it. In addition to the operation code X'4f!, bits 15, 16, and 17 must
be coded as 001, respectively.
An RIO instruction resets the selected unit in the same
manner as ZCRIO on the operator's control console. However, unlike the control command, the RIO instruction
resets only the addressed unit and may be controlled by
the executing program. Since the BP may be addressed as
an lOP, it wi II accept an RIO instruction that causes the
BP to reset itself in the same manner as ZCRBP. (Note that
this procedure is not normal practice.)
Cluster addresses (CA), bit positions 18-20, may have
values of X'O'-X'7'. Cluster addresses X'0'-X'6' may be
assigned to any cluster containing processors (i. e., -BP
and MIOP). In a monoprocessor system, cluster address
X'O' is assigned to the cluster containing the basic processor (BP). Cluster address X'7' is assigned only to the
cluster containing a system processor. If CA equals X'7',
the UA field is reserved. Unit addresses (UA), bit positions 21-23, may have values of X'O'-X'?'. Unit addresses are required only if the cluster address is X 'O'.;.X'6'
(i .e., cluster contains either a BP and/or MIOP). Unit
addresses X'O'-X'5' may be assigned to processors within
the cluster. Unit address X'5', in cluster X'O' is reserved for the BP. Unit address X'6' is assigned always
to the Ml and ~mit address X'7' is assigned always to the
PI for a II cI usters.
Status information is returned only in the condition code
bits. The R field is not used.
Affected: CC 1, CC2, CC3

122

Input/Output Instructions

Condition Code settings are as shown below:
1 2 3 4

Result of POLP

0 0 -

Processor fault interrupt not pending.

1 0 -

Processor fault interrupt pending.

1 0 1 -

Pari ty error detected on returned status and/or
condition code. The result of the POLP is
indeterminate.

1 1 0 -

Unit address not recognized.

POLR

POLL AND RESET PROCESSOR
(Word index alignment, t privileged)

POLL AND RESET PROCESSOR causes the selected unit to
return unit fault status in bits 16 to 31 of register Rtt and
resets the unit's fault status register. This status information is unit dependent (see Appendix C, Table C-1).

t See footnote to HIO instruction.
ttThis fault status is duplicated in bits 0 to 15 of register R.

The POLR instruction also resets and clears this unit's
Processor Fault Interrupt signal and the error status register. In addition to the operation code of X'4F', bits 15,
16, and 17 must be coded as 011, respectively.
Affected: (R), CC1, CC2, CC3

Condition code settings for the POLR instruction are:
1 2 3 4

Result of POLR

0 0 -

Processor fault interrupt not pending.

0 -

1 -

1 1 0 -

AID

For some conditions (transmission errors, incorrect length),
two or more flags must be properly coded (see Chapter 4
for further detai Is on IOCDs).
Some error conditions {e. g., pority error on reading command
doubleword) will unconditionally cause an I/o interrupt.
The various conditions which may result in an I/O interrupt, the coding of the corresponding control flags within
the IOCD, and the bit position within the status word (returned to register R) that indicates the presence (1) or ab~
sence (0) of that interrupt condition are listed below:

Condition

Control Flags
Coding

Status
Bit Set

Zero byte count

IZC = 1

Channel end

ICE

Transmission memory error

IUE

= 1,

HTE

Write lock violation

IUE

= 1,

HTE

Incorrect length

IUE = 1, HTE
and SIL = 0

8, 12

Processor fault interrupt pending.
Pari ty error detected on returned status and/or
condition code. The result of the POLR is
indeterminate.
Unit address not recognized.

ACKNOWLEDGE INPUT/OUTPUT INTERRUPT
(Word index alignment, privileged)

ACKNOWLEDGE INPUT/OUTPUT INTERRUPT is used to
acknowledge an input/output interrupt and to identify the
I/o subsystem (processor, device controller, device) that
is causing the interrupt and why. If more than one I/O
subsystem has' an interrupt pending, only the subsystem
with the highest priority will respond to the AIO. Bits 1823 of the effective virtual address of the AIO instruction
(normally used to specify the cluster and unit addresses of
the I/o address field) must be coded 000000 to specify
the standard I/O system interrupt acknowledgment {other
codings of these bits are reserved for use with special I/o
systems}. The remainder of the I/O selection code field
{bit positions 24-31} are not used in the standard I/o interrupt acknowledgment (the address of the interrupt source
is a part of the response from the standard I/o system to
the AIO instruction).
Standard I/O interrupts are program controlled via the control flags (IZC, ICE, IUE, HTE, and SIL) within the I/O
command doublewords (lOCDs) that comprise the command
list for the I/o operation. If a particular flag is coded as
a 1 and if the corresponding condition occurs within the
I/O operation, then an I/o interrupt is requested (e. g. , if
the IZC flag is set to 1 and if the byte count for the I/O
operation has been decremented to zero, then an I/O
interrupt is requested by that I/O subsystem to indicate the
end of that I/o operation; if the IZC flag is coded as a 0,
no I/o interrupt is requested as a result of the byte count
bei ng decremented to zero).

If two or more flags are coded to cause an interrupt for two
or more conditions, an interrupt is requested whenever any
of the IIflagged ll conditions is detected.

Memory address error,
lOP memory error,
lOP control error, or
device connection address
parity error

) (no flog needed)

Transmission data error

iUE = i, HTE = i

Unusual end

IUE

lOP halt

IUE

12, 14

9, i2

Interrupts may also be requested by certain I/o devices
when they execute specific orders {e. g., when a magnetic
tape unit executes a Rewind and Interrupt order}. Refer
to the applicable peripheral reference manual for further
details.
When a device interrupt condition occurs, the lOP forwards
the request to the interrupt system I/o interrupt level. If
this interrupt level is armed, enabled, and not inhibited,
the BP eventually acknowledges the interrupt request and
executes the XPSD instruction in main memory location
X'5C', which normally leads to the execution of an AIO
i nstructi on.
For the purpose of acknowledging standard I/O interrupts,
the lOPs, device controllers, and devices are connected in
a preestablished priority sequence that is customer-assigned
and is independent of the physical locations of the portions
of the I/O system in a particular installation.

If the R field of the AIO instruction is 0, the condition code
is set but the general register is not affected.

Input/Output Instructions

123

If the R field of AIO is not 0, the condition code is set and
register R is loaded with the following information.

2 3 4

Result of Ala

Parity error detected on returned status and/or
condition code. The result of the AlO is
i ndetermi nate.

1 0

DC Status Byte

The functions of bits within the DC status byte (which are
unique to the device and device controller) are described
in applicable peripheral reference manuals. The functions
of other bits in the AIO response word are described in
Tables 18, 19, and 20.
The AlO instruction resets the interrupt request signal for
the I/o subsystem responding to the AIO (i. e., I/o subsystem identified by bits 19-31 of register R).

1 0 0

Unusual condition interrupt recognized and
reset. Status information in general register
is correct.

1 1 0

Not possible

1 0 0 0

Interrupt recognized and reset. Status information not returned.

1 1 0 0

No I/O device requesting an interrupt and
no status i nformati on returned to the genera I
register.

1 1 1 0

Not possible.

Affected: (R), CC

If CC4 = 0, the MIOP is operating in a normal mode of
operation and the condition code settings for AIO are
shown below:

If CC4 = 1, the MIOP is in the test mode and the meaning
of the condition code during an Ala is:

2 3 4

Result of AlO

0 0 0

Normal interrupt recognized and reset.
Status information in general register is
correct.

0 1 0

124

Not possible. Parity error on returned status
and/or condition code. The result of the Ala
is i ndetermi nate.
Not possible.

Input/Output Instructions

Unit is performing an Order Out operation.

Unit is performing an Order In operation.

Unit is performing a Data Out operation.

0
0

Meaning

Parity error detected by Processor Interface.
0

Unit is performing a Data In operation.
BCF detected whi Ie unit is performing a Data
In operation.

4. INPUT/OUTPUT OPERATIONS
To accommodate the variety and number of I/o devices
which may be required for scientific and commercial applications, a Xerox 550 computer system may include
the following: External Direct Input/Output (DIO) interface, and Multiplexor Input/Output Processors (MIOPs).

more of the following types of device controllers may be
connected to (.!n MIOP:
1.

Single-unit device controller {internal or external}.

Mu Iti -un it dev ice con tro II er (i n terna I or externa I).

Unit-record controller (internal or external).

EXTERNAL 010 INTERFACE
An external DIO interface permits standard and specially
designed I/O devices to perform I/o operations (normally
in a real-time environment) that are controlled directly by
the basic processor (BP). Appropriate control signals and
up tC' one word (32 bits) of data may be exchanged between
the BP and an addressed I/O device for each READ DIRECT
or WRITE DIRECT instruction executed by the BP.
During a WRITE DIRECT instruction (Mode 2 through F),
the BP holds the control and data lines stable until an
acknowledgment signal is received from the addressed I/O
device. During a READ DIRECT instruction (Mode 2
through F), the BP holds the control lines stabl e unti I the
addressed I/O device furnishes the data accompanied with
an acknowledgment signal. Any delay encountered in
receiving the acknowledgment signal, for either READ
DIRECT or WRITE DIRECT instructions, does not have an
adverse effect upon I/O operations being performed by
the MIOP.
Refer to Xerox publication 90 09 73 (Interface Design
Manual) for further detai Is pertaining to the external DIO
interface. Also, refer to appropriate peripheral reference
manuals for detai Is on control and data signals.

MULTIPLEXOR INPUT/OUTPUT PROCESSOR (MIOP)
An MIOP permits standard and commercially available I/O
devices (e. g., card readers, card punches, magnetic tape
units, etc.) to be controlled primarily by individual I/O
subchannels within the MIOP and associated device controllers. Depending upon the number of I/O subchannels
assigned (maximum of 16, as described under II Device Controllers"), an equivalent number of I/O operations may be
performed simultaneously.

Generally, an internal device controller is physically connected via the internal I/O interface.
An external device controller is located remotely to the
MIOP and may require one or more separate chassis to accommodate it.
A single-unit device controller (internal or external) is
specifically designed to control only one I/O device,
usually a unit-record device such as a card reader, a card
punch, or a line printer. Characteristics of a single-unit
device controller are dependent upon the device controlled.
(Refer to an appropriate peripheral reference manual for
further information. )
A multi-unit device controller (internal or external) is
specially designed to control more than one I/O device,
where all the I/O devices are of the same type {e. g.,
magnetic tape units or RADs}. However, only one I/O
device at a time may be actively involved in a data transfer operation. Characteristics of a multi-unit device controller are dependent upon the I/O devices controlled. For
example, a multi -unit device controller for magnetic tape
units may control up to eight units. (Refer to an appropriate
peripheral reference manual for further information. )
Unit-record controllers {internal or external} are designed
to control up to eight unit record type of I/O devices {e. g.,
card readers, card punches, line printers}. All I/O devices attached to a unit-record controller need not be of
the same type. All I/O devices attached to a unit-record
controller may perform separate I/O operations, including
data transfers, simultaneously.
The number of device controllers, as well as the number of
I/O devices, that may be connected to an MIOP is dependent upon the following considerations:

The maximum number of I/O subchannels within an
MIOP is 16.

Each single-unit device controller (internal or external)
requires one I/o subchannel.

Each multi -unit device controller (internal or external)
requires one of the first eight subchannels within
the MIOP.

DEVICE CONTROLLERS
All I/O devices associated with an MIOP are connected
via an appropriate device controller. Depending upon the
number and type of I/O devices to be connected, one or

Input/Output Operations

125

Each unit-record controller (internal or external)
requires one I/o subchannel per each unit record device attached, up to a maximum of eight.

The maximum number of internal device controllers
within an MIOP is eight (where a unit-record device
controller is equivalent to one, regardless of the
number of assigned subchannels).

Any I/o subchannel not assigned to an internal device controller may be assigned to an external device
controller. Thus, if an MIOP has no internal device
controller, all 16 I/O subchannels may be assigned
to external device controllers.

be accomplished by including a control lOCO within
the command list (see II Transfer in Channel ll under
"Control 10CDsll).
4.

Each lOCO is comprised of two words in contiguous
memory word locations. The first word must be stored
in an even memory word location and the second
word must be stored in the next "consecutive (odd)
memory word location. Each lOCO is either an
operational lOCO or a control lOCO and contains
coded parameters to define either a complete I/o
operation or an integral portion of an I/O operation.
(See" Operational lOCO" and "Control lOCO" for
further detai Is. )

OPERATIONAL lOCO

INPUTjOUTPUT PROCESSOR [lOP) FUNDAMENTALS
This section contains general information, programming
concepts, and definition of terms pertaining to I/o operations performed by Input/Output Processors (i. e., MIOP).
The large variety of I/O devices which may be used with
these lOPs precludes a detailed or exhaustive description of features which are unique to each device. likewise, a general reference" Refer to an appropriate Xerox
peripheral reference manual" is made rather than citing
specific manuals.

An operational lOCO may contain up to five fields of
parameters, as required, to define either an entire I/O operation or an integral portion of an I/o operation. The
general format and description of parameters contained
within an operational lOCO are as follows":

Within this manual, the following terminology is used
to differentiate the hierarchy of control during an I/o
operation: The BP executes instructions, the lOPs execute commands, and the device controller/device execute orders.
ORDER

COMMAND LIST
Each I/O operation performed by an lOP must be defined
by a command list. The characteristics and requirements
of a command iist are as foiiows:
1.

126

This 8-bit field (bit positions 0-7), if required, may be
coded to spec ify ei ther an input or an output order that
is executed by the device controller/device. General
coding formats and functions of typical I/o orders are
Iisted below:

It is normally created by a BP-executed program
prior to the time that the defined I/O operation is initiated. It must reside in main memory when the I/O
operation is initiated and subsequently executed.

Bit Position
1 2 3 4 5 6 7

Order

Function

M M M M M MOl

Write

Output operati on

Depending upon various programming considerations,
the command list may be contained within one or more
areas of memory and each area may be comprised of
one or more I/o command doublewords (lOCOs).

MMMMMM 1 0

Read

Input operati on

MMMMMM1 1

Control

Output control
i nformat ion

M M M MOl 0 0

Sense

Input control
information

MMMM 1 1 0 0

Read
Backward

Input data, in reverse
sequence

Command list continuity between lOCOs relating to
the same logical record or to the same logical file
may be specified (see "Data Chain Flag ll and IICommand Chain Flag ll under 1I0perationai 10CDslI). Command list continuity between portions of a command
list located in different areas of main memory may

Input/Output Processor (lOP) Fundamenta Is

Orders that are executed by a specific type of device are
listed and described in the appropriate Xerox peripheral
equipment reference manual.
When an operational 10CD is fetched by the lOP, the content of the order field, if required, is loaded into an order
register within the device controller/device. If two or
more 10CDs are required to define a logical record (as described under "Data Chain Flag"), the order obtained from
the first 10CD prevai Is for all subsequent 10CDs within that
logi cal record and any orders contained within the subsequent
10CDs are ignored.

in Channel command, as described later, before fetching
the next operational 10CD.) As a result of fetching the
next operational 10CD, all parameters, except the I/O
order, are updated and the device controller/device continue to operate as if the I/o operation were defined by
a single IOCD (i. e., the data chain operation is transparent
to the device controller/device). If data chaining is not
specified, the lOP wi II generate a "count done" signal when
the byte count of the current 10CD is reduced to zero. The
"count done" signal indicates that the lOP has completed
all data transfers for the current logical record. However,
as described under "Interrupt on Channel End Flag", the
I/o order is not completed until the device signals a "channel end".

MEMORY BYTE ADDRESS
This 22-bit field (bit positions 10-31), if requi red, is
coded with the initial memory byte address for .the I/o operation that wi II be performed when the current IOCD is
executed. When the IOCD is fetched by the lOP, the content of the memory byte address field is loaded into a
memory byte address register within the appropriate I/O
subchannel of the lOP. Thereafter, the content of the
memory byte address register is incremented (or decremented
during Read Backward operations) by one for each byte of
data or information transmitted, even though access to main
memory may be inhibited (as described under "Skip Flag")
or the data is rejected by a memory unit (as described under
"Write Key").
Depending upon the characteristics of the I/O device, the
content of bit positions 10-31 may either be ignored (e. g.,
II

Interrupt at Zero Byte Count Flag (Bit Position 33). If an
I/O interrupt is to be requested when the byte count of the
current 10CD is reduced to zero, the Interrupt at Zero
Byte Count (IZC) flag must be coded as a 1. If the I/O
interrupt level within the interrupt system (location X' 5C)
is armed, enabled, and not inhibited, the request will be
processed by the BP in accordance with the priority that
prevai Is within the interrupt system, the lOPs, and the I/O
subchannels within an MIOP. The occurrence of an I/O
interrupt because of a zero byte count condition is reported
as status information (bit position 10 of register R) when the
BP executes an AIO instruction (normally part of the I/O
interrupt handling routine). The I/O interrupt request may
be processed without interfering with the I/o operation.
(Note: An I/O interrupt may be requested at "channel end"
or on "unusual end" condition, as described later. )

Rewind II order for maanetic taoe units) or soecifv memorY

byte locations that co;tain supplement~1 co~trol information
(e. g., starting address for a disk seek operation). Refer to
an appropriate Xerox peripheral equipment reference manual for further detai Is.

FLAGS
Each operational 10CD contains eight control flags (bit
positions 32-39). As described below, each control flag
is coded to specify a particular control function that may
be performed by the lOP either during or at the end of the
current IOC D.

Data Chain Flag (Bit Position 32). Coding ofthe data chain
flag is dependent upon the number of 10CDs required to
define the data transfers for a logical record. If two or
more 10CDs are required (e. g., to perform a "gather-write"
or a "scatter-read II operation), the data chain flag of each
operational IOCD, except the last IOCD, must be coded as
a 1. The data chain flag of the last 10CD or the only
10CD (if the record is defined by a single 10CD) is coded
as O. If data chaining is specified and no error conditions
are encountered, the lOP wi II automatically fetch the next
operational 10CD when the byte count (described later) of
the current IOCD is reduced to zero. (Note: The lOP may
also fetch and execute a control 10CD containing a Transfer

Command Chain Flag (Bit Position 34). Command chaining
permits an I/O device to execute a multiple number of
orders relating to the same I/O operation in a consecutive
manner (e. g., when reading a multi-record file, the I/O
device may automatically receive a new Read order upon
compl eti ng the current Read order wi thout the BP executing another SIO instruction). Command chaining, if required, is specified by coding the command chain flag as
a 1 in the IOCD of each record, except the last.
If command chaining is specified, the lOP wi II fetch the
next operational 10CD when the device signals a "channel
end" unless terminated by an "unusual end" condition. As
a result, new parameters are stored in the appropriate
registers within the I/o subchannel and a new I/o order
is received by the device controller/device.
Thus, an lOP wi II automati ca IIy access mai n memory and
fetch the next operational 10CD if either data chaining or
command chaining is specified. If data chaining and command chaining are both specified in the same command
doubleword, a data chaining operation wi II be performed if
the byte count is reduced to zero before the device signals
a "channel end" and a command chaining operation will be
performed if a "channel end" occurs before the byte count
is reduced to zero. If neither data chaining or command
chaining is specified, the I/O operation is completed when
the device signals a "channel end". Note that command
chaining is inhibited by "unusual end".
Input/Output Processor (lOP) Fundamentals

127

Interrupt at Channel End (Bit Position 35). An I/O interrupt
may be requested when the device signals a "channel
end" (signifying that the current order has been either completed or terminated) by coding the Interrupt at Channel
End (ICE) flag as a 1. If the I/O interrupt level within the
interrupt system (location XISC') is armed, enabled, and not
inhibited, the request will be processed by the BP in accordance with the priority that prevai Is within the interrupt
system, the lOPs, and the I/O subchannels of the MIOP.
The occurrence of an I/O interrupt because of a "channel
end ll is reported as status information (bit position 11 of
register R) when the BP executes an AIO instruction (normally part of the I/O interrupt-handling routine). The I/O
interrupt request may be processed without affecting the
I/O operation. (Note: Specific conditions under which a
IIchannel end ll signal may be generated are dependent upon
the characteri sti cs of the devi ce. Refer to an appropri ate
Xerox peripheral reference manual for further detai Is. )

Control Check Error (CCF).

lOP Memory Error (IOPME).

Bus Check Fault (BCF) whi Ie fetching an 10CD.

Memory interface Error (MIE) while fetching an lOCO.

Bus check fault (BCF) whi Ie fetching data.

Interrupt on Unusual End Flag (Bit Position 37). If an I/O
Interrupt is to be requested when an "unusual end" condition
is detected whi Ie either fetching or executing an 10CD,
the Interrupt on Unusual End (IUE) flag must be coded as
a 1. If the I/O interrupt level within the interrupt system
(location XI5C') is armed, enabled, and not inhibited, the request wi II be processed by the BP in accordance wi th the
priority that prevalis within the interrupt system, the lOPs,
and the I/O subchannels within an MIOP. The occurrence
of an I/O interrupt because of an "unusual end" condition
is reported as status information (bit position 12 of register R) when the BP executes an AIO instruction (normally
part of an I/O interrupt-handling routine). The I/O interrupt request may be processed wi thout affecti ng the progress
of the I/O operation.

Transmission Data Error (TDE); may also be detected by
device controller.

If the IUE flag is coded as a 0, an "unusual end" condition
may be detected but no interrupt wi" be requested.

Transmission Memory Error (TME).

Write Lock Violation (WLV), during input operations
only.

Incorrect length, conditional; see "Suppress Incorrect
Length Flag".

Memory Interface Error (MIERR) whi Ie fetching data.

Halt on Transmission Error Flag (Bit Position 36). The following errors (or "unusual end" condition) may be detected
by the MIOP when an lOCO is being executed:

If the HTE flag is coded as a 0, the above errors are recorded
when detected and reported as status information when the
BP executed an SIO, TIO, or HIO instruction, but the I/o
operation is not halted.
If the HTE flag is coded as a 1, and any error (as listed
above) is detected, the I/o operation is terminated immediately. The error is also reported as status information
when the BP executes an SIO, HIO, or TIO instruction.
The HTE flag must be coded identically in every lOCO associated with the same logical record. Thus, if data chaining is specified, the HTE flag in the new lOCO must be the
same as the HTE flag in the previous lOCO. This restriction
applies to data chaining only, and not to command chaining.
In addition to the "unusual end" conditions listed above,
which may terminate the I/O operation only if the HTE
flag is coded as a 1, any of the following "unusual end"
conditions wi II unconditionally terminate the I/O operation:
1.

Memory Address Error (MAE).

lOP Control Error (IOPCE).

128

Input/Output Processor (lOP) Fundamentals

Suppress Incorrect Length Flag (Bit Position 38). An incorrect length condition may occur when the specified byte
count is not equal to a fixed or prescribed byte count for a
record (e. g., attempting to read more than 80 columns of
data from a punched card). Specific conditions under which
an incorrect length signal is generated are dependent upon
the device. Refer to an appropriate Xerox peripheral equipment reference manua I for further detai Is.
If the Suppress Incorrect Length (SIL) flag is coded as a 0
when an incorrect length condition is detected, it is reported as an incorrect length and, depending upon the device, may be reported as an "unusual end". If the HTE flag
is aiso coded as a I, the I/O operation is terminated and
reported as an "unusual end".
If the SIL flag is coded as a 1 when an incorrect length condition is detected, it is reported as an incorrect length but
suppressed as an "unusual end". Hence, the I/o operation
is not terminated.
The presence or absence of an incorrect length condition
is reported as status information when the BP executes an
SIO, HIO, AIO, or TIO instruction.

Skip Flag (Bit Position 39). If the Skip (S) flag is coded as
a 0, it has no effect upon the I/o operation.
If the S flag is coded as a 1, the lOP is inhibited from accessing main memory and consequently no data is transferred
between the main memory and the data buffers of the I/O
subchanne I. All other operations or functions within the

I/o subchannel (i. e., data transfers between the device
and data buffers, updating the memory byte address and
byte count, and functions as specified by the control flags)
are performed ina norma I manner.
For input operations, the Skip flag (in conjunction with
data chaining) provides the capabi lity to selectively read
portions of a record.
For output operations, the lOP wi" generate and transmit
zeros (X1OOI) unti I the byte count is reduced to zero. Thus,
for example, if the lOCO contains a Punch Binary order, a
byte count of 120, and the S flag is coded as a 1, a blank
card may be punched without accessing main memory
for data.

WRITE KEY
This four-bit field (bit positions 40-43), if required, may
be coded with an appropriate write key. During input operations and providing the Skip control flag is coded as aD,
the lOP will access main memory and furnish a memory unit
with up to four bytes of data or information accompanied
with a four-bit write key. If the write key matches the
preassigned write lock for the memory word location accessed, or if either the key or lock has a value of 0000,
the memory unit accepts and stores the information. If the
write key does not match the write lock, and neither the
key nor the lock has a value of 0000, the memory unit rejects the information, does not disturb the previous content,
and transmits a Write Lock Violation (WLV) signal to the
lOP. The write key/write lock relationship is compared
every time a memory word location is accessed for storing
data or information. (Note: The write key/write lock relationship may change during an input operation when the
byte address is incremented (or decremented) across a memory page boundary.)
As long as the write key matches the write lock for each
memory word location accessed, or the value of either the
lock or the key is 0000, the input operation is performed
as specified by the other parameters within this lOCO; or
the input operation is terminated by an "unusual end" condition which can not be inhibited (i. e., memory address
error, control check fault, or lOP memory error).

If the HTE control flag is coded as a 1 when a WLV signal
is received, the I/O operation is terminated -immediately.
If either the ICE or IUE control flag is coded as a 1, an
I/o interrupt is requested.
If the HTE control flag is coded as a 0 when a WLV signal
is received, the I/O operation continues in a normal manner, even though the data or information may be rejected
by a memory uni t.
When the lOP receives a WLV signal, the WLV bit within
the status information register is set to 1 and remains set
until a new VO operation is initiated within this I/o subchannel by an SIO instruction. Thus, after the first WLV
signal has been recorded, subsequent WLV signals have no

further effect upon the WLV bit. The status of the WLV
bit is reported when the BP executes an SIO, TIO, TDV,
HIO, or AIO instruction.
The contents of the write key fie Id is not required and may
be ignored when the write key/write lock memory protection
feature is not operative (i. e., during any output operation
or during any input operation, if the Skip control flag of
the current lOCO is coded as a 1).

BYTE COUNT
This 16-bit field (bit positions 48-63), if required, may be
coded to specify the total number of data or information
bytes that are to be transmitted by the current lOCO.
The minimum number of bytes is 1 and the maximum is
65,356 bytes (16,384 words). When the lOCO is fetched,
the content of the byte count field is loaded into a byte
count register within the appropriate I/o subchannel.
Thereafter, the content of the byte count register is decremented by one for each byte transmitted and then tested
for a zero byte count condition. (Note: As a consequence
of decrementi ng before testi ng for a zero byte count condition' an initial byte count value of 0 is interpreted as
65,356 bytes.) Unless the I/o operation is terminated
(e. g., as the result of detecting an "unusual end ll ) , data
is transmitted unti I the byte count is reduced to zero. At
any time, the progress of the I/O operation may be ascertained by evaluating the current byte count which is
furnished as status information when the BP executes an
SIO, no, HIO, or TDV instruction. (That is, current byte
count is equal to the number of bytes remaining to be transmitted and Inltlai byte count minus current byte count is
equal to the number of bytes transmitted.) When the byte
count is reduced to zero, the MIOP may perform the following functions:

Transmit a "count done" signal to the device controller/
device if data chaining is not specified.

Request an I/O interrupt, if the IZC flag is coded
as a 1.

Fetch the next lOCO, if the data chain flag is coded
asa1.

Depending upon the characteristics of the I/O device,
certain I/O orders (e. g., Rewind for magnetic tape units)
may nat require a byte count field. In such case, the byte
count field is ignored. Refer to an appropriate Xerox peripheral equipment reference manual for further detai Is.

CONTROL IDeO
A control lOCO may contain either a Transfer in Channel
or a Stop command.

Input/Output Processor (lOP) Fundamentals

129

Transfer in Channel. A controllOCD containing a Transfer
in Channel command has the following format:

The Transfer in Channel command is executed within the
lOP and has no direct effect on any of the I/O elements
external to the addressed lOP. The primary purpose of this
command is to permit branching within the command list
{i. e., fetching the next operational 10CD from a pair of
memory word locations other than the next two consecutive
word locations}.
When the lOP executes the Transfer in Channel command,
it loads the command address register of the appropriate
I/O subchannel with the contents of bit positions 13-31
(the "next command doubleword address" field), fetches
and loads the new operational 10CD into appropriate registers within the I/O subchannel and order register within
the device controller/device (unless data chaining is specified), and then executes the new 10CD. (Bit positions 8-12 and 32-61 are ignored and should be coded as
zeros. )
If data chaining or command chaining is specified in the
10CD preceding the 10CD containing a Transfer in Channel
command, the chaining flags are not significant to nor
altered by the Transfer in Channel command.
When used in conjunction with command chaining, Transfer
in Channel command facilitates the control of devices such
as unbuffered card punches or unbuffered line printers. For
example, assume that it is desired to present the same card
image twelve times to an unbuffered card punch. The punch
counts the number of times that a record is presented to it
and automatically generates a "chain modifier" signal when
twelve rows have been punched. The command address
register within the I/o subchannel is incremented by two
by the "chain modifier" signal and the next consecutive
10CD within the command list is skipped over {not fetched
or executed}. A command list for punching two cards might
be as shown in the following example:
Locations

Description of Command

A, A + 1

Punch row for card 1, command chain.

A + 2, A +3

Transfer in Channel to location A.

A +4, A +5

Punch row for card 2, command chain.

130

Input/Output Processor (lOP) Fundamentals

Locations

Description of Command

A +6, A + 7

Transfer in Channel to location A +4.

A+8, A+9

Stop

The Transfer in Channel command can be used also in conjunction with data chaining. As one example, consider
a situation often encountered in data acqUisition applications, where data is transmitted in extremely long, contiguous streams. In this case, the data can be stored
alternately in two or more buffer storage areas so that
computer processing can be carried out on the data in one
buffer whi Ie additional data is being input into the other
buffer. The command list for such an application might be
shown in the following example:
Locations

Descri pti on of Command

B, B+ 1

Read data, store in buffer 1, data chain.

B+2, B +3

Store into buffer 2, data chain.

B+4, B+5

Transfer in Channel to location B.

If the lOP encounters two successive Transfer in Channel
commands, an lOP control error (IOPCE) occurs and the
I/O operation is terminated immediately. An 10PCE is
reported as status information (bit 13 of register Rul) when
the BP executes an SIO, HIO, TIO, or TDV instruction.

STOP
A control IOCD with a Stop command has the following
format:

The Stop command causes certain devices to stop, generate
a "channel end" signal, and also request an I/o interrupt
if bit 0 in the IOCD is coded as a 1. If the I/O interrupt

level within the interrupt system (location XISC') is armed,
enabled, and not inhibited, the request wi II be processed
by the BP in accordance with the priority that prevails
within the interrupt system, the lOPs, and the I/o subchannels within an MIOP. The occurrence of .an I/O
interrupt because of a Stop command is reported as status
information (bit position 7 of register R) when the BP
executes an AIO instruction (normally part of an I/O
handling routine).
Bi t positi ons 1-7 must be coded as zeros. Bi t posi ti ons 8-31
and 40-63 are ignored; but it is recommended that they also
be coded as zeros. Bit positions 32-39 are ,device dependent and must be coded as specified in the appropriate peripheral reference manual.
The Stop command is primari Iy used to terminate a command
chain for an unbuffered device, as i "ustrated in the first
example given for the Transfer in Channel command. Note
that not a" devices recognize the Stop order.

FETCHING PHASE

AI though the services of the BP are not requ ired duri ng
this phase, the BP may at any time execute either a TIO,
TDY, or POL instruction without interfering with the I/O
operation. However, excessive TIOs and TDVs may cause
a data overrun condition. The BP may also execute either
an HIO or RIO instruction and stop the I/O operation. (An
HIO may leave the device in an unpredictable state; an
RIO resets all controllers and devices on the addressed lOP. )
As a result of accepting an SIO instruction, a command address register within the I/O subchannel (assigned to control the addressed device controller/device) is loaded with
the first command doubleword address, the content of General Register 0 when the SIO instruction is accepted. At
the appropriate time, as determined by the priority, the
device controller/device wi II request that the lOP access
main memory and fetch the first word of the 10CD from an
even memory word location and increment the command
address register by one. The disposition of the first word
is dependent upon the contents of the first word.

If the order field contains an I/O order for a device

I/O OPERATION PHASES
This section describes the general sequence of events (or
phases) of any I/o operation performed by an lOP, the
function performed by the BP, lOP, and device controller/
device during each phase, and a description of each type
of I/O operation including the applicabi lity of parameters
that may be contained within a typical operational 10CD.
For explanation purposes, each I/o operation has five major phases: preparation, initiation, fetching, executing,
and termination phase. Each phase is furtner described
below.

PREPARATION PHASE

Before an I/o operation may be performed by an lOP, an
appropriate command list must reside in main memory.

INITIATION PHASE

Assuming that an appropriate command list resides in main
memory, an I/O operation is initiated only if the BP executes an 510 instruction that is accepted by the addressed
lOP, device controller, and device. The acceptance or
rejection of an SIO instruction is contingent upon conditions within the addressed lOP, device controller, and
device and is indicated by the condition codes at the completion of the SIO instruction. In either case, the BP is
able to perform other instructions or tasks immediately after
executing an SIO instruction. (Refer to "510" instruction,
Chapter 3, for further detai Is. )
A successful SIO instruction causes the addressed device to
go from the "ready" condition to the II busy II condition.

controller/device, the content of the order field is either
loaded into an order register within the appropriate device
controller/devi ce or ignored (if the 10CD is being fetched
for a data chained operation). If the order is a Read Backward order, a control flag is also set within the lOP which
allows the memory byte address to be decremented rather
than incremented during the data transfer.
For all orders (excluding the Transfer in Channel command,
described below), the contents of bit positions 10-31 of the
first word is loaded into a memory byte address register of
an apprapriure i/O :)ubd,unnt::L Dt::peflJifl9 vjJVfl tho:: Vo
order, as described under "Execution Phase", the content of
the memory byte address register may be used or ignored. If
used, it specifies which memory word location is to be accessed and also the number of bytes of data (or control information) to be transferred into or out of that location.

If the order field contains a Transfer in Channel command,
it is recognized and executed immediately by the lOP. The
content of bit positions 13-31 (designated as the "next command doubleword address" field) is loaded directly into the
command address register. The Transfer in Channel command is recognized and executed by the lOP, it is fetched
and executed as the result of fetching one word (rather than
two), and it is transparent to the device controller/device
(that is, it is executed without affecting the continuity of
an order that is data chained or an I/O operation that is
command chained). Note: Although bit positions 0-3
and 8-12 are currently ignored, it is recommended that they
be coded as zeros.
Immediately after executing a Transfer in Channel command,
the lOP will automatically fetch the first word of the next
10CD as specified by the contents of the "next command
doub Ieword address" fie Id. If the orderfi e Id of the nextI OC D
also contains a Transfer in Channel command, the I/O operation is terminated immediately and the lOP enters a Halt state
because an lOP control error (IOPCE) occurred (attempting
to execute two successive Transfer in Channel commands).

I/O Operation Phases

131

Depending upon the control function performed, certain
Control orders may be a part of an I/O operation
which may be continued after the Control order is
executed. For example, an I/O operation involving
a magnetic tape unit may contain a Rewind order to
reposition the tape prior to reading (or writing) one or
more records.

Otherwise, the first word of the next 10CD is fetched and
loaded as described above, and the second word is fetched
and loaded as described below.
Since the Transfer in Channel command permits 10CDs to
be fetched from nonconsecutive locations, 10CDs containing Transfer in Channel commands may be included within
a command list either to achieve command list continuity
from one segment af a command list to another segment or
to construct reiterative loops.
For all 10CDs, except a control 10CD containing a Transfer in Channel command, the lOP will automatically access
main memory at the appropriate time, as determined by the
priority that prevails for accessing main memory, and fetch
the second word of the 10CD from the next consecutive
ascending (odd) memory word location of the command list
and increment the command address register by one. Thus,
in all cases, after a fetching operation is completed, the
content of the command address register wi II be an even
(or doubleword) address.
The contents of the second word are stored in appropriate
registers within the I/O subchannel. Depending upon the
I/O order, as described under "Execution Phase", the contents of the various fields are either used or ignored.
In addition to the lOP Control Error (IOPCE), the following
types of "unusual end" conditions may be detected during
the fetching phase of an I/O operation: Memory Address
Error (MAE), Control Check Fault (CCF), lOP Memory Error
(IOPME), Bus Check Fault (BCF), and Memory Interface
Error (MIE). The detection of any of these errors causes the
I/O operation to be terminated and if the IUE flag is set to
a 1, an "unusual end" interrupt is requested.

EXECUTION PHASE

Although the services of the BP are not required during
this phase, the BP may at any time execute either a TIO,
TDV, or POL instruction without interfering with the I/o
operation. However, excessive testing may cause a data
overrun condition. The BP may also execute either an
HIO or RIO instruction and stop the I/O operation. After
the second word of an IOCD is fetched and providing no
"unusual end" condition was detected, the 10CD is executed
as prescribed by the parameters contained therein. As a
function of the order and the status of the Skip flag, if
applicable, an 10CD may be executed in one of five ways,
as described below:
1.

132

Certain Control orders (e. g., Stop) may be executed
by the device while the lOP monitors the operation in
accordance with the applicable control flogs. Since
no memory accesses and data (or information) transfers
occur, the contents of the memory byte address register, write key register, and byte count register may
be ignored. Other Control orders (e. g., Rewind for a
magnetic tape unit) are listed and described in applicable Xerox peripheral equipment reference manuals.

I/O Operation Phases

Note: Within the context of the above explanation,
the Control order is defined to be one that
does not transfer any information; thus, data
chaining is precluded within the 10CD containing the Control order; however, command
chaining may be specified. Control orders that
involve information transfers when executed
are described below (see paragraphs 2 and 4).
2.

If the order specifies an input operation (e. g., Read,
Read Backward, or Sense) and the Skip flag is coded
as a 0, all parameters of the current 10CD may be
applicable. As a result of receiving an appropriate
input order, the devi ce transmi ts data (Read, or Read
Backward order) or information from special registers
(Sense order) into data buffers of the associated I/O
subchannel within the lOP.
Depending upon the priority that prevai Is for accessing
main memory, the lOP accesses a memory word location
{as specified by the current memory byte address},
transfers up to four bytes of data or informati on from
the data buffers to a memory unit, provides a write
key, and increments (or decrements, if Read Backward
order) the memory byte address and decrements the
byte count by one for each byte transferred out of the
data buffers.
The write key is evaluated against the preassigned
write lock for the memory word location accessed.
If the write key is valid for each memory word location accessed, the input operation continues, as described above, unti I it is completed or terminated
by an "unusual end" condition; other than Write Lock
Violation. If the write key is not valid, the memory
unit (1) generates and transmits a Write lock Violation (WlV) signal to the lOP, (2) rejects the new data,
and (3) does not disturb the previous contents of the
memory word location accessed.

If the write key is invalid for any memory word location
accessed and the HTE flag is coded as a 1, the input
operation is terminated immediately upon receipt of a
WlV signal (see "Termination Phase ll ) .
If the HTE flag is coded as a 0, the memory unit may
accept or reiect the date or infermation, based on the

write key/write lock evaluation for each memory word
location accessed, without affecting the operations
within the lOP, device controller, or device. The
input operation continues unti I either completed or
terminated by an "unusual end" condition, other than
a Write lock Violation.

Note: Since the same write key prevai Is for the entire
lOCO and all memory locations within a memory page are assigned the same write lock, the
write key/write lock relationship may change
when the memory byte address is incremented
{or decremented} across a memory page boundary.
3.

If the order specifies an input operation {e. g., Read,
Read Backward, or Sense} and the Skip flag is coded
as a 1, all parameters within. the 10CD, except the
write key, may be applicable. As a result of receiving
an appropriate input order, the device transmits data
{Read or Read Backward order} or information from
special registers (Sense order) into the,data buffers
within the I/o subchannel of the lOP. - Because the
Skip flag is coded as a 1, the lOP can not access main
memory (the write key may be ignored and a Write Lock
Violation can not occur). Although the data can not
be stored in the main memory, the lOP increments the
memory byte address (except during a Read Backward
order, when it is decremented) and decrements the byte
count by one for each byte transferred out of the data
buffers. The devi ce may continue to transmit data into
the data buffers and the lOP may continue to update
the memory byte address and byte count unti I the current order is either completed in a normal manner or
terminated because of an "unusual end" condition
(other than a Write Lock Violation).
If the order specifies an output operation (e. g., Write
or Control) and if the Skip flag is coded as a 0, all
parameters within the lOCO, except the write key,
may be applicable. When transferring data (Write
order) or information (Control order) out of main
mem~ry, the write key/write lock checking is not
performed; hence, the write key may be ignored.
Likewise, a Write Lock Violation will not occur. For
an output operation, the lOP wi II access main memory
{in accordance with the priority that prevai Is for accessing main memory} and transfer up to four bytes of
data (or information), as specified by the current memory byte address, to the data buffers of the appropriate
I/O subchannel. The lOP also increments the memory
byte address and decrements the byte count by one for
each byte of data transferred. Data is then transferred
from the data buffers to the devi ceo The lOP may continue to access main memory, transfer up to four bytes
of data from main memory to the appropriate data buffers, and update the memory byte address and byte
count. The device continues to output ·data unti I the
order is either completed in a normal manner or terminated because of an "unusual end" condition.

If the order specifies an output operation (e. g., Write
or Control) and if the Skip flag is coded as a 1, all
parameters within the current lOCO, except the write
key, may be applicable. Because the Skip flag is
coded as a 1, the lOP can not access main memory for
any data (or information). Instead, the lOP generates
and loads zeros (XIOOI) into the data buffers of the
appropriate I/o subchannel and increments the memory
byte address and decrements the byte count by one for

each byte loaded. The zeros are then transferred from
the data buffer to the device. The lOP may continue
to generate and load zeros· into the data buffers and
update the memory byte address and byte count, accordingly, and the device may continue to output zeros
unti I the order is either completed in a normal manner
or terminated because of an "unusual end" condition.

DATA CHAINING
An order may be continued from the current operational
lOCO to the next operational lOCO, if data chaining is
specified in the current lOCO. In this case, the lOP wi II
automatically fetch the next operational lOCO, asdescribed
under "Fetching Phase", when the byte count of the current
lOCO is reduced to zero. In the process of fetching the
next operational lOCO, the lOP may fetch and execute a
control lOCO containing a Transfer in Channel command
without affecting the continuity of the order. The process
of fetching and loading the next operational lOCO into the
control registers of the I/O subchannel is transparent to the
device. That is, the device continues to operate as if the
order were defined by a single lOCO. Also, any changes
in the status of the Skip flag or in the write key from one
lOCO to the next is transparent to the device. The device
continues to receive zeros, data, or information from the
data buffers during an output operation, or continues to
transmit data (or information) into the data buffers regardless
of whether it is subsequently rejected or stored whi Ie performing an input operation.
During the execution phase, an I/o interrupt may be re.such time th~ byt~ c~~:";~ cf ~!j cpe:-~t:c~c! !OCD
is reduced to zero if the Interrupt at Zero Byte Count (IZC)
flag is coded as a 1. Thus, if data chaining is speCified,
the lOP may request an I/O interrupt without interfering
with the process of fetching the next operational lOCO.
quc5~cd

If the I/o interrupt level (location X' 5C') within the interrupt system is armed, enabled, and not inhibited, the I/O
interrupt may be processed by the BP in accordance with
the priority that prevai Is within the interrupt system, the
lOPs, and the device controllers connected to the lOP.
The order may be completed in a normal manner when the
Data Chain flag of the current lOCO (the last 10CD of a
logical record) is coded as a O.

COMMAND CHAINING
An I/o operation may be continued from the current lOCO
to the next IOCD if command chaining is specified in the
current IOCD. Command chaining is commonly specified
when reading (or writing) consecutive records of data from
the same fi Ie. In which case, the current IOCD must be
the last IOCD for the current record and the next 10CD
must be the first lOCO of the next logical record. Although
the device may execute the same functional order for both
records, logically, it is equivalent to two separate orders.

I/o Operation Phases

133

Depending upon the characteristics of the device, command
chaining may also be used to perform different operations
on either different but consecutive records or upon the same
record (e. g., a magnetic tape unit may be programmed to
alternately read or write consecutive records or to read the
same record backwards after writing). Refer to an appropriate Xerox peripheral equipment reference manual for
further detai Is.
If command chaining is specified, the device controller
causes the lOP to fetch the next operational lOCO, as described under "Fetching Phase ll , when the device signals
"channel end" {signifying that it is ready to accept and
execute another order}. In the process of fetching the next
operational lOCO, the lOP may fetch and execute a control lOCO containing a Transfer in Channel command without affecting the continuity of the I/O operation {i. e. ,
transparent to the device controller/device}; however, the
fetching of the next operational lOCO is not transparent
to the device controller/device. The process of automatically fetching the next operational lOCO because data
chaining and/or command chaining is specified in the current lOCO permits an I/O operation to continue normally
unti I an lOCO is executed in which both chaining flags
are coded as zeros (the last lOCO of the last record).

If data chaining and command chaining are both specified
within an lOCO, data chaining is performed if the byte
count of the current lOCO is reduced to zero before the
device generates "channel end"; command chaining is performed if the device generates "channel end" before the
byte count is reduced to zero.
During the execution phase, an I/O interrupt may also be
requested each time a "channel end ll occurs if the Interrupt
at Channel End (ICE) flag is coded as a 1. Thus, if command chaining is specified, the lOP may request an I/O
interrupt without interfering with the process of fetching
the next operational lOCO.

TERMINATION

P~ASE

Completed as specified by the command list.

Aborted whenever a SUPER RESET, SYSTEM RESET,
or I/O RESET command is entered from the System Control Console (SCC).

The progress of an 1/0 operation, including the termination,
may be ascertained by evaluating the status information
returned for I/O instructions, as described in Chapter 3.
Depending upon programming considerations, these I/O
instructions may be executed either singly or as part of an
I/O handling routine and either imperatively at logical
poi nts of a BP-executed program or on a,n II as needed ll
basis when an I/O interrupt is requested by an lOP or device controller. Normally, an I/O interrupt is requested
whenever a critical or significant event occurs within any
I/o subchannel, device controller, or device. Typically,
an I/O interrupt may be requested when the byte count of
any lOCO is reduced to zero, whenever any device detects
a "channel end" condition, or when the lOP or any device
controller detects an "unusual end" condition, providing
the appropriate control flag {IZC, ICE, and IUE} is coded
as a 1.
Note: An I/O interrupt may also be requested by certain
devices, e. g., a magnetic tape unit may be able
to execute a Rewi nd and Interrupt order and other
devices may request an I/O interrupt when executing a Stop order in which bit 0 is coded as a 1.
Refer to an appropriate Xerox peripheral reference
manual for further detai Is.
Once an I/O interrupt request has been made by a device,
that device, device controller, and I/O subchannel remain
in an interrupt pending condition unti I the interrupt request
is acknowledged, reset, or cleared.
Normally, an I/O interrupt request is acknowledged by
the BP executing an AIO instruction, as part of an I/O
interrupt-handli ng routine; reset by the BP executing either
an HIO or an RIO instruction; or for certain devices cleared
automatically, as a function of time. Refer to an appropriate Xerox periphera! equipment reference manuel

fCi

further detai Is. )
An I/O operation maybe terminated in one of the following
manners:

Aborted at any time because the BP executed either
an HIO or RIO instruction.

Aborted when an unconditional "unusual end ll condition
was detected.

Aborted when a conditional "unusual end" condition
was detected whi Ie the HTE control flag was coded
os c 1.

134

Completed as specified by the command list but with
an "unusual end" condition.

I/O Operation Phases

Since a multiple number of I/O interrupt requests may prevail simultaneously {one per each device controller} and
all requests are serviced by a common I/O interrupt level
(location X' 5C'), the BP normally acknowledges an I/O
interrupt request based on the priority that prevai Is within
the interrupt system, the lOPs, and the I/O subchannels
within an MIOP, if applicable. An interrupt pending condition prevents a new I/O operation from being initiated
by an SIO instruction on a particular subchannel but does
not affect the current I/O operation. (That is, if an I/O
intellupt was requested as the resuit of a zero byte count or
"channel end" condition, and datt" chaining or command
chaining is specified, the I/O operation may continue as
specified by the command list.)

5. OPERATIONAL CONTROL
EXTERNAL CONTROL SUBSYSTEM
The External Control Subsystem (ECS)isa group of elements
used in this computer system that provide operational and
diagnostic interfaces to control and maintain system hardware and software.

CENTRALIZED SYSTEM CONTROL
In many other computer systems II software-level II operator
interactions are transacted through an operator's teletypewriter console whi Ie hardware level interactions are performed through a fixed panel of lamps and switches. In
contrast, this Xerox computer system consolidates these interactions and controls into a console telecommunications
device, designated as the System Control Console (SCC).
Through the SCC, the operator has a single control point
for all normal system control activities.
A Remote Diagnostic Interface (RDI) permits the local
System Control Consol e to be augmented wi th a Remote
Console that may have the same degree of system control. (Usage of the RDI and Remote Console as a Remote
Assist feature is described below, under II Remote Console".)
A System Control Panel (SCP) contains indicators and basic
controls that the operator may use during system startup or
to establ ish connections with the remote location.

CONTROL CONSOLE DEVICES
The ECS provides an interface for two local (primary and
alternate) communications consoles and a data set interface for remote diagnostic connection. Each communications console must have an EIA RS232 voltage interface
and format characters in even parity ASCII code with control protocols of a Model 4691 KSR 35 Keyboard/Printer.
Allowed communications rates are 10 and 30 characters per
second.

PRIMARY CONSOLE
The primary console always has the functional capability of
the System Control Console to communicate with software
through I/O subchannel address X'Ol'. The communications
rate of the primary console is either 120 characters per
second or the same as the alternate and remote consoles
depending on the setting of the FSELA switch on the Configuration Control Panel (see Chapter 6). If the REMOTE
CHANNEL switch on the System Control Panel is in the
SCC position (implying a remote diagnostic connection),
the remote channel frequency is automatically enforced on
the primary console.

REMOTE CHANNEL
The alternate and remote consoles share the same data paths.
Both consoles receive the same output; either one of the
consoles is selected for input by the ALTSEL switch on the
Configuration Control Panel. The communications rates
of 10 or 30 characters per second are selected for both consoles by the FSELBO and FSELB 1 switches on the Configuration Control Panel. Both consoles may function either
strictly as I/O devices or as parallel System Control Consoles selected by the REMOTE CHANNEL switch on the
System Control Panel. Description of communications rate
selection is found in Chapter 6.

ALTERNATE CONSOLE
The alternate console normally functions as an output device residing at I/O subchannel address X'OB'. This console can create an edited system log, while the operator's
c'onsole functions at a higher communications rate. (REMOTE CHANNEL and ALTSEL switches are both OFF.)

If the primary console fails, the alternate console may
function as the System Control Console. In this case, the
remote console connection is only inhibited by the operator at the data set. (REMOTE CHANNEL switch in
SCC position; ALTSEL switch in ON position.)

Before the remote device can gain access to the Remote
Diagnostic Interface (RDI), the operator must manually intervene to establish the connection at the data set and the
System Control Panel. The data set (Bell 103A or equivalent) connection is inhibited while the REMOTE CHANNEL
switch is in the OFF position.
The remote console may run on-line diagnostics while the
rest of the system performs non-maintenance work. In this
case, the remote console preempts I/O subchannel X'OB'
and the alternate (local) console creates a log of the online mainentance if not turned off. The remote device
does not have access to the SCC hardware controls, but
may enter software-level control information through the
I/O system (REMOTE CHANNEL switch in I/o position,
ALTSEL switch in OFF position).

If the entire system is under the discretionary control of remote maintenance personnel, the operator may connect the
remote console to the RDI as the System Control Console.
The remote console is then connected logically in parallel,
and assumes all the functional capability of the primary console, and shares I/O subchannel X'Oll. (Note that conventions must be established to ensure that the primary and
remote consoles do not generate overlapping input.) The
remote console communications rate is automatically imposed on the primary console and the operator may have to

Operational Control

135

change the rate on the primary console to retain parallel
control. The alternate {local) device creates a log of all
SCC transactions. The normal (log) output on I/O subchannel X'OB' is suspended for the duration of the SCC
assignment to the remote channel (REMOTE CHANNEL
switch in SCC position; ALTSEL switch in OFF position).

A typical command sequence is to enter "zc HLP' from the
SCC. The system responds by printing" (HLT)" on the next
line of the SCC printout, and forcing the system to halt
instruction execution and enter the IDLE state. If a command cannot be executed due to improper syntax or context,
the system provides an advisory message following the command echo indicating the probable source of error. A typical example of the display format is "(RSY) *EVENT A 1*",
indicating that a reset command may not be executed prior
to halting instruction execution. (Refer to Table 21 for
a complete listing of event messages.)

CONTROL COMMANDS
A set of commands and display formats implements operator
communication with hardware through the System Control
Console. These hardware-control commands, called" SCC
Functions", are independent, direct hardware controls as
distinguished from the software-level operating controls
activated from the SCC through the normal I/o system. A
special micro-processor, working independently of the
BP, senses and controls the execution of SCC functions.
The flexibility of character-oriented communications equipment and micro-programmed control significantly enhance
many system operating and diagnostic features.

The various control functions that may be exercised from
the SCC may be generally classified into three categories:
operator control commands, diagnostic control commands,
and maintenance control commands.

OPERATOR CONTROL COMMANDS
These commands provide controls which an operator normally
uses to control the computer system. By entering the appropriate command the operator may direct the computer system
to load, run, halt, reset, read/set the sense switches, or
issue a "console interrupt" to the operating software.

The basic command format provides a four-level interlock
on critical system controls by requiring a correct fourcharacter sequence to initiate a command action. In addition, context analysis is provided to assure that commands are executed only in appropriate system states. This
basic format requires that each command is preceded by the
"control-Z" character (control and Z keys depressed simultaneously). Note that within this text, the control-Z character is represented with the symbol "Zc".

Table 21.

136

The sense switch control and console interrupt commands
may interact with the software and are always operative.
All other SCC functions may be enabled or disabled by
the SCC FUNCTIONS switch on the SCPo

Event Messages

Display

Significance

*EVENT 00*

System Initialization; POWER ON or SUPER RESET.

*EVENT AO*

c
Improper syntax for Z format command.

*EVENT Al*

Command not executed; Improper syntax or system may not be in IDLE mode.

*EVENT A2*

Command not executed; system not in maintenance mode.

*EVENT M*

Command not executed; SCC FUNCTION switch is in DISABLE position.

*EVENT A8*

Power ride through; recoverable power line failure detected; power on trap requested.

*EVENT FO*

Trap requested occurred; inhibited in P-Mode.

*EVENT Fl*

Basic processor error halt; watchdog timeout reset issued when watchdog timeout alarm bit
set. (See" Processor Control Word".)

*EVENT F4*

Basic processor halt; Address Halt.

*EVENT F6*

Basic processor halt; Processor-Detected Fault (PDF).

*EVENT F9*

System fai led micro-diagnostic test (followed by Single Clock Status Register display of the
element that failed).

Control Commands

To prevent inadvertent activation from disrupting a running
system, the SCC FUNCTIONS switch is placed in the
DISABLE positi on.
The following operator control commands are standard features of th i s system:
Input

Display

Name of Command

Zc I

(I)

Operator's Console
Interrupt

ZC SSW

(SSW=bbbb)

Read Sense Switches

ZC ss#t

(Ss#t =bbbb)

Set Sense Swi tches

ZC LDN####t,tt,ttt (LDN@####t)

Load Normal

ZC RSytt, ttt

(RSY)

Reset System

Ze RBp tt, ttt

(RBP)

Reset Basic Processor

ZC RIOtt , ttt

(RIO)

Reset I/O System

ZC HLTtt

(HLT)

System Halt

ZC RUN tt , ttt

(RUN)

System Run

The Operator's Console (or SCC) INTERRUPT command permits the operator to interact with the executing software by
setting interrupt level X ' 50 ' . If this interrupt level is Armed
I

....... I T r - n n l l n T

11"1 1i:l\l\vr I

CQfTIUlUrlU

___I

I~ t:lnt::I~,

1.1 __

- __

The sense switches may also be set by executing a WRITE
DIRECT instruction (see Chapter 3). The sense switches
are initialized to zero during the power on and SUPER
RESET sequences. While the ZcSS# command is active,
the basic processor is momentarily put in the IDLE state.
This prevents any conflict between the operator command
and a WRITE DIRECT instruction.

LOAD NORMAL

The loading operation is normally accomplished by readying
the load device and entering the LOAD NORMAL command
from the System Control Console. The four hexadecimal
digits (represented as ####) specify the load device address.
Successful completion of the command is signified by the
command echo II{LDN@####)II. A failure in the load
sequence is indicated by a display of an appropriate error
message (see Table F- ) following the command echo. The
LOAD NORMAL command is accepted only when the
system is in the IDLE state.

L _ _ _ . . . _L

lilt:: 1I1It::IIUI-'I

level is advanced to the Waiting state. If the interrupt
level is already in the Active state or Disarmed, the INTERRUPT command has no effect upon the computer system. This
command is always enabled.

This single command initiates the following sequence:

A series of internal micro-diagnostic tests are conducted to verify the operati on of system paths and
elements used in the loading sequence. Each test is
preceded by a system reset. If a failure is detected
during the micro-diagnostic tests, an error message
II *EVENT F9*" is generated and followed by a Single
Clock Status Register display identifying the failing
element.

Upon completion of all micro-diagnostic tests, a system reset is issued.

All system memory locations are initialized to zero.

The basic processor loads a self-diagnostic program in
memory locations X ' l00 ' through X ' 1FF ' and loads the
bootstrap loader (see Figure 14) in memory locations
X'20 ' through X'29 1 • If an error is detected during the
process, an error message "*EVENT FO*", is generated.

The system is placed in the RUN mode.

The basic processor executes the self-diagnostic progr,am, beginning at location X'l60 ' • The processor
then executes the bootstrap loader, starting at location
X'26 1 • If a failure occurs during the processor selfdiagnostic program, the processor enters the WAIT state.

READ SENSE SWITCHES
This command causes the status of the sense switches to be
displayed as part of the command echo. For example, if all
four sense switches were set to a 1, the console display
would be II (SSW=llll)". The status of the sense switches
is also displayed by indicators on the System Control Panel.
The READ SENSE SWITCHES command is always enabled.
The status of the sense switches may also be read by executing a READ DIRECT instruction (see Chapter 3).

tHexadecimal digits.
ttscc FUNCTIONS switch of SCP must be in the ENABLE
position.
ttt System must be in the ID LE state.

SET SENSE SWITCHES

This command causes the sense switches to be set to the
value specified by the hexadecimal digit in the command
(#). The new sense switch value is displayed as part of
the command echo. For example, if the operator enters
uZcSS3" the SCC will print II (SS3=O0l1)". The new status
is also displayed by indicators on the System Control
Panel. The SET SENSE SWITCHES command is always
operative.

Zct.ON####

OPERATOR'S CONSOLE INTERRUPT

wnen rne

zCSsn

Control Commands

137

Location
(hex) (dec)

Hexadecimal

020000A8

oEOOO058

22110029

L1, 1

64100023

BDR,l

68000028

BCR,O

OOOO####t

22000010

L1,O

CCOOO025

SIO,O

*37

CDOOO025

no,o

*37

69COO022

BCS,12

Symbolic form
of instruction

RESET SYSTEM
The RESET SYSTEM command performs the combined functions of the RESET BASIC PROCESSOR and RESET I/O SYSTEM commands, as well as the function described below:
1.

The system control processor bus interface is initialized.

The processor memory bus and processor bus interfaces
are initialized.

The system memory units are initialized. This process
does not alter any memory locations.

All interrupt levels are reset to the Disarmed and Disabled state.

The system ALARM indicator is cleared.

This command is accepted only when the system is in the
IDLE state.

zCRBP
t#### represents four hexadecimal digits that specify
the load device address as entered by the LOAD
NORMAL command.

The RESET BASIC PROCESSOR command initial izes the basic
processor by performing the following:

All bits in the Program Status Words, except the instruction address, are reset.

The program counter of the BP (register 05) is set to a
value of X'26'.

The BP remains in the IDLE state unti J allowed to begin execution at location X'26'.

Figure 14. Bootstrap Loader

Execution of the bootstrap program causes the following
actions:

The first record on the selected peripheral is read into
memrory locations X'2A' through X'3F' (the previous
contents of general register 0 are destroyed as a result of executing the bootstrap program in locations
X'26' through X'29').

This command is accepted only when the system is in the
IDLE state.
Since all memory requests are inhibited during a reset, the
RESET BASIC PROCESSOR command disrupts any simultaneous memory request from the standard I/o system.

After the record has been read, the next instruction
IS taken from iocation X'2A' (provided that no error
condition has been detected by the device or the
(lOP).

When the instruction in location X'2A' is executed,
the unit device and device controller selected for the
load operation can accept a new SIO instruction.

Further I/o operations from the load unit may be accomplished by coding subsequent I/O instructions to
indirectly address location X'25 1 •

RESET I/O SYSTEM
When accepted, the RESET I/O SYSTEM command initializes the lOPs and device controllers of the standard I/O
system. All peripheral devices under control of the system
are reset to the "ready" condition and all status, interrupt,
and control indicators in the I/O system are reset. This
command is accepted only when the system is in the IDLE
state. The RESET I/O SYSTEM command does not affect
the External Direct Input/Output (010), the BP, or other
non-input/output system elements.

zcttL T
Following the successful completion of the load sequence,
the computer system usually continues execution of the
loaded program and begins issuing messages to the operator
via the I/O system to the System Control Console.

138

Control Commands

RESET BASIC PROCESSOR

SYSTEM HALT

When the HALT command is entered, the BP ceases to
execute instructions and is forced into the IDLE state; the
RUN indicator on the System Control Panel is extinguished

and the IDLE indicator is illuminated. In the IDLE state
the load commands, the reset commands, and the RUN command are enabled. The I/O system may continue to perform
I/o operations initiated prior to the ZCHLT command, even
though the BP is halted. Note that the processor HALT
status is not set by the ZCHLT command, but is CalJsed by
internal processor conditions (see" Processor-Control Word").

represents the data in the location specified in the II All
field (eight hexadecimal digits). The first hexadecimal
digit of the A field is XIOI for memory addresses and X I8 1
for internal register addresses. All valid commands, except
EXIT P-MODE, produce a display in this format.

The allowed diagnostic command set is listed in Table 22.
An example of the resulting printout is shown in the section
entitled .rOperating Procedures and Information".

ZCftUN

SYSTEM RUN

The RUN command is accepted only if the BP is in the
IDLE state. When the FUN command is accepted, the BP
is allowed to execute its instruction stream. 'On the SCP,
the IDLE indicator is extinguished and the RUN indicator
is illuminated, subject to the processor control word and
system status.
When not in the IDLE state, the system does not accept any
of the load and reset control commands. Attempti ng to enter
any load and reset control command while the system is in
the RUN mode results in an error message being displayed
on the control console (see Table F- ).

ENTER P-MODE

The ENTER P-MODE control command is generated by depressing the CONTROL and P keys, simultaneously (pc).
The system is forced into the ID LE state and the processor
wi II execute di agnostic control commands entered from the
System Control Console. The ECS remains in the P-Mode
until an EXIT P-MODE command (described below) is
entered or the ZC format commands SYSTEM RUN or LOAD
NORMAL are entered. Successful entry into the P-Mode
is indicated by a P-Mode display on the SCC.

(P-Mode)
SELECT INTERNAL REGISTER ADDRESSING

(P-Mode)
/

DIAGNOSTIC CONTROL COMMANDS
Diagnostic control commands facilitate isolating software
and hardware problems by providing single-instruction ex.11 ___ - .. ________
eCUTlon, as well as petmlffll'9 It:\JU/ WIIIC u\.O\.Oc:):) IV "IUIlY
processor internal control registers and system memory locations. To perform diagnostic commands, BP instruction
execution must be interrupted and the ECS control mode
altered. This is accomplished by the ENTER P-MODE command (a "CONTROL-P" character generated by depressing
CONTROL and P keys simultaneously). Once in P-Mode
the system is forced into the IDLE state and the BP stores
and fetches data or executes single instructions only upon
request from the operator through the SCC.
...

...., _

These commands specify the storage element whose contents are to be displayed and operated upon with subsequent
_ ~I

_ _ _ ...

Note: Within this text the control-P character is repre- - sented by the following symbol, PC.
The diagnostic control (P-Mode) command format differs
from the basic command format. Hexadecimal digits are
immediately echoed and stored to be used as data or address depending on the following command. The system
truncates the data stream to eight hexadecimal digits and
assumes leading zeros if less than eight characters are entered. All non-hexadecimal characters, except basic (ZC)
format commands, are treated as P-Mode commands. If the
character is not in the allowed command set, it is echoed
followed by a question mark liN?" and no action results.
Valid commands are echoed; the requested operation is
then performed and a P-Mode data display of the form
"P:DDDDDDDD @ AAAAAAAA" is generated on the next
line of SCC printout. The II plI represents the processor address (normally 0); the II D" field (eight hexadecimal digits)

SELECT MEMORY ADDRESSING

~ornnlUllU;).

T'I _
lilt::

.. /11
/

1___ .. _ I. ___
\.OIIUIU\.OIt::1

r _ II _ . ,-.__ .
IUIIVWII'9

_.
U

L ____ .J __ - ____ I
IIC.II.UUCll..III1UI

data stream speci fi es a memory address; the ". II character
specifies an internal processor control register address. All
address calculations and memory accesses are subject to
the write lock keys, address mode, and mapping bits in the
program status words.

(P-Mode)

ADD TO- SELECTED LOCATION

The "+" character, following a hexadecimal data stream,
causes the value of the data to be added to the contents of
the selected storage element.

(P-Mode)
SUBTRACT FROM SELECTED LOCATION
The II_II character, followi ng a hexadecimal data stream,
causes the value of the data to be subtracted from the
contents of the selected storage element.

(P-Mode)
M

STORE IN SELECTED LOCATION

The" Mil character, following a hexadecimal data stream,
causes the data to be stored in the selected storage element.

Control Commands

139

Table 22. Diagnostic Control (P-Mode) Commands
Character

Function
ENTER P-MODE.

#### ••• ##

Iihut data or address value (context determined by the succeeding operator.
# ## ••• ## is any hex digit string).
SELECT INTERNAL REGISTER ADDRESSING.

SELECT MEMORY ADDRESSING.

ADD TO SELECTED LOCATION.
SUBTRACT FROM SELECTED .LOCATION.

STORE IN SELECTED LOCATION.

SHIFT LEFT AND DISPLAY.

SHIFT RIGHT AND DISPLAY.
INCREMENT REFERENCED ADDRESS AND DISPLAY.

RUBOUT

DISPLAY ADDRESSED LOCATION.

INSTRUCTION SINGLE STEP.

SPECIAL INSTRUCTION SINGLE STEP.

EXIT P-MODE.

(P-Mode)
L

SHIFT LEFT AND DISPLAY

This command causes an image of the contents of the presently selected memory location or Q register to be shifted
one bit position to the left and then displayed. A zero is
entered into the least significant bit of the location for
each L command.
Actual contents of the memory or Q-register location referenced b,' the shift iiistiuction

(P-Mode)
R

QiS

not altsred.

SHIFT RIGHT AND DISPLAY

This command causes an image of the contents of the presently selected memory location or Q register to be shifted
one bit position to the right and then displayed. A zero is
entered into the most significant bit of the memory location
or Q register for each R command executed.
Actual contents of the memory or Q register location referenced by the shift instruction are not altered.

previously executed SELECT MEMORY ADDRESSING or
SELECT INTERNAL REGISTER ADDRESSING control command). The new address and contents are displayed on the
next line.
(P-Mode)
RUB OUT

DISPLAY ADDRESSED LOCATION

This command displays the contents of the currently addressed memory location or Q register (as specified by
a previously executed SELECT MEMORY ADDRESSING
or SELECT INTERNAL REGISTER ADDRESSING control
command).
(P-Mode)
S

INSTRUCTION SINGLE STEP

This command causes the BP to execute a single instruction as pointed to by the current contents of the program
counter. Execution is precisely the same as if the system
were running continuously. Upon completion, the BP
returns to the IDLE state. If a trap occurs whi Ie the instruction is being executed, the instruction in the trap location

(P-Mode)
I

INCREMENT REFERENCED ADDRESS AND
DISPLAY

This command increments by +1 the address of the currently
selected memory location or Q register (as specified by a

140

Control Commands

is executed before the BP returns to the IDLE state. The
resultant display shows the next instruction to be executed.
Condition codes resulting from the instruction execution
are displayed as the second hexadecimal digit of the address field.

(P-Mode)
G

This command permits the contents of register Q5 to be interpreted as the current instruction, and execution by the
BP proceeds as described for the INSTRUCTION SINGLE
STEP command. The program counter is incremented by +1.
This command thus allows any single instruction (contained
in register Q5) to be executed in lieu of the instruction
pointed to by the program counter without otherwise disturbing conditions within the system. The resultant display
shows the next instruction to be executed.
Condition codes resulting from the instruction execution
are displayed as the second hexadecimal digit of the address field.
(P-Mode)

Input

Display

Name of Command

ZC MM2

(MIV\2)

SET/CLEAR CLUSTER
DISPLAY MODE

ZC MM3

(MM3)

SET/CLEAR P-MODE REPEAT
MODE

Zc MM4tt

(MM echo SUPER RESET
interrupted)

Zc MM5 tt

(MMS)

SET MICRO-DIAGNOSTIC
LOOP MODE

Zc MM6tt

(MM6)

INITIATE ELEMENT MICRODIAGNOSTIC

ZcMMlt

(MM7)

SET LOW CLOCK MARGINS

Zc MM8tt

(MM8)

SET HIGH CLOCK MARGINS

Zc MM9 tt

(MM9)

SET MEMORY INTERLEAVE
OVERRIDE

ZcMMAtt

(MM echo SET DISPLAY INHIBIT MODE
interrupted)

ZCCLKtt

(CLK)

SET SINGLE CLOCK MODE

Ispace l

SINGLE-CLOCK STEP

ZCc##t

(C##)

MUL TIPLE-CLOCK STEP

ZC KIL

(KIL)

CLEAR SINGLE CLOCK
MOuE

Zc E##

(E##)

SELECT/DISPLAY SINGLE
CLOCK STATUS REGISTER

ZC T

(T)

SET/CLEAR TRANSPARENT
TEXT MODE

SPECIAL INSTRUCTION SINGLE STEP

EXIT P-MOD E

The EXIT P-MODE command terminates the P-Mode within
the ECS. The BP resumes execution of instructions. If
no SYSTEM RUN or LOAD NORMAL commands were in effect before entering the P-Mode, the system remains in the
IDLE state.

Ispace l

MAINTENANCE CONTROL COMMANDS
Maintenance control commands facilitate isolation and
analysis of system hardware malfunctions. The commands
are accepted only if the SCC FUNCTIONS switch is in the
ENABLE position. In addition, most critical maintenance
controls can be activated only if the MAINT MODE switch
on the SCP is in the ON position.
The primary features of the maintenance control commands
are the provision of system clock control and single clock
status displays. Status is obtained from read-only registers
located in central system elements. These Single Clock Status Registers (SCSR) monitor the state of internal hardware
signals. Each SCSR display is printed on the next line of
SCC printout in the format "CE:DDDDDDDD CC". The "CE"
field contains two hexadecimal digits that represent a cluster
and an element address, respectively. The 8-digit D field
displays the contents of the register, and the 2-digit CCII
field is a modulo 256 clock step counter. This information
is valid only when the system clock is stopped.
II

The following maintenance control commands are included
as standard features of this computer system:

ZC LDS #### (LDS@####) LOAD SPECIAL
ZC LDT

(LDT)

MEMORY SET

SET SINGLE CLOCK MODE
This command sets the computer system to the II Single Clock
Mode" by simultaneously stopping all central system clocks,
except those required by the External Control Subsystem
and the I/O system. When the system is in the Single
Clock Mode all control commands may be entered and executed. Operations performed in the Single Clock Mode
may differ from those performed when the clock is running

Display

Name of Command

ZC f.N.AO

(MMO)

CLEAR MM FEATURES

tAil clock controls are inhibited unless the MAINT MODE
switch is in the ON position.

Zc MM1 t

(MM1)

SET/CLEAR REPEAT CLOCKING MODE

ttThese commands are accepted only if the system is in the
MAINT MODE.

Control Commands

141

at its normal rate (e. g., fixed duration control sequences
may not take effect and diagnostic control commands which
operate upon BP's registers or memory locations require a large
number of clock steps to complete the operation). The RESET
SYSTEM, RESET I/o, and RESET BASIC PROCESSOR commands
are effective in Single Clock Mode. When the SingleClock
Mode is set, the contents of the currently selected Single
Clock Status Register are displayed (see SELECT/DISPLAY
SINGLE CLOCK STATUS REGISTER, ZCE## command).

If the computer system is currently in the Single Clock
Mode, ZCCLK command resets the two-digit clock step
counter to X'OO'.
The Single Clock Mode may be reset by either a CLEAR
SINGLE CLOCK MODE, ZCKIL, command or a SUPER
RESET, Z CMM4, command.
Note:

Entering a SET SINGLE CLOCK MODE command
when the basic processor is performing normal data processing operations may have an adverse effect upon
I/O operations. To prevent inadvertent entry into
Single Clock Mode, the ZCCLK command is not accepted unless the MAINT MODE switch is in the ON
position. Attempting to enter a ZCCLK command
when the MAINT MODE switch is in the OFF position results in an error message (*EVENT A2*) being
displayed and no further action.

SELECT/DISPLAY SINGLE CLOCK STATUS
REGISTER
This command causes the requested SCSR to be displayed.
The n##n portion of this command (two hexadecimal digits)
is stored within the ECS and used as a reference address in
any command which displays the contents of the currently
selected Single Clock Status Register. The first hexadecimal digit is the cluster address and the second digit is
the element address.
In addition to being modified by subsequent Zc E## commands, the cluster and element addresses may also be
changed by the LOAD NORMAL command and the SET
CLUSTER DISPLAY MODE command. The LOAD NORMAL
command sets the address to X'OO' and the SET CLUSTER
DISPLAY MODE command causes the element address to
be set to a zero following each cluster scan.

Zct 27 2B 29 JO 31

DISPlAY
SflfCT

SINGLf_
ClOCK

",,@

'......

ti:U~@@ l1f1f1fl
•
I

Figure 15. System Control Panel

Control Commands

145

BP STATUS AND NO.
This group of indicators permits the processor address
(usually 0) and current internal state (RUN, WAIT, or
HALT) of the BP to be displayed. While executing instructions, the BP is normally in the RUN or WAIT state.
The HALT state is entered only when an address halt occurs,
the processor disable is on (see II Operating Procedures and
Information U ) or an irrecoverable processor fault occurs.
When the system is in the IDLE state as a result of power
on, a ZCHLT command, or a pC command, only the processor
address is lighted and RUN, WAIT, and HALT indicators
are extinguished.

ALARM AUDIO
This 4-position rotary switch controls the connection and
volume of a loudspeaker, and also permits all indicators
(except POWER ON and PRIMARY POWER) on the SCP to
be tested. When this switch is in the OFF position, the
loudspeaker is disconnected. Note that this switch does
not inhibit the ALARM indicator. When this switch is in
the LOW position, the loudspeaker is connected and the
volume is set to a low level. When this switch is in the
HIGH position, the loudspeaker is connected and the
volume is set to a high level. When this switch is held in
the LAMP TEST position, all back-lighted indicators should
illuminate, simultaneously. The switch returns to the
HIGH position when released.

SCC FUNCTIONS
This switch controls the functional capabilities of the System Control Coosole{s). When this switch is in the ENABLE
position, the SCC device{s) may perform the various control functions attributed to a System Control Console.
Certain control functions require the system to be in the
IDLE state while others (as described under II Maintenance
Control Commands") require the MAINT MODE switch to
be in the ON posi ti on.
When the SCC FUNCTIONS switch is in the DISABLE
position, the controi functions that may be entered from
the control console (to interact with operating software)
are limited to the fol lowing:
1.

Operator requested interrupt (Zc I),

Read Sense Switches (ZcSSW),

Set Sense Switches (ZcSS *).

The operator may lock out potentially disruptive control
commands when the operati ng software is runni ng by setti ng
the SCC FUNCTIONS switch to DISABLE.

REMOTE CHAN NEL
This 3-position rotary switch controls the manner in which
the alternate and remote consoles may operate. When this
switch is in the SCC position, the alternate and remote

i46

Controi Commands

consoles may be connected in parallel with the System
Control Console and may perform the same control functions as the local control device. The remote console also
requires a manual connection through the RD1 data set.
Note that any restri cti ons upon the control func ti ons i mposed upon the local control device by the SCC FUNCTIONS switch being in the DISABLE position also apply
to both consoles. Either the alternate or remote console
is selected for input by the AL TSEL switch on the Configuration Control Panel (see Chapter 6).
When the REMOTE CHANNEL switch is in the OFF position,
the remote device is disconnected from the,ECS at the data
set (if present). The alternate console functions in the I/o
mode.
When this switch is in the I/O position, the alternate and
remote consoles operate strictly as I/O devices communicating with the computer system via lOP subchannel address
X'OB'. Only one device is selected for input at a time by
the ALTSEL switch on the Configuration Control Panel
(see Chapter 6).

MAINT MODE
During normal operations, this switch is placed in the OFF
position. During maintenance and/or diagnostic activies,
this switch may be placed in the ON position or momentaril>, held in the RESET position (switch automatically returns
to the ON position when released). In addition to causing
the MAINTENANCE MODE indicator to become illuminated when placed in the ON position, the switch also enables certain hardware controls and al lows their associated
control commands to be entered from the operator's control
console (see "Maintenance Control Commands"). This
i nterl ocki ng feature prevents inadvertent adverse effects
upon the current program.
Caution should be exercised in activating RESET, since
this position (equivalent to the SCC SUPER RESET command) causes a!! components of the system to be reset and
initialized.

SELECT DISPLAY
These nine switches, labeled CCP/SCSR and 0 through 7,
are used to specify the binary address of anyone of up to
256 Single Clock Status Registers and up to 32 Configuration Status Registers or Read Direct Mode 9 Status Registers whose content is to be displayed by the 32 binary
indicators, labeled 0 through 31.
Wh,:" the CCP/SCSR switch is in the SCSR position,
swi rches 0 through 3 specify the cluster address and
sw~t( :,es 4 through 7 specify the element address of the
Sin9ie Clock Status Register whose content is to be
displayed.

When the CCP/SCSR switch is in the CCP position and
switch 0 is in the 'rOil position, switches 3 through 7
specify the binary address of the cabinet whose Read Direct
Mode 9 Status Register is to be displayed by the 32 panel
indicators.
When the CCP/SCSR switch IS In the CCP position and
switch 0 is in the 11111 position, switches 3 through 7 specify
the binary address of the cabinet whose 16-bit Configuration Status Register is to be displayed by the 16 lower-order
indicators.

SINGLE CLOCK ENABLE
This switch stops all central system clocks in the same
manner as the ZCCLK command. Activating this switch
when the basic processor is performing normal data processing
may have an adverse effect on any active I/O operations.
To prevent inadvertent activation of this control, it is
disabled unless the MAINT MODE switch is in the ON
position.

SINGLE CLOCK STEP
This switch is active only when in Single Clock Mode or
when the Single Clock Enable switch is active. When
active, this switch causes one system clock to be issued
each time it is placed in the STEP position. The new
single clock status, as selected by the MODE and SELECT
switches, may .be monitored via the 32 binary indicators
C~ the Sy!te!!! Cc~t!"c! P(!~e!; ~~ ~:H!:p!(!y ;!: ge~er~ted 0~ thE'
System Control Console by activation of the SCP Single
Clock Step switch.

of the Read operation, neither data chaining nor command
chaining is called for in the 10CD. The Suppress Incorrect
Length (SIL) flag is set to 1 so that an incorrect length indication will not cause a Transmission Error Halt. After the
SIO instruction has been executed, the basic processor executes
a no instruction with the same effective addressas the SIO
instruction. The no instruction is coded to accept only
condition code data from the lOP. The BCS instruction (in
location X'29') will cause a branch to X'22' (a LOAD
IMMEDIATE instruction), if either CC1 or CC2 is set to 1.
Execution of the LOAD IMMEDIATE instruction at X'22'
loads a count of X'10029' into general register 1. The following BDR instruction at location X'23' uses this as a
"delay" count before executing the BCR instruction in location X'24', which unconditionally branches to the no
instruction in location X'28'. In normal operations, CC1 is
reset to 0 and CC2 remai ns set to 1 unti I the device can
accept another SIO instruction. At that time, the next
instruction is taken from location X'2A'.

If a Transmission Error or equipment malfunction is detected
by either the device or the lOP, the lOP instructs the
d,evice to halt and to initiate an II unusual end" interrupt
signal (as specified by appropriate flags in the IOCD, described in Chapter 4). The II unusual end" interrupt will
be ignored since all interrupt levels have been Disarmed
and Disabled by the system reset during the load sequence.
The device wi II not accept another SIO while the interrupt
is pending and the BCS instruction in location X'29' will
continue to branch to location X'22'. The correct operator
action at this point is to repeat the NORMAL LOAD,
ZCLDN####, command. If there is no I/O address recognition of the load unit, the SIO instruction will not cause
any I/O action and CC1 will continue to be set to 1 by the
$iO and no instructions causing the BCS instruction to
branch.

FETCHING and STORING DATA

OPERATING PROCEDURES AND INFORMATION
This section contains reference information which may be
required by either the operator or maintenance/diagnostic
personnel.

LOAD OPERA nON DETAILS
The first executed instruction of the bootstrap program {in
location X'26'} loads general register 0 with the address of
the first I/O command doubleword (IOCD). The I/o address
for the SIO instruction in location X'27' is the 13 low-order
bits of location X'25' {which have been set equal to the load
unit address asa result of the NORMAL LOAD, ZCLDN"",
command}. During execution of the SIO instruction, general register 0 points to locations X'20' and X'21' as the
first IOCD for the selected device. This IOCD contains
an order to the selected peripheral device to read 88 (X'58')
bytes of data into consecutive memory locations beginning
at word location X'2A' (byte location X'A8'). At the end

The following examples illustrate how diagnostic control
(P-Mode) commands may be used to display and alter the
contents of specified memory locations and control registers
within the system. Control commands, as entered from a
keyboard device functioning as the System Control Console, are shown in the first column. The resulting printouts
are shown in the second column. The third column of information is an explanation of the functions performed by
the different control commands.

Input

Printout

Function

O:DDDDDDDD @ 80000000

Enter P-Mode of
operations; contents
of Q register 0 is
normally displayed.

100/

100/
O:DDDDDDDD @ 00000100

Select and display
contents of memory
location X'lOO'.

Control Commands

147

Input

Printout

Function

5M
0: 00000005 @ 00000100

Store X'5' into the
currently selected
memory location.

I
O:DDDDDDDD @ 00000101

Increment address
of currently selected
memory location and
display.

appropriate control i nformati on to perform mai ntenance
or diagnostic functions, such as halting and resetting the
basic processor, setting address hold, and activating various fault detection controls. During normal operations it
should not be necessary to access this word. The contents
of the Processor Control Word are not affected by either
processor or system reset, but are automatically set to zero
(default condition) during power-on sequencing and by
the SUPER RESET command. The bit assignments of the
Processor Control Word (register Q30) are listed and described in Table 23.

Note that all P-Mode accesses are qualified by address mapping bits and Write Lock keys in the Program Status Words.
ADDRESS COMPARE WORD
PROCESSOR CONTROL WORD
The Processor Control Word resides in the processor internal
addressable register, Q30. This register may be loaded with

The Address Compare Word is located in register Q31 and
contains parameters defining the type of comparison and
the desired action {alarm, halt, or none} on detecting an
address compare. (See Table 24.)

Table 23. Bit Assignments and Description, Processor Control Word, Register Q30 (X' 1E')
Bit
Position

Description

Retry Inhibit:

If this bit is a 0, the basic processor will automatically retry the instruction which caused the trap to
location X ' 4C'; if this bit is a 1, the basic processor is inhibited from retrying the instruction which
caused the trap to location X'4C'.
1

Parity Check Inhibit:

If this bit is a 0, parity checking of R register transactions is enabled; if this bit is a 1, parity checking
of R register transactions is inhibited.
2

Watchdog Timer Override:
If this bit is a 0, the watchdog timer is allowed to count; if this bit is a 1, the watchdog timer is inhibited from counting and the machine will not execute the Watchdog Timer Trap.

Watchdog Timer Alarm:

If this bit is a 0, the Watchdog Timer Trap is enabled; if this bit is a 1, the Watchdog Timer Trap is
1III1IUIIC::U.
When a rirneour occurS, (J sy:)rem re:)er is generated and the system wi i i run to timeout
again. This provides a dynamic loop for isolating the cause of the timeout.
~_L~L!L_.J

4-5

Reserved (must be coded as zeros).

Address Hold:

If this bit is a 0, the address hold is disabled; if this bit is a 1, the program counter is inhibited from
counting (incrementing) causing the machine to loop on the selected instruction (i. e., when the machine
is returned to RUN mode, the instruction pointed to by the program counter is executed continuously).

Processor Ha It:

If this bit is a 0, the processor is allowed to run under the control of system and P-Mode controls;
if this bit is a i, the processor is forced into the HALT condition.
8-15

Reserved.

16-31

Load device address.

148

Control Commands

Table 24. Bit Assignments, Address Compare Register Q31 (X11 FI)
Bit
Position
0

6-7
8-31

Status

Significance

Selects mapped address· comparison.

Selects unmapped address comparison.

Selects address comparison during instruction access only.

Selects address comparison for all memory cycles.

Selects comparisons only during memory write cycle.

Selects all memory cycle comparisons.

Selects page comparisons.

Selects word comparisons.

System turns on audible alarm for 220 microseconds each time an Address Compare occurs
(maximum frequency 1KHz).

Address match alarm is disabled.

The processor is forced into the HALT state when an Address Compare occurs.

Address Halt disabled.

Reserved.
Comparison address field.

Control Commands

149

6. SYSTEM CONFIGURATION CONTROL
Pooled resources along with flexible configuration control
provide a high degree of continuous availabi lity. If a
problem occurs in an individual unit of a resource pool,
the system may allow that unit to be isolated with a loss
only in capacity but no loss of functional capability,
assuming there is an additional unit of that type in the
system that can absorb the added load. Specialized units
can be duplicated (with all units being normally used,
where possible) and configuration controls used to divert
the input from one to the other in the event of a failure.

configuration control is designed in a modular manner. As
the system grows, previously unused rows on the panel can
be used (up to the panel's maximum of six), and an additional panel may be added. Two panels represent the maximum configuration for one endbeIl assembly.

Note: The Configuration Control Panel does not contain
- - - operational controls as the System Control Panel
does. The CCP switches are initially positioned
during system configuration and are not normally
repositioned during system operation.

Chapter 2 describes the system organization and Chapter 5
discusses system operational control. This chapter describes the Configuration Control Panel (CCP), which serves
as the principal element for controlling and modifying the
configuration of the system.
CONFIGURATION CONTROL STATUS WORD

CONFIGURATION CONTROL PANEL (CCP)
The CCP provides the capabi lity for enabling and disabling
units in the system. It accomplishes this with centrally
located manual selection switches used for the following
functions:

Establish starting addresses for all memory units in the
system.

Enable or disable memory ports.

Enable or disable individual units and clusters.

Control the power throughout the system.

The Configuration Control Panel is mounted within the endbell assembly at the end of the row of cabinets containing
the chassis assemblies for the MUs, BP, and other system
components. On the outer surface of the endbell assembly
is the System Control Panel (described and illustrated in
Chapter 5). Access is gained to the CCP by opening the
hinged endbell assembly (see Figure 16).

A CCP has six rows of 22 toggle switches and two lamp indicators each. A row may control a memory unit, processor
cluster, or system control processor. (See Figure 17, and
Tables 25 and 26.) The active logic associated with each
row of switches and indicators is located within each processor cluster or memory unit itself. Above each row is a
marker strip that identifies the function of each switch. The

150

System Configuration Control

A program may read settings of the panel switches, type of
unit, and options installed. A READ DIRECT (RD) instruction using the chassis address of the cluster or unit
as an address allows the program to determine the configuration status of a particular processor cluster or memory
unit, for example. (The chassis address assignment represents the chassis' physical location relative to the endbell
assembly.) (See Figure 16.)

The configuration control status of a panel read by the
RD instruction is a 32-bit status word consisting of panel
switch settings and type information. (The RD instruction is described in Chapter 3, "Control Instructions".)
The logic for these program provisions resides in each
unit.

In addition to reading configuration status information
via a READ DIRECT (RD) instruction in a program, the
status information may also be obtained by manual switch
selection on the System Control Panel; the 32-bit status
word is displayed on a bank of lamp indicators. (See
Chapter 5 for a discussion of the System Control Panel
features. )

CONFIGURATION BUS
The configuration bus connects to each processor cluster and
provides a path for the system control processor to select and
read the switch settings on the CCP for the selected unit via
an RD instruction.

System Control Panel (SCP)
Endbell Assembly

Chassis B

Identity Tag

Chassis A

Chassis B

Cabinet 2

Cabinet 1

Cabinet 0

Chassis B

Chassis A

Cabinet 3

Direction of System Expansion - - - -.....
Configuration Control Panel (CCP)
(Viewed from Module Side)

tStarting from the endbell as cabinet number 0, the most significant four bits designate physical cabinet number.
The least significant bit designates the back panel location in the halves of the cabinet.
Figure 16. Chassis Physical Configuration

POWER POWER SYSTEM CLOCK
NNORM ON
SEL
S El

PROCESSOR
ADDRESS I

, - - - - - REAL TIME CLOCK S E L - - - - ,
BP
MIOP
010
ENABLE ENABLE ENABLE

r- FSEL ,
ALTSEL

FSELA

,RTCI,
so
SI

,RTa,
so
SI

,RTC3,
so
SI

,STC-,

MeGOOOOOOOOOOOOOOOOOOOOOO
.----PPORT ENABlE - - - - - ,
POWER POWER SYSTEM CLOCK
NNORM ON
SEL
SEl

MUI

G ~

•

.-STARTING ADDRESS - - - - - - ,
INTLV

S12

SI3

SI.ol

SI5

SI6

SI7

SI8

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0·0 0 0

Indicator
Switch

Figure 17. Sample Rows of CCP Switches

Configuration Control Panel (CCP)

151

Table 25. Functions of Processor Cluster Configuration Control Panel Row
Label

Switch/Indicator

Function

POWER
NNORM

1 indicator

Lighted when unit power is shut down due to abnormal operational
condition.

POWER
ON

1 switch

When in up or middle position, enables power-on control in the
unit power supply. (Middle position inhibits the unit reset signal.)
When in down position, power to unit is off.

SYSTEM
SEL

1 switch

Selects the processor bus to which the processor cluster is to be
connected (up is processor bus A, down is B).

CLOCK
SEL

1 switch

SeleGts the clock source (up, A or down, B) for the unit clock
subsystem.

PROCESSOR
ADDRESS

3 switches

Establishes the logical address of the cluster within a group of
processor clusters.
Note: The 5-bit chassis location number and not the proce'ssor
address is used in addressing the configuration switches for
a given unit by the RD instruction directed to the Configuration Control Panel.

BP
ENABLE

1 switch

When in down position, inhibits the
internal bus.

MIOP
ENABLE

1 switch

When in down position, inhibits the MIOP from operating on the
internal bus.

010

1 switch

When in down position, inhibits external 010 interface.

ALTSEL

1 switch

Selects either the remote console (down position) or alternate
operator's console (up position) to enter data on the Remote
Channel Interface.

FSELA

1 switch

Selects communications frequency for the primary operator's
console as follows:

from operating on the

ENABLE

up = same frequency as remote channel
down = 1200 baud
Note: The 1200 baud selection is effective only if the REMOTE
CHANNEL switch on the System Control Panel is not in
the SCC posi ti on.
FSELBO/FSELB1

152

2 switches

Configuration Control Panel (CCP)

Selects communications frequency for the alternate operator's
console and the Remote Diagnostic Interface (Remote Channel) as
follows:

-BO

-B1

Rate (baud)

110

1200

unspecified

300

Table 25. Functions of Processor Cluster Configuration Control Panel Row (cont.)
Label

Swi tch/lndi cator

Function

REAL-TIME CLOCK SEL

8 switches

Four groups (labeled RTC1, RTC2, RTC3, and STC) of 2 switches
each (labeled SO and 51), used for selecting the real-time clock
frequencies; each of the three real-time clock counters and the one
subjective clock counter may have their frequencies selected by the
proper combination of the two switches associated with each counter:

-51

Frequency (Hz)

500

External real-time clock source

2000

Power line

Table 26. Functions of Memory Unit Configuration Control Panel Row
Label

Swi tch/lndi cator

Function

POWER
NNORM

1 indicator

Lighted when unit power is shut down due to abnormal operational
condition.

POWER
ON

1 switch

When in up or middle position, enables power-on control in the
unit power supply. (Middle position inhibits the unit reset signal.)
When .in down position, power to unit is off.

SYSTEM
SEL

1 switch

Determines to which central shared resources the reset signal is
connected.

CLOCK
SEL

1 switch

Selects which clock the memory shall use; up position selects system
c.lock A, down position selects system clock B.

UNIT
ADDRESS

3 switches

Establishes the logical address of the unit within a group of memory
units.

PORT ENABLE

6 switches

Down position disables, up enables, corresponding port when setting
up different configuration in the system. Switch 1 (leftmost) corresponds to port 1, etc., and switch 6 corresponds to port 6.

INTLV

1 switch

Up position selects interleave addressing mode in each memory unit;
down position means no interleaving in any memory unit. Only
two-way interleaving is allowed. The unit interleaved with this
memory unit must have its interleave switch on and be in the appropriate addressing range. The interleave logic operates only for
memory units with a number corresponding to a power of 2: i. e. ,
16K, 32K words; if other than a power of 2, the interleave signal
it receives is ignored. Interleaving is permissible only:

Between two memory units of the same size.

Provided the·two memory units cover an addressing range that
is continuous and starts at a multiple of the size of the two
memory units taken together.

Configuration Control Panel

153

Table 26. Functions of Memory Unit Configuration Control Panel Row (cont.)
Label

Switch/Indicator

Function

STARTING ADDRESS

7 switches

Used to set the starting addresses of the memory units. From left to
right the switches are labeled S12, S13, S14, S15, S16, S17, and
S 18. Using the switches as a 7-position binary field, this allows
memory to address up to 1 mi Ilion words.
When the memory system comprises memory units of different sizes,
some precautions are necessary to prevent false address recognition
as well as to prevent gaps in the memory range.

If all memory units have sizes that are powers of two, they can
a II be di fferent; they must , however, be assi gned in order of
decreasing size in the address continuum.
For instance, three memory units can be used in this manner:
Memory Unit No.

154

Configuration Control Panel

Size
-

Address Range

64K words

o to 64K word~

32K words

64 to 96K words

16K words

96 to 112K words

If a memory unit has a size that is not a power of two, it must
be situated in a memory system that satisfies the following
rules:
a.

All other memory units must have sizes that are a power
of two.

The starting address of the non-power-of-two unit must be
a multiple of the'next power of two above the size of that
unit.

The memory unit whose size is not a power of two must be
at the upper end of the address range.

APPENDIX A. REFERENCE TABLES
STANDARD CHARACTER SETS

This appendix contains the following reference material:
Title

EBCDIC

Standard Symbols and Codes
Standard 8-Bit Computer Codes (EBCDIC)

57-character set: uppercase letters, numerais, space,
and &
/
< > ( ) + I $ *
% # @

Standard 7-Bit Communication Codes (ANSCll)

63-character set: same as above plus

-,
Standard Symbol-Code Correspondences
89-character set: same as 63-character set plus
lowercase letters

Hexadecimal Arithmetic
Addition Table
Multiplication Table
Table of Powers of SixteenlO
Table of Powers of Ten16

ANSCII
64-character set: uppercase letters, numerals, space,
II
$ % &
()
* + ,
/ \
< >? @
A
#

and!
Hexadecimal-Decimal Integer Conversion Table

Hexadecimal-Decimal Fraction Conversion Table
95-character set: same as above plus lowercase letters
and

t }

Table of l>owers of Two
Mathematical Constants

CONTROL CODES
STANDARD SYMBOLS AND CODES
The symbol and code standards described in this publication
are applicable ·to all Xerox computer products, both hardware and software. They may be expanded or altered from
time to time to meet changing requirements.
The symbols listed here include two types: graphic symbols
and control characters. Graphic symbols are displayable
and printable; control characters are not. Hybrids are SP,
the symbol for a blank space; and DEL, the delete code,
which is not considered a control command.
Three types of code are shown: (1) the 8-bit Xerox Standard
Computer Code, i.e., the Extended Binary-Coded-Decimal
Interchange Code (EqCDIC); (2) the 7-bit American National
Standard Code for Information Interchange (ANSCII); and
(3) the Xerox standard card code.

In addition to the standard character sets Iisted above, the
symbol repertoire includes 37 control codes and the hybrid
,.

~~I

II.

L _OJ

__ J_

("0 ! _____ !..I ___ ..1 ___ I.

\,;UUI:: VLL \"YU.,U '-VU'C J'

I;) '-VII;)' ... "", "" ...

t""'"

_r _II _L ___ _
v, ... ,' ............ ...

ter sets). These are listed in the table titled Standard
Symbo I-Code Correspondences.

SPECIAL CODE PROPERTIES
The following two properties of all standard codes will be
retained for future standard code extensions:
1.

All control codes, and onl y the control codes, have
their two high-order bits equal to 1100 11 • DEL is not
considered a control code.

No two graphic EBCDIC codes have their seven loworder bi ts equa I.
.

Appendix A

155

STANDARD 8-BIT COMPUTER CODES (EBCDIC)
Most c
Hexadecimal
Binary

I 0000

NUL OLE

0001

SOH DCl

0010

STX

DC2

0011

ETX

DC3

0100

EaT DC4

0101

LF
NL

0110

0111

BEL

1000

E~M CAN

]

1001

ENQ EM

1010

1011

r//

~~"

~
~//
"///

~ ~ ~~

~ ~ ~~
~ ~ ~~

ETB

;:r//~

'// 'l'//;

~~
~1

ESC

NOTES:
A

1100

1101

(

)

1110

1111

;

[ I

] I

(7-12)

(7-14)

~~~

~~ ~

:I. ............... ,. . ~i~:l"~,,~

~ ~~
~~
~~~~
~ ~ ~ DEL

EBCDIC

ANSCII

\ (6-0)

The EBCDIC cantrol codes in columns 0
and 1 and their binary representation are
exactly the same as those in the ANSCII
table, except for two interchanges: LF /NL
with NAK, and HT with ENQ.

~
~

I...,

The characters Iappear in the 63- and
89-character EBCDIC sets but not in either
of the ANSCII-based sets. However, Xerox
software translates the characters
into ANSCII characters as follows:

t []

The characters .... \
~
are ANSCII
characters that do not appear in any of the
EBCDIC-based character sets, though they
are shown in the EBCDIC table.

1000 1001 1010 1011 1100 1101 1110 1111

~"'''FFi'

':ssi!l~;;

Digits

~~ ~ ~
'%
I/.'l. ~
~ ~ ~~
~ ~ ~ :%

NAK SUB

ACK SYN

}
.;;

0010 0011 0100 0101 , 0110 0111

0000 0001

.r; .. uI

Characters enclosed in heavy lines are
included only in the standard 63- and
89-character EBCDIC sets.
These characters are included only in the
standard 89-character EBCDIC set.

STANDARD 7-BIT COMMUNICATION CODES (ANSCII) 1
Most Significant Digits
Decimal
1
0
47
2
3
5
6
rows)
(col's.)1
Binary
xOOO xOOl xOl0 xOIl xl00 xlOI xl10 xlll

1 Most significant bit, added for 8-bit format, is either 0 or even parity.

DC3

EaT DC4

0000

NUL OLE

0001

SOH DCl

0010

STX

DC2

0011

ETX

0100

! 5

is
is

0101

ENQ NAK

0110

ACK SYN

0111

BEL

ETB

'cCl

1000

CAN

0
C

,
(

1001

1010

LF
NL

SUB

1011

ESC

;

[

1100

1101

]

1110

1111

51
\

156

Appendix A

)

..
..

m
n
'0

Columns 2-5 correspond to the 64-character ANSCII set.
Columns 2-7 correspond to the 95-character ANSCII set.
On many current teletypes, the symbol

.-Cl

Columns 0-1 are cantral codes.

(5-i4)
(5-15)
ESC or ALTMODE control (7-14)

and none of the symbols appearing in columns 6-7 are provided. Except for the three
symbol differences noted above, therefore, such teletypes provide all the characters in
the 64-character ANSCII set. (The Xerox 7015 Remote Keyboard Printer provides the
64-character ANSCII set also, but prints A as fl.)

-..
DEL

STANDARD SYMBOL-CODE CORRESPONDENCES
EBCDlCt
Hex. Dec.

Symbol

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

NUL
SOH
STX
ETX
EOT
HT
ACK
BEl
BSorEOM
ENQ
NAK

10
11
12
13
14
15
16
17
18
19
lA
lB

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

OLE
DCl
DC2
DC3
DC4
LF or NL
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US

1C
10
IE
IF
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
20
2E
2F

32
33

30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F

48
49
50
51
52
53
54
55
56
57
58
59

35
36
37
38
39
40

41
42
43
44
45
46
47

60
61
62

VT
FF
CR
SO
SI

ds
ss
ts
si

Card Code

ANSCn tt

Meaning

Remarks
00 thro~h 23 and 2F are control codes.

12-0-9-8-1
12-9-1
12-9-2
12-9-3
12-9-4
12-9-5
12-9-6
12-9-7
12-9-8
12-9-8-1
12-9-8-2
12-9-8-3
12-9-8-4
12-9-8-5
12-9-8-6
12-9-8-7

0-0
0-1
0-2
0-3
0-4
0-9
0-6
0-7
0-8
0-5
1-5
0-11
0-12
0-13
0-14
0-15

null
start of header
start of text
end of text
end of transmission
horizontal tab
acknowledge (positive)
bell
backspace or end of message
enquiry
negative acknowledge
vertical tab
form feed
carriage return
shift out
shift in

12-11-9-8-1
11-9-1
11-9-2
11-9-3
11-9-4
11-9-5
11-9-6
11-9-7
11-9-8
11-9-8-1
11-9-8-2
11-9-8-3
11-9-8-4
11-9-8-5
11-9-8-6
11-9-8-7

1-0
1-1
1-2
1-3
1-4
0-10
1-6
1-7
1-8
1-9
1-10
1-11
1-12
1-13
1-14
1-15

data link escape
device control 1
device control 2
device control 3
device control 4
line feed or new line
sync
end of transmission block
cancel
end of medium
substitute
escape
file separator
group separator
record separator
unit separator

11-0-9-8-1
0-9-1
U-4

1.'1:>:>

2956

2957

2958

2959

2967
2983
2999

2968 2969 2970 2971
2984 2985 2986 2987
3000 3001 3002 3003

2972 2973 2974 2975
2988 2989 2990 2991
3004 3005 3006 3007

BCO
BOO
BEO
BFO

3008
3024
3040
3056

3009
3025
3041
3057

3010
3026
3042
3058

3011
3027
3043
3059

3012
3028
3044
3060

3013
3029
3045
3061

3014
3030
3046
3062

3015
3031
3047
3063

3016
3032
3048
3064

3017
3033
3049
3065

3018
3034
3050
3066

3019
3035
3051
3067

3020
3036
3052
3068

3021
3037
3053
3069

3022
3038
3054
3070

3023
3039
3055
3071

COO
Cl0
C20
C30

3072
3088
3104
3120

3073
3089
3105
3121

3074
3090
3106
3122

3075
3091
3107
3123

3076
3092
3108
3124

3077
3093
3109
3125

3078
3094
3110
3126

3079
3095
3111
3127

3080
3096
3112
3128

3081
3097
3113
3129

3082
3098
3114
3130

3083
3099
3115
3131

3084
3100
3116
3132

3085
3101
3117
3133

3086
3102
3118
3134

3087
3103
3119
3135

C40
C50
C60
C70

3136
3152
3168
3184

3137
3153
3169
3185

3138
3154
3170
3186

3139
3155
3171
3187

3140
3156
3172
3188

3141
3157
3173
3189

3142
3158
3174
3190

3143
3159
3175
3191

3144
3160
3176
3192

3145
3161
3177
3193

3146
3162
3178
3194

3147
3163
3179
3195

3148
3164
3180
3196

3149
3165
3181
3197

3150
3166
3182
3198

3151
3167
3183
3199

COO
C90
CAO
CBO

3200
3216
3232
3248

3201
3217
3233
3249

3202
3218
3234
3250

3203
3219
3235
3251

3204
3220
3236
3252

3205
3221
3237
3253

3206
3222
3238
3254

3207
3223
3239
3255

3208
3224
3240
3256

3209
3225
3241
3257

3210
3226
3242
3258

3211
3227
3243
3259

3212
3228
3244
3260

3213
3229
3245
3261

3214
3230
3246
3262

3215
3231
3247
3263

CCO
CDO
CEO
CFO

3264
3280
3296
3312

3265
3281
3297
3313

3266
3282
3298
3314

3267
3283
3299
3315

3268
3284
3300
3316

3269
3285
3301
3317

3270
3286
3302
3318

3271
3287
3303
3319

3272
3288
3304
3320

3273
3289
·3305
3321

3274
3290
3306
3322

3275
3291

3276
3292
3308
3324

3277
3293
3309
3325

3278
3294
3310
3326

3279
3295
3311
3327

- - --

330l"

3323

Appendix A

167

HEXADECIMAL-DECIMAL INTEGER CONVERSION TABLE (cont.)

168

000
010
020
030

3328
3344
3360
3376

3329
3345
3361
3377

3330
3346
3362
3378

3331
3347
3363
3379

3332
3348
3364
3380

3333
3349
3365
3381

3334
3350
3366
3382

3335
3351
3367
3383

3336
3352
3368
3384

3337
3353
3369
3385

3338
3354
3370
3386

3339
3355
3371
3387

3340
3356
3372
3388

3341
3357
3373
3389

3342
3358
3374
3390

3343
3359
3375
3391

040
050
060
070

3392
3408
3424
3440

3393
3409
3425
3441

3394
3410
3426
3442

3395
3411
3427
3443

3396
3412
3428
3444

3397
3413
3429
3445

3398
3414
3430
3446

3399
3415
3431
3447

3400
3416
3432
3448

3401
3417
3433
3449

3402
3418
3434
3450

3403
3419
3435
3451

3404
3420
3436
3452

3405
3421
3437
3453

340(>

080
090
OAO
OBO

3456
3472
3488
3504

3457
3473
3489
3505

3458
3474
3490
3506

3459
3475
3491
3507

3460
3476
3492
3508

3461
3477
3493
3509

3462 J463
3478 3479
3494 3495
3510 3511

3464
3480
3496
3512

3465
3481
3497
3513

3466
3482
3498
3514

3467
3483
3499
3515

3468
3484
3500
3516

3469
3485
3501
3517

3470
3486
3502
3518

3471
3487
3503
3519

oeo
ODO
OEO
OFO

3520
3536
3552
3568

3521
3537
3553
3569

3522
3538
3554
3570

3523
3539
3555
3571

3524
3540
3556
3572

3525
3541
3557
3573

3526
3542
3558
3574

3527
3543
3559
3575

3528
3544
3560
3576

3529
3545
3561
3577

3530
3546
3562
3578

3531
3547
3563
3579

3532
3548
3564
3580

3533
3549
3565
3581

3534
3550
3566
3582

3535
3551
3567
3583

EOO
ElO
E20
E30

3584
3600
3616
3632

3585
3601
3617
3633

3586
3602
3618
3634

3587
3603
3619
3635

3588
3604
3620
3636

3589
3605
3621
3637

3590
3606
3622
3638

3591
3607
3623
3639

3592
3608
3624
3640

3593
3609
3625
3641

3594
3610
3626
3642

3595
3611
3627
3643

3596
3612
3628
3644

3597
3613
3629
3645

3598
3614
3630
3646

3599
3615
3631
3647

E40
E50
E60
E70

3648
3664
3680
3696

3649
3665
3681
3697

3650
3666
3682
3698

3651
3667
3683
3699

3652
3668
3684
3700

3653
3669
3685
3701

3654
3670
3686
3702

3655
3671
3687
3703

3656
3672
3688
3704

3657
3673
3689
3705

3658
3674
3690
3706

3659
3675
3691
3707

3660
3676
3692
3708

3661
3677
3693
3709

3662
3678
3694
3710

3663
3679
3695
3711

E80
E90
EAO
EBO

3712
3728
3744
3760

3713
3729
3745
3761

3714
3730
3746
3762

3715
3731
3747
3763

3716
3732
3748
3764

3717
3733
3749
3765

3718
3734
3750
3766

3719
3735
3751
3767

3720
3736
3752
3768

3721
3737
3753'
3769

3722
3738
3754
3770

3723
3739
3755
3771

3724
3740
3756
3772

3725
3741
3757
3773

3726
3742
3758
3774

3727
3743
3759
3775

Eeo
EOO
EEO
EFO

3776
3792
3808
3824

3777
3793
3809
3825

3778
3794
3810
3826

3779
3795
3811
3827

3780
3796
3812
3828

3781
3797
3813
3829

3782
3798
3814
3830

3783
3799
3815
3831

3784
3800
3816
3832

3785
3801
3817
3833

3786
3802
3818
3834

3787
3803
3819
3835

3788
3804
3820
3836

3789
3805
3821
3837

3790
3806
3822
3838

3791
3807
3823
3839

FOO
FlO
F20
F30

3840
3856
3872
3888

3841
3857
3873
3889

3842
3858
3874
3890

3843
3859
3875
3891

3844
3860
3876
3892

3845
3861
3877
3893

3846
3862
3878
3894

3847
3863
3879
3895

3848
3864
3880
3896

3849
3865
3881
3897

3850 3851
3866 3867
3882 3883
3P. ·1 3899

3852
3868
3884
3900

3853
3869
3885
3901

3854
3870
3886
3902

3855
3871
3887
3903

F40
F50
F60
F70

3904
3920
3936
3952

3905
3921
3937
3953

3906
3922
3938
3954

3907
3923
3939
3955

3908
3924
3940
3956

3909
3925
3941
3957

3910
3926
3942
3958

3911
3927
3943
3959

3912 3913 3914 3915
3928 :>92~ ::1930 3931
3944 3945 3946 3947
3960 3961 3962 3963

3916
3932
3948
3964

3917
3933
3949
3965

3918
3934
3950
3966

3919
3935
3951
3967

F80
F90
FAO
fBO

3968 3969 3970 3971
3984 3985 3986 3987
4000 4001 4002 4003
40~6 "tV 1/
4018 ,+V17

3972
3988
4004
4020

3973
3989
4005
4'"''
V.£I

3974
3990
4006
4022

3975
3991
4007
4023

3976 3977 3978 3979
3992 3993 3994 3995
4008 4009 4010 4011
4"nA
U.£4 4025 4026 4027

3980 3981
3996 3997
4012 4013
4028 l~';29

3982
3998
4014
4030

3983
3999
4015
403i

Feo
FOO
FEO
FFO

4032
4048
4064
4080

4036
4052
4068
4084

4037
4053
4069
4085

4038
4054
4070
4086

4039
4055
4071
4087

4040
4056
4072
4088

4045
4060 4061
4076 4077
4092 4093

4046
4062
4078
4094

4047
4063
4079
4095

~"1~

4033
4049
4065
4081

Appendix A

..11\11'\

4034
4050
4066
4082

4035
4051
4067
4083

4041
4057
4073
4089

4042
4058
4074
4090

4043
4059
4075
4091

404t1

3407
3422 3423
3438 3439
3454 3455

HEXADECIMAL-DEC..AL FRACTION CONVERSION TABLE

Hexadecimal

Decimal

Hexadecima I

.00
.01
.02
.03
.04
.05
.06
.07
.08
.09
.OA
.OB
.OC
.00
.OE
.OF

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
000000
000000
00 00 00
000000
000000

.00000 00000
.00390 62500
.00781 25000
.01171 87500
.0156250000
.01953 12500
.02343 75000
.02734 37500
.03125 00000
.0351562500
.03906 25000
.04296 87500
.04687 50000
.05078 12500
.05468 75000
.05859 37500

.40
.41
.42
.43
.44
..45
.46
.47
.48
.49
.4A
.4B
.4C
.40
.4E
.4F

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00'
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00

.. 25000 00000
.25390 62500
.25781 25000
.26171 87500
.2656250000
.26953 12500
.27343 75000
.2n34 37500
.28125 00000
.2851562500
.28906 25000
.29296 87500
.29687 50000
.30078 12500
.30468 75000
.30859 37500

.10 000000
.11 000000
.12 000000
.13 000000
.14 000000
.15 000000
.16 00 00 00
.17 000000
.18 000000
.19 000000
.IAOOOOOO
.IB 000000
.1C 000000
.10000000
.IE 000000
.IF 000000

.06250 00000
.06640 62500
.07031 25000
.07421 87500
.0781250000
.08203 12500
.08593 75000
.08984 37500
.09375 00000
.09765 62500
· 10 156 25000
.10546 87500
.10937 50000
.11328 12500
.1171875000
.1210937500

.50
.51
.52
.53
.54
.55
.56
.57
.58
.59
.5A
.5B
.5C
.50
.5E
.5F

00 00 00
00 00 00
00 00 00
00 00 00
000000
000000
00 00 00
000000
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 00 00

.20
.21
.22
.23
.24
.25
.26
.27
.28
.29
.2A
.2B
.2C
.20
.2E
.2F

000000
000000
00 00 00
000000
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 00 00
000000
000000
00 00 00
00 00 00
00 00 00
00 00 00

.12500 OOOQO
.12890 62500
.13281 25000
.13671 87500
.14062 50000
.14453 12500
.14843 75000
.15234 37500
· 15625 00000
.1601562500
· 16406 25000
.167~6 87500
.17187 50000
.17578 12500
.17968 75000
.1835937500

.60
.61
.62
.63
.64
.65
.66
.67
.68
.69
.6A
.6B
.6C
.60
.6E
.6F

.30
.31
.32
.33
.34
.35
.36
.37
.38
.39
.3A
.3B
.3C
.30
.3E
.3F

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 0000
000000
00 00 00

· 18750 00000
.19140 62500
· 19531 25000
.19921 87500
.20312 50000
.20703 12500
.21093 75000
.21484 37500
.2187500000
.22265 62500
.2265625000
.23046 87500
.23437 50000
. 23828 12500
.2421875000
.2460937500

.70
.71
.72
.73
.74
.75
.76
.77
.78
.79
.7A
.7B
.7C
.70
.7E
.7F

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

.80 00 00 00
.81 00 00 00
.82 00 00 00
.83 00 00 00
.84 00 00 00
.85 00 00 00
.86 00 00 00
.87 00 00 00
.88 00 00 00
.89 00 00 00
.8A 00 00 00
.8B 00 00 00
.8C 00 00 00
.800000 00
.8E 00 00 00
.8F 00 00 00

.50000 00000
.50390 62500
.50781 25000
.51171 87500
.5156250000
.51953 12500
.52343 75000
.52734 37500
.53125 00000
.53515 62500
.53906 25000
.5429687500
.54687 50000
.55078 12500
.55468 75000
.5585937500

.CO 00 00 00
.Cl 00 00 00
.C2 00 00 00
.C3 00 00 00
.C4 00 00 00
.C5 00 00 00
.C6 00 00 00
.C7 00 00 00
.C8 00 00 00
.C9 00 00 00
.CA 00 00 00
.CB 00 00 00
.CC 000000
.CO 00 00 00
.CE 00 00 00
.CF 00 00 00

.75000 00000
.75390 62500
.75781 25000
.7617187500
.76562 50000
.76953 12500
.n34375000
.n734 37500
.78125 00000
.78515 62500
.78906 25000
.7929687500
.79687 50000
.80078 12500
.8046875000
.80859 37500

.31250 00000
.31640 62500
.32031 25000
.32421 87500
.32812 50000
.33203 12500
.33593 75000
.33984 37500
.34375 00000
.34765 62500
.35156 25000
.35546 87500
.35937 50000
.36328 12500
.3671875000
.3710937500

.90
.91
.92
.93
.94
.95
.96
.97
.98
.99
.9A
.9B
.9C
.90
.9E
.9F

00 00 00
00 00 00
000000
000000
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00

.5625000000
.56640 62500
.57031 25000
.57421 87500
.57812 50000
.58203 12500
.58593 75000
.58984 37500
.59375 00000
.59765 62500
.60156 25000
.60546 87500
.60937 50000
.61328 12500
.6171875000
.62109 37500

.00 00 00 00
.01 00 00 00
.02 00 00 00
.03 00 00 00
.04 00 00 00
.05 00 00 00
.06 00 00 00
.07 00 00 00
.08 00 00 00
.09 00 00 00
.OA 00 00 00
.OB 00 00 00
.DC 00 00 00
.0000 00 00
.OE 00 00 00
.OF 00 00 00

.81250 00000
.81640 62500
.82031 25000
.82421 87500
.82812 50000
.83203 12500
.83593 75000
.83984 37500
.84375 00000
.8476562500
.85156 25000
.85546 87500
.85937 50000
.86328 12500
.86718 75000
.87109 37500

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
000000
00 00 00
000000
00 00 00

.37500 00000
.37890 62500
.38281 25000
.38671 87500
.39062 50000
.39453 12500
.39843 75000
.40234 37500
.40625 00000
.410 15 62500
.41406 25000
.41796 87500
.42187 50000
.42578 12500
.42968 75000
.43359 37500

.AO 00 00 00
.Al 00 00 00
.A2 00 00 00
.A3 00 00 00
.A4 00 00 00
.AS 00 00 00
.A6 00 00 00
.A7 00 00 00
.A8 00 00 00
.A9 00 00 00
.AA 00 00 00
.AB 00 00 00
.AC 00 00 00
.AO 00 00 00
.AE 00 00 00
.AF 00 00 00

.62500 00000
.62890 62500
.63281 25000
.63671 87500
.64062 50000
.64453 12500
.64843 75000
.65234 37500
.65625 00000
.66015 62500
.66406 25000
.66796 87500
.6718750000
.67578 12500
.67968 75000
.68359 37500

.EO
.El
.E2
.E3
.E4
.E5
.E6
.E7
.E8
.E9
.EA
.EB
.EC
.EO
.EE
.EF

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00

.87500 00000
.87890 62500
.88281 25000
.88671 87500
.8906250000
.89453 12500
.89843 75000
.90234 37500
.90625 00000
.9101562500
.91406 25000
.91796 87500
.92187 50000
.92578 12500
.92968 75000
.93359 37500

00 00 00
00 00 OQ
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00

.43750 00000
.44140 62500
.44531 25000
.44921 87500
.45312 50000
.45703 12500
.46093 75000
.46484 37500
.4687500000
.47265 62500
.47656 25000
.48046 87500
.48437 50000
.48828 12500
.49218 75000
.49609 37500

.BO
.Bl
.B2
.B3
.84
.B5
.86
.B7
.88
.89
.8A
.BB
.BC
.BO
.BE
.SF

.68750 00000
.6914062500
.69531 25000
.69921 87500
.70312 50000
.70703 12500
.71093 75000
.71484 37500
.71875 00000
.72265 62500
.72656 25000
.73046 87500
.73437 50000
.73828 12500 .
.7421875000
.74609 37500

.FO
.FI
.F2
.F3
.F4
.F5
.F6
.F7
.F8
.F9
.FA
.FB
.FC
.FO
.FE
.FF

00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00

.93750 00000
.94140 62500
.94531 25000
.94921 87500
.95312 50000
.95703 12500
.96093 75000
.96484 37500
.96875 00000
.97265 62500
.97656 25000
.98046 87500
.98437 50000
.98828 12500
.9921875000
.99609 37500

000000
00 00 00
00 00 00
000000
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 00 00
00 OQ 00
00 00 00
00 00 00

Appendix A

169

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadec ima I

Decimal

.0000
.00 01
.00 02
.00 03
.00 04
.00 05
.00 06
.00 07
.00 08
.00 09
.00 OA
.00 OB
.00 OC
.00 00
.00 OE
.00 OF

0000
0000
00 00
00 00
0000
00 00
0000
0000
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00

.00000 00000
.00001 52587
.0000305175
.00004 57763
.00006 10351
.00007 62939
.00009 15527
.00010 68115
.0001220703
.0001373291
.00015 25878
.0001678466
.0001831054
.0001983642
.00021 36230
.00022 88818

.00 40
.00 41
.00 42
.00 43
.00 44
.00 45
.00 46
.00 47
.00 48
.00 49
.004A
.00 4B
.00 4C
.00 40
.00 4E
.00 4F

00 00
00 00
00 00
00 00
0000
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00

.00097 65625
.00099 18212
.001 00 70800
.00 102 23388
.0010375976
.00 105 28564
.00106 81152
.00108 33740
.0010986328
.00111 38916
.0011291503
.00114 44091
.00115 96679
.00117 49267
.0011901855
.00120 54443

.00 80 00 00
.00 81 00 00
.00 82 0000
.0083 0000
.0084 00 00
.00 85 00 00
.00 86 00 00
.00 87 00 00
.00 88 00 00
.00 89 00 00
.00 8A 00 00
.008B 0000
.00 8C 00 00
.00800000
.00 8E 00 00
.008F 00 00

.0019531250
.00 196 83837
.00198 36425
.00199 89013
.00201 41601
.00202 94189
.00204 46777
.00205 99365
.00207 51953
.00209 04541
.0021057128
.0021209716
.00213 62304
.00215 14892
.0021667480
.00218 20068

.00 CO 00 00
.00 Cl 0000
.00 C2 00 00
.00 C3 00 00
.00 C4 00 00
.00 C5 00 00
.00 C6 0000
.00 C7 00 00
.00 C8 00 00
.00 C9 00 00
.00 CA 00 00
.00 CB 0000
.00 CC 00 00
.00 CD 00 00
.00 CE 0000
.00 CF 00 00

.00292 96875
.0029449462
.00296 02050
.0029754638
.00299 07226
.00300 59814
.00302 12402
.00303 64990
.00305 17578
.00306 70166
.00308 22753
.00309 75341
.00311 27929
.00312 80517
.00314 33105
.00315 85693

.00 10 00 00
.00 11 00 00
.00 12,00 00
.00 13 0000
.00 14 00 00
.00 15 0000
.00 16 0000
.00170000
.00 18 0000
.00 19 00 00
.00 lA 0000
.00 lB 00 00
.001C 00 00
.00100000
.00 IE 00 00
.00 IF 00 00

.00024 41406
.00025 93994
.00027 46582
.00028 99169
.00030 51757
.00032 04345
.0003356933
.0003509521
.0003662109
.00038 14697
.0003967285
.00041 19873
.0004272460
.00044 25048
.00045 77636
.00047 30224

.00 50 00 00
.00 51 00 00
.00 52 00 00
.0053 0000
.00 54 0000
.00 55 00 00
.00 56 0000
.00 57 00 00
.0058 0000
.00 59 00 00
.005A 00 00
.00 5B 00 00
.00 5COO 00
.00 50 00 00
.00 5E 00 00
.00 5F 00 00

.0012207031
.00123 59619
.00125 12207
.00126 64794
.00128 17382
.00 129 69970
.00131 22558
.0013275146
.00 134 27734
.00 135 80322
.00137 32910
.0013885498
.00140 38085
.00141 90673
.00143 43261
.00144 95849

.00 90
.00 91
.00 92
.00 93
.0094
.00 95
.0096
.00 97
.00 98
.00 99
.00 9A
.00 9B
.00 9C
.00 90
.00 9E
.00 9F

00 00
0000
00 00
0000
00 00
00 00
00 00
00 00
0000
00 00
00 00
00 00
0000
00 00
00 00
00 00

.0021972656
.00221 25244
.00222 77832
.00224 30419
.00225 83007
.00227 35595
.0022888183
.00230 40771
.00231 93359
.00233 45947
.00234 98535
.00236 51123
.0023803710
.00239 56298
.00241 08886
.00242 61474

.00 DO 00 00
.0001 0000
.00 02 00 00
.0003 0000
.00 04 0000
.00 05 0000
.00 D6 0000
.00 07 00 00
.0008 00 00
.00 09 00 00
.00 OA 00 00
.00 DB 0000
.00 DC 00 00
.00 DO 00 00
.00 DE 00 00
.00 OF 00 00

.00317 38281
.00318 90869
.00320 43457
.00321 96044
.00323 48632
.00325 01220
.00326 53808
.00328 06396
.00329 58984
.00331 11572
.00332 64160
.00334 16748
.00335 69335
.00337 21923
.00338 74511
.00340 27099

.00 20
.00 21
.0022
.0023
.00 24
.0025
.00 26
.00 27
.00 28
.00 29
.00 2A
.00 2B
.00 2C
.00 20
.00 2E
.00 2F

00 00
00 00
0000
00 00
00 00
0000
0000
0000
00 00
00 00
0000
00 00
0000
0000
00 00
00 00

.00048 82812
.00050 35400
.00051 87988
.00053 40576
.00054 93164
.0005645751
.00057 98339
.00059 50927
.00061 03515
.0006256103
.00064 086 91
.00065 61279
.00067 13867
.00068 66455
.00070 19042
.00071 71630

.00 60
.00 61
.00 62
.00 63
.00 64
.00 65
.00 66
.0067
.00 68
.00 69
.00 6A
.00 6B
.006C
.00 60
.00 6E
.006F

00 00
00 00
00 00
00 00
00 00
00 00
0000
0000
00 00
0000
00 00
00 00
0000
00 00
00 00
00 00

.00146 48437
.00148 01025
.0014953613
.00151 06201
.0015258789
.00154 11376
.0015563964
.00157 16552
.0015869140
.00160 21728
.00161 74316
.00163 26904
.0016479492
.00 166 32080
.0016784667
.0016937255

.00 AO
.00 Al
.00 A2
.00 A3
.00 A4
.00 A5
.00 A6
.00 A7
.00 A8
.00 A9
.00 AA
.00 AB
.00 AC
.00 AD
.00 AE
.00 AF

00 00
00 00
00 00
00 00
00 00
00 00
0000
00 00
00 00
00 00
00 00
00 00
00 00
0000
00 00
00 00

.00244 14062
.00245 66650
.00247 19238
.00248 71826
.00250 24414
.00251 77001
.00253 29589
.0025482177
.00256 34765
.00257 87353
.0025939941
,00260 92529
.00262 45117
.0026397705
.00265 50292
.00267 02880

.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00

EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

0000
00 00
0000
00 00
0000
00 00
0000
0000
0000
0000
0000
0000
0000
0000
0000
00 00

.00341 79687
.00343 32275
.00344 84863
.00346 37451
.00347 90039
.00349 42626
.00350 95214
.00352 47802
.0035400390
.00355 52978
.0035705566

.0030
.0031
.0032
.0033
.0034
.0035
.0036
.0037
.0038
.0039
.003A
.003B
.003C
.0030
.003E
.003F

0000
0000
0000
0000
00 00
0000
0000
0000
00 00
0000
00 00
0000
00 00
0000
0000
00 00

.00073
.00074
.00076
.00077
.00079
.00080
.00082
.00083
.00085
.00086
.00088
.00090
.00091
.00093
.00094
.00096

.00 70
.0071
.0072
.0073
.00 74
.0075
.0076
.0077
.0078
.0079
.007A
.007B
.007C
.0070
.007E
.007F

00 00
0000
0000
0000
0000
00 00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

.0017089843
.00172 42431
.0017395019
.0017547607
.0017700195
.0017852783
.0018005371
.00181 57958
.00183 10546
.00184 63134
.00186 15722
.0018768310
.0018920898
.00190 73486
.00192 26074
.00193 78662

.00 BO 0000
.ooBl0000
.00 B2 0000
.00 B3 0000
.00 B4 0000
.00 B5 0000
.00 B6 0000
.00 B7 00 00
.00 B8 0000
.00 B9 0000
.00 BA 0000
.00 BB 0000
.00 BC 0000
.00 BO 0000
.00 BE 0000
.00 BF 0000

.00268 55468
.0027008056
.00271 60644
.00273 13232
.0027465820
.00276 18408
.00277 70996
.00279 23583
.0028076171
.00282 28759
.00283 81347
.00285 33935
.00286 86523
.00288 39111
.0028991699
.00291 44287

.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00
.00

FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

00 00
0000
0000
00 00
00 00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

.00366 21093
.0036773681
.00369 26269
.0037078857
.00372 31445
.00373 84033
.00375 36621
.00376 89208
.0037841796
.0037994384
.00381 46972
.00382 99560
.0038452148
.00386 04736
.00387 57324
.0038909912

170

Appendix A

24218
76806
29394
81982
34570
87158
39746
92333
44921
97509
50097
02685
55273
07861
60449
13037

.0035858154

.00360
.00361
.00363
.00364

10742
63330
15917
68505

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

.000000
.000001
.00 00 02
.00 00 03
.00 00 04
.000005
.00 00 06
.000007
.000008
.00 00 09
.00 00 OA
.0000 OB
.00 00 OC
.00 00 00
.00 00 OE
.00 00 OF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 00000
.00000 00596
.00000 01192
.00000 01788
.00000 02384
.00000 02980
.00000 03576
.00000 04172
.00000 04768
.00000 05364
.00000 05960
.00000 06556
.00000 07152

.00 00 40
.00 00 41
.00 00 42
.000043
.00 00 44
.00 00 45
.00 00 46
.00 00 47
.00 00 48
.00 00 49
.00 00 4A
.00 00 4B
.00 00 4C
.00 00 40
.00 00 4E
.00 00 4F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 38146
.00000 38743
.00000 39339
.00000 39935
.00000 40531
.00000 41127
.00000 41723
.00000 42319
.00000 42915
.00000 43511
.00000 44107
.00000 44703
.00000 45 299
.00000 45895
.00000 46491
.00000 47087

.00 00 80
.00 00 81
.00 00 82
.00 00 83
.00 00 84
.00 00 85
.00 00 86
.00 00 87
.000088
.00 00 89
.0000 SA
.00 00 8B
.00 00 8C
.00 00 80
.00 00 8E
.00 00 8F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 76293
.00000 76889

.00 00 CO
.00 00 Cl
.00 00 C2
.00 00 C3
.00 00 C4
.00 00 C5
.00 00 C6
.00 00 C7
.00 00 C8
.00 00 C9
.00 00 CA
.00 00 CB
.00 00 CC
.00 00 CD
.00 00 CE
.00 00 CF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00001 14440
.00001 15036
.00001 15633
.00001 16229
.00001 16825
.00001 17421
.00001 18017
.00001 18613
.00001 19209
.00001 19805
.0000 1 2040 1
.00001 20997
.00001 21593
.00001 22189
.00001 22785
.00001 23381

.000010
.00 00 11
.00 00 12
.00 00 13
.00 00 14
.00 00 15
.000016
.00 00 17
.000018
.00 00 19
.00 00 lA
.00 00 lB
.00 00 1C
.000010
.00 00 IE
.00 00 IF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00 00 50
.00 00 51
.00 00 52
.00 00 53
.00 00 54
.00 00 55
.00 00 56
.000057
.00 00 58
.00 00 59
.00 00 5A
.00 00 5B
.00 00 5C
.000050
.00 00 5E
.00 00 5F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 47683
.00000 48279
.00000 48875
.00000 49471
.00000 50067
.00000 50663
.00000 51259
.00000 51856
.00000 52452
.00000 53048
.00000 53644
.00000 54240
.00000 54836
.00000 55432
.00000 56028
.00000 56624

.00 00 90
.00 00 91
.00 00 92
.00 00 93
.00 00 94
.00 00 95
.00 00 96
.00 00 97
.00 00 98
.00 00 99
.00 00 9A
.00 00 9B
.00 00 9C
.00 00 90
.00 00 9E
.00 00 9F

00
00
CO
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00 00 DO
.00 00 01
.00 00 02
.00 00 03
.00 00 D4
.00 00 05
.00 00 D6
.00 00 07
.00 00 OS
.000009
.00 00 OA
.00 00 DB
.0000 DC
.00 00 DO
.00 00 DE
.00 00 OF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00001 24573
.00001 25169
.00001 25765
.00001 26361
.00001 26957
.00001 27553
.00001 28149
.00001 28746
.00001 29342
.0000 1 29938
.00001 30534
.00001 31130
.00001 31726
.00001 32322
.00001 32918

EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00001 33514
.00001 34110
.00001 34706
.00001 35302
.00001 35898
.00001 36494
.00001 37090
.00001 37686
.00001 38282
.0000 1 38878
.00001 39474
.00001 40070
.00001 40666
.00001 41263
.00001 41859
.00001 42455

FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00001 43051
.0000 1 43647
.0000 1 44243
.00001 44839
.00001 45435
.0000 1 46031
.0000 1 46627
.0000 1 47223
.0000 1 47819
.00001 48415
.00001 49011
.00001 49607
.00001 50203
.00001 50799
.00001 51395
.00001 51991

.00000 on48
.00000 08344
.00000 08940
09536
10132
10728
11324
11920
12516
13113
13709
14305
14901
15497
16093
16689
17285
17881

.00000 184n

.00000 n486
.00000 78082
.00000 78678
.00000 79274
.00000 79870
.00000 80466
.00000 81062
.00000 81658
.00000 82254
.00000 82850
.00000 83446
.00000 84042
.00000 84638
.00000 85 234
85830
86426
87022
87618
88214
88810
89406
90003
90599
91195
91791
92387
92983
93579
94175

.00000 94nl

.00 00 20
.000021
.00 00 22
.00 00 23
.00 00 24
.000025
.00 00 26
.000027
.00 00 28
.00 00 29
.00 00 2A
.0000 2B
.00 00 2C
.00 00 20
.00002E
.00 00 2F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 19073
.00000 196P9
.00000 20265
.00000 20861
.00000 21457
.00000 22053
.00000 22649
.00000 23245
.0000023841
.00000 24437
.00000 25033
.00000 25629
.00000 26226
.00000 26822
.00000 27418
.00000 28014

.00 00 60
.00 00 61
.00 00 62
.00 00 63
.00 00 64
.00 00 65
.00 00 66
.00 00 67
.00 00 68
.00 00 69
.00 00 6A
.00 00 6B
.00 00 6C
.00 00 60
.00006E
.00 00 6F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000 57220
~OOOOO 57816
.00000 58412
.00000 59008
.00000 59604
.00000 60200
.00000 60796
.00000 61392
.00000 61988
.00000 62584
.00000 63180
.00000 63776
.00000 64373
.00000 64969
.00000 65565
.00000 66161

.00 00 AO
.00 00 Al
.00 00 A2
.00 00 A3
.00 00 A4
.00 00 AS
.00 00 A6
.00 00 A7
.00 00 A8
.0000 A9
.00 00 AA
.00 00 AB
.00 00 AC
.0000 AD
.0000 AE
.00 00 AF

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000
.00000
.00000
.00000

98347
98943
99539
00135
00731
01327
01923
02519
03116
03712
04308

.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00

.00 0030
.00 00 31
.00 00 32
.00 00 33
.00 00 34
.00 00 35
.000036
.00 00 37
.000038
.000039
.0000 3A
.00 00 3B
.00003C
.000030
.0000 3E
.0000 3F

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00 00 70
.00 00 71
.00 00 72
.00 00 73
.00 00 74
.00 00 75
.00 00 76
.00 00 77
.00 00 78
.00 00 79
.00 00 7A
.00 00 7B
.00 00 7C
.00 00 70
.00 00 7E
.00 00 7F

00
00

.00000 66757
.00000 67353
.00000 67949
.00000 68545
.00000 69141
.00000 69737
.00000 70333
.00000 70929
.00000 71525
.00000 72121
.00000 72717
.00000 73313
.00000 73909
.00000 74505
.00000 75101
.00000 75697

.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

.00001 04904
.00001 05500
.0000 1 06096
.0000 1 06692
.00001 07288
.00001 07884
.0000 1 08480
.00001 09076
.00001 09672
.00001 10268
.00001 10864
.00001 11460
.0000 1 12056
.00001 12652
.00001 13248
.0000 1 13844

.0000
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00

28610
29206
29802
30398
30994
31590
32186
32782
33378
33974
34570
35166
35762
36358
36954
37550

OQ
00
00
00
00
00
00
00
00
00
00
00
00
00

BO
Bl
B2
B3
B4

B6
B7
B8
B9
BA
BB
BC
SO
BE
BF

95367
95963
96559
97155

.00000 9n51
.00000
.00000
.00000
.00001
.00001
.00001
.00001
.00001
.00001
.00001
.00001

.00001239n

Appendix A

171

HEXADECIMAL-DECIMAL FRACTION CONVERSION TABLE (cont.)

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

Hexadecimal

Decimal

.0000 00 00
.00 00 00 01
.00000002
.00 00 00 03
.00 00 00 04
.00000005
.00 00 00 06
.00 00 00 07
.00000008
.00000009
.00 00 00 OA
.0000 00 OB
.00 00 00 OC
.00 00 00 00
.0000 00 OE
.00 00 00 OF

.00000 00000
.00000 00002
.00000 00004
.00000 00006
.00000 00009
.00000 000 11
.00000 000 13
.00000 00016
.00000 000 18
.00000 00020
.00000 00023
.00000 00025
.00000 00027
.00000 00030
.00000 00032
.00000 00034

.00 00 00 40
.00 00 00 41
.00 00 00 42
.00000043
.00000044
.00000045
.00 00 00 46
.00 00 00 47
.00 00 00 48
.00 00 00 49
.0000 00 4A
.00 00 00 4B
.00 00 00 4C
.00 00 00 40
.000000 4E
.00 00 00 4F

.00000 00149
.00000 00151
.00000 00153
.00000 00 155
.00000 00158
.00000 00160
.00000 00162
.00000 00165
.00000 00167
.00000 00169
~OOOOO 00 172
.00000 00174
.00000 00176
.00000 00179
.0000000181
.00000 00183

.00 00 00 80
.0000 00 81
.00 00 00 82
.00000083
.00 00 00 84
.0000 00 85
.00 00 00 86
.00 00 00 87
.00 00 00 88
.00 00 00 89
.00 00 00 8A
.00 00 00 8B
.000000 8C
.00 00 00 80
.0000 00 8E
.00 00 00 8F

.00000 00298
.00000 00300
.00000 00302
.00000 00305
.00000 00307
.00000 00309
.00000 00311
.00000 00314
.00000 00316
.00000 00318
.00000 00321
.00000 00323
.00000 00325
.00000 00328
.00000 00330
.00000 00332

.00 00 00 CO
.00 00 00 Cl
.00 00 00 C2
.00 00 00 C3
.00 0000 C4
.00 00 00 C5
.00 00 00 C6
.00 00 00 C7
.00 00 00 C8
.00 00 00 C9
.00 00 00 CA
.0000 00 CB
.00 00 00 CC
.00 00 00 CO
.00 00 00 CE
.00 00 00 CF

.00000 00447
.00000 00449
.00000 00451
.00000 00454
.00000 00456
.00000 00458
.00000 00461
.00000 00463
.00000 00465
.00000 00467
.00000 00470
.00000 00472
.00000 00474
.00000 00477
.00000 00479
.00000 00481

.00 00 00
.000000
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.000000
.000000
.000000
.000000
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00

.00000 00037
.00000 00039
.00000 00041
.00000 00044
.00000 00046
.00000 00048
.00000 00051
.00000 00053
.00000 00055
.00000 00058
.00000 00060
.00000 00062
.00000 00065
.00000 00067
.00000 00069
.00000 00072

.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.0000
.00 00
.00 00
.00 00
.00 00

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00000090
.00 00 00 91
.00 00 00 92
.00 00 00 93
.00 00 00 94
.00 00 00 95
.00 00 00 96
.00 00 00 97
.00 00 00 98
.00 00 00 99
.00 00 00 9A
.00 00 00 9B
.00 00 00 9C
.00 00 00 90
.00 00 00 9E
.00 00 00 9F

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00 00 00 DO
.00 00 0001
.00 00 00 02
.00 00 00 03
.00 00 00 D4
.00 00 00 05
.00 00 00 D6
.00 00 00 07
.00 00 00 OS
.00000009
.00 00 00 OA
.00 00 00 DB
.00 00 00 DC
.00 00 00 DO
.00 00 00 DE
.00 00 00 OF

.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

.00000020
.00 00 00 21
.00 00 00 22
.0000 00 23
.00000024
.0000 00 25
.0000 00 26
.00000027
.00000028
.00000029
.0000002A
.0000002B
.0000002C
.000000 20
.00 00 00 2E
.00 00 00 2F

.00000
.00000
.00000
.00000
.00000

.00000 00088
.00000 00090
.00000 00093
.0000000095
.00000 00097
.00000 00 100
.00000 00102
.00000 00 104
.00000 00107
.00000 00 109

.0000 00 60
.00 00 00 61
.00 00 00 62
.00 00 00 63
.00 00 00 64
.00 00 00 65
.00 00 0066
.00000067
.00000068
.00000069
.0000006A
.00 00 00 6B
.00 00 00 6C
.00 00 00 60
.0000006E
.00 00 00 6F

.00000 00223
.00000 00225
.00000 00228
.00000 00230
.00000 00232
.00000 00235
.00000 00237
.00000 00239
.00000 00242
.00000 00244
.00000 00246
.00000 00249
.00000 00251
.00000 00253
.00000 00256
.00000 00258

.00 00 00
.00 00 00
.00 00 00
.0000 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.000000
.00 00 00

.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.00 00 00
.000000
.00 00 00
.000000

EO
El
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF

.00000 00521
.00000 00523
.00000 00526
.00000 00528
.00000 00530
.00000 00533
.00000 00535
.00000 00537
.00000 00540
.00000 00542
.00000 00544
.00000 00547
.00000 00549
.00000 00551
.00000 00554
.00000 00556

.00000030
.00000031
.00000032
.00000033
.00000034
.00000035
.00000036
.00000037
.00000038

.00000 00111
.00000 00114
.00000 00116
.00000 00118
.00000 00121
.00000 00 123
.00000 00125
.00000 00 128
.00000 00 130
.00000 00132
.00000 00 135
.00000 00137
.00000 00139
.00000 00142
.00000 00 144
.00000 00146

.00000070
.00000071
.00000072
.00000073
.00000074
.00000075
.00 00 00 76
.00000077
.00 00 00 78
.00 00 00 79
.00 00 00 7A
.00 0000 7B
.0000007C
.00000070
.000000 7E
.00 00 00 7F

.00000 00260
.00000 00263
.00000 00265
.00000 00267
.00000 00270
.00000 00272
.0000000274
.00000 00277
.00000 00279
.00000 00281
.00000 00284
.00000 00286
.00000 00288
.0000000291
.00000 00293
.00000 00295

.00 00 00 SO
.00 00 00 Bl
.00 00 00 B2
.000000 B3
.0000 0054
.00 00 00 B5
.000000 B6
.00 0000 B7
.00 00 00 B8
.0000 00 B9
.000000 BA
.000000 BB
.000000 BC
.000000 BO
.000000 BE
.000000 BF

.00 00 00
.00 00 00
.000000
.00 00 00
.000000
.00 00 00
.0000 00
.00 00 00
.000000
.00 00 00
.000000
.000000
.000000
.000000
.000000
.000000

FO
Fl
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FO
FE
FF

.00000 00558
.00000 00561
.00000 00563
.00000 00565
.00000 00568
.00000 00570
.0000000572
.00000 00575
.00000 00577
.00000 00579
.00000 00582
.00000 00584
.00000 00586
.00000 00589
.00000 00591
.00000 00593

10
11
12
13
14
15
16
17
18
19
lA
lB
lC
10
IE
IF

.00000039
.0000 00 3A
.0000003B
.00 00 00 3C
.00000030
.0000 00 3E
.0000003F

172

00074
00076
00079
00081
00083

.00000 00086

Appendix A

00 50
00 51
00 52
00 53
00 54
00 55
00 56
00 57
00 58
00 59
00 5A
00 5B
00 5C
00 50
00 5E
00 5F

00 186
00 188
00 190
00 193
00 195
00 197
00200
00202
00204
00207
00209
00211
00214
00216
00218
00221

AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF

00335
00337
00339
00342
00344
00346
00349
00351
00353
00356
00358
00360
00363
00365
00367
00370

.00000 00372
.0000000374
.'.00000 00377
.00000 00379
.00000 00381
.00000 00384
.00000 00386
.00000 00388
.00000 00391
.00000 00393
.00000 00395
.00000 00398
.00000 00400
.00000 00402
.00000 00405
.00000 00407
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000
.00000

00409
00412
00414
00416
0041 9
00421
00423
00426
00428
00430
00433
00435
00437
00440
00442
00444

00484
00486
00488
00491
00493
00495
00498
00500
00502
00505
00507
00509
00512
00514
00516
00519

TABLE OF POWERS OF TWO

MATHBIATEALCONSTANTS
Hexadecimal Value

Constant Decimal Value
1
2
..
8
16
32
6.(
128

0
1
2
3

1.0
0.5
0.25
0.125

..5

0.062
0.031
6 0.015
7 0.007

256 8 0.003
512 9 0.001
1 02.. 10 0.000
2048 11 0.000
4096
8 192
16 38-4.
32 768

12
13
1..
15

11'

,..-1

oJ;
5
25
625
812 5
906
953
976
-4.88

0.000 2....
0.000 122
0.000061
0.000 030

140
070
035
517

625
312 5
156 25
578 125

65
131
262
52..

536
on
1....
288

16
17
18
19

0.000
0.000
0.000
0.000

015
007
003
001

258 789 062 5
629 394 531 25
81 .. 697 265 625
907 a..s 632 812 5

1
2
..
8

048
097
19..
388

576
152
304
608

20
21
22
23

0.000
0.000
0.000
0.000

000
000
000
000

953
..76
238
119

16
33
67
134

m
5504
108
217

216
-4.32
86-4.
728

2..
25
26
27

0.000
0.000
0.000
0.000

000
000
000
000

059 6().4 6« n5
029 802 322 387
01 .. 901 161 193
007 ..SO 580 596

268 ..as ..56 28
536 870 912 2?
I 073 741 824 30
2 1..7 483 648 31

0.000
0.000
0.000
0.000

000
000
000
000

003
001
000
000

67..
837
418
209

n5
862
931
-4.65

316
158
579
289

290
645
322
661

.u>6
203
101
5SO

298
1..9
574
287

3.243f
0.517C

CIB7

I.n245 38509 05516

I.C58F

89IC

6AB9

In 11'

1.14412 98858 49.wo

1.2500

048F

2.71828 18284 59045

2.B7El

5163

0.36787 9....11 71 ....2

0.5E2D

5809

.Je

1.6-4.872 12707 00128

I.MI2

98E2

loglOe

0.43429 -4.4819 03252

0.6f2D

EC55

log2 e

1.....269

so.wa 88963

1.71504

7653

0.5n21 566-4.9 01533

0.93C"

67E..

25
125
562 5
281 25

3.1"159 26535 89793
0.31830 98861 83790

-1

InY

-0.504953 93129 816.(5

.J2

1...1..21 35623 73095

-0.8CAE 9BCI
1.6A09

In2

0.69314 71805 59945

O.Bln

17F8

logl02

0.30102 99956 63981

0.-4.010

-4.0..2

E668

.JfO

3.16227 76601 68379

3.298B

075C

Inl0

2.30258 40929 940-4.6

2.4076

3777

25
125
562 5
781 25
390
695
W
923

625
312 5
656 25
828 125

-4.61
230
615
307

91 ..
957
478
739

062
031
515
257

5
25
625
812 5

~ ~~ f!~: ~~ 32 ~.~ ~ ~ 232 !!~ ~3 ~53 ~~ ~~ ~ 25
8 589 934 592 33 0.000 000 000 116 415 321 826 934 814 453 125
17 179 869 Is.. 34 0.000 000 000 058 207 660 913 ·-4.67 407 226 562 5
34 359 738 368 35 0.000 000 000 029 103 830 456 733 703 613 281 25

36
37
38
39

0.000
0.000
0.000
0.000

000
000
000
000

014
007
003
001

551
275
637
818

915
957
978
989

228
614
807
403

366
183
091
545

806
903
951
475

625
312 5
156 25
078 125

n6
552
104
208

40
41
42
43

494
747
373
686

701
3SO
675
837

n2 928 237 915 039
886 46.( 118 957 519
443 232 059 478 759
721 616 029 739 379

1
2
4
8

099
199
398
796

511
023
0-4.6
093

0.000
0.000
0.000
0.000

000
000
000
000

909
..504
227
113

17
35
70
140

592
184
368
737

186 044 416 44 0.000
3n 088 832 45 0.000
744 In 66-4. -4.6 0.000
-4.88 355 328 47 0.000

000
000
000
000

056 s..a .. 18 860
028 421 709 430
014 210 8504 715
007 105 427 357

808
404
202
601

014
007
003
001

281
562
1 125
2 251

474
9..9
899
799

976
953
906
813

710 656 48
.(21 312 49
8Q 62.. so
685 248 51

0.000
0.000
0.000
0.000

000
000
000
000

003 552
001 ·n6
000 888
000 444

713
356
178
089

678
839
419
209

800
400
700
8SO

500 929
2SO 46.(
125232
062 616

599
199
398
797

627
2504
509
018

370
740
481
963

0.000
0.000
0.000
0.000

000
000
000
000

222
III
055
027

0....
022
511
755

604
302
lSI
575

925
-4.62
231
615

031
515
257
628

936 56 0.000 000 000 000

000

013 8n 787 807 814 456 755 295 395 851 135 253 906 25

..
9
18
36

S03
007
01 ..
028

n 057 594
I.... 115 188
288 230 376
576460752
I
2
4
9

851
425
712
856

6.u>
320
660
830

68 719 476 736
137 ..as 953 472
274 an 906 9....
5049 755 813 888

152
305
611
223

627
255
5 II
022

037 927
075 855
151 711
303.(23

921 504 606 8-4.6
843 009 213 693
686 018 .(27 387
3n 036 8504 n5

496
992
984
968

52
53
504
55

869
..34
717
858

308
6504
827
913

062
531
765
882

5
25
625
812 5

689 941
84-4. 970
422 485
711 242

.u>6
703
351
675

25
125
562 5
781 25

355
677
338
169

337
668
334
667

890
945
4n
236

621
810
905
452

625
312 5
656 25
328 125

OS4 n6 333618 16.( 062 5
OQ 363 166 809 082 031 25

021 181 583 404 541 015 625
510 590 791 702 270 S07 812 5

8n 57 0.000 000 000 000 000 006 938 893 903 907 228 377 6.(7 697 925 567 626 953 125
7.... 58 0.000 000 000 000 000 003 469 446 951 953614 188 823 848 962 783 813 476 562 5
-4.88 59 0.000 000 000 000 000 001 734 n3 475 976 S07 094 411 924 481 391 906 738 281 25
976
952
904
808

60
61
62
63

0.000
0.000
0.000
0.000

000
000
000
000

867
433
216
lOS

361
680
840
420

737
868
434
217

988
994
497
248

403
20 I
100
5SO

547
773
886
443

205
602
SOl
400

962
981
490
745

240
120
560
280

695
347
173
086

953
976
988
994

369
684
342
171

140
570
285
142

625
312 5
156 25
578 125

Appendix A

173

APPENDIX B. GLOSSARY OF SYMBOLIC TERMS
Term

Meaning

Term

Meaning

()

Contents of.

EHl

Effective halfword location - halfword location pointed to by effective virtual address of
an instruction for halfword- operation.

External interrupt group inhibit - bit
position 39 of PSWs. If set (=1), all
interrupt levels within this group are
inhibited.

ESA

Effective source address.

EVA

Effective virtual address - virtual address
value obtained as result of indirect addressing and/or indexing. This address value is
independent of the program's actual location
in main memory, and is final address value
before memory mapping is performed.

AND (logical product, where 0 n 0 = 0,
1 n 0 = 0, and 1 n 1 = 1).

o n 1 = 0,
u

OR (logical inclusive OR, where 0 u 0 = 0,
Ou 1 =1,1 uO=l, and 1 u 1 =1).

EOR (logical exclusive OR, where
0 = 0, 0 @ 1 = 1, 1 @ 0 = 1,
and 1 @ 1 = 0).

Fixed-point arithmetic trap mask-bit position 11 of PSWs. If set (=1), basic processor
traps to location X '43 1 after executing an
instruction causing fixed-point overflow; if
not set, basic processor does not trap.
CC

Condition code - 4-bit value (bit positions
labeled CC1, CC2, CC3, and CC4), established as part of the execution of most
i nstructi ons.

Effective word - 32-bit contents of effective
word location (EWl).

EWl

Counter interrupt group inhibit - bit position 37 of PSWs. If set (=1), all interrupt
levels within this group are inhibited.

Effective word location - word location
pointed to by effective virtual address of an
instruction for a word operation.

Floating normalize mode control - bit position 7 of PSWs. If not set, resul ts of floatingpoint additions and subtractions are to be
normalized; if set (=1), results are not
normalized.

Floating round mode control - bit position 4
of PSWs. If set (=1), basic processor rounds
floating-point results. If not set, results are
truncated.

Floating significance mode control - bit position 5 of PSWs. If set (=1), basic processor
traps to location X '44 1 when more than two
hexadecimal places of postnormalization
shifting are required for a floating-point addition or subtraction; if not set, no significance checking is performed.

Floating zero mode control - bit position 6
of the PSWs. If set (=1), basic processor
traps to location X'44' when either characteristic underflow or zero result occurs for
a floating-point multiplication or division;
if not set, characteristic underflow and zero
result are treated as normal conditions.

Effective byte - 8-bit contents of effective
byte location (EBl).

EBl

Effective byte location - byte location
pointed to by effective virtual address of an
i nstructi on for byte operati on.

Effective doubleword - 64-bit contents of
effective doubleword location (EDl).

EDl

Effective doubleword location - doubleword
location pointed to by effective virtual address of an instruction for a doubleword operation. If odd-numbered word location is
spec ifi ed, low-order bit of effecti ve address
field (bit position 31) is automatically forced
to O. Hence, odd-numbered word address
(referring to middle of doubleword) designates same doub!e\AJord as even-num'bered v{ord

address when used for a doubleword operation.
EH

174

Effective halfword - 16-bit contents of effective halfword location, or (EHl).

Appendix B

Term

Meaning

Term

Meaning

Instruction register - internal basic processor
register that holds instructions. obtained from
memory while they are being decoded.

Ref.
Add.
(cont. )

value for any subsequent address computations, memory mapping, or both computation
and mappi ng.

Rul

Odd register address value - register Ru1
is general register pointed to by value
obtained by logically ORing 0001 into
address for register R. Thus, if R fip.ld of
instruction contains even value, Rul = R + 1
and if R field contains odd value, Rul = R.

Source address.

Sign extension - some instructions operate on two operands of different lengths;
they are made equal in length by extending sign of shorter operand by required
number of bit positions. For positive operands, result of sign extension is highorder O·s prefixed to the operand; for negative operands, high-order ]Is are prefixed
to operand. Sign extension process is
performed after operand accessed from
memory and before operation called for
by Instruction code is performed.

SPD

Stack pointer doubleword - contains the
context (TSA, space count, word count,
and IS, TW inhibit bits) of the pushdown instruct ions.

TCC

Trap condition code - 4-bit value (bit
positions labeled TCC1, TCC2, TCC3,
and TCC4), established as part of trap
operati ons.

Trap-on-space inhibit bit - conditions pushdown stack limit trap for impending overflow
or underflow of space count.

TSA

Top-oF-stack address - pointer that points
to highest-numbered address of operand stack
i n push-down instructions.

Trap-on-wo{d inhibit bit - conditions pushdown stack limit trap For impending overflow or underFlow of word count.

Instruction address - 17-bit value that defines
virtual address of instruction immediately prior
to the time that it is executed.

I/O interrupt group inhibit - bit position 38
of the PSWs. If set (=1), all interrupt levels
within this group are inhibitect.

Numeric value of bits 8-11 of decimal instruction word (value of 0 is 16 bytes).

Mode altered - bit position 61 of PSWs. This
bit is set (=1) during master-protected mode of
operati on and duri ng rea I extended type of
addressing.

Memory map mode control - position 9 of PSWs.
When set (== 1), the memory map is in effec t.

Master/slave mode control - bit position 8 of
PSWs. When set (=1), basic processor is in slave
mode; when not set, basic processor may be in
master or. master-protected mode as determined
by bit 40.

PSWs

Program status words - collection of separate
registers and flip-flops treated as an internal
basic processor register to store and display
critical control information.

General register address value - 4-bit contents of bit positions 8-11 (R field) of instruction word, also expressed symbolically
as (1)8-11. In instruction descriptions,
register R is general register (of current register block) that corresponds to R field address value.

Register altered - bit position 60 of PSWs.
When trap occurs, this bit set (=1) when general register or memory location altered in
executi on of i nstructi on causi ng the trap.

Ref.
Add.

Reference address - contents of bi t positions 15-31 of instruction word, a 17-bit
Field capable of directly addressing any
general register in current register block (by
using a value in range 0-15) or any word in
ma in memory in address range 16 through
131,071. This address value is initial address

Appendjx B

175

Term

Meaning

Term

Meaning

Write key - bit positions 32, 33, 34,
and 35 of PSWs; they are evaluated by
the memory write-protect feature to determine accessibility of real memory by
current program.

if X f. 0, indexing is performed (after indirect
addressing if indirect addressing is called for)
with general register X in current register block.

176

Index register address value - 3-bit contents of bit positions 12-14 (X field) of
instruction word. In instruction word,
if X = 0, no indexing is performed;

Appendix B

(cont .)

X'n'

Hexadecimal qualifier - hexadecimal value
(n) is unsigned string of tiexad~cimal digits
(O through 9 and A through F) surrounded by
single quotation marks and preceded by the
qualifier "X" (for example, 7B0 16 is written
X'7BO'.

APPENDIX C. FAULT STATUS REGISTERS
Table C-1. Fault Status Registers
Bit
Position

Status Registers

Faults Detected By:

Basic Processor

MIOP

System Control
Processor

PFI

General register parity
error

Bus Check Fault
(BCF

Map or access - protec t reg i ster pari ty error

Cluster bus
parity error

Parity error on
processor bus

Control register parity
error

Control Check
Fault (CCF)

Cl uster bus pari ty error

Processor bus
parity error

Operation code
error

Interna I basi c processor
bus pari ty error

Control Memory
Fault (CMF)

Reserved

Unrecognized
operati on code

Reserved

Cluster bus parity error

CMF

Reserved

Processor-Detected
Fault flag (PDF)

MIE

Cluster bus sequence
check fault

Reserved

Memory parity error

Data/order
indicatort

Reserved

Memory Interface Error
(MIE)

Out/In i ndicator t

Reserved

Multiple error

Reserved

Processor interface
sequence .check fault

Control Memory
Fault (CMF)
address bi t 0

Reserved

Control Memory
Fault (CMF)
address bit 0

Reserved

Extended arithmetic
sequence check fault

CMF
address bi t 1

Reserved

CMF
address bit 1

Reserved

Basic processor
sequence check fault

CMF
address bi t 2

Reserved

CMF
address bi t 2

Reserved

Successfu I i nstructi on
retry

CMF
address bi t 3

Reserved

CMF
address bi t 3

Reserved

Control memory pari ty
error (BPE module)

CMF
address bit 4

Reserved

CMF
address bit 4

Reserved

Control memory parity
error (BPF module)

CMF
address bi t 5

Reserved

CMF
address bi t 5

Reserved

Control memory parity
error (BPG module)

CMF
address bi t 6

Reserved

CMF
address bit 6

Reserved

Control memory pari ty
error (BPH module)

CMF
address bi t 7

Reserved

CMF
address bi t 7

Reserved

II0

adapter

" Reserved

tThis is a 2-bit code indicating type of service call, as follows:
Bits
7

MIOP
Significance

Order In

Order Out

MIOP
Significance

Data In

Data Out

Bits

Appendix C

177

Table C-2. Memory Unit Status Register
Bit Position
0-21

178

Faults Detected by Memory Unit:
Fau It address snapshot

Reserved

Memory unit parity error

Storage module selection error

Address In parity error

Data In parity error

Write-lock memory storage parity error

Port selecti on error

Operation mode undefined

Control sequence check fault error

Multiple error

Appendix C

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