960129 9701C_s_732_733_ASR_KSR_Maintenance_Manual_Nov74 9701C S 732 733 ASR KSR Maintenance Manual Nov74
User Manual: 960129-9701C_s_732_733_ASR_KSR_Maintenance_Manual_Nov74
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siLENT 70f'Electronic Data Terminals
Models 732/733 ASR/KSR Maintenance Manual
•
MANUAL NO. 960129-9701, Rev. C
ISSUED 15 MARCH 1973
REVISED 15 NOVEMBER 1974
•
TEXAS INSTRUMENTS
INCORPORATED
Copyright 1975
By
Texas Instruments Incorporated
All Rights Reserved
PRINTED IN U.S.A.
The information and/or drawings set forth in this document and all rights in
and to inventions disclosed herein and patents which might be granted thereon
disclosing or employing the materials, methods, techniques or apparatus
described herein are the exclusive property of Texas Instruments Incorporated.
No disclosure of the information or drawings shall be made to any other person
or organization withouf the prior consent of Texas Instruments Incorporated.
ENGINEERING CHANGE NOTICE
DESCRIPTION
DATE
ECN
LEVEL
10-15-73
383372
C
Addition of options and accessories
11-28-73
388722
C
Update text and drawings in Appendixes
1-28-74
386150
B
Update drawings; delete drawings
6-1-74
389261
C
Add options and update drawings
11-15-74
399144
C
Update; delete obsolete material, add drawings
,"
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TABLE OF CONTENTS
(
Section
Page
Section
GENERAL DESCRIPTION
1-1 Scope of Manual . . . . . . . . . . . . . . 1-1
1-2 Equipment Description . . . . . . . . . . 1-1
1-2.1 Model 732 KSR . . . . . . . . . . . . . . 1-1
1-2.2 Model 733 KSR . . . . . . . . . . . . . . 1-1
1-2.3 Model 733 ASR . . . . . . . . . . . . . . 1-1
1-2.4 Model 732 ASR '" . . . . . . . . . . . 1-3
1-3 Optional Equipment . . . . . . . . . . . . 1-3
1-3.1 Answer-Back Memory . . . . . . . . . . 1-3
1-3.2 TTY Line Interface . . . . . . . . . . . 1-3
1-3.3 Modem Line Interface
(Originate or Answer Mode) ...... 1-5
1-3.4 Full ASCII Keyboard . . . . . . . . . . 1-5
1-3.5 Auto Device Control . . . . . . . . . . 1-5
1-3.6 Single-Cassette ASR . . . . . . . . . . . 1-5
1-3.7 Automatic Search Control . . . . . . . 1-5
1-3.B Remote Device Control . . . . . . . .. 1-5
1-3.9 1200-Baud Interface . . . . . . . . . . . 1-6
1-3.10 Dual Format . . . . . . . .
. 1-6
.1-6
1-3.11 Auto Answer Control (300b)
1-3.12 ASR Footpedal
. 1-7
1-3.13 Acoustic Coupler
. 1-7
1-4 Accessories
.1-7
1-4.1 Stand . . . . .
.1~7
II
Page
2-7.10 Auto Answer Control
2-B Accessories
2-B.1 Stand . . . . . . . .
III
EQUIPMENT INSTALLATION
2-1 General . . . . . . . . . . . . . . . . . . . . 2-1
2-2 Dimensions . . . . . . . . . . . . . . . . . . 2-1
2-3 Power Connections . . . . • . . . . . . . . 2-1
2-4 EIA Line Interface . . . . . . . . . . . . . 2-1
2-5 Paper Loading . . . . . . . . . . . . . . . . 2-1
2-6 Strappable Options . . . . . . . . . . . . . 2-1
2-6.1 End-of-Line Alarm . . . . . . . . . . . . 2-1
2-6.2 Playback Stop On Error . . . . . . . . 2-5
2-6.3 Baudot Character Set . . . . . . . . . . 2-5
2-6.4 ETX Record Initiate . . . . . . . . . . . 2-5
2-7 Options . . . . . . . . . . . . . . . . . . . . 2-5·
2-7.1 Answer-Back Memory . . . . . . . . . . 2-5
2-7.2 Auto Device Control . . . . . . . . . . 2-7
2-7.3 Modem Line Interface
2-7
2-7
2-7.4 Current Loop Line Interface
2-7.5 Uppercase/Lowercase Keyboard ... 2-7
2-7.6 Dual Format PC Cards . . . . . . . . 2-10
2-7.7 Automatic Search Control ...... 2-13
2-7.B Remote Device Control . . . . . . . . 2-13
2-7.9 1200-Baud Interface . . . . . . . . . , 2-13
iii
2-14
2-16
2-17
THEORY OF OPERATION
3-1 General
3-1
3-2 System Architecture . . . . . . . . . . . . 3-1
3-3 Power Supply . . . . . . . . . . . . . . . . 3-1
3-3.1 +33 Volt Unregulated Supply .... 3-11
3-3.2 +5 Volt Regulated Supply ...... 3-11
3-3.3 +12 Volt Regulated Supply ..... 3-13
3-3.4 -12V Regulated Supply . . . . . . . . 3-13
3-3.5 -S.6V Supply . . . . . . . . . . . . . . 3-13
3-3.6 Power-On Reset Circuit . . . . . . . . 3-13
3-4 Printer System . . . . . . . . . . . . . . . 3-14
3-4.1 Paper Drive Mechanism . . . . . . . . 3-14
3-4.2 Printer Drivers . . . . . . • . . . . . .. 3-14
3-4.3 Printer Control Logic . . . . . . . . . 3-16
3-4.4 Character Decoding,
ASCII/Baudot . . . . . . . . . . . . . . 3-17
3-4.5 Printhead • . . . . . . . . . . . . . . . . 3-17
3-5 Keyboards and Keyboard Interface . 3-30
3-5.1 Standard ASCII . . . . . . . . . . . . . 3-30
3-5.2 Uppercase/Lowercase ASCII
Keyboard . . . . . . . . . . . . . . . . . 3-34
3-5.3 Baudot Keyboard . . . . . . . . . . . 3-34
3-6 Transmit/Receive PC Cards
(EIA Interface) . . . . . . . . . . . . . . 3-34
3-6.1 ASCII Transmit/Receive PC Card
(300 Baud Maximum) . . . . . . . . . 3-34
3-6.2 Baudot Transmit/Receive
PC Card . . . . . . . . . . . . . . . . . . 3-47
3-7 Terminal Control . . . . . . . . . . . . . 3-51
3-7.1 KSR Terminal Control . . . . . . . . 3-51
3-7.2 ASR Terminal Control . . . . . . . . 3-51
3-B Cassette System . . . . . . . . . . . . . . 3-54
3-B.1 Record Control . . . . . . . . . . . . . 3-54
3-B.2 Playback Control . . . . . . . . . . .. 3-63
3-B.3 Motion Control . . . . . . . . . . . . . 3-69
3-B.4 Display Functions . . . . . . . . . . . 3-72
3-B.S Cassette Transport . . . . . . . . . . . 3-72
3-9 Optional Devices . . . . . . . . . . . . . 3-73
3-9.1 Line Interface . . . . . . . . . . . . . . 3-73
3-9.2 Answer-Back Memory . . . . . . . . . 3-91
3-9.3 Auto Device Control
PC Card . . . . . . . . . . . . . . . . . . 3-94
TABLE OF CONTENTS (Continued)
Section
Page
Section
3-9.4 ASCII 1200-Baud Receiver
PC Card . . . . . . . . . . . . . . . . . . 3-94
3-9.5 ASCII 1200-Baud Transmitter
PC Card . . . . . . . . . . . . . . . . . . 3-99
3-9.6 Auto Answer Control .......• 3-103
3-9.7 Automatic Search Control ..... 3-110
3-9.8 Remote Device Control . . . . . . . 3-115
3-126
3-9.9 Acoustic Coupler . . . . .
IV
V
BASIC EQUIPMENT PC CARDS
AND FUNCTIONS
4-1 General . . . . . . . . . . . . . . . . . . . .
4-2 KSR Unit . . . . . . . . . . . . . . . . . . .
4-2.1 Power Module Motherboard . . . . . .
4-2.2 Regulator/Amplifier PC Card .....
4-2.3 Control Regulator PC Card . . . . . .
4-2.4 Printer Code PC Card
(ASCII and Baudot) . . . . . . . . . . .
4-2.5 Printer Control . . . . . . . . . . . . . .
4-2.6 Terminal Control . . . . . . . . . . . . .
4-2.7 Transmit/Receive (ASCII or
Baudot Code) . . . . . . . . . . . . . . .
4-2.8 Printhead Interface . . . . . . . . . . .
4-3 ASR Module . . . . . . . . . . . . . . . . .
4-3.1 ASR Module Motherboard . . . . . . .
4-3.2 Display PC Card . . . . . . . . . . . . .
4-3.3 Motion Control .... ~........
4-3.4 Remote Cassette Control . . . . . . . .
4-3.5 Playback Control . . . . . . . . . . . . .
4-3.6 Record Buffer Control . . . . . . . . .
4-3.7 Tape Read/Write . . . . . . . . . . . . .
4-3.8 Record Control . . . . . . . . . . . . . .
MAINTENANCE
5-1 Preventive Maintenance . . . . . . . . . .
5-1.1 Printhead Cleaning . . . . . . . . . . . .
5-1.2 Paper Drive Roller Cleaning ......
5-1.3 Printhead Drive Mechanism
Cleaning . . . . . . . . . . . . . . . . . . .
Page
5-1.4 Cassette Transport Cleaning . . . . . . 5-3
5-2 Troubleshooting . . . . . . . . . . . . . . . 5-3
5-3 Adjustments . . . . . . . . . . . . . . . . . 5-3
5-3.1 Print Contrast . . . . . . . . . . . . . . . 5-3
5-3.2 Modem Level Adjustment . . . . . . . 5-3
5-3.3 Printer Subsystem Adjustments ... 5-7
5-4 Subassembly Removal and
Replacement . . . . . . . . . . . . . . . . . 5-7
5-4.1 Keyboard . . . . . . . . . . . . . . . . . . 5-7
5-4.2 Printhead . . . . . . . . . . . . . . . . . . . 5-9
5-4.3 Drive Assembly . . . . . . . . . . . . . . 5-9
5-4.4 Printhead Interface PC Card ..... 5-10
5-4.5 Plug-in PC Cards (Lower Unit) '" 5-10
5-4.6 Secondary Fuses . . . . . . . . . . . . 5-10
5-4.7 AC Power Assembly . . . . . . . . . . 5-11
5-4.8 Lower Unit Fan . . . . . . . . . . . .. 5-11
5-4.9 Power Module Assembly . . . . . . . 5-13
5-4.10 ASR Module Assembly
(Upper Unit) . . . . . . . . . . . . . . 5-13
5-4.11 Display Card Assembly . . . . . . . 5-14
5-4.12 Plug-in PC Cards (Upper Unit)
5-14
5-4.13 Cassette Transport . . . . . . . . . . 5-14
5-4.14 Upper Unit Fan . . . . . . . . . . . . 5-14
5-4.15 Motherboard (Upper Unit)
5-15
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-3
4-3
4-3
4-3
4-3
4-3
APPENDIX A
SIGNATURE LIST
APPENDlXB
ASSEMBLY DRAWINGS
AND PARTS LISTS
APPENDlXC
ELECTRICAL SCHEMATICS
AND LOGIC DIAGRAMS
5-1
5-1
5-1
5-1
iv
LIST OF ILLUSTRATIONS
Figure No.
1-2.1
1-2.2
1-2.3
1-2.4
1-2.5
2-1.1
2-2.1
2-3.1
2-4.1
2-5.1
2-7.1
2-7.2
2-7.3
2-7.4
2-7.5
(
2-7.6
2-7.7
2-8.1
2-8.2
3-2.1
3-2.2
3-2.3
3-2.4
3-2.5
3-2.6
3-2.7
3-2.8
3-3.1
(
3-3.2
3-3.3
Page
Figure No.
3-3.4
Model 732 KSR (Baudot Code) ....... 1-2
Model 733 KSR (ASCII Code) . . . . . . . . 1-2
Model 733 ASR (ASCII Code) . . . . . . . . 1-4
Model 732 ASR (Baudot Code) ....... 1-4
Model 733 Acoustic Coupler Option
...
. 1-8
Connector Block Diagram
3-3.5
3-3.6
3-4.1
3-4.2
PC Card Locations . . . . . . . . . . . . . . . . 2-2
Overall Dimensions (KSR/ASR) ....... 2-3
115 Vac and 230 Vac Terminal
Board Jumpers . . . . . . . . . . . . . . . . . . 2-3
Terminal External Connections ....... 2-4
Paper Loading . . . . . . . . . . . . . . . . . . . 2-4
Answer-Back Memory PC Card
Component Locations . . . . . . . . . . . . . 2-6
Teletypewriter Neutral Interface
Wiring Diagram . . . . . . . . . . . . . . . . . 2-12
Teletypewriter Polar Interface
Wiring Diagram . . . . . . . . . . . . . . . . . 2-12
Auto Answer Control Option
Installation . . . . . . . • . . . . . . . . . . . . 2-15
Acoustic Coupler Panel
Installation Details
2-17
Acoustic Coupler Panel
Cable Routing
. .
2-18
Tightening the Acoustic Coupler
Panel Attach Screws
. . .
2-18
Paper Winder Installation
2-20
Data Terminal Stand (Accessory)
2-20
3-4.3
3-4.4
3-4.5
3-4.6
3-4.7
3-4.8
3-4.9
3-4.10
3-5.1
3-5.2
3-5.3
3-5.4
3-5.5
ASR Data Terminal
System Architecture . . . . . . . . . . . . . . 3-2
Data Terminal Serial Data Bus
Timing Diagram . . . . . . . . . . . . . . . . . 3-3
Terminal Control Block Diagram ...... 3-4
Timing Diagram, Typical Data
Transmission via Data Bus . . . . . . . . . . . 3-5
Terminal Control Printer, and
Keyboard Block Diagram . . . . . . . . . . . 3-6
Terminal Control, Receiver,
Transmitter, and Line Interface
(up to 300 baud) . . . . . . . . . . . . . . . . . 3-7
Auxiliary 1 or 2 and
Terminal Control . . . . . . . . . . . . . . . . . 3-8
Terminal Control, Playback,
Record, and Display Panel . . . . . . . . . . . 3-9
Data Terminal Power
Supply Block Diagram . . . . . . . . . . . . 3-10
Waveform, +5 Volts at No Load ...... 3-12
Waveform, +5 Volts at
5-Amperes Load . . . . . . . . . . . . . . . . 3-12
3-5.6
3-5.7
3-5.8
3-5.9
3-5.10
3-5.11
3-5.12
3-5.13
3-5.14
3-5.15
v
Page
Waveform, +5 Volts at
100Amperes Load . . . . . . . . . . . . . . .
Waveform, +5 Volts at Current Limit
Power Reset (PWRRST-)
Sequence Waveform . . . . . . . . . . . . . .
Printer System Block Diagram .......
Printer Control Timing
Synchronization . . . . . . . . . . . . . . . .
Printer Control Timing Printing
in Columns 1, 4, etc. . . . . . . . . . . . . .
Printer Control Normal Carriage
Return Timing Diagram . . . . . . . . . . .
Printer Control Timing, Backspace
from Columns 4, 8, etc. . . . . . . . . . . .
Printer Control, Line Feed Timing
Diagram (Double Line Spacing) ......
Printer Decode Block Diagram .......
Printer Control Character
Decoding Flow chart . . . . . . . . . . . . .
Printer Control Character
Decoding Timing Diagram . . . . . . . . . .
Printhead Buffer Clear (PHBFRCLR)
Timing Diagram . . . . . . . . . . . . . . . .
Keyboard Interface Block
Diagram . . . . . • . . . . . • . . . . . . . . . .
Keyboard Interface State,
Flow Diagram . . . . . . . . . . . . . . . . . .
Timing Diagram Keyboard
Interface . . . . . . . . . . . . . . . . . . . . .
Keyboard Strobe Pulse . . . . . . . . . . . .
Standard ASCII Keyboard Layout
and Symbolization ... . . . . . . . . . . ..
Unshifted Characters,
Standard ASCII Keyboard . . . . . . . . ..
Shifted Characters,
Standard ASCII Keyboard . . . . . . . . . .
Control Characters,
Standard ASCII Keyboard . . . . . . . . . .
Shift and Control Characters,
Standard ASCII Keyboard . . . . . . . . . .
Full ASCII Keyboard
Symbolization . . . . . . . . . . . . . . . . .
Lowercase Characters,
Full ASCII Keyboard . . . . . . . . . . . . .
Shifted Characters,
Full ASCII Keyboard . . . . . . . . . . . . .
Control Characters,
Full ASCII Keyboard . . . . . . . . . . . . .
Baudot Keyboard . . . . . . . . . . . . . . .
Baudot Letter Mode
Keyboard Codes . . . . . . . . . . . . . . . .
3-12
3-12
3-13
3-15
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-29
3-31
3-32
3-33
3-30
3-35
3-35
3-36
3-36
3-37
3-37
3-38
3-38
3-39
3-40
3-40
LIST OF ILLUSTRATIONS {Continued)
./
3-6.1
3-6.2
3-6.3
3-6.4
3-6.5
3-6.6
3-6.7
3-6.8
3-6.9
3-7.1
3-7.2
3-8.1
3-8.2
3-8.3
3-8.4
3-8.5
3-8.6
3-8.7
3-8.8
3-8.9
3-8.10
3-8.11
3-8.12
3-8.13
3-8.14
3-8.15
3-8.16
ASCII/Baudot Transmit/Receive
PC Card Block Diagram . . . . . . . . . . .
ASCII Line Data Format . . . . . . . . . . .
ASCII Serial Receiver
Timing Diagram . . . . . . . . . . . . . . . .
ASCII Serial Receiver
TimingDiagram . . . . . . . . . . . . . . . .
ASCII System Clocks
Block Diagram . . . . . . . . . . . . . . . . .
Baudot Line Data Format ........•.
Baudot Serial Transmitter
Timing Diagram . . . . . . . . . . . . . . . .
Baudot Serial Receiver
Timing Diagram . . . . . . . . . . . . . . . .
Baudot System Clocks
Block Diagram . . . . . . . . . . . . . . . . .
Terminal Control System
Timing Diagram . . . . . . . . . . . . . . . .
Terminal Control
Block D~gram . . . . . . . . . . . . . . . ..
Cassette Subsystem Block Diagram ... .
Record Control Block Diagram ..... .
Record Control Flow Diagram ...... .
Record Memory Timing Diagram .... .
Tape Write Controller Flow Diagram .. .
Tape Write Controller
Timing Diagram . . . . . . . . . . . . . . . .
Playback Control Block Diagram
Playback Control Flow Chart ....... .
Tape Read Controller
Timing Diagram . . . . . . . . . . . . . . . .
Block of Data on Tape . . . . . . . . . . . .
Phase-Encoded (PE) Data
Timing Diagram . . . . . . . . . . . . . . . .
Flow Diagram of Functions Performed by
the Remote Cassette Control PC Card ..
Tape Cassette Motion Control
Flow Diagram . . . . . . . . . . . . . . . . . .
ASR Control and Display Panel ..... .
Read/Write Electronics
Block Diagram . . . . . . . . . . . . . . . . .
Motion Control and Deck Status
Block Diagram . . . . . . . . . . . . . . . . .
Page
Figure No.
Page
Figure No.
3-8.17
3-41
3-43
3-8.18
3-44
3-9.1
3-45
3-9.2
3-46
3-48
3-9.3
3-9.4
3-49
3-50
3-9.5
3-9.6
3-52
3-9.7
3-53
3-9.8
3-54
3-55
3-56
3-57
3-59
3-60
3-9.9
3-9.10
3-9.11
3-9.12
3-61
3-62
3-9.13
3-64
3-65
3-66
. 3-86
. 3-92
. 3-95
3-96
3-101
3-102
3-110
3-111
3-112
3-113
3-121
3-124
Printhead Drive Mechanism
Cleaning . . . . . . . . . . . . . . . . . . . . . . 5-2
Tape Cassette Transport
Cleaning Areas . . . . . . . . . . . . . . . . . . 5-5
Subassembly Removal and
Replacement Information . . . . . . . . . . . 5-8
Data Terminal (Rear View) . . . . . . . . . 5-12
ASR Upper Unit Removal and
Replacement (Front View) . . . . . . . . . 5-15
54.1
54.2
54.3
vi
. 3-79
5-1.1
5-1.2
3-74
3-76
PC Card Locations . . . . . . . . . . . . . . . . 4-2
3-68
3-72
3-75
4--1
3-66
3-70
3-71
Timing for a Typical Write/
Read-Reverse-Forward Sequence
Timing for a Typical
Fast-Forward/Fast-Reverse Sequence
Originate-Mode (TL) Modem
Functional Block Diagram . . . . . . . . .
Answer Mode (TH) Modem
Functional Block Diagram . . . . . . . . .
Answer-Back Memory
Diode Matrix . . . . . . . . . . . . . . . . .
Answer-Back Memory
Timing Diagram . . . . . . . . . . . . . . .
Answer-Back Memory Flow Chart
1200-Baud Transmitter PC
Card Block Diagram . . . . . . . . . . . . .
1200-Baud Transmitter PC Card
Input Section Timing Diagram ..... .
Auto Answer Control,
Functional Flow Diagram ......•..
Auto Search Control
Simplified Flow Chart . . . . . . . . . . .
Auto Search Control
Data Timing . . . . . . . . . . . . . . . . . .
Auto Search Control
Functional Flow Diagram . . . . . . . . .
Auto Search Control
Block Diagram . . . . . . . . . . . . . . . .
Remote Device Control
Timing Diagram . . . . . . . . . . . . . . .
(-
LIST OF TABLES
2-4.1
2-6.1
2-7.1
2-7.2(A)
2-7.2(B)
2-7.3
2-7.4
2-7.5
2-7.6
(
2-7.7
2-7.8
3-4.1
3-4.2
3-4.3
3-5.1
3·5.2
3-6.1
Table No.
Page
Table No.
EIA Interface Cable Pin Functions
(Cable 959372-0001) . . . . . . . . . . . . 2-5
PC Card Connections for
Code and Character Set . . . . . . . . . . 2-7
Answer-Back Memory PC Card
Switch Options . . . . . . . . . . . . . . . . 2-8
Auto Device Controller Enabling
Options (For Part No. 971481)
2-9
Auto Device Controller (Earlier
Model) Enabling Options
(Part No. 960891) . . . . . . . . . . . . . . 2-9
Phone Line (Modem) Cable Pin
Functions (Cable 959383-0001) .... 2-10
Current Loop (TTY) Interface
Cable Pin Functions
(Cable 959284-0001) . . . . . . . . . . . 2-10
Dual Format PC Cards Strappable
Option Enables . . . . . . . . . . . . . . . 2-11
300-Baud Auto Answer Control
Pin Assignments and Signal Names
for CBS-DAA Series Data Couplers
2-16
Pin Assignment for Optional Acoustic
. . . . . 2-19
Coupler Jumper Connector
Pin Assignments for Optional Acoustic
2-19
Coupler "Y" Connector
Printer Control Read Only
Memory Input/Output . . . . . . . . . .
ASCII Code System and
Character Set . . . . . . . . . . . . . . . .
Baudot Code System and
Character Set . . . . . . . . . . . . . . . .
Standard Keyboard Connector
Pin Assignments . . . . . . . . . . . . . .
Optional Numeric Keyboard
Connector p.in Assivnments . . . . . . .
3-9.1
3-9.2
3-9.3
3-9.4
3-9.5
3-9.6
3-9.7
3-9.8
3-9.9
3-9.10
3-9.11
3-9.12
3-9.13
3-18
3-9.14
3-27
3-28
5-1
3-34
5-2
3-34
Dual Format ASCII Transmit/Receive
Transmitter Data Format . . . . . . . 3-43
VII
Page
Answer-Back Memory PC
Card Switch Options . . . . . . . . . . . 3-93
Answer-Back Memory
State Equations . . . . . . . . . . . . . . . 3-94
Auto Device Control Enabling
Options (for Part No. 971481) ..... 3-98
Auto Device Controller (Earlier Model)
Enabling Options (Part No. 960891) . 3-98
1200 Baud, EIA Interface Cable,
Pin Functions . . . . . . . . . • . . . . . 3-100
Answer-Back Memory Trigger-Delay
Chart, Resistor Options . . . . . . . . 3-104
Auto Answer Control Interface
Selection Chart, Resistor Options .. 3-104
Automatic Disconnect and Automatic
Answer-Back Memory Triggering,
Resistor Options . . . . . . . . . . . . . 3-107
State Equations for Auto
Answer Control . . . . . . . . . . . . . . 3-107
Auto Answer Control Pin Assignments
with Bell 103 Data Set . . . . . . . . . 3-108
Auto Control Pin Assignments
with Bell Type-CBS Data
Access Arrangement . . . . . . . . . . . 3-108
RDC PC Card Switch
S2 Options . . . . . . . . . . . . . . . . . 3-118
Remote Device Control Code
Bits for ASR . . . . . . . . . . . . . . .. 3-118
Remote Device Control Status
Codes and Characters . . . . . . . . . . 3-123
Failure Analysis Chart,
ASR and KSR Models
5-4
Failure Analysis Chart,
ASR Models Only ............... 5-5
/
(
SECTION I
GENERAL DESCRIPTION
1-1 SCOPE OF MANUAL.
terminal, similar in function to conventional tape punch
data terminals. The TI 732 KSR is capable of transmitting,
receiving, and printing the Baudot code and character set at
switch-selectable speeds of 50, 75, or 100 baud via a
standard EIA line interface.
This manual describes preventive and corrective
maintenance procedures for the Silent 700@ KSR/ ASR
Electronic Data Terminals manufactured by the Digital
Systems Division of Texas Instruments Incorporated.
Information is presented herein for maintaining and
servicing the following Silent 700 models: 732 KSR, 732
ASR, 733 KSR, and 733 ASR.
(
The following options are available with the model 732
KSR:
The maintenance information in this manual is intended to
help service personnel solve minor maintenance problems in
the field and assist analysis of major troubles at regional TI
service centers. A general description of each model and
module of the 732/733 KSR/ASR Electronic Data
Terminal series is included in this manual along with
necessary interfacing information. A general theory of
operation for each terminal function (the PC cards perform
more than one function) and troubleshooting guide are also
included herein. A complete parts list and related
mechanical and electrical drawings are included in the
appendixes.
a.
Answer-back memory
b.
Teletype (TTY) interface.
1-2.2 MODEL 733 KSR. The model 733 KSR (see Figure
1-2.2) is an ASCII-coded, keyboard send/receive data
terminal, similar in function to conventional tape punch
data terminals. The TI 733 KSR is capable of transmitting,
receiving, and printing the ASCII code and character set at
switch-selectable speeds of 10, 15, or 30 characters per
second (CPS) via a standard EIA line interface.
The following options are available with the model 733
KSR:
1-2 EQUIPMENT DESCRIPTION.
Each Data Terminal is a self-contained local-controlled
and/or remote-controlled electronic data terminal designed
for use in a wide variety of telecommunications systems.
Silent electronic printing is achieved using a dot matrix on a
monolithic, solid-state print head which prints characters
across the page. The matrix is composed of separate
solid-state heating elements, each electronically controlled.
A voltage is applied to the proper character element,
transferring thermal energy to the heat-sensitive paper, thus
creating a visible image.
a.
Answer-back memory
b.
Auto answer control
c.
TTY line interface series
d.
Automatic device control (line-disconnect
function)
e.
Modem line interface
The Silent 700 KSR/ ASR Electronic Data Terminals can be
configured to meet a variety of applications. This versatility
is accomplished using modular design which permits
performance variation by adding the ASR Module
Assen.;'ly (top unit) and by inserting an appropriate printed
circuit (PC) card and keyboard into the basic terminal
subassembly. The basic terminal models available are the
732 KSR, 733 KSR, 732 ASR, and 733 ASR.
f.
Full (upper and lowercase) ASCII keyboard.
g.
Acoustic coupler.
1-2.3 MODEL 733 ASR. The model 733 ASR (see Figure
1-2.3) is an ASCII-coded automatic send/receive data
terminal, similar in function to conventional tape punch
data terminals. The TI 733 ASR is capable of transmitting,
receiving, printing, playing back (from tape), and recording
on tape the ASCII code and character set at
switch-selectable speeds of 10, 15, or 30 characters per
1-2.1 MODEL 732 KSR. The model 732 KSR (see Figure
1-2.1) is a Baudot-coded keyboard send/receive data
1-1
FIGURE 1-2.1. MODEL 732 KSR (BAUDOT CODE)
..
FIGURE 1-2.2. MODEL 733 KSR (ASCII CODE)
1-2
"
/
(/
second (CPS) via a standard EIA line interface. Functions
such as tape edit or high speed tape duplication are also
possible in the off-line (local) mode.
1-2.5 MODEL 732 RECEIVE ONLY (RO). The Model 732
RO Data Terminal is a Baudot-code, receive-only data
terminal. The 732 RO is capable of receiving and printing
the Baudot code and character set at switch-selectable data
rates of 50, 75, and 100 baud via a standard EIA line
interface. The Model 732 is functionally, physically, and
operationally equivalent to the Model 732 KSR, except the
RO Data Terminal has no keyboard, no ON/OFF LINE
switch, and the paper advance switch is located adjacent to
the ON/OFF LINE switch.
The following options are available with the model 733
ASR:
a.
Answer-back memory
b.
Auto answer control
c.
TTY line interface series
The following options are available for the 732 RO:
d.
e.
(
Modem line interface
a.
Answer-back memory
b.
TTY line interface series.
Full ASCII keybaord
f.
Automatic search control
g.
Automatic device control
h.
Remote device control
i.
Single - cassette ASR.
j.
1200 Baud
k.
Footpedal for the tape playhack
1-2.6 MODEL 733 RECEIVE ONLY (RO). The Model 733
RO is an ASCII-coded receive-only data terminal. The Tl
733 RO is capable of receiving and printing the ASCII code
and character set at switch-selectable data rates of 10, 15,
and 30 characters per second (CPS) via a standard EIA line
interface. The Model 733 is functionally, physically, and
operationally equivalent to the Model 733 KSR, except the
RO has no keyboard, no ON/OFF LINE switch, and the
paper advance switch is located adjacent to the ON/OFF
LINE switch.
1.
Acoustic coupler.
The following options are available for the Model 733 RO:
1-2.4 MODEL 732 ASR. The Model 732 ASR (see Figure
1-2.4) is a Baudot-coded, automatic send/receive data
terminal, similar in function to conventional tape punch
data terminals. The 732 ASR is capable of transmitting,
receiving, printing, playing back from tape and recording on
tape the Baudot code and character set at switch-selectable
speeds of 50, 75, or 100 baud via a standard EIA line
interface. Functions such as tape edit or high-speed tape
duplication are also possible in the off-line (local) mode.
The following options are available with the model 732
ASR:
..
a.
Answer-back memory
b.
TTY line interface series
c.
Single-cassette ASR.
a.
Answer-back memory
b.
Modem line interface (answer-mode only)
c.
Automatic answer control
d.
Automatic
function)
e.
TTY line interface series.
f.
Acoustic Coupler.
device
control
(line-disconnect
1-3 OPTIONAL EQUIPMENT .
1-3.1 ANSWER-BACK MEMORY. The Answer-Back
Memory provides up to 21 field-programmable, nonvolatile
characters. The Answer-Back Memory is activated by the
USASCII ENQ character or by depressing the HERE IS key
on the keyboard. Printing or recording of the memory
contents is a switch-selectable option.
1-3
/
FIGURE 1-2.3. MODEL 733 ASR (ASCII CODE)
FIGURE 1-2.4. MODEL 732 ASR (BAUDOT CODE)
1-4
1-3.7 AUTOMATIC SEARCH CONTROL. The optional
Automatic Search Control (ASC) provides the ASR with
capability to search a recorded tape cassette at high speed
for a predetermined record. The operator or remote device
(if used in conjunction with the optional Remote Device
Control) enters an activate code through the ASR
keyboard. In the case of a remote device, the activate code
is transmitted on the line. The ASC answers (local mode
only) with a line feed and a carriage return, after which the
operator or remote device enters into the ASC memory
from one to 16 printable USASCII characters which the
ASC uses to identify the searched-for record. The operator
then activates the appropriate tape cassette PLAYBACK
CONTROL switch to initiate the search, or the remote
device issues the appropriate code. The ASC searches the
tape cassette at speeds up to 324 characters per second (3.7
blocks per second). Upon locating the desired data blocks,
the ASC stops the tape and causes a paper advance (local
mode only). The operator or remote device then may
initiate a local or remote printout or recording of the
desired data.
1-3.2 TTY LINE INTERFACE. The TTY Line Interface
replaces the standard EIA interface.
1-3.2.1 Neutral Interface. TTY neutral interface signaling is
accomplished by opening and closing the circuit presented
to the terminal I/O connector. Nominal operating current i~
6eld-settable to either 60 rnA or 20 rnA.
1-3.2.2 Polar Interface. TTY polar interface signaling is
accomplished by alternately opening one circuit and closing
the other circuit presented to the terminal I/O connector. A
positive current in the external circuit represents a MARK
and a negative current represents a SPACE.
1-3.2.3 Computer Line Interface. Designed for computer
use, with this interface signaling is accomplished by opening
and closing the circuit presented to the I/O connector.
Nominal operating current is 13 rnA.
1-3.3 MODEM LINE. INTERFACE (ORIGINATE OR
ANSWER MODE). The Modem Line Interface, which
replaces the standard EIA Interface, is a low-speed modem
conforming to the requirements of the Bell Data Access
Arrangement central data terminal. It operates
asynchronously up to a maximum speed of 300 baud in
full-or half-duplex over a two-wire voice-grade line.
Signaling is accomplished by frequency shift keying (FSK).
The Automatic Search Control consists of the ASC
printed-circuit card (card slot A7), a motherboard-access PC
card (card slot A6), and a top access connector which
connects the two PC cards. When used with the optional
Automatic Device Control (TI Part No. 971481) or the
optional Remote Device Control, the motherboard-access
card is not needed.
1-3.4 .FULL ASCII KEYBOARD. The Full ASCII Keyboard
provides transmission of both uppercase and lowercase
characters fro.m the keyboard.
The ASC receives most operating signals from the
motherboard-access PC card or the Automatic Device
Control or the Remote Device Control, depending on which
one of the three PC cards are installed.
1-3.5 AUTOMATIC DEVICE CONTROL. When the
Automatic Device Control characters DCI, DC2 DC3 or
DC4 are received from the line or generated by the
terminal, the record and playback cassette units are
switched on or off as shown below:
DCl
DC2
DC3
DC4
(X-ON)
crAPE)
(X-OFF)
(l'-AJl.E1
1-3.8 REMOTE DEVICE CONTROL (ASR MODEL
ONLY). The Remote Device Control option allows a
remote device to change the functional operating modes of
the 733 ASR Data Terminal via data received from the
communication line. The following functions may be
controlled through this option:
Playback ON
Record ON
Playback OFF
. Record OFF
Activation by these characters in either transmit, receive, or
local modes is a selectable option. In the case of the
playback cassette reading DC3, one character after DC3 will
be played back before the playback cassette is switched off.
('
1-3.6 SINGLE-CASSETTE ASR. The ASR terminal is
optionally available without cassette-2 and associated
controls. Cassette-l retains its controls, indicators, and
capabilities. Terminal capabilities requiring simultaneous
operation of two cassettes are not available with the
single-cassette system.
1-5
1.
Playback ON
2.
Playback OFF
3.
Record ON
4.
Record OFF
5.
Automatic disconnect from the phone line
when used in conjunction with the Auto
Answer Control option (EOT)
6.
Rewind cassette 1
7.
Rewind cassette 2
8.
Load/FF cassette 1
9.
Load/FF cassette 2
10.
Cassette 1 in record mode (cassette 2 in
playback mode if dual cassette model)
11.
Cassette 1 in playback mode (cassette 2 in
record mode if dual cassette model)
12.
Block forward
13.
Block reverse
14.
Printer ON
15.
Printer OFF
16.
Automatic Device Control ON (items 1 - 4
above) on received data
17.
Automatic Device Control OFF (items 1 - 4
above) on received data
18.
Request status information
19.
Automatic Search Control cancel (when used in
conjunction with the ASC option)
-20.
1200-baud print local (when used in
conjunction with the planned 1200 baud auto
answer options).
21.
Footpedal option operation of the playback-on
function.
4.
1-3.9 1200-BAUD INTERFACE. The 1200-Baud Interface
option allows the 733 ASR to transmit and receive data at
rates of 10, 15, 30, and 120 characters per second (110,
150, 300, and 1200 baud, respectively). The data set
interface section of the 1200-Baud option generates and
accepts the necessary signals to operate with Bell System
Models 202C and 202D (or equivalent) data sets.
1-3.10 DUAL FORMAT. The Dual Format option enables
the Model 733 ASR to transmit and receive either 7 bits of
data (standard ASCII configuration) or 8 bits of data
(binary configuration).
The Dual Format option consists of four PC cards which
provide an additional strappable option to enable the ETX
control character to initiate the recording of a block of data
(only when operating in the standard ASCII configuration
and the TAPE FORMAT switch is in the CaNT position).
1-3.11 AUTO ANSWER CONTROL (300 BAUD). The
Auto Answer Control option (TI Part No. 960984) provides
a 300-baud Model 733 Data Terminal the capability to
automatically answer a call through the Bell System's direct
distance dialing (DDD) network. Two versions of the Auto
Answer Control option are available: one interfaces with a
Bell CBS data access arrangement (DAA) or equivalent; the
other version interfaces with a Bell 103A data set or
equivalent with auto answer control.
TI recommends using the Auto Answer Control option in
conjunction with both the Answer-Back Memory and the
Remote Device Control options or with the Auto Device
Control option.
The Auto Answer Control consists of a 6-foot EIA or
modem cable assembly, a PC card, and a display panel.
In addition, when status information is requested, the
status of the cassettes, record, playback, and printer is
transmitted by the terminal via a single ASCII character.
1-3.12 ASR FOOTPEDAL.
These functions provide the following typical applications:
1.
Data collection from an unattended terminal
2.
Data distribution to an unattended terminal
3.
Remote record search when used in
conjunction with the Automatic Search Control
option
Data distribution to any unattended terminal at
1200-baud line speed when used in conjunction
with the 1200 baud auto answer option.
NOTE
The data terminal must be equipped with
the optional Remote Device Control
(RDC) to enable use of the Footpedal.
Available for the Model 733 ASR Data Terminal is an
optional Footpedal (TI Part No. 973866) to permit
convenient remote triggering of ASR cassette tape
./
1-6
playback. The Footpedal is particularly useful to control
playback of format tapes. The ASR Footpedal option
consists of:
1.
A footswitch pedal with an integral deb ounce
circuit mounted on a PC card
2.
A 7-foot heavy-duty shielded cable
3.
A connector to mate the footpedal to the J2
connector at the rear of the 733 ASR Data
Terminal.
1-3.13 ACOUSTIC COUPLER. The optional Acoustic
Coupler (TI Part No. 969619) is available for the Models
733 ASR, KSR, and Receive-Only Data Terminals. The
Acoustic Coupler equips the data terminal to communicate
over voice-grade telephone networks at data rates up to 300
baud in full or half duplex mode. The Acoustic Coupler
operates over any standard Western Electric SOO-series type
telephone (or equivalent). The Acoustic Coupler is typically
3.
A connector jumper which plugs into the
communication interface connector (]1) at the
rear of the data terminal. Figure 1-2.Sa. is a
block diagram of a typical Acoustic Coupler
application.
4.
An optional "Y" connector enables use of the
data terminal with both the Acoustic Coupler
and a variety of other data sources, as shown in
Figure 1-2,Sb.
1-4.1 STAND. A terminal stand is available which securely
supports the terminal. The lower row of key tops are 29
inches from the floor. The stand provides at least 24 inches
of leg room from the bottom of the stand to the floor and
at least 14 inches of leg room from the front edge of the
terminal stand to the back of the stand. The stand weighs
approximately 45 pounds.
The Acoustic Coupler option consists of
1.
The electronic interface, mounted on a single
PC card which plugs into the PC card rack.
14 ACCESSORIES.
used to gain direct access to a computer timeshare system.
In operation, the telephone handset is placed in the
Acoustic Coupler muffs and the appropriate connecting
number is dialed on' the telephone.
('
2.
A telephone handset receiver panel with muffs
and interconnecting wiring
1-7
JUMPER PLUG
(TI PART NO. 973258'()()()1l
TIMESHARE SYSTEM
r-----------------,
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DATA TERMINAL
TIMESHARE
COMPUTER
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•. STANDARD (THROUGH) JUMPER CONNECTOR FOR ACOUSTIC COUPLER OPERATION
!
103 TYPE MQDEM
113 TYPE MODEM
CASSETTE RECORDER
X·Y RECORDER
VIDEO DISPLAY
EXTERNAL COMPUTER
MODEL 733
DATA TERMINAL
I
~
~
OTHER DATA TERMINAL
COMPUTER SYSTEM
CASSETTE RECORDER
DATA ACQUISITION SYSTEM
(OTHER DEVICES MAY
USE ACOUSTic COUPLER)
ACCESS TO
DATA TERMINAL
~.
j
ACCESS TO
ACOUSTIC
COUPLER
TRANSMISSION LINE
b. MODEL 733 OPTIONAL "Y" CONNECTOR,TYPICAL USES.
A 0000104
FIGURE 1-2,5, MODEL 733 ACOUSTIC COUPLER OPTION CONNECTOR BLOCK DIAGRAM
1-8
SECTION II
("~
EQUIPMENT INSTALLATION
2-1 GENERAL.
The Silent 700® Electronic Data Terminals
self-contained, requiring no auxiliary equipment
standard data terminal operation.
are
for
compatible 25-pin connector is provided at the end of the
6-foot cable. For pin assignments see Table 2-4.1.
2-5 PAPER LOADING.
After unpacking, visually inspect the data
terminal before applying power. Check
for obvious shipping damage. Open the
top cover and remove the PC card rack
cover. Check for foreign objects. Ensure
that all PC cards (see Figure 2-1.1) are
tightly plugged into their sockets and that
all connectors are' plugged into the
motherboard. Ascertain that the
keyboard cable is connected. Replace the
PC card rack cover (be sure the three tabs
at the rear are inserted into their mating
slots at the rear of the PC card rack) and
close the top cover. Check that all keyboard keys operate freely. Do not operate
the printer without paper on the platen
(see Paragraph 2-5).
The printer should never be operated
without paper on the platen (drive roller);
damage to both platen and printhead
could result.
The data terminal must be loaded with paper before
applying power. Load the paper as follows:
a.
Raise the terminal cover and rotate the window
back~ards (see Figure 2-5.1).
b.
Place a fresh roll of paper on the supply hubs,
ascertaining that the roll can rotate freely.
c.
Thread paper between the paper chute and the
drive roller as shown in Figure 2-5.1. Be surepaper is centered in the paper chute.
d.
Lower the window.
e.
Set the POWER switch ON and depress the
PAPER ADV key. Make sure paper is feeding
smooth and straight.
f.
Close the data terminal cover, ascertaining that
paper is fed through the slot in the cover.
2-2 DIMENSIONS.
The terminal should be located in an area where its air
inlets and outlets are unobstructed. Dimensions are shown
in Figure 2-2.1.
2-3 POWER CONNECtIONS.
The normal power comiection is 115 Vac, 50/60 Hz, three
wire. To use optional 230 Vac, 50/60 Hz, power, the
terminal must be r~wired as follows: (1) remove the card
rack cover and power assembly cover (Figure 2-1.1); (2)
remove the ju:1hpers between TB 1-2 and TB 1-3 and between
TBI-5 and TBI-6; (3) install a jumper between TBI-3 and
TBI-5 (see Figure 2-3.1). The power cord plug must be
changed; the new cord must meet UL and CSA standards.
Change fuse Fl to a 1.5A, 250V Slo Blo.
2-6 , STRAPPABLE OPTIONS.
2-6.1 END-OF-LINE ALARM. The end-of-line alarm can be
prevented from sounding automatically by removing R20
(10 ohms) by hand from connectors Jl and J2 on the
Printer COl\trol PC card. If this feature is wanted, hand
insert the 10-ohm resistor (R20) between J1 and J2 on the
Printer Control card (red tabbed card in slot A2 of the KSR
card rack). Removal of R20 will not inhibit the alarm from
sounding lip on receipt of the ASCII BEL character.'
2-4 EIA LINE INTERFACE.
The EIA line connection located at the rear of the data
terminal is an edge connector (see Figure 2-4.1).
A data set cable (Part No. 959372-0001) connects the data
terminal to the external data set. A standard RS232C
2-1
ASR MOTHERBOARD
XA-9
TAPE TRANSPORT 1
XA-7
RECORD CONTROL
XA-6
TAPE READ/WRITE
XA-5
RECORD BUFFER CONTROL
XA-4
PLAYBACK CONTROL
TAPE TRANSPORT 2
XA-8
XA-3 REMOTE CASSETTE CONTROL
XA-2
XA 1
MOTION CONTROL
DISPLAY
ASR MODULE ASSEMBLY (TOP UNIT) PC CARD LOCATIONS
--~-u~~::::::::::::::::::::~~='~~------rr-~~~~~~=L~~~--~~'--+-~ACPOWER~EMBLY
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A:eI~----------~r-+--f-CONTROL REGULATOR_.7
PRINTHEAD
INTERFACE
J
r--------,LJL"lL
n...1.L__...F+--+-POWER MODULE
r----l
MOTHERBOARD
--+---...
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KEYBOARD
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·RESERVED FOR OPTIONAL DEVICES
KSR (LOWER UNIT) PC CARD LOCATIONS
FIGURE 2-1.1. PC CARD LOCATIONS
2-2
14.62
(dimensions in inches)
FIGURE 2-2.1. OVERALL DIMENSIONS (KSR/ASR)
2
3
4
5
6
2
7
(a) 115V OPERATION
3
4
5
(b) 230V OPERATION
NOTE: TB1 is located under the Power Assembly Cover (shown in Figure 2-1.11. Fuse F1
(at rear of KSR near power cord exit) must be changed to a Slo-Blo 250V. 1.5A fuse 'for
230Voperation.
FIGURE 2-3.1. 115 Vac AND 230 Vac TERMINAL BOARD JUMPERS
2-3
6
7
ASRCOVER
FASTENER
ACFAN
AC LINE
FUSE (F1)
COMMUNICATION INTERFACE
CONNECTOR(J1)
FIGURE 2-4.1. TERMINAL EXTERNAL CONNECTIONS
,--
r-'l:-.
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ROLLER
DRIVE
ROLLER
-(PLATEN)
FIGURE 2-5.1. PAPER LOADING
2-4
-',
TABLE 2-4.1. EIA INTERFACE CABLE PIN FUNCTIONS 4
(CABLE 959372-0001)
Connector Pin Numbers
Terminal
6
7
8
9
10
A
F
H
K
I
Pin Function
Data Set
20
Data Terminal Ready 1
Signal Ground
Clear to Send2
Data Set Ready:;
Received Data
Protective Ground
Request to Send 1
Transmitted Data
Data Carrier Detect 5
7
5
6
3
1
4
2
8
NOTES:
1 Held to an ON condition by data terminal.
2Held to an ON condition by data set during transmission; required by terminal for transmission.
'Held to an ON condition when data set is operative; required for terminal operation.
4 All are used only with external modem.
5Held to an ON condition by m~dem when carrier is received; required by terminal for data reception.
2-6.2 PLAYBACK STOP ON ERROR. This option is
implemented by a strappable resistor or a pencil switch;
depending on which version of the Playback Control PC
card is installed in slot XA4 of the ASR upper unit.
2-6.4 ETX RECORD INITIATE [733 MODELS WITH
DUAL-FORMAT RECORD BUFFER CONTROL (PC
CARD 962285 ) ONLY J. If recording in the CONTinuous
tape format, upon receiving the ASCII end-of-text (ETX)
control character, the recording of a block of data will be
initiated. This permits the ETX control character to
perform the function of a carriage return. To enable this
strappable option, remove R8 (10 ohms) from between J3
and J4 on the Dual-Format Record Buffer PC card (slot
XA-5, ASR upper unit). Reinstall R8 as R13 between Jl
andJ2.
2-6.2.1 Standard Playback Control (PC Card 960905).
Upon detecting a read error when reading from the tape,
the Playback Controller will automatically stop if resistor
Rl (10 ohms) is connected between J3 and J4 on the
Playback Control card (slot 4 in the upper ASR unit). If Rl
is connected between Jl and J2 on this same card, the
controller will not stop upon detecting a read error; instead,
it will transmit the erroneous block to the terminal and
continue reading tape (if in continuous playback mode).
This resistor is easily pulled out of J3/J4 and inserted in
Jl/J2, or vice versa, by hand (no tools necessary).
2-7 OPTIONS_
2-7.1 ANSWER-BACK MEMORY. To gain this option,
install the Answer-Back Memory PC card (Part No.
960881-0001) in card slot A3. To program the
Answer-Back Memory, use the following procedure:
2-6.2.2 Optional Dual-Format Playback ,Control (PC Card
969453). The stop-on-error option on the Dual-Format
Playback Control is enabled by setting switch SI-4 to ON.
In this position the controller will automatically stop tape
playback upon detecting a read error. With switch S 14 in
the OFF position, the erroneous block of data will be
transmitted to the line.
2-6.3 BAUDOT CHARACfER SET. Code and character set
may be selected on the Printer Code PC card (slot 1 in KSR
unit) by installing Z23, R46, R47, R48, R49, and R53
according to Table 2-6.1
2-5
a.
For each character to be transmitted, remove
the corresponding diode from rows CR148
through CR165 of the Answer-Back Memory
PC card shown in Figure 2-7.1. These diodes are
located on the left-hand side of the board.
b.
To encode each character, remove diodes to
transmit a ZERO (space), or leave in diodes to
transmit a ONE (mark) in each bit position.
The first bits for each character are located in
the rightmost column of diodes; bit ,2 is the
next column left, etc, The first character is
encoded in the fust row of diodes; hence, CR64
corresponds to bit 4 of character 1.
•
A
-c:::l-*
Several switchable options are incorporated into the
Answer-Back Memory PC card. Table 2-7.1 defmes each
CRI66
9608810
NOTES:
1. SEE APPENDIX B FOR PARTS LIST AND ASSEMBLY DRAWING.
2. SEE APPENDIX C FOR SCHEMATIC.
3. SEE TABLE 2-7.1 FOR SWITCH OPTIONS
FIGURE 2-7.1. ANSWER-BACK MEMORY PC CARD COMPONENT LOCATIONS.
2-6
•
TABLE 2-6.1 PC CARD CONNEC.TIONS FOR CODE AND CHARACTER SET
PRINTER CODE
CARD ASSY. NO.
CODE AND CHARACTER SET
Z23
R46
R47
R48
R49
R53
959137-0001
ASCII
TI Part No.
959328-0001
10n
OPEN
10n
OPEN
OPEN
959137-0002
Baudot, U. S. Figures
TI Part No.
959329-0001
OPEN
10n
OPEN
10n
OPEN
TI Part No.
959329-0001
OPEN
10n
OPEN
OPEN
10n
Baudot, U. K. Figures
(Optional)
assignments are listed in Table 2-7.3. After connecting to
the Bell Syste~ ])AA line, adjust the modem level
(potentiometer R18) as specified by the Bell System, using
a meter which can measure modem output in dBm. Measure
directly between the two modem output lines.
switch on the card and its function. A switch is closed when
the 'dot' on the switch rOCKer arm is in the down position.
2-7.2 AurO DEVICE CONTROL. The Auto Device
Control option accommodes device control characters DC1,
DC2, DC3, and DC4. When these characters are received
from the line or generated by the terminal, the Record and
Playback cassette transports are turned on and off
according to the follmving:
DC1
DC2
DC3
DC4
(X-ON)
(TAPE)
(X-OFF)
("f1\Pfr)
2-7.4 CURRENT LOOP LINE INTERFACE (NEUTRAL,
POLAR AND COMPUfER). To add this option install the
Teletype (TTY) Interface PC card (TI Part No.
959171-000X) in line interface card slot A8. The data
terminal may now be connected to the communication line
using a cable assembly (TI Part No. 959384-0001). For
specific connections see Figures 2-7.1 and 2-7.2. For 60 rnA
operation,add R34 (150 ohm, 0.5 watt, 5 percent) to the
TIY Interface PC card. Pin assignments are listed in Table
2-7.4. The computer interface is connected as a neutral
interface.
Playback ON
Record ON
Playback OFF
Record OFF
When the playback transport reads DC3 during playback,
one character after DC3 will be read and transmitted before
the playback transport is turned off. Strappable options
allow any of these four code functions to be inhibited
during transmit, receive, or local operations.
2-7.5 UPPERCASE/LOWERCASE KEYBOARD. If the
uppercase/lowercase keyboard capability is desired, the
standard keyboard may be replaced with an
Uppercase/Lowercase Keyboard (TI Part No.
959326-0001). To convert, remove the four mounting
screws holding the keyboard to the keyboard brackets and
disconnect the keyboard cable. When the new keyboard is
installed and the cable is plugged in, be sure to remove the
protective foam cover taped to the semiconductor chip on
the bottom of the keyboard. Full ASCII and limited ASCII
keyboard arrangements are shown in Figures 3-5.5 through
3-5.13, in Section III of this manual.
To use this option, install the Auto Device Controller PC
card (TI Part No. 971481-0001) in card slot A6 (Figure
2-1.1) in the KSR unit. Strappable options permit the 733
ASR to respond to DC1, DC2, DC3, and DC4, as shown in
Table 2-7.2.
2·7.3 MODEM LINE INTERFACE. To incorporate this
option, install the Modem Line Interface PC card (TI Part
No. 960887-000X) iJ:l Line Interface card slot A8 (Figure
2-1.1). The data terminal may now be connected to the Bell
System Data Access Arrangement (DAA) with the phone
line cable assembly (TI Part No. 959383-0001). Pin
2-7
TABLE 2-7.1 ANSWER-BACK MEMORY PC CARD SWITCH OPTIONS
I
Switch S2 1
Function 3
1
Open to remove CR141 (bit 7 character 15) from matrix
2
Open to remove CR21 (bit 1 character 21) from matrix
3
Open to remove CR121 (bit 6 character 16) from matrix
4
Open to remove CRI01 (bit 5 character 17) from matrix
5
Open to remove CR81 (bit 4 character 18) from matrix
6
Open to remove CR61 (bit 3 character 19) from matrix
7
Switch SI
.
,
Open to remove CR41 (bit 2 character 20) from matrix
Function 3
1
Close for ASCII card; open for Baudot card
2
Close for ASCII card; open for Baudot card
3
Close for ASCII card; open for Baudot card
4
Open for ASCII card; close for Baudot card
5
Open for ASCII card; close for Baudot card
6
Close to disable printing of ABM contents at all times;
open to enable printing of ABM contents when on-line in half-duplex
7
Close to disable recording of ABM contents at all times;
open to enable recording of ABM contents when on-line in half-duplex
8
Close to put an ABM ON indication on pin 9 (future option);
open for NO indication (spare run on AUXIROF)
92
Close to ignore stop bit (continuous memory cycling)
open to stop ABM at stop bit programmed
1 and 4
Open both at same time to ignore triggering ABM from the line only
NOTES
1. Switch S2, all positions are normally closed; open only during unit test
2. Switch SI-9 is normally open; closed only during unit test
3. Switches are closed when the dot on the switch rocker arm is down
2-8
TABLE 2-7.2. (A) AUTOMATIC DEVICE CONTROL ENABLING OPTIONS
(For Part No. 971481)
Enabling Switch Section
Control Function
DC1orDC3
(Playback ON/OFF)
To Enable
When
Transmitting
To EnaWe
When
Receiving
To Enable
When in
Local
S2-1
(DC3 only)
S2-2
S2-3
S2-4
S2-5
DC2orDC4
(Record ON/OFF)
NOTE
Control characters DCI through DC4 function in the selected operating modes shown above. Close the appropriate switch
section on S2 to enable the corresponding function. When the ADC ON/OFF switch is in the OFF position, all ADC
functions are disabled except the ~utomatic disconnect on receipt of the EOT character (if that option is installed).
~TABLE
2-7.2. (B) AUTOMATIC DEVICE CONTROL (EARLIER MODEL) ENABLING OPTIONS
(Part No. 960891)
Control Function
To Enable
When
Transmitting
To Enable
When
Receiving
To Enable
In
Local
OCI
Resistor Between
(Playback ON)
Rl
JI-J2
R2
J3-J4
R3
J5-J6
DC2
Resistor Between
(Record ON)
R7
J13-JI4
R8
J15-J16
R9
J17-J18
DC3
Resistor Between
(Playback OFF)
R4
]7-J8
R5
J9-JI0
R6
J11-JI2
DC4
Resistor Between
(Record OFF)
RIO
J19-J20
Rl1
J21-]22
Rl2
J23-J24
All Resistors are 1OQ, .25W, 5%
2-9
TABLE 2-7.3 PHONE LINE (MODEM) CABLE PIN FUNCTIONS*
(CABLE 959383-0001)
Terminal Pin No.
Wire Color
at Spade Lug
Pin Function
C
3
Red
Black
Communication line
Communication line
*Used only with internal modem.
TABLE 2-7.4 CURRENT LOOP (TTY) INTERFACE CABLE PIN FUNCTIONS
(CABLE 959384-0001)
Terminal Pin No.
Wire Color
at Spade Lug
Pin Function
4
D
5
EO
White
Green
Black
Red
Teletype positive receiver input loop
Teletype receiver input loop
Teletype transmitter output loop
Teletype transmitter output loop
2-7.6 DUAL FORMAT PC CARDS. Four Dual-Format PC
cards are necessary:
1.
Dual-Format Transmit/Receive (TI Part No.
969455) slot A-5, KSR lower unit
2.
Dual-Format Playback Control (TI Part No.
969453) slot XA-4, ASR upper unit
3.
Dual-Format Record Buffer Control (TI Part
No. 962285) slot XA-5, ASR upper unit
4.
Dual-Format Tape Read/Write Control (TI Part
No. 969451) slot XA-6, ASR upper unit)
NOTE
The standard format without ETX option
renders the terminal functionally
equivalent to a terminal equipped with
the standard Record Buffer (TI Part No.
960903), Tape Read/Write Control
(962281), Playback Control (960905),
and the ASCII Transmit/Receive
(959135) PC cards.
The data terminal format options listed in Table 2-7..5 are
explained in the follo~g paragraphs.
With the Dual-Format PC cards in the terminal and the·
terminal TAPE FORMAT switch in the CONT position, the
terminal has the strappable capability to handle either
binary format data or standard format data with or without
ETX. These options and their straps are listed in Table
2-7.5.
2-7.6.1 CONTinuous Tape Format Position.
a.
2-10
Standard Format Without ETX Decode - Each
data character transmitted and received consists
of 7 bits with parity in the 8th bit. Each
TABLE 2-7.5. DUAL-FORMAT PC CARDS STRAPPABLE OPTION ENABLES
733 ASR/KSR
Terminal Format
Options
*Standard Format
Without
ETX
Dual Format
.liSCn Transmit
/Receive
(Part No. 969455)
OPTION ENABLES
Dual Format
Dual Format
Playback Control
Tape Read/Write
Control
(Part No. 969451)
(Part No. 969453)
Install R17
Between
J3&J4
Install Rl
Between
Jl &J2
SI-1
OFF
SI-2
ON
Standard Format
With
ETX
Install R17
Between
J3&J4
Install Rl
Between
Jl&J2
SI-1
OFF
SI-2
ON
Binary Format
(
Install R17
Between
Jl&J2
Install Rl
Between
J3&J4
SI-1
ON
SI-2
OFF
Dual Format
Record Buffer
(Part No. 962285)
Install R8
Between J3 & J4
Remove R9
Between J5 & J6
Remove R13
Between Jl & J2 .
Install R13
Between Jl & J2
Remove R9
Between J5 & J6
Remove R8
Between J3 & J4
Install R8
BetweenJ3 & J4
Install R9
Between J5 & J6
Remove R13
Between Jl & J2
*This option is used in the standard data terminal.
recorded block of data consists of 86
characters. Recording of a block out of the
buffer is initiated only when the 86th character
is entered (CONT tape format). All characters,
including carriage return, have a ZERO in the
8th bit.
b.
c.
Standard Format With ETX Decode - Each data
character transmitted and received consists of 7
bits with parity in the 8th bit. The recording of
a block is initiated either when the 86th
character is entered into the buffer, or when
the control character ETX is decoded. All
characters, except the control character ETX,
have a ZERO in the 8th bit.
Binary Format - Each data character
transmitted and received consists of 8 bits.
Each block consists of 86 characters. R~cording
of a block out of the buffer is initiated only
when the 86th character is entered in the
buffer. The entire 8-bit character field is
recorded.
2-7.6.2 LINE Tape Format Position. Each data character
transmitted and received consists of 7 bits with parity in
the 8th bit. Each block of data in the buffer is recorded on
tape either when the 86th character is entered, or when the
carriage return character is decoded. All characters except
the carriage return character have a ZERO in the 8th bit.
('
2-11
r
/"_ ..
SPADE LUGS
r
•
TELETYPE {
TO
RECEIVE
LOOP
I
:'-'HALF-DUPLEX OPERATION
I
TELETYPE
ro
SEND
LOOP
•
{
\.
"'-y'
I.
I
,..
-
I
I
CURRENT
SWITCH
«
I
I
)
y
- -,
I
J1E
RED
•
- - -
CURRENT
SENSOR
J15
BLACK
--
TTY INTERFACE CARD
l
J1-D
GREEN
4
I
«
«
«
WHITE
~
•
J1-4
-
L
-------
_.J
CABLE ASSY
959384
FIGURE 2-7.2. TELETYPEWRITER NEUTRAL INTERFACE WIRING DIAGRAM
TTY
RECEIVE
LINE
TTY
COMMON
r
SPADE LUGS
<-
J1 4
WHITE
O~-----~·
GREEN
/
-"'
J1 -D
-,
Or------~<'L
1-5
/
"'
TTY
SEND
LINE
1-E
'/
,",
I
CURRENT
SENSOR
1--
IT
I
I
I
~)
I
CURRENT
SWITCH
9
}
V
CABLE ASSY
959384
FIGURE 2-7.3. TELETYPEWRITER POLAR INTERFACE WIRING DIAGRAM
2-12
_--,
I
t
---'
2-7.9 1200-BAUD INTERFACE. The 1200-Baud Interface
option consists of a 1200-Baud Transmit PC card (slot A7
or AS, lower unit), a 1200-Baud Receive PC card (slot AS),
a EIA line interface connector cable, and a panel SPEED
switch. To install in the 733 ASR, proceed as follows.
2-7.7
AUfOMATIC SEARCH CONTROL (ASC).
Components required for installation of the ASC option
depend on which other options are installed in the 733
ASR. When used by itself for local operation, the ASC
requires the following items:
(1)
ASC printed-circuit card installed in ASR card
slot A7
(2)
Motherboard-access PC card installed in ASR
card slot A6
(3)
Top-access connector to connect the two above
PC cards.
(4)
14-ampere power supply, consisting of two PC
cards in card slot A9 and A10.
When the ASC is used in conjunction with the Remote
Device Control which permits remote operation of the
ASC, the motherboard-access PC card is not needed in card
slot A6. If the Auto Device Control option is already
installed, the motherboard-access PC card is not required in
card slot A6. But in all three cases the top access connector
(item 3 above) is required between the ASC PC card in slot
A7 and one of the other three PC cards in slot A6.
(
Remove the standard 300-Baud
Transmit/Receive PC card from lower unit PC
card rack slot AS (green ejector) and replace
with the 1200-Baud Receive PC card.
b.
Install the ] 200-Baud Transmit PC card in PC
card slot AS (gray dot) if used with an external
modem. If the 1200-Baud Modem PC card is
installed in slot AS, install the 1200-Baud
Transmit PC card in slot A7 (violet dot).
c.
Replace the standard 300-Baud EIA cable from
the terminal to the communications interface
(see Figure 2-4.1) with the 1200-baud EIA
cable.
d.
Gently pry up the black plastic panel which
covers the ON LINE/OFF and POWER switch,
and
(1)
Install the SPEED switch 'in the extra
hole in the switch bracket next to the
existing ON LINE switch. Mount the lock
washer and knurled nut atop the bracket
and the locking ring and hex nut on the
bottom.
(2)
Snap the new black POWER switch panel
into place.
(3)
Remove the connector which connects
the ON LINE switch to the keyboard.
Insert the new SPEED switch wires into
position S and position H of the
connector. Reconnect to the keyboard.
Install the two 14-ampere power supply PC cards into ASR
card slots A9 and AI0 (right row of PC card rack).
2-7.8 REMOTE DEVICE CONTROL. The Remote Device
Control option is contained entirely on one PC card. To
install, insert the RDC PC card into PC card slot A6 (Figure
2-1.1) of the KSR lower unit. Take special care when
installing the PC card to prevent accidently changing the
pencil switch (S2) positions.
Upon installation, ascertain that the
pencil switch (S2) positions on the RDC
PC card are set as follows for normal
operation:
("
a.
S2 Position
Normal State
1
2
3
4
S
6
7
ON
ON
ON
ON
ON
OFF
OFF
2-7.11 AUTO ANSWER CONTROL. The Auto Answer
Control (1'I Part No. 960984) is available in two versions.
One connects the data terminal to the communication line
using a Bell System type CBS data access arrangement
(DAA), or equivalent, which requires an internal modem in
the 733 Data Terminal. The second Auto Answer Control
version is designed for use with a Bell System 103A data set
or equivalent (no internal modem is required). A display
panel for the 733 Data Terminal is included with both
versions.
2-13
2-7.11.1 Installation of CBS-type DAA Auto Answer
Control. The Auto Answer version for use with CBS-type
DAA includes an Auto Answer PC card (TI Part No.
960885), a display panel (960165), a panel mounting
bracket (971420), a display panel cable (971556), an
internal modem PC card (960887 series), and a 300-baud
modem cable (971557). To install this Auto Answer
Control version, switch POWER OFF, unplug the power
cord, and proceed as follows.
a.
b.
Ascertain that the Auto Answer PC card
(960885) has resistor R2 (10 ohms) installed
between jumpers Jll and J13. Also check that
there is no resistor between J12 and J18.
Lift the terminal cover, remove the PC card
rack cover, and insert the Auto Answer PC card
(purple color ejector) into PC card slot A7
(purple color dot).
c.
Install the modem PC card (grey color ejector)
into PC card slot A8 (grey color dot).
d.
Install the display panel as follows. Refer to
Figure 2-7.4 for location of components.
(1)
(2)
Remove the two Power Supply PC cards
from PC card slots A9 and A10 (brown
and red ejectors).
- (5)
Loosely insert two 6-32 x 5/16 screws
into the front lower part of the display
panel. Place a drop of Loctite on the
threads.
(6)
Locate the display panel so that the two
6-32 screw heads insert into the keyhole
slots in the back of the POWER switch
box. Press down on the panel to seat the
screws into the narrow part of the
keyholes.
(7)
Insert a screwdriver through the holes in
the front of the POWER switch box and
tighten both 6-32 screws.
(8)
Insert and tighten two 4-40 x 1/4 screws
and two No. 4 flat washers through the
slots at the rear of the display panel and
into the panel bracket as shown in Figure
2-7.5.
(9)
Replace the two Power Supply PC cards
removed in step (1) above. Be sure the
colored PC card ejectors match the color
dots on the PC card rack.
(10)
Route the display panel cable (971556)
behind and below the keyboard and along
the left bottom of the data terminal base
as shown in Figure 2-7.4. Secure the
self-adhesive clamps to the bottom of the
data terminal case.
(11)
Plug connector PI onto the top of the
Auto Answer PC card (card slot A7,
purple ejector) installed in step b. above.
On the underside of the terminal cover,
use diagonal cutters to cut the four pins
which hold the blank option panel in
place. Cut close to the metal push-on
fasteners and pry off the fasteners with a
screwdriver. Then cut the four plastic
pins again, as short as possible to prevent
interference with the new panel.
(3)
Attach the panel mounting bracket to the
PC card rack front wall, using two 4-40 x
3/16 screws, two No.4 splitlock washers,
and two 4-40 hex nuts. Insert the screws
from inside the PC card rack. See Figure
2-7.5 for installation details.
(4)
Attach the display panel cable (971556)
connector P14 to the PC card on the
tUlderside of the panel as shown in Figure
2-7.4. The connector number should face
the underside of the panel.
e.
Connect the DAA cable leads to the CBS-DAA
type data coupler according to Table 2-7.6.
Connect the other end of the cable (PI) to the
Jl connector at the right rear of the 733 Data
Terminal. Secure the PI connector with the
screws provided.
f.
Replace the PC card rack cover, close the
terminal cover, and switch POWER to ON.
2-7.11.2 Installation of 103A-Type Data Sets. The Auto
Answer Control version for use with 103A-type data sets
includes an Auto Answer Control PC card (TJ Part No.
2-14
TABLE 2-7.6. 300-BAUD AUTO ANSWER CONTROL PIN ASSIGNMENTS AND SIGNAL NAMES
FOR CBS-DAA SERIES (OR EQUIVALENT) DATA COUPLERS*
Cable
Lead
Colors
DAA
Terminal
Marking
Signal
Name
Black
Brown
Red
Orange
Yellow
Green
White
SG
DA
OH
DT
DR
RI
CCT
Signal ground
Data access
Off hook
Data tip
Data ring
Ring indicator
Coupler cut through
*Used only with built-in internal Answer Modern option.
MODEM PC
(SLOTA8)
AUTO ANSWER
PC CARD
(SLOTA7)
(
SCR EW S,LOTS
DISPLAY PANEL
CABLE
UNDERSIDE
- - - O F DISPLAY
PANEL
SELF·ADHESIVE
CABLE CLAMP
; , . - - - DISPLAY PANEL
CABLE
DISPLAY PANEL
CABLE (ROUTE
UNDER KEYBOARD)
SCREWS
~POWER
SWITCH
ACCESS
BRACKET
FOR DISPLAY PANEL
INSTALLATION SCREWS)
FIGURE 2-7.4. AUTO ANSWER CONTROL OPTION INSTALLATION COMPONENTS
2-15
960885), a display panel (960165). a display panel cable
(971556), and a 300-baud Auto Answer cable (971555). To
install this Auto Answer Control version, switch POWER to
OFF, unplug the power cord, and proceed as follows.
a.
b.
Ascertain that the Auto Answer PC card
(960885) has resistor R1 (10 ohms) installed
between jumpers J12 andJ18. Also check that
there is no resistor between J11 andJ13.
Lift the terminal cover, remove the card rack
cover, and install the Auto Answer PC card
(gray color ejector) into PC card slot A8
(gray color dot).
c.
Install the display panel as described in step
2-7.11.1.d. above.
d.
Connect the 300-baud Auto Answer cable
(971555) by connecting the P13 connector to
the 103A-type data set. Connect the other end
(P1) to the J1 jack at the right rear of the 733
Data Terminal. Secure the P1 connector with
the screws supplied.
e.
To install the Acoustic Coupler option, ftrst check that all
the following parts are supplied:
(1)
Acoustic Coupler panel with attached cable and
connector (TI Part No. 969620)
(2)
Acoustic Coupler PC card assembly (TI Part
No. 974065)
(3)
Jumper connector (TI Part No. 973258) or
optional "Y" connector cable (TI Part No.
973254)
(4)
Panel mounting bracket (TI Part No. 971420)
(5)
Cable clamp, self-adhesive
(6)
Cable tie-down straps (2 each)
(7)
Four 4-40 x 5/16 screws, two 4-40 nuts, two
6-32 x 5/16 screws, six No.4 flat washers, and
four No.4 split-lock washers.
(8)
Loctite sealant.
Replace the PC card rack cover, close the
terminal cover, imd switch POWER to ON.
2-7.12 ASR FOOTPEDAL. The optional ASR Footpedal
assembly (TI Part No. 973866) controls tape playback
in conjunction with the Remote Device Control option.
The Footpedal option consists of a footswitch,
interconnecting shielded cable, and a connector marked P2.
To install the Footpedal, simply plug connector P2 into the
J2 receptacle (auxiliary interface connector) at the rear of
the Model 733 ASR Data Terminal (see Figure 2-4.1 for
location of J2). Place the footswitch at any convenient spot
on the floor.
Disconnect the data terminal ac power
cord from the wall outlet before
proceeding.
2-7.13 ACOUSTIC COUPLER. The Acoustic Coupler
option (TI Part No. 969619) equips the data terminal to
communicate with remote facilities through a standard
telephone desk set. The Acoustic Coupler option kit is
easily installed on the ASCII-code Models 733 ASR, KSR,
and RO Data Terminals. The kit is supplied with a jumper
connector for installation into the communication interface
connector U1) at the rear of the data terminal (see Figure
2-4.1). The jumper connector permits use of the terminal
only with the Acoustic Coupler communication interface.
An optional "Y" connector cable (TI Part No. 973254) is
available to equip the data terminal to communicate
through the Acoustic Coupler and a variety of other
communication interfaces.
a.
Lift the terminal cover and remove the blank
plastic option panel by cutting the four
protruding plastic pins with diagonal cutters.
Shear the pins as close to the metal retaining
nuts as possible and pry off the nuts with a
screwdriver.
b.
Remove the blank option panel from the pins
and again trim the pins as short as possible with
the diagonal cutters.
c.
Remove the PC card rack cover by loosening
the two retaining screws; fold the cover back
and lift the three tabs at the rear of the cover
clear of their slots in the PC card rack.
d.
Remove the two Power Supply PC cards
(brown and red ejectors) as follows:
/~\
"<--../'
2-16
(1)
Place thumbs under the PC card ejectors
and lift upward to dislodge the PC card.
(2)
Lift the PC cards up and out of their PC
card rack slots.
e.
Attach the panel mounting bracket to the PC
card rack front wall, using the hardware shown
in Figure 2-7.5.
NOTE
Some Model 733 Data Terminals are
delivered with the bracket installed.
440X 1/4 SCREW
}
NO.4 FLAT WASHER
2 PLACES
PC CARD RACK (FRONT WALLI
~
MOUNTING BRACKET
CAPTIVE NUT
_
~ NO.4 FLAT WASHER}
~
2 PLACES {
6/32 SCREW }
CAPTIVE NUT
4-40X 5/16 SCREW
4-40 HEX NUT
NO.4 SPLITLOCK WASHER
NO.4 FLAT WASHER----
2 PLACES
(NOT TO SCALEI
POWER SWITCH BRACKET
SPEAKER
FIGURE 2-7.5. ACOUSTIC COUPLER PANEL INSTALLATION DETAILS
2-17
2 PLACES
f.
g.
Install the cable attached to the Acoustic
Coupler panel, routing the cable between the
keyboard and the printhead cable bracket and
between the left side of the PC card rack and
the terminal cover, slide support as shown in
Figure 2-7.6.
(1)
Remove the protectiv!,: paper from the
self-adhesive cable clamp and press it on
the terminal base between the keyboard
and the printhead PC card brace as shown
in Figure 2-7.6.
(2)
Press the cable into the cable clamp slots.
(3)
Loosely attach the cable to the PC card
rack using a cable tie-down strap as
shown in Figure 2-7.6.
(1)
Press down on the front of the Acoustic
Coupler panel so the two loose 6-32 /- "screws seat in the narrow part of the \-..-/
keyhole slots in the POWER switch box.
(2)
Insert two 4-40 x 5/16 screws and two
No. 4 flat washers through the t'.vo slot!
in the upper part of the Acoustic Coupler
panel and into the mounting bracket
captive nut as shown in Figure 2-7.5.
Tighten the screws.
(3)
Insert a screwdriver through the front of
the POWER switch box as shown in
Figure 2-7.7 and tighten the two 6-32
3crews at the front part of the Acoustic
Coupler panel.
Add a drop of Loctite to the two 6-32 x 5/16
screws and start them into the captive nuts on
the front part of the Acoustic Coupler panel as
shown in Figure 2-7.5. Position the panel so
that the loose 6-32 screws insert into the two
keyhole slots at the rear of the POWER switch
box.
FIGURE 2-7.7. INSTALLING THE ACOUSTIC
COUPLER PANEL
h.
Install the Acoustic Coupler PC card (grey
ejector) into the left rear PC card slot. Press
down fIrmly on the PC card ejectors.
(1)
FIGURE 2-7.6. INSTALLING THE ACOUSTIC
COUPLER PANEL CABLE
2-18
Connect the Acoustic Coupler panel cable
(installed in step f. above) connector to
the left side of the Acoustic Coupler PC
card. Route the cable out the rear of the
PC card rack.
(2)
i.
.•
Tighten the loosely attached cable
tie-down strap installed in step f. (3)
above.
Reinstall the two Power Supply PC cards
removed in step d. above. Be sure the ejector
colors match the color dots on the PC card
rack. Press down firmly on the ejectors.
j.
Replace the PC card rack cover by inserting the
three ears on the rear of the cover into the
three slots at the top rear of the PC card rack.
Fold down the cover as if hinged and tighten
the two cover retaining screws.
k.
Install the desired connector into the
communication interface connector (Jl) at the
rear of the data terminal. Two connectors are
available:
•
An optional "Y" connector and cable (TI
Part No. 973254) permits a variety of
interface connections in addition to the
Acoustic Coupler. V-connector pin
assignments are listed in Table 2-7.8.
To install either connector into the data terminal, simply
plug the connector into the rightmost rear connector slot of
the data terminal; insert two 4-40 x 5/16 screws into the
connector ears and tighten to secure the connector.
TABLE 2-7.7.
PIN ASSIGNMENTS FOR ACOUSTIC COUPLER
JUMPER CONNECTOR (TI PART NO. 973258)
A jumper connector (TI Part No .
973258) supplied with the Acoustic
Coupler kit equips the terminal to
communicate only through the Acoustic
Coupler. Connector pin assignments are
listed in Table 2-7.7.
H to 1
10 to 4
8 to B
9 to C
K to 5
TABLE 2-7.8. PIN ASSIGNMENTS FOR ACOUSTIC COUPLER
OPTIONAL "Y" CONNECTOR (TI PART NO. 973254)
Y -Connector
Pin No.
Signal Source
Function
A
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Data Terminal
Acoustic Coupler
Acoustic Coupler
Acoustic Coupler
Acoustic Coupler
Acoustic Coupler
Acoustic Coupler
Acoustic Coupler
Protective Ground
Transmitted Data
Received Data
Clear-to-Send
Data-Set Ready
Signal Ground
Carrier Detect
Data-Terminal Ready
Request-to-Send
Transmitted Data
Received Data
Clear-to-Send
Data-Set Ready
Signal Ground
Carrier Detect
Protective Ground
H
10
8
9
7
K
6
F
1
4
B
C
3
5
A
2-19
External Connector
Pin No.
1
2
3
5
6
7
8
20
4
2
3
5
6
7
8
1
,
Cannon DP-25P
or Equivalent
I
I
)
1
Cannon DP-25S
or Equivalent
2-8.2 STAND. An optional stand (TI Part No.
960134-0001) available for the data terminals is shown in
Figure 2-8.2.
FIGURE 2-8.2. DATA TERMINAL STAND (ACCESSORY)
2-20
SECTION III
THEORY OF OPERATION
3-1 GENERAL.
within the terminal is essentially simultaneous and
independent. This simultaneous operation is illustrated in
Figure 3-2.2, which shows that the terminal control can
send a data character on the bus as rapidly as one every 88
fJ.sec. Conversely, the table in Figure 3-2.2 states that the
fastest line action period is one every 8.33 msec and the
fastest local action is one every 180 fJ.sec.
Five basic functions are performed within each KSR:
a.
Power supply (Paragraph 3-3)
b.
Printer (Paragraph 3-4)
c.
Keyboard and Interface (Paragraph 3-5) .
d.
Line Interface (Paragraph 3-6)
e.
Terminal control (Paragraph 3-7).
Since the terminal control can provide enables to t~e line
and local loops much faster than they require, both loops
experience negligible delays from terminal control
answering their requests to send data on the serial bus.
A better understanding of the terminal control will yield
easier comprehension of the system architecture. Figure
3-2.2 shows that the terminal control accepts requests from
each transmitting device. The terminal control also
monitors the status of each device on the data bus; i.e.,
whether the device is on-line, local, off, busy, etc. If more
than·one device has requested to transmit on the serial data
bus, the terminal control must decide which device has the
highest priority (see priority order in Figure 3-2.3), whether
that device is on-line or local, and if the line loop or local
loop is busy. For example, if the highest priority device
requesting to transmit to the serial data bus is in local and
the local loop is not busy, the terminal control will enable
the transmitting device (i.e., keyboard) and all receiving
devices (i.e., printer), if they too are in local, to the data
bus and the data on it during an enable time frame. The
local loop will then go busy for some time, and the terminal
control may then act upon any request it may have from a
line device (if the line loop is not busy). Figure 3-2.4 shows
a typical timing sequence when two devices simultaneously
request the data bus. Figures 3-2.5 through 3-2.8 show
some of the signals and data paths involved when terminal
control interfaces with the various devices on the serial data
bus.
AddiJ1g the ASR Module Assembly (upper unit), the data
terminal has five additional functions necessary for ASR
terminal operation:
.
(
a.
Record controller
b.
Playback controller
c.
Motion controller
d.
Display functions
e.
Cassette transport.
Each terminal function may be contained on one or more
printed circuit (PC) cards in the terminal. Therefore,
terminal functions, rather than terminal PC cards, are
described in this theory of operation. Frequent references
are made to Texas Instruments assembly and electrical
drawings contained in the appendixes to this manual.
3-2 SYSTEM ARCHITECTURE.
The data terminal architecture is arranged around a single,
serial data bus, a concept illustrated in Figure 3-2.1. The
bus is time-shared both by a line loop and local loop within
the terminal and by the devices within each loop. The
function of controlling which devices may use the serial
data bus, and during what times, is done by a terminal
control. Because of the high rate at which data is
transferred within the terminal on the data bus, and the
comparatively slow rate at which the devices on the bus can
react once they receive the data, operation of each loop
3-3 POWER SUPPLY.
A functional block diagram of the power supply is shown in
Figure 3-3.1. The supply provides voltages of +33V
unregulated, +5V regulated, +12V regulated, -5.6V
regulated and -12V regulated to the terminal. A power reset
is incorporated in the circuit to reset the terminal upon
power up or power failure.
3-1
EIA
r--
232C
LPHrONE
J
r-----1
I-I
II
I
I
MODEM
I
.:
PLAYBACK
UNIT
--,
L-..
J!
----1
EIA
LINE
INTERFACE
~
IV
hELETYPEWRITE I
LINE INTERFACE I
(POLAR OR
2
r-
NEUT~ALl- -
-Z:URRENT
LOOP
L_20/f~
J
-(."
SERIAL DATA BUS
r--L-l
I
I
'V
SERIAL
TRANSMIT RECEIVE
~
r-
11
KEYBOARD
CONTROL
LOGIC
PRINTER
CONTROL
LOGIC
'~L:Ri
I
I
IL _____ .JI
DEVICE
[
-l
rnA _
DISPLAY
PANEL
L~-u..J
'--
-u
tr'
I
I
I
AUXILIARY 2
DEVICE
I
I
L __ ., __ ...1I
I'! "
I
RECORD
UNIT
I
)
I-I
J
L._.....J
r==>
TERMINAL
CONTROL
STANDARD
OPTIONAL
CONTROL LINES TO
AND FROM TERMINAL
CONTROL
FIGURE 3-2.1. ASR DATA TERMINAL SYSTEM ARCHITEcruRE
r
'\
\
)
/'
l
\,
/
\,
~
,
:",,-,\
(";-
,/
TERMINAL CONTROL CYCLE
88 sec
--'
II - - - - - - - - - ~~~ 9.76 llsec
I
1-1
TERMINAL CONTROL
4
DECISION- MAKING
STATE
TERMINAL
CONTROL STATED
,
.•
Ii
SERIAL DATA
BUS CLOCK
(SCLK-)
~2.44
~
\.Isec
n
1
. I
I
l11
2
,---,
~
3
4
5
6
7
,---, ,---, ,---, ,---,
8
1
i
2
3
4
i r--'1 r--'1 ,---,
5
6
~ ~
7
8
r--'1 r--"'1
1._ _ _ _ __
I
r----:
I
STATUS ENABLE
I
I
1
- 1
I
1
I
I
, I
1-=-----:"'1-=---:-,=---:-11 =----:-,=----:-'1~II - I - I ""';"--:-,--:-,-=---~I=---:-1
1 B1 1 B2 1 B3
B4 1 B5 1 B6
B7 I B8
S1 1 S2 I S3
,
,
I
I
V>
~
I
I
,
I
~
DATA CHARACTER
(8-BITS)
I
I·
I
I
11 S4
1
II S5
I
II~___
11 SF
II S7
11 S8
II S9
I
I
1
I
9-BIT STATUS CHARACTER
i
I
-l
MAXIMUM REQUIRED TRANSMIT RATES
TO SERIAL DATA BUS
1.
2.
3.
4.
5.
6.
7.
2
1
DEVICE ENABLE
Y'
~
n
SERIAL RECEIVER/XMTTER
RECORD PRINT BUFFER
AUX. 2 (ANSWER-BACK)
1200 BAUD RECEIVER/XMITTER
KEYBOARD (REPEAT TO RECORD)
AUX. 1 (AUX. INPUT TO RECORD)
PLAYBACK (BUFFER TO ASC)
RATE
CPS'
30
33
30
120
1140
1140
5.5K
PERIOD
msec
33
30
33
8.33
0.88
0.88
0.18
51
S2
S3
54
S5
sa.
57
58
S9
RCBFFL
BOEOCA1BOEOCA2RERRORRFEEDKBDLOC
PRNLOC
PRNOFF
PNHRDY-
RECORD BUFFER FULL
CAS-1 NOT ATTHE END OF THE TAPE
CAS-2 NOT AT THE END OF THE TAPE
NO PLAYBACK ERROR
PLAYBACK NOT ON
KEYBOARD IN LOCAL
PRINTER IN LOCAL
PRINTER OFF
RECORDER NOT READY
• CPS = CHARACTERS PER SECOND
FIGURE 3-2.2. DATA TERMINAL SERIAL DATA BUS TIMING DIAGRAM
ENABLE TABLE
REQUEST TABLE
DEVICE
SIGNAL
LINE
RECEIVER
SRVREO
AUX.1
AUX 1 REO
AUX 2 REO
RDRREO ..
4
BUFREO
KBDREO
5
6
AUX.2
PLAYBACK
RECORD
KEYBOARD
1
2
SIGNAL'
DEVICE
P
~
~
I/"
6-BIT
REQUEST
REGISTER
~
PRIORITY
CONTROL
~
ENABLE
CIRCUIT
3
t..
LINE
RECEIVER
I/"
LINE
XMITTER .
, AUX.1
)
,AUX.2
PLAYBACK
RECORD
PRINTER
KEYBOARD
DISPLAY
PRIORITY - - "
ORDER
SRVENA
XMTENA
AUX1 ENAS
AUX1 ENAR
AUX2 ENAS
AUX2ENAR
RDRENA
RECENA
PRNENA
KBDENA
STAENA
l..>
.J,.
LINE/LOCAL/OFF
STATUSES OF
DEVICES
TIMING
CONTROL
TERMINAL
STATUS
CONTROL
SERIAL
DATA
BUSS
'1'
.('~
.('~
1----' SERIAL DATA BUS
CLOCK (SCLK)
~
BUSY' SIGNALS
(RDRCLK) MASTER SYSTEM CLOCK
L
204.8 kH2
DEVICE INHIBIT
SIGNALS
FIGURE 3-2.3. TERMINAL CONTROL BLOCK DIAGRAM
(~-)
':
)
(
~i
--i
TERMINAL
CONTROL
STATE
__...1
DEVICE-1
ENABLE
_ _......JI
I
-l
1
DATA BUS
DEVICE-2
REQUEST
I
I
L
I
I
I
I'
9.76~II
I
I
II
II
I
I
I
B1
I
B2
1
I
I
,sEC
*
I
B3
I'
•
~
I
II_
-B5
II
I
I
l
* I
0
' 10
I
I
10
L
u ul u,--I_I
,~o ,UO ,UO U U
10
I
·1
B8IlSEC
-------4I-~1 ~2.44~EC
I
I
,.,
1
____
DECISION MAKING STATE
r
J
Ul
)'
I- TERMINAL CONTROL
1
DEVICE-1
REQUEST
DATA BUS
CLOCK
~i
~,
I
)'
-B6
I ~
I~
,
0
,
I ~~:-----I
I
I
r:
______r----
DEVICE-2
ENABLE
0- DATA CLOCKED ONTO DATA BUS BY TRANSMITTING DEVICE
* - DATA CLOCKED INTO RECEIVING DEVICE
FIGURE 3-2.4. TIMING DIAGRAM, TYPICAL DATA TRANSMISSION VIA DATA BUS
B8
I
~-.
-
CHARACTER
DECODER
VSERIAL
DATA
BUS
PRINTHEADINTERFACE
PRINTHEAD
PRINTER CONTROL
PRINTING MECHANISM
-----
vrABlETO
RECEIVE A
CHARACTER
(PRNENA)
TAPE
(TPBKSP)
r----'
TAPE
(TPFWSP)
I
PAPER ADVANCE (KBPA)
PBUSY
~
a-
PRINTER REMOTE OFF (PRNROF)
PRINTER LINE/LOCAL/OFF STATUS
CONTROL
KEYBOARD LINE/LOCAL STATUS
Vv_
V R E O U E S T TO SEND A CHARACTER (KBDREO)
I
I
II
CONTROL
I
-----,
ANSMITIER I
_____
J
- AUX-:1 OR 1
I
_~U!-.!_J
r -----1
DISPLAY I
II'
PANEL
-,
I
~
I
.L _ _ _ _ _ ..J
ENABLE TO SEND A CHARACTER (KBDENA)
KEYBOARD ON (KBDON)
SPECIAL
KEYBOARD
INTERFACE
r_I
L_
PRINTER BUSY
TERMINAL
I
L ____ J
BREAK
~
RECORD
14-
MAIN KEYBOARD
KEYS
FIGURE 3-2.5. TERMINAL CONTROL PRINTER, AND KEYBOARD BLOCK DIAGRAM
I~'l
\
/
\
1'\
)
(
\
j
........
~,,
I
~I
,
I
)
/;
3 LINE SPEEDS
LOW
10
I I
MED
15
I
•
r - AUX.l
- - -,,
XMITTER INHIBIT (XMTINHI
I
L
HIGH
30
If
r----'
I
BREAK
i
•
SERIAL
RECEIVER
XMITTER
AND PARITY
GENERATOR
r----'
I
I
~
BELL CIRCUIT
I I
-
~
I
REQUEST TO SEND A
]
CHARACTER (SRVREQI
_l __ --,
I
ENABLE TO RECEIVE
A CHARACTER (XMTENA~
I
v-
L _ ] __ ~
r -
--,
I CURRENT LOOP
I
20mA OR BOrn A
r----'
I
caOO·800Hz
PWRCLK 51.2kHz
-,
"I
I
ENABLE TO SEND A
]
CHARACTER (SRVENAI
TTY LINE
INTERFACE
..J
KEYBOARD:
TO DEBOUNCE
TAPE AND
,
,
WeKEYS
I
L --::: ___ J
EIARS232C
~
LINE INTERFACE
r -
r - - - - ,,
BELLCLK 3.2 kHz
TIMING·SIGNAL
GENERATOR
-
MODEM
L __ .__
I
...J
--------1......L ____
CRYSTAL
CLOCK
.. I
KEY BOARD
L ____
1
HALF OR FULL
DUPLEX
___ ..J
TERMINAL
CONTROL
,
I
LINE BUSY
r----'
+5V SWITCHING
I
L ~G~L':T~ _ J
r----',
PNHCLK 12.8kHzl
'.
L
PRINTER
CONTROL
TIMING
'
I
...J
r- - --,
I
,RECORD, AUX1,
•
PLAYBACK,
'RDRCLK' MASTER SYSTEMIAUX2 KEYBOARDI
~~~~~~--~.
'
CLOCK (204.8kHz)
IINTERFACE,
I
,CHARACTER
I
,DECODER
I
L ____ J
L ____ .J
_
SERIAL DATA BUS
FIGURE 3-2.6. TERMINAL CONTROL, RECEIVER, TRANSMITTER, AND LINE INTERFACE (UP TO 300 baud)
INHIBIT·
Ai
...
TERMINAL
CONTROL
V
.oj
V-SERIAL
DATA.
BUS
r
,...
I
00
l
..-
I
CASSETTE
SUBSYSTEM
/ Itt-
REQUESTS
AND
ENABLES
INHIBIT
FUNCTIONS
TERMINAL CONTROL
INTERFACE
•
MASTER CONTROL
COMPUTER,
CARD READER,
ETC .
....
~
'\.. ~
"
'l1li
AUX·1/AUX·2
XMITTER AND
RECEIVER
•
•I'
~.
DATA BUS
MONITOR
*
-
REMOTE
CONTROL
OF
CASSETTE
SYSTEM
HIGH-SPEED
INTERFACE
TO OTHER
DEVICES
*
MESSAGE
GENERATOR
AUXILIARY DEVICE
TYPICAL OPTIONS USING AUX DEVICE:
1.
2.
3.
4.
5. *POLLING OR SELECTIVE CALLING SYSTEM
6. *HIGH-SPEED DATA INTERFACE
7. *FOR DECODING, ENCODING, OR CONVERTING 'CODES'.
AUTO DEVICE CONTROL
*AUTOMATIC SEARCH CONTROL
REMOTE CONTROL OF THE TERMINAL
ANSWER-BACK MEMORY
* APPLICABLE TO AUX. 1 ONLY
FIGURE 3·2.7. AUXILIARY lOR 2 AND TERMINAL CONTROL
("\
\
)
/
i
\
(
\
\.
/'
SERIAL DATA BUS
REQUEST TO SEND
A CHARACTER (BUFREQ)
RECORD BUSY
(RECENA)
RECORD
CONTROL
ENABLE TO RECEIVE
A CHARACTER OR
ENABLE TO SEND
A CHARACTER
ENABLE TO SEND STATUS
TERMINAL'
CONTROL
-
(RDRENA)
ENABLE TO SENO
A CHARACTER
DISPLAY
PANEL
PLAYBAGK
CONTROL
REQUEST TO SEND A CHARACTER
(RDRREQ)
FIGURE 3-2.8. TERMINAL CONTROL, PLAYBACK, RECORD, AND DISPLAY PANEL
3-9
PRIMARY
115/230Vac
50/60 Hz
TRANSFORMER
I - +33;- - . - -
25.6 kHzCLOCK
RECTIFIER
r:!:-;~
I
- --
RECTlFIER
25.6 kHz
CLOCK
MONITOR
-18V
+18V
>
~
+
c(
Z
+
1------------+
+12V
REGULATOR
5 VOLT REFERENCE
Cl
w
a:
...~.-~
5 VOLT REGULATOR
~
I -12V
.
: REGULATOR
GRD
+
(lC AND BOOST'TRANSISTOR)
(SWITCHING TYPE)
~
I
- sWiTCHING- - ,
REGULATOR
1
DISABLE
w
Z
w
w
Z
w
en
>
I'll
>
I'll
+
I
en
en
en
..
.-
+5 VOLT
r---~ OVERVOLTAGE
DETECT
AND
CROWBAR
-'-
'I +5 VOLT
CURRENT
LIMITER
I
I
I
w
!
>
>
+
I
I'll
.-
en
Z
w
en
>
It)
+
>
It)
~
+
+
FIGURE 3-3.1. DATA TERMINAL POWER SUPPLY BLOCK DIAGRAM
3-10
\.. -.
..
N
./
3-3.2.3 Regulator Amplifier. At the command of the
regulator driver, the 5V regulator amplifier switches the
33V supply to charge the 5V capacitor on the
motherboard. The 33V supply is switched by Ql, with Q2,
Q3, and Q4 supplying the drive current to turn on Q1. Q7
receives the command voltages from the regulator driver
and turns on the 33V switch by controlling switch drive
current transistors Q2, Q3, and Q4. Greater current loads
on the +SV supply cause the SV capacitor to discharge to a
lower value during the off time of the regulator driver
comparator. Therefore, during the comparator-on time, the
switch must stay on longer to recharge the capacitor back
to +S volts.
3-3.1 +33 Volt UNREGULATED SUPPLY. The positive 33
volts for the terminal is obtained directly from the ac
power module. The primary line voltage is passed through a
stepdown transformer and then rectified. The unfiltered 33
volts goes to the KSR motherboard via a nine-wire cable
which plugs into connector JI0 on the motherboard. A
capacitor and bleedoff resistor on the motherboard filters
the 33 volts before it goes to the rest of the terminal.
Schematics 959200 and 959188 in Appendix C show the
generation of the 33-volt unregulated supply.
3-3.2 +5 VOLT REGULATED SUPPLY. The +5 Volt
regulated supply employs a switching-type voltage
regulator. The supply consists of four major sections:
a.
+5 Volt reference
b.
The 5 Volt regulator driver
c.
5 Volt regulator amplifier
d.
Various failsafe circuits.
Figures 3-3.2 through 3-3.S show the switch output (input
to inductor Ll) under various 5V current loads. These
figures also show +5V output at loads to illustrate a
measure of +5V regulation. The 5 volt regulator amplifier is
shown on schematic 959181 (regulator/amplifier) in
Appendix C.
3-3.2.4 Failsafe Circuits. Three basic failsafe circuits are
associated with the +5V power supply: current limit,
overvoltage, and 25.6-kHz clock and clock detect (see
schematics 959181 and 959182). The current limit circuit
consists of Q5 and Q6 on the Regulator Amplifier PC card
(schematic 959181) and Q16 on the Control Regulator PC
card (schematic 959182). When R11 on the Regulator
Amplifier PC card senses too much current (IR drop), Q6
turns on Q5, Q5 turns on Q16 (Control/Regulator PC card),
and Q16 turns off the regulator drive to the33V switch.
The current limit should be approximately 12 amps for the
+5V supply. The overvoltage circuit consists of diode
CR14, CR15, Q14, Q22, and Q23 on the Control/Regulator
card (schematic 959182) and SCRI on the motherboard
(schematic 959188).
3-3.2.1 Reference. The +5V reference and auxiliary supplies
the reference voltage for the +5V switching regulator, the
headlift switching regulator, and the limited +5V needed
for logic devices on the Control Regulator PC card. The +5
Volt reference and auxiliary is diagrammed on schematic
959182 (control/regulator PC card in Appendix C). The
+5V reference is obtained from the +18V unregulated
supply using integrated circuit (IC) voltage regulator AR3.
The output voltage of the reference supply (5.1±.02V) is
determined by resistor R27 which is selected at unit test.
Transistor Q4 acts as a current booster for the Ie voltage
regulator (AR3).
("
3-3.2.2 Regulator Driver. The 5V regulator driver uses a
voltage comparator (AR4) to compare the +5V output with
the reference voltage supplied by the +5V reference supply.
A 25.6-kHz clock supplies the switching frequency which
holds the comparator off for approximately two-thirds the
clock period and allows the comparator to operate for
approximately one-third the clock period (period ::::: 40p
sec). When the comparator is operating, if the +5V output
does not match the +5V reference input to the comparator,
the regulator will supply a drive voltage to the amplifier
switch via Q17. When the +5V output again matches the
+5V reference, the regulator will turn off the drive to the
amplifier switch. The greater the +5V current load, the
longer the regulator drive to the amplifier switch will stay
on. Q21 and CR6 help power the regulator driver during
power UP to prevent it from latching up while power is
coming up. A drawing of the +5V regulator driver is shown
on schematic 959182 (control/regulator) in Appendix C.
When the +5V output voltage rises to approximately 5.5
volts, Q18 will turn on sufficiently to trigger the SCR on
the motherboard and cause Q22 and Q23 to disable the
regulator driver via CR15. When the SCR triggers the +5V
output bus is shorted to ground by the SCR The actual
+5V output will then drop zero volts until the terminal
power is switched off'and then back on. The 25.6 kHz
clock detect circuit consists of Z2, Q19, Q15, and Q20 on
the Control/Regulator PC card (schematic 959182). As long
as the 25.6-kHz clock is present, a retriggerable oneshot
(Z2) is continually triggered. The op-eshot output Qkeeps
Q19 on"and the oneshot output Q keeps Q20 off. As long
as Q19 is on, Q15 is off, and the regulator driver is enabled.
Since Q20 is kept off, the motor drivers remain enabled and
no terminal power reset (PWRRST -) occurs. If at anytime
the 25.6-kHz clock is lost, the +5V regulator driver will be
disabled, the motor drivers will be disabled, and a terminal
3-11
35 (±10)
v
T1
5 (±0.5)
~-------T3------~~
v
------T-0.8 (±0.2) V
'
Tt =7 (±ll11SEC
NOTES: A. + 5 V OUTPUT (PIN 20) SHOULD BE 5.15 (±O.05) V.
T2 = 12 t±2) llSEC
T3=37 (±5) llSEC
B. SWITCHING WAVEFORM INTO INDUCTOR L1
SHOULD APPEAR AS ABOVE.
WAVEFORM, + 5 VOLTS AT NO LOAD
FIGURE 3-3.2.
r
30 (±10) V
120 -Hz RIPPLE
T2
j+-T1
-1.2 1±0.2) V
T1 = 10 (±2) lJSEC
NOTES: A. + 5V OUTPUT (PIN 20) SHOULD BE 5.00 (- 0.05, + O. 15) V.
T2 = 37 (±5) lJSEC
B. SWITCHING WAVEFORM INTO INDUCTOR L1
SHOULD APPEAR AS SHOWN ABOVE.
FIGURE 3-3.3. WAVEFORM, + 5 VOLTS AT 5-AMPERESLOAD
30 (±10) V
-1.2 1±0.2)V
FT' . +.......-T2--+1·11
...
__
=12 1±2) llSEC
T2 =35 1±5) lJSEC
T1
NOTES: A. TEST + 5V OUTPUT (PIN 20) SHOULD BE 4.9 (-0.1, +0.25) V.
B. SWITCHING WAVEFORM INTO INDUCTOR L1
SHOULD APPEAR AS ABOVE.
FIGURE 3-3.4. WAVEFORM, + 5 VOLTS AT 10-AMPERES LOAD
00 1±10) V
1_
------'~
T1+I~~
T2~~1
~
--
T1 = 8 (±2) lJSEC
T2
=39 (±5) lJSEC
NOTES: A. + 5V OUTPUT (PIN 20) SHOULD BE 3.0 (±0.5) V.
B. SWITCHING WAVEFORM INTO L1
SHOULD APPEAR AS ABOVE.
C. LOAD IS 0.25 ohm.
FIGURE 3-3.5. WAVEFORM, +5 VOLTS AT CURRENT LIMIT
3-12
.'---/.
APPLYING THE FOLLOWING PULSE TO POS33VUNFIL (PIN 7) ...
15V
___
~~ !-----2S·:------,·~1,~.;":"',-----.il"'ll..
I
I
SHOULD YIELD THE FOLLOWING RESET PULSE AT PWRRST-(PIN 35):
I..,
2 SEC -----;~~I
I
k-T1~.
J
I
(
I
T1 = 600 (±100) msec
i /~
V<111S~C
I"I
~I
I
5V
I
~
!I ,T2
I..
'":"',-------
-,
T2<5 msec
FIGURE 3-3.6. POWER RESET (PWRRST-) SEQUENCE WAVEFORM
(
power reset will occur. A clock circuit, located on the
Control/Regulator PC card (schematic 959182), provides
the 25.6-kHz clock used by the switching regulators. It
consists of a free running multivibrator and a divide-by-two
flipflop which are synched to the system power clock
(PWRCLK). If at anytime the PWRCLK (51.2-kHz) is lost,
the switching regulators will still have a clock,
approximately 25.6-kHz after passing through the
divide-by-two flipflop (Z1).
3-3.5 -5.6V SUPPLY. A -5.6V supply provided is used only
by the voltage comparators of the various switching
regulators. The -5.6V supply, located on the
Control/Regulator card (schematic 959182), consists of
zener diode CR9 and filter capacitor C26. Current from the
supply is limited to a few milliamperes.
3-3.6 POWER-ON RESET CIRCUIT. A power-on reset
circuit on the control/regulator PC card (schematic
959182) holds the terminal in a reset state during power up
and resets the terminal when a momentary power failure
occurs. Three field effect transistors (Q12, Q13, and Q14)
hold the power reset bus (PWRRST -) at ground during a
power up until turned off by Qll and Q24. Qll is turned
on by Q10 which is controlled by a voltage dependent on
an RC time constant set by R28 and C17 Momentary
power failures are detected by Q8 which then turns off.
When Q8 turns off, Q9 goes on and shorts C17 to ground,
turning off Q10 and causing the power reset bus to be
grounded by the three field effect transistors, Q12, Q13,
and Q14. When the power failure ends and power is
reapplied to the terminal, Q8 again goes on and Q9 goes
off. C17 again charges through R28; approximately 600
msec later, the power reset bus (PWRRST-) again is
removed from ground. A typical power reset sequence
waveform is shown in Figure 3-3.6.
3-3.3 +12 VOLT REGULATED SUPPLY. The +12 volt
regulated supply is located on the control/regulator PC card
(schematic 959182). It consists ofIC voltage-regulator AR1
and two current-booster transistors Q2 and Q1. The IC
voltage regulator transforms the +18V unregulated supply
to a +12V regulated supply with an approximate 2.5-amp
current limit.
3-3.4 -12V REGULATED SUPPLY. The -12 volt regulated
supply, located on the Control/Regulator PC card
(schematic 959182), consists of integrated circuit (IC)
voltage regulator AR2 and current booster transistor Q3.
The IC voltage regulator transforms the -18V unregulated
supply to a -12V regulated supply with an approximate 500
rnA current limit.
3-13
3-4 PRINTER SYSTEM.
card (slot AI0; see schematic 959181). The head step
motor drivers and paper step motor drivers, (Al and A2 on
schematic 959181) are nearly identical circuits (e.g., inputs
and outputs are different). Each set of motor phase drivers
(three per set) utilizes the same type switching regulator
used by the +5V power supply. The Printer Control PC card
(slot A2; see schematic 959175) provides the input signals
(commands) telling each driver when to institute an action.
When the head or paper motor drivers receive a signal
telling them a motor phase to step to (e.g., HPHA, HPHB,
HPHC, PPHSA, PPHSB, PPHSC) and giving them the
command to step (HPC, PACA), comparators AIARl or
A2ARl tum on the appropriate motor phase driver
transistor (Ql, Q4, Q7) during the comparator-on time
allowed by the switching regulator 25.6 kHz switch clock.
During the comparator-on time, the comparator (AR1)
compares the input reference voltage from the Printer
Control PC card with the voltage across R2 produced by
the current flowing through a motor phase. When the
current in a motor phase produces sufficient voltage, the
comparator (HR1) turns off and stops the drive to the
motor phases, and this reduces the motor torque. The
object of the input commands (HPC, PACA) is to keep the
current through the motor phases constant (via the
switching regulator), producing a constant number of
ampere turns, and thus a constant force to step (accelerate
and decelerate) the motors. When either the head step
driver or the paper step driver is not in the process of
moving the head or paper, respectively, the drives keep a
"holding current" in one motor phase winding to keep the
motor shafts from moving inadvertently. The amount of
holding current is also controlled by the switching regulator
via comparator ARl and is determined by the input signals
(HPC, PACA) from the Terminal Control PC card.
Transistor QI0 (collector) in both Al and A2 should be
switching (between OV and 5V) at all times except during a
power reset.
The printer consists of seven major parts:
a.
Paper drive mechanism
b.
Printer drivers
c.
Printer control logic
d.
character decoding
e.
Printhead
f.
Printhead interface
g.
Printhead compensation circuit.
The printer drivers are located on the Regulator/ Amplifier
PC card (slot AI0), the printer control logic on the Printer
Control PC card (slot A2), the character decoding on the
Code PC card (slot Al), the printhead interface on the
Printer Code PC card (slot Al on the code card), and the
printhead compensation circuit also on Code PC card (slot
Al). A block diagram of the printer system is shown in
Figure 3-4.1.
3-4.1 PAPER DRIVE MECHANISM. The paper drive
mechanism feeds the printer paper and moves the printhead
to printout information fed to the terminal. Major
components include:
a.
The head stepping motor
b.
Paper advance motor
c.
Head lift solenoid
d.
Margin limit switch.
The head lift solenoid driver is also a switching-type
regulator similar to both motor driver regulators. It
provides current to the head lift solenoid to lift the
printhead during a carriage return or paper advance. The
input signal (command) to ImtIate the head lift
(LIFTHEAD) is- provided by the printer control PC card.
Comparator AR1, during the comparator-on time allowed
by the switching clock (25.6 kHz), compares the input
reference voltage (LIFTHEAD) with the voltage across R30
produced by the current flowing in the head lift solenoid.
When the current in the solenoid produces sufficient
voltage, the comparator (AR1) turns off the drive to the
solenoid to maintain solenoid current at the proper value.
When the head lift signal (LIFTHEAD) is not present, R16
Adjustments for head lift, head damping, and head return
speed are described in Section V.
3-4.2 PRINTER DRIVERS. Three driver groups control the
motion of the printer mechanism:
a.
Head step motor drivers
b.
Paper step motor drivers
c.
Head lift solenoid driver.
All three drives are located on the Regulator/Amplifier PC
3-14
SERIAL BUS
INPUT
CHARACTER
DECODING
.----~
PRINTHEAD
COMPENSATION
PRINTER
CONTROL
LOGIC
1-------PRINTHEAD
BUFFER
PRINTER
DRIVERS
PRINTHEAD
I
I
MECHAN ISM
SENSORS
AND MOTORS
I
I
c
FIGURE 3-4.1. PRINTER SYSTEM BLOCK DIAGRAM
3-15
commands from the keyboard discrete function
(unencoded) keys.
injects sufficient current to the comparator to ensure that it
remains in the off state; therefore, no current is provided to
the head lift solenoid. The collector of Q13 should switch
(between SV and 33V) only when the LIFTHEAD signal is
present.
,-/
..
c.
Automatic carriage return generator InItiates
line feed and carriage return if a print command
is received while the printhead is at the right
margin.
d.
Character timer - counts down the 12.8-kHz
clock to time each character period in S-msec
increments (character period is defined as the
time required to perform a space, backspace, or
print operation: 30 msec). Line feed is
performed in one or two character periods,
depending on whether single or double line
spacing is selected. Note that the printer
control character period is independent of the
terminal communication rate.
3-4.3 PRINTER CONTROL LOGIC. The Printer Control
PC card (see Figure 2-1.1) contains logic and analog
circuitry to control the following printer subsystem
functions.
a.
Stepping the printhead to the right (print or
space)
b.
Stepping the printhead to the left (backspace)
c.
Slewing the printhead to the left margin
(carriage return)
d.
Advancing paper (line feed)
e.
Lifting the printhead during paper advance and
carriage return
f.
Sounding the end-of-line warning.
All command inputs are inhibited while the
character timer is counting.
e.
The character decode circuitry of the Printer Code PC card
and the keyboard TAPE, TAPE,and PAPER ADV keys
provide command inputs to the Printer Control. Basic
timing signals are provided by the Transmit/Receive PC
card clock dividers. Limit switches and position sensors on
the drive mechanism assembly provide status and feedback
control signal input.
---- -
f.
Synchronizing register - synchronizes input
commands to. the 12.8-kHz clock and starts the
character period and carriage return timers as
required. Associated gating inhibits invalid
commands (e.g., carriage return or backspace
when the printhead is at the left margin).
g.
Column counter and decoder - stores and
controls the printhead position. The counter
counts up (module 3) to 81 as the head steps to
the right and down to 0 as the head moves to
the left during backspace or carriage return.
The counter is cleared to zero whenever the
printhead is at the left margin. Decoder outputs
select the head stepping motor phases to be
energized, enable the end-of-line alarm, initiate
the automatic carriage return from the right
margin, and enable operation of the carriage
return brake. An input/output list for the
Printer Control provides output signals to the Regulator
Amplifier stepping motor and solenoid drivers and to the
printhead compensation and bell circuits of the Code PC
card. It also supplies "busy" signal outputs to the Terminal
Control.
3-4.3.1 Functional Blocks. The Printer Control consists of
the following functional blocks.
a.
Synchronous input register - accepts carriage
return, line feed, backspace and print/no-print
commands from the printer code character
decoder.
b.
Asynchronous input register accepts space
(~), backspace (~), and paper advance
(simultaneous line feed and carriage return)
3-16
Carriage return timer - counts down the
BOO-kHz clock to provide a "busy" delay
during execution of carriage return. The print
command and all asynchronous command
inputs are inhibited during the carriage return
delay. The delay terminates 190 msec after
initiation of carriage return or 10 msec after the
printhead reaches the left margin (e.g., after
power turn on or an equipment malfunction),
whichever is greater.
I--~'
printer control read-only-memory is shown in
Table 3-4.1.
h.
i.
3-4.3.2 Printer Control Timing Diagrams. Timing diagrams
for various printer control functions are shown in Figures
3-4.2 through 3-4.6.
Damping controller - provides closed loop
control of printhead deceleration when
stepping to the right or left to minimize
acoustic noise and settling time. When triggered
by a position sensor on the stepping motor
assembly, a monostable momentarily applies
power to the lagging phase of the stepping
motor to develop the required retrotorque.
3-4.4 CHARACTER DECODING, ASCII/BAUDOT. The
printer decode block diagram is shown in Figure 3-4.7.
When a printer enable is detected, a flipflop is set to allow
the system clock (SCLK) to clock data on the data bus into
the data buffer. When the data has been clocked in, the
SCLK is disabled and the pattern counter is enabled. The
pattern counter clocks the pattern from the MOS character
generator, and counts the number of patterns sent to the
printhead buffer/driver. If the first pattern is a ONE, the
character is a control character so the pattern is also
clocked to the control decode. Printer control monitors the
flipflop which tells if the character is a print character or a
control character. When the printer decode tells the printer
control to 'GO', printer control either prints the character
in the printhead buffer/driver, or does the control function
in the control decode register.
Carriage return controller - receives pulses (rom
a second position sensor (tachometer) on the
head stepping motor and synchronizes them to
the 12.8kHz clock to drive the column counter
during carriage return. The sensor pulses are
phased so that the head stepping motor is
operated in a slewing (continuous rotation)
rather than a controlled (stepping) mode. When
the printhead has returned to column 12, the
controller switches the column counter clock
from the leading to the trailing edge of the
tachometer pulse which then begins to
decelerate the printhead.
For ASCII operation, resistors R46 and R48 are installed;
resistors R47, R49, and R53 are left open; and the ASCII
character generator is used. For Baudot operation the
Baudot character generator is used, resistor R47 is installed,
and resistors R46 and R48 are left out. For Baudot U.S.
figures, R49 is also installed, and R53 is open. For Baudot
U.K. figures, R53 is installed, and R49 is open.
The controller also checks for the absence of
tachometer pulses which indicate premature
stopping of the printhead. When this occurs the
controller enters a "failsafe" mode, reducing
power and supplying clocks at 20-msec intervals
to return the printhead to the left margin.
Failsafe carriage return is initiated
automatically when power is switched on.
(
A flow chart for the character decoding is shown in Figure
3-4.8, and a timing diagram is shown in Figure 3-4.9. The
ASCII code set is listed in Table 3-4.2, and the Baudot code
set is listed in Table 3-4.3.
j.
Carriage return brake controller - provides
closed-loop control of printhead deceleration as
the head approaches the left margin,
maintaining carriage return time and acoustic
noise within specified limits independent of
friction, temperature, and line voltage
variations. The controller operates by
integrating tachometer pulses, comparing the
resulting voltage to a reference ramp voltage,
and applying retrotorque current to the
stepping motor when the difference exceeds a
preset limit.
3-4.5 PRINTHEAD. The printhead consists of a matrix of
35 (5 x 7) separate elements and a diode on a monolithic
chip. The chip is mounted on a heatsink and is connected
to the Printhead Interface PC card with a flat cable
connected to a PC board. Mounted on this board are the
balance, slow, and fast resistors used by the printhead
compensation circuit. The printhead is 'controlled by
switching both (1) base drive to each elemen t and (2) print
voltage to the entire head (PVOLT). The diode voltage on
the chip varies with temperature, and the compensation
circuit uses this voltage to control print voltage (PVOLT).
The balance, slow, and fast resistors are used to match the
printhead characteristics to the compensation circuit.
k.
Paper feed counter - controls power to the
paper advance motor phases. Paper is advanced
one line each time the counter cycles through
its three-state sequence, sequentially energizing
the three stepping motor phases.
3-4.5.1 Printhead Interface. The Printhead Interface PC
card takes serial data (35 bits) from the character generator
and converts it to parallel data with five 7 -bit shift registers.
Each bit is then buffered and sent to the proper element
(base lead) on the printhead.
3-17
TABLE 3-4.1 PRINTER CONTROL READ ONLY MEMORY INPUT/OUTPUT
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ALL
OUTPUTS
INPUTS
BINARY SELECT
WORD
A
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
B
L
L
H
H
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
X
C
L
L
L
L
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
X
D
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
E
L
.L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
ENABLE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
(L = low, H = high) .
3-18
YI
H
L
L
L
L
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
H
I I !
Y2
L
H
L
L
H
L
L
L
H
L
L
L
H
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
Y3
L
L
H
L
H
L
L
L
L
H
L
H
H
L
L
H
L
L
L
L
H
H
L
H
L
L
L
L
H
H
L
H
y4
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
1 Ys I
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
H
L
H
H
H
L
H
H
H
y6
L
H
L
L
H
L
L
L
L
H
L
L
L
H
L
L
H
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
1 Y, I Y s
L
L
H
L
L
H
L
H
L
L
L
H
L
L
L
L
L
H
L
L
L
H
L
L
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
.,.....\
~
(12.8kHz)
PNHCLK
1
2
3
CNTRL-
Ii
~
>-'
\0
~
4
j~
/)/
-V-------j~/'
Z12-15
~
-V-------
PRNPRD
1--'
-1/.--------
Z3-7/Z22-9
/ l , ; - - - - -U
~
Z:/2 15
/1,
/j,,-'- - - - - -
Z22-2
1r-
~------
FIGURE 3-4.2. PRINTER CONTROL TIMING SYNCHRONIZATION
U"",,--
o
PRNPRD
5
10
15
20
30 msec
25
I
1...._ _ _ _ _ _ __
Z22-9 (PULSE WIDTH NOT TO SCALE)
r-Ir~--lf---T
·----1. . ________________
Z22-15
Z22-2
1....___________
,..
r
m7
y.
tv
o
PRINT
HDCLK Z11-8
·--11
r
-_----1'---.---
=n
!--VARIABLE --.I
DDS
1 ____
~
DAMP
PPHSA
I~AP~P;RQOXx..~Ir---------------~--------------4 msec
t---
I
______r---l____________
PPHSB
FIGURE3-4.3. PRINTER CONTROL TIMING, PRINTING IN COLUMNS 1,4, ETC.
(j
,/ l
\.
/
I .".
(\
)
~,
,~
~
I
o
msec
5
20
60
100
140
180
PBUSY-
~
LlFTHEAD
I
L
L
L
RETURN (Z34 3)
-~
Z34-4
~
:
N
......
I
~_PR_N_P_R~D_________________________________________________________________________________
f'--
\.;>
190
L
:
~
-~
L
:
Z34-11
'---
1
Z34 12
:
I
I
~
L
..
VARIABLE
Z19 B
LHLS-
(LEFT OF COLUMN 121
L
I
I
I--
VARIABLE
---I
(COLUMN 1)
I
I
I
Z1-11
_---'~
HPC
I
L
flJULllJlNi,-____
FIGURE3-4.4. PRINTER CONTROL,NORMAL CARRIAGE RETURN TIMING DIAGRAM
r
PRNPRD
HDCLK
Zll-8
1
r1-
r
DDS
t..l
l..._______
--~-
VARIABLE
_I
~------------~--r
DAMP
N
-1....________
N
PPHSA
PPHSC
HPC
--1'--_ _ _----:
r(AMPLITUDE VARIABLE)
J
L,"'__________
FIGURE 3-4.5. PRINTER CONTROL TIMING, BACKSPACE FROM COLUMNS 4, 8, ETC.
~,
.~
~.
r-
PRNPRD
------ 1 . . ________
Z22-9
------1
Z22-15
r---------,. . .__________
Z22-2
Z22-7
~
V>
Z22-10
-PPHSC
----- PPHSB
PPHSA
LIFTHEAD
PACA
1
r-
- 1&.-___
Il'--______~
1---· --1'--________---'
I'_____
r-~
~-----.t....-_ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I
\.._ _ _ _ _ _ __
FIGURE 3-4.6. PRINTER CONTROL, LINE FEED TIMING DIAGRAM (DOUBLE LINE SPACING)
SCLK
DATA
CONTROL
DECODE
t
CON+ROL
LlNEt
PRNENA
ENABLE
DETECT
ENABLE
CLK
DATA
BUFFER
TO PRINTER
CONTROL
CHARACTER
GENERATOR
DATA
36-BIT
PATTERN
~
.j>..
PRINTHEAD
TO BUFFER
DRIVER
a:
w
~
z
::>
0
(.)
w
..,I
1:0
«
z
w
PATTERN
COUNTER
(36-BIT
PATTERN)
PRINTHEAD
AND CLOCK
PRINTHEAD CLOCK
PRINTER-GO SIGNAL TO PRINTER CONTROL
--_ ... _ - - - - - -
-------
FIGURE 3-4.7. PRINTER DECODE BLOCK DIAGRAM
(-1
\
J
/
\
)
(
\
"'J
PR INTER
DECODE
CLOCK BIT
PATTERN
TO CONTROL
DECODE
CLOCK BIT
PATTERN TO
35-BIT SHIFT
REGISTER
CLOCK DATA
TO
SHIFT
REGISTER
NO
ENABLE 32 BIT PATTERN
COUNTER
NO
ENABLE 32 BIT
PATTERN
COUNTER
YES
CLOCK BIT
PATTERN TO
CONTROL
DECODE AND
COUNT BITS
SENT
CLOCK BIT
PATTERN TO
35-BIT SHIFT
REGISTER AND
COUNT NO_
BITS SENT
DISABLE DATA
CLOCK; ENABLE·
STATE/PATTERN
COUNTER
CLEAR MOS
CHARACTER
GENERATOR
NO
NO
CLOCK IN
CONTROL
BIT
SEND PATTERN
READY SIGNAL
(PGOI. AND
RESET
PRINTER FOR
NEXT
CHARACTER
(ENABLE)
YES
SEND PATTERNREADY SIGNAL
(PGO) AND
RESET
PRINTER
FOR
NEXT
CHARACTER
(ENABLE)
NO
CONTROL
CHARACTER
PRINTABLE
CHARACTER
FIGURE 3-4.8. PRINTER CONTROL CHARACTER DECODING FWW CHART
3-25
PNRRST-
----------------------~~
--U
~~-----------------------
I
I
I:I
I
PRNENAIPRTiiNA-'
(VAlID)OATA
BIY01
81T02
81Y03
81104
81105
81T06
~
L
BITP::
81107
~
I
SCLK~~~ro~
I
I
I
I
!!!!£!:!.
IREDCLK'
REDCLK-
I
I
I
",
I
I
I
I
I
I
I
I
-1
~3T
~
ENDDAT
~---------------.
~-----
I
I
I
DATCLK
~
a..
J
~~----------------""l._____
PAT 0
PAT 0
PATt
PATt
~-----------
PAT2
PAT'
~
~I---------------'L-_ ___
PATS
PATS
~
1.-------------~
MOSCLR
MOSCLR
~
t------------------
PHelK
PHeLK
PGO
PGO
t
PRTRST
f,__- - - -____________
PRTRST--,
J.
---~
____
~
~
Y'"11204.811111C
FIGURE 3-4.9. PRINTER CONTROL CHARACTER DECODING TIMING DIAGRAM
()
\.
J
/
'\
!
J
(
'\.
TABLE 3-4.2 ASCII CODE SYSTEM AND CHARACTER SET
0
0
~
b3
~
b1
bs
1
1
0
1
0
0
1
1
1
1
0
1
1
1
,
p
A
Q
a
q
B
R
b
r
0 0 1
C
S
C
5
1 0
D
T
d
t
0 1 0 1
E
U
e.
u
0
0 0
1
0 0 1
2
1 0
&
6
F
V
f
v
0 1 1 1
.#
7
G
W
9
w
8
H
X
h
x
9
I
Y
J
Z
0
1 0 0 0
1 0 0 1
*
1 0 1 0
+
1
K
1
y
j
z
k
{
L
1
,"
M
1
1
>
N
1
1 1
?
0
IPRINTABLE CHARACTER
_
..
1
0
p
0 0 0 0
(
1
0
0
&d!lIM
A
BUT NO ACTION TAKEN
3-27
0
AUXILIARY DEVICE CONTROL CHARACTER
.9lD t: S GE~E~A:rf;PJ!Y
PRINTER CONTROL CHARACTER
n
KEYBOARD,:
TABLE 3-4.3 BAUDOT CODE SYSTEM AND CHARAcrER SET
NOTE
Essentially two character sets (U. S. and U. K.) are accommodated. Both character sets
are printed as described in Paragraph 3-4.4.
bS
'0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bits
b4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
b3
b2
bl
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
:~~~~~~t~~~~~~~~~~
1
'1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
F~es
Letters
U.S.&U.K.
u.S.
E
3
I
U.K.
3
Igmtn.tfII~tr~ffff~rrUII~.IIIfItt_~""~~~~~
A
SPACE
SPACE
SPACE
S
1 8 8
U
7
7
tl.(m~r~r~~~IIIIrr~~rtrrqjl~gtHrrrrr_~_t
D
R
J
N
F
C
*
4
*
4
IIlg~mrrrttI~IIII.t.r§
$
%
(
5
(
5
"
+
)
2
)
2
H
Y
P
#
£
Q
K
T
Z
L
W
o
6
6
o
o
1
9
9
1
B
? ?
G
&
@
:~m.~Im~f~rrrrmIfIII~~f~mmmI_mmmmmmmmmmmm~m~lI3~mm
M
x
v
;
I
fimJ~~~~~~fIf~tfffffIIIIIfl11.~IfI~ttt~~t~~~~~~~~~l"(~~
Nonprinting characters
3-28
"--._-
,/
3-4.5.2 Printhead Compensation Circuit. The Printhead
Compensation Circuit and printhead driver transistors are
located on the Printer Code PC card (see schematic 959178,
in Appendix C, Sheet 2). These circuits ensure that the
proper voltage is applied to the printhead (PVOLT).
Q2 will turn off Q13, and capacitor C4 will be isolated to
retain the DVOLT level during the 10 msec printing time.
When printing, the temperature of the diode rises quickly
and falls quickly. When printing slow, the diode has time to
return to ambient temperature. In this condition the output
of AR2 is zero, and the gain of AR3 is controlled
exclusively by the slow resistor. When the printer is running
fast, the temperature of the printhead rises, causing the
diode voltage to drop. This change is amplified by AR2,
enabling the fast resistor which controls the gain of AR3.
Thus, as the ambient temperature of the head increases, the
print voltage is decreased proportionately.
Current for the print head drivers is provided by a constant
current source consisting of Q6 and CR6. This source
provides current for printhead driver transistors Q7 and Q9.
The PVOLT output voltage is controlled by the voltage
compensation circuit which adjusts the voltage by sinking a
portion of the current available for PVOLT drive. This
current consists of two operational amplifier circuits AR2
and AR3. AR3, an OP AMP which sinks current, has two
negative inputs: one from the slow printing bias circuit and
the other negative input from the gain feedback loop. The
slow printing bias is set by choosing the slow resistor on the
printhead. This sets PVOLT to the proper level for slow
printing (1 char/sec) for this particular printhead. The gain
feedback loop consists of resistor R35 and variable resistor
R36. R36 acts as a contra~t adjustment, capable of
changing gain of this stage from 15 to 50. The positive
input to AR3 becomes effective when the printer is
operating at fast printing speeds.
When the print command is low, transistors Q3 and Q4
clamp PVOLT to ground through CR7 and CR8. If the
print command stays high too long (longer than 11-12msec)
one-shot Z19 will time out, and the buffers on the
Printhead Interface PC card will be cleared (PHBFRCLR),
removing the base drive from the head. Overvoltage
protection for the printhead is provided by CR9, CRI0,
CRll, and Q8. If PVOLT rises high enough for CR9 and
CR10 to conduct, Q8 will generate PHBFRCLR which
removes the base drive to the head. At the end of each print
pulse, Z22 generates PHBFRCLR to remove base drive
from the head. A timing diagram is shown in Figure 3-4.10.
The operational amplifier AR2 is used as a sensing amplifier
for the printhead temperature compensation diode. This
amplifier is set for a gain of 30. A resistor divider R14 and
R15 hold the negative input to a constant reference voltage.
The voltage of the printhead diode is applied to the positive
input. This diode is provided with 1 rnA current from the
9V reference voltage through R12 and the balance r:esistor
R4 located on the printhead. The balance resistor is chosen
at room temperature to ensure that all printheads have the
same diode voltage at room .temperature. When the
printhead is not printing (PRINT is low), Ql and Q2 turn
on FET Q13. This allows capacitor C4 to charge up to the
diode voltage (DVOLT). When the print command is given,
(PIN 12)
PRINT
(XA1-10)
PHBFRCLR-
-+-I
I.I
Current regulation to the head is provided by R30 and Q5.
This limits the short-circuit current of PVOLT to less thiln
3.5 amps.
Reference voltages for the compensation ciIcuits are
provided by voltage regulator ARl. Resistor R9 is selected
to produce the correct reference voltage (approximately 9.0
volts). The bell driver also is located on the Printer Code PC
card. When the head reaches column 72 or the BEL
character is received, a one-shot is fired. This gates the bell
clock (3.2kHz) to transistor AI0 and applies a 3200-Hz
tone to the speaker.
+
10 (±1/,msec
I~T1
1~·T2
I I
J
I,
10 (±1) msec
I",
.1
r
11-12 msec
I
.lI+-1
I
-I
I
T 2 = 2.5 (±0.5) ].ISEC
T1 = 1-2].1SEC
FIGURE 3-4.10. PRINTHEAD BUFFER CLEAR (PHBFRCLR) TIMING DIAGRAM
3-29
3-5 KEYBOARDS AND KEYBOARD
INTERFACE.
bits and the terminal requires 8 bits on the serial bus, the
eighth (parity bit) is hardwired on the motherboard to be
the same as bit 1. Therefore, on all data from the keyboard,
the eighth bit will be the same as bit 1 when clocked on the
internal serial data bus. However, the record control or
transmitter may change this arrangement.
The keyboard used in the data terminals is a fully encoded,
alphanumeric keyboard with two-key rollover. The
interface for the keyboards is located on the Printer Code
PC card (see schematic 959178 for both ASCII and
Baudot). A block diagram of the keyboard interface is
shown in Figure 3-5.1. A flow chart and a timing diagram
are shown in Figures 3-5.2 and 3-5.3.
3-5.1 STANDARD ASCII. The output of the standard
ASCII keyboard is serial by character and parallel by bit.
There are seven data bits and a strobe pulse; no parity is
generated by the keyboard. The strobe pulse is shown in
Figure 3-5.4 relative to a typical data bit. The ASCII codes
generated are shown in Table 3-4.2.
Upon detection of a keyboard strobe, the parallel keyboard
data is loaded into the data buffer, and the strobe flipflop is
clocked. The keyboard interface then sends a keyboard
request (KBDREQ) to terminal control and waits for a
keyboard enable (KBDENA). Keyboard interface uses this
enable and eight system clocks (SCLK) to transmit the
character serially to the data bus. When this is done, the
repeat key (REPEAT) is checked, and a flipflop is set to
remember the state of the repeat key. The interface then
checks for another strobe; if there is no strobe but the
REPEAT key is depressed, another request will be
generated and the same character will be retransmitted.
This will continue until there is a strobe or until the
REPEAT key is released. If the REPEAT key is on and a
new keyboard strobe is received, the new character will be
loaded into the data buffer, and it will then be transmitted
as before. When there is no REPEAT key signal, only one
character will be transmitted for each keyboard strobe
(depression of a key).
All signal outputs are TTL-compatible (data and strobe) ..
The outputs of the special function keys, except ~ and
TAPE, are isolated single-contact closures to ground. The
and TAPE keys are debounced, and the output from
these keys Ts"7"TTL-compatible pulse. These outputs are
normally at a logic ONE. The special function keys are:
TAPE
A state counter determines the sequence of operations as
shown in Figures 3-5.2 and 3-5.3.
a.
HERE IS
b.
PAPER ADV (Advance)
c.
BREAK
d.
REPEAT
e.
-
f.
Any time the ASR control panel keyboard
LINE/OFF/LOCAL switch is in the OFF position, the
keyboard interface will be held in the reset position and
will not accept strobes. Since the keyboard outputs only 7
TAPE
--
TAPE.
Pin assignments for the standard keyboard connector
(inside connector) are listed in Table 3-5.1.
411sec MIN.
~
LOGIC 1
LOGIC 2
I
----l4 llS8c
I 4 1lS8C
l...- }
I MIN. I MIN. I
----------
DATA GOOD DURLNG THIS TIME
FIGURE 3-5.4. KEYBOARD STROBE PULSE
3-30
KEYBOARD
STROBE
,-
FROM
KEYBOARD
FROM
.FRONT PANEL ~
KEYBOARD
DATA IN
(8BI.S)
'STROBE
REPEAT
KEY
DETECT
REPOFF
KEYBOARD
, 'ON'
DETECT
~
t
STROBE
DETECT
DATA
BUFFER
AND
TRANSMlrTE-R
STATE
COUNTER
AND
KBDLOAD
AND
ItBDREQ
LOGIC
KDBON
DATA* (BUS)
SCLK*
KBDENA*
RDRCLK
FIGURE.3-S.1 KEYBOARD INTERFACE BLOCK DIAGRAM
3-31
KBDLOADAND
STROBE CLEA!I
KBDREQ*
STO
NO
YES
YES
ST 1
GENERATE
LOAD (ST1-)
ANDSTBCLR
(ST1)
ST2
,GENERATE
KBDREa,
AND RESET
'COMPLT'
ST3
YES
CLOCK IN
REPEAT
KEY STATUS
(REPOFF)
CLOCK OUT
DATA WITH
SCLK •
YES
NO
FIGURE 3-5.2. KEYBOARD INTERFACE STATE FWW DIAGRAM
3-32
~
~.
i
t
t
~R~
~
KBDC'R-
l
•
~
1
1
1
~
f
.~
~~
_ _ _ __
RDRCLK
~
Sf')
KBDLOD
ST!--KBDLDD STI
AND STBCLR)
1ST2_=KBDREQ·,ST2
KBDREQ
KBDREQ
~.
r
L--...r'\
I
~
CO",,'T
\,,0)
LJ
II
KBDENA-
VAUDDATA
SCLK··
I
I
I
BITOI
I
I
~
I-,
tI
-t-_ _- ,
I'
r
t
I
REPOFF _ _ _ _ _ _ _ _ _ _ _ _ _
r-l..,.
LJ ~
I
J----J-+-J
BIT'
LBDREQ
t,
I
t
BIT 02
I
I'
~
r-t
.
~
KBDLOO
n
t
n
m
coMClRlJ
n
~
t
n
I
BIT"
I
BIT02
I
BIT,
I
I
I
J---U-+,j
,IT 01
tI
I
BIT 02
I
I
t
L
t
rr-
t
BIT'
I
J----L.j-+-,J~----
r-
•
1
T
Tt
T2
T3
-1120Umsac:
·4 )8EC MINIMUM
.. 4 !BEC MINIMUM
• 4).lSEC MINIMUM
,..
STROBE BUTNO REPEAT
I
I."
REPEAT BUT NO STROiE
-I..I·
FIGURE 3·5.3. TIMING DIAGRAM KEYBOARD INTERFACE
.
STR08EANOREPEAT
•
I
:~re~:;-
TABLE 3-5.1. STANDARD KEYBOARD CONNECTOR PIN ASSIGNMENTS
Pin
Number
1
2
3
4
5
6
7
8
9
10
Pin
Number
Signal
BIT 6 (Data)
SPEED (Direct Connection to Switch Connector)
BIT 1 (Data)
BIT 3 (Data)
REPEAT (Special Function Output)
TAPE (Special Function Output)
TAPE (Special Function Output)
GROUND
,
+5V Power
-12V Power
--
A
B
C
D
E
F
H
J
K
L
In addition to the standard tab area which interfaces to the
terminal KSR motherboard, an additional tab area (outside
connector) is provided on the keyboard for interfacing the
terminal (via the keyboard and decoder in the keyboard) to
an optional numeric keyboard for number entry.
l-C
2-A
2-B
2-C
3-A
3-B
3-C
3-D
4-A
4-B
4-C
4-D
5-A
5-B
5-C
5-D
5-H
5-J
7,8
!Hr'i,~
BREAK (Special Function Output)
ON LINE (Direct Connection to Switch Connector)
STROBE PULSE
HERE IS (Special Function Output)
PAPER ADVance~ (Special Function Output)
CWCK (For Debounce Circuit)
3-5.2 UPPERCASE/LOWERCASE ASCII KEYBOARD.
The Uppercase/Lowercase (full) ASCII keyboard is the
same as the standard ASCII keyboard (see Section 3-5.1)
except the uppercase/lowercase keyboard generates either
uppercase or lowercase codes, depending on the position of
the UPPERCASE key. Full ASCII keyboard layout and
symbolization are shown in Figure 3-5.10. ASCII codes
generated are listed in Table 3-4.2. The full ASCII keyboard
character set is shown in Figures 3-5.11 through 3-5.13.
TABLE 3-5.2. OPTIONAL NUMERIC KEYBOARD
CONNECTOR PIN ASSIGNMENTS
i-A
1-B
BIT 7 (Data)
BIT 5 (Data)
BIT 2 (Data)
Standard ASCII keyboard layout and symbolization are
shown in Figure 3-5.5. The character set is shown in Figures
3-5.6 through 3-5.9.
Pin assignments for the optional numeric keyboard
connection tab are listed in Table 3-5.2.
Contact Closure
Between Pin No.
Signal
ASCII Character
3-5.3 BAUDOT KEYBOARD. The Baudot keyboard is the
same as the standard ASCII keyboard except the Baudot
keyboard generates a 5-bit Baudot code instead of the
ASCII code. The additional tab area used for numeric entry
on the standard ASCII-type keyboard is used only as a
connection for the ON-LINE switch (connects to pin H) on
the Baudot-type keyboard (pins 7 and 8 are still grounded).
, (Comma)
o (Zero)
. (Period)
1
2
3
4
5
6
CR (Carriage Return)
7
8
9
LF (Line Peed)
+
The Baudot keyboard layout and symbolization are shown
in Figure 3-5.14. The Baudot codes generated for the keys
shown in Figure 3-5.15 are listed in Table 3-4.3.
3-6 TRANSMI!f/RECEIVE PC CARD
(EIA INTERFACE).
3-6.1 ASCII TRANSMIT/RECEIVE PC CARDS (300
BAUD MAXIMUM). Two versions of the ASCII
Transmit/Receive PC card are available: the standard
version (TI Part No. 959135) and the optional dual-format
version (TI Part No. 969455). The dual-format version is
equipped With strappable options which permit the
Dual-Format Transmit/Receive PC card either to operate
like the standard version (standard format) or to operate in
/
ON-LINE
SPEED
GND
3-34
IPAPERI
ADV
FIGURE 3-5.5. STANDARD ASCII KEYBOARD LAYOUT AND SYMBOLIZATION
QGJD[JGJGJQGJGJDDD~
ElGJGJGJGJGJGJGJCJGJGJGJ[;]
E1 GJ [J GJ [J GJ G~J[J [J DO GJ EJ
c::JGJ [J GJGJ [J [;JGJD DO E1
I
NOTES:
•
I
(SPACE BAR)
The above codes are generated when the labled key is depressed.
but neither the SHIFT nor the CONTROL (CTRLI key is depressed .
.. Not a code-generating key.
FIGURE 3-5.6. UNSHIFTED CHARACfERS, STANDARD ASCII KEYBOARD
3-35
* The above codes are generated when the labled key and the SHIFT
NOTES:
key are depressed. but the CONTROLlCTRLI key is not depressed.
* * Not a code1lllnerating. key.
D
A blank key indiCates strobe inhibit
FIGURE 3-5.7. SHIFTED CHARACTERS, STANDARD ASCII KEYBOARD
DDDDDDDDDODD~
BBBEJBBc:JBEJ0EJEl0
EJB EIEIBE10[~]c:J0DEIE:l
c::JEJElBBEJ00DDDc::J
I
NOTES:
I
(SPACE BAR)
* The above codes are generated when the labled key and the CONTROL ICTRL)
key are depressed. but the SHIFT key is not depressed.
.
** Not a code-generating key
A blank key indicates strobe inhibit.
.
-
-
FIGURE 3-5.8. CONTROL CHARACTERS, STANDARD ASCII KEYBOARD
3-36
---"
(
DDDDDDDDDDDD~
BDDDDDDDDBE10c:J
EJDDDDDDDE1c:JDBEJ
c::JDDDDDc:JBDDDc::J
I
I
(SPACE BAR)
* The above codes are generated when the labled key. the SH 1FT
NOTES:
key. and the control (CTAL) key are depressed.
** Not a code-generating key.
o
A blank key indicates strobe inhibited.
FIGURE 3-5.9. SHIFT AND CONTROL CHARACTERS, STANDARD ASCII KEYBOARD
LEGEND:
Control Character
Alphabetic character (SHIFT for uppercase)
Shifted character
Unshifted character
Shifted character. control character
Graphic unshifted
FIGURE 3-5.10. FULL ASCII KEYBOARD SYMBOLIZATION
3-37
NOTES:
*The above codes are generated when the labeled key is depressed but
neither the SHIFT nor the CTRL key is depressed.
**Not a code generating key.
***If UPPER CASE is depressed, only upper case alphabet codes are generated,
otherwise lower case alphabetic codes are generated.
FIGURE 3-5.11. LOWERCASE CHARACTERS, FULL ASCII KEYBOARD
."
NOTES:
*The above codes are generated when the labeled key and the SH IFT key
are depressed. UPPER CASE has no effect.
**Not a code generating key.
D
A blank key indicates strobe inhibit. Depressing SHIFT and CTRL keys
together inhibits strobe.
FIGURE 3-5.12. SHIFTED CHARACTERS, FULL ASCII KEYBOARD
3-38
..
NOTES:
* The above codes are generated when the labeled key and the CTRL
key
are depressed. UPPERCASE and SHIFT keys have no effect.
** Not a code generating key.
O
A blank indicates strobe inhibit. Depressing SHIFT and CTRL keys
together inhibits strobe.
FIGURE 3-5.13. CONTROL CHARACTERS, FULL ASCII KEYBOARD
3-39
/"
\~
~APEFJ
DV
I
E3
I
!APEI
ITAP:
I
When each key is depressed, the data terminal generates the indicated Baudot characters
according to Table 3-3. U. S. figures are shown on upper lefthand surface of the keys,
and U. K. figures are shown on upper righthand surface of the keys (where different).
Printing of either figure set is a strappable option.
FIGURE 3-5.14. BAUDOT KEYBOARD
[JGJGJ[J[JGJGJCJ[J[J~
[J[JG]GJ[JeJOGJC]1
I
GJO[J[J[J[JeJ GJGJ~[:B
RETURN
M
LTRS
FEED
E3
P~AT
I:APE
I
I TAP!
I
The Baudot codes corresponding to the above characters are generated when the LTRS and
the labeled key _is depressed.
* NOT A CODE-GENERATING KEY
FIGURE 3-5.15. BAUDOT LETTER MODE KEYBOARD CODES
3-40
~APERI
DV
I
I
EIA
DATA
IN
EIA
GND
EIA
DATA
OUT
EIA DATA TERM, ROY
EIA DATA CARRIER DETECT
EIA CLEAR TO SEND
EIA INTERFACE
EIA REQUEST TO SEND
EIA DATA SET READY
RECEIVER
RECEIVE
REQUEST
. ..---------~ DUPLEX
SWITCH
AND XMT/RCV
'LOCKOUT'
LOGIC
TRANSMITTER
PARITY
SPEED SWITCH
W
...J
III
<{
W
...I
(SYSTEM CLOCKS)
III
w
U
w
~
:ij
w
w
~
a::
10 CPS' (t 1 BITS)
10 CPS' TIMING
BIT1'IME
(SEE TABLE BELOW)
START
BIT
Bl
1+-----
B2
B3
B4
B5
B6
lilT
CHARACTER TIME Ii> 15 ANO 30 CPS' (to BITS)
(SEE TABLE BELOW)
15 CPS'
co
:Jl CPS'
BIT TIME
6.67 msec 3.33 msec
CHARACTER TIME
66.7 msec 33.3 msec
*CPS = OiARACfERS PER S.E
.\:.
153.6 kHz
120
CP~
0
0-
4
4
I
I
L
I
CPS
0-
'"
0
0-
0
0-
8
30 CPS
10 CP~I
15 CPS
38.4 kHz
0
0
32
.£.
64
0
~
Y
.r-J~
0
0-
0
2
0
2
0
4
0-
I
I
L
I
l
51.2 kHz
,
,
PWRCLK,
1
12.8 kHz
PNHCLK '"
,
I
6.4 kHz
,
BYCLK '"
1
,
3.2 kHz
BELCLK '"
J
800Hz
C800 '"
I
19.2 kHz (15 Hz)
14.08 kHz (10 Hz)
SRVCLK," ,
04 kHz
"
0
c;-
6 kHz
9.2 kHz
6.8 kHz
1
2
0
64
o
XMTCLK," ,
o Hz
50 Hz
:00 Hz
200 Hz
"
V
NOTE CPS = CHARACTERS PER SECO
'ENABLE'
FIGURE 3-6.5. ASCII SYSTEM CWCKS BLOCK DIAGRAM
(
\
"I
)
/'
(
/
"
\
"
"
/
(
EIA data set ready (EIADSR) - Must he a high level
(>3.0V) to either transmit or receive
key on the keyboard is depressed, the output line is held to
a continuous low level (continuous space) as long as the
BREAK key remains depressed. The Baudot transmitter
timing diagram is sh.own in Figure 3-6.7. A
transmitter/receiver schematic (Drawing No. 959197) is
contained in Appendix C of this manual.
EIA clear to send (EIACfS) - Must be a high level
(>3.0V) to transmit
EIA data terminal ready (EIADTR) - Held to a high
level (>3.0V) by the terminal
3-6.2.2 Receiver. The receiver is an asynchronous device
which continuously monitors the transmission line. EIA
data on the line is passed through an EIA-to-TTL level
converter for use by the receiver. Upon receipt of a start bit
(high to low transition from the line), the receiver starts
timing for 0.5-bit time. If the line has remained low for at
least a 0.5-bit interval, a latch is set which keeps the
receiver from resetting until the whole character has been
received. If the line does not remain low for at least 0.5-bit
time, the receiver resets immediately and continues looking
for a true start bit. When the start bit is recognized., it is
clocked into an input buffer, and ~a.chsucceeding dab bit
also is clocked into the buffer until the whole character is
clocked in. Then the receiver is reset to search for the next
start bit, the data in the input buffer is parallel-loaded to a
serial data bus buffer, and a serial receiver request
(SRVREQ) signals terminal control that a character has
heen received from the line. If the terminal is in half-duplex
when a start bit is recognized, a flipflop is set (HLFDPX)
which causes the line busy (LINBUSY) line to go high and
inhibit the transmitter from sending any characters.
EIA request to send (EIARTS) - Held to a high level
(>3.0V) by the terminal.
EIA data carrier detect (EIADCD) - must be a high
level (> 3.0V) to receive.
3-6.2 BAUDOT TRANSMIT/RECEIVE PC CARD. The
Baudot Transmit/Receive card, block diagrammed in Figure
3-6.1, is composed of four major sections:
(
a.
Transmitter
.b.
Receiftr
c.
System clocks
d.
EIA control signals.
3-6.2.1 Transmitter. Upon receipt of a transmit enable
(XMTENA) and eight system clocks (SCLK) from terminal
control, the transmitter stores the data on the serial data
bus in a buffer register and adds a start bit and stop bit to
the data. After the character is stored in the output buffer,
a timer starts which issues transmit clocks (XMTCLK)
which clock the data out of the buffer at the speed (50,75,
or 100 baud) selected on the PC card SPEED switch. The
TTL data then is sent through a TTL-to-EIA level converter
to the transmission line.
The transmitter will stay inhibited as long as the receiver
continues to receive characters in half-duplex, with no
longer than a character time between each character
received. When terminal control sends a serial receiver
enable and eight system clocks (SCLK) to the receiver, the
data in the serial data bus buffer is clocked out to the serial
bus. The Baudot code has only 5 bits, and the serial bus
must have 8-bit codes, one for each system clock.
Therefore, the last 3 bits clocked to the bus from the
receiver are always three ONES. The clock (32CLK) which
strobes the input data into the input buffer is derived from
the serial receiver clock (SRVCLK), whose frequency is 64
times a bit time (as selected on the SPEED switch).
At the start of a transmit enable, a transmitter busy
(XMTBSY) flipflop is set which signals terminal control
that the line is busy (LINBUSY), and no other character
can be transmitted at that time. The transmitter continues
to clock the output buffer until the total number of bits,
including start and stop bits (7.5 bits at all speeds), are
clocked to the output line. A transmit clock counter counts
the transmit clocks and resets the transmitter after the data
has been clocked to the line. The output data format is
shown in Figure 3-6.6.
(~
The 32 clock (32CLK)' starts when the clear is removed
from the receiver (a start bit is recognized). The first
32CLK comes at 0.5 bit time and then every bit time
thereafter. If T is the bit time, the 7497 from which the
SRVCLK is counted down to the 32CLK, will cause the
data to be strobed into the input buffer within ±T/128 of
the center of each bit time. A block diagram of the receiver
is shown in Figure 3-6.1. A receiver timing diagram is
shown in Figure 3-6.8, and a Baudot Transmitter/Receiver
schematic (Drawing No. 959197) is contained in Appendix
C of this manual.
As long as the transmitter is transmitting continuously (no
more than 0.5-bit time delay between transmit enables) and
the duplex switch is set to half duplex, the receiver input
data is held high (logic ONE); and the receiver is "locked
out" from receiving any data from the line. If the BREAK
3-47
r--'--T--r--r-
MARKING - -...
I
I
SPACING
I
I
I
I
I
I
I
I
I
I
I
'-----a.I _ _ L __I__ ...1 __ 1. __
20
BIT TIME
I
I
DATA BITS
msec-'
START
B1
B2
I
___ JI
30.0 msec
B4
B3
I
B5
STOP
CHARACTER TIME (150.0 msec)
CHARACTER TIMING: 50 baud
r--r-'--i--r-
MARKING - - - .
I
I
I
SPACING
'--~
I
I
I
I
I
I
I
I
___ l.I __ IL_ -1-_-'
__
13.33
meec:
BIT TIME
I
I
DATA BITS
START
B1
B2
B3
I
I
_ _ _ ,JI
. 20.0 msec
B4
B5
STOP
CHARACTER TIME (100 msec)
CHARACTER TIMING: 75.0 baud
r--r--r-'--T--
MARKING--...
SPACING
BITTIME
I
I
I
I
I
I
I
I
I
I
I _ .lI _ _ 1.
I __ IL. _...JI__
____
---~
DATA BITS
10 msec
START
B1
B2
B3
15.0 msec
B4
B5
CHARACTER TIME 175.0 msec)
CHARACTER TIMING: 100 baud
FIGURE 3-6.6. BAUDOT LINE DATA FORMAT
3-48
STOP
~
~
I
I
XMTENAJ
I
_..!A~.!!!.-i
I
I
I
I
BITll BIT21 BIT3 1 BI14I BIT5 1 BITS I BIT I I BITP I
I
:
________I~~
I
I
SCLK-
.~
I
I
I
t-Tl-j
II
I
r
---. ..-T5
I•
r
Ju
1 BITTIME---l
l
i
XMTCLK
n
.
._
XMT& COUNT
I
XMT7TH BIT (STOPBITI ON NEG. EDGE
(COUNT o
1l
~I-------------------
I
I
~n~
:
I
I
IOCLK
I
I-T3-1
L1NBUSY
OR
XMTBSY
_ _---.11
-------I
I
1---
I
I
Z13-6
L-
V>
.I::.
- - - - - {------,"---
\0
XMTOUT
I
I.
I.
INPUTTIME SCALE
START
I
• I---T1--1
I
I
STOP BITTRANSMITIED
t
BIT 4
BITS
DUTPUTTIME SCALE
NOTES:
Tl 09.8 ","C
T2:: 1 BIT TIME '" 10 msec FOR 100 baud
:: 13.33 msec FOR 75 baud
'" 20 msec FO R 50 baud
T3 0.5·BIT TIME
T4 1 SRVCLK PERIOD 1/64 81T TlME
T5 '" 2.45 lJsec
0
0
0
REFERENCE DESIGNATORS ARE THOSE
SHOWN ON SCHEMATIC 959191 (APPENDIX CI.
FIGURE 3-6.7. BAUDOT SERIAL TRANSMITTER TIMING DIAGRAM
•
I
THESE BITS TIED HIGH
.----,-----,.--- ~:D~:~ ~~c:~~~;~L
DATA BUS
I
______
BiT1
BIT2
BIT3
iiiTs
BIT4
BIT6
Bm
BITP
II
I
I
I
SCLK-
I
SRVENA-
-1
r________________________________
Tl - ,
~
r
--., T4r-
~r-
SYNCHRONOUS
ASYNCHRONOUS
ir - - - - - - i
ZI5-3
hr.- - - -
ZB·n
~~---
i
SRVCLK
'"4
~
Z11J.9
,
I
G
T3....,;--
~~--
~
START
~
II STOPBIT
" T3
'
T~3-+l'"
.... j+- T3
I
BITS 2·7
BITI
A
r
~
~
r-1
~
1
~---------
~
~.------------~~------
Z20-8
T4=2.45 ""
1 BIT TIME'
10 mllC FOR 100 boud
13.33 milt FOR 75 baud
20 milt FOR 50 boud
n=9.8JJOc
32CLK
SRDATA
NOTES:
SYNCHRONOUS AND ASYNCHRONOUS TIME SCALES
SHOWN ARE DIFFERENT.
T2 = SRVCLK IS 64 x (BIT TIME)
--.
~
o
~
~
SRVREQ-
BITP
T3' 0 TO 1 SRVCLK PERIOD 1l2)
REFERENCE DESIGNATORS ARE THOSE SHOWN
ON SCHEMATIC 959197 (APPENDIX C)
IF PARITY BIT (BIT P) ISA ONE. THE RECEIVER RESETS AT
THAT POINT.
.
IF PARITY BITIBIT P) IS A ZERO. THE RECEIVER RESETSAT
THE RISING EDGE OF THE STOP BIT.
'.~---
Ir
~r-1I,-----
~
~I-'_ __
1r------------1-----
FIGURE 3-6.8. BAUOOT SERIAL RECEIVER TIMING DIAGRAM
(j
,.
\c.
\
\.
"'
(
3-6.2.3 System Clocks. The entire clock system is derived
from a single crystal (0.005 percent accurate) located on
the Baudot Transmit/Receive PC card. The crystal
frequency of 9.8304 MHz is then counted down to provide
all system clocks used in the data terminal. A block diagram
of the system clock structure is shown in Figure 3-6.9.
3-7.2 ASR TERMINAL CONTROL. The ASR terminal
control generates the clock and enable signals used to
transfer data within the terminal. Terminal control logic
generates a status enable (STAENA) and eight system
clocks (SCLK) to check the status of the keyboard and
printer (LINEiLOCAL/OFF). It also checks for reader feed,
reader error, record-buffer-full or end-of-tape on either
cassette. This is done by clocking this information into an
eight-bit serial-to-parallel register using status enable and
eight system clocks. All of the above information, along
with the recorder and playback status signals (RECLINE
and RDRLINE), are loaded into a register and are used to
determine which devices are on the local bus and which are
on the line bus. The output of this register is gated with
remote OFF signals (PRNROF, RECROF, and RDRROF)
and is fed into a two-line-to-one-line data
selector/multiplexer. The enable for the multiplexer is a
combination of the presence of local data (DATLOC) and
line data. The select line of the multiplexer selects either
the line or local half of the network. Therefore, if a device
is in the local mode and the data is local data, the
multiplexer will select that device to receive an enable. The
outputs of the multiplexer control which of the four
devices that receive data (AUX1, AUX2, recorder, and
printer) will get the data.
3-6.2.4 EIA Control Signals. The Baudot EIA control
signals are the same as the ASCII signals described in
Paragraph 3-6.1.4 above.
3-7 TERMINAL CONTROL.
3-7.1 KSR TERMINAL CONTROL. The KSR terminal
control generates the clock and enable signals used to
transfer data within the data terminal. Action is initiated by
request signals. The keyboard request (KBDREQ-), serial
receiver request (SRVREQ-), AUX1REQ-, and
AUX2REQ- are 5-f.1sec wide pulses stored in flipflops until
the respective enable signal is generated (KBDENA,
SRVENA. AUX1ENAS, and AUX2ENAS), at which time
the flipflops are cleared. When the terminal control senses a
request and no outstanding request has priority, and the
line is not busy (LINBUSY), and the printer is not busy,
then the enable is generated. If the terminal is on-line
(TERLIN), a transmit enable (XMTENA-) is generated the
same time as the other enable. If the terminal is not
ON-LINE, or ON-LINE and in HALF-DUPLEX, th~n
receive enables (PRNENA, AUX1ENAR, AUX2ENAR) also
are generated.
When a request (AUXIREQ, AUX2REQ, RDRREQ,
BUFREQ, KDBREQ, or SRVREQ) is received by terminal
control, it is stored in a flipflop until that device receives an
enable. These requests are synchronized by clocking them
into register with the terminal control clock (TCCK). The
synchronized request signals then are gated with the busy
signals (LINBUSY and LOCBUSY) and the device line and
local status signals. From there the signals are fed into the
priority logic. If all requests arrive at the same time,
priority is as follows:
When terminal control ,senses a serial receiver request and
the terminal is on-line and not busy, a serial receiver enable
(SR VENA-) and receive enables are generated. When any
enable is generated, eight system clocks also are generated
to clock the data to and from the data bus. Devices
receiving data from this bus (PRINTER, AUXIR, AUX2R,
or transmitter) use the leading edge of this clock (SCLK-).
Devices sending data to the bus (SERIAL RECEIVER,
AUX1S, AUX2S, KEYBOARD) use the trailing edge. A
timing diagram is shown in Figure 3-7.1. A block diagram is
shown in Figure 3-7.2.
Priority is as follows:
a.
Serial receiver
b.
Auxiliary 1
c.
Auxiliary 2
d.
Playback
a.
Serial receiver
e.
Recorder (print buffer function)
b.
AUX1S
f.
Keyboard.
c.
AUX2S
.d.
Once a device is given priority and no status enable is in
progress, terminal control goes to state ONE and gives an
enable to the device with priority and any other devices set
KEYBOARD.
3-51
204.8 kHz
CRYSTAL
9.8304
MHz
~
8
1228.8 kHz
~
RDRClK
1
6
I
~
~
16
614.4 kHz
..£..
0
~
4
~
4
Lr :
Lr
8
0
If
(JI
I\)
76.8 kHz
~l00B
_
1=
~
6
:
8
:
12
75B
50B
12.8 kHz
C/
1>-
9.6 kHz
6.4 kHz
2
0-
2
~
4
I
I
I
r
I
I
I
J
I
51.2 kHz
--,
PNRClK"
--,
J
12.8 kHz
PNHClK"
,
1
6.4 kHz
BYClK ...
"
]
3.2 kHz
BElClK ....
"
1
800 Hz
C800 ...
I
"
rl
SRVClK"
50 b:Ud - 3.2 kHz
75 baud - 4.8 kHz
100 baud - 6.4 kHz
:
2
~
:
64
~
,I;-
NOTE:
SYSTEM CLOCKS ARE LOCATED ON THE TRANSMIT/RECEIVER
PC CARD. SLOT A5.
XMTClK"
,
50 baud - 50 Hz
75 baud - 75 Hz
100 baud -- 100 Hz
'ENABLE'
FIGURE 3-6,9, BAUDOT SYSTEM CLOCKS BWCK DIAGRAM
(j
"
./
(\
\
~,
~
~
RDRCLK=204.8 kHz
~T..j
RDRCLK
RDRCLK
2
TCCK-
U
U
U
U
U
U
U
U
U
U--
U
~~~
-'1 j.lSE!c I
TCSTl _ _ _
y>
U1
r..>
CK1(XXX)ENA-
--I
~
~---------------~
.r
U
t+- I7.32
. lJSec
I
(YYY)ENA-
~7.32j.1SE!c
-I
SCLK-
87.89 lJSec
+I 9.767U~
lJSec
L
U
U
U
U
U
U
U
1T=4.9 !-SEC
FIGURE 3-7.1. TERMINAL CONTROL SYSTEM TIMING DIAGRAM
(
--w4."~K~)
REQUESTS
STORE
REQUESTS
PRIORITY
AND
BUSY
LOGIC
ENABLE
AND CLOCK
CIRCUITS
ENABLES
CLOCK ...
SCLK
STATUS
BUSY
FIGURE 3-7.2. TERMINAL CONTROL BLOCK DIAGRAM
the terminal and stores it in a memory. The data can be
edited while in the memory (within certain limitations) and
then written on tape in line or continuous format. A block
diagram of the cassette system is shown in Figure 3-8.1.
up to receive data on the same bus as the priority device ..
Terminal control stays in state ONE for 80~sec, during
which eight system clocks are sent to all devices. Ten ~sec
after state ONE the device enables will go off and the status
enable is generated as described above. If the device with
priority is in the local mode, terminal control will bring up
the local busy line and hold it for 800 to 900~sec. The busy
line also may be held up by AUXIBUSY, or
record-buffer-full, or by the printer-busy signal. The local
busy line will block devices in the local loop from receiving
enables but will not affect the line loop.
3-8.1 RECORD CONTROL. Record control, block
diagrammed in Figure 3-8.2, consists of three PC cards: the
Record Control PC card, the Record Buffer PC card, and
the Tape Read/Write Control PC card.
NOTE
The Record Buffer PC card is available in
two versions: the standard format version
(TI Part No. 960903) and a dual-format
version (TI Part No. 962285). The Tape
Read/Write Pc. card also is available in
two versions: standard format (TI Part
No. 962281) and dual format (TI Part
No. 969451). The terminal is equipped
either with all dual-format PC cards or all
standard format PC cards. The Record
Control PC card (TI Part No. 960909) is
the same for either set of PC cards. The
difference between the two sets of PC
cards is that the dual-format PC cards
have stra ppable options which permit the
The ASR terminal control timing diagram is shown in
Figure 3-7.1; a block diagram is shown in Figure 3-7.2.
3-8 CASSETTE SYSTEM.
The cassette system consists of two cassette transports and
two motion control circuits. The playback control can be
used on either transport but not both simultaneously. The
playback control reads data from the tape one block at a
time and stores it in a memory. It can then send data from
the memory, one block at a time, one character at a time,
or continuously.
The record control can be used on either transport but not
both simultaneously. The record control accepts data from
3-54
f
r--\
.~
~
STATUS SIGNALS
MOTION CONTROL
CASSETTE-1
CONTROL SIGNALS
I ODO I
~
TACH
~
RECORD
CONTROL
~
U--,
SERIAL
DATA BUS
J
,
rI TERMINAL
L
~
-n-CONTROL
(J1
~ PLAYBACK
CONTROL
REMOT
1.
2.
3.
4.
P
P
5.
R
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
RECORD
BUFFER
128
CHARACTERS ~
I
-
PULSE~
TAPE
WRITE
CONTROL
WRITE DATA
GAP
COUNTER
I
REFERENCE CLOCK 1.067 kHz
FOR SPEED CONTROL
PLAYBACK
BUFFER 96
CHARACTERS
r--
TAPE
READ
CONTROL
READ DATA
GAP
COUNTER
1
I
TACH
PULSE S
CASSETTE-2
'---1
CONTROL SIGNALS
MOTION CONTROL
STATUS SIGNALS
BLOCK FWD
BLOCK REV
CHARACTER FWD
CASSETTE 1 RECORD
CASSETTE 2 RECORD
CASSETTE 1 STOP
CASSETTE 2 STOP
FIGURE 3-8.1. CASSEITE SUBSYSTEM BLOCK DIAGRAM
1
000 1
TERM
CONTROL
DATA
BUS
,
w
...J
«
z'"
w
RECORD
REGISTER
~
I
:t
!;(:I:
:;u
a:!:::
DECODE
CR OR 86th
CHARACTER'
MEMORY
I
~~
MEMORY
TIMING
CIRCUIT
I--
I
!
BLCNUP
I
I
TAPE WRITE
REGISTER
FORMAT AND
CONVERT TO
PE DATA
I
I
MEMORY
ADDRESS
SELECT
CHARACTER
DISPLAY
y.>
U'I
0\
r---
I
I
PRINT
BUFFER
I
I
r
1
l
I
-
WRITE
ADDRESS
READ
ADDRESS
TRANSPORT
I
START OF
BLOCK
ADDRESS
REGISTER
RECORD
~
END BLOCK
'E TX ALSO IS DECODED BY DUAL-FORMAT RECORD CONTROL.
I
MOTION
CONTROL
1
FIGURE 3-8_2. RECORD CONTROL BLOCK DIAGRAM
(~
J
/
I
\
"'--
('
PNHRO~
-L
(
PNHOOQ
erro)
-L
MPNrrO
VES
SET
lNO
(RESET rrATE)
C
I
VES
PNHONQ
(
\
8LCNUPQ
INO
'VES
BlCNUPQ
INO
L.-
p!!( PNHCHE8S )
GENERATE
BlCNUP
"'
j
USING BLeNUP
NO
YES
M1RDRQl
I
1. PADC"""PADRG
2. CLEAR PNHeN
PCNRG
CBKSCN
)
AND MPNSTQ
3. BlCN+1....SlCN
4. RESET BLCNUPO.
NO
IRESETM1RDRQ11
I
PNHDIO
(rrl)
YES
\
I
RECENA
)
--- ----- - -- - - ::R. REVER:~- ::EA::CK~ I ST:;PR::UF::;~-::NU::CO::P
l-I
N:j.:.
.j
CHAFI. FWD.
OVER RECORD (PUNCH)
WAIT
STATE
(
BlCNUPO
NO
r{
PNHeE86
P
r!(
NOt
)
AECENA
---4
PNHONO
YES
SET
BLCNUPO
CPNHO
)
I
Y
RECORD A
CHARACTER;
CHECK FOR
eR CHARACTER
TO END A
BLOCK
~
I
COVPQ
(
CBKSCEO
YES
---4
CBKSPO
(
PNHCNEO
p
SET
CFWSPO
N§[
tNO
NO
XCSPFW
..1.
~
~
~
XCSPRV
~
)
r
YES
SET
CPOHO
YES
-
SET
M1WRRD1 &
M1RDRD1
RESET
COVPD
J
NOJ
CBKSCN·1
-+CBKSCN
-
1.
2.
3.
4.
S.
XERASE
\
--==res
(
<.
PNHCNEa
NO
XPRNBUF
YES
NO
TAPEBKSP
SET CBKSPO
PNHCN+1-+PNHCN
PADCN+1-+PADCN
SETM1RDROl
RESET CFWSPQ
CBKSCN-1 ... CBKSCN
SET
ERASED
I
L-,.
1. PNHCN·1-+PNHCN
2. PADCN-T-+PADCN
3. CBKSCN+1->
CBKSCN
4. SETM1RDR01
S. RESET CBKSPO
I ---4
GENERATE
BlCNUP
USING BlCNUP
1. PADCN-+PADRG
2. CLEAR PNHCN
PCNRG
CBKSCN
& "PNSTQ
J. BlCN+1-+BlCN
4. CLEAR BLCNUPQ
(
SET
\
NO
ReoSTP
0 -+M1WDAT
I
J
\.
\
\
PNHCNE86 )
NOI
SET
CPNHO
\
I
PNH02ii"iST21l 1
I
PNHCN+1->PNHCN
PADCN+1-+PADCN
SETM1RDR01
RESET PNHENARQ
- --
I
I
I
1
- - - [ - - -I
I (ST3)
I
'\
RESET
MIRDROI
I
I
\
t--~-,
I PNHO.O
I
I
I
(PNHENARO
NO
(PNHCNEO
NO
~~
YES
.t.e.:AlEl
BUFREQ
~
PR INTBUFFER
aPERATlDN;
SEND CHARACTERS
ON EATATIME
I
I
I
I
~---!---~
r:r~?5Q
I
\ PCNRG~PNHCN \
I
I
----- -- --- ---------- ----- _L_~_-.J
TO
STO
EXIT
NOTE: 1. WHEN LOW. PNHRDY RESETS PNH01Q THROUGH PNH05DAND PRESas PNHOOQ.
2. ALL COUNTERS AND FLIP-FLOPS ARE CLEARED BY PNHRDY.
FIGURE 3-8.3. RECORD CONTROL FLOW DIAGRAM
3-57
)NO
TYES
SET
L-{
I
I
I
I
I
PNHCNEO ) YES
MPNSTO
YES
8lCNUPQ.
-
)
NOT
I
SET
\
MPNSTQ
H
1
(ST4)
I
~
PRNBUFQ
C8KSCN
MPNSTD
3. RESET ERASED
)-
<-
,-----J
PCNRG
\
r
~: PADRG"PAD~
. PNHC"""tNRG
1. PADRG+PADCN
2. CLEAR PNHeN
r- I
PNHCN+1-+PNHCN
PADCN+l-+PADCN
SET MtWRRQl
SETM1RD01
5. RESET CPNHQ
NO
)!!2.
~
PRNBUFQ )
(
~
1.
2.
3.
4.
r!(
)
j
\
)
YES
"-
SETBLCNUPOJ
CBKSCEO
<.
ERASED
~
NOl:
H
PNHOND?
PNHCRD
l
---4
INO
SET
~
Ni![
)
)
YES
-1
PNHONO
FWSPQ
NO
(RECENA
r~
HIGHTO LOW
(
<.
IYES
'----==::l
m.t
~
HI6H10 LOW
YES
~
~
COVPO
TO
rro
1
The first data bit is now clocked into the 1024-bit memory
using the memory wri te enable (M1WRENA). Then the first
bit is read from the memory into the character display by
MEMORY-1 read clock (M1RD1CK). Then the memory
address is changed~ and the next data bit is clocked to the
memory data line using the other edge of M1RD1CK).
Then another write enable is generated, and bit 2 is stored
in the memory. In standard format operation, this process
is repeated until all 8 bits (7 data bits and 1 bit for carriage
return decode, and ETX decode if enabled on Dual-Format
PC cards) are stored in the memory and displayed. Figure
3-8.4 shows the memory timing sequence.
handling of either standard-formatted or
binary-formatted data.
In addition, a strappable option permits
the recording of a block of data (in
CONTinuous tape format) to be initiated
when the ETX control character is
received from the communication line
{;~.. 3ections 2-6.4 and 2-7.6 for
implementation of this option).
'I1te basic operation of the standard-format and dual-format
PC cards is the same. Any differences in operation of these
two versions are noted in the following description.
NOTE
In binary-format operation the process is
repeated until all 8 bits are stored in the
memory and displayed.
Record control accepts data and stores it in a 1024-bit
memory. The last character entered into the memory is
displayed on the character display. While data is in the
memory, it can b~ modified using the tape forward (TAP!)
and tape reverse (~APE) keys on the keyboard. Data in e
buffer can be printed without altering the contents of the
buffer by activating the PRINT switch, and data in the
buffer can be erased by activating the ERASE switch. In
line format, record control puts the contents of the buffer
on taPe when the recorder is manually switched OFF, or
when 86 characters are loaded into the buffer, or when the
carriage return character is decoded. In CONTmuous tape
format, record control transfers the contents of the buffer
to tape either when the recorder is manually switched OFF,
or when 86 characters are loaded into the buffer.
Each time a character is sent to the memory (CPNHQ), the
punch address counter and the punch character counter are
incremented by one. If the character backspace counter is
not equal to zero (i.e., the buffer has been backed up), it is
decremented by one. If a carriage return has been decoded
in line format, or if the punch character counter is equal to
86, the block counter is incremented by one.
NOTE
If an ETX control character is decoded
by the Dual-Format Record Buffer when
in CONT'muous tape format, the block
counter is also incremented by one.
NOTE
When strapped for standard format
operation, the optional dual-format
record control also transfers the contents
of the buffer on tape when the ETX (end
of text} control character is decoded. The
ETX decode is a strappable option (see
Sections 2-6.4 and 2-7.6 for
implementation instructions).
This process loads the contents of the punch address
counter into the punch address register and clears the
punch counter, the punch counter register, and the
character backspace counter. The tape write controller now
senses that~a block is to be written on tape (BLCN+O) and
will start the tape write controller. The tape write
controller then starts moving the tape (TPWFW), loads 170
into the block character counter (256-86=170), and writes
the remainder of the interrecord gaps as the tape comes up
to speed (CNTQ).
Each of these functions is explained below. A record
control flow chart is shown in Figure 3-8.3.
When the tape is up to speed, the preamble (01010101) is
written on tape, after which the fIrst character is read from
the memory into the write data register Using M1RDRQ2
and M1RD2CK. The fIrst character then is clocked out of
this register by M1RD2. Then the block cli.az;acter counter
and tape write address counter a're incremented by one.
This process contiIiues until either the block character
counter is equal'to 256 (86 characters) or the end-of-block
signal (WRTEBD) is sensed. If end-of-block ·is sensed, the
tape write controller will write null characters on the tape
until the block character counter is equal to 256: When the
The record control uses recorder enable (RECENA) and
eight system clocks (SCLK) to clock data into a
serial-to-parallel converter if the recorder is ON (PNHONQ).
If the recorder is OFF, the data is clocked in on top of the
old data (overpunched). This data is then decoded and
loaded into a parallel-to-serial register. If in LINE tape
format and a carriage return is decoded, or if in
CONTinuous tape format (dual-format record control only)
and an ETX is decoded (ETX option installed), bit 8 is
forced to a ONE; otherwise, bit 8 is forced to a ZERO.
3-58
\.
~i
,..-..,
,~
!
T .. tn04.8msec
25
21
2B
29
30
31
32
~1~~~~1 --.J
M1RD2~L_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----I
I.
I
WRITE l/READ 1 ADDRESSOO-06VALID
READ2ADDRESS 0 0 - 0 6 V A l I D - - - - - - - - - - - -___-i
• I •
I
MICKENA
M1AD07~
M1CSl
L~
J
--.J
,IL-_ _ _ _ _ _ _ _ _ _ _ _---'
M1CS2
~
\C)
r --
M1CSJ
I
--I
-
-
lL.._ _ _ _ _ __
M1CS4---,
M1WRROl OR
~l~~~W~1
--.J
M1WRENA-
M1R01CK(ClK ON NEG. EDGE)
M1R02CK(ClK ON NEG. EDGE)
BIT 1
BIT2
BIT3
BIT4
BITS
BIT6
BIT7
BITP
BIT 1
BIT2
BIT3
FIGURE 3-8.4. RECORD MEMORY TIMING DIAGRAM
BIH
BIT5
BIT6
BIT7
BITP
I
I
l.
TAPE WRITE
CONTROLLER
r-
PJlHRDV
\.
110
(
-1
CENTER
I
GENERATETMFW
~~:~=
DIRECTION
(
>
TJlWD1Q
1110
O ......ENO
o ~ _END
...... DATENQ
o~_
f-
(
8LCN .. O
WllTENO
~
~
(
)
H
(
I'~-I
I
WRTEBD
IVE.
WRTEBQI
f PREA_lE
)
~
I
I
,
n
M
M
I
f
I
II
hWRTEB02
LPREAMBLE
IUITS)
WRfTELAST
M'CS2
UITS OF alOCK
CHECK CHARt ..
OaTAPE
)
INULLI
tV••
I
-t--
II
I
TWCllCLI<)
:Iv..
O.. OAT£IO
I
J
,,_/
I BLOCItCH£CJ{
I CHARACTER AND
POST.RlE
INTER8LOCK GAP
UINCHES NOMINAL
-I
II LPOST_lEIBBfTSl
~
I
r-<
USlNE
BLCNDN
DATA CHARACTERS
AND NULLS (IF NECESSARY)
TOTAL OF II CHARACTERS
as CHARACTERS
)
L..lli..
aLtN - t
VES
190 x II'"" 720 BITS
.i
MlROl
~8LCN
WATEIOt )
I-- DATA BLOCK
----
O~TI'W02Q
1
_HCLK )
-ryES
0 ..... MEMENO
)
O..... TPW010
r
BCHtNO
i.e. (N)-"
TWCHelIC
,VES
.i
I
f
I
I
I '~WRTEfIQ I
H
I
~
.i
11 . .
YES
i
NO
1..... seSELO
lWAOCN+l
.... TWADCN
M
WRITE POSTAMBLE
r
IlEllEND
VES
:':~lOCJ
110
enD
I
'-PSAMQ
CHARACTER
(810' mot)
DNTAPE
~
I
ER
)
1+1.1~1.1
CHARACTER CNI
FROM RECORD
BUFFER MEMORY
}.!!!.
)
1 + BCHCfII
.... BCNCH
I
GAP
r---!!L(
TWtIICLI<
WRTOT\I
TM02Q
I
YES
READ 8-BIT
O~_TQ
f----!!!{
~
I
TMOATA
..... WRTEBG2
(
lWCHell
j YES
WRITE CHARACTER
INIDNTAPE
GENERATE
.,HDRC12
ym----
~.CIICII
~
n
I
I ..... DATENQ
1+8CHC......
BCHeN
:::0
INUlU
TAI'£
j
CLEAR WRTQTR'
LOAD 118
(11111.10"
BLOCK CHECk
CHARACTER ON TAfIE
WRITE CHARACTER
r VES
o ~ WRTEBOI
~
WRITE FIRST
UITSOF
AS NUll
r-- 001
_0.
~
'~VES
J
~NG
lWCHClK )
,~-
B
r
WRTEl02
TAPE;'~I.I
too
~
I
\.
PREAMBLE ON
I '~TMO'Q I
(
.iNG
WRITE 01810101
,NO
.i
J
IVES
I
n
o .... BtsEla
~
(
It . . . MEMENO I
START
TAPE
WRITE
FUNCTI N
OR
HOLO
RESET
)
}m-
"'l1li
-
VES
BcstLQ
\.
100
CltO
r-<
VES
J
.iNO
>nO
o . . . TIW01Q
o ~ TM02Q
o . . . BlCN BLOCK
LOAD '(1lIII0lII0I
·TW"I)CN
1
DATEfIQ
rc
BLOCK CHECK CHARACTER (16 BITS)
DATA FORIIAT ON TAPE
BLOCK CIlARACTtR CQUllTER
11l1Il0Il8,
IICIICII:
'LCN: BLOCK cournR
4 IITS LONE (MAX. COUNT' lSI
CDJlTAIIII DIFFERENCE BETWEEN
IIU_R BLOCK. RECEIVED
AND RUMlER BLOCKS
WRITTEN onAPE
CN1ll: OUTPUT OF GAP COUNTER
IN!:
VARIABLE USED IN FlOW CllART ONlV.
lWAOCN:
TAPE WRITE ADORESS COUNTER
fOR RECORD BUFfER (MEMaRY·n
1 BfTS LONG.
WRTDTRG: WRITE DATA REGISTER
WRlEBO:
END·Of·BLOCK fLAG
(ITH BIT Of WRITE DATA REGISTER)
FIGURE 3-8.5. TAPE WRITE CONTROLLER FLOW DIAGRAM
rf"
\,-~/
3-60
(
C=C~,K__
m~l~, __
I
JUUUl __________
fTl
lWCHCLK
.F==!'5&.25 uSEC
800Hz ,..TI'I'/02Q- -
~
I
I
_____ JUUUUUl_ - - - - - f"Tl
I
~ RERINHQ
0.... BUFFULO
"I .... RSBLO
::I NO
r-~
(
-I
~
J NO
-1-1
...1.
ROROI
,
NO
8FWSPQ
-
RORREn
RORDN
ill
0 .. RERRORO
O.. BUFFULO
-
RDRSTn
I
I
II
r. -
)
'l .... RDRENAD.
'1 .... RUREBO
GENERATE
RERINHO
(
1'-+TRSYNco.l
)
-- 1
RORROY
YE.
--'-NO
PLAYBACK
"ERRon"
I
.r-- -
..i.
~
NO
TPRQO
TyES
,YES
L _ _ _ _ ..J1
+
..i.
l
I
I
I
I
I
II
J
RORDNO
O.. RSBlO.
0 .. RSCHO
O-+RFEEO
r--<.
GENERATE
BFWSPO
Up_
BUFFUW 'NO
)
BBKSPQ
YES
-
J
~
.1
TAPE READ CONTROLLER
PLAYBACK ''ON"
)-!!!- I
r - -e
1-------r-c ::r ) r I
r
KEYBOARD LOCKOUT;
LOGIC ON REMOTE
CASSETTE CONTROL
::IYE.
C
,...
r'
r
RDRDF
...1.
C
'ARO
..i.
KBDLOC
._.
r'I
RDRRDY}--
4.9}.lSllC
,
(
READER CONTROLLER
I
~
O-M2WDAT
r--
..i.
ERRCKO)
YES
M2AO + 1
-+M2AD
GENERATE
RBlCNCK
RORelK
RCHCND )
TI!
RBTeNOH
\- YES
I
NO
~
(
+
:I NO
TR5/4T
NO
~
l·l ~
RERRORD
J
+
e
TRM
~.
I
NO
GENERATE
M2WE
I
RERRORO)
i--'
)-.!IL
RCHCN+1
-+RCHCN
--{
TR1/4T
)
YES
I
READ (FROM TAPEI DATA BLOCK
AND STORE IN BUffER MEMORY.'
ALSO DETECT BIT-DRDPOUT.
MlAO+1
-+M2AO
GENERATE
RBTCIII
I
GENERATE
U2WE
I
I
~\
~.
(204·BKCI
READCK
-fl.f1.I1.I""
I
TPRDST
I
TPROl
:
.,......."..
IIEAD 1ST BIT
TRSYNC01~
_____
TRDATA-
10
:
•
fl;
TROl
J
i
i
n
~
~
:--J ~I
~
II
L--..
TRQ3
TRSYNC02
TR1/4T
---,
TR3/4T
----,
TRQ2
~
~
~
I
I
II
1
J
i
I
1I
1
L
rL-
LL"--
•
I
II
II
•
i
,
~
~EFO~~PDAT,..II
BLOCK
TRSY
:
------~i--~~
l
VJ
'"
U1
712
TR1/4T
________
I
~
RBTCNOH
~
~L--
1
f""i2i"1
I
n
(901
i___
· _~~
_r
TPR02
•
I bit 8
of
I Preamble
bit 1
OI,r.l
t
bit 1
-'-r
RCHCN
= 167
Char. 2
----t-+
1 Postamble
1-...L--1.
...1--------Bit 7
90
PO$tambl.
'I
RCHCN
= 166
1 Preamble
86 Data
2 Block Check
I'
I
M2WE
(TPRQ2*TRQ3)
READ 90 CHARACTERS. 720 BITS
I
I
TPROl
I
RCHCN
= 168
j..
RCHCN
""255
....!.- -170
RCHCN
MEMORY - 2
-~-
BIT 8 - PREAMBLE
T
TR3/4T
10
15
21
I
..;w
r-
TR21/4T
---~-'---r--.--'--r--~--r--r---,--~t~I--'---'--~l
O
w ..;
I I I
I I I
I I
314 514 7/4
11/4 1314 15/4
19/4 21/4
1
!
BLOCK CHECK
CHARACTERS
16BITS
0
~
0:
688
6B9
704
7 bits of Postamble
711
712
UNUSED
767
FIGURE 3-8.9. TAPE READ CONTROLLER TIMING DIAGRAM
T
a:
w
B6 DATA dHARACTER!
688 bits
1-0:
TR5/4T
TRTlMECK
.
000
001
1
CHARACTER 1
CHARACTER 2 TO CHARACTER 87
CHARACTER 88
DATA CHARACTERS UP TO 86
PREAMBLE
OR NULL CHARACTER TO 861F DATA IS
10101010
CHARACTER 89
CHARACTER 90
NULL
NULL
POSTAMBLE
CHARACTER
CHARACTER
10101010
LESS THAN 86 CHARACTERS
FIGURE 3-8.10. BLOCK OF DATA ON TAPE
/
1
HIGH=ERASE
DATA PHASE
BIT
o --
-
DATA
BIT
BIT
l
PHASE
DATA
PHASE
DATA
I
BIT
BIT
BIT
BIT
I
I
I
~1/4"'"
I
-+of
I
-+l
1
2/4T
I
I
I
1+1
3/4T
1
1
~
I
I
I
-+l
I
-..j
I
TAPE SPEED = 8 ips
T = 156.25 ]J)EC
4/4T
1
~I
I
5/4T
I+-
FIGURE 3-8.11. PHASE-ENCODED (PE) DATA TIMING DIAGRAM
3-66
(
the error to be inhibited, and the error block will be
transmitted and reading will be continued in the mode used
before the error was detected. At the end of the error
block, the error flipflop will be cleared.
b.
The reader control causes data to be transmitted to the
serial data bus upon command (continuous read, one block
at a time, or one character at a time). The tape read
controller takes the data off the tape and puts it in the read
d.
Two 8-bit null characters (00000000)
e.
Seven bits of the postamble (the eighth bit is
not put in memory).
c.
buffer memory. The reader controller takes the data from
the buffer memory and sends it to the serial data bus. The
sequence of events for sending one character to the serial
data bus from reader memory is as follows:
a.
Send a reader request (RDRREQ) to terminal
control.
b.
Wait for a reader enable (RDRENA) and eight
system clocks (SCLK) to take the data from the
memory.
Data is removed from memory until the reader controller
detects a ONE in the 8th bit of a carriage return (or ETX)
character or until 86 characters are sent to the serial data "
bus.
NOTE
In binary format operation, data is
removed from memory until 86
characters are sent to the serial data bus.
("
Depending on the reader controller mode, the controller
will either stop at that point or cause the tape read
controller to read the next block from tape.
(
3-8.2.2 Tape Read Controller. The tape read controller does
the task of reading a block of data from the magnetic tape
and storing in the reader buffer memory (see the flow chart
and timing diagram in Figures 3-8.8 and 3-8.9). A block of
data is shown in Figure 3-8.10. When the tape read
controller detects that the buffer is not full
(BUFFULQ=ZERO), it causes the tape transport to start
and it searches the tape for the block preamble. Once the
controller senses the first flux change of the phase-encoded
(PE) data, a timer starts which produces a clock at exactly
l/4T (see figure 3-8.11 for PE data timing). If the first bit
has remained good for at least 1/4T (time), a flipflop is set
which inhibits the read circuit from resetting until the
whole block is read. After the first preamble bit is sensed as
good (true data), the next 7 bits of the preamble then must
be detected. After the eighth bit of the preamble is
detected, the reader buffer memory is enabled and data is
entered into the buffer memory in the following order:
a.
All data bits up to eighty-six 8-bit characters
Zet:os to fill the buffer up to 86 characters, if
. 86 data characters were not written
The data on the tape is recorded in a phase~ncoded (PE)
format. The tape read controller therefore must convert the
PE data to digital data for storage in the reader memory. PE
data is self-docking; therefore, no data clock is necessary to
read the data from the tape (Figure 3-8.11 ~hows the PE
data timing). On a data transition a timer is started which
clocks the data bit into memory at exactly 1/4T. The tape
read circuit is then "locked out" until the phase bit
transition passes at 1/2T. The timer then produces a clock
at 3/4T which resets the tape read circuit to sense the next
data transition. If no new data transition occurs by 5/4T, a
bit dropout is signalled and the error flipflop is set.
At this point the reader buffer memory is fIlled with zeros
instead of data, and the tape read circuit continues reading
data until it detects a gap. If no bit dropouts are detected
(5/4T clock), the timer is reset at each new data transition
and the data is clocked into memory at each 1/4T. After all
data is docked into memory (through the fust 7 bits of the
postamble), the tape read controller then seeks the
interrecord gap between blocks. When the controller has
detected no data for more than five bit times (21/4T), the
tape read controller signals that the tape is in an interrecord
gap and stops the transport. It also sets the buffer-full
(BUFFULQ) flipflop to start the reader controller.
3-8.2.3 Playback Buffer Memory. The playback (reader)
buffer memory, located on· the Playback Control PC card,
consists of three 256 x 1 random access memories and
associated address counters and character counters. The
memory is capable of holding 768 bits or ninety-six 8-bit
characters. The memories are addressed by two 4-bit
counters, giving eight address lines to each memory, and
three flip flops which provide a chip select line to each
memory.
A character counter is provided to the tape read controller
to count the number of characters put into the memory.
The same character counter is used by the reader controller
to count the number of characters taken out of memory_
Data is put into memory 1 bit at a time, 8 bits per
character. 32 characters per memory. When the tape read is
placing characters into memory, the playback buffer
memory address is set to ZERO, and the character counter
is set to 166. Each time a data bit is written into memory,
Last bit of preamble
3-67
/
T
"A.
,I:
~
-w ===r.:==
I
INTERllOCK GAP CQUMTUSIG...
,= 1.1 INCHES MIMIMUMI
CODETAilLEFOAREIItOTECONTROL
CODEI'TS
, '3
,
4 STROlE
111'
a I 1 1
1 a 1 1
,
,
,
,
,
o
,
a
,
,
,
,
101.
•• I'a ,,
,
,
1 00'
.011
1 I • 1
1 0 1
l'
1
10' 1
111.
0110
., , ..
11'
• 1 O.
'
P~~r,.tO
FUNCTION
RORON
"PLAYIACIC:0111 IDCII
PLAY....CK OfF lDClI
RECOIIDONIOC2)
RECQIIODfFIOt4)
REWINDCAS-I
RfWllIIDCASoZ
LOolYlOR FFWD CAS-'
LOAD OR FFWD CAS-Z
ILOCKfDIIW'AIIO
'LOCKREVERH
tASlETTl·IIIICDRO
CASIlm·2I1ECDRD
.NOOflECllAIIACT'E1L
RDAOF
ReDON
IlCOOF
XIIEWI
. ""
-
XLOIFW!
XLO/FWl
XISPRY
xelllCO
XCZRCD
KACHN
/""'"
XCAmP ......-rE·"'''
CAlSETTE·2S'JlN1
.......
FIGURE 3-8.12. FWW DIAGRAM OF FUNCfIONS PERFORMED BY THE REMOTE CASSETTE CONTROL PC CARD
,
f
\.
\-
the address counter is incremented by one. and each time
an eighth bit is received to be written into memory. the
character counter is incremented by one until it overflows.
after counting 90 characters. The characters are the
preamble (only the last bit actually written in memory). 86
data characters. 2 null characters. and the postamble (only
the first 7 bits actually written in memory).
counts 16 data bits without a bit dropout (TR S/4T signals
a dropout), it assumes that it is in the middle of a block of
data and starts to search for the next interrecord gap. When
no data is detected for a period equal to 21/4T
(T=156.2Spsec). the controller assumes that it is in the
interrecord gap and should stop the tape. However. the
transport's minimum stop time is only 0.2 inches (1 inch =
132.415 tachs) of tape. while the maximum start time is
0.5 inches. Therefore, a delay timer is started when the gap
is detected. delaying stopping the transport for
approximately 64 tach pulses. These 64 tach pulses. plus
the minimum stop distance of the transports, allows enough
distance so that when the transport is started again to read
the next block. it wiil be up to speed before it is out of the
gap and into the data. The delay timer does not actually
count tach pulses to get a 64 tach pulse delay, but instead
counts the reference clock (TRFCLKB) used by the
transport for the phase lock loop which controls motor
speed, When the motor is running at full speed, the phase
lock loop ensures that a tach pulse occurs at each reference
clock (TRFCLKB) with long-term speed variation of no
more than 1 percent. Since the motor is running at full
speed during the block reverse, the proper condition exists
such that 64 reference docks (TRFCLKB) should
approximately equal 64 tach pulses; therefore, the
transport may be stopped after the timer has counted 64
reference clocks into the gap.
When the reader controller is taking characters out of
memory, the playback buffer memory address is set t.o one.
and the character counter is set to 170. The memory
address is set to one to skip the last bit of the preamble
when the reader starts sending data to the serial data bus
from the memory. Each time a data bit is taken out of
memory and sent to the serial data bus, the memory
address is incremented by one. Each time an eighth bit is
taken out of memory and put on the data bus, the
character counter is incremented by one. The reader
controller continues to take data out of memory until a one
is seen in the eighth bit of an 8-bit character, or the
character counter overflows after counting 86 characters.
NOTE'
If the Dual-Format Playback Control PC
card (TI Part No. 969481) is set for
standard format [TERLINE- switch
(S1-1) is open and the BINFMT- switch
(S1-2) is closed]; the reader controller
will continue to take data out of memory
until a ONE is seen in the 8th bit or the
character counter overflows after
counting 86 characters. If the terminal
ON-LINE/OFF switch is in ON-LINE
position and the Dual-Format Playback
Control is set for binary format
[TERLINE- switch (S1-1) is closed and
the BINFMT- switch (S1-2) is open], the
reader controller will continue to take
data out of memory until the character
counter overflows after counting 86
characters.
3-8.3 MOTION CONTROL. The Motion Control PC card
controls rewind, load, and fast forward operations of both
cassettes; generates write, forward, reverse, and fast
commands; and controls the ready signals for the playback
and record. Each of these functions is explained in the
following paragraphs. A flow chart of the motion control
function is shown in Figure 3-8.13.
3-8.3.1 Rewind: to rewind tape: (1) the cassette door must
be closed. (2) the tape must not be on the left end, (3) the
cassette tape must not be moving (either forward or
reverse), and (4) the cassette transport must not be
"BUSY" (reading or recording). When these three
conditions are met and the REWIND switch is actuated. the
rewind latch will be set (C1RWQ).
Either condition signifies the end of a block, and the tape
read controller must then put a new block of data into the
memory for the reader controller to send to the serial data
bus.
This generates reverse and fast commands for the transport
until either the STOP switch is actuated (STPCA 1), or the
left end of the tape is reached (TILEQ).
3-8.2.4 Block Backspace Controller. The block backspace
controller, located on the Remote Cassette Control PC
card, causes the tape to back up one block (see Figure
3-8.12). When a block reverse command is received by the
block backspace controller, the tape transport moves the
tape in reverse. The tape read circuit reads the tape, and the
block backspace controller counts the number of data bits
read in the reverse direction. When the backspace controller
3-8.3,2 Load: To load tape: (1) the cassette door must be
closed, (2) the write tab must be in place if the transport is
in the RECORD mode. (3) the tape must not be at the right
end or moving, and (4) the cassette must not be "busy".
Then if the LOAD/FF (fast forward) switch is actuated
while the tape is on the clear leader (BOEOCAl). the load
flipflop IS set (LOAD1Q). LOAD1Q generates the
3-69
NO
LD80no
0 .... TIRED
a-TlLEO
0- CtRWll
YES
BOEDeAI
Y'S
LOAD 96
_0110
0- CIFWD
0 .... LOAQ1Q
0- LOIOT1Q
.. CICNT
WITH
etCNTLOA
O.... GAPIQ
--i
- - - - - - - - - - END INDICATORS
READY SIGNALS
O-lOAOIQ
0- LD80T1Q
n • lOA01Q
o • LOBOTIO
0- GAPIO
!)
~
o
I.
-I .
REWIND
·GA,lQ
LOAD AND FAST FORWARD-----_ _ _ _ _ _~
CIACO
WAITE '"00(
YES
YES
TfWO'O
WAITEGATA
DNTAPE
J ORWARO CO,,"MANO
TftRSll
E.RASETAPl
HIGH SPUD FWD REV
TPIIO'
RIAODATA
FROM TAPE
GAP CNTA ((ltNT!
UP DWN COMMAND
ClRm
REVERSE CO'-MANO
.REVO'
.LOCK REVERSE
- - - - T""~OIlllANDS'-----
FIGURE 3-8.13. TAPE CASSETTE MOTION CONTROL FLOW DIAGRAM
(
TURN ON "READY'
DISPLAY FOR
CAS$(Tl( 1
NO
tape-forward (' .mmand for the transport, and if the
transport is in the record mode, it generates the write
command. When the tape reaches the end of clear leader,
the BOT flipflop is set (LDBOTIQ). The load controller
then waits for BOT to come up (BOT perforation in the
tape). When BOT is sensed the gap flipflop is set
(GAP1Q). and the gap counter is loaded. The GAP is then
written, and the load, BOT and gap flipflops are reset.
3-8.3.3 Fast Forward: To perform fast forward operations
the same initial conditions must be met as for load
operations. except the tape cannot be on clear leader. When
these conditions are met, the forward flipflop is set
(CIFWQ). This generates the forward and fast commands
for the transport until the right end (TIREQ) is reached or
the STOP switch is activated (XSTPCAl).
3-8.3.4 Write. The write command (TIWRITE) is generated
when the transport is in the record mode (CIRCD) and
either the load (LOADIQ), tape write (TPWOIQ). or tape
erase (TPERSQ) f1ipflops are set.
3-8.3.5 Forward: The forward command (TIFWD) is
generated when the write command (TIWRITE) is
generated, or fast forward flipflop is set (CIFWQ), or when
the cassette is in playback mode and the read flipflop is set
(TPRQO).
3-8.3.6 Reverse: The reverse command (TIREV) is given
when the rewind flipflop is set (CIRWQ) or when the
cassette is in the playback mode and the block reverse
flipflop is set (BREVQl).
3-8.3.7 Fast: The fast command is generated when either
the fast forward (CIFWQ) or rewind (CIRWQ) f1ipflops are
set.
3-8.3.8 Ready: The ready signal is generated if the cassette
,...._ _ _ _ _ CASSETTE 1
REWIND
LOAD/FF
(
STOP
STOP
CASSETTE 2
•
RECORD
PLAYBACK.
•
READY
READY •
•
END
•
PLAYBACK
BLOCK
FWD
CHAR
FWD
LOAD/FF
STOP
STOP
END.'
RECORD
PLAYBACK CONTROL
CONT
START
REWIND
(I)
RECORD CONTROL
•
•
CHARACTER
ON
ERROR
LINE
OFF
OFF
LOCAL
KEYBOARD
LOCAL
PLAYBACK
PRINTER
BIT 1
FIGURE 3-8.14. ASR CONTROL AND DISPLAY PANEL
3-71
is in place, is not performing fast or load operation, and is
not on clear 1eader. If the above conditions are met and the
cassette is in the record mode with a write tab, the READY
lamp will illuminate and the recorder ready signal will be
generated (PNHRDY) if the record control is not OFF. If
the cassette is in the playback mode, the READY lamp will
illuminate and the playback ready signal will be generated
(RDRRDY) if the playback control is not OFF. If the
RECORD or PLAYBACK switches are in the LINE
position, the data terminal must also be on-line, or the
ready signal will not be generated.
The left end flipflop is set (T1LEQ) when the tape is
reversing and the end is sensed. The right end flipflop is set
(T1REQ) when the tape is moving forward, not during a
load, and the end is sensed.
open collector TTL gates. The momentary switches on this
PC card have debounce circuits consisting of inverter
latches. A status register included on this circuit sends
informadon (RFEED, RERROR, BOEOCA1, BOEOCA2.
KBDLOC, PRNLOC, PRNOFF) to terminal control in serial
form, using status enable (STAENA) and eight clocks
(SCLK). The upper display and control panel is shown in
Figure 3-8.14.
3-8.5 CASSETTE TRANSPORT. All motion control,
read/write, and status-sensing electronics are contained.on a
single PC card mounted on the rear of the transport (see
schematic 960334 in Appendix C). A block diagram of the
read/write electronics is shown in Figure 3-8.15. Since the
head has a single read/write gap, reading and writing cannot
occur simultaneously. When writing occurs, the write data
, appears at the read data outputs.
3-8.4 DISPLAY FUNCfIONS. The Display PC card consists
of the switches and indicators necessary to control the tape
cassettes. The indicators are light-emitting diodes driven by
WRTTAB
3-8.5.1 Tape Write Circuit. Writing is inhibited when a write
tab is not sensed by the write tab switch. When a write tab
WRITE
TAB
SWITCH
WRITE
GATING
WDATA
HEAD
CENTER
CAP
LEVEL
DETECTORS·
RDTAGATING
RDTB-
PEAK
~--I DETECTOR ~-~
FIGURE 3-8.15. READ/WRITE ELECTRONICS BWCK DIAGRAM
3-72
(
engaged, forcing that pinch roller into contact with the tape
and capstan. The capstan motor controls the tape motion in
this case, while the reel motors supply only enough torque
to keep the tape in tension. The circuits to move tape
forward or reverse are identical except that the functions of
the forward and reverse components are interchanged.
is present on the cassette and a write command is present
on WRITE-, the digital data on WDATA is gated to the
head drivers. Each head driver is a current source which
forces sufficient current through half of the head coil to
saturate the tape.
3-8.5.2 Tape Read Circuit. During a read cycle, the flux
reversals on the tape moving past the head cause generation
of a voltage across the head coil. This signal is amplified by
the read preamp to a level sufficient for use by the peak
and level detectors. The level detectors provide noise
immunity by allowing only signal peaks above a certain
level to reach the output pins. The peak detector detects
the. point where the head voltage changes direction, which
is also the point where the flux of the tape changes
direction, and an output data transition occurs. A data
transition may occur on RDTA- or RTDB- depending on
the direction of the flux change, but the information is
containM in the transitions rather than the levels.
3-8.5.7 Capstan Control Circuit. The capstan motors are
controlled by a phase-locked loop. When a forward
command is applied to the transport, the forward solenoid
is immediately energized. The forward reel motor torque is
increased ·to provide takeup tension, the forward
tachometer signal is gated into the loop, and a 10- to
25-millisecond delay is initiated to allow the pinch roller to
engage the tape and capstan. At the end of this delay, the
capstan motor driver and the integrator are enabled,
completing the servo loop. The initial conditions imposed
on the integrator result in an initial motor voltage of
approximately 3 volts. As the speed of the tape and capstan
motor increases, the frequency of the pulse train from the
forward tachometer increases, and the error pulses out of
the phase comparator become shorter. When the frequency
of the tachometer pulses become higher than the reference
frequency, the phase comparator puts out a different pulse
train, and the motor voltage is decreased. The steady-state
condition is reached when the motor is making small
positive and negative excursions from nominal speed.
Timing for a typical operation is diagrammed in Figure
3-8.17.
3-8.5.3 EOT and BOT Sensors. Optical sensors are used to
sense the clear leader at each end of the tape as well as the
EOT and BOT perforations in the tape. Light sources (small
lamps located in the guide posts directly under the ~enter
of the tape guides) are sensed by photo-transistors mounted
over holes in the center of the tape guides. The
photo-transistor signals are buffered by operational
amplifiers and converted to TIL-compatible levels at the
card interface.
3-8.5.8 Reel Motor Control Circuit. The reel motors
perform three distinct functions, requiring three different
amounts of torque. During all operations one reel motor
applies a low hold-back torque to the supply tape spool,
and both reel motors apply this torque when the transport
is idle. During read/write operations additional current is
supplied to the reel motor, driving the takeup tape spool so
that it applies additional take up torque. During fast
forward and rewind operations 12 volts is applied to the
takeup reel motor, resulting in the high torque required to
move the tape at an average 60 inches per second (ips).
Timing for a typical fast sequence is diagrammed in Figure
3-8.18.
3-8.5.4 Switches. When actuated, three rmmature sensor
switches on the tape transport sense that the tape cassette is
installed correctly, that the cassette door is closed, and that
a write tab is on the cassette. Both the cassette-in-place and
door switches must be actuated before the transport will
move the tape.
3-8.5.5 Tachometer. The appropriate tachometer signal is
available at the card interface for use in keeping up with
record locations. The forward tachometer signal is enabled
when a forward command (FWD-) is present, and the
reverse tachometer signal is enabled when a reverse
command (REV-) is present. One tachometer cycle occurs
each time 0.0075 inch of tape passes a capstan.
3-9 OPTIONAL DEVICES.
Several optional functions are available for the 732/7 33
models as plug-in PC cards, including line interface drives,
an answer-back memory, and an auto device controller. The
theory of operation of this equipment is explained in this
section.
3-8.5.6 Motion Control and Deck Status Electronics. A
block diagram of the motion control and deck status
electronics is shown in Figure 3-8.16. Tape moved fast in
either the forward or reverse direction is controlled by the
reel motors. The solenoids are disengaged so the tape does
not touch the capstans or the pinch rollers. During
read/write operations, the forward or reverse solenoid is
3-9.1 LINE INTERFACE. The standard terminal interfact.
meets requirements of EIA standard RS232C. The terminal
3-73
EOT
SENSOR
BOT
SENSOR
f----
~
GATING
TACHOMETER
..
~
11
GATING
REVERSE
TACHOMETER
.10.
If
,.
PHASE
COMPARATOR
f--
INTE~
GRATOR
4
"---
FAST
FAST
STOP
DELAY
650 msec
GATING
GATING
__
~
f-
REVERSE
SOLENOID
f--
CAPSTAN
MOTOR
DRIVER
f-
FORWARD
CAPSTAN
MOTOR
I--
CAPSTAN
MOTOR
DRIVER
I--
REVERSE
CAPSTAN
MOTOR
I--
REEL
MOTOR
DRIVER
f-+
FORWARD
REEL
MOTOR
GATING
f---
REEL
MOTOR
DRIVER
f--
REVERSE
REEL
MOTOR
..-.
LOGIC
f------~
GATING
PINCH
ROLLER
ENGAGE
DELAY
20 msec
GO
FORWARD
REVERSE
FAST
SLOW
FORWARD/REVERSE
CASSETTE
IN PLACE
SWITCH
DOOR
SWITCH
FIGURE 3-8.16. MOTION CONTROL AND DECK STATUS BWCK DIAGRAM
"'\
SOLENOID
DRIVER
U
It
t
SOLENOID
RELEASE
DELAY
4 seconds
lEV-
FORWARD
SOLENOID
-f
REFERENCE
CLOCK
FWO-
..,....
-~
FORWARD
TACHOMETER
~
SOLENOID
DRIVER
~
"....,..
~,
i
WRITE
FWD-
READ REVERSE
~
I
----.i
REV-
~
1
0
WRITE-
1
0
r
70 msec DE LA Y
1
0
FAST-
r--
I
----+I
READ FORWARD
J
J
f.--- 70 msec DE LAY
WDATA- 1
0
rII r· .:. ·:--·ml
RDTA0
[1J [-.~~. · IIII
1111· · · · · · · ·1111
1111· . · · · · · IIII
~
1111· .. ·· .. 1111
. 1111· .. · .... 1111
1111 .. · .. ··1111
1111111········ .. · 1111111
1111111··· .... · .. 1111111
IJl
RDTB-
TACH
TAPE
VELOCITY
~
--+l
I+-- 70 msec START TIME
·1111111· .. ·· .... ·1111111
Sips
-Sips
/
"'
70mSeCSTOPTIME~
-.
~\:
7
/
FIGURE 3-8.17. TIMING FOR A TYPICAL WRITE/READ-REVERSE-FORWARD SEQUENCE
"-
FWD-
REV~
"'l
O.7-SECOND
STOP DELAY
~
r
VlJ////IJlJi1
FAST-
FIGURE .J...8.18. TIMING FOR A TYPICAL FAST-FORWARD/FAST-REVERSE SEQUENCE
can receive without error, signals with mark and space
distortion of up to 45 percent. The minimum stop bit time
for error free reception at any speed is 0.6 nominal bit
time. Four optional line interfaces are available:
a.
TTY current loop - neutral
b.
TTY current loop - polar
c.
Modem - originate mode
d.
Modem - answer mode.
flow) conditions should be less than or equal to
5 volts. The MARK/SPACE nominal threshold
decision current at 20mA operation (R34
deleted) should be lOrnA (±26%) and at 60mA
operation (R 34 installed), should be 30mA
(±20%).
The receiver utilizes a differential transistor pair
to sense the lOrnA or 30mA current level.
Upon sensing the decision level the transistor
pair switches the current load from one to the
other. When the second transistor of the pair
starts sinking current through its coUector, a
voltage sufficient to switch on the optic coupler
(Q17) is produced across R31. When the optic
coupler transistor turns on, Q11 turns on and
switches the appropriate TTL gates to give a
TTL-logic level output (logic ONE)
corresponding to a mark on the input receiver.
Likewise, when the current is below the
decision level on the receiver input line, the
differential pair switches back to normal, the
optic coupler turns off, and the logic level goes
back to that (logic ZERO) for a spacirig
condition on the input receiver line (TTYL1;f~~"
3-9.1.1 Teletype Current Loop - Neutral. The Teletype
Current Loop PC card (card slot A8) is divided into two
functional sections, receiver and transmitter, described
below. A schematic (959192) of this PC card is contained
in Appendix C.
a.
Receiver: The teletype (TTY) neutral receiver
consists of the necessary circuitry to sense
current from an outside source and convert the
current levels to appropriate TTL-logic levels.
The voltage drop across the receiver inputs
(TTYL1 and TTYL2) under working (current
.~
3-76
and TTYL2). Diode CR10 is provided to
protect the receiver circuit from line transients.
b.
(
from an outside source and convert the current
levels to appropriate TTL-logic levels. The
voltage drop across the receiver inputs (TTYL1
and TTYL2) under 20mA or 60mA operation
should be less than or equal to 5 volts. The
marking-spacing nominal threshold decision
current is 0 (±5) rnA.
Transmitter: The TTY neutral transmitter
consists of the necessary circuitry to sense a
TTL-logic level and then, as appropriate, open
or close the circuit presented to the transmitter
output lines (TTYL3 and TTYL4). When
closing the circuit presented to the transmitter
output lines (marking), the voltage drop across
the lines should be less than 5 volts under
nominal current conditions (20mA or 60mA).
The circuit utilizes a diode bridge so that the
output lines may be connected with either side
positive. Under normal circuit conditions the
input data (TTYDATOT) is a logic ONE. This
input condition causes optical coupler
transistors Q13 to be on and Q14 to be off.
Since Q14 is off, the amplifier action of Q2,
Q4, and Q3 provides sufficient drive to turn on
output transistor Q5 which acts as a switch for
closing (shorting) the equivalent sending
contacts to the outside lines (TTYL3 and
TTYL4). Even if power to the terminal is off,
the equivalent contacts should remain closed
(marking). This is accomplished by diode CR1
and resistors R6 and R7. These three
components, using the power provided by the
outside line, keep Q1 turned on. Since Q14 is
still off when power to the terminal is off, the
same conditions apply as when a logic ONE is
present at the transmitter input, pin 30
(TTYDATOT), and Q5 remains on, producing a
marking condition at the output lines (TTYL3
and TTYL4). To send a spacing condition Q5
must be turned off. This is accomplished by
putting a logic ZERO at the transmitter input
(pin 30). A logic ZERO input causes Q13 to
turn off and Q14 to turn on. With A14 on, the
current provided by Q1 is diverted around the
amplifier transistors Q2, Q4, and Q3, and drive
to Q5 is insufficient to turn it on. Since Q5 is
off the equivalent sending contacts to the
outside line (TTYL3 and TTYL4) are open, and
a spacing condition exists. CR3 and CR4 are
used to protect the transmitter circuit from line
transients.
The receiver circuit utilizes a diode CR10 for
protection and an optical coupler to sense the
current direction and convert it to TTL-logic.
levels. When positive current flows from
TTYL1 to TTYL2, optical coupler transistor
Q17 turns on. When Q17 is on, Qll is on and a
logic ONE is output from the receiver, pin 29
(TTYPATIN). If negative current flows from
TTYL1 to TTYL2, optical coupler transistor
Q17 turns off, turning off Qll, causing a logic
ZERO at the receiver output, pin 29.
b.
3-9.1.2 Teletype Current Loop - Polar. A schematic
(959191) of the TTY polar current loop is contained in
Appendix C.
a.
Receiver: The TTY polar receiver consists of
the necessary circuitry to sense the current
3-77
Transmitter: The TTY polar transmitter
consists of the necessary circuitry to sense a
TTL-logic level and then, as appropriate, open
one set of equivalent contacts and close one set
of equivalent contacts to the outside
transmitter lines (TTYL3 and TTYL2 or
TTYL4 and TTYL2). When closing the circuit
presented to the transmitter output lines
(marking), the voltage drop across the lines
should not exceed 5 volts under nominal
current conditions (20mA or 60mA). Operation
consists of two identical circuits which
complement each other so that equivalent
contacts between transmitter output lines
TTYL3 and TTYL2 and TTYL4 and TTYL2
are always in opposite states; i.e., when one set
is open, the other set is closed and vice versa.
Each transmitter output utilizes a diode bridge
arrangement, so that polarity of outside sources
is immaterial. When the input data (pin 30) is a
logic ONE, optical coupler transistors Q13 and
Q16 are on, and optic~l coupler transistors Q14
and Q15 are off. Since Q13 is on and Q14 is
off, current supplied by Q1 is amplified by Q2,
Q4, and Q3; therefore, sufficient drive is
available to turn on Q5 and close the equivalent
contacts between TTYL3 and TTYL2.
Conversely, in the other driver circuit Q15 is
off and Q16 is on; therefore, no current is
supplied to transistor amplifier Q7, Q8, and Q9,
keeping Q10 off and the equivalent contacts
between TTYL4 and TTYL2 open. If power to
the terminal is off, the same situation exists.
b.
Since Q15 is still off, no current is supplied to
the transistor amplifier Q7, QS, and Q9; thus,
Q10 is still off and the equivalent contact
between TTYL4 and TTYL2 is still open.
Conversely, due to diode CR1 and resistors R6
and R7,the outside power supplied by the line
maintains Q1 on; and since Q14 is off, the
transistor amplifier Q2, Q4, and Q3 apply
sufficient drive to turn on Q5 and keep closed
the equivalent contacts between TTYL3 and
TTYL2. This maintains a "working" condition
on the line, even when power to the terminal is
off. When the input data to the transmitter (pin
30) changes to a logic ZERO, the optical
coupler transistors change (Q14 and Q15 on;
Q13 and Q16 off); the transistor amplifier for
TTYL3' (Q2, Q4, Q3) turns off; the transistor
amplifier for TTYL4 (Q7, QS, Q9) turns on;
and transistor outputs Q5 and Q10 switch the
equivalent contacts to the outside line, putting
TTYL3 to TTYL2 open and TTYL4 to TTYL2
closed. Diodes CR3, CR4, CR6, and CR7 are
used to protect the transmitter circuits from
line transients.
Under normal circuit conditions the input data
(TTYDATOT) is a logic ONE. This input
condition causes optical coupler transistors Q13
to be on and Q14 to be off. With Q14 off,
sufficient drive is provided by the current flow
through Q13 to turn on Q4, which acts as a
switch to close (short) the equivalent sending
contacts to the outside lines (TTYL3 and
TTYL4).
To send a spacing condition Q4 must be turned
off. This is accomplished by putting a logic
ZERO at the transmitter input (pin 30). A logic
ZERO input causes Q13 to turn off and Q14 to
turn on. With Q14 on, drive is insufficient to
turn Q4 on. Since Q4 is off, the equivalent
sending contacts to the outside line (TTYL3
and TTYL4) are open and a spacing condition
exists.
3-9.1.3 Teletype Current Loop - Computer. The Teletype
Current Loop PC card (slot AS) is divided into two
functional sections, receiver and transmitter. A schematic
(966657) of this PC card is contained in Appendix C.
a.
Transmitter: The TTY computer transmitter
consists of the necessary circuitry to sense a
TTL-logic level and then, as appropriate, open
or close the circuit presented to the transmitter
output lines (TTYL3 and TTYL4). When
closing the circuit presented to the transmitter
output lines (marking), the voltage drop across
the lines should be less than 1.2 volts under
nominal current conditions (13 mA).
3-9.1.4. TL. Modem - Originate Mode. The TL Modem is an
originate-mode PC card modem, designed to communicate
with the comparable answer-mode (TH) modem. The
transmitter section of the TL Modem converts a MARK
level (EIADATOT low) from the serial transmitter into a
MARK (1270 Hz) frequency on the transmission line and
converts a SPACE level (EIADATOT high) into a SPACE
(1070 Hz) frequency on the transmission line. The TL
modem receiver section converts a received MARK (2225
Hz) frequency on the transmission line into a MARK level
(EIADATIN low) for the serial receiver and converts a
received SPACE (2025 Hz) frequency on the transmission
line into a SPACE level. (EIADATIN high) for the serial
receiver. Modulation and demodulation processes may be
carried out for data rates up to 300 baud. A block diagram
of the TL modem is shown in Figure 3-9.1.
Receiver: The TTY computer receiver consists
of the necessary circuitry to sense current from
an outside source (typically a computer) and
convert the current levels to appropriate
TTL-logic levels. The voltage drop across the
receiver input terminals (TTYL1 and TTYL2)
under working (current flow) conditions should
be 2.7 volts or less. The MARK/SPACE
nominal threshold decision current for 13 rnA
operation should be 6.5 rnA ±20 percent.
When current is flowing on the line, a voltage
sufficient to switch on the optical coupler
(Q17) is produced across R31. When the optical
coupler transistor turns on, Q11 turns on and
switches the appropriate TTL gates to produce
a TTL-logic level output (logic ONE)
corresponding to a MARK on the input
receiver. Likewise, when the current is below
the decision level, the optical coupler turns off
and the logic level goes to that (logic ZERO)
for a SPACE condition on the receiver line
(TTLl and TTL2). Diode CRlO is provided to
protect the receiver circuit from line transients.
a.
3-78
Reference Regulator Circuit: The reference
regulator circuit provides high frequency
filtering for the +12Vdc and -12Vdc terminal
power supply bus connections to the TL
Modem PC card. The circuit's other function is
to develop stable, low impedance, reference
voltage sources for the other circuits on the PC
,~
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FIGURE 3-9.1. ORIGINATE-MODE (TL) MODEM FUNCTIONAL BLOCK DIAGRAM
TRANSMISSION
LINE
card. The circuit includes two complementary
emitter followers (Q6, Q7), whose output
voltages track the voltage developed across the
matched pair of zener diodes CR4/CR5. The
anode of CRS also provides -5.6 volts for use in
the receiver discriminator amplifier circuit as a
bias reference to track the +5V and -5V
reference voltages. Data-set-ready and
clear-to-send are held high through R38 and
R29 whenever power is applied to the terminal.
b.
In order to change the frequency of the
oscillator waveform, the magnitude of the input
current supplied to the integrator is changed by
switching the shunt leg of the attenuator (RB,
R9) to ground. When the EIADATOT line is
high. Q4 is turned off, and Q5 is held pinched
off by -12 Vdc through R31. This action opens
the RB/R9 leg of the attenuator, allowing all
the current available at the cathode of CR2 to
flow to or from the integrator input summing
junction (AR3-2). The maximum amount of
the current, and hence the maximum slope of
the integrator output ramp, is determined by
adjusting R7. Since the higher the slope, the
shorter the time per oscillator cycle; the higher
transmitter (MARK) frequency (1270 Hz) is set
by adjusting R7 with the EIADATOT line held
high. The lower (SPACE) transmitter frequency
(1070 Hz) is produced when Q5 is no longer
pinched off by the action of Q4. Since the
on-resistance of Q5 is only about 20 ohms, the
shunt leg (RB, R9) of the attenuator is
essentially switched into the circuit, reducing
the current flowing through RIO to or from the
integrator summing junction input (AR3-2).
The magnitude of the current flowing in the
shunt leg of the attenuator is adjusted by means
of the pot R9 while the transmitted-data line is
held low. It is important to note that the
adjustments for MARK and SPACE frequencies
are interactive, inasmuch as R7 controls the
integrator input current whether the shunt leg
of the attenuator is switched in or out of the
circuit. Hence, the MARK frequency (1270 Hz)
must be set by R7 before setting the SPACE
frequency (1070 Hz) with R9.
Transmitter Triangular Wave Oscillator: The
transmitter triangular wave oscillator is the
source of 1070 Hz (SPACE) and 1270 Hz
(MARK) transmitted frequencies. The oscillator
frequency is controlled by the EIADATOT
signal from the transmit/receive PC card. The
output of ARI is fed back to the noninverting
input of ARI through R3, and the output of
ARI is driven into positive or negative
saturation. For purpo~es of explanation, assume
that ARI is initially driven into negative
saturation .. CRI is back-biased and CR2 is
forward-biased, clamping the voltage at the
cathode of C~2 to -5.6 vdc. The constant
negative voltage at the input to the voltage
divider network (consisting of R6 through R9)
causes the output of the inverting integrator
circuit (AR3, RIO, CB) to ramp upward linearly
with time. The rate at which the ramp rises is
determined by the current flowing into the
summing node (inverting input) of AR3. The
output voltage of AR3 continues to rise to
about +3.73 vdc, at which time the voltage at
the noninverting input of ARI becomes slightly
positive because of the R2/R3 voltage divider
between the output of AR3 and the cathode of
CR2. The positive voltage at the noninverting
input of ARI causes ARI to go into positive
saturation, back-biasing CR2 and
forward-biasing CR 1 to clamp the voltage at the
anode of CRI to +5.6 vdc. The constant
positive voltage at the input to the voltage
divider (R6 through R9) causes the output of
AR3 to ramp downward from +3.73 vdc
toward -3.73 Vdc. When the voltage at the
output of AR3 reaches -3.73 Vdc, the
noninverting input of ARI is forced negative,
and ARI rapidly reverses states, going into
negative saturation again. This action completes
a single cycle of the oscillator.
3-80
c.
Transmitter Low-Pass Filter: The triangular
wave output from the transmitter oscillator
circuit is altered to produce a low distortion
sine wave at the oscillator fundamental
frequency by attenuating all harmonics of the
fundamental with the transmitter's low-pass
filter (Rll-R13, C9-CI2, and AR4).
d.
Transmitter Output Driver: The transmitter
output driver circuit consists of variable
attenuator RIB from the output of the
transmitter low-pass, followed by noninverting
voltage follower AR6. By adjusting the wiper
position on RIB, the output level transmitted
(~
may be adjusted over the range from +5 dBm to
less than -40 dBm.
bridge provides 30 to 35 dB attenuation
between the transmitter and receiver.
e.
Communication Line Transient Suppressor
Circuit: The zener diodes CR7 and CR8 are
6.8-volt units rated at 5 watts. Their function is
to limit the difference-mode signal amplitude at
the primary (transmission line side) of
transformer T1 to an absolute maximum of
about 7.S volts. Chokes L3 and L4, in
conjunction with high voltage capacitors C18
and C19 and associated circuit resistances, form
low-pass fllter sections which limit the coupling
of high frequency common mode signals
(spikes, etc.) from the primary to the secondary
ofTl.
f.
Hybrid Bridge Circuit: The hybrid bridge
circuit performs three important functions.
First, it provides the proper driving and
terminating impedance to match the modem to
the transmission line. Second, it provides
isolation between the transmitter and receiver
of the modem to prevent a strong transmitted
signal from swamping out a small received
signal. Third, tlte bridge components are chosen
to limit the bandwidth of the modem receiver.
With the transmitter off AR6-6 will be at
ground, and the input impedance to the modem
appears as a series combination of R17, R41,
and the resistance of the secondary winding of
Tl (typically slightly over 600 ohms for the
total). This combination is set to 600 ohms so
as to match the transmission line impedance.
The total input impedance is tapped by ARS-3
via RlS between R41 and R17; thus, about S/6
of the input signal is present at the noninverting
input to AR5. Since R14 is at signal ground
with respect to receiving signals from the
transmission line, the overall gain is
approximately 2.0 from the communication
line input to the output of ARS (input to
receiver).
The receiver input bandwidth is limited by the
simple RC low-pass fllter formed by R15 and
C16. This fllter has a cutoff (3 dB) frequency
of about 4.4 kHz and a rolloff rate of -6 dB per
octave.
The bridge's operation is dependent on the
balancing of the impedance in its two arms:
R14/R39 and RI7/R41/Tl. For balancing
considerations R1S may be neglected, since the
very large input impedance of operational
amplifier AR5 does not load it. Consider the
case when the modem is transmitting into a
600-ohm transmission line termination on
which no other signal is impressed. The resistors
R14, R39, R17, and R41 are chosen so that the
ratio of values of IU4 to R39 equals the ratio
of values of R17 to the series combination of
R41, the line impedance (600 ohms, refle.cted
through 1:1 transformer T1), and the
c;quivalent winding resistance of Tl. Since R39
provides negative feedback around AR5, the
difference voltage between the inverting and
noninverting inputs to ARS is driven to zero.
Since the difference voltage from ARS-2 to.
ARS-3 is zero, and the bridge resistances are
proportional, the voltage across R14 equals the
voltage across R17. This means that the voltage
across R39 must equal the voltage from ARS-3
to ground; i.e., the output of the bridge
(ARS-6) is identically zero. Therefore, the
3-81
g.
1070-Hz Notch Filter Circuit: AR7 and its
associated twin-tee network provides a very
narrow, band-elimination fllter centered at the
transmitter SPACE frequency of 1070 Hz. The
function of the fllter is to severely attenuate
any 1070-Hz output signal from the transmitter
which "leaks" through the hybrid bridge circuit
to the receiver input.
h.
1270-Hz Notch Filter Circuit: AR8 and its
attendant twin-tee network provide a very
narrow, band-elimination fllter centered at the
transmitter MARK frequency of 1270 Hz. The
function of the fllter is to severely attenuate
any 1270-Hz output signal from the transmitter
which "leaks" through the hybrid bridge to the
receiver input.
i.
Limiter Circuit: The limiter circuit has two
functions. The first function is to produce a
square wave output which switches as closely as
possible to the zero crossing in the input
waveform. The output wave switches between
+5.4 and +0.2S Vdc. The high output voltage is
set by resistor divider RS4/R61 to +12Vdc. The
low output voltage is set by the saturation
voltage of the output stage of AR9. The second
function of the limiter circuit is to determine
the sensitivity of the receiver. The sensitivity of
the limiter may be varied by feeding back a
small portion of the output waveform to
establish the threshold voltage through which
the limiter input must pass in order to cause an
output transition. The greater the amplitude of
this positive feedback voltage, the larger the
input signal must be to cause a transition at
AR9-7.
comparator to switch states for modem input
signals of 0.3 mV peak (-64 dBm).
The two sensitivity settings of the limiter are
controlled by the carrier detect slicer circuit. If
no data has been received for some time, carrier
detect is low, pinching Q8 off and setting the
sensitivity to -54 dBm. When carrier detect is
high, Q8 is turned on, increasing the sensitivity
to -64 dBm. The higher sensitivity is provided
to allow the accurate reproduction of input
signal zero crossings by the limiter when the
input level is low.
C30, R51, R52, and C31 form a rudimentary
bandpass filter with nominal (-3 dB) cutoff
frequencies of 1040 Hz and 88.4 kHz. This
filter further restricts the bandwidth to which
the receiver is sensitive. Since C30 couples the
limiter circuit to the preceding receiver stage,
the input signal applied to the inverting input
of the comparator (AR9-3) has no dc
component. The band-limited input signal is
therefore an ac signal twice the amplitude of
the received signal on the transmission line,
since the hybrid bridge provides a gain of two.
The (positive) feedback signal supplied to the
noninverting input AR9-2 must also be an ac
signal with no dc component, but the voltage at
AR9-7 never goes negative.
j.
The output of the limiter circuit switches
between approximately +0.25 vdc and +5.4
Vdc; this waveform is applied to R62 and C32.
When the limiter output switches to +5.4 Vdc,
a short positive-sloped spike is coupled through
C32 to the cathode of CR10 where it is blocked
from passing to the base of Q10. The high-going
limiter output also supplies base drive through
R62 to the base of Q9, saturating Q9 and
coupling a negative-sloped spike through C33
and CR9 to the base of Q10. When a low-going
spike is applied to the base of Q10, it causes a
high-going spike at the collector of Q10.
Similarly, when the limiter output goes low, a
negative-sloped spike is applied to the base of
Q10 through C32 and CR10, causing a
high-going spike at the collector of Q10. If the
output of the limiter is a 50 percent duty-cycle
waveform, the train of pulses at the frequency
doubler output (Q10 collector) will have
exactly twice the frequency of the frequency
doubler output waveform. Q10 further acts as a
buffer amplifier, providing a low output
impedance source of trigger pulses to the
oneshot while isolating the differentiating
capacitors C32 and C33 from the positive
feedback voltage around the amplifier ARlO in
the oneshot.
A pull-down network composed of R55 and
R56 provide the driving potential to pull the.
feedback signal below ground. Pot R56
provides adjustment to compensate for
variation in input offset voltage as well as
tolerance variations in R54, R61, and +12 Vdc.
Pot R53 provides an additional capability to
compensate for input offset voltage in AR9.
When a valid input signal is presented to the
modem receiver after the carrier detect has
been in the off (low) state, PET Q8 is held off
and a ±2 m V signal is presented to the
noninverting input of AR9 through the
attenuator composed of R57 + R59 and R58.
If, for example, the input voltage at AR9-3 is
sufficiently negative to cause the output stage
of AR9 to cut off, the voltage at AR9-7 rises to
+5.4 Vdc, applying about +2 mVdc to AR9-2.
Before the output stage of AR9 can saturate
again, the signal at AR9-3 must go higher than
the +2 mVdc set at AR9-2. This means that the
limiter cannot respond to modem input signals
smaller than 1 mV peak (approximately -54
dBm) if Q8 is pinched off. If Q8 is turned on,
the positive feedback voltage at AR9-2 is
limited to ±0.6 mVdc swings, thus allowing the
k.
3-82
Frequency Doubler Circuit: The squarewave
output from the limiter is applied to the
frequency doubler where the wave train is
differentiated and essentially full-wave-rectified
to obtain a train of trigger pulses with a
constant amplitude and a repetition rate of
twice the incoming signal (and limiter output).
Receiver Oneshot Circuit: The output pulses
from the frequency doubler circuit trigger the
oneshot to produce a rectangular pulse train.
The change in average dc value of this
(
rectangular pulse train is directly proportional
to the change in repetition rate of the trigger
pulses and, hence, proportional also to the
change in input signal frequency.
In its stable (inactive) state oneshot amplifier
AR10-6 is in negative saturation, and the
oneshot output (cathode of CR12) is clamped
to -5.6 Vdc through CR12. The negative output
voltage is fed back to the noninverting input of
ARlO through the voltage divider comprised of
R69 and R70, holding the noninverting input
to -2.8 V dc. The negative saturation voltage at
AR10-6 is also applied to a voltage divider
formed by R75 and R74, saturating the
collector of Qll at approximately 0 vdc. This
action holds the ungrounded side of the timing
capacitor C34 (inverting input of ARlO) very
close to ground through R82. Since the
noninverting input voltage (-5.4 Vdc) is less
than the inverting input voltage (approximately
o Vdc) , the amplifier is latched in negative
saturation, holding the oneshot output in its
stable state.
When a high-going pulse is applied to the
noninverting input of ARlO from the collector
of Q10 (low impedance source), the
noninverting input of ARlO is made more'
positive than the inverting input of ARlO (0
Vdc). This condition causes ARlO to switch
from negative saturation to positive saturation,
and the metastable (active) state of the oneshot
is initiated. The oneshot output is bounded to
+5.6 vdc by the clamping action of CRll, and
the output voltage is divided by R 70 and R69
and applied to the noninverting input of ARlO.
The positive voltage at AR10-6 causes Qll to
cut off and C34 begins to charge from 0 vdc
toward +5.6 Vdc through the combination of
R72, R73, and R76, with the setting of R76
establishing the rate of charge. Since the voltage
at the inverting input of ARlO is initially less
than the +2.8 vdc at the noninverting input,
the output of ARlO is latched in positive
saturation. Finally, when C34 has charged up
higher than +2.8 Vdc, the voltage at the
inverting input of ARlO exceeds the voltage at
the noninverting input of ARlO, and the
output of ARlO switches to negative
saturation. This causes Qll to saturate, quickly
discharging C34 through R 71, and the oneshot
resumes its stable state.
3-83
The adjustment range of R76 allows the
oneshot (metastable) period to he set for a
(positive) duty cycle of 25 percent when the
trigger pulse frequency equals 4250 pulses per
second. This frequency is produced when an
input signal of 2125 Hz is applied successively
to the modem receiver limiter and frequency
doubler stages.
1.
Receiver Discriminator Low-Pass Filter Circuit:
The rectangular output waveform from the
oneshot circuit is fed into the discriminator
low-pass ftIter circuit. Since the cutoff
frequency of this ftIter (150 HE) is ~o much
lower than the repetition frequency of the
oneshot output pulses, the ftIter acts essentially
as an analog integrator. The ftIter output, then,
is a dc voltage equal to the average value of the
oneshot pulse train voltage. A change in input
frequency thus causes a proportional change in
the fUter output voltage.
m.
Discrimination Amplifier Circuit: The
discriminator amplifier modifies (biases and
amplifies) the output signal from the
discriminator low-pass ftIter to make it easier to
compare in the received-data slicer and the
carrier-detect slicer circuits.
The nominal swing in the discriminator
low-pass filter output, which corresponds to a
SP ACE -frequency-to-MARK-frequency
transition at the receiver input, is from -2.93
vdc to -2.67 vdc. It is convenient to translate
this voltage swing upward so that the decision
as to whether the output voltage of the
discriminator filter is high or low
(corresponding to MARK or SPACE received
frequencies, respectively) may be made about
ground potential. Such a translation is provided
by the discriminator amplifier. When the
receiver input frequency is 2125 Hz, the
oneshot pulse width is adjusted so that the
discriminato; amplifier output voltage is zero.
In addition to providing convenient positive
translation of the discriminator output voltage,
the discriminator amplifier also applies a gain of
nearly +25 to the output swing of the
discriminator low-pass ftIter. This additional
gain allows the output of the amplifier to swing
from -3.25 vdc for a SPACE (2025 Hz) input
to +3.25 Vdc for a MARK (2225 Hz) input
with 0 Vdc corresponding to the mid-band
frequency of 2125 Hz.
n.
The biasing of the matched pair of zener diodes
CR14/CR15 from the +12 vdc and -12 Vdc
supply buses through R88 and R90 establishes
the voltage drops across the zeners at very
nearly 5 Vdc. Thus, as the output voltage of
AR15-6 is applied to the cathode of CR15
(anode of CR14), the voltage at the cathode of
CR14 is set 5 volts above the discriminator
amplifier output voltage. Similarly, the voltage
at the anode of CR15 is set 5 volts below the
discriminator amplifier output voltage.
Received-Data Slicer Circuit: The received-data
slicer circuit monitors the output voltage of the
discriminator amplifier, providing a MARK
level to the XMT/RCV logic for any input
signal whose frequency is 2125 Hz or higher. It
produces a SPACE level to the XMT/RCV logic
for any input signal whose frequency is less
than 2125 Hz.
So long as the voltage at AR15-6 lies in the
range -5.6 vdc to +5.6 Vdc, both diodes CR13
and CR18 remain back-biased and the small
positive voltage set by the divider R89/R95
holds AR13 in positive saturation (since with
CR13 and CR18 back-biased, AR13-3 is slightly
positive and R94 is grounded through R94).
When the discriminator amplifier output
voltage (AR15-6) is higher than 0 Vdc
(corresponding to a MARK input frequency),
the inverting input voltage to comparator AR16
is made more positive than noninverting input
voltage which is fixed at ground potential. This
causes the output of AR16 to saturate, pulling
the EIADATIN line' to -12 volts through R10l.
When the discriminator amplifier output
voltage is less than 0 Vdc (corresponding to a
SPACE input frequency condition), the
inverting input voltage to AR16 is made more
negative than 'the noninverting input voltage (0
Vdc). This causes the output stage of AR16 to
saturate positive, causing the EIADATIN line to
reach +12 volts through R10l.
If the voltage at AR15-6 rises about +5.6 Vdc,
CR13 remains back-biased but CR18 is
forward-biased, increasing the voltage at
AR13-2 above that at ARI3-3. This condition
causes AR13-6 to switch to its negative
saturation voltage, indicating
carrier-out-of-band.
If the voltage at AR15-6 falls below -5.6 Vdc,
CR18 remains back-biased but CR13 is
forward-biased, reducing the voltage at AR13-3
below that at AR13-2. This condition causes
AR13-6 to switch to its negative saturation
voltage, indicating carrier-out-of-band.
The positive feedback around AR16, provided
through R93, decreases the change of
comparator output parasitic oscillations as the
noninverting input slews through the region
near 0 Vdc. It also provides a margin of
immunity (approximately 2 mY) to small
ripples present at the discriminator amplifier
output.
p.
The presence of R91 and C43 provides some
additional filtering of the discriminator
amplifier output to attenuate any high
frequency transients present.
o.
Carrier Detect Slicer Circuit: The carrier-detect
slicer circuit monitors the output voltage of the
discriminator amplifier, providing an in-band
signal to the carrier-detect delay circuit for any
input signal whose frequency lies between 1950
Hz and 2300 Hz. It produces an out-of-band
signal to the carrier-detect delay circuit for any
input signal frequency below 1950 Hz or above
2300 Hz.
3-84
Carrier Detect Delay Circuit: The carrier-detect
delay circuit provides an in-band (EIADCD
high) level to the transmit/receive logic in
accord with the in-band signal from the
carrier-detect slicer circuit. The rising transition
in the carrier-detect signal to the
transmit/receive logic is delayed until a nominal
150 msec after the carrier-detect slicer in-band
indication is given. The carrier-detect delay
circuit also provides an out-of-band (EIADCD
low) level to the transmit/receive logic,
corresponding to the out-of-band signal from
the carrier-detect slicer circuit. The falling
transition in the EIADCD signal is delayed until
a nominal 100 msec after the carrier-detect
slicer out-of-band indication is given.
(-
When the carrier detect slicer output (AR13-6)
is positively saturated, the base-emitter junction
of Q12 is forward-biased, and its collector
saturates at about +0.5 vdc. In this state CR16
is back-biased approximately 11 volts with +0.5
vdc at its anode. This small positive voltage
allows the N-channel FET Q8 to turn on,
causing the limiter sensitivity to increase. The
forward-biased base-emitter diode drop from
Q12 appears across C44 and as a reverse bias
across CR 17. The base-emitter drop also holds
AR14-3 at +0.6 Vdc, causing the output stage
of AR14 to saturate positive and hold the
carrier detect line (EIADCD) to +12 volts.
to +12 volts. C44 continues to charge up to
+0.6 volts, at which time Q12 is saturated and
the clamping action of the forward base-emitter
diode halts the charging process. As Q12
saturates it quickly pulls the gate voltage at Q8
from approximately -11 to +0.5 volts, turning
Q12 on and increasing the sensitivity of the
receiver limiter.
3-9.1.5 Modem-Answer Mode (TH). The TH Modem is an
answer-mode PC card modem, designed to communicate
with the comparable originate-mode TL Modem. The
transmitter section of the TH Modem converts a MARK
level (EIADATOT low) from the serial transmitter into a
MARK (2225 Hz) frequency on the transmission line and
converts a SPACE level (EIADATOT high) into a SPACE
(2025 Hz) frequency on the transmission line. The TH
Modem receiver section converts a received MARK (1270
Hz) frequency on the transmission line into a MARK level
(EIADATIN low) for the serial receiver and converts a
received SPACE (1070 Hz) frequency on the transmission
line into a SPACE level (EIADATIN high) for the serial
receiver. Modulation and demodulation may be carried out
for data rates up to 300 baud. A block diagram of the TH
Modem is shown in Figure 3-9.2.
If a loss of in-band carrier causes the voltage at
AR13-6 to switch to negative saturation, Q12 is
immediately turned off and CR16 is
forward-biased through R96 to clamp the gate
of Q8 to approximately -11 vdc. These
conditions quickly pinch off Q8, switching the
limiter sensitivity to its lower level. The
carrier-detect "dropout" delay cycle begins as
Q12 is cut off and the voltage between R97 and
C44 slowly decreases from +0.6 volts as C44 is
discharged toward the saturation voltage of
AR13 through R97. The output stage of AR14
remains cut off and carrier detect remains at
+12 volts until the voltage between R99 and
C44 goes slightly negative, approximately 50
msec after AR13 goes into negative saturation.
When the voltage at AR14-2 goes negative, the
output stage of AR14 is saturated and the
carrier-detect line is switched to -12 volts.
a.
After' the carrier-detect line has been low for
some time, the voltage between C44 and R99 is
clamped to -2 volts by the forward-biased
multipellet diode CR17 (CR17 serves to limit
the differential voltage between AR14-2 and
AR14-3, while establishing a 2-volt reference
across C44). If the output of the carrier-detect
slicer (AR13-6) switches from negative to
positive saturation, indicating the presence of
in-band data on the transmission line, C44
begins to charge from -2 volts toward the
positive saturation output voltage of AR13
through R97. When the voltage between R99
and C44 goes slightly positive (150 msec after
switching of AR13), the output stage of AR14
is cut off and the carrier-detect line is pulled up
3-85
Reference Regulator Circuit: The reference
regulator circuit provides high frequency
filtering for the +12 Vdc and -12 vdc terminal
power supply bus connections to the TH
Modem PC card. The circuit's other function is
to develop stable, low impedance, reference
voltage sources for the other circuits on the PC
card. The circuit includes two complementary
emitter followers (Q6, Q7) whose output
voltages track the voltage developed across the
matched pair of zener diodes CR4/CR5. The
anode of CR5 also provides -5.6 volts for use in
the receiver discriminator amplifier circuit as a
bias reference to track the +5V and -5V
reference voltages.
Data-set-ready and clear-to-send are held high
through R38 and R29 whenever power is
applied to the terminal.
b.
Transmitter triangular Wave Oscillator: The
transmitter triangular wave oscillator is the
source of 1070 Hz (SPACE) and 1270 Hz
(MARK) transmitted frequencies. The oscillator
frequency is controlled by the EIADATOT
signal from the transmit/receive. The output of
the output of AR3 to ramp downward from
+3.73 Vdc toward -3.73 Vdc. When the voltage
at the output of AR3 reaches -3.73 Vdc, the
noninverting input of AR1 is forced negative,
and AR1 rapidly reverses states, going into
negative saturation again. This action completes
a single cycle of the oscillator.
AR1 is fed back to the noninverting input of
AR1 through R3, and the output of AR1 is
driven into positive or negative saturation. For
purposes of explanation, assume that AR1 is
initially driven into negative saturation. CR1 is
back-biased and CR2 is forward-biased,
clamping the voltage at the cathode of CR2 to
-5.6 vdc. The constant negative voltage at the
input to the voltage divider network (consisting
of R6 through R9) causes the output of the
inverting integrator circuit (AR3, R10, C8) to
ramp upward linearly with time. The rate at
which the ramp rises is determined by the
current flowing into the summing node
(inverting input) of AR3. The output voltage of
AR3 continues to rise to about +3.73 vdc, at
which time the voltage at the noninverting
input of AR1 becomes slightly positive because
of the R2/R3 voltage divider between the
output of AR3 and the cathode of CR2. The
positive voltage at the noninverting input. of
AR1 causes AR1 to go into positive saturation,
back-biasing CR2 and forward-biasing CR1 to
clamp the voltage at the anode of CR1 to +5.6
Vdc. The constant positive voltage at the input
to the voltage divider (R6 through R9) causes
In order to change the frequency of the
oscillator waveform, the magnitude of the input
current supplied to the integrator is changed by
switching the shunt leg of the attenuator (R8,
R9) to ground. When the EIADATOT line is
high, Q4 is turned off, and Q5 is held pinched
off by -12 vdc through R31. This action opens
the R8/R9 leg of the attenuator, allowing -all
the current available at the cathode of CR2 to
flow to or from the integrator input summing
junction (AR3-2). The maximum amount of
the current, and hence the maximum slope of
the integrator output ramp, is determined by
adjusting R7. Since the higher the slope, the
shorter the time per oscillator cycle, the higher
transmitter (MARK) frequency (2225 Hz) is set
by adjusting R7 with the EIADATOT line held
high. The lower (SPACE) transmitter frequency
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FIGURE 3-9.2. ANSWER MODE (TH) MODEM FUNCTIONAL BLOCK DIAGRAM
TRANSMISSION
LINE
(2025 Hz) is produced when Q5 is no longer
pinched off by the action of Q4. Since the on
resistance of Q5 is only about 20 ohms, the
shunt leg (R8, R9) of the attenuator is
essentially switched into the circuit, reducing
the current flowing through RIO to or from the
integrator summing junction input (AR3-2).
The magnitude of the current flowing in the
shunt leg of the attenuator is adjusted by means
of the pot R 9 while the transmitted-data line is
held low. It is important to note that the
adjustments for MARK and SPACE frequencies
are interactive. inasmuch as R7 controls the
integrator input current whether the shunt leg
of the attenuator is switched in or out of the
circuit. Hence the MARK frequency (2225 Hz)
must be set by R7 before setting the SPACE
frequency (2025 Hz) with R9.
c.
Transmitter Low-Pass Filter: The triangle wave
output from the transmitter oscillator circuit
may be altered to produce a low distortion sine
wave at the oscillator fundamental frequency
by attenuating all harmonics of the
fundamental with the XMITTER low-pass filter
(Rll-R13, C9-C12, and AR4).
d.
Transmitter Output Driver: The transmitter
output driver circuit consists of variable
attenuator RI8 from the output of the
transmitter low-pass, followed by noninverting
voltage follower AR6. By adjusting the wiper
position on R18, the output level transmitted
may be adjusted over the range from +5 dBm to
less than -40 dBm.
e.
Communication Line Transient Suppressor
Circuit: The zener diodes CR7 and CR8 are
6.8-volt units rated at 5 watts. Their function is
to limit the difference-mode signal amplitude at
the primary (transmission line side) of
transformer TI to an absolute maximum of
about 7.5 volts. Chokes L3 and L4, in
conjunction with high voltage capacitors C18
and CI9 and associated circuit resistances, form
low-pass filter sections which limit the coupling
of high frequency common mode signals
(spikes, etc.) from the primary to the secondary
ofTl.
f.
First, it provides the proper driving and
terminating impedance to match the modem to
the transmission line. Second, it provides
isolation between the transmitter and receiver
of the modem to prevent a strong transmitted
signal from swamping a small received signal.
Third, the bridge components are chosen to
limit the bandwidth of the modem receiver.
The bridge's operation is dependent on the
balancing of the impedance in its two arms:
R14/R39 and RI7/R41/Tl. For balancing
considerations RI5 may be neglected, since the
very large input impedance of operational
amplifier AR5 does not load it. Consider the
case when the modem is transmitting into a
600-ohm transmission line termination on
which no other signal is impressed. The resistors
R14, R39, R17, and R4I are chosen so that the
ratio of values of RI4 to R39 equals the ratio
of values of RI7 to the series combination of
R4I, the line impedance (600 ohms, reflected
t h rough 1 : I transformer T I ), and the
equivalent winding resistance of TI. Since R39
provides negative feedback around AR5, the
difference voltage between the inverting and
noninverting inputs to ARS is driven to zero.
Since the difference voltage from AR5-2 to
AR5-3 is zero, and the bridge resistances are
proportional, the voltage across RI4 equals the
voltage across R17. This means that the voltage
across R39 must equal the voltage from AR5-3
to ground; i.e., the output of the bridge
(ARS-6) is identically zero. Therefore, the
bridge provides 30 to 35 dB attenuation
between the transmitter and receiver.
With the transmitter off AR6-6 will be at
ground, and the input impedance to the modem
appears as the series combination ofRl7, R41,
and the resistance of the secondary winding of
TI (typically slightly over 600 ohms for the
total). This combination is set to 600 ohms so
as to match 'the transmission line impedance.
The total input impedance is tapped by AR5-3
via R15 between R41 and R17; thus, about 5/6
of the input signal is present at the noninverting
input to AR5. Since RI4 is at signal ground
with respect to receiving signals from the
transmission line. The overall gain is
approximately 2.0 from the communication
line input to the output of AR5 (input to
receiver) .
Hybrid Bridge Circuit: The hybrid bridge
circuit performs three important functions.
3-87
The receiver input bandwidth is limited by the
simple RC low-pass filter formed by R15 and
C16. This filter has a cutoff (3 dB) frequency
of about 2.473 kHz and a rolloff rate of -6 dB
per octave.
g.
h.
of the comparator (AR9-3) has no de
component. The band-limited input signal is
therefore an ac signal twice the amplitude of
the received signal on the transmission line
since the hybrid bridge provides a gain of two.
The (positive) feedback signal supplied to the
noninverting input AR9-2 must also be an ac
signal with no de component, but the voltage at
AR9-7 never goes negative.
2025 Hz Notch Filter Circuit: AR7 and its
associated twin-tee network provide a very
narrow band-elimination filter centered at the
transmitter SPACE frequency of 2025 Hz. The
function of the filter is to severely attenuate
any 2025 Hz output signal from the transmitter
which "leaks" through the hybrid bridge circuit
to the receiver input.
A pull-down network composed of R55 and
R56 provide the driving potential to pull the
feedback signal below ground. Pot R56
provides adjustment to compensate for
variation in input offset voltage as well as
tolerance variations in R54, R61, and +12 vdc.
Pot R53 provides an additional capability to
compensate for input offset voltage in AR9.
When a valid input signal is presented to the
modem receiver after the carrier detect has
been in the off (low) state, FET Q8 is held off
and a ±2 mV signal is presented to the
noninverting input of AR9 through the
attenuator composed of R57 + R59 and R58.
If, for example, the input voltage at AR9-3 is
sufficiently negative to cause the output stage
of AR9 to cut off, the voltage at AR9-7 rises to
+5.4 Vdc, applying about +2 mVdc to AR9-2.
2225 Hz Notch Filter Circuit: AR8 and its
attendant twin-tee network provide a very
narrow band-elimination filter centered at the
transmitter MARK frequency of 2225 Hz. The
function of the filter is to severely attenuate
any 2225-Hz output· signal from the transmitter
which "leaks" through the hybrid bridge to the
receiver input.
Limiter Circuit: The limiter circuit has two
functions. The first function is to produce a
square wave output which switches as closely as
possible to the zero crossings in the input
waveform. The output wave switches between
+5.4 and +0.25 vdc. The high output voltage is
set by the resistor divider R54/R61 to +12Vdc.
The low output voltage is set by the saturation
voltage of the output stage of AR9.
Before the output stage of AR9 can saturate
again, the signal at AR9-3 must go higher than
the +2 mVdc set at AR9-2. This means that the
limiter cannot respond to modem input signals
smaller than 1 mV peak (approximately -54
dBm) if Q8 is pinched off. If Q8 is turned on,
the positive feedback voltage at AR9-2 is
limited to ±0.6 mVdc swings, thus allowing the
comparator to switch states for modem input
signals of 0.3 mV peak ( -64 dBm).
The second function of the limiter circuit is to
determine the sensitivity of the receiver. The
sensitivity of the limiter may be varied by
feeding back a small portion of the output
waveform to establish the threshold voltage
through which the limiter input must pass in
order to cause an output transition. The greater
the amplitude of this positive feedback voltage,
the larger the input signal must be to cause a
transition at AR9-7.
The two sensitivity settings of the limiter are
controlled by the carrier detect slicer circuit. If
no data has been received for some time, carrier
detect is low, pinching Q8 off and setting the
sensitivity to -54 dBm. When carrier detect is
high, Q8 is turned on, increasing the sensitivity
to -64 dBm. The higher sensitivity is provided
to allow the accurate reproduction of input
signal zero crossings by the limiter when the
input level is low.
C30, R51, and C31 form a rudimentary
bandpass filter with nominal (-3 dB) cutoff
frequencies of 570 Hz and 88.4 kHz. This filter
further restricts the bandwidth to which the
receiver is sensitive. Since C30 couples the
limiter circuit to the preceding receiver stage,
the input signal applied to the inverting input
j.
3-88
Frequency Doubler Circuit: The squarewave
output from the limiter is applied to the
frequency doubler where the wave train is
differentiated and essentially full-wave rectified
to obtain a train of trigger pulses with a
constant amplitude and a repetition rate of
twice the incoming signal (and limiter output).
(
ARIO-6 is also applied to a voltage divider
formed by R75 arid R74, saturating the
collector of Qll at approximately 0 vdc. This
action holds the ungrounded side of the timing
capacitor C34 (inverting input of ARlO) very
close to ground through R82. Since the
noninverting input voltage (-5.4 Vdc) is less
than the inverting input voltage (approximately
o Vdc), the amplifier is latched in negative
saturation, holding the oneshot output in its
stable state.
The output of the limiter circuit switches
between approximately +0.25 vdc and +5.4
Vdc: this waveform is applied to R62 and C32.
When the limiter output switches to +5.4 Vdc,
a short positive-sloped spike is coupled through
C32 to the cathode of GRIO where it is
blocked from passing to the base of QlO. The
high-going limiter output also supplies base
drive through R62 to the base of Q9, saturating
Q9 and coupling a negative-sloped spike
through C33 and CR9 to the base of QIO.When a low-going spike is applied to the base of
QlO, it causes a high-going spike at the
collector of QIO. Similarly, when the limiter
output goes low, a negative-sloped spike is
applied to the base of QlO through C32 and
CRIO, causing a high-going spike produced at
the collector: ,of QIO. If the output of the
limiter is a 50 percent duty cycle waveform, the
train of pulses at the frequency doubler output
(QlO collector) will have e~actly twice the
frequen'cy of ,the frequency doubler output
waveform. QlO furth,er acts as a buffer
amplifier. providing a low output impedance
source of trigger pulses to the oneshot while
isolating the differentiating capacitors C32 and
C33 from the positive feedback voltage around
the amplifier AR lO inthe,oneshot.
(-
k.
When a high-going pulse is applied to the
noninverting input of ARlO from the collector
of Q 10 (low impedance source), the
noninverting input of ARlO is made more
positive than the inverting input of ARlO (0
Vdc). This condition causes ARlO to switch
from negative saturation to positive saturation,
and the metastable (active) state of the oneshot
is initiated. The oneshot output is bounded to
+5.6 Vdc by the clamping action of CR11, and
the output voltage is divided by R 70 and R69
and applied to the noninverting input of ARlO.
The positive voltage at AR I 0-6 causes Q 11 to
cut off and C34 begins to charge from 0 V dc
,toward +5.6 V dc through the combination of
R72, R73, and R76, with the setting of R76
establishil1g the rate of charge. Sil1ce the voltage
at the inverting input of ARlO is initially less
thal1 the t 3.8 vdc at ,the noninverting input,
the output of ArlO is latched in positive
saturation. Finally, when C34 has charged up
higher than +2.8 Vdc, the voltage at the
inverting input of ARlO exceeds the voltage at
,the noninverting input of ARlO, and the
output of ARlO switches to negative
saturation. This causes Qll to saturate, quickly
discharging C34 through R 71, and the one-shot
,resumes its stable state.
Receiver OneshotCircuit: The output pulses
from the frequency, doubler circuit trigger the
oneshot to produce'a rectangular pulse train.
The change in average de value of this
rectangular pulse train is directly proportional
to the change in repetition rate of the trigger
pulses and. hence, proportional also to the
change in input signal freque'ncy.
The adjustment range of R76 allows the
oneshot (metastable) period to, be set for a
(positive) duty cycle of 25 percent when the
trigger pulse frequency equals 2340 pulses per
second. This frequency is produced when an
input signal of 1170 Hz is applied successively
to the modem receiver limiter and frequency
doubler stages.
In its stable (inactive) state, oneshot amplifier
ARIO-6 is in negative saturation, and the
oneshot output (cathode of CRI2) is clamped
to -5.6 Vdc through CRI2. The negative output
voltage is fed back to the noninverting input of
ARlO through the· voltagediv~der comprised of
R69 andR70, holding the noninverting input
to 2.8 Vdc. The negative saturation voltage at
L
3-89
,Receiver Discriminator Low-Pass Filter Circuit:
The rectangular output waveform from the
oneshot circuit is fed into the discriminator
low-pass filter circuit. Since the cutoff
freq uency of this filter (150 Hz) is so much
lower than the repetition frequency of the
oneshot output pulses, the filter acts essentially
as an analog integrator. The filter output, then,
is a dc voltage equal to the average value of the
oneshot pulse train voltage. A change in input
frequency thus causes a proportional change in
the filter output voltage.
m.
When the discriminator amplifier output
voltage (AR16-6) is higher than 0 vdc
(corresponding to a MARK input frequency)
the inverting input voltage to comparator AR16
is made more positive than the noninverting
input voltage, which is fixed at ground
potential. This causes the output of AR16 to
saturate, pulling the EIADATIN line to -12
volts through R101. When the discriminator
amplifier output voltage is less than 0 V dc
(corresponding to a SPACE input frequency
condition), the inverting input voltage to AR16
is made more negative than the non inverting
input voltage (0 Vdc). This causes the output
stage of ARt6 to saturate positive, causing the
EIADATIN line to reach + 12 volts through
RI01.
Discriminator Amplifier Circuit: The
discriminator amplifier modifies (biases and
amp Ii fi es) the output signal from the
discriminator low-pass filter to make it easier to
compate in the received-data slicer and the
carrier-detect slicer circuits.
The nominal swing in the discriminator
low-pass filter output, which corresponds to a
SPACE freq uency-to-MARK frequency
transition at the receiver input, is from -2.93
vdc to -2.67 vdc. It is convenient to translate
this voltage swing upward so that the decision
as to whether the output voltage of the
discriminator filter is high or low
(corresponding to MARK to SPACE received
frequencies. respectively) may be made about
ground potential. Such a translation is provided
by the discriminator amplifier. When the
receiver input frequency is 1170 Hz, the
oneshot pulse width is adjusted so that the
discriminator amplifier output voltage is zero ..
The positive feedback around ARI6, provided
through R93, decreases the chance of
comparator output parasitic oscillations as the
noninverting input slews through the region
near 0 Vde. It also provides a margin of
immunity (approximately 2 mY) to small
ripples present at the discriminator amplifier
output ..
The presence of R91 andC43 provides some
additional filtering of the discriminator
amplifier output to attenuate any high
frequency transients present.
o.
In addition to providing the convenient positive
translation of the discriminator output voltage,
the discriminator amplifier also applies a gain of
nearly +25 to the output swing of the
discriminator low-pass filter. This additional
gain allows the output of the amplifier to swing
from -3.25Vdc for a SPACE (1070 Hz) input to
+3.25 vdc for a MARK (1270 Hz) input with 0
vdc corresponding to the midband frequency
of 1170 Hz.
n.
Carrier Detect Slicer Circuit: The carrier-detect
circuit monitors the output voltage of the
discriminator amplifier, providing an in-band
signal to the carrier-detect delay circuit for any
input signal whose frequency lies between 994
Hz and 1339 Hz. It produces an out-of-band
signal to the carrier-detect delay circuit for any
input signal frequency below 994 Hz or above
1339 Hz.
The biasing of the matched pair of zener
diodes, CR14jCR 15, from the +12 vdc and -12
vdc supply buses through R88 and R90
establishes the voltage drops across the zeners
at very nearly 5 V dc. Thus. as the output
voltage of AR15-6 is applied to the cathode of
. CR15 (anode of CR14), the voltage at the
cathode of CR 14 is set 5 volts above the
discri mina tor am p lifier output voltage.
Similarly, the voltage at the anode of CR 15 is
set 5 volts below the discriminator amplifier
output voltage.
Received Data Slicer Circuit: The received-data
slicer circuit monitors the output voltage of the
discriminator amplifier, providing a MARK
level to the XMTjRCV logic for any input
signal whose frequency is 1170 Hz or higher. It
produces a SPACE· level to the XMTjRCV logic
for any input signal whose frequency is less
than 1170 Hz.
3-90
/
Sa lang as the valtage at AR15-6 lies in the
range -5.6 vdc ta +5.6 Vdc, bath diades CR13
and CR18 remain back-biased and the small
positive valtage set by the divider R89/R95
halds AR13 in pasitive'saturation (since with
CR13 and CR18 back-biased AR13-3 is slightly
positive and R94 is grounded through R94).
If the voltage at AR15-6 rises abaut +5.6 vdc,
CR13 remains back-biased, but CR18 is
forward-biased, increasing the voltage at
AR13-2 above that at AR13-3. This candition
causes AR13-6 to switch ta its negative
saturation voltage, indicating
carrier-aut-of-band.
'
If the voltage at AR15-6 falls bel~w -5.6 Vdc,
CR18 remains back-biased, but CR13 is
forward-biased, reducing the valtage at AR13-3
below that at AR 13-2. This condition causes
AR 13-6 to switch ta its negative saturation
voltage, indicating carrier-out-of-band.
p.
(
('
Carrier Detect Delay Circuit: The carrier-detect
circuit provides an in-band (EIADCD high) level
ta transmit/receive logic in accard with the
in-band signal fram the carrier-detect slicer
circuit. The rising tranSltl~n in the
carrier-detect signal to the transmit/receive
logic is delayed until a naminal ISO' msec after
the carrier-detect slicer in-bind indicatian is
given: The carrier-detect delay circuit also
provides an out-oE-band (EIADCD low) level to
the transmit/receive logic, carrespanding to the
out-of-band signal fram the carrier-detect slicer
circuit. The falling transitian in the (EIADCD)
signal is delayed until a nominal 100 msec after
the carrier-detect slicer out-oE-band indicatian
is given.
When the carrier detect slicer ~utput (AR13-6)
is positively saturated. the base-emitter junction
of Q12 is forward-biased, and its collector
saturates at about +0.5 Vdc. In this state CR16
is back-biased by approximately II volts with
+0.5 vdc at its anode. This small positive
voltage allows the N-channel FET Q8 to turn
on, causing the limiter sensitivity to increase.
The forward-biased ba.se-emitter diode drop
from Q12 appears across C44 and as a reverse
bias across CR 17. The base-emitter drop also
holds AR14-3 at +0.6 Vdc, causing the output
3-91
stage of AR14 to saturate positive and hald the
carrier detect line (EIADCD) ta +12 volts.
If a loss of in-band carrier causes the voltage at
AR13-6 to switch to negative saturatian, Q12 is
immediately turned off and CR16 is forward
biased through R96 to clamp the gate of Q8 ta
appraximately -11 vdc. These conditions
quickly pinch off Q8, switching the limiter
sensitivity to its lower level. The carrier-detect
"dropout" delay cycle begins as Q12 is cut .off
and the valtage between R97 and C44 slawly
decreases fram +0.6 Vdc as C44 is discharged
taward the saturatian voltage of AR13 through
R97. The .output stage .of AR14 remains cut off
and carrier detect remains at +12 V dc until the
valtage between R99 and C44 goes slightly
negative, approximately 50 msec after AR13
goes into negative saturation. When the voltage
at AR14-2 goes negative, the output stage of
AR14 is saturated and the carrier detect line is
switched ta -12 volts.
After the carrier detect line has been law far
some time, the valtage between C44 and R99 is
clamped ta -2 V dc' by the, forward-biased
multipellet diode CR17 (CR17 serves to limit
the differential voltage between ~AR14-2 and
, AR14 c3; ~hile establishing· a ivoltreference
across C44). If the output of the carr~er detect
slicer (AR13-6)" switches from negative' to
positive saturation, indicating the, presence of
in-band 'data on the transmission line, C44
begi,ns to, charge from ,-2 Vdc, toward the
positive saturation .output voltage .of AR13
through R97. When the voltage between R99
and C44 goes slightly pasitive (150 msec after
switching .of AR13), the .output stage of AR14
is cut .off and the carrier detect line is pulled up
ta +12 valts. C44 cantinues ta charge up ta
+0.6 Vdc, at which time Q12 is saturated and
the damping actian .of the forward base-emitter
diode halts the' charging process. As Q 12
saturates, it' quickly pulls the gate voltage at Q8
from approximately -11 vdc ta +0.5 vdc.
turning Q12 an and increa~ing the sensitivity of
the receiver limiter.
3-9.2 ANSWER-BACK MEMORY. The Answer-Back
Memary PC card is an aptianal accessory for the 733 ASR
.or KSR. This circuit autamatically transmits any
programmed sequence .of up ta twenty-one 7-bit characters
for station identification. The station identification message
is stored in a diode matrix as a series of 7 -bit ASCII-coded
characters. The matrix, shown in Figure 3-9.3, is arranged
to facilitate user programming. Each horizontal row in the
matrix (starting with CRl) represents one 7 -bit character.
The first character is the top row. and bit-l (LSB) is at the
top right (CRl). Thus. character-1 is made up of diodes
CRl (bit-I), CR22. CR43, CR64. CR8S, CR 11)6, and
CR127 (bit-7). The presence of a diode in any bit position
indicates a logic ONE in that bit position. For example, if
the first character to be programmed is an uppercase
B(1000010). diodes CR1, CR43, CR64. CR8S, and CRI06
would be cut out, and diodes CR22 and CR127 would be
left in.
(CR148 through CR16S) must be removed. For example, if
a IS-character message is desired, diodesCR148 through
CRIS9 must be removed and CR160 must be left in the
circuit.
The Answer-Back Memory (ABM) is triggered by the HERE
IS key (terminal on-line and keyboard not OFF), or by
receiving the ENQ code (card set for ASCII), or by
receiving FIG and D consecutively (card set for Baudot
code) from the serial receiver. When one of these signals is
decoded, a flipflop is set (ENQRY or HEREISQ). If the
terminal is in HALF DUPLEX. the printer (PRNROF-)
andlor recorder (RECROF-) will be disabled while the
ABM is transmitting if they are on-line, depending on
switch S 1-6 and S 1-7. as shown inTab Ie 3-9 .1.This generates
an ABM busy (STOQ-) which removes the clear from the
character counter and starts the ABM sequence.
For each character (greater than 3) needed for station
identification. the corresponding diode in the first column
SWITCH 51
ZI7
!
'"
•
A
-c::::J-tr
CRI66
960881D
SHEET 4 OF 4.
I-!(;URl: 3-9.3. ANSWER-BACK MEMORY DIODE MATRIX
392
•
[-~,
TABLE 3-9.1. ANSWER-BACK MEMORY PC CARD SWITCH OPTIONS
(
Switch S2
Function
1
Open to remove CR141 (bit 7 character 15) from matrix
2
Open to remove CR21 (bit 1 character 21) from matrix
3
Open to remove CR121 (bit 6 character 16) from matrix
4
Open to remove CR101 (bit 5 character 17) from matrix
5
Open to remove CR81 (bit 4 character 18) from matrix
6
Open to remove CR61 (bit 3 character 19) from matrix
7
Open to remove CR41 (bit 2 character 20) from matrix
Switch Sl
('
I
I
Function
1
Close for ASCII card; open for Baudot card
2
Close for ASCII card; open for Baudot card
3
Close for ASCII card; open for Baudot card
4
Open for ASCII card; close for Baudot card
5
Open for ASCII card; close for Baudot card
6
Close to disable printing of ABM contents at all times;
open to enable printing of ABM contents when online in half-duplex
7
Same as SI-6 except for recorder
8
Close to put an ABM ON indication on pin 9 (future option);
open for NO indication (spare run on AUXIROF)
9
Close to ignore stop bit (continuous memory cycling)
open to stop ABM at stop bit programmed
1 and 4
Open both at same time to ignore triggering ABM from the line only
NOTES
1. Switch S2, all positions are normally closed; open only during unit test
2. Switch SI-9 is normally open; closed only during unit test
3. Switches are closed when the dot on the switch rocker arm is down
3-93
DC1, DC2, DC3, DC4, and EOT. The ADC can be
programmed to respond to or ignore DC1, DC2, DC3, and
DC4 characters coming from the serial receiver, transmitter,
or local data bus.
The ABM then generates and sends a request signal
(AUX2REQ-) to terminal control and loads the first
character stored in the diode matrix into a parallel-to-serial
converter. The ABM then waits for an enable to send signal
from terminal control (AUX2ENAS-). This signal and
eight system clocks are used to clock the first character
from the parallel-to-serial converter to the data bus. At the
end of this enable, the character counter is clocked to
character-2 and one clock time later another request is
generated and the second character is loaded into the
output register. This sequence continues until 21 characters
are shifted out, or the character counter reaches a character
in which one of the stop bit diodes (CR148 through
CR165) have been left in. When one of these diodes is
sensed, a stop signal is generated (ABMSTP) which prevents
generation of another request. The ABM is now ready for
another trigger signal.
The ADC may be programmed to respond to control
characters DC1 through DC4 by opening or closing the
appropriate switch sections on S2. Table 3-9.3 lists the
decodes and appropriate switch section to select to enable
or disable them. When the control characters have been
decoded, they are loaded into a register and encoded into
four control data bits CDBIT1 through CDBIT4.
Approximately 20 p.sec later control data strobe DCSTRBis generated. It is a negative-going 4.9-p.sec pulse. These four
data bits and the strobe are then sent to the ASR remote
cassette control where they are decoded and acted upon.
The terminal is programmed to respond to the control
character EOT by the installation of resistors R1, R2, and
R3. R1, R2, and R3 are installed only if the Auto Answer
PC card option is installed in the data terminal. Actuating
control character EOT will cause the terminal to disconnect
from the line only if the resistors are installed.
A remote trigger signal is also available on pin 24
(FSTIME-) of the ABM card. A 5-/lsec pulse on this pin
will cause the ABM to trigger as if the HERE IS key had
been depressed. This signal will trigger the ABM at all times,
except when the terminal is not on line. Another signal on
pin 19 (AUX2ROF-) is a remote clear for the ABM;
bringing this line low will hold a clear on the ABM. Both
these remote lines are used with other terminal options.
The Answer-Back Memory timing diagram, flow chart, and
state equations are shown in Figures 3-9.4 and 3-9.5, and
Table 3-9.2, respectively.
The ADC described above supersedes an earlier version of
the ADC (Part No. 960891). The earlier ADC functions the
same as the latest model ADC described above, except that
the enabling options are programmed with strappable
resistors R1 through R12, and there are no provisions for
decoding the control character EOT, nor for operation with
the Automatic Search Control (ASe) option, and the earlier
ADC has no master ON/OFF switch on the PC card. Table
3-9.4 lists the enabling options for the earlier ADC.
ABM switch options are listed in Table 3-9.1.
3-9.3 AUTOMATIC DEVICE CONTROL PC CARD. The
Automatic Device Control (schematic 971498) monitors
the data bus at all times except when the ADC's master
ON/OFF switch is OFF) and decodes control characters
3-9.4 ASCII 1200-BAUD RECEIVER PC CARD. The
1200-baud Receiver PC card (schematic 960303) is
TABLE 3-9.2 ANSWER-BACK MEMORY STATE EQUATIONS
STOD
STID
ST2D
ABMCLR
HERISENQ
PRNROF
AUXIROF
RECROF
ABMTRIGRST
ABMTRIGRST
ABMCER
=
=
=
=
=
(STID- x ST2D-)
(STDQ x HERISENQ) + (ST2Q x (ABMSTP- x AUX2ENASQ»
ST1Q + (ST2Q x AUX2ENASQ-)
PWRRST + AUX2ROF
HERISQ + ENQRY
PRNLOC-x FULDPX-x STOQSTOQRECLINE x FULDPX- x STOQABMCLR + TERLIN- + STOQStop ABM after transmission of memory is complete
Stop and reset ABM after the character now being transmitted
3-94
.~
.~
~
T=4.9 !pEC
~T~
RDRCLK
(204.8kHz)
SRVENA -
HERISENO
~.---------------------------------
ST20
!.J.>
r
~_~
STOO
ST10
~
--.J
---~------------------------------------------
----~~~--------------------------------------~
AUX2REO-
~~--------------------------------
..:0
(J1
~~------------------------------------~--
AUX2ENAS-
~
SCLKAUX2ENASO-
-.J
U
U
U
U
U
U
U
U~------
'}---------------------------------------.
L--_
ABMSTP
t
~
ABMOFF-
i
r-
1-
r
AUX1ROF(S 8 CLOSED)
TIMING IS SHOWN TO SEND 1 CHARACTER AND STOP FOR UP TO 21 CHARACTERS;
THE SAME TIMING APPLIES, EXCEPT THAT AT THE END OF EACH AUX2ENAS-,
THE STATE COUNTER RETURNS TO STATE-ONE INSTEAD OF STATE·ZERO.
FIGURE 3-9.4. ANSWER-BACK MEMORY TIMING DIAGRAM'
/---- ,
-,I
_J
:~j
.---------------------------------~
YES
NO
YES
RESET
ABM
YES
NO
YES
NO
NO
YES
RESET
ABM
NO
STO
r
ST1
ISSUE AUX2REQ
AND LOAD 1 ST
CHARACTER TO
OUTPUT BUFFER
FIGURE 3-9.5. ANSWERBACK MEMORY FLOW CHART (SHEET 10F 2)
3-96
(
ABM F LOW CHART
5ET AUX1ROF IF
S8ISCL05ED
I
r----------
ST2
ST1 OR 5T2
NO
NO
5ETPRNROF
IF 5615
CLOSED
,..-------.1
YE5
YES
SEND DATA
TO BUS
YE5
5ET RECROF
IF 57 IS
CLOSED
NO
INCREMENT
THE MATRIX
ADDR.CNTR
BY 1
-----------------~
FIGURE 3-9.5. ANSWERBACK MEMORY FLOW CHART (CONTINUED) (SHEET 2 OF 2)
3-97
TABLE 3-9.3. AUTO DEVICE CONTROL ENABLING OPTIONS
(for Part No. 971481)
Enabling Switch Section
Control Function
DCl andDC3
(Playback ON/OFF)
To Enable
When
Transmitting
To Enable
When
Receiving
To Enable
When in
Local
S2-l0N
(DC3 only)
S2-2 ON
S2-3 ON
S2-4 ON
S2-5 ON
DC2 andDC4
(Record ON/OFF)
NOTE
Control characters DCl through DC4 function in the selected operating modes shown above. Close the appropriate switch
section on S2 to enable the corresponding function. When the ADC ON/OFF switch is in the OFF position, all ADC
functions are disabled except the automatic disconnect on receipt of the EOT character (if the Auto Answer. Option is
installed).
TABLE 3-9.4. AUTO DEVICE CONTROLLER (EARLIER MODEL) ENABLING OPTIONS
(Part No. 960891)
To Enable
When
Transmitting
To Enable
When
Receiving
To Enable
In
Local
DCl (Playback ON)
Resistor Between
Rl
JI-J2
R2
J3-J4
R3
J5-]6
DC2 (Record ON)
Resistor Between
R7
J13-]14
R8
J15-J16
R9
J17-J18
R4
]7-J8
R5
J9-JI0
R6
J11-J12
R10
J19-J20
R11
J21-J22
R12
J23-J24
Control Function
DC3 (Playback OFF)
Resistor Between
DC4 (Record OFF)
Resistor Between
NOTE: All resistors are 10 ohm, 0.25 watt, 5 %.
3-98
(
FIFO and converts it from parallel to serial for transmission
to an external data set.
composed of two major sections. The system clock section,
which contains the master oscillator, generates the general
timing signal used throughout the terminal. The serial
receiver section accepts serial data at one of four speeds
from an external data set and prepares the data for
transmission to other parts of the terminal.
3-9.5.1 Input. Upon receipt of a transmit enable
(XMTENA) and eight system clocks (SCLK) from terminal
control, the input section stores the data from the serial
data bus (DATA) in the input buffer register on the leading
edge of the transmit enable, the line busy flipflop
(QLINEBUSY) is set to inhibit terminal control from
sending another character. On the trailing edge of
XMTENA, the shift-in flipflop (QSIENA) is set. If the
first-in-first-out (FIFO) buffer is ready to accept another
character, input ready (INPUTRDY) will be high. On the
next reader clock (RDRCLK), shift-in .(SHIFTIN) is
generated to load the character stored in the input buffer
register into the FIFO. The eighth data bit loaded into the
FIFO may be a MARK (logic ONE), odd or even parity (R6
installed), or the eighth data bit received from the data bus
(Rll installed) as determined by the PARITY switch and
the two optional resistors (R6 and R 11), only one of which
is installed at one time. The shift enable flipflop (QSIENA)
is cleared as soon as SHIFTIN is generated. The QLINBUSY
flipflop is cleared after approximately 800 p.sec when in the
high-speed mode or after a character is transmitted to the
line in the low-speed mode. Holding the line busy for at
least 800p.sec assures that the recorder has sufficient time
to record a character when the system is in HALF-DUPLEX
before terminal control sends the next one.
3-9.4.1 System Clocks. The system clock section of the
1200-baud receiver PC card is functionally identical to the
clock section of the 300-baud Transmit/Receive PC card
(described in Paragraph 3-6.1) with the following
exceptions. An additional HIGH SPEED switch is located
on the POWER switch panel adjacent to the keyboard to
set the terminal to operate at 1200 baud. This switch is
independent of the setting of the SPEED switch on the
receiver PC card. A block diagram of the system clock
structure is given in Figure 3-6.5. When the switch is in the
1200 baud position a SRVCLK of 76.8 kHz is generated.
3-9.4.2 Serial Receiver. Only three differences exist
between the 1200-baud receiver section and the 300-baud
receiver section (described in Paragraph 3-6.1). First, the
1200-baud
receiver accepts TTL data; ElA-to-TTL
conversion and enabling is done on the 1200-baud
Transmitter PC card. Second, inhibiting of the transmitter
while the receiver is receiving a character and the MODE
switch is in the HALF DUPLEX position is done on the
1200-baud Transmitter PC card. Third, if the printer is on
line and the speed switch is in the 1200 baud position, the'
printer may be held off (optional strap) with the printer
remote off (PRNROF-) signal.
Once a character is loaded into the FIFO, it is
asynchronously propagated to the last empty output
location. If more than 64 characters are entered before a
character is taken from the output, input ready (IR) output
from each of the FIFO's goes low, the 65th character
cannot be loaded until a character is taken from the output;
in addition LINEBUSY - is held low until the input ready
to FIFO goes ready.
If the optionally strapped PRNROF- signal is not used and
visible printing is desired at the 1200-baud speed, filler
characters must be added as follows:
(1)
Three deletes following each character
(2)
Twenty-two deletes after each CARRIAGE
return.
3-9.5.2 Data Set Interface. The data set interface generates
and accepts the necessary signals for operation with an
external data set. For 1200-baud operation a Bell 202C or
202D data set represents the external data set; at speeds of
300, 150, and 110 baud, a Bell 103A or equivalent
represents the external' data set. The 202C and 202D are
both half-duplex data sets; hence the request-to-send signal
(EIARTS) must be generated and the terminal must wait
for the clear-to-send signal (EIACTS) before transmitting
any data to the data set. Cable pin assignments for the 202C
or D are listed in Table 3-9.5_
The deletes compensate for the 30-msec print cycle
required by the printer plus the 190-msec carriage return
time needed by the printer mechanism.
3-9.5 ASCII 1200-BAUD TRANSMITTER PC CARD. The
1200-baud Transmitter PC card (schematic 962304) is
composed of three sections. The data set interface section
generates and accepts the necessary signals to operate with
a Bell System Model 202C, 202D, or equivalent Data Set.
The input section accepts data from the data bus and loads
a 64-character first-in-first-out (FIFO) buffer. The
transmitter section accepts data from the output of the
Signals generated by the data set interface and their
functions are as follows:
3-99
a
EIA Data Terminal Ready (EIADTR) - This
signal is ON (>3.0 volts) as long as the terminal
is on-line (TERLINE-, a logic ZERO). The ON
condition permits the data set to be connected
to the communication channel.
b.
EIA Transmitted Data (EIADATOT) - Serial
data to be transmitted by the data set; the
MARK, or logic ONE voltage is less than - 3.0
volts and the SPACE voltage is greater than 3.0
volts.
c.
EIA Request-to-Send (EIARTS) - This signal,
when at the MARK level (>3.0 volts), indicates
that the terminal wishes to transmit
information over the EIADATOT line. As long
as the terminal is in the full-duplex mode of
operation (FULLDPX- a logic ZERO),
EIARTS is held to the MARK condition. In the
half-duplex mode (FULLDPX-, a logic ONE)
EIARTS is held to the MARK condition as
soon as the FIFO indicates it has a character to
transmit by bringing output ready
(OUTPUTRDY) high. After the last character is
sent from the FIFO, OUTPUTRDY goes low.
After a 20-rnsec delay, EIARTS will fall to a
SPACE level (EIA low).
a.
Signals acce'p!~d by the data set interface and their functions
are as follows:
EIA data set ready (EIADSR) -- When in the
MARK condition (>3.0 volts) the signal
indicates the external data set is ready to
operate. This signal, in conjunction with EIA
clear-to-send (EIACTS), enables the transmit
section to send serial data to the external data
set. In conjunction with EIA data carrier
detection (EIADCD), this signal also enables
sending the serial data from the data set
(EIADATIN) to the 1200-baud Receiver PC
card.
b.
EIA data carrier detector (EIADCD) - When
this signal is in the MARK condition (>3.0
volts), it indicates a valid carrier signal is being
received by the external data set.
c.
EIA received data (EIADATIN) - Serial data
received from the external data set.
d.
EIA Clear-to-Send (EIACTS) - When in the
MARK condition (> 3.0 volts) this signal
indicates the external data set is prepared to
transmit data.
3-9.5.3 Transmitter Section. The transmit section (see
Figure 3-9.6) accepts parallel data from the output buffer
of the FIFO and converts it to serial data for transmission
/
TABLE 3-9.5. 1200-BAUD, EIA INTERFACE CABLE, PIN FUNCTIONS 4
(CABLE, TI PART NO. 959372)
Connector Pin Numbers
Terminal
I
Pin Function
Data Set
4
Data Terminal Readyl
Signal Ground
Clear to Send2
Data Set Ready 3
Received Data
Protective Ground
Request to Send6
2
8
Transmitted Data
Data Carrier DetectS
6
20
7
7
8
9
10
A
C
H
K
5
6
3
1
NOTES:
1 Held to an ON condition by the data terminal ON LINE switch.
2Turned ON in response to "request to send;" typical delay is approximately 220 msec.
3 Held to an ON condition when data set is operative; required for terminal operation.
4 All are used only with external modem.
S Held to an ON condition by modern when carrier is received; required by terminal for data reception.
6Turned ON when transmission begins; turned OFF 20 ,rnsec after transmission ends.
3-100
,, ___/
,~
~
~\
i
,-----1
II
KEYBOARD
I
I
•
BREAK
•.------l~~1
SERIAL
DATA
BUS
•
•
'- ____ J
PARALLEL
DATA
...
SERIAL DATA
XMITTER
.....
.-
r----l
I
I
MODEM
202C OR
:
202 D
r
I
r
~i
.... ____ J......_-+-..,
TRANSMITTER
RESET - -
PARALLEL
.... DATA
64-CHARACTER
FIFO
BUFFER
INPUT
BUFFER
~
k
SHIFT
IN
LOAD
LOAD
I
I..f
.....
DATA-SETREADY
o.....
INPUT
CONTROL
TRANSMITTERI SHIFT
CONTROL
OUT
CLEAR-TO-SEND
INPUT READY
REQUEST -TO-SEND
OUTPUT READY
TRANSMITTER
RESET
~
:l
m
w
Z
::J
,
r----'
r----'
.
I
AUX1.
I
•
I
J,
~
I
•
I
____
..'
TRANSMITTER
INHIBIT
I
I
I
PRINTER
L.. ____ J•
I-
:2:
X
r----l
I
I...
I
«
zw
j
REMOTE
OFF
I TIMINGI
I
i ..
SIGNAL
•
GENERATOR
I
II.. ____
I
J
FIGURE 3-9.6. 1200-BAUD TRANSMITIER PC CARD BLOCK DIAGRAM
TERMINAL
CONTROL
and stop bit (logic ONE) are added at the beginning and
end of the character, respectively. For lO-CPS* operation 2
stop bits are added. The BIT COUNTER counts the number
of bits transmitted and sets the transmit reset flipflop
(QXMTRST) after the tenth bit has been transmitted
(eleventh if the terminal is operating at 10 CPS; i.e., 10 CPS
is a. logic ONE). Once the transmit flipflop is cleared(XMTBSY logic ZERO), if QOUTPUTRDY goes high
(indicating the FIFO's have another character to transmit),
another transmit cycle is started. Also, if the terminal is on
line (the ON-LINE switch is set) and the BREAK key is
depressed, the output line is held to a continuous logic
ZERO (SPACE) as long as the BREAK key remains
depressed. A timing diagram is shown in Figure 3-9.7.
to an external data set. The transmit section is controlled
by the transmit-busy flipflop (XMTBSY). If the FIFO's
have data ready for transmission, each FIFO will have the
output ready (OR) high; hence QOUTPUTRDY will be
high. As soon as XMTENA goes high, the request-to-send
flipflop (TTLR,.TS-) is set to signal the data set that the
terminal has data to transmit ..
The reader clock (RDRCLK), which occurs after
OUTPUTRDY goes high, generates a shift-out pulse
(SHIFTOUT) if the data set is prepared to transmit data
(ETACTS high) and transmit inhibit (XMTIN4-, generated
by the AUXl device) is not low. The SHIFTOUT pulse sets
the XMTBSY flipflop and loads the parallel data into the
output buffer register when XMTBSY goes low; the pulse
then shifts the next character. into the output buffer of the
FIFO's, and output ready on each FIFO again goes high.
The serial receiver clock (SRVCLK) is divided by 64 to
generate the transmit clock (XMTCLK) to shift the
character out of the output buffer register to the data set.
In addition to the eighth data bit, a start bit (logic ZERO)
J
I
I
-'
"'---
If the terminal is in the HALF-DUPLEX mode of operation
(FULLDPX-, a logic ONE), each time the 1200-baud
Receiver PC card receives a character, a reset (RESET)
pulse is generated. The RESET pulse goes high after the
receiver has received half the start bit and goes back low
*CPS = characters per second
T3
1,
XMTENA-
r
1-
LINEBUSY-
QLlNEBUSY
I..
T4
INPUTRDY
~
.. I
4-l
SIENA
1-
n
SHIFTIN
1-
--t T2 I--
RDRCLK
-~
IL
-JlJUl{
1-
axMTRDY
r
XMTBSY-
T1
1r
-I
T2= 4.9 ]..!SEC
n= lCHAR. TIME
T3=88 ]..!SEC
T4=782 ]JSEC
FIGURE 3-9.7. 1200-BAUD TRANSMITTER PC CARD INPUT SECTION TIMING DIAGRAM (FOR l-CHARACTERINPUT)
3-102
,/
(
options or RDC option also installed) when the
call is answered. The ABM is triggered after an
adjustable (with resistor jumpers) delay of 2
msec to 10.2 sec in nine steps from the carrier
detect signal (see Table 3-9.6).
after the parity bit is received. When RESET goes high the
half-duplex flipflop (RCVHDPX) is set, causing the line to
be busy so that no character may be sent to the transmitter.
The line is held busy to the transmitter for one character
time after the last character is received from the line. This
process prevents the transmitter from attempting to
transmit a character while the receiver is receiving a
character in half-duplex. Conversely, while the transmitter
is transmitting a character in half-duplex, the receiver is
inhibited by TTLRTS from receiving a character.
(2)
3-9.6 AUTO ANSWER CONTROL. The optional Auto
Answer Control basically consists of a PC card, a display
panel and cabling, and a 6-foot (minimum) EIA or modem
cable assembly in kit form. Two versions of the Auto
Answer Control Kit are available: one for use with Bell
System 103 Data Sets (TI Part No. 960984-0002) and one
for use with the Bell System Type-CBS Data Access
Arrangement (TI Part No. 960984-0001).
Table 3-9.7 lists interface resistor options for the two versions. Logic diagrams of the Auto Answer Control and its
display PC card are shown in drawings 962307 and 962308
in Appendix C of this manual; assembly drawings are contained in Appendix B.
The Auto Answer Control cannot be used with the 733
Data Terminals equipped with the 1200-baud
transmit/receive option. Furthermore, TI recommends'
using the Auto Answer Control in conjunction with the
Answer-Back Memory plus the Remote Device Control
option or with the Auto Device Controller option,
although the Auto Answer will function without them.
(a)
A carrier from the originating station is
not received within 10 seconds after a call
is answered.
(b)
The carrier from the originating station is
lost for at least 50 msec during the
progress of a call.
(c)
A disconnect character (usually EOT) is
received from the originating station (if a
remote device control option is installed).
(d)
A SPACE of at least' 1.28 seconds
without a mark is received from the
originating station.
Table 3-9.8 lists resistor options necessary to implement
either Auto Answer Control version.
The following power is required by either version:
+5 vdc @ 380 rnA (maximum)
+12 Vdc@ 10 mA (maximum)
-12 vdc @ 8 rnA (maximum)
3-9.6.1 Auto Answer Control with Belll03A Data Set. This
version of the Auto Answer Control (TI Part No.
960984-0002) provides the 733 the capability of
automatically answering a call on a Bell System DDD
network which has a Bell 103A Data Set with auto answer.
This version of the Auto Answer Control plugs into PC card
slot A8 in the 733 lower enclosure.
In addition to automatically answering a call, the Auto
Answer Control includes the following features:
(1)
Automatic disconnect from the line and
blinding of the printing and record functions if
any of the following conditions occur:
Automatic triggering of the Answer-Back
Memory (ABM) option (with ABM plus ADC
3-103
a.
Indicators
The following indicators (located on the 733
option panel) are provided with the Auto
Answer Control:
RING INDICATOR - lamp blinks 2
seconds on and 4 seconds off with the
ring indicator of the Bell System 103A. It
illuminates steadily after the call is
answered (i.e., the DTR line is turned on)
until the carrier is received from the
originating station.
TERMINAL READY - illuminates when
the 733 ON-LINE switch is ON-LINE,
indicating that the terminal will answer
an incoming call.
LINE READY - illuminates when the
terminal has answered the call, received
the carrier from the originating station,
and is ready to transmit or receive.
h.
Typical Operations
Before leaving the data terminal unattended,
the operator must switch the appropriate data
TABLE 3-9.6. ANSWER-BACK MEMORY TRIGGER-DELAY CHART, RESISTOR OPTIONS
.
Delay
10.24 sec
5.12 sec
2.56 sec
1.28 sec
640 msec
320 msec
160 msec
80 msec
0.6-1.9 mse«
InstalllO~,
0.25 W
Resistor!
Between
R15
R16
R17
R18 2
R19
R20
R21
R22
R23
JI0 andJ16
J9 andJ14
J8 andJI
J7 andJ15
J6 and J17
J5 andJ15
J4 and J14
J3 andJI
J2 and J16
NOTES
1. Only one of R15 through R23 is used.
2. Resistor normally installed.
TABLE 3-9.7. AUTO ANSWER CONTROL INTERFACE SELECTION CHART,
RESISTOR OPTIONS
Insta1110~,
0.25W
Resistor
For Use With
Between
DAA
BELL 103
Rl
J12 and J18
Open
1051
R2*
J13 andJll
1051
Open
*Resistor normally installed.
3-104
y
f
terminal function (RECORD, PLA YBACK
and/or PRINTER) to the LINE mode, switch
the data terminal to ON-LINE, and switch the
Bell 103 Data Set to AUTO. A typical
operating sequence (assuming that
Answer-Back Memory and Remote Device
Control options are installed) is shown in the
following flow chart:
Originating station dials terminal number.
I
Playback transmission continues until a DC3
character is received from the originating
station or tape.
I
The originating station begins transmitting data
to the terminal (preceded by DC2 if it is to be
recorded), followed by an EOT.
I
I
The terminal receives the EDT and turns off the
DTR line, thereby terminating the call.
Terminal detects ringing indicator (RI) from
Bell 103.
A flow diagram of the Auto Answer Control functions is
shown in Figure 3-9.8, and state equations are listed in
Table 3-9.9.
I
Terminal turns on data-terminal-ready (DTR)
line.
c.
1
The Interface signals conform to EIA Standard
RS232C. The interface connector is a 25-pin
Cannon DB-25P (or equivalent) at the end of a
6 foot (minimum length) cable. Pin assignments
and functions are shown in Table 3-9.10.
Bell 103 answers the call, turns. on the
data-set-ready (DSR) line and transmits a
MARK tone after a 1 to 2 second delay.
I
The originating station receives transmit MARK
from answering terminal and turns on its
transmit MARK tone after a 1 to 2 second
delay.
3-9.6.2 Auto Answer Control with Bell Type-CBS Data
Access Arrangement. This version of the Auto Answer
Control (TI Part No. 960984-0001), together with an
"answer-mode" modem option, provides the capability of
automatically answering a calIon a Bell System DDD
network which has a Bell type-CBS Data Access
Arrangment.This version of the Auto Answer Kit plugs
into PC card slot A7 in the 733 lower unit PC card rack.
1
The Bell 103 at the answering terminal receives
the transmit MARK from the originating
station and turns on its clear-to-send and
carrier-detect lines after a 315-msec delay.
All other general capabilities are the same as the Auto
Answer Control version described in paragraph 3-9.6 above.
1
After an adjustable delay,
answer-back is transmitted.
the
Interface Requirements
terminal
a.
Indicators
The following indicators (located on the 733
option panel) are provided in the Auto Answer
Control:
1
The originating station verifies the answer-back
and turns on the playback by transmitting a
DC 1 character.
RING INDICATOR - lamp blinks 2
seconds on and 4 seconds off with the
ring indicator of the Bell System DAA. It
illuminates steadily after the call is
answered [i.e., the off-hook (OH) line is
turned on] until the carrier is received
from the originating station.
1
The terminal receives the DC1 and begins
transmitting from the playback unit.
~
3-105
RESET LIN ROY
& TIMER
TTLDTR
TO OFF
ANO
RESET
LOGIC
SET LlNBUSY
RESET RING
INDICATOR
(RNGIND)
NO
YES
1+------1
RESET FSTIME
(RCVD DATA
LOCKOUT)
SET RNGND
& TTLDTR
STO
SET RNGIND
& TIMER
YES
TRIGGER
ABM
RESET
TIMER
STl
SET
TIMER
ST2
ST3
RESET
TIMER
RESET
TTLDTR
SET FSTIME
(LOCKOUT
RCVD
DATA)
SET
TIMER
FIGURE 3-9.8. AUTO ANSWER CONTROL, FUNCTIONAL FLOW DIAGRAM
3-106
--
------~--
-----------
TABLE 3-9.8. AUTOMATIC DISCONNECT AND AUTOMATIC ANSWER-BACK MEMORY
TRIGGERING, RESISTOR OPTIONS
(
Delete 10n
Resistor
To Disable
Disconnect (hang-up)
line upon receipt
of EOT character
R5
Long-SPACE
Disconnect
R3
Automatic Triggering
of Answer-Back
Memory
R12
TABLE 3-9.9. STATE EQUATIONS FOR AUTO ANSWER CONTROL
(
-
""
STOD
STlD
ST2D
ST3D
TIMERRST
TTLDTRD
LINBUSY
FSTIME
AUX2ROF
TD1.28 SEC
TD(xxx)MS
TD10.24 SEC
T1MERRST
STATE 0
STATE 1
STATE 2
STATE 3
=
=
=
=
=
=
=
=
=
=
=
=
=
=
ST1D- * ST2D- * ST3DSTOQ * TTLDTR * TTLDSR + STlQ * (TTLDCD- * TD10.24SEC-)
ST1Q * TTLDCD + ST2Q * TD(xxx)msecST2Q * TD(xxx) MS + ST3Q * RCVEOT- * TI'LDCD * TD1,28 SecSTOQ + ST1Q * TI'LDCD + ST3 * LNDATAQ
TTLRNG + TTLDTR * ( (STlQ + ST3Q) * STOD-)ST3Q(ST1Q * TTLDCD) + TTLDTRTI'LDTRST3Q * LNDATAQ-* (1.28-sec delay time)
ST2Q * (SELECTED delay time)
ST1Q * TTLDCD- * (10.24 sec delay time)
STOQ + STlQ * TTLDCD + ST3Q * LNDATAQ
Wait state, no call in progress
Received ring indication, answer call, and wait for carrier detect
(trigger ABM when carrier detect is received)
Received carrier detect, wait for ABM delay
ABM delay over, send ABM and set line ready indicator
3-107
TABLE 3-9.10. AUTO ANSWER CONTROL PIN ASSIGNMENTS WITH BELL 103 DATA SET
(CABLE, TI PART NO. 971555-0001)
Bell 103 Data Set
Interface
Conn Pin No.
Terminal
Cann01)
Pin No.
1
2
3
5
6
A
H
10
8
9
7
7
8
20
22
(All other pins
not used)
K
E
D
Signal
Source
Common
Terminal
Data Set
Data Set
Data Set
Common
Data Set
Terminal
Data Set
Signal Function
AA BA BB CB CC AB CF CD CE -
Protective Ground
Transmitted Data
Received Data
Clear-to-Send
Data-Set-Ready
Signal Ground
Carrier Detect
Data-Terminal-Ready
Ringing Indicator
TABLE 3-9.11. AUTO ANSWER CONTROL PIN ASSIGNMENTS WITH BELL TYPE-CBS
DATA ACCESS ARRANGEMENT
(CABLE, TI PART NO. 971557-0001)
Terminal
Conn U1)
Pin No.
DAA
Terminal
Lugs
C
3
6
E
5
DT
DR
DA
OH
CCT
SH
SH1
SG
RI
4
7
D
Wire
Color
Orange
Yellow
Brown
Red
White
Blue
Black
Green
Bell Systems Description
Data Tip
Data Ring
Data Transmission
Off Hook
Coupler Cut Through
Switch Hook
Switch Hook Return
Signal Ground
Ring Indicator
3-108
Function
Connection to phone line
Connection to phone line
Held ON by terminal to request data transmission
Held ON by terminal to answer and maintain a call
Held ON by DAA when data path has been established
Not used by terminal
Not used by terminal
Return path for control signals
Ringing signal present
y
(
TERMINAL READY - illuminates when
the 733 ON LINE switch is ON-LINE,
indicating that the terminal will answer
an incoming call.
Variable delay by terminal, 3 msec to 10
seconds.
I
Answer-Back Memory is triggered, incoming
call light OFF, line-ready light ON.
LINE READY - illuminates when the
terminal has answered the call, received
the carrier from the originating station
and is ready to transmit or receive.
b.
I
Originating station receives and verifies the
answerback and transmits the PLAYBACK ON
character.
Typical Operations
I
Before leaving the terminal unattended, the
operator must switch the appropriate data
terminal function (RECORD, PLAYBACK
and/or PRINTER) to the LINE mode and the
data terminal to ON-LINE. A typical operating
sequence (with Answer-Back Memory and
Remote Device Control options installed) is
shown in the followiqg flow chart.
Terminal receives the PLAYBACK ON
character and begins transmitting from the
playback tape.
I
Playback transmission continues until a
PLAYBACK OFF character is received from
the originating station or the tape.
I
Originating station dials terminal number.
The originating station begins transmitting data
to the terminal (preceded by RECORD .ON if it
is to be recorded) followed by a EOT code.
I
Terminal detects ringing indicator (RI) from
DAA; RING INDICATOR lamp blinks.
I
I
The terminal receives the EOT and turns off the
OH line to the DAA, thereby disconnecting the
call.
Terminal turns on the off-hook (OH) signal;
RING INDICATOR lamp glows steadily.
I
1 to 3 second delay by DAA.
A flow diagram of the Auto Answer Control functions is
shown in Figure 3-9.8, and state equations are listed in
Table 3-9.9.
I
DAA turns on CCT line.
c.
T
Terminal turns on transmit MARK tone (F2M).
The control signals to the DAA are compatible
with the logic levels and conventions defined in
EIA Standard RS232C. The signals-to-phone
line (DT and DR) is described under modem
options (see Paragraph 3-9.1). The interface
connections to the DAA are spade lugs which
attach to the screw terminals of the DAA. Pin
assignments and functions are listed in Table
3-9.11.
I
Originating station receives F2M and turns on
itl; transmit MARK (F1M) after a 1 to 3 second
delay.
I
Terminal receives F1M and turns
carrier-detect signal from internal modem.
Interface Requirements
on
~
3-109
3-9.7.2 Data Timing and Decoding. Data timing (see Figure
3-9.10) is accomplished by synching the ASC to Terminal /' ".
C~ntrol through two signals: device-enable and terminal,,--/
control state-ONE. The device-enable determines when a
data transfer will take place. The enables are
3-9.7 AUTOMATIC SEARCH CONTROL. The Automatic
Search Control (ASC) option provides the capability to
automatically search at high speed for a desired record
contained within a tape cassette. Schematics [971S00(M/L)
or 971S03(M/W)] of the ASC are contained in Appendix C.
Signatures are listed in Appendix A.
As shown in Figure 3-9.9, the operator (or remote device
if used in conjunction with the Remote Device Control
option) enters an activate code on the ASR data bus
through the keyboard (or over the remote line). The ASC
recognizes the code and if in local mode responds locally by
causing a paper advance (KBPA) signal. The printer
performs a line feed and a carriage return. The operator (or
remote device) can then enter from one to 16 printable
USASCII characters into the search field memory of the
Automatic Search Control. After the 16th character is
entered into memory, the printer is switched off via
PRNROFF.
The ASC waits for the cassette to be activated and then
writes N-l characters (one less than entered by keyboard or
line) into its cassette data memory. When the cassette data
memory is loaded, a character-by-character comparison
begins. The ASC then compares up to N-l characters at
which time the ASC waits for one more character from the
tape to complete the sequence. If the N-l field comparison
is positive (N-1 matches) and the last character [(N-l)+1] is
a match, the ASC stops the cassette and issues a paper.
advance signal if the data terminal is in local mode. If the
fields do not compare, the ASC will shift the cassette data
memory data by one character and begin an N-l compare
again.
KBDENA - keyboard data
RDRENA - cassette data playback
RMTENA - line data, generated by the RDC.
Terminal control state-ONE (TCST1) indicates when the
data transfer is complete. The data is actually transferred
by the serial clock (SCLK). The flipflop CHRDY sets when
the correct enable is up, the eight serial clocks have passed,
and the falling edge of TCSTI occurs. At th~ point in the
data path, the data is stable, so the outputs of the decoders
are inspected for
Printable characters
Activate code (ESC and $).
If the character is printable, a signal (CHROK) is sent to
logic control to signify that the character is ready and
printable.
The read-only memory (ROM) controller is the heart of the
Automatic Search Control. The ROM has three. basic
functions: data path control, data timing and decoding, and
logic control.
3-9.7.1 Data Path. The data path begins at the ASR data
bus. The ASC converts the serial data to parallel which is
applied to the input of the decoders and to the 8-bit
parallel buffer register. The output of the buffer register is
applied to both the search field memory and the cassette
data memory where, at the appropriate time, a write pulse
is applied to one of the two memories (16 x 8 bit) to load
that character.
The outputs of the memories are continuously fed to two
8-bit magnitude comparators which determine equality.
During the character-by-character tape search, the two
comparators signify a match.
3-110
3-9.7.3 Logic Control. The logic control performs two
primary functions: state control and function control.
a.
State Control - State Control is implemented
in three basic steps: (1) defining the
step-by-step sequence in which the controller
operates; (2) storing the steps into a permanent
read-only memory (ROM) to be recalled later in
a
predetermined
sequence;
and
(3)
implementing the ROM control to assign each
step or memory cell to a specific forcing
function.
The flow chart (Figure 3-9.11) and block
diagram (Figure 3-9.12) illustrate the concept.
The diamonds on the flow chart represent
forcing functions; the rectangles are control
functions; and the connecting lines are jump
paths. For example, note that state 11 (state
numbers are written in each block) has three
jump paths (10, J1, J2) and two forcing
functions (STOP BIT and MATCH). The
dominant forcing function is STOP BIT which
determines the primary decision regardless of
MATCH. If STOP BIT is true, the memory
output forces the state counter to address 10; if
it is false, MATCH determines whether address
OF or OE is forced.
NO
YES
NO
YES
NO
USE NEW
N
LOAD CHARACTER
INCREMENT(N) COUNTER
USE OLDN
yes
NO
READ N-1 CHARACTERS
INTO COMPARE BUFFER
TURN PRtNTER OFF
NO
READ ONE MORE
NO
CHA~ACTER FROM
TAPE
STOP TAPE ISSUE
CR & LF IF LOCAL
TURN PRINTER ON
YES
INCREMENT
COMPARE COUNTER
BY ONE AND BEGIN AGAIN
FIGURE 3-9.9. AUTOMATIC SEARCH CONTROL SIMPLIFIED FLOW CHART
3-111
1
I
--+i 5 ~ect--
+ - - - - - t L1l...I1J1..J1.
RDRClK
TCST1
--+-1
15 Ilsec
L-
14-1
DATA ENABLE
(KBD,RMO,RDR)
----'1
~I
1
~
1
10llsec
______
--+-17.5 ~ec
.....
.....
N
SERIAL ClK (SClK)
1~I~__________________________________________________________~
1 1
I'.....h-I--
LJ
BIT 1
CHRDY
I.
THIS EDGE CLOCKS DAT~~
U
BIT 2
U
U
BIT 3
BIT 4
U
BIT 5
U~
BIT 6
BIT 7
U
BIT 8
'-
- - - - - - - - - - - - - - - - - - - - - _.....
PRNCHR
r
CHROK
"-
IF THE CHARACTER
IS PRINTABLE
FIGURE 3-9.10. AUTOMATIC SEARCH CONTROL DATA TIMING
t
\
\
c
:-.\
)
//
'\
r-\)
\
\. . . /
CHROK ~ PRINTABLE CHARACTER CHARACTER READY
SFMA ~ SEARCH FIELD MEMORY ADDRESS
SSFMA
~
STORE SEARCH FIELD MEMORY ADDRESS
SFMW - SEARCH FIELD MEMORY WRITE
CDMW - CASSETTE DATA MEMORY WRITE
CDRAR - CASSETTE DATA RAM, ADDRESS REGISTER
CPRFG - COMPARE FLAG
SINCHARFG ~ SINGLE CHARACTER FLAG
KEVFlAG ~ THE LAST TRANSACTION WAS A KEYBOARD ENTRY
SFMAUF ~ SEARCH FIELD MEMORY ADDRESS UNDER FLOW
RfEED '" TAPE IS MOVING IN PLAYBACK MODE
(
NA(X) MUX
o o· PA
01 Jl
l1-J2
1 O· jO
la) CONTINUOUS
Ib) SLK FWD
jcl CHAR FWD
TYPICAL
CONTROL
FUNCTIONS
t
J'---
- - ----- -- -
n
-
FIGURE 3-9.11. AUTOMATIC SEARCH CONTROL FUNCTIONAL FLOW DIAGRAM
3-113
applied to the inputs of the memory address
register (NAA-NAE) the output of which is fed
to the five ROM's.
Thus, address 11 has three possible next address
jump paths: JO = OE, J1 = OF, and J2 = 10.
The method by which they are chosen is
determined by the conditions of the forcing
functions STOP BIT and MATCH when the
clock switches.
b.
The forcing functions are selected by a 2-bit
wide, 24-position multiplexer. The multiplexer
consists of three sections of two (8 ~ 1)
multiplexers, which are separated into two
control bits: A and B. When, for example,
address ZERO is applied to the multiplexer,
AAM slot-zero is switched to a three-input OR
gate (SELA); and BAM multiplexer slot ZERO
is switched to a three-input OR gate (SELB).
SELA and SELB are coded into a 2-bit field to
select the jump paths. Actually, there are four
jump paths: JO, J1, J2, and PA (present
address). However, PA is not stored in memory
since it is available at the output of the memory
address register. A truth table for these four
jump paths is shown below.
Bit A
0
0
1
1
Bit B
0
1
1
0
PATH
PA
J1
J2
JO
The AlB bits are applied to the next address
(NAM-NEM) selectors which are 4 ~ 1
multiplexers. The outputs of these selectors are
Function Control. The function controls
operate much the same way as the state
control. The control lines needed to make
things happen (clock counters, operators, reset
flipflops and control data path) are well defined
in Figure 3-9.11. The control line functions are
stored in the control ROM to be used where
appropriate. Each control line is a discrete line
from a ROM to the particular device to be
clocked or gated, and each' line is
preprogrammed to switch HIGH or LOW in
those states shown in Figure 3-9.11.
The flow chart in Figure 3-9.11 shows that
state 11 can step to-any of three states: 10 via
path J2, OF via J1, and OE via JO. As the
controller steps through one of these states, it
must perform its assigned task. The following
control functions occur each time the
controller passes through the noted states.
State
OE
OF
10
3-114
Transfer Function (Control Function)
Increment SF memory address (INCSFMA)
Increment Cassette Data RAM address register
(INCDRAR)
INCSFMA
INCDRAR
Clear the compare flag (0 ~ CPRFG)
Wait for diamond decisions
./
Cassette-l in RECORD mode
Cassette-2 in RECORD mode
Block forward
Block reverse
Printer ON
Printer OFF
Auto Device Control ON
Auto Device Control OFF
Request status
1200-baud print local
ASC remote cancel
3-9.8 REMOTE DEVICE CONTROL. The optional Remote
Device Control (RDC) consists of a single printed-circuit
card which plugs into KSR card slot A6. A manual
ON/OFF switch for the RDC is located atop the PC card,
accessible by lifting the terminal cover. Schematics of the
RDC [971499(M/L) and 971504(M/W)] are contained in
Appendix C.
The RDC permits remote control of most 733 ASR
operations via data received over the communication line.
The RDC decodes and acts upon on-line data in the form of
ASCII character and control codes.
3-9.8.1 Function Codes. All functions are performed by the
'RDC upon receipt of specific ASCII characters which are
established by a programmable read-only memory (PROM)
and an option resistor on the ROC PC card. Five functions
are performed with single characters from the USASCII
control character subset. All other functions are performed
using a sequence of two USASCII characters: the first
character is derived from the control character subset; the
second character is derived from either the control
character subset or the third and fourth columns of the
USASCII code (see Table 3-4.2), as selected by the option
resistor.
NOTE
Once a function is selected in one of the
two subsets, all other functions are
contained in the same subset.
(
The standard function code selections are listed below.
a.
Single-Character Functions
Playback ON
DCl
Playback OFF
DC3
Record ON
DC2
Record OFF
DC4
Autodisconnect (when used) with Auto Answer
Control option - EOT
First character of double-character sequence (normally DLE)
b.
Two-Character Functions - These functions are
performed using the USASCII control character
DLE plus the following character
Rewind cassette-l
1
Rewind cassette-2
2
Load cassette-l
3
Load cassette-2
4
.,
•
5
6
7
8
9
o
<
>
?
NOTE
The printer is automatically disabled
from printing the first character following
receipt of the DLE character.
c.
Function Description
Playback On function
enables the tape playback
Playback Off function
disables the tape playback
Record On function.
enables the tape recording
Record Off function.
disables the tape recording
Auto .Disconnect (EOT) - disconnects the
printing and recording functions from on-line
(if used in conjunction with Auto Answer
Control option).
Rewind Cassette 1 - causes the tape in
cassette-l to slew at high speed toward the
beginning of tape until clear leader is sensed.
Rewind Cassette 2 - causes the tape in
cassette-2 to slew at high speed toward the
beginning of tape until clear leader is sensed.
Load Cassette 1 * - causes the tape in cassette-l
to wind forward from clear leader to the
beginning of tape.
Load Cassette 2* - causes the tape in cassette-2
to wind forward from clear leader to the
beginning of tape.
Cassette-l in Record Mode - places cassette-l
in RECORD mode; cassette-2 will be in
- PLAYBACK mode (dual-cassette models) .
*If the tape cassette is not on clear leader (i.e., it is on tape), a fast forward will initiate. A fast forward cannot be stopped by
a remote command.
3-115
Cassette-2 in· Record Mode - places cassette-2
in RECORD mode (dual-cassette models);
cassette-l will be in PLAYBACK mode (all
models).
Bit 1 (least significant bit) indicates the playback
function is ready when bit 1 is a logic ONE. If bit 1 is
a logic ZERO, playback is NOT ready for one of the
following reasons:
Block Forward - causes the next block on tape
to be read and played back (or the remainder of
a block if playback stopped in the middle of a
block).
(l)
Cassette door open or cassette not in place
(2)
Cassette on clear leader
(3)
Playback not in LINE mode
(4)
Other operations being performed; e.g., rewind.
Block Reverse - causes the tape to reverse one
block and stop.
Printer On - enables the printer to receive data
from the communications line (if the PRINTER
switch is set to LINE) after having been
disabled.
Printer Off - disables the printer from receiving
line data. If this code sequence is received when
the printer is in either the LINE or LOCAL
mode, the printer is disabled while in the LINE
mode. This function is reset and reverts to the
Printer-ON condition when the terminal is
switched OFF-LINE or when power is switched
OFF and ON ..
Auto Device Control ON - enables the
functions playback ON/OFF (DCl, DC3) and
record ON/OFF (DC2, DC4) after having been
disabled by the Auto Device control OFF
function.
Auto Device Control OFF - disables the
functions playback ON/OFF (DCl, DC3) and
record ON/OFF (DC2, DC4), which is
particularly useful when recording data from
the line containing the playback ON/OFF or
record ON/OFF characters (e.g., format tapes).
ADC OFF is reset and reverts back to the ON
condition when the terminal is switched OFF
LINE, or power is switched OFF and ON.
Request Status - enables the terminal to send
the status character (see below). It is
particularly useful in determining when a
rewind, load, or other function has been
completed.
3-9.8.2 Status Character. The status character is a USASCII
character transmitted by the, data terminal when the
"request-status" code is received from the line. The specific
status and bit locations are
3-116
Bit 2 - indicates a playback error has been made if
bit 2 is a logic ONE. A logic ZERO indicates a
playback error has not been made. If the playback is
strapped so as not to stop on an error (see paragraph
2-6.2), bit 2 will indicate a ONE only while a block
with an error is being (or waiting to be) transmitted.
NOTE
A playback error may be cleared using
the remote control functions
PLAYBACK ON, BLOCK. REV, or
BLOCK FWD.
Bit 3 - indicates cassette 1 is on clear leader at either
end of tape if Bit 3 is a logic ONE. A logic ZERO
indicates the cassette is not on clear leader.
Bit 4 - same function as bit 3 for cassette 2.
Bit 5 - indicates that the record function is ready to
be enabled with the record ON signal when bit 5 is a
logic ONE. If bit 5 is a logic ZERO, record is not
ready for one of the following reasons:
(l)
Cassette-door-open or cassette-not-in-place
(2)
Cassette on clear leader
(3)
Record not in LINE mode
(4)
Other operation being performed; i.e., rewind
or load
(5)
Tape cassette write tab removed.
Bit 6 - indicates that the printer is ready when bit 6
is a logic ONE. If bit 6 is a logic ZERO, the printer is
not ready for one of the following reasons:
/--
..
(-
(1)
Printer not in LINE mode
(2)
Printer is off as a result of "printer off"
command, or the Automatic Search Control
(ASC) is searching.
Bit 7 - always a logic ONE to force the status
character out of the control character subset. This bit
may be optionally switched on the PC card to
indicate PLA YBACK-ON status (see Table 3-9.12). In
this case a logic ZERO indicates playback is on (i.e.,
playback either reading tape or transmitting data) and
a logic ONE indicates playback is not on. Bit 7 is
particularly helpful in determining when the ASC is
searching tape and when the search is completed. If
bit 7 is used, the status character is not excluded
from the control character subset.
c.
Manual Function Disable Control - A switch
located atop the ROC PC card permits
switching off all functions except the
auto-disconnect function EOT character when
used with the Auto Answer Control option.
d.
Other Functions - All other functions are
enabled only on received data.
3-9.8.4 Additional RDC Card Options.
a.
EXAMPLE
If playback is ready, a playback error has
not been made, cassette-1 is not on clear
leader, cassette-2 is on clear ieader, record
is not ready, and printer is ready, the
status character would be
b 1 -ONE
b 2 - ZERO
b 3 - ZERO
= USASCII character "i"
b 4 -ONE
b s - ZERO
b 6 - ONE
b 7 - ONE (strapped to logic ONE)
During anon-line search, the OC3 (PLAYBACK
OFF) control character will be ignored if
encountered. No data is transmitted during an
on-line search except status (if requested) or
the CAN character if a playback error occurs,
and the CAN character is enabled.
3-9.8.3 Function Operating Modes. The remote control
functions are performed when the appropriate codes are
contained in the transmitted, received, and/ or local data as
described in the following paragraphs.
a.
b.
(
Remote Search (with ASC Option) - The RDC
permits remote initiation of the optional
Automatic Search Control (ASC) from the
communication line. The initiation sequence to
the ASC is enabled if PLAYBACK is set to
LINE, the cassette is ready and the ROC is ON.
Once search is started, the same conditions are
also required for the ASC remote cancel code
to be acted on. If these conditions are met and
the double-character ASC remote cancel code is
received from the line, the RDC will send a
search cancel signal to the ASC. Status may be
requested from the controlling device any time
during the search. The on-line search speed is
always 320 characters per second. No on-line
tape duplication during search is possible.
Playback On/Off - The playback-OFF function
is performed on transmitted, received, or local
data. It may be disabled in anyone or all modes
using pencil switch S-2 on the RDC PC card as
shown in Table 3-9.12. The playback ON
function is performed on only received or local
data; it too may be disabled using the pencil
switch.
Record On/Off - The record ON/OFF function
is performed only on received or local data. It
may be disabled on received and/or local data
via the pencil switch as shown in Table 3-9.12.
3-117
b.
Automatic ASCII "CAN" character on
Playback Error - If this switch-selectable
option is set on the RDC, the ASCII CAN
character will be automatically transmitted to
the line whenever a read error is detected
during playback. The conditions required for
sending an automatic indication of an error are
(1)
Playback must be on-line and ready.
(2)
The RDC PC card must be ON.
(3)
A playback error must be detected by the
playback controller.
This switch-selectable option (S-2, position 7) is
normally open, which disables automatic
transmission of the CAN character on a
playback error.
TABLE 3-9.12. RDC PC CARD SWITCH S2 OPTIONS
Switch S2
Position
Function
1
2
3
4
Data Source
Record ON/OFF
Record ON/OFF
Playback ON/OFF
Playback ON/OFF
Playback OFF
Playback-ON Status
CANcel character on read error
5
6
7
Normal
Switch State
Local data
Received data
Local data
Received data
Transmitted data
N/A
N/A
ON
OFF
TABLE 3-9.13. REMOTE DEVICE CONTROL CODE BITS FOR ASR
(UPPER UNIT) FUNCTIONS
Code Bits
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
I
3
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
I
4
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
I
Strobe
Decoded
Signal
1.
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RDRON
RDROF
RCDON
RCDOF
XREWI
XREW2
XLD/FW1
XLD/FW2
XBSPFW
XBSPRV
XC 1 RCD
XC2RCD
XRCHFW
XCAISTP
XCA2STP
Unused
3-118
Function
Playback On (DC1)
Playback Off (DC3)
Record On (DC2)
Record Off (DC4)
Rewind Cassette-l
Rewind Cassette-2
Load or F/FWD Cassette-1
Load or F/FWD Cassette-2
Block Forward
Block Reverse
Cassette-1 Record
Cassette-2 Record
Send One Character
Cassette-1 Stop
Cassette-2 Stop
(
c.
d.
Footswitch for Local Playback-ON - This
feature on the RDC permits use of a footswitch
which closes a contact to ground to initiate the
playback-ON function. Conditions required for
enabling the footswitch are
(1)
Playback must be local.
(2)
The ROC card must be ON.
Rewind from the Right End - This feature on
the RDC permits rewinding a tape cassette
which is on clear leader at the right end of the
tape; i.e., the takeup reel is full and the END
lamp is illuminated. The only conditions
required for this action are
(1)
The cassette to be rewound is on clear
leader.
(2)
A rewind command for that cassette is
issued.
the RDC. If used, the rewind from-right-end
feature described in paragraph d. above is not
possible.
3·9.8.5 Theory of Operation. The optional Remote Device
Control (RDC) has two main functions:
(1)
Decoding characters from the serial data bus and
causing initiation of the appropriate action for that
code or code sequence
(2)
Performing certain additional on-line or local
functions, including the footswitch pedal option,
automatic sending of the ASCII CAN -character upon
detecting a playback error, 1200-baud print-local
option remote search option (with the Automatic
Search Control), and rewind the tape cassette from
the right-end option.
a.
NOTE
When a rewind from clear leader
command is issued, no other ROC card
functions can be used for 1.2 seconds.
(
e.
f.
1200 Baud Print LOCAL - Not normally
installed, this option provides a decoded output
for use by the 1200-baud Transmit/Receive PC
card with Auto Answer Control to perform the
1200-baud print-local function. The 1200-baud
print local command is a standard
two-character decode, activated when the
command is received from the communication
line.
Printer On/Off Command with DC2 and DC4 The standard printer-ON/OFF commands are
normally two-character codes. If the ROC
incorporates this single-character option, the
printer-OFF command may be initiated by the
single ASCII DC2 (record-ON) character rather
than the double-character sequence of DLE and
o (zero). Similiarly, the printer-ON command
may be initiated by the single ASCII DC4
(record-OFF) character rather than the
double-character sequence of DLE and 9. With
'this option the standard double-character
printer ON/OFF commands are ignored by the
RDC. This option is normally not installed on
3-119
Character decoding from the serial data bus The RDC monitors the serial data bus at all
times and decodes those characters selected to
perform certain functions. Data from the serial
bus is clocked into an input register on each set
of eight system clocks (SCLK-). The last 2 bits
of the ASCII character (bit 6 and bit 7) are
then decoded to indicate that the character is
either in columns 1 and 2 (control characters)
of the ASCII code table (see Table 3-4.2) or in
columns 3 and 4 (printable characters) of the
ASCII code table. Bits 1 through 5 are then
decoded by a read-only memory to indicate the
character within the two columns selected.
The PROM is programmed to encode the input
character (5 bits) into two sets of output lines.
One set of three output lines indicates up to
seven single-level decodes, and one set of five
output lines indicates up to ,,16 double-level
decodes. The output lines are then decoded by
a three-line to eight-line single-character
decoder and a four-line to 16-line
double-character decoder into discrete lines
which repr~sent each function performed by
the RDC.
If the first character of a double-character
sequence (normally DLE) has not been
received, only the single-character decoder will
be enabled. When the double-character initiator
is received from the line with a serial receiver
enable (SRVENA-), a flipflop is set (ESCQ)
which enables the double-character decoder for
received line data (i.e., that data on the bus
during SRVENA-). It will stay enabled until the
next character is received from the line. During
this period the single-level decoder will still be
enabled on transmitted data (during
XMTENA-) and during local data transfer (on
LOCDAT-). Once the second character of the
double-character code is received from the line,
the ESCQ flipflop is reset, the double-character
decoder is disabled, and the single-character
decoder is then re-enabled to line data (on
SRVENA-). The ESCQ flipflop (when enabled)
also disables the printer when it is on-line via
the printer-remote-off (PRNROF-) line, so that
the second character of the double-character
sequence will not be printed.
All functions decoded which affect the ASR
upper unit (record, playback, cassette motion
control, or mode select) must be sent to the
upper unit via a 4-bit code and a strobe pulse.
When any line from either the single- or
double-character decoder is low at time QO
(TIMEQO), the indication is clocked into a
holding register until the next TIMEQO (88
Ilsec) at which time the' present indication
(REWIND CASSETTE-I, LOAD CASSETTE-2,
etc.) is removed and the next indication, if any
is clocked into the holding register (RDC timing
is shown in Figure 3-9.12).
While the indication is in the holding register,
the code bit encoder is putting the proper code
bits (CDBITl- through CDBIT4-) on the code
bit lines going to the ASR upper unit. As shown
in Table 3-9.13 the code bits are on the lines, a
5-llsec strobe (CDSTRB-) is issued at TIMEQ4,
and the appropriate action is taken in the ASR
upper unit. The strobe is a free-running clock
from the timing generator on the PC card. The
strobe bits are always issued for a function for
881lsec starting from TIMEQO at the end of the
enable on which the function was decoded until
the next TIMEQO.
The strobe is always issued at TIMEQ4 during
each 88 Ilsec period of the timer generator
(between TIMEQO times). The timer generator
times are synchronized to terminal control via
the terminal control state-ONE (TCSTl) signal
as shown in Figure 3-9.13. Therefore, all the
3-120
times (TIMEQO, TIMEQ6, etc.) always have the
same relationship to the enables issued by
terminal control.
The double-character functions can be decoded
only from received data (SR VENA-), but the
playback ON/OFF and record ON/OFF
functions (PCl through PC4) are optionally
selectable using switches (S2) on the RDC PC
card. This is done by enabling the
single-character decoder output lines for these
four functions into the holding register only if
the appropriate switch is closed. For example,
if the switch for enabling DCl and DC3 is
closed, both these inputs to the holding register
are enabled for all local data on the bus. Local
data is signified by the local data (DATLOC-)
signal from terminal control.
Similarly, transmitted data is signified by the
transmit enable (XMTENA-) signal and received
data by the serial receiver enable (SRVENA-)
signals from terminal control.
b.
Additional RDC card line and local functions The RDC performs several double-character or
single-character decodes which do not affect
the ASR upper unit and several optional
functions. As a reference to all resistor and
pencil switch options, see the RDC schematic
(971504 or 971499) in Appendix C.
(1)
Printer ON/OFF. When the printer-OFF
code is received from the line, a latch
(PRNOFQ) is set at TIMEQO which keeps
the printer OFF via the PRNROF-line as
long as the terminal is on-line. The latch
is reset upon receiving the printer-ON
code from the line or if the terminal is
taken off-line or the RDC PC card is
switched OFF. When the RDC card is off
via the toggle switch on the PC card, all
RDC functions are inhibited except
decoding of the ASCII EOT character
(used by Auto Answer Control to
disconnect a call). The printer-OFF latch
may be optionally resistor-strapped to be
set/reset upon. receiving from the line
(SRVENA-) the single-level decoder DC2
and DC4 output lines, respectively. If this
option is selected, the double-character
decoder lines are not used. See the RDC
c
~
~
a BITS
.
SERIAL
REMOTE LINE DATA
'"
LOCAL KEYBOARD D A T A /
.
TAPE READER DATA
SERIAL CLOCK
~,
l
....
SERIAL
INPUT
7 BITS
PARAL~
1
SEARCH
-'"
BUFFER
7 BITS
REGISTER
BLOCK DIAGRAM, BASIC AUTOMATIC
SEARCH CONTROL
(ASC)
PARALL~
FIELD
,/CONTROL LINES
RAM
REGISTER
,...-
/
7 BITS
PARALLEL
J
rENTERNA'L'
I
CONTROL
I
I
LINES
I
--r--
~
V
~
~
V
STOP
BIT
V
~
H--------II
II
I I
V
L,!
r----l
UJ
I
I-
5 X32
2
FUNCTION
CONTROL
I
DATA
TIMING
~
CONTROL
CASSETTE
CHARACTER
DATA
DECODER
RAM
...
:I
axe
~
t
._---
----i---FORCING FUNCTION
SELECT MULTIPLEXER
__ 1 __
I
I
EXTERNAL
STATUS
I
- -
I
- -
.)
....
...
...)
...J'o.
I
L"':I~:"_I
- -
-
- - -- -
~-
i
-
ROM
ADDRESS
REG
INPUT
SELECT
5 BITS
- - - -- -- -- .- - - - - -
-
.
.)
...
CONTROL
_.-
-
..-
I
LINES
r
I I
Y'
,....
,....
EXTERNAL
I I
7BITS PARAV
COMPARATOR
N
ROM
I
_____ J
STATE
CONTROL
ROM
l\
I
I
~1
5 X32
ROM
ADDRESS
5 BITS
REGISTER
~ MULTIPLEXER
5 BITS
LOGIC CONTROL
JO,J1,J2
15 BITS (3 ADDRESS FIELDSI
-------------------------------------------------------------------:
FIGURE 3-9.12. AUTOMATIC SEARCH CONTROL BLOCK DIAGRAM
The PRNOFF- bit is the eighth bit of the
terminal status word and is clocked into a
flipflop on the ROC PC card for use with
the printer-local (PRNLOC-) and printer
remote-off (PRNROF-) signals to provide
the printer-ready bit of the status
character sent to the line.
schematic (971499) for a list of ROC
card options and appropriate resistor
straps.
(2)
(3)
(4)
1200-baud print LOCAL. A
double-character decoder output line is
provided for the 1200-baud print local
option to use. This line is true only
between the falling edge of the eighth
system clock (SCLK-) for each SRVENAand the rising edge of the TIMEQO signal
(see the ROC timing diagram, Figure
3-9.13). The 1200-baud print-local option
is described in paragraph 3-9.8.4.e..
DCl-4 ON/OFF. Upon receipt of the
double-character decoder DC1-to-4 OFF
code, a latch is set at TIMEQO which
inhibits the DC1 through OC4 codes from
being acted upon when received from the
line. This is done by gating out the
S R VENA- signal going to the
DC1-to-DC4 enabling option logic and
switches, so that these functions cannot
be strobed into the holding registers on a
SRVENA- signal at timeQO. The latch
(DCl-4 OFFQ) is reset upon receipt of
the DCl-4 ON code from the line or by
switching the terminal off-line or by
switching off the ROC OFF toggle
switch.
Status Request. Upon receipt of the
status request code from the line, a status
flipflop (STATUSQ) clocks in the state of
the status (STAT-) output line from the
double-character decoder at TIMEQO. At
TIMEQ5 an auxiliary-l request
(AUX1REQ-) is sent to terminal control,
and at TIMEQ6 the status flipflop is
cleared. When terminal control sends
back an auxiliary-1-enable-to-send
(AUX1ENAS-), the status is clocked from
the status register on the RDC card to the
transmitter and sent to the line as a 7-bit
ASCII character. All bits of the status
character are obtained from information
on the KSR motherboard except the
printer-off (PRNOFF-) indication which
comes from the serial data bus during the
status enable (STATUSENA-) time from
terminal control.
3-122
The seventh bit of the status character
sent to the line is switch-selectable to be
always a ONE (forces status character not
to be a control character) or to indicate
the playback-not-on (PBKON-) status.
Examples of possible status indications
which could be sent by the RDC on
request, and the ASCII characters that
the status would represent, are shown in
Table 3-9.14.
(5)
ASCII CAN character on playback error.
The playback error status bit (RERROR)
is monitored from an available KSR
motherboard signal. When a playback
error occurs, the RERROR indication is
clocked into a register on the RDC PC
card at TIMEQO (see ROC timing, Figure
3-9.13) and becomes RERRORQ. The
RERRORQ signal going HIGH clocks a
cancel/status flipflop (if the playback is
on-line and ready and the OPTION switch
is closed) which selects which data will be
sent to the serial data bus on the next
auxiliary-1-enable-to-send (AUX1ENAS-)
signal from terminal control.
The data which goes to the data bus on
the AUX1ENAS- signal comes from
either the status register or the
cancel-character register as selected by
the flipflop. The playback error will be
detected in a status-enable time period,
and on the next TIMEQ5 time a request
(AUX1REQ-) will be sent to terminal
control to transmit the CAN character.
The cancel/status flipflop is reset during
the CANRSTENA period at TIMEQO as
shown in Figure3-9.13,and data sent after
that will come from the status register
until another playback error is detected.
The CAN character option is inhibited by
either opening the pencil switch (S2-7)
TABLE 3-9.14. REMOTE DEVICE CONTROL STATUS CODES AND CHARACTERS
Status Code
Status Parity
Character
b
8
High
Printer Recorder Clear
Clear
Playback Playback
(ONE)
Ready
Ready
Leader
Leader
Error
Ready
or
(ONE)
(ONE) Cassette- Cassette- (ONE)
(ONE)
Playback
OFF
b
P
b
6
b
o
o
o
[)
P
P
P
E
P
G
H
P
P
P
P
o
o
o
P
P
P
o
A
C
K
L
P
Q
s
::;:-SOH:}
P
P
P
P
:::ETX<::::
p
T
X
II~~~-
::;::-iii'=;::::
::::- VT-:----
{OCr}
}6C3}
.:.: .............. :.:.
P
P
P
P
P
P
Status Code
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
b
3
o
o
o
o
o
o
o
o
o
b
o
o
o
I
o
o
o
d
I
I
o
o
o
o
o
I
o
1
o
g
h
o
o
o
I
b
b
b
I
o
o
o
o
o
o
o
P
o
o
o
o
o
o
o
o
o
P
P
P
P
P
P
p
o
o
I
I
I
1
o
o
o
o
o
p-
o
1
P
1
P
o
P
P
P
P
+
3-123
o
o
o
o
o
o
I
o
1
o
o
o
o
o
o
o
1
o
o
o
o
o
o
o
o
1
o
o
o
I
1
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
1
1
o
1
o
o
o
o
1
o
o
o
o
o
1
o
I
o
o
o
I
*Bit 7 is normally held in the logic ONE state. If the playback-OFF indication option is used (S2-6 in ON position),
a logic ONE indicates the playback function is OFF and a logic ZERO indicates the playback function is ON. When
the playback-OFF option is used, some status characters may be control characters as indicated by the shaded characters in the table.
(
b
I
P
P
P
P
P
P
b
1
o
o
P
b
3
o
o
P
o
I
P
o
o
o
o
High
Printer Recorder
Clear
Cbr
PI •• yback Playback
Leader
Lt.:'adcr· Elror
Ready
lONE)
Ready
Ready
(ONE)
,ONE) Cassette- Cassette- (ONE)
(ONE)
or
Playback
OFF
4
I
o
Parity
b
o
o
o
o
b
o
o
o
o
o
~
o
o
o
o
o
o
o
o
o
o
o
o
o
o
b
Statu="
~haractt.:r
o
o
o
T
~
1/0.2048
Msec
~
I
~
I
T
4.9 Msec
I
14I
RDRCLK
TCSTl
r-
1
r
(XXX)ENA-
u- - U-U
SCLK-
TIM§.QQ
TIME01
'U-
--u
u-u
Jl
~LJ
11____
II
rl_ _
lJ>
,!...
IV
.j>.
TIME02
TIME03
TIME04 (STROBE)
TlM~
TIME06
TIM§.QZ
r-,
~
I
II
II~--------------------------
II~-----------------------11-----------------------rt________________________
FIGURE 3-9.13. REMOTE DEVICE CONTROL TIMING DIAGRAM
/.)."
,
.
.'
"')
\
i
I~
J
~
(1200 baud) 1 is kept low so that the
transmitter does not detect the transmit
enables. Since no transmit enable is
detected by the transmitter, it does not
hold the line busy (LINBUSY-);
therefore, the playback can send data at
maximum search speed (320 characters
per second). When the PLAYBACK is set
to LINE and is ready and the RDC card is
ON, the remote enable (RMTENA-) line
to the ASC PC card is active. If the ASC
initiate code is received from the line via
a SRVENA- signal, the code is passed on
to the ASC PC card through the
RMTENA- line. Also, if PLAYBACK is
set to LINE and is ready and the RDC PC
card is ON, the double-character ASC
cancel code, when received from the line,
will cause an 88-J,Lsec (TIMEQO to
TIMEQO) cancel signal to be sent to the
ASC PC card via the remote cancel line
(RMTCAN-) between the cards.
for that option or by switching off the
RDC PC card toggle switch.
(
(6)
Footswitch option. A footswitch contact
closure to ground is provided as an input
to the RDC. The playback-ON (DC1)
function can be initiated by footswitch if
the PLAYBACK switch is set to LOCAL,
and the cassette is loaded and ready. The
footswitch provides a contact closure to
ground with a switch bounce of 1 msec or
less. (The TTL signal input is a low-going
pulse, the width of which exceeds 1.25
rnsec).
The footswitch input is debounced by the
C800 clock (1.25 msec period). When the
footswitch is depressed, the deb ounce
flipflop clocks the footswitch flipflop if
the PLAYBACK is not set to LINE and
the RDC card is ON. On the next status
enable period at TIMEQO, the
playback-ON (DC1) function is clocked
into the holding register and encoded to
the 4 cassette data bits. When the DC1
function is issued (DC1Q), the footswitch
flipflop is cleared until the next
footswitch actuation. The footswitch
input (FOOTSWITCH-) to the RDC is
resistor-strappable to pin 28 02;L), or it
may be hard-wire-strapped to any other
RDC PC card output pin.
(7)
Local/Remote Search Option (with
optional Automatic Search Control).
When the optional Automatic Search
Control (ASC) is searching tape, the
ASCSRCH- line is low. If the
PLAYBACK switch is set to LOCAL, the
SRCHLOC signal locks out the local data
enable (DATLOC-) so that the RDC does
not detect the DC1 through DC4
functions while the search is in progress.
If the PLAYBACK switch is set to LINE,
the SRCHLN signal locks out the
transmit enable (XMTENA-) to the RDC
so that it will not act on the DC3
function. As long as there IS no
auxiliary-1 enable to send (AUX1ENS-),
such as a status request or CAN character
transmission, the transmit inhibit line
[XMTINH, Pin 31 (300 baud), Pin 33
3-125
(8)
Rewind From the Right End Option. The
logic in the ASR upper unit tape motion
controller is designed so that rewinding a
tape from clear leader requires depressing
and holding the REWIND switch for that
cassette until the tape winds past clear
leader and onto magnetic tape, The RDC
PC card must simulate holding the
REWIND switch depressed by holding the
strobe line (CDSTRB-) low and keeping
the rewind code on the cassette data lines
until the tape has passed clear leader.
When the RDC logic senses that either
cassette is on clear leader and a rewind
command for that cassette is issued from
the line, a oneshot timer is fired which
holds the strobe low and disables the
timing generator (TIMEQO generator) for
1 ±0.2 seconds. By disabling the timing
generator the rewind code just issued will
remain in the holding register until the
timIng generator can again send a
TIMEQO clock to remove it. The 1
second during which the strobe is held
low is sufficient to ensure that the tape
has passed clear leader on the right end.
If the tape is already rewound to clear
leader on the left end, another rewind
command will have no effect on the tape
but will still cause the 1-second disable
oneshot to fire. Whenever the oneshot
fires, the timing generator is disabled for
1 ±0.2 seconds. Since no timing is being
generated, this action will cause the RDC
to be disabled for that period of time;
therefore, it cannot be used for any other
function. Rewinding a tape which is not
on clear leader does not cause the
oneshot timer disable to fire; thus the
RDC card is not disabled.
3-9.9 ACOUSTIC COUPLER. The Model 733 ASR, KSR,
or RO Electronic Data Terminal may be equipped with an
optional Acoustic Coupler which is compatible with a Bell
103A data set or equivalent. The coupler operates
asynchronously up to a maximum speed of 303 baud in the
full or half-duplex mode using standard dial telephone
facilities. The Acoustic Coupler option is an originate-mode
unit using transmit frequencies of 1270 Hz for MARK and
1070 Hz for SPACE and receive frequencies of 2225 Hz for
MARK and 2025 Hz for SPACE.
The interface to the Acoustic Coupler is completed using a
standard telephone handset. After the receive carrier
3-126
frequency is present at the receiver for 150 ±50 msec,
Model 733 Data Terminal is enabled to receive data, '
the transmit carrier frequency is enabled.
The Acoustic Coupler contains all circuitry needed
convert logic signals froin the terminal to audio signals
transmission over telephone lines. These circuits a
convert audio signals to logic signals for transmission
terminal control circuits in the terminal. In addition, t
Acoustic Coupler circuits supply carrier detect signals
the terminal control circuits to signify when the receh
data carrier has been received. The coupler provides j
timing required for communication with two data set~
the other end of the line. The Acoustic Coupler is desigr!
to provide reliable operation over the full range of receh
signals, even under high noise and low signal Ie
conditions. Operation equals or exceeds the performance
the 103-type data sets in half duplex (110 baud) mode.
All circuitry is located on a single PC card which is eas
removed for repair or replacement. Adjustment is r
required, and all critical factory adjustments are sealed
prevent maladjustment.
SECTION IV
BASIC EQUIPMENT PC CARDS AND FUNCTIONS
4-1 GENERAL.
from single-line feed to double-line feed. The timing for the
print pulse and the printer-busy signal is also generated on
this PC card.
The following standard-equipment PC cards are installed in
the ASR and KSR models as shown in Figures 4-1 and 4-2.
Schematics for the PC cards are contained in Appendix C.
4-2.6 TERMINAL CONTROL. The Terminal Control PC
card checks the status of all devices (line/local/off), accepts
requests, and sets priorities. It uses the status and priorities
to determine which devices receive enable signals. Terminal
control generates these enables plus the eight clocks used to
clock data to and from the data bus. Terminal control also
generates the local-busy signal.
4-2 KSR (KEYBOARD) UNIT.
4-2.1 POWER MODULE MOTHERBOARD. The KSR
motherboard provides interconnections between aU other
PC cards in the KSR section. Mounted on the motherboard
are the power supply filter capacitors, the 5-volt crowbar
SCR, and bleeder resistors for the Hlter capacitors. The
keyboard, printer drive assembly, bell, power module,
cassette system and output connectors plug into the power
module motherboard.
4-2.2 REGULATOR/AMPLIFIER PC CARD. This PC card
contains the motor drivers for the head-stepping and paper
advance motors and the head-lift solenoid driver. This PC
card also contains the 5-volt switching regulator.
4-2.3 CONTROL REGULATOR PC CARD. This PC card
contains the power-on reset circuit and the positive 12-volt
and negative 12-volt regulators. It also contains the
auxiliary/reference 5-volt supply, the 5-volt regulator
oscillator, the 5-volt regulator driver, and the 5-volt,
crowbar.
4-2.4 PRINTER CODE PC CARD (ASCII AND BAUDOT).
This PC card contains the keyboard interface which
converts parallel data from the keyboard to serial data for
the data bus. It also contains the character generator which
converts 8-bit data from the data bus to 35 bits for the
printhead. The Printer Code PC card also decodes printer
control characters. The printhead compensation and driver
circuits are on this PC card along with the contrast
adjustment and overvoltage protection for the printhead.
The driver circuit for the bell is also on this PC card.
4-2.7 TRANSMIT/RECEIVE (ASCII OR BAUDOT CODE).
The Transmitter/Receiver PC card contains the EIA
interface circuits and the line receiver and transmitter. The
ASCII receiver circuits receive data from the line at 10, 15,
and 30 characters per second (CPS) or 50, 75, and 100
Baud for Baudot receivers, and clocks this data to the data
bus with an enable and eight clocks from terminal control.
The transmitter circuits on this PC card accept data from
the data bus using an enable and eight clocks, add parity
and START and STOP bits, and then clock this data to the
line interface at the appropriate line speed. The SPEED
switch (La, MED, HIGH) is located on this card along with
the FULL/HALF DUPLEX switch and the break circuit.
The line-busy signal is generated on this card. This PC card
also contains the crystal oscillator and countdown circuits
which generate all master clocks used in the data terminal
in addition to the receiver/transmitter clocks.
4-2.8 PRINTHEAD INTERFACE. The Printhead Interface
PC card plugs into the Printer Code PC card and the
printhead plugs into this card. It consists of a 35-bit
serial-to-parallel converter and 35 buffers. The card accepts
serial data from the character generator and converts it to
parallel data and buffers for the printhead.
4-3 ASR MODULE (l!PPER UNIT).
4-2.5 PRINTER CONTROL. The Printer Control PC card
has the circuitry to step and damp the head, backspace the
head, and lift the head. It includes a column counter and
decoders to decode column 80, column 72 (end-of-line
bell), and column 12 (carriage return brake). This PC card
also contains the carriage return and carriage return brake
circuits. Signals for line feed and paper advance are
generated on this board. A switch is provided to change
4-3.1 ASR MODULE MOTHERBOARD. The ASR
motherboard connects all PC cards in the ASR unit with
each other and with the tape transports. The motherboard
is connected to the KSR motherboard through a
36-conductor cable.
4-3.2 DISPLAY PC CARD. The Display PC card contains
the switches and indicators to operate the ASR. There are
4-1
ASR MOTHERBOARD
XA-9
TAPE TRANSPORT 1
XA-7
RECORD CONTROL
XA-8
TAPE TRANSPORT 2
XA-6 . TAPEREADIWRITE
XA-5
RECORD BUFFER CONTROL
XA-4
PLAYBACK CONTROL
XA-3 REMOTE CASSETTE CONTROL
XA-2
XAI
MOTION CONTROL
DISPLAY
ASK MODULE ASSEMBLY (UPPER) PC CARD LOCATIONS
LINE INTERFACE
*
*
TRANSMITTER/RECEIVE R
TERMINAL CONTRO"
*
PRINTER CONTRO L
PRINTER COD E
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A-6
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A-I
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PRINTHEAD
INTERFACE
(XAlI
AC POWER ASSEMBLY
_ _ -,
A-6
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A-4
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A-3
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A-2A-
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A-7
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CONTROL REGULATOR
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~---------~---T-----l I
~---~--------------~ IL ______ II
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KEYBOARD
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~---iT-------------rr~~
l_Jt---- ---j[-J
C&O~
t
1__ ....:.. ___ - - - - - - - - - __.___1
'RESERVED FOR OPTIONAL DEVICES
KSR PC CARD LOCATIONS
FIGURE 4-1. PC CARD LOCATIONS
4-2
REGULATOR/AMPLIFIER
POWER MODULE
MOTHERBOARD
(
(
8.
four 3-position switches to place the keyboard, printer,
playback, a'1d recorder on LINE, OFF, or LOCAL. Each
transport has two switches: one for REWIND and one for
LOAD and FF (fast forward). There is also a mode
selection switch to place the transports in RECORD or
PLAYBACK. The Playback Control has three momentary
switches with debounce circuits for continuous
START/STOP, BLOCK FORWARD/REVERSE, and
CHARACTER FORWARD. The Record Control has one
momentary switch for ON/OFF, one momentary switch
with deb ounce circuits for PRINT buffer/ERASE and one
two-position switch for CONT/LINE format. The display
card also has LED'S and drivers to indicate the following
conditions for each cassette: indicators for mode
(PLAYBACK/RECORD), READY, and END of tape. The
Playback control has indicators for playback ON and
playback ERROR. The Record Control has an 8-bit
character display and a record-ON indicator.
9.
10.
11.
12.
13.
14.
15.
4-3.5 PLAYBACK CONTROL. The Playback Control PC
card contains the playback control (continuous, block
forward, and character forward) and tape read controller
circuits. The playback 'buffers with their address counters
are also on this board in addition to the character counter
which is used for playback control and the tape read
control and stop-on-read-error circuits.
4-3.6 RECORD BUFFER CONTROL. This PC card
contains the 1024-bit record buffer with the punch address
counter, tape write address counter, and the address select
gates. The punch address register, which is used in the edit
function, is on this PC card along with the memory timing
circuits and the reference clocks (TRFCLKA and
TRFCLKB) for the transports. Also on this card are the
serial-to-parallel-to-serial registers which accept data from
the line, decode and add the carriage return and
end-of-block bit, and convert back to serial for the
memory. The character display register also is located on
this PC card.
4-3.3 MOTION CONTROL. The Motion Control PC card
accepts inputs from the switch~s on the Display PC card
and from the transport sensors (EOT, BOT, cassette in
place, door closed, write tab, etc.) and generates signals to
indicate record READY, Playback READY, recorder
on-LINE, and playback on-LINE. This card also generates
forward, reverse, and fast .signals for the transports and the
load signal for the gap counter. Circuits which identify and
remember which end of the tape is which are also on this
PC card.
4-3.7 TAPE READ/WRITE. The Tape Read/Write PC card
contains the tape read circuit which converts phase-encoded
(PE) data from the transport into binary data and the tape
write circUit which converts binary data from the write data
register into PE data to go to the transport. It also contains
the tape write controller which formats the data as follows:
preamble, 86 data characters or nulls, two block check
characters (nulls), and a postamble. The block character
counter and the block counter are also located on this card.
4-3.4 REMOTE CASSETTE CONTROL. This PC card has
the gap counters and mode control for both cassettes. The
block reverse function of playback control is located on
this PC card. The playback timers (TR3/4T, TR5/4T, and
TR21/4T) are located on this PC card along with the
tape-erase circuits. This card also contains the decoding for
remote control of the cassettes. Four code bits and a strobe
are decoded into the following 15 different functions:
1.
2.
3.
4.
5.
6.
7.
Load/fast forward cassette-2
Block forward
Block reverse
Character forward
Cassette-1 record
Cassette-2 record
Cassette-1 stop
Cassette-2 stop
Playback on
Playback off
Record on
Record off
Rewind cassette-1
Rewind cassette-2
Load/fast forward cassette-1
4-3.8 RECORD CONTROL. The Record Control PC card
contains the flipflops to synchronize the signals from the
record switches (PRINT, ERASE, record ON, and manual
STOP) and the state counters for the recorder. The punch
character counter and character backspace counter with
decoding for count = 0 and count = 86 are included on this
card along with the punch counter buffer register.
4-3
SECTION V
('
MAINTENANCE
5-1 PREVENTIVE MAINTENANCE.
Model 732/733 ASR/KSR data terminals are designed and
built to provide long term trouble-free operation under
rigorous operating conditions. To ensure that the highest
performance levels are maintained, the following preventive
maintenance procedures should be performed at regular
intervals. These consist primarily of keeping the thermal
printer mechanism and cassette transports clean and free of
foreign objects.
5-1.1 PRINTHEAD CLEANING. To ensure that the
thermal printer continues to provide acceptable print
quality, the printhead periodically should be cleaned as
follows:
c.
Move the printhead to the far right side of the
mechanism.
d.
Wipe the left half of the paper drive roller with
a soft rag or paper towel moistened with
denatured alcohol. Rotate the drive roller
manually to ensure that the entire roller is
cleaned.
e.
Slide the printhead to the far left and clean the
right half of the drive roller.
f.
Load the paper roll back around the drive
roller, lower the window, and switch on power.
a.
Raise the terminal cover and raise the window
and roller.
This procedure should be repeated every 3 months or
whenever line spacing becomes uneven or too close.
b.
Insert a sheet of good quality bond paper
between the printhead and the thermal paper.
The bond paper should extend 3/4 inch below
the top of the printhead.
c.
Lower the window and print five lines on the
bond paper.
5-1.3PRINTHEAD DRIVE MECHANISM CLEANING. To
ensure continued smooth, quiet operation of the printer
mechanism, the printhead carriage rod and head lift bar
must be kept clean. A dirty carriage can cause increased
audible noise and can reduce the lifetime of the printer
mechanism. Clean the carriage rod and head lift bar as
follows.
a.
Switch off power to the terminal and remove
the roll of paper.
b.
Clean the printhead carriage rod and head lift
bar with a soft rag to remove paper residue
(see Figure 5-1.1).
The printhead should be cleaned each time a new roll of
paper is loaded into the printer or more often if the printed
images start to fade as a result of residue buildup on the
pririthead.
c.
Carefully apply light grade machine oil (lOW)
on the carriage rod and light grade
multipurpose grease (Shell Darina) on the top
and bottom edges of the head lift bar.
5-1.2 PAPER DRIVE ROLLER CLEANING. To maintain
uniform line spacing the paper drive roller must be kept
clean. Use the following procedure.
d.
Manually run the carriage back and forth
several times.
e.
Reload the paper and switch on power.
NOTE
The thermal printer will not print visibly
on the bond paper.
d.
Remove the bond paper.
a.
Switch off power to the data terminal.
b.
Remove paper from around the drive roller.
Leave the window up.
This cleaning procedure should be performed every 3
months or whenever the carriage rod and head lift bar
appear dirty.
5-1
R15
POTENTIOMETER R 57
PRINTHEAD
CARR!AGE
FIGURE 5-1.1. PRINTHEAD DRIVE MECHANISM CLEANING
5-2
(
without checking contrast by printing
a character. Contrast settings which
cause scorching or sticking of the
paper can result in permanent damage
to the printhead.
5-1.4 CASSETTE TRANSPORT CLEANING. Carefully
follow the tape manufacturers' recommendations for
proper handling and storage of magnetic tape used with the
ASR. In addition, clean the tape read/write heads, capstans,
and pinch rollers at regular intervals. To enhance cassette
system data reliability (minimize data error rate), these
cleaning procedures should be completed once each day, or
after 8 hours' operation. The read/write heads, capstans,
and pinch rollers can be easily cleaned using the following
procedure.
a.
Remove the tape cassettes from the transports.
b.
Use a clean cotton swab (or lint-free cloth)
dampened with denatured alcohol to clean the
heads, the forward and reverse capstans, and
the associated pinch rollers (see Figure 5-1.2).
2) If a new printhead is installed, turn
the adjustment screw fully
counterclockwise before reapplying
system power. Then slowly turn the
screw clockwise while typing until the
desired contrast is obtained.
5-3.2 MODEM LEVEL ADJUSTMENT. Terminals which
incorporate the optional internal data set '(modem) must
have the modem output adjusted when the terminal i~
installed. The adjustment also should be rechecked
periodically.
5-2 TROUBLESHOOTING.
(
Troubleshooting the data terminal is facilitated by use of
Tables 5-1 and 5-2, which will aid in localizing a failure to a
particular card or assembly. Table 5-1 lists failures common
to all data terminal models, and Table 5-2 lists· failures
which may occur only in the ASR models. Where more
than one possible cause is listed for a particular problem,
the PC card or subassembly is listed in descending order of
probable cause. The omission of any PC card or
subassembly as a cause fora specific problem does not
eliminate that area, but the possibility of a failure is
considered remote on the basis of experience.
5-3.2.1 Switched Telephone Network. Connection to the
switched telephone network ordinarily is made by means of
a data coupler, a Bell Direct Access Arrangement, or similar
device provided by the local telephone company. The
telephone company dictates the maximum permissible
power level of the combined received and transmitted data
signals present at the terminals of the coupling device. This
level is usually expressed in dBm (0 dBm = 1 milliwatt
dissipated in a 600-ohm load) and is stamped on the face of
the coupler.
a.
With power off connect the terminal to the
data coupler by means of the data set cable. If
the data coupler is not equipped with a power
level meter, connect an ac vacuum tube
voltmeter to the coupler terminals.
b.
Call another operating terminal within the
system and arrange to receive a data or steady
MARK signal. While receiving this signal
observe the VTVM; the indication should be
several dBm below the allowable limit stamped
on the coupler.
c.
Apply power to the terminal and again observe
the meter reading. Adjust potentiometer R18
on the Modem PC card (slot A-8) until the
meter reading is 1.5 dBm below the allowable
maximum.
5-3 ADJUSTMENTS.
The 732/733 ASR/KSR data terminals have only two field
adjustments in normal use: the print contrast control and
the modem level control (only in units equipped with the
optional internal data set). All other adjustments are
completed at the factory and should not be changed unless
replacement of a component or subassembly makes
readjustment necessary.
5-3.1 PRINT CONTRAST. To adjust print image contrast
raise the hinged terminal cover and locate Printer Code PC
card potentiometer R36. This potentiometer is accessible
through a clearance hole in the Power Module card cage
cover. To darken the images slowly turn the adjustment
screw clockwise while typing characters from the keyboard
until the desired contrast is achieved. To lighten the print
image turn the adjustment screw counterclockwise.
I~
1) DO NOT turn the adjustment screw
more than one-quarter turn clockwise
The adjustment screws of all modem
5-3
TABLE 5-1. FAILURE ANALYSIS CHART, ASR AND KSR MODELS
3 V) to answer an incoming call; goes low
« -3 V) to disconnect a call
master terminal-reset upon power-on or power tailure
from RDC card; signifies EOT characters received from the
line
204.8 kHz
signals incoming call for BeU103 Data Set or CBS DAA
line to option display panel lamp: follows incoming ring
indicator (RI) until call is answered; remains on after call is
answered until line is ready for communication
wait state, no call in progress
call answered and data-set-ready indication received; wait for
carrier-detect indication and then trigger ABM
carrier-detect indication received, wait for ABM-delay time
ABM delay time completed, bring down the line-busy
indication (send ABM data) and wait for a disconnect
condition (carrier loss, long space, receive EOT)
1O.24-second delay from timer, used for wrong number
disconnect
1.28-second delay from timer, used for long space disconnect
r"',
,!11
!
L---------------------------------------------------------------~,"~J
A-12
SLOT A-7 OR A-8 AUTO ANSWER CONTROL (CONCLUDED)
(~
.
-_./
".
Signature
I
I
Definition
ID80MS
TERLINE-
time delay 80 milliseconds
terminal on-line
TERMRDY-
terminal ready
TIMERRST
TTLDCD
timer reset
TTL data-carrier detect
TTLDSR
TTLDTR
TTL data-set ready
TTL data terminal ready
TTLRNG
TTL ring
Function
80-msec delay from timer, used for long space disconnect
from terminal ON-LINE switch, line is low when terminal is
on-line
line to option display panel lamp; illuminates when terminal is
on-line and thus ready to answer a call
reset delay timer
TTL-level data carrier detect indication; synched with
RDRCLK
TTL-level data set ready indication; synched with RDRCLK
TTL-level data terminal ready output; governs
connect/disconnect of DAA or 103 systems communication
lines
TTL-level ring indicator; synched with RDRCLK
SWT A-8. TTY LINE INTERFACE
Signature
I
Definition
EIACfS
EIADCD
EIADSR
TTYDATIN
TTYDATOT
TTYLl
TTYL2
EIA clear to send
EIA data carrier detect
EIA data set ready
Teletype interface data in
Teletype interface data out
Teletype interface line 1
Teletyl:?e interface line 2
TTYL3
TTYL4
Teletype interface line 3
Teletype interface line 4
I
Function
tied to + 5 volts
tied to + 5 volts
tied to + 5 volts
TTL data from Teletype interface to serial receiver
TTL data from serial transmitter to TTY output circuit
receiver line for neutral or polar
receiver common for neutral
receiver and transmit common for polar
transmitter line for neutral or polar
transmitter line for neutral or polar
SLOT A-8. MODEM LINE INTERFACE
Signature
I
Definition
EIACTS
EIADATIN
EIADATOT
EIADCD
EIA clear to send
EIA data in
EIA data out
EIA data carrier detect
EIADSR
MODLI
MODL2
EIA data set ready
modem line 1
modem line 2
I
Function
tied to + 12 volts by modem
EIA (±12 V) data sent from modem to serial receiver
EIA (±12 V) data sent from serial transmitter to modem
goes high (+12 V) 150 msec after modem senses in-band
signal; goes low (-12 V) 100 msec after modem loses
in-band signal
tied to + 12 volts by modem
communication line
communication line
A-13
SLOT A-9. CONTROL REGULATOR
Signature
I
NEG12V
NEG18V
POS18V
POS5VCROWBAR
POS5VOL
POS5VREF/AUX
Definition
I
negative 12 volts
negative 18 volts
positive 18 volts
5 volt crowbar
5-volt overload
positive 5 volts reference/auxiliary
POS5VREGDR
POS5VREGNA
POS5VSENSE
POS12V
POS33V
POS33VUNFIL
PWRCLK
PWRRST-
5-volt regulator drive
5-volt regulator enable
positive 5-volt sense
_positive 12 volts
positive 33 volts
positive 33 volts unfiltered
power clock
power reset
Function
-12 volt supply
-18 Vdc from ac power assembly
+18 Vdc from ac power assembly
shuts down regulator if + 5 voltage is too high
current limit for 5 volts
reference/auxiliary + 5 voltage supply to power
+ 5 volt regulator
switches on + 5 volt regulator
shuts down + 5 volt regulatar if clocks are lost
tied to + 5 volt supply
+ 12 volt supply
33 vdc from ac power assembly
33 volts rectified but unfiltered fram ac power assembly
51.2 kHz reference clock from transmit/receive
goes low for approx. 600 msec when power is first applied
SLOT A-IO. REGULATOR/AMPLIFIER
Signature
HDSOLDR
HDSOLDRET
HMRET
HPC
HPHA
HPHB
HPHC
HPHSA
HPHSB
HPHSC
L1FTHEAD
PACA
PMRET
POS5V
POS5VOVL
POS5VREF/AUX
POS5VREGDR
PPHA
PPHB
PPHC
PPHSA
PPHSB
PPHSC
PWRRST
I
Definition
head solenoid drive
head solenoid return
head motor return
head power control
head phase A
head phase B
head phase C
head phase select A
head phase select B
head phase select C
lift head
paper advance control
paper motor return
positive 5 volts
5-volt overload
5-volt reference/auxiliary
5-volt regulator drive
paper phase A
paper phase b
paper phase C
paper phase select A
paper phase select B
paper phase select C
power reset
Function
drive for head lift solenoid
return path from head solenoid
return path for head-stepping current
controls current to head-stepping motor
drive to ifJ A of head-stepping motor
drive to cp B of head-stepping motor
drive to cp C of head-stepping motor
printer control signal, selects phase A of head-stepping motor
printer control signal, selects phase B of head-stepping motor
printer control signal, selects phase C of head-stepping motor
printer control command to energize head lift solenoid
controls current to paper stepping motor
return path for paper stepping current
5-volt supply
limits curren t
auxiliary 5-volt supply from control/regulator
control regulator signal, switches on regulator
drive to cp A of paper-stepping motor
drive to cp B of paper-stepping motor
drive to cp C of paper-stepping motor
printer control signal, selects cp A of paper-stepping motor
printer control signal, selects cp B of paper-stepping motor
printer control signal, selects cp C of paper-stepping motor
goes low for approx. 600 msec after power is applied
A-14
SLOT XAI. PRINTHEAD INTERFACE.
This PC card is located on the left side of the terminal between the keyboard and the KSR card rack. The Printhead Interface
PC card interconnects the Printer Code PC card (slot A-I) and the printhead. Don't confuse this XAl number with the ASR
(upper unit) XAl Display PCcard.
SLOT XA1. PRINTHEAD INTERFACE
Signature
DGRND
DVOLT
ELM8
HDRSl
HDRS2
PHBFRCLRPHCHR
PHCLK
PVOLT
I
Definition
diode ground
diode voltage
element 8
head resistor select-l
head resistor select-2
printhead buffer clear
printhead character
printhead clock
print voltage
I
Function
return path for diode current
temperature-compensating diode voltage
base drive to printhead element 8
slow resistor voltage
fast resistor voltage
removes base drive to all printheadelements
data clocked into head buffer
clocks data into head buffer
supply voltage to printhead
(
A-IS
ASR (UPPER UNIT) PC CARDS
SLOT XA-I. I)ISPLAY
Signature
r
BOE0CA2
CA2RDY
CNFMT
CIRCD
DATADCHBIT8
Defmition
beginning and end of cassette-2
cassette-2 ready
continuous format
cassette-l record
data
display character bit 8
indicates when tape is on clear leader
indicates cassette-2 is ready to send or receive data
places recorder in continuous format
indicates cassette-l is in record mode
serial data bus
signal to LED display for bit 8 of
last character in record buffer
indicates keyboard is in local mode
indicates keyboard is not in off mode
indicates recorder is not in overpunch mode
indicates recorder on and ready to receive data
indicates printer in local mode
indicates printer in off mode
indicates when record buffer full and cannot accept more data
signal from switch which turns on recorder
signal from switch which turns off recorder
stops playback operation
starts continuous playback operation
indicates data dropout on tape
indicates playback is on
clocks out status information to bus
enables status register to send status information to data bus
indicates when terminal is on line
signal from switch to initiate block reverse
signal from switch to clear record buffer or erase tape
signal from switch to initiate block forward
signal from switch putting cassette-2 in record mode
command from switch to load or fast forward cassette-2
switch signal to put playback on line
switch signal to turn playback off
signal from switch to print out contents of record buffer
signal from switch placing recorder on line
signal from switch placing recorder in off mode
signal from switch to read 1 character
command from switch to rewind cassette-2
command from switch to stop rewind, load, or fast forward
cassette-2
keyboard local
keyboard on
punch on Q
punch ready
printer local
printer off
record buffer full
recorder on
recorder stopreader off
reader on
reader error
reader feed
serial clock
. status enable
terminal on-line
switch block space reverse
switch erase
switch block space forward
switch cassette-2 record
switch load/fast forward 2
switch playback line
switch playback off
switch print buffer
switch recorder line
switch recorder off
switch read character forward
switch rewind 2
switch stop cassette 2
KBDLOCKBooN
PNHONQ
PNHRDY
PRNLOCPRNOFF
RCBFFLRCDON
RCDSTP
RDROFRDRONRERROR
RFEED
SCLKSTAENA
TERLlNEXBSPRV
XERASE
XBSPFW
XC2RCD
XLD/FW2
XPBKLN
XPBKOF
XPRNBOF
XRCDLN
XRCDOF
XRCHFW
XREW2
XSTPCA2
Function
J
SLOT XA-2 TAPE MOTION CONTROL
Signature
I
Definition
BOEOCAI
BOTl
BOT and EOT on cassette-l
beginning-of-tape 1
CAIRDY
ClBUSY
cassette-l ready
cassette-l busy
I
Function
clear leader on transport-l
goes high when BOT sensor does not sense mag tape on
transport-l
indicates cassette-l loaded and ready
indicates cassette-l busy
A-16
SLOT XA-2 TAPE MOTION CONTROL (CONCLUDED)
(
CICNTLDA
CICNTDN
cassette-l count load
cassette-l countdown
CICNTQ
CIFWQ
ClINPLACE
CIRCD
CIRWQ
EOTl
cassette-l count Q
cassette-l fast forward Q
cassette-l in place
cassette-l record
cassette-l rewind Q
end-of-tape 1
EOTlQ
GAPIQ
LDBOTIQ
l..OADlQ
PNHRDY
PWRRSTRDLINE
RDRRDY
READCK
RECLINE
TERLINETPRQO
TPWFW
TIFAST
TlFWD
TILEQ
TlREQ
TIREV
TIWRITE
WRTTABI
XLD/FWI
XPBKLN
XPBKOF
XRCDLN
XRCDOF
XREWI
XSTPCAI
end of tape 1 Q
gap lQ
load BOT 1 Q
load 1 Q
punch ready
power reset
reader line
reader ready
read clock
recorder line
terminal on-line
tape read Q zero
tape write forward
transport-l fast
transport-l forward
.transport-l left end Q
transport-l righ tend Q
transport-l reverse
transport-l write
write tab 1
switch load/fast forward 1
switch playback line
switch playback off
switch recorder line
switch recorder off
switch rewind 1
switch stop cassette 1
load signal to cassette-l gap counter
tells gap counter to count up for
forward or down for reverse
indicates gap complete
set high when LOAD switch depressed while not on clear leader
indicates cassette-l in place and door dosed
indicates cassette-l in record mode
set when REWIND switch is depressed
goes high when EDT sensor does not sense mag tape on
transport-l
syncronized EDT signal
set high after LDBOTIQ set and BOT sensed
set high after LOADIQ and mag tape is reached
set high when LOAD switch depressed while not on clear leader
indicates recorder loaded and ready
goes low for approx. 600 msec after power is applied
indicates playback is on line and ready
indicates playback loaded and ready
204.8 kHz square wave
indicates recorder is on line and ready
terminal is on line
command to move tape forward in READ mode
command to put tape in write or forward mode
command to put transport-l in fast mode
signal puts transport-l in FORWARD mode
set when tape is on left end
set when tape is on right end
signal puts transport-l in REVERSE mode
signal sent to transport-l enabling write head
indicates presence of write enable TAB on transport-l
switch command to load or fast forward cassette-l
signal from switch to put playback on line
signal from switch putting playback in OFF mode
signal from switch to put recorder on line
signal from switch putting recorder in OFF mode
switch command to rewind cassette-l
switch command to stop rewind, load, or
fast forward cassette-l
SLOT XA-3. REMOTE CASSETTE CONTROL
Signature
BBKSPQ
BFWSPQ
BLCNDN
BREVQl
BREVQ2
BREVQ3
CDBITl
CDSTB
I
Definition
block backspace
block forward space
block countdown
block reverse state 1
block reverse state 2
block reverse state 3
code bit 1
code strobe
I
Function
initiates a block reverse
initiates a block forward
load gap counter for record transport to write a gap
block reverse in progress
data block detected
gap detected
1 of 4 parallel control bits
strobe for 4 parallel control bits
A-17
SLOT XA-3. REMOTE CASSETTE CONTROL (CONCLUDED)
CNTQ
CIBUSY
count
cassette-! busy
C2BUSY
cassette-2 husy
CICNTDN
C2CNTDN
ClCNTLD
C2CNTLD
CICNTQ
C2CNTQ
CICNTLDA
C2CNTLDA
CIRCD
CIR2BUSY
DETBLK
KBDLOC
KBDON
PBKBUSY
PNHONQ
PNHRDY
RCDBUSY
RCOOF
RCOON
RCDSTP
RDRLINE
RDROF
RDRON
RDRSTQ
RDRRDY
READCK
RERRORQ
REVDLY
RFEED
cassette-l countdown
cassette-2 countdown
cassette-l load
cassette-2 load
cassette-l count
cassette-2 count
cassette-l count load
cassette-2 count load
cassette-l record
cassette-lor -2 busy
detect block
keyboard local
keyhoard on
playback busy
punch on
punch ready
recorder busy
record off
record on
record stop
reader line
reader off
reader on
reader start
reader ready
reader clock
reader error
reverse delay
reader feed
TPERSQ
TREBLK
TRFCLKB
TRl/4T
TR3/4T
TR5/4T
TR21/4T
TlTACH
T2TACH
XBSPFW
XBSPRV
XCIRCD
XERASE
XLD/FWl
XRCHFW
XREWl
XSTPCA2
tape erase
tape read block
transport reference clock B
tape read 1/4T
tape read 3/4T
tape read 5/4T
tape read 21/4T
transport-l tach
transport-2 tach
switch block space forward
switch block space reverse
switch cassette-l record
switch erase
switch load/fast forward 1
switch read character forward
switch rewind 1
switch stop cassette 2
signifies gap has heen written by record unit
playhack, record, tape erase, or block
reverse in progress on transport-!
playback, record, tape erase, or block
reverse in progress on transport-2
signals gap counter-l to countdown during hlock reverse
signals gap counter-2 to countdown during block reverse
load transport-l gap counters
load transport-2 gap counters
terminates loading of transport-!
terminates loading of transport-2
load signal to transport-l gap counters
load signal to transport-2 gap counters
cassette-l is in record mode
(~"
'--/
block detected
keyboard is in local mode
playback on or block reverse in progress
signifies recorder is on
recorder ready to record
recorder on or tape erase in progress
remote record off line
remote record on line
stops tape erase or record controller
playback is on line
remote reader is off line
remote reader is on line
initiates continuous read operation
playback is ready
204.8 kHz
read error detected
signifies 64 tach pulses counted after gap detected
playback is reading a block from tape or
transmitting data to bus
tape erase operation in progress
signifies tape in interblock gap
1.0667 kHz used to count block reverse delay
signifies middle of data bit time
signifies middle of phase bit time
signifies bit dropout
signifies gap on tape
tach feedback from transport 1
tach feedback from transport 2
switch command to perform block forward
switch command to perform block reverse
switch command to place cassette-l in record mode
switch command to erase tape or record buffer
command to load or fast forward cassette 1
switch command to perform character forward
command to rewind cassette 1
stops rewind, load, or fast forward on cassette 2
"
\
(~.
'-.j
A-18
A-19
SLOT XA-4. PLAYBACK CONTROL (CONCLUDED)
TPRQ2
TPRQ3
TREBLK
tape reader state 2
tape reader state 3
tape read block
TRQ3
TRSY
tape read state 3
tape read sync
TRSYNCQ1TRSYNCQ2-
tape read sync 1
tape read sync 2
TR1/4T
TR5/4T
TR21/4T
XRCHFW
tape read 1/4 T
tape read 5/4 T
tape read 21/4 T
reader character forward
reading data from tape
looking for gap
signifies a block has been read
(playback reaches interblock gap)
signifies tape data bit transition
resets read data latch to proper state
after TRSYNCQ1 is removed
syncs tape read circuit to seek first preamble bit
enables setting read data latch to correct
state after TRSYNCQ1 is removed
signifies middle of a data bit time
signifies missing phase change
signifies tape data gap found
initiates a character forward operation
SLOT XA-5~ RECORD BUFFER
Signature
I
Definition
BLCNUPCBKSPQ-
block count up
character backspace
CNFMTCSCLK
DATADCHBITl
DCHCLRFLXCLK
MPNSTQM1ADOO
M1CK-M1CKENA
M1CS1
M1CS2
M1RDAT
M1RDRQ1
MIRDRQ2
continuous format
serial clock
MIRD1CK
memory 1 read 1 clock
M1RD2
MIRD2CK-
memory 1 re;ld 2
memory 1 read 2 clock
MIWRENA
M1WRRDl
MIWRRQl
PADCNL-
memory 1 write enable
memory 1 write/read 1
memory 1 write request 1
punch address count load
PNHCNUP
PNHCRD
PNHENAR
punch count up
punch carriage return
punch enable to receive
display bit 1
display character clear
flux clock
manual point stop
memory 1 address 0
memory 1 clock
memory 1 clock enable
memory 1 chip select 1
memory 1 chip select 2
memory 1 read data
memory 1 read request 1
memory 1 read request 2
1
Function
store beginning address of new block
decrement record buffer address
by 1 during edit
ignore carriage return decode
clocks data on bus
data on bus
bit 1 of character display
clear character display register
12.8 kHz, tape write data clock
causes writing of nulls in memory after a manual stop is detected
most significant bit of record buffer address
204.8 kHz
selects memory chip 1 of record buffer memory
timing to increment block counter
record buffer output for tape write
request to read from memory record buffer for display
request to record buffer memory during
memory read-only cycle
clock data to record buffer memory and
then out of memory to display register
read-only part of memory cycle
clocks data from record buffer memory
during memory read-only cycle
write data clocks for record buffer memory
write/read part of memory cycle
request to write in record buffer memory
transfer beginning address of block to
record memory address registers
increment record buffer address by 1 after punching character
carriage return decode
data on bus to recorder
A-20
(,<-j
SLOT XA-S. RECORD BUFFER (CONCLUDED)
(
PNHENAWPNHONQ
PNHRDY
PNH02Q
PWRRSTRCBFFLREADCK
TPWBSY--
punch enable to write
punch on
punch ready
punch state 2
power reset
record buffer full
read clock
tape write busy
TRFCLKA
TRFCLKB
transport reference clo~k A
transport reference clock B
data on bus
record is on
record ready
increments record buffer address by 1 during print buffer
same as TPWBSY204.8 kHz master system clock
recorder has block, but is not yet
writing on tape; or recorder is writing
block on tape and has second block in buffer
6400 Hz
1066.7 Hz
SLOT XA-6. TAPE READ/WRITE
Signature
I
I
Definition
=0
BCHCNOBcSELQ
BLCNDNBLCNEO
BLCNGI2BLCNUPCNFFMTCNTQCPNHCLK
CIRCD
C2RCD
DATENQ
FLXCLK
MEMENQ-
block character count
block check select
block count down
block count = 0
block count> 12
block count up
continuous format
count Q
cassette punch clock
cassette-l record
cassette-2 record
data enable Q
flux clock
memory enable Q
MICS2
memory 1 chip select 2
MIRDAT
MIRD2
MIRD2CK
MIRDRQ2
M2WDAT
PAMTQ
PEPHQ
PNHRDY
PSAMQ
RDRCLK
RERRORQTPERSQ
TPWBSYTPWDATA
TPWFW
TPWOIQ
TPW02Q
memory 1 read data
memory 1 read 2
memory 1 read 2 clock
memory 1 read request 2
memory 2 write data
postamble data
phase-encoded phase bit
punch ready
posta,mble
reader clock
reader error
tape erase
tape write busy
tape write data
tape write forward
tape write state 1
tape write state 2
Function
86 characters have been written on tape
enables block check data to tape
decrement block counter by 1
no block to write on tape
block counter about to overflow (record buffer is full)
increment block counter by 1
ignore end-of-block flag bit
signifies end of a gap on tape
6.4 kHz
cassette 1 in record mode
cassette 2 in record mode
enables write data to tape
12.8 kHz tape write data clock
signifies data still in record memory to
put on tape
block counter is decremented by 1
during this time, if necessary
data from record buffer memory
enables write data register
clocks record buffer data to write data register
request to read data from record buffer memory
tape read binary data for playback buffer memory
data for both preamble and postamble characters
PE data phase bit
record ready
enables postamble data to tape
204.8 kHz
causes entry of nulls into playback buffer memory
starts transport forward
signifies record buffer is full, stop sending data
PE data to tape
move tape forward
start tape forward to write
end of gap, start writing data
A-21
SLOT XA-6. TAPE READ/WRl1'E (CONCLUDED)
TRDATA
TRDTA
TRDTB
TRQ1
TRQ2
TRQ3
TRSY-
tape read data
tape read data A
tape read data B
tape read state 1
tape read state 2
tape read state 3
tape read sync
TRSYNCQl-TRSYNCQ2-
tape read sync 1
tape read sync 2
TRl/4T
tape read 1/4 T
TR3/4T
tape read 3/4 l'
TWCHCLKTIRDTATIRDTBT2RDTAT2RDTBWRTDTQ
WRTEBDWRTEBQlWRTEBQ2-
tape write character clock
tape 1 read data A
tape 1 read data B
tape 2 read data A
tape 2 read data B
write data
write end of block
write end of block 1
write end of block 2
PH data from tape
indicates- ZERO to ONE flux transition on tape
indicates ONE to ZERO flux transition on tape
signifies a tape data hit transition from a ONE to a ZERO
signifies a tape data: hit transition from a ZERQ to a ONE
signifres a tape dat~ bit transition from a ZERO to a ONE
resets read- data latch to correct state
after TRSYNCQl is removed
syncs tape read circuit to detect first preamble bit
enables resetting read !lata latch to correct
state after TRSYNCQ1 is removed
signifies 1/4 of a tape read data bit time
(center of data bit time}
signifies 3/4 of a tape read data hit time
(center of phase bit time)
800 Hz, issues requests to read from record buffer memory
tape read data from transport 1
tape read data from transport 1
tape read data from transport 2
tape read data from transport 2
binary write data to tape
signifies last character of a block (in line format)
end-of-block flag bit detected
disable input data
SLOT XA-7. RECORD CONTROL
Signature
BLCNUPBUFRREQCBKSCNEOCBKSPQCFWSPQ
COVPQ-
1
Definition
block count up
buffer request
character backspace =1= 0
character backspace
character forward space
character overpunch
CPNHCLK
CPNHQ
DA1'ADCHBITI
DCHCLRERASEQ
MPNSTQMICS2
display character bit 1
display character clear
erase
manual stop
memory 1 chip select 2
MIRDRQl
MIWRRQl
PADCNLPNHCEOPNHCLR
PNHCNE86
memory 1 read request 1
memory 1 write request 1
punch addresB count load
punch count:: 0
punch dear
punch count:: &6
cassette punch dock
character punch
I
Function
increment record block counter by 1
print buffer operation
decrement record buffer address by 1
increment record buffer address by 1
OR input character with record register
and put result back into record register
6.4 kHz
record a character
serial data bus
output of character display register
erase record buffer contents (reset address)
stop punch 'feed'
.
block coUnter incremented during this time,
if necessary
request to read from record buffer memory
request to write in record buffer memory
load beginning address of present block
reset record controller
,1'
:'''-_./
A-22
SLOT XA-7. RECORD CONTROL (CONCLUDED)
(-
PNHCNUP
PNHCRD
PNHENARPNHENAWPNHENARQ
punch
punch
punch
punch
punch
count up
carriage return decode
enable to read
enable to write
enable to receive Q
PNHLINE
PNHONQ
PNHOIQ
PNH02Q
PNH03Q
PNH04Q
PNH05Q
punch
punch
punch
punch
punch
punch
punch
on-line
on
state 1
state 2
state 3
state 4
state 5
PNHRDY
PRNBUFQRCDSTPRECENATPBKSPTPFWSPXERASEXPRNBUF-
punch ready
print buffer Q
record stop
record enable
tape backspace
tape forward space
erase
print buffer
increment punch character counter by 1
signifies a block ended by carriage return (line format)
data on bus from record buffer
data on bus to record buffer
signifies data sent to serial bus
(end-of-record enable)
record on line
start punch 'feed'
wait state
update counters during print buffer
send a print buffer request
wait for a record enable
terminate print buffer operation and
reload record character counter
ready to record
print out record buffer memory contents, if any
halts record operation
data on bus to/from recorder
backspace record buffer one character
forward space record buffer one character
zero contents of record buffer, or erase tape
print the contents of the record buffer
SLOT XA-9. CASSETTE TRANSPORT
(
Signature
BOT
CINPLACE
EDT
FAST
FWD
RDTA
RDTB
REV
TACH
TRFCLKA
WDATA
WRITEWRTTAB
I
Definition
begilining of tape
cassette in place
end of tape
fast
forward
read data A
read data B
reverse
tach pulse
tape reference clock
write data
write
write tab
I
Function
goes high when BOT sensor does not sense magnetic tape
goes high when cassette in place and door closed
goes high when EOT sensor does not sense magnetic tape
places transport in fast mode
command to move tape forward
A component of PE read data (TTL)
B component ofPE read data (TTL)
command to move tape backward.
tach pulses from capstan motor tach generators
reference dock for transports to control tape speed (6400 Hz)
TIL PE data to be written on tape
ZERO on this pin enables write circuits
indicates when write enable tab is present
(
A-23
----~------
.. ,.
~f ~~".
'-_/
APPENDIX B
ASSEMBLY DRAWINGS AND PARTS LISTS
This Appendix contains assembly drawings and parts lists to aid in maintaining, troubleshooting, and repairing the 732/733
Data Terminals. The drawings and associated parts lists are divided into five groups, and drawings within each group are
arranged in numerical order.
An index to the drawings and their associated parts lists is shown below.
MAJOR ASSEMBLIES
Title
ASR Module (Upper Unit)
Printer, Common
*732 ASR Terminal
*732 KSR Terminal
*733 ASR Terminal
*733 KSR Terminal
732 RIO Terminal
733 RIO Terminal
732 KSR Terminal
732 ASR Terminal
733 KSR Terminal
733 ASR Terminal
(
TI Drawing Number
959389U
959404V
960970C
960971C
960972E
960973D
971575
971576
97395ID
973952D
973953D
973954E
MAJ9R SUBASSEMBLIES
Power Module
Drive Mechanism
Printhead, Single Cable
AC Power
Head Stepping Motor
Paper Stepping Motor
Carriage
Printhead
Transport Assembly
Auto Answer Display Panel
Acoustic Coupler
Footpedal
959390T
95939IR
959394F
959395J
959399G
959400C
9594I3D
959422B
96033IP
960983
969620A
973866
CABLE ASSEMBLIES
Power Switch
Keyboard
ASR Module Assembly
EIA Interface
Fan, Lower Unit
AC Power Assembly
Modem Interface
TTY Interface
Fan, Upper Unit
Auto-Answer Control, EIA
Option Display Panel
Auto-Answer Control, Modem
I13A, EIA Cable
Acoustic Coupler Y Connector
(:
959246D
959370K
959371F
959372F
959379C
95938IB
959383C
959384B
960071B
971555
971556C
971557A
971558B
973254B
*Obsolete
B-1
PC CARD ASSEMBLY DRAWINGS
Printer Control
Transmit/Receive, Baudot
Transmit/Receive, ASCII
Printer Code, ASCII
Printer Code, Baudot, U.S.
Printhead Interface
Regulator /Amplifier (lOA)
Control Regulator (lOA)
Terminal Control, ASR
Display (dual cassette)
Power Module Motherboard
ASR Module Assembly Motherboard
TTY Interface, Polar
TTY Interface, Neutral
TTY Interface, Computer
Terminal Control, KSR
Cassette Transport
Remote Device Control
Answer-Back Memory
Auto-Answer Control
Modem, ATL
Modem, ATL-2
Modem, ATH
*Auto Device Control (2 cards)
Remote Cassette Control
Record Buffer Control, 300 Baud
Record Buffer Control, Baudot
Playback Control
Motion Control
Record Control
Tape Read/Write Control
Dual Format Record Buffer
Receiver, 1200 Baud
Transmitter, 1200 Baud
Dual Format Tape Read/Write Control
Dual Format Playback Control
Dual Format ASCII Transmit/Receive
Regulator/Amplifier (14A)
Control Regulator (14A)
Auto Device Control (2 cards)
Remote Device Control (Multilayer)
Auto Search Control (2 cards)
Auto Search Control (2 cards)
Remote Device Control (Multiwire)
1200 Dual Format Transmit/Receive
Receiver, 1200 Baud
959131W
959133L
959135N
959137-0001T
959137-0002T
959141F
959143W
959145T
959147N
959155N
959157J
959159D·
959171-0001H
959171-0002H
959171-0003H
959173H
960080T
960169
960881F
960885F
960887-0001E
960887-0002E
960887 -0003E
960891A
960901F
960903-0001G
960903-0002G
960905G
960907K
960909F
962281E
962285G
962291A
962293D
969451E
969453D
969455B
971443F
971450E
971481H
971483H
971485D
971493D
973901F
973905D
973907A
MISCELLANEOUS DRAWINGS
ASR Outline Dimensions
KSR Outline Dimensions
960131
960132
C
.,~
"J
C'
*Obsolete
B-2
MAJOR ASSEMBLIES
ASR Module (Upper Unit)
Printer, Common
*732 ASR Terminal
*732 KSR Terminal
*733 ASR Terminal
*733 KSR Terminal
732 RIO Terminal
733 RIO Terminal
732 KSR Terminal
732 ASR Terminal
733 KSR Terminal
733 ASR Terminal
('
*Obsolete
959389
959404
960970
960971
960972
960973
971575
971576
973951
973952
973953
973954
(~\
'_-7
\
/
nnnri
UUllii
==
959389-1
NJVEMSER 22. 197ft
PAlIT NU"SEI<
REV
9S93e~-COOl
S
l
r
C F
S T
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959389-0001t
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1209-0102-Cl Z
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1210-9159-0(1(1
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1209-0331-4.12
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1209-9155-060
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1209-15-211-(03
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1209-1529-1:13
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1l09-1'30-COI
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1209-0909-01t2
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1209-1319-00 1
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NOVEMBER 22, 1914
PART NUMBE~
959404-0001
REV
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LIS T
OF
MATEPIAL
•••••••••••••••••• ~ ••••••••••
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1209-0107-(1)0
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960105-0001
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00001.000
959391-~001
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1209-9303-(16
DRIVE MFCHANISM ASSY
1:109-9391-412
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960~66-~001
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539805-0004
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959340-0001
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1209-9390-412
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1209-0<;41-015
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1209-0112-010
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1209-9246-028
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PART NUMBER
959404-0001
REV
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1210-1443-000
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960970-1012
(
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DESCRiPTION •••••••••••••••••••••••••••••
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COMPONENT..
PART NUMBER
960971-1004
REV
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DESCRIPTION •••••••••••••••••••••••••••••
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TERMINAL ASSY,MDD 732 KSR
11M.
QTY
COMPONENT..
DESCRiPTION•••••••••••••••••••••••••••••
001
001
959404-0001
002
001
960110-0001
003
001
960110-0002
004
001
959422-0001
005
001
959370-0001
006
002
960106-0001
007
002
235053-0001
PRINTER ASSY,COMMON 110AI
1209-9404- C65
NAMEPlATE,BLANK
1209-011 O-OlD
NAMEPlATE,SIlENT 700
1209-1030-006
PRINT HEAD ASSY,EPN 1-4
1209-9422-045
CABLE ASSY,KEYBOARD
1209-9370-063
PLATE,ORESS KSR
1209-0106-013
SCREW
6-32X5/16 6H SST
OOB
006
235054-0001
SCREW
009
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232455-0000
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010
012
236385-0000
011
008
236388-0000
012
001
959290-0001
013
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959418-0001
014
004
772614-0001
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GUIUE,FlEX CABLE
1209-9290-009
CLIP SUBASSY,FLEX CABLE
1209-9418-040
FASTENER PUSH-ON RECTANGULAR
015
001
962571-0001
PLATE,IDENTIFICATION
016
REF
959223-9901
SPEC,EQUIPMENT
017
001
959228-9101
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REF
911463-9901
MANUAL,OPERATOR (8AUDOTI
1209-9228-000
SYS & SP TEST HOW,RUN-IN 700 ASR/KSR
021
001
959141-0001
6-32X3/8 BH SST
6-32X5/16X7/6~
THK SST
026
001
960111-0001
PRI NTHEAD INTERFACE
1209-9141- 053
PANEL,BlANK OPTION
021
001
959325-0001
KEYBOARD,BAUOOT
026
001
960921-0001
029
001
959372-0001
COVER,KEYBOARD-BAUOOT
1209-0921-004
CABLE ASSY,EIA INTERFACE-300 BAUD
1209-9312-040
PANEl,POWER SWITCH
031
001
960113-0001
032
001
959131-0002
033
001
960881-0001
034
001
959173-0001
035
001
959133-0001
039
001
960944-0001
041
001
960961-0001
042
003
235056-0001
PRINTER CODE,BAUOOT-U.S.FIGURES
1209-1501-010
OUAl CODE ANSWER 8ACK MEMORY
1209-0881-013
BOARD ASSY,TERMINAl CONTROl-KSR
1209-9173-049
BAUDOT TRANSMITI RECE IVE
1207-3133-000
COVER,POWER MODULE
1209-09'>4-012
lEAD,ElECTRICAL-GRD
1209-0967-029
SCREW 6-32Xll2 BH SST
043
001
236386-0000
WASHER
1/.6 EXT TOOTH LOCK SST
-1#6
044
002
232456-0000
NUT 6-32Xl/4X3/32 THK SST
045
001
960141-0001
LABEL,SERVICE
046
001
971412-0001
LABEL,PAPER lOADJNG
041
001
971461-0001
COVER ,CONNECTOR
050
002
539665-0005
FASTENER,3M #3220
051
002
911415-0001
FASTENER, MODIFIED
052
AR
410423-0001
ADHESIVE,GENER~L
1209-14b1-004
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1209-1501-011
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1209-0881-019
BOARD ASS V, TE:RMINAL CONTROL-KSR
1209-9173-046
BAUDOT TRANSMIT/RECEIVE
1207-3133-000
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1209-9171-014
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1209-1502-020
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1209-0944-008
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1209-0967-021
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ROTATE:
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PART '\lUMBER
960972-1521
REV
E
DESCRIPTION •••••••••••••••••••••••••••••
TERMINAL ASSY,MOD 733 ASR
I TM.
QTY
COMPUNENT..
DESCRIPTION •••••••••••••••••••••••••••••
001
001
959404-0002
002
001
960110-0001
007
002
235053-0001
PRINTER ASSy,COMMON (14AI
1209-1506-023
NAMEPLATE,BlANK
ll09-0 110-010
NAMEPLATE,SllENT 700 ASR
1209-1031-007
PRINT HEAD ASSY,EPN 1-4
1209-9422-045
CABLE ASSY,KEYBOARD
1209-9370-083
CABLE ASSY,CASSETTE
1209-9371-054
SCREW
6-32X5/16 BH SST
008
012
235054-0001
SCREW
009
004
232455-0000
NUT 6-32X5/16X7/64 THK SST
003
001
960110-0003
004
001
959422-0001
005
001
959370-0001
006
001
959371-0001
010
012
236385-0000
011
008
236388-0000
012
001
959290-0001
6-32X3/1' BH SST
013
001
959416-0001
014
002
960101-0001
015
004
235101-0001
WASHER
'6 FlT SS 1/32 THK
-'6 FlA T
WASHER.6 SPLITLOCK SST
-'6 SPLITLOCK
GUIDE,FLEX CABLE
1209-9290-009
CLIP SUBASSY.FLEX CABLE
1209-9418-040
PEDESTAL.MACHINED
1209-0101-014
SCREW
10-32 X 3/8 BH
016
004
772814-0001
FASTENER
PUSH-ON RECTANGULAR
017
001
962571-0001
PLATE,IOENTIFICATION
018
REF
959220-9901
SPECIFICATION,EQUIPMENT
019
001
959227-9701
020
REF
971463-9901
MANUAL,OPERATOR
1209-9227-000
SYS & SP TEST FLOh,RUN-IN 700 ASR/KSR
021
001
959141-0001
026
001
960111-0001
PRINTHEAO INTERfACE
1209-9141-053
PANEL, BLANK OPTION
027
001
959326-0001
KEYBOARD.fULL ASCII-ENCODED
028
001
960920-0001
029
001
959372-0001
030
001
959389-0001
031
001
960113-0001
COVER,KEYBOARO fULL ASCII
1209-0920-007
CA8lE ASSY.EIA INTERFACE-300 8AUO
1209-9372-040
ASR MODULE ASSY
1209-9389-069
PANEL,POWER SWITCH
032
001
959137-0001
033
001
960881-0001
034
001
959147-0001
035
001
959135-0001
036
001
971491-0002
037
001
960981-0001
039
001
960944-0001
040
001
971415-0001
041
001
900961-0001
042
003
235056-0001
PRI NTER CODE,ASCII
1209-9137-053
DUAL CODE ANSWER BACK MEMORY
1209-0881-013
TERMINAL CONTROl,ASR
1209-9147-048
ASCII TRANSMIT AND RECEIVE
1209 -9135-052
MOTHER 80ARD ACCESS,ASC
1209-1591-012
AUTOMATIC SEARCH CONTROL KIT,W/O MBAC
1209-0981-000
COVER, POWER MOOULE
1209-0944-012
CLEANING KIT-CASSETTE TRANSPORT
1209-1415-001
LEAO,ELECTRICAL-GRD
1209-0967-029
SCREW 6-32Xl/2 Ok SST
043
007
236386-0000
WASHER
044
002
232456-0000
-'6
NUT 6-32X1/4X3/32
045
COl
960141-0001
LABEL,SERVICE
.6 EXT TOOTH LOCK SST
THK SST
960972-3
- - - - _...._-- ---
041
001
971412-0001
lA6El,PAPER LOADING
048
001
959230-9101
13U133 ASR QUICK REfERENCE CARD
049
002
235028-0001
SCREW
--~---.----~-
(~
.~./
1t-40X5/8 8H SS
050
002
235025-0001
SCREW 1t-ItOX3/8 8H SST
051
002
539665-0005
FASTENER,3M .3220
052
002
91L415-0001
FASTENER,MODIFIED
053
AR
410423-0001
AOHES[VE,GENERAL PURPDSE,CYANOACRYlATE
*
1,(
960972-4
.~
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"
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.3.8.q.:t.ZS-
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960973-2
o
(
PAR T NUMBE R
960913-1511
REV
o
DESC~IPTION •••••••••••••••••••••••••••••
TERMINAL ASSY,MOO 133 KSR
ITM.
QTY
COMPONENT..
DESCRiPTION •••••••••••••••••••••••••••••
001
001
959404-0001
002
001
960110-0001
003
001
960110-0002
004
001
959422-0001
005
001
959370-0001
006
001
960108-0001
007
002
235053-0001
PRINTER ASSY,COMMCN (10AI
1209-9404-085
NAMEPLATE,BLANK
1209-0110-010
NAMEPLATE,SILENT 100
1209-1030-006
PRINT HEAD ASSY,EPN 1-4
1209-9422-045
CASLE ASSY,KEYBOARO
1209-9310-083
PLATE,DRESS KSR
1209-0108-013
SCREW
6-32X5/16 BH SST
OOB
008
235054-0001
SCREW
009
008
232455-0000
NUT 6-32 X5/16X1I64 THK SST
010
012
236385-0000
011
008
236388-0000
013
001
959418-0001
6-32X3/8 BH SST
015
001
962571-0001
WASHER
.6 FLT SS 1/32 THK
-#6 FLAT
WASHER #6 SPLITLOCK SST
-#6 SPLITLOCK
CLIP SUBASSY,FLEX CABLE
1209-9418-040
PLATE, IDENTIFICATION
016
REF
959221-9901
SPEC,EQUIPMENT
017
001
959221-9701
MANUAL,OPERATOR
1209-9227-000
SYS &. SP TEST FLOW,RUN-IN 100 ASR/KSR
018
REF
971463-9901
021
001
959141-0001
026
001
960984-0002
027
001
959326-0001
028
001
960920-0001
031
001
960113-0001
032
001
959131-0001
PRINTHEAD INTERFACE
1209-9141-053
AUTO ANSWER OPTION KIT-EIA,W/ANSB
1209-1561-012
KEYBOARO,FULL ASCll-ENCODEO
COVER,KEYBOARO FULL ASCII
1209-0920-001
PANEL,POWER SWITCH
PRINTER COOE,ASCII
1209-913 7-053
DUAL CODE ANSWER BACK MEMORY
1209-0881-013
BOARD ASSY,TERMINAL CONTROL-KSR
1209-9173-049
ASCII TRANSMIT AND RECEIVE
1209-9135-052
AUTO DEVICE CONTROL-300 BAUD
1209-1481-014
COVER,POWER MODULE
1209-0944-012
LEAD,ElECTRICAL-GRD
1209-0967- 029
SCREW 6-32Xl/2 BH SST
033
'001
960881-0001
034
001
959113-0001
035
001
959135-0001
036
001
971481-0001
039
001
960944-COOI
041
001
960961-0001
042
003
235056-0001
043
007
236386-0000
044
002
232456-0000
WASHER
#6 EXT TOOTH LOCK SST
-#6
NUT 6-32X1/4X3/32 THK SST
045
001
960141-0001
LABEl,SERVICE
046
001
971412-0001
LABEL,PAPER LOADING
047
002
539665-0005
FASTENER,3M .3220
048
002
971475-0001
FASTENER,MCDIFIEO
049
AR
410423-0001
AOHESIVE,GENERAL PURPOSE,CYANOACRYLATE
*
(
960973-3
Q
888
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i
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971575-1
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971575-2
OCTn~EP
24. 1913
PART NUMBER
971575-
LIS T
REV
*
nEscnIPTIO~
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F
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M 1\ T E R I 1\ L
-. ./
•••••••••••••••••••••••••••••
TERMINhL ASSY.MOD 732 R.O.
ITEM.
OUANTITY.
COMP(JNf'NT ••
l)ESCQ IP T ION . . . . . . . . . . . . . . . . . . . . ,. ••• ••• ••• UM
0001
00001.000
959404-0003
0002
00001.000
960110-0001
0003
00001.000
960110-0002
0006
00002.000
960108-0001
0007
00002.000
235053-0001
PRINTER ASSY,COMMON (RO)
1209-1'i 13-000
NAMF-PLAT E, BLANK
1209-0110-007
NAMEPLATE,SILENT 700
1209-1030-{)05
PRINT HEAO ASSY,EPN 1-4
120Q-9422-042
PLATE,DRESS KSR
1209-0108-007
SCRFW
6-32X5/16 BH SST
EA
0008
00004.000
235054-0001
SCREW
fA
0009
00004.000
232455-0000
NUT 6-32X.5/16X7I64 THK SST
0010
00008.000
23b385-0000
0011
00004.000
23~388-0000
0013
00001.000
959418-0001
0014
00004.000
772814-0001
WASHER
#6 FlT SS 1/32 THK
-#6 FLAT
WASHER #6 SPllTLOCK SST
-#6 SPlI TLOCK
CLIP SUBASSY,FLEX CABLE
1209-9418-023
FASTENER PUSH-ON RECTANGULAR
0015
00001.000
962571-0001
PLATE,IDENTIFICATION
EA
971573-9901
SPECIFICATION,EOUIPMfNT
EA
971579-9701
MANUAL,OPERATOR 732/733 RO
1209-1592-000
SPECIFICATION,TEST-ASR & KSR
FA
PRINTHEAD INTERFACE
1209-9141-054
PANEl,BlANK OPTION
EA
PANEL BLANK-732/733 R.O.
1209-3230-000
CARLE ASSY,EIA INTERFACE-300 BAUD
1209-9312-031
CABLE IISSY,TTY INTERFACE
1209-9384-022
PANEL,POWER SWITCH
EA
0004
0016
0017
0018
REF
00001.000
RFF
959229-9901
6-32X3/8 RH'SST
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
0021
00001.000
959141-0001
0026
00001.000
960111-0001
G028
00001.000
9737.30-0001
0029
00001.000
Q59372-0001
0029
00001.000
959384-0001
0031
00001.000
960113-0003
0032
00001.000
959137-0002
0033
00001.000
960160-0001
0034
00001.000
959173-0001
0035
00001.000
959133-0001
GO.38
00001.000
959171-0001
0038
00001.000
959171-0002
0039
00001.000
960944-0001
0041
00DD1.pOO
960967-0001
0043
00002.000
236386-0000
0044
000al.000
232456-0000
NUT 6-32Xl/4X3/32 THK SST
EA
00001.000
9601~1-0obl
LABEL.SERVICE
I:A
PRINTER COOE,BAUOOT-U.S.FIGURES
1209-1501-011
TOP IICCESS CONNECTOR
1209-0160-009
BOARO IISSy,TERMINAL CONTROL-KSR
1209-9173-046
BAUDOT TRANSMIT/RECEIVE
1209-9133-011
TTY INTERFACE-POLAR
1209-9171-014
TTY INTERFACE-NEUTRAL
1209-1502-020
COVER,POWER MODULE
1209-0944-008
lEAO,ELECTRICAL-GRO
1209-0967-021
WASHER
#6 EXT TOOTH LOCK SST
-1#6
971575-3
EA
EA
EA
EA
EA
EA
EA
EA
EA
fA
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EA
EA
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97IS7Eo~'OL2.
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PART NUMBtoR
D
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971576-2
Q
OCTOBER 24. 1973
PART NUMSER
911576-
LIS T
REV
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F
MATERIAL
DESCRIPTION •••••••••••••••••••••••••••••
TfRMINAL ASSY,MOO 733 RO
ITEM.
OUANTITY.
COMPONENT ••
DESCRIPTION ••••••••••••••••••••••••••••• UM
0001
00001.000
959404-0003
0002
00001.000
960110-0001
EA
EA
0003
00001.000
960110-0002
0004
00001.000
959422-0001
0006
00002.000
960108-0001
0007
00002.00p
235053-0001
PRINTER ASSY,COMMON (ROJ
1209-1513-000
NAMEPlATE,BLANK
1209-0110-001
NAMEPLATE,SILENT 100
1209-1030-005
PRINT HEAD ASSY,EPN 1-4
1209-9422-042
PLATE,DRESS KSR
1209-0108-007
SCREW
6-32X5/16 BH SST
OO.OS
00004.000
235054-0001
SCREW
0009
00004.000
232455-0000
NUT 6-32X5/16X7/64 THK SST
EA
0010
00008.000
236385-0000
EA
0011
00004.000
236388-0000
0013
00001.000
959418-0001
0014
00004.000
772814-0001
WASHER
#6 FlT SS 1/32 THK
-#16 FLAT
WASHERtl6 SPUTLOCK SST
-116 SPlI TLOCK
CLIP SUBASSY,FLEX CABLE
1209-9418-023
FASTENER PUSH-ON RE~TANGULAR
0015
00001.000
962571-0001
PtA TE, I DENTlFlCATtON
fA
971574-9901
SPECIFICATIDN,EOUIPMENT
EA
971579-9701
MANUAL,OPERATOR 732/733 RO
1209-1592-000
SPfCIFICATION,TEST-ASR & KSR
EA
PRINTHEAD INTERFACE
1209-9141-054
PANEL,BLANK OPTION
EA
AUTO ANSWER OPTION KIT,MODEM
1209-0984-014
PANEL RLANK-132/733 R.O.
1209- 3230-000
L~~L~ ASSY,TTY INTERFACE
1209-9384-022
PANEL,POWER SWITCH
EA
0016
0017
REF
00001.000
0018
(
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0021
00001.000
959141-0001
0026
00001.000
960111-0001
0026
00001.000
960984-0001
0028
00001.000
913230-0001
0029
00001.000
959384-0001
00~1
00001.000
960113-0003
0032
00001.000
959137-0001
0033
00001.000
960881-0001
0034
00001.0DO
959173-0001
0035
00001.000
959135-0001
0036
00001.000
911481-00u.
0038
00001.000
960881-0003
6-32X3/8 BH SST
PRINTER CODE,ASCII
1209-9137-050
DUAL CODE ANSWER SACK MEMORY
1209-0881-019
aOAPI) ASSy,TERMINAL CONTROL-KSR
1209-9173-046
ASCII TRANSMIT AND RECEIVE
1209-9135-053
AUlU DEVICE CONTROL-300 SAUD
1<'09-1481-013
"O~EM,ATH
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
EA
fA
EA
EA
EA
fA
00001.000
959171-0002
00"9
00001.000
960944-0001
0041
00001.000
960967-0001
0043
00002.000
2363~6-0JOO
1209-1523-021
TTY INTERFACE-NEUTRAL
1209-1502-020
TTY INTERFACE-POLAR
120°-9171-014
COVtR,POWER MODULE
1209-0944-008
LFAD,ELECTRJCAL-GRO
1209-0967-021
WASHER
#6 EXT TOOTH LOCK"SST
0044
00001.000
232456-0000
NUT 6-32Xl/4X3/32 THK SST
EA
0045
00001.010
96014)-0001
LABEL,SERVICE:
fA
0038
0038
-1/6
971576-3
EA
Ell
EA
fA
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111
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973953-0001
REV
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MATf~IAL
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•••••••••••••••••••••••••••••
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QUA "I TI TV.
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DESCPIPTJCN ••••••••••••••••••••••••••••• UM
0001
000Cl.000
9~q4C4-v002
PQINTFR ASSy,COM~ON 114AI
1209-1506-C31
EA
0002
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1209-0110-ClO
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1 ?09-9422-(45
EA
A~S~,KEY~OARr
1209-9310-016
0006
EA
Pl HE ,CPf5~ I(~P
1209-01C8-CI5
SCREW
6-32X5/16
C001
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235(54-..1001
(OC9
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232455-ucn~
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0010
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CLIP SUEASSY,FlEX (ABLE
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EA
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LIST
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NOVEMBER 22. 1974
PART NU"BE~
971558-0001
REV
A
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-r. a
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DESCRIPTION •••••••••••••••••••••••••••••
CA8LE ASSY,BELl 113A INTERFACE'
ITE".
QUANTITY.
COMPO~ENT ••
OESCRIPTION •••••••••••••••••••••••• ~ •• ~. UM
0001
00001.000
232118-u075
HOUSING C[NN.PC 10 DUAL P~S
AMP-58296.3-2
PI
A"P-582963-2
HCCD,I/C C[NNECTOR 10 PIN
-000
CONTACT
lEA~ 42717-3
U'P-42717-3
SPRING
RETAINING 42~73-3
AMP-42973-3
SCREW
4-40X5/8 BH SS
OODlA
0002
00CCl.000
960914-uOOI
0003
0001D.000
231553-uOl0
0004
00002.000
235~11-u050
0005
00004.000
235C28-uOOl
0006
00002.000
236371-uOOO
0007
00002.000
0008
00002.000
0009
0010
0011
000Cl.000
539409-u005
P~ENCLtC
EA
EA
EA
EA
EA
EA
216374-uOOO
WASHER.4 Fl T' .125 X .312 SST
-14 FLAT
~ASHER.4 EXT TH SST
232452-UOOO
NUl
EA
00001.000
230?C9-~000
000C6.500
236318-0000
BUSHING SNAP .37500 .2510
HEY-Se-375-4
TU81NG
.2 .263 10 8lK.PLAS
IRV-'2
CCNNECTOR PHD-20 25 PIN
AMP-205208-1
PI3
AMP-205208-1
HOOD ASSY ~/HAROWARE
AMP-205718
STRAP STD "KR BUNDLE DIA 0 TO 1-3/4 IN
PNO-SSM-2
WIRE HO(l1(UP B-22 AWG 19 STR
~HITE
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CONTACT PIN .062 OIA
A"P--205202-2
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DESCRIPTION
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LENGTH
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UJIN5TALL TWO CONNECTOR MOUNTING
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PART NUMflfR
'I13254-COOI
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OF
MATEPIAl
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CAB.E ASSY,EIA/ACCUSTIC COUPLER
ITEM.
QUANTITY.
COMPONf~T
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232113-u075
••
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DESCRIPTION ••••••••••••••••••••••••••••• UM
~CUSING CCNN.PC 10 DUAL PDS
AHP-582963-2
PI
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P13
AMP-2C5208-1
~DOD ASSY W/HARDWARE
AMP-205718
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CONTACT PIN .062 OIA
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CONNECTOR RCPT 25PINS RACK & PANEL
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Pllt
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CC~TACT.SOCKET 24-20AWG .06210
AMP-205201-3
leST PRCC.DITI'CO-EIA COUP INTPF UBLE
CABLE BRACKET
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STRAP STANDARD BUNDLE DIA 0 TO 1-3/4 IN
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PC CARD ASSEMBLY DRAWINGS
Title
Printer Control
Transmit/Receive, Baudot
Transmit/Receive, ASCII
Printer Code, ASCII
Printer Code, Baudot, U.S.
Printhead Interface
Regulator/Amplifier (lOA)
Control Regulator (lOA)
Terminal Control, ASR
Display (dual cassette)
Power Module Motherboard
ASR Module Assembly Motherboard
TTY Interface, Polar
TTY Interfac.e, Neutral
TTY Interface, Computer
Terminal Control, KSR
Cassette Transport
Answer-Back Memory
Remote Device Control
Auto-Answer Control
Modem, ATL
Modem, ATL-2
Modem, ATH
*Auto Device Control
Remote Cassette Control
Record Buffer Control, 300 baud
Record Buffer Control, Baudot
Playback Control
Motion Control
Record Control
Tape Read/Write Control
Dual Format, Record Buffer
Receiver, 1200 Baud
Transmitter, 1200 Baud
Dual Format Read/Write Control
Dual Format Playback Control
t;> Dual Format ASCII Transmit/Receive
Regulator/ Amplifier (14A)
Control Regulator (14A)
Auto Device Control
Remote Device Control
Auto Search Control
Remote Device Control
1200 Dual Format Transmit/Receive
Receiver, 1200 Baud
(,
(
*Obsolete
TI Drawing Number
959131
959133
959135
959137-0001
959137-0002
959141
959143
959145
959147
959155
959157
959159
959171-0001
959171-0002
959171-0003
959173
960080
960881
960169
960885
960887-0001
960887-0002
960887-0003
960891
960901
960903-0001
960903-0002
960905 ,- :;:;.960907
960909
962281
962285
962291
962293
969451
969453
969455
971443
971450
971481
971483
971485,493
973901
973905
973907
,~
~.
~
2
4
HOTEl
"\ II)
\
{!:I
REMOVE RZO TO DIYBl,.E END
ALARM. SEE "VIEW A~
or
LINE
UNLC:;S OTHERWise SPECIFtI;O
II DO MOT CLINCH COMPONENT LEADS
21 DO NOT SOLDER ON COMPONENT SIDE
R2f>,R27,Rza,C 2~(104 NOT UUD.
31 HASIt ALL CONNECTOR FINGERS ON 80TH
SIDES OF aOARD WHEN SOLDERING TO
PUVENl SOLDER FROM WIClING DOWN
CONNEcTOR FINGERS
101 EJECTORS flTEMS.3 AND 4, ARE TO 8E
INSTALLED AFTER WAVE SOLDERING
SI MAXIMUM COMPONENT HEIGHT FROM
COMPONENT SLOE OF aOARD IS .375
61 MAlUNUM lEAD LENGTH FROM CONDUCTOR
lZ> ;;;~7t";;;,; /;;2,S 8E
3
T(J
"
2~u
.•
SOl.OER~
ON
D RIO WAS Ra. Aa WAS RIO
LM, I) ITEM SOA ADO RIC. 2) IrE'1Y\
""A
"'DOC'" 3)ITCM3/A ~·oDR/O
4) IrEM '~A ADO R47 S) I r~M 47A I4DD
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OOOD, PE~ 2boooo.f2 .25"""
R~ wA:.s R4? .11) .IrF~'" 41 "
0000, I?,$ 12/000..12 .25"'" 1"41.... Re;o WAS .e/(P IS) IrEM of4 Qr,
""""5 2
/~) ITEM. '17 qTY WAS.I
16) ITEM So QTY ',../J'~ 1 .17) IT"EMS3
Qr, \.VAS.3 /8)/"T"I!M 5G QrY \.vA ~ .".
~/rEH se wAS 2gc7.1~-oOQ:S CAP 2·PMF Ie
201,.110"'- 20) IrEI"'\ seA R3D WAS Cl4
2.I)/~.I"'\ 64 tilTI' WAS 2
Z?).ITEM 170
.y WAS 0
Z'3)/TEM.3SA DEL#78-h
ITEM "'6A DE,LET~ RS9 2S) .ITE""
DFLC,E R30J .er;D 2~/TE"'S6A
R.lo
IrEM ?O'" DS,LErE
INSTI9lL.£O AFT'£"1f WArE St:N..PC1,
TO Pl'fEI'£NT DAM/I6E TO .sWlrCH~
S(}LDEIP W/TH l£VER IN ""SlrION
SNIJ"'N BELOIVr
.5"
I
PoSITltJNZ
r-'U-,
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VIEW A
5C.ALE: IIOIIE
~
....
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2V
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~ove~RER
22,
PART NUMBH
~.59131-0001
1974
REV
W
l
I
S T
o F
"
ATE II I A l
/"
DESCRIPTION •••••••••••••••••••••••••••••
BOARO ASSY.PRINTER CCNTROl
ITEM.
QUANTITY.
CO"PONENT ••
DESCRIPTION ••••••••••••••••••••••••••••• UM
oooi
00001.000
959130-11001
0003
00001.000
2318(2-11009
PRIN1E.D WIRING BD,PRIN1ER CONTPOl
1209-9130-000
EJECTOR
WHT 8-200
0-000
RI?D 8-200
EJEC1CR
SCA-8-200 COil
5.60 UH .13 OHMS
lOll
Mll-MS905/t2-1/t
II
MIl-MS905'12-1/t
hE1WCRK SN7/t00N
3-000
l10 Zl8 l25
3-000
IIETWORK SN7/t02N
1I--SN1402N
Zl3 216 In l24 Z30 l33
li-- SN7/t02N
N.ETWORK SN7403N
C004
00001.000
231802-11002
0006
00001.000
418093-11010
00003.000
222222-7400
00006;000
222222-1402
00001.000
222222-7403
0006A
0008
0008A
0009
0009A
0010
0010A
0011
00002.000
222222-7"04
222222-1"09
NETWCRK-SN7It09N
00002.0uO
222222-/410
IliETWCRK
00001.000
222222-1413
00002.000
222222-7"27
2'00000-7454
NETWORK-SN7"H5"N
00CC2.000
222222-74H
IIETWCPK
00002.000
222222-7'197
SN7"7"N
3-000
NETWO~K
3-000
SN7't97N
00001.000
222222-1121
NETWORK
00001.000
222222-1161
hETWCRK SI'000
00001.000
2336<; 8-u 000
oooel.OOO
233438-')00C
00004.000
233667-11000
00002.000
233156-0COO
00013.000
233869-1)000
00002.000
2330;60-0000
000C4.000
2310153-11000
00001.000
234313-11000
00001.000
234471-')000
00001.000
233311-11000
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UNLESS OTHERWISE InCIFIEO
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22. 1974
PART NUM8ER
~591~~-OOOl
ITEM.
REV
W
QUANTITY.
l
DfS~RIPTICN
J S T
o F
"'ATE~IAl
•••••••••••••••••••••••••••••
REG~lATOR/A~PlIFIER
CO'1pnNE,H ••
DESCRIPTION ••••••••••••••••••••••••••••• UM
PRT.WIRING BD.,PEGUlATOR/AMPlIFIER
1209-911i2-000
EJfCTOR
PEo 8-200
SCA-8-200
EJECTOR
GPY 8-200
SCA-8-200
HEATS INK TRANSISTOR TO-5
~~~-~F-207
'119-368-0002
05820
eRACKET,TRANSISTOR ~TG
1209-'131'1-015
paD I~TEGPATEo CKT.TO-5 8 lEA05 .3~0 OIA
0001
000Cl.000
<;59142-... 001
C003
00001.000
231802-0002
C004
00001.000
2318C2-JoC8
COOS
000C1.000
2320~7-uOC2
0007
000e2.000
959319-uOOl
0008
00003.000
232583-U005
EA
EA
EA
e.
EA
EA
THP-7717-107-N-~1
0009
00018.000
232583-0008
0010
000C4.00C
185113-,,001
PAD
XST "TG TO-5 IoHT
THR-7717-4N
SPACE!>
XST TC-18 CASE
EA
COll
00001.000
230e26-~001
*cap
EA
OOCCl.OOO
230455-50CO
00002.000
230482-~004
00001.000
23058B-UCOO
00011.000
230587-u055
00001.000
230716-0003
000C4.000
535227-0031
0012A
0013
COllA
0016
0016A
0011
OOl7A
aoue
(
OOle
0018A
0019
10~
CASE SIZE e
Cll
OOlU
0012
39.000 MF 10V
MIl-C S138C396K
EA
MIl-CS 13BC396K
CAP 47C.00
PF
200V
lC~
"1l-CK05BX41lK
C6
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CAP
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ZOOV
1(*
"1l-CK05BXl02K
C4,C7
I'll-CK058XI02K
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CAP 2.200 MF 20V -10.~ CASE SIZE A
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CAPACITOR 2.2 MF 125V lO~
EA
EA
EA
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EA
SP~-1500225X9125B2
0019A
0022
00001.000
53'l721-uOOl
00005.COO
231702-0CC2
00CC7.000
53QS13-0001
00003.000
233151-~000
000e7.000
233'21-~OOO
OOCCI.OOO
234C61-JOOO
000(7.000
233397-JOOC
0022A
0024
0024A
0026
0026A
OOUA
ce2C;
0029A
0031
00318
00l2A
0033
0033A
0033R
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SAN-556EJ1CIW065B
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SAN-556EJIOIII0658
CICDE IN~14B
3-COO
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3-000
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TRw-asp 5101
PES 2.70CC
OHM
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AS -CR21G5
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RES 5600.0
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C1)'1 P(l'lE,~ T ••
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0034
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23341S-UOOO
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003S
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00358
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00001.000
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233S29-u004
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00001.000
23344l-uOOO
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2200.00
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5~
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AB -CII2225
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RES 4.7000
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RES 100.CC
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0048
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0049
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0049A
0050
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0051
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0052A
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5.
fA
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AB -f!l6eI5
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SF.f- TI DRAWING
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SEE- TI DRAWING
RESISTOR,FIXED,WIREWCUNO .5 OHM :w IS
SH- TI DRAW ING
AIP2 A2P2 0)0
SEE- T I DP AW ING
P~SISTOP,FIXEO,WIPEWOUND 7.5 O~M 7W l'
S"~- Tl DRAWING
A2Pl 1'31
SEE- TI O~AWING
RfSISTOR,FlxED,wIPEWC~~O 30 OH~ 7h It
SEF- TI ORAWING
AlRl AIP20
SE~- TI DRAWING
~ETWOPK
SN1418N
EA
EA
FA
AllL A2Z1
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959143-3
(
NOVEMBER 22. 1914
PART NUMBER
REV
W
~59143-0001
LIS T
OFS~R[PTION
o
F
MATERI.AL
•••••••••••••••••••••••••••••
~EGJLA1CQ/A~PLIFIEP
ITEM.
OUANTllY.
COMPONE,H ••
DESCRIPlION ••••••••••••••••••••••••••••• UM
C057
00001.000
236C82-v002
00001.000
236C67-vOOl
000e8.000
236C61-JC01
TR~NSISTOR
2N2905A
418-535-00C4 QPL19500
011
418-535-0004 OPL19500
TRANSISTOR 2N22226
418-338-0004 gPL19500
06
418-338-0004 QPL19500
XST
2N2102
-2N211J2
0057A
n056
00586
fA
FA
0059~
07.~1~3.AZC3.A1Q6.AZQ6.A1Q9
C05CJB
-2N2102
AZC9.C13
-Z>l710Z
C06C
000e7.000
958759-J003
0060A
000e2.000
236e71-u002
00616
0063
0064
AR
2~1143-J001
COC01.000
537399-v012
00001.000
231S2B-JIOC
00001.000
959335-JOOI
C064A
0065
0065~
0067
0067~
C068
SOA TfSTED
EA
AIQ1.~2Ql.A1Q4.A2Q4.AIQ7.A2Q7
'lr)6'lB
0061
XST TIP 358
TI -TlP35B
TI -T IP358
e12
TI -TIP3~R
TR6NSISTnR 2N23696
3-000
AlOle A2010
3-000
CCMP(UND T~EP~AL
WAK--120-B nz
fUSE 5~MP .014 OH~
LtT-276005
F1
l tT-276005
FUSE
I A~P Pice 27bOOl.
LIT-276001.
F2
LIT-276001.
I~CUCTO~.5V PfGULATOP
FA
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EA
EA
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ooon.ooo
23lC38-... 036
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0071
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234E66-Jl0C
C072
ooen.ooc
216399-vOOO
C073
000C1.000
235C54-vCOt
INDIJCTOR 10.0 UH
.9 OHM 10.
OEL-1537-36
L2
CEL-1537-36
FLSE 3AMP
L IT-276C03
A1fl 42Fl
Lt T-27b003
SFAl~NT LOCTITE GRADE C BLUE
lCC-84
RING 0 7132Xll/32H/16
P-K-2-009-N219-7
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6-32X3/8 8~ SST
0074
000C3.000
2363e6-JCOO
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235r24-w002
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0076
00009.000
236374-,,000
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EA
C078
oooel.(,OO
959254- ... eOI
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0079
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235023-uC20
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1209-9254-C07
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0080
DIAGR~~.LOGIC.DETAILEO.REG/A~FLIFIER
EA
0082
236377-... 000
WASHER #4 fLT .125 X .312 SST
95920~-'1901
pOOG"AM
0068A
0069
0069A
0070
AR
00ce8.000
235182-J002
.6 EXT TeOTH LOCK SST
-'6 4-40X5/16
fA
T'l
EA
EA
AH SST
-'4
EA
-#4 FLn
0083
REF
EA
TEST.RfG/A~P
C084
ooce7.000
23~452-u000
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0~85
00004.000
232451-JOCC
roUT
4-40 NYLON
EA
C086
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FA
0087
1209-9316-016
SCPFW.N4 X .235 X .75
EA
0')88
JOOe1.COO
'ln76C-JOC7
959143-4
IIIP BPS
NP
~~S
~aVE~BfR
22, 10;14
PART NUMBER
<;59143-00ll1
RFV
\0
lIS T
DFS~RIP~ION
(
MATEOIAl
F
~-
•••••••••••••••••••••••••••••
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ITEM.
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CO~PONE~T
••
DESCPIPfION ••••••••••••••••••••••••••••• UM
C08q
00001.000
912162-uOC7
NUT ,I-EX-N6 X 5/16 X .114
(090
00004.000
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co'n
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0092
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DEVICE
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959143-5
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NOTES- U....ESS OTH(lWI8£ SPEaFIED
II DO NOT ct..NtH COMPONENT LEADS.
~~K ~m:'E~~'p~RGo~ivt-lEtV~tP~&.~ lATE
21 MASK ALL CONNEtTOR FINGERS ON 80TH
SiftS OF IOARD WtEII SOLDER_ TO
PREYENT SOL.DER FROM W'CKING DOWN
CONNECTOR FIUERS.
3J E.lECTOR' (ITEMS Z AND
3'
ARE TO 8E
INSTALLED .tITEIL PROCESS I
41 MAXIMUM COMPOtCENT HEiGIIT FROM
GIN(E
SEE
CQMPONENt SIDE OF 80ARD IS . 8,,"0
51 MAXIMUM LEAD LEMGTH FROM CONDUtTOR
SIDE OF 10ARD II .062.
1Il 101A.1UMUM [OWjPOaJEtJT HEM FROM
fOUDUCT'Ot SID! OF a.OAltD IS .425
1\ I~STALL T"~SlST•• S DIR.CTLYON
"EATS,,,. . . . 0 UOT US" IIfSULAT'~G
WASHeR.
>OKMAL
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RES 6800.':>
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088
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089
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236386-':>000
090
001
236052- 0000
HF
9591d2-9901
092
REF
959210-9901
PROGRAM TE ST ,CONTROL/REGULATOR
093
001
230613-0000
CAP
O'JOA
091
LEAD SllE.018-.040TIIli
AMP-380635-2
SCREW 4-40Xl/4 BH SST
~cCFPTACLE,ACCEpTS
wA SHER #4 EXT TH SST
-#4
SCRtOw
6-32 Xl/4 BH SST
wASHER
#6 EXT TOOTH LOCK SST
-#6
TRANSI STOR 21111711
418-288-0001 QPL1S500
Q21
418-288-0001 CPll <;500
DIAGRAM,LOGIC,DET~ILED.CONTROL/REGULATOR
.1000
Mf
35V 10
SPR-15DDID4X9035A~
09JA
094
liD 1
234328-0000
001
233418-0000
001
972224-0001
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096
096A
097
0'l7A
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SPR-150DI04X9D35A2
RES 33000.
OHM
.25W 5.
AB -C83335
R67
AB -C83335
RES 82.000
OHM
.25W 5.
AB -CB8205
R13
AB -CB8205
TRANSISTOR 2N222a SELEC TED
1209-2224-000
w20
1209-2224-000
959145-5
2
4
NOlES, UMLESS OTHERWISE SPECIFIEO
n
DO NOT CLINCH COMPONENT LEADS
21 00 NOT SOLDER ON COMPONENT SIDE
lJ "'ASK ALL CONNECTOR FINGERS ON 80TH
SIDES OF BOARD WHEN SOLDEflING TO
PREVENT SOLDER FROH WICKING DOWN
CONNECTOR FINGERS
""",,6ffllllT£ /r£V L£7TER
HEV/$I#N LE.VEL &tJCK
A
.1 E.JECTORS IiTEMS 2 AND '"
ARE TO 8E
INSTALLED AFTER WAVE SOLDERING
51 MAXIMUM COMPONENT HEIGHT FROM
COMPONENT SIDE Of 80ARO IS .375
61 MAlIMUN LEAD lENGTH FRO'" CONDUCTOR
sIDE OF BOARO IS .062
B
-0
-0
(J1
.....
~
.....
o
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NOVf'HlK J,.
1973
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tu'lilil'IENT ••
2 :laO" 7.,0,100
UESC:< IPTION ••••••••••••••••••••••••••••• \JM
TRANSISTi)l<
21112222
418-338-JD02 QPL19500
cJll
0:)4,1\
~18-338-0U02
Ou4!
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2341')6-0 Du
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TI-lR-771 7-4N
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12(H-142o-010
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1209-142()-010
(-
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959171-6
2
4
NOTES
.;;.,
UNLESS OTHERWISE SPEC1FIEtI
'~1'-72.
n DO NOT CLINCH COMPONENT LEADS
21 DO NOT SOLDER ON COMPONENT SIDE
.11 I'IA511' ALL CO/liNECTOR FINGERS ON 80TH
SIDES OF BOARD
WH~N
SOLDERING TO
PREVENT SOI.,OER FRO,", WICKING DOWN
CONNECTOR FINGERS
A
41 EJEtTORS IHEMS 2 AND
,.
41 ARe TO BE
INSTALLEO AFTER WAVE SOLDERING
51 MAXIMUM COMPONENT HEIGHT FROM
COMPONun SIDE OF !lOUe IS • .37,5
2.
61 MAXIMUM LEAD LENGTH FROM CONDUCTOR
SIDE OF
. ll; ~'
>~) !jJ, i:
·
~I:"
r;!!."'
1r--40
_
~
'81
I
_
,
BOARD IS .06l
E
11,
I(~~~~~W ~~~E~EL \~~1t1/'li7'
FJ 391559 [EY1=2S-14
\~~
PDAT£D REVISION LEVEL BLOC\:. ,zoNE 0-1
3Slb700(D)~'UJ~ 8'f4-=!4jl/I'l/1'1R:±
A
Z REQD
7J
2 R[QO
;1:)
L£TTER PER
(FAR SIDE)
REVISION
NOTE$: UNLESS OTHERWise SPECIFIED
/. DO NOT CLINCH COltlPON£lI/r L£ADS
2. MASX ALL CONNECTOR FINGeRS ON
BOTH SIO£S OF' BOARD WHEN
SOLDE~JNG
70 PA-EVENT SOLDER
FRQM WIC!(ING DOWN CONNECTOJlf
FINGER.S
3. MAX,IMUM COMPONENT HEIGHT FROM
COMPONENT $10£ OF BCARD IS
.480
4. MAXIMVM J.EAD LENGTH FIi(OM
f2--...CONDIJCrOR SIDE OF SOARD IS .D75
L.!--INITALL A~nfl FLOW SDLlMR
[j;:
•
a 1
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FOff'NlIIL fi'£L£IIS£
I'"
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ON -0002 AS5V REMOVE -0001 FROM
BOARD AND INK IN .OOOZ. RI!MOYe ~8Z
FROM MARD AND lNI4. IN 911,,.,'51.
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J'.Jt,Ja, J4,J7,
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OMITTED FOR
'82)
CLARITY
JIZ,..J/~
:E~L.~l:~D
TPI~I.1'P2~2:"P'!tE.-S
!Jj.....~(.r~ ",,·15 ~
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_
ll~Gifiiii01
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;:; ,.R'IVI D WIRIIV6 IIOAR
~ 4OQ/C DIAGRAM FOR
~
-0001 A$$£MBLY
I..
n WAVE
:.'..J"I
1(11./)£14
j;;"'ZtelNJt1.t1R )
~) ~<.:l1~R S"~MP.
~dL~~ ':£~'VK,,*i
t,.EVEL
---.L
:Z6
..
lIlT
ltf~lOd.o
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BLOCK.
~Jt..r
O-f
_
IIII""EI-I"'LS
"10
i D 1'I.O~31
TRANSI'OR'T,
7IANSPOR
ASSEMBLY
LM_
(
~OVF"I\EP
22, 1974
PART NUMBER
%0080-0001
R~V
o
F
14 ATE R I
A L
•••••••••••••••••••••••••••••
OES~RIPTION
CAS~ETTE TPANSPORT,PIIB
ASSY
ITEM.
QUANTI TY.
COMPONE.n ••
OESCPIPTI(~
0001
OOOCl.OOO
960C81-... 001
PIIB,CASSETTE TRANSPORT
1209-0CIII-COO
EA
0002
00e02.000
S6C 41 0-... 001
HEATSI~~
EA
0005
00oe2.eoo
233153-uCOO
00002.000
2336C2- ... 000
000e2.000
233446->/000
0005A
0006
C006A
00C8
0008A
0009
0010
000e2.000
233151- .. COC
00001.000
233545-11000
COOO1.('00
233437-11002
00C02.000
23372 3-<1 000
COO(<;.OOO
233156-Oa0-2
EA
EA
EA
EA
EA
EA
EA
MlVEM8ER 22. 1914
PART NUMBER
960080-0001
REV
R
L I
S T
C F
MilT E II I A L
•••••••••••••••••••••••••••••
DES~RIPTION
CIIS~ETTE TRANSPORT.PIIB
',--
IISSY
HEM.
QU".,TIlY.
COMPONENT ••
DESCRIPTION ••••••••••••••••••••••••••••• UM
0026
00tC2.00O
234349-.)003
OHI'
.2511
TT-"C5~D4022F
01295
116e 1118
53'1-370-0539
01295
OHM
RES
33000.
.2511 5.
A8 -C83335
R16 1I~1 R3l:
AB -CB'I335
OHM
RES 41000.
• 2511 5 •
118 -(fl4735
1174 1116
AB -CB4735
RES 75000.
OHM
.2511
5.111
AI! -(87535
1119 IIZ4
A8 -C87535
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AS -(8-1555
III
U -CP.-1555
OHM
liES 130COO.
• 2511 5 •
AB -(fl1345
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Ae -CII1345
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.2511 5.
lIB -C81545
1143 1145
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1.0000 M-OHM
.2511 5.
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II~ 114 1126
Ae -CBI055
CAP 33.0 PF
200V
10. I
Mll-CK05BX330K
C23
"1l-CK058.33OK
CAP
220.0 PF 200V
10 MIL-(ttC58X221K
419-198-0221
95275
C34
419-198-0221
95215
CAP
.0010 MF
200Y
1~1
Io1ll-CK058U02K
C13
I'1l-CK058XI02K
CAP
.0033 MF
200Y
+C~-lO:l
Mll-CK068X332K
CZC;
" Il-CI(OeBX332K
cap 0.1('00 MF 100V 10. I
MlL-CK068XI04K
C4 C5 CI0 C12 C15 (19 C22 C24
" IL-CK068Xl04K
C28 C~l C33 C35 C3f C37 C3B
Io1IL-CK06BXI04K
C3CJ
I'1l-(K06BXI04K
CAP
.4"100 MF
50Y
+011-201
ERI-B133000l5U0474M
C16
ERI-8133000Z5U0474M
CAP .4"100 MF 35V 101 CASE SIZE-A
MIl-CS138F474K
C6
MIL-CSl!Bf474K
CAP 4.100 MF 10V 10111 CASE SHE A
1'1 L -C S13I1C475K
C1
MIl-CS1'3BC4"f5K
CAP 1.000 I'F 35Y 10111 CASE SIZE A
Mll-CS13BFI05K
C8 CC; Cll C21
I'1l-CSI38FI05K
CAP 6.800 ~F 35V 10:1 CASE Sill:' B
Mll-CS13BF685K
C 17 C!'2
IlHl-CS13BFf>85K
CAP 47.000 MF 20V 10:1 CAH SIZE C
MIl-CS13BI:476K
Cl C2 C3
"1l-CS13BE476K
RES 40200.
539-370':'0~39
0026A
0027
00003.000
234328-~000
00002.000
234366-\1000
000C2.000
Z34~2e-uOC5
00001.000
234681-uOOO
OOC01.0eo
2345C4-UOOO
00002.000
234512-,)000
00003.000
234661-UOOO
00001.000
2l0389-~.00C
00001.000
2300]-il500
00001.('00
23048241004
0021A
0028
002BA
0029
0029"
0030
0030.
0031
COllA
0032
0032 A
0034
0034A
0035
0035A
0036
0036A
0031
003U
0038
00001.000
230512-0010
OODU.OOO
230618-11100
00001.000
Z30659-ill00
00001.000
230658-JCOl
00COl.000
2J0143-uOOO
OOCC4.000
230686-UOCO
00002.000
230760-\1000
OOOO~.COO
230836-1)003
0038A
0039
0039A
003'le
0039C
(040
0040_
0041
0041A
0042
0042'
0043
C0434
0044
0044A
0045
0045.
960080-3
n
U
EA
EA
EA
EA
EA
Ell
EA
EA
E·A
/-
EA
"EA
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EA
EA
EA
EA
EA
EA
(
NOVE~8EP
22, 1974
NU'4BfR
960080-0001
PA~T
REV
R
liS T
o
F
MATERIAL
DESCRIPTICN •••••••••••••••••••••••••••••
C4S,;FTTE TRANSPOP.T, PW8 ASSY
ITEM.
QUANTITY.
COMPONENT ••
OF.SCPIPTION ••••••••••••••••••••••••••••• UM
0048
00030.000
231702-0002
0 roOF
0048A
00488
00(09
00001.000
231765-~000
0050
00003.000
236017-0000
ooSl
00004.000
236Ce2-1)002
00006.000
236083-<1001
000e8.000
236C67-0001
0000".000
235~68-0001
00001.000
2361C8-0088
0049A
OOSU
00S2
0052A
0053
0053A
DOS 38
0054
0054A
0055
0057
0058
REF
960082-9901
00001.000
53799S-~001
00011.000
222224-~01lNETWORK
00CC3.000
222222-1426
OEl-1537-3C
NETWOPK MC4044P
MOT-MC4044P
IIOT-I'C4044P
lM30lAN
-lM30lAN
ARI THRU ARll
-l"30lAN
NETWOPK SN7426N
-SN1426N
fA
EA
EA
EA
EA
I:A
OPEJilAllON-Al A"P
EA
EA
ze
-SN7426N
SN7400N
3-000
000Cl.000
222222-1"00
~eTWORK
00001.000
222222-1474
NETWOJIIK
00001.000
222222-1416
EA
l6
Z5
0064A
0065
INDUCTOR 5.60 UH .32 OHM 10
DEl-I537-30
Z2 Z7
0063A
0064
fA
Z3
0062A
0063
EA
I I l2 L3
006011
0062
EA
3-000
OIAGRA",lOGIC-OETA(lED.CASSETTE XPCRT
231C38-0030
00S9A
0060
EA
T~RU
00003.000
005U
0059
IN9148
3-000
CP8 CR11 THRU CR30
3-000
CA33,CR34
3-000
DIODE
IN4002
"OT-1N4002
CR9
"OT-IN4002
TAANSISTOR,2N930
418-130-0002 OPl19500
07 Qll 014
418-130-0002 OPl19S00
TUNS IS10R 2N2905A
418-S35-0004 OPl19500
01 02 026 '27
418-535-0004 OPl19500
lRA.NS (STOA 2N2907A
418-404-0004 OPL19500
03 OS 09 010 012 015
418-404-0004 OPll9500
TRANSISTOR 2N2222A
418-338-0004 OPLl9500
08 017 G19 022 e23 024 025
418-338-00C4 OPLI9500
028
418-338-0004 QPl19500
itSl
TlP3lA
TI -31A
I: 13 1:16 018 020
TJ -31A
liST N-CHNl PLNR SILICON- (WAS 1IS-88)
3-000
CRI
0065A
3-000
SN7474N
3-000
3-000
NETWOAK S N7416N
-SN7ltI6N
EA
Zl
185113-uOOl
-SNHH>N
PAD
. XST "TG TO-5 WHT
THJII-7717-4N
SPACER
XST TO-18 CASE
EA
00004.000
235C54-0014
*SCJIIEW
-
Ell
0067
00004.000
232583-0008
0068
00020.000
0069
0070
000C4.000
23638S-~000
0071
00004.000
2!63e6-~OCO
6-32X3/8 RH NYLONSMI-252,.
WASHER
t6 FlT S5 1/32 THK
-'6 flAT
WASHER
'6 EXT TOOTH LOCK SST
0012
00C04.000
232,.55-a000
N~T
0073
000e4.000
95877o-uOOI
INSUlATOR,KAPTON PLASTIC TO-66
-'66-32X5l16X7/64
9600804
lHK SST
EA
EA
EA
EA
EA
NGVE~8ER
22,
PART NUM8ER
960080-0001
lIS T
197~
REV
p
0 .F
MAT E R·I A l
DESCRIPTION •••••••••••••••••••••••••••••
CASSETTE TRANSPORT,PW8 'SSY
ITEM.
QUANTITY.
COMPONeNT..
DeSCRIPTION ••••••••••••••• ;•••••••••••••• UM
C014
00000.000
712696-,)001
HADER-36 PI NS 3.600 LG
8EJ-65,274-1
MAY 8E USED AS AN ALTEANATE
8E1-65274-1
FOR. ITEM 80 81 82
8E1-6S214-1
RES 150.00
OHM
.25W 5.
A8 -C81!515
Ina
Aa -C81S15
CAP .02000 MF 25" 8C/-20 •
Elt 1-5835Y5U2 031
C14,C18
ER 1-5835Y5U2031
RES 39000.
OHM
• 25W 5 •
AB -C83935
A25
AS -CB3935
HUJER- 2 PI NS .200 LG
AN -0002363
J5 J6 J8 J9 J14 J15
AN -00023E3
I;EADEA- 3 PINS .300 LG
RN -000236/0
JI J2 J3 J4 JI0 Jll J12 J13
AN· -000236/0
J7
AN -0002364
HEADER- 1 PINS .100 LG
RN -0002/031
TPlEl TP2E2 TP3E3
AN -0002431
0014.
0074B
0075
00001.COO· 233484-0000
0015A
0076
00002.000
230561-';000
00001.000
234344-uOOO
000C6.000
712696-';009
00009.000
172696-0010
00003.000
712696-0008
007U
0077
0077A
0080
0080A
0081
OOBU
0081B
0082
0082A
960080-5
EA
EA
EA
EA
EA
EA
EA
.~
.~
~
2
4
NOTES: UNLESS OTHERWISE SPECIFIED
II DO NOT CLINCH COMPONENT LE.&OS
21 DO HOT SOLDER ON COMPONENT SIDE
31 "'",SI( ALL CONNlCTOR FINGERS ON eOTH
SIDES OF IOARD WHEN SOLDERING TO
PREVENT SOLDER FROM WICKING DOWN
CONNECTOR FINGERS
., EJECTORS IITEMS Z AND 31 ARE TO BE
A
A
INSTALLED AFTER WAVE SOLOElilING
PR.OC.C$S 1 DO NOT 'iU&MEItioE
11'-- A.FTER
V - "~(PENell
[!:::>
r;--
4PLA"&S
~
I!:>
SWITC.H)
RIO IN!>iALl.ED IN tt.~i:PTAC.LE BY
P~E$S FIT, PO NOT SOLPE"IZ.
ITt:M U (~"41"wl NOT USED ON
-0001, -0005 A.6SEM8L1ES
ITEM 28 (RE'i.IO.JL,.Z6W, S%,RZO
R'2.~.i"R24)"'Ile.NOTUSe-O ON
_0001 TMIlU -00040 A'!oo;;,EM8ueg,
[!> 1~::':L~~h~~~~'~~~~';E1 TO
P!f,eV&NT DAMA&E • 'iOLPEIl WIT\ot
LeVER IN PO'EoITIONS, 'il-lOWN
&EL.OW
1.
SOLPER~
B
~"'L.E'
0
COIoAPONENT
'OIPE
B
\0
0-
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0-
'P
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_JQ.~s
.....x
MAX
MARK APPROPP.IATE DASH NO
LEVel PE.II.
!lOO &AUD A.A CODE
1.EM00e l)e'ICE COMT.
~OO
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9G.O'Go9 -0005
9601Gt9-0004
REMOT£ oeVIc.e (OWT.
!l00 8AUD AA. NO PIZ.QM
REMOTG DeVICE CONT.
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REMOTE PE.VICE CONT.
9G.OIGoCit-0002
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f\
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9(,O,tittJ - 0007
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LOGIC DIAGRAM Fall: -0001 THII.U -0008 AfJRf
ASSEMBLY
.'149S~99ol'
-:.
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9~09"12.
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....
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DATE
LIST o. MATERIAL
03/2A173
PAGE 1
of
rlLM 9b01h'l-OCCI
,AlTNUM8£t
3
DESCRIPTION
pwa REMOTE DtVICE LONTROL
PART NUMBER
~hC' 1&8-0001
)!)~J
1. J)u
tA
u.,)Oz
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l(JR
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6-200
Se4-8-200
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222222-7402
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222222-7403
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RE l,RS6
A e -CB2225
RES
15000.
OHM
• 25\01
5•
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Re4,R94,R95
AB -C81535
RES
27000.
OHM
• 25\01
5•
AB -C82735
R31,RI05
A8 -C82735
RES
41.000
O~M
• 25\01
5•
A6 -C64105
R41
Ae -C64105
RES
82.0eo
OHM
• 25\01
5•
AB -CB8205
R40,P46,P71
AB ,..C68205
RES
24000.
ORM
• 25W
5•
AB -CB2435
R45,R 50
AB -C82435
PES
3920.0
OHM
.125\01
1.
Tl -"'C55C-T2-50PPM/C
R43
Tl -MC55C-T2-50PPM/C
RES
10COO.00
OHM
.25W
5~
AB -CBI035
0004A
0005
0005A
0006
0006,6
0001
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0008
0008A
0009
0009A
0010
0010,6
0011
001H
0011
001U
0012
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000(6.000
233'932-JOOO
00003.000
23'o017-uOOO
0,0001.000
233B50-1I000
000e2.000
234061-UOOO
00001.000
234696-IJOOI
00003.000
23'0;48-110(8
00002.000
2'34417-1.1030
0014,6
0015
0015,6
0016
001U
0017
0017A
0018
0018A
0019
C019A
0020
0020.11
fA
EA
Ell
EA
fA
EA
EA
EA
EA
EA
EA
EA
Rl.~60,R62,R65,P66,R67.R75.
0012B
0014
fA
AB -(61035
R'l9
AB -C61035
RES
OHM
2100.C
.25\01
5.
AB -CB2725
R54,R63,R38.RI01,RI03,R29
A6 -CB2125
RES
4700.00
OHM
.25\01
5%
AB -CB4125
R68,R92,R5
A8 -ce4725
RES
1800.0
OHM
.25\01
5.
AB -C81825
P64
AB -C1I1825
RES
5600.0
OHM
.25\01
5.
.lie -CB5625
R5€,R74
AB -C85625
RES
2.2000 "-CHM
.2511
5.
A8 -CB2255
!l89
AB -C82,255
RES
15.000 M-OH"
.25\01 5.
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P55,R93,R98
AB -C81565
OHM
RES 100000.
.2511
5.
A8 -C81045
R57 PI00
AB -CI:II045
960887-4
EA
EA
EA
EA
EA
EA
EA
~OVEM!\FP
PA~T
22, 1974
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lIS T
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MATERIAL
•••••••••••••••••••••••••••••
MaOI:~,Hl
CO'PONEMT ••
0021
OESCPIPTICN ••••••••••••••••••••••••••••• UM
5.6~-CH~
PES
A~
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AS -C85655
RES '810.
539-310-0465
C021~
0022
.25~
5.~
EA
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P~8,P90
0023
539-310-0465
PES 15~0.0
OH~
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1~
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EA
5.
EA
0129S
~12'l5
.25W
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P 4," 17
00002.000
233123-vOOO
RES
~e
0025A
0026
00002.000
233397-JCOO
000e2.000
233E50-JCOC
AB -CBA2l5
RES 68.0eo
AB -CR6SCS
A8 -CB68I)S
470.00
RES
000C2.000
234261-1100
RES
TI
OOCCl.rco
233~36-~~'l9
C02'lA
C02'l
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539370-J424
00eOl.000
233942-J400
00001.000
233954-uC~2
COCCI.roo
233~27-.!550
00((2.000
539311-0490
0030~
0031
003H
0032
0032A
0032
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53q371-J461
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234223-JOIA
0033A
0034A
0035
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5.
EA
OHM
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5.
EA
20COO.
OHM
.13 W
1.'
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-~C55C-T2-50PPM/C
RE'l,R70
TI -MC5SC-1Z-50PPM/C
RES,274C.
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.25h
539-310-0421
01295
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EA
539-370-0427
2550.
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01295
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1~
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EA
TI -MC550-TI-100PPM/C
RES 2870.
OHM .25~ 1~
539-370-0429
01295
R12
539-370-0429
01295
RES 3C90.
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539-370-0432
01295
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53~-370-0432
01295
RES 2550.C
OH~
.125W
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RF.S 12400.
OHM
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TI-MC~5C2E71F
EA
TI-~C55C3C91F
E~
1.
EA
It
EA
T I -I'C55C-T2-50PPM/C
7150. OHM .125W 1.~·
T 1 -I'C5 5C-T2-50 PPM/C
R47,R49
1 I -MC55C-T2-50PPM/C
PES 10000.
O~M
.125W 1~
Tl - "C5 5C- T2 -50PPH/C
R2
TI -MC55C-T2-S0PPM/C
RES 15CCO.00 CHI'
.125W
TI -MC55C-T2-50PPM/C
RES
EA
EA
1.~
EA
R42,~44,R3
00001.000
233904-~261
00001.000
234255-J910
0035A
0036
.25W
R47,R4~
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OHM
1111
0030A
0030
EA
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511:
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R34,R35
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R'52,~91
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0027
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820.00
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AP
0025
TI -MC55C-T2-50PPM/C
RfS.2260.0
OHM .25"
539-370-0419
01295
P13
539-370-0419
01Z95
RES 165CO.
OHM .25k
539-370-0502
01295
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539-370-0502
01295
(
960887-5
1~
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EA
1~
TI-~C!5CI652F
EA
WVEI'BEP 22, 1974
PAIH NUMBER
.960S1I7-0001
REV
E
L I S T
QUANTITY.
COMPONEI'!T ••
0037
00001.000
2343"09-u002
00001.000
j!33659-9999
0031'
003SA
0039
00003.000
539311-1146<;
00,OC1.000
539371-"'462
00001.000
234(75-;)900
00e01.COO
234139-1400
00002.000
234510-j001
00001.000
234469-,)010
00001.000
2H605-jOOC
OOOCl.COO
539371-.!42!
00001.000
539371-"'''30
C040A
0041
C04lA
0042
0042A
0043
0043A
0()1t4
0044 A
0045
00.. 5A
0046
0046A
0046
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00"7
00001.000
231t101-1>000
00001.000
539371-0456
OOitU
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00..,7 A
00.48
00.001.000.
231t01lt-yOOO
0.00.01.000
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0.048
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0049
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539311-0486
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00.51
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DESCRJPTION.~ •••• ~ •••••••••••••••••••••• UM
RES 2S000.
OHM .25" ur
539-310-0524
01295
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5'39-310-0524
01295
PES 4'l9.0
.251; 11
Oli~
539-370-0356
01295
TI-I'C !~02eC2F
EA
Tt -ftC ~ !04fJ90F
EA
539-370-0356
01295
RES 7500. OIiM .12511 1.1
TI -MC55C-T2-50PPM/C
R43,nS,RSC
TI -MC55C-T2-50PPM/C
liES t340. Oil .. .125" 1.1
TI -MC55C-T2-50PPM/C
tI19
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RfS Hge.
OHM
.12511
1.1
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1148
Tl -MC55C-T2-50PPMIt
RES 9530.0 OHM
.12511.
1.1
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1182
T I -PlC55C-T2-'50PPM/I:
RES 141:000. OHI' .25M 11 rI-IIC55DI473F
539-370-059.3
01295
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539-370"';0593
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RES 93100.
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539-370-0574
01295
R19
539-370-0574
01295
RES 464000. OHM .375M
11
Tt ~MC600-100PPM/C
R21
TI -MC6CD-I00PPli/C
RES 2800.
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.12511
11
TI -MC55C-T2-50PPM/C
1186
TI -MC55C-T2-5DPPMIC
liES 2940.
OHM
U
.12511
TI -MC55C-T2-50PPM/C
1186
T I -MC55C-T2-50PPM/C
RES 1320.0 OHM
1.1
.125"
TI -MC55C-T2-50PPMIt
IIS3
TI -MC55C~T2~50PPM/C
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1183
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.125"
TI -MC55C~T2-50~PM/C
1151
TI -MC55C-TZ-50PPM/C
RES '1990.
OHIO ~25W 11 TI-I'C !!D.,C;91F
01295
539-370-0"52
EA
EA
EA
EA
EA
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EA
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,/
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"
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fA
EA
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012.95
539-370.-0"52
OHIO
.12511
PES 11300.
11
TI,-MC55C-T2-5QPPM/C
118
TI.-MC55C-T2-50PPM/C
.125 W 1.:1
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TI -MC55C-TZ-50PPM/r
EA
EA
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539371"';u525
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RES 28100..
OHM
.I25W
TI -MC55C-T2-50PPM/C
1'72
T I ·-IIC55C-T2-50PPM/C
liES 17400.
OHM .25M III
539-370-0501t
01295
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1173
539-370.-050'1
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960887-6
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MATERIAL
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53q371-~428
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232e14-~004
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TI-MC~5C3162F
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PES 2800.
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.125W
T 1 -MC55C-12 -50PPM/C
P6,RI0
TI -MC55C-12-50PPM/C
PES VAP. 5~ 3069P-I-502
80U-3069P-1-502
I!
fA
FA
R9
0055A
0055
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P6,P10
0054A
0055
PES 26100.
O~~
.25W
TI -~C55D-TI-100PP~/C
R73
TI -~C55D-TI-IOOPPM/C
RES 31600.
OHM .25W l~
539-370-0529
01295
pe7
539-370-0529
01295
RES Ih900.
OHM
.25W
TI -MC55D-Tl-100PPM/C
P87
TI -~C55n-ll-l00PPM/C
RES 4870.
OHM
.125W
TI -MC55C-T2-50PPM/C
0055A
BOU-3069P-I-502
RES VAil 10~ MINIATURE
BOU-.3069P-1-103
P9
fA
~OU-3069P-1-103
0056
0056A
0057
00001.000
232799-u100
oooel.coo
232787-J60C
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0051
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230385-9CCO
00001.000
18423O-u044
00010.000
535997-Q015
C0002.000
184230-u045
000C3.000
nosce-vOC4
00C02.000
230527-~5CO
0064
00001.000
5071t3-~002
0064
00001.000
507163-uOOI
0058A
00588
0059
0059A
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0060B
0061
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0062
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BGU-3C69P-1-203
R53,R56,1176
BOU-3069P-1- 203
PES VAP. 2K 3C69P-I-202
BCU-]fJ69P-I-202
R1
80U-3069P-I-202
liES VAP. U
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BOU-3069P-1-102
EA
EA
P7
00010.000
0058
HS
0062A
BOU-3069P-I-102
OP 27.00
PF lOGV 10
MIl-C~05~X270K
Cl,C1,CI3,(12,CI5,C24,C29,
~ Il-CK05BX270K
C41,C42,C38
M Il-CK05BX270K
CAPACITOR 0.047
MF
-PER TI ORAWING
C9
-PER TI ORAW ING
CAP FIX MET POlYCARB .010 MF 1~
lQW- X463UW
CII,(20,('I,C22,C25,C26,C27,
TPW- X463UW
(28 04 C23
TRW- X4BUW
(APAC ITOI' 0.100
MF
-PFR TI DRAW ING
(10,C35
-PER TI OPAWING
CAP
.0022 MF
200V
lC:C
MIl-CKOI>BX222K
(17,Ol,C43
fA
EA
50VDCW
fA
EA
fA
"1L-CI(06~X2221(
0063
0063A
0064A
CAP .00500( MF 1000V GMV
410-529-0502
715QO
C 18,( 1<)
410-529-0502
71590
CAP
.033 ~F 50V
5~
TPW-X663F
(30
1PW-X663F
CAP
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5~
nW-X663F
C30
TRW-Xl>63F
960887-7
(Rl-OO-50z
EA
fA
EA
~nVE~8ER
22, 1914
PIIRT NUMBEP
960887-0001
REV
E
lIS T
o
F
MATEIIIAl
OESCRIPT1CN •••••••••••••••••••••••••••••
MOOE~,IITL
ITEM.
QUANTI TV.
COM PONEilT ••
OESCRIPTIQN ••••••••••••••••••••••••• ~ ••• UM
0065
00002.000
535997-0021
ooce2.roo
B0482-w004
00001.000
535991-0020
00002.000
535997-0029
00001.000
230E36-0003
OOCCI.COO
23~128-0002
CAPACITOR .03300 "F 50V 1.';
nW-X463UW
C37,C40
TRII-X463UW
CAP
.0010 MF
ZCOV
101
MIl-CK05BXI02K
C32.C33
I!1l-CK05BXI02K
CAP"FIX "'ET POLYCARB .027 ~F II 50VOCW
TRW- X463UW
CII
TRW- lC4E3UII
CAP FIX MET POlYCARB .120 MF l ' 50VOCW
TRII- X463UW
C36.C39
TIIII- X463UW '
CliP 41.000 MF 20V 10'; CASf SlZE C
"'1l-CS138E416K
C44
"'ll-CS138E416K
CAP 3.300 "F 15V 10'; CASE SIZE A
0065.1
0066
0066A
0061
0061.1
006!!
006U
0069
0069A
0010
EA
EA
EA
EA
EA
EA
MIl-CSl~BD335K
C070.l
0071
00002.000
230500-0001
OOOC2.000
230516-0001
00(2<;.000
230618-.1100
000C2.000
230E77-000'l
00002.000
2308C8-0000
000e2.(\CO
231038-.1092
00002.000
23103.8-11036
00012.000
2317C2-u002
007lA
0071
0071 A
0072
007211
00728
0013
0073.
0074
0014.
0075
0015.1
0076
0016.1
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00002.000
231168-!i806
00001.000
2317E4-o001
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244541-11001
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24e490-!i245
3-000
CRl3 CR16 Cllte CR1t; CR20 CR3
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DIODE "'PD300 3 PEllET SILICON "'''lTI
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CRll
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DieDE ASSY,ZENER,MATc .. eo PAIR IN152A
1210-4541-C29
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(CR14&CRI51ICR4&CR5)
1210-4547..,029
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00001.000
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0080
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84411
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419-051-0222
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CAP 0.1000 ~F 100V 10.';
Mll-CK06BX104K
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MIl-CI(06BXI04K
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MIL-CS13BEI011<
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Mtl-CS13BElD1K
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Mll-CS138D2261<
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MIL-CS13802261<
I~OUCTC~ 220. UH 7.2 0 .... 05.
DEl-1537-92
l3,l4
DEl-1531-92
INOUCTOIl 10.0 UH
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DEl-1537-36
ll,l2
DEl-1531-:U
CIODE IN914B
3-000
419-051-~222
EA
EA
EA
EA
fA
EA
EA
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0017A
0078
C2
MIl-CS13BD335K
CAP .002200 MF
EA
EA
EA
EA
0083.1
0084
0084A
05
960887-8
EA
(
~(1Vf~AEP
22, 1914
PART NUMBFR
G60BA7-0001
REV
E
LIS T
OES~RIPTION
ITEM.
QUANTITY.
CO~~ONE~T
000·'5.000
236CS-h)001
0086
00001.000
236C11-u002
0087
00001.000
236C67-JOOl
00001.000
222225-J311
••
0085A
0087A
0088
OOOH.OOO
22222lt-JOI0
000Cl.000
772~CO-uOOl
00898
q089C
0090A
DESCRlpTICh ••••••••••••••••••••••••••••• UM
TRANSISTOR 2N2907A
418-~04-00C4 Opl19500
04,06,010,'11,012
418-4C4-0004 Opl19500
T~ANSISTOR
2N2369A
3-000
09
3-[00
TRANSISTOP 2N2222A
418-338-0004 OPL19500
01
418-338-0<104 CPLl 9500
NETWOPK l~311H
FlI
EA
Ell
EA
NETWORK l"30lAH
OPERATIONAL A~P
-LM30lAH
AP1,AR3.AR4,AP5,AR6,AR1.AR8.
-LM30lAH
AR10.AR11.AR12.AR13,AR14.
-LM30lAH
AR15,AR16
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TRANSFORMER.AUOIO ISlN 600CT/6CO(T I'PO
HL-LJOll
0096
OOOC~.OOO
195113-J001
HL-lJOll
JaCK.Tlp 8LACK
EFJ-105-853
TP1 J 1
EFJ-I05-853
JACK TIP WHITE
EFJ-105-851
1t19-916-'0001
TP2 J2
419-916-0001
JACK TIP RfO
EFJ-105-852
419-916-0002
TP3 J3
419-916-0002
PAD INTEGRATED CKT.TO-5 8 LEAOS .!50 DIA
THR-1'1'-107-N-WHT
RES 39200.
OH' .25W IS· TI-~C!!03922F
539-370-05"38
0129.5
R39
539-370-0538
01295
SPACER
XS~ TO-18 CASE
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418-338-0004 QPL19500
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971443-0001
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USER'S CRITIQUE
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