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•
•
SYSTEM 80/10
MICROCOMPUTER
HARDWARE REFERENCE MANUAL

•

Manual Order Number: 9800316B

•
•
•

•

•

Copyright © 1976, 1977 Intel Corporation
Intel Corporation. 3065 Bowers Avenue. Santa Clara. California 95051

I

The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this
material, including, but not limited to, the implied warranties of
merchantability and fitness for a particular purpose.
document.

•

Intel in this

Intel Corporation makes no commitment to update nor to keep

current the information contained in this document.

•
•

No part of this document may be copied or reproduced in any form or by
any means without the prior written consent of Intel Corporation.
The following are trademarks of Intel Corporation and may be used only
to describe Intel products:
ICE-30

MCS

ICE-80

MEGACHASSIS

INSITE

MICROMAP

INTEL

MULTIBUS

INTELLEC

PROMPT

LIBRARY MANAGER

UPI
RMX

•
•
•
•

•

ii

•

•

PREFACE
This manual provides general information, installation, programming
information, principles of operation, and service information for the
Intel System 80/10 Microcomputer using either the SBC 80/10 or the

•

SBC 80/10A.

Unless specified otherwise references to the System 80/10

are valid for both Single Board Computers.
occur are identified individually.

The areas where differences

Additional systems information and

component part details are available in the following documents:

•

o

Part No.
o

98-414

Intel 8080 Microcomputer Systems User's Manual,
Part No.

o

•

Intel Microcomputer Systems Data Book,

98-153

Intel Mu1tibus Interfacing Application Note,
AP-28

o

Intel 8255 Programmable Peripheral Interface Application Note,
AP-15

o

Intel 8251 Universal Synchronous/Asynchronous Receiver/Transmitter
Application Note,

•

AP-16

•

•

iii

TABLE OF CONTENTS
TITLE

CHAPTER
1.0

PAGE NO.

INTRODUCTION • • •

1-1

1.1
1.2
1.3

1-1
1-2
1-4

8080A ARCHITECTURE
SYSTEM ORGANIZATION.
SYSTEM MONITOR

2.0

SYSTEM OVERVIEW

• • • .

3.0

SBC 80/10 AND 80/10A MODULE

•
•

. • 2-1
•

.• 3-1

3.1

FUNCTIONAL ORGANIZATION OF THE SBC 80/10 AND
SBC 80/10A MODULE • • • • • • • • •
......• •
3.2 THEORY OF OPERATION. . • • • . . .
.
3.2.1 THE CPU SET • • • • . . • • . • • • •
3.2.1.1 INSTRUCTION TIMING . . • • •
3.2.1.2 INTERRUPT SEQUENCES
3.2.1.3 HOLD SEQUENCES • .
.
3.2.1.4 HALT SEQUENCES • . .
. •
3.2.1.5 START-UP SEQUENCE. •
3.2.2 SYSTEM BUS INTERFACE LOGIC . . . . . . . • . . .
3.2.2.1 SYSTEM CONTROL SIGNAL LOGIC.
. •.
3.2.2.2 SYSTEM BUS DRIVERS
..
3.2.2.3 FAILSAFE TIMER
• • • •
•
3.2.3 RANDOM ACCESS MEMORY. • .•
•••• •
•
3.2.3.1 SBC 80/10 RAM . • .
.
3.2.3.2 SBC 80/10A RAM • • •
• • • ••
3.2.4 READ-ONLY-MEMORY (ROM/PROM)
3.2.5 SERIAL I/O INTERFACE. • . • • .
. .....
3.2.5.1 INTEL 8251 OPERATIONAL SUMMARY
.
3.2.5.2 SERIAL I/O CONFIGURATIONS.
3.2.5.3 BAUD RATE CLOCK GENERATION • • •
3.2.5.4 SERIAL I/O INTERRUPTS. . . • .
3.2.6 PARALLEL I/O INTERFACE. • . • . • • • • .
3.2.6.1 INTEL 8255 OPERATIONAL SUMMARY
.•
3.2.6.2 PARALLEL I/O CONFIGURATIONS . • • • . •
3.3 USER SELECTABLE OPTIONS . . • • • • • • • • • • •
3.3.1 SERIAL I/O INTERFACE OPTIONS. • • • • • ••
3.3.1.1 INTERFACE TYPE . • . • • • . • . • • .
3.3.1.2 BAUD RATE AND PROGRAM-SELECTABLE
SERIAL I/O OPTIONS
. •
3.3.2 PARALLEL I/O OPTIONS • • • • . . . . . . . . . .
3.3.2.1 PORT 1 (GROUP 1 PORT A) . . . • . . . .
3.3.2.2 PORT 2 (GROUP 2 PORT B) . . . • . . . •
3.3.2.3 PORT 3 (Group 1 PORT C) . . . . . • . .
3.3.2.4 PORT 4 AND 5 (GROUP 2 PORTS A AND B) .•
3.3.2.5 PORT 6 (GROUP 2 PORT C) . . . . . . . .
3.3.3 GENERAL OPTIONS • • • . • • • . . . . . . . . .
3.3.3.1 SYSTEM RESET OUTPUT. • . .
.
3.3.3.2 DISABLE BUS CLOCK SIGNALS. .
. •
3.3.3.3 ADVANCED ACKNOWLEDGE INPUT . . . . . .
3.3.4 DEFAULT OPTIONS • • • • . • . . . .
.
3.3.5 JUMPER CONFIGURATION FOR ROM/PROM INSTALLATION.
iv

3-1
3-3
3-4
3-4
3-13
3-14
3-14
3-15
3-15
3-16
3-18
3-20
3-20
3-21
3-22
3-23
3-25
3-25
3-36
3-38
3-39
3-40
3-40
3-53
3-59
3-59
3-60
3-60
3-63
3-66
3-72
3-74
3-75
3-78
3-82
3-82
3-82
3-82
3-82
3-83

•
•
•
•

•

•

•

TITLE

CHAPTER
4.0

FRONT PANEL
4. 1

4.2

..

5.0

5.2

•

6. 1

•
6.3

6.4
6.5
7.0

•

4-1
· 4-1
5-1

FUNCTIONAL ORGANIZATION OF THE CARDCAGE AND BACKPLANE
ASSEMBLY
5-1
CARDCAGE AND BACKPLANE ASSEMBLY UTILIZATION.
· 5-1

FUNCTIONAL ORGANIZATION OF THE POWER SUPPLY
THEORY OF OPERATION . . . . . . . .
6.2.1 5V, 14 A OUTPUT . . . . . . . .
6.2.1.1 VOLTAGE REGULATION
6.2.1.2 CURRENT LIMIT/FOLDBACK
6.2.1.3 OVP OPERATION.
6.2.2 +12V OPERATION . . . . . . . . .
6.2.2.1 REGULATION . . • . • .
6.2.2.2 CURRENT LIMIT/FOLDBACK
6.2.2.3 OVP OPERATION
6.2.3 -12V OPERATION . . . .
6.2.3.1 REGULATION
6.2.3.2 CURRENT LIMIT
6.2.3.3 OVP . . . .
6.2.4 -5V OPERATION . . . . .
6.2.4.1 REGULATION
6.2.4.2 CURRENT LIMIT.
6.2.4.3 OVP . . • .
6.2.5 POWER FAIL OPERATION.
DC POWER OUTPUTS . . . . . .
6.3.1 DC OUTPUT VOLTAGE ADJUSTMENT
6.3.2 OVER-VOLTAGE-PROTECTION CIRCUIT RESET
PROCEDURE
AC LOW DETECTION CIRCUIT CONNECTIONS
MODIFICATION PROCEDURE FOR 230V OPERATION

6-1
· 6-1
6-1
· 6-1
· 6-1
· 6-2
6-3
• 6-3
· 6-3
6-3
6-3
· 6-3
· 6-4
6-4
6-4
6-4
6-4
6-4
• 6-4
· 6-4
6-5
• • 6-5
6-6
6-6
· 6-7

SYSTEM MONITOR . . . . . . . . . . . .
7. 1

•

AC POWER SWITCH
SYSTEM RESET SWITCH .

POWER SUPPLY . . . . . . . . . . . . . . . . . .
6.2

•

· 4-1

CARDCAGE AND BACKPLANE ASSEMBLY
5.1

6.0

PAGE NO.

MONITOR FUNCTIONAL SPECIFICATION
·
7.1.1 GENERAL CHARACTERISTICS AND SCOPE
7.1.2 DESCRIPTION OF ALL MAJOR FUNCTIONS PERFORMED
7. 1 . 2. 1 CONSOLE COMMANDS . • • . . . . . .
•
7.1.2.2 USE OF THE MONITOR FOR PROGRAMMING AND
CHECKOUT
7.1.2.3 I/O SYSTEM
7.1.3 APPLICABLE STANDARDS
•

v

7-1
7-1
7-1
7-1
7-1
7-2
7-2
7-2

TITLE

CHAPTER
7.2

PAGE NO.

MONITOR INTERFACE SPECIFICATIONS
...
7.2.1 COMMAND STRUCTURE • . • . • . . •
. ••
7.2.1.1 DISPLAY MEMORY COMMAND, D
.•
7.2.1.2 PROGRAM EXECUTE COMMAND, G
.•.
7.2.1.3 INSERT INSTRUCTIONS INTO MEMORY, I .•
7.2.1.4 MOVE MEMORY COMMAND, M • ••
• ••
7.2.1.5 READ HEXADECIMAL FILE, R • • • • • . •
7.2.1.6 SUBSTITUTE MEMORY COMMAND, S
7.2.1.7 WRITE HEXADECIMAL FILE, W • • • .•
.
7.2.1.8 EXAMINE AND MODIFY CPU REGISTERS
COMMAND, X
. . . • •
. .
7.2.2 DEVICE DRIVERS . . • • . . .
• • •
7.2.3 USING THE I/O SYSTEM. • •
7.3 MONITOR OPERATING SPECIFICATIONS
.
7.3.1 PRODUCT ACTIVATION INSTRUCTIONS
.
7.3.1.1 COLD START PROCEDURE
••
7.3.1.2 USE OF RAM STORAGE IN THE MONITOR •••
7.3.2 ERROR CONDITIONS. . . . • . .
.
7.3.2.1 INVALID CHARACTERS
..•
7.3.2.2 ADDRESS VALUE ERRORS
7.3.2.3 PERIPHERAL DEVICE ERRORS
..
7.3.3 HEXADECIMAL OBJECT FILE FORMAT FOR PAPER TAPE
7.4 HARDWARE GENERATED BREAKPOINTS
. . • •
.

8.0

SYSTEM UTILIZATION • . • . .
8.1

8.2
9.0

SYSTEM I/O INTERFACING
8.1.1 ELECTRICAL CONNECTIONS
8.1.2 EXTERNAL SYSTEM BUS SUMMARY
8.1.3 RS232C CABLING . . • . . .
TELETYPEWRITER MODIFICATIONS

INTERFACING TO MULTIBUS MASTER . .

7-3
7-3
7-3
7-4
7-4
7-5
7-6
7-6
7-7
7-7
7-8
7-9
7-11
7-11
7-11
7-11
7-11
7-11
7-12
7-12
7-12
7-15

· 8-1
. . . 8-1
. . . . 8-1

. . • 8-7
8-9
· 8-11
· 9-1

APPENDICES
APPENDIX
A

TITLE

A.5
B

•
•

•
•
•

PAGE NO.

•

SYSTEM SPECIFICATIONS
A.1
A.2
A.3
A.4

•

• . A-l

GENERAL SYSTEM SPECIFICATIONS . . . . • • • . • • •
· A-2
SBC 80/10 AND SBC 80/10A SPECIFICATIONS •.
. . A-9
POWER SUPPLY SPECIFICATIONS . . . . . .
A-19
SBC 604 MODULAR CARDCAGE AND BACKPLANE ASSEMBLY
SPECIFICATIONS • . . • . . . . . • . • . . • • .
· A-22
SBC 901/902 TERMINATION RESISTOR PLACES
A-23

SYSTEM 80/10 SCHEMATICS
vi

B-1

•

•

•
•

C

•
•

•

PAGE NO.

SYSTEM AND SUB-ASSEMBLY OUTLINES • • . . • • •
C.1
C.2
C.3
C.4

SYSTEM 80/10 OUTLINE • • • • • • • • .
SBC 80/10 AND SBC 80/10A BOARD OUTLINE
MODULAR CARDCAGE OUTLINE • • • • • • • •
POWER SUPPLY OUTLINE DRAWING FOR vic AA

D

8080 INSTRUCTION SET SUMMARY • •

E

SBC 80P MONITOR PROGRAM LISTING

F

ASCII TABLE

G

BINARY-DECIMAL-HEXADECIMAL CONVERSION TABLES .

H

TELETYPEWRITER MODE

• C-1
• C-1
. . . . . . C-2

C-4
• • • C-5
• • D-1
• E-1

• • • • • • • • • •

• • F-1

• • • • • • . • • • • •

G-1
• • H-1

LIST OF ILLUSTRATIONS
FIGURE

•

TITLE

APPENDIX

TITLE

2-1

SYSTEM 80/10 BLOCK DIAGRAM

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10

SBC 80/10 FUNCTIONAL BLOCK DIAGRAM.
THE CPU SET • • • • • • • •
TYPICAL FETCH MACHINE CYCLE
.
INPUT INSTRUCTION CYCLE
• • • •
OUTPUT INSTRUCTION CYCLE •
READY TIMING • • • • • • • • • • • •
RAM ACCESS TIMING • • .
8251 PIN ASSIGNMENTS . • •
TYPICAL. 8251 DATA BLOCK
• •
ASYNCH~ONOUS MODE
• • • • • • • •
SYNCHRONOUS MODE • • • • ••
••
COMMAND INSTRUCTION FORMAT • • • • •
STATUS READ FORMAT • • • • •
8255 P]N ASSIGNMENTS • • • • • • • •
MODE DEFINITION CONTROL WORD FORMAT
BIT SET/RESET CONTROL WORD FORMAT
8255 MaDE 0 TIMING • • • • • • •
EXAMPLES OF MODE 0 CONFIGURATION
MODE 1 lNPUT CONFIGURATION • • • • •
8255 MODE 1 INPUT TIMING • • •
MODE 1 iOUTPUT CONFIGURATION
MODE 1 BASIC OUTPUT TIMING • • • • •

3-11

3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22

vii

PAGE NO.
• • • 2-3
•

• • • • •
• • • • • •
• . •
•
• • • • • • • ••
•
• • • • • • •
• • • • • • • •
• • . • • • •
• •
• • • • • • • •
• • • • • • • • • • • •
• •
• • • • • ••
•••
• •
• •
• • • • • • •
••••
•
• • • • •
• • • • •
• • • •
• •
••••
• •
• • •
• • •
• • • •
• •
•
• • • • •

3-2
3-5
3-8
3-11
3-12
3-19
3-24
3-26
3-30
3-32
3-32
3-33
3-34
3-42
3-42
3-43
3-45
3-45
3-47
3-47
3-48
3-48

PAGE NO.

TITLE

FIGURE

· • 3-50
3-51
· • • • 3-64
· • • • 3-65

3-23
3-24
3-25
3-26

MODE 2 PORT CONFIGURATION
MODE 2 TIMING . . • .
ASYNCHRONOUS OPERATION
SYNCHRONOUS OPERATION

4-1

SYSTEM RESET SWITCH

6-1
6-2
6-3
6-4
6-5

OUTPUT POWER CONNECTIONS .
AC LOW DETECTION CIRCUIT CONNECTIONS • • .
TYPICAL POWER FAIL SEQUENCE
215v CONNECTION
lOOv CONNECTION

8-1
8-2

TERMINATION PACK SCHEMATICS
SBC-80/l0 EDGE CONNECTORS

9-1

SERIAL PRIORITY CONFIGURATION WITH SBC 80/10 AND ANOTHER
MULTIBUS MASTER • . . . . . • . .
. . . . . •

9-2

A-I
A-2
A-3
A-4
A-5
A-6

MEMORY AND I/O READ TIMING (CONTINUOUS BUS CONTROL)
MEMORY AND I/O WRITE TIMING (CONTINUOUS BUS CONTROL)
BUS EXCHANGE (WRITE) • . . .
.•..
•
SBC 604 DIMENSIONS . . . . •
• •
SBC 901 TERMINATOR SCHEMATIC •
SBC 902 TERMINATOR SCHEMATIC •

A-16
A-17
A-18
A-22
A-24
A-25

B-1
B-2
B-3
B-4
B-5

AC/DC POWER DISTRIBUTION DIAGRAM
SBC 80/10 SCHEMATIC
SBC 80/10A SCHEMATIC . . . . . .
POWER SUPPLY SCHEMATIC . . . . . .
TERMINATION BACKPLANE SCHEMATIC

C-l
C-2
C-3
C-4

SYSTEM 80/10 OUTLINE . . . . . .
SBC 80/10 AND SBC 80/l0A BOARD OUTLINE
MODULAR CARDCAGE OUTLINE . . . . . . .
POWER SUPPLY OUTLINE DRAWING FOR vic AA

H-l
H-2
H-3
H-4
H-5
H-6
H-7
H-8

TELETYPE COMPONENT LAYOUT
CURRENT SOURCE RESISTOR
TERMINAL BLOCK . . . . • . .
TELETYPWRITER MODIFICATIONS
RELAY CIRCUIT . . . . .
MODE SWITCH . . • . . .
DISTRIBUTOR TRIP MAGNET
TTY ADAPTER CABLING

.

· 4-2

viii

·
• • •
• • •
• •
· •

•

6-5
6-6
6-8
6-10
6-10

• • 8-3
· . . . 8-4

.•••
•
.
• • . .
•.
.
. .

•

· . B-2
B-3
B-8
B-13
• B-14
C-l
· C-2
C-4
• C-5
·
·
• • •
·
. . .

H-2
H-2
H-2
H-3
H-3
H-3
· . H-4

. . .. . H-4

•
•
•
•

•

•
•

•
•
•
..
•

LIST OF TABLES
PAGE NO.

i

3-33
3-34
3-35
3-36

SERIAL ~OMMUNICATION (8251) ADDRESS ASSIGNMENTS
· .
8255 MofiE DEFINITION SUMMARY . . . . • • . • • •
•
8255 BASIC OPERATION . • . • .
• . • • • •
PARALLEL I/O PORT ADDRESSES
. . • •
· .
PORT 6 I/O CONFIGURATION . . .
20 rnA CURRENT LOOP SERIAL I/O INTERFACE
· .
RS232C +NTERFACE, "DATA SET" ROLE
• . . •
RS232C ~. NTERFACE, "DATA PROCESSING TERMINAL" ROLE
BAUD RA E SELECTION • • • . . . . . • • • •
•
PORT 1 PERATING MODES . . . . . . • . . . .
•
PORT 1, i MODE 0 INPUT CONFIGURATION . . . • .
•
PORT 1, MODE 0 LATCHED OUTPUT CONFIGURATION
PORT 1, MODE 1 STROBED INPUT CONFIGURATION.
· .
PORT 1, MODE 1 LATCHED OUTPUT CONFIGURATION
•••..
PORT 1,t'MODE 2 BIDIRECTIONAL CONFIGURATION.
· •
PORT 2 PERATING MODES . . • . . • • . . . .
• ••
PORT 2, MODE
INPUT CONFIGURATION . • • . •
·
PORT 2, MODE
LATCHED OUTPUT CONFIGURATION
PORT 2, 'MODE 1 STROBED INPUT CONFIGURATION.
• •
PORT 2, MODE 1 LATCHED OUTPUT CONFIGURATION • • • • .
•
PORT 4 AND 5 OPERATING MODES
...•.•••
PORT 3, MODE 0, 8-BIT INPUT CONFIGURATION •
·
PORT 3, MODE 0, 8-BIT LATCHED OUTPUT CONFIGURATION
PORT 4'lMODE 0, INPUT CONFIGURATION . . . . . . .
•
PORT 4, MODE 0 LATCHED OUTPUT CONFIGURATION.
.
PORT 5, MODE 0 INPUT CONFIGURATION . . . . . . . .
·
PORT 5, MODE 0 LATCHED OUTPUT CONFIGURATION . . .
•
PORT 6 . PERATING MODES . • . • . • . . . . .
.
•
PORT 6,' MODE 0, 8-BIT INPUT CONFIGURATION . . . .
.••
PORT 6, MODE 0, 8-BIT LATCHED OUTPUT CONFIGURATION •
PORT 6, MODE 0 UPPER 4-BIT INPUT/LOWER 4-BIT LATCHED
OUTPUT CONFIGURATION • • . . . . . . . . • • . • • • .
PORT 6"MODE
UPPER 4-BIT LATCHED OUTPUT/LOWER 4-BIT
INPUT CpNFIGURATION . • . . . • . • . . . • • . . . .
·
PARALLEf I/O ADDRESS AND SOCKET ASSIGNMENTS . . . . .
·
DEFAUL~~PTION OF THE SBC 80/10
...•...••..
•
PROM JUMPER CONFIGURATION • . . . . . . . . . . . • .
·
PROM ADDRESSES • • . • . . . . .
.••...• .

6-1

OPTIONAL TRANSFORMER CONNECTIONS .

8-1

PIN ASS~' GNMENTS FOR CONNECTOR Jl
(PARALL L I/O INTERFACE - GROUP 1)
PIN ASS GNMENTS FOR CONNECTOR J2
(PARALL~L I/O INTERFACE - GROUP 2)
PIN ASS1GNMENTS FOR CONNECTOR J3
(SERIAL I/O INTERFACE) . . . • •
PIN ASSIGNMENTS FOR CONNECTOR P2
(AUXILIARY CONNECTOR) . . . . . .

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11

3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23

3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32

8-2

•

TITLE

TABLE

8-3

8-4

°

°

°

I

ix

3-37
3-52
3-54
3-54
3-58
3-61
3-62
3-62
3-66
3-67
3-68
3-68
3-69
3-70
3-71
3-72

3-72
3-73
3-73
3-74
3-75
3-75
3-76
3-76
3-77

3-77
3-78
3-78
:3-79
3-79
3-80
3-80
3-81
3-83

3-84
3-84

· 6-9
. . 8-3
. • 8-5
8-6
. ••• 8-7

TABLE
8-5

8-6

A-I
A-2
A-3
A-4

A-5
A-6
A-7
A-8
A-9
A-IO
A-ll

TITLE
PIN ASSIGNMENTS FOR CONNECTOR PI
(SYSTEM BUS) . • • • • . . . • •
J3/RS232C CONNECTOR PIN CORRESPONDENCE

PAGE NO.

· • • 8-10
· 8-11

INPUT/OUTPUT PORT MODES OF OPERATION •
·
DC POWER REQUIREMENTS . • • . . . . .
AC CHARACTERISTICS (WITH BUS EXCHANGE) .
• . • . •
AC CHARACTERISTICS (WITH CONTINUOUS BUS CONTROL) .
·
DC CHARACTERISTICS • . . . . • • . . . . • • • •
SBC BOARDS COMPATIBLE CONNECTOR HARDWARE •
• •
NOMINAL DC VOLTAGE . • . • . . .
•
CURRENT LIMIT AND OVP PROTECTION
TTL "AC LOW" SIGNAL
• . • •
• • •
AC INPUT .
• • •
DC OUTPUT . . • . •
•

A-3
A-9
A-IO

•
•

A-ll

A-12
A-14

A-19
A-19
A-20
A-20
A-21

•
•
•
•

x

•

CHAPTER 1

•

INTRODUCTION
The System 80/10 is a member of Intel's complete line of OEM Computer
I

systems that take full advantage of Intel's LSI technology to provide
I

•

economical computer solutions for OEM applications.

The System 80/10 is

a completely pacWaged, self-contained computer system in a compact 3.5
inch high, 19 in9h wide RETMA compatible chassis.

The CPU, system clock,

read/write memor~, non-volatile read-only-memory, parallel I/O ports and
drivers, serial communications interface, system backplane, power supply,
fans, and OEM front panel are all included in one slim-line chassis.

•

Throughout JhiS manual references to the system 80/10 are valid for
systems using eiJher the SBC 80/10 or the SBC 80/l0A.

Areas where dif-

ferences occur are identified as SBC 80/10 only and SBC 80/l0A only.
A Single Board Computer, the SBC 80/10 or the SBC 80/l0A, provides
the processing

p~wer for the System 80/10.

The System has expansion

capacity for an ~dditional three expansion boards inside the System chassis.

•

Intel's powerful 8-bit n-channel MOS 8080A CPU, fabricated on a single
LST chip, is the central processor for the System 80/10.
six general purptse registers and an accumulator.

The 8080A contains

The six general purpose

registers may be ,addressed individually or in pairs providing both single
and double precision operators.

The 8080A has a 16-bit program counter

which allows direct addressing of up to 64K bytes of memory, and the
System 80/10 can1be expanded with standard expansion boards to utilize up

•

to 53K words of the addressing space.
any portion of

m~mory,

An external stack, located within

may be used as a last-in first-out stack to store

and retrieve the! contents of the program counter, flags, accumulator and all
of the six general purpose registers.
the addressing of this external stack.
subroutine nestifg.
busses are used

•

fO

A sixteen bit stack pointer controls
This stack provides almost unlimited

Sixteen line address and eight line bidirectional data
facilitate easy interface to memory and I/O.

I

1.1

I

8080A ARCHITECTURE
The powerful 8080A instruction set allows the user to write efficient

•

programs in a mifimum amount of time.

The accumulator group instructions

include arithmetlc and logical operators with direct, register indirect,
1-1

and immediate addressing modes.

Move, load, and store instruction groups

provide the ability to move either 8 or 16 bits of data between memory,
the six working registers and the accumulator using all addressing modes.
The ability to branch to different portions of a program is provided
with jump, jump conditional, and computer jumps.

The ability to condition-

ally and unconditionally call to and return from subroutines is provided.

•
.

The RESTART (or single byte call instruction) is used for interrupt operation.

Double precision operators such as stack manipulation and double

add instructions extend both the arithmetic and interrupt handling capability of the 8080A.

The ability to increment and decrement memory, the

six general registers and the accumulator is provided as well as extended
increment and decrement instructions to operate on the register pairs and
stack pointer.
1.2

SYSTEM ORGANIZATION

•

The System 80/10 may contain either an SBC 80/10 or an SBC 80/l0A,
depending on date of manufacture.

The only difference is in the type and

quantity of memory available on each board.
The System 80/10 with the SBC 80/10 contains lK 8-bits words of read/
write memory using Intel's 8111 Low Power Static RAMs.

Sockets for up to

4K 8-bit words of non-volatile read-only memory may be added in lK byte

•

increments using Intel's 8708 Erasable and Electrically Reprogrammable
ROM's (EPROMs) or Intel's 8308 Metal Masked ROMs.
The System 80/10 with the SBC 80/l0A contains IK 8-bit words of read/
write memory using Intel's 8102 Low Power Static RAMs.

Sockets for up

to 4K or 8K words of non-volatile read-only memory are provided on the
SBC 80/l0A.

Up to 4K words of read-only memory may be added in lK byte

•

increments using Intel's 8708 erasable and electrically reprogrammable
ROMs (EPROMs), Intel's 2758 Erasable and Electrically Reprogrmrumable ROMs
(EPROMs), or Intel's 8308 Metal Mask ROMs.

•

Optionally up to 8K words of

read-only memory may be added in 2K byte increments using Intel's 2716
Erasable and Electrically Reprogrammable ROMs (EPROMs) or Intel's 83l6E

•

Metal Masked ROMs.

1-2

•

•

The System 80/10 contains 48 programmable parallel Input/Output (I/O)
lines implemented using two Intel 8255 Programmable Peripheral Interface
devices.

The software is used to configure the I/O lines in combinations

of unidirectional input/output, and bidirectional ports.

Therefore, the

I/O interface may be customized to meet specified peripheral requirements
•

in order to take full advantage of the large number of possible I/O line
drivers and terminators.

Hence, the flexibility of the I/O interface is

further enhanced by the capability of selecting the appropriate optional
line drivers and terminators for each application.
A programmable serial communications interface using Intel's 8251
Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is con-

•

tained on the board.

The USART can be programmed by the systems soft-

ware to provide virtually any serial data transmission technique presently
in use (including IBM Bi-Sync).

The mode of operation (i.e., synchronous

or asynchronous), data format, control character format, parity and asynchronous serial transmission rate (within limitations given later) are
all under program control.

•

The 8251 provides full duplex, double buffered

transmission and receive capability.

Parity, overrun, and framing error

detection are all incorporated in the USART.

The inclusion of jumper

selectable TTY, or RS232C compatible interfaces on the board in conjunction
with the USART provide a direct interface to a TTY, CRT, RS232C

compatible

devices, and asynchronous and synchronous modems.
A single-level interrupt may originate from anyone of six sources
including the USART, programmable I/O interface, and two user designated

•

interrupt request lines.

When an interrupt request is recognized, a

RESTART 7 instruction is generated.

The processor responds by suspending

program execution and executing a user defined interrupt service routine.
Inside the compact chassis you will find a complete, quad output
power supply with ample capability to support most combinations of computing power, I/O and memory expansion boards.

Dual cooling fans are provided

to circulate the air across the computer boards and power supply.

The I/O

section of the System 80/10 is easily accessible from the rear of the
System chassis and the power supply as well as the system bus is accessible

•

from behind the OEM front panel.

1-3

1.3

SYSTEM MONITOR
A standard feature of the System 80/10 is a software monitor which

is programmed in two Intel ROMs.
basic capabilities:

The monitor provides the user with two

1) it gives the user access to console input and

•

output routines as well as paper tape input and output control software and
2) the monitor along with a TTY or CRT provides the user with a "virtual

•

console" that has immediate access to memory and registers and has control
commands to begin execution and to display or alter the contents of the
memory or registers.

The system monitor ROMs are installed in the first

two ROM sockets of the SBC 80/10 computer, occupying locations 0 to 2,048 10 ,
The development cycle of System 80/10 based OEM products may be significantly reduced using the Intellec MDS.

The resident assembler, text

editor, and system monitor greatly simplify the design, development, and
debug of System 80/10 based system software.

A unique In-Circuit Emulator

•

(ICE-80) Intellec MDS option provides the capability of executing and
debugging OEM system software directly on the System 80/10.
Intel's high level language, PL/M, can be used to significantly decrease the time required to develop OEM system software.

•
•
•

•

1-4

•

•

CHAPTER 2
SYSTEM OVERVIEW
The System 80/10 is a fully packaged microcomputer utilizing either
the SBC 80/10 or SBC 80/l0A single board computers.
divided into five functional blocks (see Figure 2-1).

The System can be
They are as follows:

1) SBC 80/10 or SBC 80/IOA
2) Front Panel

•

3) Modular card cage and backplane assembly
4) Power Supply
5) System Monitor

SBC 80/10
The SBC 80/10 is a complete computer system on a single 6.75 x 12 inch

•

printed circuit card.

The CPU, system clock, RAM, non-volatile ROM, I/O

ports and drivers, serial communication interface, bus control logic and
drivers all reside on the board.
Front Panel
The System 80/10 Front Panel consists of the AC power ON/OFF switch

•

and the system reset circuitry.

The simplicity of the System 80/10 Front

Panel allows the OEM user to add his own mylar overlay or structural foam
cover to meet his own design needs.
Modular Cardcage and Backplane Assembly
The Modular Cardcage and Backplane Assembly is installed in the
chassis to house the SBC 80/10 and provide an easily accessible bus in-

•

terface.
boards.

The cardcage houses the SBC 80/10 and up to three expansion
All SBC 80 bus signals are present on each mating connector.

Power Supply

•

The System 80/10 power supply provides regulated DC output power at
+12, +5, -5 and -12 volt levels.

The power supply is chosen to provide
2-1

power for a fully loaded SBC 80/10 and most combinations of up to three
SBC memory, I/O or combination expansion boards.

The power supply also

•

provides an "AC low" power failure output, TTL logic level, for system
power-down control.

•

System Monitor

.

The System 80/10 Monitor is an Inte1@B080 program provided in two
pre-programmed 1K ROMs.

The monitor accepts and acts upon user commands

to operate on the System 80/10 memory and I/O.

It also provides input

and uutput facilities in the form of I/O drivers for user console devices.

The monitor provides the following facilities:

Display selected areas of memory and processor registers.

•

Initiate execution of user programs.
Modify contents of memory and processor registers.
Insert instruction(s) into memory.
Reposition blocks of data in memory.
Input hexadecimal file from TTY reader to memory.
Output hexadecimal file to TTY punch from memory.

•

The monitor communicates with the user through an interac:tive console device, normally a TTY or CRT terminal.

The dialogue between the

operator and monitor consists of user originated commands in the monitor's
command language, and monitor responses, either in the form of a printed
message or an action being performed.

The monitor begins the dialogue by

printing the sign-on message "SBC 80P Monitor" on the console and requesting

•

a command by presenting a prompt character, " " (period).

•

2-2

•

•

.

•

"

RS 232C
COMPATIBLE
DEVICE

TTY

.~ ~)l.

• ~

r --..,.--I
I

V

,.,

V

7

SERIAL
DATA
INTER·
FACE

...

1------- -

SERIAL
DATA
INTER· ~
~
FACE V

~
1------

1--- -

j

I

"I

w

2K S~~~xMgnitor

2 INTERRUPT
JUMPER
REQUEST
SE LECT ABL E
LINES

.....

PROGRAMMABLE
COMMUNICATIONS
INTERFACE
IUSARTI

ROK/PROM MEMORY
(SOCKETS)

I

I

8080A
CPU

G=51

BUS INTERRUPT
REQUEST LI N E

ADDRESS BUS
DATA BUS

~

- n-:!:.Uv -- -- -- -- -

-- --

V'-

power

I

I

2~NTERRUPT

1

REQUEST
LINES

-

Power......,

I i5

supply

Fron-;

P:~

lK x 8
RAM
MEMORY

1

80/10
SYSTEM
BUS

I

-- -- -- -- -- -- -- -

cr:1
-Reset

FIGURE 2-1

I
I

PROGRAMMABLE
PERIPHERAL
INTERrACE

~

System Reset Line

+5V

I

I

,~

CONTROL BUS

ldular Cardcage and Backplane Assembly

-,
I

48 PROGRAMMABLE
PARALLEL 1/1") LINES

DRIVER/TERMINATOR
INTERFACE
\

N

-

I
INTERRUPT
REOUEST
LINE

TTY
INTERFACE

RS 232C
INTERFACE

-

CONTROL
INTERFACE
1

I

•

USER DESIGNATED
PERIPHERALS

'------

CONTROL
INTERFACE "'I

•

•

..

SYSTEM 80/10 BLOCK DIAGRAM

I
I
I

y,
--I

MEMORY
AND
liO
EXPANSION

•
•

•
•
•
•
•

•

•
•

CHAPTER 3
SBC BO/lO AND BO/lOA MODULE
3.1

FUNCTIONAL ORGANIZATION OF THE SBC BO/lO AND SBC BO/lOA MODULE
For descriptive purposes, the circuitry on the SBC BO/lO and BO/lOA

can be divided into six functional blocks:
1) CPU Set
2) System Bus Interface
3) Random Access Memory (RAM)

•

4) Read Only Memory (ROM/PROM) Logic
5) Serial I/O Interface

6) Parallel I/O Interface
as shown in Figure 3-1.
The CPU Set consists of the BOBOA Control Processor, the B224 Clock
Generator and the B23B System Controller.

•

SBC BO/lO.

The CPU Set is the heart of the

It performs all system processing functions and provides a

stable timing reference for all other circuitry in the system.

The CPU

Set generates all of the address and control signals necessary to access
memory and I/O ports both on the SBC BO/lO and external to the SBC BO/lO.
The CPU Set is capable of fetching and executing any of the BOBO's seventyeight instructions.

•

The CPU Set responds to interrupt requests origina-

ting both on and off the SBC BO/lO, to HOLD requests from modules wishing
to acquire control of the system bus, and to WAIT requests from memory 'or
I/O devices having an access time which is slower than the BOBO's cycle
time.
The System Bus Interface includes an assortment of circuitry which

•

gates interrupt requests, HOLD requests, READY (no wait inputs and the
system reset input to the appropriate pins of the CPU Set.

•

drive the various external system control signals.

Other circuits

The System Bus Inter-

face also includes two B2l6 bidirectional bus drivers which drive the
memory data bus on the SBC BO/10.

Six B226 devices drive the external

system data and address busses.

•

The Random Access Memory (RAM) provides the System BO/10 user with
1024 x B-bits of on board read/write storage.

Eight Intel BIll Low Power

Static RAM chips (256 x 4-bits each) are mounted on the SBC BO/10.
3-1

The

CPU SET

RAM

ROM/PROM

MEMORY

MEMORY

INT
HOLD

MEMORY BUS

MEMORY BUS
BUFFERS

DRESS
w
I

N

EXTERNAL

SBC-BO/IO INTERNAL BUS

BUS
INTERFACE

SERIAL I/O

PARALLEL I/O

INTERFACE

INTERFACE

BBBBJ}S
PORTS
CONNECTOR JI

PORTS
CONNECTOR J2

FIGURE 3-1 SBC 80/10 FUNCTIONAL BLOCK DIAGRAM

•

"

•

•

•

•

.,

•

•

~~T>

SBC 80/10A has eight Intel 8102 Low Power Static RAJ1 chips (1024 x I-bit

•

each).
The Read Only Memory (ROM/PROM) section provides the user with the
necessary provisions for installing up to 4096 x 8-bit of ROM or PROM
on the SBC 80/10 and up to 8192 x 8-bits of ROM or PROM on the SBC 80/10A.
The 80/10 and 80/10A have four 24-pin sockets that can accept either Intel
8708 Erasable and Electrically Reprogrammable Read Only Memory chips
or Intel 8308 Metal Masked Read Only Memory Chips.

Optionally the SBC

80/10A accepts Intel 2716 Erasable and Electrically Reprogrammable ROM
(EPROM) chips, Intel 2758 Erasable and Electrically Reprogrammable ROM
(EPROM) chips, or Intel 2316E Metal Masked ROM chips.

•

The total ROM/PROM

memory capacity using 8708, 8308 or 2758 chips is 4K x 8-bits and 8K x 8bits using 2716 or 2316E chips.
The Serial I/O Interface, using Intel's 8251 USART device, provides
a bidirectional serial data communications channel that can be programmed
to operate with most of the current serial data transmission protocols.
Synchronous or asynchronous mode, baud rate, character length, number of
stop bits and the choice of even, odd or no parity are all program selec-

•

table.

The user also has the option of configuring the Serial I/O Inter-

face as an EIA RS232 interface or as a Teletype-compatible current loop
interface.
The Parallel I/O Interface, using two Intel®8255 Programmable Peripheral interface devices, provides 48 signal lines for the transfer and control of data to or from peripheral devices.

•

Eight lines already have a

bidirectional driver and termination network permanently installed.

This

bidirectional network allows these eight lines to be inputs, outputs, or
bidirectional (selected via jumpers).
are uncommitted.

The remaining 40 lines, however,

Sockets are provided for the installation of drivers or

termination networks as required to meet the specific needs of the user
system.
3.2

THEORY OF OPERATION
In the preceding chapter we introduced each of the SBC 80/10 function-

al blocks and defined what each block was capable of doing.

In this chap-

ter we shall go one step further and describe how each block performs its

•

particular function(s).

The text will constantly refer to the SBC 80/10

schematics, provided in Appendix B.

3-3

Note:

3.2.1

Both active-high (positive true) and active-low (negative true) signals appear on the SBC 80/10 schematics. To eliminate any confusion when reading this chapter, the following convention will be
adhered to: whenever a signal is active-low, its mnemonic is followed by a slash; for example, MRDC/ means that the level on that
line will be low when the memory read command is true (active). If
the signal is subsequently inverted, thus making it active-high,
the slash is omitted; for example, MRDC means that the level on that
line will be high when the memory read command is true.

•
•

THE CPU SET

•

The CPU Set consists of three Intel®integrated circuit devices:

* 8080A Central Processor
* 8224 Clock Generator
* 8238 System Controller

Unit

and an 18.432 MHz crystal that establishes the frequency of oscillation
for the 8224 device via a 10pF capacitor, as shown in Figure 3-2.

Together

the elements in the CPU Set perform all central processing functions.

The

following paragraphs describe how the elements within the CPU Set interact
with all other logic on the SBC 80/10.

The interaction between the ICs

within the CPU Set, however, is not described.

Instead, the reader is

•

referred to the Intel "8080 Microcomputer Systems User's Manual" for a
detailed description of the 8080, 8224 and 8238 devices.
The CPU Set is shown on sheet 1 of the SBC 80/10 schematic (Appendix

B).
3.2.1.1 INSTRUCTION TIMING
The activities of the CPU Set are cyclical.

The CPU fetches an in-

•

struction, performs the operations required, fetches the next instruction,
and so on.

This orderly sequence of events requires precise timing.

The

8224 Clock Generator, provides the primary timing reference for the CPU
Set.

The crystal in conjunction with a 10pF capacitor tunes an oscilla-

tor within the 8224 to precisely 18.432 MHz.

The 8224 "divides" the

oscillations by nine to produce two-phase timing inputs (01 and 02) for
the 8080.

The 01 and 02 signals define a cycle of approximately 488 ns.

duration.

A TTL level phase 2 (02TTL) signal is also derived and made

3-4

•

..

•

•

•

•

1r-

~

25

0 r:2" "'6,...---1 27
2 29
3
4

~INT

~
+5V
20
-5V .... 11

w
I

V1

+5V

• -'.

MI

I ; '1'

Yl

C22 _ 18.432
MHZ

is

Y

82
1

_______

RESIN

.!:14~
3

r

X2

5

-!0~2. !. T .!. :I~.

RDYlN

~

JL:2_2_

02
OSC 12
SS

Figure 3-2

P.

~

C8080A

7 34

....

35

EDID-

vee

VBB

~ ~.

~~ .1~L~i

30
31

A32

+12V ~fJ
VDD
.--=---1 GND

REST
01

Xl

__

.

c;.
~

5 32
6

HOLD

SYNC
ROY
RESET

01

02

pL

_6

33

~

..

1

1o
11
12
13
14

.Il

AI5
WAIT

24

4:-:::0_ _

313. - - :
)9
e--

1( > - - >

. (
)

WR~_8

DBlN

=>

1IlOo

---=-=-=--

J1L=-=-=-=---=---=---_-=--_-_-

HLDA ,_2_1=-0_ _ _ _---,,_ _
D 0 10
15
2 HLD DBINWR
4 3

~i

:; ~9.~~

3
3
4 4

100.
6

5 -5
6
D 7 6

2

1.9. 5

21

ii

-04~
+12

,

'30

07

1 SS

D
M8

i~~
13

[B!

~_l8_
~~
~BU~S~E~NI

8238

~_ _

3 ....
.... _ 5 _ .
4

20
5
6 <1 7
DB7 - 4 --"':

MEMR )_2"---0>0
lOR )_2~
MEMW
IOWn ~2_7_......

2U

THE CPU SET

•

•

available to external logic.

In addition, the output of the oscillator

is buffered and brought out on OSC so that other system timing signals

•

can be derived from this stable, crystal controlled source (e.g., the
serial I/O baud rate is derived from OSC).

All processing activities of

the CPU Set are referred to the period of the

~1

and

~2

clock signals.

Within the 8080 CPU Set, an instruction cycle is defined as the time
required to fetch and execute an instruction.

During the fetch, a

selected instruction (one, two or three bytes) is extracted from memory
and deposited in the CPU's operating registers.

During the execution

part, the instruction is decoded and translated into specific processing
activities.
Every instruction cycle consists of one, two, three, four or five
machine cycles.

A machine cycle is required each time the CPU accesses

memory or an I/O port.

•

The fetch portion of an instruction cycle requires

one machine cycle for each byte to be fetched.

The duration of the exe-

cution portion of the instruction cycle depends on the kind of instruction that has been fetched.

Some instructions do not require any machine

cycles other than those necessary to fetch

th~

instruction; other in-

structions, however, require additional machine cycles to write or read

•

data to/from memory or I/O devices.
Each machine cycle consists of three, four or five states.

A state

is the smallest unit or processing activity and is defined as the interval between two successive positive-going transitions of the

~1

clock

pulse.
There are three exceptions to the defined duration of a state.

They

are the WAIT state, the hold (HLDA) state and the halt (HLTA) state.

•

Because the WAIT, the HLDA, and the HLTA states depend upon external
events, they are by their nature of indeterminate length.

Even these

exceptional states, however, must be synchronized with the pulses of the
driving clock.

Thus the duration of all states, including these, are

integral multiples of the clock pulse.
To summarize, then, each clock period marks a state; three to five
states summarize a machine cycle; and one to five machine cycles comprise
an instruction cycle.

A full instruction cycle requires anywhere from

3-6

•

•

four to seventeen states for its completion, depending on the kind of instruction involved.
There is just one consideration that determines how many machine
cycles are required in any given instruction cycle:

the number of times

that the processor must reference a memory address or an I/O address, in
order to fetch and execute the instruction.

Like many processors, the

8080 is so constructed that it transmits one address per machine cycle.
Thus, if the fetching and execution of an instruction requires two memory references, then the instruction cycle associated with that instruc-

•

tion consists of two machine cycles.

If five such references are called

for, then the instruction cycle contains five machine cycles.
Every instruction cycle has at least one reference to memory, during
which the instruction is fetched.

An instruction cycle must always have

a fetch, even if the execution of instruction requires no further references to memory.

•

therefore a FETCH.

The first machine cycle in every instruction cycle is
Beyond that, there are no fast rules.

the kind of instruction.

It depends on

The input (INP) and the output (OUT), instruc-

tions each require three machine cycles:

a FETCH, to obtain the instruc-

tion; a MEMORY READ, to obtain the address of the object peripheral; and
an INPUT or an OUTPUT machine cycle, to complete the transfer.
Every machine cycle within an instruction cycle consists of three
to five active states (referred to as T1, T2, T3, T4, and T5).

•

The actual

number of states depends upon the instruction being executed, and on the
particular machine cycle within the greater instruction cycle.

Figure

3-3 shows the timing relationships in a typical FETCH machine cycle.
Events that occur in each state are referred to transitions of the 01 and
02 clock pulses.
At the beginning of each machine cycle (in state T1), the 8080 activates its SYNC output and issues status information on its data bus.

•

8224 accepts SYNC and generates an active-low status strobe (STSTB/) as
soon as the status data is stable on the data bus.
indicates the type of machine cycle in progress.

•

The

The status information
The 8238 System Control-

ler accepts the status bits from the 8080 and STSTB/ from the 8224, and
uses them to generate the appropriate control signals (MEMR/, MEMW/, IOR/

3-7

I-C---

I
01

MI
(FETCH)

I

T2

TI

n

Sl

1l-1
T3

T4

n

n

n

n

----X

J

o

n

\

MEMR/

X----X
_ _ _ _

MEMORY ADDRESS

/

n

n

I

02
ADDRESS
BUS
__ _ _

M3
(INPUT)

M2
4C- - (FETCH 2nd BYTE)~""
TI
I T2
I
T3
I Tl

n

n

rL

Ill---J
X-X
_

MEMORY ADDRESS

\

~

T2

I/O PORT ADDRESS

I
\

10R/

I

DATA
BUS
BUSEN/

2nd byte
of IN instruction

1st byte
of IN instruction

FIGURE 3-3

•

..

II

•

Data From
I/O Port

TYPICAL FETCH MACHINE CYCLE

•

•

~

•

•

X-_

•

and IOWR/) for the current machine cycle.
The rising edge of 02 during Tl loads the processor's address lines
(AO - A15).

•

These lines become stable within a brief delay of the 02

clocking pulse, and they remain stable until the first 02 pulse after
state T3.

This gives the processor ample time to read the data returned

from memory.
Once the processor has sent an address to memory, there is an opportunity for the memory to request a WAIT.

•

8224's RDYIN line low.

This it does by pulling the

As long as the RDYIN line remains low, the CPU

Set will idle, giving the memory time to respond to the addressed data
request.

The 8224 synchronizes RDYIN with internal processor timing and

applies the result to the 8080's READY input.

The processor responds

to a wait request by entering an alternative state (TW) at the end of
T2, rather than proceeding directly to the T3 state.
be of indefinite duration.

•

A wait period may

The 8080 remains in the waiting condition

until its READY line again goes high.

The cycle may then proceed, begin-

ning with the rising edge of the next 01 clock.

A WAIT interval will

therefore consist of an integral number of TW states and will always be
a multiple of the clock period.
The events that take place during the T3 state are determined by
the kind of machine cycle in progress.

•

In a FETCH machine cycle, the

CPU Set interprets the data on its data bus as an instruction.

During

a MEMORY READ, signals on the same bus are interpreted as a data word.
The CPU Set itself outputs data on this bus during a MEMORY WRITE machine
cycle.

And during I/O operations, the CPU Set may either transmit or

receive data, depending on whether an INPUT or an OUTPUT operation is
involved.

Consider the following two examples.

Figure 3-4 illustrates the timing that is characteristic of an input
instruction cycle.

During the first machine cycle (Ml), the first byte of

the two-byte IN instruction is fetched from memory.

The 8080 places the

16-bit memory address on the system bus near the end of state Tl.

The

8238 activates the memory read control signal (MEMR/) during states T2

•

and T3 (and any intervening wait states, if required).

During the next

machine cycle (M2), the second byte of the instruction is fetched.

3-

During

the third machine cycle (M3) , the IN instruction is executed.

The 8080

duplicates the 8-bit I/O address on address lines ADRO-7 and ADR8-F.

•

The 8238 activates the I/O read control signal (IOR/) during states T2
and T3 of this cycle.

In all cases the system bus enable input (BUSEN/)

to the 8238 allows for normal operation of the data bus buffers and the
read/write control signals.

If BUSEN/ goes high the data bus output

•

buffers and control signal buffers are forced into a high-impedance state.
Figure 3-5 illustrates an instruction cycle during which the CPU Set
outputs data.

During the first two machine cycles (Ml and M2), the CPU

Set fetches the two-byte OUT instruction.
(M3) , the OUT instruction is executed.
I/O address on lines ADRO-7 and ADR8-F.

During the third machine cycle

The 8080 duplicates the 8-bit
The 8238 activates an advanced

I/O write control signal (IOWR/) at the beginning of state T2 of this
cycle.

•

The nature and implications of the 8238 timing will be explained

later (page 3-17). The 8238 outputs the data onto the system bus at the
end of state T2.

Data on the bus remains stable throughout the remainder

of the machine cycle.

BUSEN/ must be low to prevent the output and

control buffers from being forced into the high impedance state.
Observe that a RDYIN signal is necessary for completion of an output machine cycle.

•

Unless such an indication is present, the processor

enters the TW state, following the T2 state.

Data on the output lines

remains stable in the interim, and the processing cycle will not proceed
until the RDYIN line again goes high.
The 8080 generates a WR/ output for qualification of the advanced
I/O write (IOWR/) and memory write (MEMW/) control signals from the 8238,
during those machine cycles in which the CPU Set outputs data.

The nega-

•

tive going leading edge of WR/ is referred to the rising edge of the
first 01 clock pulse following T2.

WR/ remains low until re-triggered

by the leading edge of 02, during the state following T3.

Note that any

TW states intervening between T2 and T3 of the output machine cycle will
necessarily extend WR/.
All processor machine cycles consist of at least three states:
T2, and T3 as just described.

Tl,

If the CPU Set has to wait for a RDYIN

response, then the machine cycle may also contain one or more TW states.

•

•

..

01

Jl

T1

T2

n

I

•

•

H1
(FETCH)

,-

1-

•

•

--,-

H2
(FETCH 2nd

-.a_

T4

T3

n

n

I

T1

n

n

T2

H3
(INPUT)

BYTE)~"

I

I

T3

n

•

,..

."

T1

n

T2

n

I

~

n

Q

02

AD~~SS ~== =-X
MEMR/

\

X= ===X

MEMORY ADDRESS

r-

X=X

MEMORY ADDRESS

\

I/O PORT ADDRESS

/
\

IOR/

I

DATA
BUS
BUSEN/

1st byte
of IN instruction

FIGURE 3-4.

2nd byte
of IN instruction

INPUT INSTRUCTION CYCLE

Data From
I/O Port

X=

I....

\ Tl

01

~I-c

M1 (FETCH)
T2
I
T3

n

Jl

T4

n

n

02

AD~~~SS ~~ ~

Tl

n
1-----..J

=- X

~I-ca

T3

Tl

n n
----u-l--,------'

X =-= ~ =~ X

MEMORY ADDRESS

\

MEMR/

M2
T2

n

MEMORY ADDRESS

\

/

n
X~X

n

I/O PORT ADDRESS

\

x

DATA
BUS
BUSEN/

\

!

0=><=
i-

,11

v

Ii

1st byte
of OUT instruction

FIGURE 3-5.

..

n,----

/

IOWR/

•

M3 (OUTPUT)--'
I T2
I T3
I

•

•

2nd byte
of OUT instruction

Data Output
to I/O Port

OUTPUT INSTRUCTION CYCLE

•

•

•

•

•

X ==

•

During the three basic states, data is transferred to or from the CPU
Set.
After the T3 state, however, it becomes difficult to generalize.

T4

and T5 states are available, if the execution of a particular instruction
requires them.

But not all machine cycles make use of these states.

It

depends upon the kind of instruction being executed, and on the particular
machine cycle within the instruction cycle.

The processor will terminate

any machine cycle as soon as its processing activities are completed,

•

rather than proceeding through the T4 and T5 states every time.

Thus

the 8080 may exit a machine cycle following the T3, the T4, or the T5
state and proceed directly to the Tl state of the next machine cycle.
3.2.1.2

INTERRUPT SEQUENCES

The 8080 has the built-in capacity to handle external interrupt requests.

•

Peripheral logic can initiate an interrupt simply by driving

the processor's interrupt (INT) line high.

The interrupt (INT) input

is asynchronous, and a request may therefore originate at any time
during any instruction cycle.

Internal logic re-clocks the external re-

quest, so that a proper correspondence with the driving clock is established.

An interrupt request (INT) arriving during the time that the

interrupt enable line (INTE) is high, acts in coincidence with the

•

clock to set the internal interrupt latch.

~2

This event takes place during

the last state of the instruction cycle in which the request occurs, thus
ensuring that any instruction in progress is completed before the interrupt can be processed.
The INTERRUPT machine cycle which follows the arrival of an enabled
interrupt request resembles an ordinary FETCH machine cycle in most respects.

The contents of the program counter are latched onto the address

lines during Tl, but the counter itself is not incremented during the
INTERRUPT machine cycle, as it otherwise would be.

In this way, the pre-

interrupt status of the program counter is preserved, so that data in

•

the counter may be saved in the stack.

This in turn permits an orderly

return to the interrupted program after the interrupt request has been
processed.

3-13

Because the 8238's INTAI output (pin 23) is tied to +12 volts, the
8238 blocks incoming data and automatically inserts a Restart (RST 7) in-

•

struction onto the 8080 data bus during state T3, when the interrupt is
acknowledged by the 8080.

RST is a special one-byte call instruction that

•

facilitates the processing of interrupts (the ordinary program call instruction is three bytes long).

The RST 7 instruction causes the 8080

to branch program control to the instruction being stored in memory location 38 16 ,
3.2.1.3

HOLD SEQUENCES

By activating the 8080's HOLD input, an external device can cause the
CPU Set to suspend its normal operations and relinquish control of the
address and data busses.

•

The CPU Set responds to a request of this kind

by floating its address and data outputs, so that these exhibit a high
impedance to other devices sharing the busses.

At the same time, the pro-

cessor acknowledges the HOLD by placing a high on its HLDA output pin.
During an acknowledged HOLD, the address and data busses are under control
of the peripheral which originated the request, enabling it to conduct
memory transfers without processor intervention.
3.2.1.4

•

HALT SEQUENCES

When a halt instruction (HLT)is executed, the 8080 enters the halt
state after state T2 of the next machine cycle.

There are only three ways

in which the 8080 can exit the halt state:

•

A high on the 8224 reset input (RESIN/) will always reset the 8080
to state Tl; reset also clears the program counter .

•

• A HOLD input will cause the 8080 to enter the hold state, as previously described. When the HOLD line goes low, the 8080 re-enters
the halt state on the rising edge of the next 01 clock pulse •
• An interrupt (i.e., INT goes high while INTE is enabled) will cause

the 8080 to exit the halt state and enter state Tl on the rising
edge of the next 01 clock pulse.

NOTE:

The interrupt enable

(INTE) flag must be set when the halt state is entered; otherwise,
3-14

•

•

the 8080 will only be able to exit via a reset signal.
3.2.1.5

START-UP SEQUENCE

When power is applied initially to the 8080, the processor begins
operating immediately.

The contents of its program counter, stack pointer,

and the other working registers are naturally subject to random factors
and cannot be specified.
begins with a reset.

•

RESIN/ input.

For this reason, the CPU Set power-up sequence

An external RC network is connected to the 8224's

The slow transition of the power supply rise is sensed by

an internal Schmitt Trigger which converts the slow transition into a
clean, fast edge on the RESIN/ line when the input level reaches a predetermined value.
An active RESIN/ input to the 8224 produces a synchronized RESET
signal which restores the processor's internal program counter to zero.
Program execution thus begins with memory location zero, following a re-

•

set.

Systems which require the processor to wait for an explicit start-

up signal will store a halt instruction (HLT) in this location.
or an automatic INTERRUPT will be used for starting.

A manual

In other systems,

the processor may begin executing its stored program immediately.

Note,

however, that the reset has no effect on status flags, or on any of the
processor's working registers (accumulator, indices, or stack pointer).

•

The contents of these registers remain indeterminate, until initialized
explicitly by the program.
In addition to generating a RESET signal, the RESIN/ input causes
the 8224's status strobe (STSTB/) output to remain true (low).

This

allows both the 8080 and 8238 to be reset by a power-up sequence or an
externally generated RESIN/ condition.
3.2.2

SYSTEM BUS INTERFACE LOGIC
The System Bus Interface logic consists of three general groups of

circuitry:

•

1) assorted gates that accept the various bus control signals, the
interrupt request lines, the ready indications and then applies
3-15

•

these signals to the CPU Set,
2) the system bus drivers, and
3) the Failsafe circuitry which generates an acknowledgment during
interrupt sequences and during those cycles in which an acknowledgment is not returned because a non-existent device was inadvertently addressed.

•

Each group is described in the following paragraphs.
3.2.2.1

SYSTEM CONTROL SIGNAL LOGIC

Interrupt Requests:
Four interrupt request lines are OR'd together at A17-6 (ref. Appendix B) and applied to the 8080's INT input.
lines are from external sources:

Two of the interrupt request

EXT INTR 1/ which enters the SBC 80/10

•

at connector J1 pin 49 and EXT INTR 2/ which enters the SBC 80/10 at Pl-42.
The other two interrupt requests originate on the SBC 80/10:

INT 55/ is

an interrupt request from ports 1 or 2 in the Parallel I/O Interface (see
Section 3.2.6.2); and INT 51/ is an interrupt request from the 8251 USART
in the Serial I/O Interface (see Section 3.2.5.4).
Hold Requests:

•

If the system 80/10 is operating with other modules sharing the bus,
one of the modules can acquire control of the external bus by activating
the 8080's HOLD/ input (connector pin PI-IS).
applied to the 8080's HOLD pin.

HOLD/ is inverted and

As described in Section 3.2.1.3, the

8080 will subsequently activate its hold acknowledge (HLDA) output.
is, in turn, latched by a 74LS74 flip-flop (at A29).

HLDA

The Q output from

•

the D-type latch (DHLDA) disables the 8097 circuits (A47) that drive the
external read/write control outputs:

MRDC/, MWTC/, lORC/ and IOWC/.

DHLDA also disables the external system address and data bus drivers by
asserting a high at their active-low chip select (CS/) input pins.

As a

result of DHLDA, all of the above-mentioned drivers enter the high-impedance state.

The Q output from the DHLDA output informs other modules

of this condition via the BUSY/ output (connector pin PI-17).
driven by transistor Q5.

3-16

BUSY/ is

•

•

System Reset:
Connector pin Pl-14 on the SBC 80/10 can be used to accept an externally generated SYSTEM RESET signal and to transfer an SBC 80/10 generated RESET signal to other modules in the system.

If jumper pair 54-55

is connected, a RESET from the 8224 will be gated through the Q4 transistor to connector pin Pl-14, thus resetting other modules in the system
during power-up sequences.

An externally generated SYSTEM RESET is accep-

ted at Pl-14, buffered, applied to the 8080's RESET input and made avail-

•

able to other logic on the SBC 80/10.
I/O Ready Generation
During each serial or parallel I/O cycle, a "ready" indication
(IORDYIN/) is returned to the CPU Set.

The three chip select lines for

the 8251 and the two 8255 devices are OR'd together (at A17-8 on sheet 3
of the schematic).

•

The resultant output is then NANDed (at A44-11) with

the I/O read (lOR) or the advanced I/O write (ADV lOW)
IORDYIN/.

sign~l

to produce

Recall from Section 3.2.1 that the 8238 System Controller

(in the CPU Set) generates the I/O write control output at the beginning
of all I/O write cycles.

The 10W/ signal, alone, is labeled ADV 10W/.

IOW/ is also synchronized with the 8080's WR/ output to produce the system write command lm-;re/.

•
.

ADV 10W/ allows the ready indication to be re-

turned early enough to avoid an unnecessary wait state (see Figure 3-6).
The 10WC/ signal causes an I/O device to actually write the data, later
in the I/O cycle.
Ready Inputs:
Recall from Section 3.2.1.1 that the CPU Set must see a ready indication before proceeding to internal state T3 during all machine cycles.

..

The 74S20 section at AS7 on sheet 1 of the schematic ORs the following
ready indications:
1) INT ACK/ or TIME OUT ACK/ from the Failsafe logic (see Section
3.2.2.3),

•

2) IORDYIN/ from the Serial and Parallel 1/0 Interfaces,
3) PROM RDYINI from the ROM/PROM logic (see Section 3.2.4), and
4) RAM RDYIN/

f~om

the RAM section (see Section 3.2.3).
3-17

The resultant output indicates an on-board memory or I/O access and is
used to disable the external data bus drivers at A53 and A54.

This out-

•

put from A57-8 is also OR'd (at A30-3) with the externally generated
AACK/ (connector pin P1-25) and XACK/ (connector pin Pl-23) inputs.

The

•

output from A30-3 is then applied to the CPU Set's RDYIN input (pin 3
on the 8224).

When the SBC 80/10 CPU Set accesses an external module, the

AACK/ or XACK/ input informs the CPU Set that the external device is ready.
AACK/ is an advanced acknowledge that allows certain OEM modules to be
accessed faster.
Figure 3-6 illustrates basic timing for the ready indications.
Bus Clock Generation:
The OSC output from the CPU Set (18.432 MHz frequency) is applied to

•

the clock input of a 74LS74 D-type flip-flop (at A29-11 on sheet 1 of
the schematic).

The Q output from this latch is tied to its own D input.

Consequently, the Q output exhibits half the frequency of the OSC input.
This 9.216 MHz output is buffered and made available to external modules
on the common clock (CCLK/) line (via connector pin Pl-31) and the bus
clock (BCLK/) line (via connector pin Pl-13).
3.2.2.2

•

SYSTEM BUS DRIVERS

The SBC 80/10 internal memory data bus (DMO-DM7) is driven by two 8216
bidirectional bus drivers, shown at A55 and A56 on sheet 3 of the schematic.
All data being transferred to/from the RAM memory (see Section 3.2.3) or
ROM/PROM memory (see Section 3.2.4) is routed through these two devices.
The chip select (CS/) input is provided by the MEM CMD/ signal which is
the result of ORing RAM RDYIN/ and PROM RDYIN/.

•

The direction enable

(DIEN) input to the 8216s is provided by the memory read (MEMR) signal.
When the SBC 80/10 communicates with an external module, the data
is driven by two 8226 bidirectional data bus drivers at A53 and A54 on
sheet 1 of the schematic.

The direction input to the 8226s is provided

by the OR of memory read (MEMR) and I/O read (lOR).
be disabled during 8080 HOLD sequences.

The 8226 devices will

The eight data bus lines to the

8226 bus drivers enter/leave the SBC 80/10 via the PI edge connector.

3-18

•

•
Tl

T2

T4

T3

MEMR/, 10RI
~V MEMW/, or ADV

lowl

10RDYIN/, PROM RDYIN/,
RAM RDYINI or AACKI

,..-------

Tl

T3

}

SBC-80/10
ON-BOARD
ACCESS
(NO WAIT)

WR/

•

EXTERNAL
ACCESS
WITHOUT
ADVANCED
WRITE SIGNAL
(1 WAIT STATE)

MWTC/ or 10WC/

XACK/

•

8080 MUST
SENSE READY HERE
TO AVOID WAIT
STATE

8080 MUST
SENSE READY HERE
TO EXIT FIRST
WAIT STATE

.

FIGURE 3-6

•

READY TIMING

The external 16-bit system address bus is driven by four 8226 bidirectional bus drivers.

However, because the direction enable pin (EN/) on

these 8226 devices is tied to ground, they can only be used to transmit
addresses to external modules; they will not receive addresses from
external modules.

Consequently, the SBC 80/10 can access other modules,

but other modules cannot access the memory or I/O controllers on the
SBC 80/10.

•
•

Like the data bus drivers, these 8226 devices are disabled

during 8080 HOLD sequences.
3.2.2.3

FAILSAFE TIMER

When the 8080 acknowledges an interrupt request, the 8238 System
Controller "forces" an RST 7 instruction onto the 8080s data bus (see
Section 3.2.1.2).

In order to read this RST 7 instruction, however, the

8080 must sense a ready indication.

The 8080 acknowledges an interrupt

by setting status bit a (DO) during the status output portion of each
machine cycle (i.e., when STATUS STROBE is true).

•

When this occurs, the

9602 one-shot (shown at A28 on sheet 5 of the schematic) is reset causing
a low signal on its output (INTR ACK/).

This output is then gated through

to the RDYIN pin on the 8224 as described in Section 3.2.2.1.
The Failsafe timer also performs another function.

If the CPU Set

tries to access a memory or I/O device but that device, for some reason,

•

does not return a ready indication, then the 8080 remains in a wait state
until ready is received.

The Failsafe timer is designed to prevent hang-

ing the system up in this way.

The 9602 one-shot is triggered by STATUS

STROBE at the beginning of each machine cycle.

If the one-shot is not

re-triggered (i.e., if another cycle does not begin) within 9 ms., then
the 9602 times out and its output (also labeled TIME OUT ACK/) is gated
through to the RDYIN pin on the 8224, thus allowing the 8080 to exit the
wait state.
3.2.3

•

This can be very helpful during system debugging.

RANDOM ACCESS MEMORY
The Random Access Memory (RAM) provides the user with 1024 (lK) x

8-bits of read/write storage that requires no clocks or refresh to operate.
The SBC 80/10 and SBC 80/l0A utilize two different configurations, therefore
each configuration is discussed separately in paragraphs 3.2.3.1 and
3.2.3.2.
3-20

•

3.2.3.1 SBC 80/10 RAM

•

The RAM logic consists of eight Intel 256 x 4-bit Static MOS RAM
chips, an Intel 8205 three-to-eight decoder for chip selection and assorted gates as shown on sheet 2 of the SBC 80/20 schematic (Appendix B).
The RAM devices used on the SBC 80/10 have a maximum access time of

•

500 nsec. Each chip has eight address inputs (AO-A7) that select one of
the 256 four-bit segments, active-low write (W/) and chip enable (CE/)
inputs and an output disable (OD) input.
data input/output pins (1/01-1/04).

Each chip also has four common

A high on the OD input disables out-

put and allows the I/O pins to be used for input.

During memory read

accesses, the data is read out nondestructively and has the same polarity

•

as the input data.
The least significant system address lines (ADRO-ADR7) are applied
to the eight address input pins on each RAM.

The most significant eight

system address lines (ADR8-ADRF) feed 3205 decoder. Each of the four
most significant decoder outputs are applied to the chip enable (CE/)
inputs on two RAM chips.

•

o to

One RAM in each pair reads or writes data bits

3 (DMO-DM3) while the other RAM reads or writes data bits 4 to 7

(DM4-DM7) for each RAM access.

One of the decoder outputs will be action the system address bus is within the

rang

hexadecimal).
During memory write cycles, the advanced memory write signal (ADV MEMW/)

is applied to the write input (W/) on each RAM.

A high on the active-low

memory read line (MEMR/) allows the selected RAM's I/O pins to be used to

•

accept the data which is to be written into the addressed location. During
memory read cycles, the level on ADV MEMW/ is high but is low on MEMR/ thus
allowing the addressed data to be read out and onto the data bus.
During all RAM access cycles, the active decoder output is NANDed with
ADV MEMW or MEMR (at A44-3) to produce a ready indication for the CPU Set
(RAM RDYIN/). The 8238 System Controller (see Section 3.2.1) generates
ADV MEMW or MEMR early enough in the memory cycle to allow RAM RDYIN/ to
appear at the CPU Set in time to prevent the occurrence of any wait states.
Figure 3-7 illustrates RAM access timing.
Whenever RAM is accessed, the data is transferred to/from the RAM chips

•

on the memory data bus (DMO-DM7).

Lines DMO-DM7 are interfaced to the

system data bus through two Intel 8216 bidirectional bus drivers (shown at
ASS and A56 on sheet 3 of the schematic) as described in Section 3.2.2.
3-21

3.2.3.2

SBC 80/l0A RAM

The RAM logic consists of eight Intel 8102 1024 x l-bit Low Power
Static RAM chips, an Intel 3205 three-to-eight decoder, and assorted
gates as shown on sheet 2 of the SBC 80/l0A schematic (Figure B-3).

•

The 8102 RAM devices used on the SBC 80/l0A have a maximum access
time of 450 nsec.

Each RAM chip has ten address inputs (ADRO-ADR9) that

•

select one of the 1024 bits, an active low write (ADV MEM WI) and chip
enable.

A high on the ADV MEM W/ input allows a memory read access.

The ten least significant address lines (ADRO-ADR9) are applied to
the ten address input pins on each 8102 RAM.

The six most significant

address lines (ADRA-ADRF) feed a 3205 decoder.

The output of the 3205

decoder is applied to each Chip Enable/ (CE/) input to the eight 8102
RAM's.

When the value on the system address bus is within the range

3COO-3FFF the decoder output will be activated (low).

•

During all RAM access cycles, the active decoder output produces a
ready indication for the CPU set (RAM RDY IN/).

The 8238 System Controller

(see Section 3.1) generates ADV MEM W/ or MEM R/ early enough in the memory
cycle to allow RAM RDY IN/ to appear at the CPU set in time to prevent the
occurrence of any wait states.

Figure 3-7 illustrates RAM access timing.

Whenever SBC 80/l0A RAM is accessed, the data is transferred to/from
the RAM chips on the memory data bus (DMO-DM7).

Lines DMO-DM7 are inter-

•

faced to the system data bus through two Intel 8216 bidirectional bus
driver (shown at ASS and A56 on sheet 3 of the schematic) as described
in Section 3.2.2.
3.2.4

READ-ONLY-MEMORY (ROM/PROM)
The System 80/10 has provisions for installing 4096 (4K) x 8-bit

words of read only memory in sockets already on the PC board.

•

Four Intel

8708 lK x 8-bit Erasable and Electrically Reprogrammable Read Only Memory
(EPROM) chips or four 8308 lK by 8-bit Metal Masked Read Only Memory (ROM)
chips can be installed in the four 24-pin sockets shown on sheet 3 of the
schematic (Appendix A).

Optionally the SBC 80/l0A has provisions for in-

stalling 4096 (4K) x 8-bits of read only memory in the sockets using four
Intel 2758 lK x 8-bits Erasable and Electrically Reprogrammable Read Only
Memory (EPROM) chips or installing 8192 (8K) x 8-bit words of read only
memory using either Intel 2716 2K x 8-bit Erasable and Electrically Re3-22

•

•

programmable Read Only Memory (EPROM) chips or Intel 2316E 2K x 8-bit
Metal Masked Read Only Memory (ROM) chips.
When addressing up to 4K of ROM address lines ADRO-ADR9 are applied
to the address pins AO-A9 at each of the four sockets.

The remaining ad-

dress lines, ADRA-ADRF are decoded by the 3205 device at A42.

•

Each of the

four least significant decoder outputs are applied to the chip select (CS/)
pin at one of four sockets.

One chip select line will be activated when-

ever the value on the system address bus is between 0000 and OFFF (hexadecimal).

In addition, when the four most significant address lines are

low (i.e., the address is less than OFFF) during a memory read cycle, the

•

output from the 74LSOO section at A39-3 is NANDed with MEMR to produce a
ready indication (PROM/ RDYIN/) for the CPU Set.

PROM RDYIN/ is thus gen-

erated in time to allow all ROM/PROM reads to occur without any wait states.
PROM RDYIN/ has the same timing as RAM RDYIN/, as shown in Figure 3-7.
When using the optional 2716, or 2316E chips with the 80/10A, address
lines ADRO-ADRA are applied to the address pins to each of the four sockets.
The remaining address lines, ADRB-ADRF are decoded by the 3205 three-to-

•

eight decoder.

Each of the four least significant decoder outputs are

applied to the Chip Select (CS/) pin at one of four sockets.

One chip

select line will be enabled when the value on the system address bus is

betwee~o

and

l~(hexadecimal).

In addition when the three most significant address lines are low
(i.e. the address is less than 1FFF) during a memory read cycle, the output
from the 74LSOO at A39-3 is NANDed withMEMR/ to produce a ready indication

•

PROM RDY IN/ for the CPU set.

PROM RDY IN/ is generated in time to allow

all ROM/PROM reads to occur without any wait states.

PROM RDY IN has the

same timing as RAM RDY IN/, as shown in Figure 3-7.
Whenever one of the ROM/PROM devices are read, the data from the
chip's output pins (01-08) is placed on the memory data bus (DMO-DM7)
which is interfaced to the system bus via two Intel 8216 bidirectional
bus drivers (at A55 and A56) , as described in Section 3.2.2.

•

3-23

•
.
T2

Tl

T4

T3

ADR0ADRF

•

MEMORY ADDRESS

ADV MEMW/
OR MEMR/

•

CEI

RAM FDYIN/
DATA BUS
DURING READ

)C---------

----------

- --------

-----------....~

-~'-t

DATA FROM RAM

DATA BUS
DURING WRITE

= ===---~X-9__-.~~~ ~ ~ =-~

=~--~ ~ -= ~ -=

• DATA TO RAM

FIGURE 3-7

•

RAM ACCESS TIMING

•
3-24

•

3.2.5

SERIAL I/O INTERFACE
The Serial I/O Interface logic provides the System 80/10 with a serial

data communications channel that can be programmed to operate with most

•

of the current serial data transmission protocols, synchronous or asynchronous.

Baud rate, character length, number of stop bits and even/odd

parity are program selectable.

In addition, the serial I/O Interface can

be configured (through jumper connections) as an EIA RS232C interface or
as a Teletype-compatible current loop interface.

•

The Serial I/O Interface logic consists primarily of an Intel 8251
USART device and a counting network for baud rate selection, as shown
on sheet 4 of the SBC80/10 schematic (Appendix B).

Before describing

the specific operation of the Serial I/O logic however, we will summarize
the general operational characteristics of the 8251 USART, because it
essentially defines the character of the Serial I/O Interface.

•

3.2.5.1

INTEL®8251 OPERATIONAL SUMMARY

The 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter
designed specifically for the 8080 Microcomputer System.

Like other I/O

devices in the 8080 Microcomputer System its functional configuration is
programmed by the systems software for maximum flexibility.

The 8251 can

support virtually any serial data technique currently in use (including

•

IBM "Bi-Sync").
Modem Control
The 8251 has a set of control inputs and outputs that can be used
to simplify the interface to almost any Modem.

The modem control signals

are general purpose in nature and can be used for functions other than
Modem control, if necessary.
DSR (Data Set Ready)

•

The DSR input signal is general purpose in nature.

Its condition

can be tested by the CPU using a Status Read operation.

The DSR input

is normally used to test Modem conditions such as Data Set Ready.

3-25

DTR (Data Terminal Ready)
The DTR output signal is general purpose in nature.

It can be set

•

"low" by programming the appropriate bit in the Command Instruction word.
The DTR output signal is normally used for Modem control such as Data

•

Terminal Ready or Rate Select.
RTS (Request to Send)
The RTS output signal is general purpose in nature.

It can be set

"low" by progrannning the appropriate bit in the Comnand Instruction word.
The RTS output signal is normally used for Modem control such as Request
to Send.
CTS (Clear to Send)

•

A "low" on this input enables the 8251 to transmit data (serial) if
the TxEN bit in the Connnand byte is set to a "one".

This is very important

to remember!

•

USART
PIN CONFIGURATION
0,
03

0,
On

R.D

Ver.

GND

R;C

D.

DTR

Os

RTS

Dr,

DSR

0,
T.C

WR

cs
I:/D

rm
R.RDY

RESET
ClK
T.O
hEMPTY
CTS

Pm Name

0,·00
C/O
RD
WR
CS
ClK
RESET
T.C
TKO
R.C
R.D
R.RDY
TxRDY

Pin Function

Data Bus (8 hits'

~!. ~:;~:~::i;--

Control or Data IS 10 he Written or Read

otR

0011,111 Terminal Ready

Read Data CommiJnd

SYNDE T

Write DatJ or Control Command

ATS
CTS
r.E

Sync De.ee.
ReQue~t 10 Sf.nd DatI
Clear to Send Dati
T,"ansnlltler Empty
+5 Vol. Supply

Chip Enabl.
Cloc:~ Pulse nTL)

Reset
Transmitter Clock

Vee
GND

Ground

Tr aosmlt fer D.lta
Receiver Clock
Ap.ceivIf O"tl
Receiver Rp.ady (hiK chMactef tor 8080)

•

Transminer Ready heady for char. from 8080'

SYNDET
ToROY

..
FIGURE 3-8

8251 PIN ASSIGNMENTS

TXRDY (Transmitter Ready)
This output signals the CPU that the transmitter is ready to accept
a data character.

It can be used as an interrupt to the system or for

•

•

polled operation when the CPU can check TXRDY using a status read operation.

TXRDY is active only when CTS is enabled.

TXRDY is automatically

reset when a character is loaded from the CPU.

•
TXE (Transmitter Empty)
When the 8251 has no characters to transmit, the TxE output will
go "high".
CPU.

•

It resets automatically upon receiving a character from the

TXE can be used to indicate the end of a transmission mode, so that

the CPU "knows" when to "turn the line around" in the half-duplexed operational mode.
In synchronous mode, a "high" on this output indicates that a character has not been loaded and the SYNC character or characters are about
to be transmitted automatically as "fillers".
TXC (Transmitter Clock)

•

The Transmitter Clock controls the rate at which the character is
to be transmitted.

In the synchronous transmission mode, the frequency

of TXC is equal to the actual Baud Rate (IX).

In asynchronous transmission

mode, the frequency of TXC is a multiple of the actual baud rate.

A por-

tion of the mode instruction selects the value of the multiplier; it can
be IX, 16X or 64X the baud rate.

•

For example:
If Baud Rate equals 110 Baud,
TXC equals 110 Hz (IX)
TXC equals 1.76 kHz (16X)
TXC equals 7.04 kHz (64X).
If Baud Rate equals 9600 Baud,
TXC equals 614.4 kHz (64X).
The falling edge of TXC shifts the serial data out of the 8251.
RXRDY (Receiver Ready)
This output indicates that the 8251 contains a character that is

•

ready to be input to the CPU.

RXRDY can be connected to the interrupt

structure of the CPU or for polled operation the CPU can check the con-

3-27

dition of RXRDY using a status read operation.
set when the character is read by the

RXRDY is automatically re-

cpu.

•

RXC (Receiver Clock)
The Receiver Clock controls the rate at which the character is to
be received.

In synchronous mode, the frequency of RXC is equal to the

actual baud rate (IX).

..

In asynchronous mode, the frequency of RXC is

a multiple of the actual baud rate.

A portion of the mode instruction

selects the value of the multiplier; it can be IX, 16X or 64X the baud

•

rate.
For example:
If Baud Rate equals 300 Baud,
RXC equals 300 Hz (IX)
RXC equals 4800 Hz (16X)
RXC equals 19.2 kHz (64X).

•

If Baud Rate equals 2400 Baud,
RXC equals 2400 Hz (IX)
RXC equals 38.4 kHz (16X)
RXC equals 153.6 kHz (64X).
Data is sampled into the 8251 on the rising edge of RXC.
Note:

In most communications systems, the 8251 will be handling both
the transmission and reception operations of a single link. Consequently, the Receive and Transmit Baud Rates will be the same.
Both TXC and RXC will require identical frequencies for this
operation and can be tied together and connected to a single frequency source (Baud Rate Generator) to simplify the interface.

SYNDET (SYNC Detect)

t

This pin is used in SYNCHronous Mode only.

It is used as either in-

put or output, programmable through the Control Word.
"low" upon RESET.

•

It is reset to

When used as an output (internal Sync mode), the

SYNDET pin will go "high" to indicate that the 8251 has located the SYNC
character in the Receive mode.

If the 8251 is programmed to use double

Sync characters, then SYNDET will go "high" in the middle of the last
bit of the second Sync character.

SYNDET is automatically reset upon a

3-28

•

•

Status Read operation.
When used as an input, (external SYNC detect mode), a positive going
signal will cause the 8251 to start assembling data characters on the
falling edge of the next RXC.
be removed.

Once in SYNC, the "high" input signal can

The duration of the high signal should be at least equal to

the period of RXC.
Programming the 8251
Prior to starting data transmission or reception, the 8251 must be

•
•

loaded with a set of control words generated by the CPU.

These control

signals define the complete functional definition of the 8251 and must
immediately follow a Reset operation (internal or external).
The control words are split into two formats:
1.

Mode Instruction,

2.

Command Instruction.

Both the Mode and Command instructions must conform to a specified sequence for proper device operation.

The Mode Instruction must be inserted

immediately following a Reset operation, prior to using the 8251 for data
communication.
All control words written into the 8251 after the Mode Instruction
will load the Command Instruction.

Command Instructions can be written

into the 8251 at any time in the data block during the operation of the

•

8251.

To return to the Mode Instruction format a bit in the Command In-

struction word can be set to initiate an internal Reset operation which
automatlcally places the 8251 back into the Mode Instruction format.

Com-

mand Instructions must follow the Mode Instructions or Sync characters
(see Figure 3-9),
Mode Instruction:
This format defines the general operational characteristics of the
8251.

It must follow a Reset operation (internal or external).

Once the

Mode instruction has been written into the 8251 by the CPU, SYNC charac-

•

ters or Command instructions may be inserted.
The 8251 can be used for either synchronous or asynchronous data communications.

The two least significant bits of the Mode Instruction control
3-29

•
..
..
RESET

•

~

C/O, 1

MODE INSTRUCTION

C/O, 1

SYNC CflARACTfR 1

._-----_._-- ._-----C/O· 1

SYNC CHARACTER 2

SYNC MODE
ONLY'

r------------j
C/D· 1

CO~'MAND INSTRUCTION

f------------C/O· 0

c!£i·

I

---- .-~~~~-. -----J
]-_.
__. __ .. ------COMMAND INSTRUCTION
.--

•

DATA

C/O· 1

COMMAND INSTRUCliON

Chilr:tclrr IS ~klppp.d II MODE IOs1rurtion
has Jlr09rilnllll~d the 8251 to slIlgle Ch.H,lctf'r InlNnal SYNC
Mode. Both SYNC Chil';It~tJ!fS are \k'PIWd If MODE InstrUf';tiOrl

-The second SYNC

has programmed 'he 815110 ASYNC Illode.

FIGURE 3-9

•

TYPICAL 8251 DATA BLOCK

word specify synchronous or asynchronous operation.

The format for the

.

remaining bits in the control word depends on the mode chosen by bits 0
and 1.

Figure 3-10 shows the control word format for the asynchronous

mode, while Figure 3-11 illustrates the control word format for the synchronous mode.
Command Instruction:
Once the functional definition of the 8251 has been programmed by the
Mode Instruction and the Sync Characters are loaded (if in Sync Mode) then

•

•

the device is ready to be used for data communication.

The Command Instruc-

tion controls the actual operation of the selected format.
as:

Functions such

Enable Transmit/Receive, Error Reset and Modem Controls are provided

by the Command Instruction.
Once the Mode instruction has been written into the 8251 and Sync
characters inserted, if necessary, then all further "control writes"
(C/D = 1) will load the Command Instruction.

A Reset operation (internal

or external) will return the 8251 to the Mode Instruction Format.
Figure 3-12 illustrate the format of a Command Instruction control

•

word.
Status Read Definition
In data communication systems it is often necessary to examine the
"status" of the active device to ascertain if errors have occurred or
other conditions that require the processor's attention.

•

The 8251 has

facilities that allow the programmer to "read" that status of the device
at any time during the functional operation.
A normal "read" command is issued by the CPU with the

c/n

input at one

to accomplish this function.
Some of the bits in the Status Read Format have identical meanings
to external output pins so that the 8251 can be used in a completely

•

Polled environment or in an interrupt driven environment (refer to Figure
3-13) •

8251 DATA TRANSFERS
Once programmed, the 8251 is ready to perform its communication functions.

The TXRDY output is raised "high" to signal the CPU that the 8251

is ready to receive a character.

This output (TXRDY) is reset automatical-

ly when the CPU writes a character into the 8251.

On the other hand, the

8251 receives serial data from the MODEM or I/O device; upon receiving an
entire character the RXRDY output is raised "high" to signal the CPU that

•

the 8251 has a complete character ready for the CPU to fetch.
reset automatically upon the CPU read operation.

3-31

RXRDY is

r 5,1

5, IU·lplN! L,

•

I', I 1,1
R,

8

L

BAUD flA 1 [ FACTOR

0

1

0

1

0

1

1

OXI

IluXI

lu4X)

>--.

<----.

0
SYNCMODE

---. - - --

..

CflMIACl[fI UNGTII

0

1

fSCS}SDI fP}fNf L11 L,

1

1

7
BITS

8

f

1

0

0
6
BITS

I

0

10 1

1-0

5BITS

BITS

CHARAC1[R l f"GlIl

,

1

..

1

6

7

'-8

BITS

OIT,

BITS

.•.

Bl1S

_-- ---

1

--

.

STOP BITS

0

1

0

1

0

0

1

1

1 - - ---rINVALID

0

0

5

[VEN PARITY G[NEflATION/CHE CK
0·000
1· EVEN

or

I

0

.-. --_

PAfllTY [NAnlE
o 'DISABLE
1 ' lNMll [

NUMflER

0

- - - - PARITY ENABLE
(1 - ENABLE)
10 - DISABLEI

~~
BITS
BITS

BIT

EVEN PARITY GENERATION/CHE CK
l ' EVEN

o·

-

Mode Instruction Format, Asynchronous Mode

DOD

EXTERNAL SYNC DETECT
1 • SYNDE T IS AN INPUT
0 2 SY'IIDET IS AN OUTPUT

•

~NGlECHARACTERSYNC

1· SINGl E SYNC CHARACTER

O' DOUBLE SYNC CHARACTER·
TRANSMITTER OUTPUT

hD

STJ;;-l
BrrS

L

MARKING

Mode Instruction Format, Synchronous Mode
RECEIVER INPUT

START
BIT

R.o

•

ST6rI
BrTS

L
CPU BYTES 15 8 BITS/CHARI

TRANSMIS-~ION

FORMA T
DATA

CPU BYTE 158 BITs/eIlAR)

DATA

CI~~RACr[R

,

CH~RACTERS

ASS[MRLED SERIAL DATA OUTPUT IhOI

n:..

ASSEM8lfD SUUIIl DIITA OUTPUT IhOI
START
Bll

oMA CHARIICTrR

r

DA TA CII 1\ A_C_T_E_fl_S____--l

STOD
BITS

RECEIVE rORMAT

RECEIVE [OHMA1

SERIAL DAIAINPUT milO)

SERIAL OATA INPUT IfhOI

L-____

~

•
..

OAT A CIIAI<:._C_T_E_R_S___......J

O_A_T_A_C_I_IA~R~/\-C-l-L-R--~------~---~_j~~~

CPU BVT( SIr, 8 lIlIS!CIIAfli

_____

;

,

DATA CH;flACl I flS

CPU BYTE 158 BITS/CHARI'

i

DATA CIIARACT(R

L -_ _ _-4_1

·NOTE IF CIIARAcnR LFNc;nl IS DEFINED AS 5. 6 OR 7
BITS THE UNUSED 81TS ARE SET 10 "Z[RO"

FIGURE 3-10

ASYNCHRONOUS MODE

FIGURE 3-11

3-32

SYNCHRONOUS MODE

•

•
I

D,

I

Ol I

111

lIlTS

I

D,

0,

En IsnRKI R,l

I

D,

Do

DTH l'dN

l.

•

TRAN"MlT [NAOLr
T p.na!Jl~
0

d"dhle

DATA TfllMlNAL

'----

flEADY
"high" will force OTR
OlJtput to lr)ro

k - -_ _

REC[lVE ENAIlL [
1 " f!f1.1hlf'
0' di';OIhle

.

SEND BIIEAK
CHAf1ACTfR

..

1 ::- forcc') T xD "low
nornl,ll Opr~I,1I101l

o ;;

•

-------------

PE. Ol. FE

.

_.-

~----

-_._-

FIGURE 3-12

•

REOUEST TO SEND
"high" will force fiTS

outPllt to lern

-

•

ERnOR IllSn
1 ' rpset all error flags

-----_ .. _--------

INTERNAL HLSFT
"high" relurn!. fllS1 to

Mode Imtruction Forillilt

ENTE R HUN T MODE
1 r.oOlhle
Ch.1tacters

SC,lfCh for S ync

COMMAND INSTRUCTION FORMAT

3-33

•
..
SMIE D£FINITIONS AS 110 PINS

PARITY ERHOR
The PE flag is sr.! whr.n a p.uity
deH!ctl~l. It IS reset hy
the ER bit of Ihe Command
InslrUC1l0n. PE dor.s nol inhibit
o~ration of the 8251,

•

error IS

OVERRUN ERROR
The OE fl0I9 IS set when the CPU
doc'i not read a character before
the nC)lt one becomes aVifilable.
11 is reset by the E R bit of the

Coml1l.1nd Instruction. DE does
not Inhihit

opl~ration

of the 8251;

howevcr, rhp. PH'Vlously overrun

characler

IS

lost.

•

FnAMING rRROR IA,yoc only)
The FE flag is set when a \/a"l1
Stop bit is not d~lr.ch!d at the
end of every Chariferer. It is reset
by the [R bit of the Command
Instruction. FE does nol irllllhlt
the operMian of the 8251.

FIGURE 3-13

STATUS READ FORMAT

The 8251 cannot begin transmission until the TXEN (Transmitter Enable)

•

bit is set in the Command Instruction and it has received a Clear To
Send (CTS) input.

The TXD output will be held in the marking state upon

Reset.
Asynchronous Mode (Transmission):
Whenever a data character is sent by the CPU the 8251 automatically
adds a Start bit (low level) and the programmed number of Stop bits to
each character.

Also, an even or odd Parity bit is inserted prior to

the Stop bites), as defined by the Mode Instruction.
3-34

The character is

•

•

then transmitted as a serial data stream on the TXD output.

The serial

data is shifted out on the falling edge of TXC at a rate equal to 1/16 or
1/64 that of the TXC, as defined by the Mode Instruction.

BREAK charac-

ters can be continuously sent to the TXD if commanded to do so.
When no data characters have been loaded into the 8251 the TXD output remains "high" (marking) unless a Break (continuously low) has been
programmed.

•

Asynchronous Mode (Receive):
The RXD line is noramlly high.
the beginning of a START bit.

A falling edge on this line triggers

The validity of this START bit is checked

by again strobing this bit at its nominal center.

If a low is detected

again, it is a valid START bit, and the bit counter will start counting.
The bit counter locates the center of the data bits, the parity bit (if
it exists) and the stop bits.

•

flag is set.

Data and parity bits are sampled on the RXD pin with the

rising edge of RXC.

If a low level is detected as the STOP bit, the

Framing Error flag will be set.
ter.
8251.

The STOP bit signals the end of a charac-

This character is then loaded into the parallel I/O buffer of the
The RXRDY pin is raised to signal the CPU that a character is ready

to be fetched.

•

If parity error occurs, the parity error

If a previous character has not been fetched by the CPU,

the present character replaces it in the I/O buffer, and the OVERRUN flag
is raised (thus the previous character is lost).
can be reset by a command instruction.

All of the error flags

The occurrence of any of these

errors will not stop the operation of the 8251.
Synchronous Mode (Transmission):
The TXD output is continuously high until the CPU sends its first
character to the 8251 which usually is a SYNC character.

When the CTS

line goes low, the first character is serially transmitted out.
ters are shifted out on the falling edge of TXC.

All charac-

Data is shifted out at

the same rate as the TXC.

•

Once transmission has started, the data stream at TXD output must
continue at the TXC rate.

If the CPU does not provide the 8251 with a

3-35

character before the 8251 becomes empty, the SYNC characters (or character if in single SYNC word mode) will be automatically inserted in the
TXC data stream.

In this case, the TXEMPTY pin will momentarily go

high to signal that the 8251 is empty and SYNC characters are being sent
out.

•
•

The TXEMPTY pin is internally reset by the next character being writ-

ten into the 8251.

•

Synchronous Mode (Receive):
In this mode, character synchronization can be internally or externally achieved.

If the internal SYNC mode has been programmed, the re-

ceiver starts in a HUNT mode.
the rising edge of RXC.

Data on the RXD pin is then sampled in on

The content of the RX buffer is continuously

compared with the first SYNC character until a match occurs.

If the 8251

•

has been programmed for two SYNC characters, the subsequent received
character is also compared.

When both SYNC characters have been detected,

the USART ends the HUNT mode and is in character synchronization.

The

SYNDET pin is then set high, and is reset automatically by a STATUS READ.
In the external SYNC mode, synchronization 'is achieved by applying
a high level on the SYNDET pin.

The high level can be removed after one

•

RXC cycle.
Parity error and overrun error are both checked in the same way as
in the Asynchronous receive mode.
The CPU can command the receiver to enter the HUNT mode if synchronization is lost.
3.2.5.2

SERIAL I/O CONFIGURATIONS

•

The 8251 USART presents a parallel, eight-bit interface to the CPU
set via the system data bus (DBO-DB7) and presents an EIA RS232C* or TTY
current loop* interface to an external device (via edge connector J3).
The 8251's interface with the CPU Set is enabled by a low level on its
chip select (CS/) pin.

CS/ is low when the I/O address on the system

address bus is between EC and EF (hexadecimal).

*

Electrical interfaces provided on SBC 80/10

3-36

Address bits 2 through 7

•

•

are decoded (at A14) to produce the CS/ input.

The least significant

address bit, ADRO, is applied to the 8251s CID input (pin 12) thus indicating a control (if set) or data (if reset) byte on the data bus.

•

1/0 ADDRESS

•

(BASE 16)

COMMAND

FUNCTION

ED OR EF

OUTPUT

CONTROL WORD

EC OR EE

OUTPUT

DATA

ED OR EF

INPUT

STATUS

EC OR EE

INPUT

DATA

TABLE 3-1

SERIAL COMMUNICATION (8251)
ADDRESS ASSIGNMENTS

•

An

output instruction (IOW/ is true) to port ED or EF (CSI is low and

ADRO is high) causes the 8251 to accept a control byte through its data
bus pins.

The control byte can be either a mode instruction or a com-

mand instruction, depending on the sequence in which it is sent.

The

various bits in the mode control word specify the baud rate multiplexer,
character length, parity and the number of stop bits as described in Section 3.2.5.1.

Note that the actual baud rate selected is dependent on

the configuration of the baud rate jumper network (refer to Section
3.2.5.3).

The various bits in the command control word instruct the USART

to enable/disable the receiver and transmitter, to reset errors, to re-

•

set internal control and return to the mode control cycle, and to setl
clear the Data Terminal Ready output.

An output instruction to port EC or EE (CS/ and ADRO are low) causes
the 8251 USART to accept a data byte through its data bus pins.

Bit 0

is the least significant bit and bit 7 is the most significant bit.

•

The

8251 will subsequently transmit the data byte (if the transmitter is

•

enabled), in serial fashion, to the external device as described in Section 3.2.5.1.

An input instruction (IOR/ is true) to port ED or EF (CS/ is low
and ADRO is high) causes the 8251 USART to place a status byte onto the
system bus.

The status bits are the result of status and error checking

functions performed within the USART (see Section 3.5.1).

An input instruction (IOR/ is true) to port EC or EE (CS/ and
ADRO are low) causes the USART to output a data byte (previously received from the external device) from its data bus pins.

•

Bit 0 is the

least significant bit and bit 7 is the most significant bit.
Timing for the USART's internal function is provided by the 02TTL
signal (see Section 3.2.1.1).

The USART is reset by the occurrence of

a high level on the RESET line.
The 8251 USART transmits and receives serial data, synchronously or
asynchronously, as described in Section 3.2.5.1.

By jumper-connecting the

•

8251 pins to different external lines, the Serial I/O logic can present
either a Teletype-compatible current loop interface or an EIA RS232C
interface to an external device.

If the TTY-compatible current loop in-

terface is used, the connections listed in Table 3-5 are required (see
Section 3.3).
If the EIA RS232C interface is used, the connections listed in Table

•

3-6 are required (see Section 3.3).
3.2.5.3

BAUD RATE CLOCK GENERATION

The baud rate clock network consists of a 93S16 'divide-by-15,
counter, two 74161 'divide-by-16, counters and wire-wrap jumpers for
baud rate clock selection.

The 93S16 counter is driven by the oscilla-

tor output (OSC) from the CPU Set.
turn, drives the two 74161 counters.

The QD output from this counter, in
The outputs from these counters,

each providing a different clock frequency, are tied to jumper pins that
3-38

•

•

can be connected to the BAUD RATE CLK line.

The available frequencies

are listed in Table 3-9 (located in Section 3.3.2). Recall that the effective baud rate of the 8251 USART is also dependent on the state of
the 8251's internal frequency divider and the mode of operation (refer
to Section 3.2.5.1).

•

by 1, 16 or 64 •
3.2.5.4

•

The 8251 is capable of dividing the baud rate clock

SERIAL I/O INTERRUPTS

The Serial I/O logic can be configured with different forms of an
interrupt request mechanism.

By connecting jumper pair 16-17 and discon-

necting 15-16, the user can allow the 8251's Receiver Ready (RXRDY) output (pin 14) to generate an interrupt request INT51/) to the CPU Set.
RXRDY goes high whenever the receiver enable bit of the command word has
been set and the 8251 contains a character that is ready to be input to
the CPU Set.

•

The user can also choose to have the 8251's Transmitter

Ready (TXRDY) or the Transmitter Empty (TXE) output activate the INT51/
interrupt request.

If jumper pair 19-21 is connected, a high on TXRDY

(pin 15) will activate INT51/.

If jumper pair 18-19 is connected in-

stead, an active TXE (pin 18) output will generate INT51/.
high when the 8251 has no characters to transmit.

TXRDY is high when

the 8251 is ready to accept a character from the CPU Set.

•

TXE goes
Both TXE and

TXRDY are enabled by setting the transmit enable bit of the command word
Notice on the schematic that, if jumper pairs 19-20 and 15-16 are connected~

Serial I/O interrupts are inhibited.

Upon receiving an interrupt, the program can determine the actual
condition which is responsible for the interrupt (RXRDY, TXRDY or TXE)
by reading the status of the 8251 device as described in Section 3.2.5.1.
The interrupt request will be removed when the data is transferred to/
from the 8251, as required.

Note that the TXE or TXRDY output will be

high, and consequently maintain an interrupt request, during all idle
periods, since the 8251's transmit buffer will remain empty.

To disable

the transmitter, and the resultant interrupt request, the program can

•

issue a command instruction to the 8251 with the TXEN bit (bit 0) equal
to zero (refer to Section 3.2.5.1).

3-39

The transmitter should not be disabled

•

until TXE is high.
3.2.6

PARALLEL I/O INTERFACE
The Parallel I/O Interface logic on the SBC 80/10 provides forty-

•

eight (48) signal lines for the transfer and control of data to or from
peripheral devices.

Eight lines have a bidirectional driver and termina-

tion network permanently installed.
committed.

•

The remaining forty lines are un-

Sockets are provided for the installation of active driver

networks or passive termination networks.

The optional drivers and

terminators are installed in groups of four by insertion into the 14pin sockets.
All forty-eight signal lines emanate from the I/O ports on two Intel

•

8255 Programmable Peripheral Interface devices, as shown on sheet 5 of
the SBC 80/10 schematic (Appendix B).

The two 8255 devices allow for

a wide variety of I/O configurations.

Before describing the possible

configurations, however, we will summarize the general operational characteristics of the 8255 device.
3.2.6.1

INTEL®8255 OPERATIONAL SUMMARY

The 8255 contains three 8-bit ports (A, B and C).

•

All can be con-

figured in a wide variety of functional characteristics by the system
software but each has its own special features or "personality" to further
enhance the power and flexibility of the 8255.
Port A:

One 8-bit data output latch/buffer and one 8-bit data input latch.

Port B:

One 8-bit data input/output latch/buffer and one 8-bit data in-

•

put buffer.
Port C:

One 8-bit data output latch/buffer and one 8-bit data input buffer
(no latch for input).

•

This port can be divided into two 4-bit

ports under the mode control.

Each 4-bit port contains a 4-bit

latch and it can be used for the control signal outputs and
status signal inputs in conjunction with Ports A and B.
The 8080 CPU dictates the operating characteristics of the ports by
outputting two different types of control words to the 8255:

3-40

•

•

(1) mode definition control word (bit 7 = 1)
(2) port C bit set/reset control word (bit 7

0)

Bit 7 of each control word specifies its format, as shown in Figures 3-14
and 3-15, respectively.
Mode Selection
There are three basic modes of operation that can be selected by the
system software:

•

Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bidirectional Bus
When the RESET input goes "high" all ports will be set to the Input
mode 0 (i.e., all 24 lines will be in the high impedance state).

After

the RESET is removed the 8255 can remain in the Input mode with no ad-

•

ditional initialization required.

During the execution of the system pro-

gram, the other modes may be selected using a single OUTput instruction.
This allows a single 8255 to service a variety of peripheral devices with
a simple software maintenance routine.
The modes for Port A and Port B can be separately defined, while
Port C is divided into two portions as required by the Port A and Port

•

B definitions.

All of the output registers, including the status flip-

flops, will be reset whenever the mode is changed except for OBF in modes
1 and 2.

Modes may be combined so that their functional definition can

be "tailored" to almost any I/O structure.

For instance; Group B can be

programmed in Mode 0 to monitor simple switch closings or display computational results; Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt-driven basis.
Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a single
OUTput instruction (see Figure 3-16).

•

This feature reduces software re-

quirements in Control-based applications.
When Port C is being used as status/control for Port A or B, these

3-41

•
•

•

CONTROL WORD

I I 1 I I

PIN CONFIGURATION
'0.3

,...

'0.1

'AS

'A'

06

05

D.

OJ

1I I I
0,

0,

Do

L~

'A'

Po.,

'0.0

iii)

Wi!

cs

I

35 J RESn

GNO[ ,

3. ] 0.

A' ( •
0.0 [

0,

33] 0,

9

,e'L

'0

PCI [

"

PCS (

"

PC.

32

3'

8255

30

19

_1 0.
J 0.

1>

-J

0,

Vee

MODE SELECTION
0= MODE 0
1 =MODE 1

'----

15 ] '8'

PCl

~..

'80

23

'81

r ,q
'0

on71

PBG

l

•

PORT B
1 =INPUT
0= OUTPUT

18 ] 0.

76

\

PORT C ILOWER)
1 = INPUT
0= OUTPUT

L-....

:J 0.
J OJ

GROUP B

'B5

I.n.
,. I rllJ

27

/

GROUP A

\

•

PORT C IUPPER)
1 = INPUT
0= OUTPUT

PIN NAMES

-

PORTA
1 = INPUT
0= OUTPUT

.

~.

MODE S£lECTION
00 = MODE 0
01 = MODE 1
IX r MODE 2

MODE SET FLAG
1· ACTIVE

FIGURE 3-14 8255 PIN

FIGURE 3-15

ASSIGNMENTS

•
.-

MODE DEFINITION

CONTROL WORD FORMAT

3-42

•

•
•

bits can be set or reset by using the Bit Set/Reset operation just as if
they were data output ports.
Interrupt Control Functions
When the 8255 is programmed to operate in Mode 1 or Mode 2, control
signals are provided that can be used as interrupt request inputs to the
CPU.

The interrupt request signals, generated from Port C, can be in-

hibited or enabled by setting or resetting the associated INTE flip-flop,

•

using the Bit set/reset function of Port C.
This function allows the Programmer to disallow or allow specific
I/O devices to interrupt the CPU without effecting any other device in
the interrupt structure.
INTE flip-flop definition:
(BIT-SET) - INTE is SET - Interrupt enable
(BIT-RESET) - INTE is RESET - Interrupt disable

•

Note:

All Mask flip-flops are automatically reset during mode selection
and device Reset.

CONTROL WORD

•

BIT SET/RESET
1 =SET
0" RESET

BIT SElm ESEl FLAG
O· ACTIVE

•

FIGURE 3-16 BIT SET/RESET CONTROL WORD FORMAT

3-43

•

Operating Modes
Mode 0 (Basic Input/Output):
This functional configuration provides simple Input and Output operations for each of the three ports.

No "handshaking" is required, data

is simply written to or read from a specified port.

•

Mode 0 timing is

•

illustrated in Figure 3-17.
Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports.

•

• Any port can be input or output.
· Outputs are latched.
· Inputs are not latched.
Sixteen different Input/Output configurations are possible in this Mode.
Figure 3-18 shows two possible configurations.
Mode 1 (Strobed Input/Output):
This functional configuration provides a means for transferring I/O
data to or from a specified port in conjunction with strobes or "handshaking" signals.

•

In Mode 1, Port A and Port B use the lines on Port C

to generate or accept these "handshaking" signals.
Mode 1 Basic Functional Definitions:
Two transfer ports (A and B).
Each transfer port contains one 8-bit data port and 4 bits from
one half of the control/data port (Port C).
The 8-bit data port can be either input or output.
and outputs are latched.

•

Both inputs

Input Control Signal Definition for Mode 1
STB (Strobe Input)
A "low" on this input loads data into the input latch.

IBF (Input Buffer Full F/F)
A "high" on this output indicates that the data has been loaded into

3-44

•

•
•

•

BASIC INPUT
TIMING (07-00
FOLLOWS INPUT,
NO LATCHING)

INPUT

10[LAY1IME
FROM AD

•

WI1
BASIC OUTPUT
TIMING (OUTPUTS
LATCHED)

'----!------i-J

I-------X
- - - - - - -

X------

SET UP VIOLATION

-----.

- - ___ _

OUTPUT
[

~

~. I DATA
HOLD

OUTPUT DATA
INVALID

___ IDELAYTIME
FROM WR

•
•

FIGURE 3-17

01

Of;

D5

[).,

D]

07

[)1

8255 MODE 0 TIMING

DO

0,

D.

0]

8255

D,

0,

Do

1

\1

8155

D,·oo ...- , - - - - -....

D,DO ..
·----

B

•

D5

l' I 0 I 0 1, 1, I 0 l'

1'10101'111010101

•

D6

--/..!.- PB, PBO

FIGURE 3-18

B

EXAMPLES OF MODE 0 CONFIGURATION
3-45

.--/_8__

PB,.PBO

the input latch; in essence, an acknowledgment.

IBF is set by the falling

edge of the STB input and is reset by the rising edge of the RD input.

•
.

INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an input device is requesting service.

INTR is set by the rising edge of STB

if IBF is a "one" and INTE is a "one".
of RD.

It is reset by the falling edge

This procedure allows an input device to request service from the

CPU by simply strobing its data into the port.

•

INTE A
Controlled by bit set/reset of PC4.
INTE B
Controlled by bit/reset of PC 2.
Figure 3-19 illustrates the Mode 1 input configuration, while Figure
3-20 shows the basic timing for Mode 1 input.
Output Control Signal Definition for Mode 1
OBF (Output Buffer Full F/F)
The OBF output will go "low" to indicate that the CPU has written
data out to the specified port.

•

The OBF F/F will be set by the rising

edge of the WR input and reset by the falling edge of the ACK input signal.
ACK (Acknowledge Input)
A "low" on this input informs the 8255 that the data from Port A
or Port B has been accepted.

In essence, a response from the peripheral

•

device indicating that it has received the data output by the CPU.
INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU when an
output device has accepted data transmitted by the CPU.

INTR is set by

the rising edge of ACK if OBF is a "one" and INTE is a "one".

It is

reset by the falling edge of WR.
INTE A
Controlled by bit/reset of PC6.

3-46

•

MODE 1 (PORT A'

•

CONT ROL WORD

0, D. O. O. OJ 0, O.

o.

l' I 011 11 1';0MX1X1

L

PC"

1 -INPUT,

O· OUTPUT

Ro2

pc•. ,

--f--

110

MODE 1 (PORT Bl

CONTROL WORD

•

INTRa

RD-

FIGURE 3-19

•

MODE 1 INPUT CONFIGURATION

MODE 1 (STROBED INPUTI
BASIC TIMING

ISF
(INPUT BUFFEH FULL'

•

~'''''~'--

NO PROTECTION
FOR THIS OPERATION

DATA
INPUT

~-----------------4------.

INHRNAL
INPUT LATCH

\

'------

INTR

•

FIGURE 3-20

8255 MODE 1 INPUT TIMING

3-47

•

INTE B
Controlled by bit set/reset of PC2.
Figure 3-21 illustrates the Mode 1 output configuration, while Figure 3-22
shO\lTS basic Mode 1 output timing.

MOOE 1 IPORT AI

MOOE 1 IPORT BI

CONT ROL WORD

CONTROL WORD

0, 0, 0, 0. 0, 0, 0, 00

I, I 01, 10]TlofXJX1>----:----1

OI\.TACHAnI\CTtr~

L -_______...;, ....
, _ _ __
-'

Synchronous Mode. Transmission Format

•

FIGURE 3-26.

SYNCHRONOUS OPEMTION

3-65

TABLE 3-9.

•

BAUD RATE SELECT I ON

EFJ..'ECTIVE MUD RATE (Hz)
JUMPER
CONNECTION

ASYNClffiONOUS 1\10DE·

SYNCllllONOUS MODE

BAUD RATE FACTOR=16(2) BAUD RATE FACTOR=64 (2)

38,400

10-4

11-4
12-4
5-4
6-4
7-4
(1)
8-4
(1)
8-4 }
56-5;

4800
2400
1200
600
300
150
75

9600(3)
4800
2400
1200
600
300

19,200
9600
4800

-

6980

110 (T'IY)

Note: (1) If jumper pair 56-57 is not connected, the frequency at
jumper pole 8 is 4.8 KHZ. If jumper 56-57 is connected, however, the frequency at jumper pole 8 is 6.98 KHZ which, with
a programmed baud rate factor of 64, provides an effective
baud rate of approximately 110 baurl for Teletype use.
(2)

Baud rate factor is software .se1ectab1e.

(3)

Caution:

Baud Rate Factor

c

16

In the following paragraphs, we will define the capabilities of each port

..

•
•

and summarize, in tables, that information which is necessary to use the
port in each of its potential configurations.

Each table will list the

port I/O address, the control register address and the format for the control word which is output to the 8255 by the CPU Set and which specifies
the particular configuration to be used.

Each table will also summar!ze

all of the relevant information concerning the choice and use of driver/

•

termination networks, the data polarity, the connecting of jumpers and what
they enable, and any restrictions on the use of the other two ports in each
group.

Examples of suitable driver/termination networks are listed in

.

Section 8.1.1.
3.3.2.1

PORT 1 (GROUP 1 PORT A)

Port 1 is the only port that already includes a permanent bidirectional
driver/termination network (two 8226 Bidirectional Bus Drivers).

Port 1 is

also the only port which can be programmed to function in anyone of the
3-66

•

•

three 8255 operating modes, which were defined j,n Section 3.2.6,1.

Before

Port 1 is programmed for input or output in anyone of the three modes,
certain jumper connections must be made to allow the port to function properly in the chosen mode,

Other jumper connections must be made to enable

interrupts when Port 1 is in mode 1 or mode 2.
potential configurations for Port I,

In all, there are five

All of the necessary information for

implementing each configuration has been summarized in the following tables:

TABLE 3-10.

•

PORT 1 CONFIGURATIONS

2.

3.
4.

5.

Mode
Mode
Mode
Mode
Mode

0
0
1
1

2

Input
Output (Latched)
Input (Strobed)
Output (La tched)
Bidirectional

•
•

TABLE

Direction

Mode
1.

•

PORT 1 OPERATING MODES

3-67

Table
Table
Table
Table
Table

3-11
3-12
3-13
3-14
3-15

TABLE 3-11.

PORT 1, MODE 0 INPUT CONFIGURATION

PORT 1 ADDRESS: E4, CONTROL REGISTER ADDRESS: E7
7

CONTROL WORD FORMAT:

6

5

4

3

~

1

•

0

111 0 10111 x1Xlx1X{
DRIVER/TERMINATION NETWORKS: Two Intel®S226 Bidirectional Bus
Drivers permanently installed at A1 and A2.
DATA POLARITY:

Negative-true.

JUMPER CONNECTIONS:

41-42 to enable input at 8226's.

PORT 2 RESTRICTIONS: None; port 2 can be programmed for mode 0 or
mode 1, input or output (see Section 3.3.2.2).
PORT :I RESTRICTIONS: None; port 3 can be programmed for mode 0,
8-bit input or output, unless port 2 is in mode 1. (see Section3.3.2.3).

TABLE 3-12. PORT 1, MODE 0 LATCHED OUTPUT CONFIGURATION
PORT 1 ADDRESS: E4, CONTROL REGISTER ADDRESS: E7
CONTROL WORD FORMAT:

7

6

11 , 0

5

4

3

2

1

,0 ,0Ix I x I x I x I

Negative-true.

JUMPER CONNECTIONS:

•

0

DRIVER/TERMINATION NETWORKS: Two Intel@8226 Bidirectional Bus
Drivers permanently installed at A1 and A2.
DATA FOLARITY:

•
•

40-41 to enable output at 8226'5.

PORT 2 RESTRIL'TIONS: None; port 2 can be programmed for mode 0 or
mode 1, input or output (see Section 3.3.2.2).
PORT 3 RESTRICTIONS: None; port 3 can be programmed for mode 0,
input or output, unless port 2 is in mode 1 (see Section 3.3.2.3).

3-68

•

•

TABLE 3-13.

PORT 1, MODE 1 STROBED INPUT

CONFIGur~~TION

PORT 1 ADDRESS: E4, COI\'TROL REGI STER ADDRESS: E7
CONTROL WORn FORMAT:

7

6

5

4

3

2

1

0

111011111 x lxf xlxl

•

DRIVER/TER'.!INATION NETWORKS: Two Intel® 8226 Bidirectional Bus
Drivers permanently installed at Al and A2. A driver network must
be installed at A3 and a termination network must be installed at
A4.
DATA POLARI'IY: Negative-true. The polarity of Port 3 control outputi is dependent on the type of driver installed at A3.
JUl\lPER CO?\~ECTIONS: 41-42 to enable input at 8226 t s; connect 49-50
to enable interrupt request via I!\'T55/ .

•
•
•

PORT 2 RESTRICTIONS: None; port 2 can be programmed for node 0 or
mode 1, input or output (see Section 3.3.2.2).
PORT 3 RESTRICTIONS:
functions:

Port 3 bits perform the following dedicated

*Bits 0, 1 and 2 - dedicated to control of port 2 if port 2 is in
mode 1 (see Tables 3-17 to 3-20).
*Bit 3 - INTR (interrupt request) output for port 1.
*Bit 4 - STB/ (strobe) input for port 1.
*Bit 5 - rBF (input buffer full) output for port 1.
*Bit 6
can be used for input only. Bit 3 of control word
1
*Bit 7 - cannot be used.

3-69

TABLE 3-14.

PORT 1, MODE 1 LATCHED OUTPUT CONFIGURATION

•

PORT 1 ADDRESS: E4, CONTROL REGISTER ADDRESS: E7
CONTROL WORD FORMAT:

7

6

5

4

3

2

1

0

111 0 111 0 lXlXlXlXl
DRIVER/TER~.!INATION' NETWORKS:
Two Intel® 8226 Bidirectional Bus
Drivers permanently installed at Al and A2. A driver network must
be installed at A3 and a termination network must be installed at

A4.

DATA POLARITY: Negative-true. The polarity of Port C control outputs is dependent on the type of driver installed at A3.
JUMPER CONXECTIONS: 41-40 to enable output at 8226'5; connect 49-50
to enable interrupt request via 11'111'55/.

•

PORT 2 RESTRICTIONS: None; port 2 can be programmed for mode 0 or
mode 1, input or output (see Section 3.3.2.2).
PORT 3 RESTRICTIONS:
functions:

Port 3 bits perform the following dedicated

*Bits 0,
in mode
*Bit 3
*Bit ~,
*Bit 5

1 and 2 - dedicated to the control of port 2 if port 2 is
1 (see Tables 3-19 and 3-20).
INTR (interrupt request) output for port 1.
can be used for input if bit 3 of control word = 1
cannot be used if PC4 is used; can be used for output if
control word bit 3 = 0 (PC4 cannot be used then).
*Bit 6 - ACK! (acknowledge) input for port 1.
*Bit 7
OBF/ (output buffer full) output for port 1.

-

3-70

•
•
•

•

TABLE 3-15.

PORT 1, MODE 2 BIDIRECTIONAL CONFIGURATION

PORT 1 ADDRESS: E4,

•
•
•
•

CONTROL REGISTER ADDRESS: E7

DRIVER/TERMINATION NETWORKS: Two Intel®8226 Bidirectional Bus
Drivers permanently installed at Al and A2. A driver network must
be installed at A3 and a termination network must be installed at
A4 .
DATA POLARITY: Negative-true. The polarity of Port C control outputs is dependent on the type of driver installed at A3.
JUMPER CONNECTIONS: 41-43 to allow ACK/ input on PC6 to dynamically
change data direction at 8226's (input when ACK! = 1 and output when
ACK! = 0); connect 49-50 to enable interrupt request via INT55/.
PORT 2 RESTRICTIONS:

None .

PORT 3 RESTRICTIONS:
functions:

Port 3 bits perform the following dedicated

*Bits 0 and 1 - can be used for output if bit 3 of control word = 0
*Bit 2 - cannot be used if PeO and PCl are used; can be used for
input if control word bit 3 = 1 (PeO and PCl cannot be
used then).
*Bit 3 - INTR (interrupt request) output for port 1.
*Bit 4 - STEV (strobe input for port 1.
*Bit 5 - IBF (input buffer full) output for port 1.
*Bit 6 - ACK! (acknowledge) input for port 1.
*Bit 7 - OBF/ (output buffer full) output for port 1 .

3-71

3.3.2.2

PORT 2 (GROUP 2 PORT B)

Port 2 can be programmed for input or output in either mode 0 or mode 1.
If Port 1 is in mode 2, however, Port 2 must be programmed for mode O.

•

If

Port 2 is to be used for input, in either mode, terminator networks must be
installed in the sockets at A5 and A6.

If Port 2 is to be used for output,

in either mode, driver networks must be installed in the sockets at AS and

A6.

When Port 2 is programmed for mode 1, interrupts can be enabled by

connecting jumper pair 45-46.

The four potential configurations for Port 2

•

are summarized in the following tables;
TABLE 3-16.

PORT 2 OPERATING MODES

PORT 2 CONFIGURATIONS
TABLE
Direction

Mode
l.

2.
3.
4.

Mode
Mode
Mode
Mode

Input
Output (Latched)
Input (Strobed)
Output (La tched)

0
0

t
t

TABLE 3-17.

Table
Table
Table
Table

3-17
3-18
3-19
3-20

PORT 2, MODE 0 INPUT CONFIGURATION

PORT 2 ADDRESS: E5, CONTROL REGISTER ADDRESS: E7
CONTROL WORD FORMAT:

7

6

5

4

3

2

1 0

It Ix lxlxlx loltlxl
DRIVER/TERMINATION NETWORKS:
at A5 and A6.
DATA POLluUTY:

•

Termination networks must be installed

•

Positive-true.

JUMPER CONNECTION:
PORT 1 RESTRICTIONS:

None.

•

None (see Section 3.3.2.1).

PORT 3 RESTRICTIONS: None, port 3 can be programmed for mode 0,
input or output, unless port t is in mode 1 or mode 2 (see Section
3.3.2.3).

3-72

•

•

TABLE 3-18.

PORT 2, MODE 0 LATCHED OUTPUT CONFIGURATION
CONTROL REGISTER ADDRESS: E7

PORT 2 ADDRESS: E5,
CONTROL WORD FORMAT:

DRIVER/TERMINATION NETWORKS:
A5 and A6.
DATA POLARITY:
at A5 and A6.

Negative-true, assuming that inverting drivers are

JUMPER CONNECTIONS:

•

None.

PORT 1 RESTRICTIONS:

None (see Section 3.3.2.1).

PORT 3 RESTRICTIONS: None, port 3 can be programmed for mode 0 or
mode 1, 8-bit input or output, unless port 1 is in mode 1 or mode 2
(see Section 3.3.2.3).

TABLE 3-19.

•

Driver networks must be installed at

PORT 2, MODE 1 STROBED INPUT CONFIGURATION

PORT 2 ADDRESS: E5,
CONTROL WORD FORMAT:

CONTROL REGISTER ADDRESS: E7
7

6

11 I0

5

4

3

2

1

0

Ix Ixl x 11 III xl

DRIVER/TERMINATION ~~TWORKS: Termination networks must be installed
at A5 and A6. A driver network must be installed at A3 and a termination network must be installed at A4.

•

DATA POLARITY: Positive-true. The polarity of Port C control outputs is dependent on the type of driver installed at A3.
JUMPER CONNECTIONS:

45-46 to enable interrupt request via INT55/.

PORT 1 RESTRICTIONS:

None.

PORT 3 RESTRICTIONS:
functions:

Port 3 bits perform the following dedicated

*Bit 0 - INTR (interrupt request) output for port 2.
*Bit 1 - IBF (input buffer full) output for port 2.
*Bit 2 - STB/ (strobe) input for port 2.
*Bit 3 to Bit 7 - dedicated to control of port 1 if port 1 is in
mode 1 (see Tables 3-11 to 3-14).

•
3-73

TABLE 3-20.
PORT 2 ADDRESS:

E5,

PORT 2, MODE 1 LATCHED OUTPUT CONFIGURATION

•

CONTROL REGISTER ADDRESS: E7

DRIVER/TERMINATION NETWORKS: Driver networks must be installed
at A~; and A6. A driver network must be installed at A3 and a
termi.nation network must be installed at A4.
DATA POLARITY: Negative-true, assuming that inverting drivers are
at Mi and A6. The polarity of Port C control outputs is dependent
on the type of driver installed at A3.
JUMPER CONNECTIONS:

45-46 to enable interrupt request via INT55/

PORT 1 RESTRICTIONS:

None.

PORT 3 RESTRICTIONS:
functions:

Port 3 bits perform the following dedicated

*Bit o - INTR
*Bit: 1 - OBF/
*Bit 2 - ACK!
*Bit 3 - P3-7
mode

3.3.2.3

(interrupt request) output for port 2.
(output buffer full) output for port 2.
(acknowledge) input for port 2.
- dedicated to control of port 1 i f port 1 is in
1 (see Tables 3-11 to 3-14).

PORT 3 (GROUP 1 PORT C)

The use of Port 3 is dependent on the modes programmed for Ports 1 and
2 (refer to Tables 3-11 to 3-20).

While certain Port 3 bits are available

•
•
•

if Port 1 is in mode 1 or if Port 2 is in mode 0, the use of Port 3 as an
8-bit data path is restricted to those configurations that have both Port 1
and Port 2 programmed for mode O.

In this case, all eight bits of Port 3

can be programmed for mode 0 input (see Table 3-22) or output (see Table 3-23).
A 4-bit input/4-bit output configuration is never possible for group 1 Port 3.
Note:

If Ports 1 and 2 are not both in mode 0, then a driver network
must be installed in the sockets at A3 and a termination network
must be installed at A4, so that the Port 3 control lines can
function properly.

3-74

•

•

PORT 4 AND 5 (GROUP 2 PORTS A AND B)

3,3.2,4

Ports 4 and 5 can be programmed for input or output but only in mode O.
The two potential configurations for each port are summarized in the following tables:

TABLE 3-21.

PORT 4 AND 5 OPERATING MODES

CONFIGURATIONS
TABLE

•

1.

2.
l.

2.

Port
Port
Port
Port

Mode
Mode
Mode
Mode

4
4

5
5

TABLE 3-22.

•

PORT 3 ADDRESS: E6,

DRIVER/TER.:\lINATION
at A3 and A4.

•

DATA POLARITY:

DIRECTION

MODE

PORT

0
0
0
0

Table
Table
Table
Table

3-24
3-25
3-26
3-27

PORT 3, MODE 0, 8-BIT INPUT CONFIGURATION
CONTROL REGISTER ADDRESS: E7

Termination networks must be installed

~ETWORKS:

Positive-true.

JUMPER CO~~ECTIONS: 46-47 and 44-45 to disable port 2 interrupts
and enable P3-0; connect 48-49 and 50-51 to disable port 1 interrupts
and enable P3-3.
PORT 1 AND 2 RESTRICTIONS:

•

Input
Output (Latched)
Input
Output (Latched)

Both ports t and 2 must be in mode O.

3-75

TABLE 3-23.

PORT 3, MODE 0,8-BIT LATCHED OUTPUT CONFIGURATION

PORT 3 ADDRESS: E6,
CONTROL WORD FORMAT:

•

CONTROL REGISTER ADDRESS: E7
7

6

5

4

3

2

°

t

'tlOIOlxlololxlol
DRIVER/TERMINATION NEnVORKS:
at A3 and A4.

Driver networks must be installed

DATA POLARITY: Negative-true, assuming that inverting drivers are
installed at A3 and A4.
JUMPER CONNECTIONS: 46-47, and 44-45 to disable port 2 interrupts
and enable P3-0; connect 48-49 and 50-51 to disable port 1 interrupts
and ,enable P3-3.
PORT 1 AND 2 RESTRICTIONS:

TABLE 3-24.
PORT 4 ADDRESS:

E8,

CONTROL WORD FORMAT:

Both ports t and 2 must be in mode O.

PORT 4, MODE 0, INPUT CONFIGURATION

•

CONTROL REGISTER ADDRESS: EB
7

6

5

4

3

2

t

°

tlololtlxlolxlxl
DRIVER/TERMINATION NETWORKS:
at A7 and A8.
DATA POLARITY:

•

Termination networks must be installed

•

positive-true.

JUMPER CONNECTIONS:

None.

PORT 5 AND 6 RESTRICTIONS: None; ports 5 ~nd 6 can be programmed for
mode 0, input or output (also see Section 3.3.2.5).

3-76

•

•

TABLE 3-25.
PORT 4 ADDRESS:

PORT 4, MODE 0 LATCHED OUTPUT CONFIGURATION
E8, CONTROL REGISTER ADDRESS: EB

CONTROL WORD FORMAT:

7

6

5

4

3

2

t

0

Itlolololx(o(XIXI
DRIVER/TERMINATION NETWORKS:
A7 and A8.

Driver networks must be installed at

DATA POLARITY: Negative-true, assuming that inverting drivers are
installed at A7 and A8 .

•
•

JUMPER CONNECTIONS:

None.

PORT 5 AND 6 RESTRICTIONS: None; ports 5 and 6 can be programmed
for mode 0, input or output (also see Section 3.3.2.5).

TABLE 3-26.
PORT 5 ADDRESS: E9,
CONTROL WORD FORMAT:

PORT 5, MODE 0 INPUT CONFIGURATION
CONTROL REGISTER ADDRESS: EB
7

6

5

4

3

11 10 10 1 xlxl

•

DRIVER/TERMINATION NETWORKS:
at All and A21.
DATA POLARITY:

2

t

0

01 xl xl

Termination networks must be installed

Positive-true.

JUMPER CONNECTIONS:

None.

PORT 4 AND 6 RESTRICTIONS: None; ports 4 and 6 can be programmed
for mode 0, input or output (also see Section 3.3.2.5).

•

3-77

TABLE 3-27
PORT 5 ADDRESS:

PORT 5, MODE 0 LATCHED OUTPUT CONFIGURATION
E9, CONTROL REGISTER ADDRESS: EB

CONTROL WORD FORMAT:

7

6

11 10

5

4

3

2

1

0

0

0

x

x

I IXl I I I
0

DRIVER/TERlVIINATION NETWORKS:
at AU and A21 .

I

Driver networks must be installed

DATA POLARITY: Negative-true, assuming that inverting drivers are
installed at All and A21.
JUMPER CONNECTIONS:

None.

PORT 4 AND 6 RESTRICTIONS: None; ports 4 and 6 can be programmed
for mode 0, input or output (also Section 3.3.2.5).

3.3.2.5

•

PORT 6 (GROUP 2 PORT C)

All eight bits of Port 6 can be programmed for mode 0 input or output,
or four bits can be programmed for mode 0 input while the other four bits
are programmed for mode 0 output.

•
•

The four potential configurations for

Port 6 are summarized in the following tables:
TABLE 3-28.

PORT 6 OPERATING MODES

PORT 6 CONFIGURATIONS
1.

2.
3.
4.

MODE
MODE
MODE
MODE

0
0
0

0

8-BIT
8-BIT
UPPER
UPPER

INPUT
OUTPUT (LATCHED)
4-BIT INPUT/LOWER 4-BIT OUTPUT
4-BIT OUTPUT/LOWER 4-BIT INPUT

3-78

TABLE
Table
Table
Table
Table

•

3-29
3-30
3-31
3-32

•

•

TABLE 3-29.
PORT 6 ADDRESS: EA,
CONTROL WORD FORMAT:

PORT 6, MODE

8-BIT INPUT CONFIGURATION

~

CONTROL REGISTER ADDRESS:
7

6

5

4

3

2

1

EB

a

,110101 Xlll 01 Xlll
DRIVER/TERMINATION NETWORKS:
at A9 and AlD.
DATA POLARITY:

•
•

Positive-true.

JUMPER CONNECTIONS:

CONTROL WORD FORMAT:

CONTROL REGISTER ADDRE3S:
7

6

5

4

3

2

1

EB

a

1110(01 xl ololxlol
DRIVER/TERMINATION NETWORKS:
at A9 and AlD.

Driver networks must be installed

DATA POLARITY: Negative-true, assuming that inverting drivers
are installed at A9 and Ala.
JUMPER CONNECTIONS:

None.

PORT 4 AND 5 RESTRICTIONS:

•

None (see Section 3.3.2.4).

PORT 6, MODE 0,8-BIT LATCHED OUTPUT CONFIGURATION

PORT 6 ADDRESS: EA,

•

None.

PORT 4 AND 5 RESTRICTIONS:

TABLE 3-30.

Termination networks must be installed

None (see Section 3.3.2.4).

3-79

TABLE 3-31.
PORT 6 ADDRESS: EA,
CONTHOL WORD FORMAT:

PORT 6, MODE 0 UPPER 4-BIT INPUT/LOWER
4-BIT LATCHED OUTPUT CONFIGURATION
CONTROL REGISTER ADDRESS: EB
7

6

5

4

3

IlIOIOIX(

2

1

0

•
.

t{ofxlol

DRIVER/TERMINATION NETWORKS: A termination network must be installed
at A9 and a driver network must be installed at AlO.
DATA POLARITY: The upper 4-bits will be in positive-true form;
however, the lower four bits will be in negative-true form if an
inverting driver is installed at AlO.
JUMPER CONNECTIONS:

None.

PORT 4 AND 5 RESTRICTIONS:

TABLE 3-32.

PORT 6 ADDRESS:

None (see Section 3.3.2.4).

PORT 6, MODE 0 UPPER 4-BIT LATCHED OUTPUT/LOWER
4-BIT INPUT CONFIGURATION
EA,

CONTROL WORD FORMAT:

CONTROL REGISTER ADDRESS: EB
7

6

5

4

3

2

1

•
•

0

Illololxlolol xlll
DRIVER/TERMINATION NETWORKS: A driver network must be installed
at A9 and a termination network must be installed at AlO.
DATA POLARITY: The lower 4-bits will be in positive-true form;
however, the upper 4-bits will be in negative-true form if an inverting driver is installed at A9.
JUMPER CONNECTIONS:

•

None.

PORT 4 AND 5 RESTRICTIONS:

None (see Section 3.3.2.4).

3-80

•

•
•

•

TABLE 3-33.

PARALLEL I/O ADDRESS AND SOCKET ASSIGNMENTS

PORT

I/O ADDRESS

SOCKET NUMBERS

1

E4

BI-DIRECTIONAL DRIVER/
TERMINATOR AT AI, A2

2

ES

AS, A6

3

E6

A3, A4*

4

E8

A7, A8

S

E9

All, A21

6

EA

A9, AI0**

*Note requirements specified in Tables 3-11 through 3-23.
**Note requirements specified in Tables 3-24 through 3-32.

•
•
•

3-81

3.3 .. 3

GENERAL OPTlONS
There are several other options that may be useful. Details are pro-

•

vided in the following paragraphs,

•
3,3.3.1

SYSTEM RESET OUTPUT

The user can enable a SYSTEM RESET output from the SBC 80/10 by connecting jumper pair 54-55.
on the SBC 80/10 during

This allows the reset signal which is generated

power~up

sequences (see Section 3.2.1.5) to be

made available to other modules in the system via connector Pl-14.

Notice

on the schematic that a SYSTEM RESET input is accepted by the SBC 80/10
and Pl-14 and applied to the 8080 regardless of jumper connections.
3.3.3.2

•

DISABLE BUS CLOCK SIGNALS

The bus clock BCLK/ (connector pin Pl-13) or the constant clock CCLK/
(P-31) outputs can be disabled (if more drive, or a different frequency is
needed) by disconnecting jumper pair 61-63 or 62-64, respectively.

When

connected, both BCLK/ and CCLK/ provide a 9.216 MHz timing reference to
other modules.
3.3.3.3

•

ADVANCED ACKNOWLEDGE INPUT

Certain OEM mocules generate an advanced acknowledge, AACK/, in response to a memory read command, that allows the memory to complete the
access without requiring the CPU to wait.

When such modules are used with

the SBC 80/10, jumper pair 52-53 should be connected to allow AACK/ to be

•

accepted (at Pl-25) and gated to the RDYIN pin on the 8224 Clock generator.
3.3.4.

DEFAULT OPTIONS

Table 3-33 lists the default options jumpered on the SBC 80/10,

These

...

options permit the SBC 80/10 to communicate to a TTY; they also provide
power-up reset, bus clock, and the communication clock to the system bus,

3-82

•

•

TABLE 3-34.
DEFAULT
JUMPERS
1 - 2

.

REFERENCE
3.3.1.1

DESCRIPTION
Connect 8251 T D to 20 rnA Current Loop Driver
x

23 - 24

Connect 8251 DTR/ to TTY Reader Control Circuit

39 - 38

Connect 8251 R D to 20 rnA current Loop Receiver
x
Generates 6.98K Baud Rate Clock

4 - 8

3.3.1.2

Generates 6.98K Baud Rate Clock

57 - 56

•
•
•

DEFAULT OPTION ON THE SBC 80/10

34 - 33

Connect 8251 T

35 - 36

Connect 8251 R Clock to Baud Rate Clock
x
Connect 8251 RST/ to 8251 CTS/

x

27 - 29

Clock to Baud Rate Clock

19 - 20

3.2.5.4

Disable T RDY Interrupt from 8251

16 - 15

3.2.5.4

Disable R RDY Interrupt from 8251

26 - 25

3.3.1.2

Connect DTR/ Receiver to 8251 DSR/ Input

30 - 31

3.3.1.2

Connect Set Clear to Send Driver to +12V

40 - 41

3.3.2.1

54 - 55

3.3.3.1

Connect Power-Up Reset to System Bus

62 - 64

3.3.3.2

Connect 9.216 MHz Clock to Communication Clock Line

61 - 63

3.3.3.2

Connect 9.216 MHz Clock to Bus Clock Line

*65 - 66

3.3.5

*68 - 69

3.3.5

*73 - 74

3.3.5

*76 - 78

3.3.5

x
x

Enable Port 1 Bi-directional Drivers to Input

Configures SBC 80/10A for 4K ROM/PROM

*Used with SBC 80/10A only.

3.3.5

JUMPER CONFIGURATION FOR ROM/PROM INSTALLATION
The System 80/10 using SBC 80/10A has jumpers which allow installation

of up to 4K or up to 8K bytes of read only memory.

Up to 4K bytes can be

installed using Intel's 8708 Erasable and Electrically Reprogrammable ROMs
(EPROM), Intel's 8308 Metal Masked ROMs, or Intel's 2758 Erasable and electrically
Reprogrammable ROMs (EPROM).

Up to 8K bytes can be installed using Intel's

2716 Erasable and Electrically Reprogrammable ROMs (EPROM) or Intel's 2316E

•

Metal Masked ROMs.

Table 3-35 list the jumper configurations for 4K and 8K

3-83

bytes of read only memory.

Table 3-36 lists the addresses for each PROM

socket in 4K and 8K configurations.
TABLE 3-35.

•

PROM JUMPER CONFIGURATION

•
JUMPER
Ij.K

65-66

68-69

73-74

76-78

*1j.K

66-67

69-71

73-74

76-78

13K

66-67

69-70

74-75

77-78

*Using Intel's 2758 Erasable and Electrically Reprogrammable ROHs
(EPROM).
TABLE 3-36.

PROM ADDRESSES

•

CHIP ADDRESS
A23

A24

A25

A26

tlK

0-3FF

400-7FF

800-BFF

COO-FFF

*4K

0-3FF

400-7FF

800-BFF

COO-FFF

8K

0-7FF

1000-17FF

800-FFF

1800-1FFF

*Using Intel's 2758 Erasable and Electrically Reprogrammable ROM's
(EPROM)

•
•

3-84

•

•

CHAPTER 4
FRONT PANEL

•
The System 80/10 Front Panel allows the user to reset the entire
system and provides a visual indication of AC power on.
The System 80/10 Front Panel consists of two switches:
(1) AC Power switch

•

(2) System Reset switch

4.1

AC POWER SWITCH
The AC power switch is a double-pole-double-throw latching switch.

The switch is illuminated by a lamp.

The lamp is a midget flanged base

lamp, size T1 3/4, and operates at 28 volts.

•

It can be replaced by simply

pulling the plastic push button away from the switch housing.

Front panel

removable is not necessary.

4.2

SYSTEM RESET SWITCH
The System reset switch is a double-pole-double-throw momentary

switch.

•

One half of the DPDT switch is debounced by an RS flip-flop and

an inverter driver; the other half of the DPDT switch is not debounced.
The inverter driver is an open collector device (48 rnA sink current) and
it is connected directly to the System Bus (INIT/).

•
4-1

See Figure 4-1.

•
+5V

•
Ell-A

+-5V

c

+':;)v

R3

toE2

2.Zt:

0---<)

_!~"CI·
__ f. .
_rt=

EI

fJ_IO_"_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-

(INIT/,
PIN 14)

•

0 E.4

FIGURE 4-1.

SYSTEM RESET SWITCH

•
•

4-2

•

•

CHAPTER 5
CARDCAGE AND BACKPLANE ASSEMBLY
5.1

FUNCTIONAL ORGANIZATION OF THE CARDCAGE AND BACKPLANE ASSEMBLY
The System 80/10 modular card cage and backplane assembly consists of

two functional blocks:
(1) Structural foam card cage

•

(2) Termination backplane
Structural Foam Cardcage
The structural foam cardcage is an injection molded structure consisting of three separate pieces, the cardcage body and two card guides.
The two card guides are bonded to the cardcage body by an ultrasonic bonding process.

•

The cardcage assembly has a very high flexural, compressive

and tensile strength.

The resin used in the injection molded process

allows for very close tolerance control of all dimensions.
Termination Backplane
The termination backplane consists of a motherboard, four 43/86 pin
PCB connectors, termination resistors and two 7-pin power connectors.

•

of the bus signals on the backplane assembly are terminated.

Most

The backplane

accepts four SBC modules and each module has access to the bus.

The two

power connectors are used to supply power to the backplane.
5.2

CARD CAGE AND BACKPLANE ASSEMBLY UTILIZATION
The cardcage and backplane assembly houses the SBC 80/10 module and

three additional expansion boards if needed.

Paragraph 8.1.2 is a dis-

cussion of all signals on the backplane.
Four additional 30/60 pin auxiliary connectors can be added to the backplane assembly to form an auxiliary bus structure.

•

The auxiliary bus struc-

ture can be used to implement battery back-up or an inter-module bus.

5-1

•
•

•
•
•
•

•
•

CHAPTER 6
POWER SUPPLY
6.1

FUNCTIONAL ORGANIZATION OF THE POWER SUPPLY
The System 80/10 Power Supply provides regulated DC output power at

+12, +5, -5, and -12 volt levels.

The current capabilities of each of

these output levels have been chosen to provide power over the System 80/10
temperature range with the Single Board Computer fully loaded with I/O

•

line terminators and drivers, and four 8708 EPROMs plus residual capability
for most combinations of up to three SBC memory, I/O, or combination expansion boards within the System 80/10.
Current limiting and over-voltage protection is provided on all outputs.
Access for AC input is provided via a standard 4-pin keyed connector.

DC

output power levels are provided on cables with keyed connectors which are

•

directly compatible with the Modular Backplane/Cardcage assembly.

Supply includes logic which senses a system AC power failure and generates
a TTL signal for clean system power-down control.
6.2

THEORY OF OPERATION

6.2.1

•

The Power

5V, 14 A OUTPUT
Operation is as follows:
(Ref. Schematic 2000952, Appendix B.)

6.2.1.1

VOLTAGE REGULATION

If we start at the moment of AC on, C1, 17 and 8 will begin charging
up from the current through CR1, 6 and 7.
is present at pins 11 and 12.
will be present at pin 6.

U1 will be "off" until :;;;.8 volts

At that point, the reference voltage of 7.15V

This reference voltage is divided down to 5V at

pin 5, which is the non-inverting input of the internal differential amp-

•

lifier.

Pin 4 is the inverting input; since no output is present the dif-

ferential amplifier is unbalanced and U1 will drive current out pin 10.

6-1

When pin 10 goes positive, Q1 turns on and drives the bases of Q2 and 3 on.
Collector current through Q2 and 3 will charge the output cap C3 and 17 and
deliver power to the load.

•

When the voltage at C3 is 5.0 VDC, the differ-

ential amplifier will be balanced; pin 10 will reduce its output, and voltage
regulation will occur.

The output voltage may be adjusted by varying the

resistance of R8.
6 . 2 • 1. 2

CURRENT LIMI TI FOLD BACK

U1 has an internal current limit transistor that, when turned on, will
reduce the output of pin 10.
The base-emitter of this transistor is brought out to pins 2 and 3.
respectively.

Pin 3 is connected to the output, pin 2 is connected to a

•

current-sensitive point (in this case, the base of pass element Q2,3).
In normal, full load operation, R2 and 4 will drop :::'.5V because of the
base current at Q2,3.

R3 and 5 are shut-off resistors for the pass elements.

(R7 is used to bias the current limit transistor off during normal conditions.)
Under full load operating conditions, the voltage at Q1-E will be
approximately 6.5 VDC.

•

R6 is set to bring pin 2 to a threshold condition (:::.5.5 VDC) when 120%
to 150% of rated current is being delivered.
If additional current is draWI1, the current limit transistor in U1 will
reduce the output of pin 10.

This causes a reduction in output voltage

which reduces the bias current in R7 and increases the current to the current
limit transistor.

At the maximum load (shorted output), very little current

•

flows through R7, which means that it takes only a slight voltage at Q1-E
to activate the current limit transistor.

The current limit/foldback cir-

cuit described above has a fairly low gain, and it is reasonably normal to
deliver 20-50% of rated current into a short.

This is desirable because

most logic circuits have start-up conditions requiring greater current than
linear ViI curves would indicate.

6·-2

•

•

6.2.1.3

OVP OPERATION

Zener CR2 senses the output voltage.

When this voltage is sufficient

to cause CR7 to zener and charge C18, SCR1 will fire which reduces the out-

•

put to

~1

6.2.2

+12V OPERATION (Ref. Schematic 2000952, Appendix B.)

6.2.2.1

OVP can be reset by cycling the AC input.

REGULATION

When the secondary of T1 charges C8 through CR6 and 7, U3 will drive
current out of pin 10 until the differential amplifier is balanced (see
Section 6.2.1.1).
6.2.2.2

•

VDC.

CURRENT LIMIT/FOLDBACK

U3 has an internal current limit transistor that, when turned on, will
reduce the output of pin 10.
The base-emitter of this transistor is brought out to pins 2 and 3,
respectively.

Pin 3 is connected to the output, and pin 2 is connected

to a current-sensitive point (in this case, the base of Q6).
In normal operation, at full load, R27 will have

•

across it.

~.44

volts dropped

R25 and R26 are calculated (and tested) to bias pin 2-3 at

::: + .4V at full load.

When excess current (:::120% of rated) is drawn, the

increased drop across R3 will force the current limit transistor into conduction.

When the load is further increased the current limit transistor

takes more and more of the drive from U3-pin 10, and the output voltage will
decrease.

When the output voltage is decreased, the offset bias through R27

is less and further reduces the available current from D3-pin 10.
circuit, the current

throu~h

R27 is minimal and output current will be

20-30% of rated.
6.2.2.3

•

6.2.3

At a short

OVP OPERATION (See section 6.2.1.2.)
-12V OPERATION
6-3

6.2.3.1

REGULATION

Regulation is accomplished in a similar manner to the +12V regulator
(see Section 6.2.2.1).

Q7 is used to maintain U4 at an operational bias

level.
6.2.3.2

•
•

CURRENT LIMIT

The current limit circuit operates in an identical manner to the circuit of Section 6.2.2.2, except that the circuit does not have foldback
characteristics.

Current can be drawn until there is

~.SS

volts across R36.

Since Pins 2 and 3 are across R36, this maximum current is also the short
circuit current.
6.2.3.3
6.2.4

•

OVP (See Section 6.2.1.2)
-SV OPERATION

6.2.4.1

REGULATION

Regulation is accomplished in a similar manner to the +12V regulator
(see Section 6.2.2.1).

•

Q4 is used to maintain U2 at an operational bias

level.
6.2.4.2

CURRENT LIMIT

The current limit circuit operates in an identical manner to the circuit of Section 6.2.2.2, except that the circuit does not have foldback
characteristics.
and RSS.

Current can be drawn until there is

~.SS

•

volts across R16

Since pins 2 and 3 are across R16 and RSS, this maximum current

is also the short circuit current.
6.2.4.3
6.2.S

OVP (See Section 6.2.1.2.)
POWER FAIL OPERATION

At turn-on CIS charges through CRI3, 14.
parator.

Pin 6 is the reference voltage.
6-4

US is a 723 set up as a com-

R44 adjusts the reference voltage

•

•

on pin 4 (the inverting input).

When the voltage on pin 5 is higher than

on pin 4 the output goes high and Q9 saturates.

R48, 46, 51 determines the

hysteresis and compensates for the ripple on ClS.

R49 limits the drive to

Q9.

Operational power is obtained from C8 (raw 12V).

6.3

DC POWER OUTPUTS
Power supply provides ±5V and _±12V through power supply connectors

P6 and P8.

•

The P8 harness is 16 inches in length and P6 harness is 24

inches in length from mid-point of surface A (see outline drawings in
Appendix C).

See the diagram below for pin out and voltage assignments.

pa

P6

•
•

1

0

GND

1

2

D

+SV

2

3

D

+SV

4

D

5

•

KEY

0

GND

3

0

-SV

-12V

4

0

+12V

0

NOT USED

5

0

+SV

6

0

GND

6

0

+SV

7

•

KEY

7

0

GND

FIGURE 6-1
OUTPUT POWER CONNECTIONS

6.3.1

DC OUTPUT VOLTAGE ADJUSTMENT
Adjustment range for all voltages is ±5% of nominal voltage.

To ad-

just output voltage, locate appropriate voltage adjustment trimmer (see

•

outline drawings in Appendix C), then turn trimmer, with non-metallic
screwdriver, clockwise to increase output voltage or counterclockwise to
decrease output voltage.

If

over-voltage~protection

circuit is tripped

during voltage adjustment see OVP reset procedure below.

6.3.2

OVER-VOLTAGE-PROTECTION CIRCUIT RESET PROCEDURE
After OVP is tripped, input power must be turned off for at least

3 seconds.

•

Reduce output voltage of the tripped OVP by rotating the

voltage adjustment trimmer about a half turn counterclockwise.

Turn

power on, normal operation should be restored, if not, repeat OVP reset
procedure.

Re-adjust output voltage according to DC Output Voltage

Adjustment above.
6.4

AC LOW DETECTION CIRCUIT CONNECTIONS*
An Blctive high TTL level signal indicating AC power failure is pro-

vided to the user through connector J3 pin 5 (CAUTION:
are present in connector J3, see pin out diagram below.)

Other voltages
Use Molex con-

•

nector (PiN 09-50-7071), pin (PiN 08-50-0106) and polarizing key

(PiN 15-04-0219) for mating parts to J3 connector.

Unregulated
Voltages

D
4

5

GND

•

"AC Low"

6
:J

7

KEY
FIGURE 6-2

AC LOW DETECTION CIRCUIT CONNECTIONS

•

*For 1l5V/230V operation only.
(NOTE:

The location of the AC low detection connector can vary within
the indicated volume shown on the outline drawings. (See Appendix C.)

~~ion

of AC Power Failure Detection Circuit

The "AC Low" output from the J3 connector is an active high TTL
compatible signal which indicates that the AC input line voltage is below

6--6

•

•

103/206 VAC

(~S).

backup logic ,

HAC Low ll output should be pulled up by the battery

Ln case of a power

fa.ilure~

a.ll DC voltage is guaranteed

to stay within regulation for a minimum of 7.5 msec at any frequency

•

within the operating frequency range (47-63 hz) after the HAC Low" line
goes high.
In a battery backup system, the "AC Low" signal is used to generate
a "Power Fail Interrupt/" to the CPU and enable ''Memory Protect" logic to
disable any further Read/Write operations to the memory,

•

A "Power Failure

Detect/" signal may also be generated by the system to indicate that a
power failure has occurred.

Typical system timing during a power down and

recovery is described in Figure 6-3.
When AC power recovers, the "AC Low" signal will return to the low
state, the memory protect logic is then disarmed and a system "RESET" must
be generated.

Once reset, the system executes a start up routine which will

sample the "Power Failure Detect/" line.

•

the CPU to its original line.

If it is active, it will restore

If it is active" it will restore the CPU to

its original state before power failed, and continue operation.

inactive, a "Cold Start" initialization routine will be performed.
6.5

MODIFICATION PROCEDURE FOR 230V OPERATION
The System 80/10 is wired for 11sv/230v operation.

•

If it is

to operate at 115v as shipped.

The System is set

For 230v operation follow the procedure

as listed below:
(1) Turn off System and disconnect power cord from unit.

-- CAUTION -Be sure power to System is OFF and power cord is removed from
unit and power outlet.

Damage to the System and personnel

might result if power is NOT TURNED OFF!
(2) Remove 3 Amp fuse from fuse holder.
that is shipped with the System.

•
6-7

Replace with

1~

Amp fuse

•

Input AC Power
Below 103/206
VAC (RMS)

AC LOW
(From SBC 635)
Power Failure
Detect/

r-----

Failure
Clear/

..

•

Power Fail
Interrupt/

Memory Protect/

I

I
i

I

RESET/

I
I

I

i
Systems· Subroutines

I

I

: .

POWER F4ILURE SUBROUTINE

POWER UP SUBROUTINE

i+ 7.5 ms ....1
(MIN.). I

I

+V
(+5,+12)

DC OUTPUTS
(From
SBC
635)

•

t

GND (OV)

GND_~OVJ

~J
~~~
I

____________

•
•

_______________

1(-5,-12)

DC POWER
FROM
SBC 635 SUPPLY

POWER
FROM
BATTERY BACK-UP
TO RAM

FIGURE 6-3
TYPICAL POWER FAIL SEQUENCE

6-8

DC POWER
FROM
SBC 635 SUPPLY

•

•
'

..

(3) Remove top cover of System 80(10 and locate 115v/230v switch

mounting bracket.

Remove SBC 80/10 module,

(4) Loosen top two screws and remove switch locking plate from
mounting bracket.

Reverse orientation of locking plate by

flipping locking plate over sideways.

Locking plate is stamped

with "230".
(5) Slide voltage selection switch to the left, the side marked

•

with "230" on it, and re-install switch locking plate.

Tighten

top two screws,
(6) Re-connect power cord to unit.

voltages on backplane assembly.
SBC 80/10 module.

Turn unit on and verify all
Turn off power and re-install

Unit is now ready for 230v operation.

Modifications must be made to the transformer for other AC input

•

voltages.

See Table 6-1 and Figures 6-4 and 6--5.

TABLE 6-1

OPTIONAL TRANSFORMER CONNECTIONS

•

INPUT
RANGE

NOMINAL
INPUT

INPUT
SOURCE
(PIN)

INPUT
RETURN
(PIN)

103.5-126.5

115

1

2

1-3, 2-4

207-253

230

1

4

2-3

192.5-236.5

215

5

4

2-3

100

5

2

1-3, 2-4

90-110

•

6--9

I

TRANSFORMER
JUMPERS REQUIRED
(PIN)

SYSTEM 80/10
POWER SUPPLY
INPUT
CONNECTOR
INPUT
SOURCE
21Sv

(NOMINAL)
\ INPUT

P2*
1

________---,) >GRY

r-.-----

58
I~

c==t

•
•

I~

>RED
2!-,
ORN
3 1 •
)-"'='----="----+-~
I

I

I

I
INPUT

I

)

RETURN

L _____ _

'lIrWire from transformer TI, Pin 1 is moved to TI, Pin 5.

•

FIGURE 6-4
21SvCONNECTION
SYSTEM 80/10
POWER SUPPLY

* INPUT
CONNECTOR

P2*
GRY

"
/

100v
(NOMINAL)
INPUT

INPUT
SOURCE
INPUT
RETURN

r------1t

•

GRY

)

I
I

------~--~~--__4~
RED
L--_+-_ _~) ) ORN

21
31

•

13
.L_____ _
I

t - - -_ _~)

•

)

WHT

I

1-<,
41 ~
)

•

'lI~S

pin connectors must be used. Use Molex P/N 03-09-2052
for P2 transformer connector and use Molex P/N 03-09-1052
as mating connector.

FIGURE 6-5
100v CONNECTION

6-10

•

•

CHAPTER 7
SYSTEM MONITOR
7,1

MONITOR FUNCTIONAL SPECIFICATION

7.1.1

GENERAL CHARACTERISTICS AND SCOPE
The monitor is a program written in Intel~8080 macro assembly

language.

•

the memory address space of the System 80/10 microcomputer between 0 and
0560H (H=hexadecimal),

The non-volatile nature of the program's storage

media means that the monitor is available for use immediately after power-on
or reset.
7.1.2

•

The monitor resides in two programmed ROMs and is located in

DESCRIPTION OF ALL MAJOR FUNCTIONS PERFORMED

7.1.2.1

CONSOLE COMMANDS

The monitor communicates with the operator via an interactive console,
normally a teletypewriter.

The dialogue between the operator and the mon-

itor consists of commands in the monitor's command language and the monitor's
responses.

•

After the cold start procedure, the monitor begins the dialogue

by typing a sign-on message on the console and then requests a command by
presenting a prompt character,

" ."

.

Commands are in the form of a single

alphabetic character specifying the cOlnmand, followed by a list of numeric
or alphabetic parameters.
numbers.

Numeric parameters are entered as hexadecimal

The monitor recognizes the characters 0 through 9 and A through

F as legal hexadecimal digits.

The valid range of numbers is from 1 to 4

hex digits.

Longer numbers may be entered, but such numbers will be eval16
uated modulo 2
so that they will fall into the range specified above.
The only command requiring an alphabetic parameter is the

"X" command.

The nature of such parameters will be discussed in the section explaining
the command.

•

7-1

7.1,2,2

USE OF THE MONITOR FOR PROGRAMMING AND CHECKOUT

The lnonitor allows the user to enter, check out, and execute programs,
The monitor contains facilities for memory modification, 8080 CPU register

•
.

display and modification, program input and output from the console device,
program initiation, and the recognition of an "RST 7" instruction as an
unconditional branch to RAM address 3C3DH.

By inserting RST 7 instructions
instruc~

in a program under test, or by using the hardware generated RST 7

tion (if available), the user can cause execution of a program to transfer
to a dedicated location (3C3DH), for whatever purposes he desires.
When the user wishes to re-enter the monitor (also see Appendix E), he
should use an RST 1 instruction coded into his program.

When entered in

this manner, the monitor will print an tlfI" followed by the contents of the
user program counter (byte address of RST 1 instruction plus one).
monitor will also automatically save the state of the 8080:

The

specifically,

it will save all registers (A, B, C, D, E, H, L), the CPU flags (F), the
user's Program Counter (PC), and the user's Stack Pointer (SP).
be examined with the X command.

These may

When the operator enters a G command, these

values will be restored.
7.1.2.3

•

I/O SYSTEM

The I/O system provides four routines.

Console character in and con-

sole character out, which the user may call upon to read and write, respectively, characters from and to the console device.

The other two routines

allow the user to read and punch paper tapes from the teletype.
7.1.3

•
•

APPLICABLE STANDARDS
Throughout this specification, the numbering convention for bits in a

word is that bit 0 is the least significant, or rightmost bit.
The internal code set used by the monitor is 7 bit (no parity) ASCII,

7-2

•

•

7.2

MONITOR INTERFACE SPECIFICATIONS

7.2.1

COMMAND STRUCTURE
In the following paragraphs the monitor command language is discussed,

Each command is described, and examples of its use are included for clarity.
Error conditions that may be encountered while operating the monitor are
described in Section 7.3.2.
The monitor requires each command to be terminated by a carriage

•

re~

With the exception of the "S'" and "X" commands, the command is not

turn.

acted upon until the carriage return is sensed.

Therefore, the user can

abort any command, before he enters the carriage return by typing any
illegal character (such as RUBOUT or any alphabetic character with the
exception of A through F).
Except where indicated otherwise, a single space is synonymous with

•

the comma for use as a delimiter.

Consecutive spaces or commas, or a space

or comma immediately following the command letter, will be interpreted as
null parameters.

Null parameters are illegal in all commands except the

"X" command (see below).
Items enclosed in square brackets "[II and "],, are optional.

The con-

sequences of including or omitting them are discussed in the text.

•

7.2.1.1

DISPLAY MEMORY COMMAND, D

D,
Selected areas of addressable memory may be accessed and displayed by
the D command.

The D command produces a formatted listing of the memory

area between  and , inclusive, on the console
device,

Each line of the listing begins with the address of the first

memory location displayed on that line, represented as 4 hexadecimal digits,
followed by up to 16 memory locations, each one represented by 2 hexadecimal
digits.
The D command may be aborted during execution by typing an Escape (ESC)

•

on the console.

The command will be terminated immediately, and a new

prompt issued.

7-3

•

Example
D9,2A
0009 00 11 22 33 44 55 66

.

0010 77 88 99 AA BB CC DD EE FF 10 20 30 40 50 60 70
0020 80 90 AO BO CO DO EO FO 01 02 03
Note:

If the  parameter is greater than the 
parameter, only the first location defined by  is
printed.

7.2.1.2

•

PROGRAM EXECUTE COMMAND, G

G[]
Control of the CPU is transferred from the monitor to the user program
by means of the program execute command, G.

The  should be an

address which contains an instruction in the user's program.

If no entry

point is specified, the monitor uses, as an address, the value of the P
register saved during a previous "G" command or saved as a result of a RST 1
instruction coded into the user's program.
Example

•

G1400
Control is passed to location 1400H.
Note:

When entering a user program for the first time, the user should
initialize the Stack Pointer to his stack area.

Also, after a

reset to the SBC 80/10 the user Stack Pointer must be reinitialized
by the user during subsequent entry into the user's program or by
the
7.2.1.3

'xs'

•

command.

INSERT INSTRUCTIONS INTO MEMORY, I

I

Si.ngle or multiple instructions are entered into memory with the I
command.

After sensing the carriage return terminating the command line,

the monitor waits for the user to enter a string of hexadecimal digits
(0-9,A-F).

Each digit in the string is converted into its binary value,

•

•

and then loaded into memory, beginning at the starting address specified
and continuing into sequential locations,

Two hexadecimal digits are

loaded into each byte of memory,

.

Separators between digits (spaces, commas, carriage returns) are
ignored; illegal characters will terminate the command.
acters will terminate the command,
"$") terminates the digit string,
entered, a

•

0

The escape char-

The escape character, ESC (echoed as
If an odd number of hex digits have been

will be appended to the string.

Example
I3E10
112233445566778899$
This command puts the following pattern into RAM:
3EI0 11 22 33 44 55 66 77 88 99
I3E40
123456789$

•

This command puts the following pattern into RAM;
3E40 12 34 56 78 90
Note that, since an odd number of hexadecimal digits were entered initially,
a 0 was appended to the digit string.
7.2.1.4

•

MOVE MEMORY COMMAND, M

M,,
The M command moves the contents of memory  through , inclusive, to the area of RAM beginning at .

The

contents of the source field remain undisturbed, unless the receiving field
overlaps the source field.
The move operation is performed on a byte-by-byte basis, beginning at
.

Care should be taken if  is between  and .

For example, i f location 3ElO contains lAB,

the command

•

M3EI0,3ElF,3Ell
will result in locations 3ElO to 3E20 containing
"lA1A1A •• ,".
7-5

The monitor will continue to move data until the source field is
exhausted, or until it reaches address OFFFFH ,

If the monitor reaches

address OFFFFH without exhausting the source field, i t will move data
into this location, then stop.

•
.

Example
M3EOO,3EOF,3FOO
16 bytes of memory are moved from 3EOO-3EOF to 3FOO-3FOF by this command,
Note:

If the  parameter is greater than the 
parameter, only the first destination address is altered.

7.2.1.5

READ HEXADECIMAL FILE, R

•

R

The R command reads a hexadecimal tape from the teletypewriter and
loads the data into the locations specified by the address fields in the
hexadecimal records.

(See Section 7.3.3 for hexadecimal tape format

definition. )
A typical R command will appear as follows:
.R (User should turn on the tape reader before executing this command.)
7.2. 1.6

•

SUBSTITUTE MEMORY COMMAND!. S

S

The S command allows the user to examine and optionally modify memory
locations individually.

The command functions as follows:

•

(1) Type an S, followed by the hexadecimal address of the first memory
location you wish to examine, followed by a space or comma.
(2) The contents of the location is displayed, followed by a dash (-),

(3) To modify the contents of the location displayed, type in the new
data, followed by a space, comma, or carriage return.

If you do

not wish to modify the location, type only the space, comma, or
carriage return.
(4) If a space or comma was typed in Step (3), the next memory location

7·-6

•

•

will be displayed as in Step l2)

I

If a carriage return as typed ~

the S conunand will be term;tnated,
Example

..

S3DSO M- BB-CC 01-13 23-24
Location 3D50, which contains AA is unehanged l but location 3D51
(which used to contain BB) now contains CC, 3D52 (which used to
contain 01) now contains 13, and 3DS3 (which used to contain 23)
now contains 24 •

•

7.2.1.7

WRITE HEXADECIMAL FILE, W

W,
The W command outputs portions of memory to punched paper tape on the
teletypewriter.

Data is in hexadecimal format.

A leader tape consisting

of 60 null characters is punched followed by the memory data specified by

•

the low/high address parameters.
cally to terminate the tape.

An end of file record is punched automati-

Following the end of file record, a trailer

tape is punched consisting of 60 null characters.
An example of the Write Hexadecimal file operation is as follows:
W3DOO,3DAF

(User should turn on tape punch before executing this command.)

This command punches out the contents of memory locations 3DOOH through
3DAFH.

•

7.2.1.8

EXAMINE AND MODIFY CPU REGISTERS COMMAND, X

X
Display and modification of the CPU registers is accomplished via the
X command.

The X command uses  to select the particular

register to be displayed.

A register identifier is a single alphabetic

character denoting a register, defined as follows:

•

•

A - 8080 CPU registeJ: A

B - 8080 CPU register B
C - 8080 CPU register C

...

D - 8080 CPU register D
E - 8080 CPU register E
F

8080 CPU flags byte, displayed in the form as it is stored by the

•

"PUSH PSW" (hex code FS) instruction
H - 8080 CPU register H

L - 8080 CPU register L

•

M- 8080 CPU register H and L combined
P - 8080 Program Counter
S - 8080 Stack Pointer
The

cO~lnd

operates as follows:

(1) Type an X followed by a register identifier or a carriage return.

(2) The contents of the register are displayed (two hexadecimal digits
for A, B, C, D, E, F, H, and L, four hexadecimal digits for M, P,
and S), followed by a dash (-).

•

(3) The register may be modified at this time by typing the new value
followed by a space, comma, or carriage return.

If no modification

is desired, type only the space, comma, or carriage return.
(4) If a space or comma was typed in Step (3), the next register in
sequence (alphabetical order) will be displayed as in Step (2)
(unless S was just displayed in which case the command is terminated).

•

If a carriage return was entered in Step (3), the X command is
terminated.
(5) If a carriage return was typed in Step (1) above, an annotated list
of all registers and their contents are displayed,
7.2.2

DEVICE DRIVERS
The monitor has device drivers for the console device including the tape

reader and punch (if console device is a teletypewriter).

The drivers inter-

face through synchronous/asynchronous receiver/transmitter (USART) which is
7-8

•

•

described in Section 4 of this Hardware Reference Manual.

The monitor

configures the USART during a power on or reset condition to the following
state:

.

Mode:
2 stop bits
Parity disabled
8 bit character length
Baud rate factor of 64X

•

Command:
No hunt mode
Request to send high
Receiver enabled
Data terminal ready low
Transmitter enabled

•

Care should be exercised by the user in modifying the USART mode and command
since the monitor depends on the configuration defined above for device
driver operation.
7.2.3

USING THE I/O SYSTEM
The user may access the four monitor I/O system routines from his

•

program by calling the routine desired.

The following paragraphs describe

the routines available and their respective functions.
CI - Console Input
This routine returns an 8 bit character received from the console
device to the caller in the A,,",register.

The A'-register and the CPU condi-

tion codes are affected by this operation.
is 3FDH.
Example
CI

•

EQU

3FDH

CALL CI
STA DATA

7-9

The entry point of this routine

co -

•

Console Output

This routine transmits an 8 bit character, passed from the caller in
the C-register, to the console device,

The A and C registers. and the CPU

condition codes, are affected by this operation,

•

The entry point of this

routine is 3FAH.
Example
CO

EQU

...

~I
C~L

3FAH

•

.

C, " "
CO

RI - Reader Input
RI returns an 8 bit character read from the teletype reader in the
A-register.

If no character was read from the device (i,e., end of file),

the CARRY condition code is set equal to 1, and the A-register is zeroed.
If data is ready, the CARRY bit is zeroed.

The reader driver contains a

timer so that if no character is received from the teletype reader within
a pre-established time (250 milliseconds), an end of file may be simulated
and control returned to the calling program.

The entry point of this

•

routine is 400H.
Example
, RI
EQU
C~L

JC
STA

...

PO

400H
RI
EOF
DATA

END OF FILE SENSED

•

Punch Output

PO transmits an 8 bit character from the calling program to the teletypewriter.

PO is identical in format to CO, the only difference being

the entry point address, '403H'.

•
7-10

•

7.3

MONITOR OPERATING SPECIFICATIONS

7.3.1

PRODUCT ACTIVATION INSTRUCTIONS

•
7.3.1.1

COLD START PROCEDURE

After power-on or reset, the monitor will begin execution at location 0
in ROM.

The monitor will perform an initialization sequence, and then dis-

playa sign-on message "SBC BOP Monitor'" on the console,

•

is ready for a command, it will prompt with a period,

.

When the monitor

" ".

USE OF RAM STORAGE IN THE MONITOR

7.3.1.2

The monitor dynamically assigns its RAM stack in the first 64 bytes of

RAM.

The top 3 bytes in this block of RAM are reserved for a jump instruc-

tion, supplied by the user, which is used as a destination pointer for RST 7

•

instructions (or the optional hardwired instruction).
bytes are used, below the stack, for temporary storage.

Except for RAM

addresses 3COOH to 3C3FH, all other RAM is available for the user.
7.3.2

ERROR CONDITIONS

7.3.2.1

•

Several additional

INVALID CHARACTERS

The monitor checks the validity of each character as it is entered
from the console.

As soon as the monitor deternlines that the last character

entered is illegal in its context, the monitor aborts the command and issues
an "if" to indicate the error,
Example
D1400, 145Gif
The character G was encountered in a parameter list where only
decimal digits and delimiters are valid.
yif

•

Y is not a valid command,

hexa~

7.3.2.2

ADDRESS VALUE ERRORS

Some commands require an address pair of the form
.

~low address>~

If, on these commands, the value of  is

greater than or equal to the value of , the action indicated

•
.

by the command will be performed on the data at  only,
Addresses are evaluated modulo 216 , Thus, if a hexadecimal address
greater than FFFF is entered, only the last 4 hex digits will be used.
Another type of address error may occur when the operator specifies
a part of memory in a command which does not exist in his particular configuration.

In general, if a nonexistent portion of memory is specified

as the source field for an instruction, the data fetched will be unpredictable.

If a nonexistent portion of memory is given as the destination

•

field in a command, the command has no effect.
7.3.2.3

PERIPHERAL DEVICE ERRORS

Peripheral devices selected by the operator which are not ready or are
nonexistent will cause undefined execution of the monitor (usually an indefinite wait for ready status in an I/O loop).

This situation may be rec-

•

tified by readying the device and by executing the Cold Start sequence
(Section 7.3.1.1) to reinitialize the system.
7.3.3

HEXADECIMAL OBJECT FILE FORMAT FOR PAPER TAPE
Hexadecimal object file format is a way of representing a binary

object file in ASCII.

The ASCII character set is defined by the "American

National Standard Institute, Code.i.E.!. Information

Interchan~e,

X3,4-1968 11 ,

The hexadecimal representation. of binary is coded in ASCII,
example, the 8-bit binary value 0011 1111 is 3F in hexadecimal.

•

For
To code

this in ASCII one 8-bit byte containing the ASCII code for 3 and one 8-bit
byte containing the ASCII code for F are required.

This representation

(ASCII hexadecimal) requires twice as many bytes as the binary.
A hexadecimal object file can contain either 8-bit or 4-bit data but
not both.

Two ASCII hexadecimal digits are used to represent both 8-bit

and 4-bit data.

In the case of 4-bit data, only one of the digits is
7-12

•

•

meaningful.

Whether it is the high..-order or the low.,-order digit must be

known by the program reading the file and must 1be consistent throughout
the file.
Since ASCII characters need only

7~·bits

for their representation, the

highest-order bit of each 8-bit byte can be used as a parity bit by a program
that generates the hexadecimal format object file.

However, when such a

file is loaded by an Intel product, the highest order bit is masked as the
ASCII is converted to binary.

•

Also t Intel soft'ware does not generate parity

bits when creating object files.
The format described below is for paper tape and does not define the
format for other media, which may use record separators such as the ASCII
code for carriage return.
frame.

On paper tape, one ASCII character requires one

The record format is described here according to the fields in the

record.

•

Record Mark Field:

Frame 0

The ASCII code for a colon C:) is used to signal the start of a record.
Record Length Field:

Frames 1 and 2

The number of data bytes in
hexadecimal digits in this field.

•

thE~

record is represented by two ASCII

The high-order digit is in frame 1.

maximum number of data bytes in a record is 255 (FF in hexadecimal).

The
An

end-of-file record contains two ASCII zeros in this field.
Load Address Field:

Frames 3 - 6

The four ASCII hexadecimal digits in frames 3-6 give the address at
which the data is loaded.
digit in frame 6.

The high-order digit is in frame 3, the low-order

The first data byte is

stor€~d

in the location indicated

by the load address; successive bytes are stored in successive memory locations.

This field in an end-of-file record can contain the starting ad-

dress of the program.

•

Record Type Field;

Frames 7 and 8

The two ASCII hexadecimal digits in this field specify the record type.
The high-order digit is in frame 7.
records are type 1.

All data records are type 0;

•

end-of~file

Other possible values for this field are reserved for

•

future expansion,
Data Field:

Frames 9 to 9+2*(record length)-1

A data byte is represented by two frames containing the ASCII characters
0-9 or A-F', which represent a hexadecimal value between 0 and FF (0 and 255
decimal).

The high-order digit is in the first frame of each pair.

If the

data is 4-bit, then either the high or low-order digit represents the data
and the other digit of the pair may be any ASCII hexadecimal digit.

There

•

are no data bytes in an end-of-file record.
Checksum Field:

Frames 9+2*(record length) to 9+2*(record length)+1

The checksum field contains the ASCII hexadecimal representation of the
twos complement of the 8-bit sum of the 8-bit bytes that result from converting
each pair of ASCII hexadecimal digits to one byte of binary, from the record
length field to and including the last byte of the data field.

•

Therefore, the

sum of all the ASCII pairs in a record after converting to binary, from the
record length field to and including the checksum field, is zero.

•

Sample Hexadecimal Tape Format:

:Record Mar k
----Record Length
Load Address
Record Type
Data (16 Bytes)

~---Starting

rhecksum

'

: fihlJ 0 0 0 0i --A-2-F-S-7-7-S-2-F-SF-1-3-2-1.....0-0-0-0-3-E-l-lE-S-1-9-D-2-1-S-2
:1000100000E3EIFS79174F7S17477D176F7C17677S
:0D002000F13DC20C00S77CIFS77DIFSFC96A
: 010000001
'---r------'

I

:Because Record Length = 0 and Record Type
this record specifi~s End-of-File.
7-1Lf

=

01,

•

•

7.4

HARDWARE GENERATED BREAKPOINTS
This section is meant to describe a method whereby the user may interrupt

the operation of his program, return control to the monitor program which will
save the state of the 8080 registers and finally, allow the user to restart
his program from the point of interruption.
The first requirement in order to produce an interrupt, would be to attach a switch to ground or a low logic level signal from a user circuit to

•
•

Pl-42 or 11-49 (EXTernal INTerrupt Request 1, EXTernal INTerrupt E:equest 2
respectively) of the SBC 80/10 connnectors.
The second requirement would be to enter the following instructions in
RAM location 3C3DH and 3C3EH.
3C3D

CF

RST

3C3E

C9

RET

1

THIS WILL CAUSE A BREAKPOINT
THIS WILL CAUSE THE USER PROGRAM TO
BE RE-ENTERED

An example of how this is used follO\l7s:
(1) The user will start execution of his program by entering the monitor
command listed below .
. G
(2) Now the user may use a switch or a low logic level to force an interrupt to which the SBC 80/10 will respond with a RESTART 7.

•

(3) The monitor will break, save the state of the 8080 and print the following message .#3C3E.
(4) The user may now examine the 8080 registers or memory or his own
circuits interfaced to the 80/10.
(5) To resume operation, the user enters the following monitor command •
.G

Note:

In order to use this method of breakpointing, the user must have the
interrupts enabled.

•

•
..

•
•
•
."

•

•

CHAPTER 8
SYSTEM UTILIZATION
8.1

SYSTEM I/O INTERFACING
The SBC 80/10, with its memory and I/O ports, is a complete computer

•

on a single board.

However, the SBC 80/10 can also serve as a primary

master module within an expanded System 80/10, 

SPARES

INTERRUPTS

ADDRESS

DATA

DESCRIPTION

2
4
6
8
10
12

GND
VCC
VCC
VDD
VBB
GND

Signal GND
+ 5VDC
+ 5VDC
+12VDC
- 5VDC
Signal GND

Bus Clock
Bus Pri. In
Bus Busy
Mem Read Cmd
I/O Read Cmd
XFER Acknow

14
16
18
20
22
24

INIT/

Initialize

AACK/

Special

CCLK/

Constant Clock

26
28
30
32
34

Il>

IJ>

MWTC/
IOWC/

[1:>

INTRI/

43
45
47
49
51
53
55
57

ADRD/
ADRC/
ADRA/
ADR8/
ADR6/
ADR4/
ADR2/
ADRO/

44
46
48
50
52
54
56
58

ADRF/
ADRD/
ADRB/
ADR9/
ADR7/
ADR5/
ADR3/
ADRI/

59
61
63
65
67
69

[i>

60
62
64
66
68
70

[i:>
[i>
[i>
[t>

73
75
77

79
81
83
85

Address
Bus

fi>
[t:>

ft>

DAT6/
DAT4/
DAT2/
DATO/
GND
VBB[I>
VAA
VCC
VCC
GND

Data Bus

72

74
Signal GND
-10VDC
-12VDC
+ 5VDC
+ 5VDC
Signal GND

(i>Used by Intellec'" MDS Bus.
8-10

76
78
80
82
84
86

Mem Write Cmd
I/O Write Cmd

[i>

Ii>
Ii>

[i:>

•
..

[l>

36
38
40
42

71

POWER
SUPPLIES

MNEMONIC

fi>
fi>

DAT7/
DATS/
DAT3/
DATI/
GNDIJ:>
VBB
VAA
VCC
VCC
GND

Interrupt request

•
•

Address
Bus

•
Data Bus

Signal GND
-10VDC
-12VDC
+ 5VDC
+ 5VDC
Signal GND

•

•

3M 3483-1000.

Table 8-6 equates the J3 edge connector pins with the

associated RS232-compatible pins on the 3M 3483-1000 connector.

TABLE 8-6.

J3/RS232C CONNECTOR PIN CORRESPONDENCE

J3 CONNECTOR
PIN NO.

•

RS232C CONNECTOR
PIN NO.

1
2
3
4
5
6
7
8
9
10

•

1
14
2
15
3
16
4
17
5
12
6
19
7
20
8
21
9
22
10
23

11

12
13

14
15
16
17
18
19
20
21
22
23
24
25

•
8.2

11

24
12
25
13

TELETYPEWRITER MODIFICATIONS
The ASR-33 Teletypewriter must be modified for use with the System

80/10.

•

Appendix H is a procedure for modifying the ASR-33 Teletypewriter.

8-11

•
•

•
•
•
•

•
•

CHAPTER 9
INTERFACING TO MULTIBUS MASTER
The System 80/10's bus structure permits interfacing to one other
multibus-compatible master module.

Thi.s interface is accomplished using

the serial priority scheme as shown in Figure 9-1, using the Intlal SBC
604 cardcage/backplane.

The System 80/10 does not provide the Bus

Priority Request Out (BPRO/) signal and therefore, the System 80/10 can
only be used with one other multibus master.

For these configurations,

the SBC 80/10 or SBC 80/10A must always have lower priority than the
other Multibus Master and a wire must be added from Master's BREQ/ (pin

•

12) to the SBC 80/10 BPRN (pin 15).

In the configuration shown in

Figure 9-1 the SBC 80/10 acquires control of the multibus whenever BREQ/
generated by the Diskette Controller is in the high state.

This occurs

whenever the Diskette Controller is not using the multibus.

Similarly

BREQ/ is driven to the low state when the Diskette Controller acquires
control of the Multibus disabling the SBC 80/10 from accessing the multibus.

•

For a detailed description of Multibus interfacing refer to the Intel
Multibus Interfacing Application Note (AP-28).

•

HIGHEST
PRIORITY
J4

LOWEST
PRIORITY
J5

SSC202
DISKETTE
CONTROLLER

SSC 80110
MICRO·
COMPUTER

t

USER INSTALLED JUMPER

•

Figure 9-1.

Serial Priority Configuration with
SBC 80/10 and another Multibus Master
9-1

•
•

•
•
•
•

•

APPENDIX A
SYSTEM SPECIFICATIONS
A.l

GENERAL SYSTEM SPECIFICATIONS

WORD SIZE

•

Instruction:

8, 16, or 24 bits

Data:

S bits

CYCLE TIME
Basic Instruction Cycle:
Note:

1.95

~sec

Basic instruction cycle is defined as the fastest instruction
(i.e., four clock cycles).

MEMORY ADDRESSING

•

On-Board ROM/PROM:

O-lFFF

On-Board RAM:

3COO-3FFF

MEMORY CAPACITY
On-Board ROM/PROM:

4K bytes (sockets only)

On-Board ROM/PROM:

SK bytes (sockets only) (SBC SO/lOA only)
IK bytes

On-Board RAM:

•

Off-Board Expansion:
Note:

Up to 48K bytes using optional RAM, ROM, and
PROM expansion boards.

ROM/PROM may be added in IK byte increments for the SBC SO/lO
and SBC SO/lOA, or in 2K bytes on the SBC SO/lOA.

I/O ADDRESSING
On-Board Programmable I/O (see Table A-I).

Port

8255 8255
8255 No.1 8255 No.2 No.1 No.1 USART USART
Con- CanData Control
1
2
3 4 5 6
trol
trol

Address E4 E5 E6 E8 E9 EA

•

E7

EB

A-I

EC

ED

I/O CAPACITY
Parallel:
Note:

48 programmable lines (see Table A-I).

Expandable with optional I/O boards.

•
..

SERIAL BAUD RATES
Baud Rate (Hz)
Frequency (kHz)
I Jumper Selectable)

307.2
153.6
76.8
38.4
19.2
9.6
4.8
6.98

Synchronous

---

-38400
19200
9600
4800
6980

Asynchronous
I Program Selectable)

716
19200
9600
4800
2400
1200
600
300
--

764
4800
2400
1200
600
300
150
75
110

•

SERIAL COMMUNICATIONS CHARACTERISTICS
Synchronous:
5--8 bit characters

Internal or external character synchronization
~~tomatic

•

Sync Insertion

Asynchronous:

•

5--8 bit characters

Break character generation
1,

1~,

or 2 stop bits

False start bit detectors
INTERRUPTS
Single-level with on-board logic that automatically vectors processor
to location 38 16 using RESTART 7 instruction.

Interrupt requests may

originate from user-specified I/O (2), the programmable peripheral interface (2), or USART (2).

A-2

•

•
•

TABLE A-l
INPUT/OUTPUT PORT MODES OF OPERATION
- - -

PORT

NO. OF LINES

1
2
3
4

8
8
8
8
8
4
4

5
6

1.

MODE OF OPERATION
UNIDIRECTIONAL
OUTPUT
INPUT
LATCHED &
LATCHED &
LATCHED
UNLATCHED
STROBED
STROBED

X
X
X
X
X
X
X

X
X

X
X
X
X

X
X

BIDIRECTIONAL

X

Note: Port 3 must be used as a control port when either Port 1 or Port 2 are used as a latched and strobed input or a latched and
strobed output or Port 1 is used as a biairectional port.

Bus:

All signals TTL compatible

Parallel I/O:

All signals TTL compatible

Serial I/O:

RS232C or a 20 mA current loop TTY interface
(j umper-selec table)

Interrupt
Requests:

•

All TTL compatible (active-low)

SYSTEM CLOCK
2.048 MHz +0.1%
CONNECTORS
Interface

No. of
Double-Sided
Pins

Centers
(in.)

Parallel 1/0 (2)

50

0.1

3M 3415-000

0.1

3M 3462-0001
Flat
or AMP 88106-1 Flat

Serial 1/0

26

Mating Connectors

-Flat

--

•

Xl

hi

INTERFACES

•

CONTROL

A-3

PHYSI~~L

•

CHARACTERISTICS

Height:

8.90 cm (3.5 in.)

Width:
At Front Panel:

48.3 cm (19 in.)

Behind Front Panel:

43.2 cm (17 in.)

Depth:

50.8 cm (20 in. with all protrusions)

WI~ight:

13.6 kg. (30lbs.)

ELECTRICAL CHARACTERISTICS

•

Input Power:
Frequency:

47-63 Hz

Voltage:
Standard:

115 VAC +10,,:

Option:

230 VAC +10%

•

AIR CIRCULATION
2 x 37 CFM, 74 CFM total

OUTPUT POWER AVAILABLE FOR EXPANSION BOARDS:
Voltage

+12
+5
-5
-12

Power Available Power Available
Supply without PROM with PROM &
Current & Termination
Termination
Packs Installed Packs I nstalled*
2A
14A
0.9A
0.8A

1.86A
11.1A
0.898A
0.625A

1.6A
lOA
0.7A
0.625A

Over-Voltage
Protection
+14 to +16 volts
5.8 to 6.6 volts
5.8 to -6.6 volts
-14 to -16 vol ts

'PROMs are 4 each of 8708'5; Termination Packs are 10 each of
22011l330n.

•

LINE DRIVERS AND TERMINATORS
I/O Drivers:
TIle following line drivers and terminators are all compatible with
the I/O driver sockets on the SBC 80/10.

A-4

•

•
.,

Sink
Characteristic Current

Driver

Sink
Driver Chara cteristic Current
(mA)

(mA)

7438
7437
7432
7426

7409
7408
7403
7400

48
48
16
16

I,OC
I
NI
I,OC

16
16
16
16

NI, OC
NI
1,0 c
I

Note: I - Inverting; N.I.· non· Inverting; O.C.

~

open collector.

Port 1 has 25 mA totem-pole drivers and 1 lill pull-up.

•

I/O Terminators:
Terminators:
'5

220Q/330Q divider or 1 kQ pull-up.

J

'VVv220~l

220~lI330:~
_
330:~

------0 SSC 901 OPTION

1 k~l
1 kU

•
•

18 ----~'VV'v--------

--------0

sse 902 OPTION

Bus Drivers:
Function

Characteristics

Data
Adrlress
Commands

Tri-state
Tri-state
Tri-State

Sink Curren'

25
25

25

ENVIRONMENTAL
Operating Temperature:

OOC to 50°C

Non-operating Temperature:

-40°C to 85°C

SYSTEM MONITOR
Addresses:

•

A-5

•

Commands:
Display Memory (D)
Program Execute (G)
Insert Instructions into Memory (I)
Move Memory (M)
Read Hexadecimal File (R)
Substitute Memory (5)
Write Hexadecimal File (W)
Examine and Modify CPU Registers (X)
Drivers:
Console Input

•

Console Output
Reader Input
Punch Output
Breakpoints:
A hardware breakpoint capability may be implemented by an interrupt
service routine beginning at RAM location 3C3DH. Typically, a
2·-byte call is used. Interrupt generation at the breakpoint may be

•

accomplished by user hardware or by insertion of single byte calls
at instruction boundaries.

A-6

•
•

•
..

ENVIRONMENTAL TEST SPECIFICATION
(1) Line Voltage and Freguency Variation
a) 115v + 10%, 60hz + 10%
b) 230v + 10%, 50hz + 5%
(2) AC Leakage (Personnel Hazard) (L or N to ground)
a) Less than 1.46 ma rms at 115v, 60hz
b) Less than 5 ma pk at 66hz and 253 volts

•

(3) Insulation Resistance and High Potential (L & N to Ground)
a) Less than 210 ua of leakage current at 2,100 volts DC
b) No arcing or breakdown as indicated by current flunctuation.
c) Minimum insulation of 10 MH.
(4) Altitude

•

Non-operating:

25,000 ft. (10.8 in. hg.), test for 30 minutes
minimum after stabilization

Operating:

15,000 ft. (16.8 in. hg.), test for 30 minutes
at 25 0 C after stabilization - the relative
humidity is uncontrolled

(5) Temperature
a) Non-operating:
b) Operating:

•

c) Exposure:

-40 oC to +185 0 C, test for 2 hours minimum
after stabilization
OOC to 50 o C, test for 16 hours minimum after
stabilization
-20 oC to +65 0 C, test for 1 hour minimum after
stabilization

(6) Humidity
a) Five 24 hour cycles from 50% to 95% RH and from +25 0 C to +40oC,
product operating at all times.
b) Condensation at +40 oC and 95% RH with product operating at all
times.

•

(7) Vibration
a) Test at all three mutually perpendicular planes with product
operating at all times.
b) 15 minutes of cycling (15 one minute cycles) from 10-55hz and
with a .010" pk-pk excursion.
c) 3 minutes at .010" pk-pk excursion at major resonant points.
A-7

(8) Shock
a) 3 shocks on each of six sides for a total of 18 shocks.

•

b) Level 30G; duration 11 ms; shape ~ sinewave
(9) Transportation Environment (Packaging)
a) Drop Test:

•

12 free-fall, oriented drops (4 corner, S flat,
and 3 edge) on a concrete floor or slab.
1) from 30 inches high
2) from 20G to SOG shock range

b) Vibration:

0.5 inch amplitude, low frequency circular
synchronous vibration at an acceleration of
1+0.1G
1) on all positions used by common carriers in
transporting the package.
2) total vibration time is 2 hours.

•

(10) Finished Product Test
a) Unit is tested after final assembly for 48 hours at ambient
conditions.
lb) System test consists of 10 sub-tests. They are as follows:
1)
2)
3)
4)
5)
6)
7)

8)
9)

10)

Programmable Parallel I/O Port 111 Test
Programmable Parallel I/O Port 112 Test
RAM Memory Test 3DOO-·3FFF
RAM Memory Test 3COO-3CFF
CPU Instruction Test
Off Board I/O Test
Halt Test
Ready Time-out (non-existent memory and I/O) Test
Off-board Memory Access Test
External Interrupt Test

•
•
..

A-8

•

•

A.2

SBC 80/10 AND SBC 80/10A SPECIFICATIONS
TABLE A-2.

Without
EPRON 1

i

VCC +5V ±5%
Vec +12V ±5%
VBB -5V ±5%
VM -12V ±5%4

•

DC POWER REQUIREMENTS

1.

EPROM 2

With 2716 or 2758
EPROM 3

ICC = 2.9A
ICC = 150mA

4.0A

4.36A

400mA

150mA

IBB = 2mA
1M = 175mA

200mA

2mA

175mA

175mA

Does not include power

Vlith 8708

requirE~d

for optional ROM/EPROM, I/O

drivers or I/O terminators.
2.

With four Intel 8708 EPROMs and 220n/330n terminators installed for 48 input ports; all terminator inputs low.

3.

With four Intel 2716 or 2758 EPROMs and 220n/330n terminators installed for 48 input ports; all terminator inputs

•
4.

low.
Required for RS232e drivers.

•
...

•

A-9

TABLE A-3.

PARA.>.fETER

tAS
tAH
t DS
tDH
t ACK0

:r....

WITH BUS EXCHANGE
READ
MEHORY WRITE
MIN
MIN
MAX
MAX
(ns)
(ns)
ens)
ens)

82
61
140

82
0

61

0

REMARKS

Address Setup Time to Command
Address Hold. Time

658
61
140

-

DESCRIPTION

Data Setup Time to Command
Data Hold Time
First ACK Sampling Point of
Current Cycle

61

Generates 0 Wait States

68

191

tACK 1

551

684

-60

132

Second ACK Sampling Point of
Current Cycle

Generates 1 Wait State

tACK2

1034

1174

423

625

Third ACK Sampling Point of.
Current Cycle

Generates 2 Wait States

tCY

o

OVERALL
MIN
MAX
ens)
ens)

AC CFiARACTERISTICS OHTH BUS EXCHANGE)

483

493
596

~C

796

t ACC

344

t8KD

68

taKo
tXl{D
t XKO
t DBS
t BS
tDBY

100

0

0

1412

1516

-60

100

0

0

493

358

700

Read. 0 Wait States
Write. 2 Wait States

It>
fo~.

0

100

Advanced ACK Turn Off Delay
XACK Delay From Valid Data or Write

100

0

100

XACK Turn Off Delay
Bus Sample to Exchange Initiation

3500

a

Read Access Time
Advanced ACK Response Time
Minimum Delay

100

0

0

ACK & BPRN Sample Cycle Time
Command Width

~
~

~ Assume HOLD/ becomes
active prior to
DAD instruction

BPRN Sampling Point Delay
Bus Busy Turn On Delay

~ Memory and I/O access occurs with no wait states.

•

•

•

•

•

•

•

•

TABLE

PARAMETER

t AS
tAH
t DS
ton
tACK0

:r......

......

OVERALL
MIN
MAX
(ns)
(ns)

A~4.

CONTINUOUS BUS CONTROL
READ
MEMORY WRITE
MIN
MAX
MIN
MAX
(ns)
(ns)
(ns)
(ns)
82
0

658
79

Address Setup Time to Command
Address Hold Time

140

-

140

79

a

79

Data Setup T~me to Command
Data Hold Time
First ACK Sampling Point of
Current Cycle
Second ACK Sampling Point of
Current Cycle
Third ACK Sampling Point of
Current Cycle

191

tACKl

551

684

-60

132

tACK2

1034

1177

423

625

493
613
596

twc
tACC
t8KD

344

t 8Ko

a

tXKD

·0

100

0

0

100

a

110

tRW

107
25

tINT

3000

tXl{O
t RCY

DESCRIPTION

82
79

483
259

I.

•

AC CHARACTERISTICS (WITH CONTINUOUS BUS CONTROL)

68

tCY
t SEP

•

•

•

«

796

259
1412

~
1516

Command. Width

-60

Read Access Time
Advanced ACK Response Time for
Minimum Delay

100

0

100

Advanced ACK Turn Off Delay

0

100

100

85

~ MAX assumes no acknowledge delays.

~ Write Command to next Read Command separation.

Generates 0 Wait States
Generates 1 Wait State
Generates 2 Wait States

ACK & BPRN Sample Cycle Time
Command Separation

344
68

0

REMARKS

XACK Delay From Valid Data or Write
XACK Turn Off Delay
Bus Clock Cycle Time
Bus Clock Low or High Periods
Initialization Width

Read, 0 Wait States
Write, 2 Wait States

(j>

IP

80/10 Generator
80/10 Generator
After all voltages have
stabilized

TABLE A-S.
SIGNALS

ADR0/-ADRFI
ADDRESS

SYMBOL

OPEN COLLECTOR
INT
(SYSTEM RESET)

-0.25

mA

10

Capacitive Load

18

VA
pF

VOL
VOH

Output High Voltage

Output LoW' Voltage
Output High Voltage
Output Leakage High

ILL

Output Leakage Low

Output Low Voltage

VIH
IlL

Input High Voltage
Input Current at LoW' V

ILH

Output High Voltage

c

Vo

0.4

IOH '" -10 mA

vA
VA
pF

0.6

V
V

2.4
0.95

V
V

-0.25

Output Leakage High

100

vA

Output Leakage Low

Vo

100

VA

18

pF

'" 0.45

Capacitive Load

VIR

Input High Voltage

IlL

Input Current at Low V

Input LoW' Voltage

VIR

Input High Voltage

IlL

Input Current at LoW' V

-2.2

mA

=

5.5V

1

mA

18

pF

=

0.5

=

2.7V

10L

=

VIH

Input High Voltage

IIH

Input Current at High V VIN .. 5.5
Input Current at LoW' V VIN '" 0.3
Capacitive Load

10L '" 32 mA
OPEN COLLECTOR

Input LoW' Voltage

.Capacitive values are approximations only.

mA

mA
pF

V
pF

0.6

V

0.7

V

2.0

10L .. 20 mA
lOH c -1 mA

•

V

20

Output LoW' Voltage

Output High Voltage

-2.6

0.4

25 mA

VOL
VOH
V1L

Capacitive Load

V

18

Capacitive Load

Output LoW' Voltage

0.8

0.30

Capacitive Load

Output High Voltage

V

0.4V

2.0

VIN
Input Current at High V VIN

Output LoW' Voltage

V

=

Capacitive Load

•

mA

0.8
2.0

VIN
Input Current at High V. VIN

VIL

*CL

40

2.0

.

•

V

-40
15

IOL .. 50 mA

•

V

VIN " 0.45
Vo = 5.25

Input LoW' Voltage

VOL
VOIl

0.4
2.4

Input LoW' Voltage

VIL

VOL
*C L

IOL '" 32 mA
Iou = -5.2 mA
Vo .. 2.4

V
V

2.0

Capacitive Load

VOL
VOH
VIL

V

2.4
0.95

Input High Voltage
Input Current at LoW' V

ILH

IlL
*CL
BCLK + CCLK

V

VIN '" 0.45
Input Current at High V VIN .. 5.25V

IIH
*CL

BUSyl

0.6

IlL

IIH
*CL

AACK

UNITS

Input Low Voltage

ILL
*CL

BPRN/,XACK

MAX

VIL
VIH

*~

INTI/

IOL .. 50 mA
IOH co -10 IDA

MIN

Output Low Voltage

*~

DAT0/-DAT7/

TEST
CONDITIONS

PARAMETER
DESCRIPTION

VOL
VOH

lIn

mOC/,MWTCI
IORC/,lOWCI

DC CHARACTERISTICS

•
-

V
0.2
-0.9

mA

38

pF

0.5
2.7

mA

V
V

18

pF

•

•

TABLE A-S.

SIGNALS
EXT INTR01

SYMBOL

•

BIDIRECTIONAL
DRIVERS

•

DRIVERI
RECEIVER

TEST
CONDITIONS

Input Low Voltage

IlL

Input Current at Low V

Input High Voltage
Input Current at High V

MAX

UNITS

0.8

V

2.0

V

6.8

mA

Capacitive Load

2

mA

18

pF

Output Low Voltage

VIH

Input High Voltage

IlL

Input Current at Low V

VIN - 0.45

-5.25

mA

Output Leakage High

Vo

- 5.25

.30

mA

Output High Voltage

IOL - 20 mA
I OH - -12 mA

.45
2.4
.95

18

VOL
VOH
VIL

Output Low Voltag~
Output High Voltage

VIH

Input High Voltage

IlL

Input Current at Low V

IIH
*C
L

Input Current at High V
Capacitive Load

IOL - 1.7 mA
IOH • -50 VA

pF
.45

2.4

Input Low Voltage

.8

•
.

A-13

V
V
V
V

2.0
VIN - 0.45
VIN - 5.0

V
V

2.0

Capacitive Load

V
V

Input Low Voltage

*Capacitive values are approximations only •

•

VIN - 0.4V
VIN - 5.5V

MIN

VOL
VOH
VIL

ILH
*C
L
8255

PARAMETER
DESCRIPTION

VIL
VIH
IIH
*CL

PORT E4

DC CHARACTERISTICS (Continued)

10
10
18

\.IA
\.IA
pF

TABLE A-6.

II OF PINS

FUNCTION

PARALLEL I/O

25/50

SBC BOARDS COMPATIBLE CONNECTOR HARDWARE

CENTERS
(inches)

CONNECTOR
TYPE

13/26

0.1

PARALLEL I/O

25/S0

0.1

3M
3M

J

ANSLEY
SAE

3415-0000 WITH EARS
3415-0001 W/O EARS
88083-1
609-5015
SD6750 SERIES

SBC-955
(CABLE ASSY.)

3462-0001 CRIMP
88106-1
609-2615
SD6726 SERIES

SBC-9S6
(CABLE ASSY.)

AMP

FLAT CRIMP

3M

!

AMP

ANSLEY
SAE
AMP

VIKING

+

~

AUXILIARY

BUS

~

B>
PARALLEL I/O
SERIAL I/O ~
~

AUXILIARYB>

BUS
SBC
SBC
SBC
SBC

~

~

201
501
508
905, etc.

TI

13/26

0.1

SOLDERED

,

AMP

30/60

0.1

SOLDERED

VIKING

43/86

0.156

25/50

0.1

13/26

0.1

WI REWRAP

TI

30/60

0.1

WIREWRAP

CDC
TI

WI REWRAP
43/86

0.lS6

TI

t

TI

SOLDERED

CDC
MICRO PLASTICS
ARCO
VIKING

!
!
,

WIREWRAP

TI
VIKING
CDC
ITT CANNON

0.1

N/A

H312113
1-583485-5

N/A

3VH30/1JN5
H312130

N/A

D>
VPBOIE43DOOA1
MP-0156-43-BW-4
AE443WP1 LESS EARS
2VH43/1AV5

N/A

H311125
3Vl125/1JNDS
VPBOIB2SDOOAl
EC4AOSOA1A

N/A

D>

N/A

H311113

D>

CDC
CDC
VIKING

VFBOIE43DOOA1 or
VPB01E43AOOAl
2VH43/lANDS

D>

SOLDER TAIL

VIKING

3VHSO/1JN5

SOLDER PAK
(RAYCHEM)

CDC

VPB04BSOEOOAIE

D>

Connector heights are not guaranteed to conform to OEM packaging equipment.
Intel OEM and Intellec®Development System motherboards offer complete
mechanical compatibility.

~

Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment.
Intel connectors and OEM and Intellec®Development System motherboards offer
complete mechanical compatibility.

D>

CDC VPB01 ••• , VPB02 ••• , VPB04 ••• , etc. are identical connectors with
different electroplating thicknesses or metal surfaces.
NOTE:

See next page for vendor addresses, telephone numbers and TWX numbers.

A-14

...

2-583485-6
3VH25/1JVS
H312125

VPB01B30AOOA2
H311130

+
SO/100

n

FLAT CRIMP

SOLDERED

SERIAL I/O

INTEL PART

VENDOR PART

0.1

SERIAL I/O

n

VENDOR

•
•

MDS-980

MDS~985

MDS-990

D>

•

N/A

•
-

•

•
•

VENDORS ADDRESSES
The following information is for our customer's convenience only.
Intel does not represent these vendors, guarantee availability nor
continued quality of their products .
CDC CONNECTOR DIVISION
31829 W. LaTienda Drive
Westlake Village, CA 91361
213-889-3535
TWX 910-494-1224

•
•

USA

T & B/ANSLEY
Subsidiary of Thomas & Betts Corporation
3208 Humbolt Street
Los Angeles, CA 90031 USA
213-223-2331
TWX 910-321-3938

VIKING INDUSTRIES, INC.
21001 Nordhoff Street
Chatsworth, CA 91311 USA
213-341-4330
TWX 910-494-2094

STANDFORD APPLIED ENGINEERING, INC. (SAE)
340 Martin Avenue
Santa Clara, CA 95059 USA
408=243-9200
TWX 910-338-0132

Connector Systems
TEXAS INSTRUMENTS, INC.
34 Forest Street
Attleboro, MA 02703 USA
617-222-2800

3M Connectors
Electronic Products Division, Bldg. 223-4E
3M COMPANY
3M Center
St. Paul, MN 55101 USA
612-733-1110

AMP Incorporated
P.O. Box 3608
Harrisburg, PA 17105

•
•

US:

717-564-0100
TWX 510-657-4110

A-15

ADDRESS/
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•

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THIS DOCUMENT IS COPYRIGHTED BY INTEL CORPORATION
AND ITS USE FOR FABRICATION AND PRODUCTION PURPOSES
BY ANY SOURCE IS EXPRESSLY PROHIBITED.

SBC 80/10 AND SBC 80/10~
BOARD OUTLINE (1 of 2)

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C.4

POWER SUPPLY OUTLINE DRAWING FOR

vic

AA*

NOTES-

(j)

\1)
'2

@

HARNESS leNGTHS ARE FROM CENTER Of SURFACE
"A" TO CONNECTOR
•. DC OUTPUT 24 -O.S INCHES TO P6 CONN
b. DC OUTPUT 16 '.0.5 INCHES TO P8 CO~!'.
c. AC INPUT 12 ~ 0.5 INCHES TO P2 CONN

~:~.~:T~~~'~~~~~~~~~~~E·N;~~7~~"f:::yl~:~Ty~IN
ALL FOUR MOUNTING HOLES THREADED I~OA 10-24

MACHINE SCREWS.

I

r3'9MAXl

SURFACE "A"

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$--------

•

I

1----------11.125--------

f - - - - - - - - - - ' 2 .. - - - - - - - - - - l

•
•

*The System 80/10 Power Supply may come in anyone of several versions.
External electrical characteristics (including connector types) and mounting
information (including overall size) are given for all versions in the above
outline and in Chapter 6.

Internal parts, schematic, and exact outline dimen-

sions will vary between versions.

To determine the version you have, see the

two letter code on the side panel closest to the "AC Low" signal output connector.

The vendor code is the third group of code following the assembly

number and revision level code.
See silkscreen on power supply PC board for location of voltage and current

•

adjustment trimmers.

C-5

•
•
•
•
.

•

•

APPENDIX D

8080 INSTRUCTION SET SUMMARY

•

When a computer is designed, the engineers providt:
the Central Processing Unit (CPU) with the ability
to perform a particular set of operations. The CPU
is designed sllch that a specific operation is performed wht'n the CPU control logic decodes a p,ntil'ular instruction. Consequently, tht: operations
that can be performed by a CPU define the computer's Instruction Set.

•

Each computer instruction allows the programmer
to initiate the performance of a specific operation.
All computers implement certain arithmetic operations in their instruction set, such as an instruction
to add the contents of two registers. Often logical
operations (e.g., OR the contents of two registers)
and register operate instructions (e.g., increment a
register) are included in the instruction set. A computer's instruction set will also have instructions
that move data between registers, between a register and memory, and between register and an I/O
device. Most instruction sets also provide Conditional Instructions. A conditional instruction specifics an operation to be performed only if certain
conditions have been met; for example, jump to a
particular instruction if the result of the last operation was zero. Conditional instructions provide a
program with a decision-making capability.

•
•

form (i.c., a series of l's and O's), that is called
Machine Code. UeeausL' it would lw extrell1ely
cumbersome to program ill machine code, programming languages have beell developed. There
are programs available which cOllvert the programming language instructions into machine code
that can be interpreted hy t he processor.

A computer, no mattt:r how sophisticated, can
only do what it is "told" to do. One "tells" the
computer what to do via a series of coded instructions referred to as a Program. The realm of the
programmer is referred to as Software, in contrast
to the Hardware that cOl11prist:s the actual computer eq uipment. A computer's software refers to
all of the programs that have bt:en written for that
computer.

One type of programming language is Assemhly
Language. A unique assl'mbly language nlIll'lllOlIil'
is assigned to each of the computer's instructions.
The programmer can write a program (called the
Source Program) lIsing these mnemonics and certain operands; the source program is then converted into machine instructions (called the Objed
Code). Eal.:h assembly language instructions is COIIverted into one machine code instruction (lor
more bytes) by an Assembler program. Assembly
languages are llsually machine dependent (Le., they
are usually able to run on only one type of computer).

THE 8080 INSTRUCTION SET
The 8080 instruction set includes five different
types of instructions:

• Data Trallsfer Group - move data between
registers or between memory and registers.
• Arithmetic Group - add, subtract, increment
or decrement data in registers or in memory.
• Logical Group - AND, OR, EXCLUSIVEOR, compare, rotate or complement data in
registers or in memory.
• Brallch Group -

conditional and unconditional jump instructions, subroutine call instructions and return instructions.

By logically organizing a sequence of instructions
into a coherent program, the progranlmer can
"tell" the computer to perform a very specific and
useful function.

•

• Stack, I/O and Machine COlltrol Group - includes I/O instructions, as well as instructions
for maintaining the stack and internal control
flags.

The computer, however, can only execute programs whose instructions are in a binary coded

All Mnemonics © 1976 Intel Corp.

D-l

Instruction and Data Formats

Addressing Modes

Memory for the 8080 is organized into 8-bit quantities, called Bytes. Each byte has a unique 16-bit
binary address corresponding to its sequential position in memory.

Often the data that is to be operated 011 is stored in
memory. When multi-byte numeric data is ·used,
the data, like instructions, is stored· in successive
memory locations, with the least significant byte
first, followed by increasingly significant bytes.
The 8080 has four different modes for addressing
data stored in memory or in registers:

The 8080 can directly address up to 65,536 bytes
of memory, which may consist of both read-only
memory (ROM) elements and random-access memory (RAM) elements (read/write memory).

• Direct ~ Bytes 2 and 3 of the instruction contain the exact memory address of the data
item (the low-order bits of the address are
in byte 2, the high-order bits in byte 3).

Data in the 8080 is stored in the form of 8-bit
binary integers:
DATA WORD

I

D7

I

D6

1

D5

I

D4

I

D3

1

D2

I

D1

MSB

I

DO

I

• Register ~ The instruction specifies the register-pair in which the data is located.

LSB

• Register Indirect - The instruction specifies a
register-pair which contains the memory
address where the data is located (the highorder bits of the address are in the first
register of the pair, the low-order bits in
the second).

When a register or data word contains a binary
number, it is necessary to establish the order in
which the bits of the number are written. In the
Intel 8080, BIT 0 is referred to as the Least Significant Bit (LSB), and BIT 7 (of an 8-bit number) is
referred to as the Most Significant Bit (MSB).

• Immediate - The instruction contains the
data itself. This is either an 8-bit quantity
or a 16-bit quantity (least significant byte
first,most significant byte second).

The 8080 program instructions may be one, two or
three bytes in length. Multiple byte instructions
must be stored in successive memory locations; the
address of the first byte is always used as the address of the instructions. The exact instruction format will depend on the particular operation to be
executed.

Unless directed by an interrupt or branch instruction, the execution of instructions proceeds
through consecutively increasing memory locations. A branch instruction can specify the address
of the next instruction to be executed in one of
two ways:

Single Byte Instructions

I

D7

1

1 DO

I

OpCode

• Direct _. The hranch instruction contains the
address of the next instruction to be executed. (Except for the 'RST' instruction,
byte 2 contains the low-order address and
byte 3 the high-order address.)

Two·Byte Instructions
Byte One

10 71

10 0

I

op Code

Byte Two

1071

1 DO

I

Data or
Address

• Register Indirect - The branch instruction
indicates a register-pair which contains the
address of the next instruction to be executed. (The high-order bits of the address
are in the first register of the pair, the loworder bits in the second.)

Three·Byte Instructions
Byte One
Byte Two

01
1071
1 7

Byte Three 10 71

I DO

I

OpCode

5J) D,,"
1 00

I

•

or

The RST instruction is a special one-byte call instruction (usually used during interrupt sequences).

Address

All Mnemonics © 1976 Intel Corp.

D-2

•
•
•
•

•

•

RST includes a three-bit field; program control is
transferred to the instruction whose address is
eight times the contents of this three-bit field.

SYMBOLS

MEANING

accumulator

Register A

addlt'

16-bit address quantity

Condition Flags

data

8-bit data quantity

data 16

16-bit data quantity

byte 2

The second byte of the instruction

byte 3

The third byte of the instruction

port

8-bit addr~ss of an I/O device

r,r,l,r2

One of the registers A,B,C,D,E,H,L

DDD,SSS

The bit pattern designating one of
the registers A,B,C,D,E,H,L. (DD=
destination, SSS=source):

There are five condition flags associated with the
execution of instructions on the 8080. They are
Zero, Sign, Parity, Carry, and Auxiliary Carry, and
are each represented by a I-bit register in the CPU.
A flag is "set" by forcing the bit to 1; "reset" by
forcing the bit to O.
Unless indicated otherwise, when an instruction
affects a flag, it affects it in the following manner:

•

Zero:

Sign:

DOD or SSS

If the result of an instruction has the
value 0, this flag is set; otherwise it is
reset.
If the most significant bit of the result
of the operation has the value 1, this
flag is set; otherwise it is reset.

111

A

000
001
010

B

011
100
101

Parity:

•
•
•

Carry:

If the modulo 2 sum of the bits of the
result of the operation is 0 (Le., if the
result has even parity), this flag is set;
otherwise it is reset (Le., if the result
has odd parity).

rp

REGISTER NAME

C
D

E
H
L

One of the register pairs:
B represents the B,C pair with B
as the high-order register and C
as the low-order register;
D represents the D,E pair with D
as the high-order register and E
as the low-order register;

If the instruction resulted in a carry
(from addition), or a borrow (from
subtraction of a comparison) out of
the high-order bit, this flag is set;
otherwise it is reset.

H represents the H,L pair with H
as the high-order register and L
as the low-order register;

Auxiliary
Carry:
If the instruction caused a carry out
of bit 3 and into bit 4 of the resulting
value, the auxiliary carry is set; otherwise it is reset. This flag is affected by
single precision additions, subtractions, increments, decrements, comparisons, and logical operations, but is
principally used with additions and
increments preceding a DAA (Decimal
Adjust Accumulator) instruction.

SP represents the 16-bit stack
pointer register.
RP

The bit pattern designating one of
the register pairs B,D,H,SP:
RP

00
01
10

11

REGISTER PAIR

B-C
D-E
H-L
SP

Symbols and Abbreviations

rh

The first (high-order) register of a
designated pair.

The following symbols and abbreviations are used
in the subsequent description of the 8080 instructions:

rl

The second (low-order) register of a
designated register pair.
All Mnemonics © 1976 Intel Corp.

D-3

PC

SP

16-bit program counter register
(PCB and PCL are used to refer to
the high-order and low-order 8 bits,
respectively).

3. The next line(s) contain a symbolic description
of the operation of the instruction.

4. This is followed by a narative description of the
operand of the instruction.

16-bit stack pointer register (SPH
and SPL are used to refer to the
high-order and low-order 8 bits,
respectively).

5. The following line(s) COil tain the binary fields
and patterns that comprise the machine instruction.

Bit m of the register r (bits are
number 7 through 0 from left to
right).
Z,S,P,CY,AC

6. The last four lines contain incidental information about the execution of the instruction. The
number of machine cycles and states required to
execute the instruction are listed first. If the
instruction has two possible execution times, as
in a Conditional Jump, both times will be listed,
separated by a slash. Next, any significant data
addressing modes (see Page A-2) are listed. The
last line lists any of the five Flags that are affected by the execution of the instruction.

The condition flags:
Zero,
Sign,
Parity,
Carry, and
Auxiliary Carry, respectively.

( )

•

The contents of the memory location or registers enclosed in the
parentheses.

•

Data Transfer Group

"Is transferred to"A
f\

Logical AND

V

Exclusive OR

V

Inclusive OR

+

Addition

This group of instructions transfer data to and
from registers and memory. Condition flags are not
affected by any instruction in this group.

MOV rl, r2

(r I) +-- (r2)
The content of register r2 is moved to register rI.

Two's complement subtraction

*

(Move Register)

M ul tiplication

•

o

"Is exchanged with"
The one's complement (e.g., (A»

n

The restart number 0 through 7

NNN

The binary representation 000
through III for restart number 0
through 7, respectively.

Cycles:

1

States:

5

Addressing:

Flags:

•

register

none

MOV r,M
(Move from memory)
(r) +-- «H) (L»

Description Format

The content of the memory location, whose address is in registers Hand L, is moved to register
r.

The following pages provide a detailed description
of the instruction set of the 8080. Each instruction
is described in the following manner:

o

I. The MAC 80 assembler format, consisting of the
instruction mnemonic and operand fields, is
printed in BOLDFACE on the left side of the
first line.

o

o

o
Cycles:

2

States:

7

Addressing:

Flags:

o

reg. indirect

none

2. The name of the instruction is enclosed in parenthesis on the right side of the first line.
All Mnemonics © 1976 Intel Corp.

D-4

•

•

•

MOV M, r
(Move to memory)
((H)(L» +- (r)
The content of register r is moved to the memory location whose address is in registers Hand
L.

o
Cycles:
States:
Addressing:
Flags:

S

S

S

LXI rp, data 16
(Load regiskr pair illll1lcJiatd
(rh) +- (byte 3),
(rl) +- (byte 2)
Byte 3 of the instruction is moved into the highorder register (rh) of the register pair rp. Byte 2
of the instruction is moved into the low-order
register (rl) of the register pair rp.

o

2

I

o

I

Rip

I

none

high-order data

MVI r, data
(Move Immediate)
(r) +- (byte 2)
The content of byte 2 of the instruction is
moved to register r.

o I

0

o

I

1

1

o

data

•

Cycles:

2

States:

7

Addressing:
Flags:

o

I

0

I

1

1

I

1

I

1

I

o

I

1

I

0

high-order addr

immediate
none

I

I

low-order addr

Cycles:

MVI M, data
(Move to memory immediate)
((H)(L» +- (byte 2)
The content of byte 2 of the instruction is
moved to the memory location whose address is
in registers Hand L.
0

0

LOA addr
(Load Accumulator direct)
(A) +- «byte 3)(byte 2»
The content of the memory location, whose address is specified in byte 2 and byte 3 of the
instruction, is moved to register A.

4
13
direct

Flags:

o I

I

nona

States:
Addressing:

•

o

3
10
immediate

Flags:

o I 0

I

low-order data

Cycles:
States:
Addressing:

•

0

7
reg. indirect

o

o

STA addr
(Store Accumulator direct)
((byte 3)(byte 2» +- (A)
The content of the accumulator is moved to the
memory location whose address is specified in
byte 2 and byte 3 of the instruction.

oT o

data

none

I

1

I

1

o

I

I

o

I

1

I 0

low-ordar addr
Cycles:
States:
"Addressing:
Flags:

3
10
immed./reg. indirect
none

high-order addr
Cycles:
States:
Addressing:

•

Flags:

4
13
direct
none

All Mnemonics © 1976 Intel Corp.

D-5

STAX rp
(Store accumulator indirect)
«rp» +- (A)
The content of register A is moved to the memory location whose address is in the register pair
rp. Note: Only register pairs rp=B (registers B
and C) or rp=O (registers 0 and E) may be specified.

LHLD addr
(Load Hand L direct)
(L) ~ «byte 3)(byte 2)
(H) ~ «byte 3)(byte 2) + I)
The content of the memory location, whose address is specified in byte 2 and byte 3 of the
instruction, is moved to register L. The content
of the memory location at the succeeding address is moved to register H.

o

I

o

I

1

I

o

I

1

I

o

I

1

I

I 0

o

0

low·order addr

I

R

p
Cycles:

2

States:

7

Addressing:

high-order addr

Flags:
Cycles:
States:

1

I

o

none

none

(H)
(L)

SH LD addr
(S tore Hand L direct)
«byte 3)(byte 2)) ~ (L)
«byte 3)(byte 2) + I) ~ (H)
The content of register L is moved to the memory location whose address is specified in byte 2
and byte 3. The content of register H is moved
to the succeeding memory location.
I

reg. indirect

16

XCHG

0

o

direct

Flags:

I

0

5

Addressing:

o

I

o

I

I

o

I

1

I

(Exchange Hand L with 0 and E)
+-+
+-+

(D)
(E)

The contents of registers Hand L are exchanged
with the contents of registers 0 and E.
I 0

1

States:

4

Addressing:

0

I 1 I 0

Cycles:

Flags:

•

register
none

high-order addr
Cycles:

5

States:

16

Flags:

direct
none

LDAX rp
(Load accumulator indirect)
(A) ~ «rp»
The content of the memory iocation, whose address is in the register pair rp, is moved to register A. Note: Only register pairs rp=B (registers B
and C) or rp=O (registers D and E) may be specified.

DCR M
(Decrement memory)
«H)(L» ~ «H)(L» - I
The content of the memory location whose address is contained in the Hand L registers is
decremented by one. Note: All condition flags
except CY are affected.

o
Cycles:
States:
Addressing:
Flags:

o

I

R

P

I

Cycles:

2

States:

7

Addressing:
Flags:

1

o

•

I 1 I

low-order addr

Addressing:

•

1

•

3
10
reg. indirect
Z.S.P,AC

.

o

INX rp
(Increment register pair)
(rh)(rl) +- (rh)(rl) + I
The content of the register pair rp is incremented by one. Note: No condition flags are affected.

reg. indirect
none

All Mnemonics © 1976 Intel CorD.

D-6

•

I

0

o

•

I

R

P

I

0

Cycles:

1

States:

5

Addressing:

ADI data

o

+ (byte

2)

The content of the second byte of the instruction is added to the constant of the accumulator. The result is placed in the accumulator.

register

Flags:

(Add Immediate)

(A) +- (A)

none

I

I'

Arithmetic Group

0

o I

Cycles:

2

States:

7

Addressing:
Flags:

•

(A)

All subtraction operations are performed via two's
complement arithmetic, and s~t the carry flag to
one to indicate a borrow and clear it to indicate no
borrow.
ADD r
(A)

•

•

Z,S,P,CY,AC

(Add Register with Carry)
+-

(A) + (r) + (CY)

o

o

o

1

(A) + (r)

The content of register r is added to the content
. of the accumulator. The result is placed in the
accumulator.

Cycles:

1

States:

4

Addressing:
Flags:

o

o

o

o
Cycles:

1

States:

4

Flags:

S

S

I 0

register

Cycles:

2

States:

7

Addressing:
Flags:.

S

S

register
Z,S,P,CY,AC

ADC M
(Add Memory with Carry)
(A) +- (A) + «H)(L» + (CY)
The content of the memory location whose address is contained in the Hand L registers and
the content of the CY flag are added to the accumulator. The result is placed in the accumulator,

Z,S,P,CY,AC

I 0 I 0 I 0

I

S

ADD M
(Add Memory)
(A) +- (A) + «H)(L»)
The content of the memory location whose address is contained in the Hand L register is
added to the content of the accumulator. The
result is placed in the accumulator.
1

immediate

The content of register r and the content of the
carry bit are added to the content of the accumulator. The result is placed in the accumullator.

(Add Register)
+-

Addressing:

•

ADC r

I 0

data

This group of instructions performs arithmetic
operations on data in registers and memory.
Unless otherwise indicated, all instructions in this
group affect the Zero, Sign, Parity, Carry, and
Auxiliary Carry flags according to the standard
rules.

I 1

0

o

o

I

o

o
Cycles:

2

States:

7

Addressing:
Flags:

reg. indirect
Z,S,P,CY,AC

reg. indirect
Z,S,P,CY,AC

All Mnemonics

D-7

© 1976 Intel Corp.

(Subtract Immediate)
(A) +- (A) - (byte 2)
The content of the second byte of the instruction is subtracted from the content of the accumulator. The result is placed in the accumulator.

SUI data

ACI data
(Add Immediate with Carry)
(A) ~ (A) + (byte 2) + (CY)

The content of the second byte of the instruction and the content of the CY flag are added to
the contents of the accumulator. The result is
placed in the accumulator.

p

data
Cycles:
States:
Addressing:
Flags:

Cycles:

2

7

States:

7

Addressing:

immediate

Flags:

Z,S,P,CY,AC

I

0

I

o

0

Cycles:

1

States:

4

Addressing:
Flags:

S

S

S

S

register

I 0
Cycles:

2

States:

7

Addressing:
Flags:

Cycles:

1

States:

4

Addressing:

Z,S,P,CY,AC

Flags:

I S

•

I S

register
Z,S,P,CY,AC

•

SBB M
(Subtract Memory with Borrow)
(A) ~ (A) - «H)(L) - (CY)

The content of the memory location whose address is contained in the Hand L registers and
the content of the CY flag are both subtracted
from the accumulator. The result is placed in the
accumulator.

The content of the memory location whose address is contained in the Hand L registers is subtracted from the content of the accumulator.
The result is placed in the accumulator.
o

Z,S,P,CY,AC

The content of register r and the content of the
CY flag are both subtracted from the accumulator. The result is placed in the accumulator.

SUB M
(Subtract Memory)
(A) +- (A) - «H)(L))

o

immediate

SBB r
(Subtract Register with Borrow)
(A) +- (A) - (r) - (CY)

~

1

o

data

2

(Subtract Register)
(A) - (r)
The content of register r is subtracted from the
content of the accumulator. The result is placed
in the accumulator.

SUB r
(A)

o

o

•

I 0

1

reg. indirect

I 0

I 0
Cycles:

2

States:

7

Addressing:
Flags:

Z,S,P,CY,AC

..

reg. indirect
Z,S,P,CY,AC

All Mnemonics © 1976 Intel Corp.

D-8

•
•

•

OCR r

SBI data
(Subtract Immediate with Borrow)
(A) +- (A) - (byte 2) - (CY)
The contents of the second byte of the instruction and the contents of the CY flag are both
subtracted from the accumulator. The result is
placed in the accumulator.

I'

(Decrement Register)

(r) +- (r) - I

The content of register r is decremented by one.
Note: All condition flags except CY are affected.

o

o

o
data

o

Cycles:

1

States:

5

Addressing:
Flags:

Cycles:

2

States:

7

Addressing:
Flags:

•

Z,S,P,CY,AC

(Increment Register)
(r) +- (r) + I
The content of register r is incremented by one.
Note: All condition flags except CY are affected.

o I

•
•

Cycles:

1

States:

5

..

Flags:

o
1
5
register
Z,S,P,AC

o I

3
10

Addressing:
Flags:

none

0
Cycles:
States:
Addressing:
Flags:

o
States:

register

DAD rp
(Add register pair to Hand L)
(H)(L) +- (H)(L) + (rh)(r1)
The content of the register pair rp is added to
the content of the register pair Hand L. The result is placed in the register pair Hand L. Note:
Only the CY flag is affected. It is set if there is a
carry out of the double precision add; otherwise
it is reset.

INR M
(Increment Memory)
«H)(L» +- «H)(L» + I
The content of the memory location whose address is contained in the Hand L registers is
incremented by one. Note: All condition flags
except CY are affected.

Cycles:

register
Z,S,P,AC

0

Addressing:

Cycles:
States:
Addressing:
Flags:

o

DCX rp
(Decrement register pair)
(rh)(rl) +- (rh)(rl) - I
The content of the register pair rp is decremented by one. Note: No condition flags are
affected.

immediate

INR r

o

o

o

3
10
register
CY

DAA
(Decimal Adjust Accumulator)
The 8-bit number in the accumulator is adjusted
to form two 4-bit Binary-Coded-Decimal digits
by the following process:

reg. indirect
Z,S,P,AC

I. If the value of the least significant 4 bits of
the accumulator is greater than 9 or if the AC
flag is set, 6 is added to the accumulator.

•

All Mnemonics © 1976 Intel Corp.

D-9

2. If the value of the most significant 4 bits of
the accumulator is now greater than 9, or if
the CY flag is set, 6 is added to the most significant 4 bits of the accumulator.

o

o

0

Cycles:

2

States:

7

Addressing:
Flags:

NOTE: All flags are affected.

o

reg. indirect
Z.S.P.CY,AC

•

'1

Cycles:

,

States:

4

Flags:

ANI data
(AND immediate)
(A) +- (A) /\ (byte 2)
The content of the second byte of the instruction is logically ANDed with the contents of the
accumulator. The result is placed in the accumulator. The CY flag is cleared.

Z.S.P.CY,AC

Logical Group

, 1 , 1 , 1 0 1 0 1 ,1,10

This group of instructions performs logical (Boolean) operations on data in registers and memory
and on condition flags.

data

Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Auxiliary Carry, and Carry flags according to the standard rules.

ANA r
(A)

Cycles:

2

States:

7

Addressing:
Flags:

immediate

•

Z.S,P,CY,AC

(AND Register)
~

(A) /\ (r)

XRA r
(Exclusive OR Register)
(A) +- (A) V (r)
The content of register r is exclusive-ORed with
the content of the accumulator. The result is
placed in the accumulator. The CY and AC flags
are cleared.

The content of register r is logically ANDed with
the content of the accumulator. The result IS
placed in the accumulator. The CY flag IS
cleared.
,

I 0

o

o

S

S

S

•

o
Cycles:

,

States:

4

Addressing:

register

Flags: Z.S.P,CY.AC

Cycles:

,

States:

4

Addressing:
Flags:

ANA M
(A)

+-

register
Z,S,P,CY.AC

XRA M
(Exclusive OR Memory)
(A) +- (A) V «H)(L»
The content of the memory location whose address is contained in the Hand L registers is
exclusive-ORed with the content of the accumulator. The result is placed in the accumulator.
The CY and AC flags are cleared.

(AND memory)
(A) /\ ((11)( L)

The contents of the memory location whose address is contained in the Hand L registers is
logically ANDed with the content of the accumulator. The CY flag is cleared.

All Mnemonics © 1976 Intel Corp.

D-10

•
•

•

o

•

o

1

1

Cycles:

2

States:

7

Addressing:

ORI data
(OR Immediate)
(A) ~ (A) V (byte 2)
The content of the second byte of the instruction is inclusive-ORed with the content of the
accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.

o

reg. indirect

Flags:

Z,S,P,CY,AC

~____________1___I_O___1__
1 ~
XRI data
(Exclusive OR immediate)
(A) ~ (A) V (byte 2)
The content of the second byte of the instruction is excIusive-ORed with the content of the
accumulator. The result is placed in the accumulator. The CY and AC flags are cleared.
1

I

1

•

I

I

data
Cycles:

2

States:

7

(A)

Z,S,P,CY,AC

(OR Register)

7

Addressing:
Flags:

CMP r

immediate
Z,S,P,CY,AC

(Compare Register)

~

(A) V (r)

I 0 I 1

The content of register r is inclusive-ORed with
the content of the accumulator. The result is
placed in the accumulator. The CY and AC flags
are cleared.
I 0

o
Cycles:

1

States:

4

Addressing:
Flags:

ORA M

S I S

0

I

1

States:

4

CMP M

register
Z,S,P,CY,AC

(Compare memory)

Z.S,P,CY,AC

The content of the memory location whose address is contained in the Hand L registers is subtracted from the accumulator. The accumulator
remains unchanged. The condition flags are set
as a result of the subtraction. The Z flag is set to
1 of (A) = «H)(L». The CY flag is set to 1 if
(A) < «H)(L».

0

I

1

0

I

1

I

0

I

o

1
Cycles:

Cycles:

2

States:
Addressing:

States:

7

Flags:

Flags:

S

(A) - «H)(L»

I

Addressing:

S

register

(A) ~ (A) V «H)(L))

I

Cycles:
Addressing:

I S

(OR Memory)

1

S

Flags:

The content of the memory location whose address is contained in the Hand L registers is
inclusive-ORed with the content of the accumulator. The result is placed in the accumulator.
The CY and AC flags are cleared.

I

•

2

States:

The content of register r is subtracted from the
accumulator. The accumulator remains unchanged. The condition flags are set as a result
of the subtraction. The Z flag is set to I if (A) =
(r). The CY flag is set to 1 if (A) < (r).

immediate

Addressing:

ORA r

•

Cycles:

(A) - (r)

Flags:

•

']

I

101

===:=J

data

2
7
reg. indirect
Z,S.P,CY,AC

reg. indirect
Z,S,P,CY,AC

All Mnemonics © 1976 Intel Corp.

CPI data

(Compare immediate)

RAL

(Rotate left through carry)
(An+d +- (An); (CY) +- (A7)
(AO) +- (CY)
The content of the accumulator is rotated left
one position through the CY flag. The low-order
bit is set equal to the CY flag and the CY flag is
set to the value shifted out of the high-order bit.
Only the CY flag is affected.

(A) - (byte 2)

The content of the second byte of the instruction is subtracted from the accumulator. The
condition flags are set by the result of the subtraction. The Z flag is set to I if (A) = (byte 2).
The CY flag is set to I if (A) < (byte 2),

(]I

data
Cycles:
States:
Addressing:
Flags:

0

0

0

2
7

Cycles:

1

States:

4
CY

Flags:

immediate
Z,S,P,CY,AC

RAR

(Rotate right through carry)

(An) +- (A n+!); (CY) +- (Ao)
(A7) +- (CY)

RLC

The content of the accumulator is rotated right
one position through the CY flag. The highorder bit is set to the CY flag and the CY flag is
set to the value shifted out of the low-order bit.
Only the CY flag is affected.

(Rotate left)

(A n+!) +- (An); (Ao)
(CY) +- (A7)

+-

(A7)

The content of the accumulator is rotated left
one position. The low-order bits and the CY flag
are both set to the value shifted out of the highorder bit position. Only the CY flag is affected.

o

o

o

0

11:
~

I

0

I

Cycles:

1

States:

4

Flags:
1

States:

4
CY

CMA

•

0

0

Cycles:
Flags:

•

•

CY

(Complement accumulator)

(A) +- (A)

The contents of the accumulator are complemented (zero bits become I, one bits become 0).
No flags are affected.

RRC
(An)

c0-

(Rotate right)

(An-I); (A7) +- (Ao)
(CY) +- (Ao)
+-

The content of the accumulator is rotated right
one position. The high-order bit and the CY flag
are both set to the value shifted out of the loworder bit position. Only the CY flag is affected.
o

o

o

o
Cycles:

1

States:
Flags:

4
CY

o

0

1

Cycles:

1

States:

4
none

Flags:

•

CMC
(Complement carry)
(CY) +-, (CY)
The CY flag is complemented. No other flags are
affected.

LiO

I 0

1

'
Cycles:

1

States:

4

Flags:

CY

All Mnemonics © 1976 Intel Corp.

D-12

•

•

STC
(Set carry)
(CY) ~ 1
The CY flag is set to 1. No other flags are affected.

o

I 0

1

I

1

0

I

•
•

I

o

I

1

1

I

high-order addr

I 1
Cycles:
Cycles:
States:
Flags:

3

States:

1

10

Addressing:

4

immediate

Flags:

CV

none

(Conditional jump)

(PC) ~ (byte 3)(byte 2)
If the specified condition is true, control is

Branch Group

•

0

I

low-order addr

Jcondition addr
If (CCC),

•

0

transferred to the instruction whose address is
specified in byte 3 and byte 2 of the current instruction; otherwise, control continues sequentially.

Tills group of instructions alter normal sequential
program flow.
Condition flags are not affected by an instruction
in this group.

1

I

1

Ic

I

C

Io

C

I

I

1

I

0

low-order addr

The two types of branch instructions are unconditional and conditional. Unconditional transfers
simply perform the specified operation on register
PC (the program counter). Conditional transfers
examine the status of one of the four processor
flags to determine if the specified branch is to be
executed. The conditions that may be specified are
as follows:
CONDITION

CCC

NZ
Z
NC
C

000
001
010
011
100
101
110
III

PO
PE
P
M

-

not zero (Z=O)
zero (Z = 1)
no carry (C = 0)
carry (CY = 1)
parity odd (P = 0)
parity even (P = 1)
plus (S =0)
minus (S = 1)

(Jump)
(PC) ~ (byte 3)(byte 2)
Control is transferred to the instruction whose
address is specified in byte 3 and byte 2 of the
current instruction.

JMP addr

high-order addr
Cycles:

3

States:
Addressing:

10
immediate

Flalll:

none

(Call)
«SP) - 1) ~ (PCH)
«SP) - 2) ~ (PCL)
(SP) ~ (SP) - 2
(PC) ~ (byte 3)(byte 2,)
The high-order 8 bits of the next instruction
address are moved to the memory location
whose address is one less than the content of
register SP. The low-order 8 bits of the next
instruction address are moved to the memory
location whose address is two less than the content of register SP. The content of register SP is
decremented by 2. Control is transferred to the
instruction whose address is specified in byte 3
and byte 2 of the current instruction.

CALL addr

1

I

1

I

0

I

0

I

1

I

1

I

o

I

1

low-order addr
high-order addr

•

Cycles:
States:
Addressing:
Flags:

D-13

5
17
immed./reg. indirect
none

All Mnemonics © 1976 Intel Corp.

Ccondition addr
(Condition call)
If (CCC),
«SP) - 1) ... (PCH)
«SP) - 2) ... (PCL)
(SP) ... (SP) - 2
(PC) ... (byte 3)(byte 2)
If the specified condition is true, the actions
specified in the CALL instruction (see above)
are performed; otherwise, control continues
sequentially.
1

I

1

I

C

I

C

I

C

I

1

I

0

C

Cycl..:
States:
Addressing:
Flags:

C

0 0 0

•

1/3
5/11

reg. indirect
none

RST n
(Restart)
«SP) - 1) ... (PCH)
«SP) - 2) ... (PCL)
(SP) ... (SP) - 2
(PC) ... 8 * (NNN)
The high-order 8 bits of the next instruction address are moved to the memory location whose
address is one less than the content of register
SP. The Iow-order 8 bits of the next instruction
address are moved to the memory location
whose address is two less than the content of
register SP. The content of register SP is decremented y two. Control is transferred to the
instruction whose address is eight times the content ofNNN.

I 0

low-order addr
high-order addr
Cycl..:
Stat..:
Addressing:
Flags:

C

3/5
11/17
immed./reg. indirect
none

t

RET
(Return)
(PCL) ... «SP»;
(PCH)'" «SP) + 1);
(SP) ... (SP) + 2;
The content of the memory location whose address is specified in register SP is moved to the
low-order 8 bits of register PC. The content of
the memory location whose address is one more
than the content of register SP is moved to the
high-order 8 bits of register Pc. The content of
register SP is incremented by 2.
1

o

o

Cycl..:
Stat..:
Addressing:
Flags:

o

o

1

N

N

Cycl..:
Stat..:

N

•

1

3
11

•

Addressing:' reg. indirect
Flags: none

15 14 13 12 11 10 9 8 7 6 5

4

3

2 1 0

1010101010101010 10101N 1N 1N 101010I
Program Counter After Restart

1

PCH L

3
10
reg. indirect
none

(J ump Hand L indirect - move Hand

L to PC)
(PCH)'" (H)
(PCL)'" (L)
The content of register H is moved to the highorder 8 bits of register PC. The content of register L is moved to the low-order 8 bits of register
PC.

Rcondition
(Conditional return)
If (CCC),
(PCL) ... «SP»
(PCH) ... «SP) + 1)
(SP) ... (SP) + 2
If the specified condition is true, the actions
specified in the RET instruction (see above) are
performed; otherwise, control continues sequentially.

o
Cycles:
States:
Addressing:
Fla.:

o

o

1
5
register
none

All Mnemonics © 1976 Intel Corp.

D-14

•
•

Stack, I/O, and Machine Control Group

•

FLAG WORD

This group of instructions performs I/O, manipulates the Stack, and alters internal control flags.

•
•

04

D3

D2

D1

DO

0

AC

0

p

1

CY

POP rp

(POp)
(rl) +- «SP))
(rh) +- «SP) + 1)
(SP) +- (SP) + 2
The content of the memory location, whose address is specified by the content of register SP, is
moved to the low-order register of register pair
rp. The content of the memory location, whose
address is one more than the content of register
SP, is moved to the high-order register of register
pait rp. The content of register SP is incremented by 2. Note: Register pair rp=SP may not
be specified.

The content of the high-order register of register
pair rp is moved to the memory location whose
address is one less than the content of register
SP. The content of the low-order register of register pair rp is moved to the memory location
whose address is two less than the content of
register SP. The content .of register SP is decremented by 2. Note: Register pair rp=SP may not
be specified.

o

p

Cycles:

3

States:

11

Addressing:
Flags:

o

R

Addressing:
Flags:

none

PUSH PSW
(Push processor status word)
«SP)
I) +- (A)
«SP) - 2)0 +- (CY, «SP) - 2h +- 1
«SP) - 2h +- (P), «SP) - 2)) +- 0
«SP) - 2)4 +- (AC), «SP) - 2)5 +- 0
«SP) - 2)6 +- (Z), «SP) - 2h +- (S)
(SP) +- (SP) - 2
The content of register A is moved to the memory location whose address is one less than register SP. The contents of the condition flags are
assembled into a processor status word and the
word is moved to the memory location whose
address is two less than the contcnt of register
SP. The content of register SP is decremented by
two.

POP PSW

o

3
10
reg. indirect.
none

(POp processor status word)

(SP) +- (SP) + 2
The content of the memory location whose address is specified by the content of register SP is
used to restore the condition flags. The content
of the memory location whose address is one
more than the content of register SP is moved to
register A. The content of register SP is incremented by 2.

o

o

3

Cycles:

States:

11

States:

Flags:

o

(CY) +- «SP)o
(P) +- «SP))2
(AC) +- «SP»4
(Z) +- «SP))6
(S) +- «SP)h
(A) +- «SP) + 1)

Cycles:
Addressing:

o

P
Cycl.:
Stat.:

reg. indirect

o

•

DS

Unless otherwise specified, condition flags are not
affected by any instructions in this group.

R

•

DS

I Iz I I I I I I I
S

(Push)
PUSH rp
«SP) - I) +- (rh)
«SP) - 2) +- (rl)
(SP) +- (SP) - 2

•

D7

reg. indirect

Addressing:

none

Flags:

D-15

o

o

3
10
reg. indirect
Z,S,P,CY,AC

All Mnemonics © 1976 Intel Corp.

XTHL
(Exchange stack top with Hand L)
(L) ~ «SP»
(H) ~ «SP) + I)
The content of the L register is exchanged with
the content of the memory location whose address is specified by the content of register SP.
The content of the H register is exchanged with
the content of the memory location whose address is one more than the content ofregister SP.

o

I

I

001

Cycles:
States:
Addressing:
Flags:

I

Cycles:

(Enable interrupt)
The interrupt system is enabled following the
execution of the next instruction.

~i

18

1

none

11

o

1
Cycles:

1

States:

4
none

DI

(Disable interrupts)
The interrupt system is disabled immediately
following the execution of the DI instruction.

1

Cycles:

1

States:
Fl.:

"
none

•

none

o

HLT
(Halt)
The processor is stopped. The registers and flags
are unaffected.

o

o

1

1

port

Cycles:

1

States:

7

Fl.:
Cycles:

3

States:

10

•

~._1__________1____0____0________~

o

5
register

o

Flags:

...

reg. indirect

(Input)
(A) ~ (data)
The data placed on the 8-bit bidirectional data
bus by the specified port is moved to register A.

Addressing:

none

•

IN port

1

direct

Flags:

5

o

Flags:

•

10

Addressing:

1

SPH L
(Move HL to SP)
(SP) ~ (H)(L)
The contents of registers Hand L (16 bits) are
moved to register SP.

States:
Addressing:

()

3

States:

Flags:

Cycles:

0
port

EI

o

1

direct

o

1

•

none

•
(No op)
No operation is performed. The registers and
flags are unaffected.

NOP

none

OUT port
(Output)
(data) ~ (A)
The content of register A is placed on the 8-bit
bidirectional data bus for transmission to the
specified port.

o

o

o

o
Cycles:

1

States:

4

Flags:

D-16

0

o

o

..

o

none

All Mnemonics © 1976 Intel Corp.

•

INSTRUCTION SET

•

Summary of Processor Instructions

MNEMONIC
MOY rI,r2
toIOY M,r
MOY r,M
HLT
MYI r
MYLM
INR r
OCR r
INR M
OCR M
ADDr
AD<' r
SUB r
SOB r

•
•

DESCRIPTION
Move rcgl\ICr 10 rt:~lslcr

U

Mo ... c JC,I(ISICr to memury
Mu'o'c mcmur~ 10 rC~lsh;1
Hal,
Muve immcdialc rcgislcr

0
0
0
0
0
0
0
0

Muve immedi;tlt: memor),

InL:'remenl rCi!,iSlcr
Denemenl r~,istcr
Increment memor)'

I)ecrcmcnl memory

Sublract rcglsler fwm A

U
I
I
I

SubtraCi register from A

I

Add rej!:islcr to A
Add rc~i~ler to A wllh ~arr)

ANI
XRI

wilh borrow
And rClfi~ter with A
l:ulusl . . c Or re~l~h:r \\llh A
Or rCi'liSICI Ydth A
Compare' relUster with A
Add memory 1\) A
Add memory to A with carry
Sublrat.:t memory from A
Subtrad memory from A
wllh borrow
And rnemury with A
Exdusl'o'c Or memury with A
Or memory with A
Compare memm), with A
Add immediate 10 A
Add immediate to A wilh
I.:arry
Subtract Immcdiale hom A
Subtra,t immediate hom A
with borrow
And immediate with A
Exclusi . . e Or Immediate wllh

ORI
CPI
RlC
RRC
RAL
RAR

Or immediate wllh A
Comp.He immediale with A
Rotate A left
Rotate A right
Rotate A I.::fl lhrouf:h carry
ROUte A right through

ANA r
XRA r
ORA r
CMPr
ADDM
ADC M
SUOM
SBB M
ANA M
XRAM
ORA M
CMPM
ADI
ACI
SUI
SOl

07 06 05 04 03 02 01 DO

I
I

I
I

I
I

I
I
1
I
I

I
I
I

I
I
I
I
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0
0
0
1
I

l>
I
l>
I
0
I
D
LJ
I

l>
I
U
I
LJ
I
0
LJ
I

I

I

0
0
0

0
0

0
0
l>
0
Il
0
D
D
0
0
0

S
S

I
I
I
I
I
I
I
I

S
S
I
I
I
I
0
0
0
0

S

I

S
S

0

S

0

I
I

I

S

S
S
S

I

U

S

S

I

0

0
I
I
0

0
J
0

S

I

S
I
I
I
I

S
S
S
I
I
I

I
I

0
I
0
I

0

0

0
0

I
I

I
I
I

0

0
I

I

0

I

I

()

I
0

0

0

U

0
I

S

I
I
I
I

I
I

I

I
I
I
I
I
I

CLOCK(21
CYCLES

10
10

RZ
RNZ
RP
RM
RPI
RPO
RST
IN
OUT
LXI"

4
4

LXILJ

4
4

lX11l

S

5

S
0

7
7
7
7

U

0
0
0
I
0
I
S
S
S
S
S
S
S
S
0
0

0
0
0
0

0
0
0
0

10

5

5

4
4
4
4

7
7

I
I

0
0

I

•
...

('l

CNZ
CP
eM
CPE
CPO
RET
RC
RNC
NOTES:

PUSH It

7
7
7
7
7
7

POP 8

I

I

I

I
I

I
I
0
0
0
0

I
I
0
0
0
0

I

I
I
I
I
I

I

I
I

I
I

0
0

7
7

0
I

I
I

I

I

0
0

I

0
0

7
7

I

I

I
0
0

I
U

0
I
0

I
I
I
I
I
I

I
I
I

0
0
I

7
7
4

I

I

4

I
I

I
I

4
4

0
I
0
I

0
0
0

I
I
I
I

I
0

U

I

0
0
0
0
0
I
I
I
I

0
0
I

I
I

10
10
10
10
10
10
10
10
I'D
17
11/17
11/17
11/17
11/17
11/17
11/17
11/17
11;17
10
5/ II
5/ II

0
0

0
I
I

I

0
I

I

I
I
I
I
I
I
I
I
I
I

I
I
I
I

I
I
I
I
I

I
I

I
I
I

I
I
I
I

I
I
I
I
I
I
I

0
0
0
0
0
I
I

I
I
U

0
0
0
0
I

I

0
I

I
0
0
I

I
0
0
0
I
I

0
0
I
I

(J

0
0
0
I

0

I

I

I
0

0
I
I
0
I
I
0

I

0
I
I
0

U

I

I
I
0

0
0

I

I
I
I
I
0
0
0
0
0
0
0
0
0
0
0
0

U

0
0
0

0
0
0
I

0
0
0
0
0
0
0
0
I

0
0

Return un no lew
f{..:turn un pusltive
Return un minus
Return on parity even
RC'lurn on pJrily odd

Reslarl

Inpul
Output

Luad immediJte register

Pair B & ('
Load Immediale rCJ!,istcr
Pm D & E
Load immcditttc rc~istcr
Pair 11 & L
llliJd immt:diatc stack pOlnler
Push rc~l~tcr Pair B &. C on

°5

CLOCK I21
04 D3 D2 Dl DO CYCLES'

I
I
I
I
I
I
I
I
I
0

I
I
I
I
I
I
I
I
I
0

0
0
I
I
I
I
A
0
0
0

0
0
I
I
0
0
A
I
I

I
0
0
I
I
0
A
I
0

0

0

0

0

I

0

0

I

0
I

0
I

I

I

0
0
0
0
0
0
I
I
I
0

0
0
0
0
0
0
I
I
I

U

0
0
0
0
0
0
I
0
0
0

I

5/11
5/11
5/11
5/11
5/11
5/11
II
10
10
10

0

0

0

I

10

0

0

0

0

I

10

I
0

I
0

0
0

0
I

0
0

I
I

10
II

Push register P;,iU () & E un
slal:k
Push rqmter P .tir H & L un

0

I

0

I

0

I

II

I

I

I

0

0

I

0

I

II

I

I

I

I

0

I

0

I

II

I

I

0

0

0

0

0

I

10

I

I

0

I

0

0

0

I

10

0

0

I

10

~Ia(;'k

PUSIl PSI\'

Larry

Jump um.:onditlonal
Jump on f,;arry
Jump on no carry
Jump on l(:ro
Jump on no lew
Jump on positl ... e
Jump on minus
Jump on parity even
Jump on parit)' odd
CaJi unconditional
Calion carry
CaU on no carry
Calion zero
Calion no zero
Call un poslli\'e
Call on minus
Call on pauty e...en
Call on pallty odd
Return
Re~urn on carry
Return on no t.:arry

PUSH D

J

0
I

Relum on UfO

07 06

slat:k

7

A

JMP
IC
JNC
JZ
JNZ
JP
JM
JPE
IPO
CALL
CC
CNC

LXI SP
PUSH 8

POP U
POP H
POP PSW

I
I

DESCRIPTION

MNEMONIC

STA
LLJA
XCHG
XTHL
SPHL
PClll
CAD B
LJADU
DALlH
DAO SP
STAX B
STAX D
LDAX B
LOAX 0
INX 0
INX D
INX H
INX SP
D<'X B
OCX 0
lJ{'X H
DCX SP
CMA
STC
CMC
DAA
SHLO
LHLO
U
01
NOP

Push A and 1"I<.Itls
on stack
Pop rCttlSler pair 8 &. (' off
slad
Pop reglstcr pair D & E oil
stack
Pop re~iSlcr pair H & L off
stack
Pop A and !-"lags
off stack
Slore A dire"
Load A din~ct
lx,hango 0 & E, H & L
Registers
Exchange top of stock H &. L
H & L to stack pointer
H & L to prog:ram counter
Add B & C 10 H & L
Add D & E H & l
Add H & L 11 & l
Add stack pointer 10 H &. l
S tore A indirect
Store A indircd
lOild A indued
Load A indarel.:t
Im:remenl B & (' retlislers
(nnement D &. E registers
Increment H & L registers
In"ement suck pOinter
De..:remenl B & C
Denement [) &. E
Decrtmenl H &. L
Decrement s~a-.:k pointer
Complement A
Sel .."arry
Complement carry
Dcdm .. t adjust A
Siure H &. l dire":l
load H & l dlft<'
Enable Interrupts
Disable lRlerrupt
No-operation

'0
'0

I

I

I

0

0

I

I

I

I

0

0

0

I

10

0
0
I

0
0
I

I
I
I

I
I
0

0
I
I

0
0
0

I
I

0
0
I

13

I
I

I
I
I
0
0
0
0
0
0
0
0
0

I
I
I
0
0
I
I
0

I
0
0
0
0
0
0

0
I

0
I
I
I
I
I
I
0
0
I
I
0
0
0
0
I
I
I
I
I
0

0
0
0
0

U

0
I
0
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
0
I
I
0
0
0
I
I
0

I

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
I
I
0

0
0
0

0

0

0
0
0
0
0
0
0
U

0
0
0
I
I
0

I

0
0
I
I

I
I
I
I
I
I
I
I

0

I

0
0
I
I
0
0

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I
I
I
I
0
0
0
0
0

I

I
I
I
I
I
I
I
0
0
0
0
I
I
I
I

I
I
I
I
I
I
I
I
0
0
I
I
0

13
4

18
5
5
10
10
10
10

7
7
7
7
5
5
5
5
5
5
5
5
4
4
4
4
16

16
4
4

4

I. OOD or SSS - 000 B - 001 ('" 0100 - 011 E - 100 H - 101 l - 110 Memory - III A
2. Two pOSSible I.:ycle times. (5/11) mdicate instruction cycles dependent on condition nags.

•

All Mnemonics

D-17

© 1976 Intel Corp.

•
•
•
•
•

•

•

APPENDIX E

SBC 80P MONITOR PROGRAM LISTING

•
•
•
•
E-l

sese MACRO ASSEMBLER, VER 2.4
ERRORS
se/le MONITOR, VERSION 1.1, 1 NOVEMBER 1976

I!.I

PAGE 1

TITLE '81!.1/11!.1 MONITOR, VERSION 1.1, 1 NOVEMBER 1976'

,
;***********************************************************************
;***********************************************************************
80/10 MONITOR
MS0/Hl
VERSION 1.1
1 NOVEMBER 1976
;

,.***********************************************************************
,.***********************************************************************
(C) 1976 INTEL CORPORATION. ALL RIGHTS RESERVED. NO PART OF THIS
PROGRAM OR PUBLICATION MAY BE REPRODUCED, TRANSMITTED, TRANSCRIBED,
STORED IN A RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR
COMPUTER LANGUAGE, IN ANY FORM OR BY ANY MEANS, ELECTRONIC,
MECHANICAL, MAGNETIC, OPTICAL, CHEMICAL, MANUAL OR OTHERWISE,
WITHOUT THE PRIOR WRITTEN PERMISSION OF INTEL CORPORATION,
3065 BOWERS AVENUE, SANTA CLARA, CALIFORNIA 95051.
;

,.***********************************************************************
,.***********************************************************************
ABSTRACT
THIS PROGRAM RUNS ON THE SBC 80/10 BOARD AND IS DESIGNED TO PROVIDE
THE USER WITH A MINIMAL MONITOR. BY USING THIS PROGRAM,
THE USER CAN EXAMINE AND CHANGE MEMORY OR CPU REGISTERS, LOAD
A PROGRAM (IN ABSOLUTE HEX) INTO RAM, AND EXECUTE INSTRUCTIONS
ALREADY IN HEMORY. THE ~10NITOR ALSO PROVIDES THE USER WITH
ROUTINES FOR PERFORMING CONSOLE I/O AND PAPER TAPE I/O.
PROGRAM ORGANIZATION
THE LISTING IS ORGANIZED IN THE FOLLOWING WAY. FIRST THE BASIC
MONITOR FUNCTIONS TOGETHER WITH THE CONSOLE I/O ARE LOCATED IN THE
FIRST lK OF ROM FOLLOWED BY THE PAPER TAPE FUNCTIONS AND I/O IN THE
SECOND lK OF Rml. WITHIN THE FIRST ROM IS CONTAINED THE COMMAND
RECOGNIZER, WHICH IS THE HIGHEST LEVEL ROUTINE IN THE PROGRAM.
NEXT THE ROUTINES TO IMPLEMENT THE VARIOUS COMMANDS. FINALLY,
THE UTILITY ROUTINES WHICH ACTUALLY DO THE DIRTY WORK. WITHIN
EACH SECTION, THE ROUTINES ARE ORGANIZED IN ALPHABETICAL
ORDER, BY ENTRY POINT OF THE ROUTINE. THE SECOND ROM IS ORGANIZED
IN THE SAME MANNER AS THE FIRST WITH THE ROUTINES WHICH IMPLIMENT
THE COMMANDS FOLLOWED BY THE UTILITY ROUTINES WHICH ACTUALLY DO THE

•

II

•

•

•

~.

c

•

•

t

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

Cil

PAGE 2

•

•

MORE DETAILED OPERATIONS.
THE PROGRAM HAS BEEN PARTITIONED IN SUCH A MANNER THAT THE SECOND
ROM NEED NOT BE PLUGGED INTO THE BOARD IF ONLY THE BASIC MONITOR
FUNCTIONS ARE REQUIRED. HOWEVER IF THE PAPER TAPE FUCTIONS ARE DESIRED
BOTH ROMS ARE REQUIRED.
THIS PROGRAM EXPECTS TO RUN IN THE FIRST 2K OF ADDRESS SPACE.
IF, FOR SONE REASON, THE PROGRAM IS RE-ORG'ED, CARE SHOULD
BE TAKEN TO MAKE SURE THAT THE TRANSFER INSTRUCTIONS FOR RST 1
AND RST 7 ARE ADJUSTED APPROPRIATELY.
THE PROGRAM ALSO EXPECTS THAT RAM LOCATIONS 3C00H TO 3C3FH,
INCLUSIVE, ARE RESERVED FOR THE PROGRAM'S OWN USE. THESE
LOCATIONS MAY BE ALTERED, HOWEVER, BY CHANGING THE EQU'ED
SYMBOL "DATA" AS DESIRED.
LIST OF FUNCTIONS
=========

********
1 ST ROM

********
GETCM
DCMD
GCMD
ICMD
MCMD
RCMD
SCMD
WCMD
XCMD
ADRD
ADROUT
BREAK
CI
CNVBN
CO
CROUT
ECHO
ERROR
FRET
GETCH
GETHX
GETNM
HILO

~

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

" PAGE 3

INUST
NMOUT
PRVAL
REGDS
RGADR
RSTTF
SRET
STHF0
STHLF
VALDG
VALDL

********
2 ND ROM

********
RCMD
WCMD
BYTE
DELAY
LEAD
PADR
PBYTE
PEOF
PEOL
PO
RI
RICH
0000

ORG

08

;

;*****************************************************************
MONITOR EQUATES

,

,.*****************************************************************
;

raUB
3C3D
03FA
0025
o filED
00EC
''''EC

•

J3RCHR
BRLOC
ERTAB
CMD
CNCTL
CNIN
CNOUT

.

.

EQU
EQU
EQU
EQU
EQU
EQU
EQU

IBH
3C3DH
3FAH
025H
filEDH
0ECH
"ECH

•

CODE FOR BREAK CHARACTER (ESCAPE)
LOCATION OF USER BRANCH INSTRUCTION IN RAM
LOCATION OF START OF BRANCH TABLE IN ROM
COMMAND INSTRUCTION FOR USART INITIALIZATION
CONSOLE (USART) CONTROL PORT
CONSOLE INPUT PORT
CONSOLE OUTPUT PORT

•

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c

•

,

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
CONST EOU
CR
EOU
DATA EQU
ESC
EOU
IICHAR EQU
INVRT EQU
LF
EOU
; LSGNON
MODE EQU
;I1STAK
; NOlDS
NEWLN EQU
PRTYO EQU
REGS EQU
RBR
EQU
RSTU EOU
;RTABS
TERM EQU
TROY EQU
UPPER EQU
TXBE EOU
TTYADV
ONEMS EQU

""ED
0000
3C00
{"lIB
000F
OOFF
"00A
00CF
000F
007F
3C2E
0002
10038
001B
0001
00FF
0004
O(l27
"083

" PAGE 4

•

•

CONSOLE STATUS INPUT PORT
0EDH
ODH
CODE FOR CARRIAGE RETURN
START OF MONITOR RAM USAGE
15*1024
ll3H
CODE FOR ESCAPE CHARACTER
MASK TO SELECT LOWER HEX CHAR FROM BYTE
0FH
MASK TO INVERT HALF BYTE FLAG
0FFH
(lAH
CODE FOR LINE FEED
EQU
i LENGTH OF SIGNON MESSAGE - DEFINED LATER
0CFH
; MODE SET FOR USART INITIALIZATION
EQU
i START OF MONITOR STACK -.DEFINED LATER
; NUMBER OF VALID COM~lANDS
EQU
OFH
i MASK FOR CHECKING MEMORY ADDR DISPLAY
07FH
; MASK TO CLEAR PARITY BIT FROM CONSOLE CHAR
DATA+64-18
; START OF REGISTER SAVE AREA
; MASK TO TEST RECEIVER STATUS
2
; TRANSFER LOCATION FOR RST 7 INSTRUCTION
38H
; SIZE OF ENTRY IN RTAB TABLE
EQU
IBH
; CODE FOR ICMO TERMINATING CHARACTER (ESCAPE)
; MASK TO TEST TRANSMITTER STATUS
1
OFFH
: DENOTES UPPER HALF OF BYTE IN ICMD
04H
; USART TRANSMITTER BUFFER EMPTY
; TTY READER ADVANCE COMMAND
EQU
27H
131
; 1 MILLISECOND CONSTANT

tj

;

n

:*****************************************************************
MONITOR

~lACROS

;

,.*****************************************************************
1
1

TRUE

MACRO
JC
ENDM

WHERE
WHERE

BRANCH IF FUNCTION RETURNS TRUE (SUCCESS)

1
1

FALSE MACRO
JNC
ENDM

WHERE
WHERE

BRANCH IF FUNCTION RETURNS FALSE (FAILURE)

,
,.*****************************************************************

.,

USART INITIALIZATION CODE

;********************************~********************************

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMOER 1976

o PAGE 5

THE USART IS ASSUMED TO COME UP IN THE RESET POSITION (THIS
FUNCTION IS TAKEN CARE OF SY THE HARm'lARE). TIlE US ART WILL
BE INITIALIZED IN THE SAME WAY FOR EITHER A TTY OR CRT
INTERFACE. THE FOLLOWING PARAMETERS ARE USED:
MODE INSTRUCTION

====

===========-

2 STOP BITS
PARITY DISABLED
8 BIT CHARACTERS
BAUD RATE FACTOR OF 64
COMMAND INSTRUCTION
NO HUNT MODE
NOT(RTS) FORCED TO 0
RECEIVE ENABLED
TRANSMIT ENABLED
0000
0002
0004
0007

3E~P. 'C£
D3ED
C3B202
00

MVI
OUT
JMP
NOP

A,MODE
CNCTL
INUST

OUTPUT MODE SET ~O USART
BRANCH TO COMPLETE USART INITIALIZATION
FILLER

,
,.*****************************************************************
RESTART ENTRY POINT

,
,.*****************************************************************
0008
0008
000B
000C
"B0F
0elt)
0013
0014
0017
0018
0US

~

GO:
22343C
E1
22363C
FS
210200
39
22383C
Fl
31343C
C3B101

,

SHLD
POP
SHLD
PUSH
LXI
DAD
SHLD
POP
LXI
JMP

LSAVE
SAVE HL REGISTERS
GET TOP OF STACK ENTRY
H
PSAVE
ASSUME THIS IS LAST P COUNTER
SAVE A,F/F'S
PSW
H,2
SET HL TO 2 SO THAT STACK POINTER SAVED CORRECTLY
GET STACK POINTER VALUE
SP
SSAVE
SAVE USER'S STACK POINTER
PSW
: RESTORE A,F/F'S
SP,ASAVE+l
: NEW VALUE FOR STACK POINTER
ADROUT

,.************************************************************

•

.

,

•

•

•

•

•

,

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

° PAGE

6

•

•

PRINT SIGNON MESSAGE
;

,.************************************************************

.,
001E
001E
0021
0023
0023
"024
0027
liHl28
fiHl29

SOMSG:
219503
0611

LXI
~lVI

H,SGNON ; GET ADDRESS OF SIGNON MESSAGE
B,LSGNON
; COUNTER FOR CHARACTERS IN MESSAGE

MSGL:
4E
CDE81H
23
05
C22300

MOV
CALL
INX
OCR
JNZ

C,M
CO
H

FETCH NEXT CHAR TO C REG
SEND IT TO THE CONSOLE
POINT TO NEXT CHARACTER
DECREMENT BYTE COUNTER
RETURN FOR NEXT CHARACTER

B

MSGL

i

,.*****************************************************************
COMMAND RECOGNIZING ROUTINE

,

,.*****************************************************************
FUNCTION: GETCM
INPUTS: NONE
OUTPUTS: NONE
CALLS: GETCH,ECHO,ERROR
DESTROYS: A,D,C,H,L,F/F'S
DESCRIPTION: GETCM RECEIVES AN INPUT CHARACTER FROM THE USER
AND ATTEMPTS TO LOCATE THIS CHARACTER IN ITS COMMAND
CHARACTER TABLE. IF SUCCESSFUL, THE ROUTINE
CORRESPONDING TO THIS CHARACTER IS SELECTED FROM
A TABLE OF COMI1AND ROUTINE ADDRESSES, AND CONTROL
IS TRANSFERRED TO THIS ROUTINE. IF THE CHARACTER
DOES NOT NATCH ANY ENTRIES, CONTROL IS PASSED TO
THE ERROR HANDLER.
i

GETCM:

002C
B02C

312E3C

LXI

SP,MSTAK

iHl2F
0031
0034

0E2E
CDF901
C33cra0

MVI
CALL
JMP

CI

ECHO
GTC03

0038
0038
003B

C33D3C
06

ORG
Jl>lP
NOP

RSTU
USRBR

;

iHl3C

GTCra3:

I", I

; ALWAYS WANT TO RESET STACK PTR TO MONITOR
/STARTING VALUE SO ROUTINES NEEDN'T CLEAN UP
PROMPT CHARACTER TO C
SEND PROMPT CHARACTER TO USER TERMINAL
WANT TO LEAVE ROOM FOR RST BRANCH
ORG TO RST TRANSFER LOCATION
JUMP TO USER BRANCH LOCATION
FILLER

•

•

8~8~

MACRO ASSEMBLER, VER 2.4
ERRORS
MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o PAGE 7

8~/10

~03C

003F
0042
0043
0046
0049
0049
004A
004D
004E
004F
0052
0055
0055
0058
0059
005A
0058
005C
005D
005E

CD2002
CDF91'1l
79
010800
21B803

CALL
CALL
MOV
LXI
LXI

GETCH
ECaO
A,C
B,NCMDS
H,CTAB

GET COMMAND CHARACTER TO A
ECHO CHARAC~ER TO USER
PUT COMMAND CHARACTER INTO ACCUMULATOR
C CONTAINS LOOP AND INDEX COUNT
HL POINTS IN70 COMMAND TABLE

CMP
JZ
INX
DCR
JNZ
JMP

M

COMPARE TABLE ENTRY AND CHARACTER
BRANCH IF EQUAL - COMMAND RECOGNIZED
ELSE, INCREMENT TABLE POINTER
DECREMENT LOOP COUNT
BRANCH IF NOT AT TABLE END
ELSE, COMMAND CHARACTER IS ILLEGAL

21A603

LXI

H,CADR

09
09
7E
23
66
6F
E9

DAD
DAD
MOV
INX
MOV
MOV
PCHL

GTC05:
BE
CA5500
23

OD
C24900
C31202

GTCHl
H

C

GTC05
ERROR

GTC10:
B
B

A,M
H

H,M
L,A

IF GOOD COMMAND, LOAD ADDRESS OF TABLE
/OF COMMAND ROUTINE ADDRESSES
ADD WHAT IS LEFT OF LOOP COUNT
ADD AGAIN - EACH ENTRY IN CADR IS 2 BYTES LONG
GET LSP OF ADDRESS OF TABLE ENTRY TO A
POINT TO NEXT BYTE IN TABLE
GET MSP OF ADDRESS OF TABLE ENTRY TO H
PUT LSP OF ADDRESS OF TABLE ENTRY INTO L
NEXT INSTRUCTION COMES FROM COMMAND ROUTINE

;

;**********************************************************************
COMMAND IMPLEMENTING ROUTINES

,
;*******************************~**************************************

FUNCTION: DOlO
INPUTS: NONE
OUTPUTS:· NONE
CALLS: ECHO,NMOUT,HILO,GETCM,CROUT,GETNM
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: DCMD IMPLEMENTS THE DISPLAY MEMORY (D) COMMAND
;

005F
005F
0061
0064
0065
0066
0066
0069
006C
006C
006E

DCMD:
0E02
CD5B02
Dl
El

MVI
CALL
POP
POP

C,2
GETNM
D
H

GET TWO NUMBERS FROM INPUT STREAM

CALL
CALL

CROUT
ADRD

ECHO CARRIAGE RETURN/LINE FEED
DISPLAY ADDRESS

MVI
CALL

C,
ECHO

ENDING ADDRESS TO DE
STARTING ADDRESS TO HL

DCM05:
CDF301
CDAB01
DCM10:
0E20
CDF91'1l

•

•

, ,

•

USE BLANK AS SEPARATOR

•

•

•

..

•

•

,

•

380 MACRO ASSEMBLER, VER 2.4
ERRORS
80/13 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
3071
01372
13075

7E
CDC202
CDC261

1
0378 1 DA1702
337B
CDA002
1
007E 1 DA1732
3381
23
3382
7D
130B3
E60F

31385
0388

+
+
+

+

C26C00
C36603

MOV
CALL
CALL
TRUE
JC
CALL

A,M
NMOUT
BREAK
EXIT
EXIT
HILO

TRUE
JC
INX
MOV
ANI

EXIT
EXIT
A,L
NEWLN

JNZ
JMP

DCM10
DCM05

H

•

•
3 PAGE 8

GET CONTENTS OF NEXT MEMORY LOCATION
DISPLAY CONTENTS
SEE IF USER WANTS OUT
IF SO, BRANCH TO EXIT
SEE IF ADDRESS OF DISPLAYED LOCATION IS
/GREATER THAN OR EQUAL TO ENDING ADDRESS
EXIT IF NO MORE TO DISPLAY
IF MORE TO GO, POINT TO NEXT LOC TO DISPLAY
GET LOW ORDER BITS OF NEW ADDRESS
SEE IF LAST HEX DIGIT OF ADDRESS DENOTES
/START OF NEW LINE
NO - NOT AT END OF LINE
YES - START NEW LINE WITH ADDRESS

,
,.*****************************************************************
FUNCTION: GCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: ERROR,GETHX,RSTTF
DESTROYS: A,n,C,D,E,H,L,F/F'S
DESCRIPTION: GCMD IMPLEMENTS THE BEGIN EXECUTION (G) COMMAND.
00BB
308B

CD2702
1
U8E 1 D2A333
31391
7A
FE3D
0"92
0094
C21232
3097
21363C
009A
71
039B
23
309C
70
0090
C3A633
00A0
30A0
7A
00A1
FE3D
C21202
33A3
00A6
C32703
00A6

~

GCMD:
CALL
FALSE
JNC

+
+

MOV

GETHX
GCM35
GCM35
A,D

GET ADDRESS (IF PRESENT) FROM INPUT STREAM
BRANCH IF NO NUMBER PRESENT
ELSE, GET TERMINATOR
SEE IF CARRIAGE RETURN
ERROR IF NOT PROPERLY TERMINATED
WANT NUMBER TO REPLACE SAVE PGM COUNTER

CPI
JNZ
LXI
MOV
INX

eR

MOV

JMP

M,B
GCM13

MOV
CPI
JNZ

A,D
CR
ERROR

IF NO STARTING ADDRESS, MAKE SURE THAT
/CARRIAGE RETURN TERMINATED COMMAND
ERROR IF NOT

JMP

RSTTF

RESTORE REGISTERS AND BEGIN EXECUTION

ERROR
H,PSAVE
H,C

ij

GCM05:

GCM10:

;

,.*****************************************************************

•

•

•

18~

MACRO ASSEMBLER, VER 2.4
ERRORS = 9 PAGE 9
MONITOR, VERSION 1.1, 1 NOVEMBER 1976

8~/19

FUNCTION: ICMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: ERROR,ECHO,GETCH,VALDL,VALDG,CNVBN,STHLF,GETNM,CROUT
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: ICMD IMPLEMENTS THE INSERT CODE INTO MEMORY (I) COMMAND.
00A9
00A9
0MB
0ME
00B0
00B3
0gB4
OOD4
0121B7
00BA
00BB
00BO
00C0

:

ICMD:
0EIn
CD5B02
3EFF
323A3C
01

CALL
MVI
STA
POP

C,l
GETNM
A,UPPER
TEMP
0

CALL
CALL
MOV
CPI
JZ
CALL
TRUE
JC
CALL
FALSE
JNC
CALL
MOV
CALL
LOA
ORA
JNZ
INX

GETCH
ECHO
A,C
TERM
ICM25
VALDL
ICM05
ICM05
VALDG
ICM20
ICM20
CNVBN
C,A
STHLF
TEMP
A
ICM10
D

GET A CHARACTER FROM INPUT STREAM
ECHO IT
PUT CHARACTER BACK INTO A
SEE IF CHARACTER IS A TERMINATING CHARACTER
IF SO, ALL DONE ENTERING CHARACTERS
ELSE, SEE IF VALID DELIMITER
IF SO SIMPLY IGNORE THIS CHARACTER

XRI
STA
JMP

INVRT
TEMP
ICM05

TOGGLE STATE OF FLAG
PUT NEW VALUE OF FLAG BACK
PROCESS NEXT DIGIT

CALL
JMP

STHFI2I
ERROR

ILLEGAL CHARACTER
MAKE SURE ENTIRE BYTE FILLED THEN ERROR

CALL
JMP

STHF0
EXIT

HERE FOR ESCAPE CHARACTER - INPUT IS DONE

~1VI

GET SINGLE NUMBER FROM INPUT STREAM
TEMP WILL HOLD THE UPPER/LOWER HALF BYTE FLAG
ADDRESS OF START TO DE

ICMI2I5:
CD2002
CDF901
79
FEIB
CAE900
CD8203

1
0aC3 1 DAB4a0
00C6
CD6733
1
00C9 1 D2E30121
00ce
CDDF01
00CF
4F
0000
CD4803
0003
3A3A3C
0006
B7
~HJD7
C20B00
000A
13
000B
12100B
EEFF
0000
323A3C
00E0
C3B4121e
30E3
e0E3
CD3003
00E6
C3121212
00E9
03E9
CD3D03
C31702
""Ee

+
+
+
+

ELSE, CHECK TO SEE IF VALID HEX DIGIT
IF NOT, BRANCH TO HANDLE ERROR CONDITION
CONVERT DIGIT TO BINARY
MOVE RF.SIJLT TO C
STORE IN APPROPRIATE HALF WORD
GET HALF BYTE FLAG
SET F/F'S
BRANCH IF FLAG SET FOR UPPER
IF LOWER, INC ADDRESS OF BYTE TO STORE IN

ICM10:

ICM20:
ICM25:

.,

,.*****************************************************************
FUNCTION: MCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: GETCM,HILO,GETNM

•

•

•

•

•

•

';

•

•

•

•

\

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
aO/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o PAGE 10

•

•

DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: MCMD IMPLEMENTS THE MOVE DATA IN MEMORY (M) COMMAND.
1

fleEF
00EF
30F1
OfJF4
OOF5
0(lF6
00F7
~H)F7

0"Fa
'HJF9
0"FA
I:HlFB
00FC
00FD
00FE
00FF
0100
0101
0104
0105
0106

MCMD:
(lE03
CD5832
C1
El
Dl

MVI
CALL
POP
POP
POP

C,3
GETNM
B
H

PUSH
MOV
MOV
IIOV
MOV
MOV
MOV
INX
MOV
ORA
JZ
INX
POP
CALL
FALSE
JNC
JMP

H
H,D
L,E
A,M
H/B
L,C
M,A
B
A,B
C
GETCM
D
H
HILO
GETCM
GETCI-:l
MCMOs

0

GET 3 NUMBERS FROM INPUT STREAM
DESTINATION ADDRESS TO BC
ENDING ADDRESS TO HL
STARTING ADDRESS TO DE

MCM05:
E5
62
613
7E
60
69
77
03
78
B1
CA2C00
13
El
CDAC02

1
0109 1 D22C00
010C
C3F7D0

+
+

SAVE ENDING ADDRESS
SOURCE ADDRESS TO HL
GET SOURCE BYTE
DESTINATION ADDRESS TO HL
BYTE TO DESTINATION
INCREMENT DESTINATION ADDRESS

~lOVE

TEST FOR DESTINATION ADDRESS OVERFLOW
IF SO, CAN TERMINATE COMMAND
INCREMENT SOURCE ADDRESS
ELSE, GET BACK ENDING ADDRESS
SEE IF ENDING ADDR>=SOURCE ADDR
IF NOT, COMMAND IS DONE
NOVE ANOTHER BYTE

I

,.******************************************************************
FUNCTION: SCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: GETHX,GETCM,NMOUT,ECHO
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: SCMD IMPLEMENTS THE SUBSTITUTE INTO MEMORY (5) COMMAND.
1

013F
0tOF
0112
0113
0114
0114
0115
0117
011A
flllC
allF
011F

SCMD:
CD2702
C5
El

CALL
PUSH
POP

GETHX
B
H

GET 11. NUMBER, IF PRESENT, FROM INPUT

MOV
CPI
JZ
CPI
JNZ

A,D,

GETCM

GET TERMINATOR
SEE IF SPACE
YES - CONTINUE PROCESSING
ELSE, SEE IF COMMA
NO - TERMINATE COMMAND

MOV

A,M

GET CONTENTS OF SPECIFIED LOCATION TO A

GET NUMBER TO HL - DENOTES MEMORY LOCATION

SCM0s:
7A
FE2"
CA1F0l
FE2C
C22C00

,

SCM10
, ,

,

SCM1":
7E

f

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0120
0123
0125
0128

COC202
0E2D
CDF901
CD2702

1
012B 1 D22FU
012E
7J
0l2F
012F
23
0130
C31401

+
+

=0

PAGE 11

CALL
MVI
CALL
CALL
FALSE
JNC
MOV

NMOUT
C, '-'
ECHO
GETHX
SCMIS
SCMIS
M,C

DISPLAY CONTENTS ON CONSOLE
USE DASH FOR SEPARATOR
GET NEW VALUE FOR MEMORY LOCATION, IF ANY
IF NO VALUE PRESENT, BRANCH

INX
JMP

H

INCREMENT ADDRESS OF MEMORY LOCATION TO VIEW

ELSE, STORE LOWER 8 BITS OF NUMBER ENTERED

SCMIS:
SCM0S

;

,.*****************************************************************
FUNCTION: XCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: GETCH,ECHO,REGDS,GETCM,ERROR,RGADR,NMOUT,CROUT,GETHX
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: XCMD IMPLEMENTS THE REGISTER EXAMINE AND CHANGE (Xl
COMMAND.

'.

;

0133
0133
0136
0139
013A
0l3C
013F
0142
0145
0145
0146
13149

014A
0l4B
014D
0150
0151
0154
0154
0157
0159
DISC
BISE
0161
0161
0162
0163
0166

CD2002
CDF901
79
FE0D
C245Bl
CDDFfl2
C32C00

XCMD:

CALL
CALL
MOV
CPI
JNZ
CALL
JMP

GETCH
ECHO
A,C
CR
XCMB5
REGDS
GETCM

GET REGISTER IDENTIFIER
ECHO IT

MOV
CALL
PUSH
POP

C,A
RGADR

GET REGISTER IDENTIFIER TO C
CONVERT IDENTIFIER INTO RTAB TABLE ADOR

B
H

PUT POINTER TO REGISTER ENTRY INTO HL

BRANCH IF NOT CARRIACE RETURN
ELSE, DISPLAY REGISTER CONTENTS
THEN TERMINATE COMMAND

XCM05:
4F
CD1003
C5
E1
0E20
CDF901
79
323A3C

C,' ,
ECHO
A,C
TEMP

~IVI

CALL
~IOV

STA

ECHO SPACE TO USER
PUT SPACE INTO TEMP AS DELIMITER

XCM10:
3A3A3C
FE20
CA6101
FE2C
C22ClHl

LDA
CPI
JZ
CPI
JNZ

TEMP
XCM15

,

GETCM

1.

GET TER~HNATOR
SEE IF A BLANK
YES - GO CHECK POINTER INTO TABLE
NO - SEE IF COMMA
NO - MUST BE CARRIAGE RETURN TO END COMMAND

XCM15:
MOV
ORA
JZ
PUSH

7E
87
CA1702
E5

•

It

A,M
A

EXIT
H

,

SET FIF'S
BRANCH IF·AT END OF TABLE
PUT POINTER ON STACK

•

•

•

.'

•

•

.

.

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0167
0168
016A
016B
016C
016D
016E
016F
0170
U7l
0174
0175
0176
0177
017A
017B
017C
017F
017F
0181
0184

5E
163C
23
46
D5
D5

MOV
MVI
INX
MOV
PUSH
PUSH
POP
PUSH
MOV
CALL
POP
PUSH
ORA
JZ
DCX
MOV
CALL

El
C5
7E
CDC202

Fl
FS
B7
CA7FOI
2B
7E
.CDC202

•

o PAGE 12

E,M
D,DATA SHR 8

~

H

~

FETCH ADDRESS OF SAVE LOCATION FROM
/TABLE
FETCH LENGTH FLAG FROM TABLE
SAVE ADDRESS OF SAVE LOCATION

B,M
D
D
H
B

H

MOVE ADDRESS TO HL
SAVE LENGTH FLAG
GET 8 BITS OF REGISTER FROM SAVE LOCATION
DISPLAY IT
GET BACK LENGTH FLAG
SAVE IT AGAIN
SET F/F'S
IF 8 BIT REGISTER, NOTHING MORE TO DISPLAY
ELSE, FOR 16 BIT REGISTER, GET LOWER 8 BITS

A,M
NMOUT

DISPLAY THEM

A,M
NMOUT
PSI-l

PSW
A

XCM20

XCM20:

MVI

OE2D
CDF901
CD2702

1
0187 1 D29FOI
018A
7A
018B
323A3C
018E
Fl

OlaF

El

0190
0191
0194
0195
0196
0196
0197
0197
019A
019B
019C
019F
019F
tnAO
01A3
0lM
mAS

B7
CA9601
70
2B

+
+

C, ' - '

CALL
CALL
FALSE
JNC

ECHO
GETHX
XCM30

MOV

A,D
TEMP
PSW

STA
POP
POP
ORA
JZ

USE DASH AS SEPARATOR
SEE IF THERE IS A VALUE TO PUT INTO REGISTER
NO - GO CHECK FOR NEXT REGISTER

xcrHO

t-10V

XCM25
M,B

DCX

H

ELSE, SAVE THE TERMINATOR FOR NOW
GET BACK LENGTH FLAG
PUT ADDRESS OF SAVE LOCATION INTO HL
SET F/F'S
IF 8 BIT REGISTER, BRANCH
SAVE UPPER 8 BITS
POINT TO SAVE LOCATION FOR LOWER 8 BITS

MOV

M,C

STORE ALL OF 8 BIT OR LOWER 1/2 OF 16 BIT REG

LXI
POP
DAD
JMP

D,RTABS
H
D

SIZE OF ENTRY IN RTAB T~BLE
POINTER INTO REGISTER TABLE RTAB
ADD ENTRY SIZE TO POINTER
DO NEXT REGISTER

H
A

XCl>!25 :

71
XCM27 :.
ll0300

El
19
C35401

XCMl"

XCM30:
7A
323A3C

~1OV

STA
POP

Dl
D1
C39701

A,D
TEMP

POP

D
D

JMP

XCM27

GET'TERMINATOR
SAVE IN MEMORY
CLEAR STACK OF LENGTH FLAG AND ADDRESS
lOF SAVE LOCATION
GO INCREMENT REGISTER TABLE POINTER

;

,.*****************************************************************
UTILITY ROUTINES

«

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

=0

PAGE 13

i

,.*****************************************************************
,
,.*****************************************************************
FUNCTION ADRD
INPUTS: HL - ADDRESS TO BE DISPLAYED
OUTPUTS: NONE
CALLS: NMOUT
DESTROYS: A
DESCRIPTION: ADRD OUTPUTS TO THE CONSOLE THE ADDRESS
CONTAINED IN THE H,L REGISTERS.
01A8
01A8
01A9
01AC
01AD
01B0

ADRD:
7C
CDC202
7D
CDC202
C9

A,H
NNOUT
A,L
NMOUT

MOV

CALL
MOV
CALL
RET

DISPLAY FIRST HALF OF ADDRESS
DISPLAY SECOND HALF OF ADDRESS
RETURN TO CALLING ROUTINE

;

,.*****************************************************************
FUNCTION ADROUT
INPUTS: USER REGISTERS ON THE STACK
OUTPUTS: NOTHING
CALLS: ECHO,ADRD
DESTROYS; A,B,C,D,E,H,L,F/F'S
DESCRIPTION: ADROUT SAVES THE USER REGISTERS AND OUTPUTS TO THE
CONSOLE THE USER P COUNTER AFTER A RST 1 INSTRUCTION.

01Bl
01Bl
01B2
01B3
01B4
01B6
01B9
"lBC
01BF

F5
C5
D5
0E23
CDF9lH
21\363C
CDA801
C31702

ADROUT:
PUSH
PUSH
PUSH
11VI
CALL
LHLD
CALL
JMP

PSW
B

D
C, , It '
ECHO
PSI\VE
ADRD
EXIT

SAVE A AND FLAGS
SAVE BAND C
SAVE D AND E
OUTPUT '#'
LOI\D USER P COUNTER
DISPLAY ADDRESS
GET NEW COMMAND

FUNCTION: BREAK
INPUTS: NONE
OUTPUTS: CARRY - 1 IF ESCAPE CHARACTER INPUT
- 0 IF ANY OTHER CHARACTER OR NO CHARACTER PENDING
CALLS: NOTHING
DESTROYS: A,F/F'S

•

...

f

•

•

•

•

•

,

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
83/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o

•

•

PAGE 14

DESCRIPTION: BREAK IS USED TO SENSE AN ESCAPE CHARACTER FROM
THE USER. IF NO CHARACTER IS PENDING, OR IF THE
PENDING CHARACTER IS NOT THE ESCAPE, THEN A FAILURE
RETURN (CARRY=0) IS TAKEN. IN THIS CASE, THE
PENDING CHARACTER (IF ANY) IS LOST. IF THE PENDING
CHARACTER IS AN ESCAPE CHARACTER, BREAK TAKES A SUCCESS
RETURN (CARRY=1).
;

0lC2
0lC2
0lC4
01C6
0lC9
01CB
01CD
01CF
lHD2

BREAK:
DBED
E632
CA1D32
DBEC
E67F
FEIB
CA3B03
C31D02

IN
ANI
JZ
IN
ANI
CPI
JZ
JMP

CONST
RBR
FRET
CNIN
PRTY13
BRCHR
SRET
FRET

GET CONSOLE STATUS
SEE IF CHARACTER PENDING
NO - TAKE FAILURE RETURN
YES - PICK UP CHARACTER
STRIP OFF PARITY BIT
SEE IF BREAK CHARACTER
YES - SUCCESS RETURN
NO - FAILURE RETURN - CHARACTER LOST

;

,.*****************************************************************

.,
0105
0lDS
0107
0109
0lDC
01DE

FUNCTION: CI
INPUTS: NONE
OUTPUTS: A - CHARACTER FROM CONSOLE
CALLS: NOTHING
DESTROYS: A,F/F'S
DESCRIPTION: CI WAITS UNTIL A CHARACTER HAS BEEN ENTERED AT THE
CONSOLE AND THEN RETURNS THE CHARACTER, VIA THE A
REGISTER, TO THE CALLING ROUTINE. THIS ROUTINE
IS CALLED BY THE USER VIA A JUMP TABLE IN RAM •

CI:
DBED
E602
CADSi'll
DBEC
C9

IN
ANI
JZ
IN
RET

CONST
RBR
CI
CNIN

GET STATUS OF CONSOLE
CHECK FOR RECEIVER BUFFER READY
NOT YET - WAIT
READY SO GET CHARACTER

,
7******************************************************************
FUNCTION: CNVBN
INPUTS: C - ASCII CHARACTER
OUTPUTS: A - 3 TO F HEX
CALLS: NOTHING
DESTROYS: A,F/F'S
DESCRIPTION: CNVBN CONVERTS
CHARACTER INTO
DOES NOT CHECK

'3'-'9' OR 'A'-'F'

THE ASCII REPRESENTATION OF A HEX
ITS CORRESPONDING BINARY VALUE. CNVBN
THE VALIDITY OF ITS INPUT.

..

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEt4BER 1976

010F
01DF
01EO
01E2
01E4
01E5
UE7

r, PAGE 15

CNVBN:
79
0630
FEOA
Fa
0607
C9

MOV
SUI
CPI
RM
SUI
RET

A,C
'0 '

10
7

'"

FROM ARGUMENT
SUBTRACT CODE FOR
'
WANT TO TEST FOR RESULT
OF 0 TO 9
IF SO, THEN ALL DONE
ELSE, RESULT BETWEEN 17 AND 23 DECIMAL
SO RETURN AFTER SUBTRACTING BIAS OF 7

.**********************************************************************

I

;. FUNCTION: CO
INPUTS: C - CHARACTER TO OUTPUT TO CONSOLE
OUTPUTS: C - CHARACTER OUTPUT TO CONSOLE
CALLS: NOTHING
DESTROYS: A,F/F'S
DESCRIPTION: CO WAITS UNTIL THE CONSOLE IS READY TO ACCEPT A CHARACTER
AND THEN SENDS THE INPUT ARGUMENT TO THE CONSOLE.
01E8
01E8
fll EI\

01EC
01EF
01F"
01F2

CO:
DBED
E601
CAEB01
79
D3EC
C9

IN
}I.NI

JZ
MOV
OUT
RET

CONST
TROY
CO
A,C
CNOUT

GET STATUS OF CONSOLE
SEE IF TRANSMITTER READY
NO - WAIT
ELSE, MOVE CHARACTER TO A REGISTER FOR OUTPUT
SEND TO CONSOLE

I

;*****************************************************************
FUNCTION CROUT
INPUTS: NONE
OUTPUTS: NONE
CALLS: ECHO
DESTROYS: A,B,C,F/F'S
DESCRIPTION: CROUT SENDS A CARRIAGE RETURN (AND HENCE A LINE
FEED) TO THE CONSOLE.
;

01F3
'HF3
01FS
UF8

CROUT:
0EOD
CDF901
C9

MVI
CALL
RET

C,CR
ECHO

OUTPUT CARRIAGE RETURN TO USER TERMINAL

;

.*******************************************************************

I

FUNCTION: ECHO

•

It

•

•

•

•

"

•

•

•

"

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

•

o PAGE 16

INPUTS: C - CHARACTER TO ECHO TO TERMINAL
OUTPUTS: C - CHARACTER ECHOED TO TERMINAL
CALLS: CO
DESTROYS: A,B,P/F'S
DESCRIPTION: ECHO TAKES A SINGLE CHARACTER AS INPUT AND, VIA
THE MONITOR, SENDS THAT CHARACTER TO THE USER
TERMINAL. A CARRIAGE RETURN IS ECHOED AS A CARRIAGE
RETURN LINE FEED, AND AN ESCAPE CHARACTER IS ECHOED AS $.
;

01F9
01F9
01FA
0lFC
(lIFO

0200
0202
~." 20 2
0205
0207
0208
0208
02130
02113
0211"
0211

ECHO:
41
3E1B
B8
C20202
0E24

MOV
MVI
O!P
JNZ
MVI

B,C
A,ESC
B
ECIlOS
CI I $ I

CALL
MVI
CMP
JNZ
11VI
CALL

CO
A,CR
B
ECHUl
C,LF
CO

SEE IF CHARACTER ECHOED WAS A CARRIAGE RETURN
NO - NO NEED TO TAKE SPECIAL ACTION
YES - WANT TO ECHO LINE FEED, TOO

MOV
RET

C,B

RESTORE ARGUMENT

SAVE ARGUMENT
SEE IF ECHOING AN ESCAPE CHARACTER
NO - BRANCH
YES - ECHO AS $

ECH05:
CDE801
3E0D
B8
C210132
0EllA
CDE801

DO OUTPUT THROUGH MONITOR

ECHHl:
48
C9
;

,.**********************************************************************
FUNCTION: ERROR
INPUTS: NONE
OUTPUTS: NONE
CALLS: ECHO,CROUT,GETCM
DESTROYS: A,B,C/F/F'S
DESCRIPTION: ERROR PRINTS THE ERROR CHARACTER (CURRENTLY AN ASTERISK)
ON THE CONSOLE, FOLLOWED BY A CARRIAGE RETURN-LINE FEED,
AND THEN RETURNS CONTROL TO THE COMMAND RECOGNIZER.
0212
0212
0214
0217
0217
021A

ERROR:
0E23
CDF901

MVI
CALL

C, I # I
ECHO

SEND # TO CONSOLE

CALL
JMP

CROUT
GETCM

SKIP TO BEGINNING OF NEXT LINE
TRY AGAIN FOR ANOTHER COMMAND

EXIT:
CDF301
C32C00

,

,.**********************************************************************
FUNCTION: rRET

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS = 0 PAGE 17
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
INPUTS: NONE
OUTPUTS: CARRY - ALWAYS 0
CALLS: NOTHING
DESTROYS: CARRY
DESCRIPTION: FRET IS JUMPED TO BY ANY ROUTINE THAT WISHES TO
INDICATE FAILURE ON RETURN. FRET SETS THE CARRY
FALSE, DENOTING FAILURE, AND THEN RETURNS TO THE
CALLER OF THE ROUTINE INVOKING FRET.
021D
021D
021E
021F

FRET:
37
3F
C9

STC
CMC
RET

FIRST SET CARRY TRUE
THEN COMPLEMENT IT TO MAKE IT FALSE
RETURN APPROPRIATELY

,
r**********************************************************************

,
0220
0220
0223
0225
0226

FUNCTION: GETCH
INPUTS: NONE
OUTPUTS: C - NEXT CHARACTER IN INPUT STREAM
CALLS: CI
DESTROYS: A,C,F/F'S
DESCRIPTION: GETCH RETURNS THE NEXT CHARACTER IN THE INPUT STREAM
TO THE. CALLING PROGRAM.

GETCH:
CDD501
E67F
4F
C9

CALL
ANI
MOV
RET

CI
PRTY0
C,A

GET CHARACTER FROM TERMINAL
TURN OFF PARITY BIT IN CASE SET BY CONSOLE
PUT VALUE IN C REGISTER FOR RETURN

,
,.**********************************************************************
FUNCTION: GETHX
INPUTS: NONE
OUTPUTS: BC - 16 BIT INTEGER
D - CHARACTER WHICH TERMINATED THE INTEGER
CARRY - 1 IF FIRST CIlJ\IH\C'rER NOT DELIMITER
- 0 IF FIRST CHARACTER IS DELIMITER
CALLS: GETCH,ECHO,VALDL,VALDG,CNVBN,ERROR
DESTROYS: A,B,C,D,E,F/F'S
DESCRIPTION: GETHX ACCEPTS A STRING OF HEX DIGITS FROM THE INPUT
STREAM AND RETURNS THEIR VALUE AS A 16 BIT BINARY
INTEGER. IF MORE THAN 4 HEX DIGITS ARE ENTERED,
ONLY THE LAST 4 ARE USED. THE NUMBER TERMINATES WHEN
A VALID DELIMITER IS ENCOUNTERED. THE DELIMITER IS
ALSO RETURNED AS AN OUTPUT OF THE FUNCTION. ILLEGAL
CHARACTERS (NOT HEX DIGITS OR DELIMITERS) CAUSE AN

•

,

•

•

•

•

..

•

•

•

•

•

••

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

e

0 PAGE 18

•

•

ERROR INDICATION.
IF THE FIRST (VALID) CHARACTER
ENCOUNTERED IN THE INPUT STREAM IS NOT A DELIMITER,
GETHX WILL RETURN WITH THE CARRY BIT SET TO 1;
OTHERWISE, THE CARRY BIT IS SET TO 0 AND THE CONTENTS
OF BC ARE UNDEFINED.
;

0227
0227
0228
022B
022D
0220
0230
0233

GETHX:
E5
210000
1E00

PUSH
LXI
MVI

H
H,0
E,0

SAVE HL
INITIALIZE RESULT
INITIALIZE DIGIT FLAG TO FALSE

CALL
CALL
CALL
FALSE
JNC
MOV
PUSH
POP
POP
MOV
ORA
JNZ
JZ

GETCH
ECHO
VALDL
GHX10
GHX10
D,C
H
B
H
A,E
A
SRET
FRET

GET A CHARACTER
ECHO THE CHARACTER
SEE IF DELHlITER
NO - BRANCH

CALL
FALSE
JNC
CALL
MVI
DAD
DAD
DJI.D
DAD
MVI
MOV
DAD
JNP

VALDG
ERROR
ERROR
CNVBN
E,OFFH
H

IF NOT DELIMITER, SEE IF DIGIT
ERROR IF NOT A VALID DIGIT, .EITHER

GHX0S:
CD2002
CDFgel
CD8203

1
0236 1 024502
0239
51
023A
E5
023B
Cl
023C
El
0230
7B
023E
B7
023F
C23B03
0242
CAID02
0245
CD6703
0245
1
0248 1 D21202
024B
CDDFOl
024E
1EFF
e250
29
0251
29
0252
29
0253
29
0254
0600
0256
4F
0257
09
C32D02
0258

+

+

YES - ALL DONE, BUT WANT TO RETURN DELIMITER
MOVE RESULT TO BC
RESTORE HL
GET FLAG
SET FIF'S
IF FLAG NON-O, A NUMBER HAS BEEN FOUND
ELSE, DELIMITER WAS FIRST CHARACTER

GHX10:

+
+

H

H
H

B,0
C,A
B
GHX0S

CONVERT DIGIT TO ITS BINARY VALUE
SET DIGIT FLAG NON-0
*2
*4
*8
*16
CLEAR UPPER 8 BITS OF BC PAIR
BINARY VALUE OF CHARACTER INTO C
ADD THIS VALUE TO PARTIAL RESULT
GET NEXT CHARACTER

,
,.*****************************************************************
FUNCTION: GETNM
INPU~S: C - COUNT OF NUMBERS TO FIND IN INPUT STREAM
OUTPUTS: TOP OF STACK - NUMBERS FOUND IN REVERSE ORDER (LAST ON TOP
OF STACK)
CALLS: GETHX,HILO,ERROR
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: GETNM FINDS A SPECIFIED COUNT OF NUMBERS, BETWEEN 1
AND 3, INCLUSIVE, IN THE INPUT

-

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
813/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o PAGE 19

STREAM AND RETURNS THEIR VALUES ON THE STACK.
IF 2
OR MORE NUMBERS ARE REQUESTED, THEN THE FIRST MUST BE
LESS THAN OR EQUAL TO THE SECOND, OR THE FIRST AND
SECOND NUMBERS WILL BE SET EQUAL. THE LAST NUMBER
REQUESTED MUST BE TERMINATED BY A CARRIAGE RETURN
OR AN ERROR INDICATION WILL RESULT.
;

025B
025B
0250
025E
0260
0261
0262
0262

GETNM:
2EI:'I3
79
E603
C8
67

MVI
MOV
ANI

L,3
A,C
3

RZ

PUT MAXIMUM ARGUMENT COUNT INTO L
GET THE ACTUAL ARGUMENT COUNT
FORCE TO MAXIMUM OF 3
IF 0, DON'T BOTHER TO DO ANYTHIING
ELSE, PUT ACTUAL COUNT INTO H

MOV

H,A

CALL
FALSE
JNC
PUSH
DCR
DCR
JZ
MOV
CPI
JZ
JMP

GETHX
ERROR
ERROR

GET A NUMBER FROM INPUT STREAM
ERROR IF NOT THERE - TOO FEW NUMBERS

B

ELSE, SAVE NUMBER ON STACK
DECREMENT MAXIMUM ARGUMENT COUNT
DECREMENT ACTUAL ARGUMENT COUNT
BRANCH IF NO MORE NUMBERS WANTED
ELSE, GET NUMBER TERMINATOR TO A
SEE IF CARRIAGE RETURN
ERROR IF SO - TOO FEW NUMBERS
ELSE, PROCESS NEXT NUMBER

GNM05:

CD2702
1
0265 1 021202
0268
C5
0269
2D
026A
25
026B
CA7702
026E
7A
026F
FE0D
0271
CA1202
0274
C36202
0277
0277
7A
0278
FE0D
027A
C21202
0270
OlFFFF
0280
70
13281
B7
0282
CA8A02
0285
1:'1285
C5
13286
2D
0287
C28502
028A
028A
Cl
028B
01
028C
El
0280
CDA002
1
0290 1 029502
0293
54
0294
50
0295
0295
E3
0296
05
0297
C5
0298
E5

•

+

+

L
H

GmllO
A,O
CR
ERROR
GNN05

GNM10:
MOV
CPI
JNZ
LXI
MOV
ORA
JZ
GNM15: .
PUSH
DCR
JNZ
GNM20:
POP
POP
POP
CALL
+
FALSE
+
JNC
MOV
MOV
GNM25:
XTHL
PUSH
PUSH
PUSH

,.

A,O
CR
ERROR
B,0FFFFH
A,L
A

GNM20
B
L

WHEN COUNT 0, CHECK LAST TERMINATOR
ERROR IF NOT CARRIAGE RETURN
; HL GETS LARGEST NUMBER
GET WHAT'S .LEFT OF MAXIMUM ARG COUNT
CHECK FOR 0
IF YES, 3 NUMBERS WERE INPUT
IF NOT, FILL REMAINING ARGUMENTS WITH 0FFFFH

GNM15
B
D
H

GET THE 3 ARGUMENTS OUT

HILO
GNM25
GNM25
D,H
E,L

SEE IF FIRST
NO - BRANCH

D

B
H

.s'

>=

SECOND

YES - MAKE SECOND EQUAL TO THE FIRST
PUT
PUT
PUT
PUT

FIRST ON STACK - GET RETURN ADOR
SECOND ON STACK
THIRD ON 'STACK
RETURN ADDRESS ON STACK

•

•

'

•

.

,

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0299
0299
029A
029B
029C
0290

•

•

•

[3

•

PAGE 20

GNM30:
3D
F8
E1
E3
C39902

DCR
RM
POP
XTHL
JMP

A
H
GNM30

DECREMENT RESIDUAL COONT
IF NEGATIVE, PROPER RESULTS ON STACK
ELSE, GET RETURN ADDR
REPLACE TOP RESULT WITH RETURN ADDR
TRY AGAIN

;

,.*****************************************************************
FUNCTION: HILO
INPUTS: DE - 16 BIT INTEGER
HL - 16 BIT INTEGER
OUTPUTS: CARRY - 0 IF HL(DE
- 1 IF HL)=DE
CALLS: NOTHING
DESTROYS:'A,F/F'S
DESCRIPTION: HILO COMPARES THE 2 16 BIT INTEGERS IN HL AND DE. THE
INTEGERS ARE TREATED AS UNSIGNED NUMBERS. THE CARRY
BIT IS SET ACCORDING TO THE RESULT OF THE COMPARISON.
;

02AO
02AO
02Al
02A2
02A3
02A4
02AS
02A6
02A7
02AA
02AB
02AC
02AD
02AE
fl2AF
02AF
02BO
02Bl

HILO:
PLlSH
HOV
INX
HOV
ORA
DCX
STC
JZ
MOV
SUB
MOV
SBB
CMC

CS
47
23
7C
BS
2B
37
CAAF02
7D
93
7C
9A
3F

B
B,A
H
A,H
L
H
HIL0S
A,L
E
A,H
D

SAVE BC
SAVE A REGISTER
INCREMENT 8L BY 1
WANT TO TEST FOR 0 RESULT AFTER
/INCREMENTING
RESTORE HL
SET CARRY
IF SO, CARRY IS SET PROPERLY
IF NOT, MOVE L TO A
SUBTRACT E
MOVE H TO A
SUBTRACT D WITH BORROW
COMPLIMENT CARRY FOR CORRECT CARRY BIT VALUE

HILOS:
78
Cl
C9

MOV
POP
RET

A,B
B

RESTORE A
RESTORE BC
EXIT

;
,.*****************************************************************

FUNCTION INUST
INPUTS: NONE
OUTPUTS: ljOTHING
CALLS: NOTHING
DESTROYS: A,H,L~SP
DESCRIPTION: INUST OUTPUTS TO THE USART THE COMMAND WORD

,

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o

PAGE 21

AND INITIALIZES THE STACK POINTER.
~

02B2
02B2
0284
02B6
0289
02BC
02BF

INUST:
3E25
D3ED
2H123C
22383C
312E3C
C31E00

MVI
OUT
LXI
SHLD
LXI
JMP

A,CMD
CNCTL
: OUTPUT COMMAND WORD TO USART
H,MSTAK-44
; LOAD POINTER TO STACK
SSAVE
INITIALIZE USER STACK POINTER
; INITIALIZE MONITOR STACK
SP,MSTAK
SOMSG
: GO TO PRINT SIGNON MESSAGE

;

,.**********************************************************************
FUNCTION: NMOUT
INPUTS: A - 8 BIT INTEGER
OUTPUTS: NONE
CALLS: ECHO,PRVAL
DESTROYS: A,B,C,F/F'S
DESCRIPTION: Nl-:OUT CONVERTS THE 8 BIT, UNSIGNED INTEGER IN THE
A REGISTER INTO 2 ASCII CHARACTERS. THE ASCII CHARACTERS
ARE THE ONES REPRESENTING THE 8 BITS. THESE TWO
CHARACTERS ARE SENT TO THE CONSOLE AT THE CURRENT PRINT
POSITION OF THE CONSOLE.
~

02C2
02C2
02C3
02C4
02C5
02C6
02C7
02CA
02CD
02CE
02D1
02D4

NMOUT:
F5
0F
0F
0F
0F
CDD502
CDF901
Fl
CDD502
CDF901
C9

PUSH
RRC
RRC

PSW

SAVE ARGUMENT

RRC

RRC
CALL
CALL
POP
CALL
CALL
RET

PRVAL
ECHO
PSW
PRVAL
ECHO

; GET UPPER 4 BITS TO LOW 4 BIT POSITIONS
;CONVERT LOWER 4 BITS TO ASCII
: SEND TO TERMINAL
: GET BACK ARGUMENT

,

,.**********************************************************************
FUNCTION; PRVAL
INPUTS: A - INTEGER, RANGE 0 TO F
OUTPUTS: A - ASCII CHARACTER
CALLS: NOTHING
DESTROYS: NOTHING
DESCRIPTION: PRVAL CONVERTS A NUMBER IN THE RANGE 0 TO F HEX TO
THE CORRESPONDING ASCII CHARACTER, 0-9,A-F. PRVAL
DOES NOT CHECK THE VALIDITY OF ITS INPUT ARGUMENT.

•

•

•

•

•

•

\0

t

•

•

•

•

•

808C MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0205
0205
02D7
0209
020A
02DC
02DD
02DE

o

•

•

PAGE 22

PRVAL:
E60F
C6913
27
CE40
27
4F
C9

ANI
ADI
OAA
ACI
DAA
MOV
RET

HCHAR
90H
401l
C,A

MASK OUT UPPER 4 BITS - WANT 1 HEX CHAR
SET UP A SO THAT A-F CAUSE A CARRY
ADJUST CONTENTS OF A REGISTER
ADD IN CARRY AND ADJUST UPPER 4 BITS
ADJUST CONTENTS OF A REGISTER AGAIN
MOVE ASCII CHARACTER TO C
ALL DONE

,.********************************************************************

,
02DF
02DF
02E2
02E2
02E3
02E4
02ES
02£8
02EB
02EC
02EC
02EF
02Fl
02F4
02FS
02F6
02F8
02F9
02FA
02FO
02FE
02FF
" 302
03133
0304
0307
0307

FUNCTION: REGDS
INPUTS: NONE
OUTPUTS: NONE
CALLS: ECHO,NMOUT,ERROR,CROUT
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: REGDS DISPLAYS THE CONTENTS OF THE REGISTER SAVE
LOCATIONS, IN FORMATTED FORM, ON THE CONSOLE. THE
DISPLAY IS DRIVEN FROM A TABLE, RTAB, WHICH CONTAINS
THE REGISTER'S PRINT SYMBOL, SAVE LOCATION ADDRESS,
AND LENGTH (8 OR 16 BITS).

REGOS:
21C003

LXI

H,RTAB

LOAD HL WITH ADDRESS OF START OF TABLE

MOV
140V
ORA
JNZ
CALL
RET

C,M
A,C

GET PRINT SYMBOL OF REGISTER

A

REGI"
CROUT

TEST FOR 0 - END OF TABLE
IF N,OT END, BRANCH
ELSE, CARRIAGE RETURN/LINE FEED TO END
/DISPLAY

ECHO

ECHO CHARACTER

REG0S:
4E
79
B7
C2EC02
CDF3"1
C9
REG10:
CDF901
0E3D
COF901
23
SE
163C
23

CALL
MVI
CALL
INX
MOV
MVI
INX
LDAX
CALL
HOV
ORA
JZ
DCX
LDAX
CALL

lA
CDC202
7E
B7
CA0703
IB

lA
CDC202

C,

'_"I
-

ECHO

OUTPUT EQUALS SIGN, I.E. A=
POINT TO START OF SAVE LOCATION ADDRESS
E,N
; GET LSP OF SAVE LOCATION ADDRESS TO E
D,OATA SHR 8'
; PUT MSP OF SAVE LOC ADDRESS INTO D
H
POINT TO LENGTH FLAG
o
GET CONTENTS OF SAVE ADDRESS
NMOUT
DISPLAY ON CONSOLE
A,M
GET LENGTH FLAG
A
SET SIGN F/F
REGIS
IF 0, REGISTER IS 8 BITS
ELSE, 16 BIT REGISTER SO MORE TO DISPLAY
o
o
GET LOWER 8 BITS
NMOUT
DISPLAY THEM

H

REGIS:
0E20

HVI

C, ,

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0309

,noc
0300

CDF9£1l
23
C3E202

CALL
INX
JMP

ECHO
II

REG0S

=0

PAGE 23

OUTPUT BLANK CHARACTER
POINT TO START OF NEXT TABLE ENTRY
DO NEXT REGISTER

..• *****************************************************************
FUNCTION: RGADR
INPUTS: C - CHARACTER DENOTING REGISTER
OUTPUTS: BC - ADDRESS OF ENTRY IN RTAB CORRESPONDING TO REGISTER
CALLS: ERROR
DESTROYS: A,B,C,D,E,II,L,F/F'S
DESCRIPTION: RGADR TAKES A SINGLE CHARACTER AS INPUT. THIS CHARACTER
DENOTES A REGISTER.
RGADR SEARCHES THE TABLE RTAB
FOR A MATCH ON THE INPUT ARGUMENT.
IF ONE OCCURS,
RGADR RETURNS THE ADDRESS OF THE ADDRESS OF THE
SAVE LOCATION CORRESPONDING TO THE REGISTER. TillS
ADDRESS POINTS INTO RTAB.
IF NO ~lATCH OCCURS, THEN
THE REGISTER IDENTIFIER IS ILLEGAL AND CONTROL IS
PASSED TO THE ERROR ROUTINE.

0310
0310
0313
0316
0316
0317
0318
031B
03lC
031F
0320
0323
0323
0324
0325
0326

RGADR:
LXI
LXI

H,RTAB
D,RTABS

HL GETS ADDRESS OF TABLE START
DE GET SIZE OF A TABLE ENTRY

MOV
ORA
JZ
CMP
JZ
DAD
JMP

A,M
A
ERROR
C
RGAl0
D
RGJI,0S

GET REGISTER IDENTIFIER
CHECK FOR TABLE END (IDENTIFIER IS 0)
IF AT END OF TABLE, ARGUMENT IS ILLEGAL
ELSE, COMPARE TABLE ENTRY AND ARGm-lENT
IF EQUAL, WE'VE FOUND WHAT WE'RE LOOKING FOR
ELSE, INCREMENT TABLE POINTER TO NEXT ENTRY
TRY AGAIN

23

INX

44

~10V

4D
C9

MOV
RET

H
B,H
C,L

IF A MATCH, INCREMENT TABLE POINTER TO
/SAVE LOCATION ADDRESS
RETURN THIS VALUE

21C003
IHl300
RGJI,0S:
7E
B7
CA1202
B9
CA2303
19
C31603
RGA10:

,

,.*****************************************************************
FUNCTION: RSTTF
INPUTS: NONE
OUTPUTS: NONE
CALLS: NOTHING
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCaIPTION: RSTTF RESTORES ALL CPU REGISTER, FLIP/FLOPS, STACK
POINTER AND PROGRAM' COUNTER FROM THEIR RESPECTIVE
SAVE LOCATIONS IN MEMORY. THE ROUTINE THEN TRANSFERS

•

.

,

•

•

•

...

•

•

•

"

•

..

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o

•

•

PAGE 24

CONTROL TO THE LOCATION SPECIFIED BY THE PROGRAM
COUNTER (I.E. THE RESTORED VALUE). THE ROUTINE
EXITS WITH THE INTERRUPTS ENABLED.
0327
0327
0328
032B
032C
032D

032E
0331
0332
0335
0336
0339
033A

i

RSTTF:
F3
312E3C

01
LXI

01
Cl
FI
2A383C
F9
2A363C
E5
2A343C
FB
C9

POP

POP
POP
LHLD
SPHL
LHLD
PUSH
LHLD
EI
RET

SP,MSTAK
D
B
PSW
SSAVE

; DISABLE INTERRUPTS WHILE RESTORING THINGS
; SET MONITOR STACK POINTER TO START
IOF STACK
START ALSO END OF REGISTER SAVE AREA
RESTORE USER STACK POINTER

PSAVE
H

LSAVE

PUT USER RETURN ADDRESS ON USER STACK
RESTORE HL REGISTERS
ENABLE INTERRUPTS NOW
JUMP TO RESTORED PC LOCATION

;

,.*****************************************************************
FUNCTION: SRET
INPUTS: NONE
OUTPUTS: CARRY = I
CALLS: NOTHING
DESTROYS: CARRY
DESCRIPTION: SRET IS JUMPED TO BY ROUTINES WISHING TO RETURN SUCCESS.
SRET SETS THE CARRY TRUE AND THEN RETURNS TO THE
CALLER OF THE ROUTINE INVOKING SRET.

j

1333B
0338
1333C

SRET:
'STC
RET

37
C9

SET CARRY TRUE
RETURN APPROPRIATELY

;

,.*****************************************************************

,
033D

FUNCTION: S'l'BFO
INPUTS: DE - 16 BIT ADDRESS OF BYTE TO BE STORED INTO
OUTPUTS: NONE
CALLS: NOTHING
DESTROYS: A/B,C,n,L,F/FoS
DESCRIPTION: STHFO CHECKS THE HALF BYTE FLAG IN TEMP TO SEE IF
IT IS SET TO LOWER.
IF SO, STHF0 STORES A " TO
PAD OUT THE LOWER HALF OF THE ADDRESSED BYTE:
OTHERWISE, THE ROUTINE TAKES NO ACTION.

STHF0:

•

*

•

sese

MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

1333D
13340
0341
3342
0344
0347

3A3A3C
B7
C0
(jE00
CD4S03
C9

LOA
ORA
RNZ
MVI
CALL
RET

TEMP
A
C,0
STHLF

o

PAGE 25

GET HALF BYTE FLAG
SET F/F'S
IF SET TO UPPER, DON'T DO ANYTHING
ELSE, WANT TO STORE THE VALUE"
DO IT

;

.*****************************************************************

I

FUNCTION: STHLF'
INPUTS: C - 4 BIT VALUE TO BE STORED IN HALF' BYTE
DE - 16 BIT ADDRESS OF BYTE TO BE STORED INTO
OUTPUTS: NONE
CALLS: NOTHING
DESTROYS: A,B,C,H,L,F/F'S
DESCRIPTION: STHLF TAKES THE 4 BIT VALUE IN C AND STORES IT IN
HALF OF THE BYTE ADDRESSED BY REGISTERS DE. THE
HALF' BYTE USED (EITHER UPPER OR LOWER) IS DENOTED
BY THE VALUE OF THE FLAG IN TEMP.
STHLF ASSUMES
THAT THIS FLAG HAS BEEN PREVIOUSLY SET
(NOMINALLY BY ICMD).
;

0348
0348
0349
034A
034B
034D
034E
0351
0352
0355
0356
0358
0359
035A
335B
035B
035C
035E
035F
3360
0361
3362
0363
0364
3365
3366

STHLF:
D5
E1
79
E60F
4F
3A3A3C
B7
C25B03
7E
E6F0
B1
77
C9

PUSH
POP
MOV
ANI

D
H

MOV

C,A

LDA
ORA
JNZ
MOV
ANI
ORA
MOV
RET

TEMP
A
STH05

A,C
0FH

A,M
0F0H
C
M,A

MOVE ADDRESS OF BYTE INTO HL
GET VALUE
FORCE TO 4 BIT LENGTH
PUT VALUE BACK
GET HALF BYTE FLAG
CHECK FOR LOWER HALF
BRANCH IF NOT
ELSE, GET BYTE
CLEAR LOWER 4 BITS
OR IN VALUE
PUT BYTE BACK

STH05:
7E
E6"F
47
79
0F
3F
0F
IJF
B0
77
C9

•

A, t4

MOV
ANI
MOV
MOV
RRC
RRC
RRC
RRC
ORA
MOV
RET

"

0FH
B,A

A,C

B

M,A

.,

IF UPPER HALF, GET BYTE
CLEAR UPPER 4 BITS
SAVE BYTE IN B
GET VALUE

ALIGN TO UPPER 4 BITS
OR IN ORIGINAL LOWER 4 BITS
PUT NEW CONFIGURATION BACK

•

•

•

•

,

•

.

•

.

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

•

" PAGE 26

,

,.*****************************************************************
FUNCTION: VALDG
INPUTS: C - ASCII CHARACTER
OUTPUTS: CARRY - 1 IF CHARACTER REPRESENTS VALID HEX DIGIT
- " OTHERWISE
CALLS: NOTHING
DESTROYS: A,F/F'S
DESCRIPTION: VALDG RETURNS SUCCESS IF ITS INPUT ARGUMENT IS
AN ASCII CHARACTER REPRESENTING A VALID HEX DIGIT
(0-9,A-F), AND FAILURE OTHERWISE.
0367
0367
0368
036A
0360
036F
0372
0375
0377
037A
037C
~37F

VALDG:
79
FE30
FA1D02
FE39
FA3B03
CA3B03
FE41
FAIDfil2
FE47
F21D02
C33B03

MOV
CPI
JM
CPI
JM
JZ
CPI
JM
CPI
JP
JMP

A,C
'0 '
FRET
'9 '
SRET
SRET
'A'
FRET
'G'
FRET
SRET

TEST CHARACTER AGAINST '0'
IF ASCII CODE LESS, CANNOT BE VALID DIGIT
ELSE, SEE IF IN RANGE '0'-'9'
CODE BETVmEN '0' AND '9 '
CODE EQUAL '9'
NOT A DIGIT - TRY FOR A LETTER
NO - CODE BETWEEN '9' AND 'A'
NO - CODE GREATER THAN 'F'
OKAY - CODE IS 'A' TO 'F', INCLUSIVE

;

;**********************************************************************
FUNCTION: VALDL
INPUTS: C - CHARACTER
OUTPUTS: CARRY - 1 IF INPUT ARGUMENT VALID DELIMTER
- 0 OTHERWISE
CALLS: NOTHING
DESTROYS: A,F/F'S
DESCRIPTION: VALDL RETURNS SUCCESS IF ITS INPUT ARGUMENT IS A VALID
DELIMITER CHARACTER (SPACE, COMMA, CARRIAGE RETURN) AND
FAILURE OTHERWISE.
0382
0382
0383
0385
0388
038A
038D
038F
0392

VALDL:
79
FE2C
CA3B03
FEeD
CA3B03
FE20
CA3B03
C31D02

MOV
CPI
JZ
CPI
JZ
CPI
JZ
JMP

A,C,

,,

CHECK FOR COMMA

SRET
CR
SRET

CHECK FOR CARRIAGE RETURN

, ,

CHECK FOR SPACE

SRET
FRET

ERROR IF NONE OF THE ABOVE

•

"

•

:rJ

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

o PAGE 27

;

,.*****************************************************************
MONITOR TABLES

;

,.*********************************************~~******************
0395
0395
0399
039D
03Al
03A5
0011

SGNON:
0D0A3830
2F313020
4D4F4E49
544F520D
OA

; SIGNON MESSAGE
CR,LF,'80/10 MONITOR',CR,LF

DB

LSGNON

EQU

$-SGNON ; LENGTH OF SIGNON MESSAGE

;

03A6
03A6
03A8
03M
03AC
03AE
0380
0382
03B4
03B6
03B8
03B8
03B9
038A
038B
03BC
03BD
03BE
03BF
0008
03C0
03C0
e3Cl
(DC2
0003
03C3
03C4
03C5
e3C6
03C7

CADR:
0000
3301
0FOl
EF00
A900
8B00
5F00
0604
4104

DW
DW

0
XCMD
SCMD
MCMD
ICMD
Gcrm
DCtm
RCMD
WCMD

mol

DW
DW
DW
DW
DW
DW

; TABLE OF ADDRESSES OF COMMAND ROUTINES
; DUMMY

eTAB;
57
52
44
47
49
4D
53
58

TABLE OF VALID COMMAND CHARACTERS

'w'

DB
DB
DB
DB
DB
DB
DB
DB
NCMDS EQU

'R'
'D'
'G'
'I'
'M •
'S'
'X'
$-CTAB

NUMBER OF VALID COMMANDS

RTAB:
41
33
00
42
31
00
43
313

•

DB
DB
DB
RTABS EQU
DB
DB
DB
DB
DB

.

'A'
ASAVE AND
0
$-RTAB
'B'
BSAVE AND
0

TABLE OF REGISTER INFORMATION
REGISTER IDENTIFIER
0FFH ; ADDRESS OF REGISTER SAVE LOCATION
LENGTH FLAG - 0=8 BITS, 1=16 BITS
SIZE OF AN ENTRY IN THIS TABLE
0FFH

'c'
CSAVE AND 0FFH

#

•

•

•

,.

•

•

.

•

...

•

ERRORS
saS0 MACRO ASSEMBLER, VER 2.4
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
03C8
03C9
03CA
03CB
03CC
03CD
133CE
03CF
133D0
03D1
0302
13303
0304
0305
03D6

03D7
03D8
0309
133DA
13308
03DC
03DD
03DE
03DF
03E0
03E1
133E2

00
44
2F

DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB

fHl

45
2E
00
46
32
013
48
35
00
4C
34
00
4D
35
01
50
37
01
53
39
01

G0
00

•
o

•

PAGE 28

0
'0'
DSAVE AND 0FFH

"

'E'
ESAVE
0
'F'
FSAVE
0
'H'
HSAVE
0
'L'
LSAVE
0

AND 0FFH
AND 0FFH
AND 0FFH
AND 0FFH

'M'

HSAVE AND 0FFH
1

'p'
PSAVE+l AND 0FFH
1
'5 '

SSAVE+1 AND 0FFH
1
: END OF TABLE MARKERS
0

"

;

,.**********************************************************************
03E3
03E3
03E7
133EB
03EF
03F3

CPYRT:
28432920
31393736
20494E54
454C2043
4F5250

DB

'(C) 1976 INTEL CORP'

,
,.**********************************************************************

ORG

BRTAB

C3E801

J~lP

C3D501

JMP
JMP
JMP

CO
C1
HI
PO

'BFA
03FA
03FD
0400
0403

C31C05
C30F135

BRANCH TABLE FOR USER ACCESSIBLE ROUTINES

•

"

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1. 1 NOVEMBER 1976

o PAGE 29

.,

,.*****************************************************************
FUNCTION RCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS: GETCH,ECHO,CO,RICH,BYTE
DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: ROID INPLEMENTS TilE READ HEXADECIMAL TAPE (R)
CmlMAND.
~

0406
0406
0409
040C
040D
04(JF
0412
0412
0415
0417
041A
041B
041C
041F
0422
0423
0426
0427
042A
042B
042E
042F
042F
0432
0433
l'!4 3 4

0435
0438
043B
"43E

RCMD:
CD2002
CDF901
79
FEOD
C21202

CALL
CALL
MOV
CPI
JNZ

GETCH
ECHO
A,C
CR
ERROR

GET CARRIAGE RETURN CHARACTER
ECHO IT
MOVE IT TO A REGISTER
SEE IF CARRIAGE RETURN
ERROR IF NOT PROPERLY TERMINATED

CALL
CPI
JNZ
XRA
MOV
CALL
JZ
MOV
CALL
MOV

RICH

READ CHARACTER FROM TAPE
SEE IF RECORD MARK
TRY AGAIN IF NOT MARK
ZERO A REGISTER
INITIALIZE D FOR HOLDING TilE CHECKSUM
READ TlvO CHARACTERS FROM TAPE
IF ZERO RECORD LENGTH, ALL DONE
OTHERWISE, PUT THE RECORD LENGTH IN E
GET MSB OF LOAD ADDRESS
MOVE TO H
GET LSB OF LOAD ADDRESS
MOVE TO L
GET RECORD TYPE
MOVE RECORD LENGTH TO C

RCM05:
CD1305
FE3A
C21204
AF
57
CD96D4
CA2C00
SF
CD9604
67
CD9604
6F
CD9604
4B
CD9604
77
23
ID
C22F04
CD9604
C21202
C31204

RCM05
A

D,A
BYTE
GETCM
E,A
BYTE
Il,A
BYTE

Ca1'..LL

MOV
CALL
MOV
RCM10: .
CALL
MOV
INX
DCR
JNZ
CALL
JNZ
JMP

L,A
BYTE
C,E
BYTE
M,A
H
E

RCM10
BYTE
ERROR
RCM05

1

READ DATA FROM TAPE
PUT DATA INTO MEMORY
INCREMENT HL FOR NEXT LOCATION
DECREMENT RECORD LENGTH
LOOP UNTIL DONE
READ CHECKSUM FROM TAPE
CIIECKSUM ERROR IF NOT ZERO
GET ANOTHER RECORD

~***************************************************** ************

FUNCTION WCMD
INPUTS: NONE
OUTPUTS: NONE
CALLS:GETNM,LEAD,PO,PBYTE,PADR,PEOL,PEOF

•

.

~

•

•

•

.,

•

•

..

•

.

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS = 0 PAGE 30
SO/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

,
0441
0441
0443
0446
0449
044A
044B
044B
044C
044E
044F
3450
0452
0453
0454
0455
0456
0457
0458
045B
045D
0460
0463
0461
0463
0463
0464
0467
3468
0469
046B
046D
0470
0471
0474
0477
0478
047B
0478
047C
047F
0480
0481
0484
0485
0486
0489

•

•

DESTROYS: A,B,C,D,E,H,L,F/F'S
DESCRIPTION: WCMD IMPLEMENTS THE WRITE HEXADECIMAL TAPE (W)
COMMAND.

WCMD:
0E02
CD5B02
CDBA04
D1
E1

MVI
CALL
CALL
POP
POP

C,2
GETNM
LEAD

MOV
ADI
MOV
MOV
ACI
MOV
MOV
SUB
MOV
110V
SBB
JC
MVI
JMP

A,L
16
C,A
A,H

WCM13
A,16
WCM15

MOVE L TO A
INCREMENT THE LSB OF STARTING ADDRESS BY 16
MOVE RESULT TO C
MOVE H TO A
ADD CARRY IN FROM PREVIOUS OPERATION
SAVE RESULT IN B
NOW MOVE LSB OF ENDING ADDRESS TO A
SUBTRACT LSB OF STARTING ADDRESS
SAVE IN C
NOW GET MSB OF ENDING ADDRESS IN A
SUBTRACT MSB OF STARTING ADDRESS
BRANCH IF THE RECORD LENGTH IS NOT 16
OTHERWISE SET A TO RECORD LENGTH OF 16
NOW BRANCH TO PUNCH THE RECORD

MOV
ADI

ATC
17

THIS IS THE LAST RECORD
SO SET A TO REMAINING DATA LENGTH

A

CHECK FOR RECORD LENGTH OF ZERO
IF IT IS, ALL DONE
OTHERWISE, SAVE ENDING ADDRESS
PUT RECORD LENGTH IN E
INITIALIZE 0 FOR HO~DING CHECKSUM

D
H

GET 2 NUMBERS FROM INPUT STREAM
PUNCH 60 NULL CHARACTERS FOR TAPE LEADER
ENDING ADDRESS TO DE
STARTING ADDRESS TO HL

WCM05:
7D
C610
4F
7C
CEOO
47
7B
91
4F
7A
98
DA6004
3E10
C36304

o

B,A
A,E
C

C,A
A,D
B

WCM10:
79
C611
WCM15 :
87
CA9004
D5

ORA
JZ
PUSH
MOV
MVI
MVI
CALL
MOV
CALL
CALL
XRA
CALL

SF
1600
0E3A
CDOF05
7B
CDCF04
CDC604
AF
CDCF04

WCM25
D

E,A
D,0

.

C , '.'

PO
A,E
PBYTE
PADR
A

PBYTE

PUNCH RECORD HARK CHARACTER
PUT RECORD LENGTH IN A
PUNCH RECORD LENGTH
PUNCH STARTING ADDRESS
ZERO A
PUNCH RECORD TYPE

WCM20:
7E
CDCF04
23
10
C27B04
AF
92
CDCF04
01

MOV
CALL
INX
nCR
JNZ
XRA
SUB
CALL
POP

A,M
PBYTE
H
E

WCM20

CET CATA TO BE PUNCHED FROM MEMORY
PUNCH IT
INCREMENT MEMORY ADDRESS
DECREMENT LENGTH COUNT
LOOP UNTIL ALL DATA PUNCHED

A

o

PUNCH CHECKSUM

PBYTE
D

RESTORE ENDING ADDRESS

~

It

•

8~8~

t-IACRO ASSEMBLER, VER 2.4
ERRORS
se/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

"4SA
048D
111490
0490
0493

CD0405
C34B04

o PAGE 31

CALL
JMP

PEeL
WCM05

PUNCH CARRIAGE RETURN AND LINE FEED

CALL
JMP

PEOF
EXIT

PUNCH END OF FILE RECORD
ALL DONE

WCM25:
CDE604
C31702

.,

,.*****************************************************************
FUNCTION BYTE
INPUTS: D - CURRENT VALUE OF CHECKSUM
OUTPUTS: A - HEXADECIMAL CHARACTER
D - UPDATED VALUE OF CHECKSUM
CALLS: RICH,CNVBN
DESTROYS: A,B,C,D,F/F'S
DESCRIPTION: BYTE READS 2 ASCII CHARACTERS FROM THE TELETYPEWRITER
AND CONVERTS THE CHARACTERS TO ONE HEXADECIMAL CHARACTER.
THE A REGISTER CONTAINS THE FINAL CHARACTER AND THE
D REGISTER CONTAINS THE UPDATED VALUE OF
THE CHECKSUM.

t:r:I
I

w
N

0496
111496
0497
049A
049B
11I49E
049F
04A0
04A1
04A2
04A3
04A6
04A7
04AA
04AB
04AC
04AD
04AE
04AF
0480

BYTE:
C5
CD131115
4F
CDDF01
07
07
07
07
47
CDl305
4F
CDDF01
B0
4F
82
57
79
Cl

PUSH
CALL
MOV
CALL
RLC
RLC
RLC
RLC
MOV
CALL
MOV
CALL
ORA
MOV
ADD
MOV
MOV
POP
RET

C9

B
RICH
C,A
CNVBN

B,A
RICH
C,A
CNVBN
B
C,A
D
D,A
A,C
B

SAVE BC
READ ASCII CHARACTER FROM TAPE
CONVERT CHARACTER TO HEXADECIMAL
POSITION VALUE INTO UPPER 4 BITS

SAVE RESULTS IN B
GET ANOTHER CHARACTER FROM TAPE
CONVERT IT
OR IN THE UPPER 4 BITS
SAVE
INCREMENT CHECKSUM
RESTORE HEX DATA TO A REGISTER
RESTORE BC

,
;*******k********************************************* ************
FUNCTION DELAY
INPUTS: NONE
OUTPUTS: NONE
CALL~: NOTHING

•

...

"

•

•

•

,.

•

•

•

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

" PAGE 32

DESTROYS: F/F'S
DESCRIPTION: DELAY PROVIDES A PROGRAMMED DELAY OF 1 MILLISECOND
FOR TAPE READER OPERATION.
;

04B1
04B1
04B2
04B4
04B4
04B5
04B8
04B9

DELAY:
C5
0683

PUSH
MVI

B
B ,ONEt1S

SAVE BC REGISTERS
LOAD 1 MILLISECOND CONSTANT

DCR
JNZ
POP
RET

B
DELI
B

DECREMENT INNER COUNTER
JUMP IF NOT DONE
RESTORE BC REGISTERS
RETURN TO CALLING ROUTINE

DELI:
05
C2B404
C1
C9

,

,.*****************************************************************
FUNCTION LEAD
INPUTS: NONE
OUTPUTS: NONE
CALLS: PO
DESTROYS: B,C,F/F'S
DESCRIPTIOM: LEAD OUTPUTS 60 NULL CHARACTERS TO PAPER TAPE TO FORM A
LEADER.

!j

I

oJ
oJ

•

04BA
04BA
"4BC
04BC
04BE
04Cl
04C2
04C5

LEAD:
063C

MVI

B,60

MVI
CALL
DCR
JNZ
RET

C,0
PO

LOAD B WITH A COUNT OF 60

LE05:
0E00
CD0F05
05
C2BC04
C9

PUNCH NULL CHARACTER
DECREMENT COUNT
DO IT AGAIN IF NOT DONE

B

LE05

,
,.*****************************************************************
FUNCTION PADR
INPUTS: HL - ADDRESS TO BE PUNCHED
OUTPUTS: NONE
CALLS: PBYTE
DESTROYS: A
DESCRIPTION: PADR PUNCHES ON THE TELETYPEWRITER THE ADDRESS
CONTAINED IN THE H,L REGISTERS.
04C6
04C6
04C7
04CA

PADR:
7C
CDCF04
70

MOV
CALL
MOV

A,H
PBYTE
A,L

J

PUNCH FIRST HALF OF ADDRESS
PUNCH SECOND HALF OF ADDRESS

•

.

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
04CB
04CE

CDCF04
C9

CALL
RET

.,

o

PAGE 33

PBYTE
RETURN TO CALLING ROUTINE

,.*****************************************************************
FUNCTION PBYTE
INPUTS: A - CHARACTER TO BE PUNCHED
D - CURRENT VALUE OF CHECKSUM
OUTPUTS: 0 - UPDATED VALUE OF CHECKSUM
CALLS: PRVAL,PO
DESTROYS: A,F/F'S
DESCRIPTION: PBYTE CONVERTS THE HEXADECIMAL VALUE IN TH~ A REGISTER
INTO TWO ASCII CHARACTERS AND PUNCHES THESE CHARACTERS
,.
ON PAPER TAPE. THE CHECKSUM CONTAINED IN D IS UPDATED •

.,

t<:l
I

w

+:--

04CF
04CF
0400
0401
0402
0403
04D4
04D7
04DA
04DB
040C
04DF
04E2
04E3
04E4
04E5

PBYTE:
F5
0F
0F
OF
0F
C00502
CDOF05
Fl
F5
COD502
C00F05
F1
82
57
C9

PUSH
RRC
RRC
RRC
RRC
CALL
CALL
POP
PUSH
CALL
CALL
POP
ADD
MOV
RET

PSW

SAVE A,F/F'S
POSITION UPPER 4 BITS INTO LOWER 4 BITS

PRVAL
PO
PSW
PSW
PRVAL
PO
PSW

CONVERT UPPER 4 BITS JUST ROTATED TO ASCII
PUNCH CHARACTER
RESTORE A,F/F'S
SAVE A AGAIN
CONVERT LOWER 4 BITS TO ASCII CHARACTER
PUNCH CHARACTER
RESTORE A
ADD VALUE TO CHECKSUM
UPDATE 0 REGISTER WITH NEW CHECKSUM
RETURN TO CALLING ROUTINE

D

D,A

;

,.*****************************************************************
FUNCTION PEOF
INPUTS: NONE
OUTPUTS: NONE
CALLS: PO,PBYTE,PADR,LEAD
DESTROYS: A,C,D,H,L,F/F'S
DESCRIPTON: PEOF PUNCHES THE END OF FILE RECORD CONSISTING OF A RECORD
MARK, A LOAD ADDRESS OF 0, THE RECORD TYPE, AND THE
RECORD CHECKSUM.
;

04E6
04E6
04E8
04EB

•

PEOF:
MVI
C.\LL

0E3A
CD0F05
AF

XRA

•

•

.

C , I.
PC)
A

I

PUNCH RECORD MARK
ZERO CHECKSUM

•

•

•

It

•

•

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
04EC
04ED
04FO
04F3
04F6
04F8
04FB
04FC
04FD

0500
0503

MOV
CALL
LXI
CALL
MVI
CALL
XRA
SUB
CALL
CALL
RET

57
CDCF04

210000
CDC604
3E01
CDCF04
AF
92
CDCF04
CDBA04
C9

D,A
PBYTE
H,O
PADR
A,l
PBYTE
A
D
PBYTE
LEAD

o

PAGE 34

•

•

SAVE IN D REGISTER
PUNCH RECORD LENGTH
LOAD HL WITH ZERO ADDRESS
PUNCH IT
LOAD A vi ITH RECORD TYPE
PUNCH IT
ZERO A
COMPUTE CHECKSUM
PUNCH IT
PUNCH TRAILER

,.*****************************************************************
FUNCTION PEOL
INPUTS: NONE
OUTPUTS: NONE
CALLS: PO
DESTROYS: C
DESCRIPTION: PEOL PUNCHES A CARRIAGE RETURN AND LINE FEED ONTO
PAPER TAPE.
;

0504

0504
0506
0509
050B
050E

PEOL:
LilEOD
CD0F05
OE0A
CD0F05
C9

MVI
CALL
MVI
CALL
RET

C,CR
PO
C,LF
PO

PUNCH CARRIAGE RETURN CHARACTER
PUNCH LINE FEED CHARACTER

;

,.*****************************************************************
FUNCTION PO
INPUTS: C - CHARACTER TO BE PUNCHED
OUTPUTS: NONE
CALLS: CO
DESTROYS: NOTHING
DESCRIPTION: PO PUNCHES THE CHARACTER SUPPLIED IN THE C REGISTER TO
THE USER TELETYPEWRITER.
050F
050F
0512

PO:
CDE801
C9

CALL
RET
;

CO

CALL CONSOLE OUT TO PERFORM CHARACTER OUTPUT

,.*****************************************************************

10

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976

=0

PAGE 35

FUNCTION RICH
INPUTS: NONE
OUTPUTS: A - ZERO, CARRY - 1 IF END OF FILE
A - CHARACTER, CARRY - 0 IF VALID CHARACTER
CALLS: RI
DESTROYS: A,F/F"S
DESCRIPTION: RICH TESTS FOR AN END OF FILE CONDITION.
0513
0513
0516
0519
051B

RICH:
CD1C05
DA1202
E67F
C9

CALL
JC
ANI
RET

READ A CHARACTER FROM TAPE
JUMP IF READER TIMEOUT ERROR
REMOVE PARITY BIT
RETURN TO CALLING ROUTINE

RI
ERROR
PRTY0

,
,.*****************************************************************
FUNCTION RI
INPUTS: NONE
OUTPUTS: A - ZERO, CARRY - 1 IF END OF FILE
A - CHARACTER, CARRY - 0 IF VALID CHARACTER
CALLS: DELAY
DESTROYS: A,F/F"S
DESCRIPTION: RI READS A CHARACTER FROM THE TTY TAPE READER.

trl
I

051C
"51C
051D
051D
051F
0521
0524
0526
0528
052A
052A
052D
052E
0531
0533
0535
0537
0537
0539
053B
053E
0541
0542
0545
0546

RI:
C5

PUSH

B

SAVE BC

IN
ANI
JZ
M'lI
OUT
MVI

CNCTL
TXBE
RI05
A,TTYADV
CNCTL
8,40

READ IN USART STATUS
CHECK FOR TRANSMITTER BUFFER EMPTY
TRY AGAIN IF NOT EMPTY
; ADVANCE THE TAPE
OUTPUT THE ADVANCE COMMAND
INITIALIZE TIMER FOR 40 MS.

DELAY

DELAY FOR 1 MILLISECONDS
DECREMENT TIMER
JUMP IF TIMER NOT EXPIRED
STOP THE READER ADVANCE
OUTPUT STOP COMMAND
INITIALIZE TIMER FOR 250 MS.

RI05:
DBED
E604
CAID05
3E27
D3ED
0628
RI07:
CALL
DCR
JNZ
MVI
OUT
MVI

CDB104
05
C22A05
3E25
D3ED
D6FA

B

RIll7
A,CMD
CNCTL
B,2513

RIl0 :
DBED
E602
C24905
CDB104
05
C23705
AF
37

•

IN
ANI
JNZ
CALL
DCR
JNZ

RIl0

XRA

A

STC

'"

CONST
RBR
RIl5
DELAY
B

INPUT READER STATUS
CHECK FOR RECEIVER DUFFER READY
YES - DATA IS READY
DELAY 1 MS
DECREMENT TIMER
JUMP IF TIMER NOT EXPIRED
ZERO A
SET CARRY INDICATING EOF

•

•

•

.

•

•

•

•

•

8080 MACRO ASSEMBLER, VER 2.4
ERRORS
80/10 MONITOR, VERSION 1.1, 1 NOVEMBER 1976
0547
0548
0549
0549
054B
054C
054D

•
o PAGE 36

POP
RET

B

RESTORE BC
RETURN TO CALLING ROUTINE

IN
ORA
POP
RET

CNIN
A
B

INPUT DATA CHARACTER
CLEAR CARRY
RESTORE BC
RETURN TO CALLING ROUTINE

C1
C9

•

RIl5:
DBEC
B7
C1
C9

,

,.**********************************************************************
054E
054E
0552
0556
055A
055E

i

COPYRT:
28432920
DB
31393736
2G494E54
454C2043
4F52511

'CC) 1976 INTEL CORP'

,

,.**********************************************************************
ORG
ORG

3C00
3C2E
3C2E
3C2E
3C2F
3C30
3C31
3C32
3C33
3C34
3C35
3C36
3C38
3C3A

00
00
00
00
100
00
00
IHl

0000
13000
IHl

MSTAK
ESAVE:
DSAVE:
CSAVE:
BSAVE:
FSAVE:
ll.5AVE:
LSAVE:
HSAVE:'
PSAVE:
SSAVE:
TEMP:
ORG

3C3D
i

3C3D

DATA
REGS
EQU
DB
DB
DB
DB
DB
DB
DB
DB
DW
DW
DB

$
0.
0
0
0

"
"
13

0

13

"

13

BRLOC

DS

USRER:

ORG TO REGISTER SAVE - STACK GOES IN HERE
START OF MONITOR STACK
E REGISTER SAVE LOCATION
D REGISTER SAVE LOCATION
C REGISTER SAVE LOCATION
B REGISTER SAVE LOCATION
FLAGS SAVE LOCATION
A REGISTER SAve LOCATION
L REGISTER SAVE LOCATION
H REGISTER SAVE LOCATION
PGM COUNTER SAVE LOCATION
USER STACK POINTER SAVE LOCATION
TEMPORARY MONITOR CELL
ORG TO USER BRANCH LOCATION

...J

BRANCH GOES IN HERE

END
NO PROGRAM ERRORS
8080 MACRO ASSEMBLER, JER 2.4
ERRORS"" '" PAGE 37
80/Hl MONITOR, VlnSION 1.1, 1 NOVEMBER 1976

•

.;

•

SYMBOL TABLE

*

01

A
B
BRTAB
CADR
CNIN
CONST
CROUT
DATA
DELI
ECH05
ESAVE
FRET
GCMD
GETNM
GNM10
GNM30
GTCHJ
HILO
ICM20
INVRT
LF
MCM05
MSTAK
ONEM'S
PEOL
PSAVE
RCM10
REGIS
RGA13
RI07
RSTTF
SCM05
SGNON
SSAVE
TEMP
TTYAD
VALDG
WCM15
XCM05
XCM25

*

02

*

03

*

04

*

05

'Han

0000
(BFA
03A6
0flEC
''''lED
01F3
3C00
0484
0202
3C2E
0210
008B
025B
11277
0299
~055

02AO
"OE3
00FF
000A
00F7
3C2E
0"83
0504
3C36
042F
0307
0323
052A
0327
0114
0395
3C38
3C3A
0027
0367
0463
0145
0196

•

ADRD
BRCHR
aSAVE
CI
CNOUT
COPYR
CSAVE
DCM05
DELAY
ECHle
ESC
FSAVE
GETCH
GHX05
GNM15
GO
H
HSAVE
ICM25
L
LSAVE
MCMD
NCMDS
PADR
PO
PSW
RCMD
REGDS
RGADR
RIl0
RSTU
SCM10
SO!1SG
STH05
TERM
TXBE
VALDL
WCM20
XCI110
XCM27

0lA8
001B
3C31
0105
0GEC
054E
3C30
0066
0481
"213
0018
3C32
0220
0220
0285
(HH18
0004
3C35
00E9
0005
3C34
00EF
0008
04C6
050F
6006
0406
02DF
0310
0537
0038
011F
001E
035B
001B
fHl04
0382
047B
0154
0197

•

ADROU
BREAK
BYTE
CMD
CNVBN
CPYRT
CTAB
DCM10
DSAVE
ECHO
EXIT
GCM05
GETCt-1
GHX10
GNM20
GTC03
HCHAR
ICI-105
ICMD
LE05
LSGNO
MODE
NEWLN
PBYTE
PRTY0
RBR
REG05
REGS
RI
RIl5
RTAB
SCM15
SP
STHF0
TROY
UPPER
WCM05
WCM25
XCM15
XCM30

*

*

•

01B1
01C2
0496
0025
01DF
03E3
63B8
006C
3C2F
01F9
0217
00All
002C
0245
028A
1103C
000F
00B4
00A9
04BC
0011
00CF
000F
04CF
007F
0'HJ2
02E2
3C2E
051C
0549
63CO
012F
0006
0330
0001
00FF
044B
0490
0161
019F

•

*

ASAVE
BRLOC
C
CNCTL
CO
CR
0

DCMD
E
ERROR
FALSE
GCM10
GETHX
GNM05
Gm125
GTC05
HIL05
IC~1Hl

INUST
LEAD
M
MSGL
NMOUT
PEOF
PRVAL
RCM05
REGl"
RGA05
RI05
RICH
RTABS
SCMD
SRET
STHLF
TRUE
USRBR
\'i'C!1l0
WCMD
XCM20
XCMD

3C33
3C3D
0001
0flED
01E8
0000
0002
0a5F
0003
0212
0F9C
00A6
0227
11262
0295
0049
02AF
00DB
02B2
04BA
0006
0023
02C2
04E6
0205
0412
02EC
0316
0510
0513
00133
010F
033B
0348
llF9F
3C3D
0460
0441
017F
0133

•

•

..,

•

•

•
•

•
•
•
..
•

•

\.()

r-

eo

~

lSI

~

N

...,

lSI

lSI

Q

G

~

~

r-i

r-i

it

it

it

it

it

it

..

it

•
•
•

•
•
•
•
•

•

APPENDIX F

•

ASCII TABLE
The INTELLEC~DS uses a 7-bit ASCII code, which is the normal 8-bit ASCII code with the parity (high
order) bit always reset .

•

GRAPHIC
OR CONTROL

•
•
•
.

•

NULL
SOM
EOA
EOM
EOT
WRU
RU
BELL
FE
H. Tab
Line Feed
V. Tab
Form
Return
SO
SI
DCO
X-On
Tape Aux. On
X-Off
Tape Aux. Off
Error
Sync
LEM
SO
S1
S2
S3
S4
S5
S6
S7

ASCII
(HEXADECIMAL)

00
01
02
03
04
05
06
07
08
09
OA
OB
OC
OD
OE
OF

GRAPHIC
OR CONTROL

ASCII
(HEXADECIMAL)

ACK
Alt. Mode
Rubout

7C
7D
7F
21
22
23
24
2(·.'
26
27
28
29
2A
2B
2C
2D
2E
2F
3A

!
"

#
$

%
&

,

(
)

*

+
,
-

10
11

/

12
13

,

14
15
16
17
18
19
1A
IB
lC

<

3C

=

3D

>

3E
3F
58
5C
5D
5E
5F
40
20
30

?
[

/
]
t

1D

+@

IE
IF

blank
0

F-l

3B

•
•

•

•
•
•
..
•

•

•

APPENDIX G

BINARY-DECIMAL-HEXADECIMAL CONVERSION TABLES

HEXADECIMAL ARITHMETIC
ADDITION TABLE

•
•
•
•

•

•

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

1
2
3

02
03
04

03
04
05

08
09
OA
OB
OC
OD

OB
OC
OD
OE
OF

OC
OD
OE
OF

OE
OF

OF

10

10

10

10

11

11
12

11
12

OC
OD
OE

OA
OB
OC
OD
OE
OF

OD
OE
OF

06
07
08

07
08
09
OA
OB
OC
OD
OE
OF

09
OA
OB

05
06
07
08
09
OA
OB
OC
OD
OE
OF

05
06
07
08
09
OA
OB
OC
OD
OE
OF

06
07
08

4
5
6

04
05
06
07
08
09

10

13

11

11
12

12

10

13

14

OE
OF

OF

10

11

10
11

11
12

12

14
15
16
17
18
19
lA
IB
lC

16
17
18
19
lA
IB
lC

11

13
14
15
16
17
18
19
lA
IB

15
16
17
18
19
lA
IB
lC

10

14
15
16
17
18
19

12
13
14
15
16
17
18
19
lA

1D

IE

7
8
9
A
B
C
D
E
F

09
OA
OB
OC
OD
OE
OF

OA
OB
OC
OD
OE
OF

10

11
12

09
OA
OB
OC
OD
OE
OF

10

11
12

10

13

10

10
11

11

12

13

10

12

13

11
12
13
14

12
13
14
15

13
14
15
16

14
15
16
17

14
15
16
17
18

13

-1314
15

1D

MUL TIPLICATION TABLE
1

2

3

4

5

6

7

8

9

A

B

C

0

E

F

2
3
4
5
6
7

04
06
08
OA
OC
OE

08
OC

OA
OF
14
19
IE

10

9
A
B
C
D
E
F

12
14
16
18
lA
lC
IE

OC
12
18
IE
24
2A
30
36
30
42
48

OE
15
lC
23
2A
31
38
3F
46
4D
54
5B
62
69

10

8

06
09
OC
OF
12
15
18
IB
IE
21
24
27
2A
2D

12
IB
24
2D
36
3F
48
51
SA
63
6C
75
7E
87

14
IE
28
32
3C
46
50
SA
64
6E
78
82
8C
96

16
21
2C
37
42
4D
58
63
6E
79
84
8F
9A
AS

18
24
30
3C
48
54
60
6C
78
84
90
9C
A8
B4

lA
27
34
41
4E
5B
68
75
82
8F
9C
A9
B6
C3

lC
2A
38
46
54
62
70
7E
8C
9A
A8
B6
C4
D2

IE
2D
3C
4B
SA
69
78
87
96
AS
B4

10

14
18
lC
20
24
28
2C
30
34
38
3C

23

28
2D
32
37
3C
41
46
48

4E
54
5A

18
20
28
30
38
40
48
50
58
60
68
70
78

G-l

C3
D2
El

POWERS OF TWO

o

I
2
4
9

•

I
2
3

1.0
0.5
0.25
O. I 25

16
32
64
128

4
5
6
7

0.062
0.031
0.015
O. 007

5
25
625
8 12

256
512
024
048

8
9
10
JJ

0.003
0.001
0.000
0.000

906
953
976
488

25
125
562
281

5
25

4
8
16
32

096
192
768

12
13
14
15

0.000
0.000
0.000
0.000

244
122
061
030

140
070
035
517

625
312
156
578

25
125

65
13 I
262
524

536
072
144
288

16
17
18
19

0.000
0.000
0.000
0.000

015
007
003
001

258
629
814
907

789
394
697
348

062
531
265
632

25
625
812

4
8

048
097
194
388

576
152
304
608

20
21
22
23

0.000
0.000
0.000
0.000

000
000
000
000

953
476
238
119

674
837
418
209

316
158
579
289

406
203
101
550

25
125
562
781

16
33
67
134

777
554
108
217

216
432
864
728

24
25
26
27

0.000
0.000
0.000
0.000

000
000
000
000

059
029
014
007

604
802
901
450

644
322
161
580

775
387
193
596

390 625
695 312
347 656
923 828

5
25
125

268
536
1 073
2 147

435
870
741
483

456
912
824
648

28
29
30
31

0.000
0.000
0.000
0.000

000
000
000
000

003
001
000
000

725
862
931
465

290
645
322
661

298
149
574
287

461
230
615
307

914
957
478
739

062
031
515
257

5
25
625
812

628
814
407
703

906
453
226
613

384

.11

•

5

2"5

•

4
8
J 7
34

294
589
179
359

967
934
869
738

296
592
184
368

32

33
34
35

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

232
116
058
029

830
415
207
103

643
321
660
S30

653
826
913
456

869
934
467
733

68
137
274
549

7\9
438
877
755

476
953
906
813

736
472
944
888

36
37
38
39

0.000
0.000
0.000
0.000

000 000
000 000
000000
000 000

014
007
003
001

551
275
637
818

916
957
978
989

228
614
807
403

366 851 806 640 625
183 425 903 320 312 5
09171295166015625
545 856 475 830 078 125

4
8

099
199
398
796

5II
023
046
093

726
255
51 I
022

776
552
104
208

40
41
42
43

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

909
454
227
113

494
747
373
688

701
350
675
837

772
886
443
721

928
464
232
616

237
118
059
029

915
957
478
739

039
519
759
379

062
521
765
882

25
625
812

17
35
70
140

592
184
368
737

186
372
744
488

044
088
177
355

416
832
664
328

44
45
46
47

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

056
028
014
007

843 418
421 709
210 854
105 427

860
430
715
357

808
404
202
601

014
007
003
001

869
434
717
858

941
844
422
711

406
970
485
242

25
703
351
675

281
562
125
251

474
940
899
799

976
953
906
813

710 656
421 213
842 624
685 248

48
49
50
51

0.000
0.000
0.000
0.000

000
000
000
000

000 000 003 552 713
000 000 001 776 866
000 000 000 888 178
000 000 000 444 089

678 800
839 499
419 700
209 850

500 929 355 621 337 890
259 464 677 810 668 945
125 232 338 905 334 472
062 616 169 452 667 236

625
312
656
32R

5
25
125

4
9
18
36

503
007
014
028

599
199
398
797

627
254
509
018

370
740
481
963

496
992
984
968

52
53
54
55

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

222
111
055
027

044
022
511
755

604
302
151
575

925
462
231
615

031
515
257
628

308
654
827
913

084
042
021
510

726
363
181
590

333
166
583
791

618
809
404
702

164
082
541
270

062
031
015
507

5
25
625
812

5

72
144
288
576

057
115
230
460

594
188
376
752

037
075
151
303

927
855
711
423

936
872
744
488

56
57
58
59

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

013
006
003
001

877
938
469
734

787
893
446
723

807
903
951
475

814
907
953
976

456
228
614
807

755
377
188
094

295
647
823
411

395
697
848
924

851
925
962
481

135
567
783
391

253
676
813
906

906
950
476
738

25
125
562
281

5
25

152
305
611
223

921
843
686
372

504
009
018
036

606
213
427
854

846
693
387
775

976
952
904
808

60
61
62
63

0.000
0.000
0.000
0.000

000
000
000
000

000
000
000
000

000
000
000
000

000
000
000
000

000 867
000 433
000 216
000 108

361 737
680 868
840 434
420 217

988
994
497
248

403
201
100
550

547
773
886
443

205
602
801
400

962
981
490
745

240 695
120 347
560 173
280 086

953
976
988
994

369
684
342
171

140
570
285
142

625
312
156
578

G-2

25
125
562
281

5
25

125
562
781

•

5
25

or

•

5
25
125

•

TABLE OF POWERS OF SIXTEEN10

•
1
17
281
4 503
72 057
152 921

4
68
099
592
474
599
594
504

16
268
294
719
511
186
976
627
037
606

•

++1

o

16
256
096
536
576
216
456
296
736
776
416
656
496
936
976

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

4
65
048
777
435
967
476
627
044
710
370
927
846

0.10000
0.62500
0.39062
0.24414
0.15258
0.95367
0.59604
0.37252
0.23283
0.14551
0.90949
0.56843
0.35527
0.22204
0.13877
0.86736

00000
00000
50000
06250
78906
43164
64477
90298
06436
91522
47017
41886
13678
46049
78780
17379

00000
00000
00000
00000
25000
06250
53906
46191
53869
83668
72928
08080
80050
25031
78144
88403

00000
00000
00000
00000
00000
00000
25000
40625
62891
51807
23792
14870
09294
30808
56755
54721

X 10
X 10- 1
X 10-2
X 10-3
X 10-4
X 10-6
X 10-7
X 10-8
X 10-9
X 10- 10
X 10- 12
X 10- 13
X 10- 14
X 10- 15
X 10- 16
X 10- 18

TABLE OF POWERS OF 1016

10"

n

o

2
17

1
F
98
5F5
3B9A
540B
4876

E8

D4A5

918
5AF3
8D7E
8652
4578
B6B3
2304

4E72
107 A
A4C6
6FC 1
5D8A
A764
89E8

•
"

•

n

"

•

•

16"

3
23
163
DEO
8AC7

A
64
3E8
2710
86AO
4240
9680
E100
CAOO
E400
E800
1000
AOOO
4000
3000
0000
0000
0000
0000

1
2

3
4
5
6
7

8
9

10
11
12
13
14
15
16
17
18
19

1.0000
0.1999
0.28F5
0.4189
0.68DB
OA7C5
0.10C7
0.lAD7
0.2AF3
0.44B8
0.6DF3
O.AFEB
0.1197
0.1025
0.2D09
0.480E
0.734A
0.B877
0.1272
0.lD83

G-3

0000
9999
C28F
374B
8BAC
AC47
F7AO
F29A
IDC4
2FAO
7F67
FFOB
9981
C268
370D
BE7B
CA5F
AA32
5DDI
C94F

0000
9999
5C28
C6A7
710C
IB47
B5ED
BCAF
6118
9B5A
SEFO
CB24
2DEA
4976
4257
9D58
6226
36A4
D243
B6D2

0000
999A
F5C3
EF9E
B290
8423
8D37
4858
73BF
52CC
EADF
AAFF
1119
81C2
3604
566D
FOAE
B449
ABAI
AC35

X

X
X

X
X
X

X
X

X
X
X

X
X
X
X

X
X

X

16-1
16-2
16-3
16-4
16-4
16-5
16-6
16-7
16-8
16-9
16-9
16- 10
16- 11
16- 12
16- 13
16- 14
16- 15
16- 15

HEXADECIMAL-DECIMAL INTEGER CONVERSION

The table below provides for direct conversions between hexadecimal integers in the range O-FFF and decimal integers in the
range 0-4095. For conversions oflarger integers, the table values may be added to the following figures:

oeooo

ODOoo
OEOoo
OF 000
10000
11000
12000
13000
14000
15000
16000
17000
18000
19000
1AOoo
1BOOO
1C 000
10000
IE 000
IF 000
0

0000
0016
0032
0048
0064
0080
0096
0112
0128
0144
0160
0176
oeo 0192
ODO 0208
OEO 0224
OFO 0240

000
010
020
030
040
050
060
070
080
090
OAO
OBO

1

2

3

0001
0017
0033
0049
0065
0081
0097
0113
0129
0145
0161
0177
0193
0209
0225
0241

0002
0018
0034
0050
0066
0082
0098
0114
0130
0146
0162
0178
0194
0210
0226
0242

0003
0019
0035
0051
0067
0083
0099
0115
0131
0147
0163
0179
0195
0211
0227
0243

4

0004
0020
0036
0052
0068
0084
0100
0116
0132
0148
0164
0180
0196
0212
0228
0244

131072
196608
262144
327680
393216
458752
524288
589824
655360
720896
786432
851968
917504
933040
1048576
2097152
3145728
4194304
5242880
6291456
7340032
8388608
9437184
10485760
11534336
12582912
13 631489
14680064
15728640
16777216
33554432

20000
30000
40000
50000
60000
70000
80000
90000
AOOOO
BOOOO
CO 000
00000
EO 000
FOOOO
100 000
200000
300000
400000
500000
600 000
700000
800000
900000
AOOOOO
BOO 000
COO 000
DOOOOO
EOO 000
FOOOoo
1 000 000
2000000

4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
65536
69632
73728
77 824
81920
86016
90112
94208
98304
102400
106496
110592
114638
118784
122880
126976

01000
02000
03000
04000
05000
06000
07000
08000
09000
OAOOO
OBOOO

DECIMAL

HEXADECIMAL

DECIMAL

HEXADECIMAL

5

6

7

8

0005
0021
0037
0053
0069
0085
0101
0117
0133
0149
0165
0181
0197
0213
0229
0245

0006
0022
0038
0054
0070
0086
0102
0118
0134
0150
0166
0182
0198
0214
0230
0246

0007
0023
0039
0055
0071
0087
0103
0119
0135
0151
0167
0183
0199
0215
0231
0247

0008
0024
0040
0056
0072
0088
0104
0120
0136
0152
0168
0184
0200
0216
0232
0248

9

0009
0025
0041
0057
0073
0089
0105
0121
0137
0153
0169
0185
0201
0217
0233
0249

A

0010
0026
0042
0058
0074
0090
0106
0122
0138
0154
0170
0186
0202
0218
0234
0250

•
•
•

B

C

D

E

F

0011
0027
0043
0059
0075
0091
0107
0123
0139
1055
0171
0187
0203
0219
0235
0251

0012
0028
0044
0060
0076
0092
0108
0124
0140
0156
0172
0188
0204
0220
0236
0252

0013
0029
0045
0061
0077
0093
0109
0125
0141
0157
0173
0189
0205
0221
0237
0253

0014
0030
0046
0062
0078
0094
0110
0126
0142
0158
0174
0190
0206
0222
0238
0254

0015
0031
0047
0063
0079
0095
0111
0127
0143
0159
0175
0191
2007
0223
0239
0255

•
•

•

HEXADECIMAL-DECIMAL INTEGER CONVERSION (continued)

•
•
•
•
•

•

0

1

2

100
110
120
130
140
150
160
170
180
190
lAO
IBO
1CO
100
lEO
1FO

0256
0272
0288
0304
0320
0336
0352
0368
0384
0400
0416
0432
0448
0464
0480
0496

0257
0273
0289
0305
0321
0337
0353
0369
0385
0401
0417
0433
0449
0465
0481
0497

0258
0274
0290
0306
0322
0338
0354
0370
0386
0402
0418
0434

0259
0275
0291
0307
0323
0339
0355
0371
0387
0403
0419
0435

200
210
220
230
240
250
260
270
280'
290
2AO
2BO
2CO
200
2EO
2FO

0512
0528
0544
0560

3

7

8

9

A

B

C

D

E

F

5

6

0260
0276
0292
0308
0324
0340
0356
0372
0388
0404
0420
0436
0450 0451 0452
0466 0467 0468
0482 0483 0484
0498 0499 0500

0261
0277
0293
0309
0325
0341
0357
0373
0389
0405
0421
0437
0453
0469
0485
0501

0262
0278
0294
0310
0326
0342
0358
0374
0390
0406
0422
0438
0454
0470
0486
0502

0263 0264 0265 0266 0267 0268 0269 0270 0271
0279 0280 0281 0282 0283 0284 0285 0286 0287
0295 0296 0297 0298 0299 0300 0301 0302 0303
0311 0312 0313 0314 0315 0316 0317 0318 0319
0327 0328 0329 0330 0331 0331 0333 0334 0335
0343 0344 0345 0346 0347 0348 0349 0350 0351
0359 0360 0361 0362 0363 0364 0365 0366 0367
0375 0376 0377 0378 0379 0380 0381 0382 0383
0391 0392 0393 0394 0395 0396 0397 0398 0399
0407 0408 0409 0410 0411 0412 0413 0414 0415
0423 0424 0425 0426 0427 0428 0429 0430 0431
0439 0440 0441 0442 0443 0444 0445 0446 0447
0455 0456 0457 0458 0459 0460 0461 0462 0463
0471 0472 0473 0474 0475 0476 0477 0478 0479
0487 0488 0489 0490 0491 0492 0493 0494 0495
0503 0504 0505 0506 0507 0508 0509 0510 0511

0513
0529
0545
0561

0514
0530
0546
0562

0515
0531
0547
0563

0516
0532
0548
0564

0517
0533
0549
0565

0518
0534
0550
0566

0519
0535
0551
0567

0576
0592
0608
0624
0640
0656
0672
0688
0704
0720
0736
0752

0577
0593
0609
0625
0641
0657
0673
0689
0705
0721
0738
0753

0578
0594
0610
0626

0580
0596
0612
0628

0642
0658
0674
0690
0706
0722
0738
0754

0579
0595
0611
0627
0643
0659
0675
0691
0707
0723
0739
0755

0644
0660
0676
0692
0708
0724
0740
0756

0581
0597
0613
0629
0645
0661
0677
0693
0709
0725
0741
0757

0582
0598
0614
0630
0646
0662
0678
0694

300
310
320
330
340
350
360
370
380
390
3AO
3BO

0768
0784
0800
0816
0832
0848
0864
0880
0896
0912
0928
0944

0769
0785
0801
0817
0833
0849
0865
0881
0897
0913
0929
0945

0770
0786
0802
0818
0834
0850
0866
0882
0898
0914
0930
0946

0771
0787
0803
0819
0835
0851
0867
0883
0899
0915
0931
0947

0772
0788
0804
0820
0836
0852
0868
0884
0900
0916
0932
0948

0773
0789
0805
0821
0837
0853
0869
0885
0901
0917
0933
0949

0774
0790
0806
0822
0838
0854
0870
0886
0902
0918
0934
0950

3CO
3DO
3EO
3FO

0960
0976
0992
1008

0961
0977
0993
1009

0962
0978
0994
1010

0963 0964 0965 0966
0979 0980 0981 0982
0995 0996 0997 0998
1011 1012 1013 1014

4

0520
0536
0552
0568

0521
0537
0553
0569

0522
0538
0554
0570

0584
0600
0616
0632
0647 0648
0663 0664
0679 0680
0695 0696
0710 0711 0712
0726 0727 0728
0742 0743 0744
0758 0759 0760

0585
0601
0617
0633
0649
0665
0681
0697
0713
0729
0745
0761

0586
0602
0618
0634
0650
0666
0682
0698
0714
0730
0746
0762

0583
0599
0615
0631

0523 0524
0539 0540
0555 0556
0571 0572
0587 0588
0603 0604
0619 0620
0635 0636
0651 0652
0667 0668
0683 0684
0699 0700
0715 0716
0731 0732
0747 0748
0763 0764

0525
0541
0557
0573

0526
0542
0558
0574

0527
0543
0559
0575

0589
0605
0621
0637
0653
0669
0685
0701

0590
0606
0622
0638
0654
0670
0686
0702
0718
0734
0750
0766

0591
0607
0623
0639
0655
0671
0687
0703
0719
0735
0751
0767
0783
0799
0815
0831
0847
0863
0879
0895
0911
0927
0943
0959
0975
0991
1007
1023

0717
0733
0749
0765

0775 0776 0777 0778 0779
0791 0792 0793 0794 0795
0807 0808 0809 0810 0811
0823 0824 0825 0826 0827
0839 0840 0841 0842 0843
0855 0856 0857 0858 0859
0871 0872 0873 0874 0875
0887 0888 0889 0890 0891
0903 0904 0905 0906 0907
0919 0920 0921 0922 0923
0935 0936 0937 0938 0939
0951 0952 0953 0954 0955

0780
0796
0812
0828
0844
0860
0876
0892
0908
0924
0940
0956

0781
0797
0813
0829
0845
0861
0877
0893
0909
0925
0941
0957

0782
0798
0814
0830
0846
0862
0878
0894
0910
0926
0942
0958

0967
0983
0999
1015

0972
0988
1004
1020

0973
0989
1005
1021

0974
0990
1006
1022

G-S

0968
0984
1000
1016

0969
0985
1001
1017

0970
0986
1002
1018

0971
0987
1003
1019

HEXADECIMAL-DECIMAL INTEGER CONVERSION (continued)

0

1

2

4

5

6

7

8

9

A

B

C

D

E

F

400
410
420
430
440
450
460
470
480
490
4AO
4BO

1024
1040
1056
1072
1088
1104
1120
1136
1152
1168
1184
1200

1025
1041
1057
1073
1089
1105
1121
1137
1153
1169
1185
1201

1026
1042
1058
1074

1027
1043
1059
1075

1028
1044
1060
1076
1092
1108
1124
1140

1029
1045
1061
1077
1093
1109
1125
1141
1157
1173
1189
1205

1030
1046
1062
1078
1094
1110
1126
1142

1032
1048
1064
1080
1096
1112
1128
1144

1033
1049
1065
1081
1097
1113
1129
1145

1034
1050
1066
1082
1098
1114
1130
1146

1035
1051
1067
1083
1099
1115
1131
1147

1038
1054
1070
1086
1102
1118
1134
1150

1039
1055
1071
1087
1103
1119
1135
1151

1160
1176
1192
1208
1224
1240
1256
1272

1161
1177
1193
1209
1225
1241
1257
1273

1162
1178
1194
1210

1166
1182
1198
1214

1167
1183
1199
1215

1226
1242
1258
1274

1163
1179
1195
1211
1227
1243
1259
1275

1036
1052
1068
1084
1100
1116
1132
1148
1163
1180
1196
1212
1228
1244
1260
1276

1037
1053
1069
1085
1101
1117
1133
1149
1165
1181
1197
1213

1219 1220 1221 1222
1235 1236 1237 1238
1251 1252 1253 1254
1267 1268 1269 1270

1031
1047
1063
1079
1095
1111
1127
1143
1159
1175
1191
1207
1223
1239
1255
1271

1090
1106
1122
1138
1154
1170
1186
1202

1091
1107
1123
1139
1155
1171
1187
1203

4CO
4DO
4EO
4FO

1216
1232
1248
1264

1217
1233
1249
1265

1218
1234
1250
1266

1229
1245
1261
1277

1230
1246
1263
1278

1231
1247
1263
1279

500
510
520
530
540
550
560
570
580
590
5AO
5BO
5CO
5DO
5EO
5FO

1280
1296
1312
1382
1344
1360
1376
1392
1408
1424
1440
1456
1472
1488
1504
1520

1281
1297
1313
1329
1345
1361
1377
1393
1409
1425
1441
1457
1473
1489
1505
1521

1282
1298
1314
1330
1346
1362
1378
1394
1410
1426
1442
1458

1284
1300
1316
1332
1348
1364
1380
1396
1412
1428
1444
1460
1476
1492
1508
1524

1285
1301
1317
1333
1349
1365
1381
1397
1413
1429
1445
1461
1477
1493
1509
1525

1286
1302
1318
1334
1350
1366
1382
1398
1414
1430
1446
1462
1478
1494
1510
1526

1287
1303
1319
1335
1351
1367
1383
1399
1415
1431
1447
1463
1479
1495
1511
1527

1288
1304
1320
1336
1352
1368
1384
1400
1416
1432
1448
1464
1480
1496
1512
1528

1289
1305
1321
1337
1353
1369
1385
1401
1417
1433
1449
1465

1474
1490
1506
1522

1283
1299
1315
1331
1347
1363
1379
1395
1411
1427
1443
1459
1475
1491
1507
1523

1290
1306
1322
1338
1354
1370
1386
1402
1418
1434
1450
1466
1482
1498
1514
1530

1291 1292 1293 1294 1295
1307 1308 1309 1310 1311
1323 1324 1325 1326 1327
1339 1340 1341 1342 1343
1355 1356 1357 1358 1359
1371 11372 1373 1374 1375
1387 1388 1389 1390 1391
1403 1404 1405 1406 1407
1419 1420 1421 1422 1423
1435 1436 1437 1438 1439
1451 1452 1453 1454 1455
1467 1468 1469 1470 1471
1483 1484 1485 1486 1487
1499 1500 1501 1502 1503
1515 1516 1517 1518 1519
1531 1532 1533 1534 1535

600
610
620
630
640
650
660
670
680
690
6AO
6BO
6C0
600
6EO
6FO

1536
1552
1568
1584
1600
1616
1632
1648
1664
1680
1696
1712
1728
1744
1760
1776

1537
1553
1569
1585
1601
1617
1633
1649
1665
1681
1697
1713
1729
1745
1761
1777

1538
1554
1570
1586
1602
1618
1634
1650
1666
1682
1698
1714
1730
1746
1762
1778

1539
1555
1571
1587
1603
1619
1635
1651
1667
1683
1699
1715
1731
1747
1763
1779

1540
1556
1572
1588
1604
1620
1636
1652
1668
1684
1700
1716
1732
1748
1764
1780

1541
1557
1573
1589
1605
1621
1637
1653
1669
1685
1701
1717
1733
1749
1765
1781

1542
1558
1574
1590
1606
1622
1638
1654
1670
1686
1702
1718
1734
1750
1766
1782

1543 1544 1545 1546 1547 1548 1549 1550 1551
1559 1560 1561 1562 1563 1564 1565 1566 1567
1575 1576n 1577 1578 1579 1580 1581 1582 1583
1591 1592 1593 1594 1595 1596 1597 1598 1599
1607 1608 1609 1610 1611 1612 1613 1614 1615
1623 1624 1625 1626 1627 1628 1629 1630 1631
1639 1640 1641 1642 1643 1644 1645 1646 1647
1655 1656 1657 1658 1659 1660 1661 1662 1663
1671 1672 1673 1674 1675 1676 1677 1678 1679
1687 1688 1689 1690 1691 1692 1693 1694 1695
1703 1704 1705 1706 1707 1708 1709 1710 1711
1719 1720 1721 1722 1723 1724 1725 1726 1727
1735 1736 1737 1738 1739 1740 1741 1742 1743
1751 1752 1753 1754 1755 1756 1757 1758 1759
1767 1768 1769 1770 1771 1772 1773 1774 1775
1783 1784 1785 1786 1787 1788 1789 1790 1791

3

1156
1172
1188
1204

1158
1174
1190
1206

G-6

1481
1497
1513
1529

•
•

•
•
•
.

•

HEXADECIMAL·DECIMAL INTEGER CONVERSION (continued)

•
•
•
•
•

•

9

A

B

C

D

E

F

1801
1817
1833
1849
1865
1881
1897
1913

1802
1818
1834
1850
1866
1882
1898
1914

1803
1819
1835
1851
1867
1883
1899
1915

1930
1946
1962
1978

1805
1821
1837
1853
1869
1885
1901
1917
1933
1949
1965
1981

1806
1822
1838
1854
1870
1886
1902
1918

1929
1945
1961
1977

1804
1820
1836
1852
1868
1884
1900
1916
1932
1948
1964
1980

1993
2009
2025
2041

1994
2010
2026
2042

1934
1931
1950
1947
1963
1966
1982
1979
1995 1996 1997 1998
2011 2012 2013 2014
2027 2028 2029 2030
2043 2044 2045 2046

1807
1823
1839
1855
1871
1887
1903
1919
1935
1951
1967
1983
1999
2015
2031
2047

2056
2072
2088
2104

2057
2073
2089
2015

2058
2074
2090
2106

2059
2075
2091
2107

2119
2135
2151
2167
2183
2199
2215
2231
2247
2263
2279
2295

2120
2136
2152
2168
2184
2200
2216
2232
2248
2264
2280
2296

2121
2137
2153
2169
2185
2201
2217
2233
2249
2265
2281
2297

2122
2138
2154
2170
2186
2202
2218
2234
2250
2266
2282
2298

2123
2139
2155
2171
2187
2203
2219
2235
2251
2267
2283
2299

2311
2327
2343
2359
2375
2391
2407
2423

2312
2328
2344
2360

2313
2329
2345
2361

2376
2392
2408
2424
2439 2440
2455 2456
2471 2472
2487 2488
2501 2502 2503 2504
2517 2518 2519 2520
2533 2534 2535 2536
2549 2550 2551 2552

2377
2393
2409
2425
2441
2457
2473
2489

2314
2330
2346
2362
2378
2394
2410
2426
24422458
2474
2490
2506
2522
2538
2554

2315 2316 2317 2318 2319
2331 2332 2333 2334 2335
2347 2348 2349 2350 2351
2363 2364 2365 2366 2367
2379 2380 2381 2382 2383
2395 2396 2397 2398 2399
2411 2412 2413 2414 2415
2427 2428 2429 2430 2431
2443 2444 2445 2446 2447
2459 2460 2461 2462 2463
2475 2476 2477 2478 2479
2491 2492 2493 2494 2495
2507 2508 2509 2510 2511
2523 2524 2525 2526 2527
2539 2540 2541 2542 2543
2555 2556 2557 2558 2559

0

1

2

3

4

5

6

7

700
710
720
730
740
750
760
770
780
790
7AO
7BO

1792
1808
1824
1840
1856
1872
1888
1904

1793
1809
1825
1841
1857
1873
1889
1905

1794
1810
1826
1842
1858
1874
1890
1906

1795
1811
1827
1843
1859
1875
1891
1907

1796
1812
1828
1844
1860
1876
1892
1908

1921
1937
1953
1969

1922
1938
1954
1970

1923
1939
1955
1971

7CO
7DO
7EO
7FO

1984
2000
2016
2032

1985
2001
2017
2033

1986
2002
2018
2034

1987
2003
2019
2035

1924
1940
1956
1972
1988
2004
2020
2036

1798
1814
1830
1846
1862
1878
1894
1910
1926
1942
1958
1974
1990
2006
2022
2038

1799
1815
1831
1847
1863
1879
1895
1911

1920
1936
1952
1968

1797
1813
1829
1845
1861
1877
1893
1909
1925
1941
1957
1973
1989
2005
2021
2037

1800
1816
1832
1848
1864
1880
1896
1912
1927 1928
1943 1944
1959 1960
1975 1976
1991 1992
2007 2008·
2023 2024
2039 2040

800
810
820
830

2048
2064
2080
2096

2049
2065
2081
2097

2051 2502
2067 2068
2083 2084
2099 2100

2053
2069
2085
2101

2054
2070
2086
2102

2055
2071
2087
2103

840
850
860
870
880
890
8AO
8BO
8CO
8DO
8EO
8FO

2112
2128
2144
2160
2176
2192
2208
2224
2240
2256
2272
2288

2050
2066
2082
2098
2113 2114
2129 2130
2145 2146
2161 2162
21777 2178
2193 2194
2209 2210
2225 2226
2241 2242
2257 2258
2273 2274
2289 2290

2115
2131
2147
2163
2179
2195
2211
2227
2243
2259
2275
2291

2116
2132
2148
2164
2180
2196
2212
2228
2244
2260
2276
2292

2117
2133
2149
2165
2181
2197
2213
2229
2245
2261
2277
2293

2118
2134
2150
2166
2182
2198
2214
2230
2246
2262
2278
2294

900
910
920
930
940
950
960
970
980
990
9AO
9BO

2304
2320
2336
2352
2368
2384
2400
2416
2432
2448
2464
2480

2305
2321
2337
2353

2306
2322
2338
2354

2307
2323
2339
2355

2308
2324
2340
2356

2310
2326
2342
2358

2369
2385
2401
2417
2433
2449
2465
2481

2370
2386
2402
2418
2434
2450
2466
2482

2371
2387
2403
2419
2435
2451
2467
2483

9CO
9DO
9EO
9FO

2496
2512
2528
2544

2497
2513
2529
2545

2498
2514
2530
2546

2499
2515
2531
2547

2372
2388
2404
2420
2436
2452
2468
2484
2500
2516
2532
2548

2309
2325
2341
2357
2373
2389
2405
2421
2437
2453
2469
2485

2374
2390
2406
2422
2438
2454
2470
2486

G-7

8

2505
2521
2537
2553

2060
2076
2092
2108
2124
2140
2156
2172
2188
2204
2220
2236
2252
2268
2284
2300

2061
2077
2093
2109

2062
2078
2094
2110

2063
2079
2095
2111

2125
2141
2157
2173
2189
2205
2221
2237
2253
2269
2285
2301

2126
2142
2158
2174
2190
2206
2222
2238
2254
2270
2286
2302

2127
2143
2159
2175
2191
2207
2223
2239
2255
2271
2287
2303

HEXADECIMAL-DECIMAL INTEGER CONVERSION (continued)

2573
2589
2605
2621
2637
2653
2669
2685
2701
2717
2733
2749

2574
2590
2606
2622
2638
2654
2670
2686
2702
2718
2734
2750

2575
2591
2607
2623
2639
2655
2671
2687

B

2567
2583
2599
2615
2631
2647
2663
2679
2695
2711
27272
2743
2759
2775
2791
2807

2568
2584
2600
2616
2632
2648
2664
2680
2696
2712
2728
2744

2569
2585
2601
2617
2633
2649
2665
2681
2697
2713
2729
2745

2570
2586
2602
2618
2634
2650
2666
2682
2698
2714
2730
2746

2571
2587
2603
2619
2635
2651
2667
2683
2699
2715
2731
2747

2760
2776
2792
2808

2761
2777
2793
2809

2762
2778
2794
2810

2763 2764 2765 2766 2767
2779 2780 2781 2782 2783
2795 2796 2797 2798 2799
2811 2812 2813 2814 2815

2822
2838
2854
2870
2886
2902
2918
2934
2950
2966
2982
2998
3014
3030
3046
3062

2823
2839
2855
2871
2887
2903
2919
2935
2951
2967
2983
2999
3015
3031
3047
3063

2824
2840
2856
2872
2888
2904
2920
2936
2952
2968
2984
3000
3016
3032
3048
3064

2825
2841
2857
2873
2889
2905
2921
2937
2953
2969
2985
3001
3017
3933
3049
3065

2826
2842
2858
2874
2890
2906
2922
2938
2954
2970
2986
3002
3018
3034
3050
3066

2827
2843
2859
2875
2891
2907
2923
2939
2955
2971
2987
3003
3019
3035
3051
3067

2828
2844
2860
2876
2892
2908
2924
2940
2956
2972
2988
3004
3020
3036
3052
3068

2829
2845
2861
2877
2893
2909
2925
2941
2957
2973
2989
3005
3021
3037
3053
3069

2830
2846
2862
2878
2894
2910
2926
2942
2958
2974
2990
3006
3022
3038
3054
3070

2831
2847
2863
2879
2895
2911
2927
2943
2959
2975
2991
3007
3023
3039
3055
3071

3078
3094
3110
3126
3142
3158
3174
3190
3206
3222
3238
3254
3270
3286
3302
3318

3079
3095
3111
3127
3143
3159
3175
3191
3207
3223
3239
3255
3271
3287
3303
3319

3080
3096
3112
3128
3144
3160
3176
3192
3208
3224
3240
3256
3272
3288
3304
3320

3081
3097
3113
3129
3145
3161
3177
3193
3209
3225
3241
3257
3273
3289
3305
3321

3082
3098
3114
3130
3146
3162
3178
3194
3210
3226
3242
3258
3274
3290
3306
3322

3083
3099
3115
3131
3147
3163
3179
3195
3211
3227
3243
3259
3275
3291
3307
3323

3084
3100
3116
3132
3148
3164
3180
3196
3212
3228
3244
3260
3276
3292
3308
3324

3085
3101
3117
3133
3149
3165
3181
3197
3213
3229
3245
3261
3277
3293
3309
3325

3086
3102
3118
3134
3150
3166
3182
3198
3214
3230
3246
3262
3278
3294
3310
3326

3087
3103
3119
3135
3151
3167
3183
3199
3215
3231
3247
3263
3279
3295
3311
3327

3

4

5

6

2560
2576
2592
2608
2624
2640
2656
2672
2688
2704
2720
2736

2562
2578
2594
2610
2626
2642
2658
2674
2690
2706
2722
2738
2754
2770
2786
2802

2563
2579
2595
2611
2627
2643
2659
2675
2691
2707
2723
2739
2755
2771
2787
2803

2564
2580
2596
2612
2628
2644
2660
2676
2692
2708
2724
2740
2756
2772
2788
2804

2565
2581
2597
2613
2629
2645
2661
2677
2693
2709
2725
2741

AEO 2784
AFO 2800

2561
2577
2593
2609
2625
2641
2657
2673
2689
2705
2721
2737
2753
2769
2785
2801

2757
2773
2789
2805

2566
2582
2598
2614
2630
2646
2622
2678
2694
2710
2726
2742
2758
2774
2790
2806

BOO
BlO
B20
B30
B40
B50
B60
B70
B80
B90
BAO
BBO
BCO
BDO
BEO
BFO

2816
2832
2848
2864
2880
2896
2912
2928
2944
2960
2976
2992
3008
3024
3040
3056

2817
2833
2849
2865
2881
2897
2913
2929
2945
2961
2977
2993
3009
3025
3041
3057

2818
2834
2850
2866
2882
2898
2914
2930
2946
2962
2978
2994
3010
3026
3042
3058

2819
2835
2851
2867
2883
2899
2915
2931
2947
2963
2979
2995
3011
3027
3043
3059

2820
2836
2852
2868
2884
2900
2916
2932
2948
2964
2980
2996
3012
3028
3044
3060

2821
2837
2853
2869
2885
2901
2917
2933
2949
2965
2981
2997
3013
3029
3045
3061

COO
ClO
C20
C30
C40
C50
C60
C70
C80
C90
CAO
CBO
CCO
COO
CEO
CFO

3072
3088
3104
3120
3136
3152
3168
3184
3200
3216
3232
3248
3264
3280
3296
3312

3073
3089
3105
3121
3137
3153
3168
3185
3201
3217
3233
3249
3265
3281
3297
3313

3074
3090
3106
3122
3138
3154
3170
3186
3202
3218
3234
3250
3266
3282
3298
3314

3075
3091
3107
3123
3139
3155
3171
3187
3203
3219
3235
3251
3267
3283
3299
3315

3076
3092
3108
3124
3140
3156
3172
3188
3204
3220
3236
3252
3268
3284
3300
3316

3077
3093
3109
3125
3141
3157
3173
3189
3205
3221
3237
3253
3269
3285
3301
3317

2752

F

A

2

ADO 2768

E

9

1

AOO
A10
A20
A30
A40
A50
A60
A70
A80
A90
AAO
ABO
ACO

D

8

0

7

G-8

C

2572
2588
2604
2620
2636
2652
2668
2684
2700
2716
2732
2748

•

2703
2719
2735
2751

•
•
•
•

.

•

HEXADECIMAL-DECIMAL INTEGER CONVERSION (continued)

•
•
•
•
•

0

1

2

3

4

5

6

DOO
D10
D20
D30

3328
3344
3360
3376

3329
3345
3361
3377

3330
3346
3362
3378

3332
3348
3364
3380

3333
3349
3365
3381

3334
3350
3366
3382

D40
D50
D60
D70
D80
D90
DAO
DBO
OCO
CCO
DEO
DFO

3392
3408
3424
3440
3456
3472
3488
3504
3520
3536
3552
3568

3393
3409
3425
3441
3457
3473
3489
3505
3521
3537
3553
3569

3394
3410
3426
3442
3458
3474
3490
3506
3522
3538
3554
3570

3331
3347
3363
3379
3395
3411
3427
3443
3459
3475
3491
3507
3523
3539
3555
3571

3396
3412
3428
3444
3460
3476
3492
3508
3524
3540
3556
3572

3397
3413
3429
3445
3461
3477
3493
3509
3525
3541
3557
3573

3398
3414
3430
3446
3462
3478
3494
3410
3526
3542
3558
3574

EOO
E10
E20
E30

3584
3600
3616
3632

3586
3602
3618
3634
3650
3666
3682
3698
3714
3730
3746
3762
3778
3794
3810
3826
3842
3858
3874
3890

3589
3605
3621
3637
3653
3669
3685
3701
3717
3733
3749
3765

3590
3606
3622
3638

3648
3664
3680
3696
3712
3728
3744
3760
3776
3792
3808
3824
3840
3856
3872
3888

3587
3603
3619
3635
3651
3667
3683
3699
3715
3731
3747
3763

3588
3604
3620
3636

E40
E50
E60
E70
E80
E90
EAO
EBO

3585
3601
3617
3633
3648
3665
3681
3697
3713
3729
3745
3761
3777
3793
3809
3825
3841
3857
3873
3889

3904
3920
3936
3952
3968
3984
4000
4016
4032
4048
4064
4080

3905
3921
3937
3953
3969
3985
4001
4017
4033
4049
4065
4081

3906
3922
3938
3954
3970
3986
4002
4018
4034
4050
4066
4082

ECO
EDO
EEO
EFO
FOO
FlO
F20
F30
F40
F50
F60
F70
F80
F90
FAO
FBO
FCO
FDO
FEO
FFO

3652
3668
3684
3700
3716
3732
3748
3764
3779 3780
3795 3796
3811 3812
3827 3828
3843 3844
3859 3860
3875 3876
3891 3892
3907
3923
3939
3955

3908
3924
3940
3956
3971 3972
3987 3988
4003 4004
4019 4020
4035 4036
4051 4052
4067 4068
4083 4084

3781
3797
3813
3829
3845
3861
3877
3893

3654
3670
3686
3702
3718
3734
3750
3766
3782
3798
3814
3030
3846
3862
3878
3894

3909
3925
3941
3957

3910
3926
3942
3958

3973
3989
4005
4021
4037
4053
4069
4085

3974
3990
4006
4022
4038
4054
4070
4086

C

D

E

F

3335 3336 3337 3338 3339
3351 3352 3353 3354 3355
3367 3368 3369 3370 3371
3383 3384 3385 3386 3387
3399 3400 3401 3402 3403
3415 3416 3417 3418 3419
3431 3432 3433 3434 3435
3447 3448 3449 3450 3451
3463 3464 3465 3466 3467
3479 3480 3481 3482 3483
3495 3496 3497 3498 3499
3511 3512 3513 3514 3515
3527 3528 3529 3530 3531
3543 3544 3545 3546 3547
3559 3560 3561 3562 3563
3575 3576 3577 3578 3579

3340
3356
3372
3388

3341
3357
3373
3389

3342
3358
3374
3390

3404
3420
3436
3452
3468
3484
3500
1516
3532
3548
3564
3580

3405
3421
3437
3453
3469
3485
3501
35]7
3533
3549
3565
3581

3406
3422
3438
3454
3470
3486
3502
3518
3534
3550
3566
3582

3343
3359
3375
3391
3407
3423
3439
3455
3471
3487
3503
3519
3535
3551
3567
3583

3591
3607
3623
3639
3655
3671
3687
3703
3719
3735
3751
3767

3596
3612
3628
3644

3597
3613
3629
3645

3598
3614
3630
3646

3661
3677
3693
3709
3725
3741
3757
3773

3662
3678
3694
3710
3726
3742
3758
3774

3787
3803
3819
3835
3851
3867
3883
3899

3660
3676
3692
3708
3724
3740
3756
3772
3788
3804
3820
3836
3852
3868
3884
3900

3599
3615
3631
3647
3663
3679
3695
3711
3727
3743
3759
3775

3789
3805
3821
3837
3853
3869
3885
3901

3790
3806
3822
3838
3854
3870
3886
3902

3791
3807
3823
3839
3855
3871
3887
3903

3911 3912 3913 3914 3915
3927 3928 3929 3930 3931
3943 3944 3945 3946 3947
3959 3960 3961 3962 3963
3975 3976 3977 3978 3979
3991 3992 3993 3994 3995
4007 4008 4009 4010 4011
4023 4024 4025 4026 4027
4039 4040 4041 4042 4043
4055 4056 4057 4058 4059
4071 4072 4073 4074 4075
4087 4088 4089 4090 4091

3916
3932
3948
3964
3980
3996
4012
4028
4044
4060
4076
4092

3917
3933
3949
3965

3918
3934
3950
3966
3982
3998
4014
4030

3919
3935
3951
3967
3983
3999
4015
4031

4046
4062
4078
4094

4047
4063
4079
4095

8

7

3783
3799
3815
3831
3847
3863
3879
3895

3592
3608
3624
3640
3656
3672
3688
3704
3720
3736
3752
3768
3784
3800
3816
3832
3848
3865
3880
3896

G-9

9

A

B

3593
3609
3625
3641
3657
3673
3689
3705

3594
3610
3626
3642
3658
3674
3690
3706

3595
3611
3627
3643
3659
3675
3691
3070

3721
3737
3753
3769
3785
3801
3817
3833
3849
3865
3881
3897

3722
3738
3754
3770
3786
3802
3818
3834
3850
3866
3882
3898

3723
3739
3755
3771

3981
3997
4013
4029
4045
4061
4077
4093

•
.,

•
•
•
,

•

APPENDIX H
TELETYPEWRITER MODI FICATIONS

•
H·1. INTRODUCTION
This appendix provides information required to
modify a Model ASR-33 Teletypewriter for use with
certain Intel SBC 80 computer systems.

H·2. INTERNAL MODIFICATIONS
WARNING

•

Hazardous voltages are exposed when the
top cover of the teletypewriter is removed.
To prevent accidental shock, disconnect the
teleprinter power cord before proceeding
beyond this point.
Remove the top cover and modify the teletypewriter
as follows:

•
•

a. Refer to figure H-4 and connect a wire (Wire 'A')
from relay circuit card to terminal L2 on mode
switch. (See figure H-6.)
b. Disconnect brown wire shown in figure H -7 from
plastic connector. Connect this brown wire to terminal12 on mode switch. (Brown wire will have to
be extended.)
c. Refer to figure H-4 and connect a wire (Wire 'B')
from relay circuit board to terminal Lion mode
switch.

a. Remove blue lead from 750-ohm tap on current
source register; reconnect this lead to 1450-ohm
tap. (Refer to figures H-l and H-2.)

H·3. EXTERNAL CONNECTIONS

b. On terminal block, change two wires as follows to
create an internal full-duplex loop (refer to figures
H-l and H-3):

Connect a two-wire receive loop, a two-wire send
loop, and a two-wire tape reader control loop to the
external device as shown in figure H-4. The external
connector pin numbers shown in figure H-4 are for
interface with an RS232C device.

1. Remove brown/yellow lead from terminal 3;
reconnect this lead to terminal 5.
2. Remove white/blue lead from terminal 4;
reconnect this lead to terminal 5.
c. On terminal block, remove violet lead from
terminal 8; reconnect this lead to terminal 9. This
changes the receiver current level from 60 rnA to
20 rnA.
A relay circuit card must be fabricated and connected
. to the paper tape reader driver circuit. The relay circuit card to be fabricated requires a relay, a diode, a
thyractor, a small 'vector' board for mounting the
components, and suitable hardware for mounting the
assembled relay card.

•

substituted for tne thyractor.) After the relay circuit
card has been assembled, mount it in position as
shown in figure H-5. Secure the card to the base plate
using two self-tapping screws. Connect the relay circuit to the distributor trip magnet and mode switch as
follows:

A circuit diagram of the relay circuit card is included
in figure H-4; this diagram also includes the part
numbers of the relay, diode, and thyractor. (Note
that a 470-ohm resistor and a 0.1 /-tF capacitor may be

H·4.

sec 530 TTY ADAPTER

The SBC 530, which converts RS232C signal levels to
an optically isolated 20 rnA current loop interface,
provides signal translation for transmitted data,
received data, and a paper tape reader relay. The
SBC 530 interfaces an Intel SBC 80 computer system
to a teletypewriter as shown in figure H-8.
The SBC 530 requires + 12V at 98 rnA and -12V at
98 rnA. An auxiliary supply must be used if the SBC
80 system does not supply this power. A schematic
dia.gram of the SBC 530 is supplied with the unit. The
following auxiliary power connector (or equivalent)
must be procured by the user:
Connector, Molex 09-50-7071
Pins, Molex 08-50-0106
Polarizing Key, Molex 15-04-0219

Teletypewriter Modifications

MODE
SWITCH

•

TOP VIEW

MOUNT
CIRCUIT
CARD
KEYBOARD

TAPE
READER

CAPACITOR

?RINTER UNIT
TAPE
PUNCH

CURRENT
SOURCE
RESISTOR

DISTRIBUTOR
TRIP MAGNET
ASSEMBLY

POWER
SUPPLY

FloCARD

lQJ

TERMINAL
BLOCK

00TO~

TELETYPE MODEL 33TC

Figure 0-1. Teletype Component layout

•
•
•
•

Figure 0-2. Current Source Resistor

Figure 0-3. Terminal Block

Teletypewriter Modifications

•

TERMINAL BLOCK 151411

20MA

VIO
25-PIN
EXTERNAL
CONNECTOR

9
VEL

-- -- ---- -

8

BLK!GRN
WHT!BRN
RED!GRN
WHT!VEL
WHT/BLK
WHT!BLU

7
RECEIVE

6
5

~

FULL DUPLEX

BRN/VEL

4

GRN

SEND

•

60MA

- ------",

RED

)--+---~__---I-_-+-.....::::.30tt~J----I-_-_-_-GRY

- - -- -

- -

- -

WHT/RED
BLK
BLK

2

WHT
WHT

117VAC
CONNECTOR

0---,I

DISTRIBUTOR TRIP
MA.GNET

WIRE'A'

•

TAPE READER
CONTROL

L

•

0_11~F

*ALTERNATE CONTACT PROTECTION
.---_ _---=C:.;,.IRCUIT

...--l

•

'--""""""I'v-~

1

470 .0 'hW

TO.1200V

I
IJR-1005

I

{2VDC,600.o

co I L

~~RMAL CONTACTS
OPEN

lli.5.!-~ c:!!!fId!LC~

_

Figure 8-4. Teletypewritl~r Modifications

470.0

117 VAC
COMMON

Teletypewriter Modifications

•
•

•

Figure H -7. Distributor Trip Magnet

J1
FROM
SERIAL IN/OUT
PORT

J

.I

;

CINCH DB·25S

P3

530 SBC
TTY ADAPTER

h
J3

~

L-_ _ _...:J;.:2_ _ _----'

Figure H-8. TTY Adapter Cabling

TO TERMINAL BLOCK
(SEE FIGURES H·3 AND H.4)

•

CINCH DB·25P

•
f

•

System 80110 Hardware Reference Manual
98003168

•

REQUEST FOR READER'S COMMENTS

The Microcomputer Division Technical Publications Department attempts to provide documents that meet the needs of all
Intel product users. This form lets you participate directly in the documentation process.

,

•
•
•

Please restrict your comments to the usability, accuracy, readability, organization, and completeness of this document.
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