9800722 03 The 8086 Family Users Manual Oct79

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The
8086Family

Users Manual
October1979

© Intel Corporation 1978, 1979
9800722-03/ $7.50

The
8086 Family

Users Manual
October 1979

Additional copies of this manual or other Intel literature may be obtained from:
Literature Department

Intel Corporation
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Santa Clara, CA 95051
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Table of Contents
CHAPTERl
INTRODUCTION

PAGE
Manual Organization ...................... " I-I
8086 Family Architecture. . . . . . . . . . . . . . . . . . . .. I-I
Functional Distribution. . . .. . . .. .. . . .. . . . . . .. I-I
Microprocessors. . . . . . . . . . . . . . . . . . . . . . . . .. 1-2
Interrupt Controller ....................... 1-3
Bus Interface Components. . .. . . . . . .. . . .. .. 1-3
Multiprocessing.. . . . . . . . . . . . . . . .. . ... . .. . .. 1-3
Bus Organization. . . . . . . . . . . . . . . . . . . . . . . . . .. 1-4
Local Bus ............................... 1-4
System Bus ............ , ....... " ...... " 1-5
. Processing Modules. . . . . . . . . . . . . . . . . . . . . .. 1-6
Bus Implementation Examples. . . . . . . . . . . . .. 1-6
Development Aids. . . . . . . . . . . . .. . . . .. . .. . ... 1-12

PAGE
8289 Bus Arbiter .......................... 2-22
Processor Control and Monitoring . . . . . . . . . .. 2-22
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-22
External Interrupts .... . . . . . . . . . . . . . . . . .. 2-22
Internal Interrupts. . . . . . . . . . . . . . . . . . . . . .. 2-24
Interrupt Pointer Table. . . . . . . . . . . . . . . . . .. 2-25
Interrupt Procedures. . . . . . . . . . . . . . . . . . . .. 2-26
Single-Step (Trap) Interrupt. . . . . . . . . . . . . .. 2-28
Breakpoint Interrupt. . . . . . . . . . . . . . . . . . . .. 2-28
System Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-29
Instruction Queue Status. . . . . . . . . . . . . . . . . . .. 2-29
Processor Halt. . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-29
Status Lines ............................ " 2-30
Instruction Set ............................. 2-30
Data Transfer Instructions. . . . . . . . . . . . . . . . .. 2-31
General Purpose Data Transfers ......... " 2-31
Address Object Transfers. . . . . . . . . . . . . . . .. 2-32
Flag Transfers ................... . . . . . .. 2-32·
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . .. 2-33
Arithmetic Data Formats. . . . . . . . . . . . . . . .. 2-33
Arithmetic Instructions and Flags . . . . . . . . .. 2-34
Addition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-35
Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-36
Multiplication. . . . . . . . . . . . . . . . . . . . . . . . . .. 2-36
Division .......................... '" . " 2-37
Bit Manipulation Instructions . . . . . . . . . . . . . .. 2-38
Logical ......................... . . . . . .. 2-38
Shifts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-39
Rotates .............................. " 2-39
String Instructions. . . . . . . . . . . . . . . . . . . . . . . .. 2-40
Program Transfer Instructions. . . . . . . . . . . . . .. 2-43
Unconditional Transfers. . . . . . . . . . . . . . . . .. 2-43
Conditional Transfers. . . . . . . . . . . . . . . . . . .. 2-45
Iteration Control. . . . . . . . . . . . . . . . . . . . . . .. 2-45
Interrupt Instructions. . . . . . . . . . . . . . . . . . .. 2-46
Processor Control Instructions .............. 2-47
Flag Operations ......................... 2-47
External Synchronization. . . . . . . . . . . . . . . .. 2-48
No Operation. . . . . . . . . . . . . . . . . . . . . . . . . .. 2-48
Instruction Set Reference Information. . . . . . .. 2-48
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . .. 2-68
Register and Immediate Operands. . . . . . . . . . .. 2-68
Memory Addressing Modes ............... " 2-68
The Effective Address. . . . . . . . . . . . . . . . . . .. 2-68
Direct Addressing ....................... 2-69
Register Indirect Addressing ............. " 2-69
Based Addressing. . . . . . . . . . . . . . . . . . . . . . .. 2-70
Indexed Addressing. . . . . . . . . . . . . . . . . . . . .. 2-70

CHAPTER 2
THE 8086 AND 8088 CENTRAL
PROCESSING UNITS
Processor Overview. . . . . . . . . . . . . . . . . . . . . . . . .. 2-1
Processor Architecture. . . . . . . . . . . . . . . . . . . . . .. 2-3
Execution Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
Bus Interface Unit. . . . . . . . . . . . . . . . . . . . . . . . .. 2-5
General Registers. . . . . . . . . . . . . . . .. . . . . . . . . .. 2-6
Segment Registers ........................ " 2-7
Instruction Pointer ......................... 2-7
Flags ..................................... 2-7
8080/8085 Register and Flag Correspondence. .. 2-8
Mode Selection ........ , ......... '" ........ 2-8
Memory ............................. ; .... " 2-8
Storage Organization ........................ 2-8
Segmentation . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-10
Physical Address Generation. . . . . . . . . . . . . . .. 2-11
DynamicallyRelocatable Code .............. 2-13
Stack Implementation ...................... 2-14
Dedicated and Reserved Memory Locations .... 2-14
8086/8088 Memory Access Differences ........ 2-15
Input/Output .............................. 2-15
Input/Output Space ....................... 2-16
Restricted 110 Locations ................... 2-16
8086/8088 Memory Access Differences .. , ..... 2-16
Memory-Mapped I/O ...................... 2-16
Direct Memory Access. . . . . . . . . . . . . . . . . . . . .. 2-17
8089 Input/Output Processor (lOP) . . . . . . . . .. 2-17
Multiprocessing Features. . . . . . . . . . . . . . . . . . .. 2-17
Bus Lock ................................. 2-17
WAIT and TEST . . . . . . . . . . •. . . . . . . . . . . . . .. 2-18
Escape .................................... 2-19
Request/Grant Lines. . . . • . . . . . . . . . . . . . . . . .. 2-20
. Multibus™ Architecture .................... 2-21

iii

PAGE
DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
Bus Configurations. . . . . . . . . . . . . . . . . . . . . .. 3-5
A Sample Transaction. . . . . . . . . . . . . . . . . . .. 3-10
Applications ....................... , ...... 3-12

PAGE
Based Indexed Addressing ................ 2-71
String Addressing. . . . . . . . . . . . . . . . . . . . . . .. 2-72
110 Port Addressing ....................... 2-72
Programming Facilities ..................... 2-72
Software Development Overview ............. 2-73
PL/M-86 ................................. 2-75
Statements and Comments ................ 2-75
Data Definition ....................... " 2-75
Assignment Statement. . . . . . . . . . . . . . . . . . .. 2-77
Program Flow Statements ................. 2-79
Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-81
ASM-86 .................................. 2-83
Statements ............................. 2-83
Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-84
Defining Data ........................... 2-85
Records ............................... ;. 2-85
Structures .............................. 2-87
Addressing Modes ..................... ,. 2-87
Segment Control .... . . . . . . . . . . . . . . . . . . .. 2-88
Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-90
LINK-86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-90
LOC-86 . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 2-90
LIB-86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-91
OH-86 ................................... 2-91
CONV-86 ................................ 2-92
Sample Programs ........................ " 2-92
Programming Guidelines and Examples. . . . . .. 2-96
Programming Guidelines ..... . . . . . . . . . . . . .. 2-96
Segments and Segment Registers . . . . . . . . . .. 2-96
Self-Modifying Code ................... " 2-96
Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . .. 2-97
Operating Systems. . . . . . . . . . . . . . . . . . . . . .. 2-97
Interrupt Service Procedures ... . . . . . . . . . .. 2-99
Stack-Based Parameters ................. 2-100
Flag Images ............................ 2-100
Programming Examples ................... 2-100
Procedures ............................ 2-100
Jumps and Calls ........................ 2-105
Records .............................. , 2-110
Dynamic Code Relocation ............... 2-113
Memory-Mapped 110 ................... 2-115
Breakpoints ........................... 2-117
Interrupt Procedures .................... 2-119
String Operations ....................... 2-125

Processor Architecture ......................
Common Control Unit (CCU) ...............
Arithmetic/Logic Unit (ALU) . .. . . . . . . . . . . ..
Assembly/Disassembly Registers ............ ,
Instruction Fetch Unit ......................
Bus Interface Unit (BIU) ....................
Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
110 Control ............................
Registers .............................. ,
Program Status Word ....................
Tag Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Concurrent Channel Operation. . . . . . . . . . ..
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Storage Organization. . . . . . . . . . . . . . . . . . . . . ..
Dedicated and Reserved Memory Locations. . ..
Dynamic Relocation .......................
Memory Access .. . . . . . . . . . . . . . . . . . . . . . . . ..
Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmed 110 ...................... ; .. ,
110 Instructions. . . . . . . . . . . . . . . . . . . . . . . ..
Device Addressing ...................... ,
110 Bus Transfers. . . . . . . . . . . . . . . . . . . . . ..
DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . ..
Preparing the Device Controller. . . . . . . . . . ..
Preparing the Channel. . . . . . . . . . . . . . . . . . ..
Beginning the Transfer . . . . . . . . . . . . . . . . . ..
DMA Transfer Cycle. . . . . . . . . . . . . . . . . . . ..
Following the Transfer. . . . . . . . . . . . . . . . . ..
Multiprocessing Features. . . . . . . . . . . . . . . . . . ..
Bus Arbitration .......................... ,
Request/Grant Line ..................... ,
8289 Bus Arbiter ........................
Bus Arbitration for lOP Configurations .... ,
Bus Load Limit ... . . . . . . . . . . . . . . . . . . . . . . ..
Bus Lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Processor Control and Monitoring .......... ,
Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Channel Commands ...................... ,
DRQ (DMA Request) . . . . . . . . . . .. . . . . . . .. ..
EXT (External Terminate) .. . . . . . . . . . . . . . . ..
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Status Lines ..............................
Instruction Set " . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Transfer Instructions. . . . . . . . . . . . . . . . ..
Arithmetic Instructions. . . . . . . . . . . . . . . . . . . ..
Logical and Bit Manipulatioll Instructions. . . ..
Program Transfer Instructions. . . . . . . . . . . . . ..
Processor Control Instructions ..............
Instruction Set Reference Information. . . . . . ..

CHAPTER 3
THE 8089 INPUT/OUTPUT
PROCESSOR
Processor Overview ..... , ....................
Evolution .... . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Principles of Operation ..................... ,
CPU/lOP Communications ................
Channels ..................... , ..........
Channel Programs (Task Blocks) ............

3-1
3-1
3-2
3-2
3-4
3-4

iv

3-13
3-13
3-13
3-14
3-14
3-16
3-16
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-23
3-24
3-25
3-25
3-25
3-26
3-26
3-27
3-27
3-27
3-31
3-32
3-33
3-34
3-34
3-35
3-36
3-36
3-36
3-37
3-37
3-37
3-40
3-43
3-43
3-43
3-43
3-44
3-44
3-45
3-46
3-48
3-49
3-51

PAGE
Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . .. 3-59
Register and Immediate Operands. . . . . . . . . . .. 3-59
Memory Addressing Modes. . . . . . . . . . . . . . . .. 3-59
The Effective Address. . . . . . . . . . . . . . . . . . .. 3-60
Based Addressing ........................ 3-60
Offset Addressing. . . . . . . . . . . . . . . . . . . . . .. 3-60
Indexed Addressing. . . . . . . . . . . . . . . . . . . . .. 3-60
Indexed Auto-Increment Addressing ........ 3-61
Programming Facilities ..................... 3-63
ASM-89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-63
Statements ...... . . . . . . . . . . . . . . . . . . . . . .. 3-63
Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-66
Defining Data .................... , ...... 3-66
Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-67
Addressing Modes. . . . . . . . . . . . . . . . . . . . . .. 3-68
Program Transfer Targets ................ 3-68
Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-69
Segment Control .. . . . . . . . . . . . . . . . . . . . . .. 3-69
Intermodule Communication .............. 3-70
Sample Program ........................ 3-73
Linking and Locating ASM-89 Modules. . . . . .. 3-76
Programming Guidelines and Examples. . . . . .. 3-79
Programming Guidelines ........ . . . . . . . . . .. 3-79
Segments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-79
Self-Modifying Code. . . . . . . . . . . . . . . . . . . .. 3-79
110 System Design ....................... 3-79
Programming Examples .................... 3-81
Initialization and Dispatch. . . . . . . . . . . . . . .. 3-81
Memory-to-Memory Transfer. . . . . . . . . . . .. 3-85
Saving and Restoring Registers ............ 3-85

PAGE
DMA Transfers. . . . . . . . . . . . . . . . . . . . . . . . . .. 4-47
DMA Termination ......................... 4-50
Peripheral Interfacing. . . . . . . . . . . . . . . . . . . . .. 4-50
Instruction Encoding. . . . . . . . . . . . . . . . . . . . . .. 4-52

APPENDIX A
APPLICATION NOTES
AP-67 8086 System Design .... . . . . . . . . . . . . . . .. A-3
AP-61 Multitasking for the 8086 ............... A-67
AP-50 Debugging Strategies and
Considerations for 8089 Systems ........ A-85
AP-51 Designing 8086,8088,8089
Multiprocessing Systems with the 8289
Bus Arbiter ......................... A-Ill
AP-59 Using the 8259A Programmable
Interrupt Controller .................. A-135
AP-28A Intel®Multibus TM Interfacing. . . . . . .. A-175
AP-43 Using the iSBC-957™ Execution
Vehicle for Executing 8086
Program Code ....................... A-209

APPENDIXB
DEVICE SPECIFICATIONS
8086 Family
8086/8086-2/8086-4 16-Bit HMOS
Microprocessor ...................... B-1
M8086 16-Bit HMOS Microprocessor ..... . .. B-22
18086 16-Bit HMOS Microprocessor ........ " B-23
8088 8-Bit HMOS Microprocessor. . . . . . . . . .. B-24
8089 8/16-Bit HMOS 110 Processor. ....... " B-46
8282/8283 Octal Latch. .. . . . . . . . . . . . . . . . . .. B-59
8284 Clock Generator and Driver for
8086, 8088, 8089 Processors. . . . . . . . . .. B-63
M8284 Clock Generator and Driver for
8086, 8088, 8089 Processors ......... " B-69
18284 Clock Generator and Driver for
8086,8088,8089 Processors ........... B-70
8286/8287 Octal Bus Transceiver ............ B-71
8288 Bus Controller for 8086, 8088,
8089 Processors. . . . . . . . . . . . . . . . . . . .. B-75
8289 Bus Arbiter ........................ " B-81
8237/8237-2 High Performance Programmable
DMA Controller. . . .. . . . . . . . . . . . . . .. B-92
8259A/8259A-2/8289A-8 Programmable
Interrupt Controller . . . . . . . . . . . . . . .. B- I 06
8085 Peripherals
8155/8156/8155-2/8156-22048 Bit Static
MOS RAM with 110 Ports and Timer ... B-124
8185/8185-2 1024 x 8-Bit Static
RAM for MCS-85™ .................. B-125
8355/8355-2 16,384-Bit ROM with 110 ...... B-126
8755A18755A-2 16,384-Bit EPROM
with I/O ............................ B-127

CHAPTER 4
HARDWARE REFERENCE
INFORM A TION
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-1
8086 cnd 8088 CPUs ......................... 4-1
CPU Architecture .......................... 4-1
Bus Operation ............................. 4-5
Clock Circuit ......................... , ... 4-10
Minimum/Maximum Mode ................. 4-10
Minimum Mode ........................ . 4-11
Maximum Mode ........................ . 4-11
External Memory Addressing ............... . 4-14
110 Interfacing ........................... . 4-15
Interrupts ............................... . 4-16
Machine Instruction Encoding and Decoding .. 4-18
8086 Instruction Sequence ................. . 4-37
8089 I/O Processor ..... , .................. . 4-38
System Configuration ..................... . 4-39
Local Mode ............................ . 4-39
Remote Mode .......................... . 4-40
Bus Operation ........................... . 4-41
Initialization ............................. . 4-44
I/O Dispatching .......................... . 4-46

v

PAGE

PAGE

Standard Peripherals
8041A/8741A Universal Peripheral Interface
8-Bit Microcomputer ................. B-128
8202 Dynamic RAM Controller ............. B-129
8205 High Speed lOut of 8 Binary Decoder .. B-130
8251A Programmable Communication
Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .. B-131
8253/8253-5 Programmable Interval Timer. .. B-132
8255A/8255A-5 Programmable Peripheral
Interface. . . . . . . . . . . . . . . . . . . . . . . . . . .. B-133
8271/8271-6/8271-8 Programmable Floppy
Disk Controller ...................... B-134
8273 Programmable HDLC/SDLC Protocol
Controller. . . . . . . . . . . . . . . . . . . . . . . . •.. B-135
8275 Programmable CRT Controller ........ B-136
8279/8279-5 Programmable Keyboard/Display
Interface .............. '.............. B-137
8291 GPIB Talker/Listener .........•....... B-138
8292 GPIB Controller .............•....... B-139
8293 GPIB Transceiver. . . . . . . . . . . . . . . . . . .. B-140
8294 Data Encryption Unit ................ B-141
8295 Dot Matrix Printer Controller ......... B-142
RAM Memories
2114A 1024 x 4 Bit Static RAM. . . . . . . . . • . .. B-143
21421024 x 4 Bit Static RAM. . . . . . . . . . . . . .. 8-144

21481024 x 4 Bit Static RAM .. " ........... B-145
EPROM Memories
271616K (2K x 8) UV Erasable PROM ....... B-146
2732 32K (4K x 8) UV Erasable PROM ....... B-147
2758 8K (l K x 8) UV Erasable Low
Power PROM ....................... B-148
Development Tools
Model 230 Intellec® Series II
Microcomputer Development System .... B-149
8086/8088 Software
Development Package ....... . . . . . . . .. B-153
8089 Assembler Support Package. . . . . . . . . .. B-163
ICE-86™ 8086 In-Circuit Emulator; ........ B-165
iSBC 86/ 12ATM Single Board Computer .... , B-I71
iSBC 957™ Intellec®-iSBC 86/12ATM Interface
and Execution Package ................ B-179
iSBC 300/340™ iSBC 300™ 32K-Byte RAM
Expansion Module iSBC 340™ 16K-Byte
EPROM/ROM Expansion Module ..... B-184
SDK-86 MCS-86™ Sys.tem Design Kit ....... B-188
SDK-C86 MCS-86™ System Design Kit.: ... 8-194

'vi

Chapter 1
Introduction

CHAPTER 1
INTRODUCTION
This publication describes the Intel® 8086 family
of microcomputing components, concentrating
on the 8086, 8088 and 8089 microprocessors. It is
written for hardware and software engineers and
technicians who understand microcomputer
operating principles. The manual is intended to
introduce the product line and to serve as a reference during system design and implementation.

1.2 8086 Family Architecture
Considered individually, the 8086, 8088 and 8089
are advanced third-generation microprocessors.
Moreover, these processors are elements of a
larger design, that of the 8086 family. This
systems architecture specifies how the processors
and other components relate to each other, and is
the key to the exceptional versatility of these
products.

Recognizing that successful microcomputer-based
.products are judicious blends of hardware and
software, the User's Manual addresses both subjects, although at different levels of detail. This
publication is the definitive source for information describing the 8086 family components. Software topics, such as programming languages,
utilities and examples, are given moderately
detailed, but by no means complete, coverage.
Additional references, available from Intel's
Literature Department, are cited in the programming sections.

The components in the 8086 family have been
designed to operate together in diverse combinations within the systematic framework of the
overall family architecture. In this way a single
family of components can be used to solve a wide
array of microcomputing problems. A component mix can be tailored to fit the performance
needs of an application precisely, without having
to pay for unneeded capabilities that may be
bundled into more monolithic, CPU-centered
architectures. Using the same family of components across multiple systems limits the learning curve problem and builds on past experience.
Finally, the modular structure of the family
architecture provides an orderly way for systems
to grow and change.

1.1 Manual Organization
The manual contains four chapters and three
appendices. The remainder of this chapter
describes the architecture of the 8086 family, and
subsequent chapters cover the individual components in detail.

The 8086 family architecture is characterized by
three major principles:

Chapter 2, describes the 8086 and 8088 Central
Processing Units, and Chapter 3 covers the 8089
Input/Output Processor. These two chapters are
identically organized and focus on providing a
functional description of the 8086, 8088 and
8089, plus related Intel hardware and software
products. Hardware reference informationelectrical characteristics, timing . and physical
interfacing considerations-for ail three processors is concentrated in Chapter 4.
Appendix A is a collection of 8086 family application notes; these provide design and debugging
examples. Appendix B contains complete data
sheets for all the 8086 family components and
system development aids; summary data sheets
covering compatible components from other Intel
product lines are also reproduced in Appendix B.

1.

System functions are distributed among
specialized components.

2.

Multiprocessing capabilities are inherent in
the hardware.

3.

A hierarchical bus organization provides for
the complex data flows required by highperformance systems without burdening
simpler systems with unneeded capabilities.

Functional Distribution
Table 1-1 lists the components that constitute the
8086 microprocessor family. All components are
contained in standard dual in-line packages and
require single +5V power sources.
1-1

INTRODUCTION
Table 1-1. 8086 Component Family
Microprocessor

Technology Pins

Description

8086

Central Processing Unit (CPU)

HMOS

40

8/16 bit general-purpose microprocessor; 16-bitexternal data path.

8088

Central Processing Unit (CPU)

HMOS

40

8/16 bit general-purpose microprocessor; 8-bit external data path.

8089

Input/Output Processor (lOP)

HMOS

40

8/16 bit microprocessor optimized for
high-speed I/O operations; 8-bit and
16-bit external data paths.

Support Component

Technology Pins

Function
hig hest-priority

8259A Programmable Interrupt Controller (PIC)

NMOS

28

Identifies
request.

8282
8283

Octal Latch
Octal Latch (Inverting)

Bipolar

20

Demultiplexes and increases drive of
address bus.

8284

Clock Generator and Driver

Bipolar

18

Provides time base.

8286 Octal Bus Transceiver
8287 Octal Bus Transceiver (Inverting)

Bipolar

20

Increases drive on data bus.

8288

Bus Controller

Bipolar

20

Generates bus command signals.

8289

Bus Arbiter

Bipolar

20

Controls access of microprocessors
to multimaster system bus.

Microprocessors
At the core of the product line are three
microprocessors that share these characteristics:
•
Standard operating speed is 5 MHz (200 ns
cycle time); a selected 8 MHz version of the
8086 CPU is also available.
•
Chips are housed in reliable 40-pin packages.
•
Processors operate on both 8- and 16-bit data
types; internal data paths are at least 16 bits
wide.
•
Up to 1 megabyte of memory can be
addressed, along with a separate 64k byte
110 space.
•
The address/data and status interfaces of the
processors are compatible (the address and
data buses are time-multiplexed at the processor, i.e., an address transmission is
followed by a data transmission over a subset
of the same physical lines).

interrupt

The 8086 and 8088 are third-generation central
processing units (CPUs) that differ primarily in
their external data paths. The 8088 transfers data
between itself and other system components 8 bits
at a time. The 8086 can transfer either 8 or 16 bits
in one bus cycle and is therefore capable of
greater throughput. Both processors have two
operating modes, selectable by a strapping pin. In
minimum mode, the CPUsemit the bus control
signals needed by memory and 110 peripheral
components. In maximum mode, an 8288' Bus
Controller assumes responsibility for controlling
devices attached to the system bus. CPU pins no
longer needed for bus control are then redefined
to provide signals that support multiprocessing
systems.
The 8089 Input/Output Processor (lOP) is an
independent microprocessor whose design has
been optimized for transferring data. The 8089
1-2

INTRODUCTION

typically runs under the direction of a CPU, but it
executes a separate instruction stream and can
operate in parallel with other system processors.
The lOP contains two independent I/O channels
that combine attributes of both CPUs and
advanced DMA (direct memory access) controllers. The channels can execute programs and
perform programmed I/O operations similar to
CPUs. They may also transfer data by DMA, at
rates up to 1.25 megabytes per second (5 MHz
version). The channels can support mixes of 8and 16-bit I/O devices and memory. Combining
speed with programmable intelligence, the 8089
can assume the bulk of I/O processing overhead
and thereby free a CPU to perform other tasks.

an external crystal or TTL signal by three and
outputs the 5 MHz or 8 MHz processor clock
signal. It also provides the microprocessors with
reset and ready signals.
8282 or 8283 Octal Latches may be added to a
system to demultiplex the combined address/data
bus generated by the 8086 family microprocessors. A demultiplexed bus provides
separate stable address and data lines required by
many peripheral components. Two latches
demultiplex 16 bits of the bus to provide an
address space of up to 64k bytes, while three
latches generate the fu1l20-bit (megabyte) address
space. The latches also provide the high drive on
the address lines needed in larger systems.

Interrupt Controller

8286 and 8287 Octal Bus Transceivers are used to
provide more drive on data lines than the processors themselves are capable of providing. One
or two transceivers may be used depending on the
width of the data bus (8 or 16 bits).

The 8259A Programmable Interrupt Controller
(PIC) is a new, 8086 family-compatible version
of the familiar 8259 that has been enhanced to
operate with the advanced interrupt facilities of
the 8086 and 8088 CPUs. The 8259A accepts
interrupt requests from up to eight sources; up
to 64 sources may be accommodated by
"cascading" additional 8259As. Each interrupt
sOlirce is assigned a priority number that typically reflects its "criticality" in the system. The
8259A has several built-in, priority-resolving
mechanisms that are selectable by software commands from the CPU. These modes operate
somewhat differently, but in general the 8259A
continuously identifies the highest-priority active
interrupt request and generates an interrupt
request to the CPU if this request has higher
priority than the request currently being processed. When the CPU recognizes the interrupt
request, the 8259A transfers a code to the CPU
that identifies the interrupt source.

The 8288 Bus Controller decodes status signals
output by an 8089, or a maximum mode 8086 or
8088. When these signals indicate that the processor is to run a bus cycle, the 8288 issues a bus
command that identifies the bus cycle as memory
read, memory write, I/O read, I/O write, etc. It
also provides a signal that strobes the address into
8282183 latches. The 8288 provides the drive
levels needed for the bus control lines in medium
to large systems.
The 8289 Bus Arbiter controls the access of a processor to a multimaster system bus. A multimaster bus is a path to system resources (typically
memory) that is shared by two or more
microprocessors (masters). Arbiters for each
master may use one of several priority-resolving
techniques to ensure that only one master drives
the shared bus.

Bus Interface Components

Components may be selected from this modular
group to implement different system bus configurations. Except for the 8284, all components
are optional; their inclusion in a system is based
on the needs of the application. All of the bus
interface components are implemented using
bipolar technology to provide high-quality, highdrive signals and very fast inttrnal switching.

Multiprocessing
Employing mUltiple processors in medium to
large systems offers several significant advantages
over the centralized approach that relies on a
single CPU and extremely fast memory:
•

The 8284 Clock Generator and Driver provides
the time base for the 8086 family microprocessors. It divides the frequency signal from
1-3

system tasks may be allocated to
special-purpose processors whose designs are
optimized to perform certain types of tasks
simply and efficiently;

INTRODUCTION

•

very high levels of performance can be
attained when multiple processors can
execute simultaneously (parallel processing);

•

robustness can be improved by isolating
system functions so that a failure or error in
one part of the system has a limited effect on
the rest of the system;

•

the natural partitioning of the system
promotes parallel development of subsystems, breaks the application into smaller,
more manageable tasks, and helps isolate the
effects of system modifications.

For mutual exclusion,. each processor has a
LOCK (bus lock) signal which a program may
activate to prevent other processors from obtaining a shared system bus. The 8089 may lock the
bus during a DMA transfer to ensure that both
the transfer completes in the shortest possible
time and that another processor does not access
the target of the transfer (e.g., a buffer) while it is
being updated. Each of the processors has an
instruction that examines and updates a memory
byte with the bus locked. This instruction can be
used to implement a semaphore mechanism for
controlling the access of multiple processors to
sha:red resources. (A semaphore is a variable that
indicates whether a resource, such as a buffer or a
pointer, is "available" or "in use"; section 2.5
discusses semaphores in more detail).

The 8086 family architecture is explicitly designed
to simplify the development of multiple processor
systems by providing facilities for coordinating
the interaction of the processors.

Bus Organization
The architecture supports two types of processors: independent processors and
coprocessors. An independent processor is one
that executes its own instruction stream. The
8086, 8088 and 8089 are examples of independent
processors. An 8086 or 8088 typically executes a
program in response to an interrupt. The 8089
starts its channels in response to an interrupt-like
signal called a channel attention; this signal is
typically issued by a CPU.

Figure 1-1 summarizes the 8086 family bus structure. There are two different types of buses:
system and local. Both buses may be shared by
multiple processors,. i.e., both are multimaster
buses. Microprocessors are always connected to a
local bus, and memory and 110 components
usually reside on a system bus. The 8086 family
bus interface components link a local bus to a
system bus.

The 8086 architecture also supports a second type
of processor, called a coprocessor. Coprocessor
"hooks" have been designed into the 8086 and
8088 so that this type of processor can be
accommodated in the future. A coprocessor differs from an independent processor in that it
obtains its instructions from another processor,
called a host. The coprocessor monitors instructions fetched by the host and recognizes certain of
these as its own and executes them. A
coprocessor, in effect, extends the instruction set
of its host processor.

Local Bus
The local bus is optimized for use by the 8086
family microprocessors. Since standard memory
and 110 components are not attached to the local
bus, information can be multiplexed and encoded
to make very efficient use of processor pins (certain MCS-85™ peripheral components can be
directly connected to the local bus). This allows
several pins to be dedicated to coordinating the
activity of multiple processors sharing the local
bus. Multiple processors connected to the same
local bus are said to be local to each other; processors on different local buses are said to be
remote to each other, or configured remotely.
Both independent processors and coprocessors
may share a local bus; on-chip arbitration logic
determines which processor drives the bus.
Because the processors on the local bus share the
same bus interface components, the local configuration of multiple processors provides a compact and inexpensive multiprocessing system.

The 8086 family architecture provides built-in
solutions to two classic mUltiprocessing coordination problems: bus arbitration and mutual exclusion. Bus arbitration may be performed by the
bus request/grant logic contained in each of the
processors, by 8289 Bus Arbiters, or by a combination of the two when processors have access
to multiple shared buses. In all cases, the arbitration mechanism operates invisibly to software.
1-4

INTRODUCTION

r-----'
1

,----------------------,

.....
~

I

r---,
1
1
I

PRIVATE
MEMORY

1
L. -

-

-

1
I"''''
1 w~1 r---1
1D1"' ...1
1

......

1
1
1
1

PUBLIC
MEMORY

BUS

~~".,IINTERFACE 1

II:

~

PRIVATE

I "'~I
I.....U

1/0

I'" .,..

1

BUS
INTERFACE
GROUP

1

L. - . .-

..

PUBLIC
1/0

....-~~~~~!PI--.
LOCAL BUS

r- Y - , r-Y'-,
I

PROCESSING
MODULE

PROCESSOR

GROUP

'I

L _ _ _ .I

1
1

L _____ ..J

1
1.........

r - - _,

I

PROCESSING
MODULE

I I

:PROCESSOR:

r-----'

1

: PROCESSOR:

I
I I
I
L ___ .J L ___ .J

~

• .,.

I

PR~2Bt~~NG

1
1
I

L _____ -l

Figure 1-1. Generalized 8086 Family Bus Structure
The system bus design is modular and subsets
may be implemented according to the needs of the
application. For example, the arbitration lines are
not needed in single-processor systems or in
multiple-processor systems that perform arbitration at the local-bus level.

System Bus

A full implementation of an 8086 system bus consists of the following five sets of signals:
1.

2.
3.

4.
5.

address bus,
data bus,
control lines,
interrupt lines, and
arbitration lines.

A group of bus interface components transforms
the signals of a local bus into a system bus. The
number of bus interface components required to
generate a system bus depends on the size and
complexity of the system; reduced application
needs translate directly into reduced component
counts. These main variables determine the configuration of a bus interface group: address space
size (number of latches), data bus Width (number
of transceivers), and arbitration needs (presence
of a bus arbiter).

These signals are designed to meet the needs of
standard memory and I/O devices; the address
and data buses are demultiplexed and traditional
control signals (memory read/write, I/O
read/write, etc.) are provided on the system bus.

1-5

INTRODUCTION
tention for use of the public system bus can be
held to a minimum to ensure that shared
resources are quickly available when they are
needed. In addition, processors in separate
modules can simultaneously fetch instructions
from private memory spaces to allow multiple
system tasks to proceed in parallel.

The 8086 family system bus is functionally and
electrically compatible with the Multibus ™
multimaster system bus used in Intel's iSBC™
line of single board computing products. This
compatability gives system designers access to a
wide variety of computer, memory, communications and other modules that may be incorporated
into products, used for evaluation or for test
vehicles.

Bus Implementation Examples

This section summarizes the 8086 family bus
organization by showing how components from
the family can be combined to implement diverse
bus configurations. The first two examples
illustrate special cases that extend the applicability of the 8086 family to smaller systems. The
remaining examples add and recombine the same
basic components to form progressively more
complex bus configurations. Note that these
examples are intended to be illustrative rather
than exhaustive; many different combinations of
components can be tailored to fit the needs of
individual applications.

Processing Modules

The processor(s) and bus interface group(s) that
are connected by a local bus constitute a processing module. A simple processing module could
consist of a single CPU and one bus interface
group. A more complex module would contain
multiple processors, such as two lOPs, or a CPU
and one or two lOPs. One bus interface group
typically links the processors in the module to a
public system bus. If there are multiple processing
modules in the system, all memory or 110 connected to the public bus is accessible to all processing modules on the public bus. 8289 Bus
Arbiters in each processing module control the
access of the modules to the public bus and hence
to the public memory and 110.

In its minimum mode configuration, the 8088
time-multiplexes its 8-bit data bus with the lower
eight bits of its 20-bit address bus (figure 1-2).
This multiplexed address/data bus, and the bus
control signals emitted by the 8088, are directly
compatible with the multiplexed bus components
of Intel's 8085 family. These peripherals contain
on-chip logic that demultiplexes a combined
address/data bus. In addition, many of these
devices are multifunctional,combining, for
example, RAM, 110 ports and a timer on a single
chip. By using these components, it is possible to
build small (as few as four chips) economical
systems that are nonetheless capable of performing significant computing tasks.

A second bus interface group may be connected
to a processing module's local bus, generating a
second bus. This bus can provide the processing
module with a private address space that is not
accessible to other processing modules. Distributing memory and 110 resources in this manner
can improve system robustness by isolating the
effects of failures. It can also increase system
throughput dramatically. If processor programs
and local data are placed in private memory, con-

,
,

CONTROL LINESJi.
8284
CLOCK
GENERATOR

8088
CPU

ADDRESSI
DATA LINES

}

II..

Figure 1-2. 8088 Multiplexed Bus
1-6

8088 MULTIPLEXED
BUS

INTRODUCTION

Combining 8282/83 latches with a minimum
mode 8086 or 8088 produces a minimum mode
system bus (figure 1-3). Two latches provide an
address space of up to 64k bytes; adding a third
latch provides access to the full megabyte of
memory. An 8288 Bus Controller is not required
for this implementation as the CPUs themselves
emit the bus control signals when they are configured in the minimum mode. This demultiplexed bus structure is compatible with the wide
array of memory and 110 components that have

been developed for the industry-standard 8080A
CPU. Eight-bit peripherals may be connected to
both the upper and lower halves of the 8086's
16-bit data bus. 8286/87 transceivers may be
added to provide additional drive on the data
lines, where required. Including an 8259A gives
the CPU the ability to respond to multiple interrupt sources without polling. The minimum mode
system bus configuration is well-suited to a
variety of systems whose computational requirements can be met by a single 8086 or 8088 CPU.

.-----,
I
I
I

8284
CLOCK
GENERATOR

0 ~259A A
I ~ INTERRUPT
PR It?TE~~~p~LE I
REQUEST
CONTROLLER
I
LINES

"·rf
I
" "'"'"1

CONTROL LINES

8086/
8088
CPU
"" LOCAL BUS

"II

,.

110.

8282/83
LATCHES

r---,
I

.....: ~~s:~~~
I
I

CEIVERS

110.

,.

~

I

I~

I
I

DATA LINES

L. ___ .J

Figure 1-3. Minimum Mode System Bus
1-7

,.

•

MINIMUM
MODE
SYSTEM
BUS

INTRODUCTION

When an 8086 or 8088 is configured in maximum
mode and an 8288 is added to control the system
bus, one or two 8089s may be directly connected
to the CPU (figure 1-4). The processors all share
the same latches, transceivers, clock and bus controller, via the local bus. Arbitration logic built
into the 8086, 8088 and 8089 coordinates use of
the local bus, and thus of the system bus. This bus
configuration enables the powerful 1/0 handling
capabilities of the 8089 to be incorporated into
systems of moderate size and cost.

master system bus interface; this bus structure is
electrically compatible with the Multibus™
architecture used in Intel iSBCTM single-board
computing systems.

•
•

a single 8086 or 8088
a single 8089

The 8289 enables high-performance systems to be
designed as a series of independent processing
modules whose activities are coordinated via a
shared system bus. Figure 1-5 shows the multi-

•
•
•

two 8089s
an 8086 or 8088 and one 8089
an 8086 or 8088 and two 8089s

Several different combinations of processors may
be attached to the local bus of a multimaster computing module:

r----'

1

8259A

I

INTERRUPT
CONTROLLER

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1 PROGRAMMABLE
r-

1

1..4...INiiTiiERiiiR.UP.T..LiiiIN.ES. . .
...

I
L ____ ..J

...

r----'
I

I

1

1

1

•
L--r-J

r

1
-I

8089
lOP

I....
I"
1

r:+

8288
BUS
CONTROLLER

'TT

CONTROL LINES

a..
r

:::>

"'-'


8284
CLOCK
GENERATOR

8086/
8088
CPU

F+

8282/83
LATCHES

~

8286/87
TRANSCEIVERS

ADDRESS LINES

...
r

t

I:lfi

LJ

...'"

Figure 1-4. Muitimaster Local Bus
1-8

... ,..

DATA LINES

a..
r

INTRODUCTION

INTERRUPT LINES

,.--+--.,
:

8259A

I
I

CONTROLLER

I

~-

8284
CLOCK
GENERATOR

I

I

...- ... .1
I

I

I

- - - - ..I

I
I

I

L-- 1 --.J

I

II

... __ J __ .,

I

I

ARBITRATION

8288
BUS
CONTROLLER

CONTROL LINES

8282/83
LATCt+ES

ADDRESS LINES

LINES

MULTIMASTER
SYSTEM BUS

I

I
I

8289
BUS
ARBITER

8086/
8088
CPU

I

L_.-I

1

:
. . : - - - - - - - - -. . . .

IPROGRAMMABLEI~d~_ _ _~::::::::~_ _ _,
INTERRUPT
1l1li

I
8089
lOP

I

I
IL _____ .JI

8286/87
I ......._ _ _ _
DA.T.A..
LI_N_ES_ _ _ _~..~
TRANSCEIVERS I~
,.

Figure 1-5. Basic Multimaster Processing Module

may be connected to the private I/O bus. Taking
this approach can greatly reduce the 8089's use of
the system bus as most memory and I/O accesses
can be made to the private address space. The
system bus is thus made available for use by other
processors, and the 8089 can execute in parallel
with other processors for extended periods. A
limited private I/O bus may be implemented
using the 8-bit multiplexed peripherals of the 8085
family, eliminating the latches and transceivers
shown in figure 1-6.

All of the processors on the local bus obtain
access to the system bus through a single set of
interface components.
One or two 8089s in a multimaster processing
module may be configured with a private I/O bus
as shown in figure 1-6. In this configuration,
memory access commands are directed to the
public multimaster system bus, while I/O commands use the private I/O.bus. Memory, containing the 8089's programs, as well as I/O devices,

1-9

INTRODUCTION

INTERRUPT LINES

1"I
I

,.

8284

8289
BUS
ARBITER

~ ARBITRATION LINES.

CLOCK
GENERATOR

8089
lOP

--"

"'-~,.tl

~2J:
CONTROLLER

CONTROL LINES
1-________
,,.~

MULTIMASTER
SYSTEM BUS

CONTROL LINES

.

ADDRESS LINES

..

8282/83

LATCHES

"II

II..

'I

PRIVATE
I/O BUS

"

a:

r----'

•

DATA LINES

1
II TRANSCEIVERS
8286/87
1

...w
'"':IE"
is

8282/83

ADDRESS LINES

8286/87

DATA LINES

LATCHES

,.II..

:::>

:IE

1
1I.......
I

+-+

TRANSCEIVERS

L____ J

•

•

Figure 1-6. Private I/O Bus

Adding a second 8288 to the local bus allows an
8086 or 8088 in a processing module to divide its
address space into system and resident sections
(figure 1-7). A PROM or decoder is used to direct
an address reference to the system bus or to the
resident bus. The resident bus allows the CPU to
run out of its own address space to minimize its

use of the system bus. Since no other processors
can access the private memory on the CPU's resident bus, operating system code and data in this
space is protected from errors in other processor
programs. If a second 8289 is added to a resident
bus module, the resident bus becomes a second
multimaster system bus.
1-10

INTRODUCTION
INTERRUPT
REQUEST
LINES

'.
1/0

..III
"I

..III
PRIVATE
MEMORY

8089
lOP

I

II)

:>
.,

CL

PRIVATE

SUPERVISOR {
MODULE

It.

I. ..III

I.

"

"

"I

RESIDENT
BUS

"I

I.

"

8089
lOP

8086
CPU

.
.
. .
..

.-j

~

~

..III

I.

1..111

I.

" "w " "
....

8089
lOP

It.

g "

It.

1"1

.
a:

PRIVATE
MEMORY

w
....

l
8088
CPU

I...

...
"I

>

GRAPHICS
MODULE
II)

CL

.,:>

..III

I.

1..111

"I

"

" "

..III

It.

...

I.

PRIVATE

1/0

SYSTEM
MEMORY

0:

.. .,
II)

II)

..

:>

:; :;

;:: w
....

PRIVATE
MEMORY

..III

It. ..III

I.

" g" "

.

w
....

GRAPHICS
MODULE

2:
0:

CL

PRIVATE

1/0

..III
."1

-' II)
:> >
:; II)

8089
lOP

f
II)

:>
.,

I. ..III

I.

"

"

"I

8088
CPU

~

~ ~~

~

8089
lOP

"I

.

8088
CPU

PRIVATE
MEMORY

w
....

f

...

I.

" g "
2:

..III
,"I

GRAPHICS
MODULE
II)

0:

:>

~ ~

I.

PRIVATE

"I

"

1/0

"

Figure 1-8. Multimaster Design Example
system may be used to develop systems based on
other Intel microprocessor families such as the
8085 and the 8048.

1.3 Development Aids
Intel provides the sophisticated tools needed for
timely and economical development of products
based on the 8086 family. The 8086 family system
development environment is focused on the
Intellec® Series II Microcomputer Development
System (figure 1-9). The Intellec system is a
multiple-microprocessor system that runs
ISIS-II, a disk-based operating system that has
been proven in thousands of installations. The
Intellec has built-in interfaces for a printer,
a PROM programmer and a paper tape
reader/punch. This same hardware and operating

Three language translators support 8086 family
programming. PL/M-86 is a high-level language
for the 8086 and 8088 that supports structured
programming techniques. It is upwardcompatible with PLlM-80, the most widely used
high-level microprocessor language. ASM-86 may
be used to write assembly language programs for
the 8086 and the 8088 CPUsand gives the programmer access to the full power of these CPUs.
8089 programs are written in ASM-89, the 8089
assembly language.

1-12

INTRODUCTION

The iSBC 86/12™ board is a high-performance
single board computer based on a maximum
mode 8086 CPU. The board contains 32k of dualport RAM that is accessible to the CPU via the
on-board bus and to other processors via the
built-in Multibus™ interface. The board also has
an asynchronous serial port, parallel ports with
sockets for drivers and terminators, two timers
and sockets for 16k of ROM.

The language translators produce compatible outputs that can be manipulated by the software
development utilities. LINK-86, for example, can
combine programs written in ASM-86 with
PL/M-86 programs. LIB-86 allows related programs to be stored in libraries to simplify storage
and retrival. LOC-86 assigns absolute memory
addresses to programs. OH-86 changes the format of an executable program for PROM programming or for loading into the RAM of a test
vehicle.

An iSBC 86/12TM can be linked to an Intellec®
system using the iSBC 957™ Intellec-iSBC 86/12
Interface and Execution Package. The package
includes a ROM-based monitor for the iSBC
86/12 board, software for the Intellec system and
cabling to connect the two. The package supports
data transfers between Intellec diskettes and iSBC
86/12 memory, full speed execution of customer
programs on the iSBC 86/12 board, breakpoints,
single-stepping, and data moves, replacements,
searches and compares. All commands are
entered from the Intellec console.

The UPP-301 Universal PROM Programmer can
burn programs into any of Intel's PROM
memories; the UPP plugs into the Intellec®
system and allows program data to be
manipulated from the console before it is programmed into the PROM.
The SDK-86 is an (minimum mode) 8086-based
prototyping and evaluation kit. It includes the
CPU, RAM, I/O ports and a breadboard area for
interfacing customer circuits. A ROM-based
monitor program is supplied with the kit.
Monitor commands may be entered from an onboard keypad or from a terminal; the monitor
returns results to the SDK-86's on-board LED
display or to a terminal. Monitor commands
allow programs to be entered, run, stopped, and
single-stepped; memory contents can be altered as
well as displayed. The SDK-C86 Software and
Cable Interface connects an SDK-86 to an
Intellec® system. The software supplied with the
cable enables programs to be transferred between
the development system and the SDK-86 to allow
users to develop programs using the text editor,
translators and utilities of the Intellec system and
then download the program to the SDK-86 for
execution.

The ICE-86™ module is an in-circuit emulator
for the 8086 microprocessor. A 40-pin probe
replaces the 8086 in the system under test. This
probe is connected to ICE-86 circuit boards that
in turn plug into the Intellec® chassis. The ICE-86
module emulates the 8086 in the system under test
in response to commands entered through the
Intellec console. These commands allow the user
to debug the system by setting breakpoints, tracing the flow of execution, single-stepping,
examining and altering memory and 110, etc. All
references to program variables and labels are
symbolic (i.e., their PLlM-86 or ASM-86 names).
Software testing can also map "system under
test" memory into the Intellec memory to permit
software testing to begin before prototype hardware has been developed.

1-13

INTRODUCTION

LANGUAGE TRANSLATORS

SOFTWARE DEVELOPMENT UTILITIES

UPP
UNIVERSAL
PROM
PROGRAMMER

INTELLEC® SERIES II MICROCOMPUTER
DEVELOPMENT SYSTEM

ICE-86™ IN-CIRCUIT EMULATOR

SDK-86 SYSTEM DESIGN KIT

iSBC 86/12ATM
SINGLE BOARD COMPUTER

SKD-C86 SOFTWARE
AND CABLE INTERFACE

Figure 1-9. 8086 Family Development Aids
1-14

iSBC 957™ INTELLEC®
iSBC 86/12ATM INTERFACE
AND EXECUTION PACKAGE

Chapter 2
The 8086 and 8088
Central Processing Units

CHAPTER 2
THE 8086 AND 8088
CENTRAL PROCESSING UNITS
This chapter describes the mainstays of the 8086
microprocessor family: the 8086 and 8088 central
processing units (CPUs). The material is divided
into ten sections and generally proceeds from
hardware to software topics as follows:
1. Processor Overview
2. Processor Architecture
3. Memory
4. Input/Output
5. Multiprocessing Features
6. Processor Control and Monitoring
7. Instruction Set

GNO

8. Addressing Modes
9. Programming Facilities
10. Programming Guidelines and Examples

AD15

AD13

A1B/S3

AD12

A17/54

AD11

A18/55

AD10

A19/56

AD.

B"HE/S7

A08

MN/MX

A07

Rii

AD.

HOLD

(RQ/GTO)

ADS

HLOA

(RO/GT1)

AD.

w;;

(lOCK)

A03

M/iO

(52)

A02

OTtR

(~)

A01

DEN

(So)

ADO

ALE

(050)

NMI

INTA

(051)

INTR

The chapter describes the internal operation of
the CPUs in detail. The interaction of the processors with other devices is discussed in functional terms; electrical characteristics, timing, and
other information needed to actually interface
other devices with the 8086 and 8088 are provided
in Chapter 4.

Vcc

AD14

TEST

ClK

READY

GNO

RESET

A1'

A16/S3
A17/54

A18/55

2.1 Processor Overview

A19/56
550

The 8086 and 8088 are closely related thirdgeneration microprocessors. The 8088 is designed
with an 8-bit external data path to memory and
110, while the 8086 can transfer 16 bits at a time.
In almost every other respect the processors are
identical; software written for one CPU will
execute on the other without alteration. The chips
are contained in standard 40-pin dual in-line
packages (figure 2-1) and operate from a single
+5V power source.

(HIGH)

MN/MX

Rii
HOLD

(RO/GTo)

HLDA

tRQ/W)

w;;

(lOCK)
(52)

Dr/A"

The 8086 and 8088 are suitable for an exceptionally wide spectrum of microcomputer applications,and this flexibility is one of their most
outstanding characteristics. Systems can range
from uniprocessor minimal-memory designs
implemented with a handful of chips (figure 2-2),
to multiprocessor systems with up to a megabyte
of memory (figure 2-3).

(Si)

DEN

(So)

ALE

(050)

INTA

(051)

TEST

RESET

MAXIMUM MODE PIN FUNCTIONS (e.g.,
ARE SHOWN IN PARENTHESES.

l'OC'K)

Figure 2-1.8086 and 8088 Central Processing
Units
2-1

8086 AND 8088 CENTRAL PROCESSING UNITS

'"

'"'

'"'

""-

~

,.

I~

110.

I'll

PORTA

_1t..
~

~

PORTB

8155
RAM
I/O
TIMER

PORTe

"I

:
,.

-}CLOCK

- - . . . TIMER

ADDRESS

~
PORTA

B088

4ADDRESS/DATA

CPU

CONTROL

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,. 4

~

8755A
EPROM
I/O

4

,.

110.

110.

~

.
,.....-

~

~

4

828.

CLOCK

8185

1KX8
RAM

GEN.

""---

. ,..

. ...

.....

Figure 2-2. Small8088-Based System

Figure 2-3. 8086/8088/8089 Multiprocessing System
2-2

PORTS

~

8086 AND 8088 CENTRAL PROCESSING UNITS

The large application domain of the 8086 and
8088 is made possible primarily by the processors'
dual operating modes (minimum and maximum
mode) and built-in multiprocessing features.
Several of the 40 CPU pins have dual functions
that are selected by a strapping pin. Configured
in minimum mode, these pins transfer control
signals directly to memory and input/output
devices. In maximum mode these same pins take
on different functions that are helpful in medium
to large ystems, especially systems with mUltiple
processors. The control functions assigned to
these pins in minimum mode are assumed by a
support chip, the 8288 Bus Controller.

The 8086's advantage over the 8088 is attributable
to its 16-bit external data bus. In applications that
manipulate 8-bit quantities extensively, or that
are execution-bound, the 8088 can approach to
within 10070 of the 8086's processing throughput.
The high performance of the 8086 and 8088 is
realized by combining a 16-bit internal data path
with a pipelined architecture that allows instructions to be pre fetched during spare bus cycles.
Also contributing to performance is a compact
instruction format that enables more instructions
to be fetched in a given amount of time.
Software for high-performance 8086 and 8088
systems need not be written in assembly language.
The CPUs are designed to provide direct hardware support for programs written in high-level
languages such as Intel's PLlM-86. Most highlevel languages store variables in memory; the
8086/8088 symmetrical instruction set supports
direct operation on memory operands, including
operands on the stack. The hardware addressing
modes provide efficient, straightforward
implementations of based variables, arrays, arrays of structures and other high-level language
data constructs. A powerful set of memory-tomemory string operations is available for efficient
character data manipulation. Finally, routines
with critical performance requirements that cannot be met with PL/M-86 may be written in
ASM-86 (the 8086/8088 assembly language) and
linked with PLlM-86 code.

The CPUs are designed to operate with the 8089
Input/Output Processor (lOP) and other processors in multiprocessing and distributed processing systems. When used in conjunction with
one or more 8089s, the 8086 and 8088 expand
the applicability of microprocessors into 1/0intensive data processing systems. Built-in coordinating signals and instructions, and electrical
compatibility with Intel's Multibus ™ shared bus
architecture, simplify and reduce the cost of
developing multiple-processor designs.
Both CPUs are substantially more powerful than
any microprocessor previously offered by Intel.
Actual performance, of course, varies from
application to application, but comparisons to the
industry standard 2-MHz 8080A are instructive.
The 8088 is from four to six times more powerful
than the 8080A; the 8086 provides seven to ten
times the 8080A's performance (see figure 2-4).

100

While the 8086 and 8088 are totally new designs,
they make the most of users' existing investments
in systems designed around the 8080/8085
microprocessors. Many of the standard Intel
memory, peripheral control and communication
chips are compatible with the 8086 and the 8088.
Software is developed in the familiar Intellec®
Microcomputer Development System environment, and most existing programs, whether written in ASM-80 or PL/M-80, can be directly converted to run on the 8086 and 8088 .

~

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z

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0:

10

2.2 Processor Architecture

w
~

5w

Microprocessors generally execute a program by
repeatedly cycling through the steps shown below
(this description is somewhat simplified):
1. Fetch the next instruction from memory.
2. Read an operand (if required by the
instruction).

0:

YEAR INTRODUCED

Figure 2-4. Relative Performance of the
8086 and 8088

2-3

8086 AND 8088 CENTRAL PROCESSING UNITS

3.
4.

Execute the instruction.
Write the result (if
instruction) .

required

The two units can operate independently of one
another and are able, under most circumstances,
to extensively overlap instruction fetch with execution. The result is that, in most cases, the time
normally required to fetch instructions "disappears" because the EU executes instructions
that have already been fetched by the BIU. Figure
2-5 illustrates this overlap and compares it with
~raditional microprocessor operation. In the
example, overlapping reduces the elapsed time
required to execute three instructions, and allows
two additional instructions to be prefetched as
well.

by the

In previous CPUs, most of these steps have been
performed serially, or with only a single bus cycle
fetch overlap. The architecture of the 8086 and
8088 CPUs, while performing the same steps,
allocates them to two separate processing units
within the CPU. The execution unit (EU) executes
instructions; the bus interface unit (BIU) fetches
instructions, reads operands and writes results.

! - - - - - - - - - - - - E L A S P E D T I M E - - - - - - - - - - - - i....

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GENERATION
MICROPROCESSOR

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BUS:

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8086/8088
MICROPROCESSOR

INSTRUCTION STREAM
1st INSTRUCTION (ALREADY FETCHED):
EXECUTE AND WRITE RESULT
2nd INSTRUCTION:
EXECUTE ONLY
3rd INSTRUCTION:
READ OPERAND AND EXECUTE
4th INSTRUCTION:
(UNDEFINED)
5th INSTRUCTION:
(UNDEFINED)

Figure 2-5. Overlapped Instruction Fetch and Execution
2-4

IlffW!~~:~!~~11

8086 AND 8088 CENTRAL PROCESSING UNITS

Execution Unit

Bus Interface Unit

The execution units of the 8086 and 8088 are identical (figure 2-6). A 16-bit arithmetic/logic unit
(ALU) in the EU maintains the CPU status and
control flags, and manipulates the general
registers and instruction operands. All registers
and data paths in the EU are 16 bits wide for fast
internal transfers.

The BIUs of the 8086 and 8088 are functionally
identical, but are implemented differently to
match the structure and performance
characteristics of their respective buses.
The BIU performs all bus operations for the EU.
Data is transferred between the CPU and memory
or 110 devices upon demand from the EU. Sections 2.3 and 2.4 describe the interaction of the
BIU with memory and 110 devices.

The EU has no connection to the system bus, the
"outside world." It obtains instructions from a
queue maintained by the BIU. Likewise, when an
instruction requires access to memory or to a
peripheral device, the EU requests the BIU to
obtain or store the data. All addresses
manipulated by the EU are 16 bits wide. The BIU,
however, performs an address relocation that
gives the EU access to the full megabyte of
memory space (see section 2.3).

.....

~

In addition, during periods when the EU is busy
executing instructions, the BIU "looks ahead"
and fetches more instructions from memory. The
instructions are stored in an internal RAM array
called the instruction stream queue. The 8088
instruction queue holds up to four bytes of the
instruction stream, while the 8086 queue can store

EXECUTION UNIT (EU)

BUS INTERFACE UNIT (BIU)

GENERAL
REGISTERS

SEGMENT
REGISTERS

It It

I

OPERANDS

t

Dt

ALU

t

INSTRUCTION
POINTER

t
I

I

I
I
I
I
I

ADDRESS
GENERATION
AND BUS
CONTROL

""II

,..

INSTRUCTION
QUEUE

I

FLAGS

Figure 2-6. Execution and Bus Interface Units (EU and BIU)
2-5

MULTIPLEXED BUS

8086 AND 8088 CENTRAL PROCESSING UNITS

up to six instruction bytes. These queue sizes
allow the BIU to keep the EU supplied with prefetched instructions under most conditions
without monopolizing the system bus. The 8088
BIU fetches another instruction byte whenever
one byte in its queue is empty and there is no
active request for bus access from the EU. The
8086 BIU operates similarly except that it does
not initiate a fetch until there are two empty bytes
in its queue. The 8086 BIU normally obtains two
instruction bytes per fetch; if a program transfer
forces fetching from an odd address, the 8086
BIU automatically reads one byte from the odd
address and then resumes fetching two-byte
words from the subsequent even addresses.

I

H

15

I

8 7

L

0

AX

DATA
GROUP

{

r- - AH- - -.-- -AL - -

ACCUMULATOR

BX
r- - BH- - -.- - BL - -

BASE

I- -

CH -

CX
-.- -

I- -

DH -

~-

CL -

-

DL -

-

15

Under most circumstances the queues contain at
least one byte of the instruction stream and the
EU does not have to wait for instructions to be
fetched. The instructions in the queue are those
stored in the memory locations immediately adjacent to and higher than the instruction currently
being executed. That is, they are the next logical
instructions so long as execution proceeds serially. If the EU executes an instruction that
transfers control to another location, the BIU
resets the queue, fetches the instruction from the
new address, passes it immediately to the EU, and
then begins refilling the queue from the new location. In addition, the BIU suspends instruction
fetching whenever the EU requests a memory or
I/O read or write (except that a fetch already in
progress is completed before executing the EU's
bus request).

DATA
0

SP

POINTER
AND {
INDEX
GROUP

COUNT

STACK
POINTER

BP

BASE
POINTER

SI

SOURCE
INDEX

01

DESTINATION
I NDEX

Figure 2-7. General Registers

some instructions use certain registers implicitly
(see table 2-1) thus allowing compact yet powerful
encoding.
Table 2-1. Implicit Use of General Registers
REGISTER

General Registers
Both CPUs have the same complement of eight
16-bit general registers (figure 2-7). The general
registers are subdivided into two sets of four
registers each: the data registers (sometimes called
the H & L group for "high" and "low"), and the
pointer and index registers (sometimes called the
P & I group).
The data registers are unique in that their upper
(high) and lower halves are separately
addressable. This means that each data register
can be used interchangeably as a 16-bit register,
or as two 8-bit registers. The other CPU registers
always are accessed as 16-bit units only. The data
registers can be used without constraint in most
arithmetic and logic operations. In addition,

OPERATIONS

AX

Word Multiply, Word Divide,
Word 1/0

AL

Byte Multiply, Byte Divide, Byte
1/0, Translate, Decimal Arithmetic

AH

Byte Multiply, Byte Divide

BX

Translate

CX

String Operations, Loops

CL

Variable Shift and Rotate

OX

Word Multiply, Word Divide,
Indirect 1/0

SP

Stack Operations

SI

String Operations

01

String Operations

The pointer and index registers can also participate in most arithmetic and logic operations.
In fact, all eight general registers fit the definition
of "accumulator" as used in first and second
generation microprocessors. The P & I registers
(except for BP) also are used implicitly in some
instructions as shown in table 2-1.

2-6

8086 AND 8088 CENTRAL PROCESSING UNITS

Segment Registers

Flags

The megabyte of 8086 and 8088 memory space is
divided into logical segments of up to 64k bytes
each. (Memory segmentation is described in section 2.3.) The CPU has direct access to four
segments at a time; their base addresses (starting
locations) are contained in the segment registers
(see figure 2-S), The CS register points to the current code segment; instructions are fetched from
this segment. The SS register points to the current
stack segment; stack operations are performed on
locations in this segment. The DS register points
to the current data segment; it generally contains
program variables. The ES register points to the
current extra segment, which also is typically used
for data storage.

The SOS6 and SOSS have six I-bit status flags
(figure 2-9) that the EU posts to reflect certain
properties of the result of an arithmetic or logic

The segment registers are accessible to programs
and can be manipulated with several instructions.
Good programming practice and consideration of
compatibility with future Intel hardware and software products dictate that the segment registers
be used in a disciplined fashion. Section 2.10 provides guidelines for segment register use.

'-------------DIRECTION

.
FmF~Fr:l
~CARRY

STATUS

FLAGS

Lm

PARITY
AUXILIARY CARRY

ZERO
L-------SIGN
L---------avERFLOW
L----------INTERRUPT-ENABLE
L-------------TRAP

Figure 2-9. Flags

operation. A group of instructions is available
that allows a program to alter its execution
depending on the state of these flags, that is, on
the result of a prior operation. Different instructions affect the status flags differently; in general,
however, the flags reflect the following
conditions:

15
CS

CODE
SEGMENT

OS

DATA
SEGMENT

SS

STACK
SEGMENT

ES

EXTRA
SEGMENT

I.

If AF (the auxiliary carry flag) is set, there
has been a carry out of the low nibble into
the high nibble or a borrow from the high
nibble into the low nibble of an S-bit quantity
(low-order byte of a 16-bit quantity). This
flag is used by decimal arithmetic
instructions.

2.

If CF (the carry flag) is set, there has been a
carry out of, or a borrow into, the high-order
bit of the result (S- or 16-bit). The flag is used
by instructions that add and subtract
multibyte numbers. Rotate instructions can
also isolate a bit in memory or a register by
placing it in the carry flag.

3.

If OF (the overflow flag) is set, an arithmetic

Figure 2-8. Segment Registers

Instruction Pointer
The 16-bit instruction pointer (IP) is analogous to
the program counter (PC) in the 8080/S0S5
CPUs. The instruction pointer is updated by the
BIU so that it contains the offset (distance in
bytes) of the next instruction from the beginning
of the current code segment; i.e., IP points to the
next instruction. During normal execution, IP
contains the offset of the next instruction to be
fetched by the BIU; whenever IP is saved on the
stack, however, it first is automatically adjusted
to point to the next instruction to be executed.
Programs do not have direct access to the instruction pointer, but instructions cause it to change
and to be saved on and restored from the stack.

overflow has occurred; that is, a significant
digit has been lost because the size of the
result exceeded the capacity of its destination
location. An Interrupt On Overflow instruction is available that will generate an interrupt in this situation.

2-7

8086 AND 8088 CENTRAL PROCESSING UNITS
4.

The AF, CF, PF, SF, and ZF flags are the same in
both CPU families. The remaining flags and
registers are unique to the 8086 and 8088. This
8080/8085 to 8086 mapping allows most existing
80S0/8085 program code to be directly translated
into 8086/8088 code.

If SF (the sign flag) is set, the high-order bit

of the result is a 1. Since negative binary
numbers are represented in the SOS6 and SOSS
in standard two's complement notation, SF
indicates the sign of the result (0 = positive,
1 = negative).
5.

6.

If PF (the parity flag) is set, the result has

even parity, an even number of I-bits. This
flag can be used to check for data transmission errors.
If ZF (the zero flag) is set, the result of the
operation is O.

Mode Selection
Both processors have a strap pin (MN/MX) that
defines the function of eight CPU pins in the S086
and nine pins in the S088. Connecting MN/MX to
+5V places the CPU in minimum mode. In this
configuration, which is designed for small
systems (roughly one or two boards), the CPU
itself provides the bus control signals needed by
memory and peripherals. When MN/MX is
strapped to ground, the CPU is configured in
maximum mode. In this configuration the CPU
encodes control signals on three lines. An 8288
Bus Controller is added to decode the signals
from the CPU and to provide an expanded set of
control signals to the rest of the system. The CPU
uses the remaining free lines for a new set of
signals designed to help coordinate the activities
of other processors in the system. Sections 2.5
and 2.6 describe the functions of these signals.

Three additional control flags (figure 2-9) can be
set and cleared by programs to alter processor
operations:
1. Setting DF (the direction flag) causes string
instructions to auto-decrement; that is, to
process strings from high addresses to low
addresses, or from "right to left." Clearing
DF causes string instructions to autoincrement, or to process strings from "left to
right."
2.

3.

Setting IF (the interrupt-enable flag) allows
the CPU to recognize external (maskable)
interrupt requests. Clearing IF disables these
interrupts. IF has no affect on either nonmaskable external or internally generated
interrupts.
Setting TF (the trap flag) puts the processor
into single-step mode for debugging. In this
mode, the CPU automatically generates an
internal .interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction. Section 2.10
contains an example showing the use of TF in
a single-step and breakpoint routine.

2.3 Memory
The 8086 and 8088 can accommodate up to
1,048,576 bytes of memory in both minimum and
maximum mode. This section describes how
memory is functionally organized and used.
There are substantial differences in the way
memory components are actually accessed by the
two processors; these differences, which are invisible to programs, are covered in section 4.2,
External Memory Addressing.

8080/8085 Registers and Flag
Correspondence

Storage Organization

The registers, flags and program counter in the
SOSO/SOS5 CPUs all have counterparts in the SOS6
and 808S (see figure 2-10). The A register (accumulator) in the 8080/80S5 corresponds to the
AL register in the 8086 and 8088. The 8080/8085
H & L, B & C, and D & E registers correspond to
registers BH, BL, CH, CL, DH and DL, respectively, in the 80S6 and S088. The 8080/8085 SP
(stack pointer) and PC (program counter) have
their counterparts in the 8086/8088 SP and IP.

From a storage point of view, the 8086 and 80SS
memory spaces are organized as identical arrays
of 8-bit bytes (see figure 2-11). Instructions, byte
data and word data may be freely stored at any
byte address without regard for alignment thereby
saving memory spac'e by allowing code to be
densely packed in memory (see figure 2-12). Oddaddressed (unaligl1ed) word variables, however,
2-8

8086 AND 8088 CENTRAL PROCESSING UNITS

BP

BASE
POINTER

SI

SOURCE
INDEX

01

DESTINATION
INDEX

CS

CODE
SEGMENT

OS

DATA
SEGMENT

SS

STACK
SEGMENT

ES

EXTRA
SEGMENT

Figure 2-10.8080/8085 Register Subset (Shaded)

HIGH MEMORY

LOW MEMORY
OOOOOH

L
7

I_

00001H

00002H

5

§FFFFEH FFFFFH

I II " I I " I IIIII " " "5 §LI"" I " I " "
07

07

1 MEGABYTE

07

I

'0

-I

Figure 2-11. Storage Organization

Figure 2-12. Instruction and Variable Storage
2-9

8086 AN08088 CENTRAL PROCESSING UNITS
do not take advantage of the 8086's ability to
transfer 16-bits at a time. Instruction alignment
does not materially affect the performance of
either processor.

Segmentation
8086 and 8088 programs "view" the megabyte of
memory space as a group of segments that are
defined by the application. A segment is a logical
unit of memory that may be up to 64k bytes long.
Each segment is made up of contiguous memory
locations and is an independent, separatelyaddressable unit. Every segment is assigned (by
software) a base address, which is its starting
location in the memory space. All segments begin
on 16-byte memory boundaries. There are no
other restrictions on segment locations; segments
may be adjacent, disjoint, partially overlapped,
or fully overlapped (see figure 2-15). A physical
memory location may be mapped into (contained
in) one or more logical segments.

Following Intel convention, word data always is
stored with the most-significant byte in the higher
memory location (see figure 2-13). Most of the
time this storage convention is ,"invisible" to
anyone working with the processors; exceptions
may occur when monitoring the system bus or
when reading memory dumps.
A special class of data is stored as doublewords;
i.e., two consecutive words. These are called
pointers and are used to address data and code
that are outside the currently-addressable
segments. The lower-addressed word of a pointer
contains an offset value, and the higher-addressed
word contains a segment base address. Each word
is stored conventionally with the higher-addressed
byte containing the most-significant eight bits of
the word (see figure 2-14).

724H

The segment registers point to (contain the base
address values of) the four currently addressable
segments (see figure 2-16). Programs obtain
access to code and data in other segments by
changing the segment registers to point to the
desired segments.

Every application will define and use segments
differently. The currently addressable segments
provide a generous work space: 64k bytes for
code, a 64k byte stack and 128k bytes of data
storage. Many applications can be written to
simply initialize the segment registers and then
forget them. Larger applications should be
designed with careful consideration given to segment definition.

725H

VALUE OF WORD STORED AT 724H: 5502H

Figure 2-13. Storage of Word Variables

VALUE OF POINTER STORED AT 4H:
SEGMENT BASE ADDRESS: 3B4CH
OFFSET: 65H

Figure 2-14. Storage of Pointer Variables
2-10

8086 AND 8088 CENTRAL PROCESSING UNITS

FULLY

I

OVERLAPP~D

SEGMENT 0

PARTLY

OVERLAP~I
CONTIGUOUS~
~ -I SEGMENTC

I

SEGMENT A

I

SEGMENT B

I

LOGICAL
SEGMENTS

I
I

~1___-+1___-+1___-+1___~17 }~1~S6W

t

t

OH

10000H

t

20000H

t

30000H

Figure 2-15. Segment Locations in Physical Memory

The segmented structure of the 8086/8088
memory space supports modular software design
by discouraging huge, monolithic programs. The
segments also can be used to advantage in many
programming situations. Take, for example, the
case of an editor for several on-line terminals. A
64k text buffer (probably an extra segment) could
be assigned to each terminal. A single program
could maintain all the buffers by simply changing
register ES to point to the buffer of the terminal
requiring service.

FFFFFH

DATA:

OS:

B

CODE:

CS:

E

STACK: SS:

H

EXTRA: ES:

l--1--,
1---, II

h

I
I I

I
I I
I L
I

o

Physical Address Generation

-:

[J

It is useful to think of every memory location as
having two kinds of addresses, physical and
logical. A physical address is the 20-bit value that
uniquely identifies each byte location in the
megabyte memory space. Physical addresses may
range from OH through FFFFFH. All exchanges
between the CPU and memory components use
this physical address.

L_

Programs deal with logical, rather than physical
addresses and allow code to be developed without
prior knowledge of where the code is to be located
in memory and facilitate dynamic management of
memory resources. A logical address consists of a
segment base value and an offset value. For any
given memory location, the segment base value

OH

Figure 2-16. Currently Addressable Segments
2-11

8086 AND 8088 CENTRAL PROCESSING UNITS
locates the first byte of the containing segment
and the offset value is the distance, in bytes, of
the target location from the beginning of the
segment. Segment base and offset values are
unsigned 16-bit quantities; the lowest-addressed
byte in a segment has an offset of o. Many different logical addresses can map to the same
physical location as shown in figure 2-17. In
figure 2-17, physical memory location 2C3H is
contained in two different overlapping segments,
one beginning at 2BOH and the other at 2COH.

2-2). Instructions always are fetched from the current code segment; IP contains the offset of the
target instruction from the beginning of the segment. Stack instructions always operate on the
current stack segment; SP contains the offset of
the top of the stack. Most variables (memory
operands) are assumed to reside in the current
data segment, although a program can instruct
the BIU to access a variable in one of the other
currently addressable segments. The offset of a
memory variable is calculated by the EU. This
calculation is based on the addressing mode
specified in the instruction; the result is called the
operand's effective address (EA). Section 2.8
covers addressing modes and effective address
calculation in detail.

Whenever the BIU accesses memory-to fetch an
instruction or to obtain or store a variable-it
generates a physical address from a logical
address. This is done by shifting the segment base
value four bit positions and adding the offset as
illustrated in figure 2-18. Note that this addition
process provides for modulo 64k addressing
(addresses wrap around from the end of a segment to the beginning of the same segment).

Strings are addressed differently than other
variables. The source operand of a string instruction is assumed to lie in the current data segment,
but another currently addressable segment may be
specified. Its offset is taken from register SI, the
source index register. The destination operand of
a string instruction always resides in the current

The BIU obtains the logical address of a memory
location from different sources depending on the
type of reference that is being made (see table

r

'r'
2 C4H

PHYSICAL
ADDRESS

2 C3H

t

;-

2 C2H

OFFSET
(3H)
SEGMENT
BASE

2 C1H

•I

2 COH
2 BFH
2 BEH
2 BDH
2 BCH
2 BBH

LOGICAL
ADDRESSES --<

2 BAH

OFFSET
(13H)

2 B9H
2 BaH
2 B7H
2 B6H
2 B5H
2 B4H
2 B3H
2 B2H
2 B1H

.... SEGMENT
BASE

2 BOH

"
Figure 2-17. Logical and Physical Addresses
2-12

"

8086 AND 8088 CENTRAL PROCESSING UNITS

rIFTLEFT4 BITS I

I"';9~--""t-"'"i -!OI
r ---.....:.-,....,
1

2

3

4

I0

+

I

0

1

2

2

2

t

15
3

n~~~ENT}
0

.....----_

I

0

r--~-~

1 2 3 4

15

I. . .

0 0 2 2

15

-------J

LOGICAL
ADDRESS

IOFFSET

0

0

6

2

I

~19~--"+--~O

PHYSICAL ADDRESS

TO MEMORY

Figure 2-18. Physical Address Generation

Table 2-2. Logical Address Sources
TYPE OF MEMORY REFERENCE

Instruction Fetch
Stack Operation
Variable (except following)
String Source
String Destination
BP Used As Base Register

DEFAULT
SEGMENT
BASE

ALTERNATE
SEGMENT
BASE

OFFSET

CS
SS
DS
DS
ES
SS

NONE
NONE
CS,ES,SS
CS,ES,SS
NONE
CS,DS,ES

IP
SP
Effective Address
SI
DI
Effective Address

extra segment; its offset is taken from DI, the
destination index register. The string instructions
automatically adjust SI and DI as they process the
strings one byte or word at a time.

Dynamically Relocatable Code
The segmented memory structure of the 8086 and
8088 makes it possible to write programs that are
position-independent, or dynamically relocatable.
Dynamic relocation allows a multiprogramming
or multitasking system to make particularly effective use of available memory. Inactive programs
can be written to disk and the space they occupied
allocated to other programs. If a disk-resident
program is needed later, it can be read back into
any available memory location and restarted.
Similarly, if a program needs a large contiguous
block of storage, and the total amount is available
only in nonadjacent fragments, other program
segments can be compacted to free up a continuous space. This process is shown graphically
in figure 2-19.

When register BP, the base pointer register, is
designated as a base register in an instruction, the
variable is assumed to reside in the current stack
segment. Register BP thus provides a convenient
way to address data on the stack; BP can be used,
however, to access data in any of the other currently addressable segments.
In most cases, the BIU's segment assumptions are
a convenience to programmers. It is possible,
however, for a programmer to explicitly direct the
BIU to access a variable in any of the currently
addressable segments (the only exception is the
destination operand of a string instruction which
must be in the extra segment). This is done by
preceding an instruction with a segment override
prefix. This one-byte machine instruction tells the
BIU which segment register to use to access a
variable referenced in the following instruction.

In order to be dynamically relocatable, a program
must not load or alter its segment registers and
must not transfer directly to a location outside the
current code segment. In other words, all offsets
in the program must be relative to fixed values
2-13

8086 AND 8088 CENTRAL PROCESSING UNITS

AFTER RELOCATION

BEFORE RELOCATION

CODE
SEGMENT

I
STACK
SEGMENT

CS

I

.----

-

CS

SS

SS

OS

OS

r---

ES

ES

f-

CODE
SEGMENT
STACK
SEGMENT
DATA
SEGMENT
EXTRA
SEGMENT

DATA
SEGMENT

EXTRA
SEGEMENT

C]FREESPACE

Figure 2-19. Dynamic Code Relocation
stack segment's base address. Note, however, that
the stack's base address (contained in SS) is not
the "bottom" of the stack.

contained in the segment registers. This allows the
program to be moved anywhere in memory as
long as the segment registers are updated to point
to the new base addresses. Section 2.10 contains
an example that illustrates dynamic code
relocation.

8086 and 8088 stacks are 16 bits wide; instructions
that operate on a stack add and remove stack
items one word at a time. An item is pushed onto
the stack (see figure 2-20) by decrementing SP by
2 and writing the item at the new TOS. An item is
popped off the stack by copying it from TOS and
then incrementing SP by 2. In other words, the
stack grows down in memory toward its base
address. Stack operations never move items on
the stack, nor do they erase them. The top of the
stack changes only as a result of updating the
stack pointer.

Stack Implementation
Stacks in the 8086 and 8088 are implemented in
memory and are located by the stack segment
register (SS) and the stack pointer register (SP). A
system may have an unlimited number of stacks,
and a stack may be up to 64k bytes long, the maximum length of a segment. (An attempt to expand
a stack beyond 64k bytes overwrites the beginning
of the stack.) One stack is directly addressable at
a time; this is the current stack, often referred to
simply as "the" stack. SS contains the base
address of the current stack and SP points to the
top of the stack (TOS). In other words, SP contains the offset of the top of the stack from the

Dedicated and Reserved Memory
Locations
Two areas in extreme low and high memory are
dedicated to specific processor functions or are
reserved by Intel Corporation for use by Intel
2-14

8086 AND 8088 CENTRAL PROCESSING UNITS
POPAX
POPBX
AX

PUSHAX
EXISTING
STACK

TOS

[

1062

00

11

1060

22

33

105E 44

55

105B 66

77

105A 88

99

AxI12 1341-1

r

t

1058 AA BB

>-

~13

01
1056
1054 45

23

1052 89

AB

UJUl
a:W

CD EF
1050::

~~

}

67

m~

c..J:

10

50

I SS

00

08

SP

TOS

r

Bx[B![AAl-l

r

1062

00

11

1060

22

33

105E

44

55

105B

66

77

105A

88

99

1058

AA BB

1056

34

12

1054 45

67

89

AB

1052

['t2]"'34]- l

CD EF
1050:
:

I
I
I
I
..- J

00

11

1060 22

33

105E 44

55

1062

TOS

105C 66

77

105A 88

99

105B AA BB
1056

34

12

1054

45

67

1052

89

AB

:

I I
I I
I I
I :

JI
-~

r1050~

10

50

Iss

00

06

SP

~SS
00

OA SP

STACK OPERATION FOR CODE SEQUENCE
PUSH AX
POPAX
POPBX

Figure 2-20. Stack Operation

hardware and software products. As shown in
figure 2-21, the location are: OH throgh 7FH (128
bytes) and FFFFOH through FFFFFH (16 bytes).
These areas are used for interrupt and system
reset processing 8086 and 8088 application
systems should not use these areas for any other
purpose. Doing so may make these systems
incompatible with future Intel products.

totally transparent to software. This allows maximum data packing where memory space is
constrained.

8086/8088 Memory Access
Differences

The 8086 always fetches the instruction stream in
words from even addresses except that the first
fetch after a program transfer to an odd address
obtains a byte. The instruction stream is
disassembled inside the processor and instruction
alignment will not materially affect the performance of most systems.

The 8086 can access either 8 or 16 bits of memory
at a time. If an instruction refers to a word
variable and that variable is located at an evennumbered address, the 8086 accesses the complete
word in one bus cycle. If the word is located at an
odd-numbered address, the 8086 accesses the
word one byte at a time in two consecutive bus
cycles.

The 8088 always accesses memory in bytes. Word
operands are accessed in two bus cycles regardless
of their alignment. Instructions also are fetched
one byte at a time. Although alignment of word
operands does not affect the performance of the
8088, locating 16-bit data on even addresses will
insure maximum throughput if the system is ever
transferred to an 8086.

To maximize throughput in 8086-based systems,
16-bit data should be stored at even addresses
(should be word-aligned). This is particularly true
of stacks. Unaligned stacks can slow a system's
response to interrupts. Nevertheless, except for
the performance penalty, word alignment is

2.4 Input/Output
The 8086 and 8088 have a versatile set of input/output facilities. Both processors provide a
large lIO space that is separate from the memory
2-15

Mnemonics © Intel. 1978

SOS6 ANOSOSS CENTRAL PROCESSING UNITS
Restricted 1/0 Locations
Locations F8H through FFH (eight of the 64k
locations) in the 1/0 space are reserved by Intel
Corporation for use by future Intel hardware and
software products. Using these locations for any
other purpose may inhibit compatibility with
future Intel products.

FFFFFH
RESERVED
FFFFCH
FFFFBH
DEDICATED
FFFFOH
FFFEFH

I

OPEN

SOS6/S0SS 1/0 Access Differences
OPEN

The 8086 can transfer either 8 or 16 bits at a time
to a device located in the I/O space. A 16-bit
device should be located at an even address so
that the word will be transferred in a single bus
cycle. An 8-bit device may be located at either an
even or odd address; however, the internal
registers in a given device must be assigned alleven or all-odd addresses.

BOH
7FH
RESERVED
14H
13H
DEDICATED

OPEN
OH

MEMORY

"'-_ _ _ _..... OH
liD

The 8088 transfers one byte per bus cycle. If a
16-bit device is used in the 8088 I/O space, it must
be capable of transferring words in the same
fashion, i.e., eight bits at a time in two bus cycles.
(The 8089 Input/Output Processor can provide a
straightforward interface between the 8088 and a
16-bit I/O device.) An 8-bit device may be located
at odd or even addresses in the 8088 I/O space
and internal registers maybe assigned consecutive
addresses (e.g., IH, 2H, 3H). Assigning all-odd
or all-even addresses to these registers, however,
will simplify transferring the system to an 8086
CPU.

Figure 2-21. Reserved and Dedicated Memory
and I/O Locations
space, and instructions that transfer data between
the CPU and devices located in the I/O space.
I/O devices also may be placed in the memory
space to bring the power of the full instruction set
and addressing modes to input/output processing. For high-speed transfers, the CPUs may
be used with traditional direct memory access
controllers or the 8089 Input/Output Processor.

Memory-Mapped 1/0
I/O devices also may be placed in the 8086/8088
memory space. As long as the devices respond like
memory components, the CPU does not know the
dif f erence.

InputlOutput Space
The 808618088 I/O space can accommodate up to
64k 8-bit ports or up to 32k 16-bit ports. The IN
and OUT (input and output) instructions transfer
data between the accumulator (AL for byte
transfers, AX for word transfers) and ports
located in the I/O space.

Memory-mapped I/O provides additional programming flexibility. Any instruction that
references memory may be used to access an I/O
port located in the memory space. For example,
the MOV (move) instruction can transfer data
between any 8086/8088 register and a port, or the
AND, OR and TEST instructions may be used to
manipulate bits in I/O device registers. In addition, memory-mapped I/O can take advantage of
the 8086/8088 memory addressing modes. A
group of terminals, for example, could be treated
as an array in memory with an index register

The I/O space is not segmented; to access a port,
the BIU simply places the port address (O-64k) on
the lower 16 lines of the address bus. Different
forms of the I/O instructions allow the address to
be specified as a fixed value in the instruction or
as a variable taken from register DX.
Mnemonics © Intel, 1978

2-16

8086 AND 8088 CENTRAL PROCESSING UNITS
selecting a terminal in the array. Section 2.10 provides examples of using the instruction set and
addressing modes with memory-mapped liD.

2.5 Multiprocessing Features
As microprocessor prices have declined,
multiprocessing (using two or more coordinated
processors in a system) has become an increasingly attractive design alternative. Performance
can be substantially improved by distributing
system tasks among separate, concurrently executing processors. In addition, multiprocessing
encourages a modular approach to design, usually
resulting in systems that are more easily maintained and enhanced. For example, figure 2-22
shows a multiprocessor system in which liD
activities have been delegated to an 8089 lOP.
Should an 110 device in the system be changed
(e.g., a hard disk substituted for a floppy), the
impact of the modification is confined to the 110
subsystem and is transparent to the CPU and to
the application software.

Of course, a price must be paid for the added programming flexibility that memory-mapped liD
provides. Dedicating part of the memory space to
liD devices reduces the number of addresses
available for memory, although with a megabyte
of memory space this should rarely be a constraint. Memory reference instructions also take
longer to execute and are somewhat tess compact
than the simpler IN and OUT instructions.

Direct Memory Access
When configured in minimum mode, the 8086
and 8088 provide HOLD (hold) and HLDA (hold
acknowledge) signals that are compatible with
traditional DMA controllers such as the 8257 and
8237. A DMA controller can request Use of the
bus for direct transfer of data between an liD
device and memory by activating HOLD. The
CPU will complete the.current bus cycle, if one is
in progress, and then issue HLDA, granting the
bus to the DMA controller. The CPU will not
attempt to use the bus until HOLD goes inactive.

The 8086 and 8088 are designed for the
multiprocessing environment. They have built-in
features that help solve the coordination problems that have discouraged multiprocessing
system development in the past.

Bus Lock

The 8086 addresses memory that is physically
organized in two separate banks, one containing
even-addressed bytes and one containing odd-addressed bytes. An8-bit DMA controller must
alternately select these banks to access logically
adjacent bytes in memory. The 8089 provides a
simple way to interface a high-speed 8-bit device
to an 8086-based system (see Chapter 3).

When configured in maximum mode, the 8086
and 8088 provide the LOCK (bus lock) signal.
The BIU activates LOCK when the EU executes
the one-byte LOCK prefix instruction. The
LOCK signal remains active throughout execution of the instruction that follows the LOCK
prefix. Interrupts are not affected by the LOCK
prefix. If another processor requests use of the
bus (via the request! grant lines, which are
discussed shortly), the CPU records the request,
but does not honor it until execution of the locked
instruction has been completed.

8089 Input/Output Processor (lOP)
The 8086 and 8088 are designed to be used with
the 8089 in high-performance 110 applications.
The 8089 conceptually resembles a
microprocessor with two DMA channels and an
instruction set specifically tailored for liD operations. Unlike simple DMA controllers, the 8089
can service liD devices directly, removing this
task from the CPU. In addition, it can transfer
data on its own bus or on the system bus, can
match 8- or 16-bit peripherals to 8- or 16-bit
buses, and can transfer data from memory to
memory and from, 110 device to 110 device.
Chapter 3 describes the 8089 in detail.

Note that the L5"CK signal remains active .for the
duration of a single instruction. If two consecutive instructions are each preceded by a
LOCK prefix, there will still be an unlocked
period between these instructions. In the case of a
locked repeated string instruction, LOCK does
remain active for the duration of the block
operation.
When the 8086 or 8088 is configured in minimum
mode, the LOCK signal is not available. The
LOCK prefix can be used, however, to delay the
2-17

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

I----~~~-I-----~~~--~

I

APPLICATION
PROGRAMS

I

OR

I.~_"""""'

~o~~ ~

I
II
L __

I/O PROGRAMS

I

lID BUFFERS

t__18
i
t
.'
DATA

I
18086
I
I

II

I'

SYSTEM BUS

I
I

~A.!!'!....SYSTE~

__

810
08p9

.4~~....~..~
~

lID
DEVICES

--1 __ '- ~O~B~TEM

,

110
DEVICES
___

I

J

Figure 2-22. Multiprocessing System

generation of an HLDA response to a HOLD
request until execution of the locked instruction is
completed.

that it is available. They likewise agree to set the
semaphore when they are using the resource and
to clear it when they are finished.

The LOCK signal provides information only. It is
the responsibility of other processors on the
shared bus to not attempt to obtain the bus while
LOCK is active. If the system uses 8289 Bus
Arbiters to control access to the shared bus, the
8289's accept LOCK as an input and do not relinquish the bus while this signal is active.

The XCHG instruction can obtain the current
value of the semaphore and set it to "busy" in a
single instruction. The instruction, however,
requires two bus cycles to swap 8-bit values. It is
possible for another processor to obtain the bus
between these two cycles and to gain access to the
partially-updated semaphore. This can be
prevented by preceding the XCHG instruction
with a LOCK prefix, as illustrated in figure 2-25.
The bus lock establishes control over access to the
semaphore and thus to the shared resource.

LOCK may be used in multiprocessing systems to
coordinate access to a common resource, such as
a buffer or a pointer. If access to the resource is
not controlled, one processor can read an
erroneous value from the resource when another
processor is updating it (see figure 2-23).

WAIT and TEST
The 8086 and 8088 (in either maximum or
minimum mode) can be synchronized to an external event with the WAIT (wait for TEST) instruction and the TEST input signal. When the EU
executes aWAIT instruction, the result depends
on the state of the TEST input line. If TEST is
inactive, the processor enters an idle state and
repeatedly retests the TEST line at five-clock
intervals. If TEST is active, execution continues
with the instruction following the WAIT.

Access can be controlled (see figure 2-24) by using
the LOCK prefix in conjunction with the XCHG
(exchange register with memory) instruction. The
basis for controlling access to a given resource is a
semaphore, a software-settable flag or switch that
indicates whether the resource is "available"
(semaphore=O) or "busy" (semaphore= 1). Processors that share the bus agree by convention not
to use the resource unless the semaphore indicates
Mnemonics CS Intel, 1978

2-18

8086 AND 8088 CENTRAL PROCESSING UNITS

Escape

BUS CYCLE
0

2

SHARED POINTER
IN MEMORY

The ESC (escape) instruction provides a way for
another processor to obtain an instruction and/or
a memory operand from an 8086/8088 program.
When used in conjunction with WAIT and TEST,
ESC can initiate a "subroutine" that executes
concurrently in another processor (see figure

PROCESSOR ACTIVITIES

105 I 2214C I 1B 1
1C2 1 5914C 11 B 1
1C2 1 5914C 11 B 1
1C2 1 59 1 31 I 05 1

2-26).
"A" UPDATES 1 WORD

Six bits in the ESC instruction may be specified by
the programmer when the instruction is written.
By monitoring the 8086/8088 bus and control
lines, another processor can capture the ESC
instruction when it is fetched by the BIU. The six
bits may then direct the external processor to perform some predefined activity.

"B" READS PARTIALLY
UPDATED VALUE
"A" COMPLETES UPDATE

If the 8086/8088 is configured in maximum

mode, the external processor, having determined
that an ESC has been fetched, can monitor QSO

Figure 2-23. Uncontrolled Access to Shared
Resource

BUSCYCLE

SEMAPHORE

0

0

2

4

0

7

8
0

SHARED POINTER
IN MEMORY

PROCESSOR ACTIVITIES

105 122

4C 11B

105 I 22

4C I 1B

"A" OBTAINS EXCLUSIVE
USE

IC2 159

4C 11B

"A" UPDATES 1 WORD

4C,1B

"B" TESTS SEMAPHORE
AND WAITS

31 ,05

"A" COMPLETES UPDATE

31 ,05

"B" TESTS SEMAPHORE
AND WAITS

31 ,05

"A" RELEASES RESOURCE

31 ,05

"B" OBTAINS
EXCLUSIVE USE

31 105

"B" READS
UPDATED VALUE

31 ,05

"B" RELEASES RESOURCE

IC2 159
IC2 1 59
IC2 1 59
IC2 1 59
IC2 159
IC2 1 59
IC2 159

Figure 2-24. Controlled Access to Shared Resource
2-19

Mnemonics © Intel, 1978

8086 AN08088 CENTRAL PROCESSING UNITS

MOV
GETSEMA·
PHORE &
SET "BUSY"

and QSl (the queue status lines, discussed in section 2,6) and determine when the ESC instruction
is executed. If the instruction references memory
the external processor can then monitor the bus
and capture the operand's physical address
and/or the operand itself.

AL,l

WAIT: LOCK XCHG AL, SEMAPHORE

Note that fetching an ESC instruction is not tantamount to executing it. The ESC may be preceded by a jump that causes the queue to be
reinitialized. This event also can be determined
from the queue status lines,

BUSY(l)
TEST
JNZ

AL,AL
WAIT

Request/Grant Lines

r:;;--,

When the 8086 or 8088 is configured in maximum
mode, the HOLD and HLDA lines evolve into
two more sophisticated signals called RQ/GTO
and RQ/GTl. These are bidirectional lines that
can be used to share a local bus between an 8086
or 8088 and two other processors via a handshake
sequence.

L...:ESOURC:..J

T
SET
SEMAPHORE
"AVAILABLE"

(

MOV

SEMAPHORE,O

The request/grant sequence is a three-phase cycle:
request, grant and release. First, the processor
desiring the bus pulses a request/grant line. The
CPU returns a pulse on the same line indicating
that it is entering the "hold acknowledge" state
and is relinquishing the bus. The BIU is logically
disconnected from the bus during this period. The

EXIT)

Figure 2-25. Using XCHG and LOCK

PROCESSOR

"A"

Figure 2-26. Using ESC with WAIT and TEST
Mnemonics © Intel, 1978

2-20

8086 AND 8088 CENTRAL PROCESSING UNITS

EU, however, will continue to execute instructions until an instruction requires bus access or
the queue is emptied, whichever occurs first.
When the other processor has finished with the
bus, it sends a final pulse to the 8086/8088 indicating that the request has ended and that the
CPU may reclaim the bus.

time, and to obtain compatibility with the wide
variety of boards available in the iSBC product
line.
The Multibus architecture provides a versatile
communications channel that can be used to coordinate a wide variety of computing modules (see
figure 2-27). Modules in a Multibus system are
designated as masters or slaves. Masters may
obtain use of the bus and initiate data transfers on
it. Slaves are the objects of data transfers only.
The Multibus architecture allows both 8- and 16bit masters to be intermixed in a system. In addition to 16 data lines, the bus design provides 20
address lines, eight multilevel interrupt lines, and
control and arbitration lines. An auxiliary power
bus also is provided to route standby power to
memories if the normal supply fails.

RQ/GTO has higher priority than RQ/GTl. If
requests arrive simultaneously on both lines, the
~nt~es to the processor on RQ/GTO and
RQ/GTl is acknowledged after the bus has been
returned to the CPU. If, however, a request
arrives on RQ/GTO while the CPU is processing a
prior request on RQ/GTl, the second r~est is
not honored until the processor on RQ/GTI
releases the bus.

Multibus™ Architecture

The Multibus architecture maintains its own
clock, independent of the clocks of the modules it
links together. This allows different speed masters
to share the bus and allows masters to operate
asynchronously with respect to each other. The
arbitration logic of the bus permit slow-speed
masters to compete equably for use of the bus.
Once a module has obtained the bus, however,
transfer speeds are dependent only on the
capabilities of the transmitting and receiving
modules. Finally, the Multibus standard defines
the form factors and physical requirements of
modules that communicate on this bus. For a
complete description of the Multibus architec-

Intel has designed a general-purpose
multiprocessing bus called the Multibus. This is
the standard design used in iSBCTM single-board
microcomputer products. Many other manufacturers offer products that are compatible with the
Multibus architecture as well. When the 8086 and
8088 are configured in maximum mode, the 8288
Bus Controller outputs signals that are electrically
compatible with the Multibus protocol. Designers
of multiprocessing systems may want to consider
using the Multibus architecture in the design of
their products to reduce development cost and

MASTER

WITH

MASTER

1/0 SLAVE

MEMORY SLAVE

BUS·ACCESSIBLE
MEMORY

.1 ,[[{ fie :I{ 'f"I 'f .1
...oj

...oj

""

U)
U)

~

!;(

~

coo
..

..

0

..

. ..

~

w

I-

0
0

o

a:

w

U)

::>

.
'"

z

..

""
0

0

MULTIBUSTM INTERFACE

Figure 2-27. Multibus™-Based System
2-21

Ii:
::>
a:
a:
w

I-

~

.

8086 AND 8088 CENTRAL PROCESSINGUNtTS
and 8088 can handle up to 256 different interrupt
types. Interrupts may be initiated by devices
external to the CPU; in addition, they also may be
triggered by software interrupt instructions and,
under certain conditions, by the CPU itself (see
figure 2-28). Figure 2-29 illustrates the basic
response of the 8086 and 8088 to an interrupt.
The next sections elaborate on the information
presented in this drawing.

ture, refer to the Intel Multibus Specification
(document number 9800683) and Application
Note 28A, "Intel Multibus Interfacing."

8289 Bus Arbiter
Multiprocessor systems require a means of coordinating the processors' use of the shared bus.
The 8289 Bus Arbiter works in conjunction with
the 8288 Bus Controller to provide this control
for 8086- and 8088-based systems. It is compatible with the Multibus architecture and can be used
in other shared-bus designs as well.

External Interrupts
The 8086 and 8088 have two lines that external
devices may use to signal interrupts (lNTR and
NMI). The INTR (Interrupt Request) line is
usually driven by an Intel® 8259A Programmable
Interrupt Controller (PIC), which is in turn connected to the devices that need interrupt services.
The 8259A is a very flexible circuit that is controlled by software commands from the 8086 or
8088 (the PIC appears as a set of liD ports to the
software). Its main job is to accept interrupt
requests from the devices attached to it, determine which requesting device has the highest
priority, and then activate the 8086/8088 INTR
line if the selected device has higher priority than
the device currently being serviced (if there is
one).

The 8289 eliminates race conditions, resolves bus
contention and matches processors operating
asynchronously with respect to each other. Each
processor on the bus is assigned a different priority. When simultaneous requests for the bus
arrive, the 8289 resolves the contention and grants
the bus to the processor with the highest priority;
three different prioritizing techniques may be
used. Chapter 4 discusses the 8289 in more detail.

2.6 Processor Control and
Monitoring
Interrupts

When INTR is active, the CPU takes different
action depending on the state of the interruptenable flag (IF). No action takes place, however,
until the currently-executing instruction has been

The 8086 and 8088 have a simple and versatile
interrupt system. Every interrupt is assigned a
type code that identifies it to the CPU. The 8086

NON·MASKABLE
INTERRUPT
REQUEST

I

I

r--------t~-------,

I

II

I

INTERRUPTI
LOGIC

I

:

I

II
I

INT n
INSTR.

I
I

•

t

INTO
INSTR.

t·
DIVIDE
ERROR

IINTR

I

I

:

SINGLE·
STEP
(TF=1)

II
I

L_________________
8086/8088 CPU

8259A

I

~

Figure 2-28. Interrupt Sources
2-22

------

MASKABLE
INTERRUPT
REQUESTS

8086 AND 8088 CENTRAL PROCESSING UNITS

Figure 2-29. Interrupt Processing Sequence
2-23

8086 AND 8088 CENTRAL PROCESSING UNITS

completed. * Then, if IF is clear (meaning that
interrupts signaled on INTR are masked or disabled), the CPU ignores the interrupt request and
processes the next instruction. The INTR signal is
not latched by the CPU, so it must be held active
until a response is received or the request is
withdrawn. If interrupts on INTR are enabled (if
IF is set), then the CPU recognizes the interrupt
request and processes it. Interrupt requests arriving on INTR can be enabled by executing an STI
(set interrupt-enable flag) instruction, and disabled by executing a CLI (clear interrupt-enable
flag) instruction. They also may be selectively
masked (some types enabled, some disabled) by
writing commands to the 8259A. It should be
noted that in order to reduce the likelihood of
excessive stack buildup, the STI and IRET
instructions will reenable interrupts only after
the end of the following instruction.

An external interrupt request also may arrive on
another CPU line, NMI (non-maskable interrupt). This line is edge-triggered (lNTR is leveltriggered) and is generally used to signal the CPU
of a "catastrophic" event, such as the imminent
loss of power, memory error detection or bus
parity error. Interrupt requests arriving on NMI
cannot be disabled, are latched by the CPU, and
have higher priority than an interrupt request on
INTR. If an interrupt request arrives on both
lines during the execution of an instruction, NMI
will be recognized first. Non-maskable interrupts
are predefined as type 2; the processor does not
need to be supplied with a type code to call the
NMI procedure, and it does not run the INT A bus
cycles in response to a request on NMI.
The time required for the CPU to recognize an
external interrupt request (interrupt latency)
depends on how many clock periods remain in the
execution of the current instruction. On the
average, the longest latency occurs when a
multiplication, division or variable-bit shift or
rotate instruction is executing when the interrupt
request arrives (see section 2.7 for detailed
instruction timing data). As mentioned previously, in a few cases, worst-case latency will
span two instructions rather than one.

The CPU acknowledges the interrupt request by
executing two consecutive interrupt acknowledge
(INTA) bus cycles. If a bus hold request arrives
(via the HOLD or request/grant lines) during the
INT A cycles, it is not honored until the cycles
have been completed. In addition, if the CPU is
configured in maximum mode, it activates the
LOCK signal during these cycles to indicate to
other processors that they should not attempt to
obtain the bus. The first cycle signals the 8259A
that the request has been honored. During the
second INT A cycle, the 8259A responds by placing a byte on the data bus that contains the interrupt type (0-255) associated with the device
requesting service. (The type assignment is made
when the 8259A is initialized by software in the
8086 or 8088.) The CPU reads this type code and
uses it to call the corresponding interrupt
procedure.

Internal Interrupts
An INT (interrupt) instruction generates an interrupt immediately upon completion of its execution. The interrupt type coded into the instruction
supplies the CPU with the type code needed to
call the procedure to process the interrupt. Since
any type code may be specified, software interrupts may be used to test interrupt procedures
written to service external devices.

"There are a few cases in which an interrupt request is not recognized until after the following instruction. Repeat, LOCK
and segment override prefixes are considered "part of" the instructions they prefix; no interrupt is recognized between
execution of a prefix and an instruction. A MOV (move) to segment register instruction and a POP segment register
instruction are treated similarly: no interrupt is recognized until after the following instruction. This mechanism protects
a program that is changing to a new stack (by updating SS and SP). If an interrupt were recognized after SS had been
changed, but before SP had been altered, the processor would push the flags, CS and IP into the wrong area of memory.
It follows from this that whenever a segment register and another value must be updated together, the segment register
should be changed first, followed immediately by the instruction that changes the other value. There are also two cases,
WAIT and repeated string instructions, where an interrupt request is recognized in the middle of an instruction. In these
cases, interrupts are accepted after any completed primitive operation or wait test cycle.

Mnemonics © Intel, 1978

2-24

8086 AND 8088 CENTRAL PROCESSING UNITS

If the overflow flag (OF) is set,an INTO (inter-

2.

No INT A bus cycles are run.

rupt on overflow) instruction generates a type 4
interrupt immediately upon completion of its
execution.

3.

Internal interrupts cannot be disabled, except
for single-step.

4.

Any internal interrupt (except single-step)
has higher priority than any external interrupt (see table 2-3). If interrupt requests
arrive on NMI and/or INTR during execution of an instruction that causes an internal
interrupt (e.g., divide error), the internal
interrupt is processed first.

The CPU itself generates a type 0 interrupt
immediately following execution of a DIY or
IDlY (divide, integer divide) instruction if the
calculated quotient is larger than the specified
destination.
If the trap flag (TF) is set, the CPU automatically

generates a type 1 interrupt following every
instruction. This is called single-step execution
and is a powerful debugging tool that is discussed
in more detail shortly.

Interrupt Pointer Table

The interrupt pointer (or interrupt vector) table
(figure 2-30) is the link between an interrupt type
code and the procedure that has been designated
to service interrupts associated with that code.
The interrupt pointer table occupies up to the first
lk bytes of low memory. There may be up to 256
entries in the table, one for each interrupt type

All internal interrupts (INT, INTO, divide error,
and single-step) share these characteristics:
1.

The interrupt type code is either contained in
the instruction or is predefined.

3FFH

r--------"I
~ TY~~J~i:A~I~;)ER

3FCH~

AVAILABLE
INTERRUPT
POINTERS
(224)
OS4H

OSOH
07FH

-

______________

~

TYPE 33 POINTER:
(AVAILABLE)

-

TYPE 32 POINTER:
(AVAILABLE)

-

TYPE 31 POINTER:
(RESERVED)

-

RESERVED
INTERRUPT
POINTERS

r

(271

014H

-

TYPE 5 POINTER:
(RESERVED)

-

-

TYPE 4 POINTER:
OVERFLOW

-

010H

DEDICATED
INTERRUPT
POINTERS
(5)

OOCH

1.BY~mf rN~I~:J~+ION

-

TYPE 2 POINTER:
NON·MASKABLE

-

~

TYPE 1 POINTER:
SINGLE·STEP

-

~

TYPE 0 POINTER:
DIVIDE ERROR

-

OOSH

004H

OOOH

CS BASE ADDRESS
IP OFFSET

1_16 BITS_I

Figure 2-30. Interrupt Pointer Table
2-25

Mnemonics

Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

that can occur in the system. Each entry in the
table is a doubleword pointer containing the
address of the procedure that is to service interrupts of that type. The higher-addressed word of
the pointer contains the base address of the segment containing the procedure. The lower-addressed word contains the procedure's offset
from the beginning of the segment. Since each
entry is four bytes long, the CPU can calculate the
location of the correct entry for a given interrupt
type by simply multiplying (type*4).

are recognized in turn, in the order of their
priorities except for INTR. INTR is not recognized until after the following instruction because
recognition of the earlier interrupts cleared IF. Of
couse interrupts could be reenabled in any of the
interrupt response routines if earlier response to
INTR is desired.
As figure 2-31 shows, all main-line code is executed in single-step mode. Also, because of the
order of interrupt processing, the opportunity
exists in each occurrence of the single-step routine
to select whether pending interrupt routines
(divide error and INTR routines in this example)
are executed at full speed or in single-step mode.

Table 2-3. Interrupt Priorities
INTERRUPT

Divide error, INT n, INTO
NMI
INTR
Single-step

PRIORITY

highest

Interrupt Procedures

lowest

When an interrupt service procedure is entered,
the flags, CS, and IP are pushed onto the stack
and TF and IF are cleared. The procedure may
reenable external interrupts with the STI (set
interrupt-enable flag) instruction, thus allowing
itself to be interrupted by a request on INTR.
(Note, however, that interrupts are not actually
enabled until the instruction following STI has
executed.) An interrupt procedure always may be
interrupted by a request arriving on NMI.
Software- or processor-initiated interrupts
occurring within the procedure also will interrupt
the procedure. Care must be taken in interrupt
procedures that the type of interrupt being serviced by the procedure does not itself inadvertently occur within the procedure. For example,
an attempt to divide by 0 in the divide error (type
0) interrupt procedure may result in the procedure
being reentered endlessly. Enough stack space
must be available to accommodate the maximum
depth of interrupt nesting that can occur in the
system.

Space at the high end of the table that would be
occupied by entries for interrupt types that cannot
occur in a given application may be used for other
purposes. The dedicated and reserved portions of
the interrupt pointer table (locations OH through
7FH), however, should not be used for any other
purpose to insure proper system operation and to
preserve compatibility with future Intel hardware
and software products.
After pushing the flags onto the stack, the 8086 or
8088 activates an interrupt procedure by executing the equivalent of an intersegment indirect
CALL instruction. The target of the "CALL" is
the address contained in the interrupt pointer
table element located at (type*4). The CPU saves
the address of the next instruction by pushing CS
and IP onto the stack. These are then replaced by
the second and first words of the table element,
thus transferring control to the procedure.

Like all procedures, interrupt procedures should
save any registers they use before updating them,
and restore them before terminating. It is good
practice for an interrupt procedure to enable
external interrupts for all but "critical sections"
of code (those sections that cannot be interrupted
without risking erroneous results). If external
interrupts are disabled for too long in a procedure, interrupt requests on INTR can potentially be lost.

If multiple interrupt requests arrive simultaneously, the processor activates the interrupt procedures in priority order. Figure 2-31 shows how
procedures would be activated in an extreme case.
The processor is running in single-step mode with
external interrupts enabled. During execution of a
divide instruction, INTR is activated. Furthermore the instruction generates a divide error
interrupt. Figure 2-31 shows that the interrupts
Mnemonics © Intel, 1978

2-26

8086 AND 8088 CENTRAL PROCESSING UNITS

~

~
DIVIDE
INSTRUCTION

•

INTR

DIVIDE ERROR RECOGNIZED

~
PUSH FLAGS
PUSH CS & IP
CLEAR IF & TF
EXECUTE NEXT
INSTRUCTION

I

SINGLE STEP RECOGNIZED

~

~

PUSH FLAGS
PUSH CS & IP
CLEAR IF &TF

DIVIDE ERROR
PROCEDURE

I

I
SINGLE STEP
PROCEDURE'

POP CS & IP
POP FLAGS

I

I

TF=1,IF=1

POP CS & IP
POP FLAGS

INTR RECOGNIZED

~

TF=O,IF=O

I

PUSH FLAGS
PUSH CS & IP
CLEAR IF & TF
EXECUTE NEXT
INSTRUCTION

I

SINGLE STEP RECOGNIZED

I

I
I
I
I
I
I
I
I
I

~

~

PUSH FLAGS
PUSH CS & IP
CLEAR IF & TF

INTR
PROCEDURE

I

I
SINGLE STEP
PROCEDURE'

POP CS & IP
POP FLAGS

TF= 1,IF= 1
, TF CAN BE SET IN THE
SINGLE STEP PROCEDURE
IF SINGLE STEPPING OF
THE DIVIDE ERROR OR INTR
PROCEDURE IS DESIRED.

I

I
POPCS & IP
POP FLAGS

,.
TF=O,IF=O

I

Figure 2-31. Processing Simultaneous Interrupts
2-27

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Single-stepping is a valuable debugging tool. It
allows the single-step procedure to act as a "window" into the system through which operation
can be observed instruction-by-instruction. A
single-step interrupt procedure, for example, can
print or display register contents, the value of the
instruction pointer (it is on the stack), key
memory variables, etc., as they change after each
instruction. In this way the exact flow of a program can be traced in detail, and the point at
which discrepancies occur can be determined.
Other possible services that could be provided by
a single-step routine include:

All interrupt procedures should be terminated
with an IRET (interrupt return) instruction. The
IRET instruction assumes that the stack is in the
same condition as it was when the procedure was
entered. It pops the top three stack words into IP,
CS and the flags, thus returning to the instruction
that was about to be executed when the interrupt
procedure was activated.
The actual processing done by the procedure is
dependent upon the application. If the procedure
is servicing an external device, it should output a
command to the device instructing it to remove its
interrupt request. It might then read status
information from the device, determine the cause
of the interrupt and then take action accordingly.
Section 2.10 contains three typical interrupt procedure examples.
Software-initiated interrupt procedures may be
used as service routines ("supervisor calls") for
other programs in the system. In this case, the
interrupt procedure is activated when a program,
rather than an external device, needs attention.
(The "attention" might be to search a file for a
record, send a message to another program,
request an allocation of free memory, etc.) Software interrupt procedures can be advantageous in
systems that dynamically relocate programs during execution. Since the interrupt pointer table is
at a fixed storage location, procedures may
"call" each other through the table by issuing
software interrupt instructions. This provides a
stable communication "exchange" that is
independent of procedure addresses. The interrupt procedures may themselves be moved so long
as the interrupt pointer table always is updated to
provide the linkage from the "calling" program
via the interrupt type code.

Writing a message when a specified memory
location or 110 port changes value (or equals
a specified value).

•

Providing diagnostics selectively (only for
certain instruction addresses for instance).

•

Letting a routine execute a number of times
before providing diagnostics.

The 8086 and 8088 do not have instructions for
setting or clearing TF directly. Rather, TF can be
changed by modifying the flag-image on the
stack. The PUSHF and POPF instructions are
available for pushing and popping the flags
directly (TF can be set by ORing the flag-image
with OIOOH and cleared by ANDing it with
FEFFH). After TF is set in this manner, the first
single-step interrupt occurs after the first
instruction following the IRET from the singlestep procedure.

Single-Step (Trap) Interrupt

When TF (the trap flag) is set, the 8086 or 8088 is
said to be in single-step mode. In this mode, the
processor automatically generates a type 1 interrupt after each instruction. Recall that as part of
its interrupt processing, the CPU automatically
pushes the flags onto the stack and then clears TF
and IF. Thus the processor is not in single-step
mode when the single-step interrupt procedure is
entered; it runs normally. When the single-step
procedure terminates, the old flag image is
restored from the stack, placing the CPU back ",
into single-step mode.
Mnemonics @ Intel, 1978

•

2-28

If the processor is single-stepping, it processes an
interrupt (either internal or external) as follows.
Control is passed normally (flags, CS and IP are
pushed) to the procedure designated to handle the
type of interrupt that has occurred. However,
before the first instruction of that procedure is
executed, the single-step interrupt is "recognized" and control is passed normally (flags, CS
and IP are pushed) to the type 1 interrupt procedure. When single-step procedure terminates,
control returns to the previous interrupt procedure.Figure 2-31 illustrates this process in a
case where two interrupts occur when the processor is in single-step mode.

Breakpoint Interrupt

A type 3 interrupt is dedicated to the breakpoint
interrupt. A breakpoint is generally any place in a
program where normal execution is arrested so

8086 AND 8088 CENTRAL PROCESSING UNITS

rupts are disabled by system reset, the system
software should reenable interrupts as soon as the
system is initialized to the point where they can be
processed.

that some sort of special processing may be performed. Breakpoints typically are inserted into
programs during debugging as a way of displaying registers, memory locations, etc., at crucial
points in the program.

Table 2-4. CPU State Following RESET

The INT 3 (breakpoint) instruction is one byte
long. This makes it easy to "plant" a breakpoint
anywhere in a program. Section 2.10 contains an
example that shows how a breakpoint may be set
and how a breakpoint procedure may be used to
place the processor into single-step mode.
The breakpoint instruction also may be used to
"patch" a program (insert new instructions)
without recompiling or reassembling it. This may
be done by saving an instruction byte, and replacing it with an INT 3 (CCH) machine instruction.
The breakpoint procedure would contain the new
machine instructions, plus code to restore the
saved instruction byte and decrement IP on the
stack before returning, so that the displaced
instruction would be executed after the patch
instructions. The breakpoint example in section
2.10 illustrates these principles.

CPU COMPONENT

CONTENT

Flags
Instruction Pointer
CS Register
DS Register
SS Register
ES Register
Queue

Clear
OOOOH

FFFFH
OOOOH
OOOOH
OOOOH

Empty

Instruction Queue Status
When configured in maximum mode, the 8086
and 8088 provide information about instruction
queue operations on lines QSO and QS 1. Table 2-5
interprets the four states that these lines can
represent.
The queue status lines are provided for external
processors that receive instructions and/or
operands via the 8086/8088 ESC (escape) instruction (see sections 2.5 and 2.8). Such a processor
may monitor the bus to see when an ESC instruction is fetched and then track the instruction
through the queue to determine when (and if) the
instruction is executed.

Note that patching a program requires machineinstruction programming and should be undertaken with considerable caution; it is easy to add
new bugs to a program in an attempt to correct
existing ones. Note also that a patch is only a temporary measure to be used in exceptional conditions. The affected code should be updated and
retranslated as soon as possible.

Table 2-5. Queue Status Signals
(Maximum Mode Only)

System Reset

QS o QS1

The 8086/8088 RESET line provides an orderly
way to start or restart an executing system. When
the processor detects the positive-going edge of a
pulse on RESET, it terminates all activities until
the signal goes low, at which time it initializes the
system as shown in table 2-4.
Since the code segment register contains FFFFH
and the instruction pointer contains OH, the processor executes its first instruction following
system reset from absolute memory location
FFFFOH. This location normally contains an
inter segment direct JMP instruction whose target
is the actual beginning of the system program.
The LOC-86 utility supplies this JMP instruction
from information in the program that identifies
its first instruction. As external (maskable) inter-

QUEUE OPERATION IN LAST
CLKCYCLE

0

0

No operation; default value

0

1

First byte of an instruction was
taken from the queue

1

0

Queue was reinitialized

1

1

Subsequent byte of an instruction
was taken from the queue

Processor Halt
When the HL T (halt) instruction (see section 2.7)
is executed, the 8086 or 8088 enters the halt state.
This condition may be interpreted as "stop all

2-29

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

operations until an external interrupt occurs or
the system is reset." No signals are floated during
the halt state, a'nd the content of the address and
data buses is undefined. A bus hold request
arriving on the HOLD line (minimum mode) or
either request/grant line (maximum mode) is
acknowledged normally while the processor is
halted.
The halt state can be used when an event prevents
the system from functioning correctly. An example might be a power-fail interrupt. After
recognizing that loss of power is imminent, the
CPU could use the remaining time to move
registers, flags and vital variables to (for example)
a battery-powered CMOS RAM area and then
halt until the return of power was signaled by an
interrupt or system reset.

Status Lines
When configured in maximum mode, the 8086
and 8088 emit eight status signals that can be used
by external devices. Lines SO, S1 and 51 identify
the type of bus cycle that the CPU is starting to
execute (table 2-6). These lines are typically
decoded by the 8288 Bus Controller. S3 and S4
indicate which segment register was used to construct the physical address being used in this bus
cycle (see table 2-7). Line S5 reflects the state of
the interrupt-enable flag. S6 is always O. S7 is a
spare line whose content is undefined.
Table 2-6. Bus Cycle Status Signals
S2

S1

So

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

TYPES OF BUS CYCLE
Interrupt Acknowledge
Read 1/0
Write 1/0
HALT
Instruction Fetch
Read Memory
Write Memory
Passive; no bus cycle

Table 2-7. Segment Register Status Lines
S4

S3

SEGMENT REGISTER

0
0
1
1

0
1
0
1

ES
SS
CS or none (1/0 or Interrupt Vector)
OS

Mnemonics © Intel, 1978

2.7 Instruction Set
The 8086 and 8088 execute exactly the same
instructions. This instruction set includes
equivalents to the instructions typically found in
previous microprocessors, such as the 8080/8085.
Significant new operations include:
•

multiplication and division of signed and
unsigned binary numbers as well as unpacked
decimal numbers,

•

move, scan and compare operations for
strings up to 64k bytes in length,

•
•

non-destructive bit testing,
byte translation from one code to another,

•
•

software-generated interrupts, and
a group of instructions that can help
coordinate the activities of multiprocessor
systems.

These instructions treat different types of
operands uniformly. Nearly every instruction can
operate on either byte or word data. Register,
memory and immediate operands may be
specified interchangeably in most instructions (except, of course, that immediate values may only
serve as "source" and not "destination"
operands). In particular, memory variables can be
added to, subtracted from, shifted, compared,
and so on, in place, without moving them in and
out of registers. This saves instructions, registers,
and execution time in assembly language programs. In high-level languages, where most
variables are memory based, compilers, such as
PL/M-86, can produce faster and shorter object
programs.
The 8086/8088 instruction set can be viewed as
existing at two levels: the assembly level and the
machine level. To the assembly language programmer, the 8086 and 8088 appear to have a
repertoire of about 100 instructions. One MOV
(move) instruction, for example, transfers a byte
or a word from a register or a memory location or
an immediate value to either a register or a
memory location. The 8086 and 8088 CPUs,
however, recognize 28 different MOV machine
instructions ("move byte register to memory,"
"move word immediate to register," etc.). The
ASM-86 assembler translates the assembly-level
instructions written by a programmer into the

2-30

8086

AND

8088 CENTRAL PROCESSING UNITS

machine-level instructions that are actually executed by the 8086 or 8088. Compilers such as
PLlM-86 translate high-level language statements
directly into machine-level instructions.

Table 2-8. Data Transfer Instructions
GENERAL PURPOSE
MOV
PUSH
POP
XCHG
XLAT

The two levels of the instruction set address two
different requirements: efficiency and simplicity.
The numerous-there are about 300 in all-forms
of machine-level instructions allow these instructions to make very efficient use of storage. For
example, the machine instruction that increments
a memory operand is three or four bytes long
because the address of the operand must be
encoded in the instruction. To increment a
register, however, does not require as much
information, so the instruction can be shorter. In
fact, the 8086 and 8088 have eight different
machine-level instructions that increment a different 16-bit register; these instructions are only
one byte long.

Move byte or word
Push word onto stack
Pop word off stack
Exchange byte or word
Translate byte
INPUT/OUTPUT

IN
OUT

Input byte or word
Output byte or word
ADDRESS OBJECT

LEA
LOS
LES

Load effective address
Load pointer using OS
Load pointer using ES
FLAG TRANSFER

If a programmer had to write one instruction to

increment a register, another to increment a
memory variable, etc., the benefit of compact
instructions would be offset by the difficulty of
programming. The assembly-level instructions
simplify the programmer's view of the instruction
set. The programmer writes one form of the INC
(increment) instruction and the ASM-86
assembler examines the operand to determine
which machine-level instruction to generate.

LAHF
SAHF
PUSHF
POPF

Load AH register from flags
Store AH register in flags
Push flags onto stack
Pop flags off stack

General Purpose Data Transfers
MOV destination, source

This section presents the 8086/8088 instruction
set from two perspectives. First, the assemblylevel instructions are described in functional
terms. The assembly-level instructions are then
presented in a reference table that breaks out all
permissible operand combinations with execution
times and machine instruction length, plus the
effect that the instruction has on the CPU flags.
Machine-level instruction encoding and decoding
are covered in section 4.2.

MOY transfers a byte or a word from the source
operand to the destination operand.
PUSH source

PUSH decrements SP (the stack pointer) by two
and then transfers a word from the source
operand to the top of stack now pointed to by SP.
PUSH often is used to place parameters on the
stack before calling a procedure; more generally,
it is the basic means of storing temporary data on
the stack.

Data Transfer Instructions
POP destination

The 14 data transfer instructions (table 2-8) move
single bytes and words between memory and
registers as well as between register AL or AX and
I/O ports. The stack manipulation instructions
are included in this group as are instructions for
transferring flag contents and for loading segment registers.

POP transfers the word at the current top of stack
(pointed to by SP) to the destination operand,
and then increments SP by two to point to the
new top of stack. POP can be used to move temporary variables from the stack to registers or
memory.

2-31

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

XCHG destination, source

LEA destination,source

XCHG (exchange) switches the contents of the
source and destination (byte or word) operands.
When used in conjunction with the LOCK prefix,
XCHG can test and set a semaphore that controls
access to a resource shared by multiple processors
(see section 2.5).

LEA (load effective address) transfers the offset
of the source operand (rather than its value) to the
destination operand. The source operand must be
a memory operand, and the destination operand
must be a 16-bit general register. LEA does not
affect any flags. The XLA T and string instructions assume that certain registers point to
operands; LEA can be used to load these registers
(e.g., 10'lding BX with the address of the translate
table used by the XLA T instruction).

XLAT translate-table

XLAT (translate) replaces a byte in the AL
register with a byte from a 256-byte, user-coded
translation table. Register BX is assumed to point
to the beginning of the table. The byte in AL is
used as an index into the table and is replaced by
the byte at the offset in the table corresponding to
AL's binary value. The first byte in the table has
an offset of O. For example, if AL contains 5H,
and the sixth element of the translation table contains 33H, then AL will contain 33H following
the instruction. XLAT is useful for translating
characters from one code to another, the classic
example being ASCII to EBCDIC or the reverse.

LOS destination,source
LDS (load pointer using DS) transfers a 32-bit
pointer variable from the source operand, which
must be a memory operand, to the destination
operand and register DS. The offset word of the
pointer is transferred to the destination operand,
which may be any 16-bit general register. The segment word of the pointer is transferred to register
DS. Specifying SI as the destination operand is a
convenient way to prepare to process a source
string that is not in the current data segment
(string instructions assume that the source string
is located in the current data segment and that SI
contains the offset of the string).

IN accumulator,port
IN transfers a byte or a word from an input port
to the AL register or the AX register, respectively.
The port number may be specified either with an
immediate byte constant, allowing access to ports
numbered 0 through 255, or with a number
previously placed in the DX register, allowing
variable access (by changing the value in DX) to
ports numbered from 0 through 65,535.

LES destination, source
LES (load pointer using ES) transfers a 32-bit
pointer variable from the source operand, which
must be a memory operand, to the destination
operand and register ES. The offset word of the
pointer is transferred to the destination operand,
which may be any 16-bit general register. The segment word of the pointer is transferred to register
ES. Specifying DI as the destination operand is a
convenient way to prepare to process a destination string that is not in the current extra segment.
(The destination string must be located in the
extra segment, and DI must contain the offset of
the string.)

OUT port, accumulator

OUT transfers a byte or a word from the AL
register or the AX register, respectively, to an output port. The port number may be specified either
with an immediate byte constant; allowing access
to ports numbered 0 through 255, or with a
number previously placed in register DX, allowing variable access (by changing the value in DX)
to ports numbered from 0 through 65,535.

Flag Transfers
Address Object Transfers
LAHF

These instructions manipulate the addresses of
variables rather than the contents or values of
variables. They are most useful for list processing, based variables, and string operations.
Mnemonics © Intel, 1978

LAHF (load register AH from flags) copies SF,
ZF, AF, PF and CF (the 8080/8085 flags) into
bits 7, 6, 4, 2 and 0, respectively, of register AH

2-32

8086 AND 8088 CENTRAL PROCESSING UNITS

setting of TF (there is no instruction for updating
this flag directly). The change is accomplished by
pushing the flags, altering bit 8 of the memoryimage and then popping the flags.

(see figure 2-32). The content of bits 5, 3 and 1 is
undefined; the flags themselves are not affected.
LAHF is provided primarily for converting
8080/8085 assembly language programs to run on
an 8086 or 8088.

SAHF

Arithmetic Instructions

SAHF (store register AH into flags) transfers bits
7,6,4,2 and 0 from register AH into SF, ZF, AF,
PF and CF, respectively, replacing whatever
values these flags previously had. OF, DF, IF and
TF are not affected. This instruction is provided
for 8080/8085 compatibility.

Arithmetic Data Formats
8086 and 8088 arithmetic operations (table 2-9)
may be performed on four types of numbers:
unsigned binary, signed binary (integers),
unsigned packed decimal and unsigned unpacked
decimal (see table 2-10). Binary numbers may be 8
or 16 bits long. Decimal numbers are stored in
bytes, two digits per byte for packed decimal and
one digit per byte for unpacked decimal. The processor always assumes that the operands specified
in arithmetic instructions contain data that represent valid numbers for the type of instruction
being performed. Invalid data may produce
unpredictable results.

PUSHF
PUSHF decrements SP (the stack pointer) by two
and then transfers all flags to the word at the top
of stack pointed to by SP (see figure 2-32). The
flags themselves are not affected.

POPF
Table 2-9. Arithmetic Instructions

POPF transfers specific bits from the word at the
current top of stack (pointed to by register SP)
into the 8086/8088 flags, replacing whatever
values the flags previously contained (see figure
2-32). SP is then incremented by two to point to
the new top of stack. PUSHF and POPF allow a
procedure to save and restore a calling program's
flags. They also allow a program to change the

ADD
ADC
INC
AAA
DAA
SUB
SBB

LAHF,
SAHF

IS , Z , U
17

6

5

I

A, U

4

I

P,U

3 2

1

,c I

DEC
NEG
CMP
AAS
DAS

01

1_8080/8085 FLAGS_I

~g~~ F, I u , U I

I

I

I

I

U , U I 0 I 0, I , T , S
15 14 13 12 11 10 9 8 7

I

Z

6

I

U , A , U , P

5

4

3

2

I

U

,c

1

0

I

MUL
IMUL
AAM

U = UNDEFINED; VALUE IS INDETERMINATE

o =OVERFLOW FLAG
D
I
T
S
Z
A
P
C

= DIRECTION FLAG

= INTERRUPT ENABLE FLAG
= TRAP FLAG
= SIGN FLAG
= ZERO FLAG
= AUXILIARY CARRY FLAG
PARITY FLAG
CARRY FLAG

DIV
IDIV
AAD
CBW
CWO

=

=

ADDITION
Add byte or word
Add byte or word with carry
Increment byte or word by 1
ASCII adjust for addition
Decimal adjust for addition
SUBTRACTION
Subtract byte or word
Subtract byte or word with
borrow
Decrement byte or word by 1
Negate byte or word
Compare byte or word
ASCII adjust for subtraction
Decimal adjust for subtraction
MULTIPLICATION
Multiply byte or word unsigned
Integer multiply byte or word
ASCII adjust for multiply
DIVISION
Divide byte or word unsigned
Intege~<:Iivide byte or word
ASCII adjust for division
Convert byte to word
Convert word to doubleword

Figure 2-32. Flag Storage Formats
2-33

MnemoniCS © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-10. Arithmetic Interpretation of 8-Bit Numbers
HEX

BIT PATTERN

UNSIGNED
BINARY

SIGNED
BINARY

UNPACKED
DECIMAL

PACKED
DECIMAL

+7

7

7

07

00000111

7

89

1 0001001

137

-119

invalid

89

C5

1 1000101

197

-59

invalid

invalid

Unsigned binary numbers may be either 8 or 16
bits long; all bits are considered in determining a
number's magnitude. The value range of an 8-bit
unsigned binary number is 0-255; 16 bits can
represent values from 0 through 65,535. Addition, subtraction, multiplication and division
operations are available for unsigned binary
numbers.

Unpacked decimal numbers are stored as unsigned byte quantities. The magnitude of the
number is determined from the low-order halfbyte; hexadecimal values 0-9 are valid and are
interpreted as decimal numbers. The high-order
half-byte must be zero for multiplication and division; it may contain any value for addition and
subtraction. Arithmetic on unpacked decimal
numbers is performed in two steps. The unsigned
binary addition, subtraction and multiplication
operations are used to produce an intermediate
result in register AL. An adjustment instruction
then changes the value in AL to a final correct
unpacked decimal number. Division is performed
similarly, except that the adjustment is carried out
on the numerator operand in register AL first,
then a following unsigned binary division instruction produces a correct result.

Signed binary numbers (integers) may be either 8
or 16 bits long. The high-order (leftmost) bit is
interpreted as the number's sign: 0 = positive and
1 = negative. Negative numbers are represented
in standard two's complement notation. Since
the high-order bit is used for a sign, the range of
an 8-bit integer is -128 through +127; 16-bit
integers may range from -32,768 through
+32,767. The value zero has a positive sign.
Multiplication and division operations are provided for signed binary numbers. Addition and
subtraction are performed with the unsigned
binary instructions. Conditional jump instructions, as well as an "interrupt on overflow"
instruction, can be used following an unsigned
operation on an integer to detect overflow into
the sign bit.

Unpacked decimal numbers are similar to the
ASCII character representations of the digits 0-9.
Note, however, that the high-order half-byte of
an ASCII numeral is always 3H. Unpacked
decimal arithmetic may be performed on ASCII
numeric characters under the following
conditions:
•
the high-order half-byte of an ASCII
numeral must be set to OH prior to
multiplication or division.

Packed decimal numbers are stored as unsigned
byte quantities. The byte is treated as having one
decimal digit in each half-byte (nibble); the digit
in the high-order half-byte is the most significant.
Hexadecimal values 0-9 are valid in each halfbyte, and the range of a packed decimal number is
0-99. Addition and subtraction are performed in
two steps. First an unsigned binary instruction is
used to produce an intermediate result in register
AL. Then an adjustment operation is performed
which changes the intermediate value in AL to a
final correct packed decimal result. Multiplication and division adjustments are not available
for packed decimal numbers.
Mnemonics © Intel. 1978

•

unpacked decimal arithmetic leaves the
high-order half-byte set to OH; it must be set
to 3H to produce a valid ASCII numeral.

Arithmetic Instructions and Flags

The 8086/8088 arithmetic instructions post certain characteristics of the result of the operation
to six flags. Most of these flags can be tested by
following the arithmetic instruction with a conditional jump instruction; the INTO (interrupt on
overflow) instruction also may be used. The
2-34

8086 AND 8088 CENTRAL PROCESSING UNITS

various instructions affect the flags differently, as
explained in the instruction descriptions.
However, they follow these general rules:
•

•

CF (carry flag): If an addition results in a
carry out of the high-order bit of the result,
then CF is set; otherwise CF is cleared. If a
subtraction results in a borrow into the highorder bit of the result, then CF is set; otherwise CF is cleared. Note that a signed carry is
indicated by CF
OF. CF can be used to
detect an unsigned overflow. Two instructions, ADC (add with carry) and SBB (subtract with borrow), incorporate the carry flag
in their operations and can be used to perform multibyte (e.g., 32-bit, 64-bit) addition
and subtraction.

OF (overflow flag): If the result of an
operation is too large a positive number, or
too small a negative number to fit in the
destination operand (excluding the sign bit),
then OF is set; otherwise OF is cleared. OF
thus indicates signed arithmetic overflow; it
can be tested with a conditional jump or the
INTO (interrupt on overflow) instruction.
OF may be ignored when performing
unsigned arithmetic.

*"

•

•

•

•

Addition

ADD destination,source
The sum of the two operands, which may be bytes
or words, replaces the destination operand. Both
operands may be signed or unsigned binary
numbers (see AAA and DAA). ADD updates AF,
CF, OF, PF, SF and ZF.

AF (auxiliary carry flag): If an addition
results in a carry out of the low-order halfbyte of the result, then AF is set; otherwise
AF is cleared. If a subtraction results in a
borrow into the low-order half-byte of the
result, then AF is set; otherwise AF is
cleared. The auxiliary carry flag is provided
for the decimal adjust instructions and
ordinarily is not used for any other purpose.

ADC destination, source
ADC (Add with Carry) sums the operands, which
may be bytes or words, adds one if CF is set and
replaces the destination operand with the result.
Both operands may be signed or unsigned binary
numbers (see AAA and DAA). ADC updates AF,
CF, OF, PF, SF and ZF. Since ADC incorporates
a carry from a previous operation, it can be used
to write routines to add numbers longer than 16
bits.

SF (sign flag): Arithmetic and logical
instructions set the sign flag equal to the
high-order bit (bit 7 or 15) of the result. For
signed binary numbers, the sign flag will be a
for positive results and 1 for negative results
(so long as overflow does not occur). A conditional jump instruction can be used following addition or subtraction to alter the flow
of the program depending on the sign of the
result. Programs performing unsigned operations typically ignore SF since the high-order
bit of the result is interpreted as a digit rather
than a sign.

INC destination
INC (Increment) adds one to the destination
operand. The operand may be a byte or a word
and is treated as an unsigned binary number (see
AAA and DAA). INC updates AF, OF, PF, SF
and ZF; it does not affect CF.

ZF (zero flag): If the result of an arithmetic
or logical operation is zero, then ZF is set;
otherwise ZF is cleared. A conditional jump
instruction can be used to alter the flow of
the program if the result is or is not zero.
PF (parity flag): If the low-order eight bits of
an arithmetic or logical result contain an
even number of I-bits, then the parity flag is
set; otherwise it is cleared. PF is provided for
8080/8085 compatibility; it also can be used
to check ASCII characters for correct parity.

AAA
AAA (ASCII Adjust for Addition) changes the
contents of register AL to a valid unpacked
decimal number; the high-order half-byte is
zeroed. AAA updates AF and CF; the content of
OF, PF, SF and ZF is undefined following execution of AAA.

2-35

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

DAA

-32,768 causes no change to the operand and sets
OF. NEG updates AF, CF, OF, PF, SF and ZF.
CF is always set except when the operand is zero,
in which case it is cleared.

DAA (Decimal Adjust for Addition) corrects the
result of previously adding two valid packed
decimal operands (the destination operand must
have been register AL). DAA changes the content
of AL to a pair of valid packed decimal digits. It
updates AF, CF, PF, SF and ZF; the content of
OF is undefined following execution of DAA.

CMP destination, source

CMP (Compare) subtracts the source from the
destination, which may be bytes or words, but
does not return the result. The operands are
unchanged, but the flags are updated and can be
tested by a subsequent conditional jump instruction. CMP updates AF, CF, OF, PF, SF and ZF.
The comparison reflected in the flags is that of the
destination to the source. If a CMP instruction is
followed by a 1G (jump if greater) instruction, for
example, the jump is taken if the destination
operand is greater than the source operand.

Subtraction

SUB destination,source
The source operand is ~ubtracted from the
destination operand, and the result replaces the
destination operand. The operands may be bytes
or words. Both operands may be signed or
unsigned binary numbers (see AAS and DAS).
SUB updates AF, CF, OF, PF, SF and ZF.

AAS
AAS (ASCII Adjust for Subtraction) corrects the
result of a previous subtraction of two valid
unpacked decimal operands (the destination
operand must have been specified as register AL).
AAS changes the content of AL to a valid
unpacked decimal number; the high-order halfbyte is zeroed. AAS updates AF and CF; the content of OF, PF, SF and ZF is undefined following
execution of AAS.

SBB destination, source
SBB (Subtract with Borrow) subtracts the source
from the destination, subtracts one if CF is set,
and returns the result to the destination operand.
Both operands may be bytes or words. Both
operands may be signed or unsigned binary
numbers (see AAS and DAS). SBB updates AF,
CF, OF, PF, SF and ZF. Since it incorporates a
borrow from a previous operation, SBB may be
used to write routines that subtract numbers
longer than 16 bits.

DAS
DAS (Decimal Adjust for Subtraction) corrects
the result of a previous subtraction of two valid
packed decimal operands (the destination
operand must have been specified as register AL).
DAS changes the content of AL to a pair of valid
packed decimal digits. DAS updates AF, CF, PF,
SF and ZF; the content of OF is undefined
following execution of DAS.

DEC destination

DEC (Decrement) subtracts one from the destination, which may be a byte or a word. DEC
updates AF, OF, PF, SF, and ZF; it does not
affect CF.

NEG destination

Multiplication

NEG (Negate) subtracts the destination operand,
which may be a byte or a word, from 0 and
returns the result to the destination. This forms
the two's complement of the number, effectively
reversing the sign of an integer. If the operand is
zero, its sign is not changed. Attempting to negate
a byte containing -128 or a word containing
Mnemonics © Intel, 1978

MULsource

MUL (Multiply) performs an unsigned multiplication of the source operand and the
accumulator. If the source is a byte, then it is
multiplied by register AL, and the double-length
2-36

8086 AND 8088 CENTRAL PROCESSING UNITS

divided into the double-length dividend assumed
to be in registers AL and AH. The single-length
quotient is returned in AL, and the single-length
remainder is returned in AH. If the source
operand is a word, it is divided into the doublelength dividend in registers AX and DX. The
single-length quotient is returned in AX, and the
single-length remainder is returned in DX. If the
quotient exceeds the capacity of its destination
register (FFH for byte source, FFFFFH for word
source), as when division by zero is attempted, a
type 0 interrupt is generated, and the quotient and
remainder are undefined. Nonintegral quotients
are truncated to integers. The content of AF, CF,
OF, PF, SF and ZF is undefined following execution of DIV.

result is returned in AH and AL. If the source
operand is a word, then it is multiplied by register
AX, and the double-length result is returned in
registers DX and AX. The operands are treated as
unsigned binary numbers (see AAM). If the upper
half of the result (AH for byte source, DX for
word source) is nonzero, CF and OF are set;
otherwise they are cleared. When CF and OF are
set, they indicate that AH or DX contains significant digits of the result. The content of AF, PF,
SF and ZF is undefined following execution of
MUL.

IMULsource
IMUL (Integer Multiply) performs a signed
mUltiplication of the source operand and the
accumulator. If the source is a byte, then it is
mUltiplied by register AL, and the double-length
result is returned in AH and AL. If the source is a
word, then it is multiplied by register AX, and the
double-length result is returned in registers DX
and AX. If the upper half of the result (AH for
byte source, DX for word source) is not the sign
extension of the lower half of the result, CF and
OF are set; otherwise they are cleared. When CF
and OF are set, they indicate that AH or DX contains significant digits of the result. The content
of AF, PF, SF and ZF is undefined following
execution of IMUL.

IDIV source

IDIV (Integer Divide) performs a signed division
of the accumulator (and its extension) by the
source operand. If the source operand is a byte, it
is divided into the double-length dividend
assumed to be in registers AL and AH; the singlelength quotient is returned in AL, and the singlelength remainder is returned in AH. For byte integer division, the maximum positive quotient is
+127 (7FH) and the minimum negative quotient is
-127 (SIH). If the source operand is a word, it is
divided into the double-length dividend in
registers AX and DX; the single-length quotient is
returned in AX, and the single-length remainder
is returned in DX. For word integer division, the
maximum positive quotient is +32,767 (7FFFH)
and the minimum negative quotient is -32,767
(SOOIH). If the quotient is positive and exceeds
the maximum, or is negative and is less than the
minimum, the quotient and remainder are
undefined, and a type 0 interrupt is generated. In
particular, this occurs if division by 0 is
attempted. Nonintegral quotients are truncated
(toward 0) to integers, and the remainder has the
same sign as the dividend. The content of AF,
CF, OF, PF, SF and ZF is undefined following
IDIV.

AAM
AAM (ASCII Adjust for Multiply) corrects the
result of a previous multiplication of two valid
unpacked decimal operands. A valid 2-digit
unpacked decimal number is derived from the
content of AH and AL and is returned to AH and
AL. The high-order half-bytes of the multiplied
operands must have been OH for AAM to produce a correct result. AAM updates PF, SF and
ZF; the content of AF, CF and OF is undefined
following execution of AAM.

Division

AAD

DIV source

AAD (ASCII Adjust for Division) modifies the
numerator in AL before dividing two valid
unpacked decimal operands so that the quotient
produced by the division will be a valid unpacked
decimal number. AH must be zero for the subse-

DIV (divide) performs an unsigned division of the
accumulator (and its extension) by the source
operand. If the source operand is a byte, it is
2-37

Mnemonics

Intel,1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Logical

quent DIV to produce the correct result. The quotient is returned in AL, and the remainder is
returned in AH; both high-order half-bytes are
zeroed. AAD updates PF, SF and ZF; the content
of AF, CF and OF is undefined following execution of AAD.

The logical instructions include the boolean
operators "not," "and," "inclusive or," and
"exclusive or," plus a TEST instruction that sets
the flags, but does not alter either of its operands.

CBW

AND, OR, XOR and TEST affect the flags as
follows: The overflow (OF) and carry (CF) flags
are always cleared by logical instructions, and the
content of the auxiliary carry (A F) flag is always
undefined following execution of a logical
instruction. The sign (SF), zero (ZF) and parity
(PF) flags are always posted to reflect the result of
the operation and can be tested by conditional
jump instructions. The interpretation of these
flags is the same as for arithmetic instructions. SF
is set if the result is negative (high-order bit is I),
and is cleared if the result is positive (high-order
bit is 0). ZF is set if the result is zero, cleared
otherwise. PF is set if the result contains an even
number of I-bits (has even parity) and is cleared if
the number of I-bits is odd (the result has odd
parity). Note that NOT has no effect on the flags.

CBW (Convert Byte to Word) extends the sign of
the byte in register AL throughout register AH.
CBW does not affect any flags. CBW can be used
to produce a double-length (word) dividend from
a byte prior to performing byte division.

cwo
CWD (Convert Word to Doubleword) extends the
sign of the word in register AX throughout
register DX. CWD does not affect any flags.
CWD can be used to produce a double-length
(doubleword) dividend from a word prior to performing word division.

Bit Manipulation Instructions

NOT destination

The 8086 and 8088 provide three groups of
instructions (table 2-11) for manipulating bits
within both bytes and words: logical, shifts and
rotates.

NOT inverts the bits (forms the one's complement) of the byte or word operand.
AND destination,source

Table 2-11 . Bit Manipulation Instructions

NOT
AND
OR
XOR
TEST
SHLISAL
SHR
SAR

ROL
ROR
RCL
RCR

AND performs the logical "and" of the two
operands (byte or word) and returns the result to
the destination operand. A bit in the result is set if
both corresponding bits of the original operands
are set; otherwise the bit is cleared.

LOGICALS
"Not" byte or word
"And" byte or word
"Inclusive or" byte or word
"Exclusive or" byte or word
"Test" byte or word
SHIFTS
Shift logical/arithmetic left
byte orword
Shift logical right byte or word
Shift arithmetic right byte or
word
ROTATES
Rotate left byte or word
Rotate right byte or word
Rotate through carry left byte
or word
Rotate through carry right byte
orword

Mnemonics © Intel, 1978

OR destination,source
OR performs the logical "inclusive or" of the two
operands (byte or word) and returns the result to
the destination operand. A bit in the result is set if
either or both corresponding bits in the original
operands are set; otherwise the result bit is
cleared.

XOR destination, source
XOR (Exclusive Or) performs the logical "exclusive or" of the two operands and returns the
result to the destination operand. A bit in the

2-38

8086 AND 8088 CENTRAL PROCESSING UNITS

the number of bits specified in the count operand.
Zeros are shifted in on the left. If the sign bit
retains its original value, then OF is cleared.

result is set if the corresponding bits of the
original operands contain opposite values (one is
set, the other is cleared); otherwise the result bit is
cleared.

SAR destination, count

TEST destination, source

SAR (Shift Arithmetic Right) shifts the bits in the
destination operand (byte or word) to the right by
the number of bits specified in the count operand.
Bits equal to the original high-order (sign) bit are
shifted in on the left, preserving the sign of the
original value. Note that SAR does not produce
the same result as the dividend of an
"equivalent" IDIV instruction if the destination
operand is negative and I-bits are shifted out. For
example, shifting -5 right by one bit yields -3,
while integer division of -5 by 2 yields -2. The
difference in the instructions is that IDIV truncates all numbers toward zero, while SAR truncates positive numbers toward zero and negative
numbers toward negative infinity.

TEST performs the logical "and" of the two
operands (byte or word), updates the flags, but
does not return the result, i.e., neither operand is
changed. If a TEST instruction is followed by a
JNZ (jump if not zero) instruction, the jump will
be taken if there are any corresponding I-bits in
both operands.
Shifts

T'he bits in bytes and words may be shifted
arithmetically or logically. Up to 255 shifts may
be performed, according to the value of the count
operand coded in the instruction. The count may
be specified as the constant I, or as register CL,
allowing the shift count to be a variable supplied
at execution time. Arithmetic shifts may be used
to multiply and divide binary numbers by powers
of two (see note in description of SAR). Logical
shifts can be used to isolate bits in bytes or words.

Rotates

Bits in bytes and words also may be rotated. Bits
rotated out of an operand are not lost as in a
shift, but are "circled" back into the other "end"
of the operand. As in the shift instructions, the
number of bits to be rotated is taken from the
count operand, which may specify either a constant of I, or the CL register. The carry flag may
act as an extension of the operand in two of the
rotate instructions, allowing a bit to be isolated in
CF and then tested by a JC (jump if carry) or JNC
(jump if not carry) instruction.

Shift instructions affect the flags as follows. AF is
always undefined following a shift operation. PF,
SF and ZF are updated normally, as in the logical
instructions. CF always contains the value of the
last bit shifted out of the destination operand.
The content of OF is always undefined following
a multibit shift. In a single-bit shift, OF is set if
the value of the high-order (sign) bit was changed
by the operation; if the sign bit retains its original
value, OF is cleared.

SHL/SAL destination, count

Rotates affect only the carry and overflow flags.
CF always contains the value of the last bit
rotated out. On multibit rotates, the value of OF
is always undefined. In single-bit rotates, OF is
set if the operation changes the high-order (sign)
bit of the destination operand. If the sign bit
retains its original value, OF is cleared.

SHL and SAL (Shift Logical Left and Shift
Arithmetic Left) perform the same operation and
are physically the same instruction. The destination byte or word is shifted left by the number of
bits specified in the count operand. Zeros are
shifted in on the right. If the sign bit retains its
original value, then OF is cleared.

ROL destination, count
SHR destination, source
ROL (Rotate Left) rotates the destination byte or
word left by the number of bits specified in the
count operand.

SHR (Shift Logical Right) shifts the bits in the
destination operand (byte or word) to the right by
2-39

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

ROR destination, count

operands to determine if the elements of the
strings are bytes or words. The assembler does
not, however, use the operand names to address
the strings. Rather, the content of register Sf
(source index) is used as an offset to address the
current element of the source string, and the content of register DI (destination index) is taken as
the offset of the current destination string element. These registers must be initialized to point
to the source/destination strings before executing
the string instruction; the LDS, LES and LEA
instructions are useful in this regard.

ROR (Rotate Right) operates similar to ROL
except that the bits in the destination byte or word
are rotated right instead of left.
RCL destination, count

RCL (Rotate through Carry Left) rotates the bits
in the byte or word destination operand to the left
by the number of bits specified in the count
operand. The carry flag (CF) is treated as "part
of" the destination operand; that is, its value is
rotated into the low-order bit of the destination,
and itself is replaced by the high-order bit of the
destination.

Table 2-12. String Instructions

RCR destination, count

RCR (Rotate through Carry Right) operates
exactly like RCL except that the bits are rotated
right instead of left.

String Instructions
Five basic string operations, called prImitIves,
allow strings of bytes or words to be operated on,
one element (byte or word) at a time. Strings of
up to 64k bytes may be manipulated with these
instructions. Instructions are available to move,
compare and scan for a value, as well as for moving string elements to and from the accumulator
(see table 2-12). These basic operations may be
preceded by a special one-byte prefix that causes
the instruction to be repeated by the hardware,
allowing long strings to be processed much faster
than would be possible with a software loop. The
repetitions can be terminated by a variety of conditions, and a repeated operation may be interrupted and resumed.

Repeat

REPE/REPZ

Repeat while equal/zero

REPNE/REPNZ

Repeat while not
equal/not zero

MOVS

Move byte or word string

MOVSB/MOVSW

Move byte or word string

CMPS

Compare byte or word
string

SCAS

Scan byte or word string

LODS

Load byte or word string

STOS

Store byte or word string

Table 2-13. String Instruction Register and
Flag Use
.

The string instructions operate quite similarly in
many respects; the common characteristics are
covered here and in table 2-13 and figure 2-33
rather than in the descriptions of the individual
instructions. A string instruction may have a
source operand, a destination operand, or both.
The hardware assumes that a source string resides
in the current data segment; a segment prefix byte
may be used to override this assumption. A
destination string must be in the current extra segment. The assembler checks the attributes of the
Mnemonics © Intel, 1978

REP

2-40

SI

Index (offset) for source string

01

Index (offset) for destination
string

CX

Repetition counter

ALiAX

Scan value
Destination for LODS
Source for STOS

OF

0= auto-increment SI, 01
1 = auto-decrement SI, 01

ZF

Scan/compare terminator

8086 AND 8088 CENTRAL PROCESSING UNITS

SI/DI,CX
{ AND DFWOULD
TYPICALLY BE
INITIALIZED HERE

STRING

DF

DELTA

BYTE
BYTE
WORD
WORD

0
1
0
1

1
-1
2
-2

PREFIX

Z

REPE
REPZ
REPNE
REPNZ

1
1
0
0

PRESENT

,-----1
I

INST~ij~r,.ION I

L_~

___ J

Figure 2-33. String Operation Flow
Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

if a second or third prefix (i.e., segrnent override
or LOCK) has been specified in addition to any of
the repeat prefixes. The processor "remembers"
only one prefix in effect at the time of the interrupt, the prefix that immediately precedes the
string instruction. After returning from the interrupt, processing resumes at this point, but any
additional prefixes specified are not in effect. If
more than one prefix must be used with a string
instruction, interrupts may be disabled for the
duration of the repeated execution. However, this
will not prevent a non-maskable interrupt from
being recognized. Also, the time that the system is
unable to respond to interrupts may be unacceptable if long strings are being processed.

The string instructions automatically update SI
and/or DI in anticipation of processing the next
string element. The setting of DF (the direction
flag) determines whether the index registers are
auto-incremented (DF = 0) or auto-decremented
(DF = 1). If byte strings are being processed, SI
and/ or DI is adjusted byl; the adjustment is 2 for
word strings.
If a Repeat prefix has been coded, then register
CX (count register) is decremented by 1 after each
repetition of the string instruction; therefore, CX
must be initialized to the number of repetitions
desired before the string instruction is executed. If
CX is 0, the string instruction is not executed, and
control goes to the following instruction.

Section 2.10 contains examples that illustrate the
use of all the string instructions.

MOVS destination-string, source-string

MOYS (Move String) transfers a byte or a word
from the source string (addressed by SI) to the
destination string (addressed by DI) and updates
SI and DI to point to the next string element.
When used in conjunction with REP, MOYS performs a memory-to-memory block transfer.

REP/REPE/REPZ/REPNE/REPNZ
Repeat, Repeat While Equal, Repeat While Zero,
Repeat While Not Equal and Repeat While Not
Zero are five mnemonics for two forms of the
prefix byte that controls repetition of a subsequent string instruction. The different mnemonics
are provided to improve program clarity. The
repeat prefixes do not affect the flags.

MOVSB/MOVSW

These are alternate mnemonics for the move
string instruction. These mnemonics are coded
without operands; they explicitly tell the
assembler that a byte string (MOYSB) or a word
string. (MOYSW) is to be moved (when MOYS is
coded, the assembler determines the string type
from the attributes of the operands). These
mnemonics are useful when the assembler cannot
determine the attributes of a string, e.g., a section
of code is being moved.

REP is used in conjunction with the MOYS
(Move String) and STOS (Store String) instructions and is interpreted as "repeat while not endof-string" (CX not 0). REPE and REPZ operate
identically and are physically the same prefix byte
as REP. These instructions are used with the
CMPS (Compare String) and SCAS (Scan String)
instructions and require ZF (posted by these
instructions) to be set before initiating the next
repetition. REPNE and REPNZ are two
mnemonics for the same prefix byte. These
instructions function the same as REPE and
REPZ except that the zero flag must be cleared or
the repetition is terminated. Note that ZF does
not need to be initialized before executing the
repeated string instruction.

CMPS destination-string, source-string
CMPS(Compare String) subtracts the destination
byte or word (addressed by DI) from the source
byte or word (addressed by SI). CMPS affects the
flags but does not alter either operand, updates SI
and DI to point to the next string element and
updates AF, CF, OF, PF, SF and ZF to reflect the
relationship of the destination element to the
source element. For example, if a JG (Jump if
Greater) instruction follows CMPS, the jump is
taken if the destination element is greater than the
source element. If CMPS is prefixed with REPE

Repeated string sequences are interruptable; the
processor will recognize the interrupt before processing the next string element. System interrupt
processing is not affected in any way. Upon
return from the interrupt, the repeated operation
is resumed from the point of interruption. Note,
however, that execution does not resume properly
Mnemonics © Intel, 1978

2-42

8086 AND 8088 CENTRAL PROCESSING UNITS

or REPZ, the operation is interpreted as "compare while not end-of-string (CX not zero) and
strings are equal (ZF = 1)." If CMPS is preceded
by REPNE or REPNZ, the operation is interpreted as "compare while not end-of-string (CX
not zero) and strings are not equal (ZF = 0)."
Thus, CMPS can be used to find matching or differing string elements.

Program Transfer Instructions
The sequence of execution of instructions in an
8086/8088 program is determined by the content
of the code segment register (CS) and the instruction pointer (IP). The CS register contains the
base address of the current code segment, the 64k
portion of memory from which instructions are
presently being fetched. The IP is used as an offset from the beginning of the code segment; the
combination of CS and IP points to the memory
location from which the next instruction is to be
fetched. (Recall that under most operating conditions, the next instruction to be executed has
already been fetched from memory and is waiting
in the CPU instruction queue.) The program
transfer instructions operate on the instruction
pointer and on the CS register; changing the content of these causes normal sequential execution
to be altered. When a program transfer occurs,
the queue no longer contains the correct instruction, and the BIU obtains the next instruction
from memory using the new IP and CS values,
passes the instruction directly to the EU, and then
begins refilling the queue from the new location.

SCAS destination-string

SCAS (Scan String) subtracts the destination
string element (byte or word) addressed by DI
from the content of AL (byte string) or AX (word
string) and updates the flags, but does not alter
the destination string or the accumulator. SCAS
also updates DI to point to the next string element
and AF, CF, OF, PF, SF and ZF to reflect the
relationship of the scan value in ALI AX to the
string element. If SCAS is prefixed with REPE or
REPZ, the operation is interpreted as "scan while
not end-of-string (CX not 0) and string-element =
scan-value (ZF = 1)." This form may be used to
scan for departure from a given value. If SCAS is
prefixed with REPNE or REPNZ, the operation
is interpreted as "scan while not end-of-string
(CX not 0) and string-element is not equal to
scan-value (ZF = 0)." This form may be used to
locate a value in a string.

Four groups of program transfers are available in
the 8086/8088 (see table 2-14): unconditional
transfers, conditional transfers, iteration control
instructions and interrupt-related instructions.
Only the interrupt-related instructions affect any
CPU flags. As will be seen, however, the execution of many of the program transfer instructions
is affected by the states of the flags.

LODS source-string

LODS (Load String) transfers the byte or word
string element addressed by SI to register AL or
AX, and updates SI to point to the next element
in the string. This instruction is not ordinarily
repeated since the accumulator would be overwritten by each repetition, and only the last element would be retained. However, LODS is very
useful in software loops as part of a more complex string function built up from string
primitives and other instructions.

Unconditional Transfers

The unconditional transfer instructions may
transfer control to a target instruction within the
current code segment (intrasegment transfer) or
to a different code segment (intersegment
transfer). (The ASM-86 assembler terms an
intrasegment target NEAR and an intersegment
target FAR.) The transfer is made unconditionally any time the instruction is executed.

STOS destination-string
CALL procedure-name

STOS (Store String) transfers a byte or word from
register AL or AX to the string element addressed
by DI and updates DI to point to the next location
in the string. As a repeated operation, STOS provides a convenient way to initialize a string to a
constant value (e.g., to blank out a print line).

CALL activates an out-of-line procedure, saving
information on the stack to permit a RET (return)
instruction in the procedure to transfer control
back to the instruction following the CALL. The
2-43

Mnemonics

Intel. 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

assembler generates a different type of CALL
instruction depending on whether the programmer has defined the procedure name as NEAR or
FAR. For control to return properly, the type of
CALL instruction must match the type of RET
instruction that exits from the procedure. (The
potential for a mismatch exists if the procedure
and the CALL are contained in separately
assembled programs.) Different forms of the
CALL instruction allow the address of the target
procedure to be obtained from the instruction
itself (direct CALL) or from a memory location
or register referenced by the instruction (indirect
CALL). In the following descriptions, bear in
mind that the processor automatically adjusts IP
to point to the next instruction to be executed,
before saving it on the stack.

Table 2-14. Program Transfer Instructions

UNCONDITIONAL TRANSFERS

CALL
RET
JMP

Call procedure
Return from procedure
Jump
CONDITIONAL TRANSFERS

JA/JNBE

Jump if above/ not below
nor equal
Jump if above or
equal/not below
Jump if below / not above
nor equal
Jump if below or
equal/ not above
Jump if carry
Jump if equal/zero
Jump if greater/not less
nor equal
Jump if greater or
equal/not less
Jump if less/not greater
nor equal
Jump if less or equal/not
greater
Jump if not carry
Jump if not equal/not
zero
Jump if not overflow
J u m p if not parity / parity
odd
Jump if not sign
Jump if overflow
Jump if parity/parity
even
Jump if sign

JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JLlJNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS

For an intrasegment direct CALL, SP (the stack
pointer) is decremented by two and IP is pushed
onto the stack. The relative displacement (up to
±32k) of the target procedure from the CALL
instruction is then added to the instruction
pointer. This form of the CALL instruction is
"self-relative" and is appropriate for position- independent (dynamically relocatable) routines in
which the CALL and its target are in the same
segment and are moved together.
An intrasegment indirect CALL may be made
through memory or through a register. SP is
decremented by two and IP is pushed onto the
stack. The offset of the target procedure is
obtained from the memory word or 16-bit general
register referenced in the instruction and replaces
IP.
For an intersegment direct CALL, SP is
decremented by two, and CS is pushed onto the
stack. CS is replaced by the segment word contained in the instruction. SP again is decremented
by two. IP is pushed onto the stack and is
replaced by the offset word contained in the
instruction.

ITERATION CONTROLS

LOOP
Loop
LOOPE/LOOPZ
Loop if equal/zero
LOOPNE/LOOPNZ Loop if not equal/not
zero
JCXZ
Jump if register CX = 0

For an intersegment indirect CALL (which only
may be made through memory), SP is
decremented by two, and CS is pushed onto the
stack. CS is then replaced by the content of the
second word oithe doubleword memory pointer
referenced by the instruction. SP again is
decremented by two, and IP is pushed onto the
stack and is replaced by the content of the first
word of the doubleword pointer referenced by the
instruction.

INTERRUPTS

INT
INTO
IRET

Mn"monics © Intel, 1978

Interrupt
Interrupt ifoverflow
Interrupt return

2-44

8086 AND 8088 CENTRAL PROCESSING UNITS

RET optional-pop-value

An intersegment indirect JMP may be made only
through memory. The first word of the
doubleword pointer referenced by the instruction
replaces IP, and the second word replaces CS.

RET (Return) transfers control from a procedure
back to the instruction following the CALL that
activated the procedure. The assembler generates
an intrasegment RET if the programmer has
defined the procedure NEAR, or an intersegment
RET if the procedure has been defined as FAR.
RET pops the word at the top of the stack
(pointed to by register SP) into the instruction
pointer and increments SP by two. If RET is
intersegment, the word at the new top of stack is
popped into the CS register, and SP is again
incremented by two. If an optional pop value has
been specified, RET adds that value to SP. This
feature may be used to discard parameters pushed
onto the stack before the execution of the CALL
instruction.

Conditional Transfers

The conditional transfer instructions are jumps
that mayor may not transfer control depending
on the state of the CPU flags at the time the
instruction is executed. These 18 instructions (see
table 2-15) each test a different combination of
flags for a condition. If the condition is "true,"
then control is transferred to the target specified
in the instruction. If the condition is "false,"
then control passes to the instruction that follows
the conditional jump. All conditional jumps are
SHORT, that is, the target must be in the current
code segment and within -128 to +127 bytes of
the first byte of the next instruction (JMP OOH
jumps to the first byte of the next instruction).
Since the jump is made by adding the relative
displacement of the target to the instruction
pointer, all conditional jumps are self-relative and
are appropriate for position-independent
routines.

JMP target

JMP unconditionally transfers control to the
target location. Unlike a CALL instruction, JMP
does not save any information on the stack, and
no return to the instruction following the JMP is
expected. Like CALL, the address of the target
operand may be obtained from the instruction
itself (direct JMP) or from memory or a register
referenced by the instruction (indirect JMP).

Iteration Control

An intrasegment direct JMP changes the instruction pointer by adding the relative displacement
of the target from the JMP instruction. If the
assembler can determine that the target is within
127 bytes of the JMP, it automatically generates a
two-byte form of this instruction called a SHORT
JMP; otherwise, it generates a NEAR JMP that
can address a target within ±32k. Intrasegment
direct JMPS are self-relative and are appropriate
in position-independent (dynamically relocatable)
routines in which the JMP and its target are in the
same segment and are moved together.

The iteration control instructions can be used to
regulate the repetition of software loops. These
instructions use the CX register as a counter. Like
the conditional transfers, the iteration control
instructions are self-relative and may only
transfer to targets that are within -128 to +127
bytes of themselves, i.e., they are SHORT
transfers.
LOOP short-label

LOOP decrements CX by 1 and transfers control
to the target operand if CX is not 0; otherwise the
instruction following LOOP is executed.

An intrasegment indirect JMP may be made
either through memory or through a 16-bit
general register. In the first case, the content of
the word referenced by the instruction replaces
the instruction pointer. In the second case, the
new IP value is taken from the register named in
the instruction.

LOOPE/LOOPZ short-label

LOOPE and LOOPZ (Loop While Equal and
Loop While Zero) are different mnemonics for
the same instruction (similar to the REPE and

An intersegment direct JMP replaces IP and CS
with values contained in the instruction.
2-45

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-15. Interpretation of Conditional Transfers
MNEMONIC

CONDITION TESTED

"JUMP IF ... "

JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA
JC
JE/JZ
JG/JNLE
JGE/JNL
JLlJNGE
JLE/JNG
JNC
JNE/JNZ
JNO
JNP/JPO
JNS
JO
JP/JPE
JS

(CF OR ZF)=O
CF=O
CF=1
(CF OR ZF)=1
CF=1
ZF=1
((SF XOR OF) OR ZF)=O
(SF XOR OF)=O
(SF XOR OF)=1
((SF XOR OF) OR ZF)=1
CF=O
ZF=O
OF=O
PF=O
SF=O
OF=1
PF=1
SF=1

above/not below nor equal
above or equal/ not below
below / not above nor equal
below or equal/ not above
carry
equal/zero
greater / not less nor equal
greater or equal/not less
less/not greater nor equal
less or equal/ not greater
not carry
not equal/ not zero
not overflow
not parity / parity odd
not sign
overflow
parity / parity equal
sign

Note: "above" and "below" refer to the relationship of two unsigned values;
"greater" and "less" refer to the relationship of two signed values.

external hardware devices. The effect of software
interrupts is similar to hardware-initiated interrupts. However, the processor does not execute
an interrupt acknowledge bus cycle if the interrupt originates in software or with an NMI. The
effect of the interrupt instructions on the flags is
covered in the description of each instruction.

REPZ repeat prefixes). CX is decremented by 1,
and control is transferred to the target operand if
ex is not 0 and if ZF is set; otherwise the instruction following LOOPE/LOOPZ is executed.
LOOPNE/LOOPNZ short-label

LOOPNE and LOOPNZ (Loop While Not Equal
and Loop While Not Zero) are also synonyms for
the same instruction. CX is decremented by 1,
and control is transferred to the target operand if
ex is not 0 and if ZF is clear; otherwise the next
sequential instruction is executed.

INT interrupt-type

INT (Interrupt) activates the interrupt procedure
specified by the interrupt-type operand. INT
decrements the stack pointer by two, pushes the
flags onto the stack, and clears the trap (TF) and
interrupt-enable (IF) flags to disable single-step
and maskable interrupts. The flags are stored in
the format used by the PUSHF instruction. SP is
decremented again by two, and the es register is
pushed onto the stack. The address of the interrupt pointer is calculated by multiplying
interrupt-type by four; the second word of the interrupt pointer replaces CS. SP again is
decremented by two, and IP is pushed onto the
stack and is replaced by the first word of the interrupt pointer. If interrupt-type = 3, the assembler
generates a short (1 byte) form of the instruction,
known as the breakpoint interrupt.

JCXZ short-label

JeXZ (Jump If CX Zero) transfers control to the
target operand if CX is O. This instruction is
useful at the beginning of a loop to bypass the
loop if ex has a zero value, i.e., to execute the
loop zero times.
Interrupt Instructions

The interrupt instructions allow interrupt service
routines to be activated by programs as well as by
Mnemonics © Intel, 1978

2-46

8086 AND 8088 CENTRAL PROCESSING UNITS

Software interrupts can be used as "supervisor
calls," i.e., requests for service from an operating
system. A different interrupt-type can be used for
each type of service that the operating system
could supply for an application program. Software interrupts also may be used to check out
interrupt service procedures written for hardwareinitiated interrupts.

Table 2-16. Processor Control Instructions
FLAG OPERATIONS
STC
CLC
CMC
STO
CLO
STI
CLI

INTO

INTO (Interrupt on Overflow) generates a software interrupt if the overflow flag (OF) is set;
otherwise control proceeds to the following
instruction without activating an interrupt procedure. INTO addresses the target interrupt procedure (its type is 4) through the interrupt pointer
at location IOH; it clears the TF and IF flags and
otherwise operates like INT. INTO may be written following an arithmetic or logical operation to
activate an interrupt procedure if overflow
occurs.

Set carry flag
Clear carry flag
Complement carry flag
Set direction flag
Clear direction flag
Set interrupt enable flag
Clear interrupt enable flag
EXTERNAL SYNCHRONIZATION

HLT
WAIT
ESC
LOCK

Halt until interrupt or reset
Wait for TEST pin active
Escape to external processor
Lock bus during next
instruction
NO OPERATION

NOP

No operation

IRET

IRET (Interrupt Return) transfers control back to
the point of interruption by popping IP, CS and
the flags from the stack. IRET thus affects all
flags by restoring them to previously saved
values. IRET is used to exit any interrupt
procedure, whether activated by hardware or
software.

CMC
CMC (Complement Carry flag) "toggles" CF to
its opposite state and affects no other flags.

STC

Processor Control Instructions

STC (Set Carry flag) sets CF to 1 and affects no
other flags.

These instructions (see table 2-16) allow programs
to control various CPU functions. One group of
instructions updates flags, and another group is
used primarily for synchronizing the 8086 or 8088
with external events. A final instruction causes
the CPU to do nothing. Except for the flag opera.'
tions, none of the processor control instructions
affect the flags.

CLO

CLD (Clear Direction flag) zeroes DF causing the
string instructions to auto-increment the SI
and/or DI index registers. CLD does not affect
any other flags.

Flag Operations
CLC

STO

CLC (Clear Carry flag) zeroes the carry flag (CF)
and affects no other flags. It (and CMC and STC)
is useful in conjunction with the RCL and RCR
instructions.

STD (Set Direction flag) sets DF to 1 causing the
string instructions to auto-decrement the SI
and/or DI index registers. STD does not affect
any other flags.

2-47

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

it builds (see table 2-26). An external processor
may monitor the system bus and capture this
opcode when the ESC is fetched. If the source
operand is a register, the processor does nothing.
If the source operand isa memory variable, the
processor obtains the operand from memory and
discards it. An external processor may capture the
memory operand when the processor reads it
from memory.

CLI

CLI (Clear Interrupt-enable flag) zeroes IF.
When the interrupt-enable flag is cleared, the
8086 and 8088 do not recognize an external interrupt request that appears on the INTR line; in
other words maskable interrupts are disabled. A
non-maskable interrupt appearing on the NMI
line, however, is honored, as is a software interrupt. CLI does not affect any other flags.

LOCK

STI

LOCK is a one-byte prefix that causes the

STI (Set Interrupt-enable flag) sets IF to 1, enabling processor recognition of maskable interrupt requests appearing on the INTR line. Note
however, that a pending interrupt will not actually be recognized until the instruction following
STI has executed. STI does not affect any other
flags.

8086/8088 (configured in maximum mode) to

assert its bus LOCK signal while the following
instruction executes. LOCK does not affect any
flags. See section 2.5 for more information on
LOCK.

No Operation
External Synchronization
NOP
HLT

Nap (No Operation) causes the CPU to do
nothing. Nap does not affect any flags.

HL T (Halt) causes the 8086/8088 to enter the halt
state. The processor leaves the halt state upon
activation of the RESET line, upon receipt of a
non-maskable interrupt request on NMI, or, if
interrupts are enabled, upon receipt of a
maskable interrupt request on INTR. HL T does
not affect any flags. It may be used as an alternative to an endless software loop in situations
where a program must wait for an interrupt.

Instruction Set Reference Information
Table 2-21 provides detailed operational information for the 8086/8088 instruction set. The
information is presented from the point of view
of utility to the assembly language programmer.
Tables 2-17, 2-18 and 2-19 explain the symbols
used in table 2-21. Machine language instruction
encoding and decoding information is given in
Chapter 4.

WAIT

WAIT causes the CPU to enter the wait state
while its TEST line is not active. WAIT does not
affect any flags. This instruction is described
more completely in section 2.5.

Instruction timings are presented as the number
of clock periods required to execute a particular
form (register-to-register, immediate-to-memory,
etc.) of the instruction. If a system is running with
a 5 MHz maximum clock, the maximum clock
period is 200 ns; at 8 MHz, the clock period is 125
ns. Where memory operands are used, "+EA"
denotes a variable number of additional clock
periods needed to calculate the operand's effective address (discussed in section 2.8). Table 2-20
lists all effective address calculation times.

ESC externa/-opcode, source

ESC (Escape) provides a means for an external
processor. to obtain an opcode and possibly a
memory operand from the 8086 or 8088. The
external opcode is a 6-bit immediate constant that
the assembler encodes in the machine instruction
Mnemonics © Intel, 1978

2-48

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-17. Key to Instruction Coding Formats
IDENTIFIER

USED IN

EXPLANATION

destination

data transfer,
bit manipulation

A register or memory location that may contain data
operated on by the instruction, and which receives (is
replaced by) the result of the operation.

source

data transfer,
arithmetic,
bit manipulation

A register, memory location or immediate value that is
used in the operation, but is not altered by the instruction.

source-table

XLAT

Name of memory translation table addressed by register

BX.
target

JMP,CALL

A label to which control is to be transferred directly, or a
register or memory location whose content is the
address of the location to which control is to be transferred indirectly.

short-label

condo transfer,
iteration control

A label to which control is to be conditionally
transferred; must lie within -128 to +127 bytes of the first
byte of the next instruction.

accumulator

IN,OUT

Register AX for word transfers, AL for bytes.

port

IN,OUT

An I/O port number; specified as an immediate value of
0-255, or register OX (which contains port number in
range 0-64k).

source-string

string ops.

Name of a string in memory that is addressed by register
SI; used only to identify string as byte or word and
specify segment override, if any. This string is used in
the operation, but is not altered.

dest-string

string ops.

Name of string in memory that is addressed by register
01; used only to identify string as byte or word. This
string receives (is replaced by) the result of the operation.

count

shifts, rotates

Specifies number of bits to shift or rotate; written as
immediate value 1 or register CL (which contains the
count in the range 0-255).

interrupHype

INT

Immediate value of 0-255 identifying interrupt pOinter
number.

optional-pop-value

RET

Number of bytes (0-64k, ordinarily an even number) to
discard from stack.

external-opcode

ESC

Immediate value (0-63) that is encoded in the instruction
for use by an external processor.

2-49

Mnemonics © Intel. 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-19. Key to Operand Types

Table 2-18. Key to Flag Effects
IDENTIFIER

EXPLANATION

(blank)

not altered

0

cleared toO

1

set to 1

X

set or cleared according
to result

U

undefined-contains no
reliable value

R

restored from previouSlysaved value

IDENTIFIER
(no operands)
register
reg 16
seg-reg
accumulator
immediate
immed8
memory
mem8
mem16
source-table

For control transfer instructions, the timings
given include any additional clocks required to
reinitialize the instruction queue as well as the
time required to fetch the target instruction. For
instructions executing on an 8086, four docks
should be added for each instruction refer.en,ce to
a word operand located at an odd memory
address to reflect any additional operand bus
cycles required. Similarly for instructions executing on an 8088, four clocks should be added to
each instruction reference to a 16-bit memory
operand; this includes all stack operations. The
required number of data references is listed in
table 2-21 for each instruction to aid in this
calculation.

source-string
dest-string

ox
short-label
near-label
far-label
near-proc
far-proc

Several additional factors can increase actual
execution time over the figures shown in table
2-21. The time provided assumes that the instruction has already been prefetched and that it is
waiting in the instruction queue, an assumption
that is valid under most, but not all, operating
conditions. A series of fast executing (fewer than
two clocks per opcode byte) instructions can drain
the queue and increase execution time. Execution
time also is slightly impacted by the interaction of
the EU and BIU when memory operands must be
read or written. If the EU needs access to
memory, it may have to wait for up to one clock if
the BIU has already started an instruction fetch
bus cycle. (The EU can detect the need for a
memory operand and post a bus request far
enough in advance of its need for this operand to
avoid waiting a full 4-clock bus cycle). Of course
the EU does not have to wait if the queue is full,
because the BIU is idle. (This discussion assumes
Mnemonics © Intel, 1978

memptr16

memptr32

regptr16

repeat

EXPLANAT,ION
No operands are written
An 8- or 16-bit general register
A 16-bit general register
A segment register
Register AX or AL
A constant in the range
O-FFFFH
A constant in the range O-FFH
An 8- or f6-bit' memory
10cation(1)
An 8-bit memory 10cation(1)
A 16-bit memory 10cation(1)
Name of 256-byte translate
table
Name of string addressed by
registerSI
Name of string addressed by
register 01
Register OX
A label within -128 to +127
bytes of the end of the instruction
A label in current code
segment
A label in another code
segment
A procedure in current code
segment
A proceQure in another code
segment
A word containing the offset of
the location in the current code
segment to which control is to
be transferred(l)
A doubleword containing the
offset and the segment base
address of the location in
another code segment to which
control is to be transferred(l)i
A 16-bit general register
containing the offset of the
location In the current code
segment to which control is to
be transferred
A string instru\?tion repeat
prefix

(l)Any addressing mode-direct, register indirect, based, indexed, or based
indexed-may be used (see section 2.8).

2-50

8086 AND 8088 CENTRAL PROCESSING UNITS

that the BIU can obtain the bus on demand, i.e.,
that no other processors are competing for the
bus.)

Table 2-20. Effective Address Calculation
Time
CLOCKS·

EA COMPONENTS
Displacement Only
Base or Index Only
Displacement
+
Base or Index
Base
+
Index
Displacement
+
Base
+
Index

(BX,BP,SI,DI)

With typical instruction mixes, the time actually
required to execute a sequence of instructions will
typically be within 5-100/0 of the sum of the
individual timings given in table 2-21. Cases can
be constructed, however, in which execution time
may be much higher than the sum of the figures
provided in the table. The execution time for a
given sequence of instructions, however, is always
repeatable, assuming comparable external conditions (interrupts, coprocessor activity, etc.). If the
execution time for a given series of instructions
must be determined exactly, the instructions
should be run on an execution vehicle such as the
SDK-86 or the iSBC 86/12TM board .

6
5
9

(BX,BP ,SI,DI)
BP+DI, BX+SI
BP+SI, BX+DI
BP+DI+DISP
BX+SI+DISP
BP+SI+DISP
BX+DI+DISP

7

8
11
12

• Add 2 clocks for segment override

Table 2-21. Instruction Set Reference Data

I

AAA

AAA (no operands)
ASCII adjust for addition

Operands
, (no operands)

Clocks

Transfers·

Bytes

4

-

1

JAAD
(no operands)
ASCII adjust for division

AAD
Operands
(no operands)

AAM

Clocks

Transfers·

Bytes

60

-

2

(no operands)

Transfers·

Bytes

83

-

1

I

AAS

AAS (no operands)
ASCII adjust for subtraction

Operands

AAA

Coding Example

Transfers·

Bytes

4

-

1

ODITSZAPC
X X UX U
U

Coding Example
AAM

FI

Clocks

ODITSZAPC
XXUXU
U

AAD

Flags

Clocks

ODITSZAPC
U
UU X U X

Coding Example

Flags

IAAM (no operands)
ASCII adjust for multiply
Operands

(no operands)

Flags

ODITSZAPC
ags U
UU X U X
Coding Example

AAS

·For the 8086, add four clocks for each 16·blt word transfer with an odd address. For the 8088, add four clocks for each 16-blt word transfer.

2-51

Mnemonics © Intel,1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)
IADC destination,source
Add with carry

ADC

Flags

Operands

Clocks

Transfers·

Bytes

register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

3
9+EA
16+EA
4
17+EA
4

-

2
2-4
2-4
3-4
3-6
2-3

1
2

2

-

IADD destination, source
Addition

ADD
Operands

Clocks

Transfers·

Bytes

3
9+EA
16+EA
4
17+EA
4

-

2
2-4
2-4
3-4
3-6
2-3

1
2

2

-

lAND destination,source
Logical and

AND
Operands

Clocks

Transfers·

Bytes

3
9+EA
16+ EA
4
17+EA
4

-

2
2-4
2-4
3-4
3-6
2-3

1
2

-

2

-

I~ALL target

near-proc
far-proc
memptr16
regptr 16
memptr32

Clocks

Transfers·

Bytes

19
28
21 +EA
16
37+EA

1
2
2
1
4

3
5
2-4
2
2-4

I~BW (no operands)

CBW
(no operands)

Clocks

Transfers·

Bytes

2

-

1

ODITSZAPC
X
X X X X X

Coding Example
ADD
ADD
ADD
ADD
ADD
ADD

CX, OX
01, [BX].ALPHA
TEMP, CL
CL,2
ALPHA,2
AX, 200

ODITSZAPC
0
XX U X 0

Coding Example
AND
AND
AND
AND
AND
AND

AL,BL
CX,FLAG_WORD
ASCII [DI],AL
CX,OFOH
BETA,01H
AX,01010000B

ODITSZAPC

Coding Examples
CALL
CALL
CALL
CALL
CALL

NEAR_PROC
FAR_PROC
PROC_TABLE [SI]
AX
[BX].TASK [SI]

Flags

Convert byte to word

Operands

AX,SI
DX,BETA[SI]
ALPHA [BX] [SI], 01
BX,256
GAMMA,30H
AL,5

Flags

Call a procedure

Operands

ADC
ADC
ADC
ADC
ADC
ADC

Flags

register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

CALL

Coding Example

Flags

register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

ODITSZAPC
X
X X X X X

ODITSZAPC

Coding Example
CBW

'For the 8086, add .four clocks for each 16-blt word transfer With an odd address. For the 8088, add four clocks for each 1,6-blt word transfer.
Mnemonics © Intel, 1978

2-52

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

CLC (no operands)
Clear carry flag

CLC
Operands
(no operands)

Flags

Clocks

Transfers·

Bytes

2

-

1

I

CLD (no operands)
Clear direction flag

CLD
Operands
(no operands)

Transfers·

Bytes

2

-

1

I

CLI (no operands)
Clear interrupt flag

CLI
Operands
(no operands)

Clocks

Transfers·

Bytes

2

-

1

CMC (no operands)
Complement carry flag

Operands
(no operands)

Clocks

Transfers·

Bytes

2

-

1

CMP destination,source
Compare destination to source
Clocks

Transfers·

Bytes

register, register
register, memory
memory, register
register, immediate
memory, immediate
accumulator, immediate

3
9+EA
9+EA
4
10+EA
4

-

2
2-4
2-4
3-4
3-6
2-3

1
1

1

-

I

CMPS dest-string,source-string
Compare string

CMPS
Operands

dest-string, source-string
(repeat) dest-string, source-string

CLD

CLI

Transfers·

Bytes

22
9+22/rep

2
2/rep

1
1

ODITSZAPC
X

Coding Example
CMC

ODITSZAPC
X X X X X
X

Coding Example
CMP
CMP
CMP
CMP
CMP
CMP

BX, CX
DH, ALPHA
[BP + 2], SI
BL,02H
[BX].RADAR [DI], 3420H
AL,00010000B

Flags

Clocks

ODITSZAPC
0

Coding Example

Flags

Operands

ODITSZAPC
0

Coding Example

Flags

I

CMP

CLC

Flags

I

CMC

Coding Example

Flags

Clocks

ODITSZAPC
0

ODITSZAPC
X
X X X X X

Coding Example
CMPS BUFF1, BUFF2
REPE CMPS 10, KEY

'For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.

2-53

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

CWO (no operands)
Convert word to doubleword

CWD
Operands
(no operands)

Flags

Clocks

Transfers·

Bytes

5

-

1

I

DAA (no operands)
Decimal adjust for addition

DAA
Operands
(no operands)

Transfers·

Bytes

4

-

1

I

DAS (no operands)
Decimal adjust for subtraction

DAS
Operands
(no operands)

Clocks

Transfers·

Bytes

4

-

1

DEC destination
Decrement by 1

Operands
reg16
reg8
memory

Transfers·

Bytes

2
3
15+EA

-

1
2
2-4

2

I

DIV source
Division, unsigned

DIV
Operands
reg8
reg16
mem8
mem16

Operands
immediate, memory
immediate, register

ODITSZAPC
U
XXXXX

Coding Example
DAS

ODITSZAPC
X X X X
X.

Codlng Example
DEC AX
DEC AL
DEC ARRAY [SI]

Flags

ODITSZAPC
U
U U UU U

Coding Example

Clocks

Transfers·

Bytes

80-90
144-162
(86-96)
+EA
(150-168)
+EA

1

2
2
2-4

DIV CL
DIV BX
DIV ALPHA

1

2-4

DIV TABLE [SI]

-

Flags 0 D ITS ZAP C

ESC external-opcode,sourc.e
Escape

ESC

DAA

Flags

Clocks

ODITSZAPC
XXXXX
X

Coding Example

Flags

I

DEC

Coding Example
CWO

Flags

Clocks

ODITSZAPC

Clocks

Transfers·

8+EA
2

1

-

Bytes
2·4
2

Coding Example
ESC 6,ARRAY [SI]
ESC 20,AL

-For the 8086, add four clocks for each 16-blt word transfer with an odd address. For the 8086, add four clocks for each 16-bit word transfer.

Mnemonics © Intel, 1978

2-54

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)
I HLT (no operands)
Halt

HLT
Operands
(no operands)

Clocks

Transfers·

Bytes

2

-

1

IIDIV source
Integer division

IDIV
Operands
reg8
reg16
mem8
mem16

Operands
reg8
. reg16
mem8
mem16

Operands
accumulator, immed8
accumulator, DX

Operands

ODITSZAPC
U
U U UU U

Clocks

Transfers·

Bytes

1

2
2
2-4

IDIV BL
IDIV CX
IDIV DIVISOR_BYTE [SI]

1

2-4

IDIV [BX].DIVISOR_WORD

-

Coding Example

Flags

ODITSZAPC
X
UUUUX

Clocks

Transfers·

Bytes

80-98
128·154
(86-104)
+EA
(134-160)
+EA

1

2
2
2-4

IMUL CL
IMUL BX
IMUL RATE_BYTE

1

2-4

IMUL RATE_WORD [BP] [DI]

Coding Example

Flags

Clocks

Transfers·

Bytes

10
8

1
1

2
1

IINC destination
Increment by 1

INC

HLT

101-112
165-184
(107-118)
+EA
(171-190)
+EA

IN accumulator,port
Input byte or word

IN

ODITSZAPC

Coding Example

Flags

IIMUL source
Integer multiplication

IMUL

reg16
reg8
memory

Flags

Coding Example
IN AL, OFFEAH
IN AX, OX

Flags

Clocks

Transfers·

Bytes

2
3
15+EA

-

1
2
2-4

2

ODITSZAPC

ODITSZAPC
X
X X X X

Coding Example
INC CX
INC BL
INC ALPHA [01] [BX]

'For the 8086, add four clocks for each 16·blt word transfer wIth an odd address. For the 8088, add four clocks for each 16-blt word transfer.

2-55

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)
liNT interrupt-type
Interrupt

INT
Operands
immed8 (type = 3)
immed8 (type"* 3)

Clocks

Transfers·

Bytes

52
51

5
5

1
2

INTR (external maskable interrupt)
Interruptif INTR and IF=1

INTRt
Operands
(no operands)

Operands
(no operands)

Clocks

Transfers·

Bytes

61

7

N/A

Operands
(no operands)

Clocks

Transfers·

Bytes

53 or 4

5

1

Operands
short-label

Clocks

Transfers·

Bytes

24

3

1

Clocks

Transfers·

Bytes

16 or 4

-

2

I JAE/JNB short-label
Jump if above or equal/Jump.if not below

JAE/JNB
Operands
short-label

ODITSZAPC

o0

Coding Example
N/A

o

Clocks

Transfers·

Bytes

16 or 4

-

2

0 I. T S ZAP C
o0

Coding Example
INTO

Flags

I JA/JNBE short-label
Jump if above/Jump if not below nor equal

JA/JNBE

INT 3
INT 67

Flags

IIRET (no operands)
Interrupt Return

IRET

Coding Example

Flags

IINTO (no operands)
Interrupt if overflow

INTO

ODITSZAPC
o0

Flags

ODITSZAPC
RRRRRRRRR

Coding Example
IRET

Flags

ODITSZAPC

Coding Example
JA ABOVE

Flags

ODITSZAPC

Coding Example
JAE ABOVE_EQUAL

...

I JB/JNAE short-label
Jump if below/Jump if not above nor equal

JB/JNAE
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

Flags

ODITSZAPC

Coding Example
JB BELOW

• For the 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
tlNTR is not an instruction; it is included in table 2-21 only for timing information.

Mnemonics © Intel, 1978

2-56

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

JBE/JNA short-label
Jump if below or equal/ Jump if not above

JBE/JNA
Operands
short-label

Transfers·

Bytes

16 or 4

-

2

I

JC short-label
Jump if carry

JC
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

JCXZ short-label
Jump if CX is zero

Operands
short-label

Transfers·

Bytes

18 or 6

-

2

I

JEI JZ short-label
Jump if equal/Jump if zero

JE/JZ
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

I

JGE/JNL short-label
Jump if greater or equal/Jump if not less

JGE/JNL
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

I

JL/JNGE short-label
Jump if less/ Jump if not greater nor equal

JL/JNGE
Operands

Clocks

Transfers·

Bytes

16 or 4

-

2

ODITSZAPC

Coding Example
JC CARRY _SET

ODITSZAPC

Coding Example
JCXZ COUNT_DONE

Flags

IJG/JNLE short-label
Jump if greater/ Jump if not less nor equal

JG/JNLE

JNA NOT_ABOVE

Flags

Clocks

ODITSZAPC

Coding Example

Flags

I

JCXZ

short-label

Clocks

Flags

ODITSZAPC

Coding Example
JZ ZERO

Flags

ODITSZAPC

Coding Example
JG GREATER

Flags

ODITSZAPC

Coding Example
JGE GREATER_EQUAL

Flags

ODITSZAPC

Coding Example
JL LESS

'Forthe 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.

2-57

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

JLE/JNG short-label
Jump if less or equal/Jump if not greater

JLE/JNG
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

I

JMP target
Jump

JMP
Operands
short-label
near-label
far-label
memptr16
regptr16
memptr32

Clocks

Transfers·

Bytes

15
15
15
18+EA
11
24+EA

-

2
3
5
2-4
2
2-4

1

2

JNC short-label
Jump if not carry

Operands
short-label

Transfers·

Bytes

16 or 4

-

2

I

JNE/JNZ short-label
Jump if not equal/Jump if not zero

JNE/JNZ
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

JNO short-label
Jump if not overflow

Operands
short-label

Transfers·

Bytes

16 or 4

-

2

I

JNP/JPO short-label
Jump if not parity/Jump if parity odd

JNP/JPO
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

JNS short-label
Jump if not sign

Operands
short-label

SHORT
WITHIN_SEGMENT
FAR_LABEL
[BX].TARGET
CX
OTHER.SEG [SI]

JNC NOT_CARRY

Transfers·

Bytes

16 or 4

-

2

ODITSZAPC

Coding Example
JNE NOT _EQUAL

ODITSZAPC

Coding Example
JNO NO_OVERFLOW

ODITSZAPC

Coding Example
JPO ODD_PARITY

Flags

Clocks

ODITSZAPC

Coding Example

Flags

I

JNS

JMP
JMP
JMP
JMP
JMP
JMP

Flags

Clocks

ODITSZAPC

Coding Example

Flags

I

JNO

JNG NOT_GREATER

Flags

Clocks

ODITSZAPC

Coding Example

Flags

I

JNC

Flags

ODITSZAPC

Coding Example
JNS POSITIVE

'For the 8086, add four clocks for each 16-blt word transfer with an odd addrtlss. For the 8088, add four clocks for each 16-blt word transfer.
Mnemonics © Intel, 1978

2-58

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

JO short-label
Jump if overflow

JO
Operands
short-label

Clocks

Transfers·

Bytes

160r4

-

2

I

JP/JPE short-label
Jump if parity I Jump if parity even

JP/JPE
Operands
short-label

Clocks

Transfers·

Bytes

16 or 4

-

2

JS short-label
Jump if sign

Operands
short-label

Transfers·

Bytes

16 or 4

-

2

I

LAHF (no operands)
Load AH from flags

LAHF
Operands
(no operands) .

Clocks

Transfers·

Bytes

4

-

1

LOS destination,source
Load pOinter using OS

Operands
reg16, mem32

Transfers

Bytes

16+EA

2

2-4

I

LEA destination,source
Load effective address

LEA
Operands
reg16, mem16

Clocks

Transfers·

Bytes

2+EA

-

2-4

LES destination,source
Load pointer using ES

Operands

Coding Example

Transfers·

Bytes

16+EA

2

2-4

OOITSZAPC

Coding Example
LAHF

OOITSZAPC

Coding Example
LOS SI,OATA.SEG [01]

OOITSZAPC

Coding Example
LEA BX, [BP] [01]

Flags

Clocks

OOITSZAPC

JS NEGATIVE

Flags

I

LES

JPE EVEN_PARITY

Flags

Clocks

OOITSZAPC

Coding Example

Flags

I

LOS

JO SIGNEO_OVRFLW

Flags

Clocks

OOITSZAPC

Coding Example

Flags

I

JS

reg16, mem32

Flags

OOITSZAPC

Coding Example
LES 01, [BX].TEXT_BUFF

'Forthe 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8086, add four clocks for each 16-bit word transfer.

2-59

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

LOCK (no operands)
Lock bus

LOCK
Operands
(no operands)

Flags

Clocks

Transfers'

Bytes

2

-

1

I

LODS source-string
Load string

LODS
Operands
source-string
(repeat) source-string

Transfers'

Bytes

12
9+13/rep

1
1/rep

1
1

I

LOOP short-label
Loop

LOOP
Operands
short-label

LOOPE/LOOPZ

Clocks

Transfers'

Bytes

17/5

-

2

LOOPE/LOOPZ short-label
Loop if equal/Loop if zero

short-label

Clocks

Transfers'

Bytes

18 or 6

-

2

I

Operands

Clocks

Transfers'

Bytes

19 or 5

-

2

I

NMI (external nonmaskable interrupt)
Interrupt if NMI = 1

NMlt
Operands
(no operands)

LODS CUSTOMER_NAME
REP LODS NAME

Clocks

Transfers'

Bytes

50'

5

N/A

ODITSZAPC

Coding Example
LOOP AGAIN
ODITSZAPC

Coding Example
LOOPE AGAIN

Flags

Loop If not equal I Loop If not zero

ODITSZAPC

Coding Example

Flags

LOOPNE/LOOPNZ LOO~NE/LOOPNZ sho.rt-Iabel
short-label

LOCK XCHG FLAG,AL

Flags

I

Operands

Coding Example

Flags

Clocks

ODITSZAPC

ODITSZAPC

Coding Example
LOOPNE AGAIN

Flags

OSITSZAPC
o0

Coding Example
N/A

'Forthe 8086, add four clocks for each 16-bit word transfer with an odd address. For the 8088, add four clocks for each 16-bit word transfer.
tNMI is not an instruction; it is included in table 2-21 only for timing information.

Mnemonics © Intel, 1978

2-60

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (Cont'd.)

I

MOV destination,source
Move

MOV
Operands
memory, accumulator
accumulator, memory
register, register
register, memory
memory, register
register, immediate
memory, immediate
seg-reg, reg16
seg-reg, mem16
reg16, seg-reg
memory, seg-reg

Transfers·

Bytes

10
10
2
8+EA
9+EA
4
10+EA
2
8+EA
2
9+EA

1
1

3
3
2
2-4
2-4
2-3
3-6
2
2-4
2
2-4

1
1

1

1

1

MOVS dest-string,source-string
Move string

Operands
dest-string, source-string
(repeat) dest-string, source-string

MOVSB/MOVSW

ODITSZAPC

Bytes

Coding Example

18
9 + 17/rep

2
2/rep

1
1

MOVS LINE EDIT_DATA
REP MOVS SCREEN, BUFFER

Flags

Clocks

Transfers·

Bytes

18
9+17/rep

2
2/rep

1
1

MUl source
Multiplication, unsigned

Operands

ARRAY [SI], Al
AX, TEMP _RESULT
AX,CX
BP, STACK_TOP
COUNT [01], CX
Cl,2
MASK [BX] [SI], 2CH
ES, CX
OS, SEGMENT_BASE
BP, SS
[BX].SEG_SAVE, CS

Transfers·

I

MUL

MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

Clocks

MOVSB/MOVSW (no operands)
Move string (byte/word)

(no op,erands)
(repeat) (no operands)

ODITSZAPC

Coding Example

Flags

I

Operands

mem16

Clocks

I

MOVS

reg8
reg16
mem8

Flags

ODITSZAPC

Coding Example
MOVSB
REP MOVSW

Flags

ODITSZAPC
U U UU X
X

Coding Example

Clocks

Transfers·

Bytes

70-77
118-133
(76-83)
+EA
(124-139)
+EA

-

1

2
2
2-4

MUl Bl
MUl CX
MUl MONTH [SI]

1

2-4

MUl BAUD_RATE

-

"For the 8086, add four clocks for each 16-bit word transfer with an odd address. For Ihe 8088, add four clocks for each 16-bit word transfer.

2-61

Mnemonics © Inlel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

Table 2-21. Instruction Set Reference Data (,<, "',>=, <=

"TRUE" - FFH
"FALSE"-OH

LOGICAL

AND, OR, XOR, NOT

8'16-BIT STRING

2-77

8086 AND 8088 CENTRAL PROCESSING UNITS

I****SCALARS**** I
DECLARE SWITCH
DECLARE COU NT
INDEX
DECLARE (NET, GROSS,

BYTE;
WORD,
INTEGER;
TOTAL) REAL;

I****ARRAYS**** I
BYTE;
DECLARE MONTH (12)
DECLARE TERMINAL_LINE (80)

BYTE;

I****STRUCTURE**** I
DECLARE EMPLOYEE STRUCTURE
(lD_NUMBER
DEPARTMENT
RATE

WORD,
BYTE
REAL);

1*1 SCALAR* I
1*1 SCALAR*I
1*3 SCALARS* I

1**** ARRAY OF STRUCTURES**** I
DECLARE INVENTORY_ITEM (100)
STRUCTURE
(PART_NUMBER
WORD,
ON_HAND
WORD,
RE_ORDER
BYTE);
1**** ARRAY WITHINSTRUCTURE****I
DECLARE COUNTY_DATA
STRUCTURE
BYTE,
(NAME (20)
TEN_ YR_RAINFALL(10)
BYTE,
PER CAPITA_INCOME
REAL);

Figure 2-48. PL/M-86 Data Declarations

I*ARITHMETIC* I

A = 2; B = 3;
B = B+ 1;
C = (A*B) -2;
C = ((A*B) + 3) MOD 3;

I*B CONTAINS 4* I
I *C CONTAINS 6* I
I *C CONTAINS 2* I

I*RELATIONAL * I
A=2; B=3
C= B>A;
C= B<>A;
C= B = (A+1);

I*C CONTAINS OFFH* I
I*C CONTAINS OFFH* I
I*C CONTAINS OFFH* I

I*LOGICAL'I
A = 0011 $0001 B;
B = 1000$0001 B;
C= NOT B;
C= AAND B;
C=AOR B;
C= BXORA;
C = (A AND B) OR OFOH;

I*$IS FOR READABILlTY* I
I*C
I*C
I*C
I*C
I*C

CONTAINS 0111$1110B* I
CONTAINS 0000$0001 B* I
CONTAINS 1011$0001 B* I
CONTAINS 1011$0000B* I
CONTAINS 1111$0001 B* I

Figure 2-49. Expressions in PL/M-86 Assignment Statements
2-78

8086 AND 8088 CENTRAL PROCESSING UNITS

A DOblock begins with a DO statement and ends
with an END statement. All intervening
statements are part of the block. A DO block can
appear anywhere in a program that an executable
statement can appear. There are four kinds of DO
statements in PLlM-86: simple DO, DO CASE,
interative DO, and DO WHILE.

Program Flow Statements

Simple PL/M-86 programs can be written with
just DECLARE and assignment statements. Such
programs, however, execute exactly the same
sequence of statements every time they are run
and would not prove very useful. PL/M-86 provides statements that change the flow of control
through a program. These statements allow sections of the program to be executed selectively,
repeated, skipped entirely, etc.

A simple DO statement (figure 2-51) causes all the
statements in the block to be treated as though
they were a single statement. Simple DOs enable a
single IF statement to cause multiple statements
to be executed (the alternative would be to repeat
the IF statement for every statement, to be
executed).

The IF statement (figure 2-50) selects one or the
other of two statements 'for execution depending
on the result of a relational expression. The IF
statement is written:

'·SIMPLE DO·'
A=5; B=9;
IF(A+2)< BTHEN DO;
X=X-1;
Y(X)=O;
END;
ELSE DO;
X=X+1'
Y(X)=1;
END;

IF relational-expression
THEN statement1;
ELSE statement2;

Statementl is executed if the expression is "true";
statement2 hfnot executed'lil this case. If the relation is "false," statementl is skipped and statement2 is executed. In determining the "truth" of
an expression, the IF statement only examines the
low-order bit of the result (1="true"). Therefore,
arithmetic and logical expressions also may' be
used in an IF statement.

X=X+2;
X=X+3;

MORE_DATA = OFFH;
IF NOT MORE_DATA
THEN DONE=1;
ELSE DONE = 0;

'·SKIPPED·'
'"SKIPPED'''

'·00 CASE·'
A=2;'
DO CASE (A);

X=X+1;

A=3; B=5;
IFA=999
'"SKIPPED"'
THEN SPACE_OK';' 0;
END;
/"PO WHILE"'
CODE = 'A';
DO WHH-E (CODE c= •A');
TEMP ~ TEMP" STEP;
IFTEMP>98.6
THEN CbOE = 'B';

'"EXECUTION STOPS"'
'"AFTER TEMP"'
'"EXCEEDS 98.6"'
N~STEPS= N~STEPS + 1;
END;
,

FigO're2-S2. PL/M-86 Iterative DO and DO WHILE
2-80

'0

8086 AND 8088 CENTRAL PROCESSING UNITS

INDEX-START
FALSE

OUTOF
RANGE

EXECUTE
BLOCK

EXECUTE
BLOCK

INDEX-INDEX+STEP

Figure 2-54. PLlM-86 DO WHILE Flowchart

activates a procedure defined earlier in the program. The variables listed in "parm-list" are
passed to the procedure, the procedure is
executed, and then control returns to the statement following the CAbL. Thus, unlike a GOTO,
a CALL. brings control back to the point of
departure.
Figure 2-53. PLlM-86 Iterative DO Flowchart

A GOTO written in the form
GOTO target;
causes an unconditional transfer (branch) to
another statement in the program. The statement
receiving control would be written
target: statement;
where "target" is a label identifying the
statement.
A CALL statement written in the form

CALL proc-name (parm-list);

Procedures
Procedures are "subprograms" that make it
possible to simplify the design of complex programs and to share a single copy of a routine
among prggrams. A procedure usually is designed
to perform'one function;'Le., to solve one part of
total problem with which the program is dealing. For example, a program to calculate
paychecks could be broken down into separate
procedures for calculating gross pay, income tax,
Social Security and net pay. The organization of
the "main" program then could be understood at
a glance:

the

"CALLGROSS~PAY;

CALL INCOME_TAX;
CALL SOCIAL_SECURITY;
CALL NET_PAY;

'8086 AHo8088'CENTRAt"PROCESSfNG UN.ITS
Furthermore, the .income tax procedure could be
divided into separate procedures for calCulating
state and federal taxes. Procedures, then, provide
a mechanism by whicli'il large, complex problem
can be attacked with a "divide and conquer"
strategy.

a value. Untyped procedllres are activated by
CALL statements:: Figure 2-55 shows how simple
typed and untyped procedures may be declared
and then activated.
The statements forming the body of a procedure
need not exist within the module that activates the
procedure. The activating module can declare the
procedure EXTERNAL, and the LINK-86 utility
will connect the two modules.

A procedure usually is defined early in a program,
but it is only executed when.' it is referred to by
name in a later PLlM-86 statement. A procedure
can accept a list of variables, called parameters,
that it will use in performing its function. These
parameters may assume different values each time
the procedure is executed.

PLlM-86 procedures can be written to handle
interrupts. Procedures also may be declared
REENTRANT, making them concurrently usable
by different tasks in' a multitasking system.
PLlM-86 also has about 50 procedures built into
the language, including facilities for:

PL/M-86 provides two classes 'of procedures,
typed and untyped. A typed procedure n:turns a
value to the statement that activates it and, in
addition, may accept parameters from that statement. A typed procedure is ~ctivated whenever its
name appears in a statement; tqe value it returns
effectively takes the place:ofthe procedure name
in the statement. Typed procedures can be used in
all kinds of PLlM,86 expressions. Untyped procedures may accept parameters, but do'not return

•
•
•
•
•

converting variables fr,om one type to another
shifting and rotating bits
performing input and output
manipulating strings
activating the 'CPU LOCK signal.

!·DECLARATION OF A TYPED PROCEDURE THAT
ACCEPTS TWO REAL PARAMETERS AND RETURNS AREAL VALUE"!
AVG: PROCEDURE (X,Y) REAL;
DECLARE (X,Y) REAL.:;·
RETURN (X+Y)!2.0;
ENDAVG;
!·ACTIVATING A TYPED PROCEDURE·!
LOW=2.Q;
HIGH ;"3.0;,
,,
:rOTAL = TOT~L + AVG (LOW,'HIGH); !·2.5IS ADDED TO TOTAL *!
!*QECLAFIATION OF AN UNTYPED PROCEDURE
.THAT ACCEPTS ONE PARAMETER*!
,
TEST: PROCEDUFIE (X);
DECLARE X BYTE;
IFX = OH THEN'
COONT= COUNT +1;
END TEST;
!*ACTIVATING AN UNTYPED PROCEDURE"!
CALL TEST (ALPHA); .I"COUNT IS INCREMENTED
.'
, , IF ALPHA = 0* !
.•If

'.

Figu~e 2-55. PL/M-86 Procedures
2-82

8086 AND 8088 CENTRAL PROCESSING UNITS

languages. ASM-86 also simplifies the programmer's "view" of the 8086/8088 machine instruction set. For example, although there are 28 different types of MOV machine instructions, the
programmer always writes a single form of the
instruction:

ASM-86
Programmers who are familiar with the CPU
architecture can obtain complete access to all processor facilities with ASM-86. Since the execution
unit on both the 8086 and the 8088 is identical,
both processors use the same assembly language.
Examples of processor features not accessible
through PLlM-86 that can be utilized in ASM-86
programs include: software interrupts, the WAIT
and ESC instructions and explicit control of the
segment registers.

MOV destination-operand, source-operand

The assembler generates the correct machineinstruction form based on the attributes of the
source and destination operands (attributes are
covered later in this section). Finally, the ASM-86
assembler performs extensive checks on the consistency of operand definition versus operand use
in instructions, catching many common types of
clerical errors.

An ASM-86 program often can be written to
execute faster andlor to use less memory than the
same program written in PLlM-86. This is
because the compiler has a limited "knowledge"
of the entire program and must generate a
generalized set of machine instructions that will
work in all situations, but may not be optimal in a
particular situation. For example, assume that the
elements of an array are to be summed and the
result placed in a variable in memory. The
machine instructions generated by the PL/M-86
compiler would move the next array element to a
register and then add the register to the sum
variable in memory. An ASM-86 programmer,
knowing that a register will be "safe" while the
array is summed, could instead add all the array
elements to a register and then move the register
to the sum variable, saving one instruction execu~
tion per array element.

Statements

Compared to many assemblers, ASM-86 accepts a
relaxed statement format (see figure 2-56). This
helps to, reduce clerical errors and allows programmers to format their programs for better
readability. Variable and label names may be up
to 31 characters long and are not restricted to
alphabetic and numeric characters. In particular,
the underscore (_) may be used to improve the
readability oflong names. Blanks may be inserted
freely between identifiers (there are no "column"
requirements), and statements also may span
multiple lines.

It is easier to write assembly language programs in

All ASM-86 statements are classified as instructions or directives. A clear distinction must be
made here between AS'M-86 instructions and

ASM-86 than it is in many assembly languages.
ASM-86 contains powerful data structuring
facilities that are usually found only in high-level

; TH IS ST ATEM ENT CONTAINS A COM M ENT ON L Y
AX, [BX + 3)
MOV AX,
[BX
MOV
AX,
[BX+3)
&

; TYPICAL ASM-86 INSTRUCTION
; BLANKS NOT SIGNIFICANT

MOV

+ 3)

; CONTINUED STATEMENTS

ZERO
EQU
0
; SIMPLE ASM-86 DIRECTIVE
CUR_PROJ eQU
PROJECT [BX} [SI)
; MORE COMPLEX DIRECTIVE
THE_STACLSTARTS_HERE SEGMENT; LONG IDENTIFIER
TIGHT_LOOP: JMPTIGHT_LOOP
; LABELLED STATEMENT
MOV ES: DATA_STRING [SI), AL
; SEGMENT OVERRIDE PREFIX
WAIT: LOCK XCHG AX,SEMAPHORE
; LABEL & LOCK PREFIX

Figure 2-56. ASM-86 Statements
2-83

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAt PROCESSING UNITS

8086/8088 machine instructions. The assembler
generates machine instructions from ASM-86
instructions written by a programmer. Each
ASM-86 instruction produces one machine
instruction, but the form of the generated
machine instruction will vary according to the
operands written in the ASM-86 instruction. For
example, writing·

Writing a directive gives ASM·86 information ,10
use in generating instructions, but do.es not itself
produce .a machine instruction. About 20 different directives are available in ASM-86. Directives are written like this:
(name) mnemonic (operand(s)) (;comment)

MOV BL,1

produces a byte-immediate-to-register MOV,
while writing
MOVTERMINAL_NO,BX

produces a word-register-to-memory MOV. To
the programmer, though, there is simply a MOV
source-to-destination instruction.
ASM-86 instructions are written in the form:
(label:) (prefix) mnemonic (operand(s)) (;comment)

where parentheses denote optional fields (the
parentheses are not actually written by programmers). The label field names the storage location
containing the machine instruction so that it can
be referred to symbolically as the target of a JMP
instruction elsewhere in the program. Writing a
prefix causes ASM-86 to generate one of the
special prefix bytes (segment override, bus lock or
repeat) immediately . preceding the machine
instruction. The mnemonic identifies the type of
instruction (MOV for move, ADD for add, etc.)
that is to be generated. Zero, one or two operands
may be written next, separated by commas,
according to the requirements of the instruction.
Finally, writing a semicolon signifies that what
follows is a comment. Comments do not affect
the execution of a program, but they can greatly

MOV
MOV
ADD
OCTAL_8
OCTAL'-:9
ALL_ONES
MINUS_5
MINUS_6

improve its clarity; all good ASM-86 programs
are thoughtfully commented.

STRING [SI), 'A'
STRING [SI), 41 H
AX,OC4H
EQU 100
EQU 10Q
EQU 11111111'B
EQU -5

EqU

-60

Some directives require a name to be present,
while others prohibit a name. ASM-86 recognizes
the directive from the mnemonic keyword written
in the next field. Any operands required by the
directive are written next, separated by commas.
A comment may be written as the last field of a
directive.
Some. of the more commonly used directives
define procedures (PROC), allocate storage for
variables (DB, DW, DD) give a descriptive name
to a number or an expression (EQU), define the
bounds of segments (SEGMENT and ENDS),
and force instructions and data to be aligned at
word boundaries (EVEN).
Constants

Binary, decimal, octal and hexadecimal numeric
constants (see figure 2-57) may be written in
ASM-86 statements; the assembler can perform
basic arithmetic operations on these as well. All
numbers must, however, be integers and must be
representable in 16 bits including a sign bit.
Negative numbers are a~sembled in standard
two's complement notation.
Character constants are enclosed in single quotes
and may be up to 255 characters long when used

; CHARACTER
; EQUIVALENT IN HEX
; HEX CONSTANT MUST START WITH NUMERAL
; OCTAL
; OCTAL ALTERNATE
; BINARY·.
; DECIMAL
; DECIMAL ALTERNATE

Figure 2-57. ASM-86 Constants
Mnemonics © Intel, 197&

8086 AND 8088 CENTRAL PROCESSING UNITS

ing segment. Type identifies the variable's allocation unit (1 = byte, 2 = word, 4 = doubleword).
When a variable is referenced in an instruction,
ASM-86 uses these attributes to determine what
form of the instruction to generate. If the
variable's attributes conflict with its usage in an
instruction, ASM-86 produces an error message.
For example, attempting to add a variable defined
as a word to a byte register is an error. There are
cases where the assembler must be explicitly told
an operand's type. For example, writing MOVE
[BX],5 will produce an error message because the
assembler does not know if [BX] refers to a byte,
a word or a doubleword. The following operators
can be used to provide this information: BYTE
PTR, WORD PTR and DWORD PTR. In the
previous example, a word could be moved to the
location referenced by [BX] by writing MOVE
WORD PTR [BX],5.

to initialize storage. When used as immediate
operands, character constants may be one or two
bytes long to match the length of the destination
operand.
Defining Data

Most ASM-86 programs begin by defining the
variables with which they will work. Three directives, DB, DW and DD, are used to allocate and
name data storage locations in ASM-86 (see
figure 2-58). The directives are used to define
storage in three different units: DB means
"define byte," DW means "define word," and
DD means "define doubleword." The operands
of these directives tell the assembler how many
storage units to allocate and what initial values, if
any, with which to fill the locations.

A_SEG
ALPHA
BETA
GAMMA
DELTA
EPSILON
A_SEG

SEGMENT
DB
?
DW
?
DD
?
DB
?
DW
5
ENDS

B_SEG
IOTA
KAPPA
LAMBDA
MU
B_SEG

SEGMENT AT 55H ; SPECIFYING BASE ADDRESS
DB
'H£LLO'
; CONTAINS 48454C 4C4F H
DW
'AB'
; CONTAINS 42 41 H
B_SEG
; CONTAINS 0000 5500 H
DD
DB
100 DUP 0 ; CONTAINS (100 Xl OOH
ENDS

ASM-86 also provides two built-in operators,
LENGTH and SIZE, that can be written in
ASM-86 instructions along with attribute
information. LENGTH causes the assembler to
return the number of storage units (bytes, words
or doublewords) occupied by an array. SIZE
causes ASM-86 to return the total number of
bytes occupied by a variable or an array. These
oPerators and attributes make it possible to write
generalized instruction sequences that need not be
changed (only reassembled) if the attributes of the
variables change (e.g., a byte array is changed to a
word array). See figure 2-59 for an example of
using the attributes and attribute operators.

; NOT INITIALIZED
; NOT INITIALIZED
; NOT INITIALIZED
; NOT INITIALIZED
; CONTAINS 05H'

ATTRIBUTES

OPERATORS

VARIABLE

SEGMENT

OFFSET

TY.PE

LENGTH

SIZE

ALPHA
BETA
GAMMA
DELTA
EPSILON
IOTA
KAPPA
LAMBDA
MU

A_SEG
A_SEG
ILSEG
A_SEG
A_SEG
B_SEG
B_SEG
B_SEG
B_SEG

0
1

1
2
4
1
2
1
2
4
1

1
1
1
1
1
5
1.
1
100

1
2
4
1
2
5
2
4
100

3
7
8
0
5
7
11

Records
ASM-86 provides a means of symbolically defining individual bits and strings of bits within a byte
or a word. Such a definition is called a record,
and each named bit string (which may consist of a
single bit) in a record is called a field. Records
promote efficient use of storage while ilt the same
time improving the readability of the program
and reducing the likelihood of clerical errors.
Defining a record does not· allocate storage;
rather, a record is a template that tells the
assembler the name and location of each bit field
within the byte or word. When a field Ilame is
written later in an instruction, ASM-86 uses the
record to generate an immediate mask for instructions like TEST, AND, OR, etc., or an immediate
count for shifts and rotates. See figure 2-60 for an
,example of using a record.

Figure 2-58. ASM-86 Data Definitions

For every variable in an ASM-86 program, the
assembler keeps track of three attributes: segment, offset and type. Segment identifies the segment that contains the variable (segment control
is covered shortly). Offset is the distance in bytes
of the variable from the beginning of its contain2-85

8086 ANO·8088CENTRAL,PROCESSING UNITS

; SUM THE CONTENlS OF TABLE INTO AX
TABLE
DW
50 DUP(?)
; NOTE SAME INSTRUCTIONS WOULD WORK FOR
; TABLE
DB
25 DUP(?)
; TABLE
DW
118 DUP(?), ETC.
SUB
MOV
MOV

AX,AX
; CLEAR SUM
CX, LENGTH TABLE; LOOP TERMINATOR
,jPOINT SUBSCRIPT
SI, SIZE TABLE
; TO ENDOFTABLE.
ADD_NEXT: SUB
SI, TYPE TABLE.
; BACK UP ONE ELEMENT
ADD
AX, TABLE [SI]
; ADD ELEMENT
LOOP
ADD_NEXT
; UNTlLCX=O
; AX CONTAINS SU M

Figure 2-59. Using ASM-86,Attributes and Attribute Operators

EMP_BYTE DB ?
; 1I3YTE, UNINITIALIZED
; BIT DEFINITIONS: .
7-2 : YEARS EMPLOYED
1
: SEX (1 = FEMALE)
0 : STATUS (1 = EXEMPT)
iRECORDDEFINED HERE
EMP _BITSAECORD
&
YRS_EMP : 6,
.
&
SEX:1,
&
STATUS: 1

; SELECT NONEXEMPT FEMALES EMPLOYED10+YEARS
AL, EMP _BYTE
; KEEP ORIGINAL INTACT
MOV
TEST
AL,MASKSEX
; FEMALE?
•
R E J E C T ; NO, QUITE
JZ
AL, MASK STATUS .; NbNEX~MPT?
TEST
JNZ
REJECT'
';NO, QUIT,
AL, CL '
; ISOLATE YEARS
SHR
CMP
AL,11
; >=10 YEARS?
JL
REJECT
; NO, QUIT
; PROCESS SELECTED EMPLOYEE

REJECT: ; PROCESS REJECTED EMPLOYEE
; RECORD USED HERE
; GET SHIFT COUNT

MOV

Figure 2-60. USirigan ASM-86 RECORD Defirtition
Mnemonics © Intel, 1978

2-86

8086 AND 8088 CENTRAL PROCESSING UNITS

Structures

Addressing Modes

An ASM-86 structure is a map, or template, that
gives names and attributes (length, type, etc.) to a
collection of fields. Each field in a structure is
defined using DB, DW and DD directives;
however, no storage is allocated to the structure.
Instead, the structure becomes associated with a
particular area of memory when a field name is
referenced in an instruction along with a base
value. The base value "locates" the structure; it
may be a variable name or a base register (BX or
BP). The structure may be associated with
another area of memory by specifying a different
base value. Figure 2-61 shows how a simple structure may be defined and used. Note that a structure field may itself be a structure, allowing much
more complex· organizations to be laid out.

Figure 2-62 provides sample ASM-86 coding for
each of the 8086/8088 addressing modes. The
assembler interprets a bracketed reference to BX,
BP, SI or DI as a base or index register to be used
to construct the effective address of a memory
operand. An unbracketed reference means the
register itself is the operand.
The following cases illustrate typical ASM-86
coding for accessing arrays and structures, and
show which addressing mode the assembler
specifies in the machine instruction it generates:
•

If ALPHA is an array, then ALPHA [SI] is

the element· indexed by SI, and ALPHA
[SI + 1] is the following byte (indexed).
•

Structures are particularly useful in situations
where the same storage format is at multiple locations, ,where the location of a collection of
variables is not known at assembly-time, and
where the location of a collection of variables
changes during execution. Applications include
multiple buffers for a single file, list processing
and stack addressing.

If ALPHA is the base address of a structure

and BET A is a field in the structure, then
ALPHA. BETA selects the BETA field
(direct).
•

If register BX contajns the base address of a

structure and BETA is a field in the structure, then [BX].BETA refers to the BETA
field (based).

EMPLOYEE
SSN
RATE
DEPT
YR_HIRED
EMPLOYEE

STRUC
DB 9
DB 1
DW 1
DB 1
ENDS

DUP(?)
DUP(?)
DUP(?)
DUP(?)

MASTER
TXN

DB
DB

12
12

DUP(?)
DUP(?)

; CHANGE RATE IN MASTER TO VALUE IN TXN.
MOV
AL, TXN.RATE
MOV
MASTER-,RATE, AL
; ASSUME BX POINTS TO AN AREA CONTAINING
DATA IN THE SAME FORMAT AS THE EMPLOYEE
STRUCTURE. ZERO THE SECOND DIGIT
. OF SSN
MOV
SI,1; INDEXVALUE OF 2ND DIGIT
MOV
[BX].SSN[SI],O

Figure 2-61. Using an ASM-86 Structure
2-87

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

ADO
ADO
ADD
ADD
AD,D
ADO
ADD
ADD
ADD
ADD
ADD
ADD
IN
OUT

AX,BX
AL,5
CX,ALPHA
ALPHA,6
·ALPHA,DX
·BL, [BX]
[SI], BH
[PP].AlPHA, AH
CX, ALPHA [SI]
ALPHA [DI+2], 10
[BX].ALPHA [SI], AL
SI, [BP+4] [DI]
AL,30
DX,AX

; REGISTER +- REGISTER
; REGISTER -IMMEDIATE
; REGISTER +- MEMORY (DIRECT)
; MEMORY (DIRECT) -IMMEDIATE
; MEMORY (DIRECT)- REGISTER
; REGISTER"" MEMORY (REGISTER INDIRECT)
; MEMORY (REGISTER INDIRECT) -IMMEDIATE
; MEMORY (BASED) - REGISTER
; REGISTER - MEMORY (INDEXED)
; MEMORY (INDEXED) -IMMEDIATE
; MEMORY (BASED INDEXED) - REGISTER
; REGISTER +- MEMORY (BASED INDEXED)
; DIRECT PORT
; INDIRECT PORT

.Figure 2-62. ASM -86 Addressing Mode Examples

•

•

•

•

instructions written between SEGMENT and
ENDS are· part of the named segment. In small
programs, variables often are defined in one or
two segment(s), stack space is allocated in another
segment, and instructions are written in a third or
fourth segment. It is perfectly possible, however,
to write a complete program in one segment; if
this is done, all the segment registers will contain
the same base address; that is, the memory
segments will completely overlap.. Large programs may be divided into dozens of segmentS.

If register BX. contains the:a,ddress of an
array, then [BX) [Sil refers to the element
indel(ed by SI (based indexed).
If register BX points to a structure whose
ALPHA .field is an array, then [BX)
.ALPtIA lSI) selects the element indexed by
SI (based indexed).
If register BX points to a structure whose
ALPHA field is itself a structure, then
[BX).ALPHA.BETA refers to the BETA
field of the ALPHA substructure (based).
If register BX points to a structure and the
ALPHA field of the structure is an array and
each element of ALPHA is a structure, then
[BX).ALPHA[SI + 3).BETA refers to the
field BETA in the element of ALPHA
indexed by lSI + 3) (based indexed).

The Jirst instructions in a program usually
establish the correspondence between segment
names and segment registers, and then load each
segment register with the base address of its corresponding segment. The ASSUME .directive tells
the assembler what addresses will be in the segment registers at execution time. The assembler
checks each memory instruction operand, determines which segment it is in and which segment
register contains the address of that. segment. If
the assumed register is the register expected by the
hardw~re for that instruction type, then the
assembler generates the machine instruction normally. If, however, the hardware expects one seg~
ment register to be used, and the operand is not in
the segment pointed to by that register, then the
assembler automatically precedes the machine
instruction with a segment override prefix byte.
(If the segment can riot be .overridden, the
assembler produces an error message.) An example may clarify this. If register BP is used in an
instruction, the 8086 and 8088 CPUs expect, as a
default, that the memory operand will be located
in the segment pointed to by SS-in the current

Note that DI may be used in place of SI in these
cases and 'that BP may be substituted for BX.
Without a segment override prefix, expressions
containing BP refer to the current stack segment,
and expressions containing BX refer to the cur.
rent data segment. .

Segment Control
An ASM-8.6 prpgram is organized into a series of
named segments. These are "logical" ,segments;
they are eventually mapped into 8086/8088
. memory segments, but this usually is . not done
until the program is located~ A SEGMENT directivestarts a segment, and an ENDS directive ends
the segment (see figure 2-63). All data and
Mllemonics © Intel. 1978 .

2~88

8086 AND 8088 CENTRAL PROCESSING UNITS

DATA_SEG
SEGMENT
; DATA DEFIN ITIONS GO HERE
DATA_SEG
ENDS
STACK_SEG SEGMENT
; ALLOCATE 100 WORDS FOR A STACK AND
LABEL THE INITIAL TOS FOR LOADING SP.
OW 100 DUP(?)
STACK TOP LABEL WORD
STACK_SEG
ENDS
CODE_SEG
SEGMENT
; GIVE ASSEMBLER INITIAL REGISTER-TO-SEGMENT
; CORRESPONDENCE. NOTE THAT IN THIS
; PROGRAM THE EXTRA SEGMENT INITIALLY
; OVERLAPS THE DATA SEGMENT ENTIRELY.
ASSUME CS: CODE_SEG,
&
OS: DATA_SEG,
&
ES: DATA_SEG,
&
SS: ST ACK_SEG
START:

; THIS IS THE BEGINNING OFTHE PROGRAM.
; LOC-S6 WILL PLACE A JMP TO THIS
; LOCATION AT ADDRESS FFFFOH.

; LOAD THE SEGMENT REGISTERS. CS DOES NOT
HAVE TO BE LOADED BECAUSE SYSTEM
RESET SETS IT TO FFFFH, AND THE
LONG JMP INSTRUCTION AT THAT ADDRESS
UPDATES IT TO THE ADDRESS OF CODE_SEG.
SEGMENT REGISTERS ARE LOADED FROM AX
BECAUSE THERE IS NO IMMEDIATE-TOSEGMENT_REGISTER FORM OF THE MOV
INSTRUCTION.
MOV AX, DATA_SEG
MOV DS,AX
MOV ES, AX
MOV AX, STACK_SEG
MOV SS, AX
; SET STACK POINTER TO INITIAL TOS.
MOV SP,OFFSET STACK_TOP
; SEGMENTS ARE NOW ADDRESSABLE.
; MAIN PROGRAM CODE GOES HERE.
CODE_SEG
ENDS
; NEXT STATEMENT ENDS ASSEMBLY ANDTELLS
LOC-S6 THE PROGRAMS STARTING ADDRESS.
END

START

Figure 2-63. Setting Up ASM-86 Segments
2-89

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

stack segment. A programmer may, however,
choose to use BP to address a variable in the current data segment-the segment pointed to by
DS. The ASSUME directive enables the assembler
to detect this situation and to automatically
generate the needed override prefix.

PLlM-86. Figure 2-64 shows how procedures
may be defined.and called in ASM-86. Section
2-10 contains examples of procedures that accept
parameters on the stack.

LlNK-86
It also is possible for a programmer to explicitly
code segment override prefixes rather than relying
on the assembler. This may result in a somewhat
better-documented program since attention is
called to the override. The disadvantage of
explicit segment overrides is that the assembler
does not check whether the operand is in fact
addressable through the overriding segment
register.

Fundamentally, LINK-86 combines separate
relocatable object modules into a single program.
This process consists primarily of combining
(logical) segments of the same name into single
segments, adjusting relative addresses when
segments are combined, and resolving external
references.
A programmer can use a procedure that is actually contained in another module by naming the
procedure in an ASM-86 EXTRN directive, or
declaring the procedure to be EXTERNAL in
PLlM-86. The procedure is defined or declared
PUBLIC in the module where it actually resides,
meaning that it can be used by other modules.
When LINK-86 encounters such an external
reference, it searches through the other modules
in its input, trying to find the matching PUBLIC
declaration. If it finds the referenced object, it
links it to the reference, "satisfying" the external
reference. If it· cannot satisfy the reference,
LINK-86 prints a diagnostic message. LINK-86
also checks PLlM-86 procedure calls and function references to insure that the parameters
passed to a procedure are the type expected by the
procedure.

ASM-86, in conjunction with the relocation and
linkage facilities, provides much more
sophisticated segment handling capabilities than
have been described in this introduction. For
example, different logical segments may be combined into the same physical segment, and
segments may be assigned the same physicallocations (allowing a "common" area to be accessed
by different programs using different variable
and label names).

Procedures
Procedures may be written in ASM-86 as well as
in PLlM-86. In fact, procedures written in one
language are callable from the other, provided
that a few simple conventions are observed in the
ASM-86 program. The purpose of ASM-86 procedures is the same as in PLlM-86: to simplify the
design of complex programs and to make a single
copy of a commonly-used routine accessible from
anywhere in the program.

LINK-86 gives the programmer, particularly the
ASM-86 programmer, great control over
segments (segments may be combined end to end,
renamed, assigned the same locations, etc.).
LINK-86 also produces a map that summarizes
the link process and lists any unusual conditions
encountered. While the output of LINK-86 is
generally input to LOC-86, it also may again be
input to LINK-86 to permit modules to be linked
in incremental groups.

An ASM-86 program activates a procedure with a
CALL instruction. The procedure terminates with
a RET instruction, which transfers control to the
instruction following the CALL. Parameters may
be passed in registers or pushed onto the stack
before calling the procedure. The RET instruction
can discard stack parameters before returning to
the caller.

LOC-86
LOC-86 accepts the single relocatable object
module produced by LINK-86 and binds the
memory references in the module to actual
memory addresses. Its output is an absolute
object module ready for loading into the memory
of an execution vehicle. LOC-86 also inserts a

Unlike PLlM-86 procedures, ASM-86 procedures
are executable where they are coded, as well as by
a CALL instruction. Therefore, ASM-86 procedures often are defined following the main program logic, rather than preceding it as in
Mnemonips © Intel, 1978

2-90

8086 AND 8088 CENTRAL PROCESSING UNITS

FREQUENCY

DB

256 DUP (0)

USART_DATA
USART_STAT

EQU
EQU

OFFOH
OFF2H

NEXT:

CALL
CALL
JMP

CHAR_IN
COUNT_IT
NEXT

; DATA PORT ADDRESS
; STATUS PORT ADDRESS

CHAR_IN
PROC
; THIS PROCEDURE DOES NOT TAKE PARAMETERS.
rrSAMPLESTHE USARTSTATUS PORT
UNTIL A CHARACTER IS READY, AND
THEN READS THE CHARACTER INTO AL
MOV
DX, USART_STAT
AGAIN:
IN
AL, DX
; READ STATUS
AL,2
; CHARACTER PRESENT?
AND
; NO, TRY AGAIN
JZ
AGAIN
DX, USART_DATA
MOV
IN
AL, DX
; YES, READ CHARACTER
RET
CHAR_IN
ENDP
COUNT_IT
PROC
; THIS PROCEDURE EXPECTS A CHARACTER IN AL.
IT INCREMENTS A COUNTER IN A FREQUENCY
TABLE BASED ON THE BINARY VALUE OF
THE CHARACTER.
XOR
AH, AH
; CLEAR HIGH BYTE
SI, AL
; INDEX INTO TABLE
MOV
FREQUENCY [S); BUMP THE COUNTER
INC
RET
ENDP

Figure 2-64. ASM-86 Procedures
are a convenient way to make collections of
modules available to LINK-86. When a module
being linked refers to "external" data or instructions, LINK-86 can automatically search a series
of libraries, find the referenced module, and
include it in the program being created.

direct intersegment JMP instruction at location
FFFFOH. The target of the JMP instruction is the
logical beginning of the program. When the 8086
or 8088 is reset, this instruction is automatically
executed to restart the system. LOC-86 produces
a memory map of the absolute object module and
a table showing the address of every symbol
defined in the program.

OH-86
OH-86 converts an absolute object module into
Intel's standard hexadecimal format. This format
is used by some PROM programmers and system
loaders, such as the iSBC 957™ and SDK-86
loaders.

LlB-86
LIB-86 is a valuable adjunct to the R & L programs. It is used to maintain relocatable object
modules in special files called libraries. Libraries

2-91

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

CONV-86
Users who have developed substantial, fullytested assembly language programs for the
SOSO/SOS5 microprocessors may want to use
CON V-S6 to automatically convert large amounts
of this code into ASM-S6 source code (see figure
2-65). CONV-S6 accepts an ASM-SO source program as input and produces an ASM-S6 source
program as output, plus a print file that
documents the conversion and lists any diagnostic
messages.

CONV-86

,-,
- -

Some programs cannot be completely converted
by CONV-S6. Exceptions include:
•
•
•
•

self-modifying code,
software timing loops,
SOS5 RIM and SIM instructions,
interrupt code, and

•

macros.

I

1---I

By using the diagnostic messages produced by
CONV-S6, the converted ASM-S6 source file can
be manually edited to clean up any sections not
converted. A converted program is typically
10-20070 larger than the ASM-SO version and does
not take full advantage of the SOS6/S0SS architecture. However, the development time saved by
using CONY -S6 can make it an attractive alternative to rewriting working programs from
scratch.

EDIT

)

'-1.J
/EDiTEii 7

--~ ASM-86
- , SOURCE

I

~~~~

Figure 2-65. ASM-80/ ASM-86 Conversion

The dice program runs on an SDK-86 that is connected to an Intellec® Microcomputer Development System. The program displays two continuously changing digits in the upper left corner
of the InteIlec display. The digits are random
numbers in the range 1-6. A roll is started by
entering a monitor GO command. Pressing the
INTR key on the SDK-S6 keypad stops the roll.

Sample Programs

There are two procedures in the PL/M-S6 version
of the dice program. The first is called CO for
console output. This is an untyped PUBLIC procedure that is supplied on an SDK-CS6 diskette.
CO is written in PLlMcS6 and outputs one
character to the Intellec console. It is declared
EXTERNAL in the dice program because it exists
in another module. LINK-S6 searches' the
SDK"C86 library for CO and includes it in the
single relocatable object module it builds.

Figures 2-66 and 2-67 show how a simple program
might be written in PLlM-S6 and ASM-S6. The
program simulates a pair of rolling dice and
executes on an Intel SDK-S6 System Design Kit.
The SDK-S6 is an SOS6-based computer with
memory, parallel and serial 110 ports, a keypad
and a display. The SDK-S6 is implemented on a
single PC board which includes a large prototype
area for system expansion and experimentation.
A ROM-based monitor program provides a user
interface to the system; commands are entered
through the keypad and monitor responses are
written on the display. With the addition of a
cable and software interface (called SDK-CS6),
theSDK-S6 may be connected to an Intellec®
Microcomputer Development System. In this
mode, the user enters monitor commands from
the Intellec keyboard and receives replies on the
Intellec CRT display.
Mnemonics © Intel, 1978

___(

RANDOM is an internal typed procedure; it is
contained in the dice module and returns a word
value that is a random number between 1 and 6.
RANDOM does not use any parameters and is
activated in the parameter list passed to CO.
When CO is called like this, first RANDOM is activated,. then 30 is added to the number it returns
and the sum is passed to CO.
2-92

8086 ANO,s088 CENTRAL PROCESSING UNITS
PL/M-86 COMPILER

DICE

ISIS-II PL/M-86 Vl.2 COMPILATION OF MODULE DICE
OBJECT MODULE PLACED IN :Fl:DICE.OBJ
COMPILER INVOKED BY: PLM86 :Fl:DICE.P86 XREF
DICE: DO;
/* THIS PROGRAM SIMULATES THE HOLL OF A PAIR OF DICE */
/* GIVE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

2

3

4

5
6

NAMES TO CONSTANTS */
CLEAR$CRTl
LITERALLY 'OlBH';
CLEAR$CRT2
LITERALLY '045H';
HOME$CURSORl
LITERALLY 'OlBH';
HOME$CURSOR2
LITERALLY '048H';
SPACE
LITERALLY'020H';

/* PROGRAM VARIABLES */
DECLARE (RANDOM$NUMBER,SAVE)
8
9

10

1
2

1
2
2
2

15
16
17

2
2
2

WORD;

/* CONSOLE OUTPUT PROCEDURE */
CO: PROCEDURE(X) EXTERNAL;
DECLARE X
BYTE;
END CO;

2

11
12
13
14

/* INTELLEC */
/* CRT
*/
/* CONTROL */
/* CODES
*/
/"ASCII BLANK*/

/* RANDOM NUMBER GENERATOR PROCEDURE
"/
/* ALGORITHM FOR 16-BIT RANDOM NUMBER FROM:
*/
/*
"A GUIDE TO PL/M PROGRAMMING FOR
"/
/"
MICROCOMPUTER APPLICATIONS,"
*/
/*
DANIEL D. MCCRACKEN,
*/
/*
ADDISON-WESLEY, 1978
"/
RANDOM: PROCEDURE WORD;
RANDOM$NUMBER = SAVE;
/*START WITH OLD NUMBER"/
RANDOM$NUMBER = 2053 * RANDOM$NUMBER + 13849;
SAVE = RANDOM$NUMBER;
/"SAVE FOR NEXT TIME"/
/"FORCE 16-BIT NUMBER INTO RANGE 1-6*/
RANDOM$NUMBER = RANDOM$NUMBER MOD 6 + 1;
RETURN RANDOM$NUMBER;
END RANDOM;
/* MAIN ROUTINE */
/* CLEAR THE SCREEN*/
CALL CO(CLEAR$CRT1);
CALL CO(CLEAR$CRT2);

18
19

1* ROLL THE DICE ·UNTIL INTERRUPTED "/

20
21
22
23

2
2
2

24
25
26

2
2
2

DO WHlhE 1;
/*"DO FOREVER"*/
/*NOTE THAT ADDING 30 TO THE
/" CONVERTS IT TO ASCII.
CALL CO(RANDOM + 030H);
CALL CO(SPACE);
CALL CO(RANDOM + 030H);
/* HOME THE CURSOR */
CALL CO(HOME$CURSOR1);
CALL CO(HOME$CURSOR2);
END;

DIE VALUE */
*/

/"lST DIE*/
/"BLANK*/
/*2ND DIE"/

END DICE;

27

CROSS-REFERENCE LISTING
DEFN

ADDR

SIZE

NAME, ATTRIBUTES, AND REFERENCES
---~--------------------~-------

2

8

OOOOH
0002H

CLEARCRTl

LITERALLY
18

CLEARCRT2

LITERALLY
19

CO

PROCEDURE EXTERNAL(O) STACK=OOOOH
24
21
22
25
18
19
23

DICE

PROCEDURE STACK=0004H

4

HOMECURSORl

LITERALLY
24

5

HOMECURSOR2

LITERALLY
25

RANDOM

PROCEDURE WORD STACK=0002H
21
23

11

0049H

71

44

Figure 2-66. Sample PL/M-86 Program
2-93

8086 AND 8:088CE",TRAL PROCESSING UNITS

7

OOOOH

2

RANDOMNUMBER

WORD
12

13

0002H

2

SAVE

WORD
12

14

SPACE

LITERALLY
22

X

BYTE PARAMETER
'9

OOOOH

14

15

16

MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
VARIABLE AREA SIZE
MAXIMUM STACK SIZE
51 LINES REJlD
o PROGRAM ERROR(S)

0075H
OOOOH
0004H
0004H

117D
OD
4D
4D

END OF PL/M-86 COMPILATION

Figure 2-66. Sample PL/M-86 Program (Cont'd.)
MCS-86 MACRO ASSEMBLER

DICE

ISIS-II MCS~86 MACRO ASSEMBLER V2.0 ASSEMBLY OF MODULE DICE
OBJECT MODULE PLACED IN :Fl:DICE.OBJ
A'SSEMBLER INVOKED BY: ASM86 :Fl :DICE .. A86 XREF
LOC

OBJ

LINE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

0000
0002
0004
0006
0008
OOOA

18
19
20
21
22
23
24
25
26
27
28
29
30

lBOO
4500
lBOO
4800
?OOO
????

0000' (20

SOURCE
THIS PROGRAM SIMULATES THE ROLL OF A PAIR OF DICE
CONSOLE OUTPUT PROCEDURE
EXTRN
CO: NEAR
; SEGMENT GROUP DEFINITIONS NEEDED FOR PL/M-86 C.OMPATIBILITY
CGROUP GROUP
CODE
DGROUP GROUP
DATA,STACK
INFORM ASSEMBLER OF SEGMENT REGISTER CONTENTS.
ASSUME, CS:CGROUP,DS:DGROUP,SS:DGROUP,ES:NOTHING
; ALLOCATE DATA
DATA
SEGMENT PUBLIC 'DATA'
NOTE THAT THE FOLLOWING ARE PASSED ON THE STACK TO THE PL/M-86
PROCEDURE 'CO'. BY CONVENTION, A BYTE PARAMETER IS PASSED IN
THE LOW-ORDER 8-BITS OF A WORD ON THE STACK. HENCE, THESE ARE
bLE:~~F~m AS Wo~e VALUE~i'i3~HOUGH i~nL~~gupy 1 BYTE ONLY.
CLEAR-CRT2
DW
045H
CRT'
·HOME GURSOR 1
DW
01 BH
CONTROL
HOME-CURSOR2
DW
048H
CODES
SPACE
DW
020H
ASCII BLANK
SAVE
DW
HOLDS LAST 16-BIT RANDOM NUMBER
DATA
ENDS
; ALLOCATE STACK SPACE
STACK
SEGMENT STACK
'STACK'
DW
20 DUP (?)
.

??1?

0028

0000
0000 A10AOO

R

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

; LABEL INITIAL TOS: FOR LATER USE.
STACK TOP
LABEL
WORD
STACK- ENDS
; PROGRAM CODE
CODE
SEGMENT PUBLIC

RANDOM NUMBER GENERATOR PROCEDURE
ALGORITHM FOR 16-BIT RANDOM NUMBER FROM:
"A GUIDE TO PL/M PROGRAMMING FOR
MICROCOMPUTER APPLICATIONS,"
DANIEL D. MCCRACKEN
;
ADDISON-WESLEY, 1978
'RANDOM PROC
MOV
AX, SAVE
; NEW NUMBER

Figur~
,Mnemonll'S © Intel, 1978

'CODE'

2-67. ASM-86 Sample Program

8086 AND 8088 CENTRAL PROCESSING UNITS

MCS-86

~ACRO

LOC

OBJ

0003
0006
0008
OOOB

B90508
F7El
051936
A30AOO

OOOE
0010
0013
0015
0017
0018

2BD2
B90600
F7Fl
8BC2
40
C3

ASSEMBLER

DICE
LINE
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101

0019 B8---001C 8ED8
001E 8EDO
0020 Bc2800
0023
0027
002A
002E

SOURCE

~8

FF360000
E80000
FF360200
E80000

0031 E8CCFF
003~ 0430
0036 50
0037 E80000
003A FF360800
003E E80000
0041 E8BCH
00~4 0430
0046 50
0047 E80000

E
R
E

004A FF360400
OO~E E80000
0051 FF360600
0055 E80000

R
E
R
E

0058 EBD7

RANDOM

MOV
CX,2053
OLD NUMBER • 2053
MUL
CX
+ 13849
ADD
AX,13849
MOV
SAVE,AX
SAVE FOR NEXT TIME
; FORCE 16-BIT NUMBER INTO RANGE 1 - 6
BY MODULO 6 DIVISION + 1
SUB
DX,DX
CLEAR-UPPER DIVIDEND
MOV
SET DIVISOR
CX,6
DIV
CX
DIVIDE BY 6
MOV
AX,DX
REMAINDER TO AX
INC
AX
ADD 1
RET
RESULT IN AX
ENDP

MAIN PROGRAM
LOAD SEGMENT REGISTERS
NOTE PROGRAM DOES NOT USE ES; CS IS INITIALIZED BY HARDWARE RESET;
DATA & STACK ARE MEMBERS OF SAME GROUP, SO ARE TREATED AS A SINGLE
MEMORY SEGMENT POINTED TO BY BOTH DS & SS.
START: MOV
AX,DGROUP
MOV
DS,AX
MOV
SS,AX
INITIALIZE STACK POINTER
MOV
SP,OFFSET DGROUP:STACK TOP
CLEAR THE SCREEN
PUSH
CLEAR _CRT 1
CALL
CO
PUSH
CLEAR_CRT2
CALL
CO
; ROLL THE DICE UNTIL INTERRUPTE
ROLL:
CALL
RANDOM
ADD
AL,030H
PUSH
AX
CALL
CO
PUSH
SPACE
CALL
CO
RANDOM
CALL
ADD
AL,030H
PUSH
AX
CALL
CO
HOME THE CURSOR
PUSH
HOME CURSORl
CALL
CO
PUSH
HOME_ CURSOR2
CALL
CO
CONTINUE FOREVER
JMP
ROLL
CODE
ENDS

GET 1ST DIE IN AL'
CONVERT TO ASCII
PASS IT 1'0
CONSOLE ,OUTPUT
OUTPUT
A BLANK
GET 2ND DIE IN AL
CONVERT TO ASCII
PASS IT TO
CONSOLE OUTPUT

XREF SYMBOL TABLE LISTING
----- ------NAME

TYPE

??SEG
CGROUP.
CLEAR CRT 1.
CLEAR:::CRT2.
CO.
CODE.
DATA.
VGROUP.
flOME CURSOR 1.
HOMCCURSOR2.
RANDOM.
ROLL.
SAVE.
SPACE
STACK •
STACK TOP
START-.

SEGMENT
GROUP
V WORD
V WORD
L NEAR
SEGMENT
SEGMENT
GROUP
V WORD
V WORD
L NEAR
L NEAR
V WORD
V WORD
SEGMENT
V WORD
L NEAR

VALUE

OOOOH
0002H
OOOOH

0004H
0006H
OOOOH
0031H
OOOAH
0008H
0028H
0019H

ATTRIBUTES, XREFS
SIZE=OOOOH PARA
CODE
711 11
DATA 1911 77
DATA 2011 79
EXTRN 411 78 80
SIZE=005AH PARA
SIZE=OOOCH PARA
DATA STACK
811
DATA 2111 94
DATA 2211 96
CODE 4611 60 83
CODE 8311 99
DATA 2411 ~7 51
DATA 2311 87
SIZE=002,8H PARA
STACK :'211 7~
CODE 6911 104

PUBLIC

86 88 92 95 97
PUBLIC 'CODE' 711 37 100
PUBLIC 'DATA' 811 14 25
11 11 69 74
89

STACK 'STACK'

ASSEMBLY COMPLETE, NO ERRORS FOUND

Figure 2-67. ASM-86 Sample Program (Cont'd.)
2-95

Mnemonics © Intel. 1978

SqS6 AND. 8088 CENTRAL PROCESSING UNITS
take advantage of new hardware and software
products that are constantly being introduced
by Intel.

The ASM-86 version of the dice program operates
like the PLlM-86 version. Since the program uses
the PLlM-86 CO procedure for writing data to
the Intellec console, it adheres to certain conventions established by the PLlM-86 compiler. The
program's logical segments (called CODE,
DATA and STACK-the program does not use
an extra segment) are organized into two groups
called CGROUP and DGROUP. All the members
of a group of logical segments are located in the
same 64k byte physical memory segment.
Physically, the program's DATA and STACK
segments can be viewed as "subsegments" of
DGROUP.

Segments and Segment Registers

Segments should be considered as independent
logical units whose physical locations in memory
happen to be defined by the contents of the segment registers. Programs should be independent
of the actual contents of the segment registers and
of the physical locations of segments in memory.
For example, a program should not take
advantage of the "knowledge" that two segments
are physically adjacent to each other in memory.
The single exception to this fully-independent
treatment of segments is that a program may set
up more than one segment register to point tothe
same segment in memory, thereby obtaining
addressability through more than one segment
register. For example, if both DS and ES point to
the.same segment,a string located in thatsegment
may be used as a source operand in one string
instruction and as a destination string in another
instruction. (recall that a destination string must
be located in the extra segment).

PLlM-86 procedures expect parameters to be
passed on the stack, so the program pushes each
character before calling CO. Note that the stack
will be "cleaned up" by the PLlM-86 procedure
before returning (i.e., the parameter will be
removed from the stack by CO).

2.10 Programming Guidelines
and Examples
This section addresses 8086/8088 programming
from two different perspectives. A series of
general guidelines is presented first. These
guidelines apply to all types of systems and are
intended to make software easier to write, and
particularly, easier to maintain and enhance. The
second part contains a number of specific programming examples. Written primarily in
ASM-86, these examples illustrate how the
instruction set and addressing modes may be utilized in various, commonly encountered programming situations.

Any data aggregate or construct such as an array,
a structure, a string or a stack should be restricted
to 64k bytes in length and should be wholly contained in one segment (i.e., should not cross a segment boundary).
Segment registers should only contain values supplied by the relocation and linkage facilities. Segment register values may be moved to and from
memory, pushed onto the stack and popped from
the stack. Segment registers should never be used
to hold temporary variables nor should they be
altered in any other way.

Programming Guidelines

As an additional guideline, code should not be
written within six bytes of the end of physical
memory (or the end of the code segment if this
segment is dynamically relocatable). Failure to
observe this guideline could result in an attempted
opcode prefetch from non-existent memory,
hangingthe CPU if READY is not returned.

These guidelines encourage the development of
8086/8088 software that is adaptable to change.
Some of the guidelines refer to specific processor
features and others suggest approaches to general
software design issues. PL/M-86 programmers
need not be concerned with the discussions that
deal with specific hardware topics; they should,
however, give careful attention to. the system
design subjects. Systems that are designed in
accordance with these recommendations
should be less costly to modify or extend. In
addition, they should be better-positioned to

Self-Modifying Code .
It is possible to write a program that deliberately
changes some of its own machine instructions

2-96

8086 AND 8088 CENTRAL PROCESSING UNITS

that reads a disk file, fQr example, should have no
knowledge of where the file is located on the disk,
what size the disk sectors ani, etc. This allows
these characteristics to change without affecting
the application module. To an application
module, the 110 system appears to be a series of
file-oriented commands (e.g., Open, Close, Read,
Write). An application module would typically
issue a command by calling a file system
procedure.

during execution. While this technique may save a
few bytes or machine cycles, it does so at the
expense of program clarity. This is particularly
true if the program is being examined at the
machine instruction level; the machine instructions shown in the assembly listing may not match
those found in memory or monitored from the
bus. It also precludes executing the code from
ROM. Also, because of the pre fetch queue within
the 8086 and 8088, code that is self-modified
within six bytes of the current point of execution
cannot be guaranteed to execute as intended.
(This code may already have been fetched.) Finally, a self-modifying program may prove
incompatible with future Intel products that
assume that the content of a code segment
remains constant during execution;

The file system processes 110 command requests,
perhaps checking for gross errors, and calls a procedure in theIlO supervisor. The I/O supervisor
is a bridge between the functional 110 request of
the application module and the physical 110 performed by the lowest-level modules in the hierarchy. There shouHl be separate modules in the
supervisor for different types of devices and some
device-dependent code may be unavoidable at this
level. The 110 supervisor would typically perform
overhead activities such' as maintaining disk
directories.

A corrollary to this requirement is that variable
data should not be placed in a code segment. Constant data may be written in a code segment, but
this is not recommended for two reasons. First,
programs are simpler to understand if they' are
uniformly subdivided into segments of code, data
and stack. Second, placing data in a code segment
can restrict the segment's position independen~e.
This is because, in general, the segment base
address of a data item may be changed, but the
offset (displacement) of the data item may not.
This means that the entire segment must be
moved as a unit to avoid changing the offset of
the constant data. If the constant data were
located in a data segment or an extra segment,
individual procedures within the code segment
could be moved independently.

The modules that actually c;qmmunicate with the
I/O devices"(or their controllers) are at the lowest
level in the hierarchy. These module$ contain the
bulk of the system's device-dependent code that
will have to be modified in the event that a device
is changed.
The 8089 Input/Output Processor is specifically
designed to encourage' the' development of
modular, hierarchical 110 systems. The 8089
allows knowledge of device c;haracteristics to be
"hidden" from not only .application programs,
but also from the operating system that controls
the CPU. The CPU's 110 supervisor can simply
prepare a message in memory that describes the
nature of the operation to be performed, and then
activate tht; '8089. The 8089 independently performs all physical I/O and notifies the CPU when
the operation has been completed.

Input/Output

Since 110 devices vary so widely in their
capabilities and their interface designs, I/O software is inevitably device dependent. Substituting
a hard disk for a floppy disk, for example,.
necessitates software changes even though the
disks are functionally identical. I/O software \.(~n,
however, be designed to minimize the effect of
device changes on programs.

Operating Systems

Operating systems also shoitld he organized in a
hierarchy similar to the c'oncept· illustrated in
figure 2-69. Application modules should "see"
only the uppedevel of the operating system. This
level might provide services like sendihgmessages
between application modules, 'providing time
delays, etc. An intermediate level might consist of
housekeeping
routines that dispatch. tasks, alter
,
"'.

Figure 2-68 illustrates a design concept that structures an I/O system into a hierarchy of separately
compiled/assembled modules. This approa~h
isolates application modules that. use the
input! output devices from all physical
characteristics of. the hardware with which they
ultimately communicate. An application module

t~.

2-97

8086 AND 8088 CENTRAL PROCESSING UNITS

I

I

APPLICATION
_ _ _-.,._ _.... MODULES

....- . . , . . . - . . , . . . - - , . - - , . . . . - . , . . - . . . , . . . - . . . , 1/0 SUPERVISOR
................1""-......._
....._ _ _'--.,....""'-.,.... . .,...,...,.... MODULES

-,..........,.........,............,.......-r-""-.,...........,..........,.......I-,r--I.I

PHYSICAL 1/0
MODULES

II.

DEVICE CONTROL
THARDWARE

Q

1/0 DEVICES

Figure 2·68. I/O System Hierarchy Concept

APPLICATION MODULES

1 1.. 1___

1..-..._.....

OPERATING SYSTEM

I I

I

1

--~---. - . - , ; ; ; , ; ; , ; ; ; ; ' - . ---;Y;;M-;R~~--------l

I

I I I I I

1 1

I· II

1/0 SUPERVISOR

I

1

.

HOUSEKEEPING

I I

INVISIBLE TO
APPLICATION MODULES

II

PHYSICAL 1/0

I:

·.1·

PRIMITIVE OPERATIONS

I

I

II

Figure 2·69. Operating System Hierarchy
2-98

I

I

8086 AND 8088 CENTRAL PROCESSING UNITS

priorities, manage memory, etc. At the lowest
level would be the modules that implement
primitive operations such as adding and removing
tasks or messages from lists, servicing timer interrupts, etc.

ferent interrupt procedure. When the number of
interrupt sources is not too large, this can be
accomplished by ~.ssigning a different type code
and corresponding service procedure to each
source. In systems where a large number of
similar sources can generate closely spaced interrupts (e.g., 500 communication lines), an
approach similar to that illustrated in figure 2-70,
may be used to insure that the interrupt service
procedure is not reentered, and yet; interrupts
arriving in bursts are not missed. The basic
technique is to divide the code required to service
an interrupt into two parts. The interrupt service
procedure itself is kept as short as possible; it performs the absolute minimum amount of processing necessary to service the device. It then builds a
mcssage that contains enough information to permit another task, the interrupt message processor,
to complete the interrupt service. It adds the
message to a queue (which might be implemented
as a linked list), and terminates so that it is
available to service the next interrupt. The interrupt message processor, which is not reentrant,
obtains a message from the queue, finishes processing the interrupt associated with that message,
obtains the next message (if there is one). etc.
When a burst of interrupts occurs, the queue will
lengthen, but interrupts will not be missed so long
as there is time for the interrupt service procedure
to be activated and run between requests.

Interrupt Service Procedures

Procedures that service external interrupts should
be considered differently than those that service
internal interrupts. A service procedure that is
activated by an internal interrupt, may, and often
should, be made reentrant. External interrupt
procedures, on the other hand, should be viewed
as temporary tasks. In this sense, a task is a single
sequential thread of execution; it should not be
reentered. The processor's response to an external
interrupt may be viewed as the following sequence
of events:
•
•

•
•

the running (active) task is suspended,
a new task, the interrupt service procedure, is
created and becomes the running task,
the interrupt task ends, and is deleted,
.the suspended task is reactived and
becomes the running task from the point
where it was suspended.

An external interrupt procedure should only be
interruptable by a request that activates a dif-

MULTIPLE INTERRUPT SOURCES'

~

INTERRUPT
SERVICE'
PROCEDURE

ADD MESSAGE TO QUEUE

,_1_--,
r----l

r- - - - -l g~~~fJ~WJh
r- - - - -l ~~~~I;~ES
r-----l
L--r_--l

OBTAIN NEXT MESSAGE
FROM QUEUE

INTERRUPT
MESSAGE
PROCESSOR

Figure 2-70. Interrupt Message Processor
2-99

. 8086 AND g088 CENTRAL'PROCESSING UNITS

to. examine the memQry mapped 110 and
interrupt handling examples, since the cQncepts
illustrated are generally applicable; Qne o.f the
interrupt prQcedures is. written in PL/M-S6.

Stack-Based Parameters
.
.
,
Parameters are frequently passed to. prQcedures
Qn a stack. Results prQduced by the prQcedure,
hQwever, shQuld be returned in Qther memQry
IQcatiQns~r in registers. In QtherwQrds, the called
prQcedure .should "clean up" the stack by discarding the parameters befQre returning. The,
RET instruction can perfQrm this functiQn.
PL/M-S6 prQcedures always fQIIQW this
cQnventiQn.

The examples are intended to. sho.w Qne way to. use
the instructiQn set, addressing mQdes and features
Qf ASM-S6. They do. nQt demQnstrate the "best"
way to. sQlve any particular problem. The flexibility of the SOS6 and SOSS, applicatiQn differences
plus variatiQns in prQgramming style usually add
up to. a number Qf ways to. implement a prQgramming so.lutiQn.

Flag-Images
Procedures
PrQgrams shQuld make no. assumptiQns abQut the
CQntents Qf the undefined bits in the flag-images
stQred in memQry by the PUSHF and SAHF
instructiQns. These bits always shQuld be masked
QU,t Qf any cQmparisQns Qr tests that use these
flag-images. The undefined bits Qfthe wQrd flagimage can be cleared by ANDing the wQrd with
FD5H. The undefined bits Qf the byte flag-image
can be cleared by ANDing the byte with D5H.

The cQde in figure 2-71 illustrates several techniques that are typically used in writing ASM-S6
prQcedures. In this example a calling program
invQkes a prQcedure (called EXAMPLE) twice,
passing it a different byte array each time. Two.
parameters are passed o.n the stack; the first CQntains the number Qf elements in the array, and the
secQnd cQntains the address (Qffset in
DAT A_SEG) Qf the first array element. This
same technique can be used to. pass a variablelength parameter list to. a prQcedure (the "array"
CQuid be any series Qf parameters. or parameter
addresses). Thus, althQugh the prQcedure always
receives two. parameters, these can be used to.
indirectly access any number Qf variables in
memQry.

Programming Examples
These examples demQnstrate the SOS6/S0SS
instructiQn set and addressing mQdes in CQmmQn
prQgramming situatiQns. The fQIIQwing tQPics are
addressed:
.

•
•

Any results returned by a prQcedure shQuld be
placed in registers Qr in memQry, but nQt Qn the
stack. AX o.r AL is o.ften used to. ho.ld a single
wQrd Qr byte result. Alternatively, the calling prQgram can pass the address(Qr addresses) Qf a
result area to. the procedure as a parameter. It is
gQQd practice for ASM-S6 prQgrams to. fQIIQW the
calling cQnveritio.ns used by PLlM-S6; these are
dQcumented" in MCS-86 Assembler Operating
Instructions For ISIS-II Users, Order No..
9S00641.

prQcedures (parameters, reentrancy)
variQus fQrms
instructiQns

Qf

JMP

and

CALL

•

bit manipulatiQn with the ASM-S6 RECORD
facility

•
•
•
•

dynamic cQde relQcatiQn

•

string QperatiQns

memQry mapped 1/0
breakpQints
interrupt handling

EXAMPLE is defined as a FAR procedure,
meaning it is in a different segment than the callingprQgram. The calling prQgram must use an
intersegment CALL to. activate the prQcedure.
NQte that this type Qf CALL saves CS and IP Qn
the stack. If EXAMPLE were defined as NEAR
(in the same segment as the caller) then an intrasegment CALL WQuid be used, and Qnly IP WQuid
be saved Qn the stack. It is the resPQnsibility Qf
the calling program to. knQw hQW the procedure is
defi,ned and to. issue the CQrrect type Qf CALL.

These examples are written primarily in ASM-S6
and will be Qf mQst interest to. assembly language
prQgrammers. The PL/M-S6 cQmpiler generates
cQde that handles many Qf these situations
autQmatically fQr PL/M-86 prQgrams. FQr exam"
pIe, the cQmpiler takes care Qf the 'stack in
PL/M-S6 prQcedures, allQwing the.,prQgrammer
to. co.ncentrate Qn sQlving the applicatiQn prQblem. PL/M-S6 prQgrammers, hQwever, may want
Mnemonics © Inlel,1978

2-100

8086 AND 8088 CENTRAL PROCESSING UNITS

STACK_SEG

SEGMENT
OW

20 DUP (?)

; ALLOCATE 20-WORD STACK

WORD

; LABEL INITIAL TOS

STACK_TOP
STACK_SEG

LABEL
ENDS

DATLSEG
ARRAY_1

SEGMENT
10 DUP (?)
DB

ARRAY_2

DB

DATLSEG

ENDS

5 DUP (?)

; 10-ELEMENT BYTE ARRAY
;~ELEMENTBYTEARRAY

PROC_SEG
SEGMENT
ASSUME CS:PROC_SEG,DS:DATA_SEG,SS:STACK_SEG,ES:NOTHING
EXAMPLE

PROC

; MUST BE ACTIVATED BY
INTERSEGMENT CALL

FAR

; PROCEDURE PROLOG
; SAVE BP
PUSH
BP
MOV
BP,SP
; ESTABLISH BASE POINTER
CX
; SAVE CALLER'S
PUSH
BX
REGISTERS
PUSH
;
AND FLAGS
PUSHF
SUB
SP,6
; ALLOCATE 3 WORDS LOCAL STORAGE
; END OF PROLOG
; PROCEDURE BODY
CX, [BP+8]
; GET ELEMENT COUNT
MOV
BX, [BP+6]
; GET OFFSET OF 1ST ELEMENT
MOV
; PROCEDURE CODE GOES HERE
; FIRST PARAMETER CAN BE ADDRESSED:
; [BX]
; LOCAL STORAGE CAN BE ADDRESSED:
;
[BP-8], [BP-10], [BP-12]
; ENDOF PROCEDURE BODY
; PROCEDURE EPILOG
SP,6
ADD
; DE-ALLOCATE LOCAL STORAGE
POPF
; RESTORE CALLER'S
POP
BX
REGISTERS
POP
CX
AND
POP
BP
FLAGS
; END OF EPILOG
; PROCEDURE. RETURN
4
; DISCARD 2 PARAMETERS
RET
EXAMPLE,

; END OF PROCEDURE "EXAMPLE"

ENDP

Figure 2-71. Procedure Example 1
2-101

Mnemonics@ Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

CALLER_SEG
SEGMENT
; GIVE ASSEM BLER SEGMENT I REGISTER CORRESPONDENCE
ASSUME
CS:CALLER_SEG,
&
DS:DATA_SEG,
&
SS:STACK_SEG,
&
ES:NOTHING
; NO EXTRA SEGMENT IN THIS PROGRAM
; INITIALIZE SEGMENT REGISTERS
START:
MOV
AX,DATA_SEG
MOV
DS,AX
MOV
AX,STACK_SEG
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP ; POINT SP TO TOS
; ASSUME ARRAY _1 IS INITIALIZED

,
; CALL "EXAMPLE", PASSING ARRAY_1, THAT IS, THE NUMBER OF ELEMENTS
IN THE ARRAY, AND THE LOCATION OF THE FIRST ELEMENT.
MOV
AX,SIZE ARRAY_1
PUSH
AX
MOV
AX,OFFSET ARRAY_1'
PUSH
AX
CALL
EXAM PLE
; ASSUME ARRAY _21S INITIALIZED

,
; CALL "EXAMPLE" AGAIN WITH DIFFERENT SIZE ARRAY.
AX,SIZE ARRAY_2
MOV
PUSH
AX
MOV
AX,OFFSET ARRAY_2
PUSH
AX
CALL
EXAMPLE
ENDS
END

START

Figure 2-71. Procedure Example 1 (Cont'd.)
Figure 2-72 shows the stack before the caller
pushes the parameters onto it. Figure 2-73 shows
the stack as the procedure receives it after the
CALL has been executed.

it existed when the procedure was activated. This
is done by pushing any registers used by the procedure (only CX and BP in this case) onto the
stack. If the procedure changes the flags, and the
caller expects the flags to be unchanged following
execution of the procedure, they also may be
saved on the stack. The last instruction in the prolog allocates three words on the stack for. the procedure to use as local temporary storage. Figure
2-74 shows the stack at the end of the prolog.
Note that PL/M-86 procedures assume that all
registers except SP and BP can be used without
saving and restoring.

EXAMPLE is divided into four sections. The
"prolog" sets up register BP so it can be used to
address data on the stack (recall that specifying
BP as a base register in an instruction automatically refers to the stack segment unless a segment override prefix is coded). The next step in
the prolog is to save the "state of the machine" as
MnemoniCS © Intel, 1978

2-102

8086 AND 8088 CENTRAL PROCESSING UNITS

I--------~- SP (TOS)
HIGH ADDRESSES

PARAMETER 1
PARAMETER 2
OLDCS
OLD IP
OLD BP

_BP

OLDCX
OLD BX
OLD FLAGS
BP-8_

LOCAL 1

BP-10_

LOCAL2

BP-12_

LOCAL3

_SP(TOS)

LOW ADDRESSES

Figure 2-74. Stack Following Procedure Prolog

Figure 2-72. Stack Before Pushing Parameters

The procedure "body" does the actual processing
(none in the example). The parameters on the
stack are addressed relative to BP. Note that if
EXAMPLE were a NEAR procedure, CS would
not be on the stack and the parameters would be
two bytes "closer" to BP. BP also is used to
address the local variables on the stack. Local
constants are best stored in a data or extra
segment.

HIGH ADDRESSES

PARAMETER 1
PARAMETER 2
OLDCS
OLD IP

_SP(TOS)

The procedure "epilog" reverses the activities of
the prolog, leaving the stack as it was when the
procedure was entered (see figure 2-75).

r

HIGHER ADDRESSES

'P

PARAMETER 1
PARAMETER 2
RETURN ADDRESS
OLD BP

LOW ADDRESSES

"

LOWER ADDRESSES

___ BP & SP (TOS)

'"

Figure 2-75. Stack Following Procedure Epilog

Figure 2-73. Stack at Procedure Entry
2-103

So.S6 ANDSOSS CENTRAL PROCESSING UNITS

Figure 2-79 shows a different approach to using
an ASM-S6 structure to define the stack layout.
As shown in figure 2-S0, register BP is pointed at
the middle of the structure (at OLD_BP) rather
than at the base of the structure. Parameters and
the return address are thus located at positive
displacements (high addresses) from BP, while
local variables are at negative displacements
(lower addresses) from BP. This means that the
local variables will be "closer" to the beginning
of the stack segment and increases the likelihood
that the assembler will be able to produce shorter
instructions to access these variables, i.e., their
offsets from SS may be 255 bytes or less and can
be expressed as a I-byte value rather than a 2-byte
value. Exit from the subroutine also is slightly
faster because a MOV instruction can be used to
deallocate the local storage instead of an ADD
(compare figure 2-71).

The procedure "return" restores CS and IP from
the stack and discards the parameters. As figure
2-76 shows, when the calling program is resumed,
the stack is in the same state as it was before any
parameters were pushed onto it.

...

HIGH ADDRESSES

1----------1- SP (TOS)

It is possible for a procedure to be activated a second time before it has returned from its first
activation. For example, procedure A may call
procedure B, and an interrupt may occur while
procedure B is executing. If the interrupt service
procedure calls B, then procedure B is reentered
and must be written to handle this situation correctly, i.e., the procedure must be made
reentrant.

In PLlM-S6 this can be done by simply writing:
B: PROCEDURE (PARM1, PARM2) REENTRANT;

An ASM-S6 procedure will be reentrant if it uses
the stack for storing all local variables. When the
procedure is reentered, a new "generation" of
variables will be allocated on the stack. The stack
will grow, but the sets of variables (and the
parameters and return addresses as well) will
automatically be kept straight. The stack must be
large enough to accommodate the maximum
"depth" of procedure activation that can occur
under actual running conditions. In addition, any
procedure called by a reentrant procedure: must
itself be reentrant.

LOW ADDRESSES

Figure 2-76. Stack Following Procedure Return

Figure 2-77 shows a simple proc:eg,ure that uses an
ASM-S6 structure to address the stack. Register
BP is pointed to the base of the structure, which is
the top of the.stac:k since the stack grows toward
lower addresses (see figure 2-7S). Any structure
element canthen be addressed by specifying BP.as
a base register:

A related situation that also requires reentrant
procedures is recursion. The following are
examples of recursion:
•
•
•

[BP) .structure--,-element.

Mnem.onics © Intel, 1978

2-104

A calls A (direct recursion),
A calls B, B calls A (indirect recursion),
A calls B, B calls C, C calls A (indirect
recursion).

8086 AND 8088 CENTRAL PROCESSING UNITS

CODE

SEGMENT
ASSUME CS:CODE
MAX
PROC
; THIS PROCEDURE IS CALLED BY THE FOLLOWING
SEQUENCE:
PUSH PARM1
PUSH PARM2
CALL MAX
; IT RETURNS THE MAXIMUM OF THE TWO WORD
PARAMETERS IN AX.

; DEFINE THE STACK LAYOUT
STRUC
OLD~BP
DW?
RETURN_ADDR DW?
PARM_2
DW?
PARM_1
DW?
STACK_LAYOUT ENDS

AS A STRUCTURE.

STACK~LAYOUT

; SAVED BPVALUE-BASEOFSTRUCTURE
; RETURN ADDRESS
; SECOND PARAMETER
; FIRST PARAMETER

; PROLOG
PUSH
MOV

BP
BP, SP

; SAVE IN OLD_BP
; POINT TO OLD_BP

MOV
CMP
JG
MOV

AX, [BP).PARM_1
AX, [BP).PARM_2
FIRST_IS_MAX
AX, [BP).PARM_2

; IF FIRST
; >SECOND
; THEN RETURN FIRST
; ELSE RETURN SECOND

BP

; RESTORE BP (& SP)

4

; DISCARD PARAMETERS

; BODY

; EPILOG
FIRST_IS_MAX: POP
; RETURN
RET
MAX
ENDP
CODE

ENDS
END

Figure 2-77. Procedure Example 2

r

HIGHER ADDRESSES

,

Jumps and Calls
The 8086/8088 instruction set contains many different types of JMP and CALL instructions (e.g.,
direct, indirect. through register, indirect through
memory, etc.). These varying types of transfer
provide efficient use of space and execution time
in different programming situations. Figure 2-81
illustrates typical use of the different forms of
these instructions. Note that the ASM-86
assembler uses the terms "NEAR" and "FAR"
to denote intrasegment and intersegment transfers, respectively.

PARAMETER 1
PARAMETER 2
RETURN ADDRESS
OLDBP

"

_BP&SP(TOS)

h

LOWER ADDRESSES

Figure 2-78. Procedure Example 2 Stack Layout

2-105

Mnemonics © Intel, 1978

8086 AN08088 CENTRAL PROCESSING UNITS

EXTRA
SEGMENT
; CONTAINS STRUCTURE TEMPLATE THAT ','NEARPROC"
;
USES TO ADDRESS AN ARRAY PASSED BV ADDRESS.
DUMMY
STRUC
PARM_ARRAY
DB
256 DUP?
DUMMY
ENDS
EXTRA
ENDS
CODE

SEGMENT
ASSUME CS:COQE,ES:EXTRA
..
NEARPROC
PROC
" "
; LAY OUTTHE STACK (THE l;)yNAMICSTORAGE AREA OR DSA).
STRUC'
DSASTRUC
?
I
OW
; LOCAL VARIABLES FIRST
DUP (?) .
,
LOC_ARRA Y
DW
?:
OLD_BP
OW
; ORIG INAL BP VALU E
?
RETADDR
DW
; RETURN ADDRESS
?
POINTER
DD
; 2ND PARM-POINTERTO "PARM_ARRAY"
DB
?
COUNT
; 1ST PARM-A BYTE OCCUPIES
?
DB.
A WORD ON THE STACK
DSASTRUC
ENDS

10

; USE AN EQU TO DEFINE THE BASEtADDRESS OF THE
DSA. CANNOT SIMPLY USE BP BECA!)SI:IT WILL
BE POINTING TO ~'OLD~BP~'.IN HIE MIDDLE OF
;
THE DSA:
EQU[BP -OFFSET OLD_BP]
DSA
; PROCEDURE ENTRY
PUSH
MOV
SUB

BP
; SAVE BP
BP, SP
; POI NT BP AT OLD_BP
SP, OFFSETOLD_BP; ALLOCATE LOC_ARRAY & I

; PROCEDURE BODY
; ACCESS LOCAL VARIABLE I
MOV'
. ~X,DSA.I
; ACCESS LOCAL ARRAY (3) I.E., 4TH ELEMENT .
MOV
SI,6
; WORD ARRAY-INDEX IS 3*2
MOV
AX,DSA.LOC_ARRAY [SI]
; LOAD POINTERTOARRAY PASSED BY ADDRESS
LES
'BX,DSA.POINTER
; ES:BX NOW POIN:rS TO PARM_ARRAY (0)
; ACCESS SI'TH ELEMENT OF PARM_ARRAY
MOV
AL,ES:[BX].PARM_ARRAY [51]
; ACCESS THE BYTE PARAMETER
MOV
AL,DSA.COUNT

Figure 2"79. Procedure Example 3
Mnemonics © Int~l, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

; PROCEDURE EXIT
; DE-ALLOCATE LOCALS
MOV
SP,BP
POP
BP
; RESTORE BP
; STACK NOW AS RECEIVED FROM CALLER
RET
6
; DISCARD PARAMETERS
ENDP
ENDS
END

NEARPROC
CODE

Figure 2-79. Procedure Example 3 (Cont'd.)

,

HIGHER ADDRESSES

I

,

. The procedure in figure 2-81 illustrates how a
PLlM-86 DO CASE construction may be
implemented in ASM-86. It also shows:

COUNT

-POINTER

•

an indirect CALL through memory to a
procedure located in another segment,

•

a direct JMP to a label in another segment,

•

an indirect JMP though memory to a label in
the same segment,

•

an indirect JMP through a register to a label
in the same segment,

•

a direct CALL to a procedure in another
segment,

•

a direct CALL to a procedure in the same
segment,

•

direct JMPs to labels in the same segment,
within -128 to +127 bytes ("SHORT") and
farther than -128 to +127 bytes ("NEAR").

RETADDR
_BP

OLD_BP
LOC_ARRAY (9)
LOC_ARRAY (8)
LOC_ARRAY (7)
LOC_ARRAY (6)
LOC_ARRAY (5)
LOC_ARRAY (4)
LOC_ARRAY (3)
LOC_ARRAY (2)
LOC~ARRAY

(1)

LOC_ARRAY (0)
I

"

LOWER ADDRESSES

_SP

"

Figure 2-80. Procedure Example
3 Stack Layout
2-107

Mnemonics @ Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

DATA
SEGMENT
; DEFINE THE CASE TABLE (JUMP TABLE) USED BY PROCEDURE
"DO_CASE." THE OFFSET OF EACH LABEL WILL
;
BE PLACED IN THE TABLE BY THE ASSEMBLER.
CASE_TABLE
OW
ACTIO NO, ACTION1 , ACTION2,
&
ACTION3, ACTION4, ACTION5
DATA
ENDS
; DEFINE TWO EXTERNAL (NOT PRESENT IN THIS
ASSEMBLY BUT SUPPLIED BY R & L FACILITY)
PROCEDURES. ONE IS IN THIS CODE SEGMENT
(NEAR) AND ONE IS IN ANOTHER SEGMENT (FAR).
NEAR_PROC: NEAR, FAR_PRoe: FAR
EXTRN
; DEFINE AN EXTERNAL LABEL (JUMP TARGET) THAT
IS IN ANOTHER SEGMENT.
ERR_EXIT: FAR
EXTRN
CODE

SEGMENT
ASSUME
CS: CODE, OS: DATA
; ASSUME DS HAS BEEN SETUP
BY CALLER TO POINTTO "DATA" SEGMENT.
DO_CASE
PROC
NEAR
; THIS EXAMPLE PROCEDURE RECEIVES TWO
PARAMETERS ON THE STACK. THE FIRST
PARAMETER IS THE "CASE NUMBER" OF
A ROUTINE TO BE EXECUTED (0-5). THE SECOND
PARAMETER IS A POINTER TO AN ERROR
PROCEDURE THAT IS EXECUTED IF AN INVALID
CASE NUMBER (>5) IS RECEIVED.
; LAY OUT THE STACK.
STACK_LAYOUT STRUC
OLD_BP
DW?
RETADDR
DW?
ERR_PROC_ADDR DD
CASE_NO
DB?
DB
?
STACK_LAYOUT ENDS

?

; SET UP PARAMETER ADDRESSING
BP
PUSH
MOV
BP,SP
; CODE TO SAVE CALLER'S REGISTERS COULD GO HERE.
; CHECK THE CASE NUMBER
MOV
MOV
CMP
JLE

BH,O
BL, [BPj.CASE_NO
BX, LENGTH CASE_TABLE
OK
; ALL CONDITIONAL JUMPS
; ARE SHORT DIRECT

Figure 2-81. JMP and CALL Examples
Mnemonics © Intel, 1978

2-108

8086ANO 8088 CENTRAL PROCESSING UNITS

; CALL THE ERROR ROUTINE WITH A FAR
INDIRECT CALL. AFAR INDIRECT CALL
IS INDICATED SINCE THE OPERAND HAS
TYPE "DOUBLEWORD."
CALL.
[BP].ERR_PROC_ADDR
; JUMP DIRECTLY TO A LABEL IN ANOTHER SEGMENT.
A FAR DIRECTJUMP IS INDICATED SINCE
THE OPERAND HAS TYPE "FAR."
JMP
ERR_EXIT

OK:
; MULTIPLY CASE NUMBEfi BY 2 TO Ge;T OFFSET
INTO CASE_TABLE (EACH ENTRY IS 2 BYTES).·
SHL
BX,1
; NEAR INDIRECT JUMP THROUGH SELECTED
ELEMENT OF CASE_TABLE. A NEAR
INDIRECT JUMP IS INDICATED SINCE THE
OPERAND HAS TYPE ~IWORD."
JMP
CASE_TABLE [BX]
ACTIONO:'
; EXECUTED IF CASE_NO = 0
; CODE TO PROCESS THE ZERO CASE GOES HERE.
; FOR ILLUSTRATION PURPOSES, USE A
NEAR INDIRECT JUMP THROUGH A
REGISTER TO BRANCH. TO THE POINT
WHERE ALL CASES CONVERGE.
A DIRECT JUMP (JMP ENDCASE) IS
ACTUALLY MORE APPROPRIATE HERE.
MOV
AX, OFFSET ENDCASE
JMP
AX
ACTION1:
; EXECUTED IF CASE_NO = 1
; CALL A FAR EXTERNAL PROCEDURE. A FAR
DIRECT CALL IS INDICATED SINCE OPERAND
HAS TYPE "FAR."
CALL.
FAR_PROC
; CALL A NEAR EXTERNAL PROCEDURE.
CALL
NEAR_PROC
; BRANCH TO CONVER~ENCE POINT USiNG NEAR
.'
DIRECT JUMP. NOTE THAT "ENDCASE"
IS MORE THAN127 BYTES AWAY
SO A NEAR DIRECT JUMP WILL BE USED.
JMP
ENDCASE
; EXECUTED IF CASE_NO = 2
ACTION2:
; CODE GOES HERE
JMP
ENDCASE; NEAR DIRECT JUMP

Figure 2-&1. JMP and CALL Examples (Cont'd.)
2-109

Mnemonics © Inlel,1978

15086 AND 8088 CENTRALPROCESSLNrGUNIIS .
ACTION3:
; EXECUTED IF CASE_NO = 3
; CODE GOES HERE
ENDCASE; NEAR DIRECT JMP
JMP
; ARTIFICIALLY FORCE "ENDCASE" FURTHER AWAy ... ~
SO THAT ABOVE JUMPSGANNQ'r BE'!SHORT.'?·
500
ORG
ACTION4:
; EXECUTED IF CASE_NO = 4
; CODE GOES HERE
JMP
ENDCAsE; NEARl::ilRECT JUMP
ACTION5:
; EXECUTED IFCASE_NO = 5
; CODE GOES HERE.
; BRANCH TO CONVERGENCE POINT USING
SHORT DIRECNUMP SINCE TARGET IS
WITHIN 127 BYTES. MACHINE INSTRUCTION
HAS 1-BYTE DISPLACEMENT RATHER THAN
2-BYTE DISPLACEMENT REQUIRED FoA
NEAR DIRECT JUMPS. "SHORT" IS
WRITTEN BECAUSE "ENDCASE" ISA FORWAR't>
REFERENCE, WHICH ASS'EMBLER ASSUMESTS
"NEAR." IF "ENOCASF'APPEARED PRIOR
TO THE JUMP, THE ASSEMBLER WOULD
AUTOMATICALLY DETERMINE IF ITWERE REACHABLE
WITH A SHORT JUMP.
JMP
SHORTENDCASE
ENDCASE:

;ALLCASESCONVERGEHER~

; POP CALLER'S REGISTERS HERE.
; RESTORE BP & SP, DISCARD pARAMETERS
AND RETURN TO CALLER.
MOV
SP, BP
POP
BP
RET
6
i

'ENDP
ENDS
END

; OF ASSEMBLY

Figure 2~81. JMPand CALL Examples (C?Dt'd.)

Records
Figure 2-82 shows how the ASM-86 RECORD
facility may be used to manipulate bit data. The
example shows how to:
•
,-

•
•
•

right-justify a bit field,
test for a value,

MnEl1T1onics © Intel. 1978

2-110

assign a constant known at assembly time,
assign a variable,
set or clear. a bit:field.

8086 AND 8088 CENTRAL PROCESSING UNITS

DATA
SEGMENT
; DEFIN E A WORD ARRAY
XREF
DW 3000 DUP (?)
; EACH ELEMENT OF XREF CONSISTS OF 3 FIELDS:
A 2-BIT TYPE CODE,
A 1-BIT FLAG,
A 13-BIT NUMBER.
; DEFINE A RECORD TO LAY OUT THIS ORGANIZATION.
L1NE_REC
RECORD
LINE_TYPE: 2,
&
VISIBLE: 1,
&
L1NE_NUM: 13
DATA
ENDS
CODE

SEGMENT
ASSUME CS: CODE, DS: DATA
; ASSUME SEGMENT REGISTERS ARE SET UP PROPERLY
AND THAT SIINDEXES AN ELEMENT OF XREF.

; A RECORD FIELD-NAME USED BY ITSELF RETURNS
THE SHIFT COUNT REQUIRED TO RIGHT-JUSTIFY
; THE FIELD. ISOLATE "LINE_TYPE" IN THIS
; MANNER.
MOV
AL, XREF [SI]
MOV
CL, LINE_TYPE
SHR
AX,CL
; THE "MASK" OPERATOR APPLIED TO A RECORD
FIELD-NAME RETURNS THE BIT MASK
REQUIRED TO ISOLATE THE FIELD WITHIN
THE RECORD. CLEAR ALL BITS EXCEPT
"L1NE_NUM. "
MOV
DX, XREF[SI]
AND
DX, MASK L1NE_NUM
; DETERMINE THE VALUE OF THE "VISIBLE" FIELD
TEST
XREF[SI], MASK VISIBLE
NOT_VISIBLE
JZ
; NO JUMP IF VISIBLE = 1
NOT_VISIBLE:
; JUMP HERE IF VISIBLE = 0
; ASSIGN A CONSTANT KNOWN AT ASSEMBLY-TIME
TO A FIELD, BY FIRST CLEARING THE BITS
AND THEN OR'ING IN THE VALUE. IN
THIS CASE "LINE_TYPE" IS SET TO 2 (10B).
AND
XREF[SI], NOT MASK LINE_TYpE
OR
XREF[SI],2 SHL LINE_TYPE
; THE ASSEMBLER DOES THE MASKING AND SHIFTING.
; THE RESULT IS THE SAME AS:
AND
XREF[SI],3FFFH
OR
XREF[SIJ, 8000H
BUT IS MORE READABLE AND LESS SUBJECT
TO CLERICAL ERROR..

Figure 2-82. RECORD Example

2-111

Mnemonics © 'Intel, 11178 '

8086 AND 8088 CENTRAL PROCESSING UNITS

; ASSIGN A VARIABLE (THE CONTENT OF AX)
TO LINE_TYPE.
MOV
CL, LINE_TYPE ; SHIFT COUNT
SHL
AX, CL ; SHIFTTO "LINE UP" BITS
AND
XREF[SIJ, NOT MASK LINE_TYPE ; CLEAR BITS
OR
XREF[SIJ, AX ; OR IN NEW VALUE
; NO SHIFT IS REQUIRED TO ASSIGN TO THE
RIGHT-MOST FIELD. ASSUMING AX CONTAINS
A VALID NUMBER (HIGH 3 BITS ARE 0),
ASSIGN AX TO "LlNE_NUM."
AND
XREF[SIJ, NOT MASK LlNE_NUM
OR
XREF[SIJ, AX
; A FIELD MAY BE SET OR CLEARED WITH
ONE INSTRUCTION. CLEAR THE "VISIBLE"
FLAG AND THEN SET IT.
AND
XREF[SIJ, NOT MASK VISIBLE
XREF[SIJ, MASK VISIBLE
OR
CODE

ENDS
END

; OF ASSEMBLY

Figure 2-82. RECORD Example (Cont'd.)
The following considerations apply to positionindependent code sequences:
•
•

•

•

•

A label that is referenced by a direct FAR
(inter segment) transfer is not moveable.
A label that is referenced by an indirect
transfer (either NEAR or FAR) is moveable
so long as the register or memory pointer to
the label contains the label's current address.
A label that is referenced by a SHORT (e.g.,
conditional jump) or a direct NEAR (intrasegment) transfer is moveable so long as
the referencing instruction is moved with the
label as a unit. These transfers are selfrelative; that is they require only that the
label maintain the same distance from the
referencing instruction, and actual addresses
are immaterial.
Data is segment-independent, but not offsetindependent. That is, a data item may be
moved to a different segment, but it must
maintain the same offset from the beginning
of the segment. Placing constants in a unit
of code also effectively makes the code
offset-dependent, and therefore is not
recommended.
A procedure should not be moved while it is
active or while any procedure it has called is
active.

Mnemonics © Intel, 1978 .

2-112

•

A section of code that has been interrupted
should not be moved.

The segment that is receiving a section of code
must have "room" for the code. If the MOVS (or
MOVSB or MOVSW) instruction attempts to
auto-increment DI past 64k, it wraps around to 0
and causes the beginning of the segment to be
overwritten. If a segment override is needed for
the source operand, code similar to the following
can be used to properly resume the instruction if it
is interrupted:

RESUME:

REP

MOVS

DESTINATION, ES:SOURCE

;IF CXNOT ~ 0 THEN INTERRUPT HAS OCCURRED
AND

CX,CX

JNZ

RESUME

; CX~O?
;NO, FINISH EXECUTION

;CONTROL COMES HERE WHEN STRING HAS BEEN MOVED.

the MOVS is interrupted, the CPU
"remembers" the segment override, but
"forgets" the presence of the REP prefix when
execution resumes. Testing CX indicates whether
the instruction is completed or not. Jumping back
to the instruction resumes it where it left off. Note
that a segment override cannot be specified with
MOVSB or MOVSW.
If

8086 AND 8088 CENTRAL PROCESSING UNITS

Dynamic Code Relocation

calls the procedure through this pointer. The
supervisor also has access to the procedure's
length in bytes. The procedure is moved with the
MOVSB instruction. After the procedure is
moved, its pointer is updated with the new location. The ASM-86 WORD PTR operator is written to inform the assembler that one word of the
doubleword pointer is being updated at a time.

Figure 2-83 illustrates one approach to moving
programs in memory at execution time. A "supervisor" program (which is not moved) keeps
a pointer variable that contains the current location (offset and segment base) of a positionindependent procedure. The supervisor always

MAIN_DATA
SEGMENT
; SET UP POINTERS TO POSITION-INDEPENDENT PROCEDURE
AND FREE SPACE.
PIP _PTR
DO
EXAMPLE
FREE_PTR
DO
TARGET_SEG
; SET UP SIZE OF PROCEDURE IN BYTES
PIP_SIZE
OW
EXAMPLE_LEN
MAIN_DATA
ENDS
STACK

STACK_TOP
STACK

SEGMENT
OW
20 DUP (?)
LABEL
ENDS

WORD

; 20 WORDS FOR STACK
; TOS BEGINS HERE

SOURCE_SEG
SEGMENT
; THE POSITION-INDEPENDENT PROCEDURE IS INITIALLY IN THIS SEGMENT.
; OTHER CODE MAY PRECEDE IT, I.E., ITS OFFSET NEED NOT BE ZERO.
ASSUME
CS:SOURCE_SEG
EXAMPLE
PROC
FAR
; THIS PROCEDURE READS AN 8-BIT PORT UNTIL
; BIT 3 OF THE VALUE READ IS FOUND SET. IT
; THEN READS ANOTHER PORT. IF THE VALUE READ
; IS GREATER THAN 10H IT WRITES THE VALUE TO
; A THIRD PORT AND RETURNS; OTHERWISE IT STARTS
; OVER.
STATUS_PORT EQU
ODOH
PORT_READY
EQU
008H
INPUT_PORT
EQU
OD2H
THRESHOLD
EQU
010H
OUTPUT_PORT EQU
OD4H
AL,STATUS_PORT
; GET STATUS
CHECK_AGAIN: IN
AL,PORT_READY
TEST
; DATA READY?
CHECK_AGAIN
JNE
; NO, TRY AGAIN
AL,INPUT_PORT
IN
; YES, GET DATA
CMP
AL,THRESHOLD
; > 10H?
CHECK_AGAIN
JLE
; NO, TRY AGAIN
OUT
OUTPUT_PORT ,AL ; YES, WRITE IT

Figure 2-83. Dynamic Code Relocation Example
2-113

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

RET
;GETPROCEDURELENGTH
EXAMPLE_LEN EQU
ENDP
SOURCE_SEG
ENDS

; RETURN TO CALLER
(OFFSET THIS BYTE)-(OFFSETCHECK_AGAIN)
EXAMPLE ENDP

TARGET_SEG
SEGMENT
; THE POSITION-INDEPENDENT PROCEDURE
IS MOVED TO THIS SEGMENT, WHICH IS
;
INITIALLY "EMPTY."
; IN TYPICAL SYSTEMS, A "FREE SPACE MANAGER" WOULD
; MAINTAIN A POOL OF AVAILABLE MEMORY SPACE
; FOR ILLUSTRATION PURPOSES, ALLOCATE ENOUGH
SPACE TO HOLD IT
DB
EXAMPLE_LEN DUP (?)
TARGET_SEG

ENDS

MAIN_CODE
SEGMENT
; THIS ROUTINE CALLS THE EXAMPLE PROCEDURE
; AT ITS INITIAL LOCATION, MOVES IT, AND
; CALLS IT AGAIN ATTHE NEW LOCATION.
ASSUME
&

CS:MAIN_CODE,SS:STACK,
DS:MAIN_DATA,ES:NOTHING

; INITIALIZE SEGMENT REGISTERS & STACK POINTER.
AX,MAIN_DATA
START:
MOV
MOV
DS,AX
MOV
AX,STACK
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP
; CALL EXAMPLE AT INITIAL LOCATION.
CALL
PIP_PTA
; SET UP CX WITH COUNT OF BYTES TO MOV
MOV
CX,PIP _SIZE
; SAVE DS, SET UP DS/SI AND ES/DI TO
POINT TO THE SOU RCE AN D DESTINATION
ADDRESSES.
PUSH
DS
DI,FREE_PTR
LES
SI,PIP_PTR
LDS
; MOVE THE PROCEDURE.
CLD
REP MOVSB

; AUTO INCREMENT

; RESTORE OLD ADDRESSABILITY.
; HOLD TEMPORARILY
MOV
AX,DS
DS
POP
; UPDATE POINTER TO POSITION-INDEPENDENT PROCEDURE
MOV
WORD PTR PIP _PTR+2,ES
SUB
DI,PIP _SIZE
; PRODUCES OFFSET
MOV
WORD PTR PIP_PTR,DI

Figure 2-83. Dynamic Code Relocation Example (Cont'd.)
Mnemonics © Intel, 1978

2-114

80.86 AND 8088 CENTRAL.PROCESSINGUNITS

; UPDATE POINTER TO FREESPACE
MOV
. WORD PTR FREE_PTR+2,AX
SUB
SI,PIP _SIZE
; PRODUCES OFFSET
,MOV
WORD PTR FREE_PTR,SI
; CALL POSITION-INDEPENDENT PROCEDURE AT
NEW LOCATION AND STOP
CALL
PIP_PTR
MAIN_CODE
ENDS
END
START

Figure 2-83. Dynamic Code Relocation Example (Cont'd.)

Memory-Mapped I/O

instruction transfers characters to successive
memory addresses, the decoding logic must select
the line printer if any of these locations is written.
One way of accomplishing this is to have the chip
select logic decode only the upper 12 lines of the
address bus (AI9-A8), ignoring the contents of
the lower eight lines (A7-AO). When data is written to any address in this 256-byte block, the
upper 12 lines will not change, so the printer will
be selected.

Figure 2-84 shows how memory-mapped 110 can
be used to address a group of communication
lines as an "array." In the example, indexed
addressing is used to poll the array of status ports,
one port at a time. Any of the other 8086/8088
memory addressing modes may be used in conjunction with memory-mapped 1/0 devices as
well.
In figur\: 2-85 a MOVS instruction is used to perform a high-speed transfer to.a memory-mapped
line printer. Using this technique requires the
hardware to be set up as follows. Since the MOVS

If an 8086 is being used with an 8-oit printer, the

8086's 16-bit data bus must be mapped into 8-bits
by external hardware. Using an 8088 provides a
more direct interface.

COM_LINES
SEGMENT AT 800H
; THE FOLLOWING IS A MEMORY MAPPED "ARRAY"
OF EIGHT 8-BIT COMMUNICATIONS CONTROLLERS
(E.G.,8251 USARTS). PORTS HAVE ALL-ODD
OR ALL-EVEN ADDRESSES (EVERY OTHER BYTE
IS SKIPPED) FOR 8086-COMPATIBILITY.
COM_DATA
COM_STATUS

COM_LINES

DB
DB
DB
DB
DB
ENDS

?
?
?
?
28

; SKIP THIS ADDRESS

DUP(?)

; SKIP THIS ADDRESS
; REST OF "ARRAY'.'

SEGMENT
CODE
; ASSUME STACK IS SET UP, AS ARE SEGMENT
REGISTERS (DS POINTING TO COM_LINES).
FOLLOWING CODE POLLS THE LINES. '
CHAR_RDY
START_POLL:

EaU
MOV
SUB

00000010B
CX,8
SI,SI

; CHARACTER PRESENT
; POLL 8 LINES ZERO
; ARRAY INDEX

Figure 2-84. Memory Mapped 1/0 "Array"
2-115

Mnemonics © Intel, 1978

808SANO 8088 CENTRAL PROCESSING UNITS

POLL_NEXT:

READ_CHAR:
; ETC.
CODE

JMP

COM_STATUS [SI], CHAR_RDY
READ_CHAR; READ IF PRESENT
; ELSE BUMP TO NEXT LINE
SI,.4
POLL_NEXT ; CONTINUE POLLING UNTIL
;
ALL 8 HAVE BEEN CHECKED
START_POLL; STARTOVER

MOV

AL,COM_DATA [SI]

TEST
JE
ADD
LOOP

;GETTHE DATA

ENDS
END

Figure 2-84. Memory Mapped I/O "Array" (Cont'd.)

PRINTER
SEGMENT
; THIS SEGMENT CONTAINS A "STRING" THAT
IS ACTUALLY A MEMORY-MAPPED LINE PRINTER.
THE SEGMENT (PRINTER) MUST BE ASSIGNED (LOCATED)
TO A BLOCK OF THE ADDRESS SPACE SUCH
THATWRITING TO ANY ADDRESS IN THE
BLOCK SELECTS THE PRINTER.
PRINT_SELECT
PRINTER

DB 133
DB123
ENDS

DUP (?)
DUP(?)

DATA
SEGMENT
DB 133
DUP (?)
PRINT_BUF
PRINT_COUNT DB1
?
; OTHER PROGRAM DATA
ENDS
DATA

; "STRING" REPRESENTING PRINTER
; REST OF 256-BYTE BLOCK

; LINE TO BE PRINTED
; LINE LENGTH

CODE
SEGMENT
; ASSUME STACK AND SEGMENT REGISTERS HAVE
BEEN SET UP (DS POINTS TO DATA SEGMENT).
FOLLOWING CODE TRANSFERS A LINE TO
THE PRINTER.

REP
CODE

ASSUME
MOV
MOV
SUB
SUB
MOV
CLD
MOVS
; ETC.
ENDS
END

ES: PRINTER
AX, PRINTER
; PREVENT SEGMENT OVERRIDE
ES,AX
DI, DI
; CLEAR SOURCE AND
SI, SI
DESTINATION POINTERS
CX, PRINT_COUNT
; AUTO-INCREMENT
PRINT_SELECT, PRINT_BUF

Figure 2-85. Memory Mapped Block Transfer Example
Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

that saves the byte located at that address and
replaces it with an INT 3 (breakpoint) instruction.
When the CPU encounters the breakpoint
instruction, it calls the type 3 interrupt procedure.
In the example, this procedure places the processor into single-step mode starting with the
instruction where the breakpoint was placed.

Breakpoints

Figure 2-86 illustrates how a program may set a
breakpoint. In the example, the breakpoint
routine puts the processor into single-step mode,
but the same general approach could be used for
other purposes as well. A program passes the
address where the break is to occur to a procedure

INT_PTR_TAB SEGMENT
; INTERRUPT POINTER TABLE-LOCATE ATOH
DO
?
TYPE_O
TYPE_1
DO
SINGLE_STEP
TYPE_2
DO
?
TYPE_3
DO
BREAKPOINT
INT_PTR_TAB ENDS
SAVE_SEG
SAVE_INSTR

SEGMENT
DB 1

SAVE_SEG

ENDS

DUP (?)

; NOT DEFINED IN EXAMPLE
; NOT DEFINED IN EXAMPLE

; INSTRUCTION REPLACED
; BY BREAKPOINT

MAIN_CODE
SEGMENT
; ASSUME STACK AND SEGMENT REGISTERS ARE SET UP.
; ENABLE SINGLE-STEPPING WITH INSTRUCTION AT
LABEL "NEXT" BY PASSING SEGMENT AND
OFFSET OF "NEXT" TO "SET_BREAK" PROCEDURE
CS
PUSH
LEA
AX,CS:NEXT
PUSH
AX
CALL
FAR SET_BREAK
; ETC.
NEXT:

IN
; ETC.

AL,OFFFH

; BREAKPOINT SET HERE

ENDS
BREAK
SEGMENT
SET_BREAK
PROC
FAR
; THIS PROCEDURE SAVES AN INSTRUCTION BYTE (WHOSE
ADDRESS IS PASSED BY THE CALLER) AND WRITES
AN INT 3 (BREAKPOINT) MACHINE INSTRUCTION
AT THE TARGET ADDRESS.
TARGET

EQU

DWORD PTR [BP + 6]

Figure 2-86. Breakpoint Example
2-117

Mnemonics © Intel, 1978

8086 AND 8.088 CENTRAL PROCESSING UNITS

; S~T UP BP FOR PARM ADDRESSING & SAVE REGISTERS
PUSH
BP
MOV
BP,SP
PUSH
DS
PUSH
ES
PUSH
AX
PUSH
BX
; POINT DS/BX TO THE TARGET INSTRUCTION
BX,TARGET
LDS
; POINT ES TO THE SAVE AREA
MOV
AX, SAVE_SEG
MOV
ES, AX
; SWAP THE TARGET INSTRUCTION FOR INT 3 (OCCH)
MOV
AL,OCCH
XCHG
AL, DS: [BX)
; SAVE THE TARGET INSTRUCTION
MOV
ES: SAVE_INSTR, AL
; RESTORE AND RETURN
POP
BX
POP
AX
POP
ES
POP
DS
POP
BP
RET
4
SET_BREAK
ENDP
BREAKPOINT
PROC
FAR ..... .
; THE CPU WILL ACTIVATE THIS PROCEDURE WHEN IT
EXECUTES THE INT 3 INSTRUCTION SET BY THE
SET_BREAK PROCEDURE. tHIS PROCEDURE
RESTORES THE SAVED INSTRUCTION BYTE TO ITS
ORIGINAL LOCATION AND BACKS UP THE
INSTRUCTION POINTER IMAGE ON THE STACK
SO THAT EXECUTION WILL RESUME WITH
THE RESTORED INSTRUCTION. IT THEN SETS
TF (THE TRAP FLAG) IN THE FLAG-IMAGE
ON THE STACK. THIS PUTS THE PROCESSOR
IN SINGLE-STEP MODE WHEN EXECUTION
RESUMES.
FLAG_IMAGE
EQU
WORD PTR [BP+6)
IP _IMAGE
EQU
WORD PTR [BP + 2)
NEXT_INSTR
EQU
DWORD PTR [BP+2)
; SET UP BP TO ADDRESS STACK AND SAVE REGISTERS
BP
PUSH
MOV
BP, SP
PUSH
DS
PUSH
ES
PUSH
AX
PUSH
BX
; POINT ES AT THE SAVE AREA
MOV
AX, SAVE_SEG
MOV
ES, AX
; GET THE SAVED BYTE
MOV
AL, ES: SAVE_INSTR

Figure 2-86. Breakpoint Example (Cont'd.)
Mnemonics © Intel, 1978

2-118

8086 AND 8088 CENTRAL PROCESSING UNITS

; GET THE ADDRESS OF THE TARGET + 1
(INSTRUCTION FOLLOWING THE BREAKPOINT)
BX, NEXT_INSTR
LDS
; BACK UP IP-IMAGE (IN BX) AND REPLACE ON STACK
BX
DEC
MOV
IP_IMAGE, BX
; RESTORE THE SAVED INSTRUCTION
MOV
DS: [BX], AL
; SET TF ON STACK
AND
FLAG_IMAGE,0100H
; RESTORE EVERYTHING AND EXIT
BX
POP
POP
AX
POP
ES
POP
DS
POP
BP
IRET
ENDP
BREAKPOINT
SINGLE STEP
PROC
FAR
; ONCE SINGLE-STEP MODE HAS BEEN ENTERED,
THE CPU "TRAPS" TO THIS PROCEDURE
AFTER EVERY INSTRUCTION THAT IS NOT IN
AN INTERRUPT PROCEDURE. IN THE CASE
OF THIS EXAMPLE, THIS PROCEDURE WILL
BE ExeCUTED IMMEDIATELY FOLLOWING THE
"IN AL, OFFFH" INSTRUCTION (WHERE THE
BREAKPOINT WAS SET) AND AFTER EVERY
SUBSEQUENT INSTRUCTION. THE PROCEDURE
COULD "TURN ITSELF OFF" BY CLEARING
TF ON THE STACK.
; SINGLE-STEP CODE GOES HERE.
; SINGLE_STEP ENDP
BREAK

ENDS
END

Figure 2-86. Breakpoint Example (Cont'd.)

In this· hypothetical system, an 8253· Programmable Interval Timer is used to generate ·.a time
base. One of the three timers on the 825Hs programmed to repeatedly generate . interrupt
requests at 50 millisecond intervals. The output
from this timer is tied to one of the eight interrupt
request lines of an 8259A Programmable lnterrupt Controller. The 8259A, in turn, is connected
to the INTR line of an 8086 or 8088.

Interrupt Procedures

Figure 2-87· is a block diagram of Ii hypothetical
system that is used to illustrate three different
examples of interrupt handling: an external
(maskable) interrupt, an external non-mask able
interrupt and a software interrupt.
2-119

Mnemonics © Intel, 1978

8086AN08088 CENTRAL PROCESSING UNITS

COLD START-1

T

r~
~

r-J--

+5V
BATTERY

BATTERY
POWERED
RAM

POWER DOWN
CIRCUITS
MPRO

RESET

IE1

I'

DECODER

PF1

t
(PULSE)

PFS

~

I

NMI

EO
INTR

IR3

8086/8085

!

DATA BUS
CONTROL BUS

I

I

!

I

I

1

I

I

-

CS

DECODER

CTR1
8253

8259A

I I I

ADDRESS BUS

PFSR

T

II

EPROM

!

! I

I

I

DECODER'

I I

I

!

I

I

! I

I

! I

I

S

1.11

l-

I

PORTS

I I I

I

E2

CS

RAM

I

Figure 2-87. InterruptExample Block Diagram

A power-down circuit is used in the system to
illustrate one application of the 8086/8088 NMI
(non-mask able interrupt) line. If the ac line
voltage drops below a certain threshold, the
power supply activates ACLO. The power-down
circuit then sends a power-fail interrupt (PFI)
pulse to the CPU's NMI input. After 5
milliseconds, the power-down circuit activates
MPRO (memory protect) to disable reading
from and writing to the system's battery-powered
RAM. This protects the RAM from fluctuations
that may occur when. power is actually lost 7.5
milliseconds :.after the power failure is detected.
The system software must save all vital information in the batiery-poweredRAM segment within
5 milliseconds oHhe activatiol}:;of NMI. .

connected to the low-order bit of port EO, identifies the source of the RESET. If the bit is set, the
software executes a "warm start" to restore the
information saved by the power-fail routine. If
the PFS bit is cleared, the software executes a
"cold start" from the beginning of the program.
In either case, the software writes a "one" to the
low-order bit of port E2. This line is connected to
the power-down circuit's PFSR (power fail status
reset) signal and is used to enable the batterypowered RAM segment.
A software interrupt is used to update a simple
real-time clock. This procedure is written in
PLlM-86, while the rest of the system is written in
ASM-86 to demonstrate the interrupt handling
capability of bOth languages. The system's main
program simply initializes, .the system following
teceipt of a RESET and then waits for an
interrupt. An example of this interrupt procedure
is given in figure 2-88 ..

When power returns, the power-down circ.uit
activates the system RESET line. Pressing the
'''coldstart'' '. switch alsop.roduces a system
RESET. The PFS.(powerfail status) line;whictJ: is

2-f20

8086 AND 8088 CENTRAL PROCESSING UNITS

INT_POINTERS
SEGMENT
; INTERRUPT POINTER TABLE, LOCATE AT OH, ROM-BASED
TYPE_O
DD
?
; DIVIDE-ERROR NOT SUPPLIED IN EXAMPLE.
TYPE_1
DD
?
; SINGLE-STEP NOT SUPPLIED IN EXAMPLE.
TYPE_2
DD
POWER_FAIL
; NON-MASKABLE INTERRUPT
TYPE_3
DD
?
; BREAKPOINT NOT SUPPLIED IN EXAMPLE.
TYPE_4
DD
?
; OVERFLOW NOT SUPPLIED IN EXAMPLE.
; SKIP RESERVED PART OF EXAMPLE
ORG
32'4
TYPE_32
DD
?
; 8259A IRa - AVAILABLE
TYPE_33
DD
?
; 8259A IR1 - AVAILABLE
TYPE_34
DD
?
; 8259A IR2 - AVAILABLE
TYPE_35
DD
TIMER_PULSE
; 8259A IR3
TYPE_36
DD
?
; 8259A IR4 - AVAILABLE
TYPE_37
DD
?
; 8259A IR5 - AVAILABLE
TYPE_38
DD
?
; 8259A IR6 - AVAILABLE
TYPE_39
DD
?
; 8259A IR7 - AVAILABLE

,
; POINTER FOR TYPE 40 SUPPLIED BY PL/M-86 COMPILER
INT _POINTERS

ENDS

BATTERY
SEGMENT
; THIS RAM SEGMENT IS BATTERY-POWERED. IT CONTAINS VITAL DATA
;
THAT MUST BE MAINTAINED DURING POWER OUTAGES.
STACK_PTR
DW?
; SP SAVE AREA
STACK_SEG
DW?
; SS SAVE AREA
;SPACEFOROTHERVAR~BLESCOULDBEDEANEDHERE.

BATTERY

ENDS

DATA
SEGMENT
; RAM SEGMENTTHAT IS NOT BACKED UP BY BATTERY
N_PULSES
DB
1 DUP (0)
; ETC.
DATA

ENDS

SEGMENT
STACK
; LOCATED IN BATTERY-POWERED RAM
DW
100 DUP (?)
STACK_TOP
STACK

; #TIMER PULSES

LABEL

; THIS IS AN ARBITRARY STACKSIZE

WORD
ENDS

; LABEL THE INITIAL TOS

INTERRUPT_HANDLERS
SEGMENT
; INTERRUPT PROCEDURES EXCEPT TYPE 40 (PLI M-86)
ASSUME:

CS:INTERRUPT_HANDLERS,DS:DATA,SS:STACK,ES:BATTERY

POWER_FAIL
PROC
; TYPE 2 INTERRUPT
; POWER FAIL DETECT CIRCUIT ACTIVATES NMI LINE ON CPU IF POWER IS
ABOUT TO BE LOST. THIS PROCEDURE SAVES THE PROCESSOR STATE IN
RAM (ASSUMED TO BE POWERED BY AN AUXILIARY SOURCE) SO THAT IT
CAN BE RESTORED BY A WARM START ROUTINE IF POWER RETURNS

Figure 2-88. Interrupt Procedures Example
2-121

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

; IP, CS, AND FLAGS ARE ALREADY ON THE STACK.
SAVE THE OTHER REGISTERS.
PUSH
AX
BX
PUSH
PUSH
CX
PUSH
DX
PUSH
SI
PUSH
DI
PUSH
BP
PUSH
DS
PUSH
ES
; CRITICAL MEMORY VARIABLES COULD ALSO BE SAVED ON THE STACK ATTHIS
POINT. ALTERNATIVELY, THEY COULD BE DEFINED IN THE "BATTERY"
SEGMENT, WHERE THEY WILL AUTOMATICALLY BE PROTECTED IF MAIN POWER
IS LOST.
; SAVE SP AND SS IN FIXED LOCATIONS THAT ARE KNOWN BY WARM START ROUTINE.
MOV
AX,BATTERY
MOV
ES,AX
MOV
ES:STACK_PTR,SP
MOV
ES:STACK_SEG,SS
; STOP GRACEFULLY
HLT
ENDP
TIMER_PULSE
PROC
; TYPE 35 INTERRUPT
; THIS PROCEDURE HANDLES THE 50MS INTERRUPTS GENERATED BY THE 8253.
IT COUNTS THE INTERRUPTS AND ACTIVATES THE TYPE 40 INTERRUPT
PROCEDURE ONCE PER SECOND.

,
; DS IS ASSUMED TO BE POINTING TO THE DATA SEGMENT

,

; THE 8253 IS RUNNING FREE, AND AUTOMATICALLY LOWERS ITS INTERRUPT
REQUEST. IF A DEVICE REQUIRED ACKNOWLEDGEMENT,THE CODE MIGHTGO HERE.

,
; NOW PERFORM PROCESSING THAT MUST NOT BE INTERRUPTED (EXCEPT FOR NMI).
N_PULSES
INC
; ENABLE HIGHER-PRIORITY INTERRUPTS AND DO LESS CRITICAL PROCESSING
STI
CMP
N_PULSES,200; 1 SECOND PASSED?
DONE
; NO, GO ON.
JBE
MOV
N_PULSES,O
; YES, RESET COUNT.
40
; UPDATE CLOCK
INT
; SEND NON-SPECIFIC END-OF-INTERRUPT COMMAND TO 8259A, ENABLING EQUAL
OR LOWER PRIORITY INTERRUPTS.
;
; EOI COMMAND
DONE:
MOV
AL,020H
OCOH ,AL
; 8259A PORT
OUT
IRET
TIMER_PULSE
ENDP
INTERRUPT_HANDLERS

ENDS

CODE
SEGMENT
; THIS SEGMENT WOULD NORMALLY RESIDE IN ROM.
ASSUME

CS:CODE,DS:DATA,SS:STACK,ES:NOTHING

Figure 2-88. Interrupt Procedures Example (Cont'd.)
Mnemonics © Intel, 1978

2-122

8086 AND 8088 CENTRAL PROCESSING UNITS

INIT
PROC
NEAR
; THIS PROCEDURE IS CALLED fOR BOTH WARM AND COLD STARTS TO INITIALIZE
THE 8253 AND THE 8259A. THIS ROUTINE DOES NOT USE STACK, DATA, OR
EXTRA SEGMENTS, AS THEY ARE NOT SET PREDICTABLY DURING A WARM STA.RT.
INTERRUPTS ARE DISABLED BY VIRTUE Of THE SYSTEM RESET.
; INITIALIZE 8253 COUNTER 1 - OTHER COUNTERS NOT USED.
; CLK INPUT TO COUNTER IS ASSUMED TO BE 1.23 MHZ.
L050MS
HI50MS
CONTROL
COUNT_1
MODE2

EQU
EQU
EQU
EQU
EQU

OOOH
OfOH
OD6H
OD2H
01110100B

; COUNT VALUE IS
;
61440 DECIMAL.
; CONTROL PORT ADDRESS
; COUNTER 1 ADDRESS
; MODE 2, BINARY

; LOAD CONTROL BYTE
MOV
DX,CONTROL
MOV
AL,MODE2
OUT
DX,AL
MOV
DX,COUNT_1
; LOAD 50MS DOWNCOUNT
MOV
AL,L050MS
DX,AL
OUT
MOV
AL,HI50MS
DX,AL
OUT
; COUNTER NOW RUNNING, INTERRUPTS STILL DISABLED.
; INITIALIZE 8259A TO: SINGLE INTERRUPT CONTROLLER, EDGE-TRIGGERED,
; INTERRUPT TYPES 32-40 (DECIMAL) TO BE SENT TO CPU fOR INTERRUPT
; REQUESTS 0-7 RESPECTIVELY, 8086 MODE, NON-AUTOMATIC END-Of-INTERRUPT.
; MASK Off UNUSED INTERRUPT REQUEST LINES.
ICW1
ICW2
ICW4
OCW1
PORT_A
PORT_B

EQU
EQU
EQU
EQU
EQU
EQU

00010011 B
00100000B
00000001 B
11110111B
OCOH
OC2H

; EDGE-TRIGGERED, SINGLE 8259A, ICW4 REQUIRED.
; TYPE 20H, 32 - 40D
; 8086 MODE, NORMAL EOI
; MASK ALL BUT IR3
; ICW1 WRITTEN HERE
; OTHER ICW'S WRITTEN HERE

MOV
DX,PORT_A
; WRITE 1ST ICW
MOV
AL,ICW1
DX,AL
OUT
MOV
DX,PORT_B
; WRITE 2ND ICW
MOV
AL,ICW2
OUT
DX,AL
MOV
AL,ICW4
; WRITE 4TH ICW
OUT
DX,AL
MOV
AL,OCW1
; MASK UNUSED IR'S
OUT
DX,AL
; INITIALIZATION COMPLETE, INTERRUPTS STILL DISABLED
RET
INIT
ENDP

USER_PGM:
; "REAL" CODE WOULD GO HERE. THE EXAMPLE EXECUTES AN ENDLESS LOOP
UNTIL AN INTERRUPT OCCURS.
JMP
USER_PGM

; EXECUTION STARTS HERE WHEN CPU IS RESET.
POWER_fAIL_STATUS
EQU
OEOH
ENABLE_RAM
EQU
OE2H

; PORT ADDRESS
; PORT ADDRESS

Figure 2-88. Interrupt Procedures Example (Cont'd.)
2-123

Mnemonics © Intel, 1978

8086 AND 8088 CENTAALPROCESSINGUNITS

; ENABLE BATTERY-POWERED RAM SEGMENT
START:
MOV
AL,001H
OUT
ENABLE_RAM,AL
; DETERMINE WARM OR COLD START
IN
AL,POWER_FAIL._STATUS
RCR
AL,1
; ISOLATE LOW BIT
JC
WARM_START
COLD_START:
; INITIALIZE SEGMENT REGISTERS AND STACK POINTER.
ASSUME CS:CODE,DS:DATA,SS:STACK,ES:NOTHING
; RESET TAKES CARE OFCS AND IP.
MOV
AX,DATA
MOV
DS,AX
MOV
AX,STACK
MOV
SS,AX
MOV
SP ,OFFSET STACK_TOP
; INitiALIZE 8253 AND 8259A.
CALL

INIT

; ENABLE INTERRUPTS
STI
; START MAIN PROCESSING
JMP
WARM_START:
; INITIALIZE 8253 AND 8259A.
CALL

INIT

; RESTORE SYSTEM to STATE AT THE TIME POWER FAILED
; MAKE BATTERY SEGMENT ADDRESSABLE
MOV
AX,BATTERY
MOV
DX,AX
; VARIABLES SAVED IN THE "BATTERY" SEGMENT WOULD BE MOVED
BACK TO UNPROTECTED RAM NOW. SEGMENT REGISTERS AND
"ASSUME" DIRECTIVES WOULD HAVE TO BE WRITTEN TO GAIN
ADDRESSABILITY.
; RESTORE THE OLD STACK
MOV
SS,DS:STACK_SEG
MOV
SP,DS:STACK_PTR

CODE

; RESTORE THE OTHER REGISTERS
POP
ES.
POP
OS
POP
BP
POP
01
POP
SI
POP
OX
POP
CX
POP
BX
POP
AX
; RESUME THE ROUTINE THAT WAS EXECUTING WHEN NMI WAS ACTIVATED.
I.E., POP CS, IP, & FLAGS, EFFECTIVELY "RETURNING" FROM THE
NMI PROCEDURE.
IRET
ENDS
; TERMINATE ASSEMBLY AND MARK BEGINNING OFTHE PROGRAM.
END
START

Figure 2-88. Interrupt Procedures Example (Cont'd.)
Mnemonics © Intel, 1978

2-124

8086 AND 8088 CENTRAL PROCESSING UNITS

TYPE$40: DO;
DECLARE (HOUR, MIN, SEC) BYTE PUBLIC;
UPDATE$TOD: PROCEDURE INTERRUPT 40;
"THE PROCESSOR ACTIVATES THIS PROCEDURE
'TO HANDLE THE SOFTWARE INTERRUPT
'GENERATED EVERY SECOND BY THE TYPE 35
'EXTERNAL INTERRUPT PROCEDURE. THIS
'PROCEDURE UPDATES A REAL-TIME CLOCK.
'IT DOES NOT PRETEND TO BE "REALISTIC"
'AS THERE IS NO WAYTO SET THE CLOCK."
SEC=SEC+1;
IF SEC = 60 THEN DO;
SEC= 0;
MIN = MIN + 1;
IF MIN = 60 THEN DO;
MIN =0;
HOUR=HOUR+1;
IF HOUR = 24 THEN DO;
HOUR= 0;
END;
END;
END;
END UPDATE$TOD;
END;

Figure 2-88. Interrupt Procedures Example (Cont'd.)
(the index register is auto-decremented) to find
the last period (".") in the string. Finally a byte
string of EBCDIC characters is translated to
ASCII. The translation is stopped at the end of
the string or when a carriage return character is
encountered, whichever occurs first. This is an
example of using the string primitives in combination with other instructions to build up more complex string processing operations.

String Operations

Figure 2-89 illustrates typical use of string instructions and repeat prefixes. The XLAT instruction
also is demonstrated. The first example simply
moves 80 words of a string using MOVS. Then
two byte strings are compared to find the
alphabetically lower string, as might be done in a
sort. Next a string is scanned from right to left

ALPHA
SEGMENT
; THIS IS THE DATA THE STRING INSTRUCTIONS WILL USE
OUTPUT
DW 100
DUP (?)
INPUT
DW 100
DUP (?)
NAME_1
DB 'JONES, JON A'
NAME_2
DB 'JONES, JOHN'
DB 80
DUP (?)
SENTENCE
EBCDIC_CHARS DB 80
DUP (?)
ASCII_CHARS
DB 80
DU P (?)
CONY _TAB
DB 64
DU P(OH)
; EBCDIC TO ASCII

Figure 2-89. String Examples
2-125

Mnemonics © Intel, 1978

8086 AND 8088 CENTRAL PROCESSING UNITS

; ASCII NULLS ARE SUBSTITUTED FOR "UNPRINTABLE" CHARS
DB 1
20H
DB 9
DUP (OH)
DB?
'Q:',',','<','(','+',OH,'&'
DB 9
DUP (OH)
DBB
'!','$','*',')',';',' ','-','/'
DB 8
DUP (OH)
DB6
' ',',',1%', '_', I>', '?'
DB 9
DUP (OH)

D817

",':','#','@','''','=',''1',

DB 7

OH, 'a', 'b', Ie', 'd', Ie', If', 'g,', 'h', 'i'
DUP (OH)

DB9

Ij', 'k', 'I', 'm', In', '0', 'p', 'q', 'r'

DB 7

DUP (OH)

'1',

DB9

'~',

DB 22

DUP (OH)

'5',

lU',

'v', 'w', 'x', 'y', 'z'

' ','A', '8', 'G', 'D', 'E', IF', 'G', 'l-'i', 'I'

0810
DB 6
0810
DB 6
DB10
DB 6
0810
DB 6

DUP (OH)

' ','J', 'K','L', 'M', 'N', '0', 'P', 'Q', lR'
DUP (OH)
",OH,'S','T','U','V','W','X','Y','Z'
DUP (OH)

'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'
DUP (OH)

ALPHA

ENDS

STACK

SEGMENT
DW 100

DUP (?)

; THIS IS AN ARBITRARY STACK SIZE
; FOR ILLUSTRATION ONLY.
; INITIAL TOS

STACK_BASE
STACK

LABEL
ENDS

CODE
BEGIN:

SEGMENT
; SET UP SEGMENT REGISTERS. NOTICE THAT
; ES & DS POINT TO THE SAME SEGMENT, MEANING
; THAT THE CURRENT EXTRA & DATA
; SEGMENTS FULLY OVERLAP. THIS ALLOWS
; ANY STRJNG IN "ALPHA" TO BE USED
; AS A SOURCE OR A DESTINATION.
ASSUME CS: CODE, SS: STACK,
DS:ALPHA,ES:ALPHA
MOV
AX, STACK
MOV
SS, AX
MOV
SP, OFFSET STACK_BASE; INITIAL TOS
MOV
AX, ALPHA
MOV
DS, AX
MOV
ES, AX

&

WORD

; MOVE THE FIRST 80 WORDS OF "INPUT" TO
THE LAST 80 WORDS OF "OUTPUT".
LEA
SI, INPUT
LEA
DI, OUTPUT +20

; INITIALIZE
; INDEX REGISTERS

Figure 2-89. String Examples (Cont'd.)
Mnemonics © Intel, 1978

2-126

8086 AND 8088 CENTRAL PROCESSING UNITS

REP

MOV
CLD
MOVS

CX,SO

; REPETITION COUNT
; AUTO-INCREMENT

OUTPUT, INPUT

; FIND THE ALPHABETICALLY
MOV
MOV
MOV
CLD
REPE CMPS
JB
NAME_1_LOW:
NAME_2_LOW:

LOWER OF 2 NAMES.
SI, OFFSET NAME_1 ; ALTERNATIVE
01, OFFSET NAME_2 ; TO LEA
CX, SIZE NAME_2
; CHAR. COUNT
; AUTO-INCREMENT
NAME_2, NAME_1
"WHILE EQUAL"
NAME_2_LOW
; NOT IN THIS EXAMPLE
; CONTROL COMES HERE IN THIS EXAMPLE.
; 01 POINTS TO BYTE ('H') THAT
; COMPARED UNEQUAL.

; FIND THE LAST PERIOD (' .') IN A TEXT STRING.
MOV
01, OFFSET SENTENCE +
&
LENGTH SENTENCE ; START AT END
MOV
CX, SIZE SENTENCE
STD
; AUTO-DECREMENT
MOV
AL, '.'
; SEARCH ARGUMENT
REPNE
SCAS
SENTENCE
; "WHILE NOT ="
JCXZ
NO_PERIOD
; IF CX=O, NO PERIOD FOUND
; IF CONTROL COMES HERE THEN
PERIOD:
; 01 POINTS TO LAST PERIOD IN SENTENCE.
NO_PERIOD:
; ETC.
; TRANSLATE A STRING OF EBCDIC CHARACTERS
TO ASCII, STOPPING IF A CARRIAGE RETURN
(ODH ASCII) IS ENCOUNTERED.
MOV
BX,OFFSETCONV __ TAB; POINTTO TRANSLATE TABLE
MOV
SI, OFFSET EBCDIC_CHARS ; INITIALIZE
01, OFFSET ASCILCHARS
INDEX REGISTERS
MOV
MOV
CX, SIZE ASCII_CHARS
;
AND COUNTER
CLD
; AUTO-INCREMENT
NEXT:
LODS
EBCDIC_CHARS
; NEXT EBCDIC CHAR IN AL
XLAT
CONV_ TAB
; TRANSLATE TO ASCII
STOS
ASCII_CHARS
; STORE FROM AL
TEST
AL,ODH
; IS IT CARRIAGE RETU RN?
LOOPNE
NEXT
; NO, CONTINUE WHILE CX NOT 0
JE
CR_FOUND
; YES, JUMP
; CONTROL COMES HERE IF ALL CHARACTERS
HAVE BEEN TRANSLATED BUT NO
;
CARRIAGE RETURN IS PRESENT.
; ETC.

; 01-1 POINTS TO THE CARRIAGE RETURN
IN ASCII_CHARS.
CODE

ENDS
END

Figure 2-89. String Examples (Cont'd.)
2-12712-128

Mnemonics © Intel, 1978

Chapter 3
The 8089
Input/Output Processor

CHAPTER 3
THE 8089 INPUT/OUTPUT PROCESSOR
This chapter describes the 8089 Input/Output
Processor (lOP). Its organization parallels
Chapter 2; that is, sections generally proceed
from hardware to software topics as follows:
1. Processor Overview
2. Processor Architecture
3. Memory
4. Input/Output
5. Multiprocessing Features
6.
7.
8.
9.
10.

Vss

A1S/D1S

Al31D13

Al6fS3

A12/D12

Al1/S4

Al1fDll

A18/SS

A1U/D1U

A19/S8

Processor Control and Monitoring
Instruction Set
Addressing Modes
Programming Facilities
Programming Guidelines and Examples

A9/D9

BHE

A6fD8

EXT 1

A7/D7

EXT 2

A6fD8

DRQl

AS/DS

DRQ2

A4/D4

lOCK

A3/D3

52

A2fD2

51

A1fDl

SO
RQ/GT

AU/DU
SINTR·l
SINTR·2

As in Chapter 2, the discussion is confined to
covering the hardware in functional terms; timing, electrical characteristics and other physical
interfacing data are provided in Chapter 4.

Vee

A14/D14

SEl
CA

ClK

READY

Vss

RESET

Figure 3-1. 8089 Input/Output Processor
Pin Diagram

3.1 Processor Overview
Evolution
The 8089 Input/Output Processor is a highperformance, general-purpose I/O system
implemented on a single chip. Within the 8089 are
two independent I/O channels, each of which
combines attributes of a CPU with those of a very
flexible DMA (direct memory access) controller.
For example, channels can execute programs like
CPUs; the lOP instruction set has about 50 different types of instructions specifically designed
for efficient input/output processing. Each channel also can perform high-speed DMA transfers; a
variety of optional operations allow the data to be
manipulated (e.g., translated or searched) as it is
transferred. The 8089 is contained in a 40-pin
dual in-line package (figure 3-1) and operates
from a single + 5V power source. An integral
member of the 8086 family, the lOP is directly
compatible with both the 8086 and 8088 when
these processors are configured in maximum
mode. The lOP also may be used in any system
that incorporates Intel's Multibus™ shared bus
architecture, or a superset of the Multibus™
design.

Figure 3-2 depicts the general trend in CPU and
I/O device relationships in the first three generations of microprocessors. First generation CPUs
were forced to deal directly with substantial
numbers of TTL components, often performing
transfers at the bit level. Only a very limited
number of relatively slow devices could be
supported.
Single-chip interface controllers were introduced
in the second generation. These devices removed
the lowest level of device control from the CPU
and let the CPU transfer whole bytes at once.
With the introduction of DMA controllers, highspeed devices could be added to a system, and
whole blocks of data could be transferred without
CPU intervention. Compared to the previous
generation, I/O device and DMA controllers
allowed microprocessors to be applied to problems that required moderate levels of I/O, both in
terms of the numbers of devices that could be supported and the transfer speeds of those devices.

3-1

8089 INPUT /OUTPUT PROCESSOR

The controllers themselves, however, still
required a considerable amount of attention from
the CPU, and in many cases the CPU had to
respond to an interrupt with every byte read or
written. The CPU also had to stop while DMA
transfers were performed.

Principles of Operation
Since the 8089 is a new concept in microprocessor
components, this section surveys the basic operation of the lOP as background to the detailed
descriptions provided in the rest of the chapter.
This summary deliberately omits some operating
details in order to provide an integrated overview
of basic concepts.

The 8089 introduces the third generation of
input/output processing. It continues the trend of
simplifying the CPU's "view" of I/O devices by
removing another level of control from the CPU.
The CPU performs an I/O operation by building
a message in memory that describes the function
to be performed; the lOP reads the message, carries out the operation and notifies the CPU when
it has finished. All I/O devices appear to the CPU
as transmitting and receiving whole blocks of
data; the lOP can make both byte- and word-level
transfers invisible to the CPU. The lOP assumes
all device controller overhead, performs both programmed and DMA transfers, and can recover
from "soft" I/O errors without CPU intervention; all of these activities may be performed
while the CPU is attending to other tasks.

CPU/lOP Communications

A CPU communicates with an lOP in two distinct
modes: initialization and command. The
initialization sequence is typically performed
when the system is powered-up or reset. The CPU
initializes the lOP by preparing a series of linked
message blocks in memory. On a signal from the
CPU, the lOP reads these blocks and determines
from them how the data buses are configured and
how access to the buses is to be controlled.

HOLe/SOLe
PROTOCOL
CONTROLLER

(FUTURE CONTROLLER)

(

DATA LINK

... , r - -Ir~~;,;,I
?

/A... '"

,/ /' FLOPPY DISK

CONTROLLER

Figure 3-2. lOP Evolution
3-2

110

L ~E:C:.J

80891NPUT/OUTPUT PROCESSOR

tain space for variables (results) that the channel
is to return to the CPU~ Except for the first two
words, the format and size of a parameter block
are completely open; the PB may be set up to
exchange any kind of information between the
CPU and the channel program.

Following initialization, the CPU directs all communications to either of the lOP's two channels;
indeed, during normal operation the lOP appears
to be two separate devices-channel 1 and channel2. All CPU-to-channel communications center
on the channel control block (CB) illustrated in
figure 3-3. The CB is located in the CPU's
memory space, and its address is passed to the
lOP during initialization. Half of the block is
dedicated to each channel. The channel maintains
the BUSY flag that indicates whether it is in the
midst of an operation or is available for a new
command. The CPU sets the CCW (channel command word) to indicate what kind of operation
the lOP is to perform. Six different commands
allow the CPU to start and stop programs,
remove interrupt requests, etc.

A task block is a channel program-a sequence of
8089 instructions that will perform an operation.
A typical channel program might use parameter
block data to set up the lOP and a device controller for a transfer, perform the transfer, return
the results, and then halt. However, there are no
restrictions on what a channel program can do; its
function may be simple or elaborate to suit the
needs of the application.
Before the CPU starts a channel program, it links
the program (TB) to the parameter block and the
parameter block to the CB as shown in figure 3-3.
The links .are standard 8086/8088 doubleword
pointer variables; the lower-addressed word contains an offset, and the higher-addressed word
contains a segment base value. A system may
have many different parameter and task blocks;
however, only one of each is ever linked to a
channel aniny given time.

If the CPU is dispatching a channel to run a program, it directs the channel to a parameter block
(PB) and a task block (TB); these are also shown
in figure 3-3. The parameter block is analogous to
a parameter list passed by a program to a
subroutine; it contains variable data that the
channel program is to use in carrying out its
assignment. The parameter block also may con-

CHANNEL CONTROL BLOCK (CB)
(RESERVED)

-i -p(~~~r:.rN\RB~LS~C&KJ~~~~fr- ~~
1

(RESERVED)

-{

}

CHANNEL.

}

CHANNEL 1

ccw

BUSY

-p~~~':ti1VB~'s~C&K6~~~~f)R-

l

BUSY

15

~

ccw

87

~--------l

CHANNEL 2 PARAMETER BLOCK (P8)

1

CHANNEL PROGRAM PARAMETERS

r{

(APPLICATION·DEFINED)

I

1

~________________~4

TASK BLOCK POINTER

(SEGMENT BASE,. OFFSET)

II
I

o' ~~

:

CHANNEl2TASK BLOCK (TB)
(CH~'NNEl PROGRAM)

1

8089
INSTRUCTIONS
(APPLICATION-

DEFINED)

1

I
I
I
I
I
I
I
I
I
I
I

"

L_~

CHANNEL 1 TASK BLOCK (TB)
(CHANNEL PROGRAM)

8089
INSTRUCTIONS
(APPLICATION.
DEFINED)

_ _ _ _ _ _ _---i

Figure 3-3. Command Communication Blocks
3-3

, 8089JN'PUT /OUTPUT'PROCESSOR

Channels

After· the CPU. has filled in the CCW and has
linked the CB to a parameter block and a task
block, if appropriate, it issues a channel attention
(CA). This is done by activating the 10P's- CA
(channel attention) and SEL (channel select) pins.
The state of SEL at the falling edge of CA directs
the channel attention to channell or channel 2. If
the lOP is located in the CPU's 1/0 spa~e, it
appears to the CPU as two consecutive 1/0 'ports
(one for each channel), and an OUT instruction
to the port functions as a CA. lithe lOP is
memory-mapped, the channels appear as two
consecutive memory locations, and any memory
reference instruction (e.g., MOV) to these locations causes a channel attention.

Each of the two . lOP channels operates
iridependentiy,;a:ndeach has its own register set.
channelaitention, interrupt request and DMA
control signals. At a given point in time,.6 channel may be idle, executing a program', performing
a DMAtransfer, or responding to a channel
attention. Although only one channel actually
runs at a time, the channels can be active eoncur·)
rentiy, alternating their operations (e.g;, channel
1 may execute instructions in the periods between
successive DMA transfer cycles run by channel 2).
A built-in priority system allows high-priority
activities on one channel to preempt less critical
operations on the other channel. The CPU is able
to further adjust priorities to handle special cases.
The CPU starts the channel and can halt it, suspend it, or cause it to resume a suspended opera:tion by placing different values in theCCW.

An lOP channel attention is functionally similar
to a CPU interrupt. When the channel recognizes
the CA, it stops what it is doing (it will typically
be idle) and examines the command in the CCW.
If it is to start a program, the channei loads the
addresses of the parameter and task blocks jnto
internal registers, sets its BUSY flag and' starts
executing the channel program. After it has issued
the,CA, the CPU is free to perform other processing; the channel can perform. its function,in
parallel, subject to limitations imposed by bus
configurations (discussed shortly).

Channel Programs (Task Blocks)
Channel programs are written in ASM-89,the
8089 assembly language. About 50 basic instructions are available. These instructions operate on
- bit, byte, word and doubleword (pointer) variable
types; a 20-bit physical address variable type (not
used by the 8086/8088) can also be manipulated.
Data may be taken from registers, immediate constants and memory. Four memory addressing
modes allow flexible access to both memory
variables and 110 devices located anywhere in
either the CPU's megabyte memory space or in
the 8089's 64k 110 space.
.

When the channel has completed its program, it·
notifies the CPU by clearing its BUSY flag in the
CB. Optionally, irmay issue an interrupt request
to the CPU.
The CPUIIOP communication structure is summarized in figure 3-4. Most communication:takes
place via "message areas" shared in common
memory. The only direct hardware communications between the devices .are channel attentions
and interrupt requests.

The lOP instruction set contains general purpose
instructions similar to those found in CPUs as
well as instructions specifically tailored for 110

CHANNEL ATTENTION

CPU

MESSAGES
IN
MEMORY

,
lOP
.- .

INTERRUPT

FiBUre 3-4. CPUIIOP Commpnication.
3-4

8089 INPUTIOUTPUT PROCESSOR

Between the fetch and store cycles, the lOP can
operate on the data. A byte may be translated to
another code (e.g., EBCDIC to ASCII), or compared to a search value, or both, if desired.

operations. Data transfer, simple arithmetic,
logical and address manipulation operations are
available. Unconditional jump and call instructions also are provided so that channel programs
can link to each other. An individual bit may be
set or cleared with a single instruction. Conditional jumps .can test a bit and jump if it is set (or
cleared), or can test a value and jump if it is zero
(or non-zero). Other instructions initiate DMA
transfers, perform a locked test-and-set
semaphore operation, and issue an interrupt
request to the CPU.

A transfer can be terminated by several
programmer-specified conditions. The channel
can stop the transfer when a specified number (up
to 64k) of bytes has been transferred. An external
device may stop a transfer by signaling on the
channel's external terminate pin. The channel can
stop the transfer when a byte (possibly translated)
compares equal, or unequal, to a search value.
Single-cycle termination, which stops unconditionally after one byte or word has been stored, is
also available.

DMA Transfers
The 8089 XFER (transfer) instruction prepares
the channel for a DMA transfer. It executes one
additional instruction, then suspends program
execution and enters the DMA transfer mode.
The transfer is governed by channel registers
setup by the program prior to executing the
XFER instruction.

When the transfer terminates, the channel
automatically resumes program execution. The
channel program can determine the cause of the
termination in situations where multiple terminations are possible (e.g., terminating when 80 bytes
are transferred or a carriage return character is
encountered, whichever occurs first). As an example of post-transfer processing, the channel program could read a result register from the I/O
device controller to determine if the transfer was
performed successfully. If not (e.g., a CRC error
was detected by the controller), the channel program could retry the operation without CPU
intervention.

Data is transferred from a source toa destination.
The source and destination may be any locations
in the CPU's memory space or in the lOP's 110
space; the lOP makes no distinction between
memory components and 110 devices. Thus
transfers may be made from 110 device to
memory, memory to I/O device, memory to .
memory and I/O device to.l/O device. The lOP
automatically matches 8- and 16-bit components
to each other.

A channel program typically ends by posting the
result of the operation to a field supplied in the
parameter block, optionally interrupting the
CPU, and then halting. When the channel halts,
its BUSY flag in the channel control block is
cleared to indicate its availability for another
operation. As an alternative to being interrupted
by the channel, the CPU can poll this flag to
determine when the operation has been
completed.

Individual transfer cycles (Le., the movement of a
byte or a word) may be synchronized by a signal
(DMA request) from the source or from the
destination. In the synchronized mode, the channel waits for the synchronizing signal before starting the next transfer cycle. The transfer also may
be unsynchronized, in which case the channel
begins the next transfer cycle immediately upon
completion of the previous cycle.

Bus Configurations
A transfer cycle is performed in two steps: fetching a byte or word from the source into the lOP
and then storing it from the lOP into the destination. The lOP automatically optimizes the
transfer to make best use of the available data bus
widths. For example, if data is being transferred
from an 8-bit device to memory that resides on a
16-bit bus (e.g., 8086 memory), the lOP will normally run two one-byte fetch cycles and then store
the full word in a single cycle.

As shown in figure 3-5, the lOP can access
memory or ports (I/O devices) located in a
I-megabyte system space and memory or ports
located in a 64-kilobyte 110 space. Although the
lOP only has one physical data bus, it is useful to
think of the lOP as accessing the system space'via
a system data bus and the 110 space over an I/O
data bus. The distinction between the "two"
buses is based on the type-of-cycle signals output
3-5

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

by the 8288 Bus Controller. Components in the
system space respond to the memory read and
memory write signals, whether they are memory
or 110 devices. Components in the 1/0 space
respond to the 110 read and 110 write signals.
Thus 110 devices located in the system space are
memory-mapped and memory in the 110 space is
1I0-mapped. The two basic configuration options differ in the degree to which the lOP shares
these buses with the CPU. Both configurations require an 8086/8088 CPU to be strapped in maximummode.

8088 or 16 bits if the CPU is an 8086). The lOP
system space corresponds to the CPU memory
space, and the lOP 110 space corresponds to the
CPU 110 space. Channel programs are located in
the system space; 110 devices may be located in
either space. The lOP requests use of the bus for
channel program instruction fetches as well as for
DMA and programmed transfers. In the local
configuration, either the lOP or the CPU may use
the buses, but not both simultaneously. The
advantage of the local configuration is that
intelligent DMA may be added to a system with
no additional components beyond the lOP. The
disadvantage is that parallel operation of the processors is limited to cases in which the CPU has
instruction in its queue that can be executed
without using the bus.

In the local configuration, shown in figure 3-6,
the lOP (or lOPs if two are used) shares both
buses with the CPU. The system bus and the 110
bus are the same width (8 bits if the CPU is an

MEMORY

MEMORY

SYSTEM SPACE (1 MBYTE)

1/0 SPACE (64 KBYTES)

SYSTEM
DATA
BUS

1/0
DATA
BUS
lOP

Figure 3-5. lOP Data Buses
3-6

8089 INPUT IOUTPUT PROCESSOR

8089 lOP

.... -

B
SYSTEM SPACE

Figure 3-6. Local Configuration
In the remote configuration (figure 3-7), the lOP
(or lOPs) shares a common system blls with the
CPU. Access to this bus is controlled by 8289 Bus
Arbiters. The lOP's 110 bus, however, is
physically separated from the CPU in the remote
configuration. Two lOPs can share the local 110
bus. Any number of remote lOPs may be contained in a system, configured in remote clusters
of one or two. The local 1/0 bus need not be the
same physical width as the shared system bus,
allowing an lOP, for example, to interface 8-bit
peripherals to an 8086. In the remote configuration, the lOP can access local 1/0 devices and
memory without using the shared system bus,
thereby reducing bus contention with the CPU.
Contention can further be reduced by locating the
lOP's channel programs in the local 110 space.
The lOP can then also fetch instructions without

accessing the system bus. Parameter, channel
control and other CPUIIOP communication
blocks must be located in system memory,
however, so that both processors can access them.
The remote configuration thus increases the
degree to which an lOP and a CPU can operate in
parallel and thereby increases a .system's
throughput potential. The price paid for this is
that additional hardware must be added to
arbitrate use of the shared bus, and to separate
the shared and local buses (see Chapter '4 for
details).
It is also possible to configure an lOP remote to
one CPU, and local to another CPU (see figure
3-8). The local CPU could be used to perform
heavy computational routines for the lOP.

3-7

8089 INPUT /OUTPUT PROCESSOR

r-----------,
'--7 1

I
I
1

~--,

(1/0 DEVICE)

(1/0 DEVICEI

' - __ l.

, __ ~

!+1

8289
BUS
ARBITER

80861
8088
CPU

L _ ~!!.O~U;O.£.A,!;.I/.2.S~~ _ .J
NOT ACCESSIBLE TO lOPs

SYSTEM SPACE

8089
lOP
II)

B

::>

ro

0

::::
..J
«

8289
BUS
ARBITER

LOCAL BUS
I ARBITRATION

0

0

..J

OPTIONAL
8089
lOP

1/0 SPACE

NOT ACCESSIBLE TO CPU

\

_----------,
~

•

I

II rI -

- - ,I

-,I (·

1/0

DEVICE

I 11

: I MEMORY 1 ; ' : : ;

:1 L__ J I'---~
D~~~E I

r--,

r
•
I~

II)

:+- -I~

:
I
~~~C!. _______ -I

+.1

I

L

8089
lOP

1+

.,

1

_._..J

I
•

rI - - , I

IALR~7NA~ygNI_ +. AR~VJER

!+-

i-'-}.. : L__ J

:~L.~
..

7i

8089
lOP

...

L __
Figure 3-7. Remote Configuration
3-8

8089 INPUT/OUTPUT PROCESSOR

80861
8088
CPU

8289
BUS
ARBITER

SYSTEM SPACE

.

EJ

~

8089
lOP
III
::I
a:I

o

8289
BUS
ARBITER

:;«
t)

o....

1/0 SPACE

80861
8088
CPU

NOT ACCESSIBLE TO SYSTEM CPU

Figure 3-8. Remote lOP Configured With Local 8086/8088
3-9

8089 INPUT /OUTPUT PROCESSOR

A Sample Transaction

delete, etc.) in the parameter block and let a single
channel program execute different routines
depending on which function is requested.

Figure 3-9 shows how a CPU and an lOP might
work together to read a record (sector) from a
floppy disk. This example is not illustrati-:e of t~e
lOP's full capabilities, but it does review Its basIc
operation and its interaction with a CPU.

After the communication blocks have been setup,
the CPU dispatches the channel by issuing a channel attention, typically by an OUT instruction for
an I/O-mapped 8089, or a MOV or other memory
reference instruction for a memory-mapped 8089.

The CPU must first obtain exclusive use of a
channel. This can be done by performing a "test
and set lock" operation on the selected channel's
BUSY flag. Assuming the CPU wants to use
channel 1, this could be accomplished in
PLlM-86 by coding similar to the following:

The channel begins executing the channel program (task block) whose address has been placed
in the parameter block by the CPU. In this case
the program initializes the 8271 Floppy Disk Controller by sending it a ".read data" command
followed by a parameter indicating the track to be
read. The program initializes the channel registers
that define and control the DMA transfer.

DO WHILE LOCKSET (@CH1.BUSY,OFFH);
END;
In ASM-86 a loop containing the XCHG instruction prefixed by LOCK .would accomplish the
same thing, namely testing the BUSY flag until it
is clear (OH), and immediately setting it to FFH
(busy) to prevent another task or processor from
obtaining use of the channel.

Having prepared the 8271 and the channel itself,
the channel program executes a XFER instruction
and sends a final parameter (the sector to be read)
to the 8271. (The 8271 enters DMA transfer mode
immediately upon receiving the last of a series of
parameters; sending the last parameter after the
XFER instruction gives the channel time to setup
for the transfer.) The DMA transfer begins when
the 8271 issues a DMA request to the channel.
The transfer continues until the 8271 issues an
interrupt request, indicating that the data has
been transferred or that an error has occurred.
The 8271 's interrupt request line is tied to the
lOP's EXTl (external terminate on channell) pin
so that the channel interprets an interrupt request
as an external terminate condition. Upon termination of the transfer, the channel resumes
executing instructions and reads the 8271 result
register to determine if the data was read successfully. If a soft (correctable) error is indicated,
the lOP retries the transfer. If a hard (uncorrectable) error is detected, or if the transfer has been
successful, the lOP posts the content of the result
register to the parameter block result field, thus
passing the result back to the CPU. The channel
then interrupts the CPU (to inform the CPU that
the request has been processed) and halts.

Having obtained the channel, the CPU fills in a
parameter block (see figure 3-10). In this case, the
CPU passes the following parameters to tile chan. ne!: the address of the floppy disk controller, the
address of the buffer where the data is to be
placed, and the drive, track and sector to be read.
It also supplies space for· the lOP to return the
result of the operation. Note that this is quite a
"low-level" parameter block in that it implies
that the CPU has detailed knowledge of the I/O
system. For a "real" system, a higher-level
parameter block would isolate the CPY from I/~
device characteristics. Such a block might contam
more general parameters such as file name and
record key.
After setting up the parameter block, the CPU
writes a "start channel program" command in
channell' s CCW. Then the CPU places the
address of the desired channel program in the
parameter block and writes the parameter block
address in the CB. Notice that in this simple
example, the CPU "knows" the address of the
channel program for reading from the disk, and
presumably also "knows" the address of anot~er
program for writing, etc. A more general solutIOn
would be to place a function code (read, write,
Mnemonics © Intel, 1979

When the CPU recognizes the interrupt, it
inspects the result field in the parameter block to
see if the content of the buffer is valid. If so, it
uses the data; otherwise it typically executes an
error routine.
3-10

8089 INPUT /OUTPUT PROCESSOR

----8
----[J

----8

ICHANNELISIDLEI

----[J
----[]
I
I
IF laPIS CONFIGURED REMOTELY
CPU CAN CONTINUE WITH OTHER
PROCESSING. OTHERWISE IT WAITS

UNTIL CHANNEL CLEARS BUSY FLAG

[J--

----6---- '~~ii'

[]--

____ ~

ORISSUESINTEARUPTAEQUEST

r------------

I

I
I
I
I
I

I

f
I

INI/OSPACE

'~~;El6AJL~~~STEM SPACE
AR~O=

----8----

I
I
I
I
I
I
I
I

-',.c--G~----

FLOPPY

~----B----

FLOPPY

[J---:..... _____

NO

'-------------

I
I

.!!:I~R~U.!:T

_____ _

I
I

~----G

I
I
I

BUSY FLAG IS CLEARED,
CHANNEL IS IDLE

I

I
I
I
DATA

BUFFER

Figure 3-9. Sample CPUIIOP Transaction
3-11

DISK

DISK

8089 INPUT/OUTPUT PROCESSOR

POINTER TO

---

CHANNEL PROGRAM

___

(OFFSET & SEGMENT)

2

DEVICE ADDRESS

4

POINTER TO BUFFER
(OFFSET & SEGMENT)

---

of the system. I/O specialists can work on the I/O
system without detailed knowledge of the application; conversely, the operating system and
application teams do not need to be expert in the
operation of I/O devices. Standard high-level I/O
systems can be used in multiple application
systems. Because the application and I/O systems
are almost independent, application system
changes can be introduced without affecting the
I/O system. New peripherals can similarly be
incorporated into a system without impacting
applications or operating system software. The
lOP's simple CPU interface also is designed to be
compatible with future Intel CPUs.

o

6
8

TRACK

DRIVE

10

RESULT

SECTOR

12

Figure 3-10. Sample Parameter Block

Keeping in mind the true general-purpose nature
of the lOP, some of the situations where it can be
used to advantage are:
•
Bus matching - The lOP can transfer data
between virtually any combination of8- and
16-bit memory and 110 components. For
example, it can interface a 16-bit peripheral
to an 8-bit CPU bus, such as the 8088 bus.
The lOP also provides a straightforward
means of performing DMA between an 8-bit
peripheral and 8086 memory that is split
into odd- and even-addressed banks. The
8089 can access both 8- and 16-bit
peripherals connected to a 16-bit bus.

Applications
Combining the raw speed and responsiveness of a
traditional DMA controller, an I/O-oriented
instruction set, and a flexible bus organization,
the 8089 lOP is a very versatile I/O system.
Applications with demanding I/O requirements,
previously beyond the abilities of microcomputer
systems, can be undertaken with the lOP. These
kinds of I/O-intensive applications include:
•
systems that employ high-bandwidth, lowlatency devices such as hard disks and
graphics terminals;
•
systems with many devices requiring
asynchronous service; and
•

•

systems with high-overhead peripherals such
as intelligent CRTs and graphics terminals.

In addition, virtually every application that performs a moderate amount of I/O can benefit
from the design philosophy embodied in the lOP:
system functions should be distributed among
special-purpose processors. An lOP channel program is likely to be both faster and smaller than
an equivalent program implemented with a CPU.
Programming also is more straightforward with
the lOP's specialized instruction set.

•

Removing I/O from the CPU and assigning it to
one or more lOPs simplifies and structures a
system's design. The main interface to the I/O
. system can be limited to the parameter blocks.
Once these are defined, the I/O system can be
designed and implemented in parallel with the rest

3-12

String processing - The 8089 can perform a
memory move, translate,· scan-for-match or
scan-for-nonmatch operation much faster
than the equivalent instructions in an 8086 or
8088. Translate and scan operations can be
setup so that the source and destination refer
to the same addresses to permit the string to
be operated on in place.
Spooling - Data from low-speed devices such
as terminals and paper tape readers can be
read by the 8089 and placed in memory or on
disk until the transmission is complete. The
lOP can then transfer the data at high speed
when it is needed by an application program.
Conversely, output data ultimately destined
for a low-speed device such as a printer, can
be temporarily spooled to disk and then
printed later. This permits batches of data to
be gathered or distributed by low-priority
programs that run in the background, essentially using up "spare" CPU and lOP cycles.
Application programs that use or produce
the data can execute faster because they are
not bound by the low-speed devices.

8089 INPUT/OUTPUT PROCESSOR

•

•

•

A single lOP can concurrently support an
alphanumeric CRT and keyboard on one
channel and a floppy disk on the other channel. This configuration makes use of approximately 30 percent of the available bus bandwidth. Performance can be increased within
the available bus bandwidth by adding an
8086 or 8088 CPU to a remote lOP configuration. This configuration can provide
scaling, rotation or other sophisticated
display transformations.

Multitasking operating systems
A
multitasking operating system can dispatch
110 tasks to channels with an absolute
minimum of overhead. Because a remote
channel can run in parallel with the CPU, the
operating system's capacity for servicing
application tasks can increase dramatically,
as can its ability to handle more, and faster,
I/O devices. If both channels of an lOP are
active concurrently, the lOP automatically
gives preference to the higher-priority activity (e.g., DMA normally preempts channel
program execution). The operating system
can adjust the priority mechanism and also
can halt or suspend a channel to take care of
a critical asynchronous event.

3.2 Processor Architecture
The 8089 is internally divided into the functional
units depicted schematically in figure 3-11. The
units are connected by a 20-bit data path to obtain
maximum internal transfer rates.

Disk systems - The lOP can meet the speed
and latency requirements of hard disks. It
can be used to implement high-level, fileoriented systems that appear to application
programs as simple commands: OPEN,
READ, WRITE, etc. The lOP can search
and update disk directories and maintain free
space maps. "Hierarchical memory" systems
that automatically transfer data among
memory, high-speed disks and low-speed
disks, based on frequency of use, can be built
around lOPs. Complex database searches
(reading data directly or following pointer
chains) can appear to programs as simple
commands and can execute in parallel with
application programs if an lOP is configured
remotely.

Common Control Unit (CCU)
All lOP operations (instructions, DMA transfer
cycles, channel attention responses, etc.) are composed of sequences of more basic processes called
internal cycles. A bus cycle takes one internal
cycle; the execution of an instruction may require
several internal cycles. There are 23 different
types of internal cycles each of which takes from
two to eight clocks to execute, not including
possible wait states and bus arbitration times.
The common control unit (CCU) coordinates the
activities of the lOP primarily by allocating internal cycles to the various processor units; i.e., it
determines which unit will execute the next internal cycle. For example, when both channels are
active, the CCU determines which channel has
priority and lets that channel run; if the channels
have equal priority, the CCU "interleaves" their
execution (this is discussed more fully later in this
section). The CCU also initializes the processor.

Display terminals - The 8089 is well suited to
handling the DMA requirements of CRT
controllers. The lOP's transfer bandwidth is
high enough to support both alphanumeric
and graphic displays. The 8089 can assume
responsibility for refreshing the display from
memory data; in the remote configuration,
the refresh overhead can be removed from
the system bus entirely. Linked-list display
algorithms may be programmed to perform
sophisticated modes of display.

Arithmetic/Logic Unit (ALU)

Each time it performs a refresh operation,
the lOP can scan a keyboard for input and
translate the key's row-and-column format
into an ASCII or EBCDIC character. The
8089 can buffer the characters, scanning the
stream until an end-of-message character
(e.g., carriage return) is detected, and then
interrupt the CPU.

The ALU can perform unsigned binary arithmetic
on 8- and 16-bit binary numbers. Arithmetic
results may be up to 20 bits in length; Available
arithmetic instructions include addition, increment and decrement. Logical operations ("and,"
"or" and "not") may be performed on either 8or 16-bit quantities.

3-13

80891NPUT/OUTPUT PROCESSOR

TASK POINTER

1/0 CONTROL

tt

ORO 1 EXT 1 SINTR-1

1-----1ul
TASK POINTER ;J

BHE

~

1/0 CONTROL U

tt

ORO 2 EXT 2 SINTR-2

Figure 3-11. 8089 Block Diagram
During sequential execution, instructions are
fetched one word at a time from even addresses;
each fetch requires one bus cycle. This process is
shown graphically in figure 3-12. When the last
byte of an instruction falls on an even address, the
odd-addressed byte (the first byte of the following
instruction) of the fetched word is saved in the
queue. When the channel begins execution of the
next instruction, it fetches the first byte from the
queue rather than from memory. The queue,
then, keeps the processor fetching words, rather
than bytes, thereby reducing its use of the bus and
increasing throughput.

Assembly IDisassembly Registers
All data entering the chip flows through these
registers. When data is being transferred between
different width buses, the 8089 uses the
assembly/disassembly registers to effect the
transfer in the fewest possible bus cycles. In a
DMA transfer from an 8-bit peripheral to 16-bit
memory, for example, the lOP runs two bus
cycles, picking up eight bits in each cycle,
assembles a 16-bit word, and then transfers the
word to memory in a single bus cycle. (The first
and last cycles of a transfer may be performed
differently to accommodate odd-addressed
words; the lOP automatically adjusts for this
condition.)

The processor fetches bytes rather than words in
two cases. If a program transfer instruction (e.g.,
JMP or CALL) directs the processor to an
instruction .located at an odd address, the first
byte of the instruction is fetched by itself as
shown ·in figure 3-13. This is because the program
transfer invalidates the content of the queue by
changing the serial flow of execution.

Instruction Fetch Unit
This unit controls instruction fetching for the
executing channel (one channel actually runs at a
time). If the bus over which the instructions are
being fetched is eight bits wide, then the instructions are obtained one byte at a time, and each
fetch requires one bus cycle. If the instructions
are being fetched over a 16-bit bus, then the
instruction fetch unit automatically employs a 1byte queue to reduce the number of bus cycles.
Each channel has its own queue, and the activity
of one channel does not affect the other's queue.

The second case arises when an LPDI instruction
is located at an odd address. In this situation, the
six-byte LPDI instruction is fetched: byte, word,
byte, byte, byte, and the queue is not used. The
first byte of the following instruction is fetched in
one bus cycle as if it had been the target of a program transfer. Word fetching resumes with this
instructjon's second byte.

3-14

8089 INPUT/OUTPUT PROCESSOR

INSTRUCTION lOy"

INSTRUCTION "X"

_ _ _."A_ _--.\

,__--A....- -.......\

I I,

EVEN 1 000

I

EVEN, ODD

,,

I

2

I

EVEN, ODD

II

,

,

I

4

I

0

QUEUE

3

FETCH

INSTRUCTION BYTES

1

FIRST TWO BYTES OF "X"

2

THIRD BYTE OF "X" PLUS
FIRST BYTE OF "Y", WHICH IS
SAVED IN QUEUE

3

FIRST BYTE OF "Y" FROM
QUEUE-NO BUS CYCLE

4

LAST TWO BYTES OF "Y"

Figure 3-12. Sequential Instruction Fetching (16-Bit Bus)

INSTRUCTION "X"

INSTRUCTION "Y"

r..---,.,A_-........ r,..--,.,A_-........,

I I
ODD

EVEN I ODD

I

EVEN I ODD

I

EVEN I ODD

'----' '....___-', ,,"-___..J, ,'--__
2

3

LTRANSFER TARGET

FETCH

IJ

~,

4

I

I

Da"E"E

INSTRUCTION BYTES

1

FIRST ~ODD-ADDRESSED) BYTE OF "X"
(8-BIT US CYCLE)

2

SECOND AND THIRD BYTES OF "X"

3

FIRST AND SECOND BYTES OF "Y".

4

THIRD BYTE OF "Y"
PLUS FIRST BYTE OF NEXT INSTRUCTION,
WHICH IS SAVED IN QUEUE

Figure 3-13. Instruction Fetching Following a Program Transfer to an Odd Address (16-Bit Bus)
3-15

80891NPUT/OUTPUT PROCESSOR

Bus Interface Unit (BIU)

uses RQ/GT to coordinate use of the local I/O
bus with another lOP or a local CPU, if present.
System bus arbitration in the remote configuration is performed by an 8289 Bus Arbiter that
operates invisibly to the lOP. The BIU
automatically asserts the LOCK (bus lock) signal
during execution of a TSL (test and set lock)
instruction and, if specified by the channel program, can assert the LOCK signal for the duration of a DMA transfer. Section 3.5 contains a
complete discussion of bus arbitration.

The BIU runs all bus cycles, transferring instructions and data between the lOP and external
memory or peripherals. Every bus access is
associated with a register tag bit that indicates to
the BIU whether the system or I/O space is to be
addressed. The BIU outputs the type of bus cycle
(instruction fetch from I/O space, data store into
system space, etc.) on status lines SO, SI, and S2.
An 8288 Bus Controller decodes these lines and
provides signals that selectively enable one bus or
the other (see Chapter 4 for details).
The BIU further distinguishes between the
physical and logical widths of the system and I/O
buses. The physical widths of the buses are fixed
and are communicated to the BIU during
initialization. In the local configuration, both
buses must be the same width, either 8 or 16 bits
(matching the width of the hoscCPU bus). In the
remote configuration, the lOP system bus must
be the same physical width as the bus it shares
with the CPU. The width of the lOP's I/O bus,
which is local to the 8089, may be selected
independently. If any 16-bit peripherals are
located in the I/O space, then a 16-bit I/O bus
must be used. If only 8-bit devices reside on the
I/O bus, then either an 8- or a 16-bit I/O bus may
be selected. A 16-bit I/O bus has the advantage of
easy accommodation of future 16-bit devices and
fewer instruction fetches if channel programs are
placed in the I/O space.

Table 3-1. Physical/Logical Bus Combinations

Configuration

Local

System Bus
Physical:Logical

8:8
16:8/16

8:8
Remote

16:8/16
16:8/16

8:8

I/O Bus
Physical:Logical

8:8
16:8/16

8:8
16:8/16

8:8
16:8/16

Channels
Although the 8089 is a single processor, under
most circumstances it is useful to think of it as
two independent channels. A channel may perform DMA transfers and may execute channel
programs; it also may be idle. This section
describes the hardware features that support these
operations.

For a given DMA transfer, a channel program
specifies the logical width of the system and the
I/O buses; each channel specifies logical bus
widths independently. The logical width of an
8-bit physical bus can only be eight bits. A 16-bit
physical bus, however, can be used as either an 8or 16-bit logical bus. This allows both 8- and
16-bit devices to be accessed over a single 16-bit
physical bus. Table 3-1 lists the permissible
physical and logical bus widths for both locally
and remotely configured lOPs. Logical bus width
pertains to DMA transfers only. Instructions are
fetched and operands are read and written in
bytes or words depending on physical bus width.

I/O Control
Each channel contains its own I/O control section
that governs the operation of the channel during
DMA transfers. If the transfer is synchronized,
the channel waits for a signal on its DRQ (DMA
request) line before performing the next fetch"
store sequence in the transfer. If the transfer is. to
be terminated by an external signal, the channel
monitors its EXT (external terminate) line and
stops the transfer when this line goes active.
Between the fetch and store cycles (when the data
is in the lOP) the channel optionally counts,

In addition to performing transfers, the BIU is
responsible for local bus arbitration. In the local
configuration, the BIU uses the RQ/GT
(request/grant) line to obtain the bus from the
CPU and to return it after a transfer has been performed. In the remote configuration, the BIU
3-16

8089 INPUT/OUTPUT PROCESSOR

translates, and scans the data, and may terminate
the transfer based on the results of these operations. Each channel also has a SINTR (system
interrupt) line that can be activated by software to
issue an interrupt request to the CPU.

TAG
BIT

r,

19

I--i
~-I

1--1

Registers

L...J

Figure 3-14 illustrates the channel register set, and
table 3-2 summarizes the uses of each register.
Each channel has an independent set of registers;
they are not accessible to the other channel. Most
of the registers play different roles during channel
program execution than in DMA transfers. Channel programs must be careful to save these
registers in memory prior to a DMA transfer if
their values are needed following the transfer.

7

15

o

GENERAL PURPOSE A

GA

GENERAL PURPOSE B

GB

GENERAL PURPOSE C

GC

TASK POINTER

TP

PARAMETER BLOCK POINTER

PP

INDEX

IX

BYTE COUNT

BC

MASK/COMPARE

MC

CHANNEL CONTROL

CC

Figure 3-14. Channel Register Set

General Purpose A (GA). A channel program
may use GA for a general register or a base
register. A general register can be an operand of
most lOP instructions; a base register is used to
address memory operands (see section 3.8).
Before initiating a DMA transfer, the channel
program points GA to either the source or
destination address of the transfer.

General Purpose C (GC). GC may be used as a
general register or a base register during channel
program execution. If data is to be translated during a DMA transfer, then the channel program
loads GC with the address of the first byte of a
translation table before initiating the transfer. GC
is not altered by a transfer operation.

General Purpose B (G B). GB is functionally
interchangeable with GA. If GA points to the
source of a DMA transfer, then GB points to the
destination, and vice versa.

Task Pointer (TP). The CCU loads TP from the
parameter block when it starts or resumes a channel program. During program execution, the
channel automatically updates TP to point to the

Table 3-2. Channel Register Summary

Register

Size

Program
Access

System
or 1/0
Pointer

GA

20

Update

Either

General, base

Source/destination pointer

GB

20

Update

Either

General, base

Sourcejdestination pointer

GC

20

Update

Either

General, base

Translate table pointer

TP

20

Update

Either

Procedure return,
instruction pointer

Adjusted to reflect cause of
termination

Use by Channel Programs

Use in DMA Transfers

PP

20

IX

16

Update

N/A

General, auto-increment

N/A

BC

16

Update

N/A

General

Byte counter

MC

16

Update

N/A

General, masked compare

Masked compare

CC

16

Update

N/A

Restricted use recommended

Defines transfer options

Reference ,System Base

N/A

3-17

8089 INPUT/OUTPUT PROCESSOR
next instruction to be executed; i.e., TP is used as
an instruction pointer or program counter. Program transfer instructions (JMP, CALL, etc.)
update TP to cause nonsequential execution. A
procedure (subroutine) returns to the calling program by loading TP with an address previously
saved by the CALL instruction. The task pointer
is fully accessible to channel programs; it can be
used as a general register or as a base register.
Such use is not recommended, however, as it can
make programs very difficult to understand.

responding bit in the compare value. In figure
3-15, a value compared with MC will be considered equal if its low-order five bits contain the
value 00100; the upper three bits may contain any
value since they are masked out of the
comparison.
15

8 7

o

0 0 1 1 1 1 1

I

1 0100100

MASK
VALUE

COMPARE
VALUE

'---:t-~----'

Parameter Block Pointer (PP). The CCU
loads this register with the address of the
parameter block before it starts a channel program. The register cannot be altered by a channel
program, but is very useful as a base register for
accessing data in the parameter block. PP is not
used during DMA transfers.

XXX00100
MASKED
COMPARE
VALUE
(X = IGNORE VALUE OF CORRESPONOING BIT)

Figure 3-15. Mask/Compare Register

Index (IX). IX may be used as a general register
during channel program execution. It also may be
used as an index register to address memory
operands (the address of the operand is computed
by adding the content of IX to the content of a
base register). When specified as an index
register, IX may be optionally auto-incremented
as the last step in the instruction to provide a convenient means of "stepping" through arrays or
strings. IX is not used in DMA transfers.

Channel Control (CC). The content of the
channel control register governs a DMA transfer
(see figure 3-16). A channel program loads this
register with appropriate values before beginning
the transfer operation; section 3.4 covers the
encoding of each field in detail. Bit 8 (the chain
bit) of CC pertains to channel program execution
rather than to a DMA transfer. When this bit is
zero, the channel program runs at normal priority; when it is one, the priority of the program is
raised to the same level as DMA (priorities are
covered later in this section). Although a channel
program may use CC as a general register, such
use is not recommended because of the side
effects on the chain bit and thus on the priority of
the channel program. Channel programs should
restrict their use of CC to loading control values
in preparation for a DMA transfer, setting and
clearing the chain bit, and storing the register.

Byte Count (BC). BC may be used as a general
register during channel program execution. If
DMA is to be terminated when a specific number
of bytes has been transferred, BC should be
loaded with the desired byte count before
initiating the transfer. During DMA, BC is
decremented for each byte transferred, whether
byte count termination has been selected or not.
If BC reaches zero, the transfer is stopped only if
byte count termination has been specified. If byte
count termination has not been selected, BC
"wraps around" from OH to FFFFH and continues to be decremented.

Program Status Word (PSW)

Mask/Compare (MC). A channel program may
use MC for a general register. This register also
may be used in either a channel program or in a
DMA transfer to perform a masked compare of a
byte value. To use MCin this way, the program
loads a compare value in the low-order eight bits
of the register and a mask value in the upper eight
bits (see figure 3-15). A "1" in a mask bit selects
the bit in the corresponding position in the compare value; a "0" in a mask bit masks the cor-

Each channel maintains its own program status
word (PSW) as shown in figure 3-17. Channel
programs do not have access to the PSW. The
PSW records the state of the the channel so that
channel operation may be suspended and then
resumed later. When the CPU issues a "suspend"
command, the channel saves the PSW, task
pointer, and task pointer tag bit in the first four
bytes of the channel's parameter block as shown
in figure 3-18. Upon receipt of a subsequent
3-18

8089 INPUT /OUTPUT PROCESSOR

15

I

7
F
I

0

ITRI SYN I S I L I C ITSI
I

-~

-,--

TX I TBC I
I
I

TT

TMC
I I

I

L

TERMINATE ON MASKED COMPARE
TERMINATE ON BYTE COUNT
TERMINATE ON EXTERNAL SIGNAL
TERMINATE AFTER SINGLE TRANSFER
CHAINED CHANNEL PROGRAM
EXECUTION
LOCK BUS DURING TRANSFER
SOURCE/DESTINATION
SYNCHRONIZATION
TRANSLATE
FUNCTION (PORT TO PORT,
PORT TO MEMORY, ETC.)

Figure 3-16. Channel Control Register
"resume" command, the psw, TP, and. TP tag
bit are restored from the parameter block save
area and execution resumes.

7

0

1+·I·I,·I,cl 1+1
78

~~~
I L

Two conditions override the normal channel
priority mechanism. If one channel is performing
DMA (priority 1) and the channel receives a channel attention (priority 2), the channel attention is
serviced at the end of the current DMA transfer
cycle. This override prevents a synchronized
DMA transfers from "shutting out" a channel
attention. DMA terminations and chained channel programs postpone recognition of a CA on
the other channel; the CA is latched, however,
and is serviced as soon as priorities permit.

L

D.STlNAT'ONBUSLOG'CALW'DTH(O'8,1''')
SOURCE BUS LOGICAL WIDTH (0" 8, 1 " 18)
TASK BLOCK (CHANNEL PROGRAM) IN PROGRESS

INTERRUPT CONTROL (0 = DISABLED, 1 "ENABLED)

INTERRUPT SERVICE (0 = SINTRN INACTIVE 1 " SINTA N ACTIVE)
BUS LOAD LIMIT
TRANSFER IN PROGRESS

PRIORITY liT

Figure 3-17. Program Status Word

The lOP's LOCK (bus lock) signal also
supersedes channel switching. A running channel
will not relinquish control of the processor while
LOCK is active, regardless of the priorities of the
activities on the two channels. This is consistent
with the purpose of the LOCK signal: to
guarantee exclusive access to a shared resource in
a multiprocessing system. Refer to sections 3.5
and 3.7 for futher information on the LOCK
signal and the TSL instruction.

8 7

15

TP 15-8
psw

I
I

TP7·0
TP 19-1sl TAG

_PP

I

0 0 0

-

PP + 2

REMAINDER OF PARAMETER BLOCK

I

I

L _______ ----------~

Tag Bits

Registers GA, GB, GC, and TP are called pointer
registers because they may be used to access, or

Figure 3-18. Channel State Save Area
3-19

8089 INPUT/OUTPUT PROCESSOR

each internal cycle, the CCU lets one channel or
the other execute the next internal cycle. No extra
overhead is incurred by this channel switching.
The basis for making the determination is a
priority mechanism built i.nto the lOP. This
mechanism recognizes that some kinds of
activities (e.g., DMA) are more important than
others. Each activity that a channel can perform
has a priority that reflects its relative importance
(see table 3-3).

point to, addresses in either the system space or
the 110 space. The pointer registers may address
either memory or 110 devices (lOP instructions
do not distinguish between memory and 110
devices since the latter are memory-mapped). The
tag bit associated with each register (figure 3-14)
determines whether the register points to an
address in the system space (tag=O) or the 110
space (tag= 1) .
The CCU sets or clears TP's tag bit depending on
whether the command it receives from the CPU is
"start channel program in system space," or
"start channel program in 110 space." Channel
programs alter the tag bits of GA, GB, GC, and
TP by using different instructions for loading the
registers. Briefly, a "load pointer" instruction
clears a tag bit, a "move" instruction sets a tag
bit, and a "move pointer" instruction moves a
memory value (either 0 or 1) to a tag bit. Section
3.9 covers these instructions in detail.

Concurrent Channel Operation

Two new activities are introduced in table 3-3.
When a DMA transfer terminates, the channel
executes a short internal channel program. This
DMA termination program adjusts TP so that the
user's program resumes at the instruction
specified when the transfer was setup (this is
discussed in detail in section 3.4). Similarly, when
a channel attention is recognized, the channel
executes an internal program that examines the
CCW and carries out its command. Both cif these
programs consist of standard 8089 instructions
that are fetched from internal ROM. Intel
Application Note AP-50, Debugging Strategies
and Considerations for 8089 Systems, lists the
instructions in these programs. Users monitoring
the bus during debugging may see operands read
or written by the termination or channel attention
programs. The instructions themselves, however,
wlll not appear on the bus as they are resident in
the chip.

Both channels may be active concurrently, but
only one can actually run at a time. At the end of

Notice also that, according to table 3-3, a channel
program may run at priority 3 or at priority 1.

If a register points to the system space, .all 20 bits
are placed on the address lines to allow the full
megabyte to be directly addressed. If a register
points to the I/O space, the upper four bits of the
address lines are undefined; the lower 16 bits are
sufficient to access any location in the 64k byte
110 space.

Table 3-3. Channel Priorities and Interleave Boundaries

Channel Activity

Priority
(1 = highest)

Interleave. Boundary
By Instruction

ByOMA

DMA transfer

1

Bus cycle!

Bus cycle!

DMA termination sequence

1

Internal cycle

None

Channel program (chained)

1

Internal cycle 2

Instruction

Channel attention sequence

2

Internal cycle

None

Channel program (not chained)

3

Internal cycle 2

Instruction

Idle

4

Two clocks

Two clocks

!DMA is not interleaved while Lc5Ci< is active.
2Except TSL instruction; see section 3.7.

3-20

8089 INPUT/OUTPUT PROCESSOR

Channel program priority is determined by the
chain bit in the channel control register. If this bit
is cleared, the program runs at normal priority
(3); if it is set, the program is said to be chained,
and it runs at the same priority as DMA. Thus,
the chain bit provides a way to raise the priority
of a critical channel program.

instruction boundaries: a program on channel B
will not run until channel A reaches the end of an
instruction. Note that a DMA termination
sequence or channel attention sequence on channel A cannot be interleaved by instructions on
channel B, regardless of channel B's priority.
These internal programs are short, however, and
will not delay channel B for long (see Chapter 4
for timing information).

The CCU lets the channel with the highest priority
run. If both channels are running activities with
the same priority, the CCU examines the priority
bits in the PSWs. If the priority bits are unequal,
the channel with the higher value (1) runs. Thus,
the priority bit serves as a "tie breaker" when the
channels are otherwise at the same priority level.
The value of the priority bit in the PSW is loaded
from a corresponding bit in the CCW; therefore,
the CPU can control which channel will run when
the channels are at the same priority level. The
priority bit has no effect when the channel
priorities are different. If both channels are at the
same priority level and if both priority bits are
equal, the channels run alternately without any
additional overhead.

Table 3-4 summarizes the channel switching
mechanism with several examples. It is important
to remember that channel switching occurs only
when both channels are ready to run. In typical
applications, one of the channels will be idle
much of the time, either because it is waiting to be
dispatched by the CPU or because it is waiting for
a DMA request in a synchronized transfer. (During a synchronized transfer, the channel is idle
between DMA requests; for many peripherals, the
channel will spend much more time idling than
executing DMA cycles.) The real potential for one
channel "shutting out" a priority 1 activity on the
other channel is largely limited to un synchronized
DMA transfers and locked transfers (synchronized or unsynchronized). Long, chained channel
programs and high-speed synchronized DMA will
slow a priority I activity on the other channel, but
will not shut it out because the channels will alternate (assuming their priority bits are equal). A
chained channel program will shut out any lower
priority activity on the other channel, including a
channel attention. (The channel attention is
latched by the lOP, however, so it will execute
when the other channel drops to a lower priority.)
Chained channel programs should therefore be
used with discretion and should be made as short
as possible.

The CCU switches channels only at certain points
called interleave boundaries; these vary according
to the type of activity running in each channel and
are shown in table 3-3. In table 3-3 and in the
following .discussion, the terms "channel A" and
"channel B" are used to identify two active channels that are bidding for control of an lOP.
"Channel A" is the channel that last ran and will
run again unless the CCU switches to "channel
B." Where the CCU switches from one channel
(channel A) to another (channel B) depends on
whether channel B is performing DMA or is
executing instructions. For this determination,
instructions in the internal ROM are considered
the same as instructions executed in user-written
channel programs (chained or not chained). Table
3-3 shows that a switch from channel A to channel B will occur sooner if channel B is running
DMA. DMA, then, interleaves instruction execution at internal cycle boundaries. Since instructions are often composed of several internal
cycles, instruction execution on channel A can be
suspended by DMA on channel B (when channel
A next runs, the instruction is resumed from the
point of suspension). DMA on channel A is
interleaved by DMA on channel B after any bus
cycle (when channel A runs again, the DMA
transfer sequence is resumed from the point of
suspension). If both channels are executing programs, the interleave boundaries are extended to

3.3 Memory
The 8089 can access memory components located
in two different address spaces. The system space,
which coincides with the CPU's memory space,
may contain up to 1,048,576 bytes. The 1/0
space, which may either coincide with the CPU's
lIO space or be local (private) to the lOP, may
contain up to 65,536 bytes. Memory components
in the system space should respond to the memory
read and write commands issued by the 8288 Bus
Controller. Memory components in the 1/0 space
must respond to 8288 lIO read and write commands. Memory in either space may be
3-21

8089 INPUT /OUTPUT PROCESSOR

Table 3-4. Channel Switching Examples

ChannelA (Ran Last)

ChannelB
Result

Activity

Chain
Bit

Priority
LOCK
Bit

Activity

Chain
Bit

Priority
Bit

DMA transfer
DMA transfer

X
X

X
X

Inactive
Inactive

Idle
Channel attention

X
X

X
X

Channel program
Channel program

X
X

0
0

Inactive
Inactive

Channel program
Channel program

X
X

0

Channel program
DMA transfer

1
X

X
1

Inactive
Inactive

Channel program
Channel program

1

X
1

Channel attention

X

X

Inactive

Channel program

1

X

DMA transfer
Channel program
(TSL instruction)

X

X
X

Active
Active

Channel attention
DMA transfer

X
X

X
X

0

A runs.
A runs until end of current
transfer cycle; then Bruns.
Bruns.
A and B alternate by
instruction.
A runs.
B runs one bus or internal
cycle following each bus cycle
run by A.'
A runs if it has started the
sequence; otherwise Bruns.
A runs until DMA terminates.
A completes TSL instruction,
LOCK goes inactive and B
runs.

1

0

'If transfer is synchronized, B also runs when A goes idle between transfer cycles.

implemented like 8086 memory (l6-bit words split
into even- and odd-addressed 8-bit banks) or 8088
memory (a single 8-bit bank). See Chapter 4 for
physical implementation considerations.

LOW MEMORY
OOOOOH
SYSTEM
SPACE

I.
7

HIGH MEMORY
00001H

00002H

§ SFFFFEH FFFFFH

111111111111111111111 § 51' 11111", IIIII
07

I..

07

07

LOW MEMORY

Storage Organization

HIGH MEMORY

OOOOH ,0001H
I/O
SPACE

From a software point of view, both 8089
memory spaces are organized as unsegmented
arrays of individually addressable 8-bit bytes
(figure 3-19). Instructions and data may be stored
at any address without regard for alignment
(figure 3-20).

I. J
7

1111

I..

0

-I

1 MEGABYTE

07

0002H

§

fFFFEH

FFFFH.

11111111111111 § SklllllllllIl'
07

07

64K BYTES

II
0

-I

Figure 3-19. Storage Organization

The lOP views the system space differently from
the 8086 or 8088 with which it typically shares the
space. The 8086 and 8088 differentiate between a
location's logical (segment and offset) address
and its physical (20-bit) address.
The 8089 does not "see" the logically segmented
structure of the memory space; it uses its 20-bit
pointer registers to access all locations in the
system space by their physical addresses. Memory
in the 8089 110 space is treated similarly except
that only 16 bits are needed to address any
location.

lAH lBH

lCH lDH

lEH lFH

20H

21H

Figure 3-20. Instruction and Variable Storage
3-22

8089 INPUT /OUTPUT PROCESSOR

Following Intel convention, word data is stored
with the most-significant byte in the higher
address (see figure 3-21). The 8089 recognizes the
doubleword pointer variable used by the 8086 and
8088 (figure 3-22). The lower-addressed word of
the pointer contains an offset value, and the
higher-addressed word contains a segment base
address. Each word is stored conventionally, with
the higher-addressed byte containing the mostsignificant eight bits of the word. The 8089 can
convert a doubleword pointer into a 20-bit
physical address when it is loaded into a pointer
register to address system memory. A special 3byte variable, called a physical address pointer
(figure 3-23), is used to save and restore pointer
registers and their associated tag bits.

ware and software products; the locations are OH
through 7FH (128 bytes) and FFFFOH through
FFFFFH (16 bytes), as shown in figure 3-24. The
low addresses are used for part of the 8086/8088
interrupt pointer table. Locations FFFFOHFFFFBH are used for 8086, 8088 and 8089 startup
sequences; the remaining locations are reserved
by Intel.
If an lOP is configured locally, its 1/0 space coincides with the CPU's 110 space, and it must
respect the reserved addresses F8H-FFH. The
entire 1/0 space of a remotely-configured lOP
may be used without restriction.

Using any dedicated or reserved addresses may
inhibit the compatibility of a system with current
or future Intel hardware and software products.

Dedicated and Reserved Memory
Locations

Dynamic Relocation

The extreme low and high addresses of the system
space are dedicated to specific processor functions or are reserved for use by other Intel hard-

The 8089 is very well-suited to environments in
which programs do not occupy static memory
locations, but are moved about during execution.
Dynamic code relocation allows systems to make
efficient use of limited memory resources by
transferring programs between external storage
and memory, and by combining scattered free
areas of memory into larger, more useful, continuous spaces.
lOP channel programs are inherently positionindependent, the only restriction being that channel programs that transfer to each other or
share data must be moved as a unit. Since the lOP

VALUE OF WORD STORED AT 724H: 5502H

Figure 3-21. Storage of Word Variables

VALUE OF DOUBLEWORD POINTER STORED AT 4H:
SEGMENT BASE ADDRESS: 3B4CH
OFFSET:65H

Figure 3-22. Storage of Doubleword Pointer Variables
3-23

8089 INPUT IOUTPUT PROCESSOR

FFFFFH
POINTER
REGISTER

RESERVED
FFFFCH
FFFFBH

19

DEDICATED
FFFFOH
FFFEFH

"r
101H

I

OPEN

102H

r

HEX

OPEN

r'

80H
7FH

MEMORY
BINARY

RESERVED
14H
13H

VALUE OF PHYSICAL ADDRESS POINTER AT 100H:
ADDRESS: 265F3H
TAG: 0

RESERVED

DEDICATED

OPEN
OH

SYSTEM SPACE

Figure 3-23. Storage of Physical Address
Pointer Variables

100H
FFH
F8H
F7H
OH

I/O SPACE
(LOCAL CONFIGURATION ONLY)

Figure 3-24. Reserved Memory Locations
register are used for I/O space locations; all 20
bits are used for system space addresses. Different
types of memory accesses use base registers as
shown in table 3-5. The 8089 addressing modes
allow the base address of a memory operand to be
modified by other registers and constant values to
yield the effective address of the operand (see section 3.8).

receives the address of a channel program and its
associated parameter block when it is dispatched
by the CPU, the location of these blocks is
immaterial and can change from one dispatch to
the next. (Note, however, that the channel control
block cannot be moved without reinitializing the
lOP.) Typically, then, the CPU would direct the
movement of lOP channel programs and
parameter blocks. These blocks, of course, cannot be moved while they are in use.

Notice that table 3-5 indicates that memory
operands may be addressed using register PP in
addition to GA, GB, and GC. PP is maintained
by the lOP and can neither be read nor written by
a channel program; it can be used, however, to
access data in the parameter block. PP has no
associated tag bit; a reference to it implies the
system space, where a parameter block always
resides.

While the CPU may be in charge of relocation,
the lOP is an excellent vehicle for performing the
actual transfer of channel programs, parameter
blocks, and CPU programs as well. A very simple
channel program can transfer code between
memory locations by DMA much faster than the
equivalent CPU instructions, and transfers
between disk and memory also can be performed
more efficiently.

Table 3-5. Base Register Use in Memory Access
Base Register

Memory Access

Memory Access
Instruction Fetch
DMASource
DMA Destination
DMA Translate Table
Memory Operand

Memory accesses are always performed using a
pointer register and its associated tag bit. The tag
bit indicates whether the access is to the system
space (tag=O) or the I/O space (tag=I). The
pointer register contains the base address of the
location; i.e., the pointer register is used as a base
register. Only the low-order 16 bits of the pointer

TP
GAorGBI
GAorGBI
GC
GA or GB or GC or PP'

lAs specified in CC register
'As specified in instruction

3-24

8089 INPUT /OUTPUT PROCESSOR

The lOP is told the physical widths of the system
and 110 buses when it is initialized. If a bus is
eight bits wide, the lOP accesses memory on this
bus like an 8088. Instruction fetches and operand
reads and writes are performed one byte at a time;
one bus cycle is run for each memory access.
Word operands are accessed in two cycles, completely transparent to software. Instruction
fetches are made as needed, and the instruction
stream is not queued.

into a given address is actually memory or I/O is
immaterial. All addresses in both the system and
I/O spaces are equally accessible, and transfers
may be made between the two spaces as well as
within either address space.

Programmed I/O
A channel program performs 110 similar to the
way a CPU communicates with memory-mapped
I/O devices. Memory reference instructions perform the transfer rather than "dedicated" 110
instructions, such as the 8086/8088 IN and OUT
instructions. Programmed I/O is typically used to
prepare a device controller for a DMA transfer
and to obtain status/result information from the
controller following termination of the transfer.
It may be used, however, with any device whose
transfer rate does not require DMA.

The lOP accesses memory on a 16-bit bus like an
8086. As mentioned in the previous section, the
instruction stream is generally fetched in words
from even addresses with the second byte held in
the one-byte queue. If a word operand is aligned
(i.e., located at an even address), the 8089 will
access it in a single 16-bit bus cycle. If a word
operand is unaligned (i.e., located at an odd
address), the word will be accessed in two consecutive 8-bit bus cycles. Byte operands are
always accessed in 8-bit bus cycles.

I/O Instructions

For memory on 16-bit buses, performance is
improved and bus contention is reduced if word
operands are stored at even addresses. The
instruction queue tends to reduce the effect of
alignment on instructions fetched on a 16-bit bus,
In tight loops, performance can be increased by
word-aligning transfer targets.

Since the 8089 does not distinguish between
memory components and 110 devices, any
instruction that accepts a byte or word memory
operand can be used to access an I/O device.
Most memory reference instructions take a source
operand or a destination operand, or both. The
instructions generally obtain data from the source
operand, operate on the data, and then place the
result of the operation in the destination operand.
Therefore, when a source operand refers to an
address where an 110 device is located, data is
input from the device. Similarly, when a destination operand refers to an I/O device address, data
is output to the device.

Notice that the correct operation of a program is
completely independent of memory bus width. A
channel program written for one system that uses
an 8-bit memory bus will execute without
modification if the bus is increased to 16 bits. It is
good practice, though, to write all programs as
though they are to run on 16-bit systems;).e., to
align word operands. Such programs will then
make optimal use of the bus in whatever system
they are run.

Most I/O device controllers have one or more
internal registers that accept commands and
supply status or result information. Working with
these registers typically involves:

3.4 Input/Output
• reading or writing the entire register;
• setting or clearing some bits in a register while
leaving others alone; or
• testing a single bit in a register.

The 8089 combines the programmed I/O
capabilities of a CPU with the high-speed block
transfer facility of a DMA controller. It also provides additional features (e.g.; compare and
translate during DMA) and is more flexible than a
typical CPU or DMA controller. The 8089
transfers data from a source address to a destination address. Whether the component mapped

Table 3-6 shows some of the 8089 instructions
that are useful for performing these kinds of
operations. Sectien 3.7 covers the 8089 instruction set in detail.

3-25

8089 INPUT/OUTPUT PROCESSOR

with the corresponding address spaces of the
other 8086 family processors.

Table 3-6. Memory Reference Instructions
Used for I/O
Instruction

Effect on I/O Device

I/O Bus Transfers

MOV/MOVB Read or write word / byte
AND/ANDB

Clear multiple bits in word/byte

OR/ORB

Set multiple bits in word/byte

CLR

Clear' single bit (in byte)

SET

Set single bit (in byte)

JBT

Read (byte) and jump if
single bit =1

JNBT

Read (byte) and jump if
single bit =0

Table 3-7 shows the number of bus cycles the lOP
runs for all combinations of bus size, transfer size
(byte or word), and transfer address (even or
odd). Bus width refers to the physical bus
implementation; the instr.uction mnemonic determines whether a byte or a word is transferred.
Both 8- and 16-bit devices may reside on a 16-bit
bus. All 16-bit devices should be located at even
addresses so that transfers will be performed in
one bus cycle. The 8-bit devices on a 16-bit bus
may be located at odd or even addresses. The
internal registers in an 8-bit device on a 16-bit bus
must be assigned all-odd or all-even addresses
that are two bytes apart (e.g., IH, 3H, 5H, or 2H,
4H, 6H). All 8-bit peripherals should be referenced with byte instructions, and 16-bit devices
should be referenced with word instructions.
Odd-addressed 8-bit devices must be able to
transfer data on the upper eight bits of the 16-bit
physical data bus.

Device Addressing

Since memory reference instructions are used to
perform programmed I/O, device addressing. is
very similar to memory addressing. An operand
that refers to an I/O device always specifies one
of the pointer registers GA, GB, or GC (PP is
legal, but an 110 device would not normally be
mapped into a parameter block). The base
address of the device is taken from the specified
pointer register. Any of the memory addressing
modes (see section 3.8) may be used to modify the
base address to produce the effective (actual)
address of the device. The pointer register's tag
bit locates the device in the system space (tag=O)
or in the 110 space (tag=I). If the device is in
the I/O space, only the low-order 16 bits of the
pointer register are used for the base address; all
20 bits are used for a system space address. The
lOP's system and I/O spaces are fully compatible

Only 8-bit devices should be connected to an 8-bit
bus, and these should only be referenced with
byte instructions. An 8-bit device on an 8-bit bus
may be located at an odd or even address, and its
internal registers may be assigned consecutive
addresses (e.g., IH, 2H, 3H). Assigning all-odd
or all-even addresses, however, will simplify conversion to a 16-bit bus at a later date.

Table 3-7. Programmed I/O Bus Transfers
Bus Width:

8

Instruction:
Device Address:
Bus Cycles:

16

byte

word'

word

even

odd

even

odd

even

odd

even

odd'

1

1

2

2

1.

1

1

2

, not normally used

Mnemonics © Intel, 1979

byte

3-26

8089 INPUT/OUTPUT PROCESSOR

parameters. If this type of controller is being
used, the chanpel program instruction that sepds
the last parameter should follow the 8089 XFER
instruction. (The XFER instruction places the
channel in DMA mode after the next instruction;
this is explained in more detail later in this
section.)

DMA Transfers
In addition to byte- and word-oriented programmed 110, the 8089 can transfer blocks of
data by direct memory access. A block may be
transferred between any two addresses; memoryto-memory transfers are performed as easily as
memory-to-port, port-to-memory or port-to-port
exchanges. There is no limitation on the size of
the block that can be transferred except that the
block cannot exceed 64k bytes if byte count termination is used. A channel program typically
prepares for a DMA transfer by writing commands to a device controller and initializing channel registers that are used during the transfer. No
instructions are executed during the transfer,
however, and very high throughput speeds can be
achieved.

Preparing the Channel

For a channel to perform a DMA transfer, it must
be provided with information that describes the
operation. The channel program provides this
information by loading values into channel
registers and, in one case, by executing a special
instruction (see table 3-8).

Preparing the Device Controller

Source and Destination Pointers. One
register is loaded to point to the transfer source;
the other points to the destination. A bit in the
channel control register is set to indicate which
register is the source pointer. If a register is
pointed at a memory location, it should contain
the address where the transfer is to begin - i.e.,
the lowest address in the buffer. The channel
automatically increments a memory pointer as the
transfer proceeds. If the tag bit selects the lIO
space, the upper four bits of the register are
ignored; if the tag selects the system space, all 20
bits are used. The source and destination may be
located in the same or in different address spaces.

Most controllers that can peform DMA transfers
are quite flexible in that they can perform several
different types of operations. For example, an
8271 Floppy Disk Controller can read a sector,
write a sector, seek to track 0, etc. The controller
typically has one or more internal registers that
are "programmed" to perform a given operation.
Often, certain registers will contain status
information that can be read to determine if the
controller is busy, if it has detected an error, etc.
An 8089 channel program views these device
registers as a series of memory locations. The
channel program typically places the device's base
address in a pointer register and uses programmed
lIO to communicate with the registers.

Translate Table Pointer. If the data is to be
translated as it is transferred, GC should be
pointed at the first (lowest-addressed) byte in a
256-byte translation table. The table may be
10Gated in either the system or lIO space, and GC

Some controllers start a DMA transfer
immediately upon receiving the last of a series of

Table 3-8. DMA Transfer Control Information
Information

Source Pointer
Destination Pointer
Translate Table Pointer
Byte Count
Mask/Compare Values
Logical Bus Width
Channel Control

Register or Instruction

Required or Optional

GAorGB
GAorGB
GC
BC
MC
WID
CC

Required
Required
Optional
Optional
Optional
Optional*
Required

*Must be executed once following processor RESET.

3-27

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

ference between BC's value before and after the
transfer does not accurately reflect the number of
bytes transferred to the destination.

should be loaded by an instruction that sets or
clears its tag bit as appropriate. The translate
operation is. only defined for byte data; source
and destination logical bus widths must both be
set to eight bits.

Mask/Compare Values. If the transfer is to be
terminated when a byte (possibly translated) is
found equal or unequal to a search value, MC
should be loaded as described in section 3.2. MC
is not altered during the transfer. Normally, the
logical destination bus width is set to eight bits
when transferred data is being compared. If the
logical destination width is 16 bits, only the loworder byte of each word is compared.

The channel translates a byte by treating it as an
unsigned 8-bit binary number. This number is
added to the content of register GC to form a
memory address; GC is not altered by the operation. If GC points to the lIO space, its upper four
bits are ignored in the operation. The byte at this
address (which is in the translate table) is then
fetched from memory, replacing the source byte.
Figure 3-25 illustrates the translate process.

Logical Bus Width. The 8089 WID (logical bus
width) instruction is used to set the logical width
of the source and destination buses for a DMA
transfer. Any bus whose physical width is eight
bits can only have a logical width of eight bits. A
16-bit physical bus, however, can have a logical
width of 8 or 16 bits; i.e., it can be used as either
an 8-bit or 16-bit bus in any given transfer.
Logical bus widths are set independently for each
channel.

Byte Count. If the transfer is to be terminated
on byte count- i.e., after a specific number of
bytes have been transferred-the desired count
should be loaded into register BC as an unsigned
16-bit number. The channel decrements BC as the
transfer proceeds, whether or not byte count termination has been specified. There are cases
(discussed later in this section) where the dif-

TRANSLATE TABLE
IN SYSTEM OR I/O SPACE

00200

1--,)

3F

GC

+

=

166119
•

B

:
I

SOURCE BYTE

00202

4C

~ ______ J

TRANSLATE ADDRESS

TO DESTINATION
TRANSLATED BYTE

Figure 3-25. Translate Operation
Mnemonics © Intel, 1979

3-28

87

1(

8089 INPUT /OUTPUT PROCESSOR

ability to execute a synchronized transfer: in
effect, the peripheral synchronizes the transfer
through the use of wait states. Chapter 4 discusses
synchronization in more detail.

For a transfer to or from an 110 device on a
16-bit physical bus, the logical bus width should
be set equal to the peripheral's width; i.e., 8 or 16
bits. Transfers to or from 16-bit memory will run
at maximum speed if the logical bus width is set to
16 since the channel will fetch/store words. In the
following cases, however, the logical width
should be set to 8:
•
the data is being translated,
•
the data is being compared under mask, and
the 16-bit memory is the destination of the
transfer.

Source synchronization is typically selected when
the source is an 110 device and the destination is
memory. The 110 device starts the next transfer
cycle by activating the channel's DRQ (DMA
request) line. The channel then runs one transfer
cycle and waits for the next DRQ.
Destination synchronization is most often used
when the source is memory and the destination is
an 110 device. Again, the 110 device controls the
transfer frequency by signaling on DRQ when it is
ready to receive the next byte or word.

The WID instruction sets both logical widths and
remains in effect until another WID instruction is
executed. Following processor reset, the settings
of the logical bus widths are unpredictable.
Therefore, the WID instruction must be executed
before the first DMA transfer.

The source field (bit 10) identifies register GA or
GB as the source pointer (and the other as the
destination pointer).

Channel Control. The 16 bits of the CC register
are divided into 10 fields that specify how the
DMA transfer is to be executed (see figure 3-26).
A channel program typically sets these fields by
loading a word into the register.

The lock field (bit 9) may be used to instruct the
channel to assert the processor's bus lock (LOCK)
signal during the transfer. In a sourcesynchronized transfer, LOCK is active from the
time the first DMA request is received until the
channel enters the termination sequence. In a
destination-synchronized transfer LOCK is active
from the first fetch (which precedes the first
DMA request) until the channel enters the termination sequence.

The function field (bits 15-14) identifies the
source and destination as memory or ports (110
devices). During the transfer, the channel
increments source/destination pointer registers
that refer to memory so that the data will be
placed in successive locations. Pointers that refer
to I/O devices remain constant throughout the
transfer.

The chain field (bit 8) is not used during the
transfer. As discussed previously, setting this
bit raises channel program execution to priority
level 1.

The translate field (bit 13) controls data translation. If it is set, each incoming byte is translated
using the table pointed to by register GC.
Translate is defined only for byte transfers; the
destination bus must have a logical width of eight.

The terminate on single transfer field (bit 7) can
be used to cause the chaimel to run one complete
transfer cycle only-i.e., to transfer one byte or
word and immediately resume channel program
execution. When single transfer is specified, any
other termination conditions are ignored. Single
transfer termination can be used with low-speed
devices, such as keyboards and communication
lines, to translate and/or compare one byte as it
transferred.

The synchronization field (bits 12-11) specifies
how the transfer is to be synchronized.
Unsynchronized ("free running") transfers are
typically used in memory-to-memory moves. The
channel begins the next transfer cycle immediately
upon completion of the current cycle (assuming it
has the bus). Slow memories, which cannot run as
fast as the channel, can extend bus cycles by
signaling "not ready" to the 8284 Clock
Generator, which will insert wait states into the
bus cycle. A similar technique may be used with
peripherals whose speed exceeds the channel's

The three low-order fields in register CC instruct
the channel when to terminate the transfer,
assuming that single transfer has not been
selected. Three termination conditions may be
specified singly or in combination.

3-29

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

15

7

If

ITRI

STN I SI L I C ITSI

0
Tf

IT~C I

F
00
01
10
11

FUNCTION
PORT TO PORT
MEMORY TO PORT
PORT TO MEMORY
MEMORYTO MEMORY

TR

o
1

TRANSLATE
NO TRANSLATE
TRANSLATE

SYN
00
01
10
11

SYNCHRONIZATION
NO SYNCHRONIZATION
SYNCHRONIZE ON SOURCE
SYNCHRONIZE ON DESTINATION
RESERVED BY INTEL

S

SOURCE
GA POINTS TO SOURCE
GB POINTS TO SOURCE

o
1

o

L
1

LOCK
NO LOCK
ACTUATE LOCK DURING TRANSFER

C

~

1

NO CHAINING
CHAINED: RAISE TB TO PRIORITY 1

o
TS

TMC

o
1

TERMINATE ON SINGLE TRANSFER
NO·SINGLE TRANSFER TERMINATION
TERMINATE AFTER SINGLE TRANSFER

TX
00
01
10
11

TERMINATE ON EXTERNAL SIGNAL
NO EXTERNAL TERMINATION
TERMINATE ON EXT ACTIVE; OFFSET = 0
TERMINATE ON EXT ACTIVE; OFFSET = 4
TERMINATE ON EXT ACTIVE; OFFSET = 8

TBC TERMINATE ON BYTE COUNT
NO BYTE COUNT TERMINATION
01
TERMINATE ON BC 0; OFFSET 0
10
TERMINATE ON BC 0; OFFSET 4
11
TERMINATE ON BC = 0; OFFSET = 8

00

TMC
000
001
010
011
100
101
110
111

=
=

=
=

TERMINATE ON MASKED COMPARE
NO MASK/COMPARE TERMINATION
TERMINATE ON MATCH; OFFSET = 0
TERMINATE ON MATCH; OFFSET = 4
TERMINATE ON MATCH; OFFSET = 8
(NO EFFECT)
TERMINATE ON NON-MATCH; OFFSET = 0
TERMINATE ON NON-MATCH; OFFSET = 4
TERMINATE ON NON-MATCH; OFFSET = 8

Figure 3-26. Channel Control Register Fields
3-30

I

80891NPUT/OUTPUT PROCESSOR

External termination allows an 1/0 device
(typically, the one that is synchronizing the
transfer) to stop the transfer by activating the
channel's EXT (external terminate) line. If byte
count termination is selected, the channel will
stop when BC=O. If masked compare termination
is specified, the channel will stop the transfer
when a byte is found that is equal or unequal (two
options are available) to the low-order byte in MC
as masked by MC's high-order byte. The byte that
stops the termination is transferred. If translate
has been specified, the translated byte is
compared.

-(COULD IE A DIFFERENT INSTRUCTION)

(TP

PO~IN::TS-=TO!l'~.T~U~MP~'N~.~T"~UC~TI~ONd)

_

UMP OFFSET_O_CODE

}

L_~~L~JM~P~OF~FS~ET~_4~_~CO~D~E]

When a DMA transfer ends, the channel adds a
value called the termination offset to the task
pointer and resumes channel program execution
at that point in the program. The termination offset may assunie a value of 0, 4, or 8. Single
transfer termination always results in a termination offset of O. Figure 3-27 shows how the termination offsets can be used as indices into a
three-element "jump table" that identifies the
condition that caused the termination.

TP+8

THREE·ELEMENTJUMPTAILE

LJMP OFFSET_I_CODE

l
T

OFFSET _o_coDE:

EXECUTED IF TERMINATION

OFFSET _4_ cODE

......_ ,

OFFSET_O

l

1
T

1

T IX!cUTg~r.lf'!.M~NATIONT

OFFSET ••LCODE'l

T

1

IXECUTED IFTERMINATION
OFFIET.I

As an example of using the jump table, consider a
case in which a transfer is to terminate when 80
bytes have been transferred or a linefeed
character is detected, whichever occurs first. The
program would load 80H into BC and OOOAH
into MC (ASCII line feed, no bits masked). The
channel program could assign byte count termination an offset of 0 and masked compare termination an offset of 4. If the transfer is terminated by
byte count (no linefeed is found), the instruction
at location TP + 0 will be executed first after the
termination. If the linefeed is found before the
byte count ,expires, the instruction at TP + 4 will
be executed first. The LJMP (long unconditional
jump, see section 3.7) instruction is four bytes
long and can be placed at TP + 0 and TP + 4 to
cause the channel program to jump to a different
routine, depending on how the transfer
terminates.

T

Figure 3-27. Termination Jump Table

the preceding example, this would occur if the
80th character were a linefeed. When mUltiple terminations occur simultaneously, the channel
indicates that termination resulted from the condition with the largest offset value. In the
preceding example, if byte count and search termination occur at the same time, the channel program resumes at TP + 4.

Beginning the Transfer
The 8089 XFER (transfer) instruction puts the
channel into DMA transfer mode after the
following instruction has been executed. This
technique gives the channel time to set itself up
when it is used with device controllers, such as the
8271 Floppy Disk Controller, that begin transferring immediately upon receipt of the last in a
series of parameters or commands. If the transfer
is to or from such a device, the last parameter
should be sent to the device after the XFER
instruction. If this type of device is not being
used, the instruction following XFER would

If the transfer can only terminate in one way and

that condition is assigned an offset of 0, there is
no need for the jump table. Code which is to be
unconditionally executed when the transfer ends
can imniediately follow the instruction after
XFER. This is also the case when single transfer is
specified (execution always resumes at TP + 0).
It is possible, however, for two, or even three"ter-

mination conditions to arise at the same time. In

3-31

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

Table 3-9. DMA Transfer
AssemblyIDisassembly

typically send a "start" command to the controller. If a memory-to-memory transfer is being
made, any instruction may follow XFER except
one that alters GA, GB, or CC. The HL T instruction should normally not be coded after the
XFER; doing so clears the channel's BUSY flag,
but allows the DMA transfer to proceed.

Address
(SourceDestination)
EVEN-EVEN
EVEN-ODD
ODD-EVEN
ODD-ODD

DMA Transfer Cycle
A DMA transfer cycle is illustrated in figure 3-28;
a complete transfer is a series of these cycles run
until a termination condition is encountered. The
figure is deliberately simplified to explain the
general operation of a DMA transfer; in particular, the updating of the source and destination
pointers (GA and GB) can be more complex than
the figure indicates. Notice that it is possible to
start an unending transfer by not specifying a termination condition in CC or by specifying a condition that never occurs; it is the programmer's
responsibility to ensure that the transfer eventually stops.

B-B
B-B
B-B
B-B

B/B-W
B-B
B/B-W
B-B

W-B/B
W-B/B
B-B
B-B

W-W
W-B/B
B/B-W
B-B

B= Byte Fetched or Stored in 1 Bus Cycle
W= Word Fetched or Stored in 1 Bus Cycle
B/B= 2 Bytes Fetched or Stored in 2 Bus Cycles

type of synchronization may be specified for a
given transfer), the channel waits for DRQ before
running a store cycle. It stores a word or the
lower-addressed byte (which may be the only byte
or the first of two bytes). Table 3-9 shows the
possible combinations of even/odd addresses and
logical bus widths that define the store cycle.
Whenever stores are to memory on a 16-bit logical
bus, the channel stores words, except that bytes
may be stored on the first and last cycles.

If the transfer is source-synchronized, the channel
waits until the synchronizing device activates the
channel's DRQ line. The other channel is free to
run during this idle period. The channel fetches a
byte or a word, depending on the source address
(contained in GA or GB) and the logical bus
width. Table 3-9 shows how a channel performs
the fetch/store sequence for all combinations of
addresses and bus widths. If the destination is on
a 16-bit logical bus and the source is on an 8-bit
logical bus, and the transfer is to an even address,
the channel fetches a second byte and assembles a
word internally. During each fetch, the channel
decrements BC according to whether a byte or
word is obtained. Thus BC always indicates the
number of bytes fetched.

The channel samples EXT again after the first
store cycle and, if it is active, the channel prevents
the second store cycle from running. If specified
in the CC register, the low-order byte is compared
to the value in Me. A "hit" on the comparison
(equal or unequal, as indicated in CC) also
prevents the second of two scheduled store cycles
from running. In both of these cases, one byte has
been "overfetched," and this is reflected in BC's
value. It would be unusual, however, for a synchronizing device to issue EXT in the midst of a
DMA cycle. Note also that EXT is valid only
when DRQ is inactive. Chapter 4 covers the timing requirements for these two signals in detail.

The channel samples its EXT line after every bus
cycle in the transfer. If EXT is recognized after
the first of two scheduled fetches, the second
fetch is not run. After the fetch sequence has been
completed, the channel translates the data if this
option is specified in CC.

GA and GB are updated next. Only memory
pointers are incremented; pointers to I/O devices
remain constant throughout the transfer.
If any termination condition has occurred during
this cycle, the channel stops the transfer. It uses

If a word has been fetched or assembled, and

the content of the CC register to assign a value to
the termination offset, to reflect the cause of the
termination. The channel adds this offset to TP
and resumes channel program execution at the
location now addressed by TP. This offset will

bytes are to be stored (destination bus is eight bits
or transfer is to an odd address), the channel
disassembles the word into two bytes. If the
transfer is destination-synchronized (only one
Mnemonics © Intel, 1979

Logical Bus Width
Source-Destination)
8-8 8-16 16-8 16-16

3-32

80891NPUT/OUTPUT PROCESSOR

COMPARE
UNDER
MASK

ORO

ASSEMBLE
BYTES

WAIT FOR
DMA REQUEST

(OPTIONAL)

Figure 3-28. Simplified DMA Transfer Flowchart

Following the Transfer

always be zero, four, or eight bytes past the end
of the instruction following the XFER instruction.

A DMA transfer updates register Be, register GA
(if it points to memory), and register GB (if it
points to memory). If the original contents of
these registers are needed following the transfer,
the contents should be saved in memory prior to
executing the XFER instruction.

If no termination condition is detected and
another byte remains to be stored, the channel
stores this byte, waiting for DRQ -if necessary,
and updates the source and destination pointers.
After the store, it again checks for termination.

3-33

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

A program may determine the address of the last

The 8089's TSL (test and set while locked) instruction enables it to share a resource, such as a
buffer, with other processors by means of
semaphore (see section 2.5 for a discussion of the
use of semaphores to control access to shared
resources). Finally, the 8089 can lock the system
bus for the duration of a DMA transfer to ensure
that the transfer completes without interference
from other processors on the bus.

byte stored by a DMA transfer by inspecting the
pointer registers as shown in table 3-10. The
number of bytes stored is equal to:
lasLbyte_address - first_byte_address + 1.

For 'port-to-port transfers, the number of bytes
ttansferred can be determined by subtracting the
final value of BC from its original value provided
that:
• the original BC > final BC, .
• a transfer cycle is not "chopped off" before
it completes by a masked compare or external termination.

In the remote configuration, the 8089 is electrically compatible with Intel's Multibus™ multimaster bus design. This means that the power and
convenience of 8089 lIO processing can be used
in 8080- or 8085-based systems that implement the
Multibus protocol or a superset of it. This
includes single-board computers such as Intel's
iSBC 80120™ and iSBC 80130™ boards. In addition, the lOP can access other iSBC board
products such as memory and communications
controllers.

In general, programs should not use the contents
of GA, GB and BC following a transfer except as
noted above and in table 3-10. This is because the
contents of the registers are affected by numerous
conditions, particularly when the transfer is terminated by EXT. In particular, when a program
is performing a sequence of transfers, it should
reload these registers before each transfer.

Bus Arbitration
The 8089 shares its system bus with a CPU, and
may also share its 1/0 bus with an lOP or another
CPU. Only one processor ata time may drive a
bus. When two (or more) processors want to use a
shared bus, the system must provide an arbitration mechanism that will grant the bus to one of
the processors. This section describes the bus
arbitration facilities that may be used with the
8089 and covers their applicability to different
lOP configurations.

3.5 Multiprocessing Features
The 8089 shares the multiprocessing facilities
common to the 8086 family of processors. It has
. on-chip logic for arbitrating the use of the local
bus with a CPU or another lOP; system bus
arbitration is delegated to an 8289 Bus Arbiter.

Table 3-10. Address of Last Byte Stored
Termination

Source

Destination

Synchronization

Last Byte Stored

byte count

memory
memory
port

memory
port
memory

any
any
any

destination pointer'
source pointer
destination pOinter

masked compare

memory
memory
port

memory
port
memory

any
any
any

destination pointer
source pointer
destination pointer

external

memory
memory
port

memory
port
memory

unsynchronized
destination
source

destination pointer
source pOinter'
d.esUnation pointer

'Source pointer may also be used.
llftransfer is BI B-W, source pOinter must be decremented by 1 to point to last byte transferred.

Mnemonics © Inlel,1979

3-34

8089 INPUT/OUTPUT PROCESSOR

between two lOPs. In this case, one lOP is
designated the master, and the other is designated
the slave. However, the only difference between a
master and a slave running in mode 1 is that the
master has the bus at initialization time. Both
processors may request the bus from each other at
any time. The processor that has the bus will
grant it to the requester as soon as one of the
following occurs on either channel:

Request/Grant Line

When an 8089 is directly connected to
another 8089, an 8086 or an 8088, the
RQ/GT (request/grant) lines built into all of
these processors are used to arbitrate use of a
local bus. In the local mode, RQ/GT is used
to control access to both the system and the
110 bus.
As discussed in section 2.6, the CPU's
request/grant lines (RQ/GTO and RQ/GTl)
operate as follows:
•

an external processor sends a pulse to the
CPU to request use of the bus;

•

the CPU finishes its current bus cycle, if one
is in progress, and sends a pulse to the processor to indicate that it has been granted the
bus; and
when the external processor is finished with
the bus, it sends a final pulse to the CPU, to
indicate that it is releasing the bus.

•

•

an unchained channel program instruction is
completed, or

•

a channel goes idle due to a program halt or
the completion of a synchronized transfer
cycle (the channel waits for a DMA request).

Execution of a chained channel program, a DMA
termination sequence, a channel attention
sequence, or a synchronized DMA transfer (i.e., a
high-priority operation) on either channel
prevents the lOP from granting the bus to the
requesting lOP.

The 8089's request/grant circuit can operate in
two modes; the mode is selected when the lOP is
initialized (see section 3.6). Mode 0 is compatible
with the 8086/8088 request/ grant circuit and
must be specified when the 8089's RQ/GT line is
connected to RQ/GTO or RQ/GTl of one of
these...fPUs. Mode 0 may be s~ified when
RQ/GT of one 8089 is tied to RQ/GT of another
8089. When mode 0 is used with a CPU, the CPU
is designated the master, and the lOP is
designated a slave. When mode 0 is used with
another lOP, one lOP is the master, and the other
is the slave. Master/slave designation also is made
at initialization time as discussed in section 3.6.
The master has the bus when the system is initialized and keeps the bus until it is requested by
the slave. When the slave requests the bus, the
master grants it if the master is idle. In this sense,
the CPU becomes idle at the end of the current
bus cycle. An lOP master, on the other hand,
does not become idle until both channels have
halted program execution or are waiting for DMA
requests. Once granted the bus, the slave (always
an lOP) uses it until both channels are idle, and
then releases it to the master. In mode 0, the
master has no way of requesting the slave to
return the bus.

The handshaking sequence in mode 1 is:
•

the ~uesting processor pulses once on
RQ/GT;

•

the processor with the bus grants it by
pulsing once; and
if the processor granting the bus wants it
back immediately (for example, to fetch the
next instruction), it will pulse RQ/GT again,
two clocks after the grant pulse.

•

The fundamental difference between the two
modes is the frequency with which the bus can be
switched between the two processors when both
are active. In mode 0, the processor that has the
bus will tend to keep it for relatively long periods
if it is executing a channel program. Mode 1 in
effect places unchained channel programs at a
lower priority since the processor will give up the
bus at the end of the next instruction. Therefore,
when both processors are running channel programs or synchronized DMA, they will share the
bus more or less equally. When a processor
changes to what would typically be considered a
higher-priority activity such as chained program
execution or DMA termination, it will generally
be able to obtain the bus quickly and keep the bus
for the duration of the more critical activity.

Mode 1 operation of the request/grant lines may
only be used to arbitrate use of a private I/O bus
3-35

8089 INPUT /OUTPUT PROCESSOR

Table 3-11 summarizes the bus arbitration
requirements and options by lOP configuration.
In the local configuration, all bus arbitration is
performed by the request/ grant lines without
additional hardware. One lOP may be connected
to each of the CPU's RQ/GT lines. The lOP connected to RQ/GTO will obtain the bus if both processors make simultaneous requests.

8289 Bus Arbiter

When an lOP is configured remotely, an 8289 Bus
Arbiter is used to control its access to the shared
system bus (the CPU also has its own 8289). In a
remote cluster of two lOPs or an lOP and a CPU,
one 8289 controls access to the system bus for
both processors in the cluster. The 8289 has
several operating modes; when used with an 8089,
the 8289 is usually strapped in its lOB (I/O
Peripheral Bus) mode.

Since a s~le lOP in a remote configuration does
not use RQ/GT, its mode may be set to 0 or 1
without affect. The single remote lOP, however,
must be initialized as a master. If two remote
lOPs share an I/O bus, one must be a master and
the other a slave; both must be initialized to use
the same request/grant mode. Normally, mode 1
will be selected for its improved responsiveness,
and the designation of master will be arbitrary. If
one lOP must have the I/O bus when the system
comes up, it should be initialized as the master.

The 8289 monitors the lOP's status lines. When
these indicate that the lOP needs a cycle on the
system bus, and the lOP does not presently have
the bus, the 8289 activates a bus request signal.
This signal, along with the bus request lines of
other 8289s on the same bus, can be routed to an
external priority-resolving circuit. At the end of
the current bus cycle, this circuit grants the bus to
the requesting 8289 with the highest priority.
Several different prioritizing techniques may be
used; in a typical system, an lOP would have
higher bus priority than a CPU. If the 8289 does
not obtain the bus for its processor, it makes the
bus appear "not ready" as if a slow memory were
being accessed. The processor's clock generator
responds to the "not ready" condition by inserting wait states into the lOP's bus cycle, thereby
extending the cycle until the bus is acquired.

When a remote lOP shares its I/O bus with a
local CPU, it must be a slave and must use
request/grant mode O.

Bus Load Limit
A locally configured lOP effectively has higher
bus priority than the CPU since the CPU will
grant the bus upon request from the lOP. One or
two local lOPs can potentially monopolize the
bus at the expense of the CPU. Of course, if the
lOP activities are time-critical, this is exactly what
should happen. On the other hand, there may be
low-priority channel programs that have less
demanding performance requirements.

Bus Arbitration for lOP Configurations

When the CPU initializes an lOP, it must inform
the lOP whether it is a master or a slave, and
which request/grant mode is to be used. This section covers the requirements and options
available for each lOP configuration; section 3.6
describes how the information is communicated
at initialization time.

In such cases, the CPU may set a CCW bit called
bus load limit to constrain the channel's use of the
bus during normal (unchained) channel program

Table 3-11. Bus Arbitration Requirements and Options
Local

Remote With
Local CPU

Remote

lOP
Master/
Slave

RQ/GT
Mode

Master/
Slave

RQ/GT
Mode

Master/
Slave

RQ/GT
Mode

IOP1

Slave

0

Master

oor 1

Slave

0

IOP2

Slave

0

Slave

Same as
Master

N/A

N/A

3-36

8089 INPUT/OUTPUT PROCESSOR

execution. When this bit is set, the channel
decrements a 7-bit counter from 7F (127) to OH
with each instruction executed. Since the counter
is decremented once per clock period, the channel
waits a minimum of 128 clock cycles before it executes the next instruction. By forcing the execution time of all instructions to 128 clocks, the use
of the bus is reduced to between 3 and 25 percent
of the available bus cycles.

access of multiple processors to ~hared
resource.) The instruction activates LOCK and
inspects the value of a byte in memory. If the
value of the byte is OH, it is changed (set) to a
value specified in the instruction and the following instruction is executed. If the byte does not
contain OH, control is transferred to another location specified in the instruction. The bus is locked
from the time the byte is read until it is either written or control is transferred to ensure that another
processor does not access the variable after TSL
has read it, but before it has updated it (i.e.,
between bus cycles). The following line of code
will repeatedly test a semaphore pointed to by GA
until it is found to contain zero:

Setting the bus load limit effectively enables a
CPU to slow the execution of a normal channel
program, thus freeing up bus cycles. This is of
most use in local configurations, but also may be
effective in remote configurations, particularly
when channel programs are executed from system
memory. Bus load limit has no effect on chained
channel programs, DMA transfers, DMA termination, or channel attention sequences.

TEST_FLAG: TSL [GAl. OFFH, TEST_FLAG

When the semaphore is found to be zero, it is set
to FFH and the program continues with the next
instruction.

Bus Lock
Like the 8086 and 8088, the 8089 has a LOCK
(bus lock) signal which can be activated by software. The LOCK output is normally connected to
the LOCK input of an 8289 Bus Arbiter. When
LOCK is active, the bus arbiter will not release the
bus to another processor regardless of its priority.
A channel automatically locks the bus during execution of the TSL (test and set while locked)
instruction and may lock the bus for the duration
of a DMA transfer.

3.6 Processor Control and
Monitoring

If bit 9 of register CC is set, the 8089 activates its
LOCK output during a DMA transfer on that
channel. If the transfer is synchronized, LOCK is
active from the time that the first DRQ is
recognized. If the transfer is unsynchronized,
LOCK is active throughout the entire transfer
(there are no idle periods in an un synchronized
transfer). LOCK goes inactive when the channel
begins the DMA termination sequence.

This section focuses on lOP/CPU interaction,
i.e., how the CPU initializes the lOP and subsequently sends commands to channels, and how
the channels may interrupt the CPU. It also
covers the channels' DMA control signals and the
status signals that external devices can use to
monitor lOP activities.

Initialization

A locked transfer ensures that the transfer will be
completed in the shortest possible time and that
the transferring channel has exclusive use of the
bus. Once the channel obtains the bus and starts a
locked transfer, the channel, in effect, becomes
the highest-priority processor on that bus.

Before the 8089 channels can be dispatched to
perform I/O tasks, the lOP must be initialized.
The initialization sequence (figure 3-29) provides
the lOP with a definition of the system environment: physical bus widths, request/grant mode,
and the location of the channel control block.

The 8089 TSL (test and set while locked)
instruction can be used to implement a
semaphore. (See section 2.5 for a discussion of
how a semaphore may be used to control the

The sequence begins when the lOP's RESET line
is activated. This halts any operation in progress,
but does not affect any registers. Upon the first

3-37

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

RESET_

lOP

CPU

HALT

PREPARE
INITIALIZATION
CONTROL
BLOCKS

CH1 BUSY-FFH

CH2 BUSY-OH

WAIT FOR
CHANNEL
ATTENTION

CA+SEL

ISSUE
CHANNEL
ATTENTION

READ
INITIALIZATION
CONTROL
BLOCKS

lOP IS READY;
CPU MAY INITIALIZE
ANOTHER lOP

CH1 BUSY-OH

WAIT FOR
CHANNEL
ATTENTION

Figure 3-29. Initialization Sequence

RESET after power-up, the content of all lOP
registers is undefined. Register contents are
preserved if the lOP is subsequently RESET,
except that RESET always clears the chain bit in
register CC.

the SCP and the SCB may be in RAM or ROM. It
is the CPU's responsibility to properly setup the
control blocks.
The CPU starts the initialization sequence by issuing a channel attention to channell (SEL low) or
to channel 2 (SEL high). The CPU typically
accesses the channels as two consecutive addresses
in its I/O or memory space. An OUT instruction
(for an I/O-mapped lOP) or a memory reference
instruction (such as MOV) then issues the channel
attention.

The lOP initializes itself by reading information
from initialization control blocks located in the
system space (see. figure 3-30). The three blocks
are the SCP (system configuration pointer), SCB
(system configuration block) and the CB (channel
control block). The CB is normally RAM-based;
Mnemonics © Intel, 1979

3-38

8089 INPUT/OUTPUT PROCESSOR

HIGH SYSTEM MEMORY
F FFFEH
(RESERVED)

FFFFCH

SYSTEM
CONFIGURATION
POINTER
(FIXED LOCATION)

SCB SEGMENT BASE
SCB OFFSET
(RESERVED)

I

}-

SYSBUS

FFFFAH
F FFF8H
F FFF6H
F FFF4H

8086/8088
RESET LOCATION

F FFF2H
F FFFOH

CB SEGMENT BASE

SYSTEM
CONFIGURATION
BLOCK
(USER·DEFINED LOCATION)

(RESERVED)

CHANNEL
CONTROL
BLOCK
(USER·DEFINED LOCATION)

}-

t-

CB OFFSET

C
H
A
N
N
E
L
2
C
H
A
N
N
E
L
1

I

SOC

1-

(RESERVED)
PB SEGMENT BASE
PB OFFSET

I

BUSY

}---

CCW

(RESERVED)
PB SEGMENT BASE
PB OFFSET
BUSY

I

}--

CCW

LOW SYSTEM MEMORY

Figure 3-30. Initialization Control Blocks

If channel 1 is selected (SEL=low), the lOP con-

If the lOP is a master, it assumes that it has the
bus immediately. If it is a slave, it pulses RQ/GT

siders itself a master (as discussed in section 3.5).
If channel 2 is selected (SEL=high), the lOP
operates as a slave. The lOP ignores, and does
not latch, any subsequent channel attentions that
occur during initialization.

to request the bus from the CPU (local configuration) or the other lOP (remote configuration).
When the lOP has obtained the bus, it assumes
that the system bus is eight bits wide and reads the

3-39

8089 INPUT /OUTPUT PROCESSOR

programs and is only loaded during initialization.
The CB, therefore, cannot be moved during execution except by reinitializing the lOP.

SYSBUS field (figure 3.31) from location
FFFF6H in system memory. This byte reUs the
lOP the actual physical width of the system bus;
aU subsequent accesses take advantage of a 16-bit
bus if it is available; i.e., even-addressed words
are fetched in single bus cycles. It is therefore
advantageous to word-align the control blocks.

After loading the address of the CB, the lOP
clears the channell BUSY flag to OH. The other
fields in the CB are used when a channel is dispatched and are not read or altered in the
initialization sequence.
After the CPU has started the initialization
sequence, it should monitor channell's BUSY
flag in the CB to determine when the sequence has
been completed. When the BUSY flag has been
cleared, the CPU can dispatch either channel. It
also can begin the initialization of another lOP.
Since each lOP normally has a separate CB, the
CPU must allocate the CB and update the pointer
in the SCB before initializing the next lOP. Alternatively, mUltiple SCBs could be employed, each
pointing to a different CB area. In this case the
CPU would update the pointer in the SCP before
initializing the next lOP. It follows from this that
in multi-lOP systems, either the SCB or SCP, or
both, must be RAM-based. When all lOPs have
been initialized, the CPU may use RAM occupied
by the SCB for another purpose.

o

7

o

o

o

o

o

o

w

W = 0 = 8-BIT SYSTEM BUS
W =1 =18-BIT SYSTEM BUS

Figure 3-31. SYSBUS Encoding

Next, the lOP reads the SCB address located at
FFFF8H. This is a standard doubleword pointer,
and the lOP constructs a 20-bit physical address
from it by shifting the segment base left four bits
and adding the offset word of the pointer.
Having obtained the SCB address, the lOP reads
the SOC (system operation command). This byte
(see figure 3-32) teUs the lOP the request/grant
mode and the width of the I/O bus.

Channel Commands
After initialization, any channel attention is
interpreted as a command to channel 1
(SEL=low) or to channel 2 (SEL=high). As
discussed in section 3.2, the channel attention,
depending on the activities of both channels, may
not be recognized immediately. The channel
attention is latched, however, so that it will be
serviced as soon as priorities allow.

o

7

o

o

o

o

o

R

When the channel recognizes the CA, it sets its
BUSY flag in the CB to FFH. This does not prevent the CPU from issuing another CA, but provides status information only. In its response to a
CA, the channel reads various control fields from
system memory. It is the responsibility of the
CPU to ensure that the appropriate fields are
properly initialized before issuing the CA.

R = REQUEST/GRANT MODE
I = 0 = 8-BIT I/O BUS
I = 1 = 111-BIT I/O BUS

Figure 3-32. SOC Encoding

After setting its BUSY flag, the channel reads its
CCW from the CB. It examines the command
field (see figure 3-33) and executes the command
encoded there by the CPU.

Then the lOP reads the doubleword pointer to the
channel control block, converts the pointer into a
20-bit physical address, and stores it in an internal
register. This register is not accessible to channel
3-40

8089 INPUT/OUTPUT PROCESSOR

o

7

CF
000
001
010
011
100
101
110
111

COMMAND FIELD
UPDATE PSW
START CHANNEL PROGRAM LOCATED IN I/O SPACE.
(RESERVED)
START CHANNEL PROGRAM LOCATED IN SYSTEM SPACE.
(RESERVED)
RESUME SUSPENDED CHANNEL OPERATION
SUSPEND CHANNEL OPERATION
HALT CHANNEL OPERATION

ICF
00
01
10
11

INTERRUPT CONTROL FIELD
IGNORE, NO EFFECT ON INTERRUPTS.
REMOVE INTERRUPT REQUEST; INTERRUPT IS ACKNOWLEDGED.
ENABLE INTERRUPTS.
DISABLE INTERRUPTS.

B

o
1

BUS LOAD LIMIT
NO BUS LOAD LIMIT
BUS LOAD LIMIT

P

PRIORITY BIT

Figure 3-33. Channel Command Word Encoding

The CPU may suspend a channel operation
(either program execution or DMA transfer) by
setting CF to 110. The channel saves its state (TP,
its tag bit, and PSW) in the first two words of the
parameter block (see figure 3-18 for format) and
clears its BUSY flag to OH. Note the following in
regard to a suspended operation:

Figure 3-34 illustrates the channel's response to
each type of command. Note that if CF contains a
reserved value (010 or 100), the channel's
response is unpredictable.
The CPU can use the "update PSW" command
to alter the bus load limit and priority bits in the
PSW (see figure 3-17) without otherwise affecting
the channel. This command also allows the CPU
to control interrupts originating in the channel;
this topic is discussed in more detail later in this
section.
The two "start program" commands differ only
in their affect on the TP tag bit. If CF=OOI, the
channel sets the tag to 1 to indicate that the program resides in the 110 space. If CF=Oll, the tag
is cleared to 0, and the program is assumed to be
in the system space. The channel converts the
doubleword parameter block pointer to a 20-bit
physical address and loads this into PP. It loads
the doubleword task block (channel program)
pointer into TP, updates the PSW as specified by
the ICF, Band P fields of the CCW and starts the
program with the instruction pointed to by TP .

3-41

•

The content of the doubleword pointer to the
beginning of the channel program is replaced
by the channel state save data. Therefore, a
suspended operation may be resumed, but
cannot be start~d from the beginning without
recreating the doubleword pointer.

•

TP is the only register saved by this
operation. If another channel program is
started on this channel, the other registers,
including PP, are subject to being overwritten. In general, suspend is used to temporarily halt a channel, not to "interrupt" it
with another program. Section 3.10 provides
an example of a program that can be used to
save another program's registers.

8089 INPUT/OUTPUT PROCESSOR

COMMAND

UPDATE PSW
(CF = 000)

CHANNEL

CHANNEL
CONTROL
BLOCK

PP

(RESERVED)

rn 1. .__

-

T_p_-",

START PROGRAM
(CF=001/011)

T
A
G

TP

" '" '"' ' ' f
(CR=110)

I CCW

o

(RESERVED)

6

PARAMETER
BLOCK
POINTER

4

!

~

HALT OPERATION
(CF=111)

T
mG

2

f-

I

PARAMETER
BLOCK
POINTER

BUSY

~

{

I CCW

-:i{

-

0

!
2

TASK
BLOCK POINTER

I,

0

1'r
C~~~fEEL-

2
0

r

.Ii ., r (RESERVED)

If-

P~~~:R

BUSY

8

1
,

4

PARAMETER

TP

TB POINTER
OR
CHANNEL STATE

r--

(RESERVED)

G

T
U1~

2

-

PP

PP

RESUME OPERATION
(CF=101)

I~{

1r

4

PARAMETER
BLOCK
POINTER

BUSY

PP

PARAMETER
BLOCK

I CCW

4

-I. 2.

____________L-L-____________

PP

(RESERVED)

TP

PARAMETER
~
BLOCK POINTER
BUSY

I

CCW

Figure 3-34. Channel Commands
3-42

0

{

C~~~ikEL

2
'--_ _ _- - ' 0

~

1
4
2

o

TB POINTER
OR
CHANNEL STATE

2
0

8089 INPUT IOUTPUT PROCESSOR

•

Suspending a DMA transfer does not affect
any 110 devices (an 110 device will act as
though the transfer is proceeding). The CPU
must provide for conditions that may arise if,
for example, a device requests a DMA
transfer, but the channel does not
acknowledge the request because it has been
suspended. Similarly, an I/O device may be
in a different condition when the operation is
resumed.

of DRQ following the last transfer cycle. If EXT
is activated during a transfer cycle, a fetched byte
may not be stored as explained in section 3.4.
A channel does not recognize EXT if it is not performing a DMA transfer. If EXTl and EXT2 are
activated simultaneously, EXTI is recognized
first.

A suspended operation may be resumed by setting
CF to 101. This command causes the channel to
reload TP, its tag bit, and the PSW from the first
two words of PB. Resuming an operation that has
not been suspended will give unpredictable results
since the first two words of PB will not contain
the required channel state data. A resume command does not affect any channel registers other
than TP.

Interrupts
Each channel has a separate system interrupt line
(SINTRI and SINTR2). A channel program may
generate a CPU interrupt request by executing a
SINTR instruction. Whether this instruction
actually activates the SINTR line, however,
depends upon the state of the interrupt control bit
(bit 3 of the PSW; see figure 3-17). If this bit is
set, interrupts from the channel are enabled, and
execution of the SINTR instruction activates
SINTR. If the interrupt control bit is cleared, the
SINTR instruction has no effect; interrupts from
the channel are disabled.

The CPU may abort a channel operation by
issuing a "halt" command (CF=lll). The channel clears its BUSY flag to OH and then idles.
Again, the CPU must be prepared for the effect
aborting a DMA transfer may have on an I/O
device.

The CPU can alter a channel's interrupt control
bit by sending any command to the channel with
the value of ICF (interrupt control field) in the
CCW set to 10 (enable) or II (disable). Thus, the
CPU can prevent interrupts from either channel.

ORQ (OMA Request)
The synchronizing device in a DMA transfer uses
the DRQ line to indicate when it is ready to send
or receive the next byte or word. The channel
recognizes a signal on this line only during a
DMA transfers, i.e., after the instruction following XFER has been executed and before a ter-·
mination condition has occurred. The channels
have separate DMA request lines (DRQI and
DRQ2).

Once activated, SINTR remains active until the
CPU sends a channel command with ICF set to 01
(interrupt acknowledge). When the channel
receives this command, it clears the interrupt service bit in the PSW (figure 3-17) and removes the
interrupt request. Disabling interrupts also clears
the interrupt service bit and lowers SINTR.

EXT (External Terminate)

Status Lines

An external device (typically the synchronizing
device) can terminate a DMA transfer by signaling on this line. Each channel has its own external
terminate line (EXTl and EXT2). The channel
stops the transfer as soon as the current fetch or
store cycle is completed. An external terminate in
an unsynchronized transfer could result in a loss
of data, although this would not be a typical use
of EXT. In a synchronized transfer, the synchronizing device will normally issue EXT instead

The lOP emits signals on the SO-S2 status.\ines to
indicate to external devices the type of bus cycle
the processor is starting. Table 3-12 shows the
signals that are output for each type of cycle.
These status lines are connected to an 8288 Bus
Controller. The bus controller decodes these lines
and outputs the signals that control components
attached to the bus. The lOP indicates "instruction fetch" on these lines when it is reading and
writing memory operands as well as when it is fet3-43

Mnemonics © Intel, 1979

80891NPUT/OUTPUT PROCESSOR

ched instructions. In the remote configuration, an
8289 Bus Arbiter monitors th~ so-Si status lines
to determine when a system bus access is required.

The description of each instruction in these
categories explains how the instruction operates
and how it may be used in channel programs.
Instructions that perform essentially the same
operation (e.g., ADD and ADDB, which add
words and bytes respectively), are described
together. A reference table at the end of the section lists every instruction alphabetically and provides execution time, encoded length, and sample
ASM-89 coding for each permissable operand
combination. For information on how the 8089
machine instructions are encoded in memory, see
section 4.3.

Table 3-12. Status Signals SO-S2

S2 S1 SO
0

0

0

0

0

0

1

1
1
0

1
0
1
0

1
1
1

1
1

0

1
0
1

0

Type of Bus Cycle
Instruction fetch from 1/0 space
Data fetch from 1/0 space
Data store to 1/0 space
(not used)
Instruction fetch from system
space
Data fetch from system space
Data store to system space
Passive; no bus cycle run

In reading this section, it is important to recall
that the instruction set does not differentiate
between memory addresses and I/O device
addresses. Instructions that are described as
accepting byte and word memory operands may
also be used to read and write I/O devices.

Status lines S3-S6 indicate whether the bus cycle is
DMA or non-DMA, and which channel is running the cycle (see table 3-13). Note that when the
lOP is not running a bus cycle (e.g., when it is idle
or when it is executing an internal cycle that does
not use the bus), the status lines reflect the last
bus cycle run.

Data Transfer Instructions
These instructions move data between memory
and channel registers. Traditional byte and word
moves (including memory-to-memory) are
available, as are special instructions that load
addresses into pointer registers and update tag
bits in the process.

Table 3-13. Status Signals S3-S6

S6 S5 S4 S3
1
1
1
1

1
1
1
1

0

0

0

1

1
1

0

1

Bus Cycle
MOV destination, source

DMA cycle on channel 1
Dfy'lA cycle on channel 2
Non-DMA cycle on channel 1
Non-DMA cycle on channel 2

MOV transfers a byte or word from the source to
the destination. Four instructions are provided:

MOV
MOVB
MOVI
MOVBI

3.7 Instruction Set
This section divides the lOP's 53 instructions into
five functional categories:
I. data transfer,
2. arithmetic,
3. logic and bit manipulation,
4. program transfer,
5. processor control.
Mnemonics © Intel, 1979

Move Word Variable,
Move Byte Variable,
Move Word Immediate,
Move Byte Immediate.

Figure 3-35 shows how these instructions affect
register operands. Notice that when a pointer
register is specified as the destination of a MOV,
its tag bit is unconditionally set to I. MOV
instructions are therefore used to load I/O space
addresses into pointer registers-.
3-44

8089 INPUT/OUTPUT PROCESSOR

Register is Destination

Byte
Operation

Register is Source

Tag 19
15
7
0
__ -,-_ _ _ _ _-,-_ _ _ _---,

Tag 19

~ 1J ~S~ ~ sis S S S S S S SiR R R R R R R R I

15

7

o

~xJ0~~xlx X X X X X X XIT T T T T T TTl

~XJG~~XITTTTTTTTITTTTTTTT

T =
R=
S=
X =
1 =

I

bit is transferred to destination operand
bit is replaced by source operand
bit is sign extension of high-order bit transferred
bit is ignored
bit is unconditionally set

Figure 3-35. Register Operands in MOV Instructions

MOVP destination, source

An 8086 or 8088 can pass any address in its
megabyte memory space to a channel program in
the form of a doubleword pointer. The channel
program can access the location by using LPD to
load the location address into a pointer register.

MOVP (move pointer) transfers a physical
address variable between a pointer register and
memory. If the source is a pointer register, its
content and tag bit are converted to a physical
address pointer (see figure 3-23). If the source is a
memory location, the three bytes are converted to
a 20-bit physical address and a tag value, and are
loaded into the pointer register and its tag bit.
MOVP is typically used to save and restore
pointer registers.

Arithmetic Instructions
The arithmetic instructions interpret all operands
as unsigned binary numbers of 8, 16 or 20 bits.
Signed values may be represented in standard
two's complement notation with the high-order
bit representing the sign (O=positive, l=negative).
The processor, however, has no way of detecting
an overflow into a sign bit so this possibility must
be provided for in the user's software.

LPD destination, source

LPD (load pointer with doubleword) converts a
doubleword pointer (see figure 3-22) to a 20-bit
physical address and loads it into the destination,
which must be a pointer register. The pointer
register's tag bit is unconditionally cleared to 0,
indicating a system address. Two instructions are
provided:
LPD
LPDI

The 8089 performs arithmetic operations to 20
significant bits as follows. Byte and word
operands are sign-extended to 20 bits (e.g., bit 7
of a byte operand is propagated through bits 8-19
of an internal register). Sign extension does not
affect the magnitude of the operand. The operation is then performed, and the 20-bit result is

Load Pointer With Doubleword
Variable
Load Pointer With Doubleword
Immediate
3-45

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

returned to the destination operand. High-order
bits are truncated as necessary to fit the result in
the available space. A carry out of, or borrow
into, the high-order bit of the result is not
detected. However, if the destination is a register
that is larger than the source operand, carries will
be reflected in the upper register bits, up to the
size of the register.

INC

The destination is incremented by 1. Two instructions are available:
INC
INCB

Figure 3-36 shows how the arithmetic instructions
treat registers when they are specified as source
and destination operands.

ADD

DEC

Increment Word
Increment Byte

destination

The destination is decremented by 1. Word and
byte instructions are provided:
DEC
DECB

destination, source

The sum of the two operands replaces the destination operand. Four addition instructions are
provided:
ADD
ADDB
ADD!
ADDBI

destination

Decrement Word
Decrement Byte

Logical and Bit Manipulation
Instructions

Add Word Variable
Add Byte Variable
Add Word Immediate
Add Byte Immediate

The logical instructions include the boolean
operators AND, OR and NOT. Two bit manipulation instructions are provided for setting or

Register is Source

Register is Destination
Tag 19
Byte
Operation

Word
Operation

15

7

0

r::l r - -

LXj~~~ RIR R R R R R R RIR R R R R R R R I

Tag 19

15

-L.._ _ _ _.........J.L....-_ _ _ _--'

X = bit is ignored in operation
R = bit is replaced by operation result
P = bit participates in operation

Figure 3-36. Register Operands in Arithmetic Instructions
3-46

o

rx XXxix X X X X X X xlp P P P P P P P I

rX;
L
.....1.:___

~xJ~~~ RIR R R R R R R RIR R R R R R R R I

Mnemonics.© Intel, 1979

7

8089 INPUT/OUTPUT PROCESSOR

clearing a single bit in memory or in an I/O device
register. As shown in figure 3-37, the logical
operations always leave the upper four bits of
20-bit destination registers undefined. These bits
should not be assumed to contain reliable values
or the same values from one operation to the
next. Notice also that when a register is specified
as the destination of a byte operation, bits 8-15
are overwritten by bit 7 of the result. Bits 8-15 can
be preserved in AND and OR instructions by
using word operations in which the upper byte of
the source operand is FFH or OOH, respectively.

AND is useful when more than one bit of a device
register must be cleared while leaving the remaining bits intact. For example, ANDing an 8-bit
register with EEH only clears bits 0 and 4.

The two operands are logically ORed, and the
result replaces the destination operand. A bit in
the result is set if either or both of the corresponding bits of the operands are set; if both operand
bits are cleared, the result bit is cleared. Four
types of OR instructions are provided:

AND destination, source
The two operands are logically ANDed and the
result replaces the destination operand. A bit in
the result is set if the bits in the corresponding
positions of the operands are both set, otherwise
the result bit is cleared. The following AND
instructions are available:
AND
ANDB
ANDI
ANDBI

destination, source

OR

OR
ORB
ORI
ORBI

Logical OR Word Variable
Logical OR Byte Variable
Logical OR Word Immediate
Logical OR Byte Immediate

OR can be used to selectively set multiple bits in a
device register. For example, ORing an 8-bit
register with 30H sets bits 4 and 5, but does not
affect the other bits.

Logical AND Word Variable
Logical AND Byte Variable
Logical AND Word Immediate
Logical AND Byte Immediate

Register is Destination
Tag 19

15

Byte
Operation

r A r. - - -

Word
Operation

r ;J r.

L~LU~~

--

Register is Source

7

0

uis S S SS SS SIRR RRRR RR I
IR R R R R R R RI R R R R R R R R I

L~ ~~ ~ U

X
U
R
S
P

Tag 19

15

7

[XJ ~ ~~ xix x X X X X X xlp p p p p p p

o

pi

[~~~ xlp p p p p p p pip p p p p p p p

I

= bit is ignored in operation
= bit is undefined following operation
= bit participates in operation and is replaced by result
= bit is sign-extension of high-order result bit
= bit participates in operation, but is unchanged

Figure 3-37. Register Operands in Logical Instructions
3-47

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

NOT destination/destination, source

any location within -32,768 through +32,767
bytes. An instruction containing an 8-bit displacement is called a short transfer and ail instruction
containing a 16-bit displacement is called a long
transfer.

NOT inverts the bits of an operand. If a single
operand is coded, the inverted result replaces the
original value. If two operands are coded, the
inverted bits of the source replace the destination
value (which must be a register), but the source
retains its original value. In addition to these two
operand forms, separate mnemonics are provided
for word and byte values:
NOT
NOTB

The program transfer instructions have alternate
mnemonics. If the mnemonic begins with the letter "L," the transfer is long, and the distance to
the transfer target is expressed as a 16-bit
displacement regardless of how far away the
target is located. If the mnemonic does not begin
with "L," the ASM-89 assembler may build a
short or long displacement according to rules
discussed in section 3.9.

Logical NOT Word
Logical NOT Byte

NOT followed by INC will negate (create the
two's complement of) a positive number.

seTa

The "self-relative" addressing technique used by
program transfer instructions has two important
consequences. First, it promotes positionindependent code, i.e., code that can be moved in
memory and still execute correctly. The only
restriction here is that the entire program must be
moved as a unit so that the distance between the
transfer instruction and its target does not
change. Second, the limited addressing range of
these instructions must be kept in mind when
designing large (over 32k bytes of code) channel
programs.

destination, bit-select

The bit-select operand specifies one bit in the
destination, which must be a memory byte, that is
unconditionally set to 1. A bit-select value of 0
specifies the low-order bit of the destination while
the high-order bit is set if bit-select is 7. SETB is
handy for setting a single bit in an 8-bit device
register.
CLR

destination, bit-select

CLR operates exactly like SETB except that the
selected bit is unconditionally cleared to O.

CALL/LCALL

CALL invokes an out-of-line routine, saving the
value of TP so that the subroutine can transfer
back to the instruction following the CALL. The
instruction stores TP and its tag bit in the TPsave
operand, which must be a physical address
variable, and then transfers to the target address
formed by adding the target operand's displacement to TP. The subroutine can return to the
instruction following the CALL by using a
MOVP instruction to load TPsave back into TP.

Program Transfer Instructions
Register TP controls the sequence in which channel program instructions are executed. As each
instruction is executed, the length of the instruction is added to TP so that it points to the next
sequential instruction. The program transfer
instructions can alter this sequential execution by
adding a signed displacement value to TP. The
displacement is contained in the program transfer
instruction and may be either 8 or 16 bits long.
The displacement is encoded in two's complement
notation, and the high-order bit indicates the sign
(O=positive displacement, 1=negative displacement). An 8-bit displacement may cause a
transfer to a location in the range -128 through
+127 bytes from the end of the transfer instruction, while a 16-bit displacement can transfer to
Mnemonics © Intel, 1979

TPsave, target

Notice that the 8089's facilities for implementing
subroutines, or procedures, is less sophisticated
than its counterparts in the 8086/8088. The principal difference is that the 8089 does not have a
built in stack mechanism. 8089 programs can
implement a stack using a base register as a stack
pointer. On the other hand, since channel programs are not subject to interrupts, a stack will
not be required for most channel programs.
3-48

8089 INPUT /OUTPUT PROCESSOR

JMP/LJMP

target

JMCNE/LJMCNE

source, target

JMP causes an unconditional transfer (jump) to
the target location. Since the task pointer is not
saved, no return to the instruction following the
JMP is implied.

This instruction causes a jump to the target location if the source is not equal to the mask/
compare value in MC. It otherwise operates identically to JMCE.

JZlLJZ source, target

JBT ILJBT

JZ (jump if zero) effects a transfer to the target
location if the source operand is zero; otherwise
the instruction following JZ is executed. Word
and byte values may be tested by alternate
instructions:

JBT (jump if bit true) tests a single bit in the
source operand and jumps to the target if the bit
is a 1. The source must be a byte in memory or in
an I/O device register. The bit-select value may
range from 0 through 7, with 0 specifying the loworder bit. This instruction may be used to test a
bit in an 8-bit device register. If the target is the
JBT instruction itself, the operation effectively
becomes "wait until bit is 0."

JZ/LJZ
JZB/LJZB

Jump/Long Jump if Word Zero
Jump/Long Jump if Byte Zero

If the source operand is a register, only the loworder 16 bits are tested; any additional high-order
bits in the register are ignored. To test the loworder byte of a register, clear bits 8-15 and then
use the word form of the instruction.

JNZlLJNZ

source, bit-select, target

JNBT ILJNBT

source, bit-select, target

This instruction operates exactly like JBT, except
that the transfer is made if the bit is not true, i.e.,
if the bit is O.

source, target

Processor Control Instructions

JNZ operates exactly like JZ except that control is
transferred to the target if the source operand
does not contain all O-bits. Word and byte sources
may be tested using these mnemonics:

These instructions enable channel programs to
control lOP hardware facilities such as the LOCK
and SINTRI-2 pins, logical bus width selection,
and the initiation of a DMA transfer.

JNZlLJNZ

Jump/Long Jump if Word Not
Zero
JNZB/LJNZB Jump/Long Jump if Byte Not
Zero.

JMCE/LJMCE

TSL destination, set-value, target

Figure 3-38 illustrates the operation of the TSL
(test and set while locked) instruction. TSL can be
used to implement a semaphore variable that
controls access to a shared resource in a
multiprocessor system (see section 2.5). If the
target operand specifies the address of the TSL
instruction, the instruction is repetively executed
until the semaphore (destination) is found to contain zero. Thus the channel program does not
proceed until the resource is free.

source, target

This instruction (jump if masked compare equal)
effects a transfer to the target location if the
source (a memory byte) is equal to the lower byte
in register MC as masked by the upper byte in
MC. Figure 3-15 illustrates how O-bits in the
upper half of MC cause the corresponding bits in
the lower half of MC and the source operand to
compare equal, regardless of their actual values.
For example, if bits 8-15 of MC contain the value
01H, then the transfer will occur if bit 0 of the
source and register MC are equal. This instruction
is useful for testing multiple bits in 8-bit device
registers.

WID

source-width, dest-width

WID (set logical bus widths) alters bits 0 and 1 of
the PSW, thus specifying logical bus widths for a
DMA transfer. The operands may be specified as

3-49

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

ACTIVATE

COCK

FETCH
DESTINA TlON

# OH

DE·ACTIVATE
LOCK

ASSIGN,
SET·VALUETO
DESTINA TION

STORE
OESTINA TION

DE·ACTIVATE

meR

NEXT SEQUENTIAL INSTRUCTION

Figure 3-38. Operation of TSL Instruction

8 or 16 (bits), with the restriction that the logical
width of a bus cannot exceed its physical width.
The logical bus widths are undefined following a
processor RESET; therefore the WID instruction
must be executed before the first transfer.
Thereafter the logical widths retain their values
until the next WID instruction or processor
RESET.

the instruction following XFER may ready the
synchronizing device (e.g., send a "start" command or the last of a series of parameters). Any
instruction, including NOP and WID, may follow
XFER, except an instruction that alters GA, GB
orGC.

XFER (no operands)

SINTR

XFER (enter DMA transfer mode after following
instruction) prepares the channel for a DMA
transfer operation. In a synchronized transfer,

This instruction sets the interrupt service bit in the'
PSW and activates the channel's SINTR line if
the interrupt control bit in the PSW is set. If the

Mnemonics © Intel, 1979

3-50

(no operands)

8089 INPUT /OUTPUT PROCESSOR

with the instruction name. For every combination
of operand types (see table 3-15 for key), the
instruction's execution time and its length in
bytes, and a coding example are provided.

interrupt control bit is cleared (interrupts from
this channel are disabled), the interrupt service bit
is set, but SINTRI-2 is not activated. A channel
program may use this instruction to interrupt a
CPU.

The instruction timing figures are the number of
clock periods required to execute the instruction
with the given combination of operands. At
5 MHz, one clock period is 200 ns; at 8 MHz a
clock period is 125 ns. Two timings are provided
when an instruction operates on a memory word.
The first (lower) figure indicates execution time
when the word is aligned on an even address and
is accessed over a 16-bit bus. The second figure is
for odd-addressed words on 16-bit buses and any
word accessed via an 8-bit bus.

NOP (no operands)

This instruction consumes clock cycles but performs no operation. As such, it is useful in timing
loops.

HLT (no operands)
This instruction concludes a channel program.
The channel clears its BUSY flag and then idles.

Instruction fetch time is shown in table 3-17 and
should be added to the execution times shown in
table 3-16 to determine how long a sequence of
instructions will take to run. (Section 3.2 explains
the effect of the instruction queue on 16-bit
instruction fetches.) External delays such as bus
arbitration, wait states and activity on the other
channel will increase the elapsed time over the
figures shown in tables 3-16 and 3-17. These
delays are application dependent.

Instruction Set Reference Information
Table 3-16 lists every 8089 instruction
alphabetically by its ASM-89 mnemonic. The
ASM-89 coding format is shown (see table 3-14
for an explanation of operand identifiers) along

Table 3-14. Key to ASM-89 Operand Identifiers
USED IN

IDENTIFIER

EXPLANATION

destination

data transfer,
arithmetic,
bit manipulation

A register or memory location that may contain data operated on
by the instruction, and which receives (is replaced by) the result
of the operation.

source

data transfer,
arithmetic,
bit manipulation

A register, memory location, or immediate value that is used in
the operation, but is not altered'by the instruction.

target

program transfer

Location to which control is to be transferred.

TPsave

program transfer

A 24-bit memory location where the address of the next sequential instruction is to be saved.

bit-select

bit manipulation

Specification of a bit location within a byte; O=least-significant
(rightmost) bit, 7=most-significant (leftmost) bit.

set-value

TSL

Value to which destination is set if it is found O.

source-width

WID

Logical width of source bus.

dest-width

WID

Logical width of destination bus.

3-51

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

Table 3-15. Key to Operand Types
IDENTIFIER

EXPLANATION

(no operands)

No operands are written

register

Any general register

ptr-reg

A pointer register

immed8

A constant in the range O-FFH

immed16

A constant in the range O-FFFFH

mem8

An 8-bit memory location (byte)

mem16

A 16-bit memory location (word)

mem24

A 24-bit memory location (physical address pointer)

mem32

A 32-bit memory location (doubleword pointer.)

label

A label within -32,768 to +32,767 bytes of the end of the instruction

short-label

A label within -128 to +127 bytes of the end of the instruction

0-7

A constant in the range: 0-7

8/16

The constant 8 or the constant 16

Table 3-16. Instruction Set Reference Data

ADD

Operands
register, mem16
mem16, register

ADDB

register, mem8
mem8, register

Bytes

11/15
16/26

2-3
2-3

register, immed8
mem8, immed8

Clocks

Bytes

11
16

2-3
2-3

register, immed16
mem16, immed16

Mnemonics © Intel, 1979

ADD BC, [GA].LENGTH
ADD [GBJ, GC

Coding Example
ADDB GC, [GA].N_CHARS
ADDB [PP].ERRORS, MC

Add Byte Immediate
Clocks

Bytes

3
16

3
3-4

Coding Example
ADDBI MC,10
ADDBI [PP+IX+].RECORDS,2CH

Add Word Immediate

destination, source
Operands

Coding Example

Add Byte Variable

destination, source
Operands

ADDI

Clocks

destination, source
Operands

ADDBI

Add Word Variable

destination, source

Clocks

Bytes

3
16/26

4
4-5

3-52

Coding Example
ADD I GB,OC25BH
ADDI [GB].POINTER,5899

8089 INPUT /OUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

AND

destination, source
Operands

register, mem16
mem16, register

ANDB

register, mem8
mem8, register

ANDBI

register, immed8
mem8, immed8

ANDI

11/15
16/26

2-3
2-3

register, immed16
mem16, immed16

CALL

Clocks

Bytes

11
16

2-3
2-3

mem24, label

Clocks

Bytes

3
16

3
3-4

mem8,0-7

Clocks

Bytes

3
16/26

4
4-5

AND BC, [GC]
AND [GA+IX].RESUlT, GA

Coding Example
GA,01100000B
[GC+IX],2CH

Coding Example
IX,OH
[GB+IX].TAB,40H

Call
Clocks

Bytes

17/23

3-5

Coding Example
CAll [GC+IX].SAVE, GET_NEXT

Clear Bit To Zero
Clocks

Bytes

16

2-3

destination
Operands

Coding Example

logical AND Word Immediate

destination, bit select
Operands

AND MC, [GA].FlAG_WORD
AND [GC].STATUS, BC

logical AND Byte Immediate

TPsave, target
Operands

Coding Example

logical AND Byte Variable

destination, source
Operands

register
mem16

Bytes

destination, source
Operands

DEC

Clocks

destination, source
Operands

CLR

logical AND Word Variable

Coding Example
ClR [GAl. 3

Decrement Word By 1
Clocks

Bytes

3
16/26

2
2-3

3-53

Coding Example
DEC [PP].RETRY

Mnemonics © Intel, 1979

8089 INPUTIOUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

DECB

Operands
mema

HLT

(no operands)

register
mem16

INCB

16

2-3

mema

Clocks

Bytes

11

2

mema, 0-7, label

JMCE

Clocks

Bytes

3
16/26

2
2-3

mema, label

JMCNE

Clocks

Bytes

16

2-3

memB, label

Clocks

Bytes

14

3-5

label

Mnemonics © Intel, 1979

Coding Example
INC GA
INC [GAl.COUNT

Coding Example
INCB [GBl.POINTER

Coding Example

JBT [GA].RESULLREG, 3, DATA_VALID

Jump if Masked Compare Equal
Clocks

Bytes

14

3-5

Coding Example
JMCE [GBl.FLAG, STOP _SEARCH

Jump if Masked Compare Not Equal
Clocks

Bytes

14

3-5

target
Operands

HLT

Jump if Bit True (1)

source, target
Operands

Coding Example

Increment Byte by 1

source, target
Operands

DECB [GA+IX+l.TAB

Increment Word by 1

source, bit-select, target
Operands

Coding Example

Halt Channel Program

destination
Operands

JMP

Bytes

destination
Operands

JBT

Clocks

(no operands)
Operands

INC

Decrement Byte By 1

destinlltion

Coding Example
JMCNE [GB+IX], NEXT_ITEM

Jump Unconditionally
Clocks

Bytes

3

,3-4

3-54

Coding Example
JMP READ_SECTOR

8089 INPUT/OUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

JNBT

source, bit-select, target
Operands

mem8, 0-7, label

JNZ

Clocks

Bytes

14

3-5

source, target
Operands

register, label
mem16, label

JNZB

mem8, label

Clocks

Bytes

5
12/16

3-4
3-5

register, label
mem16, label

JZB

Clocks

Bytes

12

3-5

mem8, label

LCALL

Clocks

Bytes

5
12/16

3-4
3-5

mem24, label

LJBT

Clocks

Bytes

12

3-5

mem8, 0-7, label

LJMCE
mem8, label

JNZB [GAl. MORE_DATA

Coding Example
JZ BC, NEXT_LINE
JZ [GC+IX].INDEX, BUF _EMPTY

Coding Example
JZB [PP].L1NES_LEFT, RETURN

Clocks

Bytes

Coding Example

17/23

4-5

LCALL [GC].RETURN_SAVE,INIT_8279

Long Jump if Bit True (1)
Clocks

Bytes

14

4-5

Coding Example
LJBT [GA].RESULT, 1, DATA_OK

Long jump if Masked Compare Equal

source, target
Operands

Coding Example

Long Call

source, bit-select, target
Operands

JNZ BC, WRITE_LINE
JNZ [PP].NUM_CHARS, PUT _BYTE

Jump if Byte Zero

TPsave, target
Operands

Coding Example

Jump if Word is Zero

source, target
Operands

JNBT [GC], 3, RE_READ

Jump if Byte Not Zero

source, target
Operands

Coding Example

Jump if Word Not Zero

source, target
Operands

JZ

Jump if Bit Not True (0)

Clocks

Bytes

14

4-5

3-55

Coding Example
LJMCE [GBl. BYTE_FOUND

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

LJMCNE

source, target

Operands
mem8, label

LJMP
label

LJNBT

Operands

LJNZ

14

4-5

Operands

LJNZB

Clocks

Bytes

3

4

mem8, label

Clocks

Bytes

14

4-5

register, label
mem16, label

Clocks

Bytes

5

4
4-5

12/16

mem8, label

ptr-reg, mem32

Coding Example
LJNZ BC, PARTIAL_XMIT
LJNZ [GA+IXl.N_LEFT, PUT_DATA

Bytes

Coding Example

12

4-5

LJNZB [GB+IX+l.ITEM, BUMP_COUNT

Long Jump if Word Zero
Clocks

Bytes

5

4
4-5

12/16

Coding Example
LJZ IX, FIRST_ELEMENT
LJZ [GBl.XMIT_COUNT, NO_DATA

Long Jump if Byte Zero
Clocks

Bytes

12

4-5

Coding Example
LJZB [GAl, RETURN_LINE

Load Pointer With Doubleword Variable
Clocks

Bytes

20/28'

2-3

*20 clocks if operand is on even address; 28 if on odd address
Mnemonics © Intel, 1979

Coding Example
LJNBT [GCl, 6, CRCC_ERROR

Clocks

destination, source
Operands

LJMP GET _CURSOR

Long Jump if Byte Not Zero

source, target
Operands

Coding Example

Long Jump if Word Not Zero

source, target
Operands

LJMCNE [GC+IX+], SCAN_NEXT

Long Jump if Bit Not True (0)

source, target
Operands

Coding Example

Long Jump Unconditional

source, target

register, label
mem16, label

LPD

Bytes

source, bit-select, target

mem8, 0-7, label

LJZB

Clocks

target
Operands

LJZ

Long jump if Masked Compare Not Equal

3-56

Coding Example
LPD GA, [PPl.BUF _START

8089 INPUT /OUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

LPDI

destination, source
Operands

ptr-reg, immed32

Load Pointer With Doubleword Immediate
Clocks

Bytes

12/16'

6

Coding Example

LPDI GB, DISK_ADDRESS

'12 clocks if instruction is on even address; 16 if on odd address

MOV

destination, source
Operands

register, mem16
mem16, register
mem16, mem16

MOVB

register, mem8
mem8, register
mem8, mem8

MOVBI

Bytes

8/12
10/16
18/28

2-3
2-3
4-6

register, immed8
mem8, immed8

Bytes

8
10
18

2-3
2-3
4-6

Operands

Bytes

3
12

3
3-4

ptr-reg, mem24
mem24, ptr-reg

MOVB BC, [PP].TRAN_COUNT
MOVB [PP].RETURN_CODE, GC
MOVB [GB+IX+J, [GA+IX+]

Coding Example

MOVBI MC, 'A'
MOVBI [PP].RESULT,O

Move Word Immediate
Clocks

Bytes

3
12/18

4
4-5

Coding Example

MOVI BC,O
MOVI [GBJ, OFFFFH

Move Pointer

destination, source
Operands

Coding Example

Move Byte Immediate
Clocks

destination, source

register, immed16
mem16, immed16

Coding Example

MOV IX, [GC]
MOV [GA].COUNT, BC
MOV [GA].READING, [GB]

Move Byte
Clocks

destination, source
Operands

MOVP

Clocks

destination, source
Operands

MOVI

Move Word

Clocks

Bytes

19/27'
16/22'

2-3
2-3

Coding Example

MOVP TP, [GC+IX]
MOVP [GB].SAVE_ADDR, GC

'First figure is for operand on even address; second is for odd-addressed operand.

NOP

No Operation

(no operands)
Operands

(no operands)

Clocks

Bytes

4

2

3-57

Coding Example

NOP

Mnemonics © Intel, 1979

8089 INPUT IOUTPUT PROCESSOR

Table 3-16. Instruction Set Reference Data (Cont'd.)

NOT

Operands
register
mem16
register, mem16

NOTB

mem8
register, mem8

Bytes

3
16/26
11/15

2
2-3
2-3

register, mem16
mem16, register

ORB

Bytes

16
11

2-3
2-3

register, mem8
mem8, register

ORBI

Clocks

Bytes

11/15
16/26

2-3
2-3

Operands

Bytes

11
16

2-3
2-3

Operands

SETB

Clocks

Bytes

3
16

3
3-4

mem8,0-7

SINTR

Clocks

Bytes

3
16/26

4
4-5

(no operands)

Mnemonics © Intel. 1979

Coding Example
ORB IX, [PP].POINTER
ORB [GA+IX+], GB

Coding Example
ORBI IX,00010001B
ORBI [GB].COMMAND,OCH

Coding Example
ORI MC, OFFODH
ORI [GA], 1000H

Set Bit to 1
Clocks

Bytes

16

2-3

(no operands)
Operands

OR MC, [GC].MASK
OR [GC], BC

Logical OR Word Immediate

destination, bit-select
Operands

Coding Example

Logical OR Byte Immediate

destination, source

register, immed16
mem16,immed16

NOTB [GA].PARM_REG
NOTB IX, [GB].STATUS

Logical OR Byte
Clocks

destination, source

register, immed8
mem8, immed8

Coding Example

Logical OR Word

destination, source
Operands

Coding Example
NOT MC
NOT [GA].PARM
NOT BC, [GA+IX].LlNES_LEFT

Logical NOT Byte

Clocks

destination, source
Operands

ORI

Clocks

destination / destination, source
Operands

OR

Logical NOT Word

destination/destination, source

Coding Example
SETB [GA].PARM_REG,2

Set Interrupt Service Bit
Clocks

Bytes

4

2

3-58

Coding Example
SINTR

8089 INPUT /OUTPUT PROCESSOR

Table3-16. Instruction Set Reference Data (Cont'd.)

TSL

destination, set-value, target
Operands

mem8, immed8, short-label
*14 clocks if destination

WID

Test and Set While Locked
Clocks

Bytes

14/16*

4-5

*" 0; 16 clocks if destination = 0

source-width, dest-width

Set Logical Bus Widths

Operands

Clocks

Bytes

4

2

8/16,8/16

XFER

(no operands)

Coding Example
WID 8,8

Enter DMA Transfer Mode After Next Instruction

Operands

Clocks

Bytes

4

2

(no operands)

BUSWIDTH
16

8

Coding Example
XFER

nel processes different types of operands and how
it calculates addresses using its addressing modes.
Section 3.9 describes the ASM-89 conventions
that programmers use to specify these operands
and addressing modes.

Table 3-17. Instruction Fetch Timings
(Clock Periods)
INSTRUCTION
LENGTH
(BYTES)

Coding Example
TSL [GAj.FLAG,OFFH, NOT_READY

(1)

(2)

7
14
14
18

11
11
15
15

Register and Immediate Operands
2
3
4
5

14
18
22
26

(1)

First byte of instruction is on an even
address.

(2)

First byte of instruction is on an odd address.
Add 3 clocks if first byte is not in queue (e.g.,
first instruction following program transfer).

Registers may be specified as source or destination operands in many instructions. Instructions
that operate on registers are generally both
shorter and faster than instructions that specify
immediate or memory operands.
Immediate operands are data contained in
instructions rather than in registers or in memory.
The data may be either 8 or 16 bits in length. The
limitations of immediate operands are that they
may only serve as source operands and that they
are constant values.

3.8 Addressing Modes

Memory Addressing Modes

8089 instruction operands may reside in registers,
in the instruction itself or in the system or I/O
address spaces. Operands in the system and I/O
spaces may be either memory locations or I/O
device registers and may be addressed in four different ways. This section describes how the chan-

Whereas the channel has direct access to register
and immediate operands, operands in the system
and I/O space must be transferred to or from the
lOP over the bus. To do this, the lOP must
calculate the address of the operand, called its
3-59

Mnemonics © Intel, 1979

8089 INPUT IOUTPUT PROCESSOR

Based Addressing

effective address (EA). The programmer may
specify that an operand's address be calculated in
any of four different ways; these are the 8089'8
memory addressing modes.

In based addressing (figure 3-39), the effective
address is taken directly from the content of GA,
GB, GC or PP. Using this addressing mode, one
instruction may access different locations if the
register is updated before the instruction exec~tes.
LPD, MOV,' MOVP or arithmetic instructions
might be used to change the value of the base
register.

The Effective Address
An operand in the system space has a 20-bit effective address, and an operand in the lIO space has
a 16-bit effective address. These addresses are
unsigned numbers t):lat represent the distance (in
bytes) of the low-order byte of the operand from
the beginning of the.address space. Since the 8089
does not "see" the segmented structure of the
system space that it may share with an 8086 or
8088, 8089 effective addresses are equivalent to
8086/8088 physical addresses.

Offset AddreSSing
In this mode (figure 3-40) an 8-bit unsigned value
contained in the instruction is added to the content of a base register to form the effective
address. The offset mode provides a convenient
way to address elements in structures (a
parameter block is a typical example of a structure). As shown in figure 3-41, a base register s;an
be pointed at the base (first element) in the structure, and then different offsets can be used to
access the elements within the structure. By
changing the base address, the same structure can
be relocated elsewhere in memory.

All memory addressing modes use the content of
one of the pointer registers, and the state of that
register's tag bit determines whether the operand
lies in the system or the I/O space. If the operand
is in the I/O space (tag = 1), bits 16-19 of the
pointer register .are ignored .in the effective
address calculation. Section 4.3 describes the two
fields (AA and MM) in the encoded machine
instruction that specify addressing mode and base
(pointer) register.

R/B/P WB AA W

OPCODE

MM

Indexed Addressing
An indexed address is fOlmed by adding the content of register IX (interpreted as an unsigned
quantity) to a base register as shown in figure
3-42. Indexed addressing is often used to accesS

MACHINE INSTRUCTION FORMAT

GA
OR

GB
OR

GC
OR

PP

Figure 3-39. Based Addressing
3-60

I

EA

8089 INPUTIOUTPUT PROCESSOR

MACHINE INSTRUCTION FORMAT

MM

GA
OR

GB
OR

---f--~(+

GC
OR

PP

Figure 3-40. Offset Addressing

,~

~

HIGH ADDRESSES

.----.+ 6

ERROR

+4

I

LlNECT

BUFF_PTR

+ 2 POSITIONI CURSOR

rI
I
I
I
I
I

r --+ 0

....._-.,...-_...

I
I
I
I

END_BUS
LOW ADDRESSES
~

,~

I

EA

IL_______________ I
~

Figure 3-41. Accessing a Structure with Offset Addressing

array elements (see figure 3-43). A base register
locates the beginning of the array and the value in
IX selects one element, i.e., it acts as the array
subscript. The ith element of a byte array is
selected when IX contains (i - 1). To access the
ith element of a word array, IX should contain

Indexed Auto-Increment Addressing
In this variation of indexed addressing, the effective address is formed by summing IX and a base
register, and then IX is incremented automatically. (See figure 3-44.) The addition takes place

«i - 1) * 2).

3-61

8089 INPUT /OUTPUT PROCESSOR

mode is very useful for "stepping through" successive elements of an array (e.g., a program loop
that sums an array).

after the EA is calculated. IX is incremented by 1
for a byte operation, by 2 for a word operation
and by 3 for a MOVP instruction. This addressing

.10
R/B/P WB AA W OPCODE

MM

MACHINE INSTRUCTION FORMAT

GA
OR

+-1

GB
OR

GC

IX

OR

PP

Figure 3-42. Indexed Addressing
~

HIGH ADDRESSES

IX

I

ARRAY (g)
ARRAY (8)
ARRAY (7)

I

r
I
I
I
I
I
I

ARRAY (6)
ARRAY (5)

EA

I

•

ARRAY (4)
ARRAY (3)

I

ARRAY (2)

I
I
I
I

ARRAY (1)

-----.

ARRAY (0)
_lWORD_

"

LOW ADDRESSES

,"

Figure 3-43. Accessing a Word Array with Indexed Addressing
3-62

8089 INPUT /OUTPUT PROCESSOR

R/B/P WB AA W

OPCODE

MM

MACHINE INSTRUCTION FORMAT

GA
OR

GB
OR

GC
OR

PP

EA

~___IX____~~~__D_EL_T_A__~
Figure 3-44. Indexed Auto-Increment Addressing

3.9 Programming Facilities

ASM-89

The ASM-89 assembler reads a disk file containing 8089 assembly language statements, translates
these statements into 8089 machine instructions,
and writes the result into a second disk file. The
assembly input is called a source module, and the
principal output is a relocatable object module.
The assembler also produces a file that lists the
module and flags any errors detected during the
assembly.

The compatibility of the 8089 with the 8086 and
8088 extends beyond the hardware interface.
Comparing figure 3-45, with figure 2-45, one can
see that, except for the translate step, the software
development process is identical for both
8086/8088 and 8089 programs. The ASM-89
assembler produces a relocatable object module
that is compatible with the 8086 family software
development utilities LIB-86, LINK-86, LOC-86
and OH-86, described in section 2.9. All of these
development tools run on an Intellec® 800 or
Series II microcomputer development system.

Statements

Statements are the building blocks of ASM-89
programs. Figure 3-46 shows several examples of
ASM-89 statements. The ASM-89 assembler gives
programmers considerable flexibility in formatting program statements. Variable names and
labels (identifiers) may be up to 31 characters
long, the underscore (_) character may be used
to improve the readability of longer names (e.g.,

This section surveys the facilities of the ASM-89
assembler and discusses how LINK-86 and
LOC-86 can be used in 8089 software development. For a complete description of the 8089
assembly language, consult 8089 Assembly
Language User's Guide, Order No. 9800938,
available from Intel's Literature Department.

3-63

8089 INPUT /OUTPUT PROCESSOR

WAIT_UNTIL_READY). The component
parts of statements (fields) need not be located at
particular "columns" of the statement. Any
number of blank characters may separate fields

and multiple identifiers within the operand field.
Long statements may be continued onto the next
link by coding an ampersand (&) as the first
character of the continued line.

(FROM PL/M·88 Ii ASM-8a TRANSLATORS)

EDIT

TRANSLATE

LINK

.....-1-1

LlNK-86

Figure 3-45. 8089 Software Development Process

; THIS STATEMENTCONTAINSACOMMENT FIELD ONLY
ADDI BC,5
; TYPICAL ASM89 INSTRUCTION
BC,
5
; NO "COLUMN" REQUIREMENTS
ADDI
[GAl.STATUS,
MOV
&
6
; A CONTINUED STATEMENT
SOURCE
EQU GA
; A SIMPLE ASM89 DIRECTIVE
L1NE_BUFFER_ADDRESS DD ; A LONG IDENTIFIER

Figure 3-46. ASM-89 Statements
Mnemonics © Intel, 1979

3-64

8089 INPUT/OUTPUT PROCESSOR

A statement whose first non-blank character is a
semicolon is a comment statement. Comments
have no affect on program execution and, in fact,
are ignored by the ASM-89 assembler. Nevertheless, carefully selected comments are included
in all well written ASM-89 programs. They summarize, annotate and clarify the logic of the program where the instructions are too
"microscopic" to make the operation of the program self-evident.

tion as long as bit 3 of the byte addressed by
[GAl.STATUS is not true. The mnemonic field of
an instruction statement specifies the type of 8089
machine instruction that the assembler is to build.

An ASM-89 instruction statement (figure 3-47)
directs the assembler to build an 8089 machine
instruction. The optional label field assigns a
symbolic identifier to the address where the
instruction will be stored in memory. A labelled
instruction can be the target of a program
transfer; the transferring instruction specifies the
label for its target operand. In figure 3-47 the
labelled instruction conditionally transfers to
itself; the program will loop on this one instruc-

An ASM-89 directive statement (figure 3-48) does
not produce an 8089 machine instruction. Rather,
a directive gives the assembler information to use
during the assembly. For example, the DS (define
storage) directive in figure 3-48 tells the assembler
to reserve 80 bytes of storage and to assign a symbolic identifier (INPUT_BUFFER) to the first
(lowest-addressed) byte of this area. The ASM-89
assembler accepts 14 directives; the more commonly used directives are discussed in this section.

The operand field may contain no operands or
one or more operands as required by the instruction. Multiple operands are separated by commas
and, optionally, by blanks. Any instruction statement may contain a comment field (comment
fields are initiated by a semicolon).

;WAIT UNTIL READY

[

I

COMMENT (OPTIONAL)

OPERANDS (REQUIRED/PROHIBITED)
L . . . - - - - - - - - - - - - - - - M N E M O N I C (REQUIRED)
' - - - - - - - - - - - - - - - - - - - - LABEL (OPTIONAL)

Figure 3-47. ASM-89 Instruction Format

INPUT_BUFFER:

DS

80
COMMENT (OPTIONAL)
1...-_ _ _ _ _ _

L..-_ _ _ _ _ _ _ _ _

OPERANDS (REQUIRED/PROHIBITED)
MNEMONIC (REQUIRED)

" ' - - - - - - - - - - - - - -___ LABEL/NAME (REQUIRED/PROHIBITED)

Figure 3-48. ASM-89 Directive Format
3-65

Mnemonics © Intel, 1979

8089 INPUTIOUTPUT PROCESSOR

As an aid to program clarity, The EQU (equate)
directive may be used to give names to constants
(e.g., DISK_STATUS EQU OFF20H).

The first field in. a directive may be a label or a
name; individual directives may require or prohibit names, while labels are optional for directives.that accept them. A label ends in a colon like
an instruction statement label. However, a directive label cannot be specified as the target of a
program transfer. A name does not have a colon.
The second field is the directive mnemonic, and
the assembler distinguishes between instructions
and directives by this field. Any operands
required by the directive are written next; multiple
operands are separated by commas and, optionally, l>Y blanks. A comment may be included in
any directive by beginning the text with a
semicolon.

Defining Data

Four ASM-89 directives reserve space for memory
variables in the ASM-89 program (see figure
3-50). The DB,DW and DD directives allocate
units of bytes, words and doublewords, respectively, initialize the locations, and optionally label
them so that they may be referred to by name in
instruction statements. The label of a storage
directive always refers to the first (lowestaddressed) byte of the area reserved by the
directive.
The DB and DW directives may be used to define
byte- and word-constant scalars (individual data
items) and arrays (sequences of the same type of
item). For example, a character string constant
could be defined as a byte array:

Constants

Binary, decimal, octal and hexadecimal numeric
constants (figure 3-49) may be written in ASM-89.
instructions and directives. The assembler can
add and subtract constants at assembly time.
Numeric constants,including the· results of
arithmetic operations, must be representable in 16
bits. Positive numbers cannot exceed 65,535
(decimal); negative numbers, whieh the assembler
represents in two's complement notation, cannot
be "more negative" than -32,768 (decimal).

SIGN_ON_MSG: DB 'PLEASE ENTER PASSWORD'

The DD directive is typically used to define the
address of a location in the system space, i.e., a
doubleword pOinter variable. The address may be
loaded into a pointer register with the LPD
instruction.
The DS directive reserves, and optionally na~es,
storage in units of bytes, but does not initialize
any of the reserved bytes. DS is typically used for
RAM-based variables such as buffers. As there is
no special directive for defining a physical address
pointer, DS is typically used to reserve the three
bytes used by the MOVP instruction.

Character constants are enclosed in single quote
marks as shown in figure 3-49. Strings of
characters up to 255 bytes long may be written
when initializing storage. Instruction operands,
however, can only be one or two characters long
(for byte and word instructions respectively).

MOVBI
GA, 'A'
; CHARACTER
MOVBI
GA, 41 H
; HEXADECIMAL
GA, 65
; DECIMAL
MOVBI
GA,65D
; DECIMAL ALTERNATIVE
MOVBI
GA,101Q
; OCTAL
MOVBI
MOVBI
GA, 1Q1 0
; OCTAL ALTERNATIVE
MOVBI
GA, 01000001 B ; BINARY
; NEXT TWO STATEMENTS ARE EQUIVALENT AND
ILLUSTRATE TWO'S COMPLEMENT REPRESENTATION
,
OF NEGATIVENUMI3ERS
GA,-5
MOVBI
MOVBI
GA,11111011B

Figure 3-49. ASM89 Constants
Mn~monics

© Intel, 1979

3-66

8089 INPUT/OUTPUT PROCESSOR

; ASM89 DIRECTIVE
1
ALPHA: DB
-2
DB
DB
'A', 'B'
BETA:
DW
1
-5
DW
'AB'
DW
DW
400,500
DW
400H,500H
gamma: DW
BETA
DELTA

DD

GAMMA

ZETA:

DS

80

; MEMORY CONTENT (HEX)
; 01
; FE (TWO'S COMPLEMENT)
; 4142
; 0100
; FAFF
; 4241
; 2410F401
; 00040005
; OFFSET OF BET A ABOVE,
; FROM BEGINNING OF PROGRAM
; ADDRESS (SEGMENT & OFFSET)
;OFGAMMA
; 80 BYTES, UNINITIALIZED

Figure 3-50. ASM-89 Storage Directives

Structures

assembler uses the structure element name to produce an offset value (structures are used with the
offset addressing mode). Compared to "hard·
coded" offsets, structures improve program clarity and simplify maintenance. If the layout of a
memory block changes, only the structure definition must be modified. When the program is
reassembled, all symbolic references to the structure are automatically adjusted. When multiple
areas of memory are laid out identically, a single
structure can be used to address any area by
changing the content of the pointer (base) register
that specifies the structure's "starting address."

An ASM-89 structure is a map or template that
gives names and relative locations to a collection
of related variables that are called structure
elements or members. Defining a structure,
however, does not allocate storage. The structure
is, in effect, overlaid on a particular area of
memory when one of its elements is used as an
instruction operand. Figure 3-51 shows how a
structure representing a parameter block could be
defined and then used in a channel program. The
MEMORY MAP

OFFSETS.

+10

+8

HIGHER ADDRESSES

STRUCTURE DEFINITION

BUFFER_LEN

PARM_BLOCK
TP _RESERVED:
COMMAND:
RESULT:
BUFFER_START:
BUFFER_LEN:
PARM_BLOCK

BUFFER_START

+6

+4

,

COMMAND

I

RESULT

STRUC
OS
4
OS
1
OS
1
OS
4
OS
2
ENDS

+2
TP _RESERVED

LOWER ADDRESSES

USING "HARD-CODED" OFFSETS

USING STRUCTURE ELEMENT NAMES

LPD GA, [PPJ.6
MOVBI [PPJ.5,O

LPD GA, [PPJ.BUFFER_START
MOVBI [PPJ.RESULT,O

Figure 3-51. ASM-89 Structure Definition and Use

3-67

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

Addressing Modes

Note that any pointer register could have been
substituted for GA in the previous examples.

Table 3-18 summarizes the notation a programmer uses to specify how the effective address of a
memory operand is to be computed. Examples of
typical ASM-89 coding for each addressing mode,
as well as register and immediate operands, are
provided in figure 3-52._Notice that a bracketed
reference to a register indicates that the content of
the register is to be used to form the effective
address of a memory operand, while an
unbracketed register reference specifies that the
register itself is the operand.

Table 3-18. ASM-89 Memory Addressing
Mode Notation
Notation
[ptr-reg]
[ptr-reg].offset
[ptr-reg + IX]
[ptr-reg + IX +]

The following examples summarize how the
memory addressing modes can be used to access
simple variables, structures and arrays.
•

If GA contains the address of a memory
operand, then [GA] refers to that operand.

•

If GA contains the base address of a

ptr-reg
offset

GA,5
GC, [GB]
[PP],10
IX, [GB].5
BC, [GC].COUNT
[GC+ IX], BC
[GA+ IX+ ],5
[PP].ERROR, [GA]

or PP
8-bit signed value; may be structure element

= GA, GB, GC
=

As discussed in section 3.7, program transfer
instructions operate by adding a signed byte or
word displacement to the task pointer. Table 3-19
shows how the ASM-89 assembler determines the
sign and size of the displacement value it places in
a program transfer machine instruction. In the
table, the terms "backward" and "forward"
refer to the location of a label specified as a
transfer target relative to the transfer instruction.
"Backward" means the label physically precedes
the instruction in the source module, and "forward" means the label follows the instruction in
the source text. The distances are from the end of
the transfer instruction; the distance to the
instruction immediately following the transfer is
obytes.

If GA contains the starting address of an
array, then [GA+IX] addresses the array element indexed by IX. For example, if IX con- .
tains the value 4H, the effective address
refers to the fifth element of a byte array, or
the third element of a word array. [GA+IX+]
selects the same element and additionally
auto-increments IX by 1 (byte operation), 2
(word operation) or 3 (MOVP instruction) in
anticipation of accessing the next array
element.

ADDI
ADD
ADDBI
ADDB
ADDB
ADD
ADDI
ADDB

Based
Offset
Indexed
Indexed Post Auto-increment

Program Transfer Targets

structure, then [GA].DATA refers to the
DAT A element (field) in that structure. If
DAT A is six bytes from the beginning of the
structure, then [GA].6 refers to the same
location.
•

Addressing Mode

; REGISTER, IMMEDIATE
; REGISTER, MEMORY (BASED)
; MEMORY (BASED), IMMEDIATE
; REGISTER, MEMORY (OFFSET)
; REGISTER, MEMORY (OFFSET)
; MEMORY (INDEXED), REGISTER
; MEMORY (INDEXED AUTO-INCREMENT), IMMED
; MEMORY (OFFSET), MEMORY (BASED)

Figure 3-52. ASM-89 Operand Coding Examples
Mnemonics © Intel, 1979

3-68

8089 INPUTIOUTPUT PRO.CESSOR
issue a "suspend" command to the channel; this
command stores the current value of TP in the
same location, possibly overwriting a return
address.

Two important points can be drawn from table
3-19. First, a target must lie within 32k bytes of a
transfer instruction; this should not prove restrictive except in very large programs. Second, one
byte can be saved in the assembled instruction by
writing the short mnemonic when the target is
known to be within -128 through +127 assembled
bytes of the transfer.

As in any program transfer, the target of a
CALL/LCALL instruction must be contained in
the same module and within 32k bytes of the
instruction.

It is also important to note that a program

transfer target must reside in the same module as
the transferring instruction, i.e., the target
address must be known at assembly time.

Segment Control
The relocatable object module produced by the
ASM-89 assembler consists of a single logical segment. (A segment is a storage unit up to 64k bytes
long; for a more complete description, refer to
sections 2.3 and 2.7.) The ASM-89 SEGMENT
and ENDS directives name the segment as shown
in figure 3-54. Typically, all instructions and most
directives are coded in between these directives.
The END directive, which terminates the
assembly, is an exception.

Procedures
An ASM-89 program may invoke an out-of-line
procedure (subroutine) with the CALLILCALL
instruction. The first instruction operand
specifies a memory location where the content of
TP will be stored as a physical address pointer
before control is transferred to the procedure.
The procedure may return to the instruction
following the CALL/LCALL by using the
MOVP instruction to restore TP from the save
area. Figure 3-53 illustrates one approach to procedure linkage.

The LOC-86 utility can assign this logical segment
to any memory address that is a physical segment
boundary (i.e., whose low-order four bits are
0000). In a ROM-based system, variable data
(which must be in RAM) can be "clustered"
together at one "end" of the program as shown in
figure 3-55. The ORG directive can then be used
to force assembly of the variables to start at a
given offset from the beginning of the segment
(2,000 hexadecimal bytes in figure 3-55). As the

A channel program may use the first two words of
its parameter block (pointed to by P.P) as a task
pointer save area. However, this is not recommended if there is any chance that the CPU will

Table 3-19. Program Transfer Displacement
Target Location
Mnemonic
Form

Short
(e.g., JMP)

Long
(e.g., LJMP)

Distance

Direction

~128

Backward
Forward
Backward
Forward
Backward
Forward

~127
~32,768

~32,767

>32,768
>32,767
~128

Backward
Forward
Backward
Forward
Backward
Forward

... 127
... 32,768
~32,767

>32,768
>32,767

3-69

Displacement
Sign Bytes

+

1
1
_. 2
Error
Error
Error

+

2
2
- 2
+ 2
Error
Error

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

CALL SAVE:

DS

3

; TP SAVE AREA

; SET UP TP SAVE AREA
NOTE: EXAMPLE ASSUMES PROGRAM
IS IN 1/0 SPACE. USE LPDI
IF IN SYSTEM SPACE.
,
MOVI GC, CALLSAVE
; LOAD ADDRESS TO GC
; CALL IT.
LCALL [GC],DEMO

HLT

; LOGICAL END OF PROGRAM

; DEFINE THE PROCEDURE.
DEMO:
; PROCEDUR.E INSTRUCTIONS GO HERE.
; NOTE: PROCEDURE MUST NOT UPDATE GC
;
AS IT POINTS TO THE RETURN ADDRESS.

; RETURN TO CALLER.
MOVP TP, [GC]

Figure 3-53. ASM-89 Procedure Example
CHANNEL1

SEGMENT

; START OF SEGMENT

ASM89 SOURCE STATEMENTS

CHANNEL1

ENDS
END

; END OF SEGMENT
; END OF ASSEMBLY

Figure 3-54. ASM-89 SEGMENT and ENDS Directives
figure shows, the segment can then be located so
that instructions and constants fall into the ROM
portion of memory, while the variable part of the
segment is located in RAM. The entire segment,
including any "unused" portions, of course, cannot exceed 64k bytes.

minimum, a channel program must make the
address of its first instruction available to the
CPU module that starts the channel program.
Figure 3-56 shows an ASM-89 module that contains three channel programs labelled READ,
WRITE and DELETE. The example shows how a
PLlM-86 program and an ASM-86 program
could define these "entry points" as EXTERNAL and EXTRN symbols respectively. When
the modules are linked together, LINK-86 will
match the externals with the publics, thus providing the CPU programs with the addresses they
need.

Intermodule Communication
An ASM-89 module can make some of its
addresses available to other modules by defining
symbols with the PUBLIC directive. At a
Mnemonics © Intel. 1979

3-70

8089 INPUT /OUTPUT PROCESSOR

DEMO: SEGMENT
;CONSTANT DATA
HIGHER ADDRESSES
;INSTRUCTIONS

(AVAILABL E)
VARIABLES

ORG 2000H
;VARIABLE DATA

2000H

t-------f
(UNUSED)

DEMO ENDS
END

t
RAM
ROM

INSTRUCTIONS
CONSTANTS
(AVAILABLE)

LOWER ADDRESSES

Figure 3-55. Using the ASM-89 ORO Directive

ASM-89 MODULE DEFINES THREE PUBLIC SYMBOLS

PUBLIC

READ, WRITE, DELETE

READ:

; ASM89 INSTRUCTIONS FOR "READ" OPERATION

WRITE:

HLT
; ASM89 INSTRUCTIONS FOR "WRITE" OPERATION

DELETE:

HLT
; ASM89 INSTRUCTIONS FOR "DELETE" OPERATION
HLT

Figure 3-56. ASM-89 PUBLIC Directive
3-71

Mnemonics © Intel, 1979

8089 INPUT /OUTPUT PROCESSOR

PLlM-86 MODULE USES "WRITE" SYMBOL
DECLARE
DECLARE

(READ,WRITE,DELETE) POINTER EXTERNAL;
PARM$BLOCK STRUCTURE
(TP$START
POINTER,
BUFFER$ADDR
POINTER,
BUFFER$LEN
WORD);

'"SET UP "WRITE" CHANNEL OPERATION"'
PARM$BLOCK. TP$START = WRITE;

ASM-86

MODULE USES "READ" SYMBOL

READ,WRITE,DELETE

EXTRN

; PARM~BLOCK
EVEN
TP_START
DD ?
BUFFER_ADDRDD ?
BUFFER_LEN DW?

; FORCE TO EVEN ADDRESS

; SET UP "READ" CHANNEL OPERATION
MOV AX, WORD PTR READ_PTR
MOV WORD PTR TP_START, AX
MOV AX, WORD PTR READ_PTR
MOV WORD PTR TP_START + 2, AX

; 1ST WORD
;2NDWORD

Figure 3-56. ASM-89 PUBLIC Directive (Cont'd.)
Conversely, an ASM-89 module can obtain the
address of a public symbol in another module by
defining it with the EXTRN directive. An external
symbol, however, can only appear as the initial
value operand of a DD directive (see figure 3-57).
This effectively means that an ASM-89 program's
Mnemonics © Intel, 1979

use of external symbols is limited to obtaining the
addresses of data located in the system space.
Another way of doing this, which may be
preferable in many cases, is to have the CPU program place system space addresses in the
parameter block.

3-72

8089 INPUT /OUTPUT PROCESSOR

PLlM-86 PROGRAM DECLARES PUBLIC SYMBOL "BUFFER"

DECLARE BUFFER (80) BYTE PUBLIC;

ASM-89 PROGRAM OBTAINS ADDRESS OF PUBLIC SYMBOL "BUFFER"

EXTRN BUFFER

BUF _ADDRESS

LPD

DO

BUFFER

GA, BU F_ADDRESS

; POINT TO SYSTEM BU FFER

Figure 3-57. ASM-89 EXTRN Directive

Sample Program
Figure 3-58 diagrams the logic of a simple
ASM-89 program; the code is shown in figure
3-59. The program reads one physical record (sector) from a diskette drive controlled by an 8271
Floppy Disk Controller. No particular system
configuration is implied by the program, except
that the 8271 resides in the lOP's 110 space.
Hardware address decoding logic is assumed to be
set up as follows:

•
•
•
•
•

reading location FFOOH selects the
status register,
writing location FFOOH selects the
command register,
reading location FFOIH selects the
result register
writing location FFOIH selects the
parameter register

8271
8271
8271
8271

decoding the address FF04H provides the
8271 DACK (DMA acknowledge) signal.

Figure 3-58. ASM-89 Sample Program Flow
3-73

Mnemonics © Intel, 1979

8089 INPUT/OUTPUT PROCESSOR

Register IX is used as a retry counter.' If the
transfer is not completed successfully (bit 3 of the
8271 result register :I: 0), the program retries the
transfer up to 10 times.

The program uses structures to address the
parameter block and the 8271 registers. Register
PP contains the address of the parameter block,
and the program loads GC with FFOOH to point
to the 8271 registers. The program's entry point
(the label START) is defined as a PUBLIC symbol so that the CPU program can place its address
in the parameter block when it starts the program.

Since the 8271 automatically requests a DMA
transfer upon receipt of the last parameter, this
parameter is sent immediately following the
XFER command.

8089 ASSEMBLER
ISIS-II 8089 ASSEMBLER V1.0 ASSEMBLY OF MODULE FLOPPY
OBJECT MODULE PLACED IN :FO:FLOPPY.OBJ
ASSEMBLER INVOKED BY ASM89 FLOPPY.A89
1

0000

2 FLOPPY
SEGMENT
3 ; •••
4 ; ••• 8089 PROGRAM TO READ SECTOR FROM FLOPPY DISK
5 ; •••

6

7 ;'"

LAY OUT PARAMETER BLOCK.
STRUC
DS
4
DS
4
DS
1
DS
1
DS
1
ENDS

8 PARM BLOCK

0000
0004
0008
0009
OOOA
OOOB

9
10,
11

0000
0001
0002
FFOO
FF04

0000

OA4F OA 00

0004

B130 OAOO

0008

5130 OOFF

OOOC

EABA 00 FC

0010

OA4E 00 12

0014

0293 08 02CE 01

001A

D130 2088

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
4,1
42
43

RESERVED TP:
BUFF PTR:
TRACK:
SECTOR:
RETURN CODE:
PARM BLOCK

; ••• LAY OUT 8271 DEV,ICE REGISTERS.
FLOPPY REGS
STRUC
COMMAND STAT:
DS
DS
PARM RESULT:
FLOPPY REGS
ENDS
;".8271 ADDRESSES.
FLOPPY REG ADDR EQU
DACK 8271
EQU

OFFOOH
OFF04H

;'.'MAKE PROGRAM ENTRY POINT ADDRESS
AVAILABLE TO OTHER MODULES.
PUBLIC
START
;"'CLEAR RETURN CODE IN PARAMETER BLOCK.
START:
MOVBI
[PP).RETURN CODE,O
;"'INITIALIZE RETRY COUNT.
MOVI
lX, 10
;"·POINT GC AT LOW-ORDER B271 REGISTER.
MOVI
GC, FLOPPY REG ADDR

; •• 'SEND COMMAND SEQUENCE TO 8271, HOLDING FINAL PARM.
; ••• WAIT UNTIL 8271 IS NOT BUSY.
RETRY:
JNBT
[GC j. COMMAND STAT, '7, RETR Y
;"'SEND "READ SECTOR, DRIVE 0" COMMAND.
MOVSI
[GCj.COMMAND STAT,012H
44 ; ".SEND TRACK ADDRESS PARAMETER.
45
MOVB
[GCj.PARM RESULT,[PP).TRACK
46
47 ; ••• LOAD CHANNEL ,CONTROL REGISTER SPECIFYING:
48
FROM PORT TO MEMORY,
SYNCHRONIZ,E ON SOURCE,
49
GA POINTS TO SOURCE,
50
51
TERMINATE ON EXT,
TERMINATION OFFSET
O.
52
MOVI
CC,08820H
53
54

Figure 3-59. ASM-89 Sample Program
Mnemonics © Intel, 1979

;LOW-ADDRESSED REGISTER
;DMA ACKNOWLEDGE

3-74

8089 INPUTlOUTPUT PROCESSOR

001E

AOOO

0020
0023

238B 04
1130 04FF

0027

AABA 00 FC

002B

6000

002D

0293 09 02CE 01

0033

6ABE 01 05

0037

A03C

0039

A840 DO

003C

EABA 00 FC

0040

OA4E 00 2C

0044

BABA 00 FC

OQ48

0292 01 02CF OA

004E

4000

0050

2048

55 ;***SET SOURCE BUS = 8, DEST BUS = 16.
56
WID
8,16
57
~8 ; ***POINT GB AT DESTINATION, GA AT SOURCE.
LPD
GB,[PP].BUFF PTR
59
MOVI
GA, DACK_827160
01
02 ;***INSURE THAT 8271 IS READY FOR LAST PARAMETER.
JNBT
[GC].COMMAND_STAT,5,WAITl
63 WAIT1:
64
05 ;***PREPARE FOR DMA.
66
XFER
67
08 ;***START DMA BY SENDING FINAL PARAMETER TO 8271.
MOVB
[GCJ.PARM_RESULT,[PP].SECTOR
69
70
71 ;***PROGRAM RESUMES HERE FOLLOWING EXT.
72
73 ;***IF TRANSFER IS OK THEN EXIT, ELSE TRY AGAIN.
JBT
[GCJ.PARM_RESULT,3,EXIT
74
75
76 ;***DECREMENT RETRY COUNT.
DEC
IX
77
78
79 ; '''TRY AGAIN IF COUNT NOT EXHAUSTED.
JNZ
80
IX, RETRY
81
~2 ; ***WAIT UNTIL 8271 IS NOT BUSY.
JNBT
[GC J. COMMAND- STAT,7,EXIT
83 EXIT:
84
85 ; ***SEND "READ RESULT" COMMAND TO 8271.
86
MOVBI
[GCJ.COMMAND_STAT,02CH
87
88 ;***WAIT FOR RESULT.
JNBT
[GCJ.COHMAND_STAT,4,WAIT2
89 WAIT2:
90
91 ;***POST RESULT IN PARAMETER BLOCK FOR CPU.
MOVB
[PP]. RETURN __CODE, [GC J. PARM_RESULT
92
93
94 ;***INTERRUPT CPU.
SINTR
95
96
97 ;***STOP EXECUTION.
HLT
98
99
100 FLOPPY
ENDS
101
END

0052

SYMBOL TABLE

-----------DEFN VALUE TYPE
10 0004
18 0000
24 FF04
83 003C
2 0000
17 0000
23 FFOO
8 0000
19 0001
9 0000
41 OOOC
13 OOOA
12 0009
31 0000
11 0008
63 0027
89 0044

SYM
SYM
SYM
SYM
SYM
STR
SYI~

STR
SYM
SYM
SYM
SYM
SYM
PUB
SYM
SYM
SYM

NAME
BUFF PTR
COMMAND STAT
DACK_8 27 1
EXIT
FLOPPY
FLOPPY REGS
FLOPPY-REG ADDR
PARM BLOCKPARM-RESULT
RESERVED TP
RETRY
RETURN CODE
SECTOR
START
TRACK
WAITl
WAIT2

ASSEMBLY COMPLETE; NO ERRORS FOUND

Figure 3-59. ASM-89 Sample Program (Cont'd.)
Mnemonics © Intel, 1979

3-75

8089 INPUT IOUTPUT PROCESSOR

external symbol (see figure 3-56), LINK-86 will
obtain the address from the ASM-89 channel program when the two are linked together. (The
ASM-89 program must, of course, define the
symbol in a PUBLIC directive.)

linking and Locating ASM-89 Modules
The LINK-86 utility program combines multiple
relocatable object modules into a single
relocatable module. The input modules may consist of modules produced by any of the 8086 family language translators: ASM-89, ASM-86, or
PLlM-86. LINK-86's principal function is to
satisfy external references made in the modules.
Any symbol that is defined with the EXTRN
directive in ASM-89 or ASM-86 or is declared
EXTERNAL in PLlM-86 is an external
reference, i.e., a reference to an address containerl in another module. Whenever LINK-86
encounters an external reference, it searches the
other modules for a PUBLIC symbol of the same
name. If it finds the matching symbol, it replaces
the external reference with the address of the
object.

Other external references may arise when one
module uses data (e.g., a buffer) that is contained
in another module, and (in PLlM-86 and
ASM-86 modules) when one module executes
another module, typically by a CALL statement
or instruction.
When an 8089 module (or modules) is to be
located in the system space, it may be linked
together with PLlM-86 or ASM-86 modules as
described above and shown in figure 3-60.
LINK-86 resolves. external references and combines the input modules into a single relocatable
object module. This module can be input to
LOC-86 (LOC-86 assigns final absolute memory
addresses to all of the instructions and data). This
absolute object module may, in turn, be processed by the OH-86 utility to translate the
module into the hexadecimal format. This format
makes the module readable (the records are written in ASCII characters) and is required by some
PROM programmers and RAM loaders. Intel's
Universal PROM Programmer (UPP) and iSBC
957™ Execution Package (loader) use the hexadecimal format.

The most common occurrence of an external
reference in a system that employs one or more
8089s is the channel .program address. In order
for a CPU program to start a channel program, it
must ensure that the address of the first channel
program instruction is contained in the first two
words of the parameter block. Since the channel
program is assembled separately, the translator
that processes the CPU program will not typically
know its address. If this address is defined as an

TO SYSTEM

SPACE

Figure 3-60. Creating a Single Absolute Object Module
3-76

8089 INPUT /OUTPUT PROCESSOR

If the 8089 code is to reside in its lIO space, a dif-

segment conflict messages from LOC-86. It
requires, however, that modules in the two spaces
not use the EXTRN/PUBLlC mechanism to refer
to each other. Modules in the same space can
define external and public symbols, however.

ferent technique is required since separate
absolute object modules must be produced for the
system and 1/0 spaces. Figure 3-61 shows how to
link and locate when there are external references
between lIO space modules and system space
modules.

External references from lIO space modules to
system space modules can be eliminated if the
CPU programs pass all system space addresses in
parameter blocks. In other words, a channel program can obtain any address in the system space if
the address is in the parameter block. Using this
approach allows the system space addresses to be
changed during execution. If the addresses are
constant values, they may also be altered as
system development proceeds without relinking
the channel programs.

The normal link and locate sequence is followed
and culminates in the production of an absolute
module in hexadecimal format. Since the records
in this file are human-readable, the file can be
edited using the ISIS-II text editor. The editing
task involves finding the 8089 lIO space records
in the file, writing them to one file, and then
writing the 8086/8088 records (destined for the
system space) to another file. MCS-86 Absolute
Object File Formats, Order No. 9800921,
available from Intel's Literature Department,
describes the records in absolute (including hexadecimal) object modules.

External references from system space modules to
addresses in the 1/0 space may be eliminated by
assigning these addresses values that are known at
assembly or compilation time. Figure 3-63
illustrates how the ASM-89 ORO directive can be
used to force the first instruction (entry point) of
a channel program to an absolute address. In the
case of the example, one module contains two
entry points labelled "READ" and "WRITE."
Assuming the module is located at absolute
address OH in the lIO space, the channel programs will begin at 200H and 600H respectively.
In the example, these values have been chosen
arbitrarily; in a typical application they would be
based on the length of the programs and the location of RAM and ROM areas. By starting the programs at fixed addresses that are known to the
CPU programs that activate them, the channel
programs can be reassembled without needing to
relink the CPU programs.

When using the previous method, it is likely that
LOC-86 will issue messages warning that
segments overlap. For example, the 8089 code
would typically be located starting at absolute
location OH of the 1/0 space. However, the
8086/8088 interrupt pointer table occupies these
low memory addresses in the system space. Since
LOC-86 has no way to know that the segment will
ultimately be located in different address spaces,
it will warn of the conflict; the warning may be
ignored.
An alternative to linking the modules together
and then separating them is to link system space
modules separately from lIO space modules as
shown in figure 3-62. This approach avoids the
manual edit of the absolute object module and the

FROM

PlIM-66

TO SYSTEM
SPACE

FROM
ASM·86

TallO
SPACE

FROM

ASM·89

Figure 3-61. Creating Separate Absolute Object Modules-External References in Relocatable
Modules
3-77

80891NPUT/OUTPUT PROCESSOR

FROM
PL/M-86
TO SYSTEM
SPACE

FROM
ASM-86

TO 1/0
SPACE

FROM

ASM-89

Figure 3-62. Creating Separate Absolute Object Modules-No External References in Relocatable
Modules·
ASM-89 ENTRY POINT DEFINITIONS

ORG200H
READ:

; INSTRUCTIONS FOR·'READ" CHANNEL PROGRAM

ORG 600H
WRITE:

; INSTRUCTIONS FOR "WRITE" CHANNEL PROGRAM

ASM-86DEFINITION OF ENTRY POINT ADDRESSES

DD 200H
DD 600H

PLlM-86 DECLARATION OF ENTRY POINT ADDRESSES

DECLARE READ$ADDR POINTER;
DECLARE WRITE$ADDR POINTER;
READ$ADDR = 200H;
WRITE$ADDR = 600H;

Figure 3-63. Using Absolute Entry Point Addresses

8089 INPUT/OUTPUT PROCESSOR

3.10 Programming Guidelines
and Examples

memory if it is on an odd address. The processor
will thus execute a partially-modified instruction
with unpredictable results.

This section provides two types of 8089 programming information. A series of general guidelines,
which apply to system and program design, is
presented first. These guidelines are followed by
specific coding examples that illustrate programming techniques that may be applied to many different types of applications.

1/0 System Design

Section 2.10 notes that I/O systems should be
designed hierarchically. Application programs
"see" only the topmost level of the structure; all
details pertaining to the physical characteristics
and operation of I/O devices are relegated to
lower levels. Figure 3-64 shows how this design
approach might be employed in a system that uses
an 8089 to perform I/O. The same concept can be
expanded to larger systems with multiple lOPs.

Programming Guidelines
The practices in this section are recommended to
simplify system development and, particularly,
for system maintenance and enhancement. Software that is designed in accordance with these
guidelines will be adaptable to the changing
environment in which most systems operate,
and will be in the best position to take
advantage of new intel hardware and software
products.

The application system is clearly separated from
the I/O system. No application programs perform I/O; instead they send an I/O request to the
I/O supervisor. (In systems with file-oriented
I/O, the request might be sent to a file system that
would then invoke the I/O supervisor.) The 1/0
request should be expressed in terms of a logical
block of data-a record, a line, a message, etc. It
should also be devoid of any device-dependent
information such as device address, sector size,
etc.

Segments
Although the lOP does not "see" the segmented
organization of system memory, it should respect
this logical structure. The lOP should only
address the system space through pointers passed
by the CPU in the parameter block. It should not
perform arithmetic on these addresses or otherwise manipulate them except for the automatic
incrementing that occurs during DMA transfers.
It is the responsibility of the CPU to pass
addresses such that transfer operations do not
cross segment boundaries.

The I/O supervisor transforms the application
program's request for service into a parameter
block and dispatches a channel program to carry
out the operation. The 1/0 supervisor controls
the channels; therefore, it knows the correspondence between channels and I/O devices,
the locations of CBs and channel programs, and
the format of all of the parameter blocks. The
I/O supervisor also coordinates channel
"events," monitoring BUSY flags and responding to channel-generated interrupt requests. The
1/0 supervisor does not, however, communicate
with I/O devices that are controlled by the channels. If the CPU performs some I/O itself (this
should be restricted to devices other than those
run by the channels), the 1/0 supervisor invokes
the equivalent of a channel program in the CPU
to do the physical I/O. Note that although the
1/0 supervisor is drawn as a single box in figure
3-64, it is likely to be structured as a hierarchy
itself, with separate modules performing its many
functions.

Self-Modifying Code
Programs that alter their own instructions are difficult to understand and modify, and preclude
placing the code in ROM. They may also inhibit
compatibility with future Intel hardware and software products.
Note also that when the 8089 is on a 16-bit bus, its
instruction fetch queue can interfere with the
attempt of one instruction to modify the next
sequential instruction. Although the instruction
may be changed in memory, its unmodified first
byte will be fetched from the queue rather than

The software interface between the CPU's I/O
supervisor and an lOP channel program should
be completely and explicitly defined in the

3-79

8089 INPUT/OUTPUT PROCESSOR

1i

APPLICATION I
SYSTEM
I

! :

-------1

APPLICATION
MODULE

APPLICATION
MODULE

APPLICATION
MODULE

1

CPU DOMAIN

I

I
I

I

1/0
SUPERVISOR

I

~----------------r==='------------------I
I
I
I
I

CPU/lOP INTERFACE

• PB

PB

~----------------------~-----------------I
CHANNEL
SUPERVISOR

I/O SYSTEM

CHANNEL
FUNCTION

CHANNEL
FUNCTION

CHANNEL
FUNCTION

lOP DOMAIN

I
I
I
I

,,

,,
,,
,,,.
,
I
I

DEVICE
CONTROLLER

DEVICE
CONTROLLER

CHANNEL 1

CHANNEL2

Figure 3-64. 8089-Based I/O System Design
3-.80

CHANNEL
FUNCTION

8089 INPUT /OUTPUT PROCESSOR

parameter block. For example, the 110 supervisor
should pass the addresses of all system memory
areas that the channel program will use. The
channel program should not be written so that it
"knows" any of these addresses, even if they are
constants. Concentrating the interface into one
place like this makes the system easier to understand and reduces the likelihood of an undesirable
side effect if it is modified. It also generalizes the
design so that it may be used in other application
systems.

o

1

For
FIXED

TP/CHANNEL STATE
SAVE AREA

2

FIXED PARMi FUNCTION
CODE

4

FIXED PARM2

6

FIXED PARM3

8

10

Figure 3-64 shows a simple channel program running on channel 1 and a more complex program
running on channel 2. Channell's program performs a single function and is therefore designed
as a simple program. The program on channel 2
performs three functions (e.g., "read," "write,"
"delete") and is structured to separate its functions. The functions might be implemented as
procedures called by the "channel supervisor"
depending on the content of the parameter block.
Notice that to the 110 supervisor, both programs
appear alike; in particular, both have a single
entry point.

RESERVED FOR
FUTURE USE

1

12

VARIABLE

For

~

VARIABLE PARAMETER
FORMAT AND SIZE
GOVERNED BY
FUNCTION CODE

1

,~

J

Figure 3-65. Variable Format Parameter Block

In some channel programs, different functions
will need different information passed to them in
the parameter block. Figure 3-65 shows. one
technique that accommodates different formats
while still allowing the channel supervisor to
determine which procedure to call from the PB.
The parameter block is divided into fixed and
variable portions, and a function code in the fixed
area indicates the type of operation that is to be
performed. Part of the fixed area has been set
aside so that additional parameters can be added
in the future.

Initialization and Dispatch
The PLlM-86 code in figure 3-66 initializes two
lOPs and dispatches two channel programs on
one of the lOPs. The same general technique can
be used to initialize any number of lOPs. The
hypothetical system that this code runs on is configured as follows:
•
•

8086 CPU (16-bit system bus);
two remote lOPs share an 8-bit local 110 bus
via the request/grant lines operating in
mode 1;

The first example in this section illustrates how a
CPU can initialize a group of lOPs and then
dispatch channel programs. This code is written
in PLlM-86.

•

8089 channel attentions are mapped into four
port addresses in the CPU's 110 space;

•

channel programs reside in the 8089 I/O
space;

The remaining examples, written in ASM-89,
demonstrate the 8089 instruction set and addressing modes in various commonly-enc0\l:ntered programming situations. These include:

•

one 8089 controls a CRT terminal, one
channel running the display, the other scanning the keyboard and building input
messages;

•

memory-to-memory transfers

•

•

saving and restoring registers

the function of the second 8089 is not defined
in the example.

Programming Examples

3-81

8089 INPUT/OUTPUT PROCESSOR

lOP were on a different 110 bus, the SOC field
would have been altered if a different
request/grant mode were being used or if the lOP
had a 16-bit I/O bus. The second lOP is a slave so
its initialization is started by issuing a CA to channel 2 rather than channel I.

The code declares one CB (channel control block)
for each 8089. The CBs are declared as twoelement arrays, each element defining the structure of one channel's portion of the CB. The SCB
(system configuration block)· and SCP (system
configuration pointer) are also declared as structures. The SCP is located at its dedicated system
space address of FFFF6H. The other structures
are not located at specific addresses since they are
all linked together by a chain of pointers
"anchored" at the SCP.

After both lOPs are ready, the code dispatches
two channel programs (not coded in the example);
one program is dispatched to each channel of one
of the lOPs. To avoid external references, the
system has been set up so that the PL/M-86 code
"knows" the starting addresses of these channel
programs (200H and 600H). The code uses the
PLlM-86 LOCKSET function to:

Two simple parameter blocks define messages to
be transmitted between the PL/M-86 program
and the CRT. Each PB contains a pointer to the
beginning of the message area and the length of
the message. In the case of the keyboard (input)
message, the channel program builds the message
in the buffer pointed to by the pointer in the PB
and returns the length of the message in the PB.

•
•
•
•

The code initializes one lOP at a time since the
chain of control blocks read by the lOP during
initialization must remain static until the process
is complete. To initialize the first lOP, the code
fills in the SYSBUS and SOC fields and links the
blocks to each other using the PL/M-86 @
(address) operator.. It sets channel I's BUSY flag
to FFH so that it can monitor the flag to determine when the initialization has been completed
(the lOP clears the flag to OH when it has
finished). Channel 2's BUSY flag is cleared,
although this could just as well have been done
after the initialization. (the lOP does not alter
channel 2's BUSY flag 'eluring initialization). The
code starts the lOP by issuing a channel attention
to channel I to indicate that the lOP is a bus
master. PL/M-86's OUT function is used to select
the port address to which the lOP's CA and SEL
lines have been mapped. The data placed em the
bus (OH) is ignored by the lOP. It then waits until
the lOP clears the channell BUSY flag.

lock the system bus;
read the BUSY flag;
set the BUSY flag to FFH if it is clear;
unlock the system bus.

This operation continues until the BUSY flag is
found to be clear (indicating thatthe channel is
available). Setting the flag immediately to FFH
prevents another processor (or another task in
this program activated as a result of an interrupt)
from using the channel. The code fills in the
parameter block with the address and length of
the message to be displayed, sets the CCW and
then links the channel program (task block) start
address to the parameter block and links the
parameter block to the CB. The channel is dispatched with the OUT function that effects a
channel attention for channel I.
A similar procedure is followed to start channel 2
scanning the terminal keyboard. In this case, the
code allows channel 2 to generate an interrupt
request (which it might do to signal that a message
has been assembled). An interrupt procedure
would then handle the interrupt request.

The second lOP is initialized in the same manner,
first changing the pointer in the SCB to point to
the second lOP's channel control block. If this

I*ASSIGN NAMES TO CONSTANTS* I
DECLARE
CHANNEL$BUSY
LlTERALLY'OFFH';
LlTERALLY'OH';
DECLARE
CHANNEL$CLEAR
CR /*CARR. RET.*/
LITERALLY 'ODH';
DECLARE
LF /*LlNE FEED* /
LlTERALLY'OAH';
DECLARE
DISPLAY$TB
LlTERALLY'200H';
DECLARE
LlTERALLY'600H';
DECLARE
KEYBD$TB
Figure 3-66. Initialization and Dispatch Example

3-82

8089 INPUTIOUTPUT PROCESSOR

DECLARE I*IOP CHANNEL ATTENTION ADDRESSES* I
IOP$A$CH1
LITERALLY
'OFFEOH',
IOP$A$CH2
LITERALLY
'OFFE1 H',
IOP$B$CH1
LITERALLY
'OFFE2H',
IOP$B$CH2
LITERALLY
'OFFE3H';
DECLARE

I*CHANNEL CONTROL BLOCK FOR 10P$A)
CB$A(2)
STRUCTURE
(BUSY
BYTE,
CCW
BYTE,
PB$PTR
POINTER,
RESERVED
WORD);

DECLARE

I*CHANNEL CONTROL BLOCK FOR 10P$B* I
CB$B(2)
STRUCTURE
(BUSY
BYTE,
CCW
BYTE,
PB$PTR
POINTER,
RESERVED
WORD);

DECLARE

I*SYSTEM CONFIGURATION BLOCK* I
SCB
STRUCTURE
(SOC
BYTE,
RESERVED
BYTE,
CB$PTR
POINTER);

DECLARE

I*SYSTEM CONFIGURATION POINTER* I
SCP
STRUCTURE
BYTE, '
(SYSBUS
SCB$PTR
POINTER) AT (OFFFF~H);

DECLARE

MESSAGE$PB STRUCTURE
(TB$PTR
POINTER,
MSG$PTR
POINTER,
MSG$LENGTH WORD);

DECLARE

KEYBD$PB STRUCTUE
(TP$PTR
POINTER,
BUFF_PTR
POINTER,
WORD);
MSG$SIZE

. DECLARE
DECLARE

SIGN$ON BYTE (*) DATA
(CR, LF, 'PLEASE ENTER USER ID');
KEYBD$BUFF BYTE (256);

1*
*INITIALIZE 10P$A, THEN 10P$B
*1
I*PREPARE CONTROL BLOCKS FOR 10P$A* I
SCP .SCB$PTR = @ SCB;
SCP.SYSBUS = 01H· 1*16-BIT SYSTEM BUS* I
SCB.SOC = 02H; I*RQ/GT MODE1, 8-BIT 1/0 BUS* I
SCB.CB$PTR = @ CBSA(O);
CB$A(O).BUSY = CHANNEL$BUSY
CB$A(1 ).BUSY = CHANNEL$CLEAR;

Figure 3-66. Initialization and Dispatch Example (Cont'd.)

3-83

80891NPUT/OUTPUT PROCESSOR

I*ISSUE CA FOR CHANNEL1, INDICATING lOP IS MASTER* 1
OUT (lOP$A$CH1) = OH;
I*WAIT UNTIL FINISHED* 1
DO WHILE CB$A(O).BUSY = CHANNEL$BUSY;
END;
I*PREPARE CONTROL BLOCKS FOR 10P$B* 1
SCB.CB$PTR = @CBSB(O);
CB$B(O).BUSY = CHANNEL$BUSY;
CB$B(1).BUSY = CHANNEL$CLEAR;
I*ISSUE CA FOR CHANNEL2, INDICATING SLAVE STATUS* 1
OUT (lOP$B$CH2) = OH;
I*WAIT UNTIL lOP IS READY* 1
DO WHILE CB$B(O).BUSY = CHANNEL$BUSY;
END;

1*
*SEND SIGN ON MESSAGE TO CRT CONTROLLED
*BY CHANNEL 1 OF 10P$A

*1

.

I*WAIT UNTIL CHANNEL IS CLEAR, THEN SET TO BUSY* 1
DO WHILE LOCKSET (@CB$A(O).BUSY, CHANNEL$BUSY);
END;
I*SET CCW AS FOLLOWS:
*
PRIORITY = 1,
*
NO BUS LOAD LIMIT,
*
DISABLE INTERRUPTS,
*
START CHANNEL PROGRAM IN 1I0SPACE*1
CB$A(O).CCW = 10011001 B;
1*L1NK MESSAGE PARAMETER BLOCK TO CB* 1
CB$A(O).PB$PTR = @ MESSAGE$PB;
I*FILL IN PARAMETER BLOCK* 1
MESSAGE$PB.TB$PTR = DISPLAY$TB;
MESSAGE$PB.MSG$PTR = @SIGN$ON;
MESSAGE$PB. MSB$LENGTH = LENGTH (SIGN$ON);
J*DISPATCH THE CHANNEL * 1
OUT (IOP$A$CH1) = OH;

1*
*DISPATCH CHANNEL 2 OF 10P$A TO
*CONTINUOUSLY SCAN KEYBOARD, INTERRUPTING
*WHEN A COMPLETE MESSAGE IS READY

*1

I*WAIT UNTIL CHANNEL IS CLEAR, THEN SET TO BUSY* 1
DO WHILE LOCKSET (@ CB$A(1).BUSY, CHANNEL$BUSY);
END;

Figure 3-66. Initialization and Dispatch Example (Cont'd.)
3-84

8089 INPUT /OUTPUT PROCESSOR

I*SET CCW AS FOLLOWS:
*
PRIORITY = 0
*
BUS LOAD LIMIT,
*
ENABLE INTERRUPTS,
*
START CHANNEL PROGRAM IN 1/0 SPACE* I
CB$A(1).CCW = 00110001 B;
I*LlNK KEYBOARD PARAMETER BLOCK TO CB* I
CB$A(1).PB$PTR = @ KEYBD$PB;
I*FILL IN PARAMETER BLOCK* I
KEYBD$PB.TB$PTR = KEYBD$TB;
KEYBD$PB.BUFF$PTR = @ KEYBD$BUFF;
KEYBD$PB.MSG$SIZE = OH;
I*DISPATCH THE CHANNEL* I
OUT (IOP$A$CH2) = OH;

Figure 3-66. Initialization and Dispatch Example (Cont'd~)

Memory-to-Memory Transfer

The channel responds to this command by saving
the task pointer and PSW in the first two words
of the parameter block. The suspended program
can be restarted by issuing a "resume" command
that loads TP and the PSW from the save area.

Figure 3-67 shows a channel program that performs a memory-to-lJ1emory block transfer in
seven instructions. The program moves up to 64k
bytes between any two locations in the system
space. A 16-bit system bus is assumed, and the
CPU is assumed to be monitoring the channel's
BUSY flag to determine when the program has
finished.

If the CPU wants to execute another channel program between the suspend and resume operations, the suspended program's registers will
usually have to be saved first. If the "interrupting" program "knows" that the registers must be
saved, it can perform the operation and also
restore the registers before it halts.

To attain maximum transfer speed, the program
locks the bus during each transfer cycle. This
ensures that another processor does not acquire
the bus in the interval between the DMA fetch
and store operations. By setting this channel's
priority bit in the CCW to 1 and the other channel's to 0, the CPU could effectively prevent the
other channel from running during the transfer.
Byte count termination is selected so that the
transfer will stop when the number of bytes
specified by the CPU has been moved. Since there
is only a single termination condition, a termination offset of 0 is specified. The transfer begins
after the WID instruction, and the HLT instruction is executed immediately upon termination.

A more general solution is shown in figure 3-68.
This is a program that does nothing but save the
contents of the channel registers. The registers are
saved in the parameter block because PP is the
only register that is known to point to an available
area of memory. A similar program could be written.to restore registers from the same parameter
block.
Using this approach, the CPU would "interrupt"
a running program as follows:
•
suspend the running program,
• run the register save program,
• run the "interrupting" program,
• run the register restore program,
•
resume the suspended program.

Saving and Restoring Registers

A CPU program can "interrupt" a channel program by issuing a "suspend" channel command.

3-85

8089 INPUTIOUTPUT PROCESSOR

MEMEXAMP
SEGMENT
;**MEMORY-TO-MEMORY TRANSFER PROGRAM**
PB
STRUC
TP_RESERVED:
OS
4
FROM_ADDR:
OS
4
TO_ADDR:
OS
4
SIZE:
OS
2
PB:
ENDS
;POINT GA AT SOURCE, GB AT DESTINATION.
LPD
GA, [PPl.FROM_ADDR
LPD
GB, [PP .TO_ADDR
;LOAD BYTE COUNT INTO BC.
MOV
BC, [PP].SIZE
;LOAD CC SPECIFYING:
;
MEMORYTO MEMORY,
;
NO TRANSLATE,
UNSYNCHRONIZED,
;
;
GA POINTS TO SOURCE,
;
LOCK BUS DURING TRANSFER,
;
NO CHAJNING,
;
TERMINATING ON BYTE COUNT,OFFSET = O.
MOV
.
CC,OC208H
;PREPARE CHANNEL FOR TRANSFER.
XFER
;SET LOGICAL BUS WIDTH.
WID

16,16

;STOP EXECUTION AFTER DMA.
HLT
MEMEXAMP
ENDS
END

Figure 3-67. Memory-to-Memory Transfer Example
SAVEREGS
SEGMENT
;SAVE ANOTHER CHANNEL'S REGISTERS IN PB
PB
STRUC
TP _RESERVED:
OS
4
GA_SAVE:
OS
3
GB_SAVE:
OS
3
GC_SAVE:
OS
3
IX_SAVE:
OS
2
BC_SAVE:
OS
2
MC~SAVE:
OS
2
CC_SAVE:
OS
2
PB
ENDS

SAVEREGS

MOVP
MOVP
MOVP
MOV
MOV
MOV
MOV
HLT
ENDS
END

PP
PP
PP
PP
PP
PP
PP

.GA_SAVE, GA
.GB_SAVE, GB
.GC_SAVE, GC
.IX_SAVE, IX
.BC_SAVE, BC
.MC_SAVE, MC
.CC_SAVE, CC

Figure 3-68. Register Save Example
Mnemonics © Intel, 1979

3-86

Chapter 4
Hardware Reference
Information

CHAPTER 4
HARDWARE REFERENCE INFORMATION
4.1 Introduction

Unit or "BIU." The EU for each processor is
identical. The BIU for the 8086 incorporates a 16bit data bus and a 6-byte instruction queue
whereas the 8088 incorporates an 8-bit data bus
and a 4-byte instruction queue.

This chapter presents specific hardware information regarding the operation and functions of the
8086 family processors: the 8086 and 8088 Central
Processing Units (CPUs) and the 8089 110 Processor (lOP). Abbreviated descriptions of the
8086 family support circuits and their circuit
functions appear where appropriate within the
processor descriptions. For more specific
information on any of the 8086 family support
circuits, refer to the corresponding data sheets in
Appendix B.

The EU is responsible for the execution of all
instructions, for providing data and addresses to
the BIU, and for manipulating the general
registers and the flag register. Except for a few
control pins, the EU is completely isolated from
the "outside world." The BIU is responsible for
executing all external bus cycles and consists of
the segment and communications registers, the
instruction pointer and the instruction object
code queue. The BIU combines segment and offset values in its dedicated adder to derive 20-bit
addresses, transfers data to and from the EU on
the ALU data bus and loads or "prefetches"
ipstructions into the queue from which they are
fetched by the EU .

4.2 8086 and 8088 CPUs
The 8086 and 8088 CPUs are characterized by a
20-bit (1 megabyte) address bus and an identical
instruction/function format, and differ essentially from one another by their respective data bus
widths (the 8086 uses a 16-bit data bus, and the
8088 uses an 8-bit data bus). Except where
expressly noted, ,the ensuing descriptions are
applicable to both CPUs.

The EU, when it is ready to execute an instruction, fetches the instruction object code byte from
the BIU's instruction queue and then executes the
instruction. If the queue is empty when the EU is
ready to fetch an instruction byte, the EU waits
for the instruction byte to be fetched. In the
course of instruction execution, if a memory location or 110 port must be accessed, the EU
requests the BIU to perform the required bus
cycle.

Both the 8086 and 8088 feature a combined or
"time-multiplexed" address and data ,bus that
permits a number of the pins to serve dual functions and consequently allows the complete CPU
to be incorporated into a single, 40-pin package.
As explained later in this chapter, a number of the
CPU's control pins are defined according to the
strapping of a single input pin (the MN/MX pin).
In the "minimum mode," the CPU is configured
for small, single-processor systems, and the CPU
itself provides all control signals. In the "maximum mode," an Intel® 8288 Bus Controller,
rather than the CPU, provides the control signal
outputs and allows a number of the pins previously delegated to these control functions to be
redefined in order to support multiprocessing
applications. Figures 4-1 and 4-2 describe the pin
assignments and signal definitions for the 8086
and 8088, respectively.

The two processing sections of the CPU operate
independently. In the 8086 CPU, when two or
more bytes of the 6-byte instruction queue are
empty and the EU does not require the BIU to'
perform a bus cycle, the BIU executes instruction
fetch cycles to refill. the queue. In the 8088 CPU,
when one byte of the 4-byte instruction queue is
empty, the BIU executes an instruction fetch
cycle; Note that the 8086 CPU, since it has a 16bit data bus,' can access two instruction object
code bytes in a single bus cycle, while the 8088
CPU, since it has an 8~bit data bus, accesses one
instruction object code byte per bus cycle. If the
EU issues a request for bus access while the BIU is
in the process of an instruction fetch bus cycle,
the BIU completes the cycle before honoring the
EU's request.

CPU Architecture
As shown in figures 4-3 and 4-4, both CPUs
incorporate two separate processing units: the
Execution Unit or "EU" and the Bus Interface
4-1

HARDWARE REFERENCE INFORMATION

Common Signals
Name

Function

Type

AD15-ADO

Address/Data Bus

A19/S6A16/S3

Address/Status

Bidirectional,
3·State
Output,
3·State
Output,
3·State

BlJ~

MN/MX

High Enable/
Status
Minimum/Maximum
Mode Control

RD

Read Control

BHE/S7

TEST
READY
RESET
NMI
INTR
ClK
Vee
GND

Wait ()n Test Control
State Control
System Reset
Non·Maskable
Interrupt Request'
InterrJpt Req'uast
System Clock
't 5V
Gro\md

wait

Input
Output,
3·State
Input
Input
Input

AD12

A17/S4

Input

ADll

Ala/S5

Input
Input
Input

AD10

A19/S6

HOLD
HLDA

Function

WR

Write Control

MilO

MemoryllO Control

DT/R

Data Transmit/
Rec.eive

DEN

Data Enable

ALE

Address Latch
Enable
Interrupt Acknowledge

INTA

AD15

AD13

A16/S3

AD9

BHE/S7

ADa

MN/MX

iiii

8086

AD6

Type

Hold Requast
Hold Acknowledge

vcc

AD7

Minimum Mode, Signals (M N/MX = Vcd
Name

GND
AD14

Input
'Output
Output,
3;State
Output,
3·State
Output,
3·State
Output, '
3·State
Output

CPU

HOLD

(iiQ / GTo)
(RO/iffi)

ADS

HLDA

AD4

\iii

AD3

M/iO

(52)

AD2

DTIR

(51)

'(LOCK)

AD1

DEN

(SO)

ADO

ALE

(OSO)

NMI

iNi'A

(OSl)

INTR'

'fffi '

eLK

READY

GND

RESET

Output

Maximum Mode Signals (MN/MX =GND)
Name

Function

TYPe

RQ/G'i'T,O

Bidirectional

IO'CR

Request/Grant Bus
Access Control
Bus Priority Lock
Control

52-SO

Bus Cycle Status

Output,
3·State
' Output,
3·State ,

QS1, QSO

Instruction Queue
Status

Output

MAXIMUM MODE PIN FUNCTIONS (e.g.,UiCK)
ARE SHOWN IN PARENTHESES

Figure 4-1. 8086 Pili Definitions
4-2

HARDWARE REFERENCE INFORMATION

Common Signals
Name

Function

Type

AD7-ADO

Address/Data Bus

A15-A8

Add'ress Bus

A19/S6A16/S3

Address/Status

Bidirectional,
3-State
Output,
3-State
Output,
3-State

MN/MX

Minimum/Maximum
Mode Control

Input

RD

Read Control

TEST
READY
RESET

Wait On Test Control
Wait State Control
System Reset
Non-Maskable
Interrupt Request
Interrupt Request
System Clock
+5V
Ground

Output,
3-State
Input
Input
Input

NMI
INTR
ClK
Vee
GND

Input
Input
Input
Input

GND

vcc

A14

A15

A13

A16/S3

A12

AU/S4

A11

A18/S5
A19/S6

A10

SSO

A9

MN/MX

A8

iiii

AD7

Minimum Mode Signals (MN/MX = VCC)
Name

Function

Type

HOLD
HlDA

Hold Request
Hold Acknowledge

WR

Write Control

Input
Output
Output,
3-State
Output,
3-State
Output,
3-State
Output,
3-State

10/M

10/Memory Control

DT/A

Data Transmit/
Receive

DEN

Data Enable

ALE
INTA

Address latch
Enable
Interrupt Acknowledge

SSO

SO Status

8088

AD6

Output

(HIGH)

CPU

HOLD

(RQ/GTO)

AD5

HLDA

(RQ/GT1)

AD4

WR

(LOCK)

AD3

IO/M

(52)

AD2

DT/R

(51)

AD1

DEN

(SO)

ADO

ALE

(OSO)

NMI

INTA

(OS1)

INTR

TEST

CLK

READY
RESET

Output
Output,
3-State

Maximum Mode Signals (MN/MX = GND)
Name

Function

Type

RQ/GT1,0

Bidirectional

lOCK

Request/Grant Bus
Access Control
Bus Priority lock
Control

S2-S0

Bus Cycle Status

Output,
3-State
Output,
3-State

QS1, QSO

Instruction Queue
Status

Output

MAXIMUM MODE PIN FUNCTIONS (e.g., LOCK)
ARE SHOWN IN PARENTHESES

Figure 4-2. 8088 Pin Definitions
4-3

HARDWARE REFERENCE INFORMATION

AH

AL

BH

BL
CL

GENERAL
REGISTERS

DH

DL

DATA BUS

SP

(16 BITS)
BP
DI
CS

"

DS

ES

INTERNAL
COMMUNICATIONS
AlU DATA BUS

REGISTERS

BUS
CONTROL

lOGIC

(1681TSI

eo"
BUS

BUS INTERFACE UNIT
(B1U)

EXECUTION UNIT
(EU)

Figure 4-3. 8086 Elementary Block Diagram

AH

AL

BH

BL

CH

GENERAL
REGISTERS

DH

DL

DATA BUS

SP

(8 BITS)

8P
DI
CS
SI
DS

ES
IP

ALU DATA BUS

INTERNAL
COMMUNICATIONS
REGISTERS

BOB8

BUS

(16 BITS)

eXECUTION UNIT

(EU)

BUS INTERFACE UNIT

(BIU)

Figure 4-4. 8088 Elementary Block Diagram
4-4

HARDWARE REFERENCE INFORMATION

and T 4' and the multiplexed address/data bus is
floated in state T 2 to allow the CPU to change
from the write mode (output address) to the read
mode (input data).

Bus Operation
To explain the operation of the time-multiplexed
bus, the BIU's bus cycle must be examined.
Essentially, a bus cycle is an asynchronous event
in which the address of an I/O peripheral or
memory location is presented, followed by either
a read control signal (to capture or "read" the
data from the addressed device) or a write control
signal and the associated data (to transmit or
"write" the data to the addressed device). The
selected device (memory or I/O peripheral)
accepts the data on the bus during a write cycle or
places the requested data on the bus during a read
cycle. On termination of the cycle, the device
latches the data written or removes the data read.

It is important to note that the BIU executes a bus
cycle only when a bus cycle is requested by the EU
as part of instruction execution or when it must
fill the instruction queue. Consequently, clock
periods in which there is no BIU activity can
occur between bus cycles. These inactive clock
periods are referred to as idle states (TI)' While
idle clock states result from several conditions
(e.g., bus access granted to a coprocessor), as an
example, consider the case of the execution of a
"long" instruction. In the following example, an
8-bit register multiply (MUL) instruction (which
requires between 70 and 77 clock cycles) is executed by the 8086. Assuming that the multiplication routine is entered as a result of a program
jump (which causes the instruction queue to be
reinitialized when the jump is executed) and, as
will be explained later in this chapter, that the
object code bytes are aligned on even-byte boundaries, the BIU's bus cycle sequence would appear
as shown in figure 4-6.

As shown in figure 4-5, all bus cycles consist of a
minimum of four clock cycles or "T -states" identified as Tl, T2' T3 and T4' The CPU places the
address of the memory location or I/O device on
the bus during state T l' During a write bus cycle,
the CPU places the data on the bus from state T 2
until state T 4' During a read bus cycle, the CPU
accepts the data present on the bus in states T 3

- - - - B U S C y C L E - - - - ' - - - - B U S CyCLE------I

Figure 4-5. Typical BIU Bus Cycles

r'\

r.,

r.,

I

.J

2
EU
ACTIVITY

AS A RESULT OF THE JMP
INSTRUCTION, THE EU

4

I

5

7

8

I

9

10

11

EU FETCHES THE FIRST TWO BYTES FROM THE aUEUE (THE MUL INSTRUCTION) AND

COMPLETES INSTRUCTION EXECUTION IN 70 TO 77 CLOCK CYCLES.

REINITIALIZES THE QUEUE
DURING EXECUTION OF
THE JUMP.

BIU
ACTIVITY

SINCE THE QUEUE IS
EMPTY, THE 81U FETCHES

BIU FETCHES TWO OBJECT
CODE BYTES. QUS:UE

TWO OBJECT CODE BYTES AGAIN CONTAINS FOUR
(THE MUL INSTRUCTION) IN BYTES.

ONE BUS CYCLE AND

COMPLETES A SECOND

I

BIU FETCHES TWO MORE
OBJECT CODE BYTES.
QUEUE IS NOW FULL (SIX
BYTES).

81U IS IDLE FOR 62-69 CLOCK CYCLES
WHILE THE EU COMPLETES EXECUTION OF
THE MUL INSTRUCTION.

BUS CYCLE. THE QUEUE
CONTAINS FOUR BYTES.

Figure 4-6. BIU Idle States
4-5

EU FETCHES THE NEXT
OBJECT CODE BYTES
FROM THE QUEUE AND
BEGINS EXECUTING THE
NEXT INSTRUCTION.
BIU FETCHES TWO OBJECT
CODE BYTES TO REFILL
THE QUEUE. THE QUEUE IS
AGAIN FULL

HARDWARE REFERENC'E INFORMATION
(figure 4-8). At this time, bus cycle status is
available on the address/status lines. During state
T3' bus cycle status is maintained on the
address/status lines and either the write data is
maintained or read data is sampled on the lower
16 address/data lines. The bus cycle is terminated
in state T4 (control lines are disabled and the
addressed device deselects from the bus).

In addition to the idle state previously described,
both the 8086 and 8088' CPUs include a
mechanism fQr inserting additional T -states in the
bus cycle to compensate for devices (memory or
I/O) that cannot transfer data at the maximum
rate. These extra T -states are called wait states
(TW) and, when required, are inserted between
states T3 and T4' During a wait state, the data on
the bus, remains unchanged. When the device can
complete the transfer (present or accept the data),
it signals the CPU to exit the wait state and to
enter state T4'

The 8088 CPU, like the 8086, places a 20-bit
address on the multiplexed address/data bus during state T 1 as shown in figures 4-9 and 4-10.
Unlike the 8086, the 8088 maintains the address
on the address lines (A IS-A8) for the entire bus
cycle. During state T2' the CPU removes the
address on the address/data lines (AD7-ADO) and
either floats these lines in preparation for a read
cycle (figure 4-9) or places write data on these
lines (figure 4-10). At this time, bus cycle status is
available on the address/status lines. During state
T3, bus cycle status is maintained on the
address/status lines and either write data is maintained or read data is sampled on the
address/data lines. The bus cycle is terminated in
state T4 (control lines are disabled and the
addressed device deselects from the bus).

As shown in the following timing diagrams, the
actual bus cycle timing differs between a read and
a write bus cycle and varies between the two
CPUs. Note that the timing diagrams illustrated
are for the minimum mode. (Maximum mode
timing is described later in this chapter.)
Referring to figures 4-7 and 4-8, the 8086 CPU
places a 20-bit address on the multiplexed
address/ data bus during state T l' During state
T2' the CPU removes the address from the bus
and either three-states (floats) the lower 16
address/ data lines in preparation for a read cycle
(figure 4-7) or places write data on these lines

I - - - - - - - - - o N E BUSCYCLE---------!
eLK

A1~S:'~~~
AD15-ADo

=:J---<

...J>-

X'-_____

ST_"_JU_S_OU_T_ _ _ _

-----f-----

.....

__~____~----~r
C

~_ _ _ _ _ _LO_W_=_"O_R_EA_D_,H_IG_H=_M_EM_O_RY_R_EA_D_ _ _ _ _ _

----~I

\l-:

___ ___

DJ/R - - - \

~,

:---

----------------~----Ll

-----,1..--------"""\
-1
\-_____ /

11m ___

---J

Figure 4-7. 8086 Read Bus Cycle
4-6

\

\

\_-

HARDWARE REFERENCE INFORMATION

elK

ANOB'REf57

~

~

ADDRESS, BHE OUT

A015-AOO

~

ADDRESS OUT

A19/S6-A1S/S3

ALE

M/iO

/
_----J

X

STATUS OUT

......_ _ _ _ _ _ _ _ _ _ _- - '

X. . _____

DA_TA_O_U_T_ _ _ _- - '

\~------------------'

~'--_ _ _ _ _"_OW_=_'_'O_W_R'_TE_.H_'G_H_=_ME_M_OR_y_W_R'_TE_ _ _ _ _---'

\'----------'
DT/A

----~j---------------------~
___ J

I

DEN - - - - -

"'7/-----""'1\

____ ~

....._ _ _ _ _ _ _ _ _ _ _ _ _- - J

Figure 4-8. 8086 Write Bus Cycle

A majority of system memories and peripherals
require a stable address for the duration of the
bus cycle (certain MCS-85™ components can
operate with a multiplexed address/data bus).
During state T 1 of every bus cycle, the ALE
(Address Latch Enable) control signal is output
(either directly from the microprocessor in the
minimum mode or indirectly through an 8288 Bus
Controller in the maximum mode) to permit the
address to be latched (the address is valid on the
trailing-edge of ALE). This "demultiplexing" of
the address/data bus can be done remotely at
each device in the system or locally at the CPU
and distributed throughout the system as a
separate address bus. For optimum system performance and for compatibility with multiprocessor systems' or with the Intel Multibus
architecture, the locally-demultiplexed address
bus is recommended. To latch the address, Intel ®
8282 (non-inverting) or 8283 (inverting) Octal
Latches are offered as part of the 8086 product
family and are implemented as shown in figure
4-11. These circuits, in addition to providing the
desired latch function, provide increased current
drive capability and capacitive load immunity.

The data bus cannot be demultiplexed due to the
timing differences between read and write cycles
and the various read response times among
peripherals and memories. Consequently, the
multiplexed data bus either can be buffered or
used directly. When memory and I/O peripherals
are connected directly to an unbuffered bus, it is
essential that during a read cycle, a device is
prevented from corrupting the address present on
the bus during state T l' To ensure that the
address is not corrupted, a device's output drivers
should be enabled by an output enable function
(rather than the device's chip select function) controlled by the CPU's read signal. (The MCS-86
family processors guarantee that the read signal
will not be valid until after the address has been
latched by ALE.) Many Intel peripheral,
ROM/EPROM, and RAM circuits provide an
output enable function to allow interface to an
unbuffered multiplexed address/data bus. The
alternative of using a buffered data bus should be
considered since it simplifies the interfacing
requirements and offers both increased drive current capability and capacitive load immunity. The
Intel® 8286 (non-inverting) and 8287 (inverting)
4-7

HARDWARE REFERENCE INFORMATION

1 - - - - - - - - - - ONE
T,

BUSCYClE---------~

T2

T4

ClK

A19/S6-A16/S3

A15-Aa

~,--_A_O_O_RE_S_S_OU.;..T_-IXII..-_ _ _ _ _S_TA_J_US_O_U_T_ _ _ _ _--J}-~

,

AD7-ADO

ALE

101M

}--

ADDRESS OUT

DATA IN

ADDRESS OUT

\~~

____________

~r-

-'C

~,--_ _ _ _ _ _lO_W_=_M_E_M_O_RY_R_E_A_O'_H_'G_H_=_'IO_RE_A_O_ _ _ _ _ _ _
\~

__________J,

---,

OTI~ _ _ _

,---

-'L', _ _ _ _

~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

\

..________. ./r---T\~~=

DEN =~~~-JT/------------'\

Figure 4-9.8088 Read Bus Cycle
I - - - - - - - - - - O N E BUS C Y C l E - - - - - - - - - - -

T2
ClK

A'9ISS-A'SIS3

.~,--_A_D_D_RE_S_S_OU_T_-IX'I..-_ _ _ _ _S_TA_J_US_O_U_T_ _ _ _ _~}--

A'5-AS

~_ _ _ _ _ _ _ _ _AO_O_R_ES_S_O_U_T_ _ _ _ _ _ _ _~}--

ADT-ADO

~_ _A_O_D_RE_S_S_O_UT_-IX,,--_ _ _ _ _DA_J_A_O_UT_ _ _ _ _ _- - , } -

,

ALE

101M

\~

______________

~r-

C

~,--_ _ _ _ _ _l_OW_=_ME_M_O_R_Y_W_RI_TE_,_HI_GH_=_'_IO_W_R_'T_E_ _ _ _ _ _ _ _ _ _

\'-------',
___

,

,

~,-----~------------------~'r--L.;.. __
~

~~

-----r,---------------------.\
J
'-_ _ _ _ _ _----1',---

DEN ____

Figure 4-10.8088 Write Bus Cycle
4-8

HARDWARE REFERENCE INFORMATION

Octal Bus Transceivers, shown in figure 4-12, are
expressly designed to buffer the data bus. These
transceivers use the CPU's DEN (Data Enable)
and DT lif (Data Transmit/Receive) control
signals to enable and control the direction of data
on the bus. These signals provide the proper timing relationship to guarantee isolation of the
address that is present on the multiplexed bus
during state T 1.

r o11
-RES

8284
CLOCK

GENERATOR

Except where noted, all subsequent discussions
and e.'{amples in this chapter assume a locally
demultiplexed address bus and a buffered data
bus. The resultant address and data buses from
the address latches and data transceivers to the
memory and 110 devices will be referred to collectively as the "system" bus.

Vee

--

1

MNIMX

AD

eLK

WR
READY

101M

RESET

8088
epu

ALE

STS
ADDRESS BUS

ADDRESS

A19-A16
ADDRESS

~

ADDRESSIOATA

It.

A15- Aa

1.<1
AD7- ADO

8282
OR
8283

,

I~

~

~.J,.~~

(2 OR 3)

DE

1

!~

~

SEl RDWR

MEMORY

110 PERIPHERAL

DATA

DATA

~

~

Figure 4-11. Minimum Mode 8088 Demultiplexed Address Bus

Vee

~

I

r oI~
8284
RES

CLOCK

GENERATOR

r

Vee

r--

r---

r--

MNIMX

AD

eLK

\VA
READY

M/iO

RESET

8086
epu

SHE

STS

ALE
ADDRESS

A19-A16

I

I>
8282
OR

8283

SHE
A D15-ADO

I~

ADDRESSIOATA

I>

•

5Th 01-

OE

!

~
T

....V"

8286
OR
8287

AdDRESS BUS

j . Jj
MEMORY

110 PERIPHERAL

DATA

DATA

!

DATA BUS

OE

Figure 4-12. Minimum Mode 8086 Buffered Data Bus
4-9

I
!

HARDWARE REFERENCE INFORMATION

The insertion of wait states in the CPU's bus cycle
is accomplished by deactivating one of the 8284's
RDY inputs (RDYI or RDY2). Either of these
inputs, when enabled by its corresponding AENI
or AEN2 input, can be deactivated directly by a
peripheral device when it must extend the CPU's
bus cycle (when it is not ready to present or accept
data) or by a "wait state generator" circuit (a
logic circuit that holds the RDY input inactive for
a given number of clock cycles).

Clock Circuit
To establish the bus cycle time, the CPU requires
an external clock signal. As an integral part of the
8086 family, Intel offers the 8284 Clock
Generator/Driver for this purpose. In addition to
providing the primary (system) clock signal, this
device provides both the hardware reset interface
and the mechanism for the insertion of wait states
in the bus cycle.
The clock generator/driver requires an external
series-resonant crystal input (or external frequency source) at three times the required system clock
frequency (i.e., to operate the CPU at 5 MHz, a
15 MHz fundamental frequency source is
required). The divided-by-three output (CLK)
from the 8284 is routed directly to the CPU's
CLK input. The clock generator/driver provides a
second clock output called PCLK (Peripheral
Clock) at one half the frequency of the CLK output and a buffered TTL level OSC (oscillator)
output at the applied crystal input frequency.
These outputs are available for use by system
devices.

The READY output, which is synchronized to the
CLK signal is coupled directly to the CPU's
READY input. As shown in figure 4-13, when the
addressed device needs to insert one or more wait
states in a bus cycle, it deactivates the 8284's RDY
input prior to the end of state T2 which causes the
READY output to be deactivated at the end of
state T2. The resultant wait state (TW) is inserted
between states T3 and T4. To exit the wait state,
the device activates the 8284's RDY input which
causes the READY input to the CPU to go active
at the end of the current wait state and allows the
CPU to enter state T 4.

The 8284's hardware reset function is accomplished with an internal Schmitt trigger circuit
that is activated by the RES (Reset) input. When
this input is pulled low (i.e., a contact closure to
ground), the RESET output is activated synchronously with the CLK signal. This signal must
be active for four clock cycles and causes the CPU
to fetch and execute the instruction at location
FFFFOH. An external RC circuit is connected to
the RES input to provide the power-on reset function (on power-on, the RES input must be active
for 50 microseconds). The RESET output is
coupled directly to the RESET input of the CPU
as well as being available to system peripherals as
the system reset signal.

Minimum/Maximum Mode
A unique feature of the 8086 and 8088 CPUs is
the ability of a user to define a subset of the
CPU's control signal outputs in order to tailor the
CPU to its intended system environment. This
"system tailoring" is acc0l!!.l2lished by the strapping of the CPU's MN/MX (minimum/maximum) input pin. Table 4-1 defines the 8086 and
8088 pin assignments in both the minimum and
maximum modes.

I - - - - - - - O N E BUS C Y C L E - - - - - - I
T3

elK

'" ,.

....",=""

ROV 'NPUT _ _ _ _ _

READY OUTPUT _ _ _ _ _ _ _....,

\'--__---'1

Figure 4-13. Wait State Timing
4-10

HARDWARE REFERENCE INFORMATION

Table 4-1. Minimum/Maximum Mode Pin Assignments
8088

8086

Mode

Mode
Pin

Pin

31
30
29
28
27
26
25
24

Minimum

Maximum

HOLD
HLDA
WR
MilO

RQ/GTO
RQ/GT1
LOCK
S2

DT/R

51

DEN
ALE
INTA

SO
QSO
QS1

Minimum

Maximum

HOLD
HLDA
WR

RQ/GTO
RQ/GT1
LOCK
S2
S1
SO
QSO
QS1
High State

31
30
29
28
27
26
25
24
34

101M

DT/A"
DEN
ALE
INTA
SSO

8-bit device, compatibility with existing
MCS-85™ systems and specific MCS-85™ family
devices (e.g., the Intel® 8155156).

Minimum Mode

In the minimum mode (MN/MX pin strapped to
+5V), the CPU supports small, single-processor
systems that consist of a few devices and that use
the system bus rather than support the
Multibus™ architecture. In the minimum mode,
the CPU itse!f..-Aenerates all bus control
signals (DT/R, DEN, ALE and either MilO or
101M) and the command output signal (RD, WR
or INT A), and provides a mechanism for
requesting bus access (HOLD/HLDA) that is
compatible with bus master type controllers (e.g.,
the Intel® 8237 and 8257 DMA Controllers).

Maximum Mode

In the maximum mode (MN/MX pin strapped to
ground), an Intel® 8288 Bus Controller is added
to provide a sophisticated bus control function
and compatibility with the Multibus architecture
(combining an Intel® 8289 Arbiter with the 8288
permits the CPU to support multiple processors
on the system bus). As shown in figure 4-15, the
bus controller, rather than the CPU, provides all
bus control and command outputs, and allows the
pins previously delegated to these functions to be
redefined to support multiprocessing functions.

In the minimum mode, when a bus master
requires bus access, it activates the HOLD input
to the CPU (through its request logic). The CPU,
in response to the "hold" request, activates
HLDA as an acknowledgement to the bus master
requesting the bus and simultaneously floats the
system bus and control lines. Since a bus request
is asynchronous, the CPU samples the HOLD
input on the positive transition of each CLK
signal and, as shown in figure 4-14, activates
HLDA at the end of either the current bus cycle
(if a bus cycle is in progress) or idle clock period.
The hold state is maintained until the bus master
inactivates the HOLD input at which time the
CPU regains control of the system bus. Note that
during a "hold" state, the CPU will continue to
execute instructions until a bus cycle is required.

S2, S1 and SO

ReferringJ,oJ'igure 4-15, the 8288 Bus Controller
uses the S2, SI and SO status bit outputs from the
CPU (and the 8089 lOP) to generate all bus control and command output signals required fm a
bus cycle. The status bit outputs are decoded as
outlined in table 4-2. (For a detailed description
of the operation of the 8288 Bus Controller, refer
to the associated data sheet in Appendix B.)
The 8088 CPU, in the minimum mode, provides
an SSO status output. This output is equivalent to
SO in the maximum mode and can be decoded
with DT IN: and 101M (inverted), which are
equivalent to Si and S2 respectively, to provide
the same CPU cycle status information defined in
table 4-2. This type of decoding could be used in a
minimum mode 8088-based system to allow
dynamic RAM refresh during passive CPU cycles.

Note that in the minimum mode, the I/O-memory
control line for the 8088 CPU is the converse of
the corresponding control line for the 8086 CPU
(MilO on the 8086 and 101M on the 8088). This
was done to provide the 8088 CPU, since it is an
4-11

HARDWARE REFERENCE'INFORMATION

I

I

T4 QR TI

Figure 4-14. HOLD/HLDA Timing

VCC

rDl

~I -,.....

8284

-RES

GE~~~~~OR

...

r---

L

n

8288
ClK BUS
CONTROLLER

MN/iilX
ClK

So

So

iNi'A

READY

51

51

MRDC

RESET

52

52

-

MWfC

DEN

r-

iOiiC

DT/R

il5WC

r-- ALE
8088
CPU

C.
ADDRESS

Ii>

A19-A81----...oitl

I I

... ADDRESS/DATA
AD7-ADO"

r

STB
8282
OR

ADDRESS BUS

8283

~

Il~~
~

MEMORY

110 PERIPHERAL

DATA

DATA

t

DATA BUS

t

=,

Figure 4-15. Elementary Maximum Mode System
Table 4-2. Status Bit Decoding
Status Inputs
S2

S1

SO

0
0
0
0
1
1
1
1

0
0
1
1
0

0
1
0

0
1
1

1

0
1
0
1

CPU Cycle

8288 Command

Interrupt Acknowledge
Read 1/0 Port
Write 1/0 Port
Halt
Instruction Fetch
Read Memory
Write Memory
Passive

INTA
10RC
10WC,AIOWC
None
MRDC
MRDC
MWTC,AMWC
None

4-12

HARDWARE REFERENCE INFORMATION

- ----

RQ/GT1, RQ/GTO

"hold" state. Note that the CPU's execution unit
(EU) continues to execute the instructions in the
queue until an instruction requiring bus access is
encountered or until the queue is empty. In the
third (release) phase, the request~ processor
again outputs a pulse on the RQ/GT line. This
pulse alerts the CPU that the processor is ready to
release the bus. The CPU regains bus access on its
next clock cycle. Note that the exchange of pulses
is synchronized and, accordingly, both the CPU
and requesting processor must be referenced to
the same clock signal.

The Request/Grant signal lines (RQ/GTO and
RQ/GTl) provide the CPU's bus access
mechanism in the maximum mode (replacing the
HOLD/HLDA function available in the
minimum mode) and are designed expressly for
multiprocessor applications using the 8089 110
Processor in its local mode or other processors
that can support this function. These lines are
unique in that the request/grant function is
accomplished over a single line (RQ/GTO
or RQ/GTl) rather than the two-line
HOLD/HLDA function.

The request/ grant lines are prioritized with
RQ/QTIj taking precedence over RQ/GTl. If a
request arrives on both lines simultaneously, the
processor o~RQ/GTO is granted the bus (the
request on RQ/GTl is granted when the bus is
released by the first processor following ~ne~
two clock channel transfer delay). Both RQ/GT
lines (and the HOLD line in minimum mode) have
a higher priority than a pending interrupt.

As shown in figure 4-16, the request/grant
sequence is a three-phase cycle: request, grant and
release. The sequence is initiated by another processor on the s~em bus when it outputs a pulse
on one of the RQ/GT lines to request bus access
(request phase). In response, the CPU outputs a
pulse (on the same line) at the end of either the
current bus cycle (if a bus cycle is in progress) or
idle clock period to indicate to the requesting processor that it has floated the system bus and that it
will logically disconnect from the bus controller
on the next clock cycle (grant phase) and enter a

I

T40 R TI

Request/grant latency (the time interval between
the receipt of a request pulse and the return of a
grant pulse) for several conditions is given in table
4-3.

I

JLf\L

CLK

RQ/GT
COPROCESSOR REQUESTS
BUS ACCESS

CPU GRANTS BUS
TO COPROCESSOR

:\D

COPROCESSOR RELEASES
BUS

Figure 4-16. Request/Grant Timing

Table 4-3. Request/Grant Latency
Request/Grant Delay

Operating Condition
Normal Instruction Processing-LOCK inactive
INTA Cycle Executing-LOCK active
Locked XCHG Instruction Processing-LOCK active

8086

8088

3-6 (10*) clocks

3-10 clocks

15 clocks

15clocks

24-31 (39*) clocks

24-39 clocks

*The number of clocks in parentheses applies when the instruction being executed references a word
operand at an odd address boundary.

4-13

HARDWARE REFERENCE INFORMATION

Latency during normal instruction processing
(LOCK inactive) can be as short as three clock
cycles (e.g., during execution of an instruction
that does not reference memory) and no more
than ten clock cycles. Whenever the LOCK output is active (LOCK is activated during an interrupt acknowledge cycle or during execution of an
instruction with a Lock prefix), latency is
increased. In the case of the execution of a locked
XCHG instruction (used during semaphore
examination), maximum latency is limited to 39
clock cycles. Greater latencies occur when a
"long" instruction is locked. This, however, is
neither necessary nor recommended.

sion processing by a coprocessor. (The
corresponding Intel ICE modules use these status
bits during "trace" operations.) The encoding of
the QSl and QSO bits is shown in table 4-4.
Table 4-4. Queue Status Bit Decoding

At the end of processor activity, the 8086 or
8088 will not redirve its control and data buses
until two clock cycles following receipt of the
release pulse (or two clock cycles after HOLD
goes inactive in the minimum mode).

QS1

QSO

Queue Status

o(low)

0

No Operation. During the last
clock cycle, nothing was taken
from the queue.

0

1

First Byte. The byte taken from the
queue was the first byte of the
instruction.

1 (high)

0

Queue Empty. The queue has
been reinitialized as a result of the
execution of a transfer instruction.

1

1

Subsequent Byte. The byte taken
from the queue was a subsequent
byte of the instruction.

A Hold request is honored immediately following
CPU reset if the HOLD line is active when the
RESET line goes inactive. This action facilitates
the downloading of programs and, more
specifically, the setting of memory location
FFFFOH prior to CPU activation. Note that the
same result can be effected in the maximum mode
through the RQ/GT line by generating the request
pulse in the first or second clock cycle after
RESET goes inactive.

The queue status is valid during the clock cycle
after the indicated activity has occurred.

LOCK

External Memory Addressing

The LOCK output is used in conjunction with an
Intel 8289® Bus Arbiter to guarantee exclusive
access of a shared system bus for the duration of
an instruction. This output is software controlled
and is effected by preceding the instruction
requiring exclusive access with a one byte "lock"
prefix (see instruction set description in Chapter

The 8086 and 8088 CPUs have a 20-bit address
bus and are capable of accessing one megabyte of
memory address space.
The 8086 memory address space consists of a
sequence of up to one million individual bytes in
which any two consecutive bytes can be accessed
as a 16-bit data word. As shown in figure 4-17,
the memory address space is physically divided
into two banks of up to 512k bytes each.

2).

When the lock prefix is decoded by the EU, the
EU informs the BIU to activate the LOCK output
during the next clock cycle. This signal remains
active until one clock cycle after the execution of
the associated instruction is concluded.

One bank is associated with the lower half of the
CPU's 16-bit data bus (data bits D7-DO), and the
other bank is associated with the upper half of the
data bus (data bits DI5-D8). Address bits A19
through Al are used to simultaneously address a
specific byte location in both the upper and lower
banks, and the AOaddress bit is not used in
memory addressing. Instead, AO is used in
memory bank selection. The lower bank, which

QS1, QSO

The QSl and QSO (Queue Status) outputs permit
external monitoring of the CPU's internal
instruction queue to allow instruction set exten4-14

HARDWARE REFERENCE INFORMATION

order byte is in the lower bank), the word is said
to be "aligned" and can be accessed in a single
operation (a single bus cycle). As with the byte
transfers previously described, address bits A19
through Al address both banks, except that now
BHE is active (selecting the upper bank) and AO is
inactive (selecting the lower bank) to access both
bytes.

ADDRESS BUS

~

~

m

!

""

,..

""

When the low-order byte of the word to be
accessed is on an odd address boundary (when the
low-order byte is in the upper bank), the word is
"not aligned" and must be accessed in two bus
cycles. During the first cycle, the low-order byte
of the word is transferred to or from the upper
bank as described for a byte access at an odd
address (AO and BHE active). The memory
address is then incremented, which causes AO to
shift to an inactive level (selecting the lower
bank), and a byte access at an even address is performed during the next bus cycle to transfer the
word's high-order byte to or from the lower bank.
The above sequence is initiated automatically by
the 8086 whenever a word access at an odd
address is performed. Also, the directing of the
high- and low-order bytes of the 8086's internal
word registers to the appropriate halves of the
data bus is performed automatically and, except
for the additional four clock cycles required to
execute the second bus cycle, the entire operation
is transparent to the program.

00-07

00-07

~

""

AO-A18

LOWER
(EVEN)
BANK
5l2K x a

UPPER
(ODD)
BANK
5l2K x8

AI

...

SEL

Ao-Ala

UPPER HALF OF DATA BUS

T

.......

07-00 ----"!"LO!!!!W!!!E'!!'R!'!'!HA!'!'!L!"FO!'!F!'!!D"!!AT!'!'!A'!!BU!!!!S-----'!

Figure 4-17.8086 Memory Interface

contains even-address bytes, is selected when
AO=O. The upper bank, containing odd address
bytes (AO=l), is selected by a separate signal, Bus
High Enable (BHE). Table 4-5 defines the
BHE-AO bank selection mechanism.
Table 4-5. Memory Bank Selection

AO

Byte Transferred

o(low)

0

0
1 (high)
1

1

Both bytes
Upper byte to/from odd address
Lower byte to/from even address
None

BHE

0
1

The 8088 memory address space is logically
organized as a linear array of up to one million
bytes. Since the 8088 uses an 8-bit-wide data bus,
memory consists of a single bank. Address bit AO
is used to address memory, and a BHE signal is
not provided.

When accessing a data byte at an even address,
the byte is transferred to or from the lower bank
on the lower half of the data bus (D7-DO). In this
case, the inactive level of the AO address bit
enables the addressed byte in the lower bank, and
the inactive level of the BHE signal disables the
addressed byte in the upper bank. Conversely,
when performing a byte access at an odd address,
the data byte is transferred to or from the upper
bank on the upper half of the data bus (D15-D8).
The active level of the BHE signal enables the
upper bank, and the active level of the AO address
bit disables the lower bank.

Word (16-bit) operands can be located at odd- or
even-address boundaries. The low-order byte of
the word is stored in the lower-valued address
location, and the high-order byte is stored in the
next, higher-valued address location. The 8088
automatically executes two bus cycles when
accessing word operands.

As indicated in table 4-5, the. 8086 can access a
byte in both the upper and lower banks
simultaneously as a 16-bit word. When the loworder byte of the word to be accessed is on an
even address boundary (that is, when the low-

The 8086 and 8088 CPUs support both I/O
mapped I/O and memory mapped I/O. I/O
mapped I/O permits an I/O device to reside in a
separate address space (first 64k of address
space), and the standard I/O instruction set is

I/O Interfacing

4-15

HARDWARE REFERENCE INFORMATION

available for device communications.
mapped 1/0 permits an 110 device
anywhere in memory and allows the
CPU instruction set to be used
operations.

Memory
to reside
complete
for 1/0

When the 1/0 and memory address spaces
overlap, device selection is determined by the
appropriate read/write command set.

Interrupts

The 8086 supports both 8-bit and 16-bit 1/0
devices. An 8-bit 110 device may be associated
with either the upper or ·lower half of the data
bus. (Assigning an equal number of devices to
each half of the data bus distributes bus loading.)
When an 1/0 device is assigned to the lower half
of the bus (D7-DO), aU 110 addresses must be
even (AO equal "0"), and when an 1/0 device is
assigned to the upper half of the bus, all 110
addresses must be odd (AO equal" 1"). Note that
since AO always will be either a "1" or a "0" for
a specific device, it cannot be used as an address
input to select registers within the I/O device.
When an 110 device on the upper. half of the bus
and an 1/0 device on the lower half of the bus are
assigned addresses that differ only by the state,of
AO (adjacent odd and even addresses), AO and
BHE both must be conditions of device selection
to prevent a write operation to one device from
overwriting data in the other device.

CPU interrupts can be software or hardware
initiated. Software interrupts originate directly
from program execution (i.e., execution of a
breakpointed instruction) or indirectly through
program logic (i.e., attempting to divide by zero).
Hardware interrupts originate from external logic
and are classified as either non-maskable or
maskable. All interrupts, whether software or
hardware initiated, result in the transfer of control to a new program location. A 256-entry vec'tor table, which contains address pointers to the
interrupt routines, resides in absolute locations 0
through 3FFH. Each entry in this table consists of
two 16-bit address values ,(four bytes) that are
loaded into the code segment (CS) and the
instruction pointer (IP) registers. as the int~rrupt
routine address when an. interrupt is accepted.
Figure 4-18 illustrates the organization of tbe 256entry vector table.
Memory
Addrass

To permit data transfers to 16-bit I/O devices to
be performed in a single bus cycle, the device is
assigned an even address .. To ensure that the 110
device is selected only for word transfers, AO and
BHE both must be conditions of device selection.

Table
Entry

Vector
Definition

::: t-1---~-:;S-55-----1I} V.~M~~O
I
I

The 8088, since its data bus is eight bits wide, is
designed to support 8-bit 110 devices and places
no restrictions on odd or even addresses.
When the 8086 or the 8088 is operated in the
minimum mode, the CPU's read and write commands (RD and WR) are common for memory
and 110 devices. If the memory and 1/0 address
spaces ..QY,erlap, device selection must be qualified
by MilO (8086) or 101M (8088) to determine if
the device is memory or 110. This restriction does
not apply to systems in which 1/0 and memory
addresses' do not overlap or to systems that use
memory-mapped 1/0 exclusively. In the maximum mode, the CPU generates (through the bus
controller) separate memory readlwrite and 110
readlwrite commands in place of the MilO or
101M signal. In a maximum mode system, an 1/0
device is assigned to an 110 address or to a
memory address (memory mapped 1/0) by connecting either the memory or 110 re~d/write como.
mand lines to the device's command inputs.

82

CS32

80

IP32

7E

CS31

7C

IP31

18

CS5

14

IP5

12

CS4

10

IP4

",

I
I

UHr Available

I

R•••rved

.

OE

CS3

oc

IP3

0/\

CS2

08

IP2

08

CSI

04

IPI

02

CS Value - Vector 0 (CS 0)

~ VIctor 5

I'
Vector 4 - Ovetflow

~ V~or 3 - Breaki>Qlnt

>- Vector 2 -

NMI

t

Vector 1 - Slngle·Stap

Yector 0 - Divide Error

00

.

IP Volue - Yactor 0 (IP 0),

2 Bytas -------.

Figure 4-18. Interrupt Vector Table
4-16

HARDWARE REFERENCE INFORMATION

The CPU provides a single interrupt request input
(INTR) that can be software masked by clearing
the interrupt enable bit in the flags register
through the execution of a CLI instruction. The
INTR input is level triggered and is synchronized
internally to the positive transition of the CLK
signal. In order to be accepted before the next
instruction, INTR must be active during the clock
period preceding the end of the current instruction (and the interrupt enable bit must be set).

As shown in figure 4-18, the first five interrupt
vectors are assoCiated with the software-initiated
interrupts and the hardware non-mask able interrupt (NMI). The next 27 interrupt vectors are
reserved by Intel and should not be used if compatibility with future Intel products is to be maintained. The remaining interrupt vectors (vectors
32 thorugh 255) are available for user interrupt
routines.
The non-mask able interrupt (NMI) occurs as a
result of a positive transition at the CPU's NMI
input pin. This input is asynchronous and, in
order to ensure that it is recognized, is required to
have a minimum duration of two clock cycles.
NMI is typically used with power fail circuitry,
.error correcting memory or bus parity detection
logic to allow fast response to these fault conditions. When NMI is activated, control is transferred to the interrupt service routine pointed to
by vector 2 following execution of the current
instruction. When a non-maskable interrupt is
acknowledged, the current contents of the flags
register are pushed onto the stack (the stack
pointer is decremented by two), the interrupt
enable and trap bits in the flags register are
cleared (disabling maskable and single-step interrupts), and the vector 2 CS and IP address
pointers are loaded into the CS and IP registers as
the interrupt service routine address.

As shown in figure 4-19, when a maskable interrupt is acknowledged, the CPU executes two
interrupt acknowledge bus cycles.
During the first bus cycle, the CPU floats the
address/ data bus and activates the INT A (Interrupt Acknowledge) command output during
states T2 through T4' In the minimum mode, the
CPU will not recognize a hold request from
another bus master until the full interrupt
acknowledge sequence is completed. In the maximum mode, the CPU activates the LOCK output
from state T2 of the first bus cycle until state T2
of the second bus cycle to signal all 8289 Bus
Arbiters in the system that the bus should not be
accessed by any other processor. During the
second bus cycle, the CPU again activates its
INT A command output. In response to the

CLK

n

ALEI'

'LOCK

I

\

\\-_ _----1

\'-_----11
AD7-ADO

r

---------------------~<. VECTOR TYPE )>----

'MAXIMUM MODE ONLY
"SEVERAL (3 TYPICAL) IDLE CLOCK STATES OCCUR BETWEEN THE FIRST AND SECOND
INTERRUPT ACKNOWLEDGE BUS CYCLES IN THE 8086 CPU (DURING THIS INTERVAL THE
BUS IS DRIVEN). INTERRUPT ACKNOWLEDGE BUS CYCLES OCCUR BACK·TO·BACK IN
TH E 8088 CPU.

Figure 4-19, Interrupt Acknowledge Sequence
4-17

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

second INT A, the external interrupt system (e.g.,
an Intel® 8259A Programmable Interrupt Controller) places a byte on the data bus that identifies the source of the interrupt (the vector
number or vector "type"). This byte is read by
the CPU and then multiplied by four with the
resultant value used as a pointer into the interrupt
vector table. Before calling the' corresponding
interrupt routine, the. CPU saves the machine
status by pushing the current contents of the flags
register onto the stack. The CPU then clears the
interrupt enable and trap bits in the flags register
to prevent subsequent .maskable and sing~e-step
interrupts, and establishes the interrupt routine
return linkage by pushing the current CS and IP
register contents onto the stack before loading the
new CS and IP register values from the vector
table.

routine), additional time must be included for the
completion on an instruction being executed when
the interrupt is posted (interrupts are generally
processed' only at instruction boundaries), for
saving the contents of any additional registers
prior to interrupt processing (interrupts
automatically save only CS, IP and Flags) and for
any wait states that may be incurred during interrupt processing.

Machine Instruction Encoding and
.
Decoding .
Writing a MOV instruction in ASM-86 in the
form:
MOV destination,source

I

The four classes of interrupts are prioritized with
software-initiated interrupts having the highest
priority and with maskable and single-step interrupts sharing the lowest priority (see section 2.6).
Since the CPU disables maskable and single-step
interrupts when acknowledging any interrupt, if
recognition of maskable interrupts or single-step
operation is required as part of the interrupt
routine, the routine first must set these bits.

will cause the assembler to generate 1 of 28 possible forms of the MOV machine instruction. A
programmer rarely needs to know the details of
machine instruction formats or encoding. An
exception may occur during debugging when it
may be necessary to monitor instructions fetched
on the bus, read unformatted memory dumps,
etc. This section provides the information
necessary to translate or decode an 8086 or 8088
machine instruction. •

The processing times for the various classes of
interrupts are given in table 4-6. (These times also
are Included with the 8086/8088 instruction times
cited in section 2.7.)

To pack instructions into memory as densely as
possible, the 8086 and 8088 CPUs utilize anefficient coding technique. Machine instructions vary
from one to six bytes in length. One-byte instructions, which generally operate on single registers
or flags, are simple to identify. The keys to
decoding longer instructions are in the first two
bytes. The format of these bytes can varY,but
most instructions follow the format shown in
figure 4-20.

Table 4-6. Interrupt Processing Time
Interrupt Class

Processing Time

External Maskable Interrupt
(lNTR)

61 clocks

Non-Maskable Interrupt (NMI)

50 clocks

INT (with vector)
INT Type 3
INTO

51 clocks
52 clocks
53 clocks

Single Step

50 clocks

The first six bits of a multibyte instruction
generally contain an opcode that identifies the
basic instruction type: ADD, XOR, etc. The
following bit, called the D field, generally
specifies the "direction" of the operation: 1 = the
REG field in the second byte identifies the
destination operand, 0 = the REG field identifies
the source operand. The W field distinguishes
between byte and word operations: 0 = byte, 1 =
word.

Note that the times shown in table 4-6 represent
only the time required to process the interrupt
request after it has been recognized. To determine
interrupt latency (the time interval between the
posting of the interrupt request and the execution
of "useful" instructions within the interrupt
Mnemofljcs © Inlel. 19.78

One of three additional single-bit fields, S, V or
Z, appears in some instruction formats. S is used
in conjunction with W to indicate sign extension
4-18

HARDWARE REFERENCE INFORMATION

the zero flag in conditional repeat and loop
instructions. All single-bit field settings are summarized in table 4-7.

of immediate fields in arithmetic instructions. V
distinguishes between single- and variable-bit
shifts and rotates. Z is used as a compare bit with

r-TTM;;';'"T'"I""T-r~~;';-I""T'"

BYTE 3

BYTE 4

BYTE 5

I

I

..........................-t-H-'-+''--'--t-&.-.L-I LOW DISP/DATA I HIGH DISP/DATA I

I
'--'!"""-""""""""P"'''''-",!-''''-''''I'''''''- - - - - - - - - - - -

~

BYTE 6

- - - - - -,- - - - - - r - - - - -..., - - - - - - 1
LOW DATA

I

~ -

I
I
I

HIGH DATA

- - - - -'- - - - -

I
I
I

_.J

REGISTER OPERAND/REGISTERS TO USE IN EA CALCULATION
REGISTER OPERAND/EXTENSION OF OPCODE
REGISTER MODE/MEMORY MODE WITH DISPLACEMENT LENGTH
WORD/BYTE OPERATION

L -_ _ _ _ _ _
L -_ _ _ _ _ _ _ _ _

DIRECTION IS TO REGISTER/DIRECTION IS FROM REGISTER
OPERATION (INSTRUCTION) CODE

Figure 4-20. TypicalSOS6/S0SS Machine Instruction Format

Table 4-7. Single-Bit Field Encoding
Field

Value

Function

S

0
1

No sign extension
Sign extend 8-bit immediate data to 16 bits if W=1

W

0
1

Instruction operates on byte data
Instruction operates on word data

0

0
1

Instruction source is specified in REG field
Instruction destination is specified in REG field

V

0
1

Shift/rotate count is one
Shift/rotate count is specified in CL register

Z

0
1

Repeatlloop while zero flag is clear
Repeatlloop while zero flag is set

4-19

HARDWARE.REFERENCE INFORMATION

The second byte of the instruction usually identifies the instruction's operands: The MOD
(mode) field indicates whether one of the
operands is in memory or whether both operands
are registers (see. table 4-8). The REG (register)
field identifies a register that is one of the instruction operands (see table 4-9). In a number of
instructions, chiefly the immediate-to-memory
variety, REG is used as an extension of the
opcode to identify the type of operation. The
encoding of the RIM (register Imemory) field (see
table 4-10) depends on how the mode field is set.
If MOD = 11 (register-to-register mode), then
RIM identifies the second register operand. If
MOD selects memory mode, then RIM indicates
how the effective address of the memory operand
is to be calculated. Effective address calculation
is covered in detail in section 2.8.
Bytes 3 through 6 of an instruction are optional
fields that usually contain the displacement value
of a memory operand and I or the actual value of
an immediate constant operand.
Table 4-8. MOD (Mode) Field Encoding
CODE

EXPLANATION

00

Memory Mode, no displacement
follows*

01

Memory Mode, 8-bit
displacement follows

10

Memory Mode, 16-bit
displacement follows

11

Register Mode (no
displacement)

*Except when RIM = 110, then 16-bit
displacement follows

Table 4-9. REG (Register) Field Encoding
REG

W=O

W=1

000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

AX
CX
OX
BX
SP
BP
SI
01

There may be one or two displacement bytes; the
language translators generate one byte whenever
possible. The. MOD field. i.ndicates how many
displacement bytes are present. Following Intel
convention, if the displacement is two bytes, the
most-significant byte is stored second in the
instruction. If the displacement is only a single
byte, the 8086 or 8088 automatically sign-extends
this quantity to 16-bits before using the information in further address calculations. Immediate
values always follow any displacement values that
may be present. The second byte of a two-byte
immediate value is the most significant.
Table 4-12 lists the instruction encodings for all
8086/8088 instructions. This table can be used to
predict the machine encoding of any ASM-86
instruction. Table 4-13 lists the 8086/8088
machine instructions in order by the binary value.
of their first byte. This table can be used to
decode any machine instruction from its binary
representation. Table 4-11 is a key to the
abbreviations used in tables 4-12 and 4-13. Table
4-14 is a more compact instruction decoding
. guide.

Table 4-10. R/M (Register/Memory) Field Encoding
MOD=11

EFFECTIVE ADDRESS CALCULATION

RIM

W=O

W=1

RIM

000
001
010
011
100
101
110
111

AL
CL
OL
BL
AH
CH
OH
BH

AX
CX
OX
BX
SP
BP
SI
01

000
001
010
011
100
101
110
111

MOD=OO
(aX)+(SI)
(BX)+(OI)
(BP)+(SI)
(BP)+(OI)
(SI)
(01)
OiRECT AOORESS
(BX)

MOD=G1
(BX) + (SI) + 08
(BX) + (01) + 08
(BP)+(SI)+08
(BP) + (01) + 08
(SI)+08
(01)+08
(BP)+08
(BX)+08

MOD=1Q
(BX)+(SI)+ 016
(BX)+(01)+016
(BP)+(SI)+016
(BP)+(01)+016
(51)+016
(01)+016
(BP)+016
(BX)+D16

HARDWARE REFERENCE INFORMATION

Table 4-11. Key to Machine Instruction Encoding and Decoding
EXPLANATION

IDENTIFIER

MOD

Mode field; described in this chapter.

REG

Register field; described in this chapter.

R/M

Register/Memory field; described in this chapter.

SR

Segment register code: OO=ES, 01=CS, 10=SS, 11 =DS.

W,S,D,V,Z

Single-bit instruction fields; described in this chapter.

DATA-8

8-bit immediate constant.

DATA-SX

8-bit immediate value that is automatically sign-extended to 16-bits
before use.

DATA-LO

Low-order byte of 16-bit immediate constant.

DATA-HI

High-order byte of 16-bit immediate constant.

(DISP-LO)

Low-order byte of optional 8- or 16-bit unsigned displacement; MOD
indicates if present.

(DISP-HI)

High-order byte of optional 16-bit unsigned displacement; MOD
indicates if present.

IP-LO

Low-order byte of new IP value.

IP-HI

High-order byte of new IP value

CS-LO

Low-order byte of new CS value.

CS-HI

High-order byte of new CS value.

IP-INC8

8-bit signed increment to instruction pointer.

IP-INC-LO

Low-order byte of signed 16-bit instruction pointer increment.

IP-INC-HI

High-order byte of signed 16-bit instruction pointer increment.

ADDR-LO

Low-order byte of direct address (offset) of memory operand; EA not
calculated.

ADDR-HI

High-order byte of direct address (offset) of memory operand; EA not
calculated.
Bits may contain any value.

xxx

First 3 bits of ESC opcode.

YYY

Second 3 bits of ESC opcode.

REG8

8-bit general register operand.

REG16

16-bit general register operand.

MEM8

8-blt memory operand (any addressing mode).

MEM16

16-bit memory operand (any addressing mode).

IMMED8

8-bit immediate operand.

IMMED16

16-bit immediate operand.

SEGREG

Segment register operand.

DEST-STR8

Byte string addressed by 01.

4-21

HARDWARE REFERENCE INFORMATION

Table 4-11. Key to Machine Instruction Encoding and Decoding (Cont'd.)
IDENTIFIER

EXPLANATION

SRC-STRB

Byte string addressed by SI.

OEST-STR16

Word string addressed by 01.

SRC-STR16

Word string addressed by SI.

SHORT-LABEL

Label within ±127 bytes of instruction.

NEAR-PROC

Procedure in current code segment.

FAR-PROC

Procedure in another code segment.

NEAR-LABEL

Label in current code segment but farther than -12B to +127 bytes
from instruction.

FAR-LABEL

Label in another code segment.

SOURCE-TABLE

XLAT translation table addressed by BX.

OPCOOE

ESC opcode operand.

SOURCE

ESC register or memory operand.

Table 4-12.8086 Instruction Encoding
DATA TRANSFER
MOV

= Move:

765432107654321076543210765432107654321076543210

Registerfmemory to/from register

100010dw

mod

Immediate to register/memory

1 1 0 0 0 1 1 w

mod

Immediate to register

1 0 1 1 w reg

Memory to accumulator

Accumulator to memory

rim

(DISP·LO)

(DISP·HI)

0 0 rim

(DISP·LO)

(DISP·HI)

reg

o

data

data if w = 1

1010000w

addr·lo

addr-hi

1010001w

addr-Io

addr-hi

Aegisterlmemory to segment register

1 0 0 0 1 1 1 0

mod 0 SR

rim

(DISP·LO)

(DISP·HI)

Segment register to register/memory

10001100

mod 0 SR

rim

(DISP·LO)

(DISP·HI)

Register/memory

11111111

mod 1 1 a rIm

Register

01010 re 9

Segment register

000reg110

I
I

I
J

PUSH = Push:

I

(DISP·LO)

I

(DISP·HI)

J

(DISp·LO)

I

(DISP·HI)

I

POP = Pop:
Register/memory

1 0 0 0 1 1 1 1

Register

o 1 0 1 1 reg

Segment register

000re9111

Mnemonics

@

Intel, 1978

mod a 0 0 rIm

J

4-22

data

I

dataifw=1

J

HARDWARE REFERENCE INFORMATION

Table 4-12.8086 Instruction Encoding (Cont'd.)
DATA TRANSFER (Cont'd.)

=- ExChlnge:

75S432tO

785432tO

Fixed port

1 1 1 0 0 1 1 w

DATA·S

Variable port

1 1 1 0' 1 1 w

XCHG

78S432tO

78543210

71,432tO

71'43210

Reglsterl memory with register

Register with accumulator

IN == Input from:
Fixed port
Variable port

OUT

= Output tD:

= Translate byte to AL

XLAT

1 1 0 1 0 1 1 1

LEA

= Load EA to register

1 0 0 0 1 1 0 1

mod

reg

rim

(DISP·LO)

(DISP-HI)

LOS

= Load pointer to OS

1 1 0 0 0 1 0 1

mod

reg

rim

(DISP·LO)

(DISP·HI)

LES

= Load pointer to ES

11000100

mod

reg

rim

(DlSP·LD)

(DISP·HI)

reg

LAHF • Load AH with flags
SAHF

= Store AH Into flags

PUSHF

=- Push flags

POPF • Pop flags

1 0 0 1 1 111
1 0 0 1 1 1 1 0

1 0 0 1 1 1 0 0
1 0 0 1 1 1 0 1

ARITHMETIC
ADD. Add:
Regl memory with register to either

OOOOOOdw

mod

rim

(DISP-LO)

(DISP·HI)

Immediate to register/memory

100000sw

mod o 0 0 rim

(DISP·LO)

(DISp·HI)

Immediate to accumulator

0000010w

data

data ifw""

Aoe

=-

I
I

data

T

data If s: w=01

data

I

data If 8: w-01

1

AcId with carry:

Reg/ memory with register to either

000100dw

mod

rog

o1

rim

(DISP·LO)

(DISP·HI)

0 rim

(DISP·LD)

(DlSP·HI)

Immediate to register/memory

100000sw

Immediate to accumulator

0001010w

data

Reglster/memory

1111111 w

mod 0 0 0 rim

Register

01000rog

AAA • ASCII adjust for add

o 0 1 1 0 1 1 1

mod

data It

w-,

I
1

I

INC. Increment:

OM

= Decimal adjust for add

I

(DISP-LD)

I

(DISP·HI)

I

o 0 1 o 0 1 1 1

4-23

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

Table 4-12.8086 Instruction Encoding (Cont'd.)
ARITHMETIC (Conl'd.)

78543210

78543210

001010dw

mod

Immediate from reglsterfmemory

100000sw

Immediate from accumulator

0010110w

SUB

= Subtract:

Reg I memory and register to either

78543210

78543210

IOISP-LO)

IOISP-HI)

mod 1 0 1 rim

IOISP-LO)

IOISP-HI)

data

datalfw=l

reg

rim

78543210

78543210

data

I

data if s: w=Ol

I

data

1

data if s: w=Ol

J

data

I

data if s: w=l

I

sss = Subtract with borrow:
reg

rim

IOISP-LO)

IOISP-HI)

rim

IOISP-LO)

IOISP-HI)

Reg/memory and register to either

0OO110dw

mod

Immediate from register/memory

100000sw

mod

Immediate from accumulator

0001110w

data

mod 0 0 1 rIm

i
I

o

1 1

I
I

data if w=l

DEC Oecremenl:
IOISP-LO)

I

IOISP-HI)

I

IOISP·LO)

I

IOISP-HI)

I

Register/memory

1 1 1 1 1 1 1 w

Register

01001reg

NEG Change sign

1 1 1 1 01 1 w

mod 0 1 1 rIm

Register/memory and register

001110dw

mod

rim

IOISP-LO)

IOISP-HI)

mod 1 11 rim

IOISP-LO)

IOISP-HI)

CMP ;;; Compara:

Immediate with register/memory

100000sw

Immediate with accumulator

o0

AAS ASCII adjust for ;;ubtract

o 0 1 111 11

CAS Decimal adjust for subtract

o 0 1 o 1 1 11

1 1 1 lOw

reg

data

MUL Multiply (unsigned)

1111 01 1 w

mod 1 0 0 rim

IOISP-LO)

IOISP-HI)

IMUL Integer multiply (signed)

1111

w

mod 1 o 1 rim

IOISP-LO)

IOISP-HI)

AAM ASCII adjust for multiply

1 1 0 1 0 1 0 0

00001010

IOISP-LO)

IOISP-HI)

DIV Divide (unsigned)

1 1 1 1 01 1 w

mod 1 1 0 rIm

IOISP-LO)

IOISP-HI)

o1 1

IDIV Integer divide (signed)

1 1 1 1 0 1 1 w

mod 1 11 rim

IOISP-LO)

IOISp·HI)

AAD ASCII adjust for divide

1 1 0 1 o 1 0 1

00001010

IOISP-LO)

IOISP-HI)

caw Convert byte to word

1 0 0 1 1 o 0 0

CWD Convert word to double word

1 0 0 1 1 o 0 1

LOGIC

o

NOT Invert

1 1 1 1 01 1 w

mod 0 1

rIm

IOISP-LO)

IOISP-HI)

SHLJSAl Shift loglcallarithmetic left

11 0100vw

mod 1 o 0 rim

IOISP-LO)

IOISP-HI)

SHR Shift logical right

110100vw

mod 1 o 1 rim

IOISp·LO)

IOISP-HI)

SAR Shift arithmetic right

1 1 0 1

o0

v

w

mod 1 1 1 rim

IOISP-LO)

IOISp·HI)

ROl Rotate left

1 1 0 1

o0

v

w

mod 0 0 0 rim

IOISP·LO)

IOISP-HI)

Mnemonics © Intel, 1978

4-24

HARDWARE REFERENCE INFORMATION

Table 4"12. 8086 Instruction Encoding (Cont'd.)
LOGIC (Conl'd,)

7 6 5 4 3 2 1 0

ROR Rotate ,right

1 1

a1 o0

v w

mod

RCL Rotate through carry flag left

I I

o1 o0

v w

mod 0 1

RCR Rotate through carry right

1 1 0 1

aav

7 6 5 4 3 2 1 0

o

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

(DISP-LOI

(DISP-HII

rIm

(DISP-LOI

(DISP-HII

1 rim

(DISP-LOI

(DISP-HII

reg

rim

(DISP-LOI

IDISP-HII

o

0 rim

(DISP-LOI

(DISP-HII

0 1 rim

o1

w

mod

Reg/memory with register to either

0010QOdw

mod

Immediate to registerl memory

1000000w

mod 1

Immediate 10 accumulator

0010010w

a

7 6 5 4 3 2 1 0

7 6 5·4 3 2 1 0

AND = And:

TEST

I
I

data

I

data jf w=1

I

data

I

data if w=1

data

I

data ifw=1

I

data

I

data ifw=1

I

data if w=1

data

= And function to flags no result:

Register/memory and register

OOQ100dw

Immediate data and register/memory

1 I 1 1 01 1 w

Immediate data and accumulator

I 0 1

o1

mod
mod

0 0 w

rim

IDISP-LO)

0 0 rim

(DISP-LO)

reg

o

I
I

(DISP-HI)
(DISP-HII

I
I

1

data

OR = Or:
Reg! memory and register to either

0OOO10dw

mod

Immediate to register Imemory

1QOOOOOw

mod

Immediate to accumulator

0OOO11Qw

rim

(OISP-LO)

(DISP-HI)

0 1 rim

(DISP-LO)

(DISP-HI)

reg

o

I
I

data if w=1

data

XOR = Exclusive or:

Reg/memory and register to either

o0

1 1

Immediate to register/memory

o0

I 1 0 1 0 w

Immediate to accumulator

o0

1 1 0 1 0 w

a0

d

w

mod

rim

(DISP-LOI

(DISP-HII

data

(DISP-LO)

(DISP-HII

data

data if w=1

reg

I
I

STRING MANIPULATION

a1

REP = Repeat

1 1 1 1 0

MOVS=Move byte/word

1 0 1

o0

1 0 w

CMPS=Compare byte/word

I 0 1

o0

1 1 w

SCA5=Scan byte/word

I 0 .1

oI

11 w

LOOS=Load bytelwd to ALIAX

I 0 1

o1

lOw

STDS=Stor bytelwd from ALIA

I 0 1

a1

0 1 w

z

4-25

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

Table 4-12.8086 Instruction Encoding (Cont'd.)
CONTROL TRANSFER
CALL = Call:

765432107654321076543210765432107654321078543210

o0

Direct within segment

11 1 0 1

Indirect within segment

11 11 1111

Direct intersegment

1 00 11

Indirect intersegment

11111 1 11

o1

0

IP-INC-LO

mod

o

1 0 rim

Ip·lo

0

JMP

o

(DISP-HI)

I

(DISP-HI)

I

(DISP-HI)

I

(DISP-HI)

I

Ip·hi

CS·lo

mod

IP-INC-HI
(DISP-LO)

CS·hi

1 1 rim

(DISP-LO)

= Unconditional Jump:

o0

1

IP-ING-LO

o1 o1

1

IP-INC8

Direct within segment

1 1 1 0 1

Direct within segment-short

111

Ip·INC·HI

Indirect within segment

11 111 111

mod 1 0 0 rim

(DISP-LO)

Di~ect

11 1 0 1 01 0

lp·lo

Ip·hi

CS·lo

CS-hl

111111 1 1

mod 1 0 1 rim

(DISP-LO)

data·lo

data·hi

I

data·hi

I

intersegment

Indirect intersegment

RET = Return trom CALL:
Within segment

11000011

Within seg adding immecl to SP

11

o0

0 0 1 0

Intersegment

11

o0

1

o1

1

o1

Intersegment adding Immediate to SP

11

o0

1

0

data·lo

JE/JZ=Jump on equal/zero

o1

11

o1 o0

IP-INC8

JL/JNGE=Jump on less/not greater or equal

o1

1 111

o0

IP-INC8

JLE/JNG =Jump on less or equal/not greater~

o1

111 1 1 0

IP-INCB

JB/JNAE=Jump on below/not above or equal

o1

1 1 0 0 1 0

IP-INC8

JBE/JNA.=Jump on below or equal/nol above

o1

1 1 0 1 1 0

IP-INC8

JP/JPE=Jump on parity/parity eVen

o1

1 1 10 1 0

IP-INC8

JO=Jump on overflow

o1

1 1 0 0 0 0

IP-INC8

JS=Jump on sign

o1

1 1 1 0 0 0

IP-INC8

JNE/JNZ_Jump on not equallnot zerO

o1

1 1 0 1

o1

IP-INC8

JNL/JGE-Jump on npt less/greater or equal

o1

1 111

o1

IP-INC8

JNLE/JG _Jump on not le88 or equal/greater

o1

111111

IP-INC8

JNB/JAE_Jump on not below/above oreque!

o1

1 1 0 0 1 1

IP-INCB

JNBE/JA=Jump on not below or equal/above

o1

1 1 0 1 1 1

IP~INCB

JNP/JPO-Jump on not par/par odd

o1

1 1 1 0 1 1

IP-INC8

JNO_Jumpon not overflow

o1

1 1 0 0 0 1

IP-INC8

Mnemonics © Intel, 1978

4-26

HARDWARE REFERENCE INFORMATION

Table 4-12.8086 Instruction Encoding (Cont'd.)
CONTROL TRANSFER (Cont'd.)
RET

= Return from CALL:

76543210

76543210

JNS=Jumpon not sign

o1

1 1 1 0 0 1

IP-INC8

LOOP= Loop ex times

1 1 1 0 0 0 1 0

IP-INC8

LOOPZ/LOOPE = Loop while zero/equal

11100001

IP-INC8

LOOPNZ/LOOPNE = Loop while not zero/aqua I

11100000

IP-INC8

JCXZ=Jump on ex zero

11100011

IP-INC8

Type specified

1 1 0 0 1 1 0 1

DATA-8

Type3

1 1

INTO= Interrupt on overflow

1 1 0 0 1 1 1 0

IRET = Interrupt return

1 1 0 0 1 1 1 1

76543210

76543210

76543210

76543210

INT' = Interrupt:

a0

I

1 1 0 0

PROCESSOR CONTROL

a

CLC = Clear carry

1 1 1 1 1 0 0

CMC =Complement carry

1 1 1 1 0 1 0 1

STC = Set carry

1 1 1 1 1 0 0 1

CLD =Clear direction

1 1 1 1 1 1 0 0

5TO=5et direction

1 1 1 1 1 1 0 1

CL1=Clear interrupt

1 1 1 1 1 0 1 0

STI=Set Interrupt

1 1 1 1 1 0 1 1

HLT=Halt

11110100

WAIT=Wait

1 0 0 1 1 0 1 1

ESC = Escape (to extern~1 device)

1 1 0 1 1

lOCK=Bus lock prefix

1 1 1 1 0 0 0 0

SEGMENT=Override prefix

001re9 11 O

x xx

modyyyr/m

I

(DISP-LO)

I

(DISP-HI)

I

Table 4-13. Machine Instruction Decoding Guide
1ST BYTE
HEX
BINARY
00
01
02
03
04
05
06
07

0000
0000
0000
0000
0000
0000
0000
0000

0000
0001
0010
0011
0100
0101
0110
0111

2ND BYTE
MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

RIM
RIM
RIM
RIM

BYTES 3, 4, 5, 6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

4-27

ASM-86 INSTRUCTION FORMAT
ADD
ADD
ADD
ADD
ADD
ADD
PUSH
POP

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
ES
ES

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
20
21
22
23
24
25
26

0000 1000 MOD REG
0000 1001. MOD REG
0000 1010 MOD REG
0000 1011 MOD REG
0000 1100 DATA-8
0000 1101 DATA-LO
0000 1110
0000 1111
0001 0000 MOD REG
0001 0001 MOD REG
0001 0010 MOD REG
0001 0011 MOD REG
0001 0100 DATA-8
0001 0101 DATA-LO
0001 0110
0001 0111
0001 1000 MOD REG
0001 1001 MOD REG
0001 1010 MOD REG
0001 1011 MOD REG
0001 1100 DATA-8
0001 1101 DATA-LO
0001 1110
0001 1111
0010 0000 MOD REG
0010 0001 MOD REG
0010 ·0010 MOD REG
0010 0011 MOD REG
0010 0100 DATA-8
0010 0101 DATA-LO
0010 0110

27
28
29
2A
2B
2C
20
2E

0010
0010
0010
0010
0010
0010
0010
0010

0111
1000
1001
1010
1011
1100
1101
1110

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8··
DATA-LO

2F
30
31
32
33
34
35
36

0010
0011
0011
0011
0011
0011
0011
0011

1111
0000
0001
0010
0011
0100
0101
0110

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

Mnemonics © Inlel, 1978·

RIM
RIM
RIM
RIM

BYTES 3,4,5,6
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

ASM-86 INSTRUCTION FORMAT
OR
OR
OR
OR
OR
OR
PUSH

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
CS

(not used)
RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO), (DISP-H I)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO,(DISP-HI)
DATA-HI

RIM
RIM
RIM
RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

4-28

ADC
ADC
ADC
ADC
ADC
ADC
PUSH
POP
SBB
SBB
SBB
SBB
SBB
SBB
PUSH
POP
AND
AND
AND
AND
AND
AND
ES:
DAA
SUB
SUB
SUB
SUB
SUB
SUB
CS:
DAS
XOR
XOR
XOR
XOR
XOR
XOR
SS:

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
SS
SS
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
OS
OS
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16

(segment override
prefix)
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16

(segment override
prefix)
REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16 '

(segment override
prefix)

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
BINARY

HEX
37
38
39
3A
3B
3C
3D
3E

0011
0011
0011
0011
0011
0011
0011
0011

0110
1000
1001
1010
1011
1100
1101
1110

3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
50
5E
5F
60
61
62
63
64
65
66
67

0011
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0100
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0101
0110
0110
0110
0110
0110
0110
0110
0110

1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
11'10
1111
0000
0001
0010
0011
0100
0101
0110
0111

2ND BYTE

MOD REG
MOD REG
MOD REG
MOD REG
DATA-8
DATA-LO

RIM
RIM
RIM
RIM

BYTES 3,4,5,6

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
DATA-HI

ASM-86 INSTRUCTION FORMAT
AAA
CMP
CMP
CMP
CMP
CMP
CMP
OS:
AAS
INC
INC
INC
INC
INC
INC
INC
INC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
DEC
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
POP
POP
POP
POP
POP
POP
POP
POP
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)

"

4-29

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
AL,IMMED8
AX,IMMED16
(segment override
prefix)
AX
CX
OX
BX
SP
BP
SI
01
AX
CX
OX
BX
SP
BP
SI
01
AX
CX
OX
BX
SP
BP
SI
01
AX
CX
OX
BX
SP
BP
SI
01

Mnemonics © Intel, 1978

HARDWARE REFEREN.CE INFORMATION

Table 4-13.Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

68
69
6A
6B
6C
60
6E
6F
70
71
72

0110
0110
0110
0110
0110
0110
0110
0110
0111
0111
0111

1000
1001
1010
1011
1100
1101
1110
1111
0000 IP-INC8
0001 IP-INC8
0010 IP-INC8

73

0111

0011

IP-INC8

74
75
76
77
78
79
7A
7B
7C
70
7E
7F
80

0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
0111
1000

0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000

IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INC8
IP-INCIf
IP-INC8
IP-INC8
IP-INC8
IP-INC8
MODOOOR/M

80

1000

0000 MOD 001 RIM

80

1000

0000 MOD010 RIM

80

1000

0000 MOD 011 RIM

80

1000

0000

80

1000

0000 MOD 101 RIM

80

1000

0000 MOD 110 RIM

80

1000

0000

MOD 111 RIM

81

1000

0001

MOD 000 RIM

81

1000

0001

MOD 001 RIM

81

1000

0001

MOD010 RIM

81

1000

0001

MOD011 RIM

Mnemonics @; Intel, 1978

MOD 100 RIM

BYTES 3,4,5,6

ASM-86 INSTRUCTION FORMAT

(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)

(DISP-LO),(DISP-HI),
DATA-8
. (DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATAcLO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI

4-30

SHORT-LABEL
SHORT-LABEL
SHORT-LABEL

JO
JNO
JB/JNAEI
JC
JNB/JAEI
JNC
JE/JZ
JNE/JNZ
JBE/JNA
JNBE/JA
JS
JNS
JP/JPE
JNP/JPO
JLlJNGE
JNLlJGE
JLE/JNG
JNLE/JG
ADD

SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
SHORT-LABEL
REG8/MEM8,IMMED8

OR

REG8/MEM8,IMMED8

ADC

REG8/MEM8,IMMED8

SBB

REG8/MEM8,IMMED8

AND

REG8/MEM8,IMMED8

SUB

REG8/MEM8,IMMED8

XOR

REG8/MEM8,IMMED8

CMP

REG8/MEM8,IMMED8

ADD

REG16/MEM16,IMMED16

OR

REG16/MEM16,IMMED16

ADC

REG16/MEM16,IMMED16

SBB

REG16/MEM16,IMMED16

SHORT-LABEL

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

81

1000

0001

MOD100 RIM

81

1000

0001

MOD 101 RIM

81

1000

0001

MOD 110 RIM

81

1000

0001

MOD 111 RIM

82

1000

0010 MOD 000 RIM

82
82

1000
1000

0010
0010

82

1000

0010 MOD 011 RIM

82
82

1000
1000

0010
0010

82
82

1000
1000

0010 MOD 110 RIM
0010 MOD 111 RIM

83

1000

0011

MOD 000 RIM

83
83

1000
1000

0011
0011

MOD 001 RIM
MOD010 RIM

83

1000

0011

MOD011 RIM

83
83

1000
1000

0011
0011

MOD 100 RIM
MOD 101 RIM

83
83

1000
1000

0011
0011

MOD110 RIM
MOD 111 RIM

84
85
86
87
88
89
8A
8B
8C
8C
8D
8E
8E
8F
8F
8F

1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000

0100
0101
0110
0111
1000
1001
1010
1011
1100
1100
1101
1110
1110
1111
1111
1111

MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MOD REG RIM
MODOSRR/M
MOD 1-- RIM
MOD REG RIM
MODOSR RIM
MOD 1-- RIM
MOD 000 RIM
MOD 001 RIM
MOD 010 RIM

MOD 001 RIM
MOD010 RIM

MOD100 RIM
MOD 101 f'l/M

BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO),(DISP-HI),
DATA-8

ASM-86 INSTRUCTION FORMAT
AND

REG16/MEM16,IMMED16

SUB

REG16/MEM16,IMMED16

XOR

REG16/MEM16,IMMED16

CMP

REG16/MEM16,IMMED16

ADD

REG8/MEM8,IMMED8

(not used)
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-8

ADC

REG81 MEM8,IMMED8

SBB

REG8/MEM8,IMMED8

(not used)
REG8/MEM8,IMMED8

(DISP-LO),(DISP-HI),
DATA-8

SUB

(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI),
DATA-SX

CMP

REG8/MEM8,IMMED8

ADD

REG16/MEM16,IMMED8

(not used)

(not used)
(DISP-LO), (DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI),
DATA-SX

ADC

REG16/MEM16,IMMED8

SBB

REG16/MEM16,IMMED8

(not used)
(DISP-LO),(DISP-HI),
DATA-SX

SUB

REG16/MEM16,IMMED8

(DISP-LO),(DISP-HI),
DATA-SX
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

CMP

REG16/MEM16,IMMED8

TEST
TEST
XCHG
XCHG
MOV
MOV
MOV
MOV
MOV

REG8/MEM8,REG8
REG16/MEM16,REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG81 M EM8, REG8
REG16/MEM16/REG16
REG8,REG8/MEM8
REG16,REG16/MEM16
REG16/MEM16,SEGREG

(not used)

(not used)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

LEA
MOV

REG16,MEM16
SEGREG,REG16/MEM16

(not used)
(DISP~LO),(DISP-HI)

POP

REG16/MEM16

(not used)
(not used)

4-31

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

8F
8F
8F
8F
8F
90
91
92
93
94
95
96
97
98
99
9A

1000
1000
1000
1000
1000
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001
1001

9B
9C
90
9E
9F
AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
BO
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB

1001 1011
1001 1100
1001 1101
1001 1110
1001 1111
1010 0000 ADDR-LO
1010 0001 ADDR-LO
1010 0010 ADDR-LO
1010 0011 ADDR-LO
1010 0100
1010 0101
1010 0110
1010 0111
1010 1000 DATA-8
1010 1001 DATA-LO
1010 1010
1010 1011
1010 1100
1010 1101
1010 1110
1010 1111
1011 0000 DATA-8
1011 0001 DATA-8
1011 0010 DATA-8
1011 . 1011 DATA-8
1011 0100 DATA-8
1011 0101 DATA-8
1011 0110 DATA-8
1011 0111 DATA-8
1011 1000 DATA-LO
1011 1001 DATA-LO
1011 1010 DATA-LO
1011 1011 DATA-LO

1111
1111
1111
1111
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010

Mnemonics © Intel, 1978

BYTES 3,4,5,6

MOD 011 RIM
MOD100 RIM
MOD101 RIM
MOD 110 RIM
MOD111 RIM

DISP-LO

DISP-HI,SEG-LO,
SEG-HI

ASM-86 INSTRUCTION FORMAT
(not used)
(not used)
(not used)
(not used)
(not used)
NOP
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
XCHG
CBW
CWO
CALL
WAIT
PUSHF
POPF
SAHF
LAHF
MOV
MOV
MOV
MOV
MOVS
MOVS
CMPS
CMPS
TEST
TEST
STOS
STOS
LODS
LODS
SCAS
SCAS
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV

ADDR-HI
ADDR-HI
ADDR-HI
ADDR-HI

DATA-HI

DATA-HI
DATA-HI
DATA-HI
DATA-HI

4-32

(exchange AX,AX)
AX,CX
AX,DX
AX,BX
AX,SP
AX,BP
AX,SI
AX,DI

FAR_PROC

AL,MEM8
AX,MEM16
MEM8,AL
MEM16,AL
DEST -STR8,SRC-STR8
DEST-STR16,SRC-STR16
DEST -STR8,SRC-STR8
DEST-STR16,SRC-STR16
AL,IMMED8
AX,IMMED16
DEST-STR8
DEST-STR16
SRC-STR8
SRC-STR16
DEST-STR8
DEST-STR16
AL,IMMED8
CL,IMMED8
DL,IMMED8
BL,IMMED8
AH,IMMED8
CH,IMMED8
DH,IMMED8
BH,IMMED8
AX,IMMED16
CX,IMMED16
DX,IMMED16
BX,IMMED16

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

BC
BD
BE
BF
CO
C1
C2
C3
C4
C5
C6

1011 1100
1011 1101
1011 1110
1011 1111
1100 0000
1100 0001
1100 0010
1100 0011
1100 0100
1100 0101
1100 0110

C6
C6
C6
C6
C6
C6
C6
C7

1100
1100
1100
1100
1100
1100
1100
1100

0110
0110
0110
0110
0110
0110
0110
0111

MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD 110 RIM
MOD 111 RIM
MOD 000 RIM

C7
C7
C7
C7
C7
C7
C7
C8
C9
CA
CB
CC
CD
CE
CF
DO
DO
DO
DO
DO
DO
DO
DO
D1
D1
D1
D1
D1

1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1100
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101

0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
0001

MOD 001 RIM
MOD 010 RIM
MOD011 RIM
MOD 100 RIM
MOD101 RIM
MOD110R/M
MOD111 RIM

BYTES 3,4,5,6

DATA-LO
DATA-LO
DATA-LO
DATA-LO

DATA-HI
DATA-HI
DATA-HI
DATA-HI

DATA-LO

DATA-HI

MOD REG RIM
MOD REG RIM
MODOOOR/M

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-H I)
(DISP-LO),(DISP-HI),
DATA-8

DATA-LO

(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI

DATA-HI

DATA-8

MODOOO RIM
MOD001 RIM
MOD010R/M
MOD011 RIM
MOD 100 RIM
MOD 101 RIM
MOD110 RIM
MOD 111 RIM
MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

4-33

A~M-86INSTRUCTION

MOV
MOV
MOV
MOV
(not used)
(not used)
RET
RET
LES
LDS
MOV

FORMAT

SP,IMMED16
BP,IMMED16
SI,IMMED16
DI,IMMED16

IMMED16 (intraseg)
(intrasegment)
REG16,MEM16
REG16,MEM16
MEM8,IMMED8

(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
MOV
MEM16,IMMED16
(not used)
(not used)
(not us~d)
(not used)
(not used)
(not used)
(not used
(not used)
(not used)
RET
RET
INT
INT
INTO
IRET
ROL
ROR
RCL
RCR
SALISHL
SHR
(not used)
SAR
ROL
ROR
RCL
RCR
SALISHL

IMMED16 (intersegment)
(intersegment)
3
IMMED8

REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG8/MEM8,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1
REG16/MEM16,1

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
...

1ST BYTE
HEX
BINARY
01
01
01
02
02
02
02
02
02
02
02
03
03
03
03
03
03
03
03
04
05
06
07
08
OF
EO

1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101
1101

0001
0001
0001
0010
0010
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0011
0011
0100
0101
0110
0111
1000
1XXX
1101 1111
. 1110 0000

2NO BYTE
M00101 RIM
M00110R/M
MOO,111 RIM
MOD 000 RIM
MOD 001 RIM
MOO010R/M
M00011 RIM
M00100 RIM
M00101 RIM
M00110 RIM
M00111 RIM
MOD 000 RIM
MOD 001 RIM
MOD 010 RIM
M00011 RIM
M00100 RIM
MOO 101 RIM
M00110 RIM
M00111 RIM
00001010
00001010

MOD 000 RIM
MOOYYY RIM
M00111 RIM
IP-INC-8

1110

0001

IP-INC-8

E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
FO
F1
F2
F3
F4
F5

1110
.1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111

0010
0011
0100
0101
0110
0111
1000
1001

IP-INC-8
IP-INC-8
OATA-8
OATA-8
DATA-8
OATA-8
IP-ING-LO
IP-INC-LO
IP-LO
IP-INC8

Mnemonics

10~0

© Intel, 1978

(OISP~LO),(OISP-HI)

ASM-86 INSTRUCTION FORMAT
SHR

REG16/MEM16,1

(not used)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)

SAR
ROL
ROR
RCL
RCR
SALISHL
SHR

REG16/MEM16,1
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG8/MEM8,CL
REG81 M EM8,CL

(not used)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)
(OISP-LO),(OISP-HI)

SAR
ROL
ROR
RCL
RCR
SALISHL
SHR

(OISP-LO),(OISP-HI)

SAR
AAM
AAO

REG8/MEM8,CL
REG16/MEM"16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL
REG16/MEM16,CL

(not used)
REG16/MEM16,CL

. (not used)

E1

1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101

BYTES 3,4,5,6

(OISP-LO), (OISP-HI)

IP-INC-HI
IP-INC-HI
IP-HI,CS-LO,CS-HI

XLAT

SOURCE-TABLE

ESC

OPCOOE,SOURCE

LOOPNEI SHORT-LABEL
LOOPNZ
LOOPEI SHORT-LABEL
LOOPZ
SHORT-LABEL
LOOP
SHORT~LABEL
JCXZ
IN
AL,IMME08
IN
AX,IMME08
OUT
AL,IMME08
OUT
AX,IMME08
CALL
NEAR-PROC
JMP
NEAR-LABEL
JMP
FAR-LABEL
JMP
SHORT-LABEL
IN
AL,OX
IN
AX,OX
OUT
AL,OX
AX,OX
OUT
(prefix)
LOCK

(not used)
REPNE/REPNZ
REP/REPE/RERZ
HLT
CMC

4-34

HARDWARE REFERENCE INFORMATION

Table 4-13. Machine Instruction Decoding Guide (Cont'd.)
1ST BYTE
HEX
BINARY

2ND BYTE

F6

1111

0110 MOD 000 RIM

F6
F6
F6
F6
F6
F6
F6
F7

1111
1111
1111
1111
1111
1111
1111
1111

0110
0110
0110
0110
0110
0110
0110
0111

MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100R/M
MOD101 RIM
MOD110 RIM
MOD111 RIM
MOD 000 RIM

F7
F7
F7
F7
F7
F7
F7
F8
F9
FA
FB
FC
FD
FE
FE
FE
FE
FE
FE
FE
FE
FF
FF
FF
FF
FF
FF
FF
FF

1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111
1111

0111
0111
0111
0111
0111
0111
0111
1000
1001
1010
1011
1100
1101
1110
1110
1110
1110
1110
1110
1110
1110
1111
1111
1111
1111
1111
1111
1111
1111

MOD 001 RIM
MOD010R/M
MOD 011 RIM
MOD 100 RIM
MOD101 RIM
MOD110 RIM
MOD111 RIM

MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100 RIM
MOD101 RIM
MOD110R/M
MOD111 RIM
MOD 000 RIM
MOD 001 RIM
MOD010 RIM
MOD011 RIM
MOD100R/M
MOD101 RIM
MOD110R/M
MOD111 RIM

BYTES 3,4,5,6
(DISP-LO),(DISP-HI),
DATA-8
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI),
DATA-LO,DATA-HI
(DISP-LO) ,(DISP-H I)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)
(DISP-LO),(DISP-HI)

4-35

ASM-86 INSTRUCTION FORMAT
TEST

REG8/MEM8,IMMED8

(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
TEST

REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG8/MEM8
REG16/MEM16,IMMED16

(not used)
NOT
NEG
MUL
IMUL
DIV
IDIV
CLC
STC
CLI
STI
CLD
STD
INC
DEC
(not used)
(not used)
(not used)
(not used)
(not used)
(not used)
INC
DEC
CALL
CALL
JMP
JMP
PUSH
(not used)

REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16
REG16/MEM16

REG8/MEM8
REG8/MEM8

MEM16
MEM16
REG16/MEM16 (intra)
MEM16 (intersegment)
REG16/MEM16 (intra)
MEM16 (intersegment)
MEM16

Mnemonics © Intel, 1978

HARDWARE REFERENCE

INFO'RM~TION'

Table 4-14. Machine Instruction Encoding Matrix

Lo

HI
0
1

2
3
4

5

0
ADD
b.t.rlm
AoC
b.f.rlm
AND
b.t.rlm
XOR
b.t.rlm
INC
AX
PUSH
AX

1
ADD
w.t.rlm
AoC
w.t.rlm
AND
w.t.rlm
XOR
w.t.rlm
INC
CX
PUSH
CX

2
ADD
b.t.rlm
AoC
b.t.rlm
AND
b.t.rlm
XOR
b.t.rlm
INC
OX
PUSH
OX

3
ADD
w.t.rlm
AoC
w.t.rlm
AND
w.t.rlm
XOR
w.t.rlm
INC
BX
PUSH
BX

4
ADD
b. ia
AoC
b.i
AND
b.i
XOR
b.i
INC
SP
PUSH
SP

6

7
POP
ES
POP
SS

INC
BP
PUSH
BP

PUSH
ES
PUSH
5S
SEG
"ES
SEG
"SS
INC
SI
PUSH
SI

INC
DI
PUSH
01

JNEI
JNZ
TEST
w.rlm
XCHG
BP

JBEI
JNA
XCHG
b.rlm
XCHG
SI

JNBEI
JA
'·XCHG
w.rlm
XCHG
01

MOVS

CMPS

MOV
i - CH

MOV
i - oH
MOV
b.i.rlm

TEST
b,I,.
MOV
MOV
i - BH i-AX
MOV
w.i.r/m
ESC
XLAT

5
ADD
w.ia

AoC
w,i

AND
w,i

XOR
w,i

oAA
AAA

C

E
PUSH
CS
PUSH
OS
SEG

A
OR
b.t.rlm
SBB
b.t.rlm
SUB
b.t.r!m
CMP
b.t.rlm
DEC
OX
POP
OX

B
OR
w.l.r/m
SBB
w.t.rlm
SUB
w.t.rlm
CMP
w.t.rlm
DEC
BX
POP
BX

OR
b.i
SBB
b.i
SUB
b.i
CMP
b;i
DEC
SP
POP
SP

JPI
JPE
MOV
b.t.rlm
CALL
I.d

JNPI
JPO
MOV
w.t.rlm

JLI
JNGE
MOV
sr,l,rlm

JNLI
JGE
LEA

ar.t,r/m

WAIT

PUSHF

POPF

SAHF

LAHF

TEST
W,I,.

STOS

STOS

LODS

LODS

SCAS'

SCAS

MOV
i - CX

MOV
i - BX
RET
I
ESC

MOV
i - SP
INT
Type 3
ESC

MOV
i - BP
INT
(Any)
ESC

MOV
MOV
i -SI' i - 01

5

6

d

MOV
i-OX
RET.
1.(i+SP)
ESC
2
JMP
I.d

JMP
si.d

IN
v,b

IN
V,W

STC

CLI

STI

CLo

sm

OUT
v,b
Grp2
b,rlm

9

8
OR
b.t.rlm
SBB
b.t.rlm
SUB
b.t.rlm
CMP
b.t.rlm
DEC
AX
POP
AX

OR
w.t.rlm
SBB
w.t.rlm
SUB
w.t.rlm
CMP
w.t.rlm
DEC
CX
POP
CX

JS

JNS

MOV
b.t.rlm

MOV
w.t.rlm

0
OR
w.i

SBB
w,j

SUB
w.i
CMP

w.i

DEC
BP

poi>
BP

~CS

F

..

POP
OS
oAS

SEG

AAS

DEC
SI
POP
SI

DEC
01
POP
01

JLEI
JNG
MOV

JNLEI
JG .

~OS

8

7
8

9
A
B

C
0
E
F

JBI
JO
JNO
JNAE
Immed Immed Immed
b.rlm
w.rlm
b.rlm
XCHG
XCHG
XCHG
AX
CX
OX
MOV
MOV
MOV
m -AL m -AX AL - m
MOV
MOV
MOV
i - AL i _ CL i - oL
RET.
(i+SP)
Shift
Shift
Shift
b
W
b.v
LOOPNZI LOOPZI
LOOP
LOOPNE LOOPE
LOCK

REP

JNBI
JEI
JAE
JZ
Immed
TEST
is,rlm
b.rlm
XCHG
XCHG
BX
SP
MOV
MOVS
AX - m
MOV
MOV
i - BL i -AH
RET

LES

Shift

AAM

AAo

JCXZ

IN
b

IN
W

REP
z

HLT

CMC

~,v

where'
modDr/m
Immed
Shift

Grpl
Grp2

LOS

000
ADD
ROl
TEST
INC

CBW

CMPS

0

OUT
b
Grp t
b.rlm

001
DR
ROR

DEC

010
ADC
RCl
NOT
CAll
id

OUT
W
Grp 1
w.rlm

011
SBB
RCR
NEG
CAll
Ud

CALL
d
CLC

100
AND
SHLISAl
MUl
JMP
id

b = byte operation
d = direct
I = Irom CPU reg
i= immediate
ia = immed. to accum.
id = indirect
is = immed. byte. sign ext.
I = long ie. intersegment

Mnemonics © Intel, 1978

CWO

ESC
t
JMP

101
SUB
SHR
IMUl
JMP
1,ld

110
XdR

DIV
PUSH

3

111
CMP,
SAR
IDIV

-

m = memory
rim = EA is second byte
si = short intrasegment
sr = segment register
t = to CPU reg
v = variable
w = word operation
z = zero

4-36

'4

POP
rim

INTO

IRET

ESC

ESC
7
OUT
V,W
Grp 2
w.rlm

HARDWARE REFERENCE INFORMATION

Keeping these guidelines in mind, the instruction
sequence depicted in figure 4-22 can be described
as follows. Starting the loop arbitrarily in clock
cycle 1 with the queue reinitialization that occurs
as part of the JMP instruction, JMP instruction
execution is completed by the EU, while the BIU
performs an opcode fetch to begin refilling the
queue. (Note that a shorthand notation has been
used in the figure to represent the two queue
status lines and the three status lines-active
periods on any of these lines are noted and the
binary value of the lines is indicated above each
active region.)

8086 Instruction Sequence
Figure 4-22 illustrates the internal operation and
bus activity that occur as an 8086 CPU executes a
sequence of instructions. This figure presents the
signals and timing relationships that are important in understanding 8086 operation. The following discussion is intended to help in the interpretation of the figure.
Figure 4-22 shows the repeated execution of an
instruction loop. This loop is defined in both
machine code and assembly language by figure
4-21. A loop was chosen both to demonstrate the
effects of a program jump on the queue and to
make the instruction sequence easy to follow. The
program sequence shown was selected for several
reasons. First, consisting of seven instructions
and 16 bytes, the sequence is typical of the tight
loops found in many application programs.
Second, this particular sequence contains several
short, fast-executing instructions that
demonstrate both the effect of the queue on CPU
performance and the interaction between the execution unit (EU) fetching code from the queue
and the bus interface unit (BIU) filling the queue
and performing the requested bus cycles. Last,
for the purpose of this discussion, code, stack,
and memory data references were arranged to be
aligned on even word boundaries.
ASSEMBLY LANGUAGE
MOV AX, OF802H
PUSH AX
MOVCX, BX
MOVDX,CX
ADD AX, [SI]
ADD SI, 8M6H
JMP $ -14

In clock cycle 8, the queue status lines indicate
that the first byte of the Mbv immediate instruction has been removed from the queue (one clock
cycle after it was placed there by the BIU fetch)
and that execution of this instruction has begun.
The second byte of this instruction is taken from
the queue in clock cycle 10 and then, in clock
cycle 12, the EU pauses to wait one clock cycle for
the BIU's second opcode fetch to be completed
and for the third byte of the MOV immediate
instruction to be available for execution
(remember the queue status lines indicate queue
activity that 'has occurred in the previous clock
cycle).
Clock cycle 13 begins the execution of the PUSH
AX instruction, and in clock cycle 15, the BIU
begins the fourth opcode fetch. The BIU finishes
the fourth fetch in clock cycle 18 and prepares for
another fetch when it receives a request from the
EU for a memory write (the stack push). Instead
of completing the opcode fetch and forcing the
EU to wait four additional clock cycles, the BIU
immediately aborts the fetch cycle (resulting in
two idle clock cycles (TI) in clock cycles 19 and
20) and performs the required memory write. This
interaction between the EU and BIU results in a
single clock extension to the execution time of the
PUSH AX instruction, the maximum delay 'that
can occur in response to an EU bus cycle request.

MACHINE CODE
B802F8

50
8BCB
8BD1
0304
81C68680
EBFO

Figure 4-21. Instruction Loop Sequence

Figure 4-22 can be more easily interpreted' by
keeping the following guidelines in mind.
•

The queue status lines (QSO, QSl) are the key
indicators of EU activity.

•

Status lines S2 through SO are the main
indicators of 8086/8088 bus activity.

•

Interaction of the BIU and EU is via> the
queue for pre fetched opcodes and via the EU
for requested bus cycles for data operands.

Execution continues in clock cycle 24 with the
execution of back-to-back, register-to-register
MOV instructions'. The first of these instructions
takes full advantage of the pre fetched opcode to
complete this operation in two clock cycles. The
second MOV instruction, however, depletes the
queue and requires two additional clock cycles
(clock cycles 28 and 29).

4-37

Mnemonics © Intel, 1978

HARDWARE REFERENCE INFORMATION

1 "I

1 ' I"

I •

7

1 •

1 •

1 n

1 •

1 •

1 •

1 •

1 •

I

D

1 •

I •

I ~

1 •

1 ·1· 1 •

1 •

1 •

1

co.,
101

Ii 'Iii

I" I
au""

TI

J

T1

~

100

I"I..

L...-CCHlE_FETCH_.....

T,

100

_oo_
..
_m_CH--'r-l

",

FEl'CHII02

T4

111

T,

To

mCH ....

T4

CODEmCH...

I

T,

1"I. .

T,

...

.

FETCHIBC8

rot

I

T1

~ ~ ~ ~~~

I WA~MEMORY

T,

TI

FETCH 'I~

.. I I " I"
T,

"

100

CODE fETCH
"

T.

WfUTEF8020NTO

~
.,

T.

111

r

T,
FEreHa

STAC'

~~~
.,

.8

D1

I FIRS1' II II
L...-_ _ _ _ _ _ _ _ _ _ _ _ _- ' FIRST
BYTE II NEXT
BYTE ,BYTE

Ql1,GIO

·lNITJIucmotIEl10cun0N

no

100

_oo_"_FEI'_"O.....

-!---

_ _ _ _ _ ...
, '1_14 _ _ _ _

- - . J - - - - - - - p u s I t A x - - - - - - - - - t - I.. MOV cx. ax+-

Figure 4-22. Sample Instruction Sequence Execution

In clock cycle 30, the ADD memory indirect to
AX instruction begins. In the time required to
execute this instruction, the BIU completes two
opcode fetch cycles and a memory read and
begins a fourth opcode fetch ,cycle, Note that in
the case of the memory read, the EU's request for
a bus cycle occurs at a point ill the BIU fetch cycle
where it can be incorporated directly (idle states
are not required and no ED delay is imposed).

code sequences, however, use a higher proportion
of more complex, longer-executing instructions
and addressing modes, and therefore tend to be
execution limited. In this case, less BID-ED
interaction is required, the queue more often is
full, and more idle states occur on the bus.
The previous example sequence can be easily
extended to incorporate wait states in the bus
access cycles. In the case of a single wait state,
each bus cycle would be lengthened to five clock
cycles with a wait state (TW) inserted between
every T 3 and T4 state of the bus cycle. As a first
approximation, the instruction sequence exection
time would appear to be lengthened by 10 clock
cycles, one cycle for each useful read or write bus
cycle that occurs. Actually, this approximation
for the number of wait states inserted is incorrect
since the queue can compensate for wait states by
making use of previously idle bus time. For the
example sequence, this compensation reduced the
actual execution time by one wait state, and the
sequence was completed in 64 clock cycles, one
less than the approximated 65 clock cycles.

In clock cycle 44, the ED begins the ADD
immediate instruction, taking four bytes from the
queue and completing instruction execution in
four clock cycles. Also during this time, the BID
senses a full queue in clock cycle 45 and enters a
series of bus idle states (five or six bytes constitute
a full queue in the 8086; the BID waits until it can
fetch a full word of opcodebefore accessing the
bus).
At clock cycle 47, the BID again begins a bus
cycle sequence, one that is destined to, be an
"overfetch" since the, ED is executing a JMP
instruction. As part' of the JMP instruction" the
queue reinitialization (which began the instruction sequence) occurs.

4.3 80891/0 Processor

The entire sequence of instructions has taken 55
clock cycles. Eighteen opcode bytes were fetched,
one word memory read occurred, and one word
stack write was performed.

The Intel® 8089 110 Processor (lOP) combines
the functions of a DMA controller with the processing capabilities of a microprocessor. In addition to the normal DMA function of transferring
data, the 8089 is capable of dynamically
translating arid comparing the data as it is

This example was,by design, partially bus limited
and indicates the types of ED and BID interaction
that can occur in this situation. Most application
Mnemonics © Intel, 1978

4-38

HARDWARE REFERENCE INFORMATION

•

I

•

I

•

I

•

I

•

I

•

I

•

I

•

-

I

•

I

•

I

•

I

•

-

I

•

I

•

I

•

I

•

I

•

-

" "

T4

I

T1

~~~

"

T,

FETCH_III

T4

111

" "

READ DATA"T
AODftE8811Q

T4

I

T1

"

•

I

".

=--rI,--CO_"_"'_CH---,!I~_'''_O_.'_''_RY-,!lL.._CO_OE_fET_C_H-'

FETCH.1Ca

I

•

CODE fETCH

"

FETCH EI FO

T.

I I I I
TI

TI

~

T,

I

•

I

•

I

•

I

•

I

•

I

•

•

I

•

I

,---------- - --,

._I

F~CHXX~

T4

I I I I I
TI

TI

TI

'I

;~~~~ ~~

~

I

~

2_,

I NEXT II NEXT
' - -_ _ _ _ _- , -_ _ _ _ _ _ _ _ _ _..... FIRST
BYTE II NEXT
BYTE 11m
BYTE II f1f1lT
BYTE

I
' - - - - - - - - - - ' QUEU£ , - -

----------.tol.--ADD8I.....-j....._ _ _ _ _ _

_ _ _ _ _ _ _ _ ADDoU,(8.,..'

--

EMPTIED
,JMPI_14 _ _ __

Figure 4-22. Sample Instruction Sequence Execution

System Configuration

transferred and of supporting a number of terminate conditions including byte count expired,
data compare or miscompare and the occurrence
of an external event. The 8089 contains two
separate DMA channels, each with its own
register set. Depending on the established
priorities (both inherent and program determined), the two channels can alternate
(interleave) their respective operations.

The 8089 can be implemented in one of two
system configurations: a "local" mode in which
the 8089 shares the system bus with an 8086 or
8088 CPU and a "remote" mode in which the
8089 has exclusive access to its own dedicated bus
as well as access to the system bus. Note that in
either the local or remote mode, the 8089 can
address a full' megabyte of system memory and
64k bytes of 110 space.

Designed expressly to relieve the 8086 or 8088
CPU of the overhead associated with 110 operations, the 8089, when configured in the remote
mode, can perform a complete 110 task while the
CPU is performing data processing tasks. The
8089, when it has completed its I/O task, can then
interrupt the CPU.

Local Mode

In the local mode, the 8089 acts as a slave to an
8086 or 8088 CPU that is operating in the maximum mode. In this configuration, the 8089
shares the system address latches, data
transceivers and bus controller with the CPU as
shown in figure 4-23.

Transfer flexibility is an integral part of the
8089's design. In addition to routine transfers
between an I/O peripheral and memory, transfers
can be performed between two I/O devices or
between two areas of memory. Transfers between
dissimilar bus widths are automatically handled
by the 8089. When data is transferred from an
8-bit peripheral bus to a 16-bit memory, bus, the
8089 reads two bytes from the peripheral,
assembles the bytes into a 16-bit word and then
writes the single word to the addressed memory
location. Also, both 8- and 16-bit peripherals can
reside on the same (16-bit) bus; byte transfers are
performed with the 8-bit peripheral, and word
transfers are performed with the 16-bit
peripheral.

Since the lOP and CPU share the system bus,
either the lOP or the CPU will have access to the
bus at anyone time. When one processor is using
the bus, the other processor floats its
address/ data and control lines. Bus access
between the lOP and CPU is determined through
the request/grant function. Recalling the CPU's
request/grant sequence, the lOP requests the bus
from the CPU, the CPU grants the bus to the
lOP, and the lOP relinquishes the bus to the CPU
when its operation is complete. Remember that
the CPU cannot request the bus from the lOP
(the CPU is only capable of granting the bus and
4-39

HARDWARE REFERENCE INFORMATION

-r;

eLK

MNIMX

READY
RESET

...

§i-llii

A'9-Ao

07-Do

....

~

elK
iAfA
'-t §i-lIiilllml!

...~

~

MW'fl!

DEN

DT/Ii : ALE

iiQ/OTii

0

-=

.2..

ST80£

- -+

eLK
READY

RESET

-

--=

r-=:
r;

RQ/lrr
RESET

Si·lIii

READY

eLK
DRQ2

EXT 1
ORO 1

ADDAESS BUS

••
•

rX..,

.------

--r-

:DE~DE

:D:~E

_T

ADDRESS/DATA

.

A SE

+

""

I

'--

I
I
I

I
I
I

OE

A'5-A,

mwc
15-BITIIO

E

ADDRESS DECODe

I

:

I A~ggg~~gL 1I

ATABU

t
RAM

(2142)

OOIICE

RC•

(27'' '

___

I

~r--r'

I

+

r

· ~
•

•
.-_7_-.

--r-

I
I

I

,

:

I

•
••

r X ..,

A19-AO

D7-Do

~

'--

'----+

""

E)CT2

-

""

12 Oft 3)

I

I
I

I
I

I
I

I
I

I
I
I

I
I
I

I
I
I
I

,t J 1

1

+
e~DACLKI r:'I/ODACK
.. ~ I CDAeK
.. ~
110 PERIPHERAL
PERIPHERAL
110

r

J

PEAIP~eRAL

ORO

INT

ORO

~

INT

ORO

INT

I

.rt-

Figure 4-23. Typical 8088/8089 Local Mode Configuration
Remote Mode

must wait for the lOP to release the bus). Also,
since the request/grant pulse exchange must be
synchronized, both the CPU and lOP must be
referenced to the samec10ck signal.

The 8089, when used in the remote mode, provides a multiprocessor system with true parallel
processing. In this mode, the 8089 has a separate
(local) bus and memory for I/O peripheral communications, and the system bus is completely
isolated from the I/O peripheral(s). Accordingly,
I/O transfers between an I/O peripheral and the
lOP's local memory can occur simultaneously
with CPU operations on the system bus.

The 8089 lOP, when used in the local mode; can
be added to an 8086 or 8088 maximum mode configuration with little'affect on component count
(channel attention decoding logic as required) and
offers the benefits of intelligent DMA
(scan/match, translate, variable termination conditions), modular' programming in a full
megabyte of memory address space and a set of
optimizedIlO instructions that are unavailable to
the8086 and 8088 CPUs. Themajor disadvantage
to the local configuration is that since the system
bus is shared, bus contention always exists,
between the CPUiand lOP. The use,of the bus
load limit field in, the channel control word can
help reduce lOP bus acceSs dUring task block program execut~on (bus load limiting has no affect on
DMA transfers) although, for I/O intensive
systems, the remote mode should be considered.

As shown in figure 4-24, to interface the 8089 to
the system bus, data transceivers and address
latches are used to separate the lOP's local bus
from the system bus, an 8288 Bus Controller is
used to generate the bus control signals for both
the local and system buses as well as to govern the
operation of the transceivers/latches, an,d an 8289
Bus Arbiteds used to control access to the system
bus (each processor in the system would ,have an
associated 8289 Bus Arbiter). To interface the
8089 to its local bus, another set of add~ess
4-40

HARDWARE REFERENCE INFORMATION
r-----------;===~-AoFROMCPU
110 POM

A~~~':'

MLE~~~Y ~:: ~

"F~~~~~S t--+-+-~..-~1::::::::!r: : ~-

_~

y

_::::=--::::j-lr--:::=--R:,.::ET.'
.... RSRST'I_'

A1S-A1 FROM CPU

L_.G:.'C:.=____ :~~:;';s::MAN.

____

RDY'I~'_-_--_ _

TRANSFER ACKNOWLEDGE
(t.E..XACKt

'-

II "1 1I0D~gi~~ss~GACK
-+I-!I-..+-~

CS

I.......

CA.....- ~~~

CLKI_+-_I-----4~ CLK ....

'---0. sa

PEAI~~ERA~NTI---TO-IFR-O.·IEXT1
ANOTHER lOP

~I~:CK

CONTROL BUS

..... fil5IOr

"_iiiloo-!o-+-~....:.......
,
"
II -------------I-----.j~-I_ot'~
GRO

GRQ2

:.....w"S2-SiiAEN

1~4~"""'i'-!----.·1, PERt~~ERA~NTI----.IEXT2A~~::'~~

I
"
~

L...

L -_ _ _ _ _ _ _ _ _ _ _ _ _

I....

~MULl'IMASTER
l.,...----r

---l.
r--r
52-SO
A-'N

DRQt---·IDRQ1

I ___

elK

.
MROc I
r----

MWi'Cr-----

JNTA
~~B288

MEMORY READ COMMAND
MEMORY WRITE COMMAND

~-+_--~~

LOCAL ADDRESS BUS (A15-AoI

I...

LOCAL DATA BUS

Figure 4-24. Typical 8089 Remote Mode Configuration

Bus Operation

latches is required (unless MCS-85™ multiplexed
address components are exclusively interfaced)
and, depending on the bus loading demands, one
(8-bit bus) or two (l6-bit bus) data transceivers
would be used.

The 8089 utilizes the same bus structure as an
8086 or 8088 CPU that is configured in the maximum mode and performs a bus cycle only on demand (e.g., to fetch an instruction during task
block execution or to perform a data transfer)_
The bus cycle itself is identical to an 8086 or 8088
CPU's bus cycle in that all cycles consist of four
T -states and use the same time-multiplexing
technique of the addressdata lines. As shown in
the following timing diagrams, the address (and
ALE signal) is output during state T 1 for either a
read or write cycle. Depending on the type of
cycle indicated, the addressldata lines are floated
during state T2 for a read cycle (figure 4-25) or
data is output on these lines during a write cycle
(figure 4-26). During state T3, write data is maintained or read data is sampled, and the busy cycle
is concluded in state T 4'

In the remote mode, the lOP's local bus is treated
as 1/0 space (up to 64k bytes), and the system bus
is treated as memory space (l megabyte). The
8288 Bus Controller's 110 command outputs control the local (110) bus, and its memory command
outputs control the system (memory) bus. The
8289 Bus Arbiter, which is operated in its lOB
(1/0 ~ripheral bus) mode, also decodes the
lOP's S2 through SO status outputs. In this mode,
the 8289 will not request the multimaster system
bus when the lOP indicates an operation on its
local bus. If the lOP's bus arbiter currently has
access to the system bus, the CPU's arbiter (or
any other arbiter in the system) can acquire use of
the system bus at this time (a bus arbiter maintains bus access until another arbiter requests the
bus).

Since the 8089 is capable of transferring data to or
from both 8-bit and 16-bit buses, when an 8-bit
physical bus is specified (bus width is specified

4-41

HARDWARE REFERENCE INFORMATION

elK

S2-SO

ADDRESSIS:rATUS

(A~~~!~~,

------\~----------------------------~/~----------~--~'---52-SO ACTIVE
52-SO INACTIVE
\
'-----------'
'----

---~
___ - '

A19-A16

L._ _ _ _ _ _ _ _ _ _

X

~.".

56-53

____________________________

~

~.

----,-'~r---------------------------------------,
___

A15-A8

)--

DATA IN 07-00

'ALE

r - \ ___________________________________

--------~I

I~

"MORC or 'IORC

'DTIA

---..-,-----.\

\'------~!

I

--~

r--

'--------------------------~

I

\

'DEli! _ _ _ _ _ _----J

'8288 BUS CONTROLLER OUTPUTS

Figure 4-25. Read Bus Cycle (8-Bit Bus)

elK

52-SO

ADDRESS/STATUS

-----,\~--------------------------_,Ir-------------~'---52-SO ACTIVE
' - -_ _ _
_ _- - - - J

==~ ~

S2-§O INACTIVE

\L.. __ _

s_,-_s_,____________..J~

} - - - - - { L___A_'_'-_A'_'____XIl.______________

BHE lOW FOR DATA TRANSFER ON HIGH ORDER BYTE (015-08)

ADORESSIDATA

----~

(AD15-AOO) _ _ _ _

'ALE

X

A1S-AO

}--

______ r----\IL_________________________________________
~I

\L-_ _ _ _---..J!

"AMWC OR *AIOWC

\'--_----J!

*MWfC: OR *iOYn::

'OEN

DATA OUT 015-00

''-----'L..__________....J.L..____________________________..J.

---,

\

I

--_ ......' - - - - - - - - '

*8288 BUS CONTROLLER OUTPUTS

Figure 4-26. Write Bus Cycle (l6-Bit Bus)
4-42

HARDWARE REFERENCE INFORMATION

The 8089 operates identically to the 8086 CPU
with respect to the use of the low- and high-order
halves of the data bus. Table 4-14 defines the data
bus use for the various combinations of bus width
and address boundary.

during the initialization sequence), the address
present on the AD15 through AD8 address/data
lines is maintained for the entire bus cycle as
shown in figure 4-25 and, unless added drive
capability is required, the associated address latch
can be eliminated. An 8-bit data bus is compatible
with the 8088 CPU and with the MCS-85™
multiplexed address peripherals (8155, 8185,
etc.).

The S2 through SO status lines define the bus cycle
to be performed. These lines are used by an 8288
Bus Controller to generate all memory and I/O
command and control signals, and are decoded
according to table 4-15.

Table 4-14. Data Bus Usage
Physical Bus Width'
Address

Logical
Bus Width'

Boundary

16

8

I

Byte Transfer

Word Transfer

Even

AD7-ADO = DATA
(SHE not used)

AD7-ADO = DATA
(SHE h.igh)

N/A

Odd

AD7-ADO = DATA
(SHE not used)

. AD15-AD8 = DATA
(SHE low)

N/A

Even

Illegal

AD7-ADO = DATA
(SHE high)

AD15-ADO = OAT A
(SHE low)

Odd

Illegal

AD15-AD8 = DATA
(SHE low)

N/A'

8

16

Notes:
1.

Logical bus width is specified by the WID instruction prior to the DMA transfer.

2.

Physical bus width is specified when the 8089 is initialized.

3.

A word transfer to or from an odd boundary is performed as two byte transfers. The first byte transferred is the low-order byte on the high-order data bus (AD15-AD8), and the .second byte is the highorder byte on the low-order data bus (AD7-ADO). The 8089 automatically assemb.les the two bytes in
their proper order.

Table 4-15. Bus Cycle Decoding
Status Output
S2

S1

SO

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Bus Cycle Indicated
Instruction fetch from I/O space
Data read from I/O space
Data write to I/O space
Not uSed
Instruction fetch from system memory
Data read from system memory
Data write to system memory
Passive

4-43

Bus Controller
Command Output
INTA
IORC
IOWC,AIOWC
None
MRDC
MRDe
MWTC,AMWC
None

HARDWARE REFERENCE INFORMATION

Note that the 8089 indicates. an instruction fetch
from 1/0 space as a status of zero (S2, SI and' SO
equal 0). Since the 8288 Bus Controller decodes
an input status value of zero as an interrupt
acknowledge bus cycle, the bus controller's INTA
output must be OR'ed with its IORC output to
permit fetching of task block instructions from
local 8089 memory (remote configuration) or
system 110 space (local and remote
configtirations).
.

(RDYI or RDY2). Either of these inputs, when
enabled by its corresponding AENI or AEN2
input, can be deactivated directly by the memory
or 110 device when it must extend the 8089's bus
cycle (when the addressed device is not ready to
present or accept data). The 8284's READY output, which is synchronized to the CLK signal, is
directly connected to the 8089'8 READY input.
As shown in figure 4-27, when the addressed
device requires one or more wait states to be
inserted into a bus cycle, it deactivates the 8284's
RDY input prior to the end of state T2' The
READY output from the 8284 is subsequently
deactivated at the end of state T 2 which causes the
8089 to insert wait states following state T3' To
exit the wait state, the device activates the 8284's
RDY input which causes the READY input to the
8089 to go active on the next clock cycle and
allows the 8089 to enter state T4'

The S2 through SO status lines become active in
state T4 if a subsequent bus cycle is to be performed. These lines are set to the passive state (all
"ones") in the state immediately prior to state T4
of the current bus cycle (state T 3 or T w) and are
floated when the 8089 does not have access to the
bus.
The S6 through S3 status lines are multiplexed
with the high-order address bits (AI9-AI6) and,
accordingly, become valid in state T2 of the bus
cycle. The S4 and S3 status lines reflect the type of
bus cycle being performed on the corresponding
channel as indicated in table 4-16.

elK

Table 4-16. Type of Cycle Decoding
READY

OUTPUT

Status Output
S4
S3

a

0
0

1

1
1

1

0

-

'Awel'
RDY INPUT

Type of Cycle

READY

--11-

'Awel

'-11- --1 I-- ,elA,X'

•

\ ..._ _
NO_'A_EA_DY_____'

READY

*REFER TO THE 8284 CLOCK GENERATOR/DRIVER DATA SHEET IN APPENDIX B FOR
TIMING INFORMATION

Figure 4-27. Wait State Timing
DMA on Channel 1
DMA on Channel 2
Non-DMA on Channel 1
Non-DMA on Channel 2

The S6 and S5 status lines are always" 1" on the
8089. Since these lines are not both "1" on the
other processors in the 8086 family (S6 is always
"0" on the 8086 and 8088 CPUs), these status
lines can be used as a "signature" in a
multiprocessor environment to identify' the type
of processor performing the bus cycle.
The 8089 includes the same provision as do the
8086 and 8088 CPUs for the insertion of wait
states (T w) in bus cycle when the associated
memory or I/O device cannot respond within the
alloted time'interval or when, in the remote mode,
the 8089 must wait for access to the system bus.
An 8284 Clock Generator/Driver is used to control the insertion of wait states which, when
r~quired, are inserted between states T3 and T4'
The actual insertion of wait states is accomplished
by deactivating one of the 8284's RDY inputs

Periods of inactivity can occur between bus
cycles. These inactive periods are referred to as
. idle states (T I) and, as with the 8086 and 8088
CPUs, can result from the execution of a "long"
instruction or the loss of the bus to another processor during task block instruction execution.
Additionally, the 8089 can experience idle states
when it is in the DMA mode and it is waiting for a
DMA request from the addressed 110 device or
when the bus load limit (BLL) function is .enabled
for a channel performing task block instruction
execution and the other channel is idle.

a

InitiaUzation
Initialization of the lOP is generally the respon,sibilityof the host processor which, as. stated in
Chapter 3, prepares the communications data
structure in shared memory. Initialization of the
lOP itself begins with the activation of its RESET
input. This input (originating typically from an
4-44

HARDWARE REFERENCE INFORMATION

8284 Clock Generator/Driver) must be held active
for at least five clock cycles to allow the 8089's
internal reset sequence to be completed. Note that
like the 8086 and 8088 CPUs, the RESET input
must be held active for at least 50 microseconds
when power is first applied. Following the reset
interval, the host processor signals the lOP to
begin its initialization sequence by activating the
8089's CA (Channel Attention) input. The 8089
will not recognize a pulse at its CA input until one
clock cycle after the RESET input returns to an
inactive level. Note that the minimum width for a
CA pulse is one clock cycle and that this pulse
may go active prior to RESET returning to an
inactive level provided that the negative-going,
trailing-edge of the CA pulse does not occur prior
to one clock cycle after RESET goes inactive.
Figure 4-28 illustrates the timing for this portion
of the initialization sequence.

and an 8089 share a common bus, the 8089 must
be designated the slave. Also, when the RQ/GT
line is not used (i.e., a single 8089 in the remote
configuration), the 8089 must be designated a
master.

In addition to determining master/slave status,
the CA pulse also causes the 8089 to begin execution of its internal ROM initialization sequence.
Note that since the 8089 must have access to the
system bus in order to perform this sequence, the
8089 immediately initiates a request/grant
sequence (if designated a slave) and, if required,
then requests the bus through the 8289 Arbiter.
(If designated a master, the 8089 requests the bus
through the 8289 Arbiter.) In the execution of the
initialization sequence, the 8089 first fetches the
SYSBUS byte from location FFFF6H. The W bit
(bit 0) of this byte specifies the physical bus width
of the system bus. Depending on the bus width
specified, the 8089 then fetches the address of the
system configuration block (SCB) contained in
locations FFFF8H through FFFFBH in either two
bus cycles (16-bit bus, W bit equal 1) or four bus
cycles (8-bit bus, W bit equal 0). The SCB offset
and segment address values fetched are combined
into a 20-bit physical address that is stored in an
internal register. Using this address, the 8089 next
fetches the system operation command (SOC)
byte. As explained in Chapter 3, this byte
specifies both the request/grant operational mode
(R bit) and the physical width of the I/O bus (I
bit). After reading the SOC byte, the 8089 fetches
the channel control block (CB) offset and segment address values. These values are combined
into a 20-bit physical address and are stored in
another internal register. To inform the host CPU
that it has completed the initialization sequence,
the 8089 clears the Channel 1 Busy flag in the
channel control block by writing an all "zeroes"
byte to CB + 1.

elK

RESET

~8~~,~i ~~~~ \' - - - - - - -

CYCLES

1-'

eLK

MIN-I

CA -----------~~~~CA
_ _ _ _ _ _ _ _,___ J~~~~ RECOGNIZED

Figure 4-28. RESET -CA Initialization Timing
Coincident with the trailing edge of the first
CA pulse following reset, the 8089 samples its
SEL (Select) input from the host processor to
determine master/slave status for its
request/ grant circuity. If the SEL input is low,
the 8089 is designated a "master," and if the SEL
input is high, the 8089 is designated a "slave." As
a master, the 8089 assumes that it has the bus
initially, and it will subsequently grant the bus to
a requesting slave when the bus becomes available
(i.e., the 8089 will respond to a "request" pulse
on its RQ/GT line with a "grant" pulse). A single
8089 in the remote configuration (or one of two
8089s in a remote configuration) would be
designated a master. As a slave, the 8089 can only
request the bus from a master processor (i.e., the
8089 initiates the request/grant sequence by outputting a "request" pulse on its RQ/GT line). An
8089 that shares a bus with an 8086 or 8088 (or
one of two 8089s in a remote configuration)
would be designated a slave. Note that since the
8086 and 8088 CPUs can grant the bus only in
response to a request, whenever an 8086 or 8088

After the lOP has been initialized, the system
configuration block may be altered in order to initialize another lOP. Once an lOP has been initialized, its channel control block in system
memory cannot be moved since the CB address,
which is internally stored by the lOP during the
initialization sequence, is automatically accessed
on every subsequent CA pulse.
4-45

HARDWARE REFERENCE INFORMATION

parameter block and writing the address of
the parameter block in the channel control
block.

As previously stated, the generation of the CA
and SEL inputs to the lOP are the responsibility
of the host CPU. Typically. these signals result
from the CPU's execution of an liD write·
instruction to one of two adjacent liD ports (liD
port addresses that only differ by AD). Figure 4-29
illustrates a simple decoding circuit that could be
used to generate the CA and SEL signals. Note
that by qualifying the CA output with 10WC, the
SEL output, since it is latched for the entire liD
bus cycle, is guaranteed to be stable on the trailing
edge of the CA pulse.

•

In response to the CA, the 8089 interrupts any
current activity at its first opportunity (see "Concurrent Channel Operation" in section 3.2) and
begins execution of an internal instruction
sequence that fetches and decodes the channel
command word (CCW) and then performs the
operation indicated (i.e., start, halt or continue
channel program execution).

A7

If the CCW specifies start channel program (start
task block execution), the address of the
parameter block is fetched from the channel
control block, the address of the first channel
program instruction (contained in the first four
bytes of the parameter block) is fetched and then
loaded into the TP (task pointer) register and,
finally, task block execution is initiated from
either system or I/O space. Task block execution
continues, subject to the activity on the other
channel as described in "Concurrent Channel
Operation," until a XFER instruction is
executed. Following execution. of this instruction,
the next sequential channel program instruction is
executed before the channel enters the DMA
transfer mode.

A6
AS
A4
530

A3
A2
Al

CA

iOm:
•

AO

5EL

PORT FC = CHANNEL 1 CA
PORT FD = CHANNEL 2 CA

Figure 4-29. Channel Attention Decoding Circuit

1/0 Dispatching

If the CCW specifies halt channel, the current
operation on the specified channel is halted. If the
channel is performing task block execution (either
chained or not chained), channel operation is
stopped at an instruction boundary, and if the
channel is performing a DMA transfer, channel
operation is stopped at a DMA transfer cycle
boundary. Note that a channel will not stop a
locked DMA transfer until the operation is completed. There are two unique halt channel commands. One command simply halts the channel
and clears the busy flag in the channel control
block. This command is used when the halted
operation is to be discarded. The other command
halts the channel, saves the task pointer and program status word (PSW) byte, and clears the busy
flag. This command is used when the halted
operation is to be resumed. Note that this halt
command will not affect the integrity of resumed
task block execution or a memory-to-memory
DMAtransfer, but could affect the integrity of a
synchronized DMA transfer (a DMA request
occuring while the channel is halted could be
missed).

During normal operation, the liD supervisory
program running in the host CPU will receive a
request to perform a specific I/O operation on
one of the 8089's channels. In response to this
request, the supervisory program will typically
perform the following sequence of operations:
•
Check the availability of the specified
channel by examining the channel's busy flag
in the Channel Control Block. If it is possible
for another processor to access the channel, a
semaphore operation (implemented by a
locked XCHG instruction) is used to check
channel availability.
•

•
•

Load the variable parameters required for
the intended operation into the channel's
parameter block.
Load the channel command word (CCW)
into the channel control block.
Establish the necessary linkages by writing
the starting address of the channel program
(task block) in the first four bytes of the

Mnemonics © Intel. 1979

Issue a channel attention (CA) to the
specified channel.

4-46

HARDWARE REFERENCE INFORMATION

If the CCW specifies continue channel, an opera-

address boundary (odd or even address). The
8089 performs DMA transfers between dissimilar
bus widths by assembling bytes or disassembling
words in its internal assembly register file. As
explained in Chapter 3, the DMA source and
destination bus widths are defined by the execution of a WID instruction during task block
(channel command) execution. Note that the bus
widths specified remain in force until changed by
a subsequent WID instruction. Table 4-18 defines
the various byte (B) and word (W)
source/destination transfer combinations based
on address boundary and bus width specified.

tion that has been previously halted is resumed
(and the busy flag is set). Since this command
restores the task pointer and PSW, it should be
used only if the task pointer and PSW have been
saved by a previous halt command.
Table 4-17 outlines the various CCW command
execution times. Note that the times listed in the
table for the halt commands do not include the
time required to complete any current channel
activity when the channel attention is received
(completion of the current DMA transfer cycle or
task block instruction).

DMA Transfers

The 8089 additionally optimizes bus accesses during transfers between dissimilar bus widths
whenever possible. When either the source or
destination is a 16-bit memory bus (autoincrementing) that is initially aligned on an odd

The number of bytes transferred during a single
DMA cycle is determined by both the source and
destination logical bus widths as well as by the

Table 4-17. CCW Command Execution Times
CCWCommand

Minimum Time'

Maximum Time"

CANOP
CA Halt (no save)
CA Halt (with save)
CA Start (memory)
CA Start (1/0)
CAContinue

48 + 2n clocks
48 + 2n clocks
94 + 5n clocks
108 + 6n clocks
96 + 5n clocks
95 + 5n clocks

48 + 2n clocks
48 + 2n clocks
100 + 6n clocks
124 + 10nclocks
108 + 8n clocks
103 + 6n clocks

Notes:
n is the number of wait states per bus cycle.
*

Minimum time occurs when both the channel control block and parameter block addresses are aligned on
an even address boundary and a 16-bit bus is used.
Maximum time occurs when both the channel control block and parameter block addresses are aligned
on an odd address boundary on a 16-bit bus or when an 8-bit bus is used.

Table 4-18. DMA Assembly Register Operation
Logical Bus Width
(Source ..... Destination)

Address Boundary
(Source .... Destination)

8 ..... 8
S .....
S ....
B .....
S .....

Even .... Even
Even .... Odd
Odd ..... Even
Odd ..... Odd

4-47

S
S
B
S

8 ..... 16

16- 8

S/B ..... W
S ..... S
S/B ..... W
S ..... S

W ..... S/B
W .... S/S
S ..... B
S ..... S

16 ..... 16
W ..... W

w . . . SIS
S/B ..... W
S ..... S

Mnemonics © Intel, 1979

HARDWARE REFERENCE .INFORMATI.ON

address boundary (causing the first transfer cycle
to be byte-to-byte), following the first transfer
cycle, the memory address will be aligned on an
even address boundary, and word transfers will
subsequently occur. For example, when performing a memory-to-port transfer from a 16-bit bus
to an 8-bit bus with the source beginning on an
odd address boundary, the first transfer cycle will
be byte-to-byte (B -+ B) as indicated in table 4-18,
but subsequent transfers will be word-tobytelbyte (W -+ BIB).

The DRQinput is asynchronous and usually
originates from an 1/0 device controller rather
than from a memory circuit. This input is latched
on the positive transition of the clock (CLK)
signal and therefore must remain active for more
than one clock period (more than 200.
nanoseconds when using a 5 MHz clock) in order
to guarantee that it is recognized.
During state T 1 of the associated fetch bus cycle
(source synchronized) or store bus cycle (destination synchronized), the lOP outputs the address
of the 1/0 device (the port address). This address
must be decoded (by' external circuitry) to
generate the DMA acknowledge (DACK) signal
to the liD controller as the response to the controller's DMA request. An lIO controller will
typically use DACK as a conditional input for the
removal of DRQ. (After receipt of the DACK
signal, most Intel peripheral controllers deactivate DRQ following receipt of the corresponding read or write signal.) Figures 4-30 and 4-31
illustrate the DRQ/DACK timing for both source
synchronized (Le., port-to-memory) and destination synchronized (Le., memory-to-port)

All DMA transfer cycles consist of at least two
bus cycles; one bus cycle to fetch (read) the data
form the source into the lOP, and one bus cycle
to store (write) the data previously fetched from
the lOP into the destination. Note that in all
transfers, the data passes through the lOP to
allow masklcompare and translate operations to
be optionally performed during the transfer as
well as to allow the data to be assembled or
disassembled.
The lOP performs DMA transfers in one of three
modes: unsynchronized, source synchronized or
destination synchronized (the transfer mode is
specified in the channel control register). The unsynchronized mode is used when both the source
and destination devices do not provide a data request (DRQ) signal to the lOP as in the case of a
memory-to-memory transfer. In the synchronized
transfer modes, the source (source synchronized)
or destination (destination synchronized) device
initiates the transfer cycle by activating the lOP's.
DRQl (channell) or DRQ2 (channel 2) input.

transf~rs.

Table 4-19 defines the DMA transfer cycles in
terms of the number of bus and clock cycles required. Note that the number of clocks required
to complete a transfer cycle does not take into account the effects of possible concurrent operations on the other channel or wait states within
any of the bus cyCles.

elK

DRQ~

(FROM 110 DEVICE)

•

DAeK
(DECODED 110 ADDRESS)

---1I VALID 110 ADDRESS PRESENt \'-_ _ _ _ _ _ _ _-""

NOTES:
1. INDICATES THE NUMBER OF IDLE CLOCK CYCLES INSERTED BEFORE THE NEXT
TRANSFER CYCLE BEGINS. IF ORO IS RECEIVED PRIOR to STAte T4 OF THE CURRENT
FETCH CYCLE, THE NEXT FETCH CYCLE BEGINS IMMEDIATELY FOLLOWING THE
CURRENT STORe CYCLE.
2. IF THE 8089 IS IDLE WHEN ,ORO IS'RECOGNIZED, FIVE IDLE CLOCK CYCLES OCCUR
BEFORE THE ASSOCIATED TRANSFER CYCLE IS INITIATED.

Figure 4-30. Soutce Synchronized Transfer Cycle
4-48

HARDWARE REFERENCE INFORMATION

elK
ORO HOLD
FROM WRITE

-1 _ _1
I

ORO' -------------i~[!!=~
ADO~:~~

CLOCKS 3

tOLE-I_SIDLE CLOCKS 3 - _

CLOCKS J

~ ~

(FROM 110 DEVICE)

(DECODED 110

1-2IDLE~I-4

,r~;Q_:_;;;N_;;~R:~~;;_YCLE-I+-------~~=~

--JJ

_________

NOTES:

VALID 110 ADDRESS PRESENT

,r-----

~ ~

•

\I..___________.J!

L

1. FIRST OMA FETCH CYCLE OCCURS IMMEDIATELY AFTER THE LAST TASK BLOCK
INSTRUCTION IS EXECUTED.
2. FETCH BUS CYCLE 2 BEGINS IMMEDIATELY FOLLOWING STORE BUS CYCLE 1.
3. INDICATES THE NUMBER OF IDLE CLOCK CYCLES INSERTED BEFORE STORE BUS
CYCLE 2 BEGINS. IF ORO 15 RECEIVED PRIOR TO STATE T4 OF STORE BUS CYCLE 1,
STORE BUS CYCLE 2 BEGINS IMMEDIATELY FOLLOWING FETCH BUS CYCLE 2.
4. IF THE 8089 IS IDLE WHEN ORO IS RECOGNIZED, FIVE IDLE CLOCK CYCLES OCCUR
BEFORE THE ASSOCIATED STORE BUS CYCLE IS INITIATED.

Figure 4-31. Destination Synchronized Transfer Cycle

Table 4-19. DMA Transfer Cycles
Transfer Mode
Logical Bus Width
Source Synchronized

Unsynchronized
Source Destination

8
8

16'

8

16'
16'

16'

8

Bus Cycles
Required

TotaP
Clocks

Bus Cycles
Required

Total'
Clocks

2(1 fetch, 1 store)
3 (2 fetch, 1 store)
3 (1 fetch, 2 store)
2 (1 fetch, 1 store)

8'
12
12

2 (1 fetch, 1 store)
3 (2 fetch, 1 store)
3 (1 fetch, 2 store)
2 (1 fetch, 1 store)

16'
12

8

8'
8

Destination Synchronized
Bus Cycles
Required
2 (1 fetch,
3 (2 fetch,
3 (1 fetch,
2 (1 fetch,

1 store)
1 store)
2 store)
1 store)

Total'
Clocks

8'
12
16'

8

Notes:
1. The "Total Clocks Required" does not include wait states. One clock cycle per wait state must be
added to each fetch and/or store bus cycle in which a wait state is inserted. When performing a
memory-to-memory transfer, three additional clocks must be added to the total clocks required (the
first fetch cycle of any memory-to-memory transfer requires seven clock cycles).
2.

When performing a translate operation, one additional 7-clock bus cycle must be added to the values
specified in the table.

3.

Word transfers in the table assume an even address word boundary. Word transfers to or from odd
address boundaries are performed as indicated in table 4-18 and are subject to the bus cycle/clock
requirements for byte-to-byte transfers.

4.

Transfer cycles that include two synchronized bus cycles (i.e., synchronous transfers between
dissimilar logical bus widths) insert four idle clock cycles between the two synchronized bus cycles
to allow additional time for the synchronzing device to remove its initial DMA request.

4-49

HARDWARE REFERENCE INFORMATION

more than one terminate condition is possible,
displacements (which are added to the task
pointer register value) are specified to cause task
block execution to resume at a unique entry point .
for each condition. Three reentry points are
available: TP, TP + 4 and TP+ 8. The time interval between the occurrence of a terminate condition and the resumption of task block !!xecution is
12 clock cycles for reentry point TP
15 clock
cycles for reentry points TP + 4 and TP + 8.

DACK latency is defined as the time required for
the 8089 to acknowledge, by outputting the
device's corresponding port address, a DMA
request at its DRQ input. This response latency is
dependent on a number of factors including the
transfer cycle being performed, activity on the
other channel, memory address boundaries, wait
states present in either bus cycle and bus arbitration times.

and

Generally, when the other channel is idle, the
maximum DACK latency is five clock cycles (l
microsecond at 5 MHz), excluding wait states and
bus arbitration times. An exception occurs when
performing a word transfer to or from an odd
memory address boundary. This operation, since
two store (source synchronized) or two fetch
(destination synchronized) bus cycles are required
to access memory, has a maxirimm possible latency of nine clock cycles. When the other channel is
performing DMA transfers of equal priority
("P" bits equal), interleaving occurs at bus cycle
boundaries, and the maximum latency is either
nine clock cycles when' the other channel is performing a normal 4-clock fetch or store bus cycle
or twelve clock cycles when the other channel is
performing the first fetch cycle of a memory-tomemory transfer. If the other channel is performing "chained" task block instruction execution of
equal priority, maximum latency can be as high as
12 clock cycles (channel command instruction
execution is interrupted at machine cycle boundaries which range from two to eight clock
cycles).

Peripheral Interfacing
When interfacing a peripheral to an 8-bit physical
data bus, the 8089 uses only the lower half of the
address/data lines (AD7-ADO) as the bidirectional data bus, and the upper half of' the address/data lines (AD15-AD8) maintain address
information for the entire bus cycle. Consequently, with this bus configuration, only one octal
latch (e.g., an Intel® 8282/83 Octal Latch) is required since only the lower half of the address/ data lines is time-multiplexed (unless the
address bus requires the increased current drive
capability and capacitive load immunity provided
by the latch).
When interfacing a peripheral to a 16-bit data
bus, both the lower and upper halves of the address/data lines are time-multipelxed, and two,octal.latches are required. Note that unlike, the 8086
and 8088 CPUs, the 8089 does not time-multiplex
BHE (this signal is valid for the entire bus cycle).
Both 8- and 16-bit peripherals can be interfaced to
a 16-bit bus. An 8-bit peripheral can be connected
to either the upper or lower half of the bus. An 8.
bit peripheral on the lower half of the bus must
use an even source/destination address, and an 8bit peripheral on the upper half of the bus must
use an odd source/destination address. To take
advantage of word transfers, a 16-bit peripheral
must use an even source/destination address.

DMA Termination
As stated in Chapter 3, a channel can exit the
DMA transfer mode (and return to task block
execution) on any of the following terminate
conditions:
• Single cycle transfer
• Byte count expired
• Mask/compare match or mismatch
• External event

To prepare a peripheral device for a DMA
transfer, command and parameter'data is written
to the device's command/status port. This is
usually accomplished using pointer register GC.
Recalling that the 8089 executes one additional
task block instruction fOllowing execution of the
XFER instruction (the XFER instruction' causes
the 8089 to enter the DMA mode), this additional
instruction is used to ·access the command port of
an I/O device that immediately begins DMA

The terminate conditions are specified by individual fields in: the channel control register.
More than one terminate condition can be
specified for a transfer (e.g., a transfer can be terminated when a specific byte count is reached or
on the occurrence of an external event). When
Mnemonics © Intel, 1979

4-50

HARDWARE REFERENCE INFORMATION

operation on receipt of the last command (the
8271 Floppy Disk Controller begins its DMA
transfer on receipt of the last command
parameter). Since a translate DMA operation requires the use of all three pointer registers (GA
and GB specify the source and destination addresses; GC specifies the base address of the
translation table), when it is necessary to use the
last task block instruction to start the device,
command port access can be accomplished
relative to one of the pointer registers or relative
to the PP register. If the device's data port address (GA or GB) is below the device's command
port address, either an offset or an indexed
reference can be used to access the command
port.

individual DMA acknowledge (DACK) is returned to only the active device. DACK decoding can
be accomplished with an Intel ® 8205 Binary
Decoder or a ROM circuit. Note that the 8089 can
only determine which device has requested service
or terminated by the context of the task block
program.
Most peripheral devices interfaced to the 8089 will
use the decoded DMA acknowledge signal
(DACK) as the "chip select" input. Peripheral
devices that do not follow this convention must
use DACK as a conditional input of chip select.
While most interrupts associated with the 8089
will be DMA requests or external terminates, nonDMA related interrupts can additionally be
supported.

A peripheral's (or peripheral controller's) DMA
communication protocol with the 8089 is as
follows:
• The peripheral (when source or destination
synchronized) initiates a DMA transfer cycle
by activating the 8089's DRQ (DMA request)
input.
•

•

•

•

One technique that would be used when an 8089 is
the local configuration (or when an 8086 or 8088
and an 8089 are locally connected as a remote
module) is to allow the CPU to accept the interrupt and then direct the 8089 to the interrupt service routine. Another technique is to allow the
8089 to "poll" the device to determine when an
interrupt has occurred (most peripheral controllers have an interrupt pending bit in a status
word). The 8089's bit testing instructions are
ideally suited for polling.

The 8089 acknowledges the request by
placing the peripheral's assigned data port
address on the bus during state T 1 of the corresponding fetch (source synchronized) or
store (destination synchronized) bus cycle.
The peripheral is responsible for decoding
this address as the DMA acknowledge
(DACK) to its request.

When the 8089 is in a remote configuration, nonDMA related interrupts can be supported with the
addition of an Intel® 8259A Programmable
Interrupt Controller. Systems that require this
type of interrupt structure would dedicate one of
the 8089's channels to interrupt servicing. In
implementing this structure, the interrupt output
from the 8259A is directly connected to the channel's external terminate (EXT) input, and the
channel's DMA request (DRQ) input is not used.
A task block program is initially executed to perform a source-synchronized DMA transfer (with
an external terminate) on the "interrupt" channel
to "arm" the interrupt mechanism. Since the
DRQ input is not used, when the channel enters
the DMA transfer mode, the channel idles while
waiting for the first DMA request (which never
occurs). The other channel, since the interrupt
channel is idle, operates at maximum throughput.
When an interrupt occurs, the "pseudo" DMA
transfer is immediately terminated, and task
block instruction execution is resumed. The task
block program would write a "poll" command to
the 8259A's command port and then read the

The data is transferred between the
peripheral and the 8089 during the T 2
through T 4 state interval of the bus cycle.
The peripheral must remove its DMA request
during this interval.
The peripheral, when ready, requests another
DMA transfer cycle by again activating the
DRQ input, and the above sequence is
repeated.
The peripheral can, as an option, end the
DMA transfer by activating the 8089's EXT
(external terminate) input.

The 8089 can support mulitple peripheral devices
on a single channel provided that only one device
is in the active transfer mode at anyone time. To
interface multiple devices, the DMA request
(DRQ) lines are OR'ed together as are the external terminate (EXT) lines. Unique port addresses
are, however, assigned to each device so that an
4-51

HARDWARE REFERENCE INFORMATION

8259A's data port to acknowledge the interrupt
and to determine the device responsible for the
interrupt (the device is identified by a 3-bit binary
number in the associated data byte). The device
number read would be used by the task block program as a vector into a jump table for the device's
interrupt service routine. Pertinent interrupt data
could be written into the associated parameter
block for subsequent examination by the host
processor.

(table 4-24) and a table to "disassemble" any
machine instruction back into its associated
assembly language equivalent (table 4-26).
Figure 4-32 shows the format of a typical 8089
machine instruction. Except for the LPDI and
memory-to-memory forms of the MOY and
MOYB instructions that are six bytes long, all
8089 machine instructions consist of from two to
five bytes. The first two bytes are always present
and are generally formatted as shown in figure
4-32 (table 4-24 contains the exact encoding of
every instuction).

The interrupt mechanism previously described,
since it uses the 8089's external terminate function, provides an extremely fast interrupt
response time.

Bits 5 through 7 of the first byte of an instruction
comprise the R/B/P field. This field identifies a
register, bit select or pointer register operand as
outlined in table 4-20.

Note that when using dynamic RAM memory
with the 8089, an Intel® 8202 Dynamic RAM
Controller can be used to simplify the interface
and to perform the RAM refresh cycle. When
maximum transfer rates are required, the RAM
refresh cycle can be externally initiated by the
8089. By connecting the decoded DACK (DMA
acknowledge) signal to the 8202's REFRQ
(refresh request) input, the refresh cycle will occur
coincident with the 110 device bus cycle and
therefore will not impose wait states in the
memory bus cycle.

Table 4-20. R/B/P Field Encoding

Instruction Encoding
Most 8089 programming will be performed at the
assembly language level using ASM-89, the 8089
assembler. During program debugging, however,
it may be necessary to work directly with machine
instructions when monitoring the bus, reading unformatted memory dumps, etc. This section contains both a table to encode any ASM-89 instruction into its corresponding machine instruction
BYTE 1

I I I

I I I

R/B/PI WB I AA Iw

Register

Bit

Pointer

000
001
010
011
100
101
110
111

GA
GB
GC
BC
TP

0
1

GA
GB
GC
NJA
TP
NJA
NJA
NJA

I I I II II

1

IMM

L

2

3
4

5
6

IX

CC
MC

7

The WB field (bits 3 and 4 of the first byte) indicates how many displacement! data bytes are
present in the instruction as outlined in table 4-21.
The displacement bytes are used in program
transfers; one byte is present for short transfers,
while long transfers contain a two-byte (word)
displacement. As mentioned in Chapter 3, the

- ~Y~:" - 4- - .!~ ~ -

BYTE 2

OPCODE

Code

+- - ~:; ~ - -l

11~111lllllllllllll111~
OFFSET

I LOW DISPIDATA I HIGH DISPIDATA I

_____ L

_____

~

_____

BASE REGISTER FOR MEMORY OPERAND
OPERATION (INSTRUCTION) CODE
WIDTH (BYTE OR WORD OPERANDS)
MEMORY ADDRESSING MODE
NUMBER OF DISPLACEMENT IDATA BYTES
REGISTER, BIT, POINTER SELECT

Figure 4-32. Typical 8089 Machine Instruction Format
Mnemonics © Intel, 1979

4-52

~

HARDWARE REFERENCE INFORMATION

displacement is stored in two's complement notation with the high-order bit indicating the sign.
Data bytes contain the value of an immediate constant operand. A byte immediate instruction
(e.g., MOVBI) will have one data byte, and a
word immediate instruction (e.g., ADD!) will
have two bytes (a word) of immediate data. An
instruction may contain either displacement or
data bytes, but not both (the TSL instruction is an
exception and contains one byte of displacement
and one byte of data). If an offset byte is present,
the displacement/data byte(s) always follow the
offset byte.

Bits 7 through 2 of the second instruction byte
specify the instruction opcode. The opcode, in
conjunction with the W field of the first byte,
identifies the instruction. For example, the opcode "111011" denotes the decrement instruction; if W=O, the assembly language instruction is
DECB, while if W=I, the instruction is DEC.
Table 4-26 lists, in hexadecimal order, the opcode
of every assembly language instruction.
The MM field (bits 0 and 1) indicates which
pointer (base) register is to be used to construct
the effective address of a memory operand. Table
4-23 defines the MM field encoding. (Memory
operand addressing is described in section 3.8.)

Table 4-21. WB Field Encoding
Code

00
01
10
11

Table 4-23. MM Field Encoding

Interpretation
No displacement/data bytes
One displacement/data byte
Two displacement/data bytes
TSL instruction only

The AA field specifies the addressing mode that
the processor is to use in order to construct the effective address of a memory operand. Four addressing modes are available as outlined in table
4-22. (Address modes are described in detail in
section 3.8.)
.

Code

Base Register

00
01
10
11

GA
GB
GC
pp

When the AA field value is "01" (base register
+ offset addressing), the third byte of the instruction contains the offset value. This unsigned value
is added to the content of the base register
specified by the MM field to form the effective
address of the memory operand.

Table 4-22. AA Field Encoding

00
01
10
11

When the AA field value is "10," the IX register
value is added to the content of the base register
specified by the MM field to provide a 64k range
of effective addresses. (Note that the upper four
bits of the IX register are not sign-extended.)

Interpretation

Code

Base register only
Base register plus offset
Base register plus IX
Base register plus IX,
auto-increment

When the AA field value is "11," the IX register
value is added to the base register value to form
the effective address as described for an AA field
value of "10." In this addressing mode, however,
the IX register value is incremented by one after
every byte accessed.

Bit 0 of the first instruction byte indicates whether
the instruction operates on a byte (W=O) or a
word (W=I).

Table 4-24. 8089 Instruction Encoding
DATA TRANSFER INSTRUCTIONS

MOV = Move word variable

78543210

78543210

78543210

Memory to register

RRROOAAI

100000MM

offset it AA-01

Register to memory

RRROOAAI

1 000.0 1 M M

6ff.olll AA=OI

Memory to memory

OOOOOAAI

100100MM

offset if AA""01

4-53

78543210

00000 A A 1

78543210

1"

0 011 M M

78543210

I

off.otiIAA-Ol

I

Mnemonics © Intel, 1979

HARDWARE REFERENCE INFORMATION

Table 4-24. 8089 Instruction Encoding (Cont'd.)
DATA TRANSFER INSTRUCTIONS (Cont'd.)

Mova • Move byte variable

78643210

78643210

78543210

Memory to register

RRROOAAO

100000MM

off••tIfAA-01

Register to memory

RRROOAAO

100001MM

off••tIfAA=01

Memory to memory

OOOOOAAO

100100MM

offset If AA...01

Moyai

III:

Move byte Immediate

Immediate to register

Immediate to memory

=

: MOVI

Move word Immediate

Immediate to register
Immediate to memory

MOVP.= Move pointer

Memory to pointer register
Pointer register to memory

LPD

III:

LPDI

off••t If AA=OI

Load pointer with doublaword variable

= load pOtnler with doubleword Immediate

ARITHMETIC INSTRUCTIONS

ADD. Add word variable

Memory to ,register
Register to memory

ADDB

= Add byte variable

Memory to fegister

Register to memory

ADDI

l1li:

Add word Immediate

Immediate to register
Immediate to memory

Mnemonics

© Intel; 1979

4-54

78643210

00000 A A 0

78543210

11

1001 1 M M"'

78643210

offsstlfAA=01

I

HARDWARE REFERENCE INFORMATION

Table 4-24.8089 Instruction Encoding (Cont'd.)
ARITHMETIC INSTRUCTIONS (Conl'd.)

ADDBI

= Add byte immediate

78543210

78543210

78543210

78543210

78543210

78543210

Immedalte to register

Immediate to memory

INC

= Increment word by 1

Register
Memory

INCB • Increment byte by 1

100000 A A 0 11 1 1 01 0 M M

I

oH.elifAA=Ol

DEC = Decrement word by 1
Register
Memory

OEca

= Decrement byte by 1

100000 A A 01111011 M M

I

olf.etif AA-01

LOGICAL AND BIT MANIPULATION iNSTRUCTIONS

AND. AND word variable
Memory to register
Register to memory

ANDB • AND byte variable
Memory to register

Regi8terto memory

ANDI • AND word Immediate

Immediate to register

Immediate to memory

ANDBI

= AND byle immediate

Immediate to register

Immediate to memory

OR

= OR word variable

Memory to register
Register to memory

4-55

Mnemonics © Inlel, 1979

HARDWARE REFERENCE INFORMATION

Table 4-24.8089 Instruction Encoding (Cont'd.)
LOGICAL AND BIT MANIPULATION INSTRUCTIONS (Conl'd.)

ORB = OR byte variable

76543210

76543210

76543210

Register

RRROOOOO

o0

Memory

o0

0 0 0 A A1

1 1 0 1 1 1 M M

offset if AA=01

Memory to register

RRROOAA1

1 0 1 0 1 1 M M

offset if AA=01

seTS = Set bit to 1

IBBBOOAAOl111101MM

offset if AA=01

eLR = ClearbittoO

BBBOOAAO 1111110MM

offset if AA=01

76543210

Memory to register

Register to memory

ORI

= OR word immediate

Immediate to register
Immediate to memory

ORBI

= OR byte immediate

Immediate to register
Immediate to memory

NOT = NOT word variable

NOTB

1 0 1 1 0 0

= NOT byte variable

Memory

Memory to register

PROGRAM TRANSFER INSTRUCTIONS

·CALL = Call

LCALL = Long call

·JMP = Jump unconditional

LJMP

= Long jump unconditional

l'

0001 000 1001 00000

disp-8

1'001000'100'00000

dlsp-Io

*The ASM-89 Assembler will automatically generate the long form of a program transfer instruction ,when the
target is known to be beyond the byte-displacement range.

Mnemonics © Intel, 1979

4-56

I
I

76543210

76543210

HARDWARE REFERENCE INFORMATION

Table 4-24.8089 Instruction Encoding (Cont'd.)
PROGRAM TRANSFER INSTRUCTIONS (Conl'd.l

7 8 5 4 3 2 1 0

*JZ = Jump if word IsO

7 8 5 4 3 2 1 0

7 8 5 4 3 2 1 0

7 8· 5 4 3 2 1 0

Label to register

disp-8

label to memory

offset If AA=01

disp-8

offset if AA-01

disp-8

LJZ

7 8 5 4 3 2 1 0

7 8 5 4 3 2 1 0

= Long jump if word Is 0

Label to register
Label to memory

-JZB. Jump if byte IsO

UZB

= Long jump if byte is 0

*JNZ

= Jump If word natO

Label to register
Label to memory

UNZ

= Long jump If word not 0

Label to register
Label to memory

*JNZB

= Jump If byte notO

UNZ8

=

*JMCE

= Jump If masked compare equal

LJMCE

= Long jump If masked compare equal

Long jump if byte not 0

*JMCNE

= Jump If masked compare notequai

WMCNE

=

*JBT

Long jump if masked compare not equal

= Jump If bit Is 1

-The ASM-89 Assembler will automatically

gen~rate

the long form of a program transfer Instruction when the

target Is known to be beyond the byte-displacem.ent range.

4-57

Mnemonics © Intel, 1979

HARDWARE REFERENC.E INFORMATION

Table 4-24.8089 Instruction Encoding (Cont'd.)

PROGRAM TRANSFER INSTRUCTIONS (Cont'd.)

78543210

76543210

78543210

7854~210

78543210

78543210

= Long jump if hit Is 1

LJBT

·JNBT = Jump if bit is notl

LJNBT

= Long jump if bit is not 1

PROCESSOR CONTROL INSTRUCTIONS

TSl = Test and set while locked

WID = Set logical bus widths

11 S O' 0 0 0 0 0

I

0 0 0 0 0 0 0 0

'S=source width, D=destination width; 0=8 bits, 1=16 bits

XFER

SINTR

= Enter OMA mode
= Set interrupt service bit

101100000100000000

101000000100000000

HLT

= Halt channel program

100100000101001000

NOP

= No operation

100000000100000000

'The ASM-89 Assembler will automatically generate the long form of a program transfer instruction when the
target is known to be beyond the byte-dlsplacement range.

assembled machine instruction into its ASM-89
symbolic form. The preceding table (table 4-25)
defines the notation used in table 4-26.

Table 4-26 lists all of the 8089 machine instructions in hexadecimal/binary order by their second
byte. This table may be used to "decode" an
Mnemonics © Intel, 1979

4-58

HARDWARE REFERENCE INFORMATION

Table 4-25. Key to 8089 Machine Instruction Decoding Guide
Identifier

Explanation

5

Logical width of source bus; 0=8, 1=16
Logical width of destination bus; 0=8, 1=16
Pointer register encoded in RI B/P field
Register encoded in RI B/P field
AA (addressing mode) field
Bit select encoded in RI B/P field
Low-order byte of offset word in doubleword pOinter
High-order byte of offset word in doubleword pointer
Low-order byte of segment word in doubleword pointer
High-order byte of segment word in doubleword pointer
8-bit immediate constant
Low-order byte of 16-bit immediate constant
High-order byte of 16-bit immediate constant
8-bit signed displacement
Low-order byte of 16-bit signed displacement
High-order byte of 16-bit signed displacement
Optional 8-bit offset used in offset addressing

0
PPP
RRR
AA
BBB
offset-Io
offset-hi
segment-Io
segment-hi
data-8
data-Io
data-hi
disp-8
disp-Io
disp-hi
(offset)

Table 4-26. 8089 Machine Instruction Decoding Guide
Byte 2
Byte 1
00000000
01000000
15DOOOOO
01100000

Hex

Binary

00
00
00
00
01

00000000
00000000
00000000
00000000
00000001

+

PPP10001

07
08
09

RRR01000
RRR10001
10001000
10010001

1F
20
20
20
20
21

RRR01000
RRR10001

23
24
24
25

+

+

+

RRR01000

27
28

Bytes 3, 4, 5, 6

NOP
51NTR
WID source-width,dest-width
XFER

}

+

00000111
00001000
00001001

offset-Io,offset-hi,segment-Io,segment-hi

data-8
data-Io,data-hi
disp-8
disp-Io,disp-hi

}
data-8
data-Io,data-hi

not used

not used

ORBI register,immed8
ORI register,immed16

}

+

00100111
00101000

ptr-reg,immed32

ADDBI register,immed8
ADOI register,immed16
JMP short-label
LJMP long-label

+

00100011
00100100
00100100
00100101

not used

LPDI

}

+

00011111
00100000
00100000
00100000
00100000
00100001

ASM89 Instruction Format

data-8

not used

ANDBI

4-59

register,immed8

Mnemonics © Intel, 1979

HARDWARE REFERENCE INFORMATION

Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte2

Byte 1

RRR10001

Hex

Binary

28
29

00101000
00101001

+

RRROOOOO

2B
2C
20

RRR01000
RRR10001

2F
30
30
31

RRROOOOO

37
38
39

RRROOOOO

3B
3C
3D

RRR01000
RRR10000

3F
40
40
41

RRR01000
RRR10000

43
44
44
45

00100000

47
48
49

+

+
+

+

+

+

+

00001AAO

+

00001AAO
00010AA1

t

00010AA1

4B
4C

+

4F
4C

+

4F
50

+

RRROOAAO

7F
80

RRROOAAO

83

+

Mnemonics © Intel, 1979

Bytes 3, 4, 5, 6

data-Io,data-hi

ANDI

}

+

00101011
00101100
00101101

}
data-8
data-Io,data-hi

}

+

}

+

}
disp-8
disp-Io,disp-hi

}
disp-8
disp-Io,disp-hi

}

+

+

}

(offset) ,data-8

+

}

(offset),data-Io,data-hi

+

not used

not used

not used

}
}
}

not used

MOVBI

MOVI

mem8,immed8

mem16,immed16

} not used

+

100000MM

register

HLT

+

01111111
100000MM

not used

JZ register ,short-label
LJZregister,short-label

01000111
01001000
01001001

010011 MM
01010000

register

JNZ reg ister, short-label
LJNZ register, long-label

t

010011 MM
010011 MM

not used

DEC

+

01001011
010011MM

not used

INC

00111011
00111100
00111101

01000011
01000100
01000100
01000101

register

MOVBI register,immed8
MOVI register,immed16

00110111
00111000
00111001

00111111
01000000
01000000
01000001

register,immed16

not used

NOT

+

00101111
00110000
00110000
00110001

ASM89 Instruction Format

}

}

(offset)

4-60

MOVB

register,mem8

HARDWARE REFERENCE INFORMATION

Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1

RRROOAA1

+

RRROOAA1
RRROOAAO

+

RRROOAAO
RRROOAA1

+

RRROOAA1
PPPOOAA1

+

PPPOOAA1
PPPOOAA1

+

PPPOOAA1
OOOOOAAO

+

OOOOOAAO
00000AA1

t

00000AA1
00011AAO

+

00011AAO
PPPOOAA1

t
PPPOOAA1
10001AA1

+

10001AA1
10010AA1

+

Byte2
Hex

Binary

80

100000MM

+

83
84

t

87
84

+

87
88

+

8B
8C

+

8F
90

t

93
90

t

93
94

+

97
98

t

9B
9C

t

9F
9C

t

+

}

+

}
}
}
}
}

100000MM
100001 MM
100001 MM
100001 MM

+

100001 MM
100010MM

+

100010MM
100011MM

+

100011 MM
100100MM

t

100100MM
100100MM

+

} (offset)

101000MM
101000MM

RRROOAA1
RRROOAAO

A3
A4

101000MM
101001MM

RRROOAAO
RRROOAA1

A7

A4

101001MM
101001MM

RRROOAA1
RRROOAAO

A7
A8

101001 MM
101010MM

t

+

RRROOAAO

t

t

+

AB

(offset),OOOOOAAO, 110011 MM,(offset)

}

A3
AO

t

(offset)

t

t

RRROOAAO
RRROOAA1

t

(offset)

} (offset)

+

100111MM
100111MM
100111MM
101000MM

t

(offset)

+

t

100110MM
100111MM

9F
AO

t

(offset)

t

t

100101 MM
100110MM

10010AA1
RRROOAAO

t

(offset)

}
}
}
}
}
}
}

t

100100MM
100101 MM

t

101010MM

ASM89 Instruction Format

Bytes 3, 4, 5, 6

(offset),OOOOOAA 1,110011 MM,(offset)

(offset) ,data-8,disp-8

(offset)

(offset),disp-8

(offset),d isp-Io,d isp-h i

(offset)

(offset)

(offset)

4-61

}
}
}

MOVB

}

LPD

}
}
}
}
}
}
}
}
}
}
}
}

register,mem16

MOV

mem8,register

mem16, register

MOV

ptr-reg,mem32

MOVP

ptr-reg,mem24

MOVB

mem8,mem8

MOV

mem16,mem16

TSL

mem8,immed8,short-label

mem24, ptr-reg

MOVP

mem24,short-label

CALL

LCALL

ADDB

mem24,long-label

register,mem8

ADD

register,mem16

ORB

register,mem8

OR

register,mem16

ANDB

mem8,register

Mnemonics © Intel, 1979

HARDWARE REFERENCE INFORMATION

Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1

Byte2
Hex

Binary

RRROOAA1

A8

101010MM

t

t

RRROOAA1
RRROOAAO

t

RRROOAAO
RRROOAA1

t

RRROOAA1
00001AAO

t

00001AAO
00010AAO

t

00010AAO
00001AAO

t

00001AAO
00010AAO

t

00010AAO
BBB01AAO

t

BBB01AAO
BBB10AAO

t

BBB10AAO
BBB01AAO

t

BBB01AAO
BBB10AAO

t

BBB10AAO
00001AAO

t

00001AAO
00010AA1

t

00010AA1
00001AAO

t

00001AAO
00010AA1

t

00010AA1
00001AAO

t

00001AAO

AB
AC

t

AF
AC

t

AF
BO

t

B3
BO

t

B3
B4

t

B7
B4

t

B7
B8

t

BB
B8

t

BS
BC

t

BF
BC

t

BF
CO

t

C3
CO

t

C3
C4

t

C7
C4

t

C7
C8

t

CB

Mnemonics © Intel, 1979

Bytes 3, 4, 5, 6

t

}
}
}

t

}

t

t

}
}
}
}

t

} (offset) ,disp-Io,d isp-h i

t
t

}
}

t

}

t

}
}
}
}

t

101010MM
101011MM

t

101011 MM
101011 MM
101011MM
101100MM
101100MM
101100MM
101100MM
101101 MM

t

101101 MM
101101 MM

t

101101 MM
101110MM
101110MM
101110MM
101110MM
101111MM
101111MM
101111 MM
101111MM
110000MM
110000MM
110000MM
110000MM
110001 MM

t

110001 MM
110001 MM

t

110001MM
110010MM

t

110010MM

ASM89 Instruction Format

(offset)

}

(offset)

} NOTB

(offset)

(offset),disp-8

(offset),disp-Io,disp-hi

}
}
}

AND

mem16,register

register,mem8

NOT

register,mem16

JMCE

mem8,short-label

LJMCE

mem8, long-label

(offset),disp-8

} JMCNE

(offset),disp-Io,disp-hi

} LJMCNE

(offset),disp-8

}
}

JNBT

(offset) ,disp-Io,d isp-hi

LJNBT

(offset) ,data-8

}
}
}
}
}
}

(offset),data-8

(offset), data-Io, data-h i

(offset),data-8

4-62

mem8,bit-select,long-label

mem8, bit-select, short-label

LJBT

mem8,bit-select,long-label

ADDBI

(offset) ,data-Io,data-h i

mem8, long-label

mem8,bit-select,short-label

} JBT

(offset),disp-8

mem8,short-label

mem8,immed8

ADDI

mem16,immed16

ORBI

mem8,immed8

ORI

mem16,immed16

ANDBI

mem8,immed8

HARDWARE REFERENCE INFORMATION

Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1

00010AA1

t
00010AA1

Byte 2
Hex

Binary

C8

110010MM

CB
CC

110010MM
11001100

CF
DO

11001111
110100MM

t

t

RRROOAAO

+

RRROOAAO
RRROOAA1

+

RRROOAA1
RRROOAAO

+

t

03
DO

+

03
04

+

RRROOAAO
RRROOAA1

07
04

RRROOAA1
RRROOAAO

07
08

RRROOAAO
RRROOAA1

DB
08

t
t

t

RRROOAA1
RRROOAAO

+

RRROOAAO
RRROOAA1

+

RRROOAA1
00001AAO

+

00001AAO
00001AA1

+

00001AA1
00010AAO

+

00010AAO
00010AA1

+

+

+

+

DB
DC

+

OF
DC

+

OF
EO

+

E3
EO

+

+

+

110100MM
110100MM

}
}

not used

}
}
}
}
}

ADDB

(offset)

mem8,register

(offset)

}

ORB

mem8,register

(offset)

}

(offset)

} ANDB mem8,register

+

} (offset)

} AND mem16,register

+

} (offset)

t

}

(offset)

+

}

(offset),disp-8

} JNZB

+

}

(offset).disp-8

}

+

+

}
}

t

}

t

} (offset),disp-8

+

110101MM
110101 MM

t

110101 MM
110110MM

t

110110MM
110110MM

OR

110110MM
110111 MM
111l111MM
110111MM
110111MM
111000MM
111000MM
111000MM

111000MM
111000MM
111000MM
111001MM

00001AAO
00001AA1

E7
E4

111001MM
111001MM

00001AA1

E7

111001MM

t

mem16,immed16

mem16,register

E3
E4

t

ANDI

ADD

E3
EO

t

}

}

00010AA1
00001AAO

t

ASM89 Instruction Format

(offset)

+

110100MM
110101MM

111000MM
111000MM

+

} (offset),data-Io,data-hi

+

E3
EO

t

Bytes 3, 4, 5, &

mem16,register

}
}

NOTB

NOT

mem16,register

mem8,short-label

JNZ mem16,short-label

(offset),disp-Io,disp-hi

}

(offset),disp-Io,disp-hi

}

(offset),disp-8

} JZB

LJNZB

mem8,long-label

LJNZ mem16,longlabel

} JZ

4-63

mem8,register

mem8,short-label

mem16,short-label

Mnemonics·© Intel, 1979

HARDWARE REFERENCE INFORMATION

Table 4-26.8089 Machine Instruction Decoding Guide (Cont'd.
Byte 1

Byte 2
Hex

Binary

00010AAO

E4

111001MM

00010AAO
00010AA1

E7
E4

111001 MM
111001MM

00010AA1
OOOOOAAO

E7
E8

111001 MM
111010MM

OOOOOAAO
00000AA1

EB
E8

111010MM
111010MM

00000AA1
OOOOOAAO

EB
EC

111010MM
111011MM

OOOOOAAO
00000AA1

EF
EC

111011MM
111011MM

00000AA1

EF
FO

111011MM
11110000

BBBOOAAO

F3
F4

11110000
111101MM

BBBOOAAO
BBBOOAAO

F7
F8

111101MM
111110MM

BBBOOAAO

FB
FC

111110MM
11111100

FF

11111111

t
t
t

t

t
t

t

t

t

t

t
t

t

t
t

t
t

t

Mnemonics ©Intel, 1979

Bytes 3, 4, 5, 6

ASM89 Instruction Format

}

t

}
}
}
}
}

t

} (offset)

} DEC

t

t
t

t

(offset),d isp-Io,disp-h i

(offset),disp-Io,disp-hi

LJZB

}
}

LJZ

INCB

(offset)

(offset)

}

(offset)

} DECB

INC

t

mem8,long-label

mem16,long-label

mem8

mem16

mem8

mem16

} not used

t

} (offset)

} SETB

t

} (offset)

} GLR

t

mem8,0-7

mem8,0-7

} not used

4-64

Appendix A
Application Notes

APPENDIX A
APPLICATION NOTES

This appendix contains Intel application notes pertinent to the 8086 family microprocessors. The following
application notes, in the order listed, have been included within this appendix:
AP-67
AP-61
AP-50
AP-51
AP-59
AP-28A
AP-43

8086 System Design
Multitasking for the 8086
Debugging Strategies and Considerations for 8089 Systems
Designing 8086, 8088, 8089 Multiprocessing Systems with the 8289 Bus Arbiter
Using the 8259A Programmable Interrupt Controller
Intel® Multibus™ Interfacing
Using the iSBC-957™ Execution Vehicle for Executing 8086 Program Code

A-li A-2

APPLICATION
NOTE

Ap·67

September 1979

© Intel CorporatIon 1979

A-3

AP-67

8086 System Design

Contents
1. INTRODUCTION

2. 8086 OVERVIEW AND BASIC SYSTEM
CONCEPTS
A.
B.
C.
D.

Bus Cycle Definition
Address and Data Bus Concepts
System Data Bus Concepts
Multiprocessor Environment

3. 8086 SYSTEM DETAILS
A.
B.
C.
D.
E.
F.
G.

Operating Modes
Clock Generation
Reset
Ready Implementation and Timing
Interrupt Structure
Interpreting the 8086 Bus Timing Diagrams
Bus Control Transfer

4. INTERFACING WITH 1/0

5. INTERFACING WITH MEMORIES
6. APPENDIX

A-4

AP·67
1. INTRODUCTION

guage Reference Guide (9800749A), AP-28A MULTIBUS™ Interfacing (98005876B), INTEL MULTIBUS™
SPECIFICATION (9800683), AP-45 Using the 8202 Dynamic RAM Controller (9800809A), AP-51 Designing
8086, 8088, 8089 Multiprocessor Systems with the 8289
Bus Arbiter and AP-59 Using the 8259A Programmable
Interrupt Controller. References to other Intel publications will be made throughout this note.

The 8086 family, Intel's new series of microprocessors
and system components, offers the designer an advanced system architecture which can be structured to
satisfy a broad range of appllcatlons_ The variety of
speed, configuration and component selections available within the family enables optimization of a specific
design to both cost and performance objectives. More
important however, the 8086 family concept allows the
designer to develop a family of systems providing multiple levels of enhancement within a single design and a
growth path for future designs.

2. 8086 OVERVIEW AND BASIC SYSTEM CONCEPTS
2A. 8086 Bus Cycle Definition
The 8086 is a true 16-bit microprocessor with 16-blt Internal and external data paths, one megabyte of memory
address space (2**20) and a separate 64K byte (2**16)
I/O address space. The CPU communicates with its external environment via a twenty-bit time multiplexed address, status and data bus and a command bus. To
transfer data or feich instructions, the CPU executes a
bus cycle (Fig. 2A 1). The minimum bus cycle consists of
four CPU clock cycles called T states. During the first T
state (T1), the CPU asserts an address on the twenty-bit

This application note Is directed toward the implementation of the system hardware and will provide' an introduction to a representative sample of the systems
configurable with the 8086 CPU member of the family.
Application techniques and timing analysis will be given
to aid the designer In understanding the system requirements, advantages and limitations. Additional Intel
publications the reader may wish to reference are the
8086 User's Manual (9800722A), 8086 Assembly Lan-

!--T,_
CLK

-----'

)(

-

-T2-

~

lL'

A191S6,A161S3

-

I-

~T,rrw

~

T4-

...,v-----

..,~

}.

STATUS

ADDR

-

READY

-

ADDRESS A15-Ao \

D

----1--- IX

FLOAT

DA A IN D15'Do

)(r..UiAr" r----r-- -----

RD
READ
CYCLE

V

DTiii

1\

DEN

X

0

ADDRESS

X

V

JC:..

DATA OUT

WR
WRITE
CYCLE

V

DEN

DTIR

---

~-

--- -

Figure 2A 1. Basic 8086 Bus Cycle

A-5

AP-67
multiplexed address/data/status bus. For the second T
state (T2), the CPU removes the address from the bus
and either three-states its outputs on the lower sixteen
bus lines in preparation for a read cycle or asserts write
data. Data bus transceivers are enabled in either T1 or
T2 depending on the 8086 system configuration and the
direction of the transfer (into or out of the CPU). Read,
write or interrupt acknowledge commands are always
enabled in T2. The maximum mode 8086 configuration
(to be discussed later) also provides a write command
enabled in T3 to guarantee data setup time prior to command activation.
During T2, the upper four multiplexed bus lines switch
from address (A19-A16) to bus cycle status
(S6,S5,S4,S3). The status information (Table 2A1) is
available primarily for diagnostic monitoring. However,
a decode of S3 and S4 could be used to select one of
four banks of memory, one assigned to each segment
register. This technique allows partitioning the memory
by segment to expand the memory addressing beyond
one megabyte. It also provides a degree of protection by
preventing erroneous write operations to one segment
from overlapping into another segment and destroying
information in that segment.

Since the CPU prefetches up to six bytes of the instruction stream for storage and execution from an internal
instruction queue, the relationship of instruction fetch
and associated operand transfers may be skewed in
time and separated by additional instruction fetch bus
cycles. In general, if an instruction is fetched into the
8086's internal instruction queue, several additional instructions may be fetched before the instruction is
removed from the queue and executed. If the instruction
being executed from the queue is a jutnp or other control transfer instruction, any instructions remaining in
the queue are not executed and are discarded with no effect on the CPU's operation. The bus activity observed
during execution of a specific instruction is dependent
on the preceding instructions but is always deterministic within the specific sequence.
Table 2A1

S3

S4

o

o
o

1

o

Alternate (relative to the ES segment)
Stack (relative to the SS segment)
Code/None (relative to the CS segment or a default of zero)
Data (relative to the OS segment)

The CPU continues to provide status information on the
upper four bus lines during T3 and will either continue
to assert write data or sample read data on the lower sixteen bus lines. If the selected memory or I/O device is
not capable of transferring data at the maximum CPU
transfer rate, the device must signal the CPU "not
ready" and force the CPU to insert additional clock
cycles (Wait states TW) after T3. The 'not ready' indication must be presented to the CPU by the start of T3.
Bus activity during TW is the same as T3. When the
selected device has had sufficient time to complete the
transfer, it asserts" Ready" and allows the CPU to continue from the TW states. The CPU will latch the data on
the bus during the last wait state or during T3 if no wait
states are requested. The bus cycle is terminated in T4
(command lines are disabled and the selected external
device deselects from the bus). The bus cycle appears
to devices in the system as an asynchronous event consisting of an address to select the device followed by a
read strobe or data and a write strobe. The selected
device accepts bus data during a write cycle and drives
the desired data onto the bus during a read cycle. On termination of the command, the device latches write data
or disables its bus drivers. The only control the device
has on the bus cycle is the insertion of wait cycles.

S5 = IF (interrupt enable flag)
S6 0 (indicates the 8086 is on the bus)

=

2B_ 8086 Address and Data Bus Concepts
Since the majority of system memories and peripherals
require a stable address for the duration of the bus
cycle, the address on the multiplexed address/data bus
during T1 should be latched and the latched address
used to select the desired peripheral or memory location. Since the 8086 has a 16-bit data bus, the multiplexed bus components of the 8085 family are not applicable to the 8086 (a device on address/data bus lines
8-15 will not be able to receive the byte selection address on lines 0-7). To demultiplex the bus (Fig. 2B1a),
the 8086 system provides an Address Latch Enable
signal (ALE) to capture the address in either the 8282 or
8283 8-bit bi-stable latches (Diag. 2B1). The latches are
either inverting (8283) or non-inverting (8282) and have
outputs driven by three-state buffers that supply 32 mA
drive capability and can switch a 300 pF capacitive load
in 22 ns (inverting) or 30 ns (non-inverting). They propagate the address through to the outputs while ALE is
high and latch the address on the falling edge of ALE.
This only delays address access and chip select
decoding by the propagation delay of the latch. The outputs are enabled through the low active OE input. The
demultiplexing of the multiplexed address/data bus
(Iatchings of the address from the multiplexed bus), can
be done locally at appropriate points in the system or at
the CPU with a separate address bus distributing the address throughout the system (Fig. 2B1b). For optimum
system performance and <:ompatibility with multiprocessor and MULTIBUS™ configurations, the latter technique is strongly recommended over the first. The remainder of this note will assume the bus is demultiplexed at the CPU.

The 8086 CPU only executes a bus cycle when instructions or operands must be transferred to or from
memory or I/O devices. When not executing a bus cycle,
. the bus interface executes idle cycles (TI). During the
idle cycles, the CPU continues to drive status information from the previous bus cycle on the upper address
lines. If the previous bus cycle was a write, the CPU continues to drive the write data onto the multiplexed bus
until the start of the next bus cycle. If the CPU executes
idle cycles following a read cycle, the CPU will not drive
the lower 16 bus lines until the next bus cycle is
required.

A-6

AP-67
The programmer views the 8086 memory address space
as a sequence of one million bytes in which any byte
may contain an eight bit data element and any two consecutive bytes may contain a 16-bit data element. There
is no constraint on byte or word addresses (boundaries).
The address space is physically implemented on a sixteen bit data bus by dividing the addrllss space into two
banks of up to 512K bytes (Fig. 2B2). One bank is connected to the lower half of the sixteen-bit data bus (07-0)
and contains even addressed bytes (AD =0). The other
bank is connected to the upper half of the data bus
(015-8) and contains odd addressed bytes (AD = 1). A
specific byte within each bank is selected by address
lines A19-A1. To perform byte transfers to even addresses (Fig. 2B3a), the information is transferred over
the lower half of the data bus (07-0). AD (active low) is
used to enable the bank connected to the lower half of
the data bus to participate in the transfer. Another
signal provided by the 8086, Bus High Enable (BHE), is
used to disable the bank on the upper half of the data
bus from participating in the transfer. This is necessary
to prevent a write operation to the lower bank from
destroying data in the upper bank. Since BHE is a
multiplexed signal with timing identical to the A19-A16
address lines, it also should be latched with ALE to provide a stable signal during the bus cycle. Ouring T2
through T4, the BHE output is multiplexed with status
line S7 which is equal to BHE. To perform byte transfers
to odd addresses (Fig. 2B3b), the information is transferred over the upper half of the data bus (015-08) while
BHE (active low) enables the upper bank and AD
disables the lower bank. Oirecting the data transfer to
the appropriate half of the data bus and activation of
BH E and AD is performed by the 8086, transparent to the
programmer. As an example, consider loading a byte of
data into the CL register (lower half of the CX register)
from an odd addressed memory location (referenced
over the upper half of the 16-bit data bus). The data is
transferred into the 8086 over the upper 8 bits of the
data bus, automatically redirected to the lower half of
the 8086 internal 16-bit data path and stored into the CL
register. This capability also allows byte 1/0 transfers
with the AL register to be directed to 1/0 devices connected to either the upper or lower half of the 16-bit data
bus.

8088

ADDRESS
BUS

Figure 2B1a. Demultiplexing the 8086 Bus

ADDRESS BUS

8088
CPU

DATA BUS
SEPARATE ADDRESS AND DATA BUSSES

r------.,
I

I

I

I

I

:I
I

I

8088

;. .'----.~-----1

CPU

.. ALE

f-~--

'---''"'--_ _J\ ADDRESS/DATA

I

BUS

I
I

,
L ______ J
I

,

MULTIPLEXED BUS WITH LOCAL ADDRESS DEMULTIPLEXING

To access even addressed sixteen bit words (two consecutive bytes with the least significant byte at an even

Figure 2B1b.

T,
CLK
--J

~

T2

T3
~

r---\

-- --- v,

'---

ALE

Tw

lr-i~

DATA IN OR OUT

T,

~

---

X ---

-X--

-

\--_-

r--

\

I

Diagram 2B1. ALE Timing

A-7

-

AP-67
byte address),A19-A1 select the appropriate byte within
each bank and AO and SHE (active low) enable both
banks simultaneously (Fig. 2S3c). To access an odd addressed 16-bit word (Fig. 2S3d), the least significant
byte (addressed by A 19-A1) is first transferred over the
upper half of the bus (odd addressed byte, upper bank,
SHE low active and AO= 1). The most significant byte is
accessed by incrementing the address (A19-AO) which
allows A19-A1 to address the next physical word location (remember, AO was equal to one which indicated a
word referenced from an odd byte boundary). A second
bus cycle is then executed to perform the transfer of the
most significant byte with the lower bank (AO is now active low and SHE is high). The sequence is automatically
executed by the 8086 whenever a word transfer is executed to an odd address. Directing the upper and lower
bytes of the 8086's internal sixteen-bit registers to the
appropriate halves of the data bus is also performed
automatically by the 8086 and is transparent to the programmer.

,--_ _..,TRANSFER X+ I, Xr-_ _--.

Figure 2B3c. Even Addressed Word Transfer
FIRST BUS CYCLE

.l\

4.

:>..

....

S>""

512K BYTES

FFFFF

FFFFF

FFFF£

FFFFE

FFFFO

FFFFC,

I

FFFFD
FFFFC

~

~

Y+l
j0%; (X+ 1) W,

V

(8) PHYSICAL IMPLEMENTATION OF THE
ADDRESS SPACE
512K BYTES

(A) LOGICAL ADDRESS SPACE

AO(LOW)

015- D8

O,s-De

l

IV

1

Y
X
C>-

L.)..

~

BHE (LOW)

Ao(HIGH)

1 MEGABYTE

Figure 2B2. 8086 Memory
TRANSFER X

-V

Y

IV

--4C'--

4.

i:>..

I

~_I

1
A'9-A1

Figure 2B3d. Odd Addressed Word Transfer

~ ~(X)~

Y+l
X+l

1\

015-08

7"

""'07-00
"

BHE (HIGH)

Ao (LOW)

Figure 2B3a. Even Addressed Byte Transfer
TRANSFER X + 1

..1\

IV'

1
A19-A,

Y+l
(:0: (X + 1)

...,;

:>..

'"

5>-

0,,-0,

t\

'0:

IV

Y
X

2C. System Data Bus Concepts
When referring to the system data bus, two implementation alternatives must be considered; (a) the multiplexed address/data bus (Fig. 2C1a) and a data bus buffered from the multiplexed bus by transceivers (Fig.
2C1b).

<)..

_I

BHE (LOW)

During a byte read, the CPU floats the entire sixteen-bit
data bus even though data is only expected on the upper
or lower half of the data bus. As will be demonstrated
later, this action simplifies the chip select decoding requirements for read only devices (ROM, EPROM). During
a byte write operation, the 8086 will drive the entire
sixteen-bit data bus. The information on the half of the
data bus not transferring data is indeterminate. These
concepts also apply to the I/O address space. Specific
examples of I/O and memory interfacing are considered
in the corresponding sections.

"" 7"
0,-00

Figure 2B3b. Odd Addressed By1e Transfer

Ao (HIGH)

If memory or 1/0 devices are connected directly to the
multiplexed bus, the designer must guarantee the
devices do not corrupt the address on the bus during T1.

A-8

AP-67
To avoid this, device output drivers should not be enabled bY the device chip select, but should have an output
enable controlled by the system read signal (Fig. 2C2).
The' 8086 timing guarantees that read Is not valid ,until
after the address Is latched by ALE (Olag. 2C1). All Intel
peripherals, EPROM products and RAM's for microprocessors provide output enable or read inputs to allow
connection to the multiplexed bus.

MULTIPLEXED DATA BUS

ADDREBS

ALE----I

ADDRESS BUS

MULTIPLEXED
' - - - - - - - ' - - - - . . , / ADDRESS/DATA

Figure 2Cla. Multiplexed Data Bus
BUFFERED DATA BUS

iiii------01
Figure 2C2. Device. with Output Enable. on the Multiplexed Bua

8282

Several techniques are available for interfacing devices
without output enables to the multiplexed bus but each
introduces other restrictions or limitations. Consider
Figure 2C3 which has chip select gated with read and
write. Two problems exist with this technique. First, the
chip select access time is reduced to the read access
time, and may require a faster device if maximum
system performance (no walt states) is to be achieved
(Olag. 2C2). Second, the designer must verify that chip
select to write setup and hold times for the device are
not violated (Oiag. 2C3). Alternate techniques can be extracted from the bus Interfacing techniques given later
In this section but are subject to the associated restrictions. In general, the best solution is obtained with
devices having output enables.

SYSTEM
BUS

A subsequent limitation on the multiplexed bus Is the
8086's drive capability of 2.0 mA and capacitive loading
of 100 pF to guarantee the specified A.C. characterIstics. Assuming capacitive loads of 20 pF per 1/0
device, 12 pF per address latch and 5-12 pF per memory
device, a system mix of three peripherals and two to
four memory devices (per bus line) are close to the
loading limit.

Figure 2Clb. Bull.red Data Bua

Tl

ALE

/

T2

T3

T4

,----

\.

-----

Diagram 2Cl. Relationship of ALE to READ

A-9

AP·67

ADDRESS

ALE

'--_ _ _ _ _ _ _ _ _..J\

MULTIPLEXED BUS

Figure 2C3. Device. without Output Enable. on the Multiplexed Bu.

ADDRESS---\...._ _ _ _ _ _ _ _ _ _ _ _ __

DATA----------+--~

1 ACCESS TIME FOR CS GENERATED FROM ADDRESS DECODE.
2 ACCESS TIME IF CS IS GATED WITH RD/WH.

Diagram 2C2. Access Time: CS Gated with iiiilWR

ADDR~'_

_____

~--------

lu

WR---~----,

sa

~

1 CS lS NOT VALID PRIOR TO WRITE AND BECOMES ACTIVE ONE OR TWO GATE
DELAYS LATER.

2 CS REMAINS VALID AFTER WRITE ONE OR TWO GATE DELAYS.

Diagram 2C3. CS to WR Set·Up and Hold

To satisfy the capacitive loading and drive requirements
of larger systems, the data bus must be buffered. The
8286 non-Inverting and 8287 inverting octal transceivers
are offered as part of the 8086 family to satisfy this requirement. They have three-state .output buffers that
drive 32 mA on the bus interface arid .10 mA 011 the CPU
interface ano can switch capacitive loads of 300 pF at
the bus interface and 100 pF on the CPU interlace in 22
ns (8287) or 30 ns (8286). To enable and cont~onthe direction of the transceivers, the 8086 systemprov,ldes Data
ENable (DEN) and Data Transmit/Receive(DTiRj slgnliis
(Fig. 2C1 b). These signals provide the appropriate timing to guarantee isolation of the multiplexed'bus from
the system during T1 and elimination of bus contention
with the CPU during read and write (Diag. 2C4). Although
the memory and peripheral devices are isolated from the
CPU (Fig. 2C4), bus contention 'may stlll exist in the
system if the devices do riot have an output enable control other than chip select. AS an example, bus contllntion will exist during transition from one chip select to
another (the newly selected device begins driving the
bus before the previous device has disabled its drivers).
Another, more severe case exists during a write.cycle.
From chip select to write active, a dJlvice whose outputs
are controlled only by chip select, will drive the bus
simultaneously with write data being driven through the
transceivers by the CPU (Dlag. 2C5). The same technique given for circumventing these problems ,on the
multiplexed bus can be applied here with the' same limitations.
'
One last extension to the bus implementation Is a sec- '
ond level of buffering to reduce the total load seen by ,
devices on the system bus (Fig. 2C5). This Is typically
done for multiboard systems and Isolation of memory
arrays. The concerns with this configuration are the, additional delay for access and more important, conVol of
the second transceiver in relationship to the system blls
and the device being interfaced to the system bus.
Several techniques for controlling the transoeiver are
given in Figure 2C6. This first technique (Fig. 2C6a)
simply distributes DEN and DTIR ·throughout the
system. DT/R is inverted to prQvide proper direQtiori control for the second level transceivers. The seconG·exampie (Fig. 2C6b) provides control for devices with output
enables. RD is used to normally direct data from, the
system bus to the periptleral. The .buffElT is sel!lcted
whenever a device on the local bus is Chip $elected. Bus
contention Is possible on the device~s local bus during a
read as the read simultaneously enables the device output and changes the transceiver direction. The contention may also occur as the read is·terminated.
For devices without output enables, the same technique
can be applied (Fig. 2C6c) If the chip select to the device
Is conditioned by read or write. Controlling the chip
select with read/wrlte prevents the device from driving
against the transceiver prior to the command being
received. The, limitations with this technique are access
limited to read/write time and limited CS to write setup
and hold times.

A-lO

AP-67

r--- Tlll_~__ T2~~T3-_r------T4~

ADo

AD1swADo

1

READ
CYCLE

-+---+--"X

ADDRESSA15-/Io

IFLO;"

--

---1r---r--.../'--t--t---'--- - - -

X

DATA IN

D..-D,

)(

FLoAT" ------- - - - - -

iiii
DTIA

- i\

DEN

[\'---I---+---fV
ADDRESS

AD1S-ADO

x

DATA OUT

I

FLOAT

WR
WRITE
CYCLE

~----~-+----~-+-----yi/

DEN

DTIA

-

-

--I

_J

1

DEN IS ENABLED AFTER THE 8088 HAS FLOATED THE MULTIPLEXED BUS

2

DEN ENABLES THE TRANSCEIVERS EARLY IN THE CYCLE, BUT DTIR GUARANTEES
THE TRANSCEIVERS ARE IN TRANSMIT RATHER THAN RECEIVE MODE AND WILL
NOT DRIVE AGAINST THE CPU.

Diagram 2C4. Bus Transceiver Control

ADDR

---<'-_______________
I

DTIR

.J

'-------------01l1li

DATA

~~f.:ES~~~V:~~ -----"0(

~------------------~WR

~------------'
~
DRIVE _ _ _ _ _
~BOTH DEVICES
THE 8US
8US CONTENTION

Figure 2C4. Devices with Output Enables on the System Bus

_

Diagram 2C5.

A-II

_---------

AP-67

CPU LOCAL
BUS

MEMORYIIO
LOCAL BUS

SYSTEM
BUS

Figure 2C5. Fully Bullered System

I\r-==--,/

MEMORY/I/O DEVICES

828817

An alternate technique applicable to devices with and
without output enables is shown in Figure 2C6d. RD
again controls the direction of the transceiver but it is
not enabled until a command and chip select are active.
The possibility for bus contention stl II exists but is
reduced to variations in output enable vs. direction
change time for the transceiver. Full access time from
chip select is now available, but data will not be valid
prior to write and will only be held valid after write by the
delay to disable the transceiver.

Figura 2C8a. Controlling System Transceivers with DEN and DT/R

C!--------~----------------------~

WR------------------------,
elI----------~t_------__,

RD--------~~~------~~--t_.

SYSTEM
DATA
8US

MEMORY/110
DEVICE
SYSTEM DATA 8US

Figura 2C8b. Bullarlng Davlcos with

828617

OEiiiii

MEMORY/I/O
DEVICE

Figure 2C6d. Bullerlng Devices without
or Separate Inpul/Output

MEMORYIifO
DEVICE

828117

Figura 2C8c. Bullering Dovlces without OEiiiii and with Common
or Separate Inpul/Output

OEiRD and with Common

One last technique is given for devices with separate inputs and outputs (Fig. 2C6e). Separate bus receivers and
drivers are provided rather than a single transceiver. The
receiver is always enabled while the bus driver is controlled by RD and chip select. The only possibility for
bus contention in this system occurs as multiple
devices on each line of the local read bus are enabled
and disabled during chip selection changes.
Throughout this note, the multiplexed bus will be considered the local CPU bus and the demultlplexed address and buffered data bus will be the system bus. For
additional Information on bus contention and the
system problems associated with it, refer to Appendix 1.

A-12

AP-67
strapping options) extend the configuration options
beyond a pure CPU interface to the multlmaster system
bus for access to shared resources to Include concurrent support of a local CPU bus for private resources.
For specific configurations and additional Information
on the 8289, refer to application note AP-51.

~-.------------------------,

IIII---qi.-'

WR--------f--------------,
74S04
OR
SYSTEM
DATA
BUS

3. 8088 SYSTEM DETAILS

74$240

_-------+-1

LOCAL WRITE BUS

LOCAL READ BUS

o

3A. Operating Mode.

Possibly the most unique feature of the 8086 Is the ability to select the base machine configuration most suited
to the application. The MN/MX input to the 8086 Is a
strapping option which allows the designer to select
between two functional definitions of a subset of the
8086 outputs.

MEMORYniO
DEVICE

74$240

Figura 2C6e. Bullaring Davicas without OEiRD and with Saparata
Input/Output

MINIMUM MODE

2D. Multiprocessor Environment
The 8086 architecture supports multiprocessor systems
based on the concept of a shared system bus (Fig. 2D1).
All CPU's in the system communicate with each other
and share resources via the system bus. The bus may be
either the Intel Multibus™ system bus or an extension
of the system bus defined in the previous section. The
major addition required to the demultlplexed system
bus is arbitration logic to controi access to the system
bus. As each CPU asynchronously requests access to
the shared bus, the arbitration logic resolves priorities
and grants bus access to the highest priority CPU. Hav·
ing gained access to the bus, the CPU completes its
transfer and wlli either relinquish the bus or wait to be
for{:ed to relinquish the bus. For a discussion on
Multibus™ arbitration techniques, refer to AP-28A, Intel
Multibus™ Interfacing.

SHARED
PERIPHERALS

Figura 2D1. 8086 Family Muillprocessor Systam

To support a muitimaster interface to the Multibus
system bus for the 8086 family, the 8289 bus arbiter is
included as part of the family. The 8289 is compatible
with the 8086's iocal bus and in conjunction with the
8288 bus controller, implements the Multibus protocol
for bus arbitration. The 8289 provides a variety of arbitration and prioritization techniques to allow optimization
of bus availability, throughput and utilization of shared
resources. Additional features (implemented through

The minimum mode 8086 (Fig. 3A1) is optimized for
small to medium (one or two boards), single CPU
systems. Its system architecture Is directed at satiSfyIng the requirements of the lower to middle segment of
high performance 16-bit applications. The CPU maintains the full megabyte memory space, 64K byte I/O
space and 16-bit data path. The CPU directly provides all
bus control (DT/R, DEN, ALE, M/io), commands
(RD,WR,INTA) and a simple CPU preemption mechanism (HOLD, HLDA) compatible with existing DMA
controllers.
MAXIMUM MODE
The maximum mode (Fig. 3A2) extends the system architecture to support multiprocessor configurations,
and local instruction set extension processors (coprocessors). Through addition of the 8288 bipolar bus
controller, the 8086 outputs assigned to bus control and
commands in the minimum mode are redefined to allow
these extenSions and enhance general system performance. Specifically, (1) two prioritized levels of processor
preemption (RQ/GTO, RQ/clff) allow multiple processors to reside on the 8086's local bus and share its interface to the system bus, (2) Queue status (QSO,QS1) is
available to allow external devices like ICE™-86 or
special instruction set extension co-processors to track
the CPU instruction execution, (3) access control to
shared resources in multiprocessor· systems Is supported by a hardware bus lock mechanism and (4)
system command and configuration options are expanded via an ciliary devices like the 8288 bus controller
and 8289 bus arbiter.
The queue status indicates what Information is being
removed from the internal queue and when the queue Is
being reset due to a transfer of control (Table 3A1). By
monitoring the SO,51,52 status lines for Instructions
entering the 8086 (1,0,0 indicates code access while AO
and BHE indicate word or byte) and QSO, QS1 for instructions leaving the 8086's internal queue, it is possible to track the instruction execution. Since Instructions are executed from the 8086's internal queue, the
queue status is presented each CPU clock cycle and is
not related to the bus cycle activity. This mechanism (1)
allows a co-processor to detect execution of an

A-13

AP-67
ESCAPE instructiOn which directs the co-processor to
perform a specific task and (2) allows ICE-B6 to trap execution ofa specific memory location. An example of a
circuit used by ICE is given in Figure 3A3. The first up
down counter tracks the depth of the. queue while the
second captures the queue depth on a match. The second counter decrements on further fetches from the
queue until the queue is flushed or the count goes to
zero indicating execution of the match address. The
first counter decrements on fetch from the queue
(OSO= 1) and increments on code fetches into the

Vee

~
T

queue. Note that a normal code fetch will transfer two
bytes into the queue so two clock increments are given
to the counter (T201 and T301) unless a single byte is
loaded over the upper half of the bus (AO-P is high).
Since the execution unit (EU) is not synchronized to the
bus interface unit (BIU), a fetch from the queue can occur simultaneously with a transfer into the queue. The
exclusive-or gate driving the. ENP input of the first
counter allows these simultaneous operations to cancel
each other and not modify the queue depth.

rD~
8284 CLOCK
GENERATOR
RES

MN/MX -4---Ycc
... ClK

MIlO

... READY

INTA

... RESET

RD
WR

ROY

t

GND

OTiR
DEN

}

COMM AND
BU S

----,
--~II

r-----.

II
II

8088 CPU
ALE
GND

,A

I

I I
I I

•

BHE

DE
8282
lATCH
20R 3

J
-rr----:1

ADo-AD15 rODR/DATA
A16- Ai9

I
I

STB

r

~

II

II
IL

T---'I
L--IOE
II

1 MEGABYTE

>

II ~

8286
TRANSCEIVER
(2)

I

~

v' ADDRESS BUS

16·BIT
DATA BUS

OPTIONAL
FOR INCREASED
DATA BUS DRIVE

Figure 3Al. Minimum Mode 8086
Vee

~
T

GND

rD~
8284
CLOCK
~NERATOR

RES

+

ClK

_

READY

S;

So
S;

RESET

52

52

,..

SO

-

ROY

t

ClK

MN/MX "-GND

_

8086
CPU

DEN

MRDCMWTC-

8288

AMWC-

BUS
CTRlR

IORCIOWC-

COMMAND
BUS

AIOWC-

r--- DTiR

NTAALE
r - 1.--_
_I
---1
lOCK -N.C.

STB
GND-If-t--J
ADD-AD

15
A1S- A19

A

r

ADDR/DATA

~

DE

't-"====J.~

8282
lATCH
(20R 3)

BHE-

1 MEGABYTE
ADDRESS BUS

r

L....._ _.....

~~

......... -

8286
TRANSCEIVER
(2)

Figure 3A2. "'axlmum

A-14

':odL:-e~8:::0~88::--"""

A'L-_ _..J~'\

vi

I~

HI-BIT

r DATA BUS

AP·67
TABLE 3A1. QUEUE STATUS

QS1

QSO

o(LOW)

0
1
0
1

0
1 (HIGH)
1

No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue

The queue status is valid during the CLK cycle after
which the queue operation is performed.

tion of the locked instruction) without intervention and
possible corruption of the data by another CPU. A
classic use of the mechanism is the 'TEST and SET
semaphore' during which a CPU must read from a
shared memory location and return data to the location
without allowing another CPU to reference the same
location between the TEST operation (read) and the SET
operation (write). In the 8086 this is accomplished with a
locked exchange instruction.
LOCK XCHG reg, MEMORY; reg Is any register
;MEMORY Is the address of the

To address the problem of controlling access to shared
resources, the maximum mode 8086 provides a hard·
ware LOCK output. The LOCK output Is activated
through the instruction stream by execution of the
LOCK prefix instruction. The LOCK output goes active
in the first CPU clock cycle following execution of the
prefix and remains active until the clock following the
completion of the instruction following the LOCK prefix.
To provide bus access control in multiprocessor
systems, the LOCK signal should be incorporated into
the system bus arbitration logic resident to the CPU.

;8~maphore

The activity of the LOCK output is shown in Diagram
3A1. Another Interesting use of the LOCK for multiprocessor systems is a locked block move which allows high
speed message transfer from one CPU's message buffer to another.
During the locked instruction, a request for processor
preemption (RQ/GT) is recorded but not acknowledged
u.ntil completion of the locked instruction. The LOCK
has no direct affect on interrupts. As an e~.Eie, a
iocked HALT instruction will cause HOLD (or RQ/GT) requests to be ignored but will allow the CPU to exit the
HALT state on an interrupt. In general, prefix bytes are
considered extensions of the Instructions they precede.
Therefore, interrupts that occur during execution of a
prefix are not acknowledged (assuming interrupts are
enabled) until completion of the instruction following
the prefixes (except for instructions which allow servicIng interrupts during their execution, I.e., HALT, WAIT
and repeated string primitives). Note that multiple prefix
bytes may precede an instruction. As another example,
consider a 'string primitive' preceded by the repetition

During normal multiprocessor system operation, priority of the shared system bus is determined by the arbitration circuitry on a cycle by cycle basis. As each
CPU requires a transfer over the system bus, It requests
access to the bus via its resident bus arbitration logic.
When the CPU gains priority (determined by the system
bus arbitration scheme and any associated logic), It
takes control of the bus, performs its bus cycle and
either maintains bus control, voluntarily releases the
bus or Is forced off the bus by the loss of priority. The
lock mechanism prevents the CPU from losing bus control (either voluntarily or by force) and guarantees a CPU
the ability to execute multiple bus cycles (during execu-

.-------l:><>------'2'+CLK

============:jr=~!--------------t-=-=~~~----~9 ~AD748188
QCTO

MHBYTE AND 1 CLKA

-

MATCH CONDITIONS
CPU CLOCK

aso
~_T~

-

CPU QUEUE STATUS

:

6:J~~~~J: :~S~(CLOCK LOW TIME_Ol)

C ACCESS
OCTO
AO·P

- CODE ACCESS
- QUEUE MATCH
- SINGLE BYTE ON UPPER HALF OF THE BUS

OSl,

~::======1[:J~~~~1---------------------------------------------~-------

SllH

13

iIDi ______....:.13,
74$04

Figure 3A3. Example Circuit to Track the 8088 Queue

A-15

C ACCESS

AP·67
prefix (REP) which is interruptible after each execution
of the string primitive. This holds even if the REP prefix
is combined with the lOCK prefix and prevents interrupts from being locked out during a block move or
other repeated string operation. As long as the operation is not interrupted, lOCK remains active. Further information on the operation of an interrupted string
operation with multiple prefixes is presented in the section dealing with the 8086 interrupt structure.
Three additional status lines (SO, S1, S2) are defined to
provide communications with the 8288 and 8289. The
status lines tell the 8288 when to initiate a bus cycle,
what type of command to issue and when to terminate
the bus cycle. The 8288 samples the status lines at the
beginning of each CPU clock (ClK). To initiate a bus cycle, the CPU drives the status lines from the passive
state (SO, S1, S2 1) to one of seven possible command
codes (Table 3A2). This occurs on the rising edge of the
clock during T4 of the previous bus cycle or a TI (idle cycle, no current bus activity). The 8288 detects the status
change by sampling the status lines on the high to low
transition of each clock cycle. The 8288 starts a bus cycle by generating ALE and appropriate buffer direction
control in the clock cycle immediately following detection of the status change (T1). The bus transceivers and
the selected command are enabled in the next clock
cycle (T2) (or T3 for normal write commands). When the
status returns to the passive state, the 8288 will terminate the command as shown in Diagram 3A2. Since
the CPU will not return the status to the passive state
until the 'ready' indication is received, the 8288 will
maintain active command and bus control for any
number of walt cycles. The status lines may also be
used by other processors on the 8086's local bus to
monitor bus activity and control the 8288 If they gain
control of the local bus.

=

TABLE 3A2. STATUS LINE DECODES

S2

SI

So

o (lOW)

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1 (HIGH)
1
1
1

Interrupt Acknowledge
Read 1/0 Port
Write 1/0 Port
Halt
Code Access
Read Memory
Write Memory
Passive

The 8288 provides the bus control (DEN, DT/R, ALE) and
commands (INTA, MRDC, 10RC, MWTC, AMWC, iOWC,
AIOWC) removed from the CPU. The command structure
has separate read and write commands for memory and
1/0 to provide compatibility with the Multibus command
structure.
The advanced write commands are enabled one clock
period earlier than the normal write to accommodate the
wider write pulse widths often required by peripherals
and static RAMs. The normal write provides data setup
prior to write to accommodate dynamic RAM memories
and I/O devices which strobe data on the leading edge of
write. The advanced write commands do not guarantee
that data is valid prior to the leading edge of the command. The DEN signal in the maximum mode is inverted
from the minimum mode to extend transceiver control
by allowing logical conjunction of DEN with other
signals. While not appearing to be a significant benefit
In the basic maximum mode configuration, introduction
of interrupt control and various system configurations
will demonstrate the usefulness of quallfylng'DEN.
Diagram 3A3 compares the timing of the minimum and
maximum mode bus transfer commands. Although the

CLK

~--------~~

QSO

I - - - -__________________ ,~

LOCK

LOCKED INSTRUCTION

NOP BYTE
FROM THE
QUEUE
(LOCKED NOP)

LOCK
PREFIX
BYTE FROM
QUEUE,
1

QUEUE STATUS INDICATES FIRST BYTE OF OPCODE FROM THE QUEUE.

2

THE LOCK OUTPUT WILL GO INACTIVE BETWEEN SEPARATE LOCKED INSTRUCTIONS.

3

TWO CLOCKS ARE REQUIRED FOR DECODE OF THE LOCK PREFIX AND
ACTIVATION OF THE i:OCK SIGNAL.

4

SINCE QUEUE STATUS REFLECTS THE QUEUE OPERATION IN THE PREVIOUS CLOCK
CYCLE, THE i:OCK OUTPUT ACTUALLY GOES ACTIVE COINCIDENT WITH THE START
OF THE NEXT INSTRUCTION AND REMAINS ACTIVE FOR ONE CLOCK CYCLE
FOLLOWING THE INSTRUCTION.

5

IF THE INSTRUCTION FOLLOWING THE LOCK PREFIX IS NOT IN THE QUEUE, THE
L6CR OUTPUTSTI'LL GOES ACTIVE AS SHOWN WHILE THE INSTRUCTION IS BEING
FETCHED.

8

THE BIU WILL STILL PERFORM INSTRUCTION FETCH CYCLES DURING EXECUTION
OF A LOCKED INSTRUCTION. THE L6CR MERELY LOCKS THE BUS TO THIS CPU FOR
WHATEVER BUS CYCLES THE CPU PERFORMS DURING THE LOCKED INSTRUCTION.

Diagram 3A 1. 8088 Lock Activity

A-16

AP-67
maximum mode configuration is designed for multiprocessor environments, large single CPU designs
(either Multibus systems or greater than two PC boards)
should also.use the maximum mode. Since the 8288 is a
bipolar dedicated controller device, its output drive for
the commands (32 mAl and tolerances on AC characteristics (timing parameters and worse case delays) provide better large system performance than the minimum
mode 8086.

In addition to assuming the functions removed from the
CPU, the 8288 provides additional strapping options and
controls to support multiprocessor configurations and
peripheral devices on the CPU local bus. These capabilities allow assigning resources (memory or 1/0) as
shared (available on the Multibus system bus) or private
(accessible only by this CPU) to reduce contention for
access to the. Multibus system bus and improve multiCPU system performance. Specific configuration possibilities are discussed in AP-51.

CLK

GOES INACTIVE IN THE STATE
JUST PRIOR TO T 4

ALE

READY
READY

o

WAIT

Diagram 3A2. Status Line Activation and Termination

CLK (8284 OUTPUn

MN
MODE
8086

TCVCTX-

35 os

MX
MODE
8086
WITH
8288

TCLMH

110 ns

35

TCLMH_ 3 5 _

~ORAIOWC --------~------------4-,1

TCLML

Diagram 3A3. 8086 Minimum and Maximum Mode Command Timing

A-I7

35 -

TCLMH

AP-67
3B. Clock Generation
The 8086 requires a clock signal with fast rise and fall
times (10 ns max) between low and high voltages of
- 0.5 to + 0.6 low and 3.9 to VCC + 1.0 high. The max·
imum clock frequency of the 8086 is 5 MHz and 8 MHz
for the 8086·2. Since the design of the 8086 incorporates
dynamic cells, a minimum frequency of 2 MHz is reo
quired to retain the state of the machine. Due to the
minimum frequency requirement, single stepping or
cycling of the CPU may not be accomplished by dis·
abling the clock. The timing and voltage requirements of
the CPU clock are shown in Figure 3B1. In general, for
frequencies below the maximum, the CPU clock need
not satisfy the frequency dependent pulse width limi·
tations stated in the 8086 data sheet. The values
specified only reflect the minimum values which must
be satisfied and are stated in terms of the maximum
clock frequency. As the clock frequency approaches the
maximum frequency of the CPU, the clock must con·
form to a 33% duty cycle to satisfy the CPU minimum
clock low and high time specifications.

10n8 MAX

1.5

.6t---~~~~~~~~~--------1i---

-.~

1_ _- - - - -

:gg~: :~~ -----.,

Figure 381. 8086 Clock

An optimum 33% duty cycle clock with the required
voltage levels and transition times can be obtai ned with
the 8284 clock generator (Fig. 3B2). Either an external
frequency source or a series resonant crystal may drive
the 8284. The selected source must oscillate at 3X the
desired CPU frequency. To select the crystal Inputs of
the 8284 as the frequency source for clock generation,
the Fie Input to the 8284 must be strapped to ground.
The strapping option allows selecting either the crystal
or the external frequency Input as the source for clock
generation. Although the 8284 provides an Input for a
tank circuit to accommodate overtone mode crystals,
fundamental mode crystals are recommended for more
accurate and stable frequency generation. When selec·
ting a crystal for use with the 8284, the series resistance
should be as low as possible. Since other circuit com·
ponents will tend to shift the operating frequency from
resonance, the operating impedance will typically be
higher than the specified series resistance. If the at·
tenuatlon of the oscillator's feedback circuit reduces
the loop gain to less than one, the oscillator will fail.
Since the oscillator delays in the 8284 appear as induc·
tive elements to the crystal, causing it to run at a fre·
quency below that of the pure series resonance, a
capaCitor should be placed in series with the crystal and
the X2 input of the 8284. This capaCitor serves to cancel
this Inductive element. The value of the capaCitor (Cl)

must not cause the impedance of the feedback circuit to
reduce the loop gain below one. The impedance of the
capaCitor is a function of the operating frequency and
can be determined from the following equation:
XCl= 1/2n'F'Cl

17
XTAl

CJ

Y

osc

X,

12
8088

8284
18
Cl

13

19 ClK

ClK
X2

Fft

Figure 382. 8284 Clock Generalor

It is recommended that the crystal series resistance
plus XCl be kept less than 1K ohms. This capaCitor also
serves to debias the crystal and prevent a DC voltage
bias from straining and perhaps damaging the crystalline structure. As the crystal frequency increases, the
amount of capaCitance should be decreased. For example, a 12 MHz crystal may require Cl '" 24 pF while 22
MHz may require Cl'" 8 pF. If very close correlation
with the pure series resonance is not necessary, a
nominal CL value of 12-15 pF may be used with a 15 MHz
crystal (5 MHz 8086 operation). Board layout and component variances will affect the actual amount of inductance and therefore the series capacitance required to
cancel it out (this Is especially true for wire-wrapped
layouts).
Two of the many vendors which supplycrystals for Intel
microprocessors are listed in Table 3B1 along with a list
of crystal part numbers for various frequencies which
may be of interest. For additional information on speci·
fying crystals for Intel components refer to application
note AP-35.
TABLE 3Bl. CRYSTAL VENDORS

f

Parallel!
Series

Crystek(l)
Corp.

CTS Knlght,(2)
Inc.

15.0 MHz
18.432
24.0 MHz

S

S

CY15A
CY19B'
CY24A

MP150
MP184'
MP240

S

'Inlel also supplies a crystal numbered 8801 for this application.
Nol••: 1. Address: 1000 Crystal Drive, Fort Meyers, Florida 33901
2. Address: 400 Reimann Ave., Sandwich, illinois

If a high accuracy frequency source, externally variable
frequency source or a common source for driving mUltiple 8284's is desired, the External Frequency Input
(EFI) of the 8284 can be selected by strapping the FICinput to 5 volts through ",1 K ohms (Fig. 3B3). The external
frequency source should be TTL compatible, have a
50% duty cycle and oscillate at three times the desired
CPU operating frequency. The maximum EFI frequency
the 8284 can accept is slightly above 24 MHz with
minimum clock low and high times of 13 ns. Although

A-18

AP-67
no minimum EFI frequency is specified, it should not
violate the CPU minimum clock rate. If a common fre·
quency source is used to drive multiple 8284's
distributed throughout the system, each 8284 should be
driven by its own line from the source. To minimize
noise in the system, each line should be a twisted pair
driven by a buffer like the 74LS04 with the ground of the
twisted pair connecting the grounds of the source and
receiver. To minimize clock skew, the lines to all 8284's
should be of equal length. A simple technique for generating a master frequency source for additional 8284's
is shown in Figure 384. One 8284 with a crystal is used
to generate the desired frequency. The oscillator output
of the 8284 (OSC) equals the crystal frequency and is
used to drive the external frequency to all other 8284's
in the system.

+5

x,
leo
EXTERNAL
Fie
FREQUENCY---""'-! EFI
SOURCE

18
ClK i-=---~ ClK
8284

8088

Figure 3B3. 8284 with External Frequency Source
14

EFI

ClK

8284

Fie

~---'-'-IEFI

ClK

8284

Fie

EFI

ClK

8284

13

Fie

'K

+5

The oscillator output is inverted from the oscillator
signal used to drive the CPU clock generator circuit.
Therefore, the oscillator output of one 8284 should not
drive the EFI input of a second 8284 If both are driving
clock inputs of separate CPU's that are to be syn, chronized. The variation on EFI to' CLK delay over a
range of 8284's may approach 35 to 45 ns. If, however, all
8284's are of the same package type, have the same
relative supply voltage and operate in the same temperature environment, the variation will be reduced to
between 15 and 25 ns.
There are three frequency outputs from the 8284, the
oscillator (OSC) mentioned above, the system clock
(CLK) which drives the CPU, and a peripheral clock
(PCLK) that runs at one half the CPU clock frequency.
The oscillator output is only driven by the crystal and Is
not affected by the FIe strapping option. If a crystal is
not connected to the 8284 when the external frequency
input is used, the oscillator output Is Indetermlnate_ The
CPU clock is derived from the selected frequency
source by an internal divide by three counter. The
counter generates the 33% duty cycle clock which is optimum for the CPU at maximum frequency. The
peripheral clock has a 50% duty cycle and is derived
from the CPU clock. Diagram 380 shows the relationship of CLK to OSC and PCLK to CLK. The maximum
skew is 20 ns between OSC and CLK, and 22 ns between
CLK and PCLK.
Since the state of the 8284 divide by three counter is Indeterminate at system initialization (power on), an external sync to the counter (CSYNC) is provided to ailow
synchronization of the CPU clock to an external event.
When CSYNC is brought high, the CLK and PCLK outputs are forced high. When CSYNC returns low, the next
positive clock from the frequency source starts clock
generation. CSYNC must be active for a minimum of two
periods of the frequency source. If CSYNC is asynchronous to the frequency source, the circuit in Figure 385
should be used for synchronization. The two latches
minimize the probability of a meta-stable state in the
latch driving CSYNC. The latches are clocked with the
inverse of the frequency source to guarantee the 8284
setup and hold time of CSYNCto the frequency source
(Dlag. 381). If a single 8284 is to be synchronized to an
external event and an external frequency source Is not
used, the osciilator output of the 8284 may be used to

Figure 384. External Frequency lor Multiple 8284s

OSC

ClK

PClK

Diagrem 380. OSC - ClK and ClK - PClK Relationships

A-19

AP-67
synchronize CSYNC (Fig. 386). Since the oscillator out·
put Is inverted from the internal oscillator signal, the In·
verter in the previous example Is not required. If multiple
8284's are to be synchronized, an external frequency
source must drive all 8284's and a single CSYNC synchronization circuit must drive the CSYNC Input of all
8284's (Fig. 3B7). Since activation of CSYNC may cause
violation of CPU minimum clock low time, it should only
be enabled during reset or CPU clock high. CSYNC must
also be disabled a minimum of four CPU clocks before
the end of reset to guarantee proper CPU reset.

,.
17 X1

C

Y

,. '" ....
13 FiC

SYNC-----+---j

+5
lK

EXTERNAL
SYNC-----I
CONDITION
EXTERNAL
FREQUENCY

L -_ _ _ _ _ _ _ _ _ _ _ _ TO
EFI

INPUT

Figure 3BS. Synchronizing CSYNC with EFI

J

I

-+I

Due to the fast transitions and high drive (5 rnA) of the
8284 CLK output, it may be necessary to put a 10 to 100
ohm resistor in series with the clock line to eliminate
ringing (reSistor value depending on the amount of drive
required). If multiple sources of CLK are needed with
minimum skew, CLK can be buffered by a high drive
device (74S241) with outputs tied to 5 volts through 100
ohms to guarantee VOH 3.9 min (8086 minimum clock
input high voltage) (Fig. 3B8). A single 8284 should not
be used to generate the CLK for multiple CPU's that do
not share a common local (multiplexed) bus since the
8284 synchronizes ready to the CPU and can only accommodate ready for a single CPU. If multiple CPU's
share a local bus, they should be driven with the same
clock to optimize transfer of bus control. Under these
circumstances, only one CPU will be using the bus for a
particular bus cycle which allows sharing a common
READY signal (Fig. 3B9).

=

EFI

CIYNC

Fillure 3B7. Synchronizing Multiple 82848

TO
CSYNC
INPUT

II--TYHEH
·MAX tS SPEC'ED TO GUARANTEE MAX 8088 CLOCK FREQUENCY

Diagram 3Bl. CSYNC Setup and Hold to EFI

+5
10011
CLK

OSC 12

+5

C

8284

Y

18
13
0:-

SYNC

1

10011

X.

Fie

+5

CSYNC eLK 8

10011

Figure 3B8. EFI .rom 8284 Oscillator

Figure 3B8. Bull.rlng the 8284 ClK Output

A-20

AP-67

MULTIPLEXED BUS

Figur. 3B9. 8086 and Co·Processor on the Local Bus Share a
Common 8284

3C_ Reset
The 8086 requires a high active reset with minimum
pulse wi'~th of four CPU clocks except after power on
which requires a 50 ,.,s reset pulse. Since the CPU internally synchronizes reset with the clock, the reset is internally active for up to one clock period after the external reset. Non-Maskable Interrupts (NMI) or hold requests on RQ/GT which occur during the internal reset,
are not acknowledged. A minimum mode hold request
or maximum mode RQ pulses active immediately after
the internal reset will be honored before the first instruction fetch.

guarantee the inactive state of these lines in systems
where leakage currents or bus capacitance may cause
the voltage levels to settle below the minimum high
voltage of devices in the system. In maximum mode
systems, the 8288 contains internal pull-ups on the
SO-52 inputs to maintain the inactive state for these
lines when the CPU floats the bus. The high state of the
status lines during reset causes the 8288 to treat the
reset sequence as a passive state. The condition of the
8288 outputs for the passive state are shown in Table
3C2. If the reset occurs during a bus cycle, the return of
the status lines to the passive state will terminate the
bus cycle and return the command lines to the inactive
state_ Note that the 8288 does not three-state the command outputs based on the passive state of the status
lines. If the designer needs to three-state the CPU off
the bus during reset in a single CPU system, the reset
signal should also be connected to the 8288's AEN input
and the output enable of the address latches (Fig. 3C2).
This forces the command and address bus interface to
three-state while the inactive state of DEN from the 8288
three-states the transceivers on the data bus.
Table 3C1. 8086 Bus During Resat

From reset, the 8086 will condition the bus as shown in
Table 3C1. The multiplexed bus will three-state upon
detection of reset by the CPU. Other signals which
three-state will be driven to the inactive state for one
clock low interval prior to entering three-state (Fig_ 3C1)_
In the minimum mode, ALE and HLDA are driven inactive and are not three-stated. In the maximum mode
RQ/GT lines are held inactive and the queue status in:
dicates no activity. The queue status will not indicate a
reset of the queue so any user defined external circuits
monitoring the queue should also be reset by the
system reset. 22K ohm pull-up resistors should be connected to the CPU command and bus control lines to

Signals

Condition

AD 15.(J
A 19-1sfS6-3
BHE/5 7
52J(M/iQ)
511(DT/R)
SO/DEN
LOCKlWR
RD
INTA
ALE
HLDA
RQ/GTO
RQ/GT1
QSO
QS1

Three-State
Three-State
Three-State
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
Driven to "1" then three-state
0
0
1
1
0
0

CLOCK

RESET INPUT

INTERNAL RESET

BUS

t

LFLOATBUS

~ DRIVE OUTPUT TO INACTIVE STATE

Flgur. 3C1. 8086 Bus Conditioning on Res.t

A-21

AP-67
TABLE 3C2. 8288 OUTPUTS. DURING PASSIVE MODE

o

ALE
DEN

o

DTiR

1

MCE/PDEN
COMMANDS

0/1
1

, - - - - - - - - - _ - 1 AEN
8288
·DEN

OE
8284
RESET

8282

1---4--1 RESET
8086

Figure 3C2. Re,el Disable lor Max Mode 8086 Bus Inlerface

For multiple processor systems using arbitration of a
multimaster bus, the system reset should be connected
to the INIT input of the 8289 bus arbiter in addition to
the 8284 reset input (Fig. 3C3). The low active INIT Input
forces all 8289 outputs to their inactive state. The inac·
tive state of the 8289 AEiii output will force the 8288 to
three·state the command outputs and the address
latches to three-state the address bus interface. DEN inactive from the 8288 will three-state the data bus interface. For the multimaster CPU configuration, the reset
should be common to all CPU's (8289's and 8284's) and
satisfy the maximum of either the CPU reset requirements or 3 TBLBL (3 8289 bus clock times)+ 3
TCLCL (3 8086 clock cycle times) to satisfy 8289 reset
requirements.

If the 8288 command outputs are three-stated during
reset, the command lines should be pulled up to Vee
through 2.2K ohm reSistors.
The reset signal to the 8086 can be generated by the
8284. The 8284 has a schmitt trigger input (RES) for
generating reset from a low active external reset. The
hysteresis specified In the 8284 data sheet implies that
at least .25 volts will separate the 0 and 1 Switching
point of the 8284 reset input. Inputs without hysteresis
will switch from low to high and high to low at approximately the same voltage threshold. The Inputs are
guaranteed to switch at specified low and high voltages
(VIL and VIH) but the actual switching point is anywhere
in-between. Since VIL min is specified at .8 volts, the
hysteresis guarantees that the reset will be active until
the input reaches at least 1.05 volts. A reset will not be
recognized until the input drops at least .25 volts below
the reset inputs VIH of 2.6 volts.
To guarantee reset from power up, the reset input must
remain below 1.05 volts for 50 microseconds after Vee
has reached the minimum supply voltage of 4.5 volts.
The hysteresis allows the reset input to be driven by a
simple RC circuit as shown in Figure 3C4. The
calculated RC value does not inClude time for the power
supply to reach 4.5 volts or the charge accumulated duro
Ing this interval. Without the hysteresis, the reset out·
put might oscillate as the input voltage passes through
the switching voltage of the input. The calculated RC
value provides the minimum required reset period of 50
microseconds for 8284's that switch at the 1.05 volt
level and a reset period of approximately 162 microseconds for 8284's that switch at the 2.6 volt level. If
tighter tolerance between the minimum and maximum
reset times is necessary, the reset circuit shown in
Figure 3C5 might be used rather than the simple RC cir·
cuit. This circuit provides a constant current source and
a linear charge rate on the capacitor rather than the inverse exponential charge rate of the RC circuit. The
maximum reset period for this implementation is 124
microseconds.

+V

r _ _ _ _ _ _ _ _ _- - - - - - ( S y S T E M )
RESET

11

RESET IN

RESET
V

=

= 50 ~s.c

Ve
RC

= 1.05
= 188 x 10- 8

= 4.5

I!R

5
RESET

8086

I

.8

MINIMUM RESET ACTIVE TIME

I.-

Figure 3C3. Resel Disable 01 lor Max Mode 8086 Bus Inlerface In
Multi CPU Syslem

MAXIMUM RESET ACTIVE TIME

Figure 3C4. 8284 Re.el Circuit

A-22

Jl_.iit)

Ve!l)
I
V

8284

I

8284

RES

AP-67

Vee

3D. Reedy Implementation and Timing

R, R. -

As discussed previously, the ready signal Is used in the
system to accommodate memory and 110 devices that
cannot transfer information at the maximum CPU bus
bandwidth. Ready is also used In multiprocessor
systems to force the CPU to wait for access to the
system bus or Multibus system bus. To insert a wait
state in the bus cycle, the READY signal to the CPU
must be inactive (low) by the end of T2. To avoid inser·
tion of a walt state, READY must be active (high) within
a specified setup time prior to the positive transition
during T3. Depending on the size and characteristics of
the system, ready Implementation may take one of two
approaches.

DETERMINES CURRENT TO CHARGE C
VALUE NOT CRITICAL .,0K

Ie == CHARGE CURRENT. YbdD,

~ D2 - T,)

RESET
IF All SEMICONDUCTORS ARE SILICON, Ics

'W

·k----SVee-.6

The classical ready implementation is to have the
system 'normally not ready.' When the selected device
receives the command (RDIWRlINTA) and has had suffi·
cient time to complete the command, It activates
READY to the CPU, allowing the CPU to terminate the
bus cycle. This implementation is characteristic of large
multiprocessor, Multlbus systems or systems where
propagation delays, bus access delays and device char·
acteristics inherently slow down the system. For max·
imum system performance, devices that can run with no
wait states must return 'READY' within the previously
described limit. Failure to respond In time will only
result in the insertion of one or more walt cycles.

T

Figure 3CS. Constant Current Power·On Reset Circuit

The 8284 synchronizes the reset input with the CPU
clock to generate the RESET signal to the CPU (Fig.
3C6). The output is also available as a general reset to
the entire system. The reset has no effect on any clock
circuits in the 8284.

17

C

19

8284

Y

18

+5

13

SYSTEM
RESET

ClK 8

X,

X.
Fie

An alternate technique is to have the system 'normally
ready.' All devices are assumed to operate at the max·
imum CPU bus bandwidth. Devices that do not meet the
requirement must disable READY by the end of T2 to
guarantee the insertion of wait cycles. This Implementation is typically applied to small single CPU systems
and reduces the logic required to control the ready
signal. Since the failure of a device requiring walt states
to disable READY by the end of T2 will result in prema·
ture termination of the bus cycle, the system timing
must be carefully analyzed when using this approach.

ClK

8086
RESET

10

21

RESET

-::11

The 8086 has two different timing requirements on
READY depending on the system implementation. For a
'normally ready' system to Insert a walt state, the
READY must be disabled within 8 ns (TRYLCL) after the
end of T2 (start of T3) (Dlag. 301). To guarantee proper

m

I
Figure 3C6. 8088 Reset and System Reset

CLOCK

8086 READY

READY INACTIVE 8 no M"'............

30 ns
\ . - 119 ns TO OUARANTEE THE
NEXT CYCLE IS To

Diagram 3D1. Normally Ready System Inserting a Walt State

A-23

AP-67
operation of the 8086, the READY input must not change
from ready to not ready during the clock low time of T3.
For a 'normally not ready' system to avoid walt states,
READY must be active within 119 ns (TRYHCH) of the

positive clock transition during T3 (Diag. 302). For both
cases, READY must satisfy a hold time of 30 ns
(TCHRYX) from the T3 or TW positive clock transition.

CLOCK

8088 READY

Diagram 302. Normally Not Ready System Avoiding a Wail State

To generate a stable READY signal which satisfies the
previous setup and hold times, the 8284 provides two
separate system ready inputs (RDY1, RDY2) and a single
synchronized ready output (READY) for the CPU. The
ROY inputs are qualified with separate access enables
(AEN1,AEN2, low active) to allow selecting one of the
two ready signals (Fig. 301). The gated signals are
logically OR'ed and sampled at the beginning of each
ClK cycle to generate READY to the CPU (Diag. 303).
The sampled READY Signal is valid within 8 ns (TRYlCl)
after ClK to satisfy the CPU timing requirements on
'not ready' and ready. Since READY cannot change until
the next ClK, the hold time requirements are also satis·
fied. The system ready inputs to the 8284 (RDY1,RDY2)
must be valid 35 ns (TRIVCl) before T3 and AEN must be
valid 60 ns before T3. For a system using only one ROY
input, the associated AEN is tied to ground while the
other AEN is connected to 5 volts through ",1 K ohms
(Fig. 3D2a). If the system generates a low active ready
Signal, it can be connected to the 8284 AEN input if the
additional setup time required by the 8284 AEN input is
satisfied. In this case, the associated ROY input would
be tied high (Fig. 3D2b).

17

X,

ClK

C]

RESET 10

Y

18

+5

13

X.
FtC

READY

18
21

22

CLK
RESET
READY

8088

8284

-=
11
3

~

RES
AEN1
RDY1
7 AEN2
6 RDY2

Figura 301. Ready Inpuls to Ihe 8284 and OulpullO Ihe 8086

---~o--

CLOCK

8284 READY OUT
(TO 8088)

NOTE: THE 8284 DATA SHEET SPECIFIES READY OUT DELAY (TRYLCL) AS -8 ••
'BEFORE' THE END OF T. WHICH IMPLIES THE TIMING SHOWN.

Diagram 303. 8284 wllh 8086 Ready Timing

A-24

T.,rrw

AP-67
memory. If the access to non-existent memory fails to
enable READY, the system will be caught in an indefinite wait.
SYSTEM

RDY1

READY

AOO
RDY2

+5

RO ... TO 1214

Figure 3D2a. Using RDY1/RDY2 to Generate Ready

Figure 3D3. Single Walt State Generetor
3 AEIIl
4 RDY1
7 Am
8
RDY2

8284

3E_ Interrupt Structure

1K

+5
Figure 3D2b. Using AEN1/AEN2 to Generate Ready

The majority of memory and peripheral devices which
fail to operate at the maximum CPU frequency typically
do not require more than one wait state. The circuit
given in Figure 303 Is an example of a simple wait state
generator. The system ready line Is driven low whenever
a device requiring one walt state is selected. The flip
flop is cleared by ALE, enabling ROY to the 8284. If no
wait states are required, the flip flop does not change. If
the system ready is driven low, the flip flop toggles on
the low to high clock transition of T2 to force one wait
state. The next low to high clock transition toggles the
flip flop again to Indicate ready and allow completion of
the bus cycle. Further changes in the state of the flip
flop will not affect the bus cycle. The circuit allows
approximately 100 ns for chip select decode and conditioning of the system ready (Dlag. 304).
If the system is 'normally not ready,' the programmer
should not assign executable code to the last six bytes
of physical memory. Since the 8086 prefetches instructions, the CPU may attempt to access non-existent
memory when executing code at the end of physical

The 8086 interrupt structure is based on a table of interrupt vectors stored in memory locations OH through
003FFH. Each vector consists of two bytes for the instruction poi nter and two bytes for the code segment.
These two values combine to form the address of the interrupt service routine. This allows the table to contain
up to 256 interrupt vectors which specify the starting address of the service routines anywhere In the one megabyte address space of the 8086. If fewer than 256 different Interrupts are defined in the system, the user need
only allocate enough memory for the interrupt vector
table to provide the vectors for the defined Interrupts.
During Initial system debug, however, it may be desirable to assign all undefined interrupt types to a trap
routine to detect erroneous interrupts.
Each vector is associated with an interrupt type number
which pOints to the vector's location in the interrupt vector table. The interrupt type number multiplied by four
gives the displacement of the first byte of the associated interrupt vector from the beginning of the table. As
an example, Interrupt type number 5 pOints to the sixth
entry In the Interrupt vector table. The contents of this
entry in the table points to the interrupt service routine
for type 5 (Fig. 3E1). This structure allows the user to
specify the memory address of each service routine by
placing the address (Instruction pointer and code segment values) In the table location provided for that type
interrupt.

Diagram 3D4.

A-25

AP-67
TYPE 1 - SINGLE STEP

INTERRUPT TYPE

r ~U~I!"I

.----.,.,..--,-=;::-::;

This interrupt type occurs one instruction after the TF
(Trap Flag) is set In the flag register. It is used to allow
software single stepping through a sequence of code.
Single stepping Is initiated by copying the flags onto the
stack, setting the TF bit on the stack and popping the
flags. The Interrupt routine should be the single step
routine. The interrupt sequence saves the flags and program counter, then resets the TF flag to allow the single
step routine to execute normally. To return to the
routine under test, an interrupt return restores the IP,
CS and flags with TF set. This allows the execution of
the next instruction in the program under test before
trapping back to the single step routine. Single Step Is
not masked by the IF (Interrupt Flag) bit in the flag
register.

•

INTERRUPT
VECTOR
TABLE

TYPE 5 INTERRUPT
SERVICE ROUTINE

TYPE 2 - NMI (Non-Maskable Interrupt)
This is the highest priority hardware interrupt and is
non-maskable. The input is edge triggered but is synchronized with the CPU clock and must be active for two
clock cycles to guarantee recognition. The interrupt
signal may be removed prior to entry to the service
routine. Since the input must make a low to high transition to generate an interrupt, spurious transitions on the
Input should be suppressed. If the Input is normally
high, the NMI low time to guarantee triggering is two
CPU clock times. This Input Is typically reserved for
catastrophic failures like power failure or timeout of a
system watchdog timer.

' - -_ _ _ _- ' FFFFE

Figure 3El. Direction to Interrupt Service Routine through the
Interrupt Vector Table

All Interrupts In the 8086 must be assigned an Interrupt
type which uniquely Identifies each Interrupt. There are
three classes of Interrupt types In the 8086; predefined
Interrupt types which are issued by specific functions
within the 8086 and user defined hardware and software
Interrupts. Note that any interrupt type including the
predefined Interrupts can be Issued by the user's hardware and/or software.

TYPE 3 - ONE BYTE INTERRUPT
This Is invoked by a special form of the software interrupt Instruction which requires a single byte of code
space. Its primary use is as a breakpoint interrupt for
software debug. With full representation within a Single
byte, the Instruction can map into the smallest instruction for absolute resolution In setting breakpoints. The
Interrupt Is not maskable.

PREDEFIN ED INTERRUPTS
The predefined Interrupt types In the 8086 are listed
below with a brief description of how each is Invoked.
When Invoked, the CPU will transfer control to the
memory location specified by the vector associated
with the specific type. The user must provide the interrupt service routine and Initialize the interrupt vector
table with the appropriate service routine address. The
user may additionally Invoke these interrupts through
hardware or software. If the preassigned function Is not
used in the system, the user may assign some other
function to the associated type. However, for compatibility with future Intel hardware and software products for the 8086 family, Interrupt types 0-31 should not
be assigned as user defined interrupts.
TYPE 0 -

TYPE 4 -

INTERRUPT ON OVERFLOW

This interrupt occurs if the overflow flag (OF) is set in
the flag register and the INTO Instruction Is executed.
The instruction allows trapping to an overflow error service routine. The interrupt Is non-maskable.
Interrupt types 0 and 2 can occur without specific action
by the programmer (except for performing a divide for
Type 0) while types 1,3, and 4 require a conscious act by
the programmer to generate these interrupt types. All
but type 2 are Invoked through software activity and are
directly associated with a specific Instruction.

DIVIDE ERROR

This interrupt type Is Invoked whenever a division operation Is attempted during which the quotient exceeds the
maximum value (ex. division by zero). The Interrupt is
non-maskable and Is entered as part of the execution of
the divide Instruction. If Interrupts are not reenabled by
the divide error Interrupt service routine, the service
routine execution time should be included In the worst
case divide Instruction execution time (primarily when
considering the longest Instruction execution time and
its effect on latency to servicing hardware Interrupts).

USER DEFINED SOFTWARE INTERRUPTS
The user can generate an interrupt through the software
with a two byte Interrupt 'Instruction INT nn. The first
byte is the INT opcode while the second byte (nn) contains the type number of the Interrupt to be performed.
The INT Instruction Is. not maskable by the interrupt
enable flag. This instruction can be used to transfer contr.ol to routines that are dynamically relocatable and
whose location in memory is not known by the calling

A-26

AP-67
program. This technique also saves the flags of the calling program on the stack prior to transferring control.
The called procedure must return control with an interrupt return (IRET) instruction to remove the flags from
the stack and fully restore the state of the calling program.

UNINTERRUPTABLE INSTRUCTION SEQUENCE
MOV SS, NEW$STACK$SEGMENT
MOV SP, NEW$STACK$POINTER
Also, since prefixes are considered part of the instruction they precede, the 8086 will not sample the interrupt
line until completion of the instruction the prefix(es)
precede(s). An exception to this (other than HALT or
WAIT) is the string primatives preceded by the repeat
(REP) prefix. The repeated string operations will sample
the interrupt line at the completion of each repetition.
This includes repeat string operations which include the
lock prefix. If multiple prefixes precede a repeated
string operation, and the instruction is interrupted, only
the prefix immediately preceding the string primative is
restored. To allow correct resumption of the operation,
the following programming technique may be used:

All interrupts invoked through software (all interrupts
discussed thus far with the exception of NMI) are not
maskable with the IF flag and initiate the transfer of
control at the end of the instruction in which they occur.
They do not initiate interrupt acknowledge bus cycles
and will disable subsequent maskable Interrupts by
resetting the IF and TF flags. The interrupt vector for
these interrupt types is either implied or specified in the
instruction. Since the NMI is an asynchronous event to
the CPU, the point of recognition and initiation of the
transfer of control is similar to the maskable hardware
interrupts.

LOCKED$BLOCK$MOVE: LOCK REP MOVS DEST. CS:SOURCE
AND CX,
CX

USER DEFINED HARDWARE INTERRUPTS

JNZ LOCKED$BLOCK$MOVE

The maskable interrupts initiated by the system hardware are activated through the INTR pin of the 8086 and
are masked by the IF bit of the status register (interrupt
flag). During the last clock cycle of each instruction, the
state of the INTR pin is sampled. The 8086 deviates from
this rule when the instruction is a MOV or POP to a segment register. For this case, the Interrupts are not
sampled until completion of the following instruction.
This allows a 32-bit pOinter to be loaded to the stack
pOinter registers SS and SP without the danger of an interrupt occurring between the two loads. Another exception is the WAIT instruction which waits for a low active
input on the TEST pin. This instruction also continuously samples the interrupt request during its execution
and allows servicing interrupts during the wait. When an
interrupt is detected, the WAIT instruction is again
fetched prior to servicing the interrupt to guarantee the
interrupt routine will return to the WAIT instruction.

I

T,

\

T2

T3

T4

The code bytes generated by the 8086 assembler for the
MOVS instruction are (in descending order): LOCK
prefix, REP prefix, Segment Override prefix and MOVS.
Upon return from the interrupt, the segment override
prefix is restored to guarantee one additional transfer is
performed between the correct memory locations. The
instructions following the move operation test the
repetition count value to determine if the move was
completed and return if not.
If the INTR pin is high when sampled and the IF bit is set
to enable interrupts, the 8086 executes an interrupt
acknowledge sequence. To guarantee the interrupt will
be acknowledged, the INTR input must be held active
until the interrupt acknowledge is issued by the CPU. If
the BIU is running a bus cycle when the interrupt condition is detected (as would occur if the BIU is fetching an
instruction when the current instruction completes), the

TI

TI

T1

\

T,

T,

f\'--- _ _~n'-------,-_

ALE

\'---_ _------J/
~

\'---~/

~'--+---\

~~ ,,~, ~

FlOAT
-.J>--"''---------------.......

ADo-AD" \

\

TYPE VECTOR

DIVEN BY CPU IF QUEUE IS NOT FULL

Figure 3E2. Interrupt Acknowledge Sequence

A-27

t•

AP-67
interrupt must be valid at the 8086 2 clock cycles prior to
T4 of the bus cycle if the next cycle is to be an interrupt
acknowledge cycle. If the 2 clock setup is not satisfied,
another pending bus cycle will be executed before the
interrupt acknowledge is issued. If a hold request is also
pending (this might occur if an interrupt and hold request are made during execution of a locked instruction), the interrupt is serviced after the hold request is
serviced.
The interrupt acknowledge sequence is only generated
in response to an interrupt on the 8086 INTR input. The
associated bus activity is shown in Figure 3E2. The cycle consists of two INTA bus cycles separated by two
idle clock cycles. During the bus cycles the INTA command is issued rather than read. No address is provided
by the 8086 during either bus cycle (BHE and status are
valid), however, ALE is still generated and will load the
address latches with indeterminate information. This
condition requires that devices in the system do not
drive their outputs without being qualified by the Read
Command. As will be shown later, the ALE is useful in
maximum mode systems with multiple 8259A priority interrupt controllers. During the INTA bus cycles, DT/R
and DEN are conditioned to allow the 8086 to receive a
one byte interrupt type number from the interrupt
system. The first INTA bus cycle signals an interrupt
acknowledge cycle is in progress and allows the system
to prepare to present the interrupt type number on the
next INTA bus cycle. The CPu. does not capture information on the bus during the first cycle. The type number
must be transferred to the 8086 on the lower half of the
16-bit data bus during the second cycle. This implies
that devices which present interrupt type numbers to
the 8086 must be located on the lower half of the 16-bit
data bus. The timing of the INTA bus cycles (with exception of address timing) is similar to read cycle timing.
The 8086 interrupt acknowledge sequence deviates
from the form used on 8080 and 8085 in that no instruction is issued as part of the sequence. The 8080 and
8085 required either a restart or call instruction be
issued to affect the transfer of control.
In the minimum mode system, the MilO signal will be
low indicating I/O during the INTA bus cycles. The 8086
internal LOCK signal will be active from T2 of the first
bus cycle until T2 of the second to prevent the BIU from
honoring a hold request between the two INTA cycles.
In the maximum mode, the status lines SO-52 will request the 8288 to activate the INTA output for each cycle. The LOCK output of the 8086 will be active from T2
of the first cycle until T2 of the second to prevent the
8086 from honoring a hold request on either RQ/GT input and to prevent bus arbitration logic from relinquishing the bus between INTA's in multi-master systems.
The consequences of READY are identical to those for
READ and WRITE cycles.
Once the 8086 has the interrupt type number (from the
bus for hardware interrupts, from the instruction stream
for software interrupts or from the predefined condition), the type number is multiplied by four to form the
displacement to the corresponding interrupt vector in
the interruot vector table. The four bytes of the interrupt

vector are: least significant byte of the instruction
pointer, most significant byte of the instruction pOinter,
least significant byte of the code segment register,
most significant byte of the code segment register. During the transfer of control, the CPU pushes the flags and
current code segment register and instruction pointer
onto the stack. The new code segment and instruction
pOinter values are loaded and the single step and interrupt flags are reset. Resetting the interrupt flag disables
response to further hardware interrupts in the service
routine unless the flags are specifically re-enabled by
the service routine. The CS and IP values are read from
the interrupt vector table with data read cycles. No segment registers are used when referencing the vector
table during the interrupt context switch. The vector
displacement is added to zero to form the 20-bit address
and 54, 53= 10 indicating. no segment register selection.
The actual bus activity associated with the hardware interrupt acknowledge sequence is as follows: Two interrupt acknowledge bus cycles, read new IP from the interrupt vector table, read new CS from the interrupt vector table, Push flags, Push old CS, Opcode fetch of the
first instruction of the interrupt service routine, and
Push old IP. After saving the old IP, the BIU will resume
normal operation of prefetching instructions into the
queue and servicing EUrequests for operands. 55 (interrupt enable flag status) will go inactive in the second
clock cycle following reading the new CS.
The number of clock cycles from the end of the instruction during which the interrupt occurred to the start of
interrupt routine execution is 61 clock cycles. For software generated interrupts, the sequence of bus cycles
is the same except no interrupt aCknowledge bus cycles
are executed. This reduces the delay to service routine
execution to 51 clocks for INT nn and single step, 52
clocks for INT3 and 53 clocks for INTO. The same interrupt setup requirements with respect to the BIU that
were stated for the hardware interrupts also apply to the
software interrupts. If wait states are inserted by either
the memories or the device supplying the interrupt type
number, the given clock times will increase accordingly.
When conSidering the precedence of interrupts for
multiple simultaneous interrupts, the following guidelines apply: 1. INTR is the only maskable interrupt and if
detected simultaneously with other interrupts, resetting
of IF by the other interrupts will mask INTR. This causes
INTR to be the lowest priority interrupt serviced after all
other interrupts unless the other interrupt service
routines reenable interrupts. 2. Of the nonmaskable interrupts (NMI, Single Step and software generated), in
general, Single Step has highest priority (will be serviced first) followed by NMI, followed by the software interrupts. This implies that a simultaneous NMI and
Single Step trap will cause the NMI service routine to
follow single step; a simultaneous software trap and
Single Step trap will cause the software interrupt service routine to follow single step and a simultaneous
NMI and software trap will cause the NMI service
routine to be executed followed by the software interrupt service routine. An exception to this priority structure occurs if all three interrupts are pending. For this
case, transfer of control to the software interrupt ser-

A-28

AP-67
vice routine followed by the NMI trap will cause both the
NMI and software interrupt service routines to be ex·
ecuted without single stepping. Single stepping
resumes upon execution of the instruction following the
instruction causing the software interrupt (the next in·
struction in the routine being single stepped).

TF=l
IF=l

If the user does not wish to single step before INTR ser·
vice routines, the single step routine need only disable
interrupts during execution of the program being single
stepped and reenable interrupts on entry to the single
step routine. Disabling the interrupts during the pro·
gram under test prevents entry into the interrupt service
routine while single step (TF= 1) is active. To prevent
single stepping before NMI service routines, the single
step routine must check the return address on the stack
for the NMI service routine address and return control to
that routine without single step enabled. As examples,
consider Figures 3E3a and 3E3b. In 3E3a Single Step
and NMI occur simultaneously while in 3E3b, NMI, INTR
and a divide error all occur during a divide instruction
being single stepped.

TF,IF=l

NMI

CONTINUE TO SINGLE STEP
THE PROGRAM

Figura 3E3b. NMI, INTR, Single Step and Divide Error Simultaneous
Interrupts
NORMAL SINGLE STEP
OPERATION

SYSTEM CONFIGURATIONS
To accommodate the INTA protocol of the maskable
hardware interrupts, the 8259A Is provided as part of the
8086 family. This component Is programmable to
operate In both 8080/8085 systems and 6086 systems.
The devices are cascadable In master/slave arrange·
ments to allow up to 64 interrupts in the system. Figures
3E4 and 3E5 are examples of 8259A's In minimum and
maximum mode 6086 systems. The minimum mode con·
figuration (a) shows an 8259A connected to the CPU's

Figure 3E3a. NMI During Single Stepping and Normal Single Step
Oparatlon

A-29

AP-67
multiplexed bus. Configuration (b) illustrates an 8259A
connected to a demultiplexed bus system. These Inter·
connects are also applicable to maximum mode
systems. The configuration given for a maximum mode
system shows a master 8259A on the CPU's multiplexed
bus with additional slave 8259A's out on the buffered
system bus. This configuration demonstrates several
unique features of the maximum mode system Interface. If the master 8259A receives interrupts from a mix
of slave 8259A's and regular interrupting devices, the
slaves must provide the type number for devices connected to them while the master provides the type
number for devices directly attached to its interrupt Inputs. The master 8259A is programmable to determine if
an Interrupt is from a direct input or a slave 8259A and
will use this information to enable or disable the data
bus transceivers (via the 'nand' function of DEN and
EN). If the master must provide the type number, it will
disable the data bus transceivers. If the slave provides
the type number, the master will enable the data bus
transceivers. The EN output is normally high to allow

the 8086/8288 to control the bus transceivers. To select
the proper slave when servicing a slave Interrupt, the
master must provide a cascade address to the slave. If
the 8288 is not strapped in the 1/0 bus mode (the 8288
lOB Input connected to ground), the MCElPDEN output
becomes a MCE or Master Cascade Enable output. This
signal Is. only active during INTA cycles as shown In
Figure 3E6 a,nd enables the master 8259A's cascade address onto the 8086's 10ca.1 bus during ALE. This allows
the address latches to capture the cascade address with
ALE and allows use of the system address bus for
selecting the proper slave 8259A. The MCE is gated with
LOCK to minimize local bus contention between the
8086 three-stating Its bus outputs and the cascade address being enabled onto the bus. The first INTA bus cy;
cle allows the master to resolve internal priorities and
output a cascade address to be transmitted to ·tlie
slaves on the sui:)sequent INTA bus cycle. For additional
information on the 8259A, reference application note
AP-59.

I-__.....L._ _ _
ADDRESS
I---.,.-----..,.----.""T'---,/ BUS
..:;:]....L.:-_.=J....J:=--_~\

IJL------......::"""'--......::"---~\ DATA

I ' \ r - - - - - - - - - - - - - - - , / BUS

..

b.
Figure 3E4. Min Mode 8OB6 .wIth Master 8259A on the Local Bus and Sl ••e 8259As on the System Bus

A-30

AP-67

INTERRUPT

INTERRUPT

~~~--~--+-------~-----r----~-----r--~ffiITA

ADDRESS

~'-------'--------r-r--------,-~------,/BUS

I/I------------------~~--------~~------~\DATA

r----------------------------------------,/BUS

Figure 3E5. Max Mode 8086 with Master 8259A on the Local Bus and Sla.e 8259As on the System Bu.

f " _______---Jnl..-..--__
T1

ALE

I

T2

T3

T4

TI

T,

T1

1

T,

T,

\~_ _ _-----J/
iNTA

ADO-AD15

FLOAT

\'--_ _ _---J/

\~-

Figure 3E6. MCE Timing to Gate 8259A CAS Addres. onto the 8086 Local Bu.

A-31

AP-67
3F. Interpreting the 8086 Bus Timing Diagrams
At first glance, the 8086 bus timing diagrams (Diag. 3F1
min mode and Diag. 3F2 max mode) appear rather com·
plex. However, with a few words of explanation on how
to interpret them, they become a powerful tool in deter·
mining system requirements. The timing diagrams for
both the minimum and maximum modes may be divided
into six sections: (1) address and ALE timing; (2) read cy·
cle timing; (3) write cycle timing; (4) interrupt acknowl·
edge timing; (5) ready timing; and (6) HOLD/HlDA or
RQ/GT timing. Since the A.C. characteristics of the
signals are specified relative to the CPU clock, the rela·
tionship between the majority of signals can be de·
duced by simply determining the clock cycles between
the clock edges the signals are relative to and adding or
subtracting the appropriate minimum or maximum
parameter values. One aspect of system timing not com·
pensated for in this approach is the worst case relation·
ship between minimum and maximum parameter values
(also known as tracking relationships). As an example,
consider a signal which has specified minimum and
maximum turn on and turn off delays. Depending on
device characteristics, it may not be possible for the
component to simultaneously demonstrate a maximum
turn·on and minimum turn·off delay even though worst
case analysis might imply the possibility. This argument
is characteristic of MOS devices and is therefore ap·
plicable to the 8086 A.C. characteristics. The message
is: worst case analysis mixing minimum and maximum
delay parameters will typically exc~ed the worst case
obtainable and therefore should not be subjected to fur·
ther subjective degradation to obtain worst·worst case
values. This section will provide guidelines for specific
areas of 8086 timing sensitive to tracking relationships.
A. MINIMUM MODE BUS TIMING
1. ADDRESS and ALE
The address/ALE timing relationship is important to
determine the ability to capture a valid address from the
multiplexed bus. Since the 8282 and 8283 latches cap·
ture the address on the trailing edge of ALE, the critical
timing involves the state of the address lines when ALE
terminates. If the address valid delay is assumed to be
maximum TCLAV and ALE terminates at its earliest
point, TCHllmin (assuming zero minimum delay), the
address would be valid only TClCHmin·TClAVmax=8
ns prior to ALE termination. This result is unrealistic in
the assumption of maximum TClAV and minimum
TCHlL To provide an accurate measure of the true
worst case, a separate parameter specifies the
minimum time for address valid prior to the end of ALE
(TAVAl). TAVAl= TClCH·60 ns overrides the clock
related timings and guarantees 58 ns of address setup
to ALE termination for a 5 MHz 8086. The address is
guaranteed to remain valid beyond the end of ALE by the
TlLAX param~ter. This specification overrides the rela·
tionship between TCHll and TClAX which might seem
to imply the address may not be valid by the end of the
latest possible ALE. TllAX holds for the entire address
bus. The TClAXmin spec on the address indicates the
earliest the bus will go invalid if not restrained by a slow
ALE. TllAX and TClAX apply to the entire multiplexed
bus for both read and write cycles. AD15-O is three·

A-32

stated for read cycles and immediately switched to
write data during write cycles. AD19·16 immediately
switch from address to status for both read and write
cycles. The minimum ALE pulse width is guaranteed by
TlHllmin which takes precedence over the value obtained by relating TCllHmax and TCHllmin.
To determine the worst case delay to valid address on a
demultiplexed address bus, two paths must be con·
sidered: (1) delay of valid address and (2) delay to ALE.
Since the 8282 and 8283 are flow through latches, a valid
address is not transmitted to the address bus until ALE
is active. A comparison of address valid delay TCLAV·
max with ALE active delay TCllHmax indicates TCLAV·
max is the worst case. Subtracting the latch prop·
agation delay gives the worst case address bus valid
delay from the start of the bus cycle.
2. Read Cycle Timing
Read timing consists of conditioning the bus, activating
the read command and establishing the data transceiver
enable and direction controls. DT/R is established early
in the bus cycle and requires no further consideration.
During read, the DEN signal must allow the transceivers
to propagate data to the CPU with the appropriate data
setup time and continue to do so until the required data
hold time. The DEN turn on delay allows TClCl+
TCHClmin - TCVCTVmax - TDVCl = 127 ns transceiver
enable time prior to valid data required by the CPU.
Since the CPU data hold time TClDXmin and minimum
DEN turnoff delay TCVCTXmin are both 10 ns relative to
the same clock edge, the hold time is guaranteed. Addi·
tionally, DEN must disable the transceivers prior to the
CPU red riving the bus with the address for the next bus
cycle. The maximum DEN turn off delay (TCVCTXmax)
compared with the minimum delay for addresses out of
the 8086 (TClCl+ TCLAVmin) indicates the trans·
ceivers are disabled at least 105 ns before the CPU
drives the address onto the multiplexed bus.
If memory or I/O devices are connected directly to the
multiplexed address and data bus, the TAZRl parameter
guarantees the CPU will float the bus before activating
read and allowing the selected device to drive the bus.
At the end of the bus cycle, the TRHAV parameter spec·
ifies the bus float delay the device being deselected
must satisfy to avoid contention with the CPU driving
the address for the next bus cycle. The next bus cycle
may start as soon as the cycle following T4 or any
number of clock cycles later.
The minimum delay from read active to valid data at the
CPU is 2TClCl - TClRlmax - TDVCl = 205 ns. The
minimum pulse width is 2TClCl-75ns=325 ns. This
specification (TRlRH) overrides the result which could
be derived from clock relative delays (2TClClTClRlmax + TClRHmin).
3. Write Cycle Timing
The write cycle involves providing write data to the
system, generating the write command and controlling
data bus transceivers. The transceiver direction control
Signal DTfFi is conditioned to transmit at the end of each
read cycle and does not change during a write cycle.

AP-67
This allows the transceiver enable signal DEN to be ac·
tlve early In the cycle (while addresses are valid) without
corrupting the address on the multiplexed bus. The
write data and write command are both enabled from the
leading edge of T2. Comparing minimum WR active
delay TCVCTVmln with the maximum write data delay
TCLDV Indicates that write data may be not valid until
100 ns after write Is active. The devices in the system
should capture data on the trailing edge of the write
command rather than the leading edge to guarantee
valid data. The data from the 8086 is valid a minimum of
2TCLCL - TCLDVmax + TCVCTXmin = 300 ns before the
trailing edge of write. The minimum write pulse width is
TWLWH =2TCLCL - 60 ns =340 ns. The CPU maintains
valid write data TWHDX ns after write. The TWHDZ spec·
ification overrides the result derived by relating
TCLCHmin and TCHDZmin which implies write data
may only be valid 18 ns afterWR. The 8086 floats the bus
after write only if being forced off the bus by a HOLD or

RQ input. Otherwise, the CPU simply switches the out·
put drivers from data to address at the beginning of the
next bus cycle. As with the read cycle, the next bus cy·
cle may start in the clock cycle following T4 or any clock
cycle later.
DEN is disabled a minimum of TCLCHmin +
TCVCTXmin - TCVCTXmax = 18 ns after write to
guarantee data hold time to the selected device. Since
we are again evaluating a minimum TCVCTX with a max·
imum TCVCTX, the real minimum delay from the end of
write to transceiver disable is approximately 60 ns.
4. Interrupt Acknowledge Timing
The interrupt acknowledge sequence consists of two in·
terrupt acknowledge bus cycles as previously de·
scribed. The detailed timing of each cycle is identical to
the read cycle timing with two exceptions: command
timing and address/data bus timing.

11

VCHv--\
ClK (8284 OUTPUT)

~

...::; TCHCTV

T2"

T3

Tw

_TClCl-:JHC1~~

~
'--

MIlO

TCHCl

T.

~

-

I-- TClCH_

I

- I

TClAV-

TCllH-

i=-T

TClA;:

Y

BHE, A1 ....A1

TCHDX ......

DV

I\.
I-T~lAX

TlHJL-=:

r--

/~---

ALE
TCHll-1

I--

I--TAVAl-

RDY (8284 INPUT)

see NOTE4

VIH~i=
vt~
_ ~~ ~ ~
-TR1VCL

-

I

TRYLCL-

-

\

j--TClRIX

-

READY (8088 INPUT)

1
TClAV.

-

I.

lAVAL

~TRYHCHj

I--

I-

-

TllAX-

I-

READ CYCLE

=~TCHCTV

TDVCl-- -TClDX-:-1

M

TAZRl~

f

TClRl

DT/A

TCVCTV~

Figure 3Fl. 8086 Bus Timing -

A-33

f

-TCHRYX

-

-TClAX

A15-""

NOTE 1
(WR, iN1'A=VOH)

-

57-53

DATA IN
TCLRH-

'\I
FLOA:J~ f--TRHAV

r----

TRlRH

TCVCTX-

Minimum Mode System

1
I

TCHCTV

AP-67

CLK (8284 OUTPUT)

MliO

ALE

AD15-ADo
WRITE CYCLE
NOTE 1

(RiS, iNTA,
DTIII=vOH)

TCLAZ

FLOAT
TCHCTV

INTACYCLE
NOTES 1 &3

DTiii

RiS,W1I.vOH
liRE = VOL)

SOFTWARE HALT - (DEN =
VOe: 1m, WlI, iiiiTA DTlft - VOH; AD,.-Ao"
TI'S FOLLOW n, THEN NMI OR INTR
BEGIN A NEW Tl.
INVALID ADDRESS

AD1S- AD o
TCLAV
NOTES:

1. ALL SIGNALS SWITCH BETWEEN VOH AND VOl UNLESS OTHERWISE
SPECIFIED.
2. RDY IS SAMPLED NEAR THE END OF T" T., Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. BOTH INTA CYCLES RUN BACK·TO·BACK. THE 8088 LOCAL ADDRIDATA BUS IS
FLOATING DURING THE SECOND INTA CYCLE. CONTROL SIGNALS SHOWN
FOR SECOND INTA CYCLE.
4. SIGNALS AH284ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

Figure 3F1. 8086 Bus Timing -

Minimum Mode System (Con't)

A-34

AP-67

T,

T,

I- TCL2CL1

I--TCLCL-TCH1CH2~

1\----1

VCL-I

T

r~

,f\

VCH~

CLK

TCLAV-

,_

,'----.)

'--------.I

I------ TCHCL

r\
L-

"----'I

_TCLCH_

TCHSV

i--TCLSH

-----,~---4----r_---+---4~7n~~r+----_r~-----­

W;i;;f;!;7

52,51,So (EXCEPT HALT)
_______

\

SEE NOTE 8

~---r---r--~4----r~~TU

~-++_~,~T$~tXX--~,_T-CtL-DV----f_~----_r----_t--T-C-H-D-X-+~--"'

L

TSVLH

ii'HE, Al.-Al~

---

_

TCLLH-

r-

\..._----

5,,5,

TCHLL

'\

r--

ALE (8288 OUTPUT)

see NOTE 5

1

I~ __ -

Ii

!--TR1VCL

~K~~~~~

ROY (8284 INPUT)

TRYlCL·

"~.,,~ '''"' 1

-TCHRYX

T

YHSH

TCLAv-1

,

-

TRYHCH

t==----JL

READ CYCLE

_

~

- - TCLAZ

I--

I

)----:F::-r"'O."AT:-~

AD,.-Ao

DATA IN
FLOAT
TCLRH

TAZRL- -

/

RD

~~______________+---JI\~I

I
_ _________
TC_H_D_T_L_-__

I_{~~T-C+LR-Lr_-----,TRLRHI-----+-----I

DT/R
TCLML-8288 OUTPUTS
SEE NOTES 5,6

MRDC OR IORC

DEN

I\--

I------t<-lt-'TRHAV ----.j

-

TCLMH--

A

~~r-----------_rJ
TCVNV--

Ir----------------------------~¥

Figure 3F2a. 8086 Bus Timing

~.

TCVNX---

Maximum Mode System (Using 8288)

A-35

TCHDTH

AP-67

T,

T.

T,
Tw

ClK
VCl

Si,Ij,s, (EXCEPT HALn

'\.

WRITE CYCLE

_---

TCHDXAD1S-ADO

DATA
TCVNV-

TCVNX-

DEN

8288 0\I1'PUTS

see NOTES 5,6

MWIC OR lowe

INTACYCLE
AD16-ADo
SEe NOTES 3 & 4

FLOAT

rDvcL-

TC DX

POINTER

FLOAT

I

r--

MCEl

Pl!EN

TCHDTH

DliA:

82.

oum.JlS

'_

SEe NOTES s.SjINTA

DEN
TCVNX

INVAUD ADDRESS

TelAY

----. . \'--__---'1r - - - - - - - - - " " " T \\ -_____
_

~

NOTES:

1. ALL SIGNALS SWITCH BETWEEN YOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. RDY IS SAMPLED NEAR THE END OF T2. Ta. Tw TO DETERMINE IF Tw

MACHINES STATES ARE TO BE INSERTED.
CASCADE ADDRESS IS VAUD BETWEEN FIRST AND SECOND INTA CYCLES.
4, BOTH INTA CYCLES RUN BACK·TO·BACK. THE 8088 lOCAL ADDR/DATA BUS IS
"FLOAnNG DURING THE SECOND INTA CYCLE. CONTROL FOR POINTER ADDRESS
IS· SHOWN FOR SECOND INTA CYCLE.
5, SIGNALS AT 8214 OR 1288 ARE SHOWN FOR REFERENCE ONLY,
8. THE ISSUANCE OF THE _
COMMAND AND CONTROL SIGNALS (MRIIe,
IIWTC,
RIIIC, mwc, mI\Vll, IRn AND DEN) LAGS THE ACTIVE HIGH
I288CEN,
7, ALL nMING MEASUREMENTS ARE MADE AT ,.5V UNLESS OTHERWISE
NOTED.
.
STATUSINAcnVe IN STATE.JUSTPRIOR TO To,

a.

owe,

e.

Figura 3F2\I;

!1088 Bus Tlmln. -l\IIaxlniU.~I"Mode System (Using 8288) (Con't)

A-36

AP-67
The multiplexed address/data bus floats from the begInning (T1) of the INTA cycle (within TCLAZ ns). The upper
four multiplexed address/status lines do not three-state.
The address value on A19-A16 is indeterminate but the
status Information will be valid (S3=O, S4=O, S5=IF,
S6= 0, S7 = BHE= 0). The multiplexed address/data
lines will remain in three-state until the cycle after T4 of
the INTA cycle. This sequence occurs for each of the
INTA bus cycles. The interrupt type number read by the
8086 on the second INTA bus cycle must satisfy the
bame setup and hold times required for data during a
read cycle.

normally ready, devices not requiring wait states do
nothing to RDY while devices needing wait states
should disable RDY via the address decode and use a
combination of address decode and command to activate a delay to re-enable RDY.

The DEN and DT/R signals are enabled for each INTA cycle and do not remain active between the two cycles.
Their timing for each cycle is Identical to the read cycle.

6. Other Considerations

If the system requires no wait states for memory and a
fixed number of wait states for AD and WR to ail I/O
devices, the M/iO signal can be used as an early indication of the need for wait cycles. This allows a common
circuit to control ready timing for the entire system
without feedback of address decodes.

Detailed HOLD/HLDA timing is covered in the next section and is not examined here. One last signal consideration needs to be mentioned for the minimum
mode system. The TEST input is sampled by the 8086
only during execution of the WAIT instruction. The TEST
signal should be active for a minimum of 6 clock cycles
during the WAIT instruction to guarantee detection.

The INTA command has the same timing as the write
command. It Is active within 110 ns of the start of T2 providing 260 ns of access time from command to data
valid at the 8086. The command is active a minimum of
TCVCTXmln = 10 ns into T4 to satisfy the data hold time
of the 8086. This provides minimum INTA pulse width of
300 ns, however taking signal delay tracking into consideration gives a minimum pulse width of 340 ns. Since
the maximum Inactive delay of INTA is TCVCTXmax=
110 ns and the CPU will not drive the bus until 15 ns
(TCLAVmln) Into the next clock cycle, 105 ns are available for interrupt devices on the local bus to float their
outputs. If the data bus is buffered, DEN provides the
same amount of time for local bus transceivers to threestate their outputs.
5. Ready Timing
The detailed timing requirements of the 8086 ready
signal and the system ready signal into the 8284 are
described in Section 3D. The system ready signal Is
typically generated from either the address decode of
the selected device or the address decode and the command (RD, WR, INTA). For a system which Is normally
not ready, the time to generate ready from a valid address and not insert await state, is 2TCLCLTCLAVmax - TR1VCLmax = 255 ns. This time Is available for buffer delays and address decoding to determine if the selected device does not require a wait state
and drive the RDY line high. If walt cycles are required,
the user hardware must provide the appropriate ready
delay. Since the address will not change until the next
ALE, the RDY will remain valid throughout the cycle. If
the system Is normally ready, selected devices requiring
walt states also have 255 ns to disable the RDY line. The
user circuitry must delay re-enabling RDY by the appropriate number of wait states.

If the RD command is used to enable the RDY signal,
TCLCL- TCLRLmax- TRIVCLmax= 15 ns are available
for external logic. If the WR command is used, TCLCLTCVCTVmax - TRIVCLmax = 55 ns are available. Comparison of RDY control by address 'or command indicates that address decoding provides the best timing.
If the system is normally not ready, address decode
alone could be used to provide RDY for devices not requiring walt states while devices requiring walt states
may use a combination of address decode and command to activate a walt state generator. If the system is

B. MAXIMUM MODE BUS TIMING
The maximum mode 8086 bus operations are logically
equivalent to the minimum mode operation. Detailed
timing analysis now involves signals generated by the
CPU and the 8288 bus controlier. The 8288 also provides
additional control and command signals which expand
the flexibility of the system.
1. ADDRESS and ALE
In the maximum mode, the address information continues to come from the CPU while the ALE strobe is
generated by the 8288. To determine the worst case relationships between ALE and the address, we first must
determine 8288 ALE activation relative to the SO-S2
status from the CPU. The maximum mode timing
diagram specifies two possible delay paths to generate
ALE. The first is TCHSV + TSVLH measured from the rising edge of the clock cycle preceding n. The second
path is TCl.LH measured from the start of n. Since the
8288 initiates a bus cycle from t'he status lines leaving
the passive state (SO-52 = 1), if the 8086 is late in issuing
the status (TCHSVmax) while the clock high time is a
minimum (TCHCLmin), the status will not have changed
by the start of n and ALE is Issued TSVLH ns after the
status changes. If the status changes prior to the beginning of n, the 8288 will not issue the ALE until TCLLH
ns after the start of T1. The resulting worst case delay to
enable ALE (relative to the start of T1) is TCHSVmax+
TSVLHmax - TCHCLmin = 58 ns. Note, when calculating signal relationships, be sure to use the proper
maximum mode values rather than equivalent minimum
mode values.

A-37

The trailing edge of ALE is triggered In the 8288 by the
positive clock edge in n regardless of the delay to
enable ALE. The resulting minimum ALE pulse width Is
TCLCHmax-58ns=75ns assuming TCHLL=O.
TCLCHmax must be used since TCHCLmln was allsumed to derive the 58 ns ALE enable delay. The address is guaranteed to be valid TCLCHmin +
TCHLLmln - TCLAVmal( = 8 ns prior to the trailing edge

AP-67
of ALE to capture the address In the 8282 or 8283
latches. Again we have assumed a very conservative
TCHLL=O. Note, since the address and ALE are driven
by separate devices, no tracking of A.C. characteristics
can be assumed.
The address hold time 10 the latches Is guaranteed by
the address remaining valid until the end of T1 while
ALE is disabled a maximum of 15 ns from the positive
clock transition in T1 (TCHCLmin - TCHLLmax = 52 ns
address hold time). The multiplexed bus transitions
from address to status and write data cir three-state (for
read) are identical to the minimum mode timing. Also,
since the address valid delay (TCLAV) remains the
critical path in establishing a valid address, the address.
access times to valid data and ready are the same as·the
minimum mode system.
2. Read Cycle Timing
The maximum mode system offers read signals
generated by both the 8086 and the 8288. The 8086 RD
output signal timing is identical to the minimum mode
system. Since the A.C. characteristics .of the read commands generated by the 8288 are significantly better
than the 8086 output, access to devices on the demuitiplexed buffered system bus should use the 8288 commands. The 8086 RD signal is available for devices
which reside directly on the multiplexed bus. The
following evaluations for read, write and interrupt
acknowledge only consider the 8288 command timing.
The 8288 provides separate memory and 110 ~ead signals
which conform to the same A.C. characteristics. The
commands are issued TCLML ns after the start of T2
and terminate TCLMH ns after the start of T4.The
minimum command length is 2TCLCL- TCLMLmax+
TCLMLmin = 375 ns. The access time to valid data at the
CPU Is 2TCLCL-TCLMLmax-TDVCLmax=335 ns.
Since the 8288 was designed for systems with buffered
data busses, the commands are enabled before the CPU
has three-statedthe multiplexed bus and should not be
used with devices which reside directly on the multiplexed bus (to do so ·could result in bus contention during 8086 bus float and devicerurn-on)·:
.
The direction control fordata bus transceivers is established in T1 while the transceivers are not enabled by
DEN until the positive clock transition of T2. This provides TCLCH + TCVNVmin = 123 ns for 8086 bus float
delay and TCHCLmin+TCLCL-TCVNVmaxTDVCLmax = 187 ns of transceiver active to data valid at
the CPU. Since both DEN and command are valid a minimum of 10 ns into T4, the CPU data hold time TCLDX is
guaranteed. A maximum DEN disable of 45ns (TCVNX
max) guarantees the transceivers are disabled by the
start of the next 8086 bus cycle (215 ns minimum from
the same clock edge). On the positive clock transition of
T4, DT/R is returned to transmit in preparation for a
possible write operation on the next bus cycle. Since
the system memory and 110 devices reside on a buffered
system bus, they must three-state their outputs before
the device for the next bus cycle is selected (approximately 2TCLCL) or the transceivers drive write data onto
the tilus (approximately 2TCLCL).

3. Write Cycle Timing
In the maximum mpde, the 8.288 provides normal and advanced write commands for memory and 110. The advanced write commands are active a full clock cycle
aheadpf the np(mal write commands and have timing
identicalio the read commands. The· advanced write
pulse width is 2TCLCL- TCLMLmax+ TCLMHmln=375
ns while the nprmal write pulse width is TCLCLTCLMLmax + TCLMHmln = 175 ns. Write data setup
time to the selected device Is a function of either the
data valid delay from the 8086 (TCLDV) or the transceiver
enable delay TCVNV. The worst case delay to valid write
data is TCLDV", 110 ns minus transceiver propagation
delays. This Implies the data may not be valid until 100
ns after the advanced write command but will be valid
approximately TCLCL"': TClDVmax + TCLMLmin = 100
ns prior to the leading edge of the normal write command. Data will be valid 2TCLCL-TCLDVmax+
TCLMHmin = 300 ns before the trailing edge of either
write command. The data and command overlap for the
advanced command is 300 ns while the overlap with the
normal write command Is 175 ns. The transceivers are
disabled a minimum of TCLCHmin - TCLMHmax +
TCVNXmin =85 ns after the write command while the
CPU provides valid data a minimum of TCLCHminTCLMHmax + TCHDZmin = 85 ns. This guarantees write
data hold of 85 ns after the write command. The transceivers are disabled TCLCL - TCVNXmax +
TCHDTLmln=155 ns (assuming TCHDTL=O) prior to
transceiver direction change for a subsequent read
cycle.
4. Interrupt Acknowledge Timing
The maximum mode INTA sequence is logically identical to the minimum mode sequence. The transceiver
control (DEN and DT/R) and INTA command timing of
each interrupt acknowledge cycle is identical to the
read cycle. As in the minimum mode system, the multiplexed address/data bus will float from the leading edge
of T1 for each IIIITA bus cycle and not be driven by the
CPU until after T4 of .each INTA cycle. The setup and
hold times on the vector 'number for the second cycle
are the same as data setup and hold for the read. If the
devlcll providing the interrupt vector number is connected to the local bus, TCLCL - TCLAZmax +
TCLMLmin = 130 ns are available from 8086. bus float to
INTA command active. The selected deVice on the local
bus must disable the system data bus transceivers
since DEN is still generated'by the 8288.
If the 8288 Is not in the lOB (110 Bus) mode, the 8288
MCE/PDEN output becomes the MCE output. This output is active during each iiii'fA cycle and overiaps the
ALE signal during T1. The MCE is available for gatlrig
cascade addresses from a master 8259A onto three of
the upper AD15-AD8Iines and allowing ALE to latch the
cascade address into the address latches. The address
lines may then be used to provide CAS address selection to slave 8259A's located on the system bus (reference Figure 3E5). MCE is active within 15 ns of status or
the start of T1 for each INTA cycle. MCE should not
enable the CAS lines onto the multiplexed bus during
the first cycle since the CPU does not guarantee to float

A-38

AP-67
the bus until 80 ns into the first INTA cycle. The first
MCE can be inhibited by gating MCE with LOCK. The
8086 LOCK output is activated during T2 of the first
cycle and disabled during T2 of the second cycle. The
overlap of LOCK with MCE allows the first MCE to be
masked and the second MCE to gate the cascade address onto the local bus. Since the 8259A will not pro·
vide a cascade address until the second cycle, no infor·
mation is lost. As with ALE, MCE is guaranteed valid
within 58 ns of the start of T1 to allow 75 ns CAS address setup to the trailing edge of ALE. MCE remains
active TCHCLmin - TCHLLmax + TCLMCLmln = 52 ns
after ALE to provide data hold time to the latches.

ments are identical to those stated for the minimum
mode.
To inform the 8288 of HALT status when a HALT Instruction is executed, the 8086 will Initiate a status transition
from passive to HALT status. The status change will
cause the 8288 to emit an ALE pulse with an Indeterminate address. Since no bus cycle is Initiated (no command is issued), the results of this address will not affect CPU operation (I.e., no response such as READY Is
expected from the system). This allows external hard·
ware to latch and decode all transitions In system
status.

If the 8288 is strapped in the lOB mode, the MCE output
becomes PDEN and all I/O references are assumed to be
devices on the local bus rather than the demultiplexed
system bus. Since INTA cycles are considered I/O
cycles, all interrupts are assumed to come from the
local system and cascade addresses are not gated onto
the system address bus. Additionally, the DEN signal is
not enabled since no I/O transfers occur on the system
bus. If the local I/O bus is also buffered by transceivers,
the PDEN signal is used to enable those transceivers.
PDEN A.C. characteristics are identical to DEN with
PDEN enabled for I/O references and DEN enabled for
instruction or memory data references.

3G. Bus Control Transfer (HOLD/HLDA and RQ/GT)
The 8086 supports protocols for transferring control of
the local bus between itself and other devices capable
of acting as bus masters. The minimum mode conflg·
uration offers a signal level handshake similar to the
8080 and 8085 systems. The maximum mode provides
an enhanced pulse sequence protocol designed to op·
timize utilization of CPU pins while extending the
system configurations to two prioritized levels of alternate bus masters. These protocols are simply tech·
niques for arbitration of control of the CPU's local bus
and should not be confused with the need for arbitration
of a system bus.

5. Ready Timing
Ready timing based on address valid timing is the same
for maximum and minimum mode systems. The delay
from 8288 command valid to RDY valid at the 8284 is
TCLCL- TCLMLmax- TRIVCLmin= 130 ns. This time is
available for external circuits to determine the need to
insert wait states and disable RDY or enable RDY to
avoid wait states. INTA, all read commands and advanced write commands provide this timing. The normal
write command is not valid until after the RDY signal
must be valid. Since both normal and advanced write
commands are generated by the 8288 for all write
cycles, the advanced write may be used to generate a
RDY indication even though the selected device uses
the normal write command.
Since sepa.!!te commands are provided for memory and
110, no MilO signal is specifically available as in the
minimum mode to allow an early 'wait state required' indication for I/O devices. The S2 status line, however is
logically equivalent to the MilO signal and can be used
for this purpose.
6. Other Considerations
The RO/GT timing is covered in the next section and will
not be duplicated here. The only additional signals to be
considered in the maximum mode are the queue status
lines OSO, OS1. These signals are changed on the
leading edge of each clock cycle (high to low transition)
including idle and wait cycles (the queue status is independent of the bus activity). External logic may sample the lines on the low to high transition of each clock
cycle. When sampled, the signals indicate the queue activity in the previous clock cycle and therefore lag the
CPU's activity by one cycle. The TEST input require·

1. MINIMUM MODE
The minimum mode 8086 system uses a hold request input (HOLD) to the CPU and a hold acknowledge (HLDA)
output from the CPU. To gain control of the bus, a
device must assert HOLD to the CPU and wait for the
HLDA before driving the bus. When the 8086 can relinquish the bus, it floats the RD, WR, INTA and M/iO command lines, the DEN and DT/Rbus control lines and the
multiplexed address/data/status lines. The ALE signal is
not three-stated. The CPU acknowledges the request
with HLDA to allow the requestor to take control of the
bus. The requestor must maintain the HOLD request active until it no longer requires the bus. The HOLD request to the 8086 directly affects the bus interface unit
and only indirectly affects the execution unit. The CPU
will continue to execute from its internal queue until
either more instructions are needed or an operand
transfer is required. This allows a high degree of overlap
between CPU and auxiliary bus master operation. When
the requestor drops the HOLD Signal, the 8086 will respond by dropping HLDA. The CPU will not re-drive the
bus, command and control signals from three-state until
it needs to perform a bus transfer. Since the 8086 may
still be executing from its internal queue when HOLD
drops, there may exist a period of time during which no
device is driving the bus. To prevent the command lines
from drifting below the minimum VIH level during the
transition of bus control, 22K ohm pull up resistors
should be connected to the bus command lines. The
timing diagram in Figure 3G1 shows the handshake sequence and 8086 timing to sample HOLD, float the bus,
and enable/disable HLDA relative to the CPU clock.
To guarantee valid system operation, the designer must
assure that the requesting device does not assert con-

A-39

AP-67
trol of the bus prior to the 8086 relinquishing control and
that the device relinquishes control of the bus prior to
the 8086 driving the bus. The HOLD request into the
8086 must be stable THVCH ns prior to the CPU's low to
high clock transition. Since this input is not synchronized by the CPU, signals driving the HOLD input
should be synchronized with the CPU clock to
guarantee the setup time is not violated. Either clock
edge may be used. The maximum delay between HLDA
and the 8086 floating the bus is TCLAZmaxTCLHAVmin = 70 ns. If the system cannot tolerate the
70 ns overlap, HLDA active from the 8086 should be
delayed to the device. The minimum delay for the CPU to
drive the control bus from HOLD inactive is THVCHmin
+3TCLCL=635 ns and THVCHmin+3TCLCL+
TCHCL= 701 ns to drive the multiplexed bus. If the
device does not satisfy these requirements, HOLD inactive to the 8086 should be delayed. The delay from HLDA
inactive to driving the busses Is TCLCL+ TCLCHminTCLHAVmax = 158 ns for the control bus and 2TCLCLTCLHAVmax = 240 ns for the data bus.
1.1 Latency of HLDA to HOLD
The decision to respond to a HOLD request is made in
the bus interface unit. The major factors that influence
the decision are the current bus activity, the state of the
LOCK signal internal to the CPU (activated by the software LOCK prefix) and interrupts.
If the LOCK is not .active, an interrupt acknowledge cycle is not in progress and the BIU (Bus Interface Unit) Is
executing a T4 or TI when the HOLD request is received,
the minimum latency to HLDA is:

35 ns
65 ns
200 ns
10 ns

THVCH min (Hold setup)
TCHCL min
TCLCL (bus float delay)
TCLHAV min (HLDA delay)

310 ns

@ 5 MHz

The maximum delay under these conditions is:
34 ns
200 ns
82 ns
200 ns
180 ns

Uust missed setup time)
,',.
delay to next sample
TCHCL max
TCLCL (bus float delay)
TCLHAV max (HLDA delay)

677 ns

@5MHz

If the BIU just initiated a bus cycle when the HOLD Request was received, the worst case response time is:
34 ns
82 ns
7*200
N*200
160 ns

THVCH Uust missed)
tCHCL max
bus cycle execution
N walt states/bus cycle
TCLHAV max (HLDA delay)

1.676"s

@

5 MHz, no wait states

Note, the 200 ns delay for just misSing is included in the
delay for bus cycle execution. If the operand transfer is
a word transfer to an odd byte boundary, two bus cycles
are executed to perform the transfer. The BIU will not
acknowledge a HOLD request between the two bus
cycles. This type of transfer would extend the above
maximum latency by four additional clocks plus N additional wait states. With no wait states in the bus cycle,
the maximum would be 2.476 microseconds.
Although the minimum mode 8086 does not have. a hardware LOCK output, the software LOCK prefix may stili
be included in the instruction stream. The CPU Internally reacts to the LOCK prefix as would the maximum
mode 8086. Therefore, the LOCK does not allow a HOLD
request to be honored until completion of the instruction following the prefix. This allows an instruction
which performs more than one memory reference (ex.
ADD [BX), CX; which adds CX to [BXD to execute without
another bus master gaining control of the bus between
memory references. Since the LOCK signal is active for
one clock longer than the instruction execution, the
maximum latency to HLDA is:

elK

HOLD

.~m~==~==~7-;t--~~----------------------------~~--------------~f-~
CONTROL

HlDA _ _ _.-oJ

Figura 3G1. HOLD/HLDA Sequence

A-40

AP-67
34 ns
200 ns
82 ns
(M+ 1)*200 ns
200 ns
160 ns

THVCH ijust miss)
delay to next sample
TCHCL max
LOCK Instruction execution
set up HLDA (Internal)
TCLHAV max (HLDA delay)

(M*200ns)+876ns

@ 5 MHz

A typical use of the HOLD/HLDA signals in the minimum
mode 8086 system Is bus control exchange with DMA
devices like the Intel 8257·5 or 8237 DMA controllers.
Figure 3G2 gives a general interconnect for this type of
configuration using the 8237·2. The DMAcontrolier
resides on the upper half of the 8086's local bus and
shares the A8·A15 demultiplexing address latch of the
8086. All registers in the 8237·2 must be assigned odd
addresses to allow Initialization and Interrogation by the
CPU over the upper half of the data bus. The 8086
RDIWR commands must be demultiplexed to provide
separate 1/0 and memory commands which are compati·
ble with the 8231'2 commands. The AEN control from
the 8237·2 must disable the 8086 commands from the
command bus, disable the address latches from the
lower (AO·A7) and upper (A19·A16) address bus and
select the 8237·2 address strobe (ADSTB) to the A8·A15
address latch. If the data bus is buffered, a pull·up
resistor on the DEN line will keep the buffers dJsabled.
The DMA controller will only transfer bytes between

If the HOLD request Is made at the beginning of an Inter·
rupt acknowledge sequence, the maximum latency to
HLDA Is:

34 ns
82 ns
2600 ns
160 ns

THVCH Oust missed)
TCHCL max
13 clock cycles for INTA
TCLHAV max

2.876 JAB

@ 5 MHz

1.2 Minimum Mode DMA Configuration
Vee

T

DEMULTIPLEX
MIN MODE COMMANDS

I

rD~
1

8284

RDIWRlIOIM

WE

1

A11- 11

T

-

EJill!LE

L

READY
CLK
RESET
HOLD

ALE

AD150Q

HLDA

'--

8282

01
STB

DO

-r~
=

8088

T

001--

UPPER
DMA
AD DR -

)0-

01

-

8282

1/0 PORT
LOADED DURING
8237 INITIALIZATION
LOCAL DATA
BUS

r--e2i2

74L874

01
Q

CLR

-~D

~

DO

STB

AP7-O
8282
DO

' - - - 01
STB
EN

(AO)

~
-

087-0
AEN
ADSTB

HRQ CLK

MEMR
MEMW

t
Figure 3G2. DMA Using the 8237·2

A-41

~: )1-

iOW

8237·2

HLDA

--{>

COMMAND
BUS

RESET

AP-67
memory and 1/0 and requires the 1/0 devices to reside on
an 8-bit bus derived from the 16-bit t08-bit bus multiplex
circuit given in Section 4. Address lines A7·AO are driven
directly by the 8237 and BHE is generated by inverting
AO.lf A19-A16 are used, they must be provided by an additional port with either a fixed value or initialized by
software and enabled onto the address bus by AEN.

2.1 Shared System Bus (RO/GT Alternative)
The maximum mode RO/GT sequence is intended to
transfer control of the CPU local bus between the CPU
and alternate bus masters which reside totally on the
local bus and share the complete CPU interface to the
system bus. The complete interface includes the ad·
dress latches, data transceivers, 8288 bus controller and
8289 multi master bus arbiter. If the alternate bus
masters in the system do not reside directly on the 8086
local bus, system bus arbitration is required rather than
local CPU bus arbitration. To satisfy the need for multi·
master system bus arbitration at each CPU's system in·
terface, the 8289 bus arbiter should be used rather than
the CPU RO/GT logic.

Figure 3G3 gives an interconnection for placing the
8257 on the system bus. By using a separate latch to
hold the upper address from the 8257·5 and connecting
the outputs to the address bus as shown, 16·bit DMA
transfers are provided. In this configuration, AEN
simultaneously enables AO and BHE to allow word
transfers. AEN still disables the CPU interface to the
command and addres.s busses.

To allow a device with a simple HOLD/HLDA protocol to
gain control of a Single CPU system bus, the circuit in
Figure 3G4 could be used. The design is effectively a
simple bus arbiter which isolates the CPU from the
system bus when an alternate bus master issues a
HOLD request. The output of the Circuit, A£R (Address
ENable), disables the 8288 and 8284 when the 8086 in·
dicates idle status (50,51,$2 = 1), LOCK is not active and
a HOLD request is active. With AEN inactive, the 8288
three·states the command outputs and disables DEN

2. MAXIMUM MODE (RO/GT)
The maximum mode 8086 configuration supports a significantly different protocol for transferring bus control.
When viewed with respect to the HOLD/HLDA sequence
of the minimum mode, the protocol appears difficult to
implement externally. However, it is necessary to understand the intent of the protocol and its purpose within
the system architecture.

~
01

A19·16

ALE

3

00

A19.l7

1

STB

A16

BHE

BHE

T
CPU
BUS
INTERFACE

I
1

3

r--a282

"'L

01

AD15.8

t----

00

A15·9

1

STB

T

As

1

7

~
01

A7.'

00
~ STB

~

7

y- I

r---a2a6
'----A
OTIR
DEN

DE

_c~ll

HOL 0
HLOA

00

8282
01

DE 8282

t

087.0 ADSTB

8257-5

~

I

AEN

110 PORT

01

J

AEN

.1

1

A,

As·o

I

,I I I I,

Ao TO GROUND AND
UPPER BITS OF OMA ADDRESS
(FIXED OR REG)

CONTROLS ARE SAME AS 8·BIT
TRANSFER CONFIGURATION WITH
MANIPULATION OF THE DATA BUS

Figure 3G3. 8086 Min Syslem, 8257 on System Bus 16·Bil Transfers

A-42

AP-67
which three-states the data bus transceivers. AEN must
also three-state the address latch (8282 or 8283) outputs.
These actions remove the 8086 from the system bus and
allow the requesting device to drive the system bus. The
AEN signal to the 8284 disables the ready Input and
forces a bus cycle initiated by the 8086 to wait until the
8086 regains control of the system bus. The CPU may
actively drive its local bus during this interval.
The requesting device will not gain control of the bus
during an 8086 initiated bus cycle, a locked instruction
or an Interrupt acknowledge cycle. The LOCK signal
from the 8086 Is active between INTA cycles to
guarantee the CPU maintains control of the bus. Unlike
the minimum mode 8086 HOLD response, this arbitration circuit allows the requestor to gain control of the
bus between consecutive bus cycles which transfer a
word operand on an odd address boundary and are not
locked. Depending on the characteristics of the requesting device, any of the 74LS74 outputs can be used
to generate a HLOA to the device.
Upon completion of its bus operations, the alternate bus
master must relinquish control of the system bus and
drop the HOLD request. After AEN goes inactive, the address latches and data transceivers are enabled but, if a
CPU Initiated bus cycle is pending, the 8288 will not
drive the command bus until a minimum of 105 ns or
maximum of 275 ns later. If the system is normally not
ready, the 8284 AEN input may immediately be enabled
with ready returning to the CPU when the selected
device completes the transfer. If the system is normally
ready, the 8284 AEN input must be delayed iong enough
to provide access time equivalent to a normal bus cycle.
The 741..S74 latches in the design provide a minimum of
TCLCHmin for the alternate device to float the system
bus after releasing HOLD. They also provide 2TCLCL ns
address access and 2TCLCL- TAEVCHmax ns (8288
command enable delay) command access prior to enabling 8284 ready detection. If HLOA is generated as
shown in Figure 3G4, TCLCL ns are available for the
8086 to release the bus prior to issuing HLOA while
HLOA is dropped almost immediately upon loss of
HOLD.

A circuit configuration for an 8257-5 using this technique to interface with a maximum mode 8086 can be
derived from Figure 3G3. The 8257-5 has its own address
latch for buffering the address lines A15-A8 and uses its
AEN output to enable the latch onto the address bus.
The maximum latency from HOLD to HLOA for this circuit is dependent on the state of the system when the
HOLD is issued. For an idle system the maximum delay
is the propagation deiay through the nand gate and RIS
flip-flop (T01) plus 2TCLCL plus TCLCHmax plus propagation delay of the 74LS74 and 74LS02 (T02)_ For a
locked instruction it becomes: T01 + T02 + (M + 2)
*TCLCL+ TCLCHmax where M is the number of clocks
required for execution of the locked instruction. For the
interrupt acknowledge cycle the latency is
T01 + T02 + 9 *TCLCL + TCLCHmax.
2.2 Shared Local Bus (RQ/GT Usage)
The RQ/GT protocol was developed to allow up to two instruction set extension processors (co-processors) or
other special function processors (like the 8089 1/0
processor in local mode) to reside directly on the 8086
local bus. Each RQ/GT pin of the 8086 supports the full
protocol for exchange of bus control (Fig. 3G5). The sequence consists of a request from the alternate bus
master to gain control of the system bus, a grant from
the CPU to indicate the bus has been relinquished and a
release pulse from the alternate master when done_ The
two RQ/GT pins (RQ/GTO and RQ/Gn) are prioritized
with RQ/GTO having the highest priority. The prioritization only occurs if requests have been received on both
pins before a response has been given to either. For example, if a request is received on RQ/GT1 followed by a
request on RQ/GTO prior to a grant on RQ/Gn, RQ/GTO
will gain priority over RQ/GT1. However, if RQ/Gn had
already received a grant, a request on RQ/GTO must wait
until a release pulse is received on RQ/Gn.
The request/grant sequence interaction with the bus interface unit is similar to HOLO/HLOA. The CPU continues to execute until a bus transfer for additional instructions or data is required. If the release pulse is

+5

so
s,

, . - - - - - - - - - - - - - A E N (TO 8288&828213'0)

s,~==C)

LOCK

HOLD

D

Q

C

Q

AEN' (TO 8284)

+5
ClK
HlDA

Figure 304. Circuit to Translate HOLD Into AEN Di.abl"fo~ Max Mode 8088

A-43

AP-67
received before the CPU needs the bus, it will not drive
the bus until a transfer is required.
Upon receipt of a request pulse, the 8086 floats the
multiplexed address, data and status bus, the SO, 51,
and 52 status lines, the LOCK pin and RD. This action
does not disable the 8288 command outputs from driving the command bus and does not disable the address
latches from driving the address bus. The 8288 contains
Internal pull-up resistors on the So, 51, and 52 status
lines to maintain the passive state while the 8086 outputs are three-state. The passive state prevents the 8288
from initiating any commands or activating DEN to
enable the transceivers buffering the data bus. If the
device issuing the RO does not use the 8288, it must
disable the 8288 command outputs by disabling the
8288 AEN input. Also, address latches not used by the
requesting device must be disabled.

OND

Vcc

AD14

AD15

AD13

A161S3

AD12

A171S4

AD11

A181S5

AD10

A191S6

AD9

BHE/S7

AD8

MNIMX

AD7

RD

AD6

RDIGTO

AD5

RaIGTl

AD4

lOCK

AD3

52

AD2

Si

AD1

so

ADO

aso

NMI

2.3 RO/GT Operation
Detailed timing of the RO/GT sequence is given in
Figure 3G6. To request a transfer of bus control via the
RO/GT lines, the device must drive the line low for no
more than one CPU clock interval to generate a request
pulse. The pulse must be synchronized with the CPU
clock to guarantee the appropriate setup and hold times
to the clock edge which samples the RO/GT lines in the
CPU. After issuing a request pulse, the device must
begin sampling for a grant pulse with the next low to
high clock edge. Since the 8086 can respond with a
grant pulse in the clock cycle immediately following the
request, the RO/GT line may not return to the positive
level between the request and grant pulses. Therefore
edge triggered logic is not valid for capturing a grant
pulse. It also implies the circuitry which generates the
request pulse must guarantee the request is removed in
time to detect a grant from the CPU. After receiving the
grant pulse, the requesting device may drive the local
bus. Since the 8086 does not float the address and data
bus, LOCK or RD until the high to low clock transition
following the low to high clock transition the requestor
uses to sample for the grant, the requestor should wait
the float delay of the 8086 (TCLAZ) before driving the
local bus. This precaution prevents bus contention during the access of bus control by the requestor.
To return control of the bus to the 8086, the alternate
bus master relinquishes bus control and issues a
release pulse on the same RO/GT line. The 8086 may
drive the SO-52 status lines, RD and LOCK, three clock
cycles after detecting the release pulse and the address/data bus TCHCLmin ns (clock high time) after the
status lines. The alternate bus master should be threestated off the local bus and have other 8086 interface
circuits (8288 and address latches) re-enabled within the
8086 delay to regain control of the bus.

aS1

2.4 RO/GT Latency

INTR

TEST

ClK

READY

GND

RESET

The RO to GT latency for a single RO/GT line is similar
to the HOLD to HLDA latency. The cases given for the
minimum mode 8086 also apply to the maximum mode.
For each case the delay from RO detection by the CPU
to GT detection by the requestor is:
(HOLD to HLDA delay)- (THVCH + TCHCL+ TCLHAV)

Figure 3G5. 8086 RQ/GT Connections

__I
TClCL---------I

I-roye,",
r-TCHGX---

iiOiGi~'PULSE!....r

r----lT

.~

NOTES:
1. THE 10M FLOATSAxDx 8USIfti AND COCii ON THIS Eoo!
2. THE OTHER MASnR fLOATS Ii. Ii, 10 FADM 1.1.1 STATE ON THIS EDGE
3. THE OTHER MASTER FLOATS A~Ox IUS, ~ AND ~ ON THIS EOIlE
4. THE 10M REORIYES THE CONTROL LINES
5. THE 10M IIEDAIYES THE AOJoc LINES

Figure 3G6. Request/Grant Sequence

A-44

AP-67
This gives a clock cycle maximum delay for an idle bus
interface. All other cases are the minimum mode result
minus 476 ns. If the 8086 has previously issued a grant
on one of the RQ/GT lines, a request on the other RQ/GT
line will not receive a grant until the first device releases
the interface with a release pulse on its RQ/GT line. The
delay from release on one Ra/GT line to a grant on the
other is typically one clock period as shown in Figure
3G7. Occasionally the delay from a release on RQ/GT1

to a grant on RQ/G'fO will take two clock cycles and is a
function of a pending request for transfer of control
from the execution unit. The latency from request to
grant when the interface is under control of a bus
master on the other RQ/GT line is a function of the other
bus master. The protocol embodies no mechanism for
the CPU to force an alternate bus master off the bus. A
watchdog timer should be used to prevent an errant
alternate bus master from 'hanging' the system.

CHANNEL 0 TO 1
CLOCK

RoIGTO

~

RELEASE

~GRANT

CHANNEL 1 TO 0
CLOCK

RoIGn

~RELEASE

\'-__---J/

GRANT
OR

\

Figure 3G7. Channel T,ans'e, Delay

A-45

/

GRANT

AP-67
2.5 RQ/GT to HOLD/HLDA Conversion

of HLDA, It may be desirable to delay the acknowledge
one clock period. The HLDA is dropped no later than one
clock period after HOLD is disabled. The HLDA also
drops at the beginning of the release pulse to provide
2TCLCL + TCLCH for the requestor to relinquish control
of the status lines and 3TCLCL to float the remaining
signals.

A circuit for translating a HOLD/HLDA hand-shake sequence into a RQ/GTpulse sequence Is given in Figure
3GB. After receiving the grant pulse, the HLDA Is enabled TCHCLmin ns before the CPU has three-stated the
bus. If the requesting circuit drives the bus wlthin20 ns

ClOCK--,-----------------,

A

74lS78

)o--H-I J

74502
Q

ClK
K

1-.......- - ;........

HlDA

o ......-+-+-.

ClR

HOLD

74502

+5

74LS78

)o-+1

E3

Linear select techniques (Fig. 4C2) for 1/0 devices can
only be used with devices that either reside in the 1/0 ad·
dress space or require more than one active chip SP''lct
(at least one low active and one high active). Devices
with a single chip select input cannot use linear select if
they are memory mapped. This is due to the aSSignment
of memory address space FFFFFOH-FFFFFFH to reset
startup and memory space 00000H-003FFH to interrupt
vectors.

I

EVEN ADDRESSED
WORD PERIPHERALS

ADDRESS
LINE
~

07

Il5We

.{]cs
..
1m

110 DEVICE

Wfi

(0) SEPARATE 110 COMMANDS

Figure 4Bl. Sixleen·Bil 1/0 Decode

4C. General Design Considerations

ADDRESSi{]S
LINES(
CS

MINIMAX, MEMORY 1/0 MAPPED AND LINEAR SELECT

1m

1m

Since the minimum mode 8086 has common read and
write commands for memory and 1/0, if the memory and
1/0 address spaces overlap, the chip selects must be
qualified by MilO to determine which address space the
devices are assigned to. This restriction on chip select
decoding can be removed if the 1/0 and memory ad·
dresses in the system do not overlap and are properly
decoded; all 1/0 is memory mapped; or RD, WR and M/iO
are decoded to provide separate memory and 1/0
readlwrite commands (Fig. 4C1). The 8288 bus controller
in the maximum mode 8086 system generates separate
1/0 and memory commands in place of a M/iO signal. An
1/0 device is assigned to the 1/0 space or memory space
(memory mapped 1/0) by connection of either 1/0 or
memory command lines to the command Inputs of the
device. To allow overlap of the memory and 1/0 address
space, the device must not respond to chip select alone
but must require a combination of chip select and a read
or write command.

WA

WA

110 DEVICE

(b) MULTIPLE CHIP SELECTS

Figure 4C2. Linear Selecllor 1/0

4D. Determining 1/0 Device Compatibility
This section presents a set of A.C. characteristics whioh
represent the timing of the asynchronous bus interface
of the 8086. The equations are expressed in terms of the
CPU clock (when applicable) and are derived for
minimum and maximum modes of the 8086. They represent the bus characteristics at the CPU.
The results can be used to determine 1/0 device requirements for operation on a single CPU looal bus or
buffered system bus. These values are not applicable to

A-48

AP-67
a Multibus system bus Interface. The requirements for a
Multibus system bus are available In the Multibus inter·
face specification.
A list of bus parameters, their definition and how they
relate to the A.C. characteristics of Intel peripherals are
given in Table 401. Cycle dependent values of the
parameters are given in Table 402. For each equation, If
more than one signal path is involved, the equation
reflects the worst case path.

the relaxed device requirements for even a large complex configuration. The analysis assumes ali com·
ponents are exhibiting the specified worst case parameter values and are under the corresponding temperature, voltage and capacitive load conditions. If the
capacitive loading on the 8282183 or 8286/87 Is less than
the maximum, graphs of delay vs. capacitive loading In
the respective data sheets should be used to determine
the appropriate delay values.

=

TABLE 402. CYCLE DEPENDENT PARAMETER REQUIREMENTS
FOR PERIPHERALS

ex. TAVRL(address valid before read active)
(1) Address from CPU to RO active
( or)

(a) Minimum Mode

(2) ALE (to enable the address through the
address latches) to ROactive

TAVRL= TCLCL+ TCLRLmin- TCLAVmax=TCLCL-100
TRHAX = TCLCL - TCLRHmax + TCLLHmln = TCLCL - 150
TRLRH = 2TCLCL- 60;' 2TCLCL- 60
TRLDV = 2TCLCL- TCLRLmax- TDVCLmin = 2TCLCL-195
TRHDZ= TRHAVmin = 155 ns
TAVDV=3TCLCL- TDVClmin- TCLAVmax=3TCLCL-14O
TRLRL _ 4TCLCL= 4TCLCL
TAVWL=TCLCL+ TCVCTVmln- TCLAVmax=TCLCL-l00
TWHAX=TCLCL+ TCLLHmin- TCVCTXmax=TCLCL-ll0
TWLWH = 2TCLCL - 40= 2TCLCL - 40
TDVWH = 2TCLCL+ TCVCTXmin - TCLDVmax = 2TCLCL - 100
TWHDX= TWHDZmln =·89
TWLCL = 4TCLCL = 4TCLCL
TWHDXB=TCLCHmln+(- TCVCTXmax+ TCVCTXmin)=
TCLCHmin - 50

The worst case delay path Is (1).
For the maximum mode 8086 configurations, TAVWLA,
TWLWHA and TWLCLA are relative to the advanced
write signal while TAVWL, TWLWH and TWLCL are
relative to the normal write signal.
TABLE 401. PARAMETERS FOR PERIPHERAL COMPATIBILITY
TAVRl - Address stable before RD leading edge
TRHAX - Address hold after RD trailing edge
TRlRH - Read pulse width
TRLDV - Read to data valid delay
TRHDZ - Read trailing edge to data floating
TAVDV - Address to valid data delay
TRLRL - Read cycle time
TAVWL - Address valid before write leading edge
TAVWLA - Address valid before advanced write
TWHAX - Address hold after write trailing edge
TWLWH - Write pulse width
TWLWHA - Advanced write pulse width
TDVWH - Data set up to write trailing edge
TWHDX - Data hold from write trailing edge
TW.LCL - Write. recovery time
TWLCLA - Advanced write recovery time
TSVRL - Chip select stable before RD leading edge
TRHSX - Chip select hold after R[) trailing edge
TSLDV - Chip select to data valid delay
TSVWL - Chip select stable before WR leading edge
TWHSX - Chip select hold afterWR trailing edge
TSVWLA - Chip select stable before advanced write

(TAR)
(TRA)
(TRR)
(TRD)
(TDF)
(TAD)
. (TRCYC)
(TAW)
(TAW)
(TWA)
(TWW)
(TWW)
(TOW)
(TWO)
(TRV)
(TRV)
(TAR)
(TRA)
(TRD)
(TAW)
(TWA)
(TAW)

Note: Delays relative to chip select are a function of the chip select
decode technique used and are equal to: equivalent delay
from address - chip select decode delay .
(b) Maximum Mode
TAVRL= TCLCL+ TCLMLmin- TCLAVmax=TCLCL-l00
TRHAX = TCLCL - TCLMHmax + TCLLHmln = TCLCL - 40
TRLRH = 2TCLCL- TCLMLmax + TCLMHmln = 2TCLCL- 25
TRLDV= 2TCLCL- TCLMLmax- TDVCLmin=2TCLCL-65
TRHDZ= TRHAVmin = 155
TAVDV= 3TCLCL- TDVCLmin- TCLAVmax= 3TCLCL-140
TRLRL= 4TCLCL= 4TCLCL
TAVWLA = TAVRL= TCLCL- 100
'TAVWL=TAVRL+ TCLCL=2TCLCL-l00
TWHAX=TRHAX= TCLCL- 40
TWLWHA = TRLRH = 2TCLCL- 25
TWLWH = TRLRH - TCLCL= TCLCL - 25
TDVWH = 2TCLCL+ TCLMHmin - TCLDVmax = 2TCLCL-l00
TWHDX= TCLCHmin- TCLMHmax+ TCHDZmin= TCLCHmln- 30
TWLCL = 3TCLCL = 3TCLCL
TWLCLA = 4TCLCL = 4TCLCL

Symbols in parentheses are equivalent parameters specified for
Intel peripherals.

In the given list of equations, TWHOXB is the data hold
time from the trailing edge of write for the minimum
mode with a buffered data bus. For this equation,
TCVCTX cannot be a minimum for data hold and a max·
Imum for write Inactive. The maximum difference Is 50
,ns giving the result TCLCH·50. If the reader wishes to
verify the equations or derive others, refer to Section 3F
for assistance with Interpreting the 8086 bus timing
diagrams.

TABLE 403. COMPATIBLE PERIPHERALS (5 MHz 8088)
Configuration
Minimum Mode

8251A
8253·5
8255A·5
8257·5
8259A
8271
8273
8275
8279·5
8041A"
8741A
8291

Figure 401 shows four representative configurations
and the compatible Intel peripherals (Including walt
states If required) for each configuration are given In
Table 403. Configuration 1 and 2 are minimum mode
demultlplexed bus 8086 systems without (1) and with (2)
data bus transceivers. Configurations 3 and 4 are max·
Imum mode systems with one (3) and two (4) levels of address and data buffering. The last configuration is
characteristic of a multi-board system with bus buffers
on each board. The 5 MHz parameter values for these
configurations are given In Table 404 and demonstrate

Maximum Mode
Fully Buffered

Unbuffered

Buffered

Buffered

"
"
"

lW
lW
lW
lW

"
"
"
"
"

"
"
"
'"
"
"
"
"

"

"

lW
lW
lW
lW
lW
lW

"

"
"
"
"
"
"
"

"
"
"
"
"
"
"

"
"
"
"
'"

"Includes other Intel peripherals besed on the8041A (I.e., 8292, 8294,
8295).
" implies full operation with no walt states.
W Implies the number of wait states requirad.

A-49

AP·67
Peripheral compatibility Is determined from the equa·
tions given for the CPU by modifying them to account
for additional delays from address latches. and data
transceivers In the configuration. Once the. system con·
figuration Is selected, the system requirements can be
determined at the peripheral Interface and used to
evaluate' compatibility of the peripheral to the system.
During this process, two ,areas must be considered.
First, can the device operate at maximum bus band·
width and If not, how many wait states are required. Sec·
ond, are there any problems that cannot be resolved by
wait states.

TABLE 404. PERIPHERAL REQUIREMENTS FOR FULL SPEED
OPERAnoN WITH 5 MHz 8086

CiinHguratiOn
Maximum Mode
Minimum Mode
Fully Bullered
Suffered
Suffered
Unbuffered
TAVRL
TRHAX
TRLRH
TRLDV
TRHOZ
TAVOV
TRLRL
TAVWL
TAVWLA
TWHAX
TWLWH
TWLWHA
TOVWH
TWHOX
TWLCL
TWLCLA
TSVRL
TRHSX
TSLOV
TSVWL
TWHSX
TSVWLA
-

70
57
340
205
155
430
800
70

-97

72
27
320
150
158
400

mi'
72

-67

380

340

300
66
800

339
15
772
54
50
382
54
90

-

' 52
50
412
52
90

-

-

-

70
169
375
305
382
400
800
270
70
169
175
375
270
95
600
~o

52
171
382
252
-'171
52

58
141
347
261
380
372
772
298
58
'.. 141
147
347
25B
13
572
772
40
143

Examples of the first are TRLRH (rue:! po," width) and
TRLDV (read 'access or RD active to output data valid).
Consider address access time (valle:! address to valid
data) for the maximum mode fully buffered configura·
tlon.
TAVDV=3TCYC-140 ns - address latch delay address buffer delay - chip select decode delay - 2
transceiver delays

354

Assuming Inverting latches, buffers and trans·
celvers with 22 ns max delays (8283, 8281) and a
bipolar PROM decode with 50 ns delay, the result
is:

240
143
40

Not applicable,

TAVDV=322 ns @ 5 MHz

•• MINIMUM MODE

....

b. MINIMUM MODE BUFFERED DATA AND COMMAND BUSSES

Figura 401. 8066 Sy~lem Conllgurations

A-50

AP-67
c. MAXIMUM MODE BUFFERED DATA BUS
eLK

.21.

NOTE: FOR OPTIMUM PERFORMANCE WITH INTEl. PERIPHERAl.S, AIOW (ADVANCED
WRITE) SHOUl.D BE USED.

d. MAXIMUM MODE DOUBl.E BUFFERED SYSTEM
eLK

eMD

.214

....

PERIPHERAl.

I-===-...,/IADDR

DEVICE

Figure 401. 8086 System Configurations (Con't)

The result gives the address to data valid delay required
at the peripheral (in this configuration) to satisfy zero
walt state CPU access time. If the maximum delay
specified for the peripheral Is less than the result, this
parameter is compatible with zero wait state CPU operation. If not, wait states must be inserted until TAVDV + n
* TCYC (n is the number of wait states) is greater than
the peripherals maximum delay. If several parameters
require wait states, either the largest number required
should always be used or different transfer cycles can
insert the maximum number required for that cycle.

tional hardware, slowing down the CPU (If the parameter
is related to the clock) or not using the device.
As an example consider address valid prior to advanced
write low (TAVWLA) for the maximum mode fully buffered system.
TAVWLA= TCYC-100 ns - address latch delay address buffer delay - chip select decode delay+
write buffer delay (minimum)
Assuming inverting latches and buffers with 22 .ns
delay (8283, 8287) and an 8205 address decoder with
18 ns delay

The second area of concern includes TAVRL (address
set up to read) and TWHDX (data hold after write).
Incompatibilities in this area cannot be resolved by the
Insertion of wait states and may require either .addi-

TAVWLA=38 ns which Is the .tlme a 5 MHz 8086
system provides

A-51

AP-67
4E. 110 Examples
1. Consider an interrupt driven procedure for handling
multiple communication lines. On receiving an Interrupt
from one of the lines, the invoked procedure polls the
lines (reading the status of each) to determine which
line to service. The procedure does not enable lines but
simply services Input and output requests until the
associated output buffer is empty (for output requests)
or until an input line is terminated (for the example only
EOT is considered). On detection of the terminate condl·
tion, the routine will disable the line. It Is assumed that
other routines will fill a lines output buffer and enable
the device to request output or empty the Input buffer
and enable the device to Input additional characters.
The routine begins operation by loading CX with a count
of the number of lines in the system and OX with the 110
address of the first line. The I/O addresses are assigned
as shown in Figure 4E1 with 8251A's as the I/O devices.
The status of each line is read to determine if it needs
service. If yes, the appropriate routine is called to input
or output a character. After servicing the line or if no
service is needed, CX is decremented and OX is in·
cremented to test the next line. After all lines have been
tested and serviced, the routine terminates. If all inter·
rupts from the lines are OR'd together, only one inter·
rupt is used for all lines. If the interrupt is input to the
CPU through an 8259A interrupt controller, the 8259A
should be programmed in the level triggered mode to
guarantee all line interrupts are serviced.

buffers as a displacement into the data segment, the
base + index + displacement addressing mode allows
direct access to the appropriate memory location. 8086
code for part of this example is shown In Figure 4E2.
2. Asa second example, consider using memory
mapped I/O and the 8086 string prlmative instructions to
perform block transfers between memory and I/O. By
assigning a block of the memory address space
(equivalent in size to the maximum block to be trans·
ferred to the I/O device) and decoding this address
space to generate the I/O device's chip select, the block
transfer capability Is easily implemented. Figure 4E3
gives an Interconnect for 16·bit1/0 devices while Figure
4E4 incorporates the 16·bit bus to 8·bit bus multiplexing
scheme to support 8·bit 110 devices. A code example to
perform such a transfer is shown in Figure 4E5.

To service either an input or output request, the called
routine transfers OX to BX, and shifts BX to form the off·
set for this device into the table of input or output buf·
fers. The first entry in the buffer is an index to the next
character position in the buffer and is loaded into the 51
register. By specifying the base address of the table of

; THIS CODe DEMONSTRATES TESTING DEVICE
; STATUS FOR SERVICE, CONSTRUCTING THE

; APPROPRIATE LINE BUFFER ADDRESS FOR INPUT
; AND OUTPUT AND SERVICING AN INPUT
; REQUEST
MASK EQU OFFFDH
CHECK_STATUS:

WRITE_SERVICE:
NEXT_IO:

ADDRESS:

INPUT
MOV

AL, OX
AH,AL

TEST
JZ

AH, READ_OFLWRITLSTATUS
NEXT_IO

CALL
TEST

ADDRESS
AH, READ STATUS

JZ

WRITE_SERVICE

CALL

READ

TEST

AH, WRITE STATUS

JZ
CALL
DEC
JNC

NEXT_IO
WRITE

AND
ADD
OR
JMP

OX, MASK
OX, 3

; REMOVE Ai AND
; INCREMENT ADDREss.

OX, 2

; SELECT STATUS FOR

ex

; TEST IF DONE.

; YES, RESTORE. RETURN.

EXIT

AND
MOV
INC
SHR
XOR

CHECtLSTATUS

; NEXT INPUT.

ox, MASK

; SELECT DATA.
; CONSTRUCT BUFFER
; DISPLACEMENT FOR
; THIS DEVICE.
IS THE DISPLACEMENT.

BH, Dl
BH
BH
Bl, Bl

RET

READ:

; GET 8251A STATUS.

;ax

INPUT Al, ox
MOV SI, READ_BUFFERS IBX]
MOV READ_BUFFERS IBX + 511, AL
INC READ_BUFFERS [BX]
CMP Al, EOT
JNZ CONT_READ
CAll DISABLE READ
CONT_READ: RET

; READ CHARACTER.
; GET CHARACTER POINTER.
; STORE CHARACTER.
; INCR CHAAACTER POINTER.
; END OF TRANSMISSION?
; YES, DISABLE RECEIVER.
; SEND MESSAGE THAT INPUT
; IS READY.

Figure 4E2.

A19.8

q

3605
A·1
DECODE

1/0 CHIP SELECT

BIPOLAR
PROM

16·
BIT

1/0
DEVICES ARE CONNECTED TO THE UPPER AND
LOWER HALVES OF THE DATA BUS.
ADDRESS

o
1
2
3
4
5
6

7

TRANSFER 256 BYTE BLOCKS TO THE 1/0 DEVICE
DEVICE 0
DEVICE 1
DEVICE 0
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 2
DEVICE 3

DATA
DATA
CONTROUSTATUS
CONTROUSTATUS
DATA
DATA
CONTROUSTATUS
CONTROUSTATUS

'
=*=

THE ADDRESS SPACE ASSIGNED TO THE 1/0 DEVICE IS

A,.

FROM
THRU

k-- BASE
j . - BASE

ADDRESS
ADDRESS

A7

O's
1's

~o

MEMORY DATA NEED NOT BE ALIGNED TO EVEN ADDRESS BOUNDARIES

ETC.

1/0 TRANSFERS MUST BE WORD TRANSFERS TO EVEN ADDRESS BOUNDARIES

Figure 4E3. Block Transfer 10 16·BII 110 USing 8086 String Prlmatlves

Figure 4E1. Device Asslgnmenl

A-52

AP·67
number the device can accept, leaving the remaining ad;
dress lines for chip enable/select decoding. To connect
the devices directly to the multiplexed bus, they must
have output enables. The output enable is also
necessary to avoid bus contention in other configura·
tions. Figure 5A1 shows the bus connections for ROM
and EPROM memories. No special decode techniques
are required for generating chip enables/selects. Each
valid decode selects one device on the upper and lower
halves of bus to allow byte and word access. Byte ac·
cess is achieved by reading the full word onto the bus
with the 8086 only accepting the desired byte. For the
minimum mode 8086, if RD, WR and M/iO are not decod·
ed to form separate commands for memory and I/O, and
the I/O space overlaps the memory space assigned to
the EPROM/ROM then M/iO (high active) must be a con·
dition of chip enable/select decode. The output enable
is controlled by the system memory read signal.

3605
A·1
CHIP SELECT

015·8

\,.,---...,J

BHE

--r-- tRCo (max.).
7. tACO (max.) fs specified as a reference point only; If tRCO Is less than tRCo (m,ax.) access time Is tRACt If tRCD Is greater than tRCo (max.) acce$s time Is tRCo+tCAC·
8. tor Is measured between VIH (min.) and VIL (max.).
.
9. tr,CS. tcwo and tr,WO are specified as reference pOints only. If twcs ;. twes (min.) the cycle Is an early write cycle and the data out pin will remain high Impedance

tr

~e:~~~o~~~~:S:~~f~e~r~!~·~: :RY~~~~~n~~~~~~ ~n:a~~~d~t~:~gn~~~~~' ~~~:'~~~~~~t~s~~~:~·~~::. cycle and the data out will contain the data read from the
Figure SC1.3. 211. Family Timing (Con't)

A-61

AP·67

2) The norm,,' write command required to guarantee
data setup is not enabled until the CPU has sampled
READY thereby forcing multiple wait states during write
operations.

valid when READY was sampled and SACK to data valid
satisfied the CPU requirements. Figure 5.C.2.1 is a clr·
cuit which provides an early read command derived from
the maximum mode status. The early command Is en·
abled. from the trailing edge of ALE and disabled on the
trailing edge of the normal command. The command
provides an additional TCHCLmin - TCHLLmax +
TCLMLmax - circuit delays 53 ns of access time and
time to generate RDY from the early command. If we go
back to our previous equations, early command to valid
data at the CPU is now:

The first problem could be resolved if an early command
could be generated that would guarantee SACK was

TCHCLmin - TCHLLmax + 2TCLCL - TDVCLmax - buf·
fer and circuit delays = 333 ns

S.C.2 Enhanced Operation

Two problems are evident from the previous investlga·
tlon:
1) SACK timing from command will not allow reliable
operation while XACKis not active early enough to pre·
vent wait states.

=

+5

52"-----+=-t D

PRE
Q

13

10

81---+--+"1

Q

13
4,

.Sii---+--rt D

Q

74LS32

F+----'-11"1C~4LS74 Q

8

CLR

'--_ _--113

EARLYRo

Figura 5C2.1. Early Read and Write Command Generation

1\.-62

AP-67
We can now use the slowest 2118 which gives 8202 and
2118 access of 320 ns. Early command to ROY timing is
TCLCL- TCHLLmax - circuit delays - TR1VCLmax =
115 ns and provides 35 ns of margin beyond the 8202
command to SACK delay.
The write timing of the 8202 and write data valid timing
of the 8086 do not allow use of an early write command.
However, if the 8202 clock is reduced from 25 MHz to 20
MHz and WE to the RAM's is gated with CAS, the ad·
vanced write command (AMWC) may be used. At 20 MHz
the minimum command to CAS delay is 148 ns while the
maximum data valid delay is 144 ns.

refresh. Delaying SACK until XACK time causes the
CPU to enter wait states until the cycle is completed. If
the cycle is a read cycle, the XACK timing guarantees
data is valid at the CPU before ROY is issued to the CPU.
The use of the early command Signals also solves a
problem not mentioned previously. The cycle rate of the
8202 @ 20 MHz requires that commands (from leading
edge to leading edge) be separated by a minimum of 695
ns. The maximum mode 8086 however may issue a read
command 600 ns after the normal write command. For
the early read command and advanced write command,
725 ns are guaranteed between commands.

The reduced 8202 clock frequency still satisfies no wait
state read operation from early read and will insert no
more than one wait state for write (assuming no conflict
with refresh). 20 MHz 8202 operation will however reo
quire using the 2118·4 to satisfy read access time.
EARLY RD

Note that slowing the 8202 to 22.2 MHz guarantees valid
data within 10 ns after CAS and allows using the 2118·7.
Since this analysis is totally based on worst case
minimum and maximum delays, the designer should
evaluate the timing requirements of his specific im·
plementation.

We TO

RAMS

'-----CAS

It should be noted that the 8202 SACK is equivalent to
XACK timing if the cycle being executed was delayed by

Figure 5C2.2. Delayed Write 10 Dynamic RAMs

A-63

AP-67
APPENDIX I
BUS CONTENTION AND ITS EFFECT ON SYSTEM INTEGRITY
SYSTEM ARCHITECTURE

function, chip select (CS), which is very fast (tco = 120
ns) with respect to the overall access time (tACC = 450
ns) of the 2708. It is this time difference (330 ns) that is
used to perform the decode function, as illustrated in
Figure 2. The scheme works well and does not limit
system performance, but it does lead to the possibility
of bus contention.

As higher performance microprocessors have become
available, the architecture of microprocessor systems
has been evolving, again placing demands on memory.
For many years, system designers have been plagued
with the problem of bus contention when connecting
multiple memories to a common data bus. There have
been various schemes for avoiding the problem, but
device manufacturers have been unable to design inter·
nal circuits that would guarantee that one memory
device would be "off" the bus before another device
was selected. With small memories (512x8 and 1Kx8), it
has been traditional to connect all the system address
lines together and utilize the difference between tACC
and tco to perform a decode to select the correct device
(as shown in Figure 1).

ADDRESS~
CS

DATA OUT

I

I

{

I

,_o,~~_L~

Figure 2. Single Line Control Architecture

BUS CONTENTION

Figure 1. Single Control Line Architecture

With the 1702A, the chip select to output delay was only
100 ns shorter than the address access time; or to state
it another way, the tACC time was 1000 ns while the tco
time was 900 ns. The 1702A tACC performance of 1000 ns
was suitable for the 4004 series microprocessors, but
the 8080 processor required that the corresponding
numbers be reduced to tACC= 450 ns and tco= 120 ns.
This allowed a substantial Improvement in performance
over the 4004 series of microprocessors, but placed a
substantial burden on the memory. The 2708 was
developed to be compatible with the 8080 both in ac·
cess time and power supply requirements. A portion of
each 8080 machine cycle time had to be devoted to the
architecture of the system decoding scheme used. This
devoted portion of the machine cycle included the time
required for the system controller (8224) to perform its
function before the actual decode process could begin.

There are actually two problems with the scheme
described in the previous section. First, if one device in
a multiple memory system has a relatively long deselect
time, and a relatively fast decoder is used, it would be
possible to have another device selected at the same
time. If the two devices thus selected were reading opposite data; that is, device number one reading a HIGH
and device number two reading a LOW, the output transistors of the two memory devices would effectively pro·
duce a short circuit, as Figure 3 illustrates. In this case,
the current path is from Vcc on device number one to
GND on device number two. This current is limited only
by the "on" impedance of the MOS output transistors
and can reach levels in excess of 200 mA per device. If
the MOS transistors have a lot of "extra" margin, the
current is usually not destructive; however, an instantaneous load of 400 mA can produce "glitches" on the
VCC supply-glitches large enough to cause standard
TIL devices to drop bits or otherwise malfunction, thus
causing incorrect address decode or generation.

Let's pause here and examine the actual decode
scheme that was used so we can understand how the
control functions that a memory device requires are
related to system architecture.
The 2708 can be used to illustrate the problem of having
a single control line. The 2708 has only one read control

A-64

The second problem with a single control line scheme is
more subtle. As previously mentioned, there is only one
control function available on the 2708 and any decoding
scheme must use it out of necessity. In addition, any inadvertent changes in the state of the high order address
lines that are inputs to the decoder will cause a change
in the device that is selected. The result is the same as
before-bus contention, only from a different source.
The deselected device cannot get "off" the bus before
the selected one is "on" the bus as the addresses rapidly change state. One approach to solving this problem
would be to design (and specify as a maximum) devices

AP-67
with tOF time less than teo time, thereby assuring that if
one device is selected while another is simultaneously
being deselected, there would be some small (20 ns)
margin. Even with this solution, the user would not be
protected from devices which have very fast teo times
(teo is specified as a maximum).

RESULTS OF IMPROPER TIMING WHEN OR TYING MULTIPLE
MEMORIES.

generate the unique device selecting function, but a
separate and independent Output Enable (OE) control is
now used to gate data "on" and "off" the system data
bus. With this scheme, bus contention is completely
eliminated as the processor determines the time during
which data must be present on the bus and then
releases the bus by way of the Output Enable line, thus
freeing the bus for use by other devices, either
memories or peripheral devices. This type of architec·
ture can be easily accomplished if the memory devices
have two control functions, and the system is im·
plemented according to the block diagram shown in
Figure 5. It differs from the previous block diagram
(shown in Figure 1) in that the control bus, which is connected to all memory Output Enable pins, provides
separate and independent control over the data bus. In
this way, the microprocessor is always in control of the
system; while in the previous system, the microproc·
essor passed control to the particular memory device
and then waited for data to become available. Another
way to look at it is, with a single control line the sytem is
always asynchronous with respect to microprocessorl
memory communications. By using two control lines,
the memory is synchronized to the processor.

Figure 3. Results 01 Improper Timing when OR Tying Multiple
Memories

The only sure solution appears to be the use of an exter·
nal bus driver/transceiver that has an independent
enable function. Then that function, not the "device
selecting function," or addresses, could control the
flow of data "on" and "off" the bus, and any contention
problems would be confined to a particular card or area
of a large card. In fact, many systems are implemented
that way-the use of bus drivers is not at all uncommon
in large systems where the drive requirements of long,
highly capacitive interconnecting lines must be taken
into consideration-it also may be the reason why more
system designers were not aware of the bus contention
problem until they took a previously large (multicard)
system and, using an advanced micorprocessor and
higher density memory devices, combined them all on
one card, thereby eliminating the requirement for the
bus drivers, but experiencing the problem of bus contention as described above.

ADDRESS

J

'C

SELECTION

OUTPUT
ENABLE

DATA
OUT

\

I

(

)

Figure 4. Two Control Line Architecture

THE MICROPROCESSOR/MEMORY INTERFACE

From the foregoing discussion, it becomes clear that
some new concepts, both with regard to architecture
and performance are required. A new generation of two
control line devices is called for with general requirements as listed below:
1. Capability to control the data "on" and "off" the
system bus, independent of the device selecting function identified above.
2. Access time compatible with the high performance
microprocessors that are currently available ..
Now let's examine the system architecture that is required to implement the two line control and prevent
bus contention. This is shown in the form of a timing
diagram (Figure 4). As before, addresses are used to

A65/A66

Figure 5. Two Control LinEt Architecture

APPLICATION
NOTE

Ap·61

July 1979

© Intel Corporation, 1979

A-67

AP-61

Multitasking
For the 8086

Contents
INTRODUCTION
ANATOMY OF THE TASK MULTIPLEXER
DEFINITIONS
STATE DIAGRAM
LINKED LISTS
DELAY STRUCTURE
PROCEDURES
ACTIVATE$TASK Procedure
ACTIVATE$DELA Y Procedure
DECREMENT$DELAY Procedure
CASE$TASK Procedure
PREEMPT Procedure
DISPATCH Procedure

PL/M·86 PROCEDURES
Initialization and the Main Loop
Additional Ideas
Source Code

REFERENCES

A-68

AP-61
INTRODUCTION

Real-time software systems differ markedly from batch
processing systems_ An external signal indicating that
it is time for an hourly log or an interrupt caused by an
emergency condition is an event usually not encountered in batch processing. Because real-time control
systems of all types share a number of characteristics,
it is possible to develop flexible operating systems
which will meet the needs of a great majority of realtime applications. Intel Corporation has developed such
a system, the RMX/80TM system, for the iSBCTM line of
8080/85 based single board computers. Thus, the user is
released from the chore of designing an operating
system and is free to concentrate his efforts on the
applications software for the individual tasks and
merely integrate them into a pre-existing system.
But what if a user does not need all the capabilities of an
RMX/80™ system or wants a different hardware configuration than an iSBC™ computer? This application
note contains a set of PLlM-86 procedures designed to
be used in medium-complexity 8086 real-time systems.
A normal control system can be broken down into a
number of concurrently executable tasks. The CPU can
be running only one task at any instant of time but the
speed of the processor often makes concurrent tasks
appear to be running simultaneously. Breaking the software functions into separate concurrent tasks is the job
of the designer/programmer. Once this is done there remains the problem of integrating these tasks with a
supervisory program which acts as a traffic cop in the
scheduling and execution of the separate tasks. This
note discusses a set of PLlM-86 procedures to implement the supervisory program function.
A minimum operating system might (like its batch processing cousin) have only a queue for ready tasks (tasks
waiting to be executed). Any task that becomes ready is
put on the bottom of the queue and when a running task
is finished, the task on the top of the queue is started.
Any interrupt causes the state of the system to be
saved, an interrupt routine to be executed, the state of
the system to be restored, and execution of the interrupted program to continue. The interrupt routine might
(or might not) put a new task on the ready queue. This
approach has worked well for many simple control
systems, especially in the single-chip computer area.
But what features are lacking in this approach that are
necessary (or at least nice)?
1. A system of priorities is often needed. All waiting
ready tasks must be executed sooner or later but some
tasks need immediate attention while others can be run
when there is nothing else to do. If a midnight monthly
report, due for completion by 8 a.m. the next day, is in
the process of printing at 1 a.m. and a fire alarm occurs,
it is reasonable to assume that the fire alarm has higher
priority since the fire could conceivably render the
monthly report irrelevant.

There are a number of ways in which to assign priorities.
Tasks are usually numbered and may be assigned
priorities according to their ascending (or descending)
numbers. They could instead be grouped into a number
of priority levels, with tasks on the same level having
equal priorities. The latter approach is taken in this
application note.
Assume that a monthly report is being printed and an
alarm occurs in the external world that, because of its
importance, must be attended to immediately. The interrupt routine, executed as a result of the alarm input,
should not automatically return to the interrupted logging routine but instead should call a preempt routine
which checks to see if a higher priority task is ready for
execution. The reason for this is that the monthly report
routine, if returned to, has no way of "knowing" that a
higher priority task is waiting to be executed. The alarm
output task has been readied by the interrupt routine
and since it is known to be higher priority than the logging task, it is executed first, thereby immediately
signaling the system operator that there has been an
alarm. It then returns to the logging task provided that
there are no further high priority tasks waiting to be executed. The logging printer may not have even paused
during the alarm output task. The computer appears to
human beings to be executing concurrent tasks
simultaneously.
Of course, the alarm output function could be performed
inside the interrupt procedure. But sooner or later, the
designer will encounter a worst case situation in which
there is not enough time to execute all required tasks
between interrupts, and the system will fall behind in
real-time. It is much cleaner to make the interrupt procedures as short as possible and stack up tasks to be
executed than to stack up interrupt procedures.
2. Another feature that might be necessary is a capability to put a task to sleep for a known period of real time.
Assume a relay output must remain closed for one second. Most real-time systems cannot tolerate the dedication of the CPU to such a trivial task for that length of
time so a system of programmable dynamic delays
could be implemented. This application note implements such a system.
Although the PLlM-86 procedures here have been debugged and tested, it is assumed that the user will want
to change, add, or delete features as needed. This application note is intended to present ideas for a logical
structure of procedures that, because they are written in
PLlM-86, can be easily modified to user requirements.
Each procedure will be discussed in detail and integration and optional features will be presented.
PLlM-86

PLM-86 is a block structured high level language that
allows direct design of software modules. Using
PLlM-86, designers can forget their assembly level

A-69

AP-61
coding problems and design directly.in a subset of the
English language, The 8086 architecture was designed
to accommodate highly structured languages and the
PLM·86 compiler is quite efficient in the generation of
machine code.

DO WHILE A= B;
C=D;
E= F;
END;
DO 1=1 TO 5;
A= I;
C= D+I;
END;

PLM·86 STRUCTURE

PLlM·86 automatically keeps track of the level of the dif·
ferent software blocks, (See Chapter 10, "PLlM·86 Pro·
gramming Manual"), There are methods of writing
PLlM·86 which contribute to the understandability of
the source code without adding to the amount of object
code generated, For instance, the following three
IF/THEN/ELSE blocks generate identical object code
but are compiled from different source statements,

Line

Level

3

1

IF

A= B THEN DO;
C= D;
END;
ELSE DO;
E= F;
END;

Statement

IF A= BTHEN C= D; ELSE E= F; G= H;
IF A= B THEN
C=D;
ELSE
E=F;
G=H;

7
8

9
10
11
13
14
15
16
17
18

DO CASE A;
A= B;
A=C;
A=D;
END;

1

2
2
1
2

2

IF

A=BTHENDO;
C=D;
END;
ELSE IF A= C THEN DO;
D=E;
END;
ELSE IF A= D THEN DO;
E= F;
END;
ELSE DO;
F=G;
END;

IF A= B THEN DO;
C
D;
END;
ELSE DO;
E= F;
END;
G= H;

=

It is not instantly apparent from the code on line 3 or the
code starting at line 7 which statements will be exe·
cuted, However, adding the DO; and END; statements
(starting at line 11) remove any doubt, Either the
statements starting at line 11 or the statements starting
at line 15 will be executed and the statement on line 18
will be executed in either case, Why? Because all these
lines are at level 1 in the block structure, The other lines
are at level 2 because of the DO;/END; combinations,
When one refers to the relatively complex structures of
the task multiplexer procedures, the usefulness,of such
an approach is obvious, as the procedures have been in·
dented according to the level numbers generated by
PLlM·86, In particular, if the designer is not careful,
nested IF/THEN/ELSE statements can generate im·
proper results, Using a proper number of DO;/END; com·
binations avoids the possible ambiguity in nested
IF/THEN/ELSE statements as can be seen in the ACTI·
VATE$TASK procedure listed in the PLlM·86 source
code later in this note, The DO;/END;construct naturally
must be used when multiple statements are required
within the IF/THEN/ELSE blocks, Following are exam·
pies of the possible primary structures of PLlM·86:
DO;
A=B;
C=D;
END;

A complete tutorial on structured programming is
beyond the scope and intent of this application note and
the reader is referred to the appropriate references ap·
pearing in the bibliography.

ANATOMY OF THE TASK MULTIPLEXER

Once a decision is made on the details of the kind of
data structure that is needed to implement the task
multiplexer, the procedures that manipulate the struc·
ture are relatively simple to write. The following char·
acteristics are assumed for the task multiplexer appear·
ing in this application note.
There are two levels of priority, high and low, All high
priority tasks that are ready to run will be dispatched,
executed, and completed, on a FIFO basis, before any
low priority task is dispatched.
Any task can be interrupted. No task multiplexer pro·
cedure can be interrupted.
If a high priority task is interrupted, it will be completed
before any other task is dispatched. If a low priority task
is interrupted, all ready high priority tasks will be dis·
patched, executed, and completed before program can·
trol is returned to the low priority task.

A-70

AP-61
There are two ready queues, one for high priority tasks
and one for low priority tasks. Each queue has a head
(top) pointer and a tail (bottom) pointer and tasks on any
queue are link-listed from head to tail. Tasks are "dispatched" (taken off the queue) at the head and "activated" (put on the queue) at the tail on a FIFO basis.

HIGH$PRIORITY$HEAD = 5
HIGH$PRIORITY$TAIL = 3
LOW$PRIORITY$HEAD = 8
LOW$PRIORITY$TAIL = 10
DELAY$HEAD
=4
TASK NUMBER

Link-listed queues are chosen for simplicity. All dispatch and activate information is contained in the head
and tail pointers. Tasks located in the middle of these
link-lists are of no concern for activating and dispatching. This means, of course, that tasks are executed in
the order that they appear on the queue, i.e., first-in,
first-out.
There is a pointer byte associated with each task. If a
task is on either the low priority or high priority ready
queue, its associated pointer byte will pOint to the next
task number on the list. These pointer bytes enable the
task ready lists to be linked. Note that the pointer byte is
o for the last task on a list.
There is a status (flag) byte associated with each task. If
a task is on a ready list or a delay list, bit 7 will be a "1"
indicating that that particular task is busy. If a task is on
either high priority or low priority ready queues, bit 6 will
be a "1" indicating that the task is on one of the ready
queues. If the task is listed on the delay list, (see next
item), bit 5 will be a "1" indicating that this particular
task has a delay in progress. If a task is unlisted, bits
5-7 will be "0." Bits 0-4 are not used by the task
multiplexer procedures and are available to the user, giving 5 user defined flags per task.
There is a delay byte associated with each task. This
feature allows tasks to be "put to sleep" for a variable
length of time, from 1 to 255 "ticks" of the interrupt
clock. If a task does not need an associated delay then
this byte is available to the user as a utility byte to be
used for any purpose. These delays will be discussed in
detail later in the application note.
The following diagram is a representation of the task
multiplexer data structure:

TASK NUMBER

m-1
m

porNTER BYTE

STATUS BYTE

DELAY BYTE

n
n+3
n+6
n+9
n+ 12
n+ 15

n+1
n+4
n+7

n+ 10

n+2
n+5
n+8
n+ 11

n+ 13
n+ 16

n+ 14
n+ 17

n+3m- 5

n+ 3m-4
n+3m

n + 3m - 6
n + 3m - 2

n+3m-1

3m + 3 TOTAL RAM BYTES
n = FIRST RAM ADDRESS OF ARRAY

Following is a chart of what a task multiplexer data
structure might look like at a given moment in time:

10

TASKln).PNTR

10
0
0

TASKln).STATUS
1100
1010
1100
1010
1100
0000
1010
1100
0000
1100

TASKln).DELAY

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

·See text.

What information can one ascertain from observation of
the above chart? The ready-to-run high priority tasks, in
order, are 5,1,3. This can be seen by following the high
priority ready linked list from head to tail. The ready-torun low priority tasks, in order are 8, 10. The
TASK(n).PNTR byte=O for the last listed task. Tasks 4,
7, 2 are listed, in order, on the delay list and have
associated delays of 4, 10, 13 ticks respectively. Tasks 6
and 9 are not listed and therefore idle. The' for the
TASK (0) bytes indicate a special condition. There is no
TASKOO allowed and a zero condition is treated as an error condition. TASK(O).PNTR byte is used for the
DELAY$HEAD byte to minimize code in the ACTIVATE$DELAY procedure. TASK(O).STATUS and
TASK(O).DELAY are unused bytes.

DEFINITIONS
NEW$TASK is the number of the task that will be installed on a ready list or the delay list when ACTIVATE$TASK or ACTIVATE$DELAY is called.
NEW$DELAY is the value of the delay that will be installed on the delay list when ACTIVATE$DELAY is
called.
A task is defined as RUNNING if it is in the act of execution or if an interrupt routine is executing which interrupted a RUNNING task.
A task is defined as PREEMPTED if it has been interrupted and a higher priority task is being executed.
A task is defined as READY if it is contained within one
of the ready queues.
A task is defined as IDLE if its BUSY$BIT (bit 7) is not
set, I.e., it is not listed anywhere else. Note that it is
possible to completely disable an IDLE task simply by
setting its BUSY$BIT. In that case, it is not and cannot
be listed anywhere else. This feature is useful during
system integration.

A-71

AP-61
STATE DIAGRAM
The state diagram indicates the relationships among
the possible task states and the procedures involved in
changing states.
The state diagram looks somewhat complic'ated arid a
discussion of the possible change of states is in order.
Assuming a certain existing state, future possible
states will be discussed including the procedures which
can cause the change of state.
From the unlisted (idle) state, the ACTIVATE$TASK pro·
cedure will put the NEW$TASK on either the high priori·
ty ready queue or the low priority ready queue at the tail
end of the queue. The number of the task automatically
assigns the priority and therefore the proper queue. All
task numbers below FIRST$LOW$PRIORITY$TASK are
assumed to be high priority tasks. Also, from the
unlisted state the ACTIVATE$DELAY procedure will put
the NEW$TASK and NEW$DELAY at the proper position
on the delay list.
After a task has been put ,On eWler h'igh priority ready
queue or low priority ready queue it eventually will go to
the RUNNING$TASK state,Jhe DJSPATCH procedure
accomplishell this action. '
'

From the delay list a task can only go to one of the ready
queues. When a task's associated delay goes to zero the
DECREMENT$DELAY procedure calls the ACTI·
VATE$TASK procedure and installs the NEW$TASK on
the proper ready queue.
From the RUNNING$TASK state a task may use the
CASE$TASJ( procedure to put itself on the ready list tail
by setting' NE'W$TASK= RUNNING$TASK. It may
instead put itself on the delay list by setting
NEW$TASK= RUNNING$TASK and also setting
NEW$DELAY equal to something other than zero. Other·
wise, it will progress to the unlis,ted state upon comple·
tion.
The CASE$TASK procedure unlists tasks when they
have completed execution. A low priority RUN·
NING$TASK will go to the preempted state if a high
priority task is on the ready listfollowing an interrupt
during execution of the low priority task if the PREEMPT
procedure is called.
And finally, a PREEMPTED$TASK will return to a RUN·
NING$TASK state wheh all high priority ready task:s
have completed execution. This is accomplished by the
DISPATCH procedure which then returns to the PRE·
EMPT procedure.
'

STATE DIAGRAM

A-72

AP-61
Some lockouts are necessary to avoid chaos in the task
multiplexer. These are as follows:

The unused bits in the STATUS byte are available to the
user.

The BUSY$BIT= 1 in the TASK(n).STATUS byte will
abort the ACTIVATE$TASK and the ACTIVATE$DELAY
procedures and return an indication of the aborting by
setting the STATUS byte equal zero. A task must be
unlisted to be able to be installed on a list.

The TASK(n).DELAY byte is a number which can put
TASK(n) to sleep for up to 255 system clock ticks. The
system clock tick is interrupt driven from the user's
timer and its period is chosen for the particular applica·
tion. A one millisecond timer is popular and assuming
such a time, delays of up to 255 ms are available in the
task multiplexer as it is written. If this delay range is not
wide enough, the user may want to define his
TASK(n).DELAY as a word instead of a byte in the
PLlM·86 declare statement, giving delays of up to 65
seconds from the basic one millisecond clock tick.

A RUNNING$TASK may put itself on a list after it has
executed but it is not allowed to re·list any listed tasks
(i.e., no task may ever be listed twice at the same time!).
A task that tries to activate another task that is already
busy can wait (via the delay feature) for the required task
to complete execution, become idle, and therefore be
available to be activated. A PREEMPTED$TASK may not
be listed. If the ACTIVATE$TASK or ACTIVATE$DELAY
procedure is called and NEW$TASK= PRE·
EMPTED$TASK, the procedure will be aborted and
return with STATUS=O. Otherwise, the STATUS byte is
returned with the new task status.
Only one task may be preempted as there are only two
levels of priority. The user may desire to implement
many levels of priority in which case a linked·list of
preempted tasks could be declared in a structure which
includes the number of the first task in each priority
level group of tasks. This obviously complicates the
PREEMPT and DISPATCH procedures.
The tasks themselves are made into reentrant proce·
dures because of the necessary forward references of
the CASE$TASK procedure.
PLlM·86 allows structures and arrays of structures. The
structure needed for the task multiplexer is a link·list
pointer byte, a task status byte, and a task delay byte.
Each task has an associated pOinter byte, status byte,
and delay byte. These are combined into an array of up
to 255 tasks. For purposes of this discussion, the
number of tasks is chosen as an arbitrary 10, leading to
the following array declaration.
DECLARE TASK(10)STRUCTURE
(PNTR BYTE,STATUS BYTE,DELAY BYTE);
Thus the delay byte associated with task number 7 can
be accessed by using the variable TASK(7).DELAY and
the status of task number 5 can be examined through
the use of TASK(5).STATUS. The TASK(n).PNTR byte
contains the task number of the next listed task on the
same list as TASK(n), i.e., if TASK(n) is on the delay list,
then TASK(n).PNTR will contain the number of the next
task on the delay list or 0 indicating the end of the list.

TASK(n).STATUS is a byte with the following reserved
flags:
BIT
BIT
BIT
BIT

7 BUSY$BIT, "1" IF TASK IS BUSY
6 READY$BIT, "1" IF ON READY LIST
5 DELAY$BIT, "1" IF ON DELAY LIST
4 - BIT 0
UNUSED

LINKED LISTS

Linked lists are useful for a number of reasons.
However, a treatise on linked lists would defeat the pur·
pose of this application note and the reader is referred
to the references listed in the bibliography.
The linked lists used in this application. note have a
head byte associated with each list, i.e., the head byte
contains the number of the first task on the list. The first
task pOinter byte points to the second task on the list,
etc. The pointer of the last task on the list is set at zero
to indicate that it is the last task. Two of the linked lists
are ready queues and require a tail byte as well as a head
byte. The tail byte points to the last entry on the list.
Tasks are put on the bottom, or tail, of the ready lists
and are taken off the top, or head, of the ready lists. The
delay list has no tail but does have a head, called a
DELAY$HEAD. The delay list is not a queue, as delays
are installed on the list in order of delay magnitude for
reasons to be explained later.
There are two ready lists, one for'high priority tasks and
one for low priority tasks. The head and tail pointers
associated with these two lists are: HIGH$PRIORITY$
HEAD, HIGH$PRIORITY$TAIL, LOW$PRIORITY$HEAD,
and LOW$PRIORITY$TAIL. Obviously, the structure can
be expanded to any number of priority levels by expand·
ing the head and tail pOinters and the historical record
of the preempted tasks.

DELAY STRUCTURE

A task multiplexer can have a number of simultaneous
delays active and it would be efficient if there were a
way to keep from decrementing all delays on every clock
tick, which is most time consuming. One way to accom·
plish this feat is to move the problem from the
DECREMENT$DELAY routine to the ACTIVATE$DELAY
routine. The delays are arranged in a linked·list of
ascending sizes such that the value of each delay in·
cludes the sum of all previous delays. This allows the
decrementing of only one delay during each clock tick
interrupt routine. An example will further illuminate this
approach. Suppose the following conditions exist:

A-73

AP-61
Task 7 has a 5 millisecond delay

Interrupts must be disabled whenever the link-lists are
being changed. If interrupts are enabled when this
procedure is called, they should be re-enabled upon
returning.

Task 3 has an 8 millisecond delay
Task 9 has a 14 millisecond delay
The delay structure is arranged so that:

The assignment of priority is a simple matter. A declare
statement, DECLARE FIRST$LOW$PRIORITY$TASK
LITERALLY 'N,' (where N is the actual number of the
first low priority task) indicates to the procedures that
tasks 1 to N are high priority tasks and tasks N or higher
are low priority tasks.

DELAY$HEAD = 07
TASK(7).PNTR = 03
TASK(3).PNTR = 09
TASK(9).PNTR = 00
TASK(7).DELAY=05 (FIRST DELAY = 5)
TASK(3).DELAY= 03 (5+ 3= 8)
TASK(9).DELAY=06 (5+3+6= 14)
The linked-list is arranged so that the delays are in
ascending order and each delay is equal to the sum of
all previous delays up through that point. Since this is
true, all delays are effectively decremented merely by
decrementing the first delay. Of course, something for
nothing is impossible and the speed gained by arranging the delays in the above manner is paid for by the
complexity of the ACTIVATE$DELAY routine. But since
the ACTIVATE$DELAY routine is executed less frequently than the DECREMENT$DELAY routine, the savings in real time is worth the added complexity.
Suppose a new delay is to be activated in the above
scheme. Task 5 with a delay of 10 milliseconds is to be
added. A before and after chart will indicate what the
ACTIVATE$DELA Y procedure must accomplish.
BEFORE
TASK NUMBER
POINTER
DELAY

07

07 ,03

09

03

09

00

05

03

06

AFTER
TASK NUMBER
POINT~R

, DELAY

07
07 03
05

03

05

05"

09@

00

03

02@

04"

09

FIRST POINTER IS THE DELAY$HEAD
CHANGES ARE MARKED WITH AN "
ADDITIONS ARE MARKED WITH AN @
Note that the pOinter before the added task haS changed
and the delay after the added task has changed. The
function of the ACTIVATE$DELAY procedure is to accomplish these changes and additions.
PROCEOVRES
The following procedure explanations, reference the
PLlM-86 source code listing which follows the application note text.
ACTIVATE$TASK Procedure
This procedure is initiated by a call instruction with the
byte NEW$TASK containing the number of the task to
'
be put on the proper ready queue.

This procedure checks the busy bit in the status byte to
see if this particular task is already busy and if so,
returns a STATUS of zero. Otherwise, it returns the new
STATUS of the task. It then checks the priority to see if
this particular task is a high or low priority. If it is high
priority, then the task pOinter pOinted to by the HIGH$
PRIORITY$TAIL pOinter is changed from zero to the
number of the NEW$TASK. The HIGH$PRIORITY$TAIL
pOinter is then changed to the number of the
NEW$TASK and the pOinter associated with NEW$
TASK is made equal to zero. This completes the ACTIVATE$TASK functions. If the new task is a low priority
task, then the same functions are performed using the
LOW$PRIORITY$TAIL pointer.
ACTIVATE$OELAY Procedure,
This procedure is initiated by a call with the byte NEW$
TASK containing the number of the task to be put on the
delay list and the byte NEW$DELAY containing the
value of the associated delay.
Interrupts are disabled and the busy bit of this particular
task is checked. If the busy bit is set the STATUS byte is
set to zero and the procedure returns without activating
the delay. If the busy bit is not set the integer value DIFFERENCE is set equal to the NEW$DELAY value.
POINTER$O ,is set equal to the DELAY$HEAD. POINTER$1 is set to zero. The DO WHILE loop executes, until
POINTER$O equals zero or DIFFERENCE Is less tha'n
zero. Remember that the proper place to insert the new
delay is being searched for, and that will be either at the
end of the list (POINTER$O = 0) or when the sum of the
previous delays do not exceed the new delay value. The
DO WHILE loop has POINTER$O, POINTER$1, OLD$DIFFERENCE, and DIFFERENCE keeping track of where
the procedure is in the loop, while searching for the
proper place to insert the new delay. The existing delays
are sequentially subtracted from the remains of NEW$
DELAY according to the link-listed order until the end of
the list or a negative result is encountered indicating
that the proper delay insertion point has been reached.
At this point POINTER$O contains the task number to be
assigned to TASK(NEW$TASK).PNTR. POINTER$1 contains the task number immediately preceding the
NEW$TASK such that TASK(POINTER$1). PNTR= NEW$
TASK and our link list is fully updated, with the actual
delays yet to go. If POINTER$O = 0 it means that the new
delay is larger than any of the other delays and therefore
should go on the end of the list so TASK(NEW$
TASK).DELAY is set equal to the DIFFERENCE. If

A-74

AP-61
POINTER$O is not equal to zero then if POINTER$O
equals POINTER$1 (indicating that there were not any
delays previously listed), then TASK(POINTER$1).PNTR
is set equal to zero. TASK(NEW$TASK).DELAY is
set equal to the OLD$DIFFERENCE and TASK
(POINTER$O).DELAY is set equal to the negative of DIF·
FERENCE which at this point is negative, thereby
resulting in a positive unsigned number. The reader is
encouraged to implement an example (see Delay Struc·
ture section) to prove that the above approach is valid.
Particular attention should be paid to the contents of
the two pOinters, as they are the key to the procedure.
The final function of this procedure is to set the
BUSY$BIT and DELAY$BIT in the TASK(NEW$
TASK).STATUS byte. The byte named STATUS which is
returned by this procedure is set equal to the status of
the new task. If it is desired to have interrupts enabled,
they must be enabled after the procedure return instruc·
tion. The reason for such a complex method of ac·
tivating a delay will become apparent in the following
section.

DECREMENT$DELAY Procedure

The first delay on the linked·list is decremented and, if it
is zero, the associated task is put on the appropriate
ready queue. The next delay (if any) is checked to see if
it is zero and if so, that task is put on the appropriate
ready queue, etc. A loop is performed until either no
delay or a non·zero delay is found. The procedure then
returns.

It is assumed that this procedure is part of an interrupt
routine and that the interrupts are disabled during its
execution. Interrupts cannot be enabled during changes
to any of the linked·lists or else recovery may not be
possible.

This procedure begins by checking to see if there are
any active delays. If DELAY$HEAD = 0 then this pro·
cedure returns immediately. Otherwise it decrements
the first delay. If this delay goes to zero then the
associated task number is passed to the ACTIVATE$
TASK procedure as the OFF$DELAY byte. A new
DELAY$HEAD is chosen from. the next link·listed delay
and that delay checked for a value of zero which will
happen if the first two or more delays are equal. This
loop is accomplished by the DO WHILE DELAY$
HEAD <> 0 AND TASK(DELAY$HEAD).DELAY = 0; This
procedure is designed to require very little CPU time
unless a delay times out. The DO WHILE loop is by·
passed if the resulting delay value is not zero. A certain
amount of care should be exercised to insure that many
delays do not all time out at the same time. One method
would be to modify the ACTIVATE$DELAY procedure to
insure that there are no zero entries in the delay bytes.
The basic procedure, however, assumes that the clock
"tick" timing will be chosen to minimize the above
potential problem.

CASE$TASK Procedure

This procedure performs the function of calling the task
indicated by the contents of the RUNNING$TASK byte.
All listed tasks are called in this manner. The
CASE$TASK procedure is called by the DISPATCH pro·
cedure. When a particular task has completed execution
it returns to the CASE$TASK procedure which then
resets the BUSY$BIT and the READY$BIT and returns to
the DISPATCH procedure after setting RUNNING$TASK
equal to zero. This procedure allows a task to relist itself
immediately upon returning from execution.

PREEMPT PROCEDURE
The PREEMPT procedure is called whenever it is pos·
sible that a high priority task has been put on the ready
queue while a low priority task was in the process of
execution. An example will illustrate:
Assume that the control system is being interrupted by
the 60 Hz line frequency and a register is being in·
cremented each time this 16.67 ms edge occurs. When
the register gets to 60 (indicating that one second has
passed), the register is zeroed and the high priority time·
keeping task is put on the ready queue. Assume also
that a low priority data logging task was running when
this interrupt occurred. The interrupt routine calls PREEMPT. If a high priority task is running, PREEMPT
simply returns. But in our example, a low priority task is
running so PREEMPT transfers RUNNING$TASK to
PREEMPTED$TASK and calls DISPATCH, which calls
CASE$TASK, which calls the time-keeping task. When
the time-keeping task has completed, it returns to
CASE$TASK which returns to DISPATCH which returns
to the PREEMPT procedure which returns to the interrupt routine which returns to the interrupted low priority
data logging task if no other high priority tasks are on
the ready queue. If the high priority ready queue is not
empty, any and all high priority tasks will be completed
before the interrupted routine is returned to. PREEMPT
refuses to return to the interrupt routine until HIGH$
PRIORITY$HEAD is equal to zero. It is important to note
that a low priority task will not be preempted unless the
PREEMPT procedure is called .. As noted above, it is normally called from the interrupt routine which interrupted
the low priority task, but there is nothing to prohibit
PREEMPT from being called from inside a low priority
task procedure.

DISPATCH PROCEDURE

This procedure calls a high priority task if HIGH$
PRIORITY$HEAD is not equal to zero, restores a preempted task if PREEMPTED$TASK is not equal to zero,
calls a low priority task if LOW$PRIORITY$HEAD is not
equal to zero, and simply returns if there is nothing to
do, all in order of priority. The DISPATCH procedure is
called from the main program loop which must enable
interrupts as DISPATCH disables interrupts as soon as

A-7S

AP-61
it is called. It is alsp called by the PREEMPT procedure.
RUNNING$TASK must be 0 when this procedure is
called.
PL/M·86 PROCEDURES

Because the block structure and levels are so important
to the understanding of the following procedures, they
have been indented according to level. This was a sim·
pie task accomplished by no indenting for level one,
indenting once for level two, etc. The resulting attrac·
tive, easy to follow format was worth the effort to
increase the initial level of understanding for readers of
this application note who are not intimately familiar
with PLiM.
Everything except the very simple main program loop
has been made into procedures. Interrupt routines and
tasks are also procedures. Keeping track of interrupts,
calls, and returns is easy for PLiM and a violation of the
block structure through such devices as GOTO targets
outside the procedure body is the best way the author
knows to crash and burn. Honor the power of the struc·
ture, accept the limitations involved, and checkout and
debugging will be a pleasure.
Since CASE$iASK references the individual tasks, the
task procedure structure was included in the PLlM·86
compilation. All the user has to do is insert the par·
ticular task code in place of the I*TASKnn CODE*I com·
ment, define the interrupt procedures and the system
shoUld be ready to run. Obviously, the user will desire to
change the total number of tasks and the number of the
FIRST$LOW$PRIORITY$TASK.
INITIALIZATION AND THE MAIN LOOP

The last entry in the PLlM·86 program is the initialization
process which essentially zeros the task multiplexer
data and the main loop which loops until TRUE= FALSE,
i.e. forever, with interrupts enabled. The STATUS =
STATUS instruction simply insures that the loop can be
interrupted as the instruction following an ENABLE in·
struction is not interruptible.
These few instructions are included for information only
and will need to be expanded considerably for use in a
real·world system. The task multiplexer procedures
were checked out on an iSBC 86112™ computer running
under random interrupt control and these instructions
were the minimum necessary to cause the system to
run. As was stated earlier, the following source code
does not include any interrupt procedures and these will
have to be generated following the format explained in
the PLlM·86 programming manual.

ADOITIONAL IDEAS

Resource allocation is a feature that could be added to
the task multiplexer. To keep it simple and yet avoid the
deadlock problem (two tasks each grab a resource that
the other needs), an extra array can be added to the
TASK(n).XXX structure in which each bit in the byte (or
word), represents a resource necessary for the execu·
tion of a task. A RESOURCES$STATUS byte can then
keep the dynamic busy status of the system resources
(printers, terminals, floating point math packages, etc.).
When the CASE$TASK procedure is called, the
resources required by the next RUNNING$
TASK can be compared to the RESOURCES$STATUS
byte to see if the required resources are available. If they
are, the following PLlM·86 statement will update the
new status of the resources:
RESOURCES$STATUS = RESOURCES$STATUS OR
TASK(RUNNING$TASK).RESOURCES:

However, if the resources are not available, the CASE$
. TASK procedure can return the task to the ready or delay
list and try again later. When the task has completed,
the following PLlM·86 statement will update the
resources status byte:
RESOURCES$STATUS= RESOURCES$STATUS AND NOT
TASK(RUNNING$TASK).RESOURCES;

Message passing from task to task may also be
necessary. Assuming that a task will have only one
message at a time to deliver or receive, another byte
could be added to the task structure such that
TASK(RUNNING$TASK).MESSAGE could represent a
byte containing the number of the task wishing to
deliver a message to the RUNNING$TASK. Since a task
can call CASE$TASK which in turn will call another task,
message block parameters can be passed directly from
one task to another. The task that calls CASE$TASK
must handle the necessary housekeeping involved in
recovering after the message has been passed. Of
course, the data structure would have to be expanded to
accommodate the message parameters and blocks. For
further ideas involving message handling refer to the
RMXI80™ user's guide.
Two additional relatively simple procedures could be
added to obtain the SUSPEND and RESUME features of
the RMXI80™ system. Remember that if the BUSY$BIT
is set in a TASK(n).STATUS byte and the task is unlisted,
then it cannot be listed. If it is desired to dynamically
enable and disable a task, this bit could be set by a
SUSPEND procedure and reset by the RESUME pro·
cedure.

A-76

AP-61
SOURCE CODE

'rM86:DO;
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

TOTAL$TASKS LITERALLY '10';
TRUE LITERALLY '0FFH';
FALSE LITERALLY '0';
BUSY$BIT LITERALLY '10000000B';
READ~$BIT LITERALLY '010000008';
DELAY$BIT LITERALLY '00100000B';
FIRST$LOW$PRIORIT~$TASK LITERALLY '6';

DECLARE
DECLARE
DECLARE
DECLARE

TASK(TOTAL$TASKS) STRUCTURE(PNTR BYTE, STATUS BYTE, DELAY BYTE);
HIGH$PRIORITY$HEAD BYTE, HIGH$PRIORITY$TAIL BYTE;
LOW$PRIORITY$HEAD BY'rE, LOW$PRIORI'rY$'rAIL BYTE;
RUNNING$'rApK BYTE, PREEI"'lPTED$TASK BYTE;
DEC~ARE STATUS BYTE, NEW$TASK BYTE, NEW$DELAY BYTE;
DECLARE DELA~$HEAD 8 YT E A'r (@TASK (0) • PN'fR) ;

ACTIVATE$TASK: PROCEDURE; /* ASSUMES NEW$TASK<>0 */
DISABLE;
IF (TASK(NEW$TASK) .STATUS AND BUSY$BIT)<>0 THEN STATUS=0;
ELSE /* SINCE TASK IS NOT BUSY */ DO;
IF NEW$TASK < FIRST$LOW$PRIORITY$TASK THEN DO;
IF HIGH$PRIORITY$TAIL<>0 THEN DO;
TASK (HIGH$PRIORITY$TAIL) .PNTR=NEW$TASK;
END;
ELSE /* SINCE HIGH$PRIORITY$TAIL=0 THEN */ DO;
HIGH$PRIORITY$HEAD=NEW$TASK;
END;
HIGH$PRIORITY$TAIL=NEW$TASK;
END;
ELSE /* SINCE TASK IS LOW PRIORITY THEN */ DO;
If LOW$PRIORITY$TAIL<>0 THEN DO;
TASK (LOW$PRIORITY$'rAIL) • PN'fR=NEW$TASK;
END;
ELSE /* SINCE LOW$PRIORITY$TAIL=0 THEN */ DO;
LOW$PRIORITY$HEAD=NEW$TASK;
END;
LOW$PRIORITY$TAIL=NEW$TASK;
END;
TASK (NEW$TASK) .PNTR=0;
TASK(NEW$TASK) .STATUS=TASK(NEW$TASK) .STATUS OR
BUSY$BIT OR READY$BIT;
STATUS=TASK(NEW$TASK) .STATUS;
END;
NEW$TASK=0;
RE'rURN ;
END ACTIVATE$TASK;

A-77

AP-61
ACTIVATE$DELAY: PROCEDURE;/*ASSUMES NEW$TASK, NEW$DELAY<>0*/
DECLARE POHI'rER$0 BYTE, POINrER$l BY'rE;
DECLARE OLD$DIFFERENCE INTEGER, DIFFERENCE INTEGER;
DISABLE;
IF (TASK(NEW$TASK) .STATUS AND aUSY$BIT)<>0 THEN STATUS=0;
ELSE /* SINCE TASK IS NOT BUSY */ DO;
DIFFERENCE=INT(NEW$DELAY) ;
POINTER$0=DELAY$HEAD;
POINTER$1=0;
DO wHILE POINTER$0<>0 AND DIFfERENCE>0;
OLD$DIffERENCE=DIFFERENCE;
DIFfERENCE=DIFFERENCE-INT(TASK(POINTER$0) .DELAY) ;
If DIfFERENCE>0 THEN DO;
POINTER$1=POINTER$0;
POINTER$0=TASK(POINTER$1) .PNTR;
END;
END;
TASK(NEW$TASK) .PNTR=POINTER$0;
TASK(POINTER$l) .PNTR=NEW$TASK;
IF POINTER$0=0 THEN TASK (NEW$TASK) .DELAY=LOW(UNSIGN(DIFFERENCE));
ELSE /* SINCE DIFfERENCE<0 THEN */ DO;
IF POINTER$0=POINTER$1 THEN TASK(POINTER$l) .PNTR=0;
TASK(NEW$TASK) .DELAY=LOw(UNSIGN(OLD$DIFFERENCE));
TASK(POINTER$0) .DELAY=LOW(UNSIGN(-DIFFERENCE));
END;
TASK(NEW$TASK) .STATUS=TASK(NEW$TASK) .STATUS OR
BUSY$BIT OR DELAY$BIT;
STATUS=TASK(NEW$TASK) .STATUS;
END;
NEW$'rASK=0 ;
NEW$DELAY=0;
RETURN;
END ACTIVATE$DELAY;
DECREMENT$DELAY: PROCEDURE;
/* ASSUMES INTERRUPTS DISABLED */
DECLARE OFF$DELAY BYTE;
IF DELAY$HEAD<>0 THEN DO;
TASK (DELAY$HEAD) • DELAy='rASK (DELAY$HEAD) • DELAY-l;
DO WHILE DELAY$HEAO<>0 AND TASK(OELAY$HEAO) .DELAY=0;
OFF$DELAY=DELAY$HEAD;
DELAY$HEAD=TASK(DELAY$HEAD) .PNTR;
TASK (OFF$DELAY) .STATUS=TASK(OFF$DELAY) .STATUS
AND NOT(BUSY$BIT OR DELAY$BIT);
NEW$TASK=OFf$DELAY;
CALL ACTIVATE$TASK;
END;
END;
RETURN;
END DECREMENT$DELAY;

A-78

AP-61
CASE$TASK: PROCEDURE REENTRANT;
DO CASE RUNNING$TASK;
CALL 'rASK00;
CALL 'rASK01;
CALL 'rASK02;
CALL TASK0j;
CALL TASK04;
CALL 'rASK05;
CALL 'rASK06;
CALL TASK07;
CALL'rASK08;
CALL TASK09;
END;
TASK (RUNNING$TASK) .STATUS=TASK(RUNNING$TASK) .STATUS AND
NOT (BUSY$8IT OR READY$BIT);
TASK (RUNNING$TASK) .PNTR=0;
IF RUNNING$TASK=NEW$TASK THEN 00;
IF NEW$DELAY<>0 THEN DO;
CALL ACTIVATE$DELAY;
END;
ELSE /* SINCE NEW$DELAY=0 */ DO;
CALL ACTIVATE$TASK;
END;
END;
RUNNING$'rASK=0 ;
RETURN ;
END CASE$TASK;
REENTRANT; /* ASSUMES INTERRUPTS DISABLED */
IF PREEMPTED$TASK=0 THEN DO;
IF (HIGH$PRIORITY$HEAD<>0) AND (RUNNING$TASK>=
FIRST$LOW$PRIORITY$TASK) THEN DO;
PREEMPTED$TASK=RUNNING$TASK;
RUNNING$TASK=0;
DO WHILE PREEMPTED$TASK<>0;
CALL DISPATCH;
END;
END;
END;
RETURN ;
END PREEMPT;

PREE~PT:PROCEDURE

A-79

AP~1

DISPATCH:PROCEDURE REENTRANT, /* ASSUMES RUNNING$TASK=0 */
DISABLE,
IF HIGH$PRIORITY$HEAD<>0 THEN DO,
RUNNING$TASK=HIGH$PRIORITY$HEAD,
dIGH$PRIORITY$HEAD=TASK(RUNNING$TASK) .PNTR,
IF HIGH$PRIORITY$HEAD = 0 THEN HIGH$PRIORITY$TAIL
0,
CALL CASE$TASK,
END,
ELSE IF PREEMPTED$TASK<>0 THEN DO,
RUNNING$TASK=PREEMPTED$TASK,
PREEMPTED$TASK=0,
END,
ELSE IF LOW$PRIORITY$HEAD<>0 THEN DO,
RUNNING$TASK=LOW$PRIORITY$HEAD,
LOW$PRIORITY$HEAD=TASK(RUNNING$TASK) .PNTR,
IF LOW$PRIORITY$HEAD = 0 THEN LOW$PRIORITY$TAIL
0,
CALL CASE$TASK,
END,
ELSE RETURN,
RETURN,
END DISPATCH,

A~O

AP-61
TASK00: PROCEDURE REENTRANT;/*ERROR CODE*/RETURN;END TASK00;
TASK01: PROCEDURE REENTRANT;
ENABLE;
/*'rASK01 CODE*/
DISABLE;
RE'rURN;
END TASK01;
TASK02: PROCEDURE REENTRANT;
ENABLE;
/*'rASK02 CODE*/
DISABLE;
RE'rURN ;
END 'rASK0 2;
TASK01: PROCEDURE REENTRANT;
ENABLE;
/*TASK01 CODE*/
DISABLE;
RE'rURN ;
END 'rASK01;
'rASK04: PROCEDURE REENTRANT;
ENABLE;
/*'rASK04 CODE*/
DISABLE;
RETURN ;
END 'rASK04;
TASK05: PROCEDURE REENTRANT;
ENABLE;
/*'rASK05 CODE*/
DISABLE;
RE'rURN;
END 'rASK05;
TASK06: PROCEDURE REENTRANT;
eNABLE;
/*'rASK06 CODE*/
DISABLE;
RE'rURN ;
END TASK06;
TASK07: PROCEDURE REENTRANT;
ENABLE;
/*'rASK07 CODE* /
DISABLE;
RETURN ;
END TASK07;

A-Sl

AP-61
TASK08: PROCEDURE REENTRANT;
ENABLE;
/*rASK08 CODE*/
DISABLE;
RE'rURN ;
END TASK08;
'rASK09: PROCEDURE REENTRAN'r;
ENABLE;
/*'rASK09 CODE*/
DISABLE;
RETURN;
END 'rASK09;
/ * I NI 'r I AL I Z E * /
DISABLE;
TO 9;
TASK(STATUS).PNTR=0;
TASK(STATUS) .STATUS=0;
TASK(STATUS) .DELAY=0;
NEW$TASK,NEW$DELAY=0;
HIGH$PRIORITY$HEAD,HIGH$PRIORITY$TAIL=0;
LOW$PRIORITY$HEAD,LOW$PRIORITY$TAIL=0;
RUNNING$TASK,PREEMPTED$TASK=0;
END;

DO STATUS=0

/* MAIN LOOP */
DO WHILE TRUE<>FALSE;
CALL DISPA'rCH;
ENABLE;
STA'rUS=STA'rUS;
END;

END TM86;

A-82

AP·61
REFERENCES
1. Hansen, Brinch, Operating System Principles, Prentice-Hall, Englewood, N.J., 1973.
2. Knuth, D. E., The Art of Computer Programming, Addison-Wesley, Reading, Mass., 1969.
3. Wirth, Nicklaus, Algorithms + Data Structures = Programs, Prentice-Hall, Englewood, N.J., 1976.
4. "PLlM-86 Programming Manual," Intel Corporation, 1978, manual order number 9800466A.
5. "RMX/80 User's Guide," Intel Corporation, 1977, manual order number 9800522B.

A83/ A84

inter

APPLICATION
NOTE

Ap·50

September 1979

© Intel Corporation, 1979

A-85

AP-50

Debugging Stragegies
and Considerations for
8089 Systems

Contents
INTRODUCTION
STATIC (OR FUNCTIONAL) DEBUGGING

Hardware Testing
External Processor Interface
Software Testing
REAL·TIME TESTING

Logic Analyzer Techniques
A REVIEW OF lOP OPERATION

Task Execution
Going from Instruction Execution into DMA
DMA Termination
Priorities/Dual Channel Operation
SUMMARY
Appendix I. CHECKLIST OF
POSSIBLE PROBLEMS
Appendix II. BREAKPOINT ROUTINE
AND CONTROL PROGRAM

Our thanks to John Atwood and Dave Ferguson, the authors cif this
note. Both John and Dave are members of Intel's 8089 design
engineering group. Please direct any questions you may, have to
your local Intel FAE (field application engineer) or to MPO
Marketing at Intel, Santa Clara.

A-86

AP-50
INTRODUCTION
The Intel 8089 is the first integrated 110 processor
available. This 1/0 processor (lOP) makes available the
power of 1/0 channels, as used in mainframes and minicomputers, in a microcomputer form. Designed as part
of the MCS-86™ family, the lOP can be interfaced with
the MCS-80™ and MCS-85™ families as well.

An aid to debugging any system is a clean, well organized system deSign. The 8089 lends itself to structured,
modular software interfaces to the host CPU, via the
linked-list initialization structure, and parameter communication through the parameter block (PB) area.
Some of the aspects of structured programming that aid
debugging are:
• Top Down Programming - The functions done by
lOW-level routines are well understood, and the
number of program .fixes, which can cause more
errors, is minimized.

An 110 channel Is basically a processor remote from the
main CPU, which independently runs 1/0 operations
upon command of the CPU. To relate the 8089 to existing LSI components, it is similar to a microprocessor
that is time-multiplexed with a DMA controller, but with
two channels available. However, since the 8089 processor is optimized for 110 and multiprocessor operations, and the DMA has been made much more flexible
than existing DMA controllers, a truly general purpose
and powerful 110 control system is available on one chip.
Due to the uniqueness of the 8089, this application note
was written to review debugging strategies and point
out possible pitfalls when developing an lOP system.
Debugging an lOP system is very similar to debugging
mlcroprocessor/DMA controller systems, and many of
the techniques described here are standard microprocessor techniques. However, several factors are present
which can complicate the debugging process:

• Program Modularity - Small, easy to manage subprograms can be debugged independently, increasing the chance that the entire system will work the
first time.
• Modular Remoteness - By having all program
modules communicate only through a well-defined
interface, one module's knowledge of the "inner
workings" of another is minimized. System software complexity is reduced. Updates to program
modules are more reliable, too.
Two major areas of debugging will be outlined here static (or functional) debugging in which the hardware
and software are not tested in a real-time environment,
and real-time debugging. Applying a logic analyzer to
lOP debugging will also be explained, and a review of
lOP operation and potential problems will be done.

1. Multiprocessor Operation
Although usable by itself, the lOP Is designed to be
used with other processors. All factors normally encountered with multiprocessor operation, including bus
arbitration, processor communication, critical code sections, etc., must be addressed in the design and debug
of an lOP system.
2. DMA Tle·in to lOP Program Execution
The relationship between lOP program execution and
DMA transfers and termination is different from earlier
DMA controllers and should be fully understood to properly run the system.
3. Dependency of Programs on Real-Time 1/0
Operations
Requirements by 1/0 devices for maximum data rates
and minimum latency times force the software programmer to be aware of hardware timing constraints and can
complicate program debugging.

STATIC (OR FUNCTIONAL) DEBUGGING
The predominant errors in a system, when first tried out,
are, either errors In implementation (I.e., wrong hookups
or coding errors), or an Incorrect implementation (a
wrong assumption somewhere). Most of these bugs can
be found through static debugging techniques that are
usually easier to work with than real-time testing.
Hardware Testing
Static hardware testing Is done mainly to see if all individual parts of the system work, so the whole system
will "play" when run. The level of testing can run from
checking for continuity and shorts (which finds only
hookup errors) to trying to move data around and running 1/0 devices from a monitor or special test programs
(which can also find Incorrect circuit design). In all but
the simplest systems, the latter approach is recommended since It is a step towards software debugging.

Related to multiprocessor operation and real-time
dependencies, the two independent channels available
on the 8089 may have to be coordinated with each other
to make the whole system function. Dependence of one
channel on the other can also complicate debugging.

Several approaches to hardware testing will be covered.
Running diagnostic programs (such as a monitor) out of
the lOP's host system, in both the LOCAL and REMOTE
modes, will be covered. The case where the host system
cannot support diagnostic software and must have an
external processor to exercise the lOP and its peripherals will also be explained.

Due to the complexities of running in a real-time environment, as many steps as possible should be taken to
facilitate debugging. A major help here Is to make sure
as much of the hardware and software as possible is
working before running real-time tasks. This Is a good
practice anyway, but It should be reemphasized that a
complex multichannel system can quickly get out of
hand If more than a few things are not right.

The case where the host system can run diagnostics or
test programs that have interactive user 1/0, such as a
CRT terminal or teletype, provides the most straightforward way to test the lOP. Naturally, before these programs can be run, the baSic hardware must be correct
enough to run programs. When this point is reached, a
monitor program can be used to exercise memory and
1/0 controllers on the system bus.

4. Dual Channel Operation

A-87

AP·50
It should be mentioned that aids, other than just testing
with software, are helpful for hardware debugging.
While a necessity for real.time debugging, a logic
analyzer is also a definite help for static hardware
debugging. Its main use in hardware debugging is show·
Ing timing relationships between address or data paths
and other signals. It is especially useful for functional
software debugging, to be described shortly. The last
debugging section outlines the use of an analyzer with
the lOP. Of course, an oscilloscope, logic probes and
pulsers, etc., can be used to trac!, out specific logic or
.
timing problems.
LOCAL Mode

REMOTE Mode

From a system 'design standpOint, running the lOP in
the REMOTE Mode is advantageous In that It removes
the I/O bus cycles from the system bus. Normally, the
remote I/O Is not accessible to the host, CPU. Until the
lOP is able to run its own test programs to transfer data
from the REMOTE bus to the system bus, I/O controllers
and memory on the REMOTE bus will be invisible to the
hO-!lt. To get around this problem during prototyplng,
either an external processor interface can be used (see
next section), or a temporary bypass can be made to ac·
cess the REMOTE bus from the system bus.
Bypassing the normal REMOTE/SYSTEM interface is a
handy technique for doing preliminary debugging on the
REMOTE bus. This can be done by memory·mapping the
lOP's I/O space into an unused portion of the host
CPU's system memory space. When accessing this
space, the lOP access to its own I/O space is disabled,
and a separate set of address buffers, transceivers and
bus control signal buffers are enabled. Reads and writes
can then be done to the formerly Inaccessible REMOTE
bus by the host CPU.

When the lOP is run'ning in the LOCAL Mode, all 1/0 con·
trollers and memory are accessible by the host or con·
trolling CPU. Thus a standard monitor, such as the one
supplied with the SDK-86 or available for the ISSC·
86112™ development kit, can exercise all hardware on
the bus.' The breakpoint routines, however, will not
work due to the different instruction set. The 8086 or
8088 Is best suited for running the lOP in the LOCAL
mode due to Identical status lines and bus timing, as
well as the Request/Grant line, which eliminates bus ar·
bitration hardware. Figure 1 shows the general LOCAL
mode configuration.

A simple system (Figure 2) implements this bypassing
scheme. It was designed for just forCing or examining
devices on the REMOTE bus and may not read or write
correctly if the lOP is simultaneously trying to do bus
cycles. A more sophisticated arbitration system would
permit reliable run·time checking also.

'The SDK·86 serial monitor Is a good basis for a general 8086 monl.tor.
The lOP cannot be used directly with the SDK·86, since the 8086 Is run·
nlng In the minimum mode. The SDK-86 can be converted t.o run In the
maximum mode, If desired.

SYSTEM BUS

~
~

8284
CLOCK (lENERATOR

ADo·AD"

A'I-A'1
8086

READY RESET ClK
ClK

11

1\1

lOCAL BUS

r--v.l\

3 x 8282
lATCH

CPU

IAO-19"

1;1-

r---v Ir

PROM

so-S2 !--f!-

RESET
READY

~

RQIGii'i'

~

IV'

RQf(lRT

ADo-AD'5
AiS- A'1

ClK
RESET
READY

8089
lOP

2 x 8286
TRANS,

11

~DO-15

;U\
~ ,\rY

RAM

,lolJI"Ij"C

\I

so-S2

SO-s.

8288
BUS
CONTROllER

a

aQ ~
ClK

, iiIWfC

,AiolWl:,

,1l!I!DC

lft...t\
In

SERIAL

j---T-

110
(8251)

I~

~

~

110
PERIPHERAL

J

I

CONSOLE 110
TO RUN TEST
PRO~RAMS

Figure 1. Generalized LOCAL Conflgurallon-8086 In Max Mode

A-88

AP-50

8086 OR 8088
(HOST CPU)

SYSTEM

I

ADDR:~~ )~____________~________________~________~____________~________________~
SYSTEM (

DATABUS))--______________~----------------~-----------------------~--------~----~
SYSTEM ~---------------'-------------------"-----------'---------------'------------'-----_(

CONTROL~----------------~--------------~------~--------------~--~----~----~
BUS

r------

lOP DISABLE

I
I
I

-l

I

~~~T~~ TO

I/:~~ESS

I
I
I
L
________ :.JI

LOGIC

I

I-I-================================j ~~DRESS
BUS

1--------------------'-------'------( 1/0 DATA

1----------------------------------4 BUS
1/0

L -__________________~L-____' - -____________________---J______________ CONTROL

BUS

Figure 2. Remote Mode Bypass for Debugging

Running the lOP in the REMOTE mode, particularly if
the MULTIBUS™ protocol is adhered to, has the advan·
tage that the lOP can be exercised with any MULTlBUS·
compatible processor. If the main processor is not
amenable to being used as a debugging tool, another
processor could be used to debug the hardware inter·
face. If the microprocessor is of the same type as the
intended host processor, software debugging can be
done as well. A generalized REMOTE mode configura·
tion using the MULTI BUS is shown in Figure 3.
External Processor Interface
A technique that can be used if the host processor can·
not run any debugging or monitor.routines is to have an
external processor tie into the host processor's bus.
This is useful if the main system CPU cannot run an in·
teractive monitor or other debugging programs. If a
MULTIBUS interface is being used, an 8289 bus arbiter
and a set of address/data/control buffers can be used. A
somewhat simpler system, similar to the remote bus ac·
cess system mentioned above, could be used for static
debugging of non·MULTlBUS systems. Again, if true bus
arbitration is added (which brings us nearly to a MULTI·
BUS interface), it could also be used for run·time
testing. Intel processors that have the MUL TlBUS
interface include the iSBC·80/20™, iSBC·86/12™, iSBC·

80/10™, iSBC·80/05™, the Intellec'" development
systems, among others.
In the previously described systems, the external proc·
essor would disable the host CPU's access to the bus,
either by some form of bus request or by a "brute force"
disabling of the CPU's buffers. In the latter case, the ex·
ternal processor could only control the bus during a
time that the CPU is halted, without destroying the pro·
gram flow. Mapping the processor's memory space into
the external processor memory space is the simplest
method, but can impact programs being run on the
external processor. If the processor under test utilizes
the MULTIBUS interface (with bus arbitration), then a
processor like the iSBC·80/30™ or iSBC·86/12™ could
be used as the debug vehicle with no special hardware.
A more flexible interface that would have less impact on
the system memory space would have the addresses for
the system under test generated from latches loaded by
the I/O instructions from the external processor. This
case must have software routines to interface to the I/O
ports and handle the desired debugging routines (see
Figure 4).
Software Testing
It is desirable to check as much of the lOP program as
possible statically, since various tools and techniques
are available which may not be usable during real·time

A-89

Ap·50

HOST CPU

MULTI BUS

CONTROL--SIGNALS

Figure 3. Generalized Remote Bus Using MULTI BUS Interface

HIGH ORDER
ADDRESS LINES
ADDRESS OATA
CNTL
BUS
BUS SIGNALS

ADDRESS -

LOW ORDER
ADDRESS
LINES

.....- - - j H - I

16-20 BITS

THESE BUFFERS ENABLED WHEN SYSTEM
UNDER TEST'S BUFFERS DISABLED ~

CNTL

-----"-'~-I

-t>-

....,.-+_1

I--"M"U"'L"'TI"'B"US=-.=.C.=O"N"'TR"'O"'Lo.,L=I"N=ES'---!'-_ _ _

EXTERNAL PROCESSOR
SYSTEM UNDER TEST'S MEMORY Is MAPPED
INTO EXTERNAL PRO,CESSOR'S MEMORY.
UPPER ADDRESS BITS CAN BE SUPPLIED
FROM 110 LATCH.

SYSTEM UNDER TEST

Figure 4. External Processor Interface

A-90

AP·50
testing. This "static" software testing is not applicable
to heavily I/O-dependent or DMA-dependent routines,
but Is best suited to longer computational or data handling routines. The Idea Is to test the correctness of
algorithms, rather than seeing if the whole system runs.
There are two main approaches to functional software
testing. One is to essentially run the program In real
time and monitor program flow on a logic analyzer. The
difference between this and real-time testing Is that pro·
gram subsections can be tested separately by using different TP (Task POinter) starting addresses. If It is
necessary to set up certain registers or parameters in
memory, a small "setup" program can be run afterinitialization, which can load up registers or memory, then
jump to the program section desired.
Another technique is to run the programs with breakpoint routines so that one can step through code
segments and follow program execution. Software
breakpOints are usually implemented by inserting a
jump or restart to a monitor routine at the breakpoint
l'Ocatlon. This jump or restart is machine language
dependent so, unfortunately, the existing breakpoint
routines within monitors for the 8080 or 8086 are not
applicable.
New routines tailored to the 8089 can be used, and, if
done properly, can even be used to examine programs
running on a REMOTE bus. Using breakpOints is somewhat complicated on the 8089 because the minimum Instruction length is two bytes. There is no absolute CALL
instruction, only a relative one (which would have to
have its displacement recalculated each time it was
used). But, with a several-byte absolute jump inserted at
each place a breakpoint is desired, full breakpoint
capabilities can be obtained.
There are many ways the breakpOints can be implemented. When a breakpoint is reached, the 8089 itself
could output the machine state to a console through Its
own routines. Better suited to debugging, though, is a
system that has the 8089 place its machine state in
memory, alert the host processor, and then halt. The
host then picks up the 8089's state and can treat it in the
same way it runs its own breakpoint routines. Since the
host processor is more likely to be running a monitor or
some other kind of debugging routine (and most likely
has at least temporary console 1/0), it is the logical system to initiate and examine 8089 breakpOints. If the lOP
is running in the REMOTE mode, and the host processor
has access to the 1/0 bus via the scheme mentioned In
the hardware debugging section, then lOP programs
running on the REMOTE bus can be examined.
The breakpoint itself can consist of an escape sequence
that is used to save the TP value and jump to the save
routine, or just a jump to the save routine. This routine
saves all register contents for the channel the breakpoint is in, signals the host processor, and stops the
lOP. All user programmable registers (GA, GB, GC, IX,
MC, BC, TP), as well as the pointer tags, are accessible.
The PP (Parameter Pointer) and PSW are not normally
accessible, but if the generation of the CA Is such that
the lOP can send Itself a CA, then by sending a CA
HALT, the PSW will appear at PP + 3. Remember that

since the lOP doesn't have arithmetic or logical condition codes, the PSW is not as Important as in other
machines.
The most straightforward way to pass data from the lOP
to the host processor is through the PB (Parameter
Block) area since the PP will normally remain relatively
fixed throughout the lOP program. In order not to in·
fringe on the PB areas used by the programs, an area 18
bytes long should be allocated at the end of the PB
block to hold the register contents. Using other areas to
store the register data requires saving and reloading a
pOinter register as part of the breakpOint escape
sequence.
The data returned from the breakpoint save routine will
appear to the host processor as a sequential block of
data in the PB area. Sixteen-bit data can easily be ex·
tracted, but 20-bit pointer data will have to be
reconstructed from the move pOinter (MOVP) format:
7

:~~~:~

07

!D19...D1S!rOO!

07
D15•••DB

D7••• DO

I

LOWEST
ADDRESS

TAG BIT
O=SYSTEM

1mUO

Several means are available to signal the host processor
that a breakpoint has been reached. A bit could be set In
memory or an interrupt sent to the CPU. The best way,
though, is to use the BUSY flag (at CP + 1 or CP + 9).
After starting the lOP, the BUSY flag is set to FF. When
a breakpoint is reached, the lOP performs its save
routine and does either a software or CA HALT. These
result in clearing the BUSY flag, which then signals the
CPU to obtain valid breakpoint data. The CPU can then
restart the lOP by either a CA START or CA CONTINUE.
The breakpoint routine outlined above will work for a
"one-shot" test. However, to be more useful as a
general purpose debugging tool, some refinements
must be added. To keep from destroying the program
whenever a breakpoint is placed, the supervisory program running from the host processor must save the
lOP code that is occupied by the escape sequence.
When the breakpoint is completed and lOP execution is
to resume, the host program restores the lOP code, sets
the TP in the CB area back to where the breakpoint was
placed, and sends a CA START. Since the length of each
instruction can be easily found from bits 1-4 of the opcode, a single stepping function can also be done.· By
the time this is implemented, the host program is
becoming a full·fledged debugging routine. Appendix 3
describes a debugging program that makes use of the
ideas presented here.
BreakpOint routines can be quite useful, but some
restrictions and limitations should be mentioned. The
processor examining the breakpOints must have access
to the lOP program memory, either directly, or through
lOP programs that simulate direct access. The program
memory must be in RAM. The breakpoint must be
"The formula for length of instructions Is: length (In bytes) = 2+ 1 (If bits
1.0=01)+ 1 (If bits 3,2=01) + 2 (if bit 3= 1)+2 (If LPDI).

A-91

AP-50
placed on an instruction boundary, and multiple breakpOints must not be placed so that they overlap. There
may be some impact on the PB area. CA generation may
have to be different than usual. But, despite these
limitations, the breakpoints offer a useful and more conventional software debugging tool than analyzers.

test for data rate problems, run the system clock at its
lowest expected frequency and use memory and 110
with maximum expected wait states. Identify the
tightest program timings and try to have these sections
cOincide with worst case DMA or other heavy bus utilization (see dual channel operation later). Critical section
problems can occur when two independent processors
communicate with each other with improper "handshaking." This can result in one processor missing another's
message, or even having both processors hang up,
waiting for each other to go ahead. The 8089 provides
aids to these problems, including the TSL instruction (to
implement semaphores) and the BUSY flag. However,
any interprocessor communication (including one channel of the lOP to the other) should be checked. Beware
of cases when one processor is running considerably
slower than the other (due to DMA overhead or chained
instruction sequences).

REAL-TIME TESTING
Running an lOP program in its final environment with
real 1/0 devices is the true test of dynamic operation.
The program is no longer in a static, isolated environment. The demands of DMA and multiprocessing may
reveal unplanned timing dependencies or critical section problems. There may also be sections of hardware
or software, which couldn't be tested statically, that
may have bugs. The whole purpose of static or functional testing is to dig these problems out while convenient debugging tools can be used. Since there are no
simple techniques for real-time debugging, the use of a
logic state analyzer and techniques to fully understand
the lOP's real-time operation will be emphasized.

The techniques for real-time debugging evolve from
functional testing using a logic analyzer. For all but the
simplest systems, an analyzer is essential, since it can
graphically show program execution and timing relationships during real-time execution. Another aid is a
delayed oscilloscope. Triggering the scope from the
logic analyzer, the delay can be adjusted so that any
signal in the system can be monitored.

Multiprocessing operations and real-time asynchronous
110 requests can cause the timing complexity of the
system as a whole to rise beyond the point of complete
comprehension by an individual. It is then essential that
techniques to ensure correctness are used. These include good design methods, especially a clean, wellstructured design, as well as good testing. A thorough
test requires the attitude that the system should be
tested for failures, rather than tested for correctness. In
other words, one should try to make the system fail,
tests should be chosen that will put the worst stress on
critical timing areas.

To facilitate the use of the logic analyzer, especially if
its memory is not very deep or when using it to trigger
an OSCilloscope, a repetitive system can be used to continually update the display. Using a repetitive reset
helps to debug the software-hardware interface, since
oscilloscope or logic analyzer probes can be readily
moved around the circuit to observe new Signals
without manually retriggering the display. At its
simplest, the reset to the host processor can be strobed, say every 10 ms. The processor will then provide the
two channel attentions (CAs) that are needed to initialize the lOP. Where this isn't feasible, the CAs can be
externally forced by either a string of one-shots or a simple processor with timing loops (such as a SDK-85 or
SDK-86). See Figure 5 for initialization timing.

The best way to do this is to write a diagnostic program
that puts the CPU, lOP, and 110 devices through the
worst conceivable timing and program combinations.
Ideally, the program should be self-checking so that it
can be run without supervision, printing any data or program errors that occur, much like a memory test.
The two main real-time problem areas are insufficient
data rates or latency, and critical section problems. To

,:-~50MS-­

L_______ ~~4 CK-I-~1CK---'I
RESET

IF FIRST

IRESET AFTER

/

;:..150CK*-

I

_ __ I ~O_W_E~ __Uf_/
-;::.1CK-

CA

SLAVE-~r

INITIALIZE
___ '\

,<-'

_\....._ _ _ _

SEL_-7-_ _ _ _ _ _ _ _

POWER
,ON

,-

MASTER-7 - ROIGRT MODE
'LONGER IF WAIT STATES

Figure 5. Initialization Input Sequence

A-92

START CH2
,.._ _ _ _ _ _ __

~I

AP-50
BUS
CYCLE

Memory protection of the lOP and system programs is
helpful when debugging OMA operation. It is quite easy
for runaway OMA to wipe out memory. Another precau·
tion to avoid this problem is to set an upper limit on the
number of bytes transferred by always specifying a byte
count termination.

In the absence of other powerful debugging systems,
the logic analyzer has shown to be an extremely useful
tool. Because of its importance in debugging an lOP
system, some basic techniques and observations that
relate to monitoring lOP operation will be reviewed here.
The particular brand or type of analyzer used is not too
important, but would be desirable to have the following
features:

xxxx

111

IDLE STATUS

F010

10 1

2O·BIT ADDRESS

T2

E ~FFF

101

LOWER STATUS = MEMORY DATA READ

T3

E

A A 50

111

16-BIT DATA RETURNED=AA50

T4

t

F 010

111

ADDRESS REMAINS IN CHIP OUTPUT
LATCH AFTER END OF BUS CYCLE

E

=FF010.

DATA NOT READY YET
UPPER STATUS INDICATES: NON·DMA. CH1

As mentioned earlier, on a 16·bit bus, most instructions
starting on odd addresses won't show the first fetch,
since the internal queue is in use. It is a good idea in
that case to use only even instruction boundaries as
trigger words. When following dual channel operation,
one should keep an eye on the upper status bits (S3-S6),
since S3 indicates which channel is running (0 =CH1,
1 =CH2), and S4 indicates DMA/non·DMA transfer
(0 = OM A, 1 = non·OMA).

At least a 24·bit data width
Flexible triggering and qualification control
Display after triggering on a sequence of states
Capability for hexadecimal data display

A REVIEW OF lOP OPERATION
(With things to look out for)
When trying to get an unfamiliar system going for the
first time, it is too easy to stumble on apparent prob·
lems that are really just unexpected operation modes or
peculiarities of the machine. For this reason the basic
principles of lOP operation will be reviewed here with
special emphasis on possible problem areas or pitfalls
that a user might encounter when debugging a 8089 sys·
tem. The topics are covered generally in the order en·
countered when bringing up a system. For complete
details of operation and some design examples, see the
8086 Family User's. Manual.

It is best to hook up to the address/data lines at the lOP,
as opposed to looking at the separate address and data
lines, since 39 lines would be required just to look at ad·
dress, data and status lines. The three lower status lines
should be monitored to show the type of bus cycle be·
ing run. Other lines can be connected where needed, at
places like the ORQ lines, the EXT lines or other lines
related to the system.
For general purpose debugging, triggering the analyzer
on the rising edge of the lOP clock shows the most
useful data concerning bus cycles. Of course, using the
falling edge may be necessary to check certain signals,
particularly ones that are active only while the clock is
low. The following discussion is based on sampling
data on the clock's rising edge.

RESET
RESET must be active (HIGH) for at least four clocks in
order to fully initialize all internal circuitry. On power up,
RESET should be held high for at least 50 microsec·
onds. The chip is only ready to accept a Channe.1 Atten·
tion (CA) one clock after RESET goes inactive.
Note that the SEL pin is sampled on the falling edge of
the first CA after RESET to tell the 8089 whether it is a
master (0) or a slave (1) for its request/grant circuitry. If a
master, it will assume it has the bus from the beginning.
If a slave, it will strobe the RQ/GT Line to request the
bus back and will not start any bus transfers until it has
been granted the bus. If the RQ/GT line is not being
used, make sure the lOP comes up in the master mode.

One should be careful when setting up the triggering
for the analyzer that the desired event is what is dis·
played and not a later event with the same trigger word.
This can happen when the logic analyzer is in the repet·
itive trigger mode. It may retrigger before the system ac·
tually resets. A sequence restart feature is helpful.

The basis of following program execution and DMA on a
logic analyzer is to follow an 8089 bus cycle, which is
identical to a 8086 and 8088 bus cycle. The following
diagram shows a typical 8089 bus cycle.
For general purpose debugging, displaying every clock
is useful, but for quickly finding one's way around a pro·
gram, the analyzer can be qualified so that only instruc·
tion fetches (status = 100 or 000), with ALE active, are
trapped. A much more compact display of execution
flow resu Its.

ADO·15 ~ PREVIOUS ADDRESS. UPPER STATUS

T1

X

Logie Analyzer Techniques

•
•
•
•

A16·19

Initialization
Upon the first CA after reset, a sequence of instructions
is executed from an internal ROM. These instructions
pick up parameters and load data from the linked list
sequence (Figure 6). The instruction sequence is essen·
tially:
MOVB SYSBUS from FFFF6
LPD System Configuration Block (SCB) from FFFF8
MOVB SOC from (SCB)
LPO Control Poi nter (CP) from (SCB) + 2
MOVBI "00" to CP + 1 (clears BUSY flag)

A-93

AP-50
Remember that four bytes must be fetched during an
LPD. If on a 16·blt bus, with even addressed boundaries,
only two fetches are needed. Otherwise (8·bit bus or odd
boundaries), four fetches are needed.
Even though no bus cycles are run to fetch these in·
structions, the CH1 Task Pointer (TP) appears on the ad·
dress latches during the short internal fetch periods.
On power up, this value is meaningless, but if a repeti·
tive RESET is used, the TP remains unchanged from the
end of the last program run. See Figure 6 for the start of
a typical initialization sequence as viewed on a logic
analyzer.
Bit 0 in the SYSBUS field sets the actual (or physical)
system bus width that the lOP expects. In the 8·bit
mode, only byte accesses are made, and all 8·bit data
should appear on the lower eight data lines. In the 16·bit
mode, word accesses can be made (if the address is
even), all data on even addresses appears on the lower
eight data lines, and all data at odd addresses appears
on the upper eight.
Bit 0 in the SOC field sets the physical width for the 110
bus. The same rules for the system bus apply here. Note
that these bits should reflect the actual hardware imple'
mentation and are not to be confused with the DMA logi·
cal widths set by the WID instruction.
The R bit (bit 1) in the SOC field is used to change the
mode of the RQ/GT circuitry. When the lOP is on the
same bus as an 8086, it is required to have the R bit be 0,
with the 8086 as the master and the 8089 as the slave.

CA

A19-AO
FF F F
FF F F
FF F F
FF F F
EOO 0
EOO 0
FF C6

10
CK

14 {
CK

6
CK

F
F
F
F
0
0
0

S3- S0

T

111
111
111
111
111
111
111

COMMENTS
Trigger ClK

t

111
101
101
111
111
111
111
111

FFC60
FF F F 8
EF F F F
EF F F 0
EF F F F
EF F F 8
EF F F 8
EF F F 8
EF F F 8
FF F FA
EF F F F
EF F FA

111
101
101
111
111
111
111
111
111
101
101
111

EF F F A
FF C6 0

111
111

Wh~ two

lOPs are being used on the same bus, the
RQ/GT circuity can be put into an equal priority mode
by setting the R bit to one. A slave can only be granted
the bus if the master is doing unchained instructions or
running idle cycles. The master can request the bus
back from the slave at any time. The slave grants it if do·
ing unchained instructions or If it is idling. The master
and slave are put on essentially the same priority.
At the end of initialization, the "BUSY" flag of CH1 is
Cleared. For systems where the 8086 is waiting for the
initialization sequence to end before giving another CA,
it can set the BUSY flag high prior to initialization. The
BUSY flag going low is a sign that the lOP Is ready for
another CA. It is important to remember that the lOP will
not respond to, nor latch, a CA during an initialization
sequence.

Channel Attentions

The main system processor initiates communications
with the lOP through the Channel Attention (CA) line. As
mentioned earlier, the first CA after system RESET in·
itializes the lOP. All subsequent CAs cause the lOP to
do a two· step process. It first fetches the Channel Con·
trol Word (CCW) from the appropriate channel at (PP) for
channel 1 or (PP + 8) for channel 2. (SEL at the time of
CA falling determines the channel for all following ac·
tions.) The lower three bits of the CCW Command Field
(CF) are examined and then cause the lOP to execute
the desired function.

Bus un-tristated

Command Field (CF)
TP to latch

FFC60
FF F F 6
EF F F F
EFF 01
EF F F F
EF F F 6
EF F F 6
FF C6 0

The master (8086 or 8088) can never tab the -bus away
from the slave (8089); only the slave can give back the
bus. In other words, during DMA transfers, the 8089
would not have the bus taken away. This is the only
mode compatible with the 8086 or 8088.

T1
T2
T3
T4

T1
T2
T3

Address loaded to latch
Data not ready yet (nothing on bus)
SYSBUS loaded into chip (01)
Nothing on bus
After bus cycle, address remains in
latch
TP is loaded to latch, even though
fetches are from internal ROM

Control of task block programs is accomplished
through the command field. The various CF functions
are:
CF
000 - Examine other field only and set BUSY flag
001 - Start task program in 110 space
011 - Start task program in system memory

Address to latch

The start command causes the following instructions
to be executed out of the internal ROM:

1st 2 bytes of lPO data fetched (FFFO)

T4

LOP CP from (CP) + 2 (CH1) or + 10 (CH2)
LOP TP from (PP) (for TP in system) or
MOVB TBP from (PP) (for TBP in 110)
MOVBI "FF" to (CP) + 1 or+ 9 (set BUSY flag)
111 - HALT channel. BUSY flag cleared to "00"
110 - HALT channel. Save state of machine and
clear BUSY flag by executing:
MOVP TP to (PP)
MOVB PSW to (PP) + 3
MOVBI "00" to (PP) + 1 or + 9

2nd 2 bytes of lPO data fetched (FFFA)

Figure 6. Start of Initialization Sequence On a 16·Bit Bus

A-94

AP-50
The channel will HALT and the machine will continue execution on the other channel or go to idle if
the other channel is idle.
101 -

WAITING TO GET THE BUS BY RQ/GT - If the lOP has
given the bus away via Ra/m, it won't initiate any bus
transfers until it has the bus back. The machine will run
up to just before T1 of a bus clock cycle and will threestate its address/data and status pins until it has been
granted the bus.

Continue channel. The channel is revived
after a HALT by executing:
MOVP TP from (PP)
MOVB PSW from (PP) + 3
MOVBI "FF" to (CP)+ 1 or +9
(set BUSY flag)

WAITING FOR READY - When running bus transfers,
READY is sampled at T3 of a busy cycle. If inactive, the
whole chip will wait until READY goes active.

Do not do a CONTINUE after initialization without doing
a CA START first since the (PP) register in CH1 is used
as a temporary register (to hold SCB) and is only correctly loaded by a CA START.

The last two cases of waiting (or "wait" states) stop the
whole chip and do not permit the other channel to run.
However, with READY inactive or with the bus not acquired, there is not much that can be done on the other
channel anyway. These two cases only stop the chip
when running bus cycles. Any internal operations can
proceed without having the bus or with the system not
READY.

The upper 5 bits in the CCW will have affect if CF =000
or upon a CA START. Some things to note about these
upper fields are:
• Priority Bit - If both channels are doing tasks of
the same overall priority, the tasks with the higher
priority bit will run. If the priority bits are the same,
execution will alternate between the two channels.

Note the difference between when the chip is HALTed
when using RQ/GT and an external arbiter (8289) for
bus arbitration. Not having the bus due to RQ/GT will
inhibit the bus cycle from even starting. Since the 8289
stops the chip by forcing AEN inactive, which goes
through the 8284 clock generator to force READY inactive to the lOP (or 8086/8088), a bus cycle has already
been started, with ALE asserted, and the address on the
address/data lines. When the bus is obtained, operation
proceeds at T3 of the bus cycle.

• BLL Bit (Bus Load Limit) - Keeps nonchained instructions from occurring more often than once
every 128 clocks. However, channel attention or termination cycles, even on the other channel, may
disrupt the exact time interval to the next
instruction.
It should be noted that the setting or clearing of the
BUSY flag occurs after the loading or storing of
registers, so that in a system where the main CPU uses
the BUSY flag as a form of semaphore to tell when the
lOP is truly finished, there is no danger that the SCB,
CP, PP or TP could be changed before the lOP loads
them.

As will be mentioned later, many invalid opcodes will
cause the machine to hang up. In these cases the
address/data lines will point to where the bad opcode
was fetched.

Also since DMA termination cycles and chained instruction execution have a higher priority than CA, it is pOSSible for CA to be "shut-out" by these higher priorities
runn'ing on the other channel. However, since CA is
always latched (except during initialization), it won't be
forgotten.

Although optimized for fast and flexible DMA operation,
the lOP is also a full-fledged microprocessor. The 8086
Family User's Manual deals with programming
strategies and other details. Some of the things to be
noted during debugging will be mentioned here.

Task Execution

Instruction Fetching
Unlike the 8085 (but like the 8086), the 8089 labels all
fetches from the instruction stream, whether OPCODE,
offset, displacement, or literal data, as an instruction
fetch on the status lines. In some cases, such as MOV
R,I and ADD R,I, the instruction fetch time greatly exceeds execution time because literals are treated as instruction fetches. When following programs on a logic
analyzer, triggering on status = 100 or 000 (instruction
fetch) and a known program address is the handiest way
to trace the flow of the program.

How Can a Channel be Halted?
Sometimes a channel may stop its operation unexpectedly. To see what could cause this, and to show the
impact of halting a channel, the various ways of stopping a channel are explained:
HALTED CHANNEL - If the channel has never started
after initialization, if it has received a CA HALT command or a software HALT, channel operation is suspended. If the other channel can run, it will, otherwise
idle cycles will run. Only a CA START or CONTINUE can
resume operation.
WAITING FOR A DMA REQUEST - If the channel is in a
source or destination synchronized DMA transfer mode,
it will wait until DRQ is active before running its synchronized transfer. To minimize the impact on the
overall throughput of the chip, the other channel can run
during these DRQ wait periods.

A-95

When running programs on a 16-bit bus, a 1-byte queue
register comes into play, saving the upper byte fetched
from the last instruction fetch, if not used by the
previous instruction. This reduces fetch time and bus
utilization since the odd byte doesn't need to be fetched
again. An internal four-clock cycle fetches data from the
queue. Like the internal ROM fetches, the task pOinter is
put out on the addressldata lines, but no bus cycle is run.

AP-50
The queue can have some possible unexpected affects
thaI have to be taken into account during debugging.
These apply only to 16-bit systems and are:

• CC - The only thing that affects instructions in the
CC register is the chaining bit. If chaining doesn't
matter (if only one channel is being used without
channel attentions, for example), then the CC register can be general purpose. However, for portability of programs, it is strongly suggested not to use
the CC register except for altering DMA parameters
and chaining.

1. Instructions that start on odd boundaries will not
likely have bus cycles run to fetch the odd byte
unless jumped to, unless preceded by LPDI (which
clears the queue), or an instruction that modifies the
task pointer is executed. The latter causes the queue
to be cleared so that part of an old instruction won't
become part of the new one.

Is a general purpose 16-bit register, but is
also used to do a masked comparison either for
DMA search/match termination or for the JMCE and
JMCNE instructions.

• MC -

2. There is a queue register for each channel so loading
or clearing the queue on one channel has no affect on
the other channel's queue.

• BC, /X - Both general purpose 16-bit registers. In
instructions that reference memory using the AA
field, if AA = 11, the IX register is incremented by
the number of bytes fetched or stored.

3. The second word of immediate data fetched by a
LPDI is done during a pseudo-instruction fetch cycle
that cannot make use of the queue or already fetched
data. Thus, if on an odd boundary, fetching an LPDI
will be byte, word, byte, byte, byte, and the queue will
not be loaded.

• Pointer Registers (GA, GB, GC and TP) - Are 20-bit
registers, but can also be used as 16-bit registers.
Adds will carry into the upper 4 bits, but other
operations (COMP, OR, AND) are done only on the
lower 16 bits. Note that when used as pOinters to
system memory, it is possible to add a large 16-blt
number to the pointer and to put the pointer Into
another 64K block of memory.

When Can the Other Channel Interrupt Instruction
Execution?
This will be explained more in the "dual channel" operation section, but a few points will be mentioned here. All
instructions are made up of internal cycles, with each
cycle composed of two to eight clocks. Each bus cycle
is one internal 'cycle, but there 'can be internal cycles
with no comunications to outside the chip. Internal
cycles will be extended by the number of wait states in
each bus cycle, Between any of these cycles, DMA from
the other channel can intervene if the priorities permit it.
Instruction fetching and execution can only interrupt instructions on the other channel when the instruction
has been completed, not between internal cycles.

Sign Extension
All program data brought into the chip, either literals or
displacements in opcodes, or program data fetched
from memory, is sign-extended. Offsets used for
calculating addresses are not sign extended. Any 8-blt
data brought in has bit 7 sign-extended up to bit 19_
Sixteen-bit data is sign-extended from bit 15 to bit 19. It
is important to note this, because it can affect logical
operations. For example, if one wanted to OR 0084H
with 1234H in register GC, you couldn't do ORBI GC,
84H, because bit 7 would sign-extend into the upper
byte. Instead, you should code ORI, 0084H to do this
properly (note that this has a word for the immediate
data). The non-ADD operations will cause the upper four
bits of the pOinter registers to be invalid since the upper
four bits of the ALU come only from the adder.

Registers
All the registers have some special purpose use in the
Instruction Execution or DMA, but all except the CC
register can be used as general purpose registers during
instruction sequences. A few are loaded specially:

• CP - Is only loaded during an initialization sequence. There is one CP register that handles both
channels. (All others are duplicated, one set for
each channel.)
• PP - Is only properly loaded during a CA START
command. It holds the SCB value after the initialization sequence.
• TP - This is included as part of the registers in the
RRR field, but cannot be operated on unless you
plan on having your program execution jump
around. Every time this is operated on, the queue is
cleared. The TP is loaded from two words (address
and displacement) on a CA START, LPD, or LPDI,
and loaded from 3-byte MOVP format (see illustration on page 5) on a CA CONTINUE, and can be operated on using any register oriented instructions.
The following registers are loaded during program execution, but can have special effects:

Tags
It should be noted that the way the lOP knows which
bus to access (system or I/O) is via the Tag bit associated with the pointer register used. The TAG can only be
set in these ways: loading as a 16-bit register (MOV R,M,
MOV R,I) sets TAG to I/O space, loading as a pointer
(LPD, LPDI) sets TAG to a system space), or bringing the
TAG in from memory by a MOVP instruction.
Effects of Inralld Opcodes
The upper 6 bits of the 2-btye opcode actually determine.
which opcode will be executed. If these bits are a valid
opcode, but lower bits are invalid, the chances are good
that the bad bits will be ignored. But if the upper six bits
are invalid, there is a very good chance that the chip will
hang up and stop execution in that channel. The only
way to get out of this mode is to reset the chip. If this
hang-up occurs, it can usually be traced because the
last address of the instruction fetch will still be on the

A-96

AP-50
address/data lines, showing where the program went
astray.
Going from Instruction Execution into DMA
The XFER instruction places the current channel into
the OMA mode after the next instruction. This permits
one last instruction to start up an I/O device (start CRT
display on an 8275, for example). However, in order for
the lOP to get setup for OMA, the GA, GB, and CC
registers should not be altered during this last instruction. Failure to observe this will probably result in an
improper first OMA fetch. The WID instruction can be
placed after XFER.
DMA Transfers

tncrementing/Non·lncrementing pointers
A memory or I/O pOinter can be made to increment for
each byte transferred during OMA or it can remain fixed.
Incrementing is used primarily for memory block
transfers, and non-incrementing is used to access I/O
ports.
B/W Mode
Each OMA transfer is composed of separate fetch and
store cycles so that 8/16-bit data can be assembled and
disassembled, and translation and termination may also
be easily handled. There are four possible transfers or
B/W modes. They are:
B - B-1 byte fetched, 1 byte stored
B/B - W - 2 bytes fetched, 1 word stored
W - B/B - 1 word fetched, 2 bytes stored
W - W - 1 word fetched, 1 word stored
The B/W mode used depends on the logical bus width
(selected by the WID instruction), address boundary,
and incrementing mode.
All systems with 8-bit physical buses wil.1 run in the B/B
mode. On 16-bit physical buses the other modes are
possible, depending on the logical widths selected.
Note that the logical bus width can be different than the
physical bus width since there are cases where an 8-bit
peripheral may be used on a 16-bit bus. The selection of
the logical width, and not the physical width, is what
determines the B/W mode. Thus it is the responsibility
of the programmer not to program an invalid combination (i.e., don't specify a 16-bit logical width on an 8-bit
physical bus).
Any transfer on an odd boundary will be B/B but if the
pointer is incrementing and on a 16-bit logical bus, after
the first transfer, the pointer will be on an even .boundary. The lOP will then try to maintain word transfers in
order to transfer data as effeciently as possible. See the
user's manual for details. The change in B/W mode occurs only after the first transfer or, as explained in the
termination section, upon certain byte count terminations.
Synchronization

In the unsynchronzied mode, transfers occur as fast as
priorities will allow. This is the lOP's "block-move"
mode. Most I/O peripherals only want a OMA transfer on
demand; the ORO lines, along with synchronization
specified, will handle this need. Source synchronization

A-97

is used for I/O reads and destination synchronization is
used for I/O writes.
If the lOP is waiting for a OMA request, it will run programs or OMA on the other channel, or execute idle
cycles if nothing is pending. If running idle cycles when
the ORO comes, the transfer starts five clocks after
ORO is recognized. If running OMA or instructions on
the other channel, the ORO cannot be serviced until the
current internal cycle is done, and may require a maximum of 12 clocks (without bus arbitration or wait
states).
Consecutive ORO-synchronized OMA transfers on the
same channel are separated by four idle clocks (assuming no other delays) by an internal sampling mechanism.
This happens between the 2-byte fetches on sourcesynchronized B/B-W cycles, and between the two stores
on destination-synchronized W-B/B cycles. This delay
between consecutive OMA cycles allows adequate time
for proper acknowledgement of the current DMA request before the next request is processed. On
destination-synchronized OMA, this isn't a problem, but
on source-synchronized OMA, there will be four extra
clocks per transfer. Unless one is running right at the
speed limit, this won't be a problem. Near the maximum
data rate, unsynchronized transfers can be used, with
synchronization done by manipulating the READY line.
Trans/ate Mode
When the translate bit is set, the data fetched during
OMA will be added to the GC register. This new pointer
will in turn be used to fetch, via a seven clock extra fetch
cycle, new data, which will then be stored. Translate is
only defined for byte transfers. The bytes are added to
GC as a positive offset, so a lookup table for translating
data can be a maximum of 256 bytes long. Even if the
data to be translated falls within a smaller range (such
as ASCII code), a full 256-byte lookup table is recommended so that erroneous data can be flagged and controlled.
Translate can be run on any of the B/B transfer modes,
so it is useful for doing block translation within program
execution as well as translation directly to or from an I/O
port.
DMA Termination

One of the powerful features of the lOP is its varied
DMA termination conditions and their close tie-in with
resuming Instruction Block programs. However, because of the multitude of DMA modes, care must be
taken in predicting the exact termination parameters.
Various things to be careful about will be outlined here.
Byte Count (BC) Termination

The Be register is decremented for every byte transferred whether or. not Be termination is set. If Be termination is set, the last transfer done is the one that
results in Be being zero. To avoid the problem of missing Be= 0 on word transfers, if Be is odd between every
transfer, the lOP detects when Be is 1, and forces the
last transfer to be in the BIB mode. Since both the fetch
and store cycles are complete, the source and destinati.on pOinters point exactly to the next byte or word that
would have been fetched.

AP-50

n.
Mesked Compere (MC) Terminetion

An MC termination occurs when a pattern matches (or
doesn't match, depending on mode selected) the lower
half of the MC register (the match pattern) with only the
bits that are enabled by the upper half of MC (the mask
pattern) contributing to a match. Thus the masked bits
can be "don't cares" in both the data byte and the match
byte.

In orderto prevent an invalid signal level from becoming
trapped from the asynchronous EXT term lines, two
clocks of delay and signal conditioning are done on
these lines. In addition, a termination cycle can only be
started at certain times during OMA (or TB on the other
channel - see dual channel operation section). The EXT
terminate lines should be valid eight clocks before the
start of the OMA cycle to be stopped.

The masked comparison is only done on store (deposit)
cycles. Any bytes transferred (in BIB or W-B/B mode) will
be compared. But, since the MC comparison is done on
only one byte, any words stored (W-W or B-BIW) have
only their lower byte compared. This may be fine, but if
not, make the destination logical width 8 bits.

EXT is sampled even when the lOP is running something
on the other channel. Remember though, that despite
the high priority {)f termination, the current Instruction
on the other channel has to finish before the termination
cycle is run. Simultaneous EXTs on both channels result
in CH1 termination being done first.

Just like BC termination, the pointers will point to the
next data to be transferred. The BC will also be decremented correctly, except if the termination occurs on
the first byte of a W-B/B transfer. In this case the BC will
be decremented as if the entire transfer (both bytes) had
taken place.

In order to have enough time to process a byte count termination, the BC register is always decremented during
OMA fetch cycles. Because of this, external or MC terminations that occur during W·B/B cycles will result in
the byte count always being decremented by two, even
if only one byte is stored. This also occurs In the blockto-block or block-to-port B/B-W modes. To find the exact
number of bytes transferred, the source pointer addre&6
can be checked in the block-to-port and block-to-block
modes during B/B-W cycles and In the block-to-port
W-B/B mode. The destination pointer address can be
used to find the number of bytes transferred in the port.to-block and block-to-block modes during W-B/B cycles.

The store cycle that causes an MC termination will be
lengthened by two extra clocks (or by one extra clock if
there are walt states), to allow time to set up the termination cycle.

Termlnetlon Cycles end Multiple Termlnetlons
MASK PATTERN _ _ _ _oJ

MATCH

Figure 7. Masked Compare Logic lor 1-811

Externel (EXT) Terminetion

External termination allows the I/O devi.ce or controller
to use its own conditions to generale a termination.
Basically, the lOP will halt OMA as soon as Itrecognizes
an EXT terminate, even if a transfer is only partially complete. There might be concern that multi byte cycles
(W-B/B or B/B-W) might have data lost If an EXT terminate stopped the store cycle. In unsynchronlzed OMA
this would happen, but this mode Is typically not used
with I/O controllers that could generate external terminations. In synchronized OMA modes, it Is assumed
that the I/O controller will only do a ORQ for valid data
transferred, and ttiat it won't give an EXT terminate with
Its ORQ active. In destination synchronization, the
possible problem occurs In the W-B/B mode, where EXT
terminate comes after the first store but before the second. This Is fine, since even though data was overfetched, the proper amount was actually transferred. In
source synchronization, the B/B·W mode raises problems since if an EXT terminate came after the first byte
fetched and before the second byte fetched, normally
no store cycles would be done at all; thus losing the first
byte fetched. In this case (Le., source synced, ORQ Inac·
tive, and 1 byte already fetched), a ,single byte store
cycle is run before the termination cycle, ensuring data
.
integrity.

Upon termination, the user can run different task block
programs, depending on which type of termination has
occurred, by specifying an appropriate termination offset. That is, instruction fetching will begin after a
termination cycle starting at either the TP value before
the OMA started, TP + 4 or TP + 8. These offsets permit
long or short jumps to termination routines.
The termination cycle is an add immediate instruction
that runs from the internal ROM and adds the proper offset to the TP. It is 15 clocks long for'TP + 4 and TP + 8
termination and 12 clocks long for TP+ o termination.
As mentioned earlier, EXT terminate must. come a certain time before the end of a transfer to ensure that the
next transfer doesn't start. If it comes In time and MC
termination also occurs on the current transfer, then the
termination cycle with the largest offset is run. A
simultaneous BC terminate cycle will have priority over
MC and will result in the running the BC termination
program.
Priorities/Dual Channel Operation
Tile lOP can share its internal and external hardware
between two separate channels. The user sees two
identical lOP channels with all registers, machine flags,
etl)., independent of the other channel. The only register
In common Is the CP register, loaded by the initialization sequence. The mechanism for achieving dual channel ,operation is time multiplexing .between the two
channels.
Since interleaving two channels affects their respGIlse
time to external events and since Interfacing to these
events.is the prime purpose of the lOP, several means of
adjusting the priorities of the channels are provided.

A·98

AP-SO
Before going into the priority algorithms in detail the
four types of cycles that are affected by the priorities
will be outlined:

channel goes idle. Chaining will also lock out normal instructions on the other channel. Chaining should thus
be used with care.

1. DMA Cycles - Any type of DMA transfer cycle,
including single transfers and translate cydes. DMA
can be interrupted after any bus transfer by the other
channel.

In order to reduce the possibility of shutting out channel
attentions, an exception is made to the above priority
scheme. After every DMA transfer, whether synchronized or unsynchronized, the lOP will service any pending CA. However, chained task block execution will still
shut out CAs on the other channel.

2. Instruction Cycles - Any instructions that have
been fetched out of 1/0 or system memory. Instruc·
tion cycles are made up of internal cycles, each two
to eight clocks long (assuming no wait states). Some
cycles may not run bus transfers. Instructions can be
interrupted by DMA after anyone of the internal
cycles, but can only be interrupted by instructions on
the other channel (normal ones or ones from internal
ROM) after the current instruction is completed.
3. Termination Cycle - Performed when DMA transfers
end and instructions resume (except on Single
transfers).
4. Channel Attention Cycles - Performed when chan·
nel attention is given, performs actions specified in
the CCW field. Both termination and CA cycles can
be interrupted by DMA after any internal cycle, but
can only be interrupted by instruction cycles after
the complete sequence of internal cycles is done.

Termination and channel attention cycles as well as the
initialization cycle (which never runs concurrently with
other operations) are sequences of instructions fetched
from an internal ROM.
Recognizing the higher importance in doing DMA, termination and (to a lesser extent) CA cycles, the following priority scheme is built into the lOP. Any channel
that has a higher-priority operation will run continuously
until done. If both channels are running the same priority, execution will alternate between them.
Highest Priority

1.
2.
3.
4.

DMA transfers, termination, chained instructions
Channel attention cycles
Instruction cycles
Idle cycles

Lowest Priority

Two ways exist to alter the priority scheme. One way is
to utilize the priority bits for each channel. If one is
greater than the other, that channel will run at the expense of the other if both channels are otherwise running at the same priority. Thus the P bit only has effect
on channels running at the same priority level.
If one wants to run instructions along with or in place of
DMA on the other Channel, the other technique is to set
the chaining bit (in the CC register) which brings the
instruction priority up to the level of DMA. Care should
be taken with this since now CAs are at a lower priority
than instructions and will not be serviced unless that

What is the importance of priorities? Well, as an
example, let's say that we are running long periods of
non·time-critical block moves (via DMA) on one channel
and running short bursts of DMA that must be serviced
promptly on the other channel. With the defaul.!
priorities, the short DMA channel bursts would be in·
terleaved with the longer DMA, reducing the maximum
transfer rate for both channels. If, however, the priority
bit was one on the burst mode DMA and zero on the
other, the bursts would be serviced continuously at the
fastest possible data rate.
An even more critical case would be the same low prior·
ity, long DMA transfers on one channel with DMA on the
other channel that must terminate, run a short instruc·
tion sequence, and resume DMA again within a short,
fixed time. (This might be the case in running a CRT dis·
play with linked list processing between lines.) Normally, the low priority, long DMA could indefinitely block
the short TB sequence. By setting the high·priority chan·
nel's priority bit to one and putting it into the chained
instruction mode, the low priority channel would stop
its DMA entirely so that the terminationlinstruction se·
quence could run.
When establishing the priorities to be run, care should
be taken that both channels will run successfully under
a worst case combination. This can be tricky when the
channels are running asynchronously with fast data
rates and/or short latencies, but must be taken into ac·
count. Of course, running only one channel on the lOP is
an easy solution, but if more than one lOP is being used
in the system, the priorities and delays of the bus ar·
bitration used (either RQ/GT or an 8289 bus arbiter) must
be taken into account. It may be found that the on·chip
arbitration between the two channels is faster and more
powerful than external arbitration.
SUMMARY
It is hoped that the material presented here will aid
those who are putting together and debugging an 8089
lOP system, and help them in understanding the opera·
tion of the lOP. Many of the debugging techniques
should be familiar to those who have worked with micro·
and minicomputer systems before. Other debugging
techniques not mentioned here, which work well with
microprocessor systems, could be just as applicable to
the 8089. The unique nature of the lOP among LSI
devices warrants special consideration for its I/O func·
tions and multiprocessor capabilities.

A-99

AP-50
The breakpoint routine uses a simple jump to a save
routine. The PUM-86 supervisory or control program
handles the placement of the jump within the users program. Since it can not normally access the remote bus,
all lOP programs to be tested must run out of system
memory.

Appendix I
CHECKLIST OF POSSIBLE PROBLEMS
HARDWARE PROBLEMS
• Is RESET at least four clocks long?
• Are both Vss lines connected to ground?
• Does the first CA falling edge come at least two clocks
after RESET goes away?
• Does the second CA come at least 150 clocks (16-bit
system, no wait states) after the first CA?
• Is READY correctly synchronized and gated by
local/system bus lines?
• Is SEL correct for first CA so that lOP comes up correctly as master or slave?
• If two lOPs are local to each other, is a 2.7K pull-up resistor used on RQ/GT?
SOFTWARE PROBLEMS
• Are the initialization parameters in the initialization
Iinked-list correct?
• Is BUSY flag being properly tested by host CPU software before modifying PB or providing a new command?

When the control program starts, it assumes the lOP has
just been reset. It then prompts the user for the CP
and PP values. After this, it sends the first (initialization)
channel attention. It then asks the user for the channel
to be run, and the starting and stopping addresses. After
the stopping address has been entered, a Channel Attention Start is given. If the breakpoint is reached, a
HALT is executed, and the control program prints the
register contents. If the breakpoint hasn't been reached,
the user can type any character, and a Channel Attention Halt will be sent to the lOP. If the lOP responds
within 50 ms, the TP where it was halted is printed.
Otherwise, the control program issues an error
message. If, at any time, the user wants to get out of the
program, typing an ESC will pass control back to the
SDK-86 monitor. Figure 9 shows the flow of the control
program.
Note that, unlike a single CPU debugging routine, having the 8086 supervise the 8089 enables a clean exit
from crashed lOP programs. The program code where
jumps had been placed are always restored. The control
program is a good example of how the power of dual
processors can be put to good advantage.

• Have DMA termination conditions been met? The lOP
could be trying to do endless DMA.

Comments within the control program indicate
parameters that need to be changed to run on different
systems. It should be noted that channel attentions are
invoked by the recommended method of using an 110
write to a port to generate CA and using AO for SEL.

Appendix II

Source and object files of this program are available
through Intel's INSITE™ User's Program Library as program 8089 Break. 89 (number AD6).

• Has the chaining, translate, or lock bit in the CC
register been erroneously set?

BREAKPOINT ROUTINE
AND
CONTROL PROGRAM

MASTER DATA STORAGE LOCATIONS:

The debugging program described here is an example of
the kind of software development tool that can be
developed for the 8089 lOP. It was written to tryout
various breakpoint schemes, and has been used to
debug an engineering application test system. The program is not meant to be the ultimate debugging tool, but
is an example of what can be put together to utilize the
breakpoint routine described earlier in the application
note.
The debugging program was tested on a 8086-based
system that emulates the SDK-86 110 structure, and uses
the SDK-86 serial monitor. This enables it to use the
SDK-86 Serial Downloader to interface to an
Intellec@ development system on which the software
was created. The 8086 system is interfaced via a
MULTIBUS™ interface to an lOP running in the REMOTE
mode. The remote bus access technique, mentioned
earlier in this note, is implemented on this system, but
was not used in the software debugging program.

=l
-

TP

- pp+

GA
GA
GB
GC

GB
GC
BC
IX

cc
MC

INCREASING
ADDRESS

pp

TP

-

--

239

pp+ 242
pp+ 245
PP + 248
pp+ 250

lI- PP+ 252

-

pp+ 254

Figure 8. Breakpoint Routine to Run 8089 Program out of System
Memory

A-IOO

AP-50

NO

LOAD PP
WITH STARTING

POINT.
BUSY FLAG
WITH OFFH

Figure 9. Breakpoint Routine to Run 8089 Program out of System Memory

A-lO!

AP-50

PL/M-86 COMPILER

8089 BREAKPOINT ROUTINE

PAGE

ISIS-I I PLlM--86 Xl03 COMPILATION OF MODULE BREAKPOINT
OBJECT MODULE PLACED IN BREAK.OBJ
COMPILER INVOKED BY:
. Fl: PLM86 BREAK. SRC PAGEWIDTH (100)

..

$TITLE ('8089 BREAKPOINT ROUTINE')
;

8089 BR~AK POINT PROCEDURE
WRITTEN BY DAVE FERGUSON 2/2/79
INTEL CORPORATION

REV 2

8/14179

... *1

2
3
4
5
6
7

8
9

10

11

BREAK$POINT:
DO;
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE

I BYTE;
SAVECODE (4) WORD; I*BUFFER FOR STORAGE*I
ON~PP POINTER;
1* CHAN ONE PP *1
TWOPP POINTER; 1* CHAN TWO PP *1
STARTBYTES (4) BYTE; 1* BUFFER FOR START ADDRESS *1

DECLARE
DECLARE
DECLARE
DECLARE

STARTPOINTER POINTER; 1* POINTER FOR START ADDR. *1
ENDPOINTER POINTER; 1* POINTER FOR END ADDR. *1
PRESENT POINTER AT (@INPNTR); 1* POINTER BUFFER *1
TRUE LITERALLY 'OFFH', FALSE LITERALLY 'oaoH';

1* YOU MUST CONFIGURE YOUR 1/0 STRUCTURE AND
SYSTEM TO MATCH THE PROGRAM OR VISA VERSA *1
DECLARE CRTSTATUS LITERALLY '0F,FF2H', 1* 8251 STATUS PORT *1
CRTDATA LITERALLY 'OFFFOH', 1* 8251 DATA PORTS *1
CHANATTEN LITERALLY 'OFAH', 1* CHANNEL ONE CHANNEL ATTENTION PORT *1
1* CHANNEL TWO CHANNEL ATTENTION PORT = CHANATTEN + I *1
CHANNEL ONE LITERALLY 'OOH',
CHANNELTWO LITERALLY 'OIH',
1* ASCII IS A STRING OF HEX CHARACHTERS IN ASCII FORM *1
ASCII (*) BYTE DATA .('0123456789ABCDEF'),
TITLE$STRING (*) BYTE DATA (OAH,ODH, '8089 BREAKPOINT VER 1.0',
OAH,ODH, 'TYPE ESCAPE TO RETURN TO MONITOR. "
OAH, ODH, 0),
CHANGIVEN (*) BYTE DATA ('CHANNEL ATTENTION GIVEN TYPE ANY KEY TO ABORT. '
,OAH, ODH, 0),
BKREACHED (*) BYTE DATA (OAH,ODH, 'BREAKPOINT REACHED',OAH,ODH,O),
GETCP (*) BYTE DATA ('INPUT CP IN HEX',OAH,ODH,OO),
GET$PP (*) .BYTE DATA ('INPUT PP. IN HEX FOR ',OOH),.
GETSTART (*) BYTE DATA (OAH,ODH, 'INPUT STARTING ADDRESS IN HEX',OAH,ODH,OOH),
STOPADDR (*) BYTE DATA ('INPUT END ADDRESS IN HEX',OAH,ODH,OOH),
CHANNUMBER (*) BYTE DATA (OAH,ODH, 'CHANNEL ONE OR TWO? ',OOH),
ABORT (*) BYTE DATA (' FATAL ERROR - lOP DOES NOT RESPOND TO CHANNEL',
, ATTENTION. RE-INITIALIZE SYSTEM ',0),
ABORTAT <*) BYTE DATA (' TP WAS ',0),
ONE (*) BYTE DATA (' CHANNEL ONE',OAH,ODH,OOH),
TWO (*) BYTE DATA (' CHANNEL TWO',OAH,ODH,OOH),
GASTRING (*) BYTE DATA ('GA = ',OOH),

A-102

AP-50

.'

'Ii'

PL/M-86 COMPILER

GBSTRING
GCSTRING
BCSTRING
IXSTRING
CCSTRING
MCSTRING
12
13

PAGE

8089 BREAKPOINT ROUTINE
(*)
(*)
(*)
(*)
(*)
(*)

BYTE
BYTE
BYTE
BYTE
BYTE
BYTE

DATA
DATA
DATA
DATA
DATA
DATA

('GB = ',OOH),
('GC = ',OH),
(OAH,ODH, 'BC = ',OOH),
(OAH,ODH. 'IX
',OOH),
(OAH.ODH. 'CC
',OOH),
(OAH,ODH, 'MC, = ',OOH)

DECLARE CHAR BYTE.
DECLARE ONETWO BYTE.
1* SDKMON IS A PLM TECHNIGUE USED TO FORCE THE CPU INTO AN

14
15

2

16
17

2
2

INTERUPT LEVEL 3,
IN ORDER TO USE THIS THE PROGRAM MUST
BE COMPIL.ED (LARGE>' *1
SDKMON:
PROCEDURE.
DECLARE HERE (*) BYTE DATA (OCCH),
1* THIS IS AN INT,
3 *1
WHERE WORD DATA(,HERE).
CALL WHERE.
END.
1* CO SENDS A CHAR TO THE CONSOLE WHEN READY *1
1* THIS ROUTINE IS WRITTEN TO RUN VIA THE SERIAL
PORT OF AN SDK86 *1

18
19
20
22
23

2
2
2
2

0, END,

1* CI GETS A CHARACHTER FROM THE USER VIA THE SERIAL PORT *1
1* CI AUTOMATICALLY ECHOS THE CHARACHTER TO THE USER CONSOLE *1
DECLARE tSCAPE LITERALLY 'iSH',

24
2S
26
28
29
30
32
33

CO:
PROCEDURE (C).
DECLARE C BYTE.
DO WHILE (INPUT(CRTSTATUS) AND 01H)
OUTPUT (CRTDATA) = C.
END.

1
2
2
2
2
2
2

CI: PROCEDURE BYTE,
DO WHILE (INPUT(CRT$STATUS) AND 02H) = 0, END,
CHAR = INPUT (CRTDATA) AND 07FH,
CALL CO(CHAR),
IF CHAR = ESCAPE THEN CALL SDKMON, 1* GO TO SDK MONITOR *1
RETURN CHAR,
END,
1* VALIDHEX CHECKS THE VALIDITY OF A BYTE AS A HEX CHARACHTER*I
1* THE PROCEDURE RETURNS TRUE IF VALID FALSE IF NOT *1

34
35
36
37
39
40
41

2
2
3
3
2
2

VALIDHEX:
PROCEDURE (H) BYTE,
DECLARE H BYTE,
DO 1=0 TO LAST(ASCIl),
IF H-ASCII(I) THEN RETURN TRUE.
END,
RETURN FALSE,
END,

il

A-103

2

AP-50

PL/M-86 COMPILER

8089 BREAKPOINT ROUTINE
1* HEXCONV CONVERTS A HEX CHARACTER TO BINARY FOR MACHINE USE. :

42
43
411
46
47
49
50

2
2
2
3
3
2

IF THE CHARACTER IS NOT A VALID HEX CHAR. THE PROCEDURE RETURNS
THE VALUE OFFH *1
HEXCONV:
PROCEDURE (OAT) BYTE,
DECLARE OAT BYTE,
IF VALIDHEX(DAT) () OFFH THEN RETURN TRUE,
DO 1=0 TO LAST(ASCII),
IF OAT = ASCII(I) THEN RETURN I,
END,
END,
1* HEXOUT'WILL CONVERT A VALUE OF TYPE BYTE TO AN ASCII STRINQ
AND SEND IT TO THE CONSOLE *1

2
2
2
2

HEXOUT:
PROCEDURE (C) ,
DECLARE C BYTE,
CALL CO(ASCII(SHR(C.4) AND OFH»,
CALL CO(ASCll (C AND OFH»,
END;

2
2
2
2

1*. WORDOUT CONVERTS A VALUE OF TYPE WORD TO AN ASC I I STR ING
AND SENDS IT TO THE CONSOLE *1
WORDOUT:
PROCEDURE (W),
DECLARE W WORD;
CALL HEXOUT(HIGH(W»;
CALI_ HEXOUT(LOW(W»;
END;

51
52
::;3
54
55

56
57
58
59
60

I"

G'ETADDRESS IS A PROCEDURE'TO GET AN ADDRESS FROM THE CONSOLE,
THIS PROCEDURE WILL ONLY CONSIDER THE LAST::; CHARACHTERS ENTERED
*1

61

DECLARE INPNTR (4) BYTE;

62

GET$ADDRESS:
PROCEDURE POINTER;
DECLARE BUFF BYTE;
I*CLEAR ALL VALUES TO ZERO *1
I NPNTR (Q)
0;
INPNTR(I)
0;

63

2

64

2
2

65
66
67
68
69

2

INPNTR(2)

0;

2

INPNTR(3)

0;

2
2

BUFF = 0;
DO WHILE BUFF () TRUE;
1* THIS SEGUENCE OF SHIFTS ALLOW THE USER TO TYPE IN FIVE
OR MORE CHARACHTERS TO BECOME THE ACTUAL POINTER FOR aoac;>
OR 8086, THIS PROCEDURE RETURNS THE LAST FIVE IN PROPER
SEGUENCE STORED IN INPNTR(0-3).
THE STORAGE
IS AS FOLLOWS:
I, THE LAST CHARACTER INPUT GOES INTO
THE LOW FOUR BITS OF INPNTR(O).
2, THE NEXT TO LAST CHARACTER GOES INTO
THE LOW FOUR BITS OF INPNTR(2).

PAQE

AP-50

PAGE

8089 BREAKPOINT ROUTINE

PL/M-86 COMPILER

3. THE THIRD CHARACTER INPUT GOES INTO
THE HIGH FOUR BITS OF INPNTR(2)
4. THE SECOND CHARACHTER INPUT GOES INTO
THE LOW FOUR BITS OF INPNTR(3)
5. THE FIRST CHARACTER INPUT GOES INTO
THE UPPER FOUR BITS OF INPNTR(3).
THE 86 SHIFTS INPNTR (2.AND3) LEFT FOUR BITS AND ADDS THIS TO
INPNTR(O) RESULTING IN THE ADDRESS THE USER TYPED IN. *1
70
71
72

73
74
75
76
77

78
79

3
3

3
3
3
3

2
2
2
2

INPNTR(3) = (SHL(INPNTR(3).4) OR (SHR( INPNTR(2).4) AND OFH),
INPNTR(2) = (SHL(INPNTR(2).4) OR (INPNTR(O) AND OFH»,
INPNTR(O) = BUFF,
BUFF = CI,
BUFF = HEXCONV(BUFF) ,
END,
CALL CO(OAH), I*LINE FEED TO CRT*I
CALL CO(ODH), I*CARRIAGE RET TO CRT*I
RETURN PRESENT, 1* PRESENT IS A POINTER TO THE ARRAY INPNTR. *1
END,
1* STRINGOUT IS A PROCEDURE TO SEND THE CONSOLE AN ASCII STRING

ENDING IN THE VALUE 00. STRINGOUT NEEDS A VALUE OF TYPE POINTER
*1

80
81
82
83
84
85

86
87

2
2
2
3
3
3
2

89

93
94
95

96
97

98

I = 0,

DO WHILE STR(I) (> 0,
CALL CO(STR( I»),
I = I + 1,
END,
END,
DECLARE TAGIS (*) BYTE DATA (. OPERATING IN '.0).
TAGISONE <*) BYTE DATA ('10 SPACE'.OAH.ODH.O).
TAGISZERO (*) BYTE DATA ('SYSTEM SPACE'.OAH.ODH.O),
1* TAGTEST TESTS THE TAG BIT AND SENDS A MESSAGE TO THE CONSOLE
THE TAG IS LOCATED IN BIT THREE. A TAG BIT OF ONE MEANS THE
POINtER IS TO liD SPACE. AND A TAG BIT OF ZERO MEANS THE
POINTER IS TO SYSTEM SPACE *1
1* THE CALLER MUST DECIDE WHICH BYTE HAS THE TAG AND PASS IT TO TAGTEST *1

8B

90
91
92

STRING$OUT:
PROCEDURE( PTR),
DECLARE PTR POINTER.STR BASED PTR (1) BYTE,

2

2
2
2
3
3
2
3
3

TAGTEST:
PROCEDURE (TEST) ,
DECLARE TEST BYTE,
CALL STRINGOUT(@TAGIS),
IF (TEST AND 01000B) (> 0
THEN
DO,
CALL STRINGOUT(@TAGISONE),
END,
ELSE
DO,
CALL STRINGOUT(@TAGISZERO),
END,

A-lOS

4

AP-50

PL/M-86 COMPILER
qq

2

100

101

8089 BREAKPOINT ROUTINE

PAGE

END,
DECLARE SAVE$ADDR LITERALLY '2000H',
SAVE$SEG LITERALLY 'OOCOH',
DECLARE BREAK89 (4) WORD DATA (9B8IH,089IH,SAVE$ADDR,SAVESSEG);
1* BREAK89 IS AN 4 WORD ESCAPE SEQUENCE TO ADDRESS 2000H
CONSISTING OF AN LPDI TP,SAVE$ADDR WITH SEGMENT,
LOCATED AT OCOOH,
*1

1* BRKRTN IS 33 BYTES OF
AS FDl LOWS
GA STORED
AT PP +
GB STORED
AT PP +
GC STORED
AT PP +
BC STORED
AT PP +
IX STORED
AT PP +
CC STORED
AT PP +
Me STORED
AT PP +

CODE THAT STORES ALL REGISTERS
239
242
245
248
250

252
254

*1

DECLARE BRKRTN (33) BYTE AT (02COOH)

102

i* 02COOH IS ACTUALL,Y (SAVE$ADDR + (SHUSAVE$SEG), 4», AND SHOULD
MATCH ADDRESS AND SEGMENT WHERE BREAK ROUTINE IS WANTED
*1
INITIAL,
,03H, 09BH,OEFH,023H,09BH,OF2H,043H,09BH,OF5H,063H,087H,OF8H,OA3H,087H,
OF~h,OC3H,OB7H,OFCH,OE3H,087H,OFEH,020H,048H)

103

DECLARE PP POINTER,
DECLARE PPP BASED PP (1) BYTE,

104
1,)5

IC.6

2

107

2

108

;;>

IG9

2

110

2
;;>

111

11

'-'

113

;;2

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2

115
lIb

117
118

START$PRGM
PROCEDURE(oNE$TWo,PPP),
DECLARE ONE$TWo BYTE,PPP POINTER,
WHERE BASED PPP (1) BYTE,
WHEREIO) = START$BYTES(O),
WHERE I I)
0,
WHERE(2) - ~TART$BYTES(2)'
WHERE(3) ~ START$BYTES(3),
CPDAT(loNE$TWo) * 8) = 3,
1* IF ONE TWO = 1 THEN OUTPUT TO PORT OFBH,
IS 0 THEN OUTPUT TO PORT OFAH *1
OUTPUTICHANATTEN + (oNETWo ) = 0,
CALL STRINGoUT(@CHANOIVEN),
END,

IF oNETWo

1* THIS PART OF THE PROGRAM ALLOWS THE USER TO DEFINE THE
CP,PP OF EACH CHANNEL *1
DECLARE BREAKOUT BASED ENDPoINTER (I) WORD,

DECLARE CP POINTER,
DECLARE CPDAT BASED CP (1) BYTE,

Ilq

DECLARE oNEPPDAT BASED oNEPP (1) BYTE;
DECLARE TWoPPDAT BASED TWoPP (1) BYTE,

120

CALL STR INGoUT (@TITLESTRING);

A-106

5

AP-50

PL/M-86 COMPILER

CALL STRINGOUT(@GETCP),
CP = GETADDRESS,
CALL STRINGOUT(@GETPP),
CALL STRINGOUT(@ONE),
ONEPP = GETADDRESS,
CALL STRINGOUT(@GETPP),
CALL STRINGOUT(@TWO),
TWOPP = GETADDRESS,
OUTPUT (CHANATTEN) = 0,

1:21
1:22
123
124
125
126
127
128
129
130
131
132
134
135
136

2
2
2

137
138
139
140

1
2
2
2

PAGE

8089 BREAKPOINT ROUTINE

1* INITIALIZATION CA *1

MAIN:
CALL STRINGOUT(@CHANNUMBER),
CHAR = CI, 1* GET CHANNEL NUMBER *1
IF (CHAR AND 01H) (> 0 1* CHECK BIT ZERO TO DEFINE
CHANNEL NUMBER *1
THEN DO,
CALL STRINGOUT(@ONE),
ONE TWO = CHANNELSONE,
END,
ELSE
DO,
CALL STRINGOUT(@TWO),
ONE TWO = CHANNELSTWO,
END,
CALL STRINGOUT(@GETSSTART), 1* GET STARTING ADDRESS
FROM USE:R *1

141

143
144
145
146

I
I
2
2
1

STARTPOINTER = GET ADDRESS,
DO I = 0 TO 3, 1* MOVE STARTING ADDRESS INTO CP AREA *1
STARTBYTES(I) = INPNTR(I),
END,
CALL STRINGOUTC@STOPADDR), 1* GET STOP ADDRESS
FROM USER *1

147
148
149
150
151
152
153
154
155
156
157
158
159
160

I
I
2
2
1
2
2
1
I
I
2
2
2
1

ENDPOINTER = GETADDRESS,
DO I = 0 TO 3, 1* MOVE CODE TO SAFE AREA *1
SAVECODE(I) = BREAKOUTCI),
END,
DO I = 0 TO 3,
BREAKOUT(I) = BREAK89(I), 1* MOVE ESCAPE SEQUENCE INTO PLACE *1
END,
CPDAT(I) = OFFH, 1* SET CHANNEL ONE BUSY FLAG *1
CPDAT(9)
OFFH, 1* SET CHANNEL TWO BUSY FLAG *1
DO CASE ONETWO,
PP
ONEPP,
PP = TWOPP,
END,
CALL STARTSPRGM(ONESTWO,PP),
1* WAIT FOR ONE OF THE FOLLOWING
1. CPDAT(I) = 0 CHI NOT BUSY
2.CPDAT(9) = 0 CH2 NOT BUSY
3. THE 8251 REC. BUFFER IS FULL BECAUSE USER HAS DEPRESSED A KEY

142

=

=

*1
161

6

DO WHILE (

(CPDAT(I) AND CPDAT(9»

A-107

AND (NOT (INPUT(CRTSSTATUS) AND 02H»)

OFFH,

AP-50

PL/M-86 COMPILER
162
163

2
1

164
165
166
167
168

1
2
2
3
3

169

2

170
171
172
173

2
2
3
3

8089 BREAKPOINT ROUTINE

PAGE

END;
IF (INPUT(CRT$STATUS) AND 02H) <> 0
THEN
DO;
CHAR = CI;
DO I = 0 TO 3;
BREAKOUT(I) = SAVECODE(I);
END;
1* IF ONE TWO = 0 THEN PUT CHA HLT IN CPDAT(O)
IF ONE TWO = 1 THEN PUT CHA HLT IN CPDAT(8)
*1
CPDAT(ONE$TWO *8) = 06H;
1* IF ONE TWO = 0 THEN OUTPUT TO PORT OFAH. IF ONETWO
IS 1 THEN OUTPUT TO PORT OFBH.
*1
OUTPUT(CHANATTEN + ONETWO) = 0;
DO I ~. 0 TO 5;
CALL TIME (100);
END;
1* IF BUSY FLAG HAS BEEN CLEARED. THEN A CA HALT~SAVE
WAS EXECUTED.
IF SO. PRINT SAVED TP; IF NOT. ABORT

174

2

IF CPDAT(SHL(ONETWO.3) + 1) (> 0
THEN
DO;
CALL STRINGOUT(@ABORT)/
END;

175
176
177

2
3
3

178
17.9
180

2
3
3

181

3

CALL HEXOUT(PPP
... CI

11JJ

-

_AD"

II

AwA..

I

r-:---------,------1..
.-----+-t---------I"

""

I

.------+--h----I;,.

>

I

,-----(....1--1 f - -

.- ~7-'1!.,J, 1!
8281

-

~

8283

_ ,,;j

L

,

A

~J- .,; l:i

L--DTIR82BB

L....-.,.,.---'
... ~

I

~ ~ m.

.!.

I~

~=;nF======~r=======~~============~~~~~

(

LOCAl BUS

~------.-_--l..

Ii
a
i'

.-------h~---l"
". •
§

I

jl:r i

'i

I

IIH4

I2tIIt

r----------------------------------~~

~?L,. ~ .J -... lij : jI

-

..7

au

L....-DT1R8111

nn~h h· R D " :

;1

''---

."1- ACE

~nlnh iR,-

----------------

--------

--------

'0'

-----../

I

r---:. . ------- -------

ADDRESS BUS

III

I

i~'~~
----~ IJ
I TA'-- - - - - - - - ,

~ ~J r,'r
S"~""A<-'...J..L.-!~~ - iU I1:U Iil iR,r-

DTIii.

DON

8218

82811

PAIORITY3

RD"

-

u~~ mr-r'" n~nl~

~

"':1"
ilh

~

L -_ _---+~---IftB

10

n

d§
~

""

I~

II

1

II

I

r

K

r-

v

l- f- I - - I- r-

~
~

rr-

f=
f=
l-

I-

r- r-

~ ~
r-

1

f= I

I

rr- r-

I

7' 2".:-

.""'.
."'''''''

~

I

~

SYSTEM

I

I
II
I

I

:

C=A~======~~=============='~====~~r_I-'1

L ____________________________________ J
Figure 8. Multiprocessing System With 8289 In Single Bus Mode

00

r---- - ----,

I

I

I

I

r

I
I
:

__ J

i0.Hz
CUlCK

: )

II

~ I

f II~

'--------+-''---------1''
:

II"Jj.,J

OATA8US

I

f

~1==~II======~~,~~=====i~~~==~II~II~I==~cl~~~N~D~~======~I~I~I~I====~~>~~I~I==~~~

ir

I

U i

'---,

1-"

~..11.-

I

11214

l21li

-41------"11'------- t::--·nr--I~,.Y--------.J --- r=------jj------ 1~--- - ,L£. __ l!#~
m

_

:I

2

'",OR"'

ENCODER

.,jJ,.
DECODER

1

I
I

PRIORITY RESOLVING

I
I

I
I

I
I
I
I

L __ ~D~E~~L~ _ _ .J

AP-51

BREa

ARBITER #1

BREa
ARBITER #2

L....../-....... I-----lr--+-I2 of TI and BREQI occurs I BClK (min)
to 2 BClKs (max) thereafter. Depending upon where status occurs
with respect to clock determines how long a time exists between
status and <1>2 of n, and is anywhere from V2 CLK (min) to I ClK
(max).
tRequest originates off of T2·q,1 and BREQI occurs I BClK (min) to
2 BCLKs (max) thereafter. The same reasoning as used in the lOB
mode is valid here:
Delay
(Max)

Delay
(Min)

Bus Release (BREO!)

Mode

Higher Priority (BPRN I)

All

2 CLKs+
2 BCLKs

I CLK+
I BClK

lower Priority (CBRQI)

All

2 CLKs+
2 BCLKs

I CLK+
I BCLK

Surrender occurs once the proper surrender conditions exist.

Table 1. Surrender and Request Time Delays
One signal which has been basically ignored to this
point is CBRQ. CBRQ, like BUSY, is an open-collector
signal from the arbiter which is tied to the CBRQ Signals
of the other arbiters and to a pull-up resistor (see Figure
8). CBRQ is both an input and an output. As an output,
CBRQ serves to instruct the arbiter presently on the bus
that another arbiter wishes to acquire the bus. As an input, CBRQ serves to instruct the arbiter presently on the
bus that another arbiter wants the bus. CBRQ is an input
or output, dependent on whether the arbiter is on the
bus or not (respectively), and is issued as a function of
BREQ. Thus, a lower priority arbiter requesting the bus
already controlled by a higher priority arbiter will pull
CBRQ low, as well as BREQ. Even a higher priority arbiter will pull CBRQ low until it acquires the bus. Note,
however, that the higher priority arbiter will acquire the
bus through the reassignment of priorities - it being
given priority and the other arbiter presently on the bus
losing it. In effect, CBRQ serves to notify the arbiter that
an arbiter of lower priority wants the bus.
If the arbiter presently on the bus is configured to react
to CBRQ and the proper surrender conditions exist, the
bus is released. When releasing the bus, the arbiter also
turns off its BREQ (BREQ goes high) in order to allow
priority to be established to the next lower arbiter requesting the bus. Such is the case shown in Figure 9.
Whereas it was assumed that the proper surrender conditions did not exist for arbiter 2 when it had the bus, it
is assumed that the proper conditions do exist during
the time that arbiter 1 has the bus. Arbiter 2 had to give
up the bus because an arbiter of higher priority was re-

questing it. Arbiter 1 surrenders the bus because the
proper surrender conditions exist and a lower priority arbiter requested the bus by pulling CBRQ low. This is an
assumed condition which is not otherwise shown in
Figure 9. This is not an unrealistic condition. Normally,
a higher priority arbiter will acquire the bus through the
reassignment of priorities, while lower priority arbiters
acquire the bus through CBRQ.
Digressing for a moment, the 8289 Bus Arbiter will not
voluntarily surrender the bus (except when the processor halts execution). As a result, it has to be forced off
the bus. The 8289 Bus Arbiter does not generate a BREQ
for each cycle. It generates a BREQ once and then
hangs onto the bus. To do otherwise would require that
BREQ be dropped (go high) after each transfer cycle so
that if it did need to do another transfer cycle, another
arbiter would automatically be assigned priority. This
approach, however, entails certain overhead. Command
to address setup and hold time must be prefixed and appended to each transfer cycle. Each transfer cycle
would be characterized by first acquiring the bus, then
establishing the setup time requirements, finally performing the transfer cycle, establishing the hold time requirements, and then releasing the bus (see Figure 10).
If another transfer cycle was to immediately follow and
if the arbiter still had priority, then the whole above procedure would be repeated. The end result would be
wasted time as hold times following setup times (see
Figure 10A). The approach taken by the 8289 Bus Arbiter
of having to be forced off the bus, even when it is not
using the bus (Le., forced off by a lower priority arbiter),
provides for greater bus efficiency. A lower priority arbiter having to force off another arbiter that is not using
the bus but just hanging on to it, may not seem very efficient. In actuality it is a good trade-off. In many multimaster systems some bus masters occasionally demand the bus, while others demand the bus constantly.
The bus master which constantly demands the bus may
momentarily need not to access the bus. Why should
that arbiter surrender the bus when chances are that the
other bus masters which occasionally access the bus
don't want it at the time? If it doesn't give up the bus,
then it can momentarily cease access to the bus and
then continue, without any performance penalty of having to reestablish control of the bus. The greater bus efficiency that it affords is well worth the added complexity (Figure 10B).
Returning to Figure 9, the combination of the proper surrender conditions existing and CBRQ being low, forced
the higher priority arbiter, arbiter 1, off the bus. Arbiter
2, being of next higher priority and wanting the bus, acquired the bus on clock edge N + 1. If arbiter 1 decides
to re-access the bus, it would reacquire the bus through
the reassignment of priorities. This is not the case
shown in Figure 9. Arbiter 1 has decided that it does not
need the bus and does not renew its BREQ. Arbiter 2,
having acquired the bus through CBRQ, is now the
highest priority arbiter requesting the bus. As can be
seen it is not the only arbiter requesting the bus. Arbiter
3 is still patiently waiting for the bus and CBRQ remains
low. The same conditions that forced arbiter 1 off the

A-122

AP-51
the bus, the processor activates its status lines which in
turn enables the request input. Depending upon the
phase relationship between the occurrence of status (request active) and BClK, BREQ appears one to two
BCIKs later. As shown in Figure 12, the phase relationship between request and BClK is such that the BRQ1
flip-flop mayor may not catch request on the first
BClK."

bus for arbiter 2 now forces arbiter 2 off the bus for arbiter 3_ When the proper surrender conditions exist, arbiter 2 releases its BREQ and surrenders the bus to arbiter 3. Arbiter 3 acquires the bus on clock edge P + 1
and releases its CBRQ. Since no other arbiter wants the
bus (I.e., there is no other arbiter holding CBRQ low),
CBRQ goes high (inactive). This would have also been
true when arbiter 2 acquired the bus and released its
CBRQ if arbiter 3 didn't want the bus.

If BRQ1 flip-flop does catch the request, then one eeIK
later, BREQ goes low and one BClK after that, ~
goes low (it is assumed that priority is immediately
granted and that the bus is available). If BRQ1 flip-flop
does not catch the request, then request is caught on
the next BClK and BREQ goes low one BClK later, followed by BUSY which also goes low one BClK later.
Note that BREQ and BUSY track, as BREQ is an input
term for BUSY. During bus acquisition, the surrender
flip-flop is false (SURNDR Q= low) and AEN follows
BUSY.

In the Single interface, the arbiter monitors the processor's status lines, which are activated whenever the
processor performs a transfer cycle. The arbiter, on
detecting the status lines going active, will issue a
BREQ if the status is not the HALT status. If the processor issues the HALT status, the arbiter will not request the bus, and if it has the bus, will release it.
This effectively concludes how arbiters interact to one
another on the bus. Having examined the processor-toarbiter interface, and arbiter-to-MUlTIBUS (arbiter-toarbiter) interaction, one interface is left, the internal
interface of processor-related signals to that of
MULTI BUS-related signals.

Once the bus is acquired, the surrender circuitry is
enabled so that when a valid surrender condition exists,
the bus can be surrendered. The surrender circuitry synchronizes the surrender request to the processor's
clock and drives SURNDR low. Like the acquisition circuitry, it takes from one to two processor clocks to generate SURNDR and depends upon the phase relationship between the surrender request and the processor's
clock.

An important pOint to remember is that the processor
has its own clock (ClK) and the multi-master system
bus has its own (BClK). These two clocks are usually
out of phase and of different frequencies. Thus, the arbiter must synchronize events occurring on one interface to events occurring on another interface. As a
result of this back and forth synchronization, ambiguity
can arise as to when events actually do take place.

'The two bus request flip·flops, BRat and BRa2, are edge·triggered,
high resolution flip-flops and serve to reduce the probabW!X...2.! walkout
down to an acceptable level. Walkout occurs because BCLK is asynchronous with respect to request. If walkout does occur on BRQ1 flipflop, the probability is high that the BRat flip·flop will resolve itself
prior to BRa2 flip-flop being triggered. Even if BRat flip·flop did not
quite resolve itself, the probability of BRa2 flip·flop walking out to an
unacceptable point in time is itself low.

Very simply, the 8289 arbiter operation can be represented as two events, requesting and surrendering.
Figure 11 is a representation of the timing relationships
involved. The request input is a function of the processor's clock and the surrender input is a function of
either the bus clock or the processor's clock. To request

1'1

Ib)

a) BUS UTILIZATION AS A RESULT OF HAVING TO REQUEST AND RELEASE THE BUS

FOR EACH TRANSFER CYCLE. THIS PERMITS LOWER PRIORITY ARBITERS EASY
ACCESS TO THE 8US SHOULD THE HIGHER PRIORITY ARBITER NO LONGER NEED
THE BUS. HOWEVER, BUS EFFICIENCY IS POOR DUE TO THE ARBITER THRASING ON
AND OFF OF THE BUS FOR EACH TRANSFER CYCLE.

b) 8289 BUS UTILIZATION IS MORE EFFICIENT IN THAT THE ARBITER HAS ONLY TO
ACQUIRE THE BUS ONCE. THE 8289 HANGS ONTO THE BUS UNTIL FORCED OFF.
THIS APPROACH ADDS A LITTLE MORE COMPLEXITY TO THE SYSTEM INASMUCH AS
SOME MEANS MUST BE PROVIDED FOR LOWER PRIORITY ARBITERS TO FORCE THE
HIGHER PRIORITY ARBITER OFF OF THE BUS WHEN IT IS NOT USING IT. THE ADDED
COMPLEXITY IS WELL WORTH THE BUS EFFICIENCY AND SYSTEM FLEXIBILITY IT
AFFORDS. THE 8289 ARBITER CAN BE CONFIGURED TO HAVE THE TRANSFER TIMING
AS SHOWN IN (8) (IMITATING THE METHOD 8218 AND 8219 USES, BUS ARBITERS FOR
8080 AND 8085 RESPECTIVELY) BY STRAPPING ANYRQST HIGH AND CBREQ LOW.

Figura 10. Two Techniques For Doing Multlbus Trans.er Cycles

A-123

AP-5'1
BPRN

~
S,

BRQl FF
REQUEST
'(elKI

J

0

r---

Q

....

....

Q

~j

~j

-

0'----

BREQ

BUSY FF

~S

R

..........

Q

;.

BjJSY

i>1

'----

R

'----

.,-

ACQU ISITION
CIR CUITRY

- - - - - - - - - - - - - ' - - - - - - - - ,..- -'--

SURRE NDER
CIRC UITRY

----

r-Q

0

Q

0

SURRENDER
REQUEST

I

r<~

1<1--

-'---

BClK

f(BCLK, elK)

---

SURNDR

0-

-

'----

SAMPLE

RESOLVE

ClK

~

THIS CONCEPTUAL DIAGRAM IS PROVIDED FOR AIDING IN UNDERSTANDING
CLOCK AND BUS CLOCK RELATED EVENTS. IT DOES NOT REPRESENT THE
ACTUAL SCHEMATIC OF THE 8289 DEVICE, AND IS FOR CONCEPTUAL
PURPOSES ONLY.

AEN

Figure 11. Symbolic Representation of Internal 8289 Timing

ClK

mroR't
'(eLK)

Il

/

\

BC:[K

0!

!®
0!

!®

0!

!®

*WHEN THE REQUEST OCCURS SIMULTANEOUSLY WITH BClK, BClK MAY OR
MAY NOT CATCH THE REQUEST. IFIT DOES, THE WAVEFORMS FOllOW
THOSE SHOWN DESIGNATED BY
,IF NOT, THE REQUEST IS PICKED UP
ON THE NEXT EDGE OF BC:[K AND THE WAVEFORMS FOllOW THOSE
SHOWN DESIGNATED BY @ .

®

Figure 12. Results Of An Asynchronous Event

A~124

AP-51
Having synchronized the surrender request to the processor's clock to generate SURNDR, SURNDR is then
synchronized to BClK to reset the BUSY and BRQ flipflops. When BUSY-Q goes low, the surrender circuitry is
reset which in turn re-enables the request input. The timing in Figure 13 shows the surrender request input
gOing high on the falling edge of the clock. If the Sample
flip-flop was able to catch the surrender request on the
edge of clock 1, then SURNDR would be generated (go
low) on clock edge 2. If not, SURNDR would be generated on clock edge 3. SURNDR going low on clock edge
2will be, for ease of discussion, referred to as SURNDR
a and SURNDR going low on clock edge 3 will be referred to as SURNDR b. As can be seen from Figure 13,
SURNDR a just happens to go low on BClK edge 2.
Since SURNDR is used to reset the BRQ flip-flops,
which are clocked by the falling edge of BClK, the
BRQ1 flip-flop may or may not catch SURNDR a on
BClK edge 2. If it does, then BRQ and BUSY go high on
BClK edge 3 which, for convenience, will be called
BREQ a or BUSY a. If not, theh BREQ and BUSY will go
high on BClK edge 4, which will be referred to as BREQ
b or BUSY b, respectively. SURNDR b occurs early
enough to assure that BUSY and BREQ are reset on
BClK edge 5, which will be referred to as BUSY b1 and

BREQ b1. Depending upon when BUSY goes high, determines when the surrender circuitry is reset and how
soon the next BREQ can be generated. BUSY a1 causes
SURNDR c to occur where shown and SURNDR c in turn
would allow the earliest bus request to occur at BREQ
c1. At the other extreme, BUSY b1 allows the earliest
bus request to occur at BREQ e1.
Table 1 summarizes the maximum and minimum delays
for bus request, once the proper request and surrender
conditions exist. Table 2 lists the proper surrender conditions.
~~--~-.--.-----~

Mode

Surrender Conditions

Single

HALT state, loss of BPRN. TI.CBREO

lOB

HALT state, loss of BPRN, TI·CBREO,
110 Command.CBRO

RESB

HALT state, loss of BPRN, TI·CBREO,
(SYSBIRESB ~ O)·CBRO

10B·RESB

HALT state, loss of BPRN, TI·CBREO,
(SYSBIRESB ~ O)·CBREO,
110 Command.CBRO

Table 2. Surrender Conditions

ClK

SURRENDER
REQUEST

·i ·i bl

,

BREQI
(EARLIEST THAT BREQ COULD GO ACTIVE AFTER BUS RELEASE)

Figure 13. Asynchronous Bus Release

A-125

\

\C1
\d1
\e1
...... _
........ _ _ _ _ _ _ _ .1...-_

AP-51
lOB INTERFACE

Now that the processor·arbiter, arbiter·system bus and
internal arbiter timings have been discussed, it is ap·
propriate to consider the other interfaces that the 8289
Bus Arbiter provides.
In the lOB mode, the processor communicates and con·
trois a host of peripherals over the peripheral bus. When
the I/O processor needs to communicate with system
memory, it is done so over the system memory bus. Fig·
ure 14 shows a possible 1/0 processor system con·
figuration, utilizing the 8089 I/O processor in its
REMOTE mode. Resident memory exists on the periph·
eral bus in order that canned I/O routines and buffer
storage can be provided. Resident memory is treated as
an I/O peripheral. When a peripheral device needs ser·
vicing, the I/O processor accesses resident memory for
the proper I/O driver routine and services the device,
transmitting or storing peripheral data in buffer storage
area of resident memory. The resident memory's buffer
storage area could then be emptied or replenished from
system memory via the system bus. Using the lOB inter·
face allows an I/O processor the capability of executing
from local memory (on the peripheral bus) concurrently
with the host processor.
Timing in this mode is no different from timing in the
SINGLE BUS mode. The only difference lies in the reo
quest and surrender conditions. The arbiter extends the
single bus mode conditions to qualify when the system
bus is requested and adds on additional surrender con·
ditions. The system bus is only requested during sys·
tem bus commands (the arbiter decodes the processor's
status lines) and, in addition to the other surrender

XACK(IIO 8 U 5 ) - - - - - - I

terms, the arbiter permits surrender to occur during I/O
bus (or local bus) commands, when the I/O processor is
using its own local bus.
Like the arbiter, the bus controller must also be in·
formed of the mode it is operating in. In the lOB mode,
the 8288 bus controller issues I/O bus commands in·
dependently of the state of AEN from the arbiter. It is
assumed that all I/O bus commands are intended for the
I/O bus and hence there is a separate I/O command bus
from the controller. All I/O bus commands are sent
directly to the I/O bus and are not influenced by AEN.
System bus commands are assumed as going to the
system bus. Since system bus commands are directed
to the system bus, they must still be influenced by AEiiI
and the arbitration mechanism provided by the 8289.
As an example, suppose the processor issues an I/O bus
command. The 8288 Bus Controller generates the
necessary control signal to latch the I/O address and
configure the transceivers in the correct direction. In the
lOB mode, the multiplexed MCE/PDEN pin of the 8288
becomes PDEN (peripheral data enable) and serves to
enable the I/O bus's data transceivers during I/O bus
commands. DEN similarily serves to enable the system
bus's data transceivers during memory commands.
PDEN and DEN are mutually exclusive, so it is not possi·
ble for both sets of transceivers to be on, thereby
avoiding contention between the two sets. Since the I/O
bus commands are generated independently of AEN In
the lOB mode, the I/O bus has no delay effects due to
the arbiter. During this time in which the processor is
accessing memory the arbiter, if it already has the bus,
will permit it to be surrendered to either a higher or
lower priority independently of where the processor is in

I - - - - - - - - - - - - - - - { )tACK

MULTI·MASTER SYSTEM 8US

8289
BUS

ARBITER

K=====) MULTI·MASTEA
CONTROL
BUS

~=====:}MULTI'MASTER
SYSTEM

COMMAND
BUS

MULTI-MASTER
SYSTEM8US

'0

ADDRESS
BUS

~==~~~======JMULnMAsn:R
SYSTEM
ADDRESS

r i - - - - - \ ~:;.VARBlE

10
DATA
BUS

aus

K===========;MULfl.MASTEA
SYSTEM

DATA
BUS

Figure 14. 8289 Configured In 110 Bus Mode With 8089 1/0 Processor

A-126

AP-51
its transfer cycle (i.e., independent of the machine
state).' If the arbiter does not already have the bus, it
will make no effort to acquire the bus.
If the processor issues a memory command instead, the
same set of events take place, except that 1) the system
bus's data transceivers are enabled instead of the
peripherals bus's data transceivers, and 2) when the
command is issued depends upon the state of the ar·
biter. In both cases of I/O bus commands and system
bus commands, the address generated for that com·
mand is latched into both sets of address latches, the
system bus's address latches, and the peripherals bus's
address latches. For each command (regardless of com·
mand type), an address is put out on the I/O bus and on
the system bus if the arbiter has the bus at that particu·
lar time. However, the bus controller only issues a command to one of the buses and hence, no ill effects are
suffered by addressing both buses.
If the arbiter already has the system bus when a system
bus command is issued, no delays due to the arbiter wi II
be noticed by the processor. If the arbiter doesn't have
the bus and must acquire it, then the processor will be
delayed (via the system bus command being delayed by
the bus controller through AEN from the arbiter) until
the arbiter has acquired the bus. The arbiter will then
permit the bus controller to issue the command and the
transfer cycle continues.

RESBINTERFACE
The non-IIO processors in the 8086 family can communicate with both a resident bus and a multi-master system
bus. Two bus controllers would be needed in such a configuration as shown in Figure 15. In such a system configuration the processor would have to access to
memory and peripherals of both buses. Address mapping techniques can be applied to select which bus is to
be accessed. The SYSB/RESB (system bus/resident bus)
input on the arbiter serves to instruct the arbiter as to
whether or not the system bus is to be accessed. It also
enables or disables commands from one of the bus controllers.
In such a system configuration, it is possible to issue
both memory and 110 commands to either bus and as a
result, two bus controllers are needed, one for each bus.
Since the controllers have to issue both memory and 110
commands to their respective buses, the lOB options on
the controllers are strapped off (lOB is low). The arbiter, too, has to be informed of the system configuration in order to respond appropriately to system inputs
and has its RESB option strapped on (RESB is high). The
arbiter's lOB option is strapped inactive (lOB is high).
Strapping the arbiter into the resident bus mode
enables the arbiter to respond to the state of the
SYSB/RESB input. Depending upon the state of this input, the arbiter either requests and acquires the system
bus or permits the surrendering of that bus.
·Under other circumstances, bus surrendering wou!,d only be permitted
during the period from where address to command hold time has been
established just prior to where the next command would be issued.

In the system shown in Figure 15, memory mapping
techniques are applied on the resident bus side of the
system rather than on the multiprocessor or system
bus side. As mentioned earlier in the lOB interface, both
sets of address latches (the resident bus's address
latches and the system bus's address latches) are
latched with the same address; in this case, by their
respective bus controllers.' The system bus's address
latches, however, mayor may not be enabled depending
upon the state of the arbiter. The resident bus's address
latches are always enabled, hence the address mapping
technique is applied to the resident bus.
Address mapping techniques can range in complexity
from a single bit of the address bus (usually the most
significant bit of the address), to a decoder, to a PROM.
The more elaborate mapping technique, such as PROM,
provides segment mapping, system flexibility, and easy
mapping modifications (simply make a new PROM).
In actual operation, both bus controllers respond to the
processor's status lines and both will simultaneously
issue an address latch strobe (ALE) to their respective
address latches. Both bus controllers will issue command and control signals unless inhibited. The purpose
of the address mapping circuitry is to inhibit one of the
bus controllers before contention or erroneous commands can occur. The transceivers are enabled off the
same clock edge the commands are issued, namely <1>1
of T2 (Figure 16). The address is strobed into the address latches by ALE. ALE is activated as soon as the
processor issues status, and is terminated on <1>2 of of
T1. From when ALE is issued, plus the propagation
delay of the address latches, determines where the address is valid. The time from which the address is valid
to where control and commands are issued determines
how much settling time is available for the address mapping circuitry. The mapping circuitry must inhibit (via
CEN) one of the bus controllers prior to where controls
and commands are issued. Part of the settling time
(see Figure 16) is consumed as a setup time requirement
to the bus controllers. As it turns out, CEN (command
enable) can be disqualified as late as on the falling edge
of clock (the leading edge of <1>1 of T2) without fear of the
bus controller issuing any commands or transceiver
control signals. In systems (8 MHz) where less time is
available for the address mapping circuitry, the address
latches can be bypassed, hooking the mapping circuitry
straight onto the processor's multiplexed address/data
bus (the local bus) and using ALE to strobe the mapping
circuitry. This would avoid the propagation delay time of
the transceivers. Besides needing to inhibit one of the
bus controllers, the arbiter needs to be informed of the
address mapping circuitry's decision. Depending upon
that decision, the arbiter acquires or permits the release
of the system bus.
• A simpler system with an 8086 or 8088 can exist, if it is desirable to
only have PROM, ROM, or a read only peripheral interface on the resi·
dent bus. The 8086 and 8088 additionally generate a read signal in con·
junction with the 8288 control signals. By using this read signal and
memory mapping, the 8086 or 8088 could operate from local program

A-127

store without having the contention of using the system bus.

AP-51

o
8284
CLOCK

XACK

-----+---~---- XACK MULTI·MASTER SYSTEM BUS

RESIDENT BUS

MUlHMIj.STER SYSTEM
BUS CONTROL

RESIDENT COMMAND ; ' -_ _ _L

MULTI·MASTER SYSTEM
COMMAND BUS

BUS

MULTI-MASTER
SYSTEM BUS

RESIDENT ADDRESS I~--~

BUS

MULTI-MASTER SYSTEM
ADDRESS BUS

'<----------1

'BY ADDING ANOTHER 8289 ARBITER AND CONNECTING ITS AEN TO THE 8288
WHOSE KEN IS PRESENTLY GROUNDED, THE PROCESSOR COUto HAve ACCESS
TO TWO MUL TJ.MASTER BUSES

Figure 15. 8289 Configured In Resident Bus Mode

T4

T1

T2

eLK

PROCESSOR
STATUS

ALE (8288)

ADDRESS (8282,3)

COMMAND, CONTROL (8288)
TCY

jTCLAY

+ DELAY TIME THROUGH LATCHES] + 5 '" TSETTUNG

\

AVAILABLE
ADDAESS MAPPING

SETTLING TIME

Figure 16. Time Avairabl. For Address Mapping Prom

A-128

AP-51
The arbiter is informed of this decision via its
SYSB/RESB input. If the memory mapping circuitry
selects the resident bus, then SYSB/RESB input to the
arbiter and CEN input of the system bus controller are
brought low; and the CEN Input of the resident bus con·
troller is brought high. The commands and control
signals of the resident bus are now enabled and those of
the system bus are disabled. In addition, with the arbiter
being informed that the transfer cycle is occurring on
the resident bus, the system bus is permitted to be sur·
rendered. Glitching is permitted on the SYSB/RESB input of the arbiter up until ¢1 of T2. Thereafter, only clean
transitions can occur on the input.· So, if mapping circuitry can settle prior to ¢1 of T2, there is no need to be
concerned over glitching. If the mapping circuitry is
unable to settle prior to this time, then the designer
must guarantee a clean transition on the SYSB/RESB input.
INTERFACE TO TWO MULTI-MASTER BUSES
The interface of an 8086 family processor to two multisystem buses is simply an extension of the resident bus
interface. The only difference is that now two arbiters
are needed, one for each multi-master bus, and the address mapping circuitry must acquire its input straight
off the processor's multiplexed address/data bus (the
local bus), using ALE as an address strobe input. Figure
17 depicts how such a system might be configured.
Figure 17 illustrates the use of the 8289 in a system environment in three of its four modes. The host 8086 CPU
(priority 3) is using the 8289 in its single bus multimaster mode, while an 8089 I/O processor is using the
8289 in its lOB mode. A work station based on an 8088
processor uses the 8289 in it system/resident bus mode.
This diagram represents a hypothetical system wherein
there can exist more than one work station (only one
shown). Each work station shares system resources and
I/O. The lowest priority processor (8086) would provide
supervisory functions and system control, i.e., allow
operator intervention into the system resources. A work
station would call in assemblers and compilers or application programs as needed. When compiled or
assembled, the results are transferred to the I/O station
for output, thus freeing up a work station for another
user.

*In certain memory mapping techniques, the CENs of the bus control·
lers are controlled differently from the SYSB/RESB input of the arbiter.
In short, CEN Is brought low automatically to both bus controllers,
thereby disabling their command and control outputs. This permits a
longer settling time for the memory mapping Circuitry, since both con·
trollers are disabled. When the mapping circuitry settles, sometime
after 
II>
~

g"

u
AEN

CEN
CLK

(

MULTIBUS
COMMANDS

8288
CONTROLLER
1

So-52

~

-

Dr/A

DEN

--

I: I
t

;1.
"f

'-_
~

r

r--

AEN

CEN

LATC<

,--

elK

8288

CONTROLLER
2

DT/A

DEN

ALE

~

l
OE

8283
LATCH
(2 OR 3)

OE

Ii

AODRIDATA

I

¢

DATA

STB

8283

1\

ADDRESS

LATCH

f..

)

(2 OR 3)

r

~

+

~

I---

ALE

STB

ADDRESS

MUL TIBUS
COMMANDS

So-52

I'

y
6

t

t

6

OE

DTIR

DT/R

OE

8287
TRANSCEIVER

(1 OR 2)

A

1\

~

V

MEMORY MAPPING DECODING IS SHOWN TAKING PLACE DIRECTLY OFF OF
THE PROCESSOR'S LOCAL MULTIPLEXED ADDRESSIDATA BUS.

Figure 17. Using 82895 To Interface To Two Multimaster System Buses.

A-l30

8287
TRANSCEIVER
(1 OR 2)

DATA

}..

V

THIS PAGE LEFT INTENTIONALLY BLANK

A-131

AP-51

r--------------------,I

I
I

I
I
I
I
I
I

fj

8086

SO 51

I

I

RE~~;

I
-=-1

S2

I

I
I

iI

I

i)
/

I
I
I

I
I

L __________________ _

r-------------------l

I
I

~

r;;;b;--*"

I

11

iI

I
I
I I
I I

/

V

I

I

L ___________________ JI

Figure 18. 8289 Used In Each Of 3 Modes, Single Bus, 110 Bus, and Resident Bus Modes Implementing A Hypothetical Multlmaster Bus System

A-132

AP-51

10MH.
CLOCK

r------------..,

I

I

I

I

:======~FF~~$§8!~' !
I

I

I

2

,

I
I

PRIORITY

,."."

""."

I

321

iI

L __ ~-::'E,=,R~~___

I I I I I I I(

SYSTEM
,~

IIIIII I ~

= IIIII
==
=~
=

I I I II I I (

SYSTEM

MEMORY

IIIIII I ~

r-ji--;-----------·
IlciEN2

II
i

-i

-- --

ROV2

.28<1

01lQ1_
OllQ2_

READY_AEADY
CLK_...-CLK
8018

J

W+Ul-I-J-L~i[~~r:'~-"---J'"= =~ "

==
==
¢: =

- -

'I

_.J

III.;=:L-

==
~

-

I

I
PAIORITYRESOLVING

I

~ r-'

~S.-

~~ILK

~ICK

STORAGE DEVICES
HARD. FLOPPY DISKS

ii

N.~=I2H

~~:~

o

:

m:

4

I-

ACK

.
..

CLK_

iNTO I/D ADDAUS

~

IIeACK

SPACE

..!.
STORAGE DEVICE

CONTIIOLLrlt

I

aERVICEREaUEST

IN'~~~~~PUT I
CONTFIOUER

SEAYICEREOUEST

1r1l1r

=1--'

I

r-----L---

DTIA

I

MEMORY
ADDREISMAPPED

1r1l1r

ii

~====:::~

INPUTIOUTPUTDE

,~".6:i
~I~'"''''''

MAG.TAPEI
CASIIiIIOTTU

~=

I
L---1AEO

- - - .//1

~:fl

DTIA

"--tJ=;"

'U'
PRIOAIIV'

rr
I

.m

~

~-----------------~

Figure 18. 8289 Used In Each Of 3 Modes, Single Bus, 1/0 Bus, and Resident Bus Modes Implementing A Hypothatlcal Multlma.ter Bus System

A-133/ A-134

APPLICATION
NOTE

Ap·59

September 1979

© Intel Corporation, 1979

121500-001

A-135

AP-59

Using the 8259A
Programmable
Interrupt Controller

Contents
INTRODUCTION
CONCEPTS
MeS80 TM·8259A Overview
MCS85™·8259A Overview
M CS86/88 TM·8259A Overview
FUNCTIONAL BLOCK DIAGRAM
Interrupt Registers and Control Logic
Other Functional Blocks
Pin Functions
OPERATION OF THE 8259A
Interrupt Vectoring
MCS80/85 Mode
MCS86/88 Mode
Interrupt Priorities
Fully Nested Mode
End of Interrupt
Automatic Rotation
Specific Rotation
Interrupt Masking
Interrupt Triggering
Level Triggered Mode
Edge Triggered Mode
Interrupt Status
Reading Interrupt Registers
Poll Command
Interrupt Cascading
Cascade Mode
Special Fully Nested Mode
Buffered Mode
PROGRAMMING THE 8259A
Initialization Command Words (ICWs)
Operational Command Words (OCWs)
APPLICATION EXAMPLES
Power Fail/Auto Start with Battery Back·Up RAM
78 Level Interrupt Structure
Timer Controlled Interrupts
CONCLUSIONS
APPENDIX A
APPENDIX B

A-136

AP·59
INTRODUCTION
The Intel 8259A is a Programmable Interrupt Controller
(PIC) designed for use in real·time interrupt driven
microcomputer systems. The 8259A manages eight
levels of interrupts and has built·in features for expan·
sion up to 64 levels with additional 8259A's. Its versatile
design allows it to be used within MCS·80, MCS·85,
MCS·86, and MCS·88 microcomputer systems. Being
fully programmable, the 8259A provides a wide variety of
modes and commands to tailor 8259A interrupt process·
ing for the specific needs of the user. These modes and
commands control a number of interrupt oriented func·
tions such as interrupt priority selection and masking of
interrupts. The 8259A programming may be dynamically
changed by the software at any time, thus allowing com·
plete interrupt control throughout program execution.
The 8259A is an enhanced, fully compatible revision of
its predecessor, the 8259. This means the 8259A can use
all hardware and software originally designed for the
8259 w.ithout any changes. Furthermore, it provides ad·
ditional modes that increase its flexibility in MCS·80
and MCS·85 systems and allow it.to work in MCS·86 and
MCS·88 systems. These modes are:
•
•
•
•
•

MCS·86/88 Mode
Automatic End of Interrupt Mode
level Triggered Mode
Special Fully Nested Mode
Buffered Mode

Each of these are covered in depth further in this appli·
cation note.
This application note was written to explain completely
how to use the 8259A within MCS·80, MCS·85, MCS·86,
and MCS·88 microcomputer systems. It is divided into
five sections. The first section, "Concepts", explains
the concepts of interrupts and presents an overview of
how the 8259A works with each microcomputer system
mentioned above. The second section, "Functional
Block Diagram", describes the internal functions of t.he
8259A in block diagram form and provides a detailed
functional description of each device pin. "Operation of
the 8259A", the third section, explains in depth the
operation and use of each of the 8259A modes and com·
mands. For clarity of explanation, this section doesn't
make reference to the actual programming of the 8259A.
Instead, all programming is covered in the fourth sec·
tion, "Programming the 8259A". This section explains
how to program the 8259A with the modes and com·
mands mentioned in the previous section. These two
sections are referenced in Appendix A. The fifth and
final section "Application Examples", shows the 8259A
in three typical applications. These applications are
fully explained with reference to both hardware and soft·
ware.
The reader should note that some of the terminology
used throughout this application note may differ
slightly from existing data sheets. This is done to better
clarify and explain the operation and programming of
the 8259A.

1. CONCEPTS
In microcomputer systems there is usually a need for
the processor to communicate with various Input/Out·

put (I/O) devices such as keyboards, displays, sensors,
and other peripherals. From the system viewpoint, the
processor should spend as little time as possible servic·
ing the peripherals since the time required for these I/O
chores directly affects the amount of time available for
other tasks. In other words, the system should be
designed so that I/O servicing has little or no effect on
the total system throughput. There are two basic
methods of handling the I/O chores in a system: status
polling and interrupt servicing.
The status poll method of I/O servicing essentially in·
volves having the processor "ask" each peripheral if it
needs servicing by testing the peripheral's status line. If
the peripheral requires service, the processor branches
to the appropriate service routine; if not, the processor
continues with the main program. Clearly, there are
several problems in implementing such an approach.
First, how often a peripheral is polled is an important
constraint. Some idea of the "frequency·of·service"
required by each peripheral must be known and any soft·
ware written for the system must accommodate this
time dependence by "scheduling" when a device is
polled. Second, there will obviously be times when a
device is polled that is not ready for service, wasting the
processor time that it took to do the poll. And other
times, a ready device would have to wait until the proc·
essor "makes its rounds" before it could be serviced,
slowing down the peripheral.
Other problems arise when certain peripherals are more
important than others. The only way to implement the
"priority" of devices is to poll the high priority devices
more frequently than lower priority ones. It may even be
necessary to poll the high priority devices while in a low
priority device service routine. It is easy to see that the
polled approach can be inefficient both time·wise and
software·wise. Overall, the polled method of I/O servic·
ing can have a detrimental effect on system throughput,
thus limiting the tasks that can be performed by the
processor.
A more desirable approach in most systems would allow
the processor to be executing its main program and only
stop to service the I/O when told to do so by the I/O
itself. This is called the interrupt service method. In
effect, the device would asynchronously signal the proc·
essor when it required service. The processor would
finish its current instruction and then vector to the
service routine for the device requesting service. Once
the service routine is complete, the processor would
resume exactly where it left off. Using the interrupt ser·
vice method, no processor time is spent testing devices,
scheduling is not needed, and priority schemes are
readily implemented. It is easy to see that, using the in·
terrupt service approach, system throughput would in·
crease, allowing more tasks to be handled by the
processor.
However, to implement the interrupt service method
between processor and peripherals, additional hardware
is usually required. This is because, after interrupting
the processor, the device must supply information for
vectoring program execution. Depending on the proc·
essor used, this can be accomplished by the device tak·
ing control of the data bus and "jamming" an instruc·
tion(s) onto it. The instruction(s) then vectors the pro·

A-137

AP-59
gram to the proper service routine. This of course requires additional control logic for each interrupt requesting device. Yet the implementation so far is only in
the most basic form. What if certain peripherals are to
be of higher priority than others? What if certairi interrupts must be disabled while others are to be enabled?
The possible variations go on, but they all add up to one
theme; to provide greater flexibility using the interrupt
service method, hardware requirements increase.
So, we're caught in the middle. The status poll method
is a less desirable way of servicing 1/0 ,in terms of
throughput, but its hardware requirements are minimal.
On the other hand, the interrupt service method is most
desirable in terms of flexibility and throughput, but
additional hardware is required.
The perfect situation would be to have the flexibility and
throughput of the interrupt method in an implementation with minimal hardware requirements. The 8259A
Programmable Interrupt Controll,er (PIC) makes this all
possible.
The 8259A Programmable Interrupt Controller (PIC) was
designed to function as an overall manager of an interrupt driven system. No additional hardware is required.
The 8259A alone can handle eight prioritized in,terrupt
levels, controlling the complete interface between peripherals and processor. Additional 8259A's can be
"cascaded" to increase the number of interrupt levels
processed. A wide variety of modes and commands for
programming the 8259A give it enough flexibility for
almost any interrupt controlled structure. Thus, the
8259A is the feasible answer to handling 1/0 servicing in
microcomputer systems.
Now, before explaining exactly how to use the 8259A,
let's go over interrupt structures of the MCS-80, MCS-85,
MCS-86, and MCS-88 systems, and how they interact
with the 8259A. Figure 1 shows a block diagram of the
8259A interfacing with a standard system bus. This may
prove useful as reference throughout the rest of the
"Concepts" section.

I
INTERRUPT
RI!:QUESTS

Figure 1. 8259A Interface to Standard System Bus

1_1 MCS-80™-8259A OVERVIEW
In an MCS-80'-8259A interrupt configuration, as in
Figure 2, a device,may'cause an interrupt by pulling one
of the 8259A's interrupt request pins (IRO-IR7) high. If
the 8259A accepts the irlterruptrequest (this depends
on its programmed condition), the 8259A's INT (interrupt) pin will go high, driving the 8080A's INTpin high.
The 8080A can receive an interrupt request any, time,
since its INT input is asynchronous. The 8080A, however, doesn't always have to acknowledge an interrupt
request immediately. It can accept or disregard requests under software control using the EI (Enable Interrupt) or 01 (Disable Interrupt) instructions. These instructions either set or reset an internal interrupt enable
flip-flop. The output of this flip-flop controls the state of
the INTE (Interrupt Enabled) pin. Upon reset, the 8080A
interrupts are disabled, making INTE low.
At the end of each instruction cycle, the 8080A examines the state of its INT pin. If an interrupt request is
present and interrupts are enabled, the 8080A enters an
interrupt machine cycle. During the interrupt machine
cycle the 8080A resets the internal interrupt enable flipflop, disabling further interrupts until an EI instruction
is executed. Unlike normal machine cycles, the interrupt
machine cycle doesn't increment the program counter.
This ensures that the 8080A can return to the preinterrupt program location ,after the interrupt is completed. The 8080A then issues an INTA (Interrupt
Acknowledge) pulse via the 8228 System Controller Bus
Driver. ThislNTA pulse signals the 8259A that the 8080A
is honoring the request and is ready to process the interrupt.
The 8259A can now vector program execution to the corresponding service routine. This is' done during a sequence of the three INTA pulses from the 8080A via the
8228. Upon receiving the first INTA pulse the 8259A
places the opcode for a CALL Instruction on the data
bus. This causes the contents of the program counter to
be pushed onto the stack. In addition; the CALL instruction causes two more INTA pulses to be issued, allowing the 8259A to place onto the data bus the starting
address of the corresponding service routine. This
address is called the interrupt-vector address. The lower
8 bits (LSB) of the interrupt-vector address are released
during the second INTA pulse and the upper 8 bits
(MSB) during the third INTA pulse. Once this sequence
is completed, program execution then vectors to the
service routine at the interrupt-vector address.
If the same registers are used by both the main program
and the interrupt service routine, their contents should
be saved when entering the service routine. This includes the Program Status Word (PSW) which consists
of the accumulator and flags. The best way to do this is
to "P,USH" each register used onto the stack. The service routine can then "POP" each register off the stack
in the reverse order when it is completed. This prevents
any ambiguous operation when returning to the main
program.
Once the service routine is completed, the ma:in
program may be re-entered by using a normal RET
(Return) instruction. This will "POP" the original con-

A-13S

AP-59
uration. When an interrupt occurs, a sequence of three
INTA pulses causes the S259A to release onto the data
bus a CALL instruction and an interrupt·vector address
for the corresponding service routine. Other events that
occur during the SOSOA interrupt machine cycle, such as
disabling interrupts and not incrementing the program
counter, also occur in the SOS5A interrupt acknowledge
machine cycle. Additionally, the instructions for saving
registers, enabling or disabling of interrupts, and return·
ing from service routines are literally the same.

tents of the program counter back off the stack to
resume program execution where it left off. Note, that
because interrupts are disabled during the interrupt
acknowledge sequence, the EI instruction must be
executed either during the service routine or the main
program before further interrupts can be processed.
For additional information on the SOSOA interrupt struc·
ture and operation, refer to the MCS·SO User's Manual.
1.2 MCS·8S™_82S9A OVERVIEW

The SOS5A, however, has a different interrupt hardware
scheme as shown in Figure 3. For one, the SOS5A sup·
plies its own INTA output pin rather than using an addi·

An MCS·S5-S259A configuration processes interrupts
in much the same format as an MCS-SO-S259A config-

AO-1SI---------ADDRESS

B-US--------~

TO MEMORY AND 110

Ao
INTf-------------,
8259A

8080A

C E~ECT
cs

YlA

IRO -

INTERRUPT
REQUEST
INPUTS

8224

Figure 2. MCS·80 8259A Basic Configuration Example

TO MULTIPLEXED
Mesas FAMilY

riDb

L t

'fI' DL-_____~===-----------_".
:-l III I
I e: I

-

Xl
X2 REseT elK
REseT IN
OUT
A8-15t-r..,... . .r-_ _,

-

HOLD

-

HLDA

-

RDY

-

TRAP

-

ADDRESS BUS

E3

ALE
808SA

RST6.'

-

RST5.5

,.--- INTR
INTA

WR

E2

:2
20

A1

00 01 02 03 04 05 06

RST7.'

-

TO STANDARD MEMORY

AND OTHER 110

AD

j j
ADo.,

~,,_,..._ _...,

IO/MM ~---I----l

AO

07

Ij II!

110 SELeCT
MULTIPLEXED ADDRESS/DATA BUS

TO STANDARD MEMORY
110

~===:.=:;.=~==="'----~~---y,/ AND OTHER

I----..J

+5

Ro
'x
8259A SELECT

TO 1/0 " MEMORY

QUALIFIED BY IOiM

IT

INTERRUPT
REQUEST
INPUTS

TO SLAVE 8259A

Figure 3. MCS-85™ 8259A Balle Configuration Exc."pla

A-139

AP-59
tional. Chip, as the 8080A uses the 8228 System Controller Bus Driver. Another hardware difference is the
8085A has five hardware interrupt pins: INTR, RST 7.5,
RST 6.5, RST 5.5, and TRAP. The INTR (Interrupt Request)
pin is the equivalent to the 8080A's INT pin. The RST
(Restart) pins and TRAP pin are all restart interrupts
which vector program execution to an individual dedicated address when asserted. The important factor
associating these interrupts is their relative priority, as
shown below:
TRAP
Highest Priority
RST 7.5
RST 6.5
RST 5.5
INTR
Lowest Priority

tions. That is, a device can cause an interrupt by pulling
one of the S259A's interrupt request pins (lRO-IR7) high.
If the S259A honors the request, its INTpin will go high,
driving the 80S6/S0SS's INTR pin high. Like the S080A
and 8085A, the iNTR pin of the S086/S08S is asynchro·
nous, thus it can receive an interrupt any time. The
SOS6/8088 can also accept or disregard requests on
INTR under software control using the STi (Set Interrupt)
or CLi (Clear Interrupt) instructions. These instructions
set or clear the interrupt·enabled flag IF. Upon
8086/S0S8 reset the IF flag is cleared, disabling exte.rnal
interrupts on INTR. Beside the INTR pin, the S086/S0S8
provides an NMI (Non-Maskable Interrupt) pin. The NMI
functions similar to the SOS5A's TRAP; it can't be dis·
abled or masked. NMI has higher priority than INTR.

The INTR pin has lowest priority among the other 8085A
hardware interrupts. Thus, precautions to prevent interrupting 8259A service routines may be necessary. This,
of course, depends on how the 8085A interrupts are
being used in a particular application. Such precautions
can be implemented, however, by masking the RST pins
using the SIM instruction. The TRAP pin on the other
hand is non-maskable; all interrupt pins but TRAP can
be controlled by the EI (Enable I nterrupt) and DI (Disable
Interrupt) instructions.

Figure 4 shows an MCS·86 MAX Mode system interfac·
ing with an 8259A on the local bus. This MCS·86-8259A
configuration is also representative of an MCS·88S259A configuration except for the data bus which is 16
bits for SOS6 and S bits for 8088. In the MCS·S6 system
the 8259A must be on the lower 8 bits of the data bus.
Note that the 8259A could also be interfaced on the
system bus.

For a complete description of the 8085A inter.rupt structure, refer to the MCS-85 User's Manual.

1.3 MCS·86/88™_8259A OVERVIEW
Operation of an MCS·86/88-8259A configuration has
basic similarities of the MCS·80/S5-8259A configura·

READY
RESET
CSYNe

Although there are some basic similarities, the actual
processing of interrupts with an 80S6/S088 is different
than an SOSOA or SOS5A. When an interrupt request is
present and interrupts are enabled, the SOS6/S0SS enters
its interrupt acknowledge machine cycle .. The interrupt
acknowledge machine cycle pushes the flag registers
onto the stack (as in a PUSHF instruction). It then clears
the IF flag which disables interrupts. The contents of

r..;;;Y;;;ST;';EM~AD"'D:;;;RE;;;SS;;-;;;BU;;;S--;;."'I!Rl!"'" l~:I~~ORY
A1

ANi
Fie

I!Rl!

RESET
READY

A,S·19

MULTIPLEXED ADORESSfDATA BUS

ADo_iS'

/l--'-"SyV.S'"'TE"'M"'D""AT"'A"B"'US'-----"\ TO MEMORY
IV---.-=-=====-,/
AND 1/0

LOCK

8259A SELECT

NMI
INTR

J

TO
MEMORY

1
TO 110

---V

Figure 4. MSC-8e

TO SLAVE 8259A

™8258A B••1c ConllllUflltlon Example (8088 In Max. Mode)
A-140

AP-59
both the code segment and the instruction pOinter are
then also pushed onto the stack. Thus, the stack retains
the pre-interrupt flag status and pre-interrupt program
location which are used to return from the service
routine_ The 8086/8088 then issues the first of two INTA
pulses which signal the 8259A that the 8086/8088 has
honored its interrupt request. If the 8086/8088 is used in
its "MIN Mode" the INTA signal is available from the
8086/8088 on its INTA pin. If the 8086/8088 is used in the
"MAX Mode" the INTA signal is available via the 8288
Bus Controller INTA pin. Additionally, in the "MAX
Mode" the 8086/8088 LOCK pin goes low during the interrupt acknowledge sequence. The LOCK signal can be
used to indicate to other system bus masters not to gain
control of the system bus during the interrupt acknowledge sequence. A "HOLD" request won't be honored
while LOCK is low.
The 8259A is now ready to vector program execution to
the'corresponding service routine. This is done during
the sequence of the two INTA pulses issued by the 80861
8088_ Unlike operation with the 8080A or 8085A, the
8259A doesn't place a CALL instruction and the starting
address of the service routine on the data bus. Instead,
the first INTA pulse is used only to signal the 8259A of
the honored request. The second INTA pulse causes the
8259A to place a single interrupt-vector byte onto the
data bus. Not used as a direct address, this interruptvector byte pertains to one of 256 interrupt "types" supported by the 8086/8088 memory. Program execution is
vectored to the corresponding service routine by the
contents of a specified interrupt type.
All 256 interrupt types are located in absolute memory
locations. 0 through 3FFH which make up the 80861
8088's interrupt-vector table. Each type in the interruptvector table requires 4 bytes of memory and stores a
code segment address and an instruction pOinter address. Figure 5 shows a block diagram of the interruptvector table. Locations 0 through 3FFH should be
reserved for the interrupt-vector table alone. Furthermore, memory locations 00 through 7FH (types 0-31) are
reserved for use by Intel Corporation for Intel hardware
and software products. To maintain compatibility with
present and future Intel products, these locations
should not be used_

-

3FFH
INTERRUPT TYPE 255

3FCH
3FBH

INTERRUPT TYPE 254
3F8H

•
•
•

BH

INTERRUPT TYPE 2

8H

7H
INTERRUPT TYPE 1
INTERRUPT TYPE 0

4H
3H
OH

Figure 5_ 808618088 Interrupt Vector Table

When the 8086/8088 receives an interrupt-vector byte
from the 8259A, it multiplies its value by four to acquire
the address of the interrupt type. For example, if the
interrupt-vector byte specifies type 128 (80H), the vectored address in 8086/8088 memory is 4 x 80H, which
equals 200H. Program execution is then vectored to the
service routine whose address is specified by the code
segment and instruction pOinter values within type 128
located at 200H. To show how this is done, let's assume
interrupt type 128 is to vector data to 8086/8088 memory
location 2FF5FH. Figure 6 shows two possible ways to
set values of the code segment and instruction pointer
for vectoring to location 2FF5FH. Address generation
by the code segment and instruction pOinter is accomplished by an offset (they overlap). Of the total
20-bit address capability, the code segment can designate the upper 16 bits, the instruction pOinter can
designate the lower 16 bits.

-

-

CS(MSB)

2FH

1 FFH

CS(LSB)

FOH

1 FEH

IP(MSB)
IP(LSB)

DOH
5FH

1 FDH
1 FCH

CS(MSB)
CS(LSB)
IP(MSB)
IP(LSB)

20H

1

DOH
FFH

1 FEH
FFH
~FDH

5FH

1FCH

I

TYPE 128

~

Figure 6. Two Examples 01 8086/8088 Interrupt Type 128 Vectoring
to Location 2FF5FH

When entering an interrupt service routine, those registers that are mutually used between the main program
and service routine should be saved_ The best way to do
this is to "PUSH" each register used onto the stack immediately. The service routine can then "POP" each
register off the stack in the same order when it is completed.
Once the service routine is completed the main program
may bere-entered by using a IRET (Interrupt Return) instruction. The IRET instruction will pop the pre-interrupt
instruction pointer, code segment and flags off the
stack_ Thus the main program will resume where it was
interrupted with the same flag status regardless of
changes in the service routine_ Note especially that this
includes the state of the IF flag, thus interrupts are reenabled automatically when returning from the service
routine_
Beside external interrupt generation from the INTR pin,
the 8086/8088 is also able to invoke interrupts by software. Three interrupt instructions are provided: iNT, INT
(Type 3), and INTO. INT is a two byte instruction, the second byte selects the interrupt type. INT (Type 3) is a one
byte instruction which selects interrupt Type 3. INTO is
a conditional one byte 'interrupt instruction which
selects interrupt Type 4 if tl:le OF flag (trap on overflow)
is set. All the .software interrupts vector program execution as the hardware interrupts do_

A-141

AP-59
For further information on 8086/8088 interrupt operation
and internal interrupt structure refer to the MCS-86
User's Manual and the 8086 System Design application
note_

2_ 8259A FUNCTIONAL BLOCK DIAGRAM
A block diagram of the 8259A is shown in Figure 7_ As
can be seen from this figure, the 8259A consists of eight
major blocks: the Interrupt Request Register (IRR), the
In-Service Register (ISR), the Interrupt Mask Register
(I MR), the Priority Resolver (PR), the cascade buffer/
comparator, the data bus buffer, and logic blocks for
control and read/write. We'll first go over the blocks
directly related to interrupt handling, the IRR, ISR, IMR,
PR, and the control logic. The remaining functional
blocks are then discussed.
2_1 INTERRUPT REGISTERS AND CONTROL LOGIC
Basically, interrupt requests are handled by three "cascaded" registers: the Interrupt Request Register (IRR) is
use to store all the interrupt levels requesting service;
the In-Service Register (ISR) stores all the levels which
are being serviced; and the Interrupt Mask Register
(IMR) stores the bits of the interrupt lines to be masked.
The Priority Resolver (PR) looks at the IRR, ISR and IMR,
and determines whether an INT should be issued by the
the control logic to the processor.
Figure 8 shows conceptually how the Interrupt Request
(IR) input handles an interrupt request and how the
various interrupt registers interact. The figure repre-

sents one of eight "daisy-chained" priority cells, one for
each IR input.
The best way to explain the operation of the priority cell
is to go through the sequence of internal events that
happen when an interrupt request occurs. However,
first, notice that the input circuitry of the priority cell
allows for both level sensitive and edge sensitive IR inputs. Deciding which method to use is dependent on the
particular application and will be discussed in more
detai I later.
When the IR input is in an inactive state (LOW), the edge
sense latch is set. If edge sensitive triggering is
selected, the "Q" output of the edge sense latch will
arm the input gate to the request latch. This input gate
will be disarmed after the IR input goes active (HIGH)
and the interrupt request has been acknowledged. This
disables the input from generating any further interrupts until it has returned low to re-arm the edge sense
latch. If level sensitive triggering is selected, the "Q"
output of the edge sense latch is rendered useless. This
means the level of the IR input is in complete control of
interrupt generation; the input won't be disarmed once
acknowledged.
When an interrupt occurs on the IR input, it propagates
through the request latch and to the PR (assuming the
input isn't masked). The PR looks at the incoming requests and the currently in-service interrupts to ascertain whether an interrupt should be .issued to the processor. Let's assume that the request is the only one incoming and no requests are presently in service. The PR
then causes the control logic to pull the INT line to the
processor high.

PIN CONFIGURATION

cs

Vee

iVA

"0

AD

INTA

0,

IR7

D.

IR6

0,;

IRS

0,

IR4

OJ

IR3

O2

IR2

0,

IR'

D.

IRO

CASO

INT

CAS'

SP/EN

GND

CAS2

BLOCK DI.AGRAM
INT

INTA

DATA
BUS

CONTROL lOGIC

BUFFER

PIN NAMES
°7- DO

OAT A BUS IBI·DIR ECTIONALI

RD
WR

READ INPUT
W'RITE INPUT

A.

COMMAND SELECT ADDRESS

cs

CHIP SELECT

CAS 1

CAS'-CASO
$P/EN

CASCADE LINES
SLAVE PROGRAM/ENABLE BUFFER

CAS 2

INT
INTA
IRO-IR7

INTERRUPT OUTPUT
INTERRUPT ACKNOWLEDGE INPUT
INTERRUPT REQUEST INPUTS

SP/EN _ _ _----'

~INTERNAl sus

Figure 7. 8259A Block Diagram and Pin Configuration

A-142

AP-59

LTIM BIT
0= EDGE
LEVEL

1

TO OTHER PRIORITY CELLS

CLR ISA

=

CLR

EDGE

a

ISA BIT

SET

SENSE

-I-_-+__~l::::1I-~~~1

~LA~T:<:,eH~l-_ _l-_ _

SET ISA

PRIORITY
RESOLVER

CONTROL
LOGIC

NON·
MASKED
REO

MesaO/85

MODE

INTAG

{

FREEZE

MeS.6'•• {

INTA

MODE

~

I~

FREEZE
NOTES
1. MASTER CLEAR ACTIVE ONLY DURING 'ICW1
2. FREEZE/IS ACTIVE DURING INTAI AND POLL SEQUENCES ONLY
3. TRUTH TABLE FOR D·LATCH

c
1
o

I

0

Oi
X

I

a

01
Qn-1

I OPERATION
FOLLOW
HOLD

Figure 8. Priority Cell

When the processor honors the INT pulse, it sends a se·
quence of INTA pulses to the 8259A (three for 8080A/
8085A, two for 8086/8088). During this sequence the
state of the request latch is frozen (note the INTA·freeze
request timing diagram). Priority is again resolved by the
PR to determine the appropriate interrupt vectoring
which is conveyed to the processor via the data bus.
Immediately after the interrupt acknowledge sequence,
the PR sets the corresponding bit in the ISR which
simultaneously clears the edge sense latch. if edge sen·
sitive triggering is used, clearing the edge sense latch
also disarms the request latch. This inhibits the
possibility of a still active IR input from propagating
through the priority cell. The IR input must return to an
inactive state, setting the edge sense latch, before
another interrupt request can be recognized. If level sen·
sitive triggering is used, however, clearing the edge
sense latch has no affect on the request latch. The state
of the request latch is entirely dependent upon the IR in·
put level. Another interrupt will be generatedimmedi·
ately if the IR level is left active after its ISR bit has been
reset. An ISR bit gets reset with an End·of·lnterrupt (EOI)
command issued in the service routine. End·of·
interrupts will be covered in more detail later.

DBO-DB?). Control words, status information, and
interrupt·vector data are transferred through the data
bus buffer.
Read/Write Control Logic

The function of this block is to control the programming
of the 8259A by accepting OUTput commands from the
processor. It also controls the releasing of status onto
the data bus by accepting INput commands from the
processor. The initialization and operation command
word registers which store the various control formats
are located in this block. The RD, WR, AO, and CS
pins are used to control access to this block by the
processor.
Cascade Buffer/Comparator

As mentioned earlier, multiple 8259A's can be combined
to expand the number of interrupt levels. A master·slave
relationship of cascaded 8259A's is used for the expan·
sion. The SP/EN and the CASO-2 pins are used for oper·
ation of this block. The cascading of 8259A's is covered
in depth in the "Operation of the 8259A" section of this
application note.

2.3 PIN FUNCTIONS

2.2 OTHER FUNCTIONAL BLOCKS

Name

Data Bus Buffer

This three·state, bidirectional 8·bit buffer is used to in·
terface the 8259A to the processor system data bus (via

Vee
GND

A-143

Pin 1# I/O Function

28

+ 5V supply

14

Ground

AP-59
Name

Pin # 1/0 Function

Chip Select: A low on this pin enables RD and WR communication between the CPU and the 8259A. INTA
functions are independent of CS.

2

Write: A low on this pin when CS is
low enables the 8259A to accept
command words from the CPU.

3

Read: A low on this pin when CS is
low enables the 8259A to release
status onto the data bus for the CPU.

D7-DO 4-11 1/0 Bidirectional Data Bus: Control,
status and interrupt-vector information is transferred via this bus.
CASO- 12,13, 1/0 Cascade Lines: The CAS lines form a
CAS2
15
private 8259A bus to control a multiple 8259A structure. These pins are
outputs for a master 8259A and inputs for a slave 8259A.
SP/EN

INT

16

17

110 Slave Program/Enable Buffer: This is
a dual function pin. When in the buffered mode it can be used as an output to control buffer transceivers
(EN). When not in the buffered mode
it is used as an input to designate a
master (SP= 1) or slave (SP= 0).

0 Interrupt: This pin goes high whenever a valid interrupt request is asserted. It is used to interrupt the
CPU, thus it is connected to the
CPU's interrupt pin.

IROIR7

18-25

I Interrupt Requests: Asynchronous inputs. An interrupt request can be
generated by raising an IR input (low
to high) and holding it high until it is
acknowledged (edge triggered mode),
or just by a high level on an IR input
(level triggered mode).

INTA

26

Interrupt Acknowledge: This pin is
used to enable 8259A interrupt-vector
data onto the data bus. This is done
by a sequence of interrupt acknowledge pulses issued by the CPU.

AO

27

AO Address Line: This pin acts in conjunction with the CS, WR, and RD
pins. It is used by the 8259A to decipher between various command
words the CPU writes and status the
CPU wishes to read. It is typically
connected to the CPU AO address
line (A 1 for 8086/8088).

3. OPERATION OF THE 8259A

Interrupt operation of the 8259A falls under five main
categories: vectoring, priorities, triggering, status, and
cascading. Each of these categories use various modes
and commands. This section will explain the operation
of these modes and commands. For clarity of explanation, however, the actual programming of the 8259A isn't

covered in this section but in "Programming the 8259A".
Appendix A is provided as a cross reference between
these two sections.

3.1 INTERRUPT VECTORING

Each IR input of the 8259A has an individual interruptvector address in memory associated with it. Designation of each address depends upon the initial programming of the 8259A. As stated earlier, the interrupt
sequence and addressing of an MCS-80 and MCS-85
system differs from that of an MCS-86 and MCS-88
system. Thus, the 8259A must be initially programmed
in either a MCS-80/85 or MCS-86/88 mode of operation to
insure the correct interrupt vectoring.
MCS·80185™ Mode

When programmed in the MCS-80/85 mode, the 8259A
should only be used within an 8080A or an 8085A
system. In this mode the 8080A/8085A will handle interrupts in the format described in the "MCS-80-8259A or
MCS-85-8259A Overviews."
Upon interrupt request in the MCS-80/85 mode, the
8259A wi II output to the data bus the opcode for a CALL
instruction and the address of the desired routine. This
is in response to a sequence of three INTA pulses
issued by the 8080A/8085A after the 8259A has raised
INT high.
The first INTA pulse to the 8259A enables the CALL
opcode "CD H " onto the data bus. It also resolves IR priorities and effects operation in the cascade mode,
which will be covered later. Contents of the first
interrupt-vector byte are shown in Figure 9A.
During the second and third INTA pulses, the 8259A
conveys a 16-bit interrupt-vector address to the 8080AI
8085A. The interrupt-vector addresses for all eight levels
are selected when initially programming the 8259A.
However, only one address is needed for programming.
Interrupt-vector addresses of IRO-IR7 are automatically
set at equally spaced intervals based on the one programmed address. Address intervals are user definable
to 4 or 8 bytes apart. If the service routine for a device is
short it may be possible to fit the entire routine within
an 8-byte interval. Usually, though, the service routines
require more than 8 bytes. So, a 4-byte interval is used to
store a Jump (JMP) instruction which directs the aOaOAI
8085A to the appropriate routine. The a-byte interval
maintains compatibility with current 8080A/8085A
Restart (RST) instruction software, while the 4-byte interval is best for a compact jump table. If the 4-byte interval is selected, then the 8259A will automatically
insert bits AO-A4. This leaves A5-A15 to be programmed by the user. If the 8-byte interval is selected,
the 8259A will automatically insert bits AO-A5. This
leaves only A6-A 15 to be programmed by the user.
The LSB of the interrupt-vector address is placed on the
data bus during the second INTA pulse. Figure 9B
shows the contents of the second interrupt-vector byte
for both 4 and 8-byte intervals.
The MSB of the interrupt-vector address is placed on the
data bus during the third INTA pulse. Contents of the
third interrupt·vector byte is shown in Figure 9C.

A-144

AP-59
3.2 INTERRUPT PRIORITIES

I

CALLCODEiL _'_ _ _ _ _ _ _ _ _---.J'

A variety of modes and commands are available for controlling interrupt priorities of the 8259A. All of them are
programmable, that is, they may be changed dynamically under software control. With these modes and commands, many possibilities are conceivable, giving the
user enough versatility for almost any interrupt controlled application.

A. FIRST INTERRUPT VECTOR BYTE, MCsaO/B5 MODE
IR

Inl.....,=4

D2

,

0'

°

DO

O----,'........~

"7

A6

A5

_,O'---'---"c:'_..."...j

f--'-+=c---"'A6:........:::A5, __ ~_~_O_ _O__ ~
A6

A5

0

1 __ ~

1

_~~ ____ ._

"'7

A6

A5

"'7

A6

A5

~_

0

~

1

0

_~

Fully Nested Mode

__ .~~

0

The fully nested mode of operation is a general purpose
priority mode. This mode supports a multilevel-interrupt
structure in which priority order of all eight IR inputs are
arranged from highest to lowest.

~--;-':-:".._o,,'._0,-,'_'"-,-,'_'_0,,-'_"--:c.'_._OO"--j

7

"'7

A6

+ +-~i f-O-'

_'-::...~-_'_-::...:'_---"-::...:...j

Unless otherwise programmed, the fully nested mode is
entered by default upon initialization. At this time, IRO is
assigned the highest priority through IR7 the lowest.
The fully nested mode, however, is not confined to this
IR structure alone. Once past initialization, other IR inputs can be assigned highest priority also, keeping the
multilevel-interrupt structure of the fully nested mode.
Figure lIA-C shows some variations of the priority
structures in the fully nested mode.

1 _::...:._-::...;,_.

-f-':::":--.C:"---':,'_. . . . : -.-..-~~~~=-==
1
0
0
0
----

~-f-'A::..7~,,---,O~ __ ~O

A1

A6

0

0

0

B. SECOND INTERRUPT VECTOR BYTE, MCsaO/B5 MODE

I

07
"15

I

01
1.14

05
\

"'3

I

04
"12

I

D3
All

I

02
AID

01

1 "9 I

00
AS

I

C. THIRD INTERRUPT VECTOR BYTE, MCSBO/B5 MODE

Figure 9. SA-C. Interrupt·Vector Bytes for 825SA, MCS 80185 Mode

MCS.86188™Mode

Contents of the interrupt·vector byte for 8086/8088 type
selection is put on the data bus during the second INTA
pulse and is shown in Figure 10.
IR 07 06 05 4
02 01 DO
7 T7 T6 T5 T4 T3 1 1 1
6 T7 T6 T5 T4 T3 1 1 0
5 T7 T6 T5 T4 T3 1 0 1
4 T7 T6 T5 T4 T3 1 0 0
3 T7 T6 T5 T4 T3 0 1 1
2 T7 T6 T5 T4 T3 0 1 0
1 T7 T6 T5 T4 T3 0 0 1
OT7T6T5T4T3 0 0 0

Figuno 10. Interrupt Vector Byte, MCS ..,..TM Made

IR LEVELS
PRIORITY

IR7 IRS IRS IR4 IR3 IR2 IR1 IRO
4 3 2 1 0 7 6 5
B

I~~I~VR~~~ 11~7 1~6 1~5 1~4 i~3 1~2 1~1 I~O I

Upon interrupt in the MCS-86/88 mode, the 8259A will
output a single interrupt-vector byte to the data bus.
This is in response to only two INTA pulses issued by
the 8086/8088 after the 8259A has raised INT high.

The second INTA pulse is used to enable the single
interrupt-vector byte onto the data bus. The 8086/8088
uses this interrupt-vector byte to select one of 256 interrupt "types" in 8086/8088 memory. Interrupt type selection for all eight IR levels is made when initially programming the 8259A. However, reference to only one interrupt type is needed for programming. The upper 5 bits
of the interrupt vector byte are user definable. The lower
3 bits are automatically inserted by the 8259A depending upon the IR level.

IR7 IRs IRS IR4 IR3 IR2 IR1 IRO
7 6 5 4 3 2 1 0

A

When programmed in the MCS-86/88 mode, the 8259A
should only be used within an MCS-86 or MCS-88
system. In this mode, the 8086/8088 will handle interrupts in the format described earlier in the "8259A8086/8088 Overview".

The first INTA pulse is used only for set-up purposes internal to-the 8259A. As in the MCS-80/85 mode, this setup includes priority resolution and cascade mode operations which will be covered later. Unlike the MCS-80/85
mode, no CALL opcode is placed on the data bus.

IR LEVELS
PRIORITY

C

Figure 11. A-C. Some Variations of Priority Structure in the
Fully Nested Mode

Further explanation of the fully nested mode, in this
section, is linked with information of general 8259A interrupt operations. This is done to ease explanation to
the user in both areas.
In general, when an interrupt is acknowledged, the
highest priority request is determined from the IRR (Interrupt Request Register). The interrupt vector is then
placed on the data bus. In addition, the corresponding
bit in the ISR (In-Service Register) is set to designate the
routine in service. This ISR bit remains set until an EOI
(End·Of-lnterrupt) command is issued to the 8259A.
EOI's will be explained in greater detail shortly.
In the fully nested mode, while an ISR bit is set, all further requests of the same or lower priority are inhibited
from generating an interrupt to the microprocessor. A
higher priority request, though, can generate an interrupt, thus vectoring program execution to its service
routine. Interrupts are only acknowledged, however, if
the microprocessor has previously executed an "Enable
Interrupts" instruction. This is because the interrupt
request pin on the microprocessor gets disabled automatically after acknowledgement of any interrupt. The
assembly language instructions used to enable interrupts are "EI" for 8080Al8085A and "STI" for 8086/8088.
Interrupts can be disabled by using the instruction "Oi"
for 8080A/ 8085A and "CLI" for 8086/8088. When a
routine is completed a "return" instruction is executed
"RET" for 8080Al8085Aand "IRET" for 8086/8088.
'

A-145

AP-59
Figure 12 illustrates the correct usage of interrupt
related instructions and the interaction of interrupt
levels in the fully nested mode.
Assuming the IR priority assignment for the example in
Figure 12 is IRQ the highest through IR7 the lowest. the
sequence is as follows. During the main program, IR3
makes a request. Since interrupts are enabled, the
microprocessor is vectored to the IR~ service routine.
During the IR3 routine, IRI asserts a request. Since IRI
has higher priority than IR3, an interrupt is generated.
However, it is not acknowledged because the micro·
processor disabled interrupts in response to the IR3 in·
terrupt. The IRI interrupt is not acknowledged until the
"Enable Interrupts" instruction is executed. Thus the
IR3 routine has a "protected" section of code over
which no interrupts (except non·maskable) are allowed.
The IHI routine has no such "protected" section since
an "Enable Interrupts" instruction is the first one in its
service routine. Note that in this example the IRI reo
quest must stay high until it is acknowledged. This is
covered in more depth in the "Interrupt Triggering"
section.

the IR3 routine. This allows IRQ-IR2 to interrupt the IR3
routine again, since ISR3 is the highest ISR bit set. No
further interrupts occur in the example so the EOI com·
mand resets ISR3 and the "return" instruction causes
the main program to resume at its pre·interrupt location,
ending the example.
A single 8259A is essentially always in the fully nested
mode unless certain programming conditions disturb it.
The following programming conditions can cause the
8259A to go out of the high to low priority structure of
the fully nested mode.
o

The automatic EOI mode

o

The special mask mode

o

A slave with a master not in. the special fully nested
mode

These modes will be covered in more detai I later,
however, they are mentioned now so the user can be
aware of them. As long as these program conditions
aren't inacted, th.e fully nested mode remains undis·
turbed.
End of Interrupt

IR3

Upon completion of an interrupt service routine the
8259A needs to be notified so its ISR can be updated.
This is done to keep track of which interrupt levels are in
the process of being serviced and their relative priori·
ties. Three different End·Of·lnterrupt (EOI) formats are
available for the user. These are: the non·specific EOI
command, the specific EOI command, and the auto·
matic EOI Mode. Selection of which EOI to use is dependent upon the interrupt operations the user wishes to
perform.

IR3 SERVICE
ROUTINE

INTERRUPT

IR1
INTER·
RUPT

Non-Specific EOI Command

A non·specific EOI command sent from the microproc·
essor lets the 8259A know when a service routine has
been completed, without specification of its exact inter·
rupt level. The 8259A automatically determines the inter·
rupt level and resets the correct bit in the ISR.

IR1 SERVICE
ROUTINE

Figura 12. Fully Nested Mode Example (MCS 8O/8S™ or MCS 86188™)

What is happening to the ISR register? While in the main
program, no ISR bits are set since there aren't any inter·
rupts in service. When the IR3 interrupt is acknowledged, the ISR3 bit is set. When the IRI interrupt is
acknowledged, both the ISRI and the ISR3 bits are set,
indicating that neither routine is complete. At this time,
only IRQ could generate an interrupt since it is the only
input with a higher priority than those prev.iously in ser·
vice. To terminate the IRI routine, the routine must
inform the 8259A that it is complete by resetting its ISR
bit. It does this by executing an EOI command. A
"return" instruction then transfers execution back to

To take advantage of the non·specific EOI the 8259A
must be in a mode of operation in which it can predetermine in·service routine levels. For this reason the non·
specific EOI command should only be used when the
most recent level acknowledged and serviced is always
the highest priority level. When the 8259A receives a
non-specific EOI command, it simply resets the highest
priority ISH bit, thus confirming to the 8259A that the
highest priority routine of the routines in service is
finished.
The main advantage of using the non-specific EOI com·
mand is that IR level specification isn't necessary as in
the "Specific EOI Command", covered shortly.
However, special consideration should be taken when
deciding to use the non·specific EOL Here are two pro·
gram conditions in which it is best not used:
o

Using the set priority command within an interrupt
service routi ne.

o

Using a special mask mode.

These conditions are covered in more detail in their own
sections, but are listed here for the users reference.

A-146

AP-59
Specific EO' Command
A specific EOI command sent from the microprocessor
lets the 8259A know when a service routine of a particular interrupt level is completed_ Unlike a non-specific
EOI command, which automatically resets the highest
priority ISR bit, a specific EOI command specifies an
exact ISR bit to be reset. One of the eight IR levels of the
8259A can be specified in the command_
The reason the specific EOI command is needed, is to
reset the ISR bit of a completed service routine whenever the 8259A isn't able to automatically determine it.
An example of this type of situation might be if the
priorities of the interrupt levels were changed during an
interrupt routine ("Specific Rotation")_ In this case, if
any other routines were in service at the same time, a
non-specific EOI might reset the wrong ISR bit. Thus the
specific EOI command is the best bet in this case, or for
that matter, any time in which confusion of interrupt
priorities may exist. The specific EOI command can be
used in all conditions of 8259A operation, including
those that prohibit non-specific EOI command usage_

By doing this, higher priority interrupt levels will be serviced only after the completion of a routine in service.
This guideline restores the fully nested structure in
regards to the IRR; however, a routine in-service can't be
interrupted.
Equal Priority

Automatic Rotation -

Automatic rotation of priorities serves in applications
where the interrupting devices are of equal priority,
such as communications channels. The concept is that
once a peripheral is serviced, all other equal priority
peripherals should be given a chance to be serviced
before the original peripheral is serviced again. This is
accomplished by automatically assigning a peripheral
the lowest priority after being serviced Thus, in worst
case, the device would have to wait until all other
devices are serviced before being serviced again.
There are two methods of accomplishing automatic
rotation. One is used in conjunction with the nonspecific EOI, "rotate on non-specific EOI command".
The other is used with the automatic EOI mode, "rotate
in automatic EOI mode".

Automatic EO' Mode
When programmed in the automatic EOI mode, the
microprocessor no longer needs to issue a command to
notify the 8259A it has completed an interrupt routine_
The 8259A accomplishes this by performing a nonspecific EOI automatically at the trailing edge of the last
INTA pulse (third pulse in MCS-80/85, second in
MCS-86).
The obvious advantage of the automatic EOI mode over
the other EOI command is no command has to be
issued. In general, this simplifies programming and
lowers code requirements within interrupt routines.
However, special consideration should be taken when
deciding to use the automatic EOI mode because it
disturbs the fully nested mode. In the automatic EOI
mode the ISR bit of a routine in service is reset right
after it's acknowledged, thus leaving no designation in
the ISR that a sevice routine is being executed. If any interrupt request occurs during this time (and interrupts
are enabled) it will get serviced regardless of its priority,
low or high. The problem of "over nesting" may also
happen in this situation. "Over nesting" is when an IR
input keeps interrupting its own routine, resulting in unnecessary stack pushes which could fill the stack in a
worst case condition. This is not usually a desired form
of operation!

Rotate on Non-Specific EO' Command
When the rotate on non-specific EOI command is
issued, the highest ISR bit is reset as in a normal nonspecific EOI command. After it's reset though, the corresponding IR level is assigned lowest priority. Other IR
priorities rotate to conform to the fully nested mode
based on the newly assigned low priority
Figures 13A and B show how the rotate on non-specific
EOI command effects the interrupt priorities. Let's
assume the IR priorities were assigned with IRO the
highest and IR7 the lowest, as in 13A. IR6 and IR4 are
already in service but neither is completed. Being the
higher priority routine, IR4 is necessarily the routine
being executed. During the IR4 routine a rotate on nonspecific EOI command is executed. When this happens,
bit 4 in the ISR is reset. IR4 then becomes the lowest
priority and IR5 becomes the highest as in 13B.

ISR STATUS
A

157 156 ISS 154 153 152 151 ISO
I 0 1 0 1 0 0 0 01

7

6

5

4

3

2

1

0

1

157 156 ISS 154 153 152 151 ISO

ISR STATUS
PRIORITY

I0

2

1
1

0
0

BEFORE

J COMMAND

HIGHEST PRIORITY

LOWEST PRIORITY

So what good is the automatic EOI mode with problems
like those just covered? Well, again, like the other EOls,
selection is dependent upon the application. If interrupts are controlled at a predetermined rate, so as not to
cause the problems mentioned above, the automatic
EOI mode works perfect just the way it is. However, if interrupts happen sporadically at an indeterminate rate,
the automatic EOI mode should only be used under the
following guideline:
• When using the automatic EOI mode with an indeterminate interrupt rate, the microprocessor should
keep its interrupt request input disabled during
execution of service routines.

PRIORITY,

0
7

0
6

0
5

0
4

0
3

I

AFTER
COMMAND

I IL-_--,

~

HIGHEST PRIORITY

I

LOWEST PRIORITY

Figure 13. A-B. Rolale on Non·specific EOI Command Example

Rotate in Automatic EO' Mode
The rotate in automatic EOI mode works much like the
rotate on non-specific EOI command. The main difference is that priority rotation is done automatically after

A-147

AP-59
the last INTA pulse of an interrupt request. To enter or
exit this mode a rotate-in-automatic-EOI set command
and rotate-in-automatic-EOI clear command is provided.
After that, no commands are needed as with the normal
automatic EOI mode. However, it must be remembered,
when using any form of the automatic EOI mode, special consideration should be taken. Thus, the guideline
for the automatic EOI mode also stands for the rotate in
automatic EOI mode.
Specific Rotation -

Specific Priority

Specific rotation gives the user versatile capabilities in
interrupt controlled operations. It serves in those applications in which a specific device's interrupt priority
must be altered. As opposed to automatic rotation
which automatically sets priorities, specific rotation is
completely user controlled. That is, the user selects
which interrupt level is to receive lowest or highest
priority. This can be done during the main program or
within interrupt routines. Two specific rotation commands are available to the user, the "set priority command" and the "rotate on specific EOI command."
Set Priority Command
The set priority command allows the programmer to
assign an IR level the lowest priority. All other interrupt
levels will conform to the fully nested mode based on
the newly assigned low priority.
An example of how the set priority command works is
shown in Figures 14A and 14B. These figures show the
status of the ISR and the relative priorities of the interrupt levels before and after the set priority command.
Two interrupt routines are shown to be in service in
Figure 14A. Since IR2 is the highest priority, it is
necessarily the routine being executed. During the IR2
routine, priorities are altered so that IR5 is the highest.
This is done simply by issuing the set priority command
to the B259A. In this case, the command specifies IR4 as
being the lowest priority. The result of this set priority
command is shown in Figure 14B. Even though IR7 now
has higher priority than IR2, it won't be acknowledged
until the IR2 routine is finished (via EOI). This is because
priorities are only resolved upon an interrupt request or
an interrupt acknowledge sequence. If a higher priority
request occurs during the IR2 routine, then priorities are
resolved and the highest will be acknowledged.

A

ISR STATUS
PRIORITY

157 156 ISS 154 153 152 151 ISO
1 0 0 0 0
1 0 0
7 6 5 4 3 2 1 a

I

1

ISR STATUS

PRIORITY

BEFORE
COMMAND

1

LOWEST PRIORITY

B

I

HIGHEST PRIORITY

157 156 ISS 154 153 152 151 ISO
0 0 0 0 1 0 0 I AFTER
2 1 0 7 6 5 4 JJ COMMAND

I1

II

r---

HIGHEST PRIORITY

L..._ _

I
LOWEST PRIORITY

Figure 14. A-B. Set Priority Command Example

When completing a service routine in which the set
priority command is used, the correct EOI must be
issued. The non-specific EOI command shouldn't be
used in the same routine as a set priority command.
This is because the non-specific EOI command resets
the highest ISR bit, which, when using the set priority
command, is not always the most recent routine in service. The automatic EOI mode, on the other hand, can be
used with the set priority command. This is because it
c1utomaticallyperforms a non-specific EOI before the
set priority command can be issued. The specific EOI
command is the best bet in most cases when using the
set priority command within a routine. By resetting the
specific ISR bit of a routine being completed, confusion
is eliminated.
Rotate on Specific EOI Command
The rotate on specific EOI command is literally a combination of the set priority command and the specific
EOI command. Like the set priority command, a specified IR level is assigned lowest priority. Like the specific
EOI command, a specified level will be reset in the ISR.
Thus the rotate on specific EOI command accomplishes
both tasks in only one command.
If it is not necessary to change IR priorities prior to the
end of an interrupt routine, then this command is advantageous. For an EOI command must be executed anyway (unless in the automatic EOI mode), so why not do
both at the same time?
Interrupt Masking
Disabling or enabling interrupts can be done by other
means than just controlling the microprocessor's interrupt request pin. The B259A has an IMR (Interrupt Mask
Register) which enhances interrupt control capabilities.
Rather than all interrupts being disabled or enabled at
the same time, the IMR allows individual IR masking.
The IMR is an B-bit register, bits 0-7 directly correspond
to IRO-IRi. Any IR input can be masked by writing to the
IMR and setting the appropriate bit. Likewise, any IR input can be enabled by clearing the correct IMR bit.
There are various uses for masking off individual IR inputs. One example is when a portion of a main routine
wishes only to be interrupted by specific interrupts.
Another might be disabling higher priority interrupts for
a portion of a lower priority service routine. The possi'
bilities are many.
When an interrupt occurs while its IMR bit is set, it isn't
necessarily forgotten. For, as stated earlier, the IMR
acts only on the output of the IRR. Even with an IR input
masked it is still possible to set the IRR. Thus, when
resetting an IMR, if its IRR bit is set it will then generate
an interrupt. This is providing, of course, that other
priority factors are taken into consideration and the IR
request remains active. If the IR request is removed
before the IMR is reset, no interrupt will be acknowledged.
Special Mask Mode
In various cases, it may be desirable to enable interrupts
of a lower priority than the routine in service. Or, in other
words, allow lower priority devices to generate interrupts. However, in the fully nested mode, alliR levels of

A-148

AP-59
priority below the routine in service are inhibited. So
what can be done to enable them?
Well, one method could be using an EOI command
before the actual completion of a routine in service. But
beware, doing this may cause an "over nesting" problem, similar to in the automatic EOI mode. In addition,
resetting an ISR bit is irreversible by software control,
so lower priority IR levels could only be later disabled by
setting the IMR.
A much better solution is the special mask mode. Working in conjunction with the IMR, the special mask mode
enables interrupts from all levels except the level in service. This is done by masking the level that is in service
and then issuing the special mask mode command.
Once the special mask mode is set, it remains in effect
until reset.
Figure 15 shows how to enable lower priority interrupts
by using the Special Mask Mode (SMM). Assume that
IRO has highest priority when the main program is interrupted by IR4. In the IR4 service routine an enable interrupt instruction is executed. This only allows higher
priority interrupt requests to interrupt IR4 in the normal
fully nested mode. Further in the IR4 routine, bit 4 of the
IMR is masked and the special mask mode is entered.
Priority operation is no longer in the fully nested mode.
All interrupt levels are enabled except for IR4. To leave
the special mask mode, the sequence is executed in
reverse.

Precautions must be taken when exiting an interrupt
service routine which has used the special mask· mode.
A non-specific EOI command can't be used when in the
special mask mode. This is because a non-specific
won't clear an ISR bit of an interrupt which is masked
when in the special mask mode. In fact, the bit will appear invisible. If the special mask mode is cleared
before an EOI command is issued a non-specific EOI
command can be used. This could be the case in the example shown in Figure 15, but, to avoid any confusion
it's best to use the specific EOI whenever using the
special mask mode.
It must be remembered that the special mask mode applies to all masked levels when set. Take, for instance,
IR1 interrupting IR4 in the previous example. If this happened while in the special mask mode, and the IR1
routine masked itself, all interrupts would be enabled
except IR1 and IR4 which are masked.

3.3 INTERRUPT TRIGGERING
There are two classical ways of sensing an active interrupt request: a level sensitive input or an edge sensitive
input. The 8259A gives the user the capability for either
method with the edge triggered mode and the level triggered mode. Selection of one of these interrupt triggering methods is done during the programmed initialization of the 8259A.
Level Triggered Mode

MAIN PROGRAM

When in the level triggered mode the 8259A will recognize any active (high) level on an IR input as an interrupt
request. If the IR input remains active after an EOI command has been issued (resetting its ISR bit), another interrupt will be generated. This is providing of course, the
processor INT pin is enabled. Unless repetitious interrupt generation is desired, the IR input must be brought
to an inactive state before an EOI command is issued in
its service routine. However, it must not go inactive so
soon that it disobeys the necessary timing requirements shown in Figure 16. Note that the request on the
IR input must remain until after the falling edge of the
first INTA pulse. If on any IR input, the request goes
inactive before the first INTA pulse, the 8259A will
respond as if IR7 was active. In any design in which
there's a possibility of this happening, the IR7 default
feature can be used as a safeguard. This can be accomplished by using the IR7 routine as a "clean-up routine"
which might recheck the 8259A status or merely return
program execution to its pre-interrupt location.

EI OR STI

IR4 SERVICE
ROUTINE
IR4 ___
EI OR STI

IRO-3 ENABLED
IR4-7 DISABLED

MASK IR4

SET SMM

IRO-3, 5-7 ENABLED
IR4 DISABLED

RESET SMM

IRO-3 ENABLED
IR4-7 DISABLED

EOI

Figure 15. Special Mask Made Example (MCS 8O/8S™or MCS 8e/88™)

Depending upon the particular design and application,
the level triggered mode has a number of uses. For one,
it provides for repetitious interrupt generation. This is
useful in cases when a service routine needs to be continually executed until the interrupt request goes inactive. Another pos$ible advantage of the level triggered
mode is it allows for "wire-OR'ed" interrupt requests.
That is, a number of interrupt requests using the same
IR input. This can't be done in the edge triggered mode,
for if a device makes an interrupt request while the IR input is high (from another request), its transition will be
"shadowed". Thus the 8259A won't recognize further interrupt requests because its IR input is already high.
Note that when a "wire-OR'ed" scheme is used, the ac-

A-149

AP-59

IR~

--_\->--00---'1

\I.....--e.:::-o
_______________
-.

INT----+-J

INTA-----r---------~

808018085

LATCH'
ARMED

EARLIEST IR
CAN BE REMOVED

'EDGE TRIGGERED MODE ONLY

LATCH'
ARMED

Figure 16. IR Triggering Timing Requirements

tual requesting device has to be determined by the software in the service routine.

feature mentioned in the "level triggered mode" section
also works for the edge triggered mode.

Caution should be taken when using the automatic EOI
mode and the level triggered mode together. Since in
the automatic EOI mode an EOI is automatically performed at the end of the interrupt acknowledge sequence, if the processor enables interrupts while an IR
input is still high, an interrupt will occur immediately. To
avoid this situation interrupts should be kept disabled
until the end of the service routine or until the IR input
returns low.

Depending upon the particular design and application,
the edge triggered mode has various uses. Because of
its edge lockout operation, it is best used in those
applications where repetitious interrupt generation isn't
desired. It is also very useful in systems where the interrupt request is a pulse (this should be in the form of a
negative pulse to the 8259A). Another possible advantage is that it can be used with the automatic EOI mode
without the cautions in the level triggered mode. Overall, in most cases, the edge triggered mode simplifies
operation for the user, since the duration of the interrupt
request at a positive level is not usually a factor.

Edge Triggered Mode

When in the edge triggered mode, the 8259A will only
recognize interrupts if generated by an inactive (low) to
active (high) transition on an IR input. The edge trig·
gered mode incorporates an edge lockout method of
operation. This means that after the riSing edge of an
interrupt request and the acknowledgement of the request, the positive level of the IR input won'lgenerate
further interrupts on this level. The user needn't worry
about quickly removing the request after acknowledgement in fear of generating further interrupts as might be
the case in the level triggered mode. Before another interrupt can be generated the IR input must return to the
inactive state.
Referring back to Figure 16, the timing requirements for
interrupt triggering. is shown. Like the level triggered
mode, in the edge triggered mode the request on the IR
input must remain active until after the falling edge of
the first INTA pulse for that particular interrupt. Unlike
the level triggered mode, though, after the interrupt
request is acknowledged its IRR latch is disarmed. Only
after the IR input goes inactive will the IRR latch again
become armed, making it ready to receive another interrupt request (in the level triggered mode, the IRR latch is
always armed). Because of the way the edge triggered
mode functions, it is best to use a positive level with a
negative pulse to trigger the IR requests. With this type
of input, the trailing edge of the pulse causes the interrupt and the maintained positive level meets the necessary timing requirements (remaining high until after the
interrupt acknowledge occurs). Note that the IR7 default

3.4 INTERRUPT STATUS
By means of software control, the user can interrogate
the status of the 8259A. This allows the reading of the
internal interrupt registers, which may prove useful for
interrupt control during service routines. It also provides for a modified status poll method of device monitoring, by using the poll command. This makes the
status of the internal IR inputs available to the user via
software control. The poll command offers an alternative to the interrupt vector method, especially for those
cases when more than 64 interrupts are needed.
Reading Interrupt Registers

The contents of each S-bit interrupt register, IRR, ISR,
and IMR, can be read to update the user's program on
the present status of the 8259A. This can be a versatile
tool in the decision making process of a service routine,
giving the user more control over interrupt operations.
Before delving into the actual process of reading the
registers, let's briefly review their general descriptions:

A-ISO

IRR (Interrupt
Request Register)

Specifies all interrupt levels requesting service.

ISR (In-Service
Register)

Specifies all interrupt levels
which are being serviced.

IMR (Interrupt
Mask Register)

Specifies all interrupt levels,that
are masked.

AP-59
To read the contents of the IRR or ISR, the user must
first issue the appropriate read register command (read
IRR or read ISR) to the 8259A. Then by applying a RD
pulse to the 8259A (an INput instruction), the contents
of the desired register can be acquired. There is no need
to issue a read register command every time the IRR or
ISR is to be read. Once a read register command is
received by the 8259A, it "remembers" which register
has been selected. Thus, all that is necessary to read
the contents of the same register more than once is the
RD pulse and the correct addressing (AO = 0, explained
in "Programming thll 8259A"). Upon initialization, the
selection of registers defaults to the IRR. Some caution
should be taken when using the read register command
in a system that supports several levels of interrupts. If
the higher priority routine causes an interrupt between
the read register command and the actual input of the
register contents, there's no guarantee that the same
register will be selected when it returns. Thus it is best
in such cases to disable interrupts during the operation.
Reading the contents of the IMR is different than read·
ing the IRR or ISR. A read register command is not
necessary when reading the IMR. This is because the
IMR can be addressed directly for both reading and
writing. Thus all that the 8259A requires for reading the
IMR is a RD pulse and the correct addressing (AO= 1,
explained in "Programming the 8259A").

time the 8259A is to be polled, the poll command must
be written before reading the poll word.
The poll command is useful in various situations. For instance, it's a good alternative when memory is very
limited, because an interrupt-vector table isn't needed.
Another use for the poll command is when more than 64
interrupt levels are needed (64 is the limit when cascading 8259's). The only limit of interrupts using the poll
command is the number of 8259's that can be addressed
in a particular system. Still another application of the
poll command might be when the INT or INTA signals
are not available. This might be the case in a large
system where a processor on one card needs to use an
8259A on a different card. In this instance, the poll command is the only way to monitor the interrupt devices
and still take advantage of the 8259A's prioritizing
features. For those cases when the 8259A is using the
poll command only and not the interrupt method, each
8259A must receive an initialization sequence (interrupt
vector). This must be done even though the interrupt
vector features of the 8259A are not used. In this case,
the interrupt vector specified in the initialization
sequence could be a "fake".

-

~

Poll Command

As mentioned towards the beginning of this application
note, there are two methods of servicing peripherals:
status polling and interrupt servicing. For most applica·
tions the interrupt service method is best. This is
because it requires the least amount of CPU time, thus
increasing system throughput. However, for certain applications, the status poll method may be desirable.
For this reason, the 8259A supports polling operations
with the poll command. As opposed to the conventional
method of polling, the poll command offers improved
device servicing and increased throughput. Rather than
having the processor poll each peripheral in ,order to
find the actual device requiring service, the processor
polls the 8259A. This allows the use of all the previously
mentioned priority modes and commands. Additionally,
both polled and interrupt methods can be used within
the same program.
To use the poll command the processor must first have
its interrupt request pin disabled. Once the poll command is issued, the 8259A will treat the next (CS qualified) RD pulse issued to it (an INput instruction) as an interrupt acknowledge. It will then set the appropriate bit
in the ISR, if there was an interrupt request, and enable a
special word onto the data bus. This word shows
whether an interrupt request has occurred and the
highest priority level requesting service. Figure 17
shows the contents of the "poll word" which is read by
the processor. Bits WO-W2 convey the binary code of
the highest priority level requesting service. Bit I designates whether or not an interrupt request is present. If
an interrupt request is present, bit I will equal 1. If there
isn't an interrupt request at all, bit I will equal 0 and bits
WO-W2 will beset to ones. Service to the requesting
device is achieved by software decoding the poll word
and branching to the appropriate service routine. Each

-

-

-

W2W1WO

WO·W2 = BINARY CODE OF HIGHEST
PRIORITY LEVEL REQUESTING SERVICE
1=1 IF AN INTERRUpT OCCURRED

Figure 17. Poll Word

3.5 INTERRUPT CASCADING
As mentioned earlier, more than one 8259A can be used
to expand the priority interrupt scheme to up to 64 levels
without additional hardware. This method for expanded
interrupt capability is called "cascading". The 8259A
supports cascading operations with the cascade mode.
Additionally, the special fully nested mode and the buffered mode are available for increased flexibility when
cascading 8259A's in certain applications.
Cascade Mode
When programmed in the cascade mode, basic operation consists of one 8259A acting as a master to the
others which are serving as slaves. Figure 18 shows a
system containing a master and two slaves, providing a
total of 22 interrupt levels.
A specific hardware set-up is required to establish
operation in the cascade mode. With Figure 18 as a reference, note that the master is designated by a high on
the SP/EN pin, while the SP/EN pins of the slaves are
grounded (this can also be done by software, see buffered mode). Additionally, the INT output pin of each
slave is connected to an IR input pin of the master. The
CASO-2 pins for all 8259A's are paralleled. These pins
act as outputs when the 8259A is a master and as inputs
for the slaves. Serving as a private 8259A bus, they control which slave has control of the system bus for interrupt vectoring operation with the processor. All other
pins are connected as in normal operation (each 8259A
receives an INTA pulse).

A-151

AP-59

ADDRESS BUS 116)

\

CONTROL BUS
INT REa

\

DATA BUS

----

- ---

--

18~

- - -

------

-

r------

-

~
cs

Ao

00·7

CAsa
8259A
SLAVE A

•

5

4

3

2

1

0

•

5

4

3

,

1

0

II 1 1 1 1 1 1 1
7

00·7

Ao

8259A
SLAVE B

1-

•

SPi'El'J 7

GID 1
7

5

4

3

2

1

CAsa

CAsa

CAS 1

CAS 1

CAS2

CAS2

5

!

4

3

1

0

A,

00-7

rNTA

INT

8259A
MASTER

SPlffi M7 M6 M5 M4 M3 M2 Ml MO

0

1 1 1 1 1, 1 1
6

cs

INT

INTA

!-

CAS 1 1 CAS2

SPlEiiJ7

cs

INT

INTA

I

LL1.1 1 1.

1

5

4

!

1, 1
0

I

INTERRUPT REQUESTS

Figure 18. Cascaded 8259A'S 22 Interrupl Levels

Besides hardware set-up requirements, all 8259A's must
be software programmed to work in the cascade mode.
Programming the cascade mode is done during the initialization of each 8259A. The 8259A that is selected as
master must receive specification during its initialization as to which of its IR inputs are connected to a
slave's INT pin. Each slave 8259A, on the other hand,
must be designated during its initialization with an ID (0
through 7) corresponding to which of the master's IR inputs its INT pin is connected to. This is all necessary so
the CASO-2 pins of the masters will be able to address
each individual slave. Note that as in normal operation,
each 8259A must also be initialized to give its IR inputs
a unique interrupt vector. More detail on the necessary
programming of the cascade mode is explained in "Pro·
gramming the 8259A".
Now, with background information on both hardware
and software for the cascade mode, let's go over the
sequence of events that occur during a valid interrupt
request from a slave. Suppose a slave IR input has
received an interrupt request. Assuming this request is
higher priority than other requests and in-service levels
on the slave, the slave's INT pin is driven high. This
signals the master of the request by causing an interrupt request on a designated IR pin of the master. Again,
assuming that this request to the master is higher priority than other master requests and in-service levels
(pOSSibly from other slaves), the master's INT pin is
pulled high, interrupting the processor.
The interrupt acknowledge sequence appears to the
processor the same as the non-cascading interrupt
acknowledge sequence; however, it's different among
the 8259A's. The first INTA pulse is used by all the
8259A's for internal set-up purposes and, if in the
8080/8085 mode, the master will place the CALL opcode
on the data bus. The first INTA pulse also Signals the
master to place the requesting slave's ID code on the
CAS lines. This turns control over to the slave for the
rest of the interrupt acknowledge sequence, placing the

A-152

appropriate pre-programmed interrupt vector on the
data bus, completing the interrupt request.
During the interrupt acknowledge sequence, the corresponding ISR bit of both the master and the slave get
set. This means two EOI commands must be issued (if
not in the automatic EOI mode), one for the master and
one for the slave.
Special consideration should be taken when mixed
interrupt requests are assigned to a master 8259A; that
is, when some of the master's IR inputs are used for
slave interrupt requests and some are used for individual interrupt requests. In this type of structure, the
master's IRO must not be used for a slave. This is
because when an IR input that isn't initialized as a slave
receives an interrupt request, the CASO-21ines won't be
activated, thus staying in the default condition addressing for IRO (slave IRO). If a slave is connected to the
master's IRO when a non-slave interrupt occurs on
another master IR input, erroneous conditions may
result. Thus IRO should be the last choice when assigning slaves to IR inputs.
Special Fully Nested Mode
Depending on the application, changes in the nested
structure of the cascade mode may be desired. This is
because the nested structure of a slave 8259A differs
from that of the normal fully nested mode. In the cascade mode, if a slave receives a higher priority interrupt
request than one which is in service (through the same
slave), it won't be recognized by the master. This is
because the master's ISR bit is set, ignoring all requests
of equal or lower priority. Thus, in this case, the higher
priority slave interrupt won't be serviced until after the
master's ISR bit is reset by an EOI command. This is
most likely after the completion of the lower priority
routine.
If the user wishes to have a truly fully nested structure
within a slave 8259A, the special fully nested mode
should be used. The special fully nested mode is pro-

AP-59
grammed in the master only. This is done during the
master's initialization. In this mode the master will
ignore only those interrupt requests of lower priority
than the set ISR bit and will respond to all requests of
equal or higher priority. Thus if a slave receives a higher
priority request than one in service, it will be recognized.
To insure proper interrupt operation when using the
special fully nested mode, the software must determine
if any other slave interrupts are still in service before
issuing an EOI command to the master. This is done by
resetting the appropriate slave ISR bit with an EOI and
then reading its ISA. If the ISR contains all zeros, there
aren't any other interrupts from the slave in service and
an EOI command can be sent to the master. If the ISR
isn't all zeros, an EOI command shouldn't be sent to the
master. Clearing the master's ISR bit with an EOI com·
mand while there are still slave interrupts in service
would allow lower priority interrupts to be recognized at
the master. An example of this process is shown in the
second application in the "Applications Examples" sec·
tion.
Buffered Mode
The buffered mode is useful in large systems where buf·
fering is required on the data bus. Although not limited
to only 8259A cascading, it's most pertinent in this use.
In the buffered mode, whenever the 8259A's data bus
output is enabled, its SP/EN pin will go low. This signal
can be used to enable data transfer through a buffer
transceiver in the required direction.
Figure 19 shows a conceptual diagram of three 8259A's
in cascade, each slave is controlling an individual 8286
8·bit bidirectional bus driver by means of the buffered
mode. Note the pull·up on the SP/EN. It is used to
enable data transfer to the 8259A for its initial program·
mingo When data transfer is to go from the 8259A to the
processor, SP/EN will go low; otherwise, it will be high.
A question should arise, however, from the fact that the
SP/EN pin is used to designate a master from a slave;

how can it be used for both master·slave selection and
buffer control? The answer to this is the provision for
software programmable master·slave selection when in
the buffer mode. The buffered mode is selected during
each 8259A's initialization. At the same time, the user
can assign each individual 8259A as a master or slave
(see "Programming the 8259A").

4. PROGRAMMING THE 8259A
Programming the 8259A is accomplished by using two
types of command words: Initialization Command
Words (ICWs) and Operational Command Words
(OCWs). All the modes and commands explained in the
previous section, "Operation of the 8259A", are pro·
grammable using the ICWs and OCWs (see Appendix A
for cross reference). The ICWs are issued from the proc·
essor in a sequential format and are used to set·up the
8259A in an initial state of operation. The OCWs are
issued as needed to vary and control 8259A operation.
Both ICWs and OCWs are sent by the processor to the
8259A via the data bus (8259A CS = 0, WR = 0). The
8259A distinguishes between the different ICWs and
OCWs by the state of its AO pin (controlled by processor
addressing), the sequence they're issued in (lCWs only),
and some dedicated bits among the ICWs and OCWs.
Those bits which are dedicated are indicated so by fixed
values (0 or 1) in the corresponding ICW or OCW pro·
gramming formats which are covered shortly. Note,
when issuing either ICWs or OCWs, the interrupt
request pin of the processor should be disabled.

4.1 INITIALIZATION COMMAND WORDS (ICWs)
Before normal operation can begin, each 8259A in a
system must be initialized by a sequence of two to four
programming bytes called ICWs (Initialization Com·
mand Words). The ICWs are used to set·up the neces·
sary conditions and modes for proper 8259A operation.

DTIR

II)

+5V
1K

e""'

DEN

c

DO_7

SLAVE
8259A

INT

Figure 19. Cascade-Bullered Mode Example

A-IS3

INTR

Ap·59
Figure 20 shows the initialization flow of "the 8259A.
Both ICW1 and ICW2 must be issued for any form of
8259A operation. However, ICW3 and ICW4 are used
only if designated so in ICW1. Determining the neces·
sity and use of each ICW is covered shortly in individual
groupings. Note that, Ohce intialized, if any programming changes within the ICWs are to be made, the entire
ICW sequence must be reprogrammed, not just an individuallCW.

The ICW programming format, Figure 21, shows bit
designation and a short definition of each ICW. With the
ICW format as reference, the functions of each ICW will
now be explained individually.

ICWI

Certain internal set-up conditions occur automatically
within the 8259A after the first ICW has been issued.
These are:

1 . leW4 NEEDED
0" NO leW4 NEEDED

A. Sequencer logic is set to accept the remain'ng ICWs
as designated in ICW1.

o ~ CASCADE MODE

B. The ISR (In-Service Register) and IMR (Interrupt Mask
Register) are both cleared.

CALL INTERVAL
1 = INTERVAL OF 4

1 =SINGLE

0= INTERVAL OF 8

C. The special mask mode is reset.

1 = LEVEL TRIGQERED INPUT
0" EDGE TRIGGERED INPUT

D. The rotate in automatic EOI mode flip-flop is cleared.
E. The IRR (Interrupt Request Register) is selected for
the read register command.
F. If the IC4 bit equals 0 in ICW1, all functions in ICW4
are cleared; 8080/8085 mode is selected by default.
G. The fully nested mode is entered with an initial prior·
ity assignment of IRO highest through IR7 lowest.

A15

H. The edge" sense latch of each IR priority cell is
cleared, thus requiring a low to high transition to
generate an interrupt (edge triggered mode effected
only).

AS Of INTERRUPT VECTOR

'---'-_-'---''-...J.._-'--'_--'-_-! ~~D~~S~:~~~:~·~~~~~~~E
II'IICSSG88MOOEI

ICWJ IMASTER DEVICE)

..

3"!j 6

7

010

NO (SNGL=1)

001100

00001

NO (IC4=O)

.
8I§
,- .,
I

x
0

NOIE 1 SLAVE 10 IS lUUAL TO Hl[ COfllll SPONlJINti MASHIlIH INPUI
NOTE ;I X INUICA If S ··DDN'r CARl"

SOME OF THE TERMINOLOGY USED MAY DIFFER SLIGHTLY FROM EXISTING 8259A
DATA SHEETS. THIS IS DONE TO BmER CLARIFY AND EXPLAIN THE PROGRAM·
MING OF THE 82SSA, THE OPERATIONAL RESULTS REMAIN THE SAME.

Figura 20. Initialization Flow

Figura 21. Initialization Command Words (ICWS) Programming Format

A-154

AP-59
ICW1 and ICW2

1,,1,,1,,1,.1,,1

Issuing ICW1 and ICW2 is the minimum amount of pro·
gramming needed for any type of 8259A operation. The
majority of bits within these two ICWs are used to desig·
nate the interrupt vector starting address. The remain·
ing bits serve various purposes. Description of the ICW1
and ICW2 bits is as follows:
IC4:

SNGL:

ADI:

LTIM:

The IC4 bit is used to designate to the 8259A
whether or not ICW4 will be issued. If any of
the ICW4 operations are to be used, ICW4
must equal 1. If they aren't used, then ICW4
needn't be issued and IC4 can equal O. Note
that if IC4 = 0, the 8259A will assume operation
in the MCS·80/85 mode.
The SNGL bit is used to designate whether or
not the 8259A is to be used alone or in the cas·
cade mode. If the cascade mode is desired,
SNGL must equal O. In doing this, the 8259A
will accept ICW3 for further cascade mode pro·
gramming. If the 8259A is to be used as the
single 8259A within a system, the SNGL bit
must equal 1; ICW3 won't be accepted.
The ADI bit is used to specify the address in·
terval for the MCS·80/85 mode. If a 4·byte ad·
dress interval is to be used, ADI must equal 1.
For an 8·byte address interval, ADI must equal
O. The state of ADI is ignored when the 8259A
is in the MCS·86/88 mode.

T3-T7:

The T3-T7 bits are used to select the interrupt
type when the MCS·86/88 mode is used. The
programming of T3-T7 selects the upper 5
bits. The lower 3 bits are automatically in·
serted, corresponding to the IR level causing
the interrupt. The state of bits A5-A10 will be
ignored when in the MCS-86/88 mode. Estab·
lishing the actual memory address of the inter·
rupt is shown in Figure 22.

I

I
I

I
I

_UPPER 5 BITS OF 8086/8088
INTERRUPT TYPE (USER PROGRAMMED)

~I - ~~~~~~~~gAI~L~~~~'eRTED BY 8259A)

I

I
I

I

I

I

IT71 161151 T41 T31 T21 T, ITol -

10

I

I

r----l

,_-1

COMPLETE 8088J8088 INTERRUPT TYPE

! 0 I 0 I 0 IT71 161 151 T4' T31 T21 TIl Tol 0 I 0 I _~~~~~Jp~DTDy~~S(~~:E8~!~J8088

Figure 22. Establishing Memory Address of 8086/8088 Interrupt Type

ICW3
The 8259A will only accept ICW3 if programmed in the
cascade mode (ICW1, SNGL = 0). ICW3 is used for
specific programming within the cascade mode. Bit
definition of ICW3 differs depending on whether the
8259A is a master or a slave. Definition of the ICW3 bits
is as follows:
SO-7
(Master):

If the 8259A is a master (either when the
SP/EN pin is tied high or in the buffered
mode when MIS 1 in ICW4), ICW3 bit defi·
nition is SO-7, corresponding to "slave 0-7".
These bits are used to establish which IR in·
puts have slaves connected to them. A 1
deSignates a slave, a a no slave. For exam·
pie, if a slave was connected to IR3, the S3
bit should be set to a 1. (SO) should be last
choice for slave designation.

100-102
(Slave):

If the 8259A is a slave (either when the SP/EN
pin is low or in the buffered mode when
MIS a in ICW4), ICW3 bit definition is used
to establish its individual identity. The 10
code of a particular slave must correspond
to the number of the masters IR input it is
connected to. For example, if a slave was
connected to IR6 of the master, the slaves
100-2 bits should be set to 100 = 0, 101 = 1,
and 102 = 1.

The LTIM bit is used to select between the two
I R input triggering modes. If LTIM = 1, the level
triggered mode is selected. If LTIM = 0, the
edge triggered mode is selected.

A5-A15: The A5-A15 bits are used to select the inter·
rupt vector address when in the MCS·80/85
mode. There are two programming formats
that can be used to do this. Which one is im·
plemented depends upon the selected address
interval (ADI). If ADI is set for the 4·byte inter·
val, then the 8259A will automatically insert
AO-A4 (AO, A1=0 and A2, A3, A4=IRO-7).
Thus A5-A 15 must be user selected by pro·
gramming the A5-A15 bits with the desired ad·
dress. If ADI is set for the 8·byte interval, then
AO-A5 are automatically inserted (AO, A1,
A2=0 and A3, A4, A5=IRO-7). This leaves
A6-A15 to be selected by programming the
A6-A15 bits with the desired address. The
state of bit 5 is ignored in the latter format.

I

=

=

ICW4
The 8259A will only accept ICW4 if it was selected in
ICW1 (bit IC4= 1). Various modes are offered by using
ICW4. Bit definition of ICW4 is as follows:
,..PM:

The ,..PM bit allows for selection of either the
MCS-80/85 or MCS·86/88 mode. If set as a 1 the
MCS·86/88 mode is selected, if a 0, the
MCS-80/85 mode is selected.

AEOI:

The AEOI bit is used to select the automatic
end of interrupt mode. If AEOI = 1, the
automatic end of interrupt mode is selected. If
AEOI = 0, it isn't selected; thus an EOI com·
mand must be used during a service routine.

MIS:

The MIS bit is used in conjunction with the buf·
fered mode. If in the buffered mode, MIS
defines whether the 8259A is a master or a
slave. When MIS is set to a 1, the 8259A
operates as the master; when MIS is 0, it
operates as a slave. If not programmed in the
buffered mode, the state of the MIS bit is
ignored.

A-I55

AP-59
BUF:

The BUF bit is used to designate operation in
the buffered mode, thus controlling the use of
the SP/EN pin. If BUF is set to a 1, the buffered
mode is programmed and SP/EN is used as a
transceiver enable output. If BUF is 0, the buf·
fered mode isn't programmed and SP/EN is
used for master/slave selection. Note if ICW4
isn't programmed, SP/EN is used for master/
slave selection.

SFNM:

The SFNM bit designates selection of the
special fully nested mode which is used in
conjunction with the cascade mode. Only the
master should be programmed in the special
fully nested mode to assure a truly fully nested
structure among the slave IR inputs. If SFNM
is set to a 1, the special fully nested mode is
selected; if SFNM is 0, it is not selected.

}

ROTATE IN MJTOMATIC EOI MODE rCLEAR: }

END OF INTERRUPT

AUTOMATIC ROTATION

4.2 OPERATIONAL COMMAND WORD (OCWs)
}

SPECIFIC ROTATION

Once initialized by the ICWs, the 8259A will most likely
be operating in the fully nested mode. At this point,
operation can be further controlled or modified by the
use of OCWs (Operation Command Words). Three
OCWs are available for programming various modes and
commands. Unlike the ICWs, the OCWs needn't be in
any type of sequential order. Rather, they are issued by
the processor as needed within a program.
Figure 23, the OCW programming format, shows the bit
designation and short definition of each OCW. With the
OCW format as reference, the functions of each OCW
will be explained individually.
1

I

OCW1

OCW1 is used solely for 8259A masking operations. It
provides a direct link to the IMR (Interrupt Mask Register). The processor can write to or read from the IMR via
OCW1. The OCW1 bit definition is as fqllows:
MO-M7: The MO-M7 bits are used to control the masking of IR inputs. If an M bit is set to a 1, it will
mask the corresponding IR input. A 0 clears
the mask, thus enabling the IR input. These
bits convey the same meaning when being
read by the processor for status update.

NOTE 1

X l'JllICAHS 'DON T CARE

I

POLL COMMAND

o ' NO POLL COMMAND

RESET
SPECIAL
MASt(

SPECIAL
MASM

SOME OF THE TERMINOLOGY USED MAY DIFFER SLIGHTlY FROM EXISTING 8259A
DATA SHEETS. THIS IS DONE TO BETTER CLARIFY AND EXPLAIN THE PROGRAM·
MING OF THE 8259A, THE OPERATIONAL RESULTS REMAIN THE SAME.

Figure 23. Operational Command Words (OCWs) Programming Formal

OCW2

OCW2 is used for end of interrupt, automatic rotation,
and specific rotation operations. Associated commands
and modes of these operations (with the exception of
AEOI initialization), are selected using the bits of OCW2
in a combined fashion. Selection of a command or
mode should be made with the corresponding table for
OCW2 in the OCW programming tormat(Figure 20),
rather than on a bit by bit basis. However, for completeness of explanation, bit definition of OCW2 is as
follows:
LO-L2:

The LO-L2 bits are used to designate an interrupt level (0-7) to be acted upon for the operation selected by the EOI, SL, and R bits of
OCW2. The level designated will either be
used to reset a specific ISR bit or to set a
specific priority. The LO-L2 bits are enabled or
disabled by the SL bit.

EOI:

The EOI bit is used for all end of interrupt commands (not automatic end of interrupt mode).
If set to a 1, a form of an end of interrupt command will be executed depending on the state
of the SL and R bits. If EOI is 0, an end of inter·
rupt command won't be executed.

SL:

The SL bit is used to select a specific level for
a given operation. If SL is set to a 1, the LO-L2
bits are enabled. The operation selected by the
EOI and R bits will be executed on the
specified interrupt level. If SL is 0, the LO-L2
bits are disabled.

R:

The R bit is used to control all 8259A rotation
operations. If the R bit is set to a 1, a form of
priority rotation will be executed depending on
the state of SL and EOI bits. If R is 0, rotation
won't be executed.

A-156

AP-59
OCW3

OCW3 is used to issue various modes and commands to
the 8259A. There are two main categories of operation
associated with OCW3: interrupt status and interrupt
masking. Bit definition of OCW3 is as follows:
RIS:

The RIS bit is used to select the ISR or IRR for
the read register command. If RIS is set to 1,
ISR is selected. If RIS is 0, IRR is selected. The
state of the RIS is only honored if the RR bit is
a 1.

RR:

The RR bit is used to execute the read register
command. If RR is set to a 1, the read register
command is issued and the state of RIS determines the register to be read. If RR is 0, the
read register command isn't issued.

P:

The P bit is used to issue the poll command. If
P is set to a 1, the poll command is issued. If it
is 0, the poll command isn't issued. The poll
command will override a read register command if set simultaneously.

SMM:

The SMM bit is used to set the special mask
mode. If SMM is set to a 1, the special mask
mode is selected. If it is 0, it is not selected.
The state of the SMM bit is only honored if it is
enabled by the ESMM bit.

ESMM:

The ESMM bit is used to enable or disable the
effect of the SMM bit. If ESMM is set to a 1,
SMM is enabled. If ESMM is 0, SMM is disabled. This bit is useful to prevent interference
of mode and command selections in OCW3.

5_ APPLICATION EXAMPLES
In this section, the 8259A is shown in three different application examples. The first is an actual design implementation supporting an 8080A microprocessor system,
"Power Fail/Auto Start with Battery Back-Up RAM". The
second is a conceptual example of incorporating more
than 64 interrupt levels in an 8080A or 8085A system,
"78 Level Interrupt System". The third application is a
conceptual design using an 8086 system, "Timer Controlled Interrupts". Although specific microprocessor
systems are used in each example, these applications
can be applied to either MCS-80, MCS-85, MCS-86, or
MCS-88 systems, providing the necessary hardware and
software changes are made. Overall, these applications
should serve as a useful guide, illustrating the various
procedures in using the 8259A.
5_1 POWER FAIL/AUTO-START WITH BATTERY
BACK-UP RAM

The first application illustrates the 8259A used in an
8080A system, supporting a battery back-up scheme for
the RAM (Random Access Memory) in a microcomputer
system. Such a scheme is important in numerical and
process control applications. The entire microcomputer
system could be supported by a battery back-up
scheme, however, due to the large amount of current
usually required and the fact that most machinery is not
supported by an auxiliary power source, only the state
of calculations and variables usually need to be saved.
In the event of a loss of power, if these items are not
already stored in RAM, they can be transferred there and
saved using a simple battery back-up system.

The vehicle used in this application is the Intel®
SBC-80/20 Single Board Computer. An 8259A is used in
the SBC-80/20 along with control lines helpful in implementing the power-down and automatic restart sequence used in a battery back-up system. The SBC-80/20
also contains user-selectable jumpers which allow the
on-board RAM to be powered by a supply separate from
the supply used for the non-RAM components. Also, the
output of an undedicated latch is available to be connected to the IR inputs of the 8259A (the latch is cleared
via an output port). In addition, an undedicated, buffered
input line is provided, along with an input to the RAM
decoder that will protect memory when asserted.
The additional circuitry to be described was constructed on an SBC-905 prototyping board. An SBC-635
power supply was used to power the non-RAM section
of the SBC-80/20 while an external DC supply was used
to simulate the back-up battery supplying power to the
RAM. The SBC-635 was used since it provides an open
collector ACLO output which indicates that the AC
input line voltage is below 103/206 VAC (RMS).
The following is an example of a power-down and restart
sequence that introduces the various power fail signals.
1. An AC power failure occurs and the ACLO goes high
(ACLO is pulled up by the battery supply). This indicates that DC power will be reliable for at most 7.5
ms. The power fail circutry generates a Power Fail Interrupt (PFI) signal. This signal sets the PFI latch,
which is connected to the IRa input of the 8259A, and
sets the Power Fail Sense (PFS) latch. The state of
this latch will indicate to the processor, upon reset,
whether it is coming up from a power failure (warm
start) or if it is coming up initially (cold start).
2. The processor is interrupted by the 8259A when the
PFI latch is set. This pushes the pre-power-down program counter onto the stack and calls the service
routine for the IRa input. The IRa service routine
saves the processor status and any other needed
variables. The routine should end with a HALT
instruction to minimize bus transitions.
3. After a predetermined length of time (5 ms in this example) the power fail circuitry generates a Memory
Protect (MPRO) signal. All processing for the power
failure (including the interrupt response delays) must
be completed within this 5 ms window. The MPRO
signal ensures that spurious transitions on the system control bus caused by power going down do not
alter the contents of the RAM.
4. DC power goes down.
5. AC power returns. The power-on reset circuitry on the
SBC-80/20 generates a system RESET.
6. The processor reads the state of the PFS line to
determine the appropriate start-up sequence. The
PFS latch is cleared, the MPRO signal is removed,
and the PFI latch driving IRa is cleared by the Power
Fail Sense Reset (PFSR).signal. The system then continues from the pre-power-down location for a warm
start by restoring the processor status and popping
the pre-power-down program counter off the stack.
Figure 24 illustrates this timing.

A-IS7

AP-59

POWER DOWN

RESTART

\1..-____

ACLO

~ ___~\-_--l/
IRO

PFSR

MPRO

---+-----------'1-------_.
---+---""

.""

DC----~----------,
7.5 ms min

,------,J
POWER UP
ROUTINE

Figure 24. Power Down Aestart Timing

Figure 25 shows the block diagram for the system.
Notice that the RAM, the RAM decoder, and the power·
down circuitry are powered by the battery supply.
The schematic of the power-down circuitry and the
SBC-80/20 interface is shown in Figure 26. The design is
very straightforward and uses CMOS logic to minimize
the battery current requirements. The cold start switch
is necessary to ensure that during a cold start, the PFS
line is indicating "cold start" sense (PFS high). Thus, for

a cold start, the cold start switch is depressed during
power on. After that, no further action is n.eeded. Notice
that the PFI signal sets the on-board PFI latch. The output of this latch drives the 8259A IRO input. This latch is
cleared during the restart routine by executing an OUTput D4H instruction. The state of the PFS line may be
read oli the least significant data bus line (DBO) by executing an INput D4H instruction. An 8255 port (8255 #1,
port C, bit 0) is used to control the PFSR line.

BATTERY SUPPLY

COLD

~START

CONTROL BUS -t-t---+:---!H-4-'---+--I-.....--++---~H--...J

DATABUS-t~~--'--+-~~~--+--~--++---~~--~

.ADDRESSBUS~~---~-~~---~-----~----~~--~

Figure 25. Block Diagram 01 SBC 80120 with Power Down Circuit

A-15S

AP-59

I
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"'SBATT.

8259

'"'

--+----:<=.---------';'1];:,.<'_________----"Pf"-I~-____--_I>'"
~

5

'"LATCH

CLR

•

RAM CS

i

------+------"-1

P2

+5BA!;.TC;-T

""

DECODER

COLD
START

I

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1_ O.1pF

'---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1I" f--_ _ _ _ _--'-' ' lCO

P~~T

Figure 26. Power Down Circuil - SBC 80120 Inlerlace

The fully nested mode for the 8259A is used in its initial
state to ensure the IRO always has the highest priority.
The remaining IR inputs can be used for any other pur·
pose in the system. The only constraint is that the ser·
vice routines must enable interrupts as early as possi·
ble. Obviously, this is to ensure that the power·down interrupt does not have to wait for service. If a rotating
priority scheme is desired, another 8259A could be
added as a slave and be programmed to operate in a
rotating mode. The master would remain in the initial
state of the fully nested mode so that the IRO still remains the highest priority input.
The software to support the power-down circuitry is
shown in Figure 27. The flow for each label will be
discussed.
After any system reset, the processor starts execution
at location OOOOH (STARn. The PFS status is read and
execution is transferred to CSTART if PFS indicates a
cold start (Le., someone is depressing the cold start
switch) or WSTART if a warm start is indicated (PFS
LOW). CSTART is the start of the user's program. The
Stack Pointers (SP) and device initialization were included just to remind the reader that these must occur.
The first EI instruction must appear after the 8259A has
received its initialization sequence. The 8259A (and
other devices) are initialized in the INIT subroutine.
When a power failure occurs, execution is vectored by
the 8259A to REGSAV by way of the jump table at
JSTART. The pre-power-down program counter is placed
on the stack. REGSAV saves the processor registers
and flags in the usual manner by pushing them onto the
stack. Other items, such as output port status, program-

mabie peripheral states, etc., are pushed onto the stack
at this time. The Stack Pointer (SP) could be pushed onto the stack by way of the register pair H L but the top of
the stack can exist anywhere in memory and there is no
way then of knowing where that is when in the power-up
routine. Thus, the SP is saved at a dedicated location in
RAM. It isn't really necessary to send an EOI command
to the 8259A in REGSAV since power will be removed
from the 8259A, but one is included for completeness.
The final instruction before actually losing power is a
HALT. This minimizes somewhat spurious transitions
on the various busses and lets the processor die
gracefully.
On reset, when a warm start is detected, execution is
transferred to WSTART. WSTART activates PFSR by
way of the 8255 (all outputs go low then the 8255 is initialized). In the power-down circuitry, PFSR clears the
PFS latch and removes the MPRO signal which then
allows access to the RAM. WSTART also clears the PFI
latch which arms the 8259A IRO input. Then the 8259A is
re-initialized along with any other devices. The SP is
retrieved from RAM and the processor registers and
flags are restored by popping them off the stack. Interrupts are then enabled. Now the power-down program
counter is on top of the stack, so executing a RETurn instruction transfers the processor to exactly where it left
off before the power failure.
Aside from illustrating the usefulness of the 8259A (and
the SBC-80/20) in implementing a power failure protected microcomputer system, this application should
also point out a way of preserving the process0r status
when using interrupts.

A-159

AP-59
LllC

55
56

Ur,-,

,liDll f11l',' IJTflEP INIlIALl2P.fIUN::, KEP[
~[T

5\'$rl:~ O;'I)I1TE~

5

~ PT59R
7 PT59B

Eill)
UN!

0[IAf:
!:IDSI'.

SPl'!lU

EO!)

ttli'll

91'r!lC
i~ ~'-SR'1f

11 JrT
12

825~; f-'ORT WllH flti=0
'd<."5~ PORT wlm ,)3=1
.825511(..OIHr."OLf'OJ1';','=1:1
~4

I'I'IENW~M

511'1/<1

81:1

.

2C I>/:.TflRT
d7
~9

Ii TO l.mrUT WlDE
tOlm'OL 1'1.*'1, "r5~',' 1,IJb LUIJ

COMf'lfjN[i r'~~~b pr:..J,',' GJJ LOW rJHICK
ITS LIlTCIl

Je

~lMr.IV[$

I'H'I]

~1, ~i~

tlOOC [dEb
IJ80E[)]t>4
{:I~HI WiDe€!
9013 2flet.C:::
!itl16F9

3'!.

OUT

I'Hle

J'

uur

~S

c.PU

004H
!NIl

LHLD

SI'SfIIlE

RII/E Si' rRI}M

001~' C1
0(!18Di

['Of'

1)019[1

POP
POP

INTli
OC
RI:STDI![DE

PI>'

OOiAFl
~ijlB FG
tlW;C3

~fIM

.PEsrum: f, r'LU5 nfl(i~
ENf1illEINTEFP!Jt-'I$
,I'R[ -PO~EI'"'DDWN /'1; IJN TOP OF SlACk

5~

00lfD?DA
0021][01
~23Mlf!

IN!I

3m

~0

M14

C35~A

~11?

00
~~

q7

Bl1roo

':IS
lae .COLD
101
1<2

n
912031003F

1e3cSrr:rT

~m

'"

3126

5"1

HIlI
uIJT

H.16K
PT59Ff

52

IWI

~~

our

fj,)rl
"T598

e1~'8

f'=LS=LH7-I1'5=e !U41
82:5~ POIi'T 'lI1K He={.!
d'lSBOr .lUI1/' TIltH

j'-':

J',lP
NOP

3~:@H

.IMP
1M

~8T0H

9>::

4::1,
~lC3E16

00

811cm~:>i.l

elL

TO

'!OF'

3118

f'$W

R[]IJ~N

JMI'

~100

011"3C36038

;,gTIJ~'l

RET

N!)P

~108 C2l:!';~

aHlFOO
8110 n4~1!.:

~,e

I:

H

~:;

1~1oJf-:

If(,:,i1"

31&lc:ne?,;

HIGH
8255 11 PO~"I C
I:[SETI"FI U)l[:1I
,Get mInl~LlZ[ EI-'lRl'lf:ING
~'f.:l

OriJ
JMf'

 IN F1.lCI59A. OS.J
ASSE!'IBLER INI/OKED BY· FUiSM86FITCI59A. 5RC
LOC 08.1

LINE

2
3
4
5
6

0120
0120 0491
0122 .YC'??
0124 1801
0126 m·J
0128 3001
012f1 n~n
012C 4801
012E m?
91306001
tlD2,????
01:>47801
0B6Tm

0008 ????

9002 ????
0004 ??

SOURCE

; ******************** TIMER CONTROLLEr> INTeRRUPTS *******************
EXTRA SEGMENT DECLARATIONS

;

7

EXTRA 5t:OMEtfl

g

;

9
ORO
129H
.i TYPE 72 INSTRUCTION POINTER
10 TP72IP OW
INW72
'}
; T\'PE 72 CODE SEGMENT
11 TP72CS DW
INTla3
.i T\'PE 73 INSl RUCTIUN POINTER
12 TP73IP OW
J
i TYPE 73 CODE SI:.GI1ENI
13 TP73CS DIoI
i H'f'E 74 INSTRUCllON POINTER
INTR74
14 TP74IF' OW
; TYPE i' 4 CODE SEGMENT
15 1"f'74CS DW
?
INTR75
; TYrE 75 INSTRUCTION POINTER
16 TF'751F' I)f.I
?
; noPE 75 CODE 5I:.Gl'lENl
1l TP75CS OW
; lYPE i'6 INSTRUCTION POINTER
18 TP76IP I)f.I
INH~76
?
.i TYPE 76 (;ODE SEGMENT
19 TP76CS OW
; TYPE 77 INSTRUCTION PUINTI:.R
20 TP77IP DW
INTR77
?
i TYPE 77 CODE SEGI'IENl
21 IP77CS OW
22 ;
23 EXTRA ENDS
24 • ;
llATA SEGl'lENT DECLARATI ONS
25
26 ;
27 DATA
SEGMENT
2S
; VARlfIb'lE TO SAllE CALL flIIDRtSS
?
29 STACK1 DW
?
3{l
AXTEl1P DIoI
; VARIABLE TO SAVE AX REGISTEk
?
; I/ARIABLE "10 SAVE SELECll:D DIGIT
31 DIGIl DB
32
33 DATIl
ENDS
34 ;
GOOE SEGMENT DECLARATION
35 ;
36
s[GMENT
37 CODE
38
39 ASSIJIE ES :EXTRA, DS: D:lTA, CS : CODE
40
41
INITIflLlZE REGISTERS

42
9000
!l803
0111!5
!l808
000A

B80000
SECll
887000
SED8
1l11781l8

II89D SEOO

90IlF BCS8OO.

41
44
45
46
47
48
49

STRRT:

AX,9H
ES,AX

; OORA SEGPENT AT 9H

AX,79H

; DATA SEGIOT Al 709H

l'lOy
!'lOy

{is,AX
AX, "ISH
5S,AX

; SlACK SEGMENl AT 789H

HOY

SP,88H

; STACK POINTER AT 89H (STflCK=899H)

HOY
I'lOI/
I'm

HOY

A-168

AP.-59
t1C5-86 ASSEMBLER
LOC 08,]

TCl59A

LINE

SOURCE

50
LOA[)

51

IN'ft~:RUf-'l

VECTOR IllBLE

1;;",

.)c.

0012
0015
0019
a01E
8821
13025
e02A
002D
0031
8036
e0J9
eS3D
0042
. 9045
0049
0e4E.
0051
0055

B80401
2GiC2801
268C0E2201
B81801
26A32401
268C8E2601
B83:001
26A:l281:11
268C0E2A01
B84801
26A32C01
268C0E2E01
B86001
26A33W1
268C0E3201
887801
261133401
26SC0E36'e1

0:-'

...':"

54
55
~6

57
58
59
60
61
62
63
6.4
65
66
67
68
69

70
71

WPI:S.

MOV
MOV
MOV
1'101/
flO...
1'10'./
MOI/
1'1011
MOV
MOV
t10V
MOil
MOV
MOil
MOil
MOV

1'10','
MOV

~"
i~

005A BA0EFF
0050 B0:$6
095F EE
0060 B071
9062 EE
0063 80B5
0065 EE
0066 BAeBFF
8069 BeAS
006B EE
006CB061
006E EE
006F BAOCFF
09;'2 B009
0074 EE
0075 8002
0977 EE
0978 Bfll6Fr
0078 B93B
W7D EE
007E 1l07B
0080 EE
0!l81 B0BB
0983 EE
0984 BA10FF
088i' B050
0989 EE
IlI!SA Belli!
008C EE
II98D BA12FF
9090 0000

73
74

75
76
77
78
79
80
81

82
83
84
85
86
87
88

89
90
91

92

SET531. MOV
1'1011
OUT
MOV

olJr
I'IOV
OUT
MOV
MOIl
OUT
Mall
OIJT
MOil
MOl/
OIJT
MOil
OUT
SEPl32. MOil
1'101/

93

our

MOIl
OUT
1'10\1
OUT
MOV
/'10\1
OUT
/'10\1

96

98

99
100
101
102
103
104

I.HHR72)

. LOAD riP!:. /2

(I NTR7})

,LOAD TYPE 73

WITR(4)

; LO® T','PE 74

;. OFf SET
IP72IP. AX
IP72CS, CS
Ai<.. OFFSET
TP73IP, Aii
lP73CS, tS
AX, OFFSET
TP74IP . ftX
TF?4CS . CS
A:(, OFFSET
TP75IP . fiX
W/5CS . CS
AX, OFFSl:l
TP76IP, AX
TP76CS, C5
AX.. OFFSET
TP77IF', AX
IP77CS, CS

OUT
1'10\1
/'I0Il

DK.3FF0EH
AL 36H
I)K.AL
AL.71H
DX,AL
AL9B5H
[)X,AL
[)X, eFFeBH
AL.0ABH
DX,AL
AL.61H
DX,AL
DX, eFFOCH
AL,00H
DX,AL
AL02H
[)X,AL
DX,eFF16H
AL,3BH
DX,AL
AL,7BH
DX,AL
AL, !l88H
DX,AL
DX,0FF10H
AL,50H
DX,AL
AL,OOH
DX,AL
DX, eFF12H
ALOOH

A-169

; 8253 lI1 CONTROL WORD
; COUNTER e.. MODE 3.. BlNARY

,courmR 1..

MODE €I, BCD

; COUNTER 2, MODE 2, BCD
; LOAD COUNTER 0 (101'15)
;L~f)

.:1158
; LOA!) COUNTER 2 (2SE.C)
;LSEl

;MSB
; 13253 *2 CONl ROL WORD
; COUNTER 0, MODE S,8CD
; COUNTER 1, MODIO

~,

BCD

-' COUNTER 2, I'IODE 5, BCD
; LOAD COUNTER 0 C 551:0
;L:lB
.;1158
; LOAD COUNTER 1 (lSEt)
iL58

AP~59
M(;S-86 ASSEMBLER
LOC OS']
0092 EE
0093 8001
0IJ95 EE
0096 BA14rr
0099 B050

TCI59A

LINE
105

WI

009(; 8081
099E EE

111

BAOOFF
B013
EE
BA02fT
B048
EE
B003
EE
B0E0
EE

0081 BAEAFF
O8848000
0086 EE
0987 EC
80B8 09C0
098A?2FB
OOBC 808?
09BE EE
OOBF BAE8FF
98C2 8086
90C4 EE
00C5 BAEAFF
119C8 BOS6
98CA EE
OOCB BAE8FF
OOCE 805O
00D0 EE
0001 FB

OUT
1'1011
OUT
MOY
i'IOV
OUT
MOil
OU1

196
107
108
109

0098 1£

009r
OOA2
00A4
OOA5
00A8
00AA
OOAB
OOAD
OOAE
00B0

SOURCE

112
113
114
115
116
117
113
119
121.1

129
130
131
132
11$

LOAI) COUNTffi 2 (1. 5SEC)
, L!!B

i

iMSB

8259fl INITIALIZATION
SET59A: MOY
1'1011
OUT
1'1011

1'10',1
OUT

liOY
OUT
MOY
OUT

D;':,8FF00H
ALl3H
DX,AL
OX, !lFF02H
AL, 4SH
OX,AL
AL, 0~H
DX. AL
AL,9E0H
OX, AI..

.'!1259A AIl=0
, lCloIl-L TIll=!!. S=1, IC4=1
8259A flO=i
; ICW2-INTERRUPT TYf'l:: "12 (120H)

i

; ICIoI4-SFNI'I=0, BUr=!!.. AEOI=L MPI'I=1
i

0CI0I1-MASK IRS, 6, 7 (NOT USED)

8279 INITIALIZATION
.
~T79:

MOV
I'IOY
OUT
WAIT79: IN
~

.JB
i'IOY
OUT
HOY
MOil
OUT
110Y
HOY
OUT

134

135
136

137
138
139
140
141
142
143
144
145
146
147

,lise

;

121
122
123
124
125
126
127
128

OX. AL
AL01H
OX. AL
Ox'.0FF14H
AL . 50H
DX, AI..
AI.. . 81H
DX. A1..

I'IOY

I'IOY
OOT

OX,0FFEAH
AL,0D0H
OX.. AL
AI.. OX
AL,1
WAIT79
AI.., 87H
OX,AL
OX,8FFESH
AI.,86H
DX,AL
OX,9FFEAH
AL,86H
OX, AI.
DX,8FFESH
AI..,50H
OX, AI.

i 8279 COI'IMAND 1oIOR0S f1N/.l STATUS
; CLEAR DISPLAY
i REP,o

S1ATUS

; '00" BIT JO CARRY
i.JUMP IF OI5f'LAY IS UIfIYAILABLE
;OIGlT 8

,8279 DATA IoMJRO
; CHARACTER "I •
; 8279 COI'IIIAND WORD
; DIGIT 7
; 8"'lf9 DATA IoIORD
; CHARf{;TER "R"

.' BflBLE ItlTERRUf'TS

511
;

143
00D2EBFE

00D4 A30200
000758
0008 A39998
OODB A10280
000E 50
000F 53

149
150
151
152
15J
154
155
156
157

OOMl'lY PROGRAlt

oomrr': JMP

DUMI'IY

; WAIT FOR INTERRUPT

SAVE:

AXTEMP,AX
AX
STACK1,AX
AX. AXIDIP

; SAVE AX
; POP CflLL RETURN AOORESS
; SAVE CALL RETlRN ADDRESS
;RESTORE AX
; SAVE PROCESSll1 STATUS

MOY
POP
1'101/
I'lO\l

1~

PUSH

159

PUSH

AX

ax

A-170

AP-59
M(;S-86

A~SEMBLER

LOC OB..!
OOEIl
OOE1
BBE2
00B
01.lE4
01.lE5
0I.lE6
0I.lE7
OOEA
13I.lEB

)1
52
55
56
57
lE
06
Al0000
50

n

0I.lEC 58
0I.lED A3e13ee
00Fe 07
00F11F
OOF2 SF
··00F3 SE
OOF4 5D
0eF; 5A
00F6 59
ooF7 58
00F8 58
OOF9 A30200
OOFC A10000
OOFF 50
0100 AH12131.l
0103 G

0104
a107
010A
0100
01eE
al11
01B
0114
0117

ESCDFF
BAEAFF
A00409
EE
BAEBfF
8000
EE
E8D5FF
CF

TCI'S9A
LINE

SOIJRCE

161l
161
162
163
164
165
166
167

PUSH
PUSH
F1JSH
PUSH
PUSH
PUSH
PUSH
MOV
PUSH
RET

161]
169
170
171
172
173
174
175
176
l"(l
178
179
180
181

182
183
184
185
186
187
18S
189
190
191
192
193
194
195
196
197
1:38

199

RtSTOR. POP
MOil
POP
POP
POP
POP
POP
POP
POP
POP
POP
1'101/
MOl/
PUSH
MOV
RET

C:~

DX
BP
51
DI
DS
ES
AX, STACK!
It,

,RESTORE CALL RETURN AOORES5
; PUSH CALL RIO1LlRN AOORES5

; POP CALL RETURN AD()R[SS
; SAVE CALL RETURN ADDRESS
,RESTORE PROCESSOR STATIJ5

fiX
STACKL A;';
ES
DS
DI
51
BP
DX

ex
ex
AX
AXTEMP.• AX
AX, STACK1

.' SAVE AX
; RESTORE CALL RETURN ADORESS
; PUSH CiU RETURN ADDRESS
; RESTORE AX

~"<

AK. AXTEMP

;

INTERRUPT 72, CLEAR DISPLfI\" IR0 325911
INTR72: CALL
MOil
MOil
OUT
MOil
1'101/
OUT
CALL
IRET

SAVE
D)(,OFFEAH
AL DIGIT
ox.AL
OK.0FFESB

; ROllT! NE TO SAVf. PROCESSOR Sl ATlJS
; 8279 COMMAND WORO
.: SELECTED LED 0I GIl
; 8279 DATA
; BLANK OUT DIGIT

ALOOH
DX,AL
RESTOR

.: ROUTINE TO RES) ORE PROCE5SOk STfn US
; RETURN FkOI'l INTERRUf'l

200
2131
INTEkRUPT

202
2133
0118
0118
0UE
0120
13123
0124
0127

EB89FF
BflEAFF
B13B8
A20400
EE
BAESFF
8006
01~ EE
91<''11 CD4D
012(; EBBDFF
912~ CF

204
205
206
207
2!lB

2139
210
211

212
213
214

INTR73: CALL
I'1OV
1'1011
MOil
OLiT
MOil
1'1011
OUT
INT
CALL
IRET

n,

SAllE
DX,0FFEAH
AL,8!IH
DIGIT, AL
DX,AL
DX,8FFE8H
AL,06fj
DX,AL
77
RESTOR

A-171

IR1 825911
.: ROUTINE 10 SAlit PROCESSOR STAlUS
,8279 COft1ANl) WORD
i LEO llISPLAY DIGIT 1

.' 82(9 DATA
; CHARfl(;·'ER "1"
i 1IMER DELAY FOR LED ON TIME
; ROUTINE 10 RESTORE PROCI::SSOR STATIJ5
; RETURN FROM INTERRUPT

AP-59
t1C5-86 ASSEH8ltR
LOC 08J

TCI59A

LINE
215

SOURCE
;

216
INTERRUPT 74, Ik2 8259F:

~17

0130 E8A1FF
0133 SAEAFF
0136 B081
0138 A20400
0138 EE
813C IlftESFF
013FB05B
8141 EE
8142 CD4I)
0144 E9ASFF
0147 cr

8148 E889FF
0148 BAEAFI'
914E B082
9150 A20400
(j153EE
9154 SAESFF
015789#
9159 EE
91~A CD4D
9151: E88DFF
915F CF

9169
9163
9166
9168
016B
016C

E871FF
SAEAFF
B983
A20400
EE
SAESFF

016F 8066
0171
0172
0174
0177

81i'8
9178
0170
01lE
0180

EE
CD4D
E875FF
CF

BA9AFF
8825
EE
B909
EE

9181 CF

218
219
220
221
222
223
224

;

INTR74: CALL
MOY
I'IOV
MOil
OUT

MOV
MOil
OUT
INT
t'AlL
IRI01

225
226

227
229
229
238
231
232
233
234
235
236
237
238
239
240
241
242

;
;

244
245
246
247
248
249

259
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269

n

RESTOR

; ROUTINE TO SAVE PROCESsOR Sl ATUS
; 8279 COI'II'IAND WORD
; LED DISPLAY DIGI"I 2

; 8279 DA1A
; CHARACTER "2"
; TIMER DELAY FOR LED ON TIME
; ROlITIt£ TO RESTORE PROCESSOR SlATU5
.: RETURN FROM INTERRUPl

INTERRUPT 75.• IR3 8259A

INTR75: CAlL
I'lO\l
MOil

110\1
OUT
11011
MOil
OUT
INT
CAlL
IRET

24~

SAVE
DX,0FFEAH
AL.81H
DIGIT, Al
DX,Al
DX,0FFE8H
AL,5811
DX,Al

SAVE
D)(,0FFEAH
AI., 82H
DIGIT, Al
DX,Al
D)(,0FFESH
AL,4FH
DX,AL
77
RESTOR

; ROUTINE TO SAllE. PROCESSOR STATUS
.; 8279 COI'fI1ANI) WORD
; LED DISPLAY Dim T 3

; 8279 DATA
; CHARACTER "3"
; TIMER DELAY FOR LED ON TIME
; ROUTINE TO RESTORE PROCESSOR STATUS
; RE1URN FROM IN1Ek'RUPT

;

INTERRUPT 76, IR4 8259A

;

INTR76: CALL

110\1
/'IOV
MOil
OUT
I'IOY
1'1011
OUT
INT

CALL

SAVE
D)(,0FFEAH
fl.,83H
DIGIT, AL
D)(,AL
D)(,0FFESH
Al,66H
DX,AL
77
RESTOR

IRET

; ROUTINE TO SAVE PROCESSOR 51 ATUS
; 8279 COI'IIfINI) WORD
; LED DISPLAY blGIT 4

;82i'9 DATA
; CHARAtTlR "4"
; lIMER DaAY FOR LEII ON 111'[
; ROUTINE TO RESTORE PROCESSOR Sl ftTUS
; RETURN FRO/1 I N1 ERRUPT

INTERRUPT 77, mlER bElAY, SOFTWARE CONTROllED
INTR77: I10Y
I10Y
OUT
IIJV
OUT
IRET

D)(,0FF9AH
Al,25H
DX,Al
ALII9H
DX,AL

; LOft) COUNTER 1 8253 11 (259 I'ISEC)

; l!!I
; I1SB
; RETURN FROI'I INlERRUPT

A-ln

AP-59
11C5-86 ASSEt1BLER

TCl59A

LOC OB..!

LIN::
270
271
272

",,,,,
.. -'

SOURCE

CODE

ENDS .•

~

274
275

0000

END

START

S't'MBOL TABLE LE.TING

------ ----- ------NffME

TYPE

??SEG

SI:GMENT

AXTEMP
CODE.
[)ATA
DIGIT
DUMMY

V WORD

VALUE ATTRIBUTES

5j ZE =000lJH
a002H DATA
SEGMENT
SIZE =0182H
SEGMENT
SIZE=OOBSH
II BYTE 1j0!34H DATA
L NEAR B@D2H CODE
EXTRA SEGMENT
51 ZE=9138H
INTR72 L NEAR 91!34H COllE
INn'?:? L NEAR 81181-: CODE
INTR74 L NE.AR 0130H CODE
INTR75 L NEA~' 0l48H CODE
INTR76 L NEAR B160H CODE
INTR?? L NEAR 9l7SH CODE
RESTOR. L NEAR 00ECH CODE
SAVE.
L NE'lR OOD4H CODE
SET531 L NEAR 005flH CODE
5ET532 L NEAR 097S}! CODE
SET59A L NEAR 009rH CODE
5ET79 L NEAR 00S1H CODE
STACKl II WORD 009flH DATA
START L NEAR O9OOH CODE
TP72CS V WORD 8l22H EXTRA
TP72IP V WOfi'D 9l2aH EXTRA
TP73CS II WORD 8126H EXTRA
TF'73IP V "'ORD 8124H EXTRA
TP?4CS II WORD 012AH EXTRA
TP741P V WORD 8128H EXTRA
TP75C5 .., WORD 9l2EH EXTRA
TP751P II WORD 012CH EXTRA
TP76(:5 II WORD 0B2H EXTRA
TP761P II WORD 9B0H EXTRA
Trncs II WORD 9B6H EXTRA
TP77IP II WORD flB4H EXTRA
TYPES L NEAR 0fl12H CODE
WAIT79 L NEAR OOB7H CODE

PARA PIJSLI C
PARA
PARA

PARA

f:SSEMBL \' COMPLETE.. NO ERRORS FOUND

A173/A-174

APPLICATION
NOTE

AP-28A

January 1979

©

Intel Corporation, 1979.

A-175

9800587C

AP-28A

Related Intel Publications
MCS-80™ User's Manual, 98-153D
MCS-85T M User's Manual, 98-366C.
MCS-86T M User's Manual, 9800722A.
iSBC 80/20 and iSBC 80/20-4 Single Board Computer Hardware Reference
Manual. 98-317C.
iSBCTM 86/12 Single Board Computer Hardware Reference Manual,
9800645A.
Intel® Multibus™ Specification, 9800683.

A-176

AP·28A

Intel MUlTIBUS™
Interfacing
R

Contents
I.

INTRODUCTION

II.

MULTIBUSTM SYSTEM BUS
DESCRIPTION
OVERVIEW
MULTIBUSTM SIGNAL DESCRIPTIONS
OPERATING CHARACTERISTICS
MULTIBUSTM SLAVE INTERFACE
CIRCUIT ELEMENTS

III. MULTIBUSTM SLAVE DESIGN
EXAMPLE
FUNCTIONAL/PROGRAMMING
CHARACTERISTICS
THEORY OF OPERATION
IV. SUMMARY
APPENDIX A
MUL1'IBUSTM PIN ASSIGNMENTS
APPENDIX B
BUS TIMING SPECIFICATIONS
APPENDIXC
BUS DRIVERS, RECEIVERS,
AND TERMINATIONS
APPENDIX D
BUS POWER SUPPLY
SPECIFICATIONS
APPENDIX E
MECHANICAL SPECIFICATIONS
APPENDIX F
MULTIBUSTM SLAVE DESIGN
EXAMPLE SCHEMATIC, 8/16-BIT
VERSION
APPENDIXG
MULTIBUSTM SLAVE DESIGN
EXAMPLE SCHEMATIC, 8-BIT
VERSION

A-i77

AP-28A
I. INTRODUCTION

control the bus. Memory and I/O expansion
boards are examples of bus slaves. The MULTIBUS architecture provides for both 8 and 16-bit
bus masters and slaves.

A significant measure of the power and flexibility
of the Intel OEM Computer Product Line can be
attributed to the design of the Intel MULTIBUS
system bus. The bus structure provides a common
element for communication between a wide
variety of system modules which include: Single
Board Computers, memory, digital, and analog
I/O expansion boards, and peripheral controllers.

Notice that a system may have a number of bus
masters. Bus arbitration results when more than
one master requests control of the bus at the same
time. A bus clock is usually provided by one of the
bus masters and may be derived independently
from the processor clock. The bus clock provides a
timing reference for resolving bus contention
among multiple requests from bus masters. For
example, a processor and a DMA (direct memory
access) module may both request control of the
bus. This feature allows different speed masters to
share resources on the same bus. Actual transfers
via the bus, however, proceed asynchronously
with respect to the bus clock. Thus, the transfer
speed is dependent on the transmitting and
receiving devices only. The bus design prevents
slow master modules from being handicapped in
their attempts to gain control of the bus, but does
not restrict the speed at which faster modules can
transfer data via the same bus. Once a bus request
is granted, single or mUltiple read/write transfers
can proceed. The most 0 bvious a pplica tions for the
master-slave capabilities of the bus are multiprocessor configurations and high-speed directmemory-access (DMA) operations. However, the
master-slave capabilities of the bus are by no
means limited to these two applications.

The purpose of this application note is to help you
develop a working knowledge ofthe Intel MULTIBUS specification. This knowledge is essential for
configuring a system containing multiple modules. Another purpose is to provide you with the
information necessary to design a bus interface for
a slave module. One ofthe tools that will be used to
achieve this goal is the complete description of a
MULTIBUS slave design example. Other portions
of this application note provide an in depth
examination of the bus signals, operating characteristics, and bus interface circuits.
This application note was originally written in
1977. Since 1977, the MULTIBUS specification
has been significantly expanded to cover operation with both 8 and 16-bit system modules and
with an auxiliary power bus. This application
note now contains information on these new
MUL TIBUS specification features.
In addition, a detailed MULTI BUS specification
has also been published which provides the user
with further information concerning MULTIBUS
interfacing. The MULTIBUS specification and
other useful documents are listed in the overleaf of
this note under Related Intel Publications.

MULTIBUS™ Signal Descriptions
This section defines the signal lines that comprise
the Intel MULTIBUS system bus. These signals
are contained on either the PI or P2 connector of
boards compatible with the MULTIBUS specification. The PI signal lines contain the address,
data, bus control, bus exchange, interrupt and
power supply lines. The P2 signal lines con tain the
optional auxiliary signal lines. Most signals on
the bus are active-low. For example, a low level on
a control signal on the bus indicates active, while a
low level on an address or data signal on the bus
represents logic "1" value.

II. MULTIBUSTM SYSTEM BUS
DESCRIPTION
Overview
The Intel MULTIBUS signal lines can be grouped
in the following categories: 20 address lines, 16
bidirectional data lines, 8 multilevel interrupt
lines, and several bus control, timing and power
supply lines. The address and data lines are
driven by three-state devices, while the interrupt
and some other control lines are open-collector
driven.

NOTE
In this application note, a signal will be
designated active-low by placing a slash (I)
after the mnemonic for the signal.

Modules that use the MULTIBUS system bus have
a master-slave relationship. A bus master module
can drive the command and address lines: it can
control the bus. A Single Board Computer is an
example of a bus master.. A bus slave cannot

Appendix A contains a pin assignment list of the
following signals:

A-178

AP-28A
MULTIBUS PI Signal Lines-

assigned the same memory addresses. INHlI
may also be used to allow memory mapped I/O
devices to override RAM memory.

Initialization Signal Line
INITI

INH21

Initialization signal; resets the entire system to
a known internal state. INIT I may be driven by
one of the bus masters or by an external source
such as a front panel reset switch.

. Inhibit ROM signal; prevents ROM memory
devices from responding to the memory address
on the system address bus. INH21 effectively
allows auxiliary ROM (e.g., a bootstrap program) to override ROM devices when ROM and
auxiliary ROM memory are assigned the same
memory addresses. INH21 may also be used to
allow memory mapped I/O devices to override
ROM memory.

Address and Inhibit Lines
ADROI - ADR131

20 address lines; used to transmit the address of
the memory location or I/O port to be accessed.
The lines are labeled ADROI through ADR9/,
ADRAI through ADRF I and ADRlOl through
ADR13/. ADR131 is the most significant bit.
S-bit masters use 16 address lines (ADROI ADRF I) for memory addressing and S address
lines (ADROI - ADR7 I) for I/O port selection.
16-bit masters use all twenty address lines for
memory addressing and 12 address lines
(ADROI - ADRB/) for I/O port selection. Thus,
S-bit masters may address 64K bytes of memory
and 256 I/O devices while 16-bit masters may
address 1 megabyte of memory and 4096 1/0
devices. (The SOS6 CPU actually permits 16
address bits to be used to specify I/O devices,
the MULTIBUS specification, however, states
that only the low order 12 address bits can be
used to specify I/O ports.) In a 16-bit system,
the ADROI line is used to indicate whether a low
(even) byte or a high (odd) byte of memory or
I/O space is being accessed in a word oriented
memory or I/O device.

Data Lines
DATOI - DATFI

16 bidirectional data lines; used to transmit or
receive information to or from a memory location or I/O port. DATFI being the most significant bit. In S-bit systems, only lines DATOI DAT7I are used (DAT7I being the most significant bit). In 16-bit systems, either S or 16 lines
may be used for data transmission.

Bus Priority Resolution Lines
BCLKI

Bus clock; the negative edge (high to low) of
BCLKI is used to synchronize bus priority resolution circuits. BCLKI is asynchronous to the
CPU clock. It has a 100 ns minimum period and
a 35'1l1 to 65% duty cycle. BCLK/ may be slowed,
stopped, or single stepped for debugging.

BHENI

Byte High Enable; the address control line
which is used to specify that data will be transferred on the high byte (DATSI - DATF I) of the
MUL TIBUS data lines. With current iSBC
boards, this signal effectively specifies that a
word (two byte) transfer is to be performed. This
signal is used only in systems which incorporate
sixteen bit memory or I/O modules.
INHlI

CCLKI

Constant clock; a bus signal which provides a
clock signal of constant frequency for unspecified general use by modules on the system bus.
CCLKI has a minimum period of 100 ns and a
35% to 65% duty cycle.
BPRNI

Inhibit RAM signal; prevents RAM memory
devices from responding to the memory address
on the system address bus. INHlI effectively
allows ROM memory devices to override RAM
devices when ROM and RAM memory are

Bus priority in signal; indicates to a particular
master module th,flt no higher priority module
is requesting use of the system bus. BPRN I is
synchronized with BCLK/. This signal is not
bused on the backplane.
A-179

AP~28A

BPROI

Bus priority ollt signal; used. with serial (daisy
chain) bus priority resolution schemes. BPROI
is passed to the BPRNI input of the master
module with the next lower bus priority. BPROI
is synchronized with BCLK/. This signal is not
bused on the backplane.

the bus master in response to a read or write
command signal.
MRDCI

Memory read command; indicates that the
address of a memory location has been placed
on the system address lines and specifies that
the contents (8 or 16 bits) of the addressed
location are to be read and placed on the system
data bus. MRDC/ is asynchronous with respect
to BCLKI.

BUSYI

Bus busy signal; an open collector line driven
by the bus master currently in control to indicate
that the bus is currently in use. BUSY/prevents
all other master modules from gaining control
of the bus. BUSY I is synchronized with BCLKI.

MWTCI

Memory write command; indicates that the
address of a memory location has been placed
on the system address lines and that data (8 or
16 bits) has been placed on the system data bus.
MWTCI specifies that the data is tq be written
into the addressed memory location. MWTCI is
asynchronous with respect to BCLKI.

BREQI

Bus request signal; used with a parallel bus
priority network to indicate that a particular
master module r(;)quires use of the bus for one
or more data tran~fers. BREQI is synchronized
with BCLKI. This signal is not bused on the
backplane.

lORCI

110 read command; indicates that the address
of an input port has been placed on the system
address bus and that the data (8 or 16 bits) at
that input port is to be read and placed on the
system data bus. IORCI is asynchronous with
respect toBCLKI.
.

CBRQI

Common bus request; an open-collector line
which is driven by all potential bus masters
and is used to inform the current bus master
that another master wishes to use the bus. If
CBRQi is high, it indicates to the bus master
that no other master is requesting the bus, and
therefore, the present bus master can retain the
bus .. This saves the bus exchange overhead for
the current master.

lOWCI

I/O write command; indicates that the address
of an output port has been placed on the system
address bus and that the contents ofthe system
data bus (8 or 16 bits) are to be output to the
address port. IOWCI is asynchronous with
respect to BCLKI.

Information Transfer Protocol Lines
A bus master provides separate read/write
command signals for memory and I/O devices:
MRDC/, MWTC/, lORCI and IOWC/, as explained below. When a read/writecommand is
active, the address signals must be stabilized at all
slaves on the bus. For this reason, the protocol
requires that a bus master must issue address
signals (and data signals for a write operation) at
least 50 ns ahead of issuing a read/write command
to the bus, initiating the data transfer. The bus
master must keep address signals unchanged until
at least 50 ns after the read/write command is
turned off, terminating the data transfer.

XACKI

Transfer acknowledge signal; the required
response of .a slave board which indicates that
the specified read/write operation has been
completed. That is, data has been placed on, or
accepted from, the system data bus Hnes.
XACKI is asynchronous with respect to BCLKI.
Asynchronous Interrupt Lines
INTOI - INT7 I

A bus slave must provide an acknowledge signal to

8 Multi·level, parallel interrupt request lines;

A-I80

AP-28A
sense latch is part of external power fail circuitry and must be powered by the standby
power source.

used with a paralleL interrupt resolution network. INTO. has the highest priority, while
INT7/ has lowest priority. . Interrupt lines
should be driven with open collector drivers.

PFSRi
INTAI

Puu'er fail sellse reset; this line is used to reset
the power fail sense latch (PFSNi).

Interrupt acknuwledge; an interrupt acknowledge line (INTA/), driven by the bus master,
requests the transfer of interrupt information
onto the bus from slave priority interrupt controllers (8259s or 8259As). The specific information timed onto the bus depends upon the
implementation of the interrupt scheme. In
general, the leading edge of INTAI indicates
that the address bus is active while the trailing
edge indicates that data is present on ~he data
lines.

MPRO/

Memory protect; prevents memory operation
during period of uncertain DC power, by inhibiting memory requests. MPRO/ is driven
by external power fail circuitry.
ALE

Address latch enable; generated by the CPU
(8085 or 8086) to provide an auxiliary address
latch.

MULTIBUS P2 Signal Lines - The signals
contained on the MULTIBUS P2 auxiliary connector are used primarily by optional power
back-up circuitry for memory protection. P2
signals are not bused on the backplane, and
therefore, require a separate connector for each
board using the P2 signals. Present iSBC boards
have a slot in the card edge and should be used
with a keyed P2 edge connector. Use of the P2
signal lines is .optional.

HALT!
Halt; indicates that the master CPU is halted.

AUX RESET!
Auxiliary Reset; this externally generated signal initiates a power-up sequence.

ACLO

WAIT!

AC Low; this signal generated by the power
supply goes high when the AC line voltage
drops below a certain voltage (e.g., 103v AC in
115v AC line voltage systems) indicating D.C.
power will fail in 3 msec. ACLO goes low when
all D.C. voltages return to approximately 95%,
of the regulated value. This line must be pulled
up by the optional standby power source, if one
is used.

Bus master wait state; this signal indicates
that the processor is in a wait state.

Reserved - Several· Pi and P2 connector bus
pins are.unused. However, they should be regarded as reserved for dedicated use in future Intel
products,

PFINI
Power Supplies - The power supply bus pins
are:detailed in Appendix A which contains the
pin assignment of signals on the MULTIBUS
backplane.

Power fail interrupt; this signal interrupts the
processor when a power failure occurs, it is
driven by external power fail circuitry.

PFSNJ

It is the designer's res,pousibility to provide
adequate bulk decoupling on the board to avoid
current surges on the power supply lines. It is also
recommended that you provide high frequency

Power fail sense; this line is the output".of a
latch which indicates that a power failure has
occurred. It is reset by PFSR/. The power fail

A-lSI

AP ..28A

deco.upling fur the lo.gic un yo.ur bo.ard .. Values. 0..£
22uF fDr +5v and +I2v pins and lOuFfDr -5v a~d
-I2v pins are typical Dn iSBC bo.ards.

-tcMO-----..
10RCI

MRDel

('

.Operating Charac,teristics
BeYDnd the definitio.n Df the MULTIBUS signals
themselves, it is impurtant to. examine the
o.perating characteristics uf the bus. The AC
requirements uutline the timing ufthe bus signals
and in particular, define the relatiunships between
the vario.us bus signals. On the uther hand, the DC
requirements specify the bus driver characteristics, maximum bus luading per buard, and the
pull-up/do.wn resisto.rs.

Flgur!l1_ .Read AC Timing

Write Data;
The write o.peratiDn AC timing diagram is shDwn
in Figure 2: During a write data transfer, valid
data must be presented simultaneDusly with a
stable address. Thus, the write data setup time
'(tDS) has the same requirement as the address
setup time (tAS)' The requirement fDr stable data
bo.th befo.re and after cQmmand(IOWC/ or
MWTC/) enables the 'bus interface circuitry to.
latch data o.n.either the leading 0.1' trailing edge Df
cDmmand;·· •

The AC requirements are best presented by a
discussio.n o.f the relevant timing diagrams.
Appendix B co.ntains a list uf the MULTIBUS
timing specifications. The full owing sectiDns will
discuss data transfers, inhibit uperatio.ns, interrupt operatio.ns, MULTIBUS multi-master o.peratio.n and pDwer fail co.nsideratio.ns.
Data Transfers - Data transfers on the MULTIBUS system bus o.ccur with a maximum bandwidth Df 5 MHz fur single 0.1' multiple read/write
transfers. Due to. bus arbitrati,Qn and memo.ry
access time, a typical maximum transfer rate is
Dften Dn the Drder o.f 2 MHz.

MASTER
TO

SLAV!;

Read Data

Figure 2. Write AC Timing

Figure I sho.ws the read DperatiDn AC timing
diagram. The address must be stable (tAS) fDr a
minimum Df 50 ns befDre cDmmand· (IORC/ Dr
MRDC/). This time is typically used by the bus
interface to' decDde the address and thus prDvide
the required device selects. . The device selects
establish the data' paths un the user system in
anticipatiDn o.f the strDbe signal (cDmmand)
which will fo.llDW. The minimum cDmmand pulse
width is 100 ns. The address must remain stable
fDr at least 50 ns fo.llDwing the co.mmand (tAH): '
Valid data sho.uld nut bedriven unto. the qus prio.r
to. cDmmand, and must nut be remDved until the
co.mmand is cleared. The XACK/ signal, which is
a respDnse indicating the specified read/w:rite
Dperatio.n has been cDmpleted,must cDincide'or
fDllo.w bDth the read access and valid d~ta (fDXL)XACK/ must be held until the cDmma:ndis cleared
(tXAH)A~182

Data Byte Swapping in 16-bit Systems
A IS-bit master may transfer data un the MULTIBUS data lines using 8~bit or IS-bit paths
depending un whether a byte 0.1' wo.rd (2 byte)
o.peratiDn has been specified. (A wo.rd transfer
specified with an Ddd 110 0.1' memo.ry address will
actually be executed as two. single byte transfers.)
An.8:bit master may o.nly perfo.rm byte transfers
un the MULT!BUS data lines DATOI - DAT7I.
In o.rder to. maintain co.mpatibility with Dlder
8·lJitmasters and slaves, a byte sw'apping QUfrer
is included in all new 16-bit masters and IS-bit
slaves. Inthe iSBOpto.duct line, all byte transfers '
will take place un the IDW 8 data·lines DATOI .
DAT7I. Figure 3 co.ntains a example o.f 8/IS·bit

AP-28A

data driver logic for I6-bit master and slave
systems. In the S/16-bit system, there are three
sets of buffers; the lower byte buffer which
accesses DATOI - DAT7I, the upper byte buffer
which accesses DATSI - DATF/, and the swap
byte buffer which accesses the MULTI BUS data
lines DATOI - DAT7I and transfers the data
to/from the on-board data bus lines DS - DF.

USER BUS

MUL TlBUS

LOWER
BYTE

BUFFER

8287

•

00·07 •

DATO/-DAT7/

A
OE

T

DIRECTION

Figure 4 summarizes the Sand 16-bit data paths
used for three types of MULTI BUS transfers. Two
signals control the data transfers.

SWAP

BYTE

DATOI

BUFI'"ER

QATF!

Byte High Enable (BHEN/) active indicates that
the bus is operating in sixteen bit mode, and
Address Bit 0 (ADRO/) defines an even or odd byte
transfer address.
On the first type of transfer, BHENI is inactive,
and ADROI is inactive indicating the transfer of
an even eight bit byte. The transfer takes place
across data lines DATOI - DAT7I.

08·0>

MULTIBUS

UPPER

BUFFERED
BHENI
ADRO

On the second type oftransfer, BHEN I is inactive,
and ADROI is active indicating the transfer of a
high (odd) byte. On this type of transfer, the odd
(high) byte is transferred through the Swap Byte
Buffer to DATOI - DAT7I. This makes eight bit
and sixteen bit systems compatible.
16-BIT DEVICE

+-------+1
BYTE
BUFFER

Figure 3. a/16-Bit Data Drivers

DEVICE
BYTE
TRANSFERRED

BHENI

ADROI

H

H

8-BIT.
DATOI - DAT71

EVEN

H

L

8-BIT.
DATO/- DAT71

ODD

L

H

16-8IT.
DATOI - DATFI

EVEN
AND
ODD

MULTIBUS
TRANSFER
DATA PATH

DATOI - DAT7!

DATFI

Figure 4. a/16-Bit Device Transfer Operation

A-I83

AP-28A
The third type of transfer is a 16' bit (word)
transfer. This is indicated by BHEN/ being
active, and ADROj being inactive. On this type of
transfer, the low (even) byte is transferred on
DATO/ - DAT7I and the high (odd) byte is
transferred on DATS/ - DATF/.
Note that the condition when both BHEN/ and
ADROI are active is not used with present iSBC
boards. This condition could be used to transfer a
high odd byte of data on DAT8/ - DATF/, thus
eliminating the need for the swap byte buffer.
However, this is not a recommended transfer type,
because it eliminates the capability of communicating with 8-bit modules.

memory mapped I/O, which has actual memory
occupying the memory mapped I/O address
space, may need to inhibit RAM or ROM memory
to perform its functions.
There are two essential requirements for a successful inhibit operation. The first is that the inhibit
signal must be asserted as soon as possible, within
a maximum of 100 ns (tCl), after stable address.
The second requirement for a successful inhibit
operation is that the acknowledge must be delayed
(tXACKB) to allow the inhibited slave to terminate any irreversible timing operations initiated by detection of a valid cornmand prior to its
inhibit.
This situation may arise because a command can
be asserted within 50 ns after stable address (tAS)
and yet inhibit is not required until 100 ns (tID)
after stable address. The acknowledge delay time
(tXACKB) is a function of the cycle time of the
inhibited slave memory. Inhibiting the iSBC 016
RAM board, for example, requires a minimum of
1.5 usec. Less time is typically needed to inhibit
other memory modules. For example, the iSBC 104
board requires 475 ns.
Figure 5 depicts a situation in which both RAM

Inhibit Operations - Bus inhibit operations are
required by certain bootstrap and memory mapped
I/O configurations. The purpose of the inhibit
operation is to allow a combination of RAM , ROM,
or memory mapped 110 to. occupy the same
memory address space. In the case of a bootstrap,
it may be desirable to have both ROM and RAM
memory occupy the same address space, selecting
ROM instead of RAM for low order memory only
when the system is reset. A system designed to use

ADDRESSI

~..1 - - - ' - - - - - - - - - - 1 1

llL....

DATAl

/

1

i

COMMAND!

I
ENABLE
DRIVERI

SLAVE A

(RAM)

XACKI

LOCAL
SELECT I

1

I I

,.----

READ DATA

--11

________

~I- - - - - - - '
I

----I

/"

!

_

1--J
\I~I----~\~(I~--------------

~\

I

\

1---- -

I RAM XACK IF NOT INHIBITED
I
f---C------~

'XACKA

---I

DRIVER
ENABLE!

XACKI
SLAVE B
(PRO",,)

INH11

'xm; \ - - 1

\ 1---- 'IO-~}
~

I

r
!

---.. ~~~.~------------------I
\

LOCAL
SELECT I

Figure 5. InhibilTiming

A-184

AP-28A
and PROM memory have the same memory
addresses. In this case, PROM inhibits RAM,
producing the effect of PROM overriding RAM.
After address is stable, local selects are generated
for both the PROM and the RAM. The PROM local
select produces the INHlI signal which then
removes the RAM local select and its driver enable.
Because the slave RAM has been inhibited after it
had already begun its cycle, the PROM XACKI
must be delayed (tXACKB) until after the latest
possible acknowledgement from the RAM
(tXACKA)·

address information on the bus.
Non Bus Vectored Interrupts
N on Bus Vectored Interrupts are those interrupts
whose interrupt vector address is generated by the
bus master and do not require the MULTIBUS
address lines for transfer of the interrupt vector
address. The interrupt vector address is generated
by the interrupt controller on the master and
transferred to the processor over the local bus. The
source of the interrupt can be on the master module
or on other bus modules, in which case the bus
modules use the MULTIBUS interrupt request
lines (INTOI - INT7/) to generate their interrupt
requests to the bus master. When an interrupt
request line is activated, the bus master performs it
own interrupt operation and processes the inter·
rupt. Figure 6 shows an example of Non Bus
Vectored Interrupt implementation.

Interrupt Operations - The MULTIBUS interrupt lines INTOI - INT71 are used by a MULTIBUS master to receive interrupts from bus slaves,
other bus masters or external logic such as power
fail logic. A bus master may also contain internal
interrupt sources which do not require the bus
interrupt lines to interrupt the master. There are
two interrupt implementation schemes used by
bus interrupts, Non Bus Vectored Interrupts and
Bus Vectored Interrupts. Non Bus Vectored
Interrupts do not convey interrupt vector address
information on the bus. Bus Vectored Interrupts
are interrupts from slave Priority Interrupt Controllers (PICs) which do convey interrupt vector

Bus Vectored Interrupts
Bus Vectored Interrupts (Figure 7) are those interrupts which transfer the interrupt vector address
along the MULTIBUS address lines from the
slave to the bus master using the INTAI command
signal for synchronization.
AEMOVED BY BUS
MASTER COMMAND
TO SLAVE

sUS MASTER

I
INTAI

INTX/

I

MASTER CPU

BUS SLAVE

BUS SLAVE

DATA
BUS

iNTRI

INTERRUPT

INTERRUPT

I,

PROGRAMMABLE INTERRUPT
CONTROLLER

6

5

4

3

2

*4
-

1

J

'--I

1

~

REQUEST
FLlPFLOP

INTERRUPT

~

I---

IORCI

l

-

FROM
MASTER

__ yoe

--

-

-

...

t

IORCI

1

OR

lowe!

f-

R

R
FROM
MASTER

INTERRUPT
REQUEST
FLlPFLOP

1-

OR

lowel

l

/10e
...

-

- - -

-

INTO/

~

INT1!

~

INT2I

HI
+5

f-

~

+5

a.
::>",
o:w
o:z

+5

~

INTJI

~
~

+5

INT7!

Figure 6. Non Bus Vectored Interrupt Implementation

A-IS5

~,:::i

AP-28A
US MASTER

BUS SLAVE

DATA
BUS

INTRI

INTERRUPT
STROBE

I

MASTER CPU

(IORC!

FROM
IAASTER

OR

lowe I)

~

INT

-

I

-t=-

CONTROL.LER

-

INTERRUPT
REQUEST
FLlP-

R

FLOP

~

PROGRAMMABLE INTERRUPT

DATO/·7/

.
.

0-7

7654'210J
PROGRAMMABLE INTERRUPT

L-J-

INTERRUPT ACKNOWLtDGE (INTA/)

.

CONTROLLER
INT

DATO/-l/

-- -

INTERRUPT REQUEST (INTx/)

INTERRUPT CODE (ADRa/· ADRA/)

INTERRUPT VECTOR ADDRESS (DATA BUS)

MUl TIBUS TIMING

INTRI

INTAI

ADR8/A

DATO/-7

'-__--------------~r­
-1

L...._ _ _---I

__________________________ ______
~X~

'_N_TR_X_A_D_D_R_ES_S____

_____________________________________Jx

__J)(~

RESTARTN

__________________________

)(~_________________________

u

XACKI

BUS LOCKI *-----~\

~

/

_ _ _ _.....J

* NON

MUl TIBUS SIGNAL

Figure 7. Bus Vectored Interrupt Logic (With 2 INTAI Timing Diagram)

When an interrupt request from the MULTIBUS
interrupt lines INTOI - INT7 I occurs, the interrupt
control logic on the bus master interrupts its
processor. The processor on the bus master
generates an INTAI command which freezes the
state of the interrupt logic on the MULTIBUS
slaves for priority resolution. The bus master also
locks (retains the bus between bus cycles) the
MULTIBUS control lines to guarantee itself
consecutive bus cycles. After the first INTAI
command, the bus master's interrupt control logic
puts an interrupt code on to the MULTIBUS
address lines ADR81 - ADRA/. The interrupt code
is the address of the highest priority active interrupt request line. At this point in the Bus Vectored

Interrupt procedure, two different sequences could
take place. The difference occurs, because the
MULTI BUS specification can support masters
which generate one additional INTAI (8086
masters) or two additional INTA/s (8080A and
8085 masters).
If the bus master generates one additional INTA/,
this second INTAI causes the bus slave interrupt
control logic to transmit an interrupt vector 8-bit
pointer on the MULTIBUS data lines. The vector
pointer is used by the bus master to determine the
memory address of the interrupt service routine.
If the bus master generates two additional
INTA/s, these two INTAI commands allow the

A-186

AP-28A
highest priority master is then connected to the
priority input (BPRNI) of the next lower priority
master, and so on. Any master generating a bus
request will set its BPROI signal high to the next
lower priority master. Any master seeing a high
signal on its BPRNI line will sets its BPROI line
high, thus passing down priority information to
lower priority masters. In this implementation,
the bus request line (BREQ/) is not used outside of
the individual masters. A limited number of
masters can be accommodated by this technique,
due to gate delays through the daisy chain. Using
the current Intel MULTIBUS controller chip on
the master boards up to 3 masters may be accommodated if a BCLKI period of 100 ns is used. If
more bus masters are required, either BCLKI must
be slowed or a parallel priority technique used.

bus slave to put a two byte interrupt vector address
. on to the MULTIBUS data lines (one byte for each
INTA/). The interrupt vector address is used by
the bus master to service the interrupt.
The MULTIBUS specification provides for only
one type of Bus Vectored Interrupt operation in a
given system. Slave boards which have an 8259
interrupt controller are only capable of 3 INTAI
operation (2 additional INTA/s after the first
INTAI). Slave boards with the 8259A interrupt
controller are capable of either 2 INTAI or 3
INTAI operation. All slave boards in a given
system must operate in the same way (2 INTA/s or
3 INTA/s) if Bus Vectored Interrupts are to be
used. However, the MULTIBUS specification
does provide for Bus Vectored Interrupts and Non
Bus Vectored Interrupts in the same system.

Parallel Priority Technique
In the parallel priority technique, the priority is
resolved in a priority resolution circuit in which
the highest priority BREQI input is encoded with
a priority encoder chip (74148). This coded value is
then decoded with a priority decoder chip (74S138)
to activate the appropriate BPRNI line. The
BPROI lines are not used in the parallel priority
scheme. However, since the MULTIBUS backplane contains a trace from the BPRNI signal of
one card slot to the BPROI signal of the adjacent
lower card slot, the BPROI must be disconnected
from the bus on the board or the backplane trace
must be cut. A practical limit of sixteen masters
can be accommodated using the parallel priority
technique due to physical bus length limitations.
Figure 9 contains the schematic for a typical
parallel resolution network. Note that the parallel
priority resolution network must be externally
supplied.

MULTIBUS Multi-Master Operation - The
MULTIBUS system bus can accommodate several
bus masters on the same system, each one taking
control of the bus as it needs to affect data transfers. The bus masters request bus control through
a bus exchange sequence.
Two bus exchange priority resolution techniques
are discussed, a serial technique and a parallel
technique. Figures 8 and 9 illustrate these two
techniques. The bus exchange operation discussed later is the same for both techniques.
Serial Priority Technique
Serial priority resolution is accomplished with a
daisy chain technique (see Figure 8). The priority
input (BPRN/) of the highest priority master is
tied to ground. The priority output (BPRO/) of the

LOWEST
PRIORITY
MASTER

HIGHEST
PRIORITY
MASTER
BPRN!

Figure 8. Serial Priority Technique

A-187

AP-28A

NO ,
PRIORITY
(HIGHESTI

,,-<

ILOWESTI

SPRN

r<'
BREO;

NO ,
PRIORITY

NO ,
PRIORITY

NO 2
PRIORITY

SPRN/

0----,-

....

BAEO'

1

r-<

---c

SPAN}

BREOI ( ) - - - - -

SPANI

BREOI

p-

BUS
PRIORITY
RESOLVER

,

'I>p------

'--\
p-4

P-- J
2 I>,

3

OTHER
MASTER
OUTPUTS

0

Figure 9. Parallel Priority Technique

MULTIBUS Exchange Operation - A timing
diagram for the MULTIBUS exchange operation
is shown in Figure 10. This implementation
example uses a parallel resolution scheme, however, the timing would be basically the same for
the serial resolution scheme.

for master A are disabled. Master B must take
control of the bus with the next trailing edge of
BCLKI to complete the bus exchange. Master B
takes control by activating BUSYI and enabling
its drivers.
It is possible for master A to retain control of the
bus and prevent master B from getting contro!'
Master A activates the Bus Override (or Bus Lock)
signal which keeps BUSY I active allowing control of the bus to stay with master A. This
guarantees a master consecutive bus cycles for
software or hardware functions which require
exclusive, continuous access to the bus.

In this example, master A has been assigned a
lower priority than master B. The bus exchange
occurs because master Bgenerates a bus request
during a time when master A has control of the
bus.
The exchange process begins when master B
req uires the bus to access some resource such as an
110 or memory module while master A controls the
bus. This internal request is synchronized with
the trailing edge (high to low) of BCLKI to
generate a bus request (BREQ/). The bus priority
resolution circuit changes the BPRNI signal from
active (low) to inactive (high) for master A and
from inactive to active for master B. Master A
must first complete the current bus command if
one is in operation. After master A completes the
command, it sets BUSY I inactive on the next
trailing edge ofBCLK/. This allows the actual bus
exchange to occur, because master A has relinquished control of the bus, and master B has been
granted its BPRN/. During this time, the drivers

A-188

Note that in systems with only a single master it is
necessary to ground the BPRN I pin of the master,
if slave boards are to be accessed. In single board
systems which use a CPU board capable of Bus
Vectored Interrupt operation, the BPRN I pin must
also be grounded.
In a single master system bus transfer efficiency
may be gained if the BUS OVERRIDE signal is
kept active continuously. This permits the master
to maintain control of the bus at all times, therefore sa ving the overhead of the master reacquiring
the bus each time it is needed.
The CBRQI line may be used by a master in
control of the bus to determine if another master

AP-28A

BCLKI

TRANSFER
REOUEST I

(LOW I

BREOI

(LOWI

MASTER A

SPRNI

PRIORITY

RESOLUTION
SHOWN

TRANSFER
REOUEST I

HERE

M.t.STER B

BREDI

1

SPRN!

MASTER B

• NOTE BUS PRIORITY MUST BE RESOLVED
WITHI'N ONE BCLKI PERIOD

ON BUS

BUSY I

HIGH IMPEDENCE
STATE
ADDRESSI

ACTIVE STATE

COMMAND!

ACTIVE

HIGH IMPEDENCE
MASTER A

ORIVER

EXCHANGE
OF BUS
SHOWN
HERE

ENABLE!

HIGH IMPEDENCE
ADDRESSI

HIGH IMPEOENCE
MASTER B

COMMAND!

DRIVER

ENABLEI

Figure 10. Bus Control Exchange Operation

Note that except for the BUS OVERRIDE state, no
single master may keep exclusive control of the
bus. This is true because it is impossible for the
CPU on a master to require continuous access to
the bus. Other lower priority masters will always
be able to gain access to the bus between accesses
of a higher priority master.

requires the bus. If a master cUlTently in control of
the bus sees the CBRQI line inactive, it will
maintain control of the bus between adjacent bus
accesses'. Therefore, when a bus access is required,
the master saves the overhead of reacquiring the
bus. If a current bus master sees the CBRQI line
active, it will then relinquish control of the bus
after the current bus access and will contend for
the bus with the othermaster(s) requiring the bus.
The relative priorities of the masters will deter·
mine which master receives the bus.

Power Fail Considerations - The MULTIBUS
P2 connector signals provide a means of handling
power failures. The circuits required for power

A-189

AP-28A

AC LINE
115 VAC

ACLO

+ 5V Vee

PFINI

PFSNI

MPROI

·1....-100n5 MIN~I(On'MIN

1\\\\\\\\\\\\\\ .

INITI

- I-

14---5mSMIN~1

POWER UP

POWER DOWN

Figure 11. Power Fail Timing Sequence

failure detection and handling are optional and
must be supplied by the user. Figure 11 shows
the timing of a power fail sequence.

a power up routine which resets the latch (PFSR/),
restores the environment, and resumes execution.
Note that INIT/ is activated only after DC power
has risen to the regulated voltage levels and must
stay low for five milliseconds minimum before the
system is allowed to restart. Alternatively, IN IT /
may be held low through an open collector device
by MPRO/.

The power' supply monitors the AC power level.
When power drops below an acceptable value, the
power supply raises ACLO which tells the power
fail logic that a minim um of three milliseconds will
elapse before DC power will (all below regulated
voltage levels. The power fail logic sets a sense
latch (PFSN/) and generates an interrupt (PFIN /)
to the processor so the processor can store its
environment. After a 2.5 millisecond timeout, the
memory protect signal (MPRO/) is asserted by the
power fail logic preventing any memory activity.
As power falls, the memory goes on standby
power. Note that the power fail logic must be
powered from the standby source.

How the power failure equipmentis configured is
left to the system designer. The backup power
source may be batteries located on the memory
boards or more elaborate facilities located offboard. The location of the power- fail logic
determines which MULTI BUS power fail lines are
used. Pins on the P2 connector have been specified
for the power failure functions for use as needed.
To further clarify the location and use ofthe power
fail circuitry, an example of a typical power fail
system block diagram is shown in Figure 12. A
single board computer and a slave memory board
are contained in the system. It is desired to power
the memory circuit elements of the memory board
from auxiliary power. The single board computer
will remain on the main power supply. Toaccomplish this, user supplied. power fail logic and

As the AC line revives, the logic voltage level is
monitored by the power supply. After power has
been at its operating level for one millisecond
minimum, the power supply sets the signal ACLO
low, beginning the restart sequence. First, the
memory protect line (MPRO/) then the initialize
line (INIT/) become inactive. The bus master now
starts runnin.g; The bus master checks the power
fail latch (PFSN/) and, ifitfinds it set, branches to
A-190

AP-28A
DC Requirements - The drive and load characteristics of the bus signals are listed in Appendix
C. The physical locations of the drivers and loads,
as well as the terminating resistor value for each
bus line, are also specified. Appendix D contains
the MULTIBUS power specifications.

MULTIBUS™ Slave Interface
Circuit Elements

* USER

SUPPLIED

Figure 12. Typical Power Fail System Block Diagram

an auxiliary power supply have been included in
the system.
The single board computer is powered from the PI
power lines and accesses the P2 signal lines
PFIN/, PFSNI and PFSRI (only the P2 signal
lines used by a particular functional block are
shown on the block diagram). The PFSRI line is
driven from two sources: a front panel switch and
the single board computer. The front panel switch
is used during normal power-up to reset the power
fail sense latch. The single board computer uses
the PFSRI line to reset the latch during a power-up
sequence after a power failure. Current single
board computers must access the PFSNI and
PFSRI signals either directly with dedicated
circuitry and a P2 pin connection or through the
parallelliO lines with a cable connection from the
parallel 110 connector to the P2 connector.

The slave memory board uses both the PI and P2
power lines, the P2 power lines are used (at all
times) to power the memory circuit elements and
other support circuits, the PI power lines power all
other circuitry. In addition, the MPROI line is
input and used to sense when memory contents
should be protected.
The power fail logic contains the power fail sense
latch, and uses the PFSR! and ACLOlines for
inputs and the PFINI PFSN/, and MPROI lines
for outputs. The power fail logic must be powered
by the P2 power lines.

A-191

There are three basic elements of a slave bus
interface: address decoders, bus drivers, and
control signal logic. This section discusses each of
these elements in general terms. A description of a
detailed implementation of a slave interface is
presented in a later section of this application note.

Address Decoding - This logic decodes the
appropriate MULTIBUS address bits into.RAM
requests, ROM requests, or 110 selects. Care must
be taken in the design of the address decode logic
to ensure flexibility in the selection of base address
assignments. Without this flexibility, restrictions
may be placed upon various system configurations. Ideally, switches and jumper connections
should be associated with the decode logic to
permit field modification of base address assignments.
The initial step in designing the address decode
portion of a MULTIBUS interface is to determine
the required number of unique address locations.
This decision is influenced by the fact that
address decoding is usually done in two stages.
The first stage decodes the base address, producing an enable for the second stage which
generates the actual device selects for the user
logic. A convenient implementation of this two
stage decoding scheme utilizes a pair of decoders
driven by the high order bits of the address for the
first stage and a second decoder for the low order
bits of the address bus. This technique forces the
number of unique address locations to be a power
of two, based at the address decoded by the first
stage. Consider the scheme illustrated in Figure
13.

As shown in Figure 13, the address bits A4 - ABare
used to produce switch selected outputs of the first
stage of decoding. The 1 out of 8 binary decoders

AP-28A

have been used. The top decoder decodes address
lines A4 . A 7, and the bottom decoder decodes
address lines A8' A B. If only address lines AO' A 7
are being used for device selection, as in the case of
I/O port selection in 8-bit systems, the bottom
decoder may be disabled by setting switch S2 to the
ground position. Address lines A7 and A B drive
enable inputs E2 or E3 of the decoders. The
address lines AO - A3 enter the second stage
address decoder to produce 8 user device selects.
The second stage decoder must firstbe enabled by
an address that corresponds to the switch-selected
base address.

devices are simultaneously selected, and because
the addressing within such a system is restricted
by the extent of the address space occupied by such
a scheme.

Address decoding must be completed before the
arrival of a command. Since the command may
become active within 50 ns after stable address,
the decode logic should be kept simple with a
minimal number of layers of logic. Furthermore,
the timing is extremely critical in systems which
make use of the inhibit lines.

In systems where the user designed logic must
placedata onto the MULTIBUS data lines, threestate drivers are required. These drivers should be
enabled only when a memory read command
(MRDC/) or an I/O read command (IORC/) is
present and the module has been addressed.

A linear or unary select scheme in which no binary
encoding of device address (e.g., address bit AO
selects device 0, address bit Al selects device 1,
etc.) is performed is not recommended because the
scheme offers no protection in case multiple

oso
os,
os,

AD - - - - - - - - - - - - - - - - 1 Ao
AT

Al

A2

A2

A3

E2 E3

-OS3

8205
DECODER

os,
g~5
DS~

Ei

Data Bus Drivers - For user designed logic
which simply receives data from the MULTIBUS
data lines, this portion of the bus interface logic
may only consist of buffers. Buffers are required
to ensure that maximum allowable bus loading is
not exceeded by the user logic.

When both the read and write functions are required, parallel bidirectional bus drivers (e.g., Intel
8226,8287, etc.) are used. A note of caution must be
included for the designer who uses this type of
device. A problem may arise if data hold time
requirements must be satisfied for user logic
following write operations. When bus commands
are used to directly produce both the chip select for
the bidirectional bus driver and a strobe to a latch
in the user logic, removal of that signal may not
provide the. user's latch with adequate data hold
time. Depending on the specifics of the user logic,
this problem may be solved by permanently
enabling the data buffer's receiver circuits and
controlling only the direction of the buffers.

SECOND STAGE USER
DEVICE, SELECTS

Control Signal Logic - The control signal logic
consists of the circuits that forward the I/O and
memory read/write commands to their respective
destinations, provide the bus with a transfer
acknowledge response, and drive the system
interrupt lines.

A4-----~AO

AS

AT

A6
A7

A2
E2.E3

SWITCH

S,

8205
DECODER

Ei

74532

Bus Command Lines

FIRST STAGE BASE
ADDRESS DECODER

Figure 13. TwoSlage Decoding Scheme

The MUL TIBUS information transfer protocol
lines (MRDC/, MWTC/, IORD/. and IOWC/)
should be buffered by devices with very high speed
switching. Because the bus DC requirements
specify that each board may load these lines with
2;0 rnA, Schottky devices are recommended. LS
devices are not recommended due to their poor
noise immunity. The commands should be gated

A-I92

AP-28A

with a signal indicating the base address has been
decoded to generate read and write strobes for the
user logic.

is an 110 interface which will permit a 16-bit
master to perform 8 or 16 bit data transfers. 8-bit
masters may also use the 8/16-bit version of the
design example to perform 8-bit data transfers.

Transfer Acknowledge Generation

The 8-bit version of the design example may be
used by both 8 or 16-bit masters, but will only
perform 8-bit data transfers. It does not contain
the circuitry required to perform 16-bit data
transfers.

The user interface transfer acknowledge genera·
tion logic provides a transfer acknowledge response, XACK/, to notify the bus master that write
data provided by the bus master has been accepted
or that read data it has requested is available on
the MULTIBUS data lines. XACK/ allows the bus
master to conclude its current instruction.

Both the 8/16-bit version and the 8-bit version of
the design example were implemented on an iSBC
905 prototype board. The schematics for each of
the examples are given in Appendices F and G.

Since XACK/ timing requirements depend on both
the CPU of the bus master and characteristics of
the user logic, a circuit is needed which will provide
a range of easily modified acknowledge responses.

Functional/Programming Characteristics

The transfer acknowledge signals must be driven
by three-state drivers which are enabled when the
bus interface is addressed and a command is
present.

This section describes the organization of the
slave interface from two points of view, the
functional point of view and the programming
characteristics. First, the principal functions
performed by the hardware are identified and the
general data flow is illustrated. This point of view
is intended as an introduction to the detailed
description provided in the next section; Theory of
Operation. In the second point of view, the
information needed by a programmer to access the
slave is summarized.

Interrupt Signal Lines
The asynchronous interrupt lines must be driven
by open collector devices with a minimum drive of
16 mA.
In a typical Non Bus Vectored Inte:r;.rupt system,
logic must be provided to assert and latch-up an
interrupt signal. In addition to driving the
MULTIBUS interrupt lines, the latched interrupt
signal would be read by an I/O operation such as
reading the module's status. The interrupt signal
would be cleared by writing to the status register.

Functional Description - The function of this
110 slave is to provide the bus interface logic for
general purpose 110 functions and for two Intel
8255A Parallel Peripheral Interface (PPI) devices.
Eight device selects (port addresses) are available
for general purpose 110 functions. One of these
device select lines is used to read and reset the state
of an interrupt status flip-flop, the other seven
device selects are unused in this design. An
additional eight 110 device port addresses are
used by the two 8255A devices; four 110 port
addresses per 8255A (three 110 port address for
the three parallel ports A, B, and C and the fourth
110 port address for the device control register).

III. MULTIBUSTM SLAVE DESIGN
EXAMPLE

A MULTIBUS slave design example has been
included in this application note to reinforce the
theory previously discussed. The design example
is of general purpose 110 slave interface. This
design example could easily be modified to be used
as a slave memory interface by buffering the
address signals and using the appropriate
MULTIBUS memory commands. In addition, to
help the reader better understand an application
for an 110 slave interface, two Intel 8255A Parallel
Peripheral Interface (PPI) devices are shown connected to the slave interface.

Figure 14 contains a functional block diagram of
the slave design example. This block diagram
shows the fundamental circuit elements of a bus
slave: bidirectional data bus drivers/receivers,
address decoding logic and bus control logic. Also
shown is the address decoding logic for the low
order four bits, the interrupt logic which is selected
by this decoding logic, and the two 8255A devices.

The design example is shown in both 8/16-bit
version and an 8-bit version. The 8/16~bit version
A-193

AP-28A

8

:~i~ -Reserved

(CIRCUIT SIDE)

DESCRIPTION

PIN

MNEMONIC

Signal GND
+5V Battery
Reserved
-5V Battery
Reserved
+ 12V Battery
Power Fail Sense Reset
-12V Battery
Power Fail Sense
Power Fail Interrupt
Signal GND
+15V
-15V
Parity 1
Parity 2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND
5 VB
VCCPP
-5 VB
Reserved
12 VB
Reserved
-12 VB
ACLO
MPRO!
GND
+15V
-15V
HALT!
WAIT!
ALE
Reserved
Reserved
AUX RESET!

Reserved

Notes:
1. PFIN, on slave modules, if possible, should have the option of connecting to INTO! on P1.
2. All undefined pins are reserved for future use.
All Mnemonics © Intel Corporation 1978

A-199

DESCRIPTION
Signal GND
+ 5V Battery
+ 5V Pulsed Power
-5V Battery
+ 12V Battery
-12V Battery
AC Low
Memory Protect
Signal GND
+15V
-15V
Bus Master HALT
Bus Master WAIT ST A TE
Bus Master ALE

Reset switch

AP-28A

APPENDIX B
BUS TIMING SPECIFICATIONS SUMMARY

Parameter

Description

Minimum

Maximum

tBCY

Bus Clock Period

100

D.C.

tBW

Bus Clock Width

0.35 tBCY

0.65 tBCY

Units

ns

tSKEW

BCLK/skew

3

tpD

Standard Bus
Propagation Delay

3

tAS

Address Set-Up Time
(at Slave Board)

50

ns

tDS

Write Data Set·
Up Time

50

ns

tAH

Address Hold Time

50

ns

tDHW

Write Data Hold Time

50

ns

tDXL

Read Data Set
Up Time To XACK

0

ns

tDHR

Read Data Hold Time

0

65

ns

tXAH

Acknowledge Hold
Time

0

65

ns

tXACK

Acknowledge Time

0

tTOUT

ns

tCMD

Command Pulse
Width

100

tTOUT

ns

tiD

Inhibit Delay

0

100
(Recommend

tXACKA

Acknowledge Time of
of an Inhibited Slave

t IAD + 50 ns

tTOUT

tXACKB

Acknowledge Time of
an Inhibiting Slave

1.5

tTOUT

IlS

tlAD

Acknowledge Disable
from Inhibit (An
internal parameter on
an inhibited slave;
used to determine
tXACKA Min.)

0

100
(arbitrary)

ns

tAIZ

Address to Inhibits
High delay

100

ns

tlNTA

INTAI Width

250

ns

tCSEP

Command Separation

100

ns

A-200

ns

< 100 ns)

ns

AP-28A
APPENDIX B (Continued)
BUS TIMING SPECIFICATIONS SUMMARY
Parameter

Description

Maximum

Minimum

Units

tBREQL

IBCLKI to BREQI
Low Delay

0

35

ns

tBREQH

IBCLKI to BREQI
High Delay

0

35

ns

tBPRNS

BPRNI to IBCLKI
Setup Time

22

tBUSY

BUSY I delay
from IBCLKI

0

tBUSYS

BUSY I to IBCLKI
Setup Time

25

tBPRO

IBCLKI to BPROI
(CLK to Priority Out)

0

40

ns

tBPRNO

BPRNI to BPROI
(Priority In to Out)

0

30

ns

tCBRO

IBCLKlto CBRQI
(CLKto Common
Bus Request)

0

60

ns

tCBRQS

CBRQI to IBCLKI
Setup Time

35

tCPM

Central Priority
Module Resolution
Delay (Parallel
Priority)

0

tCCY

C-clock Period

100'

110

ns

tcw

C-clock Width

0.35 tCCY

0.65tCCY

ns

tlNIT

INIT/Width

5

ms

tiN ITS

INIT I to MPROI
Setup Time

100

ns

tpBD

Power Backup
Logic Delay

0

ns
70

ns
ns

ns

tBCy-tBREQ
-2tPD
-tBPRNS
-tSKEW

200

ns

tpFINW

PFINI Width

tMPRO

MPROI Delay

tACLOW

ACLOI Width

tPFSRW

PFSRI Width

2.5
2.0
3.0
100

troUT

.Timeout Delay

5

tDCH

D.C. Power Supply
Hold from ALCOI

3.0

ms

tDCS

D.C. Power Supply
Setup to ACLOI

5

ms

ms

2.5

ms
ms
ns

00

A-201

ms

AP-28A

APPENDIX C
BUS DRIVERS, RECEIVERS, AND TERMINATIONS
Driver 1,3
Bus Signals

location

Type

Termination

Receiver 2,3
location

IOl
IOH
Co
Mlnma Mln"a Maxpf

III

Maxma

IIH

CI
MaxJ,l8 Maxpf

Location

Type

R Units

DATOI-DATFI
(16Iines)

Masters
and Slaves

TRI

16

-2000

300

Masters
and Slaves

-0.8

125

18

1 place

Pullup

22

KQ

ADRO/-ADRB/,

Masters

TRI

16

-2000

300

Slaves

-0.8

125

1S

1 place

Pullup

22

KQ

MRDC/,MWTCI

Masters

TRI

32

-2000

300

Slaves
(Memory;
memorymapped 1/0)

-2

125

18

1 place

Pullup

1

KQ

10RC I ,IOWC I

Masters

TRI

32

-2000

300

Slaves

-2

125

18

1 place

Pull up

1

KQ

Masters

-2

125

1S

1 place

Pullup

510

Q

-2

50

1S

1 place

Pullup

1

KQ

-2

125

18

Motherboard

To +5V
ToGND

220
330

Q
Q

2

50

18

Central

Pullup

1

KQ

Pullup

1

KQ

BHENI
(21 lines)

(1/0)

XACKI

Slaves

TRI

32

-2000

300

INH1/,INH21

Inhibiting
Slaves

OC

16

-

300

Inhibited
Slaves
(RAM, PROM,
ROM, MemoryMapped 1/0)

BClKI

1 place
(Master us)

TTL

48

-3000

300

Master

BREQI

Each
Master

TTL

5

-400

60

Central
Priority
Module

Priority
Module
(not req)
-1.6

50

BPROI

Each
Master

TTL

5

-400

60

Next Master
in Serial
Priority
Chain at
its BPRNI

BPRNI

Parallel:
Central
Priority
Module
Serial:Prev
Masters
BPROI

TTL

5

-400

300

Master

-2

50

BU$Y/, CBRO

All Masters

O.C

32

-

300

All Masters

-2

50

18

(not reql

(not req)

1S

1 place

INITI

Master

O.C

32

-

300

All

-2

50

1S

1 place

Puli"p

22

KQ

CCLKI

1 place

TTL

48

-3000

300

Any

-2

125

18

Motherboard

To +5V
ToGND

220
330

Q
Q

INTAI

Masters

TRI

32

-2000

300

Slaves
(Interrupting
110)

-2

125

18

1 place

Pullup

1

KQ

INTO/-INTlI
(Sllnes)

Slaves

O.C.

16

-

300

Masters

-1.6

40

18

1 place

Pullup

1

KQ

PFSRI

User's Fron
Panel?

TTL

16

-400

300

Slaves,
Masters

-1.6

40

18

1 place

Pullup

1

KQ

PFSNI

Power Back
Up Unit

TTL

16

-400

300

Masters

-1.6

40

16

t place

Pullup

1

KQ

ACLO

Power
Supply

O.C.

16

-400

300

Slaves,
Masters

-1.6

40

18

1 place

Pullup

1

KQ

PFINI

Power BackUp Unit

O.C

16

-400

300

Masters

-1.6

40

18

1 place

Pullup

1

KQ

MPROI

Power BackUp Uni1

TTL

16

-400

300

Slaves
Masters

-1.6

40

18

1 place

Pullup

1

KQ

A·202

AP-28A

APPENDIX C (Continued)
BUS DRIVERS, RECEIVERS, AND TERMINATIONS
Driver 1,3
Bus Signals

Aux Resetl

Location

User's
Front

Type

Termination

Receiver 2,3
IOL
IOH
Co
Minma Mln~a Maxpl

Switch
toGND

-

-

-

Location

Masters

IlL

CI
Maxma Max~8 Maxpl

-2

IIH

50

18

Location

Type

R Units

None

Panel?

Notes:
1. Driver Requirements
10H = High Output Current Drive
IOL = Low Output Current Drive
Co = Capacitance Drive Capability
TRI = 3-State Drive
O.C. = Open Collector Driver
TTL = Totem-pole Driver

2. Receiver Requirements
IIH
IlL
C,

= High Input Current Load
= Low Input Current Load
= Caoacitive Load

3. TTL low state must be 2. -0.5v but ,;, 0.8v at the receivers
TTL high state must be2. 2.Ov but

~

5.5v at the receivers

4. For the iSBC 80/10 and the iSBC 80/10A use only a lK pull-up resistor to +5v for BCLKI and CCLKI termination.

A-203

AP-28A

APPENDIX D

'.

BUS POWER SPECIFICATIONS

Standard (P1)
Analog Power
Ground

+5

Mnemonic

GND

8us Pins

P1 + 1,2, Pl +3,4,
11,12,
5,6,81,
75,76
82,83,
84
85,86

+5V

"

Optional (P2)

-12

+12

+15

-15

+12

+5

-12

~5

+ 12V

-12V

+ 128

-'128

-58

P1 + 79, P2+23,
80
24

P2+25, P2+ 3,4,
26
5,6

P2 + 11,
12

P2 + 15,
16

P2-7,8

+58

Nominal Output Ref.

+5.0V

+ 12.0V

-1'2.0V + 15.0V

-15.0V

+5.0V

+ 12.0V

-12.0V

-5.0V

Tolerance from
Nominal'

Ref.

±5%

±5%

±5%

±3%

±3%

±5%

±5%

±5%

±5%

Ripple
(Pk-Pk)'

Ref.

50 mV

50 mV

50 mV

10 mV

10 mV

50 mV

50 mV

50 mV

50 mV

500 JJ.s

500JJ.s

500 JJ.s

100 JJ.s

100 JJ.s

500 JJ.s

500 JJ.s

500 JJ.s

500 JJ.s

± 10%

±10%

± 10%

± 10%

±10%

±10%

± 10%

±10%

± 10%

Transient
Response
Time'
Transient
Deviation'

'

P1 + 7,8

+15V

-15V

Battery Power Backup

NOTES:
1. Tolerance is worst case, including initial voltage setting line and load effects of power source, temperature drift, and any additional steady

state influences.
2. As measured over any bandwidth not to exceed

a to 500 kHz.

3. As measured from the start 01 a load change to the time an output recovers within ± 0.1 % of final voltage.
4. Measured as the peak deviation from the initial voltage.

A-204

'.

,

AP-28A

APPENDIX E
MECHANICAL SPECIFICATIONS

12.00 to.OOS
0.25 X 45°
2 PLACES

11.500

~

I--

0.25

I

i2·~

/r.-'I
B.l09 0 IA
3 HQl 'S

COMPONENT SIDE

5,950

D>

!O.O05
6,20
5 REF

0.0 GR
T yp

D>

~

D>

-nr

L- ,----.J"
3.080

I

6.767 to.OOS

I

4.570

I-

f

0.55
'-~ 0.390

o. 30

' " CHAMFER All
CONNECTOR EDGES

0.015 ± 0.005
2 PLACES

0.040 X 45°
NOTES:

[j>

BOARD THICKNESS: 0.062

B>

MUL TiBUS CONNECTOR: as-PIN, 0.156 SPACING

EJECTOR TYPE: SCANBE #$203

5.

CDC VFBOl E43DOOAl

BUS DRIVERS AND RECEIVERS SHOULD BE LOCATED AS CLOSE AS POSSIBLE TO
THEIR RESPECTIVE MUL TIBUS PIN CONNECTIONS

VIKING 2VH43/1ANES

G.

BOARD SPACING: 0.6

7.

COMPONENT HEIGHT: 0.4

s.

CLEARANCE ON CONDUCTOR NEAR EDGES: 0,050

AUXILIARY CONNECTOR- eO·PIN, 0.100 SPACING

CDC VPB01B30DOOAl
Tl H311130
AMP PE5·14559

A-205

x 45°

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: NIl"

- -----.
'b7.SSIl..

__ -.:. .__?

tx,lI-D1
liD ¥()i [, <: bias addr>]< CP
TIXI

{SIP}

,,< end addr>.
[,

E Exit

Exits the loader program and returns to ISIS.

N Single Step

Executes one user program instruction.

G Go

Transfers control of the 8086 CPU to the user program
with up to 2 optional breakpoints.

E

N[  1.1*..:;cr>

G«start addr>] [,
[,] J

S Substitute
Memory

Displays/modifies memory locations in byte or word
format.

X Examine/Modify
Register

Displays/modifies 8086 CPU registers.

SIW1

D Display Memory

Displays coMents of a memory block in byte or word
format.

M Move

Moves contents of a memory block.

C Compare

Compares two memory blocks.

D[WII,]

M, < end addr::',

C-,, < cr>

F Find

Searches a memory block for a byte or word constant.

H Hex Arithmetic

Performs hexadecimal addition and subtraction.

I Port Input

Inputs and displays byte or word data from input
port.

o

Outputs byte or word data to output port.

F[W],< end addr>,

H,

IIW],!. ]*, {,]* 

Syntax conventions used in the command structure are as follows:
rAJ

indicates that" A" is optional

[A]* indicates one or more optional iterations of "A"
<8> indicates that "8" is a variable

{AlB}

indicates "A" or

"B"

 indicates a carriage return is entered

Table 3
8086 CPU REGISTERS

Numeric arguments can be expressed as a number, the contents of a register,
or the sum or difference of numbers and register contents. Thus, addresses
and data can be expressed as follows:
addr :: =
expr ::

=

f : J
ll


=
number :: =
digit :: =
register ::

REGISTER NAME
Accumulator

{+ I-}

{+ I-}

Base
Count
Data
Stack Pointer

1



AXIBXICXIDXISPIBPlsllDqCSIDSISSIESPPlfl

Base Pointer
Source Index
Destination Index

l

01112131415161718191AIBICIDIEIF

Numeric fields within arguments are entered as hexadecimal numbers. The
valid range of numerical values is from OOOO-FFFF. Larger numbers may be
entered, but only the last four digits (or two in the case of byte values) are
Significant. Leading zeros may be omitted.

Code Segment

An address argument consists of a segment value and an offset value separated by a colon (:). If a segment value is not specified, the default 'segment
value is the CS register value.

Instruction Pointer

Data Segment

Stack Segment
Extra Segment
Flag

A-21S

ABBREVIATION
AX
BX
CX
DX
SP
BP
SI
DI
CS
DS
SS
ES
IP
Fl

AP-43

ON-BOARD

EPROM
18K bytes)

FFFFFH
{

39

INTR 7

38

INTR 6

98H

37

INTA 5

94 H

MONITOR PROGRAM
FEOOJH

1---------1

AVAILABLE

SOOOH

------ ~~~: - - - - - -

9CH

38

INTA 4

35

INTR 3

8C H

34

INTR 2

88 H

33

INTA 1

84H

32

INTR 0

80 H

90H

8259A PIC
VECTORS

31

:,
,
,
,

ON-BOARD

RAM
132K bytes)

RESERVED
FOR

FUTURE
USE BY
INTEL

leO H
INITIAL USER STACK

130H
MONITOR

DATA
AREA
Interrupt on Overflow

10H

One-Byte Intr Instruction

CH

INTERRUPT

Non-Maskable Intr

8H

VECTORS
0-39

Single Step

4H

Divide by Zero

°H

AOH

OHL------~

_____________________

Figure 5. Memory Map of iSBCTM 86/12 Memory With Monitor Program

Figure 5 contains a memory map of the iSBC
86/12 memory with the monitor program. Note
that the monitor uses the top 8K bytes of memory
for its program code and the first 384 bytes of
memory (locations 0 hex to 17F hex) for monitor
and user stack, data and interrupt vectors. When
the monitor program is reset, the segment registers,
the IP and the flags are set to 0; and the SP is set
to 01C0H allowing 64 bytes for the user's stack. If
64 bytes is not sufficient for the user's application
program, the SP should be set to some other value.
The monitor program sets the single-step, one-byte
instruction trap and non-maskable interrupt vectors
to monitor entry points. The monitor also sets the
8259A Priority Interrupt Controller to fully nested
mode with level 0 at the highest priority and all
interrupts unmasked. The eight interrupt vector
addresses for the 8259A are also set to addresses in
the monitor. User programs may change the 8259A
interrupt vectors to interrupt service routine addresses within the user programs; it is not necessary
for users to program the 8259A chip directly. When
an interrupt occurs, control passes to either the
monitor or directly to user code depending on the
address stored in the vector location. When the
monitor responds to an interrupt, it acknowledges
the interrupt and displays the interrupt level, CS
and IP register values and next instruction byte on

the system console (e.g., 1=3 @ lOO:230F F5).
When a user requests a breakpoint with a "G"
command, the monitor inserts the single byte
instruction trap instructions (INT 3) in the location
where the breakpoint is requested. It is also possible
for the user to code an INT 3 instruction in his
program. When a user coded INT 3 instruction is
executed, the monitor will be re-entered and a line
with the format @:  will be displayed (e.g., @1200:3F02
F5).
Included on the diskette with the Loader program
are two libraries containing 110 routines for the
console. The library files are named SBCIOS.LlB
and SBCIOL.LlB; they contain similar routines.
The routines in SBCIOS.LlB are written to be
called with intrasegment subroutine calls, a PL/M86 module compiled with the "small" control
generates this type of call. The routines in
SBCIOL.LlB are written to be called with intersegment subroutine calls, a PL/M-86 module compiled with either the "medium" or "large" control
generates this type of call.
The console input output routines, CI and CO,
contained in the library should be used when performing character input and output on the console.
Example PL/M-86 calls to the two routines are:

A-2l9

AP-43
monitor PROMs only decode 16 address bits.
Memory expansion above 64K bytes in these
systems is difficult since the boards which decode only 16 bits will force "holes" in the
address space above 64K.

CI: PROCEDURE BYTE EXTERNAL;
END CI;
CO: PROCEDURE (X) EXTERNAL;
DECLARE X BYTE;
END CO;

3. The iSBC 86/12 board is delivered with two
inputs to the 8259A Priority Interrupt Controller
connected. Interrupt request 2 (IR2) is connected
to the counter ~ output of the 8253 Programmable Interval Timer. IR5 is connected to the
INT5/signal of the MULTI BUS System Bus. If
these interrupts are not desired, the wire wrap
jumpers making the connections should be removed from the iSBC 86/12 board. A particular
problem may exist with the counter ~ connection
to IR2. If the 8253 counter ~ is not specifically
initialized with software, a low frequency square
wave output will exist at counter ~'s output. This
may cause unwanted interrupts when interrupts
are enabled by user programs.

DECLARE INPUT$CHAR,
OUTPUT$CHAR BYTE;

INPUT$CHAR

= CI;

CALL CO(OUTPUT$CHAR);

4. If the iSBC 86/12 board is used in a system with
expansion boards, it is important that the MULTIBUS bus exchange pins be properly jumpered.
For example, if the iSBC 86/12 board is used
with an iSBC 032 expansion memory board in a
system, the BPRN / MULTIBUS pin for the
iSBC 86/12 board should be grounded.

General Comments on Use of the iSBC 957 Package
1. If the iSBC 86/12 board is reset any time after
the initial baud rate search, it is not necessary to
reload the iSBC 957 Loader program or to
download the program code a second time to the
iSBC 86/12 board. It is only necessary to reestablish the communications link by typing two
"U"s for the baud rate search.

In addition, if any interrupts are used with the
iSBC 86/12 board the BPRN/ pin must be
grounded. This is true in both single and multiple board systems.

2. The iSBC 86/12 board should not be plugged
into an available card slot in an Intellec chassis;
a separate chassis should be used. There are at
least three reasons for this:

5. Certain user systems require more than one single
board computer in the system for performing the
functions required by the application. The MULTIBUS System Bus has been specifically designed
to permit multiple CPU boards to communicate
and to share system resources. However, debugging systems with multiple CPUs has always
posed somewhat of a problem. The iSBC 957
package provides a solution to this problem. The
serial cable which connects the iSBC 86/12
board to the Intellec system may be removed
after the program has been downloaded to the
iSBC 86/12 board. A console CRT may then be
connected directly to the iSBC 86/ 12 board and
the monitor program may be used to debug the
program running on the board. Other iSBC
86/12 boards may also be downloaded from the
Intellec system and then switched to their own
local terminals. An 8-bit processor board, such
as the iSBC 80/30 board, may also be included

a. There is only one RESET signal available on
the Intellec system bus. Thus, each processor
may not be reset independently. This means
that the iSBC 86/12 board cannot be reset
without re-booting the ISIS-II operating system and restarting the iSBC 957 Loader.
b. The Intellec system uses five of the eight available interrupts on the system bus. This severely
restricts the range of interrupts available to
the iSBC 86/12 board. Also, the iSBC 86/12
board cannot turn-off the interrupt lamps on
the Intellec front panel.
c. The iSBC 86/12 board may address up to 1
Megabyte of memory using a 20 bit address.
Many Intellec systems contain boards which
generate and decode only the low order 16
address bits. For example, the iSBC 016 memory expansion board and the Intellec 800

A-220

AP-43
in the system and ICE-85™ may be used for
debugging the iSBC 80/30 program concurrently
with the iSBC 86/12 programs. Using this
scheme, it is possible to debug a system which
has several CPU boards by setting breakpoints
and using other debugging features on each of
the individual CPUs.

Initialize
X$RQW & Y$AQW
Matrices

V. MATRIX MULTIPLICATION EXAMPLE
To illustrate how the iSBC 957 package can be used
to assist in the writing and debugging of 8086 programs on the iSBC 86/12 board, an example program of a matrix mUltiplication will be presented.
The example chosen has been intentionally kept
simple and straightforward. The emphasis of this
section will be to document the steps required to assemble, compile, link, locate and debug software
using an Intellec system, the iSBC 957 package and
the iSBC 86/12 board. Part of the example will be
written in 8086 assembly language and part in PLI
M-86.

Multiply
Matrices,
store result in

Z$AOW

Output MAX
value on

The main program is written in PLlM-86. The
main program first performs some initialization
and the matrix multiplication, then the program
calls an assembly language procedure (subroutine),
a PL/M-86 procedure and the console output procedure CO supplied in the 110 library on the iSBC
957 diskette. A flow diagram for the example
program is shown in Figure 6.

terminal using
CO routine

Figure 6.
Flow Diagram of Matrix Multiplication Example

Explanation of the Program Code
Much of the description given below assumes that
the reader is familiar with the PL/M-86 language
and compiler, the 8086 assembler, and the link and
locate program QRL86. It is recommended that the
reader have at least a cursory knowledge of these
subjects. The Intel literature for these subjects is
listed near the front of this application note.

The program code is contained in three software
modules EXECUTlON$VEHICLE, FIND, and
SBCCO. EXECUTlON$VEHICLE contains the
main program coded in PL/M-86 and the binary
to ASCII conversion procedure BlN$DEC$ASC
also coded in PL/M-86. The module FIND contains the assembly language procedure FIND$MX
which searches a matrix for its maximum value.
The module SBCCO resides in the library of console 110 routines supplied with the iSBC 957 package. The procedure CO will be used from this
library.
The program code for the EXECUTION$VEHICLE
and FIND modules will be explained in the following paragraphs. Appendix B contains compilation
and assembly listings for the two modules; also
contained in Appendix B is a memory and debug
map for the linked modules. The listings contain
circled reference letters (e.g.,@) which are referred
to by the code description below. The listings in the
appendix have been printed on fold-out pages so
that they may easily be seen when reading the text.

The EXECUTION$VEHICLE Module

® The first section of the module includes introductory comments and then statements to declare the matrices, other variables, and procedures used in the program. Note that the
matrix dimensions are declared using the literals
M, N, and P which are initially set to 6, 5, and
3. Later in this note, other values for M N
' ,
and P will be used.

® The next

section of code contains the statements which initialize the two matrices that will
be multiplied X$ROW and Y$ROW.
As a result of this initialization, the two matrices will contain values as shown in Figure 7.

A-221

AP-43

0

0

2

4

4

[~ ']
-1

0

2

4

X$ROW (6X5)

-1

-2

-1

-2

-1

-2

-1

-2

® The maximum value is then converted to a six

®

Y$ROW (5X3)

Figure 7.
X$ROW and Y$ROW Matrices After Initialization

© The next program section performs the matrix
multiplication. The algorithm required to multiply two matrices X and Y, storing the result in
a third matrix Z is:
n

Zmp =

L

@

Xmi *Yip

i = I
Assuming X to be 6X5 matrix and Y a 5X3
matrix then

ZII =X Il Y11 +X 1'Y'l +X n Y31 +X14 X.l +X1'YS1
Thus, the upper left term is equal to the sum of
the products of the top row of the X matrix
times the left column of the Y matrix. The result that is obtained by multiplying the two
matrices X$ROW and Y$ROW after they are
initialized as explained above, is shown in
Figure 8.

-5

-10

-10

-20

-15

-30

-20

-40

-25

-50

(6) digit ASCII character string by the procedure BIN$DEC$ASC. The character string is
stored in the array MAX$ASC$ARRAY, which
contains the sign of the number and five (5)
digits for the magnitude.
Finally, the characters "MAX VALUE =" are
output on the system console followed by the
6 ASCII characters containing the maximum
value. The PL/M-86 built-in procedure SIZE
returns the number of bytes of the array TEXT
as a word value. The PL/M-86 built-in procedure SIGNED changes the type of the value
from WORD to INTEGER. This is required so
that the type of the arguments in the DO statement agree. The console output procedure CO
is used to output the characters on the system
console.
Also contained in the module MATRIX.PLM
is the binary to ASCII conversion procedure
BIN$DEC$ASC. The first portion of the code
contains the comments explaining the parl:!meters and the calling sequence followed by the
declarations. Note that the address of the array
where the characters are to be stored is passed
to the procedure and that the characters will be
stored in the array using based variables. The
next section of the code stores either a + or sign in the first character position of the ASCII
array and stores the absolute value of VALUE
in the variable TEMP. Finally, the binary value
is converted to ASCII using the algorithm
explained in the comments. The MOD operator
returns the remainder of the division by 10. The
UNSIGN built-in procedure is required to
change the type of the expression from INTEGER to WORD.

The FIND Module

® The FIND module contains the assembly lan-

guage procedure FINDMX. The calling sequence and the parameters are explained in the
comments at the beginning of the listing. Note
that the label FINDMX has been declared
PUBLIC so the link program can fill in its
address in the CALL statement in the main
program of module EXECUTION$VEHICLE.
The FIND module will contain three segments:
a data segment, a stack segment and a code
segment. It will be both convenient and pragmatic to append these three segments to the
code, data and stack segments created by the

Z$ROW (6X3)
Figure 8. Result of Multiplying the Initialized Matrices
X$ROW and Y$ROW

® The

external assembly language procedure
FIND$MX is called to determine the maximum
value in the matrix. The procedure is a typed
procedure and returns the maximum value to
the calling program which stores it in the integer variable MAX.

A-222

AP-43
since it is desired that the code from this
module be appended directly to the code from
other modules without gaps between the code
modules.
The assembly language code follows next. The
code for the procedure must be enclosed between a pair of PROC, ENDP statements. The
PROC statement is given the label FINDMX
and specified as a NEAR procedure indicating
it will be called with a near (intra-segment)
CALL instruction and not a far (inter-segment)
CALL instruction.

compiler for the EXECUTION$VEHICLE
module. To accomplish this, the three segments
must be given the same SEGMENT and CLASS
names as those given these segments by the
compiler. The SEGMENT and CLASS names
used by the compiler are CODE, DATA, and
STACK. The GROUP statements are used to
place the segments DATA and STACK in the
group DGROUP and the segment CODE in the
group CGROUP. These group definitions conform with the group definitions generated by
the PL/M-86 compiler when the SMALL size
control option is used. A group is a collection
of segments which requires less than 64K bytes
of memory.

The comments at the beginning of the module
and adjacent to the program statements explain the function being performed by the
assembly language code.

The ASSUME directive informs the assembler
that the DS and SS registers will contain the
base address of DGROUP and the CS register
will contain the base address of CGROUP.
This information will be used by the assembler
when constructing machine instructions.

The SBCCO Module

@ The console output procedure CO is contained
in the object module SBCCO of the library file
SBCIOS.LIB. SBCIOS.LIB is part of the iSBC
957 package 110 libraries. The calling sequence
and parameters for CO may be seen in the
external procedure declaration in the EXECUTION$VEHICLE module.

first segment appearing in the module is
CD The
the data segment. The order of the segments is
arbitrary, although it is recommended that the
data segment precede the code segment to minimize forward references to variables which may
cause the assembler to generate longer instruction codes. The data segment is declared
PUBLIC, aligned on a WORD boundary and
given both a segment and class name of DATA.
Then follows the contents of the segment. In
this particular example, only one word of storage is required. The ENDS directive indicates
the end of the segment.

Compiling the EXECUTION$VEHICLE
Module
The EXECUTION$VEHICLE module is stored on
a file named MATRIX.PLM on disk device :Fl:.
To compile the module, the following command
line is used:
- PLM86 :FI :MATRIX.PLM DEBUG
This command line will cause the module stored in
the file :Fl:MATRIX.PLM to be compiled. The
object code generated will be stored in a file with
the default name :Fl:MATRIX.OBJ and the listing
generated will be stored in a file with the default
name :Fl:MATRIX.LST. To override the default
object and listing files, the NOOBJECT and NOLIST compiler control switches can be used. File
names for the listing and object files may also be
specified in the command line. The DEBUG compiler control switch causes the compiler to generate
extra symbol and line number information which
will be used during debugging of the program. A
listing of the compiled EXECUTION$VEHICLE
module is contained in Appendix B.

® Next comes the stack segment which is given
the segment name of STACK, the combinetype attribute of STACK and the class name of
STACK. The combine-type attribute of STACK
assures that the stack storage required in this
module will be appended to the storage required in the PL/M-86 compiled modules. Two
bytes of stack are required by the code in this
module, however, the monitor uses 13 words of
stack when breakpoints and interrupts are used.
Therefore, 14 words are reserved for the stack.
Finally comes the code segment. The code segment has been given a segment name and class
name of CODE and a group name of
CGROUP, and has been declared PUBLIC.
The alignment attribute of BYTE is specified

To aid in the debugging of the program, the
module was compiled a second time with the following command line:

A-223

AP-43
- PLM86 :Fl:MATRIX.PLM NOOBJECT
CODE DEBUG PRINT (:Fl :MATRIXXLS)
This command line specified that no object file is to
be created and a listing file should be stored in the
file :FI :MATRIXXLS. The CODE compiler control switch causes the compiler to list the assembly
language statements which the compiler has generated for each line of PL/M code. The listing stored
in the file MATRIXXLS is contained in Appendix

C.
Assembly of the FIND Module
The assembly language module FIND is stored on a
file named FIND.ASM, to assemble this module
the following command line is used:
ASM86 :Fl:FIND.ASM DEBUG
This command line will cause the FIND module to
be assembled with the object code stored in the
default file :FI :FIND.OBJ and the listing stored in
the default file :FI:FIND.LST. The listing of the
assembled FIND module is contained in Appendix

B.
Linking and Locating the Object Module
To link and locate the object modules, the QRL86
program will be used. The QRL86 program performs both the linking and the locating of the
object modules in a single step. QRL86 is primarily
designed for the debugging stages of program development. Some applications may require the extended
capabilities of the separate LINK and LOCATE
programs when the final link and locate is performed. The command line used to invoke the
QRL86 program is:
QRL86 :FI:MATRIX.OBJ, :Fl:FIND.OBJ,
SBCIOS.LIB ORIGIN (lOOOH)

for the program is specified as (~I~H, ~2H)
indicating a CS value of ~1~H and an IP
value of ~2H or an absolute value of ~1~2H.
The first two bytes of the code segment contain
address values which the code generated by the
compiler will use for setting up the DS and SS
registers. The memory map shows the code
segments from the three modules collected into
the group CGROUP. The code segment from
the EXECUTION$VEHICLE module is given
the segment and class names of CODE and is
put into CGROUP by the PL/M compiler. To
assure that the code segment from the FIND
module is concatenated with the code segment
from the EXECUTION$VEHICLE module the
identical class, segment and group names were
specified in the SEGMENT and GROUP statements in the FIND module. Next, the group
DGROUP is shown in the memory map.
DGROUP contains 4 segments labelled
CONST, DATA, STACK and MEMORY.
Putting all of these segments in the same group
tells the linker that they will all be in the same
64K block of memory. The SMALL size control option of the compiler, which was invoked
by default, creates CGROUP, DGROUP, and
the segments contained in them.
The debug map contains the memory address
of variables, instruction labels and the addresses of each code line of the PL/M-86
module. Notice that the variable storage labels
have their addresses specified in the format (DS
register value, displacement). For example, the
variable TEMP has an address of DS=~12AH,
displacement = ~CH or an absolute address
of f)136H. Instruction labels and line numbers
use the format (CS register value, IP register
value). Thus, line number six (6) in the module
EXECUTION$VEHICLE has the address
CS=~I~H, IP=~B5H or ~IIB5H.
Object to Hex Conversion

®

This command line will cause QRL86 to link the
code from the three modules and to locate the
resultant absolute object module starting at location
1000 hexadecimal. The iSBC 86/12 monitor uses
the first 180H bytes of memory for the monitor
stack, data and interrupt vectors, l000H was chosen
as a convenient starting address for the program.
The absolute object code will be stored in a default
file :Fl :MATRIX (note no file name extension is
used). By default, the memory and debug maps
which are generated are stored in the file :Fl:MATRIX.MPQ and are contained in Appendix B.

® The

memory map contains the starting addresses and sizes of the CODE, CONST,
DATA, STACK and MEMORY segments of
the object module. Note that the start address

A-224

Before downloading the program to the iSBC 86/12,
the format of the object module must be converted
from the absolute object module format which
QRL86 creates to a hexadecimall ASCII representation of the object module. This is done using the program OH86 with the following command line:
OH86 :Fl:MATRIX TO :FI:MATRIX.HEX
Downloading and Debugging the Program
The hardware configuration used for debugging the
matrix multiplication example program code was

AP-43
an Intellec Series II Model 230 development system, the iSBC 957 package, an iSBC 86/12 board,
and an iSBC 660 system chassis. What follows is
the system-user dialog for a typical debugging
session.
The first step required is to bootstrap load the
ISIS-II operating system by hitting the RESET
switch of the Intellec. The Intellec resident loader
software is then loaded and executed. Throughout
the dialog which follows operator entered characters will be underlined:

.00.100
0000 2A 01
0010 c7 06
0020 00 C7
0030 22 00
IHIU E6 89

FA
8E
06
88
C3

2E
00
90
06
8a

8E
00
00
8E
0E

16
00
00
00
8E

00
81
00
89
00

00
3E
81
0A
89

Be
BE
3E
01:l
88

00
00
90
F7
HI

00
05
00
E9
00

88 Ee 16 IF
~Hl 7E 03 E9
04 00 7E 03
BB 36 90 00
81 06 90 00

FB
3C
E9
Dl
01

"0Sd 00 E9 03 FF ill 06 8E 00 01 00 E9 89 FF e7 1116 8E

0060 00 00 00 81 3E 8E 00 04 00 7E 03 E9 40 00 C7 06
0070 90 00 00 ~13 81 3E 90 0~ 02 00 7E 03 E9 26 013 Be
1.:'080 06 90 00 F7 08 50 8s 06 BE 00 s9 06 00 F7 E9 8s

0090 36 90 00 Dl E6 89 C3 59 89 88 4C 00 Bl 06 90 00
00A.0 01 00 E9 CF FF Bl 06 BE 00 01 00 E9 B5 FF C7 06
"080 92 00 00 00 81 3E 92 00 '112 00 7E 03 E9 Be 00 C7

00C0 06 8E 00 00 00 Bl 3E 8E 00 05 00 7E 03 E9 72 00
00D0 Be 06 BE 'HI 89 06 00 F7 E9 8e 36 92 00 01 E6 89
00E0 e3 C7 80 6A. 00 0111 00 C7 06 90 00 !!I0 00 81 3E 90
00F0 00 04 00 7E 1113 E9 41 00 BB 06 BE U 89 0A. 00 F7

0100 E9

ISIS-II, 113.4
-~

ISIS-II ISBC 86/12 LOADER, 111.2

To initialize the iSBC 86/12 monitor, the user must
hit the RESET switch on the iSBC 660 chassis and
type two "U"s on the system console. The monitor
program will output a line on the console when it is
properly initialized.
ISBC 86/12 MONITOR, V1.2

The monitor command "X" is typed to check that
the monitor is properly operating and to examine
the contents of the 8086 registers .

The PL/M-86 compiler ends the main program in
the EXECUTION$VEHICLE module with a halt
instruction. After execution of the program it is
more desirable to return to the monitor. To accomplish this, an INT 3 instruction (code=CC)
will be substituted for the halt instruction (code=
F4) at the address of 1B4H relative to a CS value
of l00H. First the "0" command is used to verify
the address of the halt instruction, then the "S"
command is used to change the instruction to an
INT 3 instruction.
. ruM
01B4 F4
.~

•X

AX"'00"" BX"'~000 CX=IHHJ0 DX=0000 SP='HCIIl SF=00"" 81=0000
!)I::00~~ C5=001:10 DS=000~ 55::::0000 85=0000 IP=00"0 FL=0000

To download the hex object file to the iSBC
86/12, the "L" command is used. Because an
Intellec Series II Model 230 is being used, a serial
download is specified. The hex file name is
MATRIX. HEX which is resident on disk device
:Fl:.
.f.S, : FI: MA·rRIX. HEX

The "X" command is used again to examine the
CPU registers. Note that the monitor has changed
the contents of the CS and IP registers to the value
of the starting address of the program.

F4- ~

To execute the PL/M-86 main program, the "G"
command is used. After the "G" is typed, the
current contents of the IP are output, followed by
the contents of the byte pointed to by the IP. A
new value for the IP or breakpoint addresses may
be specified before a carriage return  is typed.
In this example, only a  is typed.
.9. 0002- FA.
MAX V<\LUE = -00050
@"Hl0:0185 55

The program executes and outputs the maximum
value of the matrix calculated. The INT 3 instruction is executed which causes a return to the
monitor. The monitor types out an at-sign (@)
followed by the CS and IP register values and the
first byte of the instruction following the INT 3
instruction.
The "X" command is typed to examine the CPU
registers. Note that the program has set both the SS
and OS registers to ~12A. (~12A~H is the address
of the OGROUP as shown in the memory map.)

.X
AX=0000 BX={:trd0B CX='HHHl DX='H"'" SP"'01C0 B~=0000 51=0000
01=0000 CS=0HHt DS=0~"0 55=000" Es=rU00 IP:::111002 FL=0000

The "0" command is next used to display the first
101 bytes of the program code. Unless another segment register is specified, the display command
assumes all addresses specified are relative to the CS
register. Thus, the code displayed will be from absolute addresses 1000 through 1100. The program code
displayed may be compared with program code generated by the PLlM-86 compiler shown in Appendix
C, code line 36.

.X
A.X"'~030 BX=0005 eX=1!I00A. OX=0000 SP=0000 BP=U100 Sl=0001
01=00'116 CS=0100 OS=012A. SS=IU2A ES=QU"00 IP=01B5 FL"'F202

The three matrices are displayed. Note that a word

A-225

AP-43
display has been specified by using the "OW"
Command and that the addresses have been specified relative to the OS register. The addresses of
X$ROW, Y$ROW, and Z$ROW may be found in
the debug map given by QRL86. Note that the
values stored in the matrices are the same as those
shown in Figures 8 and 9.
.DW
BBl0
BB20
8BlB
8040

OS.10.4A
011iB B00B
0BU 0Bn
0B0l BBBl
BB04 0005
.ow OS;4C.68
004C 0000 FFFF
0850 FFFE 0B~0
0060 FFFF FFFE
.OW OS.6A.BC
~06A 08B0 8~00
8070 0000 FFFS
~0B0 FFE2 0000

sequence is terminated.
i'V'm~ em-,
ealE 1101.~

BBSC

:m ::::: iJ

After the matrices are modified, execution is
resumed with the "G" command. The max value is
output and the INT 3 instruction executed. Finally,
the contents of the 3 matrices are displayed.

BBB~ B~B0 0080 BBn 0001 0~Bl

0002 0002 0BB2 B002 00B2 BBBl
U0l 0~~l 00B4 ee04 0004 0004
00B5 0005 08B5 0005
FFFF FFFE 0008 FFFF FFFE
~000 FFFF FFFE

.li 0ICB- 7E
MAX VALUE' +00400
U100.llB5 55
• OW os. 10 .BC
0010 0000 0000 0000
0~2B 0001 00U 0eB2
0010 ae~l 000l ~eBl
004~ 0eB4 eB05 0005
0050 FFFE 800B FFFF
0060 U64 FFFE sue
0070 0800 0051 FFOB
00BB FFE2 0000 01B8

000~

00~0

FFF6 ~~0~ FFF6 FFEC 0008 FFFl
FFEC FFOB 0000 FFE7 FFCE

The "G" Command is used to reset the IP register
to the start address of the program (f/1Ij2) and to
specify a breakpoint at address ~AEH, which is the
address of statement 57 of the main program.
Statement 57 is the point in the program after the
X$ROW and Y$ROW matrices have been initialized, but before the matrix multiplication is
performed. After the <:CR> is typed, the program
executes until the breakpoint is encountered. At
this point, the monitor outputs a line specifying
the number of the breakpoint, the CS and IP
values and the first byte of the next instruction to
be executed.

Next, the single-step capability is used with the
"N" command to execute single instructions. At
any time, CPU registers may be examined or
changed. In this example, the "X" command is
used. Execution of succeeding instructions is caused
by typing a comma (,).
C7
Bl ,

..I.

00BF- C7 -

.!
AX"'UI18 BX=0018 CX=FFFE DX='HHHl Sp:c:00D0 8P=00D0 SI=rtHd04
01=0006 CS::0U0 DS=012A SS::012A ES=IiHHI" IP=00BF FL=F293

c:

0010
00Sl
B0U
FFFF
B000
0U0
0120

The extra memory requirements will be supplied
by using an iSBC 032 board with the iSBC 86/12
board in the iSBC 660 chassis. The iSBC 032 board
is a 32K byte RAM board which is compatible
with both 8- and 16-bit CPU boards. The base
address of the board may be selected anywhere in
a 0 to I megabyte range on any 16K byte boundary.
8- or 16-bit data transfers may be selected. The
iSBC 032 board will be jumpered to respond to
addresses in the 512K or 544K address space (20
bit hex address range to 8~H to 87FFFH). This
will illustrate the capabilities of the 8086 to access
a 20-bit, I megabyte address range.
One other modification is required to the program.
The magnitude of the numbers which would result
from multiplying matrices of this size would greatly exceed the capacity of the 16-bit integer storage,
even with the two matrices initialized to the small

00BA- 7E -;

'~0~~~F~1

0000 0001 0101
~102 00'02 B0e2
0~04 0·884 0004
0005 0005 0000
B000 FFFF FFFE
FFFE 0I!l00 0o""
0BCB FFEC 0000
0B00 01E0 FFCE

To illustrate how the iSBC 86/12 board may be
used for executing 8086 programs which require
large amounts of RAM, the example program will
be modified. The matrix dimensions of the example
will be changed from values of 6, 5 and 3 for the
literal symbols of M, N, and P to values of 100,
50, 70. The three matrices will then be of size
lOOX50, 50X70, and lOOX70. The memory required for these matrices is 15.5K words or 31K
bytes. The data, constant, stack and memory
segments which are contained in the group
OGROUP will now comprise almost 32K bytes of
memory.

.§ 01S5- 55 tH'2,AE

.~ ~"U\E-

0000
eB02
eB0l
Bee5
FFFE
FFFF
0000
FFOB

Expanding the Example Program's
Memory Requirements

BRI @0100:00AE C7

0~s4-

it

"P!- ,FPFF-,

.!

00C8- 7E-

The contents of the X$ROW and Y$ROW matrices
are examined and changed with the "SW" (substitute word) command. If a comma (,) is typed
after the contents of memory are displayed, then
the contents are left unchanged and the next word
of memory is displayed. If a value followed by a
comma or  is entered, then the contents are
changed. If a  is entered, the substitute

A-226

AP-43
The object code is then converted to hex format
and downloaded to the iSBC 86/12 board. When
the program is executed, the maximum value is
calculated and output on the console.

values they presently contain. To keep the example
simple, the initialization values will be changed so
all elements of the X$ROW matrix are set equal to
2 and all elements of the Y$ROW matrix are set
equal to 3. The result of the multiplication should
make all the elements of Z$ROW equal to 300.

-saC661
ISIS-II ISBC 86/12 LOADER, Vl.2

The modified lines of program code are shown
below.

Isse 86/12 MONITOR" Vl. 2
• LS,: FI :MA.TRI'i. HEX

:~~%i2:4;~ ~

/* MATRIX DIMENSIONS, *;
27
28
29

DECLA.RE M LITERALLY '100 I I

36

DO I •

37
38
39
40

DOJ-BTO(N-l),
X$ROW(I).COL(J) END,
END;

41
42
43
44

DO I • 0 TO (N-l),
DO J . B TO (P-l),
Y$ROW(I).COL(J) •
END;
END,

MAX VA.LUE • +00300
@eI01!l:01AD 55

DECLARE N LITERALLY '521',
DECLARE P LITERALLY 170';

45

~

TO (M-l),

VI. CONCLUSION

2,

This application note has described the iSBC 957
Intellec-iSBC 86/12 Interface and Execution
Package, and how this package may be used to
develop and debug programs for the 8086 processor.
First, the iSBC 86/12 single board computer was
described, followed by a detailed description of the
iSBC 957 package and the iSBC 86/12 system
monitor commands. The power and versatility of
the iSBC 957 package and monitor commands for
developing and debugging programs for the 8086
were illustrated by a program example: In the
example a program which consisted of PL/M-86
and assembly language routines was presented. The
program code was explained, and the steps required
to compile, assemble, link, locate, and debug the
program were illustrated. Finally, a typical debugging session using the iSBC 86/12 system monitor which illustrates the powerful capabilities of the
monitor was presented.

3,

The EXECUTION$VEHICLE module must be recompiled and then the three program modules must
be linked and located using the QRL86 program.
Specifying the SEGMENTS option of QRL86, the
origin of the CODE segment which is in the group
CGROUP is set at l000H, as in the first example.
However, the origin of the CONST, DATA
STACK and MEMORY segments which make up
the group DGROUP is set at 80000H.
QRL86 :Fl :MATRIX.OBJ, :Fl :FIND.OBJ,
SBCIOS.LIB SEGMENTS (CODE(I000H),
CONST (80000H), DATA STACK, MEMORY)
The memory map generated by QRL86 shows the
CGROUP having a start address of 01000H and
the DGROUP having a start address of 80000H.
INVOKED BY:
QRL86 :Fl:M,I'I,:rRIY.OBJ,:Fl:FINO.OBJ,SBCIOS.LI8 &
SEGMENTS (CODE (100~H) ,CONST (8000f.:lH) , DATA, STACK, MEMORY)

INPUT MODULES INCLUDED:
: Fl: MAT~n" .OBJ (EXECUTIONVEHICLE)

: F 1: FIND. OBJ (FIND)

sec lOS .LIB (sacco)
RESULT WRITTEN TO : Fl: MATRI'f (EXECUTIONVEHICT,E)
START AOORESS IS (Wl100H,0002H)
START

0HJ00H
0Hl00H
0121DH
0125EH

LTH
298H
21DH
41H
3AH

800110H 797i'lH
80000H
CH
8eeeCH
0H
8eetlCH 792AH
87936H
2H
87938H
BH
87940H
30H
BH
8797"H
87971!lH

BH

ALIGN NAME

W

B
W

W

w
w
W
W

sw

W

/GS/ CGROUP
CODE (EXECUTIONVEH I C LE)
CODE (FIND)
CODE (saCCo)
/GE/ CGROUP
/GS/ DGROUP
CONST (EXECUTIONVEHICLE)
CONST (saCCo)
DATA (EXECUTIONVEHICLE)
DATA(FIND)
DATA(SBCCO)
STACK
MEMORY
/GE/ DGROUP
??SEG (FIND)

CLASS

CODE
CODE
CODE

CONST
CONST
DATA
DATA.
DATA
STACK
MEMORY

(NULL)

A-227

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AP-43
APPENDIX B
PROGRAM LISTINGS FOR EXECUTION$VEHICLE AND FIND MODULES
PL/M-86 COMPILER

EXECUTIONVEHICLE

ISIS-II PL/M-8fi Vl.£! COMPILATION OF MODULE EXECUTIONVEHICLE
OBJECT MODULE PLACED IN :Fl:MATRIX.OBJ
COMPILER INVOKED BY:
PLM86 :Fl:MATRIX.PLM DEBUG

1*

MATRIX MULTIPLICATION EXAMPLE PROGRAM
PL!I'I-86 MAIN PROGRAM WHICH:
A) INITIALIZES TWO INTEGER r-'lATRICES
B) MULTIPLIES THE TWO MATRICES AND STORES THE RESULT IN A

THIRD MATRIX
C)

CALLS AN ASSEMBLY LANGUAGE PROCEDURE WHICH SEARCHES THE.

THIRD MATRIX FOR THE MAXIMUM VALUE
OJ
E)

CALLS A PL/M PROCEDURE WHICH CONVERTS THE MAXIMUM VALUE
FROM INTEGER TO ASCII
CALLS'" PROCEDURE WHICH OUTPUTS THE ASCII CHARACTERS ON
THE SYSTEM CONSOLE

'j

EXECUTIONSVEHICLE:
DO;

Itt

FIND$"r-1X - EXTERNAL ASSEMBLY LANGUAGE PRdCEI)UR~ WHICH SEARCHES A
MATRIX FOR THE LARGEST ABSOLUTE MAGNITUDE.
PARAMETERS:
MATRIX$!lDR ADDRESS OF THE !-lATRIX TO BE SEARCHED
ROWS - NUMBER OF ROItI'S IN THE MATRIX
COLS - NUMBER OF COLUMNS IN THE MATRIX

'j

FTND$MX: PROCEDURE (MATRIX$PTR,
DECLARE (ROWS, COLS) INTEGER;
DECLARE MATRTX$PTR POINTER;
END FINOSMX;

/*

ROWS,

COLS)

INTEGER EXTERNAL,

BINSOECSASC - BINARY TO DFCIMAL ASCII CONVERSION PROCEDURE
PARAMETERS:
VALUE - INTEGER VALUE TO 8E CONVERTED TO ASCII
CHARSARRlIY$ADR - ADDRESS OF 6 BYTE ARRAY WHERE ASCI I
STRING CONTAINING THE VALUE \ow'ILL BE STORED

'j
BINSDEC$ASC:

PROCEDURE

(VALUE, CHARSARRAY$ADR);

DECLARE (VALUE, TEMP, I) INTEGER;
DECLARE CHARSARRAySADR POINTER;
DECLARE (CHARSARRAY BASED CHARSARRAY$ADR)

®
@

BYTE;

22
23

END BINSDEC$ASC;

15
lfi

17
18
19

"

2l

®{

(6)

IF VALUE < r. THEN
DO,
CHAR$ARRAY{!1I) '" ' - ' .
/* SIGN CHARACTER */
TEMP
-VALUE;
END,
ELSE
DO;
\1
CHARSARRAY(IZI) '" '+',
TEMP'" VALUE;
END;
DO J: '" 5 TO 1 BY -1;
CHAR$ARRAY{I) ::: UNSIGN(TEMP MOD un + 30H;
TEMP = TEMP/] 0;
/* ASCII CHARACTERS ~f1 THRU .19 HEX, REPRESENT THE' DIGITS II.' THRU 9. THUS
TO CONVERT AN INTEGER TO ASCI I REPEATED DIVISIONS BY 10 AND ADDING
THE REMATNDER TO 30 HEX WILL ACCOMPLISH THE CONVERSION */
END;

I"
II
12
13
14

/*

CO - EXTERNAL PROCEDURE TO OUTPUT A CHARACTER TO THE SYSTEM CONSOLE.
THIS PROCEDURE IS PART OF -THE ISBC 957 LIBRARY FOR CONSOLE I/O
PARAMETER:
CHAR - ASCII CHARACTER TO BE OUTPUT ON THE CONSOLE

'j

24
25
2fi

CO: PROCEDURE (CHAR)
DECLARE CHAR BYTE;
END CO;

27
28
29

/* MATRIX DIMENSIONS
DECLARE M LITERALLY , 6';
DECLARE N LITERALLY • 5' i
DECLARE P LITERALLY' 3';

EXTERNAL;

*/

/*

31!l
31
32
33
34
35

THE THREE MATRICES ARE DECLARED AS ARRAYS OF STRUCTURES.
XSROW IS COMPOSED
THUS
OF M STRUCTURES EACH OF WHICH IS COMPOSED OF N INTEGER ELEfo'IENTS.
XSROW MAY BE THOUGHT OF AS A M X N MATRIX.
THE MATRIX WILL BE STORED AS
A ROW-ORDER MATRI X WITH THE ELEMENTS OF EACH ROW STORED IN ADJACENT MEMORY
YSROW rs DECLARED AS A N X P MATRIX AND Z$ROW AS A N X P MATRIX
LOC':ATIONS.
DECLARE X$ROW(M) STRUCTURE (COL(N) INTEGER);
DECLARE Y$ROW(N) STRUCTURE (COL (P) INTEGER);
DECLARE Z$ROW(M) STRUCTURE (COL(P) INTEGER);
DE:CLARE (I',J,K,MAX) INTEGER;
DECLARE MAXSASC$ARRAY(fi) BYTE;
DECLARE TEXT (*) BYTe DATA (' MAX VALUE '" .);

A-230

*/

AP-43
/* INITIALIZE X$ROW SUCH THAT THE F'JRST ROW IS SET EQUAL TO 0,
ROW EQUAL TO 1, THE THIRD RO\<' EQUAL TO 2, ETC.
*/
DO I =: ~ TO (M-l);

36
37

DO J "''' TO (N-I),
XSROW(I) .COL(J) ::: I;
END;
END;

'"

'.

39

®

/* INITIALIZE Y$ROW SUCH THAT THE FIRST COLUMN IS SET EQUAL TO 0, THE
SECOND COLUMN EQUAL TO -1, AND THE THIRD COLUMN EQUAL TO -7.
*/
DO I ::: e' TO (N-l);
DO ,J = PI TO (P-l);
YSRDW(I) .(,OL(J) = -J;
END;
END;
/* PERFORM MATRIX MULTIPLICATION */
DO K = ~ TO (P-l)i
DO I = Iil TO (M-I);
Z$RDW{I).COL(I<") = lil;
/* SET Z$RQW ELEMENT TO 0 *1
DO J ::: r TO IN-I); /* SUM THE PROOUCT OF XSROW ROW TERMS AND Y$RCW COLUMN TERMS
Z$RDW(T).COL(K) = ZSRDWrI).COL(K) + (X$RDW(I).COL(J) * Y$ROW(J).COL(K) );
END,
END;
END;

41
4>
43

44
, 5

©{
®{

©
®

THE SECOND

46
47
48

49
5.
5]
52
53
54

MAX", FIND$MX

55

CALL BINSDEC$ASC

50
57
58

DO I
TO (SIGNSD(SIZi::(TEXT))
CALL CO (TEXT r I) ) ;
END;

59
6.
61

DO I '" '" TO 5; /* OUTPUT ASCII MAX VALUE
CALL CO(MAX$ASC$ARRAY (I) ) ;
END;

62

END EXECUTION$VEHICLEj

r€!ZSRO\'i,
(MAX,

M,

P);

/* FIND MAX VALUE OF Z$ROW */

i IABS(MAX) THEN MAX'" MATRIX(I).Y(J);
END;
END;

36
37

WHERE lABS (XYZ)

38
39

A-231

REPRESENTS THE ABSOLUTE VALUE OF THE INTEGER XYZ

AP-43
APPENDIX B
PROGRAM LISTINGS FOR EXECUTION$VEHICLE AND FIND MODULES
LDC

0{
0{
®{

LINE

aBJ

••

DEFINE GROUPS TO CONFORM WITH PL/M-86 CONVENTIONS. DATA, STACK, AND
CODE SEGMENTS WILL BE APPENDED TO THEIR RESPECTIVE SEGMENTS IN THE

41

'2
'3
4.
'5
.6
'7
48
'9
5.
51
52
53
5'
55
56
57
58
59
6'
51
62

0000 0000

0''''0

(I'

0P00

baROUP

PL/M-86 MODULES.
GROUP
DATA, STACK

CGROUP

GROUP

CODE

INSTRUCT THE ASSEMBLER THAT THE OS, SS, AND CS REGISTERS WILL CONTAIN
THE BASE ADDRESS VALUES FOR THE DGROUP, DGROUP AND CGROUP GROUPS.
OS: DGROUP,SS :DGROUP,CS :CGROUP
ASSUME

; ••••••••••••••• DI\TI\ SEGMENT
;
DATA
SEGMENT WORD PUBLIC 'DATA'
MAX
OW
"
DATA
ENDS
;
; ••••••••••••••• STACK
STACK

SEG~ENT

SEGMENT STACK I STACK'
OW
14 OUP (111)

;RESERVE 13 WORDS OF STACK FOR MONITOR

)

63
64
55
66
67
68
69
7.
71
72
73
74
75
76
77
78
79
8.
81
82

----

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97
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0012 flBSE08

©

SOURCE

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'''DE C211690

11.

;AND 1 WORD FOR FINDMX PROCEDURE
STACK

ENDS

; •• *................CODE
CODE

SEGMENT

SEGMENT BYTE PUBLIC

'CODE'

; PARAMETERS ON STACK, DISPLACEMENT FROM TOS INCREASED BY TWO DUE TO INITIAL PUSH
WORD PTR [BP+6]
NO OF ROWS
EOU
NO-OF-COLS
EQU
WORD PTR [SP+4)
WORD PTR [BP+8]
ADR"_OY_MATRIX
EOU
;
FINDMX
PROC
NEAR
;PROCEDURE DECLARATION
;SAVE BP REGISTER
BP
PUSH
Mav
SP,SP
; BP POINTS TO PARAMETERS ON STACK
xaR
DX,OX
;SET OX = ASS OF CURRENT MAX .. '"
Mav
DI,DX
;01 = I (ROW INDEX) III 0
lSI = J (COLUMN INDEX) .. 0
Mav
Mav
; MAX '" CURRENT MAX = 0
Mav
CX ,NO OF COLS
CX,l SHL
.CX = (f$OF$COLS) • 2
;TERM.INATION FOR J (51) INDEX
Mav
SX ,ADR OF MATRIX
;ADR$OF$MATAIX PARAMETER
;BX POINTS TO FIRST ELEMENT OF A GIVEN ROW
ABC:
Mav
AX, [SX] [SI]
;GET ELEMENT OF MATRIX
OR
AX,AX
;SET FLAGS
JNS
DEF
;JUMP IF SIGN '" "
NEG
;NEGATE TO FORM POSITIVE NUMBER
DEF:
CMP
AX,OX
; COMPARE TO CURRENT MAX
JL
XYZ
;JUMP IF LESS THAN CURRENT MAX
Mav
DX,AX
; MOVE TO ABS OF CURRENT MAX
;MOVE MATRIX VALUE TO CURRENT MAX
Mav
AX, [BX] [51]
Mav
MAX,AX
XYZ:
ADD
SI,2
INCREMENT J INDEX BY TWO
CMP
5I,CX
END OF THIS ROW??
JB
ABC
IF NO, LOOP SACK FOR NEXT ELEMENT OF THIS ROW
LEA
BX, rBX+SI)
ex := ex + (2 • '$OF$COLS), BX POINTS TO NEXT ROW
Mav
SI,0

=!~~~X

INC

DI

CMP

DI,NO OF ROWS

JB

ABC

Mav

I\X,MI\X

POP
RET

BP

~INDMX

ENDP

bODE:

ENDS

111
112

6

END

SYMBOL TABLE LISTING

NAME

TYPE

??SEG
ABC
ADR OF MATRIX
CGRQUP-:CODE.
DATA.
DEF
DGROUP.
FINOMX.
!"'AX
NO OF COLS.
NO-OF-RQ\oIS.
STACKXYZ

SEGMENT
L NEAR
V WORD
GROUP
SEGMENT
SEGMENT
L NEAR
GROUP
L NEAR
V WORD
V WORD
V WORD
SEGMENT
L NEAR

VALUE

"''''ISH
"''''''8H

~01DH

£'000H
"'I1I0I'IH
000§H
"'''068
01'1288

ATTRIBUTES
SIZE="""'''H PARA PUBLIC
CODE
[BP)
CODE
SIZE .. ",,41H BYTt
PUBLIC 'CODE'
PUBLIC 'DATA'
SIZE""'''02H WORD
CODE
DATA STACK
CODE PUBLIC
DATA
(BP)
rBP)
SIZE-t=l" lCH PARA STACK 'STACK'
CODE

ASSEMBLY COMPLETE, NO ERRORS FOUND

A-232

J = '"

I ..

r +

1

LAST ROW ?1
IF NO, DO THE NEXT ROW
RETURN MAX VALUE IN AX REGISTER
RESTORE BP REGISTER
INCREMENT SP BY 6 AND RETURN TO CALLER

AP-43
rSIS-II ORL-PIi, Vl. 1
INVOKED BY:
QRLRIIi :FJ:MATRIX.OBJ, :Fl:FIND.OBJ,SBCIOS.LIB ORrGTN{HJP~H)
TNPUT MODULES INCLUDED:

: FI :MATRIX.OBJ (F.XFCUTTONVEHICLF.)
:F 1 :FIND. aBJ (FIND)
see lOS • LIB (SaCCO)
RESULT WRITTEN TO : Fl :MATRIX (EXECUTTQNVEHICLE)
START ADDRESS IS

®

START

fl100P1H

~Ue0H

LTH

:lAB"

w

/GS/ CGROUP
CODE (EXEClITIONVEHICLEl

COOE

B
W

COOE (FIND)
CODE (secco)

CODE
COOE

W

CONST (EXECUTIDNVEHICtE) CONST
CONST(secCO)
CONST
DATA (EXECUTIONVEHICLE)
DATA
DATAtFIND)
DATA
DATA (SBCCO)
DATA
STACK
STACK
MEMORY
MEMORY

225H
41H

P1266H

:lAH

012M"8
012ACH
0133CH
1/l13:lEH

D0H
CH
OH
90H
2H
0H

01340H

:aIllH

sw

A 1370H

0H

W

PI370H

0H

('II2ACH

CLASS

G

01225H

1/ll2A0H

(D100H,re02H)

ALIGN NA.ME

IGE/ CGROUP
/GS/ DGROUP

w
W
W

W

IGE/

DGROUP

??SEG (FIND)

(NULL)

DEBUG MAP OF : Fl :MATRIX (EXECUTIONVEHICLE)

®

£'ll2AH,e0m'lH
01131118,01B5H
~ 121<.8, 0e0CH
012A8,0'9111EH
(1112A8, ,;aHeH
012AH, A94CH
012AFI,0A6AH
012AH,e0SER
012AR, AI/l91!1H
0] 2AR, 0(1192H
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012AH,00911H
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n00H,elB8H
~leP,H,tHC2H

RueH, ~ICSH
9lfl'H,elD1H
IHoeH,0104H
0lA~H,01DAH

MODULE:
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL;
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL:
SYMBOL
SYMBOL
LINE.
LINE f
LINE f
LINE f
LINE t
LINE t
LINE

,

EXECUTrONVEHICLE
MEMORY
BINDECASC
TEMP
I
XRO~

YROW

ZROW
I
J
K
MAX
MAXASCARRAY
TEXT
6
10
12
13
14
16
17

0HJ0H,01EIH
eHl08,01FBH
IllHH'lH,R213H
PlHHIH,f"21EH
0U0H,e221H
121100H,IH'!02H
0100H,0f1'-IH
PURR, I!IR32H
0'HJP.H,0004BH
0HJ0H,1ll0511H
ea"H,01lJ5DH
"le0H,r.0fiEH
111 HHJH, 00 7FH
nee'H, {J11I9C8
9lP'0'H,('lI~A5H

0'100'H,"0'AEH
0HH.IH,eeBFH
0HJ0H,0'0Dfl8
!lIle"H, "'flE7H
fl100'H,09F8H
PlH~"H,0'13~H

A-233

LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE
LINE

f'

19

t

20
21
22
23
30
37
38

I
I

I

•
I

,
I
I

,

I

l'!UeH,ID39H
IllHI0H,{H42H
0100f1,IH4BH
{l100H,,,"15EH
~1I!!eH,~]r,9H
01IH~H,£l17AH

I"10€H,01S5H
0Hlft'lH, (HSEH

19

~10I11R.r]9FH

4.
41
42

1'1100H,F."lAAH

43

£l100H,023A8
0100H,02428
0100'8,0225H
012AH,0'09CH
01£10'8,024DH
OHalH,0225H

44
45
40
47

'8

~10P.H,{IIIB3H

49

50
51

IU0e8,02668

,,

LINE I,
LINE
LINE
LINE I
LINE
LINE I
LINE I
LINE
LINE !
LINE
LINE
MODULE
SYMBOL
SYMBOL
SYMBOL
SYMBOL
SYMBOL
PUBLIC
MODULE
PUBLIC

52
53

,"

,,•

55
50
57
58

59
60
61
02

FIN
ABC

DEF
FINDMX
MAX

XYZ
FINDMX
SBCCO
CO

AP-43
APPENDIX C
PROGRAM LISTING FOR EXECUTION$VEHICLE MODULE WITH CODE EXPANSION
PL/~-86

EXECUTIONVEHICLE

COfo!PI LEt

ISIS-II PL/M-86 Vl.0 COMPILATION OF MODULE EXECUTIONVEHICLE
NO OBJECT MODULE REQUESTED
COMPILER INVOKED BY:
PLM8fi :FJ :MATRIX.PLM DEBUG CODE NOOBJECr PRINT(:Fl:MATRIX.XLS)

/*

MATRIX MULTIPLTCATtDN EXAMPLE PROGRAM

PL/M-86 MAIN PROGRAM WHICH:
A)
8)

INITIALIZES TWO INTEGER MATRICES
MULTIPLIES THE TWO MATRICES AND STQRE:S THE RESULT IN A

THIRD MATRIX
')

CALLS AN ASSEMBLY L~NGUAGE PROCEDURE WHICH SEARCHES THE

D)

THIRD MATRIX FOR THE MAXIMUM VALUE
CALLS A PL/M PROCEDURE WHICH CONVERTS THE MAXIMUM VALUE
FROM INTEGER TO ASCI I

E)

,/

':ALLS A PROCEDURE WHICH OUTPUTS THE AscrI CHARACTERS ON
THE SYSTEM CONSOLE

EXECUTION$VEHTCLE:
DO;

/*

FTND$,.,X - EXTERNAL ASSEMBLY LANGUAGE PROCEDURE WHICH SEARCHES A
MATRIX FOR THE LARGEST ABSOLUTE MAGNITUDE.
PARAMETERS:
MATRIX$ADR ADDRESS OF THE MATRIX TO BE SEARCHED
ROWS - NUMBER OF ROWS IN THE MATRIX
COLS - NUMBER OF COLUMNS IN THE MATRIX

,/

FIND$MX: PROCEDURE (MATRIX$PTR, ROWS, COLS)
DECLARE (ROWS, COLS) INTEGER;
DECLARE MATRIXSPTR POtNTER;
END FrND$MX;

~·,INC

/*

INTEGER EXTERNAL;

EC$ASC - BINARY TO DECIMAL ASCII CONVERSION PROCEDURE
l-ARAMETERS:
VALUE - INTEGER VALUE TO BE CONVERTED TO ASCII
CHAR$ARRAY$ADR - ADDRESS OF 6 BYTE ARRAY WHERE ASCI I
STRING CONTAINING THE VALUE WILL BE STORED

'/
BIN$DEC$ASC:

0IB5
0186

PROCEDURE

B INDECASC
PUSH
MOV

55
BBEC

(VALUE, CHARSARRAY$ADR);
STATEMENT
PROC NEAR
BP
BP,SP

DECLARE (VALUE, TEMP, I) INTEGER;
DECLARE CHARSARRAYSADR POINTER;
DECLARE (CHAR$ARRP.Y BASED CHAR$ARRAY$ADR)

10

IF VALUE

01BR

II
12

13

(is)

BYTE;

0" THEN

B17E0600~0

PlIBD
7C03
31BF
E91200
DO;
CHAR$ARRAY(0)
IHC2
01CS

l'

<

B85Ee4
C6072D
TEMP == -VALUE;

; STATEMENT II HI
rBP] .VALUE,,,H

CMP
JL
JMP

'_I;
Mev
MOV

$+5H
@1

1*

SIGN CHARP,CTER */
STATEMENT
8X, rBP) .CHARARRAYADR
CHARARRAY fex] ,20H

01Cf!
8846136
01CB
F70B
r'lCD
89~6"'0C0
END;

MOV
MOV

; STATEMENT
AX, fep]. VALUE
AX
TEMP ,AX

13101

JMP

@2

NEG

STATEMENT

J5

]6

# '5

E91m3!?!

ELSE
DO;
CHAR$ARRAY(!i')

'+' ;

12

13

t

14

0104

MOV
MOV

; STATEMENT It 1 t5
BX, rBP1. CHARARRAYADR
CHARARRAY rBX1, 7BH

17

BB5EI"4
~ 107
C6~7 2B
TEMP"" VALUE;

MOV
MOV

, STATEfo1ENT
AX, [BP1. VALUE
TEMP,AX

18

~] DP.
8B41)['6
ell0D
890()l"r~~
END;

17

@2;

19

DO I

'"

5

TO

1 BY -1;
STATEMENT ., 19

C'llEl
131E7

13]EA

C7"'6~20e05"0

MOV

I,SH

E<;\Lil6r'0

JMP

@5

@3:
8 U,H;02I?'IH'FFF

ADD

J , 0FFF·FH

A-234

AP-43
~5,

P]F0
elFIS

IH3Efli'e0P100
7013

0lF8

£926'"

CMP
JGE
JMP

I,lH
S+5H
'4

CHAASARRAY(I) = UNSIGN (TEMP MOD III + 3111H;

2.

j

elFB

8BP61UHUJ
898AfI.
3102

elFF
0212
0'204
1206
1'28"
02/i!10

F7F9

AIC;t)S""
B85Ef!4

88361281
8811'
TEMP· TEMPI] 8;

~211

21

MaV
Mav
xaR
IDIV
ADD
Mav
Mav
Mav

STATEMENT •

20

AX, TEMP

ex, eAH

ox,ox

cx
OX, 3011

sx, [SP) .CHARARRAYADR
51,1

faX). CHARARRAY

fSI J, OL

; STATEMENT' 21
/* ASCII CHARACTERS 30 THAU 39 HEX REPRESENT THE DIGITS 1/1 THRU 9. THUS
TO CONVERT AN IN:r£GER TO ASCII REPEATED DIVISIONS BY Ie AND ADDING
THE REMAINDER TO 3e HEX WILL ACCOMPLISH THE CONVERSION "'/

22

'213
1217

88"6""""
99

MOV
cwo

0218

F7F9

IDIV

ex-

021A

8986""'oUJ

MOV

TEMP,AX

JMP

@3

POP

SP

END;

02lE
23

AX,TEMP

E9C9FF

STATEMENT •

22

STATEMENT f

23

END BINSDEC$ASC';
D221
"'222

50
C2"Ur-

1*

RET
BINDECASC

4H
EHOP

co - EXTERNAL PROCEDURE TO OUTPUT A CHARA.C'l'ER TO THE SYSTEM CONSOLE.
THIS PROCEDURE IS PART OF THE ISBC 957 LIBRARY FOR CONSOLE I/O
PARAMETER:
CHAR - ASCII CHARACTER TO BE OUTPUT ON THE CONSOLE

*j
2~

,.
25

27
~~

29

('0: PROCEDURE (CHAR) EXTERNAL;
DECL,&,RE CHAR BYTE;
END CO;

/* MATRIX DIMENSIONS
DECL.a.RE M LTTERA.LLY '6';
DECLARE N LITERALLY '51;~.
DECLARE P LITERALLY '3';

*/

/* THE THREE MATRICES ARE DECLARED AS ARRAYS Olo' STRUCTURES.

X$ROW IS COMPOSED
OF M STRUCTURES EACH OF WHICH IS COMPOSED OF N INTEGER ELEMENTS.
THUS
X$R~ MAY RE THOUGHT OF AS A M X N MATRIX.
THE MATRIX WILL BE STORED AS
A ROW-ORDeR MATRIX WITH THE ELEMENTS OF EACH ROW STORED HI ADJACENT MEMORY
LOCATIONS.' YSROW IS DECLARED AS A N X P MATRIX AND Z$ROW AS A N X P MATRIX
DECLARE X$ROW(M) STRU('TURE (OOL(N) INTEGER);
DECLARE Y$ROW(N) STRUCTURE (COL (P) INTEGER);
DECL.a.RE Z$ROW(M) STRUCTURE (COL (P) INTEGER);

.l3
34
35

DECLARE (I,.l,K,M1r.X) INTEGER;
DECLIlRE MAX$ASC$ARRAY (Il) BYTE;
DECLARE TeXT (*) BYTE DATA ('1'1AX VALUE'" ');

/* TNITIlILlZE

36

X~ROW SUCH THAT THE FIRST ROW IS SET EQUAL TO PI, THE SECOND
ROW EQUAL TO 1, THE THIRD R~ EQUAL TO 2, ETC.
*/
DO I'" 0 TO (M-J);
STATEMENT f 36
i'lA02 FA
CLI
9003
2E8E16~HI09!
Mav
55 ,CS:@@STACKSFRAME
SP ,@@STACK$OFFSET
81e8 BC9SA"
Mav
BaEe
"£1108
Mav
BP,SP
16
PUSH
SS
"9"0
pap
IF
os
""eE
fleeF
F8
STI
C796B2Bfl0fl0111
Mav
r,PH

"ue
"t1I16

@6,

B13E82fl'''~50e

I!IA1C

37

7EP-3
E93erlil
~"lE
DOJ-"TO

9P.21

CMP
JLE
JMP
(N-II;

e706841!10lHH!le

I,5H
$+5H

'7

Mav

J .eH

CMP

J,4H

STATEMENT ,

37

gTA.TEMENT f

3B

P8,

IPn

B13EB400e4p~

111020

'7Er3
.lLE
E9220[l
JMP
X$ROW(I).COL(J) '" I i

@9

.ctBenBUI!0I
89PA""

MaV
MaV

AX,I
CX,0AH

F7E9
8836841P
DIE6
89C3

IMUL

CX

MaV

SI,J
SI,l
8X,AX
eX,I
fax J. XROW fSI 1 ,CX

102F
38
P'032
~e3fi

1~39

00'38
I1IB3F

e"41
39

"043

8B£IIE82fJe

rB47

8ge814A~

END;

Sf.lL

Mav
MaV
Mav

~+5H

A-235

*/

AP·43

4.

ADO
J"P

P.l(ll6E140'A100

flflt!B

""51

E9D3FF

STATEMENT

t

39

STATEMENT

f

4"

J, JH
OR

(119:

END;

RUH;S2e""100

ens.
00SA

E9B9FF

I,1H

ADO
JMP

",

~6

/0 INITIALTZE Y$ROW SUCH THAT THE FIRST COLUMN IS S£'r EOUAL TO 0, THE
0/
SECONO COLUMN EQUAL TO -1, AND THE THIRD COLUMN EQUAL TO -2.
'1

DOI=BTO(N-l);

,
, STATEMENT·' 4,1

.850·

C78682.888e.

MOV

I,0R

819,
8063
0069
IUH;B
42

CMP
813E82088.0P
7E83
JLE
JMP
E948.0
DO J = B TO (P-l),

I,4K

$+58
~Il

STATEMENT • 42

,,916E
187.
e.7A
ee7C
'3

C786841e •• 0.
MOV
@12,
813E8488.2.8
CMP
JLE
7Ee3
E9268f
JMP
YSROW(I).COL(J) • -J;

J,fIIH

J,28
$+5H
U3
STATEMENT ,

le7F
1883
eBSS
8086
liSA
1.80
888F
e893
1895
0897
OP98
4'

AX,J
AX
AX
AX,I

MOV
NEG

88.68488
F708
5.
88068218
890680
F7£9
8836848.
01£6
89C3
59
89884880
END;

PUSH

MOV
MOV
IMUL
MOV
SHL
MOV
POP
MOV

11

Cx,6H
CX

SI,J
SI, )
BX,AX
CX
I I
r8X). YROW rSI) ,CX
;

•• 9C
80A2

STATEMENT •

44

t

45

STATEMENT "

., r,

#

I! 7

J,1H

ADO
JMP

818684880ue
E9CFFF

43

~12

~ll,

45

END;
STATEMENT

OMS
fl0AB

1*

1,·1H

.10

UI'
PERFORM MATRIX MULTIPLICATJQN

DO K = ,

(!IAAE

ADO
JMP

81068208018r
E9B!)FF

TO

*1

CP-J);

C79li8f;IlIf10PfJ0

MOV

K,PH

CMP
JLE
JMP

"',2H

~14,

. POB4

.7

09SA.

e 13£B60~020e
7E03

A~BC

EgeC~0

$+5H
~1

5

00 I = 0 TO (M-1) ,
STA'I'EMENT

P0CS
08CB

C7{HH12eep.ee€l
MOV
@16,
c~p
813EB?fil0P.5011
.JL!
7E03
E972f1f'
JMP
ZSROW(I) .COL (0) • r.;

"9100
0004

PBI:I'682~H'J
B906~0

MOV
MOV

0f107

F7E9
SB3G861i!fI

MOV

01E6

SAL

"C!'SF

Aeco

'B

I, PH
I,5H
$+5H
@17

1*

SET ZSROW ELEMENT TO P - /

; ST1>.TEMENT

0009
"flOC
aADF

00£1
49

A.X, I
CX,#iH
CX
BI, K
SI,l
BX,AX

IMUL

89C3
C7805E00A000
00 J = Po TO

MOV
MOV
fN-I) ;

rex] .ZRoWrSI]

/0

# 48.

,rH

SUM THE PRODUCT OF XSROW ROW TERMS AND Y$ROW COLUMN TERMS

; STATEMENt' 49

"AE7

C70';8040P"B9f1

MOV

J,0H

finD
IU'F~

S13ES""'''AUB
7E03

80FS

eMP
JLE

J ,48

£94J00

JMP

fl9

UBI

So

$+58

ZSROW(!) .COLfK) + ( X$ROW(I) .COL(J) • YSROW(J) .COL (K) );
; STATEMENT t 5A
MOV
AX,I
CX,eAH
MOV
IMUL
CX
SI,J
MOY
SHL
SI,l
AX
; 1
PUSH
MOV
AX,J
CX,6H
MOV
IMUL
CX
DIrK
MOV
SHL
01,1
BX,AX
MOV
MOV
AX, rsx] . YROW [01 1
ax
I 1
POP
IMUL
r8X).XROWrSI)
PUSH
AX
; 1
MOV
AX,1
!MUL
CX
MOV
9X,AX

ZSROW(I) .COL(O) •
98F8

~886B2e8

I,lIflFC

890A(II0

8eFF
0ln

F7£9
88368400
01£6
588B868488
a90688
F7E9
BB3EB600
DlE7
89C3
BBBI4888
58
F7A80488

01~S

0187
0108
lleC
9ur
8111
ellS
0117
0119
ellD
8pa
0122
8123
P.l27
0129

58
08868288
F7£9
B9C3

A-236

*/

AP-43
~ 12B
A12C

~8

e181SE'"

POP
ADD

AX

ADD
JMP

J, IN

;

1

rexJ • ZROW[CI J ,AX

END;

51

;

111139

81f1HiSII'IP."0UA

"'13~

E9B4FF

STATEMENT

f

51

STATEMENT

,

52

~18

@19,
52

END;

IH39
ADF

8H1IlP2"fl010f1
E983FF

ADD
JMP

r,IH
el~

@17:
53

END;
STATEMENT' S3
~142
~

148

SH'I68fiAAAU0

ADD
JMP

£9119FF

K,IH
~,.

@15:
MAX = FINOSMX (@Zt,ROW, M, P); /* FINO MAX VALUE OF Z$ROW *1
:

11I14B
9114£
1II1J1F

55

56

Be~fi"f'

P152

59

0153

SSP-3il1"

I'll 56

SP-

A157

E8r00p.

PJ15A

899J68fHHl

CALL B IN$DEC$ASC

IUSE

FF3688A0

0162
P165
111166

a8BA'0
5.
E84C1H"

DO I

.169
016F
0175
111177
57

58

B85E0f1
SA

AX,OFFSET(ZROW)
AX
1
AX, FiR

PUSH
MOV
PUSH

,r..x

I 2

AX,3H
AX

,

CALL

FINOMX

PUSH

AX

CALL

BINDECASC

Mav

@20,
CMP
JLE
7£03
E91409J
JMP
CALL CO/TEXT{I):

e13E8 2{l00B~"

C!l17A
EtBIE820"
017E
FFB701119J9J
1i!Il82 E8""""
ENO;

J

;

I,

-

2

1) j /* OUTPUT HEADER TEXT
; STATEMENT t 56

~H

I, "BH
$+58
@21

t

57

t

58

STATEMENT I

59

; STATEMENT I
BX,l
MAXASCARRAY rax]; I
CO

6.

Mav
PUSH
CALL
ADn
JMP

I,lH
@22

Mav
PUSH
CALL

ax, I

ADD
JMP

I, ]H
@20

TEXT fBX1
CO

I

STATEMENT

j

I

STATEMENT
"185

IUSB

59

8U6El2tHHU00
E9E1FF
@21,

DO I

.. til TO 5;

5~

MOV
fllJAX, AX
(MAX, @MAXSASCSARRAY)j 1* CONVERT TO DECIMAL ASCII
j STATEMENT' 55
PUSH
MAX
; 1
Mav
AX, OFFSET (MAXASCARRAY)

= " TO (SIGNED (SIZ E (TEXT»

C7~682"'IIHH"IH'

!=iTATEMENT ,

Mev
PUSH
MOV

/* OUTPUT ASC r I MAX VALUE */
j

fil1J

C706A2""'''''''''
MOV
I, ~H
@22:
0194
813E82""'0=0"
CMP
I,5H
019A
7E"'3
JLE
$+5H
11J19c £9] 4"'~
JMP
El23
CALL CO (fIIAX$ASCSARRAYtI )).

61

11l19F
881EA2Q!~
01A3
FFB78AIlI0
P11A7
£8~"'1iI11J
ENO:

P1SE

1!l'1AA
IHB0

, !=iTATEMENT

811i1fi82"~010P

E9E1FF

t

61

@23,
62

END EXECUTIONSVEHICLE;
STATEMENT
01B3
111184

FB
F4

STI
HLT

MODULE INFORMATION:
CODE AREA SIZE
=
CONSTANT AREA SIZE =
VARIA:9LE. AREA SIZE"
MAXIMUM STACK SIZE"
137 LINES READ
" PROGRAM ERROR(S)

0225H
"1""eH
el91H
011108H

5490
120
1440
80

END OF PL/M-86 COMPILATION

A-237 / A-238

t 62

*/

*/

Appendix B
Device Specifications
• 8086 Family

•

'For complete specifications refer to the
Intel MCS-85 User's Manual.
"For complete specifications refer to the
Intel Peripheral Design Handbook.
"'For complete specifications refer to the 1979
Intel Component Data Catalog.

8086/8086·218086·4
16·BIT HMOS MICROPROCESSOR

• Bit, Byte, Word, and Block Operations

Direct Addressing Capability to 1
• MByte
of Memory

16-Bit Signed and Unsigned
• 8-and
Arithmetic in Binary or Decimal

Assembly Language Compatible with
• 808018085

Including Multiply and Divide
Clock Rate (8 MHz for 8086-2)
• (45 MHz
M Hz for 8086-4)

14 Word, By 16-Bit Register Set with
• Symmetrical
Operations

MULTIBUS™ System Compatible
• Interface

• 24 Operand Addressing Modes

The Intel@ 8086 is a new generation, high performance microprocessor implemented in N-channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8- and
16-bit microprocessors. It addresses memory as a sequence of 8-bit bytes, but has a 16-bit wide physical path to memory for high performance.

EXECUTION UNIT

BUS INTERFACE UNIT

:
REGISTER FILE

I

RElOCATiON
REGISTER FilE
SEGMENT
REGISTERS
AND
INSTRUCTION
POINTER
(5 WORDS)

DATA.
POINTER. AND
INDEX REGS
(8 WORDS)

r--""'--,-~ BH'EISl
A1g1S6

FLAGS

3

OTlR,DEN.ALE

6·BYTE
INSTRUCTION
aUEUE

VCC

AD15

A013

A16/53

AD12

A17/54

AD11

A18/55

A010

A191S6

AD9

BHE/57

ADa

MN/MX

AD7

RD

AD6

RD/GTO (HOLD)

ADS

RO/GT1 (HLDA)

AD4

LOCK

(WR)

AD3

(M/iO)

AD2

52
51

AD1

so

(DEN)

ADO

aso

(ALE)

NMI

aS1

(INTA)

INTR

___

~
r------~~------~
INT-_
NMI---

ROI~

GND
A014

(DT/R)

TEST

CLK

READY

GND

RESET

CONTROL & TIMING

2

HOLO---

40 LEAD
eLK

RESET

READY

GND

V"

Figure 1. 8086 CPU Functional Block Diagram

Figure 2_ 8086 Pin Diagram

B-1

8086/8086-2/8086-4
A 19 - A 1. Byte data with even
on the OrOo bus lines while odd a
(Ao HIGH) is transferred on the 0 15-0 8
processor provides two enable signals, BH
.,
selectively allow reading from or writing into eit~
odd byte location, even byte location, or both.
instruction stream is fetched from memory as words
and is addressed internally by the processor to the byte
level as necessary.

FUNCTIONAL DESCRIPTION
GENERAL OPERATION
The internal functions of the 8086 processor are partitioned logically into two processing units. The first is
the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the block diagram of Figure
1.
These units can interact directly but for the most part
perform as separate asynchronous operational processors. The bus interface unit provides the functions
related to instruction fetching and queuing, operand
fetch and store, and address relocation. This unit also
provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase
processor performance through improved bus bandwidth utilization. Up to 6 bytes of the instruction stream
can be queued while waiting for decoding and execution.

.r---:J. FFFFFH

:CD}
j

CODE SEGMENT

XXXXOH

r--

The instruction stream queuing mechanism allows the
BIU to keep the memory utilized very efficiently. Whenever there is space for at least 2 bytes in the queue, the
BIU will attempt a word fetch memory cycle. This greatly
reduces "dead time" on the memory bus. The queue
acts as a First-In-First-Out (FIFO) buffer, from which the
EU extracts instruction bytes as required. If the queue is
empty (following a branch instruction, for example), the
first byte into the queue immediately becomes available
to the EU.

r

i==

} STACK SEGMENT

+OjSET

SEGMENT
REGISTER FILE
CS
SS
DS
ES

.J'--

t1

} DATA SEGMENT

r---

The execution unit receives pre-fetched instructions
from the BIU queue and provides un-relocated operand
addresses to the BIU. Memory operands are passed
through the BIU for processing by the EU, which passes
results to the BIU for storage. See the Instruction Set
description for further register set and architectural
descriptions.

}EXTRA DATA SEGMENT

~OOOOOH

MEMORY ORGANIZATION

Figure 3a_ Memory Organization

The processor provides a 20-bit address to memory
which locates the byte being referenced. The memory is
logically organized as a linear array of 1 million bytes,
addressed as OOOOO(H) to FFFFF(H). The memory can be
further logically divided into code, data, alternate data,
and stack segments of up to 64K bytes each, with each
segment falling on 16-byte boundaries. (See Figure 3a.)

In referencing word data the BIU requires one or two
memory cycles depending on whether or not the starting byte of the word is on an even or odd address,
respectively. Consequently, in referencing word operands performance can be optimized by locating data on
even address boundaries. This is an especially useful
technique for using the stack, since odd address references to the stack may adversely affect the context
switching time for interrupt processing or task multiplexing.

Word (16-bit) operands can be located on even or odd
address boundaries and are thus not constrained to
even boundaries as is the case in many 16-bit computers. For address and data operands, the least significant byte of the word is stored in the lower valued
address location and the most significant byte in the
next higher address location. The BIU automatically performs the proper number of memory accesses, one if
the word operand is on an even byte boundary and two if
it is on an odd byte boundary. Except for the performance penalty, this double access is transparent to the
software. This performance penalty does not occur for
instruction fetches, only word operands.

Certain locations in memory are reserved for specific
CPU operations (see Figure 3b.) Locations from address
FFFFOH through FFFFFH are reserved for operations
including a jump to the initial program loading routine.
Following RESET, the CPU will always begin execution
at location FFFFOH where the jump must be. Locations
OOOOOH through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt types has
its service routine pOinted to by a 4-byte pointer element
conSisting of a 16-bit segment address and a 16-bit offset address. The pOinter elements are assumed to have
been stored at the respective places in reserved memory
prior to occurrence of interrupts.

Physically, the memory is organized as a high bank
(01S-0a) and a low bank (0 7-0 0) of 512K 8-bit bytes
addressed in parallel by the processor's address lines

B-2

8086/8086-2/8086-4
MINIMUM AND MAXIMDt.i~"t
""'"

r---------.
FFFFFH
RESET BOOTSTRAP

The requirements for supporting min~/h'i't
Imum 8086 systems are sufficiently differ~",
cannot be done efficiently with 40 uniquely
pins. Consequently, the 8086 is equipped with Ii s
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the pins changes
dependent on the condition of the strap pin. When
MN/MX pin is strapped to GND, the 8086 treats pins 24
through 31 in maximum mode. An 8288 bus controller
interprets status information coded into 80,8,,82 to generate bus timing and control signals compatible with
the MULTIBUSTIiII architecture. When the MN/MX pin Is
strapped to Vee, the 8086 generates bus control signals
itself on pins 24 through 31, as shown In parentheses in
Figure 2. Examples of minimum mode and maximum
mode systems are shown in Figure 4.

PROGRAM JUMP

~--------I FFFFOH

~--------I3FFH
INTERRUPT POINTER
FOR_
TYPE
1-_ _
_255
_ _----1 3FCH

~--------I7H
INTERAUPT POINTER
FOR TYPE 1

~-IN-T-E-RR-U-PT-PO-IN-T-E-R--I;~
~

FOR
0 _
__
_TYPE
__

~OH

Figure 3b. Reserved Memory Locations

o
illl

Vee

8284 CLOCK
GENERATOR

1
G

MN/MX -Vee

r- CLK
f-f--

Ii3

~

ROY

NO r - l - - ,
I

I
WAIT
STATE
I
I
I GENERATOR I

L ___ ...l

",' l'.

,
,

M/fO

READY

fiiffii:
ifij

RESET

I
I
I
I
I
I
I
I

VIR
DTiR r------,
DEN r - - - , I

-

8086 CPU
ALE

r----I
I I
I
I I
I
I &a~B
I

GND~ OE 8282

I

'~'~:::~"~ ~~;; C
BHEI---

ADDR

I

~

I I
II
IL
T---II
L----IOE
II
TRAN8~~~IVER I

I
I
I
I
I

J----,
I
I

12)

L ___

f

I I
I

DATA

i!liE

OPTIONAL
FOR INCREASED
DATA BUS DRIVE

HE

CSOH

bl1
CSOL

WE 00

2142 RAM 14)
12)
1Kx8

l! TT: 11
CE

12)

I

1Kx8

OE

2718·2 PROM (2)
2Kx8

I

2Kx8

Figure 4a. Minimum Mode 8086 Typical System Configuration

B-3

CS

RDWR

MCS·80
PERIPHERAL

8086/8086-2/8086-4

Vee
CLK

GND

MRDC

SO
51

1"
GND

MWTC

ROY

WAIT
STATE
GENERATOR

8288

IORC
BUS
DEN CTRLR IOWC

r- -...,
I
I
I

N.C.

AMWC

S,

I
I
I

8086

DTIFf

CPU
~

N.C.

N.C.

AIOWC

ALE

INTA

---:-1

L ___ ...J
8282
LATCH
(2 OR 3)

I
I
I

r--.nn.;------~L-----------~------~~--~

8286
TRANSCEIVER
(2)

2142 RAM (4)
(21
1Kx8

2716·2 PROM (2)

MCS·80
PERIPHERAL

(2)

1Kx8

2K x 8

2K x 8

Figure 4b. Maximum Mode 8086 Typical System Configuration

50,

Status bits
8;', and S2 are used, in maximum mode,
by the bus controller to identify the type of bus transac·
tion according to the following table:

BUS OPERATION
The 8086 has a combined address and data bus com·
monly referred to as a time multiplexed bus. This tech·
nique provides the most efficient use of pins on the
processor while permitting the use of a standard 40·lead
package. This "local bus" can be buffered directly and
used throughout the system with address latching pro·
vided on memory and 1/0 modules. In addition, the bus
can also be demultiplexed at the processor with a single
set of address latches if a standard non·multiplexed bus
is desired for the system.

S2

o (lOW)
0
0
0
1 (HIGH)
1
1

Each processor bus cycle consists of at least four ClK
cycles. These are referred to as T" T2, T3 and T4 (see
Figure 5). The address is emitted from the processor
during T, and data transfer occurs on the bus during T3
and T4. T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" indication is given by the addressed device,
"Wait" states (Tw) are inserted between T3 and T4. Each
inserted "Wait" state is of the same duration as a ClK
cycle. Periods can occur between 8086 bus cycles.
These are referred to as "Idle" states (T I) or inactive ClK
cycles. The processor uses these cycles for internal
housekeeping.

s:; Sa
0
0
1
1
0
0

0
1
0
1
0
1
0

Interrupt Acknowledge
Read 1/0
Write 1/0
Halt
Instruction Fetch
Read Data from Memory
Write Data to Memory
Passive (no bus cycle)

Status bits S3 through S7 are multiplexed with high·
order address bits and the SHE signal, and are therefore
valid during T2 through T4. S3 and S4 indicate which
segment register (see Instruction Set description) was
used for this bus cycle in forming the address, accord·
ing to the following table:

During T, of any bus cycle the ALE (Address latch
Enable) signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/MX strap). At
the trailing edge of this pulse, a valid address and cer·
tain status information for the cycie may be latched.

S4

83

o (lOW)
o

0
1
0
1

1 (HIGH)
1

Alternate Data (extra segment)
Stack
Code or None
Data

S5 is a reflection of the PSW interrupt enable bit. S6 =0
and 57 is a spare status bit.

B-4

8086/8086-2/8086-4

T,
elK

GOES INACTIVE IN THE STATE

:~~'------LJ..//~I/@ft-Z ~

\'----

ADDR STATUS

-----~~

AODR'DATA

____
DA_TA_D_U_T'_D,_,-_DO_'__

~~-~

READY

- - MEMORY ACCESS T l M E - -

\'---_----11
Figure 5. Basic System Timing

1/0 ADDRESSING

0 7-0 0 bus lines and odd addressed bytes on 0 15-0 8 ,
Care must be taken to assure that each register within
an 8·bit peripheral located on the lower portion of the
bus be addressed as even.

In the 8086, I/O operations can address up to a max·
imum of 64K 1/0 byte registers or 32K 1/0 word registers.
The 1/0 address appears in the same format as the
memory address on bus lines A 15-A o. The address lines
A 19-A 16 are zero in 1/0 operations. The variable 1/0 in·
structions which use register OX as a pointer have full
address capability while the direct 1/0 instructions
directly address one or two of the 256 1/0 byte locations
in page 0 of the 1/0 address space.

EXTERNAL INTERFACE
PROCESSOR RESET AND INITIALIZATION
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 8086 RESET is
required to be HIGH for greater than 4 ClK cycles. The

1/0 ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the

B-5

8086/8086-2/8086-4
8086 will terminate operations on the high·going edge of
RESET and will remain dormant as long as RESET is
HIGH. The low·going transition of RESET triggers an in·
ternal reset sequence for approximately 10 ClK cycles.
After this interval the 8086 operates normally beginning
with the instruction in absolute location FFFFOH (see
Figure 3b). The details of this operation are specified In
the Instruction Set description of the MCS·86 Users'
Manual. The RESET Input is internally synchronized to
the processor clock. At initialization the HIGH·to·lOW
transition of RESET must occur no sooner than 50 ,..s
after power·up, to allow complete initialization of the
8086.

NON·MASKABLE INTERRUP
The processor provides a single non·ma
pin (NMI) which has higher priority than the
.
terrupt request pin (INTR). A typical use would be 0tij 1;"
tivate a power failure routine. The NMI is edge.trigger~6:>$.
on a lOW.to·HIGH transition. The activation of this pin
causes a type 2 interrupt. (See Instruction Set description.)
NMI is required to have a duration in the HIGH state of
greater than two ClK cycles, but is not required to be
synchronized to the clock. Any high-going transition of
NMI is latched on-chip and will be serviced at the end of
the current instruction or between whole moves of a
block-type instruction. Worst case response to NMI
would be for multiply, divide, and variable shift instruc·
tions. There is no specification on the occurrence of the
low'going edge; it may occur before, during, or after the
servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the N M I
procedure. The signal must be free of logical spikes in
general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.

If INTR is asserted sooner than 9 ClK cycles after the
end of RESET, the processor may execute one instruc·
tion before responding to the interrupt. NMI may not be
asserted prior to the 2nd ClK cycle following the end of
RESET.

INTERRUPT OPERATIONS
Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the Instruction Set description. Hardware interrupts can
be classified as non·maskable or maskable.

MASKABLEINTERRUPTONT~

The 8086 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable FLAG status bit. The
interrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high·going
edge of ClK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block-type instruction. During the interrupt response
sequence further interrupts are disabled. The enable bit
is reset as part of the response to any interrupt (INTR,
NMI, software interrupt or single'step), although the

Interrupts result in a transfer of control to a new pro·
gram location. A 256·element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see
Figure 3b), which are reserved for this purpose. Each
element in the table is 4 bytes in size and corresponds
to an interrupt "type". An interrupting device supplies
an 8·bit type number, during the interrupt acknowledge
sequence, which is used to "vector" through the ap·
propriate element to the new interrupt service program
location.

I

T1

T2

T3

T4ITI!

T2

T1

T3

AlE~~---(ln_ _

\\--.---11
\

INTA

\

ADo-AD'5

I

I / - - - I_ _ _ _

r'

~I

FLOAT

~~~""'------------I/

,I

~

\r--TYP-EVECTO~R)-

Figure 6. Interrupt Aclmowledge Sequence

B-6

I(

8086/8086-2/8086-4
,b,;'~,'-'.i't(,,,0:.'
to become active. It must remam.
CLK cycles. The WAIT instructl~;'I&.,
repeatedly until that time. This activitY'dge~./
sume bus cycles. The processor remains in·1l-nc·...
while waiting. All 8086 drivers go to 3·state OFFif,bH·s,.
"Hold"is entered. If interrupts are enabled, they rrilly
occur while the processor is waiting. When this occurs
the processor fetches the WAIT instruction one extra
time, processes the interrupt, and then re·fetches and
re·executes the WAIT instruction upon returning from
the interrupt.

FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the
interrupt. Until the old FLAGS register is restored the
enable bit will be zero unless specifically set by an
instruction.
During the response sequence (figure 6) the processor
executes two successive (back·to·back) interrupt
acknowledge cycles. The 8086 emits the LOCK signal
from T2 of the first bus cycle until T2 of the second. A
local bus "hold" request will not be honored until the
end of the second bus cycle. In the second bus cycle a
byte is fetched from the external interrupt system (e.g.,
8259A PIC) which identifies the source (type) of the
interrupt. This byte is multiplied by four and used as a
pOinter into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within
the limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable
bit when it restores the FLAGS.

8086 COMPARED WITH 8080/8085
While the 8086 has new instruction coding patterns to
allow for the greatly expanded capabilities, all functions
of the 8080/8085 may be performed by the 8086 with
identical program semantics to their 8080/8085 ver·
sions. For every 8080/8085 instruction there is a corre·
sponding 8086 instruction (or, in rare cases, a short
sequence of instructions). Virtually all 8086 data manip·
ulation instructions may be specified to operate on
either the full set of 16·bit registers or on an 8·bit subset
of them which corresponds to the 8080 register set. This
relationship is shown in Figure 7 where the shaded
registers (names in parentheses) represent the 8080
register set.

HALT
When a software "HALT" instruction is executed the
processor indicates that it is entering the "HALT" state
in one of two ways depending upon which mode is
strapped. In minimum mode, the processor issues one
ALE with no qualifying bus control signals. In Maximum
Mode, the processor issues appropriate HALT status on
525180 and the 8288 bus controller issues one ALE. The
8086 will not leave the "HALT" state when a local bus
"hold" is entered while in "HALT". In this case, the
processor reissues the HALT indicator. An interrupt
request or RESET will force the 8086 out of the "HALT"
state.

BASIC SYSTEM TIMING
Typical system configurations for the processor
operating in minimum mode and in maximum mode are
shown in Figures 4a and 4b, respectively. In minimum
mode, the MN/MX pin is strapped to Vee and the proc·
essor emits bus control signals in a manner similar to
the 8085. In maximum mode, the MN/MX pin is strapped
to Vss and the processor emits coded status informa·
tion which the 8288 bus controller uses to generate
MULTIBUS compatible bus control signals. Figure 5 iI·
lustrates the signal timing relationships.

READ/MODIFY/WRITE (SEMAPHORE)
OPERATIONS VIA LOCK
The LOCK status information is provided by the proc·
essor when directly consecutive bus cycles are required
during the execution of an instruction. This provides the
processor with the capability of performing read/modify/
write operations on memory (via the Exchange Register
With Memory instruction, for example) without the
possibility of another system bus master receiving
intervening memory cycles. This is useful in multi·
processor system configurations to accomplish "test
and set lock" operations. The LOCK signal is activated
(forced LOW) in the clock cycle following the one in
which the software "LOCK" prefix instruction is
decoded by the EU. It is deactivated at the end of the
last bus cycle of the instruction following the "LOCK"
prefix instruction. While LOCK is active all interrupts
are masked and a request on a RQ/GT pin will be
recorded and then honored at the end of the LOCK.

AX

AH

ex

>,BH

ex

CH

ox

DH

,AL ",

(A)

ACCUMULATOR

'BL

(HL)

BASE

CL'

(BC)

COUNT

DL

(DE)

DATA

~~'

SP)

STACK POINTER

BP

BASE POINTER

SI

SOURCE INDEX

01

DESTINATION INDEX

PC)
INSTRUCTION POINTER
~~~I~(
: • FlAGSH _!H~~\: I PSW) STATUS FLAGS

EXTERNAL SYNCHRONIZATION VIA TEST
As an alternative to the interrupts and general 110
capabilities, the 8086 provides a single software·
testable input known as the TEST signal. At any time the
program may execute a WAIT instruction. If at that time
the TEST signal is inactive (HIGH), program execution
becomes suspended while the processor waits for TEST

'----

cs

CODE SEGMENT

OS

DATA SEGMENT

SS

STACK SEGMENT

ES

EXTRA SEGMENT

Figure 7. 8086 Register Model; (8080 Registers Shaded)

B-7

8086/8086-2/8086-4
t>."

SYSTEM TIMING -

MINIMUM SYSTEM

location. Even addressed bytes are t
0 7-0 0 bus lines and odd addressed bytes

The read cycle begins In Tl with the assertion of the
Address Latch Enable (ALE) signal. The trailing (low·
going) edge of this signal Is used to latch the address
information, which Is valid on the local bus at this time,
Into the 828;,1/8283 latch. The BHE and Ao signals
address the low, high, or both bytes. From Tl to T4 the
M/iO signal indicates a memory or 110 operation. At T2
the address is removed from the local bus and the bus
goes to a high impedance state. The read control signal
is also asserted at T2. The read (RD) signal causes the
addressed device to enable its data bus drivers to the
local bus. Some time later valid data will be available on
the bus and the addressed device will drive the READY
line HIGH. When the processor returns the read signal
to a HIGH level, the addressed device will again 3·state
Its bus drivers. If a transceiver (8286/8287) is required to
buffer the 8086 local bus, Signals DTiA and DEN are pro·
vided by the 8086.

The basic difference between the interrupt a
edge cycle and a read cycle is that the interru
acknowledge signal (lNTA) is asserted in place of the
read (1m) signal and the address bus Is floated. (See
Figure 6.) In the second of two successive INTA cycles,
a byte of information is read from bus lines 07-00 as
supplied by the interrupt system logic (i.e., 8259A Prior·
ity Interrupt Controller). This byte identifies the source
(type) of the interrupt. It is multiplied by four and used
as a pointer into an interrupt vector lookup table, as
described ear.lier.

BUS TIMING -

The BHE and Ao signals are used to select the proper
byte(s) of the memoryliO word to be read or written
according to the following table:

AO

0
0

0

The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8259A Priority Interrupt Controller is
positioned on the local bus, a TTL gate Is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge
sequence and software "poll".

Whole word
Upper byte froml
to odd address

0

MEDIUM COMPLEXITY SYSTEMS

For medium complexity systems the MN/MX pin is con·
nected to Vss and the 8288 Bus Controller is added to
the system as well as an 8282/8283 latch for latching the
system address, and a 8286/8287 transceiver to allow for
bus loading greater than the 8086 is capable of handling.
Signals ALE, DEN, and DTiA are generated by the 8288
instead of the processor in this configuration although
their timing remains relatively the same. The 8086 status
outputs (S"2, 8 1, and So) provide type·of·cycle information
and become 8288 inputs. This bus cycle information
specifies read (code, data, or 110), write (data or 110),
interrupt acknowledge, or software halt. The 8288 thus
issues control signals specifying memory read or write,
110 read or write, or interrupt acknowledge. The 8288
provides two types of write strobes, normal and
advanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write. The
advanced write strobes have the same timing as read
strobes, and hence data isn't valid at the leading edge of
write. The 8286/8287 transceiver receives the usual T
and DE Inputs from the 8288's DTiFi and DEN.

A write cycle also begins with the assertion of ALE and
the emission of the address. The M/iO signal is again
asserted to indicate a memory or 110 write operation. In
the T2 immediately following the address emission the
processor emits the data to be written into the
addressed location. This data remains valid until the
middle of T4. During T2, T3, and Tw the processor asserts
the write control signal. The write (WR) signal becomes
active at the beginning of T2 as opposed to the read
which is delayed somewhat into T2 to provide time for
the bus to float.

SHE

c".

110 ports are addressed In the sa

Lower byte froml
to even address
None

B-8

8086/8086-2/ 8086-4
_

8086 FUNCTIONAL PIN DEFINITION
The following pin function descriptions are for 8086
systems In either minimum or maximum mode. The
"local Bus" In these descriptions Is the direct multi·
plexed bus Interface connection to the 8086 (without
regard to additional bus buffers).

INTR (INPUT)
Interrupt request is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt
acknowledge operation. A subroutine is vectored to via
an interrupt vector lookup table located in system
memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

During T1 these are the four most significant address
lines for memory operations. During 1/0 operations
these lines are lOW. During memory and 1/0 operations,
status information is available on these lines during T2,
T3, T w, and T 4. The status of the interrupt enable FLAG
bit (S5) is updated at the beginning of each ClK cycle.
AdS4 and A1rJS3 are encoded as follows:

TEST (INPUT)
The TEST input is examined by the "Wait" instruction. If
the TEST input is lOW execution continues, otherwise
the processor waits in an "Idle" state. This input is synchronized internally during each clock cycle on the
leading edge of ClK.

A 17/S 4
1

1

aCk~a~l.

READY (INPUT)

A1g1Sa, A1a1Ss, A 17/S4 , A1a1S3 (OUTPUT 3-STATE)

o

oV~ i ~

READY is the acknowledgement from the addressed
memory or 1/0 device that it will complete the data
transfer. The ROY signal from memoryllO is synchronized by the 8284 Clock Generator to form READY. This
signal is active HIGH.

ADwADo (INPUT/OUTPUT 3·STATE)

1 (HIGH)
1
S6 is 0 (lOW

:r--

This signal floats to 3-state OFF in "hold

These lines constitute the time multiplexed memoryllO
address (T 1) and data (T 2, T3, T w, T 4) bus. Ao is analogous
to BHE for the lower byte of the data bus, pins DrDo. It
is lOW during T 1 when a byte is to be transferred on the
lower portion of the bus in memory or 1/0 operations.
Eight-bit oriented devices tied to the lower half would
normally use Ao to condition chip select functions. (See
table on page 8.) These lines are active HIGH and float to
3-state OFF during interrupt acknowledge and local bus
"hold acknowledge".

o(lOW)
o

})Jr.",

on the 8086 local bus. RD Is actt\;<.efl'eW·
and T w of any read cycle, and is gli~taii\l!Je9
HIGH in T2 until the 8086 local bus has !loa-te

NMI (INPUT)

Alternate Data
Stack
Code or None
Data

Non-maskable interrupt is an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via
an interrupt vector lookup table located in system
memory. NMI is not maskable internally by software. A
transition from a lOW to HIGH initiates the interrupt at
the end of the current instruction. This input is internally synchronized.

This information indicates which relocation register is
presently being used for data accessing.
These lines float to 3-state OFF during local bus "hold
acknowledge" .

RESET (INPUT)
RESET causes the processor to immediately terminate
its present activity. The signal must be active HIGH for
at least four clock cycles. It restarts execution, as
described in the Instruction Set description, when
RESET returns lOW. RESET is internally synchronized.

BHE/S7 (OUTPUT 3-STATE)
During T1 the bus high enable signal (BHE) should be
used to enable data onto the most significant half of the
data bus, pins 0 15-08' Eight-bit oriented devices tied to
the upper half of the bus would normally use BHE to
condition chip select functions. BHE is lOW during T1
for read, write, and interrupt acknowledge cycles when a
byte is to .be transferred on the high portion of the bus.
(See table on page 8.) The S7 status information is available during T2, T3 , and T 4. The signal is active lOW, and
floats to 3-state OFF in "hold". It is lOW during T1 for
the first interrupt acknowledge cycle.

elK (INPUT)
The clock provides the basic timing for the processor
and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.
Vee
Vee is the + 5V ± 10% (± 5% on 8086-2, 8086-4) power
supply pin.

RD (OUTPUT 3-STATE)
Read strobe indicates that the processor is performing a
memory or 1/0 read cycle, depending on the state of the
S2 pin. This signal is used to read devices which reside

GND
GND are the ground pins

B-9

8086/8086-2/8086-4
p#,<-&,!>-

2. During the CPU's next T4 ol"V .
from the 8086 to the requestinif'tl:li!
indicates that the 8086 has allowed
to float and that it will enter
acknowledge" state at the next ClK . The C .
bus interface unit is disconnected logically from'
the local bus during "hold acknowledge".

The following pin function descriptions are fo!:....!he
8086/8288 system in maximum mode (I.e., MN/MX =
Vssl. Only the pin functions which are unique to max·
Imum mode are described; all other pin functions are as
described above.

52,5 1, So (OUTPUT 3·5TATE)
These status lines are encoded as follows:
52

51

50

o (lOW)

0
0
1

0
0

1

1

0
0

0

0
0
0

1 (HIGH)
1

1

1
0

Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive

Status is active during T4• T 1• and T2 and is returned to
the passive state (1,1,1) during T3 or during Tw when
READY is HIGH. This status is used by the 8288 Bus
Controller to generate all memory and I/O access control signals_ Any change by 8;,8" or So during T4 is used
to indicate the beginning of a bus cycle, and the return
to the passive state in T3 or Tw is used to indicate the
end of a bus cycle.

3. A pulse 1 ClK wide from the requesting master
indicates to the 8086 (pulse 3) that the "hold"
request is about to end and that the 8086 can
reclaim the local bus at the next ClK.
Each master-master exchange of the local bus is a
sequence of 3 pulses. There must be one dead ClK
cycle after each bus exchange. Pulses are active lOW.

LOCK (OUTPUT 3-STATE)
The lOCK output indicates that other system bus
masters are not to gain control of the system bus while
lOCK is active lOW. The lOCK signal is activated by
the "lOCK" prefix instruction and remains active until
the completion of the next instruction. This signal is
active lOW, and floats to 3-state OFF in "hold acknowledge".

These signals float to 3-state OFF in "hold acknowledge".

aSh OSo (OUTPUT)

ROtGT o, ROtGTl (INPUT/OUTPUT)

QS1 and QS o provide status to allow external tracking of
the internal 8086 instruction queue.

The request/grant pins are used by other local bus
masters to force the processor to release the local bus
at the end of the processor's current bus cycle. Each pin
is bidirectional with RQ/GTo having higher priority than
RQ/GT 1. RQ/GT has an internal pull-up resistor so may
be left unconnected. The request/grant sequence is as
follows (see Figure 14):

Q5 1

Q5 0

o (lOW)
o

0

1 (HIGH)
1

0
1

1

No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue

1. A pulse of 1 ClK wide from another local bus
master indicates a local bus request ("hold") to
the 8086 (pulse 1).

The queue status is valid during the ClK cycle after
which the queue operation is performed.

B-1O

8086/8086-2/8086-4
The followIng pIn function descrIptIons are for the 8088
mInImum mode (I.e., MN/MX = Vcd. Only the pIn func·
tlons whIch are unIque to mInImum mode are descrIbed;
all other pIn functions are as descrIbed above.

DT/R (OUTPUT 3·STATE)
Data transmit/receive Is needed In mini
desires to use an 8286/8287 data bus trans
used to control the direction of data flow throu
In
transceiver. Logically DT/R is equivalent to
maximum mode, and its timing Is the same as for'
M/IO.(T HIGH, R LOW.) This signal floats to 3-state
OFF in local bus "hold acknowledge".

51

MilO (OUTPUT 3·STATE)
This status line is logically equivalent to S2 in the max·
imum mode. It is used to distinguish a memory access
from an 110 access. M/iO becomes valid in the T4
preceding a bus cycle and remains valid until the final T4
of the cycle (M = HIGH, 10 = LOW). M/iO floats to 3·state
OFF in local bus "hold acknowledge".

ViR (OUTPUT 3·STATE)
Write strobe indicates that the processor is performing
a write memory or write 110 cycle, depending on the
state of the M/K5" signal. INA is active forT 2, T3 and Tw of
any write cycle. It is active LOW, and floats to 3-state
OFF in local bus "hold acknowledge".
INTA (OUTPUT)
INTA is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T2, T3 and Tw of each
interrupt acknowledge cycle. INTA floats to 3-state OFF
in '''hold acknowledge".

ALE (OUTPUT)
Address latch enable is provided by the processor to
latch the address into the 8282/8283 address latch. It is
a HIGH pulse active during T1 of any bus cycle. Note
that ALE is never floated.

=

=

DEN (OUTPUT 3·STATE)
Data enable is provided as an output enable for the
8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and
1/0 access and for INTA cycles. For a read or INTA cycle
it is active from the middle of T2 until the middle of T4,
while for a write cycle it is active from the beginning of
T2 until the middle of T4. DEN floats to 3-state OFF in
local bus "hold acknowledge".

HOLD (INPUT), HLDA (OUTPUT)
HOLD indicates that another master is requesting a
local bus "hold". To be acknowledged, HOLD must be
active HIGH. The processor receiving the "hold"
request will issue HLDA (HIGH) as an acknowledgement
in the middle of T4 or TI. Simultaneous with the
issuance of HLDA the processor will float the local bus
and control lines. After HOLD is detected as being LOW,
the processor will LOWer HLDA, and when the processor needs to run another cycle, it will again drive the
local bus and control lines. (See Figure 15.)
HOLD is not an asynchronous input. External synchronization should be provided If the system cannot
otherwise guarantee the setup time.

B-ll

8086/8086·2/8086·4
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Ab
Ratings" may cause permanent damage to the device. Thl
rating only and functional operation of the device at these or a
conditions above those indicated In the operational sections of t
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.

Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on Any Pin with
Respect to Ground ..........•....... - 1.0 to + 7V
Power Dissipation ........................ 2.5 Watt

D.C. CHARACTERISTICS
8086: TA=O·Cto 70·C, Vcc=5V ±10%
8086·218086·4: T A = O·C to 70 ·C, Vee = 5V ± 5 %
Symbol

Paramet.r

Min.

Vil

IAput Low Voltage

-0.5

V IH

Input High Voltage

2.0

VOL

Output Low Voltage

V OH

Output High Voltage

lee

Power Supply Current

Max.

Units

+0.8

V

Vee+ 0.5

V

0.45

V

IOl=2.0 rnA

V

IOH= -400,..A

2.4

8086/8086·4
8086·2

340
350

rnA
rnA

T.st Conditions

T A =25·C

< V IN < Vee

III

Input Leakage Current

±10

,..A

OV

I lO

Output Leakage Current

±10

,..A

0.45V Et VOUT Et Vee

Vel

Cloek Input Low Voltage

-0.5

V qH

Clock Input High Voltage

3.9

C IN

CIO

+0.6

V

Vee + 1.0

V

Capacitance of Input Buffer
(All input except
ADo-AD15, ROIGn

10

pF

fe= 1 MHz

Capacitance of 1/0 Buffer
(AD o -AD 15, ROIGn

20

pF

fe= 1 MHz

B-12

8086/8086-2/8086-4
A.C. CHARACTERISTICS
8086: TA = O·C to 70·C, Vcc = 5V ± 10%
8086-2/8086-4: TA= O·C to 70·C, Vcc= 5V ± 5%
8088 MINIMUM COMPLEXITY SYSTEM (Figures 8, 9, 12, 15)
TIMING REQUIREMENTS
808818088-4
Symbol

Parameter

80811-2

Min.

Max.

Min.

Max.

Unlla

200
250

500
500

125

500

ns

8086
8086-4

Te.1 Condilions

TCLCL

CLK Cycle Period -

TCLCH

CLK Low Time

('h TCLCL) - 15

('h TCLCL) - 15

TCHCL

CLK High Time

('13 TCLCL) + 2

('13 TCLCL) + 2

TCH1CH2

CLK Rise Time

10

10

ns

From 1.0V to 3.5V

TCL2CLI

CLK Fall Time

10

10

ns

From 3.5V to 1.0V

TDVCL

Data In Setup Time

30

20

TCLDX

Data In Hold Time

10

10

ns

TRWCL

ROY Setup Time into 8284 (See Notes I, 2)

35

35

ns

ns
ns

ns

TCLRIX

ROY Hold Time into 8284 (Sse Notes I, 2)

0

0

ns

TRYHCH

READY Setup Time into 8086

('h TCLCL)-15

('h TCLCL)-15

ns

TCHRYX

READY Hold Time Into 8088

30

20

ns

TRYLCL

READY Inactive to CLK (See Note 3)

-8

-8

ns

THVCH

HOLD Setup Time

35

20

ns

TINVCH

INTR, NMI, TEST Setup Time (Sse Note 2)

30

15

ns

TIMING RESPONSES
Symbol

808818088-4
Paramaler

8088-2

Min.

Mex.

Min.

Max.

Unll.

10

110

10

80

ns

80

TCLAX

TCLAV

Address Valid Delay

TCLAX

Address Hold Time

10

TCLAZ

Address Float Delay

TCLAX

TLHLL

ALE Width

TCLLH

ALE Active Delay

TCHLL

ALE Inactive Delay
Address Hold Time to ALE Inactive

TCLDV

Data Valid Delay

10

TCHDX

Data Hold Time

10

50

ns

50

ns

55

ns

TCLCH-l0

80

TLLAX

ns

10

TCLCH-20

85
TCHCL-l0

ns

TCHCL-l0
110

10

ns

eO

10

ns
ns

TWHDX

Data Hold Time After WR

TCVCTV

Control Active Delay 1

10

110

10

70

ns

TCHCTV

Control Active Delay 2

10

110

10

80

ns

TCVCTX

Control Inactive Delay

10

110

10

70

ns

TAZRL

Address Float to READ Active

0

TCLRL

10

185

10

100

ns

TCLRH

1m Active Delay
1m Inactive Delay

10

150

10

80

ns

TRHAV

1m Inacllve to Next Address Active

TCLHAV

HLDA Valid Delay

TRLRH

1m Width

2TCLCL-75

2TCLCL-50

ns

TWLWH

WRWldth

2TCLCL-80

2TCLCL-40

ns

TAVAL

Address Valid to ALE Low

TCLCH-80

TCLCH-40

ns

TCLCH-30

TCLCH-30

ns

ns

0

TCLCL-45

ns

TCLCL-40

10

180

10

NOTES: 1. Signal at 8284 shown for reference only.
2. Setup requirement for asynchronous Signal only to guarantse recognition at next CLK.
3. Applies only to T2 slale. (8 ns Into T3)

B-13

Ta.1 Condilion.

100

ns

=

CL 2()'loo pF for
all 8086 Outputs
(In add Ilion to
8086 self·load)

8086/8086-2/8086-4

h

Ji~

8088 MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) (Figural 10-14)
TIMING REQUIREMENTS

'Yc '$/$

Symbol
TCLCL

Parameter
CLK Cycle Period -

8086
8086·4

1;;""11

80811-2

808618088-4

of
~

Min.

Max.

Min.

Max.

Units

200
250

500
500

125

500

ns

Test C

"4

TCLCH

CLK Low Time

(% TCLCL) -15

(% TCLCL)-15

TCHCL

CLK High Time

(v.. TCLCL) + 2

(v.. TCLCL) + 2

ns

TCH1CH2

CLK Aise Time

10

10

ns

From .1.0V to 3.5V

TCL2CLl

CLK Fall Time

10

10

ns

From 3.5V to 1.0V

TDVCL

Data In Setup Time

TCLDX

Data In Hold Time

TAWCL

ADY Setup Time Into 8284 (See Notes 1. 2)

TCLA1X

ADY Hold Time into 8284 (See Notes 1, 2)

TAYHCH
TCHAYX

ns

20

ns

10

10

ns

35

35

ns

0

0

ns

AEADY Setup Time into 8086

(2/\ TCLCL) - 15

(% TCLCL) - 15

ns

AEADY Hold Time into 8086

30

20

ns

TAYLCL

AEADY Inactive to CLK (See Note 4)

-8

-8

ns

TINVCH

Setup Time for Aecognition
(INTA, NMI, TEST) (See Note 2)

30

15

ns

TGVCH

AO/GT Setup Time

30

15

ns

TCHGX

AO Hold Time into 8086

40

30

ns

TIMING RESPONSES
Symbol

30

808618086·4
Parameter

8086·2

Min.

Max.

Min.

Max.

Unll.

35

10

35

ns

35

10

35

ns

65

ns
ns

TCLML

Command Active Delay (See Note 1)

10

TCLMH

Command Inactive Delay (See Note 1)

10

TAYHSH

AEADY Active to Status Passive (See Note 3)

TCHSV

Status Active Delay

10

110

10

80

TCLSH

Status I nactlve Delay

10

130

10

70

ns

TCLAV

Address Valid Delay

10

110

10

80

ns

80

TCLAX

110

TCLAX

Address Hold Time

10

TCLAZ

Address Float Delay

TCLAX

TSVLH

Status Valid to ALE High (See Note 1)

TSVMCH
TCLLH
TCLMCH

10

ns
50

ns

15

15

ns

Status Valid to MCE High (See Note 1)

15

15

ns

CLK Low to ALE Valid (See Note 1)

15

15

ns

CLK Low to MCE High (See Note 1)

15

15

ns

TCHLL

ALE Inactive Delay (See Note 1)

15

15

ns

TCLMCL

MCE Inactive Delay (See Note 1)

15

15

ns

TCLDV

Data Valid Delay

10

80

ns

TCHDX

Data Hold Time

10

TCVNV

Control Active Delay (See Note 1)

5

45

5

45

TCVNX

Control Inactive Delay (See Note 1)

10

45

10

45

T~AL

Address Float to Aead Active

0

TCLAL

AD Active Delay

10

165

10

100

TCLAH

AD I nactlve Delay

10

150

10

80

TAHAV

AD Inactive to Next Address Active

TCHDTL

Direction Control Active Delay (See Note 1)

50

50

ns

TCHDTH

Direction Control Inactive Delay (See Note 1)

30

30

ns

TCLGL

m Active Delay

0

65

0

50

ns

TCLGH

GT I nactlve Delay

0

65

0

50

ns

TALAH
NOTES: 1.
2.
3.
4.

AD Width

110

10

2TCLCL-50

ns
ns
ns

TCLCL-40

Signal at 8284 or 8286 shown for reference only.
Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
Applies only to T3 and wait states.
Applies only to T2 state (8 ns "nto T3).

B-14

ns

0

TCLCL-45

2TCLCL-75

10

T••t Conditions

ns
ns
ns

ns

CL=2()'100 pF for
all 8086 Outputs
(In addition to
8086 self·load)

8086/8086-2/8086-4

VCH~
CLK (8284 Output)

vi,.
-

T,

T,

T,

v----\
----"~'-tJ

f

-

'------.I

TCHCTV

~

MliO
TCLAY---

-

-

TCHCL

ALE

f-

TLH~L----:::::

TALL
TCHLL-I

-

T.

r-\-

I-TCLCH-

TCLDV 1--'

TCHDX-

I--

TCLAX~HE, A19-A,.

TCLLH-

Tw

rTCL2CL~~

\
/

5,-5,

I

I--TLLAX

:::

r--

tt--

/_---

-TR1VCL

V,H""'"
ROY (8284 Input)
SEE NOTE 4

t

VIL .......

\

..... ~--

I----'TCLR'X

TRYlCl-

-

~

--

READY (8088 Input)

1

-r- -TAVAL
TLLAX----,

TCLAVAD'5-ADo

V

!-TCLAZ

A'5-Ao
TAZRL_

RD
READ CYCLE

=~TCHCTV

(NOTE ')
(WR,INTA=VOH)

TDVCL- -TCLDX-

f=r
I

TCLRL

-TCHRYX

\

-

TRYHCH-

1-1

7

DATA IN
TCLRH-

Figure 8. 8088 Bus Timing -

B-15

FLO:~"i-TRHAV

~
TRLRH

DTIR

TCVCTV- {

,--I

TCVCTX-

Minimum Mode System

1

I

-TCHCTV

8086/8086-2/8086-4

elK (8284 Output)

M/iO

ALE

AD,.-ADo

WRITE CYCLE
(NOTE j)

DEN

(RD. iID.
DTII!=VOH)

WR

TCLAZ

AD1S-ADO

FLOAT
TCHCTV

INTA CYCLE

DTIR

(NOTES 11l3)
TCVCTV

~Wii=VOH
=VOU

iNTA
TCVCTX
DEN

INVALID ADDRESS
TCLAV

NOTES:

1. ALL SIGNALS SWITCH BETWEEN VOH AND VOL UNLESS OTHERWISE
SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF To. T3. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. TWO INTA CYCLES RUN BACK·TO·BACK. THE 8088 LOCAL ADDR/DATA BUS IS
FLOATING DURING BOTH INTA CYCLES. CONTROL SIGNALS SHOWN FOR
SECOND INTA CYCLE.
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

Figure 9. 8086 Bus Timing - Minimum Mode System (conl'd)

B-16

8086/8086-2/8086-4

T,

T,

ClK
VCl

aSo,as,

s"s"s, (EXCEPT HALT)

r-/

ALE (8288 OUTPUT)
SEE NOTE 5

1
RDY (8284 INPUT)

READ CYCLE

TCLAV-..j

TClRH -+--~~-4

RD
TRlRH

TCHDTL-I

DT/R

TCLMH--8288 OUTPUTS
SEE NOTES 5,6

MRDCOR

iORC
DEN

TCVNX-

Figure 10. 8086 Bus Timing -

Maximum Mode System (Using 8288)

B-17

8086/8086-2/8086-4

T,

T3

elK
vel

52,51,SO (EXCEPT

HALT)

WRITE CYCLE

TCHDX-

DATA
TCVNXDEN

TCLMH--8288 OUTPUTS

SEE NOTES 5,6

AMWC: OR AIOWC

MWTC OR lowe

INTA CYCLE
AD1S..'ADO
(SEE NOTES 3 & 4)

I

,--

MCEI
POEN

TCHDTH

DT/A

8288 OUTPUTS
SEE NOTES 5,6

INTA

I

DEN

TeVNx-1

SOFTWARE HALT -

(~= VoURD,MRDC,IOAC,MWfC,AMWC,IOWC,AIOWC,INTA,DTIR = VOH)

INVALID ADDRESS
reLAV
~

,..---------~\

\'----~/

NOTES:

- -----

\.- -----

1. ALL SIGNALS SWITCH BETWEEN VOH ANO VOL UNLESS OTHERWISE
SPECIFIED.
2. RDY IS SAMPLED NEAR THE END OF T2, T3. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.

3. CASCADE ADDRESS IS VALID BETweEN FIRST AND SECOND INTA CYCLE.
4. TWO INTA CYCLES RUN BACK·TO·BACK. THE 8086 LOCAL ADDR/DATA BUS IS
flOATING DURING BOTH INTA CYCLES. CONTROL FOR POINTER ADDRESS
IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNAL.S AT 8284 OR 8288 ARE SHOWN FOR REFERENCE ONL.Y.
6. THE ISSUANCE OF THE 8288 COMMAND AND CONTROL. SIGNAL.S (MlWC,
~,AMWC, 10RC, 10WC, AIOWC, INTA AND DEN) L.AGS THE ACTIVE HIGH
8288 CEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.
8. STATUS INACTIVE IN STATE JUST PRIOR TO Til.

Figure 11. 8086 Bus Timing -

Maximum Mode System (Using 8288) (cont.)

B-18

8086/8086-2/8086-4

INTR

TEST

NOTE:
1, SETUP REQUIREMENTS FOR ASYNCHRONOUS SIGNALS ONLY TO GUARANTEE RECOGNITION AT NEXT ClK

Figure 12. Asynchronous Signal Recognition

Any eLK Cycle

Any elK CYCle---j

-_I

eLK

Figure 13. Bus Lock Signal Timing (Maximum Mode Only)

I-----C

Previous grant

NOTES:

COPROCESSOR
(SEE NOTE 1)

1. THE COPROceSSOR MAY NOT DRIVE THE BUSES OUTSIDE THE REGION
SHOWN WITHOUT RISKING CONTENTION.

Figure 14. Request/Grant Sequence Timing (Maximum Mode Only)

Cl' '"\

.r-I--'

~' , CLK ~

OR 2 CYCLES

'l1-TH~r-I I~~_THV~

HOlD~I\

11 r;;TC\--'HAV_---II-__-I--.

HLDA

!
~_-I'"I--':-----;-I\lj~TClAZ______N-""-1

REGISTER FILE

REGISTER FILE

DATA.

POINTER, AND
INDEX REGS
(8 WORDS)

16·BIT ALU

FLAGS

DTiR'D"E'N ALE

GND

Vee

A014

A015

AD13

A16/S3

AD12

A17/54

AD11

AlB/55

AD10

A19/S6

AD9

BHE/S7

AD8

MN/MX

AD7

AD

AD6

Ra/GTO (HOLD)

ADS

Ra/GT1 (HLDA)

AD'

LOCK

(WR)

AD3

52

(M/iO)

AD2

51

(DTIR)

AD1

so

(DEN)

ADO

aso

(ALE)

NM)

aS1

(INTA)

INTR

~--_r------~~-------'
INT--_
NMI---

TEST

elK

READY

GND

RESET

CONTROL & TIMING

HOLD--HLOA--....-r__. . .__. - -__-;---:::~

elK

RESET

40 LEAD

READY

Figure 2. 18086 Pin Diagram

Figure 1. 18086 CPU Functional Block Diagram

B-23

8088
8-BIT HMPS MICROPROCESSOR
• 8·Bit Data Bus Interface

• 24 Operand Addressing Modes

• 16·Bit Internal Architecture

• Byte, Word, and Block Operations

• Direct Addressing Capability to 1 Mbyte
of Memory
• Direct Software Compatibility with 8086

• 8·Bit and 16·Bit Signed and Unsigned
Arithmetic in Binary or Decimal, includ·
ing Multiply and Divide

• 14·Word by 16·Bit Register Set with
Symmetrical Operations

• Compatible with 8155·2, 8755A·2 and
8185·2 Multiplexed Peripherals

The Intel"'8088 is a new generation, high performance microprocessor implemented in N·channel, depletion load,
silicon gate technology (HMOS), and packaged in a 40-pin CerDIP package. The processor has attributes of both 8 and
16-bit microprocessors. It is directly compatible with 8086 software and 8080/8085 hardware and peripherals.

8088 CPU FUNCTIONAL BLOCK DIAGRAM

8088 PIN DIAGRAM

MEMORY INTERFACE
MIN
MODE

C·BUS

INSTRUCTION
STREAM BYTE
OUEUE

GND

Vee

A14

A1S

A13

A16JS3

A12

A17/S4

A11

A181SS

A10

BUS
INTERFACE
UNIT

1

MAX
MODE

A19/S6
(HIGH)

A9

SSO

CS

A8

MN/MX

SS

AD7

DS

AD6

HOLD

IP

ADS

HlDA

(Ali/ilfi)

AD4

Wii

(lOCK)

AD3

101M

(52)

AD2

DTIft

(51)

AD1

DEN

(SO)

ADO

ALE

(OSO)

NMI

INTA

(OS1)

INTR

TEST

A·BUS

EXECUTION
UNIT

!

AH

Al

BH
CH

Bl
Cl

DH

Dl

Ali

SP

ClK

READY

BP

GND

RESET

SI
01

FLAGS

B-24

(RQ/GTO)

8088
f~f"~

Minimum and Maximum

FUNCTIONAL DESCRIPTION
Memory Organization
The processor provides a 20·bit address to memory
which locates the byte being referenced. The memory is
logically organized as a linear array of 1 million bytes,
addressed as OOOOO(H} to FFFFF(H}. The memory can be
further logically divided into code, data, alternate data,
and stack segments of up to 64K bytes each, with each
segment falling on 16·byte boundaries. (See Figure 1.)
Word (16·bit) operands can be located on even or odd ad·
dress boundaries. For address and data operands, the
least significant byte of the word is stored in the lower
valued address location and the most significant byte in
the next higher address location. The BIU will auto·
matically execute two fetch or write cycles for 16·bit
operands.

D}

i·-L

~----------~

RESET BOOTSTRAP

t
Hj

+ OFFSET

SEGMENT
REGISTER FILE

(

MSB

~~3;1~~~~==~lW~O_RD~\t:BL;:::E~

FFFFFH

1 -_ _--'-P"'RO=-G=.:R"'Ac::M-=:J"-'UM"'P_ _ _--l FFFFOH

1---------~----l3FFH

INTERRUPT POINTER

~---~F~O~R~TY~P~E~25~5---~3FOH

CODE SEGMENT
1--------------l7H
INTERRUPT POINTER

XXXXOH

I.

~'Ot

The requirements for supporting mirif~~.
mum 8088 systems are sufficiently differe'h1,\.:
cannot be done efficiently with 40 uniquely' ~jt}e~:t
pins. Consequently, the 8088 is equipped with a st'ra,p'c
pin (MN/MX) which defines the system configuration.
The definition of a certain subset of the pins changes,
dependent on the condition of the strap pin. When the
MN/MX pin is strapped to GND, the 8088 defines pins 24
through 31 and 34 in maximum mode. When the MN/MX
pin is strapped to Vee, the 8088 generates bus control
signals itself on pins 24 through 31 and 34.

~FFFFFH

6.1K6

r:

M'OQiss
P'!J:<

FOR TYPE 1

H

~-----IN-TE~R=-R~UP~T~P=-OI~N-TE-R--~~H

L-_ _ _~F_=:O~R~TY~P_=:E~O_ _ _~OH

lJ STACK SEGMENT

Figure 2. Reserved Memory Locations

l
J DATA SEGMENT

OS
ES

} EXTRA DATA SEGMENT

'---4----1
'C.-..-..:1" OOOOOH

Figure 1. Memory Organization

Certain locations in memory are reserved for specific
CPU operations. (See Figure 2.) Locations from ad·
dresses FFFFOH through FFFFFH are reserved for
operations including a jump to the initial system initial·
ization routine. Following RESET, the CPU will always
begin execution at location FFFFOH where the jump
must be located. Locations OOOOOH through 003FFH are
reserved for interrupt operations. Four·byte pointers
consisting of a 16·bit segment address and a 16·bit off·
set address direct program flow to one of the 256 possi·
ble interrupt service routines. The pointer elements are
assumed to have been stored at their respective places
in reserved memory prior to the occurrence of inter·
rupts.

The minimum mode 8088 can be used with either a
multiplexed or demultiplexed bus. The multiplexed bus
configuration is compatible with the MCS·85™ multi·
plexed bus peripherals (8155, 8156, 8355, 8755A, and
8185). This configuration (See Figure 3) provides the
user with a minimum chip count system. This architec·
ture provides the 8088 processing power in a highly in·
tegrated form.
The demultiplexed mode requires one latch (for 64K ad·
dressability) or two latches (for a full megabyte of ad·
dressing). A third latch can be used for buffering if the
address bus loading requires it. An 8286 or 8287 trans·
ceiver can also be used if data bus buffering is required.
(See Figure 4.) The 8088 provides DEN and DT/R to con·
trol the transceiver, and ALE to latch the addresses.
This configuration of the minimum mode provides the
standard demultiplexed bus structure with heavy bus
buffering and relaxed bus timing requirements.
The maximum mode employs the 8288 bus controller.
(See Figure 5.) The 8288 decodes status lines SO, Sf,
and S2, and provides the system with all bus control
signals. Moving the bus control to the 8288 provides
better source and sink current capability to the control
lines, and frees the 8088 pins for extended large system
features. Hardware lock, queue status, and two request!
grant interfaces are provided by the 8088 in maximum
mode. These features allow co·processors in local bus
and remote bus configurations.

B-25

8088

/'

/'

Vss

Vee

I I

5--

POR:~

CE

POR~~

WR
RD

a155
ALE
DATA

"'-

PORT~
C

(61

ADDR
IN10 IVl

TIMER
OUT

RESET

"As-A19

r---

lOW

ADDR

RD

,----

ADo -

AD7

ADDR/DATA

ClK

~T

"-

rD1
X,

r-

RESET

X2
ClK

READY

RES

-

I

A
1/

A

A S10

~

8355 '8755A
DATA
ADDR

-Vee

ALi

-

RI)

-

We

-

101M

PORT

CE

READY

MN/MX
VCC

ALE

s-~

t=

8088

,--

~

-"--

- -

IO,'M

RESET

PORT
B

lOR

-

!!It

8284

--

RESET

~c

Vss Vee V DD PROG

GND

WR
RD

CE,

8185

ALE

\--

CS, GEL

\--

Ag,Ag

/

ADo)

I 1

Vs~

Figure 3. Multiplexed Bus Configuration

B-26

~

Vee

8088

D

Vee

~ m 82"

CLOCK
GENERATOR

ROY

I
ONO

eLK

"'N/M'X

READY

101M

AESET

ftlj

Vee

IVA
8088
CPU INTA

L_______

----------lINT

¢=

IRO-7

Figure 4. Demultiplexed Bus Configuration

T
r OE~t~~~OR
R3

I

ONO

ROY

sof-------lsu

r---7.M~N'~MX~ __ GNO
eLK
READY

~

RESET

r--ce~LK~M~Ro~e1--------------~----~------_

s;-

5;"

S;

52

[

MWTC
AMWC

.-e=::':

A~~-=-~~;l!'-o.N'"Od±--: ~~B

f----------.---------t-If--------II-----.---N C

e::=:;l~RA:~~~r---N-------,--Ji:------ I
8288

IORC

e

Li •

- - - - - t----++

t-+--I

c=::=;::::;=~~==~AOi1iO'ffiRE~s§:s=~1~==;--;===

L l
_

_~

rln!-l~

INT

¢===IRO-7
Figure 5. Fully Buffered System Using Bus Controller

B-27

8088
/).

tion, the bus can be demultiple"~1rCt
a single address latch if a standaf~fh~
bus is desired for the system.
~-1/'''/f'

Bus Operation
The SOSS address/data bus is broken into three parts the lower eight address/data bits (ADO-AD?), the middle
eight address bits (AS-A15), and the upper four address
bits (A16-A19). The address/data bits and the highest
four address bits are time multiplexed. This technique
provides the most efficient use of pins on the processor, permitting the use of a standard 40 lead package.
The middle eight address bits are not multiplexed, i.e.
they remain valid throughout each bus cycle. In add i-

--------(4+NWAIT)::TCY

1--------t4+NwAITI=TCy
T,

1

I

T2

'J,~/Ot'f

Each processor bus cycle consists of at least four
cycles. These are referred to as T1. T2, T3, and T4.
Figure 6). The address is emitted from the processor
during T1 and data transfer occurs on the bus during T3
and T4. T2 is used primarily for changing the direction of
the bus during read operations. In the event that a "NOT
READY" indication is given by the addressed device,

T3

TWAIT

T1

I

T2

I

T3

I

TWAIT

ClK

ALE

n

\
~

JUST PRIOR TOT4

mJ

~~

_ _ _ _ _S_'-_S3_ _ _ _ _ _

~,-

______
S'_-S_3_ _ _ _ _

A_15.A' _ _ _

~

~\\~\'

/RE~DV

\. _ _ _ _ _

READY

\~\~~-

e

><=

X'---___

A15._A,_ _ _ _ _ _

ADDR/DATA

__
DA_T_A_O_UT_'D_7_.D_OI_ _

~~-~

'.~\.:---"l~DV

I

\\........:.-.

.

WAIT

DTIR

\'-->C

\I...-..._--1-/...J..J..JUJ/;.u.u..JI

. =*_______

ADDRISTATUS

GOES INACTIVE IN THE STATE

1\
1\
---.l
\'---____________
~ ____ -.~'-----------+"""'\ _ _I
L

WAIT

\1...-1---1--+----'/
I

\

'I

\~------'/

I--MEMORV ACCESS TIME---_I

\~_---J/
Figure 6_ Basic System Timing

B-28

8088
t:~~;!

"wait" states (Tw) are inserted between T3 and T4. Each
inserted "wait" state is of the same duration as a ClK
cycle. Periods can occur between 8088 driven bus
cycles. These are referred to as "idle" states (Ti), or inac·
tive ClK cycles. The processor uses these cycles for in·
ternal housekeeping.
During T1 of any bus cycle, the ALE (address latch
enable) signal is emitted (by either the processor or the
8288 bus controller, depending on the MN/IVlX strap). At
the trailing edge of this pulse, a valid address and cer·
tain status information for the cycle may be latched.
Status bits SO, 51, and S2 are used by the bus controller,
in maximum mode, to identify the type of bus transac·
tion according to the following table:

52

o (low)
0
0
0
1 (High)
1
1

51

SO

0
0

0
1
0
1
0

1
0
0

0

Interrupt Acknowledge
Read 1/0
Write 1/0
Halt
Instruction fetch
Read data from memory
Write data to memory
Passive (no bus cycle)

Status bits S3 through S6 are multiplexed wiih high
order address bits and are therefore valid during T2
through T4. S3 and S4 indicate which segment register
was used for this bus cycle in forming the address ac·
cording to the following table:

S4

S3

o (low)
o

o

1 (High)
1

1

o

Alternate data (Extra Segment)
Stack
Code or none
Data

S5 is a reflection of the PSW interrupt enable bit. S6 is
always equal to O.

I/O Addressing
In the 8088, 1/0 operations can address up to a maxi·
mum .of 64K 1/0 registers. The 1/0 address appears in the
same format as the memory address on bus lines
A15-AO. The address lines A19-A16 are zero in 1/0
operations. The variable 1/0 instructions, which use
register DX as a pointer, have full address capability,
while the direct 1/0 instructions directly address one or
two of the 256 1/0 byte locations in page 0 of the 1/0 ad·
dress space. 1/0 ports are addressed in the same man·
ner as memory locations.
Designers familiar with the 8085 or upgrading an 8085
design should note that the 8085 addresses 1/0 with an
8·bit address on both halves of the 16·bit address bus.
The 8088 uses a full 16·bit address on its lower 16 ad·
dress lines.

:,

EXTERNAL INTERFACE'·\~.>
Processor Reset and Initializatiorl' '~//,~, ,~<;t",
Processor initialization or start up is accompli~'h'6~'iNlt!;J,

activation (HIGH) of the RESET pin. The 8088 RES~'r'ji'
required to be HIGH for greater than four clock cycles'.
The 8088 will terminate operations on the high·going
edge of RESET and will remain dormant as long as
RESET is HIGH. The low·going transition of RESET trig·
gers an internal reset sequence for approximately 7
clock cycles. After this interval the 8088 operates nor·
mally, beginning with the instruction in absolute loca·
tion FFFFOH. (See Figure 2.) The RESET input is inter·
nally synchronized to the processor clock. At initializa·
tion, the HIGH to lOW transition of RESET must occur
no sooner than 50 p's after power up, to allow complete
initialization of the 8088.
If INTR is asserted sooner than nine clock cycles after
the end of RESET, the processor may execute one in·
struction before responding to the interrupt.
All 3·state outputs float to 3·state OFF during RESET.
Status is active in the idle state for the first clock after
RESET becomes active and then floats to 3·state OFF.

Interrupt Operations
Interrupt operations fall into two classes; software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in
the instruction set description found in Chapter 2 of the
8086 Family User's Manuai. Hardware interrupts can be
classified as non·maskable or maskable.
Interrupts result in a transfer of control to a new pro·
gram location. A 256 element table containing address
pointers to the interrupt service program locations
resides in absolute locations 0 through 3FFH (see Fig·
ure 2), which are reserved for this purpose. Each ele·
ment in the table is 4 bytes.in size and corresponds to
an interrupt "type". An interrupting device supplies an
8·bit type number, during the interrupt acknowledge se·
quence, which is used to vector through the appropriate
element to the new interrupt service program location.

Non·Maskable Interrupt (NMI)
The processor provides a single non·maskable interrupt
(NMI) pin which has higher priority than the maskable in·
terrupt request (INTR) pin. A typical use would be to actio
vate a power failure routine. The NMI is edge·triggered
on a lOW to HIGH transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. Any higher going transition
of NMI is latched on·chip and will be serviced at the end
of the current instruction or between whole moves (2
bytes in the case of word moves) of a block type instruc·
tion. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no
specification on the occurrence of the low·going edge; it
may occur before, during, or after the servicing of NMI.
Another high·going edge triggers another response if it

B-29

8088
j)~

occurs after the start of the NMI procedure. The signal
must be free of logical spikes in general and be free of
bounces on the low·going edge to avoid triggering ex·
traneous responses.

Maskable Interrupt (INTR)

ALE

I

T2

T3

"P!;;i

The LOCK status information is provided by the proc·
essor when consecutive bus cycles are required during
the execution of an instruction. This allows the proc·
essor to perform read/modify/write operations on
memory (via the "exchange register with memory"
instruction), without another system bus master receiv·
ing intervening memory cycles. This is useful in multi·
processor system configurations to accomplish "test
and set lock" operations. The ~ signal is activated
(LOW) in the clock cycle following decoding of the
LOCK prefix instruction. It is deactivated at the end of
the last bus cycle of the instruction following the LOCK
prefix. While LOCK is active, all interrupts are masked
and a request on a RQ/GT pin will be recorded, and then
honored at the end of the LOCK.

External Synchronization via TEST
As an alternative to interrupts, the 8088 provides a
single software·testable input pin (TEST). This input is
utilized by executing a WAIT instruction. The single

T..

T1

I

T2

T,

J'\\...--_-------'n\........-_ _
\\...--_---------/

ADo-AD-,

'~()I

Read/Modify/Write (Semaphore) Operations
via LOCK

During the response sequence (See Figure 7), the proc·
essor executes two successive (back to back) interrupt
acknowledge cycles. The 8088 emits the LOCK signal
(maximum mode only) from T2 of the first bus cycle until
T2 of the second. A local bus "hold" request will not be
honored until the end of the second bus cycle. In the
second bus cycle, a byte is fetched from the external in·
terrupt system (e.g., 8259A PIC) which identifies the
source (type) of the interrupt. This byte is multiplied by
four and used as a pOinter into the interrupt vector
lookup table. An INTR signal left HIGH will be continual·
Iy responded to within the limitations of the enable bit
and sample period. The interrupt return instruction in·
cludes a flags pop which returns the status of the
original interrupt enable bit when it restores the flags.

T1

. ''''-

'i'trl,,:'''I!;n

When a software HALT instruction ils~~
processor indicates that it is entering the H,8;
one of two ways, depending upon which m
strapped. In minimum mode, the processor issues A
delayed by one clock cycle, to allow the system to latch
the halt status. Halt status is available on 10/M, DT/R,
and SSO .. ln maximum mode, the processor issues ap·
propriate HALT status on S2, S 1, and SO, and the 8288
bus controller issues one ALE. The 8088 will not leave
the HALT state when a local bus hold is entered while in
HALT. In this case, the processor reissues the HALT in·
dicator at the end of the local bus hold. An interrupt reo
quest or RESET will force the 8088 out of the HALT
state.

The 8088 provides a single interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The in·
terrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high·going
edge of CLK. To be responded to, INTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a
block type instruction. During interrupt response se·
quence, further interrupts are disabled. The enable bit is
reset as 19art of the response to any interrupt (INTR,
NMI, software interrupt, or single step), although the
FLAGS register which is automatically pushed onto the
stack reflects the state of the processor prior to the in·
terrupt. Until the old FLAGS register is restored, the
enable bit will be zero unless specifically set by an in·
struction.

I

'0".

~""J!;

HALT

FLOAT

Figure 7. Interrupt Acknowledge Sequence

B-30

8088
;~

vI

Medium .~~~

WAIT instruction is repeatedly executed until the TEST
input goes active (LOW). The execution of WAIT does
not consume bus cycles once the queue is full.

Bus Timing -

If a local bus request occurs during WAIT execution, the
8088 3·states all output drivers. If interrupts are enabled,
the 8088 will recognize interrupts and process them.
The WAIT instruction is then refetched, and reexecuted.

For medium complexity systems, the MN/Mxprl:flS'\oli1J;J:
nected to GND and the 8288 bus controller is adCi'itd;tf5',)
the system, as well as an 8282/8283 latch for latching
the system address, and an 8286/8287 transceiver to
allow for bus loading greater than the 8088 is capable of
handling. Signals ALE, DEN, and DT/A" are generated by
the 8288 instead of the processor in this configuration,
although their timing remains relatively the same. The
8088 status outputs (52', S1, and SO) provide type of
cycle information and become 8288 inputs. This bus
cycle information specifies read (code, data, or 1/0),
write (data or I/O), interrupt acknowledge, or software
halt. The 8288 thus issues control signals specifying
memory read or write, I/O read or write, or interrupt
acknowledge. The 8288 provides two types of write
strobes, normal and advanced, to be applied as required.
The normal write strobes have data valid at the leading
edge of write. The advanced write strobes have the
same timing as read strobes, and hence, data is not
valid at the leading edge of write. The 8286/8287 transceiver receives the usual T and OE inputs from the
8288's DT/R and DEN outputs.

(See Figure 8.)
\,"~" '~\iP&

Basic System Timing
In minimum mode, the MN/MX pin is strapped to Vee
and the processor emits bus control signals compatible
with the 8085 bus structure. In maximum mode, the
MN/MX pin is strapped to GND and the processor emits
coded status information which the 8288 bus controller
uses to generate MULTIBUS compatible bus control
signals.

System Timing -

Minimum System

(See Figure 6.)
The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal. The trailing (lOW going)
edge of this signal is used to latch the address information, which is valid on the address/data bus (ADO-AD7)
at this time, into the 8282/8283 latch. Address lines A8
through A 15 do not need to be latched because they reo
main valid throughout the bus cycle. From T1 to T4 the
10/M signal indicates a memory or I/O operation. At T2
the address is removed from the address/data bus and
the bus goes to a high impedance state. The read con·
trol signal is also asserted at T2. The read (RD) signal
causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will
be available on the bus and the addressed device will
drive the READY line HIGH. When the processor returns
the read signal to a HIGH level, the addressed device
will again 3·state its bus drivers. If a transceiver
(8286/8287) is required to buffer the 8088 local bus,
signals DT/R and DEN are provided by the 8088.
A write cycle also begins with the assertion of ALE and
the emission of the address. The 101M signal is again
asserted to indicate a memory or I/O write operation. In
T2, immediately following the address emission, the
processor emits the data to be written into the addressed location. This data remains valid until at least
the middle of T4. During T2, T3, and Tw , the processor
asserts the write control signal. The write (WR) signal
becomes active at the beginning of T2, as opposed to
the read, which is delayed somewhat into T2 to provide
time for the bus to float.
The basic difference between the interrupt acknowl·
edge cycle and a read cycle is that the interrupt
acknowledge (INTA) signal is asserted in place of the
read (RD) Signal and the address bus is floated. (See
Figure 7.) In the second of two successive INTA cycles,
a byte of information is read from the data bus, as sup·
plied by the interrupt system logic (i.e. 8259A priority interrupt controller). This byte identifies the source (type)
of the interrupt. It is multiplied by four and used as a
pOinter into the interrupt vector lookup table, as de·
scribed earlier.

B-31

The pointer into the interrupt vector table, which is
passed during the second INTA cycle, can derive from
an 8259A located on either the local bus or the system
bus. If the master 8289A priority interrupt controller is
positioned on the local bus, a TTL gate is required to
disable the 8286/8287 transceiver when reading from the
master 8259A during the interrupt acknowledge se·
quence and software "poll".

The 8088 Compared to the 8086
The 8088 CPU is an 8-bit processor designed around the
8086 internal structure. Most internal functions of the
8088 are identical to the equivalent 8086 functions. The
8088 handles the external bus the same way the 8086
does with the distinction of handling only 8 bits at a
time. Sixteen-bit operands are fetched or written in two
consecutive bus cycles. Both processors will appear
identical to the software engineer, with the exception of
execution time. The internal register structure is identical and all instructions have the same end result. The
differenceS between the 8088 and 8086 are outlined
below. The engineer who is unfamiliar with the 8086 is
referred to the 8086 Family User's Manual, Chapters 2
and 4, for function description and instruction set
information.
I nternally, there are three differences between the 8088
and the 8086. All changes are related to the 8-bit bus i nterface.
• The queue length is 4 bytes in the 8088, whereas the
8086 queue contains 6 bytes, or three words. The
queue was shortened to prevent overuse of the bus by
the BIU when prefetching instructions. This was required because of the additional time necessary to
fetch instructions 8 bits at a time.

8088
ll#I';:;:Of},-

l;

• To further optimize the queue, the prefetching algorithm was changed. The 8088 BIU will fetch a new instruction to load into the queue each time there is a 1
byte hole (space available) in the queue. The 8086
waits until a 2-byte space is available.

The 8088 and 8086 are completery9s~
by virture of their identical executio
that is system dependent may not be conir~
ferable, but software that is not system deperitre
operate equally as well on an 8088 or an 8086 .

• The internal execution time of the instruction set is
affected by the 8-bit interface. All 16-bit fetches and
writes from/to memory take an additional four clock
cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs
when a series of simple operations occur. When the
more sophisticated instructions of the 8088 are being
used, the queue has time to fill and the execution proceeds as fast as the execution unit will allow.

The hardware interface of the 8088 contai ns the major
differences between the two CPUs. The pin assignments are nearly identical, however, with the following
functional changes:

T,
elK

~

• A8-A 15 - These pins are only address outputs on the
8088. These address lines are latched internally and
remain valid throughout a bus cycle in a manner
similar to the 8085 upper address lines.

.I

T,

T,

T2

,I---

J

aSl. aso
8088

II I I I

52, 51. so

S6- S3

A19-A16

A19/S6-A161S3

\~-=-====
,-

!

'\

ALE

ROY

8284

READY

8088

8288

j

--

i
AD7 -ADO

8088

A7

AO

DATA IN

./

A15-A8

A15-AB

!
RO

OTIR

8288

I
I

'\

MRoe

DEN

Figure 8_ Medium Complexity System Timing

B-32

~

8088
JJlj,. fCe:. t.
reside on the 8088 local bus. ~J;}o
T2. T3 and Tw of any read cycle, ana
main HIGH in T2 until the 8088 local bu

• BHE has no meaning on the 8088 and has been eliminated.
• SSO provides the SO status information in the minimum mode. This output occurs on pin 34 in minimum
mode only. DT/R, 101M, and SSO provide the complete
bus status in minimum mode.

READY (Input)

• 101M has been inverted to be compatible with the
MCS-85 bus structure.

READY is the acknowledgement from the addressed
memory or 1/0 device that it will complete the data transfer. The ROY signal from memory or 110 is synchronized
by the 8284 clock generator to form READY. This signal
is active HIGH.

• ALE is delayed by one clock cycle in the minimum
mode when entering HALT, to allow the status to be
latched with ALE.

8088 FUNCTIONAL PIN DEFINITIONS

INTR (Input)
Interrupt request is a level triggered input which is
sampled during the last clock cycle of each instruction
to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to
via an interrupt vector lookup table located in system
memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

The following pin function descriptions are for 8088
systems in either minimum or maximum mode. The
"local bus" in these descriptions is the direct multiplexed bus interface connection to the 8088 (without
regard to additional bus buffers).

AD7-ADO (Input/Output, 3·State)
These lines constitute the time multiplexed memoryllO
address (T1) and data (T2, T3, Tw, and T4) bus. These
lines are active HIGH and float to 3-state OFF during interrupt acknowledge and local bus "hold acknowledge"

TEST (Input)
The TEST input is examined by the "wait for test" instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an "idle" state.
This input is synchronized internally during each clock
cycle on the leading edge of CLK.

A15-A8 (Output, 3-State)
These lines provide address bits 8 through 15 for the
entire bus cycle (T1-T4). These lines do not have to be
latched by ALE to remain valid. A15-A8 are active HIGH
and float to 3-state OFF during interrupt acknowledge
and local bus "hold acknowledge".

A19/S6, A18/S5, A17/S4, A16/S3 (Output,
3·State)
During T1, these are the four most significant address
lines for memory operations_ During 1/0 operations,
these lines are LOW. During memory and 1/0 operations,
status information is available on these lines during
T2, T3, Tw, and T4. S6 is always low. The status of the
interrupt enable flag bit (S5) is updated at the beginning
of each clock cycle. S4 and 53 are encoded as follows:
54

o (LOW)
0
1 (HIGH)
1
56 is 0 (LOW)

NMI (Input)
Non-maskable interrupt is an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via
an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the
end of the current instruction. This input is internally
synchronized.

RESET (Input)
RESET causes the processor to immediately terminate
its present activity. The signal must be active HIGH for
at least four clock cycles. It restarts execution, as
described in the instruction set description, when
RESET returns LOW. RESET is internally synchronized.

S3
0
1
0

Alternate Data
Stack
Code or None
Data

elK (Input)

This information indicates which segment register is
presently being used for data accessing.

The clock provides the basic timing for the processor
and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.

These lines float to 3-state OFF during local bus "hold
acknowledge"

Vee
Vee is the

RD (Output, 3·State)
Read strobe indicates that the processor is performing a
memory or 1/0 read cycle, depending on the state of the
101M pin or 52. This signal is used to read devices which

+ 5V

± 10% power supply pin.

GND
GND are the ground pins.

B-33

8088
P#

MINIMUM MODE PIN DESCRIPTIONS
The following pin function descriptions are for the 8088
minimum mode (i.e., MN/MX = Vee). Only the pin functions which are unique to minimum mode are described;
all other pin functions are as described above.

IO/M (Output, 3-State)
This status line is an inverted maximum mode 52. It is
used to distinguish a memory access from an 1/0 access. 10iM becomes valid in the T4 preceding a bus
cycle and remains valid until the final T4 of the cycle
(1/0 = HIGH, M = LOW). 10iM floats to 3-state OFF in
local bus "hold acknowledge".

suance of HLDA, the processor
and control lines. After HOLD is dete
the processor lowers HLDA, and when
needs to run another cycle, it will again dri
bus and control lines.

SSO
This status line is logically equivalent to SO in the maximum mode. The combination of 550, 101M and DTIR
allows the system to completely decode the current bus
cycle status.

WR (Output, 3-State)

INTA (Output, 3-State)

ALE (Output)
Address latch enable (ALE) is provided by the processor
to latch the address into the 8282/8283 address latch. It
is a HIGH pulse active during clock low of T1 of any bus
cycle. Note that ALE is never floated.

DTiR (Output,

1

1
0
0

0
1
0
1
0
1
0

Interrupt Acknowledge
Read 110 port
Write 110 port
Halt
Code access
Read memory
Write memory
Passive

The following pin function descriptions are for the 8088,
8228 system in maximum mode (i.e., MNIMX = GND.
Only the pin functions which are unique to maximum
mode are described; all other pin functions are as
described above.

S2, S1, SO (Output, 3-State)
These status lines are encoded as follows:

52

51

50

o (LOW)

0
0
1
1
0
0

0
1
0
1
0
0
0

0
0
0
1 (HIGH)
1

=

Data enable is provided as an output enable for the
828618287 in a minimum system which uses the transceiver. DEN is active LOW during each memory and 110
access, and for INTA cycles. For a read or INTA cycle, it
is active from the middle of T2 until the middle of T4,
while for a write cycle, it is active from the beginning of
T2 until the middle of T4. DEN floats to 3-state OFF during local bus "hold acknowledge".

0
0

MAXIMUM MODE PIN DESCRIPTICNS

3-State)

DEN (Output, 3-State)

550

1 (HIGH)
1

0
0
0

Data transmitlreceive is needed in a minimum system
that desires to use an 8286/8287 data bus transceiver. It
is used to control the direction of data flow through the
transceiver. Logically, DTiA is equivalent to 51 in the
maximum mode, and its timing is the same as for 101M
(T HIGH, R LOW). This signal floats to 3-state OFF in
local "hold acknowledge".

=

oTiA"

o (LOW)

Write strobe indicates that the processor is performing
a write memory or write 1/0 cycle, depending on the
state of the 10iM signal. WR is active for T2, T3, and Tw
of any write cycle. It is active LOW, and floats to 3-state
OFF in local bus "hold acknowledge".

INTA is used as a read strobe for interrupt acknowledge
cycles. It is active LOW during T2, T3, and Tw of each interrupt acknowledge cycle. I NTA floats to 3-state OFF in
"hold acknowledge".

101M

Interrupt Acknowledge
Read 110 port
Write 110 port
Halt
Code access
Read memory
Write memory
Passive

Status is active during clock high of T4, T1, and T2, and
is returned to the passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is used by the
8288 bus controller to generate all memory and 110 access control signals. Any change by 52, ST, or SO during
T4 is used to indicate the beginning of a bus cycle, and
the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle.

HOLD (Input), HLDA (Output)

These signals float to 3-state OFF during "hold
acknowledge". During the first clock cycle after RESET
becomes active, these signals are active HIGH. After
this first clock, they float to 3-state OFF.

HOLD indicates that another master is requesting a
local bus "hold". To be acknowledged, HOLD must be
active HIGH. The processor receiving the "hold" request will issue HLDA (HIGH) as an acknowledgement,
in the middle of T4 or TI. Simultaneous with the is-

The requestlgrant pins are used by other local bus
masters to force the processor to release the local bus
at the end of the processor's current bus cycle. Each pin

RQ/GTO, RQ/GT1 (Input/Output)

B-34

8088
is bidirectional with RQ/GTO having higher priority than
RQ/GT1. RQ/GT has an internal pull-up resistor, so may
be left unconnected. The request/grant sequence is as
follows (See Figure 6):
1. A pulse of one ClK wide from another local bus
master indicates a local bus request ("hold") to the
8088 (pulse 1).

2. During the CPU's next T4 or TI, a pulse one clock
wide from the 8088 to the requesting master (pulse 2),
indicates that the 8088 has allowed the local bus to
float and that it will enter the "hold acknowledge"
state at the next ClK. The CPU's bus interface unit is
disconnected logically from the local bus during
"hold acknowledge".
3. A pulse one ClK wide from the requesting master indicates to the 8088 (pulse 3) that the "hold" request
is about to end and that the 8088 can reclaim the
local bus at the next ClK. The CPU then enters T4.
Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle ClK
cycle after each bus exchange. Pulses are active lOW.

LOCK (Output, 3·5tate)
The lOCK output indicates
masters are not to gain control of the system
lOCK is active (lOW). The lOCK Signal is act iva
the "lOCK" prefix instruction and remains active un
the completion of the next instruction. This signal is active lOW, and floats to 3-state off in "hold acknowledge".

a51, a50 (Output)
QS1 and QSO provide status to allow external tracking of
the internal 8088 instruction queue.
QS1

QSO

o (lOW)
o

o

1 (HIGH)
1

1

o

No operation
First byte of opcode from queue
Empty the queue
Subsequent byte from queue

The queue status is valid during the ClK cycle after
which the queue operation is performed.

PIN 34 (Output)
Pin 34 is always high in the maximum mode.

B-35

8088
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O·C to 70·C
Storage Temperature ............. -65·C to + 150·C
Voltage on Any Pin with
Respect to Ground .................. - 0.3 to + 7V
Power Dissipation ........................ 2.5 Watt

Ratings" may cause permanent damage to the device.
rating only and functional operation of the device at these or
conditions above those indicated in the operational sections
specification is not implied. Exposure to absolute maximum rating con·
ditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS
8088: TA=0·Ct070·C, V.cc=5V ±10%
Symbol

Parameter

Min.

V IL

Input Low Voltage

-0.5

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Icc

Power Supply Current

Max.

Units

+0.8

V

Vcc + 0.5

V

0.45
2.4

V

10L = 2.0 mA

V

IOH = 4OOl'A

340

mA

III

Input Leakage Current

± 10

I'A

ILO

Output Leakage Current

± 10

I'A

+0.6

V

t---.-------- ------_._------

.-

Test Conditions

VIN = Vcc
0.45V... ----------" VOUT " Vcc

.~

- 0.5

--"--

vCL

Clock Input Low Voltage

VCH

Clock Input High Voltage

Vcc + 1.0

V

C IN

Capacitance of Input Buffer
(All input except
ADo-AD? RQ/GT)

10

pF

fc = 1 MHz

CIO

Capacitance of I/O Buffer
(ADo-AD? RQ/GT)

20

pF

fc = 1 MHz

3.9

-

B-36

---

8088

~~~t~~~~

A.C. CHARACTERISTICS
8088:
8088

TA=O°C to 70°C, Vcc=5V± 10%
MINIMUM COMPLEXITY SYSTEM TIMING REQUIREMENTS

Symbol

Parameter

Min.

-

Max.

Units

500

ns

Test Conditions

TCLCL

eLK Cycle Period

TCLCH

elK Low Time

(2hTCLCL)-15

TCHCL

CLK High Time

('hTCLCL)+ 2

TCH1CH2

elK Rise Time

10

ns

From 1.0V to 3.5V

TCL2CLI

CLK Fall Time

10

ns

From 3.5V to 1.0V

TDVCL

Data In Setup Time

200

ns
ns

30

ns

TCLDX

Data In Hold Time

10

ns

TR1VCL

ROY Setup Time into 8284 (See Notes 1, 2)

35

ns

TCLR1X

ROY Hold Time Into 8284 (See Notes 1, 2)

0

ns

TRYHCH

READY Setup Time Into 8088

(2iJTCLCL)-15

ns

TCHRYX

READY Hold Time Into 8088

30

ns

TRYLCL

READY Inactive to eLK (See Note 3)

-8

THVCH

HOLD Setup Time

35

TINVCH

INTR, NMI. TEST Setup Time (See Note 2)

30

TIMING RESPONSES

,

Symbol

.-- ..
..- Min.
' -f - - - - - - - - -~--

Parameter

--

TCLAV

Address Valid Delay

TCLAX

Address Hold Time

.-----

-_

I

ns

L

ns
ns

--~~--

15

--------

.

I

Max

Units

110

ns

10

Test Conditions

ns

--

TCLAZ

Address Float Delay

- - - - -

.-

TLHLL

.------~--

..- . - - - - - f--.

ALE Width

~

TCLLH

ALE Acllve Delay

85

---

TCLDV

--~------

.. - - - - - - -

._--

Data Valid Delay

TCHCTV

-----TCVCTX

-----

ns

.-~---~

Data Hold "time

.. -

10

ns

-

110

ns
ns

,,----

Data Hold Time After WR

TCLCH-30

ns

- -r - - - - - 110
ns
-- -_.- -----

Control Active Delay 1

10

Control Active Delay 2

10

110

ns

Control Inactive Delay

10

110

ns

c----

" - r---~------ - - "

TAZRL

Address Float to READ Active

TCLRL

RD Active Delay

10

165

TCLRH

RD Inactive Delay

10

150

ns

TRHAV~

RD Inactive 10 Next Address Active

TCLHAV

HLDA Valid Delay

160

ns

---_._--_.

-

_.

1---

TCHCL-l0
10

.--~

._.

TCVCTV

ns

c--------

~-.-.---.

Address Hold Time to ALE Inactive

TWHDX

ns

- - r---'-~80

----

ALE Inactive Delay

TLLAX

-------

f-----

. -

._._-----

-----

ns

80

TCLCH-20

.. - .

TCHLL

TCHDX

TCLAX

0

f---.

ns

f---'-~--

TCLCL-45
10

.c-.

ns

-- - - - ns

TRLRH

RD Width

2TCLCL-75

ns

TWLWH

WR Width

2TCLCL-60

ns

TAVAL

Address Valid to ALE Low

TCLCH-60

ns

NOTES: 1. Signal at 8284 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next ClK.
3. Applies onty to T2 state (8 ns into T3 state).

B-37

CL = 20·100 pF for
all 8088 Outputs
in addition to
internal loads

8088

CLK (8284 Output)

Tw

T,

.'"~~ ::HC~~ L-Ir'Lvic
-

101M,

T,

T,

T1

_TCLCH_

TCHCL

TCHCTV

SSO

A1S-

TCLAV-

TCLLH-

f

-

As (Float during

INTA)

/

~TDV

TCLAXA19-A16

TCHDX--

1\
I-- T~LAX

TLH~L--=:::

r--

l ___

ALE

- vr~~
v",:.:.::, _~ ~~~~*'~ :~~ ~~
_TR1VCl

TCHLL-I
-TAVAL-

RDY (8284 tnput)
SEE NOTES

'\

\

-

TRYLCL-

READY (8088 tnput)

- h

I

f

!-TCLR1X

-

1
I

~TCLAZ

A7- AO

AD7-ADo

TAZRL-

=~TCHCTV

(WR, INTA=VOH)

TDVCl_ !-TCLDX-

;:{

READ CYCLE

I

TCLRL

DTfA
TCVCTV-

Figure 9. 8088 Bus Timing -

B-38

f

-TCHRYX

-

TRYHCH-

-

(NOTE 1)

-

57-53

DATA tN
FLOA:J'
TCLRH-

I~

-TRHAV

~
TCHCTV

TRLRH

I

TCVCTX-

Minimum Mode System

I

8088

~

T,

elK (8284 Output)

I

I

TCLAVDATA OUT

AD7-ADo

TCVCTX

WRITE CYCLE
NOTE 1

__+-____~-------T-C-V-C-TV---~~I------_T------TCLAZ

AD7-ADO

FlOAT
TCHCTV

DTiA

INTA CYCLE

TCVCTV-

NOTES 1,3

(RD,

WR=VOH)

SOFTWARE HALT - (DEN:
Vodm.WR,INTA DT/A = VOH:

AD7 - ADo

~)k'
TCLAV=:i
NOTES:

INVALID ADDRESS

'I~~-

1. ALL SIGNALS SWITCH BETWEEN VOH ANO VOl UNLESS OTHERWISE
SPECIFIED.

2. ROY IS SAMPLED NEAR THE END OF 12, T3, Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.
3. TWO INTA CYCLES RUN BACK·TO·BACK. THE 80B8 LOCAL ADDRIDATA
BUS IS FLOATING DURING BOTH INTA CYCLES. CONTROL SIGNALS
ARE SHOWN FOR THE SECOND INTA CYCLE.
4. SIGNALS AT 8284 ARE SHOWN FOR REFERENCE ONLY.
5. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE
NOTED.

Figure 10. 8088 Bus Timing -

Minimum Mode System (cont.)

B-39

8088
8088 MAX MODE SYSTEM (USING 8288 BUS CONTROLLER)
TIMING REQUIREMENTS
Symbol

+- ~~:.

Parameter

Max.

TClCl

eLK Cycle Period

TClCH

elK Low Time

TCHCl

ClK High Time

TCH1CH2
TCl2Cl1

ClK Rise Time
10
ns
From 1.0Vt03.5V
-----------------------+--------+-----+----T-~~~~-ClK Fall Time
10
ns
From 3.5V to 1.0V

500

('hTClCl)-15

ns

('hTClCl) + 2

ns

------.~------------------------------------r_--~----_r------r_--~

TDVCl

Data In Setup Time

30

ns

reLDX

Data In Hold Time

10

ns

TR1VCL

ROY Setup Time into 8284 (See Noles 1, 2)

35

ns

TClR1X

ROY Hold Time into 8284 (See Notes t. 2)

TRYHCH

READY Selup Time Inlo 8088

('hTClCl)-15

ns

TCHRYX

READY Hold Time Into 8088

30

ns

------_r---------------------------------+----------+------+-----+

TRYlCl
1--1N-V-C-H--

ns

READY Inaclive 10 ClK (See Nole 4)
-8
ns
Setup Ti me for Recognition (I NTR, N M-,.""Cr--=E=S=nc-(-S-e-e-N-o-le-2-)---t--------------t---------t--n-s---1
30

-T-G-V-C-H----+-~R=Q/GT

Selup Time

TCHGX

RQ Hold Time inlo 8086

TIMING RESPONSES
---~-i----

.__ .________ L_~

-,- -- P~~am~-t;;""---'--'------

ns

30

---------~i__=-----------------------------t---

_____

---Mi-;-~-I-----M-a-x-.---'---U-n-i-t-s---'---Te-s-t-C-on-d-j-tio-n-s-

TClMl

Command Active Delay (See Note 1)

10

35

TClMH

Command Inactive Delay (See Note 1)

10

35

.-----_._-

-.. --... - -.--. -.----.-.-----

TRYHSH

READY Active 10 Status Passive (See Note 3)

TCHSV

Sialus Active Delay

10

10

Address Valid Delay

15

------.---f-------.-----------------.---- TClAX

Address Hold Time

TClAZ

Address Float Delay

ns

. -- - - . - -

110

ns

130

ns

110

ns

---.-.------c--------

Status Inactive Delay

---- -.------------

----------- ----

_.-----

- . - - - I - -.-----..

---------- 1---.-.-- --.-.-----..- .. - - - - . - ..-TClAV

ns

--c------..t 10

------.--- -I- ---.
TCLSH

ns

-------

-- ---.-----t-------

- t - - - -.-.---.--

. -------- - - - - -

10

ns

-----j-------------r----------------j--------

TClAX

-----------------

80

ns

--f---------- f-------

TSVlH

Stalus Valid to ALE High (See Note 1)

15

TSVMCH

Slatus Valid to MCE High (See Note 1)

15

TCllH

ClK low to ALE Valid (See Note 1)

15

TClMCH

ClK low to MCE High (See Note 1)

15

ns

15

ns

110

ns

45

ns

-----------+----------------------

----- j-------------

ns

---j--------

- - - - - - - - - 1----- --------------------------- j - - - - - - - - - - - f---------

ns
ns

--------

-------------------------------- ----------+----------+----ALE Inactive Delay (See Note 1)
15
ns
-----------+-

TCHll
TClMCl

MCE Inactive Delay (See Note 1)

TCLOV

--

Data Valid Delay

15

TCHDX

--------------------- - - - t - - - - - - - - - - - - - j - - - - - - - - - - t - - - Data Hold Time
10
ns

TCVNV

Control Active Delay (See Note 1)

TCVNX

Control Inactive Delay (See Note 1)

TAZRl

Address Float to Read Active

o

TCLRl

RD Active Delay

10

165

ns

TClRH

RD Inactive Delay

10

150

ns

TRHAV

RD Inactive to Next Address Active

Cl = 20·100 pF for
all BOBB Outputs
in addition to
internal loads

------------------------1----------5

-------,~------t_------

10

45

ns
ns

-----------+---------- - - - - - - - - - - - - - - - - - - - - - t - - - - - - - ----------1-----

----------+--------- --------------------1----------+---------+--------..,
TClCL-45

ns

-----------1-----------------------------------1--------- - - - - - - - - - - - - - -

___
TC
__
H_D_Tl____
___
TC
__
H_D_T_H___

Direction Control Active Delay (See Note 1)

50

+__~D=i~re-c-ti-o-n-C-ontrollnac1ive Delay (See Note 1)

TClGL

ns

30____+-____
ns__--1

GT Active Delay

110

ns

----------+---=------------------------------t------ ---------------_r--------j

+-__ GT Inactive Delay

____
T_C_lG
__
H____
TRlRH

_________

NOTES: 1_
2.
3.
4_

~

ns

B5

RD Width

2TCLCL-75

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _L __ _ _ _ _ _ _ _ _

~

________

Signal at 8284 or 82B8 shown for reference only_
Setup requirement for asynchronous signal only to guarantee recognition at next elK.
Applies only to T3 and wait states.

Applies only to T2 state (8 ns into T3 state)_

B-40

~

ns

_ _ _ _ _ _ _L -_ _ _ _ _ _ _ _ _ _ _ _

8088

CLK

f------<

i-TCLSH

TCHSV

s"s"SO (EXCEPT HALT)

a
r-

!\.

\.._---\

CLOV
TCHOX~
I-,--+---+-+---+--+---+--,. r----

!-TCLAV
-----It-...,.
TCLAX -

----~~

A19-A16'

TSVLH~
_
TCLLH-,

57-53

~----

TCHLL

I

ALE (8288 OUTPUT)
SEE NOTE 5

1
ROV (8284 INPUT)

READ CYCLE

\------

TCLAV-I

AD7-ADO

Ao,-AO
TAZRL

RO
TCHOTL
I----+-+----TRLRH---+--~

TCLMH
8288 OUTPUTS
SeE NOTES 6,6

TCVNV-

TCVNX

Figure 11. 8088 Bus Timing -

Maximum Mode System (Using 8288)

B-41

,--

8088

1

ClK

2

"'~''IL---..J_'

r--'I ' - - '

13

r-\J~f'----If\.J//////

82.81, So (eXCEPT HAL1)
WRITE CYCLE

-

1-

TCLAV--

AD7-ADO
TCVNV--

14

.I-TC'DV

~

A

I--rCLSH

----_.

TCHDX-

t-

TCVNX-

t--

DATA

t-

DEN

8288 OUJPUTS
see NOTES 5,6

TClMH-

-TCLML

~

AMWC OR Alowe
______

~_r----_+----_+------_r------~~TClMl

INTA CYCLE
A1s-Aa
(SEE NOTES 3,4)

-

-TCLMH

I
FlOAT

RESERVED FOR
CASCADE ADDR

FLOAT

AD7-ADo

r-\

MCE!

}-

i>OEN
Dr/A"

\

8200 OUTPUTS

see NOTES 5,6

INTA

_ _ TCVNV

HALT - (DEN

{1MH

I

DEN
SOFTWARE

--

I

TCVNX--

=vOL;RD,JliIDC,TO"AC,MWfC,AMWC,TOWC,AiOWC,INTA,DT/R = VOH.
INVALID ADDRESS
. TeLAY
~

S;,s"Sij

jr---------"""'T\ -------

\'-------'
NOTES:

\.- -----

1. ALL SIGNALS SWITCH BeTweEN YOH AND VOL UNLESS OTHERWISE

SPECIFIED.
2. ROY IS SAMPLED NEAR THE END OF 12. T3. Tw TO DETERMINE IF Tw
MACHINES STATES ARE TO BE INSERTED.

3. CASCADE ADDRESS IS VALID BeTweEN FIRST AND SECOND INTA
CYCLES.
4. TWO INTA CYCLES RUN BACK·TO·SACK. THE 8088 LOCAL ADDRIDATA
BUS IS FlOATING DURING 80TH INTA CYCLES. CONTROL FOR
POINTER ADDRESS IS SHOWN FOR SECOND INTA CYCLE.
5. SIGNALS AT 8284 OR 8288 ARE SHOWN FOR REFERENCE ONLY.
6. THE ISSUANCE OF THE 8288 COMMAND AND CONTROL SIGNALS

(I.IlIIle, NIWTC, .uawe, tllRe, rowe, 1mlWl:, TfITA AND DENI lAGS THE

ACTIVE HIGH 8288 CEN.
7. ALL TIMING MEASUREMENTS ARE MADE AT 1.SV UNLESS OTHERWISE
NOTED.
8. STATUS INACTIVE IN STATE JUST PRIOR TO T4.

Figure 12. 8088 Bus Timing -

Maximum Mode System (Using 8288)

B-42

/ ---

TCHDTH

8088

CLK~

I.
INTR

-i

1--

TlNVC" ' ' ' ' ,,10 11

I ;,ge.I:=J{

:

TEST

NOTE:
1 SETUP REQUIREMENTS FOR ASYNCHRONOUS SIGNALS ONLY TO GUARANTEE RECOGNITION AT NEXT eLK

Figure 13. Asynchronous Signal Recognition

Figure 14. Bus Lock Signal Timing (Maximum Mode Only)

- Any eLK Cycle

-:. ---

'OClKCycle-i

~~

~

~

"---J

..-TCLGH

r-l"----,

~

I
1

PULSE ::>

8088Gl

Previous grant
Alt1S6A1~1~1!:

AD7-ADo

~:~

/ -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - /

eo"

F-----------------/

~----------~~ ~:.--C-OP-RO-CE-SS-O-R---------~
(SEE NOTE I)

NOTE: 1. THE COPROCESSOR MAY NOT DRIVE THE BUSSES OUTSIDE THE REGION
SHOWN WITHOUT RISKING CONTENTION.

Figure 15. Request/Grant Sequence Timing (Maximum Mode Only)

F--------~,~-8088

Figure 16. Hold/Hold Acknowledge Timing (Minimum Mode Only)

B-43

8088
8086/8088
INSTRUCTION SET SUMMARY
DATA TRANSFER
MOV Moy,;

76543210

7654321

n

76543210

Register/memory loilrom reg,ster

[Tfoo",

Immeolateto reglste'/memory

~,~~~-----data

Irnmedlate 10 register

Memory to accumulalOI

Accumulalo' to memory
Aeglster/mrmol'/ 10 segment register

DEC

76543210

0 d w~~

I

~~ala
~O 0 w
dddr-iow

I
I
li:OL1 0 0 0 1 w I
addr-Iow
I
Li::iE~_ t.,' ~ Imod 0 leg
i
Imoci [) leg

Segment register 10 reglster.'memo'y [i~01--1'oo

_l_~'~;~~~~

datal!wtj

add. high

J

I

~

Decrement

G'l1-'-'-'l;I~~-d~~O'

ReglSler

10 tOOl

NEG Change Sign

Q~.~_'_O_l_1

CMP

I

reg

Reql~!rr

~

merno1y and register

110 dw lmod

I, 00000 s w ! mod'
r00111'1~

OAS Dec,mal ildJust IQr s\Jbl,aCi

liii~

MUl Multiply iunslQred:

Segment register

IMUl integer multiply ISlgned',

POp

a a 0 1 1 II! mod a 0-0

Register/memory

11

Register

101011

Segme'ot register

XCHG

~

ffi]

'

I

reg

liiGi:iiiJ

I
I

7

data

data If

5

w 01

I

data II wI

~~Od' oliii:]
~~Od~

AAM ASC!I adlvSI lOr m·,J!llolv

Ll

OIV OlvldelJnSlgned\

II I : , 0 ' 1 w IIrT'Od \ 1 0 ' m

IOIV Integrrd'YlderSlgned'

~~~

~~O

I~

ASCII ad,usttor drvlde

CBW Cooyer! byte IG word
CWO Convert word TO double wo.'d

Exch.nge

rim

1 1 r'm

reg

liIiii::iiil__d'_la__ ~

AAS ASCII adlust tor subtract

POP

I

Irnmrdlate wllIl Mellr'lillator

Register

PUlh:

76 fI 4 3 2 ! 0

J

rim

w :mOdO 11

Register/memory

PUSH

r'm

Compare

1m media Ie With reqlsler 'memo,y

i/m~

76 fI 4 3 2 I 0

7654 3 2 1 0

Reglster.'memory

'GIO 100 IOOO()I01()J

I0 0 0 0

I () I 0 , 0 I

l

~_o_'_o_1

~GI:OOO
.~~

Register/memory with reg,s!e!
Reglsler with accumulator

IN=lopu!irom
F,~ed

port

11 1 1 00 1 Ow ]

port

11 1 100 1 1 w ]

port

Variable port

LOGIC
OUT'O Output 10
FI~ed

port

Variable port

IlAT- Translate byte to AL
LEA=Load EA!o register

.aT
SHL:SAl Shltllog,cal arithmeTIC Irtl

1

I
I

1

I mod

'~g

]mod

reg:iii]

RllR Rotaterrght

reg

RCL ROlate through carry Ilag left

tl110 11 1 w

11 1 a 1 a 11
110 0 a 1 10

lDS=Load pOinter to OS

l i l a 0 0101

LES=load pOll1ter to ES

111000100 ImOd

LANF"load AH with Hags

1,00 1 11 I I i

SAIIF,SlOre AH 111\0 ftags

110011110

S~R

rim

I

I I 0011

POPF.Pop lIags

liQiiiiiiJ

S~ltl

I

RCR Rotale Through ,allY rlgl;1

I

AND

And

Reg, memory

=

and

register to either

11000000w[mod100 rim

1m media Ie 10 accumulator

~~ _-,d,,",,'_--'----"d:::'''=-'=-,w=---'-"

10

Immediate to register/memory

1"1000

Immediate 1o accumulator

LQ 0 0 0 0 law

00 a

6 a d w I mod '_~g ~
a as w jmodO 0 Q r'm r----d~~I

I

data

dil~a

I

w'

Immediate data and accumulator

L _~_~~

OR

I

Add with carry

Reg Imemory With register to either
Immediate to register/memory
Immediate to accumulator

a 0 1 a a d w I ~Od~~
I.' a 0 a 0 Os w Imod a , a ~-~-,,-To;';~--'L~_!i!J
10 0 0 1 0 law L.__ data
I
~!'__ ~J
10

UIC ,Incrlmlnl:
Register/memory

l'

Regrster

101000

1 1 1 1 1 1 w

reg

Imod 0 ? 0
I

W=ASCII adJusl tor add

lE'iiiiiLiJ

DAA·OeClmal adlust for add

10

SUB

=

a10a

rilT'

J

ell~er

Immediate 10 register/memory
Immediate 10 accumulator

XDR

a lOw Imoo reg rl~
a 1 1 w Imod a a 0 rim I

l' 0 1 0 1 0 0 w I
lii::~ 0000
~O 1 10

I~~d

reg

I

data

w

Imod

reg

w

ImodO a 1

10 a 1 1 ODd

Immediate to register/memory

110

Immediate to accumulator

10

a0 0 0 a w

data

~~~O~'~O~'~'~O~w~I~~d~"~'~~~"~"~'~'w~iJ~'~

~

0 1 1 0 lOw

I

STRING MANIPULATION

SCAS=$can byte/word

111 ; 1 0011 I
11 a 1 001 a w I
11 a 1 001 t w I
l' 0 1 0 1 1 1 w I

lODS~load

110 t a 11 a w

REP~

Repeat

MOVS~Mo~e byTe/word

.11

=

lubtnct wllh borrow

Reg Imemory and register 10 either
Immediate from register/memory
Immediate/rom accumulator

CMPS~Compar€ byTe/word

"0

aa 1 1 0 d

1 00 000

W mod

reg

s W modO 1

100 a 1 1 1 0 w \

rim
1

rim

data

data
data If w 1

data Jf

s w 01

byte/wd to Al!AX

STOS=Stor byte/wd from Al!A

Mnemonics ©Intel, 1978

B-44

data rl w'

I

data It w 1

I

data Ilw 1

I

~
rim

I

data

~ta

It w 1

Q 010

~

imOd 1 1 0 rim

1 1 1 I

[10000oswlmodl01rim

data
data If w 1

Exclusive or

ReQ imemory and register 10 either

SUbtr.e!:

Immediate from reglsterlmemory

I

data

w

10 0 a 0 lad w

Reg Imemory and reg ISler to either

Immediate/rom accumulator

~

Or

Reg Imemory and register to

ADC

11000

Irnmedlate data and register/memory 11 1 1 1

Reg /memory With register 10 either

data

And function 10 flags. no reSUI;:-'·_ _ _ _,--_ _ _--,

Reglster1memo,y and register

Add:

~IO~O~'O~O~O~d;;,w+1m;;,O;;d~',;"9~';;,'"~_ _ _ _, -_ _ _-c---,---;

Imrwdlateloreglsterln1emorv

TEST

ARITHMETIC
ADD

arithmeTiC rrq,ht

RDl ROlalelett

I

PUINF=Push flags

I 00

SHII Shltl logical 'Ighl
rim

I

tOt wi

data

I ~
~,;-y]

8088

COITROL TRANSFER
CALL C.II:

76543210

Direct Wllhm segment

1 1

76&43210

16543210
101000
dlsp-Iow
11111111 mod 010 rim

Indirect wrlhm segment

Dlrectlntersegment

~ol

IndlreCllnlersegment

111111

I

I I

oflset·hlgh

Ol1sel-low
seg-Iow

1 Imod 0'

J.'/JAE Jump on n01 below/above

dlsp·hlgh

seg-hlgh

I

JMP - Unclndilltnil Jump:
Direct wllhm segmenl
Direct wllhm segmenl-shorl

1
1111010111

DlrecllnTersegmenl

1
Imod 100 rim 1
~10101
o!lsel-Iow 1
[
seg-Iow

Indirect Inlersegmen!

~llll11lmodl01 rim 1

Liiiiiil

Indirect Wllhln segment

1

fIIIurn fram CAll:
111000011
1110000 I 0

Intersegmenl

O!fsetohlgh--.J

seg.~

1110010111

Inlersegmenl. adding Immediate 10 SP ic11""',,,,0,=0,=:;='0,=:;='0~1~~d;:;";:;";;I'W;;"""=r----,d="",.-,-h,,,-gh----,1
JE/JZ·Jumpon equallzero
[ 01 I I 0 I 00 I
dlSp
JL/J.6E~~ue~~a~n less/not greater ~[0:"':"':"';;;";.,0::0~1~~d;;;"~P~=I

JLElJ.ag~~~~ron less or equal/no! F.
I o"":""""""",,~,;.o~1~~d~"",p~=I
J'/JIAE~~~~ea~n below/no! abovej~o:..,:",,:..';.O;.O~'0~1~~d;;;"~P~~=I
J'E/JIA~~~~~o~ne below or equal! ~I0",,',,';,.';,.0,=',=:;='0~1~~d;;;"~p~=l1

Of

eQuall

JIO Jump on ncloverllOw

101110001[

dlsp

JIB Jumpon nol Sign

[0·',11001

dlsp

LOOP loopCX times

1

LODPlIlOOPE Loop while zero/eQual
lOOP.Z/LDOP.ELoop .... hllenat
zerolequ~~

I

11 100010]
11100001

dlsp

11100000

dlsP

1110o0t 1

dlSp

1
1
1

-]

dlsp

liliiOI,

Type 3

0' 1
1110011001

linD Inlerruptan overtlow

111001110

IRET Interrupt relllrn

111001111 1

Typesoecilled

IV~'~

I

PROCESSOR CONTROL
ClCClearcarry
eMt Gomplementcarry

HLTHalt

WAIT Wall
ESC Escape

~o:..';,.';,.';,,;,.';.'0:;.;.'l==~~d;;;"~P~=I

lii 1 1 1 1 I 1 I

INT .Interrupt

CLDCleardHectlon
STDSetduecllOn
CLlClellrmterrupt
STISelmler rupl

O='='='='""o~,0~1~~d;;;"~P~=lJ
~Io:..,;,.,;,.,;.o;.o;.o:::o~1~~d;;;"~P~=l1

F,I

I

JILElJIi~~~~~ron not less

dlsp

STCSetcarry

JO=Jump on ovedlow
JS·Jumponslgn
1011 11000 I
dlsp
JIElJIZ=Jump on not eQuallnotzero F.o"",;",;",,,,,o~,o~,l==~~d;;;"~P~=I

J.L/JaE~~ue~~a~n nolless/grealer

dlsp

~ll'Ol'!

Jell Jurnpcn CX zero

I
I

Wllhlnsegment
Within seg addmgImmedto SP

JP/JPE=Jump on parity/panty even

[0 11 101111

1

T

RET

dlsp-hlgh

dlsp

78543210 76543210
dlsp
I:E!TIn, , 1
1

or equal
JIIE/JA Jump on not below or
equal/above
JNP/JPO Jump on nol par/par adel

dlSP-=oJ

110 e~!ernal

devlcel

LOCK Bus lock prell x

fillI ..,.:
If s:w = 01 then 16 bits of Immediate data form the operand_
,f s:w = 11 then an Immediate data byte is Sign extended to
form the 16-M operand
II v = 0 then "count" = 1. It v = 1 then "count" in (el)
x = don't care
Z IS used lor siring primitives lor comparison With Z.F FLAG

Al = 8-bit accumulator
AX '" 16-bit accumulator

ex = Count register

OS " Oala segment
Es " Extra segment
Above/below refers to unsigned value_
Greater = more positive,
less = less positive (more negative) Signed values

SEGMENT OVERRIDE PREFIX

Itd= 1 then"to"reg;ifd=Othen"from"reg
it w = 1 then word instruction; if w = 0 then bvte instruction

il
il
il
il

mod"
mod"
mod"
mod"

11 then
00 then
01 then
10 then

il rim" 000 then
il rim" 001 then
il rim" 010 then
il rim" 011 then
il rim" 100 then
il rim" 101 then
il rim" 110 then
il rim· llllhen
OIsP lollows 2nd

rim is treated as a REG lield
OlsP " 0', disp-Iow and dlSp-high are absenl
OIsP " disp-Iow sign-extended to 16-bits, disp-high
OIsP " disp-high: disp-Iow
EA " (BX) • (51) • OIsP
EA " (BX) • (01) • OlsP
EA • (BP) • (51) • OIsP
EA " (BP) • (01) • OIsP
EA " (51) .01SP
EA " (01) • OIsP
EA " (BP) • OlsP'
EA· (BX) .00SP
byle 01 inslruclion Ibelore oala il required)

'excepl il mod" 00 and rim" 110 Ihen EA "disp-high: disp-Iow

10 0 1 reg 1 1 01

REG is aSSIgned
IS

~ccording

16-8111. - I)
000 AX
001 CX
010 OX
011 BX
100 SP
101 BP
110 51
111 DI

absent

10 the following table

6-8111. 01
000 AL
001 CL
010 DL
011 BL
100 AH
101 CH
110 DH
111 BH

Segmlnt
00 Es
01 Cs
10 55
11 OS

Instructions which reference the flag register file as a 160bit object use the symbol FLAGS to
represent the tile:

FLAGS" X:X:X:X:IOFJ(DF):(IF).ITF):(sFIIZFI X:IAF)'X IPF) X:(CF)

Mnemonics© Inlel, 1978

B-45

8089
8/16·811 HMOS 1/0 PROCESSOR
• High Speed DMA capabilities including
I/O to memory, memory to I/O, memory
to memory and I/O to I/O

• Memory based communication with
CPU
• Supports LOCAL or REMOTE I/O
processing

• MCS·SO™, MCS·SS™, MCS·S6™ and
SOS8 compatible, removes I/O
overhead

• Flexible, intelligent DMA functions
including Translation, Search, Word
Assembly/Disassembly

• Allows mixed interface of S/16·bit
peripherals, to S/16·bit processor busses

• MULTIBUS™ compatible system
interface

• 1 Mbyte addressability

The Intel® 8089 is a revolutionary concept in microprocessor input/output processing. Packaged in a 40-pin DIP
package, the 8089 is a high performance processor implemented in N·channel, depletion load silicon gate technology
(HMOS). The 8089's instruction set and capabilities are optimized for high speed, flexible and efficient 110 handling. It
allows easy interface of Intel's 16-bit 8086 and 8-bit 8088 microprocessors with 8/16·bit peripherals. In the REMOTE
mode, the 8089 bus is user definable allowing it to be compatible with any 8/16-bit Intel microprocessor, interfacing
easily to the Intel multiprocessor system bus standard MULTIBUSTM.
The 8089 performs the function of an intelligent DMA controller for the Intel MCS-86 family and with its processing
power, can remove 110 overhead from the 8086 or 8088. It may operate completely in parallel with a CPU, giving
dramatically improved performance in 110 intensive applications. The 8089 provides two 110 channels, each supporting
a transfer rate up to 1.25 mbyte/sec at the standard clock frequency of 5 MHz. Memory based communication between
the lOP and CPU enhances system flexibility and encourages software modularity, yielding more reliable, easier to
develop systems.

CPU

1/0 CHANNEL 1

OMA REO,
DMA
TERMINATE.

'---"I
I
I
I

I

I

1

11"":1 1
I~I

L_

=.J

V..
A141D14
A17/54

STATUS
ABID9

ADDRESS/
DATA

A~"
A7/D7

EXT 1

..,06

DRQ1
DRQ2

A3ID3

51
!!O

DMA REO,
DMA
TERMINATE,

SEl

ASSEMBLY /
DISASSEMBLY

SINTR·2

eA

elK

INSTRUCTION
FETCH UNIT

Figure 1. 8089110 Processor Block Diagram

Figure 2. 8089 Pin Diagram

B-46

8089
e,

h4!'$.

scan control. CRT control, such ~
auto scrolling, is simplified with the
control, communication control and generat'tl
a few of the typical applications for the 8089.

FUNCTIONAL DESCRIPTION
The 8089 lOP has been designed to remove I/O processing, control and high speed transfers from the central
processing unit. Its major capabilities include that of initializing and maintaining peripheral components and
supporting versatile DMA. This DMA function boasts
flexible termination conditions (such as external terminate, mask compare, single transfer and byte count expired). The DMA function of the 8089 lOP uses a two cycle approach where the information actually flows
through the 8089 lOP. This approach to DMA vastly simplifies the bus timings and enhances compatibility with
memory and peripherals, in addition to allowing operations to be performed on the data as it is transferred.
Operations can include such constructs as translate,
where the 8089 automatically vectors through a lookup
table and mask compare, both on the "fly".

Remote and Local Modes
Shown in Figure 3 is the 8089 configured in a LOCAL
mode. The 8086 (or 8088) is used in its maximum mode
configuration. The 8089 and 8086 reside on the same
local bus, sharing the same set of system buffers.
Peripherals located on the system bus can be addressed by either the 8086 or the 8089. The 8089
requests the use of the LOCAL bus by means of the
RQ/GT line. This performs a similar function to that of
HOLD and HLDA on the Intel 8085A, 8080A and 8086
minimum mode, but is implemented on one physical
line. When the 8086 relinquishes the system bus, the
8089 uses the same bus control, latches and transceiver
components to generate the system address, control
and data lines. This mode allows a more economical
system configuration at the expense of reduced CPU
thruput due to lOP bus utilization.

The 8089 is functionally compatible with Intel's 8086,
8088 family. It supports any combination of 8/16-bit
busses. In the REMOTE mode it can be used to complement other Intel processor families. Hardware and communication architecture are designed to provide simple
mechanisms for system upgrade.

A typical REMOTE configuration is shown in Figure 4. In
this mode, the lOP's bus is physically separated from
the system bus by means of system buffers/latches. The
lOP maintains its own local bus and can operate out of
local or system memory. The system bus interface contains the following components:

The only direct communication between the lOP and
CPU is handled by the Channel Attention and Interrupt
lines. Status information, parameters and task programs are passed via blocks of shared memory, simplifying hardware interface and encouraging structured
programming.

• Up to three 8282 buffer/latches to latch the address to
the system bus

The 8089 can be used in applications such as file and
buffer management in hard disk or floppy disk control. It
can also provide for soft error recovery routines and

so

~~iSt===~ES1 ~~:

MNIMX -GND

....

8088,

fi

L

CPU

r- elK

READY

l§
T

ALE

I r- STO

....

GND

GENERATOR

OE

~

NO
:-

J:

L . elK 8089

lOP

=-

I:

8282
LATCH
(1,20R3)

I

II

BHE

r-------,

I

>- ~

"OR~

I I I I

DeCODe

II

Yrt~~~===::::;-·~AO!QjOR¢~;;::::;-;:--=~::::;:=~:::;:=::~=;::::;:~

,.......DRI~ TRA"~~'VER f.-~"~j~IA:lT~A[~~~~~~

r----Ir~TT1f r r
-r-ra--'
1581T UO ADDR

N.C.

INTA

~---'

AQlGl

:~~~

N.C.

r------,
r-------,

~

CLOCK

:''''''''~CI-=:-=======:==ri====!=========:
="""7
;'O~R~C~===:;::::=====+~===+===+;==+:;===:

52
CON.
~ ~~,~
TROLLER A = _

RESET

D

elK

• Up to two 8286 devices bidirectionally buffer the
system data bus

I~ ~j n I~

I
..
i5WC

I~

2142 RAM (4)
(2)
(2)

1KIC8

1Kx8

I

2718.2

1'1

EPROM (2)

2Klt8 2Kx8

~ .C~; I!:c~ ~
PERIPHERAL

PERIPHERAL

DUQ

OMQ

INT

DMAC

tNT

QMAe,

I

NOTE: ONLY ONE LATCH IS NEEDED IF CONFIGURED.WITH 8088 AND ONLY 84K
ADDRESSING IS USED. DNU ONE TRANSCEIVER IS NEEDED IF USING A
PHYSICAL. 8-81T DATA BUS (8088).

Figure 3. Typical 8088, 8086/8089 Configuration with 8089 In LOCAL Mode, 8088, 8086 in MAX Mode

B-47

8089
the lOP which channel is being a
tion from the lOP to the processor cart
similar manner via a system interrupt (SI
CPU has enabled interrupts for this purpose'.
ally, the 8089 can store messages in memory reg~r
its status and the status of any peripherals. This com'
munication mechanism is supported by a hierarchial
data structure to provide a maximum amount of flexibility of memory use with the added capability of handling multiple lOP's.

An 8288 bus controller supplies the control signals
necessary for buffer operation as well as MRDC
(Memory Read) and MWTC (Memory Write) signals.
• An 8289 bus arbiter performs all the functions
necessary to arbitrate the use of the system bus. This
is used in place of the RQ/GT logic in the LOCAL
mode. This arbiter decodes type of cycle information
from the 8089 status lines to determine if the lOP
desires to perform a transfer over the "common" or
system bus.
The peripheral devices P1 and P2 are supported on their
own data and address bus. The 8089 communicates with
the peripherals without affecting system bus operation.
Optional buffers may be used on the local bus when
capacitive loading conditions so dictate. 1/0 programs
and RAM buffers may also reside on the local bus to further reduce system bus utilization.

Illustrated in Figure 5 is an overview of the communication data structure hierarchy that exists for the 8089 1/0
processor. Upon the first CA from RESET, 5 bytes of information are read into the 8089 starting at location
FFFF6 (FFFF6, FFFF8-FFFFB) where the type of
system bus (16-bit or 8-bit) and pointers to the system
configuration are obtained. This is the only fixed location the 8089 accesses. The remaining addresses are
obtained via the data structure hierarchy. The 8089
determines addresses in the same manner as does the
8086; i.e., a 16-bit relocation pointer is offset left 4 bits
and added to the 16-bit address offset, obtaining a 20-bit
address. Once these 20-bit addresses are formed, they
are stored as such, as all the 8089 address registers are
20-bits long. After the system configuration pointer address is formed, the 8089 lOP accesses the system configuration block.

COMMUNICATION MECHANISM
Fundamentally, communication between the CPU and
lOP is performed through messages prepared in shared
memory. The CPU can cause the 8089 to execute a program by placing it in the 8089's memory space andlor
directing the 8089's attention to it by asserting a hardware Channel Attention (CA) signal to the lOP, activating the proper 1/0 channel. The SEL Pin indicates to

T~J~~~L

E
LOCAL

MEMORY
ROM/RAM

lOW
1I0R

lOR
INTA

(OPTIONAL-IF

so

NEEDED TO REDUCE
LOADING ON BOS9)

I

POEN

r:

DllR
52
51

i;L-

-

I

5,

5,

8089

···

ADDRESSIDATA

eLK
READY

PERIPHERAL

l

eLK

~MEMRD

--R
!----MEMW

I

:
I ~19-AO,

BH1

8282/83

~

LATCH

'"I"

>:

EXT1

lJ

TROLLER

ALE

r---

f-f----

CPU
SYSTEM
BUS

I'

"
jJ

ORal

DRQ2

'--

S.

,~

P2

so

OE

L

8282

:I

'us

CON·

STB

: IPERIPHERAL
PI

l\r

8288

...::::==-:'-:-:]"1

~

---

At:N

DEN

8286

~=~

i

SIGNALS

AEN

--------1
-

Lt ______ j
~

'us

ARBITRATION

\

8089

MULTI BUS
} ARBITRATION

8289

51

r;==.:,;!.,C-_'OJ,
,
~i, OEDTI~~

LOCAL
BUS

eLK

52

I

J

7'::--;

I

RO,RESET

II--

EXT2 GT

;L---~

T

---------1
Ik
,

DE

8286187
TRANC.

~

07-00

OR
015·00

~
I

AEN

1

!-READY

TO ANOTHER

8284

lOP

I--RESET

YDf-l
Figure 4_ Typical REMOTE Configuration

B-48

8089
LOCATION

I---.L:-:"::"::.::..::...jI--=.:=:..:.-J
SOC

SYSTEM
CONFIGURATION

BLOCK

L ---=.::..CB;.::A:.:D::DR:::E:.:.SS:.:..:.......J
CB RELOCATION

CONTROL
BLOCK

BUSY

I

I

Il

J
JI l

ccw

PB ADDRESS
PB RELOCATION

I
I I

.....n ..
BLOCK

BUSY

I

FFFF6

ccw

PB ADDRESS

PB RELOCATION

I,~:.a
ICHA~NEL

I-----'-'==------jl----~
TASK BLOCK

T

T

J

1..------.1'
T

lOP TASK

PROGRAM

T

Figure 5. Communication Data Structure Hierarchy

The System Configuration Block (SCB), used only duro
ing startup, points to the Control Block (CB) and provides
lOP system configuration data via the SOC byte. The
SOC byte initializes lOP 1/0 bus width to 8/16, and
defines one of two lOP RQ/GT operating modes. For
RQ/GT mode 0, the lOP is typically initialized as SLAVE
and has its RQ/GT line tied to a MASTER CPU (typical
LOCAL configuration). In this mode, the CPU normally
has control of the bus, grants control to the lOP as need·
ed, and has the bus restored to it upon lOP task completion (lOP request-CPU grant-lOP done). For RQ/GT
mode 1, useful only in remote mode between two lOPs,
MASTERISLAVE designation is used only to initialize
bus control: from then on, each lOP requests and grants
as the bus is needed (IOP1 request-IOP2 grant-IOP2
request-'IOP1 grant). Thus, each lOP retains bus con·
trol until the other requests it. The completion of in·
itialization is signalled by the lOP clearing the BUSY
flag in the CB. This type of startup allows the user to
have the startup pointers in ROM with the SCB in RAM.
Allowing the SCB to be in RAM gives the user the flex·
ibility of being able to initialize multiple lOPs.

the lOP, allowing the lOP to ope
the CPU, or reside in system memory.,*
The advantage of this type of communicai
the processor, lOP and peripheral, is that it allo
very clean method for the operating system to ha
1/0 routines. Canned programs or "Task Blocks" allow'
for execution of general purpose 1/0 routines with the
status and peripheral command information being
passed via the Parameter Block ("data" memory). Task
Blocks (or "program" memory) can be terminated or
restarted by the CPU, if need be. Clearly, the flexibility
of this communication lends itself to modularity and ap·
plicability to a large number of peripheral devices and
upward compatibility to future end user systems and
microprocessor families.

Register Set
The 8089 maintains separate registers for its two 1/0
channels as well as some common registers (see Figure
6). There are sufficient registers for each channel to sus·
tain its own DMA transfers, and process its own instruc·
tion stream. The basic DMA pointer registers (GA, GB 20 bits each), can point to either the system bus or local
bus, DMA source or destination, and can be autoincre·
mented. A third register set (GC) can be used to allow
translation during the DMA process through a lookup
table it pOints to. Additionally, registers are provided fora
masked compare during the data transfer and can be set
up to act as one of the termination conditions. Other
registers are also provided. Manyof these registers can be
used as general purpose registers during program execu·
tion, when the lOP is not performing DMA cycles.
USER PROGRAMMABLE
TAG19

G.P. ADDRESS B (GB)
G.P. ADDRESS C (Ge)

TASK POINTER (TP)
" - - 1·811 POINTER TO EITHER 110 OR SYSTEM MEMORY SPACE
15
INDEX (IX)

BYTE COUNT (BC)
MASK

The Task Block contains the instructions for the respec·
tive channel. This block can reside on the local bus of

COMPARE (Me)

CHANNEL CONTROL (ec)
NON USER PROGRAMMABLE
(ALWAYS POINTS TO SYSTEM MEMORY)

The Control Block furnishes bus control Initialization for
the lOP operation (CCW or Channel Control Word) and
provides pointers to the Parameter Block or "data"
memory for both channels 1 and 2. The CCW is retrieved
and analyzed upon all CA's other than the first after a
reset. The CCW byte is decoded to determine channel
operation.
The Parameter Block contains the address of the Task
Block and acts as a messge center between the lOP and
CPU. Parameters or variable information is passed from
the CPU to its lOP in this block to customize the soft·
ware interface to the peripheral device. It is also used
for transferring data and status information between the
lOP and CPU.

0
G.P. ADDRESS A (GAl

o~

191

I

PARAMETER POINTER (PP)

r

CHANNEL CONTROL POINTER (CP)

(PHANTOM REGISTERS DENOTE 1 FOR EACH CHANNEL)

Figure 6. Register Model

Bus Operation
The 8089 utilizes the same bus structure as the
8086/8088 in their maximum mode configurations (see
Figure 7). The address is time multiplexed with the data
on the first 16/8 lines. A16 through A19 are time multi·
plexed with four status lines S3·S6. For 8089 cycles, S4
and S3 determine what type of cycle (DMA versus non·
DMA) is being performed on channels 1 or 2. S5 and S6

B-49

8089
are a unique code assigned to the 8089 lOP, enabling
the user to detect which processor is performing a bus
cycle in a multiprocessing environment.

16·bits wide with either an 8·bit
column) or 16·bit peripheral (word colu
The latency refers to the worst case respon
the lOP to a DMA request, without the bus arbitr
times. Notice that the word transfer allows 50% mor
bandwidth. This occurs since three bus cycles are reo
quired to map 8·bit data into a 16·bit location, versus two
for a 16·bit to 16·bit transfer. Note that it is possible to
fully saturate the system bus in the LOCAL mode
whereas in the REMOTE mode this is reduced to a max·
imum of 50%.

The first three status lines, 80·82, are used with an 8288
bus controller to determine if an instruction fetch or
data transfer is being performed in 1/0 or system
memory space.
DMA transfers require at least two bus cycles with each
bus cycle requiring a minimum of four clock cycles. Ad·
ditional clock cycles are added if wait states are reo
qUired. This two cycle approach simplifies considerably
the bus timings in burst DMA. The 8089 optimizes the
transfer between two different bus widths by using
three bus cycles versus four to transfer 1 word. More
than one read (write) is performed when mapping an
8·bit bus onto a 16·bit bus (vice versa). For example, a
data transfer from an 8·bit peripheral to a 16·bit physical
location in memory is performed by first dOing two
reads, with word assembly within the lOP assembly
register file and then one write.

Local

Bandwidth

As can be expected, the data bandwidth of the lOP is a
function of the physical bus width of the system and 1/0
busses. Table 1 gives the bandwidth, latency and bus
utilization of the 8089. The system bus is assumed to be

Remote

Byte

Word

Byte

Word

830 KB/S

1250 KB/S

830 KB/S

1250 KB/S

"sec'

Latency

1.0/2.4

System Bus
Utilization

2.4 jJsec
PER
TRANSFER

1.0/2.4

"sec'

1.6 jJsec
PER
TRANSFER

Table 1. 5 MHz 8089 Operation -

"sec'

0.8 jJsec
PER
TRANSFER

1.0/2.4

"sec'

0.8 jJsec
PER
TRANSFER

With 1G·Bit BUS

*2.4 ilsec if interleaving with other channel and no wait states. 1J1.sec if
channel is waiting for request.

! -_ _ _ _ (4+ NWAIT) = T c v - - - - _

----(4+ NwAn)=Tov-----

"

"

n

1\
,'" -...l
\L..-_ _~

TWAIT

I

GOES INACTIVE IN THE STATE

JUST PRIOR TOT.

T.

1\
L

'-----~--~~~-r--. _ I

\~-

\

\

ADDR/OATA
(16·8IT
PHYSICAL BUSj

'-----p
DTIR

DEN

\L.-_-----'/
NOTE 1:

1.0/2.4

!R! IS STABLE (I ••.,

NON MULTIPLEXEDITHROUGHOUT EACH TRANSFER
CYCLE. A8-A,~ ARE ALSO STABLE ON TRANSFERS TO A PHYSICAl8·BIT

.os

Figure 7. 8089 Bus Operation

B-50

8089
Pin Name(s) I/O Description

PIN DESCRIPTION
Pin Name(s) I/O Description
AO-A15/
DO-D15

A16-A19/
S3-S6

I/O Multiplexed address and data bus. The
function of these lines are defined by
the state of SO, S1 and 52 lines. The
pins are floated after reset and when
the bus is not acquired. A8-A 15 are
stable on transfers to a physical 8-bit
data bus (same bus as 8088), and are
multiplexed with data on transfers to a
16-bit physical bus.

a

Multiplexed most significant address
lines and status information. The address lines are active only when addressing memory. Otherwise, the
status lines are active and are encoded
as shown below. The pins are floated
after reset and when the bus is not
acquired.

a

RESET

The receipt of a reset signal causes
the lOP to suspend all its activities and
enter an idle state until a channel attention is received.

ClK

System clock which provides all timing
needed for internal lOP operation.

CA

Channel Attention. Used to get the attention of the lOP. Upon the falling
edge of this signal, the SEl input pin is
examined to determine Master/Slave or
CH1/CH2 information. This input is active high.

SEl

The first CA received after system
reset informs the lOP via the SEl line,
whether it is a Master or Slave (0/1 for
Master/Slave respectively) and starts
the initialization sequence. During any
other CA the SEl line signifies the
selection of CH1/CH2. (0/1 respectively)

DRQ1-2

DMA request inputs which signal the
lOP that a peripheral is ready to transfer/receive data using channels 1 or 2
respectively. The signals are active
high.

56555453

o
o
BHE

so,81,s;;

a

a

0 DMA cycle on CHI
DMA cycle on CH2
Non-DMA cycle on CH1
1 Non-DMA cycle on CH2

o

The Bus High Enable signal is used to
enable data operations on the most
significant half of the data bus (D8D15). The signal is active low when a
byte is to be transferred on the upper
half of the data bus. The pin is floated
after reset and when the bus is not
acquired. BHE does not have to be
latched.
These are the status pins that define
the lOP activity during any given cycle.
They are encoded as shown below:

RQ/GT

525150
o 0 0
o 0 1
o 1 0
o 1 1
1 0 0

Instruction fetch; I/O space
Data fetch; I/O space
Data store; I/O space
Not used
Instruction fetch; System
Memory
o 1 Data fetch; System Memory
1 0 Data store; System Memory
1
Passive
The status lines are utilized by the bus
controller and bus arbiter to generate
all memory and I/O control signals. The
signals change during T4 if a new
cycle is to be entered while the return
to passive state in T3 or T w indicates
the end of a cycle. The pins are floated
after system reset and when the bus is
not acquired.

READY

The lock output signal indi'cates"t
bus controller that the bus iSneed'e
for more than one contiguous cycle., It>.,
is set via the channel control register,'
and during the TSl instruction. The pin
floats after reset and when the bus is
not acquired. This output is active low.

SINTR1-2

EXT1-2

The ready signal received from the addressed device indicates that the
device is ready for data transfer. The
signal is active high and is synchronized by the 8284 clock generator.

B-51

I/O The ReQuest GranT pin implements
the communication dialogue required
to arbitrate the use of the system bus
(between lOP and CPU, lOCAL mode)
or I/O bus when two lOPs share the
same bus (REMOTE mode). The RQ/GT
signal is active low. An internal pull-up
permits RQ/GT to be left floating if not
used.

a

Interrupt outputs from channels 1 and
2 respectively. The interrupts may be
sent directly to the CPU or through the
8259A interrupt controller. They are
used to indicate to the system the occurrence of user defined events.
External terminate inputs for channels
1 and 2 respectively. The EXT Signals
will cause the termination of the current DMA transfer operation if the
channel is so programmed by the
channel control register. The signals
are active high.

Vee

+ 5 volt power input.

Vss

Ground pins.

8089
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ......... O°C to 70'C
Storage Temperature ............. - 65'C to + 150'C
Voltage on Any Pin with
Respect to Ground. . .
. .... - 0.3 to + 7V
Power Dissipation. . . . . . . . . . . . . . .
. ... 2.5 Watt

·COMMENT: Stresses above those listed under
Ratings" may cause permanent damage to the device. This
rating only and functional operation of the device at these or any ~
conditions above those indicated in the operational sections of
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS
Symbol

Parameter

Vil

Input Low Voltage

V IH

Input High Voltage

VOL

Output Low Voltage

V OH

Output High Voltage

Icc

Power Supply Current

-

Min.

Max.

Units

-0.5

+0.8

V

2.0

Vcc+ 1.O

V

0.45

V

2.4

Test Conditions

IOl = 2.0 mA(2)

V
350

IOH

= - 400 I-'A

TA = 25'C

mA

= Vcc

III

Input Leakage Current(1)

± 10

I-'A

VIN

Ilo

Output Leakage Current

±10

I-'A

0.45V '" VOUT '" Vcc

VCl

Clock Input Low Voltage

V CH

Clock Input High Voltage

-0.5

+0.6

V

Vcc + 1.0

V

C IN

Capacitance of Input Buffer
(All input except
ADo- AD 15, RQ/GT)

10

pF

Ie

= 1 MHz

C IO

Capacitance of I/O Buffer
(AD o - AD 15 , RQ/GT)

20

pF

fc

= 1 MHz

3.9

NOTES: 1. Except RO/GT.
2. Test Circuits:

ALL OUTPUTS EXCEPT: RQ/GT

I
I

30 pf

20/150 pf

1

DEPENDING ON WHICH IS
WORST CASE

-::-

-::-

B-52

~

8089

'"

/Jf#r:;~;~'i

A.C. CHARACTERISTICS

i}

8089: TA =O'Cto70'C, Vcc=5V ± 10%
8089/8086 MAX MODE SYSTEM (USING 8288 BUS CONTROLLER) TIMING REQUIREMENTS
Parameter

Symbol
TCLCL

-

CLK Cycle Period

Min.

Max.

Units

200

500

ns

TCLCH

elK Low Time

('IJTCLCL)-15

ns

TCI1CL

CLK High Time

('IJTCLCL)+ 2

ns

Test Condillons"

TCH1CH2

CLK Rise Time

10

ns

From 1.0V to 3.5V

TCL2CLl

CLK Fall Time

10

ns

From 3.5V to 1.0V

TDVCL

Data In Setup Time

30

ns

----

TCLDX

Data In Hold Time

10

ns

TR1VCL

ROY Setup Time into 8284 (See Notes 1, 2)

35

ns

TCLR1X

ROY Hold Time into 8284 (See Notes 1, 2)

0

ns

TRYHCH

READY Setup Time into 8089

TCHRYX

READY Hold Time into 8089

TRYLCL

READY Inactive to CLK (See Note 4)

TINVCH

Setup Time Recognition (ORa 1.2 RESET. Ext 1,2) (See Note 2)

30

ns

TGVCH

RalGT Setup Time

30

ns

TCAHCAL

CA Width

95

ns

TSLVCAL

SEL Setup Time

75

ns

TCALSLX

SEL Hold Time

0

ns

TCHGX

1'ill' Hold Time into 8089

40

ns

-

('IJTCLCL) - 15

ns

30

ns

-8

ns

TIMING RESPONSES
Min.

Max.

Units

TCLML

Command ActIVe Delay (See Note 1)

10

35

ns

TCLMH

Command Inaclive Delay (See Note 11

10

TRYHSH

READY Active to Status Passive (See Note 3)

Symbol

Parameter

Test Conditions

- - - ' - _ .._-'----_._----_._._----- - - - - - - + - - - - - - + - - - + - - - - + - - - - - - - CL = 80 pF

.-.-----.-r-------.-------.c..'-------'--------+------+----j---+----=---'-------

_

35

ns

110

ns

110
ns
TCHS_V____ ~~s ActiV':.~':'.".~___________________ I_---ll00,----+---:-c-+----I
TCLSH
Status Inactive Delay
130
ns

-------- - - - - . - - - - - - - - - - - - . - - - - - - - - - - - - - - - - - - - - - + - - - - TCLAV

Address Valid Delay

TCLAX

Address Hold Time

TCLAZ
TSVLH
TCLLH

-

110
ns
10
------_._-_._------+-------+---+---j
10

ns

..--------------.-.- .._ . _ - - - - - - - - + - - - - - - + - - - - + - - - - - 1

Address Float Delay

TCLAX

80

ns

--.--.------------.---------+-------t---+----Status Valid to ALE High (See Note 1)
15
ns
-----ct:Ki:-ow-to-A-L-E- v~lid(S-;;;;N~-te--·l-I-----------I-------+-----+---15
ns

----.---.. - ------.-------------.-------.--.------+------t-----j-TCHLL
TCLDV
TCHDX
TCVNV

-_.,------_
Data Valid Delay

ALE Inactive Delay (See Note 1)
. .--._---. -,

10

15

ns

110

ns

C L = 150 pI

-----------.------------j------+------t------1
ns
10
- - - - - - - - - - - - - - - - - - - - - - - - - - - + - - - - - + - - - - t - - - - -- Data Hold Time'

45
+ _______f-___
+-._ns

__
C_o_nt_r~_~~ive Delay (See N.o_t_e_l_I_ _ _ _ _ _ _ _ _

-~

10

45

ns

50

ns

TCVNX

Control Inactive Delay (See Note 11

TCHDTL

Direction Control Active Delay (See Note 1)

TCHDTH

ns+ - - - - + - - - - - - - Direction Control Inacti_ve.:....cD.ce.cla.'..y..:(.~Se~e'_'_N.c0'_te'-l..:I______+ - - - - - - + _ - . . .30
:....._
85
ns
C,

TCLGH

1IT Inactive

- - - . - - --- - -

-----------+------+---+-_.---1
--

~ ,eeoc ~~-iIT 'c'" '"''
___ !~_L~~___

~"oC

Delay

85

ns

CL = 30 pF

150
SINTR Valid Delay __._ _ _ _ _ _ _ _ _ _ _ _ _.L-_ _ _ _ _--'-_ _
_ _'--_ns
_ _.L-_CL = 100 pF

NOTES: 1 Signal at 8284 or 8288 shown for reference only.
2 Setup requirement for asynchronous signal only to guarantee recognition at next elK

B-53

3, Applies only to T3 and TW states.
4, Applies only to T2 state

8089

ClK
VCl

see NOTE 7

Aa-A15 ON TRANSFERS

1TO AN 8·BIT PHYSICAL BUS
AND BHE

52,51,So (EXCEPT HAL 1)

I

TClLH

ALE (8288 OUTPUTI

SEE NOTE 4

1

RDY (8284 INPUTI

TCHRYX

READY (8089 INPUT)

READ - (MWTC,AMWC,IOWC,AIOWC = VOH)

see NOTE 7 I
ANDA~.&~ 1

AD1S- AD o

FLOAT

:
DT/A
TCLMl--

~

i

i

I

I

I

!
TClMH-i

8288 OUTPUTS

SEE NOTES 4, 5

1MRDC OR 10RC

1

I
I

DEN

TCVNV ----

1-

TCLAV--

SEE NOTE 7 I
AND A~BOHVE~ \ AD1S-ADo

X

-

~CHDTH

I

!

i

r-

TCHDX-

TClDVI-

A15"AO

FLOAT

-

-

NOTE 3)

TCVNX--

-TCLML

TCLMH-

{

~

8288 OUTPUTS
NOTES 4,5

-

,

_TClML

,

;

(SeE

DATA OUT

TCVNV-

MWTCOR lowe

i

-

I

DEN

see

11

I

I

!

TCVNX-I

WRITE - (RD,MRDC,IORC,DT/R = VOH)

r

I--

1

I

r- i

-I

I TCHDTL-I

, .o.LLSIG'IALSSWITCH8erWEENVOH ANDVOL UNlESSOTHERWISESPECIFIED
2. fillY IS SAMPLED NEAR H'E END OFT2.T J TW TO DETERMINE 1FT'll MACHINE ST/l.TESAFlE TO BE INSERTED

6 "LL TlMlNG MEASUREMENTS ARE MADE "T 1 5V UNLESS OTHERWISE NOTED
I A.-",\ ARE STABLE ON TRANSFERS TO AN e BIT PHYSICAL DATIl. BUS, a t.~.""
DON·T FlOAT ON A READ fROM "N e BIT PHYSICAL BUS OR MULTIPLEX WITH
DATA ON A WRITE TO AN 881T PHYSICAL BUS "i"iit IS STABLE 'NON
MULTIPLEXEDI FOR All TRANSFERS

B-54

-TClMH

I

3 FOLLOWING A WAITE CYCLE DATA REMAINS VALID ON THE 60119 LOCAL BUS UNTIL A LOCAL BUS MASTER Of.CIDES TO RUN ANOTHER BUS
CYCLE THE LOCAL BUS IS FLOATED BY THE B069 WHEN THEBOII9 ENTERS A REQUEST BUSA CKNOWLEOGESTATE
4SIONALSATa2840R82Il8ARESHOWNFOAREFERENCEONLY
______ _
5 :~~I~SES~~NHC:2~ ~~;. B28B COMMAND AND CONTROL SIONAl.S (MROC. MWTC. AMWC. 10RC. 10WC AIOWC. INTA AND DEl'll LAGS nil'.

Figure 8. 8089 Bus Timing -

-

(Using 8288)

8089
elK

ORO 1,2
RESET

NOTES,
1. SETUP AEQUIREMENTS FOR ASYNCHRONOUS SIGNALS ONLY TO'GUARANTEE
RECOGNITION AT NEXT elK.
2. ALL INPUTS EXCEPT CA ARE LATCHED ON A elK EDGE. THE CA INPUT IS

NEGATIVE EDGE TRIGGERED.
3. ORO BECOMING ACTIVE GREATER THAN 30 ns AFTER THE RISING EDGE OF elK
WilL GUARANTEE NON·RECOGNITION UNTIL THE NEXT RISING CLOCK EDGE.

Figure 9. Asynchronous Signal Recognition

CLK

,

SlNT"'~

LOCK

TClSRVJ~

_ _

~

Figure 10. Bus Lock Signal Timing and SINTR Timing

''''''vw
..

ClK

~r-

j I;:H/-

TClCl-

I~
PREVIOUS RELEASE

- ___ I

~--------------------------------------~

TCLAZ

v-----------~~

CPU

8089

(SEE NOTE 1)

NOTES,
1. THE CPU MAY NOT DRIVE THE BUSES INSIDE THE REGION SHOWN WITHOUT
RISKING CONTENTION.

2. IN THE REMOTE CONFIGURATION, THE 6089 lOP CAN EITHEA ISSUE OR
RESPOND TO F[QiGT, THUS ALLOWING THE USER TO TIE 2 8089's TOGETHER. THe
PROTOCOL OF RQIGT IN THIS CONFIGURATION CONSISTS OF ONLY ONE PULSE
TO TRANSFER THE BUS

Figure 11. Request/Grant Sequence Timing

elK

EXT 1,2

Figure 12. External Terminate Setup Timing

CA

Figure 13. SEL Setup and Hold Timing

B-55

8089
8089 INSTRUCTION SET SUMMARY
Data Transfers
OPCODE

LPD
LPD!
MOVP
MOVP

P,M
P,I
M,P
P,M

POINTER INSTRUCTIONS

7

Load POinter PPP from Addressed Location
Load POinter PPP Immediate 4 Bytes
Store Contents of Pointer PPP in Addressed Location
Restore Pointer

P
P
P
P

0 7
P
P
P
P

P
P
P
P

oA

0
1
0
0

A
000
A A
A A

1
1
1
1

1 000
000 0
1 001
1 0 0 0

1MM

0 OAAW
0 OAAW
0 OAAW
0 OAAW
wb OOW
wb A AW

1 001
1 100
1 000
1 000
001 1
1 0 0

OOMM
11M M
OOMM
1 MM
0 0 0
11M M

o
o

MOVE DATA

MOV

M,M

MOV
MOV
MOVI
MOVI

R,M
M,R
R
M

SourceDestinationLoad Register RRR from Addressed Location
Store Contents of Register RRR in Addressed Location
Load Register RRR Immediate (Byte) Sign Extend
Move Immediate to Addressed Location
Move from Source to Destination

o

0 0
000
R R R
R R R
R R R
000

o

o
o

Control Transfer
CALLS
'CALL

11 0 0

Call Unconditional

wb

A A W 11 0 0 1

11M M 1

JUMP

JMP
JZ
M
JZ
R
JNZ M
JNZ R
JBT
JNBT
JMCE
JMCNE

Unconditional
Jump on Zero Memory
Jump on Zero Register
Jump on Non-Zero Memory
Jump on Non-Zero Register
Test Bit and Jump if True
Test Bit and Jump if Not True
Mask/Compare and Jump on Equal
Mask/Compare and Jump on Non-Equal

1 0 0
000
R R R
000
RR R
B B B
B B B
000
000

wb DOW 001 0
wb AAW1 1 1 0
wb
0 0 0 1
0
wb AAW1 1 1 0
wb 000 0 1
0
wb A A 0 1 0 1 1
wb A A 0 1 0 1 1
wb A A 0 1 0 1 1
wb A A
1
1 1

o

o
o

a

a

o0 0 0
o1MM
o1 0 0
OOMM
0 0 0
1 1MM
1 OMM
0 OMM
1MM

o

a

Arithmetic and Logic Instructions
INCREMENT, DECREMENT

a a a a OAAW 1 1
a 000 a a a
a a a a a A AW 1 1
R R R a a a a a o 0

Increment Addressed Location
Increment Register
Decrement Addressed Location
Decrement Register

INC
INC
DEC
DEC

M
R
M
R

ADD I
ADDI
ADD
ADD

M,I
R,I
M,R
R,M

AND!
AND!
AND
AND

M,I
R,I
M,R
R,M

AND
AND
AND
AND

ORI
ORI
OR
OR

M,I
R,I
M,R
R,M

OR
OR
OR
OR

R R R

1
1
1
1

0
1
0
1

1 OMM
1
1 1 MM
1 100

aaa

ADD

ADD
ADD
ADD
ADD

aaa

a a OOMM
aa a aaaa
a OOMM
a OOMM

Immediate to Memory
Immediate to Register
Register to Memory
Memory to Register

wb A AW 1 1
R R R wb OOW
1
R R R
OAAW 1 1
1
R R R
A AW 101

Memory with Immediate
Register with Immediate
Memory with Register
Register with Memory

wb A AW 1 1
R R R wb OOW
1
R R R
OAAW 1 1
1
R R R
OAAW 1
1

a
a a

AND

aaa

a
a

aa
aa a
a
a a

1
1
1
1

OMM
000
OMM
OMM

OR

Memory with
Register with
Memory with
Register with

aaa

Immediate
Immediate
Register
Memory

a 1MM
a a a a a 100
a 1MM
a a 1MM

wb A A 0 1 100
R R R wb A A
1
R R R
OAAW 1 1 0 1
R R R
OAAW 101

a
a

B-56

8089
Arithmetic and Logic Instructions (cont.)
OPCODE
NOT
NOT
NOT

R
M
R,M

o

NOT

7

Complement Register
Complement Memory
Complement Memory, Place in Register

R R ROO 0 0 0 001
0
-,-.-------..
OOOOOAAW
10
RRRO OAAW1010 11MM

7

----~.--,~-

----~

Bit Manipulation and Test Instructions
BIT MANIPULATION
SET
CLR

~-_O A A 0

Set the Selected Bit
Clear the Selected Bit

~IOAAO

01MM1

1~

.~----

TEST
Test and Set Lock

TSL

1 A A 0

J100101M}Al

Control
HLT
SINTR

Halt Channel Execution
Set Interrupt Service Flip Flop
No Operation
Enter DMA Transfer
Set Source, Destination Bus Width; S,D 0

Nap
XFER
WID

NOTES:

=8, 1 = 16

001 0
~_O 0
000 0
1 1 0
1 S D 0

c9.

o0
o0
o0
o0
o0

0
0
0
0
0

0
0
0
0
0

o1
o0
o0
o0
o0

0
0
0
0
0

0
0
0
0
0

1 0 0-0-

00--0-0-

o

0 0 0
0-000

o0

0 0

ppp

'1\ field in call instruction can be 00,01,10 only.
"OPCODE is second byte fetched.
All instructions consist of at least 2 bytes, while some
instructions may 'use up to 3 additional bytes to specify
literals and displacement data. The definition of the
various fields within each instruction is given below:
o 7

000
001
010
100

pO
p1
p2
p4

GA
GB
GC
TP

; task block pointer

BBB Bit Select Field

M M Base Pointer Select

The bit select field replaces the RRR field in bit manipulation instructions and is used to select a bit to be oper·
ated on by those instructions. Bit 0 is the least signifi·
cant bit.

00 GA

wb

01 GB
10 GC
11 PP

01 1 byte literal or 1 byte displacement
10 2 byte (word) literal or 2 byte (word) displacement

I

R

R

R

I I IwI
W

b

A A

OPCODE

PPPBBB

RRR Register Field
The RRR field specifies a 16-bit register to be used in
the instruction. If GA, GB, GC or TP, are referenced by
the RRR field, the upper 4 bits of the registers are loaded with the sign bit (Bit 15). PPP registers are used as
20-bit address pointers.
RRR
000
001
010
011
100
101
110
111

rO
r1
r2
r3
r4
r5
r6
r7

GA
GB
GC
BC
TP
IX
CC
MC

; byte count
; task block
; index register
; channel control (mode)
; mask/compare

AA Field
00 The selected pointer contains the operand address.
01 The operand address is formed by adding an 8-bit,
unsigned, offset contained in the instruction to the
selected pointer. The contents of the pointer are unchanged.
10 The operand address is formed by adding the contents of the Index register to the selected pointer.
Both registers remain unchanged.
11 Same as 10 except the Index register is post auto·
incremented (by 1 for 8-bit transfer, by 2 for 16-bit
transfer).
W Width Field

o

The selected operand is 1 byte long.
The selected operand is 2 bytes long.

MNEMONICS i9 1979 INTEL CORP.

B-57

8089
Additional Bytes
OFFSET: 8-bit unsigned offset.
SDISP
: 8/16-bit signed displacement.
LITERAL: 8/16-bit literal.
The order in which the above optional bytes appear in
lOP instructions is given below:

Offsets are treated as unsigned numbers. Literals and
displacements are sign extended (2's complement).

B-58

8282/8283
OCTAL LATCH
•

Fully Parallel 8-Bit Data Register and
Buffer

•

Transparent during Active Strobe

•

Supports 8080, 8085, 8048, and 8086
Systems

• High Output Drive Capability for
Driving System Data Bus

•

3-State Outputs

•

20-Pin Package with 0_3" Center

•

No Output Low Noise when Entering
or Leaving High Impedance State

The 8282 and 8283 are 8-bit bipolar latches with 3-state output buffers. They can be used to implement latches, buffers,
or multiplexers. The 8283 inverts the input data at its outputs while the 8282 does not. Thus, all of the principal periph·
eral and input/output functions of a microcomputer system can be implemented with these devices.

PIN CONFIGURATIONS

LOGIC DIAGRAMS

Vee
000
DO,
002
003
DO,
005
006

L ______ _

L ______ _

007
STB

PIN NAMES
010-017
000- 007
OE
STB

OATA IN
OATA OUT
OUTPUT ENABLE
STROBE

B-59

828218283
00 0-00 7

PIN DEFINITIONS
Pin
STB

(8282)

Description

00 0-00 7
(8283)

STROBE (Input). STB is an input control
pulse used to strobe data at the data input
pins (Ao-A7) into the data latches. This
signal is active HIGH to admit input data.
The data Is latched at the HIGH to LOW
transition of STB.

true, the data in the
sented as inverted (8283)
(8282) data onto the data output'

OPERATIONAL DESCRIPTION
The 8282 and 8283 octal latches are 8·bit latches with
3·state output buffers. Data having satisfied the setup
time requirements is latched into the data latches by
strobing the STB line HIGH to LOW. Holding the STB
line in its active HIGH state makes the latches appear
transparent. Data is presented to the data output pins by
activating the OE input line. When OE is inactive HIGH
the output buffers are in their high impedance state.
Enabling or disabling the output buffers will not cause
negative·going transients to appear on the data output
bus.

OUTPUT ENABLE (Input). i5E is an input
control signal which when active LOW
enables the contents of the data latches
onto the data output pin (B o-B 7). OE being
Inactive HIGH forces the output buffers to
their high impedance state.
DATA INPUT PINS (Input). Data presented
at these pins satisfying setup time reo
quirements when STB is strobed and
latched into the data input latches.

D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 0 DC to 70 DC
Storage Temperature ............. - 65 DC to + 150 DC
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages .................. -1.0V to + 5.5V
Power Dissipation .......................... 1 Watt

'COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those Indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS FOR 828218283
Conditions: Vcc= 5V:t: 5%, TA= ODC to 70 DC
Max

Units

Vc

Input Clamp Voltage

-1

V

Icc

Power Supply Current

160

mA

IF

Forward Input Current

-0.2

mA

IR

Reverse Input Current

50

,..A

VOL

Output Low Voltage

0.50

V

IOL = 32 mA

VOH

Output High Voltage

V

10H =

± 50

,..A

VOFF = 0.45 to 5.25V

O.B

V

Vcc =5.0V

V

VCc= 5.0V See Note 1
F-1 MHz
VBIAS=2.5V, Vcc=5V
TA=25 DC

Symbol

Parameter

IOFF

Output Off Current

V IL

Input Low Voltage

V IH

Input High Voltage

C IN

Input Capacitance

Min

2.4

2.0
12

Nol••: 1. Output Loading IOL =32 mA, 10H" - 5 mAo CL =300 pF

8-60

pF

Test Conditions
Ic = -5 mA

VF = 0.45V
..
VR = 5.25V
~5

mA

See Note 1

828218283

A.C. CHARACTERISTICS FOR. 8282/8283
Conditions: Vee =5V ± 5%, T A =0 'C to 70 'C
Loading: Outputs -

= 32 mA, 10H = - 5 mA, C L = 300 pF

10L

Max

Units

Input to Output Delay
-Inverting
- Non-Inverting

25
35

ns
ns

STS to Output Delay
-Inverting
-Non-Inverting

45
55

ns
ns

25

ns

50

ns

------

TIVOV

TSHOV

Min

Parameter

Symbol

(See Note 1)

TEHOZ

Output Disable Time

TElOV

Output Enable Time

10

TIVSl

Input to STS Setup Time

o

ns

TSLIX

Input to STS Hold Time

25

ns

TSHSl

STS High Time

15

ns

----

NOTE: 1. See waveforms and test load circuit on following page.

8282/8283 TIMING

INPUTS

f

------

1:

~TlVSL-----+TSLI:~

,'------------------------

STB J~-lTsHSL--l~----

OUTPUTS

r------1.l_~ec';~~_t=
t-"", __'f-s~E:-E-N--:-O--TE-,-----------

NOTE: 1.8283 ONLY - OUTPUT MAY BE MOMENTARILY INVALID FOLLOWING THE HIGH GOING STB TRANSITION.
2. ALL TIMING MEASUREMENTS ARE MADE AT 1.5V UNLESS OTHERWISE NOTED

B-61

8282/8283
OUTPUT DELAY VS. CAPACITANCE

50

50

8282

8283
40

30

30

20

20

10

200

400

200
pF LOAD

400

600

800

1000

pF LOAD

OUTPUT TEST LOAD CIRCUITS

1.5V

1.5V

33Q

OUT

2.14V

180Q

OUT

OUT

~""
1300 pF

3·STATE TO VOL

3·STATE TO VOH

B-62

SWITCHING

8284
CLOCK GENERATOR AND DRIVER

FOR 8086, 8088, 8089 PROCESSORS
• Generates the System Clock for the
8086, 8088 and 8089

• Generates System Reset Output from
Schmitt Trigger Input

• Uses a Crystal or a TTL Signal for Fre·
quency Source

• Provides Local Ready and MULTIBUS™
Ready Synchronization

• Single

+ 5V Power Supply

• Capable of Clock Synchronization with
other 8284's

• 18·Pin Package

The 8284 is a bipolar clock generator / driver designed to provide clock signals for the 8086, 8088 & 8089 and
peripherals. It also contains READY logic for operation with two MUL TIBUS™ systems and provides the processors
required READY synchronization and timing. Reset logic with hysteresis and synchronization is also provided.

8284 PIN CONFIGURATION

8284 BLOCK DIAGRAM
RESET

x,
CYSNe

VCC

PCLK

X,

AEN1

X2

ROY'

TNK

READY

EFI

RDY2

Fie

AEN2

OSC

ClK

RES

GNO

RESET

X2

Mr------ii>'r--i----OSC

TANK

j---_ClK

Fie --.---[;><>-----L~

EFI-':======l::J
PCLK

CSyNC--------------<--+----'
RDY1----~

CK

AEN1------j

AEN2 ====~~=:C)
ROY2

8284 PIN NAMES
X'I

X21

TANK

FIe
EFI
CSYNC
ROY1 I
RDY2 I
A'E"N1 I
AEN21
RES
RESET
OSC
elK
PClK
READY

Vee
GND

CONNECTIONS FOR CRYSTAL
USED WITH OVERTONE CRYSTAL
CLOCK SOURCE SELECT

EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT

READY StGNAL FROM TWO MULTIBUS™ SYSTEMS
ADDRESS ENABLED QUALIFIERS FOR RDY1,2

RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCillATOR OUTPUT
MOS CLOCK FOR THE PROCESSOR
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+5 VOLTS
0 VOLTS

B-63

READY

8284
PIN DEFINITIONS
Pin

I/O

AEN1,
AEN2

ADDRESS ENABLE. AEN is an active
lOW signal. AEN serves to qualify its
respective Bus Ready Signal (RDY1 or
RDY2). AEN1 validates RDY1 while AEN2
validates RDY2. Two AEN signal inputs
are useful in system configurations
which permit the processor to access
two Multi-Master System Busses. In non
Multi-Master configurations the AEN
signal inputs are tied true (lOW).

RDY1,
RDY2

READY

Pin
Definition

BUS READY (Transfer Complete). ROY is
an active HIGH signal which is an indication from a device located on the system
data bus that data has been received, or
is available. RDY1 is qualified by AEN1
while RDY2 is qualified by AEN2.
0

READY. READY is an active HIGH signal
which is the synchronized ROY signal input. Since ROY occurs asynchronously
with respect to the clock (ClK) it
may be necessary for them to be synchronized before being presented to the
8284. READY is cleared after the
guaranteed hold time to the processor
has been met.

X1, X2,
TNK

CRYSTAL IN. X1 and X2 are the pins to
which a crystal is attached with TNK
(TANK) serving as the overtone input.
The crystal frequency is 3 times the
desired processor clock frequency.

F/C

FREQUENCY/CRYSTAl SELECT. Fie is
a strapping option. When strapped lOW,
FIC permits the processor's clock to be
generated by the crystal. When FIC is
strapped HIGH, ClK is generated from
the EFI input.

EFI

ClK

PClK

EXTERNAL FREQUENCY IN. When FIC
is strapped HIGH, ClK is generated from
the input frequency appearing on this
pin. The input Signal is a square wave 3
times the frequency of the desired ClK
output.

o

o

PROCESSOR CLOCK. ClK is the clock
output used by the processor and all
devices which directly connect to the
processor's local bus (I.e., the bipolar
support chips and other MOS devices).
ClK has an output frequency which is
1/3 of the crystal or EFI inpiJt frequency
and a 1/3 duty cycle. An output HIGH of
4.5 volts (V ce =5V) is provided on this
pin to drive MOS devices.
PERIPHERAL CLOCK. PClK is a TTL
level peripheral clock signal whose output frequency is 1/2 that of ClK and has
a 50% duty cycle.

OSC

1/0

0
level output of the interna"ii:>$<
cuitry. Its frequency is equal tlf"
the crystal.
RESET IN. RES is an active lOW signal
which is used to generate RESET. The
8284 provides a Schmitt trigger input so
that an RC connection can be used to
establish the power-up reset of proper
duration.

RESET

0

RESET. Reset is an active HIGH signal
which is used to reset the 8086 family
processors. Its timing characteristics
are determined by RES.

CSYNC

CLOCK SYNCHRONIZATION. CSYNC is
an active HIGH signal which allows multiple 8284's to be synchronized to provide clocks that are in phase. When
CSYNC is HIGH the internal counters are
reset. When CSYNC goes lOW the internal counters are allowed to resume
counting. CSYNC needs to be externally
synchronized to EFI. When using the internal oscillator CSYNC should be hardwired to ground.

GND

Ground

Vee

+ 5V supply

FUNCTIONAL DESCRIPTION
GENERAL
The 8284 is a single chip clock generator I driver for the
8086, 8088 & 8089 processors. The chip contains a
crystal controlled oscillator, a "divide by three"
counter, complete MULTIBUS™ "Ready" synchronization and reset logic.

OSCillATOR
The oscillator circuit of the 8284 is designed primarily
for use with an external series resonant, fundamental
mode, crystal from which the basic operating frequency
is derived. However, overtone mode crystals can be
used with a tank circuit as shown in Figure 1.

The crystal frequency should be selected at three times
the required CPU clock. X 1 and X2 are the two crystal
input crystal connections.

The output of the oscillator is buffered and brought out
on OSC so that other system timing signals can be
derived from this stable, crystal-controlled source.

B-64

8284

x,

ose

0

eLK

~l

x,

CLOCK
SYNCHRONIZE

PCLK

3 TO 10 pF

8284

EFI>--4

Vee

I

RES

RESET

L

1= 2n)rcr

(TO OTHER 82845)

Figure 2_ CSYNC Synchronization

~,

I

CLOCK OUTPUTS

USED WITH OVERTONE

:
I:

r r
eT

>1

TANK

~~~~~d~~~

e BP

0

CRYSTALS ONLY

The ClK output is a 33% duty cycle MaS clock driver
designed to drive the 8086 processor directly. PClK is a
TTL level peripheral clock signal whose output frequency is 1/2 that of ClK. PClK has a 50% duty cycle.

L_~~_~~~~~~7~_~~

The tank inp-ut to the oscillator allows the use of overtone mode crystals. The tank circuit shunts the crystal's fundamental and high overtone
frequencies and allows the third harmonic to oscillate. The external LC
network is connected to the TANK input and is AC coupled to ground.

RESET lOGIC
The reset logic provides a Schmitt trigger input (RES)
and a synchronizing flip-flop to generate the reset timing. The reset signal is synchronized to the falling edge
of ClK_ A simple RC network can be used to provide
power on reset by utilizing this function of the 8284.

Figure 1

CLOCK GENERATOR
READY SYNCHRONIZATION

The clock generator consists of a synchronous divideby-three counter with a special clear input that inhibits
the counting. This clear input (CSYNC) allows the output clock to be synchronized with an external event
(such as another 8284 clock)_ It is necessary to syrichronize the CSYNC input to the EFI clock external to the
8284_ This is accomplished with two Schottky flip-flops.
(See Figure 2.) The counter output is a 33% duty cycle
clock at one-third the input frequency.

Two READY inputs (RDY1, RDY2) are provided to
accomomodate two Multi-Master system busses. Each
input has a qualifier (AEN1 and AEN2, respectively). The
AEN signals validate their respective RDY signals_ If a
Multi-Master system is not being used the AEN pin
should be tied law.
Synchronization is required for all asynchronous active
going edges of either RDY input to guarantee that the
RDY setup and hold times are met. Inactive going edges
of RDY in normally ready systems do not require synchronization but must satisfy RDY setup and hold as a
matter of proper system design. Synchronization may
be accomplished by inserting a D flip flop between an
asynchronous RDY source and the 8284 and clocking
the flip flop on the rising edge of ClK. The 8284 READY
logic guarantees the required 8086 READY hold time
before clearing the READY signal.

The FIG input is a strapping pin that selects either the
crystal osci lIator or the EFI input as the clock for the -;- 3
counter. If the EF'I input is selected as the ClOCK source,
the oscillator section can be used independently for
another clock source. Output is taken from OSC.

D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias_ . _'" _. _..... _.. 0·Ct070·C
Storage Temperature. _'" _.. __ . _. ~65·C to + 150·C
All Output and Supply Voltages .. ___ . _. ~ 0.5V to + 7V
All Input Voltages .... _. _... _. _. __ .. ~ 1_0V to + 5.5V
Power Dissipation __ . ______ ... _. _. __ . __ ... _.1 Watt

·COMMENT: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specificatioQ is not implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

B-65

8284
D.C. CHARACTERISTICS FOR 8284
Conditions: TA = O·C to 70·C; Vcc= 5V ± 10%

Symbol

Parameter

Min

Max

Units

IF

Forward Input Current

-0.5

mA

V F =0.45V

IR

Reverse Input Current

50

,.,A

V R = 5.25V

Vc

Input Forward Clamp Voltage

Icc

Power Supply Current

V il

Input LOW Voltage

V IH

Input HIGH Voltage

2.0

V IHR

Reset Input HIGH Voltage

2.6

V

Vcc= 5.0V

VOL

Output lOW Voltage

V

5mA

V OH

Output HIGH Voltage ClK
Other Outputs

V

VIHR-VllR

-1.0

V

140

mA

0.8

V

VCC= 5.0V

V

Vcc= 5.0V

0.45

RES Input Hysteresis

Ic= -5 mA

4
2.4

V

-1 mA
-1 mA

0.25

V

Vcc= 5.0V

A.C. CHARACTERISTICS FOR 8284
Conditions: TA

=O°C to 70·C; Vee =5V ± 10%

TIMING REQUIREMENTS
Units

Test Conditions

TEHEl

Symbol

External Frequency High Time

13

ns

90% - 90% VIN

TElEH

External Frequency Low Time

13

ns

10% - 10% VIN

TElEl

EFI Period

TEHEl + TElEH + d

ns

(Note 1)

----

Min

Parameter

XTAl Frequency
TRtVCl

ROYI. ROY2 Set·Up to ClK

TClR1X

t---

Max

12

25

MHz

35

ns

ROY1, ROY2 Hold to ClK

0

ns

TA1VRtv

AEN1, AEN2 Set·Up to ROY1, ROY2

15

ns

TClA1X

AEN1, AEN2 Hold to ClK

0

ns

TYHEH

CSYNC Set·Up to EFI

20

ns

TEHYL

CSYNC Hold to EFI

20

ns

TYHYl

CSYNC Width

2·TElEl

ns

TllHCl

RES Set·Up to ClK

65

ns

(Note 2)

TCLllH

RES Hold to ClK

20

ns

(Note 2)

TIMING RESPONSES
Symbol

Parameter

Min

Max

Units

Test Conditions

--T-C'-lC-l---+--C-l-K-C-y-C-le--p-e-rio-d-------c------1-2-5- - - - + - - - - - - t - - - n - s - - - t - - - - - - - - - - - - - - - - - - - - - ! - - - - - ' - - - - - - - - - - - - - - t - - - - - - - - - - - - - t - - - - - - - t - - - - - -- - - - - - - - - - - - TCHCl
ClK High Time
('!JTClCl)+ 2.0
n5
Fig. 3 & Fig. 4

------t-----=----------f---'-----------r-------t----------t-----::--c--c---_ _T_C_lC_H_ _ -+-__C_l_K_lO_w_Ti_m_e_________-+__--'--W_'T_ClC_l_)_-_15_.0___ r--____ t-_n_s __ tFig. 3 & Fig. 4
TCH1CH2
TCl2Cll

ClK Rise or Fall Time

10

--------!----------------t-----------f----

______+ ___

ns

1.0V to 3.5V

+-________+-____--+__________ .________________ __

TPHPl

PClK High
Time
--'C_
________

TClCl- 20

ns

TPlPH

PClK low Time

TClCl - 20

ns

TRYlCl

Ready Inactive to ClK_(_S_ee_N_o_t_e_4)_--t-_ _ _ _
-s________________n_s __

TRYHCH

Ready Active to ClK (See Note 3)

TCLIl

ClK to Reset Oelay

TCLPH

ClK to PClK High Oelay

- - - - - - + - - - - - - - - - - - - - - - - + - - - - - - - - ----t------- - - - - - - --- - - - - - - - ('!JTClCl)-15.0

ns

40

ns

- - - - - - 1 - - - - - - - - - - - - - - - - - + - - - - - - - ------22

__ _
Fi_g._5~_F_ig_.~_
Fig. 5 & Fig. 6

ns

-------+-------=------'------ t------------- --------- - - - - - - - - __
T_C_LP_L_ _-+___C_L_K~t~o_P__C_L_K_Low Delay
+ __2_2_ _+-____n_s__ __ _ _______________ _
_ -'--T:c,0:c,LC:c,H--'--_-+__0=-S=--C=-:.:to'--C=cL::.cK'--H:.ci"'9:.:.h-=O:c,e:::la"-y______ t--_ _-_5_ _ _ _ _ ~ ___1_2_

ns

_ _T_O_L_C_L_ _.L.-_O_S_C_tO_C_L__Kc.....:.lo'--w....c:.oc..elccay'----_ _ _ _.L.-_____2
_____~ ___2_0_______
n"- ______________ _
Notes: 1. /j

= EFI rise (5 ns max) + EFI fall (5 ns max).

2. Set up and hold only necessary to guarantee recognition at next clock.

3. Applies only to T3 and TW states_
4. Applies only to T2 states.

B-66

8284
n

NAME 110

EFI

I

osc

-J

n.

LJ

\..

oJlJ\..

ClK

PCLK

ROY ,2

0

I

---1,---

i
READyol=:c
""~::
CSYNC

I

RES

I

TEHYL
_TClI'H_I_TI1HCl_

_TYHYL_

\

I

RESET 0
ALL TIMING MEASUREMENTS ARE MADE AT 1.5 VOLTS, UNLESS OTHERWISE NOTED

A.C. TEST CIRCUITS

ClKr---------1

r--:-:---1EFI

5 pF

...r:::-1

ClK r - - - - - 1

FIe!

X,

24 MHzc:::J

X,

Fie
CSYNC

Figure 3. Clock High and Low Time

Figure 4. Clock High and Low Time

B-67

8284

Vee

ClK

nm

I--.,--;EFI

5 pF
24 MHz

~

X,
READY

c:::::]

X,

OSC

Fie
AEN1
1----;RDY2

RDY2
Fie
AE1i12
CSYNC

CSYNC READY't------t
":"

Figure 5. Ready to Clock

Figure 6. Ready to Clock

TEST
POINT

r

LOAD
Vee

800~J

ALL DIODES 1 N3064

OR EOUIVALENT

FROM OUTPUT

UNDER TEST

I

CL
(SEE NOTE 3)

NOTES: 1. CL = 100 pF
2. CL=30 pF
3, CL INCLUDES PROBE AND JIG CAPACITANGE

B-68

M8284
CLOCK GENERATOR AND DRIVER

FOR 8086, 8088, 8089 PROCESSORS
• Generates the System Clock for the
8086, 8088 and 8089

• Generates System Reset Output from
Schmitt Trigger Input

• Uses a Crystal or a TTL Signal for Fre·
quency Source

• Provides Local Ready and MULTIBUS™
Ready Synchronization

• Single

+ 5V Power Supply

• Capable of Clock Synchronization with
other 8284'5

• 18·Pin Package

• Full Military Temperature Range
-55° to + 125°C
The MB2B4 is a bipolar clock generator/driver designed to provide clock signals for the BOB6, BOBB & BOB9 and
peripherals. It also contains READY logic for operation with two MUL TIBUSTM systems and provides the processors
required READY synchronization and timing. Reset logic with hysteresis and synchronization is also provided.

M8284 PIN CONFIGURATION

M8284 BLOCK DIAGRAM
RES--~-=-=-~==~--------ILZ>---~
X1

Vcc
PClK

Xl

AENi

X2

RDYl

TNK

READY

EFI

RDY2

Fie

AEN2

OSC

ClK

RES

GND

RESET

XTAl
X,

Q

RESET

CK

OSCIL·

LATOR

1--1---------c>O----+------osc

TANK

-eLK

Fie
EF!

PCLK

CSYNC----------------------J~_+--.J

RDY'=====l
AEN1

AEN2====~
RDY2

M8284 PIN NAMES
Xli
X21
TANK
Fie
EFI
CSYNC
RDYl I
RDY21

AENi

I

AEN21
RES
RESET
OSC
ClK
PClK
READY
VCC
GNO

CONNECTIONS FOR CRYSTAL
USED WITH OVERTONE CRYSTAL
CLOCK SOURCE SELECT
EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT
READY SIGNAL FROM TWO MULTI BUS'· SYSTEMS
ADDRESS ENABLED QUALIFIERS FOR RDV1.2

RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCillATOR OUTPUT
MOS CLOCK FOR THE PROCESSOR
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+5 VOLTS
o VOLTS

B-69

READY

18284
CLOCK GENERATOR AND DRIVER

FOR 8086, 8088, 8089 PROCESSORS
• Generates the System Clock for the
8086,8088 and 8089

• Generates System Reset Output from
Schmitt Trigger Input

• Uses a Crystal or a TTL Signal for Fre·
quency Source

• Provides Local Ready and MULTIBUS™
Ready Synchronization

• Single

• Capable of Clock Synchronization with
other 8284's

+ 5V Power Supply

• 18·Pin Package

• Industrial Temperature Range
-40° to + 85°C

The 18284 is a bipolar clock generator/driver designed to provide clock signals for the 8086, 8088 & 8089 and
peripherals. It also contains READY logic for operation with two MULTIBUSTM systems and provides the processors
required READY synchronization and timing. Reset logic with hysteresis and synchronization is also provided.

18284 PIN CONFIGURATION

18284 BLOCK DIAGRAM
RESET

Xl

VCC
PCLK

Xl

AEN1

X2

x,

I-----t-----i:>o-~-+---osc

TANK

l-----CLK

ROYl
READY

EFI

RDY2

FIG

AEN2

OSC

ClK

RES

GND

RESET

PCLK

CSYNC-----------~_-+-_~

'EN'

=====1001\

'EN'
RDY2

===jt>~<>-------f'"""\
---LJ

ROY1

po-----t-J

18284 PIN NAMES
Xl'

X2I

CONNECTIONS FOR CRYSTAL

TANK

USED WITH OVERTONE CRYSTAL

FIG

CLOCK SOURCE SElECT

EFI
CSYNC
RDY1 I
ROY2 I

EXTERNAL CLOCK INPUT
CLOCK SYNCHRONIZATION INPUT

AEN11

READY SIGNAL FROM TWO MULTIBUS™ SYSTEMS

AEN2 I

ADDRESS ENABLED aUALIFIERS FOR RDY1,2

RES
RESET
OSC
ClK
PCLK
READY
Vee
GND

RESET INPUT
SYNCHRONIZED RESET OUTPUT
OSCillATOR OUTPUT
MOS CLOCK FOR THE PROCESSOR
TTL CLOCK FOR PERIPHERALS
SYNCHRONIZED READY OUTPUT
+5 VOLTS
0 VOLTS

B-70

CK

READY

8286/8287
OCTAL BUS TRANSCEIVER
• Data Bus Buffer Driver for MCS·8S™,
MCS.80™, MCS.8S™, and MCS·48™
Families
•

High Output Drive Capability for
Driving System Data Bus

•

Fully Parallel 8·Bit Transceivers

•

3·State Outputs

•

20·Pin Package with 0.3" Center

•

No Output Low Noise when Entering
or Leaving High Impedance State

The 8286 and 8287 are 8-bit bipolar transceivers with 3-state outputs. The 8287 inverts the input data at its outputs
while the 8286 does not. Thus, a wide variety of applications for buffering in microcomputer systems can be met.

PIN CONFIGURATIONS

LOGIC DIAGRAMS

r--------,
8287

I

PIN NAMES

B-71

I

8286/8287
4:

Description

Pin

TRANSMIT (Input). T is an input control
signal used to control the direction of the
transceivers. When HIGH, it configures the
transceiver's Bo-B7 as outputs with Ao-A7
as inputs. T LOW configures AO-A? as the
outputs with Bo-B7 serving as the inputs.

T

SYSTEM BUS DATAc'f'fN
These pins serve to either '!Jr~€\nt
or accept data from the sysiWmh
pending upon the state of the T Pi~'~"''~,!'r,:iS;<

8289 MODES OF OPERATION
There are two types of processors in the 8086 family. An
Input/Output processor (the 8089 lOP) and the 8086/8088
CPUs. Consequently, there are two basic operating
modes in the 8289 bus arbiter. One, the lOB (I/O Peripheral Bus) mode, permits the processor access to both
an I/O Peripheral Bus and a multi·master system bus.
The second, the RESB (Resident Bus mode), permits the
processor to communicate over both a Resident Bus
and a multi-master system bus. An I/O Peripheral Bus is
a bus where all devices on that bus, including memory,
are treated as I/O devices and are addressed by I/O com·
mands. All memory commands are directed to another
bus, the multi-master system bus. A Resident Bus can
issue both memory and I/O commands, but it is a distinct and separate bus from the multi-master system
bus. The distinction is that the Resident Bus has only
one master, providing full availability and being
dedicated to that one master.
The lOB strapping option configures the 8289 Bus Ar·
biter into the lOB mode and the strapping option RESB
configures it into the RESB mode. It might be noted at
this point that if both strapping options are strapped
false, the arbiter interfaces the processor to a multi·
master system bus only (see Figure 7). With both options strapped true, the arbiter interfaces the processor

to a multi·master system bus, a
Bus,

r

Ff!lCSi):jl
Y!,;//"hA

In the lOB mode, the processor communi2~~
trois a host of peripherals over the Peripheral Bus,wfT'
the I/O Processor needs to communicate with sysf'/§'!J&,,'i
memory, it does so over the system memory bus. Figure'"
8 shows a possible I/O Processor system configuration.
The 8086 and 8088 processor can communicate with a
Resident Bus and a multi·master system bus. Two bus
controllers and only one Bus Arbiter would be needed in
such a configuration as shown in Figure 9. In such a
system configuration the processor would have access
to memory and peripherals of both busses. Memory
mapping techniques are applied to select which bus is
to be accessed. The SY8B/RESB input on the arbiter
serves to instruct the arbiter as to whether or not the
system bus is to be accessed. The signal connected to
SYSB/RESB also enables or disables commands from
one of the bus controllers.
A summary of the modes that the 8289 has, along with
its response to its status lines inputs, is summarized in
Table 1.
*In some system configurations it is possible for a non-I/O Processor to
have access to more than one Multi·Master System Bus, see 8289
Application Note.

Single
Bus Mos!!

Status Lines From

8086 or 8088 or 8089

52
110
COMMANDS

HALT

51

I~
I~

SO

lOB Mode

RESB (Mode) Only

lOB Mode RESB Mode

lOB = High

r;~0_n~IY~-r.~~~IO~B==_H~i9~h~R~ES~B~=~H~i~9h~~~~~~~IO~B~=_L_O_W__
RE_S~B_=~H~i;9h=-__-}R~E=SB=LOW

iOii = Low

SYSBIAESii = High

SYSBJRESB = Low

SYSBJRESB = High

SYSBJRESB = Low

0

0

MEM
COMMANDS
IDLE

NOTES:
1.
2.

x= Multi-Master System Bus is allowed
V"

= Multi·Master System

to be Surrendered.
Bus is Requested.

Multi·Master System Bus

Pi n
Strap ping

Requested" •

10B= H igh
RESB= Low

Whenever the processor's
status lines go active

RESB Mode Only

10B= H igh
RESB= High

SYSB/RESB = High·
ACTIVE STATUS

lOB Mode Only

10B= Low
RESB= Low

Memory Commands

10B= Low
RESB= High

(Memory Command) •
(SYSB/RESB = High)

Mode

-

-.

Single Bus
Multi·Master Mode

-

----- ---_ .._ . _ - - -

Surrendered"

--,------

---------

HLT+TI. CBRQ+ HPBRQt
--- - - - - - - - - _ . _ - - - - - ----

(SYSB/RESB = Low + TI) •
CBRQ + HLT + HPBRQ
..

---"

-------------~-----

lOB Mode RESB Mode

--,----

----.---

---

---

((I/O Status Commands) +
SYSB/RESB = LOW)) • CBRQ
+ HPBRQt + HLT

NOTES:
• LOCK prevents surrender of Bus to any other arbiter, CROLCK prevents surrender of Bus to any lower priority arbiter.
··Except for HALT and Passive or IDLE Status.

t HPBRO, Higher priority Bus request or BPRN = 1.
1. lOB Active 'Low.
2. RESB Active High.
3, + is read as "OR" and. as "AND,"

4. TI = Processor Idle Status 82, Si, SO = 111
5. HLT= Processor Halt Status 52, Si, SIi=OII

Table 1. Summary of 8289 Modes, Requesting and Relinquishing the Multi·master system bus.

B-84

---

(I/O Status + TI) • CBRQ +
HLT + HPBRQ

8289

D,
8284
CLOCK

READY

ROY2
-::.l..
AEN2 .~ ___

-=

T
-------,--..~---.---,--------,-,-----------_<

ROY1 - - _ .

8289
ARBITER

,
t-

READY
elK

-1

---~---

XACK MUL nMASTER SYSTEM BUS

-------------.--.~,

BUS

-------~--~~-v

CONTROL BUS

elK ANYRQST

lOB

SO·52 AEN RESS

.--l---------vcc

-~

80S6
CPU
AEN

8288

-..J\

_= __~_'-'> ~~S~~~ND
~

MULTI-MASTER

MULTl.MASTER
SYSTEM BUS

BUS

i
PROCESSOR

LOCAL BUS

i

I,
TRANSCEIVER

l/~------

MULTl.MASTER

_ . ----------~~-.~~~-__________\ SYSTEM
---~~-~--~-~~--~---v' DATA
BUS

828618287

Figure 7. Typical Medium Complexity CPU System.

- --!. XACK

XACK 11'0 BUSI /

MULTi-MASTER SYSTEM BUS

8289
BUS

READY
CCK

ARBITER

8EADY eLK--1

SO-52

VC~~:~ ANYROSTR~~~

"N

ADO-AD15 SO

52

MUl HMASTER
SYSTEM BUS

,
--"

V

~ MULTI-MASTER

TRANSCEIVER
8211618287

-

lSYSTEM

-V ~~~A

(2)

Figure 8. Typical Medium Complexity lOB System.

B-85

8289

o
AEN2

AEN11>-----

8284
CLOCK

XACK

- - - - - - XACK MUL HMASTER SYSTEM BUS

RDY11------

RESIOENT BUS

READY

READY

8086
CPU

- - - - - \ MULTI-MASTER SYSTEM

/

COMMAND BUS
MULTI-MASTER
SYSTEM BUS

0'

DECODER

ADDA
LATCH

RESIDENT ADDRESS!~ ,--~--,-----"

\---------1

BUS

RESIDENT DATA

eos

/'--------J\I

828218283

MULTI-MASTER SYSTEM
ADDRESS BUS

(2 OR 3)

"------AJ TR:2~~~;~~ER

12'

MULTI·MASTER SYSTEM
DATA BUS

'BY ADDING ANOTHER 6289 ARBITER AND CONNECTING ITS AEN TO THE 8288
WHOSE AEN IS PRESENTLY GROUNDED, THE PRoceSSOR COULD HAve ACCESS
TO TWO MULTI·MASTER BUSES.

Figure 9. 8289 Bus Arbiter Shown in System· Resident Bus Configuration.

B-86

8289
PIN DEFINITIONS
C''>-h/,

<',:;'

Name

Function

I/O

Vee

+ 5V supply

GND

Ground

SO,51,S2

STATUS INPUT PINS: These pins are
the status input pins from an 8086,
8088 or 8089 processor. The 8289
decodes these pins to initiate bus request and surrender actions. (See
Table 1)

ClK

Name

I/O

± 10%

AEN

SYSB/RESB

COMMON REQUEST lOCK: CRQlCK
is an active low signal which serves to
prevent the arbiter from surrendering
the multi·master system bus to any
other bus arbiter requesting the bus
through the CBRQ input pin.
RESB: RESIDENT BUS is a strapping
option to configure the arbiter to
operate in systems having both a
multi-master system bus and a Resi·
dent Bus. When it is strapped high the
multi·master system bus is requested
or surrendered as a function of the
SYSB/RESB input pin. When it is
strapped low the SYSB/RESB input
is ignored.

ANYRQST

ANY REQUEST: ANYRQST is a strapping option which permits the multimaster system bus to be surrendered
to a lower priority arbiter as though it
were an arbiter of higher priority (i.e.,
when a lower priority arbiter requests
the use of the multi-master system
bus, the bus is surrendered as soon as
it is possible). Strapping CBRQ low
and ANYRQST high forces the 8289 arbiter to surrender the multi-master
system bus after each transfer cycle.
Note that when surrender occurs
BREQ is driven false (high).
10 BUS: lOB is a strapping option
which configures the 8289 Arbiter to
operate in systems having both an 10
Bus (Peripheral Bus) and a multimaster system bus. The arbiter reo
quests and surrenders the use of the
multi-master system bus as a function
of the status line, S2. The multi-master
system bus is permitted to be surrendered while the processor is perfor-

3".,.

ming 10 commands and is reques
whenever the processor performs a
memory command. Interrupt cycles
are assumed as coming from the
peripheral bus and are treated as
would be an 10 command.

CLOCK: This is the clock from the
8284 clock chip and serves to
establish when bus arbiter actions are
initiated.
lOCK: lOCK is a processor generated
signal which when activated (low)
serves to prevent the arbiter from sur·
rendering the multi-master system bus
to any other bus arbiter, regardless of
its priority.

RESB

Function ,.,.,.

a

ADDRESS ENABLE. AEN is the output
of the 8289 Arbiter to the processor's
address latches, to the 8288 Bus Controller and 8284 Clock Generator. AEN
serves to instruct the Bus Controller
and address latches when to tri-state
their output drivers.
SYSTEM
BUS/=R-=E-=S""'ID=-E=Nc="T BUS:
SYSB/RESB is an input signal when
the arbiter is configured in the S.R.
Mode (RESB is strapped high) which
serves to determine when the multimaster system bus is requested and
when the multi-master system bus surrendering is permitted. The signal is intended to originate from some form of
address mapping circuitry such as a
decoder or PROM attached to the resident address bus. Signal transitions
and glitches are permitted on this pin
from 01 of T4 to 0 1 to T2 of the processor cycle. During the period from
01 of T2 to 01 of T4 only clean transitions are permitted on this pin (no
glitches). If a glitch does occur the arbiter may capture or miss it, and the
multi-master system bus may be requested or surrendered, depending
upon the state of the glitch. The arbiter
requests the multi-master system bus
in the S.R. Mode when the state of the
SYSB/RESB pin is high and permits
the bus to be surrendered when this
pin is low.

I/O COMMON BUS REQUEST: CBRQ is an
input signal which serves to instruct
the arbiter if there are any other arbiters of lower priority requesting the
use of the multi-master system bus.
The CBRQ pins (open-collector output)
of all the 8289 Bus Arbiters which are
to surrender the multi-master system
bus upon request are connected
together.
The Bus Arbiter running the current
transfer cycle will not itself pull the
CBRQ line low. Any other arbiter connected to the CBRQ line can request
the multi-master system bus. The arbiter presently running the current
transfer cycle drops its BREQ signal
and surrenders the bus whenever the

B-87

8289
PIN DEFINITIONS (Cont'd)
Name________
I/_O_____________
F_u_nc_t_io~n___________

Name

1/0
__

o

INITIALIZE: 'iNTf is an active low multimaster system bus input signal which
is used to reset all the bus arbiters on
the multi-master system bus. After initialization, no arbiters have the use of
the multi-master system bus.

BUS PRIORITY OUT: BPRO is an active
low output signal which is used in the
serial priority resolving scheme where
BPRO is daisy chained to BPRN of the
next lower priority arbiter.

110 BUSY: BUSY is an active low open collector multi-master system bus interface signal which is used to instruct
all the arbiters on the bus when the
multi-master system bus is available.
When the multi-master system bus is
available the highest requesting arbiter (determined by BPRN) seizes the
bus and pulls BUSY low to keep other
arbiters off of the bus. When the arbiter is done with the bus it releases
the BUSY signal permitting it to go
high and thereby allowing another arbiter to acquire the multi-master
system bus.

BUS CLOCK: BClK is the multi-master
system bus clock to which all multimaster system bus interface signals
are synchronized.

o

£>c/ f ,""

edge of BClK. BPRN indicates toe
arbiter that it is the highest priority r
questing arbiter presently on the bus.
The loss of BPRN instructs the arbiter
that it has loss priority to a higher
priority arbiter.

proper surrender conditions exist.
Strapping CBREQ low and ANYRQST
high allows the multi-master system
bus to be surrendered after each
transfer cycle. See the pin definition of
ANYRQST.

BUS REQUEST: BREQ is an active low
output signal in the parallel Priority
Resolving Scheme which the arbiter
activates to request the use of the
multi-master system bus.
BUS PRIORITY IN: BPRN is the active
low signal returned to the arbiter to instruct it that it may acquire the multimaster system bus on the next falling

B-88

8289
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ................ O'C to 70'C
Storage Temperature. .
. .... - 65 'C to + 150'C
All Output and Supply Voltages ........ - 0.5V to + 7V
All Input Voltages...
. ...... -1.0V to + 5.5V
Power Dissipation ......................... 1.5 Watt

COMMENT: Stresses above those listed under
Ratings" may cause permanent damage to the device.
rating only and functional operation of the device at these
conditions above those indicated in the operational sections
specification is not implied. Exposure to absolute maximum rating
dltions for extended periods may affect device reliability.

D.C. CHARACTERISTICS FOR THE 8289

Symbol

Parameter

Max.

Units

Ve

Input Clamp Voltage

- 1.0

V

IF

Input Forward Current

-0.5

rnA

Vee=5.50V, V F =0.45V

IR

Reverse Input Leakage Current

60

I'A

Vee = 5.50, V R = 5.50

VOL

Output Low Voltage
BUSY,CBRQ
AEN
BPRO,BREQ

0.45
0.45
0.45

V
V
V

IOl = 20 rnA, C l = 250 pF 1)
IOl= 16 rnA, Cl= 100 pF 2)
10l= 10 rnA, Cl= 60 pF 3)

V

IOH= 400 I'A

V OH

Min.

Output High Voltage
BUSY,CBRQ

Open Collector

All Other Outputs
Icc

Power Supply Current

V1l

Input Low Voltage

V1H

Input High Voltage

Cin Status
Cin (Others)

Test Condition
Vee=4.50V, le= -5 rnA

2.4
165

rnA

.8

V

Input Capacitance

25

pF

Input Capacitance

12

pF

2.0

V

TEST CIRCUITS:
1) BUSY. CBRa

2) AEN
2.3V

3) BPRO, BREO
2.3V

92.5Q

110Q

1100PF

B-89

2.3V

170Q

8289
A.C. CHARACTERISTICS FOR THE 8289
CONDITIONS:

Vcc=5V ± 10%, TA=O·C to 70·C

Timing Requirements
Symbol

Parameter

Max.

Min.

Unit

TClCl

ClK Cycle Period

125

ns

TClCH

ClK low Time

65

ns

TCHCl

ClK High Time

35

TSVCH

Status Active Setup

65

TClCl·10

ns

TSHCl

Status Inactive Setup

50

TClCl·10

ns

THVCH

Status Active Hold

10

ns

THVCl

Status Inactive Hold

10

ns

TBYSBl

BUSYNSetup to

BClK~

20

ns

TCBSBl

CBRONSetup to

BClK~

20

ns

100

ns

TBlBl

BClK Cycle Time

\

ns

BClK High Time

30

lOCK Inactive Hold

20

ns

TClll2

lOCK Active Setup

40

ns

TPNBl

BPRN~tto

15

ns

TClSR1

SYSB/~ Setup

0

ns

TClSR2

SYSB/11Em:! Hold

20

ns

TIVIH

Initialization Pulse Width

3 TBlBl+
3 TClCl

ns

BClK Setup Time

.65[TBlBlJ

ns

TBHCl
TClll1

Timing Responses
Max.

Unit

TBlBRl

BClK to BREO DelayH

35

ns

TBlPOH

BClK to BPROH (See Note 1)

40

ns

TPNPO

BPRNHto BPROHDelay
(See Note 1)

25

ns

TBlBYl

BClK to BUSY low

60

ns

TBlBYH

BClK to BUSY Float (See Note 2)

35

ns

TClAEH

ClK to AEN High

65

ns

TBlAEl

BClK to AEN low

40

ns

TBlCBl

BClK to CBRO low

60

ns

TBlCBH

BClK to CBRO Float (See Note 2)

35

ns

Symbol

Parameter

Min.

It Denotes that spec applies to both transitions of the signal.
NOTE 1: BCLK generates the first BPRO wherein subsequent BPRO changes lower in the chain are generated through BPRN.
NOTE 2: Measured at .5V above GND.

INITIALIZATION:

(lNIT can be either pulsed or held low through power up)

------~->-------f.

Vee AT sv

TNff

::t10%~

_

r---TIVIH

B-90

OPERATION

loading

8289
8289 TIMING DIAGRAM
STATE - - T 4 - - - r - - - T 1 - - - - - - T 2 - - - - - - - T ,

CLK

r---TClCL

LOCK
(SEE NOTE 1)

SYSBIRESB

ill
(SEE NOTE 3)

PROCESSOR ClK RELATED

BUS ClK RELATED

BCLKJ)J
TBlBRl -~I

1-

BPRN #2

(BPRO

#1)

1Il'11O #2
(BPRN #3)

CBRQ

NOTES:
1. lOCK ACTIVE CAN OCCUR DURING ANY T STATE, AS lONG AS THE RELATIONSHIPS
SHOWN ABOVE WITH RESPECT TO THE CLK ARE MAINTAINED. LOCK INACTIVE HAS
NO CRITICAL TIME AND CAN BE ASYNCHRONOUS.
-CRQlCK HAS NO CRITICAL TIMING AND IS CONSIDERED AN ASYNCHRONOUS INPUT
SIGNAL
2. GLITCHING OF SYSBIRESB PIN IS PERMITTED DURING THIS TIME. AFTERI2l2 OF T1,
AND BEFORE 01 OF T4, ONLY CLEAN TRANSITIONS ARE ACCEPTED.
3. AE"KI lEADING EDGE IS RELATED TO iJC[R", TRAILING EDGE TO ClK. THE TRAILING
EDGE OF AEN OCCURS AFTER BUS PRIORITY IS LOST.

ADDITIONAL NOTES:
The signals related to ClK are typical processor signals, and do not relate to the depicted sequence of events of the
signals referenced to BClK. The signals shown related to the BClK represent a hypothetical sequence of events for
illustration. Assume 3 bus arbiters of priorities 1,2 and 3 configured in s,erial priority resolving scheme as shown in
Figure 6. Assume arbiter 1 has the bus and is holding busy low. Arbiter #2 detects its processor wants the bus and
puils low BREO#2. If BPRN#2 is high (as shown), arbiter #2 will pull low CBRO line. CBRO signals to the higher priority
arbiter #1 that a lower priority arbiter wants the bus. [A higher priority arbiter would be granted BPRN when it makes
the bus request rather than having to wait for another arbiter to release the bus through~.'· Arbiter#1 will relinquish the multi-master system bus when it enters a state not requiring it (see Table 1), by lowering its BPRO#1 (tied to
BPRN#2) and releasing BUSY_ Arbiter #2 now sees that it has priority from BPRN#2 being low and releases CBRO. As
soon as BUSY signifies the bus is available (high), arbiter #2 pulis BUSY low on next falling edge of BClK_ Note that if
arbiter #2 didn't want the bus at the time it received priority, it would pass priority to the next lower priority arbiter by
lowering its BPRO #2 [TPNPO],
""Note that even a higher priority arbiter which is acquiring the bus through BPAN will momentarily drop CBAQ until it has acquired the bus.

B-91

8237/8237·2
HIGH PERFORMANCE
PROGRAMMABLE DMA CONTROLLER
Control of Individual
• Enable/Disable
DMA Requests

Performance: Transfers up to 1.6M
• High
Bytes/Second with 5 MHz 8237-2

• Four Independent DMA Channels

Directly Expandable to any Number of
• Channels

Independent Autoinitialization of all
• Channels

End of Process Input for Terminating
• Transfer,s

• Memory-to-Memory Transfers
• Memory Block Initialization
• Address Increment or Decrement

• Software DMA Requests
Independent Polarity Control for DREQ
• and
DACK Signals

The 8237 Multimode Direct Memory Access (DMA) Controller is a peripheral interface Circuit for microprocessor systems. It is designed to improve system performance by allowing external devices to directly transfer information to or
from the system memory. Memory·to-memory transfer capability is also provided. The 8237 offers a wide variety of programmable control features to enhance data throughput and system optimization and to allow dynamic reconfiguration under program control.
The 8237 is designed to be used in conjunction with an external 8-bit address register such as the 8282. It contains
four independent channels and may be expanded to any number of channels by cascading additional controller chips.
The three basic transfer modes allow programmability of the types of DMA service by the user. Each channel can be
individually programmed to Autoinitialize to its original condition following an End of Process (EOP).
Each channel has a full 64K address and word count capability.
The 8237-2 is a 5 MHz selected version of the standard 3 MHz 8237.

iOA

1::

1

lOW [ 2
MEMR i" 3
r.U:'MW I

q

40
39

I
J

A7
AS

38.1 AS
37

J

A4

36:J

t-()j'

3::' J Aj
AU:;T(!:

il

AfN;

9

COMMAND

HRQ

CONrROt

cs
eLK

_ _D~._~~

v

I Al

r~ 11

I.

,?

ri
1~

DACK3

L
l

lS

OAE03

r

16

I)A(;I(:.<

I A'i

3J

10

f

R£Sf:1

'--_ _-' .-----

r

34

oa,

OIl.CKO

DB,
(GNDIVss

Figu",

BLOCK DIAGRAM

B-92

"'------,

Pill Configuration

8237/8237-2
PIN DEFINITIONS
Vee:

+ 5 volt supply

Vss: Ground
ClK (Clock, Input)
This input controls the internal operations of the 8237
and its rate of data transfers. The input may be driven at
up to 3 MHz for the standard 8237 and up to 5 MHz for
the 8237-2.
CS (Chip Select, Input)
Chip Select is an active low input used to select the
8237 as an I/O device during the Idle cycle. This allows
CPU communication on the data bus.
RESET (Reset, Input)
Reset is an asynchronous active high input which clears
the Command, Status, Request and Temporary registers. It also clears the first/last flip/flop and sets the
Mask register. Following a Reset the device is in the Idle
cycle.
READY (Ready, Input)
Ready is an input used to extend the memory
read and write pulses from the 8237 to accommodate
slow memories or I/O peripheral devices.
HlDA (Hold Acknowledge, Input)
The active high Hold Acknowledge from the CPU Indicates that control of the system buses have been relinquished.

lOR (1/0 Read, Input/Output)
I/O Read is a bidirectional active low three-state line. In
the Idle cycle, it is an input control signal used by the
CPU to read the control registers. In the Active cycle, it
is an output control signal used by the 8237 to access
data from a peripheral during a DMA Write transfer.
lOW (I/O Write, Input/Output)
I/O Write is a bidirectional active low three-state line. In
the Idle cycle, it is an input control signal used by the
CPU to load information into the 8237. In the Active
cycle, it is an output control signal used by the 8237 to
load data to the peripheral during a DMA Read transfer.
EOP (End of Process, Input/Output)
EOP is an active low bidirectional signal. Information
concerning the completion of DMA services is available
at the bidirectional EOP pin. The 8237 allows an external
signal to terminate an active DMA service. This is accomplished by pulling the EOP input low with an external EOP signal. The 8237 also generates a pulse when
the terminal count (TC) for any channel is reached. This
generates an EOP signal which is output through the
EOP Line. The reception of EOP, either internal or external, will cause the 8237 to terminate the service, reset
the request, and, if Autoinitialize is enabled, to write the
base registers to the current registers of that channel.
The mask bit and TC bit in the status word will be set for
the currently active channel by EOP unless the channel
is programmed for Autoinitialize. In that case, the mask
bit remains clear. During memory-to-memory transfers,
EOP will be output when the TC for channel 1 occurs.
EOP should be tied high with a pull-up resistor if it is not
used to prevent erroneous end of process inputs.

DREQO-DREQ3 (DMA Request, Input)

AO-A3 (Address, Input/Output)

The DMA Request lines are individual asynchronous
channel request inputs used by peripheral circuits to
obtain DMA service. In Fixed Priority, DREQO has the
highest priority and DREQ3 has the lowest priority. A
request is generated by activating the DREQ line of a
channel. DACK will acknowledge the recognition of
DREQ signal. Polarity of DREQ is programmable. Reset
initializes these lines to active high. DREQ must be
maintained until the corresponding DACK goes active.

The four least significant address lines are bidirectional
three-state signals. In the Idle cycle they are inputs and
are used by the 8237 to address the control register to
be loaded or read. In the Active cycle they are outputs
and provide the lower 4 bits of the output address.

DBO-DB7 (Data Bus, Input/Output)

A4-A7 (Address, Output)
The four most significant address lines are three-state
outputs and provide 4 bits of address. These lines are
enabled only during the DMA service.

The Data Bus lines are bidirectional three-state signals
connected to the system data bus. The outputs are
enabled in the Program Condition during the I/O Read to
output the contents of an Address register, a Status
register, the Temporary register or a Word Count
register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is
programming the 8237 control registers. During DMA
cycles the most significant 8 bits of the address are output onto the data bus to be strobed into an external
latch by ADSTB. In memory-to-memory operations, data
from the memory comes into the 8237 on the data bus
during the read-from-memory transfer. In the write-tomemory transfer, the data bus outputs place the data into the new memory location.

HRQ (Hold Request, Output)
This is the Hold Request to the CPU and is used to request control of the system bus. If the corresponding
mask bit is clear, the presence of any valid DREQ
causes the 8237 to issue the HRQ. After HRQ goes
active at least one clock cycle (TCY) must
occur before HLDA goes active.
DACKO-DACK3 (DMA Acknowledge, Output)
DMA Acknowledge is used to notify the individual
peripherals when one has been granted a DMA cycle.
The sense of these lines is programmable. Reset initializes them to active low.

B-93

8237/8237-2
AEN (Address Enable, Output)

DMA OPERATION

This output enables the 8-bit latch containing the upper
8 address bits onto the system address bus_ AEN can
also be used to disable other system bus drivers during
DMA transfers. AEN is active HIGH.

The 8237 is designed to operate in two major cycles.
These are called Idle and Active cycles. Each device
cycle is made up of a number of states. The 8237 can
assume seven separate states, each composed of one
full clock period. State I (SI) is the inactive state. It is
entered when the 8237 has no valid DMA requests pending. While in SI, the DMA controller is inactive but may
be in the Program Condition, being programmed by the
processor. State a (SO) is the first state of a DMA service. The 8237 has requested a hold but the processor
has not yet returned an acknowledge. An acknowledge
from the CPU will signal that transfers may begin. SI,
S2, S3 and S4 are the working states of the DMA service.
If more time is needed to complete a transfer than is
available with normal timing, wait states (SW) can be inserted between S2 or S3 and S4 by the use of the Ready
line on the 8237.

ADSTB (Address Strobe, Output)
The active high Address Strobe is used to strobe the upper address byte into an external latch.
MEMR (Memory Read, Output)
The Memory Read signal is an active low three-state output used to access data from the selected memory location during a DMA Read or a memory-lo-memory transfer.
MEMW (Memory Write, Output)
The Memory Write signal is an active low three-state
output used to write data to the selected memory location during a DMA Write or a memory-to-memory trans·
fer.

Memory-to-memory transfers require a read-from and a
write-to-memory to complete each transfer. The states,
which resemble the normal working states, use two
digit numbers for identification. Eight states are required for a single transfer. The first four states (SII,
S12, S13, S14) are used for the read-from-memory half
and the last four states (S21, S22, S23, S24) for the writeto-memory half of the transfer.

FUNCTIONAL DESCRIPTION
The 8237 block diagram includes the major logic blocks
and all of the internal registers. The data interconnection paths are also shown. Not shown are the various
control signals between the blocks. The 8237 contains
344 bits of internal memory in the form of registers.
Figure 2 lists these registers by name and shows the
size of each. A detailed description of the registers and
their functions can be found under Register Description.
Name

8ase Address Registers
Base Word Count Registers

Current Address Registers
Current Word Count Registers
Temporary Address Register
Temporary Word Count Register
Status Register
Command Register
Temporary Register
Mode Registers

Mask Register
Request Register

Size

Number

16 bits
16bits
16bits
16 bits
16 bits
16bits
8bits
8 bits
8 bits
6bits
4 bits

4
4
4
4
1
1
1
1

4bits

1

1
4
1

Figure 2_ 8237 Internal Registers
The 8237 contains three basic blocks of control logic.
The Timing Control block generates internal timing and
external control signals for the 8237. The Program Command Control block decodes the various commands
given to the 8237 by the microprocessor prior to servicing a DMA Request. It also decodes the Mode Control
word used to select the type of DMA during the servicing. The Priority Encoder block resolves priority contention between DMA channels requesting service simultaneously.

IDLE CYCLE
When no channel is requesting service, the 8237 will
enter the Idle cycle and perform "SI" states. In this
cycle the 8237 will sample the DREQ lines every clock
cycle to determine if any channel is requesting a DMA
service. The device will also sample CS, looking for an
attempt by the microprocessor to write or read the internal registers of the 8237. When CS is low and HRQ is
low, the 8237 enters the Program Condition. The CPU
can now establish, change or inspect the internal definition of the part by reading from or writing to the internal
regilOters. Address lines AO-A3 are inputs to the device
and select which registers will be read or written. The
lOR and lOW lines are used 10 select and time reads or
writes. Due to the number and size of the internal registers, an internal flip-flop is used to generate an additional bit of address. This bit is used to determine the
upper or lower byte of the 16-btl Address and Word
Count registers. The flip-flop is reset by Master Clear or
Reset. A separate software command can also reset this
flip-flop.
Special software commands can be executed by the
8237 in the Program Condition. These commands are
decoded as sets of addresses with the CS and lOW. The
commands do not make use of the data bus. Instructions include Clear First/Last Flip-flop and Master Clear.
ACTIVE CYCLE
When the 8237 is in the Idle cycle and a channel requests a DMA service, the device will output an HRQ to
the microprocessor and enter the Active cycle. It is in
this cycle that the DMA service will take place, in one of
four modes:

The Timing Control block derives internal timing from
the clock input. In 8237 systems this input will usually
be the +2 TTL clock from an 8224 or ClK from an 8085A.
However, any appropriate system clock will suffice.

Single Transfer Mode - In Single Transfer mode the
device is programmed to make one transfer only. The

B-94

8237/8237-2
and Verify. Write transfers move data from an 1/0 device
to the memory by activating MEMW and lOR. Read
transfers move data from memory to an 1/0 device by ac·
tivating MEMR and lOW. Verify transfers are pseudo
transfers. The 8237 operates as in Read or Write trans·
fers generating addresses, and responding to EOP, etc.
However, the memory and I/O control lines all remain
inactive.

word count will be decremented and the address decre·
mented or incremented following each transfer. When
the word count goes to zero, a Terminal Count (TC) will
cause an Autoinitialize if the channel has been program·
med to do so.
DREQ must be held active until DACK becomes active in
order to be recognized. If DREQ is held active through·
out the single transfer, HRQ will go inactive and release
the bus to the system. It will again go active and, upon
receipt of a new HLDA, another single transfer will be
performed. In 8080A/8085A systems this will ensure one
full machine cycle execution between DMA transfers.
Details of timing between the 8237 and other bus con·
trol protocols will depend upon the characteristics of
the microprocessor involved.

2ND LEVEL

!-'---

Block Transfer Mode - In Block Transfer mode the
device is activated by DREQ to continue making trans·
fers during the service until a TC, caused by word count
going to zero, or an external End of Process (EOP) is en·
countered. DREQ need only be held active until DACK
becomes active. Again, an Autoinitialization will occur
at the end of the service if the channel has been pro·
grammed for it.
Demand Transfer Mode - I n Demand Transfer mode the
device is programmed to continue making transfers un·
til a TC or external EOP is encountered or until DREQ
goes inactive. Thus transfers may continue until the 1/0
device has exhausted its data capacity. After the 1/0
device has had a chance to catch up, the DMA service is
re·established by means of a DREQ. During the time
between services when the microprocessor is allowed
to operate, the Intermediate values of address and word
count are stored in the 8237 Current Address and Cur·
rent Word Count registers. Only an EOF can cause an
Autoinitialize at the end of the service. EOP is generated
either by TC or by an external signal.
Cascade Mode - This mode is used to cascade more
than one 8237 together for simple system expansion.
The HRQ and HLDA signals from the additional 8237
are connected to the DREQ and DACK signals of a chan·
nel of the Initial 8237. This allows the DMA requests of
the additional device to propagate through the priority
network circuitry of the preceding device. The priority
chain Is preserved and the new device must wait for its
turn to acknowledge requests. Since the cascade chan·
nel in the initial device is used only for prioritizing the
additional device, it does not output any address or con·
trol signals of its own. These would conflict with the
outputs of the active channel in the added device. The
823iwill respond to DREQ and DACK but all other out·
puts except HRQ will be disabled.
Figure 3 shows two additional devices cascaded into an
initial device using two of the previous channels. This
forms a two level DMA system. More 8237s could be
added at the second level by using the remaining chan·
nels of the first level. Additional devices can also be
added by cascading into the channels of the second
level devices, forming a third level.
TRANSFER TYPES

Each of the three active transfer modes can perform
three different types of transfers. These are Read, Write

8231

1ST LEVEL

MICROPROCESSOR

HRO

DREQ

HLDA

DACK

--

-

HRO

HlDA

8237

DREQ

DACK

INITIAL DEVICE

--

HRO
HLDA

8237

ADDITIONAL
DEVICES

Figure 3. Cascaded 8237s
Memory·to·Memory - To perform block moves of data
from one memroy address space to another with a mini·
mum of program effort and time, the 8237 includes a
memory·to·memory transfer feature. Programming a bit
in the Command register selects channels 0 and 1 to
operate as memory·to·memory transfer channels. The
transfer is initiated by setting the software DREQ for
channel O. The 8237 requests a DMA service in the nor·
mal manner. After HLDA is true, the device, using eight·
state transfers in Block Transfer mode, reads data from
the memory. The channel 0 Current Address register is
the source for the address used and is decremented or
incremented in the normal manner. The data byte read
from the memory is stored in the 8237 internal Tempo·
rary register. Channel 1 then writes the data from the
Temporary register to memory using the address in its
Current Address register and incrementing or decre·
menting it in the normal manner. The channel 1 Current
Word Count is decremented. When the word count of
channel 1 goes to zero, a TC is generated causing an
EOP output, terminating the service.
Channel 0 may be programmed to retain the same ad·
dress for all transfers. This allows a single word to be
written to a block of memory.
The 8237 will respond to external EOP signals during
memory·to·memory transfers. Data comparators in
block search schemes may use this input to terminate
the service when a match is found. The timing of
memory·to·memory transfers is found in Diagram 4.
Memory·to-memory operations can be detected as
an active AEN with no DACK outputs.
Autoinitialize - By programming a bit In the Mode reg·
ister, a channel may be set up as an Autoinitialize

B-95

8237/8237-2
channel. During Autoinitialize initialization, the original
values of the Current Address and Current Word Count
registers are automatically restored from the Base Ad·
dress and Base Word Count registers of that channel
following EOP. The base registers are loaded simultane·
ously with the current registers by the microprocessor
and remain unchanged throughout the DMA service. The
mask bit is not set when the channel is in Autoinitialize.
Following Autoinitialize the channel is ready to perform
another service without CPU intervention.

During Block and Demand Transfer mode services,
which include multiple transfers, the addresses gener·
ated will be sequential. For many transfers the data held
in the external address latch will remain the same. This
data need only change when a carry or borrow from A7
to A8 takes place in the normal sequence of addresses.
To save time and speed transfers, the 8237 executes S1
states only when updating of A8-A15 in the latch is
necessary. This means for long services, S1 states may
occur only once every 256 transfers, a savings of 255
clock cycles for each 256 transfers.

Priority - The 8237 has two types of priority encoding
available as software selectable options. The first is
Fixed Priority which fixes the channels in priority order
based upon the descending value of their number. The
channel with the lowest priority is 3 followed by 2, 1 and
the highest priority channel, O. After the recognition of
anyone channel for service, the other channels are pre·
vented from interferring with that service until it is com·
pleted.

REGISTER DESCRIPTION
Current Address Register - Each channel has a 16·bit
Current Address register. This register holds the value
of the address used during DMA transfers. The address
is automatically incremented or decremented after each
transfer and the intermediate values of the address are
stored in the Current Address register during the
transfer. This register is written or read by the micro·
processor in successive 8·bit bytes. It may also be reo
initialized by an Autoinitialize back to its original value.
Autoinitialize takes place only after an EOP.

The second scheme is Rotating Priority. The last chan·
nel to get service becomes the lowest priority channel
with the others rotating accordingly.
1st
Service

2nd
Service

3rd
Service

2-.- \3 -.. -

highest

o

lowest

1......-service\. 3-..-request
2
,0
3
1

service

service

0
1
2

With Rotating Priority in a single chip DMA system, any
device requesting service is guaranteed to be recog·
nized after no more than three higher priority services
have occurred. This prevents anyone channel from
monopolizing the system.
Compressed Timing - In order to achieve even greater
throughput where system characteristics permit, the
8237 can compress the transfer time to two clock
cycles. From Timing Diagram 3 it can be seen that state
S3 is used to extend the access time of the read pulse.
By removing state S3, the read pulse width is made
equal to the write pulse width and a transfer consists
only of state S2 to change the address and state S4 to
perform the read/write. S1 states will still occur when
A8-A 15 need updating (see Address Generation). Tim·
ing for compressed transfers is found in Diagram 6.
Address Generation - In order to reduce pin count, the
8237 multiplexes the eight higher order address bits on
the data lines. State S1 is used to output the higher
order address bits to an external latch from which they
may be placed on the address bus. The falling edge of
Address Strobe (ADSTB) is used to load these bits from
the data lines to the latch. Address Enable (AEN) is used
to enable the bits onto the address bus through a three·
state enable. The lower order address bits are output by
the 8237 directly. Lines AO-A7 should be connected to
the address bus. Timing Diagram 3 shows the time rela·
tionships between ClK, AEN, ADSTB, DBO-DB7 and
AO-A?

Current Word Register - Each channel has a 16·bit Cur·
rent Word Count register. This register holds the num·
ber of transfers to be performed. The word count is
decremented after each transfer. The intermediate value
of the word count is stored in the register during the
transfer. When the value in the register goes to zero, a
TC will be generated. This register is loaded or read in
successive 8·bit bytes by the microprocessor in the Pro·
gram Condition. Following the end of a DMA service it
may also be reinitialized by an Autoinitialization back to
its original value. Autoinitialize can occur only when an
EOP occurs.
Base Address and Base Word Count Registers - Each
channel has a pair of Base Address and Base Word
Count registers. These 16·bit registers store the original
value of their associated current registers. During Auto·
initialize these values are used to restore the current
registers to their original values. The base registers are
written simultaneously with their corresponding current
register in 8·bit bytes in the Program Condition by the
microprocessor. These registers cannot be read by the
microprocessor.
Command Register - This 8·bit register controls the
operation of the 8237. It is programmed by the micro·
processor in the Program Condition and is cleared by
Reset. The following table lists the function of the com·
mand bits. See Figure 6 for address coding.
Mode Register - Each channel has a 6·bit Mode regis·
ter associated with it. When the register is being written
to by the microprocessor in the Program Condition, bits
o and 1 determine which channel Mode register is to be
written.
Request Register - The 8237 can respond to requests
for DMA service which are initiated by software as well
as by a DREQ. Each channel has a request bit associ·
ated with it in the 4·bit Request register. These are non·

B-96

8237/8237 -2
maskable and subject to prioritization by the Priority Encoder network. Each register bit Is set or reset sepa·
rately under software control or Is cleared upon genera·
tlon of a TC or external EOP. The entire register is
cleared by a Reset. To set or reset a bit, the software
loads the proper form of the data word. See Figure 4 for
address coding.
Command Register
7

8

5

4

3

2

1

0 _ B i t Number

I I I I I I I I I
0
1

Memory·to-memory disable
Memory.to.memory enable

0
1
X

Channel 0 address hold disable
Channel 0 address hold enable
If bit 0=0

0
1

Controller enable
Controller disable

0
1
X

Normal timing
Compressed timing
If bit 0=1

0

I

Fixed priority
Rotating priority

J°
1
IX

Late write selection
Extended write selection
If bit 3=1

---1

,,

0

I

Mask Register - Each channel has associated with It a
mask bit which can be set to disable the Incoming
DREQ. Each mask bit is set when Its associated channel
produces an ~ If the channel Is not programmed for
Autoinitialize. Each bit of the 4·bit Mask register may
also be set or cleared separately under software control.
The entire register Is also set by a Reset. This disables
all DMA requests until a clear Mask register Instruction
allows them to occur. The Instruction to separately set
or clear the mask bits is similar in form to that used with
the Request register. See Figure 4 for Instruction ad·
dressing.
7

8

5

4

3

2

1

0_

Select
Select
Select
Select
'--_ _-( 0
1

o
1

Clear channel 0 mask bit
Set channel 0 mask bit

o
1

Clear channell mask bit
Set channell mask bit

1

Clear channel 2 mask bit
Set channel 2 mask bit

' -_ _ _- { 0
1

Clear channel 3 mask bit
Set channel 3 mask bit

Channel 0 select
Channell select
Channel 2 select
Channel 3 select
00
01
10
11
XX

Verify transfer
Write transfer
Read transfer
Illegal
If bits 6 and 7= 11

0
1

Autoinitialization disable
Autoinitialization enable

0
1

Address Increment select
Address decrement select

00
01
10
11

Demand mode select
Single mode select
Block mode select
Cascade mode select

Register
Command
Mode
Request
Mask
Mask
Temporary
Status

Signals

Operation
Write
Write
Write
Set/Reset
Write
Read
Read

CS

lOR

lOW

A3

A2

A1

AD

0
0
0
0
0
0
0

1
1
1
1
1
0
0

0
0
0
0
0
1
1

1
1
1
1
1
1
1

0
0
0
0
1
1
0

0
1
0
1
1
0
0

0
1
1
0
1
1
0

Figure 4. Definition of Register Codes
Status Register - The Status register is available to
be read out of the 8237 by the microprocessor. It contains information about the status of the devices at this
point. This information includes which channels have
reached a terminal count and which channels have
pending DMA requests. Bits 0-3 are set every time a TC
is reached by that channel or an external EOP
is applied. These bits are cleared upon Reset
and on each Status Read. Bits 4-7 are set whenever their corresponding channel is requesting service.

Request Register

,...:...,::...,=-r...:..,-=-.-=...,.:l.,..O:., ~Blt Number
Don·t Care

1

Clear mask bit
Set mask bit

OACK sense active low
DACK sense active high

r-"":""'-r--,r--,::.,...:l.,..O-,~ Bit Number

'--_ _-I 0

channel 0 mask bit
channell mask bit
channel 2 mask bit
channel 3 mask bit

All four bits of the Mask register may also be written
with a single command.

Mode Register

'----~

Bit Number

Don't Care

DREO sense active high
DREO sense active low

,

Software reql,lests will be serviced only If the channel Is
In Block mode. When Initiating a memory·to-memory
transfer, the software request for channel 0 should be
set.

Reset request bit
Set request bit

B-97

8237/8237 -2

Channel 0
Channell
Channel 2
Channel 3

has
has
has
has

reached
reached
reached
reached

Channel 0
Channell
Channel 2
Channel 3

request
request
request
request

Master Clear: This software instruction has the same
effect as the hardware Reset. The Command, Status,
Request, Temporary, and Internal First/Last Flip-Flop
registers are cleared and the Mask register is set. The
8237 will enter the Idle cycle.

TC
TC
TC
TC

Figure 5 lists the address codes for the software commands:
Signals

A3

Temporary Register - The Temporary register is used
to hold data during memory-to-memory transfers_ Following the completion of the transfers, the last word
moved can be read by the microprocessor in the Program Condition_ The Temporary register always contains the last byte transferred in the previous memoryto-memory operation, unless cleared by a Reset.

A2

A1

AO

lOR

lOW

Operation
Read Status Register
Write Command Register

Illegal
Write Request Register
Illegal
Write Single Mask Register Bit

Illegal

Software Commands - These are additional special
software commands which can be executed in the Program Condition. They do not depend on any specific bit
pattern on the data bus. The two software commands
are:
Clear First/Last Flip-Flop: This command is executed
prior to writing or reading new address or word count
information to the 8237. This initializes the flip-flop to
a known state so that subsequent accesses to register contents by the microprocessor will address upper and lower bytes in the correct sequence.

Write Mode Register
Illegal
Clear Byte Pointer Flip I Flop
Read Temporary Register

Maater Clear

Illegal
Illegal
Illegal
Write All Mask Register Bits

Figure 5. Software Command Codes
Signals

Channel

0

Reglst.r
Base and Current Address
Current Address
Base and Current Word Count
Current Wold Count

1

Base and Current Address
Current Address
Base and Current Word Count
Current Word Count

2

Base and Current Address
Current Address
Base and Current Word Count
Current Word Count

3

Base and Current Address
Current Address
Base and Current Word Count
Current Word Count

Operation
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read

Intemal Flip-Flop

Data Bus DBO-DB7

0
0

0

AQ-A7
AB-AI5

0
0

0
0

0

0
0

0
0

1
1

0

0
0

0
0

0
0

1
1

0

0
0

0
0

0
0

1
1

0
0

0

0
0

1
1

0
0

0
0

1
1

0
0

0

0
0

1
1

0
0

0
0

0
0

1
1

1
1

0

0
0

0
0

1
1

0
0

0
0

1
1

1
1

0

0
0

1
1

0
0

0
0

1
1

0
0

0
0

0

0
0

0
0

1
1

0
0

1
1

0
0

0
0

0

0
0

1
1

0
0

0
0

1
1

0
0

1
1

0

0
0

0
0

1
1

0
0

1
1

0
0

1
1

0

0
0

1
1

0
0

0
0

1
1

1
1

0
0

0

0
0

0
0

1
1

0
0

1
1

1
1

0
0

0

0
0

1
1

0
0

0
0

1
1

1
1

1
1

0

0
0

0
0

I
I

0
0

1
1

1
1

1
1

0

CS

lOR

lOW

A3

A2

Al

AO

0
0

1
1

0
0

0
0

0
0

0
0

0
0

0
0

1
1

0
0

0
0

0
0

1
1

0
0

0
0

0
0

0
0

1
1

0
0

1
1

0
0

Figure 6. Word Count and Address Register Command Codes

B-98

1
1
1
I
1
1
1
1
1
1
1
1
1
1
1
1

AQ-A7
A8-A15
WO-W7
W8-W15
W)O-W7
W8-W15
AO-A7
AB-AI5
AQ-A7
AB-AI5
WO-W7
W8-W15
WfJ-W7
W8-W15
AQ-A7
A8-A15
AO-A7
AB-A15
WQ-W7
W8-W15
W)Q-W7
W8-W15
AO-A7
AB-A15
AQ-A7
AB-AI5
WQ-W7
WB-WI5
WfJ-W7
W8-W15

8237/8237-2
APPLICATION INFORMATION

first transfer operation comes out in two bytes - the
least significant 8 bits on the eight address outputs and
the most significant 8 bits on the data bus. The contents
of the data bus are then latched into the 8282 8-bit latch
to complete the full 16 bits of the address bus. The 8282
is a high speed, 8-bit, three-state latch in a 20-pin
package. After the initial transfer takes place, the latch
is updated only after a carry or borrow is generated In
the least significant address byte. Four DMA channels
are provided when one 8237 is used.

Figure 7 shows a convenient method for configuring a
DMA system with the 8237 controller and an 8080AI
8085A microprocessor system. The multimode DMA
controller issues a HRQ to the processor whenever
there is at least one valid DMA request from a
peripheral device. When the processor replies with a
HLDA signal, the 8237 takes control of the address bus,
the data bus and the control bus. The address for the

>

ADDRESS BUS AO-A15

....

~

-y

~

A8-A15

......

I---

OE

8282

...

I
AEN

AO-A15

STB

r

7-

AO-A3

A4-A7

CS

8·BIT LATCH

ADSTB

~

BUSEN
HLDA
HOLD

8237

HLDA
HRQ

~

Ii;

'"w

" '"

CPU
CLOCK
RESET

,

~

!

I

I~

Ii e l~

MEMR

15
w

A

•

~

y

DBO~

.~

DB7

;>..

'" "
Q

Q

tt
l~~""

MEMW

BUS

iOR
lOW

DBO-DB7

"'"

r--

"""

"..

".

SYSTEM DATA BUS

Figure 7

B-99

8237/8237-2
ABSOLUTE MAXIMUM RATINGS·
'COMMENT: Stresses above those listed under "Absolute Maximum

Ambient Temperature under Bias ......... O·C to 70·C
Storage Temperature ............. - 65·C to + 150·C
Voltage on any Pin with
Respect to Ground .................... - 0.5 to 7V
Power Dissipation ......................... 1.5 Watt

Ratings" may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-

ditions for extended periods may affect device reliability.

D.C. CHARACTERISTICS
TA=O·Cto 70·C, Vcc=5.0V ±5%, GND=OV
Symbol

Parameter

Min.

Typ'(1)

Max.

V OH

Output HIGH Voltage

VOL

Output LOW Voltage

VIH

Input HIGH Voltage

V IL

Input LOW Voltage

'll
ILO

Unit
V

2.4

V

IOH = -100 IJA (HRQ Only)

0.4

V

IOL=3.2 mA

2.0

Vcc+ 0.5

V

-0.5

0.8

V

Input Load Current

±10

IJA

Output Leakage Current

±10

IJA

Vcc~Vo~Vss + 0.40

65

130

mA

TA= +25·C

75

150

mA

TA=O·C

4

8

pF

8

15

pF

10

18

pF

Icc

Vcc Supply Current

Co

Output Capacitance

CI

Input Capacitance

CIO

I/O Capacitance

3.3

Test Conditions
IOH= - 2OO IJA

VSS~VI~VCC

Ic = 1.0 MHz, Inputs = OV

Noles:
1. Typical values are for T A:;;: 25°C, nominal supply voltage and nominal processing parameters.
2. Input timing parameters assume transition times of 20 ns or less. Waveform measurement pOints for both input and output signals are 2.0V for HIGH
and O.BV for LOW, unless otherwise noted.
3. Output loading is 1 TIL gate plus 50 pF capacitance, unless otherwise noted.
4. The net lOW or M'E'MiiV Pulse width for normal write will be TCY-l00 ns and for extended write will be 2TCY-100 ns. The net lOR or MEMR pulse

width for normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns.

5. TOQ is specified for two different output HIGH levels. TOQ1 is measured at 2.0V. TOQ2 is measured at 3.3V. The value forTOQ2 assumes an external
3.3 kQ pull·up resistor connected from HRQ to V CC.
6. OREQ should be held active until OACK is returned.
7. OREQ and OACK signals may be active high or active low. Timing diagrams assume the active high mode.
B. Output loading on the data bus is 1 TIL gate plus 100 pF capacitance.
9. Successive read and/or write operations by the external processor to program or examine the controller must be timed to allow at least 600 ns forthe
8237 and at least 400 ns for the 8237·2 as recovery time between active read or write pulses.
10. Parameters are listed in alphabetical order.

11. Pin 5 is an input that should always be at a logic high level. An internal pull·up resistor will establish a logic high when the pin is left floating. Aller·
natively, pin 5 may be tied to VCC'

A.C. TEST WAVEFORM

X

2.4V---------_........

,..-----------HIGH "1"

0 . 4 5 V - - - - - - - -_ _....J.

"'O:;.;.8:..:V_ _ _ _ _ _ _ _ _ _ LOW "0"

2.0V

B-lOO

8237/8237-2
A.C. CHARACTERISTICS: DMA (MASTER) MODE
TA=O·C to 70·C, Vcc=5.0V ±50/0, GND=OV
Symbol

8237

Parameter

Min.

8237·2
Max.

Min.

Max.

Unit

TAEL

AEN HIGH from CLK LOW (51) Delay Time

300

200

ns

TAET

AEN LOW from CLK HIGH (51) Delay Time

200

130

ns

TAFAB

ADR Active to Float Delay from CLK HIGH

150

90

ns

TAFC

READ or WRITE Float from CLK HIGH

150

120

ns

TAFDB

DB Active to Float Delay from CLK HIGH

250

170

ns

TAHR

ADR from READ HIGH Hold Time

TCY-100

TCY-100

ns

TAHS

DB from ADSTB LOW Hold Time

50

30

ns

TAHW

ADR from WRITE HIGH Hold Time

TCY-50

TCY-50

ns

DACK Valid from CLK LOW Delay Time

250

170

ns

TAK

EOP HIGH

250

170

ns

EOP LOW to CLK HIGH Delay Time

250

100

ns

TASM

ADR Stable from CLK HIGH

250

170

ns

TASS

DB to ADSTB LOW Setup Time

100

100

ns

TCH

Clock High Time (Transitions <0;10 ns)

120

70

ns

TCL

Clock LOW Time (Transitions <0;10 ns)

150

50

ns

TCY

CLK Cycle Time

320

200

ns

TDCL

CLK HIGH to READ orWRITE LOW Delay (Note 4)

270

190

ns

TDCTR

READ HIGH from CLK HIGH (54) Delay Time
(Note 4)

270

190

ns

TDCTW

WRITE HIGH from CLK HIGH (54) Delay Time
(Note 4)

200

130

ns

160

120

ns

250

120

ns

TDQ1
TDQ2

from CLK HIGH Delay Time

HRQ Valid from CLK HIGH Delay Time (Note 5)

TEPS

EOP LOW from CLK LOW Setup Time

TEPW

EOP Pulse Width

TFAAB

ADR Float to Active Delay from CLK HIGH

250

170

ns

TFAC

READ or WRITE Active from CLK HIGH

200

150

ns

TFADB

DB Float to Active Delay from CLK HIGH

300

200

ns

THS

HCDA Valid to CLK HIGH Setup Time

TIDH

Input Data from MEMR HIGH Hold Time

TIDS

Input Data to MEMR HIGH Setup Time

TODH

Output Data from MEMW HIGH Hold Time

TODV

Output Data Valid to MEMW HIGH

TQS

DREQ to CLK LOW (51, 54) Setup Time

TRH

CLK to READY LOW Hold Time

TRS

READY to CLK LOW Setup Time

100

75

TSTL

ADSTB HIGH from CLK HIGH Delay Time

200

130

ns

TSTT

ADSTB LOW from CLK HIGH Delay Time

140

90

ns

B-101

60

40

300

220

ns
ns

100

75

ns

0

0

ns

250

170

ns

20

10

ns

200

130

ns

0

0

ns

20

20

ns
ns

8237/8237-2
A.C. CHARACTERISTICS: PERIPHERAL (SLAVE) MODE
TA =0·Ct070·C, Vcc=5.0V ±5%, GND=OV
Symbol

8237

Parameter

8237·2
Max.

Min.

Min.

Unit

Max.

TAR

ADR Valid or CS LOW to READ LOW

50

50

ns

TAW

ADR Valid to WRITE HIGH Setup Time

200

160

ns

TCW

CS LOW to WRITE HIGH Setup Time

200

160

ns

TOW

Data Valid to WRITE HIGH Setup Time

200

160

ns

TRA

ADR or CS Hold from READ HIGH

0

0

TRDE

Data Access from READ LOW (Note 8)

TRDF

DB Float Delay from READ HIGH

TRSTO

Power Supply HIGH to RESET LOW Setup Time

ns

200
20

100

140
70

0

500

500

ns
ns
j.!s

TRSTS

RESET to First IOWR

2TCY

2TCY

ns

TRSTW

RESET Pulse Width

300

300

ns

TRW

READ Width

300

200

ns

TWA

ADR from WRITE HIGH Hold Time

20

0

ns

TWC

CS HIGH from WRITE HIGH Hold Time

20

0

ns

TWD

Data from WRITE HIGH Hold Time

30

10

ns

TWWS

Write Width

200

160

ns

TIMING DIAGRAM #1 -

SLAVE MODE WRITE TIMING

~
I,

Tew

TWWS

TAW
AO-A3

~

---1

INPUT VALID

TDW
DBO-DB7

TIMING DIAGRAM #2 -

=::)

-i

-

I-Twe

~

-

I
_TWA

-TWO

K

INPUT VALID

SLAVE MODE READ TIMING

./

AO-A3

~

~

ADDRESS MUST BE VALID

~_"·"1t---1==-_-TRDE--=TRW~_-t-t--':"3-

IOR_-

DBO-DB7

{

B-102

DATA OUT VALID

8237/8237-2
TIMING DIAGRAM #3 -

DMA TRANSFER TIMING

eLK

DREQ

1-

HRC

______~~r--+~~~-+---+---r-r-r--~--~~~----------

HLDA

.EN

ADSTB

-TAHW

AO-A7

DACK

INTW

EXT'ElfP

B-103

8237/8237·2
TIMING DIAGRAM #4 -

MEMORY TO MEMORY TRANSFER TIMING

ADSTB

ADDRESS VALID

AO-A7

DBO-DB7

OUT

TOCV I---+--j.----I

TIMING DIAGRAM #5 -

READY TIMING

B-104

8237/8237·2
TIMING DIAGRAM #6 -

COMPRESSED TRANSFER TIMING

CLK

AO-A7

TDCL--i--I--I

_

~TRH

-

_

_

TRH

J~\'----

READY _~TRSJ ',----,TRs

TIMING DIAGRAM #7 -

RESET TIMING

Vee ______-J;frl~~~~~~~~~~~~~~~~~-T-R-S-TD--------------------_-_-_-_-_-_-_-_--=---------tI~I--------------________________~
RESET _

tI'========_T_RS_T_W~~_-_-_-_-_-_

lOR OR lOW

B-105

8259A/8259A-2/8259A-8
PROGRAMMABLE INTERRUPT CONTROLLER

• 808618088 Compatible
• MCS-8018S™ Compatible
• Eight-level Priority Controller
• Expandable to 64 levels

• Programmable Interrupt Modes
• Individual Request Mask Capability
• Single + SV Supply (No Clocks)
• 28·Pin Dual·ln·line Package

The Intel'" 8259A Programmable Interrupt Controller handles up to eight vectored priority interrupts for the CPU. It is
cascadable for up to 64 vectored priority interrupts without additional circuitry. It is packaged in a 28·pin DIP, uses
NMOS technology and requires a single + 5V supply. Circuitry is static, requiring no clock input.
The 8259A is designed to minimize the software and realtime overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.
The 8259A is fully upward compatible with the Intel'" 8259. Software originally written for the 8259 will operate the
8259A in all 8259 equivalent modes (MCS·80185, Non-Buffered, Edge Triggered).

BLOCK DIAGRAM

PIN CONFIGURATION

cs

vee

WR

"0

AD

INTA

0,

IR7

D.

IR6

DATA

0.

IR5

BUFFER

0,

IRO

0,

IR3

0,

IR2

0,

IRI

D.

IRO

CASO

INT

CAS1

SPIEN

GND

CAS 2

PIN NAMES
°1- 0 0

cs---------'

DATA BUS (SI-DiRECTIONAl!

RO

READ INPUT

WR

WRITE INPUT

A.

COMMAND SELECT ADDRESS

CS
CAS2CASO

CONTROllOGtC

BUS

CHIP SELECT

CAS 1
CAS 2

CASCADE LINES

~mil

SLAVE PROGRAM IENABLE BUFFER

INT
INTA

INTERRUPT ACKNOWLEDGE INPUT

IRO-IR7

INTERRUPT REQUeST INPUTS

SPIEN---··-

INTERRUPT OUTPUT

B-106

~

INTERNAL BUS

82S9A/82S9A-2/82S9A-8
INTERRUPTS IN MICROCOMPUTER
SYSTEMS
Microcomputer system design requires that 110 devices
such as keyboards, displays, sensors and other components receive servicing in an efficient manner so that
large amounts of the total system tasks can be assumed
by the microcomputer with little or no effect on throughput.

match his system requirements. The priority modes can
be changed or reconfigured dynamically at any time during the main program. This means that the complete
interrupt structure can be defined as required, based on
the total system environment.

The most common method of servicing such devices is
the Polled approach. This is where the processor must
test each device in sequence and in effect "ask" each
one if it needs servicing. It is easy to see that a large portion of the main program is looping through this continuous polling cycle and that such a method would
have a serious, detrimental effect on system throughput, thus limiting the tasks that could be assumed by
the microcomputer and reducing the cost effectiveness
of using such devices.

CPU·DRIVEN
MULTIPLEXOR

CPU

--, ,

A more desirable method would be one that would allow
the microprocessor to be executing its main program
and only stop to service peripheral devices when it is
told to do so by the device itself. In effect, the method
would provide an external asynchronous input that
would inform the processor that it should complete
whatever instruction that is currently being executed
and fetch a new routine that will service the requesting
device. Once this servicing is complete, however, the
processor would resume exactly where it left off.
This method is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests
is of the highest importance (priority), ascertains
whether the incoming request has a higher priority value
than the level currently being serviced, and issues an
interrupt to the CPU based on this determination.

Polled Method

CPU

.NT

Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred
to as a "service routine". The PIC, after issuing an Interrupt to the CPU, must somehow input information into
the CPU that can "point" the Program Counter to the
service routine associated with the requesting device.
This "pOinter" is an address in a vectoring table and will
often be referred to, in this document, as vectoring data.

8259A BASIC FUNCTIONAL DESCRIPTION
GENERAL
The 8259A is a device specifically designed for use in
real time, interrupt driven microcomputer systems. It
manages eight levels or requests and has built-in features for expandability to other 8259A's (up to 64 levels)_
It is programmed by the system's software as an 1/0
peripheral. A selection of priority modes is available to
the programmer so that the manner In which the requests are processed by the 8259A can be configured to

B-107

Interrupt Method

8259A/8259A-2/8259A-8
INTERRUPT REQUEST REGISTER (IRR) AND
IN-SERVICE REGISTER (lSR)

The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register
(IRR) and the In-Service Register (ISR). The IRR is used
to store all the interrupt levels which are requesting service; and the ISR is used to store all the interrupt levels
which are being serviced.
PRIORITY RESOLVER

This logic block determines the priorities of the bits set
in the IRR. The highest priority is selected and strobed
into the corresponding bit of the ISR during INTA pulse.
INTERRUPT MASK REGISTER (lMR)

The IMR stores the bits which mask the interrupt lines
to be masked. The IMR operates on the IRR. Masking of
a higher priority input will not affect the interrupt
request lines of lower priority.
INT (INTERRUPT)

This output goes directly to the cru interrupt input. The
VOH level.on this line is designed to be fully compatible
with the 8080A, 8085A, 8086 and 8088.

8259A Block Diagram

INTA (INTERRUPT ACKNOWLEDGE)

INTA pulses w;1I cause the 8259A to release vectoring
information onto the data bus. The format of this data
depends on the system mode ("PM) of the 8259A.
DATA BUS BUFFER

This 3-state, bidirectional 8-bit buffer is used to inter·
face the 8259A to the system Data Bus. Control words
and status information are transferred through the Data
Bus Buffer.
READIWRITE CONTROL LOGIC

The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation Command
Word (OCW) registers which store the various control
formats for device operation. This function block also
allows the status of the 8259A to be transferred onto the
Data Bus.
CS (CHIP SELECT)

A LOW on this input enables the 8259A. No reading or
writing of the chip will occur unless the device is
selected.
WR (WRITE)

8259A Block Diagram

A LOW on this input enables the CPU to write control
words (lCWs and OCWs) to the 8259A.
Ao
RD (READ)

A LOW on this input enables the 8259A to send the
status of the Interrupt Request Register (IRR), In Service
Register (ISR), the Interrupt Mask Register (IMR), or the
Interrupt level onto the Data Bus.

This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers, as well as reading the various status registers
of the Chip. This line can be tied directly to one of the address lines.

B-108

82S9A/82S9A-2/82S9A-8
THE CASCADE BUFFER/COMPARATOR

This function block stores and compares the IDs of all
8259A's used in the system. The associated three I/O
pins (CASO-2) are outputs when the 8259A is used as a
master and are inputs when the 8259A is used as a
slave. As a master, the 8259A sends the ID of the inter·
rupting slave device onto the CASO-2 lines. The slave
thus selected will send its preprogrammed subroutine
address onto the Data Bus during the next one or two
consecutive INTA pulses. (See section "Cascading the
8259A".)

If no interrupt request is present at step 4 of either
sequence (i.e., the request was too short in duration) the
8259A will issue an interrupt level 7. Both the vectoring
bytes and the CAS lines will look like an interrupt level 7
was requested.

INTERRUPT SEQUENCE

The powerful features of the 8259A in a microcomputer
system are its programmability and the interrupt routine
addressing capability. The latter allows direct or indirect
jumping to the specific interrupt routine requested
without any polling of the interrupting devices. The nor·
mal sequence of events during an interrupt depends on
the type of CPU being used.
The events occur as follows in an MCS·80/85 system:
1. One or more of the INTERRUPT REQUEST lines
(IR7-0) are raised high, setting the corresponding IRR
bit(s).
2. The 8259A evaluates these requests, and sends an
INT to the CPU, if appropriate.
3. The CPU acknowledges the INT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259A will also release a CALL in·
struction code (11001101) onto the 8·bit Data Bus
through its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259A from the CPU group.
6. These two INTA pulses allow the 8259A to release its
preprogrammed subroutine address onto the Data
Bus. The lower 8·bit address is released at the first
INTA pulse and and the higher 8·bit address is reo
leased at the second INTA pulse.
7. This completes the 3·byte CALL instruction released
by the 8259A. In the AEOI mode the ISR bit is reset at
the end of the third INTA pulse. Otherwise, the ISR bit
remains set until an appropriate EOI command is
issued at the end of the interrupt sequence.

8259A Block Diagram

The events occuring in an 8086/8088 system are
the same until step 4.
4. Upon receiving an INTA from the CPU group, the high·
est priority ISR bit is set and the corresponding IRR
bit is reset. The 8259A does not drive the Data Bus
during this cycle.
5. The 8086/8088 CPU will initiate a second
INTA pulse. During this pulse, the 8259A releases an
8-bit pointer onto the Data Bus where it is
read by the CPU.

I
INTERRUPT
REQUESTS

6. This completes the interrupt cycle. In the AEOI mode
the ISR bit is reset at the end of the second INTA
pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the
interrupt subroutine.

B-109

8259A Interface to Standard System Bus

8259A/8259A-2/8259A-8
INTERRUPT SEQUENCE OUTPUTS
MeS-SO/S5 MODE
This sequence is timed by three INTA pulses. During the
first iNfA pulse the CALL opcode is enabled onto the
data bus.

During the third INTA pulse the higher address of the
appropriate service routine, which was programmed as
byte 2 of the initialization sequence (A8 - A 15), is
enabled onto the bus.

Content of Third Interrupt
Vector Byte

Content of First Interrupt
Vector Byte
D7

D5

De

D4

D3

D2

D1

D7
A15

DO

D8
A14

DS
A13

I

D4
A12

I

D3
All

D2
Ala

Dl

DO

A9

CALLCODE LI_1________a
_________________a____1-J1

SOS6/S0SS Mode
During the second iNTA pulse the lower address of the
appropriate service routine is enabled onto the data bus.
When Interval 4 bits A5-A7 are programmed, while A aA. are automatically inserted by the 8259A. When Interval 8 only A6 and A7 are programmed, while Aa-A5 are
automatically inserted.

=

=

Content 01 Second Interrupt
Vector Byte
IR
7
6
5

•

3

2

1
a

InlerYal-4

D7
A7
A7
A7
A7
A7
A7
A7
A7

De

DS

A6
A6
A6
A6
A6
A6

AS

AS

A6

A5
A5
A5
A5
A5
A5
A5

D4
1
1
1
1
a
a
a
a

D5
1
1
1
1
a
a
a
a

Inlervll = 8
D4
D3
1
1
1
a
1
a
a
a
1
1
1
a
1
a
a
a

IR
7
6
5

D7
A7
A7
A7

4

A7

3

A7

2

A7

1
a

A7
A7

De
AS

A6
A6
A6
A6
A6
A6
A6

D3
1
1
a
a
1
1
a
a

D2
1
a
1
a
1
a
1
a

D1
a
a
a
a
a
a
a
a

DO

D2
a
a
a
a
a
a
a
a

Dl
a
a
a
a

DO

0

a
a
a

a
a
a
a
a
a
a
a

8086/8088 mode is similar to MCS80/85 mode
except that only two Interrupt Acknowledge cycles are
issued by the processor and no CALL opcode is sent
to the processor. The first interrupt acknowledge cycle
is similar to that of MCS-80 185 systems in that the
8259A uses it to internally freeze the state of the interrupts for priority resolution and as a master it
issues the interrupt code on the cascade lines at the
end of the INTA pulse. On this first cycle it does not
issue any data to the processor and leaves its data bus
buffers disabled. On the second interrupt acknowledge
cycle in 8086/8088 mode the master (or slave if so
programmed) wi~1 send a byte of data to the processor
with the acknowledged interrupt code composed
as follows (note the state of the ADI mode control
is ignored and A5-All are unused in 8086/8088 mode):

T7

T6

D5
T5
T5

IR5
IR4

T7
T7

T6
T6

T5
T5

IR3

T7

T6

1

1

T3
T3

0

1

0

T7

T6
T6

T4
T4
T4

0

T7

T5
T5
T5

T3

IR2
IRl

0

0

1

IRO

T7

T6

T5

T4

T3

0

0

0

IR7
IR6

0

a
0

a
a
a
a
a

B-1 10

D7
T7

D6
T6

D4
T4

D3
T3

D2
1

T4
T4

T3
T3
T3

T4

D1
1

DO
1

1

1

0

1
1

0

1

0

0

82S9A/82S9A-2/82S9A-8
PROGRAMMING THE 8259A

INITIALIZATION

The 8259A accepts two types of command words generated by the CPU:

GENERAL
Whenever a command is issued with AO=O and D4= I,
this is interpreted as Initialization Command Word 1
(lCW1). ICWI starts the initialization sequence during
which the following automatically occur.

1. Initialization Command Words (JCWs): Before normal
operation can begin, each 8259A in the system must
be brought to a startin~int - by a sequence of 2
to 4 bytes timed by WR pulses. This sequence
is described in Figure 1.

a. The edge sense circuit is reset, which means that
following initialization, an interrupt request (IR) input
must make a low-to-high transition to generate an interrupt.
b. The Interrupt Mask Register is cleared.
c. R7 input is assigned priority 7.
d. The slave mode address is set to 7.
e. Special Mask Mode is cleared and Status Read is
set to IRR.
f. If IC4=O, then all functions selected in ICW4 are set
to zero. (Non-Buffered mode', no Auto-EOI, MCS80/85 system).

2. Operation Command Words (OCWs): These are the
command words that are sent to the 8259A for various forms of operation, such as:
•
•
•
•

Interrupt Masking
End of Interrupt
Priority Rotation
Interrupt Status

The OCWs can be written into the 8259A anytime after
initialization.

Ao

D~

03

0
1

'Note: Master J Slave in ICW4 is only used in the buffered mode.

RD

WR

CS

0
0

1
1

0
0

INPUT OPERATION (READ)
IRR, ISR or Interrupting Level_DATA BUS (Note 1)
IMR ___ DATA BUS
OUTPUT OPERATION (WRITE)

0
0
0
1

0
0

0

1
X

X
X

1

1
1
1
1

0
0
0
0

0
0
0
0

DATA
DATA
DATA
DATA

BUS -OCW2
BUS -OCW3
BUS--ICWI
BUS--OCW1, ICW2, ICW3, ICW4 (Note 2)
DISABLE FUNCTION

X
X

X
X

X
X

1
X

1
X

0

DATA BUS - 3-STATE (NO OPERATION!
DATA BUS - 3-STATE (NO OPERATION!

1

Not'.: 1, Selection oIIAA, ISA or Interrupting Le\lel is based on the content 01 OCW3 written before the READ operation.
2. On-chip sequencer logic queues these commands into proper sequence.

!l259A Basic Operation

B-11l

8259A/8259A-218259A-8
INITIALIZATION COMMAND WORDS 1 AND 2
(ICW1,ICW2)

INITIALIZATION COMMAND WORD 3 (ICW3)
This word is read only when there is more than one
8259A in the system and cascading is used, in which
case SNGL = O. It will load the 8-bit slave register. The
functions of this register are:

A 5-A. 5: Page starting address of service routines. In an
MCS 80/85 system, the 8 request levels will generate
CALLs to 8 locations equally spaced in memory. These
can be programmed to be spaced at intervals of 4 or 8
memory locations, thus the 8 routines will occupy a
page of 32 or 64 bytes, respectively.

a. In the master mode (either when SP = 1, or in buffered mode when MIS = 1 in ICW4) a "1" is set for
each slave in the system. The master then will release byte 1 of the call sequence (for MCS-80/85
system) and will enable the corresponding slave to
release bytes 2 and 3 (for 8086/8088 only
byte 2) through the cascade lines.
b. In the slave mode (either when SP = 0, or if BUF
1
and M / S = 0 in ICW4) bits 2-0 identify the slave. The
slave compares its cascade input with these bits
and if they are equal, bytes 2 and 3 of the call
sequence (or just byte 2 for 8086/8088)
are released by it on the Data Bus.
INITIALIZATION COMMAND WORD 4 (ICW4)

The address format is 2 bytes long (Ao-A.s). When the
routine interval is 4, Ao-A4 are automatically inserted by
the 8259A, while A5-A'5 are programmed externally.
When the routine interval is 8, Ao-A5 are automatically
inserted by the 8259A, while A6-A.5 are programmed
externally.

=

The 8-byte interval will maintain compatibility with current software, while the 4-byte interval is best for a compact jump table.
In an MCS-86 system T7-T3 are inserted in the five
most significant bits of the vectoring byte and the
8259A sets the three least significant bits according to
the interrupt level. A lO -A 5 are ignored and ADI (Address Interval) has no effect.

=

SFNM: If SFNM 1 the special fully nested mode is
programmed.
BUF: If BUF = 1 the buffered mode is programmed. In
buffered mode SP/EN becomes an enable output
and the masterlslave determination is by MIS.
MIS: If buffered mode is selected: MIS 1 means the
8259A is programmed to be a master, MIS 0
means the 8259A is programmed to be a slave. If
BUF 0, MIS has no function.
AEOI: If AEOI = 1 the automatic end of interrupt mode
is programmed.
IlPM: Microprocessor mode: "PM 0 sets the 8259A
for MCS-80/85 system operation, "PM 1 sets
the 8259A for MCS-86 system operation.

If LTIM = 1, then the 8259A will operate in the
level interrupt mode. Edge detect logic on the
interrupt inputs will be disabled.
ADI:
CALL address interval. ADI = 1 then Interval = 4;
ADI =0 then interval =8.
SNGL: Single. Means that this is the only 8259A in the
system. If SNGL = 1 no ICW3 will be issued.
IC4:
If this bit is set - ICW4 has to be read. If ICW4
is not needed, set IC4 =O.

=

LTIM:

AO

D7

De

D5

0

A7

AI

A5

L•

A15/T7

A14/T6

A13/TS

I •

57

I

=

=

D4

D3

D2

D.

LTIM

ADI

SNQl

le4 fleW1

All/T3

A.O

A.

AI I'CW2

DO

I
A12/T4

~--------------------.;:'.~...,..
se

55

54

53

521102

51/101

SOliDO

(leW3

I

r--------------------(-.::~~."
I

1

=

5FNM

aUF

t

I

READY TO ACCEPT INTERRUPTS

Figure 1. Initialization Sequence

B-1 12

MIS

AEOI

~PM (lew..

=

82S9A/82S9A-2/82S9A-8

ICWI

1 lew" NEEDED
~ NO lew.. NEEDED

o

1 = SINGLE
CASCADE MODE

o '"

CALL A[,ORESS INTERVAL
1 ~ INTERVAL OF"

o~

INTERVAL OF 8

1 "" LEVEL TRIGGERED MODE
EDGE TRIGGERED MODE

o ""

A7-A5 01 INTERRUPT
VECTOR ADDRESS
(MeS-BO 185 MODE ONLY)
ICW'

A 15 -A a OF INTERRUPT
VECTOR ADDRESS

(MCsaD/55 MODE)

T7- T3 OF INTERRUPT
VECTOR ADDRESS
(808618088 MODE)

leW3 jMASTER DEVICE)

"--L-----'----'-----'----'----L--'-------I

1 = IR INPUT HAS A SLAVE
0" IR INPUT OOES NOT HAVE
A SLAVE

ICW31SlAVE DEVICE I

SLAVE 10111

1 = 80861B088 MODE
a = Mes-So! 85 MODE

1

o~

EliE
1
1

x
0
1

AUTO EOI
NORMAL EOI

.- NON BUFFERED MODE
- BUFFERED MODE/SLAVE
- BUFFERED MODE/MASTER
1 = SPECIAL FULLY NESTED

'----------1

0 =

~g~~PECIAL FULLY
NESTED MODE

NOTE 1· SLAVE 10 IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.

Initialization Command Word Format

B-l13

82S9A/82S9A-2/82S9A-8
OPERATION COMMAND WORDS (OCWs)

OPERATION CONTROL WORD 1 (OCW1)

After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip Is ready to accept
Interrupt requests at its input lines. However, during the
8259A operation. a selection of algorithms can command the 8259A to operate in various modes through
the Operation Command Words (OCWs).

OCW1 sets and clears the mask bits in the interrupt
Mask Register (IMR). M 7 - Mo represent the eight mask
bits. M 1 indicates the channel is masked
(inhibited), M 0 indicates the channel is enabled.

=

=

OPERATION. CONTROL WORD 2 (OCW2)
R, SL, EOI ~ These three bits control the Rotate and
End if Interrupt modes and combinations of the two. A
chart of these combinations can be found on the Operation Command Word Format.

OPERATION CONTROL WORDS (OCWs)

OCWI

AO

GJ

07

I M7

De

05

04

03

02

01

DO

M6

M5

M4

M3

M2

MI

MO

I

L2, L" Lo - These bits determine the interrupt level
acted upon when the SEOI bit is active.

OPERATION CONTROL WORD 3 (OCW3)
OCW2

0

IA

SL

EOI

0

0

L2

L1

LO

OCW3

0

I0

ESMM SMM

0

P

AA

AIS

I

I

ESMM - Enable Special Mask Mode. When this bit is
set to 1 it enables the SMM bit to set or reset the Special
Mask Mode. When ESMM = 0 the SMM bit becomes a
"don't care".
SMM - Special Mask Mode. If ESMM = 1 and SMM = 1
the 8259A will enter Special Mask Mode. If ESMM = 1
and SMM = 0 the 8259A will revert to normal mask mode.
When ESMM = 0, SMM has no effect.

B-114

8259A/8259A-2/8259A-8

1

" I I I i I " I '. I '0 I
sc

0

EO'

0

0

l
)

IR lEVEL TO BE
0

,
,

ACTED UPON
2

3

0

0

,
, ,

0

0

0

0

0

0

4

5

0

,

0

0

,
,
, ,
6

0

, , , ,

r

rtt-;;- 0-;-,
f-i- fa,
r,- roo
to r,o

0-+

r,- r-;-,
r,- c'o
~~o

Non-specifiC EOI Command
• Specific EOI Command

Rotate On Non-Specific EOI Command
Rotate In Automatic EOI Mode (SET)
Rotate In Automatic EOI Mode (CLEAR)
'Rotate On Specific EOI Command
• Set Priority Command
No operation
'lO-L2 are used

}

END OF INTERRUPT

}

AUTOMATIC ROTATION

}

SPECIFIC ROTATION

QCW3

I

0-1 -

1"""1 I I ' I ' I "" I""

IN'
CARE

SM"

0

I

l_

READ REGISTER COMMAND
0
0

I ,
I

,
READ

NO ACTION

,
,

0

0

READ

IR REG

IS REG

ON NE'i.T

ON NEXT

ROf>ULSE

RDPULSE

1 '" POLL COMMAND

a =:

NO POLL COMMAND

SPECIAL MASK MODE

0

0

I ,

I

0

NO ACTION

Operation Command Word Format

B-115

0

,

,

,

RESET

SET

SPECIAL

SPECIAL

MASK

MAS'

82S9A/82S9A-2/82S9A-8
INTERRUPT MASKS

FULLY NESTED MODE

Each Interrupt Request input can be masked indivIdually by the Interrupt Mask Register (IMR) programmed
through OCWI. Each bit in the IMR masks one interrupt
channel if it is set (1). Bit 0 masks IRO, Bit 1 masks IRI
and so forth. Masking an IR channel does not affect the
other channels operation.

This mode is entered after initialization unless another
mode is programmed. The interrupt requests are
ordered in priority form 0 through 7 (0 highest). When an
interrupt is acknowledged the highest priority request is
determined and its vector placed on the bus. Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an
End of Interrupt (EOI) command immediately before
returning from the service routine, or if AEOI (Automatic
End of Interrupt) bit is set, until the trailing edge of the
last INTA. While the IS bit is set, all further interrupts of
the same or lower priority are inhibited, while higher
levels will generate an interrupt (which will be
acknowledged only if the microprocessor internal Interrupt enable flip-flop has been re-enabled through software).

SPECIAL MASK MODE
Some applications may require an interrupt service
routine to dynamically alter the system priority structure during its execution under software control. For
example, the routine may wish to inhibit lower priority
requests for a portion of its execution but enable some
of them for another portion.
The difficulty here is that if an Interrupt Request is
acknowledged and an End of Interrupt command did not
reset its IS bit (i.e., while executing a service routine),
the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enable
them
That is where the Special Mask Mode comes in. In the
special Mask Mode, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and enables interrupts from al/ other levels (lower as well as higher) that
are not masked.
Thus, any interrupts may be selectively enabled by
loading the mask register.
The special Mask Mode is set by OCW3 where:
SMM = 1, SMM = 1, and cleared where SMM = 1,
SMM = O.
BUFFERED MODE
When the 8259A Is used In a large system where bus
driving buffers are required on the data bus and the cascading mode is used, there exists the problem of enabling buffers.
The buffered mode will structure the 8259A to send an
enable signal on SPIEN to enable the buffers. In this
mode, whenever the 8259A's data bus outputs are enabled, the SPIEN output becomes active.
This modification forces the use of software programming to determine whether the 8259A is a master or a
slave. Bit 3 in ICW4 programs the buffered mode, and bit
2 in ICW4 determine.s whether it is a master or a slave.

After the initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed,
as will be explained, by priority rotation.

THE SPECIAL FULLY NESTED MODE
This mode will be used in the case of a big system
where cascading is used, and the priority has to be conserved within each slave. In this case the special fully
nested mode will be programmed to the master (using)
ICW4). This mode is similar to the normal fully nested
mode with the foliowing exceptions:
a. When an interrupt request from a certain slave is in
service this slave is not locked out from the master's
priority logic and further interrupt requests from
higher priority IR's within the slave will bf! recognized
by the master and will initiate interrupts to the processor. (In the normal nested mode a slave is masked
out when its request is in service and no higher
requests from the same slave can be serviced.)
b. When exiting the Interrupt Service routine the software has to check whether the interrupt serviced was
the only one from that slave. This is done by sending
a non-specific End of Interrupt (EOI) command to the
slave and then reading its In-Service register and
checking for zero. If it is empty, a non-specific EOI
can be sent to the master too. If not, no EOI should be
sent.

B-116

82S9A/82S9A-2/82S9A-8
POLL
In this
Enable
Service
using a

mode the microprocessor internal Interrupt
flip·flop is reset, disabling its interrupt input.
to devices is achieved by programmer initiative
Poll command.

The Poll command is issued by setting P = "1" in OCW3.
The 8259A treats the next RD pulse to the 8259A (i.e.,
RD = 0, CS = 0) as an interrupt acknowledge, sets the
appropriate IS bit if there is a request, and reads the
priority level. Interrupt is frozen from WR to RD.
The word enabled onto the data bus during RC5 is:
07
~

De

-

05

04

03

02

01

DO

----------w-2---w-,---W-.ol

WO-W2: Binary code of the highest priority level
requesting service.
Equal to a "1" if there is an interrupt.

second in MCS·86). Note that from a system standpoint,
this mode should be used only when a nested multilevel
interrupt structure is not required within a single 8259A.
To achieve automatic rotation within AEOI, there
is a special rotate flip·flop. It is set by OCW2 with
R = 1, SL = 0. EOI = 0, and cleared with R = 0,
SEOI = 0, EOI = 0.
AUTOMATIC ROTATION
(Equal Priority Devices)
In some applications there are a number of interrupting
devices of equal priority. In this mode a device, after
being serviced, receives the lowest priority, so a device
requesting an interrupt will have to wait, in the worst
case until each of 7 other devices are serviced at Illost
once. For example, if the priority and "in service" status
is:
Belore Rotete (IR4 the highest priority requiring service)

This mode is useful if there is a routine command commmon to several levels so that the INTA sequence is not
needed (saves ROM space). Another application is to
use the poll command to expand the number of priority
levels to more than 64.

157

"'s"

END OF INTERRUPT (EOI)

There are two forms of EOI command: Specific and Non·
Specific. When the 8259A iR operated in modes which
preserve the fully nested structure, it can determine
which IS bit to reset on EOI. When a "lon·Specific EOI
command is issued the 8259A will automatically reset
the highest IS bit of those that are set, since in the
nested mode the highest IS level was necessarily the
last level acknowledged and serviced.
However, when a mode is used which may disturb the
fully nested structure, the 8259A may no longer be able
to determine the last level acknowledged. In this case a
Specific End of Interrupt (SEOI) must be issued which
includes as part of the command the IS level to be reset.
EOI is issued whenever EOI = 1, in OCW2, where LO-L2
is the binary level of the IS bit to be reset. Note that
although the Rotate command can be issued together
with an EOI where EOI = 1, it is not necessarily tied to it.
It should be noted that an IS bit that is masked by an
IMR bit will not be cleared by a non·specific EOI if the
8259A is in the Special Mask Mode.
AUTOMATIC END OF INTERRUPT (AEOI) MODE
If AEOI 1 in ICW4, then the 8259A will operate in AEOI
mode continuously until reprogrammed by ICW4. In this
mode the 8259A will automatically perform a non·
specific EOI operation at the trailing edge of the last
interrupt acknowledge pulse (third pulse in MCS·80185,

lSI

IS5

154

153

152

151

ISO

101,101,101010101
Low•• 1 P~o~'y

Priority Statu!

The In Service (IS) bit can be reset either automatically
following the trailing edge of the last in sequence INTA
pulse (when AEOI bit in ICW1 is set) or by a command
word that must be issued to the 8259A before returning
from a service routine (EOI commllnd). An EOI command
must be issued twice, once for themaster and once for
the corresponding slave if slaves are in use.

=

Status

High •••

1716 15 1 4 1 3 1 2 1

Prlo~'y

ho 1

After Rotate (IR4 was serviced, all other priorities
rotated corresp(lndingly)
157
"IS" Status

lSI

IS5

154

High... Prlo~'y
Priority Status

153

152

151

ISO

101'lololololiJiJ
Low •••

Prlo~'y

I 11)0 1 7f1JD I 1
2

4

3

There are two ways to accomplish Automatic Rotation
using OCW2, the Rotate on Non-Specific EOI Command
(R = 1, SL = 0, EOI = 1 ) and the Rotate in
Automatic EOI Mode which is set by (R = 1, SL = 0,
EOI = 0) and cleared by (R = SL = 0, EOI = 0).

°

SPECIFIC ROTATION
(Specific Priority)
The programmer can change priorities by programming
the bottom priority and thus fixing all other priorities;
i.e., if IR5 is programmed as the bottom priority device,
then IR6 will have the highest one.
The Set Priority command is issued in OCW2 where:
R = 1, SEOI = 1; LO-L2 is the binary priority level code
of the bottom priority device.
Observe that in this mode internal status is updated by
software control during OCW2. However, it is independent of the End of Interrupt (EOI) command (also executed by OCW2). Priority changes can be executed during an EOI command by using the Rotate on Specific
EOI Command in OCW2 (R = 1, SL = 1, EOI = 1 and
LO-L2 = IR level to receive bottom priority).

B-l17

8259A/8259A-2/8259A-8

lTlM 81T

TO OTH£" "uaAn CELLS

0:;: EDGE

eLA " "

1::: lEVEL
elA Q

EDGE

+___+_--+__

SENSE

~LA~TE!CH:'-.-+-__

ISft lIT

SET

-<~t-tt-t-:::;!:::::--ti sn

IS"

''''DRITY
RESOLVIER

CONTROL
LOGIC
REOUEST
LATCH
NON·
MASKED

.,a

C

MGSaD/as
MODE

lJ

a

1NTl~
I'IIl!'H

~~g~8088 {

I~

INTAn

__

FREEZE

~r-----

NOTES
1. MAlTER CLEAR ACTIVE ONLY OURING ICW1
2.

fAEEZE/'S ACTIVE DURING iNTAl AND POLL SEQUENCES ONLY

1

TRUTH TAllLE FOR D·LATCH

OPEftATION
FOLLOW
HOLD

Priority Cell - Simplified Logic Diagram
LEVEL TRIGGERED MODE

In-Service Register (ISR): 8-bit register which contains
the priority levels that are being serviced. The ISA is
updated when an End 01 Interrupt command is issued.

This mode is programmed using bit 3 in ICW1.
If LTIM = '1,' an interrupt request will be recognized by a
'high' level on IR Input, and there is no need for an edge
detection. The interrupt request must be removed
before the EOI command is issued or the CPU interrupt
is enabled to prevent a second interrupt from occurring.
The above figure shows a conceptual circuit to give the
reader an understanding of the level sensitive and edge
sensitive input circuitry of the 8259A. Be sure to note
that the request latch is a transparent D type latch.
READING THE 8259A STATUS
The input status oj several internal registers can be
read to update the user information on the system.
The following registers can be read via OCW3
(IRR and ISR or OCWI (lMR).
Interrupt Request Register (lRR): 8-bit register which
contains the levels requesting an interrupt to be
acknowledged. The highest request level is reset from
the IRR when an interrupt is acknowledged. (Not
affected by IMR).

Interrupt Mask Register: 8-bit register which contains
the interrupt request lines which are masked.

The IRR can be read when, prior to the RD pulse, a
Read Register Command is issued with OCW3 (RA = 1,
RIS = 0).
The ISR can be read when, prior to the RD pulse.
a Read Register Command is issued with OCW3 (RR =
1. RIS = 1).
There is no need to write an OCW3 before every status
read operation, as long as the status read corresponds
with the previous one; i.e., the 8259A "remembers"
whether the IAA or ISA has been previously selected by
the OCW3. This is not true when poll is used.
After initialization the 8259A is set to IAA.
For reading the IMR, no OCW3 is needed. The output
data bus will contain the IMR whenever RD is active and
AO = 1 (OCW1).
Polling overrides status read when P = I, RR = 1 in
OCW3.

B-1l8

8259A/8259A-2/8259A-8
SUMMARY OF 8259A INSTRUCTION SET
In....

4

5
8

10
11

12
13
14
15
16
17

18
19
20

21
22
23
24
25

26
27
28
29
30
31
32
33
34

35
36
37
38
39
40
41
42
43
44

45

46
47
48
49
50

51
52

53
54
55
56
57

58
59
60
61

O......lIon Dncrlptlon

Mnemonic
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI
ICWI

A
B
C

0
E
F
G
H

o
o
o

o
o

o
K

o
o

M
N

o

0
P

o
o

ICW2
ICW3
ICW3
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4

K
L
M
N

ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4
ICW4

0
P
NA
NB
NC
NO
NE
NF
NG
NH
NI
NJ
NK
NL
NM
NN
NO
NP

OCWI
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW2
OCW3
OCW3

o

A6
AS
AS
AS
AS
AS
AS
A6

A5
A5
A5
A5
0
0
0

A7
A7
A7
A7
A7
A7
A7
A7

A6
A6
A6
AS
A6
A6
AS
AS

A5
A5
A5
A5
0
0

o

o
1

1
0
0

0
0

o

0

1

0

1

0
0

o
1

0

1

1
0
0

1

0
0
0

o

0

0
0

0
0

o

o

1

o
1

o

Format = 4, single, edge triggered

I
}

0
0

0
E
F
G
H

o
o
o
o
o
o
o
o
o
o
o

0

0

0

0
0
0
0
0
0
0
0
0

o
o
o
o
o
o
o
o
o
o

o

0

o

0

o
o
o
o
o
o

0

0
0
0
0
0

0
0
1

1

o
o

0

1

1

1

o

o

0

o

0

0

0

o

0

o
o

o

0

o
o
o

1

0
0

0

0
0

o

1

o
o

1

o
o
o
o

0
0

0

0

M6

M5

1

o
o

o

M4

M3

1

1

M2

Ml

MO

o
o

o
o

0

0

o
o
o

Q
0
0
0
OOL2L1LO
0
0
0
0
0

1

o
o

not lingle, le••1 triggered
lingle, edge triggered
lingle, 1•••1 triggered
not single, edge Irlggered
not lingle, I••el triggered

Buffered mode, master AEOI, B086, 8088
Fully nested mode, MCS-BO, non buffered, no AEOI

}

ICW4 N6 through ICW4 NO are identical to
ICW4 B through ICW4 0 with the addition 01
Fully Nested Mode
FUlly Nested Mode, MCS-SO/85, non-bullered, no AEOI

ICW4 NF through ICW4 NP are idenlical to
ICW4 F through ICW4 P with the addition 01
Fully Nested Mode

1

0
000009
0100L2L1LO

o
o

Format = 4,
Format = 8,
Format = 8,
Format = 8,
Format = 8,

o

o

1

Format = 4, lingle, edge triggered
Format = 4, single, I••el triggered
Format. 4, not lingle, edge triggered

l'

0

o
o

0
0

M7

o

ICW4 Required

Format = 8, single, level triggered

Formll = 8, not lingle, edge triggered
Format = 8, not lingle, 1...1 triggered

0
1

o
1

Byte 1 Inltiallzellon

Format = 4, not. single, level trig{'ered

Buffered mode, master, no AEOI, 808618088
Buffered mode, master, AEOI, MCS-BO/85

1

0

0
0

Format = 8, single, edge triggered

No action, redundant

1
0

1

0

0
0

o
o
o
o

0

0

0

No ICW4 Required

Non-buffered mode, no AEOI, B086/8088
Non-buffered mode, AEOI, MCS-80 I B5
Non-buffered mode, AEOI, B086/8088
Buffered mode, slave, no AEOI, MCS-80/85
Buffered mode, slave, no AEOI, BOB6/B088
Buffered mode, slave, AEOI, MCS-80/85
Buffered mode, slave, AEOI, 8086/8088
Buffered mode, master, no AEOI, MCS-BO/85

o

o
o
o

1

0
0
0

Format = 4, not single, edge triggered

Byte 2 initialization
Byte 3 initialization - master
Byte 3 initialization - slave
No actio", redundant
Non-buffered mode, no AEOI, 8086/8088
Non-buffered mode, AEOI, MCS-80/85
Non-buffered mode, AEOI, 8086/808B

0
1

Format = 4, single, level triggered

Byte 1 Initi.IlZlllon

0

A15 At4 A13 A12 All Al0 AS AS
S7 sa S5 S4 S3 S2 SI SO
o 0 0 0 0 S2 SI SO
o 0 0 0 0 0 0 0
00000001
0000000
o
0
0
0
0
1
o 0 0 0
0
o 0 0 0
0
1

M
S
A
B
C

E
SE
RE
RSE
R
CR
RS
P
RIS

A7
A7
A7
A7
A7
A7
A7
A7

o
o

0

0

0

L2

Ll

LO

0

1

0

0

o

0

Load mask register, read mask register
Non-specific EOI
Specific EOI, LO-L2 code of IS FF to be reset
Rotate on Non-Specific EOI
Rotate on Specific EOI LO-L2 code of line
Rotate in Auto.EOI (set)
Rotate in Auto EOI (clear)
Set Priority Command
Poll mode
Read IS .reglster

B-119

82S9A/82S9A-2/82S9A-8
SUMMARY OF 8259A INSTRUCTION SET (Cont.)
Ina...

Operallon D.acrlpllon

AO D7 De D5 D4 D3 D2 Dl DO

Mnamonlc

46

OCW3 RR

47

OCW3 SM

1

46

OCW3 RSM

0

1. In the master mode

SP pin = 1, In slave mode SP = 0

Nol.:

0

0

0

0

0
0

0

Read request register

0
0

1

0
0

Set special mask modi
Reset special mask mode

Clscldlng

to release the device routine address during bytes 2
and 3 of INTA. (Byte 2 only for 8086/8088).

The 8259A can be easily interconnected in a system of
one master with up to eight slaves to handle up to 64
priority levels.

The cascade bus lines are normally low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the trailing edge of the third pulse. It is
obvious that each 8259A in the system must follow a
separate initialization sequence and can be programmed to work in a different mode. An EOI command
must be issued twice: once for the master and once for
the corresponding slave. An address decoder is required
to activate the Chip Select (CS) input of each 8259A.

A typical MCS-80/85 system is shown in Figure 2. The
master controls, through the 3 line cascade bus, which
one of the slaves will release the corresponding
address.
As shown in Figure 2, the slave interrupt outputs are
connected to the master interrupt request inputs. When
a slave request line is activated and afterwards acknowledged, the master will enable the corresponding slave

The cascade lines of the Master 8259A are activated for
any interrupt input, even if no slave is connected to that
input.

ADDRESS 8US (161

\

CONTROL BUS

INT REa

\

\

DATA BUS III

---

- -

-

--I-

---

GL

6

t-- t-

- - - I-

r----

f-- f--

1----'
00·7

INT

tNTA

CS

Ao

00-7

IN!

INTA

CASe
8259A
SLAVE A

SPIEN7

f-- t-

f-- ---

--

...

cs

-

-

5

4

1CAS 2 1CAS 1

3

2

1

0

I II I I 1 1 I
76543210

8259A
SLAVE 8

t-

l

CS

CASO

CASO

CAS 1

CASl

6

5

4

3

2

1

16543210

I
INTERRU'T REQUESTS

Figure 2. Clscldlng the 8259A

B-120

INT

INTA

8259A
MASTER

SPIENM7 M6 M5 M. M3 M2 Ml MO

0

G!O 1 1 111111

:;00-7

CASZ

CAS 2

SilIEN'

...

I

LLtIl
.. I. I 1 1
2

1

0

8259A/8259A-2/8259A-8
PIN FUNCTIONS
NAME
Vcc

1/0

PIN#

I

28

+5v supply

14

Ground

GNO

CS

FUNCTION
INT

2

17

valid interrupt request is as-

18-25

IRo-IR7

Asynchronous inputs. An inter-

Write:

Read:
A low on this pin when CS is low
enables the 8259A to release
status onto the data bus for the
CPU.

3

0 7-00

I/O

4-11

INTA

26

8259A interrupt-vector data
onto the data bus. This is done
by a sequence of interrupt ac·
knowledge pulses issued by
the CPU.

Bidirectional Data Bus:
Control, status and interruptferred via this bus.

110

12,13,15

27

Ao

Cascade Lines:

The CAS lines form a private
8259A bus to control a multiple
8259A structure. These pins
are outputs for a master 8259A
and inputs for a slave 8259A.
SP/EN

110

16

Interrupt Acknowledge:
This pin is used to enable

vector information is transCASo-CAS 2

Interrupt Requests:
rupt request can be generated
by raising an IR input (low to
high) and holding it high until it
is acknowledged (Edge Triggered Mode), or iust by a high
level on an IR input (Level Trig·
gered Mode).

A low on this pin when CS is
low, enables the 8259A to ac·
cept command words from the
CPU.

Ri5

Interrupt:
This pin goes high whenever a
serted. 11 is used to interrupt
the CPU, thus it is connected to
the CPU's interrupt pin.

Chip Select
A low on this pin enables RO
and WR communication between the CPU and the 8259A.
INTA functions are independent
ofCS.

WR

0

Slave Program/Enable Buffer:
This is a dual function pin.
When in the Bufferad Mode it
can be used as an output to

AO Address Line:
This pin acts in conjunction with
the CS, WR, and Ri5 pins. It is
used by the 8259A to decipher
between various Command
Words the CPU writes and sta·
tus the CPU wishes to read. It
is typically connected to the
CPU AO address line (A 1 for
8086/8088).

control buffer transceivers

(EN). When not in the buffered
mode it is used as an input to

designate a master (SP = 1) or
slave (SP =0).

ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ... ,. - 40·C to 85·C
Storage Temperature ............ -65·C to + 150·C
Voltage On Any Pin
With Respect to Ground. . . . . . . . . .. - 0.5V to + 7V
Power Dissipation ......................... 1 Watt

D.C. CHARACTERISTICS
o·c to 70·C, Vce= 5V ± 10% (8259-A), Vee =

TA=

Symbol

Parameter

·COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification Is not
implied.

5V ± 10% (8259A)
Min.

Max.

Units

Test Conditions

Input Low Voltage

-.5

V

V IH

Input High Voltage

2.0

V cc + .5V

V

VOL

Output Low Voltage

.45

V

IOL=2.2 mA

V OH

Output High Voltage

2.4

V

IOH=-400j.tA

VOH(INT)

Interrupt Output High
Voltage

3.5
2.4

C
V

IOH= -100 j.tA
IOH = - 400,.A

VIL

III

Input Load Current

10

j.tA

VIN=V CC to OV

ILOL

Output Leakage Current

-10

j.tA

V ouT =0.45V

lec

Vee Supply Current

85

mA

ILiR

IR Input Load Current

-300

j.tA

VIN=O

10

j.tA

VIN=V CC

B-121

82S9A/82S9A-2/82S9A-8
8259A A.C. CHARACTERISTICS
T..,=O·Cto70·C Vc c=5V±5%(8259A·8)

VCC =5V±10%(8259A)

TIMING REQUIREMENTS
8259A·8

Parameter

Symbol

Min.

Max.

8259A

Max.

Min.

8259A·2
Min.

TAHRL

AD / CS Setup to RD / INTAj

50

0

0

ns

TRHAX

AO / CS Hold after RD IINTA1

5

0

0

ns

TRLRH

RD Pulse Width

420

235

160

ns

TAHWL

AO/CS Setup to WRj

50

0

0

ns

TWHAX

AO/CS Hold after WRj

20

0

0

ns

TWLWH

WR Pulse Width

400

290

190

ns

TDVWH

Data Setup to WRj

300

240

160

ns

TWHDX

Data Hold after WRj

40

0

0

ns

Interrupt Request Width (Low)

100

100

100

ns

Cascade Setup to Second or Third
INTAj (Slave Only)

55

55

40

ns

TRHRL

End of RD to Next Command

160

160

160

ns

TWHRL

End of WR to Next Command

190

190

190

ns

TJLJH
TCVIAL

Note: This is the low time required to clear the input latch

In

Test Conditions

Units

Max.

See Note 1

the edge triggered mode.

TIMING RESPONSES
8259A·8

Parameter

Symbol

Min.
TRLDV

Data Valid from RDIINTAj

Max.

8259A
Min.

Max.

8259A·2

Min.

200

300

Units

Test Conditions

120

ns

C of Data Bus
100 pF

C of Data Bus
Max text C = 100 pF
Min. test C = 15 pF

Max.

-

TRHDZ

Data Float after RD liNT A1

200

100

85

ns

TJHIH

Interrupt Output Delay

400

350

300

ns

TlAHCV

Cascade Valid from First INTAj
(Master Only)

565

565

360

ns

C'NT

CeAseADE

10

TRLEL

Enable Active from RD j or INTAj

160

125

100

ns

TRHEH

Enable Inactive from RDj or INTAj

325

150

d150

ns

TAHDV

Data Valid from Stable Address

350

200

200

ns

TCVDV

Cascade Valid to Valid Data

300

300

200

ns

= 100 pF
= 100 pF

CAPACITANCE
T..,= 25·C; VCC= GND= OV
Symbol

Parameter

Max.

Unit

C'N
C rlo

Input Capacitance

10

pF

fe = 1 MHz

I/O Capacitance

20

pF

Unmeasured pins returned to V ss

Min.

Typ.

Test Conditions

Input and Output Waveforms for A.C. Tests

2.4

0.45

___JX:: >"" ~'N" <:: X

'-----

B-122

=

82S9A/82S9A-2/82S9A-8
WRITE MODE
---TWLWH

\

-

Ci

TAHWL

-

-

TWHAX

-TDVWH-

READ/INTA MODE
TRLRH

\

-

\ I--

TRLEL

)

ADDRESS IUS

Ao

i
-

iJLTRHEH

-

t--TAHRL

t--TRHAX

K

--

·----------------9~_____'r------TRLDY

TRHDZ

-~

!----TAHDY

b ,. . .

-TWHDX

L

)

DATA IUS

-

-

~

}

ADDRESS IUS

OTHER TIMING

1IDIIIITl----___.

!----TWHRL·---_I

INTA SEQUENCE
IR

INT------..J
INTA---------~

-- -0--

D8-------- ____ _

_TCVIAL

CO.2-------------------r-------L1------~----~~--------------~IlIOn. '-.... ....... _ _ ft MIGM 1M

IIIIICI_-.-...,.

-TlALCV------_,'w"", -... ...... """'IIIU.

ill c.c.. , ... IIIICt . . ._ _ _ . ... ,.........

B-123

Appendix B
Device Specifications

•
•
•
•
•
•

8085 Peripherals·

inter
8155/8156/8155-2/8156-2
2048 BIT STATIC MOS RAM WITH I/O PORTS AND TIMER

• 256 Word x 8 Bits
• Single +5V Power Supply
• Completely Static Operation

•

1 Programmable 6-Bit I/O Port

• Internal Address Latch
• 2 Programmable 8 Bit I/O Ports

• Compatible with 8085A and 8088 CPU

• Programmable 14-Bit Binary Counter/
Timer
• Multiplexed Address and Data Bus
• 40 Pin DIP

The 8155 and 89156 are RAM and I/O chips to be used in the 8085A and 8088 microprocessor systems. The
RAM portion is designed with 2048 static cells organized as 256 x 8. They have a maximum access time of 400 ns
to permit use with no wait states in 8085A CPU. The 8155-2 and 8156-2 have maximum access times of 330 ns for use
with the 8085A-2 and the full speed 5 MHz 8088 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status
pins, thus allowing the other two ports to operate in handshake mode.
A 14-bit programmable counter /timer is jalso included on chip to provide either a square wave or terminal count pulse
for the CPU system depending on timer mode.

BLOCK DIAGRAM

PIN CONFIGURATION
PC,

Vee

PC,

PC,

TIMER IN

PC,

RESET

PC.

PCs

PB,

TIMER OUT

PBs

STATIC

101M

PBs

RAM

PB,

AD
WR

PB,

101M

AD O- 7

256 X 8

*
ALE

PB,

ALE

PB,

R5

AD.

PB.

W.

AD,

PA,

AD,

PAs

AD,

PAs

AD,

PA,

ADs

PA,

ADs

PA,

AD,

PA,

Vss

PA.

TIMER

RESET

TIMER elK
TIMER OUT

': 8155/8155·2

B-124

= CE. 8156/8156·2 = CE

~
~

PAO- 7

PBo'7

G

Lvcc ~+5V)
Vss (OV)

pe a - s

inter
8185/8185-2
1024 x 8-BIT STATIC RAM FOR MCS-85™

• Multiplexed Address and Data Bus

• Low Standby Power Dissipation

• Directly Compatible with 808SA
and 8088 Microprocessors

• Single +SV Supply

• Low Operating Power Dissipation

• High Density 18-Pin Package

The Intel'" 8185 is an 8192-bit static random access memory (RAM) organized as 1024 words by 8-bits using
N-channel Silicon-Gate MOS technology. The multiplexed address and data bus allows the 8185 to interface directly
to the 8085A and 8088 microprocessors to provide a maximum level of system integration.
The low standby power dissipation minimizes system power requirements when the 8185 is disabled.
The 8185-2 is a high-speed selected version of the 8185 that is compatible with the 5 MHz 8085A-2 and the full speed
5 MHz 8088.

PIN CONFIGURATION
ADD

Vee

AD,

RD

AD,

WR

AD,

ALE

AD4

es

BLOCK DIAGRAM

cs----·I
eE,----.J
c~----.J

ADs

eE,

fli)----.J

AD,

eE,

WR---~-I

AD,

Ag

Vss

A,

R!W
LOGiC

ALE---~-I

DATA
BUS

BUFFER

PIN NAMES
AD O·AD 7

As, Ag
es

cr,

ADDRESS/DATA LINES
ADDRESS LINES
CHIP SELECT

CHIP ENABLE

RO

READ ENABLE
WRITE ENABLE

WR

A,.Ag---~·1
A L E - - - - - L______~

CHIP ENABLE (101M)

eE,
ALE

ADDRESS LATCH ENABLE

B-125

1K

x8

RAM

MEMGRY
ARRAY

8355/8355-2
16,384-BIT ROM WITH 1/0

• Each 110 Port Line Individually
Programmable as Input or Output

• 2048 Words x 8 Bits
• Single

+ 5V Power Supply

• Multiplexed Address and Data Bus

• Directly compatible with 8085A
and 8088 Microprocessors

• Internal Address Latch

• 2 General Purpose 8·Bit 110 Ports

• 40·Pin DIP

The Intel@ 8355 is a ROM and I/O chip to be used in the 8085A and 8088 microprocessor systems. The ROM portion is organized as 2048 words by 8 bits. It has a maximum acess time of 400 ns to permit use with no wait states in
the 8085A CPU.
The I/O portion consists of 2 general purpose I/O ports. Each I/O port has 8 port lines and each I/O port line is
individually programmable as input or output.
The 8355-2 has a 300ns access time for compatibility with the 8085A-2 and full speed 5 MHz 8088 microprocessors.

PIN CONFIGURATION

BLOCK DIAGRAM

Vee

elK
PB,
N.C. (NOT CONNECTED)

5

PB,
PB,

AD O_ 7

PB,
PB,

R1l

PBo

lOW

PA,
PA,
PA,
PA,
PA,
PA,
PA,

AD,

A s- lO

eE,

CE1
101M
ALE

R1l
lOW
RESET

B
ROM

PORT A

G

PAO--7

G

PB O- 7

iOR

PA o

~vee

A10
A,

1+5VI

Vss (OV)

Vss

B-126

inter
8755A 18755A-2
16,384-8IT EPROM WITH 1/0
• 2048 Words x 8 Bits

• 2 General Purpose 8·Bit 1/0 Ports

• Single + 5V Power Supply (Vee>

• Each 1/0 Port Line Individually
Programmable as Input or Output

• Directly Compatible with 8085A
and 8088 Microprocessors

• U.V. Erasable and Electrically
Reprogrammable

• Multiplexed Address and, Data Bus
• 40·Pin DIP

• Internal Address Latch

The Intel'" 8755A is an erasable and electrically reprogram mabie ROM (EPROM) and 110 chip to be used in the 8085A
and 8088 microprocessor systems. The EPROM portion is organized as 2048 words by 8 bits. It has a maximum
access time of 450 ns to permit use with no wait states in an 8085A CPU.
The 1/0 portion consists of 2 general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is
individually programmable as input or output.
The 8755A-2 is a high speed selected version of the 8755A compatible with the 5 MHz 8085A-2 and the full speed 5
MHz 8088.

PIN CONFIGURATION

BLOCK DIAGRAM

Vee

PB,

ClK

PBs
RESET

PIIs

Voo

PB,
PB,

101M

READY

A"o_,

PB,
PB,

AS--10

PlIo
CE,

lOW

PA,

ALE

PAs

101M

AD.

PA,

ALE

AD,

PA,

AD
lOW

AD,
PA,

RESET

AD,

PA,

lOR

AD,

PAD

AD.

A,.

AD,

2K x 8
EPROM

PROG/CE,

AD,

Voo

lis.

B-127

PAO-7

G
G

PBO-7

~veel+5V)
Vss IOV)

Appendix B
Device Specifications
III~

.1

• Standard Peripherals··

• For complete specifications refer to the
Intel MCS-85 User's Manual.
"For complete specifications refer to the
Intel Peripheral Design Handbook.
"'For complete specifications refer to the 1979
Intel Component Data Catalog.

8041 AJ8641 AJ8741 A
UNIVERSAL PERIPHERAL INTERFACE
8·BIT MICROCOMPUTER
CPU plus ROM, RAM, 110, Timer
• 8·Bit
and Clock in a Single Package
8·Bit Status and Two Data Regis·
• One
ters for Asynchronous Slave·to·Master
Interface
DMA, Interrupt, or Polled Operation
• Supported
1024 x 8 ROM/EPROM, 64 x 8 RAM,
• 8·Bit
Timer/Counter, 18 Programmable

110 Pins

Compatible with MCS·48™,
• Fully
MCS.80™, MCS·85™, and MCS·86™
Microprocessor Families
Interchangeable ROM and EPROM
• Versions
• 3.6 MHz 8741A·8 Available
• Expandable I/O
• RAM Power· Down Capability
• Over 90 Instructions: 70% Single Byte
• Single 5V Supply

The Intel'" 8041A/8741A is a general purpose, programmable interface device designed for use with a variety of 8-bit
microprocessor systems. It contains a low cost microcomputer with program memory, data memory, 8-bit CPU, I/O
ports, timer/counter, and clock in a single 40·pin package. Interface registers are included to enable the UPI device to
function as a peripheral controller in MCS-48™, MCS-80™, MCS-85™, MCS-86™, and other 8-bit systems.
The UPI_41A™ has 1K words of program memory and 64 words of data memory on-chip. To allow full user flexibility the
program memory is available as ROM in the 8041A version or as UV-erasable EPROM in the 8741A version. The 8741A
and the 8041A are fully pin compatible for easy transition from prototype to production level designs. The 8641A is a
one-time programmable (at the factory) 8741A which can be ordered as the first 25 pieces of a new 8041A order. The
substitution of 8641A's for 8041A's allows for very fast turnaround for initial code verification and evaluation results.
The device has two 8-bit, TTL compatible I/O ports and two test inputs. Individual port lines can function as either inputs or outputs under software control. I/O can be expanded with the 8243 device which is directly compatible and has
·,6 I/O lines. An 8-bit programmable timer/counter is included in the UPI device for generating timing sequences or
counting external inputs. Additional UPI features include: single 5V supply, low power standby mode (in the 8041 A).
single-step mode for debug (in the 8741A), and dual working register banks.
Because it's a complete microcomputer, the UPI provides more flexibility for the designer than conventional LSI interface devices. It is designed to be an efficient controller as well as an arithmetic processor. Applications include keyboard scanning, printer control, display multiplexing and similar functions which involve interfacing peripheral
devices to microprocessor systems.
PIN CONFIGURATION

BLOCK DIAGRAM

~-_~~_J~ '"

TESTQ
XTAL1
XTAL2

[go.

•

MEMO"'

~,
RESIDENT

64_8
RANDOM

:::::= 11'

ACCESS

...--

'--~::::;;;;i;';:;:;;:-r'

W'II"-_

INTEAFACE

C<-_

~-

SYNC

H-_

P"

PROG

""'--

.10
Voo

XTAL1~_.--L

r

~~o~:l XTAL2-.-l::J

CRYSTAL

Vss

B-128

MEMORY

inter
8202
DYNAMIC RAM CONTROLLER
Provides All Signals Necessary to·
• Control
2104A, 2117, or 2118 Dynamic

•
•
•
•

• Provides Transparent Refresh Capability
Fully Compatible with Intel® 8080A,
• 8085A
and 8086 Microprocessors
SOS5A Status for Advanced
• Decodes
Read Capability

Memories
Directly Addresses and Drives Up to
128K Bytes Without External Drivers
Provides Address Multiplexing
and Strobes
Provides a Refresh Timer and a
Refresh Counter
Refresh Cycles May be Internally or
Externally Requested

System Acknowledge and
• Provides
Transfer Acknowledge Signals
• Internal or External Clock Capability

The 8202 is a Dynamic RAM System Controller designed to provide all signals necessary to use 2104A, 2117, or 2118
Dynamic RAMs in microcomputer systems. The 8202 provides multiplexed addresses and address strobes, as well as
refresh/access arbitration. Refresh cycles can be started internally or externally.

PIN CONFIGURATION

8202 BLOCK DIAGRAM

~

AH4

vcc

AH3

AHS

AH2

AHS

AH,

X,ICLK

Ho

Xo'OP2

1:o.

ALo
OUTO
AL,
OUT,
AL2

AH06
v

REFRESH
COUNTER

RDIS'
WR
SACK

RD/S'

AL3

XACK

WR
PCS
REFRQ/ALE

OUT3

WE

AL4

CAS

ALs
OUTs

.

BO
8,/OP,

--------

AAll3
B,IOP,

RAS2

OUTS

AAll,

VSS

RASo

ARBITER

I-

OSCILLATOR

TNK

B-129

1
TIMING
AND
CONTROL

I---- WE
I---- CAS
I---- RASa
I---- RAS,

f-- RAS2

r-r--

.

X O/OP2

X,/eLK

OUT06

r-- RAS3

t
REFRESH
TIMER

BO

ALslOP3

~

L

PCS

OUT2

OUT4

I

t

TNK
REFRQIALE

MULTIPLEXER

XACK
SACK

inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• I/O Port or Memory Selector

• Low Input Load Current - .25 mA
max., 1/6 Standard TTL Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp

• Simple Expansion - Enable Inputs
• High Speed Schottky Bipolar
Technology - 18ns Max. Delay

• Outputs Sink 10 mA min.
• 16-Pin Dual-In-Line Ceramic or
Plastic Package

• Directly Compatible with TTL Logic
Circuits

The 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory components with active low chip select input. When the 8205 is enabled, one of its eight outputs goes
"low", thus a single row of a memory system is selected. The 3 chip enable inputs on the 8205 allow easy
system expansion. For very large systems, 8205 decoders can be cascaded such that each decoder can drive
eight other decoders for arbitrary memory expansions.
The Intel@8205 is packaged in a standard 16 pin dual-in-line package; and its performance is specified over
the temperature range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to
obtain fast switching speeds results in higher performance than equivalent devices made with a gold diffusion process.

PIN CONFIGURATION

LOGIC SYMBOL

Ao

16

V·cc

Ao

Al

15

0;;

Al

A,

14

G,'

A2

E;'

4

E3

6

0;
GRD

13

0;

12

0;

11

0;

E,

10

Os

E2

9

06

E3

8205

E;-

8

8205

ADDRESS

PIN NAMES
ADDRESS INPUTS
ENABLE INPUTS
DECODED OUTPUTS

A,

A,

E,

E,

L
H
L
H
L
H
L
H

L
L
H

L
L
L
L
H
H
H
H

L
L
L
L
L
L
L
L
L
H
L
H
H
L
H

L
L
L
L
L
L
L
L
L
L
H

X
X
X
X
X
X

X

B-130

ENABLE

Ao

H
L
L
H

H
X

X
X
X
X
X
X

X
X

X
X
X
X

X

H

L
H
H

"

H
H

0

,
H
L

3' 4'
H
H

H

H

H

L

H
H

H

H
H

H
H
H
H
H

H

H

H

H

H

H

H
L
L
L
L
H
H
H

OUTPUTS
H
H

H

H
H
H

,.
H
H
L

L
H
H
H

H

H

H

H
H

H
H

H
H
H
H
H
H
H

H
H

H

H

H

H
H
H

H
H

H
H

H

H

H

H
H

H

5

ii

7

H
H

H
H

H

H

H

H
H

H
H
L

H

H

H
H

L

H
H
H

H

L

H

H
H
H

H

H

L
H

H
H

H
H

H
H

H

H

H
H
H
H

H
H

H
H

H
H

H

"

H
H

H
H
H

H

inter

'$>/", '

8251 A
PROGRAMMABLE COMMUNICATION

• Synchronous and Asynchronous
Operation

• Asynchronous 5·8 Bit Characters;
Clock Rate-1, 16 or 64 Times Baud
Rate; Break Character Generation; 1,
11/2, or 2 Stop Bits; False Start Bit
Detection; Automatic Break Detect
and Handling.

O~ry

INTERFAtit::"

• Asynchronous Baud Rate 19.2K Baud

• Synchronous 5·8 Bit Characters;
Internal or External Character Synchro·
nization; Automatic Sync Insertion

• Synchronous Baud Rate Baud

OO!CO%?}}fSao

DC to

'0

&'ZtrB

• Full Duplex, Double Buffered, Trans·
mitter and Receiver
• Error Detection Framing

Parity, Overrun and

• Fully Compatible with 8080/8085 CPU
• 28·Pin DIP Package
• All Inputs and Outputs are TTL
Compatible

+ 5V Supply

• Single

DC to 64K

• Single TTL Clock

The Intel'" 8251A is the enhanced version of the industry standard, Intel'" 8251 Universal Synchronous/Asynchronous
Receiver/Transmitter (USART), designed for data communications with Intel's new high performance family of
microprocessors such as the 8085. The 8251A is used as a peripheral device and is programmed by the CPU to operate
using virtually any serial data transmission technique presently in use (including IBM "bi·sync"). The USART accepts
data characters from the CPU in parallel format and then converts them into a continuous serial data stream for
transmission. Simultaneously, it can receive serial data streams and convert them into parallel data characters for the
CPU. The USART will signal the CPU whenever it can accept a new character for transmission or whenever it has
received a character for the CPU. The CPU can read the complete status of the USART at any time. These include data
transmission errors and control signals such as SYNDET, TxEMPTY. The chip is constructed using N·channel silicon
gate technology.
PIN CONFIGURATION
0,

BLOCK DIAGRAM

0,

0,

On

R.D

Vcr

GND

R.e

0,

DTR

De

RTS

D,

DSR

D7

RESET

he

I

hD

c/o

C'D

eLK

Data Bus (8 bltsi
Control or Data IS 10 be Wrillen or Read
Read Data Cornmand
Write Data or Control Command
Chip Enable
Clock Pulse (TTLI

RESET

Reset

CS

"

f--

j
I

T"RDY

,

TRANSMIT
BUFFER
(P - 5)

1

I

TRANSMIT
CONTROL

r-~-

DSR

Data Set Ready

DTR

Data Terminal Ready

SYNDET/SD

Sync Detect!
Break Detect

RTS

Request to Send Data

CTS

Clear to Send Data

DTR ___D

MOD'M

cTI __ -.

CONTROL

RTS -

hRDY

!-- h'
hC

I

I

I
I

"1

~J

I

/:I

hl

Transmitter Clock

T,'

Transmitter Empty

TICD

Transmitter Data

+5 Volt Supply

FGC

Vee

INTE HNAL

Receiver Clock

Receiver Data
Receiver Ready (has character for 80801
Transmitter Ready {ready for char from 80801

GND

Ground

RxD
R"RDY
T"RDY

IlATABtiS

B-131

-

hD

I '

-

O-- 8273 Programmable HOLC/SOLC Protocol Controller is a dedicated device designed to support the ISO/CCITT's HOLC and IBM's SOLC communication line protocols. It is fully compatible with Intel's new high performance
microcomputer systems such as the MCS-85™. A frame level command set is achieved by a unique microprogrammed
dual processor chip architecture. The processing capability supported by the 8273 relieves the system CPU of the low
level real-time tasks normally associated with controllers.
PIN CONFIGURATION
FLAG DET

Vee

Tx INT

PB4
PB3

elK
RESET

PI!2

TxDACK

PB,

TxDRa

ATS

RxDACK

PA,

RxDAQ

BLOCK DIAGRAM

PA,

RD

PA2

WR

eD

Rx tNT

rn

DBO

T,D

DB'

'FXC

DB,

RiC

DB3

R,D

DB4

32xCLK

DB5

cs

DB.

OPLL

DB'

A,

GND

Ao

06 0 _ 7
hD

TxC

TKDRQ

DPLi.
32X elK

R;5"A"C'K

RTS

PB'_4
hiNT
RKINT

Rci
WR

ffi

co

PA 2_4

Ao
A,

PIN NAMES

RESET

R,D

R;C
DATA BUS (8 BITS)

CS

CHIP SELECT

FLAG DETECT
TRANSMITTER INTERRUPT

32xCLK

32 TIMES CLOCK

Rx 0
Rx C
Tx C
Tx 0

RECEIVER DATA
RECEIVER CLOCK
TRANSMITTER CLOCK
TRANSMITTER DATA

OBO-OB7
~
TxlNT
elK
RESET
Tx DACK
TxORQ

CLOCK INPUT

WR

READ INPUT
WRITE INPUT
RECEIVER DMA ACKNOWLEDGE

ilii

RxDACK

RESET
TRANSMITTER DMA ACKNOWLEDGE
TRANSMITTER DMA REQUEST

rn

CD

FLAG OET

CLEAR TO SEND

CPU INTERFACE

CARRIER DETECT

PA2-PA4 GP INPUT PORTS

~-PB4 ~:g~~:~~6~~~~

RxORQ
Rx INT

RECEIVER DMA REQUEST

RECEIVER INTERRUPT

Vee

+5 VOLT SUPPLY

Al>-A'

COMMAND REGISTER SELECT ADDRESS

GNO

GROUND

liPIT

cs

DIGITAL PHASE LOCKED LOOP

B-135

MOOEM INTERFACE

8275
PROGRAMMABLE CRT CONTROLLER
Programmable Screen and Character
• Format

Fully MCS.80™and MCS.85™
• Compatible

• 6 Independent Visual Field Attributes

• Dual Row Buffers
• Programmable DMA Burst Mode
• Single + 5V Supply

• 11 Visual Character Attributes
(Graphic Capability)

• Cursor Control (4 Types)
• Light Pen Detection and Registers

• 40·Pin Package

The Intelll> 8275 Programmable CRT Controller is a single chip device. to interface CRT raster scan displays with
Intelll> microcomputer systems. Its primary function is to refresh the display by buffering the information from main
memory and keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple
interface to almost any raster scan CRT display with a minimum of external hardware and software overhead.

BLOCK DIAGRAM

PIN CONFIGURATION

vcc
LAO
LA,
LTEN
RVV
VSP
GPA,
GPAo
HLGT
IRQ
CCLK
CCe
CCs
CC4
CC3
CC2
CC,
CCo

LC3
LC2
LC,
LCO
DRQ
DACK
HRTC
VRTC

RD
WR
LPEN
DBa
DB,
DB2
DB3
DB4
DBS
DBe
DB7
GND

eeL.

OBo-7

CCO-6

ORQ _ _ _- ,
LCO_3

DACK
IRQ

cr
AO

LAO_l

AD

PIN NAMES

HRTt
VRle
HLGT
RW
LTEN

VS.
GPAO_l

DIIO ,

B1 DIRECTIONAL DATA BUS

DRQ

DMA REQUEST OUTPUT

""""

DMA ACKNOWLEDGE INPUT
INTERRUPT REQUEST OUTPUT
READ STROBE INPUT
WRITE STROBE INPUT
REGISTER ADDRESS INPUT
CHIP SELECT INPUT
CHARACTER CLOCK INPUT
CHARACTER CODE OUTPUTS

IRQ

III!
ii1I
AD
C$

CCLK
CCo_6

LCo_3

..... ,

LINE COUNTER OUTPUll

HRTe

HORIZONTAL RETRACE OUTPUT
VERTICAL RETRACE OUTPUT
HIGHlIQHT OUTPUT
-REVERSE VIDEO OUTPUT
LIGHT ENABLE OUTPUT
VIDEO SUPPRESS OUTPUT
GENERAL. PURPOSE ATTRIBUTE OUTPUTS
LIGHT PEN INPUT

VAle
HLGT

RVV
LTEN
V. .

GPAo 1
LPEN

LINE ATTRIBUTE OUTPUTS

LPEN

B-136

inter
8279/8279·5
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
• MCS·85™ Compatible 8279·5

• Dual 8· or 16·Numerical Display

• Simultaneous Keyboard Display
Operations

• Single 16·Character Display

• Scanned Keyboard Mode

• Right or Left Entry 16·Byte Display
RAM

• Scanned Sensor Mode
• Strobed Input Entry Mode

• Mode Programmable from CPU

• 8·Character Keyboard FIFO

• Programmable Scan Timing

• 2·Key Lockout or N·Key Rollover with
Contact Debounce

• Interrupt Output on Key Entry

The Intel 8279 is a general purpose programmable keyboard and display I/O interface device designed for use with
Intel microprocessors. The keyboard portion can provide a scanned interface to a 64-contact key matrix. The
keyboard portion will also interface to an array of sensors or a strobed interface keyboard, such as the hall effect and
ferrite variety. Key depressions can be 2·key lockout or N·key rollover. Keyboard entries are debounced and strobed in
an 8-character FIFO. If more than 8 characters are entered, overrun status is set. Key entries set the interrupt output
line to the CPU.
The display portion provides a scanned display interface for LED, incandescent, and other popular display
technologies. Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279
has 16X8 display RAM which can be organized into dual 16x4. The RAM can be loaded or interrogated by the CPU. Both
right entry, calculator and left entry typewriter disPlay formats are possible. Bath read and write of the display RAM
can be done with auto-increment of the display RAM address.

PIN CONFIGURATION

LOGIC SYMBOL
Vee

PIN NAMES

,RQ

DATA BUS (81 DIRECTIONALI

Olio,
I

_I

RLO·1

SHIFT 1 - - - -

CLOCK INPUT

-

KEV DATA

RE~ET INP~ __ •__ ~~_.

AD

IW-_+-'C+'~~~M-'--'----wAiTeINiil.iT·----BUfFER ADDRESS

Viii

INTERRUPT REQUESTOtiYPuT

E:---t-""or.;:SCAT.N;li~-·-I

RETURN LINES

I

SHIFT INPUT ._ -==~­
CONTROLfSTROBE INPUT

CNTLlSTB

CPU
INTERFACE

cs

SLo.J

SCAN

OISl'LAV (A! OUTPUTS

o

OTsP'LAV"iBi-OUTPUTS-

O' BLANKOISPlAY

AD

OUTPUT

OUT Ao.]

RESET

DISPLAV

ClK

Vss

B-137

OUTB!)'J

DATA

8291
GPIB TALKER/LISTENER
to Interface Microprocessors
• Designed
(e.g., 8080, 8085, 8086, 8048) to an
IEEE Standard 488 Digital Interface
Bus
Data Transfer Rate
• Programmable
Source and Acceptor
• Complete
Handshake
Talker and Listener
• Complete
Functions with Extended Addressing
Request, Parallel Poll, Device
• Service
Clear, Device Trigger, Remote/Local
Functions
Interrupts
• Selectable
On-Chip
Primary
and Secondary
• Address Recognition
Handling of Addressing and
• Automatic
Handshake Protocol

iI

•

1 - 8 MHz Clock Range
16 Registers (8 Read, 8 Write), 2 for
Data Transfer, the Rest for Interface
Function Control, Status, etc.

Interfaces to External Non• Directly
Inverting Transceivers for Connection
to the GPIB
Three Addressing Modes,
• Provides
Allowing the Chip to be Addressed
Either as a Major or a Minor Talker/
Listener with Primary or Secondary
Addressing
DMA Handshake Provision Allows for
Bus Transfers without CPU Intervention

•
Output Pin
• Trigger
EOS (End of Sequence)
• On-Chip
Message Recognition Facilitates
Handling of Multi-Byte Transfers

• Provision for Software Implementation
of Additional Features

The 8291 GPIB Talker/Listener is a microprocessor-controlled chip designed to interface microprocessors (e.g., 8048,
8080,8085,8086) to an IEEE Standard 488 Instrumentation Interface Bus. It implements all of the Standard's interface
functions except for the controller.

PIN CONFIGURATION

BLOCK DIAGRAM
18291
GPIB DATA

INTERFACE

FUNCTIONS

I~===""",

SH

GPIB CONTROL

AH

~~
pp

B-138

JTO NON·INVERTING
BUS TRANSCEIVERS

TE
LE

I

T/R CONTROL

inter
8292
GPIB CONTROLLER

FEATURES:
• Complete IEEE Standard 488 Controller
Function.

• Complete Implementation of Transfer
Control Protocol.

• Interface Clear (IFC) Sending Capability
Allows for Seizure of Control and/or
Initialization of the Bus.

• Synchronous Control Seizure Prevents
the Destruction of any Data
Transmission in Progress.

• Responds to Service Requests (SRC).

• Connects with the 8291 to Form a
Complete IEEE Standard 488 Interface
Talker /Listener /Controller.

• Sends (REN), Allowing Instruments to
Switch to Remote Control.

The 8292 GPIB CONTROLLER is a microprocessor-controlled chip designed to connect with the 8291
GPIB TALKER/LISTENER to implement the full IEEE Standard 488 controller function, including transfer
control protocol. The 8292 is a pre-programmed UPI-41A: M

PIN CONFIGURATION

IFCR

Xl

VCC
COUNT

X2

REN

RESET

OAV

NC

IBFI

Cs

OBFI

GND

EOI

RD

SPI

AO

TCI

WR

CIC

SYNC

DO

8291,8292 SYSTEM DIAGRAM

8292
GPIB
CQNTROLLfR

NC
ATNO

01

NC

D2

CLTH

03

NC

04

NC

D5

SYC

De

IFC

07

p;'fNi

VSS

SRQ
GENERAL PURPOSE INTERFACE BUS

B-139

8293
GPIB TRANSCEIVER
• Nine Open-collector or Three-state
Line Drivers
• 48 mA Sink Current Capability on
Each Line Driver
• Nine Schmitt-type Line Receivers
• High Capacitance Load Drive
Capability
• Single 5V Power Supply
• 28-Pin Package
• Low Power HMOS Design

• On-chip Decoder for Mode
Configuration
• Power Up/Power Down Protection to
Prevent Disrupting the IEEE Bus
• Connects with the 8291 and 8292 to
Form an IEEE Standard 488 Interface
Talker/Listener/Controller with no
Additional Components
• Only Two 8293's Required per GPIB
Interface

The Intel@ 8293 GPIB Transceiver is a high current, non-inverting buffer chip designed to interface the 8291 GPIB
Talker/Listener or the 8292 GPIB Controller with the 8291 to the IEEE Standard 488-1978 Instrumentation Interface
Bus. Each GPIB interface would contain two 8293 Bus Transceivers. In addition, the 8293 can also be used as a general
purpose bus driver.

PIN CONFIGURATION

TR'

8291,8292, 8293

SYST~M

DIAGRAM

Vee
8257

ORO

OPTB

829'
GPIB
TALKERI
LISTENER

DATA8
BUS9
DATA4
DATA5
TIR',

BUS8

GENERAL PURPOSE INTERFACE BUS

B-140

8292
GPIB
CONTROLLER

8294
DATA ENCRYPTION UNIT

• 7·Bit User Output Port
• Single 5V :t 10% Power Supply
to MCS·86™, MCg-85™,
• Peripheral
MCS·80™ and MCS·48™ Processors

Certified by National Bureau of
• Standards

• 80 Byte/Sec Data Conversion Rate
Data Encryption Using 56· Bit
• 64·Bit
Key

Implements Federal Information
• Processing
Data Encryption Standard

• DMA Interface
3 Interrupt Outputs to Aid in Loading
• and
Unloading Data

• Encrypt and Decrypt Modes Available

DESCRIPTION
The Intel@ 8294 Data Encryption Unit (DEU) is a microprocessor peripheral device designed to encrypt and decrypt
64-bit blocks of data using the algorithm specified in the Federal Information Processing Data Encryption Standard.
The DEU operates on 64-bit text words using a 56-bit user-specified key to produce 64-bit cipher words. The operation
is reversible: if the cipher word is operated upon, the original text word is produced. The algorithm itself is permanently contained in the 8294; however, the 56-bit key is user-defined and may be changed at any time.
The 56-bit key and 64-bit message data are transferred to and from the 8294 in 8-bit bytes by way of the system data
bus. A DMA interface and three interrupt outputs are available to minimize software overhead associated with data
transfer. Also, by using the DMA interface two or more DEUs may be operated in parallel to achieve effective system
conversion rates which are virtually any multiple of 80 bytes/second. The 8294 also has a 7-bit TTL compatible output
port for user-specified functions.
Because the 8294 implements the NBS encryption algorithm it can be used in a variety of Electronic Funds Transfer
applications as well as other electronic banking and data handling applications where data must be encrypted.

PIN
CONFIGURATION

Ne
X1

Vee
Ne
DACK

es
GND
AO

ViR

DRO
SRO
OAV
Ne
P.
P5
P4
P3

PO
VDD
Ne
D5
D6
D7
GND

ceMP

PIN NAMES

PIN NAME

BLOCK DIAGRAM

FUNCTION

DATA
07- 0 0

RD,WR

cs
A,

RESET

X"X2
SYNC
DRQ,DACK
SRQ,OAV,CCMP
Ps'Po
vcc,vOD,GND
NC

DATA BUS
READ,WRITE STROBES
CHIP SELECT
CONTROL/DATA SELECT
RESET INPUT
FREQUENCY REFERENCE INPUT
HIGH FREQUENCY OUTPUT
DMA REOUEST,DMA ACKNOWLEDGE
INTERRUPT REQUEST OUTPUTS
OUTPUT PORT LINES

BUS

A,

+ SV POWER,GND

SRa
QAV

NO CONNECTION

ceMP

RESET~
SYNC

X,

Ne
Ne

X2

+5V-POWER-GND--

B-141

TIMING

INTERNAL
BUS

8295
DOT MATRIX PRINTER CONTROLLER

• Interfaces Dot Matrix Printers to
MCS.48™, MCS.8018S™, MCS·86™
Systems

• Programmable Print Intensity
• Single or Double Width Printing

• 40 Character Buffer On Chip
• Serial or Parallel Communication with
Host

• Programmable Multiple Line Feeds

• DMA Transfer Capability

• 3 Tabulations

• Programmable Character Density (10 or
12 Chararctersllnch)

• 2 General Purpose Outputs

The Intel@ 8295 Dot Matrix Printer Controller provides an Interface for microprocessors to the LAC 7040 Series dot
matrix impact printers. It may also be used as an Interface to other similar printers.
The chip may be used in a serial or parallel communication mode with the host processor. In parallel mode, data
transfers are based on polling, interrupts, or DMA. Furthermore, it provides internal buffering of up to 40 characters
and contains a 7 x 7 matrix character generator accommodating 64 ASCII characters.

PIN
CONFIGURATION

PIN NAMES

BLOCK DIAGRAM
INTERNAL

PIN NAME

BUS

FUNCTION
DATA 8US

READ, WRITE STROBES
CHIP SELECT
RESET INPUT
FREQUENCY AEFERENCE INPUTS
HIGH FREQUENCY OUTPUT
MAIN, PAPER FEED MOTOR DAIVES

DMA REQUEST, ACKNOWLEDGE

SERIAL INPUT, CLEAR·TO·SEND
IRQ/SEA

81-87

PFEED
HOME, fOF
STB

GP1,GP2
Vee. VOD, GND

INTERRUPT REQUEST, SERIAL GROUND
SOLENOID DRIVE OUTPUTS
PAPER FEED INPUT
HOME, TOp·Of·FORM INPUTS
SOLENOID STROBE OUTPUT
GENERAL PURPOSE OUTPUTS
+ 5V POWER, OND

B-142

Appendix B
Device Specifications

• RAM Memories···

'For complete specifications refer to the
Intel MCS-85 User's Manual.
"For complete specifications refer to the
Intel Peripheral Design Handbook.
'" For complete specifications refer to the 1979
Intel Component Data Catalog.

inter
2114A
1024 X 4 BIT STATIC RAM
I
I

2114AL-2

2114AL-3

2114AL-4

2114A-4

2114A-5

120

150

40

40

200
40

200
70

250
70

Max. Access Time (ns)
Max. Current (rnA)

•
•
•
•
•

Static Memory - No Clock
• orCompletely
Timing Strobe Required
Directly TTL Compatible: All Inputs
• and
Outputs
Common
Input and Output USing
• Three-StateDataOutputs
• 2114 Replacement

HMOS Technology
Low Power, High Speed
Identical Cycle and Access Times
Single +5V Supply ±10%
High Density 18 Pin Package

The Intel 2ll4A is a 4096-bil static Random Access Memory organized as 1024 words by 4-bits using HMOS. a high performance
MOS technology. It uses fully DC stable (static) circuitry throughout. in both the array and the decoding. therefore it requires no
clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The data is read
out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2l14A is designed for memory applications where the high performance and high reliability of HMOS. low cost. large bit
storage. and simple interfacing are important design objectives. The 2ll4A is placed in an l8-pin package for the highest
possible density.
It is directly TTL compatible in all respects: inputs. outputs. and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.

PIN CONFIGURATION

""
A5

A4

Vee

LOGIC SYMBOL
A,
A.
A4

A,

A,

""

A.

I/O,

Ag

A,

I/O,

A,

A,

1/°2

..,
CS
GND

1/03

~GND

~

ROW
SELECT

MEMORY ARRAY
64 ROWS

64 COLUMNS

@

A,-

As

A5

110,

A

@

~Vcc

~
2':

5'1)
As

A4
A,

BLOCK DIAGRAM
~4~

@

1/0 3

As

110,

@

A,

1/°4

As

WE

A,

1/°4

WE

es

PIN NAMES
AO-Ag
WE

ADDRESS INPUTS

Vee POWER (+5VI

WR ITE ENABLE

GND GROUND

CS

CHIP SELECT

WE~-L-.'"

110,-1/04 DATA INPUT/DUTPUT

B-143

0= PIN

NUMBERS

2142
1024 X 4 BIT STATIC RAM

I

I

2142-2
200
525

Max. Access Time (ns)
Max. Power Dissipation (mw)

2142
450
525

2142-3
300
525

High Density 20 Pin Package
• Access
Selectlans From 200-450ns
• IdenticalTime
Cycle
and Access Times
• Low Operating Power
• .1mW/Bit Typical Dissipation
• Single +5V Supply

2142L2
200
370

2142L3
300
370

2142L
450
370

Clock or Timing Strobe Required
• No
Completely Static Memory
• Directly
TTL Compatible: All Inputs
• and Outputs
Common Data Input and Output Using
• Three-State
Outputs

The Intel@ 2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The 2142 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing
are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a Single +5V supply.
The 2142 is placed in a 20-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied, An Output Disable is included for direct control of the output buffers.
The 2142 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection
against contamination permitting the use of low cost plastic packaging.

PIN CONFIGURATION

LOGIC SYMBOL

BLOCK DIAGRAM
@)
A3

AS

Vee

AS

A,

A,

A4

AS

A,

A3

A,

A3

es,

00

A4

®
A4---

AO

I/O,
AS
AS

liD,

AS

A,

1/02

AS

A,

1103

A,

ES1

1/04

AS

CD

SELECT

MEMORY ARRAY
64 ROWS
64 COLUMNS

A,

@)
AS
1/03

1/04

®
"0,---

COLUMN I/O CIRCUITS

@
1102

WE

DND

ROW

@)

1/02

AO

®

@
If03

@
110 4

PIN NAMES
Ao-Ag

ADDRESS INPUTS

WE
CS;,CS2
I{O,- 1/04

WRITE ENABLE
CHIP SELECT

00
Vee
GND

OUTPUT DISABLE
POWER1+5V)

o

GROUND

OAT A INPUT/OUTPUT
00

B-144

"PIN NUMBERS

~vcc
~-o

GNO

2148
1024 X 4 BIT STATIC RAM
2148·3 2148 2148·6
Max. Access Time (ns)
Max. Active Current (rnA)
Max. Standby Current (rnA)

55
125

125

85
125

30

30

30

70

• Automatic Power· Down
• High Density 18·Pin Package
TTL Compatible
• Directly
- All Inputs and Outputs
• Common Data Input and Output
• Three·State Output

• HMOS Technology
Static Memory
• Completely
- No Clock or Timing Strobe
Required

• Equal Access and Cycle Times
• Single +5V Supply

The Intel'" 2148 is a 4096·bit static Random Access Memory organized as 1024 words by 4 bits using HMOS, a highperformance MOS technology. It uses a uniquely innovative design approach which provides the ease-of-use features
associated with non-clocked static memories and the reduced standby power dissipation associated with clocked static
memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold
times, nor reduced data rates due to cycle times that are longer than access times.

es controls the power·down

feature. In less than a cycle time after es goes high - disabling the 2148 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as es remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are
disabled.
The 2148 is assembled in an 18-pin package configured with the industry standard 1K x 4 pinout. It is directly TTL
compatible in all respects: inputs, outputs, and a single +5V supply. The data is read out nondestructively and has the
same polarity as the input data.
PIN CONFIGURATION
'6

Vee

'5

'7

A,

A,

'3

A9

'0

liD,

A,

1102

LOGIC SYMBOL

~vcc

- '0
-

A,
liD,

-

A,

-

A3
1I02r

-

"
-

1103

cs

1104

GND

WE

-

A6

-

A7

-

A,

~

Ag

A,
A,
1/0 411/01

es

WE

Y

Cs'
1/01 -110 4

Vee
GND

1102

1/03

PIN NAMES
WE

ROW

ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT/OUTPUT
POWER (+5V)
GROUND

SELECT

A7

11031--

Y

Ao-Ag

~GND

t-

A5

A,

BLOCK DIAGRAM

WE

H
L
L

X
L
H

MODE

1/0

NOT SELECTED HIGH·Z
WRITE
DIN
READ
DOUT

64 ROWS
64 COLUMNS

@
@

o '"

@
COLUMN 110 CIRCUITS

@
@

1104

TRUTH TABLE
CS

MEMORY ARRAY

POWER
STANDBY
ACTIVE
ACTIVE

B-145

PIN NUMBERS

Appendix B
Device Specifications

• EPROM Memories···

* For complete specifications refer to the

Intel MCS-85 User's Manual.
• *For complete specifications refer to the
Intel Peripheral Design Handbook.
** * For complete specifications refer to the 1979
Intel Component Data Catalog.

2716
16K (2K)( 8) UV ERASABLE PROM
• Fast Access Time
350 ns Max. 2716·1
390 ns Max. 2716·2
450 ns Max. 2716
- 650 ns Max. 2716·6

• Pin Compatible to Intel® 2732 EPROM
• Simple Programming Requirements
Single Location Programming
- Programs with One 50 ms Pulse

• Single + 5V Power Supply

• Inputs and Outputs TTL Compatible
during Read and Program

• Low Power Dissipation
525 mW Max. Active Power
- 132 mW Max. Standby Power

• Completely Static

The Intel® 2716 is a 16,384·bit ultraviolet erasable and electrically programmable read·only memory (EPROM). The 2716
operates from a single 5·volt power supply, has a static standby mode, and features fast single address location program·
mingo It makes designing with EPROMs faster, easier and more economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with the newer high performance
+5V microprocessors such as Intel's 8085 and 8086. The 2716 is also the first EPROM with a static standby mode which
reduces the power dissipation without increasing access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 132 mW, a 75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Program any location at any
time-either individually, sequentially or at random, with the 2716's single address location programming. Total programming
time for all 16,384 bits is only 100 seconds.
PIN CONFIGURATION

MODE SELECTION

2716

~

CE/PGM

DE

Vpp

Vee

(1S)

(20)

(21)

(24)

.,

OUTPUTS
(9-11,13·17)

MODE

'6'

Read

V'L

V'L

Standby

V'H

Don't Care

Program

Pulsed Vil to VIH

V'H

V'L

V'L

Program Verify

06
0,
GND

00

Program Inhibit

a'

12

V'L

., .,

'2'
'2'
'2'

V'H

.,
.,
.,
.,

BLOCK DIAGRAM

t Refer to 2732

UATAOUTPUTS

Vee

0---

data sheet for
specifications
PIN NAMES
ADDRESSES

AO-.AlO
CE/PGM

CHIP ENABLE/PROGRAM

DE

OUTPUT ENABLE

0-0

OUTPUTS

AO-Al0
ADDRESS
INPUTS

B-146

---00 01

Dour
High Z

D'N
DOUT

High Z

inter
2732
32K (4K x 8) UV ERASABLE PROM

•

Fast Access Time:
450 ns Max. 2732
- 550 ns Max. 2732·6

• Single +5V ± 5% Power Supply
Enable for MCS-85™ and
• Output
MCS-86™ Compatibility
Power Dissipation:
• Low
150mA Max. Active Current
30mA Max. Standby Current

• Pin Compatible to Intel® 2716 EPROM
• Completely Static
Programming Requirements
• Simple
Single Location Programming
-

Programs with One 50ms Pulse

Output for Direct Bus
• Three-State
Interface

The Intel® 2732 is a 32,768-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2732
operates from a single 5-volt power supply, has a standby mode, and features an output enable control. The total programming time for all bits is three and a half minutes. All these features make designing with the 2732 in microcomputer systems
faster, easier, and more economical.
An important 2732 feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OE
control eliminates bus contention in multiple bus microprocessor systems. Intel's Application Note AP-30 describes the
microprocessor system implementation of the OE and CE controls on Intel's 2716 and 2732 EPROMs. AP-30 is available
from Intel's Literature Department.
The 2732 has a standby mode which reduces the power dissipation without increasing access time. The maximum active
current is 150mA, while the maximum standby current is only 30mA, an 80% savings. The standby mode is achieved by
applying a TTL-high signal to the CE input.

PIN CONFIGURATION
A7

Vee

A.

As

As

Ag

A.

A11 .

A3

OElVpp

A,

A,.

A,

CE

Ao
a.

07

0,

a.
o.

0,

O.

GND

03

MODE SELECTION

~

CE

OUTPUTS

OE/Vpp
(20)

Vcc
(24)

VIL

V IL

+5

DOUT

VIH

Don't Care

+5

High Z

Program

VIL

Vpp

+5

DIN

Program Verify

VIL

V IL

+5

DOUT

Program Inhibit

VIH

Vpp

+5

High Z

MODE

(18)

Read

Standby

19·11,13·17)

BLOCK DIAGRAM
DATA OUTPUTS

Vee 0 - - -

00-07

GNOo--Vppo---

OE

PIN NAMES
Ao-A11

ADDRESSES

CE

CHIP ENABLE

~

OUTPUT ENABLE

° .0
0

7

CE-

AO-A11
ADDRESS
INPUTS

OUTPUTS

B-147

-=

OE AND

ce LOGIC
Y
DECODER

X
DECODER

1=

LLl tUl!
OUTPUT BUFFERS

I.P-

Y·GATING

·r.:.·

CELL MATRIX

F.
32,768·BIT

2758
8K (1K x 8) UV ERASABLE LOW POWER PROM

•
•

Single + 5V Power Supply

•

Fast Access Time: 450 ns Max. in
Active and Standby Power Modes

Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse

•

Inputs and Outputs TTL Compatible
during Read and Program

•

Low Power Dissipation
525 mW Max. Active Power
132 mW Max. Standby Power

•

Completely Static

•

Three·State Outputs for OR·Ties

The Intel® 2758 is a 8192-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2758
operates from a single 5-volt power supply, has a static standby mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical. The total programming time for all 8192 bits
is 50 seconds.
The 2758 has a static standby mode which reduces the power dissipation without increasing access time. The maximum
active power dissipation is 525 mW, while the maximum standby power dissipation is only 132 mW, a 75% savings. Powerdown is achieved by applying a TTL-high signal to the CE input.
A 2758 system may be designed for total upwards compatibility with Intel's 16K 2716 EPROM (see Applications Note
30). The 2758 maintains the simplest and fastest method yet devised for programming EPROMs - single pulse TTLlevel programming. There is no need for high voltage pulsing because all programming controls are handled by TTL
signals. Program any location at any time - either individually, sequentially, or at random, with the single address
location programming.

PIN CONFIGURATION
Vee

A,
A,

A,
A,

V"

DE

MODE SELECTION

~

CE/PGM

AR

BE

V,,

Vee

OUTPUTS

1181

1191

(201

(211

(241

(9-11.13-17)

MODE

Read

V,L

V,L

V,L

+5

+5

DOUT

Standby

V,H

V,L

Don't
Care

+5

+5

High Z

Program

05

Ao--- A 9

ADDRESSES
CHIP ENABLE/PROGRAM

OE

OUTPUT ENABLE

0
AR

0,

V,L

+5

D,N

V,L

V'H
V,L

+25

V,L

+25

+5

DOUT

Program Inhibit

V,L

V,L

V,H

+25

+5

High Z

BLOCK DIAGRAM

PIN NAMES

C"E/PGM

Pulsed V Il to V IH

Program Verify

OUTPUTS
SELECT REFERENCE

INPUT LEVEL

B-148

Appendix B
Device Specifications

•
• Development Tools

"For complete l?pecifications refer to the
Intel MCS-85 User's Manual.
"" For complete specifications refer to the
Intel Peripheral Design Handbook.
"""For complete specifications refer to the 1979
Intel Component Data Catalog.

inter

MODEL 230
INTELLEC SERIES II
MICROCOMPUTER DEVELOPMENT SYSTEM

Complete microcomputer development
center for Intel MCS·86, MCS·80, MCS·85
and MCS·48 microprocessor families
LSI electronics board with CPU, RAM,
ROM, I/O, and interrupt circuitry

Powerful ISIS·II Diskette Operating
System software with relocating
macroassembler, linker, and locater

1 million bytes (expandable to 2.5M
bytes) of diskette storage

64K bytes RAM memory

Self· test diagnostic capability
Eight·level nested, maskable priority
interrupt system

Supports PL/M and FORTRAN high level
languages

Standard MULTIBUS with multiprocessor
and DMA capability

Built·in interfaces for high speed paper
tape reader/punch, printer, and universal
PROM programmer

Compatible with standard Inteliec/iSBC
expansion modules

Integral CRT with detachable upper/
lower case typewriter·style full ASCII
keyboard

Software compatible with previous
Intellec systems

The Model 230 Intellec Series II Microcomputer Development System is a complete center for the development of
microcomputer-based products. It includes a CPU, 64K bytes of RAM, 4K bytes of ROM memory, a 2000-character CRT,
a detachable full ASCII keyboard, and dual double density diskette drives providing over 1 million bytes of on-line data
storage. Powerful ISIS-II Diskette Operating System software allows the Model 230 to be used quickly and efficiently
for assembling and/or compiling and debugging programs for Intel's MCS-S6, MCS-SO, MCS-S5, or MCS-4S microprocessor families without the need for handling paper tape. ISIS-II performs all file handling operations, leaving the user
free to concentrate on the details of his own application. When used in conjunction with an optional in-circuit
emulator (ICE) module, the Model 230 provides all the hardware and software development tools necessary for the
rapid development of a microcomputer-based product.

B-149

MODEL230
FUNCTIONAL DESCRIPTION

card communicates with the IPB over an 8-bit bidirectional data bus.

Hardware Components

Memory and Control Cards - In addition, 32K bytes of
RAM (bringing the total to 64K bytes) is located on a
separate card in the main cardcage. Fabricated from
Intel's 16K RAMs, the board also contains all necessary
address decoding and refresh logic. Two additional
boards in the cardcage are used to control the two
double-density floppy disk drives.

The Intellec Series II Model 230 is a packaged, highly
integrated microcomputer development system consisting of a CRT chassis with a 6-slot cardcage, power supply, fans, cables, and five printed circuit cards. A
separate, full ASCII keyboard is connected with a cable.
A second chassis contains two floppy disk drives capable of double-density operation along with a separate
power supply, fans, and cables for connection to the
main chassis. A block diagram of the Model 230 is
shown in Figure 1.
CPU Cards - The master CPU card contains its own
microprocessor, memory, 1/0, interrupt and bus interface circuitry fashioned from Intel's high technology LSI
components. Known as the integrated processor board
(IPB), it occupies the first slot in the cardcage. A second
slave CPU card is responsible for all remaining 1/0 control including the CRT and keyboard interface. This card,
mounted on the rear panel, also contains its own microprocessor, RAM and ROM memory, and 1/0 interface
logic, thus, in effect, creating a dual processor environment. Known as the 1/0 controller (IOC), the slave CPU

Expansion - Two remaining slots in the cardcage are
available for system expansion. Additional expansion of
4 slots can be achieved through the addition of an Intellec Series II expansion chassis.

System Components
The heart of the IPB is an Intel NMOS 8-bit microprocessor, the 8080A-2, running at 2.6 MHz. 32K bytes of RAM
memory are provided on the board using Intel 16K
RAMs. 4K of ROM is provided, preprogrammed with system bootstrap "self-test" diagnostics and the Intellec
Series II System Monitor. The eight-level vectored priority interrupt system allows interrupts to be individually
masked. Using Intel's versatile 8259A interrupt controller, the interrupt system may be user programmed to
respond to individual needs.

----------------~?

Figure 1. Intellec Series II Model 230 Microcomputer Development System Block Diagram

B-150

MODEL 230
Input/Output
IPB Serial Channels - The I/O subsystem in the Model
230 consists of two parts: the 10C card and two serial
channels on the IPB itself. Each serial channel is RS232
compatible and is capable of running asynchronously
from 110 to 9600 baud or synchronously from 150 to 56K
baud. Both may be connected to a user defined data set
or terminal. One channel contains current loop
adapters. Both channels are implemented using Intel's
8251A USART. They can be programmatically selected
to perform a variety of I/O functions. Baud rate selection
is accomplished programmatically through an Intel 8253
interval timer. The 8253 also serves as a real-time clock
for the entire system. I/O activity through both serial
channels is signaled to the system through a second
8259 interrupt controller, operating in a polled mode
nested to the primary 8259.

and universal PROM programmer. Communication
between the IPB and 10C is maintained over a separate
8-bit bidirectional data bus. Connectors for the four
devices named above, as well as the two serial channels, are mounted directly on the 10C itself.

Control
User control is maintained through a front panel, consisting of a power switch and indicator, reset/boot
switch, run/halt light, and eight interrupt switches and
indicators. The front panel circuit board is attached
directly to the IPB, allowing the eight interrupt switches
to connect to the primary 8259A, as well as to the Intellec
Series II bus.

Diskette System
The Intellec Series II double density diskette system
provides direct access bulk storage, intelligent controller, and two diskette drives. Each drive provides V2 million bytes of storage with a data transfer rate of 500,000
bits/second. The controller is implemented with Intel's
powerful Series 3000 Bipolar Microcomputer Set. The
controller provides an interface to the Intellec Series II
system bus, as well as supporting up to four diskette
drives. The diskette system records all data in soft sector format. The diskette system is capable of performing
seven different operations: recalibrate, seek, format
track, write data, write deleted data, read data, and verify
CRC.

IOC Interface - The remainder of system I/O activity
takes place in the 10C. The 10C provides interface for
the CRT, keyboard, and standard Intellec peripherals
including printer, high speed paper tape reader/punch,
and universal PROM programmer. The 10C contains its
own independent microprocessor, also an 8080A-2. The
CPU controls all I/O operations as well as supervising
communications with the IPB. 8K bytes of ROM contain
all I/O control firmware. 8K bytes of RAM are used for
CRT screen refresh storage. These do not occupy space
in Intellec Series II main memory since the 10C is a
totally independent microcomputer subsystem.

Integral CRT
Display - The CRT is a 12-inch raster scan type monitor
with a 50/60 Hz vertical scan rate and 15_5 kHz horizontal
scan rate. Controls are provided for brightness and contrast adjustments. The interface to the CRT is provided
through an Intel 8275 single chip programmable CRT
controller. The master processor on the IPB transfers a
character for display to the 10C, where it is stored in
RAM. The CRT controller reads a line at a time into its
line buffer through an Intel 8257 DMA controller and
then feeds one character at a time to the character generator to produce the video signal. Timing for the CRT
control is provided by an Intel 8253 interval timer. The
screen display is formatted as 25 rows of 80 characters.
The full set of ASCII characters are displayed, including
lower case alphas.
Keyboard - The keyboard interfaces directly to the 10C
processor via an 8-bit data bus. The keyboard contains
an Intel UPI-41 Universal Peripheral Interface, which
scans the keyboard, encodes the characters, and buffers the characters to provide N-key rollover. The keyboard itself is a high quality typewriter style keyboard
containing the full ASCII character set. An upper/lower
case switch allows the system to be used for document
preparation. Cursor control keys are also provided.

Peripheral Interface
A UPI-41 Universal Peripheral Interface on the 10C board
performs similar functions to the UPI-41 on the PIO
board in the Model 210. It provides interface for other
standard Intellec peripherals including a printer, high
speed paper tape reader, high speed paper tape punch,

Diskette Controller Boards - The diskette controller
consists of two boards, the channel board and the interface board. These two PC boards reside in the Intellec
Series II system chassis and constitute the diskette
control1er. The channel board receives, decodes and
responds to channel commands from the 8080A-2 CPU
in the Model 230. The interface board provides the
diskette controller with a means of communication with
the diskette drives and with the Intellec system bus. The
interface board validates data during reads using a
cyclic redundancy check (CRG) polynomial and generates CRC data during write operations. When the diskette controller requires access to Intellec system memory, the interface board requests and maintains DMA
master control of the system bus, and generates the
appropriate memory command. The interface board also
acknowledges I/O commands as required by the Intellec
bus. In addition to supporting a second set of double
density drives, the diskette controller may co-reside
with the Intel single density controller to allow up to 2.5
million bytes of on-line storage.

MULTIBUS Capability
All Intellec Series II models implement the industry
standard MULTIBUS. MULTIBUS enables several bus
masters, such as CPU and DMA devices, to share the
bus and memory by operating at different priority levels.
Resolution of bus exchanges is synchronized by a bus
clock signal derived independently from processor
clocks. Read/write transfers may take place at rates up
to 5 MHz. The bus structure is suitable for use with any
Intel microcomputer family.

B-151

MODEL230
SPECIFICATIONS

AC Requirements - 50/60 Hz, 115/230V AC

Host Processor (IPB)
RAM - 64K (system monitor occupies 62K through 64K)
ROM - 4K (2K in monitor, 2K in boot/diagnostic)

Environmental Characteristics

Diskette System Capacity (Basic Two Drives)

Operating Temperature - 0° to 35°C (95°F)

Unformatted
Per Disk: 6.2 megabits
Per Track: 82.0 kilobits
Formatted
Per Disk: 4.1 megabits
Per Track: 53.2 kilobits

Equipment Supplied
Model 230 chassis
Integrated processor board (IPB)
110 controller board (lOC)
32K RAM board
CRT and keyboard
Double density lIoppy disk controller (2 boards)
Qual drive lIoppy disk chassis and cables
2 floppy disk drives (512K byte capacity each)
ROM-resident system monitor

Diskette Performance
Diskette System Transfer Rate - 500 kilobits/sec
Diskette System Access Time
Track·to-Track: 10 ms
Head Settling Time: 10 ms
Average Random Positioning Time - 260 ms
Rotational Speed - 360 rpm
Average Rotational Latency - 83 ms
Recording Mode - M2FM

ISIS-II system diskette with MCS-80/MCS-85
macroassembler

Physical Characteristics
Width Height Depth Weight -

17.37 in. (44.12 cm)
15.81 in. (40.16 cm)
19.13 in. (48.59 cm)
73 Ib (33 kg)

Reference Manuals
9800558 - A Guide to Microcomputer Development
Systems (SUPPLIED)
9800550 - Intellec Series II Installation and Service
Guide (SUPPLIED)

Keyboard
Width - 17.37 in. (44.12 cm)
Height - 3.0 in. (7.62 cm)
Depth - 9.0 in. (22.86 cm)
Weight - 6 Ib (3 kg)

9800306 -

9800558 - Intellec Series II Hardware Reference Manual (SUPPLIED)

Dual Drive Chassis
Width - 16.88 in. (42.88 cm)
Height - 12.08 in. (30.68 cm)
Depth - 19.0 in. (48.26 cm)
Weight - 64 Ib (29 kg)

9800301 - 8080/8085 Assembly Language Programming Manual (SUPPLIED)
9800292 - ISIS-II 8080/8085 Assembler Operator's Manual (SUPPLIED)

Electrical Characteristics

9800605 - Intellec Series II Systems Monitor Source
Listing (SUPPLIED)

DC Power Supply
Volts
Supplied

+ 5±5%
+ 12±5%
-12±5%
-10±5%
+1S±S%

+24±5%

ISIS-II System User's Guide (SUPPLIED)

Amps
Supplied

Typical
System Requirements

30
2.5
0.3
1.5
1.5
1.7

14,25
0,2
0,05
15
1,3

9800554 - Intellec Series II Schematic Drawings
(SUPPLIED)
Reference manuals are shipped with each product only
if deSignated SUPPLIED (see above). Manuals may be
ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065 Bowers
Avenue, Santa Clara, California 95051 .

• Not available on bus.

ORDERING INFORMATION
Part Number Description
MDS-230

Intellec Series II Model 230
microcomputer development system
(110V/60 Hz)

MDS-231

Intellec Series II Model 230
microcomputer development system
(220V/50 Hz)

B-152

8086/8088 SOFTWARE DEVELOPMENT PACKAGE
PL/M·86 high level programming Ian·
guage
ASM86 macro assembler for 8086/8088
assembly language programming

CONV86 converter for conversion of
8080/8085 assembly language source
code to 8086/8088 assembly language·
source code
OH86 obJect·to·hexadecimal converter

LINK86 and LOC86 linkage and
relocation utilities

LlB86 library manager

The 808618088 software development package provides a set of software development tools for the 8086 and the 8088
microprocessors and ISsC 86112 single board computer. The package operates under the ISIS·II operating system on
Intellec Microcomputer Development Systems-Model 800 or Series II-thus minimizing requirements for additional
hardware or training for Intel Microcomputer Development System users.
The package permits 808018085 users to efficiently convert existing programs into 808618088 object code from either
8080/8085 assembly language source code or PLlM-80 source code.
For the new Intel Microcomputer Development System user, the package operating on an Intellec Model 230 Micro·
computer Development System provides total 8086/8088 software development capability.

B-153

8086/8088 SOFTWARE DEVELOPMENT PACKAGE

PL/M·86 HIGH LEVEL PROGRAMMING LANGUAGE
Sophisticated new complier design
allows user to achieve maximum benefits
of 808618088 capabilities
Language Is upward compatible from
PL/M·80, assuring MCS·80/8S deSign
portability
Supports 16·bit signed Integer and 32·bit
floating point arithmetic

Produces relocatable and linkable object
code
.
Supports full extended addressing
features of the 8086 and the 8088
microprocessors
Code optimization assures efficient code
generation and minimum application
memory utilization

Like its counterpart for MCS-80/85 program development, PLlM-86 Is an advanced structured high level programming
language. PLlM-86 is a new compiler created specifically for performing software development for the Intel 8086 and
8088 Microprocessors.
PLlM-86 has significant new capabilities over PLlM-80 that take advantage of the new facilities provided by the 8086
and the 8088 microprocessors, yet the PLlM-86 language remains upward compatible from PL/M-80.
With the exception of Interrupts, hardware flags, and time-critical code sequences, PLlM-80 programs may be recompiled under PLM-86 with little or no conversion required. PLlM-86, like PLlM-80, is easy to learn, facilitates rapid program development, and reduces program maintenance costs.
PLiM is a powerful, structured high level algorithml.c language In which program statements can naturally express the
program algorithm. This frees the programmer to concentrate on the system Implementation without concern for burdensome details of assembly language programming (such as register allocatlon,meanlngs of assembler mnemonics,
etc.).
The PL/M-86 compiler effiCiently converts free-form PLiM language statements into equivalent 8086/8088 machine instructions. Substantially fewer PLiM statements are necessary for a given application than if it were programmed at
the assembly language or machine code level.
Since PLiM programs are implementation problem oriented and more compact, use of PLiM results in a high degree of
engineering productivity during project development. This translates Into significant reductions in initial software
development and follow-on maintenance costs for the user.

FEATURES

• Relocatable and Linkable Object Code
-

Major features of the Intel PLlM-86 compiler and programming language include:
• Supports Five Data Types
-

Byte: 8-bit unsigned number
Word: 16-bit unsigned number
Integer: 16-bit signed number
Real: 32-bit floating pOint number
Pointer: 16-blt or 32-blt memory address indicator

• Block Structured Language
-

• Bullt·ln String Handling Facilities
-

-

Array: Indexed list of same type data elements
Structure: Named collection of same or different
type data elements
Combinations of Each: Arrays of structures or
structures of arrays

Operates on byte strings or word strings
Six Functions: MOVE, COMPARE, TRANSLATE,
SEARCH, SKIP, and SET

• Automatic Support for 8086 Extended Addressing
-

Permits use of structured programming techniques

• Two Data Structuring Facilities
-

Permits PLlM-86 programs to be developed and
debugged in small modules. These modules can
be easily linked with other PLlM-86 or ASM86 object modules and/or library routines to form a complete application system.

-

Three compiler options offer a separate model of
computation for programs up to 1-Megabyte In
size
Language transparency for extended addressing

• Support for ICE-86 Emulator and Symbolic Debugging
-

8-154

Debug option for Inclusion of symboi table in object modules for In-Circuit Emulation with symbolic debugging

8086/8088 SOFTWARE DEVELOPMENT PACKAGE
• Numerous Complier Options

for the development of 8086 and 8088 designs.
PLlM-86 and other elements of ISIS-II and the 80861
8088 Software Development Package are all that Is
needed for development of software for the 8086 and
the 8088 microcomputers and iSBC 86/12 single board
computer. This further reduces development time and
costs because expensive (and remote) time sharing of
large computers is not required. Present users of Intel
Intellec Development Systems can begin to develop
8086 and 8088 designs without expensive hardware
reinvestment or costly retraining.

A host of 26 compiler options including:
•
•
•
•
•

Conditional compilation
Included file or copy facility
Two levels of optimization
Intra-module and inter-module cross reference
Arbitrary placement of compiler and user files
on any available combination of disk drives

• Reentrant and Interrupt Procedures
-

May be specified as user options

BENEFITS
PLlM-86 is designed to be an efficient, cost-effective
solution to the special requirements of 8086/8088
Microcomputer Software Development, as illustrated by
the following benefits of PL/M-86 use:

• Reduced Learning Effort - PLlM-86 is easy to learn
and to use, even for the novice programmer.
• Earlier Project Completion - Critical projects are
completed much earlier than otherwise possible
because PLlM-86, a structured high-level language, increases programmer productivity.
• Lower Development Cost - Increases in programmer
productivity translate immediately into lower software development costs because less programming
resources are required for a given programmed function.
• Increased Reliability - PLlM-86 is designed to aid in
the development of reliable software (PLlM-86 programs are simple statements of the program
algorithm). This substantially reduces the risk of costly correction of errors in systems that have already
reached full production status, as the more simply
stated the program is, the more likely it is to perform
its intended function.

SAMPLE PROGRAM
STATISTICS: DO;
I*The procedure in this module computes the mean and
variance of an array of data, X, of length N + 1, according
to the method of Kahan and Parlett (University of California, Berkeley, Memo no. UCB/ERL M77/21.*1

STAT: PROCEDURE(X$PTR,N,MEAN$PTR,
VARIANCE$PTR) PUBLIC;
DECLARE
(X$PTR,MEAN$PTR,VARIANCE$PTR)
POINTER,X BASED X$PTR (1) REAL,
N INTEGER,
MEAN BASED MEAN$PTR REAL,
VARIANCE BASED VARIANCE$PTR REAL,
(M,Q,DIFF) REAL,
I INTEGER;
M=X(O);
M=O.O;
DO 1=1 TO N;
DIFF=X(I)- M;
M = M + DIFF/FLOAT(I + 1);
Q= Q+ DIFF*DIFF*FLOAT(I)/FLOAT(I + 1);

• Easler Enhancements and Maintenance - Programs
written in PLiM tend to be self~documenting, thus
easier to read and understand. This means it is easier
to enhance and maintain PLiM programs as the
system capabilities expand and future products are
developed.

END;
MEAN=M;
VARIANCE = Q/FLOAT(N);
END STAT;

• Simpler Project Development - The Intellec Development Systems offer a cost-effective hardware base

END STATISTICS;

B-155

8086/8088 SOFTWARE DEVELOPMENT PACKAGE

ASM86 MACRO ASSEMBLER
Powerful and flexible text macro facility
with three macro listing options to aid
debugging

Hlgh·level data structuring facilities
such as "STRUCTUREs" and
"RECORDs"

Highly mnemonic and compact
language, most mnemonics represent
several distinct machine instructions

Over 120 detailed and fully documented
error messages

"Strongly typed" assembler helps detect
errors at assembly time

Produces relocatable and linkable object
code

ASMas Is the "high-level" macro assembler for the 8086/8088 assembly language. ASM86 translates symbolic
8066/8088 assembly language mnemonics into 8086/8088 machine code.
AS Mas should be used where maximum code efficiency and hardware control is needed. The 808618088 assembly
language includes approximately 100 instruction mnemonics. From these few mnemonics the assembler can generate
over 3,800 d.lstinct machine Instructions. Therefore, the software development task is simplified, as th!! programmer
need know only 100 mnemonics to generate all possible 8086/8088 machine instructions. ASM86 will generate the
shortest machine Instruction possible given no forward referencing or given explicit information as to the
characteristics of forward referenced symbols.
ASM86 offers many features normally found only In hlgh·levellanguages. The 8086/8088 assembly language is strongly typed. The assembler performs extensive checks on the usage of variables and labels. The assembler uses the at·
tributes which are derived explicitly when a variable or label Is first defined, then makes sure that each use of the sym·
bolln later Instructions conforms to the usage defined for that symbol. This means that many programming errors will
be detected when the program is assembled, long before It is being debugged on hardware.

FEATURES
Major features of the Intel 8086/8088 assembler and
assembly language include: .
• Powerful and Flexible Text Macro Facility
- Macro calls may appear anywhere
- Allows user to define the syntax of each macro
Bu IIt-i n functions
• conditional assembly (IF-THEN-ELSE, WHILE)
• repetition (REPEAn
• string processing functions (MATCH)
• support of assembly time I/O to console (IN,
OUT)
- Three Macro Listing Options include a GEN mode
which provides a complete trace of all macro calls
and expansions

• Fully Supports 808618088 Addressing Modes

-

STRUCTURES: Defined to be a template and then
used to allocate storage. The familiar dot notation
may be used to form instruction addresses with
structure fields.
ARRAYS: Indexed list of same tyP!! data !!I!!ments.
RECORDS: Allows bit-templates to b!! defln!!d and
used as instruction operands andlor to allocate
storage.

Provides for compl!!x address expressions Involving base and indexing regist!!rs and (structure)
field offsets.

-

Powerful EQU facility allows complicated expressions to be named and the name can be used as a
synonym for the expression throughout the
mOdule.

• Powerful STRING MANIPULATION INSTRUCTIONS
-

• High-Level Data Structuring Capability
-

-

-

Permit direct transfers to or from memory or the
accumulator.
Can be prefixed with a repeat operator for
repetitive execution with a count·down and a condition test.

• Over 120 Detailed Error Me••age.
-

B-156

Appear both In regular list file and error print file.
User documentation fully explains the occurrence
of each error and sUggests a method to correct It.

SOS6/S0SS SOFTWARE DEVELOPMENT PACKAGE
• Generate. Relocatable and Linkable Object CodeFully Compatible with LINK88, LOC8S and LlB8S
-

Permits ASM86 programs to be developed and
debugged in small modules. These modules can
be easily linked with other ASM86 or PLlM-86 object modules andlor library routines to form a complete application system.

• Support for ICE-86 Emulation and Symbolic Debugging
-

Debug options for inclusion of symbol table in
object modules for In-Circuit Emulation with symbolic debugging.

BENEFITS
The 8086/8088 macro assembler allows the extensive
capabilities of the 8086/8088 to be fully exploited. In any
application, time and space critical routines can be
effectively written in ASM86. The 8086/8088 assembler
outputs relocatable and linkable object modules. These
object modules may be easily combined with object
modules written in PLlM-86-lntel's structured, highlevel programming language. ASM86 compliments
PLM-86 as the programmer may choose to write each
module In the language most appropriate to the task
and then combine the modules into the complete applications program using the 8086/8088 relocation and
linkage utilities.

CONV86
MCS·80/85 to MCS·86 ASSEMBLY LANGUAGE
CONVERTER UTILITY PROGRAM
Translates SOS01S0S5 Assembly
Language Source Code to SOS61S0SS
Assembly Language Source Code

Automatically generates proper ASM·S6
directives to set up a "virtual SOSO"
environment that Is compatible with
PLM·86

Provides a fast and accurate means to
convert SOS01S0S5 programs to the SOS6
and the SOSS, facilitating program
portability
In support of Intel's commitment to software portability, CONV86 Is offered as a tool to move 8080/8085 programs to
the 8086 and the 8088. A comprehensive manual, "MCS-86 Assembly Language Converter Operating Instructions for
ISIS-II Users" (9800642), covers the entire conversion process. Detailed methodology of the conversion process is fully
described therein.
CONV86 will accept as input an error-free 8080/8085 assembly-language source file and optional controls, and produce
as output, optional PRINT and OUTPUT files.
The PRINT file Is a formatted copy of the 8080/8085 source and the 8086/8088 source file with embedded caution
messages.
The OUTPUT file Is an 8086/8088 source file.
CONV86 issues a caution message when It detects a potential problem in the converted 8086/8088 code.
A transliteration of the 8080/8085 programs occurs, with each 8080/8085 construct mapped to Its exact 808618088
counterpart:
-Registers
-Condition flags
-Instructions
-Operands
-Assembler directives
-Assembler control lines
-Macros

B·IS7

8086/8088 SOFTWARE DEVELOPMENT PACKAGE
Because CONV86 is a transliteration process, there is the possibility of as much as a 15%-20% code expansion over
the 8080/8085 code. For compactness and efficiency it is recommended that critical portions of programs be re-coded
in 8086/8088 assembly language.
Also, as a consequence of the tranSliteration, some manual editing may be required for converting instruction sequences dependent on:
-instruction length, timing, or encoding
-interrupt processing
} mechanical editing procedures
-PLIM parameter passing conventions
for these are suggested in the converter manual.
The accompanying diagram illustrates the flow of the conversion process. Initially, the abstract program may be represented in 8080/8085 or 808618086 assembly language to execute on that respective target machine. The conversion
process is porting a source destined for thE! 8080/8085 to the 8086 or the 8088 via CONV86.

ABSTRACT PROGRAM

SOURCE CODE
IN 8080/8085
ASSEMBLY LANG

SOURCE CODE
IN 8086/8088
ASSEMBLY LANG

---ALGORITHM

ASSEMBLE

II

FOR
808018085

EXECUTE

ON
8080/8085

1-------1--------

CONva6

EOUIVALENT

FUNCTION

II

1-------1--------

PORTING 808018085 SOURCE CODe TO THE 808618088

B-158

.

ASSEMBLE
FOR
8086/8088

EXECUTe

ON
808618088

8086/8088 SOFTWARE DEVELOPMENT PACKAGE

LINK86
Automatic combination of separately
compiled or assembled 8086/8088
programs into a relocatable module
Automatic selection of required modules
from specified libraries to satisfy
symbolic references
Extensive debug symbol manipulation,
allowing line numbers, local symbols,
and public symbols to be purged and
listed selectively

Automatic generation of a summary map
giving results of the LlNK86 process
Abbreviated control syntax
Relocatable modules may be merged
into a single module suitable for
inclusion in a library
Supports "incremental" linking
Supports type checking of public and
external symbols

LlNK86 combines object modules specified in the LlNK86 input list into a single output mOdule. LlNK86 combines
segments from the input modules according to the order in which the mOdules are listed.
Support for incremental linking is provided since an output module produced by LlNK86 can be an input to another
link. At each stage in the incremental linking process, unneeded public symbols may be purged.
LlNK86 supports type checking of public and external symbols reporting an error if their types are not conSistent.
LlNK86 will link any valid set of input modules without any controls. However, controls are available to control the output of diagnostic information in the LlNK86 process and to control the content of the output module.
LlNK86 allows the user to create a large program as the combination of several smaller, separately compiled modules.
After development and debugging of these component modules the user can link them together, locate them using
LOC86, and enter final testing with much of the work accomplished.

LOC86
Automatic and independent relocation
of segments. Segments may be
relocated to best match users memory
configuration
Extensive debug symbol manipulation,
allowing line numbers, local symbols,
and public symbols to be purged and
listed selectively

Automatic generation of a summary map
giving starting address, segment
addresses and lengths, and debug
symbols and their addresses
Extensive capability to manipulate the
order and placement of segments in
8086/8088 memory
Abbreviated control syntax

Relocatabllity allows the programmer to code programs or sections of programs without having to know the final arrangement of the object code in memory.
LOC86 converts relative addresses in an input module to absolute addresses. LOC86 orders the segments in the input
module and assigns absolute addresses to the segments. The sequence in which the segments in the input module
are assigned absolute addresses is determined by their order in the input module and the controls supplied with the
command.
LOC86 will relocate any valid input module without any controls. However, controls are available to control the output
of diagnostic information in the LOC86 process, to control the content of the output module, or both.
The program you are developing will almost certainly use some mix of random access memory (RAM), read-only
memory (ROM), and/or programmable read-only memory (PROM). Therefore, the location of your program affects both
cost and performance in your application. The relocation feature allows you to develop your program on the Intellec
development system and then simply relocate the object code to suit your application.

B-159

8086/8088 SOFTWARE DEVELOPMENT PACKAGE

OH86
Converts an 8086/8088 absOlute object
module to symbolic hexadecimal format

Converts an absolute module to a more
readable format that can be displayed
on a CRT or printed for debugging

Facilitates preparing a file for later
loading by a symbolic hexadecimal
loader, such as the ISBC Monitor or
Universal PROM Mapper

The OH86 command converts an 8086/8088 absolute object module to the hexadecimal format. This conversion may
be necessary to format a module for later loading by a hexadecimal loader such as the iSSC 86/12 monitor or Universal
Prom Mapper. The conversion may also be made to put the module In a more readable format that can be displayed or
printed.
The module to be converted must be In absolute format; the output from LOC86 is in absolute format.

LlB86
LlB86 is a library manager program
which allows you to:
Create specially formatted files to
contain libraries of object modules
Maintain these libraries by adding or
deleting modules

Libraries can be used as input to LlNK86
which will automatically link modules
from the library that satisfy external
references in the modules being linked

Abbreviated control syntax

Print a listing of the modules and
public symbols in a library file

Libraries aid in the Job of building programs. The library manager program, L1S86, creates and maintains flies contain·
ing object modules. The operation of L1S86 is controlled by commands to indicate which operation L1S86 is to per·
form. The commands are:

CREATE - creates an empty library file
ADD - adds object modules to a library file
DELETE - deletes modules from a library file
LIST - lists the module directory of library files
EXIT - terminates the L1S86 program and returns control to ISIS·II

B-160

8086/8088 SOFTWARE DEVELOPMENT PACKAGE

ISIS·II
TEXT EDITOR

t-

PLlM·86
SOURCE

f--8- ~,~". "
COMPILER

OBJECT MODULE

I-

ISIS·II
TEXT EDITOR

ASM80/85
SOURCE

r--

ASM66
SOURCE

ASM66

RELOCATABLE
OBJECT MODULE

CONVa6

B-161

LINK86
AND
LOC86

I-

USER
SYSTEM

SDK·86

OH86

iSBC 86112

ICE·66

UPM

8086/8088 SOFTWARE DEVELOPMENT PACKAGE
SPECIFICATIONS
Operating Environment
Required Hardware

Documentation Package

InteHec Microcomputer Development System

PlIM-86 Programming Manual (9800466)
ISIS-II PlIM-86 Compiler Operator's Manual (9800478)
MCS-86 User's Manual (9800722)
MCS-86 Software Development Utilities Operating
Instructions for ISIS-II Users (9800639)
MCS-86 Macro Assembly Language Reference Manual
(9800640)
MCS-86 Macro Assembler Operating Instructions for
ISIS-II Users (9800641)
MCS-86 Assembly Language Converter Operating
Instructions for ISIS-II Users (9800642)
Universal PROM Programmer User's Manual
(9800819A)

- MDS-800, MDS-888
- Series II MDS-220 or MDS-230
64K Bytes of RAM Memory
Dual Diskette Drives
-

Single or Double· Density

System Console
-

CRT or Hardcopy Interactive Device

Optional Hardware
Universal PROM Programmer
Line Printer·
ICE-86™.
Required Software

Flexible Diskettes

ISIS-II Diskette Operating System
-

-

Single or Double· Density

·Recommended

ORDERING INFORMATION
Part Number Description
MDS-311

808618088 Software Development
Package

Also available in the following development support
packages:

Part Number Description
SP86A-KIT

SP86A Support Package (for Intellec
Model 800)
Includes ICE-86 In-Circuit Emulator
(MDS-86-ICE) and 808618088 Software
Development Package (MDS-311)

SP86B-KIT

SP86B Support Package (for Series II)
Includes ICE-86 In-Circuit Emulator
(MDS-86-ICE), 808618088 Software
Development Package (MDS-311),
and Series II Expansion Chassis
(MDS-201)

B-162

Single and Double· Oensity

inter
8089 ASSEMBLER SUPPORT PACKAGE
8089 1/0 processor program generation
on the Intellec Microcomputer
Development System.

Relocatable object module compatible
with the 8086 and 8088 Microprocessors.

Includes software development utilities
to facilitate 8089 design.
-LlNK86: Combines 8086 or 8088 object
modules with 8089 object
modules and resolves
external references.
-LOC86: Assigns absolute memory
addresses to 8089 object
modules.
-OH86:

Supports 8089-based addressing modes
with a structure facility that enables easy
access to based data.

Fully detailed set of error messages.

Converts 8086/8088/8089
object code to symbolic
hexadecimal format.

-UPM86: A PROM programming aid
which has been updated to
support PROM programming
for 8086, 8088 and 8089
applications.

The 8089 Assembler Support Package extends Intellec microcomputer development system support to the 8089 ilO
Processor. The assembler translates 8089 assembly language source instructions into appropriate machine operation codes. The 8089 Assembler Support Package allows the programmer to fully utilize the capabilities of the 80891/0
Processor.

B-163

8089 ASSEMBLER SUPPORT PACKAGE
A sample assembly listing is shown in table 1.

FUNCTIONAL DESCRIPTION
The 8089 Assembler Support Package contains the 8089
assembler (ASM89) as well as LlNK86 and LOC86relocation and linkage utilities, OH86-8086/8088/8089
object code to hexadecimal converter, and UPM86PROM programming software updated to program object
code in the 8086 formats. ASM89 translates symbolic
8089 assembly language instructions into the appropriate machine operation codes. The ability to refer to
program addresses with symbolic names eliminates the
errors of hand tranSI.ation and makes it easier to modify
programs when adding or deleting instructions.

18)1-11 " " II$UMllU VII IUIU.LV OF MODULE COHSOL
a.JEer MODULE "LUlD IN ,n,CONSOL o.~
USU'LU [nOICED IV UIIU CQNUl.$RC

..

1 CONSOLE

.....U,

U~$

,U

~IIO

e27f kUlllliIU (al!TROLLERS

5 CONTROL

11.2

lin

'11'
".7

,

; aus

?
8
,

PARU5'

os

I

,PARilMUn pon

"lIUII,
ST/IIT?5,

OS
OS

I
I

; sro,TuSlCa""IiINO PUT

POATS

"g

~u~~~::

13

STAT?"

PO:!S 3
os

I4CONTROj,.

....
.114

"

11311141
JUC U II

:::~

:::~:::~

1111
11101

ASM89 provides relocatable object module compatibility with the 8086 and 8088 microprocessors. This
object module compatibility, along with the 8086/8088
relocation and,linkage utilities, facilitates the designing
of the 8089 into an 8086 or 8088 system.

SEGMENT

IHITULI~E

3 ,

Ilut II U
IUt I I "

1111

IUt u

"It

1114t 16 31

;

ST~TUS!CO""/IIHD

NOVI

17
18
19
2B
21

110"1' IGAI iUPS..
MOYaIICA1PItiI1I75,4FH
MOVIIIGII] '1I/lA7S.I0311
MD'I8IIGIilIPAIIA75.'AII
"01181 I Glil I P~I!A75. I illi

;

MOYIIIC'" Sf1IITH,1
"OYIIIGAI STIIT7',UH

; INITULIZE U7t

."

..

I

U
24

."

PORT

ENDS

U

G/II.41II11

, SET POtT SASE RODItESS

INITIAliZE 8275

26 COHSOLE ENDS

OEFHVIILllf TYPE
..........
-_ ..

,

,
"·
·

ASM89 fully supports the based addressing modes of
the 8089. A structure facility in the assembler provides
easy access to based data. The structure facility allows
the user to define a template that enables accessing of
based data symbolically.

"

IIII
IIII

.1'1
IIU

1.. 1

a

I ..
II. .

m

m
m
'"
m
'"
'"

COHSOLf
COHUOL
HULLII
HULLII
PII.,.15

SUT7S

STnn

Table 1. Sample 8089 Assembly Lisling

Required Software

SPECIFICATIONS

ISIS-II Diskette Operating System

Operating Environment

-Single or Double" Density

Required Hardware

Intellec Microcomputer Development System
-MDS-8oo, MDS-888

Documentation Package

-Series II Models 220 or 230

8089 Assembler User's Guide (9800938)

64K Bytes of RAM Memory

8089 Assembler Pocket Reference (9800936)

Minimum One Diskette Drive

MCS-86 Software Development Utilities
Operating Instructions for ISIS-II User's (9800639)

-Single or Double" Density

MCS-86 Absolute Object File Formats (9800821)

System Console

Universal PROM Programmer User's Manual (9800819)

-CRT or Hardcopy Interactive Device
Optional Hardware

Flexible Diskettes

Universal PROM Programmer"
Line Printer"

-Single and Double" Density

ORDERING INFORMATION:
Part Number

Description

MDS-312

8089 Assembler Support Package

B-164

• Recommended

ICE·86lM
8086 IN·CIRCUIT EMULATOR
Hardware in-circuit emulation

2K bytes of high speed ICE-86 mapped
memory

Full symbolic debugging
Breakpoints to halt emulation on a wide
variety of conditions
Comprehensive trace of program execution, both conditional and unconditional

Software debugging with or without user
system
Handles full 1 megabyte addressability of
8086
Compound commands

Disassembly of trace or memory from
object code into assembler mnemonics

Command macros

lhe ICE-86 module provides In-Circuit Emulation for the 8086 microprocessor and the iSBC 86/12 Single Board Computer. It Includes three circuit boards which reside In Intelle~ Microcomputer Development Systems. A cable and
buffer box connect the Intellec system to the user system by replacing the user's 8086. Powerfullntellec debug functions are thus extended into the user system. Using the ICE-86 module, the designer can execute prototype software
in continuous or single-step mode and can substitute blocks of Intellec system memory for user equivalents. Breakpoints allow the user to stop emulation on user-specified conditions, and the trace capability gives a detailed history
of the program execution prior to the break. All user access to the prototype system software may be done symbolically
by referring to the source program variables and labels.

B-165

ICE-86™
INTEGRATED HARDWARE/SOFTWARE
DEVELOPMENT
The ICE-86 emulator allows hardware and software
development to proceed interactively. This is more effective than the traditional method of independent hardware and software development followed by system integration. With the ICE-86 module, prototype hardware
can be added to the system as it is designed. Software
and hardware testing occurs while the product is being
developed.
Conceptually, the ICE-86 emulator assists three stages
of development:
1. It can be operated without being connected to the
user's system, so ICE-86 debugging capabilities can
be used to facilitate program development before any
of the user's hardware is available.
2. Integration of software and hardware can begin when
any functional element of the user system hardware
is connected to the 8086 socket. Through ICE-86
mapping capabilities, Intellec memory, ICE memory,
or diskette memory can be substituted for missing
prototype memory. Time-critical program mOdules
are debugged before hardware implementation by using the 2K-bytes of high-speed ICE-resident memory.
As each section of the user's hardware is completed,
it is added to the prototype. Thus each section of the
hardware and software is "system" tested as it
becomes available.

3. When the user's prototype is complete, it is tested
with the final version of the user system software.
The ICE-86 module is then used for real time emulation of the 8086 to debug the system as a completed
unit.
Thus the ICE-86 module provides the user with the ability to debug a prototype or production system at any
stage in its development without introducing
extraneous hardware or software test tools.

SYMBOLIC DEBUGGING
Symbols and PLIM statement numbers may be
substituted for numeric values in any of the ICE-86 commands. This allows the user to make symbolic references to 110 ports, memory addresses, and data in the
user program. Thus the user need not remember the addresses of variables or program subroutines.
Symbols can be used to reference variables, procedures, program labels, and source statements. A variable can be displayed or changed by referring to it by
name rather than by its absolute location in memory.
Using symbols for statement labels, program labels, and
procedure names simplifies both tracing and breakpoint
setting. Disassembly of a section of code from either
trace or program memory into its assembly mnemonics
is readily accomplished.
Furthermore, each symbol may have associated with it
one of the data types BYTE, WORD, INTEGER,
SINTEGER (for short, 8-bit integer) or POINTER. Thus
the user need not remember the type of a source program variable when examining or modifying it. For
example, the command "!VAR" displays the value in
memory of variable VAR in a format appropriate to its
type, while the command "!VAR= !VAFf+ 1" increments
the value of the variable.
The user symbol table generated along with the object
file during a PUM-86 compilation or an ASM-86
assembly is loaded into memory along with the user program which is to be emulated. The user may add to this
symbol table any additional symbolic values for memory
addresses, constants, or variables that are found useful
during system debugging.
The ICE-86 module provides access through symbolic
definition to all of the 8086 registers and flags. The
READY, NMI, TEST, HOLD, RESET, INTR, and MN/MX
pins of the 8086 can also be read. Symbolic references
to key ICE-86 emulation information are also provided.

PLUG INTO
USER
8088 SOCKET

r------------- ------------------------ --,I

1.- ____ .,

I I
I I
I I

I
I
I
II

I

T·CABLE

I
I

I

I

IN~~~TEC

I

I

I

:

I
I
I
IL ____ .....lI

L ______________________________

Figure 1. ICE-86 Block Diagram

B-166

I
I
II

....!N~L~CJ

ICE-86™

A typical ICE-88 development configuration. It Is based on a Model 230 Development System, which also Includes a
Double Density Diskette Operating System and a Model 201 Expansion Chassis (which holds the ICE·88 emulator). The
ICE·88 module Is shown connected to a user prototype system, In this case an SDK·88.

MACROS AND COMPOUND COMMANDS

A macro Is a set of ICE-B6 commands which is given a
Single name. Thus, a sequence of commands which is
executed frequently may be invoked Simply by typing in
a single command. The user first defines the macro by
entering the entire sequence of commands which he
wants to execute. He then names the macro and stores
it for future use. He executes the macro by typing its
name and passing up to ten parameters to the commands in the macro. Macros may be saved on a disk file
for use in subsequent debugging sessions.
Compound commands provide conditional execution of
commands(lF), and execution of commands until a condition is met or until they have been executed a
specified number of times (COUNT, REPEAn.
Compound commands and macros may be nested any
number of times.

MEMORY MAPPING
Memory for the user system can be resident in the user
system or "borrowed" from the Intellec System through
ICE-86's mapping capability.
The ICE-86 emulator allows the memory which is addressed by the BOB6 to be mapped in 1K-byte blocks to:
1. Physical memory in the user's system,
2. Either of two 1K-byte blocks of ICE-B6 high speed
memory,
3. Intellec memory,
4. A random-access diskette file.
The user can also designate a block of memory as nonexistent. The ICE·B6 module issues an error message
when any such "guarded" memory is addressed by the
user program.

Description

Command

The ICE·86 module provides a programmable diagnostic
facility which allows the user to tailor its operation us·
ing macro commands and compound commands.

GO

Initializes emulation and allows the
user to spt;;cify the starting point
and breakpoints. Example:
GO FROM .START TILL .DELAY
EXECUTED
where START and DELAY are statement labels.

STEP

Allows the user to single-step
through the program.

Table 1. Summary of ICE·86 Emulation Commands

OPERATION MODES
The ICE-86 software is a RAM-based program that provides the user with easy-to-use commands for initiating
emulation, defining breakpoints, controlling trace data
collection, and displaying and controlling system
parameters. ICE-B6 commands are configured with a
broad range of modifiers which provide the user with
maximum flexibility in describing the operation to be
performed.

Emulation
Emulation commands to the ICE-B6 emulator control the
process of setting up, running and halting an emulation
of the user's 8OB6. Breakpoints and tracepoints enable
ICE·B6 to halt emulation and provide a detailed trace of
execution in any part of the user's program. A summary
of the emulation commands is shown in Table 1.
Breakpoints - The ICE-B6 module has two breakpoint
registers that allow the user to halt emulation when a
specified condition is met. The breakpoint registers may
be set up for execution or non-execution breaking. An
execution breakpoint consists of a Single address
which causes a break whenever the BOB6 executes from
its queue an instruction byte which was obtained from

B-167

ICE-86™
the address. A non-execution breakpoint causes an
emulation break when a specified condition other than
an instruction execution occurs. A non-execution breakpoint condition, using one or both breakpoint registers,
may be specified by anyone of or a combination of:

Memory/Register Commands
Display or change the contents of:
• Memory
• 8086 Registers
• 8086 Status flags
• 8086 Input pins
• 8086 I/O ports
• ICE·B6 Pseudo-Registers (e.g. emulation timer)

1. A set of address values. Break on a set of address
values has three valuable features:
a. Break on a single address.

Memory Mapping Commands

b. The ability to set any number of breakpoints within
a limited range (1024 bytes maximum) of memory.

Display, declare, set. or reset the ICE·86 memory mapping.
Symbol Manipulation Commands

c. The ability to break in an unlimited rar,ge. Execution is halted on any memory access to an address
greater than (or less than) any 20-bit breakpoint address.

Display any or all symbols, program modules, and program
line numbers and their aSSOCiated values (locations in
memory).
Set the domain (choose the particular program module) for
the line numbers.

2. A particular status of the 8086 bus (one or more of:
memory or 110 read or write, instruction fetch, halt, or
interrupt acknowledge).

Define new symbols as they are needed in debugging.
Remove any
statements.

3. A set of data values (features comparable to break on
a set of address values, explained in pOint one).

or

all

symbols,

modules,

and

program

Change the value of any symbol.
TYPE

4. A segment register (break occurs when the register is
used in an effective address calculation).

Assign or change the type of any symbol in the symbol table.
ASM

An external breakpoint match output for user access is
provided on the buffer box. This allows synchronization
of other test equipment when a break occurs.

Disassemble user program memory into ASM·86 Assembler
mnemonics.
PRINT

Tracepoints - The ICE-86 module has two tracepoint
registers which establish match conditions to conditionally start and stop trace collection. The trace information is gathered at least twice per bus cycle, first
when the address signals are valid and second when the
data signals are valid. If the 8086 execution queue is
otherwise active, additional frames of trace are col·
lected.

Display the specified portion of the trace memory.
LOAD
Fetch user symbol table and object code from the input file.
SAVE
Send user symbol table and object code to the output file.
LIST
Send a copy of all output (including prompts, input line
echos, and error messages) to the chosen output device (e.g.
disk, printer) as well as the console.

Each trace frame contains the 20 addressldata lines and
detailed information on the status of the 8086. The trace
memory can store 1,023 frames, or an average of about
300 bus cycles, providing ample data for determining
how the 8086 was reacting prior to emulation break. The
trace memory contains the last 1,023 frames of trace
data collected, even if this spans several separate
emulations. The user has the option of displaying each
frame of the trace data or displaying by instruction in ac·
tual ASM-86 Assembler mnemonics. Unless the user
chooses to disable trace, the trace information is
always available after an emulation.

EVALUATE
Display the value of an expression in binary, octal, decimal,
hexadecimal, and ASCII.
SUFFIX/BASE
Establish the default base for numeric values in input
text/output display (binary, octal, decimal, or hexadecimal).
CLOCK
Select the internal (ICE·a6 provided, for stand·alone mode
only) or an external (user·provided) system clock.
RWTIMEOUT
Allows the user to time out READ/WRITE command signals
based on the time taken by the 8086 to access Intellec
memory or diskette memory.

Interrogation and Utility
Interrogation and utility commands give the user con·
venient access to detailed information about the user
program and the state of the 8086 that is useful in
debugging hardware and software. Changes can be
made in both memory and the 8086 registers, flags, in·
put pins, and I/O ports. Commands are also provided for
various utility operations such as loading and saving
program files, defining symbols and macros, displaying
trace data, selling up the memory map, and returning
control to ISIS-II. A summary of the basic interrogation
and utility commands is shown in Table 2.

ENABLEIDISABLE ROY
Enable or disable logical AND of ICE·86 Ready with the user
Ready signal for accessing Intellec memory, tCE memory, or
diskette memory.

Table 2. Summary of Basic ICE·S6 Interrogation and
Utility Commands

B-168

ICE-86™
DIFFERENCES BETWEEN ICE·86
EMULATION AND THE 8086
MICROPROCESSOR

DC CHARACTERISTICS OF ICE·86
USER CABLE
1. Output Low Voltages [VoLlMax)= O.4y]
IOL(Mln)

The ICE·86 module emulates the actual operation of the
8086 microprocessor with the following exceptions:
o

The ICE·86 module will not respond to a user system
NMI or RESET signal when it Is out of emulation.

o Trap is ignored in single step mode and on the first in·

struction step of an emulation.
o

In the "minimum" mode, the user HOLD signal must
remain active until HLDA Is output by the ICE·86
emulator.

o

The RO/GT lines in the "maximum" configuration are
not supported.

8mA
(24 mA @ 0.5V)

A16/S3·A19/S7, SHE/57, RD,
LOCK, 050, 051, SO, 51, 52,
WR, M/iO, DT/R, DEN, ALE,
INTA

8mA
(16 mA @ 0.5V)

HLDA

The MIN/MAX line, which chooses the "minimum" or
"maximum" configuration of the 8086, must not
change dynamically in the user system.

o

ADO·AD15

MATCHO OR MATCH1 (on
buffer box)

7mA
16 mA

2. Output High Voltages [YOH (Min) = 2.4VJ
IOH(Mln)

The speed of run emulation by the ICE·86 module
depends on where the user has mapped his memory. As
the user prototype progresses to include memory,
emulation becomes real time.

ADO·AD15

-2mA

A16/S3·A19/S7, SHE/57, RD,
LOCK, 050, 051, SO, 51, 52,
WR, M/iO, DT/R, DEN, ALE,
INTA, HLDA

-1 mA

MATCHO OR MATCH1 (on
buffer box)

- 0.8 mA

3. Input Low Voltages [YIL(Max) = O.By]
IlL (Max)
Memory
Mapped To

ADO·AD15
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1I-'f to GND)

Estimated Speed

User System

100% of real time*, up to 4 MHz
clock

ICE

2 wait states per 8086·controlled
bus cycle

4. Input High Voltages [VIH(Mln)= 2.0VJ

Intellec

Approximately 0.02% of real time
at 4 MHz clock

Diskette

**

ADO·AD15
NMI, CLK
READY
INTR, HOLD, TEST, RESET
MN/MX (0.1I-'F to GND)

"100% of real time Is emulation at the user system clock rate with
no walt states.
""The emulation speed from diskette is comparable to Inteliec
memory, but emulation must walt when a new page is accessed
on the diskette.

-0.2 mA
-0.4 mA
-0.8 mA
-1.4mA
-3.3 mA
IIH(Max)
80l-'A
20,..A
40l-'A
-0.4 mA
-1.1 mA

5. RO/GTO, RO/GT1 are pulled up to + 5V through a 5.6K
ohm resistor. No current is taken from user circuit at
Vee pin.

B-169

ICE-86™
SPECIFICATIONS

Emulation Clock

ICE·86 Operating Environment

User system clock up to 4 MHz or 2 MHz ICE-86 internal
clock in stand-alone mode

Required Hardware
Intellec microcomputer development system with:
1. Three. adjacent slots for the ICE-86 module (Series II
requires Model 201 Expansion Chassis.)
2. 64K bytes of Intellec memory. If user prototype program memory is desired, additional memory above
the basic 64K is required.
System console
Intellec dis~ette operating system
ICE·86 module
Required Software
System monitor
ISIS·II, version 3.4 or subsequent
ICE·86 software

Equipment Supplied
Printed circuit boards (3)
Interface cable and emulation buffer module
Operator's manual
ICE-86 software, diskette-based

Physlc~1

Elec.trical Characteristics
DC Power
Vcc = +5V +5% -1%
Icc = 15A maximum; llA typical
Voo = + 12V ±5%
100 = 120 mA maximum; 80 mA typical
Vss = -10V ± 5% or -12V ± 5% (optional)
Iss = 15 mA maximum; 12 mA typical

Environmental Characteristics
Operating Temperature: O· to 40·C
Operating Humidity: Up to 95% relative humidity without condensation.

ORDERING INFORMATION
Part. Number

Description

MDS·86-ICE

8086 CPU in-circuit emulator

Characteristics

Printed Circuit Boards
Width: 12.00 in (30.48 cm)
Height: 6.75 in (17.15 cm)
Depth: 0.50 in (1.27 cm)
Packaged Weight: 9.00 Ib (4.10 kg)

B-170

iSBC 86/12A
SINGLE BOARD COMPUTER
808616 bit HMOS microprocessor
central processor unit
32K-bytes of dual-port read/write
memory expandable on-board to 64Kbytes with on-board refresh
Sockets for up to 16K-bytes of read only
memory expandable on-board to 32Kbytes
System memory expandable to
1 megabyte

Two programmable 16-bit BCD or binary
timers/event counters
9 levels of vectored interrupt control,
expandable to 65 levels
Auxiliary power bus and power fail
interrupt control logic for read/write
memory battery backup

24 programmable parallel 1/0 lines with
sockets for interchangeable line drivers
and terminators

MULTIBUS interface for multimaster
configurations and system expansion

Programmable synchronous 1
asynchronous RS232C compatible serial
interface with software selectable baud
rates

Compatible with iSBC 80 family single
board computers, memory, digital and
analog 110, and peripheral controller
boards

The iSBC 86/12A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems which take
full advantage of Intel's LSI technology to provide economical self-contained computer based solutions for OEM
applications. The iSBC 86/12A board is a complete computer system on a single 6.75 x 12.00-inch printed circuit
card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O ports and drivers, serial
communications interface, priority interrupt logic and programmable timers, all reside on the board. Full MUL TIBUS
interface logic is included to offer compatibility with the Intel OEM Microcomputer Systems family of Single Board
Computers, expansion memory options, digital and analog I/O expansion boards and peripheral controllers.

B-171

iSBC 86/12ATM
FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processor for the iSSC 86/12A board is Intel's
8086, a powerful 16-bit HMOS device. The 225 sq. mil
chip contains 29,000 transistors and has a clock rate of
5MHz. The architecture includes four (4) 16-bit byte
addressable data registers, two (2) 16-bit memory base
pointer registers and two (2) 16-bit index registers, all
accessed by a total of 24 operand addressing modes for
complex data handling and very flexible memory
addressing.
Instruction Set - The 8086 instruction repertoire includes
variable length instruction format (including double
operand instructions), 8-bit and 16-bit signed and
unsigned arithmetic operators for binary, SCD and
unpacked ASCII data, and iterative word and byte string
manipulation functions. The instruction set of the 8086 is
a superset of the 8080Al8085A family and with available
software tools, programs written for the 8080Al8085A can
be easily converted and run on the 8086 processor.
Architectural Features - A 6-byte instruction queue
provides pre-fetching of sequential instructions and can
reduce the 1.2!"sec minimum instruction cycle to 400 nsec
for queued instructions. The stack oriented architecture
facilitates nested subroutines and co-routines, reentrant
code and powerful interrupt handling. The memory

expansion capabilities offer a 1 megabyte addressing
range. The dynamic relocation scheme allows ease in
segmentation of pure procedure and data for efficient
memory utilization. Four segment registers (code, stack,
data, extra) contain program loaded offset values which
are used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K-bytes at a time and activation of a
specific register is controlled explicitly by program
control and is also selected implicitly by specific functions
and instructions.

Bus Structure
The iSSC 86/12A microcomputer has three buses: an
internal bus for communicating with on-board memory
and 110 options, the MUL TISUS system bus for referencing additional memory and 1/0 options, and the dual-port
bus which allows access to RAM from the on-board CPU
and the MUL TISUS system bus. Local (on-board)
accesses do not require MUL TISUS communication,
making the system bus available for use by other
MUL TISUS masters (i.e. DMA devices and other single
board computers transferring to additional system
memory). This feature allows true parallel processing in a
multiprocessor environment. In addition, the MUL TISUS
interface can be used for system expansion through the
use of other 8- and 16-bit iSSC computers, memory and
1/0 expansion boards.

Figure 1. ISBC 86/12A Single Board Computer Block Diagram

B-l72

iSBC

86/12ATM

RAM Capabilities
The iSBC 86/12A microcomputer contains 32K bytes of
dynamic read/write memory using 16K-bit 2117 RAMs. In
addition, the on-board RAM complement may be expanded to 64K bytes with the iSBC 300 32K-byte RAM
expansion module. Power for the on-board RAM and
refresh circuitry may be optionally provided on an auxiliary power bus, and memory protect logic is included
for RAM battery backup requirements. The iSBC 86/12A
board contains a dual port controller which allows
access to the on-board RAM (32K bytes or 64K bytes
when the iSBC 300 module is included with the iSBC
86/12A board) from the iSBC 86/12A CPU and from any
other MULTI BUS master via the system bus. The dual
port controller allows 8- and 16-bit accesses from the
MULTIBUS system bus, and the on-board CPU transfers
data to RAM over a 16-bit data path. Priorities have been
established such that memory refresh is guaranteed by
the on-board refresh logic and that the on-board CPU
has priority over MULTIBUS system bus requests for
access to RAM. The dual port controller includes independent addressing logic for RAM access from the
on-board CPU and from the MULTIBUS system bus. The
on-board CPU will always access RAM starting at location OOOOOH' Address jumpers allow on-board RAM to be
located starting on any 8K-byte boundary within a 1
megabyte address range for accesses from the MULTIBUS system bus. In conjunction with this feature, the
iSBC 86/12A microcomputer has the ability to protect
on-board memory from MULTIBUS access to any contiguous 8K-byte segments (or 16K-byte segments with
iSBC 300 module). These features allow multiprocessor
systems to establish local memory for each processor
and shared system (MULTIBUS) memory configurations
where the total system memory size (including local onboard memory) can exceed 1 megabyte without addressing conflicts.

electrically programmable ROMs (EPROMs); in 4K-byte
increments up to 8K bytes by using Intel 2716 EPROMs
or Intel 2316E masked ROMs; or in 8K-byte increments
up to 16K bytes by using Intel 2732 EPROMs or 2332A
ROMs. On-board EPROM/ROM is accessed via 16-bit
data paths. On-board EPROM/ROM capacity may be expanded to 32K bytes with the addition of the iSBC 340
16K-byte EPROM expansion module. It provides an additional four sockets for Intel 2732 EPROMs or Intel 2332A
ROMs. With user modification of the iSBC 86/12A's onboard memory and MULTIBUS address decode, Intel
2758 and 2716 EPROMs or 2316E ROMs may be optionally supported. System memory size is easily expanded
by the addition of MULTI BUS system bus compatible
memory boards available in the iSBC product family.

Parallel I/O Interface
The iSBC 86/12A single board computer contains 24
programmable parallel I/O lines implemented using the
Intel 8255A Programmable Peripheral Interface. The
system software is used to configure the I/O lines in any
combination of unidirectional input/output and bidirectional ports indicated in Table 1. Therefore, the I/O
interface may be customized to meet specific peripheral
requirements. In order to take full advantage of the large
number of possible I/O configurations, sockets are
provided for interchangeable I/O line drivers and
terminators. Hence, the flexibility of the I/O interface is
further enhanced by the capability of selecting the
appropriate combination of optional line drivers and
terminators to provide the required sink current, polarity,
and drive/termination characteristics for each application. The 24 programmable I/O lines and Signal ground
lines are brought out to a 50-pin edge connector that
mates with flat, woven, or round cable.

Serial I/O

EPROM/ROM Capabilities
Four sockets are provided for up to 16K-bytes of
nonvolatile read only memory on the iSBC 86/12A
board. EPROM/ROM may be added in 2K-byte increments up to a maximum of 4K-bytes by using Intel 2758

A programmable communications interface using the
Intel 8251A Universal Synchronous/Asynchronous
Receiver/Transmitter (USART) is contained on the iSBC
86/12A board. A software selectable baud rate generator
provides the USART with all common communication

Mode of Operation
Unidirectional
Port

Lines
(qty)

Output

Input

Bidirectional

Latched

Latched &
Strobed

Latched

Latched &
Strobed

Control

1

8

X

X

X

X

2

8

X

X

X

X

3

4

X

X

X1

4

X

X

X1

~O~~rt

X

of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a latched and strobed output
port or port 1 is used as a bidirectional port.

Table 1. Input/Output Port Modes of Operation

B-173

iSBC

86/12ATM

frequencies. The USART can be programmed by the
system software to select the desired asynchronous or
synchronous serial data transmission technique (including IBM Bi-Sync). The mode of operation (i.e., synchronous or asynchronous). data format, control character
format, parity, and baud rate are all under program
control. The 8251A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a direct
interface to RS232C compatible terminals, cassettes, and
asynchronous and synchronous modems. The RS232C
command lines, serial data lines, and signal ground line
are brought out to a 26 pin edge connector that mates with
RS232C compatible flat or round cable. The iSBC 530
Teletypewriter Adapter provides an optically isolated
interface for those systems requiring a 20 mA current
loop. The iSBC 530 unit may be used to interface the iSBC
86/12A board to teletypewriters or other 20 mA current
loop equipment.

Function

Programmable Timers
The iSBC 86/12A board provides three independent, fully
programmable 16-bit interval timers/event counters
utilizing the Intel 8253 Programmable Interval Timer.
Each counter is capable of operating in either BCD or
binary modes. Two of these timers/counters are available
to the systems designer to generate accurate time
intervals under software control. Routing for the outputs
and gate/trigger inputs of two of these counters is jumper
selectable. The outputs may be independently routed to
the 8259A Programmable Interrupt Controller and to the
I/O line drivers associated with the 8255A Programmable
Peripheral Interface, or may be routed as inputs to the
8255A chip. The gate/trigger inputs may be routed to I/O
terminators associated with the 8255A or as output
connections from the 8255A. The third interval timer in
the 8253 provides the programmable baud rate generator
for the iSBC 86/12A board RS232C USART serial port. In
utilizing the iSBC 86/12A board the systems deSigner
simply configures, via software, each timer independently
to meet system requirements. Whenever a given time
delay or count is needed, software commands to the
programmable timers/event counters select the desired
function. Seven functions are available, as shown in
Table 2. The contents of each counter may be read at any
time during system operation with simple read operations
for event counting applications, and special commands
are included so that the contents can be read "on the fly".

MUL TIBUS System Bus and
Multimaster Capabilities
The MUL TIBUS system bus features asynchronous data
transfers for the accommodation of devices with v.arious
transfer rates while maintaining maximum throughput.
Twenty address lines and sixteen separate data lines
eliminate the need for address/data multiplexing/demultiplexing logic used in other systems, and allow for data
transfer rates up to 5 megawords/sec. A failsafe timer is
included in the iSBC 86/12A board which can be used to
generate an interrupt if an addressed device does not
respond within 6 msec.

Operation

Interrupt on
terminal count

When terminal count is reached,
an interrupt request is generated.
This function is extremely useful
for generation of real-time clocks.

Programmable
one-shot

Output goes low upon receipt of
an external trigger edge or software command and returns high
when terminal count is reached.
This function is retriggerable.

Rate
generator

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one low
going pulse to the next is N times
the input clock period.

Square-wave
rate generator

Output will remain high until onehalf the count has been completed,
and go low for the other half of
the count.

Software
triggered
strobe

Output remains high until software loads count (N). N counts after count is loaded, output goes
low for one input clock period.

Hardware
triggered
strobe

Output goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.

Event counter

On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
may read the number of events
occurring after the counting "window" has been enabled or an
interrupt may be generated after N
events occur in the system.

Table 2_ Programmable Timer Functions

Multimaster Capabilities - The iSBC 86/12A board is a
full computer on a single board with resources capable of
supporting a great variety of OEM system requirements.
For those applications requiring additional processing
capacity and the benefits of multiprocessing (i.e., several
CPUs and/or controllers logically sharing system tasks
through communication over the system bus), the iSBC
86/12A board provides full MULTIBUS arbitration control
logic. This control logic allows up to three iSBC 86/12A
boards or other bus masters, including iSBC 80 family
MUL TIBUS compatible 8-bit single board computers, to
share the system bus in serial (daisy chain) priority
fashion and up to 16 masters to share the MUL TIBUS
system bus with the addition of an external priority
network. The MUL TIBUS arbitration logic operates
synchronously with a MUL TIBUS clock (provided by the
iSBC 86/12A board or optionally provided directly from
the MUL TIBUS) while data is transferred via a handshake
between the .master and slave modules. This allows
different speed controllers to share resources on the same
bus, and transfers via the bus proceed asynchronously.
Thus, transfer speed is dependent on transmitting and

B-174

iSBC

86/12ATM

receiving devices only. This desigf'l prevents slow master
modules from being handicapped in their attempts to gain
control of the bus, but does not restrict the speed at which
faster modules can transfer data via the same bus. The
most obvious applications for the master-slave capabilities of the bus are multiprocessor configurations, high
speed peripheral control, but are by no means limited to
these three.

Mode

Interrupt Capablity
The iSBC 86/12A board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-maskable
Interrupt) line which is directly tied to the 8086CPU. This
interrupt cannot be inhibited by software and is typically
used for signalling catastrophic events (i.e., power
failure). On servicing this interrupt, program control will
be implicitly transferred through location 00008 H . The
Intel 8259A Programmable Interrupt Controller (PIC)
provides vectoring for the next eight interrupt levels. As
shown in Table 3, a selection of four priority processing
modes is available to the systems designer for use in
designing request processing configurations to match
system requirements. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The PIC
accepts interrupt requests from the programmable
parallel and serial I/O interfaces, the programmable
timers, the system bus, or directly from peripheral
equipment. The PIC then determines which of the
incoming requests is of the highest priority, determines
whether this request is of higher priority than the level
currently being serviced, and, if appropriate, issues an
interrupt to the CPU. Any combination of interrupt levels
may be masked, via software, by storing a single byte in
the interrupt mask register of the PIC. The PIC generates
a unique memory address for each interrupt level. These
addresses are equally spaced at 4 byte intervals. This
32-byte block may begin at any 32-byte boundary in the
lowest 1K-bytes of memory: and contains unique
instruction pointers and code segment offset values (for
expanded memory operation) for each interrupt level.
After acknowledging an interrupt and obtaining a device
identifier byte from the 8259A PIC, the CPU will store its
status flags on the stack and execute an indirect CALL
instruction through the vector location (derived from the
device identifier) to the interrupt service routine. In
systems requiring additional interrupt levels, slave 8259A
PIC's may be interfaced via the MUL TIBUS system bus,
to generate additional vector addresses, yielding a total
of 65 unique interrupt levels.
Interrupt Request Generation - Interrupt requests may
originate from 17 sources. Two jumper selectable
interrupt requests can be automatically generated by the
programmable peripheral interface when a byte of

"Note: The Ii rst 32 vector locations are reserved by Intel
for dedicated vectors. Users who wish to maintain
compatibility with present and future Intel products
should, not use these locations for user-defined vector
addresses.

Operation

Fully nested

Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.

Auto-rotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next interrupt occurs.

Specific
priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence numerically on this assignment.

Polled

System software examines priority-encoded system interrupt status
via interrupt status register.

Table 3. Programmable Interrupt Modes

information is ready to be transferred to the CPU (i.e.,
input buffer is full) or a byte of information has been
transferred to a peripheral device (i.e., output buffer is
empty). Two jumper selectable interrupt requests can be
automatically generated by the USART when a character
is ready to be transferred to the CPU (i.e., receive channel
buffer is full, or a character is ready to be transmitted (i.e.,
transmit channel data buffer is empty). A jumper
selectable request can be generated by each of the
programmable timers. An additional interrupt request
line may be jumpered directly from the parallel I/O driver
terminator section. Eight prioritized interrupt request
lines allow the iSBC 86/12A board to recognize and
service interrupts originating from peripheral boards
interfaced via the MUL TIBUS system bus. The MUL TIBUS fail safe timer also can be selected as an interrupt
source.

Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow Signal from the
iSBC 635 and iSBC 640 Power Supply or equivalent.

Expansion Capabilities
Memory and I/O capacity may be expanded and
additional functions added using Intel MUL TlBUS
compatible expansion boards. Memory may be expanded
by adding user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/output
capacity may be increased by adding digital I/O and
analog I/O expansion boards. Mass storage capability
may be achieved by adding Single or double density
diskette controllers, or hard disk controllers. Modular
expandable backplanes and cardcages are available to
support multi board systems.
Note: Certain system restrictions may be incurred by the
inclusion of some of the iSBC 80 family options in an iSBC
86/12A system. Consult the Intel OEM Microcomputer
System Configuration Guide for specific data.

B-175

iSBC 86/12ATM

System Development Capabilities
The development cycle of iSBC 86/12A products can be
significantly reduced by using the Intellec® series
microcomputer development systems. The Assembler,
Locating Linker, Library Manager, Text Editor and system
monitor are all supported by the ISIS-II disk based
operating system. A minimum of 64K-bytes of RAM is
needed in the Intellec system to support program
development for the iSBC 86/12A board. To facilitate
conversion of 8080A/8085A assembly language programs
to un on the iSBC 86/12A board CONV-86 is available
under the ISIS-II operating system.
In-Circuit Emulator-ICE-86 in-circuit emulator provides
the necessary link between the software development
environment provided by the Intellec system and the
"target" iSBC 86/12A execution system. In addition to
providing the mechanism for loading executable code and
data into the iSBC 86/12A board, ICE-86 in-circuit
emulator provides a sophisticated command set to assist
in debugging software and final integration of the user

SPECIFICATIONS
Word Size
Instruction - 8, 16, 24, or 32 bits
Data - 8,16 bits

PL/M-86 - Intel's high level programming language,
PL/M-86, is also available as an Intellec Microcomputer
Development System option. PL/M-86 provides the
capability to program in a natural, algorithmic language
and eliminates the need to manage register usage or
allocate memory. PLlM-86 programs can be written in a
much shorter time than assembly language programs for a
given application. PLlM-86 includes byte and word,
integer, pointer and floating point (32-bit) data types and
also includes conditional compilation and macro features.

MULTIBUS Access - Jumper selectable for any 8K-byte
boundary, but not crossing a 128K-byte boundary. Access for 8K, 16K, 24K or 32K (16K, 32K, 48K, 64K with
iSBC 300 option) bytes may be selected for on-board
CPU use only.

1/0 Capacity

Cycle Time
Basic Instruction Cycle

hardware and software. ICE-86 in-circuit emulator
maximizes the use of available development resources by
allowing Intellec resident resources (e.g., memory and
peripherals) to be accessed by software running on the
target iSBC 86/12A system. In addition, software can be
executed without an iSBC 86/12A execution vehicle, in 2K
bytes of RAM resident in the ICE-86 system itself. Symbolic references to instruction and data locations can be
made through ICE-86 in-circuit emulator to allow the user
to reference memory locations with assigned names.

1.2l1 sec
400 nsec (assumes
instruction in the queue)

Note:
Basic instruction cycle is defined as the fastest instruction time (Le.,
two clock cycles)

Parallel - 24 programmable lines using one 8255A.
Serial - 1 programmable line USing one 8251A.

1/0 Addressing
On-Board Programmable 110
1
Address

Memory Capacity
On-Board Read Only Memory - 16K bytes (sockets
only); expandable to 32K bytes with iSBC 340 EPROMI
ROM expansion module.
On-Board RAM - 32K bytes; expandable to 64K bytes
with iSBC 300 RAM expansion module.
Off-Board ExpanSion - Up to 1 megabyte in user
specified combinations of RAM, ROM, and EPROM.
Note:
Read only memory may be added in 2K, 4K, or 8K·byte increments.

I

2

C81 CA

I

3

I Control

I I
CC

CE

Data

I

Control

08 or
DC

I

DA or
DE

Serial Communications Characteristics
Synchronous - 5-8 bit characters; internal or external character synchronization; automatic sync insertion.
Asynchronous - 5-8 bit characters; break character
generation; 1, 1V2, or 2 stop bits; false start bit
detection.
Baud Rates
Frequency (kHz)
(Software Selectable)

Memory Addressing
On-Board EPROM/ROM - FFOOO-FFFFFH (using 2758
EPROMs); FEOOO-FFFFFH (using 2716 EPROMs or 2316
ROMs); FCOOO-FFFFFH (using 2732 EPROMs or 2332A
ROMs); F8000-FFFFFH (with iSBC 340 EPROM option
and four additional 2732 EPROMs).

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

On-Board RAM - 32K bytes of dual port RAM. Optionally expandable to 64K bytes with iSBC 300 RAM option.
CPU Access - 32K bytes: 00000-07FFF H; 64K bytes:
OOOOO-OFFFF H·

USART

8255A

Port

Baud Rate (Hz)
Synchronous

38400
19200
9600
4800
2400
1760

Asynchronpus
+ 16

+ 64

9600
4800
2400
1200
600
300
150
110

2400
1200
600
300
150
75

-

Note:
Frequency selected by 110 write of appropriate 16-bit frequency factor
to baud rate register (8253 Timer 2).

B-176

iSBC 86/12ATM

Interrupts

Interfaces

Addresses for 8259A Registers (Hex notation I/O ad·
dress space)
CO or C4 Write: Initialization Command Word 1 (ICW1)
and Operation Control Words 2 and 3
(OCW2 and OCW3)
Read: Status and Poll Registers

MULTIBUS - All signals TTL compatible
Parallel I/O - All signals TTL compatible
Interrupt Requests - All TTL compatible
Timer - All signals TTL compatible
Serial I/O - RS232C compatible, data set configuration

C2 or C6

Write: ICW2, ICW3, ICW4, OCWI (Mask
Register)
Read: OCWI (Mask Register)

Note:
Several registers have the same physical address; sequence of access
and one data bit of control word determine which register will respond.

Interrupt Levels - 8086 CPU includes a non-maskable
Interrupt (NMI) and a maskable interrupt (INTR). NMI
interrupt is provided for catastrophic events such as
power failure. NMI vector address is 00008. INTR interrupt
is driven by on-board 8259A PIC, which provides 8-bit
identifier of interrupting device to CPU. CPU multiplies
identifier by four to derive vector address. Jumpers select
interrupts from 17 sources without necessity of external
hardware. PIC may be programmed to accommodate
edge-sensitive or level-sensitive inputs.

System Clock (8086 CPU)
5.00 MHz ± 0.1%

Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup of
read/write memory. Selection of this auxiliary RAM
power bus is made via jumpers on the board.

Connectors
Interface

Timers

Centers
(in.)

Mating Connectors

Bus

86

0.156

VIKING 3KH43/9AMK12

Parallel 110

50

0.1

3M 3415·000

Serial 110

26

0.1

3M 3462·000

Memory Protect

Register Addresses (Hex notation, I/O address space)

DO
D2
D4
D6

Pins
(qty)

An active low TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory
on the board. This input is provided for the protection
of RAM contents during system power down sequences.

Timer 0
Timer 1
Timer 2
Control register

Note:
Timer counts are loaded as two sequential output operations to same

Line Drivers and Terminators

address 85 given.

1/0 Drivers - The following line drivers are all compatible

Input Frequencies
Reference: 2.46 MHz ± 0.1 % (0.041I-'s period, nominal);
1.23 MHz ±0.1% (0.81 I-'s period, nominal); or 153.60
kHz ±0.1% (6.51I-'s period nominal).

with the 110 driver sockets on the iSBC 86/12A board.
Driver

Note:
Above frequencies are user selectable.

Event Rate: 2.46 MHz max
Output Frequencies/Timing Intervals
Single Timer/Counter
Function

Dual Timer/Counter
(Two Timers Cascaded)

Min

Max

Min

Max

Real-time
interrupt

1.63f1s

427.1 ms

3.26 S

466.50 min

Programmable

1.63 ~s

427.1 ms

3.26 S

466.50 min

Rate generator

2.342 Hz

613.5 kHz

0.000036 Hz

306.8 kHz

Square-wave

2.342 Hz

613.5 kHz

0.000036 Hz

306.8 kHz

1.63 flS

427.1 ms

3.26 S

466.50 min

1.63 fls

427.1 ms

3.26 S

466.50 min

-

2.46 MHz

-

-

one-shot

strobe
Hardware

Sink Current (mA)

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

Note:

I ;;; inverting; NI = non-inverting; DC

= open collector.

Port 1 of the 8255A has 20 mA totem·pole bidirectional
drivers and 1 kQterminators.
I/O Terminators -

220n/330n

rate generator
Software
triggered

Characteristic

7438
7437
7432
7426
7409
7408
7403
7400

220Q/330Qdivider or 1 kQ piJllup

(Isac 901 OPTION)

220Q
+5V--------~~__----~

1:

triggered

strobe
Event
counter

1K

n

(Isac 902 OPTION)
1 kQ

_______________

+5V--------~~

B-l77

iSBC 86/12ATM

Bus Drivers

Environmental Characteristics

Function

Data
Address
Commands

Characteristic

Sink Current (rnA)

Trl-state
Tri-state
Tri-state

50
50
32

Operating Temperature - O°C to 55°C
Relative Humidity - to 90% (without condensation)

Reference Manual

Physical Characteristics

9803074-01 - iSBC 896/12A Single Board Computer
Hardware Reference Manual (NOT SUPPLIED)

Width - 12.00 in. (30.48 cm)
Height - 6.75 in. (17.15 cm)
Depth - 0.70 in. (1.78 cm)
Weight - 19 oz. (539 gm)

Reference manuals are shipped with each product only if
designated SUPPLIED (see above). Manuals may be
ordered from any Intel Literature Department, 3065
Bowers Avenue, Santa Clara, California 95051.

Electrical Characteristics
DC Power Requirements
CUrrent Requirements
Configuration
Without

VCC = + 5V VOO = + 12V VBB = -5V VAA = - 12V
±S% (max) ±5% (max) ±S% (max) ±S% (max)
5.2A

350 mA

-

RAM Only3

390 mA

40 mA

1.0 mA

With
iSSC 530.

5.2A

450 mA

-

140 mA

With4K
EPROM5
(using 2758)

5.5A

350 mA

-

40 mA

With8K
ROM5
(using 2316E)

6.1A

350 mA

-

40 mA

With 8K
EPROM5
(using 2716)

5.5A

350 mA

-

40 rnA

With 16K
ROM5 (using
2732or2332A)

5.4A

350 mA

-

40 rnA

EPROM'

40 mA

-

Notes:
1. Does not include power for optional AOM/EPROM, 1/0 drivers, and
1/0 terminators.

2. Does not include power required for optional ROMIEPROM, 1/0
drivers and 1/0 terminators.

3. RAM chips powered via auxiliary power bus.
4. Does not include power for optional ROM/EPROM, 1/0 drivers, and

1/0 terminators. Power for iSBC 530 is supplied via serial port

connector.
S. Includes power required for four ROM/EPROM chips, and 110
terminators installed for 161/0 lines; all terminator inputs low.

ORDERING INFORMATION
Part Number
SBC 86/12A

Description
Single Board Computer
with 32K bytes RAM
Intel Corporation

3065 Bowers Avenue
Santa Clara, California 95051
Tel: (408) 987-8088""
TWX: 910·338·0026
TELEX: 34·6372

B-178

iSBC 957
INTELLEC ,'- iSBC 86/12A INTERFACE
AND E}{ECUTION PACKAGE
Establishes communication between the
iSBC 86/12A and the Intellec Develop·
ment Systems to aid in MCS·86™ soU·
ware development

Offers "Virtual Terminal" capability which
permits the Intellec console to access the
iSBC 86/12A Monitor

Allows full speed execution of MCS·86:rM
programs

Provides powerful console commands for
software debug

Includes EPROM resident system monitor
for iSBC 86/12A

Allows access to all iSBC 86/12A memory,
registers, flags and 110 ports

Allows Intellec ISIS·II files to be trans·
ferred between iSBC 86/12A and Intellec
Microcomputer Development System

Includes all necessary hardware, soft·
ware and documentation

The iSBC 957 Intellec-iSBC 86/12A Interface and Execution Pa,ckage contains all the necessary hardware, software
cables and documentation required to interface an iSBC 86/12A Single Board Computer to an Intellec Microcomputer
Development System for software development and full speed ex,ecution.

B·179

iSBC 957™
FUNCTIONAL DESCRIPTION

Software Capabilities
The software included in the iSBC 957 package consists
of. the iSBC 86/12A monitor residing on four Intel
EPROMs whkh are inserted into sockets on the iSBC
86/12A board. A diskette is also included which contains
the Intellec resident communications software that
links the iSBC 86/12A with the Intellec Microcomputer
Development System. The EPROM resident software
creates em execution environment in which object modules may be loaded into the iSBC 86/12A memory, executed 
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