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MCS™-S1 MACRO ASSEMBLER
USER'S GUIDE
Order Number: 9800937-02
--J1
L -_ _ _ _ _
Copyright © 1979, 1981 Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
. IL...-_ _ _ _ _--J
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers Avenue
Santa Clara, CA 95051
The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this material, including, but not limited
to, the implied warranties of merchantability and fitness for a particular purpose. Intel Corporation
assumes no responsibility for any errors that may appear in this document. Intel Corporation makes no
commitment to update nor to keep current the information contained in this document.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in
an Intel product. No other circuit patent licenses are implied.
Intel software products are copyrighted by and shall remain the property of Intel Corporation. Use,
duplication or disclosure is subject to restrictions stated in Intel's software license, or as defined in ASPR
7-104.9(a)(9).
No part of this document may be copied or reproduced in any form or bl/ any means without the prior
written consent of Intel Corporation.
The following are trademarks of Intel Corporation and its affiliates and may be used only to identify Intel
products:
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CREDIT
i
ICE
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im
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inlel
lntelevision
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Library Manager
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and the combination of ICE, iCS, iRMX, iSBC, iSBX, MCS, or RMX and a numerical suffix.
ii
!A450/981/7K DO !
REV.
-001
Change 1
-002
REVISION HISTORY
Original issue.
DATE
12179
Add Macro Processing Language facility and
correct minor errors.
3/80
Add several new directives and the concepts of
relocatable object code and intermodule linkage.
Correct errors.
9/81
:
iii
PREFACE
I
This manual describes how to program the MCS™-51 single-chip microcomputers in
assembly language. It also describes the operating instructions for the MCS-51
Macro Assembler.
The term "MCS-51" refers to an entire family of single-chip microcomputers, all of
which have the same basic processor design. They include:
• 8051-the 8x51 processor with 4K bytes ROM. It is manufactured by Intel with
ROM memory pre-programmed.
• 8031-the 8x51 processor with no ROM on-chip.
• 8751-the 8x51 processor with 4K bytes EPROM. The 8751 can be programmed
and erased many times by the user.
Throughout this manual when we wish to refer to a specific chip, but also point out
something that applies to the entire family, we speak of the 8051. For software purposes, these processors are equivalent.
This book is intended as a reference, but it contains some instructional material as
well. It is organized as follows:
• Chapter I-Introduction, describes assembly language programming and
provides an overview of the 8051 hardware.
• Chapter 2-0perands and Expressions, describes each operand class and
discusses absolute and relocatable expressions .
• ,- Chapter 3-Instruction Set, completely describes the operation of each
instruction in alphabetical order.
• Chapter 4-Directives, describes how to define symbols and how to use all
directives.
• Chapter 5-Macros, defines and describes the use of the Macro Processing
Language.
• Chapter 6-Assembler Operation and Control, describes how to invoke the
assembler and how to control assembler operation.
• Chapter 7-Assembler Output: Error Messages and Listing File Format,
describes' how to interpret error messages and the listing file.
Before you program one of the MCS-51 microcomputers, you should read the
MCS-5J User's Manual, Order Number 121517.
Related Literature
To help you use this manual, you should familiarize yourself with the following
manuals:
• MCS-5J Utilities User's Guide,Order Number 121737 (describes the RL51
Relocator and Linker process)
• ,MCS-5J Family of Single-Chip Microcomputers User's Manual, Order Number
121517
• ISIS-II User's Guide, Order Number 9800306
• MCS-5J Macro Assembly Language Pocket Reference, Order Number
9800935
v
•
•
•
•
vi
MCS-51 Assembler and Utilities Pocket Reference, Order Number 121817
ICE-51 In-Circuit Emulator Operating Instructions for ISIS-ll Users, Order
Number 9801004
Universal PROM Programmer User's ManuaJ~ Order Number 9800819
Universal PROM Programmer Reference Manual, Order Number 9800133
CONTENTS
CHAPTER 1
INTRODUCTION
PAGE
What is an Assembler? .......................
How to Develop a Program ...................
The Advantages of Modular Programming ....
Efficient Program Development .............
Multiple Use of Subprograms ...............
Ease of Debugging and Modifying ...........
MCS-51 Modular Program Development Process.
Segments, Modules, and Programs.. . ... .... .
Program Entry and Edit ....................
Assembly ................................
Object File .............................
Listing File .............................
Relocation and Linkage ....................
Conversion to Hexadecimal Format ..........
Keeping Track of Files ......•..............
Writing, Assembling, and Debugging an
MCS-51 Program .......................
Hardware Overview ...........................
Memory Addresses ..........................
Data Units .................................
Arithmetic and Logic Functions ...............
General-Purpose Registers ....................
TheStack ...•...............................
Symbolically Addressable Hardware Registers ...
Bit Addressing ..............................
The Program Status Word ....................
Timer and Counter ..........................
110 Ports ..................................
Serial 110 Port. . . . . . . . . . . . . . .. .. .. ..... .....
Interrupt Control ...........................
Reset ......................................
I-I
I-I
1-2
1-2
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-4
1-6
1-8
1-9
1-10
I-II
I-II
1-12
1-13
1-13
1-14
1-14
1-15
1-15
1-17
CHAPTER 2
OPERANDS AND EXPRESSIONS
Operands .................................... 2-1
Special Assembler Symbols ................... 2-2
Indirect Addressing .......................... 2-3
Immediate Data ............................. 2-3
Data Addressing ............................ 2-4
Bit Addressing .............................. 2-5
Code Addressing ............................ 2-7
Relative Jump (SJMP) and Conditional
Jumps ............................... 2-8
In Block Jumps and Calls (AJMP and
ACALL) ............................. 2-8
Long Jumps and Calls (LJMP and LCALL) ... 2-8
Generic Jump and Call (JMP and CALL) ..... 2-9
Assembly-Time Expression Evaluation ........... 2-9
Specifying Numbers ......................... 2-9
ASM51 Number Representation ............... 2-10
Character Strings in Expressions ............... 2-10
Use of Symbols ............................. 2-11
PAGE
Using Operators in Expressions ..•............. 2-13
Arithmetic Operators ...................... 2-13
Logical Operators .......... :.............. 2-13
Special Assembler Operators ................ 2-14
ReiationalOperators ....................... 2-14
Operator Precedence ......................... 2-15
Segment Typing in Expressions ................ 2-15
Relocatable Expression Evaluation ............. 2-16
Simple Relocatable Expressions ............. 2-16
General Relocatable Expressions ............. 2-16
CHAPTER 3
INSTRUCTION SET
Introduction.. ... . .. . . ... .. . .. . . . . . . .. .. . . . . .
3-1
Notes .. " ......... " .......................... 3-142
CHAPTER 4
ASSEMBLER DIRECTIVES
Introduction ."."..............................
The Location Counter .......................
Symbol Names .. "...........................
Statement Labels ............................
Symbol Definition .............................
SEGMENT Directive ........................
EQU Directive ... "..........................
SET Directive " ....... "......................
BIT Directive ...............................
DATA Directive ............................
XDATADirective ...........................
IDA T A Directixe ............................
CODE Directive .. ".........................
Storage Initialization and Reservation ............
DS Directive ................................
DBIT Directive ."...........................
DB Directive ...............................
DW Directive ... "...........................
Program Linkage .............................
PUBLIC Directive ...........................
EXTRN Directive ...........................
NAME Directive ............................
Assembler State Controls .......................
END Directive .............. "" ........... "."
ORG Directive" ... " .................. '" .....
Segment Selection Directives ....................
USING Directive ............................
4-1
4-2
4-2
4-2
4-3
4-3
4-4
4-5
4-5
4-6
4-6
4-6
4-7
4-7
4-7
4-7
4-8
4-8
4-9
4-9
4-9
4-10
4-10
4-10
4-11
4-11
4-12
CHAPTERS
THE MACRO PROCESSING LANGUAGE
Introduction ............... "..................
Macro Processor Overview .....................
Introduction to Creating and Calling Macros ......
Creating Simple Macros ......................
Macros with Parameters ......................
5-1
5-1
5-2
5-2
5-5
vii
CONTENTS (Cont'd.) I
PAGE
PAGE
LOCAL Symbols List ........................
The Macro Processor's Built-in Functions .........
Comment, Escape, Bracket and MET ACHAR
Built-in Functions .......................
Comment Function ........................
Escape Function ..........................
Bracket Function ..........................
METACHAR Function ....................
Numbers and Expressions in MPL .............
SET Macro ...............................
EVAL Macro .............................
Logical Expressions and String Comparisons
in MPL ................................
Control Flow Functions ......................
IF Function ..............................
WHILE Function .........................
REPEAT Function ........................
EXIT Function ...........................
String Manipulation Built-in Functions .........
LEN Function ............................
SUBSTR Function ........................
MATCH Function ........................
Console I/O-Built-in Functions ................
Advanced MPL Concepts ......................
Macro Delimiters ............................
Implied Blank Delimiters ...................
Identifier Delimiters .......................
Literal Delimiters .........................
Literal vs. Normal Mode .....................
Algorithm for Evaluating Macro Calls ........
5-6
5-7
5-8
5-8
5-9
5-9
5-10
5-10
5-11
5-11
5-12
5-13
5-13
5-14
5-15
5-15
5-16
5-16
5-16
5-17
5-18
5-18
5-18
5-19
5-19
5-20
5-21
5-22
6-1
6-2
CHAPTER 7
ASSEMBLER OUTPUT: ERROR
MESSAGES AND LISTING FILE FORMAT
Error Messages and Recovery ...................
Console Error Messages ......................
I/O Errors ...............................
ASM51 Internal Errors .....................
Invocation Line Errors .....................
viii
APPENDIX A
ASSEMBL Y LANGUAGE
BNFGRAMMAR
APPENDIXB
INSTRUCTION SET SUMMARY
APPENDIXC
ASSEMBLER DIRECTIVE SUMMARY
APPENDIXD
ASSEMBLER CONTROL SUMMARY
APPENDIXE
MPL BUILT-IN FUNCTIONS
APPENDIXF
RESERVED SYMBOLS
CHAPTER 6
ASSEMBLER OPERATION
AND CONTROLS
How to Invoke the MCS-51 Macro Assembler
Assembler Controls. . . . . . . . . .. . . . . . . . . . . . . . .. . .
Listing File Error Messages ...................
Source File Error Messages .................
Macro Error Messages .....................
Control Error Messages ....................
Special Assembler Error Messages ...........
Fatal Error Messages ......................
Assembler Listing File Format ...................
Listing File Heading .......................
Source Listing ............................
Format for Macros and INCLUDE Files ......
Symbol Table .............................
Listing File Trailer .........................
7-1
7-1
7-1
7-2
7-2
APPENDIXG
SAMPLE PROGRAM
APPENDIXH
REFERENCE TABLES
APPENDIXJ
ERROR MESSAGES
APPENDIXK
CHANGING ABSOLUTE PROGRAMS
TO RELOCA TABLE PROGRAMS
7-4
7-4
7-10
7-13
7-14
7-15
7-15
7-18
7-18
7-19
7-20
7-21
TABLESi
TABLE
I-I
1-2
1-3
2-1
2-2
2-3
2-4
2-5
TITLE
PAGE
Register Bank Selection .................
Symbolically Addressable Hardware
Registers for the 8051 .................
State of the 8051 after Power-up ..........
Special Assembler Symbols ..............
Predefined Bit Addresses for 8051 ........
Assembly Language Number
Representation ......................
Examples of Number Representation ......
Interpretations of Number
Representation ......................
1-11
1-12
1-17
2-2
2-7
2-9
2-9
2-10
TABLE
2-6
2-7
2-8
2-9
2-10
3-1
6-1
B-1
B-2
C-I
D-I
TITLE
PAGE
Predefined Data Addresses for 8051 ......
Arithmetic Assembly-Time Operators .....
Logical Assembly-Time Operators ........
Special Assembly-Time Operators ........
Relational Assembly-Time Operators .....
Abbreviations and Notations Used ........
Assembler Controls ....................
Instruction Set Summary ................
Instruction Opcodes in Hexadecimal ......
Assembler Directives ...................
Assembler Controls ....................
2-12
2-13
2-13
2-14
2-14
3-3
6-2
B-2
B-9
C-l
D-l
ILLUSTRATIONS
FIGURE
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
1-11
1-12
TITLE
PAGE
Assembler and Linker IRelocator
Outputs ............................
MCS-51 Program Development Process ...
Sample Program Listing ................
8051 Block Diagram ....................
MCS-51 Code Address Space and External
Data Address Space ..................
MCS-51 Data Address Space and Bit
Address Space .......................
MCS-51 Data Units' ....................
Bit Descriptions of Program Status
Word ..............................
Bit Descriptions of TCON ...............
Bit Descriptions for Port 3 ......... '......
Bit Descriptions for Serial Port Control ...
Bit Descriptions for Interrupt Enable and
Interrupt Priority ....................
FIGURE
2-1
1-3
1-5
1-5
1-7
1-8
1-9
1-10
1-13.
1-14
1-15
1-15
2-2a
2-2b
3-1
5-1
7-1.
7-2
7-3
7-4
7-5
0-1
K-l
TITLE
PAGE
Hardware Register Address Area
for 8051 ............................
Bit Addressable Bytes in RAM ...........
Bit Addressable Bytes in Hardware
Register Address Area for 8051. . . . . . . . ..
Format For Instruction Definitions .......
Macro Processor versus AssemblerTwo Different Views of a Source File. . ..
Example Listing File Format .............
Example Heading ......................
Example Source Listing .................
Examples of Macro Listing Modes ........
Example Symbol Table Listing ...........
Sample Relocatable Program ............
Sample Absolute Program ...............
2-4
2-6
2-6
3-2
5-1
7-15
7-18
7-18
7-19
7-21
0-1
K-I
1-16
ix
"
CHAPTER 1
INTRODUCTION
This manual describes the MCS™-Sl Macro Assembler and explains the process of
developing software in assembly language for the MCS-Sl family of processors. The
8051 is the primary processor described in this manual.
Assembly language programs translate directly into machine instructions which
instruct the processor as to what operation it should perform. Therefore the
assembly language programmer should be familiar with both the microcomputer
architecture and assembly language. This chapter presents an overview of the
MCS-Sl Macro Assembler and how it is used, as well as a brief description of the
8051 architecture and hardware features.
What is an Assembler?
An assembler is a software tool-a program-designed to simplify the task of
writing computer programs. It performs the clerical task of translating symbolic
code into executable object code. This object code may then be programmed into
one of the MCS-Sl processors and executed. If you have ever written a computer
program directly in machine-recognizable form, such as binary or hexadecimal
code, you will appreciate the advantages of programming in a symbolic assembly
language.
Assembly language operation codes (mnemonics) are easily remembered (MOY for
move instructions, ADD for addition). You can also symbolically express addresses
and values referenced in the operand field of instructions. Since you assign these
names, you can make them as meaningful as the mnemonics for the instructions.
For example, if your program must manipulate a date as data, you can assign it the
symbolic name DATE. If your program contains a set of instructions used. as a timing loop ( a set of instructions executed repeatedly until a specific amount of time
has passed), you can name the instruction group TIMER_LOOP.
The assembly program has three constituent parts:
Machine instructions
Assembler directives
Assembler controls
A machine instruction is a machine code that can be executed by the machine.
Detailed discussion of the machine instructions is presented in Chapter 3.
Assembler directives are used to define the program structure and symbols, and
generate non-executable code (data, messages, etc.). See Chapter 4 for details on all
of the assembler directives.
Assembler controls set the assembly modes and direct the assembly flow. Chapter 6
contains a comprehensive guide to all the assembler controls.
How to Develop a Program
ASMSI enables the user to program in a modular fashion. The following paragraphs
explain the basics of modular program development.
1-1
MCS-SI
Introduction
The Advantages of Modular Programming
Many programs are too long or complex to write as a single unit. Programming
becomes much simpler when the code is divided into small functional units. Modular
programs are usually easier to code, debug, and change than monolithic programs.
The modular approach to programming is similar to the design of hardware which
contains numerous circuits. The device or program is logically divided into "black
boxes" with specific inputs and outputs. Once the interfaces between the units have
been defined, detailed design of each unit can proceed separately.
Efficient Program Development
Programs can be developed more quickly with the modular approach since small
subprograms are easier to understand, design, and test than large programs. With
the module inputs and outputs defined, the programmer can supply the needed input
and verify the correctness of the module by examining the output. The separate
modules are then linked and located into one program module. Finally, the completed module is tested.
Multiple Use of Subprograms
Code written for one program is often useful in others. Modular programming
allows these sections to be saved for future use. Because the code is relocatable,
saved modules can be linked to any program which fulfills their input and output
requirements. With monolithic programming, such sections of code are buried
inside the program and are not so available for use by other programs.
Ease of Debugging and Modifying
Modular programs are generally easier to debug than monolithic programs. Because
of the well-defined module interfaces of the program, problems can be isolated to
specific modules. Once the faulty module has been identified, fixing the problem is
considerably simpler. When a program must be modified, modular programming
simplifies the job. You can link new or debugged modules to the existing program
with the confidence that the rest of the program will not be changed.
MCS-S1 Modular Program Development Process
This section is a brief discussion of the program development process with the
relocatable MCS-Sl assembler (ASMSl), Linker/Relocator (RLSl), and code converdon programs.
Segments, Modules, and Programs
In the initial design stages, the tasks to be performed by the program are defined,
and then partitioned into subprograms. Here are brief introductions to the kinds of
subprograms used with the MCS-Sl assembler and linker/relocator.
A segment is a block of code or data memory. A segment may be relocatable or
absolute. A relocatable segment has a name, type, and other attributes. Segments
with the same name, from different modules, are considered part of the same segment and are called "partial segments." Partial segments are combined into
segments by RLSI. An absolute segment has no name and cannot be combined with
other segments.
1-2
Introduction
MeS-51
A module contains one or more segments or partial segments. A module has a name
assigned by the user. The module definitions determine the scope of local symbols.
An object file contains one or more modules. You can add modules to a file by
simply appending another object file to that file (e.g., COPY file1,file2 TO file3).
A program consists of a single absolute module, merging all absolute and
relocatable segments from all input modules.
Program Entry and Edit
After the design is completed, the source code for each module is entered into disk
file using a text editor. When errors are detected in the development process, the text
editor may be used to make corrections in the source code.
Assembly
The assembler (ASM51) translates the source code into object code. The assembler
produces an object file (relocatable, when at least one input segment is relocatable,
or absolute), and a listing file showing the results of the assembly. (Figure I-I summarizes the assembly and the link and relocate outputs.) When the ASM51' invocation contains the DEBUG control, the object file also receives the symbol table and
other debug information for use in symbolic debugging of the program.
Object File. The object file contains machine language instructions and data that
can be loaded into memory for execution or interpretation. In addition, it contains
cpntrol information governing the loading process.
The assembler can produce object files in relocatable object code format. However,
if the module contains only absolute segments and no external references, the object
file resulting from assembly is absolute. It can be loaded without the need of the
RL51 pass.
RL51
LINK&
LOCATE
ASM51
ASSEMBLER
PROGRAM
Figure 1-1. Assembler and Linker/Relocator Outputs
937-1
1-3
MCS-Sl
Introduction
Listing File. The listing file provides a permanent record of both the source program and the object code. The assembler also provides diagnostic messages in the
listing file for syntax and other coding errors. For example. if you specify a 16-bit
value for an instruction that can only use an 8-bit value. the assembler tells you that
the value exceeds the permissible range. Chapter 7 describes the format of the listing
file. In addition. you can also request a symbol table to be awended to the listing.
The symbol table lists all the symbols and their attributes.
Relocation and Linkage
After assembly of all modules of the program, RL51 processes the object module
files. The RL51 program assigns absolute memory locations to all the relocatable
segments, combining segments with the same name and type. RL51 also resolves all
references between modules. RL51 outputs an absolute object module file with the
completed program, and a summary listing file showing the results of the
link/ relocate process.
Conversion to Hexadecimal Format
The absolute object code produced by RL51 can be programmed into memory and
executed by the target processor without further modification. However, certain
MCS-51 support products (such as SDK-51) require the hexadecimal object code
format. For use with these products, the absolute object file must be processed by
the OBJHEX code conversion program. Refer to the ISIS-II System User's Guide
(9800306).
Keeping Track of Files
It is convenient to use the extensions of filenames to indicate the stage in the process
represented by the contents of each file. Thus. source code files can use extensions
like .SRC or .A51 (indicating that the code is for input to ASM5I). Object code files
receive the extension .OBJ by default, or the user can specify another extension.
Executable files generally have no extension. Listing files can use .LST, the default
extension given by the assembler. RL51 uses .M51 for the default summary listing
file extension.
Use caution with the extension .TMP, as many ISIS-II utilities create temporary files
with this extension. These utilities will overwrite your file if it has the same name and
extension as the temporary files they create.
Writing, Assembling, and Debugging an MCS-51 Program
There are several steps necessary to incorporate an MCS-51 microcomputer in your
application. The flow chart in Figure 1-2 shows the steps involved in preparing the
code. If you are developing hardware for your application in addition to the software, consult the MCS-5J User's Manual.
Figure 1-3 shows an assembly listing of a sample program. The assembler was
invoked by:
-ASM51
:F1:DEMO.A51
ISIS-II MCS-51 MACRO ASSEMBLER, V2.0
ASSEMBLY COMPLETE, NO ERRORS FOUND
1-4
Introduction
MeS-51
TEXT
EDITOR
Rl51
LINKER I
LOCATOR
AS.. S1
ASSE .. BLER
FACTORY
"ASK
(FOR ABSOLUTE PROGRA .. S)
PRO"
OGRA....ER
ICE-51
IN-CIRCUIT
EMULATOR
LEGEND
D
O
INTEL DEVELOPMENT TOOLS
AND OTHER PRODUCTS
OBJHEX
CODE
CONVERSION
USER-CODED
SOFTWARE
Figure 1-2. MCS-Sl Program Development Process
MCS-51 MACRO
~SS=~SLE~
SDK-51
SYSTEM
DESIGN
KIT
937-2
a051-3ASED MONITOR
ISIS-II MC5-51 MACRO ASSEM8LER v2.0
OBJECT ~ODULE PLACED IN :Fl:DEM~.03J
ASSEMBLER INVdKED SY: ASMS1 :~1:D~~O.A51
LOC
OBJ
LINE
1
2
3
$TITLE(80S1-BASEO MONITOR)
iTh& m~in module of an 8051-based Monitor
4
iSymbol
PRDG_S
TASLE_S
CR
LF
5
6
0000
OOOA
SOURCE
7
8
9
0000 020000
F
10
11
12
13
d&finitions
SEGMENT CODE
iContains the e.ectutable program
SEGMENT CODE
iContains tables and other constant
EQu
13
iCarriage-Return character (ASCII)
EQU
10
iLine-Feed character (ASCII)
EXTRN
COOE(CONSOL_OUT, MONITOR)
iOefined else.here
iTh& main program
CSEG
AT a
JMP
START
;Skip interrupt vectors if any
14
RSEG
PROG_S
17
HOV
18
19
20
21
CALL
JMP
oPTR,IISIGNOIil
CONSOL_OUT
MONITOR
15
16
0000 900000
0003 120000
0006 020000
0000 1&
0001 38303531
0005 20424153
0009 45442040
0000 4F4E4954
0011 4F522C20
0015 56312E30
0019 00
001A OA
OOU
F
F
F
22
23
24
25
START:
iPrint signon .essage
;enter the .onitoring loop
RSEG
SIGNON: OS
TABLE_S
LEN,"8051-BASED MONITOR, Y1.0·, CR, LF
LEN
S-SIGNON-l
EQU
EIilO
Figure 1-3. Sample Program Listing
1-5
MeS-51
Introduction
MCS-51 MACRO A$SEM8LER
8051-8ASEO MONITOR
SYMBOL TABLE LISTING
T Y P E
N.A .. E
'ONSOl_OUT
CR •
•
•
•
LEN • • • •
LF • • • •
MONITOR.
PROG_S • •
SIGNON • •
START. • •
TABLE_S • •
C AOOR
NUMB
NUM8
NUMB
C AOOI!
C SEG
C AOOR
C AOOR
C SEG
V A L U E
A T T R I 8 UTE S
EXT
OOOOH
001AH
OOOAH
0009H
OOOOH
OOOOH
0018H
A
A
A
EXT
R
R
R!:LaUNIT
S!:G=TA8LE_S
SEG=PROG_S
REl=UNIT
REGISTER BANKCS) USED: 0, TARGET MACHINECS): 8051
ASSEMBLY COMPLETE, NO ERRORS FOUND
Figure 1-3. Sample Program Listing (Cont'd.)
Figure 1-3 shows the listing file of a simple module which is part of a larger program
not shown here. A larger example is provided in Appendix H.
The next step after the program is assembled by ASM51 is to combine all modules
into one program using RL51. RL51 produces a summary listing file consisting of a
memory map and a symbol table. (Refer to the MCS-5J Utilities User's Guide,
J21737.)
The next step in debugging your code is to program it into an EPROM 8751 and test
it in a prototype environment. (Further testing could be done via ICE-51.) To program your code into an 8751, you must have a UPP connected to your Intellec
system. For a complete description of how to use UPP and UPM, see Universal
PROM Programmer Reference Manual, order number 9800133 and Universal
PROM Programmer User's ManuaJ, order number 9800819.
Hardware Overview
The 8051 is a high-density microcomputer on a single chip. Its major features are:
• Resident 4K bytes of ROM or EPROM program memory (no program memory
resident on 8031), expandable to 64K bytes
• Resident 128 bytes of RAM memory, which includes four banks of 8
general-purpose registers and a stack for subroutine and interrupt routine calls
·64K bytes of external RAM address space
• 16-bit Program Counter giving direct access to 64K byte~ of memory
• 8-bit stack pointer that can be set to any address in on-chip RAM
• Two programmable 16-bit timers/counters
• Programmable full duplex serial 110 ports
• Four 8-bit bidirectional parallel I/O ports
• Timer and I/O interrupts with two levels of priority
• 111 instructions with 51 basic functions (including memory to memory move)
• Boolean functions with 128 software flags, numerous hardware flags, and 12
bit-operand instructions
1-6
MeS-51
Introduction
•
•
One microsecond instruction cycle time
Arithmetic and logic unit that includes add, subtract, multiply, and divide
arithmetic functions, as well as and, or, exclusive or, and complement logic
functions.
Figure 1-4 is a block diagram of the 8051 processor. It shows the data paths and
principal functional units accessible to the programmer.
ALU
PABl
TMOD
no
SERIAL
PORT
THO
IP
INTERRUPT
CONTROL
TLl
THl
TIMER
CONTROL
Figure 1-4. 8051 Block Diagram
937-3
1-7
Introduction
MeS-51
Memory Addresses
The 8051 has five address spaces:
• Code address space-64K, of which 4K are on-chip (except for the 8031 which
has no on-chip ROM).
• . Directly addressable internal data address space-128 bytes of RAM (Q - 127)
and 128-byte hardware register address space (128 - 255, only 20 addresSes are
used); accessible by direct addressing.
• Indirectly addressable internal data address space-128 bytes (0 - 127), all of
which is accessible by indirect addressing.
• External data address space-up to 64K of off-chip memory added by the user.
• Bit address space-shares locations accessible in the data address space;
accessible by direct addressing.
The code address space, internal data address space (including both the directly and
indirectly addressable space and the bit address space), and external data space correspond to three physically distinct memories, and are addressed by different
machine instructions. This is an important distinction that is a key to understanding
how to program the 8051.
When you specify in an operand to an instruction a symbol with the wrong attribute,
ASM-51 generates an error message to warn you of the inconsistency. Chapters 2
and 3 show what segment type attribute is expected in each instruction, and Chapter
4 describes how to define a symbol with any of the segment type attributes.
Figure 1-5 shows the code address space (usually ROM), and the external data
address space (usually RAM). Off-chip ROM and RAM can be tailored to use all or
part of the address space to better reflect the needs of your application. You can
access data in ROM and off-chip RAM with the MOVC and MOVX instructions
respectively.
...-----""65.535
OFF-CHIP
. . . - - - - -... 65.535
OFF-CHIP
ROM
RAM
4095
ON·CHIP
ROM
......_ _ _ _.... 0
_ _ _ _ _... 0
CODE
ADDRESS
SPACE
EXTERNAL DATA
ADDRESS SPACE
Figure 1-5. MeS-S 1 Code Address Space and
External Data Address Space
1-8
937--4
Introduction
MCS-Sl
To the programmer, there is no distinction between on-chip and off-chip code. The
16-bit program counter freely addresses on- and off-chip code memory with no
change in instruction fetch time.
Figure 1-6 shows the data address space containing the bit address space. The data
address space contains four banks of general-purpose registers in the low 32 bytes (0
- IFH). In addition to the 128 bytes of RAM, the 8051 's hardware registers are mapped to data addresses. The addresses from 128 to 255 are reserved for these registers,
but not all of those addresses have hardware registers mapped to them. These
reserved addresses are unusable.
When programming the 8051 and using indirect addressing, the user can access
on-chio RAM from 0 to 127.
DIRECT
ADDRESSING
INDIRECT
ADDRESSING
:
HARDWARE
REGISTER
MAPPING
I
I
I
I
255
NOT
AVAILABLE
FORTHE
8051
I
127
ON-CHIP RAM
,.
DIRECTLYIINDIRECTLY
ADDRESSABLE
ON-CHIP
RAM
47
RAM BIT ADDRESS
SPACE
31
4 REGISTER BANKS
8-. STACK DEFAULT
o
Figure 1-6. MCS-51 Data Address Space and
Bit Address Space
937-5
Data Units
The 8051 manipulates data in four basic units-bits, nibbles (4 bits), bytes, and
words (16 bits)_
The most common data unit used is a byte; all of the internal data paths are 8 bits
wide, and the code memory, the data memory, and the external data memory store
and return data in byte units. However, there are many instructions that test and
manipulate single bits_ Bits can be set, cleared, complemented, logically combined
with the carry flag, and tested for jumps. The nibble (BCD packed digit) is less
commonly used in the 8051, but BCD.arithmetic can be performed without conversion to binary representation.
1-9
MeS-51
Introduction
BIT
0
4-BIT NIBBLE
I
I
3
0
a-BIT BYTE
I
I
0
7
16-BIT WORDS
15
8 7
I
0
Figure 1-7. MCS-Sl Data Units
93Hl
Instructions that use 16-bit addresses deal with the Data Pointer (DPTR, a 16-bit
register) and the Program Counter (jumps and subroutine calls). However, with the
add with carry (ADDC) and subtract with borrow (SUBB) instructions, software
implementation of 16-bit arithmetic is relatively easy.
Arithmetic and Logic Functions
The arithmetic functions include:
• ADD-signed 2's complement addition
• ADDC-signed 2's complement addition with carry
• SUBB-signed 2's complement subtraction with borrow
• DA-adjust 2 packed BCD digits after addition
• MUL-unsigned integer multiplication
• DIV-unsigned integer division
• INC-signed 2's complement increment
• DEC-signed 2's complement decrement
The accumulator receives the result of ADD, ADDC, SUBB, and DA functions. The
accumulator receives partial result from MUL and DIV. DEC and INC can be
applied to all byte operands, including the accumulator.
The logical functions include:
• ANL-Iogical and on each bit between 2 bytes or 2 bits
• CPL-Iogicalcomplement of each bit within a byte or a single bit
• ORL-Iogicalor on each bit between 2 bytes or 2 bits
• XRL-Iogical exclusive or on each bit between 2 bytes
1-10
Introduction
MeS-51
The accumulator usually receives the result of the byte functions, and the carry flag
usually receives the result of the bit functions, but some instructions place the result
in a specified byte or bit in the data address space.
The instructions shown above are described in Chapter 3.
General-Purpose Registers
The 8051 has four banks of eight I-byte general-purpose registers. They are located
in the first 32 bytes of on-chip RAM (OOH - 1FH). You can access the registers of the
currently active bank through their special assembler symbols (RO, Rl, R2, R3, R4,
R5, R6, and R7). To change the active bank you modify the register bank select bits
(RSO and RSl) contained in the program status word (pSW, described in table 1-3).
Table 1-1 below shows the bank selected for all values' of RSO and RSI.
Table 1-1. Register Bank Selection
RS1
RSO
Bank
Memory Locations
0
0
1
1
0
1
0
1
0
1
2
00H-07H
OBH-OFH
10H-17H
1BH-1FH
3
Registers RO and Rl can be used for indirect addressing within the on-chip RAM.
Each register is capable of addressing 256 bytes but the indirect addressing is limited
by the physical range of the internal RAM. RO and Rl also can address the external
data space.
The Stack
The stack is located in on-chip RAM. It is a last-in-first-out storage mechanism used
to hold the Program Counter during interrupts and subroutine calls. You can also
use it to store and return data, especially the PSW, with the PO P and PUSH instructions. The Stack Pointer contains the address of the top of the stack.
The Stack Pointer (SP) is an 8-bit register that may contain any address in on-chip
RAM memory. However, on the 8051 it should never exceed 127. If it does, all data
pushed is lost. A pop, when the SP is greater than 127, returns invalid data.
The SP always contains the address of the last byte pushed on the stack. On powerup (Reset) it is set to 07H, so the first byte pushed on the stack after reset will be at
location 08H. This location is compatible with the 8048's stack. Most programs
developed for the 8051 will reset the bottom of the stack by changing the contents of
the SP before using the stack, because 08H-IFH is the area reserved for several of
the 8051 's general-purpose-regrster banks. The following instruction causes the next
byte pushed on the stack to be placed at location 100.
MOV SP,lt99
; Initialize stack to start at location 100
; The hardware increments the SP
; BEFORE a push
1-1 ]
MeS-51
Introduction
Symbolically Addressable Hardware Registers
Each programmable register is accessible through a numeric data address, but the
assembler supplies a predefined symbol that should be used instead of the register's
numeric address. Table 1-2 identifies each hardware register, its numeric address,
and its predefined symbol.
Table 1-2. Symbolically Addressable Hardware Registers for the 8051
Predefined
Symbol
Data
Address
ACC
EOH
Meaning
ACCUMULATOR (Data address of A)
B
FOH
MULTIPLICATION REGISTER
DPH
83H
DATA POINTER (high byte)
DPL
82H
DATA POINTER (low byte)
IE
A8H
INTERRUPT ENABLE
IP
B8H
INTERRUPT PRIORITY
PO
SOH
PORTO
P1
90H
PORT 1
P2
AOH
PORT2
P3
BOH
PORT3
PSW
DOH
PROGRAM STATUS WORD
SBUF
99H
SERIAL PORT BUFFER
SCON
98H
SERIAL PORT CONTROLLER
SP
81H
STACK POINTER
TCON
88H
TIMER CONTROL
THO
SCH
TIMER 0 (high byte)
TH1
8DH
TIMER 1 (high byte)
TLO
8AH
TIMER 0 (low byte)
TL1
8BH
TIMER 1 (low byte)
TMOD
89H
TIMER MODE
The predefined symbols given in table 1-2 stand for the on-chip data addresses of the
hardware registers. In many cases the only access to these registers is through these
data addresses. However, some of the registers have an identity both as a special
assembler symbol and as a data address symbol (e.g., both "ACC" and "A" stand
for the accumulator), but even though these symbols may be semantically the same,
they are syntactically different. For example,
ADDA,I27
is a valid instruction· to add 27 to the contents of the accumulator, but
ADD ACC,I27
is invalid and will cause an error, because there is no form of ADD taking a data
address as the destination (ACC specifies a data address). The differences become
even more subtle in some assembly instructions where both symbols are valid but
assemble into different machine instructions:
MOVA,127
MOVACC,I27
1-12
; assembles into a 2 byte instruction
; assembles into a 3 byte instruction
Introduction
MeS-51
Chapter 2 describes the syntax for all instruction operands, and Chapter 3 describes
the operands expected in each instruction.
Because the hardware registers are mapped to data addresses, there is no need for
special 110 or control instructions. For example,
MOV A,P2
moves a copy of the input data at Port 2 to the accumulator. To output a character
on the Serial 110 port (after preparing SCON), simply move the character into the
Serial port buffer (SBUF):
MOV SBUF,#'?'
Bit Addressing
Many of the hardware control registers are also bit addressable. The flags contained
in them can be accessed with a bit address as well as through the byte address shown
above. One way to do this is through the bit selector (". "). For example, to access
the 0 bit in the accumulator, you might specify ACC.O.
Bit addressing allows the same simplicity in testing and modifying control and status
flags as was shown above with addressable registers. For example, to start Timer 0
running, set the run flag to 1 via its bit address (SETB TCON.4).
Throughout the remainder of this chapter, several programmable. features, including predefined bit addresses of status and control flags, are discussed. To use these
features, you simply modify the corresponding address as if it were a RAM location.
The Program Status Word
The Program Status Word (PSW) contains several status bits that reflect the state of
the 8051. Figure 1-8 shows the predefined bit address symbol, the bit position, and
meaning of each bit in the PSW.
I I I I I I I
Cy
AC
FO
RSl
CARRY FLAG RECEIVES CARRY
POUT
SW.7=J
FROM BIT 7 OF ALU OPERANDS
PSW.6
AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FROM BIT 3 OF
ADDITION OPERANDS
PSW.S - - - - - '
GENERAL PURPOSE STATUS FLAG
PSW.4 - - - - - - '
REGISTER BANK SELECT BIT 1
RSO
ov
L
PSW.o
PARITY OF ACCUMULATOR SET
BY HARDWARE TO llF IT CONTAINS
AN ODD NUMBER OF l's; OTHERWISE
ITiS RESET TO 0
PSW.l
USER DEFINABLE FLAG
L...-_ _ _ PSW.2
OVERflOW FLAG SET BY
ARITHMETIC OPERATIONS
L..------PSW.3
REGISTER BANK SELECT BIT 0
Figure 1-8. Bit Descriptions of Program Status Word
937-7
1-13
MCS-Sl
Introduction
Timer and Counter
The 8051 has two independently programmable timers. They feature a 16-bit
counter and are controlled by 2 registers, timer mode (TMOD) and timer control
(TCON). Figure 1-9 shows the predefined bit address symbols, the positions and
meanings of the bits in TCON. (For a complete description of the timer see the
MCS-5J User's Manual.)
TCON.?
~~l
I TRl I TFO ITRO IIEl
IIT~l
II~
1IEl:=0 TCON.O
TIMER 1 OVERFLOW FLAG
INTERRUPT 0 TYPE CONTROL BIT
TCON.6
TIMER 1 RUN CONTROL BIT
TCON.l
INTERRUPTO EDGE FLAG
TCON.S
TIMER 0 OVERFLOW FLAG
TIMER 0 RUN
CONT~g~~i~
TCON.2
INTERRUPT 1 TYPE CONTROL BIT
-------'
'-------
itfT~~'~UPT 1 EDGE FLAG
Figure 1-9. Bit Descriptions of TeON
937·8
1/0 Ports
The 8051 has 4 8-bit lIO ports; each bit in the ports corresponds to a specific pin on
the chip. All four ports are buffered by a port latch, and they are addressable
through a data address (as a byte) or 8 bit addresses (as a set of bits). As noted
earlier, this removes the need for special lIO instructions. The numeric data address
and the predefined symbol for each port is shown below:
Port
Predefined
Symbol
Data
Address
0
1
PO
P1
SOH
90H
AOH
BOH
2
P2
3
P3
Port 0 and Port 2 are used for external program and external data addressing. Port 0
also receives the input data from off-chip addressing. If off-chip memory is not
implemented, then ports 0 and 2 are bidirectional I/O ports. Port 1 is a general pur~
pose bidirectional lIO port.
Port 3 contains the external interrupt pins, the external timer, the external data
memory read and write enables, and the serial I/O port transmit and receive pins.
The bits that correspond to these pins are individually addressable via predefined bit
address symbols. Figure 1-10 shows the meaning of each bit, its position in Port 3,
and its predefined bit address symbol.
If the external interrupts, external data addressing, and serial lIO features of the
8051 are not used, Port 3 can function as a bidirectional lIO port.
1-14
Introduction
MCS-Sl
P3'7~~D
jWRj Tlj TO
jINT1jIN~TOjTXL=DjR~P30
READ DATA FOR EXTERNAL MEMORY
SE'RIAL PORT RECEIVE PIN
P3.6
WRITE DATA FOR EXTERNAL MEMORY
P3.1
SERIAL PORT TRANSMIT PIN
P3.S
TIMER/COUNTER 1 EXTERNAL FLAG
P3.4 _ _ _ _ _- - l
P3.2
INTERRUPT 0 INPUT PIN
L..-_ _ _ _ _ P3.3
TIMER/COUNTER 0 EXTERNAL FLAG
INTERRUPT 1 INPUT PIN
Figure 1-10. Bit Descriptions for Port 3
937-9
Serial 1/0 Port
The serial 110 port permits 110 expansion using UART protocols. The serial 110
port is controlled by Serial Port Controller (SCON), a register that is both bit
addressable and byte addressable. Figure I-II shows the predefined bit address
symbols, positions and meanings of the bits in SCON. For complete details of Serial
110 port control see the MCS-5J User's Manual.
SCON'7~
~ISMOlsMt1ISM2IRENITB8IR~B81
~
TL
I = I SCON.O
SERIAL MODE CONTROL BIT 0 ~
RECEIVE INTERRUPT FLAG
SCON.S
SERIAL MODE CONTROL BIT 1
SCON.1
TRANSMIT INTERRUPT FLAG
SCON.S
SERIAL MODE CONTROL BIT 2
SCON.2
RECEIVE BIT 8
SCON.4
RECEIVER ENABLE
--------1
L..-_ _ _ _ _ SCON.3
TRANSMIT BIT 8
Figure I-II. Bit Descriptions for Serial Port Control
937-10
Interrupt Control
There are two registers that control timer and 110 interrupts and priorities. They are
IE (Interrupt Enable) and IP (Interrupt Priority). When the interrupt enable bit for
a device is 1, it can interrupt the processor. The 8051 does not respond to an
interrupt until the instruction being executed has been completed (this can be as long
as 4 cycles).
When it does respond, the 8051' s hardware disables interrupts of the same or lesser
priority and makes a subroutine call to the code location designated for the interrupting device. Typically, that location contains a jump to a longer service routine.
1-15
MCS-Sl
Introduction
The instruction RET! must be used to return from a service routine, in order to
re-enable interrupts. The reserved locations, the predefined labels, and the
associated interrupt devices are listed below. These labels may be used to aid the
placement of I/O routines in code memory.
Predefined
Label
Location
Interrupting Device
OOH
Power on Reset (First instruction executed on power up.)
External interrupt 0
TimerO
External interrupt 1
Timer1
Serial 1/0 port
RESET
EXTIO
TIMERO
EXTI1
TIMER1
SINT
03H
OBH
13H
1BH
23H
The 8051 has two levels of interrupt priority (0 and 1). Figure 1-12 shows the
predefined bit address symbol, the position and the device associated with each bit
contained in IE and IP. A level 1 priority device can interrupt a level 0 service
routine, but a level 0 interrupt will not affect a level 1 service routine. Interrupts on
the same level are disabled.
1111 I
PS
PT11 pX11 PTO
IP'7~-.J
I
Pc
L
~IP'O
RESERVED ~
PRIORITY OF EXTERNAL INTERRUPT 0
IP.6
RESERVED
IP.l
PRIORITY OF TIMER 0 INTERRUPT
IP.S
RESERVED
IP.2
PRIORITY OF EXTERNAL INTERRUPT 1
IP.4 _ _ _ _ _---1
PRIORITY OF SERIAL PORT INTERRUPT
L-_ _ _ _ _ IP.3
PRIORITY OF TIMER 1 INTERRUPT
Interrupt Priority
I II··· I I I I I I
tL L
EA
ES
Ell
EXl
ttl
IE.7.-1·
ENABLE ALL INTERRUPTS ~
IE.e - - - - '
I
RESERVED ~
ETO
I LL-.
IE.S
RESERVED
.
EXO
IE.O
ENABLE EXTERNAL INTERRUPT 0
1£.1
ENABLE TIMER o INTERRUPT
IE.2
ENABLE EXTERNAL INTERRUPT 1
IE.4 _ _ _ _ _---1
L------IE.3
ENABLE SERIAL PORT INTERRUPT
ENABLE TIMER 1 INTERRUPT
Interrupt Enable
937-11
Figure 1-12. Bit Descriptions for Interrupt Enable and Interrupt Priority
1-16
Introduction
MeS-51
Reset
On reset all of the registers in the 8051 assume an initial value. Table 1-3 shows these
initial values. This will always be the state of the chip when your code begins
execution. You can use these initial values or reinitialize them as necessary in your
program.
Table 1-3. State of the 8051 after Power-up
Register
Value
Accumulator
Multiplication Register
Data Pointer
Interrupt Enable
Interrupt Priority
PortO
Port 1
Port 2
Port 3
Program Counter
Program Status Word
Serial Port Control
Serial 110 Buffer
Stack Pointer
Timer Control
Timer Mode
Timer 0 Counter
Timer 1 Counter
OOH
OOH
OOOOH
OOH
OOH
OFFH
OFFH
OFFH
OFFH
OOOOH
OOH
OOH
undefined
07H
OOH
OOH
OOOOH
OOOOH
NOTE
The PC is always set to 0 on reset, thus the first instruction executed in a
program is at ROM location O. The contents of RAM memory is unpredictable at reset.
1-17
CHAPTER 2
OPERANDS AND EXPRESSIONS
This chapter discusses the operand types used by ASM51. It describes their use and
some of the ways you can specify them in your program. The latter part .of the
chapter deals with expressing numbers and using expressions.
There are two terms used throughout this chapter that require some definition:
Assembly-time expressions and RL-time expressions. Assembly-time expressions are
those expressions evaluated at assembly; they are absolute expressions. RL-time
expressions are those evaluated at the time of relocation; they are relocatable expressions that are made absolute by RL51.
Operands
The general form of all instruction lines is as follows:
[label:) Mnemonic [operand) [,operand) [,operand) [;comment)
The number of operands and the type of operands expected depend entirely on the
mnemonic. Operands serve to further define the operation implied by a mnemonic,
and they identify the parts of the machine affected by the instruction.
All operands fall into one of six classes:
• Special Assembler Symbols
- Indirect Addresses
• Immediate Data
• Data Addresses (on-chip)
• Bit Addresses
• Code Addresses
.
A special assembler symbol is a specific reserved word required as the operand in an
instruction.
Indirect addresses use the contents of a register to specify a data address.
The remaining operand types (immediate data, data addresses, bit addresses, and
code addresses) are numeric expressions. They may be specified symbolically, but
they must evaluate to a number. If the expression can be evaluated completely at
assembly time, it is called an absolute expression; if not, it is called a relocatable
expression. The range permitted for a numeric operand depends on the instruction
with which it is used. The operand can be made up of predefined or user-defined
symbols, numbers, and assembly-time operators.
As described in Chapter I, there are five address spaces on the 8051. The
corresponding segment type is given in parentheses.
• Directly addressable data address space (DATA)
• Bit address space (BIT)
• External data address space (XDAT A)
• Code address space (CODE)
• Indirectly addressable data space (IDATA)
2-1
MeS-51
Operands and Expressions
In some cases the same numeric value is a valid address for all five address spaces.
To help avoid logic errors in your program, ASMSI attaches a segment type and performs type checking for instruction operands (and arguments to assembler directives), that address these segments. For example, in jump instructions the assembler
checks that the operand, the target address, has a segment type CODE. Possible segment types are DATA, BIT, CODE, XDATA, and IDATA. Chapter 4 describes
how to define symbols with different segment types.
Special Assembler Symbols
The assembler reserves sevenil symbols to designate specific registers as operands. A
special assembler symbol is encoded in the opcode byte, as opposed to a data address
which is encoded in an operand byte. Table 2-1 lists these symbols and describes the
hardware register each represents.
If the definition of an instruction requires one of these symbols, only that special
symbol can be used. However, you can, with the SET and EQU directives, define
other symbols to stand for the accumulator (A) or the working registers (RO, ... R7).
Symbols so defined may not be forward referenced in an instruction operand. You
cannot use a special assembler symbol for any other purpose in an instruction
operand or directive argument. Several examples of instructions that use these symbols are shown below.
INC DPTR
;increment the entire 16-bit contents of the Data Pointer by 1
SETB C
;set the Carry flag to 1
JMP @A+ DPTR
;add the contents of the accumulator to the contents of the data
;pointer and jump to that address
In addition to these symbols, the assembler also recognizes the location counter symbol ($), described in Chapter 4, and the register address symbols ARO, ARI, ... ,
AR 7, described with the USING directive in Chapter 4. .
Table 2-1. Special Assembler Symbols
Meaning
Special Symbol
2-2
A
Accumulator
RO, R1, R2, R3,
R4,R5,R6,R7
Stands for the 8 general registers in the currently active bank (4
register banks available)
DPTR
Data pointer: a 16-bit register used for addressing in the code
address space and the external address space
PC
Program counter: a 16-bit register that contains the address of the
next Instruction to be executed
C
Carry flag receives ALU carry out and borrow from bit 7 of the
operands
AB
Accumulator/B register pair used in MUL and DIV instructions
Operands and Expressions
MeS-51
Indirect Addressing
An indirect address operand identifies a register that contains the address of a
memory location to be used in the operation. The actual location affected will
depend on the contents of the register when the instruction is executed. In most
instructions indirect addresses affect on-chip RAM. However, the MOVe and
MOVX instructions use an indirect address operand to address code memory and
external data memory, respectively.
In on-chip indirect addressing (the IDAT A space), either register 0 or register I of
the active register bank can be specified as an indirect address operand. The commercial at sign (@) followed by the register's special symbol (RO or RI), or a symbol
defined to stand for the register's special symbol, indicates indirect addressing. On
the 8051 the address contained in the specified indirect address registers must be
between 0 and 127 (since you cannot access hardware registers through indirect
addressing.) If an indirect address register contains a value greater than 127 when it
is used for on-chip addressing, the program continues with no indication of the
error. If it is a source operand, a byte containing undefined data is returned. If it is a
destination operand, the data is lost.
The following examples show several uses of indirect addressing.
ADDA,@R1
;add the contents of the on-Chip RAM location addressed by
;register 1 to the accumulator
INC@RO
;increment the contents of the on-chip RAM location addressed
;by register 0
MOVX@DPTR,A -
;move the contents of the accumulator to the off-chip memory
;Iocation addressed by the data pOinter
Immediate Data
An immediate data operand is a numeric expression that, when assembled, is
encoded as part of the machine instruction. The pound sign (#) immediately before
the expression indicates that it is an immediate data operand. The numeric expression must be a valid assembly-time expression or RL-time expression.
The assembler represents aU" numeric expressions in 16 bits, and converts to the
appropriate form for instruction encoding.
Most instructions require the value of the immediate data to fit into a byte. The low
order byte of the assembler's 16-bit internal representation is used. The assembler
permits a numeric expression range of values from -256 to +255. These values all
have a homogeneous high order byte (i.e., all ones or all zeroes) when represented in
16 bits. The low order byte of the assembler's 16-bit internal representation is used.
Note that since only the lower order byte is taken as the result of the expression, the
sign information, i.e., the higher order byte, is lost.
The immediate data operands that accept a 16-bit value can use any value representable by the assembler. Immediate data operands do not require any specific segment
type. XDAT A and IDAT A type operands can be specified only as immediate
operands; i.e., you have to load these addresses first into a register and then access
them.
2-3
MeS-51
Operands and Expressions
The following examples show several ways of specifying the immediate data
operand.
MOVA,.OEOH
;place the hex constant EO in the accumulator
MOV DPTR,tlOA14FH
;this is the only instruction that uses a 16-bit immediate data
;operand
ANLA,'128
;mask out all but the high order bit of the accumulator
;(128-base 10) = 10000000 (base 2)
MOV RO,IIDATA_SYM
;Load RO with IDATA symbol for later access
Data Addressing
The data address operand is a numeric expression that evaluates to one of the first
128 on-chip byte addresses or one of the hardware register addresses. The low-order
byte of the assembler's 16-bit internal representation is used. This permits a range
from -256 to +255. Note that since only the lower order byte is taken as the result of
the expression, the sign information (i.e., the higher order byte) is lost. Instructions
that use the data address operand require that the symbol or expression specified be
either of segment type DATA or be a typeless number. (Symbols are discussed below
under expression evaluation.)
The direct data addresses from 0 to 127 access the 8051 's on-chip RAM space, while
the addresses from 128 to 255 access the hardware registers. Not air of the addresses
in the hardware register space are defined. The illustration below (figure 2-1) shows
the meaningful addresses and their predefined data address names.
If you read from a reserved address, undefined data will be returned. If you write to
a reserved address, the data will be lost. Using these pecularities in your program
may result .in incompatibility with future versions of the chip. Note that using
indirect addressing for locations above 127 will access lDAT A space rather than
hardware register space.
HIGH
ORDER
DIGIT
OF
ADDRESS
C
......
.....+,.,........,.+'"'''''+~..,...+''''"'!~+-"""+....,.+--+
B
A
o
2
456789ABCDEF
LOW ORDER DIGIT OF ADDRESS
Figure 2-1. Hardware Register Address Area for 80S 1
2-4
937-12
Operands and Expressions
MCS-Sl
The following examples show several ways of specifying data addresses.
MOV P1,A
;move the contents of the accumulator to the predefined data address 90
;(base 16) port 1
ORL A,20*5
;Iogical OR of accumulator with location 100 (base 10) uses an
;assembly-time operator multiply
INC COUNT
;increment the location identified by the symbol COUNT
INC32
;increment location 32(base 10) in memory
Bit Addressing
A bit address represents a bit-addressable location either in the internal RAM (bytes
32 through 47) or a hardware bit. There are two ways to represent a bit address in an
operand.
1. You can specify the byte that contains the bit with a DATA type address, and
single out the particular bit in that byte with the bit selector ("." period)
followed by a bit identifier (0-7). For example, FLAGS.3, 40.5, 2IH.0 and
ACC.7 are valid uses of the bit selector. You can use an assembly-time expression to express the byte address or the bit identifier. The assembler will translate
this to the correct absolute or relocatable value. Note that only certain bytes in
the on-chip address space are bit addressable. If the data address is specified by
a relocatable expression, the referenced segment must have
BIT ADDRESSABLE relocation type (see Chapter 6 for segments). The expression that specifies the bit address must be absolute.
2. You specify the bit address explicitly. The expression now represents the bit
address in the bit space (it must have a BIT segment type). Note that bit
addresses 0 through 127 map onto bytes 32 through 47 of the on-chip RAM, and
bits 128 through 255 map onto the bit addressable locations of the hardware
register space (not all the locations are defined).
If the bit address is used in the context of BIT directive, then the first expression
must be an absolute or simple relocatable expression. If used in a machine instruction where a bit address is expected, then a general relocatable expression is also
allowed.
Figures 2-2a and 2-2b show the bits assigned to each numeric bit address.
The following examples show several ways of specifying bits.
SETB TR1
;set the predefined bit address TR1 (timer 1 run flag)
SETB ALARM
;set the user defined bit ALARM
SETB BBH.6
;Set bit 6 of location B8H (timer 1 run flag)
CPL FLAGS.ON ;complement the bit ON of the byte FLAGS
SETB8EH
;set the bit address 8E(base 16) (timer 1 run flag)
As with data addresses, there are several bit addresses that are predefined as symbols
that you can use in an operand. Table 2-2 shows these predefined bit addresses. You
can also define your own bit address symbols with the BIT directive described in
Chapter 4, Assembler Directives.
2-5
MCS-Sl
Operands and Expressions
NOT
BIT ADDRESSABLE
BIT POSITION
t-:-.-:-.-:-r=-.-:-r:-r=-r:-.....
7F 7E 70 7C 7B 7A 79 78
RAM
BIT
ADDRESS
SPACE
NOT
BITADDRESSABLE
BIT
ADDRESS
Figure 2-2a. Bit Addressable Bytes in RAM
765
4
3
21
0
ACC
EOH E7 E6 E5 E4 E3 E2 E1 EO
PSW
DOH 07 06 05 04 03 02 01 DO
COH Ct(:6 C' ~C3 C2 (:1 CO:
P3
BOH B7 B6 B5 B4 B3 B2 B1 BO
P2
AOH A7 A6 AS A4 A3 A2 A1 AO
P1
90H 97 96 95 94 93 92 91 90
PO
BOH 87 86 85 84 83 82 81 80
937-13
76543210
""-"-
~
L
~
"-
.'" "'"
\..
ff FE FDFC FB FA F9F8 F8H
IF EE ED.EC EB EA E9 £8 E8H
DF
tn, Dt DC DB DA 09 08
.BF BE BD BC BB BA B9 B8 B8H
AI'
AS AD AC AB AA
A9 A8 A8H
IP
IE
91' 9E 9D9C 9B 9A 99 98 98H
SCON
8F 8E 808C 8B 8A 89 88 88H
TCON
Figure 2-2b. Bit Addressable Bytes in Hardware
Register Address Area for 8051
2-6
08H
OF CE CD CC CB CA C9 C8 C8H
937-14
Operands and Expressions
MeS-51
Table 2-2. Predefined Bit Addresses for 8051
Bit
Bit
Position
Address
CY
AC
FO
RS1
RSO
OV
P
PSW.7
PSW.S
PSW.5
PSW.4
PSW.3
PSW.2
PSW.O
D7H
DSH
D5H
D4H
D3H
D2H
DOH
Carry Flag
Auxiliary Carry Flag
Flag 0
Register Bank Select Bit 1
Register Bank Select Bit 0
Overflow Flag
Parity Flag
TF1
TR1
TFO
TRO
IE1
IT1
lEO
ITO
TCON.7
TCON.S
TCON.5
TCON.4
TCON.3
TCON.2
TCON.1
TCON.O
8FH
8EH
8DH
8CH
8BH
8AH
89H
88H
Timer 1 Overflow Flag
Timer 1 Run Control Bit
Timer 0 Overflow Flag
Timer 0 Run Control Bit
Interrupt 1 Edge Flag
Interrupt 1 Type Control Bit
Interrupt 0 Edge Flag
Interrupt 0 Type Control Bit
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
SCON.7
SCON.S
SCON.5
SCON.4
SCON.3
SCON.2
SCON.1
SCON.O
9FH
9EH
9DH
9CH
9BH
9AH
99H
98H
Serial Mode Control Bit 0
Serial Mode Control Bit 1
Serial Mode Control Bit 2
Receiver Enable
Transmit Bit 8
Receive Bit 8
Transmit Interrupt Flag
Receive Interrupt Flag
EA
ES
ET1
EX1
ETO
EXO
IE.7
IE.4
IE.3
IE.2
IE.1
IE.O
AFH
ACH
ABH
AAH
A9H
A8H
Enable All Interrupts
Enable Serial Port Interrupt
Enable Timer 1 Interrupt
Enable External Interrupt 1
Enable Timer 0 Interrupt
Enable External Interrupt 0
RD
WR
T1
TO
INT1
INTO
TXD
RXD
P3.7
P3.B
P3.5
P3.4
P3.3
P3.2
P3.1
P3.0
B7H
BBH
B5H
B4H
B3H
B2H
B1H
BOH
Read Data for External Memory
Write Data for External Memory
Timer /Counter 1 External Flag
Timer/Counter 0 External Flag
Interrupt 1 Input Pin
Interrupt 0 Input Pin
Serial Port Transmit Pin
Serial Port Receive Pin
PS
PT1
PX1
PTO
PXO
IP.4
IP.3
IP.2
IP.1
IP.O
BCH
BBH
BAH
B9H
B8H
Priority of Serial Port Interrupt
Priority of Timer 1 Interrupt
Priority of External Interrupt 1
Priority of Timer 0
Priority of External Interrupt 0
Symbol
-
Meaning
Code Addressing
Code addresses are either absolute expressions whose values are within 0 to 65,535,
or relocatable expressions with a segmet type of CODE. There are three types of
instructions that require a code address in their operands. They are relative jumps,
in-block (2K page) jumps or calls, and long jumps or calls.
2-7
MCS-51
Operands and Expressions
The difference between each type is the range of values that the code address
operand may assume. All three expect an expression which evaluates to a CODE
type address (an absolute expression between 0 and 65,535 or a relocatable
operand), but if you specify a relative jump or an in-block jump, only a small subset
of all possible code addresses is valid. Instructions that use the code address operand
require that the symbol or expression specified be either of segment type CODE or a
typeless number. (Symbols and labels are discussed below under absolute expression
evaluation.)
Relative Jumps (SJMP and Conditional Jumps)
The code address in a relative jump must be close to the relative jump instruction
itself. The range is from -128 to +127 bytes from the first byte of the instruction that
follows the relative jump.
The assembler takes the specified code address and computes a relative offset that is
encoded as an 8-bit 2's complement number. That offset is added to the contents of
the program counter (PC) when the jump is made; but since the PC is always incremented to the next instruction before the jump is executed, the range is computed
from the succeeding instruction.
When you use a relative jump in your code, you must use an expression that
evaluates to the code address of the jump destination. The assembler does all the
offset computations. If the address is out of range, the assembler will issue an error
message.
In-Block Jumps and Calls (AJMP and ACALL)
The code address operand to an in-block jump or call is an expression that is
"evaluated and then encoded in the instruction. The low order 11 bits of the destination address are placed in the opcode byte and the operand byte. When the jump or
call is executed, the II-bit page address replaces the low order 11 bits of the program
counter. This permits a range of 2048 bytes, or anywhere within the current block.
The current block is thus determined by the high order 5 bits of the address of the
next instruction. If the operand is not in the current block, this is an assembler (or
RU1) error.
Note that if the in-block jump or call is the last instruction in a block, the high order
bits of the program counter change when incremented to address the next instruction; thus the jump will be made within that new block.
Long Jumps and Calls (LJMP and LCALL)
The code address operand to a long jump or call is an expression that will be
evaluated and then encoded as a 16-bit value in the instruction by the assembler, or,
if the expression is relocatable, by RU1. All 16 bits of the program counter are
replaced by this new value when the jump or call is executed. Since 16 bits are used,
any value representable by the assembler will be acceptable (0 - 65,535).
The following examples show each type of instruction that calls for a code address.
2-8
SJMP LABEL
;Jump to LABEL (relative offset LABEL must be within -128 and + 127
;of instruction that follows SJM P
ACALLSORT
;Call subroutine labelled SORT (SORT must be an address within the
;current 2K page)
LJMPEXIT
;Long jump; the label or symbol EXIT must be defined somewhere in
;the program.
Operands and Expressions
MCS-Sl
Generic Jump and Call (JMP and CALL)
The assembler provides two instruction mnemonics that do not represent a specific
opcode. They are JMP and CALL. JMP may assemble to ACALL or LCALL.
These generic mnemonics will always evaluate to an instruction, not necessarily the
shortest, that will reach the specified code address operand.
This is an effective tool to use during program development, since sections of code
change drastically in size with each development cycle. (See Chapter 3 for a complete
description of both generic jumps.) Note that the assembler decision may not be
optimal. For example, if the code address is a forward reference, the assembler will
generate a long jump although an in-block or short jump may be possible.
Assembly-Time Expression Evaluation
An expression is a combination of numbers, character strings, symbols, and
operators that evaluate to a single 16-digit binary number. Except for some directives, all expressions can use forward references (symbols that have not been defined
at that point in the program) and any of the assembly-time operators.
Specifying Numbers
You can specify numbers in hexadecimal (base 16), decimal (base 10), octal (base 8),
and binary (base 2). The default representation, used when no base designation is
given, is decimal. Table 2-3 below shows the digits of each numbering system and
the base designation character for each system (upper- and lowercase characters are
perm itted) .
The only limitation to the range of numbers is that they must be representable within
16 binary digits.
Table 2-4 gives several examples of number representation in each of the number
systems.
Table 2-3. Assembly Language Number Representation
Number System
Base Designator
Digits in Order of Value
Binary
B
O~ 1
Octal
OorO
0, 1, 2, 3, 4, 5, 6, 7
Decimal
o or (nothing)
0, 1, 2, 3, 4, 5, 6, 7, 8, 9
Hexadecimal
H
0, 1, 2, 3, 4, 5, 6, 7,
8, 9, A, B, C, 0, E, F
Table 2-4. Examples of Number Representation
base 16
base 10
baseS
base 2
01010000B
50H
80
120G
OACH'
1720
254Q
10101100B
01h
1
10
1B
10H
16d
200
10000B
'A hexadecimal number must start with a decimal digit; 0 is used here.
2-9
MeS-51
Operands and Expressions
ASM51 Number Representation
Internally, ASM51 represents all numeric values with 16 bits. When ASM51
encounters a number in an expression, it immediately converts it to 16-bit binary
representation. Numbers cannot be greater than 65,535. Appendix H describes con.
version of positive numbers to binary representation.
Negative numbers (specified by the unary operator "-") are represented in 2's
complement notation. There are two steps to converting a positive binary number to
a negative (2's complement) number.
0000 0000 0010 OOOOB
= 20H
1111 1111 1101 1111
= Not 20H
1. Complement each bit in the number.
1111 1111 1110 0000
= (Not 20H) +1
2. Add 1 to the complement.
1111 1111 1110 OOOOB
= -20H
To convert back simply perform the same two steps again.
Although 2's complement notation is used, ASM51 does not convert these nl,lmbers
for comparisons. Therefore, large positive numbers have the same representation as
small negative numbers (e.g., -1 = 65,535). Table 2-5 shows number interpretation
at assembly-time and at program execution-time.
Table 2-5. Interpretations of Number Representation
Number Characteristic
Assembly-Time
Expression Evaluation
Program Execution
Arithmetic
Base Representation
Binary, Octal, Decimal,
or Hexadecimal
Binary, Octal, Decimal,
or Hexadecimal
Range
0-65,535
User Controlled
Evaluates To:
16 Bits
User Interpretation
Internal Notation
Two's Complement
Two's Complement
Signed/Unsigned
Arithmetic
Unsigned
User Interpretation
Character Strings in Expressions
The MCS-51 assembler allows you to use ASCII characters in expressions. Each
character stands for a byte containing that character's ASCII code. (Appendix H
contains a table of the ASCII character codes.) That byte can then be treated as a
numeric value in an expression. In general, two characters or less are permitted in a
string (only the DB directive accepts character strings longer than two characters). In
a one character string the high byte is filled with O's. With a two character string, the
first character's ASCII value is placed in the high order byte, and the second
character's value is placed in the low order byte.
All character strings must be surrounded by the single quote character ('). To
incorporate the single quote character into the' string, place two single quote
characters side-by-side in a string. For example, 'z'" is a string of two characters: a
lower case "Z" and the single quote character.
2-10
Operands and Expressions
MeS-51
The ability to use character strings in an expression offers many possibilities to
enhance the readability of your code. Below, there are two examples of how
character strings can be used in expressions.
TEST: CJNE A,II'X',SKIP
JMPFOUND
SKIP: MOVA,@R1
INCR1
DJNZ R2,TEST
; If A contains 'X' then fall through
; Otherwise, jump to skip and
; Move next character into accumulator
; Change R1 to point to next character
; JUMP to TEST if there are still more
; characters to test
MOV A,SBUF
; Move character in serial port buffer
; to accumulator
; Subtract '0' from character just read
; this returns binary value of the digit
SUBB A,II'O'
NOTE
A corollary of this notation for character strings is the null string-two
single quotes surrounding no characters (side-by-side). When the null
character string is used in an expression it evaluates to 0, but when used as
an item in the expression list of a DB directive it will evaluate to nothing and
will not initiate memory. (See Chapter 4 for an example.)
Use of Symbols
The assembler has several kinds of symbols available to the programmer. They may
stand for registers, segments, numbers,and memory addresses. They allow a programmer to enhancelhe readability of his code.
Symbols are defined by four attributes:
• Type-register, segment, number, address
• Segment Type-DATA, BIT, XDATA, CODE, IDATA
• Scope-local, public, external
• Value-register name, segment base address, constant value, symbol address
(depending on type)
Not all of these four attributes are valid combinations.
The type attribute provides a common classification to the symbols:
• Register-indicates symbols which were defined as such by EQU or SET
directives
• Segment-indicates symbols which were designated as relocatable segments
• Number-indicates that the symbol represents a pure number and can be used in
any expression. (It has no segment type.)
• Address-indicates that the symbol represents a memory address.
The segment type specifies, for segment symbols, the address space where the segment resides. For address type symbols, it specifies the way the symbol may be used
(as a DATA address, BIT address, etc.). Usually it is identical to the address space in
which the owning segment was defined. The only exception is for symbols defined as
bits within a BIT ADDRESSABLE DATA type segment (see the Bit directive in
Chapter 4). Such symbols have a BIT type.
The scope attribute is valid for number and address type symbols. It specifies
whether the symbol is local, public, or external.
2-11
MeS-51
Operands and Expressions
The value attribute is defined with respect to the type of the symbol:
• Register-the value is the name (in ASCII) of the register
• Segment-the value is the base address (computed at RL-time)
• Number-the value of the constant
• Address-for an absolute symbol, the value is the absolute address within the
containing address space. For a relocatable address symbol, the value is the offset (in bits or bytes depending on the segment type) from the base of its owning
segment.
Once you have defined a symbol anywhere in your program (some expressions
require that no forward references be used), you can use it in any numeric operand
in the same way that you would use a constant, providing you respect segment type
conventions. The segment type required for each numeric operand is described
above. The creation of user-defined symbols is completely described in Chapter 4.
Besides the user-defined symbols, there are several predefined addresses available
for the hardware registers and flags. Table 2-6 shows all of the predefined data
address symbols and the values they represent. The bit address symbols have been
listed earlier in this chapter. (See Table 2-2.)
Remember that these symbols evaluate to a data address and cannot be used in
instructions that call for a special assembler symbol.
ADD A,1I5
; This is a valid instruction. A is the special
; assembler symbol required for this operand
; This is an invalid instruction and will generate
; an error message. ACC is an address and not
; the special symbol required for the instruction
ADD ACC,1I5
There is an additional symbol that may be used in any numeric operand, the location
counter ($). When you are using the location counter in an instruction's operand, it
Table 2-6. Predefined Data Addresses for 8051
2-12
Symbol
Hexadecimal
Address
ACC
8
DPH
OPl
IE
IP
PO
P1
P2
P3
PSW
S8UF
SCON
SP
TCON
THO
TH1
TlO
Tl1
TMOD
EO
FO
83
82
A8
88
80
90
AO
80
DO
99
98
81
88
8C
80
8A
88
89
Meaning
Accumulator
Multiplication Register
Data Pointer (high byte)
Data POinter (low byte)
Interrupt Enable
Interrupt Priority
PortO
Port 1
Port 2
Port 3
Program Status Word
Serial Port Buffer
Serial Port Controller
Stack Pointer
Timer Control
Timer 0 (high byte)
Timer 1 (high byte)
Timer 0 (low byte)
Timer 1 (low byte)
Timer Mode
Operands and Expressions
MeS-51
will stand for the address of the first byte of the instruction currently being encoded.
You can find a complete description of how to use and manipulate the location
counter in Chapter 4, Assembler Directives.
Using Operators in Expressions
There are four classes of assembly-time operators: arithmetic, logical, special, and
relational. All of them return a 16-bit value. Instruction operands that require only 8
bits will receive the low order byte of the expression. The distinction between each
class of operators is loosely defined. Since they may be used in the same expression,
they work on the same type of data, and they return the same type of data.
Arithmetic Operators
Table 2-7 contains a list of all the arithmetic operators.
Table 2-7. Arithmetic Assembly-Time Operators
Meaning
Operator
+
Unary plus or add
-
Unary minus or subtract
,
Multiplication
1
Integer division (discard remainder)
MOD
Modular division (discard quotient)
The following examples all produce the same bit pattern in the low order byte
(0011 OlOIB):
+53
27+26
-203
65-12
2'25+3
multiplication is always executed before the addition
160/3
153 MOD 100
Note that the MOD operator must be separated from its operands by at least one
space or tab, or have the operands enclosed in parentheses.
Logical Operators
Table 2-8 contains a list of all logical operators. The logical operators perform their
operation on each bit of their operands.
.
Table 2-8. Logical Assembly-Time Operators
Operator
Meaning
OR
Full 16·bit OR
AND
Full 16·bit AN.D
XOR
Full 16·bit exclusive OR
NOT
Full 16·bit complement
The following examples all produce the same 8-bit pattern in the low order byte
(001101OIB):
00010001B OR
01110101 BAND
11000011B XOR
NOT
00110100B
10110111 B
11110110B
11001010B
2-13
MCS-Sl
Operands and Expressions
Note that all logical operators must be separated from their operand by at least one
space or tab, or have the operands enclosed in parentheses.
Special Assembler Operators
Table 2-9 contains a list of all special operators:
Table 2-9. Special Assembly-Time Operators
Operator
Meaning
SHR
16-bit shift right
SHL
16-bit shift left
HIGH
Select the high order byte of operand
LOW
Select the low order byte of operand
( )
Evaluate the contents of the parenthesis first
The following examples all produce the same 8-bit pattern in the low order byte
(0011 0101B):
01AFH SHR3
Bits are shifted out the right end
and 0 is shifted into the left.
HIGH (1135H SHL 8)
Parenthesis is required since HIGH
has a greater precedence than SHL.
Bits are shifted out the left and
ois shifted in the right.
LOW 1135H
Without using the LOW operator.
the high order byte would have
caused an error in an 8-bit
operand.
Note SHR, SHL, HIGH and LOW must be separated from their operands by at
least one space or tab, or have the operands enclosed in parentheses.
Relational Operators
The relational operators differ from all of the other operators in that the result of a
relational operation will always be either 0 (False) or OFFFFH(True). Table 2-10
contains a list of all the relational operators:
Table2-10. Relational Assembly-Time Operators
Meaning
Operator
EQ
==
Equal
NE
<>
<
<=
>
>=
Not equal
LT
LE
GT
GE
2-14
Less than
Less than or equal to
Greater than
Greater than or equal to
Operands and Expressions
MCS-51.
The following examples all will return TRUE (OFFFFH):
27H EQ 390
27H <>270
33 LT 34
7>5
16 GE 10H
Note that the two-letter (mnemonic) form of the relational operator must be
separated from their operands by at least one space or tab; the symbolic form does
not. If the space or tab is not used, the operand must be enclosed in parentheses.
Operator Precedence
Every operator is given a precedence in order to define which operator is evaluated
first in an expression. ,For example, the expression 3* 5+ 1 could be interpreted as 16
or 18 depending on whether the + or the * is evaluated first. The following list shows
the precedence of the operators in descending order.
• Parenthesized expression ( )
•
HIGH, LOW
•
*, I, MOD, SHL, SHR
•
+, - unary and binary forms
•
EQ,NE,LT,LE,GT,GE,=,<>,<,<=,>,>=
•
•
•
NOT
AND
OR,XOR
All operators on the same precedence level are evaluated from left to right in the
expression.
Segment Typing in Expressions
Most expressions formed with assembly-time operators do not have a segment type,
but some operations allow the expression to assume the segment type of a symbol
used in the expression. The rules for expressions having a segment type are listed
below.
1. The result of a unary operation (+, -, NOT, LOW, HIGH) will have the same
segment type as that of its operand.
2. The result of all binary operations except plus (+) and minus (-) will have no
segment type (Le., NUMBER).
3. For a binary plus or minus operation, if only one of the operands has a segment
type, then the result will have that segment type. If not, the result will have no
segment type.
This means that only memory address plus or minus a number (or a number plus or
minus a number) gives a memory address. All other combinations produce a typeless
value. For example, code-address + (data_address_l - data_address_2) produces a value which is a CODE address; (data_address_l - dat~address_2) has
no segment type.
2-15
Operands and Expressions
Relocatabl"e Expression Evaluation
A relocatable expression is an expression that contains a relocatable or external
reference, called the "relocatable symbol." Such an expression cannot be completely evaluated at assembly time. The Relocator and Linker program (RL51)
finalizes such expressions using its additional knowledge; i.e., where the relocatable
segments and the public symbols are located.
A relocatable expression may usually contain only one relocatable symbol.
However, when subtracting ("-") or comparing (">", EQ, etc.) relocatable symbols
which refer to the same relocatable segment, the result is absolute quantity, and
these symbols are not counted as relocatable.
The relocatable symbol may be modified by adding or subtracting an absolute quantity (called offset). Thus the following forms result in valid relocatable expressions:
relocatable_symbol + absolute_expression
relocatable_symbol - absolute_expression
absolute_expression + relocatable_symbol
There are two types of relocatable expressions: simple relocatable expressions which
can be used for symbol definition and code generation; and general r~locatable
expressions which can be used only in code generation.
'
Simple Relocatable Expressions
In simple relocatable expressions the relocatable symbol can only represent an
address in a relocatable segment. External and segment symbols are not allowed.
Simple relocatable expressions can be used in three contexts:
1. As an operand to the ORG statement.
2. As an operand to the following symbol definition directives: EQU, SET,
CODE, XDAT A, IDAT A, BIT or the DATA directives.
3. As an operand to a machine instruction or a data initialization directive (DB or
DW).
Examples:
VALID
REL1 + ABS1*10
REL2-ABS1
REL1 + (REl2- REL3) ... assuming REL2 and REL3 refer to the same segment
INVALID
(REL1 + ABS1)*10 ... relocatable quantity may not be multiplied
EXT1- ABS1
... this is a general relocatable expression
REL1 + REL2- REL3 ... you cannot add relocatable symbols (REL1, REL2)
General Relocatable Expressions
General relocatable expressions can be used only in statements which generate code;
i.e., as operands to machine instructions, or as items in a DB or DW directive.
In this case the relocatable symbol may be a simple relocatable symbol (representing
an address in a relocatable segment). a segment symbol (representing the base
address of a relocatable segment), or an external symbol.
2-16
MeS-51
Operands and Expressions
MCS-51
In addition, the relocatable expression may be prefixed by the LOW or the HIGH
operator.
Examples
VALID
REL1 + ABS1*10
EXT1 - ABS1
LOW (SEG1 + ABS1)
INVALID
(REL1 + ABS1)*10 , .. relocatable quantity may not be multiplied
EXT1 - REL 1 ... you can add I subtract only absolute quantities
LOW SEG1 + ABS1 ... LOW I HIGH may be applied only to the final relocatable expression
(or to an absolute expression); the expression here is equ ivalent to
(LOW SEG1) + ABS1
2-17
CHAPTER 3
INSTRUCTION SET
This chapter contains complete documentation for all of the 8051 instructions. The
instructions are listed in alphabetical order by mnemonic and operands.
Introduction
This chapter is designed to be used as a reference. Each instruction is documented
using the same basic format. The action performed by an instruction is defined in
three ways. First, the operation is given in a short notation; the symbols used and
their meanings are listed in the table below. The operation is then defined in a few
sentences in the description section. Finally, an example is given showing all of the
registers affected and their contents before and after the instruction.
NOTE
The only exception is that the program counter (PC) is not always shown.
All instructions increment the PC by the number of bytes in the instruction.
The "Example:" entry for most instructions do not show this increment by
the PC. Only those instructions that directly affect the PC (e.g., JMP,
ACALL, or RET) show the contents of the PC before and after execution.
The list of notes that appears at the bottom of some instructions refer to side-effects
(flags set and cleared and limitations of operands). The numbers refer to the notes
tabulated on page 3-143/3-144. You can unfold that page for easier reference while
. you are studying the instruction set.
The "Operands:" entry for each instruction briefly indicates the range of values and
segment type permitted in each operand. For a complete description of the limits of
any operand see Chapter 2. In general, the operand's name will identify what section
to consult.
With one exception, the operands to 3 byte instructions are encoded in the same
order as they appear in the source. Only the "Move Memory to Memory" instruction is encoded with the second operand preceding the first.
3-1
Instruction Set
MeS-51
The illustration below (figure 3-1) describes the meaning of each section of the
instruction documentation.
ADD
Add Immediate Data
Mnemonic:
ADO
Accumulator
-256 <= data <= + 255
A
Operands:
data
Format:
ADD
Bit Pattern:
I 00100100 IlmmediateDatal
Operation:
tA) -tAl + aata
A,faata
o
7
Byle.: 2
Cycles: I
Flags:
C
AC
FO AS1 AS(I OV
1-1-1 I I I-I I-I
PSW
Description;
This inSlrllction adds the 8-bit immediate data value to the contents
of the accumulator. It places the result in the accumulator.
Example:
ADD A,132H
; Add 32H to accumulator
Encoded Instruction:
1001001001001100101
7
0
7
0
After
Before
Accumulator
Accumulator
1001001101
1010110001
o
7
0
Notes: 4, 5,6.7
Figure 3-1. Format For Instruction Definitions
Mnemonic: shows opcode mnemonic. It is shown in upper case, but upper or
lower case characters are permitted.
Operands: indicates range and type of operands permitted.
Format: shows the format of the instruction, including the order of operands
on the source line.
Bit Pattern: indicates bit pattern in opcode and position of operands when
encoded. Letters in the opcode's bit pattern vary with operand specified.
Operation: symbolically defines the operation performed by the instruction.
The symbols used in this entry are defined in table 3-1.
Bytes and Cycles: shows the number of bytes of code and the number of
machine cycles used by the instruction.
Flags: indicates any status flag that may be changed during the execution of
the instruction.
Description: is a brief prose description of the operation performed by the
instruction.
Example: shows an example instruction as it would appear in the source. It
also shows the bit pattern of the encoded instruction, and the contents of all
registers affected by the instruction, immediately before and after the instruction is executed.
The PC is incremented by all instructions, but only instructions that affect the
PC as part of their operation show its contents in the example.
Notes: indicates the notes on page 3-142 that pertain to the instruction.
3-2
Instruction Set
MeS-51
Table 3-1. Abbreviations and Notations Used
A
AB
B
bit address
page address
relative offset
C
code address
data
data address
DPTR
PC
Rr
SP
high
low
i-j
.n
AND
NOT
OR
XOR
+
(X)
«X))
<>
<
>
Accumulator
Register Pair
Multiplication Register
8051 bit address
II-bit code address within 2K page
8-bit 2's complement offset
Carry Flag
Absolute code address
Immediate data
On-chip 8-bit RAM address
Data pointer
Program Counter
Register(r=O- 7)
Stack pointer
High order byte
Low order byte
Bits i through j
Bitn
Logical AND
Logical complement
Logical OR
Logical exclusive OR
Plus
Minus
Divide
Multiply
The contents of X
The memory location addressed by (X)
(The contents of X)
Is equal to
Is not equal to
Is less than
Is greater than
Is replaced by
l·3
MCS-Sl
Absolute Call Within 2K Byte Page
Mnemonic:
ACALL
Operands:
code address
Format:
ACALL code address
Bit Pattern:
aaa10001
7
Operation:
0
I aaaaaaaa I
7
0
(PC) +- (PC) + 2
(SP) +- (SP) + 1
«SP)) +- (PC low)
(SP) +- (SP) + 1
«SP)) +- (PC high)
(PC) 0-10 +- page address
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction stores the incremented contents of the program
counter (the return address) on the stack. The low-order byte of the
program counter (PC) is always placed on the stack first. It replaces
the low-order 11 bits of the PC with the encoded II-bit page
address. The destination address specified in the source must be
within the 2K byte page of the instruction following the ACALL.
The 3 high-order bits of the ll-bit page address form the 3 highorder bits of the opcode. The remaining 8 bits of the address form
the second byte of the instruction.
3-4
MCS-Sl
ACALL
ORG35H
ACALL SORT ; Call SORT (evaluates to page
; address 233H)
Example:
ORG233H
SORT: PUSH ACC
; Store Accumulator
RET
; Return from call
Encoded Instruction:
101010001 100110011
7
o
7
o
Before
After
Program Counter
Program Counter
I 00000000 I 00110101
I 00000010 I 00110011
15
8
7
'7
I
0
I 00000000 I
100101000
o
7
I
0
0
100110111
7
0
I
(28H)
(28H)
I 00000000 I
I 00000000 I
7
7
(27H)
(27H)
7
8
Stack Pointer
Stack Pointer
100100110
15
0
0
7
0
Notes: 2,3
3-5
ADD
MeS-51
Add Immediate Data
Mnemonic:
ADD
Operands:
A
data
Format:
ADD
Accumulator
-256 <= data <= + 255
A,#data
Bit Pattern:
I 001 001 00 Ilmmediate Datal
o
7
o
7
(A) - (A) + data
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction adds the 8-bit immediate data value to the contents
of the accumulator. It places the result in the accumulator.
Example:
ADD A,#32H
; Add 32H to accumulator
Encoded Instruction:
100100100 100110010
707
Before
After
Accumulator
Accumulator
I 00100110 I
7
0
Notes: 4, 5, 6, 7
3-6
0
01011000
7
'0
ADD
MeS-51
Add Indirect Address
Mnemonic:
ADD
Operands:
A
Rr
Format:
ADD
Accumulator
Register 0 <= r
A,@Rr
Bit Pattern:
1 0010011r
7
Operation:
(A)
<= 1
I
0
+-
(A)
+ «Rr))
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction adds the contents of the data memory location
addressed by register r to the contents of the accumulator. It places
the result in the accumulator.
Example:
ADDA,@R1
; Add indirect address to accumulator
Encoded Instruction:
100100111
7
I
o
Before
After
Accumulator
Accumulator
1 1 0000110
7
I
o
7
Register 1
100011100
o
7
(1CH)
I
o
(1CH)
101100010
7
o
Register 1
00011100
7
111101000 1
I
0
101100010
7
0
Notes: 5,6,7, 15
3-7
ADD
MeS-51
Add Register
Mnemonic:
ADD
Operands:
A
Rr
Format:
ADD A,Rr
Accumulator
Register 0 <= r
<= 7
Bit Pattern:
100101rrr
7
0
(A) - (A) + (Rr)
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO AS1 ASO OV
PSW
Description:
This instruction adds the contents of register r to the contents of
the accumulator. It places the result in the accumulator.
Example:
ADD A,R6
; Add R6 to accumulator
Encoded Instruction:
100101110 1
7
o
Before
After
Accumulator
Accumulator
10111,01101
111111011
7
o
o
Register 6
RegisterS
110000101
110000101
7
0
Notes: 5, 6, 7
3-8
7
7
0
MeS-51
ADD
Add Memory
Mnemonic:
ADD
Operands:
A
data address
Format:
ADD
Bit Pattern:
I 00100101 IData Address I
(A)
<= 255
A,data address
7
Operation:
Accumulator
0 <= data address
0
+-
(A)
7
0
+ (data address)
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction adds the contents of the specified data address to
the contents of the accumulator. It places the result in the
accumulator.
Example:
ADD A,32H
; Add the contents of
; 32H to accumulator
Encoded Instruction:
I 00100101
7
00110010
7
0
0
Before
After
Accumulator
Accumulator
100100110
7
I
o
101111001
7
o
(32H)
(32H)
101010011
101010011
7
0
7
0
Notes: 5,6,7,8
3-9
Mes-sl
ADDC
Add Carry Plus Immediate Data to Accumulator
Mnemonic:
ADDC
Accumulator
-256 <= data <= + 255
A
Operands:
data
ADDC
Format:
A,#data
Bit Pattern:
0011 01 00 Ilmmediate Datal
7
Operation:
(A)
0
+-
(A)
7
0
+ (C) + data
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
1-1-1
P
I-I
I-I
PSW
Description:
"
This instruction adds the contents of the carry flag (0 or 1) to the
contents of the accumulator. The 8-bit immediate data value is
added to that intermediate result, and the carry flag is updated. The
accumulator and carry flag reflect the sum of all three values.
Example:
ADDC A,#OAFH
; Add Carry and OAFH to accumulator
Encoded Instruction:
00110100
10101111
7
7
0
Before
After
Accumulator
Accumulator
01110001
00100001
7
7
0
Carry
Carry
QJ
QJ
Notes: 4, 5, 6, 7
3-10
0
0
ADDC
MCS-Sl
Add Carry Plus Indirect Address to Accumulator
Mnemonic:
ADDC
Operands:
A
Register
Format:
ADDC
Accumulator
0<=r<=1
A,@Rr
Bit Pattern:
0011011r
7
Operation:
(A)
0
+-
(A)
+
(C)
+ «Rr))
Bytes:
Cycles:
Flags:
C
AC
FO RS1 RSO OV
p
1-1- I
PSW
Description:
This instruction adds the contents of the carry flag (0 or 1) to the
contents of the accumulator. The contents of data memory at the
location addressed by register r is added to that intermediate result,
and the carry flag is updated. The accumulator and carry flag
reflect the sum of all three values.
3-11
MeS-51
ADDC
; Add carry and indirect address to
; accumulator
ADDC A,@R1
Example:
Encoded Instruction:
100110111
7
I
0
Before
After
Accumulator
Accumulator
111101000
7
I
1011010011
7
0
0
(69H)
(69H)
100011000
I
0
Carry
IT]
Notes: 5,6, 7, 15
3-12
0
Register 1
101101001
7
I 00000000 I
7
0
Register 1
7
I
1000110001
7
Carry
m
0
ADDC
MCS-Sl
Add Carry Plus Register to Accumulator
Mnemonic:
ADDC
Operands:
A
Register
Format:
ADDC A,Rr
Accumulator
0<=r<=7
Bit Pattern:
00111rrr
7
Operation:
(A)
0
+-
(A)
+ (C) + (Rr)
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
1-1-1
P
I-I I-I
PSW
Description:
This instruction adds the contents of the carry flag (0 or 1) to the
contents of the accumulator at bit o. The contents of register r is
added to that intermediate result, and the carry flag is updated. The
accumulator and carry flag reflect the sum of all three values.
Example:
ADDC A,R7
; Add carry and register 7
; to accumulator
Encoded Instruction:
00111111
7
0
Before
After
Accumulator
Accumulator
00110000
00111011
7
7
0
Register 7
Register 7
100001010
7
0
0
Carry
CD
00001010
7
0
Carry
m
Notes: 5, 6, 7
3-13
MeS-51
ADDC
Add Carry Plus Memory to Accumulator
Mnemonic:
ADDC
Operands:
A
data address
Format:
ADDC
Bit Pattern:
I 0011 01 01 IData Address I
<= 255
A,data address
7
Operation:
Accumulator
0 <= data address
0
(A) .... (A)
+
(C)
7
0
+ (data address)
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
P
I-I I-I
1-1-1
PSW
Description:
This instruction adds the contents of the carry flag (0 or 1) to the
contents of the accumulator. The contents of the specified data
address is added to that intermediate result, and the carry flag is
updated. The accumulator and carry flag reflect the sum of all
three values.
Example:
ADDC A,25H
; Add carry and contents of 25H to
; accumulator
Encoded Instruction:
100110101
7
0
7
0
Before
After
Accumulator
Accumulator
10101110
7
0
110110101
7
0
(25H)
(25H)
I 00000111
I 00000111
7
o
Carry
m
Notes: 5,6, 7,8
3-14
00100101
7
Carry
m
o
MeS-51
AJMP
Absolute Jump within 2K Byte Page
Mnemonic:
AJMP
Operands:
code address
Format:
AJMP code address
Bit Pattern:
I aaa00001 I aaaaaaaa I
7
0
7
0
(PC) +- (PC) + 2
(PC) 0-10 +- page address
Operation:
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1RSO OV
p
PSW
Description:
This instruction replaces the low-order 11 bits of the program
counter with the encoded ll-bit address. The destination address
specified in the source must be within the 2K byte page of the
instruction following the AJMP .
The 3 high-order bits of the ll-bit page address form the 3 highorder bits of the opcode. The remaining 8 bits of the address form
the second byte of the instruction.
Example:
ORGOE80FH
TOPP: MOV A,R1
ORGOEADCH
AJMPTOPP ; Jump backwards to TOPP
; at location OE80FH
Encoded Instruction:
00000001
00001111
7
7
0
0
After
Before
Program Counter
Program Counter
11101010
11011100
15
7
8
0
I
111101000 100001111
15
8
7
0
Notes: None
3-15
ANL
MCS-Sl
Logical AND Immediate Data to Accumulator
Mnemonic:
ANL
Operands:
Accumulator
-256 <= data <= + 255
A
data
Format:
ANL A.'data
Bit Pattern:
I 0101 01 00 Ilmmediate Datal
o
7
Operation:
o
7
(A) - (A) AN 0 data
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO AS1 ASO OV
PSW
Description:
This instruction ANDs the 8-bit immediate data value to the
contents of the accumulator. Bit n of the result is 1 if bit n of each
operand is 1; otherwise bit n is O. It places the result in the
accumulator.
Example:
ANL A,IO0001000B
; Mask out all but bit 3
Encoded Instruction:
I 01010100 I 00001000 I
707
Before
After
Accumulator
Accumulator
101110111
I 00000000 I
7
Notes: 4.5
3-16
0
o
7
o
ANL
Mes-sl
Logical AND Indirect Address to Accumulator
Mnemonic:
ANL
Operands:
A
Accumulator
Register 0 <= r
Rr
Format:
ANL
Bit Pattern:
I 0101011r I
<= 1
A,@Rr
7
0
(A) - (A) AND «Rr))
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC FO RS1 RSO OV
P
I-I
PSW
Description:
This instruction ANDs the contents of the memory location
addressed by the contents of register r to the contents of the
accumulator. Bit n of the result is 1 if bit n of each operand is 1;
otherwise bit n is O. It places the result in the accumulator.
Example:
ANL
; AND indirect address with
; accumulator
A,@RO
Encoded Instruction:
101010110
I
o
7
Before
After
Accumulator
Accumulator
100111111
100001111
7
o
7
o
Register 0
Register 0
101010010
o
7
I
101010010
7
o
I
(52H)
(52H)
100001111
7
o
7
o
Notes: 5,15
3-17
ANL
MCS-51
Logical AN 0 Register to Accumulator
Mnemonic:
ANL
Operands:
A
Accumulator
Rr
0<=Rr<=7
Format:
ANL
A,Rr
Bit Pattern:
101011rrr
7
(A)
Operation:
0
+-
(A) AND (Rr)
Bytes:
Cycles:
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
,.
Example:
This instruction ANDs the contents of register r to the contents of
the accumulator. Bit n of the result is 1 if bit n of each operand is 1;
otherwise bit n is O. It places the result in the accumulator.
MOV R4,#10000000B
ANL A,R4
; Move mask to R4
; AND register 4 with accumulator
Encoded Instruction:
101011100 1
7
o
Before
After
Accumulator
Accumulator
10011001
7
o
Register 4
Note: 5
3-18
7
o
Register 4
10000000
7
110000000 1
o
10000000
7
o
ANL
MeS-51
Logical AND Memory to Accumulator
Mnemonic:
ANL
Operands:
A
data address
Format:
AN L A,data address
Bit Pattern:
1 01 0 1 01 01
7
(A)
Operation:
0
+-
Accumulator
0 <= data address <= 255
IData Address I
7
0
(A) AND (data address)
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ANDs the contents of the specified data address to
the contents of the accumulator. Bit 11 of the result is 1 if bit n of
each operand is also 1; otherwise bit n is O. It places the result in the
accumulator.
Example:
ANL
; AND contents of 37H with
; accumulator
A,37H
Encoded Instruction:
101010101
7
o
00110111
7
o
Before
After
Accumulator
Accumulator
101110111
101110000
7
o
7
o
(37H)
(37H)
111110000 1
111110000
7
0
7
I
I
0
Notes: S,8
3-19
ANL
MeS-51
Logical AN D Bit to Carry Flag
Mnemonic:
ANL
Operands:
C
bit address
Format:
ANL
Bit Pattern:
Carry Flag
0 <= bit address <= 255
C,bitaddress
I 1 000001 0 I Bit Address I
707
Operation:
0
(C) - (C) AND (bit address)
Bytes: 2
Cycles: 1
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction ANDs the contents of the specified bit address to
the contents of the carry flag. If both bits are 1, then the result is 1;
otherwise, the result is O. It places the result in the carry flag.
Example:
ANL
C,37.3
; AN 0 bit 3 of byte 37 with Carry
Encoded Instruction:
\10000010 100101011
7
0 7
0
Before
After
Carry Flag
Carry Flag
IT]
IT]
(37)
(37)
100101110
730
Notes: None
3-20
I
\ 00101110
7
3
0
ANL
Mes-sl
Logical AN D Complement of Bit to Carry Flag
Mnemonic:
AN L
Operands:
C
bit address
Format:
ANL C,lbitaddress
Carry Flag
0 <= bit address
<= 255
Bit Pattern:
10110000
7
0
Operation:
(C)
+-
Bit Address
7
0
(C) AND NOT (bit address)
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ANDs the complemented contents of the specified
bit address to the contents of the carry flag. The result is 1 when the
carry flag is I and the contents of the specified bit address is O. It
places the result in the carry flag. The contents of the specified bit
address does not change.
Example:
ANL
; Complement contents of 40.5
; then AND with Carry
C,!40.5
Encoded Instruction:
10110000
01000101
7
7
0
0
Before
After
Carry Flag
Carry Flag
IT]
IT]
(40)
(40)
101011000
101011000
750
750
Notes: None
3-21
ANL
MCS-51
Logical AN D Immediate Data to Memory
Mnemonic:
ANL
Operands:
data address
data
Format:
AN L data address ;#da ta
0 <=data address <= 255
-256 <= data <= + 255
Bit Pattern:
01010011 I Data Address Ilmmediate Datal
7
Operation:
07
(data address)
+-
07
0
(data address) AND data
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
"
Example:
This instruction ANDs the 8-bit immediate data value to the
contents of the specified data address. Bit n of the result is 1 if bit n
of each operand is also 1; otherwise, bit n is o. It places the result in
data memory at the specified address.
; Move PSW to 57H
; Mask out all but parity bit
; to check accumulator parity
MOV 57H,PSW
ANL 57H,#01H
Encoded Instruction:
01010011
01010111
00000001
7
7
7
0
0
Before
After
(57H)
(57H)
101110111
I 00000001
7
Notes: 4,9
3-22
0
0
7
0
ANL
MeS-51
Logical AND Accumulator to Memory
Mnemonic:
ANL
Operands:
data address
A
Format:
ANL dataaddress,A
Bit Pattern:
I 0 1 0 1 0 0 1 0 IData Add ress I
o
7
(data address)
+-
7
Operation:
0 <= data address
Accumulator
<= 255
o
(data address) AND A
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
This instruction ANDs the contents of the accumulator to the
contents of the specified data address. Bit n of the result is 1 if bit n
of each operand is also 1; otherwise, bit n is O. It places the result
in data memory at the specified address.
Example:
MOV A,#1 0000001 B
ANL 10H,A
; Load mask into accumulator
; Mask out all but bits 0 and 7
Encoded Instruction:
I 01010010 I 00010000 I
7
o
7
o
Before
After
Accumulator
Accumulator
10000001
110000001
7
0
7
0
(10H)
(10H)
100110001
1 00000001
7
o
7
o
Note: 9
3-23
MeS-51
CALL
Generic Call
Mnemonic:
CALL
Operands:
code address
Format:
CALL code address
Bit Pattern:
Translated to ACALL or LCALL as needed
Operation:
Either ACALL or LCALL
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction is translated to ACALL when the specified code
address contains no forward references and that address falls
within the current 2K byte page; otherwise; it is translated to
LCALL. This will not necessarily be the most efficient representation when a forward reference is used. See the description for
ACALL and LCALL for more detail.
Example:
ORG 80DCH
CALL SUB3
; Call SUB3 (SUB3 is a forward
; reference so LCALL is encoded
; even though ACALL would work in
; this case.)
SUB3: POP 55H
; Address 8233H
Encoded Instruction:
00010010
10000010
00110011
7
7
7
0
0
After
Before
Program Counter
Program Counter
10000000
11011100 1 110000010100110011
707
0
15
8
Stack Pointer
Stack Pointer
01100100
101100110
7
o
7
o
(65H)
(65H)
I 00000000
111011111
7
0
7
0
(66H)
(66H)
I 00000000
110000000
7
0
Notes: 1, 2, 3
3-24
0
7
0
7
0
CJNE
MCS-Sl
Compare Indirect Address to Immediate Data,
Jump if Not Equal
Mnemonic:
CJNE
Operands:
Rr
Register 0 <= r <= 1
data
-256 <= data <= + 255
code address
Format:
CJNE @Rr,#data,codeaddress
Bit Pattern:
I 1 011 011
7
Operation:
r
Ilmmediate Data
0 7
(PC) - (PC) + 3
IF ((Rr» < > data
THEN
(PC) - (PC)
IF ((Rr» < data
THEN
(C) -1
ELSE
(C)-O
0
I ReI. Offset
7
0
+ relative offset
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction compares the immediate data value with the
memory location addressed by register r. If they are not equal, control passes to the specified code address. If they are equal, then
control passes to the next sequential instruction.
If the· immediate data value is greater than the contents of the
specified data address, then the carry flag is set to 1; otherwise, it is
reset to O.
The Program Counter is incremented to the next instruction. If the
operands are not equal, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-25
MCS-Sl
CJNE
CJNE @R1,#01,SCAB; Jump if contents of
Example:
; indirect address do
; not equal 1
; 5AH bytes from the
;beginning of CJNE
SCAB: MOV C,FO
Encoded Instruction:
110110111 100000001 101010111
7
0
7
0
7
Before
After
Register 1
Register 1
101010011
101010011
7
7
0
0
(53H)
(53H)
1111000011
111100001
7
7
0
0
Carry Flag
Carry Flag
OJ
[IJ
Program Counter
Program Counter
100000000 111011100
15
8
7
Notes: 4,10,11,12,15
3-26
0
0
I
00000001 1 00110110
15
8
7
0
I
MCS-Sl
CJNE
Compare Immediate Data to Accumulator,
Jump if Not Equal
Mnemonic:
Operands:
Format:
CJNE
A
Accumulator
data
-256 <= data
code address
<= + 255
CJNE A,#data,codeaddress
Bit Pattern:
1 0110100 llmmediate Data
7
Operation:
0
7
0
(PC) +- (PC) + 3
IF (A) < > data
THEN
(PC) +- (PC)
IF (A) < data
THEN
(C) +-1
ELSE
(C) +- 0
I
ReI. Offset
7
0
+ relative offset
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
This instruction compares the immediate data value with the
contents of the accumulator. If they are not equal, control passes to
the specified code address. If they are equal, then control passes to
the next sequential instruction.
If the immediate data value is greater than the contents of the
accumulator, then the carry flag is set to 1; otherwise, it is reset
toO.
The Program Counter is incremented to the next instruction. If the
operands are not equal, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-27
MCS-Sl
CJNE
Example:
ORG 10DCH
CJNE A,'10H,NEXT ; Jump if accumulator does not equal
; 10H
NEXT:
INCA
; location 1136H
Encoded Instruction:
110110100
7
0
00010000
01010111
7
7
0
Before
After
Accumulator
Accumulator
101010000
7
I
1010100001
7
0
0
Carry Flag
Carry Flag
[JJ
0]
Program Counter
Program Counter
100010000 111011100
15
8
7
Notes: 4, to, 11, 12
3-28
0
0
I
100010001 100110110
15
8
7
0
I
CJNE
MCS-Sl
Compare Memory to Accumulator,
Jump if Not Equal
Mnemonic:
CJNE
Operands:
A
Accumulator
data address 0 <= data address <= 255
code address
Format:
CJN E A,data address ,code address
Bit Pattern:
1 011 01 01
7
Operation:
0
IData Address I
7
(PC) - (PC) + 3
IF (A) < > (data address)
THEN
(PC) - (PC)
IF (A) < (data address)
THEN
(C) +-1
ELSE
(C) -0
0
ReI. Offset
7
0
+ relative offset
Bytes: 3
2
~ycles:
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction compares the contents of the specified memory
location to the contents of the accumulator. If they are not equal,
control passes to the specified code address. If they are equal, then
control passes to the next sequential instruction.
If the contents of the specified memory location is greater than the
contents of the accumulator, then the carry flag is set to 1; otherwise, it is reset to O.
The Program Counter is incremented to the next instruction. If the
operands are not equal, then the relative offset is added to the
incremented. program counter, and the instruction at that address is
executed.
3-29
CJNE
MeS-51
Example:
CJNE A, 37H, TEST, Jump if 37H and accumulator
; are not equal
TEST:
INCA
; 4FH bytes from CJNE
Encoded Instruction:
110110101 100110111 101001100 1
7
o
7
o
Before
After
(37H)
(37H)
101111110
7
100100110
7
I
101111110
7
0
0
Accumulator
I
100100110
7
0
0
Carry Flag
Carry Flag
IT]
QJ
t 00000000
15
8
I
Accumulator
Program Counter
7
I
Program Counter
1110111 00
Notes: 8, 10, II, 12
3-30
o
7
0
I I 00000001 I 00110110 I
15
8
7
0
MCS-Sl
CJNE
Compare Immediate Data to Register,
Jump if Not Equal
Mnemonic:
CJNE
Operands:
Rr
Register
0 <= r <= 7
data
-256 <= data <= + 255
code address
Format:
CJNE Rr,#data,codeaddress
Bit Pattern:
1 0111 r r r Ilmmediate Data I ReI. Offset
7
Operation:
0 7
(PC) +- (PC)
< > data
IF (Rr)
< data
(PC) +- (PC)
THEN
7
0
+3
IF (Rr)
THEN
0
+ relative offset
(C) +-1
ELSE
(C) +- 0
Bytes: 3
9ycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction compares the immediate data value with the
contents of register r. If they are not equal, control passes to the
specified code address. If they are equal, then control passes to the
next sequential instruction.
If the immediate data value is greater than the contents of the
specified register, then the carry flag is set to 1; otherwise, it is reset
toO.
The Program Counter is incremented to the next instruction. If the
operands are not equal, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-31
MeS-51
CJNE
Example:
CJNE R5,#32H,SKIP10
SKIP10: MOV R5,PO
; Jump if register 5 does not
; equal32H
;13 bytes from CJNE
Encoded Instruction:
110111101110000000 1000010101
7
o
7
o
Before
After
Register 5
Register 5
I 00000001
7
I 00000001
0
7
0
Carry Flag
Carry Flag
OJ
OJ
Program Counter
I 00000000
15
8
Program Counter
111011100
7
Notes: 4, 10, 11, 12
3-32
o
7
o
I I 00000000
15
8
111101001
7
o
MeS-51
CLR
Clear Accumulator
Mnemonic:
CLR
Operands:
A
Format:
CLR A
Accumulator
Bit Pattern:
111100100
7
0
Operation:
I
(A)-O
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
I-I
PSW
Description:
This instruction resets the accumulator to o.
Example:
CLR A
; Set accumulator to 0
,!:ncoded Instruction:
111100100
7
I
0
Before
After
Accumulator
Accumulator
100111111
I 00000000 I
7
o
7
o
Note: S
3-33
MCS-Sl
CLR
Clear Carry Flag
Mnemonic:
CLR
Operands:
C
Format:
CLR C
Carry Flag
Bit Pattern:
111000011
7
Operation:
(C)
0
0
+-
Bytes:
Cycles:
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
This instruction resets the carry flag to O.
Example:
CLR
C
; Set carry flag to 0
Encoded Instruction:
1110000111
7
o
Before
After
Carry Flag
Carry Flag
QJ
W
Notes: None
3-34
CLR
MeS-51
Clear Bit
Mnemonic:
CLR
Operands:
bit address 0 <= bit address <= 255
Format:
CLR bit address
Bit Pattern:
1 11 00001 0 1 Bit Address 1
o
7
(bit address)
Operation:
7
+-
o
0
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction resets the specified bit address to o.
Example:
CLR40.5
; Set bit 5 of byte 40 to 0
Encoded Instruction:
01000101
111000010
7
0
7
0
Before
After
(40)
(40)
100100110
7 5
o
I
100000110
7 5
I
o
Notes: None
3-35
MCS-51
CPL
Complement Accumulator
Mnemonic:
CPL
Operands:
A
Format:
CPL A
Accumulator
Bit Pattern:
111110100 1
7
(A)
Operation:
0
+-
NOT (A)
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
Example:
This instruction resets each 1 in the accumulator to 0, and sets each
oin the accumulator to 1.
; Complement accumulator
CPL A
Encoded Instruction:
1111100111
7
o
Before
After
Accumulator
Accumulator
100110101
11001010
7
0
Notes: None
3-36
7
0
MCS-Sl
CPL
Complement Carry Flag
Mnemonic:
CPL
Operands:
C
Format:
CPL C
Carry flag
Bit Pattern:
110110011
7
Operation:
0
(C) - NOT (C)
Bytes: 1
Cycles: 1
Flags:
C
AC
I-I
p
FO RS1 RSO OV
PSW
Description:
This instruction sets the carry flag to 1 if it was 0, and resets the
carry flag to 0 if it was 1.
Example:
CPL C
; Complement Carry flag
Encoded Instruction:
110110011
7
I
0
Before
After
Carry Flag
Carry Flag
OJ
CD
Notes: None
MCS-51
CPL
Complement Bit
Mnemonic:
CPL
Operands:
bit address 0 <= bit address
Format:
CPL bit address
Bit Pattern:
1 1 011 001 0
o
7
<= 255
I Bit Address I
7
o
(bit address) ... NOT (bit address)
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction sets the contents of the specified bit address to 1 if
it was 0, and resets the contents of the bit address to 0 if it was 1.
Example:
CPL33.7
; Set bit 7 of byte 33 to 0
Encoded Instruction:
110110010 100001111
707
Before
After
(33)
(33)
1 1 01 0011 0
100100110
7
0
Notes: None
3-38
0
7
0
DA
MCS-Sl
Decimal Adjust Accumulator
Mnemonic:
DA
Operands:
A
Format:
DA A
Accumulator
Bit Pattern:
11010100
7
0
(See description below.)
Operation:
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction adjusts the contents of the accumulator to
correspond to packed binary coded decimal (BCD) representation,
after an add of two BCD numbers. If the auxiliary carry flag is 1,
or the contents of the low order nibble (bits 0-3) of the
accumulator is greater than 9, then 6 is added to the accumulator.
If the carry flag is set before or after the add or the contents of the
high order nibble (bits 4-7) is greater than 9, then 60H is added to
the accumulator. The accumulator and the carry flag contain the
final adjusted value.
Example:
ADD A,R1
DA A
; Adjust the Accumulator after add
Encoded Instruction:
11010100
7
0
Before
After
Accumulator
Accumulator
10011011
00000001
7
7
0
0
Carry Flag
Carry Flag
IT]
OJ
Auxiliary Carry Flag
Auxiliary Carry Flag
IT]
IT]
Notes: 5,6
3-39
Mes-sl
DEC
Decrement Indirect Address
Mnemonic:
DEC
Operands:
Rr
Format:
DEC@Rr
Register 0 <= r
<= 1
Bit Pattern:
10001011rl
7
Operation:
0
((Rr»
4-
((Rr)) -1
Bytes: 1
Cycles: 1
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction decrements the contents of the memory location
addressed by register r by 1. It places the result in the addressed
location.
Example:
DEC@RO
; Decrement counter
Encoded Instruction:
100010110 1
7
o
Before
After
Register 0
Register 0
I 001101,11
100110111
7
7
0
(37H)
(37H)
111011101
7
Note: 15
3-40
0
0
I
111011100
7
0
I
MCS-Sl
DEC
Decrement Accumulator
Mnemonic:
DEC
Operands:
A
Format:
DEC A
Accumulator
Bit Pattern:
00010100
7
(A)
Operation:
0
+-
(A)-1
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction decrements the contents of the accumulator by 1.
It places the result in the accumulator.
DEC A
Example:
; Decrement accumulator
Encoded Instruction:
00010100
7
o
Before
After
Accumulator
Accumulator
11010000
11001111
7
7
0
0
Note: 5
3-41
MCS-Sl
DEC
Decrement Register
Mnemonic:
DEC
Operands:
Rr
Format:
DEC Rr
Register 0 <= r
<= 7
Bit Pattern:
00011rrr
7
Operation:
(Rr)
0
4-
(Rr) -1
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction decrements the contents of register r by 1. It places
the result in the specified register.
Example:
DEC Rl
; Decrement register 7
~ncoded Instruction:
100011111
7
o
Before
After
Register 7
Register 7
10101011
10101010
7
7
0
Notes: None
3-42
I
0
MeS-51
DEC
Decrement Memory
Mnemonic:
DEC
Operands:
data address
Format:
DEC data address
0 <= data address
<= 255
Bit Pattern:
1 0001 01 01 1Data Address 1
7
0
(data address)
Operation:
7
~
0
(data address \ -1
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS·,
....'" OV
p
PSW
Description:
This instruction decrements the contents of the specified data
address by 1. It places the result in the addressed location.
Example:
DEC 37H
; Decrement counter
Encoded Instruction:
1 00010101
7
0
00110111
7
0
Before
After
(37H)
(37H)
111011110
111011101
7
0
7
0
Note: 9
3-43
MeS-51
DIV
Divide Accumulator by B
Mnemonic:
OIV
Operands:
AB
Format:
OIV AB
Register Pair
Bit Pattern:
10000100
7
0
(AB) +- (A) I (B)
Operation:
Bytes: 1
Cycles: 4
Flags:
C
AC
FO RS1 RSO OV
I-I
p
I. I-I I-I
PSW
Description: . This instruction divides the contents of the accumulator by the
contents of the multiplication register (B). Both operands are
treated as unsigned integers. The accumulator contains the quotient; the multiplication register contains the remainder.
The carry flag is always cleared. Division by 0 sets the overflow
flag; otherwise, it is cleared.
Example:
MOVB,'5
DIV AB
; Divide accumulator by 5
Encoded Instruction:
10000100
7
Before
After
Accumulator
Accumulator
01110110
100010111
7
0
7
0
Multiplication Register (B)
Multiplication Register (B)
I 00000101 I
I 00000011 I
7
Note: 5
3-44
o
0
7
0
DJNZ
MCS-Sl
Decrement Register and Jump if Not Zero
DJNZ
Rr
Register 0 <= r
code address
DJNZ Rr,codeaddress
Mnemonic:
Operands:
Format:
Bit Pattern:
I 1 1 0 11 r r r I
7
0
<= 7
ReI. Offset
7
0
(PC) +- (PC) + 2
(Rr) +- (Rr) -1
IF (Rr) <>0
THEN
(PC) +- (PC) + relative offset
Operation:
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction decrements the contents of register r by 1, and
places the result in the specified register. If the result of the decrement is 0, then control passes to the next sequential instruction;
otherwise. control passes to the specified code address.
The Program Counter is incremented to the next instruction. If the
decrement does not result in O. then the relative offset is added to
the incremented program counter, and the instruction at that
address is executed.
; ADD index to accumulator
LOOP1: ADD A,R7
Example:
.
; Decrement register 7 and
; jump to LOOP1 (15 bytes
; backward from INC
; instruction)
DJNZ R7,LOOP1
INCA
Encoded Instruction:
111011111
7
11110001
0
7
0
Before
After
Register 7
Register 7
100000010
7
I
I 00000001
o
Program Counter
Program Counter
100000100 111011100
15
8
7
Notes: 10, II, 12
o
7
0
I
100000100 111001111
15
8
7
0
3-45
DJNZ
MCS~51
Decrement Memory and Jump if Not Zero
Mnemonic:
DJNZ
Operands:
data address 0 <= data address
code address
Format:
DJNZ data address ,code address
Bit Pattern:
11 01 01 01
7
Operation:
IData Address I
0
(PC) - (PC)
7
0
<= 255
ReI. Offset
7
0
+3
(data address) - (data address) -1
IF (data address) < > 0
THEN
(PC) - (PC)
+ relative offset
Bytes: 3
Cycles: 2,
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction decrements the contents of the specified data
address by 1, and places the result in the addressed location. If the
result of the decrement is 0, then control passes to the next sequen~
tial instruction; otherwise, control passes to the specified code
address.
The Program Counter is incremented to the next instruction. If the
decrement does not result in 0, then the relative offset is added to
the incremented program counter, and the instruction at that
address is executed.
3-46
DJNZ
MeS-51
LOOP 3: MOV R7,57H
Example:
; Store loop index in register 7
DJNZ 57H,LOOP3 ; Decrement 57H and jump
INC A
; backward to LOOP3 (51 bytes
; backwards from the INC A
; instruction)
Encoded Instruction:
111010101101010111 111001010 1
7
0
7
0
7
0
Before
After
(57H)
(57H)
101110111
101110110 1
7
7
0
Program Counter
0
Program Counter
1 00000000 111011100 1 1 00000000 110101001
15
8
7
o
15
8
7
o
Notes: 9, 10, 11, 12
3-47
MeS-51
INC
Increment Indirect Address
Mnemonic:
INC
Operands:
Rr
Format:
INC@Rr
Register 0 <= r <= 1
Bit Pattern:
1 0000011r 1
7
0
«Rr)) +- «Rr» + 1
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction increments the contents of the memory location
addressed by register r by 1. It places the result in the addressed
location.
Example:
INC@RO
; Increment counter
Encoded Instruction:
100000110
7
0
Before
After
RegisterO
Register 0
100110010
7
0
(32H)
7
Note: 15
I
100110010
7
0
(32H)
111011101
3-48
I
0
11011110
7
0
I
INC
MeS-51
Increment Accumulator
Mnemonic:
INC
Operands:
A
Format:
INC A
Bit Pattern:
Accumulator
I 00000100 I
7
Operation:
0
(A) -(A)
+1
Bytes: 1
Cycles: 1
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction increments the contents of the accumulator by 1. It
places the result in the accumulator.
Example:
INC A
; Increment accumulator
Encoded Instruction:
I 00000100 I
7
0
Before
After
Accumulator
Accumulator
11010000
11010001
7
7
0
0
Note: 5
3-49
MeS-51
INC
Increment Data Pointer
Mnemonic:
INC
Operands:
DPTR
Format:
INC DPTR
Data Pointer
Bit Pattern:
110100011
7
0
(DPTR) +- (DPTR) + 1
Operation:
Bytes: 1
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction increments the 16-bit contents of the data pointer
by I. It places the result inthe data pointer.
Example:
INC DPTR
; Increment data pOinter
"
Encoded Instruction:
1101000111
7
Before
°
After
Data Pointer
Data Pointer
°
1 000 1 001 1 11111111 1 1-1_00_0_0_1_0_1_0.....1_o_o_0_0_00_0_0--,1
15
8
Notes: None
3·50
7
°
15
8
7
0
Mes-sl
INC
Increment Register
Mnemonic:
INC
Operands:
Rr
Format:
INC Rr
Register 0 <= r
<= 7
Bit Pattern:
1 00001rrr 1
7
Operation:
0
(Rr) - (Rr)
+1
Bytes: 1
Cycles: 1
Flags:
C
AC
p
Fa RS1 RSO OV
PSW
Description:
This instruction increments the contents of register r by 1. It places
the result in the specified register.
Example:
INC R7
; Increment register 7
j,~
Encoded Instruction:
1000011111
7
0
Before
After
Register 7
Register 7
110101011
110101100
7
o
7
I
o
Notes: None
3-51
MeS-51
INC
Increment Memory
Mnemonic:
INC
Operands:
data address
Format:
INC data address
0 <= data address <= 255
Bit Pattern:
100000101 1Data Address
7
Operation:
0
7
I
0
(data address) - (data address)
+1
Bytes: 2
Cycles: I
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction increments the contents of the specified data
address by 1. It places the result in the addressed location.
Example:
INC 37H
; Increment 37H
it
Encoded Instruction:
100000101 100110111
7
o
o
Before
After
(37H)
(37H)
111011110
7
Note: 9
3-52
7
0
I
111011111
7
0
JB
MCS-Sl
Jump if Bit Is Set
Mnemonic:
JB
Operands:
bit address
0 <= bit address
code address
Format:
JB bit address ,code address
<= 255
Bit Pattern:
Operation:
00100000
Bit Address
ReI. Offset
7
7
7
(PC)
0
+-
(PC)
0
0
+3
IF (bit address) = 1
THEN
(PC)
+-
(PC)
+ relative offset
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction tests the specified bit address. If it is I, control
passes to the specified code address. Otherwise, control passes to
the next sequential instruction.
The Program Counter is incremented to the next instruction. If the
test was successful, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-53
MeS-51
JB
JB 39.6, EXIT
Example:
; Jump if bit 6 of byte 39 is 1
SJMPTOP
EXIT: MOV A,39
; Move 39 to accumulator (EXIT label
; is 5 bytes from jump statement) .
Encoded Instruction:
I 00100000 I 00111110 I 00000010 I
7
o
7
o
Before
After
(39)
(39)
101110111
101110111
76
o
76
Program Counter
15
8
Notes: 10, 11, 12
7
o
Program Counter
1 00000000 111011100
3-54
o
7
0
I I 00000000
15
8
111100001
7
0
MeS-51
JBC
Jump and Clear if Bit Is Set
Mnemonic:
JBC
Operands:
bit address
0 <= bit address
code address
Format:
J BC bit address ,code address
<= 255
Bit Pattern:
Operation:
00010000
Bit Address
Rei. Offset
7
7
7
(PC)
0
+-
(PC)
0
+3
IF (bit address) = 1
THEN
(bit address)
(PC)
0
+-
(PC)
+-
0
+ relative offset
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
This instruction tests the specified bit address. If it is I, the bit is
cleared, and control passes to the specified code address. Otherwise, control passes to the next sequential instruction.
The Program Counter is incremented to the next instruction. If the
test was successful, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-55
MeS-51
JBC
Example:
ORGODCH
JBC 4B.1,OUT3 ; Test bit 1 of byte 46
; jump and clear if 1
ORG136H
OUT3: INCR7
Encoded Instruction:
100010000 101110001 101010111
70707
Before
After
(46)
(46)
101110111
7
I
101110101
10
Program Counter
100000000 111011100
15
8
Notes: 10,11,12
10
7
Program Counter
3-56
0
7
0
I
1 00000001
15
8
I 00110110 I
7
0
JC
MCS-Sl
Jump if Carry Is Set
Mnemonic:
JC
Operands:
code address
Format:
JC code address
Bit Pattern:
Rei. Offset
01000000
0
7
Operation:
(PC) +- (PC)
IF (C) = 1
7
+2
THEN
(PC)
0
+-
(PC)
+ relative code
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction tests the contents of the carry flag. If it is 1, then
control passes to the specified code address. Otherwise, control
passes to the next sequential instruction.
The Program Counter is incremented to the next instruction. If the
test was successful, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-57
MeS-51
JC
Example:
; Clear carry
FIXUP: CLR C
; If carry is 1 go to FIXUP
; 49 bytes backwards from the JC
; instruction
JCFIXUP
Encoded Instruction:
101000000111001101
7
o
7
o
Before
After
Carry Flag
Carry Flag
[TI
[TI
Program Counter
Program Counter
1000001011110111001 100000101110101011
15
8
Notes: 10, 11, 12
3-58
7
o
15
8
7
o
MeS-51
JMP
Generic Jump
Mnemonic:
JMP
Operands:
code address 0 <= code address
Format:
JMP code address
Bit Pattern:
Translated to AJMP, LJMP, or SJMP, as needed
Operation:
Either AJMP, SJMP or LJMP
<= 65,535
Bytes:
Cycles:
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction will be translated to SJMP if the specified code
address contains no forward references and that address falls
within -128 and +127 of the address of the next instruction. It will
be translated to AJMP if the code address contains no forward
references and the specified code address falls within the current 2K
byte page. Otherwise, the JMP instruction is translated to LJMP.
If forward references are used to specify the jump destination, then
it will not necessarily be the most efficient representation. See the
descriptions for SJMP, AJMP, and LJMP for more detail.
Example:
JMPSKIP
FF:
INCA
SKIP: INCRS
; Jump to SKIP
; Increment A
; Increment register 5
Encoded Instruction:
00000010
7
o
00000100
7
10101011
o
o
7
Before
After
Program Counter
Program Counter
00000100
10100111
15
7
8
0
I
100000100
15
8
10101011
7
0
Notes: None
3-59
MCS-Sl
JMP
Jump to Sum of Accumulator and Data Pointer
Mnemonic:
JMP
Operands:
A
DPTR
Format:
JMP@A+DPTR
Accumulator
Data Pointer
Bit Pattern:
101110011 ,
7
Operation:
0
(PC) +- (A) + (DPTR)
Bytes: 1
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction adds the contents of the accumulator with the
contents of the data pointer. It transfers control to the code address
formed by that sum.
Example:
JMP@A+DPTR
; Jump relative to the accumulator
Encoded Instruction:
101110011 ,
7
o
Before
After
Accumulator
Accumulator
101110110
7
I
101110110
7
o
o
Data Pointer
1 0 0000 01 0 1 1 01 01 0 00
15
8
7
I
o
Notes: None
3-60
7
'-1-00-0-0-0-0-1-0-r"1-1-0-1-0-10-0-0--',
8
7
o
Program Counter
111001101 100001101
8
Data Pointer
15
Program Counter
15
I
0
I
100000011100011110
15
8
7
o
I
JNB
MeS-51
Jump if Bit Is Not Set
Mnemonic:
JNB
Operands:
bit address
code address
Format:
JNB bitaddress,codeaddress
Bit Pattern:
00110000
7
0
Operation:
(PC)
+-
(PC)
Bit Address
7
Rei. Offset
7
0
0
+3
IF (bit address) = 0
THEN
(PC)
+-
(PC)
+ relative offset
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction tests the specified bit address. If it is 0, control
passes to specified code address. Otherwise, control passes to the
next sequential instruction.
The Program Counter is incremented to the next instruction. If the
test was successful, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-61
MCS-51
JNB
ORGODCH
JNB 41.6, EXIT
Example:
EXIT:
; If bit 6 of byte 41 is 0 go to EXIT
ADD A,41
; At location 136H
Encoded Instruction:
100110000 101001110 101010111
7
o
7
o
Before
After
(41 )
(41 )
100110111
100110111
76
o
76
Program Counter
15
8
Notes: 10, 11, 12
7
o
Program Counter
100000000111011100
3-62
o
7
o
I
100000001 100110110
15
8
7
o
I
MeS-51
JNC
Jump if Carry Is Not Set
Mnemonic:
JNC
Operands:
code address
Format:
JNC code address
Bit Pattern:
Operation:
01010000
Rei. Offset
7
7
0
(PC) - (PC)
IF (C) = 0
THEN
0
+2
(PC) - (PC)
+ relative offset
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction tests the contents of tile carry flag. If it is 0, control
passes to the specified code address. Otherwise, control passes to
the next sequential instruction.
The Program Counter is incremented to the next instruction. If the
test was successful, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-63
MeS-51
JNC
FIXUP:
Example:
MOV A,R5
JNC FIXUP
; Jump to FIXUP if carry is 0
; (51 bytes backwards)
Encoded Instruction:
101010000 111001101
7
o
7
Before
After
Carry Flag
Carry Flag
IT]
IT]
Program Counter
Program Counter
I 000111 00
I 000111 00
15
1 11 0111 00 1
8
Notes: 10, 11, 12
3-64
o
7
0
15
8
1 1 01 01 011
7
0
JNZ
MCS-Sl
Jump if Accumulator Is Not Zero
Mnemonic:
JNZ
Operands:
code address
Format:
JNZ code address
Bit Pattern:
Operation:
01110000
Rei. Offset
7
7
0
(PC) +- (PC) + 2
IF (A) < > 0
THEN
(PC) +- (PC)
0
+ relative offset
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Oescription:
This instruction tests the accumulator. If it is not equal to 0,
control passes to the specified code address. Otherwise, control
passes to the next sequential instruction.
The Program Counter is incremented to the next instruction. If the
accumulator is not 0, then the relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-65
MeS·51
JNZ
JNZTEST
Example:
TEST:
; Jump if accumulator is not 0
; n bytes forward
MOV R3,A
Encoded Instruction:
101110000 101001101
7
o
7
o
Before
After
Accumulator
Accumulator
101110111
7
I
101110111
7
8
Program Counter
0
Program Counter
1 00000000 111011100 1 1 00000001 1 00101011
15
8
Notes: 10,11,12
3-66
7
0
15
8
7
0
JZ
MCS-51
Jump if Accumulator Is Zero
Mnemonic:
JZ
Operands:
code address
Format:
JZ code address
Bit Pattern:
Operation:
01100000
ReI. Offset
7
7
0
(PC) -- (PC)
IF (A) = 0
0
+2
THEN
(PC)
+-
(PC)
+ relative offset
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction tests the accumulator. If it is 0, control passes to
the specified code address. Otherwise, control passes to the next
sequential instruction.
The Program Counter is incremented to the next instruction. If the
accumulator is 0, then tht relative offset is added to the
incremented program counter, and the instruction at that address is
executed.
3-67
JZ
MeS-51
JZ EMPTY
Example:
; Jump to EMPTY if accumulator is 0
; 25 bytes from JZ instruction
EMPTY: INCA
Encoded Instruction:
101100000 100010111
707
0
Before
After
Accumulator
Accumulator
101110110 1
101110110 1
7
o
o
7
Program Counter
Program Counter
100001111 111011100 1 100001111 111011110 1
15
8
7
o
15
8
7
o
Notes: 10,11,12
(
~
3-68
MeS-51
LCALL
Long Call
Mnemonic:
LCALL
Operands:
code address 0 <= code address
Format:
LCALL code address
Bit Pattern:
I 00010010
7
Operation:
<= 65,535
\COde Addr. highlCode Addr.low
07
07
I
0
(PC) - (PC) + 3
(SP) 4- (SP) + 1
((SP)) 4- (PC low)
(SP) 4- (SP) + 1
((SP)) +- (PC high)
(PC) 4- code address
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction stores the contents of the program counter (the
return address) on the stack, then transfers control to the 16-bit
code address specified as the operand.
3-69
MCS-51
lCAll
Example:
SERVICE:
INC A
; Resides at location 233H
RETI
ORG80 DCH
LCALL SERVICE ; Call SERVICE
Encoded Instruction:
I 00010010 I 00000010 I 00110011
7
o
7
o
o
7
Before
After
Program Counter
Program Counter
1100000001110111001
100000010
15
8
7
0
15
8
Stack Pointer
Stack Pointer
1001010001
100101010 1
7
0
7
(29H)
1011101111
1110111111
o
7
(2AH)
100000000 1
1 1 0000000 1
0
7
0
o
(2AH)
7
7
0
(29H)
7
00110011
0
Notes: 1,2, 3
~
..
3-70
LJMP
MCS-Sl
Long Jump
Mnemonic:
LJMP
Operands:
code address 0 <= code address
Format:
LJMP code address
Bit Pattern:
I 0000001 0
7
Operation:
FOde Addr. highlCode Addr.low I
0 7
(PC)
+-
C
AC
<= 65,535
07
0
code address
Bytes: 3
Cycles: 2
Flags:
FO RS1 RSO OV
p
PSW
Description:
This instruction transfers control to the 16-bit code address
specified as the operand.
Example:
ORG 800H
LJMPFAR
; Jumpto FAR
FAR: INCA
; Current code location (8233H)
Encoded Instruction:
I 00000010
7
0
10000010
00110011
7
7
0
0
Before
After
Program Counter
Program Counter
00001000
15
8
I 00000000 I
7
0
110000010 1 00110011
15
8
7
0
Notes: None
3-71
MCS-Sl
MOV
Move Immediate Data to Indirect Address
Mnemonic:
MOV
Operands:
Rr
data
Format:
MOV @Rr,#data
Register 0 <= r <= 1
-256 <= data <= + 255
Bit Pattern:
Operation:
0111 011
r
Ilmmediate Datal
7
0
7
((Rr»
+-
0
data
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO
ov
p
P$W
Description:
This instruction moves the 8-bit immediate data value to the
memory location addressed by the contents of register r.
Example:
MOV @R1,#01H
; Move 1 to indirect address
Encoded Instruction:
I 01110111
7
o
7
o
Before
After
Register 1
Register 1
00010011
7
0
(13H)
7
I 00010011
7
0
(i3H)
101110111
0
Notes: 4,15
3-72
00000001
00000001
7
0
MeS-51
MOV
Move Accumulator to Indirect Address
Mnemonic:
MOV
Operands:
Rr
A
Format:
MOV@Rr,A
Register 0 <= r <= 1
Accumulator
Bit Pattern:
11111011r
7
0
((Rr»
Operation:
+-
(A)
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the accumulator to the
memory location addressed by the contents of register r.
,Example:
MOV@RO,A
; Move accumulator to indirect
; address
Encoded Instruction:
111110110 1
7
0
Before
After
Register 0
Register 0
00111000
00111000
7
7
0
0
(38H)
(38H)
110011001
1010011001
7
0
Accumulator
01001100
7
0
7
0
Accumulator
1010011§ij
7
0
Note: 15
3-73
MeS-51
MOV
Move Memory to Indirect Address
Mnemonic:
MOV
Operands:
Rr
data address
Format:
MOV @Rr,dataaddress
Register 0 <= r<= 1
0 <= data address <= 255
Bit Pattern:
\ 1 01 0011 r \ Data Address
o
7
Operation:
((Rr))
~
I
o
7
(data address)
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the specified data address to
the memory location addressed by the contents of register r.
Example:
MOV@R1,77H
; Move the contents of 77H to indirect
; address
Encoded Instruction:
01110111
\10100111
7
0
0
Before
After
Register 1
Register 1
100001000
7
0
I
1 00001000
7
0
(08H)
(08H)
\ 00110011
111111110
7
0
7
0
(77H)
(77H)
111111110
111111110
7
Notes: 8,15
3-74
7
0
7
0
I
MCS-Sl
MOV
Move Immediate Data to Accumulator
Mnemonic:
MOV
Operands:
A
data
Format:
MOV A,#data
Accumulator
-256 <= data <= + 255
Bit Pattern:
I 0111 01 00 Ilmmediate Datal
7
Operation:
(A)
0
+-
7
0
data
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the 8-bit immediate data value to the
accumulator.
~xample:
MOVA,#01H
; Initialize the accumulator to 1
Encoded Instruction:
101110100
7
0
00000001
7
0
Before
After
Accumulator
Accumulator
00100110
00000001
7
7
0
0
Notes: 4,5
3-75
MOV
MCS-Sl
Move Indirect Address to Accumulator
Mnemonic:
MOV
Operands:
A
Accumulator
Register 0 <= r <= 1
Rr
MOVA,@Rr
Format:
Bit Pattern:
11110011r
7
Operation:
(A)
1
0
+-
«Rr»
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the data memory location
addressed by register r to the accumulator.
Example:
MOVA,@R1
; Move indirect address to
; accumulator
Encoded Instruction:
111100111
7
I
o
Before
After
Accumulator
Accumulator
110000110
7
I
o
7
100011100
I
0
o
Notes: 5,15
I
0
(1CH)
111101000
7
100011100
7
(1CH)
3-76
I
Register 1
Register 1
7
111101000
0
I
111101000
7
0
I
MOV
MeS-51
Move Register to Accumulator
Mnemonic:
MOV
Operands:
A
Accumulator
Register 0 <= r
Rr
<= 7
MOV A,Rr
Format:
Bit Pattern:
111101rrr
7
Operation:
(A)
0
+-
(Rr)
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of register r to the
accumulator.
Example:
MOV A,R6
; Move R6 to accumulator
Encoded Instruction:
111101110
7
I
0
Before
After
Accumulator
Accumulator
100101110
7
o
110000101
7
o
Register 6
Register 6
110000101
7
I
0
10000101
7
0
Note: 5
3-77
MeS-51
MOV
Move Memory to Accumulator
Mnemonic:
MOV
Operands:
A
data address
Format:
MOV A,data address
Bit Pattern:
I 111 00 1 01 IData Address I
o
7
Operation:
Accumulator
0 <= data address <= 255
o
7
(A) - (data address)
Bytes: 2
Cycles: 1
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of data memory at the specified
address to the accumulator.
Example:
MOVA,P1
; Move the contents of Port 1 to
; accumulator
Encoded Instruction:
111100101110010000
7
o
7
o
Before
After
Accumulator
Accumulator
[00100110
7
I
Notes: 5,8
0
Port I (90H)
101111001
7
J 01111001
7
0
Port I (90H)
3-78
I
o
I
101111001
7
o
MCS-Sl
MOV
Move Bit to Carry Flag
Mnemonic:
MOV
Operands:
C
bit address
Format:
MOV C,bit address
Carry Flag
0 <= bit address
<= 255
Bit Pattern:
1 1 01 0001 0 1 Bit Address 1
707
0
(C) .- (bit address)
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the specified bit address to
the carry flag.
Example:
MOVC,TXD
; Move the contents of TXD to Carry
; flag
Encoded Instruction:
110100010
7
0
10110110
7
0
Before
After
Port 3 (BOH)
Port 3 (BOH)
1001000101
1001000101
76
0
76
Carry Flag
Carry Flag
OJ
IT]
0
Notes: None
3-79
MeS-51
MOV
Move Immediate Data to Data Pointer
Mnemonic:
MOV
Operands:
Data Pointer
data
Format:
MOV DPTR,ldata
0 <= data
<= 65,535
Bit Pattern:
1 1 001 0000 llmm. Data high 1 Imm. Data low
7
Operation:
7
0
0 7
I
0
(DPTR) - data
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction moves the 16-bit immediate data value to the data
pointer.
Example:
MOV DPTR,IOF4FH
; Initialize the data pOinter to OF4FH
Encoded Instruction:
110010000 100001111
7
o
7
01001111
o
Before
After
Data Pointer
Data Pointer
100000000 111011100
15
8
Notes: None
3-80
o
7
7
o
I
100001111 101001111
15
8
7
o
(
\;
MCS-Sl
MOV
Move Immediate Data to Register
Mnemonic:
MOV
Operands:
Rr
data
Format:
MOV Rr,Idata
Register 0 <= r <= 7
-256 <= data <= + 255
Bit Pattern:
I 01111 r r r Ilmmediate Datal
7
0 7
0
(Rr) -data
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the 8-bit immediate data value to register r.
~xample:
MOVR5,101H
; Initialize register 1
Encoded Instruction:
I 0 111 \11 0 1 I 0 0 0 0 0 0 0 1
7
'
0
7
0
Before
After
Register 5
Register 5
I 00010011
I 00000001
7
o
7
o
Note: 4
3-81
MeS-51
MOV
Move Accumulator to Register
Mnemonic:
MOV
Operands:
Rr
A
Format:
MOVRr,A
Register 0 <= r
Accumulator
<= 7
Bit Pattern:
111111(rr
7
Operation:
0
(Rr)
+-
C
AC
(A)
Bytes: 1
Cycles: 1
Flags:
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the accumulator to register I.
-Example:
MOVR7,A
; Move accumulator to register 7
Encoded Instruction:
1111111111
7
o
Before
After
Register 7
Register 7
111011100
7
o
00111000
7
o
Accumulator
Accumulator
100111000 )
100111000 J
7
o
Notes: None
3-82
I
7
o
MOV
MeS-51
Move Memory to Register
Mnemonic:
MOV
Operands:
Rr
data address
Format:
MOV Rr,data address
Register 0 <= r
<= 7
0 <= data address <= 255
Bit Pattern:
1 1 0 1 0 1 r r r 1Data Address 1
o
7
Operation:
o
7
(Rr) - (data address)
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the specified data address to
register T.
Example:
MOVR4,69H
; Move contents of 69H to register 4
Encoded Instruction:
110101100101101001
7
o
7
o
Before
After
Register 4
Register 4
100001010 1
111011000 1
7
o
7
o
(69H)
(69H)
111011000
7
o
I
IT1'-0-1-1-00-0--'1
7
o
Note: 8
3-83
MeS-51
MOV
Move Carry Flag to Bit
Mnemonic:
MOV
Operands:
bit address
C
Format:
MOV bitaddress,C
0 <= bit address <= 255
Carry Flag
Bit Pattern:
110010010 1 Bit Address
707
Operation:
I
0
(bit address) - (C)
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the carry flag to the
specified bit address.
Example:
MOV2FH.7,C
; Move C to bit address 7FH
Encoded Instruction:
110010010 101111111
7
o
o
Before
After
(2FH)
(2FH)
100100110
7
o
I
110100110 1
7
o
Carry Flag
Carry Flag
I1 I
Ii I
Notes: None
3-84
7
MOV
MCS-Sl
Move Immediate Data to Memory
Mnemonic:
MOV
Operands:
data address
data
Format:
MOV data address ,*data
Bit Pattern:
I 01110101
7
Operation:
0 <= data address <= 255
-256 <= data <= + 255
IData Address Ilmmediate Datal
07
07
0
(data address) - data
Bytes: 3
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the 8-bit immediate data value to the
specified data address.
Example:
MOV TMOD,#01 H
; Initialize Timer Mode to 1
Encoded Instruction:
I 01110101
7
0
110001001
7
0
I 00000001
7
0
Before
After
TMOD(89H)
TMOD(89H)
101110111
I 00000001
7
0
7
0
Notes: 4,9
3-85
MCS-Sl
MOV
Move Indirect Address to Memory
Mnemonic:
MOV
Operands:
data address
Rr
Format:
MOV data address ,@Rr
Bit Pattern:
11000011
7
Operation:
0 <= data address <= 255
Register 0 <= r <= 1
r . 1Data Address I
0
(data address)
7
+-
0
«Rr))
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of memory at the location
addressed by register r to the specified data address.
Example:
MOV11H,@R1
; Move indirect address to 11H
Encoded Instruction:
110000111
7
I 00010001
o
7
Before
After
(11H)
(11 H)
110100101
110010110
7
o
7
Register 1
1 010110001
101011000
o
7
(10010110
Notes: 9,15
I
o
(58H)
(58H)
7
I
o
Register 1
7
3-86
o
0
I
110010110
7
0
I
MCS-Sl
MOV
Move Accumulator to Memory
Mnemonic:
MOV
Operands:
data address
A
Format:
MOV data address ,A
0 <= data address
Accumulator
<= 255
Bit Pattern:
11 1 1 0 1 0 1 1Data Address 1
7
0
(data address)
Operation:
7
+-
0
(A)
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the accumulator to the
specified data address.
Example:
MOV45H,A
; Move accumulator to 45H
Encoded Instruction:
111110101
7
o
01000101
7
o
Before
After
(45H)
(45H)
110111101
110011001
7
0
7
0
Accumulator
Accumulator
110011001
110011001
7
o
7
o
Note: 9
3-87
MCS-Sl
MOV
Move Register to Memory
Mnemonic:
MOV
Operands:
data address
Rr
Format:
MOV data address, Rr
Bit Pattern:
1 10001 r r r
7
0 <= data address
Register 0 <= r
<= 255
<= 7
IData Address 1
0
7
0
(data address) +- (Rr)
Operation:
Bytes: 2
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction moves the contents of register r to the specified
data address.
Example:
MOV7EH,R3
; Move R3 to location 7EH
Encoded Instruction:
110001011 101111110 1
7
o
7
o
Before
After
(7EH)
(7EH)
111110111
110010110 1
7
0
7
0
Register 3
110010110 1
7
Note: 9
3-88
o
110010110
7
o
I
MOV
MCS-Sl
Move Memory to Memory
Mnemonic:
MOV
Operands:
data address1
data address2
Format:
MOV data address 1,data address2
0<= data address1 <= 255
0<= data address2 <= 255
Bit Pattern:
1 10000101 IData Address21Data Address11
7
0 7
(data address1)
Operation:
07
+-
0
(data address2)
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction moves the contents of the source data address
(data address2) to the destination data address (data addressJ).
Example:
MOVB,12H
; Move the contents of 12H to B (FOH)
Encoded Instruction:
110000101
7
0
00010010
11110000
7
7
0
0
Before
After
(12H)
(12H)
111100101
111100101
7
0
7
0
(FOH)
(FOH)
101011101
111100101
7
0
7
0
Note: 16
3-89
Move
MCS-Sl
Move Code Memory Offset from Data Pointer
to Accumulator
Mnemonic:
MOVe
Operands:
A
DPTR
Format:
Move A,@A+DPTR
Accumulator
Data Pointer
Bit Pattern:
1100100111
7
Operation:
0
(A) - «A) + (DPTR))
Bytes: 1
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction adds the contents of the data pointer with the
contents of the accumulator. It uses that sum as an address into
code memory and places the contents of that address in the
accumulator.
The high-order byte of the sum moves to Port 2 and the low-order
byte of the sum moves to Port o.
MOVe A,@A + DPTR
Example:
; Look up value in table
Encoded Instruction:
110000011
7
I
0
Before
After
Accumulator
Accumulator
00010001
100011110
7
o
7
Data Pointer
I
o
Data Pointer
100000010111110001 1 1 00000010 1 11110001
15
8 7
0
15
8 7
0
(0302H)
(0302H)
100011110
7
Notes: 5
3-90
0
I
100011110
7
0
I
Move
MeS-51
Move Code Memory Offset from Program
Counter to Accumulator
Mnemonic:
MOVC
Operands:
A
Accumulator
Program Counter
PC
Format:
MOVCA,@A+PC
Bit Pattern:
10000011
7
Operation:
0
(PC) - (PC) + 1
(A) - «A) + (PC»
Bytes: 1
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
p
I-I
PSW
Description:
This instruction adds the contents of the incremented program
counter with the contents of the accumulator. It uses that sum as an
address into code memory and places the contents of that address
in the accumulator.
The high-order byte of the sum moves to Port 2 and the low-order
byte of the sum moves to Port O.
3-91
Move
MeS-51
; Look up value in table
MOVCA,@A+PC
Example:
Encoded Instruction:
110000011
7
I
0
Before
After
Accumulator
Accumulator
101110110
7
I
o
I
o
7
Program Counter
Program Counter
1 00000010 1 00110001
1 00000010
15
8
7
101011000
7
15
0
8
(02A8H)
(02A8H)
0
Notes: 5,12
3-92
101011000
I
101011000
7
0
I
I 00110010 I
7
0
MOVX
MCS-Sl
Move Accumulator to External Memory
Addressed by Data Pointer
Mnemonic:
MOVX
Operands:
Data Pointer
Accumulator
DPTR
A
MOVX @DPTR,A
Format:
Bit Pattern:
111110000 1
7
Operation:
0
«DPTR» - (A)
Bytes: 1
Cycles: 2
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the accumulator to the
off-chip data memory location addressed by the contents of the
data pointer.
The high-order byte of the Data Pointer moves to Port 2, and the
low-order byte of the Data Pointer moves to Port O.
Example:
; Move accumulator at data pointer
MOVX @DPTR,A
Encoded Instruction:
111110000 1
7
o
Before
After
Data Pointer
Data Pointer
1 00110000 1 00110011
100110000 100110011
15
8
7
0
15
8
(3033H)
(3033H)
111111001
1010011001
7
o
7
Accumulator
101001100 1
1010011001
7
0
0
o
o
Accumulator
7
7
Notes: None
3-93
MeS-51
MOVX
Move Accumulator to External.Memory
Addressed by Register
Mnemonic:
Operands:
MOVX
Register 0 <= r <= 1
Accumulator
Rr
A
Format:
MOVX@Rr,A
Bit Pattern:
1111001r
7
Operation:
0
«Rr» -
(A)
Bytes: 1
Cycles: 2
Flags:
C
AC
FO RS1 RSO OV
p
PSW
3-94
Description:
This instruction moves the contents of the accumulator to the offchip data memory location addressed by the contents of register r,
and special function register P2. P2 holds the high order byte of the
address and register r holds the low order byte.
Example:
MOV P2,IO
MOVX@RO,A
; Move accumulator to indirect
; address
MOVX
MeS-51
MOV P2,#0
Example:
; Move accumulator to indirect
; address
MOVX@RO,A
Encoded Instruction:
\11100010 \
7
0
Before
After
Register 0
Register 0
110111000
7
I
7
0
110011001
I
0
101001100
0
101001100
7
0
I
0
Accumulator
Accumulator
7
I
(00B8H)
(00B8H)
7
110111000
I
101001100
7
I
0
Notes: None
3-95
MCS-Sl
MOVX
Move External Memory Addressed by
Data Pointer to Accumulator
Mnemonic:
MOVX
Operands:
A
Accumulator
Data Pointer
DPTR
Format:
MOVX A.@DPTR
Bit Pattern:
I
111100000
7
0
Operation:
(A) - «DPTR»
Bytes: 1
Cycles: 2
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction moves the contents of the off-chip data memory
location addressed by the data pointer to the accumulator.
The high-order byte of the Data Pointer moves to Port 2, and the
low-order byte of the Data Pointer moves to Port o.
Example:
MOVX A,@DPTR
; Move memory at DPTR to
; accumulator
Encoded Instruction:
111100000
7
I
0
Before
After
Accumulator
Accumulator
110000110
7
I
111101000)
7
o
o
Data Pointer
Data Pointer
101110011 111011100
15
8
7
(73DCH)
Notes: 5
3-96
101110011 111011100
0
15
8
(73DCH)
111101000
7
I
0
I
111101000
7
0
I
7
0
I
MCS-Sl
MOVX
Move External Memory Addressed by
Register to Accumulator
Mnemonic:
MOVX
Operands:
A
Accumulator
Register 0 <= r <= 1
Rr
Format:
MOVXA.@Rr
Bit Pattern:
1110001r
7
Operation:
Bytes:
(A)
0
+-
«Rr))
1
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction moves the contents of the off chip data memory
location addressed by register r, and special function register P2 to
the accumulator. P2 holds the high order byte of the address and
register r holds the low order byte.
3-97
MeS-51
MOVX
MOV P2, #55H
MOVXA,@R1
Example:
; Move memory at R1 to accumulator
Encoded Instruction:
111100011
7
I
o
Before
After
Accumulator
Accumulator
101010100
7
I
7
0
100011100
I
o
100011100
7
I
o
(551CH)
(551CH)
I 00001000 I
I 00001000 I
7
Notes: 5
3-98
0
Register 1
Register 1
7
I 00001000 I
o
7
o
MUL
MeS-51
Multiply Accumulator by B
Mnemonic:
MUL
Operands:
AB
Format:
MULAB
Multiply/Divide operand
Bit Pattern:
10100100
7
Operation:
0
(A B) - (A) * (B)
Bytes: 1
Cycles: 4
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction mUltiplies the contents of the accumulator by the
contents of the multiplication register (B). Both operands are
treated as unsigned values. It places the low-order byte of the result
in the accumulator, and places the high-order byte of the result in
the multiplication register.
The carry flag is always cleared. If the high-order byte of the product is not 0, then the overflow flag is set; otherwise, it is cleared.
3-99
MCS-SI
MUL
; Move 10 to multiplication register
; Multiply accumulator by 10
MOV B,I10
MULAB
Example:
Encoded Instruction:
1101001001
o
7
Before
After
Accumulator
Accumulator
100011111
100110110 1
o
7
7
o
Multiplication Register (B)
100001010
7
I 00000001 I
7
o
Overflow Flag
Overflow Flag
IT]
IT]
Notes: 5
3-100
o
I
Multiplication Register (B)
NOP
MCS-Sl
No Operation
Mnemonic:
NOP
Operands:
None
Format:
NOP
Bit Pattern:
00000000
7
0
No operation
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC FO RS1 RSO OV
P
PSW
Description:
This instruction does absolutely nothing for one cycle. Control
passes to the next sequential instruction.
Example:
NOP
; Pause one cycle
Encoded Instruction:
I 00000000 I
7
0
Notes: None
3-101
MeS-51
ORL
Logical OR Immediate Data to Accumulator
Mnemonic:
ORL
Operands:
A
data
Format:
ORL
Bit Pattern:
I 01000100 IImmediate Datal
Accumulator
-256 <= data <= + 255
A,lIdata
7
(A)
Operation:
0
+-
7
0
(A) OR data
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction ORs the 8-bit immediate data value to the contents
of the accumulator. Bit n of the result is 1 if bit n of either operand
is 1; otherwise bit n is O. It places the result in the accumulator.
Example:
ORL
A,#00001000B
; Set bit 3 to 1
Encoded Instruction:
I 01000100 I 00001000 I
7
7
o
Before
After
Accumulator
Accumulator
01110111
01111111
7
7
Notes: 4,5
3-102
o
0
0
ORL
MCS-Sl
Logical OR Indirect Address to Accumulator
Mnemonic:
ORL
Operands:
A
Accumulator
Register 0 <= r <= 1
Rr
Format:
ORL A,@Rr
Bit Pattern:
I 0100011r I
7
Operation:
0
(A) - (A) OR ((Rr))
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ORs the contents of the memory location
addressed by the contents of register r to the contents of the
accumulator. Bit n of the result is 1 if bit n of either operand is 1;
otherwise bit n is o. It places the result in the accumulator.
Example:
ORL
; Set bit 0 to 1
A,@RO
Encoded Instruction:
101000110
7
I
0
Before
After
Accumulator
Accumulator
100101000
7
0
I
I 00101001
7
0
Register 0
Register 0
101010010
101010010
7
0
(52H)
0
(52H)
I 00000001
7
7
I
0
00000001
7
0
Notes: 5, 15
3-103
MeS-51
ORL
Logical OR Register to Accumulator
Mnemonic:
ORL
Operands:
A
Rr
Format:
ORL A,Rr
Accumulator
Register 0 <= r <= 7
Bit Pattern:
101001rrr
7
0
(A) - (A) OR (Rr)
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ORs the contents of register r to the contents of the
accumulator. Bit n of the result is 1 if bit n of either operand is 1;
otherwise bit n is O. It places the result in the accumulator.
Example:
ORL A,R4
; Set bits 7 and 3 to 1
Encoded Instruction:
1010011001
7
0
Before
After
Accumulator
Accumulator
110010001
110011001
7
o
7
Register 4
Register 4
1100010001
1100010001
7
0
7
Note: 5
3-104
o
0
ORL
MCS-51
Logical OR Memory to Accumulator
Mnemonic:
ORL
Operands:
A
data address
Format:
ORL A,data address
Accumulator
0 <= data address
Bit Pattern:
1 01000101 1Data Address
707
<= 255
I
0
(A) -- (A) OR (data address)
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction ORs the contents of the specified data address to
the contents of the accumulator. Bit n of the result is 1 if bit n of
either operand is 1; otherwise bit n is o. It places the result in the
accumulator.
Example:
ORL A,37H
; OR 37H with accumulator
Encoded Instruction:
101000101100110111
7
o
7
o
Before
After
Accumulator
Accumulator
101110111
111110111
7
o
7
(37H)
(37H)
110000000
7
o
0
I
110000000
7
0
Notes: 5,8
3-105
MeS-51
ORL
Logical OR Bit to Carry Flag
Mnemonic:
ORL
Operands:
C
bit address
Format:
ORL C,bit address
Bit Pattern:
I 0111 001 0 I Bit Address I
o
7
Operation:
(C)
Carry Flag
0 <= bit address
+-
<= 255
o
7
(C) OR (bit address)
Bytes: 2
Cycles: 2
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ORs the contents of the specified bit address with
the contents of the carry flag. The carry flag becomes 1 when either
the carry flag or the specified bit address is 1; otherwise, it is O. It
places the result in the carry flag.
Example:
ORLC,46.2
; OR bit 2 of byte 46 with Carry
Encoded Instruction:
01110010
101110010
7
0
0
Before
After
Carry Flag
Carry Flag
IT]
[i]
(46)
(46)
100100110
720
Notes: None
3·106
7
I
I 00100110
720
MeS-51
ORL
Logical OR Complement of Bit to Carry Flag
Mnemonic:
ORL
Operands:
C
bit address
Format:
ORL C, I bit address
Bit Pattern:
I 1 01 00000 I Bit Address I
Carry Flag
0 <= bit address
707
Operation:
(C)
+-
<= 255
0
(C) OR NOT bit address
Bytes: 2
Cycles: 2
Flags:
C
p
AC FO RS1 RSO OV
I-I
PSW
Description:
"
This instruction ORs the complemented contents of the specified
bit address to the contents of the carry flag. The carry flag is 1
when either the carry flag is already 1 or the specified bit address is
O. It places the result in the carry flag. The contents of the specified
bit address is unchanged.
Example:
ORL C,I25H.5
; Complement contents of bit 5 in
; byte 25H then OR with Carry
Encoded Instruction:
110100000
7
0
00101101
7
0
Before
After
Carry Flag
Carry Flag
IT]
m
(25H)
(25H)
1000001101
1000001101
7 5
o
7 5
o
Notes: None
3-107
MCS-Sl
ORL
Logical OR Immediate Data to Memory
Mnemonic:
ORL
Operands:
data address
data
Format:
ORL data address ,#data
Bit Pattern:
I 01000011 IData Address IImmediate Datal
7
Operation:
0 <= data address <= 255
-256 <= data <= + 255
07
(data address)
+-
07
0
(data address) OR data
Bytes: 3
Cycles: 2
Flags:
C
AC
FO RS1 RSO
ov
p
I
PSW
Description:
This instruction ORs the 8-bit immediate data value to the contents
of the specified data address. Bit n of the result is 1 if bit n of either
operand is 1; otherwise bit n is O. It places the result in memory at
the specified address.
Example:
ORL 57H,#01H
; Set bit 0 to 1
Encoded Instruction:
101000011 101010111
707
7
Before
After
(57H)
(57H)
101110110
7
Notes: 4,9
3-108
0
00000001
0
I
0
101110111
7
0
MeS-51
ORL
Logical OR Accumulator to Memory
Mnemonic:
ORL
Operands:
data address
A
Format:
ORL data address ,A
Bit Pattern:
o1 0 0 0 0 1 0
7
<= 255
IData Address I
0
(data address)
Operation:
0 <= data address
Accumulator
7
+-
0
(data address) OR A
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction ORs the contents of the accumulator to the
contents of the specified data andress. Bit n of the result is 1 if bit n
of either operand is 1; otherwise bit n is O. It places the result in
memory at the specified address.
Example:
ORL 10H,A
; OR accumulator with the contents
; of 10H
Encoded Instruction:
01000010
I 00010000 I
707
0
Before
After
Accumulator
Accumulator
11110000
11110000
7
7
0
0
(10H)
(10H)
I 00110001
(11110001
7
o
7
o
Note: 9
3-109
POP
MCS-Sl
Pop Stack to Memory
Mnemonic:
POP
Operands:
data address
Format:
POP data address
Bit Pattern:
1 11 01 0000
IData Address I
o
7
Operation:
0 <= data address <= 255
o
7
(data address) - «SP))
(SP) - (SP) -1
Bytes: 2
Cycles: 2
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction places the byte addressed by the stack pointer
at the specified data address. It then decrements the stack pointer
by 1.
Example:
POPPSW
; Pop PSW parity is not affected.
Encoded Instruction:
111010000111010000
7
0
7
0
Before
After
Accumulator
Accumulator
111010101
111010101
7
0
PSW (ODOH)
110101011
7
I
0
PSW (ODOH)
0
111110011
7
0
Stack Pointer
Stack Pointer
7
100010000
7
I
0
111110010
7
0
Notes: 2, 8, 17
100001111
7
(10H)
3·110
I
I
I
I
0
(10H)
111110010
7
0
I
PUSH
MeS-51
Push Memory onto Stack
Mnemonic:
PUSH
Operands:
data address
Format:
PUSH data address
0 <= data address
<= 255
Bit Pattern:
1 11 000000 1Data Address 1
7
0
7
0
(SP) +- (SP) + 1
((SP)) +- (data address)
Operation:
Bytes: 2
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
p
PSW
Description:
This instruction increments the stack pointer, then stores the
contents of the specified data address at the location addressed by
the stack pointer.
Example:
PUSH4DH
; Push one byte to the stack
Encoded Instruction:
111000000 101001101
7
o
7
o
Before
After
(4DH)
(4DH)
110101010 1
110101010
7
0
7
Stack POinter
1 00010000
7
0
Stack Pointer
I
o
1 00010001
7
(11 H)
I
o
(11 H)
1 00000000
7
I
o
I
110101010
7
I
o
Notes: 2, 3, 8
3-111
MeS-51
RET
Return from Subroutine (Non-interrupt)
Mnemonic:
RET
Operands:
None
Format:
RET
Bit Pattern:
00100010
7
Operation:
0
(PC high) +- «SP»
(SP) ... (SP) -1
(PC low) +- «SP»
(SP) ... (SP) -1
Bytes: 1
Cycles: 2
Flags:
C
AC
FO RS1 RSO
ov
P
PSW
Description:
3-112
This instruction returns from a subroutine. Control passes to the
location addressed by the top two bytes on the stack. The highorder byte of the return address is always the first to come off the
stack. It is immediately followed by the low-order byte.
RET
MCS-51
; Return from subroutine
RET
Example:
Encoded Instruction:
100100010
7
I
0
After
Before
Program Counter
Program Counter
I 00000010 I 01010101 I I 00000000 I 01110011
15
8
7
7
15
8
I
o
7
o
(OAH)
I 00000000 I
I 00000000 I
o
7
o
(09H)
(09H)
101110011
"7
0
I 00001000 I
(OAH)
7
7
Stack Pointer
Stack Pointer
100001010
0
0
I
101110011
7
I
0
Notes: 2,17
3-113
MeS-51
RETI
Return from Interrupt Routine
Mnemonic:
RETI
Operands:
None
Format:
RETI
Bit Pattern:
00110010
7
Operation:
0
(PC high) +- ((SP))
(SP) +- (SP) -1
(PC low) +- ((SP))
(SP) +- (SP) -1
Bytes: 1
Cycles: 2
Flags:
C
AC FO RS1 RSO OV
P
PSW
Description:
3-114
This instruction returns from an interrupt service routine, and
reenables interrupts of equal or lower priority. Control passes to
the location addressed by the top two bytes on the stack. The highorder byte of the return address is always the first to come off the
stack. It is immediately followed by the low-order byte.
MCS-51
RETI
Example:
; Return from interrupt routine
RET!
Encoded Instruction:
1001100101
7
o
After
Before
Program Counter
Program Counter
1000010101 1 01010101
100000000111110001
15
8
7
0
15
8
Stack Pointer
Stack Pointer
1000010101
100001000 1
7
o
7
(OAH)
1 00000000 1
1 00000000 1
o
7
o
(09H)
(09H)
1111100011
1111100011
7
0
7
0
o
(OAH)
7
7
0
Notes: 2,17
3-115
RL
MCS-51
Rotate Accumulator Left
Mnemonic:
RL
Operands:
A
Format:
RLA
Accumulator
Bit Pattern:
00100011
7
Operation:
0
ACCUMULATOR
C
o
Bytes: 1
Cycles: 1
Flags:
C
AC FO RSl RSO
ov
p
PSW
Description:
This instruction rotates each bit in the accumulator one position to
the left. The most significant bit (bit 7) moves into the least significant bit position (bit 0).
Example:
RLA
; Rotate accumulator left one positon.
Encoded Instruction:
100100011
7
0
Before
After
Accumulator
Accumulator
111010000
I,
,
7
0
110100001
Notes: None
3-116
I
7
0
RLC
MCS-S1
Rotate Accumulator and Carry Flag Left
Mnemonic:
RLC
Operands:
A
Format:
RLCA
Accumulator
Bit Pattern:
00110011
7
0
Operation:
ACCUMULATOR
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction rotates each bit in the accumulator one position to
the left. The most significant bit (bit 7) moves into the Carry flag,
while the previous contents of Carry moves into the least significant
bit (bit 0).
Example:
RLCA
; Rotate accumulator and carry left
; one positon.
Encoded Instruction:
100110011
7
I
o
Before
After
Accumulator
Accumulator
I 00011001
00110011
7
0
7
Carry Flag
Carry Flag
IT]
[JJ
0
Note: 5
3-117
MeS-51
RR
Rotate Accumulator Right
Mnemonic:
RR
Operands:
A
Format:
RR A
Accumulator
Bit Pattern:
00000011
7
Operation:
0
C
ACCUMULATOR
D
Bytes:
Cycles:
Flags:
C
AC FO RS1 RSO OV
p
PSW
'Description:
This instruction rotates each bit in the accumulator one position to
the right. The least significant bit (bit 0) moves into the most
significant bit position (bit 7).
Example:
RRA
; Rotate accumulator right one
; positon.
Encoded Instruction:
1 00000011
7
0
Before
After
Accumulator
Accumulator
11010001
111101000
7
0
Notes: None
3-118
I
7
0
I
RRC
MeS-51
Rotate Accumulator and Carry Flag Right
Mnemonic:
RRC
Operands:
A
Format:
RRCA
Accumulator
Bit Pattern:
00010011
0
7
Operation:
C
ACCUMULATOR
~I-
Ef
1
1- 1- 1- 1- 1- 1- 1-0
7
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction rotates each bit in the accumulator one position to
the right. The least significant bit (bit 0) moves into the Carry flag,
while the previous contents of Carry moves into the most significant bit (bit 7).
Example:
RRCA
; Rotate accumulator and carry right
; one positon.
Encoded Instruction:
00010011
7
0
Before
After
Accumulator
Accumulator
10011000
11001100
7
7
0
Carry Flag
Carry Flag
[JJ
IT]
0
Note: 5
3-119
MeS-51
SETB
Set Carry Flag
Mnemonic:
SETB
Operands:
C
Format:
SETBC
Carry Flag
Bit Pattern:
111010011
7
Operation:
0
(C) -1
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO
ov
p
PSW
Description:
This instruction sets the carry flag to 1.
Example:
SETBe
; Set Carry to 1
Encoded Instruction:
111010011
7
o
Before
After
Carry Flag
Carry Flag
IT]
OJ
Notes: None
3-120
I
SETB
MeS-51
Set Bit
Mnemonic:
SETB
Operands:
bit address
Format:
SETB bit address
Bit Pattern:
I 1 1 0 1 0 0 1 0 I Bit Add ress
0 <= bit address
707
Operation:
<= 255
1
0
(bit address) ..... 1
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
This instruction sets the contents of the specified bit address to 1.
Example:
SETB41.5
; Set the contents of bit 5 in byte 41
; to 1
Encoded Instruction:
111010010
7
o
01001101
7
o
Before
After
(41)
(41)
1010001101
101100110
750
750
Notes: None
3-121
MCS-Sl
SJMP
Short Jump
Mnemonic:
SJMP
Operands:
code address
Format:
SJMP code address
Bit Pattern:
Operation:
10000000
Rei. Offset
7
7
0
(PC)
(PC)
+-
C
AC
+-
(PC)
(PC)
0
+2
+ relative offset
Bytes: 2
Cycles: 2
Flags:
FO RS1 RSO OV
p
PSW
Description:
This instruction transfers control to the specified code address. The
Program Counter is incremented to the next instruction, then the
relative offset is added to the incremented program counter, and
the instruction at that address is executed.
Example:
SJMP BOTTOM
FF:INCA
BOTTOM:
RRA
; Jump to BOTTOM
; (15 bytes ahead from the INC
; instruction)
Encoded Instruction:
10000000
00001111
7
7
0
0
Before
After
Program Counter
1110100011011100 1 111101000
11101101
15
7
8
Notes: lO, 11, 12
3-122
Program Counter
7
0
15
8
0
SUBB
MCS-Sl
Subtract Immediate Data from
Accumulator with Borrow
Mnemonic:
SUBB
Operands:
A
data
Format:
SUBB A,#data
Accumulator
-256 <= data <= +255
Bit Pattern:
1 100101 00 Ilmmediate Datal
o
7
o
7
(A) ..- (A) - (C) - data
Operation:
Bytes: 2
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction subtracts the contents of the Carry flag and the
immediate data value from the contents of the accumulator. It
places the result in the accumulator.
Example:
SUBBA,#OC1H
; Subtract OC1 H from accumulator
Encoded Instruction:
110010100
7
0
01100100
7
0
Before
After
Accumulator
Accumulator
1001001101
101100100
7
o
7
I
o
Carry Flag
Carry Flag
OJ
OJ
Auxiliary Carry Flag
Auxiliary Carry Flag
IT]
OJ
Overflow Flag
Overflow Flag
OJ
IT]
Notes: 4,5,6, 13, 14
3-123
MCS-Sl
SUBB
Subtract Indirect Address from
Accumulator with Borrow
Mnemonic:
SUBB
Operands:
A
Format:
SUBBA,@Rr
Accumulator
Register 0 <= r <= 1
Rr
Bit Pattern:
\1001011r \
7
Operation:
0
(A) +- (A) - (C) -
«Rr»
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
3-124
This instruction subtracts the Carry flag and the memory location
addressed by the contents of register r from the contents of the
accumulator. It places the result in the accumulator.
SUBB
MCS-Sl
; Subtract the indirect address from
; accumulator
SUBBA,@R1
Example:
Encoded Instruction:
1100101111
7
0
Before
After
Accumulator
Accumulator
1100001101
100100100 1
7
0
7
0
Register 1
Register 1
100011100 1
100011100 1
7
0
7
0
(1CH)
(1CH)
101100010 1
101100010 1
7
0
7
0
Carry Flag
Carry Flag
OJ
IT]
Auxiliary Carry Flag
Auxiliary Carry Flag
IT]
[JJ
Overflow Flag
Overflow Flag
IT]
[JJ
Notes: 5,6, 13, 14, 15
3-125
MeS-51
SUBB
Subtract Register from Accumulator with Borrow
Mnemonic:
SUBB
Operands:
A
Accumulator
Register 0 <= r
Rr
Format:
SUBBA,Rr
Bit Pattern:
110011rrr
7
Operation:
<= 7
I
0
(A) - (A) - (C) - (Rr)
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
1-1-1
P
I-I I-I
PSW
Description:
3-126
This instruction subtracts the contents of the Carry flag and the
contents of register r from the contents of the accumulator. It
places the result in the accumulator.
SUBB
MeS-51
; Subtract R6 from accumulator
SUBBA,R6
Example:
Encoded Instruction:
110011110 1
7
0
Before
After
Accumulator
Accumulator
101110110 1
111 1 10000 1
7
0
7
0
R6
R6
1100001011
110000101
7
o
7
o
Carry Flag
Carry Flag
QJ
QJ
Auxiliary Carry Flag
Auxiliary Carry Flag
CD
QJ
Overflow Flag
Overflow Flag
ED
QJ
Notes: 5, 6, 13, 14
3-127
MCS-Sl
SUBB
Subtract Memory from Accumulator with Borrow
Mnemonic:
SUBB
Operands:
A
data address
Format:
SUBB A,data address
Bit Pattern:
1 001 01 01
o
7
Operation:
(A)
+-
Accumulator
0 <= data address
<= 255
IData Address I
7
o
(A) - (C) - (data address)
Bytes: 2
Cycles: 1
Flags:
C
AC
FO RS1 RSO OV
p
PSW
Description:
3-128
This instruction subtracts the contents of the Carry flag and the
contents of the specified address from the contents of the
accumulator. It places the result in the accumulator.
SUBB
MeS-51
; Subtract 32H in memory from
; accumulator
SUBBA,32H
Example:
Encoded Instruction:
110010101 100110010
7
o
7
I
o
Before
After
Accumulator
Accumulator
100100110
7
I
o
7
(32H)
I
o
(32H)
101010011
7
111010010
I
o
101010011
7
o
Carry Flag
Carry Flag
IT]
IT]
Auxiliary Carry Flag
Auxiliary Carry Flag
IT]
IT]
Overflow Flag
Overflow Flag
IT]
IT]
Notes: 5,6, 8, 13, 14
3-129
MCS-Sl
SWAP
Exchange Nibbles in Accumulator
Mnemonic:
SWAP
Operands:
A
Format:
SWAPA
Accumulator
Bit Pattern:
11000100
7
0
Operation:
Bytes:
Cycles:
Flags:
C
AC
FO RSO RS1 OV
p
PSW
Description:
This instruction exchanges the contents of the low order nibble
(0-3) with the contents of the high order nibble (4-7).
Example:
SWAPA
; Swap high and low nibbles in the
; accumulator.
Encoded Instruction:
111000100
7
0
Before
After
Accumulator
Accumulator
11010000
00001101
7
7
0
Notes: None
3-130
I
0
MeS-51
XCH
Exchange Indirect Address with Accumulator
Mnemonic:
XCH
Operands:
A
Rr
Format:
XCH A,@Rr
Accumulator
Register 0 <= r
Bit Pattern:
11100011r
7
<= 1
I
0
temp ~ «Rr))
«Rr)) ~ (A)
(A) +- temp
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
I-I
PSW
Description:
This instruction exchanges the contents of the memory location
addressed by the contents of register r with the contents of the
accumulator.
Example:
XGHA,@RO
; Exchange the accumulator with
; memory
Encoded Instruction:
111000110
7
I
o
Before
After
Accumulator
Accumulator
100111111
100011101
7
o
Register 0
101010010
7
o
7
I
o
Register 0
101010010
7
o
(52H)
(52H)
100011101
100111111
7
0
7
I
0
Notes: 5,15
3-131
MCS-Sl
XCH
Exchange Register with Accumulator
Mnemonic:
XCH
Operands:
A
Rr
Format:
XCH AJRr
Accumulator
Register 0 <= r
<= 7
Bit Pattern:
111001rrr
7
0
temp +- (Rr)
(Rr) +- (A)
(A) +- temp
Operation:
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction exchanges the contents of register r with the
contents of the accumulator.
Example:
XGHA,R6
; Exchange register 6 with the
; accumulator
Encoded Instruction:
111001100 1
7
0
Before
After
Accumulator
Accumulator
10011001
110000000
7
o
110000000
Note: 5
3-132
o
Register 6
Register 6
7
7
0
10011001
7
0
I
XCH
MCS-Sl
Exchange Memory with Accumulator
Mnemonic:
XCH
Operands:
A
data address
Format:
XCH A,data address
Bit Pattern:
111000101
7
0
Accumulator
0 <= data address
<= 255
IData Address I
7
0
temp +- (data address)
(data address) +- (A)
(A) +- temp
Operation:
Bytes: 2
Cycles: 1
Flags:
C- AC
p
FO RS1 RSO OV
PSW
Description:
This instruction exchanges the contents of the specified data
address with the contents of the accumulator.
Example:
XCHA,37H
; Exchange accumulator with the
; contents of location 37H
Encoded Instruction:
111000101 100110111
7
o
7
o
Before
After
Accumulator
Accumulator
101110111
111110000
7
o
7
o
(37H)
(37H)
111110000
7
I
0
I
101110111
7
0
Notes: 5.9
3-133
Mes-sl
XCHD
Exchange Low Nibbles (Digits) of Indirect
Address with Accumulator
Mnemonic:
XCHD
Operands:
A
Accumulator
Register 0 <= r <= 1
Rr
Format:
XCHDA,@Rr
Bit Pattern:
11101011r
7
Operation:
I
0
temp .... «Rr)) 0-3
«Rr)) 0-3 .... (A) 0-3
(A) 0-3 .... temp
Bytes: 1
Cycles: 1
Flags:
C
AC
FO RS1 RSO
PSW
Pescription:
3-134
ov
p
1-'
This instruction exchanges the contents of the low order nibble (bits
0-3) of the memory location addressed by the contents of register r
with the contents of the low order nibble (bits 0-3) of the
accumulator.
XCHD
MCS-Sl
Example:
; Exchange the accumulator with
; memory
XGHDA,@RO
Encoded Instruction:
111010110 1
7
0
Before
After
Accumulator
Accumulator
100111111
100111101
7
o
7
o
Register 0
Register 0
1010100101
[010100101
7
o
7
o
(52H)
(52H)
1000111011
100011111
7
o
7
o
Notes: 5,15
3-135
MCS-Sl
XRL
Logical Exclusive OR Immediate Data
to Accumulator
Mnemonic:
XRL
A
Operands:
Accumulator
-256 <= data <= +255
data
Format:
XRLA,Idata
Bit Pattern:
I 01100100
7
Operation:
Ilmmediate Datal
0 7
0
(A) - (A) XOR data
Bytes: 2
Cycles: 1
Flags:
C
p
AC FO RS1 RSO OV
I-I
PSW
Description:
This instruction exclusive ORs the immediate data value to the
contents of the accumulator. Bit n of the result is 0 if bit n of the
accumulator equals bit n of the data value; otherwise bit n is I. It
places the result in the accumulator.
Example:
XRLA,IOFH
; Complement the low order nibble
Encoded Instruction:
101100100 100001111
707
Before
After
Accumulator
Accumulator
101110111
101111000
7
Notes: 4,5
3-136
0
o
7
o
I
XRL
MCS-51
Logical Exclusive OR Indirect Address
to Accumulator
Mnemonic:
XRL
Operands:
A
Accumulator
Rr
0<= Rr<= 1
XRLA,@Rr
Format:
Bit Pattern:
0110011r
7
0
(A) +- (A) XOR ((Rr))
Operation:
Bytes:
Cycles:
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction exclusive ORs the contents of the memory location
addressed by the contents of register r to the contents of the
accumulator. Bit n of the result is 0 if bit n of the accumulator
equals bit n of the addressed location; otherwise bit n is 1. It places
the result in the accumulator.
Example:
XRLA,@RO
; XOR indirect address with
; accumulator
Encoded Instruction:
01100110
7
o
Before
After
Accumulator
Accumulator
00101000
00101001
7
7
0
0
Register 0
Register 0
01010010
01010010
7
7
0
0
(52H)
(52H)
I 00000001
I 00000001
7
0
7
0
Notes: 5, 15
3-137
XRL
MeS-51
Logical Exclusive OR Register to Accumulator
Mnemonic:
XRL
Operands:
A
Accumulator
Register 0 <= r <= 7
Rr
Format:
XRLA,Rr
Bit Pattern:
101101rrr
7
Operation:
0
(A) .... (A) XOR (Rr)
Bytes: 1
Cycles: 1
Flags:
C
AC
p
FO RS1 RSO OV
PSW
Description:
This instruction exclusive ORs the contents of register r to the
contents of the accumulator. Bit n of the result is 0 if bit n of the
accumulator equals bit n of the specified register; otherwise bit n is
1. It places the result in the accumulator.
Example:
XRLA,R4
; XOR R4 with accumulator
Encoded Instruction:
101101100
7
o
Before
After
Accumulator
Accumulator
10010001
7
0
11100011
7
Note: 5
101110010 1
7
0
Register 4
Register 4
3-138
I
0
111100011
7
0
XRL
MeS-51
Logical Exclusive OR Memory to Accumulator
Mnemonic:
XRL
Operands:
A
data address
Format:
XRL A,data. address
Accumulator
0 <= data address
Bit Pattern:
1 011 001 01
7
(A)
Operation:
0
~
<= 255
IData Address 1
7
0
(A) XOR (data address)
Bytes: 2
Cycles: 1
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction exclusive ORs the contents of the specified data
address to the contents of the accumulator. Bit n of the result is 0 if
bit n of the accumulator equals bit n of the addressed location;
otherwise bit n is 1. It places the result in the accumulator.
Example:
XRLA,37H
; XOR the contents of location 37H
; with accumulator
Encoded Instruction:
01100101
00110111
7
7
0
0
Before
After
Accumulator
Accumulator
01111111
11110111
7
7
0
0
(37H)
(37H)
110001000
110001000
7
0
7
0
Notes: 4,8
3-l39
MeS-51
XRL
Logical Exclusive OR Immediate Data to Memory
Mnemonic:
XRL
Operands:
data address
data
Format:
XRL data address ,'data
Bit Pattern:
0 <= data address <= 255
-256 <= data <= + 255
I 011 00011 IData Address Ilmmediate Datal
7
Operation:
07
07
0
(data address) - (data address) XOR data
Bytes: 3
Cycles: 2
Flags:
C
p
AC FO RS1 RSO OV
PSW
Description:
This instruction exclusive ORs the immediate data value to the
contents of the specified data address. Bit n of the result is 0 if bit n
of the specified address equals bit n of the data value; otherwise,
bit n is 1. It places the result in data memory at the specified
address.
Example:
XRL P1,#51H
; XOR 51 H with the contents of Port 1
Encoded Instruction:
101100011
7
0
01010001
7
7
0
Before
After
Port 1 (90H)
Port 1 (90H)
101110110
7
Notes: 4,9
3-140
10010000
0
I
0
11100110
7
0
MCS-Sl
XRL
Logical Exclusive OR Accumulator to Memory
Mnemonic:
XRL
Operands:
data address
A
Format:
XRL data address ,A
Bit Pattern:
o1 1 00 0 1 0
7
0
0 <= data address
Accumulator
<= 255
1Data Address 1
7
0
(data address) +- (data address) XOR A
Operation:
Bytes: 2
Cycles: 1
Flags:
C
p
FO RS1 RSO OV
AC
I
PSW
Description:
This instruction exclusive ORs the contents of the accumulator to
the contents of the specified data address. Bit n of the result is 0 if
bit n of the accumulator equals bit n of the specified address;
otherwise bit n is 1. It places the result in data memory at the
specified address.
Example:
XRL 10H,A
; XOR the contents of 10H with the
; accumulator
Encoded Instruction:
01100010
00010000
7
7
0
0
Before
After
Accumulator
Accumulator
11110000
11110000
7
7
0
0
(10H)
(10H)
100110001
111000001
7
0
7
0
Note: 9
3-141
Mes-sl
Instruction Set
Notes
1. The low-order byte of the Program Counter is always placed on the stack first,
followed by the high order byte.
2. The Stack Pointer always points to the byte most recently placed on the stack.
3. On the 8051 the contents of the Stack Pointer should never exceed 127. If the
stack pointer exceeds 127, data pushed on the stack will be lost, and undefined
be returned. The Stack Pointer will be incremented normally even
data
though data is not recoverable..
4. The expression used as the data operand must evaluate to an eight-bit number.
This limits the range of possible values in assembly time-expressions to between
-256 and +255 inclusive.
5. The Parity Flag, PSW.O, always shows the parity of the accumulator. If the
number of l' s in the accumulator is odd, the parity flag is 1; otherwise, the
parity flag will be O.
6. All addition operations affect the Carry Flag, PSW. 7, and the Auxiliary Carry
flag, PSW.6. The Carry flag receives the carry out from the bit 7 position (Most
Significant Bit) in the accumulator. The Auxiliary Carry flag receives the carry
out from the bit 3 position. Each is either set or cleared with each ADD
operation.
7. The overflow flag (OV) is set when an operation produces an erroneous result
(i.e. the sum of two negative numbers is positive, or the sum of two positive
numbers is negative). OV is updated with each operation.
8. If one of the I/O ports is specified by the data address, then data will be taken
from the port input pins.
9. If orie of the 110 ports is specified by the data address, then data will be taken
from, and returned to, the port latch.
10. The code address operand must be within the range of -128 and +127 inclusive
of the incremented program counter's value.
11. The last byte of the encoded instruction is treated as a two's complement
number, when it is added to the program counter.
12. The Program Counter is always incremented before the add.
13. The auxiliary carry flag is set if there is a borrow from bit 3 of the accumulator;
otherwise, it is cleared.
14. The overflow flag (OV) is set when an operation produces an erroneous result
(i.e~ a positive number is subtracted from a negative number to produce a
positive result, or a negative number is subtracted from a positive number to
produce a negative result). OV is cleared with each correct operation.
15. On the 8051 the contents of the register used in the indirect address should not
exceed 127. When the contents of the register is 128 or greater, source operands
will return undefined data, and destination operands will cause data to be lost.
In either case, the program will continue with no change in execution time or
control flow.
will
16. If an I/O port is specified as the source operand, then the the port pins will be
read. If an 110 port is the destination operand, then the port latch will receive'
the data.
17. If the stack pointer is 128 or greater, then invalid data will be returned on a
POP or return.
3-142
CHAPTER 4
ASSEMBLER DIRECTIVES
This chapter describes the assembler directives. It shows how to define symbols and
how to control the placement of code and data in program memory.
Introduction
The MCS-S 1 assembler has several directives that permit you to set symbol values,
reserve and initialize storage space, and control the placement of your code.
The directives should not be confused with instructions. They do not produce executable code, and with the exception of the DB and DW directives, they have no
direct effect on the contents of code memory. What they do is change the state of the
assembler, define user symbols, and add information (other than pure object code)
to the object file (e.g., segment definitions).
The directives are divided into the following categories:
Symbol Definition
SEGMENT
EQU
SET
DATA
IDATA
XDATA
BIT
CODE
Storage Initialization/Reservation
DS
DB
DW
DBIT
Program Linkage
PUBLIC
EXTRN
NAME
Assembler State Control
ORG
END
Segment Selection Directives
RSEG
CSEG
DSEG
XSEG
ISEG
BSEG
USING
The MCS-SI assembler is a two-pass assembler. In the first pass, symbol values are
determined, and in the second, forward references are resolved, and object code is
produced. This structure imposes a restriction on the source program: expressions
4-1
Assembler Directives
which define symbol values (see Symbol Definition Directives) and expressions
which control the location counter (see ORO, OS, and DBIT directives) may not
have forward references.
The Location Counter
The location counter in ASM51 is a pointer to the address space of the active segment. When a segment is first activated, the location counter is 0 (unless a base
address was specified using the segment select directives). The location counter is
changed after each instruction by the length of the instruction. You can change its
value with the ORO directive, which sets a new program origin for statements that
follow it. The storage initialization and reservation directives (DS, DB, DW, and
DB IT) change the value of the location counter as statements are encountered within
a segment. If you change segments and later return to that segment, the location
counter is restored to its previous value. Whenever the assembler encounters a label,
it assigns to the label the current value of the location counter and the type of the
current segment.
The dollar sign ($) indicates the value of the active segment's location counter.
When you use the location counter symbol, keep in mind that its value changes with
each instruction, but only after that instruction has been completely evaluated. If
you use $ in an operand to an instruction or a directive, it represents the code
address of the first byte of that instruction.
MSG: DB MSG_LENGTH,'THIS IS A MESSAGE'
MSG_LENGTH EaU $-MSG-1 ;message length
'Symbol Names
A symbol name must begin with a letter or a special character (either? or _),
followed by letters, special characters, or digits.
You can use up to 255 characters in a symbol name, but only the first 31 characters
are significant. A symbol name may contain upper- or lower-case characters, but the
assembler converts to upper-case characters for internal representation. So, to
ASM51, "buffer" is the same as "BUFFER" and the name
is the same as the name
although the strings are different.
The instruction mnemonics, assembly-time operators, predefined bit and data
addresses, segment attributes, and assembler directives may not be used as userdefined symbol names. For a complete list of these reserved words, refer to
Appendix F.
Statement Labels
A label is a symbol. All of the rules for forming symbol names apply to labels. A
statement label is the first field in a line, but it may be preceded by any number of
tabs or spaces. You must place a colon (:) after a label to identify it as a label. Only
one label is permitted per line.
.
4-2
MeS-51
Mes-sl
Assembler Directives
Labels are allowed only before empty statements, machine instructions, data initialization directives (DB and DW), and storage reservation directives (DS and DBIT).
Simple names (without colons) can only precede symbol definition directives (EQU,
SET, CODE, DATA, IDATA, XDATA, BIT, and SEGMENT). All other
statements may not be preceded by labels or simple names.
When a label is defined, it receives a numeric value and segment type. The numeric
value will always be the current value of the location counter of the currently
selected segment at the point of use. The value of the label will be relocatable or
absolute depending on the relocatability of the current segment. The segment type
will be equivalent to the segment type of the current segment.
Several examples of lines containing labels are shown below:
LABEL1: OS 1
LABEL2: ;This line contains no instruction; it is an empty statement
LAB3: DB 27,33,'FIVE'
MOV_PROe: MOV DPTR,ILABEL3
You can use labels like any other symbol, as a memory address, or a numeric value
in an assembly-time expression. A label, once defined, may not be redefined.
Symbol Definition
The symbol definition directives allow you to create symbols that can be used to
represent segments, registers, numbers, and addresses. None of these directives may
be preceded by a label.
Symbols defined by these directives may not have been previously defined and may
not be redefined by any means. The SET directive is the only exception to this.
SEGMENT Directive
The format for the SEGMENT directive is shown below. Note that a label is not
permitted.
relocatable_segmenLname SEGMENT segmenLtype [relocation_type]
The SEGMENT directive allows you to declare a relocatable segment, assign a set of
attributes, and initialize the location counter to zero (0).
Although the name of a relocatable segment must be unique in the module, you can
define portions of the segment within other modules and let RL51 combine them.
When you do this, the segment type attributes must all be the same and the relocation types must either be the same or be of two types, one of which is UNIT (see
below). In the latter case, the more restrictive type will override.
The segment type specifies the address space where the segment will reside. The
allowable segment types are:
•
•
•
•
•
CODE-the code space
XDAT A-the external data space
DAT A-the internal data space accessible by direct addressing (0 to 127)
IDAT A-the entire internal data space accessible by indirect addressing (0 to
127)
BIT -the bit space (overlapping locations 32 to 47 of the internal data space)
4-3
MCS-Sl
Assembler Directives
The relocation type, which is optional, defines the relocation possibilities to be
assigned by the RLSI. The allowable relocation types are:
• P AGE-specifies a segment whose start address must be on a 256-byte page
boundary. Allowed only with CODE and XDAT A segment types.
• IN PAGE-specifies a segment which must be contained in a 256-byte page.
Allowed only with CODE and XDA T A segment types.
• IN BLOCK-specifies a segment which must be contained in a 2048-byteblock.
Allowed only for CODE segments.
• BITADDRESSABLE-specifies a segment which will be relocated by RL5l
within the bit space on a byte boundary. Allowed only for DATA segments;
limited to a I6-byte maximum size.
• UNIT -specifies a segment which will be aligned on a unit boundary. This will
be a byte boundary for CODE, XDA T A, DATA, and IDA T A segments and a
bit boundary for BIT segments. This relocation type is the default value.
NOTE
When used in expressions, the segment symbol stands for the base
address of the combined segment.
Any DATA or IDA T A segments may be used as a stack (there is no explicit stack
segment).
For example,
STACK
SEGMENT
RSEG
DS
IDATA
STACK
10H
MOV
SP,lfSTACK-1 ;Initialize stack pointer
;Reserve 16 bytes for stack
EQU Directive
The format for the EQU directive is shown below. Note that a label is not permitted.
symbol_name EQU expression
or
symboL name EQU speciaLassembler_symbol
The EQU directive assigns a numeric value or special assembler symbol to a
specified symbol name. The symbol name must be a valid ASM5I symbol as
described above.
If you assign an expression to the symbol, it must be an absolute or simple
relocatable expression with no forward references. You can use the symbol as a data
address, code address, bit address, or external data address depending on the segment type of the expression, i.e., the symbol will have the segment type of the
expression. If the expression evaluates into NUMBER, the symbol will be con·
sidered as such and will be allowed to be used everywhere.
The special assembler symbols A, RO, RI, R2, R3, R4, R5, R6, and R7 can be
represented by user symbols defined with the EQU directive. If you define a symbol
to a register value, it will have a type "REG". It can only be used in the place of that
register in instruction operands.
4-4
Assembler Directives
MeS-51
A symbol defined by the EQU directive cannot be defined anywhere else.
The following examples show several uses of EQU:
ACCUM
N27
HERE
DADDR1
; define ACCUM to stand for A
; (the 8051 accumulator)
27
; set N27 to equal 27
EOU
$
; set HERE to current location counter
EOU
; value
EOU DADDRO + 1 ; Assuming DADDRO is a DATA address
; DADDR1 will also be a OAT A address
EOU
A
SET Directive
The format for the SET directive is shown below.
symbol_name SET expression
or
symboL name SET special_assembler_symbol
The SET directive operates similiar to EQU. The difference is that the defined symbol can be redefined later, using another SET directive.
NOTE
You cannot set a symbol which was equated and you cannot equate a symbol which was set.
The following examples show several uses of SET:
COUNT
COUNT
HALF
SET
SET
SET
0
COUNT+1
WHOLEl2
H2O
INDIRECT
SET
SET
32
Rl
;Initialize absolute counter
;Increment absolute counter
;Give half of W!-lOLE to HALF
;the remainder is discarded
;Set H20 to 32
;Set INDIRECT to Rl
BIT Directive
The format for the BIT directive is shown below.
symboL name BIT biLaddress
The BIT directive assigns a bit address to the specified symbol name.
Bit address format is described in Chapter 2. The symbol gets the segment type BIT.
A symbol defined as BIT may not be redefined elsewhere in the program.
The following examples show several uses of BIT:
RSEG
OS
DATA_SEG
;A relocatable bit addressable segment
CONTROL:
ALARM
OPEN_DOOR
RESET_BOARD
BIT
BIT
BIT
CONTROl.O
ALARM+1
060H
;Bit in a relocatable byte
;The next bit
;An absolute bit
4-5
Assembler Directives
MeS-51
DATA Directive
The format for the DATA directive is shown below.
symbol_name DATA expression
The DATA directive assigns an on-chip data address to the specified symbol name.
The expression must be an absolute or simple relocatable expression. Absolute
expressions greater than 127 must specify a defined hardware register (see Chapter
1). The segment type of the expression must beeeither DATA or NUMBER. The
symbol gets the segment type DATA.
A symbol defined by the DATA directive may not be redefined elsewhere in the
program.
The following examples show several uses of DATA:
CONIN
DATA
TABLE __ BASE DATA
SBUF
70H
7FH
REL_TABLE DATA
RELSTART +1
;define CONIN to address
;the serial port buffer
;define TABLE_BASE to be
;at location 70H
;define TABLE_END to be
;attop of RAM (7FH)
; Define REL_TABLE to bea
;relocatable symbol (assuming
;RELSTART is)
XDATA Directive
The format for the XDAT A directive is shown below.
symboL name XDAT A expression
The XDA T A directive assigns an off-chip data address to the specified symbol
name. The expression must be an absolute or simple relocatable expression. If the
expression does not evaluate to a number, its segment type must be XDA TA. The
symbol gets the segment type XDA T A. A symbol defined by the XDA T A directive
may not be redefined elsewhere in the program.
The following examples show several uses of XDA T A:
DATE:
TIME
PLACE
RSEG
ORG
OS
XDATA
XDAT A
XSEG1
100H
5
DATE+5
TIME + 3
;Define DATE to 100H off XSEG1 base
;define TIME to be 5 bytes after DATE
;define PLACE to be 3 bytes after TIME
IDATA Directive
The format for the IDAT A directive is shown below.
symbol_name IDATA expression
The IDA T A directive assigns an indirect internal data address to the specified symbol name. The expression must be an absolute or simple relocatable expression.
Absolute expressions may not be larger than 127 for the 8051. The segment type of
the expression must be either IDATA or NUMBER. The symbol gets the segment
type IDA T A. A symbol defined by the IDA T A directive may not be redefined
elsewhere in the program.
4-6
Assembler Directives
MeS-51
The following examples show several uses of IDATA:
BUFFER
BUFFER_LEN
BUFFER_END
IDATA
EQU
IDATA
60H
20H
BUFFER+ BUFFER_LEN-1
CODe Directive
The format for the CODE directive is shown below.
symboL name CODE expression
The CODE directive assigns a code address to the specified symbol name. The
expression must be an absolute or simple relocatable expression. If the expression
does not evaluate to a number, its segment type must be CODE. The symbol gets a
segment type of CODE. A symbol defined by the CODE directive may not be
redefined elsewhere in the program.
The following examples show several uses of the CODE directive:
RESTART
INT_VECO
INT_VEC1
INT_VEC2
~torage
CODE
CODE
CODE
CODE
OOH
03H
OBH
1BH
Initialization and Reservation
The storage initialization and reservation directives are used to initialize and reserve
space in either word, byte, or bit units. The space reserved starts at the point indicated by the current value of the location counter in the currently active segment.
These directives may be preceded by a label.
OS Directive
The format of the DS directive is as follows:
[label:) OS expression
The DS directive reserves space in byte units. It can be used in any segment except a
BIT type segment. The expression must be a valid assembly-time expression with no
forward references and no relocatable or external references. When a DS statement
is encountered in a program, the location counter of the current segment is incremented by the value of the expression. The sum of the location counter and the
specified expression should not exceed the limitations of the current address space,
or those set by the current relocation type.
OBIT Directive
The format of the DBIT directive is as follows:
[label:] OBIT expression
The DBIT directive reserves a space in bit units. It can be used only in a BIT type
segment. The expression must be a valid assembly-time expression with no forward
references. When the DBIT statement is encountered in a program, the location
4-7
MeS-51
Assembler Directives
counter of the current (BIT) segment is incremented by the value of the expression.
Note that in a BIT segment, the basic unit of the location counter is in bits rather
than bytes.
DB Directive
The format for a DB directive is shown below:
[label:) DB expression_list
The DB directive initializes code memory with byte values. Therefore, a CODE type
segment must be active. The expression list is a series of one or more byte values or
strings separated by commas(,). A byte value can be represented as an absolute or
simple relocatable expression or as a character string. Each item in the list (expression or character string) is placed in memory in the same order as it appears in the
list.
The DB directive permits character strings longer than 2 characters, but they must
not be part of an expression (i.e., you cannot use long character strings with an
operator, including parentheses). If you specify the null character string as an item
in the list (not as part of an expression), it generates no data. If the directive has a
label, the value of the label will be the address of the first byte in the list.
The following examples show several ways you can specify the byte value list in a DB
directive:
AGE: DB 'MARY' ,0,27, 'BILL' ,0,25, 'JOE' ,0,21, 'SUE' ,0,18
; This DB statement lists the names (character strings)
; and ages (numbers) that have been placed in a list (the label
; AGE will address the "M" in "MARY")
PRIMES:
DB 1,2,3,5,7,11 ,13,17,19,23,29,31 ,37,41 ,43,47,53
; This DB lists the first 17 prime numbers.
; (PRIMES is the address of 1)
QUOTE:
DB 'THIS IS A QUOTE'"
; This is an example of how to put the
; quote character in a character
; strlng.
OW Directive
The format for a DW statement is shown below:
[label:) OW expression_list
The DW directive initializes code memory with a list of word (l6-bit) values.
Therefore, a CODE type segment must be active. The expression list can be a series
of one or more word values separated by commas(,). Word values can be absolute or
simple relocatable expressions. If you use the location counter ($) in the list, it
evaluates to the code address of the word being initialized. Unlike the DB directive,
no more than two characters are permitted in a character string, and the null
character string evaluates to O.
Each item in the list is placed in memory in the same order as it appears in the list,
with the high order byte first, followed by the low order byte (unlike the way it is
handled by the ASM80/86). If the statement has a label, the value of the label will
address the first value in the list (i.e., the high order byte of the first word).
4-8
Assembler Directives
MCS-Sl
The following examples show several ways you can specify the word value list in a
DW directive:
ARRIVALS:
OW 710,'AM', 943, 'AM', 315,'PM' ,941 'PM'
; This OW lists several flight arrivals.
; The numbers and characters are encoded
; consecutively.
INVENTORY: OW 'F' ,27869, 'G' ,34524, 'X' ,27834
; This list of characters and numeric
; values will be encoded with the high
; order byte of each character string
; filled with zeros. INVENTORY will
; address a zero byte.
JUMP_TABLE OW GO_PROC,BREAK_PROC,OISPLAY_PROC
; A jump table is constructed by listing
; the procedure addresses
OW $, $-2, $-4, $-6
; This OW statement initializes four
; words of memory with the same value.
; (The location counter is incremented
; by 2 for each item in the list.)
Program Linkage
program linkage directives allow the separately assembled modules to communicate
by permitting intermodule references and the naming of modules.
PUBLIC Directive
The format for the PUBLIC directive is shown below:
PUBLIC fisLoLnames
The PUBLIC directive allows symbols to be known outside the currently assembled
module. If more than one name is declared pUblic, the names must be separated by
commas (,). Each symbol name may be declared public only once in a module. Any
symbol declared PUBLIC must have been defined somewhere else in the program.
Predefined symbols and symbols defined as registers of segments (declared via the
SEGMENT directive) may not be specified as PUBLIC.
The following examples show several uses of the PUBLIC directive:
PUBLIC puLcrlf, puLstring,
PUBLIC ascbin, binasc
PUBLIC liner
puLdat~str
EXTRNDirective
The format for the EXTRN directive is shown below:
EXTRN
[segmenLtype (lisLoLsymbol_namesJ] , ...
The EXTRN directive lists symbols to be referenced in the current module· that are
defined in other ptodules. This directive may appear anywhere in the program.
4-9
Assembler Directives
The list of external symbols must have a segment type associated with each symbol
on the list. (The segment types are CODE, XDATA, DATA, IDATA, BIT, and
NUMBER, i.e., a typeless symbol.) The segment type indicates the way a symbol
may be used (e.g., a CODE type external symbol may be used as a target to a jump
instruction but not as the target of a move instruction). At link and locate time, the
segment type of the corresponding public symbol must match the segment type of
the EXTRN directive. This match is accomplished if either type is NUMBER or if
both types are the same.
The following examples show several uses of the EXTRN directive:
EXTRN CODE (puLcrlf, puLstring, geLnum), DATA (count,total)
EXTRN CODE (binasc, ascbin), NUMBER (table_size)
NAME Directive
The format for the NAME directive is shown below:
NAME module_name
The NAME directive is used to identify the current program module. All the rules
for naming apply to the module name. The NAME directive should be placed before
all directives and machine instructions in the module. Only comments and control
lines can precede the NAME directive.
If you choose not to use the name directive, the root (i.e., the file name without both
the drive and the extension identifiers) of the source filename is used as the default.
NOTE
When filename roots start with a digit and the NAME directive is not
specified, the module name cannot be used in the RL51 module list (such a
module name is illegal for RUI).
The symbol used in the NAME directive is considered undefined for the rest of the
program unless it is specifically defined later.
The following examples show several uses of the NAME directive:
NAME track
NAME compass
NAME chapter_45
Assembler State Controls
EN D Directive
Every program must have an END statement. Its format is shown below:
END
The END statement must not have a label, and only a comment may appear on the
line with it. The END statement should be the last line in the program; otherwise,
this will produce an error.
4-10
MCS-SI
Assembler Directives
MCS-Sl
ORG Directive
The ORG directive is used to alter the assembler's location counter to set a new program origin for statements that follow the directive.
The format for the ORG directive is shown below. Note that a label is not permitted.
ORG expression
The expression should be an absolute or simple relocatable expression referencing
the current segment and containing no forward references.
When the ORG directive is encountered in a program, the value of the expression is
computed as the new value of the location counter specifying the address at which
the next machine instruction or data item will be assembled in the current selected
segment. If the current segment is absolute, the value will be an absolute address in
the current segment; if the segment is relocatable, the value will be offset from the
base address of the instance of the segment in the current module.
The ORG directive modifies the location counter; it does not generate a new segment. That is, when the location counter is incremented from the current value, the
space between the previous and the current location counter becomes part of the current segment.
In an absolute segment, the location counter must not be decremented to an address
below the beginning of that segment.
Examples:
ORG ($ + 10H)AND OFFFOH ; set location counter to next
; 16-byte boundary
; set location counter to 50
ORG 50
Segment Selection Directives
The segment selection directives will divert the succeeding code or data into the
selected segment until another segment is selected by a segment selection directive.
The directives may select a previously defined relocatable segment, or optionally
create and select absolute segments.
The format for relocatable segment selection directives is shown below. Note that a
label is not permitted and that the name must be previously defined as a segment
name.
RSEG segment name
The format for absolute segment select directives is shown below. Note that a label is
not permitted here either.
CSEGj
XSEG
DSEG
/
ISEG
BSEG
{AT absolute_address 1
CSEG, DSEG, ISEG, BSEG, and XSEG select an absolute segment within the code,
internal data, indirect internal data, bit, or external data address spaces, respectively. If you choose to specify an absolute address (by including "AT absolute
4-11
MCS-Sl
Assembler Directives
address"), the assembler terminates the last absolute segment, if any. of the
specified segment type. and creates a new absolute segment starting at that address.
If you do not specify an absolute address. the last absolute segment of the specified
type is ~ontinued. If no absolute segment Of this type was selected and the absolute
address is omitted, a new segment is created starting at location o. You cannot use
any forward references and the start address must be an absolute expression.
Each segment has its own location counter; this location counter is always set to 0 in
the initial state. The default segment is an absolute code segment; therefore, the
initial state of the assembler is location 0 in the absolute code segment. When
another segment is chosen for the first time, the location counter of the former segment retains the last active value. When that former segment is reselected, the location counter picks up at the last active value. You can use the ORG directive to
change the location counter within the currently selected segment.
DATA_SEG1
CODE_SEG1
SEGMENT
DATA
CODE
SEGMENT
BSEG
AT70H
DECIMAL_MODE: OBIT
CHAR_MODE:
OBIT
RSEG
DATA_SEG1
TOTAL1:
OS
1
COUNT1:
OS
1
COUNT_W:
OS
2
RSEG
CODE_SEG1
; A relocatable data segment
; A relocatable code segment
; Absolute bit segment
; Absolute bit
; Select the relocatable data segment
; Select the relocatable code segment
USING Directive
The format for the USING directive is shown below. Note that a label is not
permitted.
USING expression
This directive notifies the assembler of the register bank that is used by the subsequent code. The expression is the number (between 0 and 3 inclusive) which refers to
one of four register banks.
The USING directive allows you to use the predefined symbolic register addresses
(ARO through AR7) instead of their absolute addresses. In addition, the directive
causes the assembler to reserve a space for the specified register bank.
Examples:
USING
PUSH
3
AR2
;Push register 2 of bank 3
USING 1
PUSH AR2
;Push register 2 of bank 1
Note that if you equate a symbol (e.g., using EQU directive) to an ARi symbol, the
user-defined symbol will not change its value as a result of the subsequent USING
directive.
4-12
CHAPTER 5
THE MACRO PROCESSING LANGUAGE
Introduction
The Macro Processing Language (MPL) of ASM51 is a string replacement facility.
It permits you to write repeatedly used sections of code once and then insert that
code at several places in your program. If several programmers are working on the
same project, a library of macros can be developed and shared by the entire team.
Perhaps MPL's most valuable capability is conditional assembly-with all
microprocessors, compact configuration dependent code is very important to goo"d
program design. Conditional assembly of sections of code can help to achieve the
most compact code possible.
This chapter documents MPL in three parts. The first section describes how to
define and use your own macros. The second section defines the syntax and
describes the operation of the macro processor's built-in functions. The final section
of the chapter is devoted to advanced concepts in MPL.
The first two sections give enough information to begin using the macro processor.
However, sometimes a more exact understanding of MPL's operation is needed.
The advanced concepts section should fill those needs.
Don't hesitate to experiment. MPL is one of the most powerful and easy to use tools
available to programmers.
Macro Processor Overview
The macro processor views the source file in very different terms than the assembler.
Figure 5-1 illustrates these two different views of the input file. To the assembler, the
source file is a series of lines-control lines, instruction lines, and directive lines. To
the macro processor, the source file is a long string of characters.
The figure below shows these two views of the source file.
•
•
•
A, #27
A,@RO
MOV @RO,A
MOV
ADD
•
•
•
Figure 5-1. Macro Processor versus AssemblerTwo Different Views of a Source File
937·15
5-1
Macro Processing Language
All macro processing of the source file is performed before your code is assembled.
Because of this independent processing of macros and assembly of code, we must
differentiate between macro-time and assembly-time. At macro-time, assembly
language symbols-labels, SET and EQU symbols, and the location counter are not
known. Similarly, at assembly-time, no information about macros is known.
The macro processor scans the source file looking for macro calls. A macro call is a
request to the processor to replace the call pattern 'of a built-in or user-defined
macro with its return value.
When a macro call is encountered, the macro processor expands the call to its return
value. The return value of a macro is then placed in a temporary work file, and the
macro processor continues. All characters that are not part of a macro call are
copied into the temporary workfile.
The return value of a macro is the text that replaces the macro call. The return value
of some macros is the null string. (The null string is a character string containing no
characters.) In other words, when these macros are called, the call is removed from
the input stream, and the assembler never sees any evidence of its presence. This is
particularly useful for conditional assembly.
Introduction to Creating and Calling Macros
The macro processor is a character string replacement facility. It searches the source
file for a macro call, and then replaces the call with the macro's return value. A 0/0
signals a macro call. % is the default metacharacter. The metacharacter must
precede a macro call .. Until the macro processor finds a metacharacter, it does not
'process text. It simply passes the text from the source file to a work file, which is
eventually assembled.
Since MPL only processes macro calls, it is necessary to call a macro in order to
create other macros. The built-in function DEFINE creates macros. Built-in functions are a predefined part of the macro language, so they may be called without
prior definition. The general syntax for DEFINE is:
% (*] DEFIN E(call-pattern )Iloca/-symbol-list ](macro-body)
DEFINE is the most important MPL built-in function. This section of the chapter is
devoted to describing this built-in function. Each of the symbols in the syntax above
(call-pattern, local-symbol-list, and macro-body) are thoroughly described in the
pages that follow. In some cases we have abbreviated this general syntax to
emphasize certain concepts.
Creating Simple Macros
When you create a simple macro, there are two parts to a DEFINE call: the call pattern and the macro body. The call pattern defines the name used when the macro is
called; the macro body defines the return value of the call.
The syntax of a simple macro definition is shown below:
%*DEFINE (call-pattern) (macro-body)
The '%' is the metacharacter that signals a macro call. The '.' is the literal
character. The literal character is normally used when defining macros. The exact
use of the literal character is discussed in the advanced concepts section of this
chapter.
5-2
MeS-51
Macro Processing Language
MeS-51
When you define a simple macro, the call-pattern is a macro identifier. It follows the
metacharacter, when you call the macro in the source file. The rules for macro identifiers are the same as ASM51 symbol names.
•
The identifier must begin with an alphabetic character (A,B,C, ... ,Z or
a,b,c, ... ,z) or a special character (a question mark ? or an underscore
character{_» .
•
The remaining characters may be alphabetic, special, or decimal digits
(0,1,2, ... ,9).
•
Only the first 31 characters of a macro identifier are recognized as the unique
identifier name. Upper and lower case characters are not distinguished in a
macro identifier.
The macro-body is usually the return value of the macro call. However, the macrobody may contain calls to other macros. If so, the return value is actually the fully
expanded macro body, including the calls to other macros. When you define a
macro using the syntax shown above, macro calls contained in the body of the
macro are not expanded, until you call the macro.
The syntax of DEFINE requires that left and right parentheses surround the macrobody. For this reason, you must have balanced parenthesis within the macro body
(i.e., each left parenthesis must have a succeeding right parenthesis, and each right
parenthesis must have a preceding left parenthesis). We call character strings that
meet these requirements balanced-text.
To call a macro, you use the metacharacter followed by the call-pattern for the
macro. (The literal character is not needed when you call a user-defined macro.) The
macro processor will remove the call and insert the return value of the call. If the
macro body contains any call to other macros, they will be replaced with their return
value.
Once a macro has been created, it may be redefined by a second call to DEFINE.
The three examples below show several macro definitions. Their return values are
also shown.
Example 1:
Macro definition at the top of program:
%' DEFINE(MOVE) (
MOVA,@R1
MOV@RO,A
INCR1
INCRO
)
Macro call as it appears in program (* literal character is not needed when you call
the user-defined macro):
POPACC
MOV R1,A
POP Ace
MOVRO,A
%MOVE
5-3
Macro Processing Language
MCS-SI
The program after the macro processor makes the expansion:
POPACC
MOVR1,A
POPACC
MOVRO,A
MOVA,@R1
MOV@RO,A
INCR1
INCRO
}
this is the return value
Example 2:
Macro definition at the top of the program:
%"DEFINE (MULT)(
MULAB
JNBOV,($+6)
LCALL OVFLERR
)
The macro call as it appears in original program body:
MOVB,@R1
MOVA,@RO
%MULT
MOV@RO,A
The program after macro expansion:
MOVB,@R1
MOVA,@RO
MULAB
JNB OV,($+6)
}
th'IS IS. the return vaI ue
LCALL OVFLERR
MOV@RO,A
Example 3:
Here is a macro that calls MUL T to mUltiply 5 bytes:
%"DEFINE(MULT_5)(
MOVR7,15
MOV RO,IADDR1
MOV R1,IADDR2
TOP:
MOV B,@R1
MOVA,@RO
%MULT
MOV@RO,A
INCRO
INCR1
DJNZR7,TOP
5-4
Macro Processing Language
MCS-51
This macro when called inserts the following code:
MOV R7,#5
MOV RO,#ADDR1
MOV R1,IIADDR2
TOP: MOV B,@R1
MOVA,@RO
MULAB
JNBOV,($+6)
LCALL OVFL_ERR
MOV@RO,A
INCRO
INC R1
DJNZR7,TOP
this is the return
} value of MULT
this is the return
value of MULT_5
Macros with Parameters
If the only thing the macro processor could do was simple string replacement, then it
would not be very useful for most programming tasks. Each time we wanted to
change even the simplest part of the macro's return value, we would have to redefine
the macro. Parameters in macro calls allow more general purpose macros.
Parameters leave blanks or holes in a macro body that you will fill in when you call
the macro. This permits you to design a single macro that produces code for many
typical programming operations.
The term parameter refers to both the formal parameters that are specified when the
macro is defined (the blanks), and the actual parameters or arguments that are
specified when the macro is called (the fill-ins).
The syntax for defining macros with parameters is very similar to the syntax for simple macros. The call-pattern that we described earlier actually includes both the
macro-name and an optional parameter-list. With this addition, the syntax for
defining simple macros becomes:
% *DEFINE(macro-name [parameter-list)) (macro-body)
The '0,7o*DEFINE' is required for the same reasons described earlier.
The macro-name must be a valid macro identifier.
The parameter-Jist is a list of macro identifiers separated by macro delimiters. This
comprises the formal parameters used in the macro. The macro identifier for each
parameter in the list must be unique.
Typically, the macro delimiters are parentheses and commas. When using these
delimiters, you would enclose the parameter list in parentheses and separate each
formal parameter with a comma. When you define a macro using parentheses and
commas as delimiters, you must use those same delimiters, when you call that
macro. The Advanced Concepts section completely describes the use of macro
delimiters. For now we will use parentheses and commas when defining macros.
The macro-body must be a balanced-text string. To indicate the locations of
parameter replacement (the holes to be filled in by the actual parameters), place the
parameter's name preceded by the metacharacter in the macro body. The
parameters may be used any number of times and in any order within the macro
body. If a user-defined macro has the same macro identifier name· as one of the
parameters to the macro, the macro may not be called within the macro body,
because the parameter takes precedence.
5-5
Macro Processing Language
The example below shows the definition of a macro with three dummy parametersSOURCE, DESTINATION, and COUNT. The macro will produce code to copy
any number of bytes from one part of memory to another.
%' DEFINE(MOVE_BYTES(SOURCE,DESTINATION .COUNT)) (
MOV R7.'%COUNT
MOV R1.'%SOURCE
MOV RO.'%DESTINATION
MOVA.@Rl
MOV@RO,A
INCRl
INCRO
DJNZ R7,($-4)
)
To call the above macro, you must use the metacharacter followed by the macro's
name similar to simple macros without parameters. However, a list of the actual
parameters must follow. The actual parameters must be surrounded by parentheses,
and separated from each other by commas, as specified in the macro definition. The
actual parameters must be balanced-text and may optionally contain calls to other
macros. A simple call to the macro defined above might be:
%MOVE_BYTES(8,16.8)
The above macro call produces the following code:
MOVR7.'8
MOV Rl.'8
MOV RO,'16
MOVA.@Rl
MOV@RO,A
INCRl
INCRO
DJNZ R7.($-4)
The code above will copy the contents of register bank 2 to register bank 3. (We
hope the user knows which bank is active when he executes this code.)
LOCAL Symbols List
The DJNZ instruction above uses offset addressing ($-4). If we chose to use a label
for the jump destination, the macro could only be used once, since a second macro
call would cause a conflict in label definitions. We could make the label a parameter
and specify a different ASM51 symbol name each time we call the macro. The best
way is to put the label in a LOCAL list. The LOCAL list construct allows you to use
macro identifiers to specify assembly-time symbols. Each use of a LOCAL symbol
in a macro guarantees that the symbol will be replaced by a unique assembly-time
symbol.
The macro processor increments a counter each time your program calls a macro
that uses the LOCAL construct. The counter is incremented once for each symbol in
the LOCAL list. Symbols in the LOCAL list, when used in the macro body, receive a
two to five digit suffix that is the hexadecimal value of the counter. The first time
you call a macro that uses the LOCAL construct, the suffix is '00' .
5-6
MCS-51
Mes-sl
Macro Processing Language
The syntax for the LOCAL construct in the DEFINE functions is shown below (This
is the complete syntax for the built-in function DEFINE):
% *DEFINE(macro-name[parameter-listJ) [LOCAL focaf-list] (macro-body)
The local-list is a list of valid macro identifiers separated by spaces. The LOCAL
construct in a macro has no affect on the syntax of a macro call.
The example below shows the MOVE_BYTES macro definition that uses a
LOCAL list:
% *DEFINE(MOVLBYTES(SOURCE, DESTINATION,COUNT)) LOCAL LABEL
(MOV R7,#%COUNT
MOV R1,#%SOURCE
MOV RO,#%DESTINATION
%LABEL: MOV A,@R1
MOV@RO,A
INCR1
INCRO
DJNZ R7, %LABEL
)
The following macro call:
%MOVE_BYTES(67,100,20)
might produce this code (if this is the eleventh call to a macro using a LOCAL list):
"
MOV R7,f27
MOV R1,f67
MOV RO,f100
LABELOA: MOV A,@R1
MOV@RO,A
INCR1
INCRO
DJNZ R7,LABELOA
NOTE
Since macro identifiers follow the same rules as ASM51, you can use any
macro identifier in a LOCAL list. However, if you use long identifier names
(31 characters or more), the appended call number will be lost when the
assembler truncates the excess characters.
The Macro Processor's Built-in Functions
The macro processor has several built-in or predefined macro functions. These
built-in functions perform many useful operations that would be difficult or
impossible to produce in a user-defined macro. An important difference between a
user-defined macro and a built-in function is that user-defined macros may be
redefined, while built-in functions can not be redefined.
We have already seen one of these built-in functions, DEFINE. DEFINE creates
user-defined macros. DEFINE does this by adding an entry in the macro processor's
table of macro definitions. Each entry in the table includes the call-pattern for a
macro, and its macro body. Entries for the built-in functions are present when the
macro processor begins operation.
5-7
Macro Processing Language
MeS-51
Other built-in functions perform numerical and logical expression evaluation, affect
control flow of the macro processor, manipulate character strings, and perform
console 110.
Comment, Escape, Bracket and METACHAR Built-in
Functions
Comment Function
The Macro Processing Language can be very subtle, and the operation of macros
written in a straightforward manner may not be immediately obvious. Therefore, it
is often necessary to comment your macro definitions. Besides, it's just good
programming practice.
The macro processor's comment function has the following syntax:
% 'text'
or
% 'text end-ot-line
The comment function always evaluates to the null string. Two terminating
characters are recognized, the apostrophe and the ·end-oi-Jine (line feed character,
ASCII OAH). The second form of the call allows you to spread macro definitions
over several lines, while avoiding any unwanted end-ai-Jines in the return value. In
either form of the comment function, the text or comment is not evaluated for
macro calls.
The example below shows a commented macro definition:
%*OEFINE(MOVE_BYTES(SOURCE,OESTINATION,COUNT)) LOCAL LABEL
(
MOV R7,#%COUNT %' iteration argument %COUNT'
MOV R1,#%SOURCE %' source address argument %SOURCE
MOV RO,#%OESTINATION %' destination address argument'
%LABEL %' %LABEL is a local symbol that will be appended with a unique number
MOV A,@R1
MOV@RO,A
INCR1
INCRO
OJNZ R7,%LABEL %'This is the same local symbol and
%' receives the same unique 10
Call to above macro:
%MOVE_BYTES(27H ,37H ,5)
Return value from above call:
MOVR7,#5
MOV R1,#27H
LABEL07: MOV A,@R1
MOV@RO,A
INCR1
INCRO
OJNZ R7,LABEL07
5-8
MOV RO,#37H
Macro Processing Language
MeS-51
Notice that the comments that were terminated with end-of-line removed the end-ofline character along with the rest of the comment. Because of this, the second line
has two instuctions on it. That line will produce an error when assembled. However,
when the comment was removed from the line containing the label %LABEL, the
colon was raised to the same line making it a legal instruction.
Note that the metacharacter is not recognized as a call to the macro processor when
it appears in the comment function.
Escape Function
Occasionally, it is necessary to prevent the macro processor from processing text.
There are two built-in functions that perform this operation: the escape function
and the bracket function.
The escape function interrupts the processor from its normal scanning of text. The
syntax for this function is shown below:
"Ion text-n-characters-Iong
The metacharacter followed by a single decimal digit designates that the specified
number of characters (maximum is 9) shall not be evaluated. The escape function is
useful for inserting a metacharacter as text, adding a comma as part of an argument,
or placing a single parenthesis in a character string that requires balanced
parentheses.
Several examples of the escape function are shown below:
Before Macro Expansion
After Macro Expansion
; COMPUTE 10%1% OF SUM
; COMPUTE 10% OF SUM
%MACCALL(JANUARY 23%1,1980,
MARCH 15%1, 1980,
APRIL 9% 1,1980)
JANUARY 23,1980
MARCH 15, 1980
APRIL 9, 1980
actual parameters
%MACCALL(1%1) ADD INPUTS,
2%1) DIVIDE BY INPUT COUNT,
3%1) GET INPUTS)
1) ADD INPUTS
2) DIVIDE BY INPUT COUNT
3) GET INPUTS
actual parameters
Bracket Function
The other built-in function that inhibits the macro processor from expanding text is
the bracket function. The syntax of the bracket function is shown below:
% (balanced-text)
The bracket function inhibits all macro processor expansion of the text contained
within the parentheses. However, the escape function, the comment function, and
parameter substitution are still recognized. Since there is no restriction for the length
of the text within the bracket function, it is usually easier to use than the escape
function. However, since balanced text is required and the metacharacter is interpreted, often this is not sufficient, and the escape function must be used.
Consider the following example of the bracket function.
%*DEFINE(DW(LlST,LBL)) (
%LBL: DW %LIST
)
5-9
MeS-51
Macro Processing Language
The macro above will add OW statements to the source file. It uses two parameters:
one for the statement label and one for the OW expression list. Without the bracket
function we would not be able to use more than one expression in the list, since the
first comma would be interpreted as the delimiter separating the macro parameters.
Bracket function permits more than one expression in the LIST argument:
%DW(%(198H, 3DBH, 163BH),PHONE)
-
PHONE: OW 198H, 3DBH, 163BH
In the example above, the bracket function prevents the character string '198H,
30BH, 163BH' from being evaluated as separate parameters.
METACHAR Function
The built-in function METACHAR allows you to redefine the metacharacter (0/0).
Its syntax is shown below:
%MET ACHAR(balanced-text)
The balanced-text argument may be any number of characters long. However, only
the first character in the string is taken to be the new metacharacter. Extreme caution should be taken when using MET ACHAR, since it can have catastrophic
effects. Consider the example below:
%METACHAR( & )
In this example, MET ACHAR defines the space character to be the new metacharacter, since it is the first character in the balanced-text string!
Numbers and Expressions in MPL
Many of the built-in functions recognize and evaluate numerical expressions in their
arguments. The macros use the same rules for representing numbers as ASMS1:
Numbers may be represented in base 2 (B suffix), base 8 (0 or Q suffix), base 10
•
(0 suffix or no suffix), and base 16 (H suffix).
• Internal representation of numbers is 16 bits (OOH to OFFFFH).
• All ASMSI operators are recognized, except the symbolic forms of the
relational operators (i.e., <, >, =, <>, >=, <=). The operators recognized by
the macro processor and their precedence is shown in the list below:
1.
2.
3.
4.
S.
6.
7.
8.
o.
HIGH,LOW
" I, MOD, SHL, SHR
+ , - unary and binary forms
EO, NE, LE, LT, GE, GT
NOT
AND
OR,XOR
Although assembly-time and macro-time expressions use the same operators, the
macro processor cannot access the assembler's symbol table. The values of labels
and SET and EQU symbols are not known during macro-time expression evaluation. Any attempt to use assembly-time symbols in a macro-time expression
generates an error. However, you can define macro-time symbols with the predefined macro SET.
5-10
Macro Processing Language
MeS-51
SET Macro
The SET predefined macro permits you to define macro-time symbols to values.
SET takes two arguments: a valid MPL identifier, and a macro-time numeric
expression.
SET has the following syntax:
%SET(macro-id ,expression)
SET assigns the value of the numeric expression to the identifier, macro-id.
macro-id must follow the same syntax conventions used for macro identifiers.
•
The first character must be a letter of the alphabet or a question mark or an
underscore.
•
The remaining characters may be digits, letters, question marks, or underscores.
•
Only the first 31 characters are recognized as the identifier name. Upper and
lower case letters are not distinguished.
The SET macro call affects the macro-time symbol table only; when it is
encountered in the source file, the macro processor replaces it with the null string.
Symbols defined by SET can be redefined by a second SET call, or defined as a
macro by a DEFINE call.
The following examples show several ways to use SET:
Before Macro Expansion
%SET(COUNT,O)
%SET(OFFSET,16)
MOV R1 ,II%COUNT + %OFFSET
MOV R4,II%COUNT
After Macro Expansion
null string
null string
MOV R1,IIOOH + 10H
MOV R4,IIOOH
The SET symbol may be used in the expression that defines its own value.
%SET(COUNT,%COUNT + %OFFSET)
%SET(OFFSET, %OFFSET • 2)
MOV R2,II%COUNT + %OFFSET
MOV R5,II%COUNT
null string
null string
MOV R2,1I10H + 20H
MOVR5,1I10H
In the example above, macro-time symbols are used rather than assembly-time
symbols because their value is shown wherever they are used. With assembly-time
symbols, you must look in the symbol table for its value.
SET is a predefined macro, not a built-in function; as such it may be redefined, but
we don't advise it.
EVAL Function
The built-in function EV AL accepts an expression as its argument and returns the
expression's value in hexadecimal. The syntax for EV AL is:
% EVAL(expression )
The expression argument must be a legal macro-time expression.
5-11
MeS-51
Macro Processing Language
The return-value from EV AL follows ASM51 's rules for representing hexadecimal
numbers (it has an 'H' suffix and when the leading digit is 'A', 'B', 'C', '0', 'E', or
'F', it is preceded by 0). EVAL always returns at least 3 characters even when the
argument evaluates to a single digit. The following examples show the return-value
from EVAL:
Before Macro Expansion
After Macro Expansion
MOV A.'%EVAL(1 +1); move two to A.
MOV A.'02H; move two toA.
COUNT EOU %EVAL(33H + 15H + OFOOH)
COUNT EOU OF48H
ADD A.'%EVAL(10H-((13 + 6)·2) + 7)
ADD A.'OFFOBH
%SET(NUM1,44)
%SET(NUM2,25H)
ANL A,'%EVAL(%NUM1 LE %NUM2)
-
ANL A,'OOH
Logical Expressions and String Comparisons in MPL
Several built-in functions return a logical value when they are called. Like relational
operators that compare numbers and return true or false (OFFFFH or OOH), these
built-in functions compare character strings. If the function evaluates to 'TRUE,'
then it returns the character string 'OFFF~H' (this represents a 16-bit value containing all ones). If the function evaluates to 'FALSE,' then it returns '~OH' (this
represents a 16-bit value containing all zeros).
The built-in functions that return a logical value compare two balanced-text string
arguments and return a logical value based on that comparison. The list of string
comparison functions below shows the syntax and describes the type of comparison
made for each. Both arguments to these functions may contain macro calls (the calls
are expanded before the comparison is made).
%EOS(arg1,arg2)
True if both arguments are identical
%NES(arg1,arg2)
True if arguments are different in any way
%LTS(arg1 ,arg2)
True if first argument has a lower value than second argument
% LES(arg1 ,arg2)
True if first argument has a lower value than second argument or if
both arguments are identical
%GTS(arg1,arg2)
True if first argument has a higher value than second argument
%G ES(arg1 ,arg2)
True if first argument has a higher value than second argument, or
if both arguments are identical
Before these funCtions perform a comparison, both arguments are completely
expanded. Then the ASCII value of the first character in the first string is compared
to the ASCII value of the first character in the second string. If they differ, then the
string with the higher ASCII value is greater. If the first characters are the same.
then the process continues with the second character in each string, and so on. Two
strings of equal length that contain the same characters in the same order are equal.
5-12
Macro Processing Language
MCS-Sl
The examples below show several calls to these macros:
Before Macro Expansion
After Macro Expansion
OOH
false
the space after the comma is part
of the second argument
%LTS(CBA,cba)
OFFFFH
true
the lower-case characters have a
higher ASCII value than uppercase
%GTS(11H,16D)
OOH
false
these macros compare strings not
numerical values ASCII '6' is
greater ASCII '1'
~OH
the space at the end of the second
argument makes the second
argument greater than the first
%EOS(ABC, ABC)
%GES(ABCDEFG,ABCDEFG )
false
As with any other macro, the arguments to the string comparison macros can be
other macros.
%*DEFINE(DOG) (CAT)
%*DEFINE(MOUSE) (%DOG)
%EOS(%DOG, %MOUSE)
OFFFFH
true
Control Flow Functions
Some built-in functions accept logical expressions in their arguments. Logical
expressions follow the same rules as numeric expressions. The difference is in how
the macro interprets the 16-bit value that the expression represents. Once the expression has been evaluated to a 16-bit value, MPL uses only the low-order bit to determine whether the expression is TRUE or FALSE. If the low-order bit is a one (the
16-bit numeric value is odd), the expression is TRUE. If the low-order bit is a zero
(the 16-bit value is even), the expression is FALSE.
Typically, you will use either the relational operators (EQ, NE, LE, LT, GT, or GE)
or the string comparison functions (EQS, NES, LES, LTS, GTS, or GES) to specify
a logical value. Since these operators and functions always evaluate (0 OFFFFH (all
ones) or OOH (all zeros), you needn't worry about the single bit test. But remember,
all numeric expressions are valid, and regardless of the value of the other 15 bits,
only the least significant bit counts.
IF Function
The IF built-in function evaluates a logical expression, and based on that expression,
expands or witholds its text arguments. The syntax for the IF macro is shown below:
• %IF (expression) THEN (balanced-text1) [ELSE (balanced-text2)] FI
IF first evaluates the expression, if the low order bit is one, then balanced-textl is
expanded; if the low order bit is zero and the optional ELSE clause is included in the
call, then balanced-text2 is expanded. If the low order bit is zero and the ELSE
clause is not included, the IF call returns the null string. FI must be included to terminate the call.
5-13
Macro Processing Language
MeS-51
IF calls can be nested; when they are, the ELSE clause refers to the most recent IF
call that is still open (not terminated by FI). FI terminates the most recent IF call
that is still open.
Several examples of IF calls are shown below:
This is the simple form of the IF call with an ELSE clause.
%IF (%EOS(ADD,%OPERATION)) THEN (ADD A,R1) ELSE (SUBB A,R1) FI
This is an example of several nested IF calls.
open first IF
open second IF
open third IF
close third IF
close second IF
close first IF
%IF (%EOS(ADD,%OPERATION)) THEN (ADD A,R1
)ELSE (%IF (%EOS(SUBTRACT,%OPERATlON)) THEN (SUBB A,R1
)ELSE(MOV B,R1
%IF (%EOS(MULTIPLY,%OPERATION)) THEN (MUL AB
)ELSE (DIV AB
) FI
)FI
)FI
WHILE Function
The IF macro is useful for implementing one kind of conditional assemblyincluding or excluding lines of code in the source file. However, in many cases this is
not enough. Often you may wish to perform macro operations until a certain condition is met. The built-in function WHILE provides this facility.
The syntax of the WHILE macro is shown below:
%WHILE (expression) (balanced-text)
WHILE first evaluates the expression. If the least significant bit is one, then the
balanced-text is expanded; otherwise, it is not. Once the balanced-text has been
expanded, the logical argument is retested and if the least significant bit is still one,
then the balanced-text is again expanded. This continues until the logical argument
proves false (the least significant bit is 0).
Since the macro continues processing until expression is false, the balanced-text
should modify the expression, or else WHILE may never terminate.
A call to the built-in function EXIT will always terminate a WHILE macro. EXIT is
described below.
The following examples show two common uses of the WHILE macro:
%SET(COUNTER,5)
%WHILE(%COUNTER GT 0)
(RRA
%SET(COUNTER, %COUNTER -1)
)
%WHILE(%LOC_COUNTER LT OFFFFH) ( NOP
%SET(LOC_COUNTER, %LOC_COUNTER + 1) )
These examples use the SET macro and a macro-time symbol to count the iterations
of the WHILE macro.
5-14
Macro Processing Language
MeS-51
REPEAT Function
MPL offers another built-in function that will perform the counting automatically.
The built-in function REPEAT expands its balanced-text a specified number of
times. The general form of the call to REPEAT is shown below:
%REPEAT (expression) (balanced-text)
Unlike the IF and WHILE macros, REPEAT uses the expression for a numerical
value that specifies the number of times the balanced-text will be expanded. The
expression is evaluated once when the macro is first called, then the specified
number of iterations is performed.
The examples below will perform the same text insertion as the WHILE examples
above.
%REPEAT (5) (RR A
)
%REPEAT (OFFFFH - %LOC_COUNTER) (NOP
)
EXIT Function
The EXIT built-in function terminates expansion of the most recently called
REPEAT, WHILE or user-defined macro. It is most commonly used to avoid
infinite loops (e.g., a WHILE expression that never becomes false, or a recursive
user-defined macro that never terminates). It allows several exit points in the same
macro.
The syntax for EXIT is:
%EXIT
Several examples of how you might use the EXIT macro follow:
This use of EXIT terminates a recursive macro when an odd number of bytes are
being added.
%*DEFINE (MEM_ADD_MEM (SOURCE,DESTIN,BYTES))
(
MOVA,%SOURCE
ADDC A, %DESTIN
MOV %DESTIN,A
IF (%BYTES EQ 1) THEN (%EX1T) FI
MOV A,%SOURCE + 1
ADDC A, %DESTIN + 1
MOV %DESTIN + 1, A
IF (%BYTES GT 2) THEN (
%MEM_ADD_MEM(%SOURCE + 2, %DESTIN + 2, %BYTES -2» FI
)
This EXIT is a simple jump out of a recursive loop.
%*DEFINE(UNTIL (CONDITION, BODY»
( %BODY
%IF (%CONDITION) THEN (%EXIT)
ELSE (%UNTIL(%CONDITION,%BODY» FI
5-15
MeS-51
Macro Processing Language
String Manipulation Built-in Functions
The purpose of the Macro Processor is to manipulate character strings. Therefore,
there are several built-in functions that perform common character string manipulation functions.
LEN Function
The built-in function LEN takes a character string argument and returns the length
of the character string in hexadecimal (the same format as EV AL). The character
string argument to LEN is limited to 256 characters.
The syntax of the LEN macro call is shown below:
%LEN(balanced-text)
Several examples of calls to LEN and the hexadecimal numbers returned are shown
below:
Before Macro Expansion
After Macro Expansion
%LEN(ABCDEFGHIJKLMNOPQRSTUVWXYZ)
1AH
%LEN(A,B,C)
OSH
%LEN()
OOH
%*DEFINE(CHEESE)(MOUSE)
%*DEFINE(DOG)(CAT)
%LEN(%DOG %CHEESE)
A the space after G is counted
as part of the length
commas are counted
... 09H
SUBSTR Function
The built-in function SUBSTR returns a substring of its text argument. The macro
takes three arguments: a character string to be divided and two numeric arguments.
The syntax of the macro call to SUBSTR is shown below:
%SU BSTR(balanced-text ,expression 1 ,expression2)
balanced-text is described above. It may contain macro calls.
expression! specifies the starting character of the substring.
expression2 specifies the number of characters to be included in the substring.
If expression! is zero or greater than the length of the argument string, then
SUBSTR returns the null string.
If expression2 is zero, then SUBSTR returns the null string. If expression2 is greater
than the remaining length of the string, then all characters from the start character
to the end of the string are included.
5-16
Macro Processing Language
MCS-Sl
The examples below show several calls to SUBSTR and the value returned:
Before Macro Expansion
After Macro Expansion
%SUBSTR(ABCDEFG,8,1)
null
%SUBSTR(ABCDEFG,3,0)
null
%SUBSTR(ABCDEFG,5,1)
E
%SU BSTR(ABCDEFG ,5,100)
EFG
%SUBSTR(123(56)890,4,4)
(56)
MATCH Function
The built-in function MATCH searches a character string for a delimiter character,
and assigns the substrings on either side of the delimiter to the identifiers. The syntax of the MATCH call is shown below:
%MATCH(identifier1 delimiter identifier2) (balanced-text)
identifier1 and identifier2 are valid MPL identifiers.
delimiter is the first character to follow identifierl . Typically, a space or comma is
used, but any character that is not a macro identifier character may be used. You
can find a more complete description of delimiters in the Advanced Concepts section
at the end of the chapter.
balanced-text is as described earlier in the chapter. It may contain macro calls.
MATCH searches the balanced-text string for the specified delimiter. When the
delimiter character is found, then all characters to the left of it are assigned to identifier 1 and all characters to the right are assigned to identifier2. If the delimiter is
not found, the entire balanced-text string is assigned to identifierl and the null
string is assigned to identifier2 .
The following example shows a typical use of the MATCH macro.
%MATCH(NEXT,LlST) (10H, 20H, 30H)
%WHILE(%LEN(%NEXT) NE 0) (
MOVA,%NEXT
ADDA,1#22H
MOV%NEXT,A
%MATCH(NEXT , LlST)(% LIST)
Produces the following code:
first
iteration
of WHILE
second
iteration
of WHILE
~
third
iteration
of WHILE
}
MOVA,10H
ADDA,1#22H
MOV10H,A
}
MOVA, 20H
ADDA,1#22H
MOV 20H,A
}
MOVA,30H
ADDA,1#22H
MOV 30H,A
5-17
Macro Processing Language
Console 1/0 Built-in Functions
There are two built-in functions that perform console I/O when expanded: IN and
OUT. Their names describe the function each performs. IN outputs a greater than
character '>' as a prompt to the console, and returns the next line typed at the console. OUT outputs a string to the console; .a call to OUT is replaced by the null
'
string. The syntax of both macros is shown below:
%IN
%OUT(balanced-text)
Several examples of how these macros can be used are shown below:
%OUT(ENTER NUMBER OF PROCESSORS IN SYSTEM?)
%SET(PROC_COUNT, %IN)
%OUT(ENTER THIS PROCESSOR'S ADDRESS?)
ADDRESS EOU %IN
%OUT(ENTER BAUD RATE?)
%SET(BAUD, %IN)
The following lines would be displayed at the console:
ENTER NUMBER OF PROCESSORS IN SYSTEM?>userresponse
ENTER THIS PROCESSOR'S ADDRESS?>user response
ENTER BAUD RATE?>userresponse
Advanced MPL Concepts
For most programming problems, the Macro Processing Language syntax described
above is sufficient. However, in some cases a more complete description of the
macro processor's function is necessary.
However, it is impossible to describe all of the subtleties of the macro processor in a
single chapter. With the rules described in this section, you should be able to discern,
with a few simple tests, the answer to any specific question about MPL. ,
Macro Delimiters
When we discussed the syntax for defining macros, we showed one type of delimiter.
The parameter-list was surrounded by parentheses, and parameters were separated
by commas. Because we used these delimiters to define a macro, a call to the macro
required that these same delimiters be used. When we discussed the MATCH function, we mentioned that a space could be used as a delimiter. In fact the macro' processor permits almost any character or group of characters to be used as a delimiter.
Regardless of the type of delimiter used to define a macro, once it has been defined,
only the delimiters used in the definition can be used in the macro call. Macros
defined with parentheses and commas require parentheses and commas in the macro
call. Macros defined with spaces (or any other delimiter), require that delimiter
when called.
Macro delimiters can be divided into three classes: implied blank delimiters. identifier (or id) delimiters. and literal delimiters.
5-18
MeS-51
Macro Processing Language
MCS-Sl
Implied Blank Delimiters
Implied blank delimiters are the easiest to use and contribute the most readability
and flexibility to macro calls and definitions. An implied blank delimiter is one or
more spaces, tabs or new lines (a carriage-return/linefeed pair) in any order. To
define a macro that uses the implied blank delimiter, simply place one or more
spaces, tabs, or new lines surrounding the parameter list and separating the formal
parameters.
When you call the macro defined with the implied blank delimiter, each delimiter
will match a series of spaces, tabs, or new lines. Each parameter in the call begins
with the first non-blank character, and ends when a blank character is found.
An example of a macro defined using implied blank delimiters is:
%*DEFINE(SENTENCE SUBJECT VERB OBJECT) (THE %SUBJECT %VERB %OBJECT.)
All of the following calls are valid for the above definition:
Before Macro Expansion
After Macro Expansion
%SENTENCE TIME IS RIPE
%SENTENCE CATS
EAT
FISH
-
THE TIME IS RIPE
-
THECATSEATFISH
-
THE PEOPLE LIKE FREEDOM
%SENTENCE
PEOPLE
LIKE
FREEDOM
Identifier Delimiters
Identifier (ld) delimiters are legal macro identifiers designated as delimiters. To
define a macro that uses an id delimiter in its call pattern, you must prefix the
delimiter with the commercial at symbol (@). You must separate the id delimiter
from the macro identifiers (formal parameters or macro name) by a blank character.
When calling a macro defined with id delimiters, an implied blank delimiter is
required to precede the id delimiter, but"none is required to follow the id delimiter.
An example of a macro defined with id delimiters is:
%*DEFINE(ADD P1 @TOP2@ANDP3)(
MOVA~%P1
ADDA,%P2
MOV%P2,A
MOVA,%P1
ADDA,%P3
MOV%P3,A
5-19
MeS-51
Macro Processing Language
The following call (note that no blank character follows the id delimiters TO and
AND):
%ADD ATOM TOMOLECULE ANDCRYSTAL
returns this code when expanded:
MOVA,ATOM
ADD A,MOLECULE
MOV MOLECULE,A
MOVA,ATOM
ADD A,CRYSTAL
MOV CRYSTAL,A
Literal Delimiters
The delimiters used when we documented user-defined macros (parentheses and
commas) were literal delimiters. A literal delimiter can be any character except the
metacharacter.
When you define a macro using a literal delimiter, you must use exactly that
delimiter when you call the macro. If you do not include the specified delimiter
character as it appears in the definition, it will generate a macro error.
When defining a macro, you must literalize the delimiter string, if the delimiter you
wish to use meets any of the following conditions:
uses more than one character,
,.
•
uses a macro identifier character (A-Z, 0-9, _, or 7),
uses a commercial at (@),
•
•
uses a space, tab, carriage-return, or linefeed,
You can use the escape function (%n) or the bracket function (%(» to literalize the
delimiter string. Several examples of definitions and calls using a variety of literal
delimiters are shown below:
This is the simple form shown earlier:
Before Macro Expansion
After Macro Expansion
%*DEFINE(MAC(A,B» (%A
%MAC(4,5)
-
null string
-
4
%B)
5
In the following example brackets are used instead of parentheses. The commercial
at symbol separates parameters:
% *DEFINE(MOV[A %(@)B]) (MOV %A, %B)
%MOV[PO@Pt]
..... null string
..... MOVPO,P1
In the next two examples, delimiters that could be id delimiters have been defined as
literal delimiter (the differences are noted):
%*DEFINE(ADD (A%(AND)B»(ADD %A,%B)
%ADD#27H)
null string
ADDA,127H
Spaces around AND are considered as part of the argument string.
5-20
Macro Processing Language
MCS-Sl
To illustrate the differences between between id delimiters and literal delimiters,
consider the following macro definition and call. (A similar macro definition is discussed with id delimiters):
%*DEFINE(ADD P1(TO)P2 %AND) P3) (
MOVA,%P1
ADD A,%P2
MOV%P2,A
MOVA,%P1
ADD A,%P3
MOV%P3,A
The following call:
%ADD ATOM TOMOLECULE ANDCRYSTAL
returns this code when expanded (the TO in ATOM is recognized as the delimiter):
MOVA,A
ADD A,M TOMOLECULE
MOV M TOMOLECULE,A
MOVA,A
ADD A,CRYSTAL
MOV CRYSTAL,A
Literal vs. Normal Mode
In normal mode, the macro processor scans text looking for the metacharacter.
When it finds one, it begins expanding the macro call. Parameters are substituted
and macro calls are expanded. This is the usual operation of the macro processor,
but sometimes it is necessary to modify this mode of operation. The most common
use of the literal mode is to prevent macro expansion. The literal character in
DEFINE prevents the expansion of macros in the macro-body until you call the
macro.
When you place the literal character in a DEFINE call, the macro processor shifts to
literal mode while expanding the call. The effect is similar to surrounding the entire
call with the bracket function. Parameters to the literalized call are expanded, the
escape, comment, and bracket functions are also expanded, but no further processing is performed. If there are any calls to other macros, they are not expanded.
If there are no parameters in the macro being defined, the DEFINE built-in function
can be called without the literal character. If the macro uses parameters, the macro
processor will attempt to evaluate the formal parameters in the macro-body as
parameterless macro calls.
The following example illustrates the difference between defining a macro in literal
mode and normal mode:
%SET(TOM ,1)
%*DEFINE(AB) (%EVAL(% TOM))
%DEFINE(CD) (%EVAL(% TOM))
5-21
Mes-sl
Macro Processing Language
When AB and CD are defined, TOM is equal to 1. The macro body of AB has not
been evaluated due to the literal character, but the macro body of CD has been completely evaluated, since the literal character is not used in the definition. Changing
the value of TOM has no effect on CD, but it changes the return value of AB, as
illustrated below:
Before Macro Expansion
After Macro Expansion
%SET(TOM,2)
%AB
%CD
-
02H
01H
The macros themselves can be called with the literal character. The return value
then is the unexpanded body:
%*CD
%*AB
-
01H
%EVAL(%TOM)
The literalized calls to AB and CD show that CD evaluates to 01H, while AB contains a macro call to EV AL with 070 TOM as its parameter.
Algorithm for Evaluating Macro Calls
The Algorithm the macro processor uses for evaluating the source file can be seen in
6 steps:
1. Scan source until metacharacter is found.
2. Isolate call pattern. See note below.
3. If macro has parameters, expand each parameter from left to right (initiate step
one on actual parameter), before expanding next parameter.
4. Substitute actual parameters for formal parameters in macro body.
S. If literal character is not used, initiate step one on macro body.
6. Insert result into output stream.
NOTE
When isolating the call pattern, the macro processor is actually scanning input for the specified delimiter. All text found between delimiters
is considered the actual parameter. For this reason Id delimiters need
not be terminated by spaces in a call, and the 'TO' in 'ATOM' satisfied
the literal delimiter, when the 'M TOMOLECULE 'became the second
parameter.
The terms 'input stream' and 'output stream' are used, because the return value of
one macro may be a parameter to another. On the first iteration, the input stream is
the source file. On the final iteration, the output stream is the temporary workfile
that passes to the assembler.
The examples below illustrate the macro processor's evaluation algorithm:
%SET(TOM,3)
% *DEFINE(STEVE)(%SET(TOM;% TOM-1) % TOM)
%*DEFINE(ADAM(A,B» (
DB %A, %B, %A, %B, %A, %B
)
5-22
Mes-sl
Macro Processing Language
Here is a call ADAM in the normal mode with TOM as the first actual parameter
and STEVE as the second actual parameter. The first parameter is completely
expanded before the second parameter is expanded. After the call to ADAM has
been completely expanded, TOM will have the value 02H.
Before Macro Expansion
After Macro Expansion
%ADAM(% TOM, %STEVE)
-
DB 03H, 02H, 03H, 02H, 03H, 02H
Now reverse the order of the two actual parameters. In this call to ADAM, STEVE
is expanded first (and TOM is decremented) before the secolld parameter is
evaluated. Both parameters have the same value.
%SET(TOM,3)
%ADAM(%STEVE, % TOM)
-
DB 02H, 02H, 02H, 02H, 02H, 02H
Now we will literalize the call to STEVE when it appears in the first actual
parameter. This prevents STEVE from being expanded until it is inserted in the
macro body, then it is expanded for each replacement of the formal parameters.
Tom is evaluated before the substitution in the macro body.
%SET(TOM,3)
%ADAM(% ·STEVE, % TOM)
-
DB 02H, 03H, 01H, 03H, OOH, 03H
5·23
CHAPTER 6
ASSEMBLER OPERATION
AND CONTROLS
This chapter describes how to invoke the MCS-Sl Macro Assembler from your
Intellec System running under the ISIS operating system. The assembler controls are
also fully described.
How to Invoke the MeS-51 Macro Assembler
The command to invoke the assembler is shown below:
[:Fn:]ASM51 [:Fn:]sourcefile[.extension] [controls]
You must specify the filename of the assembler ([:Fn:]ASMSl) and the filename of
your source code ([:Fn :]sourcefile[.extension]. The controls are optional.
ASMSI normally produces two output files. One contains a formatted listing of
your source code. Unless you specify a particular filename with the PRINT control,
it will have the same name as your source file, but with the extension 'LST'. The
format for the listing file and how to change that format will be described in Chapter
7. The other file produced by the assembler is the object file. Unless you specify a
particular filename with the OBJECT control, it will also have the same name as
your source file, but its extension will be 'OBJ'.
For example note the assembler invocation below.
-ASM51 PROG.SRC
If there were no controls in PROG.SRC that changed the default output files,
ASMSI would produce two files. The listing file will be :FO:PROG.LST, and the
object file will be :FO:PROG.OBJ.
In addition to the output files, ASMSI uses intermediate files named
ASMSlx.TMP. They will be deleted before the assembler completes execution.
Normally these files will be created on the same drive as your source program;
however, you can specify the drives to be used with the WORKFILES control.
Any control (except INCLUDE) can be used in the invocation line.
You can continue the invocation line on one or more additional lines by typing an
ampersand (&) before you type a carriage return. ASMSI prompts for the remainder
of the invocation line by issuing a double asterisk followed by a blank (** ). Since
everything following an ampersand on a line is echoed, but ignored, you can comment the invocation line; these comments are echoed in the listing heading. (See
Chapter 7 for an example.) Note the example below:
-ASM51 PROG.SRC
DATE(9-30-B1) & Comment
•• TITLE(COMPLETE PROJECT REV. 3.0) & Comment
•• GEN
Errors detected in the invocation line are considered fatal and the assembler aborts
without processing the source program.
6-1
Assembler Operation and Controls
Assembler Controls
Assemble controls may be entered in the invocation line as described above or on a
control line in your source code. The general format for control lines is shown
below:
SControl List [; Comment]
The dollar sign ($) must be the first character on the line. The control list is zero or
more controls separated by one or more spaces or tabs. The comment is optional.
ASM51 has two classes of controls: primary and general. The primary controls are
set in the invocation line or the primary control lines and remain in effect
throughout the assembly. For this reason, primary controls may only be used in the
invocation line or in a control line at the beginning of the program. Only other
control lines (that do not contain the INCLUDE control) may precede a line containing a primary control. The INCLUDE control terminates processing of primary
controls.
If a Primary Control is specified in the invocation line and in the primary control
lines, the first time counts. This enables the programmer to override primary controls via the invocation line.
The general controls are used to control the immediate action of the assembler.
Typically their status is set and modified during an assembly. Control lines containing only general controls may be placed anywhere in your source code.
Table 6-1 lists all of the controls, their abbreviations, their default values, and a
'brief description of each.
Table 6-1. Assembler Controls
Name
6-2
Prlmaryl
General
Default
Abbrev.
Meaning
DATE(date)
P
DATE()
DA
Places string in header (max
9 characters)
DEBUG
P
NODEBUG
DB
Outputs debug symbol
Information to object file
NODE BUG
P
NODB
Symbol information not
placed in object file
EJECT
G
Not Applicable
EJ
Continue listing on next
page
ERRORPRINT[(FILE)]
P
NOERRORPRINT
EP
Designates a file to receive
error messages in addition
to the listing file defaults to
:co:
NOERRORPRINT
P
NOEP
Designates that error messages will be printed in
listing file only
GEN
G
GENONLY
G
GENONLY
GE
Generates a full listing of the
macro expansion pr~ess
including macro calls In the
listing file
GO
List only the fully expanded
source as if all lines generated by a macro call were
already In source file
MCS-Sl
Assembler Operation and Controls
Table 6-1. Assembler Controls (Cont'd.)
Name
Primaryl
General
Default
Abbrev.
NOGE
Meaning
List only the original source
text in listing file
NOGEN
G
GENONLY
INCLUDE(FILE)
G
Not Applicable
IC
DeSignates a file to be
included as part of the
program
LIST
G
LIST
LI
Print subsequent lines of
source in listing file
NOLIST
G
MACRO[ (mempercent)]
P
NOMACRO
P
OBJECT[(FILE)]
P
NOOBJECT
P
PAGING
P
NOPAGING
P
PAGELENGTH(n)
P
PAGEWIDTH(n)
MACRO(50)
OBJECT(source .OBJ)
NOLI
Do not print subsequent
lines of source in listing file
MR
Evaluate and expand all
macro calls. Allocate
percentage of free memory
for macro processing
NOMR
Do not evaluate macro calls
OJ
Designate file to receive
object code
NOOJ
DeSignates that no object
file will be created
PI
Designates that listing will
be broken into pages and
each will have a header
NOPI
DeSignates that listing will
contain no page breaks
PAGELENGTH(60)
Pl
Sets maximum number of
lines in each page of listing
file (maximum = 65,535)
(minimum = 10)
P
PAGEWIDTH(120)
PW
Sets maximum number of
characters in each line of
listing file (maximum = 132;
minimum = 80)
PRINT[(FILE)]
P
PRINT(source. LST)
PR
DeSignates file to receive
source listing
NOPRINT
P
NOPA
DeSignates that no listing
file will be created
SAVE
G
SA
Stores current control setting for LIST and GEN
RESTORE
G
RS
Restores control setting
from SAVE stack
REGISTERBANK(rb, ... )
rb = 0,1, 2, 3
P
RB
Indicates one or more banks
used in program module
NOREGISTERBANK
P
SYMBOLS
P
PAGING
Not Applicable
REGISTERBANK(O)
SYMBOLS
NORB
Indicates that no banks are
used.
SB
Creates a formatted table of
all symbols used in program
NOSYMBOLS
P
NOSB
No symbol table created
TITLE(string)
G
TITLE( )
TT
Places a string in all subsequent page headers
(maximum 60 characters)
WORKFILES(:Fn:[,:Fm:])
P
same drive as
source file
WF
DeSignates alternate drives
for temporary workfiles
XREF
P
NOXREF
XR
Creates a cross reference
listing of all symbols used in
program
NOXREF
P
NOXR
No cross reference list
created
6-3
MCS-Sl
Assembler Operation and Controls
Control Definitions
Control Switch Name:
DATE
Abbreviation:
DA
Arguments:
(string)
(Nine characters maximum)
Control Class: Primary
Default:
(Spaces inserted)
Definition:
The assembler takes the character string specified as the argument
and inserts it in the header. I f you specify less than 9 characters,
then it will be padded with blanks. If more than 9 characters are
specified, then the character string will be truncated to the first
nine characters. DATE is overridden by NOPRINT.
NOTE
Any parentheses in the DATE string must be balanced.
$TITLE(PROJECT S.W.B. REV. 27)
Example:
DATE(S-1S-S1 )
(Header will/ook like this)
MCS-S1 MACRO ASSEMBLER PROJECT S.W.B. REV. 27
Control Switch Name:
8-18-81 PAGE 1
DEBUG/NODEBUG
Abbreviation:
DB/NODB
Arguments:
None
Control Class: Primary
Default:
NODE BUG
Definition:
Indicates whether debug symbol information shall be output to
object file. If DEBUG is in effect the debug information will be
output. This control must be used if you wish to.run the program
with an ICE-51.
DEBUG is overridden by NOOBJECT.
Example:
6-4
$DEBUG
Assembler Operation and Controls
MCS-51
Control Switch Name:
Abbreviation:
EJ
Arguments:
None
EJECT
Control Class: General
Default:
(New page started when PA GEL ENG TH reached)
Definition:
Inserts formfeed into listing file, after the control line containing
the EJECT, and generates a header at top of the next page. The
control is ignored if NO PAGING , NOPRINT, or NOLIST is in
effect.
Example:
$EJECT
Control Switch Name:
ERROR PRINT INOERRORPRINT
Abbreviation:
EP/NOEP
Arguments:
(Filename)
optional.)
(Indicates file to receive error messages-argument
Control Class: Primary
Default:
NOERRORPRINT
Definition:
When ERRORPRINT is in effect, indicates that all erroneous
lines of source and the corresponding error message shall be output to the specified file. This will not inhibit errors from being
placed in listing file. If no argument is specified to
ERRORPRINT, then erroneous lines and error messages will be
displayed at the console.
Example:
$ERRORPRINT
6-5
MCS-51
Assembler Operation and Controls
Control Switch Name:
GEN/GENONLY/NOGEN
Abbreviation:
GE/GO/NOGE
Arguments:
None
Control Class: General
Default:
GENONLY
Definition:
NOGEN indicates that only the contents of the source file shall be
output to the listing file with macro call expansion not shown.
Expansion will take place, but source lines generated will not be
displayed in listing file, only the macro call.
GENONL Y indicates that only the fully expanded macro calls will
appear in the listing. The listing file appears as if the expanded
text was originally in the source file with no macro calls. The
macro calls will not be displayed, but the source lines generated by
the calls will be in the listing file.
GEN indicates that each macro call shall be expanded showing
nesting of macro calls. The macro call and the source lines
generated by the macro call will be displayed in the listing file.
These controls are overridden by NOPRINT and NOLIST. (See
Chapter 7 for examples of a macro calls listed with GEN,
GENONLY and NOGEN in effect.)
Example:
$NOGEN
Control Switch Name:
INCLUDE
Abbreviation:
IC
Arguments:
(Filename) (Identifies file to be included into program)
Control Class: General
Default:
Not applicable.
Definition:
Inserts the contents of the file specified in the argument into the
program immediately following the control line. INCLUDE files
may be nested.
The INCLUDE control may not appear in the invocation line,
and it terminates processing of primary controls in the source.
Example:
6-6
$INCLUDE(:F1 :IOPACK.SRC)
Assembler Operation and Controls
MCS-Sl
Control Switch Name:
Abbreviation:
Ll/NOLI
Arguments:
None
LIST INOLIST
Control Class: General
Default:
LIST
Definition:
Indicates whether subsequent lines of source text shall be
displayed in listing file. A LIST control following a NOLIST will
not be displayed, but listing will continue with the next sequential
line. NOPRINT overrides LIST.
NOTE
Lines causing errors will be listed when NOLIST is in
effect.
Example:
C~ntrol
$NOLIST
Switch Name:
MACRO I NOMACRO
Abbreviation:
MR/NOMR
Arguments:
(mempercent) (Optional. Indicates the percentage of the free
memory to be used for macro processing.)
Control Class: Primary
Default:
MACRO(50)
Definition:
Indicates whether macro calls shall be expanded. If NOMACRO
is specified all macro calls will not be processed as macros. The
NOMACRO control will free additional symbol table space for
user-defined symbols.
Example:
$NOMACRO
$MACRO(30)
6-7
Assembler Operation and Controls
Control Switch Name:
MCS-51
OBJECT/NOOBJECT
Abbreviation:
OJ I NOOJ
Arguments:
(Filename)
optional.)
(Indicates file to receive object code-argument
Control Class: Primary
Default:
OBJECT(sourcefile.OBJ)
Definition:
Indicates whether object code shall be generated, and if so, the
file that will receive it. If you do not specify the argument, the
object file will be sourcefile.OBJ.
Example:
$OBJECT(:F1 :FINAL.REV)
Control Switch Name:
Abbreviation:
PI/NOPI
Arguments:
None
PAGING/NOPAGING
Control Class: Primary
Default:
PAGING
Definition:
Indicates whether page breaks shall be included in listing file. If
NOPAGING, then there will be no page breaks in the file, and
lines will appear listed consecutively. A single header will be
included at the top of the file. EJECT and PAGELENGTH
controls will be ignored.
If PAGING, a form feed and a page header will be inserted into
the listing file whenever the number of lines since the last page
break equals the PAGELENGTH value, or an EJECT control is
encountered. The header includes the assembler designation, the
name of the source file, the TITLE and DATE strings (if
specified), and the page number.
Example:
6-8
$ NOPAGING
Assembler Operation and Controls
MCS-51
Control Switch Name:
Abbreviation:
PL
Arguments:
(n)
PAGELENGTH
(Decimal number greater than 9.)
Control Class: Primary
Default:
PAGELENGTH(60)
Definition:
Indicates the maximum number of printed lines on each page of
the listing file. This number includes the page heading. The
minimum value for PAGELENGTH is 10. Values less than 10 will
be treated as 10. The maximum value permitted in the argument is
65,535.
Example:
$
PAGELENGTH(132)
Control Switch Name:
Abbreviation:
PW
Arguments:
(n)
PAGEWIDTH
(Number indicates maximum characters per line.)
Control Class: Primary
Default:
PAGEWIDTH(120)
Definition:
Indicates the maximum number of characters printed on a line in
the listing file. The range of values permitted is from 80 to 132;
values less than 80 are set to 80; values greater than 132 are set to
132.
Listing lines that exceed the P AGEWIDTH value will be wrapped
around on the next lines in the listing, starting at column 80.
Example:
$
PAGEWIDTH(80)
MCS-Sl
Assembler Operation and Controls
Control Switch Name:
PRINT / NOPRINT
Abbreviation:
PR/NOPR
Arguments:
(Filename)
(Indicates file to receive assembler listingargument optional.)
Control Class: Primary
. Default:
PRINT(sourcefile. LST)
Definition:
Indicates whether formatted source listing shall be generated,
and, if so, what file will receive it. If you do not specify the argument, the listing file will be sourcefile.LST. NOPRINT indicates
no listing file will be made.
Example:
-ASM51 PROG.SRC PRINT(:LP:) & print listing at line printer
**
Control Switch Name:
'Abbreviation:
SA/RS
Arguments:
None
SAVE/RESTORE
Control Class: General
Default:
Not applicable
Definition:
Permits you to save and restore the state of the LIST and GEN
controls. SAVE stores the setting of these controls on the SAVE
stack, which is internal to the assembler. RESTORE restores the
setting of the controls to the values most recently saved, but not
yet restored. SAVEs can be nested to a depth of 8.
NOTE
SAVE uses the values that were in effect on the line prior
to the SAVE control line. Therefore, if the LIST control
is in effect and the assembler encounters a control line
containing NOLIST and SAVE (in any order on the line),
the status LIST is saved on the stack. (The lines following
the control line are not listed until a LIST or RESTORE
is encountered.)
Example:
6-10
$save
MCS-Sl
Assembler Operation and Controls
Control Switch Name:
REGISTERBANK / NOREGISTERBANK
Abbreviation:
RB / NORB
Arguments:
(rb, ... )
rb=O,1,2,or3
(One or more of the permissabJe bank
numbers separated by commas.)
Control Class: Primary
Default:
REGISTERBANK(O)
Definition:
Indicates the register banks used in the program module. This
information is transferred to the RLS I and used for allocation of
register bank memory. NORB specifies that no memory is initially
reserved for register banks. Note that the USING directive also
reserves register banks.
Example:
REGISTERBANK(O,1)
Control Switch Name:
SYMBOLS/NOSYMBOLS
Abbreviation:
SB/NOSB
Argument:
None
Control Class: Primary
Default:
SYMBOLS
Definition:
Indicates whether a symbol table shall be listed. NOSYMBOLS
indicates no symbol table. SYMBOLS causes the table to be
listed. NOSYMBOLS is overridden by XREF. SYMBOLS is overridden by NOPRINT. (See Chapter 7 for an example symbol table
listing.)
Example:
$NOSYMBOLS
6-11
MCS-Sl
Assembler Operation and Controls
Control Switch Name:
TITLE
Abbreviation:
IT
Arguments:
(string) (Up to 60 characters.)
Control Class: General
Default:
(Spaces Inserted)
Definition:
Permits you to include a title for the program. It will be printed in
the header of every subsequent page. Titles longer than 60
characters will be truncated to the first 60 characters. (See
Chapter 7 for an example of the title in the header.)
NOTE
Any parentheses in the TITLE string must be balanced.
Example:
$TITLE(Final Production Run)
Control Switch Name:
WORKFILES
Abbreviation:
WF
Arguments:
(:Fm:[,:Fn:]) (Drives to use for temporary work files-second
argument optional. )
Control Class: Primary
6-12
Default:
Drive that contains source file.
Definition:
Indicates drives to be used to contain temporary workfiles. If two
drives are specified, the work files are split between them roughly
equally. If only one drive is specified, then all work files will be
placed on that drive. All work files are deleted before normal
termination.
Example:
-ASM51 :F1:BIGPR.SRC WORKFILES(:F4:,:F5:)
MCS-Sl
Assembler Operation and Controls
Control Switch Name:
XREF/NOXREF
Abbreviation:
XR I NOXR
Arguments:
None
Control Class:
Primary
Default:
NOXREF
Definition:
Indicates that a cross reference table of the use of symbols shall be
added to the symbol table. Each cross reference table will list the
line numbers of the lines that define the value of a symbol, and all
of the lines that reference the symbol. A hash mark (#) follows the
numbers of the lines that define the symbols value. XREF is overridden by NOPRINT. (See Chapter 7 for an example of a symbol
table listing with XREF.)
Example:
$XREF
6-\3
CHAPTER 7
ASSEMBLER OUTPUT: ERROR
MESSAGES AND LISTING FILE FORMAT
This chapter discusses the meaning of error messages issued by ASM51. The format of the
listing file is also described.
Error Messages and Recovery
All error messages issued by ASM51 are either displayed on the console or listed in the
listing file. Fatal errors, such as invocation line errors, are listed at the console and cause
ASM51 to abnormally terminate. Errors detected in the source file do not cause the
assembler to abort and usually allow at least the listing to continue.
Console Error Messages
Upon detecting certain catastrophic conditions with the system hardware, or in the invocation line or one of the primary control lines, ASM51 will print an informative message
at the console and abort processing.
These errors fall into three broad classes: I/O errors, internal errors and invocation line
errors.
A list of these fatal control error messages and a description of the cause of each is shown
below.
1/0 Errors
I/O error messages print with the following format:
ASM51 110 ERRORFILE: file type
NAME: file name
ERROR: ISIS error number and brief description
ASM51 TERMINATED
The list of possible file types is:
SOURCE
PRINT
OBJECT
INCLUDE
ERRORPRINT
ASM51 WORKFILE
ASM51 OVERLAY number
The list of possible error numbers is:
4-ILLEGAL PATH NAME
5-ILLEGAL OR UNRECOGNIZED DEVICE IN PATH
9-DIRECTORY FULL
12-ATTEMPTTO OPEN ALREADY OPEN FILE
13-NO SUCH FILE
14-WRITE PROTECTED FILE
22-0UTPUT MODE IMPOSSIBLE FOR SPECIFIED FILE
23-NO FILENAME SPECIFIED FOR A DISK FILE
2S-NULL FILE EXTENSION
7-1
Assembler Output: Error Messages and Listing File Format
ASM51 Internal Errors
The ASM5l internal errors indicate that an internal consistency check failed. A
likely cause is that one of the files containing the assembler's overlays was corrupted
or that a hardware failure occurred. If the problem pers(sts, contact Intel Corporation via the Software Problem report.
These messages print in the following format:
•••• ASM51 INTERNAL ERROR: message
Be sure to include the exact text of the message on the problem report.
Invocation Line Errors
The invocation line error messages print in the following format:
ASM51 FATAL ERROR-
error message
The possible error messages are:
NO SOURCE FILE FOUND IN INVOCATION
If ASM5l scans the invocation line and cannot find the source file name, then this
error will be issued and assembly aborted.
UNRECOGNIZABLE SOURCE FILE NAME
If the first character after "ASM5l" on the invocation line is not an "&" or a file
character (Le., ":", letter, digit, ". "), then ASM5l issues this error and aborts.
ILLEGAL SOURCE FILE SPECIFICATION
If the source file is not a legal file name (does not conform to the ISIS-II rules for a
path name), then this error is issued.
SOURCE TEXT MUST COME FROM A FILE
The source text must always come from a file, not devices like :TI: or :LP:.
NOT ENOUGH MEMORY
If there is not enough memory in your SERIES-II or MDS 800, then this error
message will print out and ASM5l will abort.
If identical files are specified:
_ AND _ FILES ARE THE SAME
where the "_" can be any of SOURCE, PRINT, OBJECT, and ERRORPRINT. It
doesn't make sense for any of these files to be the same.
BAD WORKFILES COMMAND
If a WORKFILES control has no parameters (Le., devices) or a device specification
is incorrect, this error message is issued.
BAD WORKFILES SYNTAX
7-2
MeS-51
Assembler Output: Error Messages and Listing File Format
MCS-Sl
If ASM51 encounters anything other than a "," or a ")" when it is looking for the
next work file, then this error is issued.
BAD PAGELENGTH
BAD PAGEWIDTH
The parameter to pagelength and pagewidth must be a decimal number. The number
may have leading and trailing blanks, but if there are any other extra characters in
the parameter, then this error will be issued.
PAGElENGTH MISSING A PARAMETER
PAGEWIDTH MISSING A PARAMETER
DATE MISSING A PARAMETER
These commands require parameters. If there is nO parameter, then assembly is
aborted.
CANNOT HAVE INCLUDE IN INVOCATION
The INCLUDE command may appear only in the source text. Don't forget that
command lines in the source file can contain primary commands, but only if they are
the very first lines in the file. Also, if One of these lines has an INCLUDE on it, then
that ends the primary command lines.
EOl ENCOUNTERED IN PARAMETER
A parameter in the ill vocation line is missing a right parenthesis.
COMMAND TOO lONG
A command word longer than 128 characters-very unlikely.
IllEGAL CHARACTER IN INVOCATION
There was an illegal character in the invocation line-usually a typing error. (See
error 403.)
UNRECOGNIZED COMMAND:
This message is issued if a problem occurs in the invocation.
NO PARAMETER AllOWED WITH control
The control specified may not be associated with the parameter.
TITLE MISSING A PARAMETER
The TITLE control was specified without the title string itself as a parameter.
TOO MANY RESTORES
More RESTORE controls encountered than the respective SAVE controls.
NO PARAMETER GIVEN FOR "REGISTERBANKS"
The REGISTERBANKS control was specified without the register bank numbers
as parameters.
ERROR IN PARAMETER LIST FOR "REGISTERBANKS"
The parameter list of the REGISTERBANKS control contains an error.
7-3
Assembler Output: Error Messages and Listing File Format
Listing File Error Messages
ASM51 features an advanced error~reporting mechanism. Some messages pinpoint
the symbol or character at which the error was detected. Error messages printed in
the source file are inserted into the listing after the lines on which the errors were
detected.
They are of the following format:
••• ERROR lIeee, LINE 11//1 (Ppp) , message
where:
eee
//I
ppp
message
is the error number
is the number of the line on which the error occurred
is the line containing the last previous error
is the English message corresponding to the error number
If the error is detected in pass 2, the clause "(PASS 2)" precedes the message.
"(MACRO)" precedes the message for macro errors; "(CONTROL)" precedes the
message for control errors.
Errors which refer to character or symbol in a particular line of the source file do so
by printing a pointer to the first item in the line that is not valid; e.g.:
A
The up arrow or vertical bar points to the first incorrect character in the line.
Error messages that appear in the listing file are given numbers. The numbers correspond to classes of errors. The classes of errors and the numbers reserved for these
classes is shown in the list below:
o300
400
800
900
-
99
399
499
899
999
Source File Errors
Macro Errors
Control Errors
Special Assembler Errors
Fatal Errors
Errors numbered less than 800 are ordinary. non-fatal errors. Assembly of the error
line can usually be regarded as suspect, but subsequent lines will be assembled. If an
error occurs within a macro definition, the definition does not take place.
Source File Error Messages
There follows a list of the error messages generated by ASM51, ordered by error
number .
••• ERROR 111 SYNTAX ERROR
This message is preceded by a pointer to the character at which the syntax error
was detected.
7-4
MeS-51
Assembler Output: Error Messages and Listing File Format
MeS-51
ASM51 contains an internally-encoded grammar of the MCS-51 assembly
language and requires your program to conform to that grammar. The syntax
error is recognized at the item indicated in the error message; e.g.,
... TEMPSER10
A
gives a syntax error at the S. "SER" is unrecognized. However, sometimes the
error is not detected until one or more characters later; e.g.,
... SETBEQU 1
A
gives a syntax error at "EQU" . The error is that SETB is already defined as an
instruction. The assembler interprets the line as a SETB instruction with
"EQU 1" as the operand field. Since the keyword "EQU" is not a legal
operand the "EQU" is flagged, even though the "SETB" is the user's
mistake.
ASM51 discards the rest of the line when it finds a syntax error .
••• ERROR 112 SOURCE LINE LISTING TERMINATED AT 255 CHARACTERS
Listing of the source line was stopped at 255 characters. The entire line was
interpreted, only the listing is incomplete .
••• ERROR.3 ARITHMETIC OVERFLOW IN NUMERIC CONSTANT
This error is reported whenever the value expressed by a constant exceeds the
internal representation of the assembler (65,535) .
••• ERROR .4 ATTEMPT TO DIVIDE BY ZERO
This error occurs when the right hand side of a division or MOD operator
evaluates to zero .
••• ERROR.5 EXPRESSION WITH FORWARD REFERENCE NOT ALLOWED
Forward references are permitted only in the expression argument to DB, DW,
and machine instructions. Change the expression to remove the forward
reference, or define the symbols earlier in the program .
••• ERROR.6 TYPE OF SET SYMBOL DOES NOT ALLOW REDEFINITION
This error occurs when the symbol being defined in a SET directive is a
predefined assembler symbol or has been previously defined not using SET
directive. For example, the following lines would cause this error on the
second line.
SKIP_1:ADDA,R1
SKIP_1 SET 22D
••• ERROR'7 SYMBOL ALREADY DEFINED
This message is given when the symbol has already been defined. To correct
this error, use a different symbol name .
••• ERROR '8 ATTEMPT TO ADDRESS NON-BIT-ADDRESSABLE BIT
7-5
Assembler Output: Error Messages and Listing File Format
This error is caused when the left hand side of the bit selector (.) is not one of
the bit addressable bytes. (See errors 40 and 9.) Figure 2-2 shows all bitaddressable bytes. Several examples of lines that would cause this type of error
are shown below.
JB 10H.5,LOOP
CLR7FH.0
MOV C,OAFH.3
••• ERROR 19 BAD BIT OFFSET IN BIT ADDRESS EXPRESSION
This error is caused when the right hand side of the bit selector (.) is out of
range (0-7). The assembler uses 0 in its place. The byte address, if correct,
remains the same. (See errors 8, and 40.) Several examples of lines that would
generate this error are shown below.
CLR25H.10
SETB 26H.5 + 4
CPLPSW.-1
••• ERROR '10 TEXT FOUND BEYOND END STATEMENT -IGNORED
This is a warning-there are no ill effects. The extra text appears in the listing
file, but it is not assembled .
••• ERROR 111 PREMATURE END OF FILE (NO END STATEMENT)
There are no ill effects from omitting the END statement, other than this
message .
••• ERROR '12 ILLEGAL CHARACTER IN NUMERIC CONSTANT
Numeric constants begin with decimal digits, and are delimited by the first
non-numeric character. The set of legal characters for a constant is determined
by the base:
1.
2.
3.
4.
Base 2:
Base 8:
Base 10:
Base 16:
0,1, and the concluding B.
0-7, and the concluding Q or O.
0-9, and the concluding 0 or null.
0-9, A-F, and the concluding H .
••• ERROR '13 ILLEGAL USE OF REGISTER NAME IN EXPRESSION
This error is caused by placing a forward reference symbol, defined as a
register, in a numeric expression. An example of this type of error is shown
below:
DBREGO
REGOEQU RO
••• ERROR '14 SYMBOL IN LABEL FIELD ALREADY DEFINED
You can define a label only once in your program. If the symbol name has
been defined anywhere else in the program this error will be generated .
••• ERROR '15 ILLEGAL CHARACTER
This message is preceded by a pointer to the illegal character.
7-6
MeS-51
Assembler Output: Error Messages and Listing File Format
MeS-51
A character that is not accepted by ASM51 was found in the input file. Either
it is an unprintable ASCII character, in which case it is printed as an up arrow
e'), or it is printable but has no function in the assembly language. Edit the
file to remove the illegal character .
••• ERROR 116 MORE ERRORS DETECTED, NOT REPORTED
After the ninth source file Error on a given source line, this message is given
and no more errors are reported for that line. Normal reporting resumes on the
next source line. (See errors 300 and 400.)
••• ERROR 117 ARITHMETIC OVERFLOW IN LOCATION COU NTER
This error is reported whenever the DS, DBIT, or ORG directive attempts to
increase the location counter beyond the limits of the current address space.
This may occur, for example, in CSEG when instructions cause the location
counter to increment above 65,535 .
••• ERROR #18 UNDEFINED SYMBOL
This error is reported when an undefined symbol occurs in an expression. Zero
is used in its place-this may cause subsequent errors .
••• ERROR 119 VALUE WILL NOT FIT INTO A BYTE
"
This error is issued whenever the expression used for a numeric operand that is
encoded as a single byte is not in the range -256 to +255 .
••• ERROR 120 OPERATION INVALID IN THIS SEGMENT
This error will occur if you use the DBIT directive not in a BIT type segment;
or a DS directive in a BIT type segment, or if you attempt to initialize memory
(use DB, DW, or a machine instruction) in a segment with different type than
CODE .
••• ERROR #21 STRING TERMINATED BY END-OF-LiNE
All strings must be completely contained on one line .
••• ERROR 122 STRING LONGER THAN 2 CHARACTERS NOT ALLOWED IN THIS CONTEXT
Outside of the DB directive all strings are treated as absolute numbers; hence,
strings of 3 or more characters are overflow quantities. If this error occurs in a
DW directive, you probably should be using DB .
••• ERROR 123 STRING, NUMBER, OR IDENTIFIER CANNOT EXCEED 255 CHARACTERS
The maximum length of a character string (including surrounding quotes), a
number, or an identifier is 255 characters .
••• ERROR 124 DESTINATION ADDRESS OUT OF RANGE FOR IN BLOCK REFERENCE
This error is caused by specifying an address that is outside the current 2K byte
block. The current block is defined by the five most significant bits of the
address-of the next instruction.
7-7
Assembler Output: Error Messages and Listing File Format
MCS-Sl
••• ERROR 125 DESTINATION ADDRESS OUT OF RANGE FOR RELATIVE REFERENCE
A relative jump has a byte range (-128 to +127) from the instruction that
follows the jump instruction. Any address outside of this range will generate
this error. You can correct this error in one of two ways: if the jump has a
logical complement (e.g., JC and JNC), the following change could be made:
JCTOP
to
JNCSKIP
JMPTOP
SKIP:
If the instruction has no logical complement, then the following change could
be made
DJNZRO, TOP
to
DJNZ RO, SKIP_1
JMPSKIP_2
SKIP_1: JMPTOP
SKIP-2:
••• ERROR 126 SEGMENT SYMBOL EXPECTED
The error occurs when the symbol specified by the RSEG directive is not a segment symbol, i.e., is not defined previously using the SEGMENT directive .
••• ERROR 127 ABSOLUTE EXPRESSION EXPECTED
The error occurs when the operand to the following directives is not absolute:
OS, OBIT, USING, CSEG, XSEG, OSEG, BSEG, and ISEG. In addition, the
bit-offset in a byte. bit form should also be absolute .
••• ERROR 128 REFERENCE NOT TO CURRENT SEGMENT
The error occurs in two cases: if a relocatable expression in an ORG directive
does not specify the current active segment; or if the absolute expression specifying the base address in a segment select directive is not of the correct segment
type.
Examples
RSEG CODE_SEG1
CODE_SYM1: DB 1
RSEG DAT A_SEG1
ORG CODE_SYMB1
;error'28
CODLSYMB2 CODE 200H
DSEG AT CODE_SYM2
;error 128
••• ERROR 129IDATA SEGMENT ADDRESS EXPECTED
The symbol specified on the left hand side of the bit selector(.) is not segment
type OAT A, or not in a bit-addressable relocatable type segment. The nuDn!ric
value is used if possible, but may cause other errors. (See errors 37 and 8.)
••• ERROR 130 PUBLIC ATIRIBUTE NOT ALLOWED FOR THIS SYMBOL
Occurs if the user attempts to define as public either segment symbols, external
symbols, or predefined symbols .
••• ERROR 131 EXTERNAL REFERENCE NOT ALLOWED IN THIS CONTEXT
7-8
Assembler Output: Error Messages and Listing File Format
MeS-51
••• ERROR 132 SEGMENT REFERENCE NOT ALLOWED IN THIS CONTEXT
Occurs if an external/segment symbol appears in a symbol definition directive
(EQU, SET, DATA, etc.); or in contexts when absolute expressions are
required (see error #27) .
••• ERROR 1133 TOO MANY RELOCAT ABLE SEGMENTS
The maximum number of relocatable segments has been exceeded .
••• ERROR 134 TOO MANY EXTERNAL SYMBOLS
The maximum;number of relocatable segments has been exceeded .
••• ERROR 1135 LOCATION COUNTER MAY NOT POINT BELOW SEGMENT BASE
Occurs if the user attempts, using the ORG directive, to set the location
counter below the beginning of the current absolute segment.
Example
CSEG AT 200H
ORG 1FFH
;starts an absolute segment at 200H
;error 1135
••• ERROR #36 CODE SEGMENT ADDRESS EXPECTED
••• ERROR #37 DATA SEGMENT ADDRESS EXPECTED
••• ERROR 1138 XDATA SEGMENT ADDRESS EXPECTED
••• ERROR 1139 BIT SEGMENT ADDRESS EXPECTED
These errors are caused by specifying a symbol with the wrong segment type in
an operand to an instruction. The numeric value of that symbol is used, but it
may cause subsequent errors (e.g., error 17) .
••• ERROR 1140 BYTE OF BIT ADDRESS NOT IN BIT ADDRESSABLE DATA SEGMENT
The symbol specified on the left hand side of the bit selector (.) is not segment
type DATA, or not in a bit-addressable relocatable type segment. The numeric
value is used if possible, but may cause other errors. (See errors 37 and 8.)
••• ERROR 1141 INVALID HARDWARE REGISTER
The data address specified in the expression points to an unidentified location
in the hardware register space (128 to 255) .
••• ERROR #42 BAD REGISTER BANK NUMBER
The register bank number specified for the USING directive should be in the
range of 0 to 3.
••• ERROR #43 INVALID SIMPLE RELOCATABLE EXPRESSION
Symbol definition directives such as EQU, SET, DATA, CODE, etc., require
a simple relocatable expression (or a special register symbol in the EQU/SET
case). See Chapter 2 .
••• ERROR #44 INVALID RELOCATABLE EXPRESSION
The relocatable expression specified violates the rules of relocatable expressions as given in Chapter 2.
7-9
Assembler Output: Error Messages and Listing File Format
••• ERROR ##45INPAGE RELOCATED SEGMENT OVERFLOW
••• ERROR ##46INBLOCK RELOCATED SEGMENT OVERFLOW
••• ERROR ##47 BITADDRESSABLE RELOCATED SEGMENT OVERFLOW
The relocatability of the current active segment specifies a limited segment
size: INPAGE = maximum 256 bytes; INBLOCK = 2048 bytes;
BITADDRESSABLE = 16 bytes.
.
••• ERROR ##48 ILLEGAL RELOCATION FOR SEGMENT TYPE
The segment type and relocatability of the defined segment is an invalid combination. See Chapter 4 on segment definition directive.
Macro Error Messages
Error messages with numbers in the 300's indicate macro call/expansion errors.
Macro errors are followed by a trace of the macro call/expansion stack-a series of
lines which print out the nesting of macro calls, expansions, INCLUDE files, etc.
Processing resumes in the original source file, with all INCLUDE files closed and
macro calls terminated .
••• ERROR ##300 MORE ERRORS DETECTED, NOT REPORTED
After 100 Macro or Control Errors on a given source line, this message is given
and no more errors are reported for that line. Normal reporting resumes on the
next source line. If the last error reported is a Macro Error, then this' message
will be issued. (See errors 16 and 400.)
••• ERROR ##301 UNDEFINED MACRO NAME
The text following a metacharacter (070) is not a recognized user function name
or built-in function. The reference is ignored and processing continues with the
character following the name .
••• ERROR ##302 ILLEGAL EXIT MACRO
The built-in macro "EXIT" is not valid in this context. The call is ignored. A
call to "EXIT" must allow an exit through a user function, or the WHILE or
REPEA T built-in functions .
••• ERROR ##303 FATAL SYSTEM ERROR
Loss of hardware and/or software integrity was discovered by the macro
processor. Contact Intel Corporation .
••• ERROR ##304 ILLEGAL EXPRESSION
A numeric expression was required as a parameter to one of the built-in
macros EVAL, IF, WHILE, REPEAT, and SUBSTR. The built-in function
call is aborted, and processing continues with the character following the
illegal expression .
••• ERROR #305 MISSING "FI" IN "IF"
The IF built-in function did not have a FI terminator. The macro is processed,
but may not be interpreted as you intended.
7-10
MeS-51
Assembler Output: Error Messages and Listing File Format
MCS-Sl
••• ERROR '306 MISSING "THEN" IN "IF"
The IF built-in macro did not have a THEN clause following the conditional
expression clause. The call to IF is aborted and processing continues at the
point in the string at which the error was discovered .
••• ERROR '307 ILLEGAL ATTEMPT TO REDEFIN E MACRO
It is illegal for a built-in function name or a parameter name to be redefined
(with the DEFINE or MATCH built-ins). Also, a user function cannot be
redefined inside an expansion of itself .
••• ERROR '308 MISSING IDENTIFIER IN DEFINE PATTERN
In DEFINE, the occurrence of "@" indicated that an identifier type delimiter
followed. It did not. The DEFINE is aborted and scanning continues from the
point at which the error was detected .
••• ERROR '309 MISSING BALANCED STRING
A balanced string "(... )" in a call to a built-in function is not present. The
macro function call is aborted and scanning continues from the point at which
the error was detected .
••• ERROR #310 MISSING LIST ITEM
In a built-in function, an item in its argument list is missing. The macro function call is aborted and scanning continues from the point at which the error
was detected .
••• ERROR #311 MISSING DELIMITER
A delimiter required by the scanning of a user-defined function is not present.
The macro function call is aborted and scanning continues from the point at
which the error was detected.
This error can occur only if a user function is defined with a call pattern containing two adjacent delimiters. If the first delimiter is scanned, but is not
immediately followed by the second, this error is reported .
••• ERROR #312 PREMATURE EOF
The end of the input file occurred while the call to the macro was being
scanned. This usually occurs when.a delimiter to a macro call is omitted, causing the macro processor to scan to the end of the file searching for the missing
delimiter.
Note that even if the closing delimiter of a macro call is given, if any preceding
delimiters are not given, this error may occur, since the macro processor
searches for delimiters one at a time.
"'ERROR #313 DYNAMIC STORAGE (MACROS OR ARGUMENTS) OVERFLOW
Either a macro argument is too long (possibly because of a missing delimiter),
or not enough space is available because of the number and size of macro
definitions. All pending and active macros and INCLUDE's are popped and
scanning continues in the primary source file. Increase the mempercent
parameter of the MACRO control to overcome this error.
7·11
Assembler Output: Error Messages and Listing File Format '
u.
ERROR .314 MACRO STACK OVERFLOW
The macro context stack has overflowed. This stack is 64 deep and contains an
entry for each of the following:
1. Every currently active input file (primary source plus currently nested
INCLUDE's).
2. Every pending macro call, that is, all calls to macros whose arguments are
still being scanned.
3. Every active macro call, that is,all macros whose values or bodies are
currently being read. Included in this category are various temporary
strings used during the expansion of some built-in macro functions.
The cause of this error is excessive recursion in macro calls, expansions, or
INCLUDE's. All pending and active macros and INCLUDE's are popped and
scanning continues in the primary source file .
••• ERROR .315 INPUT STACK OVERFLOW
The input stack is used in conjunction with the macro stack to save pointers to
strings under analysis. The cause and recovery is the same as for the macro
stack overflow .
••• ERROR .317 PATTERN TOO LONG
An element of a pattern, an identifier or delimiter, is longer than 31
characters, or the total pattern is longer than 255 characters. The DEFINE is
aborted and scanning continues from the point at which the error was
detected .
••• ERROR .318 ILLEGAL METACHARACTER: "char"
The MET ACHAR built-in function has specified a character that cannot
legally be used as a metacharactet: a blank, letter, digit, left or right parenthesis, or asterisk. The current metacharacter remains unchanged .
••• ERROR .319 UNBALANCED ")" IN ARGUMENT TO USER DEFINED MACRO
During the scan of a user-defined macro, the parenthesis count went negative,
indicating an unmatched right parenthesis. The macro function call is aborted
and scanning continues from the point at which the error was detected .
••• ERROR .320 ILLEGAL ASCENDING CALL
Ascending calls are not permitted in the macro language. If a call is not complete when the end of a macro expansion is encountered, this message is issued
and the call is aborted. A macro call beginning inside the body of a userdefined or built-in macro was incompletely contained inside that body,
possibly because of a missing delimiter for the macro call.
7-12
MCS-Sl
Assembler Output: Error Messages and Listing File Format
MCS-Sl
Control Error Messages
Control error messages are issued when something is wrong with a control line in the
source file. Command language errors, when they occur in the invocation line or in a
primary control line, are fatal. However, the errors listed below are not considered
fatal. (See INVOCATION LINE ERRORS, described above.)
••• ERROR .400 MORE ERRORS DETECTED, NOT REPORTED
After 100 Macro or Control Errors on a given source line, this message is given
and no more errors are reported for that line. Normal reporting resumes on the
next source line. If the last error reported is a Control Error, then this message
will be issued. (See errors 16 and 300.)
••• ERROR .401 BAD PARAMETER TO CONTROL
What appears to be the parameter to a control is not correctly formed. This
may be caused by the parameter missing a right parenthesis or if the parentheses are not correctly nested .
••• ERROR .402 MORE THAN ONE INCLUDE CONTROL ON A SINGLE LINE
ASM51 allows a maximum of one INCLUDE control on a single line. If more
than one appears on a line, only the first (leftmost) is included, the rest are
ignored .
••• ERROR .403 ILLEGAL CHARACTER IN COMMAND
"
When scanning a command line, ASM51 encountered an invalid character.
This error can be caused for a variety of reasons. The obvious one is that a
command line was simply mistyped. The following example is somewhat less
obvious:
$TITLE(,1 )-GO')
The title parameter ends with the first right parenthesis, the one after the digit
1. The title string is '" 1". The next character "-" is illegal and will get error
403. The next two characters, "GO", form a valid command (the abbreviation
for GENONL Y) which will cause the listing mode to be set. The final two
characters "')" will each receive error 403 .
••• ERROR .406 TOO MANY WORKFILES - ONLY FIRST TWO USED
This error occurs when you specify more than two devices in the parameters to
the WORKFILES control. Only the first two are used and the remaining list of
devices is ignored until the next right parenthesis .
••• ERROR .407 UNRECOGNIZED CONTROL OR MISPLACED PRIMARY CONTROL:
The indicated control is not recognized as an ASM51 control in this context. It
may be misspelled, mistyped, or incorrectly abbreviated.
A misplaced primary control is a likely cause of this error. Primary control
lines must l:?e· at the .start of the source file, preceding all non-control lines
(even comments and blank lines).
7-13
MeS-51
Assembler Output: Error Messages and Listing File Format
••• ERROR .408 NO TITLE FOR TITLE CONTROL
This error is issued if the title control has no parameter. The resulting title will
be a string of blanks .
••• ERROR .409 NO PARAMETER ALLOWED WITH ABOVE CONTROL
The following controls do not have parameters:
EJECT
SAVE
RESTORE
LIST
NOLIST
GENONLY
GEN
NOOBJECT
NOPRINT
NOPAGING
DEBUG
NODEBUG
NOERRORPRINT
NOGEN
NOMACRO
PAGING
SYMBOLS
NOSYMBOLS
XREF
NOXREF
If one is included, then this error will be issued, and the parameter will be
ignored .
••• ERROR .410 SAVE STACK OVERFLOW
The SAVE stack has a depth of eight. If the program tries to save more than
eight levels, then this message will be printed .
••• ERROR .411 SAVE STACK UNDERFLOW
If a RESTORE command is executed and there has been no corresponding
SAVE command, then this error will be printed.
••• ERROR '413 PAGEWIDTH BELOW MINIMUM, SET TO 80
The minimum pagewidth value is 80. If a pagewidth value less than 80 is given,
80 becomes the new pagewidth .
••• ERROR '414 PAGELENGTH BELOW MINIMUM, SET TO 10
The minimum number of printed lines per page is 10. If a value less than 10 is
requested, 10 becomes the new pagelength .
••• ERROR 1415 PAGEWIDTH ABOVE MAXIMUM, SET TO 132
The maximum pagewidth value is 132. If a value greater than 132 is requested
then, 132 becomes the new pagewidth.
Special Assembler Error Messages
Error messages in the 800's should never occur. If you get one of these error
messages, please notify Intel Corporation via the Software Problem Report included
with this manual. All of these errors are listed below:
•••
•••
•••
•••
•••
•••
'·14
ERROR '800 UNRECOGNIZED ERROR MESSAGE NUMBER
ERROR 1801 SOURCE FILE READING UNSYNCHRONIZED
ERROR '802 INTERMEDIATE FILE READING UNSYNCHRONIZED
ERROR '803 BAD OPERAND STACK POP REQUEST
ERROR 1804 PARSE STACK UNDERFLOW
ERROR .805 INVALID EXPRESSION STACK CON FIGURATION
c,
Assembler Output: Error Messages and Listing File Format
MeS-51
Fatal Error Messages
Errors numbered in the 900's are fatal errors. They are marked by the line
" ••• FATAL ERROR ••• "
preceding the message line. Assembly of the source code is halted. The remainder of
the program is scanned and listed, .but not assembled .
••• ERROR '900 USER SYMBOL TABLE SPACE EXHAUSTED
You must either eliminate some symbols from your program, or if you don't
use macros, the NOMACRO control will free additional symbol table space .
••• ERROR '901 PARSE STACK OVERFLOW
••• ERROR #902 EXPRESSION STACK OVERFLOW
This error will be given only for grammatical entities far beyond the complication seen in normal programs .
••• ERROR #903 INTERMEDIATE FILE BUFFER OVERFLOW
This error indicates that a single source line has generated an excessive amount
of information for pass 2 processing. In practical programs, the limit should
be reached only for lines with a gigantic number of errors - correcting other
errors should make this one go away .
••• ERROR #904 USER NAME TABLE SPACE EXHAUSTED
This error indicates that the sum of the number of characters used to define the
symbols contained in a source file exceeds the macro processor's capacity. Use
shorter symbol names, or reduce the number of symbols in the program.
Assembler Listing File Format
The MCS-51 assembler, unless overridden by controls, outputs two files: an object
file and a listing file. The object file contains the machine code. The listing file contains a formatted copy of your source code with page headers and, if requested
through controls (SYMBOL or XREF), a symbol table.
MCS-51 MACRO ASSEM5LER
SAMPLE
PAGE
ISIS-II MCS-51 MACRO ASSEM5LER V2.0
JBJ:CT MODULE PLACEn IN :F1:SAMP1.0BJ
ASSEMBLER INVOKED BY:
LOC
~3J
ASM51 :F1:SAMP1.A51 nESUG
LINE
1
S:JURCE
NAME
SA"!?L~
2
0000
;)000 758920
0003 758003
OC06 75~8DA
put_string, put_data_str,
ascbin)
3
=XT~N
~ode
(put_~rlf,
4
EXTRN
~ode
(bin~s~,
5
,
/)
CSEG
7
B
;
;
get_num)
This is the initializing section. Execution always
st~rts at address 0 on power-up_
..,
ORG
10
a
m~v
T,,!OO,~C0100000B
11
mov
TH1,#(-253)
12
~ov
SCON,#11011010B
; set timer mode to auto-reload
; set timer for 110 BAUD
; prepare the Serial Port
Figure 7-1. Example Listing File Format
7-15
Assembler Output: Error Messages and Listing File Format
"CS·51 MACRO ASSEM8LER
LOC
LINE
08J
0009 028:
0006 900000
OilOE 120000
0011 120000
13
14
15
16
17
18
F
F
F
0014
0017
001A
0010
001F
0022
90JOOO
120000
120000
7800
120000
120000
0025
0020
0026
002E
0030
J033
900000
120000
120000
7800
120000
120000
F
;:
F
F
;:
0036
0038
0038
0030
7900
120000
7900
120000
F
F
F
F
F
F
F
F
F
F
F
0040 e500
0042 2500
0044 F500
F
0046 7900
0048 120000
F
0048
004E
0051
0053
0055
0058
900000
120000
7900
7A04
120000
8081
0008
0000
0004
0008
0000
0004
0008
OOOC
0010
0014
0018
001A
54595045
205E5820
544F2052
45545950
45204120
4E554042
4552
00
F
F
F
F
F
F
F
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
01
62
63
64
05
66
67
68
69
70
SAMPLE
SOURCE
; sta,.t clock
setb TII1
; This is the main p,.og"am. It"s an infinite loop,
; whe,.e each ite,.ation P,.o.pts the console fo,. 2
; input numoe,.s and types out thei" sum.
START:
; type .essage explaining how to co,.,.ect a typo
moy OPT~,.typo.msg
call put.st,.ing
call put.crlf
; ~et fi,.st numbe" f,.om console
mov JPTR,.num'.msg
call put.string
call put.crlf
mov RO,/Jnum1
call get.num
call put.c,.lf
; get second numbe,. f,.om console
moy O~TR"num2.ms;
call put.st,.ing
call put.c,.lf
moy RO,'num2
call get.num
call put.c,.lf
; convert the ASCII nUllbe,.s to bina,.y
IIOY
Rl"nulI'
call ascbin
moy Rl,'nu .. 2
call ascbin
; add the 2 numbers, and sto,.e the ,.esults in SUM
moy a,nu .. 1
add a,num2
"oy SUIl, ..
; ~onve,.t SUM f,.o .. bina,.y to ASCII
moy R,,'sum
call binasc
; output sum t9 console
moy DPTR,"sum.ms;
call put.st,.ing
.ov R1"sum
IIOV
R2,.4
call put.data.st,.
j.p sta,.t
DSEG .t 8
STACK: ds 8
OATA.AREA
~ONSTANT_AREA
•
RSEG
NUM1:
NUM2:
SUM:
; at po.e,.·up the stack point.,. il
;initl.lized to point he,..
segment DATA
segment CODE
data.a,.e.
ds 4
ds 4
ds 4
RSEG constant.a,.ea
TYPO."SG: db "TYPE ·X TO RETYPE A NUMBER",OOH
Figure 7·1. Example Listing File Format (Cont'd.)
7-16
MCS-Sl
Assembler Output: Error Messages and Listing File Format
MeS-51
MC5·51 MACRO ASSEMBLER
0016
OOH
0023
0027
002B
Jil2F
:lJ31
:l032
0036
003A
J03E
0042
0046
0049
JJ4A
004:
0052
OJ55
54595045
20494E20
46495253
54204E55
40424552
3A20
00
54595045
20494E20
53 .. 5434"
4E442J4E
55404245
523A20
00
54484520
53554020
495320
00
SAMPLE
71
NUM1.MSG: db 'TYPE IN FIRST NUMBER: ',OOH
72
NU'l2_MSG: db 'TYPE
73
SUM.MSG:
74
75
ENO
I~
SECOND NUMBER: ',OOH
db 'THE SUM IS ',OOH
SYMBOL TABLE LISTING
.. T Y P E
N A M E
ASCBIN.
BINASC.
CONSTANT.AR:A
OATA.AQEA
GeT.NUM •
NUM1.MSG.
NUM1 • • •
NUM2.MSG.
NUMl • • •
PUT.CRLF • • •
PUT .OAT A.S TR.
PUT.STRING.
SAMPLE ••
SCON. • •
STACK ••
START • •
SUM.MSG •
SuM • • •
TM1
•
•
•
TMOO. •
TR1 • •
TYPO.MSG.
~EGISTER
C ADOQ
C AOOR
C SEG
o SEG
C AOOR
C AOOR
o AOOR
C AilOR
o AOOIl
C AOC~
C AOOR
C AOOq
o AOOR
o
C
C
o
il
o
B
C
AO:lR
AoOR
ADDIl
AOOR
AODR
AOOR
ADDR
AOJR
A T T RIB UTE S
V A L U E
EXT
!:XT
0056H
OOOCH
REL=UNIT
REL=UNIT
EXT
0010H
OilOOH
0032H
0004H
R
R
R
R
SEG=CONSTANT.AREA
SEG=OATA.AREA
SEG=CONSTANT.AREA
SEG=OATA.AREA
EXT
EXT
EXT
00~8H
A
0008H
0006H
004AH
0008H
COSDH
0089H
0088H.6
OOOOH
A
A
R
R
SEG=CONSTANT.AREA
SEG=DATA.AREA
A
A
A
R
BANKeS) USED: 0, TARGET MACHIN!:eS): 8051
ASSEMBLY COMPLETE, NO ERRORS FOUND
Figure 7·1. Example Listing File Format (Cont'd.)
7-17
Assembler Output: Error Messages and Listing File Format
Mes-sl
Listing File Heading
Every page has a header on the first line. It contains the words "MCS-51 MACRO
ASSEMBLER" followed by the title, if specified. If the title is not specified, then
the module name is used. It is derived from the NAME directive (if specified), or
from the root of the source filename. On the extreme right side of the header, the
date (if specified) and the page number are printed.
.
In addition to the normal header, the first page of listing includes a heading shown
in figure 7-2. In it the assembler's version number is shown, the file name of the
object file, if any, and the invocation line. The entire invocation line is displayed
even if it extends over several lines.
MCS-51 MACRO ASSEMBLER
SAMPLE
ISIS-II MCS-51 MACRO ASSEMBLER V2.0
OBJECT MODULE PLACED IN :F1 :SAMP1.0BJ
ASSEMBLER INVOKED BY: :F1:ASM51 :F1:SAMP1.A51 DEBUG
Figure 7-2. Example Heading
Source Listing
The main body of the listing file is the formatted source listing. A section of for,platted source is shown in figure 7-3.
LOC
0000
0000
0003
0006
0009
OBJ
758920
758003
7598DA
D28E
LINE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SOURCE
NAME SAMPLE
,.
EXTRN code (put_crlf, put_string,put_data_str)
EXTRN code (get_num, binasc, ascbin)
CSEG
~ This is the initializing section. Execution
~ always starts at addr~ss o on power-up.
ORG 0
Set timer to auto-reload
MOV TMOD,#00100000B
MOV TH1,#(-253)
Set timer f~r 110 BAUD
Prepare the Serial Port
MOV SCON,#11011010B
Start clock
SETB TR1
,.
~ This is the main program. It's an infinite loop,
; where each iteration prompts the console for 2
; input numbers and types out their sum.
START:
Figure 7-3. Example Source Listing
7-18
PAGE 1
Assembler Output: Error Messages and Listing File Format
MCS-51
The format for each line in the listing file depends on the source line that appears on
it. Instruction lines contain 4 fields. The name of each field and its meaning is shown
in the list below:
• LOC shows the location relative or absolute (code address) of the first byte of
the instruction. The value is displayed in hexadecimal.
• OBJ shows the actual machine code produced by the instruction, displayed in
hexadecimal.
•
If the object that corresponds to the printed line is to be fixed up (it contains
external references or is relocatable), an "F" is printed after the OBJ field. The
object fields to be fixed up contain zeroes.
• LINE shows the INCLUDE nesting level, if any, the number of source lines
from the top of the program, and the macro nesting level, if any. All values in
this field are displayed in decimal numbers.
• SOURCE shows the source line as it appears in the file. This line may be
extended onto the subsequent lines in the listing file.
DB or DW directives are formatted similarly to instruction lines, except the OBJ
field shows the data values placed in memory. All data values are shown. If the
expression list is long, then it may take several lines in the listing file to display all of
the values placed in memory. The extra lines will only contain the LOC and OBJ
fields.
The directives that affect the location counter without initializing memory (e.g.,
ORG, DBIT, or DS) do not use the OBJ field, but the new value of the location
counter is shown in the LOC field.
The SET and EQU directives do not have a LOC or OBJ field. In their place the
a,ssembler lists the value that the symbol is set to. If the symbol is defined to equal
one of the registers, then 'REG' is placed in this field. The remainaer of the directive
line is formatted in the same way as the other directives.
Format for Macros and INCLUDE Files
The format for lines generated by a macro call varies with the macro listing mode
(GEN, GENONLY, or NOGEN). Figure 7-4 shows the format of the call macro
calls listed with each of these modes in effect. In all three calls the same instructions
are encoded, the only difference is in the listing of the macro call. Note that the
macro nesting level is shown immediately to the right of the line number.·
3 .1
•
0388 E582
OlEA 24£A
a3EC F582
5 .1
6 .1
7 .2
8 .1
9 .2
.GEt.!
hdd16(DPH, DPL,,(HIGH $) .'(LOW $) ,DPH, DPL)
MOV A, ULOW
ope
ADD A,nLOW'
'(LOW .$)
10 +1
MOV SSUHL,OV
11 .2
DPL,!
MOV ",URIGH
12 +1
03EE ES83
13 +2
14 ... ,
03FO 3403
15 +2
03F2 FS8,
16 .1
17 +2
OPH
ADDC A,URIGH
I(HIGH $)
MOV SSllMaIGH
DPR,!
18 .,
19
20
21
22 +1
$GENOHLY
23 .,
03FI( E582
03F6 24F6
F582
03f'8
03F.
03FC
03FE
E583
3403
F583
24 +2
25 +2
26
21
28
29
30
+2
+2
+2
+2
+1
MOY A, DPL
ADD A,t(LOW $)
MOV DPL,"
MOV A,DPR
ADDC A,'(HIGH $)
MOV DPH.!
31
32
33
34 +1
35
,MOGEN
Jadd16( DPH. DP!...
Ie HIGH
$)
I
,< LOW' $). DPH, DPL)
'3
Figure 7-4. Examples of Macro Listing Modes
7-19
Assembler Output: Error Messages and Listing File Format
MeS-51
General control lines that appear in the source are interpreted by ASM5l 's macro
processor and, as such, they are given a macro nesting level value. It is displayed
immediately to the right of the line number. Lines added to the program as a result
of the INCLUDE control are formatted just as if they appeared in the original
source file, except that the INCLUDE nesting level is displayed immediately to the
left of the line number.
The control line shown below has both an INCLUDE nesting level and a macro
nesting level. The INCLUDE nesting level is preceded by a equal sign '=', and the
macro nesting level is preceded by a plus sign '+' .
LOC
OBJ
LINE
=1
101
SOURCE
+1
$
SAVE
NOLIST
Symbol Table
The symbol table is a list of all symbols defined in the program along with the status
information about the symbol. Any predefined symbols used will also be listed in the
symbol table. If the XREF control is used, the symbol table will contain information
about where the symbol was used in the program.
The status information includes a NAME field, a TYPE field, a VALUE field, and
an ATTRIBUTES field.
f
The TYPE field specifies the type of the symbol: ADDR if it is a memory address,
NUMB if it is a pure number (e.g., as defined by EQU), SEG if it is a relocatable
segment, and REG if a register. For ADDR and SEG symbols, the segment type is
added to the type:
•
•
•
•
•
C -CODE
D-DATA
X-XDATA
I - IDATA
B - BIT
The VALUE field shows the value of the symbol when the assembly was completed.
For REG symbols, the name of the register is given. For NUMB and ADDR symbols, their absolute value (or if relocatable, their offset) is given, followed by A
(absolute) or R (relocatable). For SEG symbols, the segment size is given here. Bit
address and size are given by the byte part, a period (.), followed by the bit part. The
scope attribute, if any, is PUB (public) or EXT (external). These are given after the
VALUE field.
For the module name symbol, the TYPE and the VALUE fields contain dashes
(-----).
The ATTRIBUTES field contains an additional piece of information for some symbols: relocation type for segments, segment name for relocatable symbols.
If the XREF control is used, then the symbol table listing will also contain all of the
line numbers of each line of code that the symbol was used. If the value of the sym-
bol was changed or defined on a line, then that line will have a hash mark , unless defined explicitly implies a
sequence of items separated by commas (,).
Square brackets are used to enclose optional items.
A-I
Assembly Language BNF Grammar
MCS-Sl
::=
::= I
::= END
::=
NULL
I I
::= $
::= I NULL
::= DATE(
I MR [«constant»]
I NOMR I
OBJECT(..
::=