9803074 01_i SBC_86_12A_Hardware_Reference_Aug79 01 I SBC 86 12A Hardware Reference Aug79
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User Manual: 9803074-01_iSBC_86_12A_Hardware_Reference_Aug79
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II
iSBC 86/12ATM
SINGLE BOARD COMPUTER
HARDWARE
REFERENCE MANUAL
Manual Order Number: 9803074-01
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iSBC 86/12ATM
SINGLE BOARD COMPUTER
HARDWARE
REFERENCE MANUAL
Manual Order Number: 9803074-01
Copyright © 1979 Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
Additional copies of this manual or other Intel literature may be obtained from:
Literature Department
Intel Corporation
3065 Bowers A venue
Santa Clara, CA 95051
The information in this document is subject to change without notice.
Intel Corporation makes no warranty of any kind with regard to this material, including, but
not limited to, the implied warranties of merchantability and fitness for a particular
purpose. Intel Corporation assumes no responsibility for any errors that may appear in this
document. Intel Corporation makes no commitment to update nor to keep current the
information contained in this document.
Intel Corporation assumes no responsibility for the use of any circuith other than circuitry
embodied in an Intel product. No other circuit patent licenses are implied.
No part ofthis document may be copied or reproduced in any form or by any means without the
prior written consent of Intel Corporation.
The following are trademarks of Intel Corporation and may be used only to describe Intel
products:
i
ICE
iCS
Insite
Intel
Intellec
iSBC
Library Manager
MCS
Megachassis
Micromap
Multibus
Multimodule
PROMPT
Promware
RMX
UPI
IlScope
and the combination of ICE, iCS, iSBC, MCS, or RMX and a numerical suffix.
ii
A93/0879/10K FL
I
PREFACE
This manual provides general information, installation, programming information,
principles of operation, and service information for the Intel iSBC 86/12A Single
Board Computer and the optional iSBC 300 Multimodule RAM and iSBC 340
Multimodule EPROM. Additional information is available in the following
documents:
•
•
•
•
8086 Assembly Language Reference Manual, Order No. 9800640
Intel MCS-86 User's Manual, Order No. 9800722
Intel MULTIBUS Specification Manual, Order No. 9800683
Intel MULTIBUS Interfacing, Application Note AP-28
iii
CONTENTS
CHAPfER 1
GENERAL INFORMATION
PAGE
Introduction ....................................
Description .....................................
Optional RAM and ROM/EPROM Expansion ..
System Software Development ..................
Equipment Supplied ............................
Equipment Required ............................
Specifications ...................................
1-1
1-1
1-3
1-4
1-4
1-4
1-4
CHAPfER2
PREPARATION FOR USE
Introduction .................................... 2-1
Unpacking and Inspection ...................... 2-1
Installation Considerations ..................... 2-1
User-Furnished Components ................... 2-1
Power Requirement ............................ 2-1
Cooling Requirement ........................... 2-1
Physical Dimensions ........................... 2-1
Component Installation ......................... 2-1
ROM/EPROM Chips ........................... 2-2
No Wait Option ............................... 2-2
Line Drivers and I/O Terminators ............. 2-2
Jumper/Switch Configuration .................. 2-2
RAM Addresses (Multibus
In terface Access) .............................. 2-7
Priority Interrupts ............................. 2-7
Serial I/O Port Configuration .................. 2-7
Parallel I/O Port Configuration ............... 2-11
Multibus Interface Configuration ............... 2-11
Signal Characteristics ........................ 2-11
Multibus Interface Arbitration ................ 2-22
Common Bus Request ........................ 2-22
Any Request ................................. 2-22
Jumper Configurations ....................... 2-23
Serial Priority Resolution ..................... 2-23
Parallel Priority Resolution ................... 2-23
Power Fail/Memory Protect Configuration ..... 2-24
Parallel I/O Cabling ........................... 2-25
Serial I/O Cabling ............................. 2-26
Board Installation ............................. 2-27
CHAPfER3
PROGRAMMING INFORMATION
Introduction ....................................
Failsafe Timer ..................................
Memory Addressing .............................
CPU Access ...................................
Multibus Interface Access ......................
I/O Addressing .................................
System Initialization ............................
8251A USART Programming ....................
3-1
3-1
3-1
3-2
3-2
3-3
3-4
3-5
PAGE
Mode Instruction Format ....................... 3-5
Sync Characters ............................... 3-5
Command Instruction Format .................. 3-6
Reset .......................................... 3-6
Addressing .................................... 3-6
Initialization ................................... 3-7
Operation ...................................... 3-8
Data Input/Output ............................ 3-8
Status Read ................................... 3-9
8253 PIT Programming ......................... 3-9
Mode Control Word and Count ................. 3-9
Addressing ................................... 3-13
Initialization .................................. 3-13
Operation ..................................... 3-13
Counter Read ................................ 3-13
Clock Frequency/Divide Ratio Selection ...... 3-14
Rate Generator/Interval Timer ............... 3-15
Interrupt Timer .............................. 3-16
8255A PPI Programming ....................... 3-16
Control Word Format ......................... 3-17
Addressing ................................... 3-17
Initialization .................................. 3-17
Operation ..................................... 3-17
Read Operation .............................. 3-17
Write Operation .............................. 3-17
8259A PIC Programming ...................... 3-17
Interrupt Priority Modes ...................... 3-18
Nested Mode ................................. 3-18
Fully Nested Mode ........................... 3-19
Automatic Rotating Mode .................... 3-19
Specific Rotating Mode ....................... 3-19
Special Mask Mode .......................... 3-19
Poll Mode .................................... 3-19
Status Read ................................... 3-19
Initialization Command Words ................ 3-19
Operation Command Words ................... 3-21
Addressing ................................... 3-21
Initialization .................................. 3-21
Operation .................................... . 3-24
Hardware Interrupts .......................... . 3-26
Non-Maskable Interrupt (NMI) ................ 3-26
Maskable Interrupt (INTR) .................... 3-27
Master PIC Byte Identifier ................... 3-27
Slave PIC Byte Identifier .................... 3-27
CHAPfER4
PRINCIPLES OF OPERATION
Introduction ....................................
Functional Description ..........................
Clock Circuits ..................................
Central Processor Unit .........................
4-1
4-1
4-1
4-1
v
CONTENTS (Continued)
PAGE
PAGE
Interval Timer ................................. 4-1
Serial I/O ..................................... 4-2
Parallel I/O ................................... 4-2
Interrupt Controller ............................ 4-2
ROM/EPROM Configuration .................. 4-2
RAM Configuration ............................ 4-2
Bus Structure .................................. 4-3
Multibus Interface ............................. 4-4
Circuit Analysis ................................ 4-4
Initialization ................................... 4-4
Clock Circuits .................................. 4-4
8086 CPU Timing .............................. 4-4
Basic Timing ................................. 4-4
Bus Timing ................................... 4-5
Address Bus ................................... 4-8
Data Bus ...................................... 4-8
Bus Time Out .................................. 4-8
Internal Control Signals ....................... 4-8
Dual Port Control Logic ........................ 4-8
Multibus Interface Access Timing ............. 4-8
CPU Access Timing .......................... 4-10
Multibus Interface Arbitration ................ 4-10
I/O Operation ................................ 4-12
On-Board I/O Operation ..................... 4-12
System I/O Operation ....................... 4-12
ROM/EPROM Operation ..................... 4-12
ROM/EPROM Operation with
iSBC 340 Multimodule EPROM ............. 4-13
RAM Operation ............................... 4-13
RAM Controller .............................. 4-13
vi
RAM Chips ..................................
RAM Controller with iSBC 300
Multimodule RAM ..........................
RAM Chips with iSBC 300
Multimodule RAM ..........................
On-Board Read/Write Operation .............
Bus Read/Write Operation ...................
Byte Operation ..............................
Interrupt Operation ...........................
NBV Interrupt ...............................
BV Interrupt ................................
4-14
4-14
4-14
4-14
4-15
4-15
4-15
4-15
4-16
CHAPTER 5
SERVICE INFORMATION
Introduction ....................................
Replaceable Parts ...............................
Service Diagrams ...............................
Service and Repair Assistance ..................
5-1
5-1
5-1
5-1
APPENDIX A
TELETYPEWRITER MODIFICATIONS
APPENDIXB
iSBC 300 MULTIMODULE RAM AND
iSBC 340 MULTIMODULE EPROM
APPENDIXC
CUSTOM PROGRAMMED PROMS
TABLES
PAGE
TITLE
TABLE
Specifications ........................... 1-4
1-1
U ser-Furnished and
2-1
Installed Components .................. 2-2
U ser-Furnished Connector Details ....... 2-4
2-2
Line Driver and I/O Terminator
2-3
Locations .............................. 2-5
Jumper and Switch Selectable
2-4
Options ................................ 2-5
Priority Interrupt Jumper Matrix ...... 2-10
2-5
Serial I/O Connector J2 Pin Assignments
2-6
Vs Configuration Jumpers ............ 2-11
Parallel I/O Port Configuration
2-7
Jumpers .............................. 2-12
Multibus Interface Connector PI
2-8
Pin Assignments ..................... 2-15
Multibus Interface Signal Functions '" 2-16
2-9
iSBC 86/12A Board DC Characteristics 2-17
2-10
iSBC 86/12A Board AC Characteristics
2-11
(Master Mode) ........................ 2-19
2-12
iSBC 86/12A Board AC Characteristics
(Slave Mode) .......................... 2-19
2-13
8289 Bus Arbiter Jumper Configurations 2-22
Auxiliary Connector P2 Pin
2-14
Assignments ......................... 2-25
Auxiliary Signal (Connector P2) DC
2-15
Characteristics ....................... 2-26
2-16
Parallel I/O Connector Jl
Pin Assignments ..................... 2-26
Parallel 110 Signal (Connector Jl)
2-17
DC Characteristics ................... 2-27
2-18
Connector J2 Vs RS232C Pin
Correspondence ....................... 2-27
3-1
Typical Dual Port Access Subroutine .... 3-2
3-2
On-Board Memory Addresses
(CPU Access) .......................... 3-3
3-3
110 Address Assignments .............. 3-4
3-4
Typical USART Mode or Command
Instruction Subroutine ................. 3-8
3-5
Typical USART Data Character
Read Subroutine ....................... 3-9
3-6
Typical USART Data Character
Write Subroutine ....................... 3-9
3-7
Typical USART Status Read Subroutine 3-10
3-8
PIT Counter Operation Vs Gate Inputs. 3-13
3-9
Typical PIT Control Word Subroutine .. 3-14
3-10
Typical PIT Count Value Load
Subroutine ............................ 3-14
TABLE
TITLE
PAGE
Typical PIT Counter Read Subroutine .. 3-15
3-11
PIT Count Value Vs Rate Multiplier
3-12
for Each Baud Rate ................... 3-16
PIT Rate Generator Frequencies and
3-13
Timer Intervals ....................... 3-16
PIT Time Intervals Vs Timer Counts ... 3-16
3-14
Typical PPI Initialization
3-15
Subroutine ............................ 3-18
Typical PPI Port Read
3-16
Subroutine .......................... " 3-18
Typical PPI Port Write
3-17
Subroutine ............................ 3-18
Interrupt Vector Byte .................. 3-20
3-18
Typical PIC Initialization
3-19
Subroutine (NBV Mode) ............... 3-23
3-20
Typical Master PIC Initialization
Subroutine (BV Mode) ................ 3-23
Typical Slave PIC Initialization
3-21
Subroutine (BV Mode) ................ 3-23
PIC Operation Procedures ............. 3-24
3-22
Typical PIC Interrupt Request
3-23
Register Read Subroutine ............. 3-26
Typical PIC In-Service Register
3-24
Read Subroutine ...................... 3-26
Typical PIC Set Mask Register
3-25
Subroutine ............................ 3-26
Typical PIC Mask Register Read
3-26
Subroutine ....... . . . . .. . . . . .. . . . .. .. .. 3-27
Typical PIC End-Of-Interrupt Command
3-27
Subroutine ............................ 3-27
ROM/EPROM Chip Selection .......... 4-14
4-1
Replaceable Parts ....................... 5-1
5-1
List of Manufacturer's Codes ............ 5-3
5-2
RAM Base Address .................... C-l
C-l
RAM Size ............................. C-2
C-2
RAM Size - PROM Page ............... C-2
C-3
Translator PROM Contents for Intel
C-4
Part Number 9100134 ................. C-3
Translator PROM Contents for Intel
C-5
Part Number 9100212 ................. C-4
Memory Chip Select PROM Outputs ... C-6
C-6
EPROM Select Coding ................. C-6
C-7
Chip Select PROM Contents for Intel
C-8
Part Number 9100129 ................. C-7
Chip Select PROM Contents for Intel
C-9
Part Number 9100213 ................. C-8
User Coded Chip Select PROM Contents C-9
C-I0
vii
ILLUSTRATIONS
FIGURE
TITLE
PAGE
1-1
iSBC 86/12A Single Board
Computer .............................. 1-1
2-1
Dual Port RAM Address Configuration
(Multibus Interface Access) ............ 2-8
2-2
Simplified Master/Slave PIC
Interconnect Example ................ 2-10
2-3
Bus Exchange Timing (Master Mode) .. 2-20
2-4
Bus Exchange Timing (Slave Mode) .... 2-21
2-5
Serial Priority Resolution Scheme ...... 2-23
2-6
Parallel Priority Resolution Scheme .... 2-24
3-1
Dual Port RAM Addressing (M ultibus
Interface Access) ...................... 3-3
3-2
USART Synchronous Mode Instruction
Word Format .......................... 3-5
3-3
USART Synchronous Mode
Transmission Format .................. 3-5
3-4
USART Asynchronous Mode Instruction
Word F-ormat .......................... 3-6
3-5
USART Asynchronous Mode
Transmission Format .................. 3-6
3-6
USART Command Instruction Word
Format ................................ 3-7
3-7
Typical USART Initialization and
I/O Data Sequence .................... 3-7
3-8
USART Status Read Format ........... 3-10
3-9
PIT Mode Control Word Format ........ 3-11
3-10
PIT Programming Sequence Examples. 3-12
3-11
PIT Counter Register Latch
Control Word Format ................. 3-15
3-12
PPI Control Word Format .............. 3-17
3-13
PPI Port C Bit SetlReset Control
Word Format ......................... 3-18
3-14
PIC Initialization Command
Word Formats ........... " ........... 3-20
viii
FIGURE
TITLE
PAGE
3-15
PIC Operation Control Word
Formats .............................. 3-22
4-1
iSBC 86/12A Input/Output and Interrupt
Simplified Logic Diagram ............. 4-17
4-2
iSBC 86/12A ROM/EPROM and Dual Port
RAM Simplified Logic Diagram ....... 4-19
4-3
Internal Bus Structure .................. 4-3
4-4
CPU Read Timing ...................... 4-5
4-5
CPU Write Timing ...................... 4-6
4-6
CPU Interrupt Acknowledge Cycle
Timing ................................ 4-7
4-7
Dual Port Control Multibus Interface Access
Timing with CPU Lockout ............. 4-9
4-8
Dual Port Control CPU Access Timing with
Multibus Interface Lockout ........... 4-11
5-1
iSBC 86/12A Parts Location Diagram ... 5-5
5-2
iSBC 86/12A Schematic Diagram ....... 5-7
A-I
Teletype Component Layout ........... A-2
A-2
Current Source Resistor................ A-2
A-3
Terminal Block ........................ A-2
A-4
Teletypewriter Modifications ........... A-3
A-5
Relay Circuit ............ "".......... A-3
A-6
Mode Switch ........................... A-3
A-7
Distributor Trip Magnet ............... A-4
A-8
TTY Adapter Cabling.... .. .. .. .. .. .... A-4
B-1
iSBC 300 Multimodule RAM Orientation B-1
B-2
iSBC 340 Multimodule EPROM
Orientation ........................... B-3
B-3
iSBC 300 Multimodule RAM Parts
Location Diagram .................... B-5
B-4
iSBC Multimodule RAM Schematic .... B-7
B-5
iSBC 340 Multimodule EPROM Parts
Location Diagram .................... B-9
B-6
iSBC 340 Multimodule EPROM
Schematic ........................... B-ll
CHAPTER 1
GENERAL INFORMATION
1-1. INTRODUCTION
The iSBC 86/12A Single Board Computer, which is a
member of Intel's complete line of8- and I6-bit single
board computer products, is a complete computer
system on a single printed-circuit assembly. The
iSBC 86/I2A board includes a I6-bit central
processing unit (CPU), 32K bytes of dynamic RAM, a
serial communications interface, three programmable parallel I/O ports, programmable timers,
priority interrupt control, Multibus interface control
logic, and bus expansion drivers for interface with
other Multibus interface-compatible expansion
boards. Also included is dual port control logic to
allow the iSBC 86/I2A board to act as a slave RAM
device to other Multibus interface masters in the
system. Provision is made for user installation of up
to 16K bytes of read only memory.
1-2. DESCRIPTION
The iSBC 86/I2A Single Board Computer (figure 1-1)
is controlled by an Intel 8086 I6-Bit Microprocessor
(CPU). The 8086 CPU includes four I6-bit general
purpose registers that may also be addressed as eight
8-bit registers. In addition, the CPU contains two
I6-bit pointer registers and two I6-bit index
registers. Four I6-bit segment registers allow
extended addressing to a full megabyte of memory.
The CPU instruction set supports a wide range of
addressing modes and data transfer operations,
signed and unsigned 8-bit and I6-bit arithmetic
including hardware multiply and divide, and logical
and string operations. The CPU architecture features dynamic code relocation, reentrant code, and
instruction look ahead.
The iSBC 86/I2A board has an internal bus for all onboard memory and I/O operations and accesses the
system bus (Multibus interface) for all external
memory and I/O operations. Hence, local (on-board)
operations do not involve the Multibus interface
making the Multibus interface available for true
parallel processing when several bus masters (e.g.,
DMA devices and other single board computers) are
used in a m ultimaster scheme.
PARALLEL
I/O
(MULTIBUSj
SERIAL
1/0
(AUXILIARY)
Figure 1-1. iSBC 86/12ATM Single Board Computer
1-1
General Information
Dual port control logic is included to interface the
dynamic RAM with the Multibus interface so that the
iSBC 86/12A board can function as a slave RAM
device when not in control of the Multibus interface.
The CPU has priority when accessing on-board
RAM. After the CPU completes its read or write
operation, the controlling bus master is allowed to
access RAM and complete its operation. Where both
the CPU and the controlling bus master have the
need to write or read several bytes or words to or from
on-board RAM, their operations are interleaved. For
CPU access, the on-board RAM addresses are
assigned from the bottom up of the I-megabyte
address space; i.e., 00000-07FFFH. The slave RAM
address decode logic includes jumpers and switches
to allow positioning the on-board RAM into any 128K
segment of the I-megabyte system address space.
The slave RAM can be configured to allow either 8K,
16K, 24K, or 32K access by another bus master. If the
iSBC 300 Multimodule RAM option is installed the
memory increments are 16K, 32K, 48K, or 64K. Thus,
the RAM can be configured to allow other bus
masters to access a segment of the on-board RAM and
still reserve another segment strictly for on-board
use. The addressing scheme accommodates both
16-bit and 20-bit addressing.
Four IC sockets are included to accommodate up to
16K bytes of user-installed read only memory. Configuration jumpers allow read only memory to be
installed in 2K, 4K, or 8K increments.
The iSBC 86/12A board includes 24 programmable
parallel I/O lines implemented by means of an Intel
8255A Programmable Peripheral Interface (PPI).
The system software is used to configure the I/O lines
in any combination of unidirectional input/output
and bidirectional ports. The I/O interface may be
customized to meet specific peripheral requirements
and, in order to take full advantage of the large
number of possible I/O configurations, IC sockets are
provided for interchangeable I/O line drivers and
terminators. Hence, the flexibility of the parallel I/O
interface is further enhanced by the capability of
selecting the appropriate combination of optional
line drivers and terminators to provide the required
sink current, polarity, and drive/termination
characteristics for each application. The 24-programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector (Jl) that
mates with flat, woven, or round cable.
The RS232C compatible serial I/O port is controlled
and interfaced by an Intel 8251A USART (Universal
Synchronous/Asynchronous Receiver!Transmitter)
chip. The USART is individually programmable for
operation in most synchronous or asynchronous
serial data transmission formats (including IBM BiSync).
1-2
iSBC 86/12A
In the synchronous mode the following are programmable:
a. Character length,
b. Sync character (or characters), and
c. Parity.
In the asynchronous mode the following are
programmable:
a. Character length,
b. Baud rate factor (clock divide ratios of 1, 16, or
64),
c. Stop bits, and
d. Parity.
In both the synchronous and asynchronous modes,
the serial I/O port features half- or full-duplex,
double buffered transmit and receive capability. In
addition, USART error detection circuits can check
for parity, overrun, and framing errors. The USART
transmit and receive clock rates are supplied by a
programmable baud rate/time generator. These
clocks may optionally be supplied from an external
source. The RS232C command lines, serial data
lines, and signal ground lines are brought out to a
50-pin edge connector (J2) that mates with flat or
round cable.
Three independent, fully programmable 16-bit
interval timer/event counters are provided by an
Intel 8253 Programmable Interval Timer (PIT).
Each counter is capable of operating in either BCD or
binary modes; two of these counters are available to
the systems designer to generate accurate time
intervals under software control. Routing for the
outputs and gate/trigger inputs of two of these
counters may be independently routed to the 8259A
Programmable Interrupt Controller (PIC). The
gate/trigger inputs of the two counters may be routed
to I/O terminators associated with the 8255A PPI or
as input connections from the 8255A PPI. The third
counter is used as a programmable baud rate
generator for the serial I/O port. In utilizing the
iSBC 86/12A board, the systems designer simply
configures, via software, each counter independently
to meet system requirements. Whenever a given time
delay or count is needed, software commands to the
8253 PIT select the desired functioil. The contents of
each counter may be read at any time during system
operation with simple operations for event counting
applications, and special commands are included so
that the contents of eac~ counter can be read "on the
fly".
The iSBC 86/12A board provides vectoring for bus
vectored (BV) and non-bus vectored (NBV) inter-
iSBC 86/12A
rupts. An on-board Intel 8259A Programmable
Interrupt Controller (PIC) handles up to eight NBV
interrupts. By using external PIC's slaved to the onboard PIC (master), the interrupt structure can be
expanded to handle and resolve the priority of up to
64 BV sources.
The PIC, which can be programmed to respond to
edge-sensitive or level-sensitive inputs, treats each
true input signal condition as an interrupt request.
After resolving the interrupt priority, the PIC issues a
single interrupt request to the CPU. Interrupt
priorities are independently programmable under
software control. The programmable interrupt
priority modes are:
a. Nested Priority. Each interrupt request has a
fixed priority: input 0 is highest, input 7 is lowest.
b. Fully Nested Priority. This mode is the same as
nested mode, except that when a slave PIC is
being serviced, it is not locked out from the
master PIC priority logic and when exiting from
the interrupt service routine, the software must
check for pending interrupts from the slave PIC
just serviced.
c. Auto-Rotating Priority. Each interrupt request
has equal priority. Each level, after receiving
service, becomes the lowest priority level until
the next interrupt occurs.
d. Specific priority. Software assigns lowest
priority. Priority of all other levels is in numerical sequence based on lowest priority.
e. Special Mask. Interrupts at the level being
serviced are inhibited, but all other levels of
interrupts (higher and lower) are enabled.
f. Poll. The CPU internal interrupt enable is
disabled. Interrupt service is achieved by
programmer initiative using a Poll command.
The CPU includes a non-maskable interrupt (NMI)
and a maskable interrupt (INTR). The NMI interrupt
is intended to be used for catastrophic events such as
power outages that require immediate action of the
CPU. The INTR interrupt is driven by the 8259A PIC
which, on demand, provides an 8-bit identifier of the
interrupting source. The CPU multiplies the 8-bit
identifier by four to derive a pointer to the service
routine for the interrupting device.
Interrupt requests may originate from 18 sources
without the necessity of external hardware. Two
jumper-selectable interrupt requests can be automatically generated by the Programmable Peripheral Interface (PPI) when a byte of information is ready
to be transferred to the 8086 CPU (i.e., input buffer is
full) or a byte of information has been transferred to a
peripheral device (i.e., output buffer is empty). Two
General Information
jumper-selectable interrupt requests can be automatically generated by the USART when a character is
ready to be transferred to the 8086 CPU (i.e., receive
channel buffer is full) or when a character is ready to
be transmitted (Le., transmit channel data buffer is
empty). A jumper-selectable interrupt request can be
generated by two of the programmable counters and
eight additional interrupt request lines are available
to the user for direct interfaces to user-designated
peripheral devices via the Multibus interface. One
interrupt request line may be jumper routed directly
from a peripheral via the parallel I/O driver/terminator section and one power fail interrupt may be input
via auxiliary connector P2.
The iSBC 86/12A board includes the resources for
supporting a variety of OEM system requirements.
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPU's and/or controllers logically sharing
systems tasks with communication over the Multibus
interface), the iSBC 86/12A board provides full bus
arbitration control logic. This control logic allows up
to three bus masters (e.g., combination of iSBC
86/12A board, DMA controller, diskette controller,
etc.) to share the Multibus interface in serial (daisychain) fashion or up to 16 bus masters to share the
Multibus interface using an external parallel priority
resolving network.
The Multibus interface arbitration logic operates
synchronously with the bus clock, which is derived
either from the iSBC 86/12A board or can be
optionally generated by some other bus master.
Data, however, is transferred via a handshake
between the controlling master and the addressed
slave module. This arrangement allows different
speed controllers to share resources on the same bus,
and transfers via the bus proceed asynchronously.
Thus, the transfer speed is dependent on transmitting and receiving devices only. This design prevents slower master modules from being handicapped in their attempts to gain control of the bus, but
does not restrict the speed at which faster modules
can transfer data via the same bus. The most obvious
applications for the master-slave capabilities of the
bus are multiprocessor configurations, high-speed
direct memory access (DMA) operations, and highspeed peripheral control, but are by no means limited
to these three.
1-3. OPTIONAL RAM AND ROM/EPROM
EXPANSION
Adding the optional iSBC 300 Multimodule RAM to
the iSBC 86/12..J\. board, allows the on~board RAM: to
be expanded by 32K (for an on-board total of 64K). If
the optional iSBC 340 Multimodule EPROM is
installed on the iSBC 86/12A board, the amount of
1-3
General Information
iSBC 86/12A
on-board ROM/EPROM can be expanded by 16k (for
an on-board total of 32k). See appendix C for other
EPROM expansion options. Appendix C also lists
the PROM maps for the custom programmed
PROMs.
1-5. EQUIPMENT SUPPLIED
The following are supplied with the iSBC 86/12A
Single Board Computer:
a. Schematic diagram, dwg no. 2003053
b. Assembly drawing, dwg no. 1003052
1-4. SYSTEM SOFTWARE
DEVELOPMENT
The development cycle ofiSBC 86/12A Single Board
Computer based products may be significantly
reduced using an Intel Intellec Microcomputer
Development System with the optional MDS-311
8086 Software Development package.
The MDS-311 8086 Software Development package
includes Intel's high level programming language,
PL/M 86. PL/M 86 provides the capability to
program in a natural, algorithmic language and
eliminates the need to manage register usage or
allocate memory. PL/M 86 programs can be written
in a much shorter time than assembly language
programs for a given application.
1-6. EQUIPMENT REQUIRED
Because the iSBC 86/12A board is designed to satisfy
a variety of applications, the user must purchase and
install only those components required to satisfy his
particular needs. A list of components required to
configure all the intended applications of the iSBC
86/12A board is provided in table 2-1.
1-7. SPECIFICATIONS
Specifications of the iSBC 86/12A Single Board
Computer are listed in table 1-1.
Table 1-1. Specifications
WORD SIZE
Instruction:
Data:
INSTRUCTION CYCLE TIME:
MEMORY CAPACITY
On-board ROM/EPROM:
8/16 bits.
400 nanoseconds for fastest executable instruction (assumes instruction is in
the queue).
1.0 microseconds for fastest executable instruction (assumes instruction is not
in the queue);
Up to 16K bytes; user installed in 2K, 4K or 8K byte increments or up to 32K bytes
if iSBC 340 Multimodule EPROM option installed.
On-board Dynamic RAM:
32K bytes or 64K bytes if iSBC 300 Multimodule RAM option installed. Integrity
maintained during power failure with user-furnished batteries.
Off-board Expansion:
Up to 1 megabyte of user-specified combination of RAM, ROM, and EPROM.
MEMORY ADDRESSING
On-board ROM/EPROM:
On-board RAM:
(CPU Access)
1-4
8, 16, or 32 bits.
FFOOO-FFFFFH (using 2758 EPROM's),
FEOOO-FFFFFH (using 2316E ROM's or 2716 EPROM's),
FCOOO-FFFFFH (using 2332A ROM's or 2732 EPROM's), and
F8000-FFFFFH (if iSBC 340 Multimodule EPROM option installed).
00000-07FFFH,
OOOOO-OFFFFH (if iSBC 300 Multimodule RAM option installed).
iSBC 86/12A
General Information
Table 1-1. Specifications (Continued)
On-Board RAM:
(Multi bus Interface Access)
Jumpers and switches allow board to act as slave RAM device for access by
another bus master. Addresses may be set within any 8K boundary of any 128K
segment of the 1-megabyte system address space. Access is selectable
for 8K, 16K, 24K, or 32K bytes.
Slave RAM Access:
Average; 1.5 mciroseconds
SERIAL COMMUNICATIONS
Synchronous:
Asynch ronous:
5-, 6-, 7-, or 8-bit characters.
Internal; 1 or 2 sync characters.
Automatic sync insertion.
5-, 6-, 7-, or 8-bit characters.
Break character generation.
1, 1%, or 2 stop bits.
False start bit detection.
Sample Baud Rate:
Baud Rate (Hz)2
Frequency'
(kHz, Software Selectable)
Synchronous
Asynchronous
+16
I
153.6
I
38400
19200
9600
4800
2400
1760
76.8
38.4
19.2
9.6
4.8
2.4
1.76
9600
4800
2400
1200
600
300
150
110
I
+64
2400
1200
600
300
150
75
-
-
Notes:
1. Frequency selected by I/O wri\es of appropriate 16-bit frequency factor to
Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible softwareprogrammable rates available. Any frequency from 18.75 Hz to 613.5 kHz
may be generated utilizing on-board crystal oscillator and 16-bit Programmable Interval Timer (used here as frequency divider).
INTERVAL TIMER AND
BAUD RATE GENERATOR
Input Frequency (selectable):
2.46 MHz ±0.1% (0.41 p,sec period nominal),
1.23 MHz ±0.1% (0.82p,sec period nominal), and
153.6 kHz ±0.1% (6.5 p,sec period nominal).
Output Frequencies:
Single Timer
Function
Real-Time
Interrupt
Interval
Rate
Generator
.(rrequencyJ
I
Dual Timers
(Two Timers Cascaded)
Min.
Max.
Min.
Max.
1.63 p,sec
427.1 msec
3.26 p,sec
466.5
minutes
2.342 Hz
613.5 kHz
0.000036 Hz
306.8 kHz
1-5
General Information
iSBC 86/12A
Table 1-1. Specifications (Continued)
8086 CPU CLOCK
5.0 MHz ±0.1%.
I/O ADDRESSING:
All communication to Parallel I/O and Serial I/O Ports, Timer, and Interrupt
Controller is via read and write commands from on-board 8086 CPU. Refer to
table 3-2.
INTERFACE COMPATIBILITY
Serial I/O:
EIA Standard RS232C signals provided and supported:
Clear to Send
Receive Data
Data Set Ready
Secondary Receive Data*
Data Terminal Ready
Secondary CTS*
Request to Send
Transmit Clock*
Receive Clock
Transmit Data
*Can support only one
Parallel 110:
24 programmable lines (8 lines per port); one port includes bidirectional bus
driver. IC sockets included for user installation of line drivers and/or I/O terminators as required for interface ports. Refer to table 2-1.
INTERRUPTS:
8086 CPU includes non-maskable interrupt (NMI) and maskable interrupt
(INTR). NMI interrupt is provided for catastrophic event such as power failure;
NMI vector address is 00008. INTR interrupt is driven by on-board 8259A PIC,
which provides 8-bit identifier of interrupting device to CPU. CPU multiplies
identifier by four to derive vector address. Jumpers select interrupts from 18
sources without necessity of external hardware. PIC may be programmed to
accommodate edge-sensitive or level-sensitive inputs.
COMPATIBLE
CONN ECTORS/CABLES:
ENVIRONMENTAL REQUIREMENTS
Operating Temperature:
Relative Humidity:
PHYSICAL CHARACTERISTICS
Width:
Height:
Thickness:
Weight:
1-6
Refer to table 2-2 for compatible connector details. Refer to paragraphs 2-26
and 2-27 recommended types and lengths of I/O cables.
0° to 55°C (32° to 131°F).
To 90% without condensation.
30.48 cm (12.00 inches).
17.15 cm (6.75 inches).
1.78 cm (0.7 inch).
539 gm (19 ounces).
iSBC 86/12A
General Information
Table 1-1. Specifications (Continued)
POWER REQUIREMENTS (MAXIMUM):
CONFiGURATiON
Without EPROM'
RAM Only2
VCC
= -t-OV:::!:OV/o
vDD
=+ I
~2'"
~M
V:::!:OV/o
5.2A
350 rnA
390 rnA
40 rnA
vBB
= -0
:::!:OU/o
I ..v AA = -I
-
~V:::!:OV/o
40 rnA
1.0 rnA
-
With iSBC 530 3
5.2A
450 rnA
-
40 rnA
With 4K EPROM4
(Using 2758)
5.5A
350 rnA
-
40mA
With 8K ROM4
(Using 2316E)
6.1A
350 rnA
-
40mA
With 8K EPROM4
(Using 2716)
5.5A
350 rnA
-
40 rnA
With 16K ROM4
(Using (2332A)
5.4A
350 rnA
-
40 rnA
With 16K EPROM4
(Using 2732)
5.4A
350 rnA
-
40 rnA
iSBC 300
Multimodule RAM
1 rnA
iSBC 340'
Multimodule PROM
120 rnA
I
24 rnA
-
I
-
-
~
~I\
I
111M.
-
Notes:
1. Does not include power required for optional ROM/EPROM, I/O drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus.
3. Does not inc!ude power for optional ROM/EPROM, I/O drivers, and I/O terminators. Power for the iSBC 530
TTY Adapter is supplied via serial port connector.
4. Includes power required for four ROM/EPROM chips, and I/O terminators installed for 16 I/O lines; all terminator
inputs low.
1-7/1-8
CHAPTER 2
PREPARATION FOR USE
2-1. INTRODUCTION
This chapter provides instructions for preparing the
iSBC 86/12A Single Board Computer for use in the
user-defined environment. It is advisable that the
contents of Chapters 1 and 3 be fully understood
before beginning the configuration and installation
procedures provided in this chapter.
2-2. UNPACKING AND INSPECTION
Inspect the shipping carton immediately upon receipt
for evidence of mishandling during transit. If the
shipping carton is severely damaged or waterstained,
request that the carrier's agent be present when the
carton is opened. If the carrier's agent is not present
when the carton is opened and the contents of the
carton are damaged, keep the carton and packing
material for the agent's inspection.
For repairs to a product damaged in shipment,
contact the Intel MCSD Technical Support Center
(see paragraph 5-4) to obtain a Return Authorization
Number and further instructions. A purchase order
will be required to complete the repair. A copy of the
purchase order should be submitted to the carrier
with your claim.
the connectors specified in table 2-1 are listed in table
2-2.
2-5. POWER REQUIREMENT
The iSBC 86/12A board requires +5V, -5V, +12V, and
-12V power. The -5V power, which is required for the
dual port RAM and the iSBC 300 Multimodule RAM,
can be supplied by the system -5V supply, an
auxiliary battery, or by the on-board -5V regulator.
(The -5V regulator operates from the system -12V
supply.)
2-6. COOLING REQUIREMENT
The iSBC 86/12A board dissipates 451 gramcalories/minute (1.83 Btu/minute) and adequate
circulation of air must be provided to prevent a
temperature rise above 55°C (131°F). The System 80
enclosures and the Intellec System include fans to
provide adequate intake and exhaust of ventilating
air.
2-7. PHYSICAL DIMENSIONS
It is suggested that salvageable shipping cartons and
packing material be saved for future use in the event
the product must be reshipped.
Physical dimensions of the iSBC 86/12A board are as
follows:
a. Width: 30.48 cm (12.00 inches).
2-3. INSTALLATION CONSIDERATIONS
b. Height: 17.15 cm (6.75 inches).
The iSBC 86/12A board is designed for use in one of
the following configurations:
c. Thickness: 1.50 cm (0.59 inch).
a. Standalone (single-board) system.
b. Bus master in a single bus master system.
2-8. COMPONENT INSTALLATION
2-4. USER-FURNISHED COMPONENTS
Instructions for installing the user supplied ROM/
EPROM, parallel I/O port line drivers and/or line
terminators are given in the following paragraphs.
When installing these chip components, be sure to
orient pin 1 of the chip adjacent to the white dot
located near pin 1 of the associated IC socket. The
grid zone location on figure 5-1 (parts location
diagram) is specified for each component chip to be
installed.
The user-furnished components required to configure
the iSBC 86/12A board for a particular application
are listed in table 2-1. Various types and vendors of
Instructions for installing the optional iSBC 300
Multimodule RAM and the optional iSBC 340
Multimodule PROM are given in Appendix B.
c. Bus master in a multiple bus master system.
Important criteria for installing and interfacing the
iSBC 86/12A board in these configurations are
presented in the following paragraphs.
2-1
iSBC 86/12A
Preparation for Use
2-9. ROMIEPROM CHIPS
IC sockets A28, A29, A46, and A47 (figure 5-1 zone
C3) accommodate 24-pin ROM/EPROM chips. Because the CPU jumps to location FFFFO on a power
up or reset, the ROM/EPROM address space resides
in the topmost portion of the I-megabyte address
space and must be loaded from the top down. IC
sockets A29 and A47 accommodate the top of the
ROM/EPROM address space and must always be
loaded; IC sockets A28 and A46 accommodate the
ROM/EPROM space directly below that installed in
A29 andA47.
The low-order byte (bits 0-7) of ROM/EPROM must
be installed in sockets A29 and A28; the high-order
byte (bits 8-15) must be installed in sockets A47 and
A46. Assuming that 2K bytes of EPROM are to be
installed using two Intel 2758 chips, the chip
containing the low-order byte must be installed in IC
socket A29 and the chip containing the high-order
byte must be installed in IC socket A47. In this
configuration, the usable ROM/EPROM address
space is FF800-FFFFF. Two additional Intel 2758
chips may be installed later in IC sockets A28 and
A46 and occupy the address space FFOOO-FF7FF.
(Even addresses read the low-order bytes and odd
addresses read the high-order bytes.)
The default (factory connected) jumpers and switch
81 are configured for 2K by 8-bit ROM/EPROM
chips (e.g., two or four Intel 2716's). If different type
chips are installed, reconfigure the jumpers and
switch 81 as listed in table 2-4.
2-10. NO WAIT OPTION. When 2716-1, 2
EPROMs or 2332 ROMs are installed, the jumper
between posts E3-E4 can be installed. This eliminates the wait state for ROM/PROM read. If any
other type of ROM or PROM is installed, the jumper
must be removed (one wait state), which is the factory
default wiring.
2-11. LINE DRIVERS AND 1/0
TERMINATORS
Table 2-3 lists the I/O ports and the location of
associated 14-pin sockets for installing either line
drivers or I/O terminators. (Refer to table 2-1 items
10 and 11.) Port C8 is factory equipped with Intel
8226 Bidirectional Bus Drivers and requires no
additional components.
2-12. JUMPER/SWITCH CONFIGURATION
The i8BC 86/12A board includes a variety of jumperand switch-selectable options to allow the user to
configure the board for his particular application.
Table 2-4 summarizes these options and lists the grid
reference locations of the jumpers and switches as
shown in figure. 5-1 (parts location diagram) and
figure 5-2 (schematic diagram). Because the schematic diagram consists of 11 sheets, grid references to
figure 5-2 may be either four or five alphanumeric
characters. For example, grid reference 3ZB7
signifies sheet 3 zone B7.
Table 2-1. User-Furnished and Installed Components
Item
No.
2-2
Item
Description
Use
1
iSBC 604
Backplane
Modular Backplane and Cardcage. Ineludes four slots with bus terminators.
Provide~ power input pins and Multibus interface signal interface between
iSBC 86/12A board and three additional boards in a multiple board
system.
2
iSBC 614
Backplane
Modular Backplane and Cardcage. Ineludes four slots without bus terminators.
Provides four-slot extention of iSBC
604 backplane.
3
iSBC 300
Multimodule RAM
32K Multimodule RAM Board.
Provides the capability to expand the
on-board RAM to 64K bytes using
2117's.
Preparation for Use
iSBC 86/12A
Table 2-1. User-Furnished and Installed Components (Continued)
Item
No.
Description
Item
Use
16K Multimodule EPROM Board.
Provides the capaollify to expand the
on-board EPROM to 32K bytes using
2332A's or 2732's. See Appendix C for
information on using 2716's or 2758's
in place of the 2732's.
Connector
(mates with P1)
See Multibus interface Connector
details in table 2-2.
Power inputs and Multibus interface
signal interface. Not required if iSBC
86/12A board is installed in an iSBC
604/614 backplane.
6
Connector
(mates with P2)
See Auxiliary Connector details in
table 2-2
Auxiliary backup battery and associated memory protect functions.
7
Connector
(mates with J1)
See Parallel I/O Connector details in
table 2-2.
Interfaces parallel I/O port with Intel
8255A PPI.
8
Connector
(mates with J2)
See Serial I/O connector details in
table 2-2.
Interfaces serial I/O port with Intel
8251A USART.
9
ROM/EPROM Chips
Two or four each of the following
types:
Ultraviolet Erasable PROM (EPROM)
for development. Masked ROM for
dedicated program.
4
iSBC 340
Multimodule PROM
5
or
EPROM
2758
2716
2732
2316E
2332
10
Line Drivers
Type
SN7403
SN7400
SN7408
SN7409
Current
I, OC
I
NI
NI, OC
16
16
16
16
rnA
rnA
rnA
rnA
Interface parallel I/O ports CA and CC
with Intel 8255A PPI. Requires two line
driver IC's for each 8-bit parallel output
port.
Types selected as typical; I =inverting,
NI = noninverting, and OC = open
collector.
11
Line Terminators
Intel iSBC 901 Divider or iSBC 902
Pull-Up:
c
+5V
:
220
Interface parallel I/O ports CA and CC
with Intel 8255A PPI. Requires two
two iSBC 901 Dividers or two iSBC 902
Pull-Ups for each 8-bit parallel input
port.
iSBC 901
-AAA
-&
330
J+5V
f1K
iSBC 902
••- - - o
o~--
2-3
Preparation for Use
iSBC 86/12A
Table 2-2. User-Furnished Connector Details
Function
No. of
Palrs/
Pins
Centers
(Inches)
Connector
Type3
Vendor
3M
3M
AMP
ANSLEY
SAE
3415-0000WITH EARS
3415-0001 W/O EARS
88083-1
609-5015
S06750 SERIES
2-583485-6
3VH25/1JV5
N/A
3VH25/1JN05
EC4A050A1A
N/A
Parallel
I/O
Connector
25/50
0.1
Flat Crimp
Parallel
I/O
Connector
25/50
0.1
Soldered'
AMP
VIKING
Parallel
I/O
Connector
24/50
0.1
Wi rewrap..' 2
VIKING
ITT CANNON
Serial
I/O
Connector
13/26
0.1
Flat Crimp
3M
AMP
ANSLEY
SAE
Serial
I/O
Connector
13/26
0.1
Soldered'
AMP
Serial
I/O
Connector
13/26
0.1
Wirewrap'2
TI
Multibus
Connector
43/86
0.156
Soldered'
Multibus
Connector
43/86
0.156
Wirewrap'2
Auxiliary
Connector
30/60
0.1
Auxiliary
Connector
30/60
0.1
Vendor Part No.
3462-0001
88106-1
609-2615
S06726 SERIES
iSBC 956
Cable
Set
iSBC 955
Cable
Set
1-583485-5
N/A
H311113
N/A
EBY
VIKING
ELFAB
EOAC
C043AE013
2KH43/9AMK12
BS1562043PBA
337086540201
EBY
ELFAB
EOAC
C043BA013
BW1562A43PBB
337086540202
Soldered'
ELFAB
EOAC
97169001
345060524300
N/A
Wirewrap'2
ELFAB
EOAC
97167901
345060523301
N/A
NOTES:
1. Connector heights are not guaranteed to conform to OEM packaging equipment.
2. Wirewrap pin lengths are not guaranteed to conform to OEM packaging equipment.
3. Connector numbering convention may not agree with board connector numbers.
2-4
Intel
Part No.
N/A
MDS985
iSBC 86/12A
Preparation for Use
Table 2-3. Line Driver and 1/0 Terminator Locations
8255A
PPI
Interface
I/O Port
Bits
Driver/Terminator
C8
0-7
None Required
CA
0-3
4-7
A12
A13
ZD4
ZD4
9ZA4
9ZA4
CC
0-3
4-7
A11
A10
ZD5
ZD5
9ZC4
9ZB4
Fig. 5-1 Grid Ref.
Fig. 5-2* Grid Ref.
-
-
*Figure 5-2 is the schematic diagram. Grid reference 9ZA4, for example, denotes sheet 9 zone A4.
Table 2-4. Jumper and Switch Selectable Options
Function
Fig. 5-1
Grid Ref.
Fig. 5-2
Grid Ref.
IROM/EPROM
Configu ration
ZC2, ZC3,
ZB6
6Z83,6ZC3,
6ZC7
Description
Jumpers E94 through E99 and switch 51 may be configured to
accommodate four types of ROM/EPROM chips:
ROM/EPROM
Type
2758
2316E/2716
2332A/2732
i5BC 340
Jumpers
E94-E95,
*E94-E96,
E94-E96,
E94-E95,
E97-E98
*E97-E98
E97-E99
E97-E99
Switch S1
-
ON
*ON
OFF
OFF
ON
*OFF
ON
OFF
Default jumpers and switch settings accommodate Intel 2316E/2716
chips. Disconnect existing configuration jumpers (if necessary) and
reset switch 51 if reconfiguration is required.
No Wait Option
ZD6
2ZB6
*Removing jumper E3-E4 creates a wait state after ROM/PROM reads.
If 2716-1,2 PROMs or 2332 ROMs are installed, the jumper can be
added, eliminating the wait state.
Dual Port RAM
(Multibus Interface
Access)
ZB6
3ZB5,3ZB7
The dual port RAM permits access by the local (on-board) CPU and
any system bus master via the Multibus interface. For local CPU
access, the dual port RAM address space is fixed beginning at location
00000. For access via the Multibus interface, one jumper and one
switch can configure the dual port RAM on any 8K boundary within the
1-:negabyte address space. Refer to paragraph 2-13 for configuration
details.
Bus Clock
ZB7
10ZB2
Default jumper *E105-E106 routes Bus Clock signal BCLK/ to the
Multibus interface. (Refer to table 2-9.) Remove this jumper only if
another bus master supplies this signal.
Constant Clock
ZB7
10ZA2
Default jumper *E103-E104 routes Constant Clock signal CCLK/ to
the Multibus interface. (Refer to table 2-9.) Remove this jumper only if
another bus master supplies this signal.
Bus Priority Out
ZB7
3ZD3
Default jumper *E151-E152 routes Bus Priority Out signal BPRO/
to the Multibus interface. (Refer to table 2-9.) Removethis jumper only
in those systems employing a parallel priority bus resolution scheme.
(Refer to paragraph 2-24.)
Bus Arbitration
ZB7,ZB8
3ZD3,3ZC4
Different combinations of CBRO and ANY ROT control the operation
of the 8289 Bus Arbiter. Table 2-13 lists the various configurations.
2-5
Preparation for Use
iSBC 86/12A
Table 2-4. Jumper and Switch Selectable Options (Continued)
Fig. 5-1
Grid Ref.
Fig. 5-2
Grid Ref.
Auxiliary Backup
Batteries
Z03, ZB6,
ZB5
1ZC7,1ZC6
If auxiliary backup batteries are used to sustain the dual port RAM
contents during ac power outages, remove default jumpers *W4(A-B),
*W5(A-8), and *W6(A-8).
On-Board -5V
Regulator
ZB6
1ZC6
The dual port RAM requires a -5V AUX input, which can be supplied
by the system -5V supply, and auxiliary backup battery, or by the onboard -5V regulator. (The -5V regulator operates from the system
-12V supply.) If a system -5V supply is available and auxiliary backup
batteries are not used, disconnect default jumper ·W5(A-8) and
connect jumper W5 (B-C). If auxiliary backup batteries are used,
disconnect default jumper ·W5(A-B); do not connect W5(8-C).
Failsafe Timer
Z06
2ZB6
If the on-board CPU addresses either a system or an on-board
memory or I/O device and that device does not return an acknowledge
signal, the CPU will hang up in a wait state. A failsafe timer is triggered
during T1 of every machine cycle and, if not retriggered within 6.2
milliseconds, the resultant time-out pulse can be used to allow the
CPU to exit the wait state. If this feature is desired, connect jumper
Function
Description
E5~E6.
Timer Input
Frequency
Input frequencies to the 8253 Programmable Interval Timer are
jumper selectable as follows:
Counter 0 (TMRO INTR)
Z03
7ZB4
E57-E58:
*E57-E56:
E57-E53:
E57-E62:
153.6 kHz.
1.23 MHz.
2.46 MHz.
External Clock to/from Port CC terminator/driver.
Counter 1 (TMR1 INTR)
Z03
7Z84
*E59-E60:
E59-E56:
E59-E53:
E59-E62:
E59-E61:
153.6 kHz.
1.23 MHz.
2.46 MHz.
External Clock to/from Port CC terminator/driver.
Counter 0 output.
Jumper E59-E61 effectively connects Counter 0 and Counter 1 in
series in which the output of Counter 0 serves as the input clock to
Counter 1. This permits programming the clock rates to Counter 1 and
thus provides longer TMR1 INTR intervals.
Counter 2 (8251A Baud Rate Clock)
E55-E58:
*E55-E54:
E55-E53:
E55-E62:
153.6 kHz.
1.23 MHz.
2.46 MHz.
External Clock to/from Port CC terminator/driver.
Z03
7ZB4
Priority Interrupts
-
Sheet 8
A jumper matrix provides a wide selection of interrupts to be interfaced to the 8086 CPU and the Multibus interface. Refer to paragraph
2-14 for configuration.
Serial I/O Port
Configuration
-
Sheet 7
Jumper posts E38 through E52 are used to configure the 8251A
USART as described in paragraph 2-15.
Parallel I/O Port
Configu ration
-
Sheet 9
Jumper posts E7 through E37 are used to configure the 8255A PPI as
described in paragraph 2-16.
*Oefault jumper connected at the factory.
2·6
iSBC 86/12A
Study table 2-4 carefully while making reference to
figures 5-1 and 5-2. If the default (factory configured) jumpers and switch settings are appropriate for
a particular function, no further action is required for
that function. If, however, a different configuration
is required, reconfigure the switch settings and/or
remove the default jumper(s) and install an optional
jumper(s) as specified. For most options, the
information in table 2-4 is sufficient for proper
configuration. Additional information, where necessary for clarity, is described in subsequent paragraphs.
2-13. RAM ADDRESSES (MULTIBUS
INTERFACE ACCESS)
The dual port RAM can be shared with other bus
masters via the Multibus interface. One jumper wire
connected between a selected pair of jumper posts
(El13 through E128) places the dual port RAM in one
of eight 128K byte segments of the I-megabyte
address space. Switch Sl is a dual-inline package
(DIP) composed of eight individual single-pole,
single-throw switches. (Two of these individual
switches are used for ROM/EPROM configuration.)
Two switches on Sl (6-11 and 5-12) are configured to
allow 8K, 16K, 24K, or 32K bytes of dual port RAM to
be accessed. Four switches on Sl (1-16, 2-15, 3-14,
and 4-13) are configured to displace the addresses
from the top of the selected 128K byte segment of
memory.
Figure 2-1 provides an example of 8K bytes of dual
port RAM being made accessible from the Multibus
interface and how the addresses are established. Note
in figure 3-1 that the Multibus interface accesses the
dual port RAM from the top down. Thus, as shown
for 8K byte access via the Multibus interface, the
bottom 24K bytes of the iSBC 86/12A board on-board
RAM is reserved strictly for on-board CPU access.
The configuration for 16K, 24K, or 32K access is done
in a similar manner. Always observe the IMPORT ANT note in figure 2-1 in that the address space
intended for Multibus interface access of the dual port
RAM must not cross a 128K boundary.
If it is desired to reserve all the dual port RAM strictly
for local CPU access, connect jumper El12-El14.
Preparation for Use
vectored priority interrupts, provides the capability
to expand the number of priority interrupts by
cascading each interrupt line with another 8259A
PIC. Figure 2-2 shows, as an example, the on-board
PIC (master) with two slave PIC's interfaced by the
Multibus interrace. This arrangement leaves the
master PIC with six inputs (IR2 through IR7) that
can be used to handle the various on-board interrupt
functions.
The master/slave PIC arrangement illustrated in
figure 2-2 is implemented by programming the
master PIC to handle IRO and IR1 as bus vectored
interrupt inputs. For example, if the Multibus
interface INT3/ line is driven low by slave PIC 1, the
master PIC will let slave PIC 1 send the vector
address to the 8086 CPU.
Each interrupt input (IRO through IR7) to the master
PIC can be individually programmed to be a non-bus
vectored (NBV) interrupt (the master PIC generates
the restart address) or bus vectored (BV) interrupt
(the slave PIC generates the restart address). Thus,
the master PIC can handle eight on-board or single
Multibus interface interrupt lines (an interrupt line
that is not driven by a slave PIC) or up to 64 interrupts
with the implementation of slave PIC's.
The iSBC 86/12A board can also generate an
interrupt to another interrupt handler via the
Multibus interface. This is accomplished by using
one of the bits of the 8255A PPI to drive the BUS
INTR OUT signal. (The BUS INTR OUT signal is
ground-true at jumper post E142 as footnoted in table
2-5.)
Default jumper E87-E89 grounds the NMI (nonmaskable interrupt) input to the CPU to prevent the
possibility of false interrupts being generated by
noise spikes. Since the NMI is not maskable, cannot
be disabled by the program, and has the highest
priority, it should only be used to detect a power
failure. For this purpose, disconnect default jumper
E87-E89 and connect E86-E89. The Power Fail
Interrupt (PFI/) is an externally generated signal
that is input via auxiliary connector P2. (Refer to
paragraph 2-25.)
2-14. PRIORITY INTERRUPTS
Table 2-5 lists the source (from) and destination (to)
of the priority interrupt jumper matrix shown in
figure 5-2 sheet 8. The INTR output of the on-board
Intel 8259A Programmable Interrupt Controller
(PIC) is applied directly to the INTR input of the 8086
CPU. The on-board PIC, which handles up to eight
2-15. SERIAL 1/0 PORT CONFIGURATION
Table 2-6 lists the signals, signal functions, and the
jumpers required (if necessary) to input or output a
particular signal to or from the serial I/O port (Intel
8251A USART).
2-7
Preparation for Use
iSBC 86/12A
SYSTEM
128K BYTE
SEGMENT
EXPLANATION
@
JUMPER
NO ACCESS
@
®
©
E12-E14
EOOOO-FFFFF
E13-E14
SELECTS X PARAMETER (128K BYTE SEGMENT)
SELECTS Z PARAMETER (MEMORY AVAILABLE TO BUS)
SELECTS Y PARAMETER (LOCATION WITHIN 128K SEGMENT)
~;;;;~;~~
AOOOO-BFFFF
E17-E18
80000-9FFFF
E19-E20
::::~::::F
E21-E22
~.3FFFF
::::::
00000-1FFFF
E27-E28
-.X PARAMETER
MEM AVAIL
TO BUS
~~j/
//
~
ADDRESS (UPPER)
XIY
~%j/
//
ADDRESS (LOWER)
XI Y Z
~
~
~
~
~~
IN THE EXAMPLE SHOWN IN THE SHADED PATH, X = COOOO, Y = OBFFF, AND
Z - 8K (01FFF). THUS,
COOOO
+OBFFF
CBFFF
-01FFF
CAOOO
~
~...,......SP--l®
~
=
=
=
=
=
X
Y
ADDRESS (UPPER)
Z (8K)
ADDRESS (LOWER)
~~~~~A
~
16K
CO"
~
24K
a
c
~
a
a
~
~
IMPORTANT
DISPLACEMENT
FFFFF
© ,.,.
~
~
~
~
g~~~ED
Z PARAMETE:DDRESS
~
~
~
-g :
THE SELECTED MEMORY SPACE CANNOT EXTEND ACROSS A 128K BYTE
BOUNDARY. THAT IS, X+Y-Z MUST BE EQUAL TO OR GREATER THAN THE
ABSOLUTE VALUE OF X.
SYSTEM
MEMORY
2.':':." 4·13
C
C
C
O'FFF
C
ceo
C
03FFF
C
C
0
C
05FFF
ceo
0
07FFF
0
09FFF
....
C
C
C
v
COO
C
C
o
o
o
OFFFF
o
C
C
C
11FFF
o
C
C
o
13FFF
....
~~~~~~ ~J---C_AOO_O-CB_FFF---I
ODFFF
o
C
o
C
o
C
o
o
17FFF
o
o
C
C
19FFF
o
o
C
o
1BFFF
o
o
o
C
o
o
o
o
v
15FFF
1DFFF
............
......
86/12A
07FFF
8K
00000
""1---------1
8K
04000
8K
02000
8K
1FFFF
--.-Y PARAMETER
Figure 2-1. Dual Port RAM Address Configuration (Multibus™ Interface Access)
2-8
06000
00000
iSBC 86/12A
Preparation for Use
SYSTEM
128K BYTE
SEGMENT
EXPLANATION
@
JUMPER
NO ACCESS
E12-E14
EOOOO-FFFFF
El3-E14
®
SELECTS X PARAMETER (128K BYTE SEGMENT)
@
SELECTS Z PARAMETER (MEMORY AVAILABLE TO BUS)
©
SELECTS Y PARAMETER (LOCATION WITHIN 128K SEGMENT)
V///A{/////LLL-t//~ ~0:
[0///////////////./0 /.RI,~p///%
AOOOO-BFFFF
E17-E18
80000-9FFFF
El9-E20
:::::~::::F
E21-E22
2
24
E2 S-3- E2 6
E
E
20000-3FFFF
00000-1 FFFF
027-028
~ARAMETER
~%j/
//
~
ADDRESS (UPPER)
X,Y
~%j/
//
ADDRESS (LOWER)
X. Y Z
~
~
~
~
~
IN THE EXAMPLE SHOWN IN THE SHADED PATH, X
Z = 16K (03FFF). THUS,
~
~
TO BUS
Sl~
~
@
Y
= OBFFF, AND
COOOO = X
+OBFFF = Y
CBFFF = ADDRESS (UPPER)
-03FFF = Z (16K)
C8000 = ADDRESS (LOWER)
~
MEMAVAIL
= coooo,
~~~~~~
~
32K
CO"
~
48K
0
C
~
~
0
0
~
IMPORTANT
"C = CLOSED
0= OPEN
THE SELECTED MEMORY SPACE CANNOT EXTEND ACROSS A 128K BYTE
BOUNDARY. THAT IS, X-'-Y-Z MUST BE EaUAL TO OR GREATER THAN THE
ABSOLUTE VALUE OF X.
Z PARAMETER
~
ADDRESS
DISPLACEMENT
~
FFFFF
Sl"
SYSTEM
MEMORY
01FFF
03FFF
05FFF
"'
C
0
0
0
OFFFF
0
C
C
C
11FFF
0
C
C
0
13FFF
0
C
0
C
0
C
0
0
0
0
C
C
0
0
C
0
0
0
0
C
0
0
0
0
15FFF
"' "'
Ce~~~
"' "' ~6'Oa
86/12A
"v
"' "'
00000
"' ~
16K
OCOOO
16K
17FFF
19FFF
08000
16K
lBFFF
lDFFF
lFFFF
-.,--
OFFFF
04000
16K
00000
Y PARAMETER
Figure 2-1. Dual Port RAM Address Configuration (Multibus™ Interface Access) (Continued)
2-9
Preparation for Use
iSBC 86/12A
Table 2-5. Priority Interrupt Jumper Matrix
Interrupt Request From
Interrupt Request To
Signal
Source
Multibus Interface (2)
(1 )
(1 )
(1 )
(1 )
(1 )
Post
Device
Multibus
Interface (2)
INTO/
INT1/
INT2/
INT3/
INT4/
INT5/
INT6/
INT7/
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
E141
E140
E139
E138
E137
E136
E135
E134
8259A PIC (6)
(5)
(5)
(5)
(5)
E81
E80
E79
E78
INTO/
INT1/
INT2/
INT3/
INT4/
INT5/
INT6/
INT7/
(1 )
(1 )
E73
E72
E71
E70
E69
E68
E66
E65
(1 )
Signal
Post
External Via J 1-50
Power Fail Logic
Via P2-19
Failsafe Timer
EXT INTO/
PFII
(1 )
(1 )
E67
E86
TIME OUT INTR
(1 )
E88
IRO
IR1
IR2
IR3
8255A PPI
Port A (Port C8)
Port B (Port CAl
Any Unused Bit
PAINTR
(1 )
(1)
PBINTR
BUS INTR OUT (3) (9)
E84
E85
E142
IR4
IR5
IR6
IR7
(5)
(5)
(5)
(5)
E77
E76
E75
E74
8251A USART
Trans Buffer Empty
Rec Buffer Empty
51TX INTR
51RX INTR
(1 )
(1 )
E90
E82
NMI
INTR
(7)
(8)
E89
-
8253 PIT
Timer 0 Out
Timer 1 Out
TMRO INTR
TMR11NTR
(1 )
(1 )
E83
E91
8086 CPU
NOTES:
(1) Signal is positive-true at associated jumper post. (Must use 8259A in edge triggered mode.)
(2) INTO/ is highest priority; INT7/ is lowest priority.
(3) Signal is ground-true at associated jumper post.
(4) Requires ground-true signal at assoicated jumper post.
(5) Requires positive-true signal at associated jumper post.
(6) IRO is highest priority; IR7 is lowest priority.
(7) Default jumper E87-E89 disables (grounds) input. The NMI input is highest priority, non-maskable, and is both level
and edge sensitive.
(8) INTR is connected directly to output of 8259A PIC.
(9) Used to generate an interrupt on Multibus interface.
r- - - -
r----------------------~~~
8086
cPU
MASTER
8259A
PIC
I
I
81
70
80
86
I
MULTIBUS
INTERFACE
INT3!
IRO
35
79
IR2
INTO!
41
0--78
INTR
INT1!
42
0---
IR3
77
IR4
0--76
IR5
0---
INPUTS FROM
ON-BOARD (NBV)
INTERRUPT
SOURCES
75
IR6
39
INT4!
37
INT5!
0--74
IR7
INT2I
38
INT7!
0---
I
L _________________________ JI
36
I
I
-
l
~O
INTR
I
I
I
I
I
I
I
INTR
I
I
I
I
I
BUS VECTORED (BV)
INTERRUPT SOURCES
L _________ J
Figure 2-2. Simplified Master/Slave PIC Interconnect Example
2-10
~LAV-;- -
PIC 1
40
INT6!
IR1
INTR
I
Preparation for Use
iSBC 86/12A
Table 2-6. Serial 1/0 Connector J2 Pin Assignments V s Configuration Jumpers
Pin 1,2
Signal
5
CHASSIS GND
TRANSMITTER DATA
SEC REC SIG2
6
7
RECEIVER DATA
REC SIG ELE TIMING
2
4
8
10
12
13
14
19
21
ROT TO SEND
CLEAR TO SEND
DATA SET RDY
DATA TERMINAL RDY
GND
-12V
TRANS SIG ELE TIMING2
22
23
25
26
+12V
+5V
GND
SEC CTS2
Function
Protective ground
8251A RXD in
Same as 8251A TXC in or
8255A STXD out (Note 3)
8251A TXD out
8251A RXC in (Note 4)
8251A TXC in (Note 4)
8251A CTS in (Note 5)
8251A RTS out (Note 5)
8251A DTR out
8251A DSR in
Ground
-12Vout
Same as 8251A TXC in or
8255A STXD out (Note 3)
+12Vout
+5Vout
Ground
Same as 8251A TXC in or
8255A STXD out (Note 3)
Jumper In
Jumper Out
E63-E64
-
E48-E49. E45-E46
E49-E50. E45-E46
*E39-E40
*E42-E43
*W3A-8
E48-E49. E44-E45
E49-E50. E44-E45
*W2A-8
*W1A-8
E48-E49. E45-E47
E49-E50. E45-E47
E38-E39
E41-E42
-
-
-
NOTES:
1. All odd-numbered pins *1,3,5, ... 25) are on component side of the board. Pin 1 is the right-most pin when viewed from the
component side of the board with the extractors at the top.
2. Only one of these signal outputs (pin 5, 21, or 26) may be selected.
3. Optional jumper selected output of 8255A PPI. Refer to figure 5-2 sheet 9.
4. Default jumpers *E39-E40and *E42-E43 connect 8253CTR2 outputto 8251A RXC and TXC inputs, respectively. See Timer
Input Frequency (Counter 2) in table 2-4.
5. For those applications without CTS capability, connect jumper E51-E52. This routes 8251A RTS output to 8251A CTS
input.
6. Cable connector numbering convention may not agree with board connector numbering convention.
* Default jumpers connected at the factory.
2-16. PARALLEL 110 PORT CONFIGURATION
Table 2-7 lists the jumper configuration for three
parallel I/O ports. Note that each of the three ports
(C8, CA, and CC) can be configured in a variety of
ways to suit the individual requirement.
2-17. MUL TIBUS INTERFACE
CONFIGURATION
For systems applications, the iSBC 86/12A board is
designed for installation in a standard Intel iSBC
604/614 Modular Backplane and Cardcage. (Referto
table 2-1 items 1 and 2.) Alternatively, the iSBC
86/12A board can be interfaced to a user-designed
system backplane by means of an 86-pin connector.
(Refer to table 2-1 item 5.) Multibus interface signal
characteristics and methods of implementing a serial
or parallel priority resolution scheme for resolving
bus contention in a multiple bus master system are
described in the following paragraphs.
Always turn off the system power supply
before installing or removing any board
from the backplane. Failure to observe this
precaution can cause damage to the board.
2-18. SIGNAL CHARACTERISTICS
As shown in figure 1-1, connector PI interfaces the
iSBC 86/12A board to the Multibus interface. Connector PI pin assignments are listed in table 2-8 and
descriptions of the signal functions are provided in
table 2-9.
The dc characteristics of the iSBC 86/12A board bus
interface signals are provided in table 2-10. The ac
characteristics of the iSBC 86/12A board when
operating in the master mode and slave mode are
provided in tables 2-11 and 2-12, respectively. Bus
exchange timing diagrams are provided in figures
2-3 and 2-4.
iSBC 86/12A
Preparation for Use
Table 2-7. Parallel 1/0 Port Configuration Jumpers
Port
C8
C8
C8
Mode
°
Input
°
Output
(latched)
1 Input
(strobed)
Driver (0)/
Terminator (T)
8226:A8, A9
8226: A8, A9
8226:A8, A9
T:Ai0
0: A11
Jumper Configuration
Restrictions
Delete
Add
*E21-E2: E24-E25
*E21-E25
*E21-E25 E24-E25
*E15-E16
8226
8226
8226
=
=
=
Effect
Port
input enabled.
CA
None; can be in mode
or 1, input or output.
CC
None; can be in Mode 0,
input or output, unless
Port CA is in Mode 1.
CA
None; can be in Mode
1, input or output.
CC
None; can be in Mode 0,
input or output, unless
Port CA is in Mode 1.
CA
None; can be in Mode
1, input or output.
CC
Port CC bits perform the
following:
output enabled.
input enabled.
Connects J1-26 to
STBAI input.
°
°
or
°
or
*E19-E20 E19-E33
and
*E32-E33
Connects IBF A output to
J1-i8.
• Bits 0, 1, 2 - Control
for Port CA if Port CA is
in Mode 1.
E22-E32
Connects INT A output to
interrupt matrix.
• Bit 3 - Port C8 Interrupt (PA INTR) to interrupt jumper matrix
• Bit 4 - Port C8 Strobe
(STB/) input.
• Bit 5 - Port C8 Input Buffer Full (IBF)
output.
• Bits 6, 7 - Port CC input or output (both,
must be in same
direction).
C8
1 Output
(latched)
8226: A8, A9
T: Ai0
0: A11
=
output enabled.
*E21-E25
8226
*E17-E18
Connects J 1 -30 to
ACKA/ input.
°
CA
None; can be in Mode
1, input or output.
CC
Port EA bits perform the
following:
or
*E32-E33 E13-E33
and
*E13-E14
Connects OBFA output
to J1-18.
• Bits 0, 1, 2 - Control
for Port CA if Port CA is
in Mode 1.
E22-E32
Connects INT A output to
interrupt matrix.
• Bit 3 - Port C8 Interrupt (PA INTR) to interrupt jumper matrix.
• Bits 4, 5 - Port CC inputoroutput(both must
be in same direction).
• Bit 6 - Port C8 Acknowledge (ACK/)
input.
• Bit 7 - Port C8 Output
Buffer Full (OBF/)
output.
*Default jumper connected at the factory.
2-12
I
Preparation for Use
iSBC 86/12A
Table 2-7. Parallel I/O Port Configuration Jumpers (Continued)
Port
Mode
CB
2
(bidirectional)
Jumper Configuration
Driver (D)/
Terminator (T)
Restrictions
Delete
B226:AB, A9
T: A10
D: A11
Add
*E21-E25 E17-E25
I
I
I
Port
Allows ACKAI input to
control B226 in/out
direction.
CA
None; can be in Mode 0 or
1, input or output.
CC
Port CC bits perform the
following:
*E15-E16
Connects J1-26 to STBAI
input.
• Bit 0 - Can only be
used for jumper option
(see figure 5-2 zone
9ZC6).
*E19-E20 E19-E27
and
*E26-E27
Connects IBFA output
to J1-24.
• Bits 1,2- Can be used
for input or output if
Port CC is in Mode O.
*E17-E1B
I
I
Effect
Connects J 1-30 to
ACKAI input.
*E13-E14 E13-E33
and
*E32-E33
Connects OBFAI output
to J1-1B.
E22-E32
Connects tNT A output to
interrupt matrix.
• Bit 3 - Port CB Interrupt (PA INTR) to interrupt jumper matrix.
I
I
I
• Bit 4 - Port CB Strobe
(STBI) input.
• Bit 5 - Port CB Input
Buffer Full (IBF) output.
• Bit 6 - Port CB Ac(ACK/)
knowledge
input.
• Bit 7 - Port CB Output
Buffer Full (OBF/)
output.
CA
CA
o Input
o Output
T:A12, A13
D: A12, A13
None
None
None
None
CB
None.
CC
None; Port CC can be in
Mode 0, input or output, if
Port CB is also in Mode O.
CB
None
CC
None; Port CC can be in
Mode 0, input or output, if
Port CB is also in Mode O.
CB
None.
CC
Port CC bits perform the
following:
(latched)
CA
1 Input
(strobed)
T:A10,A12,A13
D: A11
*E28-E29
*E13-E14 E14-E30
and
*E3G-E31
E26-E34
Connects IBF B output
to J1-22.
Connects J 1 -32 to
STBB/ input.
Connects INTB output
interrupt matrix.
• Bit 0 - Port CA Interrupt (PB INTR) to interrupt jumper matrix.
• Bit 1 - Port CA Input
(IBF)
Full
Buffer
output.
• Bit 2 - Port CA Strobe
(STBI) input.
* Default jumper connected at the factory.
2-13
iSBC 86/12A
Preparation for Use
Table 2-7. Parallel 1/0 Port Configuration Jumpers (Continued)
Port
Mode
Driver (D)
Terminator (T)
Jumper Configuration
Restrictions
Delete
Add
Effect
Port
• Bit 3 - If Port CB is in
Mode 0, bit 3 can be input or output. Otherwise, bit 3 is reserved.
• Bits 4, 5 - Depends on
Port CB mode.
• Bits 6, 7 -Input or output (both must be in
same direction).
CA
1 Output
(latched)
T:A10
D:A11,A12 A13
*E2B-E29
Connects OBF sf output
output J1-22.
CB
None.
CC
Port CC bits perform the
following:
*E13-E14 E14-E30
and
*E3G-E31
Connects J 1 -32 to
ACKsl input.
• Bit 0 - Port CA interrupt (PB INTR) to interrupt jumper matrix.
*E26-E27 E26-E34
Connects INT s output to
interrupt matrix.
• Bit 1 - Port CA Output Buffer Full (OBF/)
output.
• Bit 2 - Port CA Ac(ACKI)
knowledge
input.
• Bit 3 - If Port CB is in
Mode 0, bit 3 can be input or output. Otherwise, bit 3 is reserved.
• Bits 4, 5 - Input or output (both must be in
same direction).
• Bit 6, 7 - Depends on
Port CB mode.
CC
(upper)
o Input
T: A10
None
*E15-E16
*E19-E20
*E17-E1B
*E13-E14
Connects bit 4 to J1-26.
Connects bit 5 to J1-2B.
Connects bit 6 to J1-30.
Connects bit 7 to J1-32.
CB
CA
CC
(lower)
o Input
T: A11
None
*E26-E27 Connects bit 0 to J1-24.
*E2B-E29 Connects bit 1 to J1-22.
*E3G-E31 Connects bit 2 to J1-20.
*E32-E33 Connects bit 3 to J1-1B.
CB
CA
CA
(upper)
o Output
(latched)
D: A10
None
CA
(lower)
o Output
D: A11
None
(latched)
*Default jumper connected at the factory.
2-14
Port CB must be in Mode
all four bits to be
available.
o for
Port CA must be in Mode
all four bits to be
available.
o for
Port CB must be in Mode
all four bits to be
available.
o for
Port CA must be in Mode
all four bits to be
available.
o for
Same as for Port CC (upper) mode
CB
Same as for Port CC
(upper) Mode 0 Input.
Same as for Port CC (lower) Mode
o Input.
CC
Same as for Port CC
(lower) Mode 0 Input.
o Input.
iSBC 86/12A
Preparation for Use
Table 2-8. Multibus™ Interface Connector PI Pin Assignments
(COMPONENT SIDE)
P!N1,2
MNEMONIC
DESCR!PTION
(CIRCUIT SIDE)
PIN1,2
DESCR!PT!ON
MNEMONIC
1
GND
Signal GND
2
GND
Signal GND
3
+5V
+5Vdc
4
+5V
+5Vdc
POWER
5
+5V
+5Vdc
6
+5V
+5Vdc
SUPPLIES
7
+12V
+12Vdc
8
+12V
+12Vdc
9
-5V
-5Vdc
10
-5V
-5Vdc
11
GND
Signal GND
12
GND
Signal GND
13
BCLKI
INIT/
Bus Clock
14
Reserved
16
MRDC/
Bus Busy
Mem Read Cmd
20
MWTC/
Mem Write Cmd
10RC/
I/O Read Cmd
22
10WC/
I/O Write Cmd
XACK/
XFER Acknowledge
24
INH1/
Inhibit 1 disable RAM
Reserved
26
Byte High Enable
28
AD10/
15
17
19
21
23
BUS
CONTROLS
BUSY/
25
BUS
27
BHEN/
CONTROLS
29
31
CBRO/
I CCLK/
33
INTA/
35
37
AND
ADDRESS
INTERRUPTS
ADDRESS
DATA
I
SUPPLIES
18
Reserved
Reserved
Common Bus Request
30
AD11/
Constant elk
32
AD12/
Interrupt Acknowledge
34
I AD13/
INT6/
Parallel
36
INT7/
INT4/
Interrupt
INT5/
Interrupt
39
41
INT2/
Requests
38
40
INT3/
Requests
INTO/
42
INT1/
I
Address
I
Bus
Parallel
43
ADRE/
44
ADRF/
45
ADRC/
46
ADRD/
47
ADRAI
Address
48
ADRB/
Address
49
ADR8/
Bus
50
ADR9/
Bus
51
ADR6/
ADR7/
53
ADR4/
52
54
55
ADR2/
56
ADR3/
57
ADRO/
58
ADR1/
59
61
DATE!
60
DATF/
DATC/
62
DATD/
63
DATAl
64
DATB/
65
DAT8/
Data
66
DAT9/
Data
67
DAT6/
Bus
68
DAT7/
Bus
69
71
DAT4/
70
DAT5/
DAT2/
72
DAT3/
73
DATO/
74
DAT1/
75
GND
Signal GND
76
GND
Signal GND
78
79
-12V
Reserved
-12Vdc
-12V
-12Vdc
+5Vdc
77
POWER
Initialize
Reserved
80
ADR5/
Reserved
81
+5V
+5Vdc
82
+5V
83
+5V
+5Vdc
84
+5V
+5Vdc
85
GND
Signal GND
86
GND
Signal GND
1. All odd-numbered pins (1,3,5 ... 85) are on component side of the board. Pin 1 is the left-most pin when viewed from
the component side of the board with the extractors at the top. All unassigned pins are reserved.
2-15
Preparation for Use
iSBC 86/12A
Table 2-9. Multibus™ Interface Signal Functions
Signal
2-16
Functional Description
ADRO/-ADRF/
ADR10/-ADR13/
Address. These 20 lines transmit the address of the memory location or I/O port to be
accessed. For memory access, ADRO/ (when active low) enables the even byte (DA TO/DAT7/) on the Multibus interface; i.e., ADRO/ is active low for all even addresses. ADR13/
is the most significant address ibt.
BClK!
Bus Clock. Used to synchronize the bus contention logic on all bus masters. When generated by the iSBC 86/12A board, BClK/ has a period of 108.5 nanoseconds (9.22 MHz)
with a 35-65 percent duty cycle.
BHENI
Byte High Enable. When active low, enables the odd byte (DAT8/-DATF/) onto the Multibus interface.
BPRNI
Bus Priority In. Indicates to a particular bus master that no higher priority bus master is requesting
use of the bus. BPRNI is synchronized with BClK!.
BPROI
Bus Priority Out. In serial (daisy chain) priority resolution schemes, BPROI must be connected
to the BPRN/ input of the bus master with the next lower bus priority.
BREO/
Bus Request. In parallel priority resolution schemes, BREOI indicates that a particular bus
master requires control of the bus for one or more data transfers. BREOI is synchronized
with BClK!.
BUSYI
Bus Busy. Indicates that the bus is in use and prevents all other bus masters from gaining
control of the bus. BUSYI is synchronized with BClK!.
CBROI
Common Bus Request. Indicates that a bus master wishes control of the bus but does not
presently have control. As soon as control of the bus is obtained, the requesting bus controller
raises the CBRO/ signal.
CClK!
Constant Clock. Provides a clock signal of constand frequency for use by other system
modules. When generated by the iSBC 86/12A board, CCLK/ has a period of 108.5 nanoseconds (9.22 MHz) with a 35-65 percent duty cycle.
DATO/-DATF/
Data. These 16 bidirectional data lines transmit and receive data to and from the addressed
memory location or I/O port. DATF/ is the most-significant bit. For data byte operations,
DATO/-DAT71 is the even byte and DAT8I-DATF/ is the odd byte.
INH11
Inhibit RAM. For system applications, allows iSBC 86/12A board dual port RAM addresses
to be overlayed by ROM/PROM or memory mapped I/O devices. This signal has no
effect on local CPU access of its dual port RAM.
INIT/
Initialize. Resets the entire system to a known internal state.
INTA'
Interrupt Acknowledge. This signal is issued in response to an interrupt request.
INTO/-INT7/
Interrupt Request. These eight lines transmit Interrupt Requests to the appropriate interrupt
handler. INTO has the highest priority.
10RCI
I/O Read Command. Indicates that the address of an I/O port is on the Multibus interface
address lines and that the output of that port is to be read (placed) onto the Multibus interface data lines.
10WCI
I/O Write Command. Indicates that the address of an I/O port is on the Multibus interface
interface address lines and that the contents on the Multibus interface data lines are to be
accepted by the addressed port.
MRDC/
Memory Read Command. Indicates that the address of a memory location is on the Multibus interface address I ines and that the contents of that location are to be read (placed) on
the Multibus interface data lines.
MWTC/
Memory Write Command. Indicates that the address of a memory location is on the Multibus interface address lines and that the contents on the Multibus rnterface data lines are to
be written into that location.
XACK!
Transfer Acknowledge. Indictes that the addressed memory location has completed the
specified read or write operation. That is, data has been placed onto or accepted from
the Multibus interface data lines.
Preparation for Use
iSBC 86/12A
Table 2-10. iSBC 86/12ATM Board DC Characteristics
Signals
Parameter
Description
Symbol
AACKJ, XACKJ
VOL
Output Low Voltage
\/_ ..
YUH
Output High Voltage
Vil
Input Low Voltage
VIH
Input High Voltage
III
Input Current at Low V
IIH
Input Current at High V
-1.4
rnA
15
pF
Input Low Voltage
VIH
Input High Voltage
III
Input Current at Low V
0.55
2.4
0.8
V
V
2.0
VIN = 0.45V
V
V
-0.50
rnA
50
IIH
Input Current at High V
VIN = 5.25V
IlH
Output Leakage High
Vo = 5.25V
-0.50
/LA
rnA
Output Leakage Low
Vo = 0.45V
-0.50
rnA
18
pF
VOH
Capacitive Load
Output Low Voltage
I
I
..
Output High Voltage
Vil
Input Low Voltage
VIH
Input High Voltage
III
Input Current at Low V
Input Current at High V
0.5
IOl = 59.5 rnA
I IOH
=
-3 rnA
I
V
V
2.7
0.8
V
VIN = 0.45V
-0.5
rnA
VIN = 5.25V
40
15
/LA
pF
0.4
V
0.8
V
V
2.0
Capacitive Load
VOL
Output Low Voltage
IOl = 16 rnA
VOH
Output High Voltage
IOH = -2.0 rnA
Vil
Input Low Voltage
VIH
Input High Voltage
III
Input Current at Low V
VIN = O.4V
1.6
rnA
Input Current at High V
VIN = 2.4V
40
/LA
pF
Capacitive Load
Input Low Voltage
VIH
III
Input Current at Low V
VIN = O.4V
IIH
*C l
Input Current at High V
VIN = 5.25V
0.8
VOL
Output Low Voltage
IOl = 5.0 rnA
Output High Voltage
IOH = -0.4 rnA
Output High Voltage
*Cl
VOL
V IL
Input High Voltage
IlL
Input Current at Low V
IIH
0.45
V
15
pF
V
0.45
IOL = 20 rnA
VIN = 0.45V
Input Current at High V VIN = 5.25V
Capacitive Load
/LA
pF
V
V
2.4
Input Low Voltage
V IH
*C L
IOL = 50 rnA
IOH = -0.4 rnA
Capacitive Load
Output Low Voltage
rnA
50
2.4
Capacitive Load
Output Low Voltage
-0.5
18
VOH
V
V
2.0
Capacitive Load
VO H
V
15
Input High Voltage
VOL
V
2.4
2.0
Vil
*Cl
BUSY/, CBRQ/,
INTROUT/
(OPEN COLLECTOR)
VIN = 2.4V
Vil
IIH
BREQ/
VIN = O.4V
rnA
IOl = 32 rnA
*Cl
BPRO/
V
-2.2
IOH = 3 rnA
IIH
BPRN/
V
V
2.0
Output Low Voltage
*Cl
BHEN/
0.8
Output High Voltage
VOL
I
Units
V
2.0
IOH = -3 mA
VOL
III
BCLKJ
Max.
.04
IOl= 16 rnA
VOH
*CL
I
Min.
Capacitive Load
*Cl
ADRO/-ADRF/
ADR10/-ADR13/
Test
Conditions
10
pF
0.45
0.4
V
V
-0.5
rnA
40
/LA
20
pF
V
2.4
2-17
Preparation for Use
iSBC 86/12A
Table 2-10. iSBC 86/12ATM Board DC Characteristics (Continued)
Signals
CCLKi
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
Output Low Voltage
IOL = 32 rnA
Output High Voltage
IOH
Input Low Voltage
Input High Voltage
IlL
Input Current at Low V
VIN = 0.45V
ILH
Output Leakage High
Vo
V
15
pF
V
0.45
V
V
2.0
= 5.25V
V
V
2.4
-0.20
rnA
100
/-I- A
18
pF
0.8
V
Input Low Voltage
VIH
Input High Voltage
IlL
Input Current at Low
VIN
= 0.5V
-2.0
rnA
Input Current at High
VIN
cc
2.7V
50
/-I- A
18
pF
0.4
V
0.8
V
V
2.0
Capacitive Load
VOL
Output Low Voltage
IOL = 44 rnA
VOH
Output High Voltage
OPEN
COLLECTOR
V IL
Input Low Voltage
VIH
Input High Voltage
IlL
Input Current at Low V
VIN '" O.4V
-4.2
rnA
Input Current at High V
VIN
= 2.4V
-1.4
rnA
15
pF
V IL
2.0
Capacitive Load
Input Low Voltage
V
0.8
V
V
V IH
Input High Voltage
IlL
Input Current at Low V
VIN = O.4V
-1.6
rnA
IIH
Input Current at High V
VIN
= 2.4V
40
/-I- A
18
pF
0.45
V
';'C L
VOL
2.0
Capacitive Load
Output Low Voltage
IOL = 32 rnA
V
2.4
VO H
Output High Voltage
IOH = -5 rnA
ILH
Output Leakage High
Vo = 5.25V
100
/-I- A
ILL
Output Leakage Low
Vo
= 0.45V
-100
/-I- A
15
pF
*C L
Capacitive Load
VOL
Output Low Voltage
IOL = 30 rnA
VOL
Output High Voltage
IOH = -5 rnA
VIL
Input Low Voltage
VIH
Input High Voltage
IlL
Input Current at Low V
VIN = 0.45V
IIH
Input Current at High V
VIN
*C L
Capacitive Load
*Capacitive load values are approximations.
2-18
0.5
2.7
Capacitive Load
Units
VIL
'CL
INTA/. MRDC .
MWTCI
Max.
0.80
VIL
IIH
IORC,.IOWC
= -5 rnA
V IH
*C L
INTOi-INT7
Min.
Capacitive Load
VO H
IIH
INIT
(SYSTEM RESET)
= 60 rnA
= -3 rnA
VOL
*CL
INH1/
Test
Conditions
VOL
*CL
DATOI-DATF/
Parameter
Description
Symbol
0.45
2.4
0.95
V
-2.0
rnA
1000
/-I- A
25
pF
V
2.0
= 5.25
V
V
iSBC 86/12A
Preparation for Use
Table 2-11. iSBC 86/12ATM Board AC Characteristics (Master Mode)
Minimum
(ns)
Parameter
tAS
tAH
tos
tCY
tCMoR
tCMOW
tcswR
tCSRR
tcsww
tCSRW
tXACK1
tSAM
tACKRO
tACKWT
tOHR
tOXL
tXKH
tXKO
tsws
tss
tDBY
tCSRO
tCSROS
tNOO
toso
toso
tsCY
tsw
tlNIT
50
50
50
198
430
430
380
380
580
580
-208
202
115
205
0
-115
0
0
35
23
I
0
I Maximum
(ns)
I
202
210
00
55
60
35
30
35
40
108
109
35
74
Description
Address setup time to command
Address hold time from command
Data setup to write CMD
CPU cycle time
Read command width
Write command width
Read-to-write command separation
Read-to-write command separation
Write-to-write command separation
Write-to-read command separation
Command to XACK first sample point
Time between XACK samples
AACK to valid read data
AACK to write command inactive
Read data hold time
Read data setup to XACK
XACK hold time
AACK or XACK turn off delay
Bus clock low or high intervals
BPRN to BCLK setup time
BCLK to BUSY delay
BCLK to CBRQ
CBRQ to BCLK setup time
BPRN to BPRO delay
BCLK/ to bus request
BCLK/ to bus priority out
Bus clock period (BCLK)
Bus clock low or high interval
Initialization width
3000
I
Remarks
No wait states
With 1 wait state
In override mode
In override mode
In override mode
In override mode
In override mode
In override mode
When AACK is used
When AACK is used
Supplied by system
I
From iSBC 86/12A board
when terminated
From iSBC 86/12A board
when terminated
After all voltages have stabilized
Table 2-12. iSBC 86/12ATM Board AC Characteristics (Slave Mode)
Parameter
tAS
tos
toso
tACK
tCMO
tAH
tOHW
tOHR
tXKH
tACC
tlH
tlPW
tCY
tRO
tOXL
tcs
tiS
Minimum
(ns)
Maximum
(ns)
50
-200
980
720
720
0
0
0
0
65
640
50
100
920
555
30
200
50
Remarks
Description
Address setup to command
Write data setup to command
On-board memory cycle delay
Command to XACK
Command width
Address hold time
Write data hold time
Read data hold time
Acknowledge t:\old time
Read to data valid
Inhibit hold time
Inhibit pulse width
Cycle time of board
Refresh delay time
Read data setup to XACK
Command separation
Inhibit setup time
From address to command
Note 1
No refresh
Notes 1 and 2
Note 1
Acknowledge turnoff delay
Note 3
Blocks AACK if tiS > tiS min.
Note 4
NOTES:
1. No refresh, dual port RAM not busy.
2. Maximum = tRO + toso + tACK·
3. Maximum access = tAce + toso + tRO.
4. Maximum cycle = tCY + toso + tRO.
2-19
Preparation for Use
iSBC 86/12A
IBCy--1
H r-
IBW--1
IBW
BCLKI
BREOI
BPRNI
L ____
BUSYI
ICBROS
ICBROS
-J
CBRO/*
ICBRO
BPROI
lOBO
ADDRESS
~
WRITE DATA
~
lAS. IDS
WRITE COMMAND
\
~
(
~X
(
STABLE ADDRESS
J __
r---
STA_BLEDA_TA
-1 r:=
IAH.IDHW
ICMDW _ _ _ _---+l
.. Ir-~------
\..
\
7
WRT AACKI
READ
\~---------ICMDR--------~~I
READ DATA
IDXl
READ XACKI
READ AACKI
J
I
LIXKD
L ! - - - - - ' I A C K R D; . . . . . - - -
---~--_I__--,/
'" CBROI timing not shown relative to other bus signals other than BCLK/.
Figure 2-3. Bus Ex('hange Timing (Master Mode)
2-20
Preparation for Use
iSBC 86/12A
~---------------tCMD----------------~
-,
~------------tACK------------~
r-----~----------------------------~----~----~,
STABLE ADDRESS
ADDRESS
MWTCI
XACKJ
------I
I
tDS
tDHW
j.--
----------)<:~----------------------S-T-A-B-LE--D-A-TA-----------------------~
DATA
DUAL PORT RAM WRITE
STABLE ADDRESS
ADDRESS
MRDCI
~-------------tACK------------~~
XACKJ
~-----------tACC----------~~
DATA
INH1!
~I
\J.j
tiS
tlH
+
f.ol·.----------------------tIPw---------------------~·~1
DUAL PORT RAM READ
Figure 2-4. Bus Exchange Timing (Slave Mode)
2-21
Preparation for Use
iSBC 86/12A
2-19. MULTIBUS INTERFACE
ARBITRATION
The 8289 Bus Arbiter operates in conjunction with
the 8288 Bus controller to interface the 8086 processor
to the Multibus interface. The 8289 Bus Arbiter can
operate in several modes, depending on how it is
jumper wired and the status of Common Bus Request
(CBRQ/).
2-20. COMMON BUS REQUEST. Common Bus
Request (CBRQ/), a bidirectional Multibus interface
signal, allows a bus master to retain control of the
system bus without contending for it each transfer
cycle, as long as no other master is requesting control
of the bus. A bus master requesting control of the
bus, but not currently controlling it, asserts CBRQ/.
This causes the controlling bus master to relinquish
control of the bus when the proper surrender
conditions exist. (See table 2-13 for surrender
conditions).
The CBRQI pins of all the bus master devices that
support CBRQI are connected together on the iSBC
6041614 modular backplane. When a bus master
needs a bus resource, it informs the other bus masters
that it is requesting the bus by activating CBRQ/,
BREQ/, and/or BPROI. When the controlling
master releases the bus, the bus exchange operates
the same as described in paragraph 4-26.
CBRQI improves bus access time by allowing a bus
master to retain control without contending for it
each transfer cycle, as long as no other master is
requesting control of the bus.
There are typically two priority resolution schemes
used on the system bus: Serial and parallel. When
common bus request is used, it operates identically in
parallel and serial priority resolution schemes.
2-21. ANY REQUEST. The 8289 Bus Arbiter has
a jumper option (ANYRQST) that controls, in
conjunction with BPRNI and CBRQ/, under what
conditions the Multibus interface will be surrendered. The following paragraphs describe this
option.
When ANYRQST is jumpered to a low level (E130E131), the bus arbiter that was in control of the
Multibus interface will retain control unless one of
the following conditions exist.
1. A higher priority bus master requests the
Multibus interface (as indicated by the BPRNI
signal going high).
2.
The next transfer cycle of the iSBC 86/12A board
does not require the use of the Multibus interface,
and CBRQI is low.
Table 2-13. 8289 Bus Arbiter Jumper Configurations
Configuration
Number
Jumper
Conn
1
E144-E145
E130-E131
2
3
E144-E145
E129-E130
E143-E144*
E129-E130*
*Factory default wiring.
2-22
CBRQI
ANYRQST
Description
Low
Low
The Bus Arbiter that has control of the Multibus interface
will retain control unless a higher priority master activates
CBROI or if the next machine cycle does not require the use
of the Multibus interface it will be relinquished to a lower
priority device.
High
Low
The Bus Arbiter that has control of the Multibus interface,
retains control until another Bus Arbiter pulls CBROI low.
When CBROI goes low, the conditions are as described
above.
Low
High
The Bus Arbiter that has control of the Multibus interface
will surrender control to the Bus Arbiter that is pulling CBROI
low, regardless of its priority, upon completion of the current
bus cycle.
High
High
The Bus Arbiter that has control of the Multibus interface,
retains control until another Bus Arbiter pulls CBROI low.
When CBROI goes low, the conditions are as described
above.
Low
High
The Bus Arbiter that has control of the Multibus interface
will surrender the use of the Multibus interface after each
transfer cycle.
Preparation for Use
iSBC 86/12A
When ANYRQST is jumpered to a high level (E 129E130), it permits the Multibus interface to be
surrendered to a higher or lower priority bus master
as though it were a bus master of higher priority. A
lower priority master indicates it is requesting the
Iviultibus interface by activating CBRQ/. When this
option is used, the bus master that is in control will
surrender the bus as soon as possible.
If the CBRQI pin on the 8289 Bus Arbiter isjumpered
to ground (E144-E143), removing it from the
Multibus interface, and ANYRQST is jumpered to a
high level (E129-E130), the Multibus interface is
surrendered after each transfer cycle (this is the
factory default option).
2-22. JUMPER CONFIGURATIONS. Table
2-13 lists the various jumper configurations for the
8289 Bus Arbiter.
2-23. SERIAL PRIORITY RESOLUTION
In a multiple bus master system, bus contention can
be resolved in an iSBC 604 Modular Backplane and
Cardcage by implementing a serial priority resolution scheme as shown in figure 2-5. Due to the
propagation delay of the BPROI signal path, this
scheme is limited to a maximum of three bus masters
capable of acquiring and controlling the Multibus
interface. In the configuration shown in figure 2-5,
the bus master installed in slot J2 has the highest
priority and is able to acquire control of the Multibus
interface at any time because its BPRNI input is
always enabled (tied to ground) through jumpers B
and N on the backplane.
If the bus master in slot J2 desires control of the
Multibus interface, it drives its BPROI output high
and inhibits the BPRNI input to all lower-priority
bus masters. When finished using the Multibus
interface, the J2 bus master pulls its BPROI output
low and gives the J3 bus master the opportunity to
take control of the Multibus interface. If the J3 bus
master does not desire to control the Multibus
interface at this time, it pulls its BPROI output low
and gives the lowest priority bus master in slot J4 the
opportunity to assume control of the Multibus
interface.
The serial priority scheme can be implemented in a
user-designed system bus if the chaining of BPROI
and BPRNI signals are wired as shown in figure 2-5.
2-24. PARALLEL PRIORITY RESOLUTION
A parallel priority resolution scheme, using external
logic, allows up to 16 bus masters to acquire and
control the Multibus interface. Figure 2-6 illustrates
HIGHEST
PRIORITY
MASTER
LOWEST
PRIORITY
MASTER
J2
~
~
BPRN/
CBRQI
~
I
I
I
I
~
CBRQI
-
---------
~
",29
p!!.-
BPROI
i-- f-----------
I
29
BPRNI
J!-
BPROI
I
I
J4
J3
BPRN/
BPROI
BPROI AND BPRNI PINS
NOT USED BY
NON-MASTERS
--- ----- ----- ------4
B(
C )
EO
H(
N
1
1
1
-I
I
I Bl~~~~~~E
I (BOTTOM)
I
I
-=~-------- - - - - - - - - __________________________ J
~ R4*
~
?
1KD
+5V
*Pull-up resistor is supplied by the customer.
NOTE: All non CBRQ/ devices must have higher priority. If a non CBRQ/ device is placed at a lower priority, it will not
be able to gain control of the Multibus interface.
Figure 2-5. Serial Priority Resolution Scheme
2-23
Preparation for Use
iSBC 86/12A
IMPORTANT: In a parallel priority resolution
scheme, the BPROI output must be disabled on all
bus masters. On the iSBC 86/12A board disable the
BPROI output signal by removing jumper E151E152. If a similar jumper cannot be removed on the
other bus masters, either clip the IC pin that supplies
the BPROI output signal to the Multibus interface or
cut the signal trace.
one method of implementing such a scheme for
resolving bus contention in a system containing
eight bus masters installed in an iSBC 604/614
Modular Backplane and Cardcage. Notice that the
two highest and two lowest priority bus masters are
shown installed in the iSBC 604 Modular Backplane
and Cardcage.
In the scheme shown in figure 2-6, the priority
encoder is a 74148 and the priority decoderis an Intel
8205. Input connections to the priority encoder
determine the bus priority, with input 7 having the
highest priority and input 0 having the lowest
priority. Here, the J3 bus master has the highest
priority and the J5 bus master has the lowest
priority.
J2
J3
J4
J5
(NOTE 1)
(NOTE 1)
(NOTE 1)
BREa!
h
~
29
~ BPRN! CBRal
BPRN!
p!!-
r ---------- OB
NO.8
PRIORITY
(LOWEST)
NO.7
PRIORITY
(NOTE 1)
~ BPRN! CBRa
I
A mating connector must be installed in the iSBC
604/614 Modular Cardcage and Backplane to
accommodate auxiliary connector P2. (Refer to
NO.1
PRIORITY
(HIGHEST)
NO.2
PRIORITY
I
2-25. POWER FAIL/MEMORY
PROTECT CONFIGURATION
BREa!
f--
A
~
--------- D(
C
L - --------- ---
--------- -
BREal
~ BPRN! CBRa
29
p!L
BREa!
F(
OE
1----------
( H
--
6
BREa! INPUTS
r~~~~:l~TERS
0
{-<
--C 54
. --C 3
--C2
,.c
.--- f--<:
P
R
I
1
0
R
I
T
Y
E
N
C
0
D
E
P
R
I
0
10---
2~}
3 0 - ~~~~~TS
D
E
C
SO-
0
D
E
4 0-
TO MASTERS
IN iSBC 614
6h
7
NOTES:
1. Refer to paragraph 2-24 regarding the disabling of BPRO/ output.
2. Supplied by customer.
Figure 2-6. Parallel Priority Resolution Scheme
2-24
G
>
f
5V
I-l iSB C 604
BA CKPLANE
I (BO TTOM)
I
r--------- __ .J
Op-
R
I
T
Y
R4
1K!l
(NOTE 2)
~
I
1 - - - - - - - - - - -~- --------- -
BUS PRIORITY
RESOLVER
(NOTE 2)
-C 7
29
Preparation for Use
iSBC 86/12A
figure 1-1.) Table 2-2 lists some 60-pin connectors
that can be used for this purpose; solder and wirewrap
connector types are listed. Table 2-14 correlates the
signals and pin numbers on the connector.
b. Connect +5V battery input to P2 pins 3 and 4, -5V
battery input to P2 pins 7 and 8, and +12V battery
input to P2 pins 11 and 12. Remove jumpers W4,
W5, and W6.
Procure the appropriate mating connector for P2 and
secure it in place as follows:
c. Connect MEM PROTI input to P2 pin 20.
a. Position holes in P2 mating connector over
mounting holes that are in line with corresponding PI mating connector.
b. From top of connector, insert two 0.5-inch #4-40
pan head screws down through connector and
mounting holes.
c. Install a flat washer and star-type nut on each
screw; then tighten the nuts.
When the mating connector for P2 is in place, wire the
power fail signals to the appropriate pins of the
connector as listed in table 2-14. (The dc characteristics of the signals interfaced via P2 are given in table
2-15.) In a typical system, these signals would be
wired as follows:
a. Connect auxiliary signal common and returns
for +5V, -5V, and +12V backup batteries to P2
pins 1, 2, 21, and 22.
d. Connect PFII input to P2 pin 19; this signal is
inverted and applied to the priority jumper
matrix. To assign the PFII input the highest
priority (8086 NMI input), remove jumper E87E89 and connect jumper E86-E89.
e. Connect AUX RESET I input to P2 pin 38. This
signal is usually supplied by a momentaryclosure switch mounted on the system enclosure.
f. Connect ALE output signal to P2 pin 32.
2-26. PARALLEL 1/0 CABLING
Parallel 1/0 ports C8, CA, and CC, controlled by the
Intel 8255A Programmable Peripheral Interface
(PPI), are interfaced via edge connector J1. (Refer to
figure 1-1.) Pin assignments for connector Jl are
listed in table 2-16; dc characteristics of the parallel
1/0 signals are given in table 2-17. Table 2-2 lists
Table 2-14. Auxiliary Connector P2 Pin Assignments
Pin
1,2
Signal
Definition
1
2
GND
GND
}
Auxiliary common
3
8
11
12
+5V AUX
+5V AUX
-5V AUX
-5V AUX
+12V AUX
+12V AUX
}
Auxiliary backup battery supply
19
PFI/
Power Fai/lnterrupt. This externally generated signal, which is input
to the priority interrupt jumper matrix, should normally be connected to the 8086 CPU NMI input.
20
MEM PROT/
Memory Protect. This externally generated signal prevents access
to the dual port RAM during backup battery operation.
21
22
GND
GND
32
ALE
Address Latch Enable. This iSBC 86/12A board activates ALE during
T1 of every CPU/ machine cycle. This signal may be used as an
auxiliary address latch.
38
AUX RESET/
Reset. The externally generated signal initiates a power-up sequence;
i.e., initializes the iSBC 86/12A board and resets the entire system to
a known internal state.
4
7
}
Auxiliary common
1. All odd-numbered pins (1,3,5 ... 59) are on component side of the board. Pin 1 is the left-most pin when viewed from
the component side of the board with the extractors at the top.
2. Cable connector numbering convention may not-agree with board connector numbering convention.
2-25
Preparation for Use
iSBC 86/12A
Table 2-15. Auxiliary Signal (Connector P2) DC Characteristics
Signals
ALE
PFI
MEM PROT/
AUX RESETI
Test
Conditions
Parameter
Description
Symbol
VOL
VOH
*CL
Output Low Voltage
Output High Voltage
Capacitive Load
VIL
VIH
IlL
IIH
*CL
Input Low Voltage
Input High Voltage
Input Current at Low V
Input Current at High V
Capacitive Load
VIL
VIH
IlL
IIH
*CL
Input Low Voltage
Input High Voltage
Input Current at Low V
Input Current at High V
Capacitive Load
VIL
VIH
IlL
IIH
*CL
Input Low Voltage
Input High Voltage
Input Current at Low V
Input Current at High V
Capacitive Load
IOL
IOH
=
=
Min.
8 mA
-1.0 mA
Max.
Units
V
V
pF
0.45
2.4
20
0.8
2.4
-0.4
20
20
VIN = O.4V
VIN = 2.4V
V
V
mA
/-L
pF
V
V
mA
/-LA
pF
0.80
2.0
VIN = 0.45V
VIN = 5.25V
-6.0
250
15
0.8
2.6
VIN
VIN
=
=
-0.25
10
10
0.45V
5.25V
V
V
mA
/-LA
/-L F
*Capacitance load values are approximations.
some 50-pin edge connectors that can be used for
interface to J1 and J2; flat crimp, solder, and
wirewrap connector types are listed.
The transmission path from the I/O source to the
iSBC 86/12A board should be limited to 3 meters (10
feet) maximum. The following bulk cable types (or
equivalent) are recommended for interfacing with
the parallel I/O ports:
a. Cable, flat, 50-conductor, 3M 3306-50.
b. Cable, flat, 50-conductor (with ground plane),
3M 3380-50.
c. Cable, woven, 25-pair, 3M 3321-25.
An Intel iSBC 956 Cable Set, consisting of two cable
assemblies, is recommended for parallel I/O
interfacing. Both cable assemblies consist of a
50-conductor flat cable with a 50-pin PC connector
at one end. When attaching the cable to J1, be sure
that the connector is oriented properly with respect to
pin 1 on the edge connector. (Refer to the footnotes in
table 2-16.)
2-27. SERIAL I/O CABLING
Pin assignments and signal definitions for RS232C
serial I/O interface are listed in table 2-6. An Intel
iSBC 955 Cable Set is recommended for RS232C
interfacing. One cable assembly consists of a
25-conductor flat cable with a 26-pin PC connector
at one end and an RS232C interface connector at the
other end. The second cable assembly includes an
RS232C connector at one end and has spade lugs at
2-26
Table 2-16. Parallel 1/0 Connector J1
Pin Assignmefits
Pin 1 ,2
Function
Pin 1 ,2
Function
1
3
5
7
9
11
13
15
Ground
2
4
6
8
10
12
14
16
Port CA bit 7
Port CA bit 6
Port CA bit 5
Port CA bit 4
Port CA bit 3
Port CA bit 2
Port CA bit 1
Port CA bit 0
17
19
21
23
25
27
29
31
Ground
18
20
22
24
26
28
30
32
Port CC bit 3
Port CC bit 2
Port CC bit 1
Port CC bit 0
Port CC bit 4
Port CC bit 5
Port CC bit 6
Port CC bit 7
33
35
37
39
41
43
45
47
Ground
34
36
38
40
42
Port C8 bit 7
Port C8 bit 6
Port C8 bit 5
Port C8 bit 4
Port C8 bit 3
Port C8 bit 2
Port C8 bit 1
Port C8 bit 0
"
Ground
,
"
Ground
,
44
'W
Ground
46
48
49
Ground
EXT INTRO/
50
1. All odd-numbered pins 1, 3, 5, ... 49) are on component
side of board. Pin 1 is lhe right-most pin when viewed
from the component side of the board with the extractors at the top.
2. Cable connector numbering convention may not agree
with board connector numbering convention.
iSBC 86/12A
Preparation for Use
Table 2-17. Parallel I/O Signal (Connector J1) DC Characteristics
Signals
Parameter
Description
Symbol
Port C8
Bidirectional
Drivers
8255A
Driver/Receiver
EXT INTRO/
VOL
VOH
VIL
VIH
IlL
*CL
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
Input Current at Low V
Capacitive Load
VOL
VOH
VIL
VIH
IlL
IIH
*CL
Output Low Voltage
Output High Voltage
Input Low Voltage
Input High Voltage
Input Current at Low V
Input Current at High V
Capacitive Load
VIL
VIH
IlL
IIH
*CL
Input Low Voltage
Input High Voltage
Input Current at Low V
Input Current at High V
Capacitive Load
Test
Conditions
iOL = 20 rnA
IOH = -12 rnA
Min.
Max.
0.45
2.4
0.95
2.0
-5.25
18
VIN = 0.45V
IOL = 1.7 rnA
IOH = -200/LA
0.45
2.4
0.8
2.0
10
10
18
VIN = 0.45
VIN = 5.0
0.8
2.0
-1.0
-0.8
30
VIN = O.4V
VIN = 2.4V
Units
V
V
V
V
rnA
pF
V
V
V
V
/LA
/LA
pF
V
V
rnA
rnA
pF
*Capacitive load values are approximations.
the other end; the spade lugs are used to interface to a
teletypewriter. (See Appendix A for ASR33 TTY
interface instructions.)
For OEM applications where cables will be made for
the iSBC 86/12A board, it is important to note that
the mating connector for J2 has 26 pins whereas the
RS232C connector has 25 pins. Consequently, when
connecting the 26-pin mating connector to 25-conductor flat cable, be sure that the cable makes contact
with pins 1 and 2 of the mating connector and not
with pin 26. Table 2-18 provides pin correspondence
Table 2-18. Connector J2 Vs RS232C
Pin Correspondence
PC Conn.
J2
RS232C
Conn.
PC Conn.
J2
RS232C
Conn.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
15
2
16
3
17
4
18
5
19
6
20
14
15
16
17
18
19
20
21
22
23
24
25
26
7
21
8
22
9
23
10
24
11
25
12
N/C
13
II
between connector J2 and an RS232C connector.
When attaching the cable to J2, be sure that the PC
connector is oriented properly with respect to pin Ion
the edge connector. (Refer to the footnotes in table
2-6.)
2-28. BOARD INSTALLATION
Always turn off the computer system power
supply before installing or removing the
iSBC 86/12A board and before installing or
removing device interface cables. Failure to
take these precautions can result in damage
to the board.
NOTE
Inspect the modular backplane and cardcage and ensure that pull-up resistors have
been included for pins 27, 28, 30, 32, 33, and
34. Earlier backplanes did not include pullups on these pins.
In an iSBC 80 Single Board Computer based system,
install the iSBC 86/12A board in any slot that has not
been wired for a dedicated function. In an Intellec
2-27
Preparation for Use
Microcomputer Development System, install the
iSBC 86/12A board in any odd-numbered slot except
slot 1 or any slot of an Intellec Series II Microcomputer Development System. If another module in the
Intellec System is to supply the BCLK/ and CCLK/
2-28
iSBC 86/12A
signals, disconnect EI05-EI06 and EI03-EI04
jumpers on the iSBC 86/12A board. Make sure that
auxiliary connector P2 (if used) mates with the userinstalled mating connector. Attach the appropriate
cable assemblies to connectors Jl and J2.
CHAPTER 3
PROGRAMMING INFORMATION
3-1. INTRODUCTION
This chapter lists the dual port RAM, ROM/EPROM,
and I/O address assignments, describes the effects of
a hardware initialization (power-up and reset), and
provides programming information for the following
programmable chips:
a. Intel 8251A USART (Universal Synchronous/
Asynchronous Receiver/Transmitter) that
controls the serial I/O port.
b. Intel 8253 PIT (Programmable Interval Timer)
that controls various frequency and timing
functions.
c. Intel 8255A PPI (Programmable Peripheral
Interface) that controls the three parallel I/O
ports.
d. Intel 8259A PIC (Programmable Interrupt
Controller) that can handle up to 64 vectored
priority interrupts for the on-board microprocessor.
This chapter also discusses the Intel 8086 Microprocessor (CPU) interrupt capability. A complete
description of programming with Intel's assembly
language is given in the 8086 Assembly Language
Reference Manual, Manual Order No. 9800640.
3-2. FAILSAFE TIMER
The 8086 CPU expects an acknowledge signal to be
returned from the addressed I/O or memory device in
response to each Read or Write Command. TheiSBC
86/12A board includes a Failsafe Timer that is
triggered during T1 of every machine cycle. If the
Failsafe Timer is enabled by hardwire jumper as
described in table 2-4, and no acknowledge signal is
received within approximately 6 milliseconds after
the command is issued, the Failsafe Timer will time
out and allow the CPU to exit the wait state. As
described in Chapter 2, provision is made so that the
Failsafe Timer output (TIME OUT INTR/) can
optionally be used to interrupt the CPU.
NOTE
The 8259A must be used in the edge triggered
mode with TIME OUT INTR/.
If the Failsafe Timer is not enabled by hardwire
jumper and an acknowledge signal is not returned for
any reason, the CPU will hang up in a wait state. In
this situation, the only way to free the CPU is to
initialize the system as described in paragraph 3-7.
3-3. MEMORY ADDRESSING
The iSBC 86/12A board includes 32K bytes of
dynamic random access memory (RAM) and four IC
sockets to accommodate up to 16K bytes of userinstalled read-only memory (ROM or EPROM). The
iSBC 86/12A board features a dual port RAM access
arrangement in which the on-board RAM can be
accessed by the on-board 8086 microprocessor (CPU)
or by another bus master via the Multibus interface.
The ROM/EPROM can be accessed only by the CPU.
The dual port RAM can be accessed by another bus
master that currently has control of the Multibus
interface. It should be noted that, even though
another bus master may be contin ually accessing the
dual port RAM, this does not prevent the CPU from
also accessing the dual port RAM. When this
situation occurs, memory accesses by the CPU and
controlling bus master are interleaved. Such
interleaved access will, of course, impose a longer
wait state both for the CPU and for the controlling
bus master. Dual-port RAM access by another bus
master does not interfere with the CPU while it is
accessing the on-board ROM/EPROM and I/O
devices.
To prevent the on-board CPU from gaining access to
the dual port RAM while another bus master is
accessing the dual port RAM, the following steps
must be taken.
a. The external bus master must do the following
steps when accessing dual port RAM:
assert bus override (lock the bus)
access dual port RAM
unlock bus
b. The on-board bus .master must do the following
steps when accessing dual port RAM:
assert bus override (lock the bus)
access Multibus interface (must be
unused valid memory)
access dual port RAM
unlock bus
Typical subroutines for accessing dual port RAM
while preventing the on-board CPU from accessing
RAM is shown in table 3-1.
3-1
Programming Information
iSBC 86/12A
Table 3-1. Typical Dual Port Access Subroutine
;CRITXCHG LOCKS OUT THE ON-BOARD CPU WHILE THE DUAL PORT RAM IS ACCESSED.
;SUBROUTINE ASSUMES PPI PORT A IS MODE 0 AND OVERRIDE/ IS JUMPERED TO PORT C BIT O.
;DPACK ALLOWS OFF-BOARD MUL TIMASTER TO LOCK OUT ON-BOARD CPU WHILE DUAL PORT
;RAM IS ACCESSED.
;OFF-BOARD PROCESSOR
PUBLIC
EXTRN
CRITXCHG LOCK
CRITXCHG
DUAL-PORT-SEMA4
XCHG DUAL-PORT-SEMA4,AH
;DUAL PORT (ON-BOARD) PROCESSOR
DPACK
PUBLIC
EXTRN
DPACK
ANY-OFFBOARD-ACCESS
MOV
OUT
MOV
AL,OOH
OCEH,AL
AL,ANY-OFFBOARD-ACCESS
XCHG
MOV
OUT
DUAL-PORT-SEMA4,AH
AL,01H
OCEH,AL
3-4. CPU ACCESS
Addresses for CPU access of ROM/EPROM and onboard RAM are provided in table 3-2. Note that the
ROM/EPROM addresses are assigned from the top
down of the I-megabyte address space with the
bottom address being determined by the user
ROM/EPROM configuration. The on-board RAM
addresses are assigned from the bottom up of the
I-megabyte address space.
When the CPU is addressing on-board memory
(RAM, ROM, or EPROM), an internal acknowledge
signal is automatically generated and imposes one
wait state for each CPU operation. When the CPU is
addressing system memory via the Multibus interface, the CPU must first gain control of the Multibus
interface and, after the Memory Read or Memory
Write Command is given, must wait for the Transfer
Acknowledge (XACK/) to be received from the
addressed memory device. The Failsafe Timer, if
enabled, will prevent a CPU hang-up in the event of a
memory device equipment failure or a bus failure.
It should be noted in table 3-2 that it is possible to
configure ROM/EPROM such as to create illegal
addresses. If an illegal address is used in conjunction
with a Memory Write Command to ROM/EPROM,
an internal acknowledge signal is generated as
3-2
;RESETS BIT 0 OF PORT C
;IF OFFBOARD PROCESSOR
;HAS LOCKED BUS, WILL
;WAIT HERE UNTIL BUS
;AVAILABLE.
;SETS BIT 0 OF PORT C
though the address was legal and the CPU will
continue executing the program. However, in this
case, erroneous data will be returned.
3-5. MULTIBUS INTERFACE ACCESS
As described in paragraph 2-13, the iSBC 86/I2A
board can be configured to permit Multibus interface
access of 8K, 16K, 24K, or 32K bytes of on-board
RAM. The Multibus interface allows both 8-bit and
I6-bit masters to reside in the same system. To
accomplish this, the memory is divided into two 8-bit
data banks to form one I6-bit word. The banks are
organized such that all even bytes are in one bank
(DATO-DAT7) and all odd bytes are in the other bank
(DAT8-DATF).
The Byte High Enable (BHEN /) signal controls the
odd data byte and, when active, enables the high odd
byte (DAT8/-DATF /) onto the Multibus interface.
Address bit ADRO/ controls the even data byte and,
when active, enables the low byte (DATO/-DAT7/)
onto the Multibus interface. For maximum efficiency, I6-bit word operations must occur on an even
byte boundary with BHEN / active. Address bit
ADRO/ is active for all even byte addresses. Odd
byte addressing requires two operations to form a
I6-bit word.
iSBC 86/12A
Programming Information
Table 3-2. On-Board Memory Addresses (CPU Access)
Type
EPROM
ROM
RAM
iSBC 300
Multimodule RAM
iSBC 340
Multimodule PROM
Configuration
Legal Addresses
Illegal Addresses
Two 2758 chips
FF800-FFFFF
Four 2758 chips
FFOOO-FFFFF
FFOOO-FF7FF
-
Two 2716 chips
Four 2716 chips
FFOOO-FFFFF
FEOOO-FFFFF
FEOOO-FEFFF
-
Two 2732 chips
Four 2732 chips
FEOOO-FFFFF
FCOOO-FFFFF
FCOOO-FDFFF
-
Two 2316E chips
Four 2316E chips
FFOOO-FFFFF
FEOOO-FFFFF
FEOOO-FEFFF
-
Two 2332A chips
Four 2332A chips
FEOOO-FFFFF
FCOOO-FFFFF
FCOOO-FDFFF
-
Sixteen 2117 chips
0000-07FFF
-
Thirty two 2117 chips
OOOOO-OFFFF
-
Eight 2732 or 2332 chips
F8000-FFFFF
-
Byte operations can occur in two ways. The even
byte can be accessed by controlling ADROI, which
places the data on the DATOI-DAT7 I lines. (See
figure 3-IA.) To access the odd data bank, which
normally is placed on theDAT8/-DATF/lines, anew
data path is defined. The inactive state of ADROI
and BHEN I enable a swap byte buffer that places
the odd data bank on DATOI-DAT7 I. (See figure
3-IB.) This permits an 8-bit bus master to access
both bytes of a data word by controlling only ADROI.
Figure 3-IC illustrates how a 16-bit bus master
obtains a I6-bit word by a single address on an even
byte boundary. Figure 3-IA illustrates how a 16-bit
bus master may selectively address an even (low)
data byte.
REF
MEMORY DATA PATHS
BHEN/ ADRO/
USED
:uYs
MASTERS
DATO/-DAT7/
S-BIT,
16-BIT,
OR
MIXED
A
DATS/-DATF/
DATO/-DAT7/
B
S-BIT
DATS/-DATF/
3-6. 1/0 ADDRESSING
The CPU communicates with the on-board programmable chips through a sequence ofllO Read and 1/0
Write Commands. As shown in table 3-3, each of
these chips recognizes four separate hexadecimal 1/0
addresses that are used to control the various
programmable functions. (The 1/0 address decoder
operates on the lower 16 bits and all addresses must
be on an even byte boundary.) Where two hexadecimal addresses are listed for a single function, either
address may be used. For example, an 1/0 Read
Command to port OODA or OODE will read the status
of the 825lA USART.
DATO/-DAT7/
C
16-BIT
DATS/-DATF/
Figure 3-1. Dual Port RAM Addressing
(Multibus™ Interface Access)
3-3
iSBC 86/12A
Programming Information
3-7. SYSTEM INITIALIZATION
When power is initially applied to the system, a reset
signal is automatically generated that performs the
following:
a. The 8086 CPU internal registers are set as
follows:
PSW
= 0000
IP
= 0000
DS
= 0000
ES
= 0000
Code Segment Register = FFFF
This effectively causes a long JMP to FFFFO.
b. The 8251A USART serial I/O port is set to the
"idle" mode, waiting for a set of Command Words
to program the desired function.
c. The 8255A PPI parallel I/O ports are set to the
input mode.
The 8253 PIT and the 8259A PIC are not affected by
the power-up sequence.
The reset signal is also gated onto the Multibus
interface to initialize the remainder of the system
components to a known internal state.
The reset signal can also be generated by an auxiliary
Table 3-3. 1/0 Address Assignments
I/O
Address*
OOCO
or
00C4
00C2
Chip
Select
Function
Write: ICW1, OCW2, and OCW3
Read: Status and Poll
8259A
PIC
or
Write: ICW2, ICW3, ICW4, OCW1 (Mask)
Read: OCW1 (Mask)
00C6
Write: Port A (J1)
Read: Port A (J1)
00C8
OOCA
8255A
PPI
OOCC
Write: Port C (J 1)
Read: Port C (J1) or Status
OOCE
Write: Control
Read: None
0000
Write: Counter 0 (Load Count -;- N)
Read: Counter 0
0002
0004
8253
PIT
Write: Counter 1 (Load Count -;- N)
Read: Counter 1
Write: Counter 2 (Load Count -;- N)
Read: Counter 2
0006
Write: Control
Read: None
0008
or
OODC
Write: Data (J2)
Read: Data (J2)
OODA
8251A
USART
or
OODE
*Old addresses (Le., 00C1, 00C3, ... 0000) are illegal.
3-4
Write: Port B (J1)
Read: Port B (J1)
Write: Mode or Command
Read: Status
iSBC 86/12A
Programming Information
RESET switch. Pressing and releasing the RESET
switch produces the same effect as the power-up reset
described above.
3-8. 8251A USART PROGRAMMING
Iscs i I I I
ESD
EP
PFN
L21
I I I
L1
0
0
CHARACTER LENGTH
I
The USART converts parallel output data into
virtually any serial output data format (including
IBM Bi-Sync) for half- or full-duplex operation. The
USART also converts serial input data into parallel
data format.
0
1
0
1
0
0
1
1
5
6
BITS
BITS
7
BITS
BITS
8.
PARITY ENABLE
(1
ENABLE I
(0 - DISABLE I
Prior to starting transmitting or receiving data, the
USART must be loaded with a set of control
words. These control words, which define the
complete functional operation of the USART, must
immediately follow a reset (internal or external). The
control words are either a Mode instruction or a
Command instruction.
EVEN PARITY GENERATION/CHE CK
1 ,. EVEN
0 000
0
EXTERNAL SYNC DETECT
1 . SYNDET IS AN INPUT
0 SY"JDET IS AN OUTPUT
SINGLE CHARACTER SYNC
1 . SINGLE SYNC CHARACTER
o ' OOUBL E SYNC CHARACTE R
3-9. MODE INSTRUCTION FORMAT
The Mode instruction word defines the general characteristics of the USART and must follow a reset
operation. Once the Mode instruction word has been
written into the USART, sync characters or command instructions may be inserted. The Mode
instruction word defines the following:
a. For Sync Mode:
(1) Character length
(2) Parity enable
(3) Even/odd parity generation and check
(4) External sync detect (not supported by
the iSBC 86/[2A board)
(5) Single or double character sync
NOTE IN EXTERNAL SYNC MODE. PROGRAMMING DOUBLE CHARACTER
SYNC WILL AFFECT ONL Y THE Tx.
Figure 3-2. USART Synchronous Mode
Instruction Word Format
CPU BYTES (58 BITS/CHARI
DATA
b. For Async Mode:
(1) Baud rate factor (Xl, XI6, or X64)
(2) Character length
(3) Parity enable
(4) Even/odd parity generation and check
(5) Number of stop bits
CH:~RACHRS
ASSEMBLED SERIAL DATA OUTPUT ITxDI
SYNC
CHAR 1
SYNC
CHAR 2
DATA CHARACTERS
RECEIVE FORMAT
SERIAL DATA INPUT IRxDI
Instruction word and data transmission formats for
synchronous and asynchronous modes are shown in
figures 3-2 through 3-5.
SYNC
CHAR 1
SYNC
CHAR ~
I
DATA
CHA:R~~C_TE_R_S_---J
CPU BYTES 15 8 BITS/CHARI
3-10. SYNC CHARACTERS
Sync characters are written to the USART in the
synchronous mode only. The USART can be programmed for either one or two sync characters; the
format of the sync characters is at the option of the
programmer.
Figure 3-3. USART Synchronous Mode
Transmission Format
3-5
iSBC 86/12A
Programming Information
0001-----0.
TRANSMITTER OUTPUT
I
S2\ S1 I EP IpEN/ L21 L1 I B21 B,
GENERATED
BY8251A
I
I
STtI
L
Brrs L
BAUD RATE FACTOR
0
1
0
1
0
0
1
1
SYNC
MODE
11X)
116X)
164X)
DOES NOT APPEAR
OOD1---- D.ON THEDATABUS
RECEIVER INPUT
RXD
1 . . _S_TBA_I~_T--'-
0
1
0
1
1
5
6
BITS
BITS
7
BITS
8
BITS
Brrs L
CPU BYTE 15-8 BITS/CHAR)
DATA
EVEN PARITY GENERATION/CHE CK
1 ' EVEN
0=000
C~~RACTER
ASSEMBLED SERIAL DATA OUTPUT ITxD)
NUMBER OF STOP BITS
0
1
0
1
0
0
1
1
1
lY..
BITS
2
BITS
BIT
ST6;I
__
DA_T-iA: B\-IT_S_"",--_ _....I
TRANSMISSION FORMAT
PARITY ENABLE
1 ENABLE
0= DISABLE
INVALID
t
PROGRAMMED
CHARACTER
LENGTH
l
0
t
----
CHARACTER LENGTH
0
tt
DATA CHARACTER
STOD
BITS
~---""'----~~
RECEIVE FORMAT
(ONLY EFFECTS TX; RX NEVER
REQUIRES MORE THAN ONE
STOP BIT)
SERIAL DATA INPUT IRxD)
DATA CHARACTER
STO~
~_~_ _ _ _-i~_ _~_ _~_B~IT~
CPU BYTE (58 BITS/CHARI·
Figure 3-4. USART Asynchronous Mode
Instruction Word Format
DATA
CH~~ACTER
·NOTE IF CHARACTER LENGTH IS DEFINED AS 5 6 OR 7
BITS THE UNUSED BITS ARE SET TO "ZERO"
Figure 3-5. USART Asynchronous Mode
Transmission Format
3-11. COMMAND INSTRUCTION FORMAT
The Command instruction word shown in figure 3-6
controls the operation of the addressed USART. A
Command instruction must follow the mode and/or
sync words. Once the Command instruction is
written, data can be transmitted. or received. by the
USART.
It is not necessary for a Command instruction to
precede all data transactions; only those transmissions that require a change in the Command
instruction. An example is a change in the enable
transmit or enable receive bus. Command instructions can be written to the USART at any time after
one or more data operations.
After initialization, always read the chip status and
check for the TXRDY bit prior to writing either data
or command words to the USART. This ensures that
any prior input is not overwritten and lost. Note that
issuing a Command instruction with bit 6 (IR) set will
return the USART to the Mode instruction format.
3-6
3-12. RESET
To change the Mode instruction word, the USART
must receive a Reset command. The next word
written to the USART after a Reset command is
assumed to be a Mode instruction. Similarly, for sync
mode, the next word after a Mode instruction is
assumed to be one or more sync characters. All
control words written into the USART after the Mode
instruction (and/or the sync character) are assumed.
to be Command instructions.
3-13. ADDRESSING
The USART chip uses Port OOD8 or OODC to read and
write I/O data; Port OODA or OODE is used to write
mode and command words and read the USART
status. (Refer to table 3-3.)
Programming Information
iSBC 86/12A
r
EH
1 IR
I I I
RTS
ER
SBRK
1RXE I DTR ITXEN
LI
;RANSMn ENABLE
1
=
a=
'------
enable
disable
I
DATA TERMINAL
READY
"high" will force DTR
output to zero
ADDRESS
RESET
OOODA
MODE INSTRUCTION
OOODA
SYNC CHARACTER 1
OOODA
SYNC CHARACTER 2
OOODA
COMMAND INSTRUCTION
000D8
RECEIVE ENABLE
1 = enable
a disable
0
SEND BREAK
CHARACTER
1 = forces TXD "low"
a = normal operation
OOODA
000D8
OOODA
ERROR RESET
1 = reset error flags
PE, OE, FE
I
I
REOUEST TO SEND
"high" Will force RTS
output to zero
I
INTERNAL RESET
L - - - - - - - - - - - - J "high" returns 8251A to
Mode Instruction Format
~;;.
}
SYNC MODE
ONLY*
.'"'
DATA 1/0
COMMAND INSTRUCTION
:~
1/0 DATA
=~
COMMAND INSTRUCTION
*The second sync character is skipped if Mode instruction has
programmed USART to single character internal sync mode.
Both sync characters are skipped if Mode instruction has
programmed USART to async mode.
Figure 3-7. Typical USART Initialization
and 1/0 Data Sequence
ENTER HUNT MODE'
1 = enable search for Sync
Characters
, (HAS NO EFFECT
IN ASYNC M'ODEI
Note:
Error Reset must be performed whenever RXEnable
and Enter Hunt are programmed.
Figure 3-6. USART Command
Instruction Word Format
3-14. INITIALIZATION
A typical USART initialization and 1/0 data
sequence is presented in figure 3-7. The USART chip
is initialized in four steps:
To avoid spurious interrupts during USART initialization, disable the USART interrupt. This can be
done by either masking the appropriate interrupt
request input at the 8259A PIC or by disabling the
8086 microprocessor interrupts by executing a CLI
instruction.
First, reset the USART chip by writing a Command
instruction to Port OODA (or OODE). The Command
instruction must have bit 6 set (IR =1); all other bits
are immaterial.
NOTE
a. Reset USART to Mode instruction format.
b. Write Mode instruction word. One function of
mode word is to specify synchronous or asynchronous operation.
c. If synchronous mode is selected, write one or two
sync characters as required.
d. Write Command instruction word.
This reset procedure should be used only if
the USART has been completely initialized,
or the initialization procedure has reached
the point that the USART is ready to receive
a Command word. For example, if the reset
command is written when the initialization
sequence calls for a sync character, then
subsequent programming will be in error.
3-7
Programming Information
iSBC 86/12A
Next write a Mode instruction word to the USART.
(See figures 3-2 through 3-5.) A typical subroutine
for writing both Mode and Command instructions is
given in table 3-4.
If the USART is programmed for the synchronous
mode, write one or two sync characters depending on
the transmission format.
Finally, write a Command instruction word to the
USART. Refer to figure 3-6 and table 3-4.
IMPORTANT: During initialization, the 8251A
USART requires a minimum recovery time of 6.5
microseconds (16 USART clock cycles) between backto-back writes in order to set up its internal
registers. This recovery time can be satisfied by the
CPU performing several dummy instructions between the back-to-back writes to the 8251A USART to
create a minimum delay of 6.5 microseconds. The
following example will create a delay of approximately 7.2 microseconds.
MOV
OUT
MOV
TAG: LOOP
MOV
OUT
AL,04EH
ODAH,AL
CX,3
TAG
AL,037H
ODAH,AL
;USART MODE WORD
;FIRST USART WRITE
;DELAY
;DELAY
;USART COMMAND WORD
;SECOND USART WRITE
NOTE
After the USART has been initialized,
always check the status of the TXRDY bit
prior to writing data or writing a new
command word to the USART. The TXRDY
bit must be true to prevent overwriting and
subsequent loss of command or data words.
The TXRDY bit is inactive until initialization has been completed; do not check
TXRDY until after the command word,
which concludes the initialization procedure,
has been written.
Prior to any operating change, a new command word
must be written with command bits changed as
appropriate. (Refer to figure 3-6 and table 3-4.)
3-16. DATA INPUT/OUTPUT. For data receive
or transmit operations, perform a read or write,
respectively, to the USART. Table 3-5 and 3-6
provide examples of typical character read and write
subroutines.
3-15. OPERATION
During a normal transmit operation, the USART
generates a Transmit Ready (TXRDY) signal that
indicates that the USART is ready to accept a data
character for transmission. TXRDY is automatically
reset when the CPU loads a character into the
USART.
Normal operating procedures use data I/O read and
write, status read, and Command instruction write
operations. Programming and addressing procedures for the above are summarized in following
paragraphs.
Similarly, during a normal receive operation, the
USART generates a Receive Ready (RXRDY) signal
that indicates that a character has been received and
is ready for input to the CPU. RXRDY is automatically reset when a character is read by the CPU.
This precaution applies only to the USARTinitialization and does not apply otherwise.
Table 3-4. Typical USART Mode or Command Instruction Subroutine
;CMD 2 OUTPUTS CONTROL WORD TO USART FROM AL REGISTER.
;USES-AL, STATO; DESTROYS-NOTHING.
CMD2:
LP:
511NT:
PUBLIC
EXTRN
CMD2,511NT
STATO
PUSH
PUSH
CALL
AND
JZ
POPF
POP
OUT
RET
AX
END
3-8
F
STATO
AL,1
LP
;CHECK TXRDY
;TXRDY MUST BE TRUE
AX
ODAH,AL
;ENTER HERE FOR INITIALIZATION
Programming Information
iSBC 86/12A
Table 3-5. Typical USART Data Character Read Subroutine
;RX1 READS DATA CHARACTER FROM USART INTO REG AL.
;USES-STATO; DESTROYS-AL, FLAGS.
RX1:
RXA1:
PUBLIC
EXTRN
RX1,RXA1
STATO
CALL
AND
JZ
IN
RET
STATO
AL,2
RX1
AL,OD8H
;CHECK FOR RXRDY TRUE
;ENTER HERE IF RXRDY IS TRUE
END
Table 3-6. Typical USART Data Character Write Subroutine
;TX1 WRITES DATA CHARACTER FROM REG AL TO USART.
;USES-AL, STATO; DESTROYS-FLAGS.
TX1:
TX11 :
TXA1:
PUBLIC
EXTRN
TX1,TXA1
STATO
PUSH
CALL
AND
JZ
POP
OUT
RET
AX
STATO
AL,1
TX11
AX
OD8H,AL
;CHECK FOR TXRDY TRUE
;ENTER HERE IF TXRDY IS TRUE
END
The TXRDY and RXRDYoutputs of the USART are
available at the priority interrupt jumper matrix. If,
for instance, TXRDY and RXRDY are input to the
8259A PIC, the PIC resolves the priority and
interrupts the CPU. TXRDY and RXRDY are also
available in the status word. (Refer to paragraph
3-17.)
3-17. STATUS READ. The CPU can determine
the status of a serial 1/0 port by issuing an 1/0 Read
Command to the upper port (OODA or OODE) of the
USART chip. The format of the status word is shown
in figure 3-8. A typical status read subroutine is
given in table 3-7.
3-18. 8253 PIT PROGRAMMING
A 22.1184-MHz crystal oscillator supplies the basic
clock frequency for the programmable chips. This
clock frequency is divided by 9, 18, and 144 to produce
three jumper-selectable clocks: 2.46 MHz, 1.23 MHz,
and 153.6 kHz. These clocks are available for input to
Counter 0, Counter 1, and Counter 2 of the 8253
PIT. The default (factory connected) and optional
jumpers for selecting the clock inputs to the three
counters are listed in table 2-4.
Default jumpers connect the output of Counter 2 to
the TXC and RXC inputs of the 8251A USART.
Jumpers are included so that Counters 0 and 1 can
provide real-time interrupts to the 8259A PIC.
Before programming the 8253 PIT, ascertain the
input clock frequency and the output function of each
of the three counters. These factors are determined
and established by the user during installation.
3-19. MODE CONTROL WORD
AND COUNT
All three counters must be initialized prior to their
use. The initialization for each counter consists of
two steps:
3-9
Programming Information
I
DSR
I
SYNDET
I
iSBC 86/12A
I
FE
OE
I
PE
I
TXE
I
RXRDY
I
I
TXRDY
I
~
Y
OVERRUN ERROR
The OE flag is set when the CPU does
not read a character before the next
one becomes available. It is reset by
the ER bit of the Command instruction.
OE does not inhibit operation of the
8251; however, the previously overrun
character is lost.
TRANSMlill ••EADY
Indicates USART is ready to accept a
data character or command.
'----
FRAMING ERROR (ASYNC ONLY)
FE flag is set when a valid stop bit is not
detected at end of every character. It is
is reset by ER bit of Command instruction. FE does not inhibit operaton of
8251.
RECEIVER READY
Indicates USART has received a character on its serial input and is ready
to transfer it to the CPU.
TRANSMITTER EMPTY
Indicates that parallel to serial converter in transmitter is empty.
PARITY ERROR
PE flag is set when a parity error is
detected. It is reset by ER bit of Command instruction. PE does not inhibit
operation of 8251.
SYNC DETECT
When set for internal sync detect, indicates that character sync has been
achieved and 8251 is ready for data.
DATA SET READY
DSR is general purpose. Nonnally
used to test modem conditions such as
Data Set Ready.
Figure 3-8. USART Status Read Format
a. A mode control word (figure 3-9) is written to the
control register for each individual counter.
b. A down-count number is loaded into each
counter; the down-count number is in one or two
8-bit bytes as determined by the mode control
word.
The mode control word (figure 3-9) does the
following:
c. Selects one of the following four counter
read/load functions:
(1)
(2)
(3)
(4)
Counter latch (for stable read operation).
Read or load most-significant byte only.
Read or load least-significant byte only.
Read or load least-signigicant byte first,
then most-significant byte.
d. Sets counter for either binary or BCD count.
The mode control word and the count register bytes
for any given counter must be entered in the
following sequence:
a. Selects counter to be loaded.
b. Selects counter operating mode.
Table 3-7. Typical USART Status Read Subroutine
;STATO READS STATUS FROM USART.
;DESTROYS-AL.
STATO:
PUBLIC
STATO
IN
RET
AL,ODEH
END
3-10
;GET STATUS
Programming Information
iSBC 86/12A
07
06
05
04
03
02
01
DO
ISC11 scal RL11 RLa I M21 M1 I Ma IBCDI
II
,L
II
(BINARY/BCD)
0
Binary Counter (16-bits)
1
Binary Coded Decimal (BCD) Counter
(4 Decades)
M2
M1
MO
0
0
0
0
0
1
1
1
0
0
0
1
0
1
X
X
1
1
(MODE)
Mode
Mode
Mode
Mode
Mode
Mode
0
1
2
3 .....- Use Mode 3 for
4
Baud Rate Generator
5
RL1
RLO
(READ/LOAD)
0
0
Counter Latching operation (reter
to paragraph 3-19).
1
0
Read/Load most significant byte only.
0
1
Read/Load least significant byte only.
1
1
Read/Load least significant byte first,
then most significant byte.
SC1
SCO
(SELECT COUNTER)
0
0
Select Counter 0
0
1
Select Counter 1
1
0
Select Counter 2
1
1
Illegal
Figure 3-9. PIT Mode Control Word Format
a. Mode control word.
b. Least-significant count register byte.
c. Most-significant count register byte.
As long as the above procedure is followed for each
counter, the chip can be programmed in any
convenient sequence. For example, mode control
words can be ioaded first into each of three counters
per chip, followed by the least-significant byte, mostsignificant byte, etc. Figure 3-10 shows the two
programming sequences described above.
Since all counters in the PIT chip are downcounters,
the value loaded in the count registers is decremented. Loading all zeroes into a count register
results in a maximum countof216 for binary numbers
or 10 4 for BCD numbers.
When a selected count register is to be loaded, it must
be loaded with the number of bytes programmed in
the mode control word. One or two bytes can be
ioaded, depending on the appropriate down count.
These two bytes can be programmed at any time
following the mode control word, as long as the
correct number of bytes is loaded in order.
3-11
Programming Information
iSBC 86/12A
PROGRAMMING FORMAT
Step
Step
Mode Control Word
Counter n
1
Mode Control Word
Counter a
LSB
Count Register Byte
Counter n
2
Mode Control Word
Counter 1
MSB
Count Register Byte
Counter n
3
Mode Control Word
Counter 2
1
2
3
ALTERNATE PROGRAMMING FORMAT
4
LSB
Counter Register Byte
Counter 1
5
MSB
Count Register Byte
Counter 1
6
LSB
Count Register Byte
Counter 2
7
MSB
Count Register Byte
Counter 2
8
LSB
Count Register Byte
Counter a
9
MSB
Count Register Byte
Counter a
Figure 3-10. PIT Programming Sequence Examples
The count mode selected in the control word controls
the counter output. As shown in figure 3-9, the PIT
chip can operate in any of six modes:
a. Mode 0: Interrupt on terminal count. In this
mode, Counters 0 and 1 can be used for auxiliary
functions, such as generating real-time interrupt
intervals. After the count value is loaded into the
count register, the counter output goes low and
remains low until the terminal count is reached.
The output then goes high until either the count
register or the mode control register is reloaded.
b. Mode 1: Programmable one-shot. In this mode,
the output of Counter 0 and/or Counter 1 will go
low on the count following the rising edge of the
GATE input from Port OOCC (assuming Port
OOCC jumpers are so configured). The output will
go high on the terminal count. If a new count
value is loaded while the output is low, it will not
affect the duration of the one-shot pulse until the
succeeding trigger. The current count can be
read at any time without affecting the one-shot
pulse. The one-shot is retriggerable, hence the
output will remain low for the full count after any
rising edge of the gate input.
3-12
c. Mode 2: Rate generator. In this mode, the output
of Counter 0 and/or Counter 1 will be low for one
period of the clock input. The period from one
output pulse to the next equals the number of
input counts in the count register. If the count
register is reloaded between output pulses, the
present period will not be affected but the
subsequent period will reflect the new value. The
gate input, when low, will force the output
high. When the gate input goes high, the counter
will start from the initial count. Thus, the gate
input can be used to synchronize the counter.
When Mode 2 is set, the output will remain high
until after the count register is loaded; thus, the
count can be synchronized by software.
d. Mode 3: Square wave generator. Mode 3, which
is the primary operating mode for Counter 2, is
used for generating Baud rate clock signals. In
this mode, the counter output remains high until
one-half of the count value in the count register
has been decremented (for even numbers). The
output then goes low for the other half of the
count. If the value in the count register is odd,
the counter output is high for (N + 1)/2 counts,
and low for (N - 1)/2 counts.
Programming Information
iSBC 86/12A
e. Mode 4: Software triggered strobe. After this
mode is set, the output \\<-1.11 be high. When the
count is loaded, the counter begins counting. On
terminal count, the output will go low for one
input clock period and then go high again. If the
count register is reloaded between output pulses,
the present count will not be affected, but the
subsequent period will reflect the new value. The
count will be inhibited while the gate input is
low. Reloading the count register will restart the
counting for the new value.
3-20. ADDRESSING
As listed in table 3-3, the PIT uses four I/O
addresses. Addresses OODO, and OOD2, and OOD4,
respectively, are used in loading and reading the
count in Counters 0, 1, and 2. Address OODS is used in
writing the mode control word to the desired counter.
3-21. INITIALIZATION
To initialize the PIT chip, perform the following:
f. Mode 5: Hardware triggered strobe. Counter 0
and/ or Counter 1 will start counting on the rising
edge of the gate input and the output will go low
for one clock period when the terminal count is
reached. The counter is retriggerable. The
output will not go low until the full count after the
rising edge of the gate input.
a. Write a mode control word for Counter 0 to
OOD6. Note that all mode control words are
written to OOD6, since the mode control word
must specify which counter is being programmed. (Refer to figure 3-9.) Table 3-9 provides a
sample subroutine for writing mode control
words to all three counters.
Table 3-8 provides a summary of the counter
operation versus the gate inputs. The gate inputs to
Counters 0 and 1 are tied high by default jumpers;
these gates may optionally be controlled by Port
CC. The gate input to Counter 2 is not optionally
controlled.
b. Assuming the mode control word has selected a
2-byte load, load least-significant byte of count
into Counter 0 at OODO. (Count value to be loaded
is described in paragraphs 3-24 through 3-26.)
Table 3-10 provides a sample subroutine for
loading 2-byte count value.
c. Load most-signigicant byte of count into Counter
Oat OODO.
NOTE
Table 3-8. PIT Counter Operation V s Gate
Inputs
~
Status
Modes
0
1
Low
Or Going
Low
Disables
counting
-
Rising
1) Initiates
High
Enables
counting
-
counting
2) Resets output
after next clock
2
3
4
5
Initiates
counting
Enables
counting
Initiates
counting
Enables
counting
-
Enables
counting
1) Disables
counting
2) Sets output
immediately
high
Disables
counting
Initiates
counting
d. Repeat steps band c for Counters 1 and 2.
3-22. OPERATION
The following paragraphs describe operating procedures for a counter read, clock freqpency divide/
ratio selection, and interrupt timer counter selection.
1) Disables
counting
2) Sets output
immediately
high
Be sure to enter the down count in two bytes if
the counter was programmed for a two-byte
entry in the mode control word. Similarly,
enter the downcount value in BCD if the
counter was so programmed.
3-23. COUNTER READ. There are two methods
that can be used to read the contents of a particular
counter. The first method involves a simple read of
the desired counter. The only requirement with this
method is that, in order to ensure stable count
reading, the desired counter must be inhibited by
controlling its gate input. Only Counter 0 and
Counter 1 can be read using this method because the
gate input to Counter 2 is not controllable.
The second method allows the counter to be read "onthe-fly." The recommended procedure is to use a
mode control word to latch the contents of the count
3-13
Programming Information
iSBC 86/12A
Table 3-9. Typical PIT Control Word Subroutine
;INTTMR INITIALIZES COUNTERS 0,1,2.
;COUNTERS 0 AND 1 ARE INITIALIZED AS INTERRUPT TIMERS.
;COUNTER 2 IS INITIALIZED AS BAUD RATE GENERATOR.
;ALL THREE COUNTERS ARE SET UP FOR 16-BIT OPERATION.
;DESTROYS-AL.
INTIMA:
PUBLIC
INTIMR
MOV
OUT
MOV
OUT
MOV
OUT
RET
AL,30H
OD6H,AL
AL,70H
OD6H,AL
AL,B6H
OD6H,AL
;MODE CONTROL WORD FOR COUNTER 0
;MODE CONTROL WORD FOR COUNTER 1
;MODE CONTROL WORD FOR COUNTER 2
END
Table 3-10. Typical PIT Count Value Load Subroutine
;LOADO LOADS COUNTER 0 FROM CX, CH IS MSB, CL IS LSB.
;USES-D,E: DESTROYS-AL.
LOA DO:
PUBLIC
LOADO
MOV
OUT
MOV
OUT
RET
AL,C
ODOH,AL
AL,CH
ODOH,AL
;GET LSB
;GET MSB
END
register; this ensures that the count reading is
accurate and stable. The latched value of the count
can then be read.
b. Perform a read operation of desired counter; refer
to table 3-3 for counter addresses.
NOTE
NOTE
If a counter is read during the down count, it
is mandatory to complete the read procedure;
that is, if two bytes were programmed to the
counter, then two bytes must be read before
any other operations are performed with that
counter.
Be sure to read one or two bytes, whichever
was specified in the initialization mode
control word. For two bytes, read in the
order specified.
To read the count of a particular counter, proceed as
follows (a typical counter read subroutine is given in
table 3-11):
a. Write counter register latch control word (figure
3-11) to Port 00D6. Control word specifies
desired counter and selects counter latching
operation.
3-14
3-24. CLOCK FREQUENCY/DIVIDE RATIO
SELECTION. Table 2-1 lists the default and
optional timer input frequencies to Counters 0
through 2. The timer input frequencies are divided by
the counters to generate TMRO INTR OUT (Counter
0), TMRI INTR OUT (Counter 1), and the 8251A
Baud Rate Clock (Counter 2).
iSBC 86/12A
Programming Information
If the binary equivalent of count value N = 256 is
loaded into Counter 2, then the output frequency is
4800 Hz, which is the desired clock rate for synchronous mode operation. Note that counter 2 must be in
binary mode.
L
1.....-_ _ _
!
I
Loon't Care
Selects Counter Latching
Operation
Specifies Counter to be Latched
Figure 3-11. PIT Counter Register
Latch Control Word Format
3-26. Asynchronous Mode. In the asynchronous
mode, the TXC and/or RXC rates equal the Baud rate
times one of the following multipliers: Xl, X16, or
X64. Therefore, the count value is determined by:
N = C/BM
where N is the count value,
B is the desired Baud rate,
M is the Baud rate multiplier (1, 16, or 64,)
and
C is 1.23 MHz, the input clock frequency.
Thus, for a 4800 Baud rate, the required count value
(N) is:
Each counter must be programmed with a downcount number, or count valueN. When count value N
is loaded into a counter, it becomes the clock
divisor. To derive N for either synchronous or
asynchronous RS232C operation, use the procedures
described in the following paragraphs.
3-25. Synchronous Mode. In the synchronous mode,
the TXC and/or RXC rates equal the Baud rate.
Therefore, the count value is determined by:
N=
1.23 X 106
4800 x 16
If the binary equivalent of count value N = 16 is
loaded into Counter 2, then the output frequency is
4800 x 16 Hz, which is the desired clock rate for
asynchronous mode operation. Count values (N)
versus rate multiplier (M) for each Baud rate are
listed in table 3-12.
NOTE
N=C/B
where N is the count value,
B is the desired Baud rate, and
Cis 1.23 MHz, the input clock frequency.
Thus, for a 4800 Baud rate, the required count value
(N) is:
N=
=16.
1.23 x 106
4800
=256.
During initialization, be sure to load the
count value (N) into the appropriate counter
and the Baud rate multiplier (M) into the
8251A USART.
3-27. RATE GENERATOR/INTERVAL
TIMER. Table 3-13 shows the maximum and
minimum rate generator frequencies and timer
intervals for Counters 0 and 1 when these counters,
Table 3-11. Typical PIT Counter Read Subroutine
;READ1 READS COUNTER 1 ON-THE-FLY INTO CX. MSB IN CH, LSB IN CL.
;DESTROYS-AL,CX.
READ1:
PUBLIC
READ1
MOV
OUT
IN
MOV
IN
MOV
RET
AL,40H
OD6H,AL
AL,OD2H
CL,A
AL,OD2H
CH,AL
;MODE WORD FOR LATCHING COUNTER 1 VALUE
:LSB OF COUNTER
;MSB OF COUNTER
END
3-15
Programming Information
iSBC 86/12A
Table 3-12. PIT Count Value Vs Rate
Multiplier for Each Baud Rate
Baud Rate:
(B)
75
110
150
300
600
1200
2400
4800
9600
19200
38400
76800
Table 3-14 shows the count value (N) required for
several time intervals (T) that can be generated for
Counters 0 and 1.
*Count Value (N) For
M
=1
16384
11171
8192
4096
2048
1024
512
256
128
64
32
16
M
= 16
M
1024
698
512
256
128
64
32
16
8
4
2
= 64
Table 3-14. PIT Time Intervals Vs Timer
Counts
256
175
128
64
32
16
8
4
T
N*
10 f,J-sec
100 f,J-sec
12
123
1229
12288
61440
1 msec
10 msec
50 msec
*Count Values (N) assume clock is 1.23
MHz. Count Values (N) are in decimal.
*Count Values (N) assume clock is 1.23 MHz. Double
Count Values (N) for 2.46 MHz clo(:k. Count Values (N)
and Rate Multipliers (M) are in decimal.
3-29. 8255A PPI PROGRAMMING
respectively, have 1.23-MHz and 153.6-kHz clock
inputs. The table also provides the maximum and
minimum generator frequencies and time intervals
that may be obtained by connecting Counters 0 and 1
in series.
3-28. INTERRUPT TIMER. To program an
interval timer for an interruption terminal count,
program the appropriate timer for the correct
operating mode (Mode 0) in the control word. Then
load the count value (N), which is derived by:
The three parallel I/O ports interfaced to connector
Jl are controlled by an Intel 8255A Programmable
Peripheral Interface chip. Port A includes bidirectional data buffers and Ports Band C include IC
sockets for installation of either input terminators or
output drivers depending on the user's application.
N=TC
Default jumpers set the Port A bidirectional data
buffers to the output mode. Optional jumpers allow
the bidirectional data buffers to be set to the input
mode or allow anyone of the eight Port C bits to
selectively set the Port A bidirectional data buffers to
the input or output mode.
N is the count value for Counter 1,
T is the desired interrupt time interval in
seconds, and
C is the internal clock frequency (Hz).
Table 2-7 lists the various operating modes for the
three PPI parallel I/O ports. Note that Port A (OOC8)
can be operated in Modes 0, 1, or 2; Port B (OOCA) can
be operated in Mode 0 or 1; Port C (OOCC) can be
operated in Mode o.
where
Table 3-13. PIT Rate Generator Frequencies and Timer Intervals
Dual Timerl (0 and 1 in Series)
Single Timer1 (Counter 0)
Single Timer2 (Counter 1)
Minimum
Maximum
Minimum
Maximum
Minimum
Maximum
Rate Generator (frequency)
18.75 Hz
614.4 kHz
2.344 Hz
76.8 kHz
0.00029 Hz
307.2 kHz
Real-Time Interrupt (interval)
1.63 f,J-sec
53.3 msec
13 f,J-sec
426.67 msec
3.26 f,J-sec
58.25 minutes
NOTES:
1. Assuming a 1.23-MHz clock input.
2. Assuming a 153.6-kHz clock input.
3. Assuming Counter a has 1.23-MHz clock input.
3-16
iSBC 86/12A
Programming Information
3-30. CONTROL WORD FORMAT
The control word format shown in figure 3-12 is used
to initialize the PPI to define the operating mode of
the three ports. Note that the ports are separated into
two groups. Group A (control word bits 3 through 6)
defines the operating mode for Port A (OOC8) and the
upper four bits of Port C (OOCC). Group B (control
word bits 0 through 2) defines the operating mode for
Port B (OOCA) and the lower four bits of Port C
(OOCC). Bit 7 of the control word controls the mode
set flag.
through OOCE) for data transfer, obtaining the status
of Port C (OOCC), and for port control. (Refer to table
3-3.)
3-32. INITIALIZATION
To initialize the PPI, write a control word to port
OOCE. Refer to figure 3-12 and table 3-15 and assume
that the control word is 92 (hexadecimal). This
initializes the PPI as follows:
a. Mode Set Flag active
b. Port A (OOC8) set to Mode 0 Input
3-31. ADDRESSING
c. Port C (OOCC) upper set to Mode 0 Output
The PPI uses four consecutive even addresses (OOC8
d. Port B (OOCA) set to Mode 0 Input
e. Port C (OOCC) lower set to Mode 0 Output
CONTROL WORD
3-33. OPERATION
I I I I I I I I I
D,
D,
D,
D,
D,
D,
D,
D,
After the PPI has been initialized, the operation is
completed by simply performing a read or a write to
the appropriate port.
I I I I I I I I
-r--'
/
GROUPB
\
PORT C (LOWER)
1 = INPUT
0= OUTPUT
~
L
3-34. READ OPERATION. A typical read subroutine for Port A is given in table 3-16.
3-35. WRITE OPERATION. A typical write
subroutine for Port C is given in table 3-17. As shown
in figure 3-13, any of the Port C bits can be selectively
set or cleared by writing a control word to Port OOCE.
PORT B
1 = INPUT
0= OUTPUT
MODE SELECTION
O=MODEO
1 MODE 1
0
3-36. 8259A PIC PROGRAMMING
/
GROUP A
PORT C (UPPER)
1 = INPUT
0= OUTPUT
PORT A
1 = INPUT
0= OUTPUT
MODE SELECTION
00 = MODE 0
01 = MODE 1
1X=MODE2
MODE SET FLAG
1 = ACTIVE
Figure 3-12. PPI Control Word Format
\
The 8259A PIC functions as an overall manager in an
interrupt-driven system environment. It accepts
requests from the peripheral equipment, determines
which of the incoming requests is of the highest
importance (priority), ascertains whether the
incoming request has a higher priority value than the
level currently being serviced, and may issue an
interrupt to the CPU based on this determination.
The on-board master 8259A PIC handles up to eight
vectored priority interrupts and has the capability of
expanding the number of priority interrupts by
cascading one or more of its interrupt input lines with
slave 8259A PIC's. (Refer to paragraph 2-14.)
The basic functions of the PIC are to (1) resolve the
priority of interrupt requests, (2) issue a single
interrupt request to the CPU based on that priority,
and (3) send the CPU a vectored restart address for
servicing the interrupting device.
3-17
Programming Information
iSBC 86/12A
Table 3-15. Typical PPI Initialization Subroutine
;INTPAR INITIALIZES PARALLEL PORT MODES,
;DESTROYS-AL.
INTPAR:
PUBLIC
INTPAR
MOV
OUT
RET
AL,92H
OCEH,AL
;MODE WORD TO PPI PORT A&B IN,C OUT
END
Table 3-16. Typical PPI Port Read Subroutine
;AREAD READS A BYTE FROM PORT A INTO REG AL.
;DESTROYS-AL.
AREAD
AREAD:
IN
RET
AL,OCBH
;GET BYTE
END
Table 3-17. Typical PPI Port Write Subroutine
;COUT OUTPUTS A BYTE FROM REG AL TO PORT C,
;USES-AL; DESTROYS-NOTHING,
COUT:
PUBLIC
COUT
OUT
RET
OCCH,AL
;OUTPUT BYTE
END
3-37. INTERRUPT PRIORITY MODES
CONTROL WORD
The PIC can he programmed to operate in one of the
following modes:
I I I I I I I I I
07
06
05
03
04
I I I
I x
X
I
X
I
°2
0,
Do
L
a. Nested Mode
BIT SET/RESET
1 = SET
0= RESET
h. Fully Nested Mode
DON'T
CARE
c. Automatic Rotating Mode
BIT SELECT
o1 2 3 4 5 6 7
o1 o1 o1 o1
00 11 o 0 11
o 0 00 11 11
d. Specific Rotating Mode
B~I
BJ
e. Special Mask Mode
B11
f. Poll Mode
BIT SET/RESET FLAG
0= ACTIVE
Figure 3-13. PPI Port C Bit Set/Reset
Control Word Format
3-18
3-38. NESTED MODE. In this mode, the PIC
input signals are assigned a priority from 0 through
7. The PIC operates in this mode unless specifically
programmed otherwise. Interrupt IRO has the
highest priority and IR7 has the lowest priority.
When an interrupt is acknowledged, the highest
iSBC 86/12A
priority request is available to the CPU. Lower
priority interrupts are inhibited; higher priority
interrupts will be able to generate an interrupt that
will be acknowledged if the CPU has enabled its own
interrupt input through software. The End-OfInterrupt (EOI) command from the CPU is required to
reset the PIC for the next interrupt.
3-39. FULLY NESTED MODE. This mode is
used only when one or more PIC's are slaved to the
master PIC, in which case the priority is conserved
within the slave PIC's.
The operation in the fully nested mode is the same as
the nested mode except as follows:
a. When an interrupt from a slave PIC is being
serviced, that particular PIC is not locked out
from the master PIC priority logic. That is,
further interrupts of higher priority within this
slave PIC will be recognized and the master PIC
will initiate an interrupt to the CPU.
b. When exiting the interrupt service routine, the
software must check to determine if another
interrupt is pending from the same slave
PIC. This is done by sending an End-OfInterrupt (EOI) command to the slave PIC and
then reading its In-Service (IS) register. If the IS
register is clear (empty), an EOI command is sent
to the master PIC. If the IS register is not clear
(interrupt pending), no EOI command should be
sent to the master PIC.
3-40. AUTOMATIC ROTATING MODE. In this
mode, the interrupt priority rotates. Once an
interrupt on a given input is serviced, that interrupt
assumes the lowest priority. Thus, if there are a
number of simultaneous interrupts, the priority will
rotate among the interrupts in numerical order. For
example, if interrupts IR4 and IR6 request service
simultaneously, IR4 will receive the highest priority.
After service, the priority level rotates so that IR4 has
the lowest priority and IR5 assumes the highest
priority. In the worst case, seven other interrupts are
serviced before IR4 again has the highest priority. Of
course, if IR4 is the only request, it is serviced
promptly. The priority shifts when the PIC receives
an End-Of-Interrupt (EOI) command.
3-41. SPECIFIC ROTATING MODE. In this
mode, the software can change interrupt priority by
specifying the bottom priority, which automatically
sets the highest priority. For example, if IR5 is
assigned the bottom priority, IR6 assumes the
highest priority. In specific rotating mode, the
priority can be rotated by writing a Specific Rotate at
EOI (SEOI) command to the PIC. This command
contains the BCD code of the interrupt being
Programming Information
serviced; that interrupt is reset as the bottom
priority. In addition, the bottom priority interrupt
can be fixed at any time by writing a command word
to the appropriate PIC.
3-42. SPECIAL MASK MODE. One or more of
the eight interrupt request inputs can be individually
masked during the PIC initialization or at any
subsequent time. If an interrupt is masked while it is
being serviced, lower priority interrupts are inhibited. There are two ways to enable the lower priority
interrupts:
a. Write an End-Of-Interrupt (EOI) command.
b. Set the Special Mask Mode.
The Special Mask Mode is useful when one or more
interrupts are masked. If for any reason an input is
masked while it is being serviced, the lower priority
interrupts are disabled. However, it is possible to
enable the lower priority interrupt with the Special
Mask Mode. In this mode, the lower priority lines are
enabled until the Special Mask Mode is reset. Higher
priorities are not affected.
3-43. POLL MODE. In this mode the CPU internal Interrupt Enable flip-flop is clear (interrupts
disabled) and a software subroutine is used to initiate
a Poll command. In the Poll Mode, the addressed PIC
treats an 1/0 Read Comand as an interrupt
acknowledge, sets its In-Service flip-flop if there is a
pending interrupt request, and reads the priority
level. This mode is useful if there is a common service
routine for several devices.
3-44. STATUS READ
Interrupt request inputs are handled by the following
three internal PIC registers:
a. Interrupt Request Register (IRR), which stores
all interrupt levels that are requesting service.
b. In-Service Register (ISR), which stores all
interrupt levels that are being serviced.
c. Interrupt Mask Register (IMR), which stores the
interrupt request lines which are masked.
These registers can be read by writing a suitable
command word and then performing a read operation.
3-45. INITIALIZATION COMMAND WORDS
The on-board master PIC and each slave PIC requires
a separate initialization sequence to work in a
3-19
Programming Information
iSBC 86/12A
particular mode. The initialization sequence requires three Initialization Command Words (lCW's)
for a single PIC system and requires four ICW's for a
master PIC with one to eight slaves. The ICW
formats are shown in figure 3-14.
The first Initialization Command Word (IeWl),
which is required in all modes of operation, consists
of the following:
a. Bits 0 and 4 are both l's and identify the word as
ICWI for an 8086 CPU operation.
b. Bit 1 denotes whether or not the PIC is employed
in a multiple PIC configuration. For a single
master PIC configuration (no slaves), bit 1=1; for
a master with one or more slaves, bit 1=0.
leWl
NOTE
Bit 1=0 when programming a slave PIC.
1 - SINGLE
o - NOT SINGLE
1 - LEVEL TRIGGEREO INPUT
o - EDGE TRIGGERED INPUT
c. Bit 3 establishes whether the interrupts are
requested by a positive-true level input or
requested by a low-to-high input. This applies to
all input requests handled by the PIC. In other
words, if bit 3=1, a low-to-high transition is
required to request an interrupt on any of the
eight levels handled by the PIC.
SET BY B259A
ACCORDING TO INTERRUPT LEVEL
MOST SIGNIFICANT
BITS OF VECTORING BYTE
1 - IR INPUT HAS A SLAVE
0- IR INPUT DOES NOT HAVE
A SLAVE
The second Initialization Command Word (ICW2)
represents the vectoring byte (identifier) and is
required by the 8086 CPU during interrupt processing. ICW2 consists of the following:
a. Bits D3-D7 (AII-AI5) represent the five most
significant bits of the vector byte. These are
supplied by the programmer.
b. Bits DO-D2 represent the interrupt level requesting service. These bits are provided by the 8259A
during interrupt processing. These bits should
be programmed as O's when initializing the PIC.
ICW3 (SLAVE DEVICE)
NOTE
The 8086 CPU multiplies the vector byte by
four. This value is then used by the CPU as
the vector address.
1 - AUTO EOI
o - NORMAL EOI
BlE
Table 3-18 lists the vector byte contents for interrupts
IRO-IR7.
x -
L--_ _ _- - '
1
1
1
NON BUFFERED MODE
- BUFFERED MODE/SLAVE
- BUFFERED MODE/MASTER
Table 3-18. Interrupt Vector Byte
1 - FULL Y NESTED MODE
o - NOT FULL Y NESTED MODE
NOTE 1: SLAVED 10 IS EQUAL TO THE CORRESPONDING MASTER IR INPUT.
NOTE 2: X INDICATED "DON'T CARE".
Figure 3-14. PIC Initialization Command
Word Formats
3-20
07
06
05
04
IR7
A15
A14
A13
A12
03
A11
02
1
IR6
A15
A14
A13
A12
A11
IRS
A15
A14
A13
A12
A11
IR4
A15
A14
A13
A12
IR3
A15
A14
A13
A 11
01
1
00
1
1
1
1
0
0
1
A11
1
0
0
1
0
1
0
IR2
A15
A14
A13
A12
A10
A11
0
1
IR1
A15
A14
A13
A12
A11
0
0
1
IRO
A15
A14
A13
A12
A11
0
0
0
iSBC 86/12A
Programming Information
The third Initialization Command Word (lCW3) is
required only if bit 1=0 in IC\V1, specifying that
multiple PIC's are used; i.e., one or more PIC's are
slaved to the on-board master PIC. ICW3 programming can be in one of two formats: master mode
format and slave mode formai.
a. For master mode, the DO-D7 (SO-S7) bits correspond to the IRO-IR7 bits of the master PIC. For
example, if a slave PIC is connected to the master
PIC IR3 input, code bit 3=l.
b. For a slave PIC, the DO-D2 (IDO-ID2) bits identify
the master IR line that the slave PIC is connected
to. The slave compares its cascade input (generated by the master PIC) with these bits and, if they
are equal, the slave releases an interrupt vector
byte upon the reception of the second INTA
during interrupt processing.. For example, if a
slave is connected to the master interrupt line
IR5, code bits IDO-ID2=10l.
The fourth Initialization Command Word (ICW4),
which is required for all modes of operation, consists
of the following:
a. Bit DO is a 1 to identify that the word is for an
8086 CPU.
b. Bit D1 (AEOI) programs the end-of-interrupt
function. Code bit 1=1 if an EOI is to be
automatically executed (hardware). Code Bit 1=0
if an EOI command is to be generated by
software before returning from the service
routine.
c. Bit D2 (MIS) specifies if ICW4 is addressed to a
master PIC or a slave PIC. For example, code bit
2=1 in ICW4 for the master PIC. If bit D3 (BUF)
is zero, bit D2 has no function.
d. Bit D3 (BUF) specifies whether the 8259A is
operating in the buffered or nonbuffered mode.
For example, code bit 3=1 for buffered mode.
The master PIC in an iSBC 86/12A, with or
Without slaves, must be operated in the buffered
mode.
e. Bit D4 (FNM) programs the nested or fully nested
mode. (Refer to paragraphs 3-38 and 3-39).
• Master PIC - With Slave(s)
ICW1
ICW2
ICW3
T~UTA
.... "" "
"'%
• Each Slave PIC
ICW1
ICW2
ICW3
ICW4
3-46. OPERATION COMMAND WORDS
After being initialized, the master and slave PIC's
can be programmed at any time for various operating
modes. The Operation Command Word (OCW)
formats are shown in figure 3-15 and discussed in
paragraph 3-49.
3-47. ADDRESSING
The master PIC uses Port OOCO or OOC2 to write
initialization and operation command words and
Port OOC4 or OOC6 to read status, poll, and mask
bytes. Addresses for the specific functions are
provided in table 3-3.
Slave PIC's, if employed, are accessed via the
Multibus interface and their addresses are determined by the hardware designer.
3-48. INITIALIZATION
To initialize the PIC's (master and slaves), proceed as
follows (table 3-19 provides a typical PIC initialization subroutine for a PIC operated in the non-bus
vectored mode; tables 3-20 and 3-21 are typical
master PIC and slave PIC initialization subroutines
for the bus vectored mode):
a. Disable system interrupts by executing a CLI
(Clear Interrupt Flag) instruction.
b. Initialize master PIC by writing ICW's in the
following sequence:
(1) Write ICW1 to Port OOCO and ICW2 to
Port OOC2.
In summary, three or four ICW's are required to
initialize the master and each slave PIC. Specifically
• Master PIC - No Slaves
ICW1
ICW2
ICW4
(2) If slave PIC's are used, writelCW3andlCW4
to Port OOC2. If no slave PIC's are used,
omit ICW3 and write ICW4 only to Port
OOC2.
c. Initialize each slave PIC by writing ICW's in the
following sequence: ICW1, ICW2, ICW3, and
ICW4.
3-21
Programming Information
iSBC 86/12A
07
06
05
LRISEO~ EOII
OCW2
04
03
02
01
Do
0 I 0 IL2 ILl ILo
I
I
BCD LEVEL TO BE RESET
OR PUT INTO LOWEST PRIORITY
.
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
.
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
r
i~i
l
+-
~,2...l..
,2..
f4rl-,2.. 1
rl- f4-
f4-
tt:
0 0
~ ~;g:
~~~
&..J...fL
Non-specific EOI
Specific EOL LD-L2 code of IS FF to be reset
,Rotate at EOI Automatically
Rotate at EOL LD-L2 code of line
Set Rotate A FF
Clear Rotate A FF
Rotate priority independently of EOI
No Operation
OCW3
10
IESMMI SMM
OOl'T
CARE
1
0
11 1
P
1ERIS 1RIS
I
I
READ IN·SERVICE REGISTER
0
0
I
I
1
0
0
1
NO ACTION
READ
IR REG
ON NEXT
RDPULSE
1
1
READ
ISREG
ON NEXT
iffi PULSE
POLLING
A HIGH ENABLES THE NEXT AD PULSE
TO READ THE BCD CODE OF THE HIGH·
EST LEVEL REOUESTING INTERRUPT.
SPECIAL MASK MODE
0
0
I
1
1
0
NO ACTION
1
1
1
RESET
SPECIAL
MASK
SET
SPECIAL
MASK
0
Figure 3-15. PIC Operation Control Word Formats
3-22
iSBC 86/12A
Programming Information
Table 3-19. Typical PIC Initialization Subroutine (NBV Mode)
;INT59 INITIALIZES THE PIC. A 32-BYTE ADDRESS BLOCK BEGINNING WITH
;00020H IS SET UP FOR INTERRUPT SERVICE ROUTINES.
;PIC MASK IS SET, DISABLING ALL PIC INTERRUPTS.
;PIC IS IN FULLY NESTED MODE, NON-AUTO EOL
;USES SMASK; DESTROYS-A.
INT59:
PUBLIC
EXTRN
INT59
SMASK
MOV
OUT
MOV
OUT
MOV
OUT
MOV
CALL
RET
AL,13H
OCOH,AL
AL,08H
OC2H,AL
AL,1DH
OC2H,AL
AL,OFFH
SMASK
;ICW1 TO PIC
;1.cW2 TO PIC
;ICW4 TO PIC
END
Table 3-20. Typical Master PIC Initialization Subroutine (BV Mode)
°
;INTMA INITIALIZES MASTER PIC WITH A SINGLE SLAVE ATTACHED
;TO THE LEVEL INTERRUPT INPUT.
;PIC MASK IS SET WITH ALl PIC INTERRUPTS DISABLED.
;MASTER PIC IS FULLY NESTED, NON-AUTO EOL
;USES SMASK; DESTROYS AL.
INTMA:
PUBLIC
EXTRN
INTMA
SMASK
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
CALL
RET
AL,11H
OCOH,AL
AL,08H
OC2H,AL
AL,01H
OC2H,AL
AL,1DH
OC2H,AL
AL,OFFH
SMASK
;ICW1
;ICW2
;ICW3
;ICW4
END
Table 3-21. Typical Slave PIC Initialization Subroutine (BV Mode)
;INTSL INITIALIZES A SLAVE PIC LOCATED AT ADDRESS BLOCK
;BEGINNING WITH 00040H.
;PIC IS FULLY NESTED, NON-AUTO EOL
;PIC IS IDENTIFIED AS SLAVE 0.
;USES-SETI, DESTROYS-AL.
INTSL:
PUBLIC
INTSL
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
AL,11H
OCOH,AL
AL,10H
OC2H,AL
AL,OOH
OC2H,AL
AL,19H
OC2H,AL
;ICW1
;ICW2
;ICW3
;ICW4
RCT
L..I
END
3-23
Programming Information
iSBC 86/12A
d. Enable system interrupts by executing an STI
(Set Interrupt Flag) instruction.
NOTE
c. Status read of Interrupt Request Register (IRR).
d. Status read of In-Service Register (ISR).
e. Interrupt mask bits are set, reset, or read.
Each PIC independently operates in the
nested mode (paragraph 3-38) after initialization and before an Operation Control
Word (OCW) programs it otherwise.
3-49. OPERATION
After initialization, the master PIC and slave PIC's
can independently be programmed at any time by an
Operation Command Word (OCW) for the following
operations:
f. Special mask mode set or reset.
Table 3-22 lists details of the above operations. Note
that an End-Of-Interrupt (EOI) or a Special End-OfInterrupt (SEOI) command is required at the end of
each interrupt service routine to reset the ISR. The
EOI command is used in the fully nested and autorotating priority modes and the SEOI command,
which specifies the bit to be reset, is used in the
specific rotating priority mode. Tables 3-23 through
3-27 provide typical subroutines for the following:
a. Auto-rotating priority.
a. Read IRR (table 3-23).
b. Specific rotating priority.
b. Read ISR (table 3-24).
Table 3-22. PIC Operation Procedures
Operation
Auto -Rotating
Priority Mode
Procedure
To set:
In OeW2, write a Rotate Priority at EOI command (AOH) to Port ooeo.
Terminate interrupt and rotate priority:
In OeW2, write EOI command (20H) to Port ODeO.
Specific Rotating
Priority Mode
To set:
In OeW2, write a Rotate Priority at SEOI command in the following
format to Port ODeO:
I
07
I
1
06
I
1.
05
I
1
04
I
0
03
I
0
02
I
L2
01
I
L1
00
I
LO
~
I
I
BCO of IR line to be reset and/or put into lowest priority.
To terminate interrupt and rotate priority:
In OeW2, write an SEOI command in the following format to Port ODeO.
I
07
I
06
I
05
o
I
04
o
I
03
o
I
I
02
L2
I
01
L1
I
00
I
LO
~
I
BeO of ISR flip-flop to be reset.
To rotate priority without EOI:
In OCW2, write a command word in the following format to Port ooeo:
I I I I I I I I I
07
06
05
04
03
1
1
0
0
0
I
BCO of bottom priority IR line.
3-24
02
01
00
L2
L1
LO
~
I
iSBC 86/12A
Programming Information
Table 3-22. PIC Operation Procedures (Continued)
Procedure
Operation
The IRR stores a "1" in the associated bit for each IR input line that is requesting
an interrupt. To read the IRR (refer to footnote):
Interrupt Request
Register (IRR)
Status
(1) Write OAH to Port OOCO.
(2) Read Port OOCO. Status is as follows:
I
IR Line:
In-Service
Register (ISR)
Status
I 06 I 05 I 04
07
7
6
1
03
4
5
3
I 02
2
I 01
I
1
00
I
0
The ISR stores a "1" in the associated bit for priority inputs that are being serviced.
The ISR is updated when an EOI command is issued. To read the ISR (refer
to footnote):
(1) Write OBH to Port OOCO.
(2) Read Port OOCO. Status is as follows:
II
I D7 I 06 I 05 I 04 I 03 I 02 I 01 I 00 I
IR Line:
7
5
6
4
3
2
1
0
I
Be sure to reset ISR bit at end-of-interrupt when in the following modes:
Auto-Rotating (both types) and Special Mask. To reset ISR in OCW2, write:
I
07
1
0
06
1
1
05
1
1
04
1
03 1 02 1 01 1 00 I
0
0
L2
L1
LO
~
I
I
BCO identifies bit to be reset.
Interrupt Mask
Register
To set mask bits in OCW1, write the following mask byte to Port OOC2:
1 07 1 06 1 05 1 04 1 03 1 02 1 01 1 00
1
IR Bit Mask:
1 = Mask Set,
o=
M7
M6
M5
Mask Reset
M4
M3
M2
M1
MO
To read mask bits, read Port OOC2.
Special Mask
Mode
The Special Mask Mode enables desired bits that have been previously masked;
lower priority bits are also enabled.
To set, write 68H to Port OOCO.
To reset, write 48H to Port ODCO.
NOTE:
If previous operation was addressed to same register, it is not necessary to rewrite the OCW.
3-25
Programming Information
iSBC 86/12A
c. Set mask register (table 3-25).
When the NMI input goes active, the CPU performs
the following:
d. Read mask register (table 3-26).
a. Pushes the Flag registers onto the stack (same as
a PUSHF instruction).
e. Issue EOI command (table 3-27).
3-50. HARDWARE INTERRUPTS
The 8086 CPU includes two hardware interrupt
inputs, NMI and INTR, classified as non-maskable
and maskable, respectively.
3-51. NON-MASKABLE INTERRUPT (NMI)
The NMI input has the higher priority of the two
interrupt inputs. A low-to-high transition on the
NMI input will be serviced at the end of the current
instruction or between whole moves of a block-type
instruction. Worst-case response to NMI is during a
multiply, divide, or variable shift instruction.
b. If not already clear, clears the Interrupt Flag
(same as a CLI instruction);- this disables
maskable interrupts.
c. Transfers control with an indirect call through
vector location 00008.
The NMI input is intended only for catastrophic error
handling such as a system power failure. Upon
completion of the service routine, the CPU automatically restores the flags and returns to the main
program.
Table 3-23. Typical PIC Interrupt Request Register Read Subroutine
;RRO READS PIC INTERRUPT REQUEST REG.
;DESTROYS-AL.
RRO:
PUBLIC
RRO
MOV
OUT
IN
RET
AL,OAH
OCOH,AL
AL,OCOH
;OCW3 RR INSTRUCTION TO PIC
END
Table 3-24. Typical PIC In-Service Register Read Subroutine
;R ISO READS PIC IN-SERVICE REGISTER.
;DESTROY8-A.
RISO:
PUBLIC
RISO
MOV
OUT
IN
RET
AL,OBH
OCOH,AL
AL,OCOH
;OCW3 RIS INSTRUCTION TO PIC
END
Table 3-25. Typical PIC Set Mask Register Subroutine
;SMASK STORES AL REG INTO PIC MASK REG.
;A ONE MASKS OUT AN INTERRUPT, A ZERO ENABLES IT.
;US E8-AL, DESTROYS-NOTHING.
SMASK:
PUBLIC
SMASK
OUT
RET
OC2H,AL
END
3-26
iSBC 86/12A
Programming Information
Table 3-26. Typical PIC Mask Register Read Subroutine
;RMASK READS PIC MASK REG INTO AL REG.
;DESTROYS-AL.
RMASK:
PUBLIC
RMASK
IN
RET
AL,OC2H
END
Table 3-27. Typical PIC End-Of-Interrupt Command Subroutine
;EOI ISSUES END-Of-INTERRUPT TO PIC.
;DESTROYS-AL.
EOI:
PUBLIC
EOI
MOV
OUT
RET
AL,20H
OCOH,AL
;NON-SPEClfIC EOI
END
3-52. MASKABLE INTERRUPT (INTR)
The INTR input has the lower priority of the two
interrupt inputs. A high level on the INTR input will
be serviced at the end of the current instruction or at
the end of a whole move for a block-type instruction.
When INTR goes active, the CPU performs the
following (assuming the Interrupt Flag is set):
a. Issues two acknowledge signals; upon receipt of
the second acknowledge signal, the interrupting
device (master or slave PIC) will respond with a
one-byte interrupt identifier.
b. Pushes the Flag registers onto the stack (same as
a PUSHF instruction).
c. Clears the Interrupt Flag, thereby disabling
further maskable interrupts.
d. Multiplies by four (4) the binary value (X)
contained in the one-byte identifier from the
interrupting device.
e. Transfers control with an indirect call through
location 4X.
Upon completion of the service routine, the CPU
automatically restores its flags and returns to the
main program.
3-53. MASTER PIC BYTE IDENTIFIER. The
master (on-board) PIC responds to the second
acknowledge signal from the CPU only if the
interrupt request is from a non-slaved device; i.e., a
device that is connected directly to one of the master
PIC IR inputs. The master PIC has eight IR inputs
numbered IRO through IR7, which are identified by a
3-bit binary number. Thus, if an interrupt request
occurs on IR5, the master PIC responds to the second
acknowledge signal from the CPU by outputting the
byte 00OO01012(05H). The CPU multiplies this value
by four and transfers control with an indirect call
through 000101002(14H).
3-54. SLAVE PIC BYTE IDENTIFIER. Each
slave PIC is initialized with a 3-bit identifier (ID) in
ICW3. These three bits will form a part of the byte
identifier transferred to the CPU in response to the
second acknowledge signal.
The slave PIC requests an interrupt by driving the
associated master PIC IR line. The master PIC, in
tum, drives the CPU INTR input high and the CPU
outputs the first of two acknowledge signals. In
response to the first acknowledge signal, the master
PIC outputs a 3-bit binary code to slaved PIC's; this
3-bit code allows the appropriate slave PIC to
respond to the second acknowledge signal from the
CPU.
Assume that the slave PIC has the ID code 1112
assigned in ICW3, and that the device requesting
service is driving the IR2line (010). Thus, in response
to the second acknowledge signal, the slave PIC
outputs 001110102(3AH). The CPU multiplies this
value by four and transfers control with an indirect
call through 111010002(E8H).
3-27/3-28
CHAPTER 4
PRINCIPLES OF OPERATION
4-1. INTRODUCTION
This chapter provides a functional description and a
circuit analysis of the iSBC 86/12A Single Board
Computer. Figures 4-1 and 4-2, located at the end of
this chapter, are simplified foldout logic diagrams
that illustrate the functional interface between the
8086 microprocessor (CPU) and the on-board
facilities and between the CPU and the system
facilities via the Multibus interface. Also shown in
figure 4-2 is the Dual Port Control Logic that allows
the iSBC 86/12A board to function in a master/slave
relationship with the Multibus interface to allow
another bus master to access the on-board dual port
RAM.
4-2. FUNCTIONAL DESCRIPTION
A brief description of the functional blocks of logic
comprising the iSBC 86/12A board is given in the
following paragraphs. An operational circuit
a:nalysis is given beginning with paragraph 4-13.
4-3. CLOCK CIRCUITS
The clock circuit composed of A16, A17, and A18 is
stabilized by a 22.1184-MHz crystal. This circuit
provides nominal 153.6-kHz, 1. 23-MHz, and 2.46MHz optional clock frequencies to the 8253 Programmable Interval Timer (PIT); 2.46-MHz Baud rate
clock to the 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART); and a
22.12-MHz clock frequency to the Dual Port Control
Logic and RAM Controller.
The clock circuit composed of A80 and A63 is
stabilized by an 18.432-MHz crystal. This circuit
divides the crystal frequency by two to provide the
nominaI9.22-MHz Bus Clock (BCLK/) and Constant
Clock (CCLK/) signals to the Multibus interface.
(The BCLK/ signal is also used by the 8289 Bus
Arbiter.) Removable jumpers are provided to allow
this clock circuit to be disabled if some other source
supplies BCLK/ and CCLK/ to the Multibus
interface.
Clock generator A38 is stabilized by a 15-MHz
crystal and provides a nominal5-MHz clock to CPU
A39, Status Decoder A81, Bus Arbiter A82, and Bus
Command Decoder A83. Clock A38 also provides a
reset signal on power-up and when commanded to do
so by an optional signal supplied via auxiliary
connector P2. The RESET signal initializes the
system as well as certain iSBC 86/12A board
components to a known internal state.
4-4. CENTRAL PROCESSOR UNIT
The 8086 Microprocessor (CPU A39), which is the
heart of the single board computer, performs the
system processing functions and generates the
address and control signals required to access
memory and I/O devices. Control signals SO, Sl,
and S2 are driven by the CPU and decoded by Status
Decoder A81 to develop the various signals required
to control the board. The CPU ADO-AD15 pins are
used to multiplex the 16-bit input! output data and
the lower 16-bits of the address. During the first part
of a transfer cycle, for example, the lower 16-bits
(ADO-AD15) and the upper 4-bits (AD16-AD19) are
strobed into Address Latch A40/41/57 by the
Address Latch Enable (ALE) signal. (The ALE
signal is derived by decoding SO, Sl, and S2.) The
Address Latch outputs form the 20-bit address bus
ABO-AB13; i.e., ABO-ABF and AB10-AB13. During
the remainder of the transfer cycle, the ADO-AD15
pins of the CPU are used to form the 16-bit data bus
ADO-ADF.
4-5. INTERVAL TIMER
The 8253 Programmable Interval Timer (PIT)
includes three independently controlled counters
that provide optional (jumper selectable) timing
inputs to the on-board I/O devices and the CPU
interrupts. The clock frequency of 2.46 MHz, 1.23
MHz, or 153.6 kHz, which is derived from the clock
circuit composed of A16, A17, and A18, provides the
basic timing input.
Counter 2 provides timing for the serial I/O port
(8251A USART). This counter, in conjunction with
the USART, can provide programmable Baud rates
from 110 to 9600. Counter 0 can be used in one of two
ways: (1) as a clock generator it can be buffered to
provide an external user-defined clock or (2) as an
interval timer to generate a CPU interrupt. Counter
1, which is the system interval timer and can also
generate an interrupt, has a range of 1.6 microseconds to 853.3 milliseconds. If longer times are
needed, Counters 0 and 1 can be cascaded to provide a
single timer with a maximum delay of over 7 hours.
4-1
Principles of Operation
4-6. SERIAL 1/0
The 8251A USART provides RS232C compatibility
and is configured as a data terminal. Synchronous
or asynchronous mode, character size, parity bits,
stop bits, and Baud rates are all programmable.
Data, clocks and control lines to and from connector
J2 are buffered.
4-7. PARALLEL 1/0
The 8255A Programmable Peripheral Interface
provides 24 programmable I/O lines. Two I C sockets
are provided so that, depending on the application,
TTL drivers or I/O terminators may be installed to
complete the interface to connector Jl. The 24 lines
are grouped into three ports of eight lines each; these
ports can be programmed to be simple I/O ports,
strobed I/O ports with handshaking, or one port can
be programmed as a bidirectional port with control
lines. The iSBC 86/12A board includes various
optional functions controlled by the parallel I/O
lines such as an RS232C interface line, timer gate
control lines, bus override, strobed I/O port interrupts, and one Multibus interface interrupt.
4-8. INTERRUPr CONTROLLER
iSBC 86/12A
interrupt lines (INTO/-INT7 /) can be connected to
the master PIC to provide 8 to 64 bus interrupt
levels. The user can map interrupt sources into
interrupt levels by hardware jumpers. The iSBC
86/I2A board can also generate one Multibus
interface interrupt that is controlled by an 8255A PPI
output bit.
NOTE
The 86/I2A board must be capable of
Multibus interface access when using
interrupts.
4-9. ROMIEPROM CONFIGURATION
IC sockets A28, A29, A46, and A47 are provided for
user installation of ROM or EPROM chips; jumpers
are provided to accommodate either 2K, 4K, or 8K
chips. The ROM/EPROM address space is located
at the top of the I-megabyte memory space because
the 8086 CPU branches to FFFFO after a reset. Starting addresses for the different ROM/EPROM
configurations are FFOOO (using 2K chips), FEOOO
(using 4K chips), and FCOOO (using 8K chips).
When the iSBC 340 Multimodule EPROM board is
installed, the starting address is F8000.
The 8259A Programmable Interrupt Controller (PIC)
handles up to eight vectored priority interrupts. The
8259A PIC provides the capability to expand the
number of priority interrupts by cascading each
interrupt line with another 8259A PIC. (Refer to
figure 2-2.) This is done by programming the master
PIC (the one on the iSBC 86/12A board) so that an
interrupt line (e.g., IR3) is connected to a slave PIC
(the one interfaced to the master PIC via the Multibus
interface). If an IR3 interrupt is sensed by the master
PIC, it will allow the slave PIC to send the restart
vector address to the CPU. Each interrupt line into
the master PIC can be individually programmed to be
a non-bus vectored (NBV) interrupt line (master PIC
generates the restart address) or a bus vectored (BV)
interrupt (cascaded to a slave PIC which generates
the restart address). The iSBC 86/12A board can
handle eight on-board or single Multibus interface
interrupt lines (an interrupt line which does not have
a slave PIC connected to it) or, with the aid of eight
slave PIC's, expand the number of interrupts to
64. All 64 interrupts must be processed through the
slave PIC's and must therefore be external to the
iSBC 86/12A board.
The Dual Port Control Logic interfaces the RAM
with the Multibus interface so that the iSBC 86/I2A
board can perform as a slave RAM device when not
acting as a bus master. This dual port is designed to
maximize the CPU throughput by defaulting control
to the CPU when not in demand. Each time a bus
master generates a memory request to the dual port
RAM via the Multibus interface, the RAM must be
taken away from the CPU (when the CPU is not
using it). When the slave request is completed, the
control of the RAM returns to the CPU.
There are nine jumper-selectable interrupt sources:
serial I/O port (2), parallel I/O interface (2), timers
(2), external via J1 (1), powel" fail (1), and Multibus
interface time out (1). The eight Multibus interface
The dual port consists of CPU address and data
buffers and decoder; bidirectional address and data
bus (Multibus interface) drivers; slave RAM address
decoder/translator; control logic; and the RAM and
RAM controller.
4-2
4-10. RAM CONFIGURATION
The iSBC 86/I2A board includes 32K bytes of
read/write memory composed of sixteen 2117
Dynamic RAM chips and an 8202 RAM Controller.
If the iSBC 300 Multimodule RAM board is installed,
the read/write memory is expanded to 64k bytes of
memory composed of thirty-two 2117 dynamic RAM
chips and an 8202 RAM Controller.
iSBC 86/12A
The CPU address and data buffers separate the onboard bus (I/O and ROM/EPROM) from the dual
port bus. On-board RAM addresses (as seen by the
CPU) are (assigned from the bottom up) 0000007FFF. If the iSBC 300 Multimodule RAM board is
installed, the on-board RAM addresses are 00000OFFFF.
The address bus drivers and data bus drivers
separate the dual port bus from the Multibus
interface. The slave RAM address decoder is
separate from the CPU RAM address decoder to
provide independent Multibus interface address
selection that can be located throughout the
I-megabyte address space. The slave RAM address
is selected by specifying the base address and
memory size. The base address can be on any 8K
boundary (16K boundary if iSBC 300 Multimodule
RAM board is installed) with the exception that the
memory space cannot extend across a 128K boundary. The memory size specifies the amount of Dual
Port RAM accessible by the Multibus interface and is
switch selectable in 8K increments (16K increments
if iSBC 300 Multimodule RAM board is installed).
This provides the capability to reserve sections of the
dual port RAM for use only by the CPU and frees up
the address space. Regardless of what base address
is selected, the slave RAM address is mapped into an
on-board RAM address (as seen by the CPU). (Refer
to figure 2-1.)
4-11. BUS STRUCTURE
The iSBC 86/12A board architecture is organized
around a three-bus hierarchy: the on-board bus, the
dual port bus, and the Multibus interface. (Refer to
figure 4-3.) Each bus can communicate only within
itself and an adjacent bus, and each bus can operate
independently of each other. The performance of the
iSBC 86/12A board is directly related to which bus it
must go to perform an operation; that is, the closer the
bus to the on-board bus, the better the performance.
Principles of Operation
The iSBC 86/12A board operates at a 5-MHz CPU
cycle and requires one wait state for all on-board
system accesses. (Exception: a RAM write requires
two wait states.) However, the pipeline effect of the
8086 CPU effectively "hides" these wait states.
The core oftheiSBC 86/12A board bus architecture is
the on-board bus, which connects the CPU to all onboard I/O devices, ROM/EPROM, and the dual port
RAM bus. Activity on this bus does not require
control of the outer buses, thus permitting independent execution of on-board activities. Activities at
this level require no bus overhead and operate at
maximum board performance.
The next bus in the hierarchy is the dual port
bus. This bus controls the dynamic RAM and
communicates with the on-board bus and the
Multibus interface. The dual port bus can be in one of
three states:
a. State 1 - On-board bus is controlling it but not
using it (not busy).
b. State 2 - On-board bus is controlling it and
using it (busy).
c. State 3 - Multibus interface is controlling it
and using it (busy).
State 1 is the idle state of the dual port bus and is left
in control of the on-board bus to minimize delays
when the CPU needs it. When the on-board bus
requires the dual port bus to access RAM, the dual
port bus control logic will go from State 1 to State
2. (If the dual port bus is busy, it will wait until it is
not busy.) Activity at this level requires a minimum
of bus overhead and the RAM performance is
designed to equal that of on-board activity (if the dual
port bus is not busy when the on-board bus requests
it). The dual port bus control logic returns to State 1
when the CPU completes its operation. This level of
bus activity operates independently of the Multibus
interface activity (if the Multibus interface does not
need the dual port bus).
When the Multibus interface requests the dual port
bus, the control logic goes from State 1 to 3 (it will wait
if busy) in about 150 nanoseconds and, upon
completion, returns to State 1. The Multibus interface use of the dual port bus is independent of the onboard activity.
Figure 4-3. Internal Bus Structure
When the on-board bus needs the Multibus interface,
it must go through the dual port bus to the Multibus
interface. The on-board bus uses the dual port bus
only to communicate with the :M:ultibus interface and
leaves the dual port bus in State 1. Activity at this
level requires a minimum 200-nanosecond overhead
for Multibus interface exchange.
4-3
iSBC 86/12A
Principles of Operation
4-12. MULTIBUS INTERFACE
The iSBC 86/12A board is completely Multibus
interface compatible and supports both 8-bit and
16-bit operations. The Multibus interface includes
the Bus Arbiter A82, Bus Command Decoder A83,
bidirectional address bus and data bus drivers, and
interrupt drivers and receivers. The Bus Arbiter
allows the iSBC 86/12A board to operate as a bus
master in the system in which the 8086 CPU can
request the Multibus interface when a bus resource is
needed.
4-13. CIRCUIT ANALYSIS
The schematic diagram for the iSBC 86/12A board is
given in figure 5-2. The schematic diagram consists
of 11 sheets, each of which includes grid coordinates.
Signals that traverse from one sheet to another are
assigned grid coordinates at both the signal source
and signal destination. For example, the grid
coordinates 2ZBI locate a signal source (or signal
destination as the case may be) on sheet 2 zone BI.
Both active-high and active-low signals are used. A
signal mnemonic that ends with a virgule (e.g.,
DAT7 I) denotes that the signal is active low
(~O.4V). Conversely, a signal mnemonic without a
virgule (e.g., ALE) denotes that the signal is active
high (~2.0V).
Figures 4-1 and 4-2 at the end of this chapter are
simplified logic diagrams of the input/output,
interrupt, and memory sections. These diagrams will
be helpful in understanding both the addressing
scheme and the internal bus structure of the board.
4-14. INITIALIZATION
When power is applied in a start-up sequence, the
contents of the 8086 CPU program counter, program
status word, interrupt enable flip-flop, etc., are
subject to random factors and cannot be predicted.
For this reason, a power-up sequence is used to set the
CPU, Bus Arbiter, and 1/0 ports to a known internal
state.
When power is initially applied to the iSBC 86/12A
board, capacitor C26 (2ZD6) begins to charge through
resistor R9. The charge developed across C26 is
sensed by a Schmitt trigger, which is internal to
Clock Generator A38. The Schmitt trigger converts
the slow transition appearing at pin 11 into a clean,
fast-rising synchronized RESET signal at pin
10. The RESET signal is inverted by A48-6 to
develop RESETI and INIT/. The RESETI signal
automatically sets the 8086 CPU program counter to
FFFFO and clears the interrupt enable flip-flop; resets
the parallel 1/0 ports to the input mode; resets the
serial 1/0 port to the "idle" mode; and resets the Bus
4-4
Arbiter (outputs are tristated). The INITI signal is
transmitted over the Multibus interface to set the
entire system to a known internal state.
The initialization described above can be performed
at any time by inputting an AUX RESETI signal via
auxiliary connector P2.
4-15. CLOCK CIRCUITS
The 5-MHz CLK is developed by Clock Generator
A38 (2ZC6) in conjunction with crystal Y2. This
clock is the time base for CPU A39, Status Decoder
A8I, Bus Arbiter A82, and Bus Command Decoder
A83.
The time base for Bus Clock (BCLK/) and Constant
Clock (CCLK/) is provided by Clock Generator A80
(IOZB5) and crystal Y3. The 18.432-MHz crystal
frequency is divided by A63 and driven onto the
Multibus interface through jumpers EI05-EI06 and
EI03-EI04. The BCLKI signal is also used as a clock
input to the Bus Arbiter A82.
The time base for the remaining functions on the
board is provided by clock Generator Al 7 (7ZA6) and
crystal YI. The nominal 22.12-MHz crystal frequency appearing at the OSC output of AI7 is
buffered and supplied to the Dual Port Control Logic
and to RAM Controller A 70. Clock Generator AI7
also divides the crystal frequency by nine to develop a
2.46-MHz clock at its cf>2TTL output. The 2.46-MHz
clock is applied directly to the clock input of the 825IA
USART and applied through AI8 to provide a
selectable clock for the 8253 PIT. Divider AI6 divides
the 2.46 MHz clock by two and by nine, respectively,
to produce 1.23-MHz and 153.6-kHz selectable clocks
for the 8253 PIT.
4-16.8086 CPU TIMING
The 8086 CPU uses the 5-MHz clock input to develop
the timing requirements for various time-dependent
functions described in following paragraphs.
4-17. BASIC TIMING. Each CPU bus cycle
consists of at least four clock (CLK) cycles referred to
as TI, T2, T3, and T4. The address is emitted from the
CPU during TI and data transfer occurs on the bus
during T3 and T4; T2 is used primarily for changing
the direction ofthe bus during read operations. In the
event that a "not ready" indication is given by the
addressed device, "wait" states (TW) are inserted
between T3 and T4. Each inserted TW state is of the
same duration as a CLK cycle. Periods can occur
between CPU-driven bus cycles; these periods are
referred to as "idle" states (TI) or inactive CLK
cycles. The processor uses TI states for internal
housekeeping.
Principles of Operation
iSBC 86/12A
(DTIR) signal, which is asserted at the end ofT1, is
4-18. BUS TIMING. The CPU generates status
signals SO, Sl, and S2 during T1 of every machine
cycle. These status signals are used by Status
Decoder A81, Bus Arbiter A82, and Bus Command
Decoder A83 to identify the following types of
machine cycles.
S2
S1
SO
CPU Machine Cycle
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
Interrupt Acknowledge
I/O Read
I/O Write
Halt
Code Access
Memory Read
Memory Write
Passive
1
1
1
1
used to set up the various data buffers and data bus
drivers for a CPU read operation. The Memory Read
Command (MRDC/) or 1/0 Read Comand (IORC/) is
asserted from the beginning of T2 to the beginning of
T4. Ai ihe beginning ofT3, the ADO-AD 15 lines of the
local bus are switched to the "data" mode and the
Data Enable (DEN) signal is asserted. (The DEN
signal enables the data buffers.) The CPU examines
the state of its READY input during the last half of
T3. If its READY input is high (signifying that the
addressed device has placed data on the data lines),
the CPU proceeds into T4; if its READY input is low,
the CPU enters a wait (TW) state and stays there until
READY goes high. The external effect of using the
READY input is to preserve the exact state of the
CPU at the end of T3 for an integral number of clock
periods before finishing the transfer cycle. This
'stretching' of the system timing, in effect, increases
the allowable access time for memory or 1/0
devices. By inserting TW states, the CPU can
accommodate slower memory or slower 1/0 devices.
The CPU accepts the data and terminates the
command in T4; the DEN signal then goes false and
the data buffers are tristated.
A read cycle begins in T1 with the assertion of the
Address Latch Enable (ALE) signal and the emission
of the address. (Refer to figure 4-4.) The trailing
edge of the ALE signal latches the address into
Address Latch A40/41/57 (2ZB2). (The BHENI
signal and address bit ADO address the low byte, high
byte, or both bytes.) The Data TransmitlReceive
T1
T2
T4
T3
5-MHZ ClK
\
STATUS
\..._-
" 82/, 8i/, 801
FLOAT
VALID
" BHEN/, AD16-AD19
ALE
ADDRESS
~
DATA IN
FLOAT
ADO-AD15
DT/R
MRDC/- IORC/
," DEN
NOTE: INTA/, AMWC/, MWTC/, AIOWC/, IOWC/
= VOH
"DENOTES CPU INPUT OR OUTPUT
""DENOTES STATUS DECODER A81 OUTPUT S!GNAL
Figure 4-4. CPU Read Timing
4-5
Principles of Operation
iSBC 86/12A
issued. The CPU examines the state of its READY
input during the last half of T3. When READY goes
high (signifying that the addressed device has
accepted the data), the CPU enters T4 and terminates
the write strobe. DEN then goes false and the data
buffers are tristated.
A write cycle begins in T1 with the assertion of the
ALE signal and the emission of the address. (Refer to
figure 4-5.) The trailing edge of ALE latches the
address into the address latch as described for a read
cycle. The DTiR signal remains high throughout the
entire write cycle to set up the data buffers and data
bus drivers for a CPU write operation. Status
Decoder A81 (3ZB4) provides two types of write strobe
signals: advanced (AMWT I and AIOWC) and
normal (MWTCI and 10WC/). As shown in figure
4-5, the advanced memory and advanced 1/0 write
strobes are issued one clock cycle earlier than the
normal memory and 1/0 write strobes. (The iSBC
86/12A board doesn't use advanced 1/0 write strobe
AIOWC/.) At the beginning of T2, the advanced
write and DEN signals are asserted and the ADOAD15lines of the local bus are switched to the "data"
mode. (The DEN signal enables the data buffers.)
The CPU then places the data on the ADO-AD15 lines
and, at the beginningofT3, the normal write strobe is
The CPU interrupt acknowledge (INTA) cycle timing
is shown in figure 4-6. Two back-to-back INTA
cycles are required for each interrupt initiated by the
8259A PIC or by a slave 8259A PIC cascaded to the
master PIC. The INTA cycle is similar to a read
cycle. The basic difference is that an INTAI signal is
asserted instead of an MRDCI or 10RCI signal and
the address bus is floated. In the second INTA cycle,
a byte of information (supplied by the 8259A PIC) is
read from "data" lines ADO-AD7. This byte, which
identifies the interrupting source, is multiplied by
four by the CPU and used as a pointer into an
interrupt vector look-up table.
T2
T1
T3
T4
5·MHZ ClK
* S2/, S1/, SOl
FLOAT
VALID
* BHEN/,
**
AD16·AD19
ALE
ADDRESS
DATA OUT
, ADO·AD15
**
DEN
**
AMWT/ + AIOWCI
MWTCI + IOWCI
NOTES:
_
1. INTA/, IORCI, MRDC/, DTIR = VOH.
2. FLOATS ONLY IF ENTERING A "HOLD" CONDITION.
*DENOTES CPU INPUT OR OUTPUT
"'DENOTES STATUS DECODER A81 OUTPUT
Figure 4-5. CPU Write Timing
4-6
FLOAT
(NOTE 2)
iSBC 86/12A
Principles of Operation
T1
T4
T3
T2
5-MHZ CLK
* 52/, 51/, 501
FLOAT
VALID
*
BHEN/, AD16-AD19
** ALE
I
FLhAT
(NOTE 2)
CASCADE ADD RiESS
AS-A10
I
FLOAT
(NOTE 2)
FLOAT
* ADS-AD15
FLOAT (NOTE 2)
*
**
POINTER
FLOAT
ADO-AD7
MCE
-
J
\
** DT/R
**
INTA/
**
DEN
--
NOTES:
1. MRDC/, IORCI, AMWCI, MWTC/, AIOWCI, IOWCI = VOH; BHENI = VOL
2. THE TWO INTA CYCLES RUN BACK-TO-BACK. THUS, THE LOCAL BUS
IS FLOATING WHEN THE SECOND INTA CYCLE IS ENTERED.
*DENOTES CPU INPUT OR OUTPUT
**DENOTES STATUS DECODER AS, OUTPUT
Figure 4-6. CPU Interrupt Acknowledge Cycle Timing
4-7
iSBC 86/12A
Principles of Operation
4-19. ADDRESS BUS
The address bus is shown in weighted lines in figures
4-1 and 4-2. The 20-bit address (ADO-AD19) is
output by CPU A39 (2ZB4) during the first clock cycle
(T1) of the memory or 1/0 instruction. The trailing
edge of the Address Latch Enable (ALE) signal,
output by Status Decoder A81 (3ZB4) during T1,
strobes and latches the address into Latch A40/41/57
(2ZB2). The latched address is distributed as follows:
Signal
Address Latch Enable. Strobes address into
Address Latch A40/41 157.
AIOWCI
Advanced I/O Write. An 1/0 Write Command that
is issued earlier than 10WCI in an attempt to
avoid impOSing a CPU wait state. (Not Used)
AMWCI
Advanced Memory Write Command. A Memory
Write Command that is issued earlier than
MWTCI in an attempt to avoid imposing a CPU
wait state.
DEN
Data Enable. Enables Data Buffers A44/456 and
A60/61.
Data Transmit/Receive. Establishes direction of
Data transfer through Data Buffers A44/45 and
A60/61 and Data Bus Buffers A69/89/90.
a. AB3-ABF to 1/0 Address Decoder A54/55/56
(6ZA6).
DT/R
b. ABB-AB12 to PROM Address Decode Logic A68
(6ZC6).
10RCI
c. AB1-ABC to PROM A28/29/46/47 (6ZC3).
10WCI
d. AB13 to on-board RAM address recognition gate
A53-6 (6ZD5).
INTAI
MCE
4-20. DATA BUS
At the beginning of clock cycle T2, the CPU ADOAD15 pins become the source or destination of data
bus ADO-ADF. Data can be sourced to or input from
the following:
a. Data Buffer A44/45 (4ZC3).
b. Data Buffer A60161 (4ZC5).
4-21. BUS TIME OUT
Bus Time Out one-shot A5 (lOZA6) is triggered by the
leading edge of the ALE signal. If the CPU halts, or
is hung up in a wait state for approximately 6.2
(±15%) milliseconds, A5 times out and asserts the
TIMEOUT I signal. If jumper E5-E6 (2ZB6) is
installed, the TIMEOUTI signal drives the CPU
READY line high through A 7-12 and A38-5 to allow
the CPU to exit the wait state. The TIMEOUTI
signal is also routed as a TIMEOUT INTRI signal to
the interrupt jumper matrix (8ZC2).
4-22. INTERNAL CONTROL SIGNALS
Status Decoder A81 (3ZB4) receives the 5-MHz CLK
signal from Clock Generator A38 and status signals
S0-82 from CPU A39. The CLK signal establishes
when the command signals are generated as a result
of decoding SO-S2. The following signals are output
from Status Decoder A81:
4-8
Definition
ALE
MRDCI
MWTCI
110 Read Command to on-board PPI, USART,
PIT, and PIC.
I/O Write Command to on-board PPI, USART,
PIT, and PIC.
Interrupt Acknowledge. Provides on-board control during INTA cycle.
Master Cascade Enable. Enable cascade address from master 8259A PIC onto local bus so
that slave PIC address can be latched.
Memory Read Command. Establishes direction
of data transfer through Memory Data Buffers A71/91.
Memory Write Command. Places the 8202
RAM Controller A 70 in a write mode.
4-23. DUAL PORT CONTROL LOGIC
The Dual Port Control Logic (figure 5-2 sheet 11)
allows the dual port RAM facilities to be shared by
the on-board CPU or by another bus master via the
Multibus interface. When not acting as a bus master
or when not accessing the dual port RAM, the iSBC
86/12A board can act as a "slave" RAM device in a
multiple bus master system. When accessing the
dual port RAM, the on-board CPU has priority over
any attempt to access the dual port RAM via the
Multibus interface. In this situation, the bus access
is held off until the CPU has completed its particular
read or write operation. When a bus access is in
progress, the Dual Port Control Logic enters the
"slave" mode and any subsequent CPU request will
be held off until the slave mode is terminated. Figures 4-7 and 4-8 are timing diagrams for the Dual
Port Control Logic.
4-24. MULTIBUS INTERFACE ACCESS
TIMING. Figure 4-7 illustrates the Dual Port Control Logic timing for dual port RAM access via the
Multibus interface. (P-periods PO through P17 are
used only for descriptive purposes and have no
relationship to the 22.12-MHz clock signal.) When
the OFF BD RAM CMD signal goes high, A49-10
(11ZC6) goes high and A49-7 (11ZB5) goes low on the
next rising edge of the clock at the end of PO
(assuming that ON BD RAM RQTI and RAM
XACKI are both high).
Principles of Operation
iSBC 86/12A
DUAL PORT CLK P-PERIODS
PO
P1
P2
P3
P4
P13
I
P14
P15
P16
P17
22.12 MHZ CLK
ON BD RAM ROTI
OFF BO RAM CMD
FF A49-10
a
FF ASO-5 Q
FF A49-14
FF A49-7
a
a
0
0
0
0
0
SLAVE CMD ENI
0
DP RDI OR DP WRTI
0
RAM XACKI
8086 CPU CONTROL
0
CPU CONTROL
MUL TIBUS INTERFACE CONTROL
Figure 4-7. Dual Port Control Multibus™ Interface Access Timing With CPU Lockout
4-9
Principles of Operation
At the end of PI, A50-5 (1IZC5) goes high and asserts
the SLAVE MODEl via inverter A31-8(IIZC4). The
outputs of A50-5 and A49-7 are ANDed to hold A50-5
in the preset (high) state. At the end of P2, A49-14
(1IZC3) goes low and asserts the SLAVE CMD ENI
signal, which gates DP RDI or DP WRT I to RAM
Controller A 70 (IOZB6); SLAVE CMD EN I also gates
the subsequently generated RAM XACKI to the CPU
READY input (RAM XACKI is generated by the
RAM Controller when data has been read from or
written into RAM.)
The RAM Controller asserts RAM XACKI during
Pl3 and A49-10 goes low on the next rising edge of
the clock. The bus master then terminates the OFF
BD RAM CMD signal which terminates the SLAVE
CMD EN I signal. The SLAVE CMD EN I signal
going high terminates the DPRDI or DPWRTI
signal. The RAM Controller next terminates RAM
XACKI and then A49-7 goes high on the next rising
edge of the clock. At the end of P16, A50-5 goes low
terminating the SLAVE MODEl signal. At the end
of P17, A49-14 goes high.
iSBC 86/12A
instruction. (A49-10 is allowed to go high on the next
rising edge of the clock after ALEI goes false.)
The subsequently generated DP RDI or DP WRT I
signal, gated by the asserted ON BD CMD EN I
signal, is transmitted to RAM Controller A 70
(IOZB6). When the read or write is completed, the
RAM Controller asserts RAM XACKI and A49-10
goes low at the end ofPl2. At the end ofPl3, the CPU
terminates the instruction and the ON BD RAM
RQT/, DP RDI orDP WRT/, andADV MEM WRTI
or MEM RDI signals go false. The RAM XACKI
signal is then terminated andA49-10 goes high at the
end of PO. At the end of PI, the SLAVE MODEl is
entered when A50-5 goes high.
The foregoing discussion pertains only to the
operation of the Dual Port Control Logic for CPU
access of on-board RAM. The actual addressing and
transfer of data are discussed in paragraph 4-37.
4-26. MULTIBUS INTERFACE ARBITRATION
The foregoing discussion pertains only to the
operation of the Dual Port Control Logic for Multibus
interface access of the dual port RAM. The actual
addressing and transfer of data are discussed in
paragraph 4-38.
4-25. CPU ACCESS TIMING. Figure 4-8
illustrates the Dual Port Control Logic timing for
dual port RAM access by the on-board 8086
CPU.. (P-periods PO through Pl3 are used only for
descriptive purposes and have no relationship to the
22.12-MHz clock signal.) To demonstrate that the
CPU has priority in the access of the dual port RAM,
figure 4-8 shows the OFF BD RAM CMD signal
active when the CPU access is initiated by the ON BD
RAM RQT I signal. The timing has progressed
through PO, during which time A49-10 has been
clocked high and A49-7 has been clocked low.
Flip-Flop A50-9 is preset (high) when the Status
Decoder asserts the ALEI signal at the beginning of
Tl in the CPU instruction cycle. When the ON BD
RAM RQTI signal is asserted, the EXT ALE signal
goes low and, since A51-6 is now low, A49-10 goes
low on the next rising edge of the clock. Flip-Flop
A50-5 is thus prevented from being clocked high and
therefore keeps the DP ON BD ADR ENI signal
asserted and suppresses the SLAVE MODEl signal.
The ON BD CMD ENI signal is asserted at the same
time as the ON BD RAM RQT I signal since A49-14 is
high. The ADV MEM WRTI or MEM RDI signal
from the Status Decoder is ANDed with the ON BD
RAM RQT I signal to prevent A50-5 from changing
states when ALEI goes false at the end of TI in the
4-10
The Multibus interface arbitration circuits consist of
the Bus Arbiter A82 (3ZD4), Bus Command Decoder
A83 (3ZC4), bidirectional Address Bus Driver A87/88
(5ZA3), bidirectional Data Bus Driver A69/89/90
(4ZB4), and the Slave RAM Decode Logic (figure 5-2
sheet 3).
The falling edge of CLK provides the timing to
establish when Bus Arbiter actions are initiated. The
falling edge of BCLKI provides the bus timing
reference for the Bus Arbiter, which allows the iSBC
86/12A board to assume the role of bus master. When
the ON BD ADRI (3ZC7) signal is false (high) and the
SO-S2 status signals indicate either a read or write
operation, the Bus Arbiter drives CBRQI and BREQI
low and BPROI high (3ZD2). The BREQI output, in
conjunction with CBRQ/, from each bus master in
the system is used by the Multibus interface when the
bus priority is resolved by a parallel priority scheme
as described in paragraph 2-24. The BPROI output,
in conjunction with CBRQ/, is used by the Multibus
interface when the bus priority is resolved by a serial
priority scheme as described in paragraph 2-23.
The iSBC 86/12Ahoard gains controloftheMultibus
interface when the BPRNI input to the Bus Arbiter is
driven low and CBRQI is high. On the next falling
edge of BCLK/, the Bus Arbiter drives BUSYI and
BUS ADENI low. The BUSYI output indicates that
the bus is in use and that the current bus master, in
control, will not relinquish control until it raises its
BUSY I signal.
The BUS ADEN I output, which can be thought of as
a "master bus control" signal, is applied to the
Principles of Operation
iSBC 86/12A
DUAL PORT ClK P-PERIODS
PO
P1
P2
., ., ., .,
ON BD RAM RaT!
o
OFF BD RAM CMD
o
a
o
a
o
FF A49-10
FF ASO-S
a
FF A49-14
FF A49-7
a
a
r~
r-1
PO
rT~
P1
r-1
P2
rI
P3
P4
.,
.,
I
IUUUUUUUUUUU
22.12 MHZ ClK
FF ASO-9
P13
P12
~:
DP ON BD ADR EN/
o
SLAVE MODE
I
0
0
ON BD CMD EN!
0
SLAVE CMD EN!
0
DP RD! OR DP WRT!
0
ADV MEM WRT/ OR MEM RD/ 0
RAM XACKJ
o
8086 CPU CONTROL
0
CPU CONTROL
MUlTIBUS INTERFACE CONTROL
FOR REMAINDER OF
MULTIBUS INTERFACE
ACCESS TIMING, SEE
FIG. 4-7 BEGINNING
WITH P3.
Figure 4-8. Dual Port Control CPU Access Timing With Multibus™ Interface Lockout
4-11
iSBC 86/12A
Principles of Operation
AEN2/ input of Clock Generator A38 (2ZC6), the Bus
Address Driver A87/88 (5ZA3), and the input of AND
gate A2-II (3ZC5). With AEN2/ enabled, the Clock
Generator is prepared to recognize the ensuing
acknowledge signal (AACK/ or XACK/) transmitted
by the addressed system device. To ensure adequate
setup for the address and data, counter A4 (2ZB6) is
held in the clear state as long as ALE/ is asserted.
When ALE/ goes false, A4-3 is clocked low by the
5-MHz clock to generate T2I/. This signal (T2I/) is
driven through gate A2-II (3ZC5) to enable the Bus
Command Decoder A83.
The false ON BD ADR/ signal enables the Bus
Command Decoder, which decodes SO-S2 and drives
the appropriate command low on the Multibus
interface when CLK goes low. The Bus Command
Decoder also drives BUS DEN (3ZC2) high to enable
Data Bus Driver A69/89 (4ZB4). The Data Bus
Driver is switched to the appropriate "transmit" or
"receive" mode depending on the state of the DT /R
output of Status Decoder A8I (3ZB4).
After the command is acknowledged (signified by the
addressed device driving the Multibus interface
XACK/ line low), the CPU terminates the appropriate command. The Bus Arbiter terminates BUS
ADEN / and the Bus Command Decoder terminates
BUS DEN. The Bus Arbiter mayor may not relinquish control of the Multibus interface (depends on
how the Bus Arbiter is jumper wired) by driving
BREQ/ high and BPRO/ low and then raising
BUSY/.
It should be noted that, after gaining control of the
Multibus interface, the iSBC 86/I2A board can
invoke a "bus lock" condition to prevent losing
control at a critical time. (For instance, it may be
desired to execute several consecutive commands
without having to contend for the bus after each
command is executed.) The "bus lock" condition is
invoked by driving the Bus Arbiter LOCK input low
in one of two ways:
a. By executing a software LOCK XCNG command.
b. By clearing an option bit via I/O Port OOCC.
During an interrupt from the 8259A PIC, the LOCK
input is automatically driven low by the first of two
INTA/ signals issued by Status Decoder A8I. (Referto
paragraphs 4-40 through 4-42.)
4-28. ON-BOARD 1/0 OPERATION. Address
bits AB3-ABF are applied to the 110 Address Decoder
composed of A54/55/56 (6ZB6). The ADV 110 ADR
signal is developed by flip-flop A30-I6 (2ZA2) when the
ALE signal latches the CPU inverted S2 signal. When
ADV I/O ADR is true, the I/O Address Decoder
develops 10 AACK/ (6ZA2) when AB8-ABF are false,
AB6-AB7 are true, and AB5 is false. The 110 AACK/
signal enables decoder A54 (6ZA4) which then decodes
AB3-AB4. (The I/O AACK/ signal also drives the
CPU READY input high.) Assuming AB8-ABF are
false, AB3-AB7 are decoded to generate the following
chip select signals:
Bits
7 6 543
1
1
1
1
1 000
1 o0 1
1 010
1 o 1 1
Addresses*
Chip Select
Signal
CO, C2, C4, C6
C8, CA, CC, CE
00,02,04,06
08, OA, DC, OE
8259CS/
8255CS/
8253CS/
8251CSI
*Odd addresses (i.e., C1, C3, ... 00) are invalid.
The 10 AACK/ signal is driven through A32-8 and
A6-8 (6ZD4), respectively, to develop PROM 10 EN/
and ON BD ADR/. PROM 10 EN/enables Data
Buffer A44/45 (4ZD3) and ON BD ADR/ inhibits the
Bus Arbiter A82 and Bus Command Decoder
A83. The DT IR output of Status Decoder A8I is
inverted (A20-I2, 4ZC6) to select the proper direction
of data transfer through the Data Buffer.
After the proper I/O device is enabled, the specific
function for the device is selected by address bits
ABI-AB2 and the 10RC/ or 10WC/ output of Status
Decoder A8I.
4-29. SYSTEM 1/0 OPERATION. Address bits
AB3-ABF are decoded by the I/O Address Decoder
as described in paragraph 4-28. If the address is not
for an on-board I/O device, the ON BD ADR/ signal
is false (high) and enables the Bus Arbiter A82
(3ZD4) and Bus Command Decoder A83 (3ZC4). The
Bus Arbiter and Bus Command Decoder, which are
clocked by the 5-MHz clock to latch in and decode
status signals S0-82, then acquire Control of the
Multibus interface as described in paragraph 4-26.
4-27.110 OPERATION
4-30. ROMIEPROM OPERATION
The following paragraphs describe on-board and
system I/O operations. The actual functions performed by specific read and write commands to onboard 110 devices are described in Chapter 3.
The four ROM/EPROM chips are installed by the
user in IC sockets A28/29/ 46/ 47 (6ZC3). The
ROM/EPROM addresses are assigned from the top
down in the I-megabyte address space; the bottom
4-12
iSBC 86/12A
Principles of Operation
address is determined by the user configuration of
chips as follows:
ROM
EPROM
Address Block
-
2758
2316E
2716
2732
FFOOo-FFFFF
FEOOo-FFFFF
2332A
FCOOo-FFFF
Jumper posts E94 through E99 and switch Sl must be
properly configured to accommodate the type of
ROM/EPROM installed. (Refer to table 2-4.)
IC sockets A29 and A47 accommodate the top of
ROM/EPROM; IC sockets A28 and A46 accommodate the ROM/EPROM space directly below that
installed in A29 and A47. The low-order bytes (bits
DBO-DB7) are installed in A29 and A28; the highorder bytes (bits DB8-DBF) are installed in A47 and
A46.
When ADV 10 ADR is false, a custom ROM A68
(6ZC6) decodes address bits ABB-AB12. If the
address is within the limit specified, the 04 and 03
output pins will be low and the 02 and 01 output pins
will depend on whether the address is in the upper
half or lower half of the address block. For instance,
if 2758 EPROM chips are installed and the address is
in the range FFOOO-FF7FF, the 02 and 01 pins will be
high and low, respectively; if the address is in the
range FF800-FFFFF, the 02 and 01 pins will both be
high. The 04 and 03 output pins are compared with
address bit AB13. If AB13 is high, the PROM
AACK/ signal is asserted; if AB13 is low, the ON BD
RAM RQT / signal is asserted.
and E96 and between E97 and E99 to accommodate
the additional ROM/EPROM installed. In addition,
switch positions 7 and 8 of Sl must be off. (Refer to
table 2-4.)
IC sockets A29, A47, A3, and AS accommodate the
top half of the installed ROM/EPROM; IC sockets
AI, A2, A4, and A5 accommodate the lower half of
the installed ROM/EPROM. The low-order bytes
(bits DBO-DB7) are installed in IC sockets AI, A2, A3,
and A29; the high-order bytes (bits DB8-DBF) are
installed in IC sockets A4, A5, A6, and A47.
When ADV 10 AD DR is false, a custom ROM (A68,
6ZB6) decodes address bits ABB-AB12 and switch Sl
positions 7 and 8. If the address is within F8000FFFFF, the 04 and 03 output pins will be low and the
02 and 01 output pins will change according to the
address. Table 4-1 lists 01, 02 states and the chips
selected for the various address blocks. The 04 and
03 output pins are compared with address bit
AB13. If AB13 is high, the PROM AACK/ signal is
asserted; if AIH3 is low, the ON BD RAM RQT/
signal is asserted.
When ALE goes false, Decoder A18 (6ZC4) is enabled
and decodes the inputs presented by the 02 and 01
outputs of A68. For example, if 02/01 = 00, PCSO/ is
asserted and enables Al andA4;if02/01 =11,PCS3/
is asserted and enables A29 and A47. Each chip of
the selected pair of chips are individually addressed
by AB1-ABC. Thus when the associated enable
signal is asserted, the contents of the address
specified by ABI-ABC are transformed to the CPU
Data Buffer A44/45.
4-32. RAM OPERATION
When ALE goes false, Decoder A18 (6ZC4) is enabled
and decodes the inputs presented by the 02 and 01
output of A68. If 02/01 = 10, PCS2/ is asserted and
enables A28 and A46; if 02 and 01 = 11, PCS3/ is
asserted and enables A29 and A47. Each chip of the
selected pair of chips are individually addressed by
AB1-ABC. Thus: when the associated enable signal
(PCS2/ or PCS3/) is asserted, the contents of the
address specified by AB1-ABCaretransformed to the
CPU via Data Buffer A44/45.
4-31. ROM/EPROM OPERATION WITH iSBC
340 MULTIMODULE EPROM. The eight ROM/EPROM chips are installed, by the user, in 10 sockets
A29/A47 / A1/A2/A3/A4/A5/A6. (ROM/EPROM
IC sockets A1-A6 are located on the iSBC 340
Multimodule EPROM board. Refer to Appendix
B.) The ROM/EPROM addresses are assigned from
the top down in the I-megabyte address space. The
bottom address is F8000 and extends upward to
FFFFF. A jumper must be placed between posts E94
As described in paragraph 4-23, the Dual Port
Control Logic allows the on-board RAM facilities to
be shared by the 8086 CPU and another bus master
via the Multibus interface. The following
paragraphs describe the RAM Controller, RAM chip
arrays, and the overall operation of how the RAM is
addressed for read/write operation.
4-33. RAM CONTROLLER. All address and
control inputs to the on-board RAM are supplied by
RAM Controller A 70 (10ZC6). The RAM Controller
automatically provides a 128-cycle RAS refresh
timing cycle to the dynamic RAM composed of RAM
chips A 72-79 and A92-99.
The RAM Controller, when enabled by a low input to
its PCS/ pin, multiplexes the address to the RAM
chips. Low-order address bits AO-A6 are presented at
the RAM address lines and RAS/ is driv~n low at the
beginning of the first memory clock cycle. Highorder address bits A 7-A13 are presented at the RAM
4-13
iSBC 86/12A
Principles of Operation
Table 4-1. ROM/EPROM Chip Selection
PROM
Address
02
01
Chip Select
Signal
IC Chips
Selected
F800Q-F9FFF
0
0
PCSOI
A1,A4
IC chips A 1 and A4 are selected by
PCSOI through connector J3-1 (figure
5-2,6ZA2).
FAOOO-FBFFF
0
1
PCS11
A2,A5
IC chips A2 and A5 are selected by
PCS11 through connector J3-2 (figure
5-2,62B2).
FCOOO-FDFFF
1
0
PCS21
A3,A6
IC chips A3 and A6 are selected by
PCS21 through IC pins 18 and 20 of A46
(figure 5-2, 62B3).
FEOOO-FFFFF
1
1
PCS31
A29,A47
IC chips A29 and A47 are selected by
PCS31 through IC pins 18 and 20 of A47
(figure 5-2, 62B3).
address lines and CASI is driven low during the
second memory clock cycle. The RAM Controller
drives its WEI output pin according to whether the
CPU instruction is a read or write. For a write
operation, the DP WTI input is low to the RAM
Controller, in which case the WEI output is driven
low. For a read operation, the DPRDI input is low
and the WEI output remains high. When the
memory cycle (read or write) starts, the RAM
Controller drives its SACKI output low; when the
memory cycle is complete, it drives its XACKI output
low. The SACKI and XACKI go high when theRDI
or WRI input goes high.
4-34. RAM CHIPS. Even bytes of data are stored
in A 72-A79 and odd bytes of data are stored in
A92-A99. The WEI input pin to A72-A79 is controlled by ANDing the RAM Controller WEI output
and memory address bit AMO. The WEI input pin to
A92-A99 is controlled by ANDing the RAM Controller WEI output, AMO, and MBHEN I (Memory Byte
High Enable).
4-35. RAM CONTROLLER WITH iSBC 300
MULTIMODULE RAM. All address and control
inputs to the onboard RAM are supplied by RAM
Controller AI. (RAM IC sockets AI-AI9 are located
on the iSBC 300 Multimodule RAM board. Refer to
Appendix B). The RAM Controller automatically
provides a 128-cycle RAS refresh timing cycle to the
dynamic RAM composed of RAM chips A 72-A79,
A92-A99, A3-AIO, and AI2-AI9.
The RAM Controller when enabled by a low input to
its PCSI pin, multiplexes the address to the RAM
chips. Low-order address bits AO-A6 are presented at
the RAM address lines and RASI is driven low at the
beginning of the first memory clock cycle. Highorder address bits A 7-A13 are presented at the RAM
address lines and CASI is driven low during the
4-14
Description
second memory cycle clock. The RAM Controller
drives its WEI output pin according to whether the
CPU instruction is a read or write. For a write
operation, the DP WTI input is low to the RAM
Controller, in which case the WEI output is driven
low. For a read operation, the DPRDI input is low
and the WEI output remains high. When the
memory cycle (read or write) starts, the RAM
Controller drives its SACKI output low; when the
memory cycle is complete, it drives its XACKI output
low. The SACKI and XACKI go high when the RDI
or WRI input goes high.
4-36. RAM CHIPS WITH iSBC 300 MULTIMODULE RAM. Even bytes of data are stored in
A72-A79 and A3-AIO and odd bytes are stored in
A92-A99 and AI2-AI9. The WEll signal to A 72A 79, A3-AIO is developed by ANDing the RAM
Controller WEI output with memory address bit
AMO. The WE21 signal to A92-A99, A12-A19 is
developed by ANDing the RAM Controller WEI
output, AMO, and MBHEN I (Memory Byte High
Enable).
4-37. ON-BOARD READ/WRITE OPERATION. When the 04 output of A68 (6ZC6) and
address bit ABl3 are both low, the output of A53-6
(6ZD5) goes low and asserts the ON BD RAM RQTI
signal. When ON BD RAM RQTI goes low, A52-3
(1IZA3) is enabled and generates ON BD CMD ENI
to generate RAM CS via A52-11 and to gate DPRDI
or DPWT I to the RAM Controller. (See figure
4-8.) The RAM Controller then multiplexes the
address to RAM and, depending on which input
command is true (DPRDI or DPWT I), drives its WEI
output high or low. (The WEI output is driven low for
a write; it remains high for a read.) The SACKI and
XACKI signals are generated by the RAM Controller
as described in paragraph 4-33. The CPU completes
the read or write operation when XACKI is asserted.
Principles of Operation
iSBC 86/12A
During the CPU access of on-board RAM, the
Address Bus Drivers and Data Bus Drivers are
disabled and the Address Buffer and Data Buffer are
enabled.
4-38. BUSREAD/WRITEOPERATION. When
another bus master has control of the Multibus
interface, that bus master can address the iSBC
86/l2A board as a slave RAM device. The bus master
first places the address on the Multibus interface and
then asserts MRDCI or MWTC/. Address bits
ADRDI-ADRIOI and switch Sl present a 10-bit
address to a special ROM (A67) (3ZB5); address bits
ADRll/-ADR131 are decoded by A66 (3ZB6). The
switch settings of Sl represent the base address and
memory bus size; the 01-03 outputs of A67 are
ATRDI-ATRF/, which are multiplexed by A86
(5ZC4) into memory address bits AMD-AMF when
the SLAVE MODEl signal is subsequently activated
by the Dual Port Control Logic. The 04 output of A67
is driven through A23-4 (when the l28K byte
matches) to develop the OFF BD RAM ADR RQT
signal, which is applied to the Dual Port Control
Logic, If no CPU access is in progress, the Dual Port
Control Logic then enters the slave mode and, when
A49-l0 (11ZC6) goes low, develops the RAM CS and
SLAVE CMD EN I signals. RAM CS enables RAM
Controller A 70 (10ZC6) and SLAVE CMD EN I gates
DPRDI or DPWTI (3ZA6) to the RAM Controller.
The RAM Controller then multiplexes the address to
RAM and, depending on which input command is
true (DPRDI or DPWT I), drives its WEI output high
or low. (The WEI output is driven low for a write; it
remains high for a read.) The SACKI and XACKI
signals are generated by the RAM Controller as
described in paragraph 4-33. The CPU completes the
read or write operation when XACKI is asserted.
During the Multibus interface access of on-board
RAM, the SLAVE MODEl signal enables the
Address Bus Drivers (A86/87/88); the ON BD ADRI
signal is false and enables the Data Bus Drivers
(A69/89).
4-39. BYTE OPERATION. For Multibus interface operation, the on-board RAM is organized as two
8-bit data banks; all even byte data is in one bank
(DATOI-DAT7 I) and all odd byte data is in the other
bank (DAT8/-DATF/). Refer to figure 3-1 which
shows the data path for Multibus interface operation
by 8-bit and l6-bit bus masters.
All word operations must occur on an even byte
address boundary with BHENI asserted (low). Byte
operations can occur in one of two ways:
a. The even bank can be accessed by controlling
ADROI, which places the data on the DATOIDAT7 I lines. (Refer to figure 3-lA.)
b. To access the odd bank, wbich is normally placed
on DAT8/-DATF/, the data path shown in figure
3-lB is implemented. This requires that BHEN
be false (high) and ADROI be low.
These operations permit the access of both bytes of
the l6-bit data word by controlling ADROI. In other
words, ADROI specifies a unique byte and is not a
part of a l6-bit word operation.
Shown below are the states ofBHEN I and ADROI for
8-bit and l6-bit operations and the effects on
transceiver control and memory block chip select.
Bus Control
Lines
BHENI ADROI
1
1
a
1
a
1
Data Bus Driver
Chip Select
A69
A89
A90
On
Off
On
On*
Off
On
Off
On
Off
Memory Block
Chip Select
A72-A79 A92-A99
Yes
No
No
Yes
Yes
Yes
*don't care condition
4-40. INTERRUPT OPERATION
The 8259A PIC can support both bus vectored (BV)
and non-bus vectored (NBV) interrupts. For both BV
and NBV interrupts, the on-board PIC (A24) (8ZB5)
serves as the master PIC. (Refer to paragraph 2-14.)
The master PIC drives the CPU INTR input high to
initiate an interrupt request and the CPU then enters
the interrupt timing cycle in which two INTA cycles
occur back-to-back. The NBV and BV interrupts are
described in the following paragraphs.
NOTE
The iSBC 86/l2A board must be capable of
Multibus interface access when using interrupts.
4-41. NBV INTERRUPT. Assume that a NBV
interrupt is initiated by an on-board function driving
the IR5 line high to the on-board PIC; if no higher
interrupt is in progress, the PIC then drives the CPU
INTR input high. Assuming that the NMI interrupt
is inactive and that the CPU interrupt enable flip-flop
is set, the CPU suspends the current operation and
proceeds with the first of two back-to-back INTA
cycles. (Refer to figure 4-6 for signals activated
during the first and subsequent INTA cycle.)
The Bus Arbiter A82 (3ZD4) acquires control of the
Multibus interface and the MCE signal from the
Status Decoder A81 (3ZB4) drives the LOCKI signal
low to ensure Multibus interface control until the
second INTA cycle is complete. The Bus Command·
Decoder A83 (3ZC4) drives the INTAI signal low. On
4-15
Principles of Operation
receipt of the first INTAI signal, the master PIC
freezes the internal state of its priority resolution
logic. The first INTAI signal also sets flip-flop A63-5
(8ZA2), which generates the 1st INTA ACKI signal to
drive the CPU READY input high.
The CPU then proceeds with the second INTA
cycle. On receipt of the second INTAI signal, the
master PIC places an 8-bit identifier for IR5 on the
data bus, and drives its DENI output low. The
resultant LOCAL INTA DENI signal enables Data
Buffer A44/45 and drives the CPU READY input
high. (The second INTAI signal clears flip-flop
A63-5.) The CPU then inputs the 8-bit identifier and
terminates the interrupt timing cycle.
The CPU multiplies the 8-bit identifier by four to
derive the restart address of the interrupting
device. After the service routine is completed, the
CPU automatically resets all its affected flags and
returns to the main program.
4-42. BV INTERRUPT. As far as the CPU is
concerned, BV interrupts are handled exactly the
same as NBV interrupts. Assume that the IR6line to
the master PIC is driven by a slave PIC on the
Multibus interface. When IR6 goes high, the master
PIC drives the CPU INTR input high as previously
4-16
iSBC 86/12A
described. On receipt of the first INTAI signal, the
master PIC generates BUS INTA DEN I via its DEN I
output and places the interrupt address code for IR6
on its CO-C2 pins; since QMCEI is enabled by the
MCE output of the Status Decoder, the CO-C2 is
transferred to the Address Latch via address lines
AD8-ADA. (These bits are latched when the ALE
signal goes false.) The BUS INTA DENI signal
enables the Data Bus Driver in preparation to receive
the 8-bit identifier from the slave PIC. (The interrupt
address code is now on Multibus interface address
lines ADRBI-ADRA/.)
The first INTAI signal sets flip-flop A63-5 to drive
the CPU READY input high. The CPU then proceeds
with the second INTA cycle. When the second
INTAI signal is driven onto the Multibus interface
and the slave PIC recognizes its address, it outputs an
8-bit identifier onto the DATO/-DAT7 I lines and
drives the Multibus interface XACKI line low. (The
second INTAI also toggles and clears flip-flop
A63-5.) The CPU then inputs the 8-bit identifier and
terminates the interrupt timing cycle.
The CPU multiplies the 8-bit identifier by four to
derive the restart address of the interrupting
device. After the service routine is completed, the
CPU automatically resets all its affected flags and
returns to the main program.
CHAPTER 51
SERVICE INFORMATION I
5-1. INTRODUCTION
5-4. SERVICE AND REPAIR
ASSISTANCE
This chapter provides a list of replaceable parts,
service diagrams, and service and repair assistance
instructions for the iSBC 86/12A Single Board
Computer.
5-2. REPLACEABLE PARTS
United States customers can obtain service and
repair assistance from Intel by contacting the MCSD
Technical Support Center in Santa Clara, California
at one of the following numbers:
Telephone:
Table 5-1 provides a list of replaceable parts for the
iSBC 86/12A board. Table 5-2 identifies and locates
the manufacturers specified in the MFR CODE
column in table 5-1. Intel parts that are available on
the open market are listed in the MFR CODE column
as "COML"; every effort should be made to procure
these parts from a local (commercial) distributor.
5-3. SERVICE DIAGRAMS
The iSBC 86/12A board parts location diagram and
schematic diagram are provided in figures 5-1 and
5-2, respectively. On the schematic diagram, a
signal mnemonic that ends with a slash (e.g., IOWC/)
is active low. Conversely, a signal mnemonic
without a slash (e.g., INTR) is active high.
From Alaska or Hawaii call(408) 987-8080
From locations within California call toll free(800) 672-3507
From all other U.S. locations call toll free(800) 538-8014
TWX: 910-338-0029 or 910-338-0255
TELEX: 34-6372
Table 5-1. Replaceable Parts
Description
Reference Designation
A1,37,62
A2,21,53
A3,7
A4,49
A5
A6,51
A8,9
A14
A15
A16
A17,80
A18,54
A19,32
A20,34
A22,59
A23
A24
A25
A26
A27
A30,57
A3, ,33,43,52
A35,84,85
A36
A38
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
IC,
Ie,
IC,
IC,
IC,
74125, Quad Bus Buffer (3-state)
74S32, Quad 2-lnput Positive-OR Gate
74S10, Triple 3-lnput Positive-NAND Gate
74S175, Hex Quad D-Type Flip-Flop
9602, Dual One-Shot Multivibrator
74S11, Triple 3-lnput Positive-AND Gate
Intel 8226, 4-Bit Bidirectional Bus Driver
75189, Quad Line Receivers
75188, Quad Line Drivers
74163, Sync 4-Bit Counter
Intel 8224, Clock Generator and Driver
74S139, Decoder/Multiplexer
74S08, Quad 2-lnput Positive-AND Gate
74S04, Hex Inverters
7432, Quad 2-lnput Positive-OR Gate
74S02, Quad 2-lnput Positive-NOR Gate
Intel 8259A, Programmable Interrupt Controller
Intel 8255A, Programmable Peripheral Interface
Intel 8253, Programmable Interval Timer
Intel 8251A, Programmable Comm. Interface
74LS75, 4-Bit Bistable Latch
14800, Quad 2-lnput Positive-NAND Gate
74LS04, Hex Inverters
74LSOO, Quad 2-lnput Positive-NAND Gate
Intel 8284, 18-Pin Clock Generator
Mfr. Part No.
Mfr.
Code
SN74125
SN74S32
SN74S10
SN74S175
9602PC
SN74S11
8226
SN75189
SN75188
SN74163
8224
SN74S139
SN74S08
SN74S04
SN7432
SN74S02
8259A
8255A
8253
8251A
SN74LS75
SN14S00
SN74LS04
SN74LSOO
8284L
TI
TI
TI
TI
FAIR
TI
COML
TI
TI
TI
COML
TI
TI
TI
TI
TI
COML
COML
COML
COML
TI
Ti
TI
TI
COML
Qty.
3
3
2
2
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
4
3
1
1
5-1
Service Information
iSBC 86/12A
Table 5-1. Replaceable Parts (Continued)
Description
Reference Designation
Mfr. Part No.
Mfr.
Code
Oty.
A39'
A40,41, 71,91
A42,44,45,58,60,61
A48
A50,63
A55
A56
A64
A65
A66
A67
A68
A69,87-90
A70
A72-79,92-99
A81,83
A82
A86
IC, Intel 8086, 16-Bit Microprocessor
IC, 74S373, Octal D-Type Latches
IC, Intel 8286, 8-Bit Non-Inverting Transceiver
IC, 7438, Quad 1-lnput Positive-NAND Gate
IC, 74S74, Dual D-type Edge-Triggered Flip-Flop
IC,74S30, 8-lnput Positive-NAND Gate
IC, 7425, Dual 4-lnput Positive-NOR Gate w/Strobe
IC,74S140, Dual 4-lnput Positive-NAND Gate
IC, 8097, 3-State Hex Buffers
IC, 74LS138
IC, PROM, Address Decoder
IC, PROM, Address Decoder
IC, Intel 8287, 8-Bit Inverting Transceiver
IC, Intel 8202, Dynamic RAM Controller
IC, Intel 2117-4, Dynamic RAM
IC, Intel 8288, Bus Controller for 8086
IC, Intel 8289, Bus Arbiter for 8086
IC, 74S240, Octal Buffer/Line Driver/Line Receiver
8086
SN74S373
8286
SN7438
SN74S74
SN74S30
SN7425
SN74S140
DM8097
SN74LS138
INTEL
INTEL
8287
8202
2117-4
8288
8289
SN74S240
COML
TI
COML
TI
TI
TI
TI
TI
NAT
TI
9100134
9100129
COML
COML
COML
COML
INTEL
TI
1
4
6
1
2
1
1
1
1
1
1
1
5
1
16
2
1
1
CR1,2
C1 ,2,4-11,13,15-19,
21-25,28-51,65-75,91
C3
C12, 27,64
C20,98·
C26
C92
C52,54,55,57,58,60,61
63,76,78,79,81,82,
84,85,87
C53,56,59,62, 77 ,80,
83,86
C88-90,93-97
Diode, 1N914B
Cap., mono, 0.1I-'F, +80 -20%, 50V,
Low Profile
Cap., mono, 1.0I-'F, ±10%, 50V
Cap., mica, 1.0pF, ±5%, SOOV
Cap., mono, 0.OO1I-'F, ±20%, 50V
Cap., tant, 10I-'F, ±10%, 20V
Cap., mono, 0.33I-'F, +80 -20%, 50V
Cap., mono, 0.047I-'F, +80 -20%, 50V,
Low Profile
OBD
aBO
COML
COML
2
57
OBD
OBD
aBO
OBD
aBO
OBD
COML
COML
COML
COML
COML
COML
1
3
2
1
1
16
Cap., mono, 0.01I-'F, +80 -20%, 50V
OBD
COML
8
Cap., tant, 221-'F, ±10%, 15V
OBD
COML
8
RP1
RP2
RP3
RP4
R1 ,11 ,16,17
R2,22
R3-5,13,20
R7,8, 10, 14, 18, 19,21,23
R9
R12
R15
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
Res.,
aBO
OBD
aBO
OBD
aBO
aBO
aBO
aBO
aBO
OBD
aBO
COML
COML
COML
COML
COML
COML
COML
COML
COML
COML
COML
1
1
1
1
4
2
5
8
1
1
1
S1
Switch, 8-position, DIP
206-8
CTS
1
VR1
Voltage regulator
MC79L05AC
MOT
1
XA8,9
XA10-13
XA28,46
XA39,70
XA67,68
XA71,91
Socket,
Socket,
Socket,
Socket,
Socket,
Socket,
C-93-16-02
C-93-14-02
C-93-24-02
540-A37D
C-93-18-02
C-93-20-02
TI
TI
TI
AUG
TI
TI
2
4
4
2
2
2
Y1
Y2
Y3
Crystal, 22.1184-MHz, fundamental
Crystal, 15-MHz, fundamental
Crystal, 18.432-MHz, fundamental
Extractor, Card
Post, Wire Wrap
Plug, Shorting, 2-position
OBD
OBD
aBO
S-203
89531-6
530153-1
CTS
CTS
CTS
SCA
AMP
AMP
1
1
1
2
139
2
5-2
pack, 8-pin, 1K, ±5%, 2W PP
pack, 14-pin, 1K, ±2%, 1.5W PP
pack, 16-pin, 10K, ±5%, 2W PP
pack, 6-pin, 2.2K, ±5%, 1W PP
fxd, comp, 10K, ±5%, V4W
fxd, comp, 20K, ±5%, V4W
fxd, comp, 5.1 K, ±5%, V4W
fxd, comp, 1K, 5%, V4W
fxd, comp, 100K, 5%, V4W
fxd, comp, 330 ohm, ±5%, V4W
fxd, comp, 270 ohm, ±5%, V4W
16-pin,
14-pin,
24-pin,
40-pin,
18-pin,
20-pin,
DIP
DIP
DIP
DIP
DIP
DIP
Service Information
iSBC 86/12A
Always contact the MCSD Technical Support Center
before returning a product to Int-el for service or
repair. You will be given a "Repair Authorization
Number", shipping instructions, and other important information which will help Intel provide you
with fast, efficient service. If the product is being
returned because of damage sustained during
shipment, or if the product is out of warranty, a
purchase order is necessary in order for the MCSD
Technical Support Center to initiate the repair.
equivalent) manufactured by the Sealed Air Corporation, Ha\\rthorne, N.J., and enclose in a heavy-duty
corrugated shipping carton. Seal the carton securely,
mark it "FRAGILE" to ensure careful handling, and
ship it to the address specified by MCSD Technical
Support Center personnel.
In preparing the product for shipment to the MCSD
Technical Support Center, use the original factory
packaging material, if possible. If the original
packaging is not available, wrap the product in a
cushioning material such as Air Cap TH-240 (or
Customers outside of the United States
should contact their sales source (Intel Sales
Office or Authorized Intel Distributor) for
directions on obtaining service or repair
assistance.
NOTE
Table 5-2. List of Manufacturers' Codes
Mfr. Code
I
Manufacturer
Address
II
Mfr. Code
I Manufacturer
Address
AMP
AMP, Inc.
Harrisburg, PA
MOT
Motorola
Semiconductor
Phoenix, AZ
AUG
Augat, Inc.
Attleboro, MA
NAT
National
Semiconductor
Santa Clara, CA
CTS
CTS Corp.
Elkhart, IN
SCA
Scanbe, Inc.
EI Monte, CA
FAIR
Fairchild
Semiconductor
Mt. View, CA
TI
Texas Instruments
Dallas, TX
INTEL
Intel Corp.
Santa Clara, CA
COML
Available from any commercial source.
Order by Description (OBD)
5-3/5-4
iSBC 86/12A
8
7
THIS DRAWING CONTAINS INFORMATION
WHICH IS THE PROPRIETARY PROPERTY
OF INTEL CORPORATION. THIS DRAWING
IS RECEIVED IN CONFIDENCE AND ITS
CONTENTS MAY NOT BE DISCLOSED WITH·
OUT THE PRIOR WRITIEN CONSENT OF
INTEL CORPORATION
s
6
Service Information
4
J
DWG NO 'I
lONE
rZPW:ES
REV
r4PLACE':>
DESCRIPTION
B
Dek! IVO;-.-4-~-o~to~----h:n,..-+-iiii
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D
SEE ECOLJ-1285
A..
r2.PlACES
DO 30 5 2.
o
o
c
c
B
B
7
NOTES: UNLESS OTHERWISE SPECIFIED
I.
c... ~~E~~gE.~\~t-J_~~~?~E~~'NI\~. ~:p~T~
ASS"- P ....~T "-la. IS I00305~-04 n:.1<;, ~C.WI~b};!>.eT<;' LI':::.T
'INlet:. LIST A.'2£ TIZ.~C."-II.lG DD..N~I-lIP
PE.e
FO~
99-0007-001.
MIl.I(:I:: LA,,;:)T Foue DIGIT5 OF P....~T "-lO. DA~ MO, ZA. (P~DlJC.T ND.) ~ REV LEVEl..
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W~EIZ.G: ~140W"-l.
APPIZO'J(
DESCRIPTION
ClAR.Il',(.
PARTS LIST
0I-\OLE:.S "TO Bt ~><.E ITEM~""2... O~ -=::.0'-\:)6:'< ~\be..
C$="?v-.Ip.., r:..-. l.D~"",,\O~ i::>....-a.{~ Il>oo..~PQO'X.
wl-\~E c::,~~~. L.~a,-t--'\\,)"S:.\ \...lO"T
\ouc.~ \.c.. c:R.';:<.'C~""=>"TO~?",,~.
3065 BOWERS AVE.
SANTA CLARA
CALIF 95C51
ffi=-......,.,,;-.-;,~'--';~+-=:-"'-'-''-L:TlTlE PRINTED WIRING ASSEMBLY
[SBC ofo/12A.
LA"'!' Cc.PAC.ITOeS C35,~~\40~ as OOWI-J OIJ PWf:J
TO t::>. M~'" I-IE..\6\-\'T OF .200 1"1<.1-1.
9300021
8
7
SIZE
6
•
I
A
I
CODE
D OMS
SCALE2:1
4
1
I
I
SHEET
I
OF
I
1
Figure 5-1. iSBC 86/12A Parts Location Diagram
5-5/5-6
is]
7
8
5
6
THIS DRAWING CONTAINS INfORIIo\TION
WHICH IS THE PIIQPRIEJMY PACI'ER1Y
Of'
IN"lB. CORPCIIATIOIC.
ntiS CMWIl«i
IS RECEJYEI)
IN COIIFlDEIICE
_
I1S
CONTENTS MAY Hal" IE DISCLOSED WITIf.
OUT TIE PRIOR ~ COIISENT Of'
INTEL CCRl'CRATICIN.
f
1
'N3
Ip\-7~ ~-~---------------..-----~o_------.......- - - - - t - - - r
I----<;~
~
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+- f~~I,-",- V
CC?>
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t
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JPI-7
1
9 \-8
0,
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WiD
Option
W1
W2
W3
W4
W5
W6
A-B
A-B
A-B
A-B
A-B
A-B
N/A
N/A
N/A
E63-E64
Open
+,2.
When installed enables common
ground between chassis.
f>... -
'"
W4
B
L--.-~
7~L,,",S.
I~ I V\vRE<=')
...LC~2
'T'.~
jb~
t"
IK
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+
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B
w?
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... ':>v
22
l
IO!za
+
:
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W2.
p....
':-ID'I'o/5V
PI- fD
-+Sv
} See table 2-4
-=-
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I
Jumpers
Factory Default
II-=-~11)37)A.l
+lc,::>
T,7~o/OlISV
...L-
~., ~, ~, lr~'
cae 1 +
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I
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Jumpers
-17...'1
T-· 1
+'SvA.UX
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i
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22
1"'0,",'5'
T
lCI,zA-B
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1w~-7L
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A- I
PI-Z
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10
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C98
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SPECIFIE.D
A..lL 'RE.~\~T~E. V~UE.'S f>.S-I~
'SEE "'''''BLE'::> '2 M.l1Y~ FOR PI.,
OUT TIlE PRIOR WNTTEII CONSENT OF
IN1D. alRJIQRATION.
D
A..I~
~
-
A.S'" 742"=>
A..4,40;) 74::-175
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TP-BLE I: JjOA.DDR
741(,,3'
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I
74S24~ I
e
1(0
7
14
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20
10
-
-
-
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c
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I
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TABLE. 2: ?ROM ~.U..CT
JPI-7
l?1-8
!PROt"'\TYPE IA.'DR FROM I
2.7S5
271(0
FFOOO
FE. 000
2'7~Z.
FCOOO
''''-.'''.:.,"7
:74510
7
14
i
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I
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'·.:Z..=. 74S0Z! 7
14
Option
~,~I
7"10
'·. :Z.:'
c
} See table 2-4
installed enables common
'ound between chassis.
74LSI=ei
P2
NOTE.~: IJNlE:.'5~ OTI-'.E.:RWI~E.
I.
2.
A
~
(.98
E 152.
SPECIFlE.D
Po.lL I<.E::>I~T~E. VI'o.LUE.'E. ~e. lli OW,Mc;,.J 1: ':>'7'0,1/4 VA,"".
t>..LL c.,c...\-liC:>,(,..IT~E. V{:>"LUE.':::. f>.RE. '!.N f'<\\C.t<0\='j:>.~sJ ...50%j-20%J SOVDC..
SEE ,,a..,BLE':::. '2 AN'D3 FOR
SEE. II"'-'BLE I 1="0'12
!.Io
C.14
IK
RPI
IK
RPZ
10K
RP3
2.2K
RP4
7
14
7 _+-.-:1-,-4_+-_-_--+:__
-_-+:_=__'
7
\4
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-'
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74~'2.
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N/A
N/A
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6'289
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10
20
4
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8
I
7
I
6
I
5
4
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3
D
1
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I
2.
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CODE
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i
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I SHEET
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I
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OF
II
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 1 of 11)
5-7/5-8
I
8
I '!'!!!S DRAWING COI!TAlHS !!!I'ORIMTIOI! I
5
6
WHICH IS THE PROPRIETARY PROPERlY
OF INTEL CORPORATION. THIS DRAWING
IS RECEJYED IN COfIFIDEHCE AND ITS
COHTEHTS !lAY NOT BE DlSCUISED WlTHOUT THE PRIOR WRITTEN OOIISENT OF
INTEL CORPORATION.
.. 1vl1-------4! h1fo~'
ALE
D
PI-14
~(:,-_ _ _""",,,,,,,,,,,,,,,,,,,,,,,,,",,",,",....,,,.,,.......!.,,..=,""""""""""''''''''''''''''''''''''''''''''........................_ _
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Cf< Z.
~9
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10
17 500V
X'A.LI
10
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ICOK
!l1I1!1I1I1I1I__~--------------~~r.-~---J~~11 RS~
+
14 E.FI
Jumpers
R~i~l~O____~_~~_~
I
.
Jumpers
Factory Default
E3-E4
E5-E6
E92-E93
E132-E133
Open
Installed
Installed
Open
10
15
IG%
it>-t-IK
2.0V-=7
BUS P..:'DE.Nj [EJ1----------+';)~v--=~------~AEN2.
13 F/C
:, AENI
Option
See table 2-4
See table 2-4
N/A
Install to allow use of AACK/
from Multibus interface.
5\-1~
AN:..K/ ~
II
I
mm,
'II
ADO-ADF
Address Bits O-F
ADV 10 ADR
Advance Input/Output Address
AUX RESET
Auxiliary Reset
BHE
Byte High Enable
ClK
Clock
INIT
Initialize
lOCK
lock
RESET
Reset
so
Status Bit one
S2
Status Bit two
SYS CLOCK
System Clock
T21
Timing Pulse 21
TIME OUT INTR
Time Out Interrupt
w
,--_-"'-I RDY2
I
.
74L'::>7S
- II
Qp
6.1
1
~G.
I
5\-\ '\ 1
ON 'blYR.c>-.M AC. \(/
SHe.,
51-1 B
1
SH (0
'51-\ 10
SHE:>
IO AJ>...c.K./
INT,o... ,o...c.K./
ST
PROM AP-L'4
TIME OUI/
LOCt>-.L INTP-.DE.N/
B
51-\3
ALE/
I
4~~(.p
I
I I
~
'BD
~!2
74
1
IK.
E4
E3
EiD
~E5
4
~
4
Co
~ AU> •
I"" 74'=>11
~
'aT
1
5
(p
4
.
1~
CC'K
CLR
ZQ 7
::,r) 12
74~17S
3Q
BP
BN
TE'5>i/
CP-.
0:'~
74S~
3Q ..l.L"1Q ~
4Q ~
01)
iQ
f-lMI
~8
4D ~
IQ
INTR
10
2.Q ~
2D
SI4Sl
747:,~v
S
~
Sf.\B
2...1""'~
I~
~
4 -
S\-\5
1~3
~0
I[
Status Bit zero
S1
12.
4 ROY I
1
Address Bus 0-13
E132.
52.B4-
Glossary
ABQ-AB13
EI3>3
XACK/
c
..
RI7
10K
f---*---O
".0
eLK ...CK/
1ST INT!".. !"..C.K/
5H 0
5\-\10
5H5
AB2
5H 5,(0
PRO"'" AALK/
TIME QUI/
LO(.t>-L INl"P-..DEN/
B
51-\3
ALE/
5
t9
1-________iiCll ell..DV IO A..DI2
S\·H"
74L"::>7'::>
iQ~
~~
Q~
S2./
51-\~
'e,\-\E/ SI-\S
LOC.K.! ::'H~
S(/)/ ""H~
SI/
A
S.J,~
A
L----------------------------------r-+-----------------~I T\MEOUTr~,RlskB
L------------------------------------------------------~_r-------------------------~/J~.,
T21
L--------------------------------------------------------------~--r_--------------------------~J~ T21/ S~3
REV
8
8
7
6
5
:;
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 2 of 11)
5-9/5-10
iSH
Jumpers
I
Jumpers
Factory Default
Option
E107-E108
E112 through E128
E129-E130-E131
E143-E144-E145
E151-E152
W7 A-B-C
Open
E125-E126
E129-E130
E144-E143
Installed
A-C
..
None
Install to use AACK
See figure 2-1
See table 2-13
See table 2-13
See paragraph 2-24
N/A
See figure 2-1
--.~,
I
8
I IIJI!f!CIl
THIS DRAWING CONTAINS INfORIIATlOfI I
IS !HE !'!lOPRIEl'ARY PROPERlY I
Advance Acknowledge
ADV MEM WRT
Advance Memory Write
ALE
7
6
5
*
OF INTEL CORPORATlOfI. THIS DRAWING
IS IIEC£IVED IN CONFIDENCE AND ITS
COHTEKTS MAY NOT BE DISCLOSED WlTHOUT THE PRIOR WRITTEN CDNSEIIT OF
INTEL CORPORATlOfI.
BPRNI
Si-i 10
S\-\2.
D
Glossary
AACK
I
PI-I5 f- - - - - - - -
BC.LK.I
;v
t
RIB
i
i
II<.
I
Ot-..lBDr:>...t:>'Ql
OVEK'>;2IDE: I
5\-\(P
Address Transformed D-F
BPRO
Bus Priority Out
5\-\C)
_OCK!
~H2.
Bi>-
-A-
I
~?~
5> P-.Ig
[Ff~
2:)
I
74sa:>6
t\1~
I
Bus Priority In
BREQ
Bus Request
BUS ADEN
Bus Address Enable
I
I
I
i
I
C
5HZ
T21/
12. 74S'::>2.
!
:;,
II
r~J,c:..2../hp--t--t-t--l--t-t--
P -1r--------------------t----------~~
ADR.u!-~KF/rFXJ
Bus Data Enable
/,>...J:;:,R\¢!
BUSY
EI~I
\
T
4
BY
74S(lJ.e,
BUS DEN
I
Address Latch Enable
ATRD-ATRF
BPRN
EI2.0
I
O! 14
f
ii
ATI2D!
02 13 ATRel
~
~
['2.
f>.il2.FI
Busy
,
I
[
I
'--
I I
.~
I
I
CBRQ
Common Bus Request
DEN
Data Enable
DPRD
Dual Port Read
DPWT
Dual Port Write
DT/R
Data Transmit/Read
INHI
Inhibit
5~S
A.DRII/
A.JJ
INTA
S14 ':>
'5H'::>
.A..DRI2./
A-OR 13/
f>o..V
Interrupt Acknowledge
INTA CYCLE
Interrupt Acknowledge Cycle
10RC
Input/Output Read Command
lORD
Input/Output Read
i
B
7'1 LSl3B
~--------------------------+-------~I p...
~
2 B
' - -_ _ _(p:-jG I
~GZA
IN\-\\!
5 ~GJ-______~l~
PI-24 ~-----------~-~-4~~~04
__~~~G2B
ONeD CMD E:N! CV
51-1. 1\
E!:C:87
10WC
Input/Output Write Command
10WT
Input/Output Write
MEMRD
Memory Read
MRDC
Memory Read Command
MWTC
Memory Write Command
OFF BD RAM ADDR REQ
Off Board Random Access Memory Address Request
Rf>o..M~/
'St-IIO
'5\-\ 1\
E127~~jl~28
3 c
~
4
'?
~-----~--------------~~---,
Vi 7
Y{p
<::;l EIZ5./Yl';JEI26
IO
Yc:>hEI2.~ EIZ4II E121.,,-, 'E.1'22
YEIIG .,.<=:'v
EII'3~114
1211.0
Ell"
SU>..vt CMD E:NI
'SI-\IO
Off Board Random Access Memory Command
OFF BD RD
Off Board Read
QMCE
Qualified Master Cascade Enable
XACK
Transfer Acknowledge
10K..
t-"::,v
r--~~.rv--...IG
Rp..,M Xi'"-C.K'!
r-'-'VV'v----' RP3, 10K
:Z3 4
~s02.
8
7
5
Service Information
iSBC 86/12A
Option
I
8
Install to use AACK
See figure 2-1
See table 2-13
See table 2-13
See paragraph 2-24
I
7
I
6
5
I
4
3
!
THIS DRAWING CONTAINS INFORMATION
WHICH IS THE PROPRIEFMY PROPERTY
OF INTEL CClIIf'ORATION. THIS _
IS !!ECEI1/El IN COIII'IDEtICt :JIC ITS
CONTENTS MAY NOT BE DISClOSED WJTH.
our THE PRIOR WRITTEN CONSENT OF
INTEL CClIIf'ORATIOII.
REV!S!OI'IS
i
OESCRIF'TlON
DFT
i
CHK
I
I
DATE
APPROVED
I
N/A
See figure 2-1
D
D
-
S-\(P
Ot.JBD~\)QI
S\-\~
EJ>..
BY
OVEl.J.J
51--1':>
"'DR 12.1
f>o..V
'SI-\~
.A..DRI3/
P>'W
INf-\\1
-
51-1.1\
PI-24
ONBDCMDE:N/
-
cv
~7
i<~~1
'SHIO
'5\-\ I I
SLAVE: CMD E:NI
R}>o..M x~k./
S\-\IO
4
CI( f - - - - - - - - - - - - - - I ~'='7__-___,
P>-,.(p"';,
C?
V~~)/
1 8097
C=!}
I
I
I
I
2;.)'"
'3
'~7<:J,Lc::,¢¢
\
!
I
i=
o=:--------f
DRAWN
ISSUED
6
I
5
t
4
I
3
I
D II
SIZE CODE
SCAL£
1
OM~
I
DWG NO.
E 2.OOQO'5"3.
I SHEET
NO NE
I
~
I~
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 3 of 11)
~11/~12
iSB~
7
8
5
6
'I ThiS DRAWiNG COi'iTAiiiS iNi'ORilliftTiOioi '
WHICH IS THE !'IIClPR!ETAR'I P!IC!PEIIn'
Of lIua CORPORATION. THIS DRAWING
IS RECEIVED IN CONFIDENCE AND I1S
CONTENTS MAY NOT BE DISCLOSED WITK-
our THE PRIOR WRITTEN CONSENT Of
INTa CORPOItATION.
AD0-AD7, ADB-ADF
D
~
. - -----,r~------,-J:::...\:)¢-~F
AD8-ADA~
SH2
8286
l. . . /'>S:)--...c:._c"_ _ _1---,--5 :!,""'-t>1
_~---,~::..ct::>-,--_ _ _1_4 'B">
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J>.,..\:)'FIZ 16(.,
1'.
C
~-----1~;1
D"T/R.
Sl-\~
~________~________________~I~~~~12______________~I_l~~__8_2_8_6_
~
{:!..-U/> 74-5$4
'=::.L~VCMO~/IC.5.
51-1.\\
-::'I-l.~
Glossary
D&Jo.,J
t>.J:::
S\-I./.p
DATO-DATF
Data Bits O-F
DBO-DBF
Data Bus O-F
DMO-DMF
Multibus Data O-F
'=*\8
sl-I.e
Ot-.lC!:.\:) r>...,\::JiiZ.1
SI-\(p
BUS.\::)C:~
S""~
S~V~ ~.,.~ F:1o.i1
S\-It.1'\
I
S\-\.c.:.
~¢
c.-r
:OJ'
LOC:~L I"-l"~ Ie.~!
s\-\e
D?>O"-l'O\:)~clo.ll ~~'iC. -------------~..!.I~=~
1--1
OF-F-e.t:> Q.DI
.~--------------"'"
IZ"'~ 74L5{Zl¢
A
=
II
c...C::."""
7
5
Service Information
iSBC86/12A
8
!I WHICH
nilS Ul!AWlmi WilTJUIIS ;~TIOft
IS THE PRIlPRIETAIIY PROPERlY
1
7
I
6
I
5
4
I
3
REVISIONS
ZONE \ REV \
OF INTEL CORPORATION. ntiS DIIAWING
IS RECEIVED IN COI'IflDENCE !tIIIJ ITS
CONTENTS MAY NOT BE.DlSCLOSED WITKOUT THE PRIOR ..-rTEN CCINSENI' Of
INTEL CORI'CIIIATION.
D
AD0-AD7,ADB-ADF
SHZ
~'------r
r _____4..t:::>¢-~1=-
1
DESCRIPTION
OFT
L
CHK
I
DATE
I
APPROVED
------------------"
D
AD8-ADA~
-
'r--
c
c
B
B
A
A
-
8
I
.,.,
ISSUED
!
L
U
!
.-
lit
!
l
SCALE
z
I SHEET
NON E
I
4),
1B
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 4 of 11)
5-13/5-14
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1st INTA DEN
First Interrupt Acknowledge Data Enable
BUS INTA DEN
Bus Interrupt Acknowledge Data Enable
INTR
Interrupt
LocallNTA
Local Interrupt Acknowledge
Local INTA DE
Local Interrupt Acknowledge Data Enable
NMI
Non-maskable Interrupt
PAINTR
Po rt A Interru pt
PBINTR
Port B Interrupt
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Bus Interrupt Out
EXT ClK
External Clock
GATE 0 CTl
Gate 0 Control
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Gate 1 Control
Secondary Transmit Data
STXD
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Glossary
BCLK
Bus Clock
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CAS
Column Address Strobe
CCLK
Constant Clock
DMRO-DMRF
Dynamic RAM Output O-F
RAM AACK
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1
A
REV
B
DRAWN
ISSUED
8
7
6
5
4
:1
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 10 of 11)
5-25/5-26
iSE
5
6
7
8
I~~~=~~FO~~I
I Of INTEL COIIPOIIATION. THIS ORAWiNG I
*
IS RECEIVED IN CONFIDENCE AND I"IS
CONTENTS MAY NOT BE DISCLOSED WfTK.
OUT THE PRIOR WRITTEN CONSENT Of
INTEL CORPORATION.
u.PKD/
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5H 10
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~~~~~~~~--
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5\-\ 3
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c:? eLK:
3 '745011
M~Q~
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DP ON BD ADR EN
Dual Port On Board Address Enable
ON BD CMD EN
On Board Command Enable
ON BD RAM ACK
On Board Random Access Memory Acknowledge
RAM CS
Random Access Memory Chip Select
SLAVE CMD EN
Slave Command Enable
SLAVE DATA EN
Slave Data Enable
+t:..v
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8
I
THIS DRAWING CONTAINS INFORMAnOfl
WHICH IS TIlE PROPRIEl":J!Y :>ROPSr.Y
OF INTEL CORPORATION. THIS DRAWING
IS RECEIVED IN CONFIDENCE AND ITS
CONTENTS .....VNOT BE DISCLOSED WiTHOUT THE PRIOR WRITTEN CONSDIT OF
INTEL CORPDRATION.
7
I
4
3
REVISIONS
ZONE REV
5HIO DMR0-DMRF
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13 SD C~ SQ 12
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D.Pk?D/
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5
6
Service Information
I AS2cO:'>--........- - -____
74~
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A
A
REV
B
DRAWN
ISSUED
8
7
6
5
4
3
1
Figure 5-2. iSBC 86/12A Schematic Diagram (Sheet 11 of 11)
5-27/5-28
APPENDIX A
TELETYPEWRITER MODIFICATIONS
A=1. !I\JTRODUCTION
This appendix provides information required to
modify a Model ASR-33 Teletypewriter for use with
certain Intel iSBC 80 computer systems.
A-2. INTERNAL MODIFICATIONS
IWARNING I
Hazardous voltages are exposed when the
top cover of the teletypewriter is removed. To
prevent accidental shock, disconnect the
teleprinter power cord before proceeding
beyond this point.
Remove the top cover and modify the teletypewriter
as follows:
a.
Remove blue lead from 750-ohm tap on current
source resistor, reconnect this lead to I450-ohm
tap. (Refer to figures A-I and A-2.)
b.
On terminal block, change two wires as follows
to create an internal full-duplex loop (refer to
figures A-I and A-3):
that a 470-ohm resistor and a 0.1 F capacitor may
be substituted for the thyractor.) After the relay
circuit card has been assembled, mount it in position
as shown in figure A-5. Secure the card to the base
plate using two self-tapping screws. Connect the
relay circuit to the distributor trip magnet and mode
switch as follows:
a.
Refer to figure A-4 and connect a wire (Wire 'A')
from relay circuit card to terminal L2 on mode
switch. (See figure A-6.)
b.
Disconnect brown wire shown in figure A-7 from
plastic connector. Connect this brown wire to
terminal L2 on mode switch. (Brown wire will
have to be extended.)
c.
Refer to figure A-4 and connect a wire (Wire 'B')
from relay circuit board to terminal LIon mode
switch.
A-3. EXTERNAL CONNECTIONS
Connect a two-wire receive loop, a two-wire send loop,
and a two-wire tape reader control loop to the
external device as shown in figure A-4. The external
connector pin numbers sho.wn in figure A-4 are for
interface with an RS232C device.
A-4. iSBC 530 TTY ADAPTER
1. Remove brown/yellow lead from terminal 3;
reconnect this lead to terminal 5.
2. Remove white/blue lead from terminal 4; reconnect this lead to terminal 5.
c.
On terminal block, remove violet lead from
terminal 8; reconnect this lead to terminal 9. This
changes the receiver current level from 60 rnA to
20 rnA.
A relay circuit card must be fabricated and connected
to the paper tape reader drive circuit. The relay
circuit card to be fabricated requires a relay, a diode,
a thyractor, a small 'vector' board for mounting the
components, and suitable hardware for mounting
the assembled relay card.
A circuit diagram of the relay circuit card is included
in figure A-4; this diagram also includes the part
numbers of the relay, diode, and thyractor. (Note
The iSBC 530 TTY adapter, which converts RS232C
signal levels to an optically isolated 20 rnA current
loop interface, provides signal translation for
transmitted data, received data, and a paper tape
reader relay. The iSBC 530 TTY adapter interfaces an
Intel iSBC 80 computer system to a teletypewriter as
shown in figure A-8.
The iSBC 530 TTY adapter requires + 12V at 98 rnA
and -12V at 98 rnA. An auxiliary supply must be used
if the iSBC 80 system does not supply this power. A
schematic diagram of the iSBC 530 TTY adapter is
supplied with the unit. The following auxiliary power
connector (or equivalent) must be procured by the
user:
Connector, Molex 09-50-7071
Pins, Molex 08-50-0106
Polarizing Key, Molex 15-04-0219
A-I
Teletypewriter Modifiea tions
MODE
SWITCH
TOP VIEW
MOUNT
CIRCUIT
CARD
KEYBOARD
TAPE
READER
CAPACITOR
PRINTER UNIT
TAPE
PUNCH
CURRENT
SOURCE
RESISTOR
DISTRIBUTOR
TRIP MAGNET
ASSEMBLY
~oCARD
POWER
SUPPLY
lQJ
~OTOV
TERMINAL
BLOCK
TELETYPE MODEL 33TC
Figure A-I. Teletype Component Layout
Figure A-2. Current Source Resistor
A-2
Figure A-3. Terminal Block
Teletypewriter Modifications
TERMINAL BLOCK 151411
20MA
VIO
25-PIN
EXTERNAL
CONNECTOR
VEL
60MA
"
-- - ---- - --- ----"
RECEIVE
BlK/GRN
WHT/BRN
RED/GRN
WHT/YEl
WHT/BlK
WHT/BlU
6
5
4
SEND
FUll DUPLEX
BRN/YEl
GRN
RED
_ ....... ---4------ - - - - - - - - -
3
GRY
WHT/RED
BlK
BlK
2
WHT
WHT
o
117VAC
CONNECTOR
0--..I
117 VAC
TAPE READER
CONTROL
*Al TERNATE CONTACT PROTECTION
CIRCUIT
r-lr----1-4-7-OO-Yz-W
L
DISTRIBUTOR TRIP
MAGNET
I.....--U...-lVVoor--.....J COMMO N
0.11,uF
I
IJR-10OS
I
4700
{2VDC,6000 COil
~~RMAl CONTACTS
OPEN
l!!i!-~ <:.!.!!flllLCA R D _
TO.1200V
Figure A-4. Teletypewriter Modifications
Figure A-5. Relay Circuit
Figure A-6. Mode Switch
A-3
Teletypewriter Modifications
Figure A-7. Distributor Trip Magnet
Jl
FROM
SERIAL IN/OUT
PORT
CINCH DB-25S
P3
530 SBC
TTY ADAPTER
J3
J2
Figure A-B. TTY Adapter Cabling
A-4
TO TERMINAL BLOCK
(SEE FIGURES A·3 AND A·4)
CINCH DB-25P
APPENDIX B
iSBC 300 MULTIMODULE RAM AND
iSBC 340 MUL TIMODULE EPROM
B-i. iNTRODUCTiON
This appendix provides information for installing
the iSBC 300 Multimodule RAM Board and the iSBC
340 Multimodule EPROM Board on the iSBC 86/12A
board.
3. Remove the iSBC 86/12A board from the
backplane and place it on a soft surface
(preferably a piece of foam), component side up.
4. Remove IC (8202) at A 70 from the iSBC 86/12A
board.
5. Remove IC's (74S373) at A71 and A91 from the
iSBC 86/12A board.
B-2. iSBC 300 MULTIMODULE
RAM INSTALLATION
NOTE
The following steps explain how to unpack and
install the iSBC 300 Multimodule RAM.
Save these IC's, they will be reinstalled at a
later step.
1. Unpack the iSBC 300 Multimodule RAM.
2. Inspect the iSBC 300 Multimodule RAM for
damage. If damage exists, follow the instructions for repairs in Section 5 of this manual.
6. Insert the iSBC 300 Multimodule RAM mating
pins into socket A 70 and other mating pins,
orienting the board as shown in figure B-1.
MEMORY LATCHES
(FROM iSBC 86/12A)
G
DYNAMIC
RAM CONTROLLER
(FROM iSBC 86/12A)
iSBC 86/12A
~",,"lr""~"""-/"-
~ ~
REPLACEMENT
MEMORY ADDRESS
DECODE PROMS
(SUPPLIED WITH
iSBC 300 OPTION)
NYLON MOUNTING HARDWARE
(3 PLACES)
(SUPPLIED WITH iSBC 300 OPTION)
Figure B-1. iSBC 300 Multimodule RAM Orientation
B-1
iSBC 86/12A
Appendix B
7. Ensure the mating pins are aligned and carefully
press the iSBC 300 Multimodule RAM into place
by applying pressure at Al of the iSBC 300
Multimodule RAM.
3. Install the 2732 EPROM's in the iSBC 340
Multimodule EPROM.
4. Trim the leads of the 2732's at the end of the
connectors.
8. Place nylon spacer between the iSBC 86/12A
board and the iSBC 300 Multimodule RAM board
at one of the holes shown in figure B-1.
9. Insert screw from solder side through the iSBC
86/12A board, the spacer, and the iSBC 300
Multimodule RAM board.
10. Attach nut and tighten finger tight.
11. Repeat steps 8 through 10 for the other two holes.
12. Tighten all three screws, using a screw driver.
Do not cut connectors.
5. Remove the iSBC 86/12A board from the
backplane and place it on a soft surface
(preferably a piece of foam), component side up.
6. Remove PROM's from locations A28 and A46, if
installed.
7. Bend all capacitors, that will reside under the
iSBC 340 Multimodule EPROM, down against
the board.
Do not overtighten screws as damage to the
board could result.
13. Insert 8202 IC (removed in step 4) into location
Al on the iSBC 300 Multimodule RAM.
14. Insert the two 74S373 IC's (removed in step 5)
into locations A2 and All on the iSBC 300
Multimodule RAM.
8. Hold the iSBC 86/12A board on edge and install
two screws (reference figure B-2), from the solder
side.
9. Place a spacer on each of the screws.
10. Install the iSBC 340 Multimodule EPROM on the
iSBC 86/12A board in the location shown in
figure B-2.
11. Press the iSBC 340 Multimodule EPROM into
place by pressing at locations A3 and A6.
Ensure that the IC's are properly oriented in
their sockets or they could be damaged when
power is applied.
12. Install the two nuts and tighten them finger
tight.
13. Tighten the two nuts with a screw driver.
15. Remove two IC's, from the iSBC 86/12A board at
locations A67 and A68.
16. Insert new IC, part number 9100212, at location
A67.
17. Insert new IC, part number 9100213, at location
A68.
18. Set the switches on Sl per figure 2-1.
Do not over tighten as damage to the board
could result.
14. Reinstall the EPROM's removed in step 6, if they
were 2732 EPROM's. Reinstall them in locations
A3 andA6.
15. Set the switches on Sl per figure 2-1.
B-3. iSBC 340 MUL TIMODULE EPROM
INSTALLATION
B-4. SERVICE INFORMATION
The following steps explain how to unpack anc
install the iSBC 340 Multimodule EPROM.
The following paragraphs provide a list of replaceable parts and service diagrams.
1. Unpack the iSBC 340 Multimodule EPROM.
2. Inspect the iSBC 340 Multimodule EPROM for
damage. If damage exists, follow the instructions for repairs in Section 5 of this manual.
B-2
B-S. REPLACEABLE PARTS
Table B-1 provides a list of replaceable parts for the
Appendix B
iSBC 86/12A
iSBC 340
OPTION
Figure B-2. iSBC 340 Multimodule EPROM Orientation
iSBC 300 Multimodule RAM and iSBC 340 Multimodule EPROM. Table B-2 identifies and locates the
manufacturers specified in the MFR CODE column
in table B-l. Intel parts that are available on the
open market are listed in the MFR CODE columns as
"COML"; every effort should be made to procure
these parts from a local (commercial) distributor.
8-6. SERVICE DIAGRAMS
The iSBC 300 Multimodule RAM parts location
diagram and schematic diagram arae provided in
figures B-3 and B-4, respectively. The iSBC 340
Multimodule PROM parts location diagram and
schematic diagram are provided in figures B-5 and
B-6, respectively.
Table B-1. Replaceable Parts, iSBC 300 Multimodule RAM and iSBC 340 Multimodule PROM
Reference Designation
A3-10,12-19 (300)
C1-6 (340)
C1-3,6,8, 10, 12-21,23,
25,27 -24 (300)
C4,7,9, 11,22,24,26,38 (300)
CS,36,37 (300)
Description
Mfr. Part No.
Mfr.
Code
Oty.
IC, Intel 2117-4, Dynamic RAM
Cap., Cer, 0.1ILF, +80 -20%, SOV
Cap., Cer., 0.1ILF, +80 -20%, SOV
2117-4
aBO
aBO
COML
COML
COML
16
6
26
Cap., mono, 0.01ILF, ±10%, 1SV
Cap., tant, 221LF, ±10%, 1SV
aBO
aBO
COML
COML
8
3
B-3/B-4
Appendix B
iSBC 86/12A
8
7
6
5
4
f)WG NO
J
\Da\l':l~
____
R_EVI$IONS
THIS DRAWING CONTAINS INFORMATION
I ~rl!~~Elc Z~~P~~,~~!61~T~~~SP~~:~f~~ I
IS RECEIVED IN CONFIDENCE AND ITS
CONTENTS MAY NOT 8E DISCLOSED WITH·
OUT TH[ PRIOR WRITTlN CONSENT OF
INiEt CORPORATION
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B-5/B-6
I
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1
7
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Data Out O-F
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Data In O-F
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Figure B-6. iSBC 340 Multimodule EPROM Schematic
B-11/B-12
I
•
APPENDIX C
CUSTOM PROGRAMMED PROMS
n
-
-
C-1. INTRODUCTION
processor and the bus. The base address of RAM onboard is fixed. The base address of RAM from the bus
may be set on any 8k (or 16k if iSBC 300 Multimodule
RAM installed) boundary. It is the job of this PROM
to transform the bus address to the proper on-board
address for correct dual-port access.
This appendix provides information about two
custom programmed PROMs that are used on the
iSBC 86/12A board. One is uesd for on-board Chip
Select and Address Selection (A68), and the other is
used for Address Transformation (A67).
The base address, as seen from the bus, is set by 4
switches: sections 1 through 4 of S1. These switches
may be set in anyone of 16 patterns, corresponding to
the sixteen 8k or 16k boundaries in a 128k address
space. Table C-l shows how these switches are set.
The PROMs that are shipped from the factory with
the iSBC 86/12A, support the basic iSBC 86/12A
board with or without the iSBC 340 Multimodule
PROM. When the iSBC 300 Multimodule RAM is
ordered, a new set of PROMs are shipped. These two
configurations are described in the following
paragraphs.
The size of RAM available to the bus may also be
specified. Two additional switches enable 8k, 16k,
24k, or 32k (16k, 32k, 48k, or 64k if iSBC 340
Multimodule RAM installed) to the bus. See table
C-2.
A third configuration is listed in table C-8 that may
be programmed by the customer. This third configuration allows 2758's, 2716's, or 2732's to be installed on
the iSBC 340 Multimodule EPROM memory expansion board.
PAl\1 may also be totally disabled from the bus by
selecting a 128k byte segment that is out of
range. This is accomplished by jumpering post 112 to
114 and removing any other segment jumper.
C-2. ADDRESS TRANSFORMATION
PROM
The PROM used is an Intel 3625, lk by 4 bipolar
PROM. As such, it has 10 address inputs and 4
outputs. Four of the inputs, (PROM address lines AO,
The iSBC 86/12A board has up to 64k of dual port
RAM which may be accessed by both the on-board
Table C-l. RAM Base Address
S1*
1-16
2-15
3-14
4-13
0
0
0
0
0
0
0
0
0
0
0
0
C
C
C
C
0
0
0
0
C
0
0
0
C
0
C
0
C
0
C
C
C
C
C
C
C
C
C
C
0
0
C
C
0
0
C
C
0
0
C
C
0
c
c
C
BASE
ADDRESS
1
1
1
1
1
1
1
1
F F F F
0 F F F
B F F F
9 F F F
7 F F F
5 F F F
3
1
0 F
0 0
F F F
F F F
0
C
0
C
0
F F F
F F F
0 B F F F
o 9 F F F
C
5 F F F
3 F F F
1 F F F
o
o
o
o
7 F F F
C-l
Appendix C
iSBC 86/12A
Table C-2. RAM Size
S1*
6-11
*C
5-12
RAM Available
to Bus
C
C
8k/16k
C
0
16k/32k
0
0
C
24k/48k
0
32k/64k
= Closed,
0
=Open
AI, A2, A3) connect directly to bus address lines
ADRDI, ADRE/, ADRF I, and ADR101. These lines
tell the PROM the current address on the bus so that
the PROM may determine if that address is for the onboard RAM. Since the address lines on the bus are
inverted, the address represented by the inputs will be
the complement of the actual input. Four more
address inputs (pROM lines A4, A5, A6, A 7) connect
to the base address switches to tell the PROM the top
address of the RAM. The final two inputs (PROM
lines A8 and A9) connect to the bus memory size
switches to determine the amount of RAM available
to the bus.
One of the PROM outputs (04) is the RAM select
line. This output is negative-true, that is, it goes low
when an on-board RAM location is selected.
The other three outputs are the transformed address
lines to the RAM. These lines are also negativetrue. Output 01=ATRDI, 02=ATRE/, 03=ATRF/.
For explanation purposes, the PROM is broken up
into four 256-byte pages. Each page corresponds to
one setting of the RAM size switches. Table C-3
shows the relation between switch settings and the
PROM page selected.
C-3. ADDRESS TRANSFORMATION
PROM CONFIGURATIONS
Table C-4 lists the address transformation PROM
outputs for a factory shipped PROM (A67) to support
the iSBC 86/12A board. For presentation, the PROM
address is divided into 3 groups. The page number
(A) specifies the upper 2 bits of the PROM address (A8
and A9). The left hand column of each table (B)
specifies the middle 4 bits of the PROM address (A4,
A5, A6, and A 7). The top row of each table specifies
the lower 4 bits of the PROM address (AO, AI, A2, and
A3).
The PROM address may be found by combining the
bits from groups A, B, and C. For example, a
particular entry is on page 3, row 4, column 5. The
address within the PROM is 345 hex.
Table C-5 lists the address transformation PROM
outputs for a factory shipped PROM (A67) to support
the iSBC 86/12A board and the iSBC 300 Multimodule RAM.
C-4. MEMORY CHIP SELECT PROM
The iSBC 86/12A can have up to 64k of on-board
RAM and up to 8 EPROMs. These functional blocks
are interconnected with several on-board buses. It is
the job of the memory chip select PROM to select the
proper block, send control signals to the bus enable
logic, and generate an acknowledge if required.
The PROM used is an Intel 3625, 1k by 4 bipolar
PROM. As such, it has 10 address inputs and 4
outputs. Eight of the inputs (PROM address input
lines AO-A 7) connect to CPU address lines ABBAB12 so that the PROM may select the proper
chips. PROM address input lines A8 and A9 connect
to switch Sl positions 7 and 8 which allows the user to
select 1 of 4 possible sizes for the EPROM block.
There are four output lines from the memory chip
select PROM. The two lower outputs (01 and 02) are
encoded by a 2-to-4line decoder. The outputs from the
2-to-4 line decoder select which set of EPROM chips
will be enabled. The two upper outputs (03 and 04)
are used to control the on or off board RAM request
and to enable or disable the 2-to-4 line decoder for
PROM selection. Table C-6 lists the output coding
from the memory chip select PROM and table C-7
lists the input and outputs for the 2-to-4 decoder.
Table C-3. RAM Size - PROM Page
S1*
*C
C-2
RAM
Size
PROM
Page
PROM Address
Range
C
8k/16k
0
000 - OFF
0
16k/32k
1
C
24k/48k
2
100" 1FF
200 - 2FF
0
32k/64k
3
300 - 3FF
8-9
7-10
C
C
0
0
=Closed, 0 =Open
Appendix C
iSBC 86/12A
Table C-4. Translator PROM Contents for Intel Part Number 9100134
Page 0
A
=0
8K of RAM (Part Number 9100134)
B = Base
Address
Switches
C
0
1
2
3
4
5
6
=1
4
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
= Base
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A
=1
5
6
7
8
9
A
B
C
D
E
F
C
= Bus Address
(Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
4
F
F
F
F
F
F
4
F
F
F
F
F
4
F
F
F
F
4
F
F
F
4
F
F
4
F
4
5
5
F
F
5
F
F
5
5
5
5
5
F
5
F
F
5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
4
5
F
F
F
F
F
5
F
F
F
F
F
F
5
F
F
F
F
F
F
F
5
F
5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
R
24K of RAM
B = Base
Address
Switches
0
1
2
3
4
F
16K of RAM
Address
Switches
Page 2
3
1=
F
B
2
F
F
F
F
F
F
F
4
D
E
A
1
8
9
A
B
P3ge 1
0
7
C
=Bus Address (Inverted)
C
= Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
5
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
4
F
F
F
F
F
F
4
F
F
F
F
F
4
F
F
F
F
4
F
F
F
4
F
F
4
F
4
F
5
5
6
5
6
5
5
5
6
5
5
6
5
5
6
5
5
6
F
6
F
F
F
F
F
F
F
F
6
F
F
F
F
F
6
F
F
F
F
F
F
F
F
F
F
F
F
6
F
F
F
F
F
F
F
F
F
6
F
F
F
F
F
F
F
F
F
F
F
F
F
F
6
F
5
F
6
F
F
F
F
F
F
F
F
5
6
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
C-3
Appendix C
iSBC 86/12A
Table C-4. Translator PROM Contents for Intel Part Number 9100134 (Cont'd)
Page 3 A
=3
32K of RAM
B =Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C
= Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
F
4
F
F
F
F
F
F
F
4
F
F
F
F
F
F
4
F
F
F
F
F
4
F
F
F
F
4
F
F
F
4
F
F
4
F
4
5
6
7
6
5
5
6
5
6
7
5
6
7
F
5
6
7
5
6
7
F
F
F
F
F
5
6
7
F
F
F
F
5
6
7
F
F
F
F
F
F
F
F
F
F
F
5
7
F
F
F
F
F
F
F
5
6
7
F
F
F
F
F
F
F
F
5
6
7
F
F
F
F
F
F
F
F
F
5
6
7
5
6
7
F
F
5
6
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
E
F
F
0
1
Table C-5. Translator PROM Contents for Intel Part Number 9100212
Page 0
A
=0
16K of RAM
B =Base
Address
Switches
0
1
2
3
4
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C-4
3
4
5
6
7
8
9
A
B
C
D
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
0
1
F
F
0
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
0
1
0
1
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
B
C
D
E
F
F
F
F
F
F
F
F
0
0
1
2
3
F
1
2
3
1
2
3
F
F
F
F
F
F
32K of RAM
IS = Base
Address
Switches
0
2
F
F
F
F
F
=1
1
F
D
E
= Bus Address (Inverted)
0
F
F
F
5
6
7
8
9
A
B
C
Page 1 A
C
C
0
1
2
F
F
F
3
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
F
F
0
1
F
F
F
F
F
F
F
F
F
F
0
0
1
2
1
2
3
F
F
F
F
F
F
F
F
F
0
1
2
3
F
5
= Bus Address (Inverted)
6
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
8
F
F
F
F
F
F
F
F
F
F
0
1
2
3
0
1
2
3
1
2
3
F
F
F
F
F
0
1
2
F
F
F
F
F
0
3
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
0
0
1
2
1
2
3
1
2
3
F
2
3
3
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Appendix C
iSBC 86/12A
Table C-5. Translator PROM Contents for Intel Part Number 9100212 (Cont'd)
Page 2
A =2
48K of RAM
C = Bus Address (Inverted)
B = Base
Addl'~ss
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
1
F
F
F
F
F
F
0
1
F
F
F
F
F
0
1
F
F
F
F
0
1
F
F
F
0
1
F
F
0
1
F
0
1
F
1
F
F
F
0
1
F
F
F
F
F
F
F
F
F
0
1
F
0
1
2
3
4
5
6
7
8
9
A
F
F
F
F
F
B
C
F
0
E
F
Page 3
A=3
F
0
2
3
4
5
6
7
8
9
A
B
C
0
E
F
C-s.
0
1
0
1
2
2
3
0
1
2
3
4
F
2
3
4
5
2
3
4
5
F
0
1
2
3
4
5
F
F
2
3
4
5
2
3
4
2
3
4
5
5
F
F
F
F
F
F
F
F
F
F
F
F
9
A
F
F
5
F
F
F
F
F
F
F
5
F
F
F
2
3
4
5
F
F
F
F
5
F
F
F
F
2
3
4
5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
C
D
E
F
F
F
F
F
F
F
0
1
F
F
F
64K of RAM
B = Base
Address
Switches
0
1
F
F
F
F
F
F
2
3
4
2
3
4
2
3
4
C = Bus Address (Inverted)
I
0
1
2
3
4
5
6
7
8
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
0
0
1
F
F
F
F
F
F
F
0
1
2
F
F
F
F
F
0
1
2
3
F
F
F
F
F
0
1
2
3
4
MEMORY CHIP SELECT PROM
CONFIGURATIONS
Table C-8 lists the chip select PROM outputs for a
factory shipped PROM (A68) to support the iSBC
86/12A board and an iSBC 340 Multimodule
EPROM. For presentation, the PROM address is
divided into 3 groups. The page number (A) specifies
the upper 2 bits of the PROM address (A8 and
A9). The left hand column of each table (B) specifies
the middle 4 bits of the PROM address (A4, A5, A6,
and A 7). The top row of each table specifies the lower
4 bits of the PROM address (AO, AI, A2, and A3).
The PROM address may be found by combining the
bits from groups A, B, and C. For example, a
particular entry is on page 2, row A, column 7. The
address within the PROM is 2A 7 hex.
F
F
F
F
0
1
2
3
4
5
0
1
2
3
4
5
6
F
F
F
F
0
1
2
3
4
5
6
7
F
F
F
F
0
1
2
3
4
5
6
7
F
0
1
2
3
4
5
6
7
F
F
F
F
F
0
1
2
3
4
5
6
7
F
F
F
0
1
2
3
4
5
6
7
F
0
1
2
3
4
5
6
7
F
F
F
F
F
F
F
F
F
F
F
2
3
4
5
6
7
F
F
F
F
F
F
0
1
2
3
4
5
6
7
F
F
F
F
F
F
F
1
2
3
4
5
6
7
F
F
F
F
F
F
F
F
Table C-9 lists the chip select PROM outputs for a
factory shipped PROM (A68) to support the iSBC
86/12A, board, the iSBC 300 Multimodule RAM, and
the iSBC 340 Multimodule EPROM.
Table C-I0 lists the chip select PROM outputs for a
customer programmed PROM (A68) to support Intel
2758, 2716, or 2732 EPROMs, iSBC 300 Multimodule
RAM, and iSBC 340 Multimodule EPROM. The
PROM map listed in Table C-I0 must be programmed
into an Intel 3625 PROM by the customer. This
PROM replaces the decode PROM located at position
A68 on the iSBC 86/12A board. The factory shipped
PROM at location A67 is not replaced.
In Table C-I0 the "x" value represents one of the
iollowing two values:
1. X = F if iSBC 300 Multimodule RAM expansion
option is not installed.
C-5
Appendix C
iSBC 86/12A
2. X = 7 if i8BC 300 Multimodule RAM option is
installed.
EPROMs. The following table lists the jumper and
switch settings for 2716,2732, or 2758 EPROMs.
Switch S1
C-6. SWITCH SETTINGS FOR 2758, 2716,
OR 2732 EPROMS WITH THE
iSBC 340 MUL TIMODULE EPROM
EPROM
Type
Jumpers
2758
E94-E95, E97 -E98
ON
ON
Jumpers E94 through E99 and switch 81 must be
reconfigured to accommodate 2716, 2732, or 2758
2716
E94-E96, E97-E98
ON
OFF
2732
E94-E96, E97-E99
OFF
ON
8-9
Table C-6. Memory Chip Select PROM Outputs
Chip Output
Function
01
02
03
04
0
0
0
0
0
0
1
I
0
0
0
1
0
0
0
1
1
I
0
1
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
1
1
0
1
>Not Used
I
On Board RAM Request
0
PROM Chip Select 0*
1
0
1
0
1
0
1
PROM Chip Select 1*
PROM Chip Select 2
PROM Chip Select 3
} Off Board Memory Request
* Active only when iSBC 340 Multimodule EPROM is installed.
Table C-7. EPROM Select Coding
Output
Input
C-6
1A
18
PCSO!
0
0
0
0
1
1
1
0
1
1
1
1
1
0
1
PCS1!
PCS2!
PCS3!
1
1
0
1
1
1
1
0
1
7-10
Appendix C
iSBC 86/12A
Table C-B. Chip Select PROM Contents for Intel Part Number 9100129
Page 0
A =0
2K of EPROM (Part Number 9100129)
B = Base
Address
Switches
C = Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
5
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
B
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
Page 1 A = 1 4K of EPROM (Type 2716)
B = Base
Address
Switches
0
1
2
3
4
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
F
F
F
F
F
F
F
7
F
F
F
7
7
F
F
F
F
7
F
F
F
F
F
F
F
F
7
F
F
F
F
F
F
7
F
F
F
F
F
7
F
7
7
7
F
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
F
F
F
F
F
F
F
F
F
F
F
7
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
5
F
6
7
8
9
A
F
F
D
F
F
F
F
F
F
E
F
F
B
C
Page 2
C = Bus Address (Inverted)
A=2
F
5
6
7
8
9
A
B
C
D
E
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
F
B
F
8K of EPROM (Type 2732)
B = Base
Address
Switches
0
1
2
3
4
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
C = Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
7
F
F
7
7
7
F
7
F
F
F
F
F
F
F
7
F
F
F
F
F
F
F
F
7
F
F
F
F
F
F
7
7
F
F
F
7
F
7
F
F
7
F
F
F
7
F
F
7
F
F
F
F
F
F
F
F
F
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
B
B
B
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
C-7
Appendix C
iSBC 86/12A
Table C-B. Chip Select PROM Contents for Intel Part Number 9100129 (Cont'd)
Page 3 A=3
16K of EPROM (Type 2732 with iSBC 340 Multimodule EPROM)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C = Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
G
D
E
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
F
F
F
F
F
F
F
F
F
F
F
F
B
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
B
F
F
Table C-9. Chip Select PROM Contents for Intel Part Number 9100213
Page 0 A = 0 2K of EPROM (Type 2758) (Part Number 9100213)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C = Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
Page 1 A = 1 4K of EPROM (Type 2716)
CoB
C = Bus Address (Inverted)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
.,
Appendix C
iSBC 86/12A
Table C-9. Chip Select PROM Contents for Intel Part Number 9100213 (Cont'd)
Page 2 A=2
8K of EPROM (Type 2732)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Page 3
A=3
C = Bus Address (Inverted)
0
,
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
~
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
16K of EPROM (Type 2732 with iSBC 340 Multimodule EPROM)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C = Bus Address (Inverted)
10
,
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
8
7
7
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
9
9
9
9
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
A
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
7
7
F
F
F
F
F
F
F
F
F
F
F
F
F
B
C
D
E
F
f
F
F
8
Table C-I0. User Coded Chip Select PROM Contents
Page 0
A =0
2K of EPROM (Type 2758)
B = Base
Address
Switches
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
C = Bus Address (Inverted)
0
1
2
3
4
5
6
7
8
9
A
B
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
B
9
C-9
Appendix C
iSBC 86/12A
Table 3-10. User Coded Chip Select PROM Content (Cont'd)
Page 1
A =1
4K of EPROM (Type 2716)
B = Base
Address
Switches
2
3
4
5
6
7
8
9
A
B
C
D
E
F
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
B
B
A
B
C
D
E
F
9
A
B
C
D
E
F
A=2
8K of EPROM (Type 2732)
B = Base
Address
Switches
C = Bus Address (Inverted)
D
1
2
3
4
5
6
7
8
9
D
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1
2
3
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
B
B
B
B
A
B
C
D
E
F
5
6
7
8
9
A
B
C
D
E
F
A=3
B = Base
Address
Switches
8K of EPROM (Type 2732)
C = Bus Address (Inverted)
D
1
2
3
4
5
6
7
8
9
D
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
1
2
3
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
8
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
9
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
F
F
F
F
F
F
F
F
F
F
F
F
F
9
F
F
F
F
F
F
F
F
F
F
F
F
F
A
B
B
B
B
5
6
7
8
9
A
B
C
0
E
F
ColO
1
1
2
3
4
6
7
8
Page 3
D
D
5
Page 2
C = Bus Address (Inverted)
F
A
iSSC 86/12A Single Board Computer
Hardware Reference Manual
9803074-01
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