98 153D MCS 80 Users Manual Oct77

98-153D__MCS-80_Users_Manual_Oct77 98-153D__MCS-80_Users_Manual_Oct77

User Manual: manual pdf -FilePursuit

Open the PDF directly: View PDF .
Page Count: 468

Download
Open PDF In Browser	View PDF

OCTOBER 1977

MCS-80™ USER'S MANUAL
(WITH INTRODUCTION TO MCS-85™)

The MCS-80™ family of microcomputer components has been greatly
expanded since the last version of the MCS-80 manual was published in
September, 1975. Over the last two years, expansion of MCS-80 family
devices, coupled with the best system development support in the industry,
have made Intel's 8080A the industry standard microprocessor.
Now Intel introduces the MCS-85 family, an evolutionary system based
around the third generation 8085 microprocessor. MCS-85 has all the features
of an MCS-80 system with higher performance and lower cost. MCS-85, the
next industry standard for new designs.
Over forty microcomputer components are described in detail in this manual.
Among the newest are:
8251A
8253
8255A
8257
8259
8279
2716
2114
2116

Improved Programmable Communication Interface
Programmable Interval Timer
Improved Programmable Peripheral Interface
Programmable DMA Controller
Programmable Interrupt Controller
Programmable Keyboard/Display Controller
2K x 8 EPROM, 5 Volt Only
1K x 4 Static RAM
16K x 1 Dynamic RAM

8085
8155/56
8355
8755

5 Volt Advanced 8080 Processor
Combination 256x8 Static RAM, 22 I/O Lines, 14-bit Counter
Combination 2K x 8 ROM, 16 I/O Lines
Combination 2K x 8 EPROM (5 Volt), 16 I/O Lines

intel· Microcomputers. First from the beginning.

TABLE OF
CONTENTS

INTRODUCTION
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advantages of Designing with Microcomputers
.............................. .
Microcomputer Design Aids . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

i

II
III
III
IV

CHAPTER 1 - THE FUNCTIONS OF A COMPUTER
A Typical Computer System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Architecture of a CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Computer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
1-1
1-3

CHAPTER 2 - THE 8080 CENTRAL PROCESSING UNIT
General . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Architecture of the 8080 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
The Processor Cycle
Interrupt Sequences
................................................ .
Hold Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ha It Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-up of the 8080 CPU
.......•.....................................

2-'
2-2
2-3
2-11
2-12
2-13
2-13

CHAPTER 3 - INTERFACING THE 8080
General . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic System Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU Modu Ie Design
... ... . . .. ... . ... .. .. ... .. . .... .. .. .. . ..... .. .. ..
Interfacing the 8080 to Memory and I/O Devices
............................ .

3-1
3-1
3-2
3-6

CHAPTER 4 - INSTRUCTION SET
Genera I ......... _ . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . . . .... .
Data Transfer Group . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arithmetic Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.................................................... .
Branch Group
Stack, I/O and Machine Control Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Summary Table ..................................................... .

4-1
4-4
4-6
4-11
4-13
4-15

CHAPTER 5 - INTRODUCTION TO MCS_85™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5-1

CHAPTER 6 - MICROCOMPUTER SYSTEM COMPONENT DATA SHEETS
CPU Group
8080A 8-Bit Microprocessor
........................................ .
808OA-l 8-Bit Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
808OA-2 8-Bit Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8080A 8-Bit Microprocessor (MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8224 Clock Generator and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8224 Clock Generator and Driver (MIL)
8801 Clock Generator Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8228/8238 System Controller and Bus Driver
............................ .
M8228/M8238 System Controller and Bus Driver (MIL) ... , . . . . . . . . . . . . . . . . . . .
8085 Single Chip 8-Bit N-Channel Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . .
EPROMs and ROMs
8708 8192-Bit EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2716 2048x8 EPROM
............................................ .
8308 8192-Bit MOS ROM . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8316A 16,384-Bit MOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
2316E 2048x8 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PROM and ROM Programming Instructions

6-1
6-8
6-12
6-16
6-20
6-26
6-30
6-32
6-38
6-43
6-57
6-60
6-64
6-68
6-71
6-74

INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.

CHAPTER 6 - MICROCOMPUTER SYSTEM COMPONENT DATA SHEETS (Continued)
RAMs
8101A-4 1024·Bit RAM with I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8102A·4 1024-Bit MOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8111A-4 1024-Bit RAM with I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5101 256x4 CMOS RAM
.......................................... .
M5101-4/M5101 L-4 256x4-Bit Static CMOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . . .
2114 1024x4 Static MOS RAM
2142 1024x4-Bit Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2104A 4096xl Dynamic MOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2107B 4096xl Dynamic MOS RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.................................. .
2116 16,384xl Dynamic MOS RAM
3222 4K Dynamic RAM Refresh Cont. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3232 4K Dynamic RAM Multiplexer and Refresh Counter . . . . . . . . . . . . . . . . . . . . .
3242 16K Dynamic RAM Multiplexer and Refresh Counter
.................. .
Peripherals and Support Circuits
8205 High Speed lout of 8 Binary Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8212 8-Bit Input/Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8212 8-Bit Input/Output Port (MI L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8214 Priority Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8214 Priority Interrupt Control (MI L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8216/8226 4-Bit Parallel Bi-Directional Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8216 4-Bit Parallel Bi-Directional Bus Driver (M I L) . . . . . . . . . . . . . . . . . . . . . . . . .
8251 A Programmable Communication Interface ...' . . . . . . . . . . . . . . . . . . . . . . . . . .
M8251 Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . , ........... .
8253/8253-5 Programmable Interval Timer
8255A/8255A-5 Programmable Peripheral Interface
........................ .
M8255A Programmable Peripheral Interface (MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
8257/8257-5 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8259/8259-5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8271 Floppy Disk Controller ......... ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8273 SD LC Protocol Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8275 CRT Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8279/8279-5 Keyboard/Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory and I/O Expanders for MCS_85™
8155/8156 2048-Bit Static MOS RAM with I/O Ports and Timer . . . . . . . . . . . . . . . . .
8355 16,384-Bit ROM with I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8755 16,384-Bit EPROM with I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-95
6-98
6-102
6-105
6-109
6-112
6-116
6-120
6-128
6-134
6-142
6-148
6-152
6-159
6-165
6-174
6-179
6-183
6-186
6-191
6-194
6-209
6-212
6-223
6-244
6-247
6-265
6-281
6-285
6-289
6-293
6-307
6-319
6-326

CHAPTER 7 - SUPPORT PRODUCTS
Intellec Prompt SO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intellec Microcomputer Development System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ICE-SO SOSO In-Circuit Emulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UPP Universal PROM Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J,lSCOpeTM 820 Microprocessor System Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J,lScope ™ Probe SOSOA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7-1
7-5
7-9
7-15
7-17
7-21

CHAPTER 8 - GENERAL INFORMATION
Ordering Information . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Packaging Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
Military Program . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . , . . . . . . . • . . . . . . . . . .
Instruction Set Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . .

8-1
8-2
8-9
8-12

INTRODUCTION

r

INTRODUCTION

Since their inception, digital computers have continuously become more efficient, expanding into new applications with each major technological improvement. The
advent of minicomputers enabled the inclusion of digital
computers as a permanent part of various process control
systems. Unfortunately, the size and cost of minicomputers
in "dedicated" applications has limited their use. Another
approach has been the use of custom built systems made up
of "random logic" (i.e., logic gates, flip-flops, counters, etc.).
However, the huge expense and development time involved
in the design and debugging of these systems has restricted
their use to large volume applications where the development costs could be spread over a large number of machines.
Today, Intel offers the systems designer a new alternative ... the microcomputer. Utilizing the technologies and
experience gained in becoming the world's largest supplier
of LSI memory components, Intel has made the power of
the digital computer available at the integrated circuit level.
Using the n-channel silicon gate MOS process, Intel engineers have implemented the fast (2/.1s. cycle) and powerful
(72 basic instructions) 8080 microprocessor on a single LSI
chip. When this processor is combined with memory and
I/O circuits, the computer is complete. Intel offers a variety
of random-access memory (RAM), read·only memory (ROM)
and shift register circuits, that combine with the 8080 processor to form the MCS~80 microcomputer system, a system
that can directly address and retrieve as many as 65,536
bytes stored in the memory devices.
The 8080 processor is packaged in a 40-pin dual in-line
package (DIP) that allows for remarkably easy interfacing.
The 8080 has a 16-bit address bus, a 8-bit bidirectional data
bus and fully decoded, TTL-compatible control outputs. In
addition to supporting up to 64K bytes of mixed RAM and
ROM memory, the 8080 can address up to 256 input ports
and 256 output ports; thus allowing for virtually unlimited
system expansion. The 8080 instruction set includes conditional branching, decimal as well as binary arithmetic,

logical, register-to-register, stack control and memory reference instructions. In fact, the 8080 instruction set is powerful enough to rival the performance of many of the much
higher priced minicomputers, yet the 8080 is upward software compatible with Intel's earlier 8008 microprocessor
(i.e., programs written for the 8008 can be assembled and
executed on the 8080).
In addition to an extensive instruction set oriented to
problem solving, the 8080 has another significant featureSPEED. In contrast to random logic designs which tend to
work in parallel, the microcomputer works by sequentially
executing its program. As a result of this sequential execution, the number of tasks a microcomputer can undertake
in a given period of time is directly proportional to the
execution speed of the microcomputer. The speed of execution is the limiting factor of the realm of applications of
the microcomputer. The 8080, with instruction times as
short as 2 /.Isec., is an order of magnitude faster than earlier
generations of microcomputers, and therefore has an expanded field of potential appl ications.
The architecture of the 8080 also shows a significant
improvement over earlier microcomputer designs. The 8080
contains a 16-bit stack pointer that controls the addressing
of an external stack located in memory. The pointer can be
initialized via the proper instructions such that any portion
of external memory can be used as a last in/first out stack;
thus enabling almost unlimited subroutine nesting. The stack
pointer allows the contents of the program counter, the accumulator, the condition flags or any of the data registers to
be stored in or retrieved from the external stack. In addition, multi-level interrupt processing is possible using the
8080's stack control instructions. The status of the processor can be "pushed" onto the stack when an interrupt is
accepted, then "popped" off the stack after the interrupt has
been serviced. This ability to save the contents of the processor's registers is possible even if an interrupt service
routine, itself, is interrupted.

CONVENTIONAL SYSTEM
Product definition
System and logic design
Debug

Done with logic diagrams
Done with conventional
Lab Instrumentation

PC card layout
Documentation
Cooling and packaging
Power distribution
Engineering changes

Done with yellow wire

PROGRAMMED LOGIC
Simplified because of ease of incorporating features
Can be programmed with design aids
(compilers, assemblers, editors)
Software and hardware aids reduce time
Fewer cards to layout
Less hardware to document
Reduced system size and power consumption
eases job
Less power to distribute
Change program

Table 0-1. The Advantages of Using Microprocessors

ADVANTAGES OF DESIGNING
WITH MICROCOMPUTERS
Microcomputers simplify almost every phase of product development. The first step, as in any product development program, is to identify the various functions that
the end system is expected to perform. Instead of realizing
these functions with networks of gates and flip-flops, the
functions are implemented by encoding suitable sequences
of instructions (programs) in the memory elements. Data
and certain types of programs are stored in RAM, while the
basic program can be stored in ROM. The microprocessor
performs all of the system's functions by fetching the instructions in memory, executing them and communicating
the results via the microcomputer's I/O ports. An 8080
microprocessor, executing the programmed logic stored in a
single 2048-byte ROM element, can perform the same logical
functions that might have previously required up to 1000
logic gates.
The benefits of designing a microcomputer into your
system go far beyond the advantages of merely simplifying
product development. You will also appreciate the profitmaking advantages of using a microcomputer in place of
custom-designed random logic. The most apparent advantage
is the significant savings in hardware costs. A microcomputer
chip set replaces dozens of random logic elements, thus reo
ducing the cost as well as the size of your system. In addition, production costs drop as the number of individual
components to be handled decreases, and the number of
complex printed circuit boards (which are difficult to layout, test and correct) is greatly reduced. Probably the most
profitable advantage of a microcomputer is its flexibility
for change. To modify your system, you merely re-program
the memory elements; you don't have to redesign the entire
system. You can imagine the savings in time and money
when you want to upgrade your product. Reliability is
another reason to choose the microcomputer over random
logic. As the number of components decreases, the probability of a malfunctioning element likewise decreases. All

of the logical control functions formerly performed by
numerous hardware components can now be implemented
in a few ROM circuits which are non-volatile; that is, the
contents of ROM will never be lost, even in the event of a
power failure. Table 0-1 summarizes many of the advantages of using microcomputers.

MICROCOMPUTER DESIGN AIDS
If you're used to logic design and the idea of designing
with programmed logic seems like too radical a change, regardless of advantages, there's no need to worry because
Intel has already done most of the groundwork for you. The
INTELLEC®Microcomputer Development System provides
flexible, inexpensive and simplified methods for OEM product development. The INTELLEC MDS provides RAM
program storage making program loading and modification
easier, a display and control console for system monitoring and debugging, standard TTY and CRT interfaces, incircuit emulation capability (ICE-80), PROM programming
capability using the Universal PROM Programmer module,
and a standard software package (System Monitor, Assembler and Text Editor). In addition to the standard software
package available with the INTELLEC MDS Intel offers a
resident Pl/M compiler. Intel's Microcomputer Division is
always available to provide assistance in every phase of your
product development.
Intel also provides complete documentation on all
their hardware and software products. I n addition to this
User's Manual, there are the:
•
•
•
•
•
•
•

Pl/M'·MSO Programming Manual
8OS0/S085 Assembly Language Programming
Manual
INTE LLEC MDS Operator's Manual
INTELLEC MDS Hardware Reference
Manual
ICE-80 Operator's Manual
ICE-80 Hardware Reference Manual
S080 User's Program Library "Insite"

APPLICATIONS EXAMPLE

the control unit (as shown in Figure 0-1), the only "custom"
logic will be that of the interface circuits. These circuits are
usually quite simple, providing electrical buffering for the
input and output signals.

The 8080 can be used as the basis for a wide variety
of calculation and control systems. The system configura·
tions for particular applications will differ in the nature of
the peripheral devices used and in the amount and the type
of memory required. The applications and solutions de·
scribed in th is section are presented primarily to show how
microcomputers can be used to solve design problems. The
8080 should not be considered limited either in scope or
performance to those applications listed here.

Instead of drawing state diagrams leading to logic, the
system designer now prepares a flow chart, indicating which
input signals must be read, what processing and computations are needed, and what output signals must be produced.
A program is written from the flow chart. The program is
then assembled into bit patterns which are loaded into the
program memory. Thus, this system is customized primarily
by the contents of program memory.

Consider an 8080 microcomputer used within an auto·
matic computing scale for a supermarket. The basic machine
has two input devices: the weighing unit and a keyboard,
used for function selection and to enter the price per unit
of weight. The only output device is a display showing the
total price, although a ticket printer might be added as an
optional output device.

For this automatic scale, the program would probably
reside in read-only memory (ROM), since the microcomputer would always execute the same program, the one
which implements the scale functions. The processor would
constantly monitor the keyboard and weighing unit, and update the display whenever necessary. The unit would require
very little data memory; it would only be needed for rate
storage, intermediate results, and for storing a copy of the
display.

The control unit must accept weight information from
the weighing unit, function and data inputs from the key·
board, and generate the display. The only arithmetic function to be performed is a simple multiplication of weight
times rate.

When the control portion of a product is implemented
with a microcomputer chip set, functions can be changed
and features added merely by altering the program in memory. With a TTL based system, however, alterations may require extensive rewiring, alteration of PC boards, etc.

The control unit could probably be realized with
standard TTL logic. State diagrams for the various portions
could be drawn and a multiplier unit designed. The whole
design could then be tied together, and eventually reduced
to a selection of packages and a printed circuit board layout.
In effect, when designing with a logic family such as TTL,
the designs are "customized" by the choice of packages and
the wiring of the logic.

The number of applications for microcomputers is
limited only by the depth of the designer's imagination. We
have listed a few potential applications in Table 0-2, along
with the types of peripheral devices usually associated with
each product.

If, however, an 8080 microcomputer is used to realize

KEYBOARD

WEIGHING
UNIT

PRINTER

00
00
00
00
00

000
000
000
000

III II II

II~:I:-II~:II-II-jl
II
I

1

1
INPUT
INTERFACE .:;1

8080

cpu
CONTROL
UNIT

~

INPUT
INTERFACE ",2

OUTPUT
INTERFACE ::.:1

It I

I I
BUS

I
r - - -I- - I

OPTIONAL

I
I

INTERFACE .:;2

,

OUTPUT

~--TT--

~

I I

[J

DISPLAY

It

It I

I

MEMORY

DATA
MEMORY

(PROM

(RAMI

PROGRAM

I

Figure 0-1. Microcomputer Application - Automatic Scale

III

II t II

L...--

I

I
I
...J

l-

I

APPLICATION

PERIPHERAL DEVICES ENCOUNTERED

Intelligent Terminals

Cathode Ray Tube Display
Printing Units
Synchronous and Asynchronous data lines
Cassette Tape Unit
Keyboards

Gaming Machines

Keyboards, push buttons and switches
Various display devices
Coin acceptors
Coin dispensers

Cash Registers

Keyboard or Input Switch Array
Change Dispenser
Digital Display
Ticket Printer
Magnetic Card reader
Communication interface

Accounting and Billing Machines

Keyboard
Printer Unit
Cassette or other magnetic tape unit
"Floppy" disks

Telephone Switching Control

Telephone Line Scanner
Analog Switching Network
Dial Registers
Class of Service Parcel

Numerically Controlled Machines

Magnetic or Paper Tape Reader
Stepper Motors
Optical Shaft Encoders

Process Control

Analog-to-Digital Converters
Digital-to-Analog Converters
Control Switches
Displays

Table 0-2. Microprocessor Applications

IV

I

roo

Chapter 1

THE FUNCTIONS OF A COMPUTER

THE FUNCTIONS OF A COMPUTER

This chapter introduces certain basic computer concepts. It provides background information and definitions
which will be useful in later chapters of this manual. Those
already familiar with computers may skip this material, at
their option.

peripheral storage device, such as a floppy disk unit, or the
output may constitute process control signals that direct the
operations of another system, such as an automated assembly
line. Like input ports, output ports are addressable. The
input and output ports together permit the processor to
communicate with the outside world.

A TYPICAL COMPUTER SYSTEM

The CPU unifies the system. It controls the functions
performed by the other components. The CPU must be able
to fetch instructions from memory, decode their binary
contents and execute them. It must also be able to reference
memory and I/O ports as necessary in the execution of in·
structions. In addition, the CPU should be able to recognize
and respond to certain external control signals, such as
INTERRUPT and WAIT requests. The functional units
within a CPU that enable it to perform these functions are
described below.

A typical digital computer consists of:
a) A central processor unit (CPU)
b) A memory
c) Input/output (I/O) ports
The memory serves as a place to store Instructions,
the coded pieces of information that direct the activities of
the CPU, and Data, the coded pieces of information that are
processed by the CPU. A group of logically related instructions stored in memory is referred to as a Program. The CPU
"reads" each instruction from memory in a logically determined sequence, and uses it to initiate processing actions.
If the program sequence is coherent and logical, processing
the program will produce intelligible and useful results.

THE ARCHITECTURE OF A CPU
A typical central processor unit (CPU) consists of the
following interconnected functional units:
• Registers
• Arithmetic/Logic Unit (ALU)
• Control Circuitry

The memory is also used to store the data to be manipulated, as well as the instructions that direct that manipulation. The program must be organized such that the CPU
does not read a non-instruction word when it expects to
see an instruction. The CPU can rapidly access any data
stored in memory; but often the memory is not large enough
to store the entire data bank required for a particular application. The problem can be resolved by providing the computer with one or more Input Ports. The CPU can address
these ports and input the data contained there. The addition
of input ports enables the computer to receive information
from external equipment (such as a paper tape reader or
floppy disk) at high rates of speed and in large volumes.

Registers are temporary storage units within the CPU.
Some registers, such as the program counter and instruction
register, have dedicated uses. Other registers, such as the accumulator, are for more general purpose use.

Accumulator:
The accumulator usually stores one of the operands
to be manipulated by the ALU. A typical instruction might
direct the ALU to add the contents of some other register to
the contents of the accumulator and store the result in the
accumulator itself. In general, the accumulator is both a
source (operand) and a destination (result) register.

A computer also requires one or more Output Ports
that permit the CPU to communicate the result of its processing to the outside world. The output may go to a display, for use by a human operator, to a peripheral device
that produces "hard-copy," such as a line-printer, to a

Often a CPU will include a number of additional
general purpose registers that can be used to store operands
or intermediate data. The availability of general purpose

1-1

registers eliminates the need to "shuffle" intermediate results back and forth between memory and the accumulator,
thus improving processing speed and efficiency.

cessor loads the address specified in the Call into its Program Counter. The next instruction fetched will therefore
be the first step of the subroutine.
The last instruction in any subroutine is a Return. Such
an instruction need specify no address. When the processor
fetches a Return instruction, it simply replaces the current
contents of the Program Counter with the address on the
top of the stack. This causes the processor to resume execution of the calling program at the point immediately following the original Call Instruction.

Program Counter (Jumps, Subroutines
and the Stack):
The instructions that make up a program are stored
in the system's memory. The central processor references
the contents of memory, in order to determine what action
is appropriate. This means that the processor must know
which location contains the next instruction.

Subroutines are often Nested; that is, one subroutine
will sometimes call a second subroutine. The second may
call a third, and so on. This is perfectly acceptable, as long
as the processor has enough capacity to store the necessary
return addresses, and the logical provision for doing so_ In
other words, the maximum depth of nesting is determined
by the depth of the stack itself. If the stack has space for
storing three return addresses, then three levels of subroutines may be accommodated.

Each of the locations in memory is numbered, to distinguish it from all other locations in memory. The number
which identifies a memory location is called its Address.
The processor maintains a counter which contains the
address of the next program instruction. This register is
called the Program Counter. The processor updates the program counter by adding "1" to the counter each time it
fetches an instruction, so that the program counter is always
current (pointing to the next instruction).

Processors have different ways of maintaining stacks.
Some have facilities for the storage of return addresses built
into the processor itself. Other processors use a reserved
area of external memory as the stack and simply maintain a
Pointer register which contains the address of the most
recent stack entry. The external stack allows virtually unlimited subroutine nesting. In addition, if the processor provides instructions that cause the contents of the accumulator
and other general purpose registers to be "pushed" onto the
stack or "popped" off the stack via the address stored in the
stack pointer, multi-level interrupt processing (described
later in this chapter) is possible. The status of the processor
(i.e., the contents of all the registers) can be saved in the
stack when an interrupt is accepted and then restored after
the interrupt has been serviced_ This ability to save the processor's status at any given time is possible even if an interrupt service routine, itself, is interrupted.

The programmer therefore stores his instructions in
numerically adjacent addresses, so that the lower addresses
contain the first instructions to be executed and the higher
addresses contain later instructions. The only time the programmer may violate this sequential rule is when an instruction in one section of memory is a Jump instruction to
another section of memory.
A jump instruction contains the address of the instruction which is to follow it. The next instruction may be
stored in any memory location, as long as the programmed
jump specifies the correct address. During the execution of
a jump instruction, the processor replaces the contents of its
program counter with the address embodied in the Jump_
Thus, the logical continuity of the program is maintained.
A special kind of program jump occurs when the stored
program "Calls" a subroutine_ In this kind of jump, the processor is required to "remember" the contents of the program counter at the time that the jump occurs. This enables
the processor to resume execution of the main program
when it is finished with the last instruction of the subroutine_

Instruction Register and Decoder:
Every computer has a Word Length that is characteristic of that machine. A computer's word length is usually
determined by the size of its internal storage elements and
interconnecting paths (referred to as Busses); for example,
a computer whose registers and busses can store and transfer 8 bits of information has a characteristic word length of
8-bits and is referred to as an S-bit parallel processor. An
eight-bit parallel processor generally finds it most efficient
to deal with eight-bit binary fields, and the memory associated with such a processor is therefore organized to store
eight bits in each addressable memory location. Data and
instructions are stored in memory as eight-bit binary numbers, or as numbers that are integral multiples of eight bits:
16 bits, 24 bits, and so on. This characteristic eight-bit field
is often referred to as a Byte.

A Subroutine is a program within a program_ Usually
it is a geJ1eral-purpose set of instructions that must be executed repeatedly in the course of a main program. Routines
which calculate the square, the sine, or the logarithm of a
program variable are good examples of functions often
written as subroutines. Other examples might be programs
designed for inputting or outputting data to a particular
peripheral device.
The processor has a special way of handling subroutines, in order to insure an orderly return to the main
program. When the processor receives a Call instruction, it
increments the Program Counter and stores the counter's
contents in a reserved memory area~ known as the Stack.
The Stack thus saves the address of the instruction to be
executed after the subroutine is completed. Then the pro-

Each operation that the processor can perform is
identified by a unique byte of data known as an Instruction

1-2

performs the arithmetic and logical operations on the binary
data.

Code or Operation Code. An eight·bit word used as an in·
struction code can distinguish between 256 alternative
actions, more than adequate for most processors.

The ALU must contain an Adder which is capable of
combining the contents of two registers in accordance with
the logic of binary arithmetic. This provision permits the
processor to perform arithmetic manipulations on the data
it obtains from memory and from its other inputs.

The processor fetches an instruction in two distinct
operations. First, the processor transmits the address in its
Program Counter to the memory. Then the memory returns
the addressed byte to the processor. The CPU stores this
instruction byte in a register known as the Instruction
Register, and uses it to direct activities during the remainder
of the instruction execution.

Using only the basic adder a capable programmer can
write routines which will subtract, multiply and divide, giv·
ing the machine complete arithmetic capabilities. In practice,
however, most ALUs provide other built·in functions, including hardware subtraction, boolean logic operations, and
shift capabilities.

The mechanism by which the processor translates an
instruction code into specific processing actions requires
more elaboration than we can here afford. The concept,
however, should be intuitively clear to any logic designer.
The eight bits stored in the instruction register can be de·
coded and used to selectively activate one of a number of
output lines, in this case up to 256 lines. Each line repre·
sents a set of activities associated with execution of a par·
ticular instruction code. The enabled line can be combined
with selected timing pulses, to develop electrical signals that
can then be used to initiate specific actions. This transla·
tion of code into action is performed by the Instruction
Decoder and by the associated control circuitry.

The ALU contains Flag Bits which specify certain
conditions that arise in the course of arithmetic and logical
manipulations. Flags typically include Carry, Zero, Sign, and
Parity. It is possible to program jumps which are condi·
tionally dependent on the status of one or more flags. Thus,
for example, the program may be designed to jump to a
special routine if the carry bit is set following an addition
instruction.

Control Circuitry:

An eight-bit instruction code is often sufficient to
specify a particular processing action. There are times, how·
ever, when execution of the instruction requires more infor·
mation than eight bits can convey.

The control circuitry is the primary functional unit
within a CPU. Using clock inputs, the control circuitry
maintains the proper sequence of events required for any
processing task. After an instruction is fetched and decoded,
the control circuitry issues the appropriate signals (to units
both internal and external to the CPU) for initiating the
proper processing action. Often the control circuitry will be
capable of responding to external signals, such as an inter·
rupt or wait request. An Interrupt request will cause the
control circuitry to temporarily interrupt main program
execution, jump to a special routine to service the interrupting device, then automatically return to the main program.
A Wait request is often issued by a memory or I/O element
that operates slower than the CPU. The control circuitry
will idle the CPU until the memory or I/O port is ready with
the data.

One example of this is when the instruction refer·
ences a memory location. The basic instruction code iden·
tifies the operation to be performed, but cannot specify
the object address as well. In a case like this, a two· or threebyte instruction must be used. Successive instruction bytes
are stored in sequentially adjacent memory locations, and
the processor performs two or three fetches in succession to
obtain the full instruction. The first byte retrieved from
memory is placed in the processor's instruction register, and
subsequent bytes are placed in temporary storage; the pro·
cessor then proceeds with the execution phase. Such an
instruction is referred to as Variable Length.

Address Register(s):

COMPUTER OPERATIONS

A CPU may use a register or register-pair to hold the
address of a memory location that is to be accessed for
data. If the address register is Programmable, (i.e., if there
are instructions that allow the programmer to alter the
contents of the register) the program can "build" an address in the address register prior to executing a Memory
Reference instruction (i.e., an instruction that reads data
from memory, writes data to memory or operates on data
stored in memory).

There are certain operations that are basic to almost
any computer. A sound understanding of these basic operations is a necessary prerequisite to examining the specific
operations of a particular computer.

Timing:
The activities of the central processor are cyclical. The
processor fetches an instruction, performs the operations
required, fetches the next instruction, and so on. This
orderly sequence of events requires precise timing, and the
CPU therefore requires a free running oscillator clock which
furnishes the reference for all processor actions. The com·
bined fetch and execution of a single instruction is referred
to as an Instruction Cycle. The portion of a cycle identified

Arithmetic/Logic Unit (ALU):
All processors contain an arithmetic/logic unit, which
is often referred to simply as the ALU. The ALU, as its
name implies, is that portion of the CPU hardware which

1-3

with a clearly defined activity IS called a State. And the interval between pulses of the timing oscillator is referred to as a
Clock Period. As a general rule, one or more clock periods
are necessary for the completion of a state, and there are
several states in a cycle.

had time to respond, it frees the processor's READY line,
and the instruction cycle proceeds.

Input/Output:
Input and Output operations are similar to memory
read and write operations with the exception that a peripherall/O device is addressed instead of a memory location.
The CPU issues the appropriate input or output control
signal, sends the proper device address and either receives
the data being input or sends the data to be output.

Instruction Fetch:
The first state(s) of any instruction cycle will be
dedicated to fetching the next instruction. The CPU issues a
read signal and the contents of the program counter are sent
to memory, which responds by returning the next instruction word. The first byte of the instruction is placed in the
instruction register. If the instruction consists of more than
one byte, additional states are required to fetch each byte
of the instruction. When the entire instruction is present in
the CPU, the program counter is incremented (in preparation for the next instruction fetch) and the instruction is
decoded_ The operation specified in the instruction will be
executed in the remaining states of the instruction cycle.
The instruction may call for a memory read or write, an
input or output and/or an internal CPU operation, such as
a register-to·register transfer or an add-registers operation.

Data can be input/output in either parallel or serial
form. All data within a digital computer is represented in
binary coded form. A binary data word consists of a group
of bits; each bit is either a one or a zero. Parallel I/O consists of transferring all bits in the word at the same time,
one bit per line. Serial I/O consists of transferring one bit
at a time on a single line. Naturally serial I/O is much
slower, but it requires considerably less hardware than does
parallel I/O.

Interrupts:
Interrupt provisions are included on many central
processors, as a means of improving the processor's efficiency. Consider the case of a computer that is processing a
large volume of data, portions of which are to be output
to a printer. The CPU can output a byte of data within a
single machine cycle but it may take the printer the equivalent of many machine cycles to actually print the character
specified by the data byte. The CPU could then remain idle
waiting until the printer can accept the next data byte. If
an interrupt capability is implemented on the computer, the
CPU can output a data byte then return to data processing.
When the printer is ready to accept the next data byte, it
can request an interrupt. When the CPU acknowledges the
interrupt, it suspends main program execution and automatically branches to a routine that will output the next
data byte. After the byte is output, the CPU continues
with main program execution. Note that this is, in principle,
quite similar to a subroutine call, except that the jump is
initiated externally rather than by the program.

Memory Read:
An instruction fetch is merely a special memory read
operation that brings the instruction to the CPU's instruction register. The instruction fetched may then call for data
to be read from memory into the CPU. The CPU again issues
a read signal and sends the proper memory address; memory
responds by returning the requested word. The data received is placed in the accumulator or one of the other general purpose registers (not the instruction register).

Memory Write:
A memory write operation is similar to a read except
for the direction of data flow. The CPU issues a write
signal, sends the proper memory address, then sends the data
word to be written into the addressed memory location.

Wait (memory synchronization):

More complex interrupt structures are possible, in
which several interrupting devices share the same processor
but have different priority levels. Interruptive processing is
an important feature that enables maximum untilization of
a processor's capacity for high system throughput.

As previously stated, the activities of the processor
are timed by a master clock oscillator. The clock period
determines the timing of all processing activity.
The speed of the processing cycle, however, is limited
by the memory's Access Time. Once the processor has sent a
read address to memory, it cannot proceed until the memory
has had time to respond. Most memories are capable of
responding much faster than the processing cycle requires.
A few, however, cannot supply the addressed byte within
the minimum time established by the processor's clock.

Hold:
Another important feature that improves the throughput of a processor is the Hold. The hold provision enables
Direct Memory Access (DMA) operations.
In ordinary input and output operations, the processor
itself supervises the entire data transfer. Information to be
placed in memory is transferred from the input device to the
processor, and then from the processor to the designated
memory location. In similar fashion, information that goes

Therefore a processor should contain a synchronization provision, which permits the memory to request a Wait
state. When the memory receives a read or write enable signal, it place's a request signal on the processor's READY line,
causing the CPU to idle temporarily. After the memory has

1-4

from memory to output devices goes by way of the
processor.

having the device accomplish the transfer directly. The pro·
cessor must temporarily suspend its operation during such a
transfer, to prevent conflicts that would arise if processor
and peripheral device attempted to access memory simul·
taneously. It is for this reason that a hold provision is included on some processors.

Some peripheral devices, however, are capable of
transferring information to and from memory much faster
than the processor itself can accomplish the transfer. If any
appreciable quantity of data must be transferred to or from
such a device, then system throughput will be increased by

1-5

Chapter 2
THE 8080 CENTRAL PROCESSING UNIT

THE 8080 CENTRAL PROCESSING UNIT

The 8080 is a complete 8-bit parallel, central processor
unit (CPU) for use in general purpose digital computer systems. It is fabricated on a single LSI chip (see Figure 3-1).
using Intel's n-channel silicon gate MaS process. The 8080
transfers data and internal state information via an 8-bit,
bidirectional 3- state Data Bus (00-07). Memory and peripheral device addresses are transmitted over a separate 16-

bit 3-state Address Bus (AO-A15l. Six timing and control
outputs (SYNC, DBIN, WAIT,WR, HLDA and INTE) emanate from the 8080, while four control inputs (READY,
HOLD, INT and RESET), four power inputs (+12v, +5v,
-5v, and GND) and two clock inputs (4)1 and 4>2) are accepted by the 8080.

A"
A14
A '3

AlO

GND

A12

35

INTE~
10
RESET

11
12

HOLD
INT

A.
As
A3

,.

28

+12V

27

A,

15

26

16

25

Ao

2.
23

WAIT

SYNC

22

+5V

21

"HLDA

WR

2-1

32

29

"

Figure 2-1. 8080 Photo,micrograph With Pin Designations

8080

3'
33

13

17
18

A,

READY

ARCHITECTURE OF THE 8080 CPU

matically during every instruction fetch. The stack pointer
maintains the address of the next available stack location in
memory. The stack pointer can be initialized to use any
portion of read-write memory as a stack. The stack pointer
is decremented when data is "pushed" onto the stack and
incremented when data is "popped" off the stack (i.e., the
stack grows "downward").

The 8080 CPU consists of the following functional
units:
• Register array and address logic
• Arithmetic and logic unit (ALU)
• Instruction register and control section
• Bi-directional, 3-state data bus buffer
Figure 2-2 illustrates the functional blocks within
the 8080 CPU.

The six general purpose registers can be used either as
single registers (8-bit) or as register pairs (16-bit). The
temporary register pair, W,Z, is not program addressable
and is only used for the internal execution of instructions.

Registers:

Eight-bit data bytes can be transferred between the
internal bus and the register array via the register-select
multiplexer. Sixteen-bit transfers can proceed between the
register array and the address latch or the incrementar /
decrementer circuit. The address latch receives data from
any of the three register pairs and drives the 16 address
output buffers (AO-A15), as well as the incrementer/
decrementer circuit. The incrementer/decrementer circuit
receives data from the address latch and sends it to
the register array. The 16-bit data can be incremented or
decremented or simply transferred between registers.

The register section consists of a static RAM array
organized into six 16-bit registers:
• Program counter (PC)
• Stack pointer (SP)
• Six 8-bit general purpose registers arranged in pairs,
referred to as B,C; D,E; and H,L
• A temporary register pair called W,Z
The program counter maintains the memory address
of the current program instruction and is incremented auto-

BI·DIRECTIONAL
DATA BUS

(8 BITI
INTERNAL DATA BUS

B
REG.
D
REG.

I.'

I.'

I.'

I.,

H
REG.

I.,

STACK POINTER
PROGRAM COUNTER

I.'
(16)

(161

(16)

POWER
SUPPLI
ES

1_

TIMING
AND
CONTROL

+12V
+5V

_-5V
-GND

ACK

Figure 2-2. 8080 CPU Functional Block Diagram

2-2

REGISTER
ARRAY

Arithmetic and Logic Unit (ALU):

THE PROCESSOR CYCLE

The ALU contains the following registers:

An instruction cycle is defined as the time required
to fetch and execute an instruction. During the fetch, a
selected instruction (one, two or three bytes) is extracted
from memory and deposited in the CPU's instruction register. During the execution phase, the instruction is decoded
and translated into specific processing activities.

• An 8-bit accumulator
• An 8-bit temporary accumulator (ACT)
• A 5-bit flag regi'ster: zero, carry, sign, parity and
auxiliary carry

Every instruction cycle consists of one, two, three,
four or five machine cycles. A machine cycle is required
each time the CPU accesses memory or an I/O port. The
fetch portion of an instruction cycle requires one machine
cycle for each byte to be fetched. The duration of the execution portion of the instruction cycle depends on the kind
of instruction that has been fetched. Some instructions do
not require any machine cycles other than those necessary
to fetch the instruction; other instructions, however, require additional machine cycles to write or read data to/
from memory or I/O devices. The DAD instruction is an
exception in that it requires two additional machine cycles
to complete an internal register-pair add (see Chapter 4).

• An 8-bit temporary register (TMP)
Arithmetic, logical and rotate operations are performed in the ALU. The ALU is fed by the temporary
register (TMP) and the temporary accumulator (ACT) and
carry flip-flop. The result of the operation can be transferred to the internal bus or to the accumulator; the ALU
also feeds the flag register.
The temporary register (TMP) receives information
from the internal bus and can send all or portions of it to
the ALU, the flag register and the internal bus.

Each machine cycle consists of three, four or five
states. A state is the smallest unit of processing activity and
is defined as the interval between two successive positivegoing transitions of the <1>1 driven clock pulse. The 8080
isdriven by a two-phase clock oscillator. All processing activities are referred to the period of this clock. The two nonoverlapping clock pulses, labeled <1>1 and <1>2, are furnished
by external circuitry. It is the <1>1 clock pulse which divides
each machine cycle into states. Timing logic within the
8080 uses the clock inputs to produce a SYNC pulse,
which identifies the beginning of every machine cycle. The
SYNC pulse is triggered by the low-to-high transition of <1>2,
as shown in Figure 2-3.

The accumulator (ACC) can be loaded from the ALU
and the internal bus and can transfer data to the temporary
accumulator (ACT) and the internal bus. The contents of
the accumulator (ACC) and the auxiliary carry flip-flop can
be tested for decimal correction during the execution of the
DAA instruction (see Chapter 4).

Instruction Register and Control:
During an instruction fetch, the first byte of an instruction (containing the OP code) is transferred from the
internal bus to the 8-bit instruction register.
The contents of the instruction register are, in turn,
available to the instruction decoder. The output of the
decoder, combined with various timing signals, provides
the control signals for the register array, ALU and data
buffer blocks. In addition, the outputs from the instruction
decoder and external control signals feed the timing and
state control section which generates the state and cycle
timing signals.

FIRST STATE OF
'EVERY MACHINE
CYCLE

2

SYNC

Data Bus Buffer:
'SYNC DOES NOT OCCUR IN THE SECOND AND THIRD MACHINE
CYCLES OF A DAD INSTRUCTION SINCE THESE MACHINE CYCLES
ARE USED FOR AN INTERNAL REGISTER-PAIR ADD.

This 8-bit bidirectional 3-state buffer is used to
isolate the CPU's internal bus from the external data bus.
(DO through 07). In the output mode, the internal bus
content is loaded into an 8-bit latch that, in turn, drives the
data bus output buffers. The output buffers are switched
off during input or non-transfer operations.

Figure 2-3.cf>VP2 And SYNC Timing
There are three exceptions to the defined duration of
a state. They are the WAIT state, the hold (H LOA) state
and the halt (HL TA) state, described later in this chapter.
Because the WAIT, the H LOA, and the HL TA states depend
upon external events, they are by their nature of indeterminate length. Even these exceptional states, however, must

During the input mode, data from the external data bus
is transferred to the internal bus. The internal bus is precharged at the beginning of each internal state, except for
the transfer state (T3-described later in this chapter).

2-3

be synchronized with the pulses of the driving clock. Thus,
the duration of all states are integral mUltiples of the clock
period.

the contents of its Hand L registers. The eight-bit data
word returned during this MEMORY READ machine cycle
is placed in a temporary register inside the 8080 CPU. By
now three more clock periods (states) have elapsed. In the
seventh and final state, the contents of the temporary register are added to those of the accumulator. Two machine
cycles, consisting of seven states in all, complete the
"ADD M" instruction cycle.

To summarize then, each clock period marks a state;
three to five states constitute a machine cycle; and one to
five machine cycles comprise an instruction cycle. A full
instruction cycle requires anywhere from four to eight·
teen states for its completion, depending on the kind of instruction involved.

At the opposite extreme is the save Hand L registers
(SHLD) instruction, which requ.ires five machine cycles.
During an "SH LD u instruction cycle, the contents of the
processor's Hand L registers are deposited in two sequentially adjacent memory locations; the destination is indicated by two address bytes which are stored in the two
memory locations immediately following the operation code
byte. The following sequence of events occurs:

Machine Cycle Identification:
With the exception of the DAD instruction, there is
just one consideration that determines how many machine
cycles are required in any given instruction cycle: the number of times that the processor must reference a memory
address or an addressable peripheral device, in order to
fetch and execute the instruction. Like many processors,
the 8080 is so constructed that it can transmit only one
address per machine cycle. Thus, if the fetch and execution
of an instruction requires two memory references, then the
instruction cycle associated with that instruction consists of
two machine cycles. If five such references are called for,
then the instruction cycle contains five machine cycles.
Every instruction cycle has at least one reference to
memory, during which the instruction is fetched. An instruction cycle must always have a fetch, even if the execution of the instruction requires no further references to
memory. The first machine cycle in every instruction cycle
is therefore a FETCH. Beyond that, there are no fast rules.
It depends on the kind of instruction that is fetched.
Consider some examples. The add-register (ADD r)
instruction is an instruction that requires only a single
machine cycle (FETCH) for its completion. In this one-byte
instruction, the contents of one of the CPU's six general
purpose registers is added to the existing contents of the
accumulator. Since all the information necessary to execute
the command is contained in the eight bits of the instruction
code, only one memory reference is necessary. Three states
are used to extract the instruction from memory, and one
additional state is used to accomplish the desired addition.
The entire instruction cycle thus requires only one machine
cycle that consists of four states, or four periods of the external clock.

(1)

A FETCH machine cycle, consisting of four
states. During the first three states of this
machine cycle, the processor fetches the instruction indicated by its program counter. The program counter is then incremented. The fourth
state is used for internal instruction decoding.

(2)

A MEMORY READ machine cycle, consisting
of three states. During this machine cycle, the
byte indicated by the program counter is read
from memory and placed in· the processor's
Z register. The program counter is incremented
again.

(3)

Another MEMORY READ machine cycle, consisting of three states, in which the byte indicated by the processor's program counter is read
from memory and placed in the W register. The
program .counter is incremented, in anticipation
of the next instruction fetch.

(4)

A MEMORY WRITE machine cycle, of three
states, in which the contents of the L register
are transferred to the memory location pointed
to by the present contents of the Wand Z registers. The state following the transfer is used to
increment the W,Z register pair so that it indicates the next memory location to receive data.

(5)

A MEMORY WRITE machine cycle, of three
states, in which the contents of the H register
are transferred to the new memory location
pointed to by the W,Z register pair.

Suppose now, however, that we wish to add the contents of a specific memory location to the existing contents
of the accumulator (ADD M). Although this is quite similar
in principle to the example just cited, several additional
steps will be used. An. extra machine cycle will be used, in
order to address the desired memory location.

In summary, the "SHLD" instruction cycle contains
five machine cycles and takes 16 states to execute.

The actual sequence is as follows. First the processor
extracts from memory the one-byte instruction word addressed by its program counter. This takes three states.
The eight-bit instruction word obtained during the FETCH
machine cycle is deposited in the CPU's instruction register
and used to direct activities during the remainder of the
instruction cycle. Next, the processor sends out,as an address,

Most instructions fall somewhere between the extremes typified by the "ADD r" and the "SHLD" instructions. The input (I NP) and the output (OUT) instructions,
for example, require three machine cycles: a FETCH, to
obtain the instruction; a MEMORY READ, to obtain the
address of the object peripheral; and an INPUT or an OUTPUT machine cycle, to complete the transfer.

2-4

While no one instruction cycle will consist of more
then five machine cycles, the following ten different types
of machine cycles may occur within an instruction cycle:
(1 )

FETCH (M1)

(2)

MEMORY READ

(3)

MEMORY WRITE

(4)

STACK READ

(5)

STACK WRITE

(6)

INPUT

(7)

OUTPUT

(8)

INTERRUPT

(9)

HALT

(10)

basic transition sequence. In the present discussion, we are
concerned only with the basic sequence and with the
READY function. The HOLD and INTERRUPT functions
will be discussed later.
The 8080 CPU does not directly indicate its internal
state by transmitting a "state control" output during
each state; instead, the 8080 supplies direct control output
(lNTE, HLDA, DBIN, WR and WAIT) for use by external
circuitry.
Recall that the 8080 passes through at least three
states in every machine cycle, with each state defined by
successive low-to-high transitions of the <1>1 clock. Figure
2-5 shows the timing relationships in a typical FETCH
machine cycle. Events that occur in each state are referenced
to transitions of the <1>1 and <1>2 clock pulses.
The SYNC signal identifies the first state (T 1) in
every machine cycle. As shown in Figure 2-5, the SYNC
signal is related to the leading edge of the <1>2 clock. There is
a delay (tDC) between the low-to-high transition of <1>2 and
the positive-going edge of the SYNC pulse. There also is a
corresponding delay (also tDC) between the next <1>2 pulse
and the falling edge of the SYNC signal. Status information
is displayed on 00-07 during the same <1>2 to <1>2 interval.
Switching of the status signals is likewise controlled by <1>2.

HALT .INTERRUPT

The machine cycles that actually do occur in a particular instruction cycle depend upon the kind of instruction, with the overriding stipulation that the first machine
cycle in any instruction cycle is always a FETCH.
The processor identifies the machine cycle in progress by transmitting an eight-bit status word during the first
state of every machine cycle. Updated status information is
presented on the 8080's data lines (00-07), during the
SYNC interval. This data should be saved in latches, and
used to develop control signals for external circuitry. Table
2-1 shows how the positive-true status information is distributed on the processor's data bus.

The rising edge of <1>2 during T 1 also loads the processor's address lines (AO-A 15). These lines become stable
within a brief delay (tDA) of the <1>2 clocking pulse, and
they remain stable until the first <1>2 pulse after state T3.
This gives the processor ample time to read the data returned from memory.
Once the processor has sent an address to memory,
there is an opportunity for the memory to request a WAIT.
This it does by pulling the processor's READY line low,
prior to the "Ready set-up" interval (tRS) which occurs
during the <1>2 pulse within state T2 or TW- As long as the
READY line remains low, the processor will idle, giving the
memory time to respond to the addressed data request_
Refer to Figure 2-5.

Status signals are provided principally for the control
of external circuitry. Simplicity of interface, rather than
machine cycle identification, dictates the logical definition
of individual status bits. You will therefore observe that
certain processor mach ine cycles are uniquely identified by
a single status bit, but that others are not. The M 1 status
bit (06), for example, unambiguously identifies a FETCH
machine cycle. A STACK READ, on - the other hand, is
indicated by the coincidence of STACK and MEMR signals. Machine cycle identification data is also valuable in
the test and de-bugging phases of system development.
Table 2-1 lists the status bit outputs for each type of
machine cycle.

The processor responds to a wait request by entering
an alternative state (TW) at the end of T2, rather than proceeding directly to the T3 state. Entry into the TW state is
indicated by a WAIT signal from the processor, acknowledging the memory's request. A low-to-high transition on the
WAIT line is triggered by the rising edge of the <1>1 clock and
occurs within a brief delay (tDC) of the actual entry into
the TW state.

State Transition Sequence:
Every machine cycle within an instruction cycle consists of three to five active states (referred to as T 1, T 2, T 3,
T 4, T5 or TW). The actual number of states depends upon
the instruction being executed, and on the particular machine cycle within the greater instruction cycle. The state
transition diagram in Figure 2-4 shows how the 8080 proceeds from state to state in the course of a machine cycle.
The diagram also shows how the READY, HOLD, and
INTER RUPT lines are sampled during the machine cycle,
and how the conditions on these lines may modify the

A wait period may be of indefinite duration. The processor remains in the waiting condition until its READY line
again goes high. A READY indication must precede the faIling edge of the <1>2 clock by a specified interval (tRS), in
order to guarantee an exit from the T W state_ The cycle
may then proceed, beginning with the rising edge of the
next <1>1 clock. A WAIT interval will therefore consist of an
integral number of TW states and will always be a multiple
of the clock period.

2-5

/.0

Instructions for the 8080 require from one to five machine
cycles for complete execution. The 8080 sends out 8 bit of
status information on the data bus at the beginning of each
machine cycle (during SYNC time). The following table defines
the status information.

,

8080 STATUS LATCH

0,
0,
0,
0,
0,
0,
D.

9

0,

°

STATUS INFORMATION DEFINITION
Data Bus
Symbols
Definition
Bit
INTA*
Acknowledge signal for INTERRUPT reo
Do
quest. Signal should be used to gate are·
start instruction onto the data bus when
DBIN is active.
Indicatesthat the operation in the current
0,
machine cycle will be a WR ITE memory
or OUTPUT function (WO ~ 0). Otherwise,
a READ memory or INPUT operation will
be ex ecu ted.
STACK
Indicates that the address bus holds the
O2
pushdown stack address from the Stack
Pointer.
HLTA
Acknowledge signal for HALT instruction.
D3
Indicates that the address bus contains the
OUT
D4
address of an output device and the data
bus will contain the output data when
WR is active.
M,
Provides a signal to indicate that the CPU
DS
is in the fetch cycle for the first byte of
an instruction.
INP*
Indicates that the address bus contains the
D6
address of an input device and the input
data should be placed on the data bus
when DB IN is active.
MEMR*
Designates that the data bus will be used
D7
for memory read data.

,
0,
0,
0,
D.
0,

8080

SYNC

DBIN
,,2

01

22

87
3
4

5
6

0,

~
~

STATUS
LATCH

15

~D
5

'----i

Do

'

8212

20
22

-.1TTLi

I

r,i g~:

To-

STACK

it:

INP
MEMR

HlTA
15 OUT
"iT
f,- M'

16

18

1.

INTA

~

'-----i
CLOCK GEN
& DRIVER

f- we

MO 55·,

13 12

)"
DBIN

r----'

OAT A

STATUS

*These three status bits can be used to control

>---"--l-+-

f....---.f-J'---I

the flow of data onto the 8080 data bus.

STATUS WORD CHART
TYPE OF MACHINE CYCLE
I

STATUS WORD
Do
INTA
a a a a a a a , a
,
rD:-"'-+~W"'O~-+--'--+-'-+ ··....:0-1--"-1--'-0-+--'-'-+--=0-+-'-'+-,=--+--=,-1

INP

a
a
a
,
a

a
a
a
a
a

MEMR

1

,

02
03

STACK

04

OUT

Os
06
07

M,

HL TA

a
a
a
a
a
a

,
a
a
a
a
,

,
a
a
a
a
a

a
a
a
a
1
a

Table 2-1. 8080 Status Bit Definitions

2-6

a
a
,
a
a
a

a
a
a
1
a
a

a
,
a
a
a
,

a
,
a
1
a
a

GJ~RESET

Till

READY + Hl TA

<$>

121

HLTA

READY. HL TA

-

YES

NO

Q,..

READY

1.-------------------------1~AEADY
INT. INTE

YES

1

7?__---'.- ___ _

L -_ _

m

I HOLD
! MODE

~
~

HOLD

I
I

I

_ _ .J

YES

NO

NO

NO

SET lNTERNAL

lNT F/F
(11INTE F/F IS RESET IF INTERNAL I.NT F/F IS SET.
(2)INTERNAlINT F/F IS RESET IF INTE F/F IS RESET.
(3I SEE PAGE 2·13.

Figure 2-4. CPU State Transition Diagram

2-7

data must remain stable during the "data hold" interval
(tDH) that occurs following the rising edge of the tP2 pulse.
Data placed on these Iines by memory or by other external
devices will be sampled during T3.

The events that take place during the T3 state are
determined by the kind of machine cycle in progress. In a
FETCH machine cycle, the processor interprets the data on
its data bus as an instruction. During a MEMORY READ or
a STACK READ, data on this bus is interpreted as a data
word. The processor outputs data on th is bus during a
MEMORY WR ITE machine cycle. During I/O operations,
the processor may either transmit or receive data, depending on whether an OUTPUT or an INPUT operation
is involved.

During the input of data to the processor, the 8080
generates a DBIN signal which should be used externally to
enable the transfer. Machine cycles in which DBIN is avail·
able include: FETCH, MEMORY READ, STACK READ,
and INTERRUPT. DBIN is initiated by the rising edge of rf>2
during state T2 and terminated by the corresponding edge of
rf>2 during T3. Any TW phases intervening between T2 and
T3 will therefore extend DBIN by one or more clock
periods.

Figure 2-6 illustrates the timing that is characteristic
of a data input operation. As shown, the low·to·high transi·
tion of rf>2 during T2 clears status information from the pro·
cessor's data lines, preparing these lines for the receipt of
incoming data. The data presented to the processor must
have stabilized prior to both the "rf>l-data set·up" interval
(tDS1), that precedes the falling edge of the rf>1 pulse defin·
ing state T3, and the "rf>2-data set·up" interval (tDS2)'
that precedes the rising edge of rf>2 in state T 3. This same

T,

T,

., n

W

L

----.1
/
I

/

n
I

~

---1

n

h

L --1

LW
X

-----..... --L-.

X

®

!~

-'

I
SYNC

n

T,

T,

T,

Tw

--

r\

Figure 2·7 shows the timing of a machine cycle in
wh ich the processor outputs data. Output data may be des·
tined either for memory or for peripherals. The rising edge
of rf>2 within state T2 clears status information from the
CPU's data lines, and loads in the data which is to be output
to external devices. This substitution takes place within the

DATA
STABLE

\

WRITE MODE

UNKNOWN

--- -------FLOATING

FLOATING

t--- READ MODE

/

READY

lJ

WAIT

\

j

DBIN

STATUS
I INFORMATION

SAMPLE READY
HOLD AND HALT

A15-0

MEMORY ADDRESS

OR
I/O DEVICE NUMBER
STATUS INFORMATION
INTA
OUT

wo

INP

STACK

\
OPTIONAL

--

OR
WRITE DATA

M,

I
NOTE:

®

FETCH DATA
OR
INSTRUCTION

HALT
OR
MEMORY
ACCESS TIME
ADJUST

07_0

HlTA
MEMR

DATA

DATA

I

Refer to Status Word Chart on Page 2·6.

Figure 2-5. Basic 8080 Instruction Cycle

2-8

L

OPTIONAL
INSTRUCTION
EXECUTION
IF REQUIRED

r
SYNC

DBIN
READY
WAIT
WR

STATUS
INFORMATION

+----H-..J
+~---H----+------r-----~r-----~-------+------r------r----~--~
-r~----~-----+------~----~-----~------+-----r-------r----~------­

~~--++----~------~------t-----~------~------t------+------~-------

+--~

NOTE:

@

Refer to Status Word Chart on Page 2·6.

Figure 2-6. Input Instruction Cycle

M,
T,

M,

T,

T,

T,

T4

M:J
T,

T,

M,

T,

T,

T;~

T3

tL- h-h- h- fL- n- h- fL- h- rL- nLn w---t LJ\-U\ lI1l-F1knU\ w---t w---t Wf-J
D,·o
SYNC

DBIN

BYTE
ONE

~

I-

~h
i

__ J

1

UN'KNOWN

----

FLOATING

-

/

U __ J

I

J h

I

"0"

WAIT

I
STATUS
INFORMATION

I
NOTE:

,- -

/

X

ACCUMULATOR

h

I

I

"1"

I
i

I/O DEVICE
NUMBER

X

I 1\

\

I

READY

BYTE
TWO

I

1

I

I

1/0
@

~0

Refer to Status Word Chart on Page 2·6.

Figure 2·7. Output Instruction Cycle

2-9

\

I

_l~ CD

1

r-

"data output delay" interval (tDD) following the 1>2 clock's
leading edge. Data on the bus remains stable throughout
the remainder of the machine cycle, until replaced by up·
dated status information in the subsequent T 1 state. Observe
that a READY signal is necessary for completion of an
OUTPUT machine cycle. Unless such an indication is pres·
ent, the processor enters the TW state, following the T2
state. Data on the output lines remains stable in the
interim, and the processing cycle will not proceed until
the READY line again goes high.
The 8080 CPU generates a WR output for the syn·
chronization of external transfers, during those machine
cycles in which the processor outputs data. These include
MEMORY WRITE, STACK WRITE, and OUTPUT. The
negative-going leading edge of WR is referenced to the rising
edge of the first 1>1 clock pulse following T2, and occurs
within a brief delay (tDC) of that event. WR remains low
until re-triggered by the leading edge of 1>1 during the
state following T 3. Note that any TW states intervening
between T2 and T3 of the output machine cycle will neces-

sarily extend WR, in much the same way that DBIN is affected during data input operations.
All processor machine cycles consist of at least three
states: T 1, T2, and T3 as just described. If the processor has
to wait for a response from the peripheral or memory with
which it is communicating, then the machine cycle may
also contain one or more TW states. During the three basic
states, data is transferred to or from the processor.
After the T3 state, however, it becomes difficult to
generalize. T 4 and T5 states are available, if the execution
of a particular instruction requires them. But not all machine
cycles make use of these states. It depends upon the kind of
instruction being executed, and on the particular machine
cycle within the instruction cycle. The processor will terminate any machine cycle as soon as its processing activities
are completed, rather than proceeding through the T 4 and
T5 states every time. Thus the 8080 may exit a machine
cycle following the T3, the T 4, or the T5 state and proceed directly to the T 1 state of the next machine cycle.

ASSOCIATED ACTIVITIES

STATE

A memory address or I/O device number is
placed 1 clock pulse. Normal processing resumes with the machine cycle following the last cycle that was executed.
,

I

HALT SEQUENCES
When a halt instruction (HL T) is executed, the CPU
enters the halt state (T WH) after state T2 of the next machine cycle, as shown in Figure 2-11. There are only three
ways in which the 8080 can exit the halt state:
•

A high on the RESET line will always reset the
8080 to state T 1; RESET also clears the program
counter.
• A HO LD input wi II cause the 8080 to enter the
hold state, as previously described. When the
HOLD line goes low, the 8080 re-enters the halt
state on the rising edge of the next <1>1 clock
pulse.
• An interrupt (i.e., INT goes high while INTE is
enabled) will cause the 8080 to exit the Halt state
and enter state T 1 on the rising edge of the next
<1>1 clock pulse. NOTE: The interrupt enable (INTE)
flag must be set when the halt state is entered;
otherwise, the 8080 will only be able to exit via a
RESET signal.

Like the interrupt, the HO LD input is synchronized
internally. A HOLD signal must be stable prior to the "Hold
set-up" interval (tHS), that precedes the rising edge of <1>2.
Figures 2·9 and 2-10 illustrate the timing involved in
HOLD operations. Note the delay between the asynchronous
HOLD REQUEST and the re-clocked HOLD. As shown in
the diagram, a coincidence of the READY, the HOLD, and
the <1>2 clocks sets the internal hold latch. Setting the latch
enables the subsequent rising edge of the <1>1 clock pulse to
trigger the H LOA output.
Acknowledgement of the HOLD REQUEST precedes
slightly the actual floating of the processor's address and
data lines. The processor acknowledges a HO LD at the begin·
ning of T3, if a read or an input machine cycle is in progress
(see Figure 2-9). Otherwise, acknowledgement is deferred
until the beginning of the state following T3 (see Figure
2-10). In both cases, however, the HLDA goes high within
a specified delay (tDC) of the rising edge of the selected <1>1
clock pulse. Address and data lines are floated within a
brief delay after the rising edge of the next <1>2 clock pulse.
This relationship is also shown in the diagrams.
To all outward appearances, the processor has suspended its operations once the address and data busses are floated.
Internally, however, certain functions may continue. If a
HOLD REQUEST is acknowledged at T3, and if the processor is in the middle of a machine cycle which requires
four or more states to complete, the CPU proceeds through
T 4 and T5 before coming to a rest. Not until the end of the
machine cycle is reached will processing activities cease.
Internal processing is thus permitted to overlap the external
DMA transfer, improving both the efficiency and the speed
of the entire system.
The processor exits the holding state through a
sequence similar to that by which it entered. A HOLD
REQUEST is terminated asynchronously when the external
device has completed its data transfer. The HLDA output

2-13

Figure 2-12 illustrates halt sequencing in flow chart
form.

START-UP OF THE 8080 CPU
When power is applied initially to the 8080, the processor begins operating immediately. The contents of its
program counter, stack pointer, and the other working registers are naturally subject to random factors and cannot be
specified. For this reason, it will be necessary to begin the
power-up sequence with RESET.
An external RESET signal of three clock period duration (minimum) restores the processor's internal program
counter to zero. Program execution thus begins with memory location zero, following a RESET. Systems which require the processor to wait for an explicit start·up signal
will store a halt instruction (EI, H LT) in the first two locations. A manual or an automatic INTER RUPT will be used
for starting. In other systems, the processor may begin executing its stored program immediately. Note, however, that
the RESET has no effect on status flags, or on any of the
processor's working registers (accumulator, registers, or
stack pointer). The contents of these registers remain indeterminate, until initialized explicitly by the program.

I-

M,
T,

----

----

~~~-.--

T,

T3

T2

M2

T2

T,

TWH

TWH

n
n
nn
r1
h
r1
-".w---t-....JL,....JL
J \ . . f----JL f----JL ---1L ..JI..
1

I

~pc

SYNC

f--J
!--I

- - - - -- -

I

-

I
I

I

I

\

I

DBIN

I

\

I

\

I
I

i

WAIT

--1---- t---- - - --- ---

II
I

V0

I

I

STATUS
INFORMATION

~0

1

I

NOTE

®

Refer to Status Word Chart on Page 2-6

Figure 2·11. HALT Timing

TO STATE
TW or T3

TO STATE

T,

TO STATE T,

Figure 2·12. HALT Sequence Flow Chart.

2·14

RESET
INTERNAL
RESET

+-___-jI

SYNCf-________

~------~--------+_------~~--------~--------~--~

DBINf-________

~------~--------+_------~~--------~--------~------_+----J

STATUS
INFORMATION

I

I

I

I

I

•

(l)WHEN RESET SIGNAL IS ACTIVE, ALL OF CONTROL OUTPUT SIGNALS WILL BE RESET IMMEDIATELY OR SOME
CLOCK PERIODS LATER. THE RESET SIGNAL MUST BE ACTIVE FOR A MINIMUM OF THREE CLOCK CYCLES. IN
THE ABOVE DIAGRAM N AND I MAY BE ANY INTEGER.

NOTE:

®

Aeler to St.tusWord Ch.rt on Page 2·6

Figure 2-13. Reset.

M,
TWH

TWH

TWH

TWH

TWH

TWH

T,

TWH

T,

T,

rL- h- rL- ~i'I . L - - L - ~
h--F"""\ W'I..---.Jl--F"""\ JrL .Jl~n. Wl-Jl~

h-h-

=

0,0
SYNC

- ~-I -----11
-- --,.. - _.

~~O~T:G= t ==
=

I
I

DB IN

!

HOLD
HOLD F/F
(INTERNAL)

i

I

,/

I FLO ATING

;
\... RST_ J

I
I

,-

I

,-

'-

I

r--

HLDA
INTE

i

I

INT

i

I

INT F/F
(INTERNAL)

I

STATUS
INFORMATION

I

I

INHIBIT

INT

®

INHIBIT
HOLD

I

)

~@

0
I
NOTE:

i

Refer to Stat"sWord Chart on Page 2·6

Figure 2·14. Relation between HOLD and INT in the HALT State.

2-15

!

2-16

2-17

1 1 N N

N 1

1

1

PCHL

1

1

1 0

1

a

0

1

PUSH rp

1

1 R P

o

1 0 ..1

PUSHPSW

1

1

o

1 0

1

1

1

PC OUT
STATUS

PC = PC + 1 INST.-..TMP/IR

2-18

2-19

NOTES:
1. The first memory cycle (M1) is always an instruction
fetch; the first (or only) byte, containing the op code, is
fetched during this cycle.
2. If theR EADY input from memory is not high during
T2 of each memory cycle, the processor will enter a wait
state (TW) until READY is sampled as high.
3. States T4 and T5 are present, as required, for operations which are completely internal to the CPU. The con·
tents of the internal bus during T4 and T5 are available at
the data bus; this is designed for testing purposes only. An
"X" denotes that the state is present, but is only used for
such internal operations as instruction decoding.

12. If the condition was met, the contents of the register
pair WZ are output on the address lines (AO-15) instead of
the contents of the program counter (PC).
13. If the condition was not met, sub·cycles M4 and M5
are skipped; the processor instead proceeds immediately to
the instruction fetch (M1) of the next instruction cycle.
14. If the condition was not met, sub-cycles M2 and M3
are ski pped; the processor instead proceeds immediately to
the instruction fetch (M1) of the next instruction cycle.
15. Stack read sub-cycle.
16. Stack write sub·cycle.
17. CONDITION
NZ
Z
NC
C
PO
PE
P
M

4. Only register pairs rp = B (registers B and C) or rp= D
(registers D and E) may be specified.
5.

These states are skipped.

6. Memory read sub·cycles; an instruction or data word
will be read.
7.

Memory write sub·cycle.

8. The READY signal is not required during the second
and third sub-cycles (M2and M3). The HOLD signal is
accepted during M2 and M3. The SYNC signal is not generated during M2 and M3. During the execution of DAD,
M2 and M3 are required for an internal register·pair add;
memory is not referenced.
9. The results of these arithmetic, logical or rotate instructions are not moved into the accumulator (A) until
state T2 of the next instruction cycle. That is, A is loaded
while the next instruction is being fetched; this overlapping
of operations allows for faster processing.
10. If the value of the least significant 4-bits of the accumu·
lator is greater than 9 or if the auxiliary carry bit is set, 6
is added to the accumulator. If the value of the most signifi·
cant 4-bits of tile accumulator is now greater than 9, or if
the carry bit is set, 6 is added to the most significant 4·bits of the accumulator.

-

CCC

not zero (Z = 0)
zero (Z = 1)
no carry ICY = 0)
carry ICY = 1)
parity odd (P = 0)
parity even (P = 1)
plus (S = 0)
minus (S= 1)

000
001
010
011
100
101
110
111

18. I/O sub·cycle: the I/O port's 8-bit select code is dupli·
cated on address lines 0·7 (A0-7) and 8-15 (AS.15).
19. Output sub·cycle.
20. The processor will remain idle in the halt state until
an interrupt, a reset or a hold is accepted. When a hold reo
quest is accepted, the CPU enters the hold mode; after the
hold mode is terminated, the processor returns to the halt
state. After a reset is accepted, the processor begins execu·
tion at memory location zero. After an interrupt is accepted,
the processor executes the instruction forced onto the data
bus (usually a restart instruction).
SSSor DOD
A
B
C
0
E
H
L

11. This represents the first sub-cycle (the instruction
fetch) of the next instruction cycle.

2-20

Value
111
000
001
010
011
100
101

rp

B
0
H
SP

Value
00
01
10
11

.
,

Chapter 3

INTERFACING THE 8080

INTERFACING THE 8080

This chapter will illustrate, in detail, how to interface
the 8080 CPU with Memory and I/O. It will also show the
benefits and tradeoffs encountered when using a variety of
system architectures to achieve higher throughput, de·
creased component count or minimization of memory size.

Control Bus

A uni-directional set of signals that indicate
the type of activity in current process.
Type of activities: 1.
2.
3.
4.
5.

8080 Microcomputer system design Iends itself to a
simple, modular approach. Such an approach will yield the
designer a reliable, high performance system that contains a
minimum component count and is easy to manufacture and
maintain.

Memory Read
Memory Write
I/O Read
I/O Write
Interrupt Acknowledge

The overall system can be thought of as a simple
block diagram. The three (3) blocks in the diagram repre·
sent the functions common to any computer system.

CPU Module* Contains the Central Processing Unit, system
timing and interface circuitry to Memory
and I/O devices.
Memory

Contains Read Only Memory (ROM) and
Read/Write Memory (RAM) for program and
data storage.

I/O

Con·tains circuitry that allows the computer
system to communicate with devices or
structures existing outside of the CPU or
Memory array.

CPU

MODULE

Figure 3-1. Typical Computer System Block Diagram

Basic System Operation

for example: Keyboards, Floppy Disks,
Paper Tape, etc.

1.

The CPU Module issues an activity command on the
Control Bus.

2.

The CPU Module issues a binary code on the Address
Bus to identify which particular Memory location or
I/O device will be involved in the current process
activity.

3.

The CPU Module receives or transmits data with the
selected Memory location or I/O device.

*"Module" refers to a functional block, it does not reference a printed circuit board manufactured by INTE L.

4.

The CPU Module returns to
activity command.

t"Bus" refers to a set of signals grouped together because
of the similarity of t~eir functions.

It is easy to see at this point that the CPU module is
the central element in any computer system.

There are three busses that interconnect these blocks:
Data Bust

A bi-directional path on which data can flow
between the CPU and Memory or I/O.

Address Bus

A uni-directional group of lines that identify
a particular Memory location or I/O device.

3-1

CD

and issues the next

the design and to achieve operational characteristics that
are as close as possible to those of the 8224 and 8228.
Many auxiliary timing functions and features of the 8224
and 8228 are too complex to practically implement in
standard components, so only the basic functions of the
8224 and 8228 are generated. Since significant benefits in
system timing and component count reduction can be
realized by using the 8224 and 8228, this is the preferred
method of implementation.

The following pages will cover the detailed design of
the CPU Module with the 8080. The three Busses (Data,
Address and Control) will be developed and the intercon·
nection to Memory and I/O will be shown.
Design philosophies and system architectures presented in this manual are consistent with product development programs underway at INTEL for the MCS~80. Thus,
the designer who uses this manual as a guide for his total
system engineering is assured that all new developments in
components and software for MCS-80 from INTEL will be
compatible with his design approach.

1.

8080 CPU
The operation of the 8080 CPU was covered in previous chapters of this manual, so little reference will
be made to it in the design of the Module.

CPU Module Design
The CPU Module contains three major areas:

1.

The 8080 Central Processing Unit

2.

A Clock Generator and High Level Driver

3.

A bi-directional Data Bus Driver and System Control
Logic

2.

The following will discuss the design of the three
major areas contained in the CPU Module. This design is
presented as an alternative to the Intel® 8224 Clock Generator and Intel 8228 System Controller. By studying the
alternative approach, the designer can more clearly see the
considerations involved in the specification and engineering
of the. 8224 and 8228. Standard TTL components and Intel
general purpose peripheral devices are used to implement

The 8080 requires two (2) such Clocks. Their waveforms must be non-overlapping, and comply with the
timing and levels specified in the 8080 A.C. and D.C.
Characteristics, page 5-15.
Clock Generator Design
The Clock Generator consists of a crystal controlled,

GND

AD

'5V
-5V

Al

+12V

A3

A2
A4
A5

8080
CPU

A6
A7
A8
A9

SYSTEM DMA REO.

Clock Generator and High Level Driver
The 8080 is a dynamic device, meaning that its internal storage elements and logic circuitry require a
timing reference (Clock), supplied by external circuitry, to refresh and provide timing control signals.

25

AD

26

Al

27

A2

29

A3

30

A4

31

A5

32

A6

33

A7

34
35

A9

Al0
All
SYSTEM INT. REO.

INT

A12
A13

INT. ENABLE

INTE

A14
A15

WR
DBrN
HLDA
01
02

WAIT REO.

AlO
40

All

37

A12

38

A13

39

A14

36

A15

18

17

21

D80
Dl

D81

D2

D82

WAIT

D3

D83

READY

D4

D84

05

DB5

06

086

07

087

RESET
SYNC

ADDRESS BUS

A8

J"''''"'

~""J
MEMR

0----+ MEM W

----+

liOR

o---+17fJW

Figure 3-2. 8080 CPU Interface

3-2

CONTAOL BUS

OSCILLATOR

~
330

74804

20MH,
330

...

~-{>O~~{)~-------------------------T-----------------+ OSC
CLOCK GENERATOR

I

I---;:::=:::::JC>----f~~!_--------------_ ii ITTll

1...-=j;;:-;-..;rJII----;==l[:>--~r~o-j----------------.... i2 ITTll
AUXILIARY FUNCTIONS
SYNC
74HOO

'-------1--10
74874

WAVEFORMS

ClK lll-+-------_+ ~IA (TTll

LJ
WAIT REO

-----I-l 0

0
74574

rl__--;r-- 50ns
1A) that is handy
to use in clocking "0" type flipflops to synchronize
external requests. It can also be used to generate a
strobe (STSTB) that is the latching signal for the status information which is available on the Data Bus at
the beginning of each machine cycle. A simple gating
of the SYNC signal from the 8080 and the advanced
(t/>1A) will do the job. See Figure 3-3.

Bi-Directional Data Bus Driver Design
The 8080 Data Bus (07·00) has two (2) major areas
of concern for the designer:
1. Input Voltage level (V 1H ) 3.3 volts minimum.
2. Output Drive Capability (lOL) 1.7 mA maximum.

BUSEN

-

3

2;4 r 5.7 r 9.11,
12.14,

DO
01
02
03

cs

i5iTrii
2.4,

04
05
06
07

,r-., ...
.....
....

cs

4 INTA

9
16
18
20
22

........

STSTS--.ii

pY-"

~K

--7

808 0

13

~

15\'

3

6
10

8216
OlEN

-S

WR

3

5,7 r 9,11r12.14,

OBIN

13

8212

~
15 OUT
17 Ml

1"9iNP
21 MEMR

r

......

3·4

pY-

LU-

~,Vee

Figure 3-5. 8080 System Control

OBO
DBl
DB2
DB3

~

15'1'

-

6
10

8216

LL.»-

OB4
DB5
DB6
DB7

The input level specification implies that any semiconductor memory or I/O device connected to the
8080 Data Bus must be able to provide a minimum of
3_3 volts in its high state_ Most semiconductor memories and standard TTL I/O devices have an output
capability of between 2_0 and 2_8 volts, obviously a
direct connection onto the 8080 Data Bus would require pullup resistors, whose value should not affect
the bus speed or stress the drive capability of the
memory or I/O components_

Status information_ The signal that loads the data
into the Status Latch comes from the Clock Generator, it is Status Strobe (STSTB) and occurs at the
start of each Machine Cycle_
Note that the Status Latch is connected onto the
8080 Data Bus (07-00) before the Bus Buffer_ This is
to maintain the integrity of the Data Bus and simplify
Control Bus timing in DMA dependent environments_
As shown in the diagram, a simple gating of the outputs of the Status Latch with the DBIN and WR
signals from the 8080 generate the (4) four Control
signals that make up the basic Control Bus_

The 8080A output drive capability (lo L) 1_9mA max_
is sufficient for small systems where Memory size and
I/O requirements are minimal and the entire system is
contained on a single printed circuit board_ Most systems however, take advantage of the high-performance computing power of the 8080 CPU and thus a
more typical system would require some form of buffering on the 8080 Data Bus to support a larger array
of Memory and I/O devices which are likely to be on
separate boards_

These four signals: 1. Memory Read(MEM R)
2_ Memory Write (MEM W)
3_ I/O Read (I/O R)

4_ I/O Write (I/O W)

A device specifically designed to do this buffering
function is the INTE~ 8216, a (4) four bit bi-directiona I bus driver whose input voltage leve~ compatible with standard TTL devices and semiconductor
memory components, and has output drive capability
of 50 mA_ At the 8080 side, the 8216 has a "high"
output of 3_65 volts that not only meets the 8080
input spec but provides the designer with a worse case
350 mV noise margin_

connect directly to the MCS~80 component "family"
of ROMs, RAMs and I/O devices_
A fifth signal, Interrupt Acknowledge (I NT A) is
added to the Control Bus by gating data off the
Status Latch with the DB IN signal from the 8080
CPU_ This signal is used to enable the Interrupt
Instruction Port which holds the RST instruction
onto the Data Bus_

A pair of 8216's are connected directly to the 8080
Data Bus (D7-DO) as shown in figure 3-5_ Note that
the DBI N signal from the 8080 is connected to the
direction control input (DIEN) so the correct flow of
data on the bus is maintained_ The chip select (CS) of

Other signals that are part of the Control Bus such as
WO, Stack and M1 are present to aid in the testing of
the System and also to simplify interfacing the CPU
to dynamic memories or very large systems that require several levels of bus buffering_

the 8216 is connected to BUS ENABLE (BUSEN) to
allow for DMA activities by deselecting the Data Bus
Buffer and forcing the outputs of the 8216's into
their high impedance (3-state) mode_ This allows
other devices to gain access to the data bus (DMA).

Address Buffer Design
The Address Bus (A 15-AO) of the 8080, like the Data
Bus, is sufficient to support a small system that has a
moderate size Memory and I/O structure, confined to
a single card_ To expand the size of the system that
the Address Bus can support a simple buffer can be
added, as shown in figure 3-6_ The I NTEL® 8212 or
8216 is an excellent device for this function_ They
provide low input loading (.25 mAl, high output
drive and insert a minimal delay in the System
Timing_

System Control Logic Design
The Control Bus maintains discipline of the bi-directional Data Bus, that is, it determines what type of
device will have access to the bus (Memory or I/O)
and generates signals to assure that these devices
transfer Data with the 8080 CPU within the proper
timing "windows" as dictated by the CPU operational
characteristics_
As described previously, the 8080 issues Status information at the beginning of each Machine Cycle on its
Data Bus to indicate what operation will take place
during that cycle_ A simple (8) bit latch, like an
INTEL - - - - - MEMW

SYSTEM
CONTROL

I/OR

(82281

TO MEMORY
DEVICES

}
TO I/O DEVICES

1:>-----1/0 W

Figure 3-9. Isolated I/O.

Memory Mapped I/O
By assigning an area of memory address space as I/O a
powerful architecture can be developed that can manipulate
I/O using the same instructions that are used to manipulate
memory locations. Thus, a "new" instruction set is created
that is devoted to I/O handling.
As shown in Figure 3-10, new control signals are generated by gating the MEMR and MEMW signals with A15, the
most significant address bit. The new I/O control signals connect in exactly the same manner as Isolated I/O, thus the
system bus characteristics are unchanged.
By assigning A15 as the I/O "flag", a simple method of
I/O discipline is maintained:
If A 15 is a "zero" then Memory is active.
If A15 is a "one" then I/O is active.

ISOLATED I/O

Other address bits can also be used for this function. A15 was
chosen because it is the most significant address bit so it is
easier to control with software and because it still allows
memory addressing of 32K.

~--------------------,

lOS

II
I.

65K

1

ME~~I
S~I

i~
I~

I/O devices are still considered addressed "ports" but
instead of the Accumulator as the only transfer medium any
of the internal registers can be used. All instructions that
could be used to operate on memory locations can be used
in I/O.

i

1
1

1

r---------~-----------J

ii

.,-, i

w

Ti

Examples:

L______ ~~~~~~~~o_______ J

Figure 3-8. Memory/I/O Mapping.

Isolated I/O
In Figure 3-9 the system control signals, previously detailed in this chapter, are shown. This type of I/O architecture
separates the memory address space from the I/O address
space and uses a conceptually simple transfer to or from Accumulator technique. Such an architecture is easy to understand because I/O communicates only with the Accu,mulator
using'the IN or OUT instructions. Also because of the isolation of memory and I/O, the full address space (65K) is uneffected by I/O addressing.

3-8

MOVr, M
MOV M,r
MVIM
LDA
STA
LHLD
SHLD
ADDM
ANAM

(Input Port to any Register)
(Output any Register to Port)
(Output immediate data to Port)
(Input to ACC)
(Output from ACC to Port)
(16 Bit Input)
(16 Bit Output)
(Add Port to ACC)
("AND" Port with ACC)

It is easy to see that from the list of possible "new"
instructions that this type of I/O architecture could have a
drastic effect on increased system throughput. It is conceptually more difficult to understand than Isolated I/O and it
does limit memory address space, but Memory Mapped I/O
can mean a significant increase in overall speed and at thesame time reducing required program memory area.

MEM"R

The second example uses Memory Mapped I/O and
linear select to show how thirteen devices (8255) can be addressed without the use of extra decoders. The format shown
could be the second and third bytes of the LDA or STA instructions or any other instructions used to manipulate I/O
using the Memory Mapped technique.

TO
}

MEMORY
DEVICES

SYSTEM
CONTROL

It is easy to see that such a flexible I/O structure, that
can be "tailored" to the overall system environment, provides
the designer with a powerful tool to optimize efficiency and
minimize component count.

(8228)

EXAMPLE #2
Figure 3-10_ Memory Mapped I/O.

IA,hhlA4 hhh hi

~

I/O Addressing

}

With both systems of I/O structure the addressing of
each device can be configured to optimize efficiency and reduce component count. One method, the most common, is
to decode the address bus into exclusive "chip selects" that
enable the addressed I/O device, similar to generating chipselects in memory arrays.
Another method iscalled "linear select". In this method,
instead of decoding the Address Bus, a singular bit from the
bus is assigned as the exclusive enable for a specific I/O device. This method, of course, limits the number of I/O devices that can be addressed but eliminates the need for extra
decoders, an important consideration in small system design.
A simple example illustrates the power of such a flexib!e I/O structure. The first example illustrates the format of
the second byte of the IN or OUT instruction using the Isolated I/O technique. The devices used are Intel®8255 Programmable Peripheral Interface units and are linear selected.
Each device has three ports and from the format it can be
seen that six devices can be addressed without additional decoders.

PORT SELECTS

----

[ A1S[ A14[ A13 [ A121 All [ Al0

I Ag I As I

I~
I/O FLAG

I == I/O
0== MEMORY

ADDRESSES - 13 -- 8255s
(39 PORTS -- 312 BITS)

Figure 3-12. Memory Mapped I/O - (Linear Select (8255)

EXAMPLE #1

I/O Interface Example

I A., 1... 1... 1A,I A,I A21 A, lAo I

lJ=

}

In Figure 3-16 a typical I/O system is shown that uses a
variety of devices (8212,8251 and 8255). It could be used
to interface the peripherals around an intelligent CRT terminals; keyboards, display, and communication interface. Another application could be in a process controller to interface
sensors, relays, and motor controls. The limitation of the application area for such a circu it is solely that of the designers
imagination.

PORT SElECTS

The I/O structure shown interfaces to the 8080 CPU
using the bus architecture developed previously in this chapter. Either Isolated or Memory Mapped techniques can be
used, depending on the system I/O environment.

ADDRESSES - 6 - 8255s
(18 PORTS - 144 BITS)

The 8251 provides a serial data communication interface so that the system can transmit and receive data over
communication links such as telephone lines.

Figure 3-11. Isolated I/O - (Linear Select) (8255)

3·9

I 0 I 0 I 0 I A,I

1

t

The three 82125 can be used to drive long lines or LED
indicators due to their high drive capability. (15mA)

l' kXJ A

ClDCONTROL

0- DATA
1 -COMMAND

[
8251 SELECT
(ACTIVE lOW)

'--------- ~~~T~~:~~~~T

Figure 3-13. 8251 Format.

'----------- ~~~2Tf0;~~~~T
'------------ ~!62Tf~:~~~~T

The two (2) 8255s provide twenty four bits each of
programmable I/O data and control so that keyboards, sensors, paper tape, etc., can be interfaced to the system.

Figure 3-15. 8212 Format.
00 - PORT A
01 - PORT B
10 - PORT C

Addressing the structure is described in the formats illustrated in Figures 3-13, 3-14, 3·15. Linear Select is used so
that no decoders are requ ired thus, each device has an exclusive "enable bit".

'1 -COMMAND
}

' -_ _ _ _

PORT SELECT

~~~,:;~~~~E~)T

The example shows how a powerful yet flexible I/O
structure can be created using a minimum component count
with devices that are all members of the 8080 Microcomputer
System.

L..------8(~~Ti~~i~~~

Figure 3-14. 8255 Format.

SERIAL DATA
COMMUNICATION

j
8251

#2
8255

8212
#3

8212
#2

Figure 3-16. Typical I/O Interface.

3-10

#1

8255

8212
#1

Chapter 4

INSTRUCTION SET

!~
!

INSTRUCTION SET

A computer, no matter how sophisticated, can only
do what it is "told" to do. One "tells" the computer what
to do via a series of coded instructions referred to as a Program. The realm of the programmer is referred to as Software, in contrast to the Hardware that comprises the actual
computer equipment. A computer's software refers to all of
the programs that have been written for that computer.

are programs available which convert the programming language instructions into machine code that can be interpreted by the processor.
One type of programming language is Assembly language. A unique assembly language mnemonic is assigned to
each of the computer's instructions. The programmer can
write a program (called the Source Program) using these
mnemonics and certain operands; the source program is
then converted into machine instructions (called the Object
Code). Each assembly language instruction is converted into
one machine code instruction (1 or more bytes) by an
Assembler program. Assembly languages are usually machine dependent (i.e., they are usually able to run on only
one type of computer).

When a computer is designed, the engineers provide
the Central Processing Unit (CPU) with the ability to perform a particular set of operations. The CPU is designed
such that a specific operation is performed when the CPU
control logic decodes a particular instruction. Consequently,
the operations that can be performed by a CPU define the
computer's Instruction Set.
Each computer instruction allows the programmer to
initiate the performance of a specific operation. All com·
puters implement certain arithmetic operations in their instruction set, such as an instruction to add the contents of
two registers. Often logical operations (e.g., OR the contents of two registers) and register operate instructions (e.g.,
increment a register) are included in the instruction set. A
computer's instruction set will also have instructions that
move data between registers, between a register and memory,
and between a register and an I/O device. Most instruction
sets also provide Conditional Instructions. A conditional
instruction specifies an operation to be performed only if
certain conditions have been met; for example, jump to a
particular instruction if the result of the last operation was
zero. Conditional instructions provide a program with a
decision-making capability.

THE 8080 INSTRUCTION SET
The 8080 instruction set includes five different types
of instructions:
• Data Transfer Group-move'data between registers
or between memory and registers
• Arithmetic Group - add, subtract, increment or
decrement data in registers or in memory
•

logical Group - AND, OR, EXCLUSIVE-OR,
compare, rotate or complement data in registers
or in memory

• Branch Group - conditional and unconditional
jump instructions, subroutine call instructions and
return instructions
• Stack, I/O and Machine Control Group - includes
I/O instructions, as well as instructiens for maintaining the stack and internal control flags.

By logically organizing a sequence of instructions into
a coherent program, the programmer can "tell" the computer to perform a very specific and useful function.
The computer, however, can only execute programs
whose instructions are in a binary coded form (i.e., a series
of 1's and D's), that is called Machine Code. Because it
would be extremely cumbersome to program in machine
code, programming languages have been developed. There

Instruction and Data Formats:
Memory for the 8080 is organized into 8-bit quantities, called Bytes. Each byte has a unique 16-bit binary
address corresponding to its sequential position in memory.

4-1

The 8080 can directly address up to 65,536 bytes of memory, which may consist of both read-only memory (ROM)
elements and random-access memory (RAM) elements (read/
write memory).

address where the data is located (the
high-order bits of the address are in the
first register of the pair, the low-order
bits in the second).
•

Data in the 8080 is stored in the form of 8-bit binary
integers:
DATA WORD

Unless directed by an interrupt or branch instruction,
the execution of instructions proceeds through consecutively increasing memory locations. A branch instruction
can specify the address of the next instruction to be executed in one of two ways:

LSB

MSB

When a register or data word contains a binary number, it is necessary to establish the order in which the bits
of the number are written. In the Intel 8080, BIT 0 is referred to as the Least Significant Bit (LSB), and BIT 7 (of
an 8 bit number) is referred to as the Most Significant Bit
(MSB).
The 8080 program instructions may be one, two or
three bytes in length. Multiple byte instructions must be
stored in successive memory locations; the address of the
first byte is always used as the address of the instructions.
The exact instruction format will depend on the particular
operation to be executed.
Single Byte Instructions

I

Two-Byte Instructions

I

Byte One

I

, Do Op Code

Byte Two

I DJ '

, Do Data or
Address

DJ'

I

, Do Op Code

Byte Two

I

, Do

I

, Do

Register indirect - The branch instruction indicates a register-pair which contains the
address of the next instruction to be executed. (The high-order bits of the address
are in the first register of the pair, the
low-order bits in the second.)

There are five condition flags associated with the execution of instructions' on the 8080. They are Zero, Sign,
Parity, Carry, and Auxiliary Carry, and are each represented
by a l-bit register in the CPU. A flag is "set" by forcing the
bit to 1; "reset" by forcing the bit to O.

I

Byte Three D7 '

•

Condition Flags:

Byte One

D7'

Direct - The branch instruction contains the address of the next instruction to be executed. (Except for the 'RST' instruction,
byte 2 contains the low-order address and
byte 3 the high-order address.)

I

Three-Byte Instructions

DJ'

•

The RST instruction is a special one-byte call instruction (usually used during interrupt sequences). RST includes a three-bit field; program control is transferred to
the instruction whose address is eight times the contents
of this three-bit field.

, Do lop Code

DJ'

Immediate - The instruction contains the data itself. This is either an 8-bit quantity or a
16-bit quantity (least significant byte first,
most significant byte second).

Ir
I

ata
or
Address

Unless indicated otherwise, when an instruction affects a flag, it affects it in the following manner:
Zero:

If the result of an instruction has the
value 0, this flag is set; otherwise it is
reset.

Sign:

If the most significant bit of the result of
the operation has the value 1, this flag is
set; otherwise it is reset.

Parity:

If the modulo 2 sum of the bits of the result of the operation is 0, (i.e., if the
result has even parity), this flag is set;
otherwise it is reset (i.e., if the result has
odd parity).

Carry:

If the instruction resulted in a carry
(from addition), or a borrow (from subtraction or a comparison) out of the highorder bit, th is fl ag is set; otherwise it is
reset_

Addressing Modes:
Often the data that is to be operated on is stored in
memory. When multi-byte numeric data is used, the data,
like instructions, is stored in successive memory locations,
with the least significant byte first, followed by increasingly
significant bytes. The 8080 has four different modes for
addressing data stored in memory or in registers:
•

Direct - Bytes 2 and 3 of the instruction contain
the exact memory address of the data
item (the low-order bits of the address are
in byte 2, the high-order bits in byte 3).

•

Register - The instruction specifies the register or
register-pair in which the data is located.

•

Register Indirect - The instruction specifies a register-pair which contains the memory

4-2

Auxiliary Carry: If the instruction caused a carry out
of bit 3 and into bit 4 of the resulting
value, the auxiliary carry is set; otherwise
it is reset. This flag is affected by single
precision additions, subtractions, incre·
ments, decrements, comparisons, and log·
ical operations, but is principally used
with additions and increments preceding
a DAA (Decimal Adjust Accumulator)
instruction.

Symbols and Abbreviations:
The following symbols and abbreviations are used in
the subsequent description of the 8080 instructions:

rh

The first (high-order) register of a designated
register pair.

rl

The second (low-order) register of a designated register pair.

PC

16-bit program counter register (PCH and
PCl are used to refer to the high-order and
low-order 8 bits respectively).

SP

16-bit stack pointer register (SPH and SPL
are used to refer to the high-order and loworder 8 bits respectively).

rm

Bit m of the register r (bits are number 7
through a from left to right).

Z,S,P,CY,AC The condition flags:
Zero,
Sign,
Parity,
Carry,
and Auxiliary Carry, respectively.

SYMBOLS

MEANING

accumulator

Register A

addr

16-bit address quantity

data

8-bit data quantity

data 16

16-bit data quantity

byte 2

The second byte of the instruction

byte 3

The third byte of the instruction

1\

Logical AND

port

8-bit address of an 1/0 device

V

Exclusive OR

r,rl,r2

One of the registers A,B,C,D,E,H,L

V

Inclusive OR

DDD,SSS

The bit pattern designating one of the registers A,B,C,o,E,H,L (DDD~destination, SSS~
source) :

+

DDD or SSS

(

rp

Addition
Two's complement subtraction

*

Multiplication
"Is exchanged with"

A
B
C
D
E
H
L

The one's complement (e.g., (A))

a through

n

The restart number

NNN

The bi nary representation 000 through 111
for restart number a through 7 respectively.

7

One of the register pairs:

Description Format:

B represents the B,C pair with B as the highorder register and C as the low-order register;

The following pages provide a detailed description of
the instruction set of the 8080. Each instruction is described in the following manner:

D represents the D,E pair with D as the highorder register and E as the low-order register;

1. The MAC 80

assembler format, consisting of
the instruction mnemonic and operand fields, is
printed in BOLDFACE on the left side of the first
line.

H represents the H,L pair with H as the highorder register and L as the low-order register;
SP represents
register.
RP

The contents of the memory location or registers enclosed in the parentheses.
"Is transferred to"

REGISTER NAME

111
000
001
010
all
100
101

)

the

16-bit stack

poi nter

2. The name of the instruction is enclosed in parenthesis on the right side of the first line.

The bit pattern designating one of the register pairs B,D,H,SP:
RP
00
01
10
11

3. The next line(s) contain a symbolic description
of the operation of the instruction.

REGISTER PAIR

4. This is followed by a narative description of the

B-C
D-E
H-L
SP

operation of the instruction.

5. The following line(s) contain the binary fields and
patterns that comprise the machine instruction.

4-3

6. The last four lines contain incidental information
about the execution of the instruction. The num·
ber of machine cycles and states required to execute the instruction are listed first. If the instruction has two possible execution times, as in a
Conditional Jump, both times will be listed, separated by a slash. Next, any significant data addressing modes (see Page 4-2) are listed. The last
line lists any of the five Flags that are affected by
the execution of the instruction.

MVI r, data
(Move Immediate)
(r) - - (byte 2)
The content of byte 2 of the instruction is moved to
register r.

I 0

0

D

D

0

D
data

Cycles:
States:
Addressing:
Flags:

2
7
immediate
none

Data Transfer Group:
This group of instructions transfers data to and from
registers and memory. Condition flags are not affected by
any instruction in this group.

MOV r1, r2

(Move Register)

(rl)~

(r2)
The content of register r2 is moved to register rl.

0

I

D

D

Cycles:
States:
Addressing:
Flags:

MOV r, M

D

S

I

S

I

S

MVI M, data
(Move to memory immediate)
((H) (L)) __ (byte 2)
The content of byte 2 of the instruction is moved to
the memory location whose address is in registers H
and L.

o I o

5
register

o

o

data

none

Cycles:
States:
Addressing:
Flags:

(Move from memory)

(r) __ ((H) (L))

3
10
immed./reg. indirect
none

The content of the memory location, whose address
is in registers Hand L, is moved to register r.
0

I

D

D

Cycles:
States:
Addressing:
Flags:

D

0

2
7

reg. indirect
none

MOV M, r
(Move to memory)
((H)(L))- (r)
The content of register r is moved to the memory location whose address is in registers Hand L.
0

I

1

I

0
Cycles:
States:
Addressing:
Flags:

S

I

2
7
reg. indirect
none

S

I

S

LXI rp, data 16
(Load register pair immediate)
(rh) ~ (byte 3),
(rl) - - (byte 2)
Byte 3 of the instruction is moved into the high-order
register (rh) of the regi~ter pair rp. Byte 2 of the instruction is moved into the low-order register (rl) of
the register pair rp.

o

I

o

I

R

I

P

I

o

I

o

low-order data
high-order data
Cycles:
States:
Addressing:
Flags:

3

10
immediate
none

I

0

I

1

SHLO addr
(Store Hand L direct)
((byte 3)(byte 2)) ~ (L)
((byte3)(byte2)+1) _
(H)

LOA addr
(Load Accumulator direct)
(A) ~ ((byte 3)(byte 2))
The content of the memory location, whose address
is specified in byte 2 and byte 3 of the instruction, is
moved to register A.

o

I

0

I

1

I 1

I 1

I

0

I

1

The content of register L is moved to the memory location whose address is specified in byte 2 and byte
3. The content of register H is moved to the succeeding memory location.

I 0

low·order addr

o

I

o

I 1

I 0

I 0

I 0

I 1

I 0

high·order addr
low-order addr

4
13
direct
none

Cycles:
States:
Addressing:
Flags:

high·order addr
Cycles:
States:
Addressing:
Flags:

5
16
direct
none

LOAX rp

(Load accumulator indirect)
((rp))
The content of the memory location, whose address
is in the register pair rp, is moved to register A. Note:
only register pairs rp=B (registers B and C) or rp=D
(registers D and E) may be specified.
(A)~

STA addr

(Store Accumulator direct)

((byte 3)(byte 2)) ~ (A)
The content of the accumulator is moved to the
memory location whose address is specified in byte
2 and byte 3 of the instruction.

0

I 0

I

1

I

1

I 0

I 0

I 1

o I o

h igh·order addr

4
13
direct
none

LHLO addr
(Load Hand L direct)
(L) ~ ((byte 3)(byte 2))
((byte 3)(byte 2) + 1)
(H) The content of the memory location, whose address
is specified in byte 2 and byte 3 of the instruction, is
moved to register L. The content of the memory loca·
tion at the succeeding address is moved to register H.

I

o

I

1

I 0

I

1

I 0

I

1

I

0

2

7
reg. indirect
none

I 1

I

R
Cycles:
States:
Addressing:
Flags:

1

I

0

2
7
reg. indirect
none

XCHG
(Exchange Hand L with D and E)
(H)-(D)
(L) ---(E)
The contents of registers Hand L are exchanged with
the contents of registers D and E.

I 0

low·order addr
h igh·order addr
Cycles:
States:
Addressing:
Flags:

0

STAX rp
(Store accumulator indirect)
((rp)) ~ (A)
The content of register A is moved to the memory location whose address is in the register pair rp. Note:
only register pairs rp=B (registers B and C) or rp=D
(registers D and E) may be specified.

o I o

o

I

p

Cycles:
States:
Addressing:
Flags:

low·order addr

Cycles:
States:
Addressing:
Flags:

R

I 0

5

Cycles:
States:
Addressing:
Flags:

16
direct
none

4-5

4
register
none

i..

ADC r
(A) _

Arithmetic Group:

(Add Register with carry)
(A) + (r) + (CY)

The content of register r and the content of the carry
bit are added to the content of the accumulator. The
result is placed in the accumulator.

This group of instructions performs arithmetic operations on data in registers and memory.
Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Carry, and Auxiliary
Carry flags accord ing to the standard rules.

1

I

I

0

All -subtraction operations are performed via two's
complement arithmetic and set the carry flag to one to indicate a borrow and clear it to indicate no borrow.

I o I o

o

ADD M

4
register
Z,S,P,CY,AC

(Add memory with carry)
(A) + ((H) (L)) + (CY)
The content of the memory location whose address is
contained in the Hand L registers and the content of
the CY flag are added to the accumulator. The result
is placed in the accumulator.
(A) -

I
4

I

0

register
Z,S,P,CY,AC

0

I

0

0

Cycles:
States:
Addressing:
Flags:

(A) + ((H) (L))

2
7

reg. indirect
Z,S,P,CY,AC

I

0

I 0

0

0

(A) + (byte 2) + (CY)
The content of the second byte of the instruction and
the content of the CY flag are added to the contents
of the accumulator. The result is placed in the
accumulator.
(A) -

0
1

7
reg. indirect
Z,S,P,CY,AC

I

0

I

I

0

0

SUB r

o
2
7
immediate
Z,S,P,CY,AC

(Subtract Register)
(A) __ (A) - (r)

The content of register r is subtracted from the content of the accumulator. The result is placed in the
accumulator.

0

o

data
Cycles:
States:
Addressing:
Flags:

o

Cycles:
States:
Addressing:
Flags:

(Add immediate)
(A) + (byte 2)

1

o

data

The content of the second byte of the instruction is
added to the content of the accumulator. The result
is placed in the accumulator.

I

I

2

Cycles:
States:
Addressing:
Flags:

ADI data
(A) _

(Add immediate with carry)

ACI data

The content of the memory location whose address
is contained in the Hand L registers is added to the
content of the accumulator. The result is placed in
the accumulator.

1

S

(Add memory)

(A) _

1

S

ADC M

o

Cycles:
States:
Addressing:
Flags:

S

Cycles:
States:
Addressing:
Flags:

ADD r
(Add Register)
( A ) - (A)+(r)
The content of register r is added to the content of the
accumulator. The result is placed in the accumulator.

1

o

0

I 0
Cycles:
States:
Addressing:
Flags:

2
7
immediate
Z,S,P,CY,AC

4-6

o

S

4
register
Z,S,P,CY,AC

s

I S

SUB M

(Subtract memory)

(A) - - (A) - ((H) (L))

The content of the memory location whose address is
contained in the Hand L registers is subtracted from
the content of the accumulator. The result is placed
in the accumulator.

I

0

I

0

I

0

1

Cycles:
States:
Addressing:
Flags:

SUI data

SBI data
(Subtract immediate with borrow)
(A) - - (A) - (byte 2) - (CY)
The contents of the second byte of the instruction
and the contents of the CY flag are both subtracted
from the accumulator. The result is placed in the
accumulator.
1

0

I

o

o
data

2
7
reg. indirect
Z,S,P,CY,AC

Cycles:
States:
Addressing:
Flags:

2
7
immediate
Z,S,P,CY,AC

(Subtract immediate)

(A) - - (A) - (byte 2)

The content of the second byte of the instruction is
subtracted from the content of the accumulator. The
result is placed in the accumulator.

INR r

o

0

data
Cycles:
States:
Addressing:
Flags:

SBB r

(Increment Register)
+1
The content of register r is incremented by one.
Note: All condition flags except CY are affected.
(r) __ (r)

I

0

D

I

D

Cycles:
States:
Addressing:
Flags:

2
7
immediate
Z,S,P,CY,AC

(Subtract Register with borrow)

INR M

D

0

I

0

1

5
register
Z,S,P,AC

(Increment memory)

(A) - - (A) - (r) - (CY)

((H) (L)) - - ((H) (L))

The content of register r and the content of the CY
flag are both subtracted from the accumulator. The
result is placed in the accumulator.

The content of the memory location whose address
is contained in the Hand L registers is incremented
by one. Note: All condition flags except CY are
affected.

1

I

o I o I

S

I S I

S
0

Cycles:
States:
Addressing:
Flags:

SBB M

I

0

4
register
Z,S,P,CY,AC

+1

0
Cycles:
States:
Addressing:
Flags:

0

0

3
10
reg. indirect
Z,S,P,AC

(Subtract memory with borrow)

(A) - - (A) - ((H) (L)) - (CY)

The content of the memory location whose address is
contained in the Hand L registers and the content of
the CY flag are both subtracted from the accumulator. The result is placed in the accumulator.
1

I

oI o
Cycles:
States:
Addressing:
Flags:

1

I

1

I o

DCR r

The content of register r is decremented by one.
Note: All condition flags except CY are affected.

0

2

(Decrement Register)

(r) __ (r) - 1

I

0

D

I

D

Cycles:
States:
Addressing:
Flags:

7
reg. indirect
Z,S,P,CY,AC

4-7

D

I

1

5
register
Z,S,P,AC

I

0

I

1

DCR M

(Decrement memory)

DAA

((H) (L)) . . - ((H) (L)) - 1

The content of the memory location whose address is
contained in the Hand L registers is decremented by
one. Note: All condition flags except CY are affected.

0

I

0

0

I

1

I

0

I

1.

If the value of the least significant 4 bits of the
accumulator is greater than 9 or if the AC flag
is set, 6 is added to the accumulator.

2.

If the value of the most significant 4 bits of the
accumulator is now greater than 9, or if the CY
flag is set, 6 is added to the most significant 4
bits of the accumulator.

1

3
10

Cycles:
States:
Addressing:
Flags:

(Decimal Adjust Accumulator)
The eight-bit number in the accumulator is adjusted
to form two four-bit Binary-Coded-Decimal digits by
the following process:

reg. indirect
Z,S,P,AC

NOTE: All flags are affected.

a I a

INX rp
(I ncrement register pair)
(rh) (rl) . . - (rh) (rl) + 1
The content of the register pair rp is incremented by
one. Note: No condition flags are affected.

o I

0

I

0

Cycles:
States:
Flags:

0

4
Z,S,P,CY,AC

R

Logical Group:

Cycles:
States:
Addressing:
Flags:

5

This group of instructions performs logical (Boolean)
operations on data in registers and memory and on condition flags.

register
none

Unless indicated otherwise, all instructions in this
group affect the Zero, Sign, Parity, Auxiliary Carry, and
Carry flags according to the standard rules.
DCX rp
(Decrement register pair)
(rh) (rl) . . - (rh) (rl) - 1
The content of the register pair rp is decremented by
one. Note: No condition flags are affected.

0

I

0

R

P

Cycles:
States:
Addressing:
Flags:

I

I

0

I

I

ANA r

R

I

1

I

1

0

a

a

S

I

S

S

5
register
none

I

p

Cycles:
States:
Addressing:
Flags:

1\ (r)

The content of register. r is logically anded with the
content of the accumulator. The result is placed in
the accumulator. The CY flag is cleared.

Cycles:
States:
Addressing:
Flags:

DAD rp
(Add register pair to Hand L)
(H) (L) . . - (H) (L) + (rh) (rl)
The content of the register pair rp is added to the
.content of the register pair Hand L. The result is
placed in the register pair Hand L. Note: Only the
CY flag is affected. It is set if there is a carry out of
the double precision add; otherwise it is reset.

o I o

(AND Register)

(A) . . - (A)

0

I

0

I

ANA M

4
register
Z,S,P,CY,AC

(AND memory)

(A) . . - (A)

1\ ((H)

(L))

The contents of the memory location whose address
is contained in the Hand L registers is logically anded
with the content of the accumulator. The result is
placed in the accumulator. The CY flag is cleared.

a I

1

1

0

Cycles:
States:
Addressing:
Flags:

3
10
register
CY

4-8

a I

1

I

2
7
reg. indirect
Z,S,P,CY,AC

1

I a

ANI data
(A) _

(AND immediate)
(A) 1\ (byte 2)

ORA r
(OR Register)
(A)V(r)
(A) The content of register r is inclusive-OR'd with the
content of the accumulator. The result is placed in
the accumulator. The CY and AC flags are cleared.

The content of the second byte of the instruction is
logically anded with the contents of the accumulator.
The result is placed in the accumulator. The CY and
AC flags are cleared.

I

o
o

o

Cycles:
States:
Addressing:
Flags:

data
Cycles:
States:
Addressing:
Flags:
XRA r

2
7
immediate
Z,S,P,CY,AC

ORA M

S

I S I S

(A) V ((H) (L))

The content of the memory location whose address is
contained in the Hand L registers is inclusive-OR'd
with the content of the accumulator. The result is
placed in the accumulator. The CY and AC flags are
cleared.

(Exclusive OR Register)

The content of register r is exclusive-or'd with the
content of the accumulator. The resul t is placed in
the accumulator. The CY and AC flags are cleared_

S

4
register
Z,S,P,CY,AC

(OR memory)

(A) _

( A ) - (A)V (r)

1::1
10
~~
__1____0______________

o

1

o

o I

o

S ~
~

o

1

- 4_ _ _ _ _ _ _

Cycles:
States:
Addressing:
Flags:
XRA M

Cycles:
States:
Addressing:
Flags:

1

4
register
Z,S,P,CY,AC

OR I data
(0 R Immediate)
(A) (A) V (byte 2)
The content of the second byte of the instruction is
inclusive-OR'd ,,_ith the content of the accumulator.
The result is placed in the accumulator. The CY and
AC flags are cleared_

(Exclusive OR Memory)

(A) __ (A)

V

((H) (L))

The content of the memory location whose address
is contained in the Hand L registers is exclusive-OR 'd
with the content of the accumulator. The result is
placed in the accumulator_ The CY and AC flags are
cleared.

o

0

I 0

I 0
Cycles:
States:
Addressing:
Flags:

reg. indirect
Z,S,P,CY,AC

CMPr

7

immediate
Z,S,P,CY,AC

(Compare Register)
(A)

(r)

The content of register r is subtracted from the accumulator. The accumulator remains unchanged. The
condition flags are set as a result of the subtraction.
The Z flag is set to 1 if (A) ~ (r). The CY flag is set to
1 if (A)
(r).

<

0

o

data
Cycles:
States:
Addressing:
Flags:

2

Cycles:
States:
Addressing:
Flags:

(Exclusive OR immediate)
XRI data
(A)-- (A) V (byte 2)
The content of the second byte of the instruction is
exciusive-OR'd with the content of the accumulator.
The result is placed in the accumulator. The CY and
AC flags are cleared.

t

0

data

2
7

0

2

7
reg. indirect
Z,S,P ,CY,AC

2

S
Cycles:
States:
Addressing:
Flags:

7

immediate
Z,S,P,CY,AC

4-9

4
register
Z,S,P,CY,AC

S

S

CMPM

(Compare memory)

(A)

RRC

((H) (L))

The content of the memory location whose address
is contained in the Hand L registers is subtracted
from the accumulator. The accumulator remains un·
changed. The condition flags are set as a result of the
subtraction. The Z flag is set to 1 if (A) : ((H) (L)).
The CY flag is set to 1 if (A) < ((H) (L)).

a

(Rotate right)
(An) - - (A n+1); (A 7) - - (AO)
(CY) - - (AO)
The content of the accumulator is rotated right one
position. The high order bit and the CY flag are both
set to the value shifted out of the low order bit position. Only the CY flag is affected.

a I a I

0

a
Cycles:
States:
Addressing:
Flags:

Cycles:
States:
Flags:

2
reg. indirect
Z,S,P,CY,AC

RAL

4
CY

(Rotate left through carry)
(A n+1) - - (An); (CY) - - (A7)
(AO) - - (CY)
The content of the accumulator is rotated left one
position through the CY flag. The low order bit is set
equal to the CY flag and the CY flag is set to the
value shifted out of the high order bit. Only the CY
flag is affected.

(Compare immediate)
(byte 2)
The content of the second byte of the instruction is
subtracted from the accumulator. The condition flags
are set by the result of the subtraction. The Z flag is
set to 1 if (A) ~ (byte 2). The CY flag is set to 1 if
(A) < (byte 2).

a I

0

I

a

0
Cycles:
States:
Flags:

RAR

o
data

2
7
immediate
Z,S,P,CY,AC

I

1

I

1

4
CY

(Rotate right through carry)
(An) - - (A n+1); (CY) - - (AO)
(A7) - - (CY)
The content of the accumulator is rotated right one
position through the CY flag. The high order bit is set
to the CY flag and the CY flag is set to the value
shifted out of the low order bit. Only the CY flag is
affected.

o I o

a
Cycles:
States:
Flags:

R LC

1

7

CPI data
(A)

Cycles:
States:
Addressing:
Flags:

I

I 0

1

4
CY

(Rotate left)
(A n+1) - - (An) ; (AO) - - (A7)
(CY) (A7)
The content of the accumulator is rotated left one
position. The low order bit and the CY flag are both
set to the value shifted out of the high order bit posi·
tion. Only the CY flag is affected.

0

I

0

I

0

I

0

0

Cycles:
States:
Flags:

4

I

1

I

CMA

(Complement accumulator)
(A) - -

fA)

The contents of the accumulator are complemented
(zero bits become 1, one bits become 0). No flags are
affected.

1

0

I a I

1

Cycles:
States:
Flags:

CY

4-10

I

I a
1

4
none

1

I

1

I

1

CMC

(Complement carry)
(CY) - - (CY)
The CY flag is complemented. No other flags are
affected.

dress is specified in byte 3 and byte 2 of the current
instruction.

I 1 I 0

1

1 0

I

I

0

0

I

1

I 1

low·order addr

o I o

high·order addr
Cycles:
States:
Flags:

STC

1

3

Cycles:
States:
Addressing:
Flags:

4
CY

10
immediate
none

(Set carry)
(CY) - - 1
The CY flag is set to 1. No other flags are affected.

o I o

Jcondition addr
(Conditional jump)
If (CCC),
(PCI - - (byte 3) (byte 2)
If the specified condition is true, control is trans·
ferred to the instruction whose address is specified in
byte 3 and byte 2 of the current instruction; other·
wise, control continues sequentially.

o
Cycles:
States:
Flags:

4
CY

1

I

1

I

C

I

C

I C

I

011

I 0

low·order addr
high·order addr

3
10
immediate
none

Cycles:
States:
Addressing:
Flags:

Branch Group:
This group of instructions alter normal sequential
program flow.
Condition flags are not affected by any instruction
in this group.
The two types of branch instructions are uncondi·
tional and conditional. Unconditional transfers simply per·
form the specified operation on register PC (the program
counter). Conditional transfers examine the status of one of
the four processor flags to determine if the specified branch
is to be executed. The conditions that may be specified are
as follows:
CONDITION
NZ
Z
NC
C
PO
PE
P
M

not zero (Z = 0)
zero (Z = 1)
no carry (CY = 0)
- carry (CY = 1)
- parity odd (P = 0)
parity even (P = 1)
plus (S = 0)
minus (S = 1)

CCC
000
001
010
011
100
101
110
111

CALL addr
(Call)
((SP) -1) - - (PCH)
((SP) - 21 - - (PCL)
(SP) - - (SP) - 2
(PC) - - (byte 31 (byte 2)
The high·order eight bits of the next instruction ad·
dress are moved to the memory location whose
address is one less than the content of register SP.
The low·order eight bits of the next instruction ad·
dress are moved to the memory location whose
address is two less than the content of register SP.
The content of register SP is decremented by 2. Can·
trol is transferred to the instruction whose address is
specified in byte 3 and byte 2 of the current
instruction.
1 I

1

I

o

I

o

I

1

I

1

I

o

I 1

low·order addr
h igh·order addr
Cycles:
States:
Addressing:
Flags:

JMP addr
(Jump)
(PC) __ (byte 3) (byte 2)
Control is transferred to the instruction whose ad·

4·11

5
17
immediate/reg. indirect
none

(Condition call)
If (CCC).
((SP) - 1) --- (PCH)
((SP) - 2) --- (PCL)
(SP) ___ (SP) - 2

Ccondition addr

(NNN)

(PC) -+- (byte 3) (byte 2)
If the specified condition is true. the actions specified
in the CALL instruction (see above) are performed;
otherwise. control continues sequentially.
1 I

1

I

C

I

I C

C

I

1

I

o

I 0

low-order addr

NNN.

high-order addr
Cycles:
States:
Addressing:
Flags:

RET

RST n
(Restart)
((SP) - 1) --- (PCH)
((SP) - 2) --- (PCL)
(SP) (SP) - 2
(PC) 8'
The high-order eight bits of the next instruction address are moved to the memory location whose
address is one less than the content of register SP.
The low-order eight bits of the next instruction address are moved to the memory location whose
address is two less than the content of register SP.
The content of register SP is decremented by two.
Control is transferred to the instruction whose address is eight times the content of

3/5
11/17
immediate/reg. indirect
none

(Return)
(PCL) ___ ((SP));

1

I

N

I

0

0

I

0

I

3
10
reg. indirect
none

I

7

6

5

4

C

C

Cycles:
States:
Addressing:
Flags:

I

3

2

1 0

(Jump Hand L indirect - move Hand L to PC.
(PCH) --- (H)
(PCL) --- (L)
The content of register H is moved to the high-order
eight bits of register PC. The content of register L is
moved to the low-order eight bits of register PC.

I

1

I

o I

o I

(Conditional return)

If (CCC).
(PCL) --- ((SP))
(PCH) --- ((SP) + 1)
(SP) (SP) + 2
If the specified condition is true. the actions specified
in the RET instruction (see above) are performed;
otherwise. control continues sequentially.
1

11

reg. indirect
none

1

1
Rcondition

3

Program Counter After Restart

PCHL
Cycles:
States:
Addressing:
Flags:

I

jolololOIOIOIOIOlolOINININlolOIOI

The content of the memory location whose address
is specified in register SP is moved to the low-order
eight bits of register PC. The content of the memory
location whose address is one more than the content
of register SP is moved to the high-order eight bits of
register PC. The content of register SP is incremented
by 2.

o I

8

1

N

Cycles:
States:
Addressing:
Flags:
15 14 13 12 11 10 9

(PCH) --- ((SP) + 1);
(SP) --- (SP) + 2;

N I

C

I

0

I

1/3
5/11
reg. indirect
none

0

0

Cycles:
States:
Addressing:
Flags:

1
5
register
none

0

I

1

Stack, I/O, and Machine Control Group:

FLAG WORD

D,

This group of instructions performs I/O, manipulates
the Stack, and alters internal control flags.

S

o

Z

Unless otherwise specified, condition flags are not
affected by any instructions in this group.

PUSH rp

(Push)

POP rp

((SP) - 1) (rh)
((SP) - 2) (rl)
(SP) (SP) - 2
The content of the high·order register of register pair
rp is moved to the memory location whose address is
one less than the content of register SP. The content
of the low·order register of register pair rp is moved
to the memory location whose address is two less
than the content of register SP. The content of register SP is decremented by 2. Note: Register pair
rp = SP may not be specified.
1

I

R

P

I

Cycles: '
States:
Addressing:
Flags:

0

1

I

1

P

R

Cycles:
States:
Addressing:
Flags:

none

o

o

o

3
10
reg. indirect
none

(Pop processor status word)

(CY) - - ((SP))o
(P) ((SP))2
((SP))4
(AC) (Z) ((SP))6
(S) ((SP))7
(A) - - ((SP) + 1)
(SP) - - (SP) + 2
The content of the memory location whose address
is specified by the content of register SP is used to
restore the condition flags. The content of the memory location whose address is one more than the
content of register SP is moved to register A. The
content of register SP is incremented by 2.

(A)

Cycles:
States:
Addressing:
Flags:

1

3
11
reg. indirect

0

CY

(Pop)

I

0

((SP) - 2)0 (CY) ,((SP) - 2)1 - - 1
(P), ((SP) - 2)3 - - 0
((SP) - 2)2 ((SP) - 2)4 (AC) , ((SP) - 2)5 0
((SP) - 2)6 (Z), ((SP) - 2)7 - - (S)
(SP) (SP) - 2
The content of register A is moved to the memory
location whose address is one less than register SP.
The contents of the condition flags are assembled
into a processor status word and the word is moved
to the memory location whose address is two less
than the content of register SP. The content of register SP is decremented by two.

I

P

(rh) ((SP) + 1)
(SP) (SP) + 2
The content of the memory location, whose address
is specified by the content of register SP, is moved to
the low·order register of register pair rp. The content
of the memory location, whose address is one more
than the content of register SP, is moved to the highorder register of register pair rp. The content of register SP is incremented by 2. Note: Register pair
rp = SP may not be specified.

(Push processor status word)

((SP) -1) -

o

(rl) -((SP))

POP PSW
PUSH PSW

AC

DO

I

0

1

I

1

Cycles:
States:
Addressing:
Flags:

3
11
reg. indirect
none

4·13

o I

0

I

3
10
reg. indirect
Z,S,P,CY,AC

0

XTHL
(Exchange stack top with Hand L)
(L) _((SP))
(H) ((SP) + 1)
The content of the L register is exchanged with the
content of the memory location whose address is
specified by the content of register SP. The content
of the H register is exchanged with the content of the
memory location whose address is one more than the
content of register SP.

I 0

o

(Enable interrupts)
The interrupt system is enabled following the execution of the next instruction.
1

I

I
Cycles:
States:
Flags:

DI

I

1

reg. indirect
none

I

o
Cycles:
States:
Addressing:
Flags:

IN port
(A) _

I

1

1
4
none

(Disable interrupts)
The interrupt system is disabled immediately following the execution of the DI instruction.

(Move HL to SP)
(SP) 4 - (H) (L)
The contents of registers Hand L (16 bits) are moved
to register SP.

1

0

o

5
18

Cycles:
States:
Addressing:
Flags:

SPHL

EI

Cycles:
States:
Flags:

o

1
4
none

(Halt)

HLT

The processor is stopped. The registers and flags are
unaffected.

1
5
register
none

0

,

0
Cycles:
States:
Flags:

(Input)
(data)

,1 ,1

I

0

7

none

The data placed on the eight bit bi-directional data
bus by the specified port is moved to register A.
1

I

I

o

1

I

0

I

NOP

1

port
Cycles:
States:
Addressing:
Flags:

3

0

direct
none

0

I

0

0
Cycles:
States:
Flags:

0

0

port
Cycles:
States:
Addressing:
Flags:

,

0

10

OUT port
(Output)
(data) + - (A)
Th~ content of register A is placed on the eight bit
bi-directional data bus for transmission to the specified port.

0

(No op)
No operation is performed. The registers and flags
are unaffected.

3
10
direct
none

4-14

4
none

0

0

0

8080A
8080 INSTRUCTION SET
Summary of Processor Instructions
Mnemonic

Oescription

Inslruction Codelll
Clockl2;
07 06 05 04 03 02 01 00 Cycles Mnemonic

Oescription

Instruction Codelll
Clock[2[
07 06 05 04 03 02 01 00 Cycles

MOVE, LOAO, AND STORE
MOVrl.r2
MOV M.r
MOV r.M
MVI r
MVI M
LXI B

0

Move memory to register
Move immediate register
Move immediate memory
Load immediate register

0

Pair B & C
Load immediate register
Pair 0 & E
Load immediate register
Pair H & L

LXID
LXI H
STAX
STAX
LDAX
LDAX
STA
LOA
SHLD
LHLD

Move·register to register
Move register to memory

B
0
B
0

XCHG

S S S
S S S

JPO
PCHL

10
10
10
10

PUSH 0
PUSH H
PUSH PSW
POP B
POP 0
POP H
POP PSW
XTHL
SPHL
LXI SP
INX SP
DCX SP

Push register Pair B &
C on stack
Push register Pair 0 &
E on stack
Push register Parr H &
L on stack
Push A and Flags
on stack

CPO

JZ
JNZ
JP

13
13
16
16
4

JM
JPE

11/17
11117
11117

RET
RC
RNC

Return
Return on carry
Return on no carry

10
5111
5111

RZ
RNZ
RP
RM

Return on zero
Return on no zero
Return on positive

5111
5111
5111

Return on minus
Return on panty even
Return on parrty odd

5111
5111
5111

11

RESTART

11

INCREMENT AND DECREMENT

It

10

RST

Restart

INR r
OCR r
INR M
OCR M
INX B

10

INX 0

10

INX H

18

OCX B
OCX 0
OCX H

Load immediate stack
pointer
Increment stack painter
Decrement stack
pointer

10

ADD

Jump unconditional
Jump on carry

10
10
10

no carry
zero
no zero
positive
minus
panty even

17
11/17
11/17
11/17
11/17
11/17

no carry
zero
no zero
positive
minus
parity even
panty odd

RPE
RPO

10

on
on
on
on
on
on

Callan
Callan
Callan
Callan
Callan
Callan
Call on

11

Pop register Pair B &
C off stack
Pop register Parr 0 &
E off stack
Pop register Pair H &
L off stack
Pop A and Flags
off stack
Exchange top of
stack. H & L
H & L to stack painter

Jump
Jump
Jump
Jump
Jump
Jump

Call unconditional
Callan carry

RETURN

ADD r
AOC r
ADD M
ADC M

JUMP
JMP
JC
JNC

CALL
CC
CNC
CZ
CNZ
CP
CM
CPE

STACK OPS
PUSH B

5

CALL

0

Store A indirect

Store A Indrrect
Load A indirect
Load A indirect
Store A direct
Load A direct
Store H & L direct
Load H & L direct
Exchange 0 & E. H & L
Registers

10

Jump on panty odd
H & L to program
counter

10
10
10
10
10

AOI
ACI
DAD
DAD
DAD
DAD

B
0
H
SP

11

Increment register

Decrement register
Increment memory

0
10

0

10

Decrement memory
Increment B & C
registers
Increment 0 & E
registers
Increment H & L
registers
Decrement B & C
Decrement 0 & E
Decrement H & L
S

Add register 10 A
Add register to A
with carry
Add memory to A
Add memory to A
with carry
Add Immediate to A
Add immediate to A
with carry
Add B & C to H & L
Add D & E to H & L
Add H & L to H & L
Add stack pointer to
H& L

NOTES: 1. DOD or SSS B 000. COOl. 0010. E 011. H 100. L 101. Memory 110. Alii
2. Two possible cycle times. (6112) indicate instruction cycles dependent on condition flags.

4-15

A A

A

S S

10
10
10
10

'All mnemonics copyright
c

Intel Corporation 1977

r-

8080A
8080 INSTRUCTION SET
Summary of Processor Instructions (Cont)
Mnemonic

Description

Instruction Codelll
Clockl21
D) 06 05 04 03 02 01 DO Cycles

SUBTRACT
SUB r

S

Subtract register
from A
Subtract register from
A with borrow
Subtract memory
from A
Subtract memory from
A with borrow
Subtract Immediate
from A
Subtract immediate
from A with borrow

SBB r
SUB M
SBB M
SUI
SBI

S

LOGICAL
ANA r
XRA r

And register with A
Exclusive Or register
with A
Or register with A
Compare register with A
And memory with A
Exclusive Or memory
with A
01 memory with A
Compare memory with A
And Immediate with A
Exclusive Or immediate
with A

ORA r
CMP r
ANA M
XRA M
ORA M
CMP M
ANI
XRI
ORI
CPI

S

.7

Or immediate with A
Compare immediate
with A

ROTATE
RLC
RRC

Rolate
Rotate
Rotate
carry
Rotate
carry

RAL
RAR

A lefl
A right
A left through
A right through

SPECIALS
CMA
STC
CMC
DAA

Complement A
Set carry
Complement carry
Decimal adjust A

INPUT/OUTPUT
JN
OUT

Input
Output

10
10

CONTROL
EI
01
Nap
HLT

NOTES:

Enable Interrupts
Disable Interrupt
No-operatIOn
Hall

DOD or SSS: B"OOO. C=OO1. 0=010. E=Ol1. H=100. L·101. Memory=110. A=lll
2. Two pOSSible cycle times. (6112) indicate Instruction cycles dependent on conditIOn flags

4-16

'All mnemonics copyright
C Intel Corporation 1977

,

L
I

Chapter S
INTRODUCTION TO MCS-8S ™

INTRODUCTION TO MCS-8S ™

EVOLUTION

systems and reliable, high volume production. From
complex MOSILSI peripheral components to resi-®
dent high level systems language (PLlM) the Intel
8080 Microcomputer System provides the most
comprehensive, effective solution to today's system
problems.

In December 1971, Intel introduced the first general
purpose, 8-bit microprocessor, the 8008. It was
implemented in P-channel MaS technology and
was packaged in asingle 18pin, dual in-line package
(DIP). The 8008 used standard semiconductor ROM
and RAM and, for the most part, TTL components for
1/0 and general ·interface. It immediately found
applications in byte-oriented end products such as
terminals and computer peripherals where its
instruction execution (20 micro-seconds),
general purpose organization and instruction set
matched the requirements of these products.
Recognizing that hardware was but a small part in
the overall system picture, Intel developed both
hardware and software tools forthe design engineer
so that the transition from prototype to production
would be as simple and fast as possible. The
commitment of providing a total systems approach
with the 8008 microcomputer system was actually
the basis for the sophisticated, comprehensive
development tools that Intel has available today.

60

K

1\

30

8080

~

~

15

3
1
1971

1972

1973

1974

~

1975

80aOA AND
PEA IPHERALS

1\

1976

B085

1977

8-BIT SYSTEM COMPONENT COUNT 1971 - 1977

THE 8080A MICROPROCESSOR
With the advent of high-production N-channel RAM
memories and 40 pin DIP packaging, Intel designed
the 8080A microprocessor. It was designed to be
software compatible with the 8008 so that the
existing users of the 8008 could preserve their
investment in software and at the same time provide
dramatically increased performance (2 microsecond instruction execution), while reducing the
amount of components necessary to implement a
system. Additions were made to the basic instruction set to take advantage of this increased
performance and large system-type features were
included on-chip such as DMA, 16-bit addressing
and external stack memory so that the total
spectrum of application could be significantly
increased. The 8080 was first sampled in December
1973. Since that time it has become the standard of
the industry and is accepted as the primary building
block for more microcomputer based applications
than all other microcomputer systems combined.

5~
o

~

\

\
\

5
4
3

\

\

1

0
1973

1974

--.....
1975

1976

YEAR

A TOTAL SYSTEMS COMMITMENT
The Intel® 8080A Microcomputer System encompasses a total systems commitment to the user to
fully support his needs both in developing prototype

PROTOTYPE

5-1

PRODUCTION

1977

INTRODUCTION TO MCS-85™
THE MCS-85 '" MICROCOMPUTER
SYSTEM
This section of the MCS-S5 User's Manual will briefly
detail the basic differences between the MCS-S5 and
MCS-SO"families. It will illustrate both the hardware
and software compatibilities and also reveal some of
the engineering trade-offs that were met during the
design of MCS-S5. More detailed discussion of the
MCS-S5 bus operation and component specifications are available in Sections: 2,3,4, but the
information provided in this section, Section 1, will
be extremely helpful in understanding the basic
concepts and philosophies behind the MCS-S5.

The basic philosophy behind the MCS-S5 microcomputer system is one of logical, evolutionary
advance in technology without the waste of
discarding existing investments in hardware and
sotware. The MCS-S5 provides the existing SOSO
user with an increase in performance, a decrease in
the component count, a single 5 volt operation and
still preserves 100% of his existing software
investment. For the new microcomputer user, the
MCS-S5 represents the refinement of the most
popular microcomputer in the' industry, the Intel
SOSO, along with a wealth of supporting software,
documentation and peripheral components to
speed the cycle from prototype to production. The
identical development tools that Intel has produced
to support the SOSO microcomputer system can be
used for the MCS-S5, and additional add-on features
are available to optimize system development for
MCS-S5.

It is important for the reader of the MCS-S5 User's
Manual to have a solid understanding of the SOSO
microcomputer system. Most of the terms and
procedures that are used in the MCS-S5 User's
Manual are based on information in the MCS-SO
User's Manual. Please refer to the MCS-SO"User's
Manual as required.

MCS-8S'" TOTAL SYSTEM

5-2

INTRODUCTION TO MCS-85™
SYSTEM INTEGRATION
The MCS-S5 integrates many of the functions that
are auxiliary to an SOSOA based system. Functions
such as: clock generation, system control and
interrupt prioritizing are integrated into on-chip
features of the SOS5 Central Processor. The SOS5 is,
of course, the central element in the MCS-S5 family.
It coordinates all bus transfers and operations and
executes the instruction set. The SOS5 CPU is
designed to be the controlling master of a unique,
multiplexed bus system. This bus structure will be
discussed in detail later in the manual but basically,
the information provided on the data bus is timemultiplexed and contains both data and the lower S
address bits(A7-AO). The address bus contains the
remaining S-bits (AS-A 15). The SOS5 CPU generates
signals that tell peripheral devices what type of
information is on the multiplexed bus (Address/
Data) and from that point on the operation is almost
identical to the MCS-SO'· CPU Group. The mUltiplexed bus structure was chosen because it had no
detrimental effect on system performance, allowed
complete compatibility to existing peripheral components, provided improved timing margins and
access requirements and freed device pins so that
more functions could be integrated 0:1 the SOS5 and
other components of the family.

ADDRESS BUS

DATA
BUS
MEMRD

MEMWR
IIORD
I/OWR

MCs..SO CPU GROUP
(BASIC FUNCTIONS)

MCS-80'· CPU GROUP (BASIC FUNCTIONS)

ADDRESS BUS
8085
ALE

To enhance the system integration of MCS-S5,
several special components with combined memory and I/O were designed. These new devices have
been designed to directly interface to the multiplexed bus of the 80S5. It is interesting to note that
the pin locations of the SOS5 and the special
peripheral components were assigned to minimize
PC board area and allow for a smooth, efficient
layout. The details on the new peripheral components will be discussed later in the manual.

INTR

-.-----1

INTA

_----q

RESET IN

----~

RESET OUT

-----1

MULTIPLEXED
DATA BUS

f ' - - - - AD
f ' - - - - iNA

1----

10/M

MCS-S5 CPU/BOS5
(BASIC FUNCTIONS)

MCS-85'· CPU/8085!BASIC FUNCTIONS)

DATA/ADDRESS BUS

====J(___

DATA IN OR OUT

ADDRESS

~

--'X'-_____

A A
7' _O _ _

L

0_7.D_o_ _ _ _

TIME MULTIPLEX DATA BUS

MULTIPLEXED BUS TIMING

5-3

INTRODUCTION TO MCS-85™
SOFTWARE COMPATIBILITY
As with any computer system the cost of software
development far outweighs those of hardware. A
microcomputer-based system is traditionally a very
cost-sensitive application and the development of
software is one of the key areas where success or
failure of the cost objectives is vital.

The 8085 CPU does however add two instructions to
initialize and maintain hardware features of the
8085. Two of the unused opcodes of the 8080A
instruction set were designated for the addition so
that 100% compatibility could be maintained.
As mentioned previously, the MCS-85 is designed to
be a logical, evolutionary advance that solves
problems in the most efficient, cost effective manner
available. 100% software compatibility fulfills one of
the most 'important aspects of the overall MCS-85
system philosophy.

808S

808DA
PROGRAMS

SYSTEM

HARDWARE COMPATIBILITY

The 8085 CPU is 100% software compatible with the
Intef8080A CPU. The compatibility is at the object
or "machine code" level so that existing programs
written for 8080A execution will run on the 8085 as is.
This becomes even more evident to the user who has
mask programmed ROMs and wishes to update his
system without the need for new masks.

The integration of auxiliary 8080A functions, such as
clock generation, system control and interrupt
prioritization, dramatically reduces the amount of
components necessary for most systems, In
addition to integrating some of the MCS-80™ system
functions, the MCS-85 operates off a single +5
volt power supply to further simplify hardware
development and debug. A close examination of the
AC/DC specifications of the MCS-85 systems
components snows that each is specified to supply a
maximum of 400 micro Amps of source current and a
full TTL load of sink current so that a very substantial
system can be constructed without the need for
extra TTL buffers or drivers. Input and output
voltage levels are also specified so that a minimum
of 400 microvolts noise margin is provided for
reliable, high-performance operation,

PROGRAMMER TRAINING
A cost which is often forgotten is that of programmer
training. A new, or modified instruction set, would
require programmers to re'learn another set of
mnemomics and greatly effect the productivity
during development. The 100% compatibility of the
8085 CPU assures that no re-training effort will be
required.
For the new microcomputer user, the software
compatibility between the 8085 and 8080A means
that all of the software development tools that are
available for the 8080A and all software libraries for
8080A will operate with the new design and thus
save immeasurable cost in development and debug.

808DA
DEVELOPMENT
TOOLS

PC BOARD CONSIDERATIONS
The 8085 CPU and the 8080A are not pin-compatible
due to the reduction in power supplies and the
addition of integrated auxiliary features. However
the pinouts of the MCS-85 system components were
carefully assigned to minimize PC board area and
thus yield a smooth, efficient layout. For new
designs this incompatibility of pinouts presents no
problems and for upgrades of existing designs the
reduction of components and board area will far
offset the incompatibility.

8080A
PROGRAM
LIBRARIES

~/
MCS·85™

5-4

INTRODUCTION TO MCS-85™
I

elK

MCS-85™ SPECIAL PERIPHERAL
COMPONENTS

READY

The MCS-85 was designed to minimize the amount
of components required for most systems. Intel
designed several new peripheral components that
combine memory, 1/0 and timer functions to fulfill
this requirement. These new peripheral devices
directly interface to the multiplexed MCS-85 bus
structure and provide new levels in system
integration for today's designer.

ADO---7

i

Aa--l0
eE

2K

xB

EPROM

101M

B

PA()--,7

G

PB(}-7

ALE

R5
lOW
RESET

101M

ADO~7

lOR

B
B

256 X 8
STATIC

RAM

*
ALE

R5

PROG/CE~

Socket compatible with 8355
2K bytes EPROM
2- 8-bit ports (direction programmable)
Single +5 volt supply read operation
U.V. Erasable
40 pin DIP package

G

TIMER

Lvcc

TIMER IN

(+5V)

vss toV)

TIMER OUT

Vss (OV)

8755 EPROM and 1/0

iNA
RESET

~VCCI+5V)

VDD

8755/8355

*: 8155 = CE, 8156 = CE

One of the most important advances made with the
MCS-85 is the socket-compatibility of the 8355 and
8755 components. This allows the systems designer
to develop and debug in erasable PROM and then,
when satisfied, switch over to mask-programmed
ROM 8355 with no performance degradation or
board relayout. It also allows quick prototype
production for market impact without going to a
"kluge" solution.

8155/8156 RAM, 1/0 and Timer

256 bytes RAM
2- 8-bit ports
1- 6-bit port (programmable)
1- 14-bit programmable interval timer
Single +5 volt supply operation
40 pin DIP plastic or cerdip package

1/0 PORTS

elK---~--.,

TIMER IN

TIMER OUT

~VCOI'5VI
Vss (OV)

1/0 PORTS

1/0 PORTS

SYSTEM EXPANSION

8355 ROM and 1/0

Each of these peripheral components has features
that allow a small to medium system to be
constructed without the addition of buffers and
decoders to further reduce the component count.

2K bytes ROM
2- 8-bit ports (direction programmable)
Single +5 volt supply operation
40 pin DIP plastic or cerdip package
5-5

r

INTRODUCTION TO MCS-85™

SERIAL
DATA
LINES

INTERRUPTS

I

II I I

RST 1.5 RST 6.5 RST 5.5

r

TRAP

'(

SID

I IIII

PORT C

PORT A

I

~

r

(
RESET IN

SOD

'II I I

11

PA(I-------- PAl

51 SO

I

PORT B

I

I r II UIllH

PCD------~PC5

P80--------P81

0
-=c:.

81!i6RAM -lID - TIMER/COUNTER
(256118)

8085 CPU

X,

'0/
Pi

ifD
ADO-------AO, Aa-------A15 ALE

ADD
AD,

-,

T IMER/COUNTER
N

~X,

I

WR

HOLD
eLK
RESET j
lNTR

I ROY

I OUT

'0/

HlDA fJJTA

11

_ T IMER/COUNTER

ifii M
W1i IRESET

OUT

AOo'-- - - - - -AD] CE ALE I

11

~

}
}

AD,
AD,

ADR
DATA

AD,
AD,
AD,
AD,
A,
A.
AlO
A"
A12

ADR

A13
A14
A15

-

ALE
RD

W;;

I!O/M
READY

t- CONTROL

elK
RESET

HOLD

HLDA
INTR
INTA

-

'L

CE

I
A10

Ag

I RESETI ROY

_WR
elK 101M RD

As

CE

PAo- - - - - - - - - .PAl

1 &81T IJO-ST ATUS PORT

I II I

4 INTERRUPT LEVELS
2 SERIAL I/O LINES

5-6

P80- - - - - - - - -

11_1

"

PB7

I II JlJJ
I

I

PORT A

MCS-85'· BASIC SYSTEM

- - - - AD 1

8355 ROM -110
8755 PROM -I/O
2K x B

2K BVTES ROM

256 BYTES RAM
1 INTERVAL TIMER/EVENT COUNTER
4 8-81T I/O PORTS

ALE ADo·-

PORT B

INTRODUCTION TO MCS-85™
INTERFACING TO MCS-80™
PERIPHERAL COMPONENTS

o

The MCS-80 has a wide range of peripheral
components that solve system problems and
provide the designer with a great deal of flexibility in
his 110, Interrupt and DMA structures. The MCS-85
is directly compatible with these peripherals, and,
with the exception of the 8257 DMA controller,
needs no additional circuitry for their interface. The
8257 DMA controller uses an 8212 latch and some
gating to support the multiplexed bus of MCS-85.

8085
ALE

MULTIPLEX BUS
To understand the exact interface between the
MCS-85 and the MCS-80 T• peripheral components,
recall that the 8080A CPU issues the address of the
I/O device on its 16-bit address bus. The I/O address
appears on both the upper and lower 8-bits of the
address bus. The 8085 CPU utilizes a multiplexed
bus structure where the address bus contains only
the upper 8-bits of information. The data bus
contains both data and the lower 8-bits of
information of the address. Since the read/write
control signals are only issued when there is data on
the bus and the address bus contains the I/O device
address, then all of the MCS-80 peripherals will
interface directly with no hardware or software
problems. In fact, due to the manner in which the
8085 control signals were implemented, memorymapped I/O becomes simpler to use than with MCS80 and combinations of memory-mapped and
standard I/O techniques will provide the designer
with new flexibilities to maximize system efficiency.

o
8085
CONTROL BUS

MCS-80™ PERIPHERALS
To interface 825X peripherals to 8085 bus at 3M Hz,
the user must use a set of MCS-80 peripherals,
called, "82SX-S". It includes 8251A, 8253-5, 8255A-5,
8257-5 and 8259-5 as shown below:
8251A
8253-5
8255A-5
8257-5
8259-5

Programmable
Interface
Programmable
Programmable
Programmable
Programmable

SERIAL I/O

Communications
Interval Timer
Peripheral Interface
DMA Controller
Interrupt Controller

This compatibility also assures the designer that all
new peripheral components from Intel will interface
to the MCS-85 bus structure to further expand the
application spectrum of MCS-85.

5-7

MEMR,

lOR,

MEMW,

lOW

INTRODUCTION TO MCS-85™
INTERFACING TO STANDARD MEMORY

o

The MCS-85 was designed to support the full range
of system configurations from small 3 chip
applications to large memory and I/O applications.
The 8085 CPU issues advanced timing signals (SO &
S 1) so that, in the case of large systems, these
signals could be used to simplify bus arbitration
logic and dynamic RAM refresh circuitry.

8085

The multiplexed bus structure of the MCS-85
provides direct interface to MCS-80™ peripheral
components, but in large, memory intensive
systems, standard ROM and RAM memory will be
present due to the economies of such devices when
used in large quantities per system. In most memory
intensive systems I/O requirements do not generally track memory space. Thus standard memory
is a more cost effective solution for these
applications than the special 8155, 8355 devices.

DEMUL TIPLEXING THE BUS
In order to interface standard memory components
such as Intel® 8102A, 8101A, 8111A, 8316A, 8308,
2104 and 2116 the MCS-85 bus must be "demultiplexed". This is accomplished by connecting
an Intel® 8212 latch to the data bus and strobing the
latch with the ALE signal from the 8085 CPU. The
ALE signal is issued to indicate that the information
on the data bus is actually the lower 8-bits of the
address bus, and the 8212 simply latches this
information so that a full 16-bit address is now
available to interface standard memory components.

USE OF 8212
The additional component may at first seem
wasteful but large, memory intensive systems are
usually multi-card implementations and require
some form of TTL buffering to provide necessary
current and voltage levels. Therefore, the additional
8212 will probably be required for the buffering task
and the de-multiplexing of the data bus is incidental.

5-8

INTRODUCTION TO MCS-85™
SYSTEM PERFORMANCE
The true benchmark of any microcomputer-based
system is the amount of tasks that can be assigned
to the software execution and still meet the overall
product performance requirements. Speed of CPU
instruction execution has been the common
approach to system through-put problems but this
puts a greater strain on the memory access
requirement and bus operation than is usually
practical for most applications. A much more
desirable method would be to distribute the taskload to peripheral devices and free the systems
software to simply initializing and maintaining
these devices on a regular basis.

20
15
10

-\
\

\

\

--

\

-~

\

---

1
0
1973

DISTRIBUTED PROCESSING

1974

1975

1976

YEAR

The concept of distributed task processing is not
new to the computer designer, but until recently
little if any task distribution was available to the
microcomputer user. The MCS-85 is fully supported
by Intel's MCS-80'· peripheral components. All are
programmable and each can relieve the systems
software of many of the bookkeeping I/O and timing
tasks common to any system.

8085
CPU

INSTRUCTION CYCLE/ACCESS
The basic instruction cycle of the 8085 is 1.3
microseconds. It is the same speed as the 8080A-1
and a closer look at the MCS-85 bus operation
shows that the access requirement for this speed is
only 450 nanoseconds. The MCS-80'· access
requirements for this speed would be under 300
nanoseconds to illustrate the efficiency and
improved timing margins of the MCS-85 bus
structure.

MEMORY

THROUGHPUT/COST
When a total system through-put analysis is taken,
the MCS-85 with its programmable peripheral
components will yield the most cost-effective,
reliable and producible system available.

FOR MORE INFORMATION
Data Sheets on the 8085, 8155/56, 8355, and 8755
are provided later in this manual.
More detailed information on MCS-85 is available in
the Intel® MCS-85 User's Manual.

5·9

1977

i

r

Chapter 6

MICROCOMPUTER SYSTEM
COMPONENT DATA SHEETS

~
I

CPU Group

CPU Group
8080A 8-Bit Microprocessor
_................. . . . . . . . . . . . . . . . . . . . . . . .
8080A-l 8-Bit Microprocessor ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8080A-2 8-Bit Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8080A 8-Bit Microprocessor (MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , .. , .
8224 Clock Generator and Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8224 Clock Generator and Driver (MIL)
. .. .. . . . . . . . . . . . . . . . . .. . . . . . . . .
8801 Clock Generator Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8228/8238 System Controller and Bus Driver
.................... . . . . . . . . .
M8228/M8238 System Controller and Bus Driver (M I L) . . . . . . . . . . . . . . . . . . . . . . .
8085 Single Chip 8-Bit N-Channel Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . .

6-1
6-8
6-12
6-16
6-20
6-26
6-30
6-32
6-38
6-43

inter

8080A
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The 8080A is functionally and electrically compatible with the Intef® 8080.

• TTL Drive Capability
• 2 JLs Instruction Cycle
Problem Solving
• Powerful
Instruction Set
General Purpose Registers
• Six
and an Accumulator
Bit Program Counter for
• Sixteen
Directly Addressing up to 64K Bytes

Bit Stack Pointer and Stack
• Sixteen
Manipulation Instructions for Rapid
Switching of the Program Environment
and Double
• Decimal,Binary
Precision Arithmetic
to Provide Priority Vectored
• Ability
Interrupts
• 512 Directly Addressed I/O Ports

of Memory
The Intel@ BOBOA is a complete B·bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MOS process. This offers the user a high performance solution to control and processing applications.
The BOBOA contains six B-bit general purpose working registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The BOBOA has an external stack feature wherein any portion of memory may be used as a last inlfirst out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the BOBOA the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and B-line bi-directional data
busses are used to facilitate easy interface to memory and 110. Signals to control the interface to memory and I/O are provided directly by the BOBOA. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
D7

8080A CPU FUNCTIONAL
BLOCK DIAGRAM

Do

BI-DIRECTIONAL
DATA BUS

(8 BIT)
INTERNAL DATA BUS

lSi
181
18)

STACK POINTER

~ 161

{16)

PROGRAM COUNTER

1-

PQWER
SUPPLIES

_

TIMING
AND
CONTROL
+12V
+5V

_-5V
_GND

WR

61

DBIN

02

RESET

A15

·"o

ADDRESS BUS

6-1

REGISTER
ARRAY

8080A

8080A FUNCTIONAL PIN DEFINITION
The following describes the function of all of the 8080A I/O pins.
Several of the descriptions refer to internal timing periods.

2

40

All

39

A14
A13

A15.AO (output three-state)
ADDR ESS BUS; the address bus provides the address to memory
(up to 64K 8-bit words) or denotes the I/O device number for up
to 256 input and 256 output devices. Ao is the least significant
address bit.

3

38

4

37

5

36

6

35

Dr Do (input/output three-state)
DATA BUS; the data bus provides bi-directional communication
between the CPU, memory, and I/O devices for instructions and
data transfers. Also, during the first clock cycle of each machine
cycle, the 8080A outputs a status word on the data bus that describes the current machine cycle. Do is the least significant bit.

8

7
9
10

SYNC (output)
SYNCHRONIZING SIGNAL; the SYNC pin provides a signal to
indicate the beginning of each machine cycle.
DBIN (output)
DATA BUS IN; the DBIN signal indicates to external circuits that
the data bus is in the input mode. This signal should be used to
enable the gating of data onto the 8080A data bus from memory
or I/O.
READY (input)
READY; the READY signal indicates to the 8080A that valid
memory or input data is available on the 8080A data bus. This
signal is used to synchronize the CPU with slower memory or I/O
devices. If after sending an address out the 8080A does not receive a READY input, the 8080A will enter a WAIT state for as
long as the READY line is low. READY can also be used" to single
step the CPU.

o
o

As

34

INTE~

33

8080A

31

A'2
A,s
Ag

o

A7
A6

32

As

o

11

30

RESET

12

29

A4
AJ

HOLD

13

28

+12V

INT
92

14

27

15

26

A2
A,

INTE 0
DBIN 0

16

25

17

24

WR
SYNC

18

23

READY

19

22

9,

+5V

20

21

HLDA

Ao
WAIT

Pin Configuration
will go to the high impedance state. The HLDA signal begins at:
• T3 for READ memory or input.
• The Clock Period following T3 for WR ITE memory or OUTPUT operation.

WAIT (output)
WAIT; the WAIT signal acknowledges that the CPU is in a WAIT
state.
WR (output)
WRITE; the WR signal is used for memory WRITE or I/O output
control. The data on the data bus is stable while the WR signal is
active low (WR = 0).
HOLD (input)
HOLD; the HOLD signal requests the CPU to enter the HOLD
state. The HOLD state allows an external device to gain control
of the 8080A address and data bus as soon as the 8080A has completed its use of these buses for the current machine cycle. It is
recognized under the following conditions:
• the CPU is in the HALT state.
• the CPU is in the T2 or TW state and the READY signal is active.
As a result of entering the HOLD state the CPU ADDRESS BUS
(A15-AO) and DATA BUS (DrDo) will be in their high impedance
state. The CPU acknowledges its state with the HOLD ACKNOWLEDGE(HLDA)p~.

HLDA (output)
HOLD ACKNOWLEDGE; the HLDA signal appears in response
to the HOLD signal and indicates that the data and address bus

6·2

In either case, the H LDA signal appears after the rising edge of cfJ1
and high impedance occurs after the rising edge of cfJ2'
INTE (output)
INTE R RUPT ENAB LE; indicates the content of the internal interrupt enable flip/flop. This flip/flop may be set or reset by the Enable and Disable Interrupt instructions and inhibits interrupts
from being accepted by the CPU when it is reset. It is automatically reset (disabling further interrupts) at time T1 of the instruction fetch cycle (M 1) when an interrupt is accepted and is
also reset by the RESET signal.
INT (input)
INTERRUPT REQUEST; the CPU recognizes an interrupt request on this line at the end of the current instruction or while
halted. If the CPU is in the HOLD state or if the Interrupt Enable
flip/flop /s reset it will not honor the request.
RESET (input) [1]
RESET; while the RESET signal is activated, the content of the
program counter is cleared. After RESET, the program will start
at location 0 in memory. The INTE and HLDA flip/flops are also
reset. Note that the flags, accumulator, stack pointer, and registers
are not cleared.
VSS
Ground Reference.
Voo
+12 ± 5% Volts.
Vce
+5 ± 5% Volts.
VBe
-5 ±5% Volts (substrate bias).
cfJl, cfJ2 2 externally supplied clock phases. (non TTL compatible)

8080A

ABSOLUTE MAXIMUM RATINGS*
*COMMENT: Stresses above those listed under ''Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Temperature Under Bias . . . . . . . . . . . . . . . O°C to +70° C
Storage Temperatu re .. . . . . . . . . . . . . . _65° C to + 150° C
All Input or Output Voltages
With Respect to V BB . . . . . . . . . . . . . . -0.3V to +20V
Vcc, V DD and Vss With Respect to VBB
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

D.C. CHARACTERISTICS
TA ~ o°c to 70 e, VDD ~ +12V ± 5%, Vcc
0

Symbol

~ +5V ± 5%, VBB ~ -5V ± 5%, Vss ~ OV, Unless Otherwise Noted.

Parameter

Typ.

Min.

Max.

Unit

VsS+0.8

V

VILC

Clock Input Low Voltage

VIHC

Clock Input High Voltage

9.0

V DD +l

V

V IL

Input Low Voltage

Vss-l

Vss+0.8

V

VIH

Input High Voltage

3.3

Vcc+l

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

Vss-l

3.7

V

Test Condition

} IOL = 1.9mA on all outputs,
IOH ~-l50J.!A.

IDDIAV)

Avg. Power Supply Current (VDD)

40

70

mA

ICCIAV)

Avg. Power Supply Current (V CC )

60

80

mA

IBBIAV)

Avg. Power Supply Current (V BB )

.01

1

mA

IlL

Input Leakage

±10

f.l.A

VSS .;; VIN .;; VCC

ICL
I DL [21

Clock Leakage

±10

f.l.A

Vss .;; VCLOCK .;; VDD

Data Bus Leakage in I nput Mode

-100
-2.0

f.l.A
mA

VSS ';;VIN ';;VSS + 0.8V

+10
-100

f.l.A

IFL

Address and Data Bus Leakage
During HOLD

} Op,.doo
TCy ~ .48 f.l.sec

Vss +0.8V';;VIN ';;VCC
VADDR/DATA ~ VCC
V ADDR/DATA ~ Vss + 0.45V

CAPACITANCE
T A ~ 25°C
Symbol

TYPICAL SUPPLY CURRENT VS.
TEMPERATURE, NORMALIZED.13l

VCC ~ V DD ~ Vss ~ OV, VBB ~ -5V
Parameter

Typ.

1.5

Max.

Unit

C¢

Clock Capacitance

17

25

pf

fc

CIN

I nput Capacitance

6

10

pf

Unmeasured Pins

COUT

Output Capacitance

10

20

pf

Returned to Vss

Test Condition
~

NOTES:
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When DBIN is high and VIN > VIH an internal active pull up will
be switched onto the Data Bus.
3. AI supply / AT A = -0.45%f c.

1 MHz

0.5 O~----:+2'::-5----+6.J..O----+.J76
AMBIENT TEMPERATURE

rei

DATA BUS CHARACTERISTIC
DURING DBIN

V IN

6-3

I

!

8080A
A.C. CHARACTERISTICS
T A ~ O°C to 70°C, Voo ~ +'2V ± 5%, VCC ~ +5V ± 5%, VBB ~ -5V ± 5%, VSS ~ OV, Unless Otherwise Noted
Symbol
tCy[3]

Parameter
Clock Period

Min.

Max.

Unit

0.48

2.0

J.Lsec

50

nsec

t" tf

Clock Rise and Fall Time

0

t,p1

1/>1 Pulse Width

60

nsec

t¢2

¢2 Pulse Width

220

nsec

t01

Delay 1/>1 to 1/>2

0

nsec

t02

Delay 1/>2 to 1/>1

70

nsec

t03
tOA [2]

Delay 1/>1 to 1/>2 Leading Edges

80

Address Output Delay From 1/>2

200

nsec

too [2]

Data Output Delay From 1/>2

220

nsec

tOC[2]

Signal Output Delay From 1/>1, or 1/>2 (SYNC. WR,WAIT, HLOA)

120

nsec

tOF [2]

DBIN Delay From 1/>2

140

nsec

tOI[1]

Delay for Input Bus to Enter Input Mode

tOF

nsec

tOS1

Data Setup Time During 1/>1 and DB IN

Test Condition

nsec

25

CL

}

}CL

~ 'OOpf

~50pf

nsec

30

TIMING WAVEFORMS[14] (Note: Timing measurements are made at the following reference voltages: CLOCK "'" ~ 8.0V
"0" ~ '.OV; INPUTS "'" ~ 3.3V, "0" ~ 0.8V; OUTPUTS "'" ~ 2.0V, "0" ~ 0.8V.)

Ii,

rr-

~['."ev-~
~

",
... t 03 --

1:-I

-- I

1---'0.-':'1'
-too-I

1---

-r

SYNC

-- to:lCBIN

X

t02

-

-----

J~

-----

tOII-

~

-- --f-tAW

..\...

---- ---

--i

I--t oo-

toHI-

~

g~TA IN

---- ---tow

-

- - t052 -

OATA OUT

1

-I
I

- tocl---

t

1

I-to,":'1
READV

f-I

I

-- --::.. to:t- ~
·t:--~

....---..

~

--1 --

-

F\

\

--toF .....1

----------------------

I

-

~@

tR~~

tH-

WAIT

-

-

toc--"
HOLD

toe

.L'H"I~

t

'1-

-

-3--!f~ 1--:1

tH1_

---I~:
HlOA

INT

I· -

I@ .l.

--

X@~

tl~~

tH ----. ...

INTE

6-4

8080A

A.C. CHARACTERISTICS

(Continued)

TA = O°C to 70°C, VDD = +12V ± 5%, VCC = +5V ± 5%, VBB = -5V ± 5%, VSS = OV, Unless Otherwise Noted
Symbol

Min.

Parameter

Max.

Unit

tDS2

Data Setup Time to r/J2 During DBIN

150

nsec

tDH [1J

Data Hold Time From r/J2 During DBIN

[1]

nsec

tiE [2J

INTE Output Delay From r/J2

tRS

READY Setup Time During r/J2

120

200

tHS

HOLD Setup Time to r/J2

140

nsec

tiS

I NT Setup Time During r/J2 (During <1>1 in Halt Mode)

120

nsec

tH

Hold Time From r/J2 (READY, INT, HOLD)

tFD

Delay to Float During Hold (Address and Data Bus)

tAW[2J

Address Stable Prior to WR

[5J

tDW[2J

Output Data Stable Prior to WR

[6J

nsec

tWD[2J

Output Data Stable From WR

[7J

nsec

tWA[2J

Address Stable From WR

[7J

nsec

tHF[2J

HLDA to Float Delay

[8J

nsec

tWF[2J

WR to Float Delay

[9J

nsec

tAH [2]

Address Hold Time After DBIN During HLDA

-20

nsec

Test Condition

CL = 50pf

nsec
nsec

nsec

0
120

nsec
nsec

-

I- C L = 100pf:_ Address, Data

CL =50pf: WR, HLDA, DBIN

-

NOTES:
1. Data input should be enabled with DB IN status. No bus conflict can then occur and data hold time is as",ured.
tOH :: 50 os or tOF, whichever is less.
2. Load Circuit.

+5V

2.1K
8080A
OUTPUT

3. tey '" t03 + tr1>2 + tl/>2 + tfcp2 + t02 + tr4>1 ;:. 480n5.

TYPICAL

Il.

OUTPUT DELAY VS.1l. CAPACITANCE

+20
c

>-

~
0

+10

>-

ii'
>-

=>

..,D

·'0

+100
J. CAPAC IT ANCE (pf)
(CACTUAL - CSPEC )

4. The following are relevant when interfacing the 8080A to devices having VIH "" 3.3V:
a) Maximum output rise time from .8V to 3.3V "" 100ns@CL '" SPEC.

INT

INTE

5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

b) Output delay when measured to 3.0V :: SPEC +60n5 @ CL "" SPEC.
c) If Cl =F SPEC, add .6ns/pF jf CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < C5PEC.
tAW = 2 tey -t03 -t r¢2 -1400sec.
tow'" tey -t03 -t r¢2 -170nsec.
If oat HLOA, two "'tWA'" t03 + tr2 -50ns.
tWF = t03 + trt/>2 -10ns
Data in must be stable for this period during DBIN -T3' 80th tOSl and tD52 must be satisfied.
Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3. T 4, T5
and TWH when in hold mode. (External synchronization is not required.)
Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not reQuired.l
This timing diagram shows timing relationships only; it does not represent any specific machine cycle.

6-5

8080A

INSTRUCTION SET
The accumulator group instructions include arithmetic and
logical operators with direct, indirect, and immediate addressing modes.

increment and decrement memory, the six general registers
and the accumulator is provided as well as extended increment and decrement instructions to operate on the register
pairs and stack pointer. Further capability is provided by
the ability to rotate the accumulator I~ft or right through
or around the carry bit.

Move, load, and store instruction groups provide the ability
to move either 8 or 16 bits of data between memory, the
six working registers and the accumulator using direct, indirect, and immediate addressing modes.

Input and output may be accomplished using memory addresses as 1/0 ports or the directly addressed 1/0 provided
for in the 8080A instruction set.

The ability to branch to different portions of the program
is provided with jump, jump conditional, and computed
jumps. Also the ability to call to and return from subroutines is provided both conditionally and unconditionally.
The RESTART (or single byte call instruction) is useful for
interrupt vector operation.

The following special instruction group completes the 8080A
instruction set: the NOP instruction, HALT to stop processor execution and the DAA instructions provide decimal
arithmetic capability. STC allows the carry flag to be directly set, and the CMC instruction allows it to be complemented. CMA complements the contents of the accumulator
and XCHG exchanges the contents of two 16-bit register
pairs directly.

Double precision operators such as stack manipulation and
double add instructions extend both the arithmetic and
interrupt handling capability of the 8080A. The ability to

Data and Instruction Formats
Data in the 8080A is stored in the form of 8-bit binary integers. All data transfers to the system data bus will be in the
same format.
[07 D6 D5 D4 D3 D2 D1 Dol
DATA WORD
The program instructions may be one, two, or three bytes in length. Multiple byte instructions must be stored
in successive words in program memory. The instruction formats then depend on the particular operation
executed.
One Byte Instructions

TYPICAL INSTRUCTIONS

I D7

Register to register, memory reference, arithmetic or logical, rotate,
return, push, pop, enable or disable
Interrupt instructions

D6 D5 D4 D3 D2 Dty;;] OP CODE

Two Byte Instructions
D7 D6 D5 D4 D3 D2 D1 Do

OPCODE

D7 D6 D5 D4 D3 D2 D1 DO

I OPERAND

Immediate mode or 1/0 instructions

Three Byte Instructions

I OP CODE
Do I LOW ADDRESS OR OPERAND 1
Do I HIGH ADDRESS OR OPERAND 2

D7 D6 D5 D4 D3 D2 D1 Do
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1

Jump, call or direct load and store
instructions

For the 8080A a logic "1" is defined as a high level and a logic "0" is defined as a low level.

6-6

8080A 8-BIT MICROPROCESSOR

6-7

8080A-1
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR
The 8080A is functionally and electrically compatible with the Intet® 8080.

• TTL Drive Capability
• 1.3 JJ.s Instruction Cycle
Problem Solving
• P()werful
Instruction Set
General Purpose Registers
• Six
and an Accumulator
Bit Program Counter for
• Sixteen
Directly Addressing up to 64K Bytes

Bit Stack Pointer and Stack
• Sixteen
Manipulation Instructions for Rapid
Switching of the Program Environment
and Double
• Decimal,Binary
Precision Arithmetic
to Provide Priority Vectored
• Ability
Interrupts
• 512 Directly Addressed 1/0 Ports

of Mernory
The Intel@ BOBOA is a complete B·bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MOS process: This offers the user a high performance solution to control and processing applications.
The BOBOA contains six B-bit general purpose working registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The BOBOA has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the BOBOA the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and B-line bi-directional data
busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the B080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or multi-processor operation.
07 -Do
SI-DIRECTIONAl
DATA BUS

8080A CPU FUNCTIONAL
BLOCK DIAGRAM

(8 BIT)
INTERNAL DATA BUS

lSI

181
181
(16)

STACK POINTER
(16)

PROGRAM COUNTER

1-

POWER

SUPPLIES

_

TIMING
AND
CONTROL

+12V
+5V

_-5V
_GND

WR

OBIN

A'5 ·Ao
ADDRESS BUS

6-8

REGISTER
ARRAY

8080A-1
ABSOLUTE MAXIMUM RATINGS·

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . . . . . . O°C to +70° C
Storage Temperature . . . . . . . . . . . . . . , -65°C to +150°C
All Input or Output Voltages
With Respect to V BB . . . . . . . . . . . . . . -0.3V to +20V
Vcc, VOO and Vss With Respect to V BB
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 1.5W

D.C. CHARACTERISTICS
TA ~ o°c to 70°C, Voo ~ +12V ± 5%, Vcc
Symbol

~ +5V ± 5%, VBB ~ -5V ± 5%, Vss ~ OV, Unless Otherwise Noted.

Parameter

Typ.

Min.

Max.

Unit

VsS+0.8

V

VILC

Clock Input Low Voltage

VIHC

Clock Input High Voltage

9.0

Vo o +l

V

V IL

Input Low Voltage

Vss-l

Vss+0.8

V

VIH

Input High Voltage

3.3

Vcc+ 1

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

100 (AV)

Avg. Power Supply Current (V oo )

40

70

rnA

ICC (AV)

Avg. Power Supply Current (Vcc )

60

80

mA

IBB(AV)

Avg. Power Supply Current (V BB )

.01

1

mA

Vss-l

V

3.7

Test Condition

} IOL = 1.9mA on all outputs,
IOH = 150J.LA.

} 0",,,,,,,"
T cv = .32llsec

IlL

Input Leakage

±10

J.LA

VSS .:;; V IN .:;; Vcc

ICL

Clock Leakage

±10

J.LA

VSS .:;; VCLOCK .:;; VOO

10L ;:l

Data Bus Leakage in I nput Mode

-100
-2.0

IlA
mA

Vss ':;;VIN ':;;VSS +0.8V

+10
-100

IlA

I
IFL

Address and Data Bus Leakage
During HOLD

VSS +0.8V':;;VIN ':;;VCC
VAOOR/OATA = Vcc
V AOOR/OATA = Vss + 0.45V

CAPACITANCE
TA = 25°C
Symbol

TYPICAL SUPPL Y CURRENT VS.
TEMPERATURE, NORMALIZED.13l

VCC = Voo = Vss = OV, VBB = -5V
Parameter

1.5

Typ.

Max.

Unit

Cet>

Clock Capacitance

17

25

pf

fc

CIN

I nput Capacitance

6

10

pf

Unmeasured Pins

CO UT

Output Capacitance

10

20

pf

Retu med to Vss

Test Condition
~

1 MHz

NOTES:
0.5 O;----~+2=5----+~50,.-----+-:!7.5

1. The RESET signal must be active for a minimum of 3 clock cycles.

2. When OBIN is high and VIN > VIH an internal active pull up will
be switched onto the Data Bus.
3. l

2 Pulse Width

145

nsec

tDl

Delay 2 + t¢2 + tf¢2 + t02 + t nPl ;;;. 320ns.

TYPICAL

~

0

-

DBIN

~

.1-- tAH

+10

I

0

t--

;;>
t--

"0

f-J

I--

READY

toc

OUTPUT DELAY VS.

+20

>-

SYNC

~

~~---j<;~~""

>---1iCL

~

r--.

--

. J r . - tWF -

-10

V

-20
-100

/

V

!-t

CAPACITANCE

/

~SPEC

+so

-50
..::. CAPACITANCE

!

~

+100

(pf)

(CACTUAL - C SPEC )

HF -

WAIT

HOLD

f--

-

HLDA

tNT

~

~.

~

I
INTE

toc

I-:l~--------

4. The following are relevant when interfacing the 80S0A to devices having VIH '" 3.3V:
a) Maximum output rise time from .SV to 3.3V = 100ns@CL '" SPEC.
b) Output delay when measured to 3.0V = SPEC +60ns@CL =. SPEC.
c) If CL of. SPEC. add .6ns/pF if CL> CSPEC. subtract .3ns/pF (from modified delay) if CL < CSPEC.
5. tAW == 2 tCY ~tD3 -t r112 -110nsec.
6. tDW == tCY -tD3 -t r¢2 ~, 50nsec.
7. If not HLDA. tWD '" tWA'" tD3 + tr112 +10ns. If HLDA. tWD == tWA = tWF·
8. tHF '" t03 + tr¢2 -50ns.
9. tWF "" t03 + tr$2 -1 Ons
10. Data in must be stable for this period during DBIN 'T3' Both tOS1 and tOS2 must be satisfied.
11. Ready signal must be stable for this period during T2 or TW' (Must be externally synchronized.)
12. Hold signal must be stable for this period during TZ or TW when entering hold mode, and during T3. T 4, T5
and TWH when in hold mode. (External synchronization is not required.)
13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not required,)
14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle.

6-11

inter
8080A-2
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR

• TTL Drive Capability
• 1.5 JJ.s Instruction Cycle
Problem Solving
• Powerful
Instruction Set
General Purpose Registers
• Six
and an Accumulator
Bit Program Counter for
• Sixteen
Directly Addressing up to 64K Bytes

Bit Stack Pointer and Stack
• Sixteen
Manipulation Instructions for Rapid
Switching of the Program Environment

•
•
•

Decimal,Binary and Double
Precision Arithmetic
Ability to Provide Priority Vectored
Interrupts
512 Directly Addressed 1/0 Ports

of Memory
The Intel VIH an internal active pull up will
be switched onto the Data Bus.
3. l!.1 supply Il!. T A = -0.45%f C.

AMBIENT TEMPERATURE (OC)

DATA SUS CHARACTERISTIC
DURING OBIN

,=rm~
o~1
o

___

~~~~_
______

vee

V IN

6-13

8080A-2
A.C. CHARACTERISTICS
TA = o°c to 70°C, Voo = +12V ± 5%, VCC = +5V ± 5%, VBB = -5V ± 5%, Vss = OV, Unless Otherwise Noted
Symbol
tCy[3]

Parameter

Min.

Max.

Unit

.38

2.0

j.lsec

50

nsec

Clock Period

t r , tf

Clock Rise and Fall Time

0

!,p1

tPl Pulse Width

60

nsec

trJ>2

tP2

175

nsec

t01

Delay tP1 to

0

nsec

70

nsec

Pulse Width

tOF [2]

tP2
Delay tP2 to ifJ1
Delay cp, to tP2 Leading Edges
Address Output Delay From tP2
Data Output Delay From tP2
Signal Output Delay From ifJ1, or tP2 (SYNC, WR,WAIT,HLOAI
DBIN Delay From tP2

tOI[11

Delay for Input Bus to Enter Input Mode

tOS1

Data Setup Time During tPl and DBIN

t02
t03
tOA[2]
too [2]
toc'[2]

TIMING WAVEFORMS[14]

-0

175

nsec

200

nsec

120

nsec

'40

nsec

tOF

nsec

25

}

C L = 100pf

} CL =50pf

nsec

20

'j

~tCY

~

nsec

70

(Note: Timing measurements are made at the following reference voltages: CLOCK "'" = 8.0V
"0" = 1.0V; INPUTS "'" = 3.3V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.)

f\

"t

.,

Test Condition

---

~

\.

.... t 03 ' "

--

-1

t02

-

itt -

l\

F\
r------.

iF--

~

f-t

I

A,s',," ----------+---'-~r----

~tDA-1

1

t---too .......

1---

0 7 ,00

1:

-

1-I -:: -. DATA IN
--1'"- .... ~-t-­ ~
tos
1
I-t
tOl

----------+--Il·,..~------

1 1............

+_Jl1

SYNC _ _ _ _ _ _ _ _ _

-ltD~I_

052 -

I

-.tDcl--~-----+--,

+-_..1
.....-"

t

j.-tOF-..j

--tOF--l

OBIN _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tDCi--"
tH-'~

--A::..©l-l"*:-

~@

READY
-

tR:

1= -

'RS

....;'H;..-.-'-;..-_+-.l7I1

WAIT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

°1_

~

I

t DC

--:1 I
t~_t+_--_tt_-j
tH

-'.1:--

HOLO _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _l~.i!*ll~Jl~-_tt_-j

-ltHS~
HLOA

----------------------------------------------------------------------~~
INT

INTE

6-14

808QA-2

A.C. CHARACTERISTICS

(Continued)

TA = O°C to 70°C, V DD = +12V ± 5%, Vcc = +5V ± 5%, V BB = -5V ± 5%, Vss = OV, Unless Otherwise Noted
Min.

Parameter

Symbol
tDS2

Data Setup Time to r/>2 During DBIN

tDH [11

Data Hold Time From r/>2 During DBIN

tiE [21

INTE Output Delay From r/>2

tRS

READY Setup Time During r/>2

tHS
tiS

Max.

Unit

130

nsec

[11

nsec
200

Test Cond ition

nsec

90

nsec

HOLD Setup Time to r/>2

120

nsec

I NT Setup Time During 1>2 (During <1>1 in Halt Model

100

nsec

0

nsec

tH

Hold Time From r/>2 (READY, INT, HOLDI

tFD

Delay to Float During Hold (Address and Data Busl

tAW[21

Address Stable Prior to WR

[51

nsec

tDW[21

Output Data Stable Prior to WR

[6]

nsec

two [2]

Output Data Stable From WR

[7]

nsec

tWA[2]

Address Stable From WR

[7]

nsec

120

CL = 50pf

nsec

tHF[21

HLDA to Float Delay

[81

nsec

tWF[2]

WR to Float Delay

[9]

nsec

tAH[21

Address Hold Time After DBIN During HLDA

-20

nsec

-

~

C L = 1OOpf: Address, Data
CL =50pf: WR, HLDA, DBIN

.-

NOTES

.

1. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured.
tOH '" 50 ns or tDF. whichever is less.
2. Load Circuit .

,

+5V

9

.,

BOBOA
OUTPUT

A'S,A O

3. tey '" tD3 + t r ¢2 + tl/.l2 + tfr,b2 + t02 + t rrpl ;;. 380ns.

TYPICAL
+20

°7-0 0
0

>-

SYNC

~
;;:""

A

OUTPUT DELAY VS.

--1--

A

CAPACITANCE

+10

0

DBIN

""a:J
..,

VIR

-'0

+100

READY

J. CAPAC IT ANCE (pf)
(CACTUAl - C SPEC )

4. The following are relevant when interfacing the 8080A to devices having VIH "" 3.3V:

WAIT

al Maximum output rise time from .BV to 3.3V 1OOns @ CL SPEC.
b) Output delav when measured to 3.0V::; SPEC +60ns @ CL = SPEC.
cl If CL =t SPEC, add .6ns/pF if CL> CSPEC, subtract .3ns/pF (from modified delay) if CL < CSPEC.
tAW'" 2 tCY -t03 -t r 01>2 -130nsec.
tow'" tCY -t03 -t r 01>2 -170nsec.
If not HLDA, two'" tWA = t03 + tr01>2 +10ns. If HLOA, two = tWA"" tWF·
t HF = t03 + tn/)2 -50ns.
twF '" t03 + t r.p2 -10ns
Data in must be stable for this period during OBIN ·Ta. Both tOSl and tOS2 must be satisfied.
Ready signal must be stable for this period during T2 or TW' (Must be externally synchronized.)
Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3. T 4. T5
and T WH when in hold mode. (External synchronization is not requiredJ
Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not required.)
This timing diagram shows timing relationships only; it does not represent any specific machine cycle.
::0

HOLD

I5.
6.
7.

HLDA

8.
9.
INT

I-

10.
11.
12.
13.

INTE

14.

6-15

0=

• Sixteen Bit Stack Pointer and Stack
Manipulation Instructions for Rapid
Switching of the Program Environment

• Full Military Temperature Range
-55°C to +125°C
• ±10% Power Supply Tolerance

• Decimal,Binary and Double
Precision Arithmetic

• 2 jJ.s Instruction Cycle
• Powerful Problem Solving
Instruction Set

• Ability to Provide Priority Vectored
Interrupts

• Six General Purpose Registers
and an Accumulator

• 512 Directly Addressed 1/0 Ports

• Sixteen Bit Program Counter for
Directly Addressing up to 64K Bytes
of Memory

• TTL Drive Capability

The Intel® M8080A is a complete 8-bit parallel central processing unit (CPU). It is fabricated on a single LSI chip using Intel's
n-channel silicon gate MaS process. This offers the user a high performance solution to control and processing applications.
The M8080A contains six 8-bit general purpose working registers and an accumulator. The six general purpose registers may be
addressed individually or in pairs providing both single and double precision operators. Arithmetic and logical instructions set
or reset four testable flags. A fifth flag provides decimal arithmetic operation.
The M8080A has an external stack feature wherein any portion of memory may be used as a last in/first out stack to store/
retrieve the contents of the accumulator, flags, program counter and all of the six general purpose registers. The 'sixteen bit
stack pointer controls the addressing of this external stack. This stack gives the M8080A the ability to easily handle multiple
level priority interrupts by rapidly storing and restoring processor status. It also provides almost unlimited subroutine nesting.
This microprocessor has been designed to simplify systems design. Separate 16-line address and 8·line bi·directional data
busses are used to facilitate easy interface to memory and I/O. Signals to control the interface to memory and I/O are provided directly by the M8080A. Ultimate control of the address and data busses resides with the HOLD signal. It provides the
ability to suspend processor operation and force the address and data busses into a high impedance state. This permits ORtying these busses with other controlling devices for (DMA) direct memory access or multi·processor operation.

6-16

M8080A
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . -55°C to +125°C
Storage T emperatu re .. . . . . . . . . . . . .. _65° C to + 150° C
All Input or Output Voltages
With Respect to VS B . . . . . . . . . . . . . . -0.3V to +20V
Vcc, V DD and Vss With Respect to VBB
-0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . , 1.7W

*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. CHARACTERISTICS
TA = -55°C to +125°C, VD D = +12V ±10%, Vcc = +5V ±10%, VBB = -5V ±10%, Vss = OV,
Symbol

Min.

Parameter

Typ.

Max.

Unit

VllC

Clock Input Low Voltage

Vss-1

Vss+0.8

V

VIHC

Clock Input High Voltage

8.5

VDD+1

V

Vil

Input Low Voltage

Vss-1

Vss+O.8

V

VIH

Input High Voltage

3.0

Vcc+1

V

Val

Output Low Voltage

0.45

V

VOH

Output High Voltage

IDD(AV)

Avg. Power Supply Current (V DD )

50

80

mA

ICCIAV)

Avg. Power Supply Current (V CC )

60

100

mA

IBSIAV)

Avg. Power Supply Current (V BB )

.01

1

mA

V

3.7

Unless Otherwise Noted.
Test Condition

} IOl = 1.9mA on all outputs,
IOH = 150J.LA.

} 0 ","";0"
T Cy = .48 J.Lsec

III

I nput Leakage

±10

J.l.A

Vss .;;; VIN .;;; VCC

ICl

Clock Leakage

±10

J.LA

Vss .;;; VClOCK .;;; VDD

IDl[2J

Data Bus Leakage in I nput Mode

-100
-2.0

J.LA
mA

VSS';;;VIN ';;;Vss+0.8V

+10
-100

J.LA

IFl

Address and Data Bus Leakage
During HOLD

VsS+0.8V';;;VIN ';;;Vcc
VADDR/DATA = VCC
V ADDR/DATA = Vss + 0.45V

CAPACITANCE
T A = 25°C
Symbol

TYPICAL SUPPL Y CURRENT VS.
TEMPERATURE, NORMALIZED. [3J

Vcc = VDD = Vss = OV, VBB = -5V
Parameter

1.5,.------,.-------,

Typ.

Max.

Unit

C
O~f-----__I

0.5

NOTES:
1. The RESET signal must be active for a minimum of 3 clock cycles.
2. When DBIN is high and VIN > VIH an internal active pull up will
be switched onto the Data Bus.
3. a I supply I aT A = -0.45%( c.

f------f-------I

-55

+50
AMBIENT TEMPERATURE IOe)

DATA BUS CHARACTERISTIC
DURING DBIN

6-17

+125

M8080A
A.C. CHARACTERISTICS
TA = _55°C to +125°C, voo = +12V ±10%, vcc = +5V ±10%, VBB = -5V ±10%, vss = OV, Unless Otherwise Noted.
Symbol

Parameter

Min.

Max.

Unit

0.48

2.0

11 sec

0

50

nsec

tCy[3]

Clock Peri od

t r , tf

Clock Rise and Fall Time

t1

1 Pulse Width

60

nsec

t2

2 Pulse Width

220

nsec

t01

Delay 1 to 2

0

nsec

t02

Delay 2 to 1

80

nsec

t03

Delay 1 to 2 Leading Edges

80

tOA [2]

Address Output Delay From 2

200

nsec

too [2]

Data Output Delay From 2

220

nsec

toc [2]

Signal Output Delay From 1, or 2 (SYNC. WR.WAIT.HLOAI

140

nsec

tOF [2J

DBIN Delay From 2

150

nsec

tOF

nsec

25

tOI[1]

Delay for I nput Bus to Enter I nput Mode

t051

Data Setup Time During 1 and DBIN

TIMING WAVEFORMS [14]

Test Condition

nsec

30

lQ

0

50pl

nsec

(Note: Timing measurements are made at the following reference voltages: CLOCK "1" = 7.0V,
"0" = 1.0V; INPUTS "1" = 3.0V, "0" = 0.8V; OUTPUTS "1" = 2.0V, "0" = 0.8V.)

---------+---1]1'---- -

,X@
- 'Rsl'r

READY

~@.LI

-

t RS

~

toe .....--.1

.1

WAIT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
'H_--~~--_+_JII

'I_
~

l~rl-

_

'H

_

_+~

-.l~ -

~@!II

------------------------------------------------~_I~D#C·~'---~

HLDA

';'t

@ l Ir-f
- -y--

INT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
JAr

tl~~

tH ___

INTE

6·18

__

M8080A
A.C. CHARACTERISTICS
TA

= _55°C

to +125°C, VDD

= +12V

(Continued)
±1 0%, VCC

= +5V

±1 0%, VBB

= -5V

±1 0%, VSS

= OV,

Min.

Max.

Unless Otherwise Noted.
~~----

Symbol

Parameter
Data Setup Time to 2 During DBIN

tDs2

Unit

Test Condition

nsec

130
[1]

tDH [lJ

Data Hold Time From 2 During DBIN

tiE [2J

INTE Output Delay From 2

tRS

READY Setup Time During 2

120

nsec

tHS

HOLD Setup Time to 2

140

nsec

tiS

INT Setup Time During 2 (During <1>1 in Halt Mode)

120

nsec

tH

Hold Time From 2 (READY, INT, HOLD)

tFD

Delay to Float During Hold (Address and Data Bus)

tAW[2J

Address Stable Prior to WR

[5J

n sec

tDW[2J

Output Data Stable Prior to WR

[6J

n sec

tWD[2J

Output Data Stable From WR

[7J

nsec

tWA[2J

Address Stable From WR

[7J

nsec

tHF[2]

HLDA to Float Delay

[8J

nsec

tWF[2J

WR to Float Delay

[9J

nsec

tAH [2J

Address Hold Time After DBIN During HLDA

-20

nsec

nsec
200

nsec

CL

= 50pf

4

0

nsec

nsec

130

-

I- C L =50pf

-

NOTES
1. Data input should be enabled with DBIN status. No bus conflict can then occur and data hold time is assured.
tOH == 50 ns or tDF. whichever is less.
2. Load Circuit

+5V

M80BOA
OUTPUT
~

Y

7-~--

I

1-

-- 1--- -

~

~

,~

l

F~~2'lK
~

150"A

1--.
~-

3. tey == t03 + t r ¢2 + t1>2 + tf1>2 + t02 + treP1 ;. 480ns.

--', tWA

I

r

tFO

-----

_ _1-_.1

'.+--~two

TYPICAL" OUTPUT DELAY VS,,, CAPACITANCE

-~
-~

+20

->-

SYNC

-

DBIN

_f--

:s
tAH

.----~---~-

+10

0

>-

"'>-

:J

0

-10

~

I-f..-.1
I--

--

I
toe

.Jr-tWF +100

READY

-.::. CAPACITANCE (pO

I

HOLD

r~

HlDA

INl

toe

-

r-

____ I
...--tlE-

INTE

(CACTUAL - C SPEC )

- t HF - -

I

WAIT

--)~~:~------

4. The following are relevant when interfacing the M8080A to devices having VIH '" 3.3V:
al Maximum output rise time from .8V to 3.3V '" 100ns@ CL:= SPEC.
bl Output delay when measured to 3.0V:= SPEC +60ns @CL == SPEC.
d If CL SPEC, add .6ns/pF if CL> CSPEC. subtract .3ns/pF (from modified delay) if CL < CSPEC5. tAW == 2 tCY ~tD3 -t nP2 ~140nsec.
6. tow == tCY ~to3 -t rrp2 -170nsec.
7. If not HLOA, two == tWA == t03 + t r¢2 +10ns. If HLOA, two'" tWA = tWF.
8. tHF "" t03 + t rq'.l2 -50ns.
9. tWF:= t03 + t rq'.l2 -10ns
10. Data in must be stable for this period during DBIN 'T3' 80th tOS1 and tOS2 must be satisfied.
11. Ready signal must be stable for this period during T2 or TW. (Must be externally synchronized.)
12. Hold signal must be stable for this period during T2 or TW when entering hold mode, and during T3, T 4, TS
and TWH when in hold mode. (External synchronization is not required.}
13. Interrupt signal must be stable during this period of the last clock cycle of any instruction in order to be
recognized on the following instruction. (External synchronization is not required.)
14. This timing diagram shows timing relationships only; it does not represent any specific machine cycle.

*'

6-19

8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU
Single Chip Clock Generator/Driver
Oscillator Output for External
• for
• System
8080A CPU
Timing
Reset for CPU
Crystal Controlled for Stable System
• Power-Up
•
Operation
Ready Synchronizing Flip-Flop
• Advanced
Status
Strobe
• Reduces System Package Count
•
The 8224 is a single chip clock generator/driver for the 8080A CPU. It is controlled by a crystal, selected by
the designer, to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe and synchronization of ready.
The 8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for 8080A.

BLOCK DIAGRAM

PIN CONFIGURATION

RESET

Vee

RESIN

XTAL 1

RDYIN

XTAl2

READY
SYNC

., ITTL!
STSTB
GND

I!§>

XTAL1

IE>

XTAL2

[j1>

TANK

I-t-----j > - - - O S C

>---.,

-i>--"'

CLOCK
GEN.
+9

TANK

@>

[E>

"

t-----¢,'TTL![S>

.,

OSC

.,

[S>

SYNC

G>

RESIN

@>

RDYIN

-----!---I-,

Voo

I---<~-- RESET

-----H

PIN NAMES
RESIN

RESETINP_~

XTAL 1

RESET

RESET OUTPUT

XTAl2

(

CONNECTIONS
FOR CRYSTAL

USED WITH OVERTONE XTAL

READY INPUT

TANK

READY

READY OUTPUT

OSC

OSCILLATOR OUTPUT

SYNC

SYNC INPUT

¢2 (TTL)

¢2 eLK (TTL LEVEL)

Vee
Voo

+5V

GND

OV

RDVIN

STSTB

.,

~

STATUSSTB
(ACTIVE LOW)

(8080
CLOCKS

6-20

+12V

II>

1 - - - - - READY~

8224
The waveforms generated by the decode gating follow a
simple 2-5-2 digital pattern. See Figure 2. The clocks generated; phase 1 and phase 2, can best be thought of as consisting of "units" based on the oscillator frequency. Assume
that one "unit" equals the period of the oscillator frequency.
By multiplying the number of "units" that are contained in
a pulse width or delay, times the period of the oscillator frequency, the approximate time in nanoseconds can be derived.

FUNCTIONAL DESCRIPTION
General
The 8224 is a single chip Clock Generator/Driver for the
8080A CPU. It contains a crystal·controlled oscillator, a
"divide by nine" counter, two high·level drivers and several
auxiliary logic functions.

The outputs of the clock generator are connected to two
high level drivers for direct interface to the 8080A CPU. A
TTL level phase 2 is also brought out cfJ2 (TTL) for external
timing purposes. It is especially useful in DMA dependant
activities. This signal is used to gate the requesting device onto the bus once the 8080A CPU issues the Hold Acknowledgement (HLDA).

Oscillator
The oscillator circuit derives its basic operating frequency
from an external, series resonant, fundamental mode crystal.
Two inputs are provided for the crystal connections (XTAL 1,
XTAL2).
The selection of the external crystal frequency depends
mainly on the speed at which the 8080A is to be run at.
Basically, the oscillator operates at 9 times the desired pro·
cessor speed.

Several other signals are also generated internally so that
optimum timing of the auxiliary flip-flops and status strobe
(STSTB) is achieved.

A simple formula to guide the crystal selection is:
Crystal Frequency

1 times
.
9
tCY

= --

Example 1:

(500ns tCY)
2mHz times 9

Example 2:

(800ns tCY)
1.25mHz times 9 = 11.25mHz

=

18mHz*

Another input to the oscillator is TANK. This input allows
the use overtone mode crystals. Th is type of crystal gen·
erally has much lower "gain" than the fundamental type so
an external LC network is necessary to provide the additional
"gain" for proper oscillator operation. The external LC net·
work is connected to the TANK input and is AC coupled to
ground. See Figure 4.
The formula for the LC network is:
F=_1_ _

211 v'LC
The output of the oscillator is buffered and brought out
on E)SC (pin 12) so that other system timing signals can be
derived from this stable, crystal·controlled source.

1 UNIT = - - - ' OSC.
FREQ.

*When using crystals above 10mHz a small amount of frequency
"trimming" may be necessary to produce the exact desired fre-

I

I

i

I

1 1 2 I

3 I

I

quency. The addition of a small selected capacitance 13pF . 10pF)

0, ____..

in series with the crystal will accomplish this function.

I

I

EXAMPLE: (8080 tCY '" 500nsl

ase

= 18mHz/55ns
'" 110m (2 x 55nsl
'" 275n5 (5 x 55ns)
'" 110n5 (2 x 55n5)

Clock Generator
The Clock Generator consists of a synchronous "divide by
nine" counter and the associated decode gating to create the
waveforms of the two 8080A clocks and auxiliary timing
signals.
6-21

I

I
4 I 5

I

II
1 121

~

......I

~-"-

8224
The READY input to the 8080A CPU has certain timing
specifications such as "set-up and hold" thus, an external
synchronizing flip-flop is required. The 8224 has this feature
built-in. The ROYIN input presents the asynchronous "wait
request" to the "0" type flip-flop. By clocking the flip-flop
with ct>20, a synchronized READY signal at the correct input level, can be connected directly to the 8080A.

STSTB (Status Strobel
At the beginning of each machine cycle the 8080A CPU issues status information on its data bus. This information
tells what type of action will take place during that machine
cycle. By bringing in the SYNC signal from the CPU, and
gating it with an internal timing signal (ct>lA), an active low
strobe can be derived that occurs at the start of each machine cycle at the earliest possible moment that status data
is stable on the bus. The STSTB signal connects directly to
the 8228 System Controller.

The reason for requiring an external flip-flop to synchronize the "wait request" rather than internally in the 8080
CPU is that due to the relatively long delays of MOS logic
such an implementation would "rob" the designer of about
200ns during the time his logic is determining if a "wait"
is necessary. An external bipolar circuit built into the clock
generator eliminates most of this delay and has no effect on
component count.

The power-on Reset also generates STSTB. but of cou rse,
for a longer period of time. This feature allows the 8228 to
be automatically reset without additional pins devoted for
this function.

Power-On Reset and Ready Flip-Flops
A common function in 8080A Microcomputer systems is the
generation of an automatic system reset and start-up upon
initial power-on. The 8224 has a built in feature to accomplish this featu reo
An external RC network is connected to the R ESI N input.
The slow transition of the power supply rise is sensed by an
internal Schmitt Trigger. This circuit converts the slow transition into a clean, fast edge when its input level reaches a
predetermined value. The output of the Schmitt Trigger is
connected to a "0" type flip-flop that is clocked with ct>20
(an internal timing signal). The flip-flop is synchronously
reset and an active high level that complies with the 8080A
input spec is generated. For manual switch type system Reset circuits, an active low switch closing can be connected
to the R ESI N input in addition to the power·on RC netnetwork.

I
I
I
I
I

---1--~
F=~1_
21T

.JLC

IDhr-±-"1

USED ONLY
FOR OVERTONE
CRYSTALS

I

L _

3. 10 PF

I (ONLY NEEDED

_...J ABOVE 10 MHzl

13
11

osc

12
10

STSTB (TO 8228 PIN 1)

6-22

8224

D.C. Characteristics
TA = O°C to 70°C; vee = +5.0V ±5%; voo = +12V ±5%.

Symbol
IF

Parameter

Min.

Limits
Typ.

Input Current Loading

Max.

Units

-.25

mA

V F = .45V
V R = 5.25V

Test Conditions

IR

I nput Leakage Current

10

J.1A

Ve

Input Forward Clamp Voltage

1.0

V

Ie = -5mA

VIL

Input "Low" Voltage

.8

V

Vee = 5.0V

V 1H

Input "High" Voltage

2.6
2.0

V

Reset Input
All Other Inputs

V1WV1L

R EDIN Input Hysteresis

.25

VOL

Output "Low" Voltage

VOH

mV
.45

V

.45

V

Vee = 5.0V
(h2

¢2 Pulse Width

5tcy _ 35ns

t01

¢1 to ¢2 Delay

0

t02

¢2 to ¢1 Delay

2tcy _ 14ns

t03

¢1 to ¢2 Delay

tR

¢1 and ¢2 Rise Time

tF

¢1 and ¢2 Fall Time

to2

¢2 to ¢2 (TTL) Delay

toss

tpw

Max.

9
9
ns
CL = 20pF to 50pF

9
2tcy

2tcy + 20ns

9

9
20
20

-5

+15

¢2 to STSTB Delay

6tcy _ 30ns

6tcy

STSTB Pulse Width

tcy _ 15ns

tORS

RDYIN Setup Time to
Status Strobe

tORH

RDYIN Hold Time
After STSTB

tOR

RDYIN or RESIN to
¢2 Delay

tCLK

ClK Period

f max

Maximum Oscillating
Frequency

Cin

Input Capacitance

Test
Conditions

Units

9

ns

¢2TTl,Cl=30
R 1=300n
R 2=600n

9
STSTB,Cl=15pF

9

R, = 2K
R2 = 4K

50ns _ 4tcy

9
4tcy

9
Ready & Reset
Cl=10pF
R,=2K
R 2=4K

4tcy _ 25ns

9

tcy

9
MHz

18.432
8

pF

Vcc=+5.0V
Voo=+12V
VBIAS=2.5V
f=1MHz

TEST
CIRCUIT

INPUT

>---+----_O

GND

6-24

8224
WAVEFORMS

.,
1~~~~-'¢2-~~~"

--to2-~--

SYNC
(FROM 8080AI

STSTB

ROYIN OR RESIN

- - - - - - - - - - - - - - - - - - - '\-r-----f-------------------------Jr- - - - - - - - - - - - - - - - - - - - - - - - - - - -

READY OUT

_ _ _ I~-tDR---

RESETQUT

\

VOLTAGE MEASUREMENT POINTS: 'h. 1>2 Logic "0"

~

1.0V. Logic "1" ~ 8.0V. All other signals measured at 1.5V.

EXAMPLE:

A.C. Characteristics

(For tCY = 488.28 ns)

TA = O°C to 70°C; Vcc = +5V ± 5%; Voo = +12V ± 5%

Symbol
11

Parameter
<1>1 Pulse Width

Limits
Typ.

Min.

Max.

89

Units
ns
ns

I

Test Conditions
tCy=488.28ns

ns
t02

Delay <1>2 to <1>1

95

t03

Delay <1>1 to <1>2 Leading Edges

109

ns

~----~-+------~---------------+------+-----~--------=-=-~~f----

129

ns

Output Rise Time

20

ns

Output Fall Time

20

ns

326

ns

toss

<1>2 to STSTB Delay

t01>2

<1>2 to <1>2 (TTL) Delay

296

r--

<1>1 & <1>2 Loaded to

C L = 20 to 50pF

-~---r~~~+---~~

-5

+15

~~~--__j--------------- C----_~_ _

tpw

Status Strobe Pulse Width

tORS

RDYINSetupTimetoSTSTB

ns

------t-----j

40

ns

-167

ns

-----+-----------===~-r---~---~--------

tORH

RDYIN Hold Time after STSTB

217

ns

tOR

READY or RESET
to <1>2 Delay

192

ns

Oscillator Frequency

18.432

6-25

MHz

Ready & Reset Loaded
to 2mA/10pF
All measurements
referenced to 1.5V
unless specified
otherwise.

inter
M8224
CLOCK GENERATOR AND DRIVER
FOR 8080A CPU

•

Output for External System
• Oscillator
Timing
Controlled for Stable System
• Crystal
Operation
• Reduces System Package Count
• ±10% Power Supply Tolerance

Chip Clock Generator/Driver
• Single
for M8080A CPU
Power-Up Reset for CPU
• Ready
Synchronizing Flip-Flop
• Advanced
Strobe
• Full MilitaryStatus
Temperature
Range
• -55°C to +125°C

The M8224 is a single chip clock generator/driver for the M8080A cpu. It is controlled by a crystal, selected by the designer, to meet a variety of system speed requirements.
Also included are circuits to provide power-up reset, advance status strobe and synchronization of ready.
The M8224 provides the designer with a significant reduction of packages used to generate clocks and timing
for M8080A.

PIN CONFIGURATION

RESET

M8224 BLOCK DIAGRAM

Vee

Ii]>

XTAL 1

[4>

XTAL2

I!D

TANK

~----t~--DSC

-1;>---0,

XTAL 1

ADYIN

READY

TANK

.,

STSTB

¢,

GND

ID>

XTAL 2

¢2 (TTL)

SYNC

@>

OSC

----+---1._

[>

SYNC

IT>

RESIN

[D

RDYIN----H

VDD

I--*---RESET

[i>

1 - - - - - READY

r±>

PIN NAMES
'REsIN HESET INPUT__
I
RESET_
RESETJ?UTPU~
RDYIN

READY INPUT

CONNECT'ON-s---~---l

="'-"---t-'--

~-_~~~~J~f=l

I STSTB

_ I

9,

STATUS STB
(ACTIVE LOW)

~

,

ra080

¢2~ CLOCKS

6-26

FOR CRYSTAL

- - ------

M8224
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ... ,
Storage Temperature
Supply Voltage, Vee .....•
Supply Voltage, Voo . . . . . .
Input Voltage. . . . . . . . . . .
Output Current. . . . . . . . . •

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

. . . . ..
_.
•.
. .
. .

.
.
.
.

.
.
.
.

_55°C to 125°C
_65° C to 150° C
. ..
-0.5V to +7V
.. -0.5V to +13.5V
. ..
-1.0V to +7V
. . . . . . .. 100mA

D.C. CHARACTERISTICS
TA = -55°C to 125°C; Vee = +5.0V ±10%;Voo = +12V ±10%.
Limits
Typ.

Max.

Units

IF

I nput Current Load ing

-.25

mA

VF = .45V

10

f.1A

VR = 5.5V

Symbol

Parameter

Min.

IR

I nput Leakage Current

Ve

Input Forward C'",lnp Voltage

VIL

Input "Low" Voltage

V1H

Input "High" Voltage
RESIN
All Other Inputs

2.6
2.0

V1WV1L

R ESI N Input Hysteresis

.25

VOL

Output "Low" Voltage

VOH

Output "High" Voltage

IOS[11

9.0
3.3
2.4

Output Short Circuit Current
(All Low Voltage Outputs Only)

-10

-1.2

V

Ie = -5mA

.8

V

Vee = 5.0V

V

OSC,
2 (TTL)
A II Other 0 utputs

1 ' 2
READY, RESET
OSC, 2 (TTL), STSTB

Test Conditions

V

Vee = 5.0V

.45

V

10L = 10mA

.45

V

10L = 2.5mA

V
V
V
-60

mA

lee

Power Supply Current

115

mA

100

Power Supply Current

12

mA

Note: 1. Caution, q)1 and <1>2 output drivers do not have short circuit protection

CRYSTAL REQUIREMENTS
Tolerance: .005% at -55°C to 125°C
Resonance: Series (Fundamental)'
Load Capacitance: 20-35pF
Equivalent Resistance: 75-20 ohms
Power Dissipation (Min): 4mW
*With tank circuit use 3rd overtone mode.

6-27

10H = -100f.1A
10H = -100f.1A
10H = -lmA
Vo =OV
Vee = 5.0V

M8224

A.C. CHARACTERISTICS
vee = +5.0 ±10%; Voo = +12.0V ±10%; TA = -55°C to +125°C
Symbol

Parameter

tq,1

<1>1 Pulse Width

2tcy _ 20ns
9

t2 Pulse Width

5tey _ 45ns
9

t01

<1>1 to <1>2 Delay

0

t02

<1>2 to

t03

<1>1 to <1>2 Delay

tR

<1>1 and <1>2 Rise Time

tF

<1>1 and <1>2 Fall Time

to2 to <1>2 (TTL) Delay

 1

Delay

Limits
Typ.

Min.

Max.

Test
Conditions

Units

ns

2tey _ 25ns
9

CL = 20pF to 50pF

2tcy
9

2tcy + 40ns
9
25
25

-5

+15

ns

<1>2TTl,Cl= 30pF
R1~300n

R 2=600n
toss

<1>2 to STSTB Delay

6tcy _ 30ns
9

tpw

STSTB Pulse Width

tcy _ 23ns
9

tORS

RDYIN Setup Time to
Status Strobe

50ns _ 4tcy
9

tORH

RDYIN Hold Time
After STSTB

tOR

READY or RESET to
<1>2 Delay

6tey
9
STSTB,Cl=15pF
R1 ~ 2K
R2 = 4K

4tey
9
4tcy _ 25ns
9

Cl~10pF

R1~2K

R2=4K
tCLK

ClK Period

f max

Maximum Oscillating
Frequency

Cin

Input Capacitance

tey
9
MHz

18.432

pF

8

Vcc=+5.0V
Voo=+12V
VSIAs=2.5V
f=l MHz

Vee
TEST
CIRCUIT

R,

INPUT
CL

IGND

6-28

R,
GND

M8224
WAVEFORMS
~--------------------------~v---------------------------I
'F

~j
:~ID3_.f-

I

SYNC
(FROM B080A I

~t-~-

I"

l..------ t o

t

<,12

.. ,.~- t02

~--.--_

-

o,o2 ---.-...

t

f-'j-

-

-tpw~

""".o.~~,:3? '". ~~--------1------~------Ipw

t ass -

0

"3 ------------ -*-i'--'DR---~+-I- - - - - ------------------->r
Jt _______ ;I___________________ .

READVOUT

_~-

RESET OUT

VOLTAGE MEASUREMENT POINTS: 1>1,<1>2 Logic "0"
All other signals measured at 1.5V.

~

t OR _ _ _ _ _ !

*---------------------

1.0V, Logic "1"

~

7.0V. REAOY, RESET Logic "0"

~

0.8V, Logic "1"

~

3.0V.

Example:
A.C. CHARACTERISTICS (For tCY = 488.28 ns.)
TA = -55°C to 125°C; Voo = +5V ±10%; Voo = +12V ±10%.
Symbol

Parameter

Min.

Limits
Typ.

Max.

Units

11

2

2



'"

,,~

"'~

t;

.$>~

'<

""
I:>~$
X'"
~

,,'>f

~

~
~

CD ® ®
Do
D1
D2

INTA
WO

D3

STACK
HLTA

D4

OUT

D5
D6

M1
INP

D7

MEMR

0
1
0
0
0
1
0
1

""

~

~

~ - _
~

VOLTAGE MEASUREMENT POINTS: 00-07 (when outputs) Logic "0"
at 1.5V.
'Advanced IOW/MEMW for M8238 only.

6-41

=

- _ - _ - _ - _ - _ - __

0.8V, Logic "1"

=

3.0V. All other signals measured

M8228/M8238

WR

18

DBIN ~'u.7~_ _ _~

HDLAt2~'~---;J1__~__~

DB,
_DBO}
_DB

M8080A
CPU

_ 0 82

_

DB:

DATA BUS

_OBs
_ D 86
_DB 7

INTA}
MEM A

M.~~W

(FROM 8224) STATUS STROBE

CONTROL BUS

I/O R
I/ow

M8080A CPU Interface

TYPE OF MACHINE CYCLE

I

STATUS WORD

(j)
0,

WO

02
03

STACK
HLTA

0
0
0
0

D.

OUT

-'22~

INTA

05

M,

06

INP

07

MEMR

® ®
1

0

1

1

0

1

0
0
0

0
-0
0

0
0

1

1

0
0
0
1

--.-

INTA
(NONE)

I
~~

-.---

INTA

I/OW

170
R
--MEMW
---

MEM R

---

MEMW
MEM R
---

MEM R

Status Word Chart

6-42

r--

CONTROL
SIGNALS

8085
SINGLE CHIP 8-BIT N-CHANNEL MICROPROCESSOR

• Single +5V Power Supply
• 100% Software Compatible with 8080A
• 1.3 IJs Instruction Cycle
On-Chip Clock Generator (with External
• Crystal
or RC Network)

Vectored Interrupts (One is non• Four
Maskable)

• Serial In/Serial Out Port

Decimal, Binary and Double Precision
• Arithmetic
Addressing Capability to 64K
• Direct
Bytes of Memory

• On-Chip System Controller

The Intel® 8085 is a new generation, complete 8 bit parallel central processing unit (CPU). Its instruction set is 100% software compatible with the 8080A microprocessor, and it is designed to improve the present 8080's performance by higher
system speed. Its high level of system integration allows a minimum system of three IC's: 8085 (CPU), 8156 (RAM) and
8355/8755 (ROM/PROM).
The 8085 incorporates all of the features that the 8224 (clock generator) and 8228 (system controller) provided forthe 8080,
thereby offering a high level of system integration.
The 8085 uses a multiplexed Data Bus. The address is split between the 8 bit address bus and the 8 bit data bus. The onchip address latches of 8155/8355/8755 memory products allows a direct interface with 8085.

8085 CPU FUNCTIONAL
BLOCK DIAGRAM
INTA

RST6.5

TRAP

C

lSi

REG.

,.,
I.,

B
REG.
INSTRUCTION

DECODER
AND
MACHINE
CYCLE

ENCODING

D
REG.
H
REG.

lSi

E

I.,

REG.
L
REG.

STACK POINTER

REGISTER
ARRAY

(161
U6)

PROGRAM COUNTER

POWER {_+5V
SUPPLY

_GND

TIMING AND CONTROL

X,

x,

6-43

A15-Aa

ADJ-ADo

ADDRESS BUS

ADOR ESS/DAT A BUS

8085
8085 FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
As-A15 (Output 3-Slate)
Address Bus; The most significant 8-bits of the memory
address or the 8-bits of the I/O address,3-stated during
Hold and Halt modes.

Xl

Vee

x2

HOLD

RESET OUT
SOD
SID
TRAP

ADo_7 (Input/Output 3-state)

RST 7.5

Multiplexed Address/Data Bus; Lower 8-bits of the
memory address (or I/O address) appear on the bus
during the first clock cycle of a machine state. It then
becomes the data bus during the second and third clock
cycles.

HLDA

ClK

READY

101M

RST 6.5

SI

RST 5.5

RD

3-stated during Hold and Halt modes.
ALE (Output 3-state)
Address Latch Enable: It occurs during the first clock cycle of
a machine state and enables the address to get latched into
the on-chip latch of peripherals. The falling edge of ALE is set
to guarantee setup and hold times forthe address information.
ALE can also be used to strobe the status information. 3stated during Hold and Halt modes.

INTR

WR

INTA

ALE

ADo
ADI

So
A IS

AD2

A14

AD3

A 13

AD4

A12

ADs

A11
A l0

AD6
AD7

Ag

Vss

A8

So, S1 (Output)

(ouT)

RESET IN

Data Bus Status. Encoded status of the bus cycle:
51

50

0
0

0
1

0
1

Figure 1. 8085 PINOUT DIAGRAM

HALT
WRITE
READ
FETCH

S1 can be used as an advanced

buses in the next clock cycle. HLDA goes low after the
Hold request is removed. The CPU takes the buses one
half clock cycle after HLDA goes low.

Riw status.

RD (Output 3-slate)

INTR (Input)

READ; indicates the selected memory or I/O device is to be
read and that the Data Bus is available for the data transfer.
Tri-stated during Hold and Halt.

WRITE; indicates the data on the Data Bus is to be written
into the selecte'd memory or I/O location. Data is set up at
the trailing edge of WR. Tri-stated during Hold and Halt
modes.

INTERRUPT REQUEST; is used as a general purpose
interrupt. It is sampled only during the last clock cycle of
the instruction. If it is active, the Program Counter (PC)
will be inhibited from incrementing and an INTA will be
issued. During this cycle a RESTART or CALL instruction
can be inserted to jump to the interrupt service routine.
The INTR is enabled and disabled by software. It is
disabled by Reset and immediately after an interrupt is
accepted.

READY (Input)

INTA (Output)

If Ready is high during a read or write cycle, it indicates
that the memory or peripheral is ready to send or receive
data. If Ready is low, the CPU will wait for Ready to go high
before completing the read or write cycle.

INTERRUPT ACKNOWLEDGE; is used instead of (and
has the same timing as) RD during the Instruction cycle
after an INTR is accepted. It can be used to activate the
8259 Interrupt chip or some other interrupt port.

WR (Output 3-state)

HOLD (Input)
R5T 5.5
R5T 6.5
R5T 7.5

HOLD; indicatE;ls that another Master is requesting the use
of the Address and Data Buses. The CPU, upon receiving
the Hold request. will relinquish the use of buses as soon
as the completion of the current machine cycle. Internal
processing can continue. The processor can regain the
buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, 10iM, and
ALE lines are tri-stated.

}
(Inputs)

RESTART INTERRUPTS; These three inputs have the
same timing as INTR except they cause an internal
RESTART to be automatically inserted.
RST 7.5
RST 6.5
RST 5.5

HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has
received the Hold request and that it will relinquish the:

~

Highest Priority

~

Lowest Priority

1 he priority of these interrupts is ordered as shown above.
Tnese interrupts have a higher priority than the INTR.

6-44

8085
The 8085 provides RD, WR, and 10/Memory signals for
bus control. An Interrupt Acknowledge signal (INTA) is
also provided. Hold, Ready, and all Interrupts are
synchronized. The 8085 also provides serial input data
(SID) and serial output data (SOD) lines for simple serial
interface.

TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is
recognized at the same time as INTR. It is unaffected by
any mask or Interrupt Enable. It has the highest priority of
any interrupt.
RESET IN (Input)

I n addition to these features, the 8085 has three maskable,
restart interrupts and one nonmaskable trap interrupt.

Reset sets the Program Counter to zero and resets the
Interrupt Enable and HLDA flip-flops. None of the other
flags or registers (except the instruction register) are
affected. The CPU is held in the reset condition as long as
Reset is applied.

8085 vs. 8080
The 8085 includes the following features on-chip in
addition to all of the 8080 functions.
a. Internal clock generator
b. Clock output
c. Fully synchronized Ready
d. Schmitt action on RESET IN
e. RESET OUT pin
f. RlJ, WR, and 10/M Bus Control Signals
g. Encoded Status information
h. Multiplexed Address and Data
i. Direct Restarts and nonmaskable Interrupt
j. Serial Input/Output lines.

RESET OUT (Output)
Indicates CPU is being reset. Can be used as a system
RESET. The signal is synchronized to the processor clock.
X1, X2 (Input)
Crystal or R/C network connections to set the internal
clock generator. X1 can also be an external clock input
instead of a crystal.
elK (Output)

Clock Output for use as a system clock when a crystal or
R/C network is used as an input to the CPU.

The internal clock generator requires an external crystal
or R-C network. It will oscillate at twice the basic CPU
operating frequency. A 50% duty cycle, two phase,
nonoverlapping clock is generated from this oscillator
internally and one phase ofthe clock (4)2) is available as an
external clock. The 8085 directly provides the external
ROY synchronization previously provided by the 8224.
The RESET IN input is provided with a Schmitt action
input so that power-on reset only requires a resistor and
capacitor. RESET OUT is provided for System RESET.

101M (Output)
10/M indicates whether the Read/Write is to memory or
I/O. Tri-stated during Hold and Halt modes.
SID (Input)
Serial input data line. The data on this line is loaded into
accumulator bit 7 whenever a RIM instruction is executed.
SOD (output)

The 8085 provides RD, WR and 10/M signals for Bus
control. An INTA which was previously provided by the
8228 in 8080 system is also included in 8085.

Serial output data line. The output SOD is set or reset as
specified by the SIM instruction.

Vee

STATUS INFORMATION

+5 volt supply.

Status information is directly available from the 8085. ALE
serves as a status strobe. The status is partially encoded,
and provides the user with advanced timing of the type of
bus transfer being done. 10/M cycle status signal is
provided directly also. Decoded So' S1 carries the
following status information:

Vss
Ground Reference.

FUNCTIONAL DESCRIPTION
The 8085 is a complete 8bit parallel central processor. It is
designed with N-channel depletion loads and requires a
single +5 volt supply. Its basic clock speed is 3 MHz thus
improving on the present 8080's performance with higher
system speed. Also it is designed to fit into a minimum
system of three IC's: The CPU, a RAM/IO, and a ROM or
PROM/IO chip.

~

...!2..

HALT

0

0

WRITE

0

READ

1

0

FETCH
S1 can be interpreted as R/Vii in all bus transfers.

The 8085 uses a multiplexed Data Bus. The address is split
between the higher 8-bit Address Bus and the lower B-bit
Address/Data Bus. During the first cycle the address is
sent out. The lower 8-bits are latched into the peripherals
by the Address Latch Enable (ALE). During the rest of the
machine cycle the Data Bus is used for memory or I/O
data.

In the 8085 the 8 LSB of address are multiplexed with the
data instead of status. The ALE line is used as a strobe to
enter the lower half of the address into the memory or
peripheral address latch. This also frees extra pins for
expanded interrupt capability.

6-45

r

8085
INTERRUPT AND SERIAL I/O
The 8085 has 5 interrupt inputs: INTR, RST 5.5, RST 6.5,
RST 7.5, and TRAP. INTR is identical in function to the
8080 INT. Each of three RESTART inputs, 5.5, 6.5, 7.5, has
a programmable mask. TRAP is also a RESTART interrupt
except it is non-maskable.

For RST 7.5, only a pulse is required to set an internal flip
flop which generates the internal interrupt request. The
RST 7.5 request flip flop remains set until the request is
serviced. Then it is reset automatically. This flip flop may
also be reset by using the SIM instruction or by issuing a
RESET IN to the 8085. The RST 7.5 internal flip flop will be
set by a pulse on the RST 7.5 pin even when the RST 7.5
interrupt is masked out.

The three RESTART interrupts cause the internal
execution of RST (saving the program counter in the
stack and branching to the RESTART address) if the
interrupts are enabled and if the interrupt mask is not set.
The nonmaskable TRAP causes the internal execution of
a RST independent of the state of the interrupt enable or
masks.
Name

RESTART Address (Hex)

TRAP
RST 5.5
RST 6.5
RST 7.5

24 16
2C 16
34 16
3C16

The status of the three RST interrupt masks can only be
affected by the SIM instruction and RESET IN.
The interrupts are arranged in a fixed priority that
determines which interrupt is to be recognized if more
than one is pending as follows: TRAP - highest priority,
RST 7.5, RST 6.5, RST 5.5, INTR - lowest priority. This
priority scheme does not take into account the priority of a
routine that was started by a higher priority interrupt. RST
5.5 can interrupt a RST 7.5 routine if the interrupts were reenabled before the end of the RST 7.5 routine.
The TRAP interrupt is useful for catastrophic errors such as
power failure or bus error. The TRAP input is recognized
just as any other interrupt but has the highest priority. It is
not affected by any flag or mask. The TRAP input is both
edge and level sensitive. The TRAP input must go high and

There are two different types of inputs in the restart
interrupts. RST 5.5 and RST 6.5 are high level-sensitive
like INTR (and INT on the 8080) and are recognized with
the same timing as INTR. RST 7.5 is rising edge-sensitive.

M,
ClK

As-A,S

M,

M,

T,

PC H (HIGH ORDER ADDRESS)

(PC+ 1)H

A°0-7

ALE

RD

ViR

10iM

STATUS

8,

So (FETCH)

10 (READ)

FIGURE 2. 8085 BASIC SYSTEM TIMING.
6-46

01 WRITE

11

8085
remain high to be acknowledged, but will not be
recognized again until it goes low, then high again. This
avoids any false triggering due to noise or logic glitches.
The following diagram illustrates the TRAP interrupt
request circuitry within the 8085.
INSIDE THE

EXTERNAL
TRAP
INTERRUPT
REQUEST

8085

In addition to standard I/O, the memory mapped I/O offers
an efficient I/O addressing technique. With this technique,
an area of memory address space is assigned for I/O
address, thereby, using the memory address for I/O
manipulation. Figure 4 shows the system configuration of
Memory Mapped I/O using 8085.
The 8085 CPU can also interface with the standard
memory that does not have the multiplexed address/data
bus. It will require a simple 8212 (8-bit latch) as shown in
Figure 5 ..

TRAP

SCHMITT

TRIGGER
RESET

+5V

0 eLK

o

r1D~x I l l
x,
Vss Vee

FIF

--

---

INTERNAL
TRAP
ACKNOWLEDGE

Note that the servicing of any interrupt (TRAP, RST 7.5,
RST 6.5, RST 5.5, INTR) disables all future interrupts
(except TRAPs) until an EI instruction is executed.

TRAP

2

HOLD
HLDA

RST6,5

8085

RST5,5

1NfA
ADOR

S,I--

RESET

ADDR/

Sol--

OUT

DATA ALE AD WR 101M

AOYelK

T

(8)

[H-

eE

Vr

PORr¢V

WR
PORT ¢ V

. RD 8156

The serial I/O system is also controlled by the RIM and
SIM instructions. SID is read by RIM, and SIM sets the
SOD data.

B

ALE
PORT
DATAl
e
ADDR

.A

Y

101M

BASIC SYSTEM TIMING

RESET

The 8085 has a multiplexed Data Bus. ALE is used as a
strobe to sample the lower 8-bits of address on the Data
Bus. Figure 2 shows an instruction fetch, memory read
and I/O write cycle (OUT). Note that during the I/O write
and read cycle that the I/O port address is copied on both
the upper and lower half of the address.

~
(6)

IN~

TIMER

OUT

I--

lOW·

RD
ALE

It-I-

...

l~

As in the 8080, the READY line is used to extend the read
and write pulse lengths so that the 8085 can be used with
slow memory. Hold causes the CPU to relinguish the bus
when it is through with it by floating the Address and Data
Buses.

V

eE

PORT
A

A8-10

fN

835518155
DATAl
ADDR

101M
RESET

SYSTEM INTERFACE

~

8085 family includes memory components, which are
directly compatible to the 8085 CPU. For example, a
system conSisting of the three chips, 8085, 8156, and 8355
will have the following features:
• 2K Bytes ROM
• 256 Bytes RAM
• 1 Timer/Counter
• 4 8-bit I/O Ports
• 1 6-bit I/O Port
• 4 I nterru pt Levels
• Serial In/Serial Out Ports
This minimum system, using the standard I/O technique is
as shown in Figure 3.

~

r-

SOD I-SID ~

INTR

(8)

Since a TRAP interrupt can occur and disable the other
interrupts whether they were previously enabled or not, it
is not possible to restore the previous interrupt enable
status following a TRAP.

RESET IN

RST7,5

r-

PORT
B

ROY

fN

~ elK

VLUJROG
Vr;c

FIGURE 3. 8085 MINIMUM SYSTEM (STANDARD
110 TECHNIQUE)

6-47

8085
8086 MINIMUM SYSTEM CONFIGURATION
j..

A8-15

~

A
ADO·7

,.

~

ALE
8085

I!i5

V

-

11m
101M
CLK

r--

RESET OUT

r-r--

READY

Vee
TIMER

WARD

IN

RESET

ALE CE,

AD _

:~~,

101M

0-7 CE Ig' ALE

;;;;,m; CLK ~S

T:'~~R_
8355 [ROM

8156
IRAM, I/O, COUNTERITIMER}

OR
8756 (PROM

E E8

----

j
X,

X,

I j
RESET IN
HOLD

HLDA

SOD
SID

RST 6.5

8085

R8T5.5

-

II-

INTR

S'r-

iN'fA

SolOUT
ADORI
DATA ALE RD WR 101M
RDYCLK

RESET

ADDR

18}

181
101M ICS}

WR
8212

t-

RD

.

DATA

t..

I

STANDARD
MEMORY
ADDR leS)

y

1161

---

CLK
RESET
101M ICS}

~.

WR

r/o PORTS,
CONTROLS

;;;;
DATA
STANDARD

I/O

I

0DIIIII

y

FIGURE 5. MCS-8S'· SYSTEM (USING STANDARD MEMORIES)

6·48

+ I/O]

88

FIGURE 4. MCS-aS'· MINIMUM SYSTEM (MEMORY MAPPED I/O)

TRAP
RST7.5

+ I/O J

ADDR
ICS,CIO}

Vee

ROY

8085
DRIVING THE Xl AND X2 INPUTS

+5V

The user may drive the Xl and X2 inputs of the 8085 with a
crystal, an external clock source or an RC network as
shown below:

47011
TO

lK11
. . . - - -_ _- - - - - i

10-------<1-----1 Xl

x,

PARALLEL RESONANT
CRYSTAL (30P! LOADING)

20p!

*

I

1·6 MHz
INPUT FREQUENCY
(DUTY CYCLE AT 6MHz: 25 - 50%)
*WITH AN EXTERNAL CLOCK SOURCE
X2 SHOULD BE LEFT FLOATING.

1·6 MHz
INPUT FREQUENCY

+5V
, - - - -_ _- - - 1

x,

,.,lOK

10---+------1 Xl
2

47011

1'1::3 MHz
INPUT FREQUENCY

-6 MHz
INPUT FREQUENCY

RC Mode causes a large drift in clock frequency because
of the variation in on-chip timing generation parameters.
Use of RC Mode should be limited to an application, which
can tolerate a wide frequency variation.

This circuit may be used when the clock input has> 50%
duty cycle at 6MHz.

FIGURE 6. DRIVING THE CLOCK INPUTS (X1 AND X2) OF 8085

GENERATING 8085 WAIT STATE
The following circuit may be used to insert one WAIT state
in each 8085 machine cycle.
ALE

The 0 flip flops should be chosen such that
• ClK is rising edge triggered
• CLEAR is low-level active.

-

+5V ....... 0

FIGURE 7. GENERATION OF A WAIT STATE FOR 8085 CPU

6-49

+

81185
ClKOUTPUT_ ClK

CLEAR
ClK

"0"

"0"

F/F

F/F

Q

0

-

Q

TO 81185
RE AOY
INP UT

1--"'-

8085
ABSOLUTE MAXIMUM RATINGS·
device. This is a stress rating only and functional 0
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Ambient Temperature Under Bias......... O°C to 70°C
Storage Temperature . . . . . . . . . . . . . ._65°C to +150°C
Voltage on Any Pin
With Respect to Ground. . . . . . . . . . .. -0.3 to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . 1.5 Watt

D.C. CHARACTERISTICS
= ooc to 70°C; Vcc = 5V ±5%; VSS = OV; unless otherwise specified)

(TA

Symbol

Min.

Max.

Units

V IL

Input Low Voltage

Parameter

-0.5

+0.8

V

VIH

Input High Voltage

2.0

Vcc+0.5

V
V

IOL

V

IOH

= 2mA
= -400pA

J.iA

Yin

= VCC

pA

0.45V 0;;; V out 0;;; VCC

VOL

Output Low Voltage

VOH

Output High Voltage

Icc

Power Supply Current

170

mA

IlL

Input Leakage

±10

ILO

Output Leakage

±10

0.45
2.4

V ILR

Input Low Level, RESET

-0.5

+0.8

V

VIHR

Input High Level, RESET

2.4

Vcc +O·5

V

V Hy

Hysteresis, RESET

0.25

V

Bus Timing Specification as a TcyC Dependent
tAL

-

(1/2) T - 50

MIN

tLA

-

(1/2) T - 60

MIN

tLL
t LCK

-

(1/2) T - 40

MIN

-

(1/2)T - 60

MIN

t LC

-

(1/2) T - 30

MIN

-

(5/2 + N) T - 225

MAX

-

(3/2 + N) T - 200

MAX

(1/2) T - 60

MIN

(1/2) T - 40

MIN

(3/2 + N) T - 60

MIN

-

(1/2)T - 80

MIN

(3/2 + N) T - 80

MIN

(1/2)T-110

MIN

-

(3/2) T - 260

MAX

(1/2) T - 50

MIN

-

(1/2) T + 30

MAX

(1/2) T + 30

MAX

(2/2) T - 50

MIN

-

tAo
t RO
tRAE
tCA
tow

~
tcc

tCL
t ARy
t HACK
tHABF
tHABE
tAC
t,
t2
tRV

(1/2) T - 80

MIN

(1/2) T - 40

MIN

(3/2) T - 80

MIN

(1/2) T + 200

MIN

tiNS
NOTE: N is equal to the total WAIT states.
T=tCYC·
6·50

Test Conditions

8085

iII&
P&f::

,;,::!,

""fFI

A.C. CHARACTERISTICS

(TA = O°Cto 70°C; VCC = 5V ±5%; VSS = OV)

Parameter

Symbol

I.'

Min.

Max.

Units

2000

ns

TCYC

ClK Cycle Period

320

t1

ClK low Time

80

ns

t2

ClK High Time

120

ns
30

ClK Rise and Fall Time
Address Valid Before Trailing Edge of ALE

110

tLA

Address Hold Time After ALE

100

ns

tLL

ALE Width

120

ns

ns

t LCK

ALE low During ClK High

100

ns

t LC

Trailing Edge of ALE to leading Edge of
Control

130

ns

tAFR

Address Float After leading Edge of
READ (INTA)

tAo

Valid Address to Valid Data In
READ (or INTA) to Valid Data

t ROH

Data Hold Time After READ (lNTA)

See notes 1, 2, 3, 4,

ns

t r, t f
tAL

t RO

'Ir0i:~.

Test ConditilJli&!it

0

ns

575

ns

280

ns

0

ns

tRAE

Trailing Edge of READ to Re·Enabling
of Address

120

ns

tCA

Address (A8-A 15) Valid After Control

120

ns

tow

Data Valid to Trailing Edge of WR ITE

420

ns

two

Data Valid After Trailing Edge of WR ITE

80

ns

TCYC = 320ns;

tcc

Width of Control low (RD, WR, INTA)

400

ns

tCL

Trailing Edge of Control to leading Edge
of ALE

50

ns

t ARy

READY Valid From Address Valid

t RyS

READY Setup Time to leading Edge of ClK

t RYH

READY Hold Time

220

C L = 150 pF

ns

110

ns

0

ns
ns

t HACK

HlDA Valid to Trailing Edge of ClK

tHABF

Bus Float After HlDA

110

tRV

Control Trailing Edge to leading Edge of
Next Control

400

ns

tAC

Address Valid to Leading Edge of Control

270

ns

tHos

HOLD Setup Time to Trailing Edge of ClK

170

ns

t HOH

HOLD Hold Time

0

ns

tiNS

INTR Setup Time to leading Edge of ClK
(Ml, Tl only). Also RST and TRAP

360

ns

tlNH

INTR Hold Time

0

ns

190

ns

NOTES: 1. A8-15 Address Specs apply to 101M, so and 51.
2. For all output timing where CL "" 150pf use the following correction factors:
25pf .;; CL < 15Opf: -.10 ns/pf
150pf < CL .;; 300pf: +.30 ns/pf
3. Output timings are measured with purely capacitive load.
4. All timings are measured at output voltage VL = .SV. VH = 2.0V, and 1.5V with 20ns rise and fall time on inputs.
5. To calculate timing specifications at other values of TCYC use the table in Table 2.
6. L.E. = Leading Edge
T.E. = Trailing Edge

6-51

8085

t-o----tCYC

---->-I

FIGURE 8. CLOCK TIMING WAVEFORM

READ OPERATION

I

CLK\""_-JI
~'LCK

I

T2

)-1----..'L--..-...II

il

ADDRESS

)

ADDRESS

''-_-II

,'--_-I,

~----------~----~r_--'AD

t

f-'LL-

WI

I--'LAt AFR ......

ALE
f.-tAL_

'RO

I

'cc

~'LC_1\l.

RD/INTA

!------ 'AC_____.
J

tARY

t RVH

'RVS

I

\

READY

WRITE OPERATION

eLK\

I

->

r--

-

I

T2

)
tLCK

ADDRESS

,

r

,
1

I

T,

I

TWAIT

/

I

X
'0--- 'LA-----I !

'ow

L

'ce

ADDRESS
'LL -

ALE
_'AL-+

WR

~~
'AC

t RyS

tARV

READY

\

t RYH

1

FIGURE 9. 8085 BUS TIMING

6·52

,
I

T3

I

,
I

T,

J

8085
HOLD OPERATION

,

T,

:\

ClK

HOLD

I

t

T,

I

I

'HDS·

~tHDH

,

T HOLD

T,

~~

"\

t'HACK'"

t

HLDA

BUS

T HOLD

\

t HABF -

~tHABE-

~

(ADDRESS, CONTROLS)

FIGURE 10. 8085 HOLD TIMING

Aa-,.=t====:==l--------I
ALE

~,-t----------_t----~----------------~~.--~----------

HOLD

HlDA
.....CK

'lttABF

'101M IS ALSO FLDATING DURING THIS TIME

FIGURE 11. 8085 INTERRUPT AND HOLD TIMING

6-53

8085

8-BIT MICROPROCESSOR

6-54

EPROMs and ROMs

EPROMs and ROMs
8708 8192-Bit EPROM

_ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _ _ _ _ _ _ _ _ _ _ _ _

6-57

_________ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . .
2716 2048x8 EPROM
8308 8192-Bit MaS ROM . _ ............. _ .......... _ . . . . . . . . . . . . . . . .
8316A 16,384-Bit MaS RAM ..... _ . . . . . . . . . . . . . . . . . . . . . . . _ . . . . . .. . . . .
2316E 2048x8ROM . . . . . . . . . . . . . . . . . . . . . . . . _ .... _ .... ___ .... _ .....
PROM and ROM Programming Instructions

6-60
6-64
6-68
6-71
6-74

6·56

inter
8708
8192 BIT ERASABLE AND ELECTRICALLY
REPROGRAM MABLE READ ONLY MEMORY
1024x8 Organization
• Static-No Clocks Required
• Inputs and Outputs TTL
Compatible During Both Read
and Program Modes
• Three-State Output-OR-Tie
Capability

• Fast Programming Typ. 100 sec. For AII8K Bits
• Low Power During Programming
• Access Time - 450 ns
• Standard Power Supplies-

+12V, ±5V

The Intel® 8708 is a high speed 8192 bit erasable and electrically reprogrammable ROM (EPROM) ideally suited where
fast turn around and pattern experimentation are important requirements.
The 8708 is packaged in a 24 pin dual-in-line package with transparent lid. The transparent lid allows the user to expose the
chip to ultraviolet light to erase the bit pattern. A new pattern can then be written into the device.
A pin for pin mask programmed ROM, the Intel® 8308, is available for large volume production runs of systems initially
using the 8708.
The 8708 is fabricated with the time proven N-channel silicon gate technology.

PIN CONFIGURATION

BLOCK DIAGRAM
DATA OUTPUT

A,

Vee

A,

A,

A,

A,

A,

v"

A,

CSIWE
Cs'WE-

A,
A,

CHIP SELECT
LOGIC

OUTPUT BUFFERS

Y
DECODER

V GATING

X
DECODER

64 X 128
ROM ARRAY

PROGRAM

·0
0,

0,

0,

0,

0,

0,

I.!;s

0,

PIN NAMES
Ao-Ag
0, 'Os
CS/WE

Ao Ag
ADDRESS
INPUTS

PIN CONFIGURATION DURING READ OR PROGRAM
PIN NUMBER

ADDRESS INPUTS
DATA OUTPUTS
CHIP SELECT/WRITE ENABLE INPUT

MOOE

READ
PROGRAM

6-57

12

9-11,13-17
DOUT

D,N

I

Vss
Vss

1.

I

Vss
p~::

1.

IVoo I
Voo

20

VIL
VIHW

21

IV" I
VBa

2.
Vee
Vee

8708
PROGRAMMING
The programming specifications are identical to those of the 2708. (See ROM and PROM Programming Instructions,
page 6-74J.

ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias . . . . . . . . . . . . -25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +125°C
VDD With Respect to VBB . . . . . . . . . . . . +20V to -0.3V
Vee and Vss With Respect to VBB . . . . . . +15V to -0.3V
All Input or Output Voltages With
Respect to VBB During Read . . . . . . . . +15V to -0.3V
CSIWE Input With Respect to VBB
During Programming . . . . . . . . . . . . . +20V to -0.3V
Program Input With Respect to VBB . . . . . +35V to -0 3V
Power Dissipation. . . . . . . . . . . . . . . .
1.5W

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

READ OPERATION
D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70°C, Vee = +5V ±5%, VDD = +12V ±5%, VBB = -5V ±5%, Vss = OV, Unless Otherwise Noted.
Symbol

Parameter

Min.

TypJl]

Max.

Unit

Conditions

= 5.25 V or VIN = VIL

III

Address and Chip Select Input Sink Current

1

10

f.l.A

VIN

ILO

Output Leakage Current

1

10

f.l.A

VOUT = 5.25V, CS/WE = 5V

IDD[2]

VD D Supply Current

50

65

mA

Worst Case Supply Currents:

lee[2]

Vee Supply Current

6

10

mA

All Inputs High
CSIWE = 5V; TA = O°C

IBB[2]

VBB Supply Current

45

mA

VIL

Input Low Voltage

Vss

0.65

V

VIH

Input High Voltage

3.0

Vee+ 1

V

VOL

Output Low Voltage

0.45

V

IOL

VOH1

Output High Voltage

3.7

V

IOH = -100f.l.A

VOH2

Output High Voltage

2.4

PD

Power Dissipation

30

V
800

mW

= 1.6mA

IOH = -lmA
TA = 70°C

NOTES: 1. Typical values are for TA = 25° e and nominal supply voltages.
2. The total power dissipation of the 8708 is specified at 800 mW. It is not calculable by summing the various currents
UDD, ICC, and IBB) multiplied by their respective voltages since current paths exist between the various power supplies and
VSS. The IDD, ICC, and IBB currents should be used to determine power supply capacity only.

TYPICAL D.C. CHARACTERISTICS

8 JA

~ soocJ

Vee "'5.25V

Veo = 12.6V
Vss =-S.25V

100

~

~

~

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE

RANGE OF SUPPLY CURRENTS
VS. TEMPERATURE

MAXIMUM JUNCTION TEMPERATURE
VS. AMBIENT TEMPERATURE
150

ALL POSSIBLE OPERATING
CONDITIONS:
Vee "'S.25V

.....--

voo

= 12.6V

I ves= -5.25V
I

~

so - -

0

20

40

60

70

oe::~~
o
20

40

60

80

100
VOL (VOLTS)

6-58

8708
A.C. CHARACTERISTICS
TA ; DOC to 70°C, vee; +5V ±5%, Voo ; +12V ±5%, V BB ; -5V ±5%, vss; OV, Unless Otherwise Noted.
Typ.

Max.

Unit

tAee

Address to Output Delay

Parameter

280

450

ns

teo

Chip Select to Output Delay

60

120

ns

tOF

Chip De-Select to Output Float

0

120

ns

tOH

Address to Output Hold

0

Symbol

CAPACITANCE
Symbol

Min.

ns

TA ; 25°C, f; 1MHz

Parameter

Typ. Max. Unit Conditions

CIN

I nput Capacitance

4

6

pF

VIN;OV

COUT

Output Capacitance

8

12

pF

VOUT;OV

Note. This parameter is periodically sampled and not 100% tested.

A.C. TEST CONDITIONS
Output Load: 1 TTL gate and CL ; 100pF
Input Rise and Fall Times: ';;;20ns
Timing Measurement Reference Levels: 0.8V and 2.8V for inputs; 0.8V and 2.4V for outputs
Input Pulse Levels: 0.65V to 3.0V

WAVEFORMS

ADDRESS

--X-------X----

c.s.IWE

DATA
OUT

ERASURE CHARACTERISTICS
The erasure characteristics of the 8708 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
flourescent lighting could erase the typical 8708 in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If
the 8708 is to be exposed to these types of lighting
conditions for extended periods oftime, opaque labels are
available from Intel which should be placed over the 8708
window to prevent unintentional erasure.

The recommended erasure procedure (see page 3-55) for
the 8708 is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15W-sec/cm 2. The erasure time
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000iJW/cm2 power rating. The
8708 should be placed within one inch from the lamp tubes
during erasure. Some lamps have a filter on their tubes
and this filter should be removed before erasure.

6-59

2716
16K (2K X 8) UV ERASABLE PROM
• Single +5V Power Supply

• Pin Compatible To Intel 2316E ROM

• Simple Programming Requirements
Single Location Programming
Programs With One 50ms Pulse

• Fast Access Time:

• Low Power Dissipation
525mW Max. Active Power
132mW Max. Standby Power

450ns Max.

• Inputs and Outputs TTL
Compatible During Read
And Program

The Intel® 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2716
operates from a single 5-volt power supply, has a static power down mode, and features fast single address location programming. It makes designing with EPROMs faster, easier and more economical. For production quantities, the 2716 user can
convert rapidly to Intel's new pin-for-pin compatible 16K ROM, the 2316E.
Since the 450-nsec 2716 operates from a single 5-volt supply, it is ideal for use with the newer high performance +5V microprocessors such as Intel's 8085 and 8048. The 2716 is also the first EPROM with a static power down mode which reduces
the power dissipation without increasing access time. The maximum active power dissipation is 525 mW while the maximum
standby power dissipation is only 132 mW, a 75% savings.
The 2716 has the simplest and fastest method yet devised for programming EPROMs - single pulse TTL level programming.
No need for high voltage pulsing because all programming controls are handled by TTL signals. Now, it is possible to program
on-board, in the system, in the field. Program any location at any time - either individually, sequentially or at random, with
the 2716's single address location programming. Total programming time for all 16,384 bits is only 100 seconds.
MODE SELECTION

~

PIN CONFIGURATION

MODE

A7

Vee

Read

As

AS

Deselect

PO/PGM

es

(18)

1201

VPI'
1211

Vee
1241

OUTPUTS
(9-11,13-17)

V,L

VIL

+5

+5

DOUT

Don't Care

V ,H

+5

+5

High Z
High Z

A9
V,H

Don't Care

+5

+5

Pulsed VIL to VIH

V,H

+25

+5

D,N

Power Down

Program
PO/PGM

Program Verify

V,L

VIL

+25

+5

DOUT

07

Program Inhibit

VIL

V,H

+25

+5

High Z

o.
05
04

GNo

BLOCK DIAGRAM

, - - _ o r 03
Veco-----

DATA OUTPUTS
00-07

GNDo---

Cli
PO/PGM

PIN NAMES
ADDRESSES

AO-Al0
PD/PGM

POWER DOWN/PROGRAM

CS

CHIP SELECT

00-0 7

OUTPUTS

V-GATING

Ao-A
l0j

ADDRESS
INPUTS

16,384-BIT

CELL MATRIX

6-60

eC!'r!~L'M'NARY

2716

1$ IS not ,.
parametric Ii .
a Ina/specif .
m,ts are subj'
ICatlon. Som
.
'
m~~
e
The programming specifications are described in the PROM/ROM Programmmg InstructIOns on page 6-74.
ange.

PROGRAMMING

Absolute Maximum Ratings*

,

i..
... -10°Cto+80°C
Temperature Under Bias ...... .
.. _65°C to +125°C
Storage Temperature . . . . . . . . .
All Input or Output Voltages with
. +6V to -0.3V
Respect to Ground . . . . . . . .
Vpp Supply Voltage with Respect
to Ground . . . . . . . . . . . . . . . . . . . . +28V to -0.3V

*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.

READ OPERATION
D.C. and Operating Characteristics
TA=0°Ct070°C. VCC[1,2J =+5V±5%. Vpp[2J =Vcc±0.6V[3J
Symbol

Limits

Parameter

Typ.[4J

Min.

Unit

Max.

III

Input Load Current

10

ILO

Output Leakage Current

I pP1 [2J

Vpp Current

ICC1[2J

V CC Current (Standby)

ICC2[2J

V CC Current (Active)

VIL

Input Low Voltage

-0.1

VIH

Input High Voltage

2.2

VOL

Output Low Voltage

VOH

Output High Voltage

Conditions

J.1A

VIN = 5.25V

10

J.1A

VOUT = 5.25V

5

mA

Vpp = 5.85V

10

25

mA

PD/PGM = VIH, CS = V IL

57

100

mA

CS = PD/PGM = V IL

0.8

V

V c c+1

V

0.45
2.4

V

IOL = 2.1 mA

V

IOH = -400J.1A

NOTES: 1. VCC must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of ICC and IpP1.
3. The tolerance of

O.sV

allows the use of a driver circuit for switching the Vpp supply pin from

Vee

in read to 25V for program-

ming.
4. Typical values are for T A = 25°C and nominal supply voltages.

5. This parameter is only sampled and is not 100% tested.
6. tACC2 is referenced to PD/PGM or the addresses, whichBver occurs last.

Typical Characteristics

70

ACCESS TIME

YS.

YS.

vs.

TEMPERATURE

CAPACITANCE

TEMPERATURE

----

60

so

Vee'" 5V

.s

~

30
20

600

600

SOO

500

~

400

"
~

300

200

ICC1 STA DBY CURA NT

PO/PGM =VIH
Vee'" 5V

10

o

o

w

~

~

~

so

TEMPERATURE (Oe)

60

700

700

ICC2 ACTIVE CURRENT
PD/PGM '" VIL

;;{ 40

ACCESS TIME

ICC CURRENT

Vee'" 5V

-- --

g 400

f.--

lJ

~300
200

100

ro

-

I-- I-- r--

r--

100

o
60

I--

100

200

300

400

500

CL (pF)

6-61

600

700

800

o

w

w

~

~

so

TEMPERATURE eel

60

W

60

~~~I.'At'NARY
fIn:'

2716
A.C. Characteristics

IS IS

no

.

parametric 'imits :r:

SU

TA=0°Cto70°C, VCC[1] =+5V±5%, Vpp[2] =Vcc±0.6V[3]
Symbol

Parameter

Min.

Limits
Typ)4]

Max.

Unit

specification S
,ect to change: orne

Test Conditions

tACC1

Address to Output Delay

250

450

ns

PD/PGM = CS = VIL

tACC2

PD/PGM to Output Delay

280

450

ns

CS = VIL

tco

Chip Select to Output Delay

120

ns

PD/PGM = V IL

tpF

PD/PGM to Output Float

0

100

ns

CS = V IL

tDF

Chip Deselect to Output Float

0

100

ns

PD/PGM = V IL

tOH

Address to Output Hold

0

ns

PD/PGM = CS = VIL

Capacitance [5] T A = 25°C, f = 1 MHz
Symbol

Parameter

Typ.

A.C. Test Conditions:
Max.

Unit

Conditions

CIN

Input Capacitance

4

6

pF

VIN = OV

COUT

Output Capacitance

8

12

pF

VOUT= OV

NOTE: Please refer to page 2 for notes.

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ";;20 ns
Input Pulse Levels: 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs
1 V and 2V
Outputs 0.8V and 2V

WAVEFORMS
A. Read Mode
PD/PGM = VIL

)<

ADDRESS

><

~tOH~

\~

/

I---tco~

_tDF~

t ACC 1

/

HIGH Z

OUTPUT

\.
/

DATA OUT VALID

\
B. Standby Mode
CS= V IL

ADDRESS

PD/PGM

)<

ADDRESS N

/

STANDBY MODE

\

DATA VALID FOR ADDRESS N

ACTIVE MODE

r--(~~~~~)-

_tpF~

OUTPUT

ADDRESS N+m

\.
V

HIGH Z

/
\

DATA VALID FOR ADDRESS N+m

2716

~~!~'At'NARY

parametric limits :: f,nbal specification S
e su lect to change: om.

ERASURE CHARACTERISTICS

DESE LECT MODE

The erasure characteristics of the 2716 are such that erasure
begins to occur when exposed to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should
be noted that sunlight and certain types of fluorescent
lamps have wavelengths in the 3000-4000A range. Data
show that constant exposure to room level fluorescent
lighting could erase the typical 2716 in approximately 3
years, while it would take approximatley 1 week to cause
erasure when exposed to direct sunlight. If the 2716 is to
be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from
Intel which should be placed over the 2716 window to
prevent unintentional erasure.

The outputs of two or more 2716s may be OR-tied together on the same data bus. Only one 2716 should have its
outputs selected (CS low) to prevent data bus contention
between 2716s in this configuration. The outputs of the
other 2716s should be deselected with the CS input at a
high TTL level.
POWER DOWN MODE
The 2716 has a power down mode which reduces the active
power dissipation by 75%, from 525 mW to 132 mW.
Power down is achieved by applying a TTL high signal to
the PD/PGM input. In power down the outputs are in a
high impedance state, independent of the CS input.

The recommended erasure procedure (see page 3-55) for
the 2716 is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity X exposure time) for erasure should
be a minimum of 15 W-sec/cm 2 . The erasure time with this
dosage is approximately 15 to 20 minutes using an ultraviolet lamp with a 12000 /1-W/cm 2 power rating. The 2716
should be placed within 1 inch of the lamp tubes during
erasure. Some lamps have a filter on their tubes which
should be removed before erasure.

PROGRAMMING
Initially, and after each erasure, all bits of the 2716 are in
the "1" state. Data is introduced by selectively programming "O's" into the desired bit locations. Although only
"O's" will be programmed, both "1 's" and "O's" can be
presented in the data word. The only way to change a "0"
to a "1" is by ultraviolet light erasure.
The 2716 is in the programming mode when the Vpp power
supply is at 25V and CS is at V IH. The data to be programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs are
TTL.

DEVICE OPERATION

When the addresses and data are stable, a 50 msec, active
high, TTL program pulse is applied to the PD/PGM input.
A program pulse must be applied at each address location
to be programmed. You can program any location at any
time - either individually, sequentially, or at random.
The program pulse has a maximum width of 55 msec. The
2716 must not be programmed with a DC Signal applied to
the PD/PGM input.

The six modes of operation of the 2716 are listed in Table
I. It should be noted that all inputs for the six modes are at
TTL levels. The power supplies required are a +5V Vee and
a Vpp. The Vpp power supply must be at 25V during the
three programming modes, and must be at 5V in the other
three modes.

TABLE I. MODE SELECTION

~
MODE

Read

Deselect
Power Down
Program

cs

PD/PGM
(181

(201

Vpp
(211

Vee
(241

OUTPUTS
(9·11.13·17)

V Il

V,L

+5

+5

DOtJT

Don't Care

V,H

+5

+5

High Z

V ,H

Don't Care

+5

+5

High Z

Pulsed VIL to VIH

V,H

+25

+5

D,N

Program Verify

V,L

V,L

+25

+5

DOUT

Program Inhibit

V,L

V ,H

+25

+5

High Z

Programming of multiple 2716s in parallel with the same
data can be easily accomplished due to the simplicity of
the programming requirements. Like inputs of the paralleled 2716s may be connected together when they are programmed with the same data. A high level TTL pulse
applied to the PD/PGM input programs the paralleled
2716s.
PROGRAM INHIBIT
Programming of mUltiple 2716s in parallel with different
data is also easily accomplished. Except for PD/PGM, all
like inputs (including CS) of the parallel 2716s may be
common. A TTL level program pulse applied to a 2716's
PD/PGM input with Vpp at 25V will program that 2716.
A low level PD/PGM input inhibits the other 2716s from
being programmed.
PROGRAM VERIFY

READ MODE
Data is available at the outputs in the read mode. Data is
available 450 ns (tAecl from stable addresses with CS low
or 120 ns (teo) from CS with addresses stable.

A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify
may be performed wth Vpp at 25V. Except during programming and program verify, Vpp must be at 5V.

6-63

intel®
8308
8192 BIT STATIC MOS READ ONLY MEMORY

• Fast Access Time: 450 ns
• Standard Power Supplies: +12V, ±5V
• TTL Compatible: All Inputs and Outputs
Programmable Chip Select Input for
• Easy
Memory Expansion

• Three-State Output: OR-Tie Capability
Decoded: On Chip Address
• Fully
Decode
Inputs Protected: All Inputs Have Protec• tion
Against Static Charge
• Pin Compatible to 8708 PROM

The Intel® 8308 is a 8192 bit static MOS read only memory organized as 1024 words by 8-bits. This ROM is designed for
memory applications where high performance, large bit storage, and simple interfacing are important design objectives.
The inputs and outputs are TTL compatible. The chip select input (CS2/CS2) is programmable. An active high or low level
chip select input can be defined by the designer and the desired chip select logic level is fixed at Intel during the masking process. The programmable chip select input, as well as OR-tie compatibility on the outputs, facilitates easy memory expansion.
The pin compatible UV erasable 8708 PROM is available for initial system prototyping.
The 8308 read only memory is fabricated with N-channel silicon gate technology. This technology provides the designer
with high performance, easy-to-use MOS circuits.

BLOCK DIAGRAM

PIN CONFIGURATION

DATA OUTPUT

A,

Vee

A,

As

A,

A,

A,

\\'s

A3

CS1

A,

IIoD

A,

CS2/CS2[lJ

Ao

Os

a,

0,

0,

a,

03

a,

Vss

a,

CS1 _ _ _
CHIP SELECT

LOGIC
CS2!CS2 _ _ _

I

As _
, A,_

DECODER

Y GATING

X
DECODER

64 X 128
ROM ARRAY

A6 I

Ao -A9
~
ADDRESS
INPUTS

As_
A
A _ ,_
A,3 _ _
A, _ _
Ao-

PIN NAMES
AO-A 9

ADDRESS INPUTS

°1-08

DATA OUTPUTS

cs,

CHIP SELECT INPUT

CS2/CS2[11

PROGRAMMABLE CHIP SELECT INPUT

OUTPUT BUFFERS

NOTE 1. The CS2/CS2 LOGIC LEVELS MUST BE SPECIFIED BY THE USER AS
EITHER A LOGIC 1 (VIH) OR LOGIC 0 (VILJ. A LOGIC 0 SHOULD
BE SPECIFIED IN ORDER TO BE COMPATIBLE WITH THE 8708.

8308
ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Ambient Temperature Under Bias . . . . . . -25°C to +85°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin With Respect
To Vss . . . . . . . . . . . . . . . . . . .. -0.3V to 20V
Power Dissipation . . . . . . . . . . . . . . . . . . .
1.0 Watt

Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other condi·
tions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi-

tions for extended periods may affect device rei iability.

PROGRAMMING
The programming specifications are described in the PROM/ROM Programming Instructions on page 6-74.

D.C. AND OPERATING CHARACTERISTICS
TA = O°C to +70°C, VCC = 5V ±5%; Voo = 12V ±5%, Vss = -5V ±5%, VSS = OV Unless Otherwise Specified.
Limits
Symbol

Parameter
Min.

III

Input Load Current
(All Input Pins Except

TypJ1l

Unit

Max.

Test Conditions

±10

MA

V ,N = 0 to 5.25V

Cs 1 )

I LCL

I npu t Load Cu rrent on CS 1

-1.6

mA

V,N = 0.45V

ILPC

Input Peak Load Current on CS 1

-4

mA

V ,N = 0.8V to 3.3V

ILKC

Input Leakage Current on CS 1

10

MA

V ,N = 3.3V to 5.25V

ILO

Output Leakage Current

10

MA

Chip Deselected

V,L

Input "Low" Voltage

V ,H

Input "High" Voltage

VOL

Output "Low" Voltage

VOH1

Output "High" Voltage

2.4

VOH2

Output "High" Voltage

3.7

Vss-l
3.3

0.8V

V

Vcc+l.0

V

0.45

V

IOL = 2mA

V

IOH = -4mA

V

IOH=-lmA

ICC

Power Supply Current Vcc

10

15

mA

100

Power Supply Current Voo

32

60

mA

Iss

Power Supply Current Vss

10MA

1

mA

Po

Power Dissipation

460

840

mW

NOTE 1: Typical values for TA

=

--_.

25° C and nominal supply voltage

D.C. OUTPUT CHARACTERISTICS

D.C. OUTPUT CHARACTERISTICS

tA =Oto7QOC

~I

i
-

.I

-t;'CAL
---'-

-

o £o

.1

.2

~,/
--~·t·

I
.3

-7 f---+--+-~'+---I

~ -6

I

V.

~B

-1---

-t--

II

I

~9 I-+..-t-·-f--+-~+-~+-+-t--+---i

,

I

V'

,./

V

.4
VOL

.5

SPEC
I
.6

/ :,
.~-

.7

'-+--+-f--+-'..!

L

I--~~j-

.8

.9

1.0
VOH

VOLTS

6-65

VOLTS

8308
A.C. CHARACTERISTICS
TA = o°c to +70°C, vee

= +5V

±5%; VDD

= +12V

±5%, VBB

= -5V

±5%, vss

= OV,

Unless Otherwise Specified.
Limits[2]

Symbol

I

tAee
teal
te02
tOF

I

Parameter

Unit

Typ.

Max.

Address to Output Delay Time

200

450

ns

Chip Select 1 to Output Delay Time

85

160

ns

Chip Select 2 to Output Delay Time

125

220

ns

Chip Deselect to Output Data Float Time

125

220

ns

Min.

NOTE 2: Refer to conditions,of Test for A.C. Characteristics. Add 50 nanoseconds (worst case) to specified values at

VOH

=

3.7V@ 10H

=

-lmA, eL = 100pF.

CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS

CAPACITANCE TA = 25°C, f = 1 MHz, VBB = -5V, VDD,
Vee and all other pins tied to Vss.

Output Load . . . . . . . . 1 TTL Gate, and CLOAD = 100pF
Input Pulse Levels. . . . . . . . . . . . . . . .. .65V to 3.3V
Input Pulse Rise and Fall Times . . . . . . . . . . . 20 nsec
Timing Measurement Reference Level
. . . . . . . . . . . . . . . . . , 2.4V VIH, VOH; 0.8V VIL , VOL

Symbol

----------'""

---.."...---,f-

ADDRESS

Ao·~

cs,

---------------,

6-66

Test

Limits
Typ.

Max.

CIN

Input Capacitance

6pF

GoUT

Output Capacitance

12pF

8308
TYPICAL CHARACTERISTICS

(Nominal supply voltages unless otherwise noted.)

A. OUTPUT CAPACITANCE
VS. A. OUTPUT DELAY

100 VS. TEMPERATURE
(NORMALIZED)
1.4

+40 , - - - - . , - - - - , - - - - , - - - - ,

1.3

I

1.2

,,
,

1. 1
1.0

i

.........

.9
.8
.7

+20

f-1---

;--.....

i

I

I

... -

+

,- - -

f----+-----+---\T----j

!

,j-

.

.........

;--.....

-20 .....~--+__--_t--

.........

.6
10

20

30

40

50

60

70

80

90

cs,

-2.5

~
IIII
--- ---T-1-I

I

:.

-2.0
~

.5 -1.5

V1

-1.0

-.5

o

I

o

.5

TACC VS. TEMPERATURE
(NORMALIZED)
1.4

1.3

__

r1.2

,

1.0

I

.9

I

;

.7 f - -

\

-

1---

.8

i

1.5

.. -

r--

1.1

I

1.0

-_.

-

.

/

VI

+100

11 CAPACITANCE (pF)

INPUT
CHARACTE R ISTICS
-3.0

+50

-50

AMBIENT TEMPERATURE TA (OC)

--- ---

V

-

.6

o.~.
2.0

2.5

o

3.0

VIN (VOLTS)

10

20

30

40

50

60

70

AMBIENT TEMPERATURE TA (OC)

6-67

80

90

inter
8316A
16,384 BIT STATIC MOS READ ONLY MEMORY
Organization-2048 Words x 8 Bits
Access Time-8S0 ns max

• Single + 5 Volts Power Supply Voltage
Directly TTL Compatible - All Inputs
• and
Outputs
Low Power Dissipation of 31.4 ,uW/Bit
• Maximum
Three Programmable Chip Select
• Inputs
for Easy Memory Expansion

Three-State Output - OR-Tie
• Capability
Fu"y Decoded - On Chip Address
• Decode
Inputs Protected - A" Inputs Have
• Protection
Against Static Charge

®

The Intel 8316A is a 16,384-bit static MOS read only memory organized as 2048 words by 8 bits. This ROM is
designed for microcomputer memory applications where high performance, large bit storage, and simple interfacing are important design objectives.
The inputs and outputs are fully TTL compatible. This device operates with a single +5V power supply. The
three chip select inputs are programmable. Any combination of active high or low level chip select inputs can be
defined and the desired chip select code is fixed during the masking process. These three programmable chip
select inputs, as well as 0 R-tie compatibility on the outputs, facilitate easy memory expansion.
The 8316A read only memory is fabricated with N-channel silicon gate technology. This technology provides the
designer with high performance, easy-to-use MOS circuits. Only a single +5V power supply is needed and all
devices are directly TTL compatible.

PIN CONFIGURATION

BLOCK DIAGRAM

....--0 Vee
..............0 GND

Vee

0,
0,
OJ

°4

A ,O
Ag
As

0,
0,
°7

~

A7
A,

"'w
~
~

~

r-

OS

A,

es ,

A4

"''"

AJ

0
0

es,
eS J

A,

~
~

w

"'

"

16,384 BtT
CELL MATRIX

A,
Ao

eS3

PIN NAMES
ADDRESS INPUTS~~~~~---j
OAT A OUTPUTS
PROGRAMMABLE CHIP SELECT INPUTS

6-68

8316A

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . -10°Cto 80°C
Storage Temperature
. . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin
With Respect to Ground
Power Dissipation

...........

-O.5V to + 7V

. . . . . . . . . . . . . . . . . . . . . . . 1.0W

PROGRAMMING: The programming specifications are In
the ROM and PROM Programming Instructions (see page 6-74).

D.C. AND OPERATING CHARACTERISTICS

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
T A = O°C to +70°C, Vee = 5V ±5% unless otherwise specified

LIMITS
PARAMETER

SYMBOL

TYP.111

MIN.

1

I nput Load Current

III

TEST CONDITIONS

UNIT

MAX.

10

f.lA

V 1N = 0 to 5.25V

(All Input Pins)
ILOH

Output Leakage Current

10

f.lA

CS = 2.2V, VO UT = 4.0V

ILOL

Output Leakage Current

-20

i1 A

CS = 2.2V, VOUT = 0.45V

lee

Power Supply Current

98

mA

All inputs 5.25V Data Out Open

VIL

Input "Low" Voltage

-0.5

0.8

V

V IH

Input "High" Voltage

2.0

Vee+ 1.OV

V

VOL

Output "Low" Voltage

0.45

V

IOL = 2.0 mA

VOH

Output "High" Voltage
----,---

V

IOH = -100 i1 A

I

40

2.2
-'------

-

-------

(1) Typical values for T A "-- 25"C and nominal supply voltage

TYPICAL D.C. CHARACTERISTICS

STATIC ICC VS. AMBIENT TEMPERATURE
WORST CASE

VIN LIMITS VS. TEMPERATURE

80~--~--~~---+---~

60
Vee

~

5.25V

ALL ADDRESSES TIED

rOVce

1 Il

L-----1_---'_---'_---'_--L_--L_-'

°

10

20

30

40

50

60

20

70

40

OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE

OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE
30r--,--,--,--,--,--,-,

-30

25

-25

20

-20

15

..§. -15

I

"ico

80

60

TA I C)

T A { C)

O?

.0

I t-

~+-t
I
I

-lO

-T7-;~~1
VCC rvllN

I

+--:I

6-69

VOH {VOL lSJ

~

8316A
A.C. CHARACTERISTICS

TA ~ o°c to +70°C, Vee ~ +5V £5% unless otherwise specified
LIMITS
PARAMETER

SYMBOL

TYP.lll

MIN.

400

Address to Output Delay Time

tA
teo

Chip Select to Output Enable Delay Time

tOF

Chip Deselect to Output Data Float Delay Time

850

0

CAPACITANCE

CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS

(2) TA

UNIT

MAX.

nS

300

nS

300

nS

= 25°C, f = 1 MHz
LIMITS

Output Load ... 1 TTL Gate, and CLOAO ~ 100 pF
Input Pulse Levels . . . . . . . . . . . . . . . 0.8 to 2.0V
Input Pulse Rise and Fall Times .(10% to 90%) 20 nS
Timing Measurement Reference Level
Input . . . . . . . . . . . . . . . . . . . . . . . . 1.5V
Output . . . . . . . . . . . . . . . . 0.45V to 2.2V

SYMBOL

TEST

TYP.

MAX.

CIN

All Pins Except Pin Under
Test Tied to AC Ground

4 pF

10 pF

COUT

All Pins Except Pin Under
Test Tied to AC Ground

8 pF

15 pF

(21 This parameter is periodically sampled and is not 100"10 tested.

A.C.'WAVEFORMS
ADDRESS

-- ----- !eo-

'OF

PROGRAMMABLE
CHIP SELECTS

----I.I.

- 'A

f'---oUTP_UTVA_Llo

TYPICAL A.C. CHARACTERISTICS
ACCESS TIME VS. LOAD
CAPACITANCE

ACCESS TIME VS. AMBIENT
TEMPERATURE
900

800

600

~

-

~

y

~

200

20

40

800

I--- ~

WORST CASE

----

:J400

V

1000

600

~ICAL

60

--

~
:J400

~PICAL

200

80

100

TA ( C)

200

300

CLOAD (pfd)

6-70

400

500

2316E
16,384 BIT STATIC ROM

• Fast Access Time- 450 ns Max.

• EPROM/ROM Pin Compatible for
Cost-Effective System
Development

• Single +5V ±. 10% Power Supply

• Completly Static Operation
• Intel MCS 80 and 85 Compatible
• Three Programmable Chip
Selects for Simple Memory
Expansion and System Interface

• Inputs and Outputs TTL
Compatible
• Three-State Output for Direct
Bus Interface

The Intel® 2316E is a 16,384-bit static, N-channel MaS read only memory (ROM) organized as 2048 words by 8 bits. Its
high bit density is ideal for large, non-volatile data storage applications such as program storage. The three-state outputs and
TTL input/output levels allow for direct interface with common system bus structures. The 2316E single +5V power supply
and 450 ns access ti me are both ideal for usage with high performance microcomputers such as the Intel MCS™ -80 and
MCSTM-85 devices.
A cost-effective system development program may be implemented by using the pin compatible Intel 2716 16K UV EPROM
for prototyping and the lower cost 2316E ROM for production. The 2716 is fully compatible to the 2316E in all respects.
The three 2316E programmable chip selects may be defined by the user and are fixed during the masking process. To simplify
the conversion from 2716 prototyping to 2316E production, it is recommended that the 2316E programmable chip select
logic levels be defined the same as that shown in the below data sheet pin configuration. This pin configuration and these chip
select logic levels are the same as the 2716.

PIN CONFIGURATION

BLOCK DIAGRAM

A7

Vee

---<>Vcc

A6

A8

---<> GND

A5

A9

A4

e53

A3

(Sl

A,

A'0

A,

e5,

AO

D7

DO

D6

Dl

D5

D,

D4

GND

D3

A9
A8

A5

16,384 BIT

CELL MATRIX

CHIP

SI~~~~T

PIN NAMES

BUFFERS

AO

6-71

..-

CS2

!:!:Ir~'M'NARY

2316E

's IS nOf f

parametric limits ar:

ABSOLUTE MAXIMUM RATINGS*

s~n:' specification So
,ect to change:

Ambient Temperature Under Bias . . . . . . . . _1O oe to Booe
Storage Temperature . . . . . . . . . . . . . . _65°e to +150 oe
Voltage On Any Pin With Respect
to Ground . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1.0 Watt

*COMMENT: Stresses above those listed under "Absolute Maxi·

mum Ratings" may cause permanent damage to the device. Th is is a
stress rating only and functional operation of the device at these or
at any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.

D.C. AND OPERATING CHARACTERISTICS
T A = oOe to +70°C, Vee

= 5V ±10%, unless

otherwise specified.
LIMITS

SYMBOL

PARAMETER
MIN.

III

Input load Current
(All Input Pins)

ILOH

TEST CONDITIONS

UNIT

Typ.(1)

MAX.

a to 5.25V

10

pA

VIN =

Output leakage Current

10

pA

Chip Deselected, VOUT = 4.0V

ILOL

Output leakage Current

-20

pA

Chip Deselected, VOUT = O.4V

120

mA

All Inputs 5.25V Data Out Open

O.B

V

V ee +1.0V

V

0.4

V

IOL = 2.1 mA

V

IOH =- 400 pA

lee

Power Supply Current

VIL

Input "Low" Voltage

-0.5

VIH

Input "High" Voltage

2.4

VOL

Output "Low" Voltage

VOH

Output "High" Voltage

NOTE: 1.

70

2.4

Typical values for T A = 25" e and nominal supply voltage.

A.C. CHARACTERISTICS
T A = oOe to +70°C, Vee

= +5V

±10%, unless otherwise specified.
LIMITS

SYMBOL

PARAMETER

MIN.

UNIT
MAX.

tA

Address to Output Delay Time

450

ns

teo

Chip Select to Output Enable Delay Time

120

ns

tOF

Chip Deselect to Output Data Float Delay Time

100

ns

10

CAPACITANCE(2)

CONDITIONS OF TEST FOR
A.C. CHARACTERISTICS

SYMBOL

Output load . . . . . . . . . . . 1 TTL Gate and CL = 100 pF
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . O.B to 2.4V
Input Pulse Rise and Fall Times (10% to 90%) . . . . . 20 ns
Timing Measurement Reference Level
Input . . . . . . . . . . . . . . . . . . . . . . . . . lV and 2.2V
Output . . . . . . . . . . . . . . . . . . . . . . . O.BV and 2.0V

T A = 25°e, f = 1 MHz

TEST

LIMITS
TYP.

MAX.

CIN

All Pins Except Pin Under
Test Tied to AC Ground

5 pF

10 pF

COUT

All Pins Except Pin Under
Test Tied to AC Ground

10 pF

15 pF

NOTE: 2. This parameter is periodically sampled and is not 100%
tested.

6-72

me

2316E

A.C. Waveforms
I

""

ADDRESS

I----'eo---I

PROGRAMMABLE

CHIP SELECTS

I-----'A--

OUTPUT
DATA

1111111

""~H",'"

•••••
%1
~@.2I~'m;
ZfZf!(~••••
;:••

Typical System Application (8K x 8 ROM Memory)

;"'lIlii!d!1

9;1,;1 ,9 9, ~,!,!:.!~.9 1: ,!~: .~.,J ,1,:,11 ~ 1~ 9~ I ~ 1,1"

6-77

Data

Column

f----;---=P-""-,ch-'~TO---~
Blank

Customer Company Name
Blank
Customer's Company DiVISion or location

Blank

Customer Part Number
Blaflk
Punch the Intel 4·dlgit baSIC part number and
In ( ) the number of output bits, e.g., 2708
IS}, 2316 (8). or 3605 (4)
Blank

Chip number for ROMs With programmable
chip select Inputs. If not applicable, leave

77-78

blank.
Blank

79-80

Punch a 2·dlglt deCimal nLlmber to Indicate

truth table number. The first truth table
will be 00, second 01, third 02. etc

a. N word x 8·bit device

Column

2-3

4-7

8-9

10-73
75-75
76-78
79-80

Data

Record mark: A colon is used to signal the
start of a record.
Record length: This is the count of the actual
data bytes in the record. Column 2 contains the high order digit of the count,
Column 3 contains the low order digit. A
record length of zero indicates end of file.
All frames containing data will have a
maximum record length of 10Hex bytes
(32 decimal).
Load address: The four characters starting
addresses at which the following data will
be loaded. The high order digit of the load
address is in Column 4 and the low 9rder
digit is in Column 7. The first data byte is
stored in the location indicated by the load
address. Successive data bytes are stored in
successive memory locations. ROMs containing more than 32 bytes of data will use
two or more records or cards to transmit
the data. Although the load address for the
beginning record need not be 0000, each
subsequent load address should be "10H"
(32 decimals) greater than the last.
Record type: A 2-digit code in this field specifies the type of this record. The high order
digit of this code is located in Column 8.
Currently, all data records are type O. Endof-file records will be type 1; they are distinguished by a zero RECORD LENGTH
field (see above). Other possible values for
this field are reserved for future expansion.
Data
Checksum: Same as paper tape format.
Blank
Punch same 2-digit decimal number as in Title
Card.

b. N word x 4-bit device
This format is identical to the previously documented 8-bit hexadecimal format with the following exceptions:

Column

Data

10-73

Each memory location is represented by two
columns containing the characters 0-9,
A-F. Since this is 4-bit data, the user must
indicate which character of each pair is to
be used as valid data. A single deck must be
submitted without mixing first and second
characters of the pair.

C2. PN Computer Punched Card Format
A word field consists of only P's and N's. A punched P will result in an output high level and a punched N in an output low
level. The Band F characters, unlike the paper tape format, are illegal characters. The entire data field for all bits must be
punched even if it is "don't care". The data field must begin in consecutive order, starting with address 0 (all addresses
logically lowl.
DECIMAL NUMBER INDICATING
THE TRUTH TABLE NUMBER
NO. OF OUTPUTS
4or8
TITLE CARD
DESIGNATION

1

CUSTOMER'S
DIVISION OR
LOCATION

CUSTOMER'S
COMPAN; NAME

\',,:~

:~.C~'I

:"~;:'":d

1

INTEL

,>:;!'UC') CCRP

III
II
I III

22 l111111111l? 12

n

I

PIN

00

111111111

III

I I

I

Column

Data

1
2-3
4-28
29-30
31-50
51-52
53-61
62-63
64-72

Punch a T
Blank
Customer Company Name
Blank
Customer's Company Division or location
Blank
Customer Part Number
Blank
Punch the Intel 4-digit basic part number and
in ( ) the number of output bits; e.g., 2708
(8), 2316(8), or 3605(4)
Blank
Chip number for ROMs with programmable
chip select inputs. If not applicable, leave
blank.
Blank
Punch a 2-digit decimal number to indicate
truth table number. The first truth table
will be 00, second 01, third 02, etc.

11111111111111211211112211111111112 211112111221111111121111111

I]] 111111111111 3 3313 JIJ 1 J 311 J J 3 J 3 3 J 1 JllllI]

n

31113 J 111 J J] 1 J 313 J 3] J 3113 11 J 1 3 1 J J J J

44 4 ~ 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 U 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 44 4 4 4 4 4 41 U 4 4 4 4 4 414 4 4 4 4 4 4 4 4

73-74
75-76

SS 5 5 5 55 5 515155 5515 55 55 5 5 5 5 5 5 5 5 5 5 5 55 515 5 5 5 55 555 5 5 5 55 5 555 5 5~5 5 5 SIS 5 55 55 5 51515 5 5 5 5 5
G6 6 6 6566666666616666661666666666666666666666666666166666 6 6 6 6 6 6 6 666666666666 £ 6 666
111 J 1111111111111111] J 1111111111 J 111111111 J 11 J 11 J 1 J II J 1111 J 171 J 11/11111/1/111/1/

a8 as 8 818 a8 ft B8 BB8 8 8 8 8 8 BBBB8 8 8 B8 8 8 8 B8 B8 8 8 8 8 8 B8 8 8 8 B8 8 B8 8 B8 8 BBB8 8 8 8 8 SS 8 8 8 8 8111 BB8 8 8 B

77-78
79-80

9999 9 g 919 9 S 9 9 919 U 99 9 9 91 ~ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 919 9 3 9 919 9 9 9 9 9 9 9 9 9 3 9 j 9 9 9 9 9 9 9 9 9 ~ 9 9 9 9 999
! ) • \ • ' , , '~.~;~,;' II'!" 'II~ 101' Ii ;);. 11/'

"/I" 10113/ '3 )'jll6 II 31l1'i" 'l'!!""\<" 1113:1 ,I 1<11"1,,,,1 ,''''r,: "'J'"

L66"5"J~" 1,",',

".n ,',-",

Title Card Format.
For a N words X 4·bit organization only, cards 2 and
those following should be punched as shown. Each card
specifies the 4·bit output of 14 words.

LSBDECIMAL WORD
ADDRESS BEGINNING
EACH CARD

f'ASB,
14 DATA FIELD:

,..L-,

1

Column

1-5

DECIMAL NUMBER
INDICATING THE
TRUTH TABLE NUMBER

),

/1)(100 f"tlf'I"l 1'1NI'1f1 f'f'f'f' f'ff'INF' Pf'Nt'l NI1PP PPPI1 PI1Pfl F'f'f1f1 liFH' f'Ht-ill FH'F' h/tPP PI'111P

00

1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111

~~ ~~ ~ ~ ~ ~ ~ ,~,~ I~ ~,~ ~,~ ~,~ ,~ ~o~ ~~ ~ 1~!~ ~ ~! ~ ~~! ~ !l~~! ~~ ~1~ ~"o\~ ~ ~I'~ ~\~ ~1~) ~ ~~ ~1 ~ ~!~~, ~ ~~. ~~ ~1~1~' ~I~' ~! ~~, ~ ~i ~1~'~!

11111111111111111111111111111111111111111111111111111111111111111111111111111111

222222222 12 22 22 22 12 22 22

n

21 2 22 22 2 22 2 2 212 2 22 2 1 2 2 2 2 2 2 2 2 2 2 2 2 22222 11 Z2 2 2 2 2 2 2 2 2 22 2 2 2 2

1 J J 1 J J 1 J] 1 J J 3 J J 1]1 J J J J J J 1 J 333 33 J 3 111]J 3 3] lJ J 3 J3 J 3333 J] J J 3 J J 113 J 31133133 J J 33 J 333 J
(444 U 444 U

n

4 4 U U 4 (44 4 4 4 4 j

1j ~

14 t 4 4(4 44 4 44 4 44 4 44 44 4 4 4 4 q 4 4 4 44 4 4 4 4 4 44 44 44 44 4 44 4 (

55555 S SIs Is 11115 5 S"S ~ 5111 J 5 ~ J II J II) 5 5 S 5 51551 S1555115155"555111 5 'j 5 5 5 5115 5 5 5115 5 5 5 5 5
i6&666666666666G6666666H66H66666666666S666661iG66666666666&66666666666666666666
1111111111, Il1111111111 l l l l l l 1 1 1 11111111 11111111/ 1 7111111111111111111111111111; 1

88 B8 8 8 Q88 B8 8 8 8 8 B8 BBB8 8 9 8 8 sa 8886 B6 e8 B8 B8 8 B8 8 B8 BB8 a888888 BBB8 B8 BB8 8 B8 8 B8 8 8 8 8 B8 8 B8 8
9 9 9 ~ 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 1 9 9 9 9 ~ 9 9 9 9 S9 9 9 9 99 9 9 9 9 9 9 9 9 9 9 9 9 99 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

11

I , \ . I I , '~.'~~'\'111111'10llll!lI'illilil'I'JOJIJ11114IUIHIIJl<4I1U'

TA = 70°C

I_--L r···· . -

1.6

1.'

I--

V1lIMAX/

I

1

1.2

r

Vi

10

20

•

30

5.~V

---._-

--

CYCLE TIME

--

.+ __

0.95

50

60

'.0

70

'.5

5.5

5.0

6.0

Vee (VOLTS)

ACCESS TIME VS.
AMBIENT TEMPERATURE

ACCESS TIME VS.
LOAD CAPACITANCE
350
TA .. 25"C

: Vee MIN.
I 1 TTL LOAD

-- -

Vee MIN.
, TTL LOAD

<;. = l00pF

2SO

I-'
lSO

1

I
40

TA 1°C)

35a

350ns

I

~

TiEFT
.L
UT

2SO

..

-

I

lSO

.
CE rELS[ VOH ' 2.0V
VOL '"'t O.BV

so

so
0102030405060

70

TA 1°C)

6-101

a

'"

600
CL (pF)

infer
8111A-4
1024 BIT STATIC MOS RAM
WITH COMMON 1/0
* 450 nsec Access Time Maximum

* 256 Word by 4 Bit Organization

• Single +5V Supply Voltage
Directly TTL Compatible:
• and
Outputs

All Inputs

Static MOS: No Clocks or Refreshing
• Required
Memory Expansion: Chip Enable
• Simple
Input

• Powerful Output Drive Capability
Low Cost Packaging: 18 Pin Plastic Dual
• In-Line
Configuration
Low Power: Typically 150mW
• Three-State
Output: OR-Tie Capability
•
Disable Provided for Ease of Use
• inOutput
Common Data Bus Systems

The Intel® 8111A-4 is a 256 word by 4-bitstatic random access memory element using N-channel MOS devices integrated
on a monolithic array. It uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate.
The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 8111A-4 is designed for memory applications in sma" systems where high performance, low cost, large bit storage,
and simple interfacing are important design objectives.

It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. Separate chip enable (CE) leads allow
easy selection of an Individual package when outputs are OR-tied.
The Intel® 8111A-4 is fabricated with N-channel silicon gate technology. This technology allows the design and
production of high performance, easy-to-use MOS circuits and provides a higher functional density on a monolithic chip
than either conventional MOS technology or P-channel silicon gate technology.
Intel's silicon gate technology also provides excellent protection against contamination. This permits the use of low cost
plastic packaging.

PIN Co.NFIGURATION

LOGIC SYMBOL

A,

Vee

AD

A,

A4

A,

BLOCK DIAGRAM

AD

I/O,
A,

A,

R/W

A,

1/°2

A,

AD

ttl

A,

1/°3
8111A-4

A,

As

1/0 4

A4

1/°4

A,

A.

110 3

As

A,

1/0 2

A,

GNO

lID,

A,

R/W

00

liD,
1/02

0
0

CD

@

--Vee
ROW

SELECT

MEMORY ARRAY
32 ROWS
32 COLUMNS

~GNO

@
@
@

@

@

tE2

00

@

INPUT
DATA
CONTROL

1/03

I/o.o.?;

PIN NAMES

tE,

ADDRESS INPUTS
OUTPUT DISABLE
READIWRITE INPUT
CHIP ENABLE 1

CO,

CHIP ENABLE 2

AO-A7

00
R/W

a

1/0,-1/04 OAT A INPUT IOUTPUT

6-102

eo

PIN NUMBERS

8111A-4

*COMMENT:

ABSOLUTE MAXIMUM RATINGS*

Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Ambient Temperature Under Bias ..... -10°C to BO°C
Storage Temperature . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to Ground. . . . . . . ..

-0.5V to +7V

Power Dissipation ... . . . . . . . . . . . . . . . .. 1 Watt

D.C. AND OPERATING CHARACTERISTICS
TA = o°c to 70°C, Vcc = 5V ±5% ,unless otherwise specified.
Symbol

Parameter

Min.

Typ.£ll

Max.

Unit

Test Conditions

III

Input Load Current

1

10

IlA

V IN = 0 to 5.25V

ILOH

I/O Leakage Current

1

10

IlA

Output Disabled, V1I0=4.0V

ILOL

I/O Leakage Current

-1

-10

IlA

ICC1

Power Supply
Current

35

55

mA

Output Disabled, V1I0=0.45V
VIN - 5.25V

ICC2

Power Supply
Current

60

mA

Input Low Voltage

-0.5

O.B

V

VIH

Input High Voltage

2.0

Output Low Voltage

Vcc
0.45

V

VOL

VIL

Output High
VOH

2.4

Voltage

OUTPUT SOURCE CURRENT VS.
OUTPUT VOLTAGE

11/0 = OmA, T A = 25°C
VIN = 5.25V
11I0=OmA, TA = O°C

V

10L = 2.0mA

V

10H = -4001lA

OUTPUT SINK CURRENT VS.
OUTPUT VOLTAGE

AMBI~NT TE MPEA2TUR'E
1

\

\~
ct

-10

.§

l'
-5

0

..
25°C
1----::::: 70°C

~

"

1\\

'\

Vee'" 4.75V

'\..iUTPUI

"H1Gr" TYilCAL

~
VOL (VOLTS)

VO H (VOLTS)

NOTE: 1. Typical value. are for TA = 25°C and nominal.upply voltage.

6-103

8111A-4
A.C. CHARACTERISTICS
READ CYCLE TA = O°C to 70°C, Vce = 5V ±5%, unless otherwise specified.
Symbol

Parameter
Read Cycle

Max.

Unit

tA

Access Time

450

ns
ns

tco

Chip Enable To Output

310

ns

too
tOF [21

Output Disable To Output

250

tRC

-

T yp.(1)

Min.
450

1-"---' t - - - -

Data Output to High Z State
Previous Read Data Valid
after change of Address

tOH

(See Be[ow)

ns
-~

--

ns

200

0

Test Conditions

ns

40

WRITE CYCLE
Symbol

Parameter

twc

Write Cycle

T yp.[11

Min.

Max.

Unit

270

ns
ns

tAW

Write Delay

20

tew

Chip Enable To Write

250

ns

tow

Data Setup

250

ns

tOH
twp

Data Hold

0

Write Pulse

250

tWR

Write Recovery

0

ns

tos

Output Disable Setup

20

ns

A.C. CONDITIONS OF TEST
tr,tf . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ns
Input Levels . . . . . . . . . . . . • . . . . . 0.8V or 2.0V
Timing Reference . . . . . . . . . . . . . . . . . . . 1.5V
Load . . . . . . . . . . . . 1 TTL Gate and CL = 100 pF

Test Conditions

(See Below)

ns

--

ns

CAPACITANCE
Symbol

[31
TA = 25°C, f = 1 MHz
Test

Limits (pF)
TypJl1 Max.

C'N

Input Capacitance
(All Input Pins) VIN = OV

4

8

ClIO

I/O Capacitance VI/a = OV

10

15

WAVEFORMS
READ CYCLE

WRITE CYCLE

1 - - - - - - - tRc------1

I------~c-------~I

ADDRESS

CHIP
ENABLES

ADDRESS

_--t_'""\I_tco -

CHIP
ENABLES

(m.m,

(eEl ·CE2 )
OUTPUT
DISABLE

OUTPUT

DISABLE

DATA 110

__________

DATA I/O
-JI·'---~:::;;;,.,--+

READ!
WRITE

NOTES: 1. Typical values are for TA = 25°C and nominal supply voltage.
2. tOF is with respect to the trailing edge of CE1, CE2, or 00, whichever occurs first.
3. This parameter is periodically sampled and is not 100% tested.

6-104

inter
5101 FAMILY
256 X 4 BIT STATIC CMOS RAM

~
i

PIN

Typ. Current @ 2V Typ. Current @ 5V Max Access

5101L
5101L-1
51 01 L-3
5101-8

(IJA)

(IJA)

(ns)

0.14
0.14
0.70

0.2
0.2
1.0
10.0

650
450
650
800

Directly TTL Compatible:
• All
Inputs. and Outputs

• Single +5V Power Supply
• Ideal for Battery

• Three-State Output

Operation (5101 L)

The Intel® 5101 is an ultra·low power 1024-bit (256 words X 4 bits) static RAM fabricated with an advanced ion-implanted
silicon gate CMOS technology. The device has two chip enable inputs. Minimum standby current is drawn by this device when
CE2 is at a low level. When deselected the 5101 draws from the single 5-volt supply only 10 microamps. This device is ideally
suited for low power applications where battery operation or battery backup for non-volatility are required.
The 5101 uses fully DC stable (static) circuitry; it is not necessary to pulse chip select for each address transition. The data is read
out non-destructively and has the same polarity as the input data. All inputs and outputs are directly TTL compatible. The 5101
has separate data input and data output terminals. An output disable function is provided so that the data inputs and outputs may
be wire OR-ed for use in common data I/O systems.

The 5101 L has the additional feature of guaranteed data retention at a power supply voltage as low as 2.0 volts.
A pin compatible N-channel static RAM, the Intel® 2101 A, is also available for low cost applications where a 256 X 4 organization is needed.
The Intel ion-implanted, silicon gate, Complementary MOS (CMOS) process allows the design and production of ultra-low power,
high performance memories.

PIN CONFIGURATION

'"

22

Vee

21

A,

A,

20

A,

"0
A,
A,

CEl

A,

18

00

As

17

CE2

A,

16

DO,

GNo

15

DI,

0',

14

DO,

13

0',

As

...

00,

10

0',

11

BLOCK DIAGRAM

A,

R/W

,.

"0

LOGIC SYMBOL

12

ROW
DECODERS

X
X

CE,
X
L
X
H
H

A,

0',
0',
0',

DO

DI,

DO

DO

CE2

H

X
X
H

X
X
H

X
X
X
X
X
X

DO,

DO

R/W

'-+11>""'<>00,

D,

OD

R/W o'N

Ci"-1.... :>0-,........

ffi~---;=~<

DO,

00

32 ROWS
32 COLUMNS

As

TRUTH TABLE

ce,

CELL ARRAY

0,

L.......f-t:::~ODO,

0,
0,

'---HI>'''''<> DO,

Output
Mode
High Z Not Selected
HighZ Not Selected
HighZ Output Disabled
High Z Write

o'N

Write

DOUT

Reed

o
6-105

= PIN NUMBERS

5101 FAMILY

Absolute Maximum Ratings *

'COMMENT:

Ambient Temperature Under Bias ..... -10oe to sooe

Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature . . . . . . . . . . _65°C to +150°C
Voltage On Any Pin
With Respect to Ground .... -0.3V to Vcc +0.3V
Maximum Power Supply Voltage . . . . . . . .. +7 .OV
Power Dissipation . . . . . . . . . . . . . . . . . .. 1 Watt

D. C. and Operating Characteristics
TA ; o°c to 700 e, Vcc ; 5V ±5% unless otherwise specified.

Symbol
IL2[2]

Parameter

5101 Land 5101 L-1
5101 L-3
5101-8
Limits
Limits
Limits
Min. Typ.[1] Max. Min. Typ.[1] Max. Min. Typ.ll] Max. Units

Input Current

IILOIl2] Output Leakage Current

5

5

5

1

1

2

nA
pA

Test Cond itions
CE1~2.2V, VOUT~

o to Vee

ICCl

Operating Current

9

22

9

22

11

25

mA

VIN~VCC, Except
CEl <0.65V,
Outputs Open

ICC2

Operating Current

13

27

13

27

15

30

mA

VIN~2.2V, Except
CEl <0.65V,
Outputs Open

500

pA

CE2<0.2V, TA;
70'e

0.65 -0.3

0.65

V

2.2

VCC

V

0.4

V

IOL ~2.0 mA

V

IOH~

ICCL[2] Standby Current

10

200

VIL

Input Low Voltage

-0.3

0.65 -0.3

VIH

Input High Voltage

2.2

Vcc

VOL

Output Low Voltage

VOH

Output High Voltage

2.2

VCC

0.4

0.4

2.4

2.4

2.4

-1.0 mA

Low Vce Data Retention Characteristics (For 51.01 L, 5101 L-l and 5101 L-3) TA; 0' C to 70' C
Symbol

Parameter

Min.

Typ.ll]

VDR

VCC for Data Retention

ICCDR1

5101 L or 5101 L·l Data Retention
Current

0.14

5101 L-3 Data Retention Current

0.70

ICCDR2

Max.

2.0

Units

Test Conditions

V
10

pA
CE2<0.2V

200

pA

VDR;2.0V,
T A ;70'C
VDR;2.0V,
TA~70'C

teDR

Chip Deselect to Data Retention Time

tR

o perat ion

Recovery Ti me

0

ns

tRC[3]

ns

NOTES:
1. Typical values are TA = 25'C and nominal supply voltage.
2.

Current through all inputs and outputs included in

3.

tRC = Read Cycle Time.

leel measurement.

6-106

5101 FAMILY
Low Vcc Data Retention Waveform

SUPPLY
VOLTAGE (Vee)

CHIP ENABLE ICE2)

Typical

G)

OV- -

Vs. Temperature

4.75V

®

VDR

G)
@

@

ICCDR

V,H
O.2V

----------------------- - -

TEMPERATURE

A.C. Characteristics

TA

= o°c to

70°C, Vee

re)

= 5V ±5%, unless otherwise specified.

READ CYCLE

Symbol

Parameter

5101L-l
Limits (ns)
Min.
Max.

5101L and
5101 L-3
Limits (ns)
Max.
Min.

5101-8
Limits (ns)
Min.
Max.

450

650

800

tRe

Read Cycle

tA

Access Time

450

650

800

teol

Chip Enable (CE 1) to Output

400

600

800

teo2

Chip Enable (CE 2) to Output

500

700

850

250

350

450

tOD

Output Disable to Output

tDF

Data Output to High Z State

0

tOHl

Previous Read Data Valid with
Respect to Address Change

0

0

0

tOH2

Previous Read Data Valid with
Respect to Chip Enable

0

0

0

450

650

800

130

0

150

0

200

WRITE CYCLE
twe

Write Cycle

tAW

Write Delay

130

150

200

tewl

Chip Enable (CE 1) to Write

350

550

650

tew2

Chip Enable (CE 2) to Write

350

550

650

tDW

Data Setup

250

400

450

tDH

Data Hold

50

100

100

twp

Write Pulse

250

400

450

tWR

Wr ite Recovery

50

50

100

tDS

Output Disable Setup

130

150

200

Capaci"tance[21T A

A. C. CONDITIONS OF TEST
Input Pulse Levels:

Input Pulse Rise and Fall Times:

20nsec

Timing Measurement Reference Level:
Output Load:
NOTES:

=

25° C, f

=

1 MHz

+0.65 Volt to 2.2 Volt

1.5 Volt

Symbol
C)N

Input Capacitance
(All Input Pins) V)N = OV

GoUT

Output Capacitance VOUT

1 TTL Gate and CL -- 100pF

1. Typical values are for T A =

25

0

e and nominal supply voltage.

2. This parameter is periodically sampled and is not 100% tested.

6-107

Limits (pF)

Test

~

OV

Typ.

Max.

4

8

8

12

5101 FAMILY

Waveforms
READ CYCLE

WRITE CYCLE
I+--------------twe--------------~
ADDRESS

ADDRESS

-

t CW1

------t

CE2

14--+-------- tewl ----.~~

OD--+---_
(COMMON 1/0)[11

DATA
IN

DATA
OUT

DATA IN

STABLE

---,--,.I+--------twP ____--1- t WR RW

NOTES:

1. 00 may be tied low for separate I/O operation.
2. During the write cycle, 00 is "high" for common I/O and
"don't care" for separate I/O operation.

6-108

M5101-4, M5101L-4
256 x 4 BIT STATIC CMOS RAM

•

Military Temperature
Range:
-55°C to +125°C

•

Ultra Low Standby
Current: 200 nA/Bit

•
•

Fast Access Time-BOOns
Single +5V Power Supply

•

CE2 Controls Unconditional
Standby Mode

•

Three-State Output

The Intel® M5101 is an ultra-low power 256 X 4 CMOS RAM specified over the _55°C to +125°C temperature range. The RAM
uses fully DC stable (static) circuitry and therefore requires no clocks or refreshing to operate. When deselected with CE21ow, the
M5101 draws from the single 5-volt supply only 200 microamps at 125°C.
The Intel® M5101 is fabricated with an ion-implanted, silicon gate, Complementary MOS (CMOS) process. This technology allows
the design and production of ultra-low power, high performance memories.
PIN CONFIGURATION

LOGIC SYMBOL

5101

5101

A,

v"

A,

A,

Absolute Maximum Ratings

Ambient Temperature Under Bias ... -6SoC to 135°C
Storage Temperature
_65°C to +150°C

A.

A,

A,

A,

..

A,

A,

A"

A,

Voltage On Any Pin
With Respect to Ground '

A,
A"
A,

00,

A,

"',

"',

aND

"',
DO,

"',

"',

DO,

-Q,3V to Vee +Q,3V

Maximum Power Supply Voltage

+7 .OV

Power Dissipation

1 Watt

DO,

0',

CO,

"'.

DO,

"',

DO,

*

'COMMENT:

DO,

Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device

at these or at any other condition above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PIN NAMES
Oi, 01.
A _~

OATAI'4PUT
APDIIESSINPUTS

OUTPUTPISA8LE
OO,_DO,DATAOUTPUT

IIIW

II~AOIWIIITE

V

INPUT

D. C. and Operating Characteristics for M5101-4, M5101L-4
TA = -55°C to 125°C, VCC = 5V ±5% unless otherwise specified.
Symbol

Parameter

IU[21

Input Current

ILOH[21

Output High Leakage

IlOl[21

Output Low Leakage

ICCl

Operating Current

ICC2

Operati ng Cu rrent

ICCl [21

Standby Current

Min.

Typ.[ll

Max.

Unit

Test Conditions

nA

VIN = 0 to 5.25V

2

/lA

CE 1 =2.2V, VOUT = VCC

2

/lA

CE 1 =2.2V, VOUT=O.OV

11

25

mA

VIN =VCC Except CE1 ";O.OlV
Outputs Open

20

32

mA

VIN = 2.2V Except CE 1 ";0.5V
Outputs Open

2

200

/lA

VIN =0 to VCC, Except
CE2"; 0.2V

8

I

Vil

Input "Low" Voltage

-0.3

0.5

V

VIH

Input "High" Voltage

Vcc-2.0

VCC

V

VOL

Output "Low" Voltage

0.4

V

10l =2.0mA

VO H

Output "High" Voltage

V

10H = 1.0mA

Vcc-2.0

NOTES: 1. Typical values are TA = 25°C and nominal supply voltage~_
6-109

2. Current through all inputs and outputs included in ICCl'

M5101-4, M5101L-4
Low VCC Data Retention Characteristics (For M5101 L -4) TA - - 55°C to 125°C
Symbol

Parameter

Typ.!1]

Min.

VOR

VCC for Data Retention

ICCOR

Data Retention Current

tCOR

Ch ip Deselect to Data Retention
Time

tR

Operation Recovery Time

Max.

Unit

~

4r~

Test Conditions

V

2.0

CE2 ';;;0.2V
2

200

VOR =2.0V

/lA
ns

0
tRC[2]

ns

NOTES: 1. Typical values are TA ~ 25°C and nominal supply voltage.
2. tRC ~ Read Cycle Time.

A.C. Characteristics for M5101-4, M5101L-4
READ CYCLE

TA = -55°C to 125°C, VCC = 5V ±5%, unless otherwise specified.

Symbol
tRC

Parameter

Min.

Read Cycle

Typ.

Max.

Unit

Test Conditions

ns

800

tA

Access Time

800

ns

tC01

Chip Enable (CE 1) to Output

700

ns

tC02

Chip Enable (CE2) to Output

850

ns

350
150

ns

too

Output Disable To Output

tOF

Data Output to High Z State

0

tOH1

Previous Read Data Valid with
Respect to Address Change

0

ns

tOH2

Previous Read Data Valid with
Respect to Chip Enable

0

ns

(See below)

ns

WRITE CYCLE
Symbol

Parameter

twc

Write Cycle

tAW

Min.

Typ.

Max.

Unit

800

ns

Write Delay

150

ns

tCW1

Chip Enable (CE1) To Write

550

ns

tcw2

Chip Enable (CE2) To Write

550

ns

tow

Data Setup

400

ns

tOH

Data Hold

100

ns

twp

Write Pulse

ns

tWR

Write Recovery

400
50

tos

Output Disable Setup

150

ns

ns

1 MHz

0.5 Volt to VCC-2.O Volt
20 nsec

Input Pulse Rise and Fall Times:
Timing Measurement Reference Level:
Output Load:

(See below)

Capaci°ta nce[31TA ~ 25°C, f ~

A. C. CONDITIONS OF TEST
I nput Pulse Levels:

Test Conditions

1 TTL Gate and CL

1.5 Volt
~

Symbol
CIN

100pF
GoUT

NOTE: 3. This parameter is periodically sampled and is not 100% tested.

6-110

Limits (pF)

Test
Input Capacitance
(All Input Pins) V IN

~

OV

Output Capacitance VOUT

~

OV

Typ.

Max.

4

8

8

12

~

M5101-4, M5101L-4

Waveforms
WRITE CYCLE
1 - - - - - - - - 'RC - - - - - - - 1

1--------

'WC-------~

ADDRESS

ADDRESS

- - - t CW1

---..j

CE2

CE,

I--lf----- tCW2 - - - - - - - 1

--f----..

00
(COMMON I/O) 111

00
(COMMON 1/0)121

DATA
IN

DATA
OUT

I----'w,-----I~--_+--

ROW

NOTES:

1. 00 may be tied low for separate I/O operation.
2. During the write cycle, 00 is "high" for common I/O and
"don't care" for separate I/O operation.

Low Vcc Data Retention

CD

SUPPLY VOLTAGE (Vee)

®
®

@

CHIP ENABLE (CE2)

w------------------

6-111

4.75V
VOR
VIH

O.2V

!!!!~Llltllla~ Aliy

inter

Para

• IS IS IIot.
• .....
mettlc limit a fmalspecif" .
s are Subject to IChat'Oll. Some
c allge.

2114
1024 X 4 BIT STATIC RAM

I

I

2114-2

2114-3

2114

2114L3

2114L

200

300

450

300

450

710mw

710mw

710mw

370mw

370mw

Max. Access Time (ns)
Max. Power Dissipation (mw)

Density 18 Pin Package
• High
Identical Cycle and Access Times
• Single
+5V Supply
• No Clock
or Timing Strobe Required
•
Completely
Static Memory
•

Directly TTL Compatible: All Inputs
• and
Outputs
Common
Input and Output Using
• Three-StateDataOutputs
Compatible with 3605 and 3625
• Pin-Out
Bipolar PROMs

The Intel® 2114 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel Silicon-Gate
MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and therefore
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out non destructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing are
important design objectives. The 2114 is placed in an 18-pin package for the highest possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
easy selection of an individual package when outputs are or-tied.
The 2114 is fabricated with Intel's N-channel Silicon-Gate technology - a technology providing excellent protection against
contamination permitting the use of low cost plastic packaging.
PIN CONFIGURATION
A.

Vee

A.

As

A,

A,

A.

As

1/01

A,

As

A3

As

A.

I/0,

A,

I/o,

As

I/O,

A,

I/O.

As

WE

A.

I/O,

A.

CS

0
A3
A ®
•®
As
CD
A.
A,
As

As

GND

BLOCK DIAGRAM

LOGIC SYMBOL

@

~Vcc

~GND
ROW
SELECT

MEMORY AR RAY
64 ROWS
64 COLUMNS

@

@

1/03

As

I/O,@

1/°4

I/o,@
I/o,@

WE

CS

PIN NAMES
AO-A9
WE

ADDRESS INPUTS

Vee POWER (+5V)

WRITE ENABLE

GND GROUND

CS

CHIP SELECT

o

1/0,-1/04 DATA INPUT/OUTPUT

6-112

= PIN NUMBERS

Jeer to change: orne

ABSOLUTE MAXIMUM RATINGS·

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . . . -10°Cto SO°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1.0W

D.C. AND OPERATING CHARACTERISTICS
TA = O°C to 70°C, Vcc = 5V ± 5%, unless otherwise noted.

SYMBOL

PARAMETER

2114-2,2114·3,2114
Min.
Typ. Max.

2114L3,2114L
Typ.
Min.
Max.

UNIT

CONDITIONS

III

Input Load Current
(All I nput Pins)

10

10

IlA

VIN = 0 to 5.25V

[lLOI

I/O Leakage Current

10

10

IlA

CS = 2.4V,
Vila = O.4V to Vcc

ICC1

Power Supply Current

SO

120

65

mA

V IN = 5.25V, 11/0 = 0 mA,
TA = 25°C

ICC2

Power Supply Current

90

135

70

mA

VIN = 5.25V, 1110 = 0 mA,
TA = O°C

VIL

Input Low Voltage

-0.5

O.S

-0.5

O.S

V

VIH

Input High Voltage

2.4

VCC

2.4

VCC

V

VOL

Output Low Voltage

0.4

V

10L = 2.1 mA

VOH

Output High Voltage

Vcc

V

10H = -1.0 mA

0.4
2.4

Vec

2.4

CAPACITANCE
TA = 25°C, f = 1.0 MHz
SYMBOL

MAX

UNIT

CI/O

Input/Output Capacitance

TEST

5

pF

Vila = OV

CIN

Input Capacitance

5

pF

VIN =OV

NOTE: This parameter is periodically sampled and not 100% tested.

6·113

CONDITIONS

:~~!~IIf4RY

2114 FAMILY
A.C. CHARACTERISTICS

TA

= 0 o C to 70

0

C, Vee

Im,ls are SUb' SPeCIfication ..
~ect to ch
•"ome

= 5V ± 5%, unless otherwise noted.

ange.

READ CYCLE [11
SYMBOL

2114-2
Min.
Max.

PARAMETER

tRe

Read Cycle Time

tA

Access Time

teo

Chip Selection to Output Valid

tex

Chip Selection to Output Active

0

tOTO

Output 3-state from Deselection

0

tOHA

Output Hold from Address Change

2114-3,2114L3
Max.
Min.
300

200

2114,2114L
Max.
Min.
450

UNIT
ns

200

300

450

ns

70

100

100

ns

0

0
40

10

0

80

10

0

ns
100

10

ns
ns

WRITE CYCLE [21
2114-2
2114-3, 2114L3
Max.
Max.
Min.
Min.

2114,2114L
Max.
Min.

twe

Write Cycle Time

200

300

450

ns

tw

Write Time

100

150'

200

ns

tWR

Write Release Time

20

0

0

toTW

Output 3-state from Write

0

tow

Data to Write Time Overlap

100

150

200

ns

tOH

Data Hold From Write Time

0

0

0

ns

SYMBOL

PARAMETER

40

0

80

NOTES: 1. A Read occurs during the overlap of a low CS and a high WE.
2. A Write occurs during the overlap of a low es and a low WE.

A.C. CONDITIONS OF TEST
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .. 0.8 Volt to 2.4 Volt
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . • . . . • . . . . . . . . . . . . 10 nsec
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 50 pF

6-114

0

UNIT

ns
100

ns

2114 FAMILY
WAVEFORMS
READ CYCLE (i)
_--------"---,. --

. --------------- tRC --" .,-

ADDRESS

~tcx- ,....,...,....-----,...,..,.,
OOUT-------------------------------------------i~~
WRITE CYCLE
---------------twc - - - - -

ADDRESS

CD

1------ ----tw--------I

~'"

OOUT»»»»»»

;

NOTES:

CD

WE is high for a Read Cycle.

@ tw is measured from the latter of CS or WE going low to WE going high.
@ WE must be high during all address transitions.
@ tWR is referenced to the high transition of WE.

DATA STORAGE
When WE is high, the data input buffers are inhibited to
prevent erroneous data from getting into the array. As
long as WE remains high, the data stored cannot be
affected by the address, Chip Select, or data 1/0 voltage
levels and timing transitions. The block diagram also
shows data storage cannot be affected by WE, the
addresses, nor the 1/0 ports as long as CS is high. Either
CS or WE by itself - or in conjunction with the other can prevent extraneous writing due to signal transitions.

Internal delays on the 2114 are established such that
address decoding propagates ahead of data inputs (keyed
by the Write time). Therefore, it is permissable to establish
the addresses coincident to the selection of a Write time,
but no later. If the Write time precedes the addresses, the
data in the previously addressed locations, or some other
location, may be inadvertently changed.
While it is important that the addresses remain stable for
the entire Write cycle, the data inputs are not required to
remain stable. Appropriate voltage levels will be written
into the cells as long as the data is stablefort ow at the end
of the Write time.

Data within the array can only be changed during a Write
time - defined as the overlap of CS low and WE low. To
prevent the loss of data, the addresses must be properly
established during the entire Write time plus t wR '

6-115

inter
2142
1024 X 4 BIT STATIC RAM

I

2142-2
200
525

Max. Access Time (ns)

I

Max. Power Dissipation (mw)

2142-3
300
525

High Density 20 Pin Package
• Access
Selections From 200-450ns
• IdenticalTime
Cycle
and Access Times
•
low Operating Power Dissipation
• .1mW/Bit
Typical
Single
+5V
Supply
•

2142
450
525

2142L2
200
370

2142L3
300
370

2142L
450
370

Clock or Timing Strobe Required
• No
Static Memory
• Completely
Directly
TTL
• and Outputs Compatible: All Inputs
Common Data Input and Output Using
• Three-State
Outputs

The Intel® 2142 is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using N-channel SiliconGate MOS technology. It uses fully DC stable (static) circuitry throughout - in both the array and the decoding - and
therefore requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not
required. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are
provided.
The 2142 is designed for memory applications where high performance, low cost, large bit storage, and simple interfacing
are important design objectives. It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply.
The 2142 is placed in a 20-pin package. Two Chip Selects (CS1 and CS2) are provided for easy and flexible selection of
individual packages when outputs are OR-tied. An Output Disable is included for direct control of the output buffers.
The 2142 is fabricated with Intel's N-channel Silicon-Gate technology against contamination permitting the use of low cost plastic packaging.

PIN CONFIGURATION

LOGIC SYMBOL

BLOCK DIAGRAM
A3

A6

Vee

AO

A5

A7

A,

A4

A2

A9

A3

0
@

@

A4

------0

0
A5 - CD
A6

1/°1

AS

a technology providing excellent protection

RDW
SELECT

MEMORY ARRAY
64 ROWS
64 COLUMNS

Vee

@

- - . - : > GND

@

1/02
CS2

OD

A,

A7

AO

I/O,

A5

A8--

@

A,

1/02

A6

A2

1/03

A7

CS"l

1/04

AB

1/03

@
1/01

WE"

@

1/04

1/02 - - - -

A9
WE

cs

INPUT

DATA

@

CS 00

1/03 ~---~++~~~-4

CONTROL

@
1/04 -

PIN NAMES
AO~A9

ADDRESS INPUTS

OD

OUTPUT DISABLE

WE

WRITE ENABLE

Vee

POWER {+5vl

CS1, CS2

CHIP SELECT

GND

GROUND

I/O, 1/04

DATA INPUT/OUTPUT

o

= PIN NUMBERS

DD

INTEL CORPO RATION ASSUMES NO RESPONS!!Hl!TY FO R THE USE
INTEL CORPORATION, 1977

©

a F ANY CIRCUITRY OTHER THAN CI RCUlTRY EMBODiCD IN AN INTEl PRODUCT. rw OTHER CiRCUlT PATENT UCEr~SES ARE iMPUED.

6·116

APRIL 1977

2142 FAMILY
ABSOLUTE MAXIMUM RATINGS*
Maximum Ratings" may cause permanent damage
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . . . -10°C to SO°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin
With Respect to Ground . . . . . . . . . .. -0.5V to +7V
Power Dissipation
. . . . . . . . . . . . . . . 1.0W
. . . . . . . . . . . . . . . . . . . . . 10mA
D.C. Output Current

D.C. AND OPERATING CHARACTERISTICS
TA

= o°c to

70°C, Vcc

SYMBOL

= 5V ± 5%,

unless otherwise noted.

PARAMETER

2142-2, 2142-3, 2142
Min. Typ.llJ Max.

2142L2, 2142L3, 2142L
Min. Typ.fl1 Max.

UNIT

CONDITIONS

III

Input Load Current
(All Input Pins)

10

10

f.lA

VIN = 0 to 5.25V

IILOI

I/O Leakage Current

10

10

f.lA

CS = 2AV,
Vila = O.4V to Vcc

ICCl

Power Supply Current

95

65

mA

VIN = 5.25V, Ilia = 0 mA,
TA = 25°C

ICC2

Power Supply Current

100

70

mA

VIN = 5.25V, Ilia = 0 mA,
TA = O°C

SO

V il

Input Low Voltage

-0.5

O.S

-0.5

O.S

V

VIH

Input High Voltage

2.0

6.0

2.0

6.0

V

10l

Output Low Current

2.1

10H

Output High Current

losl2J

Output Short Circuit
Current

6.0

-104

2.1
-1.0

-1.4

40

mA

Val = OAV

-1.0

mA

VOH = 2AV

40

mA

Vila = GND to VCC

6.0

NOTE: 1. Typical values are for T A ~ 25° C and Vee ~ 5.0V.
2. Duration not to exceed 30 seconds.

CAPACITANCE
TA = 25°C, f = 1.0 MHz
SYMBOL

TEST

MAX

UNIT

CONDITIONS

CliO

Input/Output Capacitance

5

pF

Vila = OV

CIN

Input Capacitance

5

pF

VIN = OV

NOTE:

This parameter is periodically sampled and not 100% tested.

A.C. CONDITIONS OF TEST
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. O.S Volt to 2.4 Volt
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nsec
Input and Output Timing Levels. . . . . ..
Output Load

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Volts

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and C l = 100 pF

6-117

2142 FAMILY
A.C. CHARACTERISTICS
READ CYCLE

TA =

oOe to

70 o e, Vee = 5V ± 5%, unless otherwise noted.

(1)
2142-2,2142L2
Min.
Max.

PARAMETER

SYMBOL

Read Cycle Time

tRe
tA

Access Time
Output Enable to Output Valid

toox

Output Enable to Output Active

teo

Chip Selection to Output Valid
Chip Selection to Output Active
Output 3-state from Disable

tOHA

Output Hold from Address Change

ns

300

450

ns

70

100

120

ns

120

ns

20

20

ns

100

70

tOTo

UNIT

200

20

tex

2142,2142L
Min.
Max.
450

300

200

too

WR ITE CYCLE

2142-3,2142L3
Min.
Max.

20

ns

20

20
60

50

ns

100

80
50

50

ns

[2)

SYMBOL

2142-2, 2142L2 2142-3, 2142L3
Min.
Max.
Max.
Min.

PARAMETER

2142,2142L
Min.
Max.

UNIT

twe

Write Cycle Time

200

300

450

ns

tw

Write Time

120

150

200

ns

tWR

Write Release Time

0

0

0

tOTo

Output 3-state from Disable

tow

Data to Write Time Overlap

120

150

200

tOH

Data Hold From Write Time

0

0

a

60

ns
100

80

ns
ns

-- ---ns

NOTES:

CS and a high WE.
2. A Write occurs during the overlap of a low CS and a low WE.
1. A Read occurs cluring the overlap of a low

WAVEFORMS
READ CYCLE@>

WRITE CYCLE

.

'we
ADDRESS

__

J~

_______________

~~'

_____

ADDRESS

~
~

tWR- ~

OD

,\\\\,\\

U
~tOTD

cs, \\\
cs,

__

(/ / / / / / / /

\\\ \' \\'

~\ \

/11 'III 'I I.

\\\\\\

~-'w~

DOUT

------------4t==~

,\ \ \ ,\ \
DOUT

NOTES:

'DW--/-'DH

@) WE is high for a Read Cycle.

®

I

WE must be high during all address transitions.

D,N

6-118

------,r~~~~.11t2ix&x."..,xQ2X)

2142 FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
1.2

1.2

1. 1

1.1

1.0

-

I'-..

fil

NO.9

:::;

«

~
o
z

NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE

---

1.0

r-- r---

:J

fil

N

0.9

"

0.8

:::;
:;
a:

0.8

0

z

0.7

f.--- ..-

0.7

0.6

0.6

0.5

0.5

4.50

5.00

4.75

5.25

5.50

o

20

Vee (V)

NORMALIZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE

~
a:
o
z

O.

1. 1

V

V

1.

II

9r----

fij
N
:::;
~

0.8

a:

oz

0.7
0.6

o.

:~

0.8

~ b"

r--

O. 7
O. 6

O. 5

100

200

300

400

500

20

600

OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
40

30

30

~"-

10

o
o

1
~

'"

""-

40

60

OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE

40

20

80

1. 2

J...,..--:-"

1. 1
1.0

60

I"CI

NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE

1.2

:J
@
N
:::;

40
TA

20

10

~

/

V

/'

~

V

o
o

VOL (V)

VOH (V)

6-119

80

intel~
2104A FAMILY
4096 x 1 BIT DYNAMIC RAM
2104A-2

Max. Access Time (ns)

150

200

250

300

Read, Write Cycle (ns)

320

320

375

425

35

32

30

30

Max. IDD (mA)

2104A-3

2104A-4

2104A-1

Period: 2 ms
Highest Density 4K RAM Industry Stan• dard
• Refresh
16 Pin Package
On-Chip Latches for Addresses, Chip
• Select
and Data In
Low
Power
4K
RAM
• All Inputs Including Clocks TTL
Simple Memory Expansion: Chip Select
• Compatible
• Output is Three-State, TTL Compatible;
• Data is Latched and Valid into Next Cycle
±10% Tolerance on All Power Supplies
• +12V,
+5V, -5V
• Compatible with Intel® 2116 16K RAM
The Intel® 2104A is a 4096 word by 1 bit MOS RAM fabricated with N-channel silicon gate technology for high performance
and high functional density.
The efficient design of the 2104A allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin
package provides the highest system bit densities and is compatible with widely available automated handling equipment.
The use of the 16 pin package is made possible by multiplexing the 12 address bits (required to address 1 of 4096 bits) into
the 2104A on 6 address input pins. The two 6 bit address words are latched into the 21 04A by the two TTL clocks, Row
Address Strobe (RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the
multiplexing technique while maintaining high performance.
A new unique dynamic storage cell provides high speed along with low power dissipation and wide voltage margins. The
memory cell requires refreshing for data retention. Refreshing is most easily accomplished by performing a read cycle at
each of the 64 row addresses every 2 milliseconds.
The 21 04A is designed for page mode operation, "RAS-only refreshing," and "CAS-only deselection." Thus it is compatible
with the Intel® 2116, 16K RAM.

PIN CONFIGURATION

LOGIC DIAGRAM

v••

Vss

Ao

D'N

CAS

A,

WE

A,

DOUT

AAS

cs

""

A,

A,

A,

A,

""

BLOCK DIAGRAM

D'N

A,
A,
As

DOUT

Vee

VOD.

PIN NAMES
Ao

- VBB

4096 BIT

ADDRESS INPUTS

WE

WRITE ENABLE

CAS
CS

COLUMN ADDRESS STROBE

POWER (-5V)

o,N
Dour

DATA IN

DATA OUT

V••
Vee
Voo
Vss

lIAS

ROW ADDRESS STROBE

-As

CHIP SELECT

STORAGE ARRAY

-Von
-Vee

POWER (+5V)

_GND

POWER (+12V)

GROUND

CLOCK

(RAS) _-.,..,;G;,;;E"'NE"'A..,;AT...;O"'A"'N""O...,;'....

6-120

2104A FAMILY
ABSOLUTE MAXIMUM RATINGS·

'COMMENT:

Ambient Temperature Under Bias ..... -10°Cto +80°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin Relative to VBB
(Vss - VBB :;;. 4.5V) . . . . . . . . . . . . . . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Data Out Current . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Stresses above those listed under "Absolute Maximum Rat·
ings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Ex·
posure to absolute maximum rating conditions for extended
periods may affect device reliability.

D.C. AND OPERATING CHARACTERISTICS[1]
Til. ~ 0° to 70°C, Voo ~ +12V ±10%, Vcc ~ +5V ±10%, VBB ~ -5V ±1 0%, Vss ~ OV, unless otherwise noted.
Limits
Symbol

Parameter

Min.

Typ.(2)

Max.

Unit

Conditions

III

Input Load Current (any input)

10

pA

VIN ~ V IL MIN to VIH MAX

IILOI

Output Leakage Current for
High Impedance State

10

pA

Chip deselected: RAS and CAS at VIH
VOUT ~ 0 to 5.5V

1001 [3J

V 00 Standby Current

0.7

2

mA

Voo ~ 13.2V

0.7

1.5

mA

Voo ~ 12.6V

5

50

IJ.A

Voo

24

35

mA

2104A·1

tCYC ~ 320 ns

22

32

mA

2104A·2

tCYC ~ 320 ns

20

30

rnA

2104A·3,4

tCYC ~ 375 ns

160

400

IJ.A

Device Selected. Min cycle time.

10

pA

25

mA

2104A·1,2

tCYC ~ 320 ns

2104A·3,4

tCYC ~ 375 ns

ISB1

V BB Standby Current

1002[3J

Operating VOO Current
(Device Selected)

ISB2

Operating VBB Current

ICC1[4J

Vcc Supply Current when
Deselected

1003

Operating Voo Current
(RAS·only cycle)

VIL.

Input Low Voltage (any input)

12
10
-1.0

22

mA

0.8

V

~

13.2V

VIH

Input High Voltage

2.4

7.0

V

VOL.

Output Low Voltage

0.0

0.4

V

IOL

VOH

Output High Voltage

2.4

Vcc

V

IOH ~ -5 mA

CAPACITANCE [6] TA

Symbol

~

3.2 mA

= 25°C

Test

Typ.

Max.

Unit

Conditions

CI1

Input Capacitance (Ao-A5), DIN, CS

3

7

pF

VIN ~ Vss

CI2

Input Capacitance RAS, WR ITE

3

7

pF

VIN = Vss

Co

Output Capacitance (DOUT)

4

7

pF

VOUT = OV

CI3

Input Capacitance CAS

6

7

pF

VIN ~ VSS

Notes:

CAS and RAS at VIH.
Chip deselected prior
to measurement.
See Note 5.

1. All voltages referenced to VSS. The only requirement for the sequence of applying voltages to the device is that VDD. Vee. and
VSS should never be O.3V or more negative than VBB. After the application of supply voltages or after extended periods of operation without clocks, the device must perform a minimum of one initialization cycle (any vaiid memory cycles containing both RAS
and CAS) prior to normal operation.
2. Typical values are for T A = 25° C and nominal power' supply voltages.

3. The 100 current flows to VSS.
4. When chip is selected VCC supply current is dependent on output loading.

Vee is connected to output buffer only.

5. The chip is deselected; i.e., output is brought to high impedance state by CAS-only cycle or by a read cycle with
6. Capacitance measured with Boonton Meter.

6-121

Cs at VIH.

2104A FAMILY
A.C.CHARACTERISTICS[1]
TA=O°C to 70°C,VDD =12V ±10%,Vcc=5V ±10%, VBB=-5V ±10%, VSs=OV,unless otherwise noted.

READ, WRITE, AND READ MODIFY WRITE CYCLES
Parameter

Symbol

2104A·l
Min.
Max.

2104A-2
Min.
Max.

2

2104A·3
Min.
Max.

2104A·4
Min.
Max.

2

2

2

tREF

Time Between Refresh

tRP

RAS Precharge Time

100

115

115

125

tcp

CAS Precharge Time

60

80

110

110

tRCL[2]

RAS to CAS Leading Edge Lead Time

20

tCRP

CAS to RAS Precharge Time

tRSH

50

25

70

35

110

80

Unit
ms
ns
ns

135

ns

a

a

a

a

ns

RAS Hold Time

100

130

140

165

ns

tCSH

CAS Hold Time

150

200

250

300

ns

tAR

RAS to Address or CS Hold Time

95

120

160

215

ns

tASR

Row Address Set·Up Time

a

Column Address or CS Set· Up Time

-5

a
a

a
a

ns

tASC

a
a

tRAH

Row Address Hold Time

20

25

35

80

ns

tCAH

Column Address or CS Hold Time

45

50

50

80

tT

Rise or Fall Time

tOFF

Output Buffer Turn·Off Delay

80

ns

tCAC I3l
tRAC I3l

Access Time F rom CAS

100

130

140

165

ns

Access Time From RAS

150

200

250

300

ns

50
0

-

50

50

a

60

50

a

60

ns
ns
50

0

ns

READ CYCLE
2104A·l

Parameter

Symbol

Min.

Max.

2104A·2
Min.

Max.

Max.

Max.

Unit

Random Read or Write Cycle Time

320

tRAS

RAS Pulse Width

150

tCAS

CAS Pulse Width

100

130

140

165

ns

tRCS

Read Command Set·Up Time
Read Command Hold Time

a
a

a
a

a
a

ns

tRCH
tDOH

a
a
32

32

32

32

jJ.s

32000

200

375

2104A·4

Min.

tRC

Data Out Hold Time

320

2104A·3

Min.

32000

250

ns

425
32000

300

32000

ns

ns

WRITE CYCLE[4]
2104A·l
Symbol

Parameter

Min.

Max.

2104A-2
Min.

Max.

2104A·3

Min.

Max.

2104A·4
Min.

Max.

Unit

tRC

Random Read or Write Cycle Time

320

tRAS

RAS Pulse Width

150

tCAS

CAS Pu Ise Width

100

130

140

165

twcs

Write Command Set· Up Time

a

a

a

0

ns

twCH

Write Command Hold Time

55

75

75

80

ns

twCR

Write Command Hold Time Referenced to RAS

105

145

185

215

ns

twp

Write Command Pulse Width

45

55

75

80

ns

tRWL

Write Command to RAS Lead Time

100

130

140

150

ns

tCWL

Write Command to CAS Lead Time

100

130

140

150

ns

tDS

Data·ln Set·Up Time

a

a

a

a

ns

tDH

Data·ln Hold Time

55

75

75

80

ns

tDHR

Data-In Hold Time Referenced to RAS

105

145

185

215

ns

Notes:

320
32000

200

375
32000

250

425
32000

300

ns
32000

ns
ns

1. All voltages referenced to VSS. Minimum timings do not allow for tT or skews.
2. CAS m!..!s~maln at ViH a minimufTl of tRCL MIN after RAS switches to VIL. To achieve the minimum guaranteed access time
(tRAC), CAS must switch to VIL at or before tRCL of tRAC - tT - tCAC as described in the Applications Information on page 2-45.
tRCL MAX is given for reference only as tRAC _ tCAC'
3. Load = 2 TTL and 100 pF. See Applications Information.
4. In a write cycle DOUT latch will contain data written into ogll. In a read-modify-write cycle DOUT latch will contain data read
from ce!!. !f WE goes low sftei CAS and p,-io( to tCAC, DOUT is indeterminate.

6-122

2104A FAMilY
WAVEFORMS
READ CYCLE

V,H
RAS

v"

V,H
CAS

V"
~H---"""
ADDRESSES

V" - - - ' - '

"f-o-+---Ji

V,H-------t_-----=

cs

V,H--------t_------~~--------t_----------------------~I

V,,-----------i======_~
VOH------------------------------~~~G0

HIGH IMPEDANCE

VOL------------------------------------~QD

WRITE CYCLE
tRC
V,H
RAS

CD

7

0

v"

CAS

I

ROW)C) -

I
ADDRESSES

V"

t ASR : -

CD
0

tRSH

/, //,

CD ~\\\ 0

V"

--tRAH-1

-

\ -0

V,H
CS

'cAS

I---1:.cAH-------

t ASC

ADDRESS

X

COLUMN
ADDRESS

tAR

'wCR

t ASC

- - tcAH-------'

/

t RWL

tCWL
-lwCH-

~

V,H

\.

WE

v,L
V,H
D'N

V"
IIoH
"oUT

VOL

(See page 2-44 for notes)

- -'tcRP------

'cSH

-----~CL -----I

V,H

V,H

·1~tRP~

'RAS

------'twCS-------

'0

,

'wp - - - - -

/

tDHR

t.:=.-'os~ ----------- toH~

K

XCD0
t RAC

tOFF~
~@

¥0

teAc

HIGH IMPEDANCE

®

1~'cP-----1'-

2104A FAMILY
A.C.CHARACTERISTICS[1]
TA = 0 0 to 70°C, VDD=12V ±10%, Vcc=5V ±10%, VBB=-5V ±10%, VsS=OV,unless otherwise noted.

READ-MODIFY-WRITE CYCLE
2104A-l
Min.
Max.

2104A-2
Min.
Max.

2104A-3
Min.
Max.

tRWC

Read Modify Write Cycle Time[2]

350

445

505

575

tCRW

RMW Cycle CAS Width

200

260

280

315

ns

tRRw

RMW Cycle RAS Width

250

330

390

450

ns

tRWL

RMW Cycle RAS Lead Time

100

130

140

150

ns

tCWH

RMW Cycle CAS Hold Time

250

330

390

450

ns

tCWL

Write Command to CAS Lead Time

100

130

140

150

ns

twp

Write Command Pulse Width

45

55

75

80

ns

tRCS

Read Command Set-Up Time

0

0

0

0

ns

Parameter

Symbol

2104A-4
Min.
Max.

Unit
ns

tMOD

Modify Time

0

tDS

Data-In Set-Up Time

0

0

0

0

ns

tDH

Data-In Hold Time

55

75

75

80

ns

Notes:

1. All voltages referenced to

0

10

10

0

10

0

10

Vss.

2. The minimum cycle timing does not allow for tT or skews.

WAVEFORMS
READ-MODIFY-WRITE CYCLE

\-

,"we

~RW~----~---~·--

.

I --------------t
• RcL - -

tCRW

1/
_ - t R W L _________

RAH

tASR:-----1
VIL

0
0

I

K:X

---j-tCAH

tAser-

ROW
ADDRESS

j

V ,H
VIL

J

I

H

VIL

WE

---------------tcwl - - - -

i-v

0~--

V,H

CS

_ _ tcp________._._

l(

COLUMN
ADDRESS

_ _ _ _ -tAR

\.
-tcRP-

tCWH

0K.\\\ 0

:I

II-t
V ,H

.
tAP-----lo

V

0t 0

ADDRESSES

r-

-~PV

tRcsl-r

0 0/

tMoD~

-I
X0

tDH

- t DS

V ,H

D'N
VIL

0

-----tRAc
~---tCAC--~

V aH

tOFFI---i

DOUT

Val

"'Ii. ®

HIGH
IMPEDANCE

DATA IN
VALID

K

i

l'®

VALID
DATA OUT

~0

Notes: 1,2. VIHMIN and VILMAX are reference levels for measuring timing of input signals.
3,4. VOHMIN and VOLMAX are reference levels for measuring timing of DaUT.
5.
In a write cycle DaUT latch will contain data written into cell. In a read-modify-write cycle DaUT latch will contain data
read from cell. If WE goes low after

CAS ~md

prior to tCAC,DOUT is indeterminate.

6- i24

Ils

2104A FAMILY
TYPICAL CHARACTERISTICS

40

TYPICAL 1882 AND 1002

TYPICAL 1882 AND 1002

VS. TEMPERATURE

VS. CYCLE TIME

r---r-------,--~---

800

12.0V
'" -S.OV

f---t----j--

VBB

tRCL

'" 60ns

tRP

'" 125 n~ ~

600

400

200

___ ~

10

I

30

~

j

n

~

Voo '" lO.BV
VSB = -S.5V

100

-s.ov
600

~

20

~ ~2
10

r-25

=

'" 2S"C
TA
teAs '" 165 ns
tRCl ,. 80ns ' _

1'-

oL---J--~-~-_~_ _-"o

o

~------,--------,--~---

Voo '" 12.0V

tCYCLE = 375 JH

30

VS. TEMPERATURE
250

40

~

VOD
Vaa

TYPICAL ACCESS TIME

IB82

o
200

400

TEMPERATURE (C)

400

--

!

j ;

200

o

150

100

5OL---~--~-~--~

o

1000

600

F------j----j----t---

25

15
TEMPERATURE (OC)

TCYCLE Ins)

APPLICATIONS
ADDRESSING
Two externally applied negative going TTL clocks. Row
Address Strobe (RAS). and Column Address Strobe
(CAS). are used to strobe the two sets of 6 addresses into
internal address buffer registers. The first clock. RAS,
strobes in the six low order addresses (Ao-As) which
selects one of 64 rows and begins the timing which
enables the column sense amplifiers. The second clock,
CAS, strobes in the six high order addresses (A6-AI d to
select one of 64 column sense amplifiers and Chip Select
(CS) which enables the data out buffer.
An address map of the 21 04A is shown below. Address "0'"
corresponds to all addresses at VIL. All addresses are
sequentially located on the chip.
2104A Address Map
4032

0

ffi

C

§

ARRAY
(DATA IN)

c

~

a:
4095

63

SENSE AMPLIFIER

system access time since the decode time for chip select
does not enter into the calculation for access time.
Both the RAS and CAS clocks are TTL compatible and do
not require level shifting and driving at high voltage MaS
levels. Buffers internal to the 2104A convert the TTL level
signals to MaS levels inside the device. Therefore, the
delay associated with external TTL-MaS level converters
is not added to the 2104A system access time.

READ CYCLE
A Read cycle is performed by maintaining Write Enable
(WE) high during CAS. The output pin of a selected device
will unconditionally go to a high impedance state
immediately following the leading edge of CAS and
remain in this state until valid data appears at the output at
access time. The selected output data is internally latched
and will remain valid until asubsequent CAS isgiventothe
device by a Read, Write, Read-Modify-Write, CAS only or
Refresh cycle. Data-out goes to a high impedance state for
all non-selected devices.
Device access time, tACC, is the longer of two calculated
intervals:

COLUMN DECODER

1. tACC = tRAc OR

DATA CYCLES/TIMING
A memory cycle begins with addresses stable and a
negative transition of RAS. See the waveforms on page 4.
It is not necessary to know whether a Read or Write cycle
is to be performed until CAS becomes valid.

2.

tACC = tRCL +IT + tCAC

Access time from RAS, tRAc, and access time from CAS,
!cAC, are device parameters. Row to column address
strobe lead time, tRCL, and transition time, IT, are system
dependent timing parameters. For example, substituting
the device parameters of the 2104A-4 and assuming a
TTL level transition time of 5 ns yields:

Note that Chip Select (CS) does not have to be valid until
the second clock, CAS. It is, therefore, possible to start a
memory cycle before it is known which device must be
selected. This can result in a significant improvement in

3. IACC = tRAC = 300ns for 80 nsec ,;;; tRCL ,;;; 130nsec
OR
4. tACC
6-125

= tRCL + IT + !cAC =tRCL +170ns for tRCL>130ns.

2104A FAMILY

Note that if 80 nsec.;;tRcL';;130 nsec, device access time is
determined by equation 3 and is equal to tRAC. If tRcL>130
nsec, access time is determined by equation 4. This 50ns
interval (shown in the tRCL inequality in equation 3) in
which the falling edge of CAS can occur without affecting
access time is provided to allow for system timing skew in
the generation of CAS. This allowance for a tRCL skew is
designed in at the device level to allow minimum access
times to be achieved in practical system designs.

Write, or Read-Modify-Write cycle. A device is deselected
by 1) driving CS high during a Read, Write, or ReadModify-Write cycle or 2) performing a CAS Only cycle
independent of the state of CS.

REFRESH CYCLES

WRITE CYCLE
A Write Cycle is generally performed by bringing Write
Enable (WE) low before CAS. DouTwili bethe data written
into the cell addressed. If WE goes low after CAS and prior
to tCAC, DouT will be indeterminate.

Each of the 64 rows internal to the 2104A must be
refreshed every 2 msec to maintain data. Any data cycle
(Read, Write, Read-Modify-Write) refreshes the entire
selected row (defined by the low order row addresses).
The refresh operation is independent of the state of chip
select. It is evident, of course, that if a Write or ReadModify-Write cycle is used to refresh a row, the device
should be deselected (CS high) if it is desired not to
change the state of the selected cell.

RAS/CAS TIMING
READ-MODIFY-WRITE CYCLE

The device clocks, RAS and CAS, control operation of the
2104A. The timing of each clock and the timing
relationships of the two clocks must be understood by the
user in order to obtain maximum performance in a
memory system.

A Read-Modify-Write Cycle is performed by bringing
Write Enable (WE) low after access time, tRAC, with RAS
and CAS low. Data in must be valid at or before the falling
edge of WE. In a read-modify-write cycle DouT is data read
and does not change during the mOdify-write portion of
the cycle.

The RAS and CAS have minimum pulse widths as defined
by tRAS and teAS respectively. These minimum pulse
widths must be maintained for proper device operation
and data integrity. A cycle, once begun by driving RAS
and/or CAS low must not be ended or aborted prior to
fulfilling the minimum clock signal pulse width(s). A new
cycle must not begin until the minimum precharge time,
tRP, has been met.

CAS ONLY (DESELECT) CYCLE
In some applications, it is desirable to be able to deselect
all memory devices without running a regular memory
cycle. This may be accomplished with the 2104A by performing a CAS-Only Cycle. Receipt of a CAS without RAS
deselects the 2104A and forces the Data Output to the
high-impedance state. This places the 2104A in its lowest
power, standby condition. 100 will be about twice 1001 for
the first cycle of CAS'only deselection and 1001 for any
additional CAS·only cycles. The cyc~im...i!!.l! and CAS
timing should be just as if a normal RAS/CAS cycle was
being performed.

PAGE MODE OPERATION
The 2104A is designed for page mode operation and is
presently being characterized for that mode. Specifications will be available at a later date.

POWER SUPPLY
CHIP SELECTION/DESELECTION

Typical power supply current waveforms versus time are
shown below for both a RAS/CAS cycle and a CAS only
cycle. 100 and IBB current surges at RAS and CAS edges
make adequate decoupling of these supplies important. Due
to the high frequency noise component content of the cur·
rent waveforms, the decoupling capacitors should be low
inductance, ceramic units selected for their high frequency
performance.

The 2104A is selected by driving CS low during a Read,

RAS/CAS CYCLE

RAS

V'H
VOl

CAS

V'H
VOl

~.
(mA)

-t
+2:
-20

I

CAS ONLY CYCLE

I

100 200 300 400 500 600 700 800 900 1oo0(ns)

-,

- -

J

Il- r-~

,AI .... LA..

VI

\f-

lJ r-

It is recommended that a 0.1 J..IF ceramic capacitor be can·
nected between Voo and Vss at every other device in the
memory array. A 0.1 J..IF ceramic capacitor should also be
connected between V BB and V ss at every other device
(preferably the alternate devices to the Voo decoupling).
For each 16 devices, a 10 J..IF tantalum or equivalent capacitor should be connected between Voo and Vss near the
array. An equal or slightly smaller bulk capacitor is also
recommended between VBB and Vss for every 32 devices.

~

·40

II

I

I. I I I I

Ii

A 0.01 J..IF ceramic capacitor is recommended between Vee
and Vss at every eighth device to prevent noise coupling to
the Vee line which may affect the TTL peripheral logic in
the system.
TYPICAL SUPPL V CIJRf'EI\!TS VR T!ME

6-126

2104A FAMILY

Due to the high frequency characteristics of the current
waveforms, the inductance of the power supply distribution
system on the array board should be minimized. It is
recommended that the V DD , Vss, and Vss supply lines be

o

B ,

• B ,

00 ,

gridded both horizontally and vertically at each device in
the array. This technique allows use of double·sided circuit
boards with noise performance equal to or better than
multi·layered circuit boards.

o

0 ,

oB,

0 0 ,

~~~==.~5i§·==P~~~~~p~~~·==p~~~·==.~~~.~,~~~·=='~~;m• sio • 0 •
• a •
• 0'. • B 0° 0 0 • c O B .

••

••

••

••

••

••

••

••

=~~~~~VSS
VCC

VBB

DIN

DOUT

DECOUPLING CAPACITORS
o

= 0.1

B

= 0.1 pF VBS TO Vss

C

=

MF to VDD TO Vss

0.01 MF VCC TO Vss

6-127

inter
2107B
4096 BIT DYNAMIC RAM
Access Time
Read,Write Cycle
RMW Cycle

2107B
200ns
400ns
520ns

2107B-4
270ns
470ns
590ns

2107B-5
300ns
590ns
750ns

• Address Registers Incorporated on the
Chip
• Simple Memory Expansion - Chip Select
Input Lead
• Fully Decoded - On Chip Address
Decode
• Output is Three State and TTL Compatible
• Industry Standard 22-Pin Configuration

•
•
•
•

Low Cost Per Bit
Low Standby Power
Easy System Interface
Only One High Voltage
Input Signal - Chip Enable
• TTL Compatible - All Address, Data,
Write Enable, Chip Select Inputs
• Refresh Period-2ms for 2107B,
2107B-4, 1 ms for 2107B-5 @70°C

The Intel"'2107B is a 4096 word by 1 bit dynamic n-channel MaS RAM_ It was designed for memory applications where
very low cost and large bit storage are important design objectives_ The 2107B uses dynamic circuitry which reduces the
standby power dissipation_
Reading information from the memory is non-destructive_ Refreshing is most easily accomplished by performing one read
cycle on each of the 64 row addresses_ Each row address must be refreshed every two milliseconds. The memory is refreshed whether Chip Select is a logic one or a logic zero.
The 2107B is fabricated with n-channel silicon gate technology. This technology allows the design and production of
high performance, easy to use MaS circuits and provides a higher functional density on a monolithic chip than other
MaS technologies. The 2107B uses a single transistor cell to achieve high speed and low cost. It is a replacement for
the 2107A.

PIN CONFIGURATION

LOGIC SYMBOL

21078

.

v..

v"

AO
A,
A,
A,
A.
A;
A,
A,
A,

A.

A"

A,

A"

II,;

Eli

Voo

0,.

CE

Dou,

Ne

..,

..

A,

Vee

A)

A"
A"

WE

cs
PIN NAMES

~ A,,-A l1

0"

.

A;

A,

BLOCK DIAGRAM

21078

- - - ,--

Dour

CE

--

~_,,-~

ADDRESS INPUTS'

V••

POWER i-

CE

CHIP ENABLE
CHIP SELECT

Vee
VOD

POWER i+

CS

V••

GROUND

DIN

DATA INPUT

t5Ou.

DATA

NC

NOT CONNECTED

WE

POWER 1+

~

OUTPu~wi._wim~EN AB~

6-128

A"
A,

~

A,

~

A,

,~

.-<>

~

ROW DECODE

"nd BUF FER
REG!STER

64

MEMORY
ARRAY

64 x 64

"'0

+-<> Vee
.-<>

V"

.-<>

"so

21078 FAMILY

Absolute Maximum Ratings *
OOC to lO"C

Temperature Under Bias

-650 C to + 1500 C

Storage Temperature

All I nput or Output Voltoges with Respect to the most Negative Supply Voltage, Vss

+25V

Supply Voltages V oo , Vcc, and VSS with Respect to VSS

+20V to -0.3V

to

Power Dissipation

-0.3V

1.25W

'COMMENT

Stresses above those listed under IIAbsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
I!

only and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this spedfication isnot implied. Exposure to absolute maximum rating conditions for ex tended periods may affect device reliabihty.

D.C. and Operating Characteristics
T A = ODC to 70DC, V DD = +12V ±5%, vcc = +5V ±10%, V BB [1] = -5V ±5%, Vss = OV, unless otherwise noted,
Symbol

Parameter

Limits

Unit

Conditions

Typ.[2]

Max.

Input Load Current
(all inputs except CE)

.01

50

I lC

Input Load Current

.01

2

J1A

VIN = Vil MIN to VIH MAX

Illol

Output Leakage Current
for high impedance state

.01

10

J1A

CE = VILe or CS = V IH
Va = OV to 5.25V

J1A

CE = -1V to +,6V

60

rnA

CE = VIHC, CS = VIL

III [6]

Min.

J1A

VIN = VIL MIN to VIH MAX
CE = VILC or VIHC

1001

VOO Supply Current
during CE off[3]

1002

Voo Supply Current
during CE on

100Av

Average Voo Current

38

54

rnA

CS = V IL ; T A = 25°C; Min cycle time,
Min tCE

ICCl [4]

Vcc Supply Current
du ring CE off

.01

10

J1A

CE = VILC or CS = V IH

5

110

200[5]

-

-

19B

V SB Supply Current

400

J1A

V il

Input Low Voltage

-1,0

0,6

V

tT = 20ns, Vile

VIH

Input High Voltage

2.4

Vcc + 1

V

tT= 20ns

V

VllC

CE Input Low Voltage

-1.0

+1,0

VIHC

CE Input High Voltage

Voo-l

V oo +l

V

Val

Output Low Voltage

0,0

0.45

V

IOl = 2.OmA

VO H

Output High Voltage

2.4

VCC

V

IOH

~

+1.0V

= -2,OmA

NOTES;
1. The only requirement for the sequence of applying voltage to the device is that Voo. Vee. and VSS should never be .3V or more
negative than Vaa.
2. Typical values are for TA = 25°e and nominal power supply voltages.
3. The 100 and lee currents flow to VSS' The lea current is the sum of all leakage currents.
4. During eE on Vee supply current is dependent on output loading. Vee is connected to output buffer only.
5. Maximum 1001 for 21078-5 is 250 /JA.
6.

During CE high a current of O.5mA typical. 1.5mA maximum will be drawn from any address pin which
is switched from low to high.

6-129

21078 FAMILY

A. C. Characteristics

TA = oOc to 70°C, Voo = 12V ± 5%, Vee = 5V ± 10""(,, Vee = -5V ± 5%,

READ, WRITE, AND READ MODIFY/WRITE CYCLE Vss = OV. unless otherwise noted.
2107B

2107B·4

Parameter

Symbol

Min.
Time Between Refresh

tREF

Min.

Max.

2107B·5

Max.

2

Min.

Units

Note

ms

7
3

Max.

2

1

tAC

Address to CE Set Up Time

0

0

10

ns

tAH

Address Hold Time

100

100

100

ns

tcc

CE Off Time

130

tT

CE Transition Time

10

tCF

CE Off to Output
High Impedance State

0

130

ns

200

10

40

40

0

10

40

ns
ns

0

READ CYCLE
2107B
Symbol

2107B·4

Parameter
Min.

tCY

Cycle Time

400

tCE

CE On Time

230

Max.

Min.

2107B·5

Max.

470
4000

Min.

Max.

590

300

4000

350

Units

Note

ns

4

3000

ns

tco

CE Output Delay

180

250

280

ns

5

tACC

Address to Output Access

200

270

300

ns

6

tWL

CE to WE

0

0

0

ns

twc

WE to CE On

0

0

0

ns

WRITE CYCLE
Symbol

Parameter

2107B
Min.

2107B·5

2107B·4
Min.

Max.

Max.

Max.

Note

ns

4

400

tCE

CE On Time

230

tw

WE to CE Off

125

150

200

ns

tcw

CE to WE

150

150

150

ns

tDW

D,N to WE Set Up

0

0

0

ns

4000

590

Units

Cycle Time

tCY

470

Min.

300

4000

350

3000

ns

tDH

D,N Hold Time

0

0

0

ns

twp

WE Pulse Width

50

50

7'5

ns

tww

WE Delay

75

75

75

ns

Symbol

Plastic And
Ceramic Pkg.
Typ.
Max.
4
6

Test

Unit

Conditions

CAD

Address Capacitance, CS

pF

VIN = Vss

CeE

CE Capac itance

17

25

pF

VIN - VSS

COUT

Data Output Capacitance

5

7

pF

VOUT = OV

CIN

DIN and WE Capacitance

8

10

pF

VIN = Vss

Notes: 1. If WE is low before CE goes high thon D,N must be valid when CE
goes high.
2,

("-3pa~itance

meesured with Boonto;-; ~. 1Gtai
.

OJ'

effective capiicitailce

calculated from the equation.
e = Illt with the current equal to a constant 2OmA.
llV

6·130

3.
4.
5.
6.

1

tAC is measured from end of address transition.
tT = 20ns

CLOAD = 5OpF, Load = One TTL Gate, Ref = 2.0V.
tACC = tAC + tco + ItT
7. tREF = 2ms at TA = 55° C for the 21078·5.

21078 FAMILY
Read and Refresh Cycle [11
I----~-------------tev----------------------.I

,......1.-ADDRESS
ANDCS

!tT

- - - - - - - - - - teE - - - - - - - - - - - - .

V,He

----+----j-".,..,.-----------------------...

CE

'we

V,H---_+--~_+--------------------------------------------_1_+~~------~----WE

WE

CAN

CHANGE

~---------~o----------.I

IIoH---

----

~ - IMP~6a:NCE

VALID

VOL --- i,~~------------------tACC------------.,

Write Cycle

V,H
ADDRESS

ANOes

V,L

.

~®
~0

t AC -

I

tev

K

ADDR ESS 8T AB LE

- - - tAH

ADDRESS CAN CHANGE

0

teE

V

.

tww
~w

WE CAN

CHANGE

o,N CAN CHANGE

--- ---1-

IMP~~~~CE -

----- --

r\

I

----tcc~

r-r"=
-

~CANCHANGE

--

>
J

i+--taH

~(CAN CHANGE
D,N

DIN STABLE

-----I-- IMP~~C::NCE -

UNDEFINED

~

NOTES: 1.
2.
3.
4.
5.
6.
7.

r----

\

tw

-taw

D,N

I+-tT

~

-J

®

0

- tT

~

-~

I----

CE

Ao6RESSST ABLE

------

f.-~F

D..

For Refresh cycle row and column addresses must be stabl. before tAC and remain stabla for antire tAH period.
VIL MAX is tha refarenca I.vel for m.asuring timing of the addres•••• CS. WE. and DIN.
VIH MIN i. the r.fer.nc.lavel for m.asuring timing of tha addre.se•• CS.
and DIN.
VSS +2.0V is the referenca laval for measuring timing of CEo
VDD -2V is the rafaranca laval for measuring timing of CEo
VSS +2.0V is tha refarencalaval for mea.uring tha timing of DOUT.
During CE high typically O.SmA will b. drawn from any addre.s pin which is .witched from low to high.

m.

6-131

21078 FAMILY
Read Modify Write Cycle!1]
Symbol

21078

Parameter

Min.

21078-4
Max.

Min.

21078-5

Max.

Min.

tRWC

Read Modify Write (RMW)
Cycle Time

520

tCRW

CE Width During RMW

350

twc

WE to CE on

0

0

0

ns

tw

WE to CE off

150

150

200

ns

twp

WE Pulse Width

50

50

100

ns

tDW

DIN to WE Set Up

0

0

0

ns

tDH

DIN Hold Time

0

tco

CE to Output Delay

180

250

280

ns

tACC

Access Time
(tACC = tAC + tco + ltT)

200

270

300

ns

I,

V,H
ADDRESSES

ANDes

III

4000

)( ®
0)

420

750

0

ADDRESS CAN CHANGE

®

/------

-tT

tCRW

I

I-'wp~

I-

f-- 1wc

I

t

0

D,N CAN CHANGE

,

-------1\
IMPEoANC~
HIGH

----~
NOTES:

1.
2.
3.
4.
5.

:x

-j

~'cc~

/

I-tow

-~

--

WE CAN
CHANGE

-f--

DIN CAN
CHANGE

------1l

I

tco---~

®
t Acc - - - -

- tOH

K

o.N STABLE

J'

ll--

I

'\

'w

I,

0

D,N

tT-

-1

®

4--

ns

_--tAH--~

CE

J

ns

I

--~tAC

---,-

~

3000

CD

t RWC

ADDRESS STABLE

ns

510

4000

0

I

I

----..

590

Unit

Max.

HIGH

2:~::E--

VALID

tCF - -

Minimum cycle timing is based on tT of 20n5.
V, L MAX is the reference level for measuring timing of the addresses, CS, WE, and D,N_
V,H MIN is the reference level for measuring timing of the addresses, CS, WE, and D,N·
VSS +2.0V is the reference level for measuring timing of CEo
VOO -2V is the reference level for measuring timing of CEo
6. VSS +2.0V is the reference level for measuring the timing of DOUT. ClOAD = 5OpF. load = One TTL Gate.
7. WE must be at VIH until end of tCO.
S. During CE high typically O.5mA will be drawn from any address pin which is switched from low to high.

21078 FAMILY

Typical Characteristics
Fig. 2. TYPICAL 100 AVERAGE VS. CYCLE TIME

Fig. 1. 100 AV VS. TEMPERATURE

",---~--,----r---'--~--~~-'
voo - 12.6V

2.0

>
<

..e

'"

=

J9

I.'

@ 1.25 '----

TYPICAL (CS ~

~

<
~
~

'-------

~

TYPICAL /CS

~

-

13

°0L-~2~00~-'~OO~~60~0--~'0~0~~'OO~0~'~200=--'~'OO'

70

"

2S"C

c1
'"

~

"

13.6V-

=

26>--t

~

a

0.75

0.5 0

"

I

VII.j!

525V

=

Tcv (ns!

Fig. 3. 1002 VS. TEMPERATURE

Fig. 4. TYPICAL VI L MAX VS. CE RISE TIME

"

2.0

'6
1.75

I.'

.8
e
N

~

~
~

12

"

]

~

12.6V

---:::,: ~

10

1.25

0.8
Voo

>'

1.0

/ VOD _
V 1HC - '1.6V

............ ~

0.6 ~ViHC

~

--.;;:

1'.4Y/
10.4V

,

--

O.
0.75
02
0.'

o

0

20

10

30

"

35

Typical Current Transients vs. Time
, 00

200

300

400

500

---1~.
L-

CE

CYCLE

J

100

200

300

400

I

I

I

I

READ
CYCLE

500

\'---

30

2.

"

2.0
1.5
NORMALIZED
'DO

1.0
0.5

..

'

(rnA)

~
J

t- H

I Do2 TYPICAL

20

"•

,I'

For additional typical characteristics and applications information please refer to Intel Application Note AP,10, "Memory System Design
With the Intel 21078 4K RAM" or Intel's Memory Design Handbook.

6-133

inter

2116 FAMilY

16,384 X 1 BIT DYNAMIC RAM
2116-2
200
350
400

Max. Access Time (ns)
Read, Write Cycle (ns)
Read-Modify-Write Cycle (ns)

• Highest Density 16K RAM:
Industry Standard 16 Pin
Package
• Low Standby Power
• All Inputs Including Clocks
TTL Compatible
• +10% Tolerance on all
Power Supplies +12V,
+5V, -5V

2116-3
250
375
525

2116-4
300
425
595

• On-Chip Latches for
Address and Data In
• Only 64 Refresh Cycles
Required Every 2 ms
• Output is Three-State, TTL
Compatible; Data is Latched
and Valid into Next Cycle

The Intel® 2116 is a 16,384 word by 1 bit MOS RAM fabricated with two layer polysilicon N-MOS technology - a productionproven process for high performance, high reliability, and high functional density. The 2116 uses a single transistor dynamic
storage cell and dynamic circuitry to achieve high speed and low power dissipation.
The unique design of the 2116 allows it to be packaged in the industry standard 16 pin dual-in-line package. The 16 pin package
provides the highest system bit densities and is compatible with widely available automated handling equipment. The 2116 is
designed to facilitate upgrading of 2104A-type 4K RAM systems to 16K capabilities.
The use of the 16 pin package is made possible by multiplexing the 14 address bits (required to address 1 of 16,384 bits) into the
2116 on 7 address input pins. The two 7 bit address words are latched into the 2116 by the two TTL clocks, Row Address Strobe
(RAS) and Column Address Strobe (CAS). Non-critical clock timing requirements allow use of the multiplexing technique while
maintaining high performance.
The single transistor dynamic storage cell provides high speed along with low power dissipation. The memory cell requires refreshing for data retention. Refreshing can be accomplished every 2 ms by anyone of the three following methods: ("I) CAS
before RAS cycles on 64 addresses, Ao-A5, (2) RAS-only cycles on 128 address, Ao-A6, or (3) normal read or write cycles on
128 addresses, Ao-A6. A write cycle will refresh stored data on all bits of the selected row except the bit which is addressed. The
output is brought to a high impedance state by a CAS-only cycle or by a CAS-before-RAS refresh cycle.
PIN CONFIGURATION
v••

LOGIC SYMBOL

BLOCK DIAGRAM

Ao

Vss

D,N

A,
D,N

CAS

WE

DOUT

A,

RAS

A.

A.

Ao

A,

As

(CAS)

A,
D'N

Ao

DOUl

A,

A,
A,

A.

A,

As

A,
A,
A.

Vee

As

DOUT

A,

- - - VBB

- voo

PIN NAMES

-Vee

AO' A6 ADDRESS INPUTS

WE

CAS

COLUMN ADDRESS STROBE

D'N

DATA IN

DOUT

DATA OUT

RAS

ROW ADDRESS STROBE

V::m
Vee
Voo
Vss

WRITE ENABLE
POWER 1-5Vl

-GND

POWER (+5VI
POWER (+12V!
GROUND

6-134

2116 FAMILY
Absolute Maximum Ratings*
'COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is 8 stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum fating
conditions for extended periods may affect device reliability.

Ambient Temperature Under Bias. . . . . . .. _10°C to +80°C
Storage Temperature . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on any Pin Relative to Vss
(Vss - Vss ~ 4V)
. . . . . . . . . . . . . • . -0.3V to +20V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . .
1.25W

D.C. and Operating Characteristics [1],[2]
TA = O°C to 70°C, VOO = +12V ±10%, Vee = +5V ±10%, Vss = -5V ±10%, VSS = OV, unless otherwise noted.
Limits
Symbol

Parameter

III

Input Load Current (any input)

IILOI

Output Leakage Current
for high impedance state

1001
ISSl

1002[41

Min.

Typ.(3)

Max.

Unit

Conditions

10

IlA

VIN = VIL MIN to V IH MAX

0.1

10

IlA

Chip deselected: RAS and CAS at VIH
VOUT = 0 to 5.5V

Voo Supply Current

1.2

2

mA

Vss Supply Current

1

50

IlA

CAS and RAS at V IH or CAS'only
cycle. Chip deselected prior to
measurement. See Note 5.

53

69

mA

2116-2 teye = 350 ns

51

68

mA

2116-3 teye = 375 ns

49

65

mA

2116-4 teye = 425 ns

120

400

IlA

Device selected

10

IlA

Operating Voo Current

ISS2

Operating V SS Current

leel (7)

Vee Supply Current when
deselected

TA = 25°C
Device
selected.
See Note 6.

VIL

Input Low Voltage (any input)

-1.0

0.8

V

VIH

Input High Voltage (any input)

2.4

Vee+ l

V

VOL

Output Low Voltage

0.0

0.4

V

IOL = 4.1 mA (Read Cycle Only)

VOH

Output High Voltage

2.4

Vee

V

IOH = -5 mA (Read Cycle Only)

Capacitance [8]
Symbol

T A = 25°C, Voo = 12V ±10%, Vcc = 5V ±10%, Vss = -5V ±10%, VSS = OV, unless otherwise noted.
Typ.

Max.

Unit

Conditions

Cll

Address, Data In & WE Capacitance

4

7

pF

VIN = VSS

CI2

RAS Capacitance

3

5

pF

VIN = VSS

C I3

CAS Capacitance

6

10

pF

VIN = VSS

Co

Data Output Capacitance

3

7

pF

VOUT =OV

Parameter

Notes:
1. All voltages referenced to Vss. No power supplV sequencing is required but VOO, Vce, and VSS should never be 0.3V or more negative than VSB.
2. To avoid self-clocking, RAS should not be allowed to float.
3. Typical values are for TA = 25°C and nominal power supply Voltages.
4. For RAS-only refresh 100 = 0.781002. For CAS-before-RAS (64 cycle refresh) 100 = 0.961002.
5. The chip is deselected Ii.e., output is brought to high impedance state) by CAS-only cycle or by CAS-before-RAS cycle. The current flowing
in a selected (i.e., output on) chip with RAS and CAS at VIH is approximately twice 1001.
6. See Page 2-98 for typical 100 characteristics under other conditions.
7. When chip is selected Vce ",",pply current is depende"t on output loading; Vee is connected to output buffer only.
8. Capacitance measured with Soonton Meter.
6-135

2116 FAMILY

Typical Characteristics

Standby Power Calculations:
tCYC
tCYC
f>REF = POP (N -t- ) + PSB (1 - N- ) where
t REF
REF

IBB2ANO 1002 VS. TEMPERATURE
480

'00

VOO
VBB

75

S

N = Number of refresh cycles (64 or 128)
360

'" -5.0V

tCYC = Cycle time for a refresh cycle.

tCYCLE '" 426 IU
'" 96 ns
tRP

;;

.s

POP = Power dissipation (continuous operation) ~ VOO x 100 2.

.,.1

I

tREF = Time between refreshes

'002

50

240

Pse = Standby power dissipation = VOO x 1001 + IVBe I x lee

r-

S!

Note that 1002 depends upon refresh as follows:

r--

25

188l

~

'20

1. For 128 cycle (RAS before CAS) use 1002 from Figures 1 and 2.

I--

2. For 64 cycle (CAS before RAS) multiply 1002 determined in (1)
by 0.96.

o
25

50

75

'00

3. For 128 cycle (RAS only) multiply 1002 determined in (1) by
0.78.

Figure 1.
1002 VS. CYCLE TIME

Examples of typical calculations for Vee = -5.0V, Voo = 12.0V,
T A = 25°C, tCYC = 0.425 J.lS, tRAS = 0.3 J.ls. tREF = 2000 J.ls:

WRIT~

Voo '" 12.0 V

CYCLE

Ves = -5.0V

1. 128 cycle (RAS before CAS): POP = 12.0Vx43mA=516mW

T' 25"

0.425
0.425
PREF = 516 (128 2000) + (12xl.2+5xO.001) (1-128 2000)
PREF = 28.0 mW
2. 64 cycle (CAS before RAS); POP = 12.0V x 43 (0.96) mA =
495 mW.
0.425
0.425
PREF = 495 (64 2000) + (12x 1.2+5xO.001)( 1-64 2000) =

20300 400

PREF = 20.9 mW

500

3. 128 cycle (RAS only): POP = 12.0V x 43 (0.78) mA = 402 mW

T CYCLE (ns)

Figure 2.

PREF = 25.0 mW

rrt -

150
75

100
(mA)

n......1

'--

r-,

L

..,,

r-

n

~~~

NOT

A

/I, II.

~

JV ~

IA

J

Ali

\

~.

it

\

r

UV \r- W~

0

-60

IIL~

II

'V

.ft

IV \

,

400

600 Ins)

READ CYCLES

A~

.v

"

I
200

400

A

f

IV

IU

200

400

READ-MODIFY-WRITE

Note 1: Increase in current due to WE going low. Width of this
c:urrent pulse is independent of WE pulse width.

Figure 3. Supply Current Waveforms.

6-136

v

600 (nsl

CAS BEFORE RAS
(FOR 64 CYCLE REFRESH)

-

IV ty

,

All

• A, 1\

A 11M

'V

600 {nsl

~

A

\rW! ]V \

A~M

+60
I ••
(mA)

rL

rrL rL -

f1

ALII

II

'V
400

Rii ONL V REFRESH

,A

.\

600 (nl)

2116 FAMILY

. . [1]
AC
. . Ch aracteflstlcs
TA=O°C to 70°C, VDD=12V ±10%, VCC=5V ±10%, VBB=-5V ±10%, VSs=OV, unless otherwise noted.

READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
Symbol

Parameter

2116-2
Min.
Max.

2116-3
Min.
Max.

2

2116-4
Min.
Max.

tREF

Time Between Refresh

tRP

RAS Precharge Time

75

75

95

tcp

CAS Precharge Time

100

125

125

tRCL [2]

RAS to CAS Leading Edge Lead Time

tCRP [3]

CAS to RAS Precharge Time

tRSH

45

75

2

50

110

2

60

Unit
ms
ns
ns

110

ns

0

0

0

ns

RAS Hold Time

160

200

220

ns

tCSH

CAS Hold Time

200

250

300

ns

tASR

Row Address Set-Up Time

0

0

0

ns

tASC

Column Address Set·Up Time

-10

-10

-10

ns

tAH

Address Hold Time

45

50

60

tT

Transition Time (Rise and Fall)

tOFF

Output Buffer Turn Off Delay

tCAC[4]

Access Time From CAS

125

tRAC[4]

Access Time From RAS

200

50
0

60

0

ns
50

ns

80

ns

150

190

ns

250

300

ns

50
60

0

READ AND REFRESH CYCLES
Symbol

Parameter

2116-2
Min.
Max.

2116-3
Min.
Max.

2116-4
Min.
Max.

375

425

Unit

tCYC[5]

Random Read Cycle Time

350

tRAS

RAS Pulse Width

275

32000

300

32000

330

32000

ns

tCAS

CAS Pulse Width

125

10000

150

10000

190

10000

ns

ns

tCH

CAS Hold Time for RAS·Only Refresh

30

30

30

ns

tCPR

CAS Precharge for 64 Cycle Refresh

30

30

30

ns

tRCH

Read Command Hold Time

20

20

20

ns

tRCS

Read Command Set·Up Time

tDOH

Data-Out Hold Time

0

0

0

ns

32

32

32

J.ls

WRITE CYCLE
Symbol

Parameter

2116-2
Min.
Max.

2116·3
Min.
Max.

2116·4
Min.
Max.

375

425

Unit

tCYC[5]

Random Write Cycle Time

350

tRAS

RAS Pulse Width

275

32000

300

32000

330

32000

ns

tCAS

CA""S Pulse Width

125

10000

150

10000

190

10000

ns

tWCH

Write Command Hold Time

75

100

100

ns

twp

Write Command Pulse Width

50

100

100

ns

tRWL

Write Command to RAS Lead Time

125

200

200

ns

tCWL
tDS[6]

Write Command to CAS Lead Time

100

150

160

ns

0

0

0

ns

tDH l6J

Data·ln Hold Time

100

100

125

ns

Notes:

Data-In Set-Up Time

ns

1. All voltages referenced to VSS.
2. CAS must remain at VIH a minimum of tRCL MIN after RAS switches to VIL. To achieve the minimum guaranteed access time
(tRAC), CAS must switch to VI L at or before tRCL (MAX) = tRAC -tCAC· Device operation is not guaranteed for tRCL>2 J,ts.
3. The tCRP specification is less restrictive than the teRL range which was specified in the 2116 preliminary data sheet.

4. Load = 1 TTL and 50 pF.
5. The minimum cycle timing does not allow for tT or skews.
6. Referenced to CAS or WE, whichever occurs last.

6-137

2116 FAMILY

Waveforms
READ CYCLE
tCYC

I---'RP~

tRAS

0)

V-

~~

i--'CRP

r-'CP~1

'CSH
l----tRcL~

0)

tAS A

~H
ADDRESSES

I-- I--'AW-,

~

V,L

ROW

ADDRESS

l( )

·RSH----~

1\\\\ 0

I-

teAs

~'AH-

tAse

K

COLUMN

ADDRESS

I-

t

V

I-

Acs

cf¥
I'

'oFF- .~

1\

.

tRAC

teAc

®
eD

-};.@
J-

tACH

'DaH~

r

VALID
DATAQUT

WRITE CYCLE
~---------------tcvc----------~-------'
4-----------------tRAS-------------~

V ,H

!'!AS

~ I-- 'CRP - -

CD I' 0

V'L

-tR~

~---------------------------------4
~-------------·CSH------------_i-~

______-+-t~
___
·_•.;;R.;;;CL""_ _=t1_f""'""r""':\l. I-~----·RSH------_I

CD 1\\~~1-':::0~~-

V,H

CAS

V,L

'CP

---r--~V

'CAS . - -

~tAH--

V,H

V(J)

A -0

ADDRESSES
V'L

ROW

ADDRESS

COLUMN
ADDRESS

~------+-~-tRWL----------··1

II---twc~~=r,,~;::===::'::::L- _ __

V,H

WE

.1

cff,,",~----- 'wP

V,L

V,H

D'N
V'L

teAc
~------~----tRAC+:==========~~==========~
__ I..

_ _______________________________

.~OF~F --~~~~~

VOH
DaUT

Notes:

~0

VOL

1,2.
3,4.
5.
6.
7.

VIH MIN and VIL MAX are reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of DOUT.
DOUT follows DIN when writing, with WE before CAS.
Referenced to CAS or WE, whichever occurs last.
tOFF is measured to lOUT';; IILOI.

6-138

®

2116 FAMILY

A.C. Characteristics
TA ~ o°c to 70°C, VDD ~ 12V ±10%, Vcc ~ 5V ±10%, VB B ~ -5V ±10%, Vss ~ OV, unless otherwise noted.

READ-MODIFY-WRITE CYCLE
Symbol

Parameter

2116·2
Min.
Max.

2116-3
Min.
Max.

21164
Min.
Max.

525

595

Unit

tRMW

Read-Modify-Write Cycle Time

400

tCRW

RMW Cycle CAS Width

225

10000

310

10000

350

10000

ns

tRRW

RMW Cycle RAS Width

325

32000

450

32000

500

32000

ns

tRwH

RMW Cycle RAS Hold Time

250

350

390

ns

tCWH

RMW Cycle CAS Hold Time

300

410

460

ns

tRWL

Write Command to RAS Lead Time

125

200

200

ns

tCWL

Write Command to CAS Lead Time

100

160

160

ns

twp

Write Command Pulse Width

50

100

100

ns

tRCS

Read Command Set-Up Time

0

0

0

tMOD

Modify Time

0

tDS

Data-In Set-Up Time

tDHM

Data-In Hold Time (RMW Cycle)

10

10

0

ns

ns

0

10

}J.s

0

0

0

ns

50

100

125

ns

Waveforms
READ MODIFY WRITE CYCLE

.

'RMW
tRRW

RAS

V,H
V'L

CD

-

V ,H

t RCL

){CD

IL

'AH
tASC

ROW

ADDRESS

tCRW

t RWH

-'RWL-

.r-

K ){

l~~~:LtAH

-'CWL

l(

COLUMN
ADDRESS

®

~-'wPV

'Rcsl--I

WE

~IH
IL

®CDf
'MOD

1-

t RAC
tOF F -

'CRP-I\

-tcp~

'CWH

~\\\ ®

CD

t A S R i ...........

~IH

.

~-+

V'L

r---ADDRESSES

r-'RP-

r--

®
-4--

CAS

•

-=-----1

~®

tCAc

HIGH
IMPEDANCE

-Y-

..

r--

1--'0.

I)

CDOATAIN

VALID

I ®

®3, Ti

0

tOHM

I ...

VALID
DATA OUT

Notes: 1,2. V,HM,N and V,LMAX are reference levels for measuring timing of input signals.
3,4. VOHMIN and VOLMAX are reference levels for measuring timing of DOUT.
5. tOFF is measured to 'OUT';; IILol.

6-139

K

"-

2116 FAMilY
Refresh Cycle Waveforms
CAS BEFORE RAS CYCLES. (64 CYCLE REFRESH)
f.----~~'RAS ----~-I

---I

-tAH _ _

-~- tAH --+---~

cAs

V,H
ADDRESSES
AO-As

~l

____

-'~~

VALID
__________________

VALID
~~J~

________________________________

-'~~

____________

All OTHER INPUTS: DON'T CARE

RAS ONLY CYCLES (128 CYCLE REFRESH)

r-

--------tCYC----

1+--------- 'RAS--------i

I~'---tRP---~1

V,H-------~
RAS

CAS

ADDRE~E-S------~~~---V-A-L-'D---'A-H---t~I~---------------------------------------X~~----V-A-Ll-D------­
Ao·As

Vll ______

-L~~------__----~~--------------------------------------~~---------------

Notes: 1,2. VIHMI N and VI LMAX are reference levels for measuring timing of input signals.
3.

CAS must be high or low as appropriate for the next cycle.

Applications Information
REFRESH MODES
The 2116 may be refreshed in any of three modes.
Read/Refresh cycles and RAS-only cycles refresh the row
addressed by Ao through A6 and therefore require 128
cycles to refresh the stored data. Assuming a 500 nsec
system cycle time, the refresh opefations require 64 ,usee
out of each 2.0 msec refresh period or 3.2% of the available
memory time. The third 2116 refresh mode, CAS-beforeRAS, allows refresh of the stored data in only 64 cycles and
requires only 32 f..'sec or 1.6% of the available memory time

(equal to the 64-cycle refresh 4K RAMs). While some 2116
aplications would not be impacted by the 3.2% memory
lockout time using 128 cycle refresh, most large mainframe
memory applications would suffer throughput degradation
in that refresh mode. Intel designed the 2116 to allow either
128-cycle or 64-cycle refresh, allowing the system designer
to choose the refresh mode which fits his system needs. In
addition to ailowing higher memory throughput, the CASbefore-RAS 64-cycle refresh mode dissipates approximately 14% less power than the 128-cycle RAS-only mode
and 23% less power than the 128-cyC'le Read/Refresh mode
(refer to the Standby Power Calculation section).

6-i40

2116 FAMILY
POWER SUPPLY DECOUPLINGI
DISTRIBUTION
Power supply current waveforms for the 2116 are shown in
Figure 3. The Voo supply provides virtually all of the
operating current for the 2116. The Voo supply current,
10 0 , has two components: transient current peaks when the
clocks change state and a DC component while the clocks are
active (Iowl. When selecting the decoupling capacitors for
the Voo supply, the characteristics of capacitors as well as
the current waveform must be considered. Suppression of
transient or pulse currents require capacitors with small
physical size and low inherent inductance. Monolithic and
other ceramic capacitors exhibit these desirable character·
istics. When the current waveform indicates a DC component, bulk capacity must be located near the current load to
supply the load power. Inductive effects of PC board traces
and bus bars preclude supplying the DC component from
bulk capacitors at the periphery of a memory matrix without
voltage droop during the active portion of a memory cycle.
This means that some bulk capacity in the form of electrolytic or large ceramic capacitors should be distributed around
or within the memory matrix.
The VBB supply current, IBB, has high transient current
peaks, with essentially no DC component (less than 400
microamperes). The VBB capacitors should be selected for
transient suppression characteristics. The following capacitance values and locations are recommended for the
2116:
1. A 0.33 }.IF ceramic capacitor between Voo and Vss
(ground) at every other device.

OUTPUT DATA LATCH
The 2116 contains an output data latch eliminating the need
for an external system data latch and the timing circuitry
required to strobe an external latch. The 2116 output latch
operates identically to the output latch found on all industry
standard 16-pin, 4K RAMs and enhances the system compatibility of the 16K and 4K devices.
Operation of the output latch is controlled by CAS. The data
output will go to the high-impedance state immediately
following the CAS leading edge during each data cycle and
will either go to valid data at access time on selected devices
(devices receiving both RAS and CAS) or will remain in the
high impedance state on unselected devices (devices
receiving only CAS). During RAS-only refresh cycles, the
data output remains in the state it was prior to the RAS-only
cycle. This unique feature of latched output RAMs allows a
refresh cycle to be hidden among data cycles without
impacting data availability. For instance. a RAS-only
refresh cycle could follow each data cycle in a
microprocessor system but the accessed data would
remain at the device output and the microprocessor could
take the data at any time within the cycle. Non-latched
output devices do not provide this type of hidden refresh
capability since their data output would go to the high
impedance state at the end of the data cycle.

PAGE MODE OPERATION
The 2116 is deSigned for page mode operation and is
presently being characterized forthat mode. Specifications
will be available at a later date.

2. A 0.1 J.LF ceramic capacitor between '1BB and Vss at every
other device (preferably alternate devices to the VDD
decoupling above).
3. A 4.7 J.LF electrolytic capacitor between VDD and Vss for

each eight devices and located adjacent to the devices.
The Vee supply is connected only to the 2116 output buffer
and is not used internally. The load current from the Vee
supply is dependent only upon the output loading and is
usually only the input high level current to a TTL gate and
the output leakage currents of any OR-tied 2116s (typically
100 J.LA or less total). Intel recommends that a 0.1 or 0.01 J.LF
ceramic capaCitor be connected between Vee and Vss for
every eight devices to preclude coupled noise from
affecting the TTL devices in the system.
Intel recommends a power supply distribution system such
that each power supply is grided both horizontallY and
vertically at each memory device. This technique minimizes
the power distribution system impedance and enhances the
effect of the decoupling capacitors.

6-141

..
,
,

inter

3222

REFRESH CONTROLLER FOR 4K DYNAMIC
RANDOM ACCESS MEMORIES
Ideal for use in
• 2107A,
2107B Systems

• Adjustable Refresh Timing
Oscillator

• Simplifies System Design

• 6-Bit Address Multiplexer

• Reduces Package Count

• 6-Bit Refresh Address Counter

• Standard 22-Pin DIP

• Refresh Cy~le Controller

The Intel® 3222 is a refresh controller for dynamic RAMs requiring refresh of up to 6 input addresses (or 4K bits for 64 x 64
organization). The device contains an accurate refresh timer (whose frequency can be set by an external resistor and
capacitor), plus all necessary control and I/O circuitry to provide for the refresh requirements of dynamic RAMs. The chip's
high performance makes it especially suitable for use with high speed N-channel RAMs like the Intel® 21078. The 3222 is well
suited for asynchronous dynamic memory systems.
The 3222 operates from a single +5 volt power supply and is specified for operation over a OOG to 75°G ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process.

BLOCK DIAGRAM

PIN CONFIGURATION

ADDRESS

6

INPUTS

 3232 contains an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh
of up to 6 input addresses (or 4K bits for64x 640rganization).lt multiplexes twelve bits of system supplied address to six output
address pins. The device also contains a 6 bit refresh counter which is externally controlled so that either distributed or burst
refresh may be used. The high performance of the 3232 makes it especially suitable for use with high speed N-channel RAMs
like the 2104A.
The 3232 operates from a single +5 volt power supply and is specified for operation over a 0 to +75°C ambient temperature
range.

PIN CONFIGURATION
COUNT

LOGIC DIAGRAM

Vee

REFRESH ENABLE

ROW ENABLE

"',

As

"',

A"

A,

A.

A.

A"

"'"
As

0,

I
I

I

I
A.

A3

A.

....

0;,

0,

0,

O.

0;

0.

12 I
TOT"'L I
8

G

,TOTAL

TOTAL

I

I

....
A.

D.

As THROUGH As ... RE ROW ADDRESSES.
As THROUGH A" ARE COLUMN ADDRESSES.

TRUTH TABLE AND DEFINITIONS:
REFRESH
EN...BLE

ROW
ENABLE

H

X

L

H

L

L

REFRESH
ENABLE

ROW
ENABLE

OUTPUT
REFRESH ADDRESS

IFROM INTERNAL COUNTERI

~~~~~g~~~.... 1
COLUMN ADDRESS
(AS THRQUqH

.An!

00iiNT - ...DV...NCES INTERN... L REFRESH COUNTER.
ZERO DETECT

I

I

ZERO DETECT
NOTE,

I

I

I
I
I

INDIC...TES'" ZERO IN THE REFRESH ...DDRESS
IUSED IN BURST REFRESH MODEl.

6-148

a TOTAL

nOT"'L

ZEiiO

DETECT

3232
Absolute Maximum Ratings*
'COMMENT:
Temperature Under Bias •........•.... -65° to +125°C
Storage Temperature ..•.............. -65° to +160"C
All Input, Output, or
Supply Voltages .............•...... -0.5V to +7 Volts
Output Currents •....................•........ 100mA
Power Dissipation .....•.•...•..........•......... 1W

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

D.C. and Operating Characteristics
All Limits Apply for Vee = 5.0V ±10%, T A = 0" C to

+ 75° C
LIMITS
TYP.(l1

MAX.

-0.04

-0.25

mA

VIN

0.45V

0

10

p.A

VIN

5.5V

0.8

V
V

0.40

V

10L

V

10H

SmA
1mA

V

10H - -1mA

SYMBOL

PARAMETER

IF

Input Load Current

IR
VlH
VIL

Input Leakage Current

VOL
VOH

Output Low Voltage
Output High Voltage (O...l:),)

2.8

4.0

VOHI

Output High Voltage
(zero Detect)

2.4

3.3

Ice

Power Supply Current

Note 1.

Input High Voltage

MIN.

2.0

Input Low Voltage
0.25

100

Typical values are for TA = 25°e and Vee = 5.0V.

6·149

150

UNIT

mA

TEST CONDITIONS

Vee

5.5V

3232
A.C. Characteristics
All Limits Apply for Vee = +5.0V ±10'!1t. T A = O"C to 75"C. Load = 1 TTL. CL = 250pF. Unless Otherwise Specified.
TYP~')

SYMBOL

PARAMETER

MAX.

UNIT

tAO

Address Input to Output Delay

6

9

ns

CONDITIONS
Refresh Enable

tAO'

Address Input to Output Delay

16

25

ns

Refresh Enable

MIN.

too

Row Enable to Output Delay

7

12

27

ns

Refresh Enable

tOO'

Row Enable to Output Delay

12

28

41

ns

Refresh Enable

tEO

Refresh Enable to Output Delay

7

14

27

ns

Note 1. 2

tEOI

Refresh Enable to Output Delay

12

30

45

Refresh Enable
Refresh Enable

tco

Count to Output

15

40

60

ns
ns

tcO!

Count to Output

20

55

80

ns

fc
tcpw

Counting Frequency

5

Count Pulse Width

35

tcz

Count to Zero Detect

15

= Lowll)
= Low
= LOw(l)
= Low

= Highll)
= High

MHz
ns
70

ns

Note 2

Note 1: Vee = S.OV. T A = 2Soe
2: eL = 1SpF

A.C. TIMING WAVEFORMS (Typically used with 2104A)
NORMAL CYCLE
vlH
ROW ENABLE

Ao-A"

VIH
V,L

1I.-lJa

VON
VOL

REFRESH

ENABLE

1.6V

V,L

V1H -

COLUMN ADDRESS

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

--

v,L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - _

REFRESH CYCLE
REFRESH
ENABLE

1.5V
,L
V ---

V.H---+------------_I
l.IiV
________________
-I.lIo_--'
VIL - - - -

VON----~~2~A~V----~-----+-~~-------,
REFRESH ADDRESS

~L-----J~O=JW~-----------+--'-~--------'

-- ":--m------------___ J];_________
6-150

(2)

(2)

(2)

3232
PIN NAMES AND FUNCTIONS
Pin.
Pin
Function
No.
Name

inputs. The truth table on page 1 shows the levels required
to multiplex to the output:

Count Input

Active low input increments
internal six bit counter by
one for each count pulse in.

2

Refresh Enable
Input

Active high input which
determines whether the
3232 is in refresh mode (H)
or address enable (L).

7,3,5,18,
20,22

Ao-A, Inputs

Row Address inputs.

8,4,6,17,
19,21

A.-A" Inputs

Column address inputs.

9,11,10,
16,15,14

0 0-0,

Address outputs to memories. Inverted with respect
to address inputs.

Outputs

12

GND

Power supply ground.

13

Zero Detect
Output

Active low output which
senses that all six bits of
refresh address in the counter are zero. Can be used in
the burst mode to sense
refresh completion.

23

Row Enable
Input

High input selects row, low
input selects column addresses of the driven memories.

24

DEVICE OPERATION
The Intel@ 3232 Address Multiplexer/Refresh Counter
performs the following functions:
1. Row, Column and Refresh Address multiplexing
2. Address counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh
Enable and Row Enable, both of which are active high TTL

AI1

3232

I
I

Ao
REFRESH

ENABLE

0.

>--

I
I

>--

00

Burst Refresh Mode
When refresh is requested, the refresh enable input is high.
This input is ANDed with the 6 outputs of the internal 6 bit
counter. At each Count pulse the counter increments by
one, sequencing the outputs (00-0,) through all 64 row
addresses. When the counter sequences to all zeros, the
Zero Detect output goes low signaling the end of the refresh
sequence. Due to counter decoding spikes, the Zero Detect
output is va"lid only after lez following the low going edge cif
Count.
Distributed Refresh Mode
In the distributed refresh mode, one row is selected for
refresh each (tREFRESH/n) time where n ; number of rows in
the device and tREFRESH is the specified refresh rate for the
device. For the 2104A tREFRESH; 2msec and n; 64, therefore one row is refreshed each 31 J-Isec. Following the refresh
cycle at row n x , the Count input is pulsed, advancing the
refresh address by one row so that the next refresh cycle will
be performed on row n x +1' The Count input may be pulsed
following each refresh cycle or within the refresh cycle after
the specified memory device address hold time.
Rowand Column Address

+5V power supply input.

Vee

1. Refresh addresses (from internal counter)
2. Row addresses (Ao through A,)
3. Column addresses (Ao through All)

All twelve system address lines are applied to the inputs of
the 3232. When Refresh Enable is low and Row Enable is
high, input addresses Ao-A, are gated to the outputs and
applied to the driven memories. Conversely, when Row
Enable is low (with Refresh Enable still low), input
addresses A.-A" are gated to the outputs and applied to the
driven memories.
Figure 1 shows a typical connection between the 3232 and
the 2104A 4K dynamic RAM. When the memory devices are
driven directly by the 3232, the address applied to the
memory devices is the inverse of the address at the 3232
inputs due to the inverted outputs of the 3232. This should
be remembered when checking out the memory system.

As
I
I
I
I

2104A

Ao

As

A.

~
I
I
I

21D4A

AD

r--

r--rI

ZERO~ETECT

ROW
ENABLE

Figure 1. Typical Connection of 3232 and 2104 Memories.

6-151

I

~

2104A

f-

intel~
3242
ADDRESS MULTIPLEXER AND REFRESH
COUNTER FOR 16K DYNAMIC RAMs
• Single Power Supply:
+5 Volts ±10%

• Ideal For 2116
• Simplifies System Design

• Address Input to Output Delay:
9ns Driving 15 pF,
25ns Driving 250pF

• Reduces Package Count
• Standard 28-Pin DIP
• Suitable For Either Distributed
Or Burst Refresh

The Intel® 3242 is an address multiplexer and refresh counter for multiplexed address dynamic RAMs requiring refresh of 640r
128 cycles. It multiplexes 14 bits of system supplied address to 7 output address pins. The device also contains a 7 bit refresh
counter which is externally controlled so that either distributed or burst refresh may be used. The high performance of the 3242
makes it especially suitable for use with high speed N-channel RAMs like the 2116.
The 3242 operates from a single +5 volt power supply and is specified for operation over a 0 to +75° C ambient temperature
range. It is fabricated by means of Intel's highly reliable Schottky bipolar process and is packaged in a hermetically sealed 28
pin Type D package.

PIN CONFIGURATION
COUNT

Vee

REFRESH ENABLE

A,

ROW ENABLE

LOGIC DIAGRAM

A13
AI6

A,

N.C.

A,

A12

As

A,
Al1

A,

A,

Ao

A10

A,

0,

°0

0,

ff2

0.

o~

0;

GNO

O----t1===;======~)

06
I

I
I

I

I
I

,.

I
I
7
I
TOTAL I

TOTAL

I

7

I TOTAL

I
I

I
I
I
I
I
00

ZERO DETECT

NOTE: Ao THROUGH A6 ARE ROW ADDRESSES.
A7 THROUGH Au ARE COLUMN ADDRESSES.

TRUTH TABLE AND DEFINITIONS:
REFRESH

ROW

ENABLE

ENABLE

H

X

l

H

l

l

REFRESH
ENABLE

.......'

~-",,~--r

7 TOTAL

6 TOTAL
OUTPUT

ROW
ENABLE

ZERO
DETECT

REFRESH ADDRESS
(FROM INTERNAL COUNTER)
ROW ADDRESS
(Ao THROUGH Asl
COLUMN ADDRESS
(A7 THROUGH A'3)
COUNT

0--.-------'

COUN'f -

ADVANCES INTERNAL REFRESH COUNTER.
ZERO DETECT INDICATES ZERO IN THE fiRST 6
SIGNIFICANT REFRESH COUNTER
BITS (USeD IN BURST REFRESH MODE)

6-152

3242
A.C. Characteristics
All Limits Apply for Vee = +5.0V ±10%, TA = O°C to 75°C, Load = 1 TTL, C[ = 250pF, Unless Otherwise Specified.
SYMBOL

PARAMETER

Typ.11)

MAX.

UNIT

tAO

Address Input to Output Delay

6

9

ns

CONDITIONS
Refresh Enable = Low(2)(3)

t AOI

Address Input to Output Delay

16

25

ns

Refresh Enable = Low

MIN.

too

Row Enable to Output Delay

7

12

27

ns

Refresh Enable = Low(2)(3)

tOOl

Row Enable to Output Delay

12

28

41

ns

Refresh Enable = Low

ho

Refresh Enable to Output Delay

7

14

27

ns

Notes 2, 3

hOI

Refresh Enable to Output Delay

12

30

45

ns

teo

Count to Output

15

40

60

ns

Refresh Enable = High(2)(3)

teol

Count to Output

20

55

80

ns

Refresh Enable = High

5

MHz

fe

Counting Frequency

tcpw

Count Pulse Width

35

tez

Count to Zero Detect

15

ns
70

ns

Note 3

Notes: 1. Typical values are for T A = 25°e and Vee = 5.0V.

2. TA = 25°e, Vee = 5.0V.

3. eL=15pF.

A.C. TIMING WAVEFORMS (Typically used with 2116)
NORMAL CYCLE
ROW ENABLE

1.5V

V,H ______+_----~~------------------+_-----------------------------/\,.5V
vIL------+_----~~------------------+_------------------------------

~H------------------~--------------------------~-----------------2.4V
ROvV ADDRESS

DON'T CARE

COLUMN ADDRESS

~L------------------~~O~.8~V-----------------------L~-----------------

REFRESH
ENABLE

~---------------------------

VIL -----------------------------------------------------------------REFRESH CYCLE
REFRESH
ENABLE

I

V I H - 1• 1 .5V

\-----

VIL
I
j

V,H
COUNT

VIL - - - -

LtEo1

VOH
0-06

ADDRESS

VOL

I-tcpw~

7

- - - - - - - - - - - - - - -1.5V
-tco~

X

2 .4V
O.8V

REFRESH ADDRESS

}

REFRESH ADDRESS

I
_tcz_

V OH1

2ERllDnECT

1.5V

VOL - - - - - - - - - - - - - - - - - - - - - - - - - - 6-153

X

~

I

3242
Absolute Maximum Ratings·
*COMMENT:
Temperature Under Bias .............. -10 0 to +S5°C
Storage Temperature ................. -65° to +150°C
All Input, Output, or
Supply Voltages .................... -0.5V to +7 Volts
Output Currents .............................. 100mA
Power Dissipation ................................ 1W

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

D.C. and Operating Characteristics
All Limits Apply for Vee = 5.0V ±10%, TA = O°C to + 75°C
SYMBOL

PARAMETER

IF

Input Load Current

IR

Input Leakage Current

VIH

Input High Voltage

MIN.

LIMITS
TYP.(1)

MAX.

-0.04

-0.25

mA

VIN - 0.45V, Note 2

0.01

10

/lA
V

VIN

O.S

V

0.25

0.40

2.0

VIL

Input Low Voltage

VOL

Output Low Voltage

VOH

Output High Voltage (00-06)

VOHI

Output High Voltage
(zero Detect)

Icc

Power Supply Current

3.0
2.4

UNIT

TEST CONDITIONS

5.5V

V

IOL - SmA

4.0

V

10H

3.3

V

10H = -1mA

mA

Vec - 5.5V

1mA

.~-"-

Notes: 1. Typical values are for T A

= 25' e and

105
Vee

= 5.0V.

2. Inputs are high impedance, TTL compatible, and suitable for bus operation.

6-154

165

3242
PIN NAMES AND FUNCTIONS
Pin
No.

Pin
Name

2. Row addresses (Ao through A6)'
3. Column addresses (A7 throughoA13).

Function

Count
Input*

Active low input increments internal 7bit counter by one for each count pulse
in.

2

Refresh
Enable
Input*

Active high input which determines
whether the 3242 is in refresh mode (H)
or address enable (L).

9,5,7,21,
23,25,27

Ao-A£
Inputs*

Row address inputs.

10,6,8,20, A7-A13
22,24,26
Inputs *

Column address inputs.

11,13,12,
18,17,16,
19

00-06
Outputs

Address outputs to memories. Inverted
with respect to address inputs.

14

GND

Power supply ground.

15

Zero
Detect
Output

Active low output which senses that the
six low order bits of refresh address in
the counter are zero. Can be used in the
burst mode to sense refresh completion.

3

Row
Enable
Input*

High input selects row, low input selects
column addresses of the driven memo·
ries.

28

Vee

+5V power supply input.

Burst Refresh Mode

i

When refresh is requested, the refresh enable input is high.
This input is ANDed with the seven outputs of the internal
7-bit counter. At each Count pulse the counter increments by
one, sequencing the outputs (00-06) through 128 row addresses. When the first six significant bits of the counter
sequence to all zeros, the Zero Detect output goes low,
signaling the end of the refresh sequence. Due to counter decoding spikes, the Zero Detect output is valid only after tez
following the low-going edge of Count. The Zero Detect output used in this manner signals the completion of 64 refresh
cycles. To use the 128-cycle burst refresh mode, an external
flip-flop must be driven by the Zero Detect.
Distributed Refresh Mode

*The inputs are high impedance, TTL compatible, and suitable for bus

In the distributed refresh mode, one row is selected for refresh
each (tREFRESH/n) time where n = number of refresh cycles
required for the device and tREFRESH is the specified refresh
rate for the device. For the 2116 tREFRESH = 2 msec and n =
128 or 64, therefore, one row is refreshed each 15.5 or 31
psec, respectively. Following the refresh cycle at row n x, the
Count input is pulsed, advancing the refresh address by one
row so that the next refresh cycle will be performed on row
n x+1. The Count input may be pulsed following each refresh
cycle or within the refresh cycle after the specified memory
device address hold time.

operation.

Rowand Column Address
DEVICE OPERATION
The Intel® 3242 Address Multiplexer/Refresh Counter per·
forms the following functions:
1. Row, Column and Refresh Address multiplexing.
2. Address Counting for burst or distributed refresh.
These functions are controlled by two signals: Refresh Enable
and Row Enable, both of which are active high TTL inputs.
The truth table on page 1 shows the levels required to multiplex to the output:
1. Refresh addresses (from internal counter).

A"

0,

A,

00

Ao

All 14 system address lines are applied to the inputs of the
3242. When Refresh Enable is low and Row Enable is high,
input addresses Ao-A6 are gated to the outputs and appl ied to
the driven memories. Conversely, when Row Enable is low
(with Refresh Enable still low), input addresses A7-A13 are
gated to the outputs and applied to the driven memories.
Figure 1 shows a typical connection between the 3242 and the
2116 16K dynamic RAM. When the memory devices are
driven directly by the 3242, the address applied to the memory devices is the inverse of the address at the 3242 inputs due
to the inverted outputs of the 3242. This should be remembered when checking out the memory system.

A,

2116

3242

A,

2116
Ao

Ao

REFRESH
ENABLE

ROW

ENABLE

00iJNf

Figure 1. Typical Connection of 3242 and 2116 Memories.

6-155

2116

An

I

r

6-156

PERIPHERALS and SUPPORT CIRCUITS

PERIPHERALS and SUPPORT CIRCUITS
8205 High Speed lout of 8 Binary Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8212 8-Bit Input/Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8212 8-Bit Input/Output Port (MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8214 Priority Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
................................ .
M8214 Priority Interrupt Control (MIL)
8216/8226 4·Bit Parallel Bi·Directional Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8216 4-Bit Parallel Bi-Directional Bus Driver (MIL) . . . . . . . . . . . . . . . . . . . . . . . . .
8251 A Programmable Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8251 Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . _. . . . . . . . . . . . . . . . . . . . .
8253/8253-5 Programmable Interval Timer
8255A/8255A-5 Programmable Peripheral Interface
........................ .
M8255A Programmable Peripheral Interface (MIL) . . . . . . . . . . . . . . . . . . . . . . . . . . .
8257/8257-5 DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8259/8259-5 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8271 Floppy Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8273 SD LC Protocol Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8275 CRT Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8279/8279-5 Keyboard/Display Interface . . . . . . . . . . . . _ . . . . . . . . . . . . . . . . . _ ..

6-159
6-165
6-174
6-179
6-183
6-186
6-191
6-194
6-209
6-212
6-223
6-244
6-247
6-265
6-281
6-285
6-289
6-293

inter
8205
HIGH SPEED 1 OUT OF 8 BINARY DECODER
• 1/0 Port or Memory Selector

• Simple Expansion -

• Low Input Load Current - .25 mA
max., 1/6 Standard TTL Input Load
• Minimum Line Reflection - Low
Voltage Diode Input Clamp

Enable Inputs

• High Speed Schottky Bipolar
Technology -18ns Max. Delay

• Outputs Sink 10 mA min.
• 16-Pin Dual-In-Line Ceramic or
Plastic Package

• Directly Compatible with TTL Logic
Circuits

The 8205 decoder can be used for expansion of systems which utilize input ports, output ports, and memory components with active low chip select input. When the 8205 is enabled, one of its eight outputs goes
"low", thus a single row of a memory system is selected. The 3 chip enable inputs on the 8205 allow easy
system expansion. For very large systems, 8205 decoders can be cascaded such that each decoder can drive
eight other decoders for arbitrary memory expansions.
The Intel®8205 is packaged in a standard 16 pin dual-in-line package; and its performance is specified over
the temperature range of O°C to +75°C, ambient. The use of Schottky barrier diode clamped transistors to
obtain fast switching speeds results in higher performance than equivalent devices made with a gold diffusion process.

PIN CONFIGURATION

LOGIC SYMBOL

Ao

16

v·ce

Ao

A,

15

00

A,

A,

14

0,

A,

13

0,

12

03

11

°4

E,

07

10

05

E,

GRD

9

06

E3

4

E,

8205

8205

E,
6

E3

ADDRESS

PIN NAMES
,-------------~~

~!!~

fl- E3
00- 57

._ ADDRE~~~PUTS __
ENABLE INPUTS
DECODED OUTPUTS

6-159

ENABLE

AQ

A,

A,

E,

E2

E3

0

,

L
H
L
H
L
H
l
H
X
X
X
X
X
X
X

L
L
H
H
L
L
H
H
X
X
X
X
X
X
X

L
L
L
L
H
H
H
H
X
X
X
X
X
X
X

L
L
L
L
L
L
L
L
L
H
L
H
H
L
H

L
L
L
L
L
L
L
L
L
L
H
H
L
H
H

H
H
H
H
H
H
H
H
L
L
L
L
H
H
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

OUTPUTS

2

3

4

5

6

7

H
H
L
H
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

H
H
H
H
L

H

H
H
H
H

H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

H

H
H
H
H
H
H
H
H

H

H
H
H
H
H
H

H
H
H

H

H
H
H
L
H

H
H

H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H

8205

FUNCTIONAL DESCRIPTION
Decoder
The 8205 contains a one out of eight binary decoder. It ac·
cepts a three bit binary code and by gating this input, creates
an exclusive output that represents the value of the input
code.
For example, if a binary code of 101 was present on the AO,
A 1 and A2 address input lines, and the device was enabled,
an active low signal would appear on the 55 output line.
Note that all of the other output pins are sitting at a logic
high, thus the decoded output is said to be exclusive. The
decoders outputs will follow the truth table shown below in
the same manner for all other input variations.

AO

0;;

A,

0;

A,

0-;
0,
DECODER

a.
0;;
0,

Enable Gate

0;

When using a decoder it is often necessary to gate the outputs with timing or enabling signals so that the exclusive
output of the decoded value is synchronous with the overall
system.

ENABLE GATE

E;
E,

(E;·E2·E3)

E,

The 8205 has a built-in function for such gating. The three
enable inputs (Ei, E2, E3) are ANDed together and create
a single enable signal for the decoder. The combination of
both active "high" and active "low" device enable inputs
provides the designer with a powerfully flexible gating function to help reduce package count in his system.

ADDRESS

OUTPUTS

A,

A2

E,

E2

E3

0

1

2

3

4

5

6

7

L
H
L
H
L
H

L
L
L
L
H
H
H
H

X
X
X
X
X
X
X

X
X
X
X
X
X
X

X
X
X
X
X
X
X

L
L
L
L
L
L
L
L
L
H
L
H
H
L
H

L
L
L
L
L
L
L
L
L
L
H
H
L
H
H

H
H
H
H
H
H
H
H
L
L
L
L
H
H
H

L
H
H
H
H
H
H
H
H
H
H
H
H
H
H

H
L
H
H
H
H
H
H
H
H
H
H
H
H
H

H
H
L
H
H
H
H
H
H
H
H
H
H
H
H

H
H
H
L
H
H
H
H
H
H
H
H
H
H
H

H
H
.H
H
L
H
H
H
H
H
H
H
H
H
H

H

H

L
L
H
H
L
L
H
H

H
H
H
H
H
H
L
H
H
H
H
H
H
H
H

H
H
H
H
H
H
H
L
H
H
H
H
H
H
H

l

6-160

ENABLE

Ao

H

H
H
H
L

H
H
H
H
H
H
H
H
H

8205

ray of 8205s can be used to create a simple interface to a
24K memory system.

APPLICATIONS OF THE 8205
The 8205 can be used in a wide variety of applications in
microcomputer systems. I/O ports can be decoded from the
address bus, chip select signals can be generated to select
memory devices and the type of machine state such as in
8008 systems can be derived from a simple decoding of the
state lines (SO, S1, S2) of the 8008 CPU.

I/O Port Decoder
Shown in the figure below is a typical application of the
8205. Address input lines are decoded by a group of 8205s
(3). Each input has a binary weight. For example, AO is as·
signed a value of 1 and is the LSB; A4 is assigned a value of
16 and is the MSB. By connecting them to the decoders as
shown, an active low signal that is exclusive in nature and
represents the value of the input address lines, is available at
the outputs of the 8205s.
This circuit can be used to generate enable signals for I/O
ports or any other decoder related application.
Note that no external gating is required to decode up to 24
exclusive devices and that a simple addition of an inverter
or two will allow expansion to even larger decoder networks.

The memory devices used can be either ROM or RAM and
are 1K in storage capacity. 8308s and 8102s are the devices
typically used for this application. This type of memory de·
vice has ten (10) address inputs and an active "low" chip
select (CS). The lower order address bits AO-A9 which come
from the microprocessor are "bussed" to all memory ele·
ments and the chip select to enable a specific device or group
of devices comes from the array of 8205s. The output of
the 8205 is active low so it is directly compatible with the
memory components.
Basic operation is that the CPU issues an address to identify
a specific memory location in which it wishes to "write" or
"read" data. The most significant address bits A 1O-A 14 are
decoded by the array of 8205s and an exclusive, active low,
chip select is generated that enables a specific memory device. The least significant address bits AO·A9 identify a
specific location within the selected device. Thus, all ad'
dresses throughout the entire memory array are exclusive
in nature and are non-redundant.
This technique can be expanded almost indefinitely to sup·
port even larger systems with the addition of a few inverters
and an extra decoder (8205).

Chip Select Decoder
Using a very similar circuit to the I/O port decoder, an ar-

E,

oop-o,p-o,p-o,p-o,p-o,p-o,p-o,p--

Ao

00 0--

AO
A,

A,

A,

A,
8205

E,
E,

A,
EN

f--

r-- A,
r-- A,

0,0-8205

0,0--

EN

E,

O:;p-- CS,
o,p-- CS,

E,

0; 0 - - -

E,

0,0--.

E,

o,p-o;p-o,p-o,p-- CS l1
o;p-- CS'2
o,p-- CS 13

f--

Ao

r--

A,
A,

"

"

0 , 0 - - - 13
0,0--- 14

E,

0,0--- 15

00 0--

8205

PORT
NUMBERS

GNO

,.

E,

DoP-- C5,""4

E,

o,p-- CS'5

' - - Ao

o,p-- CS16

~A,

0,0--

"

0,0--- 19
0,0--0,0---

8205

2.

"

E,

0 , 0 - - 22

E,

0 , 0 - - - 23

6-161

CS n

o,fr--

CS'9

D.p...--.. CS20

E,

D,fr-- CS21

E,

a.p-- CS22
o;p.-- CS23

E,

24K Memory Interface

fr--

o,p-- CS'B

'---------- A,

8205

I/O Port Decoder

0;

0,0--- 17

_A,

E,

0,0-- CS,

"

E,

~Ao

0,0-- CS,

0,0-- CS3

E,

' - - A,

00

8205

0,0--

0,C>--

0 - - CSo

Ao

A,
A,

CHIP
SELECTS

8205

Logic Element Example
Probably the most overlooked application of the 8205 is
that of a general purpose logic element. Using the "on·chip"
enabling gate, the 8205 can be configured to gate its decoded outputs with system timing signals and generate
strobes that can be directly connected to latches, fl ip-flops
and one-shots that are used throughout the system.

and T2 decoded strobes can connect directly to devices like
8212s for latching the address information. The other decoded strobes can be used to generate signals to control the
system data bus, memory timing functions and interrupt
structure. RESET is connected to the enable gate so that
strobes are not generated during system reset, eliminating
accidental loading.

An excellent example of such an appl ication is the "state
decoder" in an 8008 CPU based system. The 8008 CPU issues three bits of information (SO, Sl, S2) that indicate the
nature of the data on the Data Bus during each machine
state. Decoding of these signals is vital to generate strobes
that can load the address latches, control bus discipline and
general machine functions.

The power of such a circuit becomes evident when a single
decoded strobe is logically broken down. Consider 11 output, the boolean equation for it would be:
T1

In the figure below a circuit is shown using the 8205 as the
"state decoder" for an 8008 CPU that not only decodes the
SO, Sl, S2 outputs but gates these signals with the clock
(phase 2) and the SYNC output of the 8008 CPU. The Tl

T1

T3
T'
T5

E3

,
6

WAIT

12

STOP
T1I

SYSTEM RESET

State Control Coding

~m
o
o
o.
0
1
1
1
1

1
1
0
0
0
1
1
0

=

(SO'Sl'S2)'(SYNC'Phase 2'Reset)

A six input NAND gate plus a few inverters would be needed to implement this function. The seven remaining outputs
would need a similar circuit to duplicate their function,
obviously a substantial savings in components can be
achieved when using such a technique.

5,

STATE

o· ~
1
1
0
0
0
1
1

T1I
T2
WAIT

T3
STOP
T'
T5

6-162

8205
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias:

'COMMENT

-65°C to "125° C
-65°C to +75°C

Ceramic
Plastic

Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

-65°C to +1600 C

Storage Temperature

-0.5 to +7 Volts

All Output or Supply Voltages

-1.0 to +5.5 Volts

All I nput Voltages

125 mA

Output Currents

D.C. CHARACTERISTICS

TA = O°C to +75°C, Vee = 5.0V ±5%

8205
PARAMETER

SYMBOL

-

LIMIT
MAX.
-0.25

MIN.

UNIT

TEST CONDITIONS

IF

INPUT LOAD CURRENT

mA

Vee = 5.25V, V F = 0.45V

IR

INPUT LEAKAGE CURRENT

10

~A

Vee = 5.25V, V R = 5.25V

Ve

INPUT FORWARD CLAMP VOLTAGE

-1.0

V

Vee

VOL

OUTPUT "LOW" VOLTAGE

V

Vee = 4.75V, IOL = 10.0 mA

VOH

OUTPUT HIGH VOLTAGE

V

Vee

V 1L

INPUT "LOW" VOLTAGE

V

Vee = 5.0V

0.45
2.4
0.85

V 1H

INPUT "HIGH" VOLTAGE

Ise

OUTPUT HIGH SHORT
CIRCUIT CURRENT

2.0

Vox

OUTPUT "LOW" VOLTAGE
@ HIGH CURRENT

lee

POWER SUPPLY CURRENT

-40

-120
0.8
70

= 4.75V, Ie = -5.0 mA
= 4.75V, IOH = -1.5 mA

V

Vee = 5.0V

mA

Vee = 5.0V, VOUT

V

Vee

mA

Vee = 5.25V

= OV

= 5.0V, lox = 40 mA

TYPICAL CHARACTERISTICS
OUTPUT CURRENT VS.
OUTPUT "LOW" VOLTAGE
100

TA "'25"C,,-t-

!

Vee'" S.OV

60

)

I
40

~
/, ~

~

TA '" 75"C-....,

20

o

H
o

.2

l.4

~

~

~

t-- Vee

-=

flV

s.nv

I

-10

TA '"

TA '" DOC

o°c-

--l--20

I--

TA '" O°C

.6

-40

!
.8

OUTPUT "lOW' VOL TAGE (V)

1.0

TA - DOC

TA '" 25"C

2.0

TA " 75<><;

J

1.0

3.0

4.0

OUTPUT "HIGH" VOLTAGE (V)

6-163

5.0

,2

f\ ~
H f..\1\
+--1

\

\

I

i

1\ 1\
\. _\ ~

I
2.0

,-

J.---.-

40

A

-50
1.0

Vee = S.Ov

3.0

1/

i

i -,-TA =25"C

.,

II

I- l-- ..

TA " 75°C

II

If

I-- f--

I

~

//f.

i;.. 25"C

J

-30

f-

DATA TRANSFER FUNCTION
5.0

I II

V

TA '" 75°C __

80

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

.4

.6

.8

1.0

1.2 1.4 1.6 1.8 2.0

INPUT VOL T AGE IV)

8205

SWITCHING CHARACTERISTICS

CONDITIONS OF TEST:

Input pulse amplitudes:

TEST LOAD:
390(2

2.5V

Input rise and fall times: 5 nsec
between 1 V and 2V
Measurements are made at 1.5V

All Transistors 2N2369 or Equivalent.

CL

=

30 pF

TEST WAVEFORMS
ADDRESS OR ENABLE
INPUT PULSE

OUTPUT

A.C. CHARACTERISTICS TA

=

oDe to +75°e, Vee

PARAMETER

SYMBOL

5.0V ±5% unless otherwise specified.
UNIT

MAX. LIMIT
18

t++

---------

~---.-----

ADDRESS OR ENABLE TO
OUTPUT DELAY

t

~~--

t+

18
--

18

--~-

t --

=

18

,

CIN (1/

INPUT CAPACITANCE

1. This parameter

------

IS

periodically sampled and

IS

TEST CONDITIONS
II
---~---+--------.

"'f

~-

--

ns

--

ns

4(ty~ I--I---;;F
5(typ I I
pF
I

P8205
C8205

- - - - - - - - - -------

---------------f" 1 MHz. Vee" OV

vBIAS - 2.0V. TA - 25°C

not 100% tested.

TYPICAL CHARACTERISTICS
ADDRESS OR ENABLE TO OUTPUT
DELAY VS. LOAD CAPACITANCE

ADDRESS OR ENABLE TO OUTPUT
DELAY VS. AMBIENT TEMPERATURE

20r---,---,---,-----,

20.------.-------.-[.-----.

Vee

=

5.0V

Vee

TA = 25"C

cl

15r---+1---+\~;~--~-~~~~

15

eo 5.0V
'" 30 pF

-------+-----+---~

t._t

10

t===::t===t====1

5 ~-----+-----+---

uL-_ _L -_ _

o

50

~

100

_ _ _J -_ _ _

150

oL-______L -_ _ _ _ _J-·_ _ _ _ _
o
25
50

~

200

AMBIENT TEMPERATURE (OCt

LOAD CAPACITANCE (pF)

6-164

~

75

inter
8212

EIGHT-BIT INPUT/OUTPUT PORT
Fully Parallel 8-Bit Data Register
• and
Buffer
Service
Flip-Flop for
• InterruptRequest
Generation
Low Input Load Current - .25 rnA Max.
• Three
Outputs
• OutputsState
Sink
15 rnA
•

Output High Voltage for Direct
• 3.65V
Interface to 8080 CPU or 8008 CPU
Register Clear
• Asynchronous
Replaces
Buffers,
Latches and Multi• plexers in Microcomputer
Systems
Reduces
System
Package
Count
•

The 8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device is multimode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with this device.
PIN CONFIGURATION

LOGIC DIAGRAM
SERVICE REOUEST FF

os,

Vee

MD

INT

DI,

Dis

DO,

DOs

01 2

01 7

00 2

D0 7

DI3

01 6

00 3

00 6

01.

015

DO.

005

STB

CLR

GND

DS 2

\

jg)

DS2

~ MD

--4iH_.1

III> STB - -........--{_.J

[DD12 -------~~

[E>D14 --------I-~

PIN NAMES
Dll·D~~ ~_~NUT

~O,.D?"-

DSi·DS,

r-ffi-INT
ClR

[j]> D 15 --------+-+1

----

DEVICE SELECT
MODE

[j]> D 16 --------+-1-1

CsiROBE-"--""INTERRUPT (~CTIVE LOW)
CLEAR (ACTIVE LOW)

gg::. DI7 --------+-+1

gp D1 8 - - - - - - - - l . . . - + I
! E > C L R - - - - - - < t ! ~+-_..J-....J
(ACTIVE LOW)

6-165

OUTPUT
BUFFER

8212
FUNCTIONAL DESCRIPTION
Data Latch
The 8 flip-flops that make up the data latch are of a
"0" type design. The output (a) of the flip-flop will
follow the data input (0) while the clock input (e) is
high. Latching will occur when the clock (e) returns
low.
The data latch is cleared by an asynchronous reset
input (CLR). (Note: Clock (C) Overides Reset (CLR).)
Output Buffer
The outputs of the data latch (a) are connected to
3-state, non-inverting output buffers. These buffers
have a common control line (EN); this control line
either enables the buffer to transmit the data from
the outputs of the data latch (a) or disables the
buffer, forcing the output into a high impedance
state. (3 -state)
This high-impedance state allows the designer to
connect the 8212 directly onto the microprocessor
bi-directional data bus.

Service Request Flip-Flop
The (SR) flip-flop is used to generate and control
interrupts in microcomputer systems. It is asynchronously set by the eLR input (active low). When
the (SR) flip-flop is set it is in the non-interrupting
state.
The output of the (SR) flip-flop (a) is connected to
an inverting input of a "NOR" gate. The other input
to the "NOR" gate is non-inverting and is connected
to the device selection logic (OS1 • OS2). The output
of the "NOR" gate (INT) is active low (interrupting
state) for connection to active low input priority
generating circuits.

SERVICE REOUEST FF

\
lIT> OS2
[?> MO

lIT> STB

I

Control Logic
The 8212 has control inputs OS1, OS2, MO and
STB. These inputs are used to control device selection, data latching, output buffer state and service
request flip-flop.

001

DATA LATCH
@>012

[2:> 01 3

MD (Mode)
This input is used to control the state of the output
buffer and to determine the source of the clock input
(C) to the data latch.
When MO is high (output mode) the output buffers
are enabled and the source of clock (e) to the data
latch is from the device selection logic (OS1 • OS2).
When MO is low (input mode) the output buffer state
is determined by the device selection logic (OS1 .
OS2) and the source of clock (e) to the data latch is
the STB (Strobe) input.

II§> 0 16

STB (Strobe)
This input is used as the clock (e) to the data latch
for the input mode MO = 0) and to synchronously
reset the service request flip-flop (SR).

I~

[I>011

DS1, DS2 (Device Select)
These 2 inputs are used for device selection. When
OS1 is low and OS2 is high (DS1 . OS2) the device is
selected. In the selected state the output buffer is
enabled and the service request flip-flop (SR) is
asynchronously set.

[1>01,

1I§>015

~D17

@t>018

iE>CLR
(ACTIVE LOWI

~--

j

-~-

CLR - RESETS DATA LATCH

Note that the SR flip-flop is negative edge triggered.
6-166

OUTPUT
BUFFER

SETS SR FUP·FLOP
(NO EFFECT ON OUTPUT BUFFER)

L1>

8212

Applications Of The 8212 -- For Microcomputer Systems
II
III
IV
V
VI

Basic Schematic Symbol
Gated Buffer
Bi-Directional Bus Driver
Interrupting Input Port
Interrupt Instruction Port
Output Port

VII
VIII
IX

8080 Status Latch
8008 System
8080 System:
8 Input Ports
8 Output Ports
8 Level Priority Interrupt

I. Basic Schematic Symbols
Two examples of ways to draw the 8212 on system
schematics-(l) the top being the detailed view
showing pin numbers, and (2) the bottom being the
symbolic view showing the system input or output

as a system bus (bus containing 8 parallel lines).
The output to the data bus is symbolic in referencing 8 parallel lines.

BASIC SCHEMATIC SYMBOLS
OUTPUT DEVICE

INPUT DEVICE

DI

16
18
20

11
STB

11
3

DO

8212

5
10
15
17
19

DI

16
18
20
22
23

(DETAILED)

GND
INPUT
STROBE-------;:=L---,

STB

DO

4
6
10
15
17
19

8212

14

Vee

SYSTEM
INPUT

OUTPUT
FLAG

SYSTEM
OUTPUT

(SYMBOLIC)

GND

DATA BUS

GATED BUFFER

II. Gated Buffer ( 3 - STATE)

3-STATE

The simplest use of the 8212 is that of a gated
buffer. By tying the mode signal low and the strobe
input high, the data latch is acting as a straight
through gate. The output buffers are then enabled
from the device selection logic DS1 and DS2.
When the device selection logic is false, the outputs

vee

-~--------,

r-~S~TB::--'

INPUT
DATA
(250 ~A)

8212

are 3-state.
When the device selection logic is true, the input
data from the system is directly transferred to the
output. The input data load is 250 micro amps. The
output data can sink 15 milli amps. The minimum
high output is 3.65 volts.

'------<:4 CLR
GATING {
CONTROL
(D51.052)

6-167

----------'

OUTPUT
DATA
(15mA)
(3.65V MIN)

8212

III. Bi-Directional Bus Driver

BI·DIRECTIONAL BUS DRIVER

A pair of 8212's wired (back-to-back) can be used
as a symmetrical drive, bi-directional bus driver.
The devices are controlled by the data bus input
control which is connected to D81 on the first 8212
and to DS2 on the second. One device is active, and
acting as a straight through buffer the other is in
3-state mode. This is a very useful circuit in small
system design.

STB

DATA
BUS

"-

}

,1

8212

-0

v

DATA
BUS

---< Ci:R
DATA BUS
CONTROL
(0= L - R)
(I = R -

-

y

G~D L--.....

L)

STB

8212

L

('l

CLR

~

f-Y
GND

INTERRUPTING INPUT PORT

IV. Interrupting Input Port
This use of an 8212 is that of a system input port
that accepts a strobe from the system input source,
which in turn clears the service request flip-flop
and interrupts the processor. The processor then
goes through a service routine, identifies the port,
and causes the device selection logic to go trueenabling the system input data onto the data bus.

DATA
BUS

INPUT
STROBE
STB

SYSTEM
INPUT

SYSTEM
RESET
{
PORT
SELECTION
(DS1.DS2)

- - - - -....

~_ _ _ T~C~~~~R~~~)CKT
OR
TO CPU
INTERRUPT INPUT

INTERRUPT INSTRUCTION PORT

V. Interrupt Instruction Port
The 8212 can be used to gate the interrupt instruction, normally RESTART instructions, onto the data
bus. The device is enabled from the interrupt
acknowledge signal from the microprocessor and
from a port selection signal. This signal is normally
tied to ground. (D81 could be used to multiplex a
variety of interrupt instruction ports onto a common bus).

DATA
BUS
STB

RESTART
INSTRUCTION
(RST 0 - RST 7)

(DSI) PORT SELECTION
INTERRUPT ACKNOWLEDGE _ _- - - . . J

6·168

8212

VI. Output Port (With Hand-Shaking)

OUTPUT PORT (WITH HAND-SHAKING)

The 8212 can be used to transmit data from the data
bus to a system output. The output strobe could be
a hand-shaking signal such as "reception of data"
from the device that the system is outputting to, It
in turn, can interrupt the system signifying the reception of data, The selection of the port comes
from the device selection logic, (OS1· OS2)

DATA
BUS
, - - - - OUTPUT STROBE
STB

SYSTEM OUTPUT

SYSTEM RESET

l
SYSTEM
INTERRUPT

PORT SELECTION
~ (LATCH CONTROL)

~-----J (DS1.DS2)

VII. 8080 Status Latch
Here the 8212 is used as the status latch for an 8080
microcomputer system, The input to the 8212 latch
is directly from the 8080 data bus, Timing shows
that when the SYNC signal is true, which is connected to the OS2 input and the phase 1 signal is
true, which is a TTL level coming from the clock
generator; then, the status data will be latched into
the 8212,

Note: The mode signal is tied high so that the output
on the latch is active and enabled all the time,
It is shown that the two areas of concern are the
bidirectional data bus of the microprocessor and the
control bus,

8080 STATUS LATCH

~
D,

D2

DBIN

ov..J

'-

,~

- DATA BUS

---+---

19

t2Z--

¢2
22

n

II

4

D5 5
D6 6
D7

SYNC

12V

,..

7

D3 3
D4

8080

¢1

10
9
8

STATUS
LATCH

15

'-4
5

~

CLOCK GEN,
& DRIVER

D,

Do

'-------J

--

~TL}

9
16
18
20
22

~

~

+a-'i5
'17
t19

8212

~

CLR

t-=-

INTA
WO
STACK
HLTA
OUT
Ml
INP
MEMR

Tl
11
BASIC
¢2
CONTROL
BUS
SYNC

11 DS2 MD DS,
13 12

DATA

'( 1
DBIN

STATUS

6-169

T2

8212
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias Plastic .. - 65°C to + 75°C
Storage Temperature .......... -65°C to +160°C
All Output or Supply Voltages

.. - 0.5 to + 7 Volts

All Input Voltages. . .

. . -1.0 to 5.5 Volts

Output Currents. . . .

. ................ 125 mA

D.C. CHARACTERISTICS
TA = O°Cto +75°C

Symbol

Vee = +5V ±5%

,

Limits

Parameter
Min.

Typ.

Unit

Test Conditions

Max.
~,---.

IF

Input Load Current
ACK, OS" CR, 01 ,-01 8 Inputs

-.25

mA

VF = .45V

IF

Input Load Current
MO Input

-.75

rnA

VF = .45V

IF

Input Load Current
OS, Input

-1.0

mA

VF = .45V

IR

Input Leakage Current
ACK, OS, CR, 01,-01 8 Inputs

10

VA

VR = 5.25V

IR

Input Leakage Current
MO Input

30

ILA

VR = 5.25V

IR

Input Leakage Current
DS, Input

40

/J,A

V R = 5.25V

Ve

Input Forward Voltage Clamp

-1

V

.85

V

.45

V

VIL

Input "Low" Voltage

V,H

Input "High" Voltage

VOL

Output "Low" Voltage

2.0

VOH

Output "High" Voltage

3.65

Ise

Short Circuit Output Current

-15

[Ioi

Output Leakage Current
High Impedance State

lee

Power Supply Current

Ic= -5mA

V

4.0

6-170

V

IOH = -1 mA

mA

Vo = 0 V

20

MA

Vo = .45V/5.25V

130

rnA

-75

90

I

IOL = 15 mA

8212
TYPICAL CHARACTERISTICS

INPUT CURRENT VS. INPUT VOLTAGE

-50

~

-+----+-

+----r-- t - - -

I

>-

ii'

V TA "25'C
V TA "75'C

/

TA '"

~ -150

--~

f"'"

100

::>
u

Vee'" +5.0V

--

-t-1>a"c
:'i

'00,----,,----,----,----,

~~

Vee'" !s.ov

OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE

-200

I
f---t-

I

-250

~-~l~-

-300
-3

.,

-,

-2

'2

INPUT VOLTAGE IV)

OUTPUT 'lOW" VOLTAGE (V)

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE

50,---,--,---,--,---,---,
Vee

=;

+5.0V

T A " 25 C

I

,

4°1---r-~-I----T-

-r---1~i~+--

30 - - - -

I

20

'\.'''';.--

--+--~~-~---~'--T~-+--~

'0 ~---+--+--

°O~--~--~~-~-~~-~~~300
OUTPUT "HIGH' VOLTAGE (V)

LOAD CAPACITANCE (pF)

DATA TO OUTPUT DELAY
VS. TEMPERATURE
2

o
>-

~

B

>-

::>

a

g

"c>"

.5 OV

I

It--

6

Vee

I+-r---/!

35

--+----~-----~-I--I
./'
i

a

ii'>-

vee"

WRITE ENABLE TO OUTPUT DELAY
VS. TEMPERATURE
40,---,---,---,----,--eo

+5.0V

----i---r---r----)------

30r---t---+----t-----r---1

. . ~><;/

---,-----:;;.~~-, ----+----1
.... -'"
t - _I

4~--+-~~-~-+i~~~~___j

I

I

I

I

'5r----t---t---i---+---;

2~--t---+---~----L---1

'OL-__
__ 25
-25
~

I

~--J----L---"

50

75

.

-

'O.L---~--~--~--~--~

'00

~

TEMPERATURE reI

~

TEMPERATURE

6-171

r C)

~

8212
TIMING DIAGRAM

15VX---------Y.5V
!---'PW
-'1'- _ _ _

DATA

_____ -1.

STB

0'

l

Ir-

[ls1 .

=:1 r

_ _ _ _ _ _ _ _ _ _ _ _~
___
'W_E

OUTPUT

[lsI'

_______ _

)<.1._5_________
V
_
\1.5V

_ _ _ _ _ _ _ _ _ _ _ _ _..

1.5Vi

DS2

_________l_'E_~ r _

OUTPUT

'H--l

15Vl -----..\\,.1_5V________

DS2

_______

X

~~~~W1_ _ ~-'-D-____1-""---~:-==-=~-.-

I'PW~

15V\

CLR

115V

_______
1. _ _'_C_........,·1 ,

____ _

1_5V_______

DO

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _/ \...

"" ----~":f--,=-~~-~"- -1~"~-ST8 or 051. DS2

""""' ______ ~~'k":----------.
!\15V
e---,PW
'--------------------

STB

----~

NOTE: ALTERNATIVE TEST LOAD

-=cl

VCC'OK

OUT

CL

_"

6·172

8212
A.C. CHARACTERISTICS
TA

=

O°C to +75°C

Symbol

Vee

=

+5V ± 5%
Limits

Parameter
Min.

Typ.

Unit
ns

Pulse Width

tpd

Data To Output Delay

30

ns

twe

Write Enable To Output Delay

40

ns

t,ot

Data Setup Time

15

ns

th

Data Hold Time

20

ns

t

Reset To Output Delay

40

ns

t,

Set To Output Delay

30

ns

te

Output Enable/Disable Time

45

ns

tc

Clear To Output Delay

55

ns

Symbol

30

V"AS

= 2.5V

Vee

=

+5V

TA

= 25°C
LIMITS

Test

Typ.

Max.

C'N

OS, MD Input Capacitance

9 pF

12 pF

C'N

OS" CK, ACK, 01,-01,
Input Capacitance

5 pF

9 pF

C OUT

00,-00, Output Capacitance

8 pF

12 pF

·This parameter is sampled and not 100% tested.

SWITCHING CHARACTERISTICS
CONDITIONS OF TEST
Input Pulse Amplitude = 2.5 V
Input Rise and Fall Times 5 ns
Between 1V and 2V Measurements made at 1.5V
with 15 mA & 30 pF Test Load

TEST LOAD
15mA & 30pF

300

TO
D.U.T.
*30pF

I

600

* INCLUDING JIG & PROBE CAPACITANCE

6-173

I

r

tpw

CAPACITANCE* F = 1 MHz

Test Conditions

Max.

M8212
EIGHT-BIT INPUT/OUTPUT PORT
II

Fully Parallel 8-Bit Data Register
and Buffer

II

Service Request Flip-Flop for Interrupt
Generation

II

3.4V Output High Voltage for Direct
Interface to M8080A CPU

II

Asynchronous Register Clear

II

Replaces Buffers, Latches and Multiplexers in Microcomputer Systems
Reduces System Package Count

II

Low Input Load Current: .25 rnA Max.

II

Three-State Outputs

II

II

Full Military Temperature Range -55°C
To +125°C

II

±10% Power Supply Tolerance

II

24-Pin Dual In-Line Package

The M8212 input/output port consists of an 8-bit latch with 3-state output buffers along with control and device selection
logic. Also included is a service request flip-flop for the generation and control of interrupts to the microprocessor.
The device is multi mode in nature. It can be used to implement latches, gated buffers or multiplexers. Thus, all of the principal peripheral and input/output functions of a microcomputer system can be implemented with this device.

PIN CONFIGURATION

os,

vee

MD

INT

01,

01.

DO,

DDs

01 2

01,

00 2

DO,

01 3

01 6
00 6

00 3
01 4

015

DO.

0°5

STB

CLR

GND

DS 2

PIN NAMES

M8212
ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias ........ -55°C to +125°C
Storage Temperature

.......... -65°C to +160°C

All Output or Supply Voltages .... -0.5 to +7 Volts
All Input Voltages

............ -1.0t05.5Volts

Output Currents ...................... 125 mA

D.C. CHARACTERISTICS
TA

= -55°C to +125°C

Symbol

Vee

= +5V

±10%
Limits

Parameter
Min.

Typ.

Unit

Test Conditions

Max.

IF

Input Load Current
ACK, OS" CR, 01,-01, Inputs

-.25

mA

VF

= .45V

IF

Input Load Current
MO Input

-.75

mA

VF

=

.45V

IF

Input Load Current
OS, Input

-1.0

mA

VF

=

.45V

IR

Input Leakage Current
ACK, OS, CR, 01,-01 8 Inputs

10

/k A

VR = Vee

IR

Input Leakage Current
MO Input

30

p,A

VR = Vee

IR

Input Leakage Current
OS, Input

40

p,A

VR = Vee

Ve

Input Forward Voltage Clamp

-1.2

V

VIL

Input "Low" Voltage

.80

V

.45

V

-75

mA

Vec = 5.0V

20

p,A

Vo

145

mA

VIH

Input "High" Voltage

VOL

Output "Low" Voltage

2.0

VOH

Output "High" Voltage

3.4

los

Short Circuit Output Current

-15

1101

Output Leakage Current
High Impedance State

---

Icc

Power Supply Current

Ie = -5 mA

V
4.0

90

6-175

V

IOL = lOrnA
10H = -.5mA

= .45V to Vee

L

M8212
A.C. CHARACTERISTICS
T A = -55°e to +125°e

Symbol

Vee = +5V ±10%

Limits

Parameter
Min.

Unit

Test Conditions

Max.

tpw

Pulse Width

tpD

Data To Output Delay

30

ns

NOTE 1

tWE

Write Enable To Output Delay

50

ns

NOTE 1

tSET

Data Setup Time

20

ns

tH

Data Hold Time

30

ns

tR

Reset To Output Delay

55

ns

NOTE 1

ts

Set To Output Delay

35

ns

NOTE 1

ns

40

---- --

tE

Output Enable/Disable Time

50

ns

NOTE 1

tc

Clear To Output Delay

65

ns

NOTE 1

CAPACITANCE

F

Symbol

lMHz

VSIAS

2.5V

Vee

+5V TA

25°C

LIMITS

Test

Typ.

Max.

elN

OS, MD Input Capacitance

9 pF

12 pF

C'N

DS 2 ,CLR,STB, DI,-DI,
Input Capacitance

5 pF

9 pF

COUT

DO,-DO, Output Capacitance

8 pF

12 pF

SWITCHING CHARACTERISTICS
CONDITIONS OF TEST
Input Pulse Amplitude = 2.5V
Input Rise and Fall Times: 5 ns between 1V and 2V

TEST LOAD
vee

R,

TO
D.U.T.

I-=
NOTE 1:

CL

R,

R2

tpD, tWE, tR, ts, tc

30pF

300[1

600[1

tE, ENABLEt

30pF

10K[I

1K[I

tE, ENABLEt

30pF

300[1

600[1

tE, DISABLEt

5pF

300[1

600[1

tE, DISABLE<

5pF

10KD.

1K[I

TEST

6-176

R2
CL

-=

M8212
TIMING DIAGRAM

15vA--------*'5v

Dala

- - - - - - - - -./ .
STBO.OS,.DS,

ir=='pw------I-- 'H=::.! '--- \~"5V_______

'5vl

________L_'wE---,~I/--------

OUTPUT

OS, e05 2

________________ JX~,.5V______

+_MD______________
'5Vj

' \15V_____

l-lE1r-______ l.:=~~----'--

OUTPUT

-----------~5V

~~~=::=

I-,pwi
'5V \

1'---,.5v- -

I..

DO

"I r - - - - -

'e

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~\'___'.5V_ _
'5V ~--------*'bV

DATA

--------~~'SET-'5VT
STB 0. OS, . OS,

I

'"

~'-----

'\

____________k--_'P_D=J r - - -- ----____________
OUTPUT _ _ _ _ _ _ _ _ _ _ _ -I*('-'.5_V_ _ _ _ _ _ _ _ _ _ _ __

STB

'.5Vr\1.5V

---------' I-,pw-! '------------1.SV

1.SV

"--________
1.SV

~'R-I

6-177

-..J

M8212
TYPICAL CHARACTERISTICS
INPUT CURRENT VS. INPUT VOLTAGE
Vee

=

OUTPUT CURRENT VS. OUTPUT "LOW" VOLTAGE
100r-------~------.-------_r------_,

~~

15.ov

-50

Vee'" +5.0V

80r-------+-------~-------r-------_i

"" .......
~ -100

~
a:

/

/T A "'25C
/ TA =75C

T A '" O"C

f-

-150

:J

"

40r-------+-------~~~~-r------_i

f-

Ii:
~

-200
20~------~--~~~------+------_4

-250

-300

-3

-2

-1

'2

"

'3
OUTPUT "LOW" VOL TAGE (V)

INPUT VOL TAGE (V)

OUTPUT CURRENT VS.
OUTPUT "HIGH" VOLTAGE

DATA TO OUTPUT DELAY
VS. LOAD CAPACITANCE
50
Vee =.
TA

=

~5,OV

25 C

40

]
;;'

>-

E

~

f-

a

~
cr

r

"
f-

"0

:J

;0

30

~

:J

ii'f-

~

0

20

~--

~

a

10

0

0

vee" +5.0V
0

35

>-

~

/'
18

16

:J

0

0

f-

"""" --

30

~
:J

"..

0
0

"
'..--

'"
'"-<

~~

--- I--

-- ------ ~I-\",;.--

75

100

8214
i

PRIORITY INTERRUPT CONTROL UNIT
• Eight Priority Levels
• Current Status Register
• Priority Comparator

r

• Fully Expandable
• High Performance (50ns)
• 24-Pin Dual In-Line Package

The 8214 is an eight level priority interrupt control unit designed to simplify interrupt driven microcomputer
systems.
The PICU can accept eight requesting levels; determine the highest priority, compare this priority to a software controlled current status register and issue an interrupt to the system along with vector information to
identify the service routine.
The 8214 is fully expandable by the use of open collector interrupt output and vector information. Control
signals are also provided to simplify this function.
The PICU is designed to support a wide variety of vectored interrupt structures and reduce package count
in interrupt driven microcomputer systems.

LOGIC DIAGRAM

PIN CONFIGURATION
[IT> U R - - Bo

2'

Vee

iTI>ETlC--

B,

23

ECS

[1D

B,

22

R,

REQUEST ACTIVITY

liD
@>

SGS

21

R6

INT

20

Rs

ClK

19

R,

INTE

18

R3

Ao

17

R,

16

R,

15

Ro

liD
[1D

~
~

8214

A,
A,

10

ElR

11

GND

12

IE>
IT>
CD

CD

13

R;
R,
R,

(OPEN COLLECTOR)
REQUEST

AND
PRIORITY
ENCODER

II>

R5

[iD

"6

r--.t+=t.~f------- ENLG[E>

R,

(OPEN
COLLECTOR)

-t>~-INT
Bo

B,

}B

li2

I

--"

ReOUEST LEVelS (R7 HIGHEST PRIORITY)
CURRENT STATUS

SGS
ill

STATUS GROUP SELECT

INTE

ill

INTERRUPT ENABLE
CLOCK UNT F·F)

EIR

ENABLE lEVEL READ

ETLG

ENABLE THIS LEVEL GROUP

OS>

1-

INTE------------------"------~l

[D eLK

ENABLE CURRENT STA"JUS

I

::J

Ao·A2

REQUEST lEVELS

OPEN

fNf

INTERRUPT (ACT. lOW) ]

COLLECTOR

ENLG

ENABLE NEXT LEVEL GROUP

I

PRIORITY
COMPARATOR

[Q> ECS

--------",,:

INPUTS
---

Ro-R7
8 0.8 2

OUTPUTS:

CD

LATCH

ETlG

PIN NAMES
--

",

[D SGS

ENLG

"

Ro

6-179

"""

J

I

ID

8214

D.C. AND OPERATING CHARACTERISTICS
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias. . . . . . . . . . . . .. O°C to 70°C
Storage Temperature . . . . . . . . . . . . . -65°C to +150°C
All Output and Supply Voltages. . . . . . .. -0.5V to + 7V
All Input Voltages . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . .. 100 mA

TA = o°c to + 70°C, Vee = 5V ±5%.
Symbol

Parameter

Ve

Input Clamp Voltage (all inputs)

IF

Input Forward Current:

ETLG input
all other inputs

IR

Input Reverse Current:

ETLG input
all other inputs

VIL

Input LOW Voltage:

all inputs

VIH

Input HIGH Voltage:

all inputs

Icc

Power Supply Current

VOL

Output LOW Voltage:

all outputs

VO H

Output HIGH Voltage:

ENLG output

los

Short Circuit Output Current: EN LG output

leEx

Output Leakage Current: INT and AO·A 2

Min.

Limits
TypJ1J

-.15
-.08

Max.

V

le=-5mA

-0.5
-0.25

mA
mA

VF=0.45V

80
40

/1A
/1A

VR=5.25V

0.8

V

Vee=5.0V

V

Vee=5.0V

90

130

mA

See Note 2.

.3

.45

V

IOL =15mA

V

IOH=-lmA

2.4

3.0

-20

-35

6-180

Conditions

-1.0

2.0

NOTES:
1. Typical values are for T A ~ 25° e, Vee ~ 5.0V.
2. 80.82, SGS, eLK, FiQ.R4 grounded, all other inputs and all outputs open.

Unit

-55

mA

Vos=OV, Vee=5.0V

100

/1A

Ve EX=5.25V

-

8214
A.C. CHARACTERISTICS AND WAVEFORMS
Symbol

TA = o°c to +70°C, vcc = +5V ±5%

Parameter

Min.

Limits
Typ,£1J

I

I

Max.

Unit

tCY

ClK Cycle Time

80

50

ns

tpw

ClK, ECS, INT Pulse Width

25

15

ns

tlSS

INTE Setup Time to ClK

16

12

ns

tlSH

INTE Hold Time after ClK

20

10

ns

tETCS[2J

ETlG Setup Time to ClK

25

12

ns

tETCH[2J

ETlG Hold Time After ClK

20

10

ns

tECCS[2J

ECS Setup Time to ClK

80

50

ns

tEcCH [3J

ECS Hold Time After ClK

tECRS[3J

ECS Setup Time to ClK
ECS Hold Time After ClK

0

tECSS[2J

ECS Setup Time to ClK

75

tECSH [2J

ECS Hold Time After ClK

toCS[2J

SGS and Bo ·B 2 Setup Time to ClK

tOCH[2J

SGS and Bo·B 2 Hold Time After ClK

ns

0

tECRH[3J

110

70

ns

70

ns
ns

0
70

ns

50

ns

0

tRCS[3J

RO·R 7 Setup Time to ClK

tRCH[3J

Ro ·R 7 Hold Time After ClK

0

tiCS

INT Setup Time to ClK

55

tCI

ClK to I NT Propagation Delay

tRIS[4J

Ro ·R 7 Setup Time to INT

10

0

ns

tRIH [4J

RO·R 7 Hold Time After INT

35

20

ns

tRA

Ro ·R 7 to A O·A 2 Propagation Delay

80

100

ns

tELA

ElR to A O·A 2 Propagation Delay

40

55

ns

tECA

ECS to A O·A 2 Propagation Delay

100

120

ns

35

70

ns

90

ns

55

ns
ns

35
15

ns

25

tETA

ETlG to A O·A 2 Propagation Delay

tOECS[4J

SGS and Bo·B 2 Setup Time to ECS

15

10

tOECH [4J

SGS and Bo·B2 Hold Time After ECS

15

10

tREN

RO·R 7 to ENlG Propagation Delay

tETEN

ETlG to EN lG Propagation Delay

20

25

ns

tECRN

ECS to ENlG Propagation Delay

85

90

ns

tECSN

ECS to ENlG Propagation Delay

35

55

ns

---_._----- f--:-

I

r

45

ns
ns
70

I

ns

.-

CAPACITANCE [51

Symbol
CIN
COUT

Min.

Parameter
Input Capacitance

TEST CONDITIONS: VBIAS

= 2_5V,

Vcc

Max

I

Unit

5

10

I

pF

7

Output Capacitance

= 5V, TA = 25°C, f = 1 MHz

NOTE 5. This parameter is periodically sampled and not 100% tested.

6-181

j

Limits
Typ,£11

12

I

I

pF

8214
WAVEFORMS

x-------

'1:-----------------'1."'______ Jj'
._-----,
tRCH

tRCS

ETLG

-------

I

--""1...---------

-J

l

lETCH

------- ... -- --------XIX----- ----------r---- ,
"~

"1

tlss

...

-"J

fiSH

-------JFpP ElR
ITI> ETLG
REOUEST ACTIVITY

SGS

21

INT

20

R,

elK

19

R,

INTE

18

R3

Ao

17

R,

liD
liD

R6

A,
A,
ELR

10
11

GND

PIN NAMES

8 0 .82

SGS

R,

15

Ro

,.

ENLG

13

ETLG

R,

QD

R,

liD

1-------'==0--- A,

R4
R,

R6

~

R,

[D

Bo

CD

B,

A>8

II>

8,

CD

SGS

@}>

Ees

}B
PRIORITY

COMPARATOR

CC>

INTE------------------ClK-----------------------

INTE

CLOCK (lNT F-FI

ElFi

ENABLE LEVEL READ

ETlG

ENABLE THIS lEVEL GROUP

I
I

OUTPUTS:
REQUEST lEVELS
l
INTERRUPT (ACT. LOW)

j

OPEN

COLLECTOR

I

ENABLE NEXT LEVEL GROUP

6-183

CD
CD
[fD

--ENlG[E>

Q[>

CD<

AO-A2

A-,

----I

STATUSGROUPSELECT
ENABLE CURRENT STAl"US
INTERRUPT ENABLE

INT

(OPEN COLLECTOR)
REQUEST
LATCH
AND

~~~~!~~ ~~:~~~ (R 7 HIGHEST PRIORITYII

INPUTS

~R7

16

R,

@>

12.2>
Gi>

M8214

Ao

"liNT CD

~

J

M8214

D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . -65°C to +160°C
All Output and Supply Voltages ........ -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents . . . . . . . . . . . . . . . . . . . . .. 100 mA

Symbol

Parameter

Vc

Input Clamp Voltage (all inputs)

IF

Input Forward Current:

ETLG input
all other inputs

IR

Input Reverse Current:

ETLG input
all other inputs

Vil

Input LOW Voltage:

all inputs

VIH

Input HIGH Voltage:

all inputs

Icc

Power Supply Current

Val

Output LOW Voltage:

all outputs

VOH

Output HIGH Voltage:

ENLG output

los

Short Circuit Output Current: EN LG output

ICEX

Output Leakage Cu rrent: I NT, Ao, Alo A2

Min.

Limits
Typ.f1]

-.15
-.08

Max.

V

IC=-5mA

-0.5
-0.25

mA
mA

VF=0.45V

80
40

pA
pA

VR=5.5V

V

VCC=5.0V

V

VCC=5.0V

0.8

90

130

mA

.3

.'15

V

IOL =10mA

V

IOW- 1mA

-55

mA

Vcc=5.0V

100

pA

VCEX=5.5V

2.4

3.0

-15

-35

1. Typical values are for TA = 25"C, VCC= 5.0V.
2. 80.82, SGS, ClK, R(j.R4 grounded, all other inputs and all outputs open.

6-184

Conditions

-1.2

2.0

NOTES:

Unit

See Note 2.

M8214

A.C. CHARACTERISTICS

TA = _55°C to +125°C, VCC = +5V ±10%

Symbol

Parameter

Min.

Limits
Typ.llJ

Max.

Unit

tCY

ClK Cycle Time

85

tpw

ClK, ECS, INT Pulse Width

25

15

ns

tlSS

INTE Setup Time to ClK

16

12

ns

tlSH

INTE Hold Time after ClK

20

10

ns

tETCS[21

ETlG Setup Time to ClK

25

12

ns

tETCH[21

ETlG Hold Time After ClK

20

10

ns

tECCS[21

ECS Setup Time to ClK

85

25

tECCH[31

ECS Hold Time After ClK

tECRS[31

ECS Setup Time to ClK

ns

ns

0
110

ns
70

ns

70

ns

tECRH [31

ECS Hold Time After ClK

0

tECSS[21

ECS Setup Time to ClK

85

tECSH [21

ECS Hold Time After ClK

toCS[21

SGS and 8 0 .82 Setup Time to ClK

tOCH[21

SGS and 8 0 .8 2 Hold Time After ClK

tRCS[31

Ro ·R 7 Setup Time to ClK

tRCH[31

Ro ·R 7 Hold Time After ClK

0

tiCS

INT Setup Time to ClK

55

tCI

ClK to INT Propagation Delay

tRIS[41

Ro ·R 7 Setup Time to INT

10

0

tRIH[41

Ro ·R 7 Hold Time After INT

35

20

0
90

ns
50

ns

0
100

ns
55

ns
ns

35
15

80

ns
30

ns
ns
ns

100

ns

tRA

Ro ·R 7 to Ao-A2 Propagation Delay

tELA

ElR to Ao-A2 Propagation Delay

40

55

ns

tECA

ECS to Ao-A2 Propagation Delay

100

130

ns

tETA

ETlG to Ao-A2 Propagation Delay

35

70

ns

--

tOECS[41

SGS and 8 0 .8 2 Setup Time to ECS

20

10

tOECH[41

SGS and 8 0 -82 Hold Time After ECS

20

10

tREN

Ro-R7 to EN lG Propagation Delay

45

70

ns

tETEN

ETlG to ENlG Propagation Delay

20

30

ns

tECRN

ECS to EN lG Propagation Delay

85

110

ns

tECSN

ECS to EN lG Propagation Delay

35

55

ns

WAVEFORMS

ns
ns

(See 8214 Waveforms, page 10-131)

CAPACITANCE
Limits
Typ.llJ

Max

Unit

CIN

Input Capacitance

5

10

pF

COUT

Output Capacitance

7

12

pF

Symbol

Min.

Parameter

TEST CONDITIONS: VSIAS = 2.5V, Vcc = 5V, TA ~ 25°C, f = 1 MHz

6-185

8216/8226
4-BIT PARAllEL BI·DIRECTIONAl BUS DRIVER
• Data Bus Buffer Driver for 8080 CPU
• Low Input Load Current - .25 mA
Maximum
• High Output Drive Capability for
Driving System Data Bus

• 3.65V Output High Voltage for Direct
Interface to 8080 CPU
• Three State Outputs
• Reduces System Package Count

The 8216/8226 is a 4-bit bi-directional bus driver/receiver.
All inputs are low power TTL compatible. For driving MaS, the DO outputs provide a high 3.65V VOH, and for high capacitance terminated bus structures, the DB outputs provide a high 50mA IOL capability.

A non-inverting (8216) and an inverting (8226) are available to meet a wide variety of applications for buffering in microcomputer systems.

PIN CONFIGURATION

cs

LOGIC DIAGRAM

LOGIC DIAGRAM

8216

8226

Vee

000

DIEN

DBo

00 3

010

DB,

DO,

01,

DB,

DO,

010

01 0

DBo
00 0

00 0

01,

~DBI

DO,
01,

DB,

GNO

01,

01,

01, ,

-0 DB,

DO,

01,
~----o

DB,
DO,

PIN NAMES

DB,

DO,

01,

013
~---o DB,

DB,
DO,~--t--<

J--t--'

----ocs

' - - - - - t......

00 3

'-----+.......----ocs
OlEN 0 - -......- - - - - '

OlEN 0 - -......- - - - - - '

6-186

8216/8226

FUNCTIONAL DESCRIPTION
Microprocessors like the 8080 are MaS devices and are
generally capable of driving a single TTL load. The same is
true for MaS memory devices. While this type of drive is
sufficient in small systems with few components, quite often
it is necessary to buffer the microprocessor and memories
when adding components or expanding to a multi·board
system.

010

o------Do__--+-,

,-

ODOo---t-~(;.t_-_t_~

I

01,

o---t---I>-~-...,

DB,

DO, o---t--~c: t_-_t_---'

The 8216/8226 is a four bit bi·directional bus driver specif·
ically designed to buffer microcomputer system components.

0', o---t--1~-_t__...,

Bi-Directional Driver

DO, o---t-~(;.t_-_t_~

DB,

Each buffered Iine of the four bit driver consists of two
separate buffers that are tri-state in nature to achieve direct
bus interface and bi-~irectional capability. On one side of
the driver the output of one buffer and the input of another
are tied together (DB), this side is used to interface to the
system side components such as memories, 1/0, etc., because its interface is direct TTL compatible and it has high
drive (50mA). On the other side of the driver the inputs
and outputs are separated to provide maximum flexibility.
Of course, they can be tied together so that the driver can
be used to buffer a true bi-directional bus such as the 8080
Data Bus. The DO outputs on this side of the driver have a
special high voltage output drive capability (3.65V) so that
direct interface to the 8080 and 8008 CPUs is achieved with
an adequate amount of noise immunity (350mV worst case).

0'3 o---t----I

DB3
00 3 o---t--~(;. t_-_t_~

OlEN

(a) 8216

01 0 0

080
00 0
01,

Control Gating OlEN, CS
The CS input is actually a device select. When it is "high"
the output drivers are all forced to their high·impedance
state. When it is at "zero" the device is selected (enabled)
and the direction of the data flow is determined by the
OlEN input.

00,0----

01 2

08,
D02~

The OlEN input controls the direction of data flow (see
Figure 1) for complete truth table. This direction control
is accomplished by forcing one of the pair of buffers into its
high impedance state and allowing the other to transmit its
data. A simple two gate circuit is used for this function.
The 8216/8226 is a device that will reduce component count
in microcomputer systems and at the same time enhance
noise immunity to assure reliable, high performance operation.

>--+---,

01 3
DB3
00 3

oo,,~l
(b) 8226
OlEN

CS

0

0
0

1

1,0

1

'"'

01 ' DB

DB> DO
}HIGH IMPEDANCE

Figure 1. 8216/8226 Logic Diagrams

6-187

o

cs

8216/8226
APPLICATIONS OF 8216/8226
8080 Data Bus Buffer
The 8080 CPU Data Bus is capable of driving a single TTL
load and is more than adequate for small, single board systems. When expanding such a system to more than one board
to increase I/O or Memory size, it is necessary to provide a
buffer. The 8216/8226 is a device that is exactly litted to
this application.

The 8216/8226 can be used in a wide variety of other buffering functions in microcomputer systems such as Address
Bus Drivers, Drivers to peripheral devices such as printers,
and as Drivers for long length cables to other peripherals or
systems.

Shown in Figure 2 are a pair of 8216/8226' connected directly to the 8080 Data Bus and associated control signals_
The buffer is bi-directional in nature and serves to isolate the
CPU data bus.

r-__________B,USEN~
15

•

On the system side, the DB lines interface with standard
semiconductor I/O and Memory components and are completely TTL compatible. The DB lines also provide a high
drive capability (50mA) so that an extremely large system
can be dirven along with possible bus termination networks.

Do

ot OlEN
DB

DO

DBo

DB,

0,
8216
8226
0,

10

11
12

03

On the 8080 side the 01 and DO lines are tied together and
are directly connected to the 8080 Data Bus for hi-directional
operation. The DO outputs of the 8216/8226 have a high
voltage output capability of 3.65 volts which allows direct
connection to the 8080 whose minimum input voltage is
3.3 volts_ It also gives a very adequate noise margin of
350mV (worst case).

DB,

13

1.

DB3

CS
SYSTEM
DATA
BUS

80BO
15

4

04

01 OIE.N

DB

DO

DB4

DBs

05

8216
8226

The iSTEN inputs to 8216/8226 is connected directly to the
8080. OlEN is tied to DBIN so that proper bus flow is
maintained, and CS is tied to BUSEN sO that the system
side Data Bus will be 3-stated when a Hold request has been
acknowledged during a DMA activity.

06

11

10

:

- 0 86

12

D,

13

"

DB,

CS

Memory and I/O Interface to a Bi-directional Bus
In large microcomputer systems it is often necessary to provide Memory and I/O with their own buffers and at the same
time maintain a direct, common interface to a bi-directional
Data Bus. The 8216/8226 has separated data in and data
out lines on one side and a common bi-directional set on the
other to accomodate such a function.

Figure 2. 8080 Data Bus Buffer.

Shown in Figure 3 is an example of how the 8216/8226 is
used in this type of appl ication.

MEMORY

I/O

The interface to Memory is simple and direct. The memories
used are typically Intel@8102,8102A,8101 or 8107B-4 and
have separate data inputs and outputs. The 0 I and DO lines
of the 8216/8226 tie to them directly and under control of
the MEMR signal, which is connected to the OlEN input,
an interface to the bi-directional Data Bus is maintained.
The interface to I/O is similar to Memory. The I/O devices
used are typically Intel@ 8255s, and can be used for both
input and output ports. The I/O R signal is connected directly to the OlEN input so that proper data flow from the
I/O device to the Data Bus is maintained.
Figure 3. Memory and I/O Interface to a Bi-Directional Bus.

6-188

8216/8226
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias . . . . . . . . . . . . . o°c to 70°C
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
All Output and Supply Voltages. . . . . ..

-0.5V to +7V

All I nput Voltages. . . . . . . . . . . . . . . -1.0V to +5.5V
Output Currents .. . . . . . . . . . . . . . . . . . .. 125 mA

TA

=

O°C to +70°C,Vee=+5V±5%

Symbol

Parameter

Min.

Limits
Typ.

Max.

Unit

Conditions

IF1

Input Load Current DI EN, CS

-0.15

-.5

mA

VF = 0.45

IF2

Input Load Current All Other Inputs

-0.08

-.25

mA

VF = 0.45

IR1

Input Leakage Current DIEN, CS

20

Jl.A

V R =5.25V

IR2

Input Leakage Current DI Inputs

10

Jl.A

VR =5.25V

Ve

Input Forward Voltage Clamp

-1

V

le= -5mA

V IL

Input "Low" Voltage

.95

V

V IH
1101

Input "High" Voltage

V

2.0

Output Leakage Current

DO
DB

(3-State)

20
100

Jl.A

Vo = 0.45V /5.25V

8216

95

130

mA

8226

85

120

mA

0.3

.45

V

DO Outputs IOL=15mA
DB Outputs IOL=25mA

0.5

.6

V

DB Outputs 10L =55mA

.6

V

DB Outputs 10L =50mA

4.0

V

DO Outputs 10H - -1mA

3.0

V

DB Outputs 10H = -10mA

lee

Power Supply Current

V OL1

Output "Low" Voltage

VO L2

Output "Low" Voltage

VOH1

Output "High" Voltage

3.65

VOH2

Output "High" Voltage

2.4

los

Output Short Circuit Current

-15
-30

-35
-75

8216

-

0.5

8226

NOTE: Typical values are for TA = 25° e, Vee = 5.0V.

6-189

-65
-120

mA
mA

=-

DO Outputs Vo OV,
DB Outputs Vee=5.0V

8216/8226

WAVEFORMS
INPUTS

OUTPUT

ENABLE

1'I
~tD-

.5V
+

15V"'~-----'"'~ Vat!
OUTPUTS

t

VOL

.5V
A.C. CHARACTERISTICS

Limits
Typ.llJ

Max.

Unit

TpDl

I nput to Output Delay DO Outputs

15

25

ns

CL =30pF, R 1=300n
R 2 =600n

TpD2

Input to Output Delay DB Outputs
8216

Symbol

Parameter

Min.

Conditions

20

30

ns

CL =300pF, R 1=90n

8226

16

25

ns

R2 = 180n

8216

45

65

ns

(Note 2)

8226

35

54

ns

(Note 3)

20

35

ns

(Note 4)

--TE

TD

Output Enable Time

Output Disable Time

TEST CONDITIONS;

TEST LOAD CIRCUIT

Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
Output loading is 5 mA and 10 pF.
Speed measurements are made at 1.5 volt levels.

OUT

o---,.-------t

CAPACITANCE [5J
Symbol

Parameter

Min.

Limits
Typ.llJ

Max.

Unit

CIN

Input Capacitance

4

8

pF

CDUTl

Output Capacitance

6

10

pF

COUT2

Output Capacitance

13

18

pF

TEST CONDITIONS;
NOTES:

VBIAS = 2.5V, VCC = 5.0V, TA = 25°C, f = 1 MHz.

1. Typical values are for TA = 25°C, VCC = 5.0V.
2. DO Outputs, CL = 30pF, Rl = 300/10 Kn, R2 = 180/1 Kn; DB Outputs, CL = 300pF, Rl = 90/10 Kn, R2 = 180/1 Kn.
3. DO Outputs, CL = 30pF, R 1 = 300/10 Kn, R2 = 600/1 K; DB Outputs, CL =300pF, Rl =90/10 Kn, R2 = 180/1 KR
4. DO Outputs, CL = 5pF, Rl = 300/10 Kn, R2 = 600/1 Kn; DB Outputs, CL = 5pF, Rl = 90/10 Kn, R2 = 180/1 Kn.
5. This parameter is periodically sampled and not 100% tested.

6-190

inter
M8216
4-BIT PARALLEL BI-DIRECTIONAL BUS DRIVER

3.40V Output High Voltage for Direct
• Interface
to 8080 CPU
• Three-State Outputs
Full Military Temperature Range -55° C
• To
+125°C

• Data Bus Buffer Driver for 8080 CPU
Input Load Current: .25 mA
• Low
Maximum
Output Drive Capability for Driving
• High
System Data Bus
• 16-Pin Dual In-Line Package

• ±10% Power Supply Tolerance

The M8216 is a 4-bit bi-directional bus driver/receiver.
All inputs are low power TTL compatible. For driving MOS, the DO outputs provide a high 3.40V VOH, and for high capacitance
terminated bus structures, the DB outputs provide a high 50mA IOL capability.
The M8216 is used to meet a wide variety of applications for buffering in microcomputer systems.

LOGIC DIAGRAM
8216

PIN CONFIGURATION

cs

Vee

000

DlEN

DBo

DO,

010

DB,

DO,

01,

DB,

DO,

010 o~-----L:I---_t--,
.......---oDBO

0°00----+--< t-_t--'
01,

o----j---I.>"--t----,
.......- - - 0 DB,

00,0----+--< t-_t--'
01,

DB,

3ND

01,

01, o----t--D~_t-,
.......- - - 0 DB,

00,0----+·--< t-_t--'
PIN NAMES

01,

0----+-; ..;I~-+--,

DO,

o----t--< ........---1--'

.......- - - 0 DB,

DlO·013
00 0 .0°3

-----====-OlEN

DATA INPUT
DATA OUTPUT

[)ATA'IN ENABLE-DIRECTION CONTROL

-~-rcHI~~--

L - - - - t......----ocs
OlEN

6-191

<>----4-------'

•

M8216
D.C. AND OPERATING CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias " " " , ' , , , ,-55°C to +125°C
Storage Temperature " "

, , ' , , , , , ' , -65°C to +150°C

All Output and Supply Voltages, , , , _ ' , , _ -O,5V to +7V
All Input Voltages, _ , ' , , _ , , , , _ , , ' , , -1.0V to +5,5V
Output Currents "

, , ' , ' _, ' , , , , , , ' , _' , "

125 mA

Limits
Typ,

Max,

Unit

IFl

Input Load Current OlEN, CS

-0,15

-,5

mA

V F = 0,45

IF2

Input Load Current All Other Inputs

-0,08

-,25

mA

VF =0,45

IRl

Input Leakage Current OlEN, CS

20

J.1A

VR = 5,5V

IR2

Input Leakage Current 01 Inputs

10

J.1A

VR = 5,5V

-1.2

V

Ie = -5mA

.95

V

Vee = 5V

V

Vee = 5V

Symbol

Parameter

Ve

Input Forward Voltage Clamp

VIL

Input "Low" Voltage

V 1H

Input "High" Voltage

1101

Min,

*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device, This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied, Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability,

Output Leakage Current
(3-State)

2.0
DO
DB

20
100

J.1A

Conditions

Vo

= ,45V to Vee

lee

Power Supply Current

95

130

mA

VaLl

Output "Low" Voltage

0.3

,45

V

DO Outputs IOL=15mA
DB Outputs 10L =25mA

VOL2

Output "Low" Voltage

0.5

.6

V

DB Outputs 10L =50mA

VO Hl

Output "H igh" Voltage

3,4

3.8

V

DO Outputs 10H = -.5mA

VO H2

Output "High" Voltage

2,4

3.0

V

DO Outputs 10H = -2mA
DB Outputs 10H = -5,OmA

los

Output Short Circuit Current

-15
-30

-35
-75

NOTE: Typical values are for TA

~

25° e, Vee ~ 5.0V.

6-192

-65
-120

mA
mA

DO Outputs Vee = 5.0V
DB Outputs Vee = 5,OV

M8216
WAVEFORMS

-J'i. .

INPUTS _ _ _ _ _ _ _

'_SV_ _ _ _ _ _ _ _ _ _ _ _ _ __

l~trD-

OUTPUT

1.5V

ENABLE

1.5V

~-tE--

r

~tD--1

"',.------""~~

QUTPUTS-----------,-.S'""V

aH
V

-1

VOL

.SV

A.C. CHARACTERISTICS
TA ~ -55°C to +125°C, VCC ~+5V ±10%

Symbol

Parameter

-~--.-

Limits---,
Typ.l11 I Max.
,--15
25

Min.

-~~------.-.

Tp01

Input to Output Delay DO Outputs

I

-------~~-,--.,------------

I Input to Output Delay DB Outputs I
~- ~"-r Output Enable Time ---~--.
Tp02

r

To

~O

1----] 45

OutPu~-Dlsable

-r;;;;-;------ 1------1

TEST CONDITIONS:

20'-

Unit

I

Conditions

tn~
-

33
75

(NOTE 2)

.

~--~--~~~-

ns

(NOTE 2)

ns

(NOTE 2)

ns

(NOTE 2)

_._-_._---_._---

40

TEST LOAD CIRCUIT

Input pulse amplitude of 2.5V.
Input rise and fall times of 5 ns between 1 and 2 volts.
OUTO----~~--~

CAPACITANCE
_Symbol
C'N

__

_L_~ ~~.F'aramete!

_____

~~______

I Input Capacitance
-....:.:..:'--------t---------------.------......--.---COUTl
! Output Capacitance
DO Outputs

~ill:.._T~;;~~l

___

--------- - - -

4

6

I
I
I

Unit
pF

6
10
pF
r---=O-u-tP-u-t-CC'a-p-a-c-it-an--c-e------·-D-B--O-u-tP-u-t-s------ - - ...- . - --- - - - -----1-3----I---1-S---+I-p'--F---

COUT2

VBIAS ~ 2.5V, Vee = 5.0V, TA = 25°C, f = 1 MHz.

TEST CONDITIONS:
NOTES:

m

1. Typical values are for TA
2.

_.

TEST

25"e, Vee

I 30pF I 300n
300pF I 90n

T pD1

T PD2
T E, (DO, ENABLE!)

I' OKS)

=

5.0V.

R2

600n

18OS2

TE, (DB, ENABLE1)

30pF
30pF
300pF

T E, (DB, ENABLEtI

300pF

'OKE
90n

'KIl
'80Sl

To, (DO, OISABLEti

5pF

300n

To, (DO, OISABLEtI

600[2
, KSl

To, (DB, DISABLE!)

5pF i,oKn
5pF
9011

To, (DB, OISABLOI

5pF ilOKn

T E,

I

~

C~Rl

(~O,

ENABLEO

300n

'KE
60011

'80S2
'Kn

6·193

inter
8251A
PROGRAMMABLE COMMUNICATION INTERFACE
• Synchronous and Asynchronous
Operation

• Baud Rate - DC to

• Synchronous:
5·8 Bit Characters
Internal or External Character
Synchronization
Automatic Sync Insertion

• Error Detection
and Framing
• Fully

CPU

L . . . .TI.J, . .

• Asynchronous:
5·8 Bit Characters
Clock Rate -1,16 or 64 Times
Baud Rate
Break Character Generation
1,1%, or 2 Stop Bits
False Start Bit Detection
Automatic Break Detect
and Handling
The 8251A is the enhanced version of the industry
mitter (USART), designed for data communications with
8085. The 8251A is used as a peripheral device and is
sion technique presently in use (including IBM BI
then converts them into a continuous serial
convert them into parallel data characters for
for transmission or whenever it has received a
time. These include data transmission errors
N-channel silicon gate technology.

I Synchronous/Asynchronous ReceiverlTransfamily of microprocessors such as the
U to operate using virtually any serial data transmisdata characters from the CPU in parallel format and
Simultaneously, it can receive serial data streams and
signal the CPU whenever it can accept a new character
CPU can read the complete status of the USART at any
as SYNDET, TxEMPTY. The chip is constructed using

PIN CONFIGURATION

BLOCK DIAGRAM

hD

TxRDV
TxEMPTY

TxC

Pin Function

RxD

Data Set Ready

Data Terminal Ready
Sync Detectl

Write Data or Control Command

Break Detect
Request to Send Data

Chip Select
Clock Pulse (TTL)

Clear to Send Data

Reset

fXC

T ransminer Clock

TxEMPTY

Transmitter Empty

TltO

Transmitter Data

Axe

Vee

+5 Volt Supply

GND

Ground

RxADY

Receiver Clock
Receiver Data
R8C8Wer Readv (has charactet for CPU)

TItRDY

Transmitter

AxD

INTERNAL
DATA BUS

_SYNDETI

BRKDET

(ready for char. from CPU)

6-194

8251A
8251A BASIC FUNCTIONAL DESCRIPTION
General
The 8251 A is a Universal Synchronous/Asynchronous ReceiverfTransmitter designed specifically for the 80/85 Microcomputer Systems. Like other 1/0 devices in a Microcomputer System, its functional configuration is programmed
by the system's software for maximum flexibility. The
8251 A can support virtually any serial data technique currently in use (including IBM "bi-sync").
In a communication environment an interface device must
convert parallel format system data into serial format for
transmission and convert incoming serial format data into
parallel system data for reception. The interface device must
also delete or insert bits or characters that are functionally
unique to the communication technique. In essence, the
interface should appear "transparent" to the CPU, a simple
input or output of byte-oriented system data.

i.

C/O (Control/Data)

This input, in conjunction with the WR a~'if'"~"iil),
informs the 8251A that the word on the Data BtA:ls,~i:th!l[
a data character, control word or status information. ',i (':::", ..:'0"
1 = CONTROL/STATUS 0 = DATA
"//.

CS (Chip Select)
A "low" on this input selects the 8251A. No reading or
writing will occur unless the device is selected. When CS is
high, the Data Bus in the float state and RD and WR will
have no effect on the ch ip.

Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to interface
the 8251 A to the system Data Bus. Data is transmitted or
received by the buffer upon execution of INput or OUTput
instructions of the CPU. Control words, Command words
and Status information are also transferred through the
Data Bus Buffer. The command status and data in, and
data out are separate 8-bit registers to provide double
buffering.
This functional block accepts inputs from the system Control bus and generates control signals for overall device
operation. It contains the Control Word Register and Command Word Register that store the various control formats
for the device functional definition.

RESET (Reset)
A "high" on this input forces the 8251 A into an "Idle"
mode. The device will remain at "Idle" until a new set of
control words is written into the 8251A to program its
functional definition. Minimum RESET pulse width is
6 tCY (clock must be running).

ClK (Clock)
The ClK input is used to generate internal device timing
and is normally connected to the Phase 2 (TTL) output of
the 8224 Clock Generator. No external inputs or outputs
are referenced to ClK but the frequency of CLK must be
greater than 30 times the Receiver or Transmitter data
bit rates.

C/D

RD

0
0

0

WR

CS

1
0
1
0
1
X

0
0
0
0
0

0
X
X

1
X

8251A DATA = DATA BUS
DATA BUS = 8251A DATA
STATUS = DATA BUS
DATA BUS = CONTROL
DATA BUS= 3-STATE
DATA BUS = 3-STATE

WR (Write)
A "low" on this input informs the 8251A that the CPU is
writing data or control words to the 8251A.

RD (Read)
A "low" on this input informs the 8251A that the CPU is
reading data or status information from the 8251A.

Modem Control
The 8251A has a set of control inputs and outputs that can
be used to simplify the interface to almost any Modem. The
Modem control signals are general purpose in nature and
can be used for functions other than Modem control, if
necessary.

6-195

8251A
DSR (Data Set Ready)
The DSR input signal is a general purpose, l-bit inverting
input port. Its condition can be tested by the CPU using a
Status Read operation. The DSR input is normally used to
test Modem conditions such as Data Set Ready.

DTR (Data Terminal Ready)
The DTR output signal is a general purpose, l-bit inverting
output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The DTR
output signal is normally used for Modem control such as
Data Terminal Ready or Rate Select.

TxE (Transmitter Empty)
When the 8251 A has no characters to transmi~:'th~''f)(E
TY output will go "high". It resets automatically l.iPO~"te.:
ceiving a character from the CPU. TxEMPTY can be used to,.\.,
indicate the end of a transmission mode, so that the CPU
"knows" when to "turn the line around" in the halfduplexed operational mode. TxEMPTY is independent of
the Tx Enable bit in the Command instruction.
In SYNChronous mode, a "high" on this output indicates
that a character has not been loaded and the SYNC character or characters are about to be or are being transmitted
automatically as "fillers". TxEMPTY does not go low
when the SYNC characters are being shifted out.

RTS (Request to Send)
The RTS output signal is a general purpose, l-bit inverting
output port. It can be set "low" by programming the appropriate bit in the Command Instruction word. The RTS
output signal is normally used for Modem control such as
Request to Send.

CTS (Clear to Send)
A "low" on this input enables the 8251A to transmit
serial data if the Tx Enable bit in the Command byte is
set to a "one." If either a Tx Enable off or CTS off condition occurs while the Tx is in operation, the Tx will
transmit all the data in the USART, written prior to Tx
Disable command before shutting down.

Transmitter Buffer
The Transmitter Buffer accepts parallel data from the Data
Bus Buffer, converts it to a serial bit stream, inserts the
appropriate characters or bits (based on the communication technique) and outputs a composite serial stream of
data on the TxD output pin on the fall ing edge of TxC.
The transmitter will begin transmission upon being enabled
if CTS = O. The TxD line will be held in the marking
state immediately upon a master Reset or when Tx Enable/
CTS off or TxEMPTY.

Transmitter Control
The transmitter Control manages all activities associated
with the transmission of serial data. It accepts and issues
signals both externally and internally to accomplish this
function.

TxRDY (Transmitter Ready)
This output signals the CPU that the transmitter is ready to
accept a data character. The TxRDY output pin can be
used as an interrupt to the system, since it is masked by
Tx Disabled, or, for Polled operation, the CPU can check
TxRDY using a Status Read operation. TxRDY is automatically reset by the leading edge of WR when a data
character is loaded from the CPU.

TxC (Transmitter Clock)
The Transmitter Clock controls the rate at which the character is to be transmitted. In the Synchronous transmis.ion
mode, the Baud Rate (lx) is equal to the TxC frequency.
In Asynchronous transmission mode the baud rate is a
fraction of the actual TxC frequency. A portion of the
mode instruction selects th is factor; it can be 1, 1/16 or
1/64 the TxC.

For Example:
If Baud Rate equals 110 Baud,
TxC equals 110 Hz (lx)
TxC equals 1.76 kHz (16x)
TxC equals 7.04 kHz (64x) ..

Note that when using the Polled operation, the TxRDY
status bit is not masked by Tx Enabled, but will only
indicate the Empty/Full Status of the Tx Data Input
Register.

The falling edge of TxC shifts the serial data out of the
8251A.

6-196

8251A
('''''''','',I!

Receiver Buffer

quency. A portion of the mode instruction selects this
factor; 1, 1/16 or 1/64 the RxC.

The Receiver accepts serial data, converts this serial input
to parallel format, checks for bits or characters that are
unique to the communication technique and sends an
"assembled" character to the CPU. Serial data is input to
RxD pin, and is clocked in on the rising edge of RxC.

For Example:
Baud Rate equals 300 Baud, if
RxC equals 300 Hz (lx)
RxC equals 4800 Hz (16x)
RxC equals 19.2 kHz (64x).

Receiver Control

Baud Rate equals 2400 Baud, if
RxC equals 2400 Hz (lx)
RxC equals 38.4 kHz (16x)
RxC equals 153.6 kHz (64x).

This functional block manages all receiver·related activities
which consist of the following features:
The RxD initialization circuit prevents the 8251A from
mistaking an unused input line for an active low data
line in the "break condition". Before starting to receive
serial characters on the RxD line, a valid "1" must first
be detected after a chip master Reset. Once this has been
determined, a search for a valid low (Start bit) is en·
abled. This feature is only active in the asynchronous
mode, and is only done once for each master Reset.
The False Start bit detection circuit prevents false starts
due to a transient noise spike by first detecting the fall·
ing edge and then strobing the rominal center of the
Start bit (RxD ; low).
The Parity Toggle F/F and Parity Error F/F circuits are
used for parity error detection and set the corresponding
status bit.
The Framing Error Flag F/F is set if the Stop bit is
absent at the end of the data byte (asynchronous mode),
and also sets the corresponding status bit.

RxRDY (Receiver Ready)
This output indicates that the 8251A contains a character
that is ready to be input to the CPU. Rx RDY can be con·
nected to the interrupt structure of the CPU or, for Polled
operation, the CPU can check the condition of RxRDY
using a Status Read operation.

Data is sampled into the 8251 A on the rising edge of RxC.
NOTE: In most communications systems, the 8251A will
be handling both the transmission and reception operations
of a single link. Consequently, the Receive and Transmit
Baud Rates will be the same. 80th TxC and RxC will reo
quire identical frequencies for this operation and can be
tied together and connected to a single frequency source
(Baud Rate Generator) to simplify the interface.

SYNDET (SYNC Detect)/BRKDET (Break Detect)
This pin is used in SYNChronous Mode for SYNDET and
may be used as either input or output, programmable
through the Control Word. It is reset to output mode low
upon RESET. When used as an output (internal Sync mode),
the SYNDET pin will go "high" to indicate that the 8251 A
has located the SYNC character in the Receive mode. If the
8251 A is programmed to use double Sync characters (bi·
sync), then SYNDET will go "high" in the middle of the
last bit of the second Sync character. SYNDET is auto·
matically reset upon a Status Read operation.

Rx Enable off both masks and holds RxRDY in the Reset
Condition. For Asynchronous mode, to set RxRDY, the
Receiver must be Enabled to sense a Start Bit and a com·
plete character must be assembled and transferred to the
Data Output Register. For Synchronous mode, to set
RxRDY, the Receiver must be enabled and a character
must finish assembly and be transferred to the Data Output
Register.
Failure to read the received character from the Rx Data
Output Register prior to the assembly of the next Rx Data
character will set overrun condition error and the previous
character will be written over and lost. If the Rx Data is
being read by the CPU when the internal transfer is occurring, overrun error will be set and the old character will be
lost.

RxC (Receiver Clock)
The Receiver Clock controls the rate at which the character
is to be received. In Synchronous Mode, the Baud Rate (lx)
is equal to the actual frequency of RxC. In Asynchronous
Mode, the Baud Rate is a fraction of the actual RxC fre-

6-197

8251A
When used as an input (external SYNC detect mode), a
positive going signal will cause the 8251A to start assembling data characters on the rising edge of the next RxC.
Once in SYNC, the "high" input signal can be removed.
the period of RxC. When External SYNC Detect is programmed, the Internal SYNC Detect is disabled.

Break Detect (Async Mode Only)
This output will go high whenever an all zero word of the
programmed length (including start bit, data bit, parity bit,
and one stop bit) is received. Break Detect may also be read
as a Status bit. It is reset only upon a master chip Reset or
Rx Data returning to a "one" state.

The 8251A cannot begin transmission uittitthe
(Transmitter Enable) bit is set in the Command IQI(tr\lc~IOrliN'1i
and it has received a Clear To Send (CTS) input.
output will be held in the marking state upon Reset.

Programming the 8251A
Prior to starting data transmission or reception, the 8251A
must be loaded with a set of control words generated by
the CPU. These control signals define the complete functional definition of the 8251A and must immediately folIowa Reset operation (internal or external).
The control words are split into two formats:
1. Mode Instruction
2. Command Instruction

Mode Instruction
ADDRESS BUS

\

CONTROL BUS

I/O R

1(0 W

9,

RESET

(TTL)

\

j

DATA BUS

This format defines the general operational characteristics
of the 8251A. It must follow a Reset operation (internal or
external). Once the Mode Instruction has been written into
the 8251A by the CPU, SYNC characters or Command Instructions may be inserted.

Command Instruction
This format defines a status word that is used to control the
actual operation of the 8251 A.

J"

CID

CS

"'"

°7-DO

RD

WR

RESET

elK

8251A

8251 A Interface to 8080 Standard System Bus

DETAILED OPERATION DESCRIPTION
General
The complete functional definition of the 8251A is programmed by the system's software. A set of control words
must be sent out by the CPU to initialize the 8251A to
support the ·desired communications format. These control
words will program the: BAUD RATE, CHARACTER
LENGTH, NUMBER OF STOP BITS, SYNCHRONOUS or
ASYNCHRONOUS OPERATION, EVEN/ODD/OFF PARITY, etc. In the Synchronous Mode, options are also provided to select either internal or external character synchronization.
Once programmed, the 8251 A is ready to perform its communication functions. The TxRDY output is raised "high"
to signal the CPU that the 8251A is ready to receive a data
character from the CPU. This output (TxRDY) is reset
automatically when the CPU writes a character into the
8251A. On the other hand, the 8251A receives serial data
from the MODEM or I/O device. Upon receiving an entire
character, the RxRDY output is raised "high" to signal the
CPU that the 8251A has a complete character ready for the
CPU to fetch. RxRDY is reset automatically upon the CPU
data read operation.

Both the Mode and Command Instructions must conform
to a specified sequence for proper device operation. The
Mode Instruction must be inserted immediately following a
Reset operation, prior to using the 8251A for data communication.
All control words written into the 8251A after the Mode Instruction will load the Command Instruction. Command
Instructions can be written into the 8251A at any time in
the data block during the operation of the 8251A. To return to the Mode Instruction format, the master Reset bit
in the Command Instruction word can be set to initiate an
internal Reset operation which automatically places the
8251 A back into the Mode Instruction format. Command
Instructions must follow the Mode Instructions or Sync
characters.

c/o

= 1

MODE INSTRUCTION

C/O'" 1

SYNC CHARACTER 1
~--~~---

C/D

= ,

SYNC CHARACTER 2

C/D'" 1

COMMAND INSTRUCTION

C/D=O

DATA

C/O=O

DATA

SYNC MODE
ONLY *

~o' r.~O;~H"cr~
c/o

= ,

COMMAND 1f\ISTRUCTION

* The second SYNC character is skipped if MODE instruction
has programmed the 8251A to single character Internal SYNC
Mode. Both SYNC characters are skipped if MODE instruction
has programmed the 8251A to ASYNC mode.

Typical Data Block

6-198

8251A
Mode Instruction Definition
The 8251 A can be used for either Asynchronous or Synchronous data communication. To understand how the
Mode Instruction. defines the functional operation of the
8251 A, the designer can best view the device as two separate components sharing the same package, one Asynchronous the other Synchronous. The format definition can be
changed only after a master chip Reset. For explanation
purposes the two formats will be isolated.

I

s,

1

s,

1 EP 1PEN 1 L, 1 L, 1 B,I B I

~

NOTE: When parity is enabled it is not considered as one of
the data bits for the purpose of programming the word
length. The actual parity bit received on the Rx Data line
cannot be read on the Data Bus. In the case of a programmed character length of less than 8 bits, the least
significant Data Bus bits will hold the data; unused bits are
"don't care" when writing data to the 8251A, and will be
"zeros" when reading the data from the 8251A.

BAUD RATE FACTOR

0

1

0

0

0

1

1
1

SYNC
MODE

(1X)

(16X)

164X)

CHARACTER LENGTH

I I
I

0

1

0

0

0

1

1

5
BITS

6
BITS

7
BITS

8
BITS

PARITY ENABLE
, = ENABLE
0 DISABLE
0

L -_ _ _ _ _ _ _ _ ~~~~~~RIT6 ~~~~AATION/CHECK

L:=

NUMBER OF STOP BITS

0

1

a

0

0

1

1

INVALID

1
BIT

1%
BITS

2
BITS

Asynchronous Mode (Transmission)
Whenever a data character is sent by the CPU the 8251 A
automatically adds a Start bit (low level) followed by the
data bits (least significant bit first). and the programmed
number of Stop bits to each character. Also, an even or
odd Parity bit is inserted prior to the Stop bit(s), as de·
fined by the Mode Instruction. The character is then transmitted as a serial data stream on the TxD output. The serial
data is shifted out on the falling edge of TxC at a rate equal
to 1,1/16, or 1/64 that of the TxC, as defined by the Mode
Instruction. BREAK characters can be continuously sent to
the TxD if commanded to do so.

(ONLY EFFECTS Tx; Rx NEVER
REQUIRES MORE THAN ONE

Asynchronous Mode

srJ;i

arrs L

DOES NOT APPEAR

RxO

6-199

GENERATED
BY 8251A

DO 01---- Ox

DO D1 ----Ox ON THE DATA BUS

RECEIVER INPUT

The RxD line is normally high. A falling edge on this line
triggers the beginning of a START bit. The validity of this
START bit is checked by again strobing this bit at its nominal center (16X or 64X mode only). If a low is detected
again, it is a valid START bit, and the bit counter will
start counting. The bit counter thus locates the center of
the data bits, the parity bit (if it exists) and the stop bits.
If parity error occurs, the parity error flag is set. Data and
parity bits are sampled on the RxD pin with the rising edge
of RxC. If a low level is detected as the STOP bit, the
Framing Error flag will be set. The STOP bit signals the end
of a character. Note that the receiver requires only one stop
bit, regardless of the number of stop bits programmed. This
character is then loaded into the parallel 1/0 buffer of the
8251 A. The RxRDY pin is raised to signal the CPU that a
character is ready to be fetched. If a previous character has
not been fetched by the CPU, the present character replaces
it in the 1/0 buffer, and the OVERRUN Error flag is raised
(thus the previous character is lost). All of the error flags
can be reset by an Error Reset Instruction. The occurrence
of any of these errors will not affect the operation of the
8251A.

1

STOP BIT)

When no data characters have been loaded into the 8251A
the TxD output remains "high" (marking) unless a Break
(continuously low) has been programmed.

Asynchronous Mode (Receive)

1

tt t
IL._S_TB;...~_~T_L.G

t

-------

__
OA_T-;A Bj-'T_S_-'-_ _......

ST6;"l
BrrS

PROGRAMMED

CHARACTER
LENGTH

TRANSMISSION FORMAT

CPU BYTE (5-8 BITS/CHAR)
DATA C:ARACTER

L..----lI~;- - - - '
ASSEMBLED SERIAL DATA OUTPUT (TxD)
SToh

L-~,--,--__D_A_TA_C~H~A_RA_C_T_ER__~'--~__L-~BIT~
RECEIVE FORMAT

SERIAL DATA INPUT (RxO)
DATA CHARACTER

STOD
BITS

1----'----'---1

.-----...;' ....
, ---,
CPU BYTE (5-8 BITS/CHAR)·
DATA CHARACTER

'--------41 1-1- - - - '
-NOTE: IF CHARACTER LENGTH IS DEFINED AS 5, 6 OR 7
BITS THE UNUSED BITS ARE SET TO "ZERO".

L

8251A
i.'

The TxD output is continuously high until the CPU sends
its first character to the 8251A which usually is a SYNC
character. When the CTS line goes low, the first character
is serially transmitted out. All characters are shifted out on
the falling edge of TxC. Data is shifted out at the same
rate as the TxC.
Once transmission has started, the data stream at the TxD
output must continue at the TxC rate. If the CPU does not
provide the 8251A with a data character before the 8251A
Transmitter Buffers become empty, the SYNC characters
(or character if in single SYNC character mode) will be
automatically inserted in the TxD data stream. In this case,
the TxEMPTY pin is raised high to signal that the 8251 A is
empty and SYNC characters are being sent out. TxEMPTY
does not go low when the SYNC is being shifted out (see
figure below). The TxEMPTY pin is internally reset by a
data character being written into the 8251A.

Mode Instruction Format

Iscs I I I I L21 L, I I
ESD

TxD

TxEMPTV

I

DATA

I I
DATA

------("
./

SYNC 1

I

SYNC

21

DATA

.:...if':,

the SYNDET F/F is reset at each Status R~a~f/eg~~..
.:~'.:;::\§"
whether internal or external SYNC has been pro\l[~mrp~d'\··'~,'~jft! III
This does not cause the 8251A to return to theHlJ~t :\. ' .~: I~
mode. When in SYNC mode, but not in HUNT, Sync Detedtion is still functional, but only occurs at the "known"
word boundaries. Thus, if one Status Read indicates SYNDET and a second Status Read also indicates SYNDET,
then the programmed SYNDET characters have been received since the previous Status Read. (If double character
sync has been programmed, then both sync characters have
been contiguously received to gate a SYNDET indication.)
When external SYNDET mode is selected, internal Sync
Detect is disabled, and the SYNDET F /F may be set at
any bit boundary.

Synchronous Mode (Transmission)

EP

PEN

I-- - --

0

I

0

J

L~

" ' \ \ \ \ \ \ \ FALLS UPON CPU WRITING A
'-_ _ _ _ _ _ /CHARACTER TaTHE USART

CHARACTER LENGTH
0

1

0

0

0

1

1

5

6
BITS

7
BITS

B
BITS

BITS

1

NOMINAL CENTER OF LAST BIT

PARITY ENABLE
{1 = ENABLE!
(0 = DISABLE)

Synchronous Mode (Receive)
In this mode, character synchronization can be internally
or externally achieved. If the SYNC mode has been programmed, ENTER HUNT command should be included in
the first command instruction word written. Data on the
RxD pin is then sampled in on the riSing edge of RxC. The
content of the Rx buffer is compared at every bit boundary
with the first SYNC character until a match occurs. If the
8251 A has been programmed for two SYNC characters, the
subsequent received character is also compared; when both
SYNC characters have been detected, the USART ends the
HUNT mode and is in character synchronization. The
SYNDET pin is then set high, and is reset automatically by
a STATUS READ. If parity is programmed, SYNDET
will not be set until the middle of the parity bit instead of
the middle of the last data bit.

EVEN PARITY GENERATION/CHEe
1 -= EVEN
0= ODD

EXTERNAL SYNC DETECT
, = SYNDET IS AN INPUT
0= SYf\JDET IS AN OUTPUT

SINGLE CHARACTER SYNC
1 = SINGLE SYNC CHARACTER
0= DOUBLE SYNC CHARACTER
NOTE: IN EXTERNAL SYNC MODE, PROGRAMMING DOUBLE CHARACTER
SYNC WILL AFFECT ONLY THE Tx.

Data Format, Synchronous Mode
CPU BYTES (5-8 BITS/CHAR)

. - - - - - ; 1 ...
, ----,

In the external SYNC mode, synchronization is achieved by
applying a high level 011 the SYNDET pin, thus forcing the
8251A out of the HUNT mode. The high level can be
removed after one RxC cycle. An ENTER HUNT command
has no effect in the asynchronous mode of operation.

DATA CHARACTERS

~-----~'''''------~
ASSEMBLED SERIAL DATA OUTPUT (TxD)

r--'S"'Y"'NC::-"'-~S"'YN"'C::--,------_T_ER_S

CPU BYTES (5·8 BITS/CHAR)

6-200

____-,

8251A
COMMAND INSTRUCTION DEFINITION

STATUS READ DEFINITION

Once the fUllctional definition of the 8251A has been programmed by the Mode Instruction and the Sync Characters
are loaded (if in Sync Mode) then the device is ready to be
used for data communication_ The Command Instruction
controls the actual operation of the selected format. Functions such as: Enable Transmit/Receive, Error Reset and
Modem Controls are provided by the Command Instruction.

In data commuflication systems it is
nec;r~itar:;',"f~'tl'
examine the "status" of the active device to ascertai~" if-'ll,:,:,':
errors have occurred or other conditions that require the
processor's attention. The 8251A has facilities that allow
the programmer to "read" the status of the device at any
time during the functional operation. (The status update is
inhibited during status read).

Once the Mode Instruction has been written into the 8251 A
and Sync characters inserted, if necessary, then all further
"control writes" (C/O = 1) will load a Command Instruction. A Reset Operation (internal or external) will return
the 8251 A to the Mode Instruction format.

A normal "read" command is issued by the CPU with
to accomplish this function.

cio = 1

Some of the bits in the Status Read Furmat have identical
meanings to external output pins so that the 8251A can be
used in a completely Polled environment or in an interrupt
driven environment. TxRDY is an exception.
Note that status update can have a maximum delay of 28
clock periods from the actual event affecting the status.

7

r

TRANSMIT ENABLE
1 '" enable
0'" disable

DSR

o6

o5

o4

o3

SVNDET

FE

DE

PE

I I I I I

o2

,

oa

TXEMPTVI RxRDV I TxRDV

I

I

o

I

~

SAME DEFINITIONS AS I/O PINS
DATA TERMINAL

READY
"high" will force OTR

PARITV ERROR

output to zero

The PE flag is set when a parity
error is·detected. It is reset by
the E R bit of the Command
Instruction. PE does not inhibit
operation of the 8251 A.

RECEIVE ENABLE
'----~.j 1 = enable
0'" disable

SEND BREAK

~-----~-l ~~~:~;$T;:D
o = normal

"low"

operation

'-------

ERROR RESET

~--------.J 1'" reset error flags
PE. DE, FE

'---------------1

FRAMING ERROR (Async only)
The FE flag is set when a valid
Stop bit is not detected at the
end of every character. It is reset
by the ER bit of the Command
Instruction. FE does not inhibit
the operation of the 8251A.

REQUEST TO SEND
"high" will force RTS

output to zero

'-_____________-1

OVERRUN ERROR
The OE flag is set when the CPU
does not read a character bafore
the next one becomes available.
It is reset by the ER bit of the
Command Instruction. DE does
not inhibit operation of the 8251 A
however, the previously overrun
character is lost.

!·~~~~~e~uLr~~~;1A to
Mode Instruction Format

., DATASET READY: Indicates
that the OSR is at a zero level.

ENTER HUNT MODE1 = enable search for Sync

Characters

Status Read Format

* (HAS NO EFFECT
IN ASYNC MODE)

Note1:
Note: Error Reset must be performed whenever RxEnable and
Enter Hunt are programmed.

Command Instruction Format

6·201

TxRDY status bit has different meanings from the
TxRDY output pin'. The former is not conditioned
by CTS and TxEN; the latter is conditioned by both
ffi and TxEN.
i.e. TxR DY status bit = DB Buffer Empty
TxRDY pin out = DB Buffer Empty' (CTS=O)' (TxEN=1)

8251A
APPLICATIONS OF THE 8251A

ADDRESS BUS

CONTROL BUS

DATA BUS

PHONE

LINE
INTERFACE

R'ol-----I
8251A

T'OI----

I

Axe

T.in
EXAMPLE FORMAT'" 7 BIT CHARACTER WITH PARITY & 2 STOP BITS.

6-207

"

"
Q

8251A
RECEIVER CONTROL & FLAG TIMING (ASYNC MODE)

r-(STATUS BITI

c/5

~

'""i5Ai'A

OVERRUN ERROR

CHAR 2
LOST

!l-::-tRXRDY

r-

f--------

RdOATA

=r-

""

Wr ERR

WrRxEn 1

U

EXAMPLE FORMAT

U

j

WrRX~

r-v-

,J

I,J

-----------uro:JJJJ

WrRxEn

WJJJJJJJ

WJJJ\J..JJJ

0--

-

7 BIT CHARACTER WITH PARITY 80 2 STOP BITS

TRANSMITTER CONTROL & FLAG TIMING (SYNC MODE)

(STATUS BITI

Tx READY
(PIN!

if

LIt!

Tx READY

MARKING STATE

W,OATA

~
J.

0'

2

EXAMPLE FORMAT

SBRKI
WrDATA

CHAR 3

CHAR 4

SN~\
CHAR t

0'"

J'

M'

W,COMMAND

Wr DATA

DATA
CHAR2

CHAR 1

0"

fL

'----<
Ir-

r

{\
WrDATA

1'------<
r-

1

- J y - - ~~'---.

c/o

'~

• "

J'

M.

M'

CH~~~~

SYNC CHAR 2

•

M.

IiWrDATA

W'COMMAJ!
SBRK t

." J.

MA~~

C~~TRA~
0'

STATE

STAH

DATA
CHAR 5

STATE

'---J!

23'
M.

M'

CHAR 5

0',

J'

5 BIT CHARACTER WITH PARITy' 2 SYNC CHARACTERS

SYNC
CHAR

".

0"

no

0"

J.

e..

RECEIVER CONTROL & FLAG TIMING (SYNC MODE)

SYNDET
(PIN) NOTE ,,1

.L.!:!0TE'!......J
liS ...........

SYNDer (5,6)

~

'L--

OVERRUN
ERROR (S,BI

1'--

r---

~

""~
.lo N;:+

~1TUS

Rx ROY (PIN)

CID

-

'ES-

~

--1~rEH

Rd DATA
CHAR 1

RxEn T

-V

CHAR 3

,. ,

" " x " ,

SYNC

SYNC

CHAR 1

CHAR 2

2

~

4

~

0

,

~

3

4

DATA
CHAR 1
<{ Q

,

~

3

CHAR 2

4

• " 'c'A' ••

1 1 1 1 1 I I 1 1 , 1 r 1 ~-!.lH~lAss~IELJsT

DATA
CHAR 3

0'

23'

TTTTT

J1JU1.Ilf
L

CHAR 1

..

0

-Ad STATUS

Rd;rT::~S

.~

L

Rd DATA

CHAR 1

>---

DON'T
CARE

-

Ir

SYNCCHAR2

1 2 3 4 <{O,

2

34

IV

r--

'o£A

DATA \...
CHAR 2

CHAR 1

DON'T CARE

. " <'X'"

X

0123'

/

ruI



TEST POINTS

0.45 _ _ _oJ

6-221

<:.:X___

'----

8253, 8253-5
A.C. CHARACTERISTICS (Cont'd): TA = O°Cto 70°C; VCC= 5.0V ±5%; GND = OV
CLOCK AND GATE TIMING
8253·5

8253
PARAMETER

SYMBOL

Note 1:

MIN.

MAX.

MIN.

MAX.

UNIT

de

380

de

ns

tCLK

Clock Per iod

380

tpWH

High Pulse Width

230

230

ns

tPWL

Low Pulse Width

150

150

ns

tGW

Gate Width High

150

150

ns

tGL

Gate Width Low

100

100

ns

tGS

Gate Set Up Time to CLKt

100

100

ns

tGH

Gate Hold Time After CLKt

50

50

ns

too

Output Delay From CLK.j,I1]

400

400

ns

tOOG

Output Delay From Gate,!,!1]

300

300

ns

Test Conditions: 8253: CL

= 1 OOpF; 8253·5:

CL

= 150pF.

6·222

inter
8255A, 8255A-5
PROGRAMMABLE PERIPHERAL INTERFACE
Compatible 8255A-5
• 24MCS-85™
Programmable I/O Pins

•
• Completely TTL Compatible
Compatible with Intel
• Fully
Microprocessor Families
• Improved Timing Characteristics

Bit Set/Reset Capability Easing
• Direct
Control Application Interface
40 Pin Dual-In-Line Package
• Reduces
System Package Count
•

• Improved DC Driving Capability

The 8255A is a general purpose programmable I/O device designed for use with Intel® microprocessors. It has 241/0 pins
which may be individually programmed in two groups of twelve and used in three major modes of operation. In the first
mode (Mode 0), each group of twelve I/O pins may be programmed in sets of 4 to be input or output. In Mode 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining four pins three are used for
handshaking and interrupt control signals. The third mode of operation (Mode 2) is a Bi-directional Bus mode which uses 8
lines for a bi-directional bus, and five lines, borrowing one from the other group, for handshaking.

PIN CONFIGURATION

8255A BLOCK DIAGRAM

DATA

'"'

PIN NAMES
01-00

DATA BUS !BI-DIRECT10NAL}

RESET

RESET INPUT

CS
AD
WR

CHIP SELECT
READ INPUT

WRITE INPUT

AO, A 1

PORT ADDA ESS

PA7-PAO

PORT A (BIT)

P87·PBO
PC7·PCO

PORT B IBITI
PORT C IBITI

Vee
GNO

+5 VOL 1S
gVOLTS

6-223

8255A, 8255A-5

8255 BASIC FUNCTIONAL DESCRIPTION

General
The 8255 is a Programmable Peripheral Interface (PPI) device designed for use in Intel Microcomputer Systems_ Its
function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus.
The functional configuration of the 8255 is programmed by
the system software so that normally no external logic is
necessary to interface peripheral devices or structures.

Data Bus Buffer
This 3-state, bi-directional, eight bit buffer is used to interface the 8255 to the system data bus. Data is transmitted
or received by the buffer upon execution of INput or
OUTput instructions by the CPU. Control Words and Status
information are also transferred through the Data Bus buffer.

(RD)
Read: A "low" on this input pin enables the 8255 to send
the Data or Status information to the CPU on the Data
Bus. In essence, it allows the CPU to "read from" the
8255.

(WR)
Write: A "low" on this input pin enables the CPU to write
Data or Control words into the 8255.

(AO and Al)
Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of
one of the three ports or the Control Word Register. They
are normally connected to the least significant bits of the
Address Bus (Ao and A 1 ).

8255 BASIC OPERATION
AO
0
1
0

RD

0
0
1

0
0
1
1

0
1
0
1

X
1
X

A,

Read/Write and Control Logic
The function of this block is to manage all of the internal
and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the
Control Groups.

,

INPUT OPERATION (READ)

WR

CS

1
1

0
0
0

PORT A => DATA BUS
PORT B => DATA BUS
PORT C => DATA BUS
OUTPUT OPERATION
(WRITE)

1
1
1
1

0
0
0
0

0
0
0
0

DATA
DATA
DATA
DATA

X
1

X
0

X
1

1
0

DATA BUS => 3-STATE
ILLEGAL CONDITION

X

1

1

0

DATA BUS => 3-STATE

0
0
0

BUS =>
BUS =>
BUS =>
BUS =>

PORT A
PORT B
PORT C
CONTROL

DISABLE FUNCTION

Chip Select: A "low" on this input pin enables the communication between the 8255 and the CPU.

8255 Block Diagram
6-224

8255A, 8255A-5
I

(RESET)

Ports A, B, and C

Reset: A "high" on this input clears all internal registers including the Control Register and all ports (A, B, C) are set
to the input mode.

The 8255 contains three 8-bit ports (A, B, and C). All can
be configured in a wide variety of functional characteristics
by the system software but each has its own special features
or "personality" to further enhance the power and flex ibil ity of the 8255.

Group A and Group B Controls
The functional configuration of each port is programmed
by the systems software. In essence, the CPU "outputs" a
control word to the 8255. The control word contains information such as "mode", "bit set", "bit reset" etc. that initializes the functional configuration of the 8255.
Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Write Control Logic, receives
"control words" from the internal data bus and issues the
proper commands to its associated ports.
Control Group A - Port A and Port C upper (C7-C4)
Control Group B - Port B and Port Clower (C3-CO)

I
I

Port A: One 8-bit data output latch/buffer and one 8-bit
data input latch.
Port B: One 8-bit data input/output latch/buffer and one
8-bit data input buffer.
Port C: One 8-bit data output latch/buffer and one 8-bit
data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4bit port contains a 4-bit latch and it can be used for the
control signal outputs and status signal inputs in conjunction with Ports A and B.

The Control Word Register can Only be written into. No
Read operation of the Control Word Register is allowed.

8255 BLOCK DIAGRAM

PIN CONFIGURATION
PA'
PA'

PAS

PA,

PAG
PA7

Os

RESET

A'

0,

D,
D,
PC7

D,
D,

PCS

D,

PC4

D,

PCO

0,

PC,

VCC

PBO

PBS

PB'

PB4

PB,

PB'

PBG

PIN NAMES
DATA BUS (BI·DIRECTIONAL)

~SET

I REstTIN.~P~UT~·_--______~

CS

,CHIP SELECT

RD_
I WR

---1

-+-

READ

INPU~-_-.~~=-_ __
---I

WRITE INPUT

~~n+_~~~RESS

m~~+~IT) -~~
; pe7·paO
pe7·pea

' ~~:r B (BIT) ----------I
PORT C (BIT}_ _
+5 VOL1S

11 VOLTS

6-225

8255A, 8255A-5

8255 DETAILED OPERATIONAL DESCRIPTION
CONTROL WORD

Mode Selection
There are three basic modes of operation that can be selected by the system software:

ID71 D6

D51 D41 D31 D, I D, I Do I
LJ

Mode 0 - Basic Input/Output
Mode 1 - Strobed Input/Output
Mode 2 - Bi-Directional Bus

/

When the RESET input goes "high" all ports will be set to
the Input mode (Le_, all 24 lines will be in the high impedance state)_ After the RESET is removed the 8255 can
remain in the Input mode with no additional initialization
required_ During the execution of the system program any
of the other modes may be selected using a single OUTput
instruction_ This allows a single 8255 to service a variety of
peripheral devices with a simple software maintenance routine_

GROUP B

\

PORT C (LOWER)

'-----

1'" INPUT
0"" OUTPUT

PORTS
1 == INPUT

0'" OUTPUT

MODE SELECTION

O=MODEO
1'" MODE 1

The modes for Port A Oild Port B can be separately defined,
while Port C is divided into two portions as required by the
Port A and Port B definitions_ All of the output registers, including the status flip-flops, will be reset whenever the
mode is changed_ Modes may be combined so that their
functional definition can be "tailored" to almost any I/O
structure_ For instance; Group B can be programmed in
Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1
to monitor a keyboard or tape reader on an interrupt-driven
basis_

/

GROUP A

\

PORT C (UPPER)

1'" INPUT
0== OUTPUT

PORT A
1 == INPUT
0= OUTPUT
MODE SELECTION

00'" MODE 0
01'" MODE 1
lX '" MODE 2

MODE SET FLAG

1 == ACTIVE
ADDRESS BUS

c=

CONTROL BUS

~~--1'-~rl______D~A~T~A~BU~S______~,_,_--~

~Z

f1

11

Mode Definition Format

MODE 0

The Mode definitions and possible Mode combinations may
seem confusing at first but after a cursory review of the
complete device operation a simple, logical I/O approach
will surface_ The design of the 8255 has taken into account
things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to
support almost any peripheral device with no external logic_
Such design represents the maximum use of the available
pins_

MDDE 1 ---..:rLk~----7/0t~l
t !~I::::rr:It?--1B~:I/~
PB7-PS o

C~~TI7gL

C~~TI~gL

PA7-PAo

Single Bit Set/Reset Feature
Any of the eight bits of Port C can be Set or Reset using a
single OUTput instruction_ This feature reduces software
requirements in Control-based applications_

Basic Mode Definitions and Bus Interface

6-226

8255A, 825SA-S
When Port C is being used as status/control for Port A or B,
these bits can be set or reset by using the Bit Set/Reset operation just as if they were data output ports.

CONTROL WOAD

Interrupt Control Functions
When the 8255 is programmed to operate in Mode 1 or
Mode 2, control signals are provided that can be used as
interrupt request inputs to the CPU. The interrupt request
signals, generated from Port C, can be inhibited or enabled
by setting or resetting the associated I NTE flip-flop, using
the Bit set/reset function of Port C.

BIT SET/RESET
1 = SET
0= RESET

This function allows the Programmer to disallow or allow a
specific I/O device to interrupt the CPU without affecting
any other device in the interrupt structure.
I NTE flip-flop definition:
BIT SET/RESET FLAG

(BIT-SET) - INTE is SET - Interrupt enable
(BIT-RESET) -INTE is RESET -Interrupt disable

0= ACTIVE

Note: All Mask flip-flops are automatically reset during
mode selection and device Reset.

Bit Set/Reset Format

Operating Modes
Mode 0 (Basic Input/Output)
This functional configuration provides simple Input and
Output operations for each of the three ports. No "handshaking" is required, data is simply written to or read from
a specified port.

.

.'-,

AD

Mode 0 Basic Functional Definitions:
• Two 8-bit ports and two 4-bit ports.
• Any port can be input or output.
• Outputs are latched.
• Inputs are not latched.
• 16 different Input/Output configu rations are possible
in this Mode.
t RR - - - -

7

C'R--

L

-tHR-1

INPUT

t==t

-tRA'-~1

AR - - - - -

CS. A1, AD

DrDo- -

-

-

-

-

-

-

-

i~.
<'----tRO------'~

1 _ . tOF

~J- --

Mode 0 (Basic Input)

WA

~------~A-------

CS, A1, AO

OUTPUT

Mode 0 (Basic Output)
6-227

1

8255A, 8255A-5
MODE 0 PORT DEFINITION CHART
A

B

GROUP A

GROUP B

PORTC

PORTC

04

03

01

DO

PORTA

0
0
0
0
0
0
0
0

0
0

0
0

0
1

OUTPUT
OUTPUT

0
0

1

OUTPUT

1

0
1

OUTPUT

OUTPUT

3

INPUT

INPUT

1
1

0

0

OUTPUT

INPUT

4

OUTPUT

OUTPUT

0
1

1
0

OUTPUT

INPUT

5

OUTPUT

INPUT

OUTPUT

INPUT

6

INPUT

OUTPUT

7
8

INPUT

INPUT

OUTPUT

OUTPUT

-

1

#

PORT B
OUTPUT

OUTPUT

0
1

OUTPUT

INPUT

OUTPUT

2

INPUT

OUTPUT

(UPPER)
OUTPUT

1

1

1

OUTPUT

INPUT

1

0

0

0

INPUT

OUTPUT

1

0

0

1

INPUT

OUTPUT

1

1
1

0

INPUT

OUTPUT

1

0
0

1

INPUT

1

1

0

0

INPUT

1

1

0

1

INPUT

1

1

1

0

INPUT

1

1

1

1

INPUT

INPUT

(LOWER)
OUTPUT

OUTPUT

INPUT

INPUT

OUTPUT

OUTPUT

9
10
11

INPUT

INPUT

INPUT

12

OUTPUT

OUTPUT

INPUT

13

OUTPUT

INPUT

INPUT

14

INPUT

OUTPUT

15

INPUT

INPUT

MODE 0 CONFIGURATIONS
CONTROL WORD #0

0,

D,

l' I

0,

D,

CONTROL WORD #2

0,

0,

0,

Io I I Io I IoI
0

0

I

0

0

D,

0,

DO

8

A

1

D,

0,

D,

I I I I I
0

0

0

0

0,

D,

DO

0

1

I I

4

PC 7 -PC4

4

8

pe3 -pc O

B

PB 7 -PB o

I

1

0,

D,

0,

I I I I I
0

0

0

0

0,

0,

DO

0

0

1

I

I

0,

I

l' I
8

A

0,

o

0,

I

0

0,

0,

0,

I0 I0

0

1

0,

ill

.

I

I

PA 7-PAo

4

.

;8
I

PC T PC 4

pe 3 -pc O

PB 7 -PB o

DO

I

I

1

8

A

PA7 -PAc

8255

8255

D7-DO

PArPAo

CONTROL WORD #3

CONTROL WORD #1

0,

4

c{

D7-DO ..

B

D,

8

A

8255

c{

..

0

PA7 ·PAo

8255

D 7·Do

I

4

c{

/"
8

.

4

Pe3 -PC O

c{ .

I

PB7·PBo

B

.

I

D7"DO •
I

B

PC7 -PC 4

6-228

PC7 -PC4

/4

pe3 -pcO

/8

PB7 ,PBo

8255A, 8255A-5

CONTROL WORD #4

D,

I

D,

D5

D,

CONTROL WORD #8

D3

D,

D,

D,

DO

0

0

0

1

0

0

0

8

A

,
,

8255

c{

.

°7-0 0 •

8

B

D5

D.

l' I

0,

0

0

D,

0,

1

0

0

l' I

0

D5

I

0

0,

I

0

8

,
,
8

0,

0,

DO

0

1

0

c{

°7-0 0 •

I

8

PA 7 -PA O

PC7 -PC 4

pe 3 -pc O

PS7 -PSo

05

0,

03

D,

0,

I I I Io Io I
o

0

1

0

DO

l' I
/8

A

J

,

8255

pe 3 -pc O

c{ .

PB7 ·PSo

B

PC 7 ·PC 4

°7-0 0 •

/

J

,
8

PA 7 ·pAo

PC 7 ·PC 4

pe 3 -pc O

PS7 -PSo

l' I
8

.

D.

o

05

0,

D3

0,

0,

DO

Io I Io Io I I I
1

1

0

8

A

PA 7 "PAO

,
,

8255

/'

J

,
8

c{

PC 7 -PC 4
°7- 0 0
pel-pcO

/8

B

PB7 -PSo

I

PA 7 ,PAa

PC 7 -PC 4

pe 3 -pc O

PB7 ·PSo

CONTROL WORD #11

D5

0,

0,

D,

0,

Do

0

0

1

0

1

1

I I I I I I I

0,

I

0

8

A

.

,

c{ .

J

.

I

B

D.

05

0,

D3

0,

0,

DO

1, I I I I I o I I

8255

D7 -0 0 -

1

D.

PA,·pAo

CONTROL WORD #7

0

,
,

B

D,

B

1

/8

J

c{

PS7 -PS o

I I I I I
1

8255

D.

0

CONTROL WORD #10

D3

A

D,

Io I Io Io I I I

pe 3 -pc O

CONTROL WORD #6

D.

Do

0

°7-°0--

I

B

OJ

D,

D,

PC 7 -PC 4

l' I

c{

.

•

D3

1

A

0,

A

7 ,0 0

D,

8255

DO

8255

°

D5

CONTROL WORD #9

03

I I I I I
0

0

PA 7 ,PAc!

CONTROL WORD #5

D,

D.

l' I

I I I I I I I I

1

/'
/8

0

1

0

1

I

1

A

PA 7 ,PAa
8255
PC 7 -PC 4
°7- 0 0
pe 3 -pc O

c{
B

PBrPBn

6-229

.

/8

J

,
,
8

PA7 -PA a

PC 7 -PC4

pe 3 -pc O

PS7 ,PSO

8255A, 8255A-5

CONTROL WORD #12

07

D6

Os

D4

CONTROL WORD #14

D3

02

0,

07

DO

I

c{

.

.

I,

05

1 0 1 0

04

1

03

1

1

DO

01

1

I

1

A

.

,,8

.

•

c{

8

B

,'

.
•

,,8

CONTROL WORD #15

03

I, I,

02

01

1 0 1 0

07

DO

I, I
A

06

Os

04

03

.

02

0,

,

,8

00

A

8

8255

8255

.

02

8255

CONTROL WORD #13

06

1

04

. ,"

B

07

1

Os

,,8

A

8255

06

c{
B

~-

.

.

,,

8

.

c{
B

•
•
8

Operating Modes

Mode 1 Basic Functional Definitions:

Mode 1 (Strobed Input/Output)

• Two Groups (Group A and Group B)
• Each group contains one 8-bit data port and one 4-bit
control/data port.
• The 8-bit data port can be either input or output.
Both inputs and outputs are latched.
• The 4-bit port is used for control and status of the
8-bit data port.

This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction
with strobes or "handshaking" signals. In Mode 1, Port A
and Port B use the Iines on Port C to generate or accept
these "handshaking" signals.

6·230

8255A, 8255A-5

Input Control Signal Definition
MODE 1 (PORT A)

STB (Strobe Input)

A "low" on this input loads data into the input latch.

CONTROL WORD
r - -....,

IBF (Input Buffer Full F/F)

I INTE I

~~~J

A "high" on this output indicates that the data has been
loaded into the input latch; in essence, an acknowledgement
IBF is set by STB input being low and is reset by the rising
edge of the RD input.

CL

INTR (Interrupt Request)
A "high" on this output can be used to interrupt the CPU
when an input device is requesting service. INTR is set by
the STB is a "one", IBF is a "one" and INTE is a "one".
It is reset by the falling edge of RD. This procedure allows
an input device to request service from the CPU by simply
strobing its data into the port.

MODE 1 (PORT B)

INTE A

Controlled by bit set/reset of PC 4.
INTE B

Controlled by bit set/reset of PC 2 .

Mode 1 Input

1_________ - t ST - -

\
SlB
-'

IBF

l

I

1
tSIT

--.,1
I

1--7

:1

INTR

1-'RI8_)
If

/

/

I--t'H-1
INPUT FROM
PERIPHERAL

---

I.

tps

.

---------------------

Mode 1 (Strobed Input)

6-231

8255A, 8255A-5

Output Control Signal Definition
MODE 1 (PORT A)

OBF (Output Buffer Full F/F)
The OBF output will go "low" to indicate that the CPU has
written data out to the specified port. The OBF F/F will be
set by the rising edge of the WR input and reset by ACK
input being low.

CONTROL WORD

ACK (Acknowledge Input!
A "low" on this input informs the 8255 that the data from
Port A or Port B has been accepted. In essence, a response
from the peripheral device indicating that it has received
the data output by the CPU.
INTR (Interrupt Request!

MODE 1 (PORT B)

A "high" on this output can be used to interrupt the CPU
when an output device has accepted data transm itted by the
CPU. INTR is set when ACK is a "one", OBF is a "one"
and INTE is a "one". It is reset by the falling edge
of WR.

P~.PBo

CONTROL WORD

INTEA
Controlled by bit set/reset of PC 6.
WR-

INTE B
Controlled by bit set/reset of PC 2 .

Mode 1 Output

INTR

OUTPUT

Mode 1 (Strobed Output)

6·232

8

8255A, 8255A-5
Combinations of Mode 1
Port A and Port B can be individually defined as input or
output in Mode 1 to support a wide variety of strobed I/O
applications.

PA 7 -PA O

PC,

rnA

PC5

IBFA

PC,

CONTROL WORD

PC,

pe 3

INTRA

INTRA

2

pe6,7

2

----f-- 1/0

PC,

PC4. 5

--f-

I/O

OBFS

PC o

PC,

1BFa

PC o

INTRa

PORT A - (STROBED OUTPUT)
PORT B - (STROBED INPUT)

PORT A - (STROBED INPUT)
PORT B - (STROBED OUTPUT)

Operating Modes

Output Operations

Mode 2 (Strobed Bi-Directional Bus I/O)

OBF (Output Buffer Full)

This functional configuration provides a means for com·
municating with a peripheral device or structure on a single
a-bit bus for both transmitting and receiving data (bi-directional bus I/O). "Handshaking" signals are provided to main·
tain proper bus flow discipline in a similar manner to Mode
1. Interrupt generation and enable/disable functions are
also available.

The OBF output will go "low" to indicate that the CPU has
written data out to Port A.

Mode 2 Basic Functional Definitions:
• Used in Group A only.
• One a-bit, bi-directional bus Port (Port A) and a 5·bit
control Port (port C).
• Both inputs and outputs are latched.
• The 5·bit control port (Port C) is used for control
and status for the a-bit, bi-directional bus port (Port

ACK (Acknowledge)
A "low" on this input enables the tri-state output buffer of
Port A to send out the data. Otherwise, the output buffer
will be in the high-impedance state.
INTE 1 (The INTE Flip-Flop associated with OBFI
Controlled by bit set/reset of PCs.

Input Operations
STB (Strobe Input)
A "low" on this input loads data into the input latch.
IBF (Input Buffer Full F/F)

A).

A "high" on this output indicates that data has been loaded
into the input latch.

Bi-Directional Bus I/O Control Signal Definition
INTR (Interrupt Request)
A high on this output can be used to interrupt the CPU for
both input or output operations.

6-233

INTE 2 (The INTE Flip-Flop associated with IBF)
Controlled by bit set/reset of PC4.

8255A, 8255A-5

CONTROL WORD

L

~~2~NPUT
0'" OUTPUT

PORT B
1 = INPUT
0'" OUTPUT
PC51-~~- IBFA
'-~~~~- GROUP B MODE

O=MODEO
1 = MODE 1

3

PC2.~l/a

Mode 2 Control Word

Mode 2

DATA FROM
/ , CPU TO 8255

/

WR

!_______.- tAOB
aBF

\

INTR

i

\'4-t

I

------t-----J

l--- t wOB-

\\-e--s

_--+\\~ ___

\~

-J

r-tSTy
tS_'Bi----It!
~

IBF _ _ _ _ _ _

I

!

-~----tpS--i

PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS

.

~ ~---J-~.~

------------------~------------~--~----+------.

/

DATA FROM
PERIPHERAL TO 8255

DATA FROM
8255 TO 8080

Mode 2 (Bi-directionall

NOTE:

L

Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
(INTR = IBF • MASK. STB • RD + OBF • MASK· ACK • WR )

8255A, 8255A-5

MODE 2 AND MODE 0 (INPUT)

MODE 2 AND MODE 0 (OUTPUT)

PC,

PA 7 "PAO

~

Pc,
peG - A C K A

CONTROL WORD

D7

D6 D5 D4 D3 D2 D,

CONTROL WORD

DO

D7 D6 D5 D4

I ' I ' txtXt>- ~--

PB,

Printer Interface

R,

PC,

PB,

INTERRUPT

R3

STROBE

PB o
CONTROL LOGIC AND DRIVERS

R,

PC 5

-------

PCo

Ro
R,

PC,
CARRIAGE SEI\J.

2

PA u
PA,

PC,

MODEl
(OUTPUT)

R5
SHIFT

PA7

f PB
o

iOUTPUT)

PA,

(OUTPUT)

R,

PB,

PA,

MODEl

FULLY
DECODED
KEYBOARD

-

PAD

PRINTER

R,
R3

PA,

I pes

PC o

PA 3

.

PA,

INTERRUPT
REQUEST

HIGH·SPEED

R,

! PAs

Each peripheral device in a microcomputer system usually
has a "service routine" associated with it. The routine manages the software interface between the device and the CPU.
The functional definition of the 8255 is programmed by the
I/O service routine and becomes an extension of the systems software. By examining the I/O devices interface characteristics for both data transfer and tim ing, and matching
this information to the examples and tables in the Detailed
Operational Description, a control word can easily be developed to initialize the 8255 to exactly "fit" the application. Here are a few examples of typical applications of the
8255.

PA,

Ro

MODE 0

PB,

(INPUT)

PB,

TERMINAL
ADDRESS

'0- -

-- ' 0 - -

-- ':>- --

--

'0- -

--'0---

--u- -

PB5
PB,
PB 7

f-----
/
/

---------------------

Mode 1 (Strobed Input)

INTR

OUTPUT

Mode 1 (Strobed Output)

6-242

8255A, 8255A-5

DATA FROM

/ . 8080 TO 8255

/

/
/'-----

\

~

INTR

....---tAOB~_

i

.II
-tWOB-~

_\

I_IAK~//

~

/,,//;

ACK

/

~

-~tST------------

1\
I SlB
IBF

,
PERIPHERAL
BUS

----------

/

-

1
I

""

J

I
I

.

-tAol__

-I

--__ tPHj.--

DATA~OM

/

DATA~OM

PERIPHERAL TO 8255

1

"r - - - - -

8255 TO PERIPHERAL

/

DATA FROM

8255 TO 8080

Mode 2 {Bi-directionall

NOTE:

Any sequence where WR occurs before ACK and STBoccurs before RD is permissible.
(lNTR = IBF • MASK· STB • RD + OBF • MASK· ACK • WR )

6-243

---

J-'""

inter
M8255A
PROGRAMMABLE PERIPHERAL INTERFACE
Direct Bit Set/Reset Capability Easing
• Control
Application Interface
Pin Dual In-Line Package
• 40Reduces
System Package Count
•
±10%
Power
Supply Tolerance
•

24 Programmable I/O Pins
• Completely
TTL Compatible
• Fully Compatible
with MCS'"-80
• Microprocessor Family

Military Temperature Range
• Full
-55°C to +125°C

The M8255A is a general purpose programmable 1/0 device designed for use with microprocessors. It has 24 1/0 pins
which may be individually programmed in two groups of twelve and used in three major modes of operation. In the first
mode (Mode 0), each group of twelve 1/0 pins may be programmed in sets of 4 to be input or output. In Mode 1, the second
mode, each group may be programmed to have 8 lines of input or output. Of the remaining four pins three are used for
handshaking and interrupt control signals. The third mode of operation (Mode 2) is a Bi-directional Bus mode which uses 8
lines for a bi-directional bus, and five lines, borrowing one from the other group, for handshaking.
Other features of the M8255A include bit set and reset capability and the ability to source 1 mA of current at 1.5volts. This
allows darlington transistors to be directly driven for applications such as printers and high voltage displays.

PIN CONFIGURATION

M8255A BLOCK DIAGRAM

PAO
PAO

POWER

SUPPLIES

W.

I- · ' v

_ _ GND

K:::=:::::>

PA, PAo

RESET
Do

0,
0,
0,

Vee
PB7
PBS

PBO
PBO

""--_0
READ
WRITE

A,--_

CONTROL
LOGIC

A,---

PIN NAMES
°7-0 0

,",--_0

DATA BUS IBI·DIRECTIONAL)

RESET

RESET INPUT

CS
RD
WR
AO,AI
PA7·PAO
PS7-PBO
PC7·PCO
Vee
GND

CHIP SELECT
READ INPUT
WRITE INPUT

PORT ADDRESS
PORTAIBIT)
PORT B IBIT)
PORTC IBIT)
+5 VOLTS

--

~VOLTS

6-244

C::~~:l K·::-------~___, l/'-~" ,~:~~p

, K::::::::::::::)PB/PB

'"

O

ee~!~t~~'NARY

M8255A

1111 .",orne limits a ARa! speclrleatlon So
re subject to eh
. me
'COMMENT: Stresses above those listed under "Abso/~~~e.
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied_ Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias .... _ -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
Voltage On Any Pin
With Respect to GND .... _ . _ . _ ..... -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt

D.C. CHARACTERISTICS
Symbol

TA ~ -55°C to +125°C;Vee ~ +5V ±10%; GND ~ OV

V IL

Parameter
-_..
- --- - - Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

2.4

IOH[l)

Darlington Drive Current

1.0

_..

.. -

"---

Typ.

Min.
_.-

- -

c....

.-

Max.
-_.

Unit
f

....

-

Test Conditions
_.

-.5

.8

V

2.0

Vee

V

.45

V

IOL ~ l.7mA

V

IOH

4.0

mA

~

-50fJA (-100fJA for D_B. Port)

VOH~

1.5V, R EXT = 750D

lee

Power Supply Current

120

mA

IlL

Input Leakage

10

fJA

VIN ~ Vee

ilOFd

Output Float Leakage

10

pA

VOUT ~ 0.45V/Vee

NOTE:
1. Available on 8 pins only.

A.C. CHARACTERISTICS
Symbol

TA ~ -55°C to +125°C, Vee ~ +5V ±10%; GND ~ OV

Parameter

Min. Typ. Max.
400

Pulse Width of WR
Time D.B. Stable Before WR

Unit

50

ns

35

ns

20

ns

20

ns

Time CS Stable Before WR

20

ns

Time CS Stable After WR

35

Time D.B. Stable After WR
Time Address Stable Before

WR

Time Address Stable After WR
-

ns
500

Delay From WR To Output

RD Set-Up Time
Input Hold Time
Delay From RD

~

OTo System Bus

Delay From RD

~

1 To System Bus

ns

405

ns

o
o

ns

10

ns

295

ns

CL

~

100pF

150

ns

CL

~

15pF /1 OOpF

Time Address Stable Before RD

50

ns

Time CS Stable Before RD

50

ns

Width Of ACK Pulse

500

ns

Width Of STB Pulse

500

ns

Set-Up Time For Peripheral

60

ns

180

ns

o

ns

Hold Time For Peripheral
Hold Time for A l , Ao After RD

~

1

6-245

Test Condition

ns

!

I

M8255A
A C CHARACTERISTICS (Continued)
1Re

Hold Time For CS After RD

tAD

Time From ACK
--

tKD

Time From ACK

two

Time From WR

-

tAO

Time From ACK

tSI

Time From STS

--

Time From RD

tRI

CAPACITANCE

0 To Output(Mode 2)

~

1 To Output Floating
--

1 To OSF

~

~

--

~

~

1

~

~

--

~

~

0 To ISF

1 To ISF

~

111

'~.... q ~i.

... s~6.':" slI(l .~:.~

ns

0

20

0
~

0 To OBF

,~. Of

1

1

0

ge"f

400

ns

CL

~

50pF

300

ns

CL

~

15pF /50pF

700

ns

450

ns

450

ns

rec ~ ~F

360

ns

"'Ii,'
fo "q".

"6, 10"

q".9t! •

TA ~ 25°C, Vee ~ GND ~ OV

Symbol

Parameter

Min.

Typ.

Max.

Unit

CIN

Input Capacitance

10

pF

Test Conditions
fe

CliO

I/O Capacitance

20

pF

Unmeasured pins returned
to GND

1 MHz

~

TEST LOAD CIRCUIT:

/

WR

DATA FROM
BOBO TO B255

~(bl

-------Ill

INTR----.\'<>-\~

--------------------------------------~

__ :,'-tAI<-1
,
r------------------

IBF

,-·----fps------PERIPHERAL _ _ _ _ _ _ _ _ _ _
BUS
_

tpH

r----

------f--1....-.-

''---*7---Ji

------------------7-----------------------~------,
DATA FROM
PERIPHERAL TO 8255
DATA FROM

8255 TO 8080

Mode 2 (Bi-directional)

6-246

tRI

8257, 8257-5
PROGRAMMABLE DMA CONTROLLER
Compatible 8257-5
• MCS-85™
Four Channel DMA Controller

• Auto Load Mode
TTL Clock
• Single
• Single +5V Supply
• Expandable
• 40 Pin Dual-In-Line Package

• Priority DMA Request Logic
•
• Channel Inhibit Logic
Count and Modulo 128
• Terminal
Outputs

The 8257 is a four-channel Direct Memory Access (DMA) controller. It is specifically designed to simplify the transfer of
data at high speeds for the Intel® Microcomputer Systems. Its primary function is to generate, upon a peripheral request, a
sequential memory address which will allow the peripheral to read or write data directly to orfrom memory. Acquisition of
the system bus is accomplished via the CPU's HOLD function. The 8257 has priority logic that resolves the peripherals
requests and issues a composite HOLD request to the CPU. It maintains the DMA cycle count for each channel and outputs
a control signal to notify the peripheral that the programmed number of DMA cycles is complete. Other output control
signals simplify sectored data transfers and expansion to other 8257 devices for systems that require more than four
channels of DMA controlled transfer. The 82.57 represents a significant savings in component count for DMA-based
microcomputer systems and greatly simplifies the transfer of data at high speed between peripherals and memories.

PIN CONFIGURATION
IIOR

A,

I/OW

A,

MEM R

A5

MEMW

A4

MARK

Te

BLOCK DIAGRAM

ORO 0

A3
HLDA

DACK 0

A,
A,
Ao

HRG

Vee

es
eLK

do
D,

CLK---

RESET

0,

RESET--_

DACK 2

03

DACK 3

04

Ao-

ORO 3

DACK 0

OR02

OACK 1

A,A,_

ORO 1

Os

ORaD

D.

GND

0,

DACK 1

READI
WRITE

lOGIC
ORO 2

A3

cs
A,
A5
A,

PIN NAMES
07-0 0

DATA BUS

A,-AO

ADDRESS BUS
I/O READ

f70R

i70W
MEMR

I!OWRITE
MEMORY READ

MEMW

MEMORY WRITE

eLK
I RESET

CLOCK INPUT

R-"SET INwr--==

READY READY
HRG

HOLD REOUEST
(TO 8080A)

HLDA

HOLD ACKNOWLEDGE

A,

AEN
ADSTB

ADDRESS STROBE

Te

TERMINAL COUNT

~~
ORQ3-DRCo

READY-

ADDRESS ENABLE

MEMR

DMA REQUEST
INPUT

es
'l:c

+5 VOLTS

GND

GROUND

CHIP SELECT

AND
MODE

HRQ

HlDA ---------

MODULO 128 MARK

DAC K3-DAC Ko DMA ACKNOWLEDGE
OUT

CONTROL
lOGIC

MEMW

AEN
I

ADSTB

Te
MARK

(FROM SOBOA)

6-247

SET
REG.

DACK 3

8257, 8257-5
8257 BASIC FUNCTIONAL DESCRIPTION
General

Block Diagram Description

The 8257 is a programmable, Direct Memory Access
(DMA) device which, when coupled with a single Intel®
8212 I/O port device, provides a complete four-channel
DMA controller for use in Intel® microcomputer systems.
After being initialized by software, the 8257 can transfer a
block of data, containing up to 16,384 bytes, between
memory and a peripheral device directly, without further
intervention required of the CPU. Upon receiving a DMA
transfer request from an enabled peripheral, the 8257:
8257:

1. DMA Channels

• Acquires control of the system bus.
• Acknowledges that requesting peripheral which is
connected to the highest priority channel.
• Outputs the least significant eight bits of the memory
address onto system address lines Ao-A7, outputs
the most significant eight bits of the memory address
to the 8212 I/O port via the data bus (the 8212 places
these address bits on lines As-AI5, and

The 8257 provides four separate DMA channels (labeled
CH-O to CH-3). Each channel includes two sixteen-bit
registers: (1) a DMA address register, and (2) a terminal count register. Both registers must be initialized
before a channel is enabled. The DMA address register is
loaded with the address of the first memory location to be
accessed. The value loaded into the low-order 14-bits of
the terminal count register specifies the number of DMA
cycles minus one before the Terminal Count (TC) output
is activated. For instance, a terminal count of 0 would
cause the TC output to be active in the first DMA cycle for
that channel. In general, if N = the number of desired DMA
cycles, load the value N-1 into the low-order 14-bits of the
terminal count register. The most significant two bits of the
terminal count register specify the type of DMA operation
for that channel:

• Generates the appropriate memory and I/O read/
write control signals that cause the peripheral to
receive or deposit a data byte directly from or to the
addressed location in memory.
The 8257 will retain control of the system bus and repeat
the transfer sequence, as long as a peripheral maintains its
DMA request. Thus, the 8257 can transfer a block of data
to/from a high speed peripheral (e.g., a sector of data on a
floppy disk) in a single "burst". When the specified
number of data bytes have been transferred, the 8257
activates its Terminal Count (TC) output, informing the
CPU that the operation is complete.
The 8257 offers three different modes of operation:
(1) DMA read, which causes data to be transferred from
memory to a peripheral; (2) DMA write, which causes
data to be transferred from a peripheral to memory;
and (3) DMA verify, which does not actually involve the
transfer of data. When an 8257 channel is in the DMA verify
mode, it will respond the same as described for transfer
operations, except that no memory or I/O read/write
control signals will be generated, thus preventing the
transfer of data. The 8257, however, will gain control of the
system bus and will acknowledge the peripheral's DMA
request for each DMA cycle. The peripheral can use these
acknowledge signals to enable an internal access of each
byte of a data block in order to execute some verification
procedure, such as the accumulation of a CRC (Cyclic
Redundancy Code) checkword. For example, a block of
DMA verify cycles might follow a block of DMA read cycles
(memory to peripheral) to allow the peripheral to verify its
newly acquired data.

8257 BLOCK DIAGRAM

6-248

8257, 8257-5
These two bits are not modified during a DMA cycle, but
can be changed between DMA blocks.

BIT 15

BIT 14

TYPE OF DMA OPERATION

Each channel accepts a DMA Request (DR an) input and
provides a DMA Acknowledge (DACKn) output:

o

o

Verify DMA Cycle
Write DMA Cycle
Read OMA Cycle
(Illegal)

I.·

o
1

(ORO 0 - ORO 3)

1

o

DMA Request: These are individual asynchronous channel request inputs used by the peripherals to obtain a DMA
cycle. If not in the rotating priority mode then ORO 0 has
the highest priority and DRO 3 has the lowest. A request
can be generated by raising the request line and holding it
high until DMA acknowledge. For multiple DMA cycles
(Burst Mode) the request line is held high until the DMA
acknowledge of the last cycle arrives.
(OACK 0 - OACK 3)

DMA Acknowledge: An active low level on the acknowledge output informs the peripheral connected to that
channel that it has been selected for a DMA cycle.

2. Oata Bus Buffer

This three-state, bi-directional, eight bit buffer interfaces
the 8257 to the system data bus:
(00-07)

Data Bus Lines: These are bi-directional three-state lines.
When the 8257 is being programmed by the CPU, eightbits of data for a DMA address register, a terminal count
register or the Mode Set register are received on the data
bus. When the CPU reads a DMA address register, a
terminal count register or the Status register, the data is
sent to the CPU over the data bus. During DMA cycles
(when the 8257 is the bus master), the 8257 will output the
most significant eight-bits of the memory address (from
one of the DMA address registers) to the 82121atch via the
data bus. These address bits will be transferred at the
beginning of the DMA cycle; the bus will then be released
to handle the memory data transfer during the balance of
the DMA cycle.

8257 BLOCK OIAGRAM

6-249

i.

8257,8257-5
3. Read/Write logic

(Ao-A3)

When the CPU is programming or reading one of the
8257's register (I.e., when the 8257 is a "slave" device on
the system bus), the Read/Write Logic accepts the I/O
Read (IIOR) or 110 Write (I/OW) signal, decodes the least
significant four address bits, (Ao-A;j), and either writes the
contents of the data bus into the addressed register (if
I/OW is true) or places the contents of the addressed
register onto the data bus (if I/OR is true!.

Address Lines: These least significant four address lines
are bi-directional. In the "slave" mode they are inputs
which select one of the registers to be read or
programmed. In the "master" mode, they are outputs
which constitute the least significant four bits ofthe 16-bit
memory address generated by the 8257.

During DMA cycles (I.e., when the 8257 is the bus
"master"). the Read/Write Logic generates the I/O read
and memory write (DMA write cycle) or I/O Write and
memory read (DMA read cycle) signals which control the
data link with the peripheral that has been granted the
DMA cycle.

Chip Select: An active-low input which enables the I/O
Read or I/O Write input when the 8257 is being read or
programmed in the "slave" mode. In the "master" mode,
CS is automatically disabled to prevent the chip from
selecting itself while performing the DMA function.

(CS)

Note that during DMA transfers Non-DMA I/O devices
should be de-selected (disabled) using "AEN" signal to
inhibit I/O device decoding of the memory address as an
erroneous device address.
(I/OR)
I/O Read: An active-low, bi-directional three-state line. In
the "slave" mode, it is an input which allows the 8-bit
status register or the upper/lower byte of a 16-bit DMA
address register or terminal count register to be read. In
the "master" mode, I/OR is a control output which is used
to access data from a peripheral during the DMA write
cycle.
(I/OW)
I/O Write: An active-low, bi-directional three-state line. In
the "slave" mode, it is an input which allows the contents
of the data bus to be loaded into the 8-bit mode set register
or the upper/lower byte of a 16-bit DMA address register
or terminal count register. In the "master" mode,l/OW is a
control output which allows data to be output to a
peripheral during a DMA read cycle.
(ClK)
Clock Input: Generally from
Generator device. (4)2 TTL)

an Intel® 8224 Clock

(RESET)
Reset: An asynchronous input (generally from an 8224
device) which clears all registers and control lines.

8257 BLOCK DIAGRAM

6-250

8257, 8257-5
4. Control Logic

(TC)

This block controls the sequence of operations during all
DMA cycles by generating the appropriate control signals
and the 16-bit address that specifies the memory location
to be accessed.

Terminal Count: This output notifies the currently
selected peripheral that the present DMA cycle should be
the last cycle for this data block. If the TC STOP bit in the
Mode Set register is set, the selected channel will be
automatically disabled at the end of that DMA cycle. TC is
activated when the 14-bit value in the selected channel's
terminal count register equals zero. Recall that the loworder 14-bits of the terminal count register should be
loaded with the values (n-1). where n =the desired number
of the DMA cycles.

(A4-A)

Address Lines: These four address lines are three-state
outputs which constitute bits 4 through 7 of the 16-bit
memory address generated by the 8257 during all DMA
cycles.
(READY)

(MARK)

Ready: This asynchronous input is used to elongate the
memory read and write cycles in the 8257 with wait states
if the selected memory requires longer cycles.

Modulo 128 Mark: This output notifies the selected
peripheral that the current DMA cycle is the 128th cycle
since the previous MARK output. MARK always occurs at
128 (and all multiples of 128) cycles from the end of the
data block. Only if the total number of DMA cycles (n) is
evenly divisable by 128 (and the terminal count register
was loaded with n-1). will MARK occur at 128 (and each
succeeding multiple of 128) cycles from the beginning of
the data block.

(HRQ)
Hold Request: This output requests control of the system
bus. In systems with only one 8257, HRQ will normally be
applied to the HOLD input on the CPU.
(HLDA)
Hold Acknowledge: This input from the CPU indicates
that the 8257 has acquired control of the system bus.
(MEMR)
Memory Read: This active-low three-state output is used
to read data from the addressed memory location during
DMA Read cycles.
(MEMW)
Memory Write: This active-low three-state output is used
to write data into the addressed memory location during
DMA Write cycles.
(ADSTB)
Address Strobe: This output strobes the most significant
byte of the memory address into the 8212 device from the
data bus.
(AEN)
Address Enable: This output is used to disable (float) the
System Data Bus and the System Control Bus. It may also
be used to disable (float) the System Address Bus by use
of an enable on the Address Bus drivers in systems to
inhibit non-DMA devices from responding during DMA
cycles. It may be further used to isolate the 8257 data bus
from the System Data Bus to facilitate the transfer ofthe 8
most significant DMA address bits over the 8257 data I/O
pins without subjecting the System Data Bus to any
timing constraints for the transfer. When the 8257 is used
in an I/O device structure (as opposed to memory
mapped), this AEN output should be used to disable the
selection of an I/O device when the DMA address is on the
address bus. The I/O device selection should be
determined by the DMA acknowledge outputs for the 4
channels.

8257 BLOCK DIAGRAM

6-251

8257, 8257-5
5. Mode Set Register
When set, the various bits in the Mode Set register enable
each of the four DMA channels, and allow four different
options for the 8257:
7

6

5

4

~",","ro'MY{n

Enables TC STOP

Enables EXTENDED WRITE
Enables ROTATING PRIORITY

1

0

I~

Enables
Enables
Enables
L-----Enables

1

DMA
DMA
DMA
DMA

Channel
Channel
Channel
Channel

Note that rotating priority will prevent anyone channel
from monopolizing the DMA mode; consecutive DMA
cycles will service different channels if more than one
channel is enabled and requesting service. All DMA
operations began with Channel a initially assigned to the
highest priority for the first DMA cycle.

Extended Write Bit 5

0
1
2
3

The Mode Set register is normally programmed by the
CPU after the DMA address registeris) and terminal
count register(s) are initialized. The Mode Set Register is
cleared by the RESET input, thus disabling all options,
inhibiting all channels, and preventing bus conflicts on
power-up. A channel should not be left enabled unless its
DMA address and terminal count registers contain valid
values; otherwise, an inadvertent DMA request (DROn)
from a peripheral could initiate a DMA cycle that would
destroy memory data.
The various options which can be enabled by bits in the
Mode Set register are explained below:
Rotating Priority Bit 4
In the Rotating Priority Mode, the priority of the channels
has a circular sequence. After each DMA cycle, the
priority of each channel changes. The channel which had
just been serviced will have the lowest priority.

If the EXTENDED WRITE bit is set, the duration of both the
MEMW and I/OW signals is extended by activating them
earlier in the DMA cycle. Data transfers within microcomputer systems proceed asynchronously to allow
use of various types of memory and I/O devices with
different access times. If a device cannot be accessed
within a specific amount of time it returns a "not ready"
indication to the 8257 that causes the 8257 to insert one or
more wait states in its internal sequencing. Some devices
are fast enough to be accessed without the use of wait
states, but if they generate their READY response with the
leading edge of the I/OW or MEMW signal (which
generally occurs late in the transfer sequence), they
would normally cause the 8257 to enter a wait state
because it does not receive READY in time. For systems
with these types of devices, the Extended Write option
provides alternative timing for the I/O and memory write
signals which allows the devices to return an early READY
and prevents the unnecessary occurrence of wait states in
the 8257, thus increasing system throughput.

TC Stop Bit 6
If the TC STOP bit is set, a channel is disabled (i.e., its
enable bit is reset) after the Terminal Count (TC) output
goes true, thus automatically preventing further DMA
operation on that channel. The enable bit for that channel
must be re-programmed to continue or begin another
DMA operation. If the TC STOP bit is not set, the
occurrence of the TC output has no effect on the channel
enable bits. In this case, it is generally the responsibility of
the peripheral to cease DMA requests in orderto terminate
a DMA operation.
If the ROTATING PRIORITY bit is not set (set to a zero),
each DMA channel has a fixed priority. In the fixed priority
mode, Channel a has the highest priority and Channel 3
has the lowest priority. If the ROTATING PRIORITY bit is
set to a one, the priority of each channel changes after
each DMA cycle (not each DMA request). Each channel
moves up to the next highest priority assignment, while
the channel which has just been serviced moves to the
lowest priority assignment:

CHANNEL--'- CH-O CH-1 CH-2 CH-3
JUST SERVICED
Priority _
Assignments

Highest

~

Lowest

CH-1
CH-2
CH-3
CH-O

CH-2
CH-3
CH-O
CH-1

CH-3
CH-O
CH-1
CH-2

CH-O
CH-1
CH-2
CH-3

Auto Load Bit 7
The Auto Load mode permits Channel 2 to be used for
repeat block or block chaining operations, without
immediate software intervention between blocks. Channel 2 registers are initialized as usual for the first data
block; Channel 3 registers, however, are used to store the
block re-initialization parameters (DMA starting address,
terminal count and DMA transfer mode). After the first
block of DMA cycles is executed by Channel 2 (i.e., after
the TC output goes true), the parameters stored in the
Channel 3 registers are transferred to Channel 2 during an
"update" cycle. Note that the TC STOP feature, described
above, has no effect on Channel 2 when the Auto Load bit
is set.

6-252

8257, 8257-5
If the Auto Load bit is set, the initial parameters for
Channel 2 are automatically duplicated in the Channel 3
registers when Channel 2 is programmed. This permits
repeat block operations to be set up with the programming
of a single channel. Repeat block operations can be used
in applications such as CRT refreshing. Channels 2 and 3
can still be loaded with separate values if Channel 2 is
loaded before loading Channel 3. Note that in the Auto
Load mode, Channel 3 is still available to the user if the
Channel 3 enable bit is set, but use of this channel will
change the values to be auto loaded into Channel 2 at
update time. All that is necessary to use the Auto Load
feature for chaining operations is to reload Channel 3
registers at the conclusion of each update cycle with the
new parameters for the next data block transfer.
Each time that the 8257 enters an update cycle, the update
flag in the status register is set and parameters in Channel
3 are transferred to Channel 2, non-destructively for
Channel 3. The actual re-initialization of Channel20ccurs
at the beginning of the next channel 2 DMA cycle after the
TC cycle. This will be the first DMA cycle of the new data
block for Channel 2. The update flag is cleared at the
conclusion of this DMA cycle. For chaining operations,
the update flag in the status register can be monitored by
the CPU to determine when the re-initialization process
has been completed so that the next block parameters can
be safely loaded into Channel 3.

6. Status Register
The eight-bit status register indicates which channels
have reached a terminal count condition and includes the
update flag described previously.

Te STATUS FOR CHANNEL
Te STATUS FOR CHANNEL
- - - T e 5T AT US FOR CHANN E L
--~TC STATUS FOR CHANNEL

The TC status bits are set when the Terminal Count (TC)
output is activated for that channel. These bits remain set
until tile status register is read or the 8257 is reset. The
UPDATE FLAG, however, is not affected by a status
register read operation. The UPDATE FLAG can be
cleared by resetting ihe 8257, by changing to the non-auto
load mode (i.e., by resetting the AUTO LOAD bit in the
Mode Set register) or it can be left to clear itself at the
completion of the update cycle. The purpose of the
UPDATE FLAG is to prevent the CPU from inadvertently
skipping a data block by overwriting a starting address or
terminal count in the Channel 3 registers before those
parameters are properly auto-loaded into Channel 2.

--I ~~~AB~~~~R1S II~ ~1~~~AB~~~~Ri Ii

0
1
2
3

-I

I

ETC - -

I

I/O WRITE

\

flJ1Jl.JL - - ~1\-

DRQ2

I~-- DATA BLOCK 1 ----

I

!

....

1

i

TC

\

\

________________-'n

i-

!
!

!

,

1

-- JlJU1J1JL.fl- DATA 8LOCK 2

I

-------

1

1_ _\

I

+- - - - -\

DATA BLOCK 3 -

I

I!

nL._+I_f-1___
( I
I

I\\./!
--------------------------'~~'~I--------~~~----1\

UPDATE FLAG

\

AUTOLOAD TIMING

6-253

/

8257,8257-5
8257 DETAILED OPERATIONAL SUMMARY
Programming and Reading the 8257 Registers
There are four pairs of "channel registers"; each pair
consisting of a 16-bit DMA address register and a 16-bit
terminal count register (one pair for each channel). The
8257 also includes two "general registers"; one 8-bit
Mode Set register and one 8-bit Status register. The
registers are loaded or read when the CPU executes a
write or read instruction that addresses the 8257 device
and the appropriate register within the 8257. The 8228
generates the appropriate read or write control signal
(generally IIOR or IIOW while the CPU places a 16-bit
address on the system address bus, and either outputs the
data to be written onto the system data bus or accepts the
data being read from the data bus. Allor some of the most
significant 12 address bits A4-A,s (depending on the
systems memory, I/O configuration) are usually decoded
to produce the chip select (CS) input to the 8257. An 1/0
Write input (or Memory Write in memory mapped 1/0
configurations, described below) specifies that the
addressed register is to be programmed, while an 1/0
Read input (or Memory Read) specifies that the addressed
register is to be read. Address bit 3 specifies whether a
"channel register" (A3 = 0) or the Mode Set (program
only)/Status (read only) register (A3 = 1) is to be accessed.

CONTROL INPUT

CS

IIOW

IIOR

A3

Program Hall 01 a
Channel Register

0

0

1

0

Read Hall 01 a
Channel Register

0

1

0

0

Program Mode Set
Register

0

0

1

1

Read Status Register

0

1

0

1

four channels. Because the "channel registers" are 16bits, two program instruction cycles are required to load
or read an entire register. The 8257 contains a first/last
(F/L) flip flop which toggles at the completion of each
channel program or read operation. The F/L flip flop
determines whether the upper or lower byte of the register
is to be accessed. The F/L flip flop is reset by the RESET
input and whenever the Mode Set register is loaded. To
maintain proper synchronization when accessing the
"channel registers" all channel command instruction
operations should occur in pairs, with the lower byte of a
register always being accessed first. Do not allow CS to
clock while eitherllOR or I/OW is active, as this will cause
an erroneous F/L flip flop state. In systems utilizing an
interrupt structure, interrupts should be disabled prior to
any paired programming operations to prevent an
interrupt from splitting them. The result of such a split
would leave the F/L F/F in the wrong state. This problem is
particularly obvious when other DMA channels are
programmed by an interrupt structure.

The least significant three address bits, Ao-Az, indicate the
specific register to be accessed. When accessing the
Mode Set or Status register, Ao-A2 are all zero. When
accessing a channel register bit Ao differentiates between
the DMA address register (Ao = 0) and the terminal count
register (Ao = 1), while bits A, and Az specify one of the

8257 REGISTER SELECTION
ADDRESS INPUTS
REGISTER

BYTE

CH-O DMA Address

"BI-DIRECTIONAL DATA BUS
F/L

OJ

06

Os

0,

03

0,

0,

Do

0
1

AJ
AI5

A6
AI4

As
A,]

A,
AI2

A3
All

A,
AIO

A,
A9

Au
As

1
1

0
1

CJ
Rd

C6
Wr

Cs
Cl3

C,
CI2

C3
CII

C,
CIO

C,
C9

Co
Cs

1
1

0
0

0
1

0
0

1
1

1
1

0
1

0
0

1
1

0
0

0
0

0
1

LSB
MSB

0
0

1
1

0
0

1
1

0
1

CH-3 DMA Address

LSB
MSB

0
0

1
1

1
1

0
0

0
1

CH-3 Terminal Count

LSB
MSB

0
0

1
1

1
1

1
1

0

-

1

0

0

0

0

AL

TCS

EW

RP

EN3

EN2

ENl

ENO

1

0

0

0

0

0

0

0

UP

TC3

TC2

TCl

TCO

A3

A,

AI

Ao

LSB
MSB

0
0

0

0

0
0

0
0

CH-O Terminal Count

LSB
MSB

0
0

0
0

0
0

CH-l DMA Address

LSB
MSB

0
0

0
0

CH-l Terminal Count

LSB
MSB

0
0

CH-2 DMA Address

LSB
MSB

CH-2 Terminal Count

MODE SET (Program only)
STATUS (Read only)

Same as Channel 0

I I I

Same as Channel 0

I I I

Same as Channel 0

1

"Ao-AI5: DMA Starting Address, CO-Cl3: Terminal Count value (N-l), Rd and Wr: DMA Verify (00), Write (01) or Read (10) cycle selection,
AL: Auto Load, TCS: TC STOP, EW: EXTENDED WRITE, RP: ROTATING PRIORITY, EN3-ENO: CHANNEL ENABLE MASK,UP: UPDATE
FLAG, TC3-TCO: TERMINAL COUNT STATUS BITS.

6-254

8257, 8257-5
DMA Operation
Internal 8257 operations may proceed through seven
different states. The duration of a state is defined by the
clock input. When the 8257 is not executing a DMA cycle,
it is in the idle state, SI . A DMA cycle begins when one or
more DMA Request (DRQn) lines become active. The
8257 then enters state So, sends a Hold Request (HRQ) to
the CPU and waits for as many So states as are necessary
for the CPU to return a Hold Acknowledge IHLDA)' For
each So state, the DMA Request lines are again sampled
and DMA priority is resolved (according to the fixed or
rotating priority scheme). When HLDA is received, the
DMA Acknowledge (DACKn) line for the highest priority
requesting channel is activated, thus selecting that
channel and its peripheral for the DMA cycle. The 8257
then proceeds to state SI. Note that the DMA Request
(DRQn) input should remain high until either DACKn is
received for a single DMA cycle service, or until both the
DACKn and TC outputs are received when transferring an
entire data block in a "burst" mode. If the 8257 should lose
control of the system bus (i.e., if HLDA goes false), the
DMA Acknowledge will be removed after the current DMA
cycle is completed and no more DMA cycles will occur
until the 8257 again acquires control of the system bus.
Each DMA cycle will consist of at least four internal
states: SI, S2, S3, and S4. If the access ti me for the memory
or I/O devices involved is not fast enough to return the
required READY response and complete a byte transfer
within the specified amount of time, one or more wait
states (SW) are inserted between states S3 and S4. Recall
that in certain cases the Extended Write option can
eliminate the need for a wait state. Note that a READY
response is not required during DMA verify cycles.
Specified minimum/maximum values for READY setup
time (tRS), write data setup time (tDW), read data access
time (tRD) and HLDA setup time (tQs) are listed under A.C.
CHARACTERISTICS and are illustrated in the accompanying timing diagrams.

RESET

I

i

r

(11

l
~

HRQ

HRQ

~o~

HLDA

HLDA

Y
Y
1. HRG is set if DROll is active.
2. HRD is reset If OROl) IS not active.

DMA OPERATION STATE DIAGRAM

During DMA write cycles, the I/O Read (I/OR) output is
generated at the beginning of state S2 and the Memory
Write (MEMW) output is generated at the beginning of S3.
During DMA read cycles, the Memory Read (MEMR)
output is generated at the beginning of state S2 and the I/O
Write (I/OW) output goes true at the beginning of of state
S3. Recall that no read or write control signals are
generated during DMA verify cycles. Extended WR for
MEM and I/O will be generated in S2.

6-255

8257, 8257-5
Memory Mapped 1/0 Configurations
The 8257 can be connected to the system bus as a memory
device instead of as an 1/0 device for memory mapped 1/0
configurations by connecting the system memory control
lines to the 8257's 1/0 control lines and the system 1/0
control lines to the 8257's memory control lines.
This configuration permits use of the 8080's considerably
larger repertoire of memory instructions when reading or
loading the 8257's registers. Note that with this
connection, the programming of the Read (bit 15) and
Write (bit 14) bits in the terminal count register will have a
different meaning:

r------iM~E~M;;;R~DI_---~--

I/O RD

MEMWRJ----~-- I/O WR

8257

liD RD

MEM RD

[!OWR

MEMWR

SYSTEM INTERFACE FOR MEMORY MAPPED 1/0

BIT 15

READ

BIT 14
WRITE

o

o

o

1

1

o

DMA Verify Cycle
DMA Read Cycle
DMA Write Cycle
Illegal

TC REGISTER FOR MEMORY MAPPED 1/0 ONLY

6-256

8257

DETAILED SYSTEM INTERFACE SCHEMATIC

25
26
27
29
30
31
32
33
34
35
1
40
37
38
39
36

aoaOA
14
INT-

r,~ft
14 1,5
ose ~

-

14

WR

it

11
10

I
I

I
I
I
I ADDRESS
I

READY

I
I

I

-

I
I
A,5

13
21
17

~3

I
4

12

15

13
16
11
9
5
18
20
7

~
¢,

~

8228

MEIVi"R
15

MEMW
IIOR

1

IjOw
INTA

7

DO

I
I
jDATA
I BUS

I
I
07

24
26
25
27
23

CONTROL

BUS

BUSEN
¢2{TTL)

BUS

I

~
~

RESET

22j

I

~
~
~

SYNC

0,

8224

STSTB

DBIN

19

~~

~

HlDA

10

5

3

RDYIN
RESIN

"". '"

HOLD

AO

10

7

22

HLDA HRO

6

~

~

f--#

f#---

~
26

E---37

~

r--#
23
22
21
3
4
1
2
13
12
11
6

CHIP SELECT

READY

38
39
40

8257

elK

19
25

DROO

18
24

ORO

17
14

os

,.

READY

15
36
5
AEN ADSTB

8

]9

\13
OS2

11
STB
4
6
8
10
15
17
19
21

'---4

~

DISABLE I/O
ADDRESS BUS

------4

'----------i

8212

18
20
22

Vcc~
GND

6-257

elR
MO

OS1

12

'('

DACKO
1

DACK 1
ORO 2
DACK 2
ORO 3
DACK 3

Te
MARK

8257,8257-5

DETAILED SYSTEM INTERFACE SCHEMATIC

A,.
I
I
A,
~

ALE

---2.!..

STB 008-- 001

-:F"

13

DS2
8212

2

MD

CLR

DSf

018- - 01,

r==>

0,

I------

1

Vee

AD

WR

{

~

A,
B,

....2J

~

8,

4

I

7

lOR

I

9

MEMW

[

12

lOW

A3

~ B3

~
13

0,

A_
B_

SELIB) 1

101M

MEMR

0_
CHIP
SELECT

fiE

~

HLOA
CLK lOUT)

---

RESET IN -

RESET OUT

-/

RESET

I------

MEMR

~

lOR

I-----I------

lOW

CONTROL
MEMW BUS

READY

,,1

~

HOLD

DATA BUS

[
Do

~

ADo

A,

BUS
AO

,

[

t-l-

ADDRESS

Vee

~

Af'

B085

A,.

16
READY

CS

Ao

07

I--

I

,

,1,1-----

Do
8257-5

-

t--

'-----

1i

~

-.!a
~
~

--

MEMR

DROo

lOR

DACKo

ORO,

MEMW
-

lOW

DACK,
ORQ2

--

~ HRO

--.2..

-E..
--E..

DAC K2

HLDA

DRQ3
DACK3

CLK

TC

MARK

RESET

AEN

ADSTB

9

8

~

13
DS2

~

~

J"

ClR 5Ta

Oi"
[

D?'
[
DO,

8212

01,

MD

-

DSI

11
6-258

f-

19

DRGo

25

DACK o

18

DROT

24

DACKl

17

OR02

14

DACK2

16

DRQ3

'5
36
5

DACK3

TC
~

MARK

8257, 8257-5
SYSTEM APPLICATION EXAMPLES
\

(I
\

\

\

ADDRESS BUS

CONTROL BUS

'1'1

II

f70W!

IIOR

DATA BUS

11 t}

U DU
DRQO

II
II

1

~J

DISK 1

DACKO

-------

ORQ 1

8257
AND
8212

!

I
I

DISK 2

DACK 1

\

II

f}
SYSTEM

RAM

MEMORY

1-------

ORQ2

DISK 3

DACK 2

------

ORa 3

DISK4

DACK 3
DMA CONTROLLER

FLOPPY DISK CONTROLLER (4 DRIVES)

ORO

8257
AND
8212

8251
DACK

USART

MODEM

TELEPHONE
LINES

HIGH-SPEED COMMUNICATION CONTROLLER

6-259

SYSTEM

RAM
MEMORY

~J

\

8257, 8257-5
DMA MODE WAVEFORMS

CONSECUTIVE CYCLES AND BURST MODE SEQUENCE
SI
CLOCK

ORO 0-3

I

I a

~

I

I

M

I

~

~

---------<-1'1----------1

I a

I m

M

m I W

~~~:~~~~\J~ru~
7

\

)i(

~
HRO

I

S1

so

I"'--'T

/

TDO -

DQ

l'

'i

--

/

I-- TOH

THS ------+-

7'

HLDA

-\. ___ J

1--

TAEl - -

~

tTAET

7'

AEN

-

TFAAB -.......-

ADR 0-7 (LOWER AORI

lfilllili/,

DAT A 0-7 (UPPER AORI

'1111111/1/

~

- r-- t-TS~T

TFADB -----

(lillY111111) 'II, '111111

TSTL -----

---,-

I-

-

TA.

'\

DACK 0-3

TFAC-------_~_

'1111111111/)'

~:=..

I

MEM WR/I/O WR

IfIIIIIIIIIJJ

I

1---:;:-Del

r

7' "1\

---

TAK -----.

TC/MARK

6-260

RWM-I

------ T

1-

I-~

IT

!'i

DCT

TDCT

F~~ ~r-T}H

---

f AHS

rill/IIIIIIIIIIIIIIII, '111111111111111;:

.l1

TRS - -

READY

TAFAB

rllllllllllll;

l~--TA.-I ~TASC

-- I-+---T
l'

\

TDCl -

t-

1----

TAS8

~-

ADR STB

MEM RD/I/O RO

r-- -

TAH -

TAFDB

-

---TASM

/
-

-

\

---

VIIIIIIIIIII/;,
..-- TAFC

1111111111111i.

8257, 8257-5

~

I

~

CONTROL OVERRIDE SEOUENCE

I

a

I

a

I

~

I

SI

SI

S2

~ NOT READY SEOUENCE - - - - - _
~
SW
SW

I

a

SI

SI
CLOCK

!----------J'-I------------t>-------+-----+-- - - - - - - - - -

DRO

O~3

HRO

~------------~----------+---------~

'----

HLDA

AEN

ADR 6~7
(LOWER ADR)

DATA 0-7

(UPPER ADR)

'----1----------+---- - - - - - - - -

ADR STB

DACK

~

_ - TRS

~------------------------+-------'~ \~--------/

ijl;1//iII/I/j/JIj

~

HIGH IMPEDANCE

6-261

O~3

\

READY

TC/MARK

8257, 8257-5
<'Zf},<' 'f:}

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ......... oOe to 700 e
Storage Temperature ... , , , ........ _65°e to +150 o e
Voltage on Any Pin
With Respect to Ground . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 1 Watt

*C0fl!'MENT: ~tresses above those listed ~;;'ciIJ:::,i",
Maximum Ratings" may cause permanent damagt!', ,
device. This is a stress rating only and functional opif'a'J
tion of the device at these or any other conditions above "',"Pi',
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

D.C. CHARACTERISTICS
TA ; oOe to 70°C, Vee; +5V ± 5%, GND ; OV
MIN.

MAX.

UNIT

Input Low Voltage

-0.5

O.S

Volts

2.0

Vee+· 5

Volts

0.45

Volts

IOL; 1.6 mA
IOH;-150IlA for AB,
DB and AEN
IOH;-SOIlA for others
IOH ; -SOIlA

SYMBOL
VIL

PARAMETER

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

2.4

Vee

Volts

VHH

HRQ Output High Voltage

3.3

Vee

Volts

Icc

Vee Current Drain

120

mA

TEST CONDITIONS

IlL

Input Leakage

±10

IlA

VIN ; Vee to OV

IOFL

Output Leakage During Float

±10

IlA

VOUT ; Vee to OV

CAPACITANCE
TA ; 25°C; Vee; GND; ov
MAX.

UNIT

CIN

Input Capacitance

10

pF

fc; 1MHz

CliO

I/O Capacitance

20

pF

Unmeasured pins
returned to G NO

SYMBOL

PARAMETER

MIN.

6-262

TYP.

TEST CONDITIONS

8257,8257-5
A.C. CHARACTERISTICS: PERIPHERAL (SLAVE) MODE
TA ; oOe to 70°C, vee; 5.0V ±5%; GND ; OV (Note 1).
8080 BUS PARAMETERS:
READ CYCLE
8257-5

8257
Symbol

Parameter

Max.

Min.

Min.

Max.

Unit

TAR

Adr or CSt Setup to R D t

0

0

ns

TRA

Adr or cst Hold from RDt

0

0

ns

T RO

Data Access from R D')'

0

300

TOF

DB-->Float Delay from RDt

20

150

TRR

RD Width

WRITE

0

200

ns

20

100

ns

(Note 2)

ns

250

250

Test Conditions

CY~LE:

8257
Symbol

Parameter

TAW

Adr Setup to WRt

TWA

Adr Hold from WRt

Tow

Data Setup to WRt

Two

Data Hold from WRt

Tww

WR Width

Min.

8257-5
Max.

Min.

20

Max.

Unit

20

ns

0

0

ns

200

200

ns

0

0

ns

200

200

ns

Test Conditions

OTHER TIMING:
8257
Symbol

Parameter

TRSTW

Min.

Reset Pulse Width

300
500

8257-5
Max.

Min.

Max.

Unit

TRSTO

Power Supplyt (Vee) Setup to Resett

T,

Signal Rise Time

20

20

ns

Tf

Signal Fall Time

20

20

ns

TRSTS

Reset to First IOWR

Notes:

500

2

Test Conditions

ns

300

/-1S

2

1. All timing measurements are made at the following reference voltages unless specified otherwise:
2. 8257: CL ~ 100pF, 8257-5: CL ~ 150pF.

tey
Input "1" at 2.0V, "0" at O.8V
Output "1" at 2.0V, "0" at 0.8V

8257 PERIPHERAL MODE TIMING DIAGRAM
WRITE TIMING:

READ TIMING:

_ _---., - - - - - T AW~-

CHIPSETECT

ADDRESS BUS

ADDRESS BUS

DATA BUS

iTOFID

//II/IIII/IIII/II$IffIA

DATA BUs1J

RESET TIMING:

INPUT WAVEFORM FOR A.C. TESTS:

6-263

~//Iffffi

8257,8257-5
j,'"

1
"10 ;(,1;/'/,,,",';,1,,

A.C. CHARACTERISTICS: DMA (MASTER) MODE

TA

= O°Cto

70°C, VCC

= +5V ±5%;;(J~g
'"

8257-5

8257
SYMBOL

PARAMETER

MIN.

MAX.

MIN.

h

'}!}""'0

ffii

MAX.

UNIT

Tcy

Cycle Time (Period)

320

4

320

4

f-lS

Til

Clock Active (High)

120

.STCY

SO

.STcy

ns

TOO

DRQt Setup to II HSI,S4)

120

TOH

DRO')' Hold from HLDAt[4]

Too

HROt or ,),Delay from IIt(SI,S4)
(measured at 2.0V) [1]

160

160

ns

TOOl

HROt or ,),Delay from IIt(SI,S4)
(measured at 3.3V)[3]

250

250

ns

THS

HLDAt or tSetup to IIHSI,S4)

TAEL

AENt Delay from IItlSl)[l]

TAET

AENt Delay from IIt(SI)11]

TAEA

Adr(AB)(Active) Delay from AENt(Sl)[4]

TFAAB

Adr(AB)(Active) Delay from IIt(Sl)[2]

TAFAB

Adr(ABHFloat) Delay from IIt(SI)[2]

TASM

Adr(ABHStable) Delay from IIt(Sl )12]

TAH

Adr(AB)(Stable) Hold from ot(Sll[2]

-

120

0

0

100

100
300

ns

200

ns

250

250

ns

150

150

ns

250

ns

200
20

20

250
TASM-50

Adr(AB)(Valid) Hold from Rdt(Sl,SI)[4]

60

60

300

300

TAHW
TFAOB

Adr(DB)(Active) Delay from Ot(Sl )[2]

TAFOB

Adr(DB)(Float) Delay from Ot(S2)[2]

TSTT+20

TASS

Adr(DB) Setup to AdrStb,j,(Sl-S2)[4]

100

TAHS

Adr(DB)(Valid) Hold from AdrStbt(S2)[4]

50

TSTL

AdrStbt Delay from IIt(Sl)[l]

TSTT

AdrStb,), Delay from IIt(S2)[ 1]

Tsw

AdrStb Width (Sl-S2)[4]

ns

TASM-50

TAHR

Adr(AB)(Valid) Hold from Wrt(Sl,SI)[4]

ns
300

300

ns
ns
300

250

TSTT+20

170

100

ns
200

140

ns
ns

50
200

ns

140

ns
ns

TCy-l00

TCy-l00

ns

TASC

Rd.j, or Wr(Ext),), Delay from AdrStbt(S2)[4]

70

70

ns

TOBC

Rd')' or Wr(Ext}t Delay from Adr(DB)
(Float)(S2)[4]

20

20

ns

TAK

DACKt or ,),Delay from 0 HS2,Sl) and
TC/Markt Delay from 0 t(S3) and
TC/Mark.j, Delay from ot (S4)[1.5]

250

250

ns

TOCL

Rd')' or Wr(Extlt Delay from IIt(S2) and
Wrt Delay from ot(S3)[2.6]

200

200

ns

TOCT

Rdt Delay from 1I+(Sl,SI) and
Wrt Delay from IIt(S4)[2.7]

200

200

ns

TFAC

Rd or Wr (Active) from Ot(Sl )[2]

300

300

ns

TAFC

Rd or Wr ,(Float) from IIt(SI)[2]

150

150

ns

TRWM

Rd Width (S2-S1 or SI)[ 4]

TWWM

Wr Width (S3-S4)[ 4]

TCy-50

TCy-50

ns

TWWME

Wr(Ext) Width (S2-S4)[4]

2Tcy-50

2TCy-50

ns

2Tcy+ To-50

2Tcy+ To-50

ns

TRS

READY Set Up Time to ot (S3, Sw)

30

30

ns

TRH

READY Hold Time from lit (S3, Sw)

20

20

ns

Notes:

1. Load = 1 TTL. 2. Load = 1 TTL + 50pF
3. Lo~d = 1 T! L + (R L = 3.3K), VOH
5..H AK < 50 ns. 6. .:l. TOCL < 50 ns. 7. .:l. TOCT < 50 ns. 6-264

=

3.3V.

4. Tracking Specification.

in1er
8259, 8259-5
PROGRAMMABLE INTERRUPT CONTROLLER

• MCS-85™ Compatible 8259-5

• Individual Request Mask Capability
• Single +5V Supply (No Clocks)
• 28 Pin Dual-In-Line Package
• Fully Compatible with Intel CPUs

• Eight Level Priority Controller
• Expandable to 64 Levels

• Programmable Interrupt Modes

The 8259 handles up to eight vectored priority interrupts for the CPU. It is cascadable for up to 64 vectored priority
interrupts, without additional circuitry. It will be packaged in a 28-pin plastic DIP, uses nMOS technology and requires a
single +5V supply. Circuitry is static, requiring no clock input.
The 8259 is designed to minimize the software and real time overhead in handling multi-level priority interrupts. It has
several modes, permitting optimization for a variety of system requirements.

BLOCK DIAGRAM

PIN CONFIGURATION

INT

cs

vee

WR

Ao

AD

INTA

0.,

IR7

D6

IR6

Ds

IR5

D.

lR4

D3

IR3

D2

IR2

D,

IR1

DATA
BUS
BUFFER

Do

IRO

CASO

INT

RD

CAS 1

SP

We

READ!
WRITE
LOGIC

CAS 2

GND

CONTROL LOG Ie

Cs--

PIN NAMES
°7- 0 0

DATA BUS (BI·DlRECTIONAL)

RD
WR

READ INPUT
WRITE INPUT

Ao

COMMAND SELECT ADDRESS

CASO

--

CS

CHIP SELECT

CAS1-CASO

CASCADE LINES

SP

SLAVE PROGRAM INPUT

INT

INTERRUPT OUTPUT

INTA

INTERRUPT ACKNOWLEDGE INPUT

IRO-IR7

INTERRUPT REQUEST INPUTS

CAS 1

SP-------'

6-265

~INTERNAlBUS

8259, 8259-5
INTERRUPTS IN MICROCOMPUTER
SYSTEMS

CPU·DRIVEN
MULTIPLEXOR

CPU

Microcomputer system design requires that I/O devices
such as keyboards, displays, sensors and other components receive servicing in an efficient method so that
large amounts of the total system tasks can be assumed by
the microcomputer with little or no effect on throughput.

RAM

The most common method of servicing such devices is the
Polled approach. This is where the processor must test
each device in sequence and in effect "ask" each one if it
needs servicing. It is easy to see that a large portion of the
main program is looping through this continuence polling
cycle and that such a method would have a serious,
detrimental effect on system throughput thus limiting the
tasks that could be assumed by the microcomputer and
reducing the cost effectiveness of using such devices.
A more desireable method would be one that would allow
the microprocessor to be executing its main program and
only stop to service peripheral devices when it is told to do
so by the device itself. In effect, the method would provide
an external asynchronous input that would inform the
processor that it should complete whatever instruction
that is currently being executed and fetch a new routine
that will service the requesting device. Once this servicing
is complete however the processor would resume exactly
where it left off.

ROM

POLLED METHOD

This method is called Interrupt. It is easy to see that
system throughput would drastically increase, and thus
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.

CPU

The Programmable Interrupt Controller (PIC) functions
as an overall manager in an Interrupt-Driven system
environment. It accepts requests from the peripheral
equipment, determines which of the incoming requests is
of the highest importance (priority), ascertains whether
the incoming request has a higher priority value than the
level currently being serviced and issues an Interrupt to
the CPU based on this determination.

INT

RAM

PIC

ROM

110(1)

Each peripheral device or structure usually has a special
program or "routine" that is associated with its specific
functional or operational requirements; this is referred to
as a "service routine". The PIC, after issuing an Interrupt
to the CPU, must somehow input information into the CPU
that can "point" the Program Counter to the service
routine associated with the requesting device. The PIC
does this by providing the CPU with a 3-byte CALL
instruction.

I/O (2)

I

1

I/O IN)

I

I

1_____ J

INTERRUPT METHOD

6-266

8259, 8259-5
8259 BASIC FUNCTIONAL DESCRIPTION
General
The 8259 is a device specifically designed for use in real
time, interrupt driven, microcomputer systems. It manages eight levels or requests and has built-in features for
expandability to other 8259s (up to 64 levels). It is
programmed by the system's software as an 1/0
peripheral. A selection of priority modes is available to the
programmer so that the manner in which the requests are
processed by the 8259 can be configured to match his
system requirements. The priority modes can be changed
or reconfigured dynamically at any time during the main
program. This means thatthe complete interrupt structure
can be defined as required, based on the total system
environment.
Interrupt Request Register (IRR) and In-Service
Register (ISR)
The interrupts at the IR input lines are handled by two
registers in cascade, the Interrupt Request Register (IRR)
and the In-Service Register (ISR). The IRR is usedto store
all the interrupt levels which are requesting service; and
the ISR is used to store all the interrupt levels which are
being serviced.
Priority Resolver

8259 BLOCK DIAGRAM

This logic block determines the priorities of the bits set in
the IRR. The highest priority is selected and strobed into
the corresponding bit of the ISR during INTA pulse.
INT (Interrupt)
This output goes directly to the CPU interrupt input. The
VOH level on this line is designed to be fully compatible
with the 8080 input level.
INTA (Interrupt Acknowledge)
Three INTA pulses will cause the 8259 to release a 3-byte
CALL instruction onto the Data Bus.
Interrupt Mask Register (IMR)
The IMR stores the bits of the interrupt lines to be masked.
The IMR operates on the ISR. Masking of a higher priority
input will not affect the interrupt request lines of lower
priority.

-,,{LINES

cs

CASO

AD

Ao

WR

INT

INTA

8259

CAS 1
CASZ

SP

SLAVE

PROG.

I

I

rI

INTERRUPT
REQUESTS

8259 INTERFACE TO STANDARD SYSTEM BUS

6-267

8259, 8259-5
Data Bus Buffer
This 3-state, bi-directional, 8-bit buffer is used to interface
the 8259 to the system Data Bus. Control words and status
information are transferred through the Data Bus Buffer.
Read/Write Control Logic
The function of this block is to accept OUTput commands
from the CPU. It contains the Initialization Command
Word (ICW) registers and Operation Command Word
(OCW) registers which store the various control formats
for device operation. This function block also allows the
status of the 8259 to be transferred onto the Data Bus.
CS (Chip Select)
A "low" on this input enables the 8259. No reading or
writing of the chip will occur unless the device is selected.
WR (Write)
A "low" on this input enables the CPU to write control
words (ICWs and OCWs) to the 8259.
RD (Read)
A "low" on this input enables the 8259 to send the status of
the Interrupt Request Register (IRR), In Service Register
(ISR), the Interrupt Mask Register (IMR) orthe BCD olthe
Interrupt level on to the Data Bus.

AO
This input signal is used in conjunction with WR and RD
signals to write commands into the various command
registers as well as reading the various status registers of
the chip. This line can be tied directly to one of the address
lines.

8259 BLOCK DIAGRAM

8259 BASIC OPERATION
Ao

D4

D3

0

RD

WR

0
0

CS

INPUT OPERATION (READ)

0

IRR, ISR or Interrupting Level =?

0

IMR =? DATA BUS

DATA BUS (Note 1)

OUTPUT OPERATION (WRITE)

0

0

0

0

0

0

0

DATA BUS =? OCW2

0

0

DATA BUS=?OCW3

X

0

0

DATA BUS =? ICW1

X

X

0

0

DATA BUS =? OCW1, ICW2, ICW3 (Note 2)

X

X

X

0

DATA BUS =? 3-STATE

X

X

X

0

DISABLE FUNCTION

Note 1:
Note 2:

X

X

DATA BUS =? 3-STATE

Selection of IRR, ISR or Interrupting Level is based on the content of OCW3 written before the READ operation.
On-chip sequencer logic queues these commands into proper sequence.

6-268

8259, 8259-5
3. The CPU acknowledges the I NT and responds with an
INTA pulse.
4. Upon receiving an INTA from the CPU group, the
highest priority ISR bit is set, and the corresponding
IRR bit is reset. The 8259 will also release a CALL
instruction code (11001101) onto the 8-bit Data Bus
through its 07-0 pins.
5. This CALL instruction will initiate two more INTA
pulses to be sent to the 8259 from the CPU group.
6. These two INTA pulses allow the 8259 to release its
preprogrammed subroutine address onto the Data Bus.
The lower 8-bit address is released at the first INTA
pulse and the higher 8-bit address is released at the
second INTA pulse.
7. This completes the 3-byte CALL instruction released
by the 8259. ISR bit is not reset until the end of the
subroutine when an EOI (End of interrupt> command is
issued to the 8259.

SP (Slave Program)
More than one 8259 can be used in the system to expand
the priority interrupt scheme up to 64 levels. In such case,
one 8259 acts as the master, and the others act as slaves. A
"high" on the SP pin designates the 8259 as the master, a
"low" designates it as a slave.
The Cascade Buffer/Comparator
This function block stores and compares the IDs of all
8259 used in the system. The associated three I/O pins
(CASO-2) are outputs when the 8259 is used as a master
(SP = 1), and are inputs when the 8259 is used as a slave
(SP = 0). As a master, the 8259 sends the 10 of the
interrupting slave device onto the CASO-2Iines. The slave
thus selected will send its preprogrammed subroutine
addressed onto the Data Bus during next two consecutive
INTA pulses. (See section "Cascading the 8259".)

Programming The 8259
The 8259 accepts two types of command words generated
by the CPU:
1. Initialization Command Words (ICWs):
Before normal operation can begin, each 8259 in the
system must be brought to a starting point - by a
sequence of 2 or 3 bytes timed by WR pulses. This
sequence is described in Figure 1.
2. Operation Command Words (OCWs):
These are the command words which command the
8259 to operate in various interrupt modes. These
modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259 at anytime after
initialization.

A.

D,

I '"
0

Os

05

As

As

I

0,

03

1

•

O2

0,

I Is I
F

Do
0

I

ICW1

ICW2

8259 BLOCK DIAGRAM

8259 DETAILED OPERATIONAL SUMMARY
General
The powerful features of the 8259 in a microcomputer
system are its programmability and its utilization of the
CALL instruction to jump into any address in the memory
map. The normal sequence of events that the 8259
interacts with the CPU is as follows:

ICW3

1. One or more of the INTERRUPT REQUEST lines (lR7Q) are raised high, setting the corresponding IRR bit(s).
2. The 8259 accepts these requests, resolves t'le
priorities, and sends an INT to the CPU.

6-269

FIGURE 1. INITIALIZATION SEQUENCE

rI

8259, 8259-5
AO-4 are automatically inserted by the 8259. while A15-6
are programmed by ICW1 and ICW2. When interval = 8. A5
is fixed by the 8259. If interval = 4. A5 is programmed in
ICW1. Thus. the interrupt service routines can be located
anywhere in the memory space. The 8 byte interval will
maintain compatibility with current 8080 RESTART
instruction software. while the 4 byte interval is best for
compact jump table.

Initialization Command Words 1 and 2: (ICWl and ICW2)
Whenever a command is issued with AO =0 and 04 =1. this
is interpreted as Initialization Command Word 1 (ICW1).
and initiates the initialization sequence. During this
sequence. the following occur automatically:
a. The edge sense circuit is reset. which means that
following initialization. an interrupt request (fR)
input must make a low to high transition to generate
an i nterru pI.
b. The interrupt Mask Register is cleared.
c. IR 7 input is assigned priority 7.
d. Special Mask Mode Flip-flop and status Read Flipflop are reset.

The address format inserted by the 8259 is described in
Table 1.
The bits F and S are defined by ICW1 as follows:
F: Call address interval. F = 1. then interval = 4;
then interval = 8.

The 8 requesting devices have 8 addresses equally spaced
in memory. The addresses can be programmed at
intervals of 40r 8 bytes; the 8 routines thus occupying a
page of 32 or 64 bytes respectively in memory.

S:
Single. S = 1 means that this is the only 8259 in the
system. It avoids the necesity of programming ICW3.

The address format is:
06

0,

05

I'---v----l- - A7

As

03

D.

A5

A.

A3

A,.

A'3

D.

A2

A,

A.

I

V

AUTOMATICALLY
INSERTED BY 8259

A'2

\

0,

)

J\

DEFINED BY D 5_7 OF leW1

A'5

O2

I I I
All

A,.

Ag

As

)

I

V
DEFINED BY

ICW2

I

INTERVAL = 4

INTERVAL = 8

LOWER MEMORY ROUTINE ADDRESS

IR

7

F = O.

07

06

05

04

03

02

01

00

07

06

05

04

03

02

01

00

A7

A6

A5

1

1

1

0

0

A7

A6

1

1

1

0

0

0

IR

6

A7

A6

A5

1

1

0

0

0

A7

A6

1

1

0

0

0

0

IR

5

A7

A6

A5

1

0

1

0

0

A7

A6

1

0

1

0

0

0

IR

4

A7

A6

A5

1

0

0

0

0

A7

A6

1

0

0

0

0

0
0
0

IR

3

A7

A6

A5

0

1

1

0

0

A7

A6

0

1

1

0

0

IR

2

A7

A6

A5

0

1

0

0

0

A7

A6

0

1

0

0

0

IR

1

A7

A6

A5

0

0

1

0

0

A7

A6

0

0

1

0

0

0

IR

0

A7

A6

A5

0

0

0

0

0

A7

A6

0

0

0

0

0

0

TABLE 1.

6-270

8259, 8259-5
Example of Interrupt Acknowledge Sequence

Initialization Command Word 3 (ICW3)

Assume the 8259 is programmed with F = 1 (CALL address
interval = 4), and IR5 is the interrupting level. The 3 byte
sequence released by the 8259timed by the INTA pulses is
as follows:

This will load the 8-bit slave register. The functions of this
register are as follows:

D7

D6

D5

D4

D3

D2

D1

a. If the 8259 is the master, a "1" is set for each slave in
the system. The master then will release byte 1 of the
CALL sequence and will enable the corresponding
slave to release bytes 2 and 3, through the cascade
lines.
b. If the 8259 is a slave, bits 2 - 0 identify the slave. The
slave compares its CASO-2 inputs (sent by the
master) with these bits. If they are equal, bytes 2 and
3 of the CALL sequence are released.

DO
CALL
CODE

1st INTA

2nd tNT A

A7

A6

A5

Jo-d INTA

A15

A14

A13

LOWER
ROUTINE
ADDRESS

A12

All

Ala

A9

AS

HIGHER
ROUTINE
ADDRESS

If bit S is set in ICW1, there is no need to program ICW3.

lew'

1'" SINGLE

0'" NOT SINGLE

CALL ADDRESS INTERVAL
1 = INTERVAL IS 4
0'" INTERVAL IS 8

A 7 _5 OF LOWER
ROUTINE ADDRESS

ICW2

UPPER ROUTINE
ADDReSS

ICW3 (MASTER DEVICE)

, =

lR INPUTHASASlAVE

0= IR INPUT DOES NOT HAVE

A SLAVE

ICW3 (SLAVE DEVICE)

~

~

~

~

~

~

I' I I I I I
0

0

0

0

0

x

x

x

x

X

I

I

I

I

~

~

~

lID, lID, lIDo

I
SLAVE 10111

o , 2 3 4 5 6 7
o , o , o , o ,
o 0 1 , 0 0
o 0 0 o , ,

I

,,
,,

DON'T
CARE

NOTE 1: SLAVE ID IS EQUAL TO THE CORRESPONDING MASTER IR INPUT,

INITIALIZATION COMMAND WORD FORMAT

6-271

r

8259, 8259-5
Operation Command Words (OCWs)
AFTER ROTATE

After the Initialization Command Words (ICWs) are
programmed into the 8259, the chip is ready to accept
interrupt requests at its input lines. However, during the
8259 operation, a selection of algorithms can command
the 8259 to operate in various modes through the
Operation Command Words (OCWs). These various
modes and their associated OCWs are described below.

"IS" STATUS

IS7

I° I

IS6

,

IS5

IS4

I ° I° I

IS3
0

LOWEST PRIORITY
PRIORITY STATUS

IS2

IS,

0

0

I

ISO

I°I

HIGHEST PRIORITY

I I I I, I I I I ~
4

3

2

0

7

6

Interrupt Masks
In this example, the In-Service FF corresponding to
line 4 (the highest priority FF set) was reset and line 4
became the lowest priority, while all the other priorities
rotated correspondingly.

Each Interrupt Request input can be masked individually
by the Interrupt Masked Register (IMR) programmed
through OCW1.
The IMR operates on the In-Service Register. Note that if
an interrupt is already acknowledged by the 8259 Ian INTA
pulse has occurred), then the Interrupting level, although
masked, will inhibit the lower priorities. To enable these
lower priority interrupts, one can do one of two things: (1)
Write an End of Interrupt (EOI) command IOCW2) to reset
the 1ST bit or (2) Set the special mask mode using OCW3
(as will be explained later in the special mask mode,)

The Rotate command is issued in OCW2, where:-R =
1, EOI = 1, SEal = O.
2. Specific Rotate - The programmer can change
priorities by programming the bottom priority, and by
doing this, to fix the highest priority: i.e., if IR5 is
programmed as the bottom priority device, the IR6 will
have the highest one. This command can be used with
or without resetting the selected ISR bit.

Fully Nested Mode
The 8259 will operate in the fully nested mode after the
execution of the initialization sequence without any OCW
being written. In this mode, the interrupt requests are
ordered in priorities from Othrough 7. When an interrupt is
acknowledged, the highest priority request is determined
and its address vector placed on the bus. In addition, a bit
of the Interrupt service register (IS 7-0) is set. This bit
remains set until the CPU issues an End of Interrupt lEal)
command immediately before returning from the service
routine. While the IS bit is set, all further interrupts of lower
priority are inhibited, while higher levels will be able to
generate an interrupt (which will only be acknowledged if
the CPU has enabled its own interrupt input through
software).

The Rotate command is issued in OCW2 where: R = 1,
SEal = 1. L2, L 1, LO are the BCD priority level codes of the
bottom priority device. If EOI = 1 also, the ISR bit selected
by L2-LO is reset.

After the Initialization sequence, IRO has the highest
priority and IR7 the lowest. Priorities can be changed, as
will be explained in the rotating priority mode.

There are two forms of EOI command: Specific and nonSpecific. When the 8259 is operated in modes which
preserve the fully nested structure, it can determine which
IS bit to reset on EOI. When a non-Specific EOI command
is issued the 8259 will automatically reset the highest IS
bit of those that are set, since in the nested mode, the
highest IS level was necessarily the last level acknowledged and will necessarily be the next routine level
returned from.

Observe that this mode is independent of the End of
Interrupt Command and priority changes can be
executed during EOI command or independently from
the EOI command.
End of Interrupt (EOI) and Specific End of
Interrupt (SEOI)
An End of Interrupt command word must be issued to the
8259 before returning from a service routine, to reset the
appropriate IS bit.

Rolating Priority Commands
There are two variations of rotating priority: auto rotate
and specific rotate.
1. Auto Rotate - Executing the Rotate-at-EOI (Auto)
command, resets the highest priority ISR bit and
assigns that input the lowest priority. Thus, a device
requesting an interrupt will have to wait, in the worst
case, until 7 other devices are serviced at most once
each, i.e., if the priority and "in-service" status is:
BEFORE ROTATE

151

"IS" STATUS [

IS6

155

154

° I' I° I
LOWEST PRIORITY

PRIORITY STATUS

1

1S3

IS2

IS'

ISO

I° I° I° I°I
HIGHEST PRIORITY

1..._7......J1'--6--'_5.....1.1_4-L1_3-L.1_2_...I_,......J'--0-l1

6-272

However, when a mode is used which may disturb the fully
nested structure, such as in the rotating priority case, the
8259 may no longer be able to determine the last level
acknowledged. In this case, a specific EOI (SEal) must be
issued which includes the IS level to be reset as part of the
command. The End of the Interrupt is issued whenever
EOI = "1" in OCW2. Forspecific EOI, SEal = "1", and EOI =
1. L2, L 1, LO is then the BCD level to be reset. As explained
in the Rotate Mode earlier, this can also be the bottom
priority code. Note that although the Rotate command can
be issued during an EOI = 1, it is not necessarily tied to it.

8259, 8259-5

OCW,

~

~

~

~

~

~

~

~

~

DCW2

I I I I I I I I I I
0

R

SEOI

EOI

0

L,

0

L,

LO

BCD LEVEL TO BE RESET
OR PUT INTO LOWEST PRIORITY

[

0

,

0

1

0

0

0

0

3

2

0

,

0

0

4

5

6

0

,

0

0

0

1

7

,
, ,
,
, , , ,

NON·SPECIFIC END OF INTERRUPT
1'" RESET THE HIGHEST PRIORITY

BIT OF ISR
0= NO ACTION

SPECIFIC END OF INTERRUPT
1'" l2, L" LO BITS ARE USED
0= NO ACTION

ROTATE PRIORITY
1 == ROTATE
0== NOT ROTATE

aCW3

I

0

I - IESMMI SMM I

0

I

1

I

p

IER'SI

RIS

I
READ IN-SERVICE REGISTER

DJN'
T
CARE

I

0
0

I
I

1
0

NO ACTION

0

,

,
,

READ
READ
IR REG
ISREG
ON NEXT ON NEXT
AD PULSE AD PULSE

POLLING
A HIGH ENABLES THE NEXT AD PULSE
TO READ THE BCD CODE OF THE HIGHEST LEVEL REQUESTING INTERRUPT.

SPECIAL MASK MODE

0
0

I ,
I
0

NO ACTION

OPERATION COMMAND WORD FORMAT

6-273

0

,
,

RESET
SPECIAL
MASK

SPECIAL

,

SET
MASK

8259, 8259-5
The word enabled onto the data bus during RD is:

Special Mask Mode (SMM)
This mode is useful when some bil(s) are set (masked) by
the Interrupt Mask Register (IMR) through OCW1. If, for
some reason, we are currently in an interrupt service
routine which is masked (this could happen when the
subroutine intentionally mask itself off), it is still possible
to enable the lower priority lines by setting the Special
Mask mode. In this mode the lower priority lines are
enabled until the SMM is reset. The higher priorities are
not affected.

D7

D6

D5

D4

D3

D2

D1

DO

I -I WO -

2: BCD code of the highest priority
requesting service.
I: Equal to a "1" if there is an interrupt.

level

This mode is useful if there is a routine common to
several levels - so that the INTA sequence is not
needed (and this saves ROM space). Another
application is to use the poll mode to expand the
number of priority levels to more than 64.

The special mask mode FF is set by OCW3 where ESMM =
1, SMM = 1, and reset where: ESSM = 1 and SMM = O.
Polled Mode
In this mode, the CPU must disable its interrupt input.
Service to device is achieved by programmer initiative by a
Poll command.
The poll command is issued by setting P = "1" in OCW3
during a WR pulse.
The 8259 treats the next RD pulse as an interrupt
acknowledge, sets the appropriate IS Flip-flop, if there is a
request, and reads the priority level.
For polling operation, an OCW3 must be written before
every read.

SUMMARY OF OPERATION COMMAND WORD PROGRAMMING
AO
OCWl

1

OCW2

0

04

03

0

0

R SEOI

0
0
0
0
1

OCW3

0

IMR (Interrupt Mask Register). WR will load it while status can be
read with RD.

M7-MO

0

1

EOI

0
0

0

1

0

1

1

0

1
1

0
0
1

1

1

1

ESMM

SMM

0
0
1

0

1

1

0

1

RIS

0
0

0
1
0
1

1

}

0
1

ERIS

1

No Action.
Non-specific End of Interrupt.
No Action.
Specific End of Interrupt. L2, L 1, LO is the BCD level to be reset.
No Action.
Rotate priority at EO!. (Auto Mode)
Rotate priority, L2, L 1, LO becomes bottom priority without
Ending of Interrupt.
Rotate priority at EO I (Specific Mode), L2, L1, LO becomes
bottom priority, and its corresponding IS FF is reset.

1

Special Mask not Affected.
Reset Special Mask.
Set Special Mask.

}

No Action.
Read IR Register Status.
Read IS Register Status.

Note: The CPU interrupt input must be disabled during:
1. Initialization sequence for all the 8259 in the system.
2. Any control command execution.

6-274

8259, 8259-5
Reading 8259 Status

Cascading

The input status of several internal registers can be read
to update the user information on the system. The
following registers can be read by issuing a suitable
oeW3 and reading with RD.

The 8259 can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
A typical system is shown in Figure 2. The master
controls, through the 3 line cascade bus, which one of the
slaves will release the corresponding address.

Interrupt Requests Register ORR): 8-bit register which
contains the levels requesting an interrupt to be
acknowledged. The highest request level is reset from the
IRR when an interrupt is acknowledged. (Not affected by
IMRl.

As shown in Figure 2, the slaves interrupt outputs are
connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged, the master will release the 8080 CALL code during
byte 1 of INTA and will enable the corresponding slave to
release the device routine address during bytes 2 and 30f
INTA.

In·Service Register (ISR): 8-bit register which contains
the priority levels that are being serviced. The ISR is
updated when an End of Interrupt command is issued.
Interrupt Mask Register: 8-bit register which contains the
interrupt request lines which are masked.

The cascade bus lines are normally low and will contain
the slave address code from the trailing edge of the first
INTA pulse to the trailing edge of the third pulse. It is
obvious that each 8259 in the system must follow a
separate initialization sequence and can be programmed
to work in a different mode. An EOI command must be
issued twice: once for the master and once for the
corresponding slave. An address decoder is required to
activate the Chip Select (CS) input of each 8259. The slave
program pin (SP) must be at a "low" level for a slave (and
then the cascade lines are inputs) and at a "high" level for
a master (and then the cascade lines are outpus).

The IRR can be read when prior to the RD pulse, an WR
pulse is issued with OeW3, and ERIS = 1, RIS = O.
The ISR can be read in a similar mode, when ERIS = 1, RIS
=

1.

There is no need to write an OCW3 before every status
read operation as long as the status read corresponds with
the previous one, i.e. the 8259 "remembers" whether the
I RR or ISR has been previously selected by the OCW3.
For reading the IMR, a WR pulse is not necessary to
preceed the RD. The output data bus will contain the IMR
whenever RD is active and AO = 1.
Polling overrides status read when P = 1, ERIS = 1 in
OCW3.

\

ADDRESS BUS (16)

\

CONTROL BUS

-.'l

INTREQ

\

\

DATA BUS (8)

--

---

--I- t - -

---- -

--

CASO

8259
SLAVE 2

CAS 1
CAS 2

§P

IR

IR

IR

IR

.R

.R 'R

'R

II I r r I r I I
21

-

-

r----

r---

7

20 19 18 17 16 15 14

I

INT

8259
SLAVE 1

"-

§P IR

G!O

IR

.R

IR

IR

.R

IR

8

6-275

cs

CASO

CASO

CAS 1

CAS 1

CAS2

CAS 2
§P

IR

11 J11 I 1I
INTERRUPT• REQUESTS

FIGURE 2. CASCADING THE 8259

7

I

cs Ao

INT

Ao

r--r--

--- - - I--

r--

7
cs

---

r

Vee

'NT

Ao

8259
MASTER

'R

'R

IR

IR .R

IR

IR

IR

1IIIIIr
0

I

,..
I

8259, 8259-5
8259 INSTRUCTION SET
INST.
NO.

AO

D7

D6

D5

D4

D3

D2

D1

DO

OPERATION DESCRIPTION

ICW1 A

0

A7

A6

A5

0

1

0

Byte 1 initialization, format = 4, single.

2

ICW1 B

a

A7

A6

A5

0

0

0

Byte 1 initialization, format = 4, not single.

3

ICW1 C

0

A7

A6

A5

0

0

1

a

Byte 1 initialization, format = 8, single.

4

ICWl D

0

A7

A6

A5

0

0

0

0

Byte 1 initialization, format = 8, not single.

5

ICW2

A15 A14 A13 A12 All

Ala A9

A8

Byte 2 initialization (Address No.2)

6

ICW3M

S7

S6

S5

S4

S3

S2

Sl

SO

Byte 3 initialization - master.

7

ICW3S

0

0

S2

Sl

SO

Byte 3 initialization - slave.

OCWl

1

M6

0
M5

0

8

0
M7

M4

M3

M2

M1

Ma

Load mask reg, read mask reg.

9

OCW2E

0

0

0

a

0

0

0

0

Non specific EO I.

10

OCW2SE

0

0

0

0

L2

Ll

LO

Specific EO I. L2, L 1, LO code of IS F F
to be reset.

11

OCW2RE

a

0

0

0

a

0

Rotate at EOI (Auto Mode).

12

OCW2 RSE

a

a

0

L2

Ll

LO

Rotate at EOI (Specific Mode). L2, L 1, LO,
code of line to be reset and selected as
bottom priority.

0

0

13

OCW2 RS

0

0

0

14

OCW3 P

a

0

0

0

L2

Ll

LO

L2, L1, LO code of bottom priority line.

1

a

a

Poll mode.

1

Read IS register.

15

OCW3 RIS

a

0

0

0

0

16

OCW3RR

0

0

a

0

a

1

0

Read requests register.

17

OCW3SM

0

1

a

0

0

0

Set special mask mode.

18

OCW3 RSM

0

0

a

0

0

0

Reset special mask mode.

Notes:
1. I n the master mode
2. 1-) = do not care.

SP pin = 1, in

slave mode

SP = o.

6-276

8259, 8259-5
I

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ........ DoC to 70°C
Storage Temperature ............ . -65° C to +150° C
Voltage On Any Pin
-0.5 Vto +7 V
With Respect to Ground
. . .. 1 Watt
Power Dissipation .. . . . . . . . . . . . .

D.C. CHARACTERISTICS

·COMMENT:
Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this
specification is not implied.

(TA = O°Cto 70°C; Vee

=

5V ±5%)

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

VIL

Input Low Voltage

-.5

.8

V

VIH

Input High Voltage

2.0

Vee+. 5V

V

VOL

Output Low Voltage

.45

V

VOH

Output High Voltage

VOH-INT

Interrupt Output High Voltage

IlL

IOL = 2 mA

2.4

V

IOH = -400 f.lA

2.4

V

IOH = -400 f.lA

3.5

V

Input Leakage Current
I I LURO.7)

TEST CONDITIONS

for IR()'7

IOH = -50 f.lA

-300

f.lA

VIN

10

f.lA

VIN = Vee

10

f.lA

VIN = Vee to OV

f.lA

VOUT = 0.45V to Vee

=

OV

Input Lea kage Current
for Other Inputs

IOFL

Output Float Lea kage

lee

Vee Supply Current

CAPACITANCE

±10
100

mA

TA = 25°C; Vee = GND = OV

SYMBOL

PARAMETER

MAX.

UNIT

CIN

I nput Capacitance

MIN.

10

pF

fc= 1 MHz

ClIO

I/O Capacitance

20

pF

Unmeasured pins returned to Vss

TYP.

6-277

TEST CONDITIONS

8259, 8259-5
A.C. CHARACTERISTICS

(TA

= o°c to 70°C; VCC = +5V ±5%, GND = OV)

BUS PARAMETERS
READ
8259
PARAMETER

SYMBOL

MIN.

8259·5
MAX.

MIN.

MAX.

UNIT
ns

tAR

CS/Ao Stable Before RD or INTA

50

50

tRA

CS/Ao Stable After RD or INTA

5

30

ns

lRR

RD Pulse Width

420

300

ns

tRO

Data Valid From RD/INTA[11

tOF

Data Float After RD/INTA

200

ns

100

ns

MAX.

UNIT

300
20

200

20

WRITE
8259·5

8259
SYMBOL

PARAMETER

MIN.

MAX.

MIN.

tAW

Ao Stable Before WR

50

50

ns

tWA

Ao Stable After WR

20

30

ns

tww

WR Pulse Width

400

300

ns

tDW

Data Valid to WR (T.E.)

300

250

ns

two

Data Valid After WR

40

30

ns

OTHER TIMINGS
8259
SYMBOL

Note 1:

PARAMETER

tlW

Width of Interrupt Request Pulse

tiNT

INT

tiC

Cascade Line Stable After INTA

t

MIN.
100

After IR t

t

8259·5
MAX.

MIN.
100

_'0'.28

350

ns

400

ns

TEST POINTS

0 . 4 5 - - -J

6-278

ns

400

INPUT WAVEFORMS FOR A.C. TESTS

•

UNIT

400

8259: CL = 100pF,8259-5: CL = 150pF.

2.4---..,.X >

MAX.

<::x__

8259, 8259-5
WAVEFORMS
READ TIMING

WRITE TIMING
CHll'SETECT

ADDRESS BUS

DATA BUS

-----------';~~--+---~,----

I/OWR

OTHER TIMING

IR
INT

-i2F
t,W

. ._________

y-~------------------\

INTA

DB

Note: Interrupt Request must remain "HIGH" (at least) until leading edge of first INTA.

6-279

8259, 8259-5

READ STATUS/POLL MODE

CS~,-_ _ _-,I

''-_ _ _....11

~..~_"""1+--ocw.J~ rzmzmzzzz)j ~.. wmvozzm,
I

6-280

inter
8271
PROGRAMMABLE FLOPPY DISK CONTROLLER

• Internal CRC Generation and Checking
Programmable Step Rate, Settle-Time,
• Head
Load Time, Head Unload Index

IBM 3740 Soft Sectored Format
• Compatible

•• Programmable Record Lengths

• Multi-Sector Capability
Maintain Dual Drives with Minimum Soft• ware
Overhead Expandable to 4 Drives
Automatic Read/Write Head Positioning
• and
Verification

Count

• Single +5Volt Supply
• 40 Pin Package

The 8271 Floppy Disk Controller (FOC) is an LSI Component designed to interface one to four floppy disk drives to an 8-bit
microcomputer system. Its powerful control functions minimize both hardware and software overhead normally
associated with floppy disk controllers.

BLOCK DIAGRAM

PIN CONFIGURATION

FAULT RESET/OPO
SELECT 0
4 MHz

elK

RESET

Vee
LOW CURRENT
LOAD HEAD

DIRECTION

READY1

SEEK/STEP

SELECT 1

WR ENBlE

DACK
DRO

INDEX
WR PROTECT

AD

READY 0

WR

TAKO

INT

COUNT/OPI

DBD

WR DATA

DBI

FAULT

DB2

UNSEPDATA

DB3

DATA WINDOW

DB'

PlO/SS

DB5

CS

DB.

PLOC

DB7

Al

GND

Ao

1-----

WRDATA

1>-----

AD DATA

SERIAL
INTERFACE
CONTROllER
- - - DATA WINDOW

DRO

~------,

L -_ _ _ _ _ _

PLO/SS

DACK - - - - - ,
INT

DRIVE
INTERFACE

CONTROllER

SElECT 0

RESET

SELECT 1

WR ENABLE
LOAD HEAD
SEEK/STEP

os - - - - - '

DIRECTION
LOW CURRENT

INTERNAL
DATA BUS

CPU INTERFACE

6-281

FAULT RESET/OPO

DISK INTERFACE

8271
8271 BASIC FUNCTIONAL DESCRIPTION

Pin Name

General

A,- A O

The FOC supports a soft sectored format that is IBM 3740
compatible. This component is a high level controller that
relieves the CPU (and user) of many of the control tasks
associated with implementing afloppy disk interface. The
FOC supports a variety of high level instructions which
allow the user to store and retrieve data on a floppy disk
without dealing with the low level details of the disk
operation.

DRQ

1/0

Vee

0

Description

The OMA request signal is used to
request a transfer of data between
the 8271 and memory.
The DMA ACK signal notifies the
8271 that a OMA cycle has been
granted.

Select 1Select 0

0

These lines are used to specify the
selected drive.

Fault Reset/
OPO

0

The fault reset line is used to reset
an error condition which is latched
by the drive, otherwise the pin is a
user specified optional output.

Write Enable

0

This signal enables the drive write
logic.

Seek/Step

0

This multi-function line is used during drive seeks.

Direction

0

The direction line specifies the seek
direction.

Load Head

0

The load head line causes the drive
to load the Read/Write head load
pad against the diskette,

Low Current

0

This line notifies the drive that track
43 or greater is selected.

Hardware Description
The 8271 is packaged in a 40 pin DIP. The following is a
functional description of each pin.

Description
These. two lines are used to select
the destination of source of data to
be accessed by the control logic.

OACK

In addition to the standard read/write commands a scan
command is supported. The scan command allows the
user program to specify a data pattern and instruct the
FOC to search for that pattern on a track. Any application
that is required to search the disk (such as point of sale
price lookup, disk directory search, etc.) for information
may use the scan command to reduce the CPU overhead.
Once the scan operation is initiated, no CPU intervention
is required.

Pin Name

I/O

+5V supply

Ready 1,
Ready 0

These two lines indicate that the
specified drive is ready.

Fault

This line is used by the drive to
specify a file unsafe condition.

GND

Ground

4MHz Clock

A 4MHz square wave clock

Reset

A high signal on the reset input will
force the 8271 to an idle state. The
8271 will remain idle until a command is issued by the CPU. The
drive interface output signals are
forced low.

Count/OPI

If the seek I direction I count seek
mode is selected, the count pin is
pulsed for each track. Otherwise this
pin is user specified optional input.

Write Protect

This signal is used to specify if the
driveldiskette may be written.

The 1/0 Read and 110 Write inputs
are enabled by the chip select signal.

TRKO

This signal indicates when the RIW
head is positioned over track zero.

The Data Bus lines are bidirectional three-state lines.

Index

The index signal gives an indication
of the relative position of the diskette.

PLO/SS

This pin is used to specify the type
of data separator used.

CS
DBrDBa

1/0

WR

The Write Signal is used to signal
the control logic that a transfer of
data from the data bus to the 8271
is required.

RO

INT

The Read signal is used to signal
the control logic that a transfer of
data from the 8271 to the data bus
is required.

0

The interrupt signal indicates that
the 8271 requires service.

6-282

Write Data

0

Composite write data.

Unseparated
Data

This input is the unseparated data
and clocks.

Data Window

This is a data window established
by the single-shot or phase-locked
oscillator data separator.

PLOC

0

This line is low when the 8271 is
searching for input data sync.

8271
Principles of Operation

The Result Phase

The 8271 is fully compatible with Intel microprocessors. It
accepts commands from the CPU, executes these
Commands and provides a Result at the end of execution.

During the Result Phase, the FDC chip notified the CPU of
the outcome of the command execution. This phase may be
initiated by:

Communication with the CPU are through the activating of
CS, RD, WR pins. The A"Ao select the appropriate registers
on chip:

1. The successful completion of an operation.
2. An error detected during an operation.
3. An illegal command or parameter detected during the
Command Phase.
In the Result Phase, tile CPU Reads the Status Register
which provides the following information:

A3

Aa

0
0

0
1

RD

CS

CS

Status Reg
Result Reg

WR

Command Reg
Parameter Reg
COMMAND BUSY
COMMAND A EG FULL
PARAMETER REG FULL

The FDC chip operation is composed of the following general sequence of events:

After reading the Status Register, the CPU then Reads the
Result Register for more information.

The Command Phase
During the Command Phase, the CPU issues a command
byte to the 8271. The command byte provides a general
description of the type of operation requested. Many
operations require more detailed information about the
comand. In such case, from zero to five parameters are
written following the command byte to provide such
information. The various commands that the 8271 can
recognize are listed in the Software Operation Section.

CPU WRITES THE COMMAND AND PARAMETERS INTO
THE 8271 COMMAND AND PARAMETER REGISTERS.

THE 8271 IS ON ITS OWN TO CARRY OUT THE COMMANDS.
THE 8271 SIGNALS THE CPU THAT THE EXECUTION HAS

FINISHED. THE CPU WILL PERFORM A READ OPERATION
OF ONE OR MORE OF THE REGISTERS.

The Execution Phase
Soon as the last parameter is written into the 8271, the FDC
enters the Execution Phase. During this phase there is no
need for CPU involvement. The FDC may optionally
interface with the 8257 (DMA controller) for high speed data
transfers (See System Diagram).

I
\

MEMORIES

U

I
I

SYSTEM BUS

.().

/\,.

060 _7

Ao. A,

MEMR
lOW
MEMW
lOR
CS
HRD

D6 0_7

RD
WR
CS
INT

'<-..),HACK

'\..7

DATA
WINDOW

I

DATA
SEPARATOR

ORO
8257
DMA
CONTROLLER

UNSEPARATED DATA
DACK

8271
FDC

A

I
I

DRIVE
INTERFACE

CONTROL IN

"

8271 SYSTEM DIAGRAM

6-283

LINE
7438
DRIVER

WR DATA

1/

CONTROL OUT

\(

8271
As an example, the SPECIFY command is associated with
4 parameters:

Software Operation
The 8271 can accept many powerful commands from the
CPU. The following is a list of Basic Commands (associated
Parameters not shown).

A,

SCAN DATA

SPECIFY

SCAN DATA AND DELETED DATA

Ao

r::-T:l

COMMAND

~

PARAMETER 0

~

07

06

05

04

OJ

02

01

Do

I· I • I ' I ' I ° I ' I ' [ , I
1.1.1°1°1,1,[°1,1
,

WRITE DATA
WRITE DATA AND DELETED DATA
READ DATA

PARAMETER'

!

~ =I==~:::;:=='===::J
'l:::'

- -_ _ STEP RATE (O·255m5IN

READ DATA AND DELETED DATA

STEPSOF lms)

READID

PARAMETER 2

VERIFY DATA AND DELETED DATA

~ : :1:::I====~==m=::j,
' - -_ _ _ STEP SETTLE TIME 0-255ms, IN

STEPSOF lms

FORMAT
SEEK
READ DRIVE STATUS
SPECIFY
RESET

EXECUTION PHASE BASIC CHARACTERISTICS
The following table summarizes the various commands
with corresponding execution phase characteristics.

2
COMMANDS

Deleted
Data

3

4

Head

Ready

Write!
Protect

5

6

7

8

Seek

Seek
Check

Result

Completion
Interrupt

SCAN DATA

SKIP

LOAD

j

x

YES

YES

YES

YES

SCAN DATA AND
DEL DATA
WRITE DATA

XFER

LOAD

j

x

YES

YES

YES

YES

x

LOAD

j

j

YES

YES

YES

YES

WRITE DEL DATA

XFER

LOAD

v

j

YES

YES

YES

YES

I

READ DATA

SKIP

LOAD

j

x

YES

YES

YES

YES

READ DATA AND
DEL DATA
READID

XFER

LOAD

j

x

YES

YES

YES

YES

x

LOAD

j

x

YES

NO

YES

YES

VERIFY DATA AND
DEL DATA
FORMAT

XFER

LOAD

j

x

YES

YES

YES

YES

x

LOAD

j

j

YES

NO

YES

YES

SEEK

x

x

x

YES

NO

YES

YES

READ DRIVE STAT
SPECIFY

x

x
x
x

x

NO

NO

YES

NO

x

NO

NO

NO

NO

x

NO

NO

NO

NO

RESET

x
x

UNLOAD

Note: 1. "x" ~ DON'T CARE
2. ",/" ~ check
3. "-" - No change

6-284

inter
8273
SOLC PROTOCOL CONTROLLER
Digital Phase Locked Loop-Clock
• Recovery
CPU Overhead
• Minimum
Single
+5Volt
• 40 Pin PackageSupply
•

IBM (SDLC) Compatible
• Full
Operation-56K BAUD
• SDLCDuplex
Loop
Operation
• User Programmable
Modem Control
• Ports
Programmable NRZI Encode/Decode
• N-Bit
Reception Capability
•

The 8273 SOLC (Synchronous Oata Link Control) Protocol controller is a single chip device designed to support the SOLC
protocol within a microcomputer system environment. Its internal supervisory instruction set is oriented to frame level
(SOLC) functions with a minimum of CPU overhead.

PIN CONFIGURATION

BLOCK DIAGRAM
REGISTERS
Tx

REG

COMMAND REG

Rx

FLAG DET

Vce

TxlNT

PB 4

o ClK

PB3

RESET

PB2

TxDACK

PB,

TxDRO

RTS

RxDACK

PA 4

RxDRO

PA 3

TEST MODE

TxD

RD

P~

WR

CD

RxlNT

CTS

DBO

TxD

DB1

TxC

DB2

RxC

DB3

RxD

DB4

32xC

DB5

CS

DB6

DPll

TxC

32X elK

RTs
PBo-J

DPlL

.--~:....-.......- -

RxD
RxC

DB7

A,

GND

Ao
MODEM INTERFACE

CPU INTERFACE

6-285

8273
General

Pin Name

The IBM Synchronous Data Link Control (SDlC) communi·
cation protocol is a bit oriented communication protocol vs
the BI·SYNC protocol which is character or code oriented.
The SDlC protocol greatly reduces the overall CPU software
on one hand and increases the throughput on the other
because of its ability to go full·duplexed mode.

TxDRQ

0

The Transmitter DMA Request signal
indicates the transmitter Buffer is empty
and is ready to transmit another data
byte.

RxRDQ

0

The Receiver DMA Request Signal in·
dicates the Receiver Buffer is full.

The 8273 SDlC chip is designed to handle the IBM SDlC
protocol with minimum CPU software. The 8273 handles the
zero·insertion technique used in SDlC protocol, as well as
performing NRZI encoding and decoding for the data.
Modem handshake signals are provided so that the CPU
intervention is minimized. The FCS (Frame check sequence)
is also generated and checked by the SDlC chip as well as
Flags (01111110) and Idle characters.
One implementation of SDlC is the loop·configuration
typified by IBM 3650 Retail Store System which can also be
handled by the 8273 by going into 1·bit delay mode. In such
configuration a two wire pair can be effectively used for data
transfer between controllers and loop stations. Digital phase
locked loop pin·out can be used by the loop station without
the presence of an accurate 1X clock.

1/0

TxDACK

The Transmitter DMA acknowledge sig·
nal notifies the 8273 that the TxDMA
cycle has been granted.

RxDACK

The Receiver DMA acknowledge signal
notifies the 8273 that the RxDMA cycle
has been granted.

A,·A o

These two lines are used to select the
destination or source of data to be
accessed by the control logic.

TxD

0

Pin Name

1/0

The transmitter clock controls the TxD
BAUD rate.

RxD

The Receiver Data line receives the
NRZI encoded data from the communi·
cation data channel.

RxC

The Receiver clock is the 1X BAUD
rate that RxD is received.

32X ClK

The 32X clock is used to provide clock
recovery when Asynchronous modem
is used. In loop configuration the loop
station can run without an accurate 1 X
clock by using the 32X ClK.

Description

Vee

+5V supply

GND

Ground

RESET

A high signal on this pin will force the
8273 to an idle state. The 8273 will
remain idle until a command is issued
by the CPU. The modem interface
output signals are forced high.

CS
DBrDBa

1/0

The NRZI encoded data are transmitted
through the TxD line.

TxC

Hardware Description
The 8273 is packaged in a 40 pin DIP. The following is a
functional description of each pin.

Description

DPll

0

The 1/0 Read and 1/0 Write inputs are
enabled by the chip.

Digital Phase locked loop output can
be tied to RxC andlor TxC when 1X
clock is not available. DPll is used
with 32X ClK.

FLAG DET

0

The Data Bus lines are bidirectional
three·state lines.

Flag Detect signals that a flag (01111110)
has been detected.

RTS

0

Request to send signals the terminal is
ready to transmit Data.

WR

The Write Signal is used to control the
transfer of either a command or data
from CPU to the 8273.

RD

The Read signal is used to control the
transfer of either a data byte or a status
word from the 8273 to the CPU.

TxlNT

0

The Transmitter interrupt signal indi·
cates that the transmitter logic requires
service.

RxlNT

0

The Receiver interrupt signal indicates
that the Receiver logic requires service.

CTS

Clear to send signals that the modem is
ready to accept data for transmission.

CD

Carrier Detect signals that the line trans·
mission has started and the 8273 may
begin sample data on RxD line.

PAI).2

General Purpose input Ports. The logic
levels on these lines can be Read by the
CPU through the Data Bus Buffer.

PBI).3

 ClK

0

General Purpose output Ports. The CPU
can write these output lines through
Data Bus Buffer.
A 4 MHz Square Wave Clock.

8273
Principles of Operation
The 8273 is fully compatible with Intel microprocessors. It
accepts commands from the CPU, executes these
Commands and provides a Result at the end of execution.
Communication with CPU is through the activating of CS,
RD, WR pins. The A1Ao select the appropriate registers on
chip:
A1

Ao

CSoRD

CSoWR

0
0

0

Command Reg
Parameter Reg

1
1

0

Status Reg
Result Reg
TX Reg
RX Reg

1
1

In the Result Phase, the CPU Reads the Status Register
which provides the following information.

I I I I I I I I I

I~

RX INTERRUPT RESULT AVAILABLE
TX INTERRUPT RESULT AVAILABLE
RX INTERRUPT
TX INTERRUPT
COMMAND RESULT BUFFER FULL

-

COMMAND PARAMETER BUFFER FULL
COMMAND BUFFER FULL
COMMAND BUSY

The SDLC chip operation is composed of the following
general sequence of events:
The Command Phase
During the Command Phase, the CPU issues a command
byte to the 8273. The command byte provides a general
description of the type of operation requested. Many operations require more detailed information about the command.
In such case, from zero to four parameters are written
following the command byte to provide such information. The
various commands that the 8273 can recognize are listed in
the Software Operation Section.
The Execution Phase

After the last parameter is written into the 8273, the SDLC
chip enters the Execution Phase. During this phase there is
no need for CPU involvement. The system might interface
with the 8257 (DMA controller) if programmed to do so, for
high speed data transfers (see System Diagram). On the
other hand for low speed data rate communication TxlNT
and RxlNT can be used.
The Result Phase

During the Result Phase, the SDLC chip notifies the CPU of
the outcome of the command execution. This phase may be
initiated by:
1. The successful completion of an operation.
2. An error detected during an operation.

Based on the status of the Status Register, the CPU may
Read the Tx Reg, Rx Reg, or Result Register, if more
information is needed.
Software Operation
The 8273 can accept many powerful commands from the
CPU. The following is a list of such commands (associated
parameters not shown).
General Receive
Selective Receive
Selective Loop Receive
End of Polling Search
Receive Disable
Transmit Frame
Loop Transmit
Transparent Transmit
Abort Tx Frame
Abort Loop Tx
Abort Transparent Tx
Read Port A
Read Port B
Set/Reset 1 Bit Delay
Set/Reset Serial I/O
Set/Reset Operating Mode
Set/Reset Port AlB Bit

CPU WRITES COMMAND AND PARAMETERS INTO THE
8273 COMMAND AND PARAMETER REGISTERS.

THE 8273 IS ON ITS OWN TO CARRY OUT THE COMMAND.
THE 8273 SIGNALS THE CPU THAT THE EXECUTION
HAS FINISHED. THE CPU WILL PERFORM A READ
OPERATION OF ONE OR MORE OF THE REGISTERS.

6-287

8273

I
'1

MEMORIES

J

I

SYSTEM BUS
D80_7

"

..

"'A O' A,

MEMR
lOW
MEMW
lOR
CS
HRO
;.-HACK

OB0-7

RD
WR
CS
TXINT
RXINT

"

7
RXC
RXD
TXC
TXD

DRO
8257
DMA
CONTROLLER

~

L

~

OACK

8273
SDLC

MODEM

MODEM CONTROLS

A

~

'I

8273 SYSTEM DIAGRAM
SYNCHRONOUS MODEM - DUPLEX OR HALF DUPLEX OPERATION
8273

8273

RXC
RXDi----I
TXCI----I
TXDt-----I

RXC
1----+lRXD
MODEM 1----+1 TXC
I----ITXD
32X PLL

32X PLL
TXC
GND N.C.

LOOP
CONTROLLER
(8273)

N.C.
ASYNCHRONOUS MODEMS - DUPLEX OPERATION

TXD
MODEM

t------1-t

ASYNCHRONOUS MODEMS - HALF DUPLEX OPERATION

RXD RXC
LOOP
TERMINAL
(8273)

TXC TXD
LOOP
TERMINAL
(8273)

TXD

RXD

TXC

RXC

I-+--~

MODEM
32X PLL

ASYNCHRONOUS OPERATION - NO MODEMS - DUPLEX OR HALF DUPLEX
PLL

32X
TXC
TXD
RXC
RXD

~

~

~

r-+ TXC

32X PLL

f L.
SDLC LOOP APPLICATION

8273 MODEM OPERATION

6-288

Rxe
TXD
TXD
32X PLL

t I
I

8275
PROGRAMMABLE CRT CONTROLLER
• Programmable Screen and Character
Formats

• Light Pen Detection and Registers
• Dual Row Buffers

• Six Indepependent Visual Field
Attributes

• Programmable DMA Burst Mode

• Eleven Visual Character Attributes
(Graphic Capability)

• Single +5 Volt Supply

• Cursor Control (4 Types)

• 40 Pin

Pac~age

The 8275 Programmable CRT Controller is a single chip device to interface CRT F!aster Scan Displays with Intel® Microcomputer Systems. Its primary function is to refresh the display by buffering the information from main memory and
keeping track of the display position of the screen. The flexibility designed into the 8275 will allow simple interface to
almost any Raster Scan CRT Display with a minimum of external hardware and software overhead.

BLOCK DIAGRAM

PIN CONFIGURATION

CHARACTER
COUNTER
LC3

VCC

LC2

LAo

LC1

LAl

LCO

LTEN

DRO

RVV

DACK

VSP

HRTC

GPAl

VRTC

GPAo

R5

HLGT

WR

IRO

LPEN

CCLK

DBO_7

DATA
BUS
BUFFER

CCO_6

CCLK

DBa

CCs

DBl

CC5

DB2

CC4

DB3

CC3

OACK

DB4

CC2

IRa

ORO

DB5

CCl

DBS

CCo

DB7

CS

Rfi

GND

Ao

WR

LINE
COUNTER

LCO_3

LAO_l

AO-

RASTER TIMING
AND
VIDEO CONTROL

HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO_l

cs
LPEN

6-289

8275
General

Pin Name

The CRT Controller (8275) is a single chip, programmable,
NMOS-LSI device which is designed to provide an interface
for microcomputers to a large class of CRT character
displays. The chip provides the display row buffering, raster
timing, cursor timing, light pen detection and visual attribute
decoding. It is programmable to a large number of different
display formats. The controller can be interfaced to standard
character generator ROMs for dot matrix decoding.

1/0

VRTC

o

Vertical retrace. Output signal which is
active during the programmed vertical
retrace interval. During this period the
VSP output is high and the LTEN output
is low.

LCo-LC3

o

Line count. Output from the line counter
which is uaed to address the character
generator for the line positions on the
screen.

CCo-CCa

o

Character codes. Output from the row
buffers used for character selection in
the character generator.

GPAO,
GPA1

o

General purpose attribute codes. Outputs which are enabled by the general
purpose field attribute codes.

LAO, LA1

o

Line attribute codes. These attribute
codes have to be decoded externally
by the dot/timing logic to generate the
horizontal and vertical line combinations for the graphic displays specified
by the character attribute codes.

HLGT

o

Highlight. Output signal used to intenSify
the display at particular positions on
the screen as specified by the character
attribute codes or field attribute codes.

RVV

o

Reverse video. Output signal used to
indicate the CRT circuitry to reverse
the video signal. This output is active at
the cursor position if a reverse video
block cursor is programmed or at the
positions specified by the field attribute
codes.

LTEN

o

Light enable. Output signal used to
enable the video signal to the CRT.
This output is active at the programmed
underline cursor pOSition, and at
positions specified by the character
attribute codes during generation of
graphics display.

VSP

o

Video suppression. Output signal used
to blank the video signal to the CRT.
This output is active:
- during the horizontal and vertical
retrace intervals.
- at the top and bottom lines of rows if
the number of lineslrow are greater
than or equal to 9.
- when an end of row or end of
screen code is detected.
- when a DMA underrun occurs.
- at regular intervals (1/16 frame
frequency for cursor, 1132 frame
frequency for character and field
attributes)-to create blinking displays as specified by cursor, character attribute, or field attribute
programming.

The controller can generate a screen format size of from 1 to
80 characters per row, 1 to 64 rows per screen and from 1 to
16 horizontal lines per character row.
The device has 7 character code address bits allowing 6 or 7
bit ASCII capability or can be used with other 7 bit codes to
generate up to 128 characters.

Hardware Description
The 8275 is Packaged in a 40 pin DIP. The following is a
functional description of each pin.
Pin Name

1/0

Vee
CCLK
DB7-DBo.

Description
+5V power supply

GND

Ground
I

Character Clock (from dot/timing logic)

1/0

Bi-directional three-state data bus lines.
The outputs are enabled during a read
of the C or P ports.
Chip select. The read and write are
enabled by CS.
Read input. A control signal to read
registers.
Write input. A control signal to write
commands into the control registers or
write data into the row buffers during a
DMA cycle.
Port Address. A high input on Ao
selects the "c" port or command
registers and a low input selects the
"P" port or parameter registers.

Ao

INT

0

Interrupt request.

DRO

0

DMA request. Output signal to the 8257
DMA controller requesting a DMA cycle.
DMA acknowledge. Input signal from
the 8257 DMA controller acknowledging
that the requested DMA cycle has been
granted.
.

LPEN

HRTC

Light pen. Input Signal from the CRT
system signifying that a light pen signal
has been detected.

o

Description

Horizontal retrace. Output signal which
is active during the programmed horizontal retrace interval. During this period
the VSP output is high and the LTEN
output is low.

6-290

8275
Principles of Operation

Field Attributes

The basic elements of the CRT controller are the two row
buffers (80X8), cursor position, light pen position, and visual
attribute decode and control logic. The CRT controller is
used with the DMA chip (8257) to provide the high speed
controlling function of a CRT.

The field attributes are control codes which will affect the
visual characteristics for a field of characters starting at the
character following the field attribute code up to the character
which precedes the next field attribute code. A field attribute
code does not have to occupy a display position. Any of the
following field display can be independently selected for
a field:

Two row buffers are utilized to provide display row refresh.
Each buffer is alternately loaded from main memory and
then used to provide characters to the external character
generator and internal visual attribute decode logic during
row display. Each buffer is loaded from main memory by
DMA cycles which are requested by the CRT controller at
programmable intervals. The controller can also be programmed to request a single DMA at a time or bursts of 2, 4,
or 8 bytes.
Raster Control and Timing

The raster logic provides the proper video scan timing for the
CRT. The various parameters of the raster timing are
programmable at controller reset. Raster timing is derived
from the basic character interval clock which is provided to
the controller from the external dot timing logic. The following
count functions are performed by the raster logic:
Character Count
Horizontal Retrace Interval Count
Line Count
Row Count
Vertical Retrace Interval Count

Blink
Highlight
Reverse Video
Underline
Character Attributes
A character attribute generates a graphics symbol in the
character position without the use of an external character
generator. A chara€ter attribute is generated through the
Line Attribute outputs together with the Video Suppress and
Light Enable outputs. The external logic then can generate
the proper symbol. Character attributes can be programmed
to blink or be highlighted.
Software Operation

The 8275 can accept commands from the CPU at any time to
perform the CRT controlling functions. A command
(Ao=1) from the CPU to the 8275 chip may be followed by
up to 4 bytes of parameters (Ao=Ol. The list of commands
and their associated parameters are summarized below:

Blink Timing
Cursor

CIP

The cursor location is determined by the cursor line and
character position registers which are loaded by command to
the controller. The cursor can be programmed to appear on
the display as 1) a blinking underline, 2) a blinking reverse
video blOCk, 3) a non-blinking underline, or 4) a non-blinking
reverse video block.

Visual Attributes

Visual attributes are generated and timed by the CRT
controller without the intervention of the external character
generator. They are actuated and controlled by special code
combinations. These attribute codes can affect the display
for just the character position in which they appear (character
type) or they may affect a field of characters (field type).

6-291

RESET & STOP DISPLAY

0
0
0

SHHHHHHH

SCREEN COMPOSITION #1

VVRRRRRR

SCREEN COMPOSITION #2

UUUULLLL

SCREEN COMPOSITION #3

0

DFCCZZZZ

SCREEN COMPOSITION #4

00lSSSBB

START DISPLAY

010XXXXX

STOP DISPLAY

011XXXXX

READ LIGHT PEN (*2

100XXXXX

LOAD CURSOR POSITION

0

XCCCCCCC

CURSOR X·POSITION

0

XXCCCCCC

CURSOR Y·POSITION

Light Pen

When the controller detects a light pen signal, the row and
character position coordinates of the raster are stored in a
pair of registers. On command to the controller, these
registers can be read by the microprocessor. The registers
are loaded on the 0-1 transition of the light pen input which is
internally synchronized with the character clock. The horizontal address will be off three character positions (more if
external delays are present) and has to be corrected in the
software. In addition, the controller has a status flag to
indicate that the light pen signal was detected.

DB
OOOXXXXX

101XXXXX

ENABLE INTERRUPT

110XXXXX

DISABLE INTERRUPT

RD)

8275

I
~

MEMORIES

J

(

SYSTEM BUS

•

•

'" DBO_7
MEMR

lOW

'"

DS0-7

lOR

WR
Ri5
CS

CS

,

7

AO

MEMW
HRO
HACK

IRO

"

CHARACTER
GENERATOR

lCO-J

128x7x9

ORO

8257
DMA
CONTROLLER

DACK

8275
CRT

~

~

CCO-6

CHAR. CLK

CONTROLLER

"
VIDEO CONTROLS

8275 SYSTEM DIAGRAM

6-292

f - - VIDEO SIGNAL
HIGH
SPEED
DOT
TIMING
AND
INTERFACE

I----HORIZONTAL SY NC
I----VERTICAL SYNC
f--INTENSITY

inter
8279, 8279-5
PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE
Dual 8 or 16 Numerical Display
• Single
16 Character Display
•
Right or Left Entry 16 Byte
• Display
RAM
Mode Programmable from CPU
• Programmable
Timing
• Interrupt 9utputScan
on
Key
Entry
•

• MCS,,85™ Compatible 8279-5
Keyboard Display
• Simultaneous
Operations
• Scanned Keyboard Mode
Sensor Mode
• Scanned
Strobed
Input
Entry Mode
• 8 Character Keyboard
• 2 Key Lockout or N KeyFIFO
• with· Contact Debounce Rollover

The 8279 is a general purpose programmable keyboard and display I/O interface device designed for use with Intel@
microprocessors. The keyboard portion can provide a scanned interfaceto a 64 contact key matrix which can be expanded
to 128. The keyboard portion will also interface to an array of sensors or a strobed interface keyboard. such as the Hall
effect and Ferrite variety. Key depressions can be 2 key lockout or N key rollover. Keyboard entries are debounced and
strobed in an 8 character FIFO. If more than 8 characters are entered. over run status is set. Key entries set the interrupt
output line to the CPU.
The display portion provides a scanned display interface for LED. incandescent and other popular display technologies.
Both numeric and alphanumeric segment displays may be used as well as simple indicators. The 8279 has a 16 x 8 display
RAM which can be organized into a dual 16 x 4. The RAM can be loaded or interrogated by the CPU. Both right entry.
calculator and left entry typewriter display formats are possi ble. Both read and write of the display RAM can be done with
auto-increment of the display RAM address.

PIN CONFIGURATION

LOGIC SYMBOL

Vee

PIN NAMES

RL,

----lIRa

RLo
CNTL/STB

SHIFT

SL3
RL.
RL,
RESET

SL2
SL,
9

SLo

M
DBo

NAME

080_7
elK
RESET

lOT
liIi

OUTB,
DUTB2

SHIFT

OUT 83

DB2

OUT Au

DB3

OUT At

DB.

OUT A2

DB.

OUT A3

DB.
DB,

CS

CNTllSTB
OUTAo-a
OUTBD-3

I""

FUNCTION
DATA BUS (SI-DIRECTIONAL)
CLOCK INPuT-

SHIFTI-\

RESET INPUT

----1M

CHIP SELECT
I
I

A,
IRa

Sl.,
RLo-7

DB,

I/O
I/O
I

READ INPUT
WRITE INPUT

----+lWii

BUFFER ADDRESS

CNTL/STB

INTERRUPT REQUEST OUTPUT

a

"'.~U

1----

CPU

SCAN LINES

INTERFACE

RETURN LINES

-----Ics

SHIFT INPUT

CONTROL/STROBE INPUT

I
a
0

DISPLAY (A) OUTPUTS

0

BLANK DISPLAY OUTPUT

DISPLAY {B} OUTPUTS

SL..

SCAN

-----ICID
OUTA0-3

- - - - - I RESET

BD

L - - - - " I CLK

Vss

Vss

6-293

OUT B. .

r-----,/

DISPLAY
DATA

8279, 8279-5
8279 BASIC FUNCTIONAL DESCRIPTION
Introduction
Since data input and display are an integral part of many
microprocessor designs, the system designer needs an
interface that can control these functions without placing
a large load on the CPU. The 8279 provides this function
for 8-bit microprocessors.

• Scanned Sensor Matrix - with encoded (8 x 8 matrix
switches) or decoded (4 x 8 matrix switches) scan lines.
Key status (open or closed) stored in RAM addressable
by CPU.
• Strobed Input - Data on return lines during control
line strobe is transferred to FIFO.

The 8279 has two sections: keyboard and display. The
keyboard section can interface to regular typewriter style
keyboards or random toggle or thumb switches. The
display section drives alphanumeric displays or a bank of
indicator lights. Thus the CPU is relieved from scanning
the keyboard or refreshing the display.

Output Modes
• 8 or 16 character multiplexed displays that can be
organized as dual 4-bit or single 8-bit.
• Right entry or left entry display formats.

The 8279 is designed to directly connect to the
microprocessor bus. The CPU can program all operating
modes for the 8279. These modes include:

• Mode programming from the CPU.

Input Modes

• Programmable clock to match the 8279 scan times to
the CPU cycle time .

Other features of the 8279 include:

• Scanned Keyboard - with encoded (8 x 8 x 4 key
keyboard) or decoded (4 x 8 x 4 key keyboard) scan
lines. A key depression generates a 6-bit encoding of
key position. Position and shift and control status are
stored in the FIFO. Keys are automatically debounced
with 2-key lockout or N-key rollover.

eLK

• Interrupt output to signal CPU when there is keyboard
or sensor data available.
• An 8 byte FIFO to store keyboard information.
• 16 byte internal Display RAM for display refresh. This
RAM can also be read by the CPU.

RESET

IRQ

DBO-7

KEYBOARD

DEBOUNCE
AND
CONTROL

TIMING

AND
CONTROL

OUT A()'3

OUT B0-3

Slo-3

FIGURE 1. 8279 BLOCK DIAGRAM

6·294

RlO.7

CNTl/STB

8279, 8279-5
Hardware Description
The 8279 is packaged in a 40 pin DIP. The following is
a functional description of each pin.
No. Of
Pins

8

Designation

Function

DBo-DB7

Bi-directional data bus. All data
and commands between the
CPU and the 8279 are transmitted on these lines.

ClK

Clock from system used to generate internal timing.

RESET

A high Signal on this pin resets
the 8279.

No, Of
Pins

Designation

Keyboard modes. It has an
active internal pullup to keep it
high until a switch closure pulls
it low,
CNTLlSTB

Chip Select. A low on this pin
enables the interface functions
to receive or transmit.
Ao

2

2

Buffer Address. A high on this
line indicates the signals in or
out are interpreted as a command or status. A low indicates
that they are data.

RD, WR

Input/Output read and write.
These signals enable the data
buffers to either send data to
the external bus or receive it
from the external bus.

IRQ

Interrupt Request. In a keyboard
mode, the interrupt line is high
when there is data in the FIFO/
Sensor RAM. The interrupt line
goes low with each FIFO/
Sensor RAM read and returns
high if there is still information in the RAM. In a sensor
mode, the interrupt line goes
high whenever a change in a
sensor is detected.

Vss , Vee

4
4

For keyboard modes this line is
used as a control input and
stored like status on a key closure. The line is also the strobe
line that enters the data into the
FIFO in the Strobed Input mode.
(Rising Edge). It has an active
internal pull up to keep it high
until a switch closure pulls it
low.

OUT Ao-OUT A3 These two ports are the outputs
OUT Bo-OUT B3 for the 16 x 4 display refresh
registers. The data from these
outputs is synchronized to the
scan lines (Slo-Sl3) for multiplexed digit displays. The two 4
bit ports may be blanked independently. These two ports may
also be considered as one 8 bit
port.
BD

Blank Display. This output is
used to blank the display during
digit switching or by a display
blanking command.

Principles of Operation
The following is a description of the major elements of the
8279 Programmable Keyboard/Display interface device.
Refer to the block diagram in Figure 1.

Ground and power supply pins.
1/0 Control and Data Buffers

4

Slo-Sl3

Scan Lines which are used to
scan the key switch or sensor
matrix and the display digits.
These lines can be either encoded (1 of 16) or decoded (1 of
4).

8

Rlo-Rl7

Return line inputs which are
connected to the scan lines
through the keys or sensor
switches. They have active internal pull ups to keep them
high until a switch closure pulls
one low. They also serve as an
8-bit input in the Strobed Input
mode.

SHIFT

Function

The shift input status is stored
along with the key position on
key closure in the Scanned

The I/O control section uses the CS, Ao, RD and WR lines
to control data flow to and from the various internal
registers and buffers. All data flow to and from the 8279 is
enabled by CS. The character of the information, given or
desired by the CPU, is identified by Ao. A logic one
means the information is a command or status. A logic
zero means the information is data. RD and WR determine
the direction of data flow through the Data Buffers. The
Data Buffers are bi-directional buffers that connect the
internal bus to the external bus. When the chip is not
selected (CS = 1), the devices are in a high impedance
state. The drivers input during WR- CS and output during
RD. CS.
Control and Timing Registers and Timing Control
These registers store the keyboard and display modes and
other operating conditions programmed by the CPU. The
modes are programmed by presenting the proper
command on the data lines with Ao = 1 and then sending
a WR. The command is latched on the rising edge of WR.

6-295

8279, 8279-5
The command is then decoded and the .appropriate
function is set. The timing control contains the basic
timing counter chain. The first counter is a + N prescaler
that can be programmed to match the CPU cycle time to
the internal timing. The prescaler is software programmed
to a value between 2 and 31. A value which yields an
internal frequency of 100 kHz gives a 5.1 ms keyboard
scan time and a 10.3 ms debounce time. The other
counters divide down the basic internal frequency to
provide the proper key scan, row scan, keyboard matrix
scan, and display scan times.

Software Operation

Scan Counter

Code:

The scan counter has two modes. In the encoded mode,
the counter provides a binary count that must be
externally decoded to provide the scan lines for the
keyboard and display. In the decoded mode, the scan
counter decodes the least significant 2 bits and provides a
decoded 1 of 4 scan. Note than when the keyboard is in
decoded scan, so is the display. This means that only the
first 4 characters in the Display RAM are displayed.
In the encoded mode, the scan lines are active high
outputs. In the decoded mode, the scan lines are active
low outputs.
Return Buffers and Keyboard Debounce and Control
The 8 return lines are buffered and latched by the Return
Buffers. In the keyboard mode, these lines are scanned,
looking for key closures in that row. If the debounce
circuit detects a closed switch, it waits about 10 msec to
check if the switch remains closed. If it does, the address
of the switch in the matrix plus the status of SHIFT and
CONTROL are transferred to the FIFO. In the scanned
Sensor Matrix modes, the contents of the return lines is
directly transferred to the corresponding row of the
Sensor RAM (FIFO) each key scan time. In Strobed Input
mode, the contents of the return lines are transferred to
the FIFO on the rising edge of the CNTLlSTB line pulse.

8279 Commands
The following commands program the 8279 operating
modes. The commands are sent on the Data Bus with CS
low and Ao high and are loaded to the 8279 on the rising
edge of WR.
Keyboard/Display Mode Set
MSB

Where DD is the Display Mode and KKK is the Keyboard
Mode.
DD

o
o

0

8 8-bit character display -

1

16 8-bit character display -

o

8 8-bit character display 16 8-bit character display -

Left entry
Left entry'
Right entry
Right entry

For description of right and left entry, see Interface
Considerations. Note that when decoded scan is set in
keyboard mode, the display is reduced to 4 characters
independent of display mode set.
KKK

0 0 0

Encoded Scan Keyboard - 2 Key Lockout

0 0

1

Decoded Scan Keyboard - 2-Key Lockout

0

0

Encoded Scan Keyboard -

N-Key Rollover

0

1

Decoded Scan Keyboard -

N-Key Rollover

0 0
0

FIFO/Sensor RAM and Status
This block is a dual function 8 x 8 RAM. In Keyboard or
Strobed Input modes, it is a FIFO. Each new entry is
written into successive RAM positions and each is then
read in order of entry. FIFO status keeps track of the
number of characters in the FIFO and whether it is full or
empty. Too many reads or writes will be recognized as an
error. The status can be read by an RD with CS low and
Ao high. The status logic also provides an IRQ signal
when the FIFO is not empty. In Scanned Sensor Matrix
mode, the memory is a Sensor RAM. Each row of the
Sensor RAM is loaded with the status of the corresponding row of sensor in the sensor matrix. In this mode, IRQ is
high if a change in a sensor is detected.

LSB

lolololDJDJKJKJKI

Encoded Scan Sensor Matrix

1

Decoded Scan Sensor Matrix

0

Strobed Input, Encoded Display Scan
Strobed Input, Decoded Display Scan

Program Clock
Code:
Where PPPPP is the prescaler value 2 to 31. The
programmable prescaler divides the external clock by
PPPPP to get the basic internal frequency. Choosing a
divisor that yields 100 KHz will give the specified scan and
debounce times. Default after a reset pulse (but not a
program clear) is 31.

·Dlsplay Address Registers and Display RAM
The Display Address Registers hold the address of the
word currently being written or read by the CPU and the
two 4-bit nibbles being displayed. The read/write
addresses are programmed by CPU command. They also
can be set to auto increment after each read or write. The
Display RAM can be directly read by the CPU after the
correct mode and address is set. The addresses for the A
and B nibbles are automatically updated by the 8279 to
match data entry by the CPU. The A and B nibbles can be
entered independently or as one word, according to the
mode that is set by the CPU. Data entry to the display can
be set to either left or right entry. See Interface
Considerations for details.

6-296

Read FIFO/Sensor RAM
Code:

I 0 11 10 1AI 1 X 1 A 1 A 1 A 1 X = Don't Care

Where AI is the Auto-Increment flag for the Sensor RAM
and AAA is the row that is going to be read by the CPU. AI
and AAA are used only if the mode is set to Sensor Matrix.
This command is used to specify that the source of data
reads (CS • RD • AO) by the CPU is the FIFO/Sensor
RAM. No additional commands are necessary as long as
'Default after reset.

8219, 8219-5
;- t~
~ '':'; t

data is desired from the FIFO/Sensor RAM. Another
command is necessary if reading is desired from a
different row than has been selected. If AI is a one, the row
select counter will be incremented after each read so the
next read will be from the next Sensor RAM row.

clear all positions of the Display RAM to apfQgr
code. All ones, all zeros and hexadecimal 20 ar~'p{):;;Stb
The 2 least significant bits of CD are also used to sp~bi
the blanking code (see below).

In the Auto Increment mode for reading data from the
FIFO/Sensor RAM, each read advances the address by
one so that the next read is from the next character. This
Auto Incrementing has no effect on the display.

r~
1

Read Display RAM

C",'

AU
IX ' OM''
AB = Hex 20 (0010 0000)

1

All Ones

Enable clear display when = 1 (or by CA = 1)

Where AI is the Auto-Increment flag for the Display RAM
and AAAA is the character that the CPU is going to read
next. Since the CPU uses the same counter for reading
and writing, this command also sets the next write location
and Auto-Increment mode. This command is used to
specify the display RAM as the data source for CPU data
reads. If AI is set, the character address will be
incremented after each read (or write) so that the next
read (or write) will be from (to) the next character.
Write Display RAM
11

I 0 I 0 IAI IA IA I A I A 1

Where AI is the Auto-Increment flag for the Display RAM
and AAAA is the character that the CPU is going to write
next. The addressing and Auto-Increment are identical to
Read Display RAM. The difference is that Write Display
RAM does not affect the source of CPU reads. The CPU
will read from whichever RAM (Display or FIFO/Sensor)
was last specified. This command will, however, change
the location the next Display RAM read will be from if that
source was specified.

Clearing the display takes one display scan. During this
time the CPU cannot write to the Display RAM. The MSB
of the FIFO status word will be set during this time.
C F set the FIFO status to empty and resets the interrupt
output line. After execution of a clear command with C F
set, the Sensor Matrix mode RAM pointer will besetto row
O.
C A has the combined effect of CD and C F • C A uses the CD
clearing code to determine how to clear the Display RAM.
CA also resets the internal timing chain to resynchronize
it.
End Interrupt/Error Mode Set
Code:
For the sensor matrix modes this command lowers the
IRQ line and enables further writing into RAM. (The IRQ
line would have been raised upon the detection of a
change in a sensor value. This would have also inhibited
further writing into the RAM until resetl.

Display Write Inhibit/Blanking
Code:

'"'0'

0

1

Code:

Code:

':'

"""
i

JOJ1JxJIWJIWJBLJ BL
A

B

A

For the N-key rollover mode - if the E bit is programmed
to "1" the chip will operate in the special Error mode. (For
further details, see Interface Considerations Section.)

I

B

Status Word
Where IW is Inhibit Writing (nibble A or B) and BL is
Blanking (nibble A or B). If the display is being used as a
dual 4-bit display, then it is necessary to mask one of the 4bit halves so that entries to the Display from the CPU do
not affect the other half. The IW flags allow the
programmer to do this. It is also useful to be able to blank
either half when that half is not to be displayed. The BL
flags blank the display. The next command sets the output
code to be used as a "blank". Default after reset is all zeros.
Note that to blank a display formatted as a single 8-bit
output, it is necessary to set both BL flags to entirely blank
the display. A "1" sets the flag. Reissuing the command
with a "0" resets the flag.

The status word contains the FIFO status, error, and
display unavailable Signals. This word is read by the CPU
when Ao is high and CS and RD are low. See Interface
Considerations for more detail on status word.

Data Read
Data is read when Ao, CS and RD are all low. The source
of the data is specified by the Read FIFO or Read Display
commands. The trailing edge of RD will cause the address
of the RAM being read to be incremented if the AutoIncrement flag is set. FIFO reads always increment (if no
error occurs) independent of AI.

Clear
Code:
Where Co is Clear Display, C F is Clear FIFO Status
(including interrupt), and CA is Clear All. CD is used to

Data Write
Data that is written with Ao, CS and WR low is always
written to the Display RAM. The address is specified by the
latest Read Display or Write Display command. AutoIncrementing on the rising edge of WR occurs if AI set by
the latest display command.

6-297

8279, 8279-5
INTERFACE CONSIDERATIONS
A.

S~anned

Increment flag is set to zero, or by the End Inte
command if the Auto-Increment flag is set to one.

Keyboard Mode, 2-Key Lockout

There are three possible combinations of conditions that
can occur during debounce scanning. When a key is
depressed, the debounce logic is set. A full scan of the
keyboard is ignored, then other depressed keys are
looked for. If none are encountered, it is a single key
depression and the key position is entered into the FIFO
along with the status of CNTL and SHIFT lines. If the FIFO
was empty, IRQ will be set to signal the CPU that there is
an entry in the FI FO. If the FI FO was full, the key will not be
entered and the error flag will be set. If another closed
switch is encountered, no entry to the FIFO can occur. If
all other keys are released before this one, then it will be
entered to the FIFO. If this key is released before any
other, it will be entirely ignored. A key is entered to the
FIFO only once per depression, no matter how many keys
were pressed along with it or in what order they were
released. If two keys are depressed within the debounce
cycle, it is a simultaneous depression. Neither key will be
recognized until one key remains depressed alone. The
last key will be treated as a single key depression.

Note: Multiple changes in the matrix Addressed by (SLO-3
= 0) may cause multiple interrupts. (SLo = 0 in the Decoded
Model. Reset may cause the 8279 to see multiple changes.
E. Data Format
In the Scanned Keyboard mode, the character entered
into the FIFO corresponds to the position of the switch in
the keyboard plus the status of the CNTL and SHI FT lines.
CNTL is the MSB of the 'character and SHIFT is the next
most significant bit. The next three bits are from the scan
counter and indicate the row the key was found in. The last
three bits are from the column counter and indicate to
which return line the key was connected.

I

CNTL

ISHIFTI

~ETUR~
SCANNED KEYBOARD DATA FORMAT

In Sensor Matrix mode, the data on the return lines is
entered directly in the row of the Sensor RAM that
corresponds to the row in the matrix being scanned.
Therefore, each switch postion maps directly to a Sensor
RAM position. The SHIFT and CNTL inputs are ignored in
this mode. Note that switches are not necessarily the only
thing that can be connected to the return lines in this
mode. Any logic that can be triggered by the scan lines
can enter data to the return line inputs. Eight multiplexed
input ports could be tied to the return lines and scanned by
the 8279.

B. Scanned Keyboard Mode, N-Key Rollover
With N-key Rollover each key depression is treated
independently from all others. When a key is depressed,
the debounce circuit waits 2 keyboard scans and then
checks to see if the key is still down. If it is, the key is
entered into the FIFO. Any number of keys can be
depressed and another can be recognized and entered
into the FIFO. If a simultaneous depression occurs, the
keys are recognized and entered according to the order
the keyboard scan found them.
C. Scanned Keyboard - Special Erlor Modes

MSB

For N-key rollover mode the user can program a special
error mode. This is done by the "End Interrupt/Error Mode
Set" command. The debounce cycle and key-validity
check are as in normal N-key mode. If during a single
debounce cycle, two keys are found depressed, this is
considered a simultaneous multiple depression, and sets
an error flag. This flag will prevent any further writing into
the FIFO and will set interrupt (if not yet set). The error flag
could be read in this mode by reading the FIFO STATUS
word. (See "FIFO STATUS" for further details.) The error
flag is reset by sending the normal CLEAR command with
CF

LSB

MSB

RL71 RL61 RLsl RL41 RL31 RL21 RLl

LSB

IRLo

In Strobed Input mode, the data is also entered to the FIFO
from the return lines. The data is entered by the rising
edge of a CNTL/STB line pulse. Data can come from
another encoded keyboard or simple switch matrix. The
return lines can also be used as a general purpose strobed
input.
MSB

= 1.

LSB

D. Sensor Matrix Mode
In Sensor Matrix mode, the debounce logic is inhibited.
The status of the sensor switch is inputted directly to the
Sensor RAM. In this way the Sensor RAM keeps an image
of the state of the switches in the sensor matrix. Although
debouncing is not provided, this mode has the advantage
that the CPU knows how long the sensor was closed and
when it was released. A keyboard mode can only indicate
a validated closure. To make the software easier, the
designer should functionally group the sensors by row
since this is the format in which the CPU will read them.
The IRQ line goes high if any sensor value change is
detected at the end ofa sensor matrix scan. The IRQ line is
cleared by the first data read operation if the Auto-

F. Display
Left Entry
Left Entry mode is the simplest display format in that each
display position directly corresponds to a byte (or nibble)
in the Display RAM. Address 0 in the RAM is the left-most
display character and address 15 (or address 7 in 8
character display) is the right most display character.
Entering characters from position zero causes the display
to fill from the left. The 17th (9th) character is entered back
in the left most position and filling again proceeds from
there.

6-298

8279, 8279-5
o

1st entry

L:...L.J.

o
2nd entry

1

1

1st entry

Address

1

14 15

3
1

2

2nd entry

11 1 2 1

O>mmand
10010101

11 12 1

o

===EEJ
o
G2I ====EEJ
o
~= ===
EEl
~=

2
1

o

1

4
1

3

5
1

4

1

5

234
1

1

1

1

6

5

I ::d~es~

1

1

1

7....:.'b!$pl~~li.

6

7

1
6

1

7

I

1

Enter next at Location 5 Auto Increment

o

14 15

3rd entry

1

4th entry

2

11 1 2 1

o

LEFT ENTRY MODE
(AUTO INCREMENT)

1

11 1 2

3
1

2

4

II!

6

13 1

1

3

5

4

5

7
1

6

I

7

13 14 1

LEFT ENTRY MODE
(AUTO INCREMENT)

Right Entry

Right entry is the method used by most electronic
calculators. The first entry is placed in the right most
display character. The next entry is also placed in the right
most character after the display is shifted left one
character. The left most character is shifted off the end
and is lost.
2

1st entry

1

11 1

14 15

1

lBthentry

RAM

14 15

1

17th entry

o

14 15_Display

_-II]

Q:EI ====ITI
o

16th entry

1

f1lI_- _- _-

14 15

IT] ====1

1

In the Right Entry mode, Auto Incrementing and non
Incrementing have the same effect as in the Left Entry
except if the address sequence is interrupted:
2
1st entry

I I

O-Display
11

I ::d~ess

2nd entry

I

3
1

4
1

234
1

1

5
1

1

7

0-4-Display
11 1

1

670

5

1

6

1

1

1

11 1 2

::d~ess

I

23456701
O>mmand
10010101
3

3rdentry

rn= ===

0

2

Enter next at Location 5 Auto Increment

1 112 13

o

16th entry

4

11 121

1

34567012

13 14 15

GliI ====

114115116

1

2

14 15

~====1151161171

18th entry

~=

3

==

15

0

I

11131

111211

45670123

0

17th entry

2

3rdentry

4th entry

13141

11 121

RIGHT ENTRY MODE
(AUTO INCREMENT)

1

Starting at an arbitrary location operates as shown below:

-1161171181

o

RIGHT ENTRY MODE
(AUTO INCREMENT)

~;,~;~~

Note that now the display position and register address do
not correspond. Consequently, entering a character to an
arbitrary position in the Auto Increment mode may have
unexpected results. Entry starting at Display RAM address
o with sequential entry is recommended.

1

1
1

2
1

4

3

1

1

5
1

6
1

7 -4- Display

1

I ::d~ess

Enter next at Location 5 Auto Increment

12345670

1st entry

I I

2nd entry

[

Bthentry

14151617181112131

9thentry

15161718191213141

1

I

11

I

23456701

Auto Increment
In the Left Entry mode, Auto Incrementing causes the
address where the CPU will next write to be incremented
by one and the character appears in the next location.
With non-Auto Incrementing the entry is both to the same
RAM address and display position. Entry to an arbitrary
address in the Auto Increment mode has no undesirable
side effects and the result is predictable:

I

11 12 1

II

RIGHT ENTRY MODE
(AUTO INCREMENT)

6-299

8279, 8279-5
Entry appears to be from the initial entry point.

In a Sensor Matrix mode, a bit is set in
word to indicate that at least one sensor
is contained in the Sensor RAM.

8/16 Character Display Formats

In Special Error Mode the SIE bit is showing the error flag
and serves as an indication to whether a simultaneous
multiple closure error has occurred.

If the display mode is set to an 8 character display, the on
duty-cycle is double what it would be for a 16 character
display (e.g., 5.1 ms scan time for 8 characters vs. 10.3 ms
for 16 characters with 100 kHz internal frequency).

FIFO STATUS WORD

G. FIFO Status

,FIFO Full

FIFO status is used in the Keyboard and Strobed Input
modes to indicate the number of characters in the FIFO
and to indicate whether an error has occurred. There are
two types of errors possible: overrun and underrun.
Overrun occurs when the entry of another character into a
full FIFO is attempted. Underrun occurs when the CPU
tries to read an empty FIFO.

Flag for

The FIFO status word also has a bit to indicate that the
Display RAM was unavailable because a Clear Display or
Clear All command had not completed its clearing
operation.

APPLICATIONS

KEYBOARD
MATRIX

SHIFT
CONTROL

8 COLUMNS

8/
RETURN
LINES

INT
8·BIT
MICRO-

PROCESSOR
SYSTEM

SHIFT CNTL
INT

RO_7

vOD

BUS

8/

DO_7

CONTROLS {

WR

RESET
CS

ADDRESS{
BUS
CLOCK

C/O
ClK

lOR
lOW

3-- 8 DECODER

~ ~3lSB

ov

-

RD

?

3

Vssj

DATA BUS

DATA

8 ROWS

8 0 _3

8279

4/

t4

SCAN LINES

RESET

4 ....... 16 DECODER

CS

c/o
CLK SO _
3

A O_ 3 BD

BLANK I

I ~'SPlAY

1

tis

ADDRESSES
(DECODED)

4
I

FIGURE 2. GENERAL BLOCK DIAGRAM

6-300

DISPLAY
CHARACTERS
DATA
DISPLAY

I

8279, 8279-5
'COMMENT: Stresses above those listed u~d~'[~''tsql
Maximum Ratings" may cause permanent damage"to, (he""
device. This is a stress rating onlv and functional op~~a/\.,
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliabilitv.

ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature . . . . . . . . . . . . . . O°C to 70°C
Storage Temperature . . . . . . . . . . . . . -65°C to 125°C
Voltage on any Pin with
Respect to Ground . . . . . . . . . . . . . . -0.5V to +7V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 1 Watt

D.C. CHARACTERISTICS
Symbol

TA = O°C to 70°C, Vss = OV, Note 1

Parameter

Min.

Max.

Unit

Input Low Voltage for Shift Control
and Return Lines

-0.5

1.4

V

VIL2

Input Low Voltage for All Others

-0.5

0.8

VIH1

Input High Voltage for Shift, Control
and Return Lines

2.2

VIH2

Input High Voltage for All Others

2.0

VOL

Output Low Voltage

VOH

Output High Voltage on Interrupt
Line

11L1

Input Current on Shift, Control and
Return Lines

+10
-100

IIL2

Input Leakage Current on All Others

10FL
Icc

VIL1

Test Cond itions

V
V
V

0.45
3.5

V

Note 2

V

Note 3

pA
pA

VIN = Vee
VIN = OV

±10

pA

VIN = Vee to OV

Output Float Leakage

±10

pA

VO UT = Vee to OV

Power Supply Current

120

mA

Notes:

1. 8279. Vee ~ +5V ± 5%; 8279-5. Vee ~ +5V ± 10%.
2. 8279. 10 L ~ 1.6mA; 8279-5. 10 L ~ 2.2mA.
3. 8279, 10H ~ -100MA; 8279-5. 10H ~ -400MA.

CAPACITANCE
SYMBOL

TEST

TYP.

MAX.

UNIT

Cin

Input Capacitance

5

10

pF

Vin=Vee

Cout

Output Capacitance

10

20

pF

Vout=Vec

6-301

TEST CONDITIONS

8279, 8279-5
A.C. CHARACTERISTICS
TA ; O°C to 70°C, VSS ; OV, (Note 1 )

BUS PARAMETERS
READ CYCLE:
8279-5

8279
Symbol

Parameter

Min.

Max.

Max.

Min.

Unit

tAR

Address Stable Before READ

50

0

ns

tRA

Address Hold Time for READ

5

0

ns
ns

250

tRR

READ Pulse Width

tRO[2]

Data Delay from READ

420
300

150

ns

tAO[2]

Address to Data Valid

450

250

ns

tOF

READ to Data Floating

100

ns

tRCY

Read Cycle Time

10

100

10
1

1

Jis

WRITE CYCLE:
8279
Symbol

-

Parameter

Min.

8279-5
Max.

Min.

Max.

Unit

tAW

Address Stable Before WR ITE

50

0

tWA

Address Hold Time for WR ITE

20

0

ns

tww

WR ITE Pulse Width

400

250

ns

tow

Data Set Up Time for WR ITE

300

150

ns

two

Data Hold Time for WR ITE

40

0

ns

ns

Notes:

1. 8279. VCC ~ +5V ±5%; 8279-5, VCC ~ +5V ±10%.
2. 8279, CL ~ 100pF; 8279-5, CL ~ 150pF.
OTHER TIMINGS:
8279
Symbol

8279-5
Max.

Unit

Min.

Clock Pulse Width

230

120

nsec

tCY

Clock Period

500

320

nsec

Keyboard Scan Time:
Keyboard Debounce Time:
Key Scan Time:
Display Scan Time:

Max.

Min.

Parameter

t1,w

Digit-on Time:
Blanking Time:
Internal Clock Cycle:

5.1 msec
10.3 msec
80 Jisec
10.3 msec

INPUT WAVEFORMS FOR A.C. TESTS:

"=X

2.0

>

TEST POINTS

0.8

0.45

6-302

<

2.0

0.8

)C

480 Jisec
160 Jisec
10 Jisec

8279, 8279-5
WAVEFORMS
1. Read Operation
(SYSTEM'S
ADDRESS BUS)
....--tAR _1~·~-------------------tRCY

~---------------------

------+---------------1

1~--------tRR---------'1

(R EAD CONTRO II

2. Write Operation
(SYSTEM'S
ADDR ESS BUSI

~-------~w--------~

(WRITE CONTROL I

~tDW~
'J - D A T A VALID
--'fI

DATA BUS
DATA
IINPUTI _ _ _ _ _M_A_Y_C_H_A_N_G_E_ _ _

1---__

3. Clock Input

6·303

~D
~

DATA

. "''-_____M_A_Y_CH_A_N_G_E_ _ _ _ __

6-304

, '

~
I
I

MEMORY and I/O EXPANDERS FOR MCS-85™

TM

MEMORY and I/O EXPANDERS FOR MCS-85
8155/8156 2048-Bit Static MOS RAM with 110 Ports and Timer . . . . . . . . . . . . . . . . .
8355 16,384·Bit ROM with 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8755 16,384-Bit EPROM with 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6·307
6·319
6·326

inter

I,

8155/8156
2048 BIT STATIC MOS RAM WITH 1/0 PORTS AND TIMER
8155 8156 -

Active Low Chip Enable (CE)
Active High Chip Enable (CE)

* Directly Compatible With 8085 CPU
• 256 Word x 8 Bits

• 1 Programmable 6 Bit I/O Port

• Single +5V Power Supply
• Completely Static Operation

• Programmable 14 Bit Binary Counter/
Timer

• Internal Address Latch

• Multiplexed Address and Data Bus

• 2 Programmable 8 Bit I/O Ports

• 40 Pin DIP

The 8155 and 8156 are RAM and I/O chips to be used in the MCS-85'· microcomputer system. The RAM portion is designed
with 2K bit static cells organized as 256 x 8. They have a maximum access time of400nsto permit use with no wait states in
8085 CPU.
The I/O portion consists of three general purpose I/O ports. One of the three ports can be programmed to be status pins,
thus allowing the other two ports to operate in handshake mode.
A 14 bit programmable counter/timer is also included on chip to provide either a square wave or terminal count pulse for
the CPU system. It operates in binary countdown mode. and its timer modes are programmable.

BLOCK DIAGRAM

PIN CONFIGURATION

PC3

vee

pc.

PC 2

TIMER IN

PC,

RESET

PC o

PC s

PB1

TIMER OUT

PBs

101M

PBs

*

PB.

AD
WR

PB 3

101M

ADo_7

256 X 8
STATIC
RAM

*
ALE

PB 2

ALE

PB,

ADo

PB o

AD,

PA1

AD2

PAs

AD3

PAs

AD.

PA.

RD

WR
RESET

TIMER

ADs

PA3

TIMER ClK

AD.

PA2

TIMER OUT

AD1

PA,

Vss

PAo

*.

8155

6-307

= CE,

~
~
~

PAo~7

PBo-1

PC O- 5

Lvcc

(+5V)

vss IOV}

8156

= CE

8155/8156
8155/8156 FUNCTIONAL PIN DEFINITION
The following describes the functions of all of the 8155/8156 pins.

Symbol

Function
The Reset signal is a pulse provided
by the 8085 to initialize the system.
Input high on this line resets the chip
and initializes the three I/O ports to
input mode. The width of RESET
pulse should typically be 600 nsec.
(Two 8085 clock cycle times).
These are 3-state Address/Data lines
that interface with the CPU lower 8bit Address/Data Bus. The 8-bit
address is latched into the address
latch on the falling edge of the ALE.
The address can be either for the
memory section or the I/O section
depending on the polarity olthe 10/M
input signal. The 8-bit data is either
written into the chip or Read from the
chip depending on the status of
WRITE or READ input signal.

ADO-7

CE or

CE

PA O-7(8)

These 8 pins are general purpose I/O
pins. The in/out direction is selected
by programming the Command/
Status Register.
PCO-5(6)

Input Iowan this line with the Chip
Enable active causes the data on the
AD lines to be written to the RAM or
I/O ports depending on the polarity of
10/M.
ALE

Address Latch Enable: This control
signal latches both the address on the
ADo-7 lines and the state of the Chip
Enable and 10/M into the chip at the
falling edge of ALE.

10/M

10/Memory Select: This line selects
the memory if low and selects the 10 if
high.

6-308

These 6 pins can function as either
input port. output port. or as control
signals for PA and PB. Programming
is done through the CIS Register.
When PCO-5 are used as control
signals. they will provide the following:
PCo - A INTR (Port A Interrupt)
PC1 - A BF (Port A Buffer full)
PC2 -

Chip Enable: On the 8155. this pin is
CE and is ACTIVE LOW. On the 8156.
this pin is CE and is ACTIVE HIGH.
Input Iowan this line with the Chip
Enable active enables the ADo-7
buffers. If 10/M pin is low. the RAM
content will be read out to the AD bus.
Otherwise the content of the selected
I/O port will be read to the AD bus.

Function
These 8 pins are general purpose I/O
pins. The ill/out direction is selected
by programming the Command/
Status Register.

A STB (Port A Strobe)

PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 -- B STB (Port B Strobe)
TIMER IN

This is the input to the counter timer.

TIMER OUT

This pin is the timer output. This
output can be either a square wave or
a pulse depending on the timer mode.
+5 volt supply.

Vss

Ground Reference.

8155/8156
OPERATIONAL DESCRIPTION
The 8-bit address on the AD lines, the Chip Enable input,
and 10/M are all latched on chip at the falling edge of ALE.
A Iowan the 10/M must be provided to select the memory
section.

The 8155/8156 includes the following operational
features:
• 2K Bit Static RAM organized as 256 x 8
• Two 8-bit I/O ports (PA & PB) and one 6-bit I/O port
(PC)
• 14-bit binary down counter
The I/O portion contains four registers (Command/
Status, PAO-7, PBO-7, PCO-5). The 10/M (IO/Memory
Select) pin selects the I/O or the memory (RAM) portion.
Detailed descriptions of memory, I/O ports and timer
functions will follow.

IT {8155 I

\

V

~

/

1\

/

\

V

OR

CE {81 56 I

10(M

i

~

ADO_7

ADDRESS

~

I

1\

/

V

\.

X

DATA VALID

i
I
AL E

I

RD OR WR

I
I
I

NOTE, FOR DETAILED TIMING DIAGRAM INFORMATION, SEE FIGURE 7 AND A.C. CHARACTERISTICS.

FIGURE 1. MEMORY READ/WRITE CYCLE,

6-309

8155/8156
PROGRAMMING OF THE COMMAND/
STATUS REGISTER

READING THE COMMAND/STATUS
REGISTER

The command register consists of eight latches one for
each bit. Four bits (0-3) define the mode of the ports, two
bits (4-5) enable or disable the interrupt from port C when
it acts as control port, and the last two bits (6-7) are for the
timer.

The status register consists of seven latches one for each
bit; six (0-5) for the status of the ports and one (6) for the
status of the timer.

The CIS register contents can be altered at any time by
using the I/O address XXXXXOOO during a WRITE
operation. The meaning of each bit of the command byte
is defined as follows:

~l~

DEfiNES PA0-7 }

The status of the timer and the I/O section can be polled by
reading the CIS Register (Address XXXXXOOO). Status
word format is shown below:

0'" INPUT

_ _ +- DEFINES PBO_7

1 == OUTPUT

PORT A INTERRUPT REQUEST

00 ,-;ALT1
------Jto-

DEFINES PC0-5 {

11 '" Al T 2

10

'---------_

___

~~:EBRL~~~RT

=

(INPUT/OUTPUT)

AL T 4

PORT A INTERRUPT ENABLE

A

1 '" ENABLE

B

}

~ ~~::RL~~~RT

PORT A BUFFER FULL/EMPTY

01 =ALT3

----~

- - - - - -________ PORT B BUFFER FULL/EMPTY
(INPUT/OUTPUT)

00"" NOP - DO NOT AFFECT COUNTER
OPERATION
01

TIMER COMMAND

=

'---------~..

STOP - NOP IF TIMER HAS NOT STARTED;
STOP COUNTING IF THE TIMER IS
RUNNING

=0

NEW COUNT,)

START - LOAD MODE AND CNT LErlJGTH
AND START IMMEDIATELY AFTER
LOADING (IF TIMER IS NOT PRESENTLY
RUNNING). IF TIMER IS RUNNING, START
THE NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PAESENT Te
IS REACHED.

FIGURE 2. COMMAND/STATUS REGISTER BIT
ASSIGNMENT.

PORT B INTERRUPT ENABLED

~----------_ TIMER INTERRUPT (THIS BIT
IS LATCHED HIGH WHEN
TERMINAL COUNT IS
REACHED, AND IS A ESET TO
LOW UPON READING OF THE
cIS REGISTER OR STARTING

10"" STOP AFTER Te - STOP IMMEDIATELY
AFTER PR ESENT Te IS REACHED (NOP
IF TIMER HAS NOT STARTED)
11

PORT B INTERRUPT REQUEST

0= DISABLE

FIGURE 3. COMMAND/STATUS REGISTER STATUS
WORD FORMAT.

6-310

8155/8156
INPUT/OUTPUT SECTION

The following diagram shows how I/O PORTS Aand Bare
structured within the 8155 and 8156:

The I/O section of the 8155/8156 consists of four registers
as described below.
•

8155/8156
ONE BIT OF PORT A OR PORT B

Command/Status Register (C/S) - This register is
assigned the address XXXXXOOO. The CIS address
serves the dual purpose.
When the CIS register is selected during WRITE
operation, a command is written into the command
register. The contents of this register are not
accessible through the pins.
When the CIS (XXXXXOOO) is selected during a READ
operation, the status information of the I/O ports and
the timer become available on the ADO-7 lines.

•

PA Register - This register can be programmed to be
either input or output ports depending on the
status of the contents of the CIS Register. Also
depending on the command, this port can operate in
either the basic mode or the strobed mode (See timing
diagram). The I/O pins assigned in relation to this
register are PAO-7' The address of this regis:er is
XXXXX001.

NOTES:
(1) OUTPUT MODE

i~l ~~~~LBEE~i~:UT _

Low
Low

S'il3

Input Control

1 FOR OUTPUT MODE

Reading from an input port with nothing connected to the
pins will provide unpredictable results.

OUTPUT MODE
Low

High
Input Control

TABLE 1. TABLE OF PORT CONTROL ASSIGNMENT.
Pin
PCO
PC1
PC2
PC3
PC4

~

ALT 1
Input
Input
Input
Input
I nput
Input

Port
Port
Port
Port
Port
Port

ALT 2
Output
Output
Output
Output
Output
Output

Port
Port
Port
Port
Port
Port

ALT 3

ALT 4

A INTR (Port A Interrupt)
A Bf..l!:'ort A Buffer Full)
A STB (Port A Strobe)
Output Port
Output Port
Output Port

A INTR (Port A Interrupt)
A B£....(£'ort A Buffer Full)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B Bf..l!:'ort B Buffer Full)
B STB (Port B Strobe)

The set and reset of INTR and BF with respect to STB, WR and RD timing is shown in Figure 8.
To summarize, the registers' aSSignments are:

Address

Pinouts

Functions

XXXXXOOO
XXXXXOO1
XXXXX010
XXXXX011

Internal
PAO-7
PSO-7
PCO-5

Command/Status Register
General Purpose 1/0 Port
General Purpose I/O Port
General Purpos8 I/O Port or
Control Lines

6-311

INPUT MODE

When in the AL T 1 or AL T 2 modes, the bits of PORT Care
structured like the diagram above in the simple input or
output mode, respectively.

When the 'C' port is programmed to either AL T3 or AL T4,
the control signals for PA and PB are initialized as follows:
INPUT MODE

=0

'" a FOR

Note also that the output latch is cleared when the port
enters the input mode. The output latch cannot be loaded
by writing to the port if the port is in the input mode. The
result is that each time a port mode is changed from input
to output, the output pins will go low. When the 8155/56 is
RESET, the output latches are all cleared and all 3 ports
enter the input mode.

When PCO-5 is used as a control port, 3-bits are
assigned for Port A and 3 for Port B. The first bit is an
interrupt that the 8155 sends out. The second is an
output signal indicating whether the buffer is full or
empty, and the third is an input pin to accept a strobe
for the strobed input mode. See Table 1.

SF
INTR

(4)

CONTROL

Note in the diagram that when the I/O ports are
programmed to be output ports, the contents of the output
ports can still be read by a READ operation when
appropriately addressed.

PC Register - This register has the address XXXXX011
and contains only 6-bits. The 6-bits can be programmed to be either input ports, output ports or as control
signals for PA and PB by properly programmin9 the
AD2 and AD3 bits of the CIS register.

CONTROL

MU L TIPLEXER

READ PORT'" (IO/M=1). (RD=O). (CE ACTIVE). (PORT ADDRESS SELECTED)
WRITE PORT'" (IO/M;1). (WR=O). ICE ACTIVE). (PORT ADDRESS SELECTED)

PB Register - This register functions the same as PA
Register. The 1/0 pins assigned are PBO-7' The address
of this register is XXXXX010.
•

STB

}

No. of Bits
8
8
8
6

8155/8156
TIMER SECTION
The timer is a 14-bit counter that counts the 'timer input'
pulses and provides either a square wave or pulse when
terminal count (TC) is reached.
'----,._-'11'----_ _ _ _- ,_ _

The timer has the I/O address XXXXX1 00 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register.

TIMER MODE

The timer addresses serve a dual purpose. During WRITE
operation, a COUNT LENGTH REGISTER (CLR) with a
count length (bits 0-13) and a timer mode (bits 14-15) are
loaded. During READ operation the contents of the
counter (the present count) and the mode bits are read.

I
LSB OF CNT LENGTH

To be sure that the right content of the counter is read, it is
preferable to stop counting, read it, and then load it again
and continue counting.

FIGURE 4. TIMER FORMAT

To program the timer, the COUNT LENGTH REG is
loaded first, one byte at a time, by selecting the timer
addresses. Bits 0-13 will specify the length of the next
count and bits 14-15 will specify the timer output mode.

M2

Ml defines the timer mode as follows:

M2

Ml

a

a

Puts out low during second half of
count.
Square wave, i.e., the period of the
square wave equals the count
length programmed with automatic reload at terminal count.

a

Single pulse upon TC being
reached.
Automatic reload, i.e., single pulse
every time TC is reached.

There are four modes to choose from:

o

O.

Puts out low during second half of count.
1. Square wave
2. Single pulse upon TC being reached
3. Repetitive single pulse every time TC is readied and
automatic reload of counter upon TC being reached, until
instructed to stop by a new command loaded into CIS.
Bits 6-7 of Command/Status Register Contents are used
to start and stop the counter. There are four commands to
choose from:

-

MSB OF CNT LENGTH

Note: In case of an asymmetric count, i.e. 9, larger half of
the count will be high, the larger count will stay active as
shown in Figure 5.

Note: See the further description on Command/Status
Register.

C/S7 C/S6

o

a

a

NOP -

Do not affect counter operation.

STOP - NOP if timer has not started; stop
counting if the timer is running.

a

STOP AFTER TC - Stop immediately after
present TC is reached (NOP if timer has not
started)
START -- Load mode and CNT length and
start immediately after loading (if timer is
not presently running). If timer is running,
start the new mode and CNT length
immediately after present TC is reached.

5

__

Note: 5 and 4 refer to the number of clock cycles in that
time period.

FIGURE 5. ASYMMETRIC COUNT.
The timer in the 8155 is not initialized to any particular
mode when hardware RESET occurs, but RESET does
~ the counting. Therefore, counting cannot begin
following RESET until the desired mode and count length
and START command are issued.

6-312

8155/8156
8085 MINIMUM SYSTEM CONFIGURATION
Figure 6shows that a minimum system is possible using only
three chips:
•
•
•
•
•

256 Bytes RAM
2K Bytes ROM
38 I/O Pins
1 Interval Timer
4 I nterru pt Levels

A8-15

:>

/1
ADO-7

/'-..,

"ALE
8085

-

RD
WR
101M

-

eLK

-

RESET OUT

-

READY

TIMER
IN

RESET

T6~"i'~

/~

H

TIMER

-

-

WR RD ALE

,

CE " ( ) '

LATCHES

~

I
t
CONTROL

101M

A8AD _101
CE M ALE
\)'Al0'\j07

iffiiOW CLK RST

J

256 x 8
RAM

8355 [ROM + 110 I
OR
8755 [PROM + 1101

1

8156

~~~$

BBB

FIGURE 6. 8085 MINIMUM SYSTEM CONFIGURATION.

6-313

BB

RDY

.8155/8156

ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Stresses above those listed
Maximum Ratings" may cause permanent dam
device. This is a stress rating only and functional opiJrlii;7h
tion of the device at these or any other conditions above '(l;},
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias ................ O°C to +70°C
Storage Temperature ............... -65°Cto+150°C
Voltage on Any Pin
With Respect to Ground ............... -0.3Vto +7V
Power Dissipation ............................. 1.5W

D.C. CHARACTERISTICS

(TA

=

O°C to 70°C; Vee

=

5V ± 5%)

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

VIL

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vee +O·5

V

VOL

Output Low Voltage

0.45

V

VOH

Output High Voltage

IlL

Input Leakage

MA

VIN = Vee to OV

ILO

Output Leakage Current

±10

J1A

0.45V <___________
B. BASIC OUTPUT MODE

DATA BUS*

DUTPUT
'DATA BUS TIMING IS SHOWN IN FIGURE 7.

FIGURE 9. BASIC I/O TIMING WAVEFORM.

LOAD
COUNTER
FROM CLR
COUNT

RELOAD

--1

COUNTER

FROM CLR

I

TIMER-IN

TIMER-OUT
(PULSEJ

TIMER-OUT
(SO. WAVEJ _ _ _ _ _ _ _ _ -.J '/

COUNTDOWN FROM 3 TO 0
tCYC

320 ns MIN.

t R1SE & tFALl

ns MAX.
BOns MIN.
120 ns MIN.
TIMER-IN TO TIMER-OUT LOW (TO BE DEFINEDJ.
TIMER-IN TO TlMER-OUT HIGH (TO BE DEFINEDJ.

t1
t2
ITL

ITH

30

FIGURE 10. TIMER OUTPUT WAVEFORM.

6-318

----I

inter

I.I
I

8355
16,384 BIT ROM WITH I/O

I
I

~

*Directly Compatible With 8085 CPU

• 2 General Purpose 8 Bit I/O Ports

• 2048 Words x 8 Bits
• Single +5V Power Supply
• Internal Address Latch

I/O Port Line Individually
• Each
Programmable as Input or Output
• Multiplexed Address and Data Bus
• 40 Pin DIP

The 8355 is a ROM and I/O chip to be used in the MCS-85'· microcomputer system. The ROM portion is organized as 2048 x
8. It has maximum access time of 400 ns to permit use with no wait states in 8085 CPU.
The I/O portion consists of two general purpose I/O ports. Each I/O port has 8 port lines. and each I/O port line is individually programmable as input or output.

BLOCK DIAGRAM

PIN CONFIGURATION

vee

ps,

ClK

PBs
PB,
N.C. (NOT CONNECTED)

5

PB.
PB,

READY
ADO~7

PB,
PB,

Aa:-10

PB.
CE

2K X8

PAs

CE

ROM

AD,

PAs

101M

AD,

PA.

ALE

AD,

PA,

AD

lOW

AD,

PA,

lOW

AD.

PA,

RESET

AD,

PA,

lOR

AD.

A,.

AD,

Ag

~
~

PAO~7

PBO~7

~vce

Vss

1+5V)

Vss IOV)

6-319

8355
8355 FUNCTIONAL PIN DEFINITION
Symbol

Function

Symbol

Function

ALE

When ALE (Address Latch Enable) is
high, ADO-7, 10/M, AS-10, CE, and CE
enter address latched. The signals
(AD, 10/M, AS-10, CE, CE) are latched
in at the trailing edge of ALE.

CLK

The CLK is used to force the READY
into its high impedance state after it
has been forced low by CE low, CE
high and ALE high.

READY

ADO-7

Bi-directional Address/Data bus. The
lower 8-bits of the ROM or I/O
address are applied to the bus lines
when ALE is high.

Ready is a tri-state output controlled
by CE, CE, ALE and CLK. READY is
forced low when the Chip Enables are
active during the time ALE is high,
and remains low until the rising edge
of the next CLK (see Figure 4).

PA O- 7

These are general purpose I/O pins.
Their input/output direction is determined by the contents of Data
Direction Register (DDR). Port A~
selected for write operations when
the Chip Enables are active and lOW
is low and a a was previously latched
from ADo.

During an I/O cycle, Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when latched
Chip Enables are active, the output
buffers present data on the bus.
AS-lO

These are the high order bits of the
ROM address. They do not affect I/O
operations.

CE
CE

Chip Enable Inputs: CE is active low
and CE is active~. The 8355 can be
accessed only when BOTH Chip
Enables are active at the time the ALE
signal latches them up. If either Chip
Enable input is not active, the ADo-7
and READY outputs will be in a high
impedance state.

10/M

If the latched 10/Mis high when RD is
low, the output data comes from an
I/O port. If it is low the output data
comes from the ROM.

Read operation is selected by lOR low
when the Chip is enabled and ADo
low.
Alternately, 10/M high and RD low
may be used in place of lOR when the
chip is enabled and ADO is low to
allow reading from a port.
PBO-7

This general purpose I/O port is
identical to Port A except that it is
selected by a 1 latched from ADO.

RESET

An input high on RESET causes all
pins in Ports A and B to assume input
mode.

If the latched Chip Enables are active
when RD goes low, the ADo-7 output
buffers are enabled and output either
the selected ROM location or I/O
port. When both RD and lOR are high,
the ADo-7 output buffers are tristated.
If the latched Chip Enables are active,
a Iowan lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on AD o- 7.
The state of 10/M is ignored.

6-320

When the Chip Enables are active, a
Iowan lOR will output the selected
I/O port onto the AD bus. lOR low
performs the same function as the
combination 10/M high and RD low.

Vee
Vss

+5 volt supply.

a volt supply.

8355
FUNCTIONAL DESCRIPTION

Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's output buffer to be
disabled, preventing the data in the output latch from
being passed through to the pin. This is equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be
initialized with a value prior to enabling the output.

ROM Section
The ROM section of the chip is addressed by an 11-bit
address and the Chip Enables. The address and levels on
the Chip Enable pins are latched into the address latches
on the falling edge of ALE. If the latched Chip Enables are
active and 10iM is low when RD goes low, the contents of
the ROM location addressed by the latched address are
put out through ADo-7 output buffers.

The diagram also shows that the contents of PORT A and
PORT B can be read even when the ports are configured
as outputs.

1/0 Section

System Interface with 8085

The I/O section oj the chip is addressed by the latched
value of ADO-1' Two 8-bit Data Direction Registers in 8355
determine the input/output status of each pin in the
corresponding ports. A 0 specifies an input mode, and a 1
specifies an output mode. The table summarizes port and
DDR designation. DDR's cannot be read.

A system using the 8355 can use either one of the two I/O
Interface techniques:
Standard I/O
Memory Mapped I/O
If a standard I/O technique is used, the system can use the
feature of both CE and CEo By using a combination of
unused address lines A11-15 and the Chip Enable inputs,
the 8085 system can use up to .s each 8355's without
requiring a CE decoder. See Figure 1

ADo Selection

AD1

0
0

0

1
1

0

1
1

Port
Port
Port
Port

A
B
A Data Direction Register (DDR A)
B Data Direction Register (DDR B)

If a memory mapped I/O approach is used the 8355 will be
selected by the combination of both the Chip Enables and
IO/M Llsing the ADS-15 address lines. See Figure 2.

When lOW goes low and the Chip Enables are active, the
data on the ADo-7 is written into I/O port selected by the
latched value of ADO-1'
During this operation all I/O bits of the selected port are
affected, regardless of their I/O mode and the state of
loiM. The actual output level does not change until lOW
returns high (glitch free output).

/1

~

1<;8-15
[/

I~DO_7

A port can be read out when the latched Chip Enables are
active and either RD goes low with 10/M high, or lOR goes
low. Both input and output mode bits of a selected port will
appear on lines AD o- 7.

8085

ALE

t-t--

RD
WR
CLK (¢2)

To clarify the function of the I/O ports and Data Direction
Registers, the following diagram shows the configuration
of one bit of PORT A and DDR A. The same logic applies to
PORT Band DDR B.

I--JiEADV101M

v

rrr-

-.t

r---

l'Vv
ADO_7

8355

lOR

ONE BIT OF PORT A AND DDR A:

AS_l0

RD

ALE

8355

FIGURE 2. 8355 IN 8085 SYSTEM
(MEMORY-MAPPED I/O).

DO

READ PA
WRIfI: PA ~ (IOW-O). (CHIP ENABLES ACTIVE). (PORT A ADDRESS SELECTED)
WRITE DOR A" (i1i'W;O). (CHIP ENABLES ACTIVE) • (DIlR A ADDRESS SELECTED)
READ PA = {[(lO/M=l). (RD"O)] + (lOR"o)} • (CHIP ENABLES ACTIVE). (PORT A ADDRESS SELECTED)

6-321

1

eLK
101M
READY CE

iOW

t--

A
A8-15

A"

,~

AU

A12

A,S . V

A14

-

-

-

-

-

-

elK (q)2)

-

-

-

cp

READY

W
N

101M

-

-

-

)

r-

V

8085
ALE

RO

WR

N

-

vee

f

iiiii

AlDO~7

AS-Ill

101M
RD eLK
ALE iOW READY C1

~'"

A/DO~7

iDA

-

rrr-

vee

J
RD
ALE

eLK
101M
READY CE

row

8355

8355

(2K BYTES)

(2K BYTES)

T AlO _ '7
O1
AS-Ill

iOR

RO

ALE

eLK

iOW

t"

101M

READY

A1°0-1

CE

'.7

iOR

8355
12K BYTES)

AI-,ll

ALE

eLK

t" 7 "'7

101M

iOW READY

AIDO-7

Cf

ffiR

AI-II

1

RD elK
101M
ALE itJW READY Cf

8355
~_ {2K~"!,ES) __ ._________

Use CE for the first 8355 in the system, and CE for the other 8355's. Permits up to 5 ea. 8355's in a
system without CE decoder.

FIGURE 1.. 8355 IN 8085 SYSTEM (STANDARD 1/0).

U1
U1

v
RD

8355
(2K BYTES)
~-

Note:

CCI

Co)

I

~7
A8-10

t-t-t--

8355
',c'

ifJO,~~,'N>

;

COMMENT: Stresses above those listed urlder:.~
Maximum Ratings" may cause permanent dama
device. This is a stress rating only and functional opfJNJI.)
tion of the device at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature Under Bias ................ O°C to +70°C
Storage Temperature ............... -65°C to +150°C
Voltage on Any Pin
With Respect to Ground ............... -O.3Vto+7V
Power Dissipation ............................. 1.5W

D.C. CHARACTERISTICS

;,

*

ABSOLUTE MAXIMUM RATINGS*

(TA = o°c to 70°C; Vee = 5V

± 5%)

SYMBOL

PARAMETER

MIN.

MAX.

UNITS

Vil

Input Low Voltage

-0.5

0.8

V

VIH

Input High Voltage

2.0

Vee+O· 5

V

VOL

Output Low Voltage

VOH

Output High Voltage

III

Input Leakage

ILO
lee

0.45
2.4

TEST CONDITIONS

V

IOl = 2mA

V

IOH = -400/lA

10

/lA

VIN = Vee to OV

Output Leakage Current

±10

/lA

0.45V ';;;VOUT <'Vee

Vee Supply Current

180

mA

A.C. CHARACTERISTICS

(TA

= O°Cto

70°C; Vee

= 5V ± 5%)

SYMBOL

PARAMETER

MIN.
320

MAX.

UNITS
ns

teYe

Clock Cycle Time

Tl

ClK Pulse Width

80

ns

T2

ClK Pulse Width

120

ns

tf,t r

ClK Rise and Fall Time

tAL

Address to Latch Set Up Time

30

ns
ns

tLA

Address Hold Time after latch

80

Latch to R EAD/WR ITE Control

100

tRD

Valid Data Out Delay from READ Control

150

ns

tAD

Address Stable to Data Out Valid

400

ns

100

ns

Latch Enable Width

tRDF

Data Bus Float after READ

0

tel

READIWRITE Control to Latch Enable

20

ns

100

ns

ns

tee

READIWRITE Control Width

250

tow

Data In to WR ITE Set Up Time

150

ns

two

Data In Hold Time After WR ITE

0

ns

twp

WR ITE to Port Output

tpR

Port Input Set Up Time

50

tRP

Port Input Hold Time

50

tRYH

READY HOLD TIME

0

tARY

ADDRESS (CE) to READY
Recovery Time between Controls
Data Out Delay from READ Control

400

ns
ns
ns

120

ns

160

ns

300

ns

10

ns

6-323

I

ns

tll

tRDE

CLOAD = 150 pF
(See Figure 3)

ns

50

tle

tRv

TEST CONDITIONS

150 pF Load

8355

FIGURE 4. CLOCK SPECIFICATION FOR 8355.

eLK

A8-10

101M

=:=J
=:=J

ADDRESS
'AD

)

ADDRESS

DATA

~

I

'LL~ t----'LA-~

I

ALE
-'AL~

I- 'RDF •

i--'RDE-

I---- 'RD------.-

~'LC~

tow
~tcc

'I---"'0-

tRV

;o---tCL-

FIGURE 5. ROM READ AND 1/0 READ AND WRITE.

6·324

FIGURE 6. WAIT STATE TIMING (READY

~

0).

A. INPUT MODE

PORT
INPUT

DATA'- BUS

-- -

-

-y

-------

--------------------

B. OUTPUT MODE

__________

t:-_~-~

/

GLITCH FREE
OUTPUT

PORT
OUTPUT

DATA' - BUS
____ _

"""\/

-A_______

X. . ____

..J

'DATA BUS TIMING IS SHOWN IN FIGURE 3.

FIGURE 7. 1/0 PORT TIMING.

6·325

inter
8755
16,384 BIT EPROM WITH I/O
*Directly Compatible With 8085 CPU

•
•
•
•

•
•
•
•

2048 Words x 8 Bits
Single +5V Power Supply (V cc)
U. V. Erasable and Electrically Reprogrammable
Internal Address Latch

2 General Purpose 8 bit I/O Ports
Each I/O Port line Individually
Programmable as Input or Output
Multiplexed Address and Data Bus
40 Pin DIP

The 8755 is an erasable and electrically reprogram mabie ROM (EPROM) and I/O chip to be used in the MCS-85'·
microcomputer system. The PROM portion is organized as 2048 x 8. It has maximum access time of 400 ns to permit use
with no wait states in 8085 CPU.
The 1/0 portion consists of two general purpose 1/0 ports. Each 1/0 port has 8 port lines, and each 1/0 port line is individually programmable as input or output.

PIN CONFIGURATION

BLOCK DIAGRAM

eLK

READY
ADO~7

AS'"'-'lO

CE

2K x 8
EPROM

101M
ALE

R5
iOvii
RESET

~
~

PAO~7

PBO~7

lOR

PROG/CE~
VDD

6-326

~vccl+5VI
Vss IOVI

8755
8755 FUNCTIONAL PIN DESCRIPTION
Symbol

Function

ALE

When Address latch Enable is high,
ADO-?, 101M, AS-10, CE, and CE enter
the address latches. The signals (AD,
101M, AS-10, CE) are latched in at the
trailing edge of ALE.

ADO_?

Bi-directional AddresslData bus. The
lower 8-bits of the PROM or 1/0
address are applied to the bus lines
when ALE is high.
During an 1/0 cycle, Port A or Bare
selected based on the latched value of
ADo. If RD or lOR is low when the
latched Chip Enables are active, the
output buffers present data on the
bus.

A S-10

These are the high order bits of the
PROM address. They do not affect
1/0 operations.

CE/PROG

CHIP ENABLE INPUTS: CE is active
low and CE is active high. Both chip
enables must be active to permit
accessing the PROM. CE is also used
as a programming pin (see section on
programming).

CE

101M

If the latched 101M is high when RD is
low, the output data comes from an
1/0 port. If it is low the output data
comes from the PROM.

RD

If the latched Chip Enables are active
when RD goes' low, the ADO_? output
buffers are enabled and output either
the selected PROM location or 1/0
port. When both RD and lOR are high
the ADO_? output buffers are tristated.
If the latched Chip Enables are active.
a Iowan lOW causes the output port
pointed to by the latched value of ADo
to be written with the data on ADO-?
The state of 101M is ignored.

ClK

The ClK is used to force the READY
into its high impedance state after it
has been forced low by CE low, CE
high, and ALE high.

READY

READY is a 3-state output controlled
by CE, CE, ALE and ClK. READY is
forced low when the Chip Enables are
active during the time ALE is high,
and remains low until the rising edge
of the next ClK (see Figure 2.).

PA O_?

These are general purpose 1/0 pins.
Their input/output direction is determined by the contents of Data
Direction Register (DDR). Port A is
selected for write operations when
the Chip Enables are active and lOW
is low and a 0 was previously latched
from ADo.

Read operation is selected by either
lOR low and active Chip Enables and
ADo low, ill 10iMhigh, RD low, active
Chip Enables, and ADo low.
PBO-?

This general purpose 1/0 port is
identical to Port A except that it is
selected by a 1 latched from ADo.

RESET

In normal operation, an input high on
RESET causes all pins in Ports A and
B to assume input mode (clear DDR
register).

lOR

When the Chip Enables are active, a
Iowan lOR will output the selected
1/0 port onto the AD bus. lOR low
performs the same function as the
combination of 101M high and RD
low. When lOR is not used in a
system, lOR should be tied to Vee
("1")
+5 volt supply.
Ground Reference.
Voo is a programming voltage, and it
is normally grounded.
For programming, a high voltage is
supplied with V OO ' = 25V, typical.

FUNCTIONAL DESCRIPTION
PROM Section
The 8755 contains an 8-bit address latch which allows it to
interface directly to MCS-48 and MCS-85 Microcomputers without additional hardware.
The PROM section of the chip is addressed by the 11-bit
address and CEo The address, CE and CE are latched into
the address latches on the falling edge of ALE. If the
latched Chip Enables are active and 101M is low when RD
goes low, the contents of the PROM location addressed by
the latched address are put out on the ADO_? lines.

I/O Section
The 1/0 section of the chip is addressed by the latched
value of AD o- 1. Two 8-bit Data Direction Registers
determine the input/output status of each pin in the
corresponding port. A 0 specifies an input mode, and a 1
specifies an output mode. The table summarizes port and
DDR designation. Contents of the DDR's cannot be read.

6-327

AD1

ADO

o
o

0
1

o

Selection
Port
Port
Port
Port

A
B
A Data Direction Register (DDR A)
B Data Direction Register (DDR B)

8755
~'~!CI:j~:;~t,:~ ~ ){;~
When lOW goes low and the Chip Enables are active, the
data on the AD
is written into 1/0 port selected by the
latched value of ADO-1. During this operation all 1/0 bits of
the selected port are affected, regardless of their 1/0 mode
and the state of lo/iii!. The actual output level does not
change until lOW returns high. (glitch free output).
A port can be read out when the latched Chip Enables are
active and either RD goes low with 101M high, or lOR goes
low. Both input and output mode bits of aselected port will
appear on lines ADO-7.
To clarify the function of the 1/0 Ports and Data Direction
Registers, the following diagram shows the configuration
of one bit of PORT A and DDR A. The same logic applies to
PORT Band DDR B.
8755
ONE BIT OF PORT A AND DDR A:

initialized with a value prior to enabling tl'fe,t!?,,!itj;),
The diagram also shows that the contents of Pd~1il'(a
PORT B can be read even when the ports are conft 6'teit);\;"
as outputs.
'(II;lii,

g

ERASURE CHARACTERISTICS
The erasure characteristics of the 8755 are such that
erasure begins to occur when exposed to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
flourescent lighting could erase the typical 8755 in
approximately 3 years while it would take approximately 1
week to cause erasure when exposed to direct sunlight If
the 8755 is to be exposed to these types of lighting
conditions for extended periods of time, opaque labels are
available from Intel which should be placed over the 8755
window to prevent unintentional erasure.
The recommended erasure procedure (see page 3-55) for
the 8755 is exposure to shortwave ultraviolet light which
has a wavelength of 2537 Angstroms (A). The integrated
dose (i.e., UV intensity X exposure time) for erasure
should be a minimum of 15W-sec/cm 2 . The erasure time
with this dosage is approximately 15 to 20 minutes using
an ultraviolet lamp with a 12000).JW/cm 2 power rating.The
8755 should be placed within one inch from the lamp tubes
during erasure. Some lamps have a filter on their tubes
and this filter should be removed before erasure.

WAITE DDR A

DO

~

READ PA

WRITE PA" (iOW=O). (CHIP ENABLES ACTIVE)_ (PORT A ADDRESS SELECTED)
WRITE DoR A" (iow=O). (CHIP ENABLES ACTIVE) • (DOR A ADDRESS SELECTED)
READ PA '" {[(IO/M"'1)- (RO=O)] + (iOR=o)} • (CHIP ENABLES ACTIVE) • (PORT A ADDRESS SElECTED)

Note that hardware RESET or writing a zero to the DDR
latch will cause the output latch's output buffer to be
disabled, preventing the data in the Output Latch from
being passed through to the pin. This is equivalent to
putting the port in the input mode. Note also that the data
can be written to the Output Latch even though the Output
Buffer has been disabled. This enables a port to be

6-328

PROGRAMMING
Initially, and after each erasure, all bits of the EPROM
portions of the 8755 are in the "I" state. Information is
introduced by selectively programming "a" into the
desired bit locations. A programmed "0" can only be
changed to a "I" by UV erasure.
The 8755 is programmed on the Intel® Universal PROM
Programmer (UPPl. The UPP and its related personality
cards for the 8755 are described beginning on page 13-45
of the 1977 Intel Data Catalog.

('f'

8755
SYSTEM APPLICATIONS

K

)

~~'7

:>

/1

A8-,S
'I

8085

ALE

r-r--

RD
WR
CLK 1<12)
READY
101M

Vee

8085

~~7
ALE

r-r--

AD

r-

CLK 1<12)

r-r--

AEADY

t

r-

AlD o_,

)
)

WR

fvv

-

lOR

/1

<;8-'S

A8-10

101M

Vee

I!

rr-r--

t

r-

fVv
A/DO_7

RD CLK
101M
ALE iliW READY CE

iDA

8755

AS_1D

I

RD CLK
IDiM
ALE iliW READY CE
8755

·USE CE fOR FIRST 8755 IN SYSTEM. AND CE FOR OTHERS.
BY CONNECTING CE OF EACH 8755 CHIP TO EACH OF A"
THROUGH A,s, THE MINIMUM SYSTEM CAN USE 5·8755',
110K BYTES) WITHOUT REQUIRING CE DECODER.

FIGURE 1. 8755 IN 8085 SYSTEM
(STANDARD 1/0).

FIGURE 2. 8755 IN 8085 SYSTEM
(MEMORY-MAPPED I/O).

6-329

8755
ABSOLUTE MAXIMUM RATINGS*

'COMMENT: Stresses above those listed
$0
Maximum Ratings" may cause permanent dama'gfy,;(~,
device. This is a stress rating only and functional op'lfrai,-"",:' ,
tion of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

TemperatureUnderBias .............. -10 oe to +70 oe
Storage Temperature ............... -65°eto+150oe
Voltage on Any Pin
With Respect to Ground ............... -O.5V to +7V
Power Dissipation ............................. 1.5W

D.C. CHARACTERISTICS

(TA = o°c to 70°C; VCC = 5V ± 5%)

PARAMETER

MIN.

VIL

Input low Voltage

VIH

Input High Voltage

VOL

Output low Voltage

VOH

Output High Voltage

IlL

Input lea kage

10

J.lA

= 2mA
IoH = -400J.lA
VIN = VCC to OV

ILO

Output leakage Current

±10

J.lA

0.45V ';;;VOUT ';;;Vcc

Icc

Vcc Supply Current

180

mA

SYMBOL

MAX.

UNITS

-0.5

0.8

V

2.0

Vcc+{)·5

V

0.45

V

2.4

.

A.C. CHARACTERISTICS

V

TEST CONDITIONS

IOL

.

(TA = o°c to 70°C; Vcc = 5V ± 5%)

SYMBOL

PARAMETER

MIN.

MAX.

tCYC

Clock Cycle Time

320

ns

T1

ClK Pulse Width

80

ns

T2

ClK Pulse Width

120

ns

tf,t,

ClK Rise and Fall Time

tAL

Address to latch Set Up Time

50

ns

tLA

Address Hold Time after latch

80

ns

tLC

latch to R EAD/WR ITE Control

tRD

Valid Data Out Delay from READ Control

tAD

Address Stable to Data Out Valid

tLL

latch Enable Width

tROF

Data Bus Float after READ

tCL

R EADIWR ITE Control to latch Enable

20

ns

tcc

R EADIWR ITE Control Width

250

ns

tow

Data In to WRITE Set Up Time

150

ns

two

Data In Hold Time After WR ITE

0

ns

twp

WR ITE to Port Output

tpR

Port Input Set Up Time

50

tRP

Port Input Hold Time

50

tRYH

READY HOLD TIME

0

tARY

ADDRESS (CEI to READY

tRY

Recovery Time between Controls

tROE

Data Out Delay from READ Control

30

100

400
100

CLOAO = 150 pF
(See Figure 3)

ns

ns
ns
ns

100

400

ns

ns
ns
ns

120

ns

160

ns

300

ns

10

ns

6·330

TEST CONDITIONS

ns
150

0

UNITS

150 pF load

8755

FIGURE 3. CLOCK SPECIFICATION FOR 8755

Aa·l0

~

K

ADDRESS

ADDRESS

tAD

ADo-7

)

t

ADDRESS

)

~---<

~----<

DATA

tLL~

~tAL_

CE

>-

V

ALE

iPROGJ/CE

ADDRESS

f--tlA-

\

J
~

-tRDE

---0-

tRDF

\

--

"I\.-

/
~tLe~

tow

f--tRD

I+- -two

f\-

tee

f--teL~
tRV

FIGURE 4. PROM READ, 1/0 READ, AND WRITE TIMING.

Please note that ffi must remain low for the entire cycle.
This is due to the fact that the programming enable
function common to this pin will disrupt internal data bus
levels if GE1 is taken high during the read.

6-331

8755

A. INPUT MODE

flOOR
lOR

PORT
INPUT

DATA' BUS

-

-

-

-

-

-)(

-------

--------------------

B. OUTPUT MODE

rOW
GLITCH FREE
_ _ _ _ _ _ _ _ _ _ ~-_~-~/OUTPUT
PORT
OUTPUT

DATA* - BUS
____ _

~

.JX'-____

- "_ _ _ _ _ _ _

*DATA BUS TIMING IS SHOWN IN FIGURE 4.

FIGURE 5. 1/0 PORT TIMING.

FIGURE 6. WAIT STATE TIMING (READY = 0).

6-332

Chapter 7

SUPPORT PRODUCTS

PROMPT 80 DESIGN AID

INTELLEC® PROMPT 80™.
8080 MICROCOMPUTER DESIGN AID
Simplifies microcomputing

Low Cost

Enter, run, debug and save machine language programs with calculator-like ease

PROM Programmer for 8708/2708/2704 UV
Erasable, Electrically Reprogrammable ROMs
(EPROMs)

Complete, fully-assembled microcomputer, including:

Integral keyboard and 16-digit display (no teletypewriter or CRT terminal required)

Standard 8080A on popular SBC
80/10 Single Board Computer
Memory 1 K byte RAM, 3K byte ROM, and
two spare 1 K byte 8708 EPROMs
24 programmable parallel I/O (TTL)
I/O
lines, including two:
8-bit
ports,
fully
implemented
switches, displays
Programmable serial I/O interfaces
directly with most terminals
Only 110 or 230 VAC required
Power

CPU

Extensive system monitor software in ROM:
Examine/Display/Modify
Registers and Memory
Enter, Run, Test, Single-Step programs
Hex Calculator
Move, Search Memory Blocks
Self-programmable - user can add functions
Comprehensive design library

Intellec® PROMPT 80™ is a low-cost, fully assembled microcomputer design aid. PROMPT 80 simplifies the programming of
SBe 80 and System 80 microcomputers, as well as 8080 processors, 8708/2708/2704 EPROMs and 8255/8251 programmable I/O devices. 8080 programs can be entered and debugged with calculator-like ease on the large, informative display and
keyboard panel. The comprehensive design library with tutorial manual is ideal for newcomers to microcomputing.
PROMPT 80's SBe 80/10 can be expanded using the SBe modular cardcage. And PROMPT 80 can serve as an economical
8708 Specialized PROM Programmer (SPP) peripheral in Intellec Microcomputer Development Systems.

7-2

INTELLEC PROMPT 80 T .M .
PROMPT SIMPLIFIES MICROCOMPUTING

A COMPLETE COMPUTER

Intellec PROMPT 80 simplifies the programming of 8080
processors, SBC 80 and System 80 microcomputers, as
well as 8708 EPROMs and 8255/8251 programmable I/O
devices.

The heart of PROMPT 80 is the popular SBC 80/10 Single
Board Computer, a complete computer on a single printed
circuit board. The SBC 80/10 includes an 80~OA, 1K
bytes of static RAM memory, and sockets for 4K bytes of
EPROM memory. Signals to the SBC 80/10 include 48
programmable, parallel I/O lines with sockets for interchangeable line drivers and terminators, a programmable
serial channel, a multi-source single level interrupt network, and bus drivers for memory and I/O expansion.
Read-only-memory may be added in 1K byte increments
using Intel 8708 EPROMs or 8308 ROMs.

PROMPT is a low,cost programming tool. It is a microcomputer design aid - not a development system with
sophisticated software and peripherals.
PROMPT encourages the preparation and verification of
small, modular routines which together may comprise
sizable programs. These are written in assembly language,
then entered in machine language and debugged with
calculator-like ease on the large, informative display and
keyboard panel.

The central processor for PROMPT's SBC 80/10 is Intel's
powerful 8-bit n-channel MOS 8080A CPU. The 8080A
contains six 8-bit general-purpose registers and an accumulator. The six general-purpose registers may be addressed
individually or in pairs, providing both single and double
precision operations.

Many 8080 operations can be specified with only two
key strokes. Once entered, programs can be exercised one
instruction (single step) or many instructions at a time.
And, any of the 8080 registers can be watched while
si ngle-steppi ng.

The 8080A has a 16-bit address bus which allows direct
addressing of up to 64K bytes of memory. An external
stack, located anywhere in read/write memory, may be
used as a last-in/first-out store. The contents of the program counter, accumulator, flags, and all of the generalprupose registers are stacked using a 16-bit pointer. Subroutine nesting is bounded only by memory size.

Programs are readily saved and instantly reloaded via UV
Erasable, Electrically Reprogrammable ROMs (EPROMs).
PROMPT 80 can program the popular 8708 EPROMs in
small blocks, so routines can be debugged and saved
incrementally. Several programs are pre-recorded as
examples on PROMPT's spare 8708 EPROMs.
PROMPT 80 is a complete, fully assembled and powered
8080 microcomputer, including RAM, I/O, and system
monitor in ROM. Twenty-four lines of programmable,
TTL-compatible, parallel I/O are easily accessed on a
panel connector. Two 8-bit ports are fully implemented,
one with displays for output, the other with displays and
switches for input. PROMPT's programmable serial I/O
interfaces directly with most terminals. A teletypewriter
or CRT can be used, but neither is required because of
PROMPT's built-in keyboard and display.

EXPANDING PROMPT 80™

The PROMPT 80 manual includes chapters for the reader
with little or no programming experience. Topics treated
range from the 'number system to microcomputer hardware design. A novel, unifying set of tutorial diagrams MICROMApTM - simplify microcomputer concepts.

PERIPHERALS
&MEMQRY

B/

CENTRAL
PROCESSOR

:: B~IL-__--II
FFFF

0000

MEMORY

PROMPT 80's SBC 80/10 can be expanded via the SBC
604 Modular Cardcage. The cardcage houses the SBC
80/10 and up to three expansion boards. Memory and I/O
can be added in various combinations. Additional power
may be required.

A

OTHER
REGISTERS

~

PROMPT's handy, pocket-sized reference cardlet can be
affixed to the mainframe. Programming pads aid in the
organization and documentation of programs. These
features, plus a comprehensive design library of manuals,
articles, and applications notes, make Intellec PROMPT
80 ideal for the newcomer tomicrocomputing.

A Specialized PROM Programmer kit, the PROMPT-SPP.
allows PROMPT 80 to serve as an economical 8708 Specialized PROM Programmer peripheral in Intellec Microcomputer Development Systems. The PROMPT-SPP cable
plugs directly into the rear panel of the Intellec Microcomputer Development System.
7-3

INTELLEC@ PROMPT 80

PROM PROGRAMMER
8708 UV Erasable, Electrically Reprogrammable ROMs
(EPROMs) can be easily programmed, compared, and
transferred to RAM using the zero-insertion force socket
on the panel. A new technique allows 8708 to be partially
programmed in mUltiple blocks of 16 bytes. Thus, small,
modular routines can be entered, tested, and readily saved
using EPROM. EPROMs can also be conveniently duplicated. The master
(original) device plugs into the SBC 80/10 inside PROMPT
80, and can be copied to the panel programming socket.

REGISTER/DISPLAY GROUP
All 8080 registers can be displayed, even while singlestepping programs. The registers are shown in three rows:
first row:

B

C

D

E

second row:

H

L

Flags

A

third row:

Program Counter

Stack Pointer

One register row is visible at a time. Three small LEDs to
the left of these rows indicate which row is displayed. The
SCROLL REGISTER DISPLAY command displays the
next row (first, second, third, etc.)

RESET,INTERRUPTS
SYS RST resets the system, initializes the PROMPT 80
registers and enters the monitor. MON INT interrupts a
uSer program and enters the monitor saving the user
registers. USR INT is a user interrupt which traps
PROMPT 80 to location 3C0216.

MONITOR
A comprehensive system monitor resides in three 1 K
ROMs. It' drives PROMPT's keyboard, displays, and
responds to COMMANDS and FUNCTIONS. The monitor is modular, organized so that the third ROM may be
removed if F FUNCTIONS are not required. This allows
sizable user routines - as much as 2K ROM/EPROM and
nearly 1 K RAM - to be exercised.

COMMANDS
PROMPT 80 commands are compatible with those used
by Intel's SDK, SBC, and Intellec monitors.
You can EXAMINE/MODIFY a REGISTER, or DISPLAY/MODIFY ME:MORY. Then either the NEXT or
PREVIOUS register and memory locations can be opened
with one button.
The GO command executes programs, allowing multiple,
optional breakpoints. Or a program can be SI NG LE
STEPped, executed one instruction at a time.
The SCROLL REGISTER DISPLAY command displays
the next row of the REGISTER/DISPLAY GROUP.

7-4

INTELLEC® PROMPT 80
INPUT/OUTPUT GROUP
The INPUT/OUTPUT (I/O) GROUP features two fully
implemented 8-bit ports, both with displays, and with
latch switches for the input port E9. The port addresses
are clearly marked E8 and E9. Those two ports and a
third, at EA, are easily accessible on the I/O PORTS
CONNECTOR. Negative true logic is used throughout the
I/O GROUP and PORTS CONNECTOR to enhance noise
immunity and allow wire-ANDing.
PARALLEL I/O
The I/O PORTS CONNECTOR provides easy access to 24
parallel, TTL-compatible lines. These lines are addressed
as three ports (each 8 lines), port E8, E8, and EA.
These ports can be defined to be input or output by software. Defining control words, tabulated in "Specifications", are sent OUT to port EB, the control word register.
SERIAL I/O
PROMPT's programmable serial I/O readily interfaces
with most terminals. Jumpers select either 20 mA teletypewriter (TTY) current loop or RS-232C operation, and
the appropriate communications frequency. Asynchronous or synchronous transmission, data format, control
characters, parity, and transmission rate can be programmed.
A serial cable kit, PROMPT-SER, connects PROMPT to
either a teletypewriter or RS-232C standard (CRT) terminal through a rear chassis access slot. Teletypewriters may
require minor reader control modifications.
COMMAND/FUNCTION DISPLAYS
The COMMAND/FUNCTION displays show addresses and
data when DISPLAYing MEMORY, and parameters for
COMMANDS and FUNCTIONS are entered.
FUNCTIONS
Eight FUNCTIONS are provided by PROMPT. Others
may be added by the user. Pressing a HEX DATA/FUNCTIONS key (0-7) starts a function.

Commands are entered natural,y, like phrases in a sentence: the NEXT parameters are separated bycommas 0
and command sentences end with [] EXECUTE/END.
The commands do what makes sense. For example:
GO D ITl liilliil [] EXECUTE/END
starts the program at address 100.
GO D ITlliillQJ 0 NEXT I2J IQJ IQJ [] EXECUTE/END
starts the program at 100, but stops if you get to 200,
a breakpoint.
GO D [] EXECUTE/END
starts the program where you last stopped.
7-5

IQJ

is

FO

Read Paper Tape

ITl
I2J

is

F1

Write Paper Tape

is

F2

Program EPROM, Compare

[;j]

is

F3

Compare EPROM

~

Transfer EPROM to RAM

is

F4

!ill is
Ilil is
I1J is

F5

Move Block Memory

F6

Hexadecimal Calculator, +,-

F7

Byte Search Memory, optional mask

IjjJ

F8

Word Search Memory, optional mask

is

INTELLEC® PROMPT 80 T .M .
SPECIFICATIONS
COMMANDS
Examine/Modify Register
Go Iwith optional breakpoints)
Scroll Register Display
Next GJ

WORD SIZE

Instruction: 8,16, or 24 bits
Data:
8 bits
TIMING

Basic Instruction: 1.951Jsec
Cycle Time:
Clock:

tey = 488 nsec
2.058 MHz ± 0.1%

MEMORY BYTES
ROM/PROM
RAM

Addressing
On Board
0-OFFF 16
4096
3COO-3FFF 16
1024

FUNCTIONS
IQ] Read Tape
III Write Tape
GU Program EPROM, Compare
QJ Compare EPROM
I1l Transfer EPROM to RAM
[§] Move Block Memory
f[] Hexadecimal Calculator, +,121 Byte Search Memory, optional mask
!ill Word Search Memory, optional mask

Monitor Uses
2048 or 3072
114

Up to 48K bytes may be added using optional RAM, ROM, or
PROM expansion boards and the SBC 604 Cardeage.
I/O ADDRESSING
Ports E4 to E7 are dedicated to PROMPT's display/keyboard
groups. Ports E8 to EB drive the panel I/O PORTS CONNECTOR and PROM SOCKET.
Dedicated to
Display/Keyboard

I I I

ABC
PORT

E4

I E5 I E6 I

Control
E7

I/O Ports Connector/
PROM Socket

I I I

ABC

E8

Control

I E9 IEA I E B

Serial 1/0
USART

Data

I

EC

I

Con-

trol
ED

PARALLEL I/O
The panel I/O ports can be defined input or output by OUTputing control words to port address EB.
HEX Control Word

(OUT this to EBI

Port E8
Bits 7-0

Port E9
Bits 7-0

80

OUTPUT

OUTPUT

OUTPUT

81

OUTPUT

OUTPUT

OUTPUT

INPUT

82

OUTPUT

INPUT

OUTPUT

OUTPUT

83

OUTPUT

INPUT

OUTPUT

INPUT

84 or 86

OUTPUT

85 or 87

OUTPUT

STROBED
OUTPUT
STROBED

INPUT

SOFTWARE DRIVERS
Panel Keyboard Input
Console Terminal Input
TTY Reader Input

Panel Display Output
Console Terminal Output
TTY Punch Output

CONNECTORS
PROMPT Panel I/O Ports
SBC 80/10 Parallel I/O
SBC 80/10 Serial I/O
SBC 80/10 Bus
SBC 80/10 Auxil iary Bus

3M 3425 Flat
3M 3415 Flat
3M 3462 Flat
CDC VPB01 E43DOOA 1
TI H312130

EQUIPMENT SUPPLIED
PROMPT 80 mainframe with SBC 80/10, display/keyboard,
PROM Programmer, power supply, cabinet, and ROM-based
system monitor
12) 8708 EPROMs with pre-recorded example programs
110 V AC power cable, 110 or 220 VAC fuse
PROMPT 80 User's Manual, PROMPT 80 Monitor Listing
PROMPT 80 Reference Cardlist, PROMPT 80 Programming
Pads
8080 Systems User's Guide, 8080 Assembly Language Manual
System 80/10 Hardware Reference Manual
Design Library of Application Notes, Article Reprints
PROMPT 80 Schematics

Port EA
Bits 7-4
Bits 3-0
OUTPUT

OUTPUT
OUTPUT

Display /Modify Memory
Single Step
Open Previous/Clear Entry
[J Execute/end

Bits 2,1,
strobes

a are

ORDERING INFORMATION, COMPATIBLE EQUIPMENT
PROMT-80 - Complete PROMPT 80 set 110 VAC
PROMT-80-220V - Complete PROMPT 80 set 220 VAC
PROMT-SER - Serial Cable connects PROMPT to TTY, CRT
PROMT-SPP - Specialized PROM Programmer Kit connects
PROMPT 80 to Intellec® Microcomputer Development
Systems for 8708 EPROM programming.
All SBC products ladditional memory, I/O, wire-wrap, and
other boards) are compatible with PROMPT's SBC 80/1 O.
Additional PROMPT 80 Programming Pads can be ordered
from Intel Literature Department.

All input ports are TTL~compatible, Ports E8 and EA are one~
load fully TTL-compatible as output. Port E9 is ordinarily
used as input. When used as output, E9 can sink at least one
low-power TTL load.
SERIAL I/O
The serial I/O port is defined by software and jumpers.
PROMPT is configured at the factory for 20 mA current loop
TTY interface, but can easily be jumpered for RS-232C levels.
Asynchronous or synchronous transmission, data format,
control characters, parity and transmission rate can be programmed.

PHYSICAL CHARACTERISTICS
Maximum Height: 13.5 em
15.3 in.)
Width:
43.2 cm
117 in.)
Maximum Depth: 43.2 cm
117 in.)
Weight:
9.6 kg
121 Ib)

INTERRUPTS
PROMPT 80 provides a panel user interrupt to 3C02 16 . The
SBC 80/10 supports single level vectoring to location 38 16.
Requests may originate from user-specified I/O 12), the parallel
ports 12), or serial port 12).

ELECTRICAL REQUIREMENTS
Either 115 or 230 VAC 1±10%) may be switch-selected on the
mainframe. 1.8 amps max current lat 125 VAC)
Frequency is 47-63 Hz.

EPROM PROGRAMMI'NG
8708/2708/2704 EPROMs can be programmed in multiple
blocks of 16 bytes. Starting and ending memory address need
only differ by a multiple of 16, and starting EPROM address
end XXO hexadecimal IX = don't care). Programming time is
115 sec for 1 K byte, 3 sec for 16 bytes.

Voltage
+26.5
+12
+ 5

The 8708 may be erased by exposure to high intensitY shortwave ultraviolet I ight at a wavelength of 2537 A. The recommended integrated dose (UV intensity X exposure time) is
10 W-see/cm 2 .

- 5
-12

SYSTEM MONITOR
Resides in three 8308 ROMs, 0 to 3FF 16 , 400 1 6 to 7FF 1 6,
and 800 16 to BFF 16 . The third ROM implements F FUNCTIONS, and can be removed. PROMPT has an unused ROM/
EPROM socket at address C00 16 to F F F 16.

Internal PROMPT 80
Supply

PROMPT 80 ReqUires

0.1A
1.2A
6.0A
0.3A
0.3A

0.03A
0.5A
5.0A
O.lA
0.2A

Fixed over-voltage protect on 5V supply 6.2-6.7 volts.
ENVI RONMENTAL
Operating Temperature:
10°C to 40°C
Non-operating Temperature: -20°C to 65°C

7-6

INTELLECCY
MICROCOMPUTER DEVELOPMENT SYSTEM
Modular microcomputer development system for
development and implementation of MCST M -80
and Series 3000 Microcomputer Systems

Optional PROM programmer peripheral capable of
programming all Intel PROMs
ICE (In-Circuit Emulator) options extend Intellec
MDS diagnostic capabilities into user configured
system allowing real-time emulation of user processors

Intel® 8080 microprocessor, with 2 /lS cycle time
and 78 instructions, controls all Intellec MDS
functions

Optional I/O modules expandable in groups of four
8-bit input and output ports to a maximum of 88
ports (all TTL compatible)

16K bytes RAM memory expandable to 64K bytes
2K bytes ROM memory expandable to 14K bytes

ROM resident system monitor includes all necessary functions for program loading, debugging, and
execution

Hardware interfaces and software drivers provided
for TTY, CRT, line printer, high-speed paper tape
reader, high-speed paper tape punch, and Universal
PROM Programmer

RAM resident macro assembler used to assemble all
8080 machine instructions with full macro and
conditional assembly capabilities

Universal bus structure with multiprocessor and
DMA capabilities

RAM resident text editor with powerful string
search, substitution, insertion, and deletion commands

Eight level nested, maskable, priority interrupt
system

The I ntellec® MDS is a modular microcomputer development system containing all necessary hardware and software to develop
and implement Intel MCS T .M ·_80 and Series 3000 microcomputer systems. The addition of MDS options and peripherals provides
the user with a complete in-circuit microcomputer development system, supporting product design from program development
through prototype debug, to production and field test.

7-7

i

r

\
INTELLEC HARDWARE

indicators, a bootstrap loader switch, RESET switch, and a
POWER ON switch and indicator.

The standard Intellec® MDS consists of four microcomputer modules (CPU, 16K RAM Memory, Front Panel Control, and Monitor), an interconnecting printed circuit
motherboard, power suppl ies, fans, a chassis, and a front
panel. Modular expansion capability is provided by 14
additional sockets on the motherboard_

The basic Intellec MDS capabilities may be significantly enhanced by the addition of the following optional features.
ICE (In-Circuit Emulator) extends Intellec MDS diagnositc
capabilities into user configured systems. The Intellec MDS
resident ICE processor operates in conjunction with the
MDS host CPU and interfaces to the user system via an external cable. The ICE processor replaces the user system
processor providing real time emulation capability. MDS
resident memory and I/O may be substituted for equivalent
user system elements, allowing the hardware designer to
sequentially develop his system by integrating MDS and user
system hardware. MDS display and debug hardware eliminate the need for specially constructed user system equivalents. Augmenting these capabilities are such powerful ICE
debug functions as setting breakpoints, tracing program
flow, single stepping, examining and altering CPU registers
and memory locations.

The CPU module uses Intel's powerful NMOS 8-bit 8080
microprocessor. The 8080's 2 f..lS cycle time, 78 instructions, unlimited subroutine nesting, vectored interrupt, and
DMA capabilities are fully utilized by the Intellec MDS_
8us control logic resolves bus contention conflicts between
the CPU module and other modules capable of acquiring
control of the bus_ The CPU module interfaces with a sixteen line address bus and a bidirectional eight line data bus_
8080 status signals are decoded and utilized for memory
and I/O operations_ An eight-level, nested interrupt priority
system, complete with an interrupt priority push-down
stack, resolves contention for 8080 interrupt servicing_

The Universal PROM Programmer is an Intellec MDS peripheral capable of programming and verifying the following
Intel PROMs: 1702A, 2704, 2708, 3601, 3604, 3624,
8702A, 8704, and 8708. Programming and verification
operations are initiated from the Intellec MDS system console and are controlled by programs resident in the Intellec
MDS and Universal PROM Programmer.

The RAM memory module contains 16K bytes of Intel
2107A dynamic RAM which operates at full processor
speed_ All necessary address decoding and refresh logic is
contained on the module.
The front panel control module provides system initialization, priority arbitration, and real time clock functions.
System initialization routines reside in a 256 byte, PROM
resident, bootstrap loader. An eight-level priority arbitration network resolves bus contention requests among potential bus masters. Alms interrupt request generator, which
can be disabled under program control, provides real time
clock functions. A 10 ms automatic time-out feature is also
provided to force an interrupt request if nonexistent memory or I/O is addressed.

The addition of a single or dual drive Diskette Operating
System significantly reduces program development time.
An intelligent controller, constructed around Intel's powerful Series 3000 computing elements, provides diskette
interface and control. Intel's software operating system
(I DOS) in conjunction with the diskette operating system
hardware provides a highly efficient and easy to use method
of assembling, editing, and executing programs.

The Monitor module contains the Intellec MDS system
monitor and all Intellec MDS peripheral interface hardware.
The system monitor resides in a 2K byte Intel 8316 ROM.
The module contains all necessary control and data transfer
circuitry to interface with the following Intellec MDS
peripherals:

Customized user I/O requirements may be satisfied by
adding I/O modules. Each I/O module contains four 8-bit
input ports (latched or unlatched), four 8-bit latched output ports (with adjustable strobe pulses), and eight system
interrupt lines. All inputs and outputs are TTL compatible.
Optional I/O may be expanded to a maximum of 44 input
and 44 output ports.

• Teletype
• CRT
• High Speed Paper Tape Reader
• High Speed Paper Tape Punch
• PROM Programmer
• Line Printer

Memory may be expanded by adding RAM or PROM modules in user defined combinations. Up to 64K bytes of RAM
may be added in 16K byte increments. PROM (Intel 8702A)
may be added in 256 byte increments by adding PROM
modules with socket capacity for 6K bytes and populating
each module with the desired number of PROMs. Maximum
PROM capacity is 12K bytes. RAM/PROM memory overlap
is resolved by giving PROM priority.

The Intellec MDS universal bus structure enables several
CPU and DMA devices to share the bus by operating at different priority levels. Resolution of bus exchanges is synchronized by a bus clock signal which is derived independently from processor clocks. Read/write transfers may take
place at rates up to 5 MHz. The bus structure contains provisions for up to 16-bit address and data transfers and is not
limited to anyone Intel microcomputer family.

DMA (direct memory access) modules work in conjunction
with the Inteliec MDS universal bus to maximize the efficiency of data transfers between MDS memory and selected
I/O devices. Each module contains all the necessary control
and data transfer logic to implement a complete DMA
channel.

The Intellec MDS front panel is intended to augment the
primary user interaction medium, the system console. The
simplicity of the front panel coupled with the power of the
system monitor provides an efficient user/lntellec interface.
The front panel contains eight interrupt request switches
with corresponding indicators, CPU RUN and HALT status

A ROM simulator composed of high speed bipolar RAM
emulates Series 3000 bipolar microprogram ROM memory_
Each ROM simulator module may be used in 512 X 16 or
1024 X 8 configurations.

7-8

i,
INTEllEC SOFTWARE

Conditional assembly permits the assembler to include or
delete sections of code which may vary from system to
system, such as the code required to handle optional
external devices.

Resident software provided with the Intellec MDS includes
the system monitor, 8080 macro assembler and text editor.
Used together, these three programs simplify program
preparation and speed the debugging task.

The assembler performs its function in three passes. The
first pass builds the symbol table. The second pass produces a source listing and provides error diagnostics. The
third pass produces the object code. If the punch and list
devices are separate (e.g. a high speed punch or printer is
available) passes 2 and 3 may be combined into one pass.

The system monitor provides complete control over operation of the Intellec MDS. All necessary functions for program loading and execution are provided. Additional commands provide extensive debug facilities and PROM programming functions. System peripherals may be dynamically assigned either via monitor commands or through calls
to the system monitor's I/O subroutines.

Object code produced by the assembler is in hexadecimal
format. It may be loaded directly into the Intellec MDS for
execution and debugging or may be converted by the system monitor to BNPF format for ROM programming.

Programs may be loaded from the reader device in either
BNPF or hexadecimal format. Utility commands which aid
in the execution and checkout of programs include:
•
•
•
•
•
•
•
•
•

The assembler is written in Pl/M T .M ·_80, Intel's high level
systems programming language. It occupies 12K bytes of
RAM memory including space for over 800 symbols. The
symbol table size may be expanded to a maximum of 6500
symbols by adding RAM memory. All I/O in the assembler
is done through the system monitor, enabling the assembler
to take advantage of the monitor's I/O system. The assembler is shipped in hexadecimal object format on paper tape
or diskette and is standard with each Intellec MDS.

initialize memory to a constant
move a block of memory to another location
display memory
modify RAM memory
examine and modify CPU registers
set breakpoints
initiate execution at any given address
perform hexadecimal arithmetic
examine and modify the interrupt mask

The Intellec MDS editor is a comprehensive tool for the
entry and correction of assembly language programs for the
Intel 8080 microcomputer. Its command set allows manipulation of either entire lines of text or individual characters
within a line.

The Intellec MDS System Monitor contains a powerful and
easily expandable input/output system, which is built
around four logical device types; console device, reader
device, punch device and list device. Associated with each
logical device may be anyone of four physical devices. The
user controls physical device assignment to each logical
device through a System command.

Programs may be entered directly from the console keyboard or from the system reader device. Text is stored
internally in the editor's workspace, and may be edited
with the following commands:

Drivers are provided in the system monitor for the Universal
PROM Programmer, ASR 33 teletype, high speed paper
tape reader, high speed paper tape punch, line printer, and
CRT. The user may write his own drivers for other peripheral devices and easily link them to the system monitor.

• string insertion or deletion
• string search
• string substitution
To facilitate the use of these editing commands, utility
commands are used to change positions in the workspace.
These incl ude:

All system peripherals may be accessed simply by calling
I/O subroutines in the system monitor. In addition, the user
may dynamically reconfigure his system by monitor commands or by calling system subroutines which can assign a
different physical device to each logical device. The user
may also determine the current system peripheral configuration, check I/O status and determine the size of available
memory.

• move pointer by line or by character
• move pointer to start of workspace
• move pointer to end of workspace

The monitor is written in 8080 Assembly language and
resides in 2K bytes of ROM memory.

The contents of the workspace may be listed to the system
console or written to the system Iist or punch device for
future use.

The Intellec MDS Resident Assembler translates symbolic
8080 assembly language instructions into the appropriate
machine operation codes. In addition to eliminating the
errors of hand translation, the ability to refer to program
addresses with symbolic names makes it easy to modify
programs by adding or deleting instructions. Full macro
capability eliminates the need to rewrite similar sections of
code repeatedly and simplifies program documentation.

The text editor is written in Pl/M T.M·_ 80. It occupies 8K
bytes of RAM memory, including over 4500 bytes of workspace. The workspace may be expanded to a maximum of
58K bytes by adding RAM memory. All I/O in the editor is
done through the system monitor, enabling the editor to
take advantage of the monitor's I/O system. The editor is
shipped in hexadecimal object format on paper tape or
diskette and is standard with each Intellec MDS.

7-9

INTELLEC® BLOCK DIAGRAM
r-------------------------~--------------.--------------,

6
7
8.
9
10,

11.
12.
13.
14

HARDWARE SPECIFICATIONS
WORD SIZE
Host Processor (I ntel BOBO)
Data: 8 bits
Instruction, B, 16, or 24 bits
MEMORY SIZE
RAM:
16K bytes expandable to 64K bytes using optional
modules.
ROM:

2K bytes expandable to 14K bytes in 256 byte
increments using optional PROM modules.

PROM: 256 bytes expandable to 12K bytes using optional
modules.
Total:
RAM, ROM and PROM may be combined in user
defined configurations up to a maximum of 64K
bytes.
MACHINE CYCLE TIME
Host Processor (Intel BOBO): 2.0/1S
BUS TRANSFER RATE
Maximum bus transfer rate of 5 MHz.
SYSTEM CLOCKS
Host Processor (Intel BOBO) Clock: Crystal controlled at
2 MHz±O.l%.
Bus Clock: Crystal controlled at 9.B304 MHz ±0.1%.
I/O INTERFACES
CRT:
Baud Rates:
110/300/600/1200/2400/4BOO/9600
(selectable) .
Code Format: 7-12 level code (programmable).
Parity:
Odd/even (programmable).
Interface:
TTL/RS232C (selectable).
TTY:
Baud Rate:
Code Format:
Input:
Output:
Parity:
Interface:

110
10 level or greater.
11 level.
Odd.
20 mA current loop.

High Speed Paper Tape Reader:
Transfer Rate: 200 cps.
Control:
2-bit output.
l-bit input.
Data:
B-bit byte
I nterface:
TTL
Punch:
Transfer Rate: 75 cps
Control:
2-bit output
l-bit input
Data:
B-bit byte
; ilterface:
TTL

TTY DATA/STATUS'COMMANDS
FRONT PANEL STATUS/SWITCH iNPUTS
USER SYSTEM CPU OR Meu PIN SIGNALS
USER SYSTEM ROM PIN SIGNALS
EIGHT INTERRUPT LINES
FOUR S-SH OUTPUT PORTS
FOUR S-SIT INPUT PORTS
OMA DEVICE DATA/STATUS/COMMANDS
DISKETTE DRIVE DATA/STATUS/COMMANDS

Printer:
Transfer Rate: 165 cps
Control:
2-bit status input
l-bit output
Data:
ASCII
Interface:
TTL
PROM Programmer:
Control:
3 strobes for multiplexed output data.
Data:
B-bit bidirectional
I nterface:
TTL
GENERAL PURPOSE I/O (OPTIONAL)
Input Ports: B-bit TTL compatible (latched or unlatched);
expandable in 4 port increments to 44 input
ports.
Output Ports: B-bit TTL compatible (latched); expandable
in 4 port increments to 44.
Interrupts:
B TTL compatible interrupt lines.
INTERRUPT
B-Ievel, maskable, nested priority interrupt network initiated from front panel or user selected devices.
DIRECT MEMORY ACCESS
Standard capability on Intellec bus; implemented for user
selected DMA devices through optional DMA module maximum transfer rate of 2 MHz.
MEMORY ACCESS TIME
RAM: 450 ns
PROM: 1.3/1s using IntelB70BA PROM.
PHYSICAL CHARACTERISTICS
Dimensions: B.5" X 19" X 17"
21.6 cm X 4B.3 cm X 43.2 cm
Weight:
65 Ib (29.5 kg)
ELECTRICAL CHARACTERISTICS
DC POWER
SUPPLY

POWER SUPPLY
CURRENT

(Volts)

(Amps)

+ 5 ±5%
+12 ±5%
-10 ±5%
-12 ±5%

BASIC SYSTEM CURRENT
REQUIREMENTS
(Amps)

Maximum

Typical

9.0
0.7
0.2

6.6
0.4
0.2

35.0
3.0
3.0
0.5

AC POWER REQUIREMENTS
50-60 Hz; 115/230 VAC; 150 Watts
ENVIRONMENTAL CHARACTERISTICS
Operating ., emperature: 0 to 55°C

SOFTWARE SPECIFICATIONS

MDS OPTIONS
MDS-016 16K Dynamic RAM
MDS-406 6K PROM (sockets and logic)
DMA Channel Controller
MDS-501
MDS-504 General Purpose I/O Module
MDS-600 Prototype Module
MDS-610 Extender Module
MDS-620 Rack Mounting Kit

CAPABILITIES
System Monitor:
Devices supported include:
ASR 33 teletype
Intel high speed paper tape reader
Paper tape punch
CRT
Printer
Universal PROM programmer
4 logical devices recognized
16 physical devices maximum allowed

MDS EMULATORS/SIMULATOR
MDS-ICE-30
3001 In-Circuit Emulator
MDS-ICE-80
8080 In-Circuit Emulator
MDS-SIM-100 Bipolar ROM Simulator

Macro Assembler:
800 symbols in standard system; automatically expandable with additional RAM memory to 6500 symbols
maximum.

MDS PERIPHERALS
MDS-UPP Universal PROM Programmer
MDS-PTR High Speed Paper Tape Reader
MDS-DOS Diskette Operating System

Assembles all seventy-eight 8080 machine instructions
pi us 10 pseudo-operators.

MDS INTERFACE CABLES/CONNECTORS
MDS-900 CRT Interface Cable
MDS-910 Line Printer Interface Cable
MDS-915 High Speed Reader Interface Cable
MDS-920 High Speed Punch Interface Cable
MDS-930 Peripheral Extension Cable
MDS-940 DMA Cable
MDS-950 General Purpose I/O Cable
MDS-960 25-pin Connector Pair
MDS-970 37-pin Connector Pair
MDS-980 60-pin Motherboard Auxiliary Connector
MDS-985 86-pin Motherboard Main Connector
MDS-990 100-pin Connector Hood

Text Editor:
12K bytes of workspace in standard system; automatically expandable with additional RAM memory to
58K bytes.

OPERATIONAL ENVIRONMENTAL
System Monitor:
Required hardware:
Intellec MDS
331 bytes RAM memory
2K bytes ROM memory
System console
Macro Assembler:
Required hardware:
I ntellec M DS
12K bytes RAM memory
System console
Reader device
Punch device
List device

EQUIPMENT SUPPLIED
Central Processor Module
RAM Memory Module
Monitof Module (System I/O)
Front Panel Control Module
Chassis with Motherboard
Power Supplies
Finished Cabinet
Front Panel
ROM Resident System Monitor
RAM Resident Macro Assembler
RAM Resident Text Editor
Hardware Reference Manual
Reference Schematics
Operator's Manual
8080 Assembly Language Programming Manual
System Monitor Source Listing
8080 Assembly Language Reference Card
TTY Cable
European AC Adapter
AC Cord

Required software:
System monilor
Text Editor:
Required hardware:
Intellec MDS
8K bytes RAM memory
System console
Reader device
Punch device
Required software:
System monitor
Tape Format:
Hexadecimal object format.

7-11

ICE-80 8080
IN-CIRCUIT EMULATOR
Connects Intellec® MDS to user configured system
via an external cable and 40-pin plug, replacing the
user 8080

Offers full symbolic debugging capabilities

Allows real-time (2 MHz) emulation of the user
system 8080

Provides address, data and 8080 status information
on last 44 machine cycles emulated

Allows user configured system to share Intellec®
MDS RAM, ROM and PROM memory and Intellec® MDS I/O facilities

Provides capability to examine and alter CPU registers, main memory, pin and flag values

Checks for up to three hardware and four software
break conditions

Eliminates the need for extraneous debugging tools
residing in the user system
.

Integrates hardware and software development
efforts
Available in diskette or paper tape versions

The Intellec® MDS In-Circuit Emulator/80 (lCE-80) is an Intellec® MDS resident module that interfaces to any user configured 8080 system. With ICE-80 as a replacement for a prototype system 8080, the designer can emulate the system's 8080 in
real time, single-step the system's program, and substitute Intellec® MDS memory and I/O for user system equivalents. Powerful Intellec® MDS debug functions are extended into the user system. For the first time the designer may examine and
modify his sytem with symbolic references instead of absolute values.

7-12

ICE-SO

INTEGRATED HARDWAREI
SOFTWARE
DEVELOPMENT

MEMORY AND
1/0 MAPPING
Memory and I/O for the user system can be resident in the
user system or "borrowed" from the MDS through
ICE-80's mapping capability.

The user prototype need consist of no more than an 8080
CPU socket and a user bus to begi n integration of software and hardware development efforts. Through ICE-80
mapping capabilities, MDS equivalents can be accessed for
missing prototype hardware. Hardware designs can be
tested Llsing the system software which will drive the final
product.

ICE-80 separates user memory into 16 4K blocks. User
I/O is divided into 16 16-port blocks. Each block of
memory or I/O can be defined independently. The user
may assign MDS equivalents to take the place of devices
not yet designed for the user system during prototyping.
In addition, proven MDS memory or I/O can be accessed
in place of suspect user system devices during prototype
or production checkout.

The system integration phase, which can be so costly and
frustrating when attempting to mesh completed hardware
and software products, becomes a convenient two-way
debug tool when begun early in the design cycle.

The user can also designate a block of memory or I/O as
nonexistent. ICE-80 issues error messages when memory
or I/O designated as nonexistent is accessed by the user
program.

SYMBOLIC DEBUGGING
ICE-80 allows the user to make symbolic references to
memory addresses and data in his program. Symbols may
be substituted for numeric values in any of the ICE-80
commands. The user is relieved from looking up addresses
of variables or program subroutines.
The user symbol table generated along with the object
file during a PL/M compilation or a MAC80 or MDS
assembly, is loaded to MDS memory along with the user
program which is to be emulated. The user may add to
this symbol table any additional symbolic values for
memory addresses, constants, or variables that are found
useful during system debugging. By referring to symbolic
memory addresses, the user can be assured of examining,
changing, or breaking at the intended location.
ICE-80 provides symbolic definition of all 8080 registers,
flags, and selected pins. The following symbolic references
are also provided for user convenience: TIMER, a 16-bit
register containin-g the number of 1>2 clock pulses elapsed
during emulation; ADDRESS, the address of the last
instruction emulated; INTERRUPTENABLED, the user
8080 interrupt mechanism status; and UPPER LIMIT, the
highest MDS RAM address that can be occupied by user
memory.

ICE·SO INSTALLED IN USER SYSTEM

REAL TIME TRACE

DEBUG CAPABILITY
INSIDE USER SYSTEM

ICE-80 captures valuable trace information while the user
is executing programs in real time. The 8080 status, the
user memory or port addressed, and the data read or
written (snap data), is stored for the last 44 machine
cycles executed. This provides ample data for determining
how the user system was reacting prior to emulation
break. It is available whether the break was user initiated
or the result of an error condition.

ICE-80 provides the user with the ability to debug a full
prototype or production system without introducing
extraneous hardware or software test tools.
ICE-80 connects to the user system through the socket
provided for the user 8080 in the user system. Intellec®
MDS memory is used for the execution of the ICE-80
software, while MDS I/O provides the user with the ability
to communicate with ICE-80 and receive information on
the operation of the user system.

For detailed information on the actions of CPU registers,
flags, or other system operations, the user may operate in
single or multiple-step sequences tailored to system debug
needs.

7·13

ICE-80
HARDWARE
MHz. The CPU can alternately be driven by a clock derived from user system signal lines. The clock source is
selected by a jumper option on the board. A timer on the
Trace Board counts the 40H
; ELSE RESTART WHOLE PROCEDURE

ISIS ICE-80, Vl.0
(j) "XFORM MEMORY 0 TO 1 U
'XFORM IO OFH U
~ 'LOAD PROG. HEX
ERR=067
STAT=ll H TYPE=06H CMND=07H ADDR=1320H GOOD=06H BAD=04H
'CHANGE MEMORY 1321 H=FFH
ERR~067

STAT=llH TYPE~06H CMND=07H ADDR~1321H
'LOAD PROG. HEX
@ 'GO FROM START UNTIL RSLT WRITTEN
EMULATION BEGUN

®

ERR~067

®

STAT=ll H TYPE=07H CMND=02H
'DISPLAY CYCLES 5

®

CV
®

1.

2.

STAT=A2H
STAT=82H
STAT=82H
STAT=04H

ADDR=1326H DATA~CDH
ADDR=1327H DATA~E3H
ADDR=1328H DATA=OlH
ADDR=FFFFH DATA=13H

STAT~04H

ADDR~FFFEH

GOOD~FFH

BAD=FDH

DATA~29H

'CHANGE DOUBLE REGISTER SP~13FFH
*8ASE HEX
'EOUATE STOP=1333H
*GO FROM START UNTIL STOP EXECUTED THEN DUMP
EMULATION BEGUN
B=OlH C=41H D=OOH E=OOH H=OOH L~OOH F~56H A=40H P=1320H *=1333H S=13FFH
EMULATION TERMINATED AT 1333H
'EXIT
'FFFF

Set up user memory and 1/0. The program is set up to execute in block 1 (1000H-1FFFH) of user memory, and requires access to the
SDK-80 monitor (block 0) and 1/0 ports in block OFH. Both ports and memory are defined as available to the user system. All other
memory and 1/0 is initialized by ICE-80 as nonexistent (guarded).
A load command generates an error. The type and command numbers indicate that a data mismatch occurred on a write to memory com-

mand. The data to be written to address 1320H should have been 06H. When ICE-80 read the data after writing it, a 04H was detected.
A change command to a different memory address hints that bit 1 does not go to 1 anywhere in this memory block. Examination

indi~

cates that a pin was shorted on the RAM located at 1300H-13FFH in the prototype system. The problem is fixed and a subsequent
load succeeds.
3.

A real-time emulation is begun. The program is executed FROM 'START' (1320H) and continues UNTIL 'RSL T' is written (in location
1328H, the contents of the accumulator is stored in (written into) 'RSLT').

4.

An error condition results: TYPE 07, CMND 02 indicate the program accessed a guarded area.

5.

The last 5 machine cycles executed are displayed. The last instruction executed was a call (CDH). The fourth and fifth cycles are a push
operation (designated by status 04H) to store the program counter before executing the call. The stack pointer was not initialized in the
program and is accessing memory location FFFFH.

6.

After making a note to initialize the stack pointer in the next assembly, a temporary fix is effected by setting the stack pointer to the top
of user available memory.

7.

After setting the base for displays to hex and adding the symbol 'STOP' to the symbol table, emulation is started which will terminate
when the instruction at 1333H ('STOP') is executed. When emulation terminates, a DUMP of the contents of user 80BO registers is
requested. One can see that the value of the accumulator is set at 40H, the stack pointer is set at 13FFH, the last address executed (*) is
1333H, and the program counter has been set to 1320H.

B.

EXIT returns control to the MDS monitor.

7-16

ICE-80
ICE80SD OPERATING ENVIRONMENT

SYSTEM CLOCK
Crystal controlled 2.185 MHz ±0.01%. May be replaced
by user clock through jumper selection.

Paper Tape-Based ICE80SD
Required Hardware:
Intellec@ MPS
System console
MDS Reader device
MDS Punch device
ICE-80
Required Software:
System monitor

PHYSICAL CHARACTERISTICS
Width: 12.00 in. (30.48cm)
Height: 6.75 in. (17.15cm)
Depth:
0.50 in. (1.27 cm)
Weight: 8.00 Ib (3.64 kg)

ELECTRICAL CHARACTERISTICS
DC Power:
+5V, ±5%
Vee
9.81A maximum; 6.90A typical
lec
+12V, ±5%
Voo
79 mA maximum; 45 mA typical
100
V BB = -9V, ±5%
IBB = 1 mA maximum; 1 J.lA typical

Diskette-Based ICE80SD
Required Hardware:
Intellec@MDS
32K bytes RAM memory
System console
MDS-DOS Diskette Operating System
ICE-80
Required Software:
System monitor
ISIS

ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: O°C to 40°C
Operating Humidity:
Up to 95% relative humidity
without condensation

EQUIPMENT SUPPLIED

CONNECTORS

Printed Circuit Modules (2)
Interface Cables and Buffer Board
Hardware Reference Manual
Operator's Manual
Schematic Diagram
ICE-80 Software Driver, paper tape version
(ICE-80 Software Driver, disketted-based version is
supplied with MDS Diskette Operating System)

Edge Connector: CDC VPB01 E32AOOA 1

ORDERING INFORMATION

7-17

Part Number

Description

MDS-80-ICE

8080 CPU In-Circuit Emulator. Cable
Assembly and Interactive Software included

i
i

!""

UPP UNIVERSAL PROM PROGRAMMER
Intellec® MDS peripheral capable of programming
the following Intel® PROMs: 1702A, 2704,2708,
3601,3604,3624, 8702A, 8704 and 8708

Flexible power source for system logic and programming pulse generation

Personality cards used for specific Intel® PROM
programming requirements

PROM programming verification facility

Zero insertion force sockets for both 16-pin and
24-pin PROMs

Stand-alone or rack-mountable

The Universal PROM Programmer is an I ntellec MDS peripheral capable of programming and verifying the following I ntel PROMs: .
1702A, 2704, 2708, 3601,3604,3624, 8702A, 8704, and 8708. Programming and verification operations are initiated from the
. I ntellec MDS system console and are controlled by programs resident in the I ntellec ·MDS and Universal PROM Programmer.
The basic MDS-UPP consists of a controller module, two personality card sockets, front panel, power supplies, chassis, and an
Intellec MDS interconnection cable. An Intel 4040 based intelligent controller monitors the Intellec MDS interface and controls
the command generation and data transfer interface between the selected PROM personality card and the I ntellec MDS. The 4040
CPU operates in conjunction with a fixed central control program residing in an Intel 4001 ROM. Each Intel PROM to be programmed is driven by a unique personality card which contains the appropriate pulse generation functions and driver circuitry.
Hence, programming and verifying any Intel PROM may be accomplished by selecting and plugging in the appropriate personality card option. The front panel contains a power-on switch and indicator, reset switch, and two zero-force insertion sockets
(one 16-pin and one 24-pin or two 24-pin). A central power supply provides regulated power for system logic and ±40 and +70
volts for PROM programming pulse generation.
PROM programming commands are initiated from the Intellec MDS system console and are implemented by programs in the
Intellec MDS. The desired PROM image is loaded into Intellec MDS RAM through a user selected input medium (e.g., TTY, diskette drive, high speed paper tape reader). Next, the PROM programming command is issued specifying the location of the programming data, the socket option, the "nibble" option (upper or lower four bits of an 8-bit RAM data byte), and PROM starting
address. The PROM programming algorithm programs each specified PROM location, compares the resulting PROM word with
the source data, and regenerates program pulses when necessary. The Intellec MDS system monitor contains a compare feature
which allows specified sections of programmed PROM to be compared with MDS resident RAM. A transfer feature which can be
used to copy the contents of a PROM to MDS RAM for PROM duplication is also included.
The Universal PROM Programmer may be used as a table top unit or mounted in a standard 19" R ETMA cabinet.

7-18

SPECIFICATIONS
INTERFACE
Data: Two 8-bit unidirectional buses
Commands: 3 Write Commands
2 Read Commands
Initiate Command

ENVIRONMENTAL CHARACTERISTICS
Operating Temperature: 0° to 70°C.
OPTIONS
Personality Cards:
MDS·UPP·361 :3601 Personality Card
MDS-UPP·864:8604/3604/3624 Personality Card
MDS-UPP·872:8702A/1702A Personality Card
MDS-UPP·878:8708/8704/2708/2704 Personality Card

AVERAGE PROGRAMMING TIME
1702A/8702A: 40 seconds
2708/8708:
5 minutes
3601 :
2 seconds
3604:
10 seconds
10 seconds
3624:
2704/8704:
2.5 minutes

PROM Programming Sockets:
MDS·UPP-501: 16·pin/24·pin pair
MDS-UPP-502: 24-pin/24·pin pair
EOUIPMENT SUPPLIED
Cabinet
Power Suppl ies
4040 Intelligent Controller Module
Specified Zero I nsertion Force Socket Pair
I ntellec M DS I nterface Cable
Hardware Reference Manual
Reference Schematics

PHYSICAL CHARACTERISTICS
Dimensions: 6" X 7" X 17"
14.7 cm X 17.2 cm X 41.7 cm
Weight: 18 Ib (8.2 kg)
ELECTRICAL CHARACTERISTICS
DC Power Supplies:
Voltage

Current

5V
-10V
±40V
70V

2.5A
0.75A
0.5A
O.4A

AC Power Requirements:
50-60 Hz; 115/230 VAC; 80 Watts

7-19

INSTRUMENTATION AND TEST SYSTEMS

j-LSCOPETM 820
MICROPROCESSOR SYSTEM CONSOLE
Provides an interface to microcomputer systems
for troubleshooting system problems

Is a stand-alone, self-contained, rugged portable
unit

Monitors, displays, and alters register, memory
and I/O values for system under test

Human engineered with easy to read 9-segment
hexadecimal displays and extensive operator
prompting

Executes diagnostic routines from [.lScope 820 console overlay memory

Gives complete control over microprocessor
including single step, run with display, or run
real-time capability

Executes instrument resident software patch
routines even when microcomputer system is
ROM-based

Designed to
processors

Provides a 32-bit hardware breakpoint with bit
masking and a 256-word trace memory

support

many

different

micro-

Has built-in, self-test operation

The IlScope™ 820 Microprocessor System Console is a portable, self-contained instrument designed to provide the control,
monitoring, and interaction necessary to effectively and quickly evaluate and debug 8-bit microcomputer-based systems
in the lab, on the production line, or in the field. Connection to the user's system is through a personality probe that is
plugged into the microprocessor socket. Each personality probe is unique to each microprocessor type. The instrument
features many different operating and control modes which allow the operator to carry out a number of functional checks
on the microcomputer System Under Test (SUT).
The unit has been specificially designed to ease the task of microcomputer system check-out for the lab, production line,
and field technician. It also provides the more powerful analytical capabilities necessary to troubleshoot difficult problems
by the more experienced, sophisticated user. Pre programmed test routines resident in front panel PROMs, dedicated high
level command keys, visual prompting, and simplified data entry sequences all ease the check-out of microcomputer hardware. For more rigorous diagnostic tasks, the unit provides a 32-bit maskable hardware breakpoint with optional course of
action after a breakpoint match, a 256 X 32-bit trace memory and a 128 X 8 overlay RAM that allows real-time entry of test
routines via the IlScope 820 Microprocessor System Console keyboard.

7-21

CPU CONTROL

AOORESS OISPLAY/SELECT

The instrument provides complete control over the operation of the microprocessor in the System Under Test

A dedicated, 4-digit hexadecimal address display allows the
following address information to be displayed:

(SUT). The user CPU can be forced to HALT, SINGLE

• The address of any memory location_

STEP, RESET, RUN REAL TIME, or RUN WITH DISPLAY. All of the above CPU commands can be issued

• The I/O port number of any I/O port_

without impacting other operational parameters or diag-

The address of any overlay memory location.

nostic sequences that have been set up.

• The address of the overlay memory origin assignment.
• The address at which the breakpoint is to occur.
• The address portion of the breakpoint mask.
• The address of the given trace record element.
An additional feature of the address display/select logic is
that once the operator has initiated a given memory, trace,
or I/O examination, it is possible to continue the examination in a sequential fashion either in an ascending or descending address value.

RESET/SELF-TEST
The RESET and SELF-TEST features of the unit allow the
operator to either initialize the instrument to a known state
or quickly verify that the instrument is operating correctly.
When the console is RESET, the breakpoint and overlay
memory are disabled, the display registers are cleared and
the specific examine modes are aborted.

When the operator initiates the SELF-TEST of the unit, a
sequence of operations take place which serve to confirm
proper operation of a majority of the instrument.

BREAKPOINT CONTROL

The hardware breakpoint of the instrument allows the
operator to alter the normal program flow of the SUT.
Breakpoint logic is implemented in hardware, thereby
eliminating any throughput degradation of the SUT. All
32 bits of the breakpoint condition word are maskable in
~~da:r g!~e~~'o: ~ha~ ~:e~~~~!~~ condition to be as specific _ _ _ _ _ _ _ _ _ _ _ _ _ __
The occurrence of a breakpoint match can cause an uncon·
ditional halt, incrementing of the pass counter, calling of
a subroutine, or the recording of a single cycle of trace
data. All of these options are selectable via the EXAM
ACTION key prior to enabling the breakpoint.

TRACE MEMORY

The console has a full 32-bit word trace memory that
records 256 cycles of SUT operation without causing any
delays. The trace memory provides information about CPU
operation just prior to a CPU halt or just prior to the
initiation of a panel freeze via the trace DISPLAY key.
The operator can alternatively elect to have data recorded
on all SUT microprocessor cycles or only when program
execution of the SUT microprocessor generates a break·
point match. Once the data is recorded, sequential examination of the data can be accomplished simply by depressing
the EXAM NEXT or EXAM LAST keys.

The address, data, and control variable entry into the
instrument is accomplished via the conveniently located
hexadecimal keypad.

OVERLAY MEMORY

A unique feature of the unit is the ability to map its
memory onto the SUT memory space. Using the overlay
memory allows the operator to insert patch, exercise, or
diagnostic subroutines at any location or point of execution
in the SUT program. The subroutine can either be entered
via the front panel hexadecimal keypad or via the front
panel's ROM/PROM socket.
By using the unit's overlay memory, the operator can
quickiy set up the SUT to execute special maintenance
or troubleshooting programs that permit rapid evaluation
of system operation.

7-22

For selection of the information to be displayed or modified the operator enters the hexadecimal value of the desired address, I/O port number or label assigned to each of
the registers. Once this entry is made, the operator can then
elect to either CONTINUE data entry if modification is
desired or press the END/EXECUTE key if examination
only is desired. For all data entry seql.Jences that potentia!!y
require mUltiple value entry, the ~Scope™ 820 Microprocessor System Console provides oper1, <1>2

±1O MA max; 55 pF typical

A15-AO, D7-DO

-0.25 mA max @ 0.45V; 10 MA max
@ 5.25V; 45 pF typical

ENVIRONMENTAL CONDITIONS

15 MA max

Operating Temperature:

0° to 55°C (32° to 130°F)

35 pF typical (capacitive loading only)

Storage Temperature:

-40°C to 75°C (_40° to 167°F)

Humidity:

95% RH, 15° to 40°C (59° to
104°F) noncondensing

+12V Supply
WAIT
Intercepted Signals

Outputs to user system:
20 mA min @ 0.5V; -1 mA min
2. 7V; 40 pF typical

SYNC
HOLDA, INTE,
DBIN, and WR

@

4 mA min @ O.4V; -0.2 mA min @
2.7V; 40 pF typical

ORDERING INFORMATION
Part Number

Description

PRB-80

8080A I nterface Probe

ACCESSORIES SUPPLIED
One MScope 820 System Console Overlay
One Personality ROM
One Hardware Reference Manual

7-26

Chapter 8

GENERAL INFORMATION

ORDERING INFORMATION
Semiconductor components are identified as follows:
Example:

M

C

o

5

1

L

L -_ _ _ _ _ _ _ _ _ _- ._ _ _ _ _ _ _ _ _ _ _ _~I

I

Fou r or f'Ive characters
per device type

4

LI______, ,______~
Up to three character
modifier for power,
speed, processing, etc.

Package Type
B - Hermetic Package, Type B
C - Hermetic Package, Type C
D - Hermetic Package, Type D
M - Metal Can Package
P - Plastic Package
X - Unpackaged Device
M - I ndicates Military Operating
Temperature Range

Examples:

P5101 L

CMOS 256 X 4 RAM, low power selection, plastic package, commercial temperature range.

C8080A2

8080A Microprocessor with 1.5 J.ls cycle time, hermetic package Type C, commercial
temperature range.

MD3604/C

512 X 8 PROM, hermetic package Type D, military temperature range, M I L-STD-883 Level
C processing. *

MC8080A/B

8080A Microprocessor, hermetic package Type C, military temperature range, M I L-STD-883
Level B processing. *

Kits, boards and systems may be ordered using the part number designations in this catalog.
The latest Intel OEM price book should be consulted for availability of various options. These may be
obtained from your local Intel representative or by writing directly to Intel Corporation, 3065 Bowers
Avenue, Santa Clara, CAlifornia 95051.

*On military temperature devices, B suffix indicates MIL-STD-883 Level B processing. Suffix C indicates MIL-STD-883 Level

C processing. "S" number suffixes must be specified when entering any order for military temperature devices. All orders
requesting source inspection will be rejected by Intel.

8-1

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

PLASTIC DUAL IN-LINE PACKAGE TYPE P
l6-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

C ---3.840 (21.336)

~.820(20.826)~

1
-

-

-

-

-"',,;;,1.260 1...;041

.200 (5.080)
MAX.

SEATING

___

PLA~~ (2.5401
.165(4.191)

.140 (3.5561

===-.-::-'

~
If I I
~ L~ 1

.240 (S.096)

~

---

.130

(3.~

~--.t
-----r

.015 MIN .

--11-.023 (0.::,81)

.110 (2.794)

.065 l!:.651)

,032TYP

.090 f2.286)

.040 (1.016)

(0.813)

.014 (0.356)

.910 (23.114)

l8-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

~.890 (22.098)-~

1_ _ _ _

_!!N~I

C ---3~!
~

.260 (6.604)
.240 (6.096)

---

.200(5.080)
MAX.

r~

SEATING

~=t-=--=YU
[(-JMI
.!.Q!! (2.540)
J

.~

.165/4.191)

,- - - . 1 L-

.:~ (2.794)
.090 f2.286)

====

.130

__

.065 ~
.040 (1.016)

[

(3.::~.~

____ ~_l
~
-----r

i

.325
MAX.]

.140 (3.556)

Jl:.9.~

.015 ( 0 . 3 B l l - A - 0'
.015 MIN. .008 (0.203)
(0.381)

15"

-...:
I

I

L-:---J

(0.584)
.014 (0.356)

.032 TYP
(0.813)

(8.255)

(10.160)
(S.3S.:;!)

1.110 (28.194)

r----'.090 (27.686)-~
1_ _ _ _ _ ~JN!I

C ---3

22-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

1

___

.200 (5.0801

.. ""

.U

PL~~~ (2.5401
.165 (4.191)

.360 (9.1441
.340 ,8.6361

.---t

.425

.155 (3.9371

[

~•. ~~'l

.015 (0.3Bll

·1

.OOB (0.2031

r-1

L~ I

.110 (2.794)
.090 (2.286)

8-2

1I--T.~b5;~~

1

.065 (1.651)
.040 (1.016)

-..JI-- .023
.032TYP
(0.813)

(0.584)

.014 (0.356)

MAX. ]
(10.795)

-R9:
1

.510

....

1

\----- .450--.j
(12.954)
(11.430)

15"

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

PLASTIC DUAL IN-LINE PACKAGE TYPE P
24-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

C ---3·

1.250 (31.750)
r-------,.230 (31.442)-~

1
-

-

-

I'IN~I

-

-~-

.200(5.080)

===
fITlTiJ1 __

~I

PLANE

.!QQ

L

(13.970)

~

.625

[(1~~~51J

.160 (4.064)

MAX.
SEATING

.510

.530 (13.462)

I L=-.!

(2.540)

.165 (4.191)
~
.110 (2.794)
.090 (2.286)

.150 (3.810) ]

~_:r=o=o=m

.015 (0.381)

'Cp·r----r.01SMIN . .008

II
..Jf-- .023

-J

i

.065 (1.651)

,032TYP

.040 (1.016)

(0.813)

IF91

0"

(O.203)~~~15Q

(0.381)

I

(0.584)
.014 (0.356)

I

L '

i

.700

.630~

g~:~~~:

C ---3-I'IN~!I
1.460 (37.084)

[ ~~~1.440

28-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

(36.5761~

-~-

.200 (5.080)

S:t:~~G
.~

MAX.

.

..10 (13.970)
.530 (13.462)

~

.625

.160 (4.064)

[.

= = = : 1 5 0 (3.810) )

~1---UOJjJ~
I
=.!
JL~ ~ ~

----r.015 MIN.

(2.540)
I
.165 (4.191)
.110 (2.794)
.090 (2.286)

r-I

I..-

~

.

.065 (1.6511
.040 (1.016)

-..11-

.032 TYP
(0.813)

C ---3-I'IN~I

~

(O.2031--f..~~15o

.015 (0.381)

.008

MAX. ]

(15.875)

·L .
I

to.381}
.023 (0.584)
.014 (0.356)

D·

I

I
---J

700
.630
117.7BO)
{l6.a02)

2.060 (52.324)
(51.816)-----J

[ ~-- 2.040

40-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P

-~-

'200(5.080)

..10 (13.970)
.530 (13.462)

~

.625

[(1~~~5)J

.175 (4.445)

=_.

~

.165

-,S~E"A,"TI,!,!N"G_-t_--,fITlTiJ1]jiJ]JQ
~
Pl~~:(2.540) yumL~I JL~ ~ ~~tO{~53~~~ .OO8(0203)-+~~i5
MAX.

{4.'911]

.015 (0.3811

.165 (4.191)

i

1

1.-1
.110 (2.794)

.0650.651)

.032TYP

.090 12.286)

.040 (1.016)

(0.8131

8-3

--.if..- .023

(0.584)
.014 (0.356)

0'

L ~.630------JI
.700

(17.780)
(16.002)

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

CERAMIC DUAL IN-LINE PACKAGE TYPE D

c

16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

.7ao (19.812)~

.740 (18.796)

L

---~PIN'l
.300 (7.620)

.260 (6.604)

~

---

.322

13iS83) ]
"DDI::~~!£m-~~
- II fD38"
-.I t
.200(5.080)

.i65 (4.191)

~

.110 (2.794)

.065 (1.6511

.090 (2.286)

.040 (1.016) 032
-- -- .014 (0.356)
(0.813) TYP.

C

18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

CI~~~)]

.160 (4,064)

MAX.

.0'5

fO.381)~i'io

.008 (O.203)

.023 (0.584)

I

'

I

i-~:--i
(10.160)
(a.382)

'~ (22.987J=-=-:J

.875 (22.225)

L

----..,.~PIN'l
.~(7.620)

.260 (6.604)

~

---

.322
.200 (5.080j
MAX.

I
SEATING
PLANE

.100 (2.540)
.166 (4.191)

.~f3·d

~~--~~-=r0'5MIN
i

:.:!..!Q.

r--!

U~L~LD231~~~:~)

t

P9
~~fio

.015 (O.3811--lf..008 (0.203)
I

(2.7941

.065 (1.651)

.090 (2.286)

.040 (1.0161

~1'085

I

I~:-I

.014 (0.356)

C

22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

CI~~~)J

.160 (4.064)

.032 TVP

/10.160)

(0.813)

(S.3ail

127.SS9'-=-:J

1.055 (26.797)

L

_-_~PIN',
.400~

.350 (8.89)

~

---

.425

.200 (5.080)

SEATING

Mp:-~_~~ _
IVI V
~ ~

PLANE~¥ ~t

·100 fl,MQ)

.165(4.1911. 110 (2.794) I
.090 (2286,--l

065 (1651)

.040 (1.016) .032

(0.813jTYP

8-4

.'40
I

1~'D.795~!

13.:561]

:~.D15MIN'
--11

~-'-

j(MAX.:;i

.180 (4.572)

(0.381)

023 (0584)
--:014 (0:356)

.0'5

ID.38')~i'io

.008 (0.203)

J

I

i-:~--i
(12.954)
(11.176)

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

CERAMIC DUAL IN-LINE PACKAGE TYPE D

-__
C
C

24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

,.270 (32.258)~
1.230 (31.242)

~PINll

L

.530 (' 3.462)

.510 (12.954)

___

.-l

.625
.220(5.588)
SEATINGMAX.

~_~~-

.1QQ{~)LANE --]f
.165(4.191)

lrJUll.o65

t

:!1Q (2.794)j

·i50~d

L
,jl__

(l.SS')

l01SMIN.

.040 TiJfi6)

.090 (2.286)

MAX.~

C (15.875) I

.175 (4.445)

.032 TYP

.02~O·f:~~4)

.01510.3.')
.008 (0.203)

~i'io
I

-...... I

l.-~----i

.014 (0.356)

(17.780)

(0.8131

(16.0021

1.470 (37.338)

28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

'------,.430

(36.322)~

,

1

C

!'N_~I

---~!

.530 (13.462)
.510 (12.954J

~

---

.625
.220(5.588)

-=~=-

MAX.

___

.'5013.;'01

S:~~~G5401[1WVt'j
~:~:651)
~lllOI~53~~~
.16514.191)
.040 11.016) U~U~~_.023 1~.5.4)
r-I

.110 (2.794)
.090 (2.286)

C~~~5J

.~ (4.445)

.032 TVP
(0.813)

.014 (i).3S6)

'0151.381)~*O

.008 (.203)

I

I

i---.~~
(17.780)
(16.002)

C
C---~I
2 .070 (52.5~_-:J

40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D

2.030 (51.562)

PIN 1

.530 {13.4621
.510 (12.954\

---

'~n~
PLANE

~

=rnrnn · ~";'nJ
.175 (4.445)

f

~n

l

'if lUi V

~~!~~:3-1 t'~ ~065
r-l
040
.110 (2.794)
.090 (2.286)

8-5

(1651)
(1016)
.032 TYP
(0.813)

JL

015 MIN.

(0381)
023 (0584)
.014 (0.356)

(17.780)
(16.002)

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

CERAMIC DUAL IN-LINE PACKAGE TYPE C

c

16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

oB20 120.820'--:J

.780 (19.812)

- [=== .310~~
[1
--fm L TI
,.'''.~
~ L~UL ~. ".' '~ J ~ ~

PIN 1 MARK

PIN:

J

.210

L

~~-

(6.858~

~

.200 (5.080)

.010

i1.778

===-=-Wf

SEATING
PLANE

R

.096 (2.413)

MAX

---

_

.13013.3021

(0.381)

.100 (2.540)

.065 11.65)

.:!!.Q.

. (O.St3) .

032TVP

(2.794)

I

'~

.OBO (2.032)

l.015 MIN.

.015(0.381)
.008 (O.203)

"'-t..:

I

10°

"

. '

l..-300--.J
.200

.01' 10.3561

.....

(9.6521

.090 12.286)

(7.112)

C·..

.920 (20.820)

18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

[1

O 119 .• ,21---:::1

=

=- __

PIN.

.270 (6.858)

.09512.4131

LJ

==.I

Jm==-=-m07011778IJ

SEATING

---

L

PLANE
100 {2540j

~

065(1651)

16514191]

040 11Oi6i

110 (2 794)

032 TYP

.090 (2.286)

(0.813)

C

22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

_

1130@,302IM
080 (2.032)

---r...015 MIN
(0381)

l..- .300
.280

===
L~_
-~-

~

--

---

I

PIN 1

PIN1MARK

1
s:;
~

1~06~~1

8-6

.07D(1·~.'30(3.302)

___Ll

.080 (2.032)

---r...015 MIN.

.065 0.651)
.040 (1.016)

.110(2.794)
.090 (2.286)

---..I

:~:~~:

.100 (2.540j

.165 (4.191)

':

014 (0 356)

rr

0"

'-..: #",1it

!

.008 (O.203)

.023 10 5841

,·055 126.7971--;:1

.200 (5.080)
MAX.

~ (2.540)

,

.01510.3811

1.095 (27.813)

1
[
[

SEATING
PLANE

.310 (7.8741

~

.200 (5.080)
MAX

PIN 1 MARK

,032 TYP. ___
(0.813)

J~ :g~! ~g:::l

(O.3SH

R
,

'a.:

.015(0.381)
.008 10.203)!

I

~

~ :: ---J
(12.192)

/9.906)

!.f

PACKAGING INFORMATION
CERAMIC DUAL IN-LINE PACKAGE TYPE C
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

All dimensions in inches and (millimeters)

D[- a
(29.972)---1

1.220 (30.988)
-------,.180

1

~J-

PIN1MARK

PIN 1 .600 t5.'.0)
.560 (14.224)

_~ _

.200 (S.080)
MAX.

--.-l

.095 (2.413)
.070 ff7781

t

n
1

PLANE

.100 (z.540)
.165(4.191)

ru

~-=~

SEATING_~- -

-

.065 (l.GS')
.040T1.Oi6)

r.110(2.794)

n
n. .~l~~IN. (2.0~2)
TIL
J\__

.13013.302}
.080

R
"

.01:;)(0.381)
.008 (0.203)

O.

':tr...,,,vw

_

-

:

!

(.
)
.023 (0.584)
.014 (0.356)

!

L.680---...J
.580
(17.272)
(14.732)

,090 (2.286)

D[-]a::~ g:~~:
1.420 (36.068)

" - - ' . 3 8 0 (35.0521----1

28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

1

-t

__ _

--.-l

PIN 1

.200 (5.080)

.-.~,

.095 {2.413}

I

! w~-=~·
L 1n
n
Tn
¥ --..
,.",",r- 1"..., .II. .,
MAX.

.070 (1.778}i

SEATING___

PLANE

PIN 1 MARK

-~-

.100 (2.540)

~-""
- -

-

1________

40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C

(0.381)

a

D[-J__ _
-~-

T
'L

.200 (s.oao)

.100 (2.540)

.110 (2.794)

:000(2.286)

8-7

-

!

.580

PIN 1 MARK

-t

:=g::~~:

.095 (2.413)

n
I

!

L •• ----jI
(17.272)
(14.732)

m~-=lm·070(1.778}b'l30 (3.302)

PLANE -

00

#,;00

1

--.-l

,.""SI?R~"..

SEATING

I

_,

(0.203)

.01' (0.356)

2.025 (51.435) ~I
1.975 (50.'6 5)
PINl

A
I

.015 (0.381)

L .015 MIN . . 008

.065 (1.651)

.110 (2.794)
.090 (2.286)

,080 (2.032)
.130
(3.302)

~-

.065 (1.651)

n
T

.080 (2.032)

I"
.015 MIN.
(O.381)

R
,

.015 (0.381)
.008 (0.203)

JL'= -,
.014 (0.356)

0"

'0.:

10'

:

!

!

I-::---i
(17.272)

(14.732)

PACKAGING INFORMATION

All dimensions in inches and (millimeters)

CERAMIC DUAL IN-LINE PACKAGE TYPE B
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B

-

r - - - - , . 0 8 5 (27.559) - - - - ,

1_ _ _ _ 1.065 (27.0S1) _

.!!r-u.!

B~=E~-----.1

PIN1:1..7791
.370 (9.398)

.~~~

_ -----

120

I+-

i3.D~

I

MAX.

1

(lD.7951;:J.1

m~~~~~Jm==i D15MI~ffi:~::::3811~~-M~.

SEATING

PLANE
.100 (2.540)

.165 (4.119) .l1D(2.794Ij

L4 i1

.090 (2.286)

24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B

.065 (l.6SH
,040 Tf])1'6T

~ JLD23(~::~:
])14

.032 TYP.
(0.831)

~-- 1.270 ~258)
1230 (31.242)

_

MAX.

~

(~)

.165 (4.191) .110 (2.794Ij
.090 (2.286)

L

,530 (13.462)
.510 (12.954)

----.1

.625

\.190 (4.8261

i---.i·,25

h-------J
I~
t'

015MIN

.065 (1.651)

032 TYP

.040 (1.016)

'(0.813)

JL·023

(0.381) .

(O.584)
.014 (0.356)

(3.175)

.015 (0.3811
.008 (0.203)

~MAX.g
875
1 * \ "1 5 .
I

:

~

L·700 J
1i3O-

(17.780)
(16.1)02)

8-8

I(

--.l

P1N'_1

__

~:=::I:::-~~~m·ll0
(2.7~

PLANE

545Ql0

~N..J.l

.150 (3.8101

SEATING

L.

--4

___~__

.220(5.5581

(02031.008

(0.356)

(12.454)
(11.430)

EI:=-r--]
I

.1sm

.42'

.~ (3.556)

.200 (5.080)
MAX.

!!:
15°

I

INTEL MILITARY PRODUCTS
IC 38510 PROGRAM

Intel offers selected products in full conformance with requirements for military components.
Effort is underway by agencies of the Department of Defense with full Intel cooperation to establish "JAN" standards for several of our products. Intel has led these standards by emulating the
anticipated "JAN" processing and lot acceptance requirements with the Intel in-house IC 38510
Program. I ntel Specifications are available which document general and detailed requirements for
each of the military products. Detail specifications are organized by generic family and provide all
information necessary for non-standard parts submissions in accordance with MIL-STD-749, Step I,
Step II, and Step III. These documents are available from your local Intel Sales Office or authorized
Intel Distributor.
Three levels of product assurance are offered: Level B, Level C, and Military Temperature Only.
The Military Temperature level products have guaranteed operating characteristics over the specified
temperature range and have undergone I ntel's rigid product assurance requirements.
Level C and Level B products are in conformance with M I L-STD-883, Method 5004 requirements,
and in addition, have a specified maximum rebond criteria (10%) and a specified burn-in PDA
(10%), all documented in the detail specifications, consistent with 38510 requirements. Lot conformance tests are performed in accordance with M I L-STD-883A, Method 5005.

Available now.

Qualification in progress. Check with local Intel
Sales Office or Distributor for availability.
MD8238
MD8253
MD8259
MD8316E
MC8748
MC8755

MC8080A
MB8101A
MD8102A-4
MD8111A
MD8212
MD8214
MD8216
MD8224
MD8226
MD8228
MD8251
MD8255
MD8316A
MC8702A
MC8708

8-9

LEVEL BAND C
MILITARY PRODUCTS MANUFACTURING FLOW
Incoming QC Raw Material Inspection
Incoming QC Silicon Wafer Inspection
Wafers

Optical Inspections
Contamination Checks
Particle Counts
Critical Dimensions

} - - - - Wafer Fabrication
Optical Inspection
Wafer Sort

QA Wafer Inspection
and Die Count

Scr ibe and Brea k
01 Water Die Clean
/ l - - - - Post Break Chip Inspection -

MI L-STD-883A, Method 2010
Condition B

QA Post Break Chip
Inspection, MIL-STD883A, Method 2010
Condition B
Lead Frame
and Base
Lead Frame Attach

V l - - - - Visual Inspection for Alignment
and Glass Flow
Die Attach: Jumper Chip Attach
Visual I nspection of

~--------------------~6

Die Attached Units.
Monitor of Die Attach
Machines.

Aluminum Ultrasonic Wire Bond

1-----------------------0
Die Attach and Bond Inspection

Bond Pull A cceptance to
Monitor Bond Strengths per

MIL-STD-883A, Method 2011

/1----- per MIL-STD-883A, Method 2010
Condition B

QA Die Attach and Bond
Inspection per MIL-STD-883A,
Method 2010 Condition B
AQL = 1%
Cap
1"---

Cap Sea I

QA Seal Monitor. Cap
Alignment and Glass Flow

1---_____________________ Stabilization Bake,
Temperature Cycle, per MIL-STD-883A,
Method 1010 Condition C, 10 cycles

150°C, 24 Hours

Centrifuge, per MIL-STD-883A, Method
2001, Condition E, Y 1 Axis, 30KG
/ ) - - - - Hermeticity Testing: Fine Leak - Helium

or Kr 85 to 5x 1 0-8 cc/sec.
Gross Leak - Fluorocarbon,

Condition C2, 100% MIL-STD883A, Method 1014

J - - - - Tin Plate

QA Tin Thickness Monitor

Thickness Spec 200-700
J----

Microinches

Trim Tie Bar

Hermeticity Lot Acceptance

AQl= 1%

8-10

LEVEL BAND C
MILITARY PRODUCTS MANUFACTURING FLOW (Cont'd)
Final Visual - Package, Seal Date Code,
Country of Origin, and
Lead Inspection
Final Visual Lot
Acceptance, AQL = 1 %

------0 Plant Outgoing Inspection*
Mark, Tube Load and Opens and Shorts

Testing
Ship to USA
Stabilization Bake - 1500 C, 24 Hours
Incoming Inspection of

t------------------~ Foreign Assembly Plant
Shipments**. l TPD
Dependent Upon Test
25° C Interim Electrical Tests, Level
B Products Only per MI L-STD-883A

Burn-In (Level B Products Only) per
MIL-STD-883A, Method 1015, Condition
Cor F

100% Electrical Tests at 2SoC

(AC, DC, Function)
100% Electrical Test at _55°C

V t - - - - (AC, DC, Function) Level B Product Only
/'-_ _ _ 100% Electrical Tests at +125°(;
(AC, DC, Function) level B Product Only
Final QA Visual and Electrical
Tests at 25'C, -55'C, and 125'C
L TPD = 5 (AC, DC and Function)
(_55°C and +125'C Testing On
Levels Band C Product Onlv)

Mark Customer Number

Group B Tests Performed per
MIL-STD-883A, Method 5005,
for Lot Conformance. (Levels
Band COnly)
Group C and 0 Tests Performed
l

r

-------------------LJ
Ship to Customer

o

50

o

MANUFACTURING INSPECTION OR TEST

LTPD

ACC

1. Hermeticity

5

2

2. Centrifuge

5

2

3. X-Ray

7

4. Lead Fatigue

6

MANUFACTURING OPERATION

20

5. Acoustic (Loose Particles) AQL

QAMONITOR
QA LOT ACCEPTANCE

**Incorning Inspection Testing:

*Outgoing Acceptance (Plant Clearance) Inspections:
Test

per MIL-STD-883A, Method 5005,
for Lot Conformance. (Levels B
and COnly)

Test

0

= .04%

LTPD

1. X-Ray, Die Attach and
Seal Quality

7

2. E xterna I Visua I

7

3. Opens and Shorts

7

4, Hermeticity

7

5, lead Fatigue

20

6. Internal Visual

10

7, Bond Pull

7

8. Acoustic (1000 Particles) AQL = .04%

8-11

o
o

INSTRUCTION SET
Summary of Processor Instructions

Mnemonic

Description

MOV r1 . r2
MQV M,r

Move register to register
Move register to memory
Move memory to regiStl:H
Halt
Move immediate register
Move immediate memory
Increment register
Decrement register
Increment memory
Decrement memory
Add register to A
Add register to A with carry
Subtract register from A
Subtract register from A
with borrow
And register With A
Exclusive Or register With A
Or register with A
Compare register with A
Add memory to A
Add memory to A with carry
Subtract memory from A
Subtract memory from A
with borrow
And memory With A
Exclusive 0 r memory with A
Or memory with A
Compare memory wtth A
Add immediate to A
Add Immediate to A With
carry
Subtract immediate from A
Subtract immediate from A
with burrow
And immediate with A
Exclusive Or immediate with
A
Or immediate With A
Compare immediate with A
Rotate A left
Rotate A right
Rotate A left through carry
Rotate A right through
carry
Jump unconditional
Jump on cany
Jump on no carry
Jump on zero
Jump on no zero
Jump on positive
Jump on minus
Jump on parity even
Jump on parity odd
Call unconditional
Call on carry
Call on no carry
Call on zero
Call on no zero
Call on positive
CaU on minus
Call on parity even
Call on parity odd
Return
Return on carry
Return on no carry

MDVr,M
Hl T
MVI r
MVI M

INR r
OCR r
INR M
OCR M
ADDr
ADe r
SUB r
SBB r

ANA r
XRA r
ORAr
CMP r
ADO M
ADC M
SU8 M
S88 M
ANA M
XRA M
ORA M
CMP M
AOI
ACI
SUI
S81
ANI
XRI
ORI
CPI
RLC
RRC
RAL
RAR
JMP
JC
JNC
JZ
JNZ
JP
JM
JPE
JPO
CALL
CC
CNC
CZ
CNZ
CP
CM
CPE
CPO
RET
RC
RNC

NOTES:

0, D.

Instruction Code [11
Ils 0, 0 3 O2 0,
S

0

0
0
0
0
0
0
0
0

1
1
1

0

Clock[21
00

S
S
0
0
0
0
0

Cycles

10
5
10
10

S
S
S
S

Description

RZ
RNZ
RP
RM
RPE
RPO
RST
IN
OUT
LXI8

Return
Return
Return
Return
Return
Return

LXIO

LXI H
lXI SP
PUSH 8
S

S
S
0
0
0
0

PUSH 0
PUSH H
PUSH PSW

POP 0

POP H
POP PSW
STA
LOA
XCHG
XTHl
SPHL
PCHL
OAD 8
DAD 0
DAD H
DAD SP
STAX 8
STAX 0
LOAX 8
LOAX 0
INX B
INX 0
INX H
INX SP
OCX 8
OCX D
OCX H
DCX SP
CMA
STC
CMC
DAA
SHLO
lHlO
EI
01
NOP

1
0
0
0
0
0

0

1
0
0
0
0
0
0
0
0
0
0
0
0

on
on
on
on
on
on

0, D.

Ils

0, 03 02

zero
no lero
positive
minus
parity even
parity odd

Restart
Input
Output
Load Immediate register
Pair B & C
Load immediate register
Pair 0 & E
Load immediate register
Pair H & L
load Immediate stack pointer
Push register Pair B & C on

1
0

0

A
0
0
0

A
1

0
0
0
0
0
0
1
0
0
0

A

0

0, Do

Cvcles
5/11
5/11
5/11
5/11
5/11
5/11
11
10
10
10
10
10
10
11

sta~k

POP B

0

Clock [2J

Instruction Codelll
Mnemonic

10
10
10
10
10
10
10
10
10
17
11117
11117
11117
11/17
11/17
11117
11117
11/17
10
5/11
5/11

Push register Pair 0 & E on
Slack
Push register Pair H & l on
stack
Push A and Flags
on stack
Pop register pair B & C off
stack
Pop register pair 0 & E off
stack
Pop register P,lIr H & L off
stack
Pop A and Flags
off stack
Store A direct
Load A direct
Ex;::hange 0 & E, H&L
Registers
EXChange top of stack,H & l
H & l to stack pOinter
H & l to ~rogram counter
Add B & C to H & l
Add 0 & E to H & l
Add H & L to H & L
Arld stack pointer to H & l
Store A indirect
Store A Indirect
load A indirect
Load A indirect
Increment B & C registers
Increment D & E registers
Increment H & l registers
Increment stack pointer
Decrement B & C
Decrement D & E
Decrement H & l
Decrement stack pointer
Complement A
Set carry
Complement carry
Decimal adjust A
Store H & l direct
load H & l direct
Enable Interrupts
Di$ilble interrupt
No-operation

1. DOD or SSS - 000 8 - 001 C - 010 D - 011 E - 100 H - 101 L - 110 Memory - '111 A.
2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.

8-12

11
11
11
0

0

10
10
10
10

0
0
0

0

13
13

4
18

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

10
10
10
10
7

0

<

0

0
0
0
0
0

1
0
0
0
0
0

4
16
16
4

INSTRUCTION SET
Summary of Processor Instructions
By Alphabetical Order
Mnemonic

Description

ACI

Add immediate to A with

0,

D.

Instruction Codelll
0, 0,
0,
05

0,

D.

Clock[2J
Cyclm:

Mnemonic

DltSCl'iption

MVI M
MVlr
MOV M,T

MoveimmediateregistBr
Move register to memory

07

D.

Instruction Codel1J
0,
0, 02
05

0,

D.

Clocki21
Cycles

...,
I

ADC M
AUer
AOD M
ADO r
ADI

carry
Add memory to A with carry
register to A wilh carry
memory to A
register to A
immediate to A
memory with A
And register with A

ANA M

Add
Add
Add
Add
And

ANAr
ANI

And immediate with A

CALL
CC
CM
CMA
CMC
eMP M
CMPr
CNC
CNZ
CP
CPE
CPI
CPO
CZ
DAA
OAO B
DAD 0
DAD H
DAD SP
OCR M
OCR r
OCX B
OCX 0
DCX H
OCX SP
01

EI
HLT
IN
INR M
INR r
INX B
INX 0
INX H
lNXSP
JC
JM
JMP
JNC
JNZ
JP
JPE
JPO
JZ
LOA
LDAX B
LDAX D
LHLD
LXI B

LX] 0
LX] H
LXI SP

Call unconditional
Call on carry
Gallon minus

Compliment A
Compliment carry
Compare memory WIth A
Compare register with A
Call on no carry
Call on no lero
Callan positive
Callan parity even
Compare immedIate with A
Call on parity odd
Call on zero
Decimal adjust A
AddB&CtoH&L
Add 0 & E to H & L
AddH&LtoH&L
Add stack pointer to H & L
Decrement memory
Decrement register
Decrement B & C
Decrement D & E
Decrement H & L
Decrement stack pointer
Disable Interrupt
Enable Interrupts
Halt
Input
Increment memory
Increment register
lncrementB&Cregisters
Increment 0 & E registers
Increment H & Lregisters
tncrement stack pointer
Jump on csrry
Jumponminus
Jump unconditional
Jump on no carry
Jumponnozero
Jump on posItive
Jump on parity even
Jumponparityodd
Jumponzero
Load A direct
Load A indiract
Load A indirect
Load H & Ldirect
Load immediate register
PairB &C
Load immediate register
Pair 0 & E
Load immediate register
Pair H & L
Load immediate stack pointer

17
11/17
11/17
4

MOVr, M

Move mBmory to register

MOV rll2
NDP
ORA M
ORA r
DAI
OUT
PCHL
POPB

Moverllllisterto rltgister
No-op!lIation

POP 0
POP H

4
11/17
11/17
11/17
11/17
7
11/17
11/17
4
10
10
10
10
10
5

POPPSW
PUSH B

Exchange top of stack, H & L

RAL
RAR
RC
RET
RLC
RM
RNC
RNZ
RP
RPE
RPO
RAC
RST
RZ
SBB M

SBBr
SBI

SHLO
SPHL
STA
STAX B
STAX 0
STC
SUB M
SUBr
SUI
XCHG

10

10

Output
H & ltoprogram counter
PDP register pair B & Coff
stack
Pop reyisterpair 0 & Eoff
stack
Pop register pair H & Loft
stack
PopAand Flags
off stack
Push register PairB &Con

XTHL

PUSH PSW

5
10
10
10
10
10
10
10
10
10
13
7
7
16
10

Or immediate with A

XRAM
XRAr
XAI

PUSH H

10

Or memory with A
Or register with A

""k
Push register Pair 0 & E on
stack
Pushreyister Pair H & Lon
stack
PushAand Flags
0" stack
Rotate A left through carry
Rotate A ri1!htthrough
carry
Return on carry
Return
Rotate A left
Return on minus
Return on no carry
Return on flO zero
Return 011 positive
Return on parity even
Return on parity odd
Rotate A right
Restart
Return on zero
Subtract memory from A
with borrow
Subtract register from A
with borrow
Subtract immediate from A
with borrow
Store H & Ldirect
H & L to stack pointer
Store A direct
Store A indirect
Store A indirect
Set carry
Subtract memory from A
Subtract register from A
Subtract immediate from A
Exchange 0 & E, H & L
Registers
Exclusive Or memory with A
Exclusive Or register with A
Exclusille Or immediate with

PUSH 0

7
10
10

Move immediate memory

10
10
10
10

11
11
11
11

5/11
10
4
5/11
5/11
5/11
5/11
5/11
5/11
A
0

11
5/11
7

16

13

10
10

NOT ES: 1. D DD or SSS - 000 B - 001 C - 01 0 D - 011 E - 1 OOH - 101 L - 110 Memory - 111 A.
2. Two possible cycle times, (5/11) indicate instruction cycles dependent on condition flags.

8-13

18

8-14

Notes

inter

MICROCOMPUTER AND MEMORY SYSTEM
SALES AND MARKETING OFFICES

u.s. AND CANADA SALES OFFICES
ALAIIAMA
Pen-Tecl' Asaocletva, Inc.

HolldlyOHlceClllll1t!'
3322 S. MCIII'IOIIII Pkwy.
Huntsvllle368Dl
TIl; {2O$)S33-OOllO
GI8IlWIIllaAaaoclalfls

CONIiIKTlCUT
Complllflr Marketing "IKletatlon
P.O,BOJCI72

~~~=~\O:
InteiColp.

l'eacocltAllay
1 PllSanaremFload,Sulte146

Tel: (205)883-8384

o.nbury06B10

,,.

Tal: (203) 7S2-8388
TWX: 710-458-1119

442t1NorlhSadclle8a1lTnlll

SGotIId,l,aSl!$1
T81:(902)994-5400
Intel Corp.
8850N.351hAwanua
Phoenix65Q21
Tel; (6D2)242-121l5

CAUfO....1A

.

,

Tol: (203) 788-1013

7844Ho_hclltT";'
HuMsvllle3li8D2

. .OZONA

IIARYLAND
GlenWhll.Atllllclaltls
57WIIaITImoniumRoed
Timonium 21(193
T.I:(30I)252-7742

F1.Laudllrdale3330&
Tel: (3OIi)77100600
TW)(:510-956-9407
InieICorp.
5151 Adaneon SlnlaI,SUllfll0!
Or1llndo32804
Tal: (305) 628-2393
TW)(:611l-4$3-9219

T-SqUllrld
4054 NawcouflAwn_
SyrICusal3208

TENfilESSEE

~,'=ol~wnorlve
RockYIUa20852
Tel: W.IIh. (301) &Bl-B43O
Bilio. (301) 792-0021

P.O. Box W
PltllIordl4534
Tol;(7161248-6005

TELEX: 97-8289

b~~':=.o=' Bulla 14A
Tal: (811)258-8587
TWX: 71D-343-8333
Computer Marllllllnil Assoclalall
257C",",nlS1rH1
WllthamD2154
T.I:(817)B94-7000

~~!::::-Sbeat

Poughkeapsl.ll!801
T.I: (9141 41&-2303
TWX: 510-24&-ODIlO
MUluramentTechnology, Inc:.
159 NorthemBoullt'llrd
G,aalNeckl1l1l!1
T.I:(518)482-35OO

~~~415J 84a.ms

lLUNC»I

=j~~1eYard

8312 Nonh MalnStreal

P.O. Box 1420

o.ktlrook60621
Tel: (312j325-9510
TWX: 91H!Hi8Bl

T\Y)(:810-450-252a

....

1m.ICorp.'

, "

'851 Eas141hStI1l8l

SanIaAIIlI82701
r81: (1'4) 835-8842

...

~.~":r.=,lnc.

Brighton 48118
Tal: (313) 221-7087

Tat:(801)2&6-H17

-,

INDIANA

~\3~:J_~=

Mac.'

WoodlandHlll191384
Tel: (213) 347.s&QO
EarleA."DCI"lno.

Tal: (317)255-4147
TWX: 810-3oil-.3211

~MerculYS1,.at

NIWJlR8BY
Intel Corp.
1 MalroplUil OfIlce Bldg.

:~~~OO~:'~Sl

ElectfOR"",lnc:.
34D2N.Antllolly Blvd.
Ft. Wayne 481102
Tel; (21I)<482-l!38B

Intel Corp.

T

",.L

i:Z::Oa'::=-'

IndlanapoUa48240

8&nDklgo92111
Til: (714) 278-5441

""........

IOWA

T"': (2011 B85-9100

~X:71CH8D-8238

~~~a::~~~=
Mounlainlllk
25921 FemGuichRo..t

P.O. BOll 13$5

E~8IM38

Till: (303) 674-6256

-".....

LowrylAll80clal8ll,lnc.

~~~~RllhnRoad
Till: (5131435-4795

Lowry&Alfloclalal,lnc.

24200 CIllg,ln Blvd.

Sultal48
CII\'II.nd44122

.....,

275 Commarc.Dr.

TechnlcaIRllpresantative"lnc.
1245 Nieman Road,SUlte#l00
LlIlelul88l!14

~J~l~;~~~

=~c;'Canllr

FonWashlnlllonl9D34
T.I: (215) 542-9444

TWX: 51o-t161-2077
Q.E.D.Electr'IYCroll'SlIHIIBMarklltlnglnc.
13777 N. Cenlral EXpl1lHW8Y

"",.

.......

Lowry'A~I.,lnc.

ThraeParltwayCentar
Sul1l201

PllIsburghl5220
Tel:(412Ig22-5110

T-8quared
842 Kreag Road

InltllCorp.'

~r~~=-:!.Inc.

I'ENN8YLVAlftA(conLl

f=~\7~18cl~~~~
~~~3~fJ.:r~~

MMSACIfUSITT8
MlHland327$1
Tal: (305) 845-3444
IMeICorp.
1001 N.W. &2nd Streel,Sulla408

NEW YORK (canL)
Intel Corp.
474 Thu,tIon Road
FlochHlerl4619

woo.......
InItlICotp.

4368 S. Howell Ave.
Mllwaukae53207
T.I: (414) 741-07811

~~taJ.::.om't.rllInA'YI.

0Ilawa,Onta~oK1S1V9

T.I:(813)232-8578
TELEX; 053-4419
Mullilek,Jnc."

15GrunlellC"'"mt
Ottawa, Onlarlo K20 OGl3
T.I;(tI13)22S-23e!I
TeLEX:D53-4S85

....

, ,

8CANDINAVIA

Slllc223

~~!6:~~~.11

........

EUROPEAN MARKETING OfFICES

~"l:I~~:r:r:~~~.R.L.'

941>28 RunglsCeIlu
Tel: (Ol)8B12221
TELEX: 210-47$

lnltll8emicondUCIOtGmbH"
Seldla1r_27

Intel ScIIndlnllViaA/S'

Til: (01) 182000

8000 Muenchlll2
T.I; (0881 5581 41
TELEX: $23177

TELex: 191367
InlalSwedenAB'
Bo~ 2009l!

Intel SemlconduclorGmbli
AbnlhamUncoinst.-.-3D
8200WI ... badenl

.......

f:tJ~~V~~~5

S-18120Bromma

~~11~11S:~~1IO

ORIENT MARKEnNG OFFICES

......

,..wAN

KoIlllllDlllllel

Taiwan AutomatlonQo.'
2nd Floor, 224

...... ,

NanklngEasIRaad

Telpel

Tel: (Ol!)nl0114D-3
TELEX: 111142TAIAUTO

-,

G_ral Enlilnea,lnll Anoc:Ia1al
37,HIliStreet

81ngep0fl8

SamYung Bldg. #303
~~~::ghang-DangChung_KU
Leewoodlntamallonal,lnc:.

C.P.O.Box4048
112-25,SOkong-Oong
CIlung-Ku,SaouI

INTERNATIONAL DISTRIBUTORS

DE_'"

GUllA1ft' (-'-l

LYII9IOI("rnponentA/S

Qelmarkan4

...,""'"

A.J.F. SpMms l Componente

PT't'.LTD.

28B0Soborg
Tel: (01)87 00
TELE)(:2291IO

n

ScandlnaYillnSemlconduCIOr

SupplyA/S
Nannesgade18
DK-2200CopenhllllllnN

f:tfx~)I~D3S:fIO

FINLAND
O~FlntronlcAB

~e:'I~lnkaW 35D
Hei8lnkll8

Tel: (80)884451
TEL£X:I2428

~:::~~~ffl~

Il-8l!77K.1mberg
Tal: (08434)8ODS

TELEX: 494428

INDIA
Ellllltronicainlema1tonal
128 MahatmaGllfldhl Road

~tri:':
"

...

oIAPAN(canL)
Nippon Micro Computar Co.LttI.
MutsumIBldg.4-e-21 Kojlnlllchl
ChIYQde-ku,ToIIyol02
Tal: (03) 230-0041
NnHERLANDS
C.N. RoodBV
Con Vencler
Llndenattaal,13
-~.,
RI/IowlJk2H21OD
Tal: 070-998380

CABLE: GUNTICO

TELEX,3123$

Eastronk:altd."

Joan Muyskanweg22
NL_1D08Amsterdam
Tat: (020)834824
TELEX: 14822

~~o~~reaI

TeI-Aviv

Tal: 415151

TELEX:3383B

~:~I=:t~~~nd

NEW ZEALAND
W.K.MeL_Ltd.
I03-5F.lton M&llthewAvllnul

~!~:nM~;' Auckland
TELEX:NZ2783

NORWAY
Eladre3SS.P.A.'
VIaPaoloGaldano,141D

10131 Torino

Via Gluleppa Valnlllrana, &3

~~
~~r~:t!=,~~a LOA

=~11.!te::~':'hnlk GmbH
1I!LG1U1l
InalCCl Balglum S.A.
AwnueVai Duch_, 3
EI-lI80BIIIIIII~

TELEX: 25411
*"Note New Telephone Numb.,

TELEX:D2-13580
EleclronIc2OOQV.fbi .... 0mI;IH
Neumerkl8rStr_1S
D-IOOOMuencmen80

~~='

,
UNITED KINGDOM
RlpldRecall,L.t1I.
11_15 Be\IIrton SlreaI
Drury Lena
London WC2H 9BS
Tel: (01j379-8741
Tel.ElC:28752

11845313

80UTHAfRICA
EIeQlronlcBulldln9 Eleflllln\S

D-2085Qulckbom-Hamburg
Tel: (04t0818121

T8I:(02jIlllDOOI2

~D

TELEX: 18983

Tel:

GIRIIANY

NordlakElectronlkAB
S-ID3EIOStockholm7

NordlakElektronlklNoraelA/8
T.I:(O.21553893

f:'J:~I~290-812732<4

SweDEN

'"'

T.I;(OIlI_
TELEX: 10547

~~~~Vell

~~:~~):':'.~~-3087114
001311 Roma,11eIy

~::''!c.,
5~I7,dro22
TElE)(:&I508IFCEE

RyoyoElectrlcCorp.
KonwaBldg.
1-12-22, Tsuklll, I-Choma
Chuo-Ku,ToIIW0104
TOI:(03) !43-7711

~~~:

"Field AppllCldlon Locdon

MICROCOMPUTER AND MEMORY COMPONENT
SALES AND MARKETING OFFICES

3065 Bowers AVBnue
Santa Clara, California 95051

Tul: (408)981.8080"
lWX:910-338-0026
TELEX: 34-6372

u.s.

AND CANADIAN SALES OFFICES

ALABAMA
Glen While Associales
7644 Horseshoe Trail
Huntsville 35802

CONNECTICUT

MASSACHUSETTS

NEW YORK (con!.)

Intel Corp

Intel Corp."

l'eacockAlley

1 PadaMram Road, $ult1l146

b~7el~I~I,~~~~f802~d, Suite 14A

85 MarketStteet
Poughkeepsia, New York 12601

Tel: (205)683-9394

Danb~ry06Bl0

T81: (617) 256-6567

ARIZONA

TWX, 710-343-6333

Tel: (914)473_2303
TWX: 51O-24S-00BO

TWX: 710-456-1199

MICHIGAN

NORTH CAROLINA

k~~6 ~~~5th Avenue

T81:(203) 792-8366
FLORIDA

1001 NW. 62nd Slreet,Sulte406
FtLauderdale33309

~~~3g156_~~~g:g~

CALIFORNIA

~~t~~~~~;rlson
Suite 345
Sherman Oaks 91403
(213)966-9510
TWX: 910-495-2045
Intel Gorp.'
990 E. Arques Ave.
suite 112
Sunnyvale 94086
Tel: (409) 736-3870
TWX: 910-339-9279
TWX: 910-338-0255
Mac-I

~~;~ ~~atlUCk
Barkelay 94704
Tel: (415) 043-7625
Mac-I
P.O. Bo~ 1420
Cupertino 95014
Tel: (408) 257-9880
Earle Associates, Inc
4805 Mercury Street
SuiteL
San 0lag092111
Tel: (714) 278-5441
TWX: 910-335-15B5
Mac-I
P.O. Box 8763
Fountain Valley 92708
Tel: (714)839-3341
Mec-l
~0121 Ventura Blvd.

~u~~ed~~odE Hills 91364
;el: (213) 347-5900
TWX: 910-494-4966
Intel Corp.'
1651 East41h Street
Suite 150
Santa Ana 92701
Tel: (714)835-9842
TWX: 910-595-1114
COLORADO

~~t~~ ~~~·Evans Ave.
g~ve~' 8~~1~~ 260
Tal: (303)758-8066
TWX: 910-931-2289

intelCorp

tnletCmp

Phoenix 85021
Tet:(602)242-7205

InlelCarp.

~~~t~Oto~rthweS\ern Hwy
Southfield 48075
Tel: (313) 353-0920

OHIO

:::~L~i'" giI21°.;~ 212

Intel Gorp.

6!ra~~~~~~~~ Street, Suite 105

~~~eJ S~~ ~aln Street

ILLINOIS

MINNESOTA
Intel Gorp
8200 Normandale Avenue
Suite 422
Bloomington 55437

):o~IJ~~;:;oulevard

~l~n.~~t~~~~

Tel: (305) 626-2393
TWX: 810-853·9219

Suite 220
Oakbrook 60521

INDIANA

:~~c~.o6~r~~i~~~t

Indianapolis 46240
Tel; (317) 255-4147
TWX: 810-341-3217
Electro Reps Inc.
3402 N. Anthony Blvd.
Ft.Wayna46802
Tel: (219)482-2388

NEW JERSEY
Intal Corp,
1 MatrcplalaOffice Bldg.

IOWA
Technical Representatives, Inc
SI. Andrews Building
1930 SI.Andrews Drive N.E
Cedar Rapids 52402
Tel: (319) 393-5510
KANSAS
TeChnical Representatives, Inc.

~~~;x~I~~~ln4 Road. Suite g100

~~~WJ-~:~:~g, 3,

& 4

MARYLAND
Glen White Associates

~im~~~\JI;;6~~um

Road

Tel: (301)252-6360
Intel Corp."
57 West Tlmonlum Road
Sulta307
Timonium 21093
Tel: (301) 252-7742
TWX: 710-232-1807

Dayl'm45415
Tal: (513)890-5350
TWX: 810-45{}-2528
InleICorp.'
Chagrin-Brainard Bldg

~~~~~I:n~a~~~ 2~IVd

MISSOURI
Technical Representatives. Inc
Trade Center Bldg
320 Brookes Drive. Suite 104
Hazelwood 63042
Tel: (314) 731-5200
TWX: 910-762-0618

~2J~n~t~~k~

Glen White Associates
3700 Computer Dr., Suite 330
Raleigh 27609
Tal: (919) 787-7016

~~~s~~o;~:\17St
Tel: (201) 985-11100
TWX: 710-480-6238

~~~~!%~!~~2~t
Tel: (503) 641-4111
PENNSYLVANIA
Intel Corp.'
275 Commerce Or.

;~~t~~;~e

Center

Fort Washington 19034

~~(:5~~b_~~~~~~~
Intel Corp.
474 Thurston Roed
Rochestar, N.Y. 14619
Tel: (716)328-7340
TWX: 510-253-3841
T-Squared
4054 NewcourtAve.
Syracuse 13206

!~~:t~~~;7:~:way
Tel: (713) 784-3400
MycrosystemsMarkatlnglnc.
13777 N.Cantral Expr&ssway

t~ill:s4~~243

:::~P~:6-~~~:~~~~
MycrcsystamsMarketlng Inc.
~~~~ro~'ii~3~venue, Suite 125
Tel: (713) 7B3-2000
Intel CorP.'

~~~t~ ~J'I/ FrBflway
Oallas75234
Tal: (214) 241-9521
TWX: 910-860-5487

Tel: (216) 464-2736
OREGON
ES/ChaseCompany

i~)2~15J_~~~:~~ii

NEW YORK
Intel Corp,'
350 Vanderbilt Motor Pkwy.
suite 402
Hauppaugal1787

TEXAS
Intel Corp.

TENNESSEE
Glen WhIle Associates
Rt. #12, Norwood 5/0
Jonesboro 37659
Tal: (615)477-6850
Glan White Associates

Glen White Associales
P.O.Bc' 1104
Lynchb~rg 24505
Tel: (804) 384-6920
Glen White Associates

~~I~~'i~O~e!~~

22443
Tel: (004) 224-4B71

~:~ /~~:s:O~~

..
SeattiagOl08
Tel: (206) 762-4624
Twx: 910-444-2298
WISCONSIN
Intel Corp
4369 S. Howell Ave.
Milwaukee 53207
Tel: (414) 747-0769

~!~~~~t~!:~ 3~~~~

Tel: (901) 754-0463
Glen White Asscciates
6446 Ridge Lake Road
Hixon 37343
Tel: (615) 642-7799

i~li;6 ~:t~;~~
T-Squared
642 Krea9 Road
P.O. BoxW
Pittsford 14534

i~I~Ji~ ~7~::8~005

Intal Corp.
70 Chamberlain Ave.
Ottawa, Ontario K1S lV9
Tel: (613) 232-8576
TELEX;053-4419
Multitak, Inc.'
15 Granfall Crescent
Ottawe, Ontario K2G OG3
Tel: (613) 226-2365
TELEX: 053-4585

EUROPEAN MARKETING OFFICES
BELGIUM
Intellnlernatlonal'
Ruedu Moulin IiPapler
51-Bolte 1
B-1160 Bruasels
Tel: (02)6603010
TELEX: 24814

FRANCE
Intal Corporation, S.A.R.L."
5 Place de laBalance
Sllic 223
94528 RUngis Cedex
Tel: (01) 6872221
TELEX: 270475

SCANDINAVIA
Intel Scandinavia A/S'
Lyngbyvej 322nd Floor
DK-2100 Copanhegen East
Denmark
Tel: (01) 162000
TELEX: 19567
Intal Sweden AB'
Bo~ 20092

~~:~~ Bromma
Tel: (08) 985390
TELEX: 12261

ENGLAND

~nr~:t~~l~¥g~E ~~':~) Ltd.'
Cowley. OXford OX4 3NB
Tel: (0665) 77 14 31
TELEX:e37203
Intel Corporation (U.K.) Ltd.
46-50 Beam Street
Nantwlch,CheshlreCW55LJ
Tel: (a2701 6265 sa
TELEX: 36620

ORIENT MARKETING OFFICES
JAPAN
Intal Japan Corporation'
FlowarHIIt-Shlnmachi East Bldg,
1-23-9, Shlnmachl, Sata9aya-ku
Tokyo 154
Tel: (03) 426-9261
TELEX: 781-2B426

TAIWAN
Taiwan Automation Co.'
2nd Floor. 224
Nanking EaslRcad
Section 3
Taipei
Tel: (02) 7710940-3
TELEX: 11942TAIAUTO

HONG KONG
China Electronics
Sea Bird House, 9th Floor
22-2BWyndham Street
Hcng Kong
SINGAPORE
General Engineers Associates
37, Hilt Street
Sinllspore6

KOREA
Koram Digital
Sam Yung Bldg. #303
~~;u~~~ghang - Dong Chung-Ku

GERMANY
Intal Semiconductor GmbH'
Seidlstrasse 27
8000 Muenchen 2
Tel:(089)558141
TELEX: 523177
Intel Semiconductor GmbH
Abraham Lincoln Strassa30
6200Wiesbadenl
Tel: (06121) 74B55
TELEX:041061B3
Intel Semiconduclor GmbH
Ernsthaldenstrasse17
D-7000 Stutlgart60
Tel: (0711) 7351506
TELEX: 7255346
Intel Vertri~bsburo
HindenburgerStrassa 28/29
3000 Hannover
Tel: (0511)852051
TELEX: 0923625

te~1>~0:0~n~~~6ational, Inc.
112-25, Sokong-Dong
Chung-Ku, Seoul

INTERNATIONAL DISTRIBUTORS

~~.~~~~~NA
Av. Pte. Rogua Saenz Pena 1142 98
1035 Buenos Airas
Tal: 35-6784
AUSTRALIA
A.J.F. Systems & Components

:I~~;;p~·C! Rd.
Prospact5082
South Australia 17005
Tel: 269-1244
TELEX: 82635
A.J.F. Systems & Components
PTY. LTD.

~i~:~;l~~2BVl

~n~~~I~~19IUm

S.A
Avenue Val Duches88, 3
B-1160 Brussels
Tel: (02)660 00 12
TELEX: 25441
DENMARK

~s~~saork~~~ponent A/S
2860Soborg
Tel: (01) 67 00 77
TELEX: 22990
Scandinavian Semicnndllctllf
Supply A/S
Nannasgade 18

~~~2(~~~ ;3o~g~~agen N

TELEX: 24908
A.J.F. Systems & Ccmponents
PTY. LTO.

TELEX: 19037
FINLAND
Oy Fintronlc AB

¥:I:b~i~~i7:~~ria 3000

~:~£~if~;:katu 350

TELEX: 30270
Tel: (90) 664 451
Warburton-Fronk; (Sydney) Pty. Ltd. TELEX: 12426
199 Parramatta Road
FRANCE
Celdls
Auburn, N.SW.2114
Tel: 648-1711, 648-1381
53, Aue Charles Frerot
94250 Gentilly
TELEX: WARFRAN AA 22265
Warburtcn-Frankl Industries
Tel:5S1 0020-581 0469
(Melbourne) Pty. Ltd.
TELEX: 200 4B5 F
220 Park Street
Melrologle
South Melbourne, Victoria 3205
La Tour d·Asniares
4. avenue Laurent Cely
Tel: 699-4999
TELEX; WARFRAN AA 31370
92606 Asnieres
Tel: 7914444
AUSTRIA
TELEX: 611 448 F
Tekelec Airlronic"
Bacher Elektronischa Gerale GmbH

~~~d~6n?f~n~!UPlStrasse 78

~~: g~I:~:r~~t

Tel: (0222) 83 63 96
TELEX: (01) 1532

92310$evres
Tel:(1)0277535
TELEX: 250997

"Note Naw Telephone Numbar

GERMANY
Allred Neya Enatachnik GmbH
Schilterslrasse14
0-2085 Quiokborn-Hamburg
Tel: (04106) 6121
TELEX: 02-13590
Electronic 2000 Verlriebs GmbH
NeumarkterStrasse75
O-BOOOMuenchen 80
Tal: (089) 434061
TELEX: 522561
Jermyn GmbH
Poslfach1146
0-6277 Kamberg
Tel: (06434)6005
TELEX; 484426
INDIA
Electronics International

~;~u~~~~:~:dGandhl

Rcad

~i~{r~~J~co
ISRAEL
EastronlcsLtd.·
11 Rozanis Street

~it)~~~~::O
ITALY
Eledra3SS.P.A."
V,ale Elvazia. 18
20154 Milan,
Tel: (02) 3493041
TELEX: 39332
Eledra3SS,P.A.'
Via Paolo Gaidano. 141 D
10137 Torino
TEL:(011)3097097-3097114
Eledra3SS,PA'
Via Giusappe Valmarana, 63
00139 Rome, Italy
Tel: (06)8t 27290_S1 27324
TELEX: 63051

JAPAN
Pan Electron
No.1 Higashlkata-Machi
Midori·Ku. Yokohama 226
Tel: (045)471-8811
TELEX: 781_4773
Ryoyo Electric Corp.
Konwa Bldg.
1-12-22, Tsukljt, l-Chome
Chua-Ku, Tokyo 104
Tal: (03) 543-7711
Nippon Micro Computar Co. Ltd.
Mutsumi Bid!!. 4-5-21 Kojimachl
Chiyoda-ku, Tokyo 102
Tel: (031230-0041
NETHERLANDS

~;~c~I~:t~~~li~nd

SOUTH AFRICA
Electronic Building Elaments
P.O. Box 4609
Pretoria
Tel: 78 9221
TELEX: 30t81

~n'::~~ce"

Ronda San Pedro 22
Barcelona 10
Tal:3017851
TELEX: 515081FCE E
SWEDEN
~~~~iSk Elactronik AB
S-10380 Stockholm 7
Tel: (OB) 240340
TELEX: 10547

Joan Muyskenweg 22
NL-l006 Amsterdam
Tal: (020) 934824
TELEX: 14622

SWITZERLAND

MEW ZEALAND
W. K. McLean Ltd
103-5 Felton Matthew Avenue
Glenn Innes, Auckland

CH-B021 Zurich
Tel: (Ql) 60 22 30
TELEX: 5678B

:::~I~J'~;-~i;763

UNITED KINGDOM
Rapid Recall. Lt
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date                     : 2012:12:14 10:43:37-08:00
Modify Date                     : 2012:12:14 11:40:21-08:00
Metadata Date                   : 2012:12:14 11:40:21-08:00
Producer                        : Adobe Acrobat 9.52 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:0ba34cdf-8933-43b7-8587-0738a30532b9
Instance ID                     : uuid:5883840f-1676-4251-954e-5ed52c7ab538
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 468

EXIF Metadata provided by EXIF.tools