AL39 0_MULTICS_Processor_Manual__Oct75 0 MULTICS Processor Manual Oct75
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AL39-0_MULTICS_Processor_Manual__Oct75 AL39-0_MULTICS_Processor_Manual__Oct75
User Manual: AL39-0_MULTICS_Processor_Manual__Oct75
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Honeywell
HONEYW ELL INFORMATION SYSTE MS
Multics
Processor
Manual
SUBJECT.
Description and Use of the "uttlc'S Processor.
SOFT'WARE
SUPPORTED.
All Multlcs Software Releases
DATE.
October, 1975
ORDER NU"BERI
Al39, Rev. 0
PREfACE
This document describes the Processor used in the Kultlcs system.
It _s
assumed that the reader is familiar with the overall modular or9~nlzatlon of the
Hultlcs system and with the philosophy of asynchronous operation. In additlo~.
this manual presents a thorough discussion of virtual memory addressing conc.pt~
including segll.entation and paging.
'
.
The manual Is Intended for use by system programme~s responsible for
writing software to interface with the special virtual memo~y hardware an~ "lth
the fault and lnterruJ)t portions of the hardware. It should also prove "a"ua~l.
to
programmers w~o must use machine instructions (particularly language
iranslator i.plementors) and to those persons responsible for analyzing cra~h
conditions in System Dumps.
c
197~
Honeywell Information Svstems9 Inc.
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
il
AL39
CONTENTS
Page
Section I
Introduction To Processor • • • • • • • • • • • • • • • •
features of the Hultics Processor • • • • • • • • • •
Seg.entat 1 on and Pag Ing. • • • • • • • • •. •• • •
Address Modification and Aadress Appending • • • •
Faults and Interrupts • • • • • • • • •
Summary of Processor Features. • • •• • • • • • •
Processor Hodes of Operation • • • • • • •
Instruction Hodes.
• ••••••
Normal Hode • • • • • • • • • • • • • • • • • •
Privileged Hode •
• •••••• • •••••
Addressing Modes • • • • • • • • • • • • • • • • •
Absolute Hode • • • • • •
• •• • • • • • •
Append Hode •
• ••••
Bar ~ode. • • • • • • • • • • • • •
Processor Unit Functions. •
• •••• • •••••
Appending Unit • • • • • • • • • • • •
Associative Hemory Assemblies • • • • •
Control Unit • • • • • •
• ••••
Operation UnIt • • • • • • • • • • • • • • • • • •
Decimal Unit • • • • • • • • • • • •• • • • • • •
· .....
·· .....
. . . . ..
.....
·· .....
··· ... ... ... ... ...
Sedtlon II
Machine Instructions. • • • • • • • • • • •
• •••
Instruction Repertoire • • • • • • • • • • • • • • • •
Bas lc Operat1ions • .'. • • • • • • • • • • • • • •
Extended Instruction Set (EIS) Operations • • • • •
EIS Single-Word Operations • • • • • • • • • • •
EIS Hulti-Word Operations • • • • • • • • • • •
Format of Instruction DescriptIon • • • • • • • • • •
Definitions of Notation and Symbols • • • • • • • • •
Hain Store Addresses • • • • • • • • • • • • • • •
Index Values • • • • • • • • • • • • • • • • • • •
Abbreviations and Symbols • • • • • • • • • • • • •
Register POSitions and Contents • • • • • • • • • •
Other Symbols • • • • • • • • • • • • • • • • • • •
Arrangement of Instructions • • • • • • • • • • • • •
Common Attributes of Instructions • • • • • • • • • •
Illegal ModificatIon • • • • • • • • • • • • • • •
Parity Indicator • • • • • • • • • • • • • • • • •
Instruction Word Formats. • • • • • • • •
• •••
BaSic and EIS Single-Word Instructions • • • • • •
Indirect Words • • • • • • • • • • • • • • • • • •
1-1
1-1
1-1
1-2
1-2
1-2
1-3
1-3
1-3
1-1t
I-It
I-It
I-It
1-1t
1-5
1-5
1-5
1-6
1-6
1-6
2-1
2-1
2-1
2-1
2-1
2-2
2-2
2-1t
2-1t
2-1t
2-1t
2-5
2-6
2-6
2-6
2-6
2-6
2-7
2-7
2-8
•
EIS "ulti-Word Instructions • • • • • • • • • •
EIS "oalfication Fielas (HF) • • • • • • • • • • •
EIS Operand Descriptors ana Indirect ~ointers • • •
Operand Descriptor Indirect Pointe- For.at • • •
AJphanumeric Operand Descriptor Fo-mat • • • • •
Numeric Operand Descriptor Format • •
• ••
Bit String Operand Descriptor Format • • • • • •
Fixed' Point Arithmetic Instructions • • • • • • • • •
Data Hovement Load Instructions.
• ••••••
Data Movement Store Instructions • • • • • • • • •
REVIEW DRAFT
SU8JECT TO CHANGE
October, 1975
Iii
2-9
2-9
2-11
2-11
2-12
2-11t
2-15
2-16
2-16
2-25
AL39
CON TENTS (Conti
Page
Data Mo~e.ent Shift Instructions • • • • • •
Addition Inst~uctions • • • • • • • • • • • • •
Subtraction Instructions • • • • • • • • • • • • •
Multiplication Instructions • • • • • • • • • • • •
Division Inst~uctions • • • • • • • • •
• ! • • •
Negate Instructions • • • • • • • • • • • • •
• •
ComparIson Instructions • • • • • • • • • • •
• •
Miscellaneous Instructions • • • • • •
•
•
•
•
Boolean Operation InstructIons • • • • • • • •
• •
AND Instructions. • • • • •
• •• •
• •
•
OR.Instructions • • • • • • • • • • • • • • •
•
Exclusive OR Instructions • • • • • • • • • • • • •
Comparative AND Instructions
•••••••••
COMparative NOT Instructions
•••••••••
Floating Point A~ithmetic Instructions • • • • • • • •
Data Hovement load Instructions • • • • • • • • • •
Data Hovement Store Instructions • • • • • • •
AdditIon Instructions. • • •
• ••••••••
Subtraction Instructions • • • • • • • • • •
MultIplication Instructions • • • • • • • • • • • •
Division Instructions • • • • • • • • • • • • • •
Negate Instructions. •
• ••••••••••
NormalIze InstructIons.
• ••••••••••
Round Instructions. • • • • • • • • •
• •••
Compare Instructions • • • • • • • • • • • • • • •
HI scellaneous Instruct ions • • • • • • • • • • • •
Transfer Instructions • • • • • • • • • • • • • • • •
Pointer RegIster InstructIons • • • • • • • • • • • •
Data Movement load Instructions. • • • • • • • • •
Data Movement Store Instructions
Address Arith~etic Instructions.
Miscellaneous Instructions • • •
Miscellaneous Instructions • • • • . • • ••
Calendar Clock Instruction. ••
Derail Instruction. • • • •
• •••••
Execute Instructions • • • • • • • • • • • • • • •
Master Hode Entry Instructions • • • • • • • • • •
No Operation Instructions. • • • • • •
• ••
Repeat Instructions • • • • • • • • • • • • • • • •
RIng Alarm Register Instruction • • • • • • • • • •
Store Base Address Register InstructIon • • • • • •
Translation Instructions • • • • • • • • • • • • •
Privileged Instructions. • • •
• ••••••••
Register Load Instructions • • • • • • • • •
Register Store Instructions • • • • • • • • • • • •
Clear Associative Memory Instructions • • • • • • •
Configuration and Status Instructions • • • • • • •
System Control InstructIons• • • • • • • • • • • •
Hiscellaneous Instructions • • • • • • • • • • • •
· ·
· ·· ··
· ·· ·
. . . . . . ..
·· .......
.......
.
·
.
.
· . . . . . ...
2-3"
2-40
2-48
2-55
2-57
2-60
2·61
2-66
2-61
2-67
2-70
2-73
2-76
2-78
2-80
2-80
2-81
2-84
2-87
2-90
2-93
2-97
2-98
2-99
2-101
2-103
2-105
2-117
2-117
2-1212-12"
2-125
2-126
2-126
2-127
2-128
2-130
2-133
2-115
2-14"
2-1"5
2-146
2-14'
2-148
2-155
2-162
2-164
2-167
2-111
•
Extended Ins~ructlon Set (EIS) • • • • • • • • • • • •
Address Register Loae Instructions • • • • • • • •
Address ~egister Store Instructions • • • • • • • •
Address Register Special Arithmetic InstructIons.
Alphanumeric Compare Instructions • • • • • • • • •
Alphanumeric Hove Instructions • • • • • • • • • •
Numeric Compare Instruction • • • • • • • • • • • •
Numeric Hove Instructions • • • • • • • • • • • • •
Bit String Combine Instructions • • • • • • • • • •
Bit String Compare Instructions • • • • • • • • • •
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
iv
2-172
2-172
2-175
2-178
2-186
2-197
2-205
2-208
2-213
2-217
AL39
CONTENTS (Cont)
Page
Bit String Set Indicators Instructions • • • • • •
Data Conversion Instructions • • • • • • • • • • •
Decimal Addition Instructions • • • • • • • • • • •
Decimal Subtraction Instructions • • • • • • • • •
Decimal Multiplication Instructions. •
• •••
Decimal Division Instructions • • • • • • • • • • •
Micro Operations for Edit Instructions • • • • • • • •
Micro Operation SeQuence
•••••••••••
Edit Insertion Table • • • • • • • • • • • • • • •
EdIt Flags • • • • • • • • • • • • • • • • • • • •
Terminating Micro Operations • • • • • • • • • • •
"VNE and HVE Differences • • • • • • • • • • • • •
Numeric Edit • • • • • • • • • • • • • • • • • •
Alphanumeric EdIt
•••••••••••••
Micro Operators. • •
• ••••••••••••
Micro Operation Code Assignment Map • • • • • • • •
Sect ion III
Section tv
/
Data Representation • • • • • • • • • • • • • • • • • • •
Information OrganIzation. •
• ••••••
POSitIon Nu_bering • • • • • • • • • • • • • • • • • •
Number Syslem • • • • • • • • • • • • • • • • • • • •
Information Formats • • • • • • • • • • • • • • • • •
Data Parity • • • • • • • • • • • • • • • • • • • • •
Representation of Data.
• ••••••••••••
Numeric Data • • • • • • • • • • • • • • • • • • •
Fixed Point Binary Data • • • • • • • • • • • •
Fixed Point BInary Integers. • • • • • • • •
FiKed Point Binary Fractions • • • • • • • • •
Floating Point Binary Data. •
• •••••
Over length Registers • • • • • • • • • • • •
Normallzed Numbers • • • • • • • • • • • • •
Decimal Data. • • • • • • • • • • • • • • • • •
Decimal Data Values • • • • • • • • • • • • •
Decimal Zero • • • • • • •
• •••••
Alphanumeric Data • • • • • • • • • • • • • • • • •
Character String Data • • • • • • • • • • • • •
Bit String Data • • • • • • • • • • • • • • • •
3-1
3-1
3-1
3-1
3-2
3-1t
3-5
3-5
3-5
3-5
3-&
3-8
3-9
3-9
3-11
3-13
3-14
3-11t
3-1"
3-15
4-1
• • ··•
·
•
•
•
•
"-2
· ·· • • • • ·• ·•
• • • •
• •
"-3
·
·
·
•
•
•
•
•
•
•
•
•
•
· · ·
• • • •
· · ·· •• •• ·• ·· •• •• •• •• ·• •• ·• •• "-5
• • · • • • • • • • • •
Program Accessible R.egisters • •
Accumulator Reglster (A). • •
Quotient Register (Q) • • •
Accumulator-Quotient Register
EKponent Register (E) • • •
Exponent-Accumu I ator-Quot ient
IndeK Registers (Xn).
•
Indicator Register (IR) • •
Base Address Register (BAR) •
• • • • • •
• • •
•
• • • •
(AQ) •
Register (EAQ).
Timer Register (TR) • • • • • • • • • ••
• ••••
Ring Alarm Register (RALR) • • • • • • • • • • • • • •
POinter Registers (P~n) • • • • • • • • • • • • • • •
Procedure Pointer Register (PPR) • • • • • • • • • • •
Temporary POinter R.egister (TPR). •
• ••••••
Desiriptor Segment Base Register (DSBR.DBR) • • • • •
Segment Descriptor Word ASSOCiative Hemo~y (SDMAH) • •
Page Table Word Associative Hemory (PTWA~).
• ••
Fault Register. • • • • • • • • • • • • •
• ••••
Hode Register 'HR). •
• ••••••••••••
REVIEW DRAft
SUBJECT TO CHANGE
October, 1915
2-219
2-221
2-225
2-231
2-23"
2-237
2-2"0
2-2"0
2-2 ..1
2-2"1
2-2 .. 2
2-2lt2
2-242
2-242
2-21t3
2-250
v
1t-2
..-It
It .....
It-S
1t-9
·"-9
1t-10
1t-11
1t-13
"-15
1t-16
1t-18
1t-21
1t-23
1t-25
AL39
CONTENTS (Cont)
Cache Hode Register (CHR) • • • • • • • • •
• ••
Control Unit (CU) Hlstory Registers. • •
• ••
Operations Unit (OU) History Registers • • • • • • • •
Decimal Unit (OU) History Registers • • • • • • • • •
Appending Unit (AU) History RegIsters • • • • • • • •
Configuration Switch Data • • • • • • • • • • • • • •
Contro I Uni t Data
••••••••••••••••
Decimal Unit Data • • • • • • • • • • • • • • • • • •
Section V
Section VI
--
· ·• •• ·• ·• ·• •• ••
·
·
·
·
• · ·• ·•
·
·
·
·
•
• • • •
·
·
·
·
·
·
·
·
·
.
•
•
. . . . ·· · · · · · · ·· · · · ·· · ·· .-• •• ••
• • • ·
., · · ·· · · ·· ·· · · ·· ·· •• ·...
• • •
• •
· ·· ·· ·• • • • ·• •• ••
·· ····• ·• •
AddressiQg
Segmentation and Pag Ing. •
Address ing Hodes.
•
•
Absolute Hode.
•
• •
Append Mode.
•
•
• •
•
Segment at Ion.
•
•
•
•
Paging.
• •
•
Changing Addressing Hodes
•
• •
Address Apl?endi ng
•
•
Address Appendlng Sequences. • •
Appending Unl t Data Word Forllats.
Segllent Descriptor Word (SOW) Format
Page Ta,b' e Word (PTW) Format
•
Effective Address Formation • • • • • • • • • • • • • • •
Definition of Effective Address • • • • • • • • • • •
Types of Effective Address Formation.
• •••••
Effective Address Formation Description • • • • • • •
Effective Address Formation Involving Offset Only • •
The Address Modifier (TAG) Field • • • • • • • • •
General Tvpes of Offset Modification. •
• ••
Effective Address Formation Flowcharts • • • • • •
Register (R) Modi f icat ion • • • • • • • • • • • • •
Register Then Indirect CRr) Modification
•••
Indirect Then Register (IR) Modification • • • • •
Indirect Then Tally (IT) Modification • • • • • • •
Effective Address Formation Involving Both
Segment Number and Offset • • • • • • • • • • • • •
The Use of Bit 29 of the Instruction Word • • • • •
Special MOdifiers • • • • • • • • • • • • • • • • •
Indirect to Pointer Citp) Modification • • • • •
Indirect to Segment (Its) Modification • • • • •
Effective Segment Number Generation • • • • • • • •
Effective Address Formation for Extended
Instruction Set • • • • • • • • • • • • • • • • • •
Character- and Bit-String Addressing.
• ••
Character- and Bit-String Address Arithmetic
Algorithms • • • • • • • • • • • • • • • • • • •
9-Bit Character String Address Arithmetic • • •
1t-28
1t-29
1t~32
1t-31t
1t-37
1t-39
1t-40
it-itS
5-1
S-1
5-1
5-2
5-2
5-3
5-6
5-7
5-7
5-10
5-io
5-11
6-1
6-1
6-1
6-2
6-2
6-2
6-2
6-4
6-,.
6-6
6-8
6-9
6-15
6-16
6-16
6-17
6-18
6-19
6-21
6-23
6-23
6-24
•
6-81t Character String Address Arlthlletic • • •
4-Blt Character String Address Arithmetic • • •
Bit String Address Arithmetic • • • • • • • • •
Section VII
REVIEW DRIFT
TO CHANGE
October, 1915
· ·· · · ·• ·· ·· ·· ·· ·· ·· ·• ·· ·• ·· ·• ·•
· ·· · · · · · · • · ·• ·· ·· ·· ·• ·· ·· ·· ·•
···· ····• ···• ·•
Faults and Interrupts.
Faul t Cycle Sequence.
Faul t Priority.
F au' t Recogni t1 on
•
Faul t Oescr ip ti ons.
7-1
7-1
7-2
1-3
7-4
SUB~ECT
vi
AL3CJ
,
CONTENTS (Cont)
Page
Group 1 Faults
•••••
Group 2 Faults.
• • • •
• ••
Group 3 Fau.ts
• • •
• ••••
Group 4 Faults
••••••••••
Group 5 Faults
••••••••••
Group 6 Faults
••••••••••
Group 7 Faults. • •
• ••••
PrograM Interrupts and External Faults • •
Execute Interrupt Sampling.
•
Execute Interrupt Cycle SeQuence • • •
Sec t ion VIII .
Section IX
· •• ·· •• ·•
· ·• ·· ·• .'•
• •
• • • •
• •
· ·•• ·•• •• ·•
·• ·• •
•
• •
•
• •
• •
• •
• •
•
• •
•
7-It
7-It
7-5
7-5
7-6
7-7
1-7
7-8
7-8
7-CJ
Ring Implementation.
• •
• •••••
Ring Protection Philosophy • • • • • • • • • • • • • •
Ring Protection in Multics. • • • • •
• •••••
Ring Protection In the Mu.tics ProceSsor • • • • • • •
Appending Unit Operation with Ring Hechanlsm • • • • •
8-1
1-1
8-1
1-2
Cache Store Operation. • • • • • •
• ••••••••
Philosophy of Cache Store • • • • • • • • • • • • • •
Cache Store Organization. •
• ••••••••
Cache Store/Hain Store Happing • • • • • • • • • •
Cache Store Addressing • • • • • • • • • • • • • •
Cache Store Control • • • • • • • • • • • • • • • • •
Enabling and DisablIng Cache Store • • • • • • • •
Cache Store Control in Segment Descrlptor Words • •
Loading the Cache Store.
• ••••••••••
General C I ear • • • • • • • • • • • • • • • • •
Selective Clear. • •
• ••••••
Dumping the Cache Store • • • • • • • • • • • • • •
9-1
9-1
9-1
9-2
Hard~are
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
vii
8-1t
9-1t
C)-It
g-It
9-5
9-6
9-6
9-7
9-7
Al3CJ
CONTENTS' (Cont)
Page
·.... ·..
·.·. • • • • • • · ..
· .. . . . .. .. .. . . . . . ..
Appendix A
Operation Code Hap • • • • • •
A-l
e
Alphabetic Operation Code List
B-1
Address Modifiers.
C-l
Appendix
Appendix C
ILLUSTRATIONS
Figure 2-1
2-2
Figure 2-3
Figure 2-4
Figure 2-5
Figure 2-6
Figure 2-1
Figure 2-8
Figure 2-9
Figure 2-10
Figure 2-11
Figure 2-12
F~gure
Figure 2-13
Fig"re 2-14
Figure 2-15
Figure 2-16
Figure 2-17
Figure 2-18
Figure 2-19
Figure 2-20
FIgure 2-21
Figure 2-22
Figure 2-23
Flgure 2-2"
Figure 2-25
Figure 2-26
· · · · · · ·· · · · · · ·
· · ···
·· ·· ·· ·· · · ·· ··· ·
····· ·
· · ·
··· · ·· ···· · ·· · ··
Basic and EIS Sin11e-Hord Instruction For-mat
• •
•
Indirect Word Format
•
•
•
• • • • • • •
EIS Hulti-Hord Ins truct I on Format. •
• •
• • •
• •
EIS Modification Field (MF) Format •
•
•
•
Operand DescrIptor IndIrect Pointer Format • •
• •
Alphanumeric Operand DescrIptor Format
• • •
•
•
Numeric Operand Descriptor Format. •
• • •
• • •
Operand
Descriptor
Bit String
Format
•
•
Repeat Double (RPD) Instruction Word Format.
• •
•
Repeat LInk (RPL) Instruct ion Word Format. • • •
•
Repeat (RPT) Instruction Hord Format • •
• •
•
• •
EIS Addre.ss Register Special ArithmetiC Instruction
Format.
•
•
•
• •
• •
Compare Alphanumeric Strings (CHPC) EIS Multi-Word
Instruction Format. •
•
•
•
• •
Scan Characters Double (SCD) EIS Multi-Word Ins truct ion
Format.
•
• •
• •
• •
• •
• • •
Scan with MaSk ( SCM) EIS Multi-Woro Instruction Format •
Test Character and Translate (TCn EIS Multi-Word
Ins truc t 1 on Format.
•
•
• • •
• • • • • •
Move Alphanumeric Left to Right CHLR) EIS MJ.tl-Word
Ins truc t 1 on Format.
• •
• • •
• •
•
Move Alphanumeric Ed Hed (MVE) EIS Multi-Word
I nstruc t ion Format.
• •
•
Move Alphanumeric with Translation (MVT) EIS Mu I t i-Word
Instruction Format.
• • • • • •
• •
• •
Compare Numeric (C MPN) EIS Multi-Word InstrJctlon For.at
Hove Numeric (HVN) EIS Mu I ti-Woro Instruction Format
•
Move Numeric Edi te d (HVNE) EIS Hulti-Hord I~struction
Format.
•
•
• •
• • • • •
Combine Bit Strings left (CSL) EIS Hult i-Word
Instruction Format. •
• •
•
•
• •
•
Compare Bit Strings (CHPB) EIS Multi-Word I~struction
Format.
• •
•
•
•
Binary to Decimal Con"ert rBTo) EIS Hut t i-W!)rd
Instruction Format.
•
•
•
• • • • • • •
Oeci mal to Binary Convert (OrB) EIS Hulti-Word
··
···· ·· ·
· ·· · ·· ·· ·· ·
·· ·· ·
·
·
··· · ·
···· ·· ···
·· ·
····· · ·
·
· ··· · ·· · ·
·· ·
· · ·· · · ·
···· · ··· · ···· ·· ···
·· · ··· ·
2-1
2-8
2-9
2-10
2-12
2-12
2-1"
2-15
2-13'1
2-138
2-1"1
2-118
2-186
2-188
2-191
2-19"
2-197
2-200
2-202
2-205
2-208
2-211
2-213
2-217
2-221
•
Figure 2-27
Figure 2-28
Figure
Figure
Figure
Figure
Figure
2-29
3-1
3-2
3-3
3-"
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
Instruction' Forllat • • • • • • • • • • • • • • • • • •
Add Using 2 Decimal Operands (A020) EIS Hulti-Word
Instruction Format • • • • • • • • • • • • • • • • • •
Add Using 3 Decimal Operands (A03D) EIS Hulti-Word
Instruction Format • • • • • • • • • • • • • • • • • •
Micro Operation (~OP) Character Format • • • • • • • • •
Unstructured Machine Word Format • • • • • • • • • • • •
Unstructured Word Pair Format. • • • •
• •••••
unstructured ~-bit Character Format • • • • • • • • • • •
Unstructured E)-bit Characte'r Format • • • • • • • • • • •
viiI
2-223
2-225
2-228
2-240
3-2
3-3
3-3
3-3
AL39
CON TENTS CCont»
Page
Figure 3-5
Figure 3-6
Figure 3-1
Figure 3-8
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
F 19ure
Figure
Figure
Figure
Figure
Figure
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
"-9
4-10
4-11
4-12
4-13
4-14
4-15
Figure
Fig",re
Figure
Figure
FIgure
Figure
Figure
Figure
FIgure
Figure
Figure
FIgure
Figure
FIgure
Figure
Figure
Figure
Flgur-e
Figur-e
Figure
Figure
Figure
Figure
F 19ure
Figure
4-16
4-11
4-18
4-19
4-20
4-21
"-22
4-23
4-24
4-25
5-1
5-2
5-3
5-1t
5-5
5-6
6-1
6-2
Figure
Figure
Figure
Figure
6-10
6-11
8-1
9-1
6-3
6-1t
6-5
&-6
6-7
6-8
6-9
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
•
·
·
·
· · · •
·· ·· ···· · · · · · · · ·
··· · ···· · ·
· · ••
•
· · ·· ·· ·· · · ·· · · •
· · · · · · · · · · · ••
· · ·· ·
·· ·· ·· · ·· ••
•
· · · ·· ·· ·· · · ··· ·· · ·· · ··
· · · · ·· ·· ·· · · · ••
· · · · · ••
· · · · · · · · · · · · · · · · · · ·· ••
· ·· · · ·· · ·· · ·· · ·· ••
· · · · · ·· ·· ·· ••
· ·· · · ·•
·
•
·
·
·
·
·
•
·
· · ·· · ·· · ·· · ·· · · ·· ·· ··· ••
· · · · · · · · ••
· ·· · ·· · · · · ·· ·· ••
· · ·· ·· · · ·· ·· ••
•
·
·
····
··
·· ·· ••
•
·· · · · ·· · · · · ·· · · · ·•
•
Unstructured 9-bit Character- Format. • • • • • •
•
unstructured 18-bl t Half Wor-d Format
• •
•
•
•
Upper l8-bit Half Word Floating Point Binary
Operand
Format.
• •
• • •
• •
lower 18-bit Half Word F I oat ing PoInt Binary Operand
For-mat.
•
•
•
• • • • • •
•
Single Pr-ecision Ftoating Foint Binar-v Operand
Format.
Doub Ie Pr-ecislon Floating POit"!t 8inar-y Operand Format.
Accu mu I at or Register- CA) For-mat.
•
•
• •
Quotient Register (Q) Format
•
•
• • •
Accumulator-Quotient Register (AQ) Forl'llat •.•
•
Exponent RegIster (El For-mat
•
•
Exponent-Accumulator--Quotlent Register- (EAQ) Format. •
Index Register (Xn) Format
• •
Indicator Regis ter- ( IR) Format
•
•
Base Addr-ess Register (BAR) Forllat
•
•
•
Timer Register (TR) Format
•
•
•
•
•
Ring Alarm Register (RAlR) Format. •
•
•
Pointer Regi ster (PRn) Format.
Procedur-e Pointer Register (PPR) For-mat. •
• • •
Temporarv POinter Register (TPR) Format.
• • • •
Descriptor Segment Base Register (OSBR,DBR) Forllat
Segment Descriptor Wor-d Associative Mellory ( SDWAH)
For-mat.
•
•
•
Page Table Word Associative Memory (PTWAH)
Format. •
Fault Register Format. •
•
•
•
•
Hode Register (HR) For-ma,t.
•
•
•
•
•
•
•
Cache Hode Register- (CHR) Forlllat • • •
•
Control Unit leU) Histor-y Register- Forllat. • •
Oper-ations Unit (OU) History Regis ter Format •
Appending Unit (AU) History Register Format.
•
• •
Configur-ation Switch Data Formats.
• •
•
Cont ro' Unit Data format
•
•
•
•
Deci ma 1 Unit Data Format
• •
•
FInal Address Gener-ation for- an Unpaged Segaent. •
EKamples of Page Number FormatIon. '.
•
Final Address Generation for an Paged Segment. • • • •
Appending Un! t Operation Flowchar-t
• •
•
Segment Descriptor Word (SOH) Format
•
•
Page Table Word (PTW) Format
• •
•
• •
Address Hodif ier ( TAG) Field Format.
•
• • • •
Common Effective Address Formation Flowchar-t
• • •
Register Modification Flowchart.
•
• • •
•
•
Register- Then Ind! rect Modification Flowchart. •
• •
Indirect Then Register- Modification Flowchart.
• •
Indirect Then TaJ Iy Hodification Flowchart • •
•
Format of Instruction Word ADDRESS When Bit 29 = 1 •• •
ITP Pointer Pair For-Illat.
•
•
•
ITS Pointer- Pair For-mat.
• •
• • •
•
•
Effective Segment Number Generation Flowchart • • •
EIS Effective Addr-ess Formation Flowchart • • • • •
Complete Appending Unit Operation Flowchart.
Cache Store/Hain Store Mapping • • • • • • • • • •
ix
·· ..
..
·· ..
..
3-1t
3-4
3-8
3-8
3-9
3-9
1t-2
1t-2
"-3
It-It
It-It
4-5
1t-5
4-9
4-9
1t-10
4-11
4-13
It-IS
4-16
1t-18
"-21
4-23
4-25
1t-28
"-29
4-32
1t-31
4-39
1t-.. 1
ft-46
5-3
5-1t
5-6
5-9
5-10
5-11
6-2
6-4
6-6
6-1
6-9
6-15
6-16
~1a
6-19
6-20
6-22
a-It
9-3
Al39
CONTENTS CCont.
Page
TABLES
Table
Table
Table
Table
Table
Table
2-1
2-2
2-3
2-4
2-5
2-6
Table 2-7
Table
Taule
'Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Tabl.
Table
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
"-1
It-2
5-1
6-1
6-2
6-3
6-1t
7-1
R-type Hodifie~s fo~ REG Fields • • • • • • • • • • • • •
Alphanumeric Character Number (CN) Codes • • • • • • • •
Alphanumeric Data Type (TA) Code~ • • • • • • • • • • • •
Sign and Decimal Type (S) Codes • • • • • • • • • • • • •
Relation Between Data Bits and Indlcato~s • • • • • • • •
Control Relations for store Character Instructions
(Nine Bit) • • • • • • • • • • • • • • • • • • • • •
Control Relations for Store Character Instr~etlons
(Six BIt) • • • • • • • • • • • • • • •
• •••••
Default Edit Inse~tIon Table Characters • • • • • • • • •
Micro Operation Code ASSignment Map • • • • • • • • • • •
Fixed Point Binarv Integer Values • • • • • • • • • • • •
Fixed Point BInary Fraction Values • • • • • • • • • • •
Floating Point Binary Operand Values • • • • • • • • • •
Decimal Sign C~aracter Interpretation • • • • • • • • • •
Decimal Data Values • • • • • • • • • • • • • • • • • • •
Character String Data length Lim1ts • • • • • • • • • • •
Processor RegIsters • • • • • • • • • • • • • • • • • • •
System Controller Illegal Action Codes • • • • • • • • •
Appending Unit Cycle Definitions • • • • • • • • • • • •
General Offset Modification Types.. • • • • • • • • •
Register ModificatIon Decode • • • • • • • • • • • • • •
Variations of Indirect Then Tally ModIfication • • • • •
Special Append Hode Address Modifiers. • • • • • • • • •
list of Faults • • • • • • • • • • • • • • • • • • • • •
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..
2-10
2-13
2-13
2-1,.
2-21
2-28
2-30
2-2lt1
2-251
3-6
3-7
3-10
3-12
3-13
3-1"
1t-1
1t-25
5-8
6-3
6-5
6-10
6-17
7-3
AL39
SECTION I
INTROOUCTION TO PROCESSOR
The -Processor~ described iri this reference manual
Is a hardware module
designed for use with the HUL!iplexed Information and komputing ~ervlce
(Multics). The many distinctive features and functions of H~ltics are enhanced
by the powerful hardware features of the Processor. The add-essing features. In
particular, are designed to permit the Hultics software to compute relative and
absolute addresses, locate data and programs in different devices. and retrieve
such data and program as necessarv.
The Multics Processor contains the following general featuresl
~1.
Storage protectIon to place access restrictions on speclfied seg.ents.
2.
Capability to interrupt a process In execution In response to an
external Signal
(e.g., tlO terminatIon) at the end of any evenlodd
Instruction pair (mid-instruction interrupts are permitted for
50.e
instructions),
to save Processor status, and to restore the status at
a .ater time without loss of continuity of the process.
3.
CapabilIty to fetch instruction pairs and to buffer two instructions
(up to four instructions, depending on certai~ main store overlap
conditions) including the one currently in execution.
4.
Overlapping
-lnstructlon-execution~.
address
preparation,
and
instruction
fetch.
While an instruction is being executed, address
preparation for the next operand (or even the operand following it) or
the next instruction pair is taking place. The operations unit can be
executing instruction N; instruction N+l can be buffered
in the
operations unit (with its operand buffered in a maIn store port); and
the control unit can be executing instructlons N+2 or N+3
(if such
execution does not involve the main store port or registers of
lnstructions N or N+1), or preparing the address to fetch instructions
N+4 and N+5.
5.
Capabilltv to detect ma1n store instructions that alter
the contents
of
buffered instructions.
Ability to delay preprocessing of an
address using register modification if the instruction currently In
.execution changes the register to be used In that .odification.
&.
Interlacing capability to direct maIn store
system controller module.
7.
Intermediate storage of address and control information In
registers addressable by content (Associative Hemo~y).
accesses
to
the
proper
high-speed
REVIEW DRAFT
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1-1
AL3CJ
8.
Intermediate storage of base address and control
Information
pOinter registers which are loaded by the executing prograa.
9.
Absolute address computation at execution time.
In
SPECIAL-'AfAaILll1E~
The Processor also includes several unique capabllties, such as hardMare
implemented segmeniation and paging, address modfication, address appending, and
detection of
faults and external Interrupts.
These features are sum.arlzed In
this section and described in detail respectively in Sections V, VI, and VII.
-Segmentatlon-an~lD~~
A segment Is a collection of data or instructions that Is assigned a
symbolic name and addressed symbolically by the user.
Paging is at the
discretion of the software;
the user need not be aware of
the existence of
pages.
User visible address preparation is concerned with the calculation of a
segment effective address relative to the origin of the segment;
the Processor
hardware
completes address preparation by translatIng
the
final
seg_ent
effective address into an absol~te main store address.
The ~ser may view each
of his segments as residing in an independent maIn store unit.
Each segment has
its
own origin which can be addressed as location %er~.
The size of each
segment varies without affec~lng the addressing of the other segments.
Each
segment can be addressed
like a conventional maIn sto~e image startIng at
Joca$ion zero. Maximum -segment-size~ is 262,1~4 words.
When viewed from the Processor, main store consists of blocks or pages,
each of which is defined as "page-size" words in length.
eThe page size used by
Muftlcs Is 1024 words.)
Each page begins at an absolute address Mhlch is zero
modulo the page size.
Any page of a segment can be placed i~ any available .ain
store block.
These pages may be addressed as jf they we~e contiguous even
though they are in widely scattered absolute locations.
Only currently
referenced pages need be in main store. If a segment is not paged, the coaplete
segment Is located In contiguous blocks of main store. In the current Hultics
Implementation, all user segments are paged.
Address HodlficatioD
Prior to
take placel
1.
~!gdre$s
Appending
each main store access,
-Address-modification~
by
two major phases of address preparation
Register
or
Indirect
Word
content,
If
specified by the Instruction Word or Indirect Word.
-Address-appending@, in which
a
segment
effectIve
translated Into an absolute address-to access main store.
Although the above
two types of
modification are combined in _ost
operations, they are described separately in sections V and VI.
The address
modification procedure can go on indefinitely, with one type of modification
leading to repetitions of the same type or to other types of modification prior
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
1-2
AL39
to a main store access for an operand. However, to simplify the descriptions In
this manual, each type of address modificatIon Is described as if it were the
first (and usuallY the only) modification prior to a maIn st~re access.
fay1J$ and lntecrypts
The Processor detects certain il legal procedures; fault, COMmunication with
the ma 1 n store;
programmed f aul ts;
cert ai n external
events; and ari thllet ic
faults.
Many
of
the
Processor fault conditions are deliberately or
inadvertently caused by the software and do not necessa~llv invo've error.
condl t Ions.
Similarlv, the Processor co~~unicates with the other system modules by
setting and answering external
interrupts.
When a fault or interrupt Is
recognized,
a trap results.
This causes the forced execution of a pair of
l~s~ructions in a main store location, unique to the fault o~
Interrupt,
known
as the fault or interrupt vector. The first of the forced instructions ~ay
;cause safe storage of the Processor status. The second inst~uction in a
fault
vector shoul d be a transfer, or the f au' t lng program wIll be resumed "1 thout the
fault having been processed. -Faults-and-lnterruptsa are described in Section
VII.
Interrupts and certain low priority faults are recognized only at specific
times during the execution of an instruction pair.
If, at these tll1es. the
Processor detects the presence of bit 28 In the Inst~uction Word,
the trap Is
inhibited and program executIon continues. The interrupt or fault signa' 15
save~ for future recognition and Is reset only "hen the trap occurs.
PROCESSQR HODES Qf OPERATION
There are three -modes of maIn store addresslnga 'Abs~lute Hode,
ApDend
Hode, and BAR Hode), and two lIodes of instruction execution (Normal Hode and
Privileged "Dd~). These modes of operatIon and the functions performed .~e
su •• ar!zed in table 1-1.
Iostryctign Hodes
NORHAL HODE
•
Host instructions can be executed In the -Normal-Hodea of operation.
Certain Instructions,c~as~_t!~ as prIvileged. cannot be execu1ed in Normal. Hode.
These are Identified in-The "Indlvidual instruction descriptions. An attempt to
execute prIvileged instructions while in the Normal Hode results in an Illegal
Procedure Fault.
In· the Normal
Hode. various restrictIons are indicated In
Segment Descriptor Words and Page Table Wores, which are explained in Section V.
Address Preparat jon- usest he appending phaSe. The Processor· executes in Normal
Mode when the access bits of the Seg~ent Descriptor Word specIfy a nonprlvlteged
procedure.
REVIEW DRAFT
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1-3
ALJ9
PRIVILEGED HOOE
In Privileged Hode, all Instructions can be executed. Address Preparation
uses the appending phase. The Processor executes in -Privileged-Hode~ when· the
access bits of the Segment Descriptor Hord specif, a privilegeo procedure and
the execution ring is eQual to zero. Refer to· Sections V and VIII for .ore
detailed information.
A~resslQg U~
ABSOLUTE MODE
All instructions can be executed In the -Absolute-Ho~e; and unrestrIcted
is permitted to privileged hardware features.
Address Preparation for
instructIon fetches does ~ use the appending phase. Ourlng instruction
fetches, ~he Procedure Pointer Register is ignored.
acc~ss
The Processor enters Absolute Hode immediately after a fau.t or Interrupt
and remains in Abs~lute Hode until it executes a transfer instruction whose
operand Is obtained via explicit use of the appending mechanism, that Is, via
explicit reference to one of the Pointer Register bV the ~se of bit 29 of the
Instruction Word (See.Append Mode beJo~).
APPEND HOOE
The -Append-Hode" Is the most common I y used lIaln store address 1ng 110 de.
this mode the final
effective segment address Is either added to the
Procedure Pointer Register, or it Is added to one of the eight Pointer
Registers.
If bit 29 of the Instruction Word contains a 0, then the Proeedure
Pointer Register is selected; otherwise, the Pointer Register given by bits 0-2
of the instruction word is selected.
In
BAR "ODE
In -SAR-(Base-Address-Reglster»-Hodea, the l8-blt BAR is used. The 8AR
contains a·O modulo 512 address bound In bit posItions 9-17 and a 0 modulo 512
base address in bit positions 0-8. All addresses are rel3cated by adding the
effectIve segment address to the base address in bits 0-8.
The relocated
addr.ss then becomes the fInal segment efre~tIve address as In Append "od~ and
Is added to the Procedure Pointer Register. A process 15 kept within certain
maIn store lImIts bv subtracting the unrelocated effective address fro. the
•
address bcund in bits 9-17. If the result Is zero or negative,
address would be out of range, and a store Fault oceurs.
REVIEW DRAFT
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October, 1975
the
relocat.'d
AL39
Table 1-1. "odes of Operation
NORMAL
£RIYILEGEp
A8S0LUTE
Execute privileged
instructions.
No
Yes
Yes
No
Main store address for
instruction fetch.
Append
Append
Absolute
Procedure Pointer
Reg ister p I us BAR
base address.
Haln store addrass for
for operand fetch.
Append· Append
Append 1f bit
29 = 1, else
Absolute.
Procedure Pointer
Register plus BAR
base address.
None
Total
fUNCTIONS
Restriction of access
to other seg.ents.
So .. e
PROCESSOR UNIT fUNCTIONS
~"aJor
functions of each principal logic ele.ent are listed below and are,
described In subsequent sections of this aanual.
Controls data input/output to main store.
'erfor.s main store selectIon and interlace.
Does address appending.
Controls fault recognitIon.
This assemblv conSists of sixteen 72-blt Page Table Word Associative Hellory
and sixteen 108-bit Segment Oescripto~ Word Associative
Memorv -(SDWAH)-"eglsterscil These registers are used to hold pointers to lIost
-CPTWAH)-regi~ters~
•
recently used segments (SOWs) and pages CPTWs.. This unit oDviates the need for
possiblel'uttlple main store accesses before obtaining an absolute aaln store
address of ari operand.
REVIEW DRAFT
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October, 1975
1-5
AL39
Performs all Processor control functions.
Perfcrms address modification.
Controls mode of operation (Privileged, Normal, etc •••
Per f arms interrupt recagnl t ion.
Decodes Instruction Words and Indirect Words.
Performs Timer Register loading and decrementing.
Does fixed and floating blnarv arithmetic.
Does shifting and Boolean operations.
Does decimal arithmetic.
Does character- and bIt-string operations.
RlVIEW URlfT
SUBJECT TO CHANGE
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1-6
AL39
SECTION II
HACHINE INSTRUCTtONS
This section describes the cOllprehensive set Of -macnine-instructionsil for the
Hultics Processor. The presentation assumes that the reader is familiar with
the general structure of the Processor, the representation of informatIon. the
data formats, and the method of address preparation. Additional information on
these subjects appear$ near the beginning of this section and in Sections III
through VI.
INSTRUCTION
REeER1D1&~
The Processor interprets a 10 bit field of tl;\e Instru:tlon ; Word as the
Operation Code. ThiS fieJd size vields an instruction universe of) 1021t of ...,ICh
547 are implemented.
The instruction population Is divided ~nto 1t56 Basic
Operations and 91 Extended Instruction Set lEIS) Operations.
Arrangment
of
IostructiQDS
Instructions In thls section are presented alphabeticaJly bv their mneaonlc
codes within fUnctional categories. However, an overal' alpnabetic listing of
Instruction codes aod their names appears in Appendix 3 to aid the use~ in
locatIng specific Instructions via that code.
aasic
ODera~
The 1t56 -basic-operatlonsil in the Processor al. reQui~e exactlv one
machine word and are further subdivided Into the following tiPesl
181
85
31t
36
Fixed Point Binary Arithmetic
800lean Opera~ions
floating Point Binary Arithmetic
Transfer of Control
75
17
28
36-blt
Pointer Register
Hi see II an'eOJS
Privileged
The 91 -Extended-Instruction-Set-(EIS)-Operatjonsil are. futher subdivided
into 62 EIS Single-Word Instructions and 29 EIS Multi-Word I~structlons.
REVIEW DRAfT
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2-1
AL39
EIS SINGLE-WORD OPERATIONS
The &2 -EIS-Single-Word-Instructlons~ load, store, and perform specIal
arithmetic
on
the
Address
Registers
(ARn) used to access bit- and
character-string operands, and safe-store Decimal Unit (DU) control informatIon
required to service a Processor fault.
Like the Basic Operations, EIS
Single-Word Instructions require exactlv one J& bit Machine Word.
EIS MULTI-WORD OPERATIONS
The 29 -EIS-MuJti-Word-Instructions~ perform DecImal
and character-string operations.
Thev require 3 or
depending on individual Operand Descriptor requirements.
and blt3&-blt Machine Words
A~ithmetlc
~
Each Instruction in the repertoire is described in the followIng pa9BS
this sectlon. The descriptions are presented in the format shown below_
INSTRUCTION NAME
MNEMONIC
~FORHATI
OP CODE (OCTAL)
Figure or Figure reference
SUMMARYI
Text and/or bit transfer
MODIFICATIONS:
Text
INDICATORSI
Text and/or logic statements
NOTESI
Text
Line 11
~~C.
of
INSTRU~!InN-~
equ~tlons
OP COPE (OCTAL)
This line has three parts that contain the followingl
1.
Mnemonic --
The
-mnemonic-codew
for
the
Operation
field
of
the
assembler statement.
The HuStics assembler, ALH, recognizes this
value and maps it into t~e appropriate binary pattern when generating
the actual object code.
2.
Instruction Name -- The name of the machine instruction from which the
Mnemonic was deri~ed.
3.
Op Code (Octal) -- The octal value of the operation code for the
instruction.
A
zero or a one in parentheses fo.lowing an octal code
indicates whether bit 27 COP Code extensIon bit) ~f
the instruction
REVIEW OR~fT
SUBJECT TO CHANGE
OctOber, 1915
2-2
AL39
word is OfF or ON.
Line
za
filB.11A.I
The layout and definition of the subflelds of the instr~ctlon· word or words
is given here either as a Figure or as a reference to a Flgu-e.
Line 31
SWit1A.lU
The change in t~e state of the processor affected by tHe execution of the
instruction is described in a short and general IV symbolic fo~m.
If reference
is made to "the state of an indicator in the SUMHARY, it is the state of the
indicator before the instruction is executed.
Those modifiers that cannot be used with the inst~uction are listed
exp I ici t I y as except ions ei the,.. because they are not perm! tted or because th·e lr
effect cannot be predicted from the general
address modification procedure.
(See -Effective Address Formation- in Section VI.)
~
Line 5 I
l.tiD.l.kA.IQRS.
Only those indicators a,..e
listed whose state can be chan~ed by the
execution of the instruction. In most cases, a condition fo,.. setting ON· as well
as one for setting OFF is stated.
If only one of the two is stated,
then the
indicator remains unchanged if
the condition is not Bet.
Unless stated
otherwise, the conditions refer to the contents of regl~ters existing after
instruction execution. Refer also t~ ·Common Attributes of Instructions H , tater
in this section.
Line &1
lWIES
This part of the description exists only In those cases where the SUMMARY
is not sufficient for in depth understanding of the operatio~.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-.3
AL39
Y
= the
V-pair
=a
Y-blockn
=a
18 low order bits of the final 24 bit main store
address of
the instruction operand after all addresS
preparat i on ~ s comp Ie tee
symbol denoting that Y designates a pair of maIn store
locations with successive addresses, the smaller address
be Ing even.
When t he mal n store address is even, It
designates the pair Y(even), Y+l; and when it is odd.
the pair Y-1, Y(odd). The main store location with the
. smalJer (even) address contains the most significant
part of a double-word operand or the first of a pair of
instructions.
symbol denoting that Y designates a block of main
store locations of ~-, 8-, or 16-word extent. Fer a
block of a-word extent, the Processor assumes that
Y-blockO is a 0 modulo 0 address and performs address
incrementing through the block ac:ording'y, stopolng
when the ajdress next reaches a vaJ~e 0 modulo n. Note
the difference between V-block addressing and V-pair
addressjn~ that forces the address to be 0 modu'o Z.
=a
symbol denoting that Y designates a character or
string of characters in main store of character size D
bits as described by the ~th Operand Descriptor.
n is
specIfied by the data type field of Operand Descriptor h
and may have values ~, 5, or 9.
See Section VI,
Effective Address Formation, for details of Operand
Descriptors.
Y-bl
t11
=a
symbol denoting that Y deSignates a bit or string of
bits in main store as described by the ~th Operand
Descriptor.
See
Section
VI.
Effective
Address
Formation. for details of Operand Descriptors.
When reference Is made to the elements 01 a string of characters or bits in
main store, the notation shown In Register POSition and Contents belo ... Is used.
The index used to sho ... traversing a string of extent n may take any of the
values in the interval
(1,0) unless noted otherwise.
The elements of a main
store block are traversed explicitly by USing the index as an addend to the
given block address, e.g, Y-block8+m and Y-block~+Zm.l.
A
ARn
AQ
BAR
REVIEW DRAFT
SUBJECT TO CHANGE
Oc t ober, 1 CJ 75
Accumulator Register
Address Register n (n = 0, 1, 2 •••• , 7)
(consists ofl PRn.WORONOJ:PRn.CHARIIPRn.BITNO)
Combinec Accumulator-Quotient Register
Base Address Register
2-4
AL39
CO
CA
OSSR
DSSR.AODR
DSBR.8NO
OSBR.STACK
DSBR.U
E
EA
EAQ
ERN
ESN
IC
IR
PPR
PPR.PRR
PPR.PSR
PPR.IC
PPR.P
PRn
PRn.RNR
PRn.SNR
PRn.WORDNO
PRn.CHAR
PRn.BITNO
Q
PTWAtt
SOMAM
RAlR
TPR
TPR.CA
TPR.TRR
TPR. TSR
TPR.TBR
TR
Xn
Z
"Contents 0'"
Computed Address
Descriptor Segment Base Register
Descriptor Segment Base Address Register of DS8R
Descriptor Segment Bound Reister of DSSR
Stack Base Register of DSBR
Unpaged Flag of DSBR
Exponent Register
Combined Exponent and Accumulator Registers
Combined Exponent-Accumulator-Quotlent Register
Effective Ring Number
Effective Segment Number
Instruction Counter
Indicator Register
Procedure Pointer Register
Procedure Ring Register or PPR
Procedure Segment Register of PPR
Instruction Counter Register of PPR
Privilege Flag of PPR
POinter Register n en
0, 1, 2, •••• 7)
Ring Number Register of PRn
Segment Number Register of PRn
Word Address Register
PRn
Character Address Register of PRn
Bit Offset Register of PRn
Quotient Register
Page Table Word Associative Memory
Segment Desriptor Word Associative "emort
Ring Alarm ~egister
Temporarv Pointer Register
Computed Address Register of 'PR
Temporary Ring Register of TPR
Temporarv Segment Register of TPR
Temporary Bit Register of TPR
T lmer Register
Index Register n (n = 0, 1, 2 •••• , 7)
Temporary pseudo-result of a nonstore cowparative operation
=
0'
ReqisterPQ$ltlo~Lk.stD.1m1s
(-R- standing for any of the registers listed above as well as for Main
store .. ords. Nord-pal rs, word-b' ocks, and character str lngs.
Ri
the ith bit pOSition of R
RU)
the Ith register of a set of n registers, R
the bit pOSitions 1 through J of R
CrR)
the contents of the full regIster R
•
CeR)!
the contents of the ith bit or character of R
the contents of the bits or characters i through J of R
xx ••• x
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
a string of binary blts (O·s or l·s) of any necessary length
2-5
AL39
When the description of an instruction specifies a chan~e for a part of a
register or main store location, it is understood that the 3art of the register
or maln store location not _enttoned remains unchanged.
-other-Symbolsii}
replaces
->
I
a
compare w lth
the Boolean connective AND
the Boolean connective OR
•
the Boolean connective NON-EQUIVALENCE (or EXCLUSIVE OR)
the Boolean unary NOT operator
not equal
indicates exponentiation Cn and m are Integers);
example, the fifth power of 2 is represented as 2 •• 5.
for
x
multiplication; for example, elY) times :(Q) is
as CCY) x C(Q).
represented
I
dl~ision;
for example, CCY) divided by C(A)
as Cry) I C(A).
represented
II
concatenatIon; for example, strlng1 JJ stringZ.
1 ••• 1
is
the absolute value of the value between vertical bars (no
algebraic sign). For example the absolute value of CIA) Dlus
elY) is represented as. JCIA) + C(Y)'.
COHMON ATTRIBUTES Of IHSTRUCTIONS
Illegal HodificaLl2n
If an -illegal-modifieriil is used wIth any instruction, an Illegal Procedure
fault with a subcode class of Illegal Hodifier occurs.
ear 1 t y
~ilUI:.
The Parity Indicator is turned
has incorrect parity.
RE.VIEW DRAFT
SUBJECT TO CHANGE
Oct ober. 1975
ON
at the end of a
2-6
mai~
store access which
AL39
The -Baslc-I~struct,ons; and -EIS-Single-Word-In$t~uctions; require e~actly
one 36 bit Machine Word and are interpreted according to the format shoMn In
figure 2-1 below.
o
1 1
--L8
Q
J
I
ADDRESS
OPCODE
I
18
Figure 2-1
ADDRESS
Ba~lc
222 3
3
l 1
~
~
I I I
IIIAI
-1.;..1 I
10 1 1
D
I
I
TAG
I
6
and EIS Single-Word Instruction Format
The given address of the Operand or
address may bel
An 18
only)
bIt
Word.
In~lrect
maIn store address If l
=0
This
(Absolute Hode
An 18 bit offset to the Base Address Register If A
CBAR Hode only)
=
0
An 18 bit offset relative to the base of the current
procedure segment If A = 0 (Appendl,g Hode onlv)
A 3 bit PoInter Register number (0) and a 15 bIt offset
to C(PRQ.WORONO) if A = 1 CAbsolute and Appending Hodes
onl y)
A 3 bit Address Register number (0) and a 15 bit offset
CCARo) if A
1 CAli modes dependIng on instruction
type)
~o
=
An 18 bit literal signed or unsigned constant (All
modes depending on instruction type and Hodifier)
An 8 bit Shift Operation count CAli modes)
An 18 offset t~ the current value
Counter CIPRR.IC) CAli modes.
of
the
Instruction
OPCOOE
Instruction operation code.
I
Program Interrupt inhibIt bit. When this bit is set9 the
Processor M,II ignore all e~ternal Program Interrupt
signals. See Section VII, Faults and Interrupts, for
detaIls.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-7
Al39
A
Indirect via pointer registe~ flag.
See Section VI.
F.ffective Address Formation. for detaIls on the use of
POinter Registers.
TAG
Instruction address modifier. See Section VI. Effective
Address Formation, for details on Address Modification.
Indirect Words
Certain of the Basic and EIS Single-Word Instructions permit Indirection to
be specified as part of Address Modification.
When such indirectior. Is
specified, C(~) is iriterpreted as an -Indirect-Word~ according to the fo~rat
shown in Figure 2-2 below.
1 1
0
g
Z~
ADDRESS
I
-
I
I
I
g
I
I
I
TAG
-------12 I
18
ADDRESS
3
5
TALLY
I
Figure 2-2
Z 3
3
I
6
I
Indirect Word format
The given address of the Operand or
This address mav bel
next
An 18 bit main store address If
Instruction Word (Absolute Hode cnlt)
Word.
Indirect
A
=
0
In
the
An 18 bit offset relative to the Base Address Register
(BAR) if A
0 In the Instruction Word (BAR Hode onlv)
=
An 18 bit offset relative to the base of the current
procedure segment if A = 0 (Appending Hode on.~)
An 18 bit offset relative to the origin of the seg_ent
described bv PRO if A
1 in the Instructlon Word and
PRn is selected bV the Instr~ction Word (Absolute and
Appending Modes onlv)
=
TALLY
A count field for use
involve tallying.
TAG
Next address modifler.
REVIEW DRAFT
SUBJECT TO CHANGE
Octobec. 1975
2-8
by
those
Address
Modifiers
that
AL39
The -lIS-Hulti-Word-Instructlons~ require 3 or ~ Machine Words depending on
the Operand Descriptor requirements of the individual instructions.· The ~ords
are interpreted according to the format shown in figure 2-3 3elow.
0
1 1
D
l Ii
222
3
9
~
7_1
I
VARIABLE
a
I I
III
OPCODE
I
I
HF1
I_i
I
I
71
18
10 1
Operand Descriptor or Indirect Pointer for Operand 1
I
I
I
I
Operand Descriptor or Indirect Pointer for Operand 2
I
I
I
Operand Descriptor or Indirec t PoInter for Operand 3
I
J&
Figure 2-3
This fie'd
is interpreted variously according to
requirements of the individual EIS Instructions.
interpretation is given under FORHlT for
each
Ins truct ion.
The Modification Fields HF2 and HF3
contained In this fleld if they are required.
the
Its
EIS
are
OPCODE
Instruction operation code
Single-Word Instructions.
EIS
I
Program Interrupt inhibit
SIngle-Word Instructions.
ttFl
Modification Fjeld 'or Operand Descriptor
Modification Fields (HFl beloM for details.
"VARIABLE
(IS
EIS Mu It i-Word Instruction for.at
ModificA~-Elalds
as(
bit
for
as
BaSic
for
BaSic
1.
and
and
EIS
See
EIS
'HF)
Each of the Operand Descriptors follo~in9 an EIS Hulti-Word Instruct.on
Word has a -Hodificatlon-fleld~ In the Instruction Word. The Hodification Fif·ld
contro I s
the i nterpretat Ion of .the Operand Descriptor. The Hodi f leat Ion FIe I d
is interpreted according to the format shown in Figure 2-4.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-9
ALJ9
a
0 0 0
0
3
Z
-LLa
J I J •
JalbJcJ
I
REG
I
LLl.--1-__ --1
1 1 1
Figure 2-4
U:L
a AR
4
EIS Modification Field eMF)
For~at
Address Register flag. This flag conf~ols interpretation
the ADDRESS field of the Operand Descriptor Just as the
"AM flag controls lhterpretation of the ADDRESS field of
the BaSic and EIS Single-Word Instructions.
of
b
=
Register length control. If RL
0, t~en the Length (N)
field of the Operand Descriptor contai~s the length of the
operand.
If RL
1, then the length (N) field of the
Operand Descriptor contains a se~ector value specifving a
register holding the operand length.
RL
=
c
=
to
Indirect descriptor control. If 10
1 for HF~, then the
hth word foltowing the Instruction Word Is an Indirect
Pointer to the Operand Descrptor for the hth operand;
otherwise, that word is the Operand Descriptor.
REG
The register numbe'" for R-type modification Uf an·v) of
ADDRESS of the Operand Descriptor. These modIfications
are similar to R-tvpe modifications fo~ Basic Instructions
and are summarized in Table 2-1 below. II legal mOdifiers
have the entry MIPR" and cause an Illegal Procedure Fault.
Table 2-1
R-type Modifiers for REG Fields
Meaning
Octal
~
B-:t~cc
00
01
02
N
Hf...REIi
~ y~
in
Indirect Operand
C:tS:U: eR1n!.tt
llc~cci
CeOperand
~CC'QlgCI~ZI~i
03 .
AU
QU
OU
N
AU
QU
IP.RCa)
04
05
06
07
IC
Al
QL
OL
IC(bt
A(c)
Q'c)
IPR
IC(b)
AL
QL
IPR
A(c)
Q(c)
IPR
10
11
12
13
XO
Xl
X2
X3
XO
Xl
X2
X3
XO
Xl
X2
X3
XO
Xl
X2
X3
14
X4
X5
X6
X7
X4
X5
X6
f.7
X4
X5
X6
X7
X4
X5
X&
X7
15
16
17
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
N
AU
QU
IPR
2-10
l
IPR
AU
QU
IPR
IPR
AL39
Ca)
The DU modifier is permitted only in the second Operand Descriptor of
the SCD. SCDR. SCH. and SCHR instructions to s3ecify that the test
character(s) reside(s) in bits 0-18 of the Operand Descriptor.
The IC modifier Is permitted only In the REG field of Indirect
Pointers and in HF3.REG for the SCD. SCDR. SCH. SCHR, HVT. TCT. and
TCTR instructions, that is. the instructions that store sum.ary
results of a scan operation. CeIC) Is always i~terpreted as a ~~
offset.
(c)
The limit of addressing extent of the processo~ ls 2--18 - 1 words;
that Is,. given any main store address, Y, a modife~ may be employed to
access a main store word anywhere in the range (Y - 2··18 + 1,
V + 2··18 - 1), provided other ·address range contraints are not
violated. Since it is desirable to address this same extent as words,
cha~acters,
and bits It is necessary to provide a registe~ with range
greater than the 12 bits of N or the 18 bits of no~mal R-type
modifiers.
This is done by extending the range of the A and Q
modifiers as fol lows •••
~
9-blt
6-blt
4-blt
bit
~
20
21
21
24
A.a
bits
1&,35
15.35
15,35
12,35
The unused high order bits are ignored.
EIS Operand Pessr1ptors and Indirest poInters
The words fol'owin~ an EIS Hulti-Word Instruction Word are
either
descriptions of tne operands or -lndirect-Polnters~ to the operand descriptions.
The interpretation of the words is performed acco~ding to the settings of the
control bits in the associated Hodification Field 'HF). Thehth Word following
the InstructIon Word is interpreted according to the contents of HF~. See EIS
Modifications FieldS eMF) above for meaning of the various control bits.
See Section III, Data RepresentatIon, and
Formation, for further details.
Section
VI,
Effective
Address
=
If HF6.ID
1, then the hth word following an EIS ~ulti-word Instruction
Word Is not an Operand Descriptor, but is an Indirect Pointer to an Operand
Descriptor and 15 interpreted as shdwn in Figure 2-5.
•
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-11
AL39
o
1 1
--L8
o
I
ADDRESS
10
J I
_I
18
ADDRESS
J
2
I
01
a o a a 0 o a a 0 OJAla
---1
Figure 2-5
2 2 J 3 J
1 3 D 1 ;)
11 1
i
2
REG
I
I
I
I
&
Operand Descriptor Indirect Pointer Forlllat
The given address of the Operand Descriptor.
may bel
An 18 bit maIn store address if A =
o"ly)
This address
(Absolute
0
An 18 bit offset relative to the ease Address
(BAR) if A = 0 (BAR Hode only)
"ode
Re~lster
An 18 bit offset retative to the base of the current
procedure segment if A = 0 (Appending Hode onlv)
A 3 bIt Pointer Register number Cn) and a 15 bit offset
relative to C(PRn.WORDNO) if A
1 (AI' modes)
=
Indirect via Pointer Register flag.
This flag controls
interpretation of the ADDRESS field of the Indirect
M
Pointer Just as the ··A flag controls interpretation of
the ADDRESS field of the BaSic a~d EIS Single-WOrd
Instruct ions.
A
Address modifier for ADDRESS.
All Register Hodflers
except DU and DL may be used. If IC is used. then AODRE$S
is an 18 bit offset to value of the Instruction Counter
LQL ~~ I~~~. C(REG) Is always interpreted as
a ~~ offset to ADDRESS.
-ALPHANUMERIC-OPERA~D-DESCRIPTOR-FORHATa
For any operand of an EIS Multi-word Instruction that requires Alphanumeric
Data. the Operand Descriptor is interpreted as shown 1n Figu·e 2-& below.
1 1
--LII
0
D
J
I
I
I
18
ADDRESS
3
a
I I
5
I
ITA lOa
1-1--_ _ _
J
J
3
N
Z 1
12
I•
Alphanumeric Operand Descriptor Forlllat
The given address of the operand.
(for the ~th operand):
An 18 Dit
Mode onlv)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
I
: eN
ADDRESS
Figure 2-&
2 2 2 2 2
II 1 Z
!t
maIn
2-12
This
store address 1f
address
HF~.AR=
may
be
0 (Absolute
AlJ9
An 18 bIt offset to the Base Address Register If
(BAR Hode onlya
=0
"F~.AR
An 18 bit offset relative to the base of the current
procedure segment if HF~.AR = 0 (Ap~ending Hode only)
A 3 bit Address Register num~er (D) and a 15 bit
offset to C(ARn.) if HFl1.AR = 1 (All modes)
U~
Character Number. This field gives the character position
within the word at ADDRESS of the first operand character.
Its interpretation depends on the Data Tvpe (see TA bel OM)
of the operand. Table 2-2 beloM shows the interpretation
of· the field.
A digit in the table indicates the
corresponding character position (See Section III. Data
Representat ion.
for data formats) and an ")t" indicates an
invalid code for the Data Type.
I~va'id
codes cause
Illegal Procedure Faults.
CN
Table 2-2
Alphanumeric Character Number (CN) Codes
.D.iltA lm.
kl.kW..
!t::Ju..1
ODD
0
1
2
3
001
010
011
100
101
110
l1i
fA
3._Rll
0
0
1
x
2
1
3
x
It
It
2
5
x
6
S
x
7
x
x
3
Type Alphanumeric. This is the Data Type code for the
operand.
The interpretation of the field is shown 1n
lable 2-3 below. The code shown as Invalid causes an
Illegal Procedure Fault.
Table 2-3
Alphanumeric Data Tvpe (TA) Codes
9-b1t
6-blt
4-bit
Inval1d
00
D1
10
11
N
6:Jtil
bperand lengt"'. If HFi1.RL = 0. this field contains the
string length of the operand. If HF~.RL
1. thiS field
contains the code for a register holding the operand
string length. See Table 2-1 and EIS Modification Fields
(HF) above fora discussion of register codes.
=
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
2-13
AL39
For any operand of an EIS Multi-word Instruction that requires Numeric
Data, the Operand Descriptor is interpreted as ShOMn in FIgure 2-7 bel OM.
o
2 2 222
a 1 Z J !t
1 1
---L8
Q
J I
I
I CN
ADDRESS
3 1
18
FIgure 2-7
I
I aJ S J
I I
---1.
2
3
a
5
I
a
SF
I
N
I
£»
6
I
I
I
Numeric Operand Descriptor Format
hu
The given address of the operand.
(for the ~th operand) I
ADDRESS
2 3
_ 9
An 18 bIt
Hode onl y)
main
This
store address if
address
HF~.AR=
may
be
0 (Absolute
An 18 bit· offset to the Base Address RegIster it
(BAR Hode only)
=0
"F~.AR
An 18 bit offset relatlve to the base of the current
procedure segment if HFls.AR = 0 (Appending Hode onl~)
A 3 bit Address Register number (~) and a 15 bit
offset to C(ARQ.) if "F~.AR = 1 (AI' modes)
a
~
CN
Character Number. This field gives the character position
within the word at ADDRESS of the first operand character.
Its interpretatIon depends on the Data Type (see TA beloM)
of the operand. Table 2-2 above ShOMS the interpretation
oft he fl e I d.
TN
Type NumerIc. This Is the Data type COd,:e for the operand.
The codes are •••
o
9-01t
It-bit
1
s
Sign and decimal type of data. The interpretation of
field is shown i~ Table 2-1t bel OM.
the
•
Tab.e 2-4
octal
OD
01
10
11
REVIEW DR~FT
SUBJECT TO CHANGE
Oct ober, 1915
~g~
Sign and Decimal Type (S) Codes
~n ~
Qec 1mat Ixaa
Floating point, leading Sign
Scaled fixed point, leading SIgn
Scaled fixed pOint, trailing Sign
Seated fixed point, unsig~ed
2-14
Al39
Scaling factor. This field contains t~e two·s complement
value of the base 10 ~cal Ing factor; that is, the value of
m for numbers represented a D x 10··m. The decimal ~oint
is assumed to the right of the least Significant digit of
O• . Negative
values move the decimal point to the .Ieft;
positive values, to the right.
The range of
is
SF
m
(-32,31).
Operand length. If HFts..RL= 0, this fietd contains the
operand length In digits. If HF~.RL = 1, it contains the
REG code for the register holding the operand length and
C(REG) is treated as a 0 modulo &4 num~er.
N
For any operand of an EIS Hulti-word Instruction that -eQuires BIt-string
Data, the Operand Descriptor Is interpreted as shown In FIgure 2-8 below.
o
1 1 1 2
--L8 3 g
o
a
I
I C J
ADDRESS
~
18
Figure 2-8
ADDRESS
2 2
3
3 !t
5
a
B
I
2
I
; I
4
I
N
I
I-
12
Bit String Operand Descrptor Format
The given address of the operand.
(for the ~th operand).
An 18 bit
Hode onl v)
main
This
address
may
be
store address if HFh.AR= 0 (Absolute
An 18 bIt offset to the Base Address Register if
= 0 (BAR Hode onlv)
HF~.AR
An 18 bit offset relative to the base of the current
procedure segment if HFh.AR = 0 (Ap~endln9 Hode only)
A 3 bit Address Register number (Q) and a 15 bit
offset to C(ARa.) If HFh.AR
1 (All modes)
=
~
c
The character number of the 9-bit character within ADDRESS
containing the first bit of the operan~.
B
The bit number within the 9-bit character, C, of the first
bit of the operand.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1915
2-15
ALJ9
fIXED POINT DATA HOVEHENT LOAO
EAA
Effective Address to A
FORHATa
8asic Instruction Format (See Figure 2-1).
SUMHARY'
Y -> .CrA)O,l7
635
r 0)
00 ••• 0 -> CCA)18.35
MODIFICATIONSI
All except OU. OL
INDICATORSI
(Indicato~s
If C(A)
Zero
Ne~at
•
ive
NOTESI
= O.
then ON; otherwise OFf
= 1.
If CIA) bit 0
then ON; otherwise JFF
The EAA instruction. and the instructions EAQ and EAXn,
facIlitate interregister data movements; the data source
is specified by the address
modification, and the data
destination by the operation code of tne instruction.
Attempted
Fault.
EAQ
not listed are not affected)
repetition with RPL causes an Illegal Procedure
Effective Address to Q
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHHARYI
Y ->
MODIFICATIONSI
All except DU. Ol
INDICATORSI
(Indicators not listed are not affectej)
CIQ)O.17
Zero
If C(Q) =
Negative
It C(Q)O
NOTES'
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
636 CO)
~,
= 1,
then ON; otherwise OFf
then ON; otherwise OFF
Attempted repetition with RPL causes a, II legal
Fault.
2-16
Procedure
AL39
FIKEO POINT DATA MOVEHENT LOAD
Effective Address to Xn
EAXn
&2n (0)
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHMARY'
For n
= 0,
Y ->
1, ••• , or 7 as determined
~,
C( Xn)
MODIFICATIONSI
AI. except OU, OL
INDICATORSI
(IncHcators not listed are not affected)
Zero
If C(Xn) = 0, then ON; otherlltise OFF
Negative
If C(Xn)O
NOTES'
operation code
= 1,
then ON; otherlltise OFF
Attempted repetition lItith RPL causes an II legal
Fault.
Procedure
Load Co_pi ellent A
LCA
335 (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
If C(Y)
~
0, then -C(Y) -> C(A)
otherwise, 00 ••• 0
->
C(A)
MODIFICATIONSI
All
INDICATORSI
(Indicators not listed are not affected)
= 0,
Zero
If CIA)
Negative
If CCA)O
Overf I o lit
If range of A is exceeded, then ON; otherwise OFF
NOTESI
= 1,
then ON; otherwise OFF
then ON; otherwise OFF
The LCA instruction changes the n~mber to its negative (If
_ 0) while moving It from Y to A. The operation is
executed by for.lng the 'wo·s coaplement of the string
3& bi ts.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-17
of
Al39
FIXED POINT DATA MOVEMENT LOAD
337 (0)
LCAQ
FORMAT'
Basic Instruction Format (See Figure 2-1).
SUH"ARYI
If CCY-pair)
~
O. then -CCY-pair) -> CCAQ)
otherwise, 00 ••• 0 -> C(AQ)
MODIFICATIONSI
All except DU, DL, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
= 0, then ON; otherwise OFF
CCAQ)a = 1, then ON; otherwise OFF
Zero
If CIAQ)
Negative
If
Overflow
If range of AQ is exceeded, then ON; other,dse OFF
NOTES.
The LCAQ "instruction changes the numbe- to its negative
(if ~ 0) while moving it from Y-pair t3 AQ. The operation
is executed by forming the two·s compleaent of the string
72 bits.
0'
Load Complement Q
LCQ
336 COJ
FOR"AT.
Basic Instruction Format (See Figure 2-1).
SU""ARYI
If CIY) _ D, then -elY).
->
ceQ)
otherwise, 00 ••• 0 -> CeQ)
"OOIFICATIONSI
All
INDICATORS'
CIndicators not listed are not affected)
= 0,
Zero
If CIQ)
Negative
If CCQ)O
Overflow
If range of Q Is exceeded, then
NOTES.
= 1,
then ON; otherwise OFF
then ON; otherwise OFF
O~;
otherwise OFF
The lCQ instruction changes the number to Its negative Clf
0) while moving it
from Y to Q.
The operation IS
executed by forming the tNO·S complement of the string of
36 bi ts.
~
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-18
AL39
FIXED POINT DATA "OVEMENT LOAO
32n (D)
Load Complement Xn
LCXn
FORHAT.
Basic Instruction Format (See Figure 2-1).
SUMMARY.
For n
= 0,
1 •••• , or 1 as determined
If C(YlO,11 _ 0, then -C(YIO.17
otherwise, 00 ••• 0
MODIFICATIONS'
I
~O.lCATORS2
Alt except CI,
se,
->
->
operation code
:IXn)
CCXn)
SCR
(Indicators not listed are not affected)
Zero
If eeXn)
Negative
If C(XnlO = 1, then ON; otherwise OfF
Overf I ow
If range
NOTES'
by
~
0, then ON; otherwise DFf
~f
Xn is exceeded, then ON; otherwise OfF
The LeXn instructlon changes the number to its negative
elf ~ 0) while moving It from YO,11 to Xn. The operation
is executed by forming the two·s compleMent of the string
of 18 bi ts.
Attempted repetition Mith RPL and with the same register
given as target and modifier causes an Illegal Pr.ocedure
fault.
235 CDI
Load A
LOA
FORHATI
Basic Instruc ti~ Format (See figure 2-1).
SUMMARY'
elY)
"ODIFICATIONS'
All
INDICATORSI
elndicators not listed are not
~~~dkH
-~
CIA)
Zero
If eeA)
Negative
If CIAIO
= 0,
= 1,
affecte~)
then ON; otherMlse OFF
then ON; otherwise OFF
REVH.W DRAFT
SUBJECT TO CHANGE
Oct 0 b er. 19 7 5
2-19
AL39
FIXED POINT DATA HOVEHENT LOAD
Load A and Clear
LDAC
031t (Ot
FORMAT.
Basic Instruction Format (See Figure 2-1t.
SUMMARYI
ctY) -> CIA)
00 ••• 0 ->C(Y)
MODIFICA TIONS'
All except DU, Dl, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
Zero
If CIA) = 0, then ON; otherwise OFF
Negative
If C(A)O = 1, then ON; otherwise OFF
NOTES'
LDAQ
The lOAC instruction causes a special .a1n store reference
that performs the load and clear in one cvcle. Thus, this
instruction can be used In locking data.
load AQ
-
237 (0)
FORHATa
Basic Instruction ForMat (See Figure 2-1).
SUMMARYI
C(Y-pair)
MODIFICATIONS'
All except DU, Dl, CI,
I NDICATORS I
(Indicators not Ii s ted are not
->
C(AQ)
se,
SCR
affecte~)
Zero
If C(AQ) = 0, then ON; other.is. OfF
Negative
If C(AQ)O -= 1, then ON; otherwise OFf
load Indicator Register
lDI
FORHAT'
BaSic .Instructjon Format (See Figure 2-1).
SUMMARY'
e(Y.18,31 -> C(IRa
MODIFICATIONS:
AI. except CI, SC, SCR
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-20
63 .. (0)
Al39
FIXED POtNT DATA MOVEMENT LOAO
INDICATORS'
(IndIcators not listed are not affected)
Parity
Hask
If C(Y)27 = 1, and the Process~r is in Absolute or
PrivIleged Hode, then ON; otherwise OF~.
This indicator
is not affected in the Normal or BAR .,des.
Not BAR
Hode
Carinot
b~
changed by the LOt instruction
Hultiword
If C(Y)30 = 1. and the Processor is In Absolute or
Instruction Privileged mode. then ON; otherwise OFF.
This lndicator
fault
is not affected in Normal or BAR modes.
Absolute
Hode.
Cannot be changed by the LDI instruct10n
Atl Other
If corresponding bit 1n C(Y) is 1. then ON; otherwise. OFF
Indicators
NOTES'
The relation between CCY)18,31 and the indicators is given
in Tab'e 2-5 below.
The Tally Runout indicator reflects :(Y)25 regardless of
what add~ess modification Is performed' on
the
LOI
instruction fo~ tally operations.
Attempted repetition with
Illegal Procedure Fault.
Table 2-5.
RPT.
RPO,
or
RPL causes an
Relation Between Data 81ts and Indicators
Indicator
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Zero
NegatIve
Carr V
Overt I ow
Exponent Overflo"
Exponent Undeflo"
Over f low Hask
Ta II If Runout
Par 1 ty Error
Parity "ask
Not BAR Hode
Truncation
H~ltiword Instruction Fault (MIF)
Absolute Hode
FIXED POINT DATA
LOAD
HOVE~ENT
Load Q
LDQ
236 IOJ
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARY'
CIY)
MODIFICATIONSI
All
INDICATORS.
(Indicators not listed are not affected'
->
= 0, then ON; othewise OFF
CeQJO = 1, then ON; otherwise OFf
Zero
If CeQ)
Negative
If
Load Q
lOQC
CIQ)
~nd
Clear
034 rOJ
FORHATa
Basic Instruction For.at (See Figure 2-1).
SUHHARya
cey)
-> CeQ)
00 ••• 0
->
cry)
HODIFICA TIONS'
AI. except DU.Ol. CIt Set SCR
INDICATORS.
(Indicators not listed are not affected)
Zero
If cry) : 0. then ON; otherwise OFF
Negative
If ceYJO
NOTES.
= 1,
then ON. otherwise OFF
The LOQC instruction causes ~ special main store reference
that performs the load and clear 1n one cycle. Thus, this
instruction can be used in locking data.
Load Index Register Xn
lOXn
32n rOJ
FORtUT'
Basic Instruction Format
SUHHARYI
For n = 0. i ••••• or 7 as determined DY operation code
C(Y)O,17
"OOIFICATIONS-
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
->
'~ee
FIgure 2-1J.
C(Xn)
All except CI, SC, SCR
2-22
AL3CJ
FIXED POINT DATA MOVEMENT LOAD
INDICATORSI
(Indicators not listed are not
Zero
If CIXn) = 0, then ON;
Negative
If C(Xn)O
NOTEsa
= 1,
then ON;
affecte~)
other~ise
other~ise
OFF
OFF
Attempted repetition ~ith RPL and Mith the saMe register
given as target and modifier causes an Illegal Procedure
Fault.
Load Registers
LREG
073 (OJ
FOR""TI
Basic Instruction Format ISee Figure 2-1).
SUMMARya
Cly)~,17
-> C(XO)
C(Y)18,35 -> C(X1)
C(Y+1)O,17 -> C(XZ)
CIY+Z)O,t7 ->
C(Y+1)18.35 -> C(X3)
C(X~)
C(Y+3)O,17 -> C(X6)
C(Y+3)18,35 -. C(X7)
C(Y+,.) -> CeA)
C(Y+5) ->
~h~re Y must be 0 modu10 8;
such address is used.
other~ise,
se,
MODIFICATIONS'
All except OU, DL, CI,
INDICATORSI
None af fected
NOTES'
Attempted repetition ~ith
I.legal Procedure Fault.
~(Q)
the
RPT.
RPD,
or
RPL
causes
an
72n (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
For n
= at
smaller
SCR
Load Xn from LOMer
LXLn
next
1, ••• , or 7 as determined
~y
operation code
C(Y)18,35 -> C(Xn)
MODIFICATIONS.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
AI. except CI,
se,
SCR
2-23
AL39
FIXED POINT DATA MOVEMENT LOAD
INllICATORSI
(Indicators not listed are not affected)
Zero
If C(Xn)
Negative
If C(Xn)O
NOTESI
= 0,
= 1,
~
then ON; otherwise OFF
then ON; otherwise OfF
Attempted repetition with RPl and with the 58me register
given a5 target and modifier causes an Illegal Procedure
fault.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
2-2"
AL39
FIXED POINT DATA MOVEMENT STORE
store Base Address Register
SOAR
350 (01
FORMAT.
Basic Instruction Format (See Figure 2-11.
SUMMARY.
C(BARJ
MODIFICATIONS'
All except DU. Dl. CI. SC. SCR
INDICATOR'S'
None affected
NOTES'
Attempted repetition .,lth
Illegal Procedure Fault.
->
eCYJO.l1
RPT.
RPD.
or
RPl
causes
Store Registers
SREG
FORMATa
.SU"HAR~I
an
753 (01
Basic Instruction format CSee figure 2-1).
CCXD)
->
CeVlD.17
CeXl)
->
CeY)18.3S
C(X21
->
CIY+l)O.17·
CeX3)
->
CeY+l)la.35
CIXIt)
-> C IY+2)
0.17
CeXS)
->
CeY+2)la.35
CIK6)
->
CeY+3)0,17
e1K7)
->
CeY+3)18.35
CIA)
->
CIY+It)
CeQ)
CIE)
->
C(Y+6)O.7
00 ••• 0
->
::(Y+6)8,35
00 ••• 0
->
::eY+7)27,32
CITR)
->
CIRAlR)
CIY+7)O.26
->
->
CIY+S)
CeY+7)33.35
.,here Y must be a 0 modulo 8 address; other.,lse the next
lower such address Is used.
"'ODIFICATIONS'
All eKeept OU. Ol. CI. SC. SCR
I NDICA TORS:
None affected
NOTES.
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-25
.RPT,
RPD.
or
RPL
causes
an
Al39
FIXED POINT DATA MOVEMENT STORE
Store A
STA
755 (OJ
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
C(A)
MODIFICATIONSI
AI. except DU, DL
INDICATORSa·
None af f ec ted
NOTEsa
Attempted repetition "ith RPL causes
Fault.
->
cry)
II legal
=0
Store A CondItional C(Y,)
STAC
an
354 (0)
FORMATa
Basic Instruction Format (See Figure 2-11.
SUMMARYI
If Cry)
HODIFICATIONS'
A.I except OU, Dl, CI,
INDICATORS:
(Indicators not lIsted are not affected)
Zero
NOTESI
= 0,
then CeA)
Cry)
->
se.
SCR
If inItial CIY) = 0, then ON; otherwise OFF
If the inItial C(Y) is nonzero, then Cry) Is
by
= CeQ)
654
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
If C(Y)
MODIFICATIONS:
All except DU, Dl, CI,
INDICATORS:
(Indicators not listed are not affected)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
changed
repetition "lth RPl causes an Illegal Procedure
Store A Conditional Cry)
Zero
not
the STAC instruction.
Attempted
Fault.
STACQ
Prodedure
= C(Q),
If initial C(Y)
then C(A)
= ClQ),
2-2&
se,
->
«0)
cey)
SCR
then ON;
other~ise
OFF
Al3CJ
FIXED POINT DATA HOVEHENT STORE
NOTEsa
If the in1tial C(Y) 1s
the STACQ instruction.
Attempted
Fault.
repetl~lon
~
C(Q), then C(Y) Is not changed bV
with RPL causes an II'egal
Store AQ
STAQ
757 (0)>
FORHAT.
Basic Instruction Format (See Figure 2-1).
SUHHARYI
CCAQ)
HOOIFICATIONS'
All except OU. OL. CIt SC, SCR
INDICATORS.
None af 'ected
NOTEsa
Attempted repetItion with RPL causes a'\ Illegal
Fault.
->
C(Y-pair)
Store Character of A (Nine Bit)
STBA
Procedure
Procedure
551 (0)
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUHHARY.
Characters of CIA) -> Corresponding Characters of CIVI,
the character pOSitions affected being specified in the
tag tield.
"ODIFICATIONS'
Mone
INDICATORS'
N.one at fected
NOTES'
Binary ones in the tag field of this instruction' specif,
the character posit ions of A and V that are affected~ The
control relations are shown in Table 2-6.
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPO.
or
RPL causes an
•
________ REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
2-27
AL39
FIXED POINT DATA HOVEHENT STORE
Table 2-6.
Control Relations for Store Character Instructions eNine 81t)
Bit POSitIon
liilhiD-I..ag Fie I d
Bit of
structure
Intlt:.udlJul
QLA-a~
0
30
Char
0
(bl ts 0-81
1
31
Char
(bi ts
1
~-17)
2
32
Char
2
lbits 18-26)
3
33
Char
3
(bi ts 27-35)
Store Character of Q (Nine BIt)
STBQ
552 COt
FORMATa
BaSic
SUMMARya
Characters of C(Q) -> Corresponding Cnaracters of e(y),
the character positions affected being specified In the
tag field.
MODIFICATIONS.
None
INDICATORSI
None affected
NOTES.
Binary ones in the tag field of this instruction sPecify
the character posItions of Q and Y that are affe~ted. The
control relations are shown In Table 2-'6 above.
In~tructlon
For_at eSee Figure 2-1).
Attempted repetition with
Illega' Procedure Fault.
RPT,
RPD,
or
Store Instruction Counter Plus 1
STC1
FORMATI
BasIc Instruction Format (See Figure 2-1).
SUMMARya
C(PPR.IC) + 1 -> C(Y)O,17
RPl causes an
55 ..
(at
CCIR) -> CIY)lB,31
00 ••• 0 -> C(Y)32,35
MODIFICATIONSI
All except OU, DL, CIt SC, SCR
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-28
Al39
FtXED POINT OATA MOVE"ENTSTORE
INDICATORS.
None af f ec ted
NOTES'
The contents of the Instruction Counte~ and the Indicator
Register after address preparation are stored 1ne(Y)O,17
and C(Y)18,31, respectivelv. C(Y)2S reflects the state of
the Tatlv Ronout indicator prior to lIodi ficat ion.; The
relationship betMeen the CCYJ18,31 and the indicators are
given in Table 2-5.
Attempted repetition Mlth
Illegal Procedure Fault.
RPT,
RPD,
or
RPl
causes
750 CD)
Store Instruction Counter Plus 2
STC2
fORHAT'
an
Basic Instruction Format (See Figure 2-1).
C(PPR.IC) + 2 -> CCYJO,17"
MODIFICATIONSI
All except OU, Dl, CI,
INDICATORSI
None af fected
•NOTES'
se,
Attempted repetition Klth
Illegal Procedure Fault.
SCR
RPT,
RPD.
or
RPL
causes
751 (OJ
Store Character of A (Six BIt)
STCA
aft
FOR"ATI
Basic Instruction Format (S•• Figure 2-1).
SU"HARVI
Characters of CeA) -> Corresponding Cnaracters of CIYI,
the character positions affected being specified in the
tag fie I d.
HOOIF~CATIONS.
'None
INDICATORS'
None af fected
NOTES'
Binary ones In the tag field of this
Instruction
spec I fy
character posi tions of A and y that are affected.
contrpl relations are shoMn in Table 2-7.
Attempted repetition Kith
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-29
RPT.
RPD.
or
RPL
causes
The
an
AL39
FIXED POINT DATA MOVEMENT STORE
Table 2-7.
Control Relations for Store Character Instructions (She Bit)
Bit Position
Klthin Tag fIeld
Bit of
los trye t ion
Structure
~LLaQLl
0
30
Char
0
(bl ts 0-5.
1
31
Char
1
lbi ts &-11)
2
32
Char. 2
(blts 12-17)
3
33
Char
3
(bits 18-23)
ft
31t
Char
It
(bi ts 21t-2 en
5
35
Char
5
(bi ts 30-35)
Store Character of Q (SlK Bit)
STCQ
~FORHATI
752 (DJ
Basic Instruction format ISee figure 2-1).
SUMHARY'
Characters of C(Q) -> Correspondlng Cnaracters of CrY),
the character positions affected being specified by the
tag f Ie I d.
MODIFICATIONS'
None
INDICATORSt
None affected
NOTESI
Binary ones in the tag field of this instruction specify
the character positions of Q and Y that are affected. The
control relations are sho"n in Ta)le 2-7 above.
Attempted repetition with
Illegal Procedure fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-30
RPT,
RPD.
or
RPL causes an
Al39
FIXED POINT DATA MOVEMENT STORE
Store Control Double
SlCD
357 (0)
FORHAl'
8asic Instruction Format (See Figure 2-1).
SUMMARY.
00 ••• 0 -. eCY-pair'O,Z
CCPPR.PSRl -. CCY-pair)3,1?
CCPPR.PRR)
00 ••• 0
~3
Coctal)
->
C(Y-pair)18,20
CCY-palr)21,Z9
->
00 ••• 0
->
->
CCY-palr30,35
C(y-pair)5~,71
MODIFICATIONS'
All except OU, Ot, CI, SC, SCR
INDICATORSI
None af fected
NOfESI
The" hardware assumes Y17 = 0; no check is made.
Attempted repetition with
Illegal Procedure Fault.
srI
RPT,
RPD,
or
RPL
causes
an
75~
CO)
Store Indicator Register
FORHAT.
Basic Instruction Format (See Figure 2-1).
SU""ARY.
C(IR)
->
do ••• o
->
C(Y'18,31
CCY)3Z,35
se,
MODIFICATIONS'
All except OU, Dl, CI,
SCR
INDICATORS'
None af fee ted
NOTES'
The contents of the Indicator Register after address
preparation are stored In CCY)18,31. C(Y)2S reflects the
•
state of the Tallv Runout indIcator prior to address
preparation.
The relation between eCY)18,31 and the
Indicators is given in Table Z-5.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
2-31
RPT,
RPD,
or
RPl
causes
an
FIXED POINT DATA MOVEMENT STORE
756 (OJ
Store Q
STQ
FORMATI
Basic
SUMHARYI
C(Q) -> C(Y)
MODIFICATIONS.
All except OU, Ol
INDICATORsa
None af fected
NOTESI
Attempted repetItion with RPl causes a, II legal
Fau It.
Store
STT
Inst~uctlon
Time~
Format (See Figure 2-1).
Register
Procedure
454 (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
CITR) -> C(Y)O,26
00 ••• 0 -> C(Y)27,35
MODIFICATIONSI
All except OU, Ol, CI, SC y SCR
INDICATORSI
None affected
NOTES'
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
RPl
Store Xn in Upper
STXn
FORHATI
BaSic
Inst~uctlon
SUMMARY'
For n
= 0,
CeXn)
->
74n (0)
Format (See Figure 2-1).
1 •••• , or 7 as determined
~v
operation code
C(Y)0,17
HOOIFICATIONSJ
All except OU, Ol, CI, SC, SCR
INDICATORS I
None af fected
NOTES;
Attempted repetItion with RPl causes
Fau It.
REVIEW DRAFT
SUBJECT TO CHANGE
Octobery 1975
an
causes
2-32
a,
II legal
Procedure
AL39
FIXED POINT DATA MOVEHENT STORE
Store Zero
STZ
450 (0)
FORMAT'
Basic Instruction Format (See Figure 2-1).
SUMMARY.
00 ••• 0 -> ceY)
HOOIFICATtONSI
AI) except OU, OL
INDICATORSI
None affected
NOTESI
Attempted repetition with RPL causes
Fault.
a~
IIIe9al
Store Xn in Lower
SXLn
44n CO)
FORHAT'
BasIc Instruction Format (See Figure 2-1).
SUMMARYI
For n
= 0,
Procedure
1, ••• , or 7 as determined DV operation code
e(Xn) -> C(Y)18,35
se,
MODIFICATIONSI
All except DU, DL, CI,
INDICATORS'
None affected
NOTES.
Attempted repetition with RPL causes
Fault.
REV lEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-33
SCR
a~
Illegal
Procedure
Al39
FIXED POINT DATA MOVEMENT SHIFT
A left Rotate
AlR
175 (0'
FORMATa
Basic Instruction Format (See Figure 2-1'.
SUMHARY.
Shift CU) Jeft the number of positions specified
enter each bit leaving AO into A35.
HODIFICATIONSz
All except DU, Ol, CIt SC, SCR
INDICATORSI
(Indicators not listed are not affected)
= Ot
Zero
If C(A)
Negative
If C(A)O : 1, then ON; otherwise OFF
NOTES.
then ON; otherwise OFF
Attempted repetition with RPL causes an Illegal
Fault.
FORHATa
Basic Instruction Format (See Figure 2-1).'
SUMMARY'
Shift C(A) left tne number of pOSitions
Y11,17; fil I vacated pOSitions with zeros.
HODIFICATIONS'
All eKcept OU, Ol, CI, SC, SCR
INDICA TORS:
(Indicators not listed are not
= 0,
If CIA)
Negative
If C(A)O
Carry
If C(A)O changes during the shIft,
NOTESI
specified
by
affecte~1
Zero
= 1,
Procedure
735 CO)
A Lelt ShIft
AlS
Yi1,17;
then ON; otherwise OFF
then ON; otherwise OrF
the~
ON; otherwise OFF
Attempted repetltion wIth RPL causes an Illegal
Proc~dure
Fault.
REVIEW DR'FT
SUBJECT TO CHANGE
October, 1975
Al39
FIXED POINT DATA MOVEMENT SHIFT
A Right Logic
ARL
771 (OJ
Instruction Format (See Figure 2-1).
FORHATa
Bas~c
SUMHARya
Shift CeA) right the number of positions specified
11,17; fill vacated pos1tions with zeros.
MODIFICATIONSI
All except DU, OL, CI, SC, SCR
INDICATORSI
(Indicators not listed are not
Zero
If CIA)
Negative
If CeA)O
NOTESa
= 0,
= 1,
then ON; otherwise OFf
then ON; otherwise Off
Attempted repetition with RPL causes an Illegal
Fault.
Basic
SUHMARY.
Shift CIA) right the number of positions
Y11,17; f111 vacated positions with CeA)O.
MODIFICATIONSa
All except DU, OL, CI. SC, SCR
INDICATORSI
(Indicators not listed are not affected)
Instruct~on
= 0,
If CeA)
Negative
If C(A)O
NOTESI
= 1,
format (See Figure 2-1).
specified
then ON; otherwise OFF
Attempted repetition with RPL causes an Illega'
Fault.
Procedure
777 (0)
FORHATa
Basic Instruction Format (See Figure 2-U.
SU"MARya
Shift CIAQ) left by the number of pOSitions specifIed
Y1t,17; enter each bit leaving AQO Into AQ71.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
bV
then ON; otherwise OFF
Long Left Rotate
LLR
Procedure
731 rO)
FORHATa
Zero
Y
affecte~)
A RIght Shift
ARS
by
2-35
bV
Al39
FIXED POINT DATA MOVEMENT SHIFT
MODIFICATIONSI
All except OU, Dl, CI, SC, SCR
INDICA TORSI
(Indicators not listed are not
= 0.
affecte~)
Zero
If C(AQ)
Negative
If C(AQJO = 1, then ON; otherwise OFF
NOTES.
then ON; otherwise OFF
Attempted repetition with RPl causes
Fault.
a~
II
legal
long Left Shift
LlS
737 (0)
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMHARYI
Shift C(AQ) 'eft the number
positions
Yll,17; fil' vacated positions with zeros.
MODIFICATIONS:
All except OUt Ol, CIt SC, SCR
INDICA TORSI
(Indicators not listed are not
0'
If C(AQ).
Negative
If
Carry
If C(AQ)O changes during the
s~ift,
Attempted repetition with RPL causes
Fault.
then ON; otherwise OFF
a~
II legal
Procedure
773 (0)
FORHATa
Basic InstructIon Format (See FIgure 2-1).
SUMHARY:
Shift CCAQ) right the number of positions
Yll,17; fitl vacated positions with zeros.
MODIFICATIONS I
All except DU, Dl, CI, SC, SCR
REV lEW DRAFT
SUBJECT TO CHANGE
October. 1975
by
affecte~)
Long Right Loglc
LRl
specifIed
= 0. then ON; otherwise OFF
C(AQ)O = 1, then ON; otherwise OFF
Zero
NOTESI
Procedure
2-36
specified
by
Al39
FIX[D POINT DATA MOVEMENT SHIFT
INDICA TORSI
(Indicators not listed are not
Zero
If .CCAQ) = 0, then ON;
Negative
If C(AQ)O
= 1,
aff.cte~)
other~dse
OFF
then ON; otherwise OFF
Attempted repetition wIth RPL causes
Fault.
NOTESI
a~
II legal
Procedure
Long RIght Shift
lRS
733 (D)
FORHATa
Basic InstructIon Format (See Figure 2-1).
SUMMARY.
Shift 'CCAQ) right the number of positions
Yl1,17; fIll vacated positions wIth C(AIO.
"OOIFICATIONSI
All except DU, OL, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
If C(AQ)
Negative
If
Attempted repetItIon with RPL causes
Fault.
a~
Illegal
Procedure
Q Left Rotate
QLR
776 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUM"ARYI
Shift C(Q) the number of positions specified
enter each bit leaving QO Into Q35.
MODIFICATIONSI
All except DU, OL, CI, SC, SCR
INDICATORS'
(Indicators not listed are
by'
Yll,17;
~ot affecte~)
= D, then ON; otherwise OFF
C(Q)O = 1, then ON; otherwise OFF
Zero
If C(Q)
Negative
If
NOTESI
by
= 0, then ON; otherwise OFF
CCAQ)O = 1, then ON; otherwise OFF
Zero
NOTES.
specified
Attempted repetition with RPL causes
a~
II legal
Procedure
Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-37
AL39
FIXED POINT DATA MOVEMENT SHIFT
736
«oa
specified
by
Q Left Shift
QlS
FORMATI
Basic Instruction Format (See Figure 2-1).
SUHHARYI
Shift CeQ) left. the number of positions
Vll,17; fl' I vacated positions with ze~os.
HOOIFICATIONSI
All except DU, Dl. CI, SC, SCR
INDICA TORS'
(Indicators not listed are not affected)
= D,
Zer"O
If CeQ)
Negative
If CCQ)D
Carry
If CCQ)O changes during the shift,
NOTESI
= 1,
then ON; otherwise OFF
then ON; otherwise OFF
the~
ON; otherwise OFF
Attempted repetitIon with RPl causes an Illegal
Fault.
Q Right Logie
QRL
4t
772 CO)
FORHATa
Basic Instruction Format ISee Figure 2-1).
SUHMARVI
Shift CeQ) right the nUMber of positions
Yll,17; fIll vacated positions with ze-os.
HODIfICATIONS.
All except OU, Dl, CI, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
= 0,
If CeQ)
Negative
If C(Q)O = 1, then ON; otherwise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
specified
by
then ON; otherwise OFf
Zero
NOTES'
Prodecure
Attempted repetition with RPL causes an Illegal
Fault.
2-38
Procedure
AL39
FIXED POINT DATA MOVEMENT SHIFT
QRS
Q
Right Shi It
732 eO)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMHARya
Shift CeQ) right the number of positions
Yi1,17; fIll vacated positions with celIO.
MODIFICATIONSI
All except OU, Ol, CI, SC, SCR
INDICATORS'
(Indicators not listed are not
specified
by
affecte~)
= 0, then ON; otherwise OFF
CCQ)O = 1, then ON; otherwise OFF
If C(Q)
Negative
NOTESI
If
Attempted repetition with RPl causes an Illegal
Fault.
Procedure
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-3<)
AL39
FIXED POINT ADDITION
AOO to A
ADA
075 (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHHARYa
C(A) + C(Y) -> CeA)
HOOIfICATIONSI
AI J
INDICATORSa
(Indicators not listed are not
= 0.,
affecte~)
Zero
If CIA)
then ON; othe ... wise OFF
Negatlve
If C(A)O
Ove ... f I ow
If range of A is exceeded., then ON; otherwise OFF
Carry
If a carry out of AO 1s generated., then ON; otherMise OFF
= 1 ..
then ON; otherwise OfF
Add to AQ
ADAQ
• FORHATa
077 (0)
Basic Instruction Format (See Figure 2-1).
SUHMARYa
CIAQ) + elY-pair) -> C(AQ)
HODIFICATIONSI
All except OU, OL, CI, SC, SCR
INDICATORSI
(IndIcators not listed are not affected)
Zero
If CeAQ) = 0, then ON; otherwise OFF
Negative
If C(AQ)O
Overflow
If range of AQ is exceeded., then ON; otherMise OFF
Car ... y
If a carry out of AQO is generated .. than ON; otherwIse OFf
= 1,
then ON; otherwise OFF
Add LOM to AQ
AOL
033 (0)
FORHATa
Basic Instruction Format (See Figu ... e 2-1).
SUMHARYI
C(AQ) + elY) sign extended
REV lEW OR lifT
SUBJECT TO CHANGE
Octobe ..... 1975
2-40
-~
C(AQ)
AL39
FIXED POINT ADDITION
MODIFICATIONS'
All except CI, SC, SCR
INDICATORS.
(Indicators not listed are not affected)
= 0, then ON; other"ise
C(AQ)O = 1, then ON; other .. ise
Zero
If C(AQ)
. . . egative
If
Overflo ..
If range of AQ is exceeded, then ON; otherMise OFF
Carry
If a carry out of AQO Is generated, then ON; other .. ise OFF
NOTES.
A 72-bl t number is
mannerl
formed
O~F
from
OFF
C(Y)
In
FORMAT'
follo .. ing
The 10Mer 36 bits (36,71) is identic~1 to CIYl.
the upper 36 bits (0,35) is identical to C(Y)D.
Each of
This 72-~lt number Is
combined AQ-register.
of
added
to
the
contents
Add logIcal to A
ADlA
the
the
035 (Q)
Basic InstructIon For.at (See Figure 2-1).
CIA) +C(Yl -> CIA)
MODIFICATIONS.
All
INDICA TORSI
(Indicators not Ilsted are not
= 0,
affecte~)
Zero
If C(A)
Negative
If CIA)O
Carry
If a carry out of AD 1s generated.
NOTESI
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
~
then ON; otherMise OFF
1, then ON; otherMise DFF
the~
ON; other .. ise OFF
The ADlA instruction is identical to the ADA instruction
.. lth the exception that the Overflow indicator is not
affected by the AOlA instruction, nor does an Overflo ..
Fault
occur.
Operands and results are treated as
unsigned, positive binary integers.
2-"1
Al39
FIXED POINT ADDITION
Add logical to AQ
AOlAQ
037 CO)
FORMAT I
Basic Instruction Format (See Figure Z-l).
SUMMARYI
C(AQ) + C(Y-pair)
MOOIFICATIONSS
All except OU, OL.
INOICATO~SI
(Indicators not listed are not affected)
= 0,
Zer.o
If CCAQ)
Negative
If C(AQ)O
Carry
If a carry out
NOTES'
->
C(AQ)
ct,
SC, SCR
then ON; otherwise OFF
= 1,
then ON; otherwise OFF
0'
AQO Is genera"ted, then ON; otherwise OFF
The AOLAQ instruction is identical to the ADAQ instruction
with the exception that the Overflow indicator. is not
affected by the AOlAQ instruction. nor does an OverfloM
Fault occur.
Operands and results are
treated
as
unsigned, positive binary integers.
Add Logica. to Q
ADlS
036 (0)
FORHAT.
Basic Instruction Format (See Figure Z-l).
SUHHARYS
C(Q) + C(Y) -> CeQ)
MODIfICATIONSI
A II
INDICA TORSI
(Indicators not listed are not affected)
Zero
If C(Q)
= 0,
= 1,
then ON; otherwise OFF
·Negative
If C(Q)O
Carry
If a carry out of QO is generated,
NOTESI
then ON; otherwise OFf
the~
The AOLQ instruction 1s identical to tne
ON; otherwise OfF
ADQ
instruction
with the exceptIon that the Overflow indicator is not
affected oy the AOLQ instruction, nor does an Overflo.
Fault
occur.
Operands and results are treated as
unsigned, positive binary integers.
REV lEW OR 'FT
SUBJECT TO CHANGE
October, 1975
AL39
. FIXED POINT ADDITION
Add logical to Xn
ADLXn
02n (0)
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUMHARya
For n
= 0,
1 •••• , or 7 as determined !)v operation code
C(Xn) + C(Y)O,17
->
C(Xn)
MODIFlCATIONsa
All except CI, SC, SCR
INDICATORSa
(Indicators not listed are not
affecte~)
= 0, then ON;.otherlillse OFF
CeXn)O = 1, then ON; otherlilise OFF
Zero
If CeXn)
NegatIve
If
Carrv
If a carrv out of XnO Is generated, then ON; otherwise OFF
NOTES'
ADQ
The ADlXn instruction 1s identical to the ADXn instruction
with the exception that the Overflow lndicator Is not
affected by the AOlXn instruction. nor does an OverfloM
Fault occur.
Operands and results are
treated
as
unsigned. positive binarv integers.
Add to Q
01& CO)
FORMATa
Basic Instruction ForMat (See Figure 2-1).
SUMMARY a
ceQ) + CCY)
MODlFICATIONSI
AI.
INDICATORS:
eIndicators not listed are not affected)
->
ceQ)
= 0. then ON; otherwise OFF
C(Q)O = 1, then ON; otherwise OFF
Zero
If C(Q)
Negative
If
Overflolll
If range of Q is exceeded. then ON;
Carry
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
~therMise
OFF
If a carry out of QO Is generated. then ON; otherlilise OFF
Z-ltJ
Al39
fIXED POINT ADDITION
O&n (0)
Add to Xn
AOXn
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
For n
= 0,
1, ••• , or 7 as determined bV operation code
C(Xn) + C(Y)0,17
->
C(Xn)
MODIFICATIONSI
AI' except CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
= 0,
Zero
If CeXn)
then ON; other",lse OFF
Negative
If C(Xn)O = 1, then ON; otherwise Off
OVerflo",
If range of Xn Is exceeded, then ON; otherwise OFf
Carrv
If a carry out of XnO Is generated, then ON; otherwise OFF
Add One to Storage
AOS
..FORHATI
Basic Instruction
05,. CO)
for~at
(See Figure 2-1' •
SUMMARY I
cry) + 1 -> elY)
MODIFICATIONS'
All except OU, Dl, CI, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
= 0,
Zero
If C(Y)
Negative
If C(Y)O
Overflow
If range of Y is exceeded, then ON; otherwise OFf
Carry
If a carrv out of YO is generated, then ON; otherwise
NOTES.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
= 1,
then ON; otherwise OFF
then ON; otherwise OfF
Attempted repetition with RPl causes
Fau It.
a~
II legal
OfF
Procedure
FIXED POINT ADDITION
Add Stored to A
ASA
055 CO)
For~at
FORHAT.
Basfc Instruction
SUMMARYI
CeA) + CIY) -:. ceY)
MODIFICATIONS.
All except OU, OL, CI, SC, SCR
INDICATORS.
(IndIcators not listed are not
= 0,
(See Figure 2-1).
affecte~)
Zero
If elY)
Negative
If C(Y)O
Overt low
If range of Y Is exceeded, then ON; otherwise OFF
Carry
If a carry out of YO is generated, then ON; otherwise OFF
NOTES.
= 1,
then ON; otherwIse OFF
Attempted repetition with RPL causes an Illegal
fault.
Add Stored to
ASQ
then ON; otherwise OFF
Procedure
056 (0)
Q
FORHATa
BaSic InstructIon Format (See Figure 2-1).
SUMHARY'
CIQ) + CU) -> CU)
MODIFICATIONS.
All except OU, Ol, CI, SC, SCR
IHDICATORSI
(Indicators not listed are not affected)
= 0, then ON; otherwIse OFf
CIY)O = 1, then ON; otherwIse OFF
Zero
If CIY)
NegatIve
IF
Overflow
If range of Y Is exceeded, then ON; otnerwise OFF
Carr~
If a carry out of YO is generated, then ON; otherwise OFF
NOTEsa
REVIEW DR.FT
SUBJECT TO CHANGE
October, 1975
Attempted repetition with RPl causes
Fault.
2-'+5
a~
II legal
Procedure
Al39
FIXED POINT ADDITION
Ottn (D)
Add Stored to Xn
ASXn
FORHATa
Basic Instruction Format eSee Figure 2-1).
SUHMARV'
For n
= 0,
1 ••••• or 7 as determined DY operation code
C(Xn) + CIV)0.17
->
C(Y)0,17
MODIFICATIONS:
AI. except OUt Dl. CIt SC, SCR
INDICATORS:
(Indicators not 'isted are not
= 0,
affecte~)
Zero
If C(Y)0,17
Negative
If CeYIO = 1. then ON; otherwise OFF
Overflow
If range of YO.17 is exceeded, then ON; otherwise OFF
Carry
If a carry out of YO is generated, then ON; otherwise OFF
NOTES'
then ON; otherwIse OFF
Attempted repetition with RPl causes
Fault.
a~
II legal
Procedure
Add with Carry to A
AWCA
071 (0)
FORHATI
BaSic Instruction Format (See Figure 2-1).
SUHHARY'
If Carry indicator OFF, then CIA) + C(Y) -> CIA)
If Carry indicator ON, then
CeA) + cey) + 1
HODIFICATIONS'
All
I NDICA TORS:
(Indicators not listed are not
= 0,
->
CeA)
affecte~)
Zero
If CeA)
Negative
If CeA)O = 1. then ON; otherwise OFF
Overf low
If range of A Is exceeded, then ON;
Carry
If a carry out of AD is generated, then ON; otherwise OFF
NOTESI
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
then ON; otherwise OFF
ot~erwlse
OFF
The AWCA instruction is identical to the ADA instruction
with the exception that when the Carrv indicator is ON at
the beginning of the instruction, 1 is added to the sum of
C(A) and C(Y).
2-4&
Al39
FIXED POINT ADDITION
AWCQ
Add wlth Carry to Q
072 CO)
FORHATa
Basic Instruction Format (See
SUMMARY.
If Carry indicator OFF. then CeQ)
If Carry indicator ON, then
Fig~re
+
2-1).
cet) -> ceQ)
CeQ) + cty) + 1
HOOIFICATIONS'
All
INOICATORSZ
(Indicators not lIsted are not
->
ceQ)
affecte~)
= D. then ON; otherwise OFF
CeQ)O = 1. then ON; otherwise OFF
Zero
If C(Q)
Negative
If
Overflo.
If range of Q is exceeded, then ON; otAerwise OFF
Carry
I f a carry' out of QO Is generated, then ON; other"wise OFF
NOTES.
The AWCQ instruction is identical to t~e AOQ instruction
.ith the exception that when the Carr, indicator is ON at
the beginning of the instruct lon, 1 is added to the s_ of
C(Q) and CCY).
.
•
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-47
Al39
FIXED POINT SUBTRACTION
Subtract from A
SBA
175 (0)
FORHAT.
Basic Instruction Format (See Figure 2-1a.
SUMMARY'
C(A) - elY) -> C(A)
MODIFICATIONS'
All
INDICATORS:
(Indicators not listed are not affected)
Zero
If CIA) = 0, then ON; otherwise OFF
Negat 1 ve
If CCA)O
Overflo ..
If range of A is exceeded, then ON; otherwise OFF
Carry
If a carry out of AD is generated, then ON; otherwise OFF
= 1,
then ON; otherwise OFF
Subtract froll AQ
SBAQ
177 I D)
FORHATI
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
c(AQ) - e(Y-palr) -> CCAQ)
MODIFICATIONSI
All except DU, DL, CI, SC, SCR
INDICATORS:
(Indicators not listed are not
affecte~)
= 0, then ON; otherwise OFF
CIAQ)O = 1, then ON; otherwise OFF
Zero
If C(AQ)
NegatIve
If
Overflow
If range of AQ is exceeded, then ON; otherwise OFF
Carry
If a carry out of AQO is generated, then ON; otherwise OfF
Subtract logical from A
SBlA
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHHARya
CeA) - CIY)
->
135 (0)
CIA)
R[VIEW DRAFT
SU8JECT TO CHANGE
October, 1975
2-48
Al39
FIXED POINT SUBTRACTION
MODIFICATIONS:
All
INDICA TORSI
(Indicators not listed are not affected)
= 0,
zero
If C(A)
Negative
If C(A)O = 1, then ON; otherwise OFF
Carry
If a carry out of AO is generated,
NOTES.
then ON; otherwise OFF
the~
ON; otherwise OFF
The SBlA instruction is identical to the SBA instructlon
~ith
the exception that the Overflow indicator is not
affected by the SBLA instruction, nor does an Overflow
Fault
occur.
OperandS and results are treated as
unsigned. positive binary integers.
Subtract Logical from AQ
SBLAQ
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY a
C(AQ) - C(Y-pair)
.. MODIFICATIONS:
I NDICATORSI
->
137 (0)
C(AQ)
All except DU, OL, CIt SC, SCR
(Indicators not listed are not affected)
= O.
Zero
If C(AQ)
Negative
If CIAQ}O
Carry
If a carry out of AQO is generated. then ON; otherwise OFF
NOTESI
= i.
then ON; otherwise OFF
then ON; other.lse OFF
The SBLAQ instruction is identical to the SBAQ instruction
with the exception that the Overflow indicator is not
affected by the SB~AQ instruction. ~or does an Overflow
Fault occur.
Operands and results are
treated
as
unsigned. positive binary integers.
Subtract Logical from Q
SBLa
FORHATa
Basic Instruction Format (See Figure 2-1).
SUH"ARYI
e(Q) - elY)
MODIFICATIONSI
AII
R£VIEW DRAFT
SUBJECT TO CHANGE
October. 1975
->
136 (0)
c(a)
AL39
fIXED POINT SUBTRACTION
I NDICA TORS I
(Indicators not lIsted are not affected)
= D, then ON; otherwise OFf
C(Q)O = 1, then ON; otherwise Off
Zero
If C(Q)
Negative
If
Carry
If a carry out of QD Is generated,
NOTESI
the~
ON; otherwise Off
The SBLQ instruction is identical to tne SaQ instruction
with the exception that the Overflow indicator is not
affected by the SBLQ instruction. nor does an Overflow
fault
occur.
Oper~nds
and results are treated as
unsigned, pOSitive binary integers.
Subtract Logical froll Xn
SSLXn
FORHATa
Basic Instruction Format (See figure 2-1).
SUMMARY I
for n
= O.
12n CO)
1, •••• or 7 as determined bY operation code
CeXn) - C(Y)O,17
->
CeXn)
MODIFICATIONSI
All except CI, SC, SCR
IHDICATORS.
(Indicators nof listed are not affected)
Zero
If C(Xn) = 0, then ON; otherwise OFF
Negative
If CeXn)O
Carry
If a carry out of XnO Is generated, then ON; otherwise OFf
NOTES
= 1,
The SBLXn instruction is identical to the SeXn instruction
witn the exception that the Overflow indicator Is not
affected by the SBLXn instruction, nor does an Overflow
Fault occur.
Operands and results are
treated
as
unSigned, positive binary integers.
Subtract from
SSQ
then ON; otherwise OFf
176 CO)
Q
•
FORMATa
Basic Instruction format (See Figure 2-1).
SUMMARYI
C(Q) -
MODIfICATIONS'
Ait
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
en)
-> ceQ)
2-50
AL39
FIX~D
INDICATORS'
(Indicators not listed are not
POINT SUBTRACTION
affecte~)
Zero
If C(Q) = 0, then ON; otherwise OFf
Negative
If C(Q)O
Overflow
If range of Q is exceeded, then ON; otherwise OFF
Carry
If a carry out of QO is generated,
= 1,
Sub trac t f r
S8Xn
011
then ON; otherwise OFF
the~
O~;
10n (0)
ltn
fORHAT:
Basic Instruction Format (See Figure 2-1).
SUMMARY'
For n
= 0,
otherwise OFF
1, ••• , or 7 as determined Oy operation code
C(Xn) - C(Y)O,17 -> C(Xn)
MODIFICATIONS'
All except CI, SC, SCR
INDICATORSI
(Indicators not listed are not
affecte~)
Zero
If C(Xn) = 0, then ON; otherwise OFF
Negative
If C(Xn)O
Overflow
If range of Xn is exceeded, then ON; otherwIse OFf
Carry
If a carry out of XnO is generated, then ON; .otherwlse Off
= 1,
then ON; otherwise OfF
155 (0)
Subtract Stored fro. A
SSA
fORMATI
Basic Instruction Format tSee Figure 2-1).
SUHMARYI
C(A) - C(Y)
HODIFICATIONSI
All except DU, Ol, CI, SC, SCR
INDICATORSI
(Indicators not listed are not
->
elY)
affecte~)
Zero
If C(Y) = 0, then ON; otherwise OFF
Negative
If C(Y)O
Overflow
If range of Y is exceeded, then ON;
Carry
If a carry out of YO Is g.nerated,
= 1,
then ON; otherwise Off
ot~erwise
the~
OFF
ON; otherwise OFF
REVIEW OR'fT
SUBJECT TO CHANGE
October, 1975
2-51
AL39
FIXED POINT SUBTRACTION
NOTES'
Subtract Stored froll
SSQ
a~
Attempted repetition with RPL causes
Fault.
Illegal
156 (0)
Q
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUMMARya
C(Q) - cry)
MODIFICATIONSI
All except DU, Dl, CI, SC, SCR
INDICATORSI
(Indicators not listed are not
->
= 0,
Procedure
C(Y)
affecte~)
Zero
If cty)
Negative
If C(Y)O
Overfl ow
If range of Y is exceeded, then ON;
Carry
If a carry out of YO is generated, then ON; otherwise OFF
NOTESI
then ON; otherwise OFF
= 1.
then ON; otherwise OFF
ot~erwise
OFF
Altempted repetition with RPl causes an Illegal
Fault.
Procedure
Subtract Stored from Xn
SSXn
FORHAT.
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
For n
= 0.
1, •••• or 7 as deterMined by operation code
C(Xn) - C(Y)0.17
->
C(Y)O,11
MODIFICATIONSI
All except OUt Dl, CI, SC, SCR
INDICATORS:
(Indicators not listed are not
= 0,
affecte~)
Zero
If C(Y)O,17
Negative
If C(Y)O
Overflow
If range of YO,1T exceeded, then ON; otherwise OFF
Carry
If a carry out of YO is generated,
NOTESI
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
(0)
1~n
= 1,
then ON; other.lse OFF
then ON; otherwise OFF
the~
ON; otherwise OFF
Attempted repetition with RPl causes an Illegal
Fault.
2-52
Procedure
Al39
FIX~O
POINT SUBTRACTION
Subtract with Carry from A
SWCA
171 (0)
FORMAT!
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
If Carry indicator ON, then
cry)
CIA) -
->
CIA)
If Carry indicator OFF, then C(A) - Cry) - 1 -> CIA)
HODIFICATIONSI
AU
INDICATORSI
(Indicators not listed are not affected)
Zero
If CeA) = 0, then ON; otherwise OFF
NegatIve
If C(A)O
Overflow
If range of A Is exceeded, then ON; otherwIse OFF
Carry
If a carry out of AD Is generated, then ON; otherwise OFF
NOTES!
= 1,
then ON; otherwise Off
The SHCA instruction is identical to tne SBA instruction
with the exception that when the Carry indicator is OFF at
the beginning of the instruction. +1 is subtracted from
the difference of CIA) minus C(Y). The SWCA instruction
treats the Carry indicator as the complement of a borrow
indicator; due to the implementation of
negative
numbers
in two·s complement torm.
172
Subtract with Carry from Q
SWCQ
FORHAT!
BaSic Instruct ion Format (See Figure 2-1).
SUMMARYI
If Carry indicator ON, then
(b)
C(Q) - ClY) -> CeQ,
If Carry indicator OFF. then C(Q) - CIY) - 1 -> CIQ)
MODIFICATIONS.
All
INDICATORSI
(Indicators not listed are not affected)
•
= D.
Zero
If CIQ)
Negative
If CIQ)O = 1, then ON; otherwise OFF
Overf low
If range of Q is exceeded. then ON; otherwise OfF
Carry
If a carry out of QO is generated.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
then ON; otherwIse OFF
2-53
then ON; otherwise OFf
AL3()
FIXED POINT SUBTRACTION
NOTES.
REVIEW OR_FT
SUBJECT TO CHANGE
October. lq75
The SWCQ instruction is identical to the SBQ instruction
with the exception that when the Carrv indicator is OFF at
the beginning of the instruction, +1 is subtracted from
the'difference of CCQ) minus Cry). The SWCQ instruction
tredts the Carrv indicator as the cO~plement of a borrow
indicator; due to the implementation of negative numbers
in two·s complement form.
2-54
AL39
FIXED POINT HULTIPLICATION
Hultiplv Fraction
HPF
FORMATa
Basic Instruction Format (See Figure 2-1 ••
SUMMARY'
CIA) x C(Y) -> CCAQ), left adJusted
MODIFICATIONS'
All except CI,
INDICATORS:
lIn~icators
se,
SCR
not listed are not affectej)
= 0,
Zero
If C(AQ)
Negative
If CCAQ)D
Overflow
If range of AQ is exceeded, then
NOTESI
~
to»
ltOl
then ON; otherwise OFF
1, then ON; otherwise OFF
~N;
otherwise OFF
Two 3&-bit f,.actional
factors
(including
sign)
are
multiplied to form a 71-bit fractional product (including
sign), which is stored left-adjusted in the AQ-register.
AQ71 contains a zero. Overflow can oc:ur only in the case
of A and Y containing all ones and the result exceeding
the combined AQ-register.
n
0
I
o 0
3
-1-1---________________
5 __
3
_0 1
5
I.
J
L I
I
IsJ<-----factor--------->1
J
I
A Register
x
I
Isl<-~---factor--------->l
I
1
I
Hain Store location Y
vielding
o
0 ______________
~_1
I
~
____________________________
I
7 7
~Q~l_
I
I
lsi <----------------product--------------------------> 101
Ll
L1Combined AQ Register
Hultiply Integer
HPY
.. 02 (0)
FORMATI
Basic Instruction Format (See Figure 2-U.
SUMMARYI
C(Q) x CIY) -> ClAQ), right adjusted
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-55
Al39
FIxED POINT MULTIPLICATION
se,
HODIFICATIONS:
AI. except CI,
INDICATORS:
(Indicators not listed are not affectej)
SCR
Zero
If C(AQ) = 0, then ON; otherwise OFF
Negative
If C(AQ)O = 1. then ON; otherwise OFF
NOTES:
Two 3&-bit integer factors (including sign) are multiplied
to form a 11-bit integer product (including sign). which
is stored in AQ, right-adJusted.
AlD is filled with an
Uextended sign bit-.
o
0
I
o 0
_1-1---
3
_0 1
5_
I
I
Isl<-----factor--------->.
I t
J
x
3
5
I .J.
1
LL--_
J
Isl<----~factor--------->1
Q Register
Hain store Location Y
vieldlng
000
7
01 2
J I I
1
Islsl<----------product-------------------------------->I
I
I
I
_
I
Coabined AQ Register
In the case of (-2··35) x (-Z·.35)
to represent
the product rather
overflow can occur.
= +2 •• 70.
,than
AQ1
the
Is used
sIgn.
No
REVIEW DRlIFT
SUBJECT TO CHANGE
October, 1915
2-5&
AL39
FIXED POINT
DIV
Oi v I'de Integer
FORMATI
Basic
SUMMARYI
C(Q) I
Format (See Figure 2-1).
C(Y) intege~ Quotient -> CeQ)
remainde~
MODIFICATIONS.
All
INDICATORS:
(Indicato~s
If
506 (0)
Inst~uction
integer
OIVlS10~
-> CeA)
not listed are not affected)
If
diylSioD-1a~placel
=
DO di~ision
takes plac ••
=
Zero
If ceQ)
0, then ON;
other"ise OFF
If divis~r
0, then ON;
other"isl! OFF
Negative
If C(Q)O = 1, then ON;
other"ise OFF
If dividend < 0, then ON;
other"ise OFF
-
NOTESt
A 3&-blt integer dividend (including sign) Is divided by a
l6-blt integer divisor (including sign) to form a
36-blt
integer quotient
(including Sign)
~nd a 36-blt integer
remainder (including sign). The remainder sign is eQual
to the dividend Sign unless the remain~er is zero.
o
o
I
o
0
0
-1~
1
I
I
lsi <-----dlvldend------->I
l-L--
J
,
_______________ 3
~5~
I
I
Isl<-----divisor-------->1
LL--_
Q Register
Main
,
Sto~e
Location Y
vlelding
0 0 3
D 1
5
: 1
1
151 <----remainder-------> I
L I
I
A-Register
If the dividend
=
o
0
3
-'l-L-_
5
I I
I
Isl<----quotient-------->1
L1--_
I
l-Register
=
-2.·35 and the divis~~
-1
or If
the
divisor = 0, then division does not take place.
Instead,
a Divide Check fault occu~s, C(Q)
contains the dividend
magnitude,
and
the Negative
indi=ator reflects the
d i vi den d sIgn.
REVIEW DRAFT
SU9JECT TO CHANGE
October, 1975
2-51
AL39
FIXED POINT DIVISION
01 \I ide Fract i on
DVF
507 (0.
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMHARY.
C(AQ) I Cry)
f~actlona'
HODIFICATIONSI
All
INDICATORS:
(Indlcato~s
f~actional
remainde~
Quotient -> CIA.
-> C(Q)
not listed are not affected)
If no diViSion takes place,
If diViSion takes glace:
=
=
Zero
If C(A)
0, then ON;
otherwise-OFF
If diviso~
0, then ON;
otherwise OFF
Negative
If CeA)O = 1, then ON;
otherwise OFF
If dYvide~d < 0, then ON;
otherwise OFF
NOTES.
A 71-blt fractional dl\lldend CinclucUng Sign) is divided
bv
a
36-bit
fractional divisor yielding a 36-blt
f~actional
Quotient UnclucHng Sign)
and
a
36-bit
fractional
remainder
(Including
sign).
C(AQ)71 is
19nored; bi t pbsi t Ion 35 of the rellainder corresponds to
bit position· 70 of the cUvldend. Tne rellainder sign Is
eQua I to the 01 vidend sIgn un I ess the ~ellla Inder· is zero.
o
0
7 7
_.ILl
I I
Q 1
: I
lsi <--------------------dl\lldend---------------------> I xl
L.1
.L..l.-
Comb Ined AQ-Register
0
0 3
___________________
-KO~l
I
I
~
I
I
lsI <------divisor------->I
1
J I
Hain store Location Y
yielding
o0
_.ILl
3
5
I I
Is' <------Quotient------>I
1 I
I
A-Re ~i ster
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-58
0 0 3
-i~
I
_______________
~5~
J
I
lsI <----remainder-------> I
Ll.--
I
Q-Register
AL39
FIXED POINT DIVISION
If Idlvidendl >= Idlvisorl or If the divisor = O. dIviSion
does not take place.
Instead,a Divide Check Fault
occurs, CCAQ) contains the dividend ",a~n1tude in absolute,
and the Negative indicator reflects the divide~d sign.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Al39
FIXED POINT NEGATE
Negate A
NEG
. FORHATa
531 fO)
Basic Instruction Format (See Figure 2-1).
SUMMARY'
-CtA) -> CIA)
MODIFICATIONS:
All. but none affect instruction execution.
IN OICA TORSI
(Indicators not listed are not
= O.
if C(A)
~
0
affecte~)
then ON; otherwise OFF
Zero
If CfA)
Negative
If CfAIO = 1. then ON; otherwise OFF
Overflow
If range of A is exceeded. then ON;
NOTES:
ot~erwise
OFF
The NEG instruction changes the number in A to its
negative (if _ 0). The operation is performed bV for~Ing
the two·s complement of the string of 3& bits.
Attempted repetition with RPL causes
Fault.
a~
Illegal
Procedure
Negate long
NEGL
533 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
-C(AQ)
MODIFICATIONS.
All. but none affect
INDICATORS'
CIndicators not listed are not
-> C(AQ)
if CCAQ) _ 0
1nstruction execution.
affecte~)
Zero
If CCAQ) = Of then ON; otherwise OFF
NegatIve
If CCAQaO = 1, then ON; otherwise OfF
Overflow
If range of AQ is exceeded, then ON; otherwise OFF
NOTES-
The NEGL instruction changes the num3er 1n AQ to its
negative (11 _ 0). The operation 1s ~erformed bV for~ing
the two·s complement of the string of 72 bits.
Attempted repetition with RPL causes
FauJt.
REVIEW DRlIFT
SUBJECT TO CHANGE
Oc tober, 1CJ75
2-&0
a~
II legal
Procedure
Al39
FI(EO POINT COMPARISON
Comp~re
CHG
Magnitude
405 ,
FORHATS
Basic Instruction Format (See Figure 2-1).
SUMMARY:
IC(A) I sa tC(v) I
MODIFICATIONSI
All
INDICATORSI
(Indicators not listed are not
= IC(Y)I,
affecte~)
Zero
If IClA)1
Negative
If IC(A)' < tCey)., then ON; otherwise OFF
then ON; otherwise OFF
211
Compare Masked
CHI(
FORHATa
Basic Instruction Format eSee Figure 2-1).
SUHMARYS
For 1
•
= 0,
(0)
1, ••• t 35
CeZ)i = -C(Q)l ,
(CeA)i • CIY)i)
HODIFICATIONS.
All
INDICATORS'
(Indicators not listed are not
= 0,
affecte~)
Zero
If CeZ)
Negative
If C(Z)O = 1, then ON; otherwise OFF
NOTESI
Q)
then ON; otherwise OFF
The CHK instruction compares the contents of bit positions
of A and Y for Identitv that are not lasked bv a 1 in the
corresponding bit oosition of Q.
The Zero indicator Is set ON if the comparison Is
successful for all bit positIons; i.e., if for all 1=0,
1, ••• ,35 there Is e.itherlCCAH = C(Y)i
lthe identical
case) or C(Q)i = 1 (the ~asked case); otherwise, Zero
indicator Is
~et
OFF.
The Negative Indica~or is set ON if the comparison Is
unsuccessful for bit position 0; i.e., if C(AlO • C(Y)O
(they are nonidentical) as well as CCQ)O
0 (they are
unmasked); otherwise, Negative indicator is set OFF.
=
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-&1
AL39
FIXED POINT COMPARISON
115 (0)
Compare "11th A
CMPA
FORHATS
Basic Instruction Format (See Figure 2-1).
SUMMARYI
CIA)
MODIFICATIONSI
All
INDICATORSI
(Indicator~
II
CtY)
not listed are not affected)
The Zero CZ), Negative IN), and Carr, Ce) indicators 3re
set as follows.
AlgebraIc
CQmQ~aD-lSlqned
z u
~
RJtU1.jjm
llsm
0
0
0
CU) > C( Y)
CIA)O
:
0
0
1
CU)
>
Cly)
1
0
1.
e CA)
.::
C IV)
CCA)a
= C(Y)O
0
1
0
CIA)
< C (y)
0
1
1
Cf4 )
<
C(A)a
= 1,
~~cal
C(V)
ComQac~
BInary Operands)
a, C( V) 0
CIV)O
=1
=0
(Un$igoed PO$ltiye alnary Operands)
Z k
a
0
CeA)
<
1
1
CIA)
= CIY)
o
1
C(A) > cry)
C(Y)
117 (0)
Compare "'th AQ
CHPAQ
FO~HATI
BasiC Instruction Format (See Figure 2-1).
SUMMARYI
CCAQ)
MODIFICATIONSI
All except OU, Ol, CI, SC t SCR
REVIEW DRAFT
SUBJECT TO CHANGE
October, lY75
u· elY-pair)
2-&2
AL39
Ft(EO POINT COHPARISON
INDICA TORSI
(Indicators not listed are not affected'
The Zero (Z), Negative (N), and CarrV (C)
set as follows.
1..
ri
k
&!til1.llD
0
0
0
C (A 0)
> C(Y-palr)
0
0
1
C (A Q)
> ClY-pair)
1
0
1
C fA 0)
= C(Y-palr)
0
1
0
C (AQ) < Cn-palr)
0
1
1
e (AQ) < eeY-palr)
l.~aJ
indicators
are
USIO
C(AQ)O = 0, C(Y-cair)O = 1
CIAQ)O
=
C(Y-pair)O
C(AQ)O = 1, e(Y-cair)Q :: 0
Comparison (Unsigned PQsitlyp- aioary Operands)
D O C lAQ) < C (V-palr)
CKPQ
= C(Y-pair)
1
1
C(AQ)
o
1
C(AQ) > eeY-pair)
Compare with Q
116 (0)
FORHATI
Basic InstructIon Format (See Figure 2-1).
SUMMARYI
C(Q)
MODIFICATIONS:
At I
INDICATORSI
(Indicators not listed are not
1*
C(Y)
alfecte~)
The Zero (Z), Negatlve (N), and Carri (el indicators are
set as follows.
REVIEW DRAFT
SUB~ECT TO CHANGE
October, 1975
2-&3
Al39
FIXED POINT COMPARISON
A..LlUc..a..ls;~.2l'D..Q a.r:l.s. Q 0
CHPXn
(Sigoed £1.i...O.at:.L.QQ e.r:..3Ili1.sl
Z
Ii
Co
RUiitiJm
Sign
0
0
D
ceQ) » C( V)
C(Q)O = 0, C(V)O = 1
D
0
1
ceQ) » C tV)
1
0
1
ceQ)
D
1
0
C(Q) < C co
0
1
1
ceQ) < C(V)
o
0
ceQ)
1
1
ceQ) = CO')
o
1
ctQ)
= eeY)
C (Q)O
= C CY) 0
C (Q) 0 = 1, C (Y) 0 = 0
CIV)
<
ClY)
>
10n (0)
Compare with Xn
• FORHATI
SU"HARVI
Basic Instruction
For n
= O.
'orm~t
(See Figure l-I) •
1, ••• , or 7 as determined oy operation code
C(Xn) :: C(Y)D,17
MODIFICATIONS:
All except CI. SC, SCR
INDICATORS:
(IndicatorS not listed are not affected)
The Zero (Z), Negative (N), and Carry (C)
set as f 0 I I ow s.
Z
ti
indicators
are
t.
000
C IXn) » C(V)O,17
a
o
0
1
COCn) » C(Y)O,17
1
0
CeXn)
1
0
1
C(Xn) < C(Y)Q,17
011
C(Xn) < C(V)O,17
= ClV)O,17
C(XnlO : 0, C(V)O
=1
C(Xn)O : C(Y)O
C(XntO
=
1, ClYtO
=0
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
Al39
FI(ED POINT COMPARISON
o
0
ClXn)
<
1
1
ClXn)
= CeY)O.17
o
1
C(Xn)
>
C(Y)O.17
C(Y)O,17
Compare with Limits
CWL
111 (0)
FORHAT:
Basic Instruction Format (See Figure 2-1).
SUMMARYI
C(Y)
II
closed interval tC(A);CCQ»)
ecY)
II
CCQ)
MODIFICATIONS.
All
I NDICATORSI
(Indicators not listed are no t a f f ected J
Zero
If CeA) <= elY) <= C CQ) or ce A) >= CIY) >=
otherwIse OFF.
Negat lve
The
(N)
and
Carry
IC)
C
IQI. then
ON;
Indicators are set as
10110Ns.
NOTES'
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
N
C.
JaUtiJm
~
0
0
C(Q) :> C(Y)
C(Q)O = O. eeY)o
0
1
CeQ) :>= C IY)
elQ)O
1
0
ceQ) < C(Y)
C(Q)O
1
1
ceQ) < elY)
CIQ)O = 1. ceY)o
=1
= ceY)o
= CIY)O
=0
The CWL instructIon tes's the value of ClY) to deteralne
If it is within the range of values set bv CeA) and CeQ).
The comparison of elY) wIth ceQ) locates eey) with resoect
to the interval if C(Y) is not contained within the
interval.
2-65
AL39
FIXED POINT MISCELLANEOUS
SZN
Set Zero and Negative Indicators
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
Set indicators according to C(Y)
MODIFICATIONSI
AII
INDICATORSI
(Indicators not listed are not
If C(Y)
Negative
If
affecte~)
Set Zero and Negative Indicators and Clear
FORHAT.
(0)
= D. then ON; otherNlse OFF
C(Y)O = 1, then ON; otherNlse OFF
Zero
SZNC
23~
21"(0)
Basic Instruction Format (See Figure 2-1).
Set indicators according to elY)
00 ••• 0 => elY)
MODIFICATIONSI
All
INDICATORSI
(Indicators not listed are not affected)
except DU, Dl, CI, SC, SCR
= 0.
Zero
If C(Y)
Negative
If C(Y)O = 1, then ON; otherNise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
then ON, otherNlse OFF
2-&&
AL39
BOOLEAN AND
AND to A
ANA
375
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY.
ceAli t C(Y)i
MODIFICATIONSI
A II
INDICATORSI
(Indicators not listed are not
->
C(A)1 for 1
= (0.
1 • • • • • 35)
affecte~)
Zero
If CeA) : O. then ON; otherMise OFF
t-4egative
If CeA)O
= 1.
then ON; otherwIse OFF
AND to AQ
ANAQ
-FORHATa
377 (0) .
Basic Instruction Format (See Figure 2-1).
SUMMARYI
C(AQ)i & CrY-pair)!
MODIFICATIONS'
All except OUt DL. CI. SC. SCR
INDICATORS.
(Indicators not listed are not
->
C(AQ)i for 1
= CD.
If C(AQ) = O. then ON; otherwise OFF
Negative
If CeAQ)O
= 1.
1 ••••• 71)
affecte~)
Zero
ANQ
(D)
then ON; otherwise OfF
AND to Q
37& (0)
FORMAT:
Basic Instruction Format (See Figure 2-1).
SUMMARY'
CeQ)i & CeYH -> CeQ)i for i
MODIFICATIONSI
AI.
REVIEW D~AFT
SUBJECT TO CHANGE
October, 1975
2-&7
= (0.
1 • • • • • 35)
AL39
BOOLEAN AND
INDICATORSI
(Indicators not listed are not affectel)
CeO) :
Zero
If
0, then ON; otherwise OFF
NegatIve
If C(O)O :
1, then ON; otherwise OFF
AND to Storage A
ANSA
355
FORHATa
aasic Instruction Format (See Figure 2-1).
SUMMARY'
C(A)1 "C(YH -> Cry)! for
MODIfICATIONS'
All except OU, ol, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
j
:
(0, 1, ••• , 35)
Zero
If Cry) : 0, then ON; otherwise OFF
Negative
If CCY)O : 1, then ON; otherwise OFF
... NOTESI
Attempted repetitlon with RPl causes
Fault.
a~
II legal
AND to Storage Q
ANSQ
Basic Instruction Format (See Figure 2-1).
SUMMARY'
C(Q)l i. CCY)! -> CCY)l for 1 :
MODIFICATIONS:
All except OU, oL., CI, SC, SCR
INOICATORSI
(Indicators not listed are not affectej)
If Cry) :
Negative
If CCY)O
NOTESI
CO,
1, ••• .,
35)
0, then ON; otherwise OFF
= 1,
then ON; otherwise aFF
Attempted repetition with RPl causes
Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Procedure
356 (0)
FORHATa
Zero
(0)
2-&8
a~
Illegal
Procedure
AL39
BOOLEAN AND
3ltn
AND to Storage Xn
ANSXn
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMHARYI
For n
= O.
1 ••••• or 7 as determined
C IXn)! l C (Y) 1 -> Cry) i
All except OUt DL. CI. SC. SCR
IN OICA TORS I
(Indicators not listed are not
Zero
If C(Y)O,17
Negative
If CIYIO
NOTESI
= D.
= 1.
= CO.
for i
MODIFICATIONSI
by
operation code
1 ••••• 11)
affecte~)
then ON; otherwise OFF
then ON; otherwise OFF
Attempted repetition with RPL causes
Fault.
a~
Illegal
Procedure
AND to Xn
ANXn
36n (0)
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARY.
For n
= D.
(0)
1 ••••• or 7 as deter.ined
C(Xn)l l C(Y)l
->
C(Xn)l for i
MODIFICATIONSI
All except CI, SC. SCR
INDICATORS:
(Indicators not listed are not
by
= (0.
operation code
1 ••••• 17)
affecte~)
= O. then ON; otherwise OFF
CCXn)O = 1, then ON; otherwIse OFF
Zero
If C(Xn1
Negatlve
If
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
AL39
BOOLEAN OR
OR to A
ORA
275 (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
C(A)1 I C(Y)i
MODIFICATIONS!
A II
INDICATORS:
(Indicators not listed are not affected)
Zero
If C(A)
Negative
If C(A)O
= D,
= 1,
->
t~en
CrAll for 1 = (D, 1, ••• , 35)
ON; otherwise OFF
then ON; otherwise OFF
OR to AQ
ORAQ
FORHAT!
• SUMMARY'
277 (0)
Basic Instruction Format (See Figure 2-1).
CCAQ)i f C(Y-pair)i -> C(AQ)l for 1
se,
= (0,
MODIFICATIONS'
All except DU, Ol, CI,
1 NDICATORS I
(Indicators not listed are not affected)
1, ••• , 71)
SCR
= 0, then ON; otherwise OFF
C(AQ)O = 1, then ON; otherwise OFF
Zero
If C(AQ)
Negative
If
OR to Q
ORQ
276
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMHARY'
C (Q) 1 t C (Y) I - > C ( Q) i
HODIFICATIONS!
All
INDICATORS:
(IndIcators not listed are not affected)
Zero
If CeQ)
REVIEW CRAFT
SUBJECT TO CHANGE
October, 1975
= D,
(Q)
for 1 = (0, 1, ••• , 35)
then ON; otherwise OFF
2-70
Al39
BOOLEAN OR
Negative
If C(QID
= 1.
then ON; otherwise OrF
OR to Storage A
ORSA
2t.i5 (0)
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARY I
C(A)i I CCYII
MODIFICATIONSI
AI. except OUt OL. CIt SC, SCR
INDICATORSI
CIndicators not listed are not
Zero
If elY)
Negative
If CCY)!
NOTES'
ORSQ400
= O.
= 1.
->
CCY)1 for i
= CD.
1 ••••• 35)
affecte~1
then ON; otherMise OFF
then ON; otherwise OFF
Attemoted repetition with RPL causes aA Illegal
Fault.
OR to Storage Q
·25& CD)
FORHATa
Basic Instruction Format CSee Figure 2-1).
SUMMARYI
C(Q)! I CCY)1
MODIFICATIONSI
All except DU, DL. CIt SC, SCR
INDICATORSI
CIndicators not listed are not
CCY) for I
= CO.
1.
• ••• 35)
affecte~)
= 0, then ON; otherwise OFF
CeYIO = 1, then ON; otherwise OFf
Zero
If CCY)
Negat i ve
If
NOTESI
->
Procedure
Attempted
Fau It.
REVIEW DRAFT
SUBJECT TO CHANGE
Cctober. 1975
repetition with RPl causes 3n Illegal
2-71
Procedu~e
AL39
BOOLEAN OR
2ltn
OR to storage Xn
ORSXn
FORHAT'
SUMMARY 1
Basic Instruction Format (See Figure 2-1).
For n = 0, 1, ••• , or 7
C(Xn)l a C(Y)1
->
a~
determined
C(Y), for 1
~V
= (0,
All except DU, OL, CI, SC, SCR
INDICATORS:
(Indieators not listed are not affectej)
Zero
If C(Y)O,17 = D, then ON; otherwise OFF
Negati.ve
If C(Y)O
= 1,
operatIon code
1, •••• 17)
MODIfICATIONS.
NOTESI
then ON; otherwise OFF
Attempted repetitIon wi.th RPL causes
fault.
a~
Illegal
Procedure
OR to Xn
ORXn
..FORMAT I
SUMMARYI
(0)
26n (D)
Basic Instruction Format (See Figure 2-1) •
For n = 0, 1, ••• , or 7 as determined DV operatIon code
C{Xn)i
I e(Y)l ->
C(Xn)l fo,. i.
= (0,1,
MODIfICATIONS:
AI
INDICATORS:
(Indicators not listed are not affectej)
I
••• , 17.
except CI, SC, SCR
Zero
If C(Xn)
Negative
If C(Xn)O
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1q75
= 0,
= 1.
then ON; otherwise OFF
then ON;' otherwise. OFF
2-72
AL39
300LEAN EXCLUSIVE OR
EXCLUSIVE OR to A
ERA
675 (01
FORHATa
Basic Instruction Format (See Figure 2-11.
SUMMARY'
CCA)l • C(V)i -> CIA)! for 1
MODIFICATIONS.
All
INDICATORS'
(Indicators not listed are not affectedl
Zero
If CeA)
Negative
If C(A)O
ERAQ
= D,
= 1,
= CO,
1, •••• 351
then ON; otherwise OFF
then ON; otherwise OFf
EXCLUSIVE OR to AQ
FORHATa
-
677 (0)
BasIc Instruction Format (See
SUMMARYl
CCAQli • elY-pairli -> CeAQ)i for 1
HOOIFICATIONSI
All except OU, DL, eI, se, SCR
INDICATORSl
(Indicators not listed are not
= ee,
1 ••••• 71)
affecte~)
= 0, then ON; otherwise OFF
C(AQ)O = 1, then ON; otherwise OFF
Zero
If C(AQ)
Negative
If
ERQ
2-1).
Fig~re
EXCLUSIVE OR to Q
676 (0)
FORHAT'
Basic Instruction Format eSee Figure 2-1).
SUMMARva
C(Q)i • C(VII -> CeQ)! for i
MODIFICATIONS I
All
INDICATORSI
(IndIcators not listed are not
Zero
If C(Q)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
= 0,
= (0,
1, •••• 3S1
affecte~)
then ON; otherwise OFF
2-73
AL39
BOOLEAN EXCLUSIVE OR
NegatIve
If C(Q)O = 1. then ON; otherwise OFF
EXCLUSIVE OR to Storage A
ERSA
655 (0)
FORHATI
9aslc Instruction Format (See
SUMMARYI
C(A)i • C(Y)l -> C(Y)i for i
MODIFICATIONSI
AI I except OUt Ol, CI, SC, SCR
INDICATORS:
(Indicators not listed are not affectej)
Zero
If C(Y)
Negative
If C(Y)O
NOTESI
= 0,
= 1,
Figur~
= (0.
2-1).
1, •••• 35)
then ON; otherwise OFF
then ON; otherwise OFF
Attempted repetitIon with RPl causes
Fault.
a~
II legal
EXCLUSIVE OR to Storage Q
ERSQ
656 (0'
FORHATS
Basic Instruction Format (See Figure 2-1).
SUMMARYI
C(Qll • C(Y)1
MODIFICATIONSI
All except OU, OLe CI, SC, SCR
IN DICA TORSI
(Indicators not listed are not affected)
Zero
If C(Y)
NegatIve
If C(Y)O
NOTESI
= 0,
= 1,
->
e(Y)I for i
= (0,
1 ••••• 35)
then ON; otherwise OFF
then ON; otherwise OFF
Attempted repetltion with RPl causes
Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
Cctober. 1975
Procedure
2-7"
a~
II legal
Procedure
AL39
300LEAN EXCLUSIVE OR
EXCLUSIVE OR to Storage Xn
ERSXn
6ftn (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARYS
For n
= D.
1, •••• or 7 as determined
C(Xn)i • CIY)!
->
C(Y)l for i
~y
= (0.
1 ••••• 17)
MODIfICATIONS:
Ala except OU, OL, CI, SC, SCR
IN DrCATORS:
(Indicators not listed are not affectej)
Zero
If C(Y)O,17 = 0, then ON; otherwise
operation cOde
OF~
,
NOTES,
Attempted repetition with RPL causes an Illegal
Fault.
Procedure
EXCLUSIVE OR to Xn
ERXn
...FORHATa
SUHHARYI
66n (0)
Basic Instruction Format (See Figure 2-1) •
For n
= 0,
1, •••• or 7 as determined Dy operation code
C(Xn)i • C(Y)i
->
C(Xn)i tor i
= (0.
MODIFICATIONsa
All except CIt SC, SCR
INDICATORSI
(Indicators not listed are not affected)
Zero
If CeXn)
Negative
If C(XnlO
REVIEW DRAFT
SUBJECT TO CHANGE.
Oct obert 1975
= 0,
= 1,
1, •••• 11)
then ON; otherwise OFF
then ON; otherwise OFF
2-75
AL39
315 (0)
Comparative AND with A
CANA
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHH-ARY'
C (Z) i
MODIFICATIONS.
A II
INDICATORS:
(Injicators not listed are not
= C ( A) i
,
C ( Y) i
f
or i
= (0,
1. • •• ,
35 )
affecte~)
ZERO
If CeZ) = 0, then ON; otherwise OFF
Negative
If C(Z)O = 1, then ON; otherwIse OFF
317
ComparatIve AND with AQ
CANAQ
FORHAT.
"'SUMMARYt
Basic Instruction Format (See Figure 2-1).
C(l)i
= C(AQ)l
, C(Y-palr)! for
HODIFICATIONSI
All except OU, Ol, CI, SC, SCR
INDICATORSJ
(Indicators not listed are not
j
=
(0, 1, ••• ,
If Cel) = 0, then ON; otherwise OFF
Negative
If C(Z)O = 1, then ON; other"lse OFF
31 & (0)
ComparatIve AND with Q
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUMMARya
Cel)i
MOUIFICATIONS'
AI1
INDICATORSI
(Indicators not listed
ZERO
= C(Q)l
If C(Z)
= 0,
71)
affecte~)
Zero
CANQ
(0)
& C(Y)l for
i
= (0,
1, ••• ,
35)
are not affected)
then ON; other"lse OFF
REVIEW DRAFT
SUBJECT to CHANGE
October, 1975
2-7&
AL39
BOOLEAn COMPARATIVE AND
Negative
If C(Z)O
= 1,
than ON; otherwise OFF
Comparative AND with Xn
CANXn
30n (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
For n
= 0,
C(Z)i
or 7 as determined =»v operation code
1, ••• ,
= C(Xn)l
~
e(Y)l for 1
= (0,
1, ••• , 17)
MODIFICATIONS:
All except CI, SC, SCR
INDICATORS:
(Indicators not listed are not affectej)
Zero
If C(Z)
Negative
If CeZ)O
= 0,
= 1,
then ON; otherwise OFF
then ON; otherwise OFF
REVIE~ DRAFT
SUBJECT TO CHANGE
October, 1975
2-77
AL39
BOOLEAN COMPARATIVE NOT
Comparative NOT with A
CNAA
215 (0)
FORHATS
Basic Instruction Format (See Figure 2-i).
SUMMARYI
C(Z)!
MODIFICATIONSI
A I.
INDICATORS:
(Indicators not listed are not affected)
= C(A)!
Zero
If C(Z)
Negative
If C(Z)O
CNAAQ
= 0,
, -elY), 'or I
= (0,
1, ••• , 35)
then ON; otherwise OFF
= 1t
then ON; otherwIse OFF
ComparatIve NOT with AQ
217 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
CrZ)l
MODIFICATIONSI
All except DU, Ol, CI, SC. SCR
INDICATORSI
(Indicators not listed are not affected)
= C(AQ)l
-elY-pair)! for 1
=
(O~
1.
~.,
71)
= 0, then ON; otherwise OFF
C(Z)O = 1, then ON; otherwise OFF"
Zero
If C(Z)
Negative
If
CNAQ
~
Comparative NOT with Q
21& (0)
FORHAT:
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
C ( Z)!
MODIFICATIO'NSI
All
INDICATORS:
(Indicators not listed are not affectej)
= C( Q) i
Zero
If CIZ)
Negative
If C(Z)O
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
= 0,
= 1,
,
-c ( Y)
i for
= (0, 1, ••• , 35)
then ON; otherwise OFF
then ON; otherwise OFF
2-78
AL39
BOOLEAN COHPARATIVE
Comparative NOT with Xn
CNAXn
20n (0)
FORHAT I
Basic Instruction Format (See Figure 2-1 ••
SUMHARYI
For n
= O.
ceZli
~OT
1 •••• , or 7 as determined oy operation code
= C(Xn)l
~
-C(Y)i
for i = (0. 1, ••• , 17)
except CI, SC, SCR
"ODIFICATIONS'
All
INDICATORS'
(IndIcators not listed are not affecte:J)
= 0,
then ON; otherwise OFF
Zero
If C(Z)
Negative
If C(Z)O = 1, then ON; otherwise
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
~FF
AL39
FLOATING POINT DATA MOVEMENT lOAD
DFlD
ft33 (0)
Oouble Precision Floating load
FORHATa
Basic Instruction Format
SUMHARYa
C(Y-pair)O,7 -> ClE)
C(Y-pairt8,71
00 ••• 0
->
->
C(AQ)O,G3
C(AQ)Gft,71
except DU, Ol, CI, SC 9 SCR
MODIFICATIONS'
All
INDICATORsa
(Indicators not
Zero
If C(AQ)
Negative
If C(AQ)O
FLO
(See Figure 2-1).
lIsted are not
affecte~)
= 0, then ON; otherwise OFF
= 19 then ON; otherwise OFF
431 (0)
Floating load
FORHATI
Basic Instruction Format (See Figure
SUHHARY:
C(Y)097 -> C(E)
C(Y)8,3S
00 ••• 0 ->
->
C(AQ)O,27
C(AQ)30~71
except CI, SC9 SCR
HODIFICATIONSI
All
INDICATORS:
(Indicators not
listed are not affecte::U
Zero
It C(AQ) .: 0, then ON; otherwise OFF
Negative
IF C(AQ)O .: 1,
then ON; otherwise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-1).
2-80
Al3CJ
FLOATING POINT DATA MOVEMENT STORE
457 CO)
uouble Precision Floating Store
DFST
FORHATJ
Basic Instruction Format (See Figure 2-1).
SUMMARY'
MODIFICATIONSI
All except OU. DL. CIt SC. SCR
INDICATORSI
None affected
NOTES:
Attempted repetition with RPL causes
Fault.
Double Precision Floating Store
DFSTR
a~
Illegal
Rounde~
FORMATa
BaSic Instruction Format (See Figure 2-1).
SUMMARY a
C(EAQ) rounded
MODIFICATIONS.
All except CU. OL, CI,
INDICATORS:
(Indicators not listed are not
->
Procedu~e
472 (D)
ClY-palr)
se,
SCR
affecte~)
Zero
If elY-pair) = floating point 0, then IN; otherwise OFF
Negative
If CCY-pair)8 = 1, then ON; otherMise lFF
Exponent
Over f low
If exponent is greater than +121, then ON; otherwise OFF
Exponent
Under' low
If exponent is less than -128, then ON; otherwise OFF
NOTES.
The DFSTR instruction performs a dOU31e precision
round and nor~alization on C(EAQ) as it is sto~ed.
The
definition of true round 1s located under
description of the Floati"g Round (FRO) instruction.
true
the
The definition of normalization is located under the
description of the Floating Normaliz~ (FNO) instruction.
Except for tne precision of the stored result. the
instruction is identical to the FSTR l~struction.
REVIEW CRAFT
SUBJECT TO CHANGE
October9 1915
2-61
DFSTR
IlL39
FLOATING POINT DATA MOVEMENT STORE
Attempted
Fault.
repetItion with RPL causes an Illegal Procedure
Flo a tin g S t or e
FST
455 (0)
FORMATa
Basic Instruction Format (See FIgure 2-1).
SUHMARY I
C(E) -> CIY)O,1
C(A)O,2?
-> C(Y)8,35
HODIFICATIONSI
All except OU, OL, CI, SC, SCR
INDICATORS'
None af feeted
NOTESI
At~empted
repetition with RPL causes
a~
Illegal
Procedure
Fault.
FSTR
Flo a tin g S t or e R0 un d e d
"FORHATa
41 0 ( 0 )
gas i c Instr uc t ion F or mat (See Figure 2-1).
SUMMARYI
CIEAQ) rounded
MODIFICATIONSI
All except OU, Ol, CI, SC, SCR
INOICATORsa
(Indicators not listed are not affecte:U
->
= floating
CIY)
Zero
If ClY)
Negative
If C(Y)8
t::KPonent
Overflo\llf
If exponent is greater than +127, then ON; otherwise OFF
Exponent
Under flo ..
If eKPonent is less than -128, then ON; otherwise OFF
NOTESa
= 1,
point 0, then ON; otherwise OFF
then ON; otherwise OFf
The fSTR instruction
performs
a
true
normalization on C(EAQ) as it is storej.
round
The
definition of true round is located under
description of the Floating Round (FRO) instruction.
and
the
The definition of normal ization is located under the
description of
the Flo a t 1n 9 Nor :II a Ii z e ( F NO) ins t r uc ti 0 n •
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-82
FLOATING POINT DATA MOVEMENT STORE
Steps 1n the execution may be thought of as foiloNs,
Execute FNO
Execute FST
Restore C(EAQ) to original values.
Attempted repetition with RPL causes
Fault.
REVIEW ORJ!FT
SUBJECT TO CHANGE
October, 1975
2-83
a~
Illegal
Procedure
Al39
FLOATING POINT
AODITIO~
.'
DFAD
417 (0)
DOUDle Precision Floating Add
FORHATa
Oasic Instruction
SUMMARY'
(C(EAQ) +
MODIFICATIONSI
Al. except ou, Ol, CI, SC, SCR
INDICATORS:
(Indicators not listed are not affected)
For~at
C(Y-p~ir))
(See Figure 2-1).
normalIzed
->
CCEAQJ
Zero
If C(AQ) ; 0, then ON; otherwIse OFF
Negative
If C(AQ)O
Exponent
Overflow
If exponent is greater than +121, then ON; otherwise OFF
Exponent
Underf 10M
If exponent is less than -128, then ON; otherwise OFF
Carrv
If a carry out of AQO Is generated, then ON; otherwise OFF
NOTES.
= 1,
then ON; otherwise OFF
The OFAD instruction may be thought of as a Doub.e
Precision Unnormalizard Floating Add (OUFA) instruction
follo"ed by a Floating Normalize (FNO) instruction.
The definition of normalization Is located under the
description of the Floating Normalize (FNO) instruction.
DUFA
Double Precision unnormalized Floating Add
FORMAT:
Basic Instruction Format (See Figure 2-1).
SUMMARY:
C(EAQ) + ClY-pair)
HODIFICATIONS:
All except OU, OL, Ct. SC, SCR
RE:.VIEW
->
"37 (0)
C(EAQ)
OR~FT
TO CHANGE
Oc t ober, 1 Y75
SUB~ECT
2-84
AL3!)
FLOATING POINT ADDITION
INDICATORS.
(Indicators not listed are not
= 0,
affecte~.
Zero
If C(AQ)
Negative
If CCAQ)O
E.xponent
Overflow
If exponent is greater than +127, then ON; otherwise OFF
Exponent
Under f low
If exponent is less than -128, then ON; otherwise OFF
Carry
If a carry out of AQO Is generated. then ON; otherllt1se OFF
NOTES.
= 1,
then ON; otherlltlse DFF
then ON; otherlltlse OFF
Except for the precision of the mantissa of the operand
from maIn store. the DUFA instruction is Identical to the
urA instruction.
Floating Add
FAD
475 (01
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHMARY.
(C(EAQ) + C(Y»
HODIFICATIONS.
All except CI,
INDICATORS'
(Indicators not listed are not affected)
normalized
se,
->
CCEAQ)
SCR
Zero
If CIAQ) = Ot then ON; otherlltlse OFF
Negative
If CCAQIO
Exponent
Overflow
If exponent Is greater than +127, then ON; otherlltise OFF
Exponent
Under' 1o lit
If exponent is less than -128, then ON; otherlltise OFF
Carry
If a carry out of AQD Is generated, then ON; otherwise OFF
NOTES.
= 1,
then ON; otherlltise OFF
The FAD instruction may be thought of a an iJnnor ma 11 zed
Floating Add (UrA) instructIon followed by a Floating
Normalize (FNO) instruction.
The definition of normalization is located under the
description of the Floating Normalize (FNO) instruction.
REVIEW DRAFT
SUBJECT TO CHANGE
Oct ober, 1975
2-85
AL39
FLOATING POINT ADDITION
UFA
Unnormaltzed FloatIng Add
~35
FORHATa
3asic Instruction Format
SUMMARY.
CCEAQ) • C(Y) -> CCEAQ)
MODIFICATIONS.
AI. except CI, SC, SCR
INDICATORS'
(Indicators not listed are not affectej)
=
(See
Flg~re
(O)
2-1).
Zero
If C(AQ)
Negative
If CCAQ)O
Exponent
If exponent is greater than .127, then ON; otherwise OFF
0, then ON; otherwise OFF
= 1,
then ON; otherwise OFF
Overflo~
Exponent
Underflow
If exponent is less than -128, then ON;
Carry
If a carry out of AQO is generated, then ON; otherwise OFF
NOTES.
otherwise OFF
The UFA instruction is executed as follows.
The mantissas are aligned by shifting the mantissa of
the operand having the a'gebralcal Iy smaller exponent
to the right
the number of pl3ces equal
to the
absolute
value
of
the difference in the two
exponents.
Bits shifted beyond the bIt pOSItion
equivalent to AQ71 are lost.
The algebraically larger exponent replaces ClE).
The sum of the mantissas replaces CCAQ).
If an overflOW occurs during addltion, then;
CCAQ) are shifted one place to the right.
C(AQ)O Is inverted to restore the sIgn.
CCE) is increased by one.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-6&
AL39
FlOATI~G
Double Precision Floating
DFSB
POINT SUBTRACTION
577 (D)
Subt~act
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY:
(CCEAQ) - CIY-pair»
MODIFICATIONS:
All except OU, Dl, CI, SC. SCR
INDICATORS:
(Indicators not listed are not affectej)
normallzed
->
C(E_Q)
Zero
If C(AQ) :
Negative
If C(AQ)O = 1, then ON; otherwIse OFF
Exponent
Overflow
If exponent Is greater than +127, then
Exponent
Under f low
If exponent Is less than -128, then ON; otherwise OFF
Carry
If a carr, out of AQO is generated, then ON; otherwise OFF
NOTESI
OUFS
0. then ON; otherwise OFF
~N;
otherwise OFF
The OFSB instruction Is identical to the Double Precision
Floating Add (OFAD)
instruction wlt~ the exception that
the 2·s complement of the mantissa of the operand fro.
main store Is used.
DOUble Precision unnormalized Floating Subtract
FORHAT:
3asic Instruction Format (See Figure 2-1).
SUMMARYI
CCEAQ) - C(Y-pair)
MODIFICATIONS:
All except OU, Olt CI. SC, SCR
INDICATORS:
(Indicators not listed are not affected)
= 0,
->
537
(D)
C(EAQ)
Zero
If CCAQ)
Negative
If C(AQ)O
£)cponent
Overflow
If exponent Is greater than +127, then ON; otherwise OFF
I:)(Ponent
Under f low
If exponent is less than -128, then ON; otherwise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
October, lC~75
= 1,
then ON; otherwise OFF
then ON; otherwise OFt
2-87
Al39
FLOATING POINT SUBTRACTION
Carry
NO TESI
If a carry out of AQO is generated, th!n ON; otherwIse OFF
Except for the precision of the mantisia of the operand
from main store, the DUFS instr~ction is indentical with
the UFS instruction.
Floating Subtract
FSB
575 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
(C(EAQ) -
MODIFICATIONSI
All except CI, SC, SCR
INDICATORSI
(Indicato~s
normal ized -> ClEAQ)
Cry)~
not listed are not
affecte~)
7 0, then ON; otherwise OFF
Zero
If
Negative
If C(AQ)O
Exponent
Overflow
11 exponent Is greater than +127, then ON; otherwIse OFF
EJCponent
Under f low
If exponent is less than -128, then ON; otherwise OFF
Carry
If a carry out of AQO is generated, then ON; otherwise OFF
NOTES:
~(AQ)
= 1,
then ON; otherwise OFF
The FSB instruction may be thought of as an Unnormalzled
Floating Subtract (UFS) instruction followed by a Floating
NormalIze (FNO) instruction.
The definition of normalization is located under the
description of the Floating Normalize (FNO) instruction.
UFS
Unnormalized Floating Subtract
FORMAT:
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
C(EAQ) - C(Y)
MODIFICATIONS I
AIS
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
->
535 (0)
C(EAQ)
except CI, SC, SCR
2-88
AL39
FLOATI~G
INDICATORS'
POINT SUBTRACTION
(Indicators not listed are not affected)
= 0,
Zero
If CCAQ)
Negative
If CCAQ)O = 1, then ON; otherwise OFF
Exponent
OverfloM
If exponent Is greater than +127, then ON; otherwise OFF
Exponent
Underflow
If exponent is less than -128, then ON; otherwIse OFF
Carry
If a.carry out of AQO Is generated, then ON; otherMise OFF
NOTES.
then ON; otherwise OFF
The UFS Instruction is identical
to the Unnor.allzed
Floating Add CUFA) instruction with the exception that the
2·s complement of
the mantissa of t~e operand ',..om maIn
store is used.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-89
Al39
flOATING POINT MULTIPLICATION
Double Precislon Floatlng Hultlply
DFHP
40
'+&3 CO)
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHHARYI
(C(EAQ) x CeY-pair»
MODIFICATIONSI
All except DU, Dl, CI, SC, SCR
INDICATORSI
(Indicators not listed are not
= n,
normalized
->
CCEAQ)
affecte~)·
Zero
If C(AQ)
Negative
If CCAQ)O : 1, then ON; otherwise OFF
Exponent
Overfl 0 ..
If exponent Is greater than +127, then ON; otherwise OFF
Exponent
Underf 10 ..
If exponent Is less than -128, then ON; otherwise OFF
NOTESI
then ON; otherwise OFf
The OFMP instruction may be thought
Floating
Precision
Unnormallzed
instruction followed bv a Floating
instruction.
of as a
Multiplv
Normal i ze
Double
( DUf")
(FNO)
The definition of normalIzation Is located under the
description of the Floating Norma1ize (FNO) instruction.
Double Precision Unnormalized Floating Hultiply
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMHARY I
ClEAQ) x e(Y-palr)
HODIFICATIONSI
All except DU, Dl, Cl, SC, SCR
INDICATORSI
(Indicators not listed are not affected'
->
423 (0)
CCEAQ)
Zero
11 CCAQ) = 0, then ON; otherwise OfF
Negative
If C(AQ)O = 1, then ON; otherwise OFF
Exponent
Overf I 0 ..
If exponent is greater than +127, then ON; other.ise OFF
Exponent
Underflow
If exponent is tess than -128, then ON;
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-90
otherwise OFF
Al39
FLOATING POINT MULTIPLICATION
NOTESI
Except tor the precIsion of the mantIssa of the operand
from main sto~e, the DUFM instruction I~ identical to the
Unnormalized Floating Hultiply (UFM) i~struction.
Floating Multiply
FHP
..61 (0)
FORHATa
Basic Instruction Format (See Figure Z-1).
SUMMARYI
(C(EAQ) x C(Y»
MODIFICATIONSI
All except CIt SC, SCR
INDICATORSI
(Indicators not listed are not affected)
normalIzed
->
C(EAQ)
= 0, then ON; otherwise OFF
C(AQ)D = 1, then ON; otherwise Off
Zero
If C(AQ)
NegatIve
If
Exponent
Overflow
If exponent is greater than +lZ7. then ON; otherwise OFF
Exponent
Underf .ow
If exponent Is less than -128, then ON; otherwise OFF
NOTESI
The FMP instruction may be thought of as an Unnormalized
Floating Multiply CUFM) instruction fol lowed bv a Floating
Normalize (FNO) instruction.
The definition of norlllallzatlon is located under the
descrlpt ion 0 f the F. oating Normalize (FNO) instructi on.
unnormallzed Floating Huitiply
UFM
FORMATa
BasIc Instruction Format (See Figure 2-1).
SUMMARY.
C(EAQ) x C(Y)
MODIFICATIONSI
All except CI,
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
->
.. 21 (0)
C(EAQ)
se,
SCR
AL39
FLOATING POINT MULTIPLICATION
INDICATORS.
(Indicato~s
not listed are not affected)
Zero
If ClAQ) = 0, then ON; otherwise OFF
Negative
If CCAQ)O
Exponent
Overflollt
If exponent is
Exponent
Under'low
If exponent is less than -128, then ON;
NOTES'
= 1,
then ON; otherwise OFF
greate~
than +127, then ON;
othe~wise
othe~"lse
•
OFF
OFF
The UF" instruction is executed as foilowsl
ClE) + C(YlO,7 -> C(E)
(C(AQ) x ClY)8,35)O,71 -> ClAQ)
A normalization is performed onlv in the case of both
factor mantissas being 100 ••• 0 which Is the 2·s comple~ent
approxImation to the decimal value -1.0.
The definitIon of normalization Is located under the
descrlptl'on of the Floating Nor.alize (FNO) instruction.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-92
Al39
FLOlTING POINT OIVISION
-E'oatiDg-P~iD.LDiv'sioDQ)
OouDle Precision Floating Divide Inverted
OFOI
FORMAT.
BaSic Instruction Format (See Figure 2-1).
SUMMARY'
ClY-palr)
"OOIFICATIONSI
All except OU, Ol, CI, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
521 (0)
ClEAQ) -> C(EAQ)
I
Ii-division takes
pJa~
=
II no diVision takti pi gel
Zero
If CCAQ)
0, then ON;
otherwise OFF
If divisor mantissa = 0,
then ON; otherMise OFF
NegatIve
If C(AQ)O = 1, then ON;
otherwise OFF
If dividend < 0, then ON;
otherwise OFF
Exponent
Overflo ..
If exponent Is greater than +127, then ON; otherMise OFF
Exponent
Underf 10M
If exponent Is less than -128, then ON; otherMIse OfF
NOTESI
Except for the lnterchange of the roles of the operands,
the execution of the DFOI instuction Is identical to the
execution of the Double Precision Floating DivIde (OFOV)
ins true tiO".
If the divisor mantIssa C(AQ) is zer~. the divisIon does
not take place. Instead, a Divide Check Fault occurs and
all regIsters remain unchanged.·
Double Preeislon Floating Divide
OFDV
FORHAT.
SUHHARYS
MODIFICATIONS-
REVIEW DRAFT
SUB~ECT TO CHANGE
October, 1975
567 CO)
Basic Instruction Format (See Figure 2-11.
C(EAQ)
I
eCY-pair)
->
C(EAQ)
All except OUt OL, CI, SC, SCR
2-93
Al39
FLOATING POINT DIVISION
INDICATORS'
(Indicators not 'isted are not
l~visioD
affecte~)
ta~~a~
=
=
Zero
If CCAQ)
0, then ON;
otherwise OFF
If divisor mantissa
0,
then ON; otherwise OFF
Negative
If CCAQ)O = 1, then ON;
otherwise OFF
otherwise )FF
If
divlden~
<
0, then ON;
Exponent
O"erfloM
If exponent Is greater than +121, then ON; otherwise OFF
Exponent
Under' 10M
If exponent Is less than -128, then ON; otherwise OFF
NOTES'
The OFOV instruction is executed as fol'ows.
The dividend mantissa C(AQ) is snifted right and the
dividend exponent eeE)
increased accordingly
until
IC(AQ)O,631 < JC(Y-pair)8,711.
CeE) - C(Y-pair)O,7 -> eeE)
CIAQ) I
CIY-pair)8,71 -> CCAQ)O,63
00 ••• 0 -> CCQ)64,71
If
the dIvisor mantIssa ClY-pair)S,71
is zero,
the
division does not take place.
Instead,
a Divide Check
fault
occurs, C(AQ) contains the dividend magnitude, and
the Negative indicator reflects the dividend sign.
FOI
525 CO)
Floating Divide Inverted
FORHATa
Basic Instruction Format
SUHHARYI
C(Y) I
(See Figure 2-1).
C(EAQ) -> C(EA)
00 ••• 0 -> CeQ)
HODIFICATIONsa
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1Y75
All except CI, SC, SCR
2-94
AL39
FLOATING POINT DIVISION
INDICATORsa
(Indicators not listed are not affected)
Zero
If CeA) = 0, then ON;
otherwise OFF
Negative
If CeA)O
0, then ON;
otherwise OFF
Exponent
Overflollt
If exponent is greater than +127, then ON; otherwise OFF
Exponent
Underf I Ollt
If exponent is Jess than -128, then ON; otherwise OFf
=
If divisor mantissa = 0, then
ON; otherwise OFF
If dividenj < 0. then ON;
otherwise lFf
Except for the interchange of roles of the operands, the
execution of the FOI instruction is identical to the
execution·of the Floating Divide (FOV) instruction.
NOTESZ
If the divisor mantIssa CCAQ) is zero. the division does
not take place. Instead, a Divide-Check fault occurs and
all the registers remain unchanged.
5&5 CO)
Floating Divide
FDV
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARY
C(EAQl
I
ClY)
->
CeEA)
00 ••• 0 -> C(Q)
MODIFICATtONSI
All except CI, SC, SCR
INDICATDRSJ
(Indicators not listed are not
If diviSion takes placel
=
If CeA)
a, then ON;
otherwise OFF
Np.gatlve
If CeAlO
= 1,
then ON;
affecte~'
If no
d~ision
takes place!
diviso~ mantissa
ON; otherwise OFF
If
If
divide~d
< 0,
= 0,
then
then ON;
otherwise OFF
otherwise OFF
Exponent
Overflow
If exponent is greater than +127, then ON; otherwise OFF
Exponent
Underf low
If exponent is less than -128, then ON; otherwise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-95
AL39
FLOATING POINT DIVISION
NOTES'
The FOV instruction Is executed as follows.
The dividend mantissa C(AQ) is shifted right and
the
dividend
exponent eeE)
increased accordingly until
IC(AQ)O,271 < IC(Y)8,351.
CeE) - CeY)O,7 -> CeE)
CeAQ) I C(Y)8,35 -> CeA)
00 ••• 0 -> C(Q'
If the divisor mantissa CCY)8,35
Is zero.
the division
does not take place.
Instead,
a
Divide Check fault
occurs, CCAQ) contains the dividend ~agnitude,
and
the
Negative indicator reflects the dividend sign.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-9&
AL39
FLOATING POINT NEGATE
f loa t Ing Negate
FNEG
51J (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
-C(AQ) normalized
MODIFICATIONS'
All, but none affect instruction execution.
INDICATORS:
(IndIcators not lIsted are not affected)
->
C(AQ)
Zero
If C(AQ) = O. then ON; otherwise OFF
Negative
If CCAQ)O
Exponent
OverfloM
If exponent Is greater than +127. then ON; otherwise OFF
Exponent
Under' 10M
If exponent Is less than -128, then ON; otherwise OFF
NOTES.
= 1,
then ON; otherwise OfF
This instruct 10n changes the number in C(EAQ)
to 1 ts
normalized negative (If CCAQ) ~ 0). The operation is
executed by first forming the tMO·S co.ptement of C(AQ).
and then normalizing C(EAQ).
Even If originally C(EAQ) Mere normalized, an exponent
overflow can stIlI occur. namely when CeE) = +127 and
CCAQ)
100 ••• 0 which is the 2·s complement approximation
for the decimal value -1.0.
=
The definit10n of normalization may be found under the
description of the Floating NormalIze (FNO) Instruction.
Attempted repetition w1th RPL causes an II legal
Fault.
REVIEW DRAFT
SUSJECT TO CHANGE
October, 1975
2-97
Procedure
ALJ9
FLOATING POINT NORMALIZE
Floating Normalize
FNO
573 CO)
FORMAT'
Basic Instruction Format (See Figure 2-1).
SUMMARY.
C(EAQ) normal ized -> C(EAQ)
MODIFICATIONS'
All. but none affect instruction execution.
INDICATORS a
(Indicators not listed are not
affecte~)
= floating point D. then ON;
= 1. then ON; otherwise OFF
Zero
If CCEAQ)
otherwise OFF
Negative
If CCAQ)O
Exponent
Overflo"
If exponent is greater than +127. then ON; otherwise OFF
Exponent
Underflow
If exponent is less than -128, then ON otherwise OFF
Overflo"
Set OFF
The FNO instruction normalizes the nuwber in
CCAQ) _ 0 and the Overflow indicator is OFF.
C(EAQ)
if
A normalized floating number is d~fined as one whose
mantissa lies in the interval (0.5.1.0) such that
0.5 <= ICCAQ)' < 1.0
which. 1n turn, reQuires that CCAQ)O _ C(AQ)l.
If the Overflow indicator is ON, then C(AQ) is shIfted one
place to the right, ClAQ)O is inverted to reconstitute the
actual s1gn, and the Overflow indicato· is set OFF.
Normalization is performed by shifting C(AQ)1,71 one place
to the left and reducing CIE) by 1. repeatedly, until the
conditions for C(AQ)O and C(AQ)l are met. Bits shifted
out of AQ1 are lost.
=
If CCAQ)
O. then ClE)
indlcator is set ON.
is
set
to
-128
and
the
Zero
The FHO i~struction can be used to correct overflows that
occur with fixed point numbers.
Attempted repetItion with RPl causes
Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-96
a~
Illegal
Procedure
AL39
FLOATING POINT ROUND
Double Precision Floating Round
DFRD
,+73 CO)
FORMATa
Basic Instruction format (See Figu ... e 2-1).
SUMMARY'
C(EAQ) ...ounded to 6'+ bits
"OOIFICATIONSI
All, but none affect instructIon executIon.
INDICATORSJ
(Indicators not listed are not affected)
->
CtEA~.
= floating point 0, then ON;
= 1, then ON; otherwise OFF
Ze ... o
If C(EAQ)
NegatI"e
If CCAQ)O
Exponent
Ovel""Io ...
If
Exponent
Underf low
If e)CPonent is less than -128, then ON; other ... ise OFF
NOTESI
•
ex~onent
othe"''''ise OFF
is greate ... than +127, then ON; othe ..... lse OFF
The OFRO instruction is identical to the Floating Round
(FRO) instruction except that the rounding constant used
is (11 ••• 1)&5,71 instead of (11 ••• 1)29,71.
Attem~ted
repetition ... ith RPL causes an Illegal
Procedure
Fault.
Floating Round
FRO
471 (0)
FORHATa
Basic Inst ... uction For.at (See Figure 2-1).
SUMMARY'
C(EAQ) rounded to 28 bits
HODIF~CATIONSI
All, but none affect instruction executIon.
INDICATORSI
(Indicators not listed are not affected)
= floating
->
C(EAQ)
Zero
If C(EAQ)
Negative
If C(AQ)O = 1 then ON; other ... ise OFF
[)CPonent
Ove ... flow
If exponent is greater than +127, then ON; other.ise OFF
E)Cponent
Under' 10 ..
If exponent is less than -128, then ON; otherwise OFF
REVIEW DRAFT
SUBJECT TO CHANGE
Oct ober, 1975
2-99
~oint
0, then ON; otherwise OFF
AL39
FLOATING POINT ROUND
NOTES.
If C(AQ) ~ 0, the FRO instruction performs a true round to
a precision of 28 bits and a norllaliz"ation on C(EAQ).
true round Is a rounding operation such that the sum of
the'result of applying the operation to two nu~bers of
eQual magnitude but oPPosite sign is eKactly zero.
A
The FRO instruction is executed as follows.
C ( AQ) + (11 ••• 1 ) 29, 71 - > C( AQ)
If C(AQ)O
= 0,
then a carry Is added at AQ71
If overflow occurs, C(AQ) is shifted one place to the
right and C(E) is increased by 1.
If overflow does not occur, C(EAQ) is normalized.
If
C(AQ)
is set ON.
= 0,
erE) Is set to -128 and the Zero indicator
Attempted repetition with RPL causes an II legal
Fault.
REVIEW DR'FT
SUBJECT TO CHANGE
October, 1975
2-100
Procedure
AL39
FLlATING POINT COMPARE
-floatIng-PoInt ComDacaa
Double Precision Floating Compare Magnitude·
DfCMG
FORHATa
BasIc Instruction format (See Figure 2-1).
SUMMARY'
IC(E,AQO,63)1 I' IC(Y-pair)1
MODIfICATIONS'
All except OU, OL, CX, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
= 1C(Y-palr)',
Zero
If ICCE,AQD,63)1
Negative
If IC(E,AQD,63) 1< JClY-paIr)I, then
NOTESa
then
O~;
otherwise OFF
aN; otherwise OFf
The DfCHG instruction is identical to the Double Precision
Floating Co_pare (DFCHP) jnstructlo, except that the
magnitudes 01 the mantissas are compared instead of the
algebraic values.
Double Precision Floating Compare
OFCHP
FORHAT'
Basic Instruction Format (See Figure 2-1).
SUMMARY:
C(E,AQO,63) II
MODIFICATIONSI
All except DU, DL, CI, SC, SCR
INDICATORS:
(Indicators not listed are not affected)
If CCE,AQO,&J)
= CCY-pair),
Negative
If C(E,AQO,63)
<
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
517
«Q)
C(Y-pair)
Zero
NOTES'
,.27 (0)
then ON; otherw1se OFF
C(Y-pair), then ON; otherwise OFF
The DFCHP instruction is identical to the Floating Co.~are
(FCHP)
instruction except for the preeision of the
mantissas actually compared.
2-101
AL39
FLOATING POINT COMPARE
Floating Compare Magnitude
FC"'
1t25 (0)
FORMAT'
Basic InstructIon Format (See Figure 2-11.
SUMMARY'
IC(E,AQO,27)1
MODIFICATIONS.
All except
INDICATORS'
(Indicators not listed are not affectej)
IC(Y)'
II
ct,
SC, SCR
= IC (Y) I,
Zero
If
Megat i ve
If JC(E,AQO,27)1 < IC(Y)I, then ON; otherwise OFF
NOTES.
ICCE,A~O,2n
S
then ON; otherwIse OFF
The FCHG instruction 1s identical to the Floating Compare
(FCMP) instruction except that the magnitudes of the
mantissas are co_pared instead of the algebraic values.
515 (0)
Floating Compare
FCHP
FORMAT.
Basic Instruction Format (See Figure 2-1).
C(E,AQO,27)
II
Cry)
MODIfICATIONSI
All except CI, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
= Cry),
Zero
If CCE,AQO,27)
NegatIve
If C(E,AQO,27) < Cey), then ON; otherwise OFF
NOTESI
then ON; otherwise OFF
The fCHP instruction is executed as foiloMSI
The mantissas are aligned by shifting the mantissa of
the operand with the algebralcallf smaller exponent
to the right
the number of places equal to the
difference In the tMO exponents.
The alIgned mantissas are compared and the indicators
~et
RE.VIEW DRAFT
SUBJECT TO CHANGE
October, 1975
accor~ing'v.
2-102
AL39
FLOATING POINT MISCELLANEOUS
Add to Exponent
ADE
415 (0)
FORMATI
Basic Instruction Format (See Figure 2-1).
SUHMARYI
CIE) + C(Y)O,7
MODIFICATIONSI
All except CI, SC, SCR
INDICATORSI
(Indicators not listed are not
->
CIE)
affecte~)
Zero
Set OFF
Negative
Set OFF
Exponent
Overflow
If exponent Is greater than +127, then ON; otherwise OFF
Exponent
Underf low
If exponent Is less than -128, then ON; otherwise OFF
Floating Set Zero and Negative Indicators
FSZN·
FORMATt
.. 30
(0)
Basic Instruction Format (See Figure 2-1).
Set indicators according to C(Y)
HODIFICATIONSI
All except CI, SC, SCR
INDICATORSI
(Indicators not listed are not affected)
Zero
If C(Y)8,35
NegatIve
If C(Y)8
= 0,
= 1,
then ON; otherwise OFF
then ON; otherwise OFF
.. 11 (0)
Load Exponent
LOE
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMHARYI
C(Y)O,7 -> C(E)
HODIFICATIONSI
All except CI, SC, SCR
RE.VIEW DRAFT
SUBJECT TO CHANGE
Oct ober, 1'375
2-103
AL39
FLOATING POINT MISCELLANEOUS
INDICATORS.
(Indicators nof listed are not affected)
Zero
Set'OFF
Negative
Set OFF
STE
45& (0)
Store Exponent
FORHATa
BasIc InstructIon Format (See Figure 2-1).
SUMMARY •.
C(E) -> C(Y)O,7
00 ••• 0 -> C(Y)S,17
3
3
3
HODIFICATIONSI
All except DU. DL. CI, SC, SCR
INDICATORS'
None affected
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-104
AL39
TRANSFER
-IRANSFER~
INSTRUCTIONS
113
Ca II CUsing PR& and PR1)
CALL6
FORHATa
BaSic Instruction Format (See Figure 2-1».
SUMMARY'
If CCTPR.TRR) < C(PPR.PRR) then
CeOSaR.STACK) II CCTPR.TRR) -> C(PR7.SNR)
= CCPPR.PRR)
If C(TPR.TRR)
C(PR6.SNR)
->
CCTPR.TRR)
CCPR7.RNR)
->
C(PR1.SNR)
((I)
then
=
If CCTPR.TRR)
0 then
C(SDW.P) -> C(PPR.P);
otherwise 0 -> C(PPR.P)
00 ••• 0 ->"CCPR1.WORONO)
00 ••• 0 -> C(PR1.BIINO)
C(PPR.PRR)
c'rpR.TR~)
->
C(rp~.TSR)
-> C(PPR.PSR)
C(TPR.CA)
->
C(PPR.IC)
•
"ODlflCATIONSI
All except OU, OL, CI, SC, SCR
INDICATORS'
None affected
NOTESI
If CCTPR.TRR)
Outward Call,
executed.
>
C(PPR.PRR),
occurs and
an Access Violation fault,
the CALLD Instruction Is not
If the CALLE) 1nstruct1on Is executed with the Processor In
Absojute "ode with bit 29 of the instr,Jction word eQual to
o 'and .,ithout 1ndirection through an ITP or ITS pair,
then •••
the
Appending Hode 1s entered for the address
preparation of the CALLE) operand address and is
retained if the instruction executes successfully,
and •••
the Effective Segment Number generated
for
the
SOW
•
fetch and subseQuent loaclng Into CCTPR.TSR) Is eQua'
to C(PPR.PSRJ and mav be undefined 1n Absolute Mode.
and •••
the Effective Ring Number loaded into CCTPR.1RR)
prior to the SOW fetch 1s eaual to C(PPR.PR~) (which·
Is 0 In Absolute Hode) implvln; that the Access
Violation checks tor Outward Cal' and Ba~ OutMard
Call are Ineffective and that an Access Violation,
out of Call Brackets will occur if C(SDW.R1) _ O.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-105
AL39
TRANSFER
Attempted repetitIon with
I.legal Procedure Fault.
RPT,
RPD,
or
630 (0)
Return
RET
RPl causes an
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHHARYI
C(Y)O,17 -> C(PPR.IC)
C(Y)18,31 -> C(IR)
MODIFICATIONS'
All except DU, Dl, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affectej)
=
Parity
"ask
If C(Y)Z7
1, and the Processor is in Absolute or
Privileged Hode,
then ON; other~lse JFF. This indic~tor
is not affected in the Normal or BAR modes.
Not BAR
Hode
Cannot be changed by the
~ET
instruction
=
Hultiword
If C(Y)30
1, and the Processor is in Absolute or
Instruction Privileged mode,
then ON; otherwise JFF.
This lndicator
Fault
is not affected in Nor.al or BAR modes.
Absolute
Hode
Cannot be changed by the RET Instruction
other
Indicators
If cprresp~nding bi t
A'I I
NOTESI
In elY)
Is 1, then ON; otherwise, OFF
The relation between C(Y)18,31 and the indIcators is given
in Table 2-5.
The TalJy Runout indicator reflects C(1)25 regardless of
what
address
modification is performed on the RET
instruction for ta'Iy operations.
The RET instruction may be thought of as a load Indicators
(lOI) instruction followed by a transfer to location
CeY)O,17.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO.
or
RPl causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-106
Al39
TRANSfER
· RTCD
&10 (0)
Return Control Double
fORHATI
Baste Instruction Format (See Figure 2-1).
SUMMARYI
C(Y-pairJ3,17 -> C(PPR.PSR)
ttaKi.um of
C(Y-palr)18,20; C(TPR.TRR); C(SDW.Rl) -> C(PPR.PRR)
C(Y-pair)3&,53 -> C(PPR.IC)
If C(PPR.PRR) : 0 then C(SOH.PJ -> CCPPR.P);
otherwise D -> C(PPR.P)
C(PPR.PRR) -> C(PRn.RNR) for n :
se,
MODIfICATIONSI
All except OU, DL, CI,
INDICATORSI
None af f ected
NOTES.
The hardware assumes that C(Y)17
(0, 1, •••• 7)
SCR
= 0;
~o
check is made.
If an access violation occurs when fet:hlng the SOW for
location V, the C(PPR.PSR) and C(PPR.P~R) are Aot altered.
If
the RTCO instruction Is executed with the Processor in
Absolute Mode with bit 29 of the instr~ction Mord equal to
o and withQut indirection through an ITP or ITS pair,
then •••
the
Appending Hode 15 entered for the address
preparation of the RTCD operand address and is
retained if
the instruction executes successfully,
and •••
the Effective Segment Number generated for the SOW
fetch and subsequent loading into CCTPR.TSR) is eQual
to C(PPR.PSR) and may be undefined in Absolute Hode,
and •••
the Effective Ring Number loaded Into C(TPR.TRR)
prIor to the SOW fetch is eQual to C(PPR.PRR) (Mhich
Is a in Absolute Hode)
implying that control
Is
always transferred into Ring o.
Attempted repetition with
1.legal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-107
RPT,
RPO,
or
RPL causes an
AL39
TRANSFER
Transfer On Exponent Overflow
TEO
614 . CO)
FORMATI
Basic InstructIon Format (See
SUMMARYI
If Exponent Overflow indicator ON then
C(TPR.CA)
C(TPR.TSR)
Figu~e
2-1).
C(PPR.IC)
-~
~>
C(PPR.PSR)
otherwIse. no change to CCPPR)
MOOIFICAT-IONSI
All
INDICATORS'
(Indicators not listed are not affected)
Exponent
Overf I ow
NOTESI
except OUt Ol, CI, se, SCR
Set OFF
Attempted repetitIon with
Illegal Procedure Fault.
RPT,
RPO.
or
RPl
Transfer on Exponent Underflow
TEU •
Basic Instruction Format (See Figure 2-1).
SUHHARYI
If Exponent Underflow indicator ON then
->
an
61S CO)
FORHATI
CCTPR.CA)
causes
C(PPR.IC)
CCTPR.TSR) -> e(PPR.PSRJ
otherwIse, no change to eCPPR)
MODIFICATIONSI
All except OU, Ol, CI, se, SCR
INDICATORSI
(IndIcators not 'isted are not affected)
Exponent
Underf low
NOTES'
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Set OFF
Attempted repetitIon wIth
II'ega' Procedure Fau.t.
2-108
RPT,
RPO,
or
RPl
causes
an
Al39 .
TRANSFER
Transfer on Minus
THI
EDft COl
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUMMARY.
If
Negatl~e
indicator OM then
CCTPR.CA)
C(PPR.IC)
->
CCTPR.TSR)
->
CCPPR.PSR)
otherwise, no change to C(PPR)
MODIFICATIONS.
All except DU. Dl, CIt SC, SCR
INDICATORSI
None affected
NOTES.
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD,
or
RPl
Transfer On Minus or Zero
THOZ
an
60ft (1)
FORHAT.
Basic Instruction Format ISee Figure 2-1).
SUHMARY.
If
Negatl~e
causes
or Zero in41cator ON then
CCTPR.CA)
CCTPR.TSR)
CCPPR.ICI
->
->
C(PPR.PSR)
otherwise, no change to C(PPR)
MODIFICATIONS'
All except DU, Dl. CI, SC, SCR
INDICATORSI
None af 'ected
NOTES.
Attempted repetition "lth
Illegal Procedure Fault.
RPT.
RPD,
or
Transfer on No Carry
TNC
FORHATI
Basic Instruct jon Format ISee Figure 2-1).
SUHMARYI
If Carry Indicator OFF then
C(TPR.CA)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
~>
RPl
causes
an
602 (0)
CCPPR.IC)
2-109
AL39
TRANSFER
C(TPR.TSR)
->
C(PPR.PSRa
otherwise, no change to C(PPR)
MODIFICATIONS'
All except OU, OL, CI, SC, SCR
INDICATORSI
None affected
NOTES'
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
RPL
Transfer On Not Zero
THZ
Basic Instruction Format (See Figure 2-1).
SUMMARYI
If Zero indicator OFF then
CCTPR.TSR)
an
601 (0)
FORMAT'
CCTPR.CA)
causes
C(PPR.IC)
->
->
C(PPR.PSR)
otherwise, no change to CCPPR)
MODIFICATIONS.
AI. except, OU, OL, CI, SC, SCR
INDICATORS.
None affected
NOTES'
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD,
or
Transfer On Overflow
TOV
FORHAT'
Basic Instruction Format (See Figure 2-1).
SUMMARY'
If Overflow indicator ON then
RPL
causes
an
617 (0)
CCTPR.CA) C(PPR.IC)
C(TPR.TSR)
->
CCPPR.PSR)
otherwIse, no change to CCPPR)
MODIFICAT IONS.
All except OU, OL, CIt SC, SCR
INDICATORSI
(Indicators not listed are not affectej)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-110
AL39
TRANSfER
OverfloM
NOTES'
Set OFF
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
RPL
Transfer on Plus
TPL
an
605 CO)
FORHATa
Basic Instruction ForMat (See Figure 2-1).
SUMMARya
If Negative indicator OFF, then
C(PTR.TSR)
causes
->
C(PPR.PSR)
otherwise, no change to CCPPR)
MODIFICATIONSl
All except OUt OL, CI, se, SCR
INDICATORSI
None af 'ected
.. NOTESI
Attempted repetition wIth
I.legal Procedure Fault.
RPT,
RPO,
or
RPL
FORHATl
an
605 (1)
Transfer on Plus and Nonzero
TPNZ
causes
Basic Instruction Format (See Figure 2-1).
If Negative and Zero indicators are OFF then
CCTPR.CA) -> CCPPR.IC)
eCTPR.TSR)
->
C(PPR.PSR)
otherwise, no change to CCPPR)
MODIFICATIONS.
All except OU, OL, CIt se, SCR
INDICATORS'
None affected
NOTES.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-111
RPT.
RPO.
or
RPL
causes
an
Al39
TRANSFER
Transfer Unconditionally
TRA
710 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
CCTPR.CA)
C(TPR.TSR)
C(PPR.IC)
-->
-->
C(PPR.PSR'
MODIFICATIONS'
All except DU, Ol, CI, SC, SCR
INDICATORsa
None af f ected
NOTESI
Attempted repetition wIth
I.legal Procedure Fault.
RPT,
RPO,
or
RPL
Transfer on Carry
TRC
causes
an
603 (0)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
If Carry indicator ON then
C(TPR.CA) CCPPR.IC)
C(TPR.TSR)
->
C(PPR.PSR)
otherwise, no change to e(PPR)
HODIFICATIONsa
All except OUt OL. CI, se, SCR
INDICATORS.
None af rected
NOTES'
Attempted repetition "ith
Illega' Procedure Fault.
RPT,
RPD,
or
Transfer on TruncatIon Indicator OFF
TRTF
FORHATa
Basic Instruction Format (See Figure Z-1).
SUHHARY.
If Truncation Indicator OFF then
C(TPR.CA)
C(TPR.TSR)
RPl
causes
an
601 (1)
C(PPR.IC)
->
->
C(PPR.PSR)
otherwise, no change to C(PPR)
Rl:.VIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-112
AL39
TRANSFER
ct.
HODIfICATIONSI
All except OU, Ol,
INDICATORSI
None affected
NOTES'
Attempted repetition with
Illegal Procedure Fault.
TRTN
T~ansfer
SC. SCR
RPT,
RPD,
or
RPl
on Truncation Indicator ON
Basic Instruction Format (See Figure 2-1).
SUHHARya
If Truncation Indicator ON then
->
an
600 C11
FORHATa
C(TPR.CA)
causes
C(PPR.ICI
C(TPR.TSR) -> C(PPR.PSR)
otherwise, no change to C(PPRl
HODIFICATIONSa
All except DU. Dl, CI, SC, SCR
INDICATORS'
(Indicators not listed are not affected)
T~uncatlon
NOTESI
set OFF
Attempted repetition with
Illegal Procedure fault.
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
Transfer
TSPO
TSP1
TSP2
TSP3
TSPlt
TSP5
TSPo
TSP7
and
and
and
and
and
and
and
and
Set
Set
Set
Set
Set
Set
Set
Set
RPT,
RPO,
or
PRO
Plt1
PR2
PR3
PRlt
PitS
PRo
PR7
FORMATa
Basic Instruction format (See Figure 2-1).
SUMMARYI
For n
= 0,
1 •••• ,
->
CCPRn.RNR)
C(PPR.PSR)
->
CCPRn.SNR)
00 ••• 0
RE V lEW DRAFT
SUBJECT TO CHANGE
October, 1975
->
->
causes
an
270
271
272
273
670
·671
672
613
(0)
(0)
(0)
(0)
(0)
(0)
CO)
(0)
or 7 as determIned by operation code
C(PPR.PRR)
C(PPR.IC) +1
RPl
C(PRn.HORDNO)
CCPRn.aITNO)
2-113
Al39
TRANSFER
C(TPR.CA) -> C(PPR.IC)
C(TPR.TSRJ -> C(PPR.PSR)
HODIFICATIONS'
All
INDICATORS'
None affected
NOTES'
Attempted repetition Mlth
Illegal Procedure Fault.
e~cept
DU, Dl, CI, SC, SCR
RPT,
RPD,
or
RPl
FORHAT'
Basic Instruction Format (See Figure 2-1).
SUHMARY'
C(TPR.CA) -> C(PPR.IC)
HODIFICATIONS'
.INDICATORSI
NOTES.
C(TPR.TSR)
->
All
DU, Dl, CI, SC, SCR
e~cept
an
715 (0)
Transfer and Set Slave
TSS
causes
C(PPR.PSR)
None affected (except as noted beloM)
If the TSS instructIon is executed Mlt~ the Processor nAt
in BAR mode,
the Absolute indicator is set OFF, and the
Not
BAR Hode indicator is set OF:
to signal
that
subseQuent addressing is to be done i~ the BA~ Hode. The
Base Address Register
(BAR) is used in the address
preparation of
the transfer, and the BAR will be used in
address preparation for al I SubseQuent instructions until
a fault or interrupt occurs.
If
the TSS instruct Ion is e~ecuted wi th the Not BAR Ho(;e
Indicator alreadv OFF, it functions as a Transfer
(TR~)
instruction and no indicators are chan~ed.
Attempted repetition Mith
Illegal Procedure Fau1t.
Transfer and Set
TSXn
Inde~
RPT,
RPD,
or
Register Xn
RPL causes an
70n
(I)
FORHATa
BaSic Instruction Format (See Figure 2-1).
SUHMARYI
For n = 0, 1, ••• , or 7 as determined bV operation code
C(PPR.IC) + 1 -> C(Xn)
C(TPR.CA)
REVIEW DRAFT
SUBJECT TO CHANGE
Oc tober, 1975
->
C(PPR.IC)
2-11"
AL39
TRANSfER
CtTPR.TSR)
CCPPR.PSR)
->
HODIFICATIONSI
All except DU, DL, CI. SC, SCR
I NDICA TORSI
None af fectect
NOTES'
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD,
or
RPL
Transfer on Tally Runout Indicator OFf
TTF
BaSic Instruction Format (See Figure 2-1).
SUMMARY.
If Tally Runout Indicator OFF then
C6PPR.IC)
->
C(TPR.TSR)
an
601 (0)
FORHAT.
C(TPR.CA)
causes
->
C(PPR.PSR)
otherwise, no change to C(PPR)
MODIFICATIONS:
AI' except DU, DL, CIt SC, SCR
INDICATORS'
None affected
NOTES:
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD,
or
RPL
causes
Transfer on Tally Runout Indicator ON
TTti
606 (1)
FORMAta
Basic Instruction Format (See Figure 2-1).
SUMMARY'
If Tally Runout Indicator ON then
ClTPR.CA)
ClTPR.TSRt
an
C(PPR.IC)
->
->
C(PPR.PSR)
otherwise, no change to C(PPR)
•
HODIFIC ATIONS Z
All except DU, OL, CI, SC, SCR
INDICATORS.
None affected
NOTES'
Attempted repetition with
Ilregal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-115 .
RPT,
RPD,
or
RPL
causes
an
Al39
TRANSFER
Transfer On Zero
TZE
&00
(0)
causes
an
Instruction Format (See Figure 2-1).
FORHATa
Basl~
SUMMARY:
If Zero indicator ON then
CCTPR.CA)
C(TPR.TSR)
C(PPR.IC)
->
->
C(PPR.PSR)
otherwise, no change to CCPPR)
except OU, Ol, CI,
se,
HOD IFIC AllONS:
All
INDICATORS:
None af fected
NO TESI
Attempted repetition with
IJlegal Procedure Fault.
REVIEW DR,.FT
SUBJECT TO CHANGE
October, 1915
2-11&
SCR
RPT,
RPD,
or
RPL
ALJ9
POINTER
E f fee t i ve
E f fee t i ve
E t fee t i ve
Effective
£1 fee t i ve
Ef fee t i lie
E1 fee tllle
E f fee t 1 ve
EASPO
EASPl
EASPZ
EASP3
EASP"
EASP5
EASP&
EASP7
Address
Address
Addr~ss
Address
Address
Address
Address
Address
to
to
to
to
to
to
to
to
Seglllent
Segment
Segment
Segment
Segment
Segment
Segment
Segment
DATA MOVEMENT LOAD
REGISTE~
Number
Number
Number
Number
Number
Number
Number
Numb er
of
of
of
of
of
of
of
of
PRD
PR1
PR2
PiU
PRit
PR5
PRo
PR7
FORHATI
Basic lnstruc t i on Format (See Figure 2-U.
SUMHARY'
For n = 0, 1,
CCTPR.CA)
... ,
->
INDICATORSI
None af fected
Attempted execution
Procedure Fault.
In
BAR
Attempted repetItion with
Illegal Procedure Fault.
Eff ec t 1 ve
E1 f ec tllle
Ef feet lve
Effective
Et f ec t 1 ve
Effective
Effective
E f fee t I lie
Address
Address
Address
Address
Address
Address
Address
Address
to
to
to
to
to
to
to
to
Word/Sl t
Word/Bit
Word/Sit
Word/Sl t
WordlBlt
Word/Bit
Word/Blt
Word/BIt
Mode
R?T,
causes
RPD.
Number
Number
Number
Number
Number
Number
Numl3er
Number
of
of
of
of
of
of
of
of
or
PRO
PRl
PR2
PR3
PRIt
PR5
PRo
PR7
FORHATI
Basic Instruc t Ion Format (See Figure 2-1'.
SUHHARYI
For n
= o.
1.
C(TPR.CA)
... ,
->
(1)
an
II lega I
RPL causes an
310
311
312
313
330
331
332
333
(0)
(1)
(0)
(1)
(0)
(1)
CO)
(1)
or 7 as determIned ov operation code
->
C(Prn.CHAR)
C(TPR.TBR) modulo 9
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
COJ
C(PRn.WORDNO)
C(TPR.TBR) I 9
MODIFICATIONS!
(U
C(PRn.SNR)
All except OU, OL, CI, SC, SCR
EAWPO
EAWP1
EAWP2
EAWP3
EAWP"
EAWP5
EAWP&
EAWP7
(01
(0
(0'
or 7 as determIned bv operation code
HODIFICATIONS'
~NOTESI
(OJ
(1'
311
310
313
312
331
330
333
332
->
C(PRn.8ITNO)
All except OU, DL, CI, SC, SCR
2-117
AL39
POINTER REGISTER DATA MOVEMENT LOAD
INDICATORSI
None af fected
NOTES'
Attempted execution
Procedure Fault.
BAR
Mode
Attempted repetition with
Illegal Procedure Fault.
RPT.
Pol nter
Pol nter
Pointer
Poi nt er
Poi nt er
Pointer
Poi nt er
Poi nt er
PRO
PRl
PR2
PR3
PRCt
PR5
PRE)
PR7
Effective
Effective
Effective
Effective
Effec'tive
Effective
E f fec tl ve
E f fee t i ve
EPBPO
EPBP1
EPBP2
EPBP3
EPBPCt
EPBP5
EPBPE)
EPBP7
in
FORMATI
Basic Instruction
SUMMARY.
For n
= 0,
at
at
at
at
at
at
at
at
Base
Base
Base
Base
Base
Base
ease
Base
For~at
to
to
to
to
to
to
to
to
causes
RPD.
or
an
Illegal
RPL causes an
350
351
352
353
370
:!71
372
373
(1)
(D)
(1)
(0 )
(1)
(0)
(U
CO)
(See Figure 2-1).
1 ••••• or 7 as determined ,y operation code
C(TPR.TRR)
-> C(PRn.RN~)
CCTPR.TSR)
->
C(PRn.SNR)
00 ••• 0 -> C(Prn.WORONO)
00
~>
0000
C(Prn.CHAR)
->
C(PRn.BtTNO)
HOOIFICA lIONSI
All except OU, OL. CI, SC. SCR
INDICATORS:
None affected
NOTES.
Attempted execution
Procedure Fault.
in
BAR
Attempted repetition with
Illegal Procedure Fault.
EPPO
EPPl
Effective Pointer to PRO
Effective Pointer to PR1
EPP2
EPP3
EPPCt
EPP5
EPPE)
EPP7
E f f ec t i ve
Effective
Effective
Effective
Effective
Effective
FORHATa
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Pol nter
P'ol nter
Pointer
P 01 nter
Pointer
Pointer
to
to
to
to
to
to
Mode
R?T,
causes
RPO,
or
PR2
PR3
PRIt
PR5
PRE)
PR7
an
Illegal
RPL causes an
350 (0)
351 (U
352 (0)
353 (1)
370 ( 0 )
371 (1)
372 ( II )
373 (1)
Oasic Instruction Format (See Figure 2-0.
2-118
AL39
POINTER
SUHHARY.
For n
= 0,
REGISTE~
DATA MOVEMENT LOAD
1 •••• , or 7 as determined by operation code
C(TPR.TRR) -> C(PRn.RNR)
C(TPR.TSRa -> C(PRn.SNR)
C(TPR.CA) -> C(PRn.WORONO)
C(TPR.TBR) I 9 -> C(PRn.CHAR)
C(TPR.TBR) modulo 9
->
C(PRn.BITNO)
MODIFICATIONSI
All except OU, OL, CI, SC, SCR
INDICATORS:
None af fected
NOTES.
Attempted eKecut!on
Procedure Fault.
in
BAR
Attempted repetition with
Illegal Procedure Fault.
Hade
RPT.
an
causes
RPO,
or
RPl causes an
173 CO)
load Pointer RegIsters from ITS Pairs
LPRI
.. FORHAT.
SUMMARY.
I I • ega I
BaSic Instruction Format (See Figure 2-1) •
For n
= 0,
1, ••• , 7
Hax i mum of
C(Y+Zn-pair)18,ZO; CISCH.RI); C{TPR.TRR) ->
C(PRn.RN~)
C(Y+Zn-palr)3,17 -> C(PRn.SNR)
C(Y+Zn-palr)3&,53 -> C(PRn.WORJNO)
C(Y+2n-palr)57,&Z I q -> C(Prn.CHAR)
C(Y+Zn-pair)57,&2 modulo 9 -> C(PRn.BITNO)
HODIFICATIONS'
All except CU, Ol, CI, SC, SCR
INDICATORS:
None Af fected
NOTES'
Starting at location Y, the. contents of eight word pairs
(in
ITS pair
format)
replace the contents of Pointer
Registers 0 through 1 as shown. The h3rd~are assymes that
Y14,11 = 0000 and addressing is Incre~ented accordlngly;
no check is made.
Since C(TPR.TRR) and C(SDW.Rl) are
Absolute mode, C(Y+Zn-pair)18,ZO are
in Absolute mode.
REVIEW DR ~FT
SUBJECT TO CHANGE
October, 1975
2-119
b~th
eQual to zero In
into PRn.~N~
I~aded
AL39
POINTER
RE~ISTER
DATA MOVEMENT LOAD
Attempted
execution
Procedure Fault.
in
Attempted repetition with
Illegal Procedure Fault.
BAR
Hode
causes
RPT,
RPO.
or
an
RPL
causes
Load PRn Packed
LPRPn
Illegal
an
7&n (OJ
FORHAT'
Basic
Inst~uctlon
SUMHARY.
For n
= Q.
Format (See Figure 2-1).
1 ••••• or 7 as determlned 3Y operation code
C(TPR.TRR)
->
C(PRn.RNR)
If C(Y)O.2
~ 11, then
C(Y)O.S I 9 -> C(PRn.CHAR)
C(Y)Q,S modulo 9 -> C(PRn.BITNO);
otherwise, generate Command Fault
If C(Y)&.17 = 11 ••• 1, then 111 -> C(PRn.SNR)O,2
otherwise, 000 -> C(PRn.SNR)O.2
C(Y)G.17 ->
C(PRn.SNR)3,1~
C(Y)18,35 -> C(PRn.HORDNO)
except OUt OL. CI, SC, SCR
MODIFICATIONSI
AI~
INDICATORS'
None af 'ected
NOTESI
Binary -1-s in C(Y)O,2 correspond to an i l legal
BITNO,
that
is, a bit posltion beyond t~e extent of C(Y).
Detection of these bits causes a Comma~d Fault.
Attempted execution
Procedure Fault.
in
BAR
Attempted repetition Kith
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1q75
2-120
Hode
RPT,
causes
RPO,
or
an
II legal
RPl causes an
POINTER REGISTER DATA MOVEMENT STORE
Store
Stor'e
Store
Store
Store
store
Store
Store
SPBPO
spap1
SPBPZ
spap3
spap,.
SPBP5
spap&
spap7
Segment
Segment
Se,)ment
Segment
Segment
Segment
Segment
Segment
Base Po inter
Base Pointer
~ase Pointer
Base Pointer
Base Pointer
Base Poi.nter
Base Pointer
Base Pointer
0'of
0'
of
of
of
of
of
FORMATa
BasIc Instruction Format (See Figure 2-1).
SUMMARYI
For n
= O.
1 ••••• or 7 as determined
C(PRn.SNR)
->
(1)
( 0)
250
251
252
253
&50
651
652
653
PRO
PR1
PR2
PR3
PR4
PR5
PR6
PR7
oy
(1)
(0 )
(1)
(0)
(1)
(0 )
operation code
ClY-palr)3.17
C(PRn.RNR) -> C(V-pair)18.20
000 -> CCY-palr)O.2
00 ••• 0 -> CCY-pair)21.29
43 (octal) -> C(Y-palr)30,3S
00 ••• 0 -> C(Y-pair)36,71
"'MODIFICATIONS I
All except DU. Ol, CIt
se.
SCR
INDICATORSI
None affected
NOTES'
The hardware assumes Y bit 17
Attempted execution
Procedure Fault.
In
= 0;
BAR
Attempted repetition with
Illegal Procedure Fault.
no check is made.
Mode
RPT.
causes
RPD.
or
Store Pointer Registers as ITS Pairs
SPRI
FORHATI
Basic Instruction Format (See figure 2-1).
SUHMARya
For n
= O.
an
I lie gal
RPl causes an
25,. (at
1 ••••• 1
000 -> C(Y+2n-pair)O.2
C(PRn.SNRl -> C(Y+2n-pair13.17
C(PRn.RNR) -> C(Y+2n-pair)18.20
00 ••• 0
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
->
C(Y+2n-pairlZ1.29
2-121
AL39
POINTER REGISTER DATA MOVEMENT STORE
43 (octat) -> CCY+2n-palr)30,35
C(PRn.HORONO) -> CIY+2n-pair)3&,53
000 -> C(Y+2n-palr)54,5&
9 • CCPRn.CHAR) + CCPRn.BITNO) -> CCY+2n-pair)57,&2
00 ••• 0 -> CtV+2n-pair)63,7l
MODIFICATIONSI
All except DU. Dli CI, SC. SCR
INDICATORS.
None. af f ec ted
NOTES.
Starting at location Y, the contents of Pointer Registers
o through 7 replace the contents of eight word pairs (in
ITS pair format).
The hardware assumes V bits 14 to 17
0000 and addressing is incremented accordInglv; no check
is made.
=
Attemped execution In BAR Hode causes 3n Illegal Procedure
Fault.
Attempted repetition with
Illegal Procedure Fault.
SPRID
Store
Store
Store
Store
Store
Store
Store
Store
SPRI1
SPRI2
SPRI3
SPRI4
SPRIS
SPRIG
SPRI7
PRO
PR1
PR2
PR3
PRlt
PR5
PRo
PR7
as
as
as
as
as
as
as
as
ITS
ITS
ITS
ITS
ITS
ITS
ITS
ITS
RPT,
RPD,
or
causes
Pair
Pair
PaIr
Pair
Pair
Pair
Pair
Pair
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHMARY I
For n
= 0,
RPL
1, ••• , or 7 as determined DY operation code
000 -> CCY-pair)O,2
CCPRn.SNR) -> CIY-pair)3,l7
CCPRn.RNR) -> CCY-pair)18,20
00 ••• 0 -> C(Y-pair)21,Z9
43 (octal) -> CCY-pair)30,35
C(PRn.HORONO) -> C(Y-pair)36,53
000 -> CtV-pairl54,56
9 • CCPRn.CHAR) + C(PRn.BITNO) -> C(Y-Dair)57,&2
REVIEH DRAFT
SUBJECT TO CHANGE
October, 1975
250
251
252
253
650
651
652
653
2-122
an
(0)
(1)
(()
(1)
(0)
(1)
to)
(1)
POINTER REGISTER DATA HOVEMENT STORE
HODlfICATIONSZ
All except DU. Olt CIt SC t SCR
INDICATORSI
None affected
NOTESI
The hardware assumes Y bit 17
Attempted
execution
Procedure Fau I t .
in
Attempted repetition with
Illegal Procedure Fault.
= 0;
no ::heck is made.
BAR
Hode
causes
RPT,
RPD.
or
an
RPl
causes
an
54n
(0)>
Store PRn Packed
SPRPn
fORHATa
Basic Instruction Format (See FIgure 2-1).
SUMMARYI
For n
= O.
II Ie 9a I
1 ••••• or 7 as determined oy operation code
9 • C(PRn.CHAR) +
C(PRn.BITN~)
->
C(Y)O.5
C(PRn.SNR)3.14 -> C(Y)6.17
C(PRn.WORONO) -> CIY)18.3S
MODIFICATIONS'
All except DU. Ol, CI, SC, SCR
INDICATORS:
None at fected
NOTESI
If C(PRn.SNR)O,2 are nonzero,
and C(PRn.SNR) _ 11 ••• 1.
then a Store Fault. Illegal Pointer. Mill occur and C(Y)
will not be changed.
Attempted execution
Procedure Fault.
in
BAR
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
2-123
Mode
RPT.
causes
RPO,
or
an
Illegal
RPl causes an
Al39
POINTER REGISTER ADDRESS ARITHMETIC
Add
Add
Add
Add
Add
Add
Add
Add
ADWPO
AOHPl
AOWP2
ADWP3
AOWPIt
AOWP5
AOHP6
ADHP7
FORHATI
SUHHAKYI
to
to
to
to
to
to
to
to
Word
Word
Word
Word
Word
Hord
Word
Word
Register
Register
Register
Register
Register
Register
Register
Register
of
of
of
of
of
of
of
of
PRO
PR1
PR2
PR3
PRft
PR5
PR6
PR7
050
051
052
D53
150
151
152
153
CO)
(0)
(0)
(0)
(0)
(0)
(0)
(0 )
Basic Instruction Format (See Figure 2-1).
-For n : 0, 1, •••• or 7 as determined
CeY)O,17 + C(PRn.WORONO)
00
->
->
~v
operation code
C(PRn.WJRDNOa
C(PRn.CHAR)
0000 -> C(PRn.BITNO)
MODIFICATIONS'
All except OL, CIt SC, SCR
INDICATORSI
None af fee ted
HOTESI
Attempted execution
Procedure Fault.
In
BAR
Attempted repetition with
Illegat Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-12"
Hode
RPT,
causes
RPO,
or
an
I I Ie ga'
RPL causes an
AL39
POINTER RE;ISTER HISCEllANEOUS
-P Q i
0
t ec.:B.cgl..S.J:j:C-!1.U"1..L.m~i
Effective Pointer to AQ Register
EPAQ
213 CO)
FORHATI
BaSic Instruction Format CSee Figure 2-1).
SUMHARYI
00 ••• 0
CCAQ)O.Z
->
CCTPR.TSR)
00 ••• 0
->
CCAQ)3.17
CCAQ)18,32
->
C(TPR.TRR)
->
CCAQ)33,35
CCTPR.CA) -> CCAQ)3o.53
00 ••• 0
-> CCAQ)54.o5
C(TPR.TBR)
->
CCAQ)&o,71
MODIFICATIONS'
All eKcept OUt Ol, CIt SC, SCR
INDICATORS.
(tndlcators not listed are not
Zero
NOTES'
If CCAQ)
= 0.
affecte~)
then ON; otherwise OFF
Attempted eKecution
Procedure Fault.
In
BAR
Attempted repetItion with
Illegal Procedure Fault.
Mode
RPT.
causes
RPO.
or
an
I I Ie 9a'
RPL causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-125
AL39
CALENDAR CLOCK
RCCL
633 (0)
Read Calendar CJock
FORMATI
Basic Instruction Format (See Flgure 2-1).
00 ••• 0 -> CCAQ)0.19
CCCal.endar Clock) -> CCAQ)20.71
except OUt Ol. CIt
se.
MODIFICATIONS'
All
INDICATORS'
None af f ected
NOTES'
CCTPR.CAJO,2 specify which Processor port
CI.e.. which
System Controller)
is to be used. The contents of the
clock in the designated System Cont~oller replace
the
contents of the AQ-register as Shown.
Attempted
~xecutlon
Procedure Fault.
In
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAFT
SUOJECT TO CHANGE
October. 1975
2-126
SCR
BAR
Hode
causes
PRJ,
RPD,
or
RPl
an
II legal
causes
an
AL39
DE~AIl
D·era! I
DRL
OD 2 10»
fORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY:
Causes a fault which fetches and executes, In Abso'~te
Mode,
the
instruction pair at m3in store location
C+1~(octal).
The value of C is obtained from the F4UlT
VECTOR switches on the Processor Configuration Panel.
MODIFICATIONS:
All,
INDICATORsa
None af lee ted
NOTESI
Except for the different constant used for fetching the
instruction pair from main store. the DRL Instruction Is
identical to the Haster Mode Entrv (MH~) instruction.
bu~
none affect
in~truction
Attempted repetition with
Illegal ProcedUre fault.
REVIEW DRAFT
SUBJECT TO CHANGE
Octo er, 1f~75
2-127
RPT,
execution
RPD,
or
RPL
causes
an
Al39
EXECUTE
XEC
Execute
716 (0)
FORHAT'
Basic Instruction Format (See Figure 2-1».
SUMHARY I
Fetch and
MODIFICATIONS'
All except DU. OL, CI. SC. SCR
INDICATORS'
None af fected
NOTESI
The XEC instruction itself does not affect any indicator.
However. the execution of/the instruction from Cey) may
affect indicators.
e~ectue
the Instruction in C(Y)
If the execution of the instruction from CeYt modifies
C(PPR.tC). then a transfer of control occurs; otherwise.
the next instruction to be executej is fetched from
C(PPR.IC)+l.
To execute a Repeat Double (RPD) instruction, the XEC
instruction must be in an odd location.
The instruction
pair repeated Is that instruction oair at C(PRR.IC)+l,
that Is, the instruction pair Immediately following the
XEC
instruction.
C(PPR.IC) Is adJusted during the
execution of the repeated instruction pair so that the
next Instruction fetched for execution is from the first
word following the repeated Instructio~ pair.
EIS Hultiword instructions may be executed but
the
reQuired Data Descriptors must be located immediately
after the XEC instruction, that Is, starting at CCPRR.IC)
+ 1.
C(PRR.ICt is adjusted during execution of the EIS
Hultiword instruction so that the next instruction fetched
for execution Is from the first word following the EIS
Data Descriptors.
Attempted repetition wIth
Illegal Procedure Fault.
REVIEW OR~FT
SUBJECT TO CHANGE
October. 1915
2-128
RPT.
RPD,
or
RPL causes an
AL39
EXECUTE
XED
717 (D)
Execute DGuble
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
Fetch and
MODIFICATIONS I
All except OU, oL, CI,
INDICATORSI
None affected
NOTES.
The XED instruction itsel f does nGt affect any
However,
the execution of the instruction
C(Y-pair) may affect Indicators.
exec~te
the instruction pair at CIY-paIr)
se,
SCR
indicator.
pair fro.
The even instruction from CCY-pair)
must not
after
C(Y-pairJ36,71, and must not be another XED Instruction.
If ,the execution of the instruction P3ir from CCY-pair)
alters C(PPR.IC),
then a transfer of
control occurs;
otherwise, the next instruction to be executed Is
fetChed
from ClPPR.IC)+1.
If the even instruction from ClY-pair)
alters C(PPR.IC),
then the transfer of
control
Is
effective immediately and the odd instruction is not
executed.
To execute an InstructIon pair havln~ a
Repeat Do~ble
(RPo)
instruction as the odd instruction, the XED must be
located at an odd address. The Instruction pair repeated
is that instruction pair at ClPRR.I:) + 1. that Is, the
instruction
pair
immediately
folloMing
the
XED
instruction.
C(PPR.IC)
is adJusted ~uring the execution
of
the repeated instruction pair so
the
the
next
instruction fetched
for execution is from the first Mord
follo"lng the repeated instruction pai~.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
An attempt to execute an EIS Hultiword
cause an Illegal Procedure fault.
instruction
Attempted repetition with
illeal Procedure Fault.
or
2-129
RPT,
RPo,
"111
RPL causes an
AL39
HASTER HOOE ENTRY
Haster Hode Entry
"HE
001
(0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHHARYI
Causes a fault that
fetches and executes,
In Absolute
Hode,
the
instruction pair at main store location
C+4(octal).
The value of C is obtained 'rom the FAULT
VECTOR switches on the Processor Configuration Panel.
HODIFICATIONS;
All, but none affect
INDICATORS:
None affected
NOTES'
Execution of the HHE
conditIonsl
instruction execution
instruction
implies
the
follow1ng
Ourl~g
the execution of the HHE instruction and the
two
instructions
fetched,
tne
Processor
is
temporarily in Absolute Hode inde~endent of the value
of the Absolute Hode indicator.
The Processor stays
in Absolute Hode If the Absolute Hode indicator is ON
afte~ the execution of the instructions.
The instruction at C+4 must not alter the contents of
main store location C+5, and ~ust not be an XED
instructIon.
If the contents of the instruction counter (PPR.IC)
are changed during execution of the Instruction paIr
at C+~,
the next
instruction is fetched from the
modified C(PRR.IC); otherwise, t~e next
instruction
Is fetched from C(PPR.IC)+l.
If the instruction at C+~ alters ~(PPR.IC), then this
transfer of control is effective immediately, and the
inst~uctlon at C+5 is not execute~.
Attempted
II legal
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
repetition with RPT,
Fault.
Proced~e
2-130
R~D,
or RPL causes an
HASTER HODE ENTRY
Haster Hode Entry 2
HME2
004 (0)
fORHATa
Basic Instruction Format (See Figure 2-1t.
SU"HARYI
Causes a faul t that
fetches and executes, In Absol ute
Mode,
the
instructIon pai~ at main sto~e location
C+52(octal). The value of C is obtained from the fAULT
VECTOR switches on the Processor Configuration Panel.
HODIfICATIONS:
All, but none affect Instruction executlon
INDICATORS:
None af fected
NOTESI
Attempted execution in BAR mode
Procedure, Illegal Opcode Fault.
causes
an
I I Ie ga I
Except for the dIfferent constant used for fetchlng the
instruction pair from main store, the ~ME2 instructIon is
identical to the Haster Mode Entry (MM~) instruction.
Attempted repetItion with
Illegal procedure Fault.
RPT,
RPD,
or
RPL causes an
Haster Hode Entry 3
"ME3
005 (0)
FORHATI
BasIc Instruction Format (See Figure 2-1).
SUHHARYI
Causes a fault that fetches and eKecutes, in Absolute
Mode,
the
Instruction pair at main store location
C+54(octal). The value of C is obtained from the fAULT
VECTOR switches on the Processor Configuration Panel.
MODIFICATIONS:
All, but none affect instruction eKecutlon
INDICA TORS:
None af
NOTESI
Attempted eKecutlon in BAR mode
Procedure, 11 legal Opcode Fault.
fect~1
causes
an
Illegal
Except for the dlfferent constant used for fetching the
instruction pair from main store, the ~ME3 instruction is
identical to the Haster Hode Entry (MHE) instruction.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1'375
2-131
RPT,
RPO,
or
RPL causes an
AL39
HASTER HODE ENTRY
Haster Hode Entry It
HHElt
007 (0)
FORHAT.
Basic Instruction Format (See Figure 2-1).
SUHMARYI
Causes a fault that
fetches and executes, in Absolute
Hode,
the
instruction pair at main store location
C+5&(octal). Tne value of C is obtained from the F4UlT
VECTOR switches on the Processor Configuration Panel.
MODIFICATIONSI
All, but none affect instruction execution
INDICATORS:
None af fected
NOTES'
Attempted. execution in BAR mode
Procedure, II legal Opcode Fault.
causes
an
III egal
Except for the different constant used for fetching tne
instruction pair from main store, the MME4 instruction is
Identcal to the Haster Hode Entry (MHE) instruction.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
RPL causes an
REVIEW DRAFT
SUBJECT TO CHANGE
Oct 0 b er , 1975
2-132
AL39
NO OP ER.A lION
Nap
011 (0)
No Operation
FaRHAT'
Basic Instruction Format (See Figure 2-1).
SUMMARY'
No operation takes place
MODIfICATIONS I
All
INDICATORSZ
None affected (except as noted beloM)
NOTES'
No operation
takes place but address preparation is
performed according to the specifled modifier, if any.
If
modification other
than OU or Dl is used, tne effective
addresses generated may cause Store Fa~lts.
The use of Indlrect and Tallv modifiers causes chanses In
the
address and tally fields of the referenced Indirect
Words and the lally Runout indicator may be set ON as a
result.
Attempted repetition Mith
Illegal Procedure Fault.
RPT,
RPD,
or
012 (0)
Pulse One
PULSl
RPL causes an
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
No operation takes place
MODIFICATIONSI
All
INDICATORSZ
None affected (except as noted bel OM'
NOTESz
The PUlSl instruction is identIcal
to the No Operation
(NOP)
instruction except that
it C3uses certain uniQue
synchronizing signals to appear in tne Processor
logic
circuitry.
Attempted repetItion Mlth
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-133
RPT,. RPO.
or
RPL causes an
Al39
NO OPERATION
013 (0)
Pulse Two
PULS2
FORMATS
Basic Instruction Format (See Figure 2-1).
SUMMARYI
No operation takes place
MODIFICATIONSI
All
INDICATORS.
None affected (except as
NOTES.
The PULS2 Instruction is identical to the No Operation
(NOP)
Instruction except that it Cluses certain unique
synchronIzing signals to appear In t~e Processor
logic
cIrcuitry.
~oted
Attempted repetition with
Illega' ~rocedure Fault.
REVIEW DR~FT
SUBJECT TO CHANGE
October, 1975
2-134
below)
RPT,
RPO,
or
RPL causes an
REPEAT
RPD
5&0 (0)
Repeat Double
FORHATa
a
I
I
o
0 1 1
1 1
22223
3
-LJ-.3.J_l
---1--a.
-LLa.-LO
2
0
-D.
TALLY
I
t
a I I I
tAa31Cl Term. Cond. 1
I I I I
I
7
8 1 1 1 1
Figure 2-9
I
(5&0)8
I
I
I
1011101
I
DEL TA
I
I
--L.1 I I
911 1
&
Repeat Double (RPD) Instruction Word Format
SUMMARYI
Execute the pair of instructions at C(PPR.IC)+l either
a
specified number of times or until a s~ecified terminatIon
condition Is met.
MODIFICATIONSI
None
INDICATORS'
(Indicators not listed are not affected)
=0
at terminatIon. then ON; otherwise. OFF
Tally
Runout
If CeXO)O,7
All other
Indicators
None affected.
However.
the execution of
instructions may affect indicators.
NOTEsa
the
repeated
The RPD instruction must be stored in ~n odd main store
location
except
when accessed vIa the XEC or XED
instructions, in which case the XEC or XED instructIon
must itself be in an odd main store location.
Both repeated instructions must use R or RI modifiers and
only Xl. X2, •••• X7 are permittej. For the purposes of
this description, the even repeated i~struction shall use
X-even and the odd repeated Instr~ctio~ shall
use. X-odd.
X-even and X-odd may be the same register.
If
C = 1,
then C(RPO instruction word)O.11 -> C(XO);
otherwise, C(XO) unchanged prior to executIon.
The
termination condltion and
tallt
fIelds of
C(XO)
control
the repetit Ion of
the instruction paIr.
An
initial tally of zero is interpreted ai 25&.
The repetition cycle consists of the fol lowing stepsl
R[VIEW DRAFT
SUBJECT TO CHANGE
October. 1915
a.
Execute the pair of repeated
b.
C(XO)O.7 - 1 -> C(XO)O.7
Modify C(X-even) and C(X-odd) as jescrlbed below.
c.
If C(XO)O,7
0. then set Tally Runout
and terminate.
=
2-135
inst~uctlons
indicator
ON
AL39
REPEAT
d.
If a terminate condition has been met. then set Tallv
Runout indicator OfF and terminate.
e.
Go to step a.
If a Processor Fault occurs during the exection of the
instruction pair. the repetition 'oop is terminated and
control
passes to the Fault Trap accoroing to the
conditions for the Processor Fault. C(XO), C(X-even), and
C(X-odd) are not updated for the repetition cvcle in ~hich
the fault occurs.
Note· in partic~lar that
certain
Processor Faults occurring during e~ecution of the even
instruction preclude the e~ecutlon of the odd instruction
for the faulting repetition cyc'e.
.
EIS
instructions cannot be ~epeated. All other
be repeated except
as
noted
for
individual instructions or those that •••
Multi~ord
~nstructions
~av
Explicitly alter C(XO)
The effective address, Y. of the operand (in the case of R
modification)
or indirect ~ord (i~ the case of RI
modification) is determined as fol10~sl
...
for the first execution of the
repeate~
C(C(PPR.IC)+1)O.17
+ C(X-even)
C(X-evenJ
C(CIPPR.IC)+Z)O.17 + C(X-odd) -.
CIX-odd)
instruction
->
Y;
pair
V-even
->
V-odd
->
V-odd;
For all successive executions of the -epeated instruction
pair •••
=
if CeXO)8
1. then CIX-even) + Delta -> V-even,
V-even -> C(X-even); other~ise, CIX-even) -> V-even
=
if CIXO)9
1, then C(X-odd) + Delta -> V-odd,
C(X-Odd); otherwise, C(X-odd) -> V-odd
V-odd
->
C(XO)8.9 correspond to Control BIts A and B. respectively,
of the RPD instruction.
In
the case of RI modification. only one indirect
reference is made per repeated execution. The tag field
of the indirect word is not interpreted. The indirect
word is treated as though it had R modification with R
N.
=
The bit configuration in C(XO)11.17 defines the conditions
for
which
~he
repetition loop is t~rminated.
The
terminate conditions are examined at the completion of
e~ecutlon
of the odd instruction.
If more than one
condition is specified. the repeat terlinates if any of
the specified conditlons are met.
Slt 17
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
=0
Ignore all overflo~s. Do not set
Indicator; inhibit Overflo~ Fault.
Z-13&
Overflo~
AL39
REPEAT
Bit 17
=1
If Overflow Hask indicat~r is ON. then set
Over flo M
indicator
and
terllina te;
otherwise. cause an Overflow Fault.
Bit 16
=1
Terminate if Carry indicator OFF.
Bit 15 = 1
Terminate if Carry indicator ON.
Bit 14 = 1
Terminate if Negative indicator OFF.
Bi t 13
81t 12
=1
=1
Bit 11 = 1
Terminate if Negative
in~icator
O~.
Terminate if Zero indicator OFF.
Terminate If Zero indicator ON.
At the tlme of terminationS
ceXO)O.7 contaIn the Tally Resilue;
number of repeats remaini ng un t 11
would have occurred.
that
Is.
the
a lallv Runout
is
If the RPO instruction
interrupted eby anv fault)
before ter.inatlon, the Tally Runout indicator is
OFF.
CeX-even) and
CeX-odd)
contain
the
effective
addresses of the next operands or indirect words that
would have been used had the repetition loop not
terminated.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-137
RPl,
RPO.
or
RPL
causes
an
AL39
REPEAT
Repeat link
RPl
500
(0)
FORHATa
Z
II
I
J
a 3..Jl_l
I
10
TALLY
I
I
8
I
----L8
3
~~~9-LO__•______45_
I
I
OICI Term. Cond. I
L.L
--1.
7
Z 1 1
Figure 2-10
Z Z 2 Z 3
1 1
0 0 0 1 1
0
(500)8
_____________
I
I I I I
10111010 0 0 0 0 O.
--1-1~1~;
__________
9 111
~1
6
Repeat link (RPl) Instruction Word Format
SUMMARY'
Execute the instruction at C(p~R.Ie)+l either a specified
number of times or until a specified termination condition
is lIet.
MODIFICATIONSI
None
INDICATORS:
(Indicators not listed are not
affecte~)
=
=0
Runout
If CeXO)O,l
0 or link address eeY)
then ON; otherwise OFF
All other
Indicators
None affecte~. HONever, the executIon of
instruction may affect indicators.
Tallv
NOTESI
at
termination,
the
repeated
The repeated instruction must use an R modifier and only
Xl, XZ, ••• , X7 are permitted. For the purposes of thiS
description, the repeated instruction shal I use Xn.
=
If C
1, then
otherwise, C(XD)
ClRPL
instruction
Nord)O,17
prior to execution.
->
C(XO);
unchan~ed
The termination concition and tall, fields of C(XO)
control the repetition of the instruction.
An inItIal
tally of zero is interpreted as 256.
The repetItion cycle consists of the following stepsi
REVIEW DRltFT
SUBJECT TO CHANGE
October, 1975
a.
Execute the repeated instruction
b.
C(XO)O,7 - 1 -> C(XOIO,7
Hodify CeXn) as descrlbed bel OM.
c.
If C(XO)O,7 = 0 or e(Y)O,ll
0,
Runout indicator ON and terminate.
d.
If a
e.
Go to step a.
=
then
set
Tally
ter~inate condition has been met, then set Tally
Runout indicator OFF and terminate.
2-138
AL39
REPEAT
If a Processor Fault occurs dur-i"g the exection of the
instruction, the repetition 10~~ is te~mlnated and control
passes to the Faul t Trap a::;clt,"ding to' the condi t ions for
the Processor fault. ceXO) and C(Xn) are not updated for
the repetition cyc'~ in .hlch the fault occurs.
EIS Hultiw ord instructions cannot be repeated.
instructions
may
be
repeated ex:ept as
Inaividual instr~ctlons or those that •••
A II
noted
other
for
Explicitlv alter C(XO)
ExplicItlv alter the 1ink address, C(YlO,17
The effective address, Y, of the
is determined
opera~d
f 01 1 OlliS :
For the first execution of the repeated instruction
CeC(PPR.IC)+1)O,17 + C(Xn)
for
->
Y; Y
all successive executions of the
C eXn) -> Y
if CeYtO,17 # 0, then C(Y)O,17
no Change to CeXn)
->
->
as
...
C(Xn)
~epeated
instructIon
C(Xn);
otherwise,
C(Y)O,17 Is known as the link address and is the effective
address of the next entry in a threaded list of operands
to be referenced by the repeated instr~ction.
The operand data is formed as
where p is 35 for single precision
double precision operands.
ope~ands
and
71
for
The bit configuration in C(XO)11,17 a~d the link address,
C(YlO,17, define the conditions for which the repetition
loop is terminated. The terminate conditions are examined
at the completion of execution of the Inst~uction. If
more than one condition is
specified,
the
repeat
terminates if any of the specified conditions are·met.
C(Y)O,17 =
°
Set Tally Runout indicator ON and terminate.
Bit 17
=0
Ignore all overftows. 00 not set
Indicator; inhibit Overflo. fault.
17
=1
If Overflow Mask
B1 t
indicat~r
is ON,
Overflow
then
set
terllinate;
and
Overf low
indicator
otherMise, cause an Overflow fault.
Bit 1& = 1
Bit 15
=1
Bit 14 = 1
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Terminate if Carrv indicator OfF.
Terminate 1 f Carry indicator ON.
Terminate if Negat i ve injlcator Off.
2-13'9
AL39
REPEAT
Bit 13 :: 1
Terminate if Negative
Bit 12 :: 1
Terminate if Zero indIcator OFF.
8i t
Terminate if Zero indicator ON.
11 :: 1
ln~lcator
ON.
At the time of terminationl
C(XO)O,7 contain the Tallv Residue;
number of repeats remaining u~til
"ould have occurred.
that i 5, the
a Tal IV Runout
If the RPL instruction is interrupted (bv any fault)
before termination, the Tallv Runout indicator Is
OFF.
C(Xn) contain the last link address, that is, the
effective address of the list word containing the
last operand data and the Da¥l li~k address.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-1lt 0
RPT,
RPO,
or
RPl
causes
an
REPEAT
Repeat
RPT
520
(0)>
FORHATa
o
0
0
o
1 1
1 1
- L -_ _ _ -LA.-3_lL.1_____--L8
J
I
I
10
TALLY
I
I
8
I
3
~
J I J I
a011101
I
I
(520)8
OICI Term. Cond. I
I I
----L
7
211
Figure 2-11
2 2 2 Z l
_LLa.-L1J.
DELTA
I
I I _LJ
9 1 1 1
Repeat (RPT) Instruction Word
,
I
6
Fo~mat
SUMMARY"
Execute the instruction at C(PPR.ICt+l either a specified
number of times or until a specified termination condition
1 s me t.
MODIFICATIONS I
None
INDICATORsa
(Indicators not _,sted are not affectej)
= D at
Tally
Runout
If C(XO)O,7
AI. other
Non. affected. However, the execution of
Instruction may affect indicators.
Indicators
NOTES'
termination, then
O~;
otherwIse, OFF
the
repeated
The repeated instruction must use an R or RI modifier and
only Xl, X2, ••• , X7 are permitted. For the purposes of
thiS description, the repeated instruction shall use Xn.
=
If
C
1.
then C(RPT instructIon word)O,17
otherwise. C(XO) unchanged prior to execution.
->
C(XO);
The termination condition and tallt fields of C(XO)
control the repetition of the instruction pair.
An
Initial tally of zero is interpreted a~ 256.
The repetition cycle consists of the following stepsa
REVIEW DRlIFT
SUBJECT TO CHANGE
October. 1q75
a.
Exec~te
the repeated instruction
b.
C(XO)O,7 - 1 -> CeXO)O,7
Modify C(Xn) as described below
c.
If C~XO)O,7 = 0, then set Tally
and term inate
d.
If a terminate condition has been met, then set Tally
Runout indicator OFF and terminate
e.
Go to step a
2-1" 1
R~nout
indicator
ON
AL39
R[PEAT
If a Processor Fault occurs during the exection of the
instruction, the repetition loop is te~minated and control
passes to the Fault Trap according to the conditions for
the. Processor Fau It. C (XO) and C( Xn) are not updated for
the repetition cycle In which the fault occurs.
EIS Hultiword inst~uctions cannot be repeated.
instructions
may
be
repeated ex:ept as
individual instructions or those that •••
All other
noted for
Explicitly alter C(XO)
Explicitlv alter C(PPR.IC)+2
The effectIve address, Y, of the opera~d (in the case of R
modification) or indirect word Un the case of
RI
modification) is determined as foilowsl
For the first execution of the repeatej instruction
C(C(PPR.IC)+I)O,17 + C(Xn)
...
For
->
V; Y
all successive executions of the
if C(XOl8 : 1, then C(Xn) + Delta
otherwise, C(Xn) -> V
C(XO)8
corresponds
instruction.
to
Control
->
C(Xn)
~epeated
->
Bit
...
instruction
V, Y
->
A of
C(Xn);
the
RPO
In the case of RI modificatIon. only one
indirect
reference Is made per repeated execution. The tag fIeld
of the indirect word is not interpreted.
The indIrect
word is treated as though it had R modification with R ~
N.
The bit confl~uratlon in C(XO)II.11 defines the conditions
for which the repetItion loop is
terminated.
The
terminate conditions are examine~ at the completion of
execution of the instruction. If more than one condition
Is
specified, the repeat terminates if any of the
specified conditions are met.
Bit 17
=0
Ignore all overflows. Do not set
Indicator; inhibit Overflow Fault.
Overflow
81t 11 : 1
If Overflow Hask indicat~r is ON, then set
OverfJoM
indicator
and
terminate;
otherwise, cause an Overflow Fault.
Bit 16 = 1
Terminate if Carry indicator OFF.
Bit 15
Blt 14
=1
=1
Bit 13
:
Bit 12
=1
=1
Blt 11
1
Terminate if Carry indicator ON.
Termi.nate if Negat ive in:iicator OFF.
Terlllinate if Negat ive indicator ON.
Terminate if Zero indicator OFF.
Terminate if Zero indicator ON.
REVIEW DRAFT
SUBJECT to CHANGE
October, 1975
2-1"2
AL39
REPEAT
At the time of termination'
C(XO)O,7 contain the Tallv Resl::tue;
number of repeat~ remaining unt i I
would have occurred.
that is, the
a Ta I I y Run 0 u t
If the RPT instruction Is interru3ted (by any fault)
before termination, the Tallv Runout indicator is
OFF.
C(Xn) contain the effective address of the next
operand or indirect wo~d that would have been used
had the repetition loop not terminated.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
RPl
causes
an
RE.VIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-143
AL39
RING ALARM REGISTER
Stor-e Ring Alar-II
SRA
75 .. (1)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
00 ••• 0 -> CCY)O.32
C(RALR)
->
CCY)33,35
MODIFICATIONSI
All except OU, DL, CIt
INDICATORS'
None a11ected
NOTES:
Attempted execution
Procedure Fault.
se,
In
SCR
BAR
Attempted repetition wIth
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Mode
RPT,
causes
RPO,
or
an
Illegal
RPL causes an
AL39
STORE 8.SE ADDRESS REGISTER
SBAR
Store Base
Add~ess
Basic Instruction For.at
SUMMARY'
CIBAR) -> CCY)O.17
MODIFICATIONS'
All
INDICATORSI
None affected
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
exc.~t
SSD CD)
Register
(588
Figure 2-1 ••
DU. OL. CI, SC, and SCR
2-1"5
Al3<}
FORHATI
SUHMARYI
"11C(~~ I ,(. C(,~,~
)i.~~. bt,~, "',,'':. ":.
->
It-b,i t Quotient plus rellainder
""J,':
l(;,r::J.:)';(
E.
! 5 fe,
Shift C(Q) left six positions
remainder
->
CeA)
MODIFICATIONSI
AIJ except
CI, SC, SCR
INDICATORS.
(Indicators not listed are not affected)
Zero
If C(A) : 0, then ON
Negative
If C(A)O
NOTES.
=1
before execution, then ON; otherwise OFF
The BCD instruction carries out one step in an ~a,gorjthll
for the conversion of a binary n~mber to a string of
Binary-Coded-Decimal (SOC) dIgIts. The algorithm reQuires
the repeated short division of the bin3ry number or last
remainder by a set of constants Cli) = 8··j x 10··(n-l)
for 1 : 1, 2 •••• , n with n being defined byl
The values in the table that follows are the conversion
constants to be used with the Be) instructIon. Each
vertical column represents the set of constants to be used
depending on the initial value of the 31nary number to be
converted.
The instruction is executed once per digIt
~hile
traversing the appropriate C31umn from top to
bottom.
An alternate use of the table for conversion involves the
use of the constants in the row
corresponding
to
conversion step 1. If, after each exe:ution, the contents
of
the accumulator are shifted ri~ht 3 positions, the
constants In the first row, starting at the appropriate
column,
right.
may be used while traversing the row from left to
Because there is a limit on range, a ful I 3& bit word
cannot be converted. The largest bi~ary number that may
be converted correctly is 2·.33 -1 yi21ding ten decimal
digits.
Attempted
Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
Oc:tober, 1975
repetition with RPL
2-146
ca~ses
3n Illegal Proce1ure
AL39
TRANSL ATION
,,
,,
For 10··'n-1) <= I C ( AR) I <= 10··n - 1 a'\d n =
1Jl
~
A
1
8000000000
&'+00000000
5120000000
409&000000
327£>800000
2&214'+0000
2097152000
1&77721&00
1342177280
1073741824
800000000
&'+0000000
512000000
409£>00000
327£>80000
2&2144000
209715200
i&77721&0
134217728
80000000
&'+000000
51200000
409&0000
327&8000
2&21'+'+00
20971520
1&77721&
6000000
&'+OOO()O
5120000
409&000
327&800
2&21440
2097152
• 2-
fl
...
~
!t
L
1
1=
1
2
3
..
5
6
7
8
9
10
800000
&40000
512000
'+ 096 0 0
327&80
2&21'+4
80000 8000 600 80 8
6'+000 6'+00 6'+0 64
51Z00 5120 512
40~6Q 40436
327&8
Grav to Binary
GTa
774 (0)
FORMATI
Basic Instruction Format (See Figure 2-1).
SUMMARYJ
CeA) converted from Gray Code to a 36 bIt binary number
MODIFICATIONSI
None
INDICATORS.
(Indicators not listed are not
= O. then ON; otherwise OFF
C(A)O = 1. then ON; otherwise OFF
Zero
If CeA)
Negative
If
NOTESI
affecte~)
This converSion is defined br the
foll~wing
atgorith.:
ClA)O -> C(A)O
CIA)(l)
e
CeA) Ci-1) -> CeA) ei)
fo~
i
= 1.
2 ••••• 3S
Attempted repetition with RPL causes a'\ 11 legal Procedure Fault.
REVIEW ORAf T
SUBJECT TO CHANGE
October. 1975
2-147
AL343
PRIVILEGED - REGISTER LOAD
230 (0)
load Base Address Register
LSAR
FORHATa
Basic Instruction Format ISee Figure 2-1).
SUHHARYa
C(V)O,lT
MODIFICATIONS
All
INDICATORS'
None af lected
NOTES:
Attempted repetition with
Illegal Procedure Fault.
->
CISAR)
except CI, SC, SCR
Attemp~ed
RPT,
RPD,
or
RPl
causes
an
execution in BAR Hode causes a Illegal Procedure
Fault.
load Central Processor Register
lCPR
FORHAT.
67 .. CO)
BaSic Instruction Format (See Figure 2-1).
Load selected register as noted
f10DIfiCATIONS'
None. The ins truct j on
sel ec tion as follows.
~l
TAG
f lei d
is
used
for
reg is ter
Jla!.a-iLOSl Reg 1 s t m:.1U
02
CCy) -> C(Cache Hode Registe"')O,35
0 ..
CIY) -> C(Hode Reglster)O,J5
03
CICU,
00 ••• 0 ->
Reg ister) 0.71
OU,
DU,
and
APU
History
07
11 ••• 1 -> C(CU,
Reglster)O,71
OU,
OU,
and
APU
History
INDICATORS:
None af fee ted
NOTES'
See Section IV, Program
Accessible
Registers,
descriptions and use of the various re~lsters.
for
For TAG values 03 and 07, the Histort Register loaded Is
selected Dy the current value of a Cyclic Counter for each
Uni t. AII four eve I.i. c Counters are advancej by one count
RE.VIEH DRAFT
SUBJECT TO CHANGE
October, 1975
2-1" S
AL39
PRIVILEGED - REGISTER LOAD
for each executIon of the instruction.
Use of TAG values other than those defined above causes an
Illegal Procedure Fault.
Attempted execution In Normal or BAR M)de causes a Illegal
Procedure Fault.
Attempted repetItIon with
IIJegal Procedure Fault.
RPT,
RPO,
or
RPL causes an
Load,Descriptor Segment Base Register
LDBR
232 (0)
FORMATa
Basic InstructIon Format (See Figure 2-1 ••
SUMMARY.
If SOWAH is enabled, then
o
-> CtSOWAH(i).FULL)
for i = O. 1, ••• , 15
ei) -> C(SOWAHCi).USE) for 1
= 0,
1, •••• 15
If PTWAH °is enabled, then
Q -> C(PTWAH(i).FULl)
(i» -> C (PTWAHCl). USE)
n.
for 1 =
for i
1, •••• 15
= O.
1, ••• , 15
CCY-palr)O.23 -> C(DSBR.ADDR)
CCY-palr)37,50 -> CeOSBR.BOUND)
C(Y-pair,,5 -> C(OSBR.U)
eIY-pair)bO.71 -> CeOSBR.STACK)
MODIFICATIONS:
All except OUt DL. CI, SC, and SCR
INDICATORS:
None af fected
NOTES.
The hardware assumes Y17
= 0;
no check is made.
The Associative Hemorles are
reset) if they are enabled.
See
cleared
(FULL
indicators
Section IV, Program Accessible Registers, and Section
Pagi~g,
for description
V. AddreSSing -- Segmentation and
and use. respectively. of the SDNAH, PfWAH, and OSBR.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Attempted execution In
Illegal Procedure Fault.
Normal
or
3AR
Attempted repetition wi th
Illegal Procedure Fault.
RPT,
RPO.
or
2-1'+9
Hode
RPL
causes an
causes
an
AL39
PRIVILEGED - REGISTER LOAD
&37 (0)
load Timer' Register
LOT
FORHATa
Basic Instr'uction FOr'mat (See Flgur'e 2-1).
SUMHARYI
C{Y)O.26
MODIFICATIONS&
All except CIt SC, SCR
INDICATORSa
None Affected
NOTEsa
Attempted execution in
Pr'oc e dUr'e F au It.
->
CCTR)
or BAR Hode causes a Illegal
NOr'~al
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD.
or
RPL causes an
Load Page Table Pointers
LPTP
.
257
FORMATI
Basic Instr'uction Format (See Figure 2-1).
SUHHARYI
For 1
(1)
= D. i •••• , 1S
m = CCPTWAH(i).USE)
C(Y+m)O.1~
->
CCPTWAM(m).POINTER)
C(Y+m)i5.26
->
C(Y+m)Z7
C(PTWAHCm).F)
->
CCPTWAH(m).PAGE)
se.
MOOIFICATIONSI
All except OUt Ol. CI,
INDICATORS.
None affected
NOTES.
The har'dware assumes Y14.17
SCR
= 0000;
no check is made.
The Associative Hemor'V is ignored (for:ed to
during Addr'ess Prepar'ation.
-no
match")
See Section IV, Program Accessible Registers, and Section
V, Addressing -- Segmentation and Paging, for descr'lption
and use, respective IV. of the PTWAH.
Attempted execution In
I)legal Pr'ocedure Fault.
Attempted repetltion with
legal Pr'oce1ure Fault.
Normal
Or'
3AR
RPT,
RPO,
Or'
Hude
RPL
causes an
causes
an
II
REVIEW DRlIFT
SUBJECT TO CHANGE
October', 1975
2-150
AL3·q
PRIVIl~GEO
lPTR
loa~
- REGISTER lOAD
173
Page TaDle Registers
FORMATa
Basic Instruction Format (See Figure 2-1).
SUHMARYI
For i :: 0, 1, ••• , 15
(1)
m :: C(PTWAH(il.USE)
C(Y+m)D,17 -> C(PTWAH(m).AOOR)
C(Y+m)29 ->
C(PTWA~(m).M)
HODIFICATIONSI
All except OU, Ol, CI, SC, SCR
INDICATORS:
None affected
NOTES.
The
hard~are
assumes Y14,17 :: OOOD; no check is made.
The
Associative Memorv is ignored (forced to "no match")
during Add~ess Preoaration.
See Section IV, Program Accessible Registers, and Section
V,
AddreSSing -- Segmentation and Paging, for descriptIon
and use, respective Iv, of the PTWAH.
Attempted execution
In Normal
Illegal Procedure Fault.
Attemoted repetition with
Illegal Procedure Fault.
RPT.
or
BlR
RPD,
Hode
or
774 (1)
FORMATa
BaSic Instruction Format (See Figure 2-11.
SUMMARY a
C(Y)33,35 -> CCRAlR)
HODIFICATIONS1
AI) except OU, Ol, CI, SC, SCR
INDICATORSI
None affected
NOTESI
Attempted execution
in Normal
Illegal Procedure Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJ[CT TO CHANGE
October, 1975
2-151
an
RPL causes an
Load Ring AJar~ Register
LRA
causes
RPT.
o~
BAR
RPO,
Hode
or
causes
an
RPl causes an
IlL39
PRIVILEGED - REGISTER LOAD
lSDP
Load Segment Descriptor
257 (0)
Polnte~s
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHKARY I
For 1 = 0, 1, •••• 15
• = CCSOWAH(i).USE)
CCY+m)O,14 -> C(SDWAHCm).POINTER)
CCY+m)17
->
C(SDWAK(m).P)
MODIFICATIONSI
All except OU, DL, CI, SC, SCR
INDICATORSI
None affected
NOTESI
The
hard~are
assumes Y14,17
= 0000;
no check is made.
The Associative Hemory is ignored ,for:ed to
during Address PreparatIon.
-no
match")
SectIon IV, Program Accessible Re~lsters. and Section
V. Addressing -- Segmentation and Paging, for description
See
and use, respectively, of the SOWA".
Attempted executIon In
Illegal Procedure Fault.
Attempted repetition wIth
Illegal Procedure Fault.
Nor.al
or
RPT,
RPO,
~AR
or
"ode
RPL
causes an
causes
an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-152
AL3CJ
PRIVILEGED - REGISTER LOAD
Load Segment DescriPtor Registers
LSDR
232 (1)
FORHAT.
BaSic Instruction Format (See Figure 2-1).
SUMMARY.
For i = 0, 1, ••• , 15
m
= C(SDWAH(l).USE)
C~Y+2m)O,23
->
C(SDWAMlm).AORI
C(Y+2m)2~,32
->
C(SDWAM(m).R1, R2,
C(Y+2m)37,50
->
CCSDWAHCm).BOUND)
~(Y+2m)52,57
->
CCSDWAHCm).R, E, W, P, U, G, CI
CCY+2mJ58,71
->
CCSDWAM(m).CL)
MODIFICATIONSI
All except DU, OL, CI,
INDICATORS.
None Affected
.. NOTES.
The
hard~are
assumes
se,
~3)
SCR
Y1~,17
= 0000; no check Is .ade.
The Associative Memory is ignored
during Address Preparation.
(f~rced
to -no-match-)
See Section IV, Program Accessible Registers, and Section
V, AddreSSing -- Segmentation and Paging for descriptIon
and use, respectively, of the SOWAH.
Attempted executIon in Normal
Illega' Procedure Fault.
Attempted repetition ~ith
Illegal Procedure Fault.
Reu
RPT,
or
BAR
RPO,
"ode
or
causes
RPL causes an
Restore Control UnIt
FORHATa
an
613 (OJ
BaSic Instruction Format (See Figure 2-1).
•
SUMHARYI
C(Y-block8) words 0 to 7
MODIFICATIONSI
All except DU, DL, CI, SC, SCR
INDICAtORSI
None affected
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-153
->
CCControl Jnit Data'
AL39
PRIVILEGED - REGISTER LOAD
NOTES,
See Section IV,
Pro~ram
Accesible
Registers,
description and use of Control Unit Data.
=
The hardware assumes ViS,17
000 and
incremented accordingly; no check is m3de.
Attempted execution in
Illegal Procedure Fault
Normal
Attempted repetition ~ith
Illegal Procedure Fault.
RPT.
or
BAR
RPD,
addressing is
Hode
or
for
causes
an
RPL causes an
REVIEW DR~T
SUBJECT TO CHANGE
October. 1975
2-15~
AL39
PRIV[LE~EO
Sto~e
SCPR
- REGISTER STORE
452
Central Processor Register
FORMATI
Basic Instruction Format CSee Figure 2-1).
SUMMARYI
Store selected register as noted
MODIFICATIONSI
None. The instruction TAG
selection as follows.
field
Is
used
for
register
00
ClAPU Historv Register) -> CCY-pair)
01
CCFauit Register) -> C(Y-pai~)O,35
00 ••• 0 -> C(Y-pair)3&,71
06
CC"ode Register) -> CCY-palr.O,35
C(Cache Hode Regiser' -> CIY-palr)36 t 71
20
C(CU History
40
C(OU History Register) -> Cet-pair)
60
C(OU History Register) -> Ctt-pair)
Reglst~r)
(0)
-> CIY-pair)
INDICATORSI
None affected
NOTESI
See Section IV, Program
Accessible
Registers,
description and use of the various registers.
for
For TAG values 00, 20. 40, and 60, the Historv Register
stored is selected by the current ~alue of a Cyclic
Counter for each Unit. The individual CycliC Counters are
advanced
b,
one
count for each execution of
the
instruction.
The use of TAG values other than
causes an Illegal Procedure Fault.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
t,ose
Attempted execution in
Illegal Procedure Fault.
Normal
or
BAR
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD,
or
2-155
defined
Mode
RPl
above
causes an
causes
an
AL39
PRIVILEGED - REGISTER STORE
scu
651 (0)
Store Control unit
FORHAT.
Basic Instruction Format (See FIgure 2-1).
SUMMARY'
C(Control Unit Data) -> ClY-blockS)
MODIFICATIONS'
All except DU, OL, CI, SC. SCR
INDICATORS:
None af f ec ted
NOTEsa
See Section IV, Program
Accessible
RegIsters,
description and use of Control unit Data.
"o~ds
0 to 7
for
The
SCU· instruction safe-sto~es ::ontrol information
reQuired to service a Processor fault.
The Control Unit
Data is not, in general, valid at any tIme except when
safe-stored by the first instruction of a fault/interrupt
vector.
=
The hardware assumes Y15,17
000
and
Incremented accordingly; no check is made.
Attempted executIon In Normal
Illegal Procedure Fault.
Attempted repetition with
Illegal Procedure Fault.
RE. V lEW DRAF T
SUBJECT TO CHANGE
October, 1975
2-15&
RPT,
or
84R
RPD.
addressing is
Hode
or
causes
an
RPL causes an
- REGISTER STORE
PRIVILE~EO
15,.
Store Descriptor Segment Base Register
SOBR
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARYI
CCoSBR.AOoR)
00 ••• 0
->
->
CIY-pairJO,23
->
CeY-palr)2,.,J&
ceosaR.BOUNo)
0000
(0)
->
CIY-pair)37.50
CeY-pair)51,54
C(OSaR.U)
->
C(Y-pair)55
000 -> CeY-pair)S&,59
ceos8R.STACK.
->
C(Y-pair)&O,71
MODIfICATIONSI
All except OU, ol, CI, SC, SCR
INDICATORSI
None
NOTEsa
The hardware assumes Y 17
af fected
= 0;
no
chec~
Is made.
C(OSBR) is unchanged.
See Section IV, Program Accessib1e Registers, and Section
V, AddressIng -- Segmentation and Paging for description
and use, respectIvely, of the OBR.
Attempted execution In Normal
Illegal Procedure Fault.
Attempted repetition .ith
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-157
RPT,
or
BlR
RPO,
Hode
or
causes
an
RPL causes an
AL3CJ
PRIVILEGED -
REGISTER STORE
557 (1)
Store Page Table Pointers
SPTP
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
For i
= 0,
1, ••• , 15
C(PTWAH(i).POINTER) ->
C(Y+i)O,l~
C(PTWAH(it.PAGE) -> C(Y+i)15,Z&
C'PTWAM(i).F~
->
C(Y+i)Z7
0000 -> C(Y+i)ZB,31
C(PTWAHCi).USE) -> C(Y+l)32,35
MODIFICATIONS.
All except DU, Dl. CI, SC, SCR
INDICATORS:
None affected
NOTES'
The hardware assumes that Yl~,17
0000, and addressing Is
incremented according IV; no check is m~de.
=
The contents of PTWAH(m) remain
unchan~ed.
The Associative Memorv is ignored (forced to a Mno match-)
during Address Preparation.
See Section IV, Program Accessible Registers, and Section
V,
Addressing -- Segmentation and Pa~ing for description
and use, respectively, of the PTWAH.
Attempted execution
in Normal
Illegal Procedure Fault.
Attempted repetition "ith
Illegal Procedure Fault.
REVIEW DRAFT
SUUJECT TO CHANGE
October, 1975
2-158
RPT,
or
BAR
RPO,
Hode
or
causes
an
RPL causes an
AL39
PRIVIlE;EO - REGISTER STORE
Store Page Table Registers
SPTR
15~
(1)
Basic Instruction Format (See Figure 2-1).
SUMMARY.
For 1
= 0.
1, ••• , 15
C(PTWAM(l).AOOR)
o~
••• o
->
-> C(Y+l)O,17
C(Y+l)18,28
00 ••• 0 -> C(Y+l)30,35
MODIFICATIONSI
AI. except OU, Ol, CI, SC, SCR
INDICATORS:
None affected
NOTES.
The hardware assumes that Y14.17 = 0000, and addressing
will be Incremented accordingly; no check is made.
The contents of PTWAMCm) are unchanged.
The Associative Memory Is ignored (forced to a -no .atch-}
during Address Preparation.
See Section IV, Program Accessible Registers, and Section
V, Addressing -- Segmentation and Pagl~g for description
and use, respectively, of the PTWAH.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Attempted execution in
Illegal Procedure Fault.
Normal
or
aAR
Mode
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD,
or
RPL
2-159
causes an
causes
an
AL39
PRIVILEGED -
REGISTER 3TORE
•
Store Segment Descriptor Pointers
SSDP
557 (0)
FORMATI
Basic Instruction Format (See Figure 2-1).
SUMMARY.
For i
= 0,
1, ••• , 15
C(SDHAH(i).POINTER) ->
C(Y+i)O.l~
00 ••• 0 -> C(Y+i)15.2&
C(SDHAH(i).F) -> C(Y+l)27
0000 -> C(Y+iJ28,31
C(SDHAH(l).USE) -> C(Y+l)32.35
MODIFICATIONSI
All except OU, OL, CI, SC, SCR
INDIC~TORSI
~one
NOTES.
The hardNare assumes Y14.11
DODO, and
lncre.ented accordingly; no check is made.
affected
=
addressing
Is
The contents of SDHAM(l) are unchanged.
The Associatlve Memory is ignored (forced to a "no match-)
durlng Address Preparation.
See Section IV. Program Accessible Re~isters, and Section
V, Addressing -- Segmentation and Pagi~g
for description
and use, respectively, of the SOWAH.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Attempted execution In
Illegal Procedure Fault.
Normal
or
9AR
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
2-1&0
Mode
RPL
causes an
causes
an
AL39
PRtVIlE;EO - REGISTER STORE
Store Segment Oescriptor Registers
SSOR
254 (1)
I
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARya
For i
= 0,
1, ••• , 15
C(SOWAH(l).AOOR) -> C(Y+2i-pair)O,23
C(SOWAHtl).R1. R2, R3) -> C(Y+2i-pair)24,32
DODO -> C(Y+21-palr)33,3&
C(SO~AH(i).BOUNO)
-> CtY+21-palr)37.S0
C(SOWAHCl).R, E, P, U, G, C) ->.CtY+21-pair)51,51
CtSDWAHCi).Cl) -> C(Y+21-pair)58,71
MODIFICATIONsa
All except OU, Ol, CIt SC. SCR
INDICATORSI
None affected
.
NOTES.
The hardware assumes Y13.17 = 00000, and addressing
incremented according Iv; no check is tade.
Is
The contents of SDHAH(I) are unchanged.
The Associative Memory Is ignored Cforced to a -no Match-)
during Address Preparation.
See Section IV, Program Accessible Re~isters, and Section
V. AddreSSing -- Segmentation and Pagi~g
for description
and use, respective IV. of the SOMAH.
Attempted execution In
Illegal Procedure Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEH DRAFT
SU8JECT TO CHANGE
October, 1975
2-1&1
Normal
or
BAR
RPT,
RPO,
or
Hode
RPl
causes an
causes
an
Al39
PRIVILEGED - CLEAR ASSOCIATIVE MEMORY
Clear Associative Memory Paged
CAMP
532 (1)
FORMATa
Basic Instruction Format (See Figure 2-1).
SUMMARY'
For 1
o
= 0,
->
(I)
1, ••• , 15
C(PTWAMCi).Ft
->
C(PTWAHCl).USE)
MODIFICATIONS:
All except OU, OL, CI, SC, SCR
INDICATORS'
None affected
NOTEsa
The Full/Empty bit of each PTHAH Register is set to 0, and
the
usage
counters
(PTWAH.USE)
are set to t~eir
pre-assigned values of 0 through 15. The remainder of of
C(PTWAH(l») is unchanged.
The execution of this instruction ena)'es the PTWAH If it
is dlsab'ed and CCTPR.CA)16,11
01.
=
The execution of thiS instruction
CtTPR.CA)16,17
10.
=
the
dlsa~les
PTWAH
if
If C(TPR.CA)15 = 1, a selective :Iear of cache is
executed. Any cache block for which t,e upper 1~ bits of
the directory entry equal C(T~R.CA)O,13 wil I have its
Full/Empty bit set to Empty.
See Section IV, Program Accessible Registers and Section
V, AddressIng -- Segmentation and Paging for description
and use, respectively, of the PTWAH.
Attempted execution in Normal
Illegal Procedure Fault.
Attempted repetition with
Illegal Procedure fault.
REVIEW OR'FT
SUBJECT TO CHANGE
October, 1975
2-162
RPT.
or
B4~
RPO,
Hode
or
causes
an
RPL causes an
AL39
PR!VllEGED -
CAHS
ClEA~
ASSOCIATIVE MEMORY
532 (0)
Associative Memory Segments
Cle~r
FORHATa
BaSic instruction Format tSee Figure 2-1).
SUMHARya
For i
o
= 0,
-~
(i)
1, ••• , 15
CCSDWAHti).FJ
->
CCSOWAH(l).USE)
HODIFICATIONS'
All except OU, Ol, CI, SC, SCR
INDICATORS:
None
NOTES'
The Full/Empty bit of each SOWAH Register is set to zero,
and the usage counters (SDWAH.USE) are initialize~ to
their pre-assigned values of 0 through 15. The remainder
of C(SOWAH(i») are unchan~ed.
affecte~
The execution of this instruction ena~les the SOWAM if 1t
is previously disabled and if CtTPR.CA)10,17 = 01.
The execution
C(TPR.CA)lot17
0'= 10.
this
instruction disaDles
the
SDNA"
1f
The executIon of this instruction sets the full/Empty bits
of all cache blocks to Empty if CCTPR.:A)15
1.
=
See Section IV, Program Accessible Re~lsters, and Section
V. Addressing -- Segmentation and Pagi~g for description
and use, respectively, of the SOWAH.
Attempted execution in
Illegal Procedure Fault.
Attempted repetition ~lth
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-1&3
Normal
or
RPT,
RPD,
aAR
or
Hode
RPl
causes an
causes
an
AL39
PRIVILEGED - CONFIGURATION AND STATUS
233 (0)
Read Memorv Controller Mask Register
RHCH
FORHATI
Basic Instruction Format (See Figure 2-1).
SUHHARVI
For the selected System Controller'
If the Processor has a Hask
C(HR10,15
->
Registe~
asssigned, then
C(AQ'O,15
00 ••• 0 -> C(AQ)16,31
CCHR)32,35 -> C(AQ)32,3S
C(MR)36,51
->
CCAQ)36,S1
00 ••• 0 -> C(AQ)52,67
C(HR)68,71
->
C(AQ)68,71
otherwise, 00 ••• 0
->
C(AQ)
se,
MODIFICATIONSI
All except DU, Ol. CI,
INDICATORS.
(Indicators not listed are not
Zero
If C(AQ)
Negative
If C(AQ)O
NOTES'
= D,
= 1,
SCR
affecte~)
then ON; otherwise OFF
then ON; otherwise OFF
The contents of the Mask Register remain unchanged.
C(TPR.CA)O,2 specify which
System Controller) Is used.
Processo~
Attempted execution 1n Normal
Illegal Procedure Fault.
RlVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-16~
or
B~R
Port (i.e., which
Mode
causes
an
PRIVILEGED - CONFIGURATION AND STATUS
.. 12 (0)
Read System Controller Register
RSCR
FORHAT.
Basic Instruction Format (See Figure 2-1).
SUMMARY.
The effective address, Y, is used tl select a sy~te.
controller (SCU)
and t~e function to be performed as
folio MSI
Effective
AJUiC£.U
yOODDx
C(SCU Mode Register) -> C(AQ)
yOOOlx
C(SCU Configuration Switches) -> C(AQ)
y0002x
CCInterrupt Mask Port 0) -> C(AQ)
yOD12x
C(lnterrupt Mask Port 1) -> C(AQ)
y0022x
CClnterrupt Hask Port 2) -> C(AQ)
y0032x
C(Interrupt Mask Port 3) -> C(AQ)
y0042x
C(Interrupt Mask Port 4) -> C(AQ)
y0052x
C(Interrupt Hask Port 5) -> C(AQ)
y0062x
C(Interrupt Mask Port 6) -> CCAQ)
y0072x
C(Interrupt Hask Port 7) -> CCAQ)
y0003x
C(Interrupt Cells) -> C(Al)
y0004x
or
y0005x
C(System Clock) ->
i
yOD06x
or
C(AQ)
C(Store Unit Hode Registe·) ->
C(AQ)
y0007x
wherel
y
x
= octal value of YO,2
= any octal digit
as used to select SCU
MODIFICATIONS.
All except DU, Ol, CI, SC, SCR
INDICATORSI
None af f ected
NOTES'
See Section IV, Program
Accessible
Registers,
description and use of the various registers.
for
For effective addresses y0006x and y0007x. Store Unit
selection is done by the normal addres; decoding function
of the System Controller.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-165
AL39
PRIVIL~Gf.O
- CONFIGURATION AND STATUS
Attempted e~ecut!on in
Illega' Prodecure Fault.
Normal
or
Attempted repetition with RPl causes
Fault.
BAR
a~
Hode
causes an
11 legal
Proce1ure
Read Sw itches
RSW
231 CO)
FORMAT I
BaSic Instruction Format (See Figure 2-1).
SUMMARYI
The effective address. Y, is used to select certain
Processor switches whose settings are read into C(Al.
The switches selected are as rollows'
Effective
Address
~tlgQ
xxxxxO
CIOata Switches)
xxxxxi
C(Config. Switches, ports A. B, C, 0)
xxxxx2
00 ••• 0 -> C(AlO,5
C(Fault Base Switches) -> C(A)&,12
00 ••• 0 -> CfA)13,2&
CfProcessor 10) -> CCA)27,33
C(Processor Number Switches) -> C(A)3~,35
xxxxx3
C(Config. Switches, ports E, F, G, H)
xxxxx~
->
CfA)
MODIFICATIONS.
All, but none affect instruction execution
INDICATORS'
(Indicators not listed are not
If CIA)
Negative
If C(A)O
NOTES'
REVIEW DRAfT
SUBJECT TO CHANGE
Oct 0 b er , 197 5
->
C(A)
CIA)
00 ••• 0 -> CCA)0.12
C(Port Interlace and Size Switches)
00 ••• 0 -> C(A)29,35
Zero
->
= 0,
= 1.
->
CCA)13,28
affecte~)
then ON; otherwise OFF
then ON; otherwise OFF
See Section IV,
Program
Accessible
description and use of the switch data.
Registers
Attempted e~ecution in
Illegal Procedure Fault.
Normal
or
BAR
Hode
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO.
or
RPL
2-1&&
for
causes an
causes
an
AL39
PRIVILE;EO - SYSTEM CONTROL
015
connect 1/0 Channel
CIOC
(0)
FORHATa
Basic Instruction Format (See Flgure 2-1).
SUMMARY I
The System Controller addressed by Y (i.e., contains the
word at Y) sends a connect pulse to the port specified by
C (Y) 33,35.
MODIFICATIONSI
All except OU, OL, CI, SC, SCR
INDICATORSI
None affected
NOTES'
Attempted e~ecutlon in Normal
Illegal Procedure Fault.
Attempted repetition with
Illegal Procedure Fault.
or
RPT,
BAR
RPD,
Hode
or
caus~s
RPL causes an
Set Hemory Controller Mask Register
SHeM
an
553 (0)
FORHATa
Basic Instruction Format (See Figure 2-1).
SUMMARYI
For the selected System Contro'lerl
If the Processor has a Mask Registe- assigned, then
CtAQ)32,35
->
CIHR)3Z,35
C(AQ)36,51
->
C(HR)36,51
CCAQ)68,71
->
C'HR)68,71
otherwise, a Store Fault, Not
HODIFICATIONS.
All except DU, Dl, CI, SC, SCR
INDICATORS'
None af 'ected
NOTEsa
C(AQ) are unchanged.
Con'r~l,
C(TPR.CA)O,2 specify which Processor
System Controller) is used.
Attempted e~ecution In
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-167
Nor.al
or
occurs.
Port
3AR
(I.e.,
Hode
which
causes an
Al39
PRIVILEGED - SYSTEH CONTROL
Attempted repetition with RPL causes an Illegal
Fault.
Procedure
Set Memory Controller Interrupt Cells
SHIC
451 (D)
FORHATa
Bas!c Instruction Format (See Figure 2-1).
SUMMARya
For i
i~
For i
= 0,
C(A'!
= D.
1 ••••• 15 and C(A)35 = 0'
= 1.
then set Interrupt Cell i ON
1 • • • • • 15 and C(A)35
= 11
if C(A)! = 1, then set Interrupt Cell 16+1 0,.
MODIFICATIONSI
Alt except DU. OL, CI, SC, SCR
INDICATORSI
None affected
NOTES.
CfTPR.CA)O.2 specify which Processor
System Controller) is used.
Attempted eKecution in
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-1&8
Normal
or
Port
BAR
(i.e.,
Hode
which
causes an
AL39
PRIVILE~ED
Set
SSCR
Syste~
- SYSTEM CONTROL
D57 (D)
Controller Register
FORHATI
Basic Instruction Format (See Figure 2-1).
SUMMARYI
The effective address, V. is used t) select a System
Controller (SCU) and the functIon to be performed as
follo"SI
Ef f eC,t lve
Address
Ewlc.ll.sln
yOOOOx
e(AQ) -> C(SCU Hode Register)
yOOO1x
Reserved
yOD02x
C( AQ) -> CCInterrupt Mask Port
yOO12x
C(AQ)
->
CClnterrupt Mask Port 1)
yOD22x
C (AQ'
->
CCInterrupt Hask Port 2)
y003Zx
C (AQ)
->
CClnterrupt Hask Port 3)
yOD42x
C(AQ)
->
C CInterrupt Hask Port
yOO52x
C CAQ)
->
CClnterrupt "ask Port 5)
vOO6Zx
C(AQ)
->
C (Interrupt Mask Port 6)
yOO7Zx
C (AQ)
->
C (Interrupt Hask Port 7)
yOOO 3x
C(AQ'O,15 -> C(Interrupt Cells)(0.15)
C(AQ)36.51 -> CClnterrupt Cel's'(16,31)
yOOO6x
or
vOOD7x
C (AQ)
"here'
y = octal va Iue of
->
Q)
It)
C(Store Unit Hode Register)
YD.2 as used to select SCU
x = any octal digit
MODIFICATIONS a
All except OU, OL, CIt SC, SCR
INDICATORSI
None af fected
NOTES.
If the Processor does not have a Mask
the selected System Controller, a
Control, Mill occur.
~eglster
Store
assigned in
Fault,
Not
For effective addresses yOOOOX and yOOD7x, Store Unit
selection is done bv the normal addreSi decoding function
of the System Controller.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-1&9
PRIVILEGED - SYSTEM CONTROL
See
Section
IV,
Progralll Accessi31e Registers,
description and use of the various registers.
Attempted execution on Normal
Illegal Procedure Fault.
or
B4R
Mode
causes
for
an
REV lEW DR liFT
SUBJECT TO CHANGE
October, 1975
2-17D
AL39
PRIVILEGED - MISCELLANEOUS
Absolute Address to Accumulator
ABSA
212 COl
FORHATa
Basic Instruction Format (See Figure 2-1).
SUHMARY Z
Final Hain Store Address
00 ••• 0
->
->
CIA)O,23
C(A)Z4,35
HODIFICA"TIONSI
All except OU, DL, CI, SC, SCR
INDICATORS:
(Indicators not listed are not affectej)
Zero
If CtA) = 0, then ON; otherwise
Negative
If C(AIO
NOTES:
= 1,
~FF
then ON; otherwise OFF
If the ABSA instruction Is executed in Absolute mode, CIA)
will be undefined.
Attempted execution in
Illegal Procedure Fault.
Noraal
or
BAR
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD.
or
modes causes an
RPL
Delay Until Interrupt Signal
DIS
Basic Instruction Format (See Figure 2-1).
SUMMARY:
No operation takes place,
continue with the next
program interrupt signal.
MODIFICATIONSI
All, but none affect Instruction execution
INDICATORS:
None affected
NOTES:
Attempted execution in Normal
Illegal Procedure Fault.
REVIEW DRAFT
SUSJECT TO CHANGE
October. 1975
2-171
an
&1& (01
FORMAT:
Attempted repetition with
Illegal Procedure Fault~
causes
and
the
Processor does not
1t waits for a
instructi~n;
RPT,
or
BAR
RPD,
Hode
or
causes
an
RPL causes an
AL39
EIS - ADDRESS REGISTER LOAD
56n (1)
Alphanumeric Descriptor to ARn
AARn
FORMAT.
EIS Single-Word Instruction (See Figure 2-1).
SUMMARY'
For n
= O.
1 ••••• or 7 as determined oy operation code
CeY)O.lT
CCPRn.WORDNOl
->
= 00
If C(Yl21,22
CCY)18.19
->
(TA code
= 0).
then
= 1),
then
C(PRn.CHAR)
0000 -> C(PRn.BITNOl
= 01
If ClYlZl,22
(TA code
(6 • C(Y)18.20) I 9 -> C(PRn.CHAR)
-> C(~Rn.BITNOl
(6 • C(Y)18.20) modulo 9
= Z).
If C(YlZl.22 = 10 (TA code
then
ClY)18.20 I 2 -> C(PRn.CHAR)
4 • (C(Y)18.20) modulo 2) + 1 -> C(PRn.BITNO)
"OOIFICATIONS'
All except OUt Ol. CI. SC. SCR
INDICATORS'
None af fected.
NOTES'
An alphanumeric descriptor is fetched from Y and C(Y)21,Z2
(TA field)
is examined to determine the data
type
descr lbed.
=
If TA
a (C)-bit data), C(Y)18,19 goes to C(PRn.CHAR) and
zeros fi11 C(PRn.BITNO).
=
If TA = 1 (6-bit data) or fA
2 l4-bit data), ClY)18,ZO
is appropriately translated into an equivalent character
and bit
pOSition
that
goes
to
C(PRn.CHAR)
and
CCPRn.BIfNO).
If C(Y)Zl.Z2
occurs.
If CCY)ZJ
=1
= 11
(TA code
= 3)
an Illegal Procedure Fault
an Illegal Procedure Fault occurs.
=
If
CCY)21,22
00 CTA code = 0) and CCY)20
Procedure Fault occurs.
=
=1
an IllEgal
=
If CCY)21,22
01 CTA code
1) and C(Y)16,20 = 110 or 111
an I. legal Procedure Fau. t occurs.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-172
AlJ9
EIS - ADDRESS REGISTER LOAD
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD.
or
RPL
Load Address Register n
LARn
FORMATa
EIS Single-Word Instruction (See Figure 2-1).
SUMMARYI
For n
= D.
All except DU. Ol. CI. SC, SCR
INDICATORS.
None affected
NOTES.
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD.
or
RPL
Load Address Registers
SUMMARY'
causes
an
4&3 (1)
For n
= O.
I ••••• 7
->
C(ARn)
MODIFICATIONS.
All except OU, Ole CIt SC, SCR
INDICATORS.
None a1 'ected
NOTES.
The hardware assumes Y15.17 = 000 and
increaented accordingly; no check is made.
Attempted repetition with
Illegal Procedure Fault.
RPT.
RPD.
addressing
or
load Pointers and Lengths
EIS Single-Word Instruction (See Figure 2-1).
SUMMARYI
e(Y-biockS)
MODIFICATIONSI
All except OU, DL. CI,
->
is
RPl causes an
4&7 (1)
FORHATa
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
(1)
EIS Single-Word Instruction (See Figure Z-l) •
C(Y+n)O.Z3
LPL
7&n
CCARn)
->
MODIFICATIONSI
.. FORHAT'
an
1 ••••• or 7 as deteralned by operatIon code
C(Y)O,23
LAREG
causes
CeOecimal Unit Control lata)
2-173
se,
SCR
AL39
EIS -
ADDR[SS REGIST[R LOAD
INDICATORSa
None affected
NOTES.
See. Section IV. Program
Accessibl!
Registers,
description and use of Decimal Unit Control Data.
The hardware aSSumes Y15,17 = 000 and
incremented accordingly; no check is made.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
or
addressing is
RPL
causes
Numeric Descriptor to ARn
NARn
EIS Single-Word Instruction (See Figure 2-1).
SUHHARYI
For n
1, ••• ,
an
66n Cl)
FORHATZ
= 0,
for
or 7 as determined oy operation code
C(Y)O,17 -> C(PRn.WORONO)
If C(Y)Z1
=0
(TN code = D), then
C(Y)18,20 -> C(PRn.CHAR)
0000 -> C(PRn.BITNO)
If C(Y)21
=1
(TN code
(C(Y)18,ZO) I
~
•
= 1),
then
Z -> C(PRn.CHARl
CC(Y)18,20 modulo 2) + 1 -> :(PRn.BITNO)
HODIFICATIONSI
All except OU, Ol, CI, SC, SCR
INDICATORSI
None affected
NOTES.
A numeric descriptor
Is fetched from Y
is examined.
~nd
C(Y)Zl (TN bit)
.
=
If TN
0 (9-blt data), then C(Y)18,19 go to C(PRn.CHAR)
and zeros fil I C(PRn.BITNO).
=
If
TN
1
(~-bit
data), C(Y)18,2D
is appropriatelv
translated to an eQuivalent character and bit position
that goes to C(PRn.CHAR) and C(PRn.BITNO).
=
If C(Y)21
0 (TN code
Procedure Fault occurs.
= 0)
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-17~
and
RPT,
C(Y)2D
=
RPO,
or
1
an
Illegal
RPL causes an
AL39
EIS - ADDRESS REGISTER STORE
ARn to Alphanumeric Descriptor
ARAn
FOR"ATa
EIS Single-Word Instruction (See FIgure Z-l).
SUMMARya
For n
= 0,
1, ••• , or 7 as determined
C(PRn.HORDNO)
l~
C(Y)Zl.ZZ
->
o
->
operation code
C(Y)O,17
= 00
C(PRn.CHAR)
~y
->
= 0),
(TA code
then
C(Y)18,19
C(Y)ZO
If CIY)Zl,ZZ
= 01
'TA code = 1), then
(9 • crPRn.CHAR) + C(PRn.BITNO) , & -> CCY)18,ZO
If C(Y)Zl,ZZ
= 10
'TA code = Z), then
19 • C(PRn.CHAR) + C(PRn.BITNO) - 1) I
HODIFICATIONSI
All except OU •. OL, CI, SC, SCR
INDICATORS.
None af f ected
NOTESI
This instruction is the inverse of
4 -> C(Y)18,20
AAR~.
The alphanumeric descriptor Is fetched from
Y
and
C(Y)Zl,22 ITA fie'd) Is examined to determine the data
type described.
If fA
=a
=1
(9-bit data), CIPRn.CHAR) goes to C(Y)18,19.
=
If fA
(&-blt data) or TA
2 C4-bif data). C(PRn.CHAR)
and C(PRn.BITNO) are tran~lated ~o an e~uivalent charatter
position that goes to CIY)18.20.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
If C(Y)Zl,ZZ = 11 (TA code = 3) or C(Y)23
bit), an Illegal Procedure Fault occurs.
= 1
Attempted repetition with
Illegal Procedure Fault.
RPl
2-175
RPf,
RPO.
or
(unused
cause~
an
AL39
EIS -
ADDRESS REGISTER STORE
ARn to Numeric Descriptor
ARNn
FORHAT'
(IS Single-Word Instruction (See Figure 2-1).
SUMHARYI
For n
= O.
1, •••• or 7 as determined
operation code
~V
C(PRn.WORONO) -> C(Y)O.17
=0
If C(Y)21
'TN code
= 0),
tnen
C(PRn.CHAR) -> C(Y)18.19
o
->
C(Y)2D
If C(Y)Zl :
(9 •
1 (TN code
C(P~n.CHAR)
ct.
= 1).
then
+ C(PRn.BITNO) -
1) I 4 -> C(Y)18.2D
MODIFICATIONS'
All except DU. Dl.
INDICATORS'
None af fected
NOTES.
This instruction is the inverse of NAR,.
..
SC, SCR
The numeric descriptor 1s fetched from Y
is examined •
and
C(Y)21
(TN
bit)
If
TN =
CCY)18.19.
0
(9-blt
data).
then
CCPRn.CHAR)
goes
to
=
If TN
1 (4-blt data), then C(PRn.CHAR) and C(PRn.BITNO)
are
translated to an equivalent cha·acter position that
goes to C(Y)18.20.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD.
or
RPl
Store Address Register n
SARn
FORHAll
EIS Single-Word Instruction (See Figure 2-1).
SUHMARYI
For n
= 0,
causes
an
7ltn (1)
1 ••••• or 7 as determined oy operation code
C(PRn.AR) -> C(Y)O,23
00 ••• 0 -> C(Y)24.35
MODIFICATIONS:
All
INDICATORS:
None affected
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
except OUt DL. CIt SC, SCR
2-17&
AL39
[IS -
NOTEsa
Attempted repetition with
Illegal Procedure Fault.
RPT,
REGISTER STORE
AO~RESS
RPO,
or
RPl
Store Address Registers
SAREG
EIS SIngle-Word Instruction (See Figure 2-1).
SUH"ARYI
For n
C(ARn)
an
It43 (1)
FORHATI
= 0,
causes
1, ••• , 7
->
C(Y+n)O,23
00 ••• 0 -> C(Y+n)Z4,35
HODIFICATIONS'
All except OU, Ol, CI, SCt SCR
INDICATORS.
None affected
NOTEI
The hardware assu~es Y1S,17 = ODD and
incremented accordingly; no check is m3de.
Att~mpted
repetition with
Illegal Procedure Fault.
RPT,
RPD,
addressIng
or
RPl causes an
Store Pointers and lengths
SPL
It,. 7 (1)
FORHATa
EIS Sinlle-Word Instruction (See FIgure 2-1).
SUHHARYI
C(Declaal Unit Control Data) ->
HODIFICA TIONS:
All except OU, Ol. CI.
INDICATORS:
None af fee ted
NOTES:
The hardware assumes ·Y15,17 = 000 and
incremented accordingly; no check is .ade.
se,
Is
C(Y-bl~ck8)
SCR
addressIng
See
Section
IV,
Program Accessl~le Registers,
description and use of Decimal Unit Control Data.
Is
for
•
Attempted repetition with
Illegal Procedure Fault.
RlVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
Z-177
RPT,
RPD.
or
RPl
causes
an
Al3c)
EIS - ADOklSS REGISTER SPECIAL ARITHMETIC
5D 2 (1)
Add It-Bit Displacement to Address Register
AltBD
FORHATI
o
0 0
Q
2 J
I
I
1 1
1
ADDRESS
:
OPCOOE
J
2
I
3
Figure 2-12
--La.
J
a ARn I
3
2 2 Z J J 3
9 0 1-Z
_---LA.
I
I
UIAIO 01
--1-LL J
18
2
REG
Z
10 1 1
I
J
,. I
EIS Address Register Special Arithmetic Instruction Format
ARn
Number of Address Register selected
ADDRESS
Literal word displacement value
OPCOOE
Instrucfion operation code
I
Program Interrupt inhibit bit
A
Use Address Register contents flag
REG
Any Register Modifier except DU, Ol,
SU""ARYI
If A = 0, then
ADDRESS. C(REG)
C(REG) modulo It
I
->
,. ->
a~~
IC
C(PRn.WORDNJ)
C(PRn.CHAR)
It • (C(REG) modulo 2) + 1 -> C(PRn.3ITNO)
If A
= 1,
then
C(PRn.WOROND) + ADDRESS + (9 • C(PR~.CHAR) + ,. • C(REG)
+ C(PRn.BITNO»
I 36 -> C(PRn.WORJNO)
«9 • C(PRn.CHAR) + ,. • CCREG) +
C(PRn.8ITNO) mOdulo 36) I 9 -> C(PRn.CHAR)
,. • (C(PRn.CHAR) + 2 • CCREG) +
C(PRn.BITNO» I 4) modulo 2 + 1
->
C(PRn.BITNO)
MODIFICATIONS:
None except AU, QU, AL, QL, or Xn
INDICATORS:
None af fee ted
NOTESI
The steps described in SJMMARY define special 4-bit
addition arithmetic for ADDRESS, C(~EG), C(PRn.WORONO),
C(PRn.CHAR), and C(PRn.dITNO).
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-178
4L39
EIS - ADDRESS
REGISTE~
SPECIAL ARITHMETIC
The use of an Address Register Is inhe~ent; the value of
bit 29 affects Address Preparation but not instruction
decod Ing.
Attempted repetition with
Illegal procedure Fault.
RPT.
RPD.
or
RPL
causes
Add &-81t Displacement to Address Register
A&8D
501 (11
FORMATa
EIS Address Register Special Arithmetic Instruction
(See Figure 2-121.
SUMI1ARYI
If A
= 0,
an
then
ADDRESS. C(REG)
(Co • CCREG»
(0 • C(REG)
I
0 -> C(PRn.WORDNl)
modulo 3&) I 9 ->
C(P~n.CHAR)
modulo 9 -> C(PRn.8ITNl)
I f A = 1, then
C(PRn.WORDNO) • ADDRESS + (9 • C(PRn.CHAR) + 0 •
+ C(PRn.BITNO»
I 3& -> C(PRn.WORlNO)
C(~EG)
«(9 • C(PRn.CHAR) + 0 • CeREG) +
C(PRn.BITNO» modulo 3&) I 9 -> C(PRn.CHAR)
(9 • C(PRn.CHAR) + 6 • C(REG) +
C(PRn.8ITNOll modulo 9 -> CePRn.BITNO)
MODIfICATIONSI
None except AU. QU. Al, QL. and Xn
INDICATORSI
None Affected
NOTES'
The steps described in SUMMARY define special 6-bit
addition arithmetic for ADDRESS, C(~EG). C(PRn.WORDNO),
C(PRn.CHAR), and C(PRn.BITNOI.
The use of an Address Register is inhe·ent; the value of
bit 29 affects Address Preparation but not instruction
decoding.
Atempted repetition with
Illegal Procedure Fau.t.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-119
RPT,
RPD,
or
RPl
causes
an
Al39
EIS - ADDRESS
REGIST~~_SPECIAL
ARITHMETIC
500
Add C)-Bit OlsP'acement to Address RegIster
A9BD
FORMATI
EIS Address Register Special Arithmetic Instruction
(See Figure 2-12).
SUMMARYI
If
A
=
Q,
then
ADDRESS + C(REG) I 4
CCREG) modulo 4
If A
(1)
->
->
C(PRn.WORONO)
CCPRn.CHAR)
= 1, then
C(PRn.WORONO) + ADDRESS +
(C(REG) + C(PRn.CHAR»/~
(C(PRn.CHAR) + C(REG»
->
C(PRn.HORONO)
mOdulo 4
->
:CPRn.CHAR)
0000 -> CCPRn.DITNO)
MODIFICATIONSI
None except AU, QU, AL, Ql, and Xn
INDICA TORS.
None affected
NOTES_
The steps described in
addition arithmetic for
and C(PRn.CHAR).
SUMMARY define special C)-bit
ADDRESS, CC~EG), CCPRn.HORONO),
The use of an Address Register is inhe~ent; the value of
bit 29 affects Address Preparation but not instruc~ion
decoding.
Attempted repetition with
Illegal Procedure Fault.
ABO
R~T,
RPO,
or
RPL
causes
Add 81t Displacement to Address Register
FORHAT_
EIS Address Register Special Arithmetic Instruction
CSee Figure 2-12).
SUMMARY I
I f A = 0, the n
ADDRESS + C(REG) I 3&
(CCREG) modulo 3&) I 9
CCREG) modulo 9
If A
= 1,
->
an
503 C1)
-> C(PRn.WORD~O)
-> C(PRn.CHA~)
CCPRn.BITNO)
then
C(PRn.WORONO) + ADDRESS + (9 • C(PR~.CHAR) + 36 • C(REG)
+ C(PRn.BITNO»
I 36 -> C(PRn.HORJNO)
REVIEH DRAFT
SUBJECT TO CHANGE
October, 1975
2-180
AL39
EIS - ADDRESS
REGISTE~
SPECIAL ARITHMETIC
(9 • C(PRn.CHAR) + 36 • CCREG) +
C(PRn.etTNO» modulo 36) I 9 -> C(PRn.CHAR)
(q
• C(PRn.CHAR) + 36 • CCREG) +
C(PRn.BITNO» modulo q -> C(PRn.BITNO)
HODIFICATIONSI
None except AU, QU, Al, Ql, or
INDICATORS'
None affected
NOTES.
The ~teps described in SUMMARY define special bit addition
arithmetic
for
ADDRESS,
CCREG),
CCPRn.WORO~O),
C(PRn.CHAR), and C(PRn.dITNO).
X~
The use of an Address Register is inhe-ent; the value of
bit Zq affects Address Preparation but not instructIon
decoding.
Attempted "repetition with
Illegal Proced~re Fault.
RPT,
RPD.
or
RPl
causes
Add Word Displacement to Address Register
AND
an
507 (1)
EIS Address Register Special ArithmetIc InstructIon
(See Figure 2-12).
SUHHARYI
If A
= 0,
then
ADDRESS + C(REG)
If A
= 1,
->
CtPRn.WORDNO)
then
C(PRn.HORONO) + ADDRESS + C(REG) ->:(PRn.WORONO)
00 -> C(PRn.CHAR)
0000 -> C(PRn.8ITNO)
MODIFICATIONS'
None except AU, QU. Al, Ql, and Xn
INDICATORSI
None affected
NOTES'
The use of an Address Register Is lnne-ent; the
bit 29 affects
decod ing.
Address
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-181
value
of
PreparatIon but not instruction
RPT,
RPD,
or
RPl
causes
an
Al39
[IS -
ADOR~SS
REGISTER SPECIAL ARITHMETIC
Subtract 4-bit DIsplacement from Address
SltBO
FORMATa
EIS Address Register Special
(See Figure 2-12).
SUMMARYI
If A = 0, then
~
(ADDRESS + CCREG)
- CCREG)
~odulo
'+
I
= 1,
522 (1)
Instruction
A~ithmetic
4) -> C(PRn.HlRDHO)
C(PRn.CHAR)
->
- '+ • (CCREG) modulo 2) + 1
If A
Reglste~
-> CCPR~.BITNO)
then
C(PRn.HORDNO) - ADDRESS + (9 • C(PRn.CHAR) - 4 • C(REG)
+ C(PRn.8ITNO»
/ 30 -> CCPRn.HORlNO)
«9 •
C(PRn.CHAR) - .. • CCREG) +
C(PRn.BITNO)J modulo 36) I 9 -> C(PRn.CHAR)
.. • CC(PRn.CHAR) - 2 • CCREG) +
C(PRn.BITNO) I '+)modulo 2 + 1
->
CCPRn.BITNO)
MODIFICATIONSI . None except AU, QU, AL, QL, or Xn
..INDICATORS:
NOTESI
None affected
The steps described in SUMMARY defIne specia1 it-bIt
subtraction arithmetic for ADDRESS, Ce~EG), CCPRn.WORDNO),
C(PRn.CHAR), and C(PRn.BITNO).
The use of an Address Register is
bit 29 affects Add~ess Preparation
decoding.
Attempted repetition with
Illegal procedure Fault.
RPT,
in~erent;
b~t
RPD,
not
or
the value of
instruction
R?L causes an
Subtract 6-Blt Displacement from Address Register
5680
FORHAT I
EIS Address Register Special Arithmetic Instruction
CSee Figure 2-12).
SUMMARY I
I
f
A = 0, then
- (ADDRESS + CCREG)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
521 (1)
C CREG»
-
CC& •
-
(e& • CCREG)
m0
I
6) -> C(PRn.WQRDNO)
cu I 0 3 I)
modulo q
2-182
I
->
9 - > C ( P Rn • CHAR.)
CePRn.BITNO)
AL39
EIS - ADDRESS
If A
= 1,
REGISTE~
SPECIAL ARITHHETIC
then
,C(PRn.WORONO) - ADDRESS. (9 • C(PR~.CHAR) - & • C(REG)
+ C(PRn.BITNO» I 36 -> C(PRn.WORJNO)
(C9 • C(PRn.CHAR) - 6 • CCREG) +
C(PRn.BITNO» modulo 3&) I 9 -> C(PRn.CHAR)
(9 • C(PRn.CHAR) - 6 • C(REG) +
C(PRn.BITNO» modulo 9 -> CCPRn.BITNO)
MODIFICATIONS.
None except AU, QU, AL, QL, and Xn
INDICATORS:
None Affected
NOTESa
The· steps described in SUMMARY define special 6-blt
subtraction arithmetic for ADDRESS, C(~EG), C(PRn.WORONO),
C(PRn.CHAR), and C(PRn.BITNO).
The use of an Address Register ls
bit 29 affects Address Preparation
decoding.
Atempted repetition with
Illegal Procedure Fault.
RPT,
In~erent;
not
b~t
RPD,
or
the value of
instruction
RPL
causes an
Subtract 9-Bit Dlsplacement from AddresS Register
S980
FORHATa
520 (1)
EIS Address Register Special Arithmetic Instruction
(See figure 2-12).
If A = 0, then
-
(ADD~ESS
+ C(REG) I
- CCREG) modulo 4
If A
= 1,
->
~)
C(PRn.WORDNO)
->
C(PRn.CHAR)
then
C(PRn.WORDNO) - ADDRESS +
(CCPRn.CHAR) - CCREG» I
(CCPRn.CHAR) - C(REG»
~
->
modulo
~
CCP~.CHAR)
->
:CPRn.CHAR)
0000 -> CCPRn.BITNO)
MODIFICATIONSI
None except AU, QU, AL, QU, or Xn
INDICATORSZ
None affected
NOTES:
The steps described in SUMMARY define
subtraction arithmetic for ADDRESS. C(REG).
so~ci~1
9-bit
C(~~n.WORDN~),
and C(PRn.CHAiU.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-183
AL39
EIS - ADDRESS REGISTER SPECIAL ARITHMETIC
The use of an Address Register is
bit 29 affects Address Preparation
decoding.
Attempted repetition with
Illegal Procedure Fault.
RPT.
in~erentl
bJt
RPO.
not
or
the value of
instruction
RPL causes an
Sybtract Bit Displacement from Address Register
SBO
FORHAT'
EIS Address Register Special Arithmetic Instruction
(See 'Figur-e 2-12).
SUHHARY'
If A
= O.
523 (1)
then
-
(ADDRESS + C(REG) / 36)
-
CCCREG) modulo 3&) / 9
- CCREG) modulo 9
-> -
-> C(PRn.~ORDNO)
->
CCPRn.C~AR)
C(PRn.BITNO)
If A = 1,' then
C(PRn.WORDNO) - ADDRESS + (9 • C(PR~.CHAR) - 3& • C(REG)
+ C(PRn.BITNO»
/ 36 -> C(PRn.WOR)NO)
C(PRn.CHAR) - 36 • C(REG) +
C(PRn.BITNO» modulo 36) I 9 -> CCPRn.CHAR)
«9 •
(9 • C(PRn.CHAR) -
C(PRn.BITNO»
36 • CCREG) •
modulo 9
->
C(PRn.BITNO)
MODIFICATIONSI
None except AU, QU. AL, QL. or Xn
INDICATORS:
None a1 'ected
NOTES:
The steps described in SUMMARY define
special
bIt
subtraction arithmetic for ADDRESS. C(~EG), C(PRn.WORDNO),
C(PRn.CHAR). and C(PRn.BITNO).
The use of an Address Register Is
bit 29 affects Address Preparation
decoding.
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1915
2-18"
RPT,
in~erent;
bJt
RPD,
not
or
the value of
instruction
RPL causes an
AL39
EIS - ADDRESS
SPECIAL ARITHMETIC
REGISTE~
527 (1)
Subtract Word Displacement fro. Address Register
SMD
FORMATs
[IS Address Register Special Arithmetic Instruction
(See Figure 2-12).
SUMMARYI
If A
-
= 0, then
(ADDRESS + C(REG»
->
C(PRn.WORDNl)
If A = 1, then
C(PRn.WORDNO) 00
->
(ADDRESS + CCREG»
->
C(PRn.WORDNO)
C(PRn.CHARJ
0000 -> CCPRn.BITNO)
MODIFICATIONSI
None except AU, QU, Al, Ql, or Xn
INDICATORSa
None Affected
NOTES.
The use of an Address Register is lnhe-ent; the value of
bit 29 affects Address PreDaratlon but not instruction
decoding.
Attempted repetItion with
Illegal Procedure Fault.
RPT,
RPD,
or
RPl
causes
an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-185
Al39
lIS -
ALPHANUMERIC COMPARE
CHPC
Compare Alphanumeric Character Strings
106 (1)
FORHATS
___---i-Lll.-1
Il
I
I
S
J0
FILL
1-
q
J
--L.i
106
Y-charo2
I
J
HFl
III
(1)
1_1
I
71
Nl
J
I
1
I
NZ
I
I
18
I
2 1
3
J
I
I
10 1
71
I
I I
I CN1 ITAUOS
a
I
I I
I
I
I
I CN2 I 0 0 01
Y-charnl
Figure 2-13
3
2
--1
Z
LI
I
2 2 2
1 Z l_L---La-3
I
:
I1F2
I
I
Q
J
I
0:
Z Z Z Z Z
1 1
0 0 1 1
0
12
Hultl-W~rd
Compare Alphanumeric Strings (CMPC) EIS
Instruction Format
FIll
Fill character for string extension
HFl
Modification Field for Operand Descriptor 1
·HF2
Modification Field for Operand Descriptor 2
I
Program Interrupt inhibit bIt
Y-charn1
Address of "Ieft-hand- string
CN1
First character position of "1eft-hand- string
TAl
Data type of "left-hand" string
Nl
Length of "left-hand" string
Y-charQ2
Address of ··r i ght-hand" s tr ing
CNZ
First Character position of "right-hand" string
N2
Length of "right-hand- string
ALH Coding Format:
cmpc
desc,Oc
(MFl),(HFZ)[,fill(octalexpression»)
Y-charnl[(CN1»),Nl
D
4, 6, or 9 (TAl
descna
Y-charnZ(CNZ)],NZ
SUMMARYS
=
For i
= 1,
2, ••• ,
C(Y-charol)i-l
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
n
= 4,
= 2,
1, or 0)
6, or 9 (TAZ is ignored)
minimum (Nl,N2J
II
Z-186
C(Y-charoZ)i-l
AL39
EIS - ALPHANUMERIC COMPARE
If N1 < HZ, then for i
CCFILL)
II
= N1+1.
Nl+Z •••• , NZ
C1Y-charQ2)i-l
If N~ < HZ, then for 1
CCY-charnl)i-l
II
= NZ+l.
NZ+Z •••• , N1
C(FILL)
MODIFICATIONS.
None except AU. QU. AL. QL. or Xn for HF1 and "F2
INDICATORS'
(Indicators not listed are not affected)
= C(Y-charn2li
Zero
If C(Y-charn1)!
otherwise. OfF
Carry
IfC(Y-charnl)i < CCY-charnZ)i for any 1,
otherwise ON
NOTES'
for all i . then ON;
th~n
OFF;
Both strings are treated as the data ttpe given for
the
"left-hand" string. TAl.
The data type given 'or the
"right-hand" string. TAZ, is ignored.
Comparis!on is made on full 9-bit fields.
If the given
data type is not
~-bit (TAl _ 0). then characters fro.
ClY-charD1) and C(Y-charnZ) are high-order zero filled.
All 9 bits of C(FILL) are used.
Instruction execution proceeds until
an inequality Is
found or the larger string length count is exhausted.
=
If HFk.RL
1. then Nk does not contain
length; instead.
it contains a re~ister
register holding the operand length.
the operand
code
for a
=
If HFk.ID
1. then the ~th word following the InstructIon
Word does not contain an Operand Descriptor;
instead. it
contains an Indirect Pointer to the Operand Descriptor.
Attempted
Fault.
executlon
with XED causes an Illegal Procedure
Attempted repetitIon with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, lY75
Z-187
RPT.
RPD.
or
RPL
ca~ses
an
AL39
EIS - ALPHANUHERIC COMPARE
120 (1)
Scan Characters Double
SCD
FORHATa
I 1
1 1
---11-1
-----1-8
0
a
I
J 0 0 000 0
o
0 0
o
MF2
I
I
120
I
11
J
I
222 3 3 3
D 1-LJ_L_ _ La q Q 1 L
J
J
I
01
2 Z 222
71
I
Y-charnl
J
I
I
Y-cha r o2
I
I
I
I
I
1
Y3
L -___
I
J
CN2 : 0
10 0
I
o
I
I
0 0 0 0 0 0 0 0 0 0
a
0
I
3
o
1 1
0 0 0 0 0 0 0 o IA 20
I
18
FIgure 2-14
71
Nl
I I
2 1
J
I
I
10 1
CN1 ITAlIOI
---1
1...--
J
HFl
---1-L
. I
I
J I
SI :
(1)
3
~
I
11 1
I
oI
2
I
12.
ot
I
151
REG
I
,. a
Scan Characters Double (SCD) [IS Multi-Word InstructIon Format
HF1
Modification Field for Operand Descriptor 1
"F2
Modification Field for Operand Descriptor 2
-I
Program Interrupt inhibIt bit
Y-charD1
Address of string
CNI
First character posItion of string
TAl
Data type of string
Nt
length of string
Y-charn2
Address of test character paIr
CN2
FIrst character posItion of test character pair
YJ
Address of compare count word
A
IndIrect via Pointer Register flag for Y3
REG
Register modifier for Y3
Al" Coding Formatl
scd
descna
descna
arg
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
( t1 F 1)
,
"'iF 2 )
Y-charnl[(CN1)].N1
Y-charn2 [ (CN2 ) J
Y3[,tagJ
2-188
n : 4, 0, or 9 (TA! : 2, 1, or
0)
n : 4, 0, or 9 (TA2 is ignored)
AL39
EIS -
SUMMARYI
= 1.
For 1
ALPHANUMERIC COMPARE
2 ••••• N1-1
.
C (Y-charnU 1-1. i
II
C CY-cha"'o2) 0,1"
On instruction completion
00 ••• 0 -> C(Y3'O.11
i
-> C(Y3'12.35
MODIFICATIONS'
None except AU. QU, AL. QL, or Xn 10r MF1 and REG
None except DU, AU, QU, AL. QL, or Xn for MF2
INDICATORS.
(Indicators not listed are not
Ta Ily
Runout
NOTES.
affecte~)
If
the string length count Is exhausted without a match.
or if N1 = 1, then ON; otherwise OFF
Botn the string and the test character pair are treated as
the data type given for the string, TAl.
The data type
given for the test character pai,... TA2, is ignored.
Instruction execution proceeds until
a character pair
match is found or the string length co~nt is exhausted.
If HFh.RL = 1.
then Nh does not contain
length; instead.
It contains a re~lster
register holding the operand length.
the operand
code for a
=
If HFh.ID
1, then the hth word follo~ing the Instruction
Word does not contain an Operand Descriptor; instead.
It
contains an Indirect PoInter to the Operand DescrIptor.
=
If HF2.IO = 0 and HF2.REG
DU. then the second word
following the Instruction Word does not contain an Operand
Descriptor for the test character pair;
instead,
It
contains the test character paIr as a Direct Upper operand
1 n bits D,17.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPD,
or
Scan Characters Double in Reverse
SCDR
RPl
causes
an
121 (1)
FORMAT a
Same as Scan Characters Double (SCD) (See Figure 2-14).
SUMMARY:
For I
= 1,
2, •••• N1-1
CCY-charn1)Nl-!-1.Nl-i
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-189
II
C(Y-charoZ'O,l
AL39
EIS - ALPHANUMERIC COMPARE
On instruction completion
00 ••• 0 -> C(YJ)O,11
1 -> C(Y3)12,35
HODIFICATIONSI
None except AU, QU, AL, QL. or Xn for HF1 and REG
None except DU. AU, QU, AL, QL, or Xn for HF2
INDICATORSI
(Indicators not lIsted are not
Tally
Runout
NOTES'
affecte~)
If the string length count Is eXhausted
or if N1 = 1. then aNi other~ise OFF
~ithout
a match,
Both the string and the test character pair are treate1 as
the data type given for the string, TAl.
The data type
given for the test character pair. TA2, Is ignored.
Instruction execution proceeds until
a character paIr
match is found or the string length co~nt is exhausted.
If HF~.RL = 1, then Nh does not contain
length; instead, it contains a re1ister
register holding the operand length.
the operand
code for a
=
If HF~.ID
1, then the ~th ~ord fo'Jo~ing the Instruction
Word does not contain an Operand Descriptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
=
0 and HF2.REG = OU, then the second ~ord
the Instruction Word does not contain an Operand
Descriptor for the fest character pair; instead, It
contains the test character pair as a Direct Upper operand
in bits 0.17.
If
HF2.tD
fol'o~ing
Attempted
Fau't.
execution
with XED causes an Illegal Procedure
Attempted repetition ~ith
Illegal Procedure Fault.
REVIEW DRAFT
SU8JECT TO CHANGE
October, 1975
2-190
RPT,
RPD,
or
RPL
causes
an
Al39
EIS - ALPHANUHERIC COMPARE
Scan with Hask
SCH
121t (It
FORHATI
o
0
I
I
D
011
1 1
--'O'~l
I
I
HASK
10 01
----La
a
L-
I
I
1
HFl
II
2 2 l 2
222 3 3 3
1 Z 3 !L.---L! 9 g 1 Z
.•
I
UI
124 ( 1)
---1
I
a I
I CNl I TAli 0 I
Y-cha r o1
I
I
Y-charn2
I
Nl
Y3
I
I
Z 1
121
o a 0 o
01
J
a
I
3
10 000 0 0 0 0 0 0
I
18
I
I
71
10 1
1 CN2 10 0 0 0 0 0 0 0 0 0
--1
Figure 2-15
HFI
,~
a
J
3
5
~-L
71
2
C)
l
I I
I
o I AI 0 01
_1
REG
J
I
I
11 1
151
2
I
It
Scan with Hask (SCH) EIS Hulti-Hord Instr.Jction Format
HASK
Comparison bit _ask
HFl
Modification Field for Operand Descriptor 1
-HF2
Modification FIeld for Operand Descriptor l
I
Program Interrupt inhibit bit
Y-charQ!
Address of string
CN1
First
TAl
Data type of string
Nl
Length of string
Y-charnl
Address of test character
CNZ
First
Y3
Address of compare count word
A
Indirect via Fointer Register flag for Y3
REG
Register modifier for Y3
position of string
cha~acter
cha~acter
position of test character
ALH Coding Format.
scm
descna
descna
arg
REVIEH DRAFT
SUBJECT TO CHANGE
October, 1975
(MF1),tMFZ){,mask(octalexpressiontJ
Y-charo1[(CN1)),Nl
D
It, 6. or 9 (TAL
Z. 1, or 0)
Y-charnZ(CNZ»)
D
It, 0, or 9 (TAZ is ignoredt
Y3[,tag)
=
=
2-191
=
AL39
EIS - ALPHANUHERIC COHPARE
SUMMARYI
For characters i :: 1, 2, ••• , Nt
For bits J :: 0, 1 ••••• 8
C(Z)) = -C(MAS)OI I.
(C(Y-char ol)i-1)J •
= 00 ••• 0,
If CeZ)o.,s
OO ••• D
->
(C(Y-cha r u2)1)1)
then
C(Y3)O,11
1 -> C(Y3)12,35
other~lse.
continue scan of CCY-charol)
HODIFICATIONS:
None except AU, QU, AL, QL, or Xn for HFl and REG
None except OU, AU, QU, AL, Ql. or Xn for MFZ
INDICATORSI
(IndIcators not
Tal'v
Runout
NOTES'
If
the
other~lse,
lis~ed
string
OFF
are not affectedt
length
count
exhausts,
then
ON;
Both the string and the test character are treated as
the
data
type given for the string, TAl.
The data type given
for the test character, TAl. is ignored.
Instruction execution proceeds until
a masked character
match Is found or the string length co~nt is exhausted.
MaSKing and comparision is
the
given data type is
characters from CCY-charnl)
zero filled.
AI. 9 bits of
done on ful I 9-bit fields. If
not 9-blt
(TA1 'I- 0), then
and C(Y-ch3rn2) are high-order
C(HASK) are used.
If MF1.RL = 1.
then N1 does not contain the operand
length;
instead,
It contains a re~ister code for a
register holding t~e operand length.
If HFh.ID :: 1, then the hth word follo~ing the Instruction
Word does not contain an Operand Desc-iptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
If HFZ.tD
=0
and MF2.REG :: DU,
the~
the second word
the Instruction Word does not contain an Operand
Descriptor for
the
test character; instead. it contains
the test character as a Direct Upper ooer~nd in bits 0,8.
folJo~ing
Attempted
execution
with XED causes an Illegal Procedure
Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-192
RPT,
RPD,
or
RPl
causes
an
AL39
EIS - ALPHANUHERIC COMPARE
Scan
~ith
Mask in
125 (1)
~everse
FORHAT'
Same as Scan with Mask (SCM)
SUHMARY'
For characters i
= 1,
= 0,
For bits
(See
2-15).
2, ••• , Nl
1, •••• 8
C(Z») = -C(HASK)J ,
«C(Y-charnl)Nl-i)] •
If CIZIO,8
Flgu~e
= 00 ••• 0,
(CCY-cha-n2)1»))'
then
00 ••• 0 -> C(Y3)O,11
i -> C(Y3)12.35
other~lse,
continue scan of
CCY-cha~n1)
MODIFICATIONS'
None except AU, QU, AL, QL, or Xn for ~F1 and REG
None except OU, AU, QU, AL, QL, or Xn for MF2
INDICATORS'
(Indicators not listed are not affected)
Tally
Runout
NOTES.
If
the
other~ise.
string
OFF
length
count
exhausts,
then
ON;
80th the string and the test character are treated as the
data type given for the string, TAl.
The data type given
for the test character, TAZ. IS ignorej.
Instruction execution proceeds until a masked character
match Is found or the string length co~nt is exhausted.
Masking and comparision is
the given data type is
characters from CCY-charD1)
zero filled.
All 9 bits of
done on full 9-blt fields.
If
not 9-bit (TAl _ 0), then
and CCY-ch3rnZ) are high-order
CCHASK) are used.
If
HF1.RL = 1,
then Nt does not contain the' operand
length; instead,
it contains a re;ister code for a
register holding the operand length.
If HF~.ID = 1, then the ht~ ~ord folloMing the Instruction
Word does not contain an Operand Desc-iptor;
instead, it
contains an Indirect Pointer to the Operand Descriptor.
=
If MFZ.ID = 0 and HFZ.REG
OU,
the~
the second word
follofting the Instruction Word does not contain an Operand
Descriptor for
the
test cha~acter; instead, it cont~lns
the test character as a Direct Upper oierand in bits 0,8.
Attempted
Fault.
execution
~ith
Attempted repetltion with
IllegaJ Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Z-193
XED causes an II legal Procedure
RPT,
RPO,
or
RPL
c~uses
an
AL39
EIS -
ALPHANUMERIC COMPARE
Test Character and Translate
TCT
161t (U
FORHAT.
o
11
o
o
22222
a
---L8
0
0 0 0 0 0 0 0 0 0 0 0 0 0
a
222333
3
1 2 LL_--L6.-L1LL2
5
I I
JI :
J
0 0J
1 () It (1)
~_L
I
I
I
I I
I CN1 JTAlIOI
Y-chara1
I
I
I
Y-char9Z
3
to 1
J I
________ ---L
1 I
-1_~
REG
______
S
I I
I
10 0 0 0 0 0 0 0 0 0 OIAJO 0:
~
REG
-1-LI__~;______- L
18
11 1
Test Character and Translate (TCT) EIS
Multi-Wo~d
2
It
Instruction Format
Hfl
Modification Field for Operand Descriptor 1
I
Program Interrupt inhibit bit
.Y-charnl
15
0 0 0 0 DIAIO 0:
I
Figure 2-1&
1
Nl
2 1
1000 0 0 0
Y3
I
.1
1
HF 1
Address of string
CN1
first character posItion of string
TAl
Data type of string
Nl
Length of strIng
Y-char92
Address of character translation table
Y3
Address of result Mord
A
Indirect via Pointer Register flag for YZ and Y3
REG
Register modIfier for Y2 and Y3
ALI1 Coding Fermat I
tct
descna
arg
arg
SUMHARYI
(MF1)
Y-charol[(CN1)1,Nl
Y-char9Z(,tag]
Y3[,tagl
For 1
m
= 1,
a
= It,
0, or 9 (TAl
= 2,
1, or 0)
2, ••• , N1
= C(Y-charol)i-l
If C(Y-charQ2)m-1
~
00 ••• 0,
then
C(Y-charQ2)m-l -> C(Y3)O,8
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-194
AL39
EIS - ALPHANUMERIC COMPARE
000 -> C(Y3)9,11
i -> C(Y3)ll,35
otherwise, continue scan of
C(v-cha~Q1)
MODIFICATIONS.
None except AU, QU, AL, QL, or Xn for HF1 and REG
INDICATORSI
(Indicators not listed are not affected)
Tallv
Runout
NOTES:
string
If
the
otherwise, OFF
length
count
exhausts,
then
If the data type of the string to be s:anned Is not
(TAl
~
0),
then characters frow C(Y-charQl)!
high-order zero filled in forming the table index, m.
ON;
9-bit
are
Instruction execution proceeds until
a non-zero table
entry is found or the string length co~nt is exhausted.
=
If HF1.RL
1, then Nl does not contain the operand
length; instead,
it containS a re~ister code for a
register holding the operand length.
=
If
HF1.ID
1,
then the first word following
the
Instruction Word does not contaln an Jperand Descriptor;
instead, it contains an Indirect Pointer to the Operand
Descriptor.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
TCTR
RPT,
RPD,
IIJegal
or
Test Character and Translate In Reverse
FORMATI
Same as Test Character and Translate (TeT)
(See Figure 2-16).
SUMHARYI
For i
m
= 1,
2, ••• , Nl
= C(Y-charnl)Nl-i
If C(Y-char92)m-1
~
00 ••• 0, then
C(Y-char92)m-l -> C(Y3)O,8
000 -> C(Y3)9,11
i
->
C(Y3)12,35
otherwise, continue scan of C(y-cha-nl)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-195
Procedure
RPL causes an
165 (1)
EIS - ALPHANUMERIC COKPARE
HOOIFICATIONSI
None except AU, QU, AL, Ql, or Xn for 1Ft and REG
INDICA TORSI
(IncHcators not listed are not affecte::U
fa Ilv
kunout
NOTESI
If the
strin9
otherwise, OFF
length
count
exhaus ts,
then
ON;
If the data type of the string to be scanned is not 9-bit
(TAl
~
0),
then characters fro~ C(Y-charnl)i are
high-order zero filled in forming the table index, m.
Ihstruction execution proceeds until
a non-zero table
entry is found or the string length COJnt is exhausted.
=
If HF1.RL
1, then Nl doeS not contain the operand
length; instead, it contains a re~lster code for a
register holding the operand length.
If
MF1.IO = 1,
then the
first word following the
Instruction Word does not contain an Operand Descriptor;
instead, it contains an Indirect Pointer to the Operand
Descriptor.
Attempted execution with XEO causes an
Fault.
Attempted repetitIon with
Illegal Procedure Fault.
RPT,
RPO,
II legal
or
Procedure
RPL causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-19&
AL39
EIS - ALPHANUHERIC "OVE
Hove Alphanumeric Left to Right
HlR
100
(1)
FORHATI
1 1
0 011
0
a-3
D
J J I
IT 101
FILL
______ LI
2 2 2 Z 2
r1F2
100 (1)
I
I
HF1
211
I
)
I
~
1-1
1
1 I
J CNZ aTAZI01
I
---1
18
3
I
10 1
1 CN1 ITAliO)
--1
Y-charn2
~
--1._L
I
71
Y-charol
3
<}
1 I
J
I
I
I
911
Figure 2-17
2 Z Z
--1-a._L.1-LLL_--L§.
II 1
71
I
Nt
I
I
1
tiZ
I I
2 1
12
1
Move Alphanumeric left to Right (MlR) EIS Hulti-Word
Instruction Format
FIll
FIll character for string extension
T
Truncation Fault enable bit
"F1
Hodification Field for Operand Descriptor 1
"F2
Hodification Field for Operand Descriptor 2
Y-chrnl
Address of sendIng string
CN1
First character position of sendIng st-Ing
TAl
Data type of sending string
N1
Length of sending string
Y-charo.2
Address of receiving string
CN2
First character pOSition of receiving strIng
TA2
Data type of receiving string
NZ
Length of receiving string
ALH Codlng Format:
mlr
descna
descna
SUMMARY I
(MF1) t (HF2) (, fill (o·etal expression)][ ,e"\abl efaul t 1
Y-charol(CN1)],Nl
n = ~, 0, or 9 (TAl: 2,1, or 0)
Y-cnarnZ(CNZ)],N2
D
4, D, or 9 (TA2
2, 1, or 0)
=
For i
= 1,
2, ••• , minimum (N1,N2)
CCY-charn1)l-1
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
=
->
Z-197
C(Y-charn2)i-1
Al39
EIS - ALPHANUMERIC MOVE
If Nt < NZ, then for i
C(FILl)
->
= Nl+l,
Nt+Z,
... ,
C(Y-charoZ)1-1
MODIFICATIONS.
None eKcept AU, QU, AL, Ql, or Xn for
INDICATORSI
(Indicators not listed are not affected)
Truncation
NOTESI
If N1
>
N2
~Ft
and MF2
NZ then ON; otherwise OFF
If data types are dissimilar (TAt ~ TA2), each character
Is high-order truncated or zero filled, as aopropriate, as
it is moved.
No character conversion takes place.
If
N1
>
NZ,
then (Nt-HZ)
trail lng Characters
C(Y-charol) are not moved and the Trun:ation indicator
set ON.
If Nt <
then FIll
moved to
place.
of
is
and TAZ = Z '~-bit data) or 1 (6-bit data),
are high-order truncated as they are
C(Y-charoZ).
No characte- conversion takes
N2
ch~racters
If N1 < NZ, C(FILl)D = 1, TAl = 1,
a,d TA2 = Z,
C(Y-charol)Nl is eKamined for a GBCD overpunch sign.
negative overpunch sign is found,
then the minus
character is placed in C(Y-charQ2)NZ; otherwise, a
Sign character is placed in C(Y-charoZ)NZ.
then
If a
sign
plus
If HF~.Rl = 1, then N~ does not contain the operand
length; instead, it contains a re~ister code for a
register holding the operand length.
If MFt1.IO = 1t then the 11th word following the Instruction
Hord does not contain an Operand Desc~iptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
ClY-charoi) and C(Y-charoZ) may be overlapping strings; no
check is made. ThiS feature is useful for replication of
substrings within a
larger string,
but care must be
exercised in the construction of the Jperand Descriptors
so
that
sendin~
string (C(Y-cha"'nU) data is not
inadvertently destroyed.
The user of string replication or overlaying is warned
that
the Decimal
Unit addresses the main store in
unaligned (not on 0 modulo 8 boundary) units of
Y-blockS
words an1 that the overlaved string (C(Y-charnZ)
is not
returned to m3in store until the unit of Y-block8 words is
filled or the instruction completes.
=
If T
1 and
the Truncation indicator is set ON by
execution of the instruction, then a Truncatio~ (OverfloM)
F au I t occurs.
Attempted
Fault.
REVIEW
execution
with XED causes an Illegal Procedure
2-198
Al39
OR~FT
SUBJECT TO CHANGE
October, lC375
EIS - ALPHANUMERIC HOVr
Attempted repetition with
Illegal Proce1ure Fault.
RPT.
RPD.
or
RPL
causes
101 (1)
Hove Alphanumeric Right to Left
HRl
FORHATJ
Same as Hove Alphanumeric Left to Right (HLR)
(See Figur~ z-11 ••
SUMMARYJ
For i
= 1.
an
2 ••••• minimum (N1.HZ)
C(Y-charnl)Nl-i
->
C(Y-charoZ)NZ-i
If Nl < NZ. then for i : Nl+l. HZ+1, •••• NZ
CCFILl)
->
C(Y-charnZ)NZ-i
MODIFICATIONS.
None except AU. QU. AL. QL, or Xn for
INDICATORSI
(Indicators not listed are not affected)
Truncation
-NOTES.
~Fl
and HF2
If Nl > NZ then ON; otherwise OFF
If data types are dissimilar (TAl ~ TAZ), each character
is high-order truncated or zero filled. as appropriate. as
it is moved.
No character conversion takes place.
If N1 > NZ. then (Nt-NZ) leading characters of C(Y-charnl)
are not moved and the Truncation indicator is set ON.
If Nl < NZ and TAZ = Z (4-bit data) or 1 (o-bit data),
then FILL characters are high-order tr~ncated as they are
moved to CCY-charoZ).
No characte~ conversion takes
place.
= 1, then Nh does not contain
length; instead. it contains a register
register holding the operand length.
If HFh.RL
the operand
code for a
If HFh.IO = 1, then the hth word following the Instruction
Word does not contain an Operand Descriptor; instead. it
contains an Indirect Pointer to the Operand Descriptor.
ClY-charo1) and C(Y-charnZ) may be ove~lapping strings; no
check is made. ThiS feature is useful for replication of
substrings within a larger string, but care must be
exercised in the construction of the Operand Descriptors
so that sending string (CeY-charol»
data
is
not
inadvertently destroyed.
The user of string replication or overlaying is warned
that
the Decimal Unit addresses tne main store
in
unaligned (not on 0 modulo 8 boundary) units of Y-blockS
words and that the overlayed string (C(Y-charnZ)
is not
returned to maln store until the unit of Y-bloc~8 words is
filled or the instruction completes.
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
2-199
AL39
EIS -
ALPHANUMERIC HOVE
=
If
T
1
and
the
Truncation
indicator
is set ON by
execution of the instruction, then a T~uncation (Overflow)
Fault occurs.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
RPT,
II legal
RPD,
or
RPL causes an
Hove Alphanumeric Edited
MVE
Procedure
020
(1)
FORHATI
0 0 1 1
000
012
J
I
10 0 I
~-1-D.
1
I
I
2 2 2 2 2
1 1
---L-8
LL
II 1 Z
I
KF2
I
020 (1)
ID 01
J
I
I
a
---1
71
1
7
I J
I 2
2
I
Y-charDl
I CNl HAlIOI
1---________________________
__
t
1 1
--1
a
I
J
I CN2 10
Y-char92
---1
J
I
I
Y-charn3
Move Alphanumeric Edited
5
9
10 1
7
Nt
J
01
I
t
t
I I
3
HFl
---1~
N2
S
a I
CN] ITA31DJ
181
Figure 2-18
o
]
~
I I
lit
HF3
I
J
2 2 2
7
2 1
N3
I
I
12
(MVE) EIS Hulti-Word Instruction Fermat
"Fl
Modification Field for Operand Descriptor 1
HF2
ModIfication Field for Operand DescrIptor 2
HF3
Modification Field for Operand Descriptor 3
I
Program Interrupt inhibit bit
Y-charn1
Address of sending string
CNl
First Character position of sending
TAl
Oata type of sending string
Nl
Length of sending string
Y-char92
Address of MOP control string
CN2
First character position of HOP control string
N2
Length of HOP control string
Y-charo3
Address of receiving string
st~ing
REVIEW DRAFT
SUB~ECT
TO CHANGE
October, 1975
2-200
AL39
EIS -
ALPHANUMERIC HOVE
CNl
First character position of receiving string
TA3
Data type of receiving string
N3
length of receiving string
ALH Coding Formatl
mve
descOa'
desc9a
descoa
SUMMARYI
(HFl), 01Fl) ,OtF3)
Y4 charol[(CN1)],Ni
Y-char92[(CN2)~,N2
Y-charn3[(CNl)],N3
C(Y-charol)
->
or 9 (TAl
= 2,
1, or 0)
4, 0, or 9 (TA3
= 2,
1, or 0)
o = 4, 0,
n =
C(Y-charol) under C(Y_cnar9l) HOP control
See -Micro Operations for Edit Instructions· later in
section for details of editing under M)P control.
thi~
HODIFICATIONSI
None except AU, QU, AL, QL, or Xn for 1F1, HFl, and HF3
INDICATORS:
None af fected
NOTESI
If data types are dissimilar (TAt ~ TA3), each character
of
e(Y-charOl) is high-order truncated or zero filled, as
appropriate, as it
is moved.
No c~aracter converSion
takes place.
If the data type of the receiving strl,g is not 9-blt (TAl
~
0),
then Insertlon Characters are nigh-orcer truncated
as they are Inserted.
The maximum string leng~h is 63.
The :ount fields Nl, N2,
and N3 are treated as modulo 64 numberi.
The instruction completes normally onlv if
N3
= minimuN
(Nl,N2,N3),
that is, if the receiving string is the first
to e~haust; otherwise, an Illegal Procedure Fault
occurs.
=
If
HFh.RL
1, then Nh does not contain the operand
length; instead,
it contains a register code
for a
register holding the operand length.
=
If HF~.IO
1, then the hth word follo~ing the Instruction
Word does not contain an Operand Desc~iptor;
instead. jt
contains an Indirect Pointer to the Operand Descriptor.
C(Y-charol) and elY-charoJ) may be ove~lapping strings; no
check is made.
This feature is useful for replication of
substrings within a
larger string,
but care must be
exercised in the construction of the )perand Descriptors
so
that
sending
. str Ing
(e (Y-cha~oU J data Is not
inadvertently destroyed.
The user of st~in~ replication or overlaving Is warned
that
the Decimal
Unit addresses the main store in
unaligned (not on 0 modulo 8 boundary) units of
Y-block8
words and that the overlayed st~ing (C(Y-chcrn3)) Is not
returned to m3in store untit the unit of Y-bloc~~ wores is
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-201
AL39
FORHATa
D 0 1 1
0
----G.~ 0
II
I
FIll
J
:
1
IT I 0:
_LI a
911
Y-char-01
Z 2 Z :3 3 3
1 Z 3 L----L_a. 9 a 1 z.
1 1
2 2 Z 2 2
l
Q
J
HF2
a
I
I
•
CN1 ITAll01
--1.
I I
J
J
I CNZ
t
Y-cha r o2
,
,
I
.
7
Nl
J
3
10 0 0 0
, ;
Z 1
o
--1.
1.8
Figure 2-19
10 1
NZ
ITAZIO:
181
Y-char93
HFl
J-L
----1
7:
.
• J
I I:
1&0 (U
I
I
1Z
I
0 0 0 0 0 D 1 AS 0 0:
_I I
I
11 1
2
Hove AJphanumer-ic with Tr-anslation (MVT)
Instruction Format
~IS
REG
..
Multi-Word
FIll
Fill character- for str-1ng extension
T
Truncation Fault enable bit
HF1
Modification Field for Operand Descr-iptor- 1
Hf2
Modification Field for Operand Descriptor Z
Y-charo1
Addr-ess 01 sending str-lng
eN1
First char-acter- position of sending st-lng
TAl
Oata type of sending string
Nl
len~th
Y-charo2
Address of r-eceiving string
CN2
First char-acter- position of receiving string
TA2
Oata type of r-eceiving string
NZ
Length of r-eceiving str-lng
Y-char93
Address of character translation table
DRAFT
SUBJECT TO CHANGE
October, 1975
3
:l
of sending string
R~vtEW
z-ZOZ
AL39
EIS - ALPHANUMERIC
A
Indirect via Pointer Register flag for Y-char93
REG
Register modifier lor
~OVE
Y-char~3
ALM Coding format.
IDvt
descna
descQa
a,..g
SUMMARY'
'HF1),(HFZ){,fill(octa.exp,..ession)](,e~ablefault)
n
n
Y-charnl[(CN1»),N1
Y-charn2[(CNZ));N2
Y-cha,..93t, tag]
Fo,.. i
m
= 1,
6, or 9 (TAl
6, or 9 (TAZ
= 2,
= Z.
1, or 0)
1, or 0)
2, •••• minimum (N1.HZ)
= C(Y-charn1)i-1
C(Y-char93)m-i
->
C(Y-charnZ)i-1
If Nl < NZ. then for i
11
= 4,
= 4,
= Nl+1.
N1+2 ••••• NZ
= C(F-ILL)
C(Y-char93)m-l
->
C(Y-cha"'n2Ji-1
MODIFICATIONS.
None except AU, QU, AL. QL, and Xn for HFI, "F2. and REG
INDICATORS'
(Indicators not listed are not
Truncation
HOTES.
If N1
>
affecte~)
H2 then ON; otherwise OFF
If the data type of the receiving fleld is not 9-Dit (TA2
0), then characters from C(Y-ch3r93) are high-order
truncated, as appropriate. as they areemoved.
~
If the data type of the sending field is not 9-bit (TAl _
0).
then characters from C(Y-charn1) are high-order zero
filled when forming the table index.
If N1 > HZ, then (Nl-N2J leading cha,..acters of C(Y-char-nl)
are ",ot moved and" the Truncat ion indicator is set ON.
II HFh.RL
length;
r~gister
If HFt:s..IO
=
1, then Nh does not c~nt~ln
instead, it contains a re~lster
holding the operand length.
the operand
code for a
=
1. then the 11th wo,..d 101l0llling the Instruction
Word does not contain an Operand Descriptor; instead, it
contains an Indirect Pointer to the Ope,..and Descriptor.
C(Y-charnl) and C(Y-charnZ) may be ove-lapping strings; no
Check is made. This feature is useful for repl.ication of
substrings within a larger string. 'but care must be
exercised in the construction of the Operand Descriptors
so that sending string (CIY-charal))
data
Is
not
inadvertently destroved.
The user
that the
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
of string replication or ~verJa~ing is wa~nea
Decimal Unit aadresses t'le main store
in
2-203
AL39
EIS -
ALPHANUHERIC HOVE
una.igned
(not
on 0 modulo 8 boundary) units of Y-blockS
words and that the overlayed string (C(Y-charn2)
Is not
returned to ~aln store until the ~nlt of Y-blockS words Is
filled or the instruction completes.
If T = 1 and the Truncation indicator is set ON bv
execution of the instruction, then a T~uncation (Overflow)
Fault occurs.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-204
RPT.
RPD.
It legal
or
Procedure
RPL causes an
AL39
EIS -
CHPN
NUMERIC COMPARE
303 (1 )
Compare Numeric
FORHATa
0
1 1
1 1
2 2 2 2 2
Q
--1--1.
--Lll
D l-Z..L4
o 0 0
0
0
o
J
0 0 0
I
I
I'tF2
I
o--L:
01
_ _ _ _ ---1
11
Y-charol
71
303
Figure 2-20
a
I
t1Fl
JI J
(1)
3
~
1_1
I
I
CNI la: 51:
I
I I
I
I
I
Y-cha r o2
222 3
La. 9 Q
I
10 L
SF1
I
I
I
I
I CN2 I b: 52.
I
I I
I
18
3 1
2
7
Nl
J
5F2
I
N2
I
{)
{)
Compare Numeric (CMPNt EIS Multi-Word Inst-uction Format
ItF1
Hodification Field for Operand Descriptor 1
.. HF2
Modification Field for Operand Descriptor 2
I
Program Interrupt inhibit bit
Y-charnl
Address of "'eft-hand" number
CNl
First character posItion of -'eft-hand- number
TN1
Data type of "Ieft-hand- nUMber
S1
Sign and decimal type of "Ieft-hand-
SFI
Scallng factor of "Ieft-hand- number
N1
Length of "Jeft-hand- number
n~mber
V-char-1l2
b
CH2
FIrst character positIon of -right-hand" number
TH2
Data type of
S2
Sign and decimal type of "right-hand- number
SF2
Scaling factor of "right-hand- number
N2
Length of "right-hand" string
-rl~ht-hand"
number
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-205
Al39
EIS - NUMERIC COMPARE
AlM Coding Formata
cmpn
descntfl,ls,ns,ts)
descnlfl,ls,ns,ts]
eMF1), eMFZ)
'(-charnU (CNU] ,N1,SFl
Y-cnaroZ { (C NZ» ], NZ, SFZ
o = It
= '+
o
II C(Y-charnZ) as numeric
or 9
or 9
SUMMARYI
CCY-charn1)
MODIFICATIONSI
None excDt AU, QU, Al, QI, or Xn for HF1 and HFZ
INDICATORS'
Clndicato~s
not
listed are not
~alue$
affecte~)
Zero
If C(Y-charn1)
= C(Y-charn2),
then ON;
other~ise
OFF
NegatIve
If C(Y-charn1)
> C(Y-charnZ),
then ON;
other~ise
OFF
Carry
If JC(Y-charn1)
I >
NOTESI
IC(Y-charo2):, then OFF, otherwise ON
Comparison is made on It-bit numeric v31ues contained in
eacn character of C'Y-char~).
If either given data type
is 9-blt
(TNh
D), characters from C(Y-char9~)
are
high-order truncated to '+ bits before comparison.
=
Sign characters are
located according to information in
CNh, S~, and N~ and interpreted as It-bit
fields;
9-bit
sign
characters
are
high-order
truncated
before
interpretation.
The sign character
15
(octall
is
interpreted
as a
minus sign;
all
other
legal sign
characters are interpreted as plus sig~s.
The positIon of
the decimal
determined from information In
point
CN~,
S~,
In
CCY-charD~)
SF~,
is
and Nh.
Comparision begins at the decimal position corrsponding to
the
first
digit of the operand with the larger number of
integer digits and ends ~ith the last jigit of the operand
with the larger number of fraction dIgits.
FOUr-bit numeric zeros are used to rep~esent digits to the
left of the first given digit of
the operand with
the
smaller number of integer digits.
Four-bit numeric zeros are used to rep~esent digits to the
right
of
the
I ast
given digit of the operand with the
sma'ler number of fraction digits.
Instruction execution proceeds until
an
ineQuality
found or the larger string length count is exhausted.
is
=
If
HFh.Rl
1,
then Nh does not contain the operand
length; instead,
it contains a register code
for a
register holding the operand length.
=
If HFh.ID
1, then the hth word followIng the Instruction
Word
does not contain an Operand Desc-iptor;
instead, it
contains an Indirect Pointer to the Ope~and Descriptor.
REV lEW OR ~FT
SUBJECT TO CHANGE
October. 1975
2-20&
AL39
EIS -
NUHE~IC
COMPARE
Detection of a character outside the r:tnge (0.11)
(octa"
in a digit position or a character outside the range
t12,171 (octal) in a s1gn position" causes an
Illegal
Procedure Fault.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-207
RPT,
~PD,
or
RPL
causes
an
AL39
EIS - NUMERIC HOVE
Hove Numeric
"VN
300 (1)
FORHATa
o 0
~
a 011
1 1
__________~8~~ _______ ~a
I
I J I
PIa 0 0 0 0 a a OITJRI
LJ
I
1
,
I
MFZ
I
J
71
1 1
V-charD!
________________________
---1: eN1
•I CN2
Y-charQ2
J
Jsn
•
a
b
Hove Numeric
(HVN)
3 .
2 2 2 J
D 1 Z J L-_La.-LIl
t J
UI
300 (1)
L
MF1
1_1
J
10 1
SF1
1
J
'a 1
I I
SlI
J I
Ibl
I I
S21
3 1
18
Figure Z-21
Z Z 2 Z Z
Nt
I
J
7.
I
J
I
I
-1I
SF2
NZ
J
I
Z
6
,
I
6
EIS MultI-Word Instruction Format
p
4-blt data sign character control
T
Truncation Fault enable bit
R
Rounding flag
HF1
Modification Field for Operand Descriptor 1
HF2
Modification Field for Operand Descriptor Z
1
Program Interrupt Inhibit bit
Y-charn1
Address of sending number
CN1
First character position of sending nUBber
TN1
Data type of sending number
Sl
Sign and decimal type of sending
SF1
Scaling factor of sendIng number
N1
Length of sending number
Y-charnZ
Address of receivIng number
CNZ
First character posItion of receiving number
TNZ
Data type of receiving number
S2
Sign and deCimal type of receiving
SF2
Scaling factor of receiving number
NZ
Length of receiving string
numbe~
num~er
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
Z-208
Al39
EIS - NUMERIC HOVE
ALH Coding ForMat.
mvn
descn(fl,ls,ns,ts)
desco(fl,ls,ns,ts)
(HF 1) , (MF Z) ( ,enab I e f au I t ) (,r:) und ]
Y-charnU (eNt)] ,,Nl,SFl
n = It or 9
Y-charn2((CNZ)],NZ,SFZ
0 = ~ or 9
SUHMARY
C(Y-charo1) converted and/or rescaled
MODIFICATIONSI
None except AU, QU, AL. QLt or Xn for HFl and HF2
INDICATORS.
IIndicators not listed are not affectej)
Zero
Negative
->
C{Y-charo2)
If ClY-charoZ) : decimal 0, then ON; otherwise OFF
If a minus sign character is moved
to
ClY-charaZ),
then
ON; otherwise OFF
Truncation
If low-order digit truncation
then ON; otherwise OFF
Overf I 0111
If fixed point integer overflow occurs, then ON;
unchanged. (See NOTES)
Exponent
Overflow
If exponent of floating point result exceeds +127,
ON; otherwise unchanged.
Exponent
Under' low
If exponent of floating point result
then ON; otherwise unchanged.
NOTES'
occurs
l~
without
less
rounding,
other"i~e
than
then
-128,
If data types are dissimilar (TN1 ~ TN2)t each character
is high-order truncated or filled, as appropriate, as it
is moved. The fill data used is "00011··b for digit
characters and "Oa01D N b for sign characters.
If TNZ and 5Z specify a 4-bit signed n~mber and 52 specify
a ~-bit signed number and P
1, then a legal plus sign
character in C(Y-charol) is converted to 13 (octal) as it
is moved.
=
If N2 is not large enough to hold the integer part of
CIY-charD1) as rescaled by 5F2, an overflow condition
exists;
the Overflo~ indicator is set ON and an Overflow
Fault occurs.
This implies that an unsigned fixed point
receiving fIeld has a minimum lengt, of 1 character; a
signed fixed point field, 2 characters; and a floating
point field, J characters.
If
NZ is not
large enough to hold atl the given digits of
CIY-charaU
as rescaled by 5F2 and R = Dt
then a
truncation condItion exists; data movement stops when
C(Y-charn2) is filled and the Truncation indicator is set
ON.
If R = 1, then the last di~it moved is rounded
according to the absolute value of the remaining digits of
C(Y-charol) and the instruction completes normally.
=
If HF~.RL
1,
then Nh does not contain
length; instead,
it contains a register
register holding the operand length.
REV lEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-209
the operand
code for a
EIS - NUHERIC HOVE
If HFh.IO = 1. then the 11th word following the Instruction
Word does not contain an Operand Descriptor; Instead. it
contains an Indirect Pointer to the Operand Descriptor.
CrY-charol) and C(Y-charo2) may be overlapping strings; no
check is made.
ThiS feature Is useful for rep' ication of
substrings within a
larger string. but care must be
exercised in the construction of the Operand Descriptors
so that sending string (C(Y-charol»)
data
is
not
inadvertently destroyed. Difficul ties may be encountered
because of seal in~ factors and the special
treatment of
Sign characters and floating point exponents.
The user of string replication or over laving is warned
that
the Decima' Unit aodresses t,e main store
In
unaligned (not on a modulo 8 boundary) units of Y-block8
words and that the overlayed string (C(Y-charOZ»
is not
returned to main store until the unit of Y-block8 words Is
filled or the instruction completes.
If T :
1 and the Truncation Indicator is set ON by
execution of the instruction. then a T~uncation (Overflow)
F au I t occurs.
Detection of a character outSide the range to,tll
(octal)
in a di~it position or a character outSide the range
{ll.17] (octal) in
a sign posItion causes an Illegal
Procedure Fault.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted repetition with
I11egal Procedure Fault.
RPT.
RPD,
or
RPl
causes
an
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
2-210
AL39
EIS -
HVNE
NUMERIC HOVE
Hove Numeric Edited
024 (U
FORHATa
o
0 0
0 0 1 1
1 1
--L1 Z
8~-11-1
-L~
I
I
J 0 01
;
I
J
2
2
I
I
10 01
HF3
I
I
-1.
71
I
Y-charn1
I
I
Y-char9Z
I
I
J
J
Y-charn3
L-
Figure 2-22
I
11Ft
1
---1_L
I I
10 1 I
CN1 : al SUD 0 0 0 0 OJ
11
CN2 I 0
I
t
I
o
I
J
Nt
71
1
I
I
01
2
0 0 0 0 0 0 01
N2
I
I
---1._--LL-l.
1.a
!2
J
HI
024 (1)
I
3
.•
J
HF2
Z
7
2 2 2
2 Z 2 2 2
D 1 Z 3 L---La. 9
I
1 J
.
CN1 ITA1IDIO
J
I
---1.
18
3
2 1
91
0 0 0 D 01
I
J
Nl
I
I
£>
I
£>
Hove Numeric Edited (I1VNE) EIS Multi-Word InstructIon Format
Hfl
Modification Field for Operand Descriptor 1
HFZ
Modification Field for Operand Descriptor 2
-Hf3
Modification Field for Operand Descriptor 3
I
Program Interrupt inhIbIt bit
Y-charD1
Address of sending string
CN1
First
TN1
Data type of sending string
S1
S1gn and deciaa' type of sending
N1
Length of senoing string
Y-char92
Address of MOP control string
CN2
First
H2
Length of HOP control strIng
Y-charo3
Address 01 receiving strlng
CN3
First character position of receiving string
TA3
Data type of receiving string
NJ
Length of receiving string
cha~acter
characte~
positIon of sending
st~ing
strin~
position of MOP control string
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
2-211
AL39
EIS - NUMERIC MOVE
AlH Coding Formata
mvne
desco(fl,ls,ns,ts)
desc9a
descOa
SUMMARY I
(MF1),(MFZ) ,(I1FJ)
Y-charnl((CN1) 1 ,Nl
Y-char92[ (CNZ) I,NZ
Y-c har n3[(CN31),N3
Q
= It
Q
=
or 9
It, 6, or 9
eeY-charn1) -> C(Y-charo3) under C(Y_cnarQ2) MOP control
See -Micro Operations for Edit Instructions· later in this
section for details of editing under H)P control.
MOOIFICATIONSa
None .except AU, QU, AL, QL, or Xn for "'Fl, HFZ, and MF3
INOICATORSi
None af 'ected
NOTESI
If data types are dissimilar (TAl _ TA3),
each character
of
C e Y-charoU is hi gh-order truncate d or zero f iI J ed, as
appropriaie, as it
is moved.
No chara~ter conversion
takes place.
If the data tvpe of the receiving stri~9 is not 9-bit (TA3
~
0),
then Insertion Characters are high-order truncated
as they are Inserted.
The maximum string length is 63.
The :ount fields Nl, N2,
and N3 are treated as modulo 61t numbers.
=
The instruction completes normally onl~ if
N3
minimum
(Nl,NZ,N3),
that is, if the receiving string is the first
to exhaust; otherMise, an Illegal Procedure Fault
occurs.
If
HF~.Rl
1,
then
N~
does not contain the operand
length;
instead,
it contains a re;ister code
for a
register holding the operand length.
=
If MF~.IO
1, then the hth Mord follo~ing the Instruction
Word does not contain an Operand Desc~lptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
C(Y-charni) and e(Y-charo3) may be ove~lapping strings; no
check is made.
This feature 1s useful for reDlication of
substrings within a
larger st~in9,
but care
must be
exercised in the construction of the )perand Descriptors
so
that
sending
string
(C'Y-cha~ni»
data
is not
inadvertentlv destroyed.
The user of string replication or overlaving is
warned
that
the Decimal
Unit addresses the main store
in
unaligned (not on 0 modulo 8 boundarv) units of
Y-block8
words and
that the overlayed string (e(Y-char-03}) is not
returned to main store untit the unit ~f Y-block8 words is
filled or the instruction comptetes.
Attempted execution with XED causes an
Fault.
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
Z-212
RPT,
RPD,
II legal
or
Procedure
RPL causes an
Al39
EIS - BIT STRING COMBINE
Combine Bit Strings left
CSl
0&0' (1)
FORHATI
o
o
0
II 1
0
I
a
IFIO 0 0 01
I
I
I I
111 2
0 0 1 1
-LL2 g
!LL_--A~_!l.-1
I
.
11
I
0&0 (1)
71
I
I
Cll
Y-bit2
B1
J
I
B2
I
I
J
1
I
C2 I
I
J
I
I
18
J
HF1
II'
-11
--1
Figure 2-23
~
I
I
I
3
Lll 9
!!
I
:
HF2
.. 1 1
Y-bit1
I
Z Z 2
~
a
I
BOlR I TID I
_--L-_ _LLI
2 2
2
.
10 1
7
N1
NZ
I
12
Combine Bit Strings left (CSL) EIS Multi-Word Instruction Format
F
FIll bit for string extension
BOlR
Boolean result control fIeld
Truncation Faul t er)ab Ie bi t
_T
"F1
Modification Field for Operand Descriptor 1
"F2
Modiflcation Field for Operand Descriptor 2
I
Program Interrupt inhibit bit
Y-bit1
Address of ·sending" string
Cl
First character position of "sending" string
81
First bit position of "sending- string
Nl
length of "sending- string
V-bitl
Address of "receiving" string
C2
First character position of "receiving- string
82
First bit position of "receiving-
N2
Length of "recelving" string
strl~9
AlH Coding Format:
csl
descO
descb
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1'375
(MF
1) ,
(HF 2) ( •
enab I e f au It] {, boo I (oct a I expres s ion) ) ( , f i
I I (011) )
Y-oit1[COITN01) l,NI
V-bit2[(BITN02)),N2
2-213
AL39
EIS-, BIT STRING COMBINE
SU"MARya
Fo~
1
= bits
1, Z, ••• , minimum (N1,NZ.
m : C(Y-bit1)1-1
C(BOLR)m
->
'1
C(Y-blt2)i-1
C(Y-bit2)i-1
If N1 < NZ, then
fo~
i
= N1+1,
Nl+Z, ••• , NZ
m = C(F) ,: C(Y-bltZ)i-1
CCBOLR)m
->
C(Y-bitZ)i-l
MODIFICATIONSI
None except AU, QU, AL, QL, or Xn
INDICATORSI
(Indicators not listed are not affectej)
=
Zero
If CCY-blt2)
Truncation
If Nl > NZ, then ON; otherwise OFF
NOTEsa
fo~
~Fl
and
~FZ
00 ••• 0, then ON; otherwise OFF
If N1 > NZ, the low order (Nl-NZ) bits of e(Y-bitl)
not processed and the Truncation indicator is set ON.
a~e
The bit pattern in C(BOlR) defines the Boolean operation
to be performed. Any of the sixteen possible Boolean
operations may be used. Some common Boolean operations
and their BOlR fields are shown below.
Qwu:a.1.lJul
C..Le.tlLBl
MOVE
0011
AND
0001
OR
0111
NAND
1110
Exclusive OR
0110
Clea~
0000
Inve~t
1100
If MF~.RL = 1, then N~ does not c)ntain
length; instead,
it contains a re~ister
reglste~ holding the operand length.
the operand
code for a
=
If HF~.IO
1, then the ~th word following the Instruction
Hord does not contain an Operand Descriptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
C(Y-bitl) and e(Y-bitZ) may be overlapping strings; no
check is made.
This feature is useful for replication of
substrings ~lthin a larger string, but care must be
exercised in the construction of the Jperand Descriptors
so
that
sending, string
(e(Y-bitl)
data is not
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-Z11+
AL39
(IS -
BIT STRING COMBINE
Inadvertently destroyed.
The user of string replication or ov!r'aying is warned
that
the Decimal
Unit
addresses the main store
in
unaligned (not on 0 modulo 6 boundary) units of
Y-blockS
words and
that
the overlaved strin1 (e(Y-bitZ)
is not
returned to main store until the unit of Y-block8 words is
filled or the instruction completes.
=
If T
1 and
the
Truncation indicator
is set ON by
execution of the instruction, then a T-uncatlon (Overflow)
Fault occurs.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted repetition with
Illegal Procedure Fault.
CSR
RPT.
RPD,
or
RPL
causes
061 (1)
Combine Bit Strings RIght
FORHAT:
Same as Combine Strings Left (CSL)
SUMMARYI
For i
= bits
an
(See Figure 2-Z3).
1. Z, •••• minimum (N1.NZ)
m = C(Y-bltl)Nl-i 1. C(Y-bitZ)NZ-l
C(BOLR)m -> C(Y-bitZ)NZ-l
If N1 < N2, then for i
m
= C(F)
= N1.1.
Nl.Z •••• , NZ
I: C(Y-bltZ)NZ-i
C(BOLR)m -> C(Y-bitZ)NZ-i
MODIFICATIONSI
None except AU.QU, AL, QL, or
INDICATORSI
(Indicators not listed are not
Zero
If CIY-bitZ)
Truncation
If N1
NOTESI
>
= 00 ••• 0,
~n
for
H~1
and HFZ
affecte~)
then ON; otherwise OFF
NZ, then ON; otherwise OFF
If N1 > N2. the high order (N1-NZ) biti of
C(Y-bit1)
not processed and the Truncation indicator is set ON.
are
The
bit pattern in C(BOLR) defines t~e Boolean operation
to be performed.
Any of
the sixteen possible
Boolean
operations may be used~
See NOTES u~der Combine Strings
Left (CSL) instruction for examples of BOLR.
=
If HF~.RL
1,
then N~ does not contain
length; instead,
It contains a re~ister
register holding the operand length.
REVIEW OR'FT
SUBJECT TO CHANGE
October. 1975
2-Z15
the
operand
code
for
a
AL39
EIS - BIT
~TRING
COM8INE
=
If HFh.ID
1, then the ~th word folJo~lng the Instruction
Word does not contain an Operand Descriptor; instead, it
contains dn Indirect Pointer to the Op~rand Descriptor.
C(Y-bit1) and C(Y-bit2) may be ove-Iapping strings; no
check is made.
This feature is useful for replication of
substrings within a larger string, but care· must be
exercised in the construction of the )perand Descriptors
so
that
sending
string
(ClY-bit1»
data is not
inadvertently destroyed.
The user of string replication or overlaying is warned
that
the Decimal
Unit addresses the main store In
unaligned (not on 0 modulo 8 boundary) units of Y-block8
words anj that the overlayed strin1 (C(Y-bitZ)
is not
returned to main store until the ~njt Jf Y-block8 words is
filled or the instruction completes.
=
If T
1 and the Truncation indicator is set ON by
execution of the instruction, then a T~uncation (Overflow)
Fault occurs.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted repetition with
Illegal Procedure Fault.
R~VIEW DRAFT
SUBJECT TO CHANGE
October, 1915
Z-21&
RPT,
RPD,
or
RPL
causes
an
AL39
EIS - BIT STRING
Compare BIt Strings
CMPB
CO~PARE
006 (1)
FORHATa
o 0
001 1
Q 1
I I
I FlO
----A-i~_1
I
I
I
000 0 0 0 OaTIOI
____
.LL
1 1 1 2
________ __1_8
I
HF2
71
J
I Cll
V-bitl
I
I
I
I
3
3
_ ___1_~~9__________~5_
I I
066 (1)
II J
HF1
~
--1_L
10 1
Bl
-1--,_____
I
J
2 Z 2
2 2
1 ____________
~I_1-l
8 1 1
11
9 0
7
Nl
I
N2
_________ ----1_-..a.I _____-.l.S____________
....L
V-bit2
I C21
18
Figure 2-24
82
2
,.
12
Compare Bit StrIngs (CHPB) EIS Multi-Word Instruction Format
f
Fill bit for string extension
T
Truncation Fault enable bit
~"fl
Modification FIeld for Operand Descriptor 1
"fZ
Hodification Field for Operand Descriptor Z
I
Program Interrupt inhibit bit
Y-bitl
Address of -left hand" string
Cl
First character positIon of "left hand- string
B1
First bit position of "left hand"
Nl
Length of -left hand" string
Y-blt2
Address of "right hand u string
C2
First character position of "right
82
First bit position of "right hand
HZ
Length of "right hand" string
stri~g
u
ALH Coding Formata
cmpb
descb
descb
SUMMARV.
REVIEW DRAFT
SUBJECT TO CHANGE
Oct 0 b er , 1975
(MF1).(MF2)[.enablefault)[,flIICDll)]
V-bitl[(BITN01»).N1
V-blt2[(BITN02»),N2
For 1
= 1,
2, ••• , minimum (Nl,N2)
2-217
han~-
strlng
string
EIS - BIT STRING COMPARE
C(Y-bltlJi-l :: C(Y-bltZ)i-l
If N1 < NZ. then for 1
= N1+1.
Nl+Z • •••• HZ
C(FILU :: C(Y-bitZH-l
If NZ < NZ. then for 1 = NZ+1. N2+2, •••• N1
C(Y-bitl)l-l :: C(fILl)
HODIFICA TIONS:
None except AU. QU. Al, Ql. or Xn for
INDICATORS:
(Indicators not listed are not affected)
= C(Y-bltZ)i
~F1
and HF2
Zero
If CtY-bit1)'
otherwise. OFF
Carrv
If e(Y-bit1)l < C(Y-bitZ)! for anr i. then OFf;
otherwise ON
NOTES:
for all i. then ON;
Instruction execution proceeds untit
an ineQual i ty
found or tne larger string length count is exhausted.
is
If HF~.RL = 1. then N~ does not contain the operand
length; instead. It contains a register code for a
register holding the operand length.
=
If HF~.ID
1. then the ~th word follo.lng the Instruction
Word does not contain an Operand Desc~iptor; Instead. it
contains an Indirect Pointer to the Operand Descriptor.
Attempted
Fault.
e~ecution
with XEO causes an
Attempted repetItion with
Illegal Procedure Fault.
RPT.
RPD,
Illegal
or
Procedure
RPl causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-216
Al39
EIS - aIT SfRIHG SET INDICATORS
-£IS SZTL
.au.:~1c.ln!L-S!U.-I.~~~
06 .. (1)
Set Zero and T~uncatlon Indicators
with Bit Strings Left
FORMAT.
Same as Combine Strings left ICSl) (Sea Figure 2-23).
SUMMARYI
For i
m
= bits
1. 2 •••••
= C(Y-bit1)i-l
If CCBOLR)m
If Nt
m
<
~
I: CCY-bitZ)i-l
0, then terminate
HZ, then for
= C(F)
II
If CCBOLR)m.
(Nl.NZ)
minimu~
i
= Nt+1,
N1+l • ••• , HZ
CCY-bitl)l-l
~
0, then terminate
MODIFICATIONS'
None except AU. QU, AL. QL, or Xn for
INDICATORS.
(Indicators not listed are not affected)
~Fl
and HFl
Zero
If CCBOLR)m = 0 for alJ i . then ON; otherwise OFF
Truncation
If N1
NOTES.
>
NZ. then ON; otherwise OFF
If Nt > HZ, the low order (N1-NZ) bits of CIY-bitt)
not processed and the Truncation indicator is set ON.
are
The execution of thiS instruction is identical to Combine
Strings Left (CSL) except that C(BOLRJ~ is not placed into
C(Y-bi t2)1-1.
The bit pattern in C(BOLR) defines the Boolean operation
to be performed.
Anv of the sixteen possible Boolean
operations may be used. See NOTES under Combine Strings
Left (CSl) instruction for examples of aOLR.
=
If HFt.Rl
1. then N~ does not contain the. operand
length; instead, it contains a register code for a
register holding the operand length.
=
If MFh.ID
1. then the hth "o~d following the Instruction
Word does not contain an Operand Desc~iptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
If T
=1
and
the
Truncation
Indicator
execution of the instruction, then a
Fau I t occurs.
Attempted
Fault.
execution
Z-219
T~uncation
set
ON
bV
(Overflow)
wIth xto causes an I I legal Procedur-e
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
is
RPT,
RPO.
or
RPL
causes
an
EIS -
BIT STRING SET INDICATORS
Set Zero and T~uncation Indlcato~s
with Bit Strings Right
SZTR
FORMATa
Same as Combine Strings Left (CSL)
SUMMARY'
Fo~
1
m
= bits 1, 2, ••••
= C(Y-bit1)N1-i II
If ClBOLR)m
~
= C(F)
J
minimum CN1.N2)
C(Y-bitZ)N2-i
= N1+1,
N1+2, ••• , NZ
J elY-hi t2)N2-i
If C(BOLR)m
exce~t
(See Figure 2-23).
0, then terminate
If Nt' < N2, then for i
m
065 (t)
~
0, then terminate
MODIFICATIONS'
None
AU, QU, AL, QL, or Xn for HF1 and HF2
INDICATORS'
(Indicators not listed are not affectej)
Zero
If C(BOLR)m = Q for all i, then OH; otherwise OFF
Truncation
If Nt > N2. then ON; otherwise OFF
NOTES'
If Nt > N2, the low order (N1-HZ) bits
of
CrY-bitt)
not processed and the Truncation indicator is set ON.
are
The execution of this instruction 15 identical to Combine
Strings Right (CSR) except that C(80L~)m is not
placed
into C(Y-bitZ)N2-i.
The bit pattern in C(BOLR) defines t~e Boolean operation
to be performed. Any of
the sixteen possIble
Boolean
operations may be used.
See NOTES under CombIne Strings
Left (CSL) instruction for examples of BOLR.
MF~.Rl = 1,
then N~ does not contain
length;
instead.
It contains a re~ister
register holding the operand length.
If
the operand
code
for a
If HFh.ID = 1, then the 11th wo~d follo",lng the Instruction
Hord does not contain an Operand Descriptor;
instead,
it
contains an Indirect Pointer to the Ope~and Desc~lptor.
If
T = 1 and the Truncation
indicator is set ON by
execution of the instruction, then a T~uncation (Overf low)
Fault occurs.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
II legal
or
Procedure
RPL causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-220
Al39
EIS - DATA CONVERSION
~Ol
Binary to Decimal Convert
8TO
(1)
FORMATa
'0 0
o
I
I
IPao o
,
1 1
o 1
I
1
I
0 0 0 0 0 0 0 01
I
I
11
10
J I
a
301 (1)
---1
,
71
CN1 : 0 0
J
.
J
J
I
1
I
18
o
~
7
8 10 1
J
0 0 0 0 0 01
N1
I
3 1
NZ
__ ____________
I
~J
Z
6
6
Binary to Decima' Convert (BTD) EIS Hulti-Word Instruction
For~at
4-blt data sign character control
P
a
HF1
HI
----1-L-__________
I
91
I CN2 J a J 5210 0 0 0 0 0 I
Y-charn2
Figure 2-25
2 Z 233
I
HF2
Y-char11
I
I
Z Z Z 2 2
1 1
______~5_
Q 1 Z
-La__~~~~3_~---Z-~~9_D~
... ttF1
Modification Field for Operand Descriptor t
HF2
Modification Field for Operand Descriptor 2
I
Program Interrupt inhibit bit
Y-charCJ1
Address of binary number
CNt
first character position of binary numDer
Ni
Length of binary number In characters
Y-charnZ
Address of decimal number
CN2
First character position of decimal nuwber
TNZ
Data type of decimal number
S2
Sign and decimal type of decimal
NZ
Length of decimal number
numbe~
ALH Coding Formatl
btd
desc9ns
desco(ls,ns,tsl
SUMMARYI
REVIEW OR~T
SUBJECT TO CHANGE
October, 1975
(I1FU,U1F2)
Y-char91(CN1»),N1
Y-charnZ(CNZ»),NZ
C(Y-char,)1) converted to deciMal
Z-ZZl
D.
->
= 4 or
«)
C(Y-CharnZ)
AL3CJ
EIS - DATA CONVERSION
MODIFICATIONS I
None except AU, QU, Al, Ql, or Xn for
INDICATORS:
(Indicators not listed are not affectej)
Zero
Negative
If C(Y-charn2)
NOTESa
ad HF2
D, then ONI otherwise OFF
If a minus sign character is moved
ON;
Overflow
= decimal
~Fl
to
C(Y-chara2),
then
otherwise OFF
If fixed point integer overflow occurs, then ON;
unchanged (See NOTES)
other~lse
C(Y-char91) contains a two·s complement binary integer
aligned on 9-blt character boundaries with length 0 < Nl
<= 8.
=
If TN2 and S2 specify a 4-bit signed nJmber and P
1,
then if C(Y-char9i) is posltive (bit 0 of C(Y-char91)D =
0), then the 13 (octal) plus sign character is moved to
C(Y-charnZ) as appropriate.
The scaling factor of CCY-charQ2), SF2, must be O.
If
N2 is not large enough to h3'd the digits of
C(Y-char91) an overflow condition exists;
the pver"ow
indicator is set ON and an Overflow Fault occurs. This
implies that an unsigned fixed point receiving field has a
1 character and a Signed fixed point
minimum length
field, 2 characters.
0'
=
If HF~.RL
1, then Nh does not contain the operand
length; instead, 1t contains a re~ister code for a
register holding the operand length.
=
If MFh.IO
1, then the ~th word follo~lng the InstructIon
Word does not contain an Operand Oesc~iptor; instead, it
contains an Indirect Pointer to the Operand Descriptor.
C(Y-char91) and C(Y-charn2) may be overlapping strings; no
check is made.
Attempted conversion to a floating poi~t number (S2 = 0)
or attempted use of a scaling factor (SF2 ~ D) causes an
Illegal Procedure Fault.
If Nl
=0
or N1 > 6 an IJ JegaJ Procedure FauJt occurs.
Attempted execution with XED causes an
II legal
Procedure
F au I t .
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-222
RPT,
RPD,
or
RPL causes an
Al39
EIS - OATA
DTB
CONVERSIO~
Decimal to Binary Convert
305 (1)
FORHATa
0
1 1
D
_11-1
I
I0 0 0 0 0 0
o
J
I
I
J
0 0 0 01
I
11
2 2 2 Z Z
1 1
J
I
HFZ
305
Y-cha~nl
I
I J
J1
MFt
J
I
N1
I
N2
I
I
J
J
2
I
J
3
t
I
7J
61
I 0 0 0 0 0 0 0 0 01
----1.
8
,
&
9
Decimal to Binary Convert (OTB) EIS Hultl-Word Instruction Format
Jsu
HFl
Modification Field for Operand Descriptor 1
HFl
Modification Field for Operand Descriptor Z
I
Program Interrupt inhibit bit
• V-charIll
a
~
---1_1
CN2
Y-cha~9Z
Figure 2-l&
3
J I
1
10 1 I
CN1 J a 1 SUO 0 0 0 0 01
---L
:
I
I 1
III
(1)
I
71
LI
J
2 Z 2 3
-LL-D 1 Z L L - _ L ' 3 D
Address of decimal number
CNt
First
TNl
Data type of decimal number
S1
Sign and decimal type of decimal
N1
length of decimal number
Y-charlll
Address of binary number
CN2
First
H2
length of binary number in
cha~acter
cha~acte~
position of decimal
position of
nu~ber
numbe~
bina~y
num~er
cha~acters
ALH Coding Formatl
dtb
descn[ls,ns,tsl
desc9ns
(HF 1) , U1F 2 )
Y-charn1[ (CN1)l,Nl
Y-char92((CNZ)],NZ
Q
-=
SUMMARY I
C(Y-charn1) converted to binary
MODIFICATIONSI
None except AU, QU, AL, Ql, or Xn for
INDICATORS:
(Indicato~s
not
->
it or 9
C(Y-char9Z)
~Fl
ad HF2
listed are not affected)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-223
AL39
EIS -
DATA CONVERSION
= 0,
Zero
If C(Y-char9Z)
Negative
If a minus sign character is found
ON;
otherwise OFF
Overflow
If fixed point integer overflow occurs,
unchanged (See NOTES)
NOTES.
then ON: otherwise OFF
in
C(Y-charn1),
then
then ON; other",ise
C(Y-char9Z) "'ill contain a two·s complement binary integer
aliJned on 9-bit character boundaries with length 0 < HZ
<= 8.
The scaling factor of e(Y-charD1), SF1, must be O.
If N2 is not large enou~h to hold the converted value of
e(Y-charD1)
an overflow conoition eKists;
the Overflow
indicator is set ON and an Overflow Fa~lt occurs.
=
If
HF~.aL
1,
then N~ does not contain
length; instead.
It contains a register
register holding the operand length.
the operand
code
for
a
If HFh.IO = 1, then the hth word following the Instruction
Word does not contain an Operand Oescri ptor;
Inst"!ad, It
contains an Indirect Pointer to the Operand Descriptor.
C(Y-charn1) and C(Y-char9Z) may be overlapping strings; no
check is made.
Attempted conversIon of a
floating point number (S1
or attempted use of a scaling factor (SF1 _ 0)
causes
Illegal Procedure Fault.
If
N2
=0
Attempted
Fault.
or NZ
~
an
8 an Illegal Procedure Fault occurs.
execution
with XED causes 3n I I legal Procedure
Attempted repetItion with
Illegal Procedure Fault.
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
= 0)
2-22"
RPT.
RPO,
or
RPL
causes
an
AL39
EIS -
-us -
DECIHAL ADDITION
Oec4ma..L.A~Wlil
20l (1)
Add Using 2 Decimal Operands
ADZD
FORHATa
J
PID
o
1 1
0 011
§ 2 Il 1
J I
0 0
-LJ.
•
0 0 0 o 0 OJTJRJ
Z a.
t1Fl
LL-L-
I
~
P
-T
a
_---1
,
I
I
I
a CN1 2 a I S11
I I
I
J
1
3
l
D
2
I
HF1
I
I
I
10 1
SFI
I
I
4)
1 I
tIl
20l (U
I
Y-charnl
Figure 2-l1
2 Z l
D 1 Z 3 L..---L8
J
J
11
1 1
Y-cha r n1
1
2 2 2 2 2
71
I
I
Nl
I
I
I
I
SFZ
CN2 J b I S21
J
I
I I
18
3 1
2
I
I
I
I
N2
I
I
£»
£»
Add Using 2 Decimal Operands (AOlO) EIS t1ulti-Word
Instruction Format
4-bit data sign character control
Truncation Fault enable bit
R
Rounding flag
HFl
Modification Field for Operand Descriptor 1
HFZ
Hodification Field for Operand Descriptor l
I
Program Interrupt inhibit bit
Y-charn1
Address of augend (ADlD),
(HPlD), or divisor (OVlD)
CN1
First character position of augend (AOZD), minuend (5820),
mu'tipicand (HPlO), or divisor (DVlO)
TN1
minuend
Data type of augend (A02D), minuend
_ (HP20), or dl vi sor (OVlO)
(SB20),
(SB20),
S1
Sign and decimal type of augend (AOlO),
multiplicand (HPZO), or divisor (OVlO)
SF1
Scal ing
factor
of
augend
(ADlO),
multiplicand
multiplicand
minuend
minuend
(SB20),
(S8l0) ,
multiplicand (HPlO)9 or divisor (OVlO)
N1
Length of augend
(ADlD),
(MPlOI, or divisor (OVlO)
V-charol
Address of
addend and sum
(AOlO),
subtrahend
and
difference (S820)9
multiplter and product
(HPlO), or
dividend and Quotient (OV20)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Z-225
minuend
(S820),
multiplicand
ALl9
EIS - DECIHAL ADDITION
b
CH2
First character position of addend and sum
IADlO),
subtrahend and difference (S8l0), multiplier and prOduct
(HP2D), or divIdend and Quotient (OVlD)
TH2
Data
type of
addend and sum
(A020),
subtrahend and
difference
(SB20),
multiplier and product
(HP2D),
or
dividend and QuotIent (OV20)
S2
Sign and decimal type of addend and su~ (AD20), subtrahend
and difference (Sa20). multiplIer and product
(HP20), or
dividend and quotient (OV20)
SF2
Scaling factor of addend and sum
(AD2D),
subtrahend and
dIfference
(SB20),
multiplier and product
(HP20). or
dividend and Quotient (OVlO)
H2
Length of addend and sum (ADlO), subtrahend and dIfference
(SB20), multiplier and product
(HP20),
or dividend and
quotIent (OVlO)
AlH Coding Format.
ad2d
descn(fl.ls,ns,tsl
descn(f •• ls,ns,ts)
CHF1),(MFl)[,enabJefault]{,rDundJ
'Y-charnl[(CN1)},N1,SFl
n
4 or 9
Y-cha r oZ[CCNl)],Nl,SF2
n
4 or 9
=
=
SUMMARY.
CtY-charnl) + CCY-charnl) -> CCY-charn2)
MODIFICATIONS.
None except AU, QU, AL, QL, or Xn for
INDICATORS'
(Indicators not
~F1
and "F2
listed are not affected)
= decimal
Zero
If CCY-charn2)
Negative
If CCY-charnZ) is negative, then ON; otherwise OFF
Truncation
If the truncation condition exists without rounding,
ON; otherwise OFF (See NOTES)
Overflow
If the overflow condition
unChanged (See NOTES)
Exponent
Overflow
If
exponent of
floating
ON; otherwise unchanged.
Exponent
If exponent of floating point result
Underflow
then ON; otherwise unchanged
NOTESI
0, then ON; otherwise OFF
exists,
point
then
res~lt
is
ON;
then
otherwise
exceeds 127 then
less
than
-128
=
If TN2 and S2 specify a 4-bit Signed n~mber and P
1,
then
the 13
(octal)
pluS Sign c,aracter is placed
appropriately if the result of the ope~ationis positive.
If
N2 is not large enough to hold the integer part of the
result as scaled by SF2,
an overflow condition exi5ts;
the Overflow
inulcator is set ON a~d an Overflow fault
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-22&
AL39
EIS - DECIMAL ADDITION
occurs.
This implies that an unsigned fixed
point
receiving field has a minim~m lengt~ of 1 character; a
signed flKed point field, 2 characters; and a
floating
point field, 3 characters.
If N2 is not large enough to hold all the digits of the
result as scaled by SF2 and R
0,
then a truncation
condition exists; data movement stops when C(Y-charnZ) is
filled and the Truncation indicator Is set ON.
If R
1,
then the last digit moved is rounded according to the
aDsolute value of the remaining digits of the result and
the instruction completes normally.
=
=
If HF~.RL = 1, then Nh does not contain the operand
len1th; instead,
it contains a register code for a
register holding the operand length.
=
If HFh.ID
1, then the hth word following the Instruction
Word does not contain an Operand Descriptor;
instead, it
contains an Indirect Pointer to the Oparand Descriptor.
C(Y-charnl) and C(Y-charn2) may be
check is made.
If T
ove~lapping
strings; no
=1
and the Truncation indicator is set ON by
of the instruction, then a Truncation (Overflow)
Fault occurs.
executio~
Detection of a cnaracter outSide the ~ange [0,111 (octal)
in a digit posItion or a character outside the range
[12,17) (octal) in a Sign position causes an II legal
Procedure Fault.
Attempted execution w1th XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
RPT,
RPO,
II legal
or
Procedure
RPl causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
2-227
AL39
EIS -
DECIMAL ADDITION
222 (1)
Add Using 3 Decimal Operands
A030
FORHAT.
0 0 0
~
fI
I
I I
I P 10 I
1 1
----Lfl
0 D 1 1
-'L1_Z-
J I
HF3
I I I
11 1
a 1.
I
IT I RI
•I
71
I
V-charo2
2
I
.T
a
: CN2 :b
521
10 1
SF1
7
N1
I
I
I
I
I
531
SF2
N2
I
I
CN3 :c
I
I
18
3 1
V-charo3
P
I
511
I
a
MFl
tIl
---1_1
CNI la
I
Js..u
1 1
I
I
I
Figure 2-28
3
~
222 (1)
J
L-
I
I
2 2 2 3
D l....L.LL-_LLL.Il
I
HF2
I I
1 1
V-charo1
I
2 2 2 2 2
J
I
SF3
I
N3
I
2
6
6
Add Using 3 Decimal Operands CAD30) [IS Hulti-Word
Instruction Forqat
4-bit data sign character control
Truncation Fault enable bit
R
Rounding flag
I1F1
Modification Field for Operand Descriptor 1
J1F2
Modification Field for Operand Descriptor 2
I1F3
Hodification Field for Operand Descriptor 3
I
Progra_ Interrupt inhibit bit
V-chara1
Address of
(MP3D», or
au~end
dl~isor
(AD30),
(OV3D)
minuend
(SB30),
multiplicand
CN1
First character position of augend (AD30), minuend (5830),
multiplicand (MPlD), or divisor COV30)
TN1
Data type of augend (A030), minuend
(MP30), or divisor (OVlO)
51
Sign and decimal type of augend (AD30),
multiplicand (HPlO), or divisor (OV30)
SF1
Scaling factor of
augend
(A030),
multlplicand (HP30), or divisor (OV30)
N1
Length of
augend
(ADlO),
(HPJO), or divisor (OV30)
Y-charo2
Address of addend CAD30), Subtrahend
(HP30), or dividend (OV30)
REVIEW DRAfT
SUOJECT TO CHANGE
October, 1975
2-228
minuend
(S930),
multiplicand
minuend
minuend
(SB30),
(5930),
(5830),
(5830),
multiplicand
multiplier
AL39
Eli - DECIMAL ADDITION
b
CN2
First character position of addend
(AOlO),
(5830), multiplier (HP30), or divIdend (OV30)
subtrahend
TN2
Data type of addend (AOlO), suDtrahend (S9l0),
(HPJO), or dividend (OV30)
~ultiplier
S2
Sign and decl_al type of addend (A030), subtrahend
multiplier (HP30), or dividend (OVlO)
(SB~O),
SFZ
Scaling factor of
addend (A030), subtrahend
multiplier (HPlO), or dividend (DV30)
(S830) ,
N2
Le~gth
(HP30"
a
of addend (ADlO), subtrahend
or dividend (OVlO)
(S830),
multiplIer
Y-charDl
Address of sum (AD30), difference (S8l), product
or Quotient (OV30)
CNl
First character position of sum (ADlO), difference (S830),
product (HPlO), or Quotient (OV3D)
TNl
Data type- of sum
CA03D),
(HP30), or Quot ient (OVlD)
S3
Sign and decimal type of sum (A030),
product (HPlD), or quotient (OVlO)
SFl
Scaling factor of sum (AOlO), differen:e
U1P30), or Quot ient (DVlO)
(S830),
product
Length of su. (AD30), difference (S830),
or Quotient (OVlO)
product
(HP3D),
'"Nl
dlfferen::e
(HP30),
(S8l0),
product
difference
(5830),
ALH Coding Format.
ad3d
oescn[fl,ls,ns,tsl
descn[fl,ls,ns,ts]
descQ[fl,ls,ns,ts]
(HF11,U1FZ) ,HtF3)(,enablefault](,roundl
Y-charnl((CN1)l,N1,SF1
a. It or 9
Y-enarnZr (CNZ)],N2,SF2
o It or C)
Y-charn3[(CN3)],Nl,SFl
o
It or C)
=
=
=
SUHHARYI
C(Y-charn1) + C(Y-charo2) -> C(Y-charn3)
HODIFICATIONSI
None except AU, QU, AL, QL, or Xn for
INDICATORSI
(Indicators not
list~d
~F1
and HF2
are not affected)
Zero
If e(Y-charn3)
= decimal
Negative
If C(Y-charo3)
is negative, then ON; otherwise OFF
Truncation
If the truncation condition exIsts wlt,out rounding,
ON; otherwise OFF (See NOTES)
Overflow
If the overflow condition
unchanged (See NOTES)
Exponent
Overflow
If
exponent
of
ON;
other~ise
unchang~d.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
0, then ON; otherwIse OFF
floating
2-229
exists,
point
then
ON;
then
otherwise
resJlt exceeds 127 then
ALlCJ
EIS -
DECIMAL ADDITION
Exponent
Underflow
NOTES.
If exponent of floating point result
then ON; otherMise unchanged
is
less
than
-128
If TN3 and S3 specify a ~-bit signed n~mber and P = 1,
then
the 13
(octal)
plus sign character is placed
appropriately if the result of the ope~ation is positive.
If
S3 specifies fixed point and N3 is not large enough to
hold the integer part of the result as scaled by SF3, an
overflow condition exists;
tne Overflow indicator is set
ON and an Overflo~ Fault occurs.
ThiS
implies
that an
unsigne~
fixed poInt receiving fIeld has a minimum length
of 1 character;
a Signed fixed point field, Z characters;
and a floating point field, 3 characte~s.
If N3 is not large enough to hold all the
digits of
the
result as scaled by SF3 and R
D, then a truncation
condition exists; data movement stops ~hen C(Y-charn3)
is
filled
and the Truncation indicator is set ON.
It R
1.
then the last digit moved is rounded according to
the
absolute ·value of the remaining digits of the result and
the instruction completes normally.
=
=
=
If HF~.RL
1,
then Nh does not contain
length;
instead,
it contains a re~ister
register holding the operand length.
the operand
code
for a
=
If HFh.ID
1, then the hth Mord fo"o~ing the Instruction
Word does not contain an Operand Descriptor;
instead, It
contains an Indirect POinter to the Operand Descriptor.
CCY-charnlt,
C(Y-charnZ),
and
C(Y-charn3)
overlapping strings; no check is ~ade.
may
be
=
If T
1 and
the Truncation indicator
is set ON by
execution of the instruction, then a Truncation (Overflow)
Fault occurs.
Detection of a character outside the -ange (0,111 (octal)
in a digit position or a character outside the range
(12,17] (octal) in a sign positio~ causes an II 'e9al
Procedure Fault.
Atte~pted
execution with XED causes an
Illegal
Procedure
Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1q75
2-230
RPT,
RPO,
or
RPL causes an
AL39
EIS - DECIHAl SU9TRACTION
Subtract Using 2 Decimal Operand~
S820
203 (1)
FORHAT.
Same as Add Using 2 Decimal Operands (A020)
(See Figure 2-27).
SUMMARYI
CCY-charn1J - C(Y-charnZ)
HODIFICATIONS.
None except AU, QU, At, Ql, or Xn for HFl and HFZ
I ~ DICA TORS:
(Indicators not listed are not affected)
= decimaJ
->
CCY-charnZ)
Zero
If C(Y-charaZ)
Negative
If CCY-charnZJ is negative, then ON; otherwise OFF
Truncation
If the truncation condition exists witnout rounding,
ON; otherwise OFF (See NOTES)
Overflow
If the overflow condition
unchanged (See NOTES)
Exponent
Overflow
If exponent of floatIng
ON; otherwise unchanged.
Exponent
Underf I ow
If exponent of floatIng point result
then ON; otherwise unchanged
NOTES.
0, then ON; otherwise OFF
exists,
point
then
res~'t
is
ON;
then
otherwise
exceeds lZ7 then
less
than
-128
=
If TNZ and S2 specify a 4-bit Signed n~mber and P
1,
then
the 13 (octal) plus Sign c~aracter is placed
appropriately if the result of the operation is pOSitive.
If N2 Is not large enough to hold the integer part of the
result as scaled by SF2, an overflow condition exists;
the Overflow indicator is set ON and an Overflow Fault
occurs.
This implies that an unsigned fixed
point
receiving field has a minimum lengt~ of 1 character; a
signed fixed point field, 2 characteri; and a float1ng
pOint fIeld, 3 characters.
If NZ 1s not large enough to hold all the digits of the
result as scaled by SFZ and R = O. then a truncation
condition exists; data movement stops when CCY-charnZ) is
filled and the Truncation indicator is set ON. If R
1.
then the last digit moved is rounded according to the
=
absolute value of the remaining dlgits of the
the instruction completes normally.
~esult
and
If HFh.RL = 1, then N~ does not contain the operand
length; instead, it contains a register code for a
register holding the operand length.
If MFis,.IO = 1, then the 11th wo~d following the Instruction
Word does not contain an Operand Oesc~iptor; instead. it
contains an Indirect Pointer to the Operand Descriptor.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-Z31
Al39
EIS - DECIMAL SUBTRACTION
C(Y-charnl) and C(Y-cnarn2) may be
check is made.
ove~lapping
strings; no
=
If T
1 and
the Truncation indicator
i~
set ON bv
execution of the instruction, then a Truncation (Overflow)
F au I t occurs.
Detection of a character outside the -ange (0,11] (octal)
in a dIgit p~sition or a character outside the range
(12,17]
(octa')
in a sign posltiort causes an II legal
Procedure Fault.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
RPT,
Illegal
RPO,
or
Procedure
RPL causes an
223 (1)
Subtract Using 3 Decimal Operands
S830
FORHAT'
Same as Add Using 3 Decima' Operands (lD30)
(See Figure 2-28).
SUMMARY'
C(Y~charQl)
"'MODIFICATIONS.
INDICATORS:
-
CIY-charn2) -> C(Y-charn3)
None except AU, QU, Al, Ql, or Xn for HF1 and HF2
(Indicators not listed are not affected)
= decimal
0, then ON; otherwise OFF
Zero
If C(Y-charn3)
NegatIve
If C(Y·charn3) is negative, then ON; otherwise OFF
Truncation
If the truncation concition exists without rounding,
ON; otherwise OFF (See NOTES)
Overflow
If the overflow condition
unchanged (See NOTES)
Exponent
Overflow
If
exponent of
floating
ON; otherwise unchanged.
Exponent
Underflow
If exponent of floating point result
then ON; otherwise unchanged
NOTES.
exists,
point
then
ON;
then
otherwise
result exceeds 127 then
is
less
than
-128
=
If TN3 and 53 specify a ~-bit Signed n~mber and P
1,
then
the 13 (octal)
plus Sign character is placed
appropriately if the result of the operation is positive.
If
S3 specifies fixed poInt and N3 is not large enough to
hold the integer part of the result as scaled bv SF3,
an
overflow condition exists;
the Overflow indicator is set
ON and an Overflow Fault occurs.
Thii
implies that
an
unsigned fixed point receiving field has a minimum le~gth
of 1 character;
a signed fixed point field, 2 characters;
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-232
EIS - DECIMAL SUBTRACTION
and a
floating point
field, 3
cha~acte-s.
If N3 is not large enouJh to hold al' the
digits
of
the
result
as scaled
by SF3 and
R
0, then a truncation
condition exists; data movement stops ~hen C(Y-charn3)
is
filled
and the Truncation indicator is set ON.
If R
1,
then the last digit moved
is rounded according
to
the
absolute value of the remaining digits of the result and
the instruction completes normal Iv.
=
=
If HF~.Rl = 1,
then N~ does not contain
length;
instead.
it contains a re~ister
register holding the operand length.
the
operand
code
for
a
=
If Hfh.IO
1, then the ~th word fol'o~ing the Instruction
Word does not contain an Operand Descriptor;
instead,
It
contains an Indirect Pointer to the Op~~and Descriptor.
C(Y-charn1),
ove~lapping
C(Y-cha~D2),
st~ings;
and
C(Y-charn3t
no check is made.
may
be
=
If T
1 and
the
Truncation indicator
is set
ON by
execution of the instruction, then a T~uncation (Overflow)
Fault occurs.
Detection of a character outside the ~ange [0,11] (octal)
in a digit position
or a character outside the range
(12,171 (octal) in a sign position causes an II'legal
Procedure Fault.
Attempted execution Mith XED causes an
Fault.
Attempted repetitIon with
Illegal Procedure Fault.
RPT,
RPD,
Illegal
or
Procedure
RPL causes an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-233
AL39
EIS - DECIMAL MULTIPLICATION
Hultiplv Using 2 Decimal Operands
HP2D
ZO& (1)
FORHAT.
Same as Add Using 2 Decimal
(See Figure 2-27).
SUHMARYI
C(Y-charn1) x C(Y-charn2)
MODIFICATIONSI
None except AU, QU, AL, QL, or Xn for
INDICATORS:
(Indicators not listed are not affected)
= decimal
->
O~erands
(~OZD)
ClY-charQ2)
~Fl
and HF2
Zero
If C(Y-charn2)
NegatIve
If ClY-charn2) is negative, then ON; otherwise OFF
Truncation
If the truncation condItion exists wltnout rounding,
ON; otherwise OFF (See HOTES)
Overflow
If the
0, then ON; otherwise OFF
overflow condition
(See NOTES)
exIsts,
then
ON;
then
otherwise
unch~nged
Exponent
Overflow
If exponent of floating
ON; other~ise unchanged.
Exponent
Underf I OM
If exponent of floating point result
NOTES:
point
res~lt
is
exceeds 1Z7 then
less
than
-128
then ON; otherwise unchanged
=
If TNZ and S2 specify a 4-blt signed number and P
1,
then
the 13 (octal) plus si~n character is placed
appropriately if the result 01 the ope~ation is positive.
If N2 is not large enough to hold the integer part of the
result as scaled by SF2, an overflow condition exists;
the Overflow indicator is set ON a,d an Overflow Fault
occurs.
This implIes that an unsigned fixed
point
receiving field has a minimum lengt, of 1 character; a
Signed fIxed point field, 2 characters; and a floating
poInt field, 3 characters.
If NZ Is not large enough to hold all the digits of the
result as scaled bv SF2 and R
0, then a truncation
condItion exists; data movement stops when C(Y-charnZ) is
filled and the Truncation indicator is set ON. If R
1,
then the last digit moved is rounded acco~din9 to the
=
=
absolute value of the remaining digits of the
the instruction completes normativ.
result
and
If MFh. RL = 1,
then N,h does not con t at n the operand
length; instead, it contains a register code for a
register holding the operand length.
If MFh.ID = 1, then the 11th wor-d tollollling the Instr-uction
Word does not contain dn Operand Oesc~iptor; instead, it
contain~ an Indirect Pointer to the Ope~and Oescr-iptor.
REVIEW OR~FT
SUBJECT TO CHANGE
Oct ober, 1975
Z-234
AL39
EIS -
C(Y-charnl) and C(Y-charoZ) may be
check is made.
DE~IHAL
MULTIPLICATION
ove~lapplng
strings; no
=
If T
1 and the Truncation indicator is set ON bV
execution of the instruction. then a T~~ncation (Overflow)
Fault occurs.
Detection of a character outside the ~ange [0,111 (octal)
in a digit position or a character outside the range
[12,17l (octal) in a sign positio"\ causes an Illegal
Procedure Fault.
Attempted execution with XED causes an
Fault.
Attempted repetition ~ith
Illegal Procedure Fault.
RPT,
Illegal
RPO,
or
Procedure
RPL causes an
Multiply Using 3 Decimal Operands
MP3D
2Z&
FORHAT:
Same as Add USing 3. Decimal Operands (A030)
(See Figure 2-28).
SUMMARY:
eIY-charnl) x ClY-charoZ) -> eIY-charn3)
MODIFICATIONS:
None except AU, QU, AL. QL, or Xn for NFl and HF2
INDICATORS:
(Indicators not listed are not
= decimal
affecte~)
Zero
If C(Y-charn3)
Negative
If C(Y-charn3) is negative, then
Truncation
If the truncation condition exists
ON; otherwise OFF (See NOTES)
Overflow
If the overflow condition
unchanged (See NOTES)
.Exponent
Overflow
If exponent of floating
ON; otherwise unchanged.
Exponent
Under f low
If exponent of floating point result
then ON; otherwise unchanged
NOTESI
(1)
0, then ON; otherwise OFF
~N;
wit~out
exists,
point
otherwise OFF
then
res~lt
is
roundlng,
ON;
then
otherwise
exceeds 127 then
less
than
-1Z8
=
If TN3 and S3 specify a ~-bit Signed number and P
1,
then
the 13 (octal) plus Sign cnaracter is placed
appropriatelv If the result of the operation Is positive.
If
S3 specifies fixed point and N3 is not 1arge enough to
nold the integer part of the result as scaled bv SF3, an
overflow condition exists; the Overflow indicator Is set
ON and~n Overflow Fault occurs.
ThiS
implies that an
unsigned fixed point receiving field "\as a mInimum length
of 1 character; a Signed fixed point field, 2 characters;
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-235
AL39
EIS - DECIMAL MULTIPLICATION
and a floating point field, 3
characte~s.
If N3 is not large enou:,Ih to hold all- the digits of the
resuJt as scaled by SF3 and R
0, then a truncation
condition exists; data move~ent stops ~hen C(Y-charn3) is
filled and the Truncation indicator is set ON. If R = 1,
then the last digit moved is rounded according to the
dbsolute value of the remaining digits of the result and
the instruction completes normally.
=
If "F~.RL = 1, then Nh does not contain
length; instead, it contains a register
register holding the operand length.
the operand
code for a
=
If HF~.ID
1, then the hth word 'olto~ing the Instruction
Word does not contain ~n Operand Descriptor; instead, It
contains an Indirect Pointer to the Operand Descriptor.
C(Y-charn1),
C(Y-charnZ),
and
C(Y-charo3)
overlapping strings; no check Is made.
may
be
If T = 1 and the Truncation Indicator is set ON by
execution of the instructIon, then a Truncation (Overflow)
F au I t occurs.
Detection of a character outsIde the range [0,11] (octal)
in a digit position or a character outSide the range
l1Z,171 (octal J in a sign positio'\ causes an It legal
Procedure Fault.
Attempted execution with XED causes an
Fault.
Attempted repetition with
Illegal Procedure Fault.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-Z3&
RPT,
RPD,
Illegal
or
Procedure
RPL causes an
AL39
EI5 - DECIHAL DIVISION
Divide Using Z Decimal Operands
DVZO
227 (1)
FORHAT.
Same as Add Using 2 Decimal Operands (AD20)
(See Flgu~e 2-27).
SUMMARY.
C(Y-charn2) I
e(Y-charn1) -> C(Y-charn2)
HODIFICATIONS:
None except AU. QU. AL, QL, or Xn for
INDICA TORS:
(Indicators not listed are not affected)
?)
~F1
and HF2
Zero
If C(Y-charnZ)
= decimal
NegatIve
If C(Y-charnZ'
is negative. then ON; otherwise OFF
Truncation
If the truncation condition exIsts wit"out rounding.
ON; othe~wise OFF (See NOTES)
Overflow
If the
Exponent
Overflow
If exponent of
floating
ON; otherwise unchanged.
Exponent
Under f' ow
If exponent of floating point result
NOTES,
0, then ON; otherwise OFF
overflow condition
unchanged (See NOTES)
eKists.
point
then
res~lt
is
ON;
then
otherwise
exceeds tZ7 then
less
than
-128
then ON; otherwise unchanged
This instruction performs contInued long diviSion on the
operands until
it
has produced enough output digIts to
satisfy the requirements of
the ~uotient
field.
The
number of required Quotient digits.
NQ, is determined
before divISion begins as follows •••
1)
F I oat I ng point
QUO
Hent
=
NQ
N2. but if
the divisor is greater than the
dividend after operand alignme~t9 the leading zero
digit produced is counted and the effective precision
of the result is reduced by one.
2)
Fixed point Quotient
NQ
= (N2-LZ2+1)
wherel
NO
LZn
En
SF2
3)
-
(Nt-LZl) + (E2-E1-SF2)
operand field length
= 3iven
leading zero count for operand
= exponent
of opera"d 0
= scaling factor
of Quotient
=
Roundin~
If rounding is specified (R
Quotient digit is produced.
REVIEW DRAFT
SUBJECT TO CHANGE
Oct ober. 1975
D
2-237
=
1),
then
one
extra
AL39
EIS -
DECIHAL DIVISION
=
If
C(Y-charo1)
decimal 0 or NQ > 63, then division does
not take place, C(Y-charoZ) are unchan~ed,
and a
Divide
Check Fault occurs.
=
If
'TNZ ~nd S2 specify a ~-bit signed number and P
1.
then
the. 13
(octal)
plus sign character is
placed
appropriately
if the result of the operation is positive.
If NZ is not large enough to hold the inteJer part of
the
result as scaled bv SF2, an overflow condition exists;
the Overflow indicator is set ON
and an Overflow
Fault
occurs.
This
implies
that an unsigned
fixed point
receiving field has a minimum length of
1 character;
a
Signed fixed
poInt
field,
2 Characters; and a floating
point field, 3 characters.
If N2 Is not large enough to hold all the digits 01 th~
result as scaled by SFZ and R
0, then a truncatIon
condition exists; data movement stops ~hen C(Y-charo2)
Is
filled
and the Truncation indicator is set ON.
If R
1,
then the last digit moved is rounded according
to
the
absolute value of
the extra Quotient
digit and
the
instruction completes normallv.
=
=
If
=
HF~.RL
1,
then Nh does not contain
length;
instead,
it contains a re~ister
register holding the operand length.
the operand
code
for a
=
If HFt1.ID
1, then the hth word follolflng the Instruction
Word does not contain an Operand Descriptor;
instead,
it
contains an Indirect Pointer to the Operand Descriptor.
CCY-charn1) and C(Y-charnZ) /lay be overlapping strings; no
check I s made.
If
T = 1 and the Truncation indicator
is set ON by
execution of the instruction, then a Truncation (Overf 10M)
Fault occurs.
Detection of a character outside the r3nge [0.,11)
(octal)
in a
digit
position or a
character outside the range
[12,171 (octal) in a Sign pOSition causes an Illegal
Procedure Fault.
Attempted
Fault.
execution
with XED causes an Illegal Procedure
Attempted reDetltion with
Illegal Procedure Fault.
DV3D
RPT,
RPD,
or
Divide Using 3 Decimal Operands
FORHATa
Same as Add Using 3 Decimal Operands (AD3D)
(See Flgure 2-28 ••
SUHHARYI
C(Y-charn2) I
REVIEW OR"rr
SUBJECT TO CHANGE
Oc tober, 1975
RPL
causes
an
227
(1)
e(Y-charn1) -> C(Y-charo3)
2-238
AL39
EIS -
DECIMAL DIVISION
MODIFICATIONSI
None except AU, QU, AL. QL. or Xn for HF1 and HF2
INDICATORSI
(Indicators not
listed are not affected)
Zero
If C(Y-charn3)
= decimal
Negative
If C(Y-charn3)
is negative, then ON; otherwise OFF
Truncation
If the truncation condItion exists witnout rounding,
ON; otherwise OFF (See NOTES)
Overflow
If
Exponent
Overflo.
ON; otherwise unchanged.
Exponent
Underflow
If exponent of floating point result
then ON; otherwise unchanged
NOTESI
0, then
the overflow condition
unchanged (See NOTES)
If
exponent
of
floating
~N;
exists,
point
otherwise OFF
then
res~lt
is
ON;
then
otherwise
exceeds 127 then
Jess
than
-128
ThIs instruction performs continued lo~g division
on
the
operands until
it
has
produced eno~gh output digits to
satisfy the requirements of
the Quotient
field.
The
number of reQuired Quotient digits,
NQ, is determined
before diviSion begins as follows •••
1)
Floating point quotient
=
NQ
N3, but if
the divIsor Is
greater than the
dividend
after
operand a'ignme~tt the leading zero
digit produced is counted and the effective precision
of the result Is reduced by one.
2)
Fixed point quotient
= (N2-LZ2+1) - (N1-LZ1) + (E2-El-5F3)
wherel
= given operand field lengfh
NQ
NQ
LZn
EO
SF3
3)
= leading zero
= exponent of
count for operand 0
n
= scaling factor of quotient
opera~d
Rounding
If rounding is specified (R
quotient digit is produced.
=
1),
then
one
extra
=
If
C(Y-charn1)
decimal 0 or NQ > 03, then division does
not take place, C(Y-charn3) are unchanged,
and a
Divide
Check Fault occurs.
=
If
TN3 and 53 specify a 4-bit Signed number and P
1,
(octal)
plus sign character
is
placed
then
the
13
appropriatelv
if the result of the operation is positi~e.
If 53 specifies fixed point and N3 Is ~ot large enough
to
hold
the
integer part of the result as scaled bV SF3, an
overflow condition exists;
the O~erfJlw indicator Is set
ON and an Overflow Fault occurs.
This implies that an
unsigned fixed point receiving field has a minimum
length
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-239
AL39
EIS -
DECIHAL DIVISION
of 1 character;
a signed fixed point field, 2 characters;
and a floating point field, 3 characte-s.
It N3 Is not large enough to ho1d aJ I the digits of the
result as scaled by SF3 and R
0,
then
a truncation
condition exists; data movement stops when C(Y-charn3) is
filled and the Truncation indicator is set ON.
If R
1,
then
the
last digit
moved is rounded according to the
absolute value of
the extra Quotient
digit
and
the
instruction completes normally.
=
=
=
If
HFh.RL
1, then Nh does not contain the operand
length;
instead,
it contains a re~ister code
for a
regl~ter holding the operand length.
=
If HF~.ID
1, then the ~th word follo~ing the Instruction
Word does not contain an Operand Desc-lptor;
instead, it
contains an Indirect Pointer to the Operand Descriptor.
CCY-charo1),
CCY-charo2),
and
C(Y-charn3)
overtapping strings; no check Is made.
may
be
=
If
T
1 and the Truncation indicator
is set ON by
execution of the instruction, then a T~uncation (Overflow)
Fault occurs.
Detection of a character outside the r3nge (0.111
(octal)
in a
digit
positIon or a
charact_~ outside the range
t12,17l (octal) in a Sign position causes an
II legal
Procedure Fault.
Attempted
FauJt.
eKecution
with XEO causes 3n Illegal Procedure
Attempted repetItion with
Illegal Procedure Fault.
RPT,
RPD,
or
RPL
causes
an
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-2~a
AL39
The
Hove Alphanumeric Edited
(HVE) and Hove Numeric Edited
(HVNE)
instructions require micro operations to perform the eaitlnl
functions
in an
efficient manner.
The sequence of micro operation steJS to be executed is
contained in storage and is referenced by the second operand descriptor of
the
HVE
or HVNE
instructions.
Some
of
the micro operations require special
characters for insertion into the string of characters being edited.
These
special characters are shown in the "Edit Insertion Table" discussion below.
H~ro
Opeca~~Segyenca
The micro operation string operand descriptor points to a string of 9-bit
characters that specify the micro operations to be performed during an edited
move.
Each of
the 9-blt characters defines a micro o~eration and has the
followIng formata
0
_LI
I
0 0
0
~
~
!i
I
I
HOP
;
I
5
figure 2-29
E~it
I
IF
2
I
4
Hicro Operation (HOP) Character Format
HOP
5 bit code specifying Micro Operation to be perfomed.
IF
Information Field containing one of the following •••
Insertion
1.
A sending string character count. A
Interpreted as 16.
0
is
2.
The index of an entry in the edit insertion table
be used. PermIsslble values are 1 through 8.
to
3.
An int erpretat ion of the ieb I ank-w,en-zero·
value
of
operat ion
T~
~hlle
executing an edIt instruction, the Processor provides a register of
eight 9-bit characters to hold insertion information.
This ~egister. called the
-Edit
Insertion Table~,
is not
maintained after execution of
an
edit
instruction.
At the start of' each edit instructIon, the Processor hardware
initializes the table to the values given in Table 2-8, where each symbol refers
to the corresponding standard ASCII character.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-241
AL39
Table 2-8
Default Edit Insertlon Tab.e Characters
TaDle Entrv
--1:Uulltu:c. __
~c:.ilUe.C
bl
1
2
3
ank
•
•
it
5
£»
S
7
•
8
0 (zero)
One or all of the table entries can be changed bv the Load Table Entrv
the Change Table micro operations to provIde different insertion characters.
The hardware provides the following four -edIt
operations.
flags~
or
for use by the micro
ES
End Suppression Flag; initiallv OFF and set ON by a
operation when zero suppressIon ends.
micro
SN
Sign Flag; initially set OFF If the sending string Is
aJphanumericor unSigned numeric. If the sending string
is signed numaric, the sending string sign character is
tested and SN is set OFF If positive, and ON if negative.
Z
Zero Flag; initially set ON. It Is set OFF whenever a
sending string character that is not decimal zero is moved
into the receiving strIng.
8Z
Blank-When-Zero Flag; initially set OF~ and is set ON by
either the ENF or SES micro operation.
If,
at the
completion of a move, both the Z anj BZ are ON,
the
receiving string is filled with cha-acter 1 of the Edit
Insertion Table.
The micro operations are terminated normally when the receive string length
becomes exhausted. The micro operations are terminated abOrmally (with an
Illega'
Procedure Fault) if a move from an exhausted sendi"lg string or the use
of an exhausted HOP string Is attempted.
REVIEW DRAFT
SUBJECT TO CHANGE
Dc to ber, 1<375
Z-2ltZ
AL39
The hardware executes HVNE in a slightly different manner than it executes
This is due to the inherent differences In which nume-ic and alphanumeric
data
is handled.
The
following
are brief descriptioni
of
the hardware
operations for HVNE and HVE.
"VEe
-NUMERIC EOITi}
1.
Load the entIre sending string number (maximum length 63 characters)
Into the Decimal
Unit Input
Buffer as It-bit digits (high-order
truncating 9-bit data).
Strip the sign and exponent cha~acters
(if
any),
put
them aside into special holding registers and decrease the
Input Buffer count accordinglv.
2.
Test sIgn and, If reQuIred, set the SN f'ag.
3.
Execute micro
4.
If an Edit Insertion Table entry or HOP insertion character is to be
stored, MANDed",
or ·ORed" into a receiving string of 4- or 6-bit
characters, high-order truncate the character acco~dlngly.
5.
If the receIving string
operatl~n
strIng, starting with first
fft-bit) digit.
is 9-bit characters,
high-order fill
the
(4-bit)
digits
from the Input Buffer with bits 0-4 of character 8 of
the Edit
InsertIon Table.
If
the receiving string
Is
6-blt
characters, high-order fill the dIgits with "DO-b.
-ALPHANUMERIC
EOIT~
1.
Load Cecimal Unit Input Buffer with sending string characters.
Oata
is read from main store in unaligned units (not 0 modulo 8 boundary)
of V-blockS words. The number of characters read is the minimum of
the remaining sending string count, the remaining receiving string
count. and 64.
2.
Execute micro operatIon string,
string character.
3.
If an Edit Insertion Table entry or HOP insertion character is to be
stored, "ANDed-,
or MORed" into a receive string of 4- or 6-blt
characters, hlgh-oroer truncate the character acco~dinglv.
starting
with
tne
first
receiving
t11cro Operators
A description of the 17 micro operations
(HOPs)
follo~s.
The mnemonic,
name,
octal value, and the function performed is given for each HOP in a format
similar to that for Processor Instructions.
These micro ope-at Ions are included
in the alphabeItc list of instructions in Appendix C.
identified bv the code
HOP.
Checks for termInation are made during and after each micro operation.
All
HOPs
that make a zero
test of a sending string characte- test onlv the four
least significant bits of the character.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-2'+3
AL39
The fol lowing addltional
descriptions of the HOPs.
abbreviations
and
symbols
are
EIT
Edit Insertion Table
pin
current position in the sending string
pmop
current posItion in the micro operation string
pout
current posItion in the receiving string
CHT
used
in
Change Table
SUMMARY I
21
For 1 = 1, 2, ••• , 8
CCY-char92)pmop+i
->
CeEIT)i
FLAGS'
None affected
NOTES'
CCIF) is not interpreted for this operation.
End Floating Suppression
ENF
the
02
If C(IF)O = 0, then
If ES is OFF, then
If SN if OFF, then C(EIT)3
If SN in ON, then
pout
= pout
->
C(EITI~ ->
C(Y-charn3)pout+l
C(Y-charn3)pout+l
+ 1
ES set ON
If ES is ON, then no action
If ClIF)O
= 1,
then
If ES is.OFF, then
C(EIT)5
pout
->
= pout
C(V-charn3)pout+l
+ 1
ES set ON
11 ES is ON, then no action
If ClIF'1
FLAGS'
REVIEW DRAFT
SUBJECT TO CHANGE
0<; tober, 14375
= 1,
then BZ set ON; otherwiie no action
(Flags not listed are not affected)
2-244
AL39
ES
If OFF, then set ON
8Z
If CeIF)1 :: 1, then set ON; otheMlse no change
14
Ignore Source Character
IGN
SUHMARYI
CeIF) + pin ->,pin
FLAGSI
None af fee ted
INSA
Insert Asterisk on Suppression
SUMMAR'll
11
If ES is OFF, then
CeEIT)2
->
CCY-charn3)pout+1
If CCIF) :: 0, then pmop :: pmop + 1
If ES Is ON, then
If CCIF)
11 ::
~
0, then
CUF)
C(EIT)m -> CCY-charD3)pout+l
If CCIF) :: 0, then
C(Y-char92)pmop+l ->C(Y-charn3)pout+1
pmop • 1
plllOP ::
FLAGS'
None aff ected
NOTES'
If C(IF) > 8 an itlegal
INS8
procedure Fault occurs.
Insert Blank on Suppression
SUMMARYI
10
If ES is OFf, then
C(EIT)1 -> C(Y-charn3)pout+1
If CeIF)
= 0,
then pmop :: pmop + 1
If ES is ON, then
If C(IF)
In
=
~
0, then
C (IF)
C(EIT)m -> C(Y-charn3)pout+1
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SUBJECT TO CHANGE
October, 1915
2-2'+5
AL39
If CCIF)
=
0, then
C(Y-char9Z)pmop+l
->CCY-charn3)p~ut+1
pmop :: pmop + 1
FLAGS'
None affecte::J
NOTES'
If CCIF) > 8 an Illegal Procedure Fault occurs.
Insert Table Entrv 1 Multiple
INS"
SUMMARY'
For i
= 1,
01
2, ••• , CCIF)
C(EIT)l -> C(Y-charn3Jpout+i
FLAGS.
INSN
None affected
Insert on Negative
SUMMARY'
12
If SN is OFF, then
C(EIT)1
->
If C(IF) =
CCY-charn3)pout+l
a,
then pmop
= pmop
+ 1
If SN is ON, then
If CIIF) _ 0. then
m
=
C (IF)
C(EIT)m -> C(Y-charn3)pout+1
If C(IF)
= 0.
then
C(Y-char9Z)pmoP+1
pmop
= pmop
->C(Y-charn3)p~ut+l
+ 1
FLAGSI
None af fected
NOTESI
If C(IF) > 8 an Illegal procedure Fault occurs.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-2«'&
AL39
INSP
Insert on Positive
SUMMARY'
13
If SN is ON. then
C(EIT)1 -> CCY-charnJ)pout+1
If C(IF)
= O.
then pmop
= pmop
+ 1
If SN Is OFF, then
If C(IF) _ 0, then
m
= C (IF)
C(EIT)m -> C(Y-charnJ'pout+l
If C(IF) = 0, then
C(Y-char92)pmop+1 ->CCY-charnJ)pout+l
pmop
= pmop
+ 1
FLAGSI
None affected
NOTES:
If C(IF) > 6 an Illegal Procedure Fault occurs.
LTE
Load Table EntrY'
SUMMARY I
m
20
C(IF)
:.I:
ClY-char92)pmop+l -> C(EIT).
pmop
=
pmop + 1
FLAGSI
None al rected
NOTES'
If C(IF)
occurs.
=0
or ClIF)
>
8
an
IIIeg31
Procedure
Fault
Hove with Float Currency Symbol Insertion
"FLC
SUMMARY-
For i
= 1,
07
2, •••• C(IF)
If ES is ON. then C(Y-charnl)pin+i ->
If ES is OFF and
CCY-ch~rDl)pin+!
C(Y-char~J)pout+l
= decimal
0, then
C(EIT)1 -> C(Y-charn3)pout+l
If ES Is OFF and ClY-charol)pin+! _ decimaJ 0, then
ClEIT)5
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
->
C(Y-charnJ)pout+l
2-2"7
AL39
CCY-charol)pin+!
-> CCY-cha~n3)p~ut+i+1
pout = pout + 1
ES set ON
FLAGS:
ES
NOTES:
CFlags not listed are not affected)
If OFF and any of C(Y-charnl)pin+i
otherwise unchanged
~
decimal 0,
then
ON;
If N1 or NZ exhausts before N3. an Illegal Procedure Fault
occurs.
The numbe~ of cha~acters moved to the ~eceiving string Is
data dependent. If the enti~e C(Y-cha-ol) is decimal O·s,
C(IF) cha~acte~s are moved to C(Y-cha-a3).
However, if
the receiving string contains a non-zero character. then
C(IF)+1 characters are moved to C(Y-charn3); the insertion
character plus ClY-charal). The user is advised that a
possible II legal Procedure Fault due to this condition may
be avoided by assuring that the Z and BZ flags are ON.
Hove wIth Float SIgn Insertion
HFLS
For 1
= 1.
0&
2 ••••• CeIFJ
If ES is ON, then
CCY-cha~nl)pin+l
->
C(Y-charn3)pout+l
It ES is OFF and C(Y-charo1Jpin+i = decima' 0. then
C(EIT)l
->
CCY-charn3)pout+i
If ES Is OFF and CCY-charnl)pln+l
If SN is OFF, then eeEIT)3
If SN is ON, then CCEIT)4
CCY-charnl)p!n+i
pout
= pout
~
decimal 0. then
-> CCY-c~arD3)pout+i
->
CCY-charo3)pout+i
-> CeY-charQ3)p~ut+i+l
+ 1
ES set On
FLAGS:
(Flags not Ilsted are not affected)
If OFF and any of CCY-charol)pin+l _ decimal 0,
otherwise unchanged
NOTES:
then
ON;
If N1 or NZ exhausts before N3. an Illegal Procedure Fault
occurs.
The number of characters moved to the ~eceivlng string is
data dependent. If the entire C(Y-c~a-Ql) is decimal O·s,
REVIEW OR~FT
SUBJECT TO CHANGE
October. 1975
2-248
CeIF) cha~acters are moved to C(Y-cha-n3).
However, if
the receiving string contains a non-zero character, then
C(IF)+l characters are moved to C(Y-charo3); the insertIon
character oJus C(Y-charnl). The ~ser is advised
that a
possible Illegal Procedure Fault due t3 this condition may
be avoided bv assuring that the land 3l flags are dN.
HORS
Hove and OR Sign
SUMMARYI
For I
= 1,
17
2, ••• , CIIF)
If SN is OFF, then
C(Y-charo1)pin+i I CCEIT)3 -> C(Y-charn3)pout+i
If SN if ON, then
CeY-charo1)pin+i I
FLAGSI
HSES
CeEIT)~
->
C(Y-char n3)pout+i
None affected
Hove and Set Sign
16
SUHHARY1
For 1
= 1,
2, ••• , CeIF)
C(Y-charnl)pin+l
For 1
= 1,
->
CCY-charo3)pout+l
2, ••• , C(IF)
C(Y-charol)pln+i -> CCY-charo3)pout+l
C(l)
= CCY-charnl)pln+i
If Cel)
0,
~
, CCEIT)3
then for J = 1+1, 1+2, ••• , CeIF)
C(Y-charn1)pln+J -> CeY-charol)pout+)
If Cel)
C(Z)
= 0, then
= CCY-charo1)pin+i
If eel)
~
,
C(EIT)~
0, then
SN set ON
For J = 1+1,·1+2 •••• , CeIF)
C(Y-charnl)pin+) -> C(Y-charn3)pout+J
FLAGS_
(Flags not JIsted are not affected)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
2-2"9
AL39
SN
If C(EIT)~
change
~ound
in C(Y-chara1),
then
ON;
otherwise
Hove Source Character
HVC
SUMHARY'
For 1
= 1,
15
2 ••••• C(IF)
C(Y-charn1)pin+l
FLAGS'
->
C(Y-charQ3)pout+l
None af fected
Hove with Zero Suppression and
"VZA
SUMMARYI
no.
For i
= 1,
Replacement
Asteris~
05
2, ••• , C(IF)
If ES Is ON, then C(Y-charnl)pin+l
If ES Is OFF and C(Y-charo1)pln+i
->
C(Y-charo3)pout+i
= decimal
0, then
C(EIT)2 -> C(Y-charn3)pout.l
if
ES is OFF and C(Y-charnl)pln+l _ decimal 0, then
C(Y-charal)pin+l ->
CCY-charn3)p~ut+l
ES set On
FLAGS.
ES
NOTESI
(Flags not lIsted are not affected)
If OFF and any of CCY-charnl)pin+l
otherwise unchanged
~
decimal 0,
then
If N1 or N2 exhausts before N3, an Illegal Procedure Fault
occurs.
Hove with Zero Suppression and Blank Replacement
"VZB
SUHHARYI
ON;
For 1
= 1,
04
2, ••• , C(IF)
If ES Is ON, then CCY-charn1)pln+i
If ES Is OFF and C(Y-charni)pln+l
->
C(Y-charo3)pout+l
= decimal
0, then
C(EIT)1 -> CCY-charo3)pout+i
If ES 1s OFF and CCY-charol)pin+i
CCY-charol)pin+i ->
#
decimal 0, then
C(Y-charn3)p~ut+l
ES set ON
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
2-250
AL39
(Flags not listed are not affected)
FLAGS'
If OFF and any of CCY-charnl)pin+l
otherMise uncahnged
ES
NOTESa
~ ~ecimal
0,
then
ON;
If N1 or N2 exhausts before N3. an Illegal Procedure Fault
occurs.
Set End Suppression
SES
If CCIF)O
SUMHARya
If CCIF)O
If CCIF)l
= 0,
= 1,
= 1.
03
then ES set OFf
then ES set ON
then BZ set ON; otherwise no action
(Flags not listed are not affected)
FLAGsa
ES
Set by
Bl
If CCIF)l
th~S
micro operation
= 1,
then ON; otherwIse no
c~ange
tticr& QAACa1LRn-Code Assignment HaR
Operation code assignments for the micro operations are shOMn in Table 2-9
below.
(---). indicates an unassigned code.
All unassigned codes cause an
I II e ga I Procedure Fau It.
2-9
Ta~le
-Micro Operation Code ASSignment
_--'1-
DO
10
20
3D
~ap~
;1
2
i
Z
!t
ses
mvzbl mvzal mf lsI mfleS
,,,sal insnJ inspJ ign 1 mvc I msesl morsJ
J
J .te J cht I
I
1
I
I
1
I
;
L--- I
--=-L::.- I
1-:=--.1.
J
--insb:
1
2
J ins",) enf
--- ---
---
REVIEW DRAfT
SUOJECT TO CHANGE
October, 1975
2-251
Al39
SECTION Itl
DATA REPRESENTATION
INfORMATION QRGANI1ATtaH
The P~Qcessort like the rest of the Hultics $vste~t is organized to deal with inforsatlon
in basic units of 3&-blt "words".
Other units of 4-, &-, 9-bit ··chardcters" or "bytes", 1S-bit ··half .. o~ds-, and 72-bit "word pairs·
can be man{pulated within the Processor by use
the instruction set.
These bit groupings are used by the
hardware and software to represent a var-iety of forms of coded data.
Certain Processor functions appear to manipulate larger units of 144, 288, 576, and 1152 ~lts, but
0'
0'
'unctions are performed by means
repeated
A t I In format ion 1s
respresented as strings of binary bits.
~se
01 12-blt
~ord
pairs.
The numbering Of bit positions,char-acte'" positions, and wordS ,,,creases in the direction
of conventlona' reading and writingl fro~ the most-significant to the feast-sign1flcant
digit of a nu_ber, and from teft to right In conv~ntional ~'phanu.eric teMf.
Graphic presentations in this manual sholf reg1$ters and da'. wit" pos!tlon
numbers Increasln g froll left to right.
O
The arithmetic f~nctions of the Proeesso· a~e I_plem.ftted 1n the tM~·S
comp Ie ment f bl nary number $y ste",_ One 0 f the prl mary proper ti es oft". s
number system 1s that a field (or register) hav'n~ Width Q bits Mav:be
Inprep~eted in t"O dIfferent wavs; the -logical- ~ase and the Marith•• tic·
or 0'· a I gebra lc·· ease.
In the logical case. the number Is unsig"ed. positive. and I'es In the
(D,2·.n - 1). The results of arithmetic ooerations OR nuntbers
for thiS case are inter~reted as 0 modulo n n~mbers.
Overflo" is not defined tor this case since t,e range of the fIeld or
~egister cannot b.ex~.eded.
The numbers "OUand "2 •• Q - 1" are conSecutive (not separated) in the
set of numberS defined for the field or register.
r.n~e
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
3-1
Al39
In the arithmetic case, the number Is si~ned and lies in the ran~e
Overflow is defined for this case since si,ce the
range can be exceeded in either direction (poiitive o~ negative ••
The lett-hand-most bit of the field or register (bit 0) serves as the sign bit and
does not contribute to the value of the numbe~.
(-2··'0-1),2 •• (n-1) - 1).
The main advantage of this '"pleaentation is that the hardware ar-lthlftetlc
a'gorithms for the two cases are identical; the onlv distinction
lying in the interpretation
the results by the user.
Instruction set 'eatu"'.~ are provided
. .
for performing binary .-Ithmetic .. lth overftojlj disabled
ethe so-called loglcat lnstruc.'ons)
and for co.parlng numbers In either sense.
of
Subtraction Is performed by adding the 'wo·s compl •• ent of the
subtrahend to the Minuend.
(Not. that when the subtr.hend Is zero the al~orlthm tor for.lng the two·s co.pt •• ent
Is stl't carried out, but. Since the two·s compteaent of zero is zer~t
the result 1s correct.) ,
Another Important feature of the two·s complellent
number System (with respect to comparison of numeric values) is that
the MhO borrow" condition In true subtraction is identlca. to the
··carry·· condition in true addition and vice Vlrsa.
A statement on 'the assumed "ocatlon of the binary pOint has significance" only
tor Multiplicatlon and division. These two 03eratlons are i~le.ente~ for the arltheetic case
1n both integer and fraction modes.
"Int~~er" means that the position
the bjna~v ooint Is
3ssulled to the right of the least-significant bit position (that is, to the
right of the r~ght-hand-.ost,blt of the field ~r ~eglster)
and "fraction- lIeans that the position of the binary point Is assulled
to the left of the Most-significant bit pOSition (that iSt bet"een bit D and
bit· 1 of the field or register; reca" that bit 0 is the sign bit).
0'
~.titJW1Al.liULf 0 BttAI S
The Figures beto. ShON the unstruet~red for.~ts (templates) f~r the vari~us infor.atlon units
defined for the Processor.
Data transfer between the ProceSsor and main store is word oriented; a 3&-bit aachlne word Is,
transfer~ed for single-precision ope~ands and sub-fields of machine w~rdSt and a 72-blt word pair
Is transferred for "a II other cases (liul t i-word operands, lnstruct Ion fetches, bl t- a,,~ character-str;
The information unit to be used and the data transfer .ode is
according to ,the function to be perforMed.
deterlli~ed
Dy the
Proc~ssor
the 36-blt unstructured machine word Shown In Figure 3-1 below Ii the IIlnl,.ulII addressable
information unit in main store. Its .ocation is uniQuely dete~~lned ~y Its .~in store address, Y.
All other information units are defined relative to the 36-blt Machine Nord.
REVIEW DRAFT
SUBJ£CT TO CHANGE
October, 1915
At.39
o
3
Q
5
I
I
I
I
J
I
36
figure 3-1
Unstructured Machine Word format
Two consecutive machines words as shown in Figure 3-2 below. the first
having an even main store address. form a 72-bit word pair.
In 72-bit word pair
data transfer mode. the word pair is uniQuely located by the main store address
of either of its constituent 36-bit machine words. Thus, if Y is even, the word
pair at (Y,Y+1) is selected. If Y is odd,
the word p3ir at
(Y-l,Y)
is
selected. The term ·Y-pair" Is used for such a word pair address.
o______________________________ --2-2
3 3 _________________
-a
7
1
Q
I
I
I
I
J
I
36
36
Even Word
Odd Word
figure 3-2
Unstructured Word Pair Format
4-bit characters are mapped onto 36-bit machines words as shown in Figure
3-3 below. The ·0" bits at bit positions 0, 9, 18, and 27 a~e forced to be 0 by
the Processor on data transfers to main store and a~e ignored on data transfers
from main store.
0 0
0 0
II 1
!t 2
I
1
J
I
101
LL_ _....L4
1
0 0 1
1 1
1 1 1
~
3 !t
--L8 ~
a I
a
..
I
II
a0 I
I
I
J
I I
1
.. I
Figure 3-3
101
I J
.. 1
2 2
Z
.
a
S
I
~
2 2 2
3 3
3
fa
1 Z
2
Z_a
I
..
1
J0I
I I
1
-
.
I
1
1
I
I
I
4
Unstructured 4-bi t Character Format
6-bit characters are mapped onto 36-bit machines words as shown
in
Figure
3-4 below.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
3-3
AL39
0
0 0
1 1
-1-__---2-6
I
I
I
I
I
2 l
3_L--_ _ _ -LO
Figure 3-4
9-bit characters
3-5 below.
a~e
,
I
I
6
6
3
2 2
I
I
J
I
----1
6
&
5
I
I
I
6
I
6
mapped onto 3&-blt machine
wo~ds
as
shown
In
I
Figu~e
0
0 0
1 1
Z Z
3
~-2
-La.
-Ll
5
I
I
1
I
•I
I
9
I
I
Unstructured 6-blt Character Format
II
I
J
I
I
J
--L-
--1
9
9
9
Figure 3-5
...
1 1
l-L- ___ ---L8
I
Uns,truc tu~ed 9-blt Character Format
lS-bit half Nords are mapped onto 3S-blt machine Nords as shown
3-6 be' ow.
o
1 1
Q
--1-~8
in
Figu~e
3
5
___________,
I
__________________________ ---1I ________________
18
18
Uppe~
Flgu~e
Half
3-6
Lower HaJf
unstructured is-bit Half Word Format
IlATA PARITY
Odd parity on
generated as it
transmission path,
parity is detected
each 3D-bit machine word transferred to main store is
leaves the Processor, is verified at seve~al points along the
and is held in main store as an "extra" bit.
If an incorrect
at any of the various parity Mcneck poInts", the main store
returns an Illegal Action signal and a code
approp~late
to the check point.
On data transfe~s from main store, the parity bit is retrieved and
transmitted with the data bits.
The same verification checks are made and
Illegal Action signa' led for errors. The Processor makes a final parity check
as the data enters the Processor.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1~15
AL 39
Any detected parity error causes the Processor Parity indicator to
and (if enabled) a Parity Fault.
set
ON
REPRESENTATI01LQf PATA
Data is defined bV Imposing an operand structure on the
information
units
described above.
Oata
is represented in two forms: nume-ic or alphanumeric.
The form Is determined by the Processor according to function to be performed.
Numeric data is represented in three modeSI fixed point binary, floating
point binary, and decimal.
The mode is determined by the Processor according to
the function being performed and any Address ModificatIon
invoked for
the
instruction being executed.
FIXED POINT BINARY DATA
Fixed PoInt Binary Integers
Fixed point binary integer data is defined by imposing either of
the
position value structures sho~n below on an information unit of 0 bits.
bit
Logical valuel
atO)x2··0 + a(1)xZ··CO-l) + ••• + a(0-1)
T
Arithmetic valuel
["-ALa(O)]
(aUllalO)xZ.·(a-1)+(a(Z)la(D»xZ·.(c.-Z)+ •••
+(a(o-Ula(O»
,
where.
all) is the value of the bit in the Lth bit position
•
indicates the Boolean Exclusive OR function
"T" indicates the position of the binary point
("-"La(O)] selects the proper sign according the v31ue of a(O)
The following fixed point binary integer data items are definedl
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1<375
3-5
AL3<3
n
&-blt Byte Ope~and
9-bit Byte Operand
Half Word Ope~and
Single Precision Operand
Double Precision Operand
&
9
18
36
72
Note that ~-bit Byte Operands a~e n~ defined.
only for Oecimal Data.
(See Decimal Oata below.}
This data item
1s
defined
The proper operand and its position within a 3&-bit machine word is
determined by the Processor during prepa~ation of the main store address for the
operand.
If the data width of the operand selected is smaller than the register
involved,
the operand is high-order and/or low-order zero filled as necessary.
Table 3-1
6-bi t
Operand
Byte
FiKed PoInt Binary Integer Values
9-blt
Byte
18-blt
Half Word
36-bit
Single Precisio~
72-blt
Double Precision
o
o
logical range
Minimum'
0
Haxlmuml
(2··0)-1
Resolutions
1
.
~
Arithmetic range
Minimum'
0
"axillal
Neg.
-(2··5)
POSe
(2··5)-1
Resolutionl
1
o
- (2··8)
(2··8 )-1
1
o
- (2··17)
(2··17)-1
1
--(2··71)
(2··71'-1
1
-(2··35)
(2··35)-1
1
Fixed Point Binary Fractions
Fixed point binary fraction data Is defined by imposing
value structure below on an information unit of D bits.
the
bit
position
Arithmetic valuel
("-"'a(O']
(aC1)ea(O)'x2··-1+(a(2)'a(O»K2·"-2+ ••• +(a(n-l)'aCO»)K2··-(0-1)
T
Note that logical values are not defined for fiKed
poi~t
binary
fraction
data.
The following fiKed point binary fraction data items are definedl
REVIEW DRAFT
SU9JECT TO CHANGE
October, 1975
3-&
AL39
.D
ti~.!IUt
6
9
6-bit Byte Ope~and
9-bit Byte Ope~and
Half Word Operand
Single Precision Ope~and
18
36
Note that ~-bit Byte Operands and 72-blt Double Precision Operands are n21
defined.
~-bit
Byte Operands a~e defIned only fo~ Decimal Data. (See Decimal
Oata belo __ .)
If the instruction being eKecuted is Divide F!'-actlon
(DVF),
the
contents of
the combined Accumulato~ and Quotient Registers are treated as a
72-bit fixed point binary fraction value but are not address3ble as an operand.
The proper operand and
its position within a l6-bit machine word Is
determined by the Processor during preparation of the maIn store address for the
operand. If the data width of the operand selected is smaller than the register
involved, the operand is high-orde~ or low-o~der zero filled as necessary.
Table 3-2
Operand
6-bit
Bvte
9-blt
Byte
o
o
ArithmetIc range
Hiniaunt:
.. Maximal
Neg.
- - - (1)
POSe
Resolution.
the
o
«(2·.8)-1) x 2 4 "'-35
2··-35
Upper 18-bit
Half Word
36-bit
Single PreciSion
o
o
ArithlDetic range
ttlni ttutU
Haxin:al
Neg_
POSe
Resolutionl
18-bit
Ha If Wor d
lowe~
«(2 4 .5)-1) x 2.·-35
2"'4-35
Operand
(1)
Fixed Point Binarv Fraction Values
-1.0
1.0 - 2··-17
2·"-11
«2. 4 17)-1) x 2··-35
2 44 _35
-1.0
1.0 - 2·"-35
Z··-35
No Negative maximum 1s shown for 6-bit Byte, 9-blt Bvte, and Lower 18-bit
Half
Word operands since the
high-order zero fiJI
Quring
ope~and
alignment forces the sIgn bit to zero.
All operands are legal for the Divide Fraction (OVF) Instruction but only
18-bit
Half
Word and 36-bit Single PreciSion operanls are legal for the
Multiply Fraction (MPF) instruction.
Fixed point
instructions.
binary
fraction
operands
are
i I'egal
for
aI I
other
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AL39
FLOATING POINT BINARY DATA
A floating point binary number is expressed as
Z
="
x Z •• E
... here" is an arithmetic fixed point binary fraction; the
E is an arithmetic fixed point integer; the
~antissa
expone~t
A floating point binary number is defined by imposing
value structure below on an information unit of 0 bits.
the
bit
position
Exponent val uel
{"-"la(Ol] (a(lJ'a(O)xZ··o + (aCZ.'a(O»xZ·.5 + ••• + (3(7)la(0))
T
Hant issa val ueS
[88--la (8)] (a19 )Ia (8)) xZ"·-l+ (a (10) la (8)) xZ"·-Z+ ••• + (alo-l) ea C8 UxZ·· 17-n)
T
where
above.
the
symbols
and
notation
are
the same as for fixed point binary data
The 101 lowIng f'oatlng poInt data items are defined.
tiUl."
Half Word Operand
Sing'e Precision Operand
Double Precision Operand
18
3&
7Z
For clarity. the formats of these operandS are shown in Figures 3-7 through
be I 0 ...
i
I
1
Figure 3-7
I
J
I
__
J
IS:
"
10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
______________ ---1____________________________________
7 1
10
1
:
E
~
-
~
0 0 ____________ --L-d
1 1 _______________________________53__
1
I 1
lSI
I
o
0
o
~
o
~
3-10
18
Upper lS-bit Half Word Floating Point Binary Operand Format
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3-8
AL39
o
a
000
1 1
3
--L8.-3.
-La
~
0
g 1
t
101 0
o
0 o 0
o
-Lt
J I
Figure 3-8
0
o
0 0 0
o
I
I
01
---1.
10
J
"
18
I
LaMer 18-bit Half Word Floating Point Binary Operand Format
0 0
0 0 0
3
1
Z D 51
~
a
I
1
lSI
I I
1
I
I
lSI
E
I
H
I
---1- •I
7 1
Figure 3-9
I
o
7 1
1
I
I I
01010
27
Single Precision Floating Point Binary Operand Format
0 0
o
0 0
7
1
Z
8~
Z
a
a
lSI
I
I I
1
I
1
I
,
lSI
E
H
I
I
7 1
Figure 3-10
63
Double PreciSion Floating Point Binary Operand Format
The proper operand is selected by the Processor during preparation of the
main store address for the operand. If the data width of the operand is smaller
than the register involved. the operand is high-order or low-order zero fIt led
as necessary.
Overlength Registers
The combined AQ register is used to hold the mantissa of a.1 floating point
binary numbers. The AJ register is said to be overlength with respect to the
operands since it has more bits than are provided by the operands. Operands are
low-order zero filled when loaded and low-order truncated (or rounded, depending
on the in~truction)
when stored~
Thus, the result of all floating point
instructions has more bits of precision In the AQ than may be stored.
Users are cautioned that algorithms involving floating point
operands
may
suffer from propagation of truncation errors unless the algorithms are designed
to hold mantissas in the AQ register as long as possible.
It is possible to
retain full
AQ preCision of results If they are saved with the Store AQ (STAQ)
and Store lxponent (5TE) instructions but such saved data are not usable as a
floating point operand.
Normalized Numbers
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Al39
A floating point number is said to be nor~alized if the rela~ion
(0.5
~
IHI < 1.0)
is satified.
The presence of unnormalized numbers in any finIte mantissa
arithmetic can only degrade the accuracy of results.
Flr example,
in an
arithmetic allowing only two digits in the mantissa. the number 0.005 x 10.·2
has the value zero instead the value one half.
Normalization is a process of shifting the mantissa and adjusting the
exponent until
the relation above is satisfied. Normalization may be used to
recover some or all of the extra bits of the overlength AQ register after a
floating point operation.
There are cases where the limits of the registers force t~e use of
unnormallzed numbers.
For example. in an arithmetic allo~ing three digits
mantissa and one digit of exponent. the calculation 0.3 x 10·.-10
0.1 x
10··-11 (the normalized case) may not be made. but 0.03 x 10··-9 - 0.001 x
10··-9
0.029 x 10··-9 (the unnormallzed case) is a valid result.
0'
=
Some examples of normalized and unnormalized numbers are'
unnormalized positive binary
Same number normalized
Unnormalized negative binary
'Same number normalized
The minimum normalIzed non-zero floating point binary
all cases.
Table 3-3
Floating Point Binary Operand
Lower 18-bit
Half Word
Operand
Unnormalized range
Hinimuml
Maximum.
Neg.
0(1)
---(2)
(2·.9 - 1) x 2··-155
Resolution'
2··-155
POSe
n~mber
Is 2··-128
in
Val~es
Upper 18-bit
Half Hord
36-bit
SIngle Precision
o
o
-1.0 x 2··127
(1 - 2··-9) x 2··127
119(3)
-1.0 x 2··127
(1 - 2.·-27) x 2··127
1127
72-bit
Operand
DoubJe PrecIsion
Unnormalized range
Minimuma
Maximuma
Neg.
POSe
Resolutionl
o
-1.0 x 2··127
(1 - 2··-63) x 2··127
11&3
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3-10
Al39
(1)
There is no unique representation for the value zero in floating point
binary numbers; any number with mantissa zero has the v3lue zero.
However,
the Processor treats a zero mantissa as a special case in order to preserve
precision in later calculations with a zero intermediate resu1t.
Whenever
the Processor detects a zero mantissa as the result of
a
floatin1 bin~ry
operatio~, the AQ register is cleared to zeros and the ~ register is set to
-128.
This representation Is known as a floatIng n~rmaJizej zero. The
unnormal ized zero
(any zero mantissa)
will
be ha1dled correctly if
encountered in an operand but precision may be lost. For example, A x
10··-1~ + 0 x 10··S5
will not produce deSired results since all
the
precision of A will be lost when it is aligned to match the 10··85 exponent
of the o.
(Z)
No Negative maximum is shown for Lower lS-bit Half Word operands Since the
high-order zero fill during operand alignment forces the Sign bit to zero.
(3)
A value cannot be given for Resolution in these cases Since
such a value
dependS on the value of the exponent, E.
The notation used (l:m) indicates
resoJution to 1 bit in a field of m.
Thus, the followl~g general state~ent
on resolution may be madel
The resolution of a floating point binary operand with mantissa length
and exponent value E is 2··(E-.).
m
DECIHAl DATA
Dect_a' numbers are expressed in one
0'
the following formSI
Fixed point, no Sign
HHMHMH.
Fixed poInt, leading Sign
±..HHI1 MMH.
Fixed point, trailing slgn
Floating point
The form is specified by control information In the Operand Descriptor for
the operand as used by the Extended InstructIon Set (EI5). (See Section II,
Machine Instructions.)
A decimal number is defined by impOSing any of the character position value
structures belo~ on a 4-blt Character or 9-bit Character l~formatlon unit of
length n characters.
Fixed point. no signa
T
Fixed point,
leading signa
(sign=c(O)] c(1)xl0··(n-2) + c(2)x10··(n-3) + ••• + c(Q-1)
T
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3-11
AL39
fixed point, trailing signl
cCQ)xl0··(O-2) • c(1)xl0··CO-3)
+ • • • • cCo-l)
(slgn=cCQ)]
T
floating polntl
(sign=c(O)]
c(1)xl0··(o-3).c(2)xl0··(n-~)
•••• +c(n-2) (exponent=8 bits)
T
.. herel
is the
position.
decimal
c(~)
value
of
the
character In the Lth character
"T" indicates the position of the decimal pOint •
•
(sign=c(L») indicates that c(L) is interpreted as a Sign character.
[exponent=8 bits] indicates that the exponent value is taken from
the
.ast 8 bits of
the character string.
If the data is in 9-bit
Characters, the exponent is bits 1-8 of cCo).
If tne data is in ~-bit
Characters, the exponent is the concatenated value of c(n-1) and c(nJ.
The decimal number as described above is the only decimal
data item
defined.
It may begin on any legal character boundary (without regard to word
boundaries) and has a maximum extent of &3 characters.
The Processor handles decimal data as ~-blt bytes internally. Thus,
9-bit
characters are high-order truncated as they are transferred from main store and
high-order filled as they are transferred to main store.
The
fill
pattern is
MOOll0"b for digit characters and ·00100-b for sign characters. The floating
point exponent is a special case and is tre3ted as a two·s complement binary
integer.
The Processor performs validity checking on decimal dat~.
Only
the byte
values
(0,11)
octal
are
legal
in digit positions and only the byte values
(12,17) octal are legal in Sign positions.
Detection of an illegal
byte value
causes
an
Illegal
Procedure fault.
The interpretation of
decimal sign
characters is shown In Tabel 3-~ below.
Table
3-~
Decimal Sign Character Interpretation
9-bit
It-blt
~C~C kha~ac
52
53( 1)
5lt
55(1)
5&
57
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12
13(2)
14(1)
15(t)
1&
17
IoterpretatlQn
+
+
+
+
•
3-12
AL39
(1)
for storage of
This character is used as the default sign character
results.
The presence of
other characters will yield c~rrect results
according to the lnterpreta~ion.
(2)
An optioral control bIt in the Eis Decimal Arithmetic instructions (See
Section II, Machine Instructions) allowS the selection of (13) octal for
the plus sign character for storage of results in ~-bit data mode.
Decimal Data Values
The Operand Descriptors for decimal
data operands h~ve a 6-blt
two·s
complement binary field for invocation of a Scaling Factor (SF). This Scal ing
Factor has the same effect as the value of E in floating point decimal operands;
a negative value moves the assu~ed decimal point to the left; a positive value,
to
the right.
The use of the Scaling Factor e~tended the ~ange and resolution
of decimal data operands.
The range of the Scaling Factor I i (-32,31).
Table 3-5
Decimal Data Values
Fi~ej Point
Leading or Trailing Sign
Fixed Point
No Sign
Operand
Arithmetic range
Hinimum.
Haximumi
o
O(1)
'10··6~
~(lO··63
- 1) x 10··31
1ast
1ISF(2)
R~solutlonl
Operand
4-bjt Floating PoInt
9-bit Floating Point
Arithmetic range
H1nimuma
Maximuml
ResolutIonl
o
o
~(10··62
- 1) x 10··31
~'10··61
- 1) x 10··158
1ISF+E
- 1) x 10··158
1ISF+E
(1)
See Decimal Zero below_
(2)
A value cannot be given for Resolution in these cases since SUCh a value
dependS
on the va.ue of the Scaling Factor, SF, and/or the exponent. E.
The notation used (lISF+E) indicates resolution to 1 part
In 10·.'SF+E).
Thus, the followIng general statement on resolution may be madel
The resolution of a fixed point decimal operand with Scaling Factor SF
is 10··SF and the resolution of a floatIng point de:lmaJ
operand with
Scaling Factor SF and exponent E is 10··(SF+E).
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3-13
AL39
Decimal Zero
As In floating point binary arithmetic. there Is no uniQue representation
of
the value zero except in the case of fixed point, no si~n data.
Therefore,
the Processor detects a zero result and forces a value of +0. for
flxed point,
leading or
trailing sign and +0. x 10··127 for floating point data. Again, as
in ftoating binary arithmetic. other representations of the ~alue zero will
be
handled
correctly except
for possible
loss of precision during operand
a I ignment.
Alphanymeric Qata
Alphanumeric data is represented in two ~odes;
character string and bit
string.
The mode is deter.ined by the Processor ac~ordlng tl the function being
performed.
CHARACTER STRING DATA
Character string data is defined by imposing
the character pOSition
structure below on a ~-bit. &-bit, or 9-bit Character infor~ation unit of length
D characters.
~'O)
II cll)
U
•••
II ceO-i)
where'
eel) is the character in the
II
~th
character
positio~.
indicates the concatenation operation.
The character string described above is the only character string data item
defIned.
It may begin on any legal character boundary (without regard to word
boundaries) and has a maximum extent as shown in Table 3-& below.
Table 3-&
Character String Data Length LImits
Character S 11..e
len 9th liLUl
C)-bit
104857&
o-bit
15728&4
4-bit
2097152
No interpretation of the characters is made except as
specified
instruction being executed.
'See Section II, Machine Instru:tions.)
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3-14
for
the
AL39
BIT STRING DATA
Blt string data Is defined by imposing the bit position structure belo"
a machine word information unit of length n bIts.
b «0 ) Jib (1) 'I I • • •
on
I I b (0-1 )
wherel
bll) is the value of the bit in the lth position.
II
indicates the. concatenation operation.
The bit string described above is the only bit string data
item defined.
may begin at any bIt position (without regard to character or word
boundaries) and has a maximum extent of q~3718~OOO bits.
It
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3-15
AL39
SECTION IV
PROGRAH ACCESSIBLE REGISTERS
A Processor register is a harware assembly that holdS l~forma'ion
for use
in some specified way.
An accessible register is a registe~ whose contents are
available to
the user
for his purposes.
Some accessible registers are
explicitly referenced by particular instructions, some are i~plicltly referenced
during
the course of execytion of instructions, and so~e are used in both wayS.
The accessible registers are listed in the table bel3w.
See Section II, Hachine
Instructions, for a discussion of each instruction to determine the way in which
the registers are used.
Table
~-1
Processor Registers
12oemonj,c
Accumulator Register
Quotlent Register
Accumulator-Quotient Register(1)
EKPonent Register
Exponent-Accumulator-Quotient Register(l)
Index Registers
Indicator Register
Base Address Register
Timer RegIster
Ring Alarm Register
Pointer Registers
Procedure Pointer Register
Temporary Pointer Register
Descriptor Segment Base Register
Segment Descriptor Word Associative Memory
Pa1e Table Word Associative Memory
Fault Register
Mode Register
Cache Hode Register
Control Unit (CU) History Register
Operations Unit (OU) Historv Register
Decimal Unit (OU) History Register
Appending Unit (AU) History Re9ister
Configuration Switch Data
not
Qyant Ux
1
36
A
Q
1
1
36
72
AQ
1
1
8
1
1
1
1
8
1
1
8
E
80
18
EAQ
Xn
lR
1~
BAR
18
27
3
TR
RALR
PRn
PPR
,.2
37
,.2
TPR
DSBR,(OBR)
51
SOWAI'1
PTWAI'1
85
51
35
HR
CHR
33
Control Unit Data
Decimal unit data
(1)
a1..LLitl.gib
1
16
16
1
1
28
1
72
72
72
72
16
16
16
16
3&
5
57&
1
1
288
These registers are not separate physical
combinations of their constituent registers.
assemblIes
but
are
logical
in the descriptions that folJow, the dIagrams given for re1ister formats do
imply that a physical assembly posseSSing the pictured bit pattern exists.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
4-1
AL39
The diagrdm is a graphic representation of the form of the register data as It
appears
1n main store
when the register contents are sto-ed or how data bits
must be a~sembled for loading into the register.
E.m:m..all -
36 bi ts
o
-D..-
__________________
1 1
3
5
--1-~
s
I
A-Upper
S
A-lowe'"
I
18
Figure 4-1
18
Accumulator Register CA) Format
Descriptioo:
A 3& bit physical register located in the Operations Unit.
In fixed point bInary operations, holds operands and results.
In floating point binary operations, holds the most significant part of the
mant issa.
In shifting operations, holds original data and shifted results.
In aCdress preparation, may hold two logica11y indepenjent
word offsets,
A-Upper and A-lower, or an extended range bit or character 01fset.
~ma1!
-
36 bits
o
1 1
1 8
-1l.
Q-Upper
_________ ---1____________
Q-lowe"
18
Figure 4-2
Quotient Register
16
(Q)
Format
REV lEW OR ~FT
SUBJECT TO CHANGE
October, 1975
4-2
Al39
Q~$cr,iDt.1onl
A 36 bit physical
re~lster
located in the Operations Unit.
fJ.LQctlQn'
In fixed point binary operations, holds operands and results.
In floating point
the mant lssa.
binary operations, holds the least significant part of
In Shifting operatIons, holds original data and shifted results.
In acaress preparation, may hold t~o logicallv indepen~ent word offsets,
Q-Upper and Q-lower, or an extended range bit or character offset.
format' - 72 bits
o
7
3 3
5 6
Q
.-
Z
I
I
Odd Word
Even Word
_____________________
---1a ____________________
_
I
36
Figure
~-3
36
Accumulator-Quotient Register (AQ) rormat
Qe$C;r Ip t lonl
A logical combination of the Accumulator (A) and
Q~otient
(Q)
registers.
Eunc;t1 oD.1
In fixed
results.
point
binary
operations,
holds
dOUble precision operands and
In floating pOint binary operations, holds the mantissa.
In shifting operations. holds orIgInal data and shifted results.
REVIEW DRI!FT
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October, 1':175
~-3
AL39
[m:m.all - 8 bits
o
I
a
0
3
----~--------a
p
5
J
a
exponent
Ix x x x x x x x x x x x x x x x x x x x x x x x x x x x:
L -_ _ _ _ _-L
-----
8
Figure
~-4
28
)
Exponent Register (E) Fromat
Cl1tScriotion!.
An 8 bit phvsical register located in the OperatIons Unit.
Bits pictured
as "x" are "donat care" bits, that is, are irrelevant to the register or
its use.
fUDction'
In floating point binary operations, holds the exponent.
El~ENT-ACCUHUlATQR-QUQTIENT
~1i
R~~IER
(EAQ)
- 80 bits
0
0 0 _______________________________________
-l
____________
7
~1~8
I
I
I
I
I
I
exponent
2
man t Issa
8
Figure 4-5
6~
Exponent-Accumulator-QuotIent Register (EAQ) Format
OficriDtion!
A logical combinatIon of the Exponent (E), Accumulator (A), and Quotient
(Q)
reglstersa
Although the register has a total of 60 bits, only 72 are
Involved In transfers to and from maIn store.
truncated on store and zero filted on 'oad.
The low
order
8
bits
are
Eimction,
In float Ing pOint binary operatIons, holds operands and results.
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Al39
lHUEK REGISltRS-lXDl
E~na11
- 18 bits each
o
1
_____________--1-
Q
I
I
J
18
Figure
~-&
Index Register (Xn) Format
Qescription:
Eight 18 bit phvsical registers in the Operations Unit numbered 0 throUgh
7. Index Register data may OCCUpy the pOSition of either an Upper or lo~er
18-bit Half Hord operand In a main store machine word.
functIonl
In fixed point binary operations. hold half word operanjs and results.
In acdress preparation.
.character offsets.
f~1
-
1~
hold
word
offsets
or
extended
range
bit
or
bits
0 1 1 1 Z 2 2 2 2 2 2 2 Z 2 3 333
-&0______________________________
J
~Z_a8_49~O~1
__
2_~~~2~~
9 Q 1
Z
5
:::I::IJIIIIIII
Ix x x x x x x x x x x x x x x x x
,
x:alb:cld:elflglh:itll~:'lmlnIO
_____________________ ---1 ; I ; I 1
1-1-1-1-l_~J~I~J~;~
18 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure
4-7
I
0 0 OJ
______
4
~:
Indicator Register (IR) Format
~~ription!
A logical assemblage of 14 indicator flags from ~arious units of the
Processor. T~e data occupies the pOSition of a Lower 1S-bit Half Word
operand.
Bits pictured as -x" are "don·t care- bits a~d are irrelevant to
the register or its use. Bits pictured as "0· are reserved and must have
value O. When interpreted as data, a bit value of 1 corresponds to the ON
state of the indicator, a bit value of 0 corresponds to the OFF state.
REVIEW DRAfT
SUBJECT TO CHANGE
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~-5
AL39
[unctionl
The functions of the individual indicator bits are gjve~ below. An ··x·
the column headed •• 1.... indicates that the state of the .indicator is
affected by instructions that load the IR.
in
1l~1
a
Zero
This indicator is set ON Mhenever the output
of the main binary adder conSists entirely of
zero bits for binary or shifting operations
or the output of the deci~al adder consists
of
z e r o d i g its
f or dec 1 ma I' 0 per a t 1 on s ;
otherwise, it is set OFF.
b
Negat ive
This indicator is set ON ~henever the output
of bit 0 of the main bina~y adder has value 1
for b.inary or shifting operations or the sign
character
of
the.
result of a dec lila I
operation is the ne9ati~e sign character;
otherwise, it is set OFF.
c
Carry
This indicator is set
following conditions;
OFF.
for any of the
otherwise, it is set
O~
(1)
If a bit propagates leftward out of bit
o of the main bi~ary adder for any
binary or shifting o)eration.
(Z)
If Ivaluell =< Ivalue21
for a
numeric compar-islon )per-atlon.
decillal
(3)
If chart =< charZ
for
a
alphanumeric compare operation.
decimal
d
Overflow
This indicator is set ON if
the arithmetiC
range of a register is exceeded In a fixed
point binary operation or if the target
string of a decimal nume~ic operation is too
small to hold the integer part of the result.
It remains ON until reset by the Transfer on
Overflow (TOV) instruction or Is reset by
some other instruction that loads the IR.
The event that sets t~is indicator ON may
also cause an OverfloMi Fa ... t.
(See OverfioM
Mask indicator beloM.)
e
Exponent Overflow
ThiS indicator is set ON if the eKPonent of
the result of a floating point binary or
decimal numeric operatio~ is greater
than
+127.
It remains ON Jntil reset by the
Transfer
on
Exponent
Overflow
(TEO)
instruction
or
is reset by some other
instruction that loads t~e IR.
The event
that sets this injicator )N may also cause an
Overflow Fault. (See Ove""low Mask indicator
beloMi.)
Exponent Underflow
R1:.VIEWORAfT
SUBJECT TO CHANGE
October9 1975
This indicator is set ON if the exponent of
the result of a floating point binary or
decimal numeric operation is less than -128.
It-I)
AL3CJ
It remains ON untIl reset by the Transfer on
Exponent Underflow (TEU)
instruction or is
reset by some other initructlo~ that loads
the IR. The event that sets this indicator
ON may also cause an lverflow Fault. (See
Overflow MaSK indicator below.)
9
Overflow Mask
This indicator is set ON or OFF only by the
instructions that load t~e IR. When set ON.
it inhibits the generation of the fault for
those events that normally cause an Overflo.
Fault.
If the Overflo~ Mask indicator Is set
OFF after ocurrence of an Overflo" event, an
Overflow Fault " i l l not occur even though the
indicator for that eve~t
is still set ON.
The state of the Overflow MaSk indicator does
not affect the setting, testing, or storing
of any other indicator.
h
Ta II 'I Runout
This indicator is set OFF at
initial ization
of any tallying operation, that Is, any
repeat instruction or any Indirect Then Tally
Address Modification. It is then set ON for
any of the follo~ing conditions:
i
(1)
If a repeat
inst~uction
because of tallv exh~ust.
(2)
If
(3)
If a tally exhaust is detected
for an
Indirect
Then
Tally modifier.
The
instructIon will be executed whether or
not tally exhaust occurs.
t er IIi na tes
a Repeat Link (RPl)
instruction
terminates
because
of a zero lInk
address.
Parity Error
This indicator is set ON whenever the ~ain
store signals Illegal ~ctor with a parity
error code or the Processor detects
an
internal
parity
error
condition.
The
indicator is set OFF only by instructIons
that load the IR.
Parity "ask
This indicator is set ON or OFF only by the
instructions that load the IR. When it is
set ON, it inhibits the generation of
the
Parity Fault for all events that set the
Parity Error indicator. If the Parity Mask
indicator is set OFF afte~ the ocurrence of a
Parity Error event. a Parity Fault wi" not
occur even though the Parity Error indicator
may stIli be set ON. The state of the Parity
Mask indicator does not affect the loading,
testing, or storing of anf other indicator.
generated fro~ previouslv set parity error
indicators. The status of
the parity mask
indicator
does
not affect the setting,
testing, or storin~ of the parity error
indicator.
REV lEW DRAFT
SUBJECT TO CHANGE
October, 1RPO) in Section I I y
Machine Instuctions.
REVIEW DRAFT
SUBJECT to CHANGE
Octobery 1975
'+-12
Al39
PRn.SITNO
The Bit Number register contains th~ number of the bit
within PRn.CHAR of the word at P~n.WO~ONO containing
the data item.
The value is determined when the
pointer
data
is constructed f~om
the data item
description in the procedure.
~ord
and character
boundary aligned data items Mill always have the value
O.
Unaligned data items may have any value in the
range (0.10) octal. See NOTE under PRn.CHAR above.
f.R.Q.k.EllU&LfQ I NIE R REG 1.S.1E.&-ifeRl
E~l1
-
37 bits
Word 0 of Control Unit Data
o
0
1 1 1
7 8 ~
J J
ZP he x x x x
0
g Q
II
J
J
I
I
PRR I
PSR
I
J
~
J
)(
x
)(
)(
K
X
X X
X
X X
xI
I
---L--L-
3
Word
•
3
2
of
15 1
17
1 1
3
Control Unit Data
o
-'L18
2
J
I
a
I ________________________________
IC
AI
---1Ix x x x x x )( x x x )( x x x x x x xlI
18
Figure
~-12
18
Procedure Pointer Register (PPR) Format
1l..sc;riDtlon!
A logical combination of physical registers from the Appending Unit and the
Control Unit.
PPR.PRR. PPR.PSR, and PPR.P are located In the Appending
Unit and PRR.IC Is located in the Control Unit. The data is pictured as it
appeers in main store in Words 0 and ~ of Control Unit Jata.
Bits pictured
as "x" are "don-t care" bits and are irrelevant to the ~egister or its use.
The bits ~ have meaning wIth regard to Control Unit Data.
(See Control
Unit Data beloM.)
(unction.!
The Procedur~ Pointer Register holds information relative to the location
in mdin store of the procedure segment in e~ecution and the location of the
current instruction within that segment. The functions of
the indivi1ua'
constituent registers are:
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
4-13
AL39
PPR.PRR
The erocedure ~ing RegIster contains the number of the
ring
(validation level.
in ~hlch tne process is
executing.
It is set to the Effective ~inq Number of
the procedure segment when contr31 is transferred to
the procedure.
PPR.PSR
The erocedure Segment Register contains the segment
number of
the procedure being executed. Its value
changes every time control is tra~sferred to a new
procedure.
PPR.P
The frivlleged bit register is a flag controlling
execution of privIleged instructions.
Its value is
"l"b (permitting privileged instructions) Is PPR.PR~ is
o 3nd the privileged bit in the Seg~ent Descriptor ~ord
(SOW.P) for the procedure is "1"b.
Its value is "ONb
if
SOW.P is 0 or PPR.PRR is greate- than o. Its v~lu~
is set every time a new procedure is entered.
PPR.IC
The Instruction kounter register contains the
~o~d
offset from the origin of the procedure segment to the
current instruction.
RE.VIEW OR~FT
SUBJECT TO CHANGE
October, 1975
AL39
Eormata - 42 bits
Word 2 of Control Unit Data
0
o
0
1 1
3
D
D 0
-Ll
S
I
1
I
I
&
Ix x x x x x x x x
I
TSR
TRR I
I
I
X
IC
X X X X X X
18
15
3
xI
I
Word 3 of Control Unit Oata
o
2 3
Q
_~9~Q~
3
________5,-
I
J
Ix x x x x x x x x x x x x x x x x x x x x x x x x x x
I
X
IC
xl
I
I
TBR
41____________~1
30
&
Word 5 of Control Unit Oat a
0'_________________________________
~Q
I
1
I
1 1 ___________________________________5,3
--Z-~8
I
CA
I
Ix x x x x x x x x x x x x x x x x xl;
_ _ _ _ _ _--a._______
t
18
Figure 4-13
Temporary Pointer Reglster (TPR)
18
~ormat
A logical combination of phYSical re3isters from the Ap)ending Unit and the
Control Unit. TPR.TRR. TPR.TSR, and TPR.TBR are locatej in the Appending
Unit and TPR.CA is located in the Control Unit. The data is pictured as it
appears in main store in Words 2, 3, and 5 of Cont~oJ unit Data. Bits
pictured as "x'· are "don·t care" bits and are irrelevant to the register or
its use. The bits ~~ have meaning with regard to Contr)1 Unit Data.
(See
Control Unit Data below.)
The Temporary POinter Register holds information relative to the location
in main store of indirect words and pointers (during address preparation)
and operands (during instruction execution). At the completion of address
preparation, the contents of the TPR is presented to the Appending Unit
Associative Memory Assemblies for translation into tne final 2~-bit main
store address.
The functions of the individual constit~ent registers ~re:
REVIEW DRAFT
SUBJECT TO CHANGE
October t 1975
~L39
fPR.TRR
The temporary &ing Register contains the Effective ~ing
Number
for
the
data access.
If the access is to the
procedure segment, TPR.TRR is set to
PPR.PRK;
if
the
access
invokes
a
Pointer Registe~, TPR.TRR is set to
the larger of PRn.RNR and PPR.PRR.
TPR.TSR
The Ie~pora~y Segment &egiste~ contains
number of the segment to be accesse~.
TPR.TBR
The lemDora~y ait Register holds t~e bit offset
for
indirect wo~ds or pointers (during ~ddress preparation)
or operands (during instruction execution).
Its value
is
calculdted
during
add~ess
preparation
from
the
contents
of
PRn.CHAR
and
PR~.3ITNO
and other
informatlon provided by
the
Address
Modification
specified
for
the
instruction.
See PRn.CHAR and
PRn.BIrNO above for further detail.
TPR.CA
The ~omputed Address register contains the word offset
01
indirect
words
or pointers
(during adddress
preparation)
or
operands
(dJring
instruction
execution).
QESCRIPTOR
~~HI-aASE
the
segment
REGISTER 1US3R.DBR)
formata - 51 blts
Even Word of V-pair
2 2
;5 !t.-
0
II
I
I
I
10 0 0
L -_ _o_0
ADDR
I
3
~
0 0 000
0 01
12
24
I
Odd Word of V-pair
0 0
-lL1
1. I
101
I I
1
BND
--------
Figure 4-14
1 1 2
2 2
1 1
ft-2. _ _ _ L~--1_L-.
I 1
:
I
: 0 0 0 OlUl0 0 0 01
,
I I
1ft
4 1
3
~
1
I
STACK
I
4
12
I
Descriptor Segment Base Register (OSBR,J8R) Format
A
lo~ical
combination of
various Appending Unit registers.
The data is
pictured in the format expected by the load Oescriotor3ase Register (l08~)
and Store Descriptor Base Register (SOOR) instructions.
Bits pictured as
REVIEW DRAFT
SUOJECT TO CHANGE
October, 1975
4-1&
AL39
·0· are reserved and must have the value O.
[ynctloo.1
The Descriptor Segment Base Re]ister contains information concerning the
Descriptor Segment for a process.
The Descriptor Segment holds the Seg~ent
Descriptor Hords (SOWs) for all segments accesslbl e bv
the process.
The
functions of its individual constituent registers arel
The interpretation of the AllllRress "egister dependS
the value of OSBR.U.
OSBR.BND
E~~
DSBR.ADOR
u=o
The 2~-bit main store address of
for the Descriptor Segment.
U=l
The 2~-bit main store address
Segment.
The
on
coo~
of
the
the
Page
Table
Descriptor
aou~
register contains 14 most significant bits of
highest
10 word block of the Descriptor Seg~ent
that can be addressed wIthout causing an
Access
Violation.
~he
OSBR.U
The U register
Is a flag specifying whether
the
descriptor segment is unpaged (U = 1) or paged (U = 0).
OSBR.STACK
The SI~ register contains the upper 12 bits of
the
15-bit stack base segment numbe~.
It is used on1v
during the eKecution of the CALL6 instruction.
(The
Segment
Number of the Stack Se~ment
for a running
process is given bv 8 • OSBR.STACK • PPR.PRR.)
REVIEW DRAfT
SUB~ECT TO CHANGE
October. 1975
1t-17
Ettm.a.1.!. - 85 bi ts each
Even Word of V-pairs as stored
Store Segment Descriptor Registers
by
_1o____________________,________
(SSD~)
_________2 2 2 2
__ 2 3 3 3 35
3_~_2_l
_3_~Z_3
J
I
J
I
I
I
J ______________________________________________
ADD R
I ___
R __1_____1_
1 I
~2 I
R3 ;10 0 0 II
~J
~I
2~
3
3
3
3
Odd Word of Y-palrs as stored by Store Segment Descriptor Registers (SSDR)
3 3
555 555 555
JO~
~1~J~
1
Da~a
7
1
__________~_'-1-~_L5~6_7~8~_________
1111:111
6 7
11
BOUND
JRJEIW:PJUIG1CI
____________________________
: I I I ; I
14 1 1 1 1 1 1 1
Cl
~I~l
11+
as stored by Store Segment Descriptor POinters (SSOP)
D
I
t
~4
J
ao
POINTER
;
222
1 1
!t ~
It
0
o
0 0 0 0
J
15
Figure 4-15
o
1 I
0 0
.
a OIFIO
J ,
12 1
3 3
3
1 Z
~
I
0 0 01
I
4
USE
I
I
,. I
Segment DescrIptor Word Associative Memory (SOWAM) Format
IlncriDtlop=
Sixteen logIcal combinations of registers and flags from the Appending unit
comprising the Segment Descriptor Word Associative Mem~ry Assembly.
The
registers are numbered from 0 through 15 but are not directlv addressable
by number. 81ts pictured as "D· are reserved and must ~ave the value D.
segmentation in the Hultics Processor is implemented by the
Appending Unit
(See Section V, Address -- Segmentation and Paging for
details). In order to per~lt addreSSing by Segment Num~er and offset as
prepared in the Temporarv Pointer Register (described above), a table
containiny the location and status of each accessible segment must be kept.
This table is the Descriptor Segment and is uni~ue to the pr,cess.
The
Descriptor Segment for a running process is located by information held in
the Descriptor Segment Base ~egister (OSBR) described a~ove.
Hard~are
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
4-16
Al39
Every time an Effective Segment Number (TPR.TSR) is preoared, it is used as
an indeK into the Descriptor Segment to retrieve
the Segment Descriptor
Word
(SmO
for
the
tdrjet
segment. To reduce the 'lumber of main store
references reQuired for segment addressing, the SOWAH provides a
content
addressable store to hold the sixteen most recently referenced SOWs.
Whenever
a reference
to the SOW for a segment is reQJired, the EffectIve
Segment
Number
(TPR.TSR)
is
matched associatively
against
all
16
SOWAH.POINTER registers (described
below).
If
the SOWAH match logiC
circuitry indicates a Mh!t·, all usage counts (SDWAH.US~) greater than the
usage count of the "hit· register are decremented bV one, the usage count
of the "hit" register is set to 15, and the contents of the "hit· register
are read out
into the address preparation circuitry as necesary.
If the
SOWAH match logic does not indicate a "hit", the SOW is fetched
from .aln
store and loaded int~ the SDWAM register with usage cou~t 0 (the "oldest"),
all
usage counts are decremented
by one with the n!~ly loaded register
rolling over from 0 to 15 t and the newly loaded registe~ is read out
into
the address preparat Ion c ircu! try as necessary.
Faul ted SOWs are loaded
into the SOWAH.
The functions of the constituent registers and flags of each SOWAH register
area
SDWAf1.AODR
The Interpretation of the
the value of SDWAH.U.
~&ress
u=o
The 24-bit maIn store address
for the target segment.
U=1
The 24-bit
segment.
~ain
store
~egister
depends
~f
the
Page
of
the
address
on
Table
target
SOWAH.R1
Upper limit of read/write Ring Bra=ket.
VIII. Hardware Ring Implementatlon)
(See
Section
SOWAH.R2
Upper limit of read/execute Ring Bracket.
VIII, Hardware Ring Implementation)
(See
Section
SDWAH.RJ
Upper limit of call Ring Bracket.
Hardware Ring Implementation)
SOWAH.BOUND
The upper limit of segment addresses stated as a nu~ber
of
16 word blocks.
A seg~ent add~ess (TPR.CA) wlth a
block address larger than this, value will
cause an
Access Violation, Out of Segment Bo~nds, Fault.
SOWAH.R
&ead permiss ion bi t.
If
this bi t
access reQuests may be honored.
SOWA H.E
Execute permission bit.
If this bit is set ON, the SOW
may be loaded into the Procedure POinter Re~ister (PPR)
and control transfered to the segment for exectulon.
SDWAH.W
~rite permission bit.
If this bit
access reQuests may be honored.
SDWAH.P
erivileged flag bit.
If this bit is set ON, privileged
instructions
from
the segment m3Y be e~ec~ted
if
PPR.Pi~~ is O.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
(See
is
Is
Section
set
set
ON,
ON,
VIII,
read
write
4LJ9
[.un~liJln
flag bit. If this bit is set ON, the segment
is unpaged and SOWAH.AODR is t~e 2~-blt main store
address of the base of the segment. If thIs bit is set
OFF, the segment is paged and ~OWAM.AOaR is the 2~-bit
address the array of Page TabJe Words (pnofs) for the
segment.
SOWAM.U
~npaged
SOWAH. G
~ate
SOWAH.C
~ache
SOWAH.CL
~all ~imiter value.
If the segment is gated (SaWAH.G
set ON), transfers of control into the segment must be
to segment addresses no greater tha~ this value.
SOWAM.POINTER
The Effective Segment Number used
from main store.
SOWAtt.F
full/empty bit. If this bit is set ON, the SOW in the
register
is valid.
If this oit is set OFF, a ""hit- is
not possible. All SOWAH.F bits are set OFF by the
instructiorys that clear the SO WAH.
SOWAM.USE
USagE count for the register. The SOWAH.USE fIeld is
used to maintain a strict FIFO Queue order among the
SOWs. When an SOW is matched its USE value is set to
15 ("newest")
and the Queue is relrdered. SOWs newly
fetched from main store replace the SOW with USE value
o (-oldest") and the Queue is reordered. SOWAH.USE is
set the internal (and invisible) SO~AH register nu~ber
by instructions that clear the SOWA~.
REVIEW DRAFT
SUBJECT TO CHANGE
October. lq75
control bit. If this bit is set ON, calls into
the segment must be to an offset no greater than the
value of SOWAH.CL as described beloN.
control bit. If this bit is set ON, data
the segment may be p'aced in the cache store.
It-2 a
to
fetch
this
from
SOW
AL39
f.m::ull - 51 bi ts each
Data as stored by Store Page Table Registers (SPTR)
0
1 1
.J1
---La
I
I
I
10 0
AOOR
Z Z 3
1 3 Q
o 0 o
---1.
L-
18
I
o
0 0 0
3
2
J
I
0 D:HIO 000 0 01
I
I
6
11 1
-----,
Data as stored bv Store Page Table Pointers (SPTP)
0
1 1
.J1
!t 2
I
J
PAGENO
I
POINTER
I
15
Figure 4-16
t
tFIO
--L1_
I
1
~
2 2
-LL1
o
12 1
Page Table Word AssociatIve Memory
(PT~AH)
3 3
3
1 Z
2
0 OJ
,. I
I
1
USE
J
It
Format
Ilescriotlonl
Sixteen logical combinations of registers and flags from the AppendIng Unit
comprising the Page Table Word Associative Memory Asse~bly.
The registers
are "umbered from 0 throu1h 15 but are not directly add~essable by number.
Bits pictured a~ "0" are reserved and must have the val~e o.
EUDctlQn'
paging In the Mu'tics Processor Is implemented by the AppendIng
Unit (See Section V. Address -- Segmentation and Paging for details).
In
order to permit segment addressing Dy Page Number and page offset as
derived from the Effective Address prepared in the Temporary' Pointer
Register (TPR.CA described above). a table contaIning the loc~tlon and
status of each page of an accessible segment must be ke~t. This table is
the Page Table Word Array (PTWA) for the segment that is located in the
System Segment table (SST) (a supervisory ring 0 data b~se) and is sharable
by all processes. The PTWA for an accessible paged seg~ent is located by
information heJd in the Segment Descriptor Word (SOW) for the segment.
Hard~are
Everv time an Effective Address (TPR.CA) for a paged segment is prepared,
it is separated into a Page Number and a page offset. The Page Number is
used as an index into the Page Table Word Array to retrieve the Page Table
Word (PTW) for the target oage.
To reduce the num3er of main store
references reQuired for paging, the PTWAM provides a content addressable
store to hoi d the sixteen most recently referenced PTWs.
Whenever a reference to the PTW for a page of a paged segment is reQuired,
the Page Number (as derived from TPR.CA) is matched associatively against
all
10
PTWA:1.PAC;E~J\)
registers
(described below) a1d, simultaneovsly,
REVIEW OR~FT
SUBJECT TO CHANGE
OctOber, 1975
it-Zl
AL39
TPR.TSR is matched against PTWAH.POINTER (described below). If the PTWAH
match logic circuitry indicates a "hit", al I usage counts (PTWAH.USE)
greater than the usage count of the "hit· register are decremented by one,
the usage count of the "hit" register is set to 15, and tne contents of the
"hit" register are read out into the address prepar~tion circuitry as
necesary.
If
the PTWAM match logic does not indicate a "hit", the PTW is
fetched from main store and loaded into the PTWAH ~egister with usage count
o (the ·oldest"), all usage counts are decremented by one with the newly
loaded register rolling over from 0 to 15, and the newly loaded register is
read out into the address preparation circuitry as neceisary. Faulted FTWs
are not loaded into the PTWAM.
The functions of the constituent registers and flags of each PTWAH register
are.
~51i..S.1.e1:
PTWAH.AOOR
The AUl&ess register holds the 18 m~st significant bits
of
the 24-blt main store address of the page. The
hardware ignores low order bits of the page address
accord~ng to page size based on the fol lowing •••
Page Size
In words
6ft
128
25&
512
102't
2048
ft09&
ADOR 31ts
ignored
none
17
16-17
15-17
14-17
13-17
12-17
PTMAH."
Page Hodlfied flag bit. This bit is set ON
the PTW is used for a store type initruction.
bit changes value from 0 to 1, a special extra
generated to write it back into the PTW in the
PTWAM.POINTER
The Effective Segment Number used
from mai n st ore.
PTWAH.PAGENO
The 12 mos t significant bi ts of the 18-bit £1 feet i ve
(TPR.CA) used to fetch this PTW from main
Address
store. low order bits are forced to zero by the
the PTWA in oex
hardware and not used as oart of
according to page size based on the following
Page Size
in words
to
fetch
whenever
When the
cycle is
PTWA.
thiS
PTN
PAGENJ bits
for=ed
64
nO/"le
128
256
512
11
10-11
09-11
102'+
08-11
2048
07-11
'+096
06-11
PTWAM. F
[ull/empty bit. If this bit is set ON, the PTW In the
register
is valid. If this bit is set OFF, a "tlit" Is
not possiole. All PTWAM.F otts are set OFF by the
instructions that clear the PTWAH.
PTWAH.USE
u.s.ag£ count
used
REVIEW OR~FT
SUBJECT TO CHANGE
October, 1975
to
for the reJister.
The :lTWAM.USE field Is
a strict FIFO QJeue oraer among the
~aintain
't-22
Al39
PTWs. Hhe~ an PTW is matched its UiE value Is set to
15 '''newest··t and the Queue is ,.eordered. PTws ne"d y
fetched f,.om main store replace the PT~ wit~ UiE value
o ("oldest"t and the Queue is ,.eorjered. PTWAM.USE is
set the internal (and invisible) PT"AH reg ister numbe"
by inst,.uctions that clear the PTWA~.
EQrmat: - 35 bits
Data as stored
instruction
0 0
o
0 0 0
o 0
by
Store
Central
0 0 1 1 1 1 1 1 1
1 Z ;5 !t 2 2
I I I I 1 1 1 J J
•
Figure 1t-17
Register
2 2
2 2
;5 L-_L.!l
1 2
-1LJ.--Z.J_L2-~-.a.-3. Q
a I I I I I I I
lalblcldlelflglhlilJ Ikl11mlnlol01
LLLL1--L.l I I I I I J I I • J
1 111 1 1 111 1 .1 1 1 111
Processor
3 D
I
IAA
I
I
I
lAB
I
It
I
I
.
lAC
-.1._
It
It
(SCPR),
TAG = 01,
3 3 333
1 Z ;5
!t
~
I I I I
lAO
Iplolrlsl
I I I •I I
It 1 111
I
Fault Register Format
Q.escrlpt ionl
A logical coabination of flags and registers all
located in the Control
Unit.
The registe,.
is stored A~~ k'eared by the SC~R (tag 01) com~and.
Note that the data is stored into the l121:J1 lL.a.lt:. at locat ion Y and that the
contents of Y+l are cleare2. The Fault Register cannot be loaded.
fynctlQnl
The Fault Register contains the conditions in the Processor for several of
the hardware faults.
Oata is s~robed into the Fault Register during a
fault sequence. Once a bit or field in the fault Register has been set, it
remains set until
the register is cleared.
The data wil'
not be
overwritten during subsequent fault events.
The reader·s attention is directed to another aDPare~t
anomoly in the
deSign of
the MuJtics Processor as an enhancement to an existing design.
It will be noted that the Fault Register recorgs events from only ports A
through O.
These four ports are the
limit of c~nnectability of the
existing deSign and, since all eight ports are reported in Control Unit
Data (described below), no change "as made in the FaJlt Register for the
added ports. Data reported for ports A through 0 are valid in both
I ocat ions.
The functions of the constituent flags and registers arel
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
4-23
AL39
g~ ~glster
a
ILL OP
An Illegal operation code has been
b
ILL
An illegal Address Modifier has
c
ILL SUI
HO~
dILL PROC
~etected.
bee~
detected.
An illegal BAR Mode procedure has been encountered.
An illegal procedure
encountered.
other
than
3AR
Hode
has
been
e
HE'"
A nonexistant main store address has been requested.
f
OOB
A BAR Mode ooundary violation has occured.
g
WRT INH
An illega' decimal digit has bee, detected
Decimal Unit. (Flag name 1s obsolete)
h
PROC PARU
A parity error has been detected In the upper
of data.
3&
i
PROC PARL
A parity error has dtected in
data.
bits
SCaN A
A SCONNECT Signal has been received through
SCON B
A SCONNECT signal has been received through port B.
SCON C
A SCONNECT signal has been received through port C.
m SCON 0
A SCONNECT signa' has been received through port O.
k
the
lower
36
by
~ort
the
bits
of
A.
n
OA ERR1
CPU/SCU interface sequence error 1 has been detected.
(SDATA-AVAIL received with no prIor SINTERRUPT sent.)
o
OA ERRZ
CPU/SCU interface sequence error 2 ~as been detected.
(Multiple SDATA-AVAIL received or 'DATA-AVAIL received
out of order.)
IAA
Coded Illegal Action, Port A. (See Table
~-2
below)
lAB
Coded Illegal Action, Port B. (See Table
~-2
below)
lAC
Coded Illegal ActIon, Port C. (See Table 4-2 below)
lAO
Coded Illegal Action, Port O. (See Table
p
CPAR DIR
A parity error has been detected
directory.
q
CPAR STR
A data parity error has
store.
r
CPAR IA
An Illegal Action has been received from an SCU
been
In
~-2
the
detected
in
below)
cache
store
the
cache
du~in9
a store operation.
s
CPAR BlK
REVIEW DRAFT
SUBJECT TO CHANGE
Oc tober. 1975
A cache parity error has occured
data block load.
du~ing
a
cache
store
~L39
Tabl e 4-2
CJuk
P[:lgI:11~
System Controller Illegal Act ion
Processor
Ullll.
C~des
&u:i.QO
5
1
CHO
STR
CHO
No i I I ega I action
Unassigned
None~istent address
Stop on condition
12
11
10
CHO
PAR
PAR
PAR
Unassigned
Oata parity, store to S:U
Oata parity in store
Oata parity in store and store to SCU
7
CH!)
CHD
CMO
STR
Not control
Port not enaoled
tHega I command
Store not ready
14
2
PA~
15
16
6
8
9
PAR
PAR
PAR
ZAC parlty. CPU to SCU
Data pari tv, CPU to SCU
ZAC pari t y, SCU to store
Data parity. SCU to store
00
01
02
03
04
05
06
07
10
11
12
13
4
13
17
3
MODE REGISIU
Eo[:matl - 33 bits
Even word of V-pair as stored by Store Central Processor
~egister
= 06. instruction
(SCPR), TAG
0 1 1 1 1 1 122 2 2 2 2 222 2 333 333
4 5 £p 7 8 9
1 J I :
Q
J
I
FFV
£1 ____________________• ___________
Q
1 2 3 U-LLa 9 Q 1 2 3 It 5
aP co aE
: It: I 2
1 1
JOlalb:-------------------:iJJlkll:mIO Oint
1-1 ; Scld;e"; 9 1 h
__
~_1-1-l-.;-4J
15 1 1 1
10 1 1 1 1 1
1 111
Figure 4-18
2
2
~t~;
2 1
2
Hode Register (HR) Format
Ofikriotion!
A
109 I ca I
asse mb I age
of
flags and reg i sters from the Contro 1 Uni t.
The
Hode RegIster and the Cache Hode Register are both stored into the V-oair
bv
the SCPR, TAG = 06, instruction. The Mode Re~iste~ is loaded with the
Load Central Processor Register (Lcpro, Tag = 04 instruction.
Bits
pictured as "0" are reserved and must have the value o.
The
function~
REVIEW DRAFT
SUBJECT TO CHANGE
Oc t ober. 1975
of the constituent flags and registers are:
4-25
FFV
A -floatIng fault vector- address.
The 15
most
significant bits of the Y-blockS ~ddress of four word
pairs constituting a "floating fault vector". Traps to
these floating faults are senerated by othe~ condItions
setable by the mode registe~.
a
OC TRAP
Trap on OPCODE match.
If this bit is set ON ang OPCOOE
matches the operation code of the instruction for which
an address is being prepared (including
indi~ect
cycles),
generate the secor)d floating fault (XED
FFV+Z). (See NOTE below)
b
AOR TRAP
Trap on ADDRESS match. If this bit is set ON ang the
Computed Address (TPR.CA) matche~ the setting of the
Address Switches on the Processor Haintenence pane',
generate the fourth floating fault (XED FFV+6). (See
NOTE below)
OPCODE
The operation code on which to trap If OC TRAP (bit 16,
key a) is set ON or for which to strobe all CU cycles
into the CU History ~egisters if O.C,t (bit 29, key ))
is set ON
Processor conditions codes as follows if OC TRAP (bit
16, key a) and O.cst (bit 29, key J) are set OFF and t
VOLTAGE (bit 32, key m) is set ON.
ts.n ConditUD
c
Set Control Unit Overlap Inhibit if set ON.
The
Control Unit shall wait for the operations Unit to
complete execution of the ever) instruction of the
current instruction pair before it begins address
preparation for the associated odd instructIon.
The Contro I
Uni t shal J al s:)
wai t
for
the
Operations Unit to complete execution of the odd
instruction before it fetches the next instruction
pair.
d
Set Store Overlap
Unit shaJ I
\IOIait
store fetch (re3d
m~in store access
e
Set Store Incorrect Data Parltf if set ON.
The
Control Unit shall cause inco~rect data pari tv to
be sent to
the SCU for the next data store
instruction and then Sh~JJ reset bit ZD.
Inhibit if S!t ON. The Control
for completion of a current main
cvcles only) before reQuesting a
for another fetch.
Set Store Incorrect lAC Parltv
if
Set
ON.
The
Control
Unit
shall
cause
incorrect
Zone-Address-Command (ZAC) parity to be sent to
tne SCU for eacn main store cy:le of the next data
store instruction anj shall reset bit 21 at the
end of the instruction.
9
REVIEW DRAFT
SUaJECT TO CHANGE
October, 1975
Set Timing Margins if set ON. If t VOLT (bit 32,
key m) is set ON and the Hargin Control switch on
the Processor Maintenance panel
is
in
PROG
position, set Processor timing margins as follows.
AL39
mar:g.iQ
normal
slow
normal
t ast
h
Set +5 Voltage MargIns if set IN. If t VOll (bit
32, key m) is set ON and the H3rgin Control switch
on the Processor Maintenance ~anel is in the PROG
pOSition, set +5 voltage ~argi~s as follows.
Uc.9.i1l
norma I
low
high
norma I
Trap on Contro. unit History Register count overflow if
set ON. If this bit and STROBE ¢ (3it 30, key k) are
set ON and the Control Unit Hist~ry Register counter
overflows, generate the third floating fault (XED
FFV+It).
Further, if FAULT RESET (bit 31, key I ) is
set, reset
STROBE t
(bit 30, kef k),
lOCKing the
history registers.
An LCPR, TA; : Olt, instruction
setting bit 28 ON will reset the Control Unit History
Register counter to zero.
(See NOTE below)
1
... J
k
o.cst
Strobe Control Unit History Registers on OPCODE match •
If this bit and STROBE t (bit 30, key k) are set ON and
the operation code of the current instruction matches
OPCOOE, strbbe the Control Unit History Registers on
all Control Unit cycles (including indirect cycles).
STROBE t
Enable history registers. If this Dit is set ON, all
history registers are strobp.d at 8DPropriate points in
the various Processor cycles. It t~is bit is set OFF
or MR ENABLE (bit 35, key n) is set OFF, all history
registers are locked. This bit is set OFF with an
LePR. TAG
Olt, instruction providing a ·zero" bit, by
an Op Not Complete Fault, and, ~ondltional Iy, by other
faults (See FAULT RESET (bit 31, key I) below). Once
set OFF, this bit must be set ON with an LCPR, TAG
Olt,
instruction providing a "one" bit before the
history registers again become active.
=
=
FAULT RESET
Historv register lock control.
11 this bit is set
ON,
set STROBE t
(bit 30, key k) OFF, locking the higtory
registers,
for all faults inclujlng the
floating
faults.
(See NOTE belo")
m
t VOLT
Test mode indicator. ThIs bit is set ON whenever the
Test/Normal switch on the Processor Maintenance panel
is in Test pOSition and is set OFF otherwise. It serves
to enable the program control of \loltage and Timing
Margins.
n
HR ENABLE
Enable mode register. When this bIt
Is set ON, all
other bits and controls of
the mode register are
active. When this bit is set OFF, the mode register
controls are disabled.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
It-27
AL39
The traps described above (Address match, OPCOOE match.
Control
Unit
History Register counter overflow) occur after c~~pletion·of the next
~g~ lo~u~ii~n follow1n1 their detection.
They a-e handled as Group
VII
faults in regard to servicing and inhibition.
T~e complete Group
VII priority seQuence is •••
NOTEI
1 - con
2 - tro
3 - sdf
.. - OPCOOE trap
5 - Control Unit History Register counte- overflow
o - Address match trap
7 - External interrupts
[ormat: - 28 bits
Odd word of V-pair as stored by Store Central Processor Register (SCPR),
Do, instruction
TAG
=
3 5 5 555 5 5 5 5 5 0 6 06&
677
6
U-1_~4 5 Q ~~l-1_~~ _________ 49~O-a1_
,
I
~1
11"11111111
CACHE OIR ADDRESS
____________________.____________ __
l-1-l I
~J
-
1
I
:
I
J
'J
1-1-1-1-1---1
15 1 1 1 1 1 1 1 1 1 1 1
Figure 4-1q
I
lalbJOlcldle:fIOJglh:il ) :0 0 0 0 0 0: k I
2
6
2
Cache Hode Register (CHR) Format
Description:
A
logical
assemblage of
flags and registers from the control unit. The
Hode Register and Cache Mode Register are Doth stored i~to
the Y-pair by
the SCPR, TAG
00, instruction.
=
The Cache Hode Register data stored is address depenjent.
The algorithm
used to map main store into the cache store (See Sectio~ XX, Cache Store)
is effective for the SCPR instruction. In general, t~e user may read out
data from the directory entry for any cache block by p~oper selection of
certain subfields of the final 24-bit main store address.
In particular,
the user may read out the directory entry for the cache block involved in a
suspected cache error Dy assuring that the reQuired 24-bit
final
add~ess
suDfields are the same as those for the access which produced the suspected
error.
WARNING:
The user is warned that the fauJt handling proc~dure(s)
should be
unencacnable (SOW.C = 0)
and that the History Registers and c~che
should be disabled as Quickly as Possible in order that vital
infomation concerning the suspected error not be Ilst.
The Cache Mode Register is loaded with the Load Central Procesor ~e9ister
(LCPR), TAG
02, instruction.
Those items with an "x" in the column
headed L are Il2.1 loaded with the LCPR instruction. Bits pictured as '·0·'
are reserved and must have the value O.
=
REV lEW DRAF T
SUBJECT TO CHANGE
October, 1975
"-26
AL39
The functions of the constituent flags and registers are.
~}!,
L Rit9ll1tt
x CACHE DIR
ADDRESS
BIT
15 most si~nificant bits
the cache directory
of
the
Dlock
address
from
Cache direct orv par 1 tv error on this ,..ead out
a
x PAR
b
x LEV rUL
c
CSH1 ON
Enable the upper 1024 "ords of the cache
d
CSH2 ON
Enable the lo"er 1024 "ords of the cache
e
OPND ON
Enable the cache for operands
f
INST ON
Enable the cache for i.ns truc t ions
•9
CSH REG
Enable cache-to-register (dump) mode
When this bit is set ON, double precision Operations Unit
operands- (e.g., LOAQ operands) are ,..ead from the cache
according to the mapping algorithm and without regard to
matching of
the full final address. All other operands
address main store as though the ca:he were disabled.
This bit Is reset automatically by the hardware for anv
Fault or Program Interrupt.
h
x STR ASO
Enable store asIde
When this bit is set ON, the Processo~ does not wait fo,..
maln store cycle completion after a store operation but
proceeds after the cache cycle is com~lete.
i
x COL rUL
Selected cache column is ful I
x RRO A,B
Cache round robin counter
k
LUF
HSB,LSB
The selected column and level is loaded wIt h ac t 1 ve
Lockup time,.. setting
The Lockup Timer may set to
according to the setting of this
LUF
.It.a..J.l.lA
four
values
flel~.
Lockup
l~
0
2 ms.
1
2
3
4 ms.
8 ms.
16 ms.
The Lockup Time,.. is set to 1& ms.
initialIzed.
C Q NI RO L UN I
different
data
w~en
the ProceSSor is
IJt.llLtil.S.I.Q!ll...R~lER.S.
E.l2..r:.ull - 72 bIt s each
Even word as stored by Store
instruction
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Cent~aJ
Processor
4-29
Re~ister
(SCPR),
Tag
=
20,
AL39
a 0 000 0 0 aDD 1 1 1 1 1 1 111
223
3
1 ? 3 It 5 .LL.a.--9._JL-LZ.J_!t-2_LLa _ _ _ _ _ _ _ _ _ l~ _
___S_
1111111111,.,1:11,.
:1:
I
I a I b I c I dIe J f : g I h J .i I J 1 k I I I m J n I 0 1p I Q 1 r'
a P co DE
I r • t-ll
TAG
•
J ; ; I 1-1-1-1-1-1-1-1-1-1-1-1-1-1-1
_____ l_L_~I__________~1
Q
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Odd word as
instruction
stored
by
10 1 1
Stcu-e Central Processor register (SCPR), TAG = 20,
0
1 1
D
-LB
2 Z
,
CHD
ADDRESS
J
18
Figure 4-20
3 3 3
I
;1 !t 2
I I J I
SEL
J
I
I
1 I
Islt lulvJwlxlylzl"Z
-Ll_I_LLl ;
---1
I
..L..-.-
Z Z
Z L---LI __
I
I
6
5
J I I
It 1 1 1 1 1 1 1 1 1
Control Unit (CU) History Register Format
Il~eriptlonl
Sixteen logical combinations of flags and registers from the Control
Unit.
The sixteen registers are handled as a rotating Que~e controlled by the
Control Unit History Register counter. The counter 1s always set to the
number of
the oldest entry and advances by one for each history register
reference (data entry or SCPR).
True multicycie instructions (such as
~Iprl. Ireg, rcu, etc.) will have an entry for each of t~eir cycles.
fyne! 10nl
A Control
Unit History Register entry shows the conditions at the end of
the Control Unit cycle to which it applies.
Tne sixteen registers will
hold the conditions for the last sixteen Control Unit cycles. Entries are
made according to controls set in the Mode Register. (See Mode Register
above)
The meanings of the constituent flags and registers arel
a
PIA
prepare instruction address
b
PQA
prepdre operand address
c
RIW
reQuest indirect word
d
SIW
restor indirect word
e
POT
prepare operand tally (indirect tally chain)
PON
prepare operand notally (as for POT except no chain)
g
RAW
reQuest read-alter-reririte word
h
SAW
restore read-alter-rewrite word
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
1t-30
Al39
ls.sl~ Elil!L.tiaU
TRGO
transfer GO (conditions met)
XDE
execute XED from even IC
XOO
execute XED from odd IC
IC
execute odd instruction of the current pair
•
RPTS
execute a repeat operation
n
WI
wait for Instruction fetch
0
AR FIE
1
p
XIP
NOT prepare
Q
FLT
NOT prepare Faul t address
r
BASE
NOT BAR mo de
OPCODE
current operation code
1
Program Int.errupt lnhibl t bit
p
PoInter register flag bit
TAG
Currrent address modifier
This modifier Is replaced bv the contents of the TAG
fields of indirect words as they are fetched durlng
indIrect chains •
ADDRESS
Current Computed Address (TPR.CA)
ettO
SCU
I
k
...
SEL
selected)
= Computed
Address (TPR.CA) has valid data
Progra~
Interrupt address
C01'llilan d
Port
select
bits. (Valid only If Port A through D is
s
XEC-INT
A Program Interrupt Is present
t
INS-FETCH
Perform an instruction fetch
u
CU-STORE
Control Unit store cycle
v
OU-STORE
Operatons Unit store cycle
"
CU"'LOAD
Control UnIt 'oad cycle
x
QU-LOAD
OperatIons Unit 10ad cvcle
DIRECT
direct cycle
z
PC-BUSY
Port control logic not buSY
..
BUSY
Port interface busy
y
----
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
"-31
AL39
(ormat a - 72 bi ts each
Even word as stored by Store
instruct Ion
o
cent~al
Processor
Regsiter
00111111111
o
=
(SCPRt,TAG
J
ZZ
0 1 2 3 It 5 fLLJL8 _ _ _ _ _ _ _ -LL_
RP REG
: I
J I J J :
5
~-9.
I
.---------------------------------101
1
Or COPE
I a:
b
Ic.uuEAC,' I
91
Odd word as
instruction
o
a
0 0 0
stored
. 311
by
I I I 1 I
JelflglhJiljlkJllml
--L.1_LL.L.L1
21
I
I I
9111111111
= 40,
Store Centra' Processor RegIster (SCPR), TAG
0 0 0 0 0 1 1 1 1-1 1
D 1 2 3 It 5
RS REG
A-l-A-3-i-1-a2-¥3~4_5'_
1 1
3
__~Z_8~_____________
5
I I I 1 I :_1_1_1_1_'_1_'_1_'_'
I
InlolplqlrIAIQJOJlI2J3J415.&J710 0 OJ
ICT TRACI'.
IPR - i I I ega I address or modIfier
Fo~
-
1
d
x ORB
x ISP
Fo~
1
e
x R-OFF
x IPR
Fo~
x OWB
x NEA
Fo~ ACV - out of write bracket
For STR - nonexistent add,..ess
1
ACV
out of read bra:ket
For IPR - i l I ega I s I ave pI"'ocedure
ACV - read bit is of f
IPR - i I legal EIS digit
Fo~
1
9
x W-OFF
x 008
For ACV - w~ite bit is off
For STR - out of bounds
1
h
x NO GA
For ACV - not a gate
1
x OCB
For ACV
1
x OCAlL
For ACV - ouhtard call
x BOC
For ACV - bad
x INRET
For ACV
1
k
1
out of call
out~ard
b~a:ket
call
- inward return
1
II
x CRT
For ACV - cross rIng trans fer
1
n
x RAlR
For ACV
1
0
x AH-ER
Fo~
1
p
x 0058
For ACV - out of segment :>ounds
1
Q
x PARU
For PAR - processor parity upper
1
~
x PARL
Fo~
1
s
x ONC1
For ONC - CPU.lS:U seQuence error '1
1
t
x ONeZ
For ONC - CPU.lSCU seQuence
1
x IA
SCU illegal act Ion lInes (See Table 4-2)
1
x IACHN
Illegal action CPU port.
1
x CNCHN
For CON - connect eClOe) ::PU port
1
x FII AOOR
ttodu 10 2 fau It lin te~~upt lIector address
x F/I
Fault/interrupt bit flag :>It
1
u
ACV - associ ative memory error
PAR -
a
1
Z
TPR. TRrt
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
ring alaI"'''
p~ocessor
pa~itf
lower
e~ror
.Z
= inte~rupt
= f au I t
Tempo~ary
ring
~eglster
AL39
2
TPR.TSR
Temporary segment
2
CPU
CPU number
2
DEL TA
Address increment for repeats
3
TSNA
Pointer Register number
or for EIS operand '1
as •••
3
a
3
b
PRNO
registe~
f~r
non-EIS operands
substructured
f~rther
Pointer register number
1
= PRNO is valid
3
TSNB
Pointer Register numoer f~r EIS operand
further substructurej as for TSNA above
.2
3
TSNC
Pointer Re]ister number f~r EIS operand
further suostructured as for TSNA above
'3
3
TEMP BIT
8ITNO field
(TPR.TBR)
It
PPR.IC
Instruction counter
a
ZERO
Zero indicator
It
b
NEG
Negative indicator
It
c
CARY
Carry indicator
'+
d
OVFl
OverfJo~
'+
e
EOVF
Exponent overf low 1 ndicat:)r
f
EUFl
Exponent underflow indicator
9
OFl"
Overflow mask indicator
h
TRO
Tallv runout indicator
i
PAR
Parity error indicator
PAR"
Parity mask indicator
8"
Not 8AR Hode indicator
TRU
EIS truncation indicator
m
HIF
Mid-instruction interrupt
n
ASS
Absolute mode
.
It
It
,.
k
x TPR.CA
5
of
Temporary
Pointer
indicator
Current Effective Address
5
a
RF
First cycle of a repeat oJeration
5
b
RPT
Execut 1ng a repeat
5
c
RD
Executing a repeat double
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Register
AL39
5
d
RL
Executing a repeat link
5
e
POT
Prepare operand tally
This flag is up until tne indirect word of an
IT indirect cycle is successfully fetched.
5
f
paN
Prepare operand notally
This flag is up until the in1irect ~ord of a
"return" type instruction is successfully
fetched.
It
indicates that there is no
indirect chain even thoug, an indirect
fetch
is being done.
5
g
XDE
Execute double from even
5
h
XOO
Execute double from odd
5
1
ITP
ITP cycle
RST
Restart this instruction
ITS
ExecutIng ITS indirect cycle
FIF
Fault occured during
5
5
k
5
CT HOLD
5
Ie
Ie
inst~uction
fetch
Contents of the -remember modifier" register
&
Word & is the contenti of the "working
instruction register" and reflects conditions
at the exact poInt of address preparation
when the
fault/interrult
occured.
The
ADDRESS and TAG fields are replaced with data
from pointer registers,
indirect pointers,
and/or indirect words du~ing each indi~ect
cy'e.
Each instruction of the current pair
is moved to this regiiter before actual
address preparation begins.
1
Word 7 is the contents of the -instruction
holding register".
It contains the odd lJIord
of the last instruction pair fetched fro~
main store. Note that, orimarllv because of
store overlap. thiS initructio~
is
not
necessarily paired with the instruction in
Hord o.
E~~i1
-
288 bits, 8 machine words
REVlfH OR~fT
SUBJECT TO CHANGE
October, 1975
AL39
Oata as stored bV store Pointers and Lengths (SPL)
o
n
~~C~
inst-uetion
0 0 111
-L-_______a-3_.tLl_2_ __
t
J : I J
10 a 0 0 0 0 0 0 OtZ:0Z0:
1
LLLL911 1
3
5
CH TALLY
o
3
J
L
1
1
I
10 0 000 0 00 0 0 0 0 0 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01
I
3&
2 2 2 2 2
0
I
I
I J
1
10' T A 10
01 PTR
J
I
I
24 1
o
0
0
I
I
I
I
01I1FIA:0 0 01
.I
I
I I
3
3
2
I
I
~
J
~
.
-
-
1
-
LEVEL ______ :0 OJ ________ .____________________________________
01 RES
J
10
2
2,.
0
D
-&______ ._________________________._____________
J
I
2 3 3 3 333
9 Q 1 2 3 It ;
I
1111111
10lTA 10 0 OJRIF:A101010:
_________________________________._______________
;; I I 1 ; J
24 1
2
3 1 1 1 1 1 1
I:
~
I
22222
~3~~
02 PTR
~I~J~~;__
0
a
10 0
o
1 1
3
1 Z
2
1
0 0 0 0 0 0 0 0 01
I
02 RES
J
I
I
12
21t
2 2 2 2 2
0
g
2 3 3 3 3
3
_~....LL3
2
.
I I
1 I I I
10lTA 10 D OIRIFJAI
03 PTR
J
J
24
•
1
I
--1
2
I
I
I
I
I
3 1 1 1
•I
JHP
I
3
0
1 1
3
D
1 Z
2
1
I
I
2 fz Z
J !t
1
fl
I
3 1 1 1
111
:
2
2
I)
2
~-L1.-L-
J.
!1
3
,
• . .
,
Z.
2 3 3 3 3
l-L2_LI __ -Lll.....LL3
Q
10 0 0 0 0
a
ODD 0
a
OJ
L
03 RES
!
12
Figure 1t-25
24
Decimal Unit Data Format
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
AL39
llescrip.1Jjm!.
A logical collection of ftags and registers from the Decimal
pictured as "0·· are reserved and must have the value O.
Unit.
~its
Eu.octlool
The Decimal Unit Data allows the Proce~sor to restart a~ EIS instruction at
the point of
Interruption when it is interrupted by an Access Violation
Fault, a Directed fault, or (for certain EIS Instr.Jctions) a Program
Interrupt.
Directed faults are intentional, and mls~ Access Violation
faults and Program Interrupts are recoverabl e.
The data are restored wIth the Load Pointers and Lengthi (LPL) instruction.
fields having an "x'· in the column headed L are o~l restored.
When
starting execution of an EIS instruction, thp. decimal unit re3isters and
,flags are not initialized from
the
Operand
Descriptors
if
the
Hid-instruction Interrupt Fault (HIF) indicator is set IN.
The meanings of the constituent fla3s and registers arel
E1li.tLJ:til.m~
He aning
0
z
All bIt string instruction results are zero
0
IJ
Negative overpunch found in 6-4 expanded move
0
CHTALLY
The number of characters examined bV the SCAN, TCT,
TCTR Instruction (up to the interru~t or match)
2
01 PTR
Address of last double word accessed by
Descriptor 1; bits 17-23 (bit add-ess) valid
initial access
~e,g
.L
TA
2,4,6
2
x I
or
Operand
for
o~ly
Alphanumeric type of Operand Oescriotor 1,2,3
Decl mal Uni t interrupted flag;
a
copy
Hid-Instruction Interrupt Fault indicator
of
the
2,4,6
f
FIrst time; data in Operand Descriptor 1,2.3 is valid
2,1t,6
A
Operand Descriptor 1.2,3 is active
3
LEVEL
Difference in the count of cha~acte-s loaded
CPU and cha~acters stored back to main store
3
01 RES
Count of characters remaining in Operand Descriptor 1
It
02 PTR
Address
of
last
Descriptor 2;
inlti31 access
4,6
x R
double
word
bl ts 17-23 (bit
ac:essed
add~ess)
by
into
the
Operand
valid only for
Last cvcle performed must be repeated
5
02 RES
Count of characters remlining in Operand Descriptor 2
6
03 PTR
Address of the last double word accesssed by Operand
Descriptor 3; bi to; 17-23 (bit add"ess) valId only for
initial access
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
AL39
()
JHP
Descriptor count; number of words to skip to find
the
next instruction following this multi"ord instruction
7
03 RES
Count of characters remaining in Operand Descriptor 3
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
4-48
AL39
SECTION V
ADDRESSING -- SEGMENTATION ANOPAGtNG
The Mu.tics Processor is able to access the maIn store
modes; Absolute Hode or Append Mode.
in
~lther
of
two
The Processor prepares an Effective Address for each maIn store reference
for instructions or operands. An Effective Address consi$ts of a 12-bit segment
number and an lS-bit offset withIn that segment. An UUlllis d~fined as the
number of machine words from the ~:Itm1 ~ or orIgin to the referent.
The
Processor uses the Effective Address to generate a 24"'bit Una1. ait!.t~. The
t Ina I addres's is used either as a d lrecf operand or as an address 1:O,r
amal.t\
store access. The variOUS means of Effective Address for'raation ar'e itXpi\a,lned 1n
Section VI. Effective Address Formation. The gener.tionof t'heflna~' ~a(jde$$ 1s
different In the two Addressing Hodes •
.
Ab$olut. Hode
tn Absolute Hode, the segment number is null, that is., undefined'. and the
segment base Is the origIn of lIain store~ The final add~ess 1s g'enerated by
high-order zero f!lUng the offset with six binary O·s • . Absolute Kode
addressIng Is limIted to the first 2&2.14~ Nords of main sto~ ••
In Absolute Hode, al. instruction fetches are made from Absolute addresses.
Instruction opera~ds may be Jocated anywhere in main store and may be accessed
by specifying ITS Address Modification tor the instructIon or by loading a
PoInter
Register
with an appropriate value and specifying ITP Address
Modification or using bit 29 of the instruction word. T~e use of ITS or ITP
Address MOdifIcation in an Indirect Word MIlt have the same effect.
WARNINGI
The use any of the above constructs in Absolute Hode places the
Processor in Append Mode for one or more Addr~ss Pre~a~atlon c'cJes~
All necessary r~glsters must be properly loaded and all Fault
conditions must be
conside~ed
(See
Appen~
Hode beI3W).
If a transfer of control is made with any of the abo~e constructs, the
processor remains in Append Hode after the transfer and sUbse~uerit instruction
fetches are _ade in Append Hode.
REVIEW DRAFT
SUBJECT TO CHANGE
OctOber, 1975
5-1
AL39
AI though no segment is defined for Absolute Hode,
Is .ay be helpful
to
understanding to visualize a virutal,unpaged segaent ~verlaying t~e first
Z6Z.1~~ words of main store.
ADPend ~
In Append mode. the appending mechanism is employed for atl maIn store
references.
The appending mechanism is described in ·SegmentatIon" and "Paging"
folloMlng in this section.
SEGHENTATIOH
A HuUlcs sunnl is defined as an array
limIted) size containing arbitrary data.
ProcesSor by a s~l Dymh£C (~). unique
that Is asslgnei by the operating system Nhen
t he process.
of machine words of arbitrary (but
A segment is l~entlfied within the
to the segment
for the process,
the segment is first reference~ by
To simpify this discussion, the operation of the hardwa~e ring mechanism is
no't described al though
1t
is an integral part of Address Preparat ion. See
Section VIII, Hardware Ring Impl.mentation.
for a discussion of the ring
mechanism hardWare.
- An
Address in the Processor consists of a pair of integers
The range of ~ is (0,2··12-1), the range of offset Is
(O,2··18-U • . The description of the segllent identified by ~:'5Ul2 value n is I= 1& • (OSBR.BND + 1),
Violation. Out of Segment Bounds Fault.
2.
fetch the SOW from OSBR.AOOR + 2 •
3.
If SOW.F
·0", then generate Directed Fault D where n is given In
SOW.Fe.
The value of Dused here is the value assigned to defIne a
missing segment fault or ~~~n1 ~.
~.
If ~~ >= 1& • (SOW.BOUNO + 1), then generate
Out of Segment Bounds Fault.
5.
If
the access bits (SOW.R, SOW.E, etc.)
incompatible with the reference, generate
Violation fault.
generate
then
an
Access
~.
=
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
5-2
a~
Access
Violation,
of
the
segment
are
the appropriate Access
AL39
6.
Generate final address SOW.ADR +
Figure 5-1 depi,cts the relationships
211s~.
d~scribed
dseg
T
1
a
J
I
I
_1-~e9ment
J
I
1
.1--1
I
<-------1 SOW
J
J
I
Q.ll~t J
I
:<-- os BR.AOJR
1
2 • ~~
T
above • .
I
J
I
-L_L,_ _~
J
J
;
J<-- OS8R.BND
data
I
I
a _ ___
L
<-- SOW. BOUND
Figure 5-1
Final Address Generation for an Unpaged Segment
pAGING
A ~ Is defined as a block of Z··o machine words. The "ultics Processor
Is designed In such a way that 0 is adJustable in the range (&,12).
Experience
has shown that the optimum value for 0 is 10 vielding a ~~ ~~ of 1024 words.
With the value of Q established, the Processor divides a ~-bit offset or
value Into two Pdrts;
the high order (~-D) bits formin~ a page number, ~,
and
the
low order D. bi ts forming a word number, ~.
At gori thm lea II v, this may
stated asl
~~n2
~
=
~~
modulo
(~ ~~a)
The svmbols X and ~ will be used in this context throug~out
Examples of page number formation are shown in Figure 5-Z below.
REVIEW DRAfT
TO CHANGE
October, 1915
this
section.
SUS~ECT
5-3
Al39
= 10
n
n
=6
0
1
0
1
~
Z
!l
--L
t
I
a
I
I
I
s
~1ll~1
L
J
I
I
alls.d
1
18
0 0
0
--l _ _ 2_L-
s
I
I
I
~
1
0
L
D
I
J
I
X
L _ _ _L 8
18
I
J
I
J
~
X-
t
I
--1---1
12
&
10
102ft word page
Figure 5-2
1
1 1
-LZ. ___ .2._
&4 word page
Examples of Page Number Formation
A bit in the SOW for a ~egment (sgW.U) specifies whether the segment js
or YOQ~. A paged segment may be defined as an array of pa~es of
arbitrary (but limited)
size with each page an array of 1024 machine words.
Thus9 a reference to a word or ~ords of a paged segment may be treated as a
reference to word ~ of page X of the segment.
~~
Hultics subdivides the Virtual Memory into ~g~ ~Lt~ bl~cks of 1024 wOrds
In the main store, the blocks are known as .m.a.l.ntl2.C....t n.a.9.~; on the
pa9i~g device and the secondary storage~ the blocks are know~ as ~~.
Such
a
subdIvision of space allows a segment page to handled as a physical bloek
Independently from the other pages of the segment and from other segments. When
a reference to a word in a paged segment is reQuired (and the word is not
already in main store), a main store page is allocated and t,e re~ord containing
the segment Pdge is read in. Unneeded segment pa~es need not occupy space in
main store.
each.
The location and status of page ~ of a paged segment is kept in the ~th
word of a table known as the ~~~ 1~ for the segment. The words in thiS
table are known as eag~ lanl~ H2~ (ellis).
(See Figure 5-6, Page Table Word
(pnO Format, Idter in this section.)
SDW.ADR for a
Any segment may be paged as appropriate and convenient.
paged segment pOints to the page table for the segment instead of the base of
the segment.
If ~ for a process is paged, DSBR.AOOR points to the page table
for J1U.g.
The full algorithm used bv the processor to access
segment ~gQ.2 (including .s1.s!:3. paging) is as follows.
word ~1 of paged
(Refer to Fi1ures ~-1~,
5-5, and 5-&)
1.
If 2 • ~~9U~ >= 16 • OSB~.BND, the generate
Segment Bounds Fault.
a~
Access
Violation,
Out
of
2•
For m the
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Qu
an tit i e s S
~~
= (2
•
~~gn~)
~1
(2
~
~~gn~
modulo 1024
-
~1)
s-~
I
1024
AL39
o
Avoid using
qoto
co~mon
declare
When names
keywords as names.
dcl
i f
such as
then
and so on ar~ used as names, a superficial but irritatjng confusion is
introquced.
On the other hand, QQ use uncommon keYkords as names
where that is convenient.
There is certainly no har~ in using
'dft·
to nam~ a variable for th~ "debit final total" (or sOlT'eth;ng of the
sort) even t~ough 'dft' is a keyword.
o
~here
possible, avoid u.sing troublesome letters in
idertifiers.
For
the
diQits ~frQ and gD~ are trcublesome because SOme output
devices do not clearly distinguish between zero and the letter '0' . or
between one ~nd the letter " ' .
exa~ple,
There
is
a literal constant lexeme for each type of arithmetic and string
val up.
The f u l l s y n t a x a· n 1 i n t err ret a t ion 0 f the s e l e l( em e s are q i ve n l ate r ,
;n
the section on "Expressions".
The following is a representative set of examples
of ;Hithm'~tic lit~r~l CO!'lstants:
fixed decO)
fi xed dec(3,2)
float dec(3)
complex float dec(3)
3n 4
3.04
3.04e-5
3.04e-5;
fi xed(])
fi xed(?,4)
float(?)
complex n·oat(7)
011r.C01b
0·1 , • ("0 C 1 b
f'11.r.Or1e-2b
011.0nOle-2bi
Cbserve that an arit~metic constant dees not begin ~ith a sign.
When a negative
constant
;5 required, it is written as two lexemes, a sign followed by an
arith~etic constant.
The following is
constants:
a
representative
set
of
e xa mpl e s
of
s t r ; n9
Uteral
St!iQ!l_!:QQ~12Q!
"abed"
(3)"abcd"
...... H~llo," .. he said."
char(4)
char(12)
chdr
means
th~
null string
Any ASCII character can be usee in cl 'character' string constant, including such
non-printin1
characters as
tab,
newline, and so on.
A strin~· constant is a
sin~l~ lexc~e, and ;s not consider~d to contain smaller lexemes.
H0 n e y we·ll Proprietary
Draft - Subject to Chanqe
Draft - Subject to
Chan~e
5-5
Honeywell
proprietar~
EUQttuatQCS
in
There are six gUQklu~lgt_!f!f~fS; each is given, together with its purpose,
following table:
t~e
,
(pedon)
point;
inrlicates
the decimal or binary
separates names in a Quallfied r.eference
(corrma)
separates items in a list of arguments,
pararr,eters,
subscripts, declarations; options, and so on
~colon)
ter~inate5 a condit ion prefix
or a
label
also; seoarates the hounds of an array
.( s em; colon)
also,
prefix;
t e r min ate 5 a 5 tat e men t
indicates the beginnin~ cf a list, an expression, an
factor, and so on
(lpft
parenthesis)
iter~tion
(right
parenthesis)
the end
of
a list,
iteraticn factor, and 5C on
i~dicates
These lexemes are used in most of the
feat~res
an
expre$sion,
an
of PL/I.
Qcecatcu:s
There are five kir)ds of
arithmeHc
+
r~laticnal
=
$2'r~r21Q!_J.~!~n::f~;
•
they are defined as follows:
**
loqical
string
II
->
the operators are dpfined
!Vost .of
opereltor,
exception is the Qualifier
"Expressions".
i n the section on "Operators".
The only
which
i·s
defined
in
the section on
Draft - Subject to Change
Draft - Subject to
Chanq~
5-6
Honey~ell
Proprietary
Honey~ell
proprietary
ADQRESS
APP~HDlN~
At the completion of the formation of the Effective Addre.ss (See Section
Effective Address Formation) an Effective Segment Numb:!r (~~ngJ is in the
Segment Number Register of the Temporary Pointer Registe- (TPR.SNR) and a
Computed Address (~L1~1) is in the Co~puted Address register of the Temporary
Pointe ... Register (fPR.CA) (See Section IV, Program Accessible Registerlit for a
discussion of the Temporarv Pointer Register).
VI,
Once ~~gn~ and ~L1~~ are formad in TPR.SNR and TP~.CA, respectively, the
process of g~neratin1 the final address can invol~e a num~er of different and
distinct Appending Unit cycles.
The operation of the Appending Unit Is shown the flowchart in Figure 5-~.
This flowchart assumes that Directed Faults Store Faults, or Parity Faults do
not occur.
A segment boundary check is made in every cvcle except PSOW. If a boundary
violation is detected. an Acce~s Violation, Out of Segment B~~ndS Fault will be
generated and the exec~tion of the instruction aborted. The occurence of any
Fault will abort the sequence at the point of occurence. The operatln~ system
will safe store the Control Unit Data for possible retry and will attempt to
resolve the Fault codition •
.. The
value of the AssOCiative ~emories may be seen In the flowchart by
observing the number of cycles bypassed if an SOW 0 ... PTW is found 1n the
Associative Hemorv.
There are nine different Appending Unit cycles that i~vo've accesses to
store. Two of these (FANP, ~AP) generate the final address and initiate a
~ain store ac.cess for the operand or instruction paIr; five
(NSOW, PSDW, PTW.
PTW2 and OSPTW) generate a main store access to fetch an SOW or PTW; and two
CHOSPTW and HPTW) generate a m~'n store access to uDd~te paga status bits (PTW.U
and PTw.H) In a PTW. The cvcl,~ are def1ne~ in T~ble5·1'belo ...
maIn
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
5-7
lL39
Table 5-1
Appending Unit Cvcle Definitioni
Cycle·
!ia1!!.L
FANP
fi na I Address lioneaged
Generates the -final address and initiates an ~ain store access to
an unpaged segment for operands or instructions.
FAP
final Address eaged
Generates the final address and initiates a main store access
a paged segment for operands or instructions.
NSOW
Nonpaged
~j
Fetch
Fetches an SDW from an unpaged
PSOW
to
~.
faged SJllf Fetch
Fetches an SOW from a paged descriptor segment.
PTW
£lH Fetch
Fetches a PTW from a page table other than a
PTWZ
'Second
e.lii
ct~
page table.
Fetch (Same as PTW above)
Fetches the nekt PTW frOID a page '-able oth-er than a ~g page
table during hardware prepaging for certain Jninterruptable EIS
instructions.
This cycle d.oes ~1 load t~e next PTW into the
Appending Unit. It merely assures that the PTW is not
faulted
(PTW.F = "1") and that the target page wltl be in ~ain store when
and if needed by the inst~uctidn.
OSPTW
DescrIptor Segment
eI~
Fetches a PTW from a
HOSPTW
110 d I
fy
Fetch
~
page table.
u..s.e.Ilt
the page accessed bit (PTW.U) in the PTW for a page in a
page table. This cycle alwavs immediately follows a OSPTW
eye' e.
Sets
~
HPTW
Hodi fy
e.ll
Sets the page modified bit (PTW.H) in the PTW for a page in other
than a «~~ page table.
REVIEW DRAFT
SUBJECT TO CHANGE
Dc tober, 1975
5-8
AL39
S.I.A&I
A.e.eE.Wl
I
__L
-
,
_ _ _ _.J.IN""Q_/is
1
t
1
1
\
is
paged? 1
~
\
\
In\.-lti_ _ _ _ _ _ _ _ __
T
J
\ SOW A"? 1
t
\
1
\
\_~
SD~
I
lIs
______________
se 9
\
\-1'UL-_ _ _ __
1
\ paged?
\
1
t
_I
J
I
Yes
Yes
I
t
I FANP
l ____-.L
---*---\
1
J
PTW In\.J:UL___
•
\ PTHAH? 1
J
EHa
APPEND
\
I
__ _____
OSPTH I
,--L
lis
& . -_ _ _
~t
t
1
\
\
I
Yes
DSPTW.U \_~NQ_ __
\ set ON? 1
I
I
a Yes
a
---*--I
I
I
HOSPTW.
L
I
I
.
t PTW;Loaal
PTWAH
I
1: ______
...
1<-------------+
\
Prepage \-I.tt:i ___ _
\ Mode? 1
I
I
J
1<-----------+
\
t
t
+------------------------>.t
I
I
Load
SDNA"
I
_~t~
___
I
I
I No
J
I
NSDW
PSDW
1
PTW2
1 _ _ _ _...
<-------------t
•
\
STR-OP &\-IJlL _ _
\ PTW.H=O 1
I
I
+---------t
\
I
t
1
I
I
•
t
No
\
_ _ _~I PTW from\
I
\ store & I
I
1 HPTW;SetJ
1 PTW.H & I
J PTW.U
:
1_
J
\PTW.U:QI
____~t_
I
I
I
I
HPTW;Setl
PIW,U--1
+------------->1<-------------+
t
FAP
Notel A STR-OP Is any Processor function
that ~rites data to main store.
Figure
5-~
I
t
E1:lD. APPEND
Appending Unit Operation Flowchart
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
5-9
AL39
The Segment Oe~criptor Word (SOW) pair contains infcrmation necessary to
control
the
access
to a
segment
bV a
process.
The SOW for a segment is
constructed from data in the directory entry for the segment and i~ the System
Segment
Table
(SST) when the segment Is initiaTed by the p·ocess.
The SOW for
segment D (unique within the process) is placed at offset aD in
the Descriptor
Segment (~~9) of the process.
o
2
2 2
3 !t
g Z
I
I
I
Rl •
I
I
ADOR
.
I
I
21t
o
0
~~~1
~1~1
3
-
3
~2
a
a
I
3 3 3 3
;5 !t ~
..
z
I
•
R3 1Ft Fel
J
3
I I .
3 1
111 1 1 1 2 2 2
____.__________.__________~4~5_~-Z-1-9 D 1 2
II
101
2 3
2
--'L-
BOUND
________________ .____________
3
5
l11J1111
I
:RIEIWIPIUIGICI
J
~;~I-1-1
J
J J
I
f
1,.
14 1 1 1 1 1 1 1
1
Figure S-S
J
2
Segment Descriptor Word (SOW)
Fo~mat
lltig:lDtioo
AOOR
24 bit base address of segment (U=l)
or
segment
page
tab'e
(U= 0).
Rl
highest effective read/write ring.
R2.
highest effective read/execute ring.
R3
highest effective call ring.
F
directed fault indicator.
1 = the necessary unpaged segment or segme,t page table is
memory.
o
Fe
= eKecute
in
the directed fault specified in FC.
the number of the directed fault
(OFO-OF]) to be
executed
if
F=D.
BOUND
largest 16-word oJock number
that may be accessed without
causin9 an Access Violation, Out of Segment BoundS Fault.
R
read permission bit.
REVIEW DR"FT
SUBJECT TO CHANGE
October, 1975
S-10
AL39
Qug:iot iOQ
eXECute permission bit. (XEC , XED
w
"rite permission bit.
p
privileged mode bit.
o privileged instructions cannot be executed.
1 = privileged instructions may De executed if in ring O.
u
paged/unpaged bit.
o segment is paged and AODR is the
table.
1 = segment is unpaged and AOOR is the
segment.
=
=
address
base
the
of
address
gate indicator bit.
o any call from an external segment must be
less th3n the value of el.
1
any legal segment offset may be called.
G
fag'
exclude~)
=
=
to
page
of
an
the
offset
C
cache control bIt.
o = words (operands or instructions) from this segment may not
be placed in the cache.
1 = words from this segment may be placed in the cache.
Cl
call limiter.
Any external call
than Cl If G=O.
Ia~Hord
to thiS segment must
to an offset less
~e
'PI")-E~
The Page Table Word (PIW) contains location and status information for a
page of a paged se~ment.
The PTHs for a paged segment are copied from the
directory entry file map for the segment into the Page Table Word Array (PINA)
of a free area in the Active Segment Table (AST) area of the SST "hen the
seg.ent Is first initiated by a process~
Subsequent initiations by other
proceSses reference the exjstin~ PIWA.
o
1 1
2 Z Z 2 2 222 2 333 333
_ _ _ _ _ _ _._47_8~_._....1_'2_;I_L2_LL8. CJ
Q
I
AOOR
I_I
I
a
1
I
1 2 :5 4 5
Q
I
I
I
:
I.
t
I DID swaPIO OIUIO DIMIQ1WISIFI FCI
_________________ ---1 ________ __J___ 1_1___1_J I J I I
I
18
4 1 1
Z 1
2 1 1 1 1 1
Z
'~I
Figure 5-6
Fie I d
Pa~e
Table Word (PTW) Format
t:!.ajlU~
AODR
18 bit modulo 64 page address if page is
su:
18 bit record
nu~ber
i~
store,
of page if page is not in store.
The hardware ignores low oroer blts ~f the in-store page
address according to page size based on the folloRing •••
REVIEW DRAFT
SUBJECT TO CHANGE
Oct 0 b er, 1975
5-11
AL:5c)
D.~cclQtlSlD
Page Size
ADDR Bits
.lIL~~
.i.9Cl~~g
&'+
none
126
11
16-11
15-11
1'+-11
13-17
12-17
Z5&
512
102ft
201,8
409&
DID
device id for device containing the page.
W
1
p
temporary bit used in post_processing.
U
1
"
1
= page
has not ye t been wr i tten out.
Q
1
= page
= page
= page
W
1
= page
is
S
1
Is out of service
F
1
0
= page
= page
= page
Fe
directed fault number for page fault.
REVIEW DRAFT
SUBJECT TO CHANGE
Oct 0 b er, 1975
has been used. (t-ouched).
has been modi' .led.
has been used during the
~uantuli.
w~red.
(1/0
1n p,..ogress).
is in store.
not in store. Execute directed f a.J I t
5-12
Fe.
Al39
SECTION VI
EFFECTIVE ADDRESS FORMATION
The Effective Address in the Mu'tics Processor Is the user·s specification
of the location of a data item in the Multics Virtual Hemorv. Each reference to
the Virtual
Memorv for operands. indirect words. indirect pointers, Operand
Descriptors, or instructions must proviae an Effective Address.
The hard~a~e
and
the operating system translate the Effective Address into the true location
of the data item and assure that the data item is in main store for the
reference.
The Effective Address consists of two parts. a segment number and an
offset.
The value of each part is the result of the evalJation of a hardware
algorltha (expression) of one or more terms. The selection ~f the algorIthm is
made, bV the use of control bits in the Instruction Word; namelv, bit 29 for
segment number modification and the Address Modification (or TAG)
field for
offset modification. If the TAG field of the Instruction Wo-d specifies certain
"indirect- modifications, the TAG field of the In~irect Worj Is also treated as
an Address Hodifier. thus establiShing a continuing Mindirect chain". Bit 29 of
an Indirect Word has no meaning in the context of Address Hojification.
The results of evaluatIon of the Address Modification algorithm are stored
in temporary registers used as working registers bV the Pro:essor. The segment
numDer is stored in the Temporarv Segment Register
lTPR.TS~).
The of fset is
stored
in the Computed Address Register (TPR.CA). When each Effective Address
computation has been completed, the C(TPR.TSR) and the C(TPR.CA)
are presented
to the Appending Unit for trans'ati~n to a Z~-bit flnal Add-ess (See Section V,
Addressing --Segmentation and Paging).
There are two types of Effective Address formation. The first type does not
make expl lcit use of segment numbers. The algorithm selecte~ produces a value
for C(TPR.CA) only. The segment number In C(TPR.TSR) does not changp. and is the
segment rumber used to fetch the instruction. In this case, al I references are
said to be "local" to the procedure segment as held In C(PPR.PSR).
The second type makes use of a seyment number stored either in an IndIrect
Word-pair in main store or in a Pointer Register (PR.n). The algorithm selected
produces values for Doth C(TPR.TS~)
and C(TPR.CA).
The segment number In
C(Tf'R.TSR) m..a~ change and, i f it changes,references are s~ld to be '"externalto the proceaure segment as held in C(PPR.PSR).
REVIEW ORJlFT
SUBJECT TO CHANGE
October. 1975
6-1
AL39
The t~o tvpes of Effective Address formation can be intermixed.
In cases
where Effective Address calculations are chained toget,er thro~gh Pointer
'Registers or Indirect Words, each Effective Address is translated to a 24-bit
final address to fetch the next item in the chain.
This description of Effective Address 'ormation is divided Into t~o parts
corresponding to the two types. The first part describes the type that involves
onlv the offset value CCTPR.CA).
The segm.nt number C(T~R~TSR) Is
assumed
constant and equal to C(PPR.PSR).
The second part describes the type that involves both the segment
CCTPR.TSR) and the offset C(TPR.CAa.
nu~ber
The Address ModifIcations described here produce values for CCTPR.CA) only.
The segment number C(TP~.TSR) is assumed constant and eQual to C(PPR.PSR).
Bits 30-35 of an Instruction Hord or Indirect Word constitute
Modifier or ~AG field.
The format of the TAG field isl
the
Address
333_____
3_
--Ll-J
2
Figure 0-1
I
J
J
Tml
J
I
5
Td
I
J
I
Address Modifier (TAG) Field
For~at
[ynction
i~eral
Tm
The "modifier- field; specifies one of four general types of
offset modification.
Td
The "designator- field; specifies a register
Indirect Then Tal Iv variation.
nu~ber
or
an
Tvpe~~~-HQdifica~D
There are four general types of offset modification: Register, Register
Then Indirect, Indirect Then Register, and Indirect Then T311y.
The general
types are described In Table &-1 belo~.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
&-2
AL39
Each Effective Address for~ation for an operand begins ~ith a preliminary
step of
loading TPR.CA with the ADDRESS field of the Instruction Word.
This
preliminary step takes place durin~ instruction decode. The va1ue loaded into
TPR.CA is symbolzied by NyU in the descriptions fol lowIng. Table 6-1
General Offset Modification TYD!S
Til
1l..illu.J.
H~rtiller
t"pe
o
Register (R)
The contents of the designated register, Td, are
added
to the current Computed Adjress to form the
modified Computed Address.
Addition is two·s
comple~entt
modulo 2··18 anj overflOM is not
possible.
1
Register Then
Ind irect eRU
The contents of the designated register, Td, are
added
to the current Computed Address to form the
mOdified Computed
Address
as
for
Register
modification.
The word at C(TPR.CA)
is then
fetched and interpreted as an Indirect Hord.
The
TAG field of the Indirect Horj specifies the next
step in Effective Address formation.
The use of
du or dl
as the designator In this lIIodi f icat ion
type will cause an Illegal Procedure, Illegal
Hodif i er Faul t.
Indirect Then
The Indirect Word at C(TPR.CA) is fetched and the
modification performed according to the variation
specified in Td amd the contents of the Indirect
Word.
This modification ty~e allows automatic
incrementing and decrementing of addresses and
t a I I y c ou n tin g.
2
Ta I I y (IT)
J
Indirect Then
Register (IR)
Tne register designator, Td, is safe-stored in a
special
holdin) register (CT-iOLO). The word at
the current CITPR.CA) is fetched and interpreted
as an Indirect Word. The TAG field of the Indirect
Word specifIes the next step in Effective Address
formation as follows:
If Indirect
lAL.U.L
thiul!.
IT
Perform Register modificatIon
from CT-HOLO.
RI
Perform
R or
using
Td
the
.Register
Then
Indirect
immediately and fetch the
next Indirect Word f~om the result of
that modification.
modific~tion
IR
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
Replace the safe-stored Td value In
C T- P.OLD
with
the Td va I ue of the
Indirect Word TAG fIeld and fetch the
next Indirect Word from the ADDRESS
given in the Indirect Hord.
6-3
ALJ9
The algorithmic
flowc~arts
depicting the Effective Address
formation
process
are scattered throuqhout this section and are link!d together with -Go
to" labels.
The flowchart starts ~ith Figure 6-2 below.
iI.AfU EA
J
I
,
\
---*.--
\
Interpret \
Tm
I
\_----,
J
t
I
I
•
J
I Tm:RI
Tm:R
I
•
•
I
I
t
Tm=IT
Tm=IR
Go to
Go. to
Go to
Go to
SIARI
& mm
llAJil
SlAfll
1.I H.Q.Il
s.I!fU
1& 1tilD.
(Figure 6-3)
Figure 0-2
Rl !.1211
(Flgure6-ItJ
Co~mon
igure 6-5)
(F
(Figu-e &-&)
Effective Address Formation Flowchart
RegiSter (R~ificat'Qn
)
In Register modIfication (T~ = 0) the value of Td deSignates a register
whose contents are to be added to C(TPR.CA) to form a modified C(TPR.CA).
This
modfied C(TPR.CA) becomes the Effective Address of the opera~d.
See Table 6-2
and Figure 6-3 below for details.
EXAMPLESI
La..b.JU
lotlI:.u.~.tiJm
E11 s:~! ,&l.:s:
1.
a
• dd 'I
'I
2.
a
sta '1,n
'I
3.
a
'daQ '1,au
'I
4.
a
tra 3.ic
a + 3
5.
a
I dQ v,du
'I ;
A..Q~5.~
+ CIA)O,17
operand has the form
zero 'I,D
operand has the form
zero 0,'1
6.
a
.x14 v,dt
'I;
7.
a
mpv '1,1
V + C(X1)
8.
a
stx4 '1,7
y
REV lEW ORAF T
SUBJECT TO CHANGE
October, 1975
+ C(X7)
AL39
Table 6-2
(NOTE a AU
Register Modification Decode
examples start w Uh the preliminarv step, V -> C(TPR.CA»
Register
Coding
Effective
.ll.alw:
s.H."-.te.d.
t1D~mgal"
A.~~
0
none
n or null
1
AO,17
au
V + CfA)O,17
2
QO.17
QU
V + C(Q)O,17
3
none
du
y; V becomes the uppe- 18 bi ts of
the 3&-bit zero filled operand
tt
PPR.IC
lc
V + C(PPR.IC)
S
A18,35
at
V + C(A)18,35
&
Q18,35
QI
V + C(Q)18,35
7
none
dl
v;
Td
.,
y becomes the 10Me- 18 bi ts. of
the 3&-bit zero filled operand
10
XO
0 or xO
V + C(XD)
11
Xl
1 or xl
V + C(Xl)
12
X2
Z or x2
V + C(Xl)
13
X3
3 or x3
.,
+ C(X3)
lit
X4
4 or x4
V + C(X4)
15
X5
S or xS
V + C(XS)
1&
X&
6 or xo
y + C(X6)
17
X7
7 or x7
.,
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
&-5
+ C(X7)
Al39
ilA.&l
& rulD.
I
t
__lJ:.s._,
I
I
I
\
Td =0 ?
\
\
I
\
I
I
I
No
__~t___
J
I
I
I
I
I
I
_______ t.I
I
I
J No
Set Direct Operanj Flag
Forll Operand
--1-________
I
I
1
S
I c:.=Td
I
I
I
J
I
\_l.e.s.-_ _ _ _ _ _ __
I
\
S
a
\
'Td=3
\
or 71
=
Eff. Addr.
C(TPR.CA) + CCr:J
1
+----------->1<---------------------------+
•
EtiD. EA
Figure &-3
Register
Tb~~1-i&ll
Register "odification Flowchart
Modif i C a 1i2Q
In Register Then Indirect modification (Tm = 1) the vatue of Td designates
a register whose contents are to be added to C(TPR.CA) to form a modfled
CCTPR.CA).
This modified C(TPR.CA) Is used an as Effective Address to fetch an
Indirect Word.
The ADDRESS field of the Indirect Word is loa~ed into TPR.CA and
tbe TAG field field of the Indirect Word is interpreted in t~e next step of an
indirect chain. The TALLY field of the Indirect Word is ignored.
The indirect chain continues until an Indirect Word TAG field
modificatIon without indirection, namely, a RegIster modifIcation.
specifies
a
The coding mnemonic for Register Then Indirect modification Is c· where c:.
is any of the coding mnemonics for Register modification as given in Table 6-2
above except du and dl. The du and dl register codes a~e illegal and will cause
an Illegal Procedure, Illegal Modifier fault.
See flowchart in Figure &-4
below.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
6-&
AL39
EXAMPLES'
1.
2.
3.
J..aCUll
lns..ll:J.t,.lJ.JlD
8
b
Ida
erg
b.·
y
a
b+C(X11
I dQ
.,..g
b.l·
....•
tra Ittlc·
arg Ct·
C
It.
a
b.C(XO)
c+CCX1)
y
v
v,au
+ C(A)O,17
8rg V
Ix'lt btO.
arg c.l·
erg v.dl
v; operand has the for.
zero OtV
I
I
\
\
Td=l
or 71
\._--'
I
\-.:£1.1-._ _ _ __
I
I
•
AB.QU
1 No
I
\
•
, Td=O?
\
II legal Procedure.
Illegal Hodifier Fault
\
,,
\-HQ~
•
____________
I
t
I
I
I Yes
C=Td
E f f. Addr.
J
I
=
CCTPR.CA) + CCc.)
I
J
I
1
I
I
a
J<-------------------+
t
I
J
I
I
I
I
!
Indirect Word
Fetch
APPEND CYCLE
(Figure
5-".
I
I
I
I
1
1
Go •to
~lAJU
EA.
CF igure 6-2)
Figure 6-"
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
Register Then Indirect Modification Flowchart
6-7
ALl9
Indirec1-lh~~~c-1lRl Modifica~
In
Indirect Then Register modification (Tm
= 3»
the value of Td deSignates
to fo~m the final modfied
CCTPR.CA) durin1 the last step in the indirect chain.
The value of Td is
safe-stored in a special holding register, CT-HOLD. The inital CCTPR.CA) is
used an as Effective Address to fetch an Indirect Wo~d.
The ADDRESS field of
the
Indirect Hora Is loaded Into TPR.CA and the TAG field field of the Indi~ect
Word is interpreted in the next step of an indirect chain. The TALLY field of
the Indirect Word is Ignored.
a register whose contents are to be added to C(TPR.CA)
If the Indirect Word TAG field specifies a Register Then Indi~ect
modification,
that modifIcation is performed and the indirect chain continues.
If
the Indirect Word TAG fIeld specifies
Indire:t
The~
Register
modification, the Td value from that TAG field replaces the safe-stored Td value
in CT-HOLD and the indirect chain continues.
If
the Indirect Word TAG specfies Register or I~direct Then Tal IV
modification, that modification is replaced with a Register modification using
the Td value safe-stored in CT-HOLD and the indirect chain e~ds.
The coding mnemonic for Indirect Then Register modification is·C ~here C
is anv of the coding mnemonics for Register modification as given in Table 6-2
above except DYll.
EXAMPLESI
3.
4.
L.ab.JU
l~~tl.J...o.n
Effecti~A~~~~~
a
b
Ida b,·n
arg "1,2
V
a
b
I x 12 b,·dl
sta y,au
eCT-HOLD = dU
y; operand has the f:>rm
zero 0, y
a
b
c
d
Ida
arg
arg
arg
(eT-HOLD
a
b+C exu
c
IdxQ b,l·
arg c,·lc
arg 5, d I
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
b,·1
c,n·
dt·"
y,ql
(CT-HOLD = n)
= xU
eCT-HOLD = x4.
+ CeX,.)
y
eCT-HOLD = Ie)
a + 5
6-8
AL39
lliRl
LR t1Wl
I
t
-
I
a
J Td -> CT-HOlO I
1
LI
+----------------------------->J
______
~t~_______
I
I Indirect Word
1 Fetch
I APPEND CYCLE
I
I
1
I
J (Figure 5-4)
.1-
1
I
I
t
I
\
Interpret
\ Indirect TAG
I
--'
\
\
I
t
1
I
1 TII=RI
I
t
I
1
I
IJ
C=Td
J
Eff. Addr. =
I
C(TPR.CA) + C(C) --1J
1 -_____________
1
J
t
Indirect
SliBl.
1& tum
Tm=R or IT
t
r:.=CT-HOlD
Eff. Addr.
C(TP~.CA)
=
+ c(c)
t
•
. EtiIl .fA
t------------t
Figure 6-5
Tm=IR
Go •to
Indirect Then Register Hodification Flowchart
Th~11L.1.I..lLt1~~SlO
In Indirect Then Tally modification (Tm = 2) the value of Td specifies a
variat 100.
The lnital
ClTPR.CA)
is used an as Effective Address to f etch an
Indirect Word. The Indirect Word is interpreted and possibly altered as the
modification is performed.
The TALLY field of the Indirect Word is used to cOJnt ~eferences made to
the Indirect Word. It has a maximum range of ~D9o. If the TALLY field haS the
value 0 after a reference to the Indirect Word. the Tally Ru~out indicator wi'l
be set ON. otherwise the Tally Runout indicator will be set OFF. The value of
the TALLY fIeld and the state of the Tally Runout indIcator have
Effective Address formation.
WARNINGI
no
effect
on
If there Is ~ore than one Indirect Hord in an indi-ect chain t~at is
refer.nced by a tally counting modification. o~ly the state of the
TALLY field of the last Such word will be refle=ted in the Tally
Ruoout indicator.
REVIEW DRAFT
SUBJECT TO CHANGE
Oct 0 b er 9 1975
6-9
Al39
The variations of the Indirect Then Tally modification are given
In
Table
6-3 below and explained in cetait in the paragraphs fo'loMin~.
See floMchart In
figure 6-6.
Those ent r i es given as ··Undef i ned·· cause
II I ega I Procedure t
a"
Illegal Modifier Fault.
(See "Effective Address Form~"on Involving Both
Segment Number and O'fset~ later in this section for certain special cases.)
Table 6-3
Coding
Td
..
\lar1at10ns of Indirect Then Tally Hodification
~
H.o~k.
0
fl
~su::.i.at..i...suLtin.e
Fau.t Tag 1
1
Undef lned
2
Undefined
3
Undefined
It
sd
Subtract Delta
5
scr
Sequence Character Reverse
6
fZ
Fault Tag 2
7
f3
Fault Tag 3
10
ci
Character Indirect
11
i
Indirect
12
sc
Sequence Character
13
ad
Add Delta
1,.
di
Decrement Address, Increment Tally
15
dic
Decrement Address 9 Increment Tally, and Continue
16
id
Increment Address, Decrement Ta II y
17
idc
Increment Address 9 Decrement Tally, and
Contin~e
Fault Tag 1 (Td = 0)
Effective Address formation is terminated immediately and a Fault Tag
1 Fault is generated. A Fault Tag 1 Fault e~ecutes the Fault Trap
pair at C + & where the value of C is obtained from the FAULT BASE
sMitches on the Processor Configuration panel.
This variation may be used in Indirect Word ~r program control
transfer vectors or tr-ee structures to signal inval id entries or
entries that require special handling. CCTPR.CA) at the time of the
fault contains the Effective Address of the word =ontaining the Fault
Tag 1 modif ication. Thus, the ADDRESS and TALLY fieldS of that word
may contain information relative to recovery from the fault.
REV lEW DRAFT
SUBJECT TO CHANGE
October, 1975
&-10
AL39
Subtract Delta (Td = ft)
The TAG field of the Indirect Word Is Interpreted as a 6-blt.
unslQned, positive address increment value, a~. For each reference
to the Indirect Word, the ADDRESS field is reduced Dy ~~la and the
TALLY fieid is increased bv 1 ~~ the Effective Address is for~ed.
ADDRESS arithmetic is modulo 2··18. TALLY arithmetic is modulo ~09&.
If the TALLY field overflows to Ot the Tallv Runout indicator is set
ON, otherwise it is set OFF. The Effective Address is the value of
the modified ADDRESS field.
EXAMPLE:
LiibJU
1~1I:J.ltl.1sm
a
b
Ida b,ad
vfd 18/c.12/t,&/d
Reference
CJwo.1
Effective
Ta' I y
A.g~r::e~~
~
1
2
3
c-d
c-2d
c-3d
t+1
t+2
t+3
0
c-nd
t+O
Sequence Character Reverse CTd = 5)
Bit 30 of the TA~ field of the Indirect Word is interpreted as a
character size flagt tn, with the value 0 indlcatl~g &-bit characters
and the value 1 indicating 9-bit characters. Bits 33-35 of the TAG
field are interpreted as a 3-bit character position counter, kl. Bits
31-32 of the TAG field must be zero.
For each reference to the Indirect Word. the character counter, kit is
reduced by 1 and the TALLY field is increased bv 1 k~ the
Effective Address is formed. Character count arithmetic is modulo 6
for 6-bit characters and modulo ~ for 9-bit characters.
If the
character count. ki, underflows to -1, it is -eset to 5 for &-bit
characters or to 3 for 9-~lt characters and ADORESS is reduced by 1.
ADDRESS arithmetic is modulo 2··18. TALLY arithmetic is modulo ~09&.
If the TALLY field overflows to O. the Tally Runout indicator is set
ON, otherwise it is set OFF. The Effective Add-ess is the modified
value of the ADDRESS field.
A 36-blt operand is formed bv high-order zero filling the
character ~l of ADO~ESS with an appropriate number of bits.
value
of
EXAMPLES.
Reference
LabJU
lo.U~~
a
Ida b,scr
vfd 18/c+l,12/t,1/D,5/2
bcl "ABCDEFGHIJKL-
b
c
~~
2
1
3
It
0
Ida b,scr
vfd 1~/c+l,12/t,1/1.5/2
ac i ··abcdefgh"
{lQi:CilDs:2
t+1
00 ••• 0"1-
5
5
It
c
t+5
OO ••• O"E"
1
2
2
1
J
0
3
2
c+1
c+1
c+l
c
c
t+1
t+2
t+J
t+4
OO ••• U··g"
OO ••• O·f"
OO ••• O"e"
OO ••• O"dOO ••• O"c"
...
5
&-11
Ta It Y
Ul.w:
c+1
c+l
c+l
c
~
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
"s1r:..tn
1
2
...
a
b
c
Effective
d
t+2
OO ••• O··H"
t+3
OD ••• O-G-
t+~
OO ••• O"F"
t+5
AL39
Fault Tag Z CTd
= &)
The action for this va~iation is identical to that for Fault Tag 1
except that the Trap Pair at C + 60 (octal) is executed.
WARNINGI
Fault Tag Z Is reserved to the Multics operating system for use in the
Dynamic Linking feature. Its attempted use for ot~er purposes could
cause serious system inconsistencies and/or system crashes.
Fault Tag 3 'Td
= 7)
The action for this variation is identical to that for Fault Tag 1
except that the Trap Pair at C + &2 (octal) Is executed.
Character Indirect (Td
= 10)
Bit 30 of the TAG field of the Indirect ~ord is interpreted as a
character size flag, 1n, with the value 0 indicating &-bit characters
and the value 1 indicating 9-bit characters. Bits 33-35 of the TAG
field are Interpreted as a 3-bit character position value, ~1. Bits
31-32 of the TAG fIeld must be zero.
If the character pOSition value is greater than 5 for &-bit characters
or greater than 3 for" 9-01t characters, an Illegal Procedure, Illegal
ModifIer Fault will occur. The TALLY field is Ignored. The EffectIve
Address is the value of the ADDRESS field.
A 3G-blt operand is formed by high-order zero filling the
character ~ of ADDRESS with an appropriate number of bits.
value
of
EXAMPLES.
LaJull
lnllCl.l.c...t..UD
a
c
Ida b,ci
vfd 16/c+l,lZ/O,1/0,5/Z
bci ··ABCDEFGHIJKL-
d
Ida d,ci
vfd 18/c,12/0,1/0,5/1
e
f
Ida e,cl
vfd 18/f,12/0,l/1,5/3
acl .oabcdefgh-
9
Ida gtci
vfd 18/f+1,12/0,1/1,5/0
b
QAttaOA
00 ••• 0"1"
OO ••• O"B"
00 •••
O"d"
OO ••• O"e-
Indirect (Td = 11)
The
Effective
Address
Is the value of the ADDRESS fIeld.
The TALLY
and TAG fieldS are ignored.
SeQuence Character (Td
= 12)
Bit 30 of the TAG field of the Indirect Word is interpreted as a
character size flag. 1Q, with the value 0 indicating &-bit characters
and the value 1 indicating ~-bit characters. Bits 33-35 of the TAG
field are Interpreted as a 3-blt character position counter, ~1. Bits
31-32 of the TAG field must oe zero.
REV lEW DRAFT
SU~JECT TO CHANGE
October, 1975
&-12
AL39
For each reference to the Indirect Word, the character counter, ki. Is
increased by 1 and the TALLY field is reduced by 1 ~11~ the Effective
Address is formed. Character count arithmetic i i modulo & for ~-bit
characters and modulo ~ 'or 9-bit characters. If the character count,
,,1, overf lows to b for &-bi t characters or to ,. fo'" 9-bi t char'acters.
it Is reset to 0 and ADD~ESS is increased bv 1. ADDRESS arithmetic is
modulo 2•• 18. TALLY arithmetic is modulo ,.Oq&. If the TALLY field is
reduced to 0,
the Tally RUDout indicator is set ON, otherwise it 15
set OFF. The Effective Address is the original unmodified value of
the ADDRESS field.
A 3&-blt operand 15 formed by high-order zero f111ing the value of
character kl of ADDRESS with an appropriate n~mber of bits.
EXAMPLES'
Reference
Lilb..li
InUryctiQn
a
Ida b,sc
vfd 18/c,lZ/t,1/O,S',.
bcl "ABCDEFGHI~KL -
b
c
a
b
c
~
Ida b,sc
vfd 18/c,lZ/t,1/1,5/2
acl "abcdef gh-
1
2
3
4
5
It
...
2
1
2
3
2
3
Effective
Talty
~~
~
Qperand
c
c
c+l
c+1
c+l
t-l
t-z
t-3
t-4
t-5
OD ••• O"E"
00 ••• 0 ··F-
c
c
c+l
c+l
9+1
t-1
t-2
t-3
t-4
t-5
5
0
1
4
0
1
5
2
...
Add Delta (Td
k1
OO ••• O··G-
OO ••• O"H00 ••• 0"100 ••• 0 "c"
OO ••• O··d"
OO ••• O-e"
OO ••• O"fOO ••• O"g"
= 13)
The TAG flelj of
the Indirect Word is interpreted as a 6-blt,
unsigned, positive address increment value. ~~. For each reference
to the Indirect Word, the ADDRESS field is increased by ~la and the
TALLY field Is reduced by 1 a1~ the Effective Address is
formed.
ADDi(ESS arithmetiC is modulo 2··18.
TALLY arithmetic is modulo ItOQ6.
If the TALLY field is reduced to 0, the Tally Runo.Jt indicator- is set
ON, otherwise it 15 set OFF.
The Effective Add·ess is the value of
the original unmodified ADDRESS field.
f.XAHPLEI
I~tryctlQn
a
b
Ida b,ad
vfd 18/c,1/t,6/d
Decrement Address, Increment Tallv (Td :
Reference
Effecti.ve
Ta I I V
~iUm.1
~ddress
~
1
2
3
c
c-d
c-2d
t-1
D
c- (0-1) d
t-o
t-2
t-3
14)
For each reference to the Indirect Word, the ADDRESS field is reduced
Dy 1 and the TALLY field is increased Dy 1 ~~~ the Effective
Address !S formed.
AOD~ESS
arithmetic is mOjulo 2··18.
TALLY
arithmetic is modulo ,.09&.
If the TALLY field overflows to 0, the
Tallv Runout indicator is set ON, otherwise it is set OFF.
The TAG
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
6-13
AL39
field of
the Indirect Word is gnored.
value of the modified ADDRESS field.
The Effective Address is the
EXAMPLE'
tion
Lab..tl
I.~truc
a
Ida b,di
vfd 18/c,12/t
b
Reference
Effective
Tally
~Wll
a11.ar:~~
~1wt
3
c-l
c-2
c-3
t+1
t+2
t+3
Q
C-n
t+.o
1
2
Decrement Address, Increment Tally, and Continue (Td: 15)
The action for ~hls variation is identical to that for the Decrement
Address, Increment Tally variation except that the TAG field of the
Indirect Word uinterpreted and continuation of the indirect chain Is
possible. If the TAG of the Indirect Hord invokes a register,
that
is, specifies R, Rt, or IR modIfication, the effective Td value for
the reglste~ is force~ to Mnull" before the next Effective Address is
formed.
Increment Address, Decrement Tally (Td : 16)
for each reference to the Indirect Word, th! ADDRESS field is
increased by 1 and the TALLY f·leld is reduced by 1 il.U..tt the Effective
Address is formed.
ADDRESS arithmetiC Is mojulo 2·.18.
TALLY
arithmetic is modulo 409&. If the TALLY field is reduced to 0, the
Tally Runout indicator is set ON, otherwise it is set OFf.
The TAG
field of
the Indirect Word is ignored. The Effective Address Is the
value of the original unmodified ADDRESS field.
EXAMPLE'
LatLU
Instryction
Reference
CJwnl
a
, da b,id
vfd 18/c,1/t
1
b
Effective
lddtes$
Tall V
~
3
c
c-1
c-Z
t-1
t-2
t-3
II
c-(.o-1)
t-.o
2
Increment Address, Decrement Tally, and Continue (Td : 17)
The action for this variation is identical to that for the Incre~ent
Aodress, Decrement -Tallv variation except that the TAG field of the
Indirect Word ~ interpreted and continuatIon of the indirect chaIn Is
possIble. If the TAG of the Indirect WorG invokes a register,
that
is, specifies R, RI, or IR modIfication, the effective Td value for
the register is forced to "nul I" before the next Effective Address is
formed.
RlVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
AL39
SlUl
11 Mil
1
__L - -
Illegal Procedure,
Illegal Hodlfier Fault
!.Wl&l
I
,I nter-pret ,
\
Td
au·' t Tag 1, 2.
or 3 Fau' t
f
\
r
T d=unde f
+--------->1 (1,2,3)
I
,-----,
~l
T
~
Td=fl,fZ,f3
I
1(0,6,7)
I
J
t
_-1.
a
I
I
I
I
I
Td=ci,sc,scr
(10,12.5)
t
Indirect Word
1 F etch
I APPEND CYCLE
J (Figure 5-4)
~~
Td=i,ad,sd,di,ld
I td=dlc.ldc
a (11,13''',14,1&)
I (15.17)
____.---.t_ _ __
t
..
Indirect Word
Fetch
APPEND CYCLE
(Figure 5-'+)
J
I
I
1
I
I
Indl"'ect Word
I fetc,",
I APPEND CYCLE
I (FigJre 5-4)
1.___
"
,_,
I
1
I
I
1
1 Yes
I
I
I
I
1-JiQ._' Legal d '
'value? ,
1
t
I
I
I
I
TALLY and
for-m Eff.
Address
L -_ _ _-....
,
1<--------------------.
t
TALLY and
form Eff.
Addr.
as
required
I
I
I
I
I
__~.__
I
1
I
,
t
, lnt erpre t
,
\ Indirect TAG'
"
1
___________________ •________ --1
I
I TII=R
•
I
<-------------t
•
.EWl EA
1
TII=IR or IT
TII=RI
1
Indirect Word I
Fetch
1
APPEND CYCLE
I
(figure
_
_ _ _5-'+)
_ _-1.1
~
+------------>
t
;0 to
ll!UEA
(Fig.Jr-e 6-2)
Figure &-&
Indirect Then Tally Modification
E.EE.E..C.IlllLAIlllB..E.S.LE.O.&t1A.I.U N
F'o~chart
I NV 0 L VI N LaQI.tLSE (j HE NT N W:1aEJLA..tiP
Of f SE I
The second type of Address Formation allows formation of a modified
Number and a modified Offset simulta~eously. See Figure &-1D. Effective
Number Generation Flo~chart, for- details.
RlVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
6-15
Seg~ent
Se9~ent
Al39
0'
In the foregoing discussion
EffectIve Address Formation Involving Offset
Onlv
it "as noted that a preliminary step of loading the ~ODRESS field (y) of
the Instruction Word into C(TPR.CA)
was performed bef~re
the
specifIed
modification was carried out. C(TPR.CA) was then used as o~e data inp~t to the
_odification process.
If bit 29 of the Instruction Word is set to "1", so-called Pointer Register
modification is invoked and the preliminary step Is executed as follows.
1.
The ADDRESS fIeld of the Instruction Word is interpretej as show" in Figure
&-7 below.
2.
C(PRn.SNR) -> C(TPR.TSR)
3.
maximum (C(PRn.RNR), C(TPR.TRR), C(PPR.PRR»
~.
C(PRQ.WORDNO) + OFFSET -> C(TPR.CA)
o
o
0
--'L- 2 3
J
1
_____________---1I
I
I
J
J PRO I
I
1
OFFSET
3
Figure 6-7
-> C(TPR.TRR)
15
Format of Instruction Word ADDRESS When Bit 29
=1
After this preliminary step is performed. Effective Address Formation
proceeds as discussed above or as discussed for the Special ~odifiers below.
Special Modifiers
Whenever the Processor Is forming an
Append Hode Effective Address two
special
Address Hodifiersmay be specified and are effective under certain
restrictive conditions.
The special Address Modifiers are s~own in Tab'.
6-~
beJo" and discussed in the paragraphs follo"ing.
The conditions for which the speCial Address Modifiers are effective are as
followSI
1.
The Processor must be forming an Append Mode Effective Address, that is, it
must be in Append Hode or
In Absolute Hode "itn bit 29 set in the
Instruction Word.
2.
The Instruction Word (or previous Indirect Hord) must s3ecify Indirect Then
Register or Register Then Indirect modification.
3.
The Effective Address for the Indirect Word must be
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
&-1&
eve~.
AL39
If any of these conditions is violated. the $pecial Add-ess Modifier ~111
be interpreted as a normal Address Modifier and wII I cause a~ II legal Procedure,
Illegal Modifier Fault.
Table 0-4
Special Append Hode Address
~odifiers
Coding
H~ik
~Qdlficati~am~
itp
Indirect to Pointer
its
Indirect to Segment
INDIRECT TO POtNTER (ITP) MODIFICATION
If the condItions above are satisfied, the Processor examines the TAG field
of
the
Indirect Word for the value ~1 (octal). If that value is found, the
Indi.rect Word-paIr is interpreted as an ITP Pointer Pai~ (See Figure &-8 belo"
for format) and the folJowing actions take placel
For n
= CfITP.PRNUH11
C(PRn.SNR) -> CfTPR.TSR)
.axi.um (C(PRD.RNR), C(SOH.Rl), CITPR.TRR») ->
C(T~R.TRR)
CCITP.BITNOl -> C(TPR.TBR)
C(PRQ.HORDNO) + C(ITP.WORONO) + C(e) -> C(TPR.CA)
wherel
c
=
C(eT-HOLO) if the
preceding
Indirect
modification, or
field of the I~struction
specified Indi~ect Then
Word or
Register
C(ITP.MOO.Td) if the TAG field of the I~struction
preceding
Indirect
Wo~d
specified Register Then
modification ~ ITP.HOO specifies eithe~ Register or
Then Indirect modification.
Word or
Indirect
Register
TAG
Ho~d
=
z.
c
3.
SDW.R1 is the upper limit of the read/write Ring Bracket for
the
segment
C(PRa.SNR).
(See
Section
VIII,
Hardwa~e
Ring
Implementation.)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
&-17
AL39
Even Nord
o
0 0
-.Jl
Z 3
I
2 3
1
: PRNUtU 0 o
I
3
. _-.!Li _ _ _--L
0 0 0 0 0 0 0
0 0 0 0
DODO ODD 0
0 0
I
0 0 0 0:
J
(lt1)8
I
I
I
I
&
27
3
Odd Word
1 1
0
Z Z
2 Z
I
I
MORONO
I
I
18
Figure 6-8
I
SO 0 01
I
10 0 01
3
Z 3
3
-LZ__ 2 II
-----1-L-L1
D
~
J
BITNO
--1
I
6
3
J
HOD
~
J
6
I
ITP Pointer Pair format
Field
liiUD.Jl
PRNUH
The number of the Pointer Register through which to make the
segment refe~ence.
NORDNO
A word offset ualue to be added to C(PRn.MOROHO).
8ITNO
A bit offset ualue for the data itea.
Any normal Address Hoditier
I~
itp or its).
INDIRECT TO SEGMENT (ITS) "ODIfICATION
If the conditions above are satisfied, the Processor examines the TAG fIeld of
the Indirect Word for the value 1t3 (octal).
If that value is found, the
Indirect Word-pair is ihterpreted as an ITS Pointer Pai~ ISee Figure &-9 beloM
for format) and the folloMing actions take placel
CIITS.SEGNO)
->
CITPR.TSR)
maximum (C(ITS.RN), CISOW.Rl), CCTPR.TRR»
ceITS.SITNO)
->
->
CCTPR.TRRJ
CCTPR.TBR)
CIITS.NORONO) + elc)
->
CCTPR.CA)
.. herel
1.
2.
C = C(CT-HOLO) If the
preceding
Indirect
modification, or
c
TAG
Wo~d
=
field of the I~structlon
specified Indirect Then
C(ITP.HOD.Tdl if the TAG field of the I~structlon
preceding
Indirect
Word
specifIed Register Then
modification ang ITP.HOD specifies either Register or
Then Indi~ect modification.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
&-18
Word or
Register
Word
or
Indi~ect
Register
Al39
3.
SOW. Rl is the upper I i ml t 01 the readh.... l te Ring Bracket for
segment
C(ITS.SEGNO) •
(See
Section
VIII. Hardware
Implementation.)
the
~lng
Even Word
0
0 0
_L_LL
a
J
10 0 01
2 2
D1
t
SEGNO
J
I
I
.1
1 1
-L4
RN 1O
I
15
3
2 3
_9
o
I
0 0 0 0 0 0 01
-I
.)
3
a
~
I
I
(43)8
I
<1
6
2 2
2 3
:5
6 Z
-La.
2
Odd Word
2 2
1 1
0
Za
D
I
I
a1
I
I
10 0 01
WORD NO
I
I
BITNO
a
I
0 OJ
3
()
I
3
6
ITS Pointer Pair Format
Field
lUlu
HeaDIng
SEGNO
The number of the segment to be referenced.
.. ORONO
Word of fset to be used in the effective
BITNO
The bit offset for the data ite ••
HOD
Any valid normal Address Hodlfier.
The detaIls of Effective Segment
flowchart in Figure 6-10 below.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
I
1
HOD
I
I
I
18
FIgure 6-9
I
J
Number
6-19
generation
address
are
formation •
shoMn
in
the
Al39
~IA!u
(S.H
I
_ _ -.i ___ _
I
WclS
IdSt
,
cycle dn
,
'Indirect Word I
'J.~1c..!l.1. _ _ _ 1
-I~~I
I
I
I
I
I
I
I
I
*
Was it a ,
seQuential '_1Q. _ _ __
instruction I
J
I
I
,
I
I
I
No
\_L~l~l
____1
__ 1---
I
I
a
I
I
:
I
I
I
I
I
J
I
I No
I O=C(TPR.CA10.2
I
I
Yes
I
\
"
Is Dit
,_~
29 ON?
I
\ _ _ _1
I
_ _ _ _ _1 _ _ __
1<----------------.
-1_
I
______ _
I C(PRO.S~R)
->
I C(TPR.TiR)
1---___________
I
C(PPR.PSR) -> I
a cnPR.TSR)
I
L _ _ _ _ _ -1
~
I
I
I
I
+----------->1J <------------------------------------t
----*-----I
EA CYCLE
J
(F Igure &-2) J
J
_ _ -i_ _
I
\
Indirect
\-1~ _______
, Hord fetch? I
I
I
' _ _ _ _ _1
:
:
I
I
I
I
I
No
I
,
*
,
,_In-____ _
I
I
I
I
I
I
J<------------------+
I
•
No
I
t
Go to
"A ..
~o
to
-e-
( Fig ur e 0 -lOa»
Figure &-10
\
RI or IR &.
TPR.CA even?1
(F ig~,.e &-10 a)
Effective Segment Number Generation ='oMchart
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
&-20
Al39
"8I
,--*--,
_ _ _ _ ~Q._I TAG =
I
'ITS?
-L-_
I
TAG
\ ITP?
I
='\
, _ _,
'-Ie~
,
•
n
No
,
, Normal
'\ yes
\ Indirect? ,
,
'\
,
\
,
I
I
I
C(Y+1)O,17 -> I
C(TPR.CA)
J
J
•I
I
J
J<-------------------------+<-------------------+
•
SIMI ES.!i
(Figure 6-10)
______________
\
'\-1~
-'
,
I
t
C(y)3,17 ->
C (PPR.PRR)
No
I
CAll6 or
\ Transfer
\ Operand?
\
I
yes
J
I
J
2
I
________
\
C(TPR.TSR) ->
C(PPR.PSR)
I C (lPR, CA) ->
I
1. C (ePE, IC1 ____l
J
I
I
J
I
I
J
~t_____
I
I
I
J No
t
I
C(Y+1)D,17 ->
____~
1-k1E~~.~I_C~)
'\
APU data
\_u.NQ____
\ lIIovellent?'
I
I
\-----------,
I
•
1
C(PRn.SNR) -> I
C(TPR. TS'U
I
C(PRO. WORDNO) +1
t
I
C(Y+1)D.17 ->
Go to
•
RTCO
\ Operand?
= C(Y)O,2
I
~~&a.A&..)_ _.....
I
No
I
C(Y) 3,17 ->
C(TPR.TSR)
_ _ _LI _ __
<-------------~---------t
I
J
t
_________
'--'
I
I
'..:l~~
,
Yes
J
•<----------------------+<---------------------+
•
ftftl E.S..H
Go to
Execute
Cyc'e
Figure 6-1Da
Effective Segment Number Generation F'ow:hart (Con't.)
EfEECTI~E_A~~~HAIlQN
fOR
EllE~INSTRUCIION
SEI
A flowchart of the steps involved in Operand DescriptJr Effective Address
formation is shown in Figure 6-11 below. The flowchart depicts the Effective
Address formation for operand ~ as described bv its Modification field, MFh.
This Effective Address Formation is performed for each opera~d as its Operand
Descriptor is decoded.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
6-21
Al39
SlAlU
.lIS. fA
I
_riLl
I
\
f
:
--L-
,
MFJ1.10\-1._t_s_ _ __
= 1?
\ _ _,
/
I
----*---I
I
I
I ESN CYCLE
:CFigure ;-10)1
J
I
I
I
I
I
t
J
I
I
J
I
----*---I Operand
1 Descriptor
I
: APPEND CYCLEI
l.-1E~_.i::.!tll
J
1<----------------------+
/
______~I
,
--*--
MFJ1.A~\_~Y&e~$
\\ _____
= 11 , ,
I
t
_______
I
______At_____ _
J
I
I O=nul.
1--
O=C(Y)O.2 I
(NOTE 11--1
'
•
I
t--------------+--------------+
-L_
/
\
_ _ _-X.u.-/HF1s.. RE G\_11...
o _ _ __
I
\ = 01 I
_____...
t ____ _
t
\ __/
I
J t:=nul'
J
c.=HFiS.. REG
L-_ _ _ _
.A-
I
I
+--------------+--------------+
t
Form E f f e c ti v t
Word/Char/Bit
Address f rom
Y, CN. C. B.
C(PRQ).
:
1
C (I:,)
(NOTL1..s.2)
I
I
I
I
I
t
EtUl
E.I.S. U
Figure 6-11
EIS Effective Adress Formation
Flo~chart
NOTE 11
The symbol uy" stands for the contents of the AOD~ESS fitld of th~
Operand Descriptor.
The svmbols "eN" and "C" st3nd for the contents
of the Character Number fie 'd.
The symbol "B" sta,ds for the contents
of the Bit Number field.
NOTE 21
The algorithms used in the formation of the Effective Hord/Char/Bit
Address are described in "Character- and 81t~String Addressing"
fot IOil'lin9.
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
6-22
AL39
The Processor represents the Effective Address
bit-string operand In three different forms as follows&
1.
a
0"'
character-·
0,.
Pointer Regist.r Form
This form consists of a word value (PRn.WOR)NO) and a bit value
(PRn.BITNO). The word value is the wo,.d offset of the word containing
the first character
bit of tne operand and the ~it value is the bit
position of that character or bit within the wo,.d.
This form is seen
when C(PRn)
are stored as an ITS Pointer Pair 0,. as a Packed Pointer
(See "Indirect
to Segment (its)
Hodification" earlier In
this
Sect ion).
0,.
2.
Address Register For.
This form consists of a word value CARn.WORDHO). a character number
CARn.CHAR), and a bit value (ARC.BITNO). The word value is the word
offset of the word" containing the fIrst cha~acter or bit of the
operand. The character number is the number of tne 9-bit character
containing the
first character or bIt. The bit ~alue is the bit bit
position within ARO.CHAR of the first character or bit. This for", is
seen when ClARO)
stored with the Store Address Register Q (SARa)
instruction.
are
3.
Operand Descriptor For.
This fora 1s valid for character-strIng operands only. It consists of
a word value (ADDRESS) and a character number (CN).
The word value is
the word offset of the word containing the first
characte,. of the
operand and the characte,. numbe,. is the number of that character
within the wo,.d.
This fo,.m Is seen when C(ARa) is stored with the ARC
to Alphanumeric Descriptor (ARAO) or ARQ to N~meric Descriptor
(ARNa)
instructions.
(The Operand Descriptor form for bit-string operands is
identical to the Address Register form.J
NOTE'
The terms ·Pointer Regist.r" and "Address Register- both apply to the
same physical
hardware register.
The distinction arises fro. the
manner In which
the registe,. is invoked and used and in the
interpretation of the ,.egister contents. "Pointer Register" refers to
the regIster as used bv the Appending Unit anj "Address ~eglster
refers to the register as used bV the Deci_al unit.
The three forms are compatible and may be freelv intermixed. For example,
PRQ may be
loaded in Pointe,. Register form with the Effective Pointer to PRn
(EPPo) inst,.uction, then modified in Pointer Register form ~ith the Effective
Address to WordlBit
Number of PRO (EAWPn), then further modified in Address
Register form (assumln~ character size~) with the Add h-Bit DIsplacement to
Address Register
'A~BD) instruction, and finallv invoKed
form by the use of HF.AR in an EIS Hultiword instruction.
Cbaracter- and
B~clng
A~~~Llibmetic
i~
Operand Jescriptor
Algorlthm~
The arithmetic algorithms for calculatIng cha~acte-- and
bit-string
addresses are presented below.
The svmbols "ADDRESS" anj "eN" represent the
REVIEW ORN'T
SUB~ECT TO CHANGE
October. 1975
6-23
AL39
ADDRESS and CN fields of the Operand Descriptor being decodej. "1:,-- and --a.. are
set according to the flowchart in Figure 6-11 above. If either has the value
"null". the contents of all fields shown is Identically zero.
9-BIT CHARACTER STRING ADDRESS ARITHMETIC
Effective CHAR
= 0000
= (CN +
Effective NORDNO
= ADDRESS
Effective BITNO
CeARO.CHAR) + CeC»
(CN +
modulo
+ CCARO.WORDNO) +
C(A~n.CHAR) + Cee»
I
~
~
6-BIT CHARACTER STRING ADDRESS ARITHMETIC
EffectIve SITNO
Effective CHAR
EffectIve WORONO
= ( rZ, the procedure is a gate for ring rZ, accessible fro.
rings no higher
than r3; if r2
r3, tne procedure is not a gate.
=
Third,
it "as found useful to relax, also for data seg.ents, the condition
that_they be assigned to onlv one ring. One would like to ba
able to specify
that a
segment resides
In ring rl for ·write- purposes b~t resides in a less
privileged ring r2 for -read- purposes.
Fourth, several difficulties ~ere encountered in
the Implementation of
outward calls and
their
associated returns. Because outward calls were not
found essential for implementing the Multics system. they we-e sImply declared
illegal,
and as a result, a procedure with ring brackets (rl. r2, r3) cannot be
called from a ring R such that R < rl.
In summary, the operations that are potentIally permitted to a
ring
process
In
R on a segment whose ring brackets are (r1, r2, rJ) are as foilowsl
Write
Read
Execute
Inward call
I
I
I
I
if
If
if
if
0 <= R <= rl
0 <= R <= rZ
rl <= R <= rZ (Execution in ring R)
rZ < R <= rJ (Execution in ring r2)
The attempted operatIons are permitted if, in addition, the user has the
appropriate access rights (read, write. execute) on that segment.
The Multics Processor offers hardware support for the implementation of the
Multics ring protection.
A .particular effort was made to minimize the overhead
associated with all
authoriZed ring crossings, which the processor performs
without operating system intervention, and to mInimize the overhead associated
with the validation of arguments, for ~hich the processor provides a valuable
REVIEW
DR~FT
SUBJECT TO CHANGE
October, 1975
8-2
AL39
assistance.
The rumber of rings available In the processor is eight, numbered from 0 to
The current ring R 01 a process is recorded in a hardware register
lPPR.PRR) •
7.
The ring brackets
(rt, r2, r3) of a Segment are rec~rded in the Segment
Descriptor Word (SDW) used by the hardware to access the seg~ent.
In addition,
the SOW contains the number of gates (SOW.eL) existing in the segment.
The
hardware assumes that aJ. gates are loc~ted from ~ord 0 to ~lrd (CL-1) and does
not accept an in~ard call to this segment if the word num~er specified In the
call Is greater than (CL-1).
The reason for
this control
is to prevent a
malicious user from generating a call that would transfer control to any machIne
instruction of the gate procedure.
(Such a call would defeat the purpose of the
gate.)
The sow also contains the access rights (read, write, execute) that the
user has on that segment.
If the same segment is used by several processes,
there is an SOW describing the
segment!n the Oescriltor Segment of each
process. In all SOWs pOinting ~o the Same segment, the values of r1, r2, r3 and
CL are identical since they are user independent.
The value of the access
rights (read, write, execute) are not necessarily the same because they are user
dependent.
In order to provide assistance in argument validation, any pointer, being
stored into an ITS Pointer Pair or loaded into a Pointer Register, also contains
a ring number.
Although the hardware does not prevent a process
from writing
any ring number in an ITS Pointer Pair, it ensures that, if (r1,r2, r3) are the
ring brackets of the seg_ent in which the ITS Pointer Pair is located, the ring
number field of this ITS Pointer Pair can be set or modIfied only from ring R
such' that R <= r1.
As for the ring number recorded in a Pointer Register. the
hardware ensures that a process in ring R can set it to a ~alue equal
to or
greater than R, but never sa.ller.
During
the execution of a machine instruction, the hardware may examine
several SOWs. ITS Pointer Pairs and POinter Registers.
For any given such
examination,
the hardware records the maximum of the current ring, the r1 value
found In an SOW. the ring number found in an ITS Pointer Pair, or the ring
number found in an Pointer Register. This maximum, called the Temporary Ring
Number, is kept In a hardware register (TPR.TRR)
that
is updated each Such
exaalnatlon.
The reason for having this Temporary Ring Number available at any point of
a
machine instruction Is because it represents the highest ring
(teast
prIvileged)
that might
have created or modified any information that led the
hardware to the targe t segment it is abou t to re ference.
Al t hough the current
ring 1s R,
the hardware uses the most peSSimistIc approach and pretends the
current ring is CCTPR.TRR), which is always eQual to or greater
than R.
Thus
the hard~are uses ClTPR.TRR)
instead of R in all comparisions with the ring
brackets involved in the enforcement of the ring protection rules given
In the
previous paragra~h.
The use of ClTPR.TRR) by the hardware allows the gate procedures to rely on
the hardware to perform the validation of all addresses passed to the gate by
the less privileged ring.
The general
rule enforced here by the hardware
regarding ar
1-t
I
t
Go To
··A-
(Figure 8-1a)
Figure 8-1
Complete Appending Unit Operation
FI~"chart
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
8-4
AL39
..."
I
t
I
,
'Is SOW 'or ,-llA._ _ _...._ _ _ _ _ _
~
\CCTPR.TSR) I
I
\1n-1WtWI
I
I Yes
*
-IA_',I .
,
~SaR.U
I
1
I
\
,~v.~S~
01
,
___
I
•
'
I
DSPTW 1
I
____
•I
I
t
,
I
t
V'S
I
,
\
OSPTW.'
\ set ON?
\
, set ON? ,
\
,
In1t1ate a
I
I
I
a
MOSPT.U
____
1
I,C-----.,---..+
__~t~.__
I
I NSDW
~t~~
PSDW
•I
I
I
tI
c,..-..
_ ---~---t
, ,
___v.'_$1 sow.
\ set ON!
,
,
F
__
,_tl~Q
I
I
t
I
Directed Fault
t
I
I Yes
Load SDWA"I
.r..-_ _ _ _ _.l
•
I
\
DSPTW.U '_"_Q_~_
,
..
'I_"I&lQI&-_I
•
In1tlat. a
Dirac: tad Fau' t
+-------->1
•
I
I
leISON.RU->1
IClRSDWH.Rl)1
I
•
I
Go
•
to
-a-
(Figure 8-ib)
Figure 8-1.
Compl.te Appending Unit Operation Flowchart Ccon-t.)
RE.VIEW DRAfT
SUBJECT TO CHANGE
Dc tober. lCJ15
8-5
AL39
I
\
_ _-u.N2-1 C(SDW.R1l
=< \
\ CCSDW.RZ)=< I
1
t
\ C1.S.IHL..lUll._'
I
t
I
t Set F au It
I ACVD=IRO
Yes
I
L ____
-L
I
I
I
+-------------->1
_ _ -L-__
I
Was last
\
____~N¥o_1 cvcle an
\~
\ RTCO operandi
J
t
\_Lel~
I
I
t
__ 1
Go to
"C"
\
Is OPCOOE \-1~
\ CALL&?
I
I
_-.\JNLlo(.o_1
\
t
I
\
I
ITransfer or\ yes
\instruct"ionl
\ -1.Jt:tkht-1
(F 19urc 8-1el
•
Go to
"E(Figure 8-1d)
•
•
. I
Go to
I No
"F"
(Figure 8-1e)
t·
I
\
\
I
Is ita '_y._es...._ __
\ STR-OP? I
_ _ _ fuLl
I
t
I
\
IC(TPR.TRR»\-I_e~$
_____
\ C(SDW.RZ)?I
,_
t
I
\
I
I
\
IC (TPR. TRfU >\_Y~e....s_ __
,
t
C (SOW. RZ)?I
I
a
t
J
Set Fault
ACV3=ORB
I No
I
I
I
No
'1
I
a
t
, _ _ _,1
I
I
J
I
J
I
I
J
Set Fault:
I ACV4=R-OFFJ
\_:.r.N...
o _ __
I
I
' _ _ _ _1
t
\
__ ----H~/C(PPR.PSR)='~_
I
\CCTPR.TSR)?I
I
__-L__'
,
SO W. W
,
ON?
I
I
t
I
I
I
1
I
J
I
<-------------+
t
_ __
I
ACV5 =) WB
r
,
\_~
I
J
Fault
L ___----1
1<-------------+
t
--.bs.J so W. R
I
,
ON?
S~t
I
Yes
I
I
ACV6=W-OFFI
Set FaJJt
I
I
1--_ _ _ _1
I
I
J<--+<------------t
1
1 -____.-...1..
+-------->+----------------------~->I
•
Go to
-G"
(Figure 8-10
Figure 8-1b
REVIEW DRAFT
SUBJECT TO CHANGE
october 9 1975
Complete Appending Unit Operation
8-&
Flo~chart
(con·'.)
AL39
:0::
, J
J
t
1
,
_ _ --.t1sL1 C(TPR. TRRJ <
:
, C (SC W. RU 1
t
,
,~
I
1
I
,
, \
, ClTPR.TRR»
\ ClSDW.RZJ?
\
I
'_yes
1
I
I
_,
t _____
I
I Set Fault
No
I ACV1=OEB
l _ _ _ _ _...a.
I
1<---------------------------.
--L-
,
2
\
1 SDW.E '_N~o
_____
\set ON11
I
\ _ _ _1
t
a
I
J
I
a
J
I Yes
I
I
I
I
I
I
I
I
I
I
t
t
I
I
I
1
Set Faul t
ACV2=E-OFFJ
__
_ _ _ _1
I
1<-------------+
t
,
,
, C(TPR.TRR»='_~~Q________
\ ClPPR.PRfU? ,
\
•1
J
-'
t
Yes
I Set Fault
t
I
a
a
1 ACV11=INRET:
I
I
I
I
J
1
+-------->1<----------------+
--L1
,RALR ,
, = 01
'---'
I
'~N~Q
1 Yes
2
2
1
I
.
_____
,
I
,
C(PPR.PRR) \_H_o____
, < RALR?'
I
,
1
I
J Yes
+------------>1I
:
I
_-,tL-....___
I
I
Set Fault I
A:V13=RALRI
L-_
1
I
+---------------->1I
t
Go to
(Fj~u,.e
a-1f)
REVIEW DRAFT
SUBJECT TO CHANGE
Oetobe,.. 1975
8-7
AL39
"E"
a
__LI-
,
SOW.E \
,
ON? I
I
_____
I
___1
- -__
uN~o
' _ _ _I
I
I
Set F au 1 t
I Yes
I
ACV2=E-OFFI1
___________
J
I
1
1<-----------+
I
_--L-
,
_-""Y....
e_s _I
SOH. G
'ON?
I
*
' ___ I
1
' I
,___
1-
C(PPR.PSR)= \
\ C(TPR.TSR)? 1
-I No
I
__---.titLl
I
t
I
\
I
I
\
I
C CTPR.CA) £t, 17 '-liQ. _ _ t
>= SOW. CL?
I.
I
\
I
I
J
I
, Yes
I
I
I
I
Set fault I
I
t
ACV7=NO GA'-
~1_-
'1es
I
<----------f.
,
&
_______---1
I
t
I
I
1<--------------+
I
\
,
\
C(TPR.TRR)
, C(PPR.PRR»
,
\
C(TPR.TRR)\ yes
> SOW.R3? I
I
t
\
1 C(PPR.PRR)' __
ye_$_____
No
,
<
SOH.RZ? I
,
a
1
t
No
Set Fau 1 t
ACV10=SOC
I
1<-------------+
*
,
______________
CCTPR.TRR)\~No
< SOH.R1? I
,
I
I
I
t
I
1
I
\
I
I
,
I Set Fault
t ACV8=OC8
J
I
I
I
t
I
I No
I
>\_X~ews~_
I
t
I
\
I
1<------------1<-------------+
T
t
I
~1
I
\
\
,
C ( TPR. TRR) \_1itL. _ _
> SD~.R2? I
I
I
_ - - - L_ _
Yes
I
No
Set Fault I
ACV9=OCALLI
t
Figure 8-1d
SOH.RZ -> I
C(TPR.TRR)1
1 -_ _ ----1
I
I
I
1
l<-----------~----------+
I
I
1
:<-----"----_ ..... _+
Go to
"0"
(Figure 6-1c)
Complete Appending Unit Operation Flowchart (conet.)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
8-8
AL?9
··fI
•
1
\
_ _ _ tijLl
'_In..
2.
1
C(TPR. TRR) <
\ C(SCW.Rl)?
,
t
1
C(TPR.TRR»
, C (S 0 W. RZ ) ?
\
1
,
1
\-I~$~
J
I
I
________________~t
J
1
•
1
No
Set fault
ACV1=OEB
I
I
I
1
J<---------------------------t
1
-*--\
1 SO W. E
',~N.>&o__
'set ON?I
t
__~t~____
' _____I
I
I
aYe s S e t F au I t I
I
J ACVZ=E-OtFI
I
1I
I
I
.------------->1
,
,
•
_ _~NCLI C( PPR.PRR)= \
I
, CCTPR.TRRJ? ~
t
\
1
Set Fault
Yes
ACV1Z=CRT
+-------------->1
•
Go to
'·0"
lfl gure 8-1c)
FIgure 8-1e
Complete AppendIng Unit Operat1on Flowchart (con-t.)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
8-9
AL39
"G"
•
t
1
,
1
C(T?~.CA)0913
,
>
,
SOW. BOUND?
,~~
1
1
____
--.*---..
I
I No
Fault 1
~et
I
I
~CV15=00S61
I L L
1
I
1<---------------+
•
1
,
'_Xf!.L-__
Any ACV
\ Faults?
_---ti~_1
I
____~*_
____________
1
\
is
, C(TPR.TSR)I
~~_I
segment'-1~~s
1
I
"
•
Initiate an Access
Violation Fault
,
_____
,
t
'_~.aLI
I
PTW for' No
'C(TPR.CA) 1
'in PTHAH?I
~~/is
I
I
a
-,
i
PTW
I
I
:
t
S
I
1
J
t
I
I
1
1
,
_tll-I Is PTW.F'-H.~
:
, set ON? I
1
____~t_
,
1
•
I
Initiate a
load I
Directed Fault
I
J
I
I
I
I
PTWAtt I
~
__ --1
I<~-------------+
,,
--*--I
,' ____'
I
Prepage
115
Hode? 1
J
I
J
1
J
1
I
I
I
,.
No
PTWZ
I
I
I
1
iJ
•
•
Go to
Go to
"I··
(Figure 8-1g)
(Figure 8-1g)
Figure 8-1f
REVIEW DRAfT
SUBJECT TO CHANGE
October, 1975
I
_1
,
llS 1 Is PTW.F'_ti:t_
set ON? 1
I
I
"H-
,
t:
a
,----,
•
I'\itiate a
Directed Fault
Complete Appending Unit Operation Flowchart (con-t.)
8-10
AL39
-H-
-I-
I
I
I
t
I
I
I
I
_ _-uNLI
,
1
1
-~
1 PTW
,
STR-O? &\-1-..e....
s _ _ __
PTW.I1=O 1
I
' _ _ _ _1
---*---J
1
,
from'~ye~s~
___
, sfore l I
HPTW;Setl
PTW.H i. 1
PTW.U
J
J
'eIiL.JJ.~1
t_
I
•
S No
I
2 HPTW;Set:
1 pTW.U
1
1
J
L -_ _ _ _ _
I
l
+------------>1I <--------------t
~--
I
FANP
_____
I
~
I
I
I FAP
I
L---~
t
J
+------------------------>1
•
,
an Indirect 'J:i¥.o_ _
, Word fetch? /
a
/
1
Was this
,
/
t
an ,
1 Was it
I Yes
Go
•to
/
,
RTCO
operand
,
-.,J-
(Figure 8-1h)
fetcb?
•I
'JiL_a
I
I
Yes
t
Go to
(F i gure 8-11)
,
.--JtL-.._
/
1 Is OPCOOE
'CALL&?
,
I
I
•
____
',~N~o
I
/
--*__
I
'fes
Go to
,
/Transfer or'-H4---'Instructionl
I
__~tL-__
'~hI-_1
I
1
I
Yes
,
data '~N~o___
•
, movement? I
I
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I
I
1
~PU
(Figure 8-11)
I
1
Yes
I
a
t
1
J
I
Load/Stor-el
tlPU data 1
L_
1
I
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t
I
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<----------+
E..Wl
APPENQ
Fgiure 8-1g
Complete Appending Unit Operation
Flo~chart
(con·t.)
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
8-11
Al39
•• J"
I
t
I
\
RIoI' IR & '_~.~e~s____
I
\ TPR. CA even?1
I
,______'
___L - _
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No
\
C(Y)30,35
I TS Mod?
I
,
\
= \-HKo_____
1
_ _......tI_____ _
I
1
,
: Yes
•
\
C(Y)30,35
ITP Hod?
,
\
Go to
= \-1i.sL-_
1
I
_,
(Figure 8-1k)
1
I
I
J Yes
•
I
a
Go to
··P"
(Figure 8-11)
:
I
____t_____
+------------------------------------------·>1
1
______~y~1 C(Y)30,35
\
t
C(Y)O .. 11->
C(IHB)O,17
C (Y) 30,35->
I C(tHB)30,35
LQ->C(IWBI29
I
0
=\ ,
ther
,
\.-io;lirect? I
I
1 No
I
I
I
I
+---------------->1t
.Elifl
A.eeEWl
Figure 8-1h
Complete AppendIng Unit Operation Flowchart (con-t.)
REVIEW DRAFT
SUBJECT TO CHANGE
October. 1975
8-12
Al39
-K-a
:t1:!
=~
I
___ -*-__
__L---
I C(Y)3,17-> I
I C(TPR.TSR)
a
I C(Y+l)l,17->1
"
I
~
.l_klle.R...&AL-l.
Is OPCOOE
TSPQ?
'_y~e~s~
I
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J
---*.---
_--L-_
I
I C(PPR.PRru
No
I
I
I
t
C(TPR.TRR»=\-Yes
, C(PPR.PRR)1 , :
, _ _ _ _ _ _,
t
I
I
I for i=O,7
I
l
<---------------------t
C(TPR.TRRJ->'
C(PR1.RNR)
I
I
-1
L-
I
I
-> C(PRn.RNR)
C(PPR.PSR) -> C(PRa.RSR)
I
C(PPR.IC) -> C(PR~.HORONO)I
J 000000 -> C(PRO.BITNO)
I
"
I
I No
I
J
___
I
.--------------->1
t
•
C (TPR. TRR) -> I
I
C ( PPR.PRR)
-1
+--------> t
CCTPR.TSR)->I
: C (PPR. PSR)
I
I C (TPR. CA) -> I
LC.(PPR.IC)
I
I
I
+----------------------------------->.t
I
,
_ _....yUle~s'_.1 C ( TP R.T RR) ,-tiL_ __
I
•
\
,
=
01
I
I
I
-*--__
I
C(SDH.P)->I
C(PPR.P) I
L
I
J
O->C(PPR.~)
_ _---1
I
I
I
+----------------------------->.t
I
Is thIs an'
,~
I
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\
operand
'_~1~
J
I No
•
flW.
__1
I
I
•
Go to
"0·
(Figure 8-1k)
A.eeE.tiIl
Flgute 8-11
REVIEH DRAFT
SUBJECT TO CHANGE
October, 1975
Complete Appending Unit Operation
8-13
Flowcha~t
(con-t.)
AL39
:rt:
_ _tI __ _
,
~
\
____1~_' CCTPR.TRR)=
I
\
______~t_
C(PPR.PR~)?
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______ -L-_______
_
a
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-> C(?R7.S~R)
_ _ _ _ _--1.I
.1-_
I
+---------------------------------------->1t
J
C(TPR.TRR)
->
C(PR7.RNR)1
00 ••• 0 -> C(PR7.HORDNO) I
000000 -> C(PR7.BITNO)
1
C(TPR.TRR) -> C(PPR.PRR):
C(TPR.TSR)
C(TPR.CA )
->
->
C(PPR.PSR)I
CCPPR.IC)
_ _ _ -1I
J
t
Go to
CFigur-e 8-1i)
Flgu~e
8-1}
REV lEW ORAF T
SUBJECT TO CHANGE
October, 1975
Complete Appending Unit
6-14
Ope~atlon
Flo~cha~t
(conete)
Al39
"0"
J .
t
1
\
_ _ ti~1 C (TPR. TRR) >=\--1as. __ _
J
\
______t____
I
\
\
_I
RSOWH.R1?
\
_I
1
I
__ _____
~t
1
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\
1
______ ~_I C(Y)18,20 >=\_y&e_s_________-H~_I C(TPR.TRR»=\
I
\ RSOWH.R1?
1
J
. \ C{y)18,20? 1
_ _ _....
t___
•
I
J
RSOHH.Rl->1
Yes
IC(Y)18,20->1
C(TPR.TRR)1
J CCTPR.TRRJJ
;
I
J
+------------------------------>+-------------->1
t
EWl
APPEND
Figure 8-1k
Complete Appending Unit Operation FlowChart (con-t.)
:e.:
I
t
1
___~N~I
a
\ RSDWH.Rl?
t
I
\
C(TPR.TRR»=\~
\
_____
1
J
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I
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I
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______~N~I C(PRn.RNR»=\-1&e_s____________~N~1 C(TPR.TRR»=\
\ RSDWH.Rl)? 1
, C(PRO.RNR)? I
\
I
t
,___
1
t
I
RSDWH.Rl->1
C(TPR.TRR11
Yes
C (PRO_ RNfU -> 1
,C (T P R. T RR )
:
.
I
L
+------------------------------->+--------------->1
•
E.NU
A2.e.£tl.D.
FIgure 8-1k
R[VIEW
Complete Appending Unit
OR~FT
SU~JECT
TO CHANGE
October, 1975
8-15
Opl~(Oation
rolow.::hH"t
(conet.)
SECTION IX
CACHE STORE OPERATION
The Hultics processor may be fttted
described in this section.
~ith
an optional eache Store.
The
operatio~
of this Cache Store Is
The Cache Store 15 a hlgh speed buffer store
located within the Processor that is intended to hold operanjs and/or instructions
in expectation of their immediate use.
This concept is different 'rom that
holding a single operand (such as the Divisor 'or a Divide
instruct ion) in the Processor during execut ion of a singte l!lstruct ion.
A Cache Store depends on the localitv of Reference Princlpte.·
Local!"tv of Reference involves the calcul at ion of the probabll ity.
for any value of £1. that the ~ instruction or operan·d ref,erence after a reference
to the instruction or operand at location A 15 to location A.a.
0'
The calculation of probabilities 'or a set of values~' U reQuires the statistical analysis
of large masses of real and Simulated instruction se~uences ~nd data organizations.
.
It it can be sho~n that the aVerage p-xpected data/instructlo~ acces~ tim. reduction (over the rang_ 1 to
is statisticallv significant in co.pari~lon to the "~ed Hain Store acceSs time, the, the
Implementation of a Cache Store with block site ~ Hilt contribute a ~lgniflcant ,.prowe_ent.
In perfo,.lIIance.
The results of such studies for the Hultlcs Processor Mlth a Cache Store a~ described
a hit probablltty ranging bet~een SOX and ~5X tdepending On Insfructlon ~lx and data
organization) and a peformance improvement ~anglng up t~ 30X.
s~ow
be.o~
The Cache Store Is implemented as lOftS J&-blt Hords of high speed register storage MUh
associated control and content dlrectorv clrcultrv within
the Processor. It 15 fully integrated ~lth the norlilal data oath cirCUitry and is vi-tually invisible
to' all programming sequences.
Paritv Is generated, stored, and checked Just as in Hain Sto-e.
The total storage is divided into 512 blocks of 4 word~ each and the blocks ar. orga,lzed lnto
128 "Colu~ns-. of four ~levels" each.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 19.75
9-1
~)
Cache Storell1aln Stote Happing
Hain Store Is mapped into the Cache store as
desc~lbed
3elow and shown in Figure 9-1.
•
Hain Store Is divided Into ii blocks of 4 wordS each ar·ranged 1n ascendIng order and
numbered with the value of Finat Address bits 15 t~rough 21 of the first word Of. the bloc
•
All Haln Store blocks with numbers n modulo 128 are grouped associatively !llfh Cache Store
Column n.
•
Each Cache Store Column .at hold any four biocks 01 the
.
~ssoclated
.
set of
~~ln
Store blocks.
•
Each Cach~ Stor~ column has associated with it a four entry directory (one entry for each Lev
and a fwo bit "round ro~in~ counter.
ParIty is generat~d, stored, and checked on each directory entry.
•
A Cache Ol~ectory entry consisfs of a fift~en ~lt AodRESS register, a pre-~ett
T~G
•
or
L~vel
Number register and a level full flag bit.
When a Main Store block is roaded into a Cache Sto~e block at some level I" the
a;socia~ed Column, the Directory ADDRESS regIster for that Column and
Level is loaded with the Final ADdress bits 0 thro~9h 14~
(~evel selection is discussed in Cache Store c6ntroi folloHing.)
REVIEW DRAfT
SUBJECT TO CHANGE
October. 1975
AL39
two bit
I
I
f
I
I
Block
Black
0
1
Words
Words
0.3
... 1
...
1
I
I
I
I
Words
8.11
I
I
Bt ock
129
J
130
Words
(
Words
51&',519 I 520.523
_1
I
1
I
...
2
Block
I
I
Block
128
I
Words
I
I 512, S15
I
I
Block
I
I
Main
Store
I
I
I
J
I
I
I
I
li-127
I
Block
I
I
-t
I
I
I
I
t
1
Column 'I
1
0
Level I
I
Coiumn
I
1
level
I
I
level
.l ___ - - 1____- L
J
Cache
Store
Column
I
I
a
0
I
I
Level
1
J
1
J
1 ___ ---1.
I
I
I
I
I
Coiumn
0
Level
l
CoJumr't
Column
I
0
I
I
I
2
I
Level
I
1
I
L-..
I
1
I
2
Level
I
Level
•I
•I
2
I
2
1
Column a
Column
I
1
Figure 9-1
I
I
I
I
I
J
Column
I
I
2
I
level
I
3
I
L-
508.511
Block
255
Words
...
I
1
Words
Words
-8 .... 5
J
- ... ~i
tt-l
i
Level
12&
0
12&
12&
Level
-
I . Co luiln
126
•I
LeveS
I
3
a
*
Co lunm
1
t
127
Level
0
I
I
1
1
I
1
I
I
I
I
I
I
I
I
I
J.
I
I
Column
I
•
--'-
I
Columr\ I
2
fi
,
I
t
I
1
1
I
I
I
Bloek
I
I
Column
Hain Store/Cache Store
...
I
I
I
J
alock
I
J
I
I
I
I
I
I
I
I
I
t
I
Level
a
I
I
1
__1 -___
I
J
J
Column
I
I
I
J
I
I
I
I
Column
J
Level I Level
3
J
1.___-----1.
_ _ 3_
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1975
•
...
I
1
I
I
J
,
0
Level
.1
I
J.
I
I
I
I
I
I
I
I
I
Words
121
Words
I
J
I
I
254
Block
I
I
I
t
~
Column
2
I
_._1-_ _ _ J
--t
I
0
...
I
1
1
I
I
I
1101&.101911020,10231
I
1
I
I
I
__ --1
0
I
•I
S
Block
a
Block
Words
1
I
I
I
I
I
I
I
• 504.507
J
I
I
I
I
Block
12&
Words
I
• ••
•••
Block
1-_'_ _ I
•I
ti-125
ti"'12 &
1 Words I
1 Words
1-512,-509,-506,-5051-504,-5011
J
•••
I
I
I
t
Column I
127
1
level
I
1 .
1
Co1umn
I
I
1
I
121
Leve'
2
,
I
I
J
Column 1
121
Level
3
f
I
J
I
Happin~
AL39
For a read operation, the 2~ bit Final Address ~repared by th~ Ap~e~dln9 Unit 1s presented
simultaneouslv to the Cache Control and to the Hain store po~t selection circuitry.
While port selection is being accomplished, the Ca~he Stor. 1s accessed as 'olloMs.
1~
throUgh 21
a~e
•
Final Address bits
•
Final Address bits 0 through l4 are matched assoclatlveiv against the tour Directory ADDRESS
reglsters for the seJected COlumn.
used to select a Cache Store ColUMn.
•
It a match occurs fo~ a Level Whose Full fiag Is O~, a htt is signal ted, t~e Haln Store reference
cvcle Is cancelled, and the TAG register Is read o~t.
•
The TAG vdlue and Final Address bit~ Zl and 23 are used to Select the Level and Word in the selected
ColuMn and. the Cache Store data Is read out into t~e data clrcuitry.
•
1r no hit is Signalled, the Hdin Sfore reference ctc.e proceeds and a Cache Store blOCk load
cycle t~ Initiated (See Cache Store Control beloN).
For a MrUe operation, the 24 bit final Address prepared by the Appending Unit is presented
simultaneously to the Cache Control and to the Hain Store p.o'"t selection cH"cultry.
While port selection is being accomplished, the Cache Store I~ accessed as to'to~s.
a~e u~ed
to select a Cache
Stor~
•
Final Address bits 15 through Zl
•
final Addres~ bits 0 through l~ are Matched
registers Jor the selected Column.
•
It a match occurs for a Level Mhose FuJI flag is
•
The TAG value and Final Addre~s bits 22 and 23 are used to select the Leve' and Word In the selected
Column, a Cache Store wri'. cvcle l~ .nabled, and the data is ~~ltten
to the Hain store and the Cache Store slmuitaneously.
•
It no hit Is signalled, the Haln Store
assoc1at~vetv
~ererence
O~,
Cot own.
against the four 01rectorv ADDRESS
a hit is signalled anj the TAG register is read out.
ctcle proc.eds Mith no rurther Cache store action.
The Cache Store Is controlled by the state of several bits in the Cache
Mode Register (See Section IV. Program Accessible Registers, for a diSCUSSion of the CaChe Hode Register).
The Cache Hode Register may be loaded Mlth the load Central ~rocessor Register (LCPR) instruction.
.
The Cache Store control bits are as follollSI
b.11
The lower half of the Cache Store CLeye's 0 and 1) Is disabled and is
totally inactive.
The lower half of the Cache Store Is active and enabled as per
the state of bits 20 an~ 21.
18
REVIEW DRAfT
SUB~ECT
TO
CHANGE
Octr ber, 1975
o
1
o
20
1
o
21
1
23
D
1
NOTE'
the upper half of the Cache Store CLewets Z a~d 3) Is dlsab_ed and Is
totally In~ctlve.
the upper halt of the Cache Store 1s active and enabled as D.r
.the state
bits 20 and 21.
0'
The Cache Store (If active) ~ ~ ~sed for Operands and Indirect Words.
The Cache Store U f active) is used for Operands and IndIrect Words.
The Ca·che store ( l f active) is. rutl ",sed for tnstri,Actlons.
The Cache Store Ci' active) is. used for Instructions.
The Cache-to-Register mode 11 lUll. ,,, et .ect (See "OuIIPlng t"te Cache Store"
foil~~ing 1n th!s
Section).
The Cache-to-Register mode is. in effect.
The Cache Store option furniShes a switch paneillaintenance aid that attac"es
to the free edge of the Cache Store Control LogIc Board.
The switch panel provides six switches lor manual control of the Cache Stj)-e.
four of the sMitcheS inhibit the control functions
bits 18 through 21
the Cache Hode
and have the effect of forcing the correspondlng '.lnction to be disabled.
The fifth switch inhibits the "store-aside- featur~ wherein the Processor Is perllitted to
proceed i~mediately after the Cache Store write cycle ~n write operations ~ithout waItIng
for a data acknowledgellent frOM Hain Store.
(There is no so.tware control corresPOhding this s.lteh).
The sixth switch forces the "~nabled" condition on all Cache Store con~rol$wlthout reg~rd
to the corr5ponding Cache Hode Re91~ter ~ontrol bit.
There &s no Switch corrspondjng to the CaChe-to-Re~lster control bit.
0'
0'
Re~1ster
Whl(e·the~e
switches ar~ intended primarily for Malnt~riance seSSions, they have been
'ound useful in testing thf C~che Store durin~ nor~a' operatlon ahd lnperlttting
oDe~atlon of the Processor with the Cach. Stor. In d~~raded or Dartially dlsabied 1I0de.
CertaIn data have characteristics suCh that they should never be loaded into the Cache Store.
Primary exaMples of such data are hardM~re mallboxes tor the 1/0 MultipleXer, aulk. Store Controller. etc.,
-status return wordS, and varlou~ dynallic system data base se~ments such as the Systel Seg_ent fable and
shared Directorv SeQments.
.
In general, any data that Is purposely lIodlfied by an agency external to the Process~r
, with the intent to convey lnformation to the Processor should never be loaded Into Cache store.
Bit 51 of ttle Seg:lent De~crlptor Word is used to reflect this prol)erty ot .0enca::habllHY" tor each segment
(See Section V. Addressing -- Se~mentatlon and Paging. for a disctission ot the Se9me~t Descriptor Wordl.
If the bit 1s set ON, data 'roni the segllient lIay be loaded Into the Cache Store; If the bit 1$ OFF, they lI.av not.
The enc3chabl11tv property may be treated asper.anent (e.go, for hardware lIall~oxes) or dynallic
(e.g •• certain shared data baSe~) by the operating system.
The op~~ating system sets bit 57 ON or OFF as
approl)riate 'or the function to be performed on the segMent.
The Cache Store 15 loaded Hith data impllclt.y whenever a Cache Store Block Loa1 is sIgnal led
(See t~e discussion ot read operations in "Cache Store Addres~ing~ above In this section).
There is no explicit method or instruction to load data Into the Cache Store.
REVIEW DRAFT
SUBJECT TO CHANGE
October, 1915
When a Cache Store Block load is signalled. the Level Is Selected frOM the valut of the
Round Robin Counter for the selected Column, and the C~che Store Write function Is e~abled.
(The Round Robin Counter contains the number of the least recently load~d Leve'.)
When the data arrives frOM Haln Store, It Is written into th. Cache stor~ and
e~tered into the data circuitrv_
The Processor proceeds with the e~~cutlon of the
instruction requiring the operand 1f appropriate.
When the Cache Store Write Is complete. further Address Preparation Is InhIbltej, bit ZZ of the
Final Address Is Inverted, and a seeond Hain Store access '01" the other hal f 0' the bloc~ is lIIade. When the
second half data arrives from Hain Store, It is wrItten Into the Cache Store,
Final Address bits O,through 14 are 'oaded into the ~'r~ctor~AOO~ESS RegiSter.
the Level F'ul' flag is set ON, the Round Robin Counter is ad.,anced bV 1, and
Address Preparation is permitted to proceed.
I f all four Leve,' Full IIags for a Column are set IlN, a ColUMn Full
remains ON until one or aore Levels In the Column are ctea~ej.
flag
1s also set ON and
Cache Sto~e can be tlea~ed In two ways; General Clear a~d Selective Ciesr.
The clearing action is the salle in both cases, na,.ely, the F" .. flags
the
selected Column(sJand/or Level(s) a~e ~et OFF~
0'
GENERAL CLEAR
The enUre Cache Store is cleared bv settln;a All Colulln and Level Full flags to OFF In the foiloMin9
s 1 tuat 'onsl
•
Upper or lower CaChe Stor~ or both beco .. ing enabled by appronrlate bits In the operand
a Load Centra' Proce5~·)r Register (LCPR) Instru:tlOn. or by action of tha LOIJie Board 'ree edge swltche1
•
E.lCecutlon of
0'
a Clear Associative Hemory Seg.ents (::A"S) Instruction wUh. bit
15 of
the address field
SELECTIVE CLEAR
The Cache Store Is cleared selectively as followSI
•
If a Read-and-Clear operation (LOAC. SINC. etc.) results in a hit on the
Cache Stor~ block hit 1s cleared.
•
of a Clear Associative Memo~v PageS (CAH~) with address bit 15 set ON causes
final Address bits Ii through lit to be .. atched against
Cache Directory ADDRESS Registers.
All Cache Store blocks hit are cleared.
Ex~cutlon
Cac~e
Store, the
..au.
When the Cache-to-Register mode 11ag (bit 2~ of the Cacna Hode Register) Is set ON. the
Is forced to fetch the operands of all Dou~le Precision Operations Unit Load operations 'ro ..
REVIEW O~AFT
SUBJECT TO CHANGE
October. 1915
AL39
Processo~
0
the Cache Store.
Final Address bits 0 throUgh 14 are ignored. Fina. Add~e~~ bIts 15 throu~~ 21
select a ColUMn, and Final ·address b't~ 22 and 2~ sele~t a levet~
All other operations (e.g., InstructIon Fetches. Sln91e Precision Operands, etc.) are
treated norMally.
Note that the phrase ·treated normally· as used he~. includeS the ca~e _he-.
the Cache St~re In enabled. It the Cache ·Store. 1s enabled, the Wother" op*ratlons wi'l
cause ~ormal Block Loads ahd Cacho Store Writes th~s destr~ylng the orginai contents
of the Cache' Store.
~ARNlttyl
An Indexed pr09~a~ loop inVOlving the LOAQ a~d STAQ Instructions wIth the
will serve to du~p any or al' of the CaChe Store.
Note I
OPERATION CODE HAP lBlT 2'
-..JlQ D
Cache-to-~egiste ...
lIode bit Is reset
= d)
0 01 -.D..Ut_1l.Jl.L--1lDJt__ .D...ll.L-1.Il~I_--1l1L-u..1L-..IllZ."':---lI.J..L.__.ll.1L_Il.1.L_-JQiLoj1""'&~1-'0......110.&7_;IHHE
JORL I
IMMEl IMME3 I
IHHE4 I
INOP 'PULSllPUlS21
ICIOC I
•
020
JADLXOJADLX1IADlX21AOLX3IAOLX~IAdlX5IAOLXoIAOLX71
o£) 0
J..A.Q~ADll_lAJl~Z.-1A1lU-1AD.l!t..J.AlllL1All.XLlAUll_L _ _1Ad.C A
o~o
aode bIt set ON
If a Faul tor PrOgraM Interrupt shou1 d occur during the C!ixecut ion
of a Cache Store dUlI\pi~1 loop, the Caehe-t~-~egiSter .ode bit would seriously Inferfere.lth nor.a) addres
in the servicing of Such Fault or Inter~upt. Hence, the
automaticallV by any Fault or Program Interrupt.
APPENIlIX A
000 I
Cache~to-Reglster
I
ilDQC tAOL IlOAC IA)tA IAO~Q IAOlACI
IAS)(O IASXl IASX2 IASXJ lASX4 IASX5 IASX£) USX7 lAowPOt4)WP1lAOHPZIAOWPJfAOS tHA IASQ ISSCR.
I AHCQJL.Rf.!i.-L_ _ LA:lA-1C1.lAoouQ.............lAwD.&J;A:u.QL-A,'
REVIEW DRAFT
SUBJECT TO CHANGE
Oc'ob~rt
11375
9-7
Al39
100 :CMPXOrCMPXIJCHPX2ICHPX3ICMPX4JCHPX5ICHPX&ICHPX7'
ICWL
I.
IC~PA ICHPQ
CHPAQI
120 lSBlXO:SBLXllSBLX2ISBLX3ISBLX4ISBlX5:SBLX&ISBLX7J
t
I
I
I
IS3LA ISBLQ SBLAQI
140 ISSXO :SSXl ISSX2 ISSX3 ISSX4 ISSXS ISSX6 ISSX7 JAOWP41ADHP5tADH~6IAOWP71S0BR aSiA
ISSQ
I
160 J.S6XQ Js.aXl ISBR.-1SJlX3 JSB~a.xLisBX6 ISBXl I
lS-tCA I SHC.Q-1.I..PRI t
JS1A.--1SlHl
SBAe J
200 ICNAXOICNAX11CNAX21CNAX31CNAX41CNAXS1CNAxedCNAX71
.IC!oIK
IABSA JEPAQ SSZNC JC~AA JCNAQ CHAAQI
220 JLDXO ILOXl ILOX2 'LOX3 :lOX4 ILOX5 IlOX6 :lOX7 ILSAR IR5W
SLOBR tRHCH ISZN
ILJA
ILDQ
LOAQ J
240 IORSXOIORSX110RSX210RSX3ioRSX410RSXSIORSX&IORSX7ISPBPOIS~RllISPBP2ISPRt3:SPRI tO~SA SORSQ LSDP I
260 .LQ.RXJL1Q.&XLl.QR!Z.-11l&U--lJlBK.!t-12RX2-1Q.1U6 ; ORX7 11SeJL1IiPl I ISPLI ISP3 .1
IQig.A-"JII..IQ","R~.>jQ~...L.lC.JQR~AI:a.lQIiL-.LI
300 :CANXO:CANX1JCANX2ICANX3ICA~X4JCANX5ICANX&ICANX7IEAHPOJEASPOIEAWP2:EASP2J
IClNA JCANQ CANAQ:
320 lLCXO ILCXl ILCX2 IlC)(3 JLCX4 ILC)(S tLCX£) IlCX7 afAHP41EASP41EAWP61EASP61
ILeA
ILCQ
LeAQ I
340 :ANSXOIANSX11A.NSX2IANSX3:ANSX4iANSX5IANSX6:ANSX71E Pe.~ IEPB?lJEPP2 tEPBP31SrAC IAiSA JANSQ SICP I
3&0 J.ANXQ I Ali.U-l..AHXL1ANX3 I AN~Ll.AtiXLIAN X6 I ANX7 1Ee.e.L1E.e.eps I EPP£) I EPae?
I A~la~N~Q___JI.: A;u.N:r. I:A:LliQ........
l
400 I
JHPF
IHPY
J
I
JCHG.
I
,"
- IUjE
I
IRSCR I
lAOE
I
I
I
- 420 J
IUFH
I
10UFH I
IFCHG I
10FCHGIESlN IFLO
I
IOFLO t
SUFA
J
IOUFA I
440 ISXLO ISXL1 ISXl2 ISXL3 ISXl4 :SXL5 I-5XL6 ISXL7 ISTZ ISPlIC tSCPR 1
ISTT
IFSl
ISlE
JOFST· t
460 J.
tE.tfL..'
IOFM? I
...
J
J
IfSJR lEla _DESTR_PFR.O;
IE!Q
J
JDEA • .
500 IRPL I
I
I
I
Jaco 10IV
IOVF
I
I
,
IFNEG I
IFCKP f
10Fe l
520 IRPl
I
J
I
IFOI·.
10tOl I
IN::G
tCAKS INEGL t
IUFS
1
IOUFS I
540 ISPRPOISPRPIJSPRP2JSPRP31SPRP41SPRPSISPRP61SPRP71SBAR ISTBA :STBQ 'SHCH ISTC1 J
I
ISSDP I
560 .LR POI
J
1F 0 V I
IllEtlLL
J
--'---I F NQ f
lES,13.--1 _ _.........
1 D.uF....SuB"--Lo1
600 :TlE
IINZ
ITNC
ITRC
11tH
IIPL
t
ITIF
aR1CO I
I
IRCU IIEO
n::u lOIS tTOV I
620 IEAXO :EAXl lEAX2 IEAX3 IEAX4 IEAX5 lEAX6 lEAX7 .RET
I
I
IRCCL lLOI
IEAA
IEAQ
ILor I
640 IERS)(OIERSX1:ERSX2JERSX3IER5~4JERSXSIERSX&:ERSX7ISPRI4ISPBP5ISPRI61SPBP71STACQ:E~SA lERSQ ISCU J
660 LERXO lERXl-1ERX2 1(R!3 IERX~~lERX6 IERXt-llS~I~P5 ITSP2-IJSPl JLte&-lE~A--l&E~RQ~-uIE~R~A~Q~1
70n lrsxo lrSXl ITSX2 IlSX3 IISX~ ~TSX5 ITSX6 J1SX7 ITRA I
ICALL61
:I5S
IXEC
'XED I
720 ILXLO ILXll ILXL2 ILXL3 fLXL4 lLXL5 JLXL6 ILXL7 I
IA~S
IQRS
ILRS
I
lALS
IQLS
ILLS I
740 ISIXO ISIX1 ISI)(2 ISIX3 15IX4 JSIXS lSIX6 ISTX7 ISlC2 ISTCA lSTCQ .SREG (SrI
ISlA
ISIQ
fSTAQ I
760 J LPRPQ I L.f.8f.11 LPRP 21 LPg? 31 LP&P41 1..e.ru!llLPRP& ILPRP II
J AiL. I aRL
JL&L
IGTB
IA~W.B
J LLR
I
REVIEW DRAFI
SUBJECT TO CHANGE
October, 1975
9-8
Al39
(BIT
OPERATION CODE HAP
60 lCSL
00 I HlR
120 ISCO
f
140 . J
160 JHVT
200 I
220
2!t0 I
260 I
300 lttVN
·320
I"
I
JBTD
DO!t
,:
JJ1VNE
ICHPN •
I
I
360
I
I
!tOO
420
440
460
SOD A9BO
520
S960
540
ARAO
560 ..LAAR Q
600 ITRTN
620 I
640 IARNO
660 I NARO
700 I
I .
I
I
J
34D
720 I
I
I
1
006
0111-1111
,
I
I
L---L....----1----L
I
J
I
I
QQ5
DOl
= 0)
111L_..ll6-'-.lIQu lI.1.1_
J
I
J
I
I
I
I
J
t .
•
I
t
J
I
I
I
ICSR
I:
ISZIL1~z.ILICHeB I
1---L _1_·_ _ _ _ _-..a..1_ _...1_____Ja..-_--4I_ _--'-J·
J HRl
t
I
J
I CHPC I
I
I
I
I
1
J
I
I
,seOR I
:SCH
lS.Ct1R I.
I
a
I
I
1
I
I
I
t
I
J
I
I
J
I
i
I
I
I SPTR I
I
I
I
1
ITer
J IUlLl
I
I
1
J
LPJR I
1--.
t
I
I
IA02D
SBZO f
I
"MP2D IOV20 I
t
I
J
I
,
I
~A03D
SB30 1
I
I~P30 IOV3D I
I
tSDR
I
I
J
I
J
I
I
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J
I
t
JSPBPOIS~Rll SPBP2 SPRI3JSSOR I
J
ILPTP
_&.:OQII,.:IO'---_.a..D.1..---D.AZ_-1U
000 I
020 HiVE
40 I
27
10TB
I
J
012
013
I.
t
J
t
I
'014
t
_I_ _....
1 _ _L_-L
t
I
I
I
IEASpifEAWPi EASP31EAHP31
I
J
IEASPS,EAWP, EASP71EAWP71
I
I
IEPBPOIEPPl
EPBP21EPP3 •
I.
If.fBf..UEf!P5 EpaPg J fPPl . I
I
I
1SPL
I
I
ISAREGI
I
J
IkARfGI
IA60D lA,.BD IABO
I
'S6BD ;S!teD IsaD
I
ILeL
IAWO
ISWD
I
a
I
I
I
J
-1----1-_
I
I
I
I
JARA31ARA4 JARAS IARA6 IARA7 I
I
IAARZ..J.AA.ll-lAAR!t...J.AA.~lAA B6 1 AARl.-L-_L_
ITRTF J
I
aTHOl ITP~l ITTN
I
a
I
I
I
•
I
I
I
I
I
ICAMP
J
I
I
I
I
I ---1_ _...L.'_ _...L.
I
J
I
t t l
11
J
II
I·
I
I
I
I
I
I
I
I
t
a
J
I
I
I
J
SPTP
Ji.-__~1_____-"'"
lARA1
I aA&1
lARA~
J
J
IARNl
I tiA&1
IARNZ JARN3 lARN'+ JARN5 JARN6 rARN7 ISPBP,.IS'RI5ISPBP&ISPRI71
)
I
I NARZ I NQR3 J NARLlN!82-1 HARE? J HARl t
I
~I_ _•.Io1_ _---...I_ _.....I____Ia.-_--I._ _......
I
I
I
I
J
I
I
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I
J
I
I
J
I
f
I
I
J
I
I
I
I
I
I
I
tIl
REVIEW DRAFT
~U8~ECT TO CHANGE
October
1975
9-9
I
---L_
I
.~I_ _........_ _..4t_ _.....
I
7'+0 ISARO JSARl ISAR2 ISAR3 ISAR4 tSARS ISAR6 tSAR7 I
760 lLARO 'L.AR.LJJ...ARZ....1LAR~ ILARLlL..!R.L1LAR6 lLARl I
I
I
I
I
I
I
f
1
J
J
I
J
JSRA
I1.RA
J
I
I
I
I
I
J
J
AL39
APP£NOIX B
ALPHABETIC OPERATtON CODE lIST
This appendIx presents a list of al' Processor instruction operation codes sorted on mnemonic and
giving the octal operation code value, the Instructron name, and the functional cate~ory.
The function category codes are as followSI
FXO
BOOL
fLTG
PREG
PRIV
MISe
EIS
TXFR
Fixed ,?olnt
Boolean Operations
FloatIng Point
Pointer Register
Privileged
Hisce.laneous
Extended 1nstruction Set
Transfer of Control
A4BD
AGBD
A9BD
AARO
ABO
502 (1)
EIS
501 (1)
EIS
500(1)
EIS
SOQ (1)
EtS
EIS
ABSA
AD2D
AD3D
ADA
AOAQ
212 (0)
50-3 (1)
202(1)
PRIV
EtS
222(1)
EIS
075(0)
077 (0)
FXO
FXD
AOE
AOL
AOLA
AOLAQ
-AOLQ
415(0)
FLTG
033(0)
035(0)
03·7« D)
036 (0)
FXD
AOlXn
AOQ
AOWPO
ADWP1
AOWP2
020 (0)
075 (0)
050 (0)
FXD
FXO
OSl(O}
PREG
052(0)
PREG
053(0)
150 (0 )
151(0)
152(0)
PREG
PR.EG
PREG
PREG
lbJ ( 0)
PREG
ADl-iP3
ADHP4
ADWP5
ADWP5
AOHP7
REVIEW DRAFT
TO CHANGE
~UBJECT
bctober, lC375
FXO
FXO
FXO
PREG_
A~d 4-bit Character Disp'acement to AR
Add 6-blt Character Displacement to AR
Add 9-bit Character Displacement to AR
Alphanumeric Descriptor to ARo
Add Bit Displacement to AR
Absolute Address to A-Register
Add Using 2 Decimal Operands
Add Using 3 Decimal Operands
Add to A-R~glster
Add to AQ-~eglster
Add to E-Register
Add Low to AQ-Reglster
Add Logica' to A-Register
Add L~gical to AQ-Register
A~d Logical to Q-Reglster
Add
Add
Add
Add
Add
Logical to Index Q
to Q-Register
to Word Number Field 01 PRO
to Word Number FIeld of PRl
to Word Number Field of PR2
Add
Add
Add
Add
Add
to Word Number
to Word Number
to Word Number
to Word Number
to Word Number
Field
Field
Field
Field
Field
PR3
PR:4
01 PR5
of PR6
of PRl
of
of
AL39
AOXti.
AlR
AlS
ANA
96tH 0)
17S(Ot
735 (OJ
FXD
AJ11
FXO
fXO
BOOL
BOOl
J-~fo)ister
to !ndelC
H
left Rotate
Shllt
A-ReJ~ster Lelt
to A-R~gister
AND
ANO to
ANAQ
375' Ot
311(0)
ANQ
37£)( Q)
ANSA
35510)
3S6( 0)
800l
AND to
AND to
ANO to
3ltn (D)
36nCO)
BOOL
BaaL
AND to Sto~age fro. Index Q
AND to Index Q
05"(0)
54n( 1)
711 t 0 J
64n(1)
131 (0)
FXD
EIS
F'XD
EIS
FXD
Add One to storage
ARo to AI~h3numeric Oescrlptor
A~ReglsterRi~ht Ldgtca' ShIft
ARn to Numeric Descriptor
A-Register Right Shift
ASA
ASQ
055 (0)
FXO
05& (0)
ASXO
AweA
AWCQ
altulO)
071 (0)
072(0)
FXO
FltO
fXD
FXD
AWD
S0711)
505(0)
EIS
BCD
8TD
ANSa
ANSlCQ
ANXn
AOS
ARA!).
ARl
ARNa
A~S
CALL&
CAMP
CAHS
CAHA
CANAQ
CANQ
CAHXn
CIOC
eHG
CHK
CHPA
CHPAQ
CHPB
CHPC
CMPN
CHPQ
CHPX.o
aOOL
BOOL
MISC
301' 1)
713 CO)
532 C1)
EIS
532 (0)
315 (U)
311 CO)
316 (0)
30n( 0)
01S UI'
40$ COJ
211 (0)
liSt in
111 (0)
066(1)
101) (1)
303(1)
11& (0)
10n( 0)
AQ-Reglste~
Q-Reglste~
Sto~age from
A-Register
Sfo~age fro~ Q-R~gl~te~
Add
Add
Add
Add
Stored to A-Register
Stored to Q·Reglster
Stored to lri~eK n
With Carr, to A-Register
Add Wl th Carry to Q-Re.gls fer
Add Word DisplaceMent to
Binarv-to-BCD
At
TXFR
Binarv-to-Oecl •• ' .
Call
PRIV
Clear Assoclatlve
PRJ: V
C'e~ Associ.ttve Memory Se,lIents
Co.paratl~e AND ~lth A-Register
COMparative AND III1,th ~~R.glster
Co.paratlv. AND wI th Q"'R.~ist.r
BOOl
·BOOL
BOOL
BOOL
Hemory
CO·ilParatlve AND Mlth t",de. D
PRlv
connec;t
FXO
FXD
FXO
COMpare "agnlt~d.
COllpare !'tasked
Co",t)8r~ 'If ith A-Register
Compare "lth AQ-~.91st~r
FXD
EIS
EIS
EIS
FXO
F'XO
Pages
Compar~
Compare
Compare
Compare
Compare
Bit Strings
Alphano •• rlc Character Strings
NUlleric
w:i ttl
with
Q-Reglster
Index n
NOt III1th A~Re91$ter
Not wIth AQ-Register
215« 0)
BOOl
CNAQ
217 (0 J
216' 0)
BOOl
BOOL
CNAXo
2DntO)
800l
CSl
060 (1)
EIS
CSR
C.Wl
DI)Ut1)
111(0)
EIS
F)(O
OFAD
'+17(0)
FLTG
Combin& Blt Strln~$ Right
Co~pare With Limits
OoubltPrec:lsion f:loatlng Add
OFCHG
DFCHP
421(0)>
511eO)
FlTG
FlTG
Double P~e.els!on Floating Compare
Double PrecIsion floating Compare
OFOt
OfDV
OFlD
DfHP
OFRD
521' 0)
4&3(U
FLTG
FLTG
FlTG
FLTG
'+73(0)
FLTG
Double
DOUble
Double
Double
Ooub'e
CNAA
CNAAQ
5&7 (0)
433 CO)
ComparatIve
Comparatlve
Comparative
Comparative
Q-Reglste,.
NOT .lth Ind.~ n
Combine Sit Strings left
NOr wIth
Precision
Precision
Precision
precision
PrecIsion
1'1 a g." 1 tude
Floating Divide In\le,..ted
Floating Divide
F"loatlng Load
FloatIng Mu It ipl y
Floating ~ound
REVIEW ORAfT
SUBJECT TO CHANGE
October t 1975
Ai.,39
DFSB
OFST
OFSTR
DIS
DIV
577( 0)
457(0)
'+72(0)
61& (0)
50&(0)
FLTG
FLTG
FLTG
PRIV
FlTG
Double PrecIsion Floating Subtract
DoubJe Precision Floating Store
Double Precision Floating Store Rounded
Delav Until Interrupt Signal
Divide Integer
ORL
DT8
OUFA
OUFM
DUFS
002' D)
rousc
305 (1)
437(0)
ItZJ «0)
537(0)
EIS
FlTG
FlTG
FLTG
Dera 11
Declmal-to-BInary Convert
Double Precision Unnormalized Floating Add
Double Precision unnormalized Floating Multiply
Double Precision Unn~rmal ized Floating Subtract
DV20
DV30
OVF
EAA
EAQ
l07( U
EIS
227(1)
507(0)
E3S (0)
63&« 0)
EIS
FXO
FXO
FXO
Divide Using 2 Decimal Operands
DIvide Using 3 Decimal operands
DivIde Fraction
Effective Address to A-Register
Effective Address to Q-Register
311 ( 0)
310(t)
Effective
Effective
Effective
Effective
Effective
Effective Address to Segment Numbe~ Field of PR5
E1fectLve 4jdress to Segment Numbe- Fie'
EASPD
EASP1
EASP2
EASPJ
EASP4
313 (0)
3."51' 0)
PREG
PREG
PREG
PREG
PREG
EASP5
EASP6
J30( U
3.33(0)
PREG
PREG
~12« 1)
B-3
Address
Address
Address
Address
Address
to
to
to
to
to
Segment
Segment
Segment
Segment
Segment
Numbe~
Numbe~
Numbe~
Numbe~
Numbe~
Field
Field
Field
Field
Field
of PRO
of pR1
of PR2
of PR3
of PR4
The Other Computer Company:
Hone)'"'ell
HONEYWELL INFORMATION SYSTEMS
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