QRC0001_UALside1 ARM Instruction Set Quick Ref QRC0001_UAL QRC0001 UAL 2007_ARM_instructions_set instructions pdf -FilePursuit
User Manual: ARM Instruction Set Quick Ref - QRC0001_UAL
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ARM® and Thumb®-2 Instruction Set
Quick Reference Card
Key to Tables
Rm {, }
C*, V*
See Table Register, optionally shifted by constant
See Table Flexible Operand 2. Shift and rotate are only available as part of Operand2.
See Table PSR fields.
Either CPSR (Current Processor Status Register) or SPSR (Saved Processor Status Register)
Flag is unpredictable in Architecture v4 and earlier, unchanged in Architecture v5 and later.
Can be Rs or an immediate shift value. The values allowed for each shift type are the same as those
shown in Table Register, optionally shifted by constant.
x,y
B meaning half-register [15:0], or T meaning [31:16].
ARM: a 32-bit constant, formed by right-rotating an 8-bit value by an even number of bits.
Thumb: a 32-bit constant, formed by left-shifting an 8-bit value by any number of bits, or a bit
pattern of one of the forms 0xXYXYXYXY, 0x00XY00XY or 0xXY00XY00.
See Table Prefixes for Parallel instructions
{IA|IB|DA|DB} Increment After, Increment Before, Decrement After, or Decrement Before.
IB and DA are not available in Thumb state. If omitted, defaults to IA.
B, SB, H, or SH, meaning Byte, Signed Byte, Halfword, and Signed Halfword respectively.
SB and SH are not available in STR instructions.
Operation
Add
§
6
6
6
Assembler
ADD{S} Rd, Rn,
ADC{S} Rd, Rn,
ADD Rd, Rn, #
Q{D}ADD Rd, Rm, Rn
ADR Rd,
SUB{S} Rd, Rn,
SBC{S} Rd, Rn,
SUB Rd, Rn, #
RSB{S} Rd, Rn,
RSC{S} Rd, Rn,
Q{D}SUB Rd, Rm, Rn
SUBS PC, LR, #
ADD16 Rd, Rn, Rm
SUB16 Rd, Rn, Rm
ADD8 Rd, Rn, Rm
Byte-wise subtraction
6
SUB8 Rd, Rn, Rm
Halfword-wise exchange, add, subtract
Halfword-wise exchange, subtract, add
Unsigned sum of absolute differences
6
6
6
ASX Rd, Rn, Rm
SAX Rd, Rn, Rm
USAD8 Rd, Rm, Rs
6
USADA8 Rd, Rm, Rs, Rn
Signed saturate word, right shift
Signed saturate word, left shift
Signed saturate two halfwords
6
6
6
SSAT Rd, #, Rm{, ASR }
SSAT Rd, #, Rm{, LSL }
SSAT16 Rd, #, Rm
Unsigned saturate word, right shift
Unsigned saturate word, left shift
Unsigned saturate two halfwords
6
6
6
USAT Rd, #, Rm{, ASR }
USAT Rd, #, Rm{, LSL }
USAT16 Rd, #, Rm
Add
with carry
wide
saturating {doubled}
Address
Form PC-relative address
Subtract
Subtract
with carry
wide
reverse subtract
reverse subtract with carry
saturating {doubled}
Exception return without stack
Parallel
Halfword-wise addition
arithmetic Halfword-wise subtraction
Byte-wise addition
and accumulate
Saturate
T2
5E
T2
5E
+/§
SPm
{X}
{!}
{S}
{T}
{R}
A comma-separated list of registers, enclosed in braces { and }.
As , must not include the PC.
As , including the PC.
+ or –. (+ may be omitted.)
See Table ARM architecture versions.
Interrupt flags. One or more of a, i, f (abort, interrupt, fast interrupt).
See Table Processor Modes
SP for the processor mode specified by
Least significant bit of bitfield.
Width of bitfield. + must be <= 32.
RsX is Rs rotated 16 bits if X present. Otherwise, RsX is Rs.
Updates base register after data transfer if ! present (pre-indexed).
Updates condition flags if S present.
User mode privilege if T present.
Rounds result to nearest if R present, otherwise truncates result.
S updates Action
Notes
N Z C V Rd := Rn + Operand2
N
N Z C V Rd := Rn + Operand2 + Carry
N
Rd := Rn + imm12, imm12 range 0-4095
T, P
Rd := SAT(Rm + Rn)
doubled: Rd := SAT(Rm + SAT(Rn * 2))
Q
Rd := , for range from current instruction see Note L
N, L
N Z C V Rd := Rn – Operand2
N
N Z C V Rd := Rn – Operand2 – NOT(Carry)
N
N Z C V Rd := Rn – imm12, imm12 range 0-4095
T, P
N Z C V Rd := Operand2 – Rn
N
N Z C V Rd := Operand2 – Rn – NOT(Carry)
A
Rd := SAT(Rm – Rn)
doubled: Rd := SAT(Rm – SAT(Rn * 2))
Q
PC = LR – imm8, CPSR = SPSR(current mode), imm8 range 0-255.
T
Rd[31:16] := Rn[31:16] + Rm[31:16], Rd[15:0] := Rn[15:0] + Rm[15:0]
G
Rd[31:16] := Rn[31:16] – Rm[31:16], Rd[15:0] := Rn[15:0] – Rm[15:0]
G
Rd[31:24] := Rn[31:24] + Rm[31:24], Rd[23:16] := Rn[23:16] + Rm[23:16],
G
Rd[15:8] := Rn[15:8] + Rm[15:8], Rd[7:0] := Rn[7:0] + Rm[7:0]
Rd[31:24] := Rn[31:24] – Rm[31:24], Rd[23:16] := Rn[23:16] – Rm[23:16],
G
Rd[15:8] := Rn[15:8] – Rm[15:8], Rd[7:0] := Rn[7:0] – Rm[7:0]
Rd[31:16] := Rn[31:16] + Rm[15:0], Rd[15:0] := Rn[15:0] – Rm[31:16]
G
Rd[31:16] := Rn[31:16] – Rm[15:0], Rd[15:0] := Rn[15:0] + Rm[31:16]
G
Rd := Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])
+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])
Rd := Rn + Abs(Rm[31:24] – Rs[31:24]) + Abs(Rm[23:16] – Rs[23:16])
+ Abs(Rm[15:8] – Rs[15:8]) + Abs(Rm[7:0] – Rs[7:0])
Rd := SignedSat((Rm ASR sh), sat). range 1-32, range 1-31.
Q, R
Q
Rd := SignedSat((Rm LSL sh), sat). range 1-32, range 0-31.
Rd[31:16] := SignedSat(Rm[31:16], sat),
Q
Rd[15:0] := SignedSat(Rm[15:0], sat). range 1-16.
Rd := UnsignedSat((Rm ASR sh), sat). range 0-31, range 1-31.
Q, R
Rd := UnsignedSat((Rm LSL sh), sat). range 0-31, range 0-31.
Q
Rd[31:16] := UnsignedSat(Rm[31:16], sat),
Q
Rd[15:0] := UnsignedSat(Rm[15:0], sat). range 0-15.
ARM and Thumb-2 Instruction Set
Quick Reference Card
Operation
Multiply
Multiply
and accumulate
and subtract
unsigned long
unsigned accumulate long
unsigned double accumulate long
Signed multiply long
and accumulate long
16 * 16 bit
32 * 16 bit
16 * 16 bit and accumulate
32 * 16 bit and accumulate
16 * 16 bit and accumulate long
Dual signed multiply, add
and accumulate
and accumulate long
Dual signed multiply, subtract
and accumulate
and accumulate long
Signed top word multiply
and accumulate
and subtract
with internal 40-bit accumulate
packed halfword
halfword
Divide
Signed or Unsigned
Move
Move
data
NOT
top
wide
40-bit accumulator to register
register to 40-bit accumulator
Shift
Arithmetic shift right
Logical shift left
Logical shift right
Rotate right
Rotate right with extend
Count leading zeros
Compare Compare
negative
Logical
Test
Test equivalence
AND
EOR
ORR
ORN
Bit Clear
§
T2
6
5E
5E
5E
5E
5E
6
6
6
6
6
6
6
6
6
XS
XS
XS
RM
T2
T2
XS
XS
5
T2
Assembler
S updates
Action
Notes
MUL{S} Rd, Rm, Rs
N Z C*
Rd := (Rm * Rs)[31:0]
(If Rm is Rd, S can be used in Thumb-2)
N, S
MLA{S} Rd, Rm, Rs, Rn
N Z C*
Rd := (Rn + (Rm * Rs))[31:0]
S
MLS Rd, Rm, Rs, Rn
Rd := (Rn – (Rm * Rs))[31:0]
UMULL{S} RdLo, RdHi, Rm, Rs
N Z C* V* RdHi,RdLo := unsigned(Rm * Rs)
S
UMLAL{S} RdLo, RdHi, Rm, Rs
N Z C* V* RdHi,RdLo := unsigned(RdHi,RdLo + Rm * Rs)
S
UMAAL RdLo, RdHi, Rm, Rs
RdHi,RdLo := unsigned(RdHi + RdLo + Rm * Rs)
SMULL{S} RdLo, RdHi, Rm, Rs
N Z C* V* RdHi,RdLo := signed(Rm * Rs)
S
SMLAL{S} RdLo, RdHi, Rm, Rs
N Z C* V* RdHi,RdLo := signed(RdHi,RdLo + Rm * Rs)
S
SMULxy Rd, Rm, Rs
Rd := Rm[x] * Rs[y]
SMULWy Rd, Rm, Rs
Rd := (Rm * Rs[y])[47:16]
SMLAxy Rd, Rm, Rs, Rn
Rd := Rn + Rm[x] * Rs[y]
Q
SMLAWy Rd, Rm, Rs, Rn
Rd := Rn + (Rm * Rs[y])[47:16]
Q
SMLALxy RdLo, RdHi, Rm, Rs
RdHi,RdLo := RdHi,RdLo + Rm[x] * Rs[y]
SMUAD{X} Rd, Rm, Rs
Rd := Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]
Q
SMLAD{X} Rd, Rm, Rs, Rn
Rd := Rn + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]
Q
SMLALD{X} RdLo, RdHi, Rm, Rs
RdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] + Rm[31:16] * RsX[31:16]
SMUSD{X} Rd, Rm, Rs
Rd := Rm[15:0] * RsX[15:0] – Rm[31:16] * RsX[31:16]
Q
SMLSD{X} Rd, Rm, Rs, Rn
Rd := Rn + Rm[15:0] * RsX[15:0] – Rm[31:16] * RsX[31:16]
Q
SMLSLD{X} RdLo, RdHi, Rm, Rs
RdHi,RdLo := RdHi,RdLo + Rm[15:0] * RsX[15:0] – Rm[31:16] * RsX[31:16]
SMMUL{R} Rd, Rm, Rs
Rd := (Rm * Rs)[63:32]
SMMLA{R} Rd, Rm, Rs, Rn
Rd := Rn + (Rm * Rs)[63:32]
SMMLS{R} Rd, Rm, Rs, Rn
Rd := Rn – (Rm * Rs)[63:32]
MIA Ac, Rm, Rs
Ac := Ac + Rm * Rs
MIAPH Ac, Rm, Rs
Ac := Ac + Rm[15:0] * Rs[15:0] + Rm[31:16] * Rs[31:16]
MIAxy Ac, Rm, Rs
Ac := Ac + Rm[x] * Rs[y]
Rd, Rn, Rm
Rd := Rn / Rm
is SDIV (signed) or UDIV (unsigned)
MOV{S} Rd,
N Z C
Rd := Operand2
See also Shift instructions
N
MVN{S} Rd,
N Z C
Rd := 0xFFFFFFFF EOR Operand2
N
MOVT Rd, #
Rd[31:16] := imm16, Rd[15:0] unaffected, imm16 range 0-65535
MOV Rd, #
Rd[15:0] := imm16, Rd[31:16] = 0, imm16 range 0-65535
MRA RdLo, RdHi, Ac
RdLo := Ac[31:0], RdHi := Ac[39:32]
MAR Ac, RdLo, RdHi
Ac[31:0] := RdLo, Ac[39:32] := RdHi
ASR{S} Rd, Rm,
N Z C
Rd := ASR(Rm, Rs|sh)
Same as MOV{S} Rd, Rm, ASR
N
LSL{S} Rd, Rm,
N Z C
Rd := LSL(Rm, Rs|sh)
Same as MOV{S} Rd, Rm, LSL
N
LSR{S} Rd, Rm,
N Z C
Rd := LSR(Rm, Rs|sh)
Same as MOV{S} Rd, Rm, LSR
N
ROR{S} Rd, Rm,
N Z C
Rd := ROR(Rm, Rs|sh)
Same as MOV{S} Rd, Rm, ROR
N
RRX{S} Rd, Rm
N Z C
Rd := RRX(Rm)
Same as MOV{S} Rd, Rm, RRX
CLZ Rd, Rm
Rd := number of leading zeros in Rm
CMP Rn,
N Z C V Update CPSR flags on Rn – Operand2
N
CMN Rn,
N Z C V Update CPSR flags on Rn + Operand2
N
TST Rn,
N Z C
Update CPSR flags on Rn AND Operand2
N
TEQ Rn,
N Z C
Update CPSR flags on Rn EOR Operand2
AND{S} Rd, Rn,
N Z C
Rd := Rn AND Operand2
N
EOR{S} Rd, Rn,
N Z C
Rd := Rn EOR Operand2
N
ORR{S} Rd, Rn,
N Z C
Rd := Rn OR Operand2
N
ORN{S} Rd, Rn,
N Z C
Rd := Rn OR NOT Operand2
T
BIC{S} Rd, Rn,
N Z C
Rd := Rn AND NOT Operand2
N
ARM and Thumb-2 Instruction Set
Quick Reference Card
Operation
Bit field
§
T2
T2
T2
T2
6
6
6
6
Assembler
BFC Rd, #, #
BFI Rd, Rn, #, #
SBFX Rd, Rn, #, #
UBFX Rd, Rn, #, #
PKHBT Rd, Rn, Rm{, LSL #}
PKHTB Rd, Rn, Rm{, ASR #}
SXTH Rd, Rm{, ROR #}
SXTB16 Rd, Rm{, ROR #}
Action
Rd[(width+lsb–1):lsb] := 0, other bits of Rd unaffected
Rd[(width+lsb–1):lsb] := Rn[(width-1):0], other bits of Rd unaffected
Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( Rn[width+lsb–1] )
Rd[(width–1):0] = Rn[(width+lsb–1):lsb], Rd[31:width] = Replicate( 0 )
Rd[15:0] := Rn[15:0], Rd[31:16] := (Rm LSL sh)[31:16]. sh 0-31.
Rd[31:16] := Rn[31:16], Rd[15:0] := (Rm ASR sh)[15:0]. sh 1-32.
Rd[31:0] := SignExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.
Rd[31:16] := SignExtend((Rm ROR (8 * sh))[23:16]),
Rd[15:0] := SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
SXTB Rd, Rm{, ROR #}
Rd[31:0] := SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
UXTH Rd, Rm{, ROR #}
Rd[31:0] := ZeroExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.
UXTB16 Rd, Rm{, ROR #}
Rd[31:16] := ZeroExtend((Rm ROR (8 * sh))[23:16]),
Rd[15:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
UXTB Rd, Rm{, ROR #}
Rd[31:0] := ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
SXTAH Rd, Rn, Rm{, ROR #}
Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.
SXTAB16 Rd, Rn, Rm{, ROR #} Rd[31:16] := Rn[31:16] + SignExtend((Rm ROR (8 * sh))[23:16]),
Rd[15:0] := Rn[15:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
SXTAB Rd, Rn, Rm{, ROR #}
Rd[31:0] := Rn[31:0] + SignExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
UXTAH Rd, Rn, Rm{, ROR #}
Rd[31:0] := Rn[31:0] + ZeroExtend((Rm ROR (8 * sh))[15:0]). sh 0-3.
UXTAB16 Rd, Rn, Rm{, ROR #} Rd[31:16] := Rn[31:16] + ZeroExtend((Rm ROR (8 * sh))[23:16]),
Rd[15:0] := Rn[15:0] + ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
UXTAB Rd, Rn, Rm{, ROR #}
Rd[31:0] := Rn[31:0] + ZeroExtend((Rm ROR (8 * sh))[7:0]). sh 0-3.
RBIT Rd, Rm
For (i = 0; i < 32; i++) : Rd[i] = Rm[31– i]
REV Rd, Rm
Rd[31:24] := Rm[7:0], Rd[23:16] := Rm[15:8], Rd[15:8] := Rm[23:16], Rd[7:0] := Rm[31:24]
REV16 Rd, Rm
Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:24] := Rm[23:16], Rd[23:16] := Rm[31:24]
REVSH Rd, Rm
Rd[15:8] := Rm[7:0], Rd[7:0] := Rm[15:8], Rd[31:16] := Rm[7] * &FFFF
Signed
extend
Bit Field Clear
Bit Field Insert
Signed Bit Field Extract
Unsigned Bit Field Extract
Pack halfword bottom + top
Pack halfword top + bottom
Halfword to word
Two bytes to halfwords
Unsigned
extend
Byte to word
Halfword to word
Two bytes to halfwords
6
6
6
Byte to word
Halfword to word, add
Two bytes to halfwords, add
6
6
6
Byte to word, add
Halfword to word, add
Two bytes to halfwords, add
6
6
6
6
T2
6
6
6
Select
Byte to word, add
Bits in word
Bytes in word
Bytes in both halfwords
Bytes in low halfword,
sign extend
Select bytes
If-Then
If-Then
T2
IT{pattern} {cond}
Branch
Branch
with link
and exchange
with link and exchange (1)
4T
5T
B
BL
BX Rm
BLX
Pack
Signed
extend
with add
Unsigned
extend
with add
Reverse
with link and exchange (2)
and change to Jazelle state
Compare, branch if (non) zero
Table Branch Byte
Table Branch Halfword
Move to or PSR to register
from PSR register to PSR
immediate to PSR
Processor Change processor state
state
change
Change processor mode
Set endianness
6
5
5J
T2
T2
T2
6
6
6
6
SEL Rd, Rn, Rm
BLX Rm
BXJ Rm
CB{N}Z Rn,
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
MRS Rd,
MSR _, Rm
MSR _, #
CPSID {, #}
CPSIE {, #}
CPS #
SETEND
Notes
N
N
N
N
N
N
N
Rd[7:0] := Rn[7:0] if GE[0] = 1, else Rd[7:0] := Rm[7:0]
Bits[15:8], [23:16], [31:24] selected similarly by GE[1], GE[2], GE[3]
TU
Makes up to four following instructions conditional, according to pattern. pattern is a string of up to three
letters. Each letter can be T (Then) or E (Else).
The first instruction after IT has condition cond. The following instructions have condition cond if the
corresponding letter is T, or the inverse of cond if the corresponding letter is E.
See Table Condition Field for available condition codes.
PC := label. label is this instruction ±32MB (T2: ±16MB, T: –252 - +256B)
N, B
LR := address of next instruction, PC := label. label is this instruction ±32MB (T2: ±16MB).
PC := Rm. Target is Thumb if Rm[0] is 1, ARM if Rm[0] is 0.
N
LR := address of next instruction, PC := label, Change instruction set.
C
label is this instruction ±32MB (T2: ±16MB).
LR := address of next instruction, PC := Rm[31:1]. Change to Thumb if Rm[0] is 1, to ARM if Rm[0] is 0.
N
Change to Jazelle state if available
If Rn {== or !=} 0 then PC := label. label is (this instruction + 4-130).
NTU
PC = PC + ZeroExtend( Memory( Rn + Rm, 1) << 1). Branch range 4-512. Rn can be PC.
TU
PC = PC + ZeroExtend( Memory( Rn + Rm << 1, 2) << 1). Branch range 4-131072. Rn can be PC.
TU
Rd := PSR
PSR := Rm (selected bytes only)
PSR := immed_8r (selected bytes only)
Disable specified interrupts, optional change mode.
U, N
Enable specified interrupts, optional change mode.
U, N
U
Sets endianness for loads and saves. can be BE (Big Endian) or LE (Little Endian).
U, N
ARM Instruction Set
Quick Reference Card
Single data item loads and stores
Load
Immediate offset
or store
Post-indexed, immediate
word, byte
Register offset
or halfword
Post-indexed, register
PC-relative
Load or store Immediate offset
doubleword
Post-indexed, immediate
Register offset
Post-indexed, register
PC-relative
§
Preload data or instruction
Immediate offset
Register offset
PC-relative
§ (PLD)
5E
5E
5E
5E
5E
5E
5E
5E
Other memory operations
Load multiple
Block data load
return (and exchange)
and restore CPSR
User mode registers
Pop
Load
Semaphore operation
exclusive
Halfword or Byte
Doubleword
Store multiple
Push
Store
exclusive
Push, or Block data store
User mode registers
Semaphore operation
Halfword or Byte
Doubleword
Clear exclusive
Assembler
{size}{T} Rd, [Rn {, #}]{!}
{size}{T} Rd, [Rn], #
{size} Rd, [Rn, +/-Rm {, }]{!}
{size}{T} Rd, [Rn], +/-Rm {, }
{size} Rd,
D Rd1, Rd2, [Rn {, #}]{!}
D Rd1, Rd2, [Rn], #
D Rd1, Rd2, [Rn, +/-Rm {, }]{!}
D Rd1, Rd2, [Rn], +/-Rm {, }
D Rd1, Rd2,
§
6
§ (PLI)
7
7
7
Assembler
[Rn {, #}]
[Rn, +/-Rm {, }]
Assembler
LDM{IA|IB|DA|DB}
LDM{IA|IB|DA|DB}
LDM{IA|IB|DA|DB}
LDM{IA|IB|DA|DB}
POP
LDREX Rd, [Rn]
Rn{!},
Rn{!},
Rn{!}, ^
Rn, ^
6K LDREX{H|B} Rd, [Rn]
6K LDREXD Rd1, Rd2, [Rn]
STM{IA|IB|DA|DB} Rn{!},
STM{IA|IB|DA|DB} Rn{!}, ^
PUSH
6 STREX Rd, Rm, [Rn]
6K STREX{H|B} Rd, Rm, [Rn]
6K STREXD Rd, Rm1, Rm2, [Rn]
6K CLREX
Notes: availability and range of options for Load, Store, and Preload operations
Note ARM Word, B, D
ARM SB, H, SH
ARM T, BT
1
offset: – 4095 to +4095
offset: –255 to +255
Not available
2
offset: – 4095 to +4095
offset: –255 to +255
offset: – 4095 to +4095
3
Full range of {, }
{, } not allowed Not available
4
Full range of {, }
{, } not allowed Full range of {, }
5
label within +/– 4092 of current instruction Not available
Not available
6
offset: –255 to +255
7
{, } not allowed
8
label within +/– 252 of current instruction 9
Rd1 even, and not r14, Rd2 == Rd1 + 1.
-
Action if is LDR
Rd := [address, size]
Rd := [address, size]
Rd := [address, size]
Rd := [address, size]
Rd := [label, size]
Rd1 := [address], Rd2 := [address + 4]
Rd1 := [address], Rd2 := [address + 4]
Rd1 := [address], Rd2 := [address + 4]
Rd1 := [address], Rd2 := [address + 4]
Rd1 := [label], Rd2 := [label + 4]
Action if is STR
[address, size] := Rd
[address, size] := Rd
[address, size] := Rd
[address, size] := Rd
Not available
[address] := Rd1, [address + 4] := Rd2
[address] := Rd1, [address + 4] := Rd2
[address] := Rd1, [address + 4] := Rd2
[address] := Rd1, [address + 4] := Rd2
Not available
Notes
1, N
2
3, N
4
5, N
6, 9
6, 9
7, 9
7, 9
8, 9
Action if is PLD
Preload [address, 32] (data)
Preload [address, 32] (data)
Preload [label, 32] (data)
Action if is PLI
Preload [address, 32] (instruction)
Preload [address, 32] (instruction)
Preload [label, 32] (instruction)
Notes
1, C
3, C
5, C
Action
Load list of registers from [Rn]
Load registers, PC := [address][31:1] (§ 5T: Change to Thumb if [address][0] is 1)
Load registers, branch (§ 5T: and exchange), CPSR := SPSR. Exception modes only.
Load list of User mode registers from [Rn]. Privileged modes only.
Canonical form of LDM SP!,
Rd := [Rn], tag address as exclusive access. Outstanding tag set if not shared address.
Rd, Rn not PC.
Rd[15:0] := [Rn] or Rd[7:0] := [Rn], tag address as exclusive access.
Outstanding tag set if not shared address. Rd, Rn not PC.
Rd1 := [Rn], Rd2 := [Rn+4], tag addresses as exclusive access
Outstanding tags set if not shared addresses. Rd1, Rd2, Rn not PC.
Store list of registers to [Rn]
Store list of User mode registers to [Rn]. Privileged modes only.
Canonical form of STMDB SP!,
If allowed, [Rn] := Rm, clear exclusive tag, Rd := 0. Else Rd := 1. Rd, Rm, Rn not PC.
If allowed, [Rn] := Rm[15:0] or [Rn] := Rm[7:0], clear exclusive tag, Rd := 0. Else Rd := 1
Rd, Rm, Rn not PC.
If allowed, [Rn] := Rm1, [Rn+4] := Rm2, clear exclusive tags, Rd := 0. Else Rd := 1
Rd, Rm1, Rm2, Rn not PC.
Clear local processor exclusive tag
Thumb-2 Word, B, SB, H, SH, D
offset: –255 to +255 if writeback, –255 to +4095 otherwise
offset: –255 to +255
restricted to LSL #, range 0 to 3
Not available
label within +/– 4092 of current instruction
offset: –1020 to +1020, must be multiple of 4.
Not available
Not available
Rd1 != PC, Rd2 != PC
Notes
N, I
I
I
I
N
9
N, I
I
N
9
C
Thumb-2 T, BT, SBT, HT, SHT
offset: 0 to +255, writeback not allowed
Not available
Not available
Not available
Not available
-
ARM Instruction Set
Quick Reference Card
Coprocessor operations
Assembler
Action
Data operations
CDP{2} , , CRd, CRn, CRm{, }
Coprocessor defined
C2
Move to ARM register from coprocessor
MRC{2} , , Rd, CRn, CRm{, }
Coprocessor defined
C2
MRRC , , Rd, Rn, CRm
Coprocessor defined
MRRC2 , , Rd, Rn, CRm
Coprocessor defined
C
MCR{2} , , Rd, CRn, CRm{, }
Coprocessor defined
C2
MCRR , , Rd, Rn, CRm
Coprocessor defined
Two ARM register move
Alternative two ARM register move
§
5E
6
Move to coproc from ARM reg
Two ARM register move
Alternative two ARM register move
5E
6
MCRR2 , , Rd, Rn, CRm
Loads and stores, pre-indexed
{2} , CRd, [Rn, #+/-]{!}
op: LDC or STC. offset: multiple of 4 in range 0 to 1020.
Loads and stores, zero offset
{2} , CRd, [Rn] {, 8-bit copro. option} op: LDC or STC.
Loads and stores, post-indexed
{2} , CRd, [Rn], #+/-
Miscellaneous operations
Assembler
Action
Swap word
SWP Rd, Rm, [Rn]
temp := [Rn], [Rn] := Rm, Rd := temp.
Swap byte
SWPB Rd, Rm, [Rn]
temp := ZeroExtend([Rn][7:0]), [Rn][7:0] := Rm[7:0], Rd := temp
SRS{IA|IB|DA|DB} SP{!}, #
[SPm] := LR, [SPm + 4] := CPSR
Store return state
§
op: LDC or STC. offset: multiple of 4 in range 0 to 1020.
6
Notes
Coprocessor defined
C
Coprocessor defined
C2
Coprocessor defined
C2
Coprocessor defined
C2
Notes
D
D
C, I
Return from exception
6
RFE{IA|IB|DA|DB} Rn{!}
PC := [Rn], CPSR := [Rn + 4]
C, I
Breakpoint
5
BKPT
Prefetch abort or enter debug state. 16-bit bitfield encoded in instruction.
C, N
Secure Monitor Call
Z
SMC
Secure Monitor Call exception. 16-bit bitfield encoded in instruction. Formerly SMI.
Supervisor Call
No operation
Hints
6
SVC
Supervisor Call exception. 24-bit bitfield encoded in instruction. Formerly SWI.
N
NOP
None, might not even consume any time.
N
Debug Hint
7
DBG
Provide hint to debug and related systems.
Data Memory Barrier
7
DMB
Ensure the order of observation of memory accesses.
Data Synchronization Barrier
7
DSB
Ensure the completion of memory accesses,
C
Instruction Synchronization Barrier
7
ISB
Flush processor pipeline and branch prediction logic.
C
C
Set event
T2 SEV
Signal event in multiprocessor system. NOP if not implemented.
N
Wait for event
T2 WFE
Wait for event, IRQ, FIQ, Imprecise abort, or Debug entry request. NOP if not implemented.
N
Wait for interrupt
T2 WFI
Wait for IRQ, FIQ, Imprecise abort, or Debug entry request. NOP if not implemented.
N
Yield
T2 YIELD
Yield control to alternative thread. NOP if not implemented.
N
Notes
A
Not available in Thumb state.
B
Can be conditional in Thumb state without having to be in an IT block.
N
Some or all forms of this instruction are 16-bit (Narrow) instructions in Thumb-2 code. For details
see the Thumb 16-bit Instruction Set (UAL) Quick Reference Card.
P
Rn can be the PC in Thumb state in this instruction.
C
Condition codes are not allowed in ARM state.
C2
The optional 2 is available from ARMv5. It provides an alternative operation. Condition codes are not Q
allowed for the alternative form in ARM state.
Sets the Q flag if saturation (addition or substraction) or overflow (multiplication) occurs. Read and
reset the Q flag using MRS and MSR.
D
Deprecated. Use LDREX and STREX instead.
R
range is 1-32 in the ARM instruction.
G
Updates the four GE flags in the CPSR based on the results of the individual operations.
S
The S modifier is not available in the Thumb-2 instruction.
I
IA is the default, and is normally omitted.
T
Not available in ARM state.
L
ARM: . 16-bit Thumb: multiple of 4 in range 0-1020. 32-bit Thumb: 0-4095.
U
Not allowed in an IT block. Condition codes not allowed in either ARM or Thumb state.
ARM Instruction Set
Quick Reference Card
ARM architecture versions
Condition Field
Mnemonic
Description
Description (VFP)
n
ARM architecture version n and above
nT, nJ
T or J variants of ARM architecture version n and above
5E
ARM v5E, and 6 and above
T2
All Thumb-2 versions of ARM v6 and above
CS / HS
Carry Set / Unsigned higher or same
Greater than or equal, or unordered
6K
ARMv6K and above for ARM instructions, ARMv7 for Thumb
CC / LO
Carry Clear / Unsigned lower
Less than
Z
All Security extension versions of ARMv6 and above
MI
Negative
Less than
RM
ARMv7-R and ARMv7-M only
PL
Positive or zero
Greater than or equal, or unordered
XS
XScale coprocessor instruction
VS
Overflow
Unordered (at least one NaN operand)
VC
No overflow
Not unordered
HI
Unsigned higher
Greater than, or unordered
Flexible Operand 2
EQ
Equal
Equal
NE
Not equal
Not equal, or unordered
Immediate value
#
LS
Unsigned lower or same
Less than or equal
Register, optionally shifted by constant (see below)
Rm {, }
GE
Signed greater than or equal
Greater than or equal
Register, logical shift left by register
Rm, LSL Rs
LT
Signed less than
Less than, or unordered
Register, logical shift right by register
Rm, LSR Rs
GT
Signed greater than
Greater than
Register, arithmetic shift right by register
Rm, ASR Rs
LE
Signed less than or equal
Less than or equal, or unordered
Register, rotate right by register
Rm, ROR Rs
AL
Always (normally omitted)
Always (normally omitted)
Register, optionally shifted by constant
(No shift)
Rm
Same as Rm, LSL #0
Logical shift left
Rm, LSL #
Allowed shifts 0-31
Logical shift right
Rm, LSR #
Allowed shifts 1-32
Arithmetic shift right
Rm, ASR #
Allowed shifts 1-32
Rotate right
Rm, ROR #
Allowed shifts 1-31
Processor Modes
Rotate right with extend Rm, RRX
PSR fields
Suffix
All ARM instructions (except those with Note C or Note U) can have any one of these condition codes after the
instruction mnemonic (that is, before the first space in the instruction as shown on this card). This condition is
encoded in the instruction.
All Thumb-2 instructions (except those with Note U) can have any one of these condition codes after the
instruction mnemonic. This condition is encoded in a preceding IT instruction (except in the case of
conditional Branch instructions). Condition codes in instructions must match those in the preceding IT
instruction.
On processors without Thumb-2, the only Thumb instruction that can have a condition code is B .
(use at least one suffix)
Meaning
Prefixes for Parallel Instructions
16
User
S
Signed arithmetic modulo 28 or 216, sets CPSR GE bits
17
FIQ Fast Interrupt
Q
Signed saturating arithmetic
Signed arithmetic, halving results
18
IRQ Interrupt
SH
c
Control field mask byte
PSR[7:0]
19
Supervisor
U
Unsigned arithmetic modulo 28 or 216, sets CPSR GE bits
f
Flags field mask byte
PSR[31:24]
23
Abort
UQ
Unsigned saturating arithmetic
s
Status field mask byte
PSR[23:16]
27
Undefined
UH
Unsigned arithmetic, halving results
x
Extension field mask byte
PSR[15:8]
31
System
Proprietary Notice
Document Number
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited.
Other brands and names mentioned herein may be the trademarks of their respective owners.
ARM QRC 0001L
Neither the whole nor any part of the information contained in, or the product described in, this document
may be adapted or reproduced in any material form except with the prior written permission of the
copyright holder.
Change Log
The product described in this document is subject to continuous developments and improvements. All
particulars of the product and its use contained in this document are given by ARM in good faith.
However, all warranties implied or expressed, including but not limited to implied warranties of
merchantability, or fitness for purpose, are excluded.
This reference card is intended only to assist the reader in the use of the product. ARM Ltd shall not be
liable for any loss or damage arising from the use of any information in this reference card, or any error
or omission in such information, or any incorrect use of the product.
Issue
A
C
E
G
I
K
Date
June 1995
Nov 1998
Oct 2000
Jan 2003
Dec 2004
March 2006
Change
First Release
Third Release
Fifth Release
Seventh Release
Ninth Release
RVCT 3.0
Issue
B
D
F
H
J
L
Date
Sept 1996
Oct 1999
Sept 2001
Oct 2003
May 2005
March 2007
Change
Second Release
Fourth Release
Sixth Release
Eighth Release
RVCT 2.2 SP1
RVCT 3.1
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