A8M ASUS A8t.M
ASUS A8M - REV 2.1 - SC
User Manual:
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Page Count: 55
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
C51M--CRT & LVDS
VGA CONN
MCP51--HT
39
40
PAGE Content
4
5
6
7
8
9
10
11
12
13
14
15
16
26
27
28
29
SYSTEM PAGE REF.
C51M--HT TO MCP
32
33
34
30
31
AMD S1 CPU--DDR2
DDR2 SO-DIMM_0
19
23
18
22
17
21
25
20
24
A8T/M SCHEMATIC R2.1
POWER PAGE REF.
DDR2 SO-DIMM_1
DDR2 ADDRESS TERMINATION
C51M--HT TO CPU
CRT & TV_OUT
41
42
43
36
37
38
AMD S1 CPU--HT
AMD S1 CPU--CNTL
AMD S1 CPU--PWR/GND
C51M--PWR/GND
C51M--PCI-E
LVDS & INVERTER CONN
35
PAGE Content
MCP51--USB & HDA & GPIO
MCP51--PWR/GND
MCP51--PCI
MCP51--IDE
HDD & CD-ROM CONN
SUPER I/O LPC47N217
BIOS & FIR
USB PORTS
PCI-E--MINI CARD
KBC 38857
PCI--4 IN1 CON
SM BUS & POWER PORT
PCI--LAN RTL8110CL
MDC,B/T,TPM & DISCHG,HOLE
ACIN, BAT, FAN, I/O PORT
AUDIO CODEC ALC660
AUDIO AMP G1420
DVI CONN
SW & LED & TP
POWER-ON SEQUENCE
HISTORY
61 POWER_VCORE
62 POWER_SYSTEM
63 POWER_I/O_1.2VO & 1.0VO
64 POWER_I/O_LDO
67 POWER_LOAD_SYSTEM
65 POWER_I/O_DDR2
68 POWER_CHARGER
66 POWER_VGA_CORE(Empty)
69 POWER_PIC
70 POWER_PROTECT
72 POWER_DIAGRAM
71 POWER_SWITCH_+5VLCM
I/O PORT44
PCI-E--NEW CARD
PCI--1394,CardReader R5C832
RJ45 & RJ11
PAGE REF.
2.1
A8T
155
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
HT X16
RESET SM_BUS
DDR2 SDRAM 533/667MHz
AMD
638
H/W MONITOR
THERMAL
DCIN
RTC
FAN CON.
68
1.2VO & 1.0VO
PIC
64
CHARGER
62
67
I/O LDO
VCORE
SYSTEM
+1.8V & +0.9V
61
+1.8V
+0.9V
....
DDR
CAP/RES
BATTERY
TYPE
3S2P
HT X8
RTL8110SBL
MCP51
LAN IO
USB2.0
MINI CARD
PCI_BUS
3.3V, 33MHz
USB x5
PATA BUS
LAN 1G
LINE
OUT
RJ11,RJ45
CON
SW & LED &
TOUCHPAD
CON
Codec
ADI1986A
32
30
33
8,9
10
42 29
40
70
41
AUDIO AMP
G1420
26
28
INTERNAL
KEYBOARD
FIR
47N217
LPC, 33MHz
KEYBOARD
CONTROLLER
M38857
FWH
BIOS
SUPER I/O
3027
MIC_IN
MDC
CON
1394
SLOT
4 IN 1
CARD
READER
CARDBUS
33
34
35
40
65
PROTECT
63
69
40,44
IO PORT
RICOH
R5C832
ODD
(Secondary)
2424
HDD
(Primary)
37
36
38
27
37
ACZ
POWER
SEQENCE
42
40
40
A8T/M AMD S1/C51MV BLOCK DIAGRAM
PCI-E
x16
LVDS & INV
CON
Nvidia
17
DVI Dual
CH.
G7x series
CRT & TV
CON
C51MV
39
PCI EXPRESS X1
1394 USB MIC LINE_IN
4,5,6,7
VGA
CON
VGA BAORD
LFB LFB LFB LFB
18
16 11,12,13,14,15
25
Camera
38
B/T
38
VGA
CON
16
TPM
38
NEW
CARD
31
AC & BAT CON
FAN CTRL
40
70
71
72
SWITCH 5VLCM
DIAGRAM
DDR2 533/667
SODIMM X2
19,20,21,22,23
LOAD SYSTEM
MIC AMP
LM358
BLOCK DAIGRAM
2.1
A8T
255
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
M38857_GPIO USE_AS SIGNAL_NAME
P23
P22
P20
P42
P43
P50
P45
P52
P54
P55
P56
P57
P67
P66
P65
P64
P63
P62
GPO BAT_LEARN
GPO KBCRSM
ACIN_OC#
GPI
BAT_LLOW#_OC
PANLOCK_#
LID_KBC#
P61
BLUETOOTH_#
WATCHDOG
INTERNET_#
P44 KBCPURST_3Q
KBC_GA20
P60
P24
P41
SET_PCIRSTNS#
P46 KBSCI_3Q
P47 PM_CLKRUN#
P51
P27
P26
P25 CAP_LED#
BAT_IN_OC#
P77
P76 GPIO
GPIO
SM_BUS ADDRESS :
DDR_SODIMM0 = 1010000x ( A0h )
DDR_SODIMM1 = 1010001x ( A2h )
ADJ_BL
SMC_BAT
SMD_BAT
GPO
(AD30 internal)
1394
Chipset (Host to PCI)
IDSEL#
B
PCI Device
A
PC/PCI
Interrupts
n/a
REQ/GNT#
47N217_GPIO USE_AS SIGNAL_NAME
4 IN 1
P21 GPO
FAN1_TACH
MARATHON_#
PANLOCK_LED
P40 KBC_EXTSMI
WIRELESS_#
P53
Power
Power
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
GPO
GPO
GPO
GPO
GPI
GPI
GPO
GPO
GPO
GPO
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
GPI
KBDDT0
KBDDT1
FAN1_DC
NUM_LED#
GPO
GPO
GPO
GPO
GPO
GPO
SCR_LED# +3V
+3V
+3V
+3V
+3V
+3V
0
0
AD16
LAN -- Realtek AD17
GPI
GPI
GPO
+3VS
+3VS
+3VS
+3VSGPIO[40:45] GPI
GPIO46
GPIO47
GPIO23 +3VS
GPIO10
GPIO[11:12]
GPIO[13:14]
GPI
GPO
GPI
+3VS
+3VS
Thermal MAX6657 = 1001100x ( 98h )
MSK_INSTKEY#
SWDJ_EN
NEWCARD_OFF#
NEWCARD_DET#
1 C
PCI_PME#
ACZ_SDIN0_AUD
PCI_PERR#
+3VSUS
+3VS
GPO
GPIO_4
BACK_OFF#
GPIO_20
+3VSUS
GPIO_40
GPI
CHG_FULL_OC
GPO
+3VSUS
+3VS
GPIO_24
SMB_CLK_SB
+3VSUS
+3VSUS
+3VSUS
BT_ON/OFF#
GPIO_45
SUS_STAT#
GPIO_2
GPIO_27
+3VSUS
GPO
CB_SD#
GPO OP_SD#
GPIO_18
IGP_DDC_SELECT +3VSUS
+3VS
+3VSUS
GPI
Power
GPIO_1
BATT_TALARM#
GPIO_34
Use As
+3VSUS
+3VS
GPIO_26
SMB_MEM_SCL +3VSUS
EXTSMI#_3A
+3VSUS
GPIO_29
+3VSUS
+3VS
GPIO_7
MXM_PWR_ON
+3VSUS
MCP51_GPIO
+3VSUS
GPO
USB_OC#1
(SMB_ALERT#)
+3VSUS
GPI
GPIO_35
+3VSUS
+3VSUS
GPI
GPIO_44
GPO
GPIO_9 CR_VID1
KB_SCI#
CR_VID0
GPI
+3VS
(RI#)
GPIO_25
+3VS
GPIO_3
GPIO_47
WLAN_ON#
ACZ_SDIN1_MDC
+3VS
GPIO_22
GPIO_36
(CR_VID2)
ACZ_SYNC
(CPU_VID[0:5])
GPIO_46
ACZ_SDOUT
+3VSUS
GPIO_37
+3VSUS
SIO_SMI#
+3VSUS
GPIO_8
GPO
+3VSUS
GPIO_32
GPIO_43
GPIO_[11:16]
GPIO_5
+3VSUS
GPO
PM_CLKRUN#
+3VSUS
+3VSUS
+3VSUS
GPIO_6
+3VS
+3VSUS
GPIO_42
GPIO_23
+3VS
GPO
MCP_TV_EN
+3VSUS
GPIO_38
GPIO_39
GPIO_31
GPIO_28
GPIO_41
GPIO_10
PCB_ID2
GPIO_21
GPIO_17
SMB_DAT_SB
GPIO_33
PWRLMT#
SMB_MEM_SDA
+3VSUS
GPI
+3VSUS
Signal Name
802_LED_EN#
GPIO_30
1 Hz
GPO
+3VSUS
+3VS
GPIO_19
MCP51_GPIO Use As Signal Name Power
+3VS
GPIO_61
GPIO_62
GPO
+3VS
GPIO_64
+3VS
+3VS
GPIO_50
+3VS
GPIO_53
+3VS
LCD_VDD_EN_GM
GPI
+3VS
+3VS
SATA_LED#
GPO
HA20GATE
FWH_WP#
+3VS
KBDCPURST
GPIO_54
GPIO_58
GPIO_51
EDID_CLK_C51M
GPI +3VS
+3VS
GPO
+3VS
+3VS
PCB_ID0
GPIO_52
GPIO_63
IGP_SELECT
GPIO_60
GPU_ON
CPU_THERMTRIP#
GPIO_48
GPIO_57
+3VS
GPIO_59
GPIO_56
EDID_DATA_C51M
PM_THERM#
LCD_BACKEN_GM
GPIO_55
GPIO_49
PCB_ID1
+3VS
+3VS
GPO
(LID#)
GPI
SUS_CLK
LOAD_TEST
GPO
(CABLE_DET_P)
(CABLE_DET_S)
VGA_PWRGD
GPI VGA_DETECT#
GPI
SCHEMATICS REF.
2.1
A8T
355
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S1 CPU HT
2.1
A8T
455
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
HTCPU_TXDP4
HTCPU_TXDP8
HTCPU_TXDP13
HTCPU_TXDP7
HTCPU_TXDP10
HTCPU_TXDP15
HTCPU_TXDP12
HTCPU_TXDP9
HTCPU_TXDP11
HTCPU_TXDP5
HTCPU_TXDP6
HTCPU_TXDP14
HTCPU_TXDN15
HTCPU_TXDN6
HTCPU_TXDN14
HTCPU_TXDN4
HTCPU_TXDN8
HTCPU_TXDN13
HTCPU_TXDN3
HTCPU_TXDN5
HTCPU_TXDN7
HTCPU_TXDN0
HTCPU_TXDN1
HTCPU_TXDN2
HTCPU_TXDN12
HTCPU_TXDN10
HTCPU_TXDN11
HTCPU_TXDN9
HTCPU_TXDP3
HTCPU_TXDP1
HTCPU_TXDP0
HTCPU_TXDP2
HTCPU_RXDP5
HTCPU_RXDP4
HTCPU_RXDP8
HTCPU_RXDP10
HTCPU_RXDP2
HTCPU_RXDP3
HTCPU_RXDP6
HTCPU_RXDP11
HTCPU_RXDP0
HTCPU_RXDP13
HTCPU_RXDP1
HTCPU_RXDP7
HTCPU_RXDP9
HTCPU_RXDP12
HTCPU_RXDP15
HTCPU_RXDP14
HTCPU_RXDN7
HTCPU_RXDN13
HTCPU_RXDN2
HTCPU_RXDN1
HTCPU_RXDN14
HTCPU_RXDN5
HTCPU_RXDN4
HTCPU_RXDN8
HTCPU_RXDN12
HTCPU_RXDN9
HTCPU_RXDN11
HTCPU_RXDN3
HTCPU_RXDN6
HTCPU_RXDN15
HTCPU_RXDN10
HTCPU_RXDN0
HT_TXCTL
HT_TXCTL#
HT_TXCTL
HT_TXCTL#
+1.2VS_HT
HYPE RTRA NSPORT
U1A
SOCKET638
J5
K5
J3
J2
P3
P4
N1
P1
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
Y4
Y3
Y1
W1
T5
R5
R2
R3
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
R773
49.9Ohm
R772
49.9Ohm
T222
1
T221
1
HTCPU_TXDP[0..15]11
HTCPU_TXDN[0..15]11
HTCPU_RXDN[0..15] 11
HTCPU_RXDP[0..15] 11
HTCPU_RXCTL# 11
HTCPU_RXCLK1 11
HTCPU_RXCTL 11
HTCPU_RXCLK1# 11
HTCPU_TXCLK011
HTCPU_TXCTL11
HTCPU_TXCLK1#11
HTCPU_TXCTL#11
HTCPU_TXCLK0#11
HTCPU_TXCLK111
HTCPU_RXCLK0 11
HTCPU_RXCLK0# 11
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
R < 600 mils from CPU
AC caps < 1250 mils
Place near CPU socket
AMD circuit is 51 ohm
nVIDIA circuit is 10 ohm
< 1" from CPU
80 ohm diff impedence
For future processors
R1.1
R2.1
S1 CPU CNTL
2.1
A8T
555
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
H_THERMDC
H_THERMDA
VDDA
CLKIN
CLKIN#
VTT_SENSE
MEM_ZN
MEM_ZP
CPU_MVREF
CPU_MVREF
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
HT_REF1
HT_REF0
CPU_VDD_FB
CPU_VDD_FB#
PM_THRM#
H_THRMTRIP#
H_THERMDC
H_THERMDA
H_THRMTRIP#
H_PROCHOT#
FBCLKOUT
FBCLKOUT#
CPU_PWRGD
CPU_STP#
CPU_RST#
CPU_STP#
CPU_RST#
CPU_PWRGD
CPU_VID1
CPU_VDDIO_FB
H_PROCHOT# PROCHOT#
+2.5VS
+1.8V
+1.8V
+1.8V
+1.2VS_HT
+1.8V
+VCORE
+1.8VS
+1.8V
+3VS
+3VS
+3VS
+1.8VS
+1.8V
+2.5VS +1.8V
+3VSUS
+1.8V
+3VSUS
+5VO
R783
2KOhm
T229
1
R20
10K
RN35A
300Ohm
1 2
VCC
GND
U52E
74LVC07AD
11 10
R22
10KOhm
R780 44.2Ohm
1 2
R775 1KOhm
1 2
VCC
GND
U52B
74LVC07AD
3 4
R795
4.7KOhm
C1
0.1UF/16V
L100
180NH
21
Q102
2N7002
R774 169Ohm
1 2
T234
1
C704 3900PF/50V
12
RN35B
300Ohm
3 4
T232
1
T226 1
RN34A
1KOhm
1 2
Q1
PMBS3904
R799 51Ohm
1 2
C34 1000P
R779
2KOhm
T230
1
VCC
GND
U52A
74LVC07AD
1 2
RN35C
300Ohm
5 6
T7131 1
R27
4.7KOhm
T224
1
C701
4.7UF/6.3V
RN34B
1KOhm
3 4
R23
300Ohm
RN35D
300Ohm
7 8
C702
0.22UF/6.3V
T237
1
T238 1
Q109
PMBS3904
Q2A
UM6K1N
2
T225 1
R789 300Ohm
1 2
T231 1
RN34C
1KOhm
5 6
VCC
GND
U52C
74LVC07AD
5 6
VCC
GND
U52F
74LVC07AD
13 12
T7129
1
C705 3900PF/50V
12
R786 80.6Ohm
1 2
Q2B
UM6K1N
5
R21
1KOhm
R782 44.2Ohm
1 2
R798 51Ohm
1 2
U2
MAX6657MSA
8
7
6
1
4
2
3
5
SCLK
SDA
ALERT#
VCC
OVERT#
DXP
DXN
GND
RN34D
1KOhm
7 8
T223 1
VCC
GND
U52D
74LVC07AD
9 8
T235 1
T233 1
R792
10KOhm
R797
0Ohm
1 2
T7130
1
C706
0.1UF/16V
R790 300Ohm
1 2
R19 200
T7128 1
T236 1
C13
0.1U
T227 1
Q3A
UM6K1N
2
R777
300Ohm
1 2
R785 510Ohm
1 2
T228 1
R787 510Ohm
1 2
R791 300Ohm
1 2
R781
39.2Ohm
1 2
R784 39.2Ohm
1 2
C707
1000PF/50V
Q3B
UM6K1N
5
R794
300Ohm
+
CE7
100UF/6.3V
R788 300Ohm
1 2
MISC
U1D
SOCKET638
F8
F9
A9
A8
A7
F10
B7
AC6
AF4
AF5
AF9
AD9
AC9
AA9
E10
F6
E6
Y10
W17
AE10
AF10
E9
E8
G9
H10
AA7
C2
D7
E7
F7
C7
AC8
C3
AA6
W7
W8
Y6
AB6
A5
C6
A6
A4
C5
B5
AF6
AC7
AE9
G10
W9
Y9
A3
P6
R6
C9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
THERMDC
THERMDA
TEST3
TEST2
VID5
VID4
VID3
VID2
VID1
VID0
THERMTRIP_L
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
C703
3300PF/25V
R793 300Ohm
1 2
CLK_CPU11
CLK_CPU#11
CPU_VID[0..5] 61
CPU_VDD_FB61
CPU_VDD_FB#61
OTP_RESET# 42
SDA_3S 16,29
SCL_3S 16,29
CPU_THRMTRIP# 19
PM_THRM# 22
CPU_PSI# 61
HTCPU_RST#11
HTCPU_PWRGD11
HTCPU_STP#11
PCIRST_NEWC#20,31
PWRGD22,70
PROCHOT# 28
PWRLMT# 22,68,71
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
<1200 mil from CPU <1200 mil from CPU
S1 CPU MEM
2.1
A8T
655
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
M_A_DQ19
M_A_DQ27
M_A_DQ45
M_A_DQ4
M_A_DQ7
M_A_DQ56
M_A_DQ24
M_A_DQ22
M_A_DQ0
M_A_DQ41
M_A_DQ[0..63]
M_A_DQ29
M_A_DQ28
M_A_DQ38
M_A_DQ63
M_A_DQ11
M_A_DQ46
M_A_DQ42
M_A_DQ21
M_A_DQ50
M_A_DQ3
M_A_DQ60
M_A_DQ6
M_A_DQ52
M_A_DQ23
M_A_DQ35
M_A_DQ47
M_A_DQ61
M_A_DQ33
M_A_DQ20
M_A_DQ51
M_A_DQ13
M_A_DQ9
M_A_DQ5
M_A_DQ16
M_A_DQ15
M_A_DQ53
M_A_DQ2
M_A_DQ8
M_A_DQ62
M_A_DQ26
M_A_DQ37
M_A_DQ48
M_A_DQ30
M_A_DQ31
M_A_DQ54
M_A_DQ57
M_A_DQ18
M_A_DQ43
M_A_DQ34
M_A_DQ10
M_A_DQ14
M_A_DQ39
M_A_DQ58
M_A_DQ32
M_A_DQ1
M_A_DQ44
M_A_DQ17
M_A_DQ49
M_A_DQ55
M_A_DQ59
M_A_DQ25
M_A_DQ12
M_A_DQ36
M_A_DQ40
M_B_DQ59
M_B_DQ63
M_B_DQ22
M_B_DQ46
M_B_DQ13
M_B_DQ5
M_B_DQ11
M_B_DQ31
M_B_DQ57
M_B_DQ42
M_B_DQ18
M_B_DQ50
M_B_DQ26
M_B_DQ14
M_B_DQ55
M_B_DQ23
M_B_DQ44
M_B_DQ[0..63]
M_B_DQ36
M_B_DQ45
M_B_DQ17
M_B_DQ51
M_B_DQ27
M_B_DQ19
M_B_DQ0
M_B_DQ6
M_B_DQ48
M_B_DQ37
M_B_DQ34
M_B_DQ8
M_B_DQ61
M_B_DQ43
M_B_DQ24
M_B_DQ47
M_B_DQ20
M_B_DQ3
M_B_DQ7
M_B_DQ28
M_B_DQ38
M_B_DQ35
M_B_DQ1
M_B_DQ9
M_B_DQ29
M_B_DQ15
M_B_DQ21
M_B_DQ60
M_B_DQ52
M_B_DQ33
M_B_DQ4
M_B_DQ25
M_B_DQ53
M_B_DQ62
M_B_DQ58
M_B_DQ39
M_B_DQ56
M_B_DQ12
M_B_DQ32
M_B_DQ10
M_B_DQ30
M_B_DQ41
M_B_DQ2
M_B_DQ40
M_B_DQ16
M_B_DQ49
M_B_DQ54
M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR1
M_CLK_DDR0
M_CLK_DDR2
M_CLK_DDR3
M_CLK_DDR#3
M_CLK_DDR#2
MEMORY
INTERFACE
U1C
SOCKET638
AF18
AF17
A17
A18
Y26
J24
W24
U23
W23
W26
V26
U22
U24
K26
T26
U26
H26
J23
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
F26
E26
A24
A23
D16
C16
C12
B12
AD12
AC16
AE22
AB26
E25
A22
B16
A12
AD11
AF11
AF14
AE14
Y11
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
MB0_ODT1
MB0_ODT0
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK2
MB_BANK1
MB_BANK0
MB_CKE1
MB_CKE0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
C756
1.5PF/50V
INTERFACE
MEMORY
U1B
SOCKET638
Y16
AA16
E16
F16
V19
J22
V22
T19
V20
U19
U20
U21
T20
K22
R20
T22
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
Y13
AB16
Y19
AC24
F24
E19
C15
E12
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MA0_ODT1
MA0_ODT0
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK2
MA_BANK1
MA_BANK0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
C134
1.5PF/50V
C133
1.5PF/50V
C757
1.5PF/50V
M_A_CS#18,10
M_A_DQS#78
M_A_DQS#18
M_A_A98,10
M_A_RAS#8,10
M_A_DQS#48
M_A_BS#28,10
M_CLK_DDR08
M_CKE08,10
M_A_BS#08,10
M_ODT08,10
M_A_DQ[0..63]8
M_A_A38,10
M_A_A128,10
M_A_DQS38
M_A_DQS#38
M_A_DQS68
M_A_A138,10
M_A_DQS#08
M_A_WE#8,10
M_A_DQS48
M_ODT18,10
M_A_A18,10
M_A_BS#18,10
M_A_CAS#8,10
M_A_A48,10
M_CLK_DDR#18
M_A_A28,10
M_A_DQS#58
M_A_A68,10
M_A_DQS78
M_A_A78,10
M_A_A08,10
M_A_DQS08
M_CLK_DDR18
M_A_DQS18
M_A_A88,10
M_A_CS#08,10
M_A_A58,10
M_A_DQS58
M_A_DQS28
M_CLK_DDR#08
M_A_DQS#28
M_A_A118,10
M_A_A108,10
M_A_DQS#68
M_CKE18,10
M_ODT39,10
M_CLK_DDR39
M_B_BS#29,10
M_B_A79,10
M_B_DQS#49
M_B_A139,10
M_B_DQS#69
M_B_A59,10
M_B_RAS#9,10
M_B_DQS#59
M_B_DQS09
M_B_A39,10
M_B_A29,10
M_B_A49,10
M_B_A109,10
M_B_A119,10
M_CKE29,10
M_B_A69,10
M_B_BS#09,10
M_B_A129,10
M_CLK_DDR29
M_B_DQS#39
M_B_WE#9,10
M_B_DQS#29
M_B_DQS69
M_B_DQS#19
M_B_CAS#9,10
M_B_A09,10
M_B_DQ[0..63]9
M_B_BS#19,10
M_B_DQS#09
M_B_DQS79
M_B_DQS#79
M_CLK_DDR#29
M_B_A19,10
M_CLK_DDR#39
M_B_DQS39
M_B_DQS29
M_B_DQS19
M_B_DQS59
M_B_A99,10
M_B_A89,10
M_B_DQS49
M_ODT29,10
M_CKE39,10
M_A_DM48
M_A_DM68
M_A_DM18
M_A_DM38
M_A_DM08
M_A_DM28
M_A_DM58
M_A_DM78
M_B_DM19
M_B_DM29
M_B_DM49
M_B_DM39
M_B_DM59
M_B_DM69
M_B_DM79
M_B_DM09
M_B_CS#19,10
M_B_CS#09,10
M_A_A148,10
M_A_A158,10
M_A_CS#38,10
M_A_CS#28,10
M_B_A149,10
M_B_A159,10
M_B_CS#29,10
M_B_CS#39,10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place under socket on bottom side
Place close to socket
Place close to socket
Place close to socket
Place under socket on bottom side
S1 CPU PWR/GND
2.1
A8T
755
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+0.9V
+1.2VS_HT
+VCORE
+VCORE
+1.8V
+0.9V
+1.8V
C2
0.01UF/25V
C720
4.7UF/6.3V
C722
0.22UF/6.3V
C715
4.7UF/6.3V
C727
22UF/6.3V
C753
22UF/6.3V
C750
180PF/50V
C749
0.22UF/6.3V
C746
0.22UF/6.3V
C711
0.22UF/6.3V
C732
22UF/6.3V
C725
180PF/50V
C752
22UF/6.3V
C739
0.22UF/6.3V
C721
0.22UF/6.3V
C755
0.22UF/6.3V
C735
180PF/50V
C709
4.7UF/6.3V
VDD
U1G
SOCKET638
J15
K16
L15
M16
P16
T16
U15
V16
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS130
VSS131
VSS132
VSS133
C726
180PF/50V
C6
0.01UF/25V
C7114
0.22UF/6.3V
MISC
INTERNAL
U1E
SOCKET638
P20
P19
N20
N19
R26
R25
P22
R22
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
RSVD_MA0_CLK_H3
RSVD_MA0_CLK_L3
RSVD_MA0_CLK_H0
RSVD_MA0_CLK_L0
RSVD_MB0_CLK_H3
RSVD_MB0_CLK_L3
RSVD_MB0_CLK_H0
RSVD_MB0_CLK_L0
RSVD_MA_RESET_L
RSVD_MB_RESET_L
RSVD_VIDSTRB1
RSVD_VIDSTRB0
RSVD_VDDNB_FB_H
RSVD_VDDNB_FB_L
RSVD_CORE_TYPE
FREE5
FREE6
FREE4
FREE1
FREE2
FREE3
C714
180PF/50V
C736
180PF/50V
C724
1000PF/50VC734
1000PF/50V
C733
1000PF/50V
C751
180PF/50V
C710
4.7UF/6.3V
C719
4.7UF/6.3V
C740
180PF/50V
C708 4.7UF/6.3V
12
POWER
I O
U1H
SOCKET638
D4
D3
D2
D1
D10
C10
B10
AD10
W10
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
AE5
AE4
AE3
AE2
AC10
AB10
AA10
A10
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
VLDT_A4
VLDT_A3
VLDT_A2
VLDT_A1
VTT8
VTT7
VTT6
VTT5
VTT9
VDDIO23
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VLDT_B4
VLDT_B3
VLDT_B2
VLDT_B1
VTT4
VTT3
VTT2
VTT1
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
C3
0.01UF/25V
C717
0.22UF/6.3V
C747
0.22UF/6.3V
C748
0.22UF/6.3V
C738
22UF/6.3V
C712
0.22UF/6.3V
C731
22UF/6.3V
C743
4.7UF/6.3V
C741
22UF/6.3V
C745
4.7UF/6.3V
C723
1000PF/50V
VDD
U1F
SOCKET638
AC4
AD2
G4
H2
J9
J11
J13
K6
K10
K12
K14
L4
L7
L9
L11
L13
M2
M6
M8
M10
N7
N9
N11
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
V6
V8
V10
V12
V14
W4
Y2
AA4
AA11
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
C729
22UF/6.3V
C730
22UF/6.3V
C737
22UF/6.3V
C716
4.7UF/6.3V
C718
0.22UF/6.3V
C728
22UF/6.3V
C713
180PF/50V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note: Place these Caps near SO DIMM 0
DDR2 SO-DIMM0
2.1
A8T
855
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_DQ[0..63]
M_A_DQ6
M_A_DQ62
M_A_DQ15
M_A_DQ16
M_A_DQ34
M_A_DQ45
M_A_DQ47
M_A_DQ56
M_A_DQ0
M_A_DQ38
M_A_DQ11
M_A_DQ3
M_A_DQ51
M_A_DQ39
M_A_DQ59
M_A_DQ12
M_A_DQ30
M_A_DQ19
M_A_DQ43
M_A_DQ57
M_A_DQ9
M_A_DQ35
M_A_DQ28
M_A_DQ33
M_A_DQ42
M_A_DQ55
M_A_DQ1
M_A_DQ7
M_A_DQ58
M_A_DQ21
M_A_DQ36
M_A_DQ46
M_A_DQ53
M_A_DQ14
M_A_DQ10
M_A_DQ24
M_A_DQ29
M_A_DQ37
M_A_DQ49
M_A_DQ4
M_A_DQ61
M_A_DQ23
M_A_DQ17
M_A_DQ32
M_A_DQ31
M_A_DQ25
M_A_DQ40
M_A_DQ52
M_A_DQ8
M_A_DQ54
M_A_DQ5
M_A_DQ60
M_A_DQ20
M_A_DQ63
M_A_DQ22
M_A_DQ41
M_A_DQ27
M_A_DQ44
M_A_DQ13
M_A_DQ18
M_A_DQ2
M_A_DQ48
M_A_DQ50
M_A_DQ26
M_A_DQS#3
M_A_DM2
M_A_DQS1
M_A_DQS#1
M_A_DQS7
M_A_DQS#5
M_A_DM4
M_A_DQS6
M_A_DM1
M_A_DQS4
M_A_DM3
M_A_DQS#0
M_A_DQS3
M_A_DQS2
M_A_DM7
M_A_DM5
M_A_DQS#4
M_A_DQS#7
M_A_DM6
M_A_DM0
M_A_DQS5
M_A_DQS#2
M_A_DQS#6
M_A_DQS0
M_A_A14
M_A_A15
+1.8V
+3VS
VTT_REF
+1.8V
+3VS
+1.8V
+1.8V
CON2B
DDR_DIMM_200P
112
111
117
96
95
118
81
82
87
103
88
104
199
83
120
50
69
163
1
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
203
204
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
NP_NC1
NP_NC2
C145
1U/6.3V
C137
0.1U
C141
1U/6.3V
C139
0.1U
CON2A
DDR_DIMM_200P
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
107
106
110
115
30
32
164
166
79
80
113
108
109
198
200
197
195
114
119
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
85
194
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
A16_BA2
DQ63
C138
0.1U
C140
0.1U
C136
0.1U
C142
1U/6.3V
C143
1U/6.3V
C135
0.1U
C144
1U/6.3V
SMB_MEM_SDA9,22
M_A_DQS[0..7]6
M_A_DQS#[0..7]6
M_ODT16,10
M_A_CAS#6,10
M_CKE16,10
M_ODT06,10
M_A_CS#06,10
M_CKE06,10
M_A_RAS#6,10
SMB_MEM_SCL9,22
M_A_CS#16,10
M_A_WE#6,10
M_CLK_DDR16
M_CLK_DDR06
M_CLK_DDR#06
M_CLK_DDR#16
M_A_DQ[0..63]6
M_A_A[0..15]6,10
M_A_BS#26,10
M_A_BS#06,10
M_A_BS#16,10
+1.8V 5,7,9,10,38,65
+3VS 5,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
M_A_DM[0..7]6
M_A_CS#36,10
M_A_CS#26,10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note: Place these Caps near SO DIMM 1
DDR2 SO-DIMM1
2.1
A8T
955
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_DQ[0..63]
M_B_DQ31
M_B_DQ6
M_B_DQ48
M_B_DQ61
M_B_DQ38
M_B_DQ21
M_B_DQ39
M_B_DQ7
M_B_DQ32
M_B_DQ40
M_B_DQ59
M_B_DQ50
M_B_DQ3
M_B_DQ13
M_B_DQ4
M_B_DQ34
M_B_DQ20
M_B_DQ44
M_B_DQ62
M_B_DQ51
M_B_DQ16
M_B_DQ8
M_B_DQ45
M_B_DQ1
M_B_DQ57
M_B_DQ52
M_B_DQ33
M_B_DQ22
M_B_DQ24
M_B_DQ41
M_B_DQ17
M_B_DQ43
M_B_DQ35
M_B_DQ56
M_B_DQ49
M_B_DQ12
M_B_DQ46
M_B_DQ14
M_B_DQ15
M_B_DQ36
M_B_DQ47
M_B_DQ18
M_B_DQ30
M_B_DQ42
M_B_DQ63
M_B_DQ29
M_B_DQ54
M_B_DQ25
M_B_DQ23
M_B_DQ0
M_B_DQ5
M_B_DQ11
M_B_DQ58
M_B_DQ55
M_B_DQ27
M_B_DQ9
M_B_DQ2
M_B_DQ26
M_B_DQ28
M_B_DQ19
M_B_DQ53
M_B_DQ10
M_B_DQ60
M_B_DQ37
M_B_DQS1
M_B_DQS6
M_B_DM7
M_B_DQS#4
M_B_DQS2
M_B_DQS0
M_B_DQS5
M_B_DM0
M_B_DM2
M_B_DQS#1
M_B_DQS#7
M_B_DQS3
M_B_DQS#0
M_B_DQS#6
M_B_DQS4
M_B_DM1
M_B_DM5
M_B_DM4
M_B_DQS#2
M_B_DQS7
M_B_DM3
M_B_DQS#5
M_B_DM6
M_B_DQS#3
M_B_A15
M_B_A14
+1.8V
+3VS
VTT_REF
+5V
+1.8V
VTT_REF
+5V
+1.8V
+3VS
+5V
+1.8V
+1.8V
+3VS
T21
C152
0.1U
R156
10K_1
CON1A
DDR2_DIMM_200P
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
107
106
110
115
30
32
164
166
79
80
113
108
109
198
200
197
195
114
119
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
85
194
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15
BA0
BA1
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
A16_BA2
DQ63
C149
1U/6.3V_*
C156
1U/6.3V
C153
0.1U
C155
1U/6.3V
C160
0.1U
+
-
V+
V-
U5
LMV321IDBVR
1
3
4
C159
1U/6.3V
C150
0.1U
C161
0.01U/X7R
C157
1U/6.3V
C154
0.1U
C158
1U/6.3V
C166
1U/6.3V
C151
0.1U
CON1B
DDR2_DIMM_200P
112
111
117
96
95
118
81
82
87
103
88
104
199
83
120
50
69
163
1
201
202
47
133
183
77
12
48
184
78
71
72
121
122
196
193
8
18
24
41
53
42
54
59
65
60
66
127
139
128
145
165
171
172
177
187
178
190
9
21
33
155
34
132
144
156
168
2
3
15
27
39
149
161
28
40
138
150
162
203
204
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDDSPD
NC1
NC2
NC3
NC4
NCTEST
VREF
GND0
GND1
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
NP_NC1
NP_NC2
C148
0.1U
R157
10K_1
C758
1000PF/50V
SMB_MEM_SDA8,22
M_B_DM[0..7]6
M_B_DQS[0..7]6
M_B_DQS#[0..7]6
M_B_CAS#6,10
M_B_RAS#6,10
M_B_WE#6,10
SMB_MEM_SCL8,22
M_ODT26,10
M_ODT36,10
M_B_CS#06,10
M_B_CS#16,10
M_CKE36,10
M_B_DQ[0..63]6
M_CKE26,10
M_B_A[0..15]6,10
M_B_BS#26,10
M_B_BS#16,10
M_B_BS#06,10
M_CLK_DDR#26
M_CLK_DDR#36
M_CLK_DDR26
M_CLK_DDR36
+3VS 5,8,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+1.8V 5,7,8,10,38,65
+5V 16,18,25,28,31,38,40,41
M_B_CS#26,10
M_B_CS#36,10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9V
DDR2 ADDRESS TERMINATION
2.1
A8T
10 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
M_B_A3
M_A_CS#3
M_B_A5
M_A_A11
M_B_A9
M_A_A10
M_B_A13
M_A_A0
M_A_A1
M_A_WE#
M_ODT1
M_B_A11
M_B_A6
M_A_A5
M_A_A7
M_B_CS#1
M_CKE0
M_B_A15
M_A_A4
M_A_CS#2
M_B_CS#2
M_A_BS#1
M_A_BS#2
M_A_A2
M_B_A2
M_B_A12
M_B_A7
M_CKE1
M_B_CS#0
M_A_A6
M_B_A0
M_A_A13
M_ODT0
M_B_BS#0
M_B_A4
M_B_A1
M_B_A14
M_B_A8
M_A_A3
M_B_CS#3
M_B_BS#2
M_A_A8
M_A_BS#0
M_A_A12
M_B_A10
M_CKE3
M_A_A14
M_A_A15
M_CKE2
M_ODT2
M_A_CS#1
M_A_CS#0
M_A_A9
M_ODT3
+0.9V
+0.9V +1.8V
+0.9V
+0.9V
R159 47
C187
0.1U
RN3D
47OHM
7 8
C171
0.1U
RN4E
47
5 12
RN2C
47
3 14
R187 47
RN5F
47
6 11
C191
0.1U
RN10A
47OHM
1 2
RN4A
47
1 16
RN9D
47
4 13
C190
0.1U
RN5E
47
5 12
C172
0.1U
RN6F
47
6 11
RN2E
47
5 12
RN7H
47
8 9
R185 47
RN3C
47OHM
5 6
RN6G
47
7 10
RN10D
47OHM
7 8
RN4H
47
8 9
RN9C
47
3 14
RN6A
47
1 16
R168 47
C189
0.1U
RN7C
47
3 14
C167
0.1U
C178
0.1U
RN2A
47
1 16
C184
0.1U
RN6C
47
3 14
RN5B
47
2 15
RN9F
47
6 11
C183
0.1U
RN3B
47OHM
3 4
RN7B
47
2 15
C179
0.1U
RN5D
47
4 13
RN2G
47
7 10
C168
0.1U
RN7G
47
7 10
RN9H
47
8 9
R184 47
RN6B
47
2 15
C182
0.1U
RN5H
47
8 9
C175
0.1U RN4B
47
2 15
RN2H
47
8 9
RN5A
47
1 16
RN3A
47OHM
1 2
C169
0.1U
RN6D
47
4 13
RN9E
47
5 12
C185
0.1U
RN7D
47
4 13
C177
0.1U
RN5C
47
3 14
RN2F
47
6 11
C170
0.1U
RN4G
47
7 10
RN7A
47
1 16
RN4C
47
3 14
RN9G
47
7 10
C188
0.1U
C176
0.1U
RN7F
47
6 11
RN7E
47
5 12
RN2B
47
2 15
C174
0.1U
RN5G
47
7 10
R158 47
RN9B
47
2 15
RN4F
47
6 11
RN10C
47OHM
5 6
RN6H
47
8 9
C173
0.1U
RN2D
47
4 13
RN9A
47
1 16
RN10B
47OHM
3 4
C180
0.1U
RN4D
47
4 13
RN6E
47
5 12
M_A_CS#2 6,8
M_B_A11 6,9
M_A_A13 6,8
M_A_CS#0 6,8
M_A_A5 6,8
M_B_RAS# 6,9
M_B_BS#1 6,9
M_B_A14 6,9
M_B_A4 6,9
M_CKE3 6,9
M_B_A1 6,9
M_B_CS#2 6,9
M_A_CAS# 6,8
M_B_BS#0 6,9
M_B_A0 6,9
M_B_CS#3 6,9
M_B_A15 6,9
M_B_A13 6,9
M_CKE1 6,8
M_A_WE# 6,8
M_A_A0 6,8
M_ODT2 6,9
M_B_CS#0 6,9
M_B_A6 6,9
M_A_A3 6,8
M_B_A3 6,9
M_ODT0 6,8
M_A_BS#2 6,8
M_A_A11 6,8
M_A_A15 6,8
M_A_A14 6,8
M_B_CS#1 6,9
M_A_A8 6,8
M_A_A7 6,8
M_A_BS#1 6,8
M_B_WE# 6,9
M_A_A10 6,8
M_A_A6 6,8
M_A_A4 6,8
M_A_A12 6,8
M_ODT1 6,8
M_B_A10 6,9
M_A_BS#0 6,8
+0.9V 7,48,65
M_A_A2 6,8
M_A_RAS# 6,8
M_A_CS#1 6,8
M_B_BS#2 6,9
M_B_A5 6,9
M_B_CAS# 6,9
M_A_A9 6,8
M_B_A9 6,9
M_ODT3 6,9
M_B_A2 6,9
M_CKE0 6,8
M_B_A7 6,9
M_CKE2 6,9
M_B_A12 6,9
M_A_CS#3 6,8
M_A_A1 6,8
M_B_A8 6,9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Near BGA
< 500 mil; 5/10
Int. PU
1.5" ~ 7"
breakout: 5/5
normal: 5/10
C51M HT
2.1
A8T
11 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
HTCPU_TXDP0
HTCPU_TXDP1
HTCPU_TXDP2
HTCPU_TXDP3
HTCPU_TXDP4
HTCPU_TXDP5
HTCPU_TXDP6
HTCPU_TXDP7
HTCPU_TXDP8
HTCPU_TXDP9
HTCPU_TXDP10
HTCPU_TXDP11
HTCPU_TXDP12
HTCPU_TXDP13
HTCPU_TXDP14
HTCPU_TXDP15
HTCPU_TXDN0
HTCPU_TXDN1
HTCPU_TXDN2
HTCPU_TXDN3
HTCPU_TXDN4
HTCPU_TXDN5
HTCPU_TXDN6
HTCPU_TXDN7
HTCPU_TXDN8
HTCPU_TXDN9
HTCPU_TXDN10
HTCPU_TXDN11
HTCPU_TXDN12
HTCPU_TXDN13
HTCPU_TXDN14
HTCPU_TXDN15
HTCPU_REQ#
+2.5VS_PLLHT
HTCPU_RXDP0
HTCPU_RXDP1
HTCPU_RXDP2
HTCPU_RXDP3
HTCPU_RXDP4
HTCPU_RXDP5
HTCPU_RXDP6
HTCPU_RXDP7
HTCPU_RXDP8
HTCPU_RXDP9
HTCPU_RXDP10
HTCPU_RXDP11
HTCPU_RXDP12
HTCPU_RXDP13
HTCPU_RXDP14
HTCPU_RXDP15
HTCPU_RXDN0
HTCPU_RXDN1
HTCPU_RXDN2
HTCPU_RXDN3
HTCPU_RXDN4
HTCPU_RXDN5
HTCPU_RXDN6
HTCPU_RXDN7
HTCPU_RXDN8
HTCPU_RXDN9
HTCPU_RXDN10
HTCPU_RXDN11
HTCPU_RXDN12
HTCPU_RXDN13
HTCPU_RXDN14
HTCPU_RXDN15
HTCPUCA_1P2V
HTCPUCA_GND
+1.2VS_PLLHT
+2.5VS
+2.5VS+1.2VS
+1.2VS_HT
C760
0.1UF/16V
R800 150Ohm
1 2
C761
1UF/10V
R801 150Ohm
1 2
C759
1UF/10V
U4A
C51MV
Y23
W24
V24
U22
R24
P24
P22
N22
Y21
V21
W21
T21
R18
P16
N20
M17
Y22
W23
V23
U21
R23
P23
P21
N21
Y20
W20
W22
U20
R19
P17
N19
N18
T23
T22
R21
R20
M23
M22
W19
Y19
N16
T13
C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18
C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19
G23
G24
G22
G21
L23
L24
B24
B23
A22
B21
F18
G18
D20
E19
L16
HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P
HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N
HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N
HT_CPU_RXCTL_P
HT_CPU_RXCTL_N
HT_CPU_CAL_1P2V
HT_CPU_CAL_GND
+1.2V_PLLHTCPU
+1.2V_PLLHTMCP
HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P
HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P
HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N
HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N
HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N
HT_CPU_TXCTL_P
HT_CPU_TXCTL_N
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N
HT_CPU_REQ*
HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD
+2.5V_PLLHTCPU
T240
1
T239
1
L102
120Ohm/100Mhz
21
C762
0.1UF/16V
L101
120Ohm/100Mhz
21
R802 22kOhm_*
1 2
HTCPU_RXDP[0..15]4
HTCPU_RXDN[0..15]4
HTCPU_TXDP[0..15] 4
HTCPU_TXDN[0..15] 4
HTCPU_TXCLK0 4
HTCPU_TXCLK0# 4
HTCPU_TXCLK1 4
HTCPU_TXCLK1# 4
HTCPU_TXCTL 4
HTCPU_TXCTL# 4
CLK_CPU 5
CLK_CPU# 5
HTCPU_STP# 5
HTCPU_RST# 5
HTCPU_PWRGD 5
HTCPU_RXCLK04
HTCPU_RXCLK0#4
HTCPU_RXCLK14
HTCPU_RXCLK1#4
HTCPU_RXCTL4
HTCPU_RXCTL#4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OD
OD1.5" ~ 7"
1.5" ~ 7"
breakout: 5/5
normal: 5/10
< 500 mil; 5/5/10
C51M HT TO MCP
2.1
A8T
12 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
HTMCP_TXDP0
HTMCP_TXDP1
HTMCP_TXDP2
HTMCP_TXDP3
CLKOUT_CTERM_GND
HTMCPCA_1P2V
HTMCPCA_GND
HTMCP_RXDP0
HTMCP_RXDP3
HTMCP_RXDP2
HTMCP_RXDP1
HTMCP_TXDN0
HTMCP_TXDN1
HTMCP_TXDN2
HTMCP_TXDN3
HTMCP_RXDP4
HTMCP_RXDP5
HTMCP_RXDP6
HTMCP_RXDP7
HTMCP_RXDN0
HTMCP_RXDN2
HTMCP_RXDN1
HTMCP_RXDN3
HTMCP_RXDN4
HTMCP_RXDN5
HTMCP_RXDN6
HTMCP_RXDN7
HTMCP_TXDP4
HTMCP_TXDP5
HTMCP_TXDP6
HTMCP_TXDP7
HTMCP_TXDN4
HTMCP_TXDN5
HTMCP_TXDN6
HTMCP_TXDN7
+1.2VS
U4B
C51MV
AD6
AC7
AA8
AA9
AD10
AD11
AC12
AC13
AA6
W7
Y8
V9
Y10
AA11
V11
W12
AC6
AB7
AB8
AB9
AC10
AC11
AB12
AB13
Y6
Y7
AA7
W9
W10
Y12
W11
V13
AD9
AC9
U10
T10
AD14
AC14
AB5
AA5
AC5
AD5
AB24
AC4
Y5
W5
AC24
AD23
AC22
AC20
AB18
AA17
AB16
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13
AC23
AD22
AC21
AD20
AC18
AB17
AB15
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13
AC19
AD19
Y17
W17
AC15
AD15
B22
A20
B20
AB23
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N
HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD
HT_MCP_CAL_GND
CLKIN_25MHZ
CLKIN_200MHZ_P
CLKIN_200MHZ_N
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_CTERM_GND
SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N
HT_MCP_CAL_1P2V
R805 2.37KOhm
1 2
T241
1
R806 150Ohm
1 2
R807 150Ohm
1 2
T242
1
HTMCP_RXDN[0..7]19
HTMCP_TXDP[0..7] 19
HTMCP_TXDN[0..7] 19
HTMCP_RXCLK019
HTMCP_RXCTL19
HTMCP_RXCTL#19
HTMCP_RXCLK0#19 HTMCP_TXCLK0# 19
HTMCP_TXCTL# 19
HTMCP_TXCLK0 19
HTMCP_TXCTL 19
HTMCP_REQ#19
HTMCP_STP#19
HTMCP_RST#19
HTMCP_PWRGD19
CLK_25M19
CLK_NBHT19
CLK_NBHT#19
HTMCP_RXDP[0..7]19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
C51M PCI-E
2.1
A8T
13 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PCIE_TXP1
PCIE_TXN1
PCIE_TXN2
PCIE_TXP2
+1.2VS_PLLPE
PRSNT_NEWCARD#
EXP_RXP7
EXP_RXP3
EXP_RXP11
EXP_RXN4
EXP_RXN0
EXP_RXN12
EXP_RXN8
EXP_RXP6
EXP_RXP2
EXP_RXN3
EXP_RXP15
EXP_RXN7
EXP_RXP5
EXP_RXN15
EXP_RXP1
EXP_RXP10
EXP_RXN2
EXP_RXP14
EXP_RXN6
EXP_RXN11
EXP_RXP9
EXP_RXN1
EXP_RXP13
EXP_RXN5
EXP_RXN14
EXP_RXN10
EXP_RXP8
EXP_RXP4
EXP_RXP12
EXP_RXN13
EXP_RXN9
EXP_RXP0
EXP_TXN8
EXP_TXP7
EXP_TXN12
EXP_TXP13
EXP_TXP0
EXP_TXP5
EXP_TXN7
EXP_TXN11
EXP_TXN3
EXP_TXN2
EXP_TXP12
EXP_TXP11
EXP_TXP10
EXP_TXN1
EXP_TXN6
EXP_TXP4
EXP_TXN10
EXP_TXP9
EXP_TXN14
EXP_TXN0
EXP_TXN5
EXP_TXP3
EXP_TXN13
EXP_TXN4
EXP_TXP2
EXP_TXN9
EXP_TXP14
EXP_TXP8
EXP_TXP1
EXP_TXP6
EXP_TXP15
EXP_TXN15
+3VS
+1.2VS
+3VS
C763
0.1UF/10V
12
L103
120Ohm/100Mhz
21
R7140 0Ohm
1 2
C764 0.1UF/10V
12
R809 100Ohm_*
1 2
C768
0.1UF/16V
R7141 0Ohm_*
1 2
C767
1UF/16V_*
R7133
10KOhm_*
C765
0.1UF/10V
12
R810 2.37KOhm
1 2
U4C
C51MV
J8
J6
K9
L6
L7
M9
N8
N6
R6
P3
R8
U6
T8
U7
V4
Y3
J7
J5
J9
L5
L8
M8
N7
N5
R5
P4
R7
U5
T9
U8
V3
AA3
D1
G6
H6
E2
J4
K3
E3
J3
H2
D3
H3
E4
F1
AC3
F2
AB3
T11
L1
L3
L4
M4
P1
R1
R3
R4
U4
V1
W1
W3
AA1
AB1
AC1
AD2
L2
M2
M3
N3
P2
R2
T2
T3
U3
V2
W2
Y2
AA2
AB2
AC2
AD3
K1
K2
G4
G5
G2
G3
H4
G1
D2
PE0_RX0_P
PE0_RX1_P
PE0_RX2_P
PE0_RX3_P
PE0_RX4_P
PE0_RX5_P
PE0_RX6_P
PE0_RX7_P
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX11_P
PE0_RX12_P
PE0_RX13_P
PE0_RX14_P
PE0_RX15_P
PE0_RX0_N
PE0_RX1_N
PE0_RX2_N
PE0_RX3_N
PE0_RX4_N
PE0_RX5_N
PE0_RX6_N
PE0_RX7_N
PE0_RX8_N
PE0_RX9_N
PE0_RX10_N
PE0_RX11_N
PE0_RX12_N
PE0_RX13_N
PE0_RX14_N
PE0_RX15_N
PE0_PRSNT*
PE1_RX_P
PE1_RX_N
PE1_PRSNT*
PE2_RX_P
PE2_RX_N
PE2_PRSNT*
PE2_TX_N
PE2_REFCLK_P
PE1_CLKREQ*/CLK
PE2_REFCLK_N
PE2_CLKREQ*/DATA
PE_TSTCLK_P
PE_REFCLKIN_P
PE_TSTCLK_N
PE_REFCLKIN_N
+1.2V_PLLPE
PE0_TX0_P
PE0_TX1_P
PE0_TX2_P
PE0_TX3_P
PE0_TX4_P
PE0_TX5_P
PE0_TX6_P
PE0_TX7_P
PE0_TX8_P
PE0_TX9_P
PE0_TX10_P
PE0_TX11_P
PE0_TX12_P
PE0_TX13_P
PE0_TX14_P
PE0_TX15_P
PE0_TX0_N
PE0_TX1_N
PE0_TX2_N
PE0_TX3_N
PE0_TX4_N
PE0_TX5_N
PE0_TX6_N
PE0_TX7_N
PE0_TX8_N
PE0_TX9_N
PE0_TX10_N
PE0_TX11_N
PE0_TX12_N
PE0_TX13_N
PE0_TX14_N
PE0_TX15_N
PE0_REFCLK_P
PE0_REFCLK_N
PE1_TX_P
PE1_TX_N
PE1_REFCLK_P
PE1_REFCLK_N
PE2_TX_P
PE_RESET*
PE_CTERM_GND
C766 0.1UF/10V
12
R808
10KOhm
EXP_RXP[0..15]16
EXP_RXN[0..15]16
EXP_TXP[0..15] 16
EXP_TXN[0..15] 16
CLK_PCIE_VGA# 16
CLK_PCIE_VGA 16
PCIE_TXP1_MINICARD 30
PCIE_TXN1_MINICARD 30
CLK_PCIE_NEWCARD 31
CLK_PCIE_NEWCARD# 31
PCIE_TXN2_NEWCARD 31
PCIE_TXP2_NEWCARD 31
CLK_PCIE_MINICARD 30
CLK_PCIE_MINICARD# 30
PE_RST# 16,30
PCIE_RXN1_MINICARD30
PCIE_RXP1_MINICARD30
PCIE_RXN2_NEWCARD31
PCIE_RXP2_NEWCARD31
PRSNT_NEWCARD#31
CLK_REQ_MINICARD#30
CLK_REQ_NEWCARD#31
VGA_DETECT#16,20
GPU_ON16,20
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place near C51M
Place near connector
C51MV TV/CRT
SELECT
TV SLI Mux Between C51 & G7X
CRT SLI Mux Between C51 & G7X
10 mA
20 mA
20 mA
20 mA
Place near
switch
Place near switch
Place near switch
Place near connector
Place near connector
Place near switch
R1.1
R1.1
R1.1 R1.1
R1.1
C51M CRT&LVDS
2.1
A8T
14 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
IFPAB_RSET
IFPAB_VPROBE
DAC_B_C51M
DAC_G_C51M
DAC_RSET
DAC_VREF
+3VS_DAC
+2.5VS_PLLGPU
X1
X2
X1 X2
+2.5VS_PLLCORE
+2.5VS_PLLIFP +2.5VS_PLLIFP
+1.2VS_PLLGCI
DAC_R_C51M
LOAD_VIDEO
TVDAC_CVBS_NB
DAC_G_NB
TVDAC_Y_NB
LOAD_VGA
DAC_G_C51M
TVDAC_CVBS_NB
TVDAC_C_NB
TVDAC_Y_NB
DAC_G_NB
DAC_B_NB
DAC_R_NB
DAC_B_NB
IGP_SELECT
DAC_R_NB
TVDAC_C_NB
DAC_R_C51M
DAC_B_C51M
TV_C_NV
TV_Y_NV
TV_CVBS_NV
DAC_B_NV
DAC_G_NV
DAC_R_NV
+3VS
+2.5VS
+1.2VS
+3VS
+2.5VS
+2.5VS
+5VS
+3VS
+5VS
+5VS
C777
0.1UF/16V
R826
22KOhm
C775
1UF/10V
R819
22KOhm_*
R33
150Ohm
1 2
X6
27Mhz
R820 1KOhm
1 2
C776
4.7UF/6.3V
R201
150_1
C770
4.7UF/6.3V
C772 0.1UF/16V
1 2
C771
0.1UF/16V
R814
150Ohm
R827 0Ohm
1 2
C779
18PF/50V
R818 1KOhm
12
R823 0Ohm
1 2
C778
18PF/50V
R32
150Ohm RN36B
10KOhm
3 4
L105
120Ohm/100Mhz
21
R204
150_1
R817
124Ohm
R31
150Ohm
R205
150_1
C774
0.1UF/16V
R206
150_1
U54
PI5C3257QE
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
S
IA0
IA1
YA
IB0
IB1
YB
GND YC
IC1
IC0
YD
ID1
ID0
E#
VCC
C7110
0.1UF/16V
U55
PI5C3257QE
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
S
IA0
IA1
YA
IB0
IB1
YB
GND YC
IC1
IC0
YD
ID1
ID0
E#
VCC
R202
150_1
L104
120Ohm/100Mhz
21
C7109
0.1UF/16V
C7111
0.1UF/16V
R813
150Ohm
L106
120Ohm/100Mhz
21
R203
150_1
R815
150Ohm
U53
PI5C3257QE
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
S
IA0
IA1
YA
IB0
IB1
YB
GND YC
IC1
IC0
YD
ID1
ID0
E#
VCC
C773
4.7UF/6.3V
RN36C
10KOhm
5 6
C769
0.01UF/25V
U4D
C51MV
A5
B6
A6
B7
C7
D8
D9
C8
A9
H13
C9
B9
F12
E11
E17
F17
G17
R9
P9
H16
C14
B13
A15
D15
A14
F14
B15
C15
B14
E14
A10
B10
B11
E13
D13
B12
A11
F13
C13
C12
A16
F15
E16
H12
D17
C17
C18
B19
C19
B18
A19
DAC_RED
DAC_GREEN
DAC_BLUE
DAC_HSYNC
DAC_VSYNC
DAC_RSET
DAC_VREF
DAC_IDUMP
+3.3V_DAC
+2.5V_PLLGPU
XTAL_IN
XTAL_OUT
NC1/DDC_CLK
NC2/DDC_DATA
NC3/HPDET
NC4/EE_CLK
NC5/EE_DATA
+1.2V_PLLGPU
+1.2V_PLLCORE
+1.2V_PLLIFP
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD1_P
IFPA_TXD2_P
IFPA_TXD3_P
IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD5_P
IFPB_TXD6_P
IFPB_TXD7_P
IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N
IFPAB_VPROBE
IFPAB_RSET
+2.5V_PLLIFP
+2.5V_PLLCORE
PKG_TEST
TEST_MODE_EN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
R816
124Ohm_*
RN36A
10KOhm
1 2
RN36D
10KOhm
7 8
L107
120Ohm/100Mhz
21
R822
22KOhm_*
C780
0.1UF/16V
R51
0Ohm_*
1 2
R821
22KOhm_*
R824 22KOhm_*
12
C781
0.1UF/16V
R825
22KOhm_*
LVDS_YA2P_C51M 17
LVDS_YA1P_C51M 17
LVDS_YA0P_C51M 17
LVDS_YA2N_C51M 17
LVDS_YA1N_C51M 17
LVDS_YA0N_C51M 17
LVDS_YB2P_C51M 17
LVDS_YB1P_C51M 17
LVDS_YB0P_C51M 17
LVDS_YB0N_C51M 17
LVDS_YB1N_C51M 17
LVDS_YB2N_C51M 17
LVDS_CLKAN_C51M 17
LVDS_CLKAP_C51M 17
LVDS_CLKBN_C51M 17
LVDS_CLKBP_C51M 17
DAC_HSYNC_C51M18
DAC_VSYNC_C51M18
LOAD_TEST 22
MCP_TV_EN22
DAC_G_NV16
DAC_R_NV16
TV_CVBS_NV 16
TV_Y_NV16
DAC_B_NV 16
TV_CVBS 18
TV_C_NV16
TV_C18
TV_Y18
IGP_SELECT17,18,22
LCD_VDD_EN_NV 16
LCD_VDDEN_C51M 23
LCD_BACKEN_NV 16
LCD_BKLEN_C51M 23
LCD_BACKEN 17
LCD_VDD_EN 17
DAC_R_CRT18
DAC_G_CRT18
DAC_B_CRT 18
27MREF16
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
5.6A C51MV
3.5A C51M
200 mA
150 mA
370 mA
300 mA
260 mA
200 mA
100 mA
15 mA
C51M PWR/GND
2.1
A8T
15 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+1.2VS_NBCORE
+1.2VS_PED
+1.2VS_C51MHT
+1.2VS_HTMCP
+1.2VS_PEA
+1.2VS_PLL
+2.5VS_CORE
+1.8VS_IFPAB
+1.2VS_CORE
+1.2VS
+1.2VS_HT
+3VS
+1.2VS
+2.5VS
+1.8VS
C802
0.1UF/16V
C793
1UF/10V
C814
0.1UF/16V
C800
0.1UF/16V
C803
0.1UF/16V
C810
1UF/10V
C821
0.1UF/16V
C794
1UF/10V
L108
120Ohm/100Mhz
21
C804
0.1UF/16V
L109
120Ohm/100Mhz
21
U4E
C51MV
B5
C6
D7
E8
E9
E10
F10
F11
G11
H11
J11
J12
J13
J14
T15
U13
U11
Y9
AB11
AA18
W16
U16
U15
B4
C5
D6
E7
K16
M16
R16
M21
J20
T16
U17
C21
H17
D18
C10
A3
B3
C4
D5
E6
F7
F8
F9
A2
B2
C2
C3
D4
E5
F6
G7
G8
G9
H10
J10
C16
B16
G15
H15
+1.2V_CORE1
+1.2V_CORE2
+1.2V_CORE3
+1.2V_CORE4
+1.2V_CORE5
+1.2V_CORE6
+1.2V_CORE7
+1.2V_CORE8
+1.2V_CORE9
+1.2V_CORE10
+1.2V_CORE11
+1.2V_CORE12
+1.2V_CORE13
+1.2V_CORE14
+1.2V_HTMCP1
+1.2V_HTMCP2
+1.2V_HTMCP3
+1.2V_HTMCP4
+1.2V_HTMCP5
+1.2V_HTMCP6
+1.2V_HTMCP7
+1.2V_HTMCP8
+1.2V_HTMCP9
+1.2V_PED1
+1.2V_PED2
+1.2V_PED3
+1.2V_PED4
+1.2V_HT1
+1.2V_HT2
+1.2V_HT3
+1.2V_HT4
+1.2V_HT5
+1.2V_HT6
+1.2V_HT7
+1.2V_HT8
+1.2V_HT9
+3.3V_1
+3.3V_2
+1.2V_PEA1
+1.2V_PEA2
+1.2V_PEA3
+1.2V_PEA4
+1.2V_PEA5
+1.2V_PEA6
+1.2V_PEA7
+1.2V_PEA8
+1.2V_PLL1
+1.2V_PLL2
+1.2V_PLL3
+1.2V_PLL4
+1.2V_PLL5
+1.2V_PLL6
+1.2V_PLL7
+1.2V_PLL8
+1.2V_PLL9
+1.2V_PLL10
+1.2V_PLL11
+1.2V_PLL12
+2.5V_CORE_1
+2.5V_CORE_2
+2.5V_IFPA
+2.5V_IFPB
C807
0.1UF/16V
C813
0.1UF/16V
C792
0.1UF/16V
C798
1UF/10V
R832 0Ohm
1 2
C812
1UF/10V
C819
0.1UF/16V
C815
0.1UF/16V
C822
0.1UF/16V
C817
47UF/6.3V
C786
1UF/10V
C826
0.1UF/16V
C825
0.1UF/16V
C799
1UF/10V
C828
1UF/10V
C801
0.1UF/16V
C823
1UF/10V
C827
0.1UF/16V
C783
22UF/6.3V
C816
0.1UF/16V
R831 0Ohm
1 2
C824
0.1UF/16V
C789
0.1UF/16V
L110
120Ohm/100Mhz
21
C791
0.1UF/16V
U4F
C51MV
C1
AA21
AA13
U14
H14
C11
AB4
AA4
J15
E12
AB10
Y18
E18
U18
E15
Y11
U19
N17
F16
J17
L13
B1
T17
D11
T12
J16
D19
H19
L21
M19
P19
T19
L14
F3
L9
P8
N9
K4
N4
T4
W4
Y4
U9
H9
V19
T14
C20
R17
AB14
U12
G13
Y16
H21
C22
AB6
F22
L22
R22
V22
AA22
A23
AA23
AA24
L11
M11
N11
P11
M12
N12
P12
M13
N13
P13
M14
N14
P14
L12
K6
M6
P6
T6
W6
W8
H8
K8
V6
F4
V8
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
PE_GND1
PE_GND2
PE_GND3
PE_GND4
PE_GND5
PE_GND6
PE_GND7
PE_GND8
PE_GND9
PE_GND10
PE_GND11
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
PE_GND12
PE_GND13
PE_GND14
PE_GND15
PE_GND16
PE_GND17
PE_GND18
PE_GND19
PE_GND20
PE_GND21
PE_GND22
C790
0.1UF/16V
C797
1UF/10V
C788
1UF/10V
C784
22UF/6.3V
C805
0.1UF/16V
R833 0Ohm
1 2
C806
0.1UF/16V
C809
47UF/6.3V
C811
1UF/10V
C795
22UF/6.3V
C785
1UF/10V
R834 0Ohm
1 2
C808
4.7U/6.3V
C787
1UF/10V
C796
22UF/6.3V
C818
0.1UF/16V
C820
0.1UF/16V
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Polarity Inversion:
PEXP_TXP0, 1, 2, 4, 5,
6, 8, 14
VGA CONN
2.1
A8T
16 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PEXP_TXP10#
PEXP_TXP7
PEXP_TXP7#
PEXP_TXP9
PEXP_TXP12#
PEXP_TXP12
PEXP_TXP3
PEXP_TXP9#
PEXP_TXP11
PEXP_TXP11#
PEXP_TXP3#
PEXP_TXP13
PEXP_TXP10
PEXP_TXP13#
PE_RST#
HDTV_EN#
CLK_VGA27SS
CLK_VGA27FIX
PEX_RST#
PEX_RST#
PEXP_TXP0#
PEXP_TXP0
PEXP_TXP1#
PEXP_TXP1
PEXP_TXP2#
PEXP_TXP2
PEXP_TXP4#
PEXP_TXP4
PEXP_TXP5
PEXP_TXP5#
PEXP_TXP6
PEXP_TXP6#
PEXP_TXP8#
PEXP_TXP8
PEXP_TXP14
PEXP_TXP14#
CLK_VGA27SS
CLK_VGA27FIX
SSCLK
REFCLK
27M_X227M_X1
PEXP_TXP15
PEXP_TXP15#
+3VS
+1.5VS_VG
+2.5VS
AC_BAT_SYS
+5V
+12VS
+1.8VS
+1.5VS
+1.8VS
+3VS
+12VS
+2.5VS
+5V
+0.9VS
+3VS
+3VS
+
C201
15UF/25V
R100
100K_*
C206
10U/10V
C38
18PF/50V_*
C211
10U/10V
R42
22Ohm_*
1 2
C215 0.1U/10V
C197 0.1U/10V
C220 0.1U/10V
C204 0.1U/10V
CON3B GF_VGA_230P
31
32
37
38
43
44
55
56
59
63
67
70
73
74
78
79
82
85
88
91
94
97
100
103
106
112
113
119
120
125
126
131
132
137
138
143
144
149
150
155
156
161
162
167
168
173
174
179
180
185
186
191
192
197198
203
204
209
210
215
216
219
220
218
217
25
6
8
10
12
14
18
17
19
21
1
3
5
7
9
11
13
15
2
16
20
22
23
52
53
54
51
4
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
1V8RUN_3
1V8RUN_4
1V8RUN_5
1V8RUN_6
1V8RUN_7
5VRUN
3V3RUN_1
3V3RUN_2
3V3RUN_3
PWR_SRC1
PWR_SRC2
PWR_SRC3
PWR_SRC4
PWR_SRC5
PWR_SRC6
PWR_SRC7
PWR_SRC8
1V8RUN_1
2V5RUN
RSVD1
RSVD2
RSVD3
RSVD4
AC/BATT#
RSVD5
RSVD6
1V8RUN_2
C221 0.1U/10V
C205 0.1U/10V
PEX
DVI
VGA
LVDS
IGP
TV-OUT
SMBUS OTHER
CON3A GF_VGA_230P
225
226
58
60
66
68
46
48
50
49
28
34
40
30
36
42
118
115
117
24
111
109
72
80
76
121
133
127
139
145
151
157
163
169
175
181
187
193
199
205
211
123
129
135
141
147
153
159
165
171
177
183
189
195
201
207
213
214
208
202
196
190
184
178
172
166
160
154
148
142
136
130
212
206
200
194
188
182
176
170
164
158
152
122
124
128
134
140
146
71
57
69
61
65
75
77
87
93
83
105
89
95
81
107
99
101
114
86
92
98
108
84
90
96
110
102
104
223
230
224
221
228
222
229
227
39
33
27
41
35
29
45
47
64
62
116
26
PRSNT1#
PRSNT2#
DDCA_CLK
DDCA_DAT
DDCB_CLK
DDCB_DAT
DVI_A_CLK
DVI_A_CLK#
DVI_A_HPD
DVI_B_HPD/GND
DVI_A_TX0
DVI_A_TX1
DVI_A_TX2
DVI_A_TX0#
DVI_A_TX1#
DVI_A_TX2#
PEX_RST#
PEX_REFCLK
PEX_REFCLK#
THERM#
SMB_DAT
SMB_CLK
TV_Y/HDTV_Y/TV_CVBS
TV_CVBS/HDTV_Pb
TV_C/HDTV_Pr
PEX_TX0
PEX_TX2
PEX_TX1
PEX_TX3
PEX_TX4
PEX_TX5
PEX_TX6
PEX_TX7
PEX_TX8
PEX_TX9
PEX_TX10
PEX_TX11
PEX_TX12
PEX_TX13
PEX_TX14
PEX_TX15
PEX_TX0#
PEX_TX1#
PEX_TX2#
PEX_TX3#
PEX_TX4#
PEX_TX5#
PEX_TX6#
PEX_TX7#
PEX_TX8#
PEX_TX9#
PEX_TX10#
PEX_TX11#
PEX_TX12#
PEX_TX13#
PEX_TX14#
PEX_TX15#
PEX_RX15#
PEX_RX14#
PEX_RX13#
PEX_RX12#
PEX_RX11#
PEX_RX10#
PEX_RX9#
PEX_RX8#
PEX_RX7#
PEX_RX6#
PEX_RX5#
PEX_RX4#
PEX_RX3#
PEX_RX2#
PEX_RX1#
PEX_RX15
PEX_RX14
PEX_RX13
PEX_RX12
PEX_RX11
PEX_RX10
PEX_RX9
PEX_RX8
PEX_RX7
PEX_RX6
PEX_RX5
PEX_RX0
PEX_RX0#
PEX_RX1
PEX_RX2
PEX_RX3
PEX_RX4
VGA_VSYNC
VGA_RED
VGA_HSYNC
VGA_GRN
VGA_BLU
LVDS_LCLK#
LVDS_LCLK
LVDS_LTX0
LVDS_LTX1
LVDS_LTX2
LVDS_LTX3
LVDS_LTX0#
LVDS_LTX1#
LVDS_LTX2#
LVDS_LTX3#
LVDS_PPEN
LVDS_BLEN
LVDS_BL_BRGHT
LVDS_UTX0
LVDS_UTX1
LVDS_UTX2
LVDS_UTX3
LVDS_UTX0#
LVDS_UTX1#
LVDS_UTX2#
LVDS_UTX3#
LVDS_UCLK
LVDS_UCLK#
IGP_UTX2#
IGP_UTX1#
IGP_UTX0#
IGP_UTX2
IGP_UTX1
IGP_UTX0
IGP_UCLK#
IGP_UCLK
IGP_LTX2/DVI_B_TX2
IGP_LTX1/DVI_B_TX1
IGP_LTX0/DVI_B_TX0
IGP_LTX2#/DVI_B_TX2#
IGP_LTX1#/DVI_B_TX1#
IGP_LTX0#/DVI_B_TX0#
IGP_LCLK/DVI_B_CLK
IGP_LCLK#/DVI_B_CLK#
DDCC_DAT
DDCC_CLK
CLK_REQ#
RUNPWROK
C227 0.1U/10V
C212 0.1U/10V
R7139 0Ohm_*
1 2
C196 0.1U/10V
C194 0.1U/10V
C226 0.1U/10V
C213 0.1U/10V
C195 0.1U/10V
C218 0.1U/10V
C203 0.1U/10V
R44
22Ohm_*
1 2
C219 0.1U/10V
C202 0.1U/10V
C225 0.1U/10V
C209 0.1U/10V
R101 0Ohm
1 2
L1
120Ohm/100Mhz_*
21
C224 0.1U/10V
1 2
X2
27Mhz
C210 0.1U/10V
C216 0.1U/10V
C200 0.1U/10V
C40
0.1UF/16V_*
C217 0.1U/10V
C199 0.1U/10V
C39
18PF/50V_*
C222 0.1U/10V
C207 0.1U/10V
R7138 0Ohm
1 2
C193 0.1U/10V
R41
22Ohm_*
1 2
G
S
D3
2
1
Q116
2N7002_*
R43
10KOhm_*
C223 0.1U/10V
U42
MK1726_08STR
1
2
3
4 5
6
7
8
X1/ICLK
GND
S0
SSCLK REFCLK
PD#
VDD
X2
C208 0.1U/10V
C214 0.1U/10V
C198 0.1U/10V
DAC_G_NV14
DAC_R_NV14
DAC_B_NV14
DAC_VSYNC_NV18
DAC_HSYNC_NV18
TV_Y_NV14
TV_C_NV14
TV_CVBS_NV14
CLK_PCIE_VGA# 13
CLK_PCIE_VGA 13
PE_RST# 13,30
DDC2BD_NV18
EDID_DATA_NV17
EDID_CLK_NV17
SDA_3S5,29
SCL_3S5,29
SUSB#_PWR47,67
VGA_DETECT# 13,20
EXP_RXP6 13
EXP_RXN6 13
EXP_RXP12 13
EXP_RXN8 13
EXP_RXP15 13
EXP_RXN2 13
EXP_RXP1 13
EXP_RXP4 13
EXP_TXN13 13
EXP_TXN7 13
EXP_TXP7 13
EXP_TXN12 13
EXP_RXN5 13
EXP_RXP11 13
EXP_RXP7 13
EXP_RXN4 13
EXP_RXN1 13
EXP_RXN0 13
EXP_RXN9 13
EXP_TXP9 13
EXP_RXN10 13
EXP_TXP3 13
EXP_TXP12 13
EXP_RXP0 13
EXP_RXN7 13
EXP_RXN12 13
EXP_RXN14 13
EXP_RXN3 13
EXP_RXP9 13
EXP_RXN13 13
EXP_RXP5 13
EXP_RXP8 13
EXP_RXP14 13
EXP_TXP13 13
EXP_TXP11 13
EXP_RXP2 13
EXP_RXP3 13
EXP_TXN3 13
EXP_TXN9 13
EXP_TXN11 13
EXP_RXP13 13
EXP_TXP10 13
EXP_RXP10 13
EXP_TXN10 13
EXP_RXN11 13
EXP_RXN15 13
VGA_PWRGD 20,70
DVI_TX0P_NV39
DVI_TX0N_NV39
DVI_TX1N_NV39
DVI_TX1P_NV39
DVI_CLKP_NV39
DVI_TX2N_NV39
DVI_CLKN_NV39
DVI_TX2P_NV39
DDC2BC_NV18
DVI_DDCCLK_NV39
DVI_DDCDAT_NV39
DVI_TX4P_NV39
DVI_TX5P_NV39
DVI_TX3N_NV39
DVI_TX5N_NV39
DVI_TX4N_NV39
DVI_TX3P_NV39
+1.8VS 5,15,17,48
+1.5VS 19,21,22,23,30,31,38,48
+3VS 5,8,9,13,14,15,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+12VS 17
+2.5VS 5,11,14,15,18,38,48
+5V 9,18,25,28,31,38,40,41
LCD_BACKEN_NV14
LCD_VDD_EN_NV14
LVDS_YB0P_NV17
LVDS_CLKBN_NV17
LVDS_YB1P_NV17
LVDS_CLKBP_NV17
LVDS_YB2N_NV17
LVDS_YB1N_NV17
LVDS_YB2P_NV17
LVDS_YB0N_NV17
LVDS_YA2P_NV17
LVDS_CLKAN_NV17
LVDS_CLKAP_NV17
LVDS_YA0P_NV17
LVDS_YA1P_NV17
LVDS_YA0N_NV17
LVDS_YA2N_NV17
LVDS_YA1N_NV17
DVI_HDP_NV39
MXM_PWR_ON20
HDTV_EN#18
GPU_ON 13,20
EXP_TXP0 13
EXP_TXN0 13
EXP_TXP1 13
EXP_TXN1 13
EXP_TXP2 13
EXP_TXN2 13
EXP_TXN4 13
EXP_TXP4 13
EXP_TXN5 13
EXP_TXP5 13
EXP_TXP6 13
EXP_TXN6 13
EXP_TXN8 13
EXP_TXP8 13
EXP_TXP14 13
EXP_TXN14 13
27MREF14EXP_TXP15 13
EXP_TXN15 13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
INVERTOR
CNT
FootPrinter from 12-172010300
LVDS A Channel SLI MUX
EDID SLI MUX
LVDS B Channel SLI MUX
Vref=1.215V
LVDS,INVERTER CONN
2.1
A8T
17 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
EDID_DATAEDID_CLK
LVDS_CLKAN
LVDS_YA2P
LVDS_YA0N
LVDS_CLKAP
LVDS_YA1P
LVDS_YA1N
LVDS_YA0P
LVDS_YA2N
LVDS_CLKBP
LVDS_CLKBN
LVDS_YB0P
LVDS_YB1N
LVDS_YB2P
LVDS_YB0N
LVDS_YB2N
LVDS_YB1P
LVDS_CLKAP
LVDS_CLKAN
LVDS_YA1N
LVDS_YA0P
LVDS_YA2N
LVDS_YA1P
LVDS_YA0N
LVDS_YA2P
IGP_SELECT
+LCD_VCC
EDID_CLK
EDID_DATA
IGP_SELECT
LVDS_YB1P
LVDS_YB1N
LVDS_YB2N
LVDS_YB0N
LVDS_CLKBN
LVDS_YB2P
LVDS_YB0P
LVDS_CLKBP
+3VS
AC_BAT_SYS
+3VSUS +12VS +3VS
+LCD_VCC
+LCD_VCC
+3VS
+LCD_VCC
+LCD_VCC
+3VS
+3VS
+3VSUS
+12VS
+1.8V
+1.8_2.1VS
+3VS
+3VS
+3VS
+1.8_2.1VS
+3VS
+2.1VS
+1.8_2.1VS
+1.8VS
S
D
G
Q5
PMN45EN
1
2
3
5
6
4
C229
100P
U57A
PI2PCIE412E_*
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1722
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38 GND1
A0
A1
GND2
VDD1
A2
A3
VDD2
SEL
GND3
A4
A5
VDD3
GND4
A6
A7
GND57B2
6B2
5B2
4B2
7B1
6B1
5B1
4B1
VDD6
3B2
2B2
1B2
0B2
3B1
2B1
1B1
0B1
C233
0.1U
CON5
Inverter_CON
1
2
3
4
5
6
7
8
9
VCC1
VCC2
GND1
GND2
VREF
BKEN
PWM
8
9
Q112A
UM6K1N
6 1
CON4 LVDS_CON
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
U56B
PI2PCIE412E
44
45
46
47
GND11
GND12
GND13
GND14
L16 1K/300mA
Q112B
UM6K1N
3 4
R7120
47K
GS
D
3
2
1
Q111
2N7002
L14 80/2A
R192
10K
C238
10U/10V
R35
47KOhm
R189
10K
R198
10K
C231
0.1U/X7R
C232
0.1U
D2 F01J4L
12
C237
0.1UQ8A
UM6K1N
2
Q8B
UM6K1N
5
L15 1K/300mA
R7117
2.7K
Q110A
UM6K1N
6 1
R194 100K
U56A
PI2PCIE412E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1722
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38 GND1
A0
A1
GND2
VDD1
A2
A3
VDD2
SEL
GND3
A4
A5
VDD3
GND4
A6
A7
GND57B2
6B2
5B2
4B2
7B1
6B1
5B1
4B1
VDD6
3B2
2B2
1B2
0B2
3B1
2B1
1B1
0B1
R26
10K
R195 470K
R7122
2.7K
R7121
2.7K
R36
34KOhm
1 2
C239
10U/10V
L17 80/2A
C230
100P
Q4
2N7002
C235
0.1U/X7R
U57B
PI2PCIE412E_*
44
45
46
47
GND11
GND12
GND13
GND14
D11 RB717F
1
2
3
R188
10K
C14
4.7U/6.3V
R193
1M
R37 0Ohm
1 2
C228
0.1U
R7116
2.7K
C234
1000P
D1
1SS355
1 2
C15
1UF/16V
R736 100
U31
SI9183DT
1
2
3
4
5
VIN
GND
SD#
FB
VOUT
Q110B
UM6K1N
3 4
R38 0Ohm_*
1 2
C236
0.1U
ADJ_BL28
LCD_VDD_EN14
EDID_DATA_NV16
EDID_CLK_NV16
LID_SW#41,42
LCD_BACKEN14
BACK_OFF#20
+3VS 5,8,9,13,14,15,16,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+3VSUS 5,20,22,23,28,29,32,42,46,48,70
+12VS 16
+1.8V 5,7,8,9,10,38,65
LVDS_YA0N_C51M14
LVDS_YA0P_C51M14
LVDS_YA1N_NV16
LVDS_YA0P_NV16
LVDS_YA1P_C51M14
LVDS_YA0N_NV16
LVDS_YA1P_NV16
LVDS_YA1N_C51M14
IGP_SELECT 14,18,22
EDID_CLK_C51M22
EDID_DATA_C51M22
IGP_DDC_SELECT18,22
LVDS_CLKAP_NV16
LVDS_CLKAN_C51M14
LVDS_YA2P_C51M14
LVDS_YA2N_C51M14
LVDS_YA2N_NV16
LVDS_CLKAP_C51M14
LVDS_CLKAN_NV16
LVDS_YA2P_NV16
NV_DDC_EN18
LVDS_YB1N_NV16
LVDS_CLKBN_NV16
LVDS_YB0N_NV16
LVDS_YB0P_C51M14
LVDS_YB1N_C51M14
LVDS_CLKBN_C51M14
LVDS_YB2N_C51M14
LVDS_YB2P_C51M14
LVDS_CLKBP_C51M14
LVDS_YB1P_C51M14
LVDS_YB0N_C51M14
LVDS_YB2N_NV16
LVDS_CLKBP_NV16
LVDS_YB2P_NV16
LVDS_YB0P_NV16
LVDS_YB1P_NV16
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
H,VSYNC SLI MUX
DDC MUX Between C51 & G7X
CRT & TV OUT
2.1
A8T
18 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
TV_Y
TV_CVBS
DDC2BD
HSYNC
VSYNC
DDC2BC
BLUEDAC_B_CRT
TV_C
TV_C
CVBS_CON
Y_CON
C_CON
DDC2BD
HSYNC
VSYNC
DDC2BC
GREEN
RED
GREEN
BLUE
RED
TV_Y
TV_CVBS
DAC_R_CRT
IGP_SELECT#
IGP_SELECT#
IGP_SELECT#
IGP_SELECT
IGP_SELECT
DAC_G_CRT
HSYNC_CRT
DDC2BD_5
HSYNC_CRT
VSYNC_CRT
VSYNC_CRT
DDC2BC_5
DDC2BD_5
DDC2BC_5
+2.5VS
+3VS
+5V
+3VS
+2.5VS
+5V
+5VS
+3VS
+3VS
+5VS
+3VS
+5V
+5V
+5V
+5V
C240
0.1U
Q113B
UM6K1N
3 4
GS
D
3
2
1
Q115
2N7002
D4
BAV99_*
L20 0.068U/300mA
R828
2.2KOhm
C245
8.2P
L19 0.068U/300mA
R7131
47K
RN43A
2.2kOhm
1 2
C254
82P
D5
BAV99_*
L24 1.8U/50mA
C249
10P
L23 1.8U/50mA
RN43B
2.2kOhm
3 4
L22 120/400mA
R200 33_0603
C248
10P
RN43C
2.2kOhm
5 6
L25 1.8U/50mA
C242
8.2P
VCC
GND
U58A
SN74HCT125DR
2 3
L18 0.068U/300mA
C243
8.2P
C247
82P
D8 BAV99_*
1
2
3
RN43D
2.2kOhm
7 8
C250
82P
R829
2.2KOhm
D3
BAV99_*
C244
8.2P
Q114A
UM6K1N
6 1
D_SUB_15P3R
CON6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
VCC
GND
U58B
SN74HCT125DR
5 6
Q113A
UM6K1N
6 1
C252
82P
L21 120/400mA
C251
82P
R46 0Ohm_*
1 2
C255
82P
D9 BAV99_*
1
2
3
Q114B
UM6K1N
3 4
VCC
GND
U58C
SN74HCT125DR
9 8
C246
8.2P
D6
1SS355
1 2
C256
82P
C253
82P
CON7
MINI_DIN_7P
1
2
3
4
5
6
7
GND0
CVBS1
GND1
Y
NC
C
CVBS2
R199 33_0603
D7 BAV99_*
1
2
3
VCC
GND
U58D
SN74HCT125DR
12 11
C241
8.2P
DDC2BC_NV16
DDC2BD_NV16
+3VS 5,8,9,13,14,15,16,17,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+2.5VS 5,11,14,15,16,38,48
+5V 9,16,25,28,31,38,40,41
+5VS 14,23,24,28,29,36,37,38,39,40,41,61
DDC2BD_C51M22
DDC2BC_C51M22
IGP_DDC_SELECT17,22
NV_DDC_EN17
DAC_VSYNC_NV16
DAC_VSYNC_C51M14
DAC_HSYNC_C51M14
IGP_SELECT14,17,22
TV_C14
TV_Y14
TV_CVBS14
DAC_HSYNC_NV16
DAC_G_CRT14
DAC_R_CRT14
DAC_B_CRT14
HDTV_EN#16
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
150 mA
20 mA
MCP51 HT I/F
2.1
A8T
19 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
HTMCP_RXDN1
HTMCP_RXDP3
HTMCP_RXDN3
HTMCP_RXDN0
HTMCP_RXDP1
HTMCP_RXDN2
HTMCP_RXDP2
HTMCP_RXDP0
HTMCP_TXDN3
HTMCP_TXDN2
HTMCP_TXDP0
HTMCP_TXDN1
HTMCP_TXDN0
HTMCP_TXDP3
HTMCP_TXDP1
HTMCP_TXDP2
HTMCP_REQ#
HTMCP_STP#
HTMCP_COMP_GND1
HTMCP_COMP_GND2
VDLT_PWRGD
VCORE_PWRGD
VDDIO_PWRGD
+3VS_PLL_CPUHT
HTMCP_RST#
HTMCP_PWRGD
HTMCP_TXDP7
HTMCP_TXDN7
HTMCP_TXDP4
HTMCP_TXDP5
HTMCP_TXDP6
HTMCP_TXDN4
HTMCP_TXDN5
HTMCP_TXDN6
HTMCP_RXDP4
HTMCP_RXDP5
HTMCP_RXDP6
HTMCP_RXDP7
HTMCP_RXDN4
HTMCP_RXDN5
HTMCP_RXDN6
HTMCP_RXDN7
HTVDD_EN
+3VS
+3VS
+1.5VS +3VS
C831
0.1UF/16V
RN1A
10KOhm
1 2
R841 976Ohm
12
RN1B
10KOhm
3 4
C829
0.1UF/16V
RN1C
10KOhm
5 6
R849
1.5KOhm
U3A
MCP51
K1
L1
M1
N1
R1
T1
U1
V1
K2
L2
M2
N2
R2
T2
U2
V2
P1
P2
W1
W2
AD1
AA5
AB1
AB2
F22
N26
M24
F23
N25
M6
M5
AA1
Y1
AA3
W5
U5
T5
R5
P5
AA2
Y2
AA4
W6
U6
T6
R6
P6
V5
V6
N5
N6
AC2
AC1
Y5
AD2
AE1
J6
K6
H22
H21
H23
D26
F25
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RX_CLK_P
HT_MCP_RX_CLK_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ#
HT_MCP_STOP#
HT_MCP_COMP_GND1
HT_MCP_COMP_GND2
HT_VLD
CPU_VLD
MEM_VLD
HTVDD_EN
CPUVDD_EN
+1.5V_PLL_CPU_HT
+3.3V_PLL_CPU_HT
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TX_CLK_P
HT_MCP_TX_CLK_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_200MHZ_N
CLKOUT_200MHZ_P
CLKOUT_25MHZ
HT_MCP_PWRGD
HT_MCP_RST#
THERMTRIP#/GPIO_58
CLK200_TERM_GND
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
R840 49.9Ohm
1 2
RN1D
10KOhm
7 8
C7112
0.1UF/16V_* L111
120Ohm/100Mhz
21
C830
0.1UF/16V
R850
1.5KOhm
R839 22Ohm
1 2
R838 150Ohm
1 2
C4
10uF/10V
R848
1.5KOhm
R843 0Ohm
1 2
R7134 0Ohm
1 2
R851
1.5KOhm
C5
0.01UF/25V
HTMCP_TXDP[0..7]12
HTMCP_TXDN[0..7]12 HTMCP_RXDN[0..7] 12
HTMCP_RXDP[0..7] 12
HTMCP_TXCTL#12
HTMCP_TXCTL12 HTMCP_RXCTL 12
HTMCP_RXCTL# 12
HTMCP_RXCLK0# 12
HTMCP_RXCLK0 12HTMCP_TXCLK012
HTMCP_TXCLK0#12
CLK_NBHT# 12
CLK_NBHT 12
CLK_25M 12
HTMCP_PWRGD 12
HTMCP_RST# 12
HTMCP_REQ#12
HTMCP_STP#12
HT_VLD48
CPUPWR_GD61,70
MEM_VLD48
HTVDD_EN67
CPU_VRON61
CPU_THRMTRIP# 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MCP51 PCI
2.1
A8T
20 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PCI_PERR#
PCI_AD18
PCI_AD25
PCI_AD12
PCI_AD6
PCI_IRDY#
PCI_AD22
PCI_AD17
PCI_AD30
PCI_AD9
PCI_AD11
PCI_PAR
PCI_AD5
PCI_AD21
PCI_AD16
PCI_AD8
PCI_FRAME#
PCI_C/BE#3
PCI_AD10
PCI_AD4
PCI_AD[0..31]
PCI_AD29
PCI_AD31
PCI_AD15
PM_CLKRUN#
PCI_AD3
PCI_C/BE#2
PCI_AD14
PCI_AD28
PCI_DEVSEL#
PCI_AD2
PCI_PME#
PCI_AD0
PCI_AD1
PCI_AD20
PCI_AD27
PCI_C/BE#1
PCI_STOP#
PCI_AD24
PCI_SERR#
PCI_C/BE#0
PCI_AD19
PCI_AD26
PCI_C/BE#[0..3]
PCI_TRDY#
PCI_AD23
PCI_AD13
PCI_AD7
PCI_CLKIN
LPC_AD0
PCI_REQ#0
LPC_DRQ#0
PCI_GNT#1
LPC_DRQ#1
LPC_FRAME#
PCI_INTB#
LPC_CLK1
PCI_GNT#0
PCI_CLK1
LPC_AD3
PCI_INTA#
LPC_CLK0
LPC_AD2
PCI_CLK0
PCI_CLK4
LPC_AD1
PCI_REQ#1
PCI_INTC#
PCI_INTD#
PCI_REQ#2
PCI_INTA#
PCI_TRDY#
PCI_STOP#
PCI_PERR#
PCI_DEVSEL#
PCI_REQ#1
PCI_IRDY#
PCI_SERR#
PCI_INTB#
PCI_REQ#0
PCI_INTD#
PCI_INTC#
PCI_FRAME#
PCI_REQ#2
PCI_PME#
GPU_ON
PCI_CLK2
MXM_PWR_ON
PM_CLKRUN#
MXM_PWR_ON
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
LPC_DRQ#0
LPC_DRQ#1
INT_SERIRQ
BACK_OFF#
+3VS
+3VSUS
RN44A
8.2KOHM
1 2
RP6E 8.2K
6 5
10
R866 33Ohm
1 2
C833
10PF/50V
_*
RN12D
8.2KOHM
7 8
RP7G 8.2K
8 5
10
RN44D
8.2KOHM
7 8
R859 33Ohm
1 2
R102 0Ohm_*
1 2
R7142 33Ohm
1 2
R865 22Ohm
1 2
R852 22Ohm
1 2
RP7E 8.2K
6 5
10
RN44C
8.2KOHM
5 6
C835
10PF/50V
_*
RP6D 8.2K
4 5
10
RN44B
8.2KOHM
3 4
RP7F 8.2K
7 5
10
R858 10K
RP6H 8.2K
9 5
10
RP7D 8.2K
4 5
10
C834
10PF/50V
_*
C832
10PF/50V
_*
RP6C 8.2K
3 5
10
C7108
10PF/50V
_*
RP7H 8.2K
9 5
10
RP6F 8.2K
7 5
10
R862 22Ohm
1 2
R7143 33Ohm
1 2
R857 33Ohm
1 2
RP7C 8.2K
3 5
10
C836
10PF/50V
_*
R854 22Ohm
1 2
R867 8.2KOhm
12
RN12A
8.2KOHM
1 2
R103 0Ohm
1 2
R7144 33Ohm
1 2
U3B
MCP51
AF19
AB21
AC19
AA20
AA19
AF20
AE19
AE20
AB20
AB19
AA18
AB18
AE18
AF18
AC17
AA17
AB15
AF15
AE15
AF14
AE14
AA14
AB14
AC13
AB13
AE13
AA12
AF13
AB12
AF12
AE12
AF11
AD19
AB17
AA15
AA13
AC15
AD15
AB16
AE16
AA16
AE17
AF16
AF17
AD11
AF25
AE25
AD24
AE26
W22
L26
AA22
AE22
AF21
AF22
AE23
AE21
AC21
AA21
AB24
AB22
AE11
AB11
AC11
AA11
AE24
AF24
AD23
AF23
AB23
AC23
K24
H26
H25
K22
G25
K21
K23
L22
H24
F26
G26
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_PAR
PCI_PERR#/GPIO_43
PCI_SERR#
PCI_PME#/GPIO_30
PCI_CLKRUN#/GPIO_42
PCI_RESET0#
PCI_RESET1#
PCI_RESET2#
PCI_RESET3#
LPC_RESET#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#/GPIO_38
PCI_REQ4#/GPIO_40
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#/GPIO_39
PCI_GNT4#/GPIO_41
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCI_CLKIN
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
LPC_CS#/LPC_DRQ1#
LPC_SERIRQ
LPC_PWRDWN#/GPIO_54
LPC_CLK0
LPC_CLK1
RP7B 8.2K
2 5
10
RP6G 8.2K
8 5
10
R30
10K
RN12B
8.2KOHM
3 4
RP6A 8.2K
1 5
10
R7115 22Ohm
1 2
T245
1
R860 22Ohm
1 2
RP7A 8.2K
1 5
10
R864 33Ohm
1 2
R853 22Ohm
1 2
RP6B 8.2K
2 5
10
R7112 33Ohm
1 2
RN12C
8.2KOHM
5 6
LPCSIO_RST#26
PCI_PERR#32,34
PCI_SERR#32,34
PCI_C/BE#[0..3]32,34
PCI_AD[0..31]32,34
PCIRST_CB#34
PCI_PME#32,34
PCI_PAR32,34
PCIRST_LAN#32
PCI_IRDY#32,34
PCI_TRDY#32,34
PCI_DEVSEL#32,34
PCI_STOP#32,34
PCI_FRAME#32,34
PM_CLKRUN#26,28,34,38
PCI_INTA# 34
PCI_GNT#0 34
PCI_INTB# 34
CLK_LANPCI 32
PCI_REQ#0 34
LPC_DRQ#0 26
CLK_CBPCI 34
CLK_FWHPCI 27
CLK_SIOPCI 26,31
CLK_KBCPCI 28
PCI_REQ#1 32
PCI_INTC# 32
LPC_AD3 26,27,28,31,38
LPC_AD2 26,27,28,31,38
LPC_AD1 26,27,28,31,38
LPC_AD0 26,27,28,31,38
INT_SERIRQ 26,28,34,38
LPC_FRAME# 26,27,28,31,38
IDE_RST#24
PCI_GNT#1 32
BACK_OFF# 17
PCIRST_NEWC#5,31
CLK_TPMPCI 38
MXM_PWR_ON 16
GPU_ON 13,16
LPCFWH_RST#27
LPCKBC_RST#28
LPCTPM_RST#38
VGA_PWRGD 16,70
VGA_DETECT# 13,16
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
180 mA
12 mA
MCP51 IDE
2.1
A8T
21 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
IDE_SDD7
IDE_PDD4
IDE_SDD2
IDE_PDD14
IDE_SDD15
IDE_SDD10
IDE_COMP_GND
IDE_PDD15
IDE_SDD6
IDE_PDD1
IDE_SDD1
IDE_COMP_3P3V
IDE_PDD6
IDE_SDD14
IDE_PDD9
IDE_PDD3
IDE_SDD9
IDE_SDD5
IDE_SDD0
IDE_PDD11
IDE_PDD13
IDE_SDD13
IDE_SDD8
IDE_PDD12
IDE_SDD4
IDE_PDD8
IDE_PDD7
IDE_PDD2
IDE_SDD12
IDE_PDD10
IDE_SDD3
IDE_PDD0
IDE_SDD[15..0]
IDE_PDD[15..0]
IDE_PDD5
IDE_SDD11
+1.5VS_PLL_SP_VDD
SATA_TSTCLK
+3VS
+3VS
+1.5VS
+3VS_PLL_SP_SS
R871 121Ohm
1 2
C838
10uF/10V
T7127
R869 2.49KOhm
1 2
C843
0.01UF/25V
C839
0.01UF/25V
C844
0.1UF/16V
C840
0.1UF/16V
R941 0_*
R868 100Ohm_*
1 2
R274 0_*
L112
120Ohm/100Mhz
21
C841
0.1UF/16V
U3C
MCP51
B20
A20
A19
B19
B18
A18
A17
B17
B15
A15
A16
B16
B13
A13
A14
B14
C20
D14
E13
F13
F14
E14
F18
F19
D20
F8
D8
A9
E9
A10
E10
C10
E11
F11
D10
F10
B10
F9
B9
E8
A8
A6
D6
B6
A5
B5
B7
F7
E6
B8
E7
A7
C6
E4
D1
D4
C2
B2
C3
A3
A4
B4
B3
A2
B1
C1
D2
E3
E5
G4
G6
G2
G1
G3
F5
E1
F6
E2
F2
F1
G5
B11
A11
SATA_A0_TX_P
SATA_A0_TX_N
SATA_A0_RX_N
SATA_A0_RX_P
SATA_A1_TX_P
SATA_A1_TX_N
SATA_A1_RX_N
SATA_A1_RX_P
SATA_B0_TX_P
SATA_B0_TX_N
SATA_B0_RX_N
SATA_B0_RX_P
SATA_B1_TX_P
SATA_B1_TX_N
SATA_B1_RX_N
SATA_B1_RX_P
SATA_LED#/GPIO_57
SATA_TSTCLK_P
SATA_GND
SATA_TEST
SATA_TERMP
SATA_TERMN
+1.5V_PLL_SP_VDD
+1.5V_PLL_SP_SS
+3.3V_PLL_SP_SS
IDE_DATA_P0
IDE_DATA_P1
IDE_DATA_P2
IDE_DATA_P3
IDE_DATA_P4
IDE_DATA_P5
IDE_DATA_P6
IDE_DATA_P7
IDE_DATA_P8
IDE_DATA_P9
IDE_DATA_P10
IDE_DATA_P11
IDE_DATA_P12
IDE_DATA_P13
IDE_DATA_P14
IDE_DATA_P15
IDE_ADDR_P0
IDE_ADDR_P1
IDE_ADDR_P2
IDE_CS1_P#
IDE_CS3_P#
IDE_DACK_P#
IDE_IOW_P#
IDE_INTR_P
IDE_DREQ_P
IDE_IOR_P#
IDE_RDY_P
CABLE_DET_P/GPIO_63
IDE_DATA_S0
IDE_DATA_S1
IDE_DATA_S2
IDE_DATA_S3
IDE_DATA_S4
IDE_DATA_S5
IDE_DATA_S6
IDE_DATA_S7
IDE_DATA_S8
IDE_DATA_S9
IDE_DATA_S10
IDE_DATA_S11
IDE_DATA_S12
IDE_DATA_S13
IDE_DATA_S14
IDE_DATA_S15
IDE_ADDR_S0
IDE_ADDR_S1
IDE_ADDR_S2
IDE_CS1_S#
IDE_CS3_S#
IDE_DACK_S#
IDE_IOW_S#
IDE_INTR_S
IDE_DREQ_S
IDE_IOR_S#
IDE_RDY_S
CABLE_DET_S/GPIO_64
IDE_COMP_3P3
IDE_COMP_GND
R870 121Ohm
1 2
L113
120Ohm/100Mhz
21
C837
0.1UF/16V
C842
10uF/10V
IDE_SINTR 24
IDE_PDIAG 24
IDE_SDCS3# 24
IDE_SDIOW# 24
IDE_SDA1 24
IDE_PDCS1# 24
IDE_PDCS3# 24
IDE_SDCS1# 24
IDE_PDDACK# 24
IDE_PDIOW# 24
IDE_PDIOR# 24
IDE_SDA0 24
IDE_PINTR 24
IDE_PDA0 24
IDE_PDDREQ 24
IDE_SDA2 24
IDE_SDDACK# 24
IDE_PDA2 24
IDE_PIORDY 24
IDE_SIORDY 24
IDE_SDD[15..0] 24
IDE_PDA1 24
IDE_PDD[15..0] 24
IDE_SDIOR# 24
IDE_SDDREQ 24
SATA_RXN024
SATA_RXP024
SATA_TSTCLK#23
SATA_TXP024
SATA_TXN024
SATA_LED#24
IDE_SDIAG 24
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AC_SRT# STRAP (LAN)
0 M11
1 RGMII
SPDIFO strap for BUF_SIO_CLK
0 14.318MHz (default)
1 24MHz
PWRGD => +xVS and +xV OK
PWRGD_SB => +xVSUS OK
5 mA
20 mA
18 mA
R1.1 (NVIDIA request)
PCB_(ID2, ID1, ID0)
R1.0-->000
R1.1-->001
R2.0-->010
R2.1
MCP51 USB/HDA
2.1
A8T
22 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
USB_PP6
USB_PN5
USB_PP5
USB_PP4
USB_PN4
USB_PP7
USB_PN6
USB_PP3
USB_PN7
USB_PN3
USB_PN2
USB_RBIAS_GND
RI#
SMB_MEM_SCL
SMB_MEM_SDA
RSTBTN#
+3VS_PLL_USB
+1.5VS_PLLUL
RTC_RST#
AC_SDOUT
AC_SYNC AC_BITCLK
AC_SDIN_1
AC_SDIN_0
AC_SDOUT
AC_SYNC
AC_RST#
RSTBTN#
PCIE_WAKE#
SMB_ALERT#
SMB_MEM_SCL
SMB_MEM_SDA
AC_RST#
AC_BITCLK
SIO_SMI#
CHG_FULL_OC
PCB_ID0
PCB_ID2
PCB_ID1
PCB_ID0
PCB_ID1
802_LED_EN#
CB_SD#
PWRLMT#
KB_SCI#
PCB_ID2
LOAD_TEST
USB_PN0
USB_PP1
USB_PN1
USB_PP2
USB_PP0
SUSCLK
IGP_SEL
IGP_SEL
DDC_CLKC51M
EDID_CLKC51M
BT_ON/OFF#
SUSCLK
SUSB#
BATT_65C#
BATT_65C#
+VCC_RTC
+3VSUS
+VCC_RTC
+1.5VS
+3VS
+3VS_PLL_SP_SS
+VCC_RTC
+3VSUS
+RTCBAT +3VA +VCC_RTC
+3VSUS
+3VSUS
+3VS
+3VSUS
+3VS+3VS+3VS
+3VS
+3VSUS
+3V
R7149 10KOhm
1 2
R15 15KOhm
1 2
RN41B
10KOhm
3 4
C849
0.01UF/25V
R254
10K
R4 15KOhm
1 2
T301
1
C851
0.1UF/16V
R883 732Ohm
1 2
R16 15KOhm
1 2
RN41C
10KOhm
5 6
R5 15KOhm
1 2
R7146 0Ohm
1 2
R7135 2.7KOhm
1 2
C850
0.1UF/16V
R893 22Ohm
1 2
RN42A
10KOhm
1 2
R17 15KOhm
1 2
R892 2.7KOhm
1 2
D67
RB715F
1
2
3
RN41D
10KOhm
7 8
R8 15KOhm
1 2
R879 22Ohm
1 2
R7114 10KOhm
1 2
JRST1
RTC_RST#
R7136 2.7KOhm
1 2
R899 10KOhm
1 2
R874 22Ohm
1 2
RN42B
10KOhm
3 4
R18 15KOhm
1 2
U3D
MCP51
R22
U26
T25
R26
T24
U21
U25
R21
T26
AE10
AF10
AF9
AB10
AE9
AA10
J4
J3
J5
AE2
K5
J2
J1
AC9
AB9
AA9
P24
P25
P22
P26
R25
P23
B25
B24
E22
G22
A25
B22
A22
Y21
AD26
AC26
AC25
AB26
AB25
AA26
AA25
Y26
Y25
W26
W25
V24
V23
V26
V25
T22
T23
Y24
Y23
U22
V22
AD25
J22
A24
M26
M25
E26
D23
M23
J21
AC3
H1
H2
M21
L25
M22
A23
J26
N21
K25
F21
C26
F24
B26
N22
L21
J25
K26
D25
AC97_CLK
AC_BITCLK/HDA_BCLK
(AC/HAD)_SDATA_OUT0/GPIO_45
(AC/HAD)_SDATA_IN0/GPIO_22
(AC/HAD)_SDATA_IN1/GPIO_23
(AC/HAD)_SDATA_IN2/GPIO_24
AC_RESET#/HDA_RST#
AC_SYNC/HDA_SYNC/GPIO_44
SPDIF0/GPIO_46
DDC_CLK0
DDC_DATA0
HPLUG_DET0/GPIO_47
DDC_DATA1/GPIO_53
NC
DDC_CLK1/GPIO_52
GPIO_1/SLV_RDY4PWRDWN
GPIO_2/CPU_SLP
GPIO_3/CPU_CLKRUN
GPIO_4/AGPSTP/SUS_STAT
GPIO_5/SYS_SHUTDOWN
GPIO_6/NFERR/SYS_PERR
GPIO_7/FERR/SYS_SERR
GPIO_8/CR_VID0
GPIO_9/CR_VID1
GPIO_10/CR_VID2
GPIO_11/CPU_VID0
GPIO_12/CPU_VID1
GPIO_13/CPU_VID2
GPIO_14/CPU_VID3
GPIO_15/CPU_VID4
GPIO_16/CPU_VID5
LID#/GPIO_17
SLP_DEEP#
V3P3_DEEP
LLB#
RTC_RST#
+1.5V_PLL_LEG
+3.3V_PLL_LEG
+1.5V_PLL_USB
+3.3V_PLL_USB
USB0_P
USB0_N
USB1_P
USB1_N
USB2_P
USB2_N
USB3_P
USB3_N
USB4_P
USB4_N
USB5_P
USB5_N
USB6_P
USB6_N
USB7_P
USB7_N
USB_OC0#/GPIO_18
USB_OC1#/GPIO_19
USB_OC2#/GPIO_20
USB_OC3#/GPIO_21
USB_RBIAS_GND
A20GATE/GPIO_55
INTRUDER#
EXT_SMI#/GPIO_32
RI#/GPIO_33
SPKR
PWRBTN#
SIO_PME#/GPIO_31
KBRDRSTIN#/GPIO_56
PE_WAKE#
SMB_CLK0/GPIO_25
SMB_DATA0/GPIO_26
SMB_CLK1/GPIO_27
SMB_DATA1/GPIO_28
SMB_ALERT#/GPIO_29
+3.3V_VBAT
BUF_SIO_CLK
SUS_CLK/GPIO_34
THERM#/GPIO_59
RSTBTN#
SLP_S5#
SLP_S3#
PWRGD_SB
PWRGD
FANRPM/GPIO_60
FANCTL0/GPIO_61
FANCTL1/GPIO_62
TEST_MODE_EN
R9 15KOhm
1 2
R891 49.9KOhm
1 2
R896 10KOhm
1 2
RN45C 10KOhm
5 6
C852
10uF/10V
C846
1UF/10V
G
S
D3
2
1
Q190
2N7002
R881
100KOhm
R873 22Ohm
1 2
R256
10K_*
R888 0Ohm
1 2
R7148 0Ohm
1 2
RN42C
10KOhm
5 6
R10 15KOhm
1 2
C845
1UF/X7R
RN45A
10KOhm
1 2
R876 22Ohm
1 2
RN42D
10KOhm
7 8
C853
0.01UF/25V
C848
0.1UF/16V
R11 15KOhm
1 2
C7113
0.01UF/25V
C847
10PF/50VSB_
R895 10KOhm
1 2
R25 22kOhm
1 2
RN45B
10KOhm
3 4
CON44
RTC_CON
R877 22Ohm
1 2
T300
1
R886 10KOhm
1 2
R878 22Ohm
1 2
R12 15KOhm
1 2
R1 15KOhm
1 2
R889 10KOhm
1 2
R264
10K
R87
0Ohm_*
1 2
RN45D
10KOhm
7 8
R882 1K
R872 22Ohm
1 2
R894 1KOhm
1 2
R885 1MOhm
1 2
R13 15KOhm
1 2
R2 15KOhm
1 2
R7150 10KOhm
1 2
R897 10KOhm
1 2
R263
10K_*
T246 1
R255
10K_*
R880 10KOhm
1 2
R14 15KOhm
1 2
L115
120Ohm/100Mhz
21
R875 22Ohm
1 2
R7113 10KOhm
1 2
R7147 22Ohm
1 2
RN41A
10KOhm
1 2
C854
0.1UF/16V
R3 15KOhm
1 2
L114
120Ohm/100Mhz
21
R898 10KOhm
1 2 R265
10K
T305
1
USB_PP7 25
USB_PP2 38
USB_PN2 38
USB_PP0 25
USB_PP3 38
USB_PN3 38
USB_PN7 25
USB_PP6 31
USB_PP4 40
USB_PN4 40
USB_PN6 31
USB_PP5 25
USB_PN5 25
USB_PP1 25
USB_PN1 25
USB_PN0 25
HA20GATE 28
EXTSMI#_3A 28
PM_PWRBTN# 42
SIO_SMI# 26
KBDCPURST 28
PCIE_WAKE# 30,31
SMB_DAT_SB 29,31
SMB_CLK_SB 29,31
CLK_SIO14 26
PM_THRM# 5
SUSB# 31,32,42,67,70
SUSC# 42,67
EDID_DATA_C51M17
DDC2BD_C51M18
ACZ_SDIN0_AUD36
ACZ_SDIN1_MDC38
SPKR_SB 36
SMB_MEM_SCL 8,9
SMB_MEM_SDA 8,9
ACZ_SYNC_MDC38
ACZ_BCLK_AUD36
ACZ_RST#_MDC38
ACZ_BCLK_MDC38
ACZ_SDOUT_AUD36
ACZ_SDOUT_MDC38
ACZ_SYNC_AUD36
ACZ_RST#_AUD36,37
PM_RSMRST# 42
PWRGD 5,70
MCP_TV_EN14
CR_VID147
CR_VID047
CB_SD#34
802_LED_EN#41
PM_SUS_STAT#26,38
KB_SCI#28
PWRLMT#5,68,71
SUS_CLK 38
CHG_FULL_OC69
IGP_SELECT 14,17,18
IGP_DDC_SELECT 17,18
1HZ 41
LOAD_TEST14
DDC2BC_C51M18
EDID_CLK_C51M17
BT_ON/OFF#38
BATT_TALARM 69
PROCHOT# 5
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
750 mA
200 mA
150 mA
50 mA
150 mA
55 mA
120 mA
450 mA
175 mA
150 mA
5 mA 10 mA
MCP51 PWR/GND
2.1
A8T
23 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
RTC_X1
+1.2VS_MCPCORE
+3VS_MCPHT
+1.2VS_MCPHT +1.5VS_SP
+3VS_MCPHT
+3VSUS_USB
XIN_25M
XOUT_25M
BUF_25MHZ
RTC_X0
+3VSUS
+1.5VSUS_DUAL
+1.2VS
+1.5VSUS_DUAL+1.5VSUS
+1.2VS
+3VS
+5VS
+3VS
+3VSUS
+1.5VS
R28 22Ohm
1 2
R904 10KOhm
1 2
RP9D
10kOhm
45
10
C861
0.1UF/16V
C856
0.1UF/16V
C868
22UF/6.3V
U3E
MCP51
AE7
AF6
AB6
AA6
AA7
AB7
AF7
AF8
AD7
AB8
AC7
AE8
AF4
AF5
AE6
AD3
AC4
AF2
AE5
AA8
AC5
AE4
AB5
E19
D12
C25
E25
C24
E12
D24
E21
D22
C22
B23
RGMII_TXD0/MII_TXD0
RGMII_TXD1/MII_TXD1
RGMII_TXD2/MII_TXD2
RGMII_TXD3/MII_TXD3
RGMII_TXCLK/MII_TXCLK
RGMII_TXCTL/MII_TXEN
RGMII_RXD0/MII_RXD0
RGMII_RXD1/MII_RXD1
RGMII_RXD2/MII_RXD2
RGMII_RXD3/MII_RXD3
RGMII_RXCLK/MII_RXCLK
RGMII_RXCTL/MII_RXDV
RGMII_VREF/MII_VREF
RGMII_MDC/MII_MDC
RGMII_MDIO/MII_MDIO
MII_RXER/GPIO_36
MII_COL
MII_CRS
RGMII_PWRDWN/MII_PWRDWN/GPIO_37
RGMII_INTR/MII_INTR/GPIO_35
BUF_25MHZ
+1.2V_PLL_MAC_DUAL
+3.3V_PLL_MAC_DUAL
NC1
NC2
LCD_BKL_ON/GPIO_51
NC3
LCD_BKL_CTL/GPIO_49
NC4
LCD_PANEL_PWR/GPIO_50
XTALIN
XTALOUT
XTALIN_RTC
XTALOUT_RTC
C907
0.1UF/16V
R901
0Ohm
R903 0Ohm
1 2
RP9E
10kOhm
65
10
C901
1UF/6.3V
L116
120Ohm/100Mhz
21
C859
1UF/6.3V
C889
22UF/6.3V
C880
0.1UF/16V
L117
120Ohm/100Mhz
21
RP9F
10kOhm
75
10
C879
0.1UF/16V
C883
0.1UF/16V
C906
18PF/50V
C863
0.1UF/16V
1 2
X7
25Mhz
R900 0Ohm
1 2
C857
22UF/6.3V
C884
0.1UF/16V
C904
18PF/50V
RP9G
10kOhm
85
10
C876
0.1UF/16V
U3F
MCP51
U17
U16
U15
U12
U11
U10
T17
T10
R17
R10
M17
M10
L17
L10
K17
K16
K15
K12
K11
K10
U3
R3
N3
L3
W3
AE3
AF3
Y22
F12
AD21
AD17
AD13
AD9
AD5
C12
C8
C4
Y6
T21
P21
G21
W21
V21
F17
E17
F15
E15
E16
F16
+1.2V_1
+1.2V_2
+1.2V_3
+1.2V_4
+1.2V_5
+1.2V_6
+1.2V_7
+1.2V_8
+1.2V_9
+1.2V_10
+1.2V_11
+1.2V_12
+1.2V_13
+1.2V_14
+1.2V_15
+1.2V_16
+1.2V_17
+1.2V_18
+1.2V_19
+1.2V_20
+1.2V_HT_1
+1.2V_HT_2
+1.2V_HT_3
+1.2V_HT_4
+1.2V_HT_5
+1.2V_DUAL_1
+1.2V_DUAL_2
+5V_1
+5V_2
+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_HT
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_DUAL_1
+3.3V_DUAL_2
+3.3V_DUAL_3
+3.3V_DUAL_4
+3.3V_USB_DUAL_1
+3.3V_USB_DUAL_2
+1.5V_SP_A_1
+1.5V_SP_A_2
+1.5V_SP_D_1
+1.5V_SP_D_2
+1.5V_SP_A_3
+1.5V_SP_A_4
C886
0.1UF/16V
X8 32.768Khz
1 4
C867
0.1UF/16V
C898
10uF/10V
C872
0.1UF/16V
C855
0.1UF/16V
C870
1UF/6.3V
U3G
MCP51
AF26
AF1
AD22
AD20
AD18
AD16
AD14
AD12
AD10
AD8
AD6
AD4
AC24
AB3
AA24
Y3
W24
V3
U24
U14
U13
T16
T15
T14
T13
T12
T11
T3
R24
R16
R15
R14
R13
R12
R11
P17
P16
P15
P14
P13
P12
P11
P10
P3
N24
N17
F20
E18
D18
D16
E20
C18
C16
B21
A21
N16
N15
N14
N13
N12
N11
N10
M16
M15
M14
M13
M12
M11
M3
L24
L16
L15
L14
L13
L12
L11
K14
K13
K3
J24
H3
G24
F3
E24
D3
C23
C11
C9
C7
C5
A26
A1
H5
H6
U4
R4
N4
L4
W4
L5
L6
C21
C19
C17
C15
C13
C14
B12
A12
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
SATA_GND1
SATA_GND2
SATA_GND3
SATA_GND4
SATA_GND5
SATA_GND6
SATA_GND7
SATA_GND8
SATA_GND9
GND47
GND48
GND49
GND50
GND51
GND52
GND53
GND54
GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64
GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
SATA_GND10
SATA_GND11
SATA_GND12
SATA_GND13
SATA_GND14
SATA_TSTCLK_N
SATA_GND15
SATA_GND16
C871
1UF/6.3V
R902 0Ohm
1 2
RP9H
10kOhm
95
10
C903
0.01UF/16V
C862
0.1UF/16V
C877
0.1UF/16V
C887
0.1UF/16V
C905
18PF/50V
C891
4.7U/6.3V
C894
0.1UF/16V
C885
0.1UF/16V
C865
0.1UF/16V
RP9A
10kOhm
15
10
C895
0.1UF/16V
C882
0.1UF/16V
C892
0.1UF/16V
C881
0.1UF/16V
C864
0.1UF/16V
C911
18PF/50V
C869
4.7U/6.3V
C866
0.1UF/16V
C874
0.1UF/16V
C860
1UF/6.3V
C899
0.1UF/16V
RP9B
10kOhm
25
10
C858
4.7U/6.3V
C893
0.1UF/16V
C902
0.1UF/16V
R907 0Ohm
1 2
C890
22UF/6.3V
C888
1UF/6.3V
C908
10uF/10V
RP9C
10kOhm
35
10
C910
0.01UF/16V
C875
0.1UF/16V
C873
10uF/10V
C900
0.01UF/16V
R905 10KOhm
1 2
C878
0.1UF/16V
C909
0.1UF/16V
R906 1MOhm_*
12
C897
10uF/10V
SATA_TSTCLK# 21
LCD_BKLEN_C51M 14
LCD_VDDEN_C51M 14
FWH_WP# 27
OP_SD#37
BUF_25M32
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
SATA HDD CON
PATA HDD CON
PATA CD-ROM CON
Differential
Pair
Differential
Pair
Differential
Pair
HDD & CD-ROM CONN
2.1
A8T
24 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
IDE_SDD0
IDE_SDD11
IDE_SDD4
IDE_SDD10
IDE_SDD8
IDE_SDD3
IDE_SDD15
IDE_SDD5
IDE_SDD9
IDE_SDD14
IDE_SDD13
CD_L_A CD_R_A
IDE_SDD12
IDE_SDIOW#
IDE_SIORDY
IDE_SDA1
IDE_SDCS1#
IDE_SDASP#
IDE_SCSEL
IDE_SDCS3#
IDE_SDA2
IDE_SDIAG
IDE_SDDACK#
IDE_SDIOR#
IDE_SDDREQ
CD_GND_A
IDERST#_5
IDE_SDD7
IDE_SDD6
IDE_SDD2
IDE_SDD1
IDE_SINTR
IDE_SDA0
IDE_SIORDY
IDE_PDD10
IDE_PDD11
IDE_PDIOR#
IDE_PINTR
IDE_PDD2 IDE_PDD13
IDE_PDCS3#
IDE_PDA1
IDE_PDDACK#
IDE_SCSEL
IDE_PDD6
IDE_PDD4
IDE_PDCS1#
IDE_PDD7
IDE_PDD3
IDE_PIORDY
IDE_PDD14
IDE_PDD[15:0]
IDE_PDIOW#
IDE_PDA0
IDE_PDD12
IDE_PDD5
IDE_PDDREQ
IDE_PDD7
IDE_PDASP#
IDE_PCSEL
IDE_PCSEL
IDE_PDD8
IDE_PDD9
IDE_PDDREQ
IDE_PDD0
IDE_PDD1
IDE_PDD15
SATA_HDD_TXP0
SATA_HDD_RXP0
SATA_HDD_RXN0
SATA_HDD_TXN0
IDE_PDASP#
IDERST#_5
IDE_SDD[15:0]
IDE_PINTR
IDE_PDA2
IDE_PDIAG
IDE_PIORDY
IDE_SINTR
IDE_SDDREQ
IDE_PDIAG
IDE_SDIAG
IDE_SDASP#
IDE_SDD7
+5VS +5VS
+5VS
+3VS
+5VS
+5V
+3VS
+5VS
+5VS+5VS
+5VS
+3VS
+3VS
+3VS
+3VS
+3VS
C688
0.1U_*
D68 1SS355
1 2
R186 10K_*
C305
0.1U
C689
10U/10V_*
R278 470_*
R279 5.6K_*
R282
10K
Q108A
UM6K1N
2
C690
10U/10V_*
CON42
SATA_HDD_CON
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
23
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NP_NC2
NP_NC1
GND2
GND1
R275 4.7K_*
C304
0.1U
C311
10U/10V
R276 1K_*
R916 15K_*
R277 470
R281
1K_*R913 4.7K
CON10 ODD_CON
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
R917 15K_*
R273
10K_*
C307
10U/10V
C308
0.1U
C691 0.01UF/16V
Q108B
UM6K1N
5
R914 5.6K
C309
0.1U
D62
DAP202K
1
2
3
C692 0.01UF/16V
R7137 10K
C310
10U/10V
R915 10K
R908 33Ohm
1 2
C693 0.01UF/16V
R280 10K_*
CON9 PATA_HDD_CON_*
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
C306
10U/10V
R748
10K
C694 0.01UF/16V
A
B
GND
VCC
Y
U9
NC7ST32M5X_*
1
2
3 4
5
T220
CD_L_A36 CD_R_A 36
CD_GND_A36
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,26,27,28,29,30,31,34,36,38,39,41,48,61,70
+5VS 14,18,23,28,29,36,37,38,39,40,41,61
+5V 9,16,18,25,28,31,38,40,41
IDE_PDA2 21IDE_PDA021
IDE_PDCS1#21 IDE_PDCS3# 21
IDE_PDDACK#21
IDE_PIORDY21
IDE_PDD[15:0]21
IDE_PDIOR#21
IDE_RST#20
IDE_PDDREQ21
IDE_PDIOW#21
IDE_PDA121
IDE_PINTR21
SATA_TXN021
SATA_TXP021
SATA_RXP021
SATA_RXN021
HDD_LED#41
IDE_SDD[15:0]21
IDE_SDIOW#21
IDE_SDA121
IDE_SIORDY21
IDE_SDA021
IDE_SINTR21
IDE_SDCS1#21 IDE_SDCS3# 21
IDE_SDA2 21
IDE_SDIAG 21
IDE_SDDACK# 21
IDE_SDDREQ 21
IDE_SDIOR# 21
IDE_PDIAG 21
SATA_LED# 21
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
USB
USB
USB
FOR EMI
FOR EMI
FOR EMI
FOR EMI
USB PORTS
2.1
A8T
25 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
USBP0+
USBP1+
USBP1+
USBP1-
USBP0+
USBP0-
+5VUSB0
+5VUSB0
+5VUSB7
+5VUSB5
+5VUSB0
+5VUSB_57
+5VUSB_01
USBP5-
USBP5-
USBP5+
+5VUSB5
USBP7+
+5VUSB7
USBP7-
USBP5+
USBP7-
USBP1-
USBP0-
USBP7+
+5V
+12V
+5V_USB57+5V
+12V
+5V_USB01+5V
C313
10U/10V
C314
0.1U
R133
10K
R762 0_0805_*
C312
0.1U
L28 80/2A
R763 0_0805_*
F3 1.5A/6V
12
F1 1.5A/6V
12
R135 0
Q19
PMN45EN
L30 80/2A
R141 0
R138 0
R134 0
R139 0 R764 0_0805_*
R136 0
L35 80/2A
C317
10U/10V
R137 0
VCC
DATA0-
DATA0+
GND
SIDE_G1
SIDE_G3
SIDE_G2
SIDE_G4
CON11
USB_CON_1X4P
1
2
3
4
5
6
7
8
R132
10K
R140 0
+
CE3
100U/6.3V
+
CE1
100UF/10V
CON14
USB_CON_2X4P
1
2
3
4
5
6
7
8
9
10
11
12
VCC1
1P-
1P+
GND1
VCC2
0P-
0P+
GND2
GND3
GND4
GND5
GND6
Q22
PMN45EN
C318
0.1U
R765 0_0805_*
VCC
DATA0-
DATA0+
GND
SIDE_G1
SIDE_G3
SIDE_G2
SIDE_G4
CON12
USB_CON_1X4P
1
2
3
4
5
6
7
8
USB_PP722
USB_PN722
USB_PN522
USB_PP522
USB_PN122
USB_PP122
USB_PP022
USB_PN022
+5V 9,16,18,28,31,38,40,41
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
SYSOPT=0 --> 0x002E
SYSOPT=1 --> 0x004F
SUPER IO LPC47N217
2.1
A8T
26 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
CLK_SIOPCI
LPCPD#
RI1#
CTS1#
DCD1#
LPCPD#
CLK_SIOPCI
IO_PME#
SYSOPT
DSR1#
SYSOPT
IO_PME#
GPI13
GPI13
GPI14
ATI_RST#
ATI_RST#
IO_SMI#
GPI14
DCD1#
DSR1#
RI1#
CTS1#
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
R300 10K
RN26B
10K_*
3 4
R295 10K_*
U10 LPC47N217
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
nRTS1
nCTS1
nDTR1
nRI1
nDCD1
IO_PME#
VTR
VSS1
CLOCKI
LAD0
VCC1
LAD1
LAD2
LAD3
LFRAME#
LDRQ# GP11/SYSOPT
GP12/IO_SMI#
GP13/IRQIN1
GP14/IRQIN2
IRRX2
IRTX2
IRMODE/IRRX3
GP23
nINIT
nSLCTIN
VSS3
PD0
VCC3
PD1
PD2
PD3
RN26C
10K_*
5 6
RN26A
10K_*
1 2
Q107
2N7002
R297 10K_*
C322
0.1U
C321
10U/10V
R298 10K
C323
0.1U
R666 10K_*
R299 0_*
C319
10P_*
R294 10K_*
RN26D
10K_*
7 8
C324
0.1U
C320
0.1U
T7125
1
LPC_AD320,27,28,31,38
LPC_AD220,27,28,31,38
LPC_AD020,27,28,31,38
PM_CLKRUN#20,28,34,38
PM_SUS_STAT#22,38
CLK_SIOPCI20,31
CLK_SIO1422
LPCSIO_RST#20
LPC_AD120,27,28,31,38
FIR_SEL 27
IR_TXD 27
IR_RXD 27
INT_SERIRQ20,28,34,38
LPC_FRAME#20,27,28,31,38
LPC_DRQ#020
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,27,28,29,30,31,34,36,38,39,41,48,61,70
SIO_SMI# 22
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Trace Wide=40mil
Internal PD w/
20-100K Ohm
PLCC32 Socket Part Number :
12G043400324
1206
Trace Wide=40mil
Graphics from:
05-001005111
BIOS , IR
2.1
A8T
27 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
IR_LEDA
IR_TXD_Q
IR_RXD
FWH_FGPI4
FWH_FGPI1
FWH_FGPI3
CLK_FWHPCI
FWH_FGPI0
FWH_FGPI2
+3VS
+3VS
+3VS
+3VS
+3VS
IR1
HSDL_3602_007
1
2
3
4
5
6
7
8
11
10
9
VCC
AGND
FIR_SEL
MD0
MD1
NC
GND
RXD
SHIELD
LEDA
TXD
R7151 0_*
T76
R7132 10K
T74
C330
1000P
T75
C327
10P_*
C326
10U/10V
R303 10K
R304
10K
C331
0.47U
RN27A
10K
1 2
R305 2.7
U11
SST 49LF004A-33-4C-N
24
2
31
6
5
4
3
30
9
10
11
12
18
19
20
21
2216
26
28
29
13
14
15
17
23
8
7
1
25
32
27
INIT#
RST#
CLK
FGPI0
FGPI1
FGPI2
FGPI3
FGPI4
ID3
ID2
ID1
ID0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5GND1
GND2
GNDA
IC
FWH0
FWH1
FWH2
FWH3
FWH4
TBL#
WP#
VPP
VCC1
VCC2
VCCA
RN27C
10K
5 6
R301 100
C329
0.1U
RN27B
10K
3 4
R302
10K_*
RN27D
10K
7 8
C328
10U/10V
C325
0.1U
FIR_SEL26
IR_TXD26
IR_RXD26
FWH_WP# 23
LPC_AD0 20,26,28,31,38
CLK_FWHPCI20
LPC_AD1 20,26,28,31,38
LPC_AD3 20,26,28,31,38
LPC_AD2 20,26,28,31,38
DIS_FWH28,31,38
LPCFWH_RST#20
LPC_FRAME# 20,26,28,31,38
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,28,29,30,31,34,36,38,39,41,48,61,70
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
P50, P43, P54, P55 are wake-up event
inputs when KBC in standby mode
Input Event only at P54, P55, P60 - P67
P2.1 Low : Power Button Override disable
EC should set
OP_SD low in S3,
keep from
leakage.
80mA
KBDDT1 KBDDT0 Matrix
1 1 US
1 0 UK
0 1 JP
KBC 38857
2.1
A8T
28 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
KSO1
KBC_EXTSMI
KSO9
KSO6
KSI2
KSO7
KSI5
KSI4
KSO10
KBCPURST_3Q
KBC_GA20
KSO15
KSO8
KSI3
BAT_LEARN
KSO14
X2_KBC
KSI7
KSO2
KSI6
KSO5
KSO3
KSO0
X1_KBC
KSO12
KSO11
KSO13
PCI_RSTNS#
KSI0
KSI1
KSO4
SET_PCIRSTNS#
KSI7
KSI0
KSI4
KSI1
KSI2
KSI6
KSI3
KSI5
KBC_EXTSMI
X1_KBC
X2_KBC
KBC_GA20
KBSCI_3Q
CLK_KBCPCI
KBSCI_3Q
INTCLK_5S
INTDATA_5S
KBDDT1
INTCLK_5S
INTDATA_5S
SCR_LED#
KSI5
KSO14
KSO4
KSO15
KSI6
KSO5
KSO10
KSI7
KSI4
KSO2
KSO9
KSI3
KBDDT0
KSI1
KSO3
KSO6
KSO8
KSI2
KSO1
KSO11
KSO0
KSI0
KSO7
KSO13
KSO12
LPCKBC_RST#
SET_PCIRSTNS#
PCI_RSTNS#
KBCPURST_3Q
BAT_LLOW#_OC
BAT_LLOW#_OC
FAN1_TACH
FAN1_TACH
BAT_LEARN
KBDDT1
KBDDT0
LPC_AD3
CLK_KBCPCI
LPC_AD2
LPC_AD0
DIS_FWH
LPC_FRAME#
LPC_AD1
+5VS
+3V
+3V
+3V
+3V
+3VSUS
+3VS
+3V
+5V
+3V
+5VLCM
+5VS
+5VLCM
+3V
+5VS
+3V
+3V +3VS
+3V
+5VS
+5VLCM
+3VSUS
+5V
RP4F 10K
7 5
10
RP4G 10K
8 5
10
RN30C 10K
5 6
C338
0.1U
R327
4.7K
D15 1SS355
12
RP4A 10K
1 5
10
RN30D 10K
7 8
D14
1SS355
12
RP4C 10K
3 5
10
R321 100K
R333
10K
R734 100K
C341 10P
RN33C
10K
5 6
R324
1M
Q14A
UM6K1N
6 1
RP4D 10K
4 5
10
C339
0.1U
R331
4.7K
RN30A 10K
1 2
R330
47K
R325
4.7K
RN33D
10K
7 8
RN33A
10K
1 2
CON43
DEBUG_CON
12
11
10
9
8
7
6
5
4
3
2
1
13
14 12
11
10
9
8
7
6
5
4
3
2
1
SIDE1
SIDE2
A
B
GND
VCC
Y
U14
74LVC1G32GV
1
2
3 4
5
GS
D
3
2
1
Q15
2N7002
RN33B
10K
3 4
D16 1SS355
12
R332
4.7K
R322
10K
C340 10P
RP4B 10K
2 5
10
Q13
2N7002
Q14B
UM6K1N
3 4
R320
10K
RP4H 10K
9 5
10
C342
0.1U
RN30B 10K
3 4
R319
10K
R323
10K
P54,P55,P43,P50 are
wake-up event
inputs when KBC in
standby mode
U13 M38857
63
64
65
66
67
68
69
70
35
36
37
38
18
19
20
21
22
23
10
11
12
13
14
15
16
17
74
75
76
77
78
79
80
1
4
5
6
7
8
9
2
3
71
72
31
32
33
34
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
28
29
27
26
25
24
30
73
P87/SERIRQ
P86/LCLK
P85/LRESET#
P84/LFRAME#
P83/LAD3
P82/LAD2
P81/LAD1
P80/LAD0
P23
P22
P21
P20
P47/SRDY1#/CLKRUN#
P46/SCLK1
P45/TXD
P44/RXD
P43/INT1*
P42/INT0
P57/DA2/PWM11
P56/DA1/PWM01
P55/CNTR1*
P54/CNTR0*
P53/INT40/1-WIRE2
P52/INT30/1-WIRE1
P51/INT20
P50/INT5*
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
P61/AN1
P60/AN0
P75/INT41
P74/INT31
P73/INT21
P72
P71
P70
P77/SCL
P76/SDA
VCC
VREF
P27
P26
P25
P24
P17/KSO15
P16/KOS14
P15/KSO13
P14/KSO12
P13/KSO11
P12/KSO10
P11/KSO9
P10/KSO8
P07/KSO7
P06/KSO6
P05/KSO5
P04/KSO4
P03/KSO3
P02/KSO2
P01/KSO1
P00/KSO0
P37/KSI8
P36/KSI7
P35/KSI6
P34/KSI5
P33/KSI4
P32/KSI3
P31/PWM10/KSI2
P30/PWM00/KSI0
XIN
XOUT
P40/XCOUT
P41/XCIN
RESET#
CNVSS
VSS
AVSS
C337
10P_*
R326
4.7K
X3
8MHZ
2
CON16
Internal_KB_CON
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SIDE1
SIDE2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RP4E 10K
6 5
10
LPC_AD220,26,27,31,38
LPC_FRAME#20,26,27,31,38
LPC_AD320,26,27,31,38
LPC_AD020,26,27,31,38
LPC_AD120,26,27,31,38
PM_CLKRUN#20,26,34,38
LPCKBC_RST#20
CLK_KBCPCI20
BAT_IN_OC#71
BLUETOOTH_#41
INTERNET_#41
MARATHON_#41
WIRELESS_#41
INT_SERIRQ20,26,34,38
KBCRSM42
BAT_LEARN68
CAP_LED# 41
NUM_LED# 41
ADJ_BL17
EXTSMI#_3A 22
HA20GATE 22
KB_SCI# 22
KBDCPURST 22
SMC_BAT39,69
SMD_BAT39,69
INTCLK_5S41
INTDATA_5S41
WATCHDOG40
FAN1_DC40
BAT_LLOW#_OC69
LID_KBC#42
PANLOCK_#41
FAN1_TACH40
MSK_INSTKEY#41
SWDJ_EN41
DIS_FWH 27,31,38
PANLOCK_LED 41
+5VS 14,18,23,24,29,36,37,38,39,40,41,61
+5VLCM 68,69,70,71
+3V 22,30,31,35,37,38,42
+3VSUS 5,17,20,22,23,29,32,42,46,48,70
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,29,30,31,34,36,38,39,41,48,61,70
+5V 9,16,18,25,31,38,40,41
AC_IN#68
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
Termal Sensor,
TPM
MCP51
SM BUS & POWER PORT
2.1
A8T
29 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+5VS
+3VS+3VS+3VSUS +3VSUS
+5VS
+1.5VS
+3VA
+12VS
+12V
+2.5VS
+3V
+VCORE
+3VS
+5V
+1.8V
+5VLCM
+0.9VS
+3VSUS
Q18B
UM6K1N
3 4
RN31C
2.2K
RN31A
2.2K
Q18A
UM6K1N
6 1
RN31D
2.2K
RN31B
2.2K
SDA_3S 5,16
SCL_3S 5,16
SMB_DAT_SB22,31
SMB_CLK_SB22,31
+0.9VS 16
+3VA 22,38,41,42,48,71
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,30,31,34,36,38,39,41,48,61,70
+VCORE 5,7,61
+3VSUS 5,17,20,22,23,28,32,42,46,48,70
+1.5VS 19,21,22,23,30,31,38,48
+1.8V 5,7,8,9,10,38,65
+5VLCM 28,68,69,70,71
+5V 9,16,18,25,28,31,38,40,41
+12VS 16,17
+5VS 14,18,23,24,28,36,37,38,39,40,41,61
+3V 22,28,30,31,35,37,38,42
+12V 25,40
+2.5VS 5,11,14,15,16,18,38,48
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
MINI CARD
2.1
A8T
30 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
WLAN_WAKE#
WLAN_WAKE#
WLAN_LED#
+1.5VS+3V+3VS
+1.5VS
+3V+3VS
+1.5VS
+3V
+3VS
+3V
C382
0.1U
C379
0.1U
CON19
MINI_PCI_LATCH_52P
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
54
56
55
WAKE#
BT_DATA
BT_CHCLK
CLKREQ#
GND1
REFCLK-
REFCLK+
GND2
Reserved1
Reserved2
GND3
PERn0
PERp0
GND4
GND5
PETn0
PETp0
GND6
Reserved3
Reserved4
Reserved5
Reserved6
Reserved7
Reserved8
Reserved9
Reserved10
3.3V_1
GND7
1.5V_1
Reserved11
Reserved12
Reserved13
Reserved14
Reserved15
GND8
W_DISABLE#
PERST#
3.3Vaux
GND9
1.5V_2
Reserved16
Reserved17
GND10
Reserved18
Reserved19
GND11
NC1
LED_WLAN#
NC2
1.5V_3
GND12
3.3V_2
GND13
GND14
NP_NC2
NP_NC1
R359 0
C384
0.1U
C375
0.1U
C380
10U/10V
R123 0_*
R360 0
C378
0.1U
T218
CON20
MINI_PCI_LATCH_3P
1
2
3
GND
P_GND1
P_GND2
C377
0.1U
C376
0.1U
C381
0.1U
C383
0.1U
Q100
2N7002
PE_RST# 13,16
CLK_PCIE_MINICARD13
CLK_PCIE_MINICARD#13
+1.5VS 19,21,22,23,31,38,48
CH_DATA_A38
CH_CLK_A38
PCIE_WAKE#22,31
CLK_REQ_MINICARD#13
+3V 22,28,31,35,37,38,42
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,31,34,36,38,39,41,48,61,70
PCIE_TXP1_MINICARD13
PCIE_TXN1_MINICARD13
PCIE_RXN1_MINICARD13
PCIE_RXP1_MINICARD13
802_ON/OFF# 41
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
90ohm Diff. pair
2A
1A
0.7A
Int.PU
Int.PU
Int.PU
Int.PU
Int.PU
Int.PU
OD
NEW CARD
2.1
A8T
31 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PCIE_WAKE#_R
SHDN#
SMB_DAT_SB_R
CP_PE#_R
PERST#
USB_P6-
USB_P6+
USB_P6+
CP_USB#
SHDN#
PERST#
CP_USB#
USB_P6-
SMB_CLK_SB_R
DEBUG_EN#
DEBUG_EN#
CP_PE#_R
CLK_REQ#
PCIE_WAKE#_R
SMB_CLK_SB_R
SMB_DAT_SB_R
CP_PE#
PCIE_WAKE#
SMB_CLK_SB
SMB_DAT_SB
PERST#
CLK_REQ#
CP_PE#
PCIE_WAKE#
SMB_DAT_SB
SMB_CLK_SB
PCIE_WAKE#_R
CP_PE#_R
SMB_CLK_SB_R
SMB_DAT_SB_R
CP_PE#
CLK_REQ#
+1.5VS_PE
+1.5VS_PE
+1.5VS_PE
+3VS_PE
+1.5VS
+3VS_PE
+3VS
+3VS_PE
+3V
+1.5VS
+3V
+3VS +3V_PE
+3V_PE
+3V_PE
+3VS
+1.5VS
+3V
+5V
+3V
+3VS
R119 0
T83
B
C
E
1
2
3
Q17
PMBS3904_*
C696
2200PF/50V_*
C669
10U/10V
C697
0.1UF/16V_*
CON37
EXPRESS_CARD_26P
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
27
28
29
30
GND4
PETp0
PETn0
GND3
PERp0
PERn0
GND2
REFCLK+
REFCLK-
CPPE#
CLKREQ#
+3.3V_2
+3.3V_1
PERST#
+3.3VAUX
WAKE#
+1.5V_2
+1.5V_1
SMBDATA
SMBCLK
RESERVED2
RESERVED1
CPUSB#
USB_D+
USB_D-
GND1
NP_NC1
NP_NC2
GND5
GND6
C663
10U/10V
C668
0.1U
R909
22KOhm
C662
0.1U
R758 1K
C660
0.1U
R754
100K_*
RN8A
0
1 2
R756 33_*
D59
1SS355_*
12
R757 33_*
D58
RSB6.8S_*
C667
10U/10V
RN8D
0
7 8
C665
10U/10V
C666
0.1U
C664
0.1U
R755
10K_*
CON41
CARD_EJECTOR_2P_*
1
2
P_GND1
P_GND2
R910
22KOhm
C695
0.1U_*
R771 47K_*
RN8C
0
5 6
U51 SN74CBT3383PWR_*
3
7
11
17
21
4
8
14
18
22
1
13
2
6
10
16
20
5
9
15
19
23
24
12
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
BE#
BX
C0
C1
C2
C3
C4
D0
D1
D2
D3
D4
VCC
GND
GS
D
3
2
1
Q104
2N7002
U48 R5538D001
14
15
4
5
7
8
1
2
18
13
3
6
1017
16
12
19
20 11
9
21
1.5VIN_1
AUXOUT
3.3VIN_2
3.3VOUT_2
GND1
PERST#
STBY#
3.3VIN_1
RCLKEN
1.5VOUT_2
3.3VOUT_1
SYSRST#
CPPE#AUXIN
NC
1.5VIN_2
OC#
SHDN# 1.5VOUT_1
CPUSB#
GND2
RN8B
0
3 4
C659
10U/10V
D57
RSB6.8S_*
C661
10U/10V
R118 0
D65
1SS355_*
12
C670
0.1U
USB_PN622
USB_PP622
SUSB#22,32,42,67,70
CLK_PCIE_NEWCARD#13
VSUS_ON42,46,67
PCIRST_NEWC#5,20
CLK_PCIE_NEWCARD13
PCIE_RXP2_NEWCARD13
PCIE_TXP2_NEWCARD13
PCIE_RXN2_NEWCARD13
PCIE_TXN2_NEWCARD13
CLK_REQ_NEWCARD# 13
+3V 22,28,30,35,37,38,42
+1.5VS 19,21,22,23,30,38,48
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,34,36,38,39,41,48,61,70
LPC_AD320,26,27,28,38
DIS_FWH27,28,38
SMB_CLK_SB22,29
SMB_DAT_SB22,29
PCIE_WAKE#22,30
LPC_AD020,26,27,28,38
LPC_AD120,26,27,28,38
LPC_AD220,26,27,28,38
CLK_SIOPCI20,26
LPC_FRAME#20,26,27,28,38
PRSNT_NEWCARD# 13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PIN 10/120
8100:5.6KOHM(1%)
8110:2.49KOHM(1%)
8100:NOT SYUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100/ 2.5V
8110/ 3.3V
8100:NO STUFF
8110:STUFF
PIN 12
PIN 3/7/20/16
8100:STUFF
8110:NO STUFF
8100:NO STUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100:STUFF
8110:NO STUFF
8100:STUFF
8110:NO STUFF
8100/ N/A
8110/1.2V
8100/2.5V
8110/1.2V
8100/3.3V
8110/2.5V
PIN
126
PIN 24/32/45/54/64
/78/99/110/116
V_DAC
AVDDH
PIN 12
DVDD_A
N/A
V_12P
N/A
2.5AVDD
1.2AVDD
DVDD
2.5AVDD
PIN 10/120
N/A
PIN 126
3.3AVDD
PIN 3/7/20/16
AVDDL
1.2VDD
RTL8100C RTL8110SB
3.3AVDD
2.5VDD
3.3AVDD
2.5AVDD
PIN 24/32/45/54/64
/78/99/110/116
15mA
71mA
307mA
226mA
11mA
700mA
LAN -- RTL8110CL
2.1
A8T
32 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
L_TDN
PCI_AD26
LAN_EECS
LAN_EEDI
L_TDP
L_TRDM3
PCI_AD25
DVDD_A
LAN_EEDO
PCI_AD20
L_TRDM2
L_RDN
PCI_AD27
L_TRDP3
L_TDN
L_TRDM3
L_TRDP2
L_TRDP2
PCI_AD1
PCI_AD0
PCI_AD17
PCI_AD16
PCI_AD21
PCI_AD18
L_RDP
DVDD
PCI_AD19
PCI_AD22
L_TDP
PCI_AD23
LAN_EECS
LAN_EEDO
L_TRDP3
LAN_EESK
PCI_AD17
LAN_EEDI
L_RDN
CTRL12
L_TRDM2
LAN_EESK
PCI_AD24
L_RDP
DVDD_A
XTAL2
V_12P
DVDD_A
CTRL25
+3V_LAN
AVDDH
V_12P
AVDDH
CTRL12
AVDDL
DVDD
AVDDL
AVDDL
XTAL1
+3V_LAN
V_DAC
GND
+3V_LAN
+3V_LAN
+3V_LAN
AVDDHAVDDL
DVDD
+3VSUS
R354 49.9Ohm
12
R950 10KOhm
1 2
R955
0Ohm_*
1 2
C368
10UF/10V
C372
22UF/6.3V
R45 0Ohm
1 2
C365
0.1UF/16V
R356 49.9Ohm
12
C916
0.1UF/16V
U17
RTL8110SBL
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
123
124
125
126
121
122
127
128
129 PCIAD27
PCIAD26
VDD33_1
PCIAD25
PCIAD24
CBEB3
VDD12_2
IDSEL
PCIAD23
GND2
PCIAD22
PCIAD21
VSSPST2
GND3
PCIAD20
VDD12_3
PCIAD19
VDD33_2
PCIAD18
PCIAD17
PCIAD16
CBEB2
FRAMEB
GND4
IRDYB
VDD12_4PCIAD1
PCIAD0
LANWAKE
EECS
VDD33_6
EEDO
EEDI
VDD12_7
EESK
GND8
LED3
LED2
LED1
VDD12_8
LED0
GND9
VSSPST7
AVDDH2
VSS4
VSS5
CTRL12
VDD12_9
XTAL1
XTAL2
RSET
VSS6
GND
C932
0.1UF/16V
C366
27P_*
C362
0.1UF/16V
R952
0Ohm
R358 49.9Ohm
12
C913
0.1UF/16V
R954 0Ohm
1 2
C951
0.1UF/16V
C919
0.1UF/16V
C925
0.1UF/16V
R352 49.9Ohm
12
C371
22UF/6.3V
L3
120Ohm/100Mhz
21
R357 49.9Ohm
12
C938
22UF/6.3V
C360
0.1UF/16V
R953
2.49KOhm
C917
0.1UF/16V
C926
0.1UF/16V
L48
120Ohm/100Mhz
21
C370
22UF/6.3V
C918
0.1UF/16V
C931
0.1UF/16V
C935
0.01UF/16V
R947
0Ohm
1 2
R944
0Ohm_*
1 2
Q52
2SB772PT
C914
0.1UF/16V
R943
0Ohm
1 2
C367
27P_*
R949 10KOhm
/*
1 2
U16
AT93C46
1
2
3
4 5
6
7
8
CS
SK
DI
DO GND
ORG
DC
VCC
C933
0.01UF/16V
R6
0Ohm
1 2
C363
0.1UF/16V
L49
120Ohm/100Mhz_*
21 C361
0.1UF/16V
R918
100Ohm
1 2
R945 0Ohm
1 2
R351 49.9Ohm
12
C924
0.1UF/16V
R942
0Ohm
1 2
C369
22UF/6.3V
R951 10KOhm_*
1 2
Q51
2SB772PT
C939
22UF/6.3V
C934
0.01UF/16V
R946
0Ohm_*
C921
0.1UF/16V
C920
0.1UF/16V
R350 49.9Ohm
12
C936
0.01UF/16V
C927
10UF/10V
R948 0Ohm
1 2
C923
0.1UF/16V
1 2
X4
25Mhz_*
C928
0.1UF/16V
C915
0.1UF/16VC937
22UF/6.3V
C922
0.1UF/16V
R355 49.9Ohm
12
C364
0.1UF/16V
PCI_STOP# 20,34
PCIRST_LAN# 20
PCI_C/BE#2 20,34
PCI_DEVSEL# 20,34
PCI_PME# 20,34
PCI_REQ#1 20
PCI_IRDY# 20,34
PCI_PERR# 20,34
PCI_FRAME# 20,34
PCI_GNT#1 20
PCI_C/BE#3 20,34
PCI_SERR# 20,34
L_TRDM2 33
L_TRDM3 33
L_TRDP2 33
PCI_PAR 20,34
L_TRDP3 33
PCI_C/BE#0 20,34
L_TDP 33
PCI_C/BE#1 20,34
L_RDP 33
PCI_TRDY# 20,34
SUSB# 22,31,42,67,70
L_RDN 33
L_TDN 33
CLK_LANPCI 20
PCI_INTC# 20
PCI_AD[31:0] 20,34
BUF_25M23
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
8100:NO STUFF
8110:STUFF
8100:NO STUFF
8110:STUFF
8100:0.1UF
8110:0.01UF
Co- layout
RJ45 & RJ11
2.1
A8T
33 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
LTXN
LTRLM2
L_TRLP2
L_CMT2
L_TXP
L_TRLM3
L_TRLM2
L_CMT0
LTRLM3
L_CMT3
L_CMT1
LRXN
LRXP
L_CMT1
RDC
TIP_J
L_CMT0
LTRLP2
LTRLP3
L_RXP
L_RXN
L_TXN
TIP
LTXP
L_TRLP3
RING_J
L_CMT3
L_CMT2
FGND1S
L_TXN
L_RXN
L_TRLM3
L_TRLP3
LTXP
LTXN
LRXN
L_RXP LRXP
L_TRLM2
L_TRLP2
LTRLM2
LTRLM3
LTRLP3
RING
LTRLP2
L_TDP
L_RDP
L_RXN
L_TXN
L_RDN
L_TXP
L_CMT1
L_RXP
L_TXP
RDC
L_TDN
L_CMT0
V_DAC
L46 1KOhm/100Mhz
21
C674
1000PF/3KV
R143 0
C943
0.01UF/25V
RN32A
75Ohm
1 2
R142 0
C675
1000PF/3KV
CON17
MODULAR_JACK_12P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
NP_NC1
NP_NC2
P_GND1
P_GND2
SIDE1
SIDE2
R146 0
C942
0.01UF/25V
C944
1000PF/50V
HA003
TAIMIC
U59
LFE8505 _*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TD+
TDCT
TD-
NC1
NC2
RD+
RDCT
RD-
TX+
TXCT
TX-
NC4
NC3
RX+
RXCT
RX-
R150 0
RN32B
75Ohm
3 4
R145 0
C941
0.01UF/25V
L47 1KOhm/100Mhz
21
R148 0
R149 0
L43 180OHM/100MHz_*
R147 0
R7
0Ohm
1 2
MCT1
MCT2
MCT3
MCT4
MX1+
MX1-
MX2+
MX2-
MX3+
MX3-
MX4+
MX4-
TCT1
TD1+
TD1-
TD2+
TD2-
TD3+
TD3-
TD4+
TD4-
TCT2
TCT3
TCT4
U15
LG_2402S_1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
RN32C
75Ohm
5 6
C940
0.01UF/25V
L45 180OHM/100MHz_*
RN32D
75Ohm
7 8
L44 180OHM/100MHz_*
CON18
MODEM_CON
3
4
1
2
SIDE1
SIDE2
1
2
L42 180OHM/100MHz_*
L_RDN32
L_TRDP232
L_TRDM332
L_RDP32
L_TRDP332
L_TDN32
L_TDP32
L_TRDM232
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
GBRST# POWER SEQ
+3V ==> (GBRST#/CB_HWSUSP#) ==>PCIRST#
H/W SUSPEND# POWER SEQ :
SUSPEND : CB_HWSUSP# LO=> PCIRST# LO=> +3VS OFF
RESUME : +3VS ON => PCIRST# HI=> CB_HWSUSP# HI+3VS ==> CB_GBRST#
1ms < T < 100ms
Open Drain:
PME#,
SERR#,
INTn#
CLOSE TO R5C832
1.CLOSE TO R5C841
2.The area is as compact as possible,length<10 mm
3.TPA Pair and TPB pair mismatch<2.5mm
4.No via recommend , maxmium is one.
5.Total length<50 mm
6.Differential impedance is 110+/- 6 ohm
7.TPA Pair trace or TPB pair trace mismatch < 1.25mm
PCI R5C832
2.1
A8T
34 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
CB_GBRST#
CB_GBRST#
PCI_C/BE#2
PCI_C/BE#0
CB_IDSEL_J
PCI_C/BE#1
PCI_C/BE#3
CB_HWSUSP#
CB_HWSUSP#
CB_IDSEL_JPCI_AD16
PCI_AD26
PCI_AD24
PCI_AD6
PCI_AD8
PCI_AD5
PCI_AD2
PCI_AD3
PCI_AD23
PCI_AD17
PCI_AD13
PCI_AD27
PCI_AD15
PCI_AD25
PCI_AD29
PCI_AD22
PCI_AD19
PCI_AD9
PCI_AD10
PCI_AD31
PCI_AD20
PCI_AD18
PCI_AD4
PCI_AD7
PCI_AD0
PCI_AD28
PCI_AD14
PCI_AD21
PCI_AD1
PCI_AD12
PCI_AD16
PCI_AD30
PCI_AD11
1394_SCL
1394_SDA
1394_SCL
1394_SDA
X2_1394
X1_1394
1394_REF
TPBIAS0
AVCC_PHY_CB
1394_FIL
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
C431 18P
R369 100K
X5
24.576Mhz
C430 18P
R393
56_1
C433 0.01U/X7R
R384 10K
D18 1SS355
1 2
C396
0.1U
C432 0.1U
L50 120/400mA
R392
56_1
R375 10K
R371 10K
C397
0.1U
C394
0.1U
C390
0.1U
R391
5.11K_1
C391
0.1U
C399
0.01U/X7R
U18B R5C832
57
72
67
115
70
45
35
21
7
53
52
51
50
49
48
47
46
44
69
43
42
40
39
38
37
36
19
18
17
15
14
12
11
9
6
5
3
2
1
127
126
125
4
10
20
16
33
124
123
31
30
29
26
25
8
24
23
117
119
121
71
13
22
28
34
86
116
59
65
99
103
102
61
66
60
56
58
55
27
32
41
128
64
114
120
54
62
63
68
118
122
107
111
UDIO5
UDIO0/SRIRQ#
VCC_3V
INTA#
PME#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
HWSPND#
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
GND1
VCC_PCI3V_1
VCC_PCI3V_2
VCC_ROUT1
PAR
REQ#
GNT#
SERR#
PERR#
STOP#
DEVSEL#
TRDY#
IDSEL
IRDY#
FRAME#
CLKRUN#
PCIRST#
PCICLK
GBRST#
GND2
GND3
GND4
VCC_ROUT2
VCC_MD
INTB#
UDIO4
UDIO3
AGND1
AGND2
AGND3
VCC_RIN
TEST
UDIO1
UDIO2
MSEN
XDEN
VCC_PCI3V_3
VCC_PCI3V_4
VCC_PCI3V_5
VCC_PCI3V_6
VCC_ROUT3
VCC_ROUT4
VCC_ROUT5
GND5
GND6
GND7
GND8
GND9
GND10
AGND4
AGND5
C405
10P_*
C392
10U/10V
Q105
2N7002_*
U22
AT24C02N
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
C387
0.1U
C434 0.33U
R362 10K_1
C386
0.1U
R374 100
C400
10U/10V
C407 1UF/X7R
C402
0.1U
C393
0.1U
R361 10K
R383 10K
R386
56_1
C388
0.01U/X7R
C401
1000P
C406
10P
C385
10U/10V
C435 270P
R368
10K
U18A R5C832
98
106
110
113
104
105
108
109
94
95
96
101
100
80
90
77
76
75
74
73
88
84
82
81
93
79
78
91
89
92
87
85
83
112
97
AVCC_PHY3V_1
AVCC_PHY3V_2
AVCC_PHY3V_3
TPBIAS0
TPBN0
TPBP0
TPAN0
TPAP0
XI
XO
FIL0
REXT
VREF
MDIO00
MDIO13
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO01
MDIO02
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
AVCC_PHY3V_4
RSV
C389
10U/10V
C424
0.01U/X7R
R385
56_1
R364 10K
PCI_TRDY#20,32
PCI_PERR#20,32
PCI_STOP#20,32
PCI_FRAME#20,32
PCI_PAR20,32
PCI_DEVSEL#20,32
PCI_IRDY#20,32
PCI_C/BE#[3:0]20,32
PCI_GNT#020
CLK_CBPCI20
PCIRST_CB#20
PCI_PME#20,32
PCI_REQ#020
PCI_SERR#20,32
PCI_AD[31:0]20,32
CB_SD# 22
PM_CLKRUN#20,26,28,38
PCI_INTA# 20
PCI_INTB# 20
INT_SERIRQ 20,26,28,38
TPB0-_0 40
TPB0+_0 40
TPA0+_0 40
TPA0-_0 40
MDIO12 35
MDIO00 35
MDIO11 35
MDIO15 35
MDIO17 35
MDIO04_SD/MS/XDPWR 35
MDIO19 35
MDIO01 35
MDIO13 35
MDIO10 35
MDIO08 35
MDIO09 35
MDIO02 35
MDIO14 35
MDIO03 35
MDIO16 35
MDIO05 35
MDIO18 35
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,36,38,39,41,48,61,70
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Solve MS Duo Adaptor
short problem
Place as
close to
card reader
socket as
possible
4 IN 1 CONN
2.1
A8T
35 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
SDCD#
MSCD#
XD_CD#
SD_DAT1
SD_DAT2
SD_CD
MDIO12_SD/MS/XDDAT2
MDIO11_SD/MS/XDDAT1
SDCD#
XD_CD
XD_CD#
MDIO13_SD/MS/XDDAT3
MDIO12_SD/MS/XDDAT2
MDIO12_SD/MS/XDDAT2
MDIO13_SD/MS/XDDAT3
MDIO09_SD/MSCLK_XDRE#
MDIO14_XDDAT4
MDIO10_SD/MS/XDDAT0
MDIO09_SD/MSCLK_XDRE#
MDIO08_SDCMD_MSBS_XDWE#
MDIO19_XDALE
MSCD#
MDIO10_SD/MS/XDDAT0
MDIO13_SD/MS/XDDAT3
MDIO16_XDDAT6
MDIO15_XDDAT5
MDIO02_XDCE#
MDIO11_SD/MS/XDDAT1
MDIO10_SD/MS/XDDAT0
MDIO09_SD/MSCLK_XDRE#
MSCD#
MDIO08_SDCMD_MSBS_XDWE#
MDIO08_SDCMD_MSBS_XDWE#
MDIO18_XDCLE
XD_CD#
MDIO11_SD/MS/XDDAT1
MDIO17_XDDAT7
MDIO05_XDWP#
MDIO03_SDWP_XDR/B#
SD_DAT1
SD_DAT2
MDIO08_SDCMD_MSBS_XDWE#
MDIO17_XDDAT7
MDIO09_SD/MSCLK_XDRE#
MDIO11_SD/MS/XDDAT1
MDIO15_XDDAT5
MDIO14_XDDAT4
MDIO03_SDWP_XDR/B#
MDIO05_XDWP#
MDIO12_SD/MS/XDDAT2
MDIO19_XDALE
MDIO18_XDCLE
MDIO03_SDWP_XDR/B#
MDIO01_MSCD#_XDCD#
MDIO13_SD/MS/XDDAT3
MDIO10_SD/MS/XDDAT0
SDCD#
MDIO02_XDCE#
MDIO00_SDCD#_XDCD#
MDIO16_XDDAT6
+MC_VCC XD_VCC
+12V
+MC_VCC XD_VCC
+3V
+MC_VCC
+12V
+3V
R397
150K
Q25
2N7002
GS
D
3
2
1
Q27
2N7002
C439
270P_*
D
S
G
1
2
3
Q28
SI2301BDS
1
Q24
2N7002
GS
D
3
2
1
Q26
2N7002
R395 10K
C440
270P_*
C437
0.1U
CON23 SD_CARD_38P
1
2
S9
S1
S2
S3
M10
M9
M8
M7
M6
M5
M4
M3
M2
M1
S4
S5
S6
S7
S8
X1
X0
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
X17
X18
NP_NC1
NP_NC2
DAT2
CD/DAT3
CMD
VSS1
VSS2
VCC1
SCLK
Reserved1
INS
Reserved2
SDIO
VCC2
BS
VSS3
VDD
CLK
VSS4
DAT0
DAT1
GND1
CD
R/-B
-RE
-CE
CLE
ALE
-WE
-WP
GND2
D0
D1
D2
D3
D4
D5
D6
D7
VCC3
Q23
2N7002
GS
D
3
2
1
Q29
2N7002
R394 10K
D21
DAN202K
1
2
3
C438
270P_*
C436
0.1U
R396
10K
MDIO00_SDCD#_XDCD#34
MDIO01_MSCD#_XDCD#34
MDIO04_SD/MS/XDPWR34
+3V 22,28,30,31,37,38,42
+12V 25,37,40,67
MDIO1934
MDIO0234
MDIO0934
MDIO1534
MDIO1034
MDIO1234
MDIO0534
MDIO0334
MDIO0134
MDIO1734
MDIO1434
MDIO0834
MDIO1834
MDIO0034
MDIO1134
MDIO1334
MDIO1634
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Trace
wide=10 mils
Vout=1.25*(1+(100K/34.8K)= 4.84V
For EMI
Trace
wide=10 mils
R2.1
R2.0
R2.0
R2.1
CODEC_ADI1986A
2.1
A8T
36 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
L_35_A
R_36_A
PC_BEEP_C
MIC_IN_A
+3VS
+5VAUD
+5VAUD
AGND_A
AGND_A
AGND_A
AGND_A
+5VAUD
AGND_A AGND_AAGND_A AGND_A AGND_A
+5VS
+3VS
+5V
+5VAUD
AGND_AAGND_A
+5VS +5VAUD
AGND_A
AGND_A
AGND_A
AGND_A
+5VAUD
1UF/16V
C465
U25 G913CF
1
2
3 4
5
SHDN#
GND
IN OUT
SET
R78 0Ohm _*
12
R76 0_*
C478
0.1U_*
Q125B
UM6K1N_*
5
R674 4.7K
C484 1UF/X7R
20PF/50VC463
1 2
1UF/16V
C468
R412 100K_1
0.1UF/16V
C460
R418 47KOhm
1 2
120Ohm/100Mhz_*L58 21
120Ohm/100Mhz_*L57 21
C470
0.1U
R414 10K
R675 2.2K
R423
47K_1
U26 AD1986AJCPZ
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
DVDD1
AC97CK
GPO
DVSS1
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD2
SYNC
RESET#
PCBEEP
SURR_OUT_R
SURR_OUT_L
AVDD3
VREF_OUT/C/LFE
LFE_OUT
CENTER_OUT
AVSS2
VREF_OUT/LINE_IN
VREF_OUT/MIC_1/2
VREF_FILT
AVSS1
AVDD1
C475
10U/10V
C472 1UF/X7R
4.7KOhm
R420
0.01UF/50V
C912
R59 20KOhm _*
12
22PF/50V_*
_*
C474
R676 2.2K
C967
1UF/10V_*
C469
10U/10V
0OhmL118
1 2
R77 0
R427
47K_1
C476
1UF/X7R
33OhmR416
1 2
T107
0OhmR912 1 2
R413
34.8K_1
R58 40.2KOhm _*
C477
0.1U
10UF/10V
C462
C480 1UF/X7R
R419 47K_1
R425
23.7K_1
C471
0.1U
C67 1UF/X7R_*
C473 1UF/X7R
R424 23.7K_1
C486 1UF/X7R
C485 1UF/X7R
C479 1UF/X7R
R426 47K_1
Q125A
UM6K1N_*
2
C66 1UF/X7R_*
0.1UF/16VC482
12
R79
100KOhm_*
VREFOUT 37
ACZ_SDOUT_AUD22
ACZ_SDIN0_AUD22
ACZ_SYNC_AUD22
MIC_IN_A 37
OUTR_A 37
OUTL_A 37
SPDIF_A37
CD_L_A 24
CD_GND_A 24
CD_R_A 24
ACZ_BCLK_AUD22
ACZ_RST#_AUD22,37
+5VS 14,18,23,24,28,29,37,38,39,40,41,61
+5V 9,16,18,25,28,31,38,40,41
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,38,39,41,48,61,70
+5VAUD 37
EAPD37
HP_L_CODEC 37
HP_R_CODEC 37
VREFOUT_I 37
SPKR_SB22
MIC_IN#_JACK40
EXT_MIC 37
HP_IN#_JACK37,40
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
AUDIO OUT
AMP
R0603
R0603
R0603 R0603
R0603
R0603
R2.0
Digital Area
R2.0
R2.0
AUDIO_AMP(G1420)
2.1
A8T
37 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
SPKR+
SPKL+
SPKL-
SPKR-
OPTIC_HP
SPDIF_O
OPTIC_VCC
AOUTR_C 2_AJK_R
2_AJK_L
HP_JACK_L
HP_L_SW
HP_IN#
INT_MIC_CON
HP_JACK_R
AOUTL_C
MIC_JACK
HP_IN#
OPTIC_HP
SPDIF_O
OPTIC_VCC
HP_IN#
HP_R_SW
SPKR-
SE/BTL#
SE/BTL#
SPKR+
SPKL-
SPKL+
MUTE
MUTE
DEPOP#
DEPOP#
SPKL+_MB_CON
SPKL-_MB_CON
SPKR+_MB_CON
SPKR-_MB_CON
SPKL+
HP_R_SW
SPKR+
HP_L_SW
EAPD
EXT_MIC
VREFOUT
AGND_A
+5VAMP
+3V
+12V
AGND_A
AGND_A
+5VAUD
AGND_A
AGND_A
+5VAUD
+5VS
+5VS
AGND_A
+5VAMP
AGND_A
+5VAMP
+5VS
+5VAMP
AGND_A
+5VAMP
AGND_A
+5VAUD
+3V
+5VAUD
+12V
+5VS
AGND_A
AGND_A
AGND_A
+5VAUD
R678
22K_1
L62 80/2A
D69
1SS355_*
12
CON30
INT_MIC_CON
3
4
1
2
SIDE1
SIDE2
1
2
D24
RB751V_40
1 2
R759 0
C507
100P
R67 0Ohm
1 2
R65 0Ohm
1 2
C504
1UF/X7R
Q35A
UM6K1N
2
C503
100P
D26
DAP202K
1
2
3
L70
1K/300mA
GS
D
3
2
1
Q37
2N7002
R66 0Ohm_*
1 2
L71 1K/300mA
R434
47K
C496 100P
L63 80/2A
C510 100P
C492
0.1U
C652 100P
C493
10U/10V
R69
4.7KOhm_*
C499
100P
U28 G1420F31UF
21
20
19
11
9
8
6
5
4
22
15
3
10
18
7
2
14
16
17
23
RLINEIN
RHPIN
RBYPASS
MUTE IN
MUTE OUT
SHUTDOWN
LBYPASS
LHPIN
LLINEIN
ROUT+
ROUT-
LOUT+
LOUT-
RVDD
LVDD
TJ
SE/BTL#
HP/LINE#
NC1
NC2
R81
22K_1_*
R428 12.7K_1
+
-
U29A
LM358MX
3
2
1
L68 1K/300mA
R441
100K R442 100
Q39B
UM6K1N
5
R451 15KOhm
R429
100K
C509 1UF/X7R
R432 100K
R677
22K_1
C490 1UF/X7R
C500
100P
L64 80/2A
R435
47K
R82
22K_1_*
R436 12.7K_1
R446
1K
G
S
D3
2
1
Q36
2N7002
R448
1KOhm
L69 1K/300mA
R751 0_*
R440 100
R450
2.2K
R438
2.2M
C491
10U/10V
R433 10K_1
R430 10K_1
C506
100P
R760 0
C698
100P_*
R431 100K
C505 0.1U
R71
0Ohm_*
R68 0Ohm_*
1 2
D25
1SS355
A
B
GND
VCC
Y
U27
SN74AHCT1G08DBVR
1
2
3 4
5
L60 80/2A
R449
1K
R447 0_*
C508
1UF/X7R
C501
1UF/X7R
R761 0
R670
100K
C497
0.1U
R445
1K
C498
100P
Q39A
UM6K1N
2
R437
47K
L61 80/2A
CE6 100U/6.3V
1 2
GS
D
3
2
1
Q66
2N7002
C502
100P
Q33
SI2301BDS
2 3
CE5 100U/6.3V
1 2
GS
D
3
2
1
Q34
2N7002
CON27
SPEAKER_CON
1
2
3
4
5
6
1
2
3
4
NC1
NC2
Q35B
UM6K1N
5
C489
0.1U
R72
0Ohm
C494
0.1U
+
-
U29B
LM358MX
5
6
7
L99 1K/300mA
OP_SD#23
MIC_IN_A36
VREFOUT_I36
SPDIF_A36
OUTL_A36
OUTR_A36
HP_JACK_L 40
SPDIF_O_JACK 40
HP_JACK_R 40
OPTIC_VCC_JACK 40
OPTIC_HP_JACK 40
HP_IN#_JACK 36,40
+3V 22,28,30,31,35,38,42
+5VAUD 36
+12V 25,35,40,67
+5VS 14,18,23,24,28,29,36,38,39,40,41,61
HP_L_CODEC36
HP_R_CODEC36
EAPD36
INT_MIC_JACK 40
EXT_MIC_JACK 40
EXT_MIC 36
ACZ_RST#_AUD22,36
VREFOUT 36
A
A
B
B
C
C
D
D
E
E
E E
D D
C C
B B
A A
Azalia MDC MODEM CON Bluetooth Module CON
TPM Module CON Camera Module CON
MDC,B/T,TPM,Camera & DISCHG
2.1
A8T
38 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
USBP3+
USBP3-
+5V_Camera
+3V
+3V
+3V +3VS
+1.8V
+1.5VS
+5VS
+2.5VS
+5V
+3VS
+5VS
+3VS
+5V
+1.5VS
+1.8V
+2.5VS
+3V
+3V
+3VA
+5V
C511
0.1U
C700
10U/16V
Q41B
UM6K1N_*
5
L96
90/370mA
CON39 TPM_CON
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
C684
0.1U
Q42B
UM6K1N
5
Q42A
UM6K1N
2
R457
330
L95 80/3A
Q40B
UM6K1N_*
5
Q40A
UM6K1N_*
2
CON32
BLUE_TOOTH_CON
1
2
3
4
5
6
7
8
9
10
11
12
GND1
USB_D+
USB_D-
RSVD
CLK
HW_DIS#
DATA
+3.3V
LED
GND2
HOLD1
HOLD2
C512
0.1U
GS
D
3
2
1
Q43
2N7002_*
R731 0_*
R452 39
R455
330_*
Q41A
UM6K1N_*
2
R182 0_*
R458
330
CON40
Camera_CON
4
3
2
1 5
6
4
3
2
1 SIDE1
SIDE2
R454
330
R183 0
CON31
BTOB_CON_12P
1 2
3 4
5 6
7 8
9 10
11 12
1 2
3 4
5 6
7 8
9 10
11 12
R456
150_*
R453
330
R459
330_*
CH_DATA_A30
BT_ON/OFF#22
ACZ_SDOUT_MDC22
ACZ_SDIN1_MDC22
ACZ_SYNC_MDC22
ACZ_RST#_MDC22 ACZ_BCLK_MDC 22
CH_CLK_A30
BT_LED41
USB_PN222
USB_PP222
PM_SUSC41,42 PM_SUSB41,42
CLK_TPMPCI20
LPC_FRAME#20,26,27,28,31
LPC_AD320,26,27,28,31
LPCTPM_RST#20
LPC_AD020,26,27,28,31
PM_SUS_STAT#22,26
LPC_AD2 20,26,27,28,31
INT_SERIRQ 20,26,28,34
LPC_AD1 20,26,27,28,31
PM_CLKRUN# 20,26,28,34
+5VS 14,18,23,24,28,29,36,37,39,40,41,61
+1.8V 5,7,8,9,10,65
+5V 9,16,18,25,28,31,40,41
+1.5VS 19,21,22,23,30,31,48
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,39,41,48,61,70
+2.5VS 5,11,14,15,16,18,48
+3V 22,28,30,31,35,37,42
DIS_FWH 27,28,31
SUS_CLK 22
USB_PP322
USB_PN322
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
KEYBOARD
IO Board
VGA_NUT
SCREW
MDC_NUT
TPM_NUT
CPU
FIXED HOLE
KB NUT
R2.0
DVI CONN & HOLE
2.1
A8T
39 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
DVI_DDCCLK_NV
DVI_DDCDAT_NV
+5V_DDC
BAT_S
+5VS
+5VS
+5VS
BAT
GND
BAT_S
+3VS
L78 80/2A
H15
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
PT7013
TPC28T
H29
hole_c87d87n
PT7018TPC28T 1
R73 10KL77 1K/300mA
_*
H34
F40M20_701130AS
R733 2.2K
PL7005 1KOhm/100Mhz
21
H8
CR315X354D110N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
PT7021TPC28T 1
H5
CT276B167D138
PT7011TPC28T 1
H33
DO276X39
PT7009TPC28T 1
H16
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H32
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H19
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H3
CT276B167D138
PT7010TPC28T 1
C334
0.1U
PL7006 1KOhm/100Mhz
21
PT7001
TPC28T
H36
B40M20
H2
L4E_1A
H31
CR315X354D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H14
CT217B315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H13
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H6
CT276B167D138
H20
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H9
CR315X354D110N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H1
L4E_1A
R74
100K
PL7001 1KOhm/100Mhz
21
H17
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
L76 1K/300mA
PL7003 680Ohm/100Mhz
21
H35
F40M20_701130AS
PCO701
BATT_CON_9P
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
NP_NC1
NP_NC2
H21
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
PL7002 1KOhm/100Mhz
21
L75 1K/300mA
H27
O295X413DO216X334
D17
BAV99_*
1
2
3
PT7012
TPC28T
H30
hole_c87d87n
H10
CR315X354D110N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
PT7017TPC28T 1
H25
L4E_1A
H18
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
H7
CR315X354D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
J1
EMI_SPRING_PAD
11
PL7004 680Ohm/100Mhz
21
PT7008TPC28T 1
H28
O295X413DO216X334
CON15
DVI_CON_24P
2
1
5
4
10
9
13
12
18
17
21
20
23
24
26
25
8
16
7
6
15
14
22
3
11
19
27
28
TMDS_DATA_2+
TMDS_DATA_2-
TMDS_DATA_4+
TMDS_DATA_4-
TMDS_DATA_1+
TMDS_DATA_1-
TMDS_DATA_3+
TMDS_DATA_3-
TMDS_DATA_0+
TMDS_DATA_0-
TMDS_DATA_5+
TMDS_DATA_5-
TMDS_CLK+
TMDS_CLK-
P_GND2
P_GND1
V_SYNC
HOT_PLUG_DETECT
DDC_DATA
DDC_CK
GND_for+5V
+5V_POWER
TMDS_CLK_Shield
TMDS_2/4_Shield
TMDS_DATA_1/3_Shield
TMDS_DATA_0/5_Shield
NP_NC1
NP_NC2
PT7019TPC28T 1
H12
C315D87N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
D10
FS1J4TP
12
H4
CT276B167D138
R732 2.2K
H11
CR315X354D110N
1
2
3
5
4
NP_NC
GND1
GND2
GND4
GND3
F4 1.5A/6V
12
DVI_DDCCLK_NV 16
DVI_TX3N_NV16
DVI_TX5P_NV16
DVI_CLKP_NV16
DVI_CLKN_NV16
DVI_TX3P_NV16
DVI_TX2N_NV16
DVI_TX4P_NV16
DVI_TX2P_NV16
DVI_TX0P_NV16
DVI_TX5N_NV16
DVI_DDCDAT_NV 16
DVI_TX1P_NV16
DVI_TX0N_NV16
DVI_TX1N_NV16
DVI_TX4N_NV16
+5VS 14,18,23,24,28,29,36,37,38,40,41,61
DVI_HDP_NV 16
TS# 68,69,71
SMD_BAT 28,69
SMC_BAT 28,69
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
DC IN
FAN CONTROL
ACIN_CONN
I/O PORT
Differential
Pair
Differential
Pair
FOR EMI
FAN_CTRL & ACIN
2.1
A8T
40 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+5VS_FAN
+5VUSB4
LTPA0-
LTPB0+
LTPB0-
LTPA0+
USBP4+
LTPB0-
LTPB0+
LTPA0-
USBP4-
LTPA0+
+5VUSB_4 +5VUSB4
USBP4+
MIC_IN#_JACK
USBP4-
A/D_DOCK_IN
+5VS
+5VS
+5V
+5V_USB4+5V
+12V
C316
0.1U
C444
0.1U/X7R
C442
0.1U
vcc
GND
NP_NC
P_GND
P_GND
P_GND
P_GND
CON25
DC_PWR_JACK_2P
1
2
7
6
5
4
3
C446
0.1U/X7R
L32 80/2A
T101
R400 1K
D53 RB751V_40
1 2
R129
10K
HOLD 1
HOLD 2
CON24
FAN_CON
1
2
3
C315
10U/10V
+
CE2
100U/6.3V
L53
150Ohm/100Mhz
21
T102
Comm on
Chok e
L51
IEEE1394
1
2
3
45
6
7
8
CON34 I/O_PORT_CON
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
T104
C441
10U/10V
Q38
PMN45EN
T103 T105
R131 0
T99
C447
0.1U/X7R
T98
D22 RB751V_40_*
1 2
F2 1.5A/6V
12
R130 0
U23
G993P1U
1
2
3
4 5
6
7
8
VEN
VIN
VO
VSET GND1
GND2
GND3
GND4
T100
A/D_DOCK_IN 42,68,69,70,71
FAN1_DC28
FAN1_TACH28
WATCHDOG28
INT_MIC_JACK 37
EXT_MIC_JACK 37
OPTIC_HP_JACK 37
HP_JACK_R 37
HP_IN#_JACK 36,37
HP_JACK_L 37
SPDIF_O_JACK 37
OPTIC_VCC_JACK 37
TPA0-_034
TPB0+_034
TPA0+_034
TPB0-_034
+5V 9,16,18,25,28,31,38,41
+5VS 14,18,23,24,28,29,36,37,38,39,41,61
USB_PN422
USB_PP422
MIC_IN#_JACK36
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
TOUCH PAD
CNT
HDD
LED
NUM
LED
CAP
LED
PWR
LED
PWR
LED
B/T
LED
Charger
LED
WLAN
LED
PWR
SW
B/T
SW
WLAN
SW
PADlock
SW
Internet
SW
Pwr4_Gear
SW
SW & LED & TP
2.1
A8T
41 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
GATE_PWR_SW#
TP_RIGHT#
TP_RIGHT#
TP_LEFT#
INTERNET_#
GATE_PWR_SW#
INTERNET_#
TP_LEFT#
INTERNET_#
+5V+5VS_TP
+12VS
+5VS_TP
+3VS +3VS+3VS
+5VS +5VS +3VS
+5VS
+5VS
+5V
+3VS
+12VS
+3VA
+3VS
+5VS
+3VS
+5V
C452
100P_*
R406
390
LED2
GREEN
Q10
2N7002
LED8
GREEN
C454
100P_*
R407
390
SW4
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
R741 10K
D66 1SS355
12
C79
0.1U
SW6
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
LED3
GREEN
U50A SN74LVC74APWR
2
3
5
6
7 14
D
CK
Q
Q#
GND VCC
R409
100K
GS
D
3
2
1
Q12
2N7002
R753 10K
C458
0.1U
C450
100P_*
C74 0.1U
L54 1K/300mA
R403
200
LED5
GREEN
Q31A
UM6K1N
2
SW2
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
Q32
2N7002
C455
100P_*
C459
0.1U
Q30B
UM6K1N
5
D64 1SS355
1 2
Q31B
UM6K1N
5
C453
100P_*
CON26
TOUTH_PAD_CON
12
11
10
9
8
7
6
5
4
3
2
1
13
14
12
11
10
9
8
7
6
5
4
3
2
1
SIDE1
SIDE2
SW8
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
LED9
GREEN
R408
390
R743 1K
SW7
SWITCH_4P
1
2 3
4
5 6
SW3
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
LED1
GREEN
U50B SN74LVC74APWR
9
8
12
147
11
Q
Q#
D
VCCGND
CK
SW5
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
LED4
GREEN_*
R405
390
R752
390_*
C77
1UF/X7R
C451
100P_*
SW9
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
Q30A
UM6K1N
2
R401
200
C448
100P_*
R691
390
C457
0.1U
GS
D
3
2
1
Q50
2N7002_*
T106R411
100K
SW1
TACT_SWITCH_5P
1
3
2
5
4
1
3
2
5
4
R739
100K
T302 1
C456
100P_*
LED7
GREEN
C449
100P_*
R402
200
Q16
2N7002
LED6
ORANGE
LN1
120/150mA
1 2
3 4
5 6
7 8
R742
10K
R740 100K
INTDATA_5S28
INTCLK_5S28
MARATHON_#28 GATE_PWR_SW#42BLUETOOTH_#28 PANLOCK_#28WIRELESS_#28
HDD_LED#24
BT_LED38
CHG_LED_UP69
802_LED_EN# 22
+5V 9,16,18,25,28,31,38,40
+3VS 5,8,9,13,14,15,16,17,18,19,20,21,22,23,24,26,27,28,29,30,31,34,36,38,39,48,61,70
+5VS 14,18,23,24,28,29,36,37,38,39,40,61
+12VS 67
LID_SW#17,42
SWDJ_EN 28
MSK_INSTKEY#28
PM_SUSB38,42
PM_SUSC38,42
INTERNET_#28
PANLOCK_LED28
802_ON/OFF# 30
CAP_LED#28
NUM_LED#28
1Hz
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
POWER-ON SEQUENCE
2.1
A8T
42 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PWR_SW#
PWRBTN#
PWRBTN#
PWR_SW
PM_SUSC
PWR_SW#
PWR_SW
+3VSUS
+3VA
+3VSUS
+3VSUS
+3VA
+3VA
+3V
+3VA
+3V
+3VA
+3VA
+3VA
+3VA
+3VA
+3VA
+3VA
+3VA
+3VA
+3VSUS
U21B SN74LVC74APWR
9
8
12
147
11
Q
Q#
D
VCCGND
CK
C654 1UF/X7R
C685
0.1U/X7R
C519
0.1U
T303 1
R475
1M
VCC
GND
U30F
74LVC14APW_T
1312
Q46A
UM6K1N
2
D27 1SS355
12
C699 0.1U/X7R
R729
100K
C520
0.1U/X7R
R766
100K
R471
100K
R726 100K
VCC
GND
U30E
74LVC14APW_T
1110
R730
100K
R7145
10KOhm
C517
0.1U/X7R
R472 100K
C514
0.1U
R728
100K
R463 0
R476 1M
D31
1SS355
12
R461 20K
Q46B
UM6K1N
5
D30 1SS355
1 2
R468
100K
JP8
OPEN_PIN
C686
0.1U/X7R
GS
D
3
2
1
Q103
2N7002
R725
1M
R727 100K
R473
1M
VCC
GND
U30A
74LVC14APW_T
1 2
VCC
GND
U30D
74LVC14APW_T
9 8
Q47
2N7002
R767 0_*
VCC
GND
U30C
74LVC14APW_T
5 6
C481
0.1U
RS#
VOUT
NC
SUB GND
VCC
U49 PST9128NR
1
4
5
R656 1K
VCC
GND
U30B
74LVC14APW_T
3 4
R467 100K
D63
DAN202K
1
2
3
GS
D
3
2
1
Q49
2N7002
U21A SN74LVC74APWR
2
3
5
6
7 14
D
CK
Q
Q#
GND VCC
T108
C521
0.1U
GS
D
3
2
1
Q106
2N7002
C515
1UF/X7R
+3VSUS 5,17,20,22,23,28,29,32,46,48,70
KBCRSM28
OTP_RESET# 5FORCE_OFF#46,70
PM_SUSB 38,41
LID_SW# 17,41
VSUS_ON 31,46,67
+3VA 22,38,41,48,71
SUSB#22,31,32,67,70
GATE_PWR_SW# 41PM_PWRBTN#22
A/D_DOCK_IN 40,68,69,70,71
SUSC#22,67
+3V 22,28,30,31,35,37,38
PM_SUSC 38,41
LID_KBC# 28
PM_RSMRST# 22
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Revision History
Power:
System:
HISTORY
2.1
A8T
43 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1394A
USB
MIC
LINE_OUT
SPDIF
I/O PORT
2.1
A8T
44 55
Friday, July 21, 2006
Albert Su
<Core Design>
PROJECT:
SHEET OF
DATE:
REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
HP_JACK_L_I/O
OPTIC_VCC_JACK_I/O
OPTIC_HP_JACK_I/O
HP_IN#_JACK_I/O
OPTIC_VCC_JACK_I/O
INT_MIC_JACK_I/O
HP_IN#_JACK_I/O
SPDIF_O_JACK_I/O
INT_MIC_JACK_I/O USBP2+_I/O
EXT_MIC_JACK_I/O
USBP2-_I/O
OPTIC_HP_JACK_I/O
SPDIF_O_JACK_I/O
HP_JACK_R_I/O
+5VUSB2_I/O
+5VUSB2_I/O
HP_JACK_L_I/O
EXT_MIC_JACK_I/O
HP_JACK_R_I/O
LTPA0-_I/O
LTPA0+_I/O
LTPB0-_I/O
LTPB0+_I/O
USBP2-_I/O
USBP2+_I/O
LTPA0+_I/O
LTPA0-_I/O
LTPB0+_I/O
LTPB0-_I/O
MIC_IN#_JACK_I/O
MIC_IN#_JACK_I/O
GND
GND
GNDGND
GND
GNDGND
IO_H4
O63X157DO39X98
IO_CON4
EXT_MIC_CON
1
2
3
4
5
6
9
10
7
8
1
2
3
4
5
6
NP_NC1
NP_NC2
P_GND1
P_GND2
GND
VCC
Vin
MS
IO_CON2
PHONE_CON
C
9
11
12
B
A
6
1
4
5
7
10
IO_CON5
USB_CON_1X4P
4
3
2
1
4
3
2
1
IO_H1
O63X157DO39X98
IO_CON1
1394_CON
5
7
6
8
1
2
3
4
P_GND1
P_GND3
P_GND2
P_GND4
1
2
3
4
IO_CON3
I/O_PORT_CON
1
3 4
5 6
7 8
9
11
10
12
13 14
1615
17 18
20
2
19
IO_R2 0_0603
IO_H2
O63X157DO39X98
IO_H3
O63X157DO39X98
IO_R1 0_0603
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ON: EN>2V (A/D_DOCK_IN:17V)
20050406
OFF: EN<0.6V(A/D_DOCK_IN:5.1V)
+5VCHG, +5VLCM, +2.5VREF
Ref: 1.24V
BATTERY IN CIRCUIT
3/9 for
soft
start
5/26 PD ISSUE
Ibat=2.5*200k/256k/100/0.003=6.51A
6/7 for bat
current
limit
6/14 EE change
6/14 EE change
Custom
54 55Friday, July 21, 2006
ASUSTECH
POW ER_SWITCH_5VLCM
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
+5VCHG
BATT_PWRLMT
A/D_DOCK_IN
AC_BAT_SYS
AC_BAT_SYS_IN
BAT
GND
+5VO
+5VCHG
A/D_DOCK_IN
+2.5VREF
+5VLCM
+3VA
GND
+2.5VREF
+5VLCM
+5VLCM
PQ7104A
UM6K1N
2
PT7111
TPC28T
PT7109
TPC28T
PR7113
6.8KOhm
1 2
PT7113
TPC28T
PT7112
TPC28T
3
PQ7101
TPC8107
1
2
3
45
6
7
8
PU7102
MIC5235YM5
3 4
5
2
1
EN NC or ADJ
OUT
GND
IN
PT7106
TPC28T
PT7116
TPC28T
PQ7104B
UM6K1N
5
PR7112
18KOhm
1 2
PT7104
TPC28T
PT7105
TPC28T
PT7114
TPC28T
G
S
D3
2
1
PQ7106
2N7002
PT7107
TPC28T
PR7109
1KOhm
PT7103
TPC28T
PC7106
1UF/10V
PQ7102
TPC8107
1
2
3
45
6
7
8
@
PT7115
TPC28T
+
-
-
+
A+
A-
B+
B-
AO
BO
VCC
GND
PU7103
LM358DR
1
2
3
4
8
7
6
5
PR7110
31.6KOHM
1 2
PU7104
MAX4073HAXK_T
1
2
3 4
5
OUT
GND
VCC RS+
RS-
PT7101
TPC28T
PT7102
TPC28T
PT7110
TPC28T
@
PR7122
100KOhm
1%
12
1%
PD7104
1SS355
12
1%
PT7118
TPC28T
1
PQ7105
TPC8107
1
2
3
4 5
6
7
8
PD7103
F02JK2E
1
2
3
PR7111
10KOhm
PC7105
1UF/25V
PT7117
TPC28T
PR7102
10mOhm
1 2
PT7108
TPC28T
PC7104
2.2UF/16V
MAX8725_PDL68
MAX8725_PDS68
TS#39,68,69
CHG_SRC68
BAT_IN_OC# 28
CSSP 68
PWRLMT#5,22,68
CSSN 68
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SWITCH
TPS51020
+5VO
ON_SUS
+5VCHG
(20mA)
SWITCH
+5VO
(100mA)
78L05
(Regulator) (F02JK2E)
SI4925BDY
(Charger)
MAX8725
BAT
TPC8107
CPU_VDD_FB,
CPU_VDD_FB#,CPU_VID
CPUPWR_GD
+VCORE
MAX8760 (35A)
A/D_DOCK_IN
AC_BAT_SYS
+3VO
LM4040BIM +2.5VREF (500uA)
+5VLCM
(6A)
(6.3A) +3V (0.6A)
(2.1A)
+0.9VS
(4.5A)
(0.5A)
+1.8VS
SUSC#_PWR
(18.2A)
SUSC#_PWR
(4.5A)
(5.4A)
+1.8VO
+0.9VO
ISL6227
+1.2VS
+1.5VSUS
(0.12A)
SI9183
(0.7A)
+3VSUS
SUSC#_PWR
HTVDD_EN
SUSB#_PWR
SUSB#_PWR
SUSB#_PWR
SUSB#_PWR
VSUS_GD#
(3.6A)
+5VS
(Regulator)
(4A)
+3.3VS
ON_SUS
SUSC#_PWR (2.0A)
+5V
+5VAO
MIC5236BM +3VAO
+1.2VSUS
ISL6227
SUSB#_PWR
SUSB#_PWR
+1.2VO
+1.0VO +1.0VS
(3.75A)
+1.2VS_HT
(3.3A)
+1.8V
+0.9V
(10A)
(4.0A)
+3VA (0.06A)
MAX1844 VGA_VCORE (16.5A)
SUSB#_PWR
Custom
55 55Friday, July 21, 2006
ASUSTECH
POWER DIAGRAM
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(35A)
VREF = 2V
REF =
300kHz,
PR6122 close
to PL6101
3/8 emi
issue
3/8 emi
issue
SKIP#>2.7V , TWO PHASE PWM MODE
2.3V>SKIP#>1.2V , TWO PHASE PFM MODE
SKIP#<0.8V , SINGLE PHASE PFM MODE
CPU_PSI#:HIGH, SKIP#=5V
CPU_PSI#:LOW, SKIP#=1.74V
5/10 change to change OCP >40A
5/26 VDS issue
5/26 VDS issue
6/14 EE change
Custom
61 55Friday, July 21, 2006
ASUSTek
POWER_VCORE
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
+VCORE
OAIN+
OAIN-
OAIN+
OAIN-
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
CPUPWR_GD
CPU_VDD_FB
CPU_VDD_FB#
CPU_VID5
OAIN+
+VCORE
AC_BAT_SYS
+VCORE
AC_BAT_SYS
+5VS
+3VS
+5VS
PT6107 TPC28T
1
PT6119
TPC28T
PQ6109A
UM6K1N
2
PD6102
EC31QS04
PT6105
TPC28T
PC6114
100PF/50V
PT6126
TPC28T
PQ6109B
UM6K1N
5
PD6103
RB717F
1
2
3
PT6110 TPC28T
1
PQ6104
FDS6676S
PC6113
0.1UF/50V
PT6127
TPC28T
PT6133
TPC28T
1
PT6112
TPC28T
+
PR6124
1Ohm
1 2
PQ6107
FDS6676S
PT6125
TPC28T
PR6125 1KOhm
1 2
PT6118
TPC28T
PR6132
121KOhm
@
12
@
PR6129
10Ohm
PD6101
EC31QS04
+
PT6121
TPC28T
1
PR6133
200KOhm
12
PC6111
0.22UF/25V
12
PT6103
TPC28T
PT6120
TPC28T
PQ6105
FDS6298
PT6101
TPC28T
PT6129
TPC28T
PC6119
0.1UF/50V
@
PT6102
TPC28T
PT6115
TPC28T
PC6112 470PF/50V
1 2
PQ6108
FDS6676S
+
+
PR6120 0Ohm
12
PR6130 10Ohm
12
PR6102
1mOhm
1 2
PT6131
TPC28T
PR6126 1KOhm
1 2
PR6144
53.6KOhm
1%
PR6109
1.82KOhm
PT6113
TPC28T
PR6131
0Ohm
1 2
PT6116
TPC28T
PT6130
TPC28T
+
PT6109 TPC28T
1
PT6117
TPC28T
PR6142
0Ohm
r0603_h24
1 2
PQ6106
FDS6298
PQ6102
FDS6298
PR6112
1Ohm
1 2
PL6102
0.56UH
21
PT6108 TPC28T
1
PC6101
1000PF/50V
PT6132
TPC28T
1
PQ6101
FDS6298
PT6123
TPC28T
PR6121 470Ohm
@
12
+
PR6140
100KOhm
PC6107
1000PF/50V
@
1 2
PQ6103
FDS6676S
PR6139
100KOhm
1%
PR6119 0Ohm
12
PT6104
TPC28T
PC6116
4.7UF/16V
PC6106
0.22UF/25V
12
PT6106 TPC28T
1
PR6141
470KOhm
@
PC6104
0.1UF/50V
PT6124
TPC28T
PR6143 0Ohm
r0603_h24
1 2
PR6127
10Ohm
12
PR6122 10KOHM @
1 2
PR6136
200KOhm
PT6122
TPC28T
PR6123 1MOhm
1 2
+
PL6101
0.56UH
21
PT6128
TPC28T
PT6114
TPC28T
PT6111 TPC28T
1
+
PU6101
MAX8760ETL
11
12
13
14
15
16
17
18
19
20 31
32
33
34
35
36
37
38
39
40
41
GND1
CCV
GNDS
CCI
FB
OAIN-
OAIN+
SKIP#
D5
D4 PGND
DLS
DHS
LXS
BSTS
V+
CMP
CMN
CSN
CSP
GND2
PR6128
1.82KOhm
PC6108
4.7UF/16V
CPU_VID35
CPU_VID15
CPU_VID25
CPU_VID45
CPUPWR_GD19,70
CPU_VDD_FB#5
CPU_VRON19
CPU_VDD_FB5
CPU_VID55
CPU_VID05
CPU_PSI#5
CPU_VRON_PWR67
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(6A)
(6.3A)
(0.02A)
(REF=1.24V)
1.24*(95.3+845)/95.3=12.235
F=450KHZ
(0.7A)
11/02
11/23/05
3/3
3/3
Custom
62 55Friday, July 21, 2006
ASUSTECH
2.1
A8T
Eric_Ko
POWER_SYSTEM
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
VSUS_GD#
RUN_5VO
RUN_3VO
+5VAO
RUN_5VO
+12VO
VSUS_ON
VSUS_GD#
+5VAO
+3VSUS
RUN_3VO
+3VO
AC_BAT_SYS +5VAO
+5VO
+5VO
AC_BAT_SYS
+3VSUS
+12VSUS
AC_BAT_SYS
AC_BAT_SYS
+5VAO
PC6204
0.1UF/25V
PT6217
TPC28T
1
PT6209 1
PR6205
0Ohm
1 2
PC6208
1UF/25V
PL6202
3.8UH
21
PL6201
3.8UH
21
PC6206
0.1UF/50V
1 2
+
PCE624
150UF/4V
PR6206
1.8KOhm
1 2
PT6203
TPC28T
+
PT6202
TPC28T
PQ6202
SI4800BDY
PQ6203
SI4894DY
PT6212
TPC28T
PR6209
10KOhm
1 2
PT6201
TPC28T
PC6209
3300PF/50V
12
PT6204
TPC28T
PC6205
3900PF/50V
12
PU6201
MIC5235YM5
3 4
5
2
1
EN NC or ADJ
OUT
GND
IN
PC6211
4.7UF/16V
PR6202
0Ohm
1 2
PD6203 RB751V_40
12
PR6210
2.7KOhm
1 2
PC6207
1UF/10V
PU6202
TPS51020
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INV1
COMP1
SSTRT1
SKIP#
VO1_VDDQ
DDR#
GND
REF_X
ENBL1
ENBL2
VO2
PGOOD
SSTRT2
COMP2
INV2
VBST1
OUT1_U
LL1
OUT1_D
OUTGND1
TRIP1
VIN
TRIP2
VREG5
REG5_IN
OUTGND2
OUT2_D
LL2
OUT2_U
VBST2
PT6219
TPC28T
PT6205
TPC28T
PR6201 0Ohm
12
PR6215
10KOhm
1 2 PT6213
TPC28T
+
PT6220
TPC28T
1
PC6216
4.7UF/16V
PD6202
FS1J4TP
PT6208
TPC28T
PQ6201
SI4894DY
PT6211
TPC28T
PT6216
TPC28T
PR6218 1KOhm
12
PR6220
95.3KOhm
PQ6204
SI4800BDY
PC6201
4.7UF/16V
PT6214
TPC28T
PT6218
TPC28T
1
PT6210
TPC28T
PT6207
TPC28T
PR6211
0Ohm
12
+
PCE622
100UF/6.3V
PJP621
1MM_OPEN_5MIL
@
1 2
1 2
PR6219
845KOhm
1 2
PC6202
1UF/25V
PC6210
0.1UF/50V
1 2
PD6201
FS1J4TP
PT6215
TPC28T
PT6206
TPC28T
VSUS_ON31,42,67
VSUS_GD#70
FORCE_OFF#42,70
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
0CR_VID1
0
(6.1A)
F=300KHZ
1
(2.1A)
CR_VID0
1.0V
VREF = 0.9V
1.11V1.21V
1
0
0
+1.0VO
(2.1A)
(6.1A)
4/19 CHANGE
6/14
EE
change
old 1.07k
old 196k
Custom
63 55Friday, July 21, 2006
ASUSTECH
POW ER_I/O_1.2VO & 1.0VO
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
+1.0VO_VSEN
+1.0VO_VSEN +1.0VO_VSEN
+1.2VO
+1.0VO
+5VO
+3VS
+1.2VO
+1.0VO
+3VS
AC_BAT_SYS
+1.2VS
+1.2VS_CORE
PT6308
TPC28T
PR6309
0Ohm
@
PR6319
100KOhm
@PR6317
10KOhm
@
PC6311 0.01UF/50V
12
PC6302
0.1UF/50V
PT6312
TPC28T
PR6308
0Ohm
@
12
+
PCE631
390UF/2.5V
PR6303
0Ohm
PQ6305A
UM6K1N
@
2
PT6309
TPC28T
PR6318
4.53KOHM
@
PC6313
0.01UF/50V
@
PL6301
3.8UH
21
+
PR6310
0Ohm
PL6302
3.8UH
21
PR6301 0Ohm@
12
+
PCE634
390UF/2.5V
PQ6304
SI4894DY
PR6321
100Ohm
1 2
PR6322
100Ohm
1 2
PR6312 6.81KOhm
12
PR6314 6.81KOhm
12
PT6310
TPC28T
@
PQ6305B
UM6K1N
@
5
PJP633
3MM_OPEN_5MIL
@
12 12
@
PT6304
TPC28T
D1_1
D1_2
G2
G1
S2 S1/ D2_1
S1/D 2_2
S1/D 2_3
PQ6303
SI4914DY
5
6
7
81
2
3
4
PC6314
0.01UF/50V
@
PC6306 4.7UF/6.3V
1 2
PT6311
TPC28T
PR6320
100KOhm
@
PJP631
3MM_OPEN_5MIL
@
1 2
1 2
PQ6301B
UM6K1N
@
5
PC6312 0.01UF/50V
1 2
PT6305
TPC28T
PQ6302
SI4800BDY
PT6303
TPC28T
PQ6301A
UM6K1N
@
2
PT6307
TPC28T
PR6315
18.2KOhm
PT6302
TPC28T
PR6306
2.1KOhm
1 2
PT6306
TPC28T
@
PC6301
0.1UF/25V
PJP632
3MM_OPEN_5MIL
@
12 12
PU6301
ISL6227CAZ_T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
LGATE1
PGND1
PHASE1
UGATE1
BOOT1
ISEN1
EN1
VOUT1
VSEN1
OCSET1
SOFT1
DDR
VIN
VCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
ISEN2
EN2
VOUT2
VSEN2
OCSET2
SOFT2
PG2/REF
PG1
PR6307
1.2KOhm
1 2
PT6313
TPC28T
PT6301
TPC28T
PD6302
RB717F
+3VS 5,13,14,15,19,20,21,22,23,39,48,61,67,70
SUSB#_PWR16,67
1.2VO_1.0VO_PWRGD70
CR_VID1 22
CR_VID0 22
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Vref = 1.23V
IOUT = 40 ~ 60mA
(0.12A)
(2A)
Vref=1.215V
+3VA
(0.85A)
+1.5VS
Von=0.8V
+2.5VS
+1.5VSUS
+1.5VS_VGA
3/13
change
3/13
change
3/13 change
3/13 change
3/13 change
3/13 change
3/13 change
6/14 EE change
6/14 EE change
C
64 55Friday, July 21, 2006
ASUSTEC H
POWER_I/O_LDO
2.1
A8T
Eric_Ko
<Core Design>
Size Project N ame Rev
Date: Sheet of
Title :
Engineer:
AC_BAT_SYS
+3VSUS
+1.5VO
+3VSUS
+5VO
+5VO
+1.5VSUS
+3VAO
+2.5VS
+2.5VO
+1.2VS_H T
+0.9V
+1.5VS
+3VS
+3VS
+3VAO
+3VA
+3VS
+1.8VS
+3VO
+3VA
+5VO
+1.8VS
+1.5VS_VG
+1.5VO_VG
+1.8VS
+1.8VS
PC6418
0.1UF/25V
PJP647
2MM_OPEN_5MIL
1 2
1 2
PU6405
CM8562GISTR
1
2
3
4 5
6
7
8
VIN
VFB
VOUT0
VOUT1 RE FEN
VCCA
AGND
PGND
PT6415
TPC28T
PC6410
0.22UF/10V
PJP648
2MM_OPEN_5MIL
1 2
1 2
PT6405
TPC28T
+
PCE641
150UF/2V
PT6410
TPC28T
PJP646
1MM_OPEN_5MIL
@
1 2
1 2
B
C
E
1
2
3
PQ6406
PMBS3904
PR6417
100KOhm
PR6413
20KOhm
GS
D
3
2
1
PQ6405
2N7002
PJP641
1MM_OPEN_5MIL @
1 2
1 2
PC6402
0.1UF/25V
PR6414
100KOhm
PR6411
23.7KOhm
1 2
PR6402
18.2KOhm
PT6407
TPC28T
PT6416
TPC28T
PC6414
0.22UF/10V
PT6401
TPC28T
PJP645
1MM_OPEN_5MIL
@
1 2
1 2
PT6409
TPC28T
PU6404
CM8562GISTR
1
2
3
4 5
6
7
8
VIN
VFB
VOUT0
VOUT1 RE FEN
VCCA
AGND
PGND
PT6402
TPC28T
PT6403
TPC28T
PC6405
1UF/25V
PT6408
TPC28T
PR6416
165KOhm
PJP644
1MM_OPEN_5MIL
@
1 2
1 2
PR6404
16.9KOhm
PR6407
10KOhm
PC6407
0.1UF/25V
c0603
@
PT6411
TPC28T
B
C
E
1
2
3
PQ6404
PMBS3904
PT6417
TPC28T
PT6422
TPC28T
PR6423
18.2KOhm
PR6401
165KOhm
PT6421
TPC28T
GS
D
3
2
1
PQ6403
2N7002
PC6413
0.1UF/25V
PR6410
100KOhm
PC6409
1UF/10V
PC6404
10UF/6.3V
PR6426
51KOhm
PT6423
TPC28T
PC6411
0.1UF/25V
c0603
@
PT6414
TPC28T
PJP642
2MM_OPEN_5MIL
@
1 2
1 2
PT6420
TPC28T
PT6404
TPC28T
PT6418
TPC28T
PT6413
TPC28T
PC6419
10UF/10V
PC6408
4.7UF/6.3V
PR6408
100KOhm
PU6402
CM8562GISTR
1
2
3
4 5
6
7
8
VIN
VFB
VOUT0
VOUT1 RE FEN
VCCA
AGND
PGND
PT6406
TPC28T
PR6418
18.2KOhm
PR6409
0Ohm
1 2
PJP643
2MM_OPEN_5MIL
@
1 2
1 2PU6403
MIC5236Y M
1
2
3
4
8
7
6
5
ADJ
IN
OUT
EN
GND4
GND3
GND2
GND1
PR6420
82KOhm
PT6419
TPC28T
PR6419
100KOhm
+
PU6401
SI9183DT
1
2
3
4
5
VIN
GND
SD#
FB
VOUT
+
PCE643
150UF/2V
MEM_VLD 19
HT_VLD 19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FB=AVDD,OUTPUT=1.8V
For output adjustable
For foldback
current limit
6/29 modify ocp
point
H=4.0mm
(1.0A)
VILIM=0.905V,
Set OCP to
12.57A
6/29
change
(12A)
(12A)
(1.0A)
5/26 VDS issue
Custom
65 55Friday, July 21, 2006
<OrgName>
POWER_I/O_DDRII
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
+1.8VO
+5VO
+1.8V
AC_BAT_SYS
+0.9V
+1.8VO
+0.9VO
PL6501
1.8UH
21
PT6507
TPC28T
PT6509
TPC28T
PD6503
1SS355
12
PT6511
TPC28T
PT6501
TPC28T
PT6502
TPC28T
PQ6501
FDS6298
PR6507
0Ohm
@
PC6518
0.1UF/25V
PC6510
0.22UF/10V
PR6509
1Ohm
1 2
PR6513
124KOhm
1%
PT6508
TPC28T
PJP651
3MM_OPEN_5MIL
@
1 2
1 2
PC6506
0.22UF/25V
12
PC6508
0.033UF/16V
PC6517
4700PF/50V
1 2
+
PU6501
MAX8632ETI
1
2
3
4
5
6
7 15
16
17
18
19
20
21
TON
OVP/UVP
REF
ILIM
POK1
POK2
STBY# FB
OUT
VIN
DH
LX
BST
DL
PR6514 10Ohm
12
PR6508
0Ohm
@
12
PT6506
TPC28T
PR6515
10KOhm
1%
PT6503
TPC28T
PR6511
150KOhm
1%
PJP653
3MM_OPEN_5MIL
@
1 2
1 2
PD6502
RB751V_40
1 2
PR6504
0Ohm
PC6504
0.033UF/16V
PR6510 22KOhm
12
PR6506
22KOhm
12
+
PD6501
FS1J4TP
PT6510
TPC28T
PJP654
1MM_OPEN_5MIL
@
1 2
1 2
PR6512
0Ohm
@
12
PT6512
TPC28T
PT6504
TPC28T
PR6502
0Ohm
@
12
PT6505
TPC28T
PR6501
15.8KOhm
12
PJP652
3MM_OPEN_5MIL
@
1 2
1 2
PR6505
0Ohm
@
SUSC#_PWR67
SUSC#_PWR67
DDR_PWRGD70
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
(4.08A)
(5.18A)
(4.137A)
(0.81A)
(0.01A)
(0.01A)
FOR TEST
(3.0A)
(2.62A)
(0.5A)
11/17
3/6 for
timing
issue
3/13
change
3/13 change
3/13 change
3/14
add
6/29 change for power sequence
Custom
67 55Friday, July 21, 2006
ASUSTEC H
POWER_LOAD_SY STEM
2.1
A8T
Eric_Ko
<Core Design>
Size Project N ame Rev
Date: Sheet of
Title :
Engineer:
SUSB#_P WR
SUSC#_PWR
SUSB#_P WR
SUSC#_PWR_ON
SUSC#_PWR_ON
SUSB#_P WR_ON
HTVDD_EN
1.2VHT_EN_ON
SUSB#_P WR_ON
1.2VHT_EN_ON
SUSC#_PWR
+3V
+5VO
+2.5VO
AC_BAT_SYS
+3VO
+3VA
+VCORE
+5VAO
+1.8VO
+3VO
+12VS
+5VS
+3V+3VO
+1.8VS
+3VS
+12VSUS
+3VO
+3VA
+1.2VO
+3VO
+5VO
+12V
+12VSUS
+12VSUS
+3VS
+3VSUS
+1.8VS
+1.2VS_H T
+12V
+5VCHG
+12VS
+1.8VO
+2.5VS
+2.5VREF
+1.2VSUS
+5V
+0.9V
+1.8V
+1.2VS_H T
+1.5VSUS
+1.2VS
BAT
+5VLCM
+5VS
+3VO
+5VO
+5V
+1.0VO
+12VSUS
+3VAO
+0.9VO +0.9VS
+0.9VS
+1.2VO
PR6716
100KOhm
PJP673
SGL_JUMP
@
1 2
1 2
@
PJP674
SGL_JUMP
@
1 2
1 2
PQ6701B
UM6K1N
5
PR6713
10KOhm
12
PT6734
TPC28T
PT6701
TPC28T
PT6713
TPC28T
PT6724
TPC28T
PT6728
TPC28T
SD
G
PQ6702
SI4800BDY
1
2
3
5
6
7
8
4
PT6717
TPC28T
PT6735
TPC28T
PC6701
0.1UF/25V
PR6707
100KOhm
PT6709
TPC28T
PR6702
100KOhm
S
D
G
PQ6704
PMN45EN
1
2
3
5
6
4
PT6720
TPC28T
PR6717
470KOhm
@
PC6710
0.1UF/25V
@
PC6706
0.1UF/25V
PT6731
TPC28T
PJP672
SGL_JUMP
@
1 2
1 2
PT6710
TPC28T
PT6702
TPC28T
PT6732
TPC28T
PQ6703B
UM6K1N
5
PT6721
TPC28T
PT6705
TPC28T
PC6702
0.1UF/25V
PR6715
100KOhm
PR6714
1KOhm
PT6711
TPC28T
PT6718
TPC28T
DRAIN_1
SOURCE_1
SOURCE_2
GATE_1 GATE_2
SOURCE_4
SOURCE_3
DRAIN_2
PQ6711
FDW2501NZ
5
6
7
81
2
3
4
PQ6701A
UM6K1N
2
DRAIN_1
SOURCE_1
SOURCE_2
GATE_1 GATE_2
SOURCE_4
SOURCE_3
DRAIN_2
PQ6706
FDW2501NZ
5
6
7
81
2
3
4
PQ6703A
UM6K1N
2
PR6710
1KOhm
PT6727
TPC28T
PT6725
TPC28T
S
D
G
PQ6710
PMN45EN
1
2
3
5
6
4
PR6706
100KOhm
PQ6712
UMC4N
@
PT6719
TPC28T
@
PR6709
10KOhm
12
PT6722
TPC28T
PC6708
0.1UF/25V
PT6708
TPC28T
PQ6707A
UM6K1N
2
PT6726
TPC28T
PT6723
TPC28T
DRAIN_1
SOURCE_1
SOURCE_2
GATE_1 GATE_2
SOURCE_4
SOURCE_3
DRAIN_2
PQ6705
FDW2501NZ
5
6
7
81
2
3
4
PT6716
TPC28T
PT6714
TPC28T
PJP671
SGL_JUMP
@
1 2
1 2
PT6715
TPC28T
DRAIN_1
SOURCE_1
SOURCE_2
GATE_1 GATE_2
SOURCE_4
SOURCE_3
DRAIN_2
PQ6708
FDW2501NZ
5
6
7
81
2
3
4
PC6712
0.1UF/25V
PC6704
0.1UF/25V
PQ6707B
UM6K1N
5
PR6719
470KOhm
@
PT6704
TPC28T
PT6730
TPC28T
PC6703
0.1UF/25V
PR6703
10KOhm
1 2
PT6707
TPC28T
PQ6709
UMC4N
PT6729
TPC28T
PR6711
100KOhm
PT6712
TPC28T
PT6733
TPC28T
PR6701
100KOhm
@
PT6706
TPC28T
+3V 22
+5VO 5,46,47,48,65,71
+2.5VO 48
+3VA 22,38,41,48,71
+3VO 46,48
+VCORE 5,7,61
+5VAO 46,70
SUSB#22,31,32,42,70
SUSB#_P WR16,47
+12VSUS 46
CPU_VRO N_PWR 61
+1.2VS_H T 4,5,7,11,15,48
SUSC#_PWR65
SUSC#22,42
+1.2VSUS
+5VLCM 68,69,70,71
+3VS 5,13,14,15,19,20,21,22,23,39,47,48,61,70
+2.5VS 5,11,14,15,48
+5VCHG 68,69,71
+1.8VO 65
+0.9V 7,48,65
+5V 31
+1.8V 5,7,10,65
+1.5VSUS 23,48
+12V 25,35,37,40
+5VS 14,23,61
+2.5VREF 68,69,70,71
BAT 39,68,71
+3VSUS 5,20,22,23,32,46,48,70
+1.2VS 11,12,13,14,15,23,47
+1.8VS 5,15,17,48
+12VS 41
+1.0VO 47
+3VAO 48
HTVDD_EN19
+0.9VS 16
AC_BAT_SYS 16,17,46,47,48,61,65,68,71
+1.2VO 47
VSUS_ON 31,42,46
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCTL= 1.615V
4.46A * 10mOHM = 44.6mV
=> Iin(max)=4.6A
Charge Current Ichg = [0.075V/Rsense(CHG)]*[ICTL/3.6V]
90W / 19V * 0.941 = 4.46A
=> Vbatt = 4.2V
LDO : 5.4V
Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells
AD_IINP(5%) , R(0.7%) , 2.5VERF(0.2%) = 5.9%
VICTL= 0.18V
VICTL< 0.8V or DCIN < 7V -->Charger Disable
=> Ichg = 150mA
Rsense(ADin)=0.01 ohm
VCLS= 2.59V
=> Ichg = 2.5A
REF : 4.2235V
Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF]
0.8 > Vmode (trie to GND) ----> Learning mode
VICTL= 3.0V
Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] }
AC_IN Threshold 2.048Vmax A/D_DOCK_IN
>17.46V active
2.0 > Vmode > 1.6V (floating) ----> 3 Cells
=> Ichg = 1.25A
Rsense(CHG)=0.025 ohm
=> Constant Power = 19 * 4.737A = 90W
44.6*3uA*10K = 1.338V
VICTL= 1.5V
12/19
3/3
maxim
recommend
1uF 3/6
change
05/05
5/17
5/17
6/14 EE change
Custom
68 55Friday, July 21, 2006
ASUSTECH
POWER_CHARGE
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
CHG_GND
PKPRES#
AD_IINP
PKPRES#
AD_IINP
CHG_CCS
BAT
CHG_GND
MAX8725_LDO
+2.5VREF
+5VCHG
AC_BAT_SYS
MAX8725_LDO
A/D_DOCK_IN
+5VLCM
MAX8725_LDO
BAT
A/D_DOCK_IN
MAX8725_REF
PT6814
TPC28TPQ6801B
UM6K1N
5
G
S
D3
2
1
PQ6807
2N7002
@
+
PR6828
470KOhm
@
GS
D
3
2
1
PQ6809
2N7002
PT6810
TPC28T
PT6812
TPC28T
PC6816
0.1UF/25V
PR6803
33Ohm
@
@
PT6803
TPC28T
PD6802
1SS355
@
PU6801
MAX8725ETI
21
20
19
18
17
16
15
1
2
3
4
5
6
7
DLOV
DLO
PGND
CSIP
CSIN
BATT
GND1
DCIN
LDO
ACIN
REF
GND/PKPRES#
ACOK
MODE
PQ6803A
UM6K1N
2
PT6804
TPC28T
PD6803
1SS355
12
PR6806
25mOHM
1 2
PQ6802
SI4835BDY
PC6806
1UF/25V
1 2
PQ6804
SI4800BDY
PC6814
0.1UF/25V
PT6805
TPC28T
PR6801
107KOhm
PL6801
10UH
21
PT6815
TPC28T
PR6826
15KOhm
1 2
PT6801
TPC28T
PR6816
10KOhm
PD6801
1SS355
12
PT6809
TPC28TPT6807
TPC28T
PT6808
TPC28T
PR6825
470KOhm
@
PC6807
0.22UF/10V
PT6818
TPC28T
1
PT6817
TPC28T
PT6816
TPC28T
GS
D
3
2
1
PQ6808
2N7002
PQ6801A
UM6K1N
2
PR6819
100KOhm
1%
12
PR6813
2.7KOhm
PT6811
TPC28T
+
GS
D
3
2
1
PQ6806
2N7002
PQ6803B
UM6K1N
5
PC6811
0.047UF/16V
PR6823
470KOhm
@
PR6807
13.3KOhm
PR6805
100KOhm
1 2
PR6818
4.7KOhm
1 2
PT6802
TPC28T
+
-
V+
V-
PU6802
LMV321IDBVR
1
3
4
MAX8725_PDS71
A/D_SD#70
CHG_EN#69
TS#39,69,71
PWRLMT#5,22,71
PRECHG69
CHG_SRC71
MAX8725_PDL71
AC_APR_UC69
CSSP71
BAT_LEARN28
CSSN71
AC_IN# 28
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PIC16F54
Adaptor error circuit for +19V adaptor
Vth = 17.5V (MAX. 17.8V & MIN. 17.2V)
For PIC
refresh
6/14 EE change
Custom
69 55Friday, July 21, 2006
<OrgName>
POWER_PIC
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
ADP_ERR#
AC_APR_UC
ICSPCLK
+5VCHG
BAT_LLOW
ICSPDAT
VPP
VPP
+5VLCM
ICSPDAT
ICSPCLK
BAT_LLOW
ADP_ERR#
+5VLCMA/D_DOCK_IN +5VLCM
+5VLCM
+2.5VREF
+5VCHG
PC6903
0.1UF/10V
MLCC/+/-10%
PT6915
TPC28T
PR6904
10KOhm_0402
1 2
GS
D
3
2
1
PQ6902
2N7002
PT6901
TPC28T
PT6907
TPC28T
PT6914
TPC28T
PT6917
TPC28T
PR6914
470KOhm
PT6904
TPC28T
GS
D
3
2
1
PQ6903
2N7002
PT6912
TPC28T
PT6913
TPC28T
PT6910
TPC28T
PD6901 RB751V_40
1 2
PT6918
TPC28T
PR6918
0Ohm
1 2
@
PU6903
PIC16F54
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RA2
RA3
T0CKI
MCLR#/VPP
VSS1
VSS2
RB0
RB1
RB2
RB3
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD2
VDD1
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
@
PT6909
TPC28T
PT6906
TPC28T
PT6908
TPC28T
PC6904
0.1UF/25V
PCO691
PIC_REFRESH_5P
PT6916
TPC28T
PC6905
0.1UF/25V
PC6902
1UF/25V
MLCC/+80%-20%
@
PR6901
20KOhm
1%
PD6905
1SS355
12
PT6905
TPC28T
GND
PX6901
4MHZ
1 3
A
B
GND
VCC
Y
PU6901
NL17SZ08XV5T2
1
2
3 4
5
PU6902
PST9142NR
1
2
34
5NC
SUB
GNDVOUT
VCC
PT6911
TPC28T
PD6906
RB751V_40
12
PT6919
TPC28T
@
PR6911
100KOhm
1 2
GS
D
3
2
1
PQ6901
2N7002
PT6920
TPC28T
PT6902
TPC28T
PR6910
120KOhm
1%
+
-
V+
V-
PU6904
LMV321IDBVR
1
3
4
PR6905
1MOhm_0402
1 2
PT6903
TPC28T
AC_APR_UC 68
CHG_EN#68
PRECHG 68
CHG_LED_UP41
TS# 39,68,71
BATSEL_3S#
BAT_LLOW#_OC 28
BATSEL_2P#SMD_BAT28,39
SMC_BAT28,39
CHG_FULL_OC22 CHG_FULL_OC22
BATT_TALARM22
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Place under CPU
THERMAL PROTECTION
11/09
OVP=13.405V
324k 1%->316k
0.1%
3/13
change
6/14 EE change
Custom
70 55Friday, July 21, 2006
ASUSTECH
POWER_PROTECT
2.1
A8T
Eric_Ko
<Core Design>
Size Project Name Rev
Date: Sheet of
Title :
Engineer:
PWROK
+5VAO
+3VS
A/D_DOCK_IN
+2.5VREF
+5VLCM
BAT_S
+5VLCM
+3VSUS
+3VSUS
+3VSUS
PR7016
470KOhm
PJP703
SHORTPIN
@
12
PR7005
10KOhm
PT7015
TPC28T
PR7007
10KOhm
PRT701
100KOhm
12
PR7001
100KOhm
PQ7001A
UM6K1N
2
PR7010
75KOhm
PR7006
316KOhm
PJP701
SHORTPIN
@
12
PT7024
TPC28T
PT7023
TPC28T
PT7005
TPC28T
PR7012
100KOhm
PR7013
1MOhm
PT7003
TPC28T
PC7002
0.1UF/25V
B
C
E
1
2
3
PQ7002
PMBS3906
PT7014
TPC28T
PR7009
5.6KOhm
@
PQ7001B
UM6K1N
5
PC7003
0.1UF/16V
12
PU7002
PST9013NR
1
2
3 4
5
NC
SUB
GND VOUT
VCC
@
@
@
PT7022
TPC28T
PR7015
100KOhm
PT7002
TPC28T
PR7011
80.6KOhm
B
C
E
1
2
3
PQ7003
PMBS3904
PR7014
0Ohm
PT7006
TPC28T
@
PU7001
LM393DR
1
2
3
4 5
6
7
8
VOUT1
VIN1-
VIN1+
GND VIN2+
VIN2-
VOUT2
VCC
PT7016
TPC28T
PT7020
TPC28T
PT7007
TPC28T
PR7003
100KOhm
PC7011
1UF/10V
@
PD70011SS355
12
PD7002
1SS355
PR7002
47KOHM
PT7004
TPC28T
A
B
GND
VCC
Y
PU7003
NC7SZ08P5X
1
2
3 4
5
PJP702
SHORTPIN
@
12
FORCE_OFF# 42,46
PWRGD5,22
1.2VO_1.0VO_PWRGD47
DDR_PWRGD65
VSUS_GD#46
SUSB#22,31,32,42,67
FORCE_OFF# 42,46
CPUPWR_GD19,61
A/D_SD#68
VGA_PWRGD16,20
