La 7551pr01 0217a (Restored) ASUS K43T(la 7551p)

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1

Compal Confidential
2

2

QBL50 Schematics Document
AMD Sabine
APU Llano / Hudson M2_M3 / Vancouver Whistler
UMA only / PX Muxless with BACO
3

3

2010-02-16
LA-7552P REV: 0.03

4

4

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

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Title

Cover Page
Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
E

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of

49

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Compal Confidential
Model Name : QBL60

Sabine

VRAM 1G/2G
128M16 x 4/8

1

page 23, 24

1

DDR3
Thermal Sensor

ATI Vancuver Whistler

GFX x 8

Gen2

ADM1032

page 19

uFCBGA-962
Page 18~22

GFX x 4
APU HDMI
(UMA / Muxless)
DP x1 (DP0 TXP/N0)

AMD FS1 APU
Llano

Memory BUS(DDR3)
Dual Channel

204pin DDRIII-SO-DIMM X2
Page 11,12

BANK 0, 1, 2, 3

1.5V DDRIII 800~1333MHz

uPGA-722 Package

HDMI Conn.
page 28

2

LVDS Conn.
Reserve eDP

Page 6~10

Travis LVDS
Translator

LVDS

P_GPP x 2
GEN1

page 26

DP x 4
(DP1 TXP/N 0~4)

2

UMI
USB2

page 27

page 27

GPP1

GPP0

FCH
Hudson-M2/M3

page 34

page 30

Port 0

Port 1

Port 5

LAN(GbE)
BCM57785

page 32

CMOS
Camera

Card Reader
RTS5137

Mini Card
(with BT)

page 27

page 32

Port2

page 31

Port 3

Port 4

USB
3.3V 48MHz

HD Audio 3.3V 24.576MHz/48Mhz

uFCBGA-656
MINI Card 1
WLAN

USB2
(LS-7322P)

page 34

FCH CRT (VGA DAC)

CRT Conn.

USB2

Page 13~17

S-ATA Gen2

page 29

port 0

LPC BUS

3

RJ45

port 1
3

SATA HDD1
Conn.

page 29

ODD
Conn.
page

page 33

33

HDA Codec
ALC269 page

30

ENE KB930
page 36

Touch Pad
LED

Int.KBD

page 38

page 38

page 37

RTC CKT.
4

External board

page 25

DC/DC
Interface CKT.page

4

LS-7326P
Power/B

page 35

SYS BIOS (2M)

39

Power Circuit

page 40~48
A

BIOS ROM
page 15

LS-7322P
Audio BD

2010/08/04

Issued Date

page 30

EC BIOS (128K)

page 35

B

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
E

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of

49

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1

DISPLAY DISTRIBUTION

CLOCK DISTRIBUTION

: LVDS PATH
: APU HDMI PATH
LVDS CONN

A_SODIMM

B_SODIMM

D

D

TXOUT[0:2]+/TXCLK+/TZOUT[0:2]+/TZCLK+/I2CC_SCL/DA

AMD

R

ATI VGA
1066~1600MHz

MEM_MA_CLK1_P/N
MEM_MA_CLK7_P/N

1066~1600MHz

MEM_MB_CLK1_P/N
MEM_MB_CLK7_P/N

Whistler

CLK_PEG_VGAP/N
100MHz

APU_DISP_CLKP/N
C

AMD

100MHz

CPU FS1 SOCKET

APU_TXOUT[0:2]+/APU_TXOUT_CLK+/APU_TZOUT[0:2]+/APU_TZOUT_CLK+/APU_LVDS_CLK/DATA

APU_CLKP/N
100MHz

AMD

C

LVDS_OUT

RTD2132

FCH
Hudson-M2/M3
Internal CLK GEN

DP0_AUX

DP_IN

GPP_CLK
100MHz

32.768KHz 25MHz

LVDS Transtator

C

DP0_TXP/N[0:1]
DP0_AUXP/N
B

GPP0

GPP1

WLAN
Mini PCI Socket

B

DP0

APU

GbE LAN

DP1

PCIE_GFX[0:7]

C

PCIE_GFX[12:15]

C

VGA

PCIE_GFX[0:7]

25MHz

FCH
LS
R
A

A

CRT CONN
Compal Secret Data

Security Classification
2010/08/04

Issued Date

HDMI CONN

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

CLOCK / DISPLAY DISTRIBUTION
Size
Document Number
Custom QBL60 LA-7552P
Date:

Rev
0.03

Tuesday, February 22, 2011

Sheet
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Voltage Rails
Power Plane

Description

S3

S5

STATE

+VALW

+V

+VS

Full ON

HIGH

HIGH

HIGH

ON

ON

ON

ON

S1(Power On Suspend)

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

ON

OFF

OFF

OFF

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit.

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+CPU_CORE_NB

Voltage for On-die VGA of APU

ON

OFF

OFF

+VGA_CORE

0.95-1.2V switched power rail

ON

OFF

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

ON

OFF

+1.0VSG

1.0V switched power rail for VGA

ON

OFF

OFF

+1.1ALW

1.1V switched power rail for FCH

ON

ON

ON*

+1.1VS

1.1V switched power rail for FCH

ON

OFF

OFF

+1.2VS

1.2V switched power rail for APU

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDR

ON

ON

OFF

+1.5VS

1.5V switched power rail

ON

OFF

OFF
OFF

1

2

SIGNAL

S1

+1.8VSG

1.8V switched power rail

ON

OFF

+2.5VS

2.5V for CPU_VDDA

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+LAN_IO

3.3V power rail for LAN

ON

ON

ON

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

SLP_S3# SLP_S4# SLP_S5#

Clock

1

2

BTO Option Table

M3@ U25

BOM Structure

BTO Item

VGA@

Use VGA (Mux)

X76@

VRAM ID Table

M2@

Use Hudson-M2

M3@

Use Hudson-M3

USB30@

USB30 on M/B

USB20@

USB20 on M/B

FCH M3

Part Number = SA000043I90

BOM Config

x = 1 is read cmd, x= 0 is writee cmd.

External PCI Devices
Device

IDSEL#

REQ#/GNT#

Interrupts

3

3

EC SM Bus1 address

EC SM Bus2 address

Device

Address

HEX

Device

Address

HEX

Smart Battery

0001 011X b

16H

ADI ADM1032 (VGA)

1001 101X b

9AH

(APU)
RTD2132S (TL)

4

FCH
SM Bus 0 address

FCH
SM Bus 1 address

Device

Address

HEX

DDR DIMM1

1101 000X b

D0

DDR DIMM2

1101 001X b

D2

Device

4

Address

HEX

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

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Title

Notes List
Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
E

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of

49

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1

AMD APU FS1
BATTERY
12.6V

PU101
CHARGER

BATT+

PU201
ISL6267HRZ-T

+CPU_CORE
+CPU_CORE_NB

AC ADAPTOR
19V 90W

PU501
RT8209MGQW

VIN

0.7~1.475V

VDD CORE 54A

+CPU_CORE_NB

0.7~1.475V

VDDNB 27.5A

+2.5VS

+2.5VS

VDDA 500mA

+1.5V

+1.5V

VDDIO 4.6A

+1.2VS

+1.2VS

VDDR 6.7A

+2.5VS

+1.5V
D

+CPU_CORE

PU603
APL5508-25DC

D

RAM DDRIII SODIMMX2
PU801
RT8209MGQW

B+

+1.2VS

+1.5V

VDD_MEM 4A

+0.75VS

VTT_MEM 0.5A

+0.75VS +0.75VS
PU601
APL5336KAI

PU901
RT8237CZQW

+VGA_CORE

+VDDCI

+1.0VSG
PU602
APL5930KAI

+1.0VSG

+1.5VSG

+1.5VSG

U41
AO4430L
PU701
RT8209MGQW

+1.1VALW

PU301
RT8205LZQW

+3VALW

VGA ATI
Whistler/Seymour/Granville

+VGA_CORE

0.85~1.1V

VDDC 47A

0.9~1.0V

VDDCI 4.6A

+1.0VSG

DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA

+1.5VSG

VDDR1: 3400 mA

C

+INVPWR_B+

PU401
SY8033BDBC

U40
SI4800

+5VALW

+1.8VSG

+1.8VSG

+1.8VSG

PJ14

+3VSG

+3VSG

+3VSG

U33
SI4800

U39
AO4430L

+1.1VS

+1.1VS

+3.3 350mA

FAN Control
APL5607

+1.1VALW

VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA

+5VALW

+USB_VCCA
+USB_VCCB

+3VS
+3VS

+3VS

+1.5VS

USB X3
+5V
Dual+1
2.5A

+3VALW
+3VALW

+3VALW

SATA
HDD*2
ODD*1
+5V 3A

A2VDD: 130 mA
VDDR3: 60 mA

VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

+5VS

+5VS 500mA

Audio Codec
ALC269-GR

EC
ENE KB930

+5V 45mA

+3.3VALW 30mA
+3.3VS 3mA

+3.3VS 25mA

LAN
RTL8111E

Mini Card

+3.3VALW 201mA

+1.5VS 500mA
+3.3VS 1A
+3.3VALW 330mA

RTC
Bettary

A

Issued Date

VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA

VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA

GND

VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S

RTC BAT

VDDBT_RTC_G

2010/08/04

Deciphered Date

2010/08/04

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

A

Title

POWER DELIVERY CHART
Size
Document Number
Custom QBL60 LA-7552P
Date:

4

B

Compal Secret Data

Security Classification

5

C

+1.1VS

+1.1VALW

+3.3V

2.4 A

FCH AMD Hudson M2/M3

B+ 300mA

U54/U55
AP2301MPG

+1.5VSG

PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA

+3VS

LCD panel
15.6"

B

VRAM 1GB/2GB
64M / 128Mx16 * 4 / 8

2

Rev
0.03

Tuesday, February 22, 2011
1

Sheet

5

of

49

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C

D

18 PCIE_GTX_C_FRX_P[0..7]

PCIE_FTX_C_GRX_P[0..7] 18

18 PCIE_GTX_C_FRX_N[0..7]

PCIE_FTX_C_GRX_N[0..7] 18
JCPU1A

E

APU To HDMI
PCIE_FTX_GRX_P[12..15] 28

CONN@

PCIE_FTX_GRX_N[12..15] 28

PCI EXPRESS
AA2

PCIE_FTX_GRX_P0

C917VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P0

AA3

PCIE_FTX_GRX_N0

C918VGA@

1

2 0.1U_0402_16V7K

Y7

PCIE_FTX_C_GRX_N0

Y2

PCIE_FTX_GRX_P1

C919VGA@

1

2 0.1U_0402_16V7K

PCIE_GTX_C_FRX_N1

Y8

PCIE_FTX_C_GRX_P1

P_GFX_TXN1

Y1

PCIE_FTX_GRX_N1

C920VGA@

1

2 0.1U_0402_16V7K

PCIE_GTX_C_FRX_P2

W5

PCIE_FTX_C_GRX_N1

P_GFX_RXP2

P_GFX_TXP2

Y4

PCIE_FTX_GRX_P2

C921VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P2

PCIE_GTX_C_FRX_N2

W6

PCIE_GTX_C_FRX_P3

P_GFX_RXN2

P_GFX_TXN2

W8

Y5

PCIE_FTX_GRX_N2

C922VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_N2

P_GFX_RXP3

P_GFX_TXP3

W2

PCIE_FTX_GRX_P3

C923VGA@

1

2 0.1U_0402_16V7K

PCIE_GTX_C_FRX_N3

W9

PCIE_FTX_C_GRX_P3

P_GFX_RXN3

P_GFX_TXN3

W3

PCIE_FTX_GRX_N3

C924VGA@

1

2 0.1U_0402_16V7K

PCIE_GTX_C_FRX_P4

V7

PCIE_FTX_C_GRX_N3

P_GFX_RXP4

P_GFX_TXP4

V2

PCIE_FTX_GRX_P4

C925VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P4

PCIE_GTX_C_FRX_N4

V8

P_GFX_RXN4

P_GFX_TXN4

PCIE_GTX_C_FRX_P5

U5

V1

PCIE_FTX_GRX_N4

C926VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_N4

P_GFX_RXP5

P_GFX_TXP5

V4

PCIE_FTX_GRX_P5

C927VGA@

1

2 0.1U_0402_16V7K

PCIE_GTX_C_FRX_N5

PCIE_FTX_C_GRX_P5

U6

P_GFX_RXN5

P_GFX_TXN5

V5

PCIE_FTX_GRX_N5

C928VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_N5

PCIE_GTX_C_FRX_P6

U8

P_GFX_RXP6

P_GFX_TXP6

U2

PCIE_FTX_GRX_P6

C929VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P6

PCIE_GTX_C_FRX_N6

U9

U3

PCIE_FTX_GRX_N6

C930VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_N6

PCIE_GTX_C_FRX_P7

T7

T2

PCIE_FTX_GRX_P7

C931VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P7

PCIE_GTX_C_FRX_N7

T8

T1

PCIE_FTX_GRX_N7

C932VGA@

1

2 0.1U_0402_16V7K

PCIE_FTX_C_GRX_N7

R5
R6
R8
R9
P7

P_GFX_RXP7

P_GFX_TXN6
P_GFX_TXP7

P_GFX_RXN7

P_GFX_TXN7

P_GFX_RXP8

P_GFX_TXP8

P_GFX_RXN8

P_GFX_TXN8

P_GFX_RXP9

P_GFX_TXP9

P_GFX_RXN9

P_GFX_TXN9

P_GFX_RXP10

P_GFX_TXP10

CPU TSI interface level shift
R2

N6

P_GFX_RXN11

P_GFX_TXN11

P5

N8

P_GFX_RXP12

P_GFX_TXP12

N2

32 PCIE_DTX_C_FRX_N1

AC9
AB7
AB8
AA5
AA6

13 UMI_MTX_C_FRX_P0

AF8

13 UMI_MTX_C_FRX_N0

AF7

13 UMI_MTX_C_FRX_P1

AE6

13 UMI_MTX_C_FRX_N1

AE5

13 UMI_MTX_C_FRX_P2

AE9

13 UMI_MTX_C_FRX_N2

AE8

13 UMI_MTX_C_FRX_P3

AD8

13 UMI_MTX_C_FRX_N3

AD7
K5

P_GFX_RXP15

P_GFX_TXP15

P_GFX_RXN15

P_GFX_TXN15

P_GPP_RXP0

P_GPP_TXP0

P_GPP_RXN0

P_GPP_TXN0

P_GPP_RXP1
P_GPP_RXN1

P_GPP_TXP1
P_GPP_TXN1

N3

PCIE_FTX_GRX_N12

M2

PCIE_FTX_GRX_P13

M1

PCIE_FTX_GRX_N13

M4

PCIE_FTX_GRX_P14

M5

PCIE_FTX_GRX_N14

L2

PCIE_FTX_GRX_P15

2

8,14

0
8,14

PCIE_FTX_GRX_N15

AD4

PCIE_FTX_DRX_P0

C950 1

2 0.1U_0402_16V7K

PCIE_FTX_C_DRX_P0 29

AD5

PCIE_FTX_DRX_N0

C951 1

2 0.1U_0402_16V7K

PCIE_FTX_C_DRX_N0 29

AC2

PCIE_FTX_DRX_P1

C952 1

2 0.1U_0402_16V7K

PCIE_FTX_C_DRX_P1 32

AC3

PCIE_FTX_DRX_N1

C953 1

2 0.1U_0402_16V7K

PCIE_FTX_C_DRX_N1 32

P_GPP_RXN3

P_GPP_TXN3

AB5

P_UMI_RXP0

P_UMI_TXP0

AF1

UMI_FTX_MRX_P0

C956 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_P0 13

P_UMI_RXN0

P_UMI_TXN0

AF2

UMI_FTX_MRX_N0

C957 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_N0 13

AF5

UMI_FTX_MRX_P1

C958 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_P1 13

AF4

UMI_FTX_MRX_N1

C959 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_N1 13

AE3

UMI_FTX_MRX_P2

C960 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_P2 13

AE2

UMI_FTX_MRX_N2

C961 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_N2 13

AD1

UMI_FTX_MRX_P3

C962 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_P3 13

AD2

UMI_FTX_MRX_N3

C963 1

2 0.1U_0402_16V7K

UMI_FTX_C_MRX_N3 13

K4

P_ZVSS

P_UMI_RXN2

P_UMI_TXN2

P_UMI_RXP3

P_UMI_TXP3

P_UMI_RXN3

P_UMI_TXN3

P_ZVDDP

P_ZVSS

Q10
EC_SMB_CK 1
R538

1

2
0_0402_5%

EC_SMB_CK2 19,26,36

GLAN
3

WLAN

AB1
AB4

Power Sequence of APU

1
R540

+1.5V
+2.5VS

Group A

+1.5VS
+CPU_CORE
Group B

+CPU_CORE_NB

2
196_0402_1%

4

AMD_TOPEDO_FS-1

+1.2VS

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

EC_SMB_DA2 19,26,36

AB2

P_GPP_TXP3

P_UMI_TXP2

APU_SIC 3

APU_SIC

CK

L3

P_GPP_RXP3

P_UMI_TXN1

2
0_0402_5%

BSH111 1N_SOT23-3

P_GPP_TXP2

P_UMI_RXP2

EC_SMB_DA 1
R537

1

To EC

To HDMI

P_GPP_TXN2

P_UMI_RXN1

Q9

1

P_GPP_RXN2

P_UMI_TXP1

2

BSH111 1N_SOT23-3

P_GPP_RXP2

P_UMI_RXP1

APU_SID 3

APU_SID

D

32 PCIE_DTX_C_FRX_P1

AC8

P_GFX_TXN14

2

PCIE_FTX_GRX_P12

S

AC6

P_GFX_RXN14

BSH111, the Vgs is:
min = 0.4V
Max = 1.3V

30K_0402_1%

G

AC5

29 PCIE_DTX_C_FRX_N0

P_GFX_TXP14

2

31.6K_0402_1%

D

29 PCIE_DTX_C_FRX_P0

P_GFX_RXP14

+3VS

1 R536

S

L9

P_GFX_TXN13

1 R535

G

L8

P_GFX_TXP13

P_GFX_RXN13

2 0.1U_0402_16V4Z

P2

P4

P_GFX_RXP13

C935 1

R3

P1

P_GFX_TXN12

For UMA Mux.

T5

P_GFX_TXP11

P_GFX_RXN12

1

T4

P_GFX_TXN10

L6

P_ZVDDP
2
196_0402_1%

P_GFX_RXN6

P_GFX_RXP11

L5

1
R539

P_GFX_RXN1

P_GFX_RXN10

M8

+1.2VS

P_GFX_TXP1

P8

M7

4

P_GFX_RXP1

N5

N9

3

P_GFX_TXN0

GPP

2

P_GFX_TXP0

P_GFX_RXN0

2

PCIE_GTX_C_FRX_P1

P_GFX_RXP0

2

AA9

GRAPHICS

AA8

PCIE_GTX_C_FRX_N0

UMI-LINK

1

PCIE_GTX_C_FRX_P0

B

C

D

Title

AMD FS1 PCIE / UMI / TSI
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

6

of

49

A

B

C

D

E

1

1

JCPU1B
11 DDRA_SMA[15..0]

11
11
11
11

DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#

DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM[7..0]

DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7

2

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

11
11
11
11

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#

11 DDRA_CKE0
11 DDRA_CKE1
11 DDRA_ODT0
11 DDRA_ODT1
11 DDRA_SCS0#
11 DDRA_SCS1#

3

11 DDRA_SRAS#
11 DDRA_SCAS#
11 DDRA_SWE#
11 MEM_MA_RST#
11 MEM_MA_EVENT#

+1.5V

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

U24
U21
L23

MA_BANK0
MA_BANK1
MA_BANK2

E14
J17
E21
F25
AD27
AC23
AD19
AC15
G14
H14
G18
H18
J21
H21
E27
E26
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15
T21
T22
R23
R24

DDRA_CKE0
DDRA_CKE1

H28
H27

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CKE0
MA_CKE1

H17
F17
E19
J19
G16
H16
H19
F19

DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

H20
F21
J23
H23
G20
E20
G22
H22

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

G24
E25
G27
G26
F23
H24
E28
F27

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

Y25
AA27

DDRA_SCS0#
DDRA_SCS1#

V22
AA26

DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#

V21
W24
W23

MEM_MA_RST#
MEM_MA_EVENT#

H25
T24

MA_RESET_L
MA_EVENT_L

W20

M_VREF

M_ZVDDIO W21
2
39.2_0402_1%

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_ODT0
MA_ODT1
MA_CS_L0
MA_CS_L1
MA_RAS_L
MA_CAS_L
MA_WE_L

DDRA_SDQ[63..0]

E13
J13
H15
J15
H13
F13
F15
E15

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

DDRA_ODT0
DDRA_ODT1

15mil

JCPU1C

MEMORY CHANNEL A
U20
R20
R21
P22
P21
N24
N23
N20
N21
M21
U23
M22
L24
AA25
L21
L20

DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#

+MEM_VREF
1
R541

CONN@

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

11

12 DDRB_SMA[15..0]

12
12
12
12

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM[7..0]

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

12
12
12
12

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

MEMORY CHANNEL B

DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15

T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
W26
K25
K24

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#

U27
T28
K28

MB_BANK0
MB_BANK1
MB_BANK2

DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7

D14
A18
A22
C25
AF25
AG22
AH18
AD14

DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#

C15
B15
E18
D18
E22
D22
B26
A26
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14

DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#

12 DDRB_CKE0
12 DDRB_CKE1
12 DDRB_ODT0
12 DDRB_ODT1
12 DDRB_SCS0#
12 DDRB_SCS1#
12 DDRB_SRAS#
12 DDRB_SCAS#
12 DDRB_SWE#
12 MEM_MB_RST#
12 MEM_MB_EVENT#

CONN@

R26
R27
P27
P28

DDRB_CKE0
DDRB_CKE1

J26
J27

DDRB_ODT0
DDRB_ODT1

W27
Y28

DDRB_SCS0#
DDRB_SCS1#

V25
Y27

DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#

V24
V27
V28

MEM_MB_RST#
MEM_MB_EVENT#

J25
T25

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L

A14
B14
D16
E16
B13
C13
B16
A16

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

C17
B18
B20
A20
E17
B17
B19
C19

DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

C21
B22
C23
A24
D20
B21
E23
B23

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

E24
B25
B27
D28
B24
D24
D26
C27

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

DDRB_SDQ[63..0]

12

2

3

M_ZVDDIO
AMD_TOPEDO_FS-1

Place them close to APU within 1"
AMD_TOPEDO_FS-1

EVENT# pull high

0.75V reference voltage

+1.5V
2

+1.5V
4

4

R542
1K_0402_1%
R545 1

2 1K_0402_5% MEM_MB_EVENT#

15mil
1

2 1K_0402_5% MEM_MA_EVENT#

+MEM_VREF

2

R544 1

1

R543
1K_0402_1%
1

2

C964
1000P_0402_50V7K

2

1

C965
0.1U_0402_16V7K

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

AMD FS1 DDRIII I/F
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

7

of

49

B

DP0_TXN0_C

F1

DP0_TXP1

E3

DP0_TXN1

E2

DP0_TXP2

D2

T21
T22

DP0_TXN2

D1

DP0_TXP3

C2

DP0_TXN3

C3

DP1_AUXP

DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3

Place near APU
C977 1

2 0.1U_0402_16V7K

DP1_TXP0

K2

DP1_TXP0

15 ML_VGA_TXN0

C968 1

2 0.1U_0402_16V7K

DP1_TXN0

K1

DP1_TXN0

15 ML_VGA_TXP1

C969 1

2 0.1U_0402_16V7K

DP1_TXP1

J3

C970 1

2 0.1U_0402_16V7K

DP1_TXN1

J2

15 ML_VGA_TXP2

C978 1

2 0.1U_0402_16V7K

DP1_TXP2

H2

15 ML_VGA_TXN2

C979 1

2 0.1U_0402_16V7K

DP1_TXN2

H1

15 ML_VGA_TXP3

C980 1

15 ML_VGA_TXN3

C981 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

DP1_TXP3
DP1_TXN3

G2
G3

DP1_TXN1
DP1_TXP2
DP1_TXN2

APU_CLKP

13

APU_CLKN

13 APU_DISP_CLKP

100MHz_NSS

APU_CLKP

AH7

APU_CLKN

AH6

APU_DISP_CLKP

AH4

APU_DISP_CLKN

13 APU_DISP_CLKN

AH3

DP1_HPD
DP2_HPD

APU_SVC

47

APU_SVD

APU_SVD

TSI

A8

6,14

APU_SIC

6,14

APU_SID

APU_SIC

AH11

APU_SID

AG11

CLKIN_L
DP_DIGON

DISP_CLKIN_H

DP_VARY_BL

R576 1

2 1K_0402_5%
2 1K_0402_5%

AE10

APU_PROCHOT#

AD10

APU_SVC

Serial VID

APU_SVD

SVC
TEST6
TEST9

SIC

TEST10

SID

TEST12

RESET_L

TEST15

PWROK

TEST16

APU_THERMTRIP#

AG12

ALERT_L

AH12

TEST17
PROCHOT_L
THERMTRIP_L

C12

R581 1

2 1K_0402_5%

APU_SID

APU_TDO

A12

R791 1

2 1K_0402_5%

ALERT_L

APU_TCK

A11

APU_TMS

D12
B12

DP1_HPD

TDI

DP1_HPD 10

CRT

R558 1

2 300_0402_5%

DP5_HPD

F7

DP5_HPD 10

C6

DP_ENBKL

C5

DP_ENVDD

C7

DP_INT_PWM

DP_ENBKL 10

TEST25_H

TRST_L
TEST25_L

2 1K_0402_5%

APU_TRST#

TEST30_H

DP_INT_PWM 10

DP_AUX_ZVSS

D8

R569 1

2 150_0402_1%

MISC

R612 1

2 1K_0402_5%

ALLOW_STOP R577 1

2 1K_0402_5%

AA10

R573 1

G10

@

APU_RST#

R578 1

2 300_0402_5%

APU_PWRGD

R580 1

2 300_0402_5%

+1.5V

2 0_0402_5%

R574 1

H12
D9

T6

E9

T7

G9

T8

+3VS

Asserted as an input to force the
processor into the HTC-active state

H10

TEST28_H

RSVD_1
RSVD

H9

2 1K_0402_5%

R587
10K_0402_5%

R586
1K_0402_5%

TEST30_L
TEST31

RSVD_3

APU_TEST24

AH10

TEST25_H

AH9

SENSE

FS1R1

AMD_TOPEDO_FS-1

AB12

T12

3

M_TEST

K22

Q12
1

3

1
R611

2
0_0402_5%

H_THERMTRIP# 14

APU_TRST# R5981

TEST35

D10

Y11

FS1R1

AB10

ALLOW_STOP
C639 1

THERMDA

AE12

THERMDC

AD12

T15

2 0_0402_5%

APU_TCK

4

APU_TMS

6

APU_TDI

8

8

APU_TDO

9

10

10

R5991

@

2 0_0402_5%

APU_PWRGD

11

12

12

R6021

@

2 0_0402_5%

APU_RST#

13

14

2

3

4

5

6

7

7

9

R601 1

2 10K_0402_5%

11

R603 1

2 10K_0402_5%

13

R605 1

2 10K_0402_5%

15

14
16

Cut on CPU side, Debug mount

APU_DBRDY
APU_DBREQ#

15

16

ALLOW_STOP 13

17

17

18

18

R606 1

2 0_0402_5% APU_TEST19

2 0.1U_0402_16V4Z
@

19

19

20

20

R608 1

2 0_0402_5% APU_TEST18

T16

Compal Electronics, Inc.

Compal Secret Data
2010/08/04

4

SAMTE_ASP-136446-07-B
CONN@

Llano do not support this thermal die
Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

2

1

5

Issued Date

B

3

R609
10K_0402_5%

JP1
1

VDD_SENSE
VDDR_SENSE

Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately

+1.5V

HDT Debug conn
T11

VDDP_SENSE

DMAACTIVE_L

APU_THERMTRIP#

AA12

2 0_0402_5%

A10

2 1K_0402_5%

K8

T14

VDDIO_SENSE

THERMTRIP shutdown
temperature: 125 degree

EC_THERM# 13,36,47

K7

AA11

VDDNB_SENSE

+1.5V

1K_0402_5%
R590 1

Q11
2
1
3
0_0402_5%
MMBT3904_NL_SOT23-3

1
R591

TEST25_L

TEST32_L
TEST35

2 1K_0402_5%

R588
10K_0402_5%

MMBT3904_NL_SOT23-3

T13

VSS_SENSE

R582 1

T10

G12

AB11

C9

APU_PROCHOT#

T9

TEST32_H

B10

+1.5VS

Chang to unpop (DG ref.)
20101111

2 0_0402_5%

A9

2 10K_0402_5%

2

DP_ENVDD 10

F10

R595 1

C8

R571 1

+1.5V

TEST23

TEST28_L

B9

2 39.2_0402_1%

VDDIO level
Need Level shift

R610

TEST24

RSVD_2

R567 1

FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use

2 1K_0402_5%

DBREQ_L

K21

2 39.2_0402_1%

HDMI

R589 1

APU_TMS
E8

+1.5V
@

+3VALW

APU_TEST22

TCK
TMS

2 300_0402_5%

R564 1

FS1R1

D11

2 1K_0402_5%

A

TEST35

J7

TEST22

TDO

R594 1

APU_VDD_SEN

2 510_0402_1%

M_TEST

VDDIO level
Need Level shift

2 1K_0402_5%

DBRDY

APU_VDDNB_SEN

LVDS

2 1K_0402_5%

B11

47 APU_VDD_SEN

E7

DP0_HPD 10

R585 1

C11

APU_VDD_RUN_FB_L
APU_VDD_SEN
route as differential

DP0_HPD

APU_TEST21

APU_DBREQ#

47 APU_VDDNB_SEN

D7

E11

TEST21

APU_DBRDY

APU_VDDNB_RUN_FB_L
APU_VDDNB_SEN
route as differential

2 510_0402_1%

R557 1

@

2 1K_0402_5%

APU_TCK

R600 1

R548 1

TEST25_H

R559 1

R584 1

APU_TDI

47 APU_VDD_RUN_FB_L

TEST25_L

APU_HDMI_DATA 28

R583 1

2 1K_0402_5%

47 APU_VDDNB_RUN_FB_L

1 1.8K_0402_5%

APU_HDMI_CLK 28

APU_TEST20

2 1K_0402_5%

Route as differential
with VSS_SENSE

APU_HDMI_DATA

APU_TEST19

R593 1

R597 1

APU_HDMI_CLK

F5

F12

R592 1

AC11

4

TEST

APU_TDI

APU_DBREQ#

F4

G11

TEST19
ALERT_L

JTAG

APU_SIC

2 300_0402_5%

2

C

2 1K_0402_5%

R596 1

1 1.8K_0402_5%

ML_VGA_AUXN R556

+1.5V

G6

E

R579 1

APU_TRST#

VDDIO level
Need Level shift

H11

TEST20

Close to Header

2

1

B

+1.5V

1 1.8K_0402_5%

ML_VGA_AUXP R547

+1.2VS

APU_TEST18

TEST18

+1.5V
3

1 1.8K_0402_5%

2

1

AF10

APU_PWRGD

2

R555

@

DISP_CLKIN_L

SVD

R554

DP0_AUXN

G5

G7

DP_BLON

To FCH

DP0_AUXP

AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic

H5

DP4_HPD

CLKIN_H

If not used, pins are left unconnected (DG ref.)
20101111

To LVDS
Translator

2

R575 1

13 APU_PWRGD

ML_VGA_AUXN_C 15

DP1_TXN3

CTRL

13 APU_RST#
Chang to PU +1.5VS (DG ref.)
20101111

+1.5V

2 0.1U_0402_16V7K

H7

TEST14
APU_RST#

ML_VGA_AUXN C976 1

DP3_HPD

SER.

47

B8

E6

DP1_TXP3

DP_AUX_ZVSS
APU_SVC

ML_VGA_AUXP_C 15

DP3_AUXP
DP3_AUXN

DP0_HPD

CLK

2

13

2 0.1U_0402_16V7K

H4

DP5_HPD

100MHz

ML_VGA_AUXP C975 1

J6

DP5_AUXN

System DP

DP0_AUXN_C 26

E5

DP2_AUXN

DP5_AUXP
DISPLAY PORT 1

15 ML_VGA_TXN1

DP0_AUXP_C 26

2 0.1U_0402_16V7K

DP2_AUXP

DP4_AUXN

DP1_TXP1

2 0.1U_0402_16V7K

C974 1

J5

DP4_AUXP

15 ML_VGA_TXP0

To FCH VGA ML

DP1_AUXN

C972 1

DP0_AUXN

E

T20

1

DP0_AUXN

DP0_TXP1

DP0_AUXP

D5

C

T19

DP0_TXN0

D4

1

T26

DP0_AUXP

2 2

T25

DP0_TXP0

1

F2

DP0_TXN0

2

DP0_TXP0

2 0.1U_0402_16V7K

1

2 0.1U_0402_16V7K

C973 1

E

2 2
B

C971 1

D

Place near APU

2

26

DP0_TXP0_C

DISPLAY PORT MISC.

26

CONN@

DISPLAY PORT 0

To LVDS
Translator

C

JCPU1D

Place near APU

1

A

D

Title

AMD FS1 Display / MISC / HDT
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

8

of

49

A

Power Name
VDD
+CPU_CORE

50A

VDDNB
+CPU_CORE_NB

22.5A

VDDIO
+1.5V

4A

2

1

2

1

2

1

2

1

2

1
+
2

1
+
2

1
+
2

390U_2.5V_10M

2

1

C1011
390U_2.5V_10M

2

1

C1010
390U_2.5V_10M

2

1

C1009
180P_0402_50V8J

C1001

1

2

C5

2

1

1
+
2

330U_D2_2V_Y

1

180P_0402_50V8J

2

C1024

2

1

0.22U_0603_16V4Z

2

1

C1023

2

1

0.22U_0603_16V4Z

2

1

C1022

2

1

0.22U_0603_16V4Z

2

1

C1021

1

0.22U_0603_16V4Z

2

C17

1

4.7U_0603_6.3V6K

2

C16

1

4.7U_0603_6.3V6K

2

C15

1

4.7U_0603_6.3V6K

C14

2

22U_0805_6.3V6M

C1013

1

+1.5V

1

2

180P_0402_50V8J

2

C1030

1

180P_0402_50V8J

C1029

2

0.22U_0603_16V4Z

1

Decoupling between CPU and DIMMs
across VDDIO and VSS split

VDDP decoupling
+1.2VS
+1.2VS

120mil

2

2

C1037

2

1

1

2

0.22U_0603_16V4Z

2

1

C1036

2

1

0.22U_0603_16V4Z

2

1

180P_0402_50V8J

160mil

1

C1035

1

180P_0402_50V8J

A5
A6
B5
B6

2

C1028

VDDR
VDDR
VDDR
VDDR

1

C1034

VDDR
VDDR
VDDR
VDDR

A3
A4
B3
B4

+1.5V

10U_0603_6.3V6M

VDDP_B_1
VDDP_B_2
VDDP_B_3
VDDP_B_4

R22
R25
R28
T20
T23
T26
U22
U25
U28
V20
V23
V26
W22
W25
W28
Y24
Y26
AA28

C6

VDDP_A_1
VDDP_A_2
VDDP_A_3
VDDP_A_4

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

0.22U_0603_16V4Z

VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO

1
+

C1038
220U_6.3V_M

CONN@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

T11
T19
U4
U7
U10
U18
V9
V11
V19
W4
W7
W10
W12
W14
W16
W18
Y9
Y22
AA4
AA7
AB9
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AB27
AC4
AC7
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AC26
AC28
AD9
AD11
AE4
AE7
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AF3
AF6
AF9
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AH5
AH8
AH13
AH15
AH17
AH19
AH21
AH23
AH25

1

2

3

2
AMD_TOPEDO_FS-1
C1038 change to SF000002Y00
20101228

VDDA
VDDA

VDDR decoupling
C1051

2

1

2

1000P_0402_50V7K

C1050

2

1

1000P_0402_50V7K

C1049

2

1

1000P_0402_50V7K

2

1

1000P_0402_50V7K

2

C1048

2

1

180P_0402_50V8J

2

Keep trace from Caps to APU
within 1.2"

1

C1047

Keep trace from resistor to APU
within 0.6"

1

180P_0402_50V8J

1

C1046

AMD_TOPEDO_FS-1

180P_0402_50V8J

1

2

160mil

C1045

2

C1025

1

180P_0402_50V8J

180P_0402_50V8J

2

C992

1

180P_0402_50V8J

2

C991

1

0.01U_0402_16V7K

2

C990

1

0.01U_0402_16V7K

2

C998

1

0.01U_0402_16V7K

C1020

2

C989

0.22U_0603_16V4Z

1

0.22U_0603_16V4Z

C1008

C1019

C988

0.22U_0603_16V4Z

2

180P_0402_50V8J

C1007

1

0.22U_0603_16V4Z

180P_0402_50V8J

4.7U_0603_6.3V6K

C1018

2

C987

C1006

1

22U_0805_6.3V6M

0.22U_0603_16V4Z

2

C986

C1005

1

22U_0805_6.3V6M

0.22U_0603_16V4Z

2

C985

C1004

1

22U_0805_6.3V6M

22U_0805_6.3V6M

C1003

2

C997

22U_0805_6.3V6M

1

22U_0805_6.3V6M

C984

2

22U_0805_6.3V6M

C1002

1

+CPU_CORE_NB

C1044

2

AE11
AF11

K11
K12
K13
K14
K16
K17
K18
L18

180P_0402_50V8J

1

180P_0402_50V8J

2

C1043

1

22U_0805_6.3V6M

C18

2

0.22U_0603_16V4Z

C1041

3300P_0402_50V7K

C1040

1

40mil
+VDDA_APU

2

10U_0603_6.3V6M

L1
FBMA-L11-201209-221LMA30T_0805
2
1

1

C7

+2.5VS

AG6
AG7
AG8
AG9

2

A7
A13
A15
A17
A19
A21
A23
A25
B7
C4
C10
C14
C16
C18
C20
C22
C24
C26
C28
D13
D15
D17
D19
D21
D23
D25
D27
E4
E10
E12
F9
F11
F14
F16
F18
F20
F22
F24
F26
F28
G4
G8
G13
G15
G17
G19
G21
G23
G25
J4
J8
J18
J20
J22
J24
K19
L4
L7
L10
M9
M11
M19
N4
N7
N10
N18
P9
P11
P19
R4
R7
R10
R18
T9

+1.5V

C8

160mil
+1.2VS

AG2
AG3
AG4
AG5

2

10U_0603_6.3V6M

+1.2VS

3

G28
H26
J28
K20
K23
K26
L22
L25
L28
M20
M23
M26
N22
N25
N28
P20
P23
P26

1

900mil

VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB

1

22U_0805_6.3V6M

120mil

Del C1039
201012061900

JCPU1F

+CPU_CORE_NB

C1027

+1.5V

VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB

2

22U_0805_6.3V6M

160mil

J9
J10
J11
J12
J14
J16
K9
K10

1

+CPU_CORE
T6
T10
T18
U1
U11
U19
V3
V6
V10
V18
W1
W11
W13
W15
W17
W19
Y3
Y6
Y10
Y12
Y14
Y16
Y18
Y20
AA1
AB3
AB6
AC1
AD3
AD6
AE1

C1012

900mil
+CPU_CORE_NB

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C1000

2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

2000mil

C983

CPU_CORE
330uF X 4
22uF X 11

C1
D3
D6
E1
F3
F6
F8
G1
H3
H6
H8
J1
K3
K6
L1
L11
L19
M3
M6
M10
M18
N1
N11
N19
P3
P6
P10
P18
R1
R11
R19
T3

CONN@

22U_0805_6.3V6M

+CPU_CORE

3A / 3.5A

JCPU1E

22U_0805_6.3V6M

2000mil

0.75A

CORE_NB
330uF X 2
22uF X 4

E

+CPU_CORE

C996

VDDA
+2.5VS

D

CPU BOTTOM SIDE DECOUPLING
22U_0805_6.3V6M

1

C

C982

VDDP / VDDR
+1.2VS

B

Consumption

+1.2VS

Demo Board Capacitor (include PWM side)

C13

2

2

1

CPU_CORE
470uF x 6
22uF x 9
0.22uF x 2
180pF x 2
10nF x 3

4.7U_0603_6.3V6K

C12

2

1

4.7U_0603_6.3V6K

C11

2

1

4.7U_0603_6.3V6K

C10

2

1

4.7U_0603_6.3V6K

1

0.22U_0603_16V4Z

2

C1055

1

0.22U_0603_16V4Z

2

C1054

1

0.22U_0603_16V4Z

C1053

2

4

0.22U_0603_16V4Z

C1052

1

VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4

2010/08/04

B

C

VDDP/R_PWM VDDP
470uF x 2
10uF x 3
10uF x 1
0.22uF x 2
180pF x 2

VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4

4

Compal Electronics, Inc.
2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

VDDIO_SUS
(DIMM x2)
100uF x 4
0.1uF

Compal Secret Data

Security Classification
Issued Date

CORE_NB
470uF x 4
22uF x 6
0.22uF x 2
180uF x 3

D

Title

AMD FS1 PWR / GND
Size Document Number
Custom

Rev
0.02

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

9

of

49

5

4

HPD

3

2

Panel ENBKL

+3VS

+3VS

2

2

2

Q13
3
1
MMBT3904_NL_SOT23-3

C

3

E
@
R620
100K_0402_5%

1

+3VS

1

@
1
R619

DP_ENBKL
2

8

S

@
Q14
2N7002_SOT23

2

1

1

+1.5VS

MMBT3904_NL_SOT23-3

1
100K_0402_5%

@
Q15
2
2
2.2K_0402_5% B

D

2
G

DP0_HPD 8

C

2
R618

D

APU_ENBKL

1

1
LVDS_HPD

LVDS_HPD

R616
4.7K_0402_5%

E

26

B

From Translator

@
R614
4.7K_0402_5%

3

@
R615
1K_0402_5%

Translator HPD

2 2

D

@
R617
100K_0402_5%
1

2

1

1

1

+1.5VS

R613
10K_0402_5%

1

R621
10K_0402_5%

1

R623
4.7K_0402_5%
2

APU_ENBKL

Q16
3
1
MMBT3904_NL_SOT23-3

2 0_0402_5%

ENBKL 36

DP1_HPD 8

C

2
R627

R624 1 @

E

FCH_CRT_HPD

15 FCH_CRT_HPD

B

From FCH

2 2

@
R622
1K_0402_5%

CRT HPD

1
100K_0402_5%

Panel ENVDD

C

+3VS

C

+3VS

1
@
R632
4.7K_0402_5%
2

2

2 2

Q17
3
1
MMBT3904_NL_SOT23-3

APU_ENVDD 27

1
R633

DP_ENVDD

C

3

E

2
1

@
R634
100K_0402_5%

Panel PWM

Q18
@
2N7002_SOT23

B

+3VS

1

B

S

2
G

1

8

@
Q19
2
2
2.2K_0402_5% B

1
@

MMBT3904_NL_SOT23-3

1
100K_0402_5%

D

3

DP5_HPD 8

C

2
R659

@
R631
100K_0402_5%

1

1

R630
4.7K_0402_5%

E

APU_HDMI_HPD

B

From HDMI Conn
28 APU_HDMI_HPD

2

R628
10K_0402_5%

@
R629
1K_0402_5%

HDMI HPD

1

2

1

1

+1.5VS

R636
4.7K_0402_5%
2

2

R635
47K_0402_5%

1
R637

3

2

R638
4.7K_0402_5%

1
3

1

C

E

1

8 DP_INT_PWM

Q21
2
2
2.2K_0402_5% B

MMBT3904_NL_SOT23-3

APU_INVT_PWM 26,27
D

S

2
G

Q20
2N7002_SOT23

Q15 / Q19 / Q21 change to SB000006A00
20101228

A

A

Compal Secret Data

Security Classification
Issued Date

2010/08/04

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

AMD FS1 Singal Level Shifter
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
1

10

of

49

A

B

+1.5V

DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27

7
2

7

DDRA_CKE0
DDRA_SBS2#

DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

7
7

DDRA_CLK0
DDRA_CLK0#

7

DDRA_SCS1#

DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#

7 DDRA_SDQS4#
7 DDRA_SDQS4

DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35

3

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
7 DDRA_SDQS6#
7 DDRA_SDQS6

DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R643
10K_0402_5%
1
2

+3VS

1

+3VS

4

C1080

1

C1081

R645

1

205

2.2U_0603_6.3V4Z

2

0.1U_0402_16V4Z
2

G2

2

0.1U_0402_16V4Z
2

DDRA_SDM2

C1067
1
0.1U_0402_16V4Z

DDRA_SDQ22
DDRA_SDQ23

C1069

2

C1070

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2
C1071

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C1072

C1073

C1074

1
0.1U_0402_16V4Z

1

0.1U_0402_16V4Z
2

2

C1075

1
0.1U_0402_16V4Z

C1076
1

DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3

DDRA_SDQS3# 7
DDRA_SDQS3 7

+0.75VS

+1.5V
@

DDRA_SDQ30
DDRA_SDQ31

DDRA_CKE1

0.1U_0402_16V4Z
2

2

1
0.1U_0402_16V4Z

DDRA_CKE1 7

1

C1078
1

C1106

1
C1079

2
4.7U_0603_6.3V6K

2
0.1U_0402_16V4Z
Add C1106
20101101

DDRA_SMA15
DDRA_SMA14

2

DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SMA4
+VREF_CA

DDRA_SMA2
DDRA_SMA0
DDRA_CLK1
DDRA_CLK1#
DDRA_SBS1#
DDRA_SRAS#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1

+VREF_DQ

15mil

DDRA_SCS0# 7
DDRA_ODT0 7
DDRA_ODT1 7

1

C1066

1

2

@

DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39

2

R640
1K_0402_1%

R639
1K_0402_1%

DDRA_SBS1# 7
DDRA_SRAS# 7

+VREF_CA
DDRA_SDQ36
DDRA_SDQ37

+1.5V

+1.5V

DDRA_CLK1 7
DDRA_CLK1# 7

15mil

15mil
+VREF_DQ

1

2

C1061

1

C1062

R641
1K_0402_1%

2

1

2

@

+VREF_CA

1

2

C1064

1

C1065

R642
1K_0402_1%

2

1000P_0402_50V7K
3

DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5#
DDRA_SDQS5

DDRA_SDQS5# 7
DDRA_SDQS5 7

DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7

DDRA_SDQS7# 7
DDRA_SDQS7 7

DDRA_SDQ62
DDRA_SDQ63
MEM_MA_EVENT#

MEM_MA_EVENT# 7
FCH_SDATA0 12,14,32
FCH_SCLK0 12,14,32

+0.75VS
4

206

TYCO_2-2013310-1

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_A STD H:9.2mm

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


A

1

C1077

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

0.1U_0402_16V4Z
2

2

C1068

2

10K_0402_5%

G1

+1.5V

DDRA_SDQ20
DDRA_SDQ21

C1060

DDRA_SDQ32
DDRA_SDQ33

Place near DIMM1

MEM_MA_RST# 7

DDRA_SDQ14
DDRA_SDQ15

C1063

DDRA_SWE#
DDRA_SCAS#

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

DDRA_SDM1
MEM_MA_RST#

4.7U_0603_6.3V6K

DDRA_SBS0#

7
7

DDRA_SMA10
DDRA_SBS0#

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

1

DDRA_SDQ12
DDRA_SDQ13

4.7U_0603_6.3V6K

7

DDRA_CLK0
DDRA_CLK0#

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

DDRA_SMA[0..15] 7

2

DDRA_SDQ24
DDRA_SDQ25

DDRA_SMA[0..15]

DDRA_SDQ6
DDRA_SDQ7

1

DDRA_SDQ18
DDRA_SDQ19

DDRA_SDQS0# 7
DDRA_SDQS0 7

7

DDRA_SDM[0..7] 7

2

7 DDRA_SDQS2#
7 DDRA_SDQS2

DDRA_SDQS2#
DDRA_SDQS2

DDRA_SDQS0#
DDRA_SDQS0

1

DDRA_SDQ16
DDRA_SDQ17

DDRA_SDQ[0..63]

DDRA_SDM[0..7]

1000P_0402_50V7K

DDRA_SDQ10
DDRA_SDQ11

DDRA_SDQ[0..63]

DDRA_SDQ4
DDRA_SDQ5

0.1U_0402_16V4Z

DDRA_SDQS1#
DDRA_SDQS1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

2

7 DDRA_SDQS1#
7 DDRA_SDQS1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1

DDRA_SDQ8
DDRA_SDQ9

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

2

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

1

DDRA_SDQ2
DDRA_SDQ3

JDIMM1

1000P_0402_50V7K

DDRA_SDM0

E

+1.5V

15mil
DDRA_SDQ0
DDRA_SDQ1

D

0.1U_0402_16V4Z

+VREF_DQ

C

B

C

D

Title

DDRIII SO-DIMM 1
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

11

of

49

A

B

+1.5V

DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
1

DDRB_SDQ8
DDRB_SDQ9
7 DDRB_SDQS1#
7 DDRB_SDQS1

DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17

7 DDRB_SDQS2#
7 DDRB_SDQS2

DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27

E

+1.5V

15mil
DDRB_SDQ0
DDRB_SDQ1

D

JDIMM2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDRB_SDQ[0..63]

DDRB_SDQ4
DDRB_SDQ5

DDRB_SDQ[0..63]

DDRB_SDM[0..7]
DDRB_SDQS0#
DDRB_SDQS0

DDRB_SDQS0# 7
DDRB_SDQS0 7

7

DDRB_SDM[0..7] 7

DDRB_SMA[0..15]

DDRB_SMA[0..15] 7

DDRB_SDQ6
DDRB_SDQ7
1

DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
MEM_MB_RST#

MEM_MB_RST# 7

DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ20
DDRB_SDQ21

Place near DIMM2

DDRB_SDM2
DDRB_SDQ22
DDRB_SDQ23

+1.5V

DDRB_SDQ28
DDRB_SDQ29

2

0.1U_0402_16V4Z
2
C1089

DDRB_SDQS3#
DDRB_SDQS3

DDRB_SDQS3# 7
DDRB_SDQS3 7

0.1U_0402_16V4Z
2

2

C1090

1
0.1U_0402_16V4Z

1

C1091

1
0.1U_0402_16V4Z

1

C1093

1
0.1U_0402_16V4Z

7

DDRB_SBS2#

DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

7
7
7
7
7
7

DDRB_CLK0
DDRB_CLK0#
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#

DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#

DDRB_SDQ32
DDRB_SDQ33

DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
7 DDRB_SDQS6#
7 DDRB_SDQS6

DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R646
10K_0402_5%
1
2

1

+3VS

4

R648

G1

G2

2

C1096
1

0.1U_0402_16V4Z
2
C1097

1
0.1U_0402_16V4Z

C1098
1

+1.5V

C1099
1
0.1U_0402_16V4Z

C1100
1

C1107

1

2
0.1U_0402_16V4Z
Add C1107
20101101

C1101

2
4.7U_0603_6.3V6K

1
+
@

2

C9
330U_X_2VM_R6M

2

DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_CLK1
DDRB_CLK1#
DDRB_SBS1#
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_ODT1

DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_SBS1# 7
DDRB_SRAS# 7
DDRB_SCS0# 7
DDRB_ODT0 7
DDRB_ODT1 7

+VREF_DQ

15mil
DDRB_SDQ36
DDRB_SDQ37

1

DDRB_SDM4
DDRB_SDQ38
DDRB_SDQ39

C1088
1000P_0402_50V7K

2

DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5

+VREF_CA

15mil

+VREF_CA

1

2

@

1

2

15mil

+VREF_DQ

C1083

1

C1084

2

1

2

@

1

+VREF_CA

C1086

2

1

C1087

2

3

DDRB_SDQS5# 7
DDRB_SDQS5 7

DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7

DDRB_SDQS7# 7
DDRB_SDQS7 7

DDRB_SDQ62
DDRB_SDQ63
MEM_MB_EVENT#

MEM_MB_EVENT# 7
FCH_SDATA0 11,14,32
FCH_SCLK0 11,14,32

+0.75VS
4

206

TYCO_2-2013289-1

2

10K_0402_5%

205

2

DDRB_SMA11
DDRB_SMA7

C1085

DDRB_SDM5

DDRB_SMA15
DDRB_SMA14

1

0.1U_0402_16V4Z

DDRB_SDQ40
DDRB_SDQ41

1
0.1U_0402_16V4Z

+1.5V
0.1U_0402_16V4Z
2

4.7U_0603_6.3V6K

3

1

0.1U_0402_16V4Z
2
C1095

@

DDRB_CKE1 7

C1082

DDRB_SDQ34
DDRB_SDQ35

DDRB_CKE1

0.1U_0402_16V4Z

DDRB_SDQS4#
DDRB_SDQS4

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

4.7U_0603_6.3V6K

7 DDRB_SDQS4#
7 DDRB_SDQS4

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2

1000P_0402_50V7K

2

DDRB_CKE0

2

C1094

DDRB_SDQ30
DDRB_SDQ31

+0.75VS
7

0.1U_0402_16V4Z
2

2

C1092

1000P_0402_50V7K

+VREF_DQ

C

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.


A

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

DIMM_B STD H:5.2mm
B

C

D

Title

DDRIII SO-DIMM 2
Size Document Number
Custom
Date:

Rev
0.03

QBL60 LA-7552P

Tuesday, February 22, 2011

Sheet
E

12

of

49

A

B

C1195

C

D

E

150P_0402_50V8J
2

U25A

1

HUDSON-2

GLAN

29 CLK_PCIE_LAN
29 CLK_PCIE_LAN#

CLK_PCIE_LAN R604 1
CLK_PCIE_LAN# R625 1

CLK_PCIE_LAN_R
0_0402_5%
2
CLK_PCIE_LAN#_R
0_0402_5%
2

WLAN

32 CLK_PCIE_MINI1
32 CLK_PCIE_MINI1#

CLK_PCIE_MINI1 R644 1
CLK_PCIE_MINI1#R572 1

CLK_PCIE_MINI1_R J27
0_0402_5%
2
CLK_PCIE_MINI1#_R K26
0_0402_5%
2

H27
H28

F33
F31

SS

E33
E31

3

R657 1

25M_X1
2
0_0402_5%

R858
1M_0402_5%

X1

GPP_CLK3P
GPP_CLK3N

GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N

R23
R24

GPP_CLK7P
GPP_CLK7N

N27
R27

GPP_CLK8P
GPP_CLK8N

C33

LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#

14M_25M_48M_OSC

25M_X1

S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
32K_X1

B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19

G25
E28
E26
G26
F26

3

NC

2

32K_X2

1

2

R842

PE_GPIO0 18
PE_GPIO1 25,36

0_0402_5%

B

G
3
5
P
G

+3VS

Q38 change to SB000006A00
20101228
R836
4.7K_0402_5%

3

1
Q38
MMBT3904_NL_SOT23-3

APU_PWRGD_L 47

RTC BATT Conn.

T24

+RTCBATT
PE_GPIO1 1
R109

2
10K_0402_5%

LPC_CLK0_EC_R R8431
2 LPC_CLK0_EC
R6711 22_0402_5%
2
LPC_CLK1_R
R8441 22_0402_5%
2
LPC_AD0
0_0402_5%
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLK0_EC 16,36
CLK_PCI_DB 32
LPC_CLK1 16
LPC_AD0 32,36
LPC_AD1 32,36
LPC_AD2 32,36
LPC_AD3 32,36
LPC_FRAME# 32,36
CONN@

R853 1

APU_PWRGD

@

ALLOW_STOP 8
EC_THERM# 8,36,47
APU_PWRGD 8

2 0_0402_5%

H7
F1
F3
E6

R855 1

2 22_0402_5%

APU_PG/APU_RST#/LDT_STP# : OD pin
DMA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.

APU_RST# 8

G2

32K_X1

G4

32K_X2

+RTCBATT

RTC_CLK 16,36
R857
1K_0402_5%

RTCVCC_R

2

1 C1203

D23

2

2
1
R859

2
510_0402_5%

W=20mils

1

CLRP1
SHORT PADS

for Clear CMOS

C1204

1

2
@

3

+CHGRTC

DAN202UT106_SC70-3
4

Compal Electronics, Inc.

Compal Secret Data
2010/08/04

C

3

SERIRQ 36

C1202 1

Issued Date

JRTC1
SUYIN_060003HA002G202ZL

@

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Close to HUDSON-M2

P

5
APU_PWRGD
T23

Security Classification

32.768KHZ_12.5PF_Q13MC14610002

2

22P_0402_50V8J

A

NC

OSC

2
0_0402_5%

R834
10K_0402_5%

0.1U_0402_16V4Z

1
2

C1206 1

OSC

1

1
R832

2

Y4
4

VGA_PWRGD_R

2
0_0402_5%

1
2
R831 @ 100K_0402_5%

16
16
16
16
16

+1.5VS

32K_X1

R861
20M_0402_5%

1
R830 @

Level shift to ISL6267

4

22P_0402_50V8J

4

+RTCVCC
32K_X2

2

A

3

VGA_PWRGD_R

HUDSON-M2_FCBGA656
M2@
C1205 1

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

25M_X2

1
2
C1201
27P_0402_50V8J

Y

1

NC7SZ08P5X_NL_SC70-5

AF18
AE18
AC16
AD18

2

25MHZ_20PF_7A25000012

25M_X2

GPP_CLK2P
GPP_CLK2N

GPP_CLK4P
GPP_CLK4N

C31

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

GPP_CLK1P
GPP_CLK1N

M27
M26

22_0402_5% CLK_SD_48M_R J26

1
R856

1

1
2
C1200
27P_0402_50V8J

EMI2

GPP_CLK0P
GPP_CLK0N

M23
M24

N25
N26

31 CLK_SD_48M

SLT_GFX_CLKP
SLT_GFX_CLKN

VGA_PWRGD

25,48 VGA_PWRGD

0.1U_0402_16V4Z

1

J30
K29

18 CLK_PEG_VGA
18 CLK_PEG_VGA#

@U27
@
U27
2 B

2

CLK_PEG_VGA
CLK_PEG_VGA#

VGA

APU_CLKP
APU_CLKN

1
2
R835
0_0402_5%
+3VALW
@ C1199
1
2

1

T24
T23

R826
8.2K_0402_5%

1

PLT_RST# 18,29,32

U26
NC7SZ08P5X_NL_SC70-5

+

APU_CLKP
APU_CLKN

@
1

@
4

-

8 APU_CLKP
8 APU_CLKN

DISP2_CLKP
DISP2_CLKN

C1188
150P_0402_50V8J

Y

C

APU

H33
H31

DISP_CLKP
DISP_CLKN

A

E

APU DISP

PCIE_RCLKP
PCIE_RCLKN

B

1

B

8 APU_DISP_CLKP
8 APU_DISP_CLKN

R26
T26

2

2

G30
G28

APU_DISP_CLKP
APU_DISP_CLKN

CLK_CALRN

2
2 33_0402_5%

2

F27

For "EXT" CLK mode, input to PCIE,

SS
NSS

2 2K_0402_1% CLK_CALRN

R833 1

+1.1VS_CKVDD

R825 1

1

2

APU_PCIE_RST#_C

1

GPP Port0 For USB30 on SUS/B
GPP Port1 For USB30 on M/B 20101103

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

C1193
1
2
0.1U_0402_16V4Z

1

AA27
AA26
W27
V27
V26
W26
W24
W23

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

2

V33
V31
W30
W32
AB26
AB27
AA24
AA23

PCIE_CALRP
PCIE_CALRN

+3VALW

For PCIE device reset on FS1
(GLAN,WLAN)

1U_0402_6.3V4Z

AF29
AF31

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

PCI_CLK3 16
PCI_CLK4 16

AB5

2 2

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCI_CLK1 16

0.1U_0402_16V4Z

AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29

PCIRST#

AF3
AF1
AF5
AG2
AF6

2

UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

1

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

2 590_0402_1% PCIE_CALRP
2 2K_0402_1% PCIE_CALRN

R827 1
R828 1

+PCIE_VDDR_FCH

AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32

PCI CLKS

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PCI INTERFACE

UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3

2
2
2
2
2
2
2
2

LPC

6
6
6
6
6
6
6
6

C1189 1
C1190 1
C1191 1
C1192 1
C1196 1
C1197 1
C1198 1
C1194 1

APU

UMI_MTX_C_FRX_P0
UMI_MTX_C_FRX_N0
UMI_MTX_C_FRX_P1
UMI_MTX_C_FRX_N1
UMI_MTX_C_FRX_P2
UMI_MTX_C_FRX_N2
UMI_MTX_C_FRX_P3
UMI_MTX_C_FRX_N3

UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3

S5 PLUS

1

6
6
6
6
6
6
6
6

PCIE_RST#
A_RST#

PCI EXPRESS INTERFACES

PCI Host Bus Reset (To EC)

APU_PCIE_RST#_CAE2
A_RST#_R
AD5

2 33_0402_5%

1

CLOCK GENERATOR

R829

36 A_RST#

D

Title

Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

13

of

49

A

B

C

D

E

PCIE_RST2 : Reset PCIE device on Hudson2
U25D

EC_KBRST#
EC_SCI#
EC_SMI#

AG19
R9
C26
T5
U4
K1
V7
R10
AF19

+3VALW
FCH_PCIE_WAKE#

8 H_THERMTRIP#

@
1
2 SYS_RESET#
R18 10K_0402_5%

1
2
R862 10K_0402_5%

+3VS

U2

36 EC_RSMRST#

R81

29 LAN_CLKREQ#

2 0_0402_5% LAN_CLKREQ#_1

1

Modify 2010212-AMD request
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1

11,12,32 FCH_SCLK0
11,12,32 FCH_SDATA0

SM bus 0-->S0 PWR domain
SM bus 1-->S5 PWR domain
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
2

2
10K_0402_5%

MINI1_CLKREQ#

32 MINI1_CLKREQ#
16

1
R873

VGA_PD

VGA_PD

T29

T28
34
34

USB_OC1#
USB_OC0#

USB_OC1#
USB_OC0#

AG24
AE24
AE26
AF22
AH17
AG18
AF24
AD26
AD25
T7
R7
AG25
AG22
J2
AG26
V8
W8
Y6
V10
AA8
AF25
M7
R8
T1
P6
F5
P5
J7
T8

GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD

USB 1.1

TEST0
TEST1/TMS
TEST2

G8

USB_RCOMP

B9

USB_FSD1P/GPIO186
USB_FSD1N

H1
H3

USB_FSD0P/GPIO185
USB_FSD0N

H6
H5

USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

R868 1
R869 1

2 33_0402_5%
2 33_0402_5%

HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SDIN1
T31
T35
HDA_SYNC
HDA_RST#

AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#

HD AUDIO

2 33_0402_5%
2 33_0402_5%

F8
E8

USB20_P4
USB20_N4

C6
A6

USB20_P3
USB20_N3

C5
A5

USB20_P2
USB20_N2

C1
C3

USB20_P1
USB20_N1

E1
E3

USB20_P0
USB20_N0

USBSS_CALRP
USBSS_CALRN

C16
A16

USBSS_CALRP
USBSS_CALRN

USB_SS_TX3P
USB_SS_TX3N

A14
C14

USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N

T27
USB_OC1#

1
2
2

1

1

1

2

2
1

1
2

@
R44
8.2K_0402_5%

MINI1_CLKREQ#

@
R46
8.2K_0402_5%

FCH_SDATA0

R48
8.2K_0402_5%

1
R940

FCH_SCLK0

@
R43
8.2K_0402_5%

FCH_PCIE_WAKE#

@

@
R45
8.2K_0402_5%

EC_LID_OUT#

@

@

4

FCH_GPIO189
FCH_GPIO190
FCH_GPIO191

FCH_SDATA1

Modify 2010212-AMD request

2
2.2K_0402_5%
2
2.2K_0402_5%
2
8.2K_0402_5%

FCH_GPIO189
FCH_GPIO190
FCH_GPIO191

Project SKU ID
GPIO189 (use VGA)

L(NO)
R44
L(NO)
R46
L(15")
R48

GPIO190 (use PX)
GPIO191

Modify 2010212-AMD request

Add Project ID Table
201011301600

LAN_CLKREQ#_1

2
8.2K_0402_5%

PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166

+3VALW
FCH_SCLK1

+3VS
1
R880
1
R881
1
R882

K19
J19
J21

H_THERMTRIP#

R47
8.2K_0402_5%

@

USB_OC0#

2

3

2
100K_0402_5%
2
100K_0402_5%
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

H(YES)
R43
H(YES)
R45
H(17")
R47

D21
C20
D23
C22

F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EMBEDDED CTRL

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

USB20_P4 31
USB20_N4 31
USB20_P3 32
USB20_N3 32
USB20_P2 27
USB20_N2 27
USB20_P1 30
USB20_N1 30
USB20_P0 34
USB20_N0 34
R864 1 M3@
R865 1
M3@

2 1K_0402_1%
2 1K_0402_1%

Hudson-M2/M3
EHCI CTL
DEV 18, Fn 2
2

+FCH_VDD_11_SSUSB_S

Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

D15
B15
E14
F14
F15
G15
H13
G13
J16
H16

USB30_MTX_DRX_P0
USB30_MTX_DRX_N0

USB_SS_RX0P
USB_SS_RX0N

J15
K15

USB30_MRX_DTX_P0
USB30_MRX_DTX_N0

H19
G19
G22
G21
E22
H22
J22
H21

R870 1
R872 1
APU_SIC
APU_SID

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

CardReder
WLAN(BT)
CMOS
USB3
USB2

C12
A12

USB_SS_TX0P
USB_SS_TX0N

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

USB1

C10
A10

USB_HSD4P
USB_HSD4N

USB_SS_TX2P
USB_SS_TX2N

USB20_P10 34
USB20_N10 34

Hudson-M3
xHCI CTL
DEV 16, Fn 1
xHCI CTL
DEV 16, Fn 0

Hudson-M2/M3
EHCI CTL
DEV 19, Fn 2

A8
C8

USB_SS_RX1P
USB_SS_RX1N
1
R55
1
R54
1
R871
1
R874
1
R876
1
R877
1
R878

USB20_P10
USB20_N10

USB_HSD5P
USB_HSD5N

USB_HSD0P
USB_HSD0N

USB 3.0

30 HDA_SYNC_AUDIO
30 HDA_RST_AUDIO#

+3VALW

R866 1
R867 1

Hudson-M2
EHCI CTL
DEV 22, Fn 2


H9
G9

USB_SS_RX3P
USB_SS_RX3N
30 HDA_BITCLK_AUDIO
30 HDA_SDOUT_AUDIO
30 HDA_SDIN0

1

USB_HSD6P
USB_HSD6N

USB_HSD1P
USB_HSD1N

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

K12
K13

E10
F10

USB_HSD2P
USB_HSD2N

2 11.8K_0402_1%

G12
F12

USB_HSD8P
USB_HSD8N

USB_HSD3P
USB_HSD3N

R863 1

K10
J12

USB_HSD9P
USB_HSD9N

USB_HSD7P
USB_HSD7N

USB_RCOMP

H10
G10

B11
D11

RSMRST#

USB 2.0

EC_GA20

36
36
36

ACPI / WAKE UP EVENTS

36

AE22

29,32,36 FCH_PCIE_WAKE#

THERMTRIP:
Need level shift from +3VALW to +1.5V

T9
T10
V9

USBCLK/14M_25M_48M_OSC

GPIO

TEST0
TEST1
TEST2

1

PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD

USB OC

36
SLP_S3#
36
SLP_S5#
36 PBTN_OUT#
36 FCH_PWRGD

AB6
R2
W7
T3
W2
J4
N7

USB MISC

HUDSON-2
EC_LID_OUT#

36 EC_LID_OUT#

C39 1
C37 1
M3@

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
M3@

USB30_MTX_C_DRX_P0 34
USB30_MTX_C_DRX_N0 34

3

On board
USB Conn

USB30_MRX_DTX_P0 34
USB30_MRX_DTX_N0 34

2 10K_0402_5%
2 10K_0402_5%
APU_SIC 6,8
APU_SID 6,8

EC_PWM2

EC_PWM2 16

K21
K22
F22
F24
E24
B23
C24
F18

4

HUDSON-M2_FCBGA656
M2@

Modify 20101111
1
R884
@
1
R885
@
1
R886
@
1
R888

EC_RSMRST#

2
2.2K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

+3VALW

For FCH internal debug use

HDA_BITCLK

1

@

2

1

@

2

1

@

2

R887
HDA_SDIN0
R889
HDA_SDIN1
R890

A

TEST0
2.2K_0402_5%
TEST1
2.2K_0402_5%
TEST2
2.2K_0402_5%

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Title

Hudson-M2/M3-ACPI/USB/EC
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

14

of

49

A

B

C

D

E

SYS BIOS ROM

U25B

+3VALW
0.1U_0402_16V4Z
2

HUDSON-2

33 SATA_STX_DRX_P1
33 SATA_STX_DRX_N1

AN22
AL22

SATA_TX1P
SATA_TX1N

33 SATA_DTX_C_SRX_N1
33 SATA_DTX_C_SRX_P1

AH20
AJ20

SATA_RX1N
SATA_RX1P

AJ22
AH22

SATA_TX2P
SATA_TX2N

AM23
AK23

SATA_RX2N
SATA_RX2P

AH24
AJ24

SATA_TX3P
SATA_TX3N

AN24
AL24

SATA_RX3N
SATA_RX3P

AL26
AN26
AJ26
AH26
AN29
AL28

SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
NC6
NC7

AL31
AL33

NC8
NC9

AJ33
AJ31

+AVDD_SATA

SATA_RX4N
SATA_RX4P

AL29
AN31

AH33
AH31

2

SATA_TX4P
SATA_TX4N

AK27
AM27

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

SD CARD

SATA_RX0N
SATA_RX0P

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

GBE LAN

AL20
AN20

VGA_RED
VGA_GREEN
NC10
NC11
VGA_BLUE
NC12
NC13

1K_0402_1% 2

1 R899

SATA_CALRP

AF28

SATA_CALRP

1K_0402_1% 2

1 R900

SATA_CALRN

AF27

SATA_CALRN

VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
VGA_DAC_RSET

SATA_LED#

SATA_LED#
R902 1

+3VS

AD22

SATA_ACT#/GPIO67
AUX_VGA_CH_P
AUX_VGA_CH_N

2 10K_0402_5%
AF21

AG21

VGA MAINLINK

32

SATA_X1

SATA_X2

AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229

3

32

BT_ON

BT_ON

WL_OFF#

32 WL_OFF#

1

2

1

2

R13

AK15
AN16
AL16
K6

10K_0402_5%

R14

K5
10K_0402_5%

1

2

R15

K3
10K_0402_5%

1
R16

AH16
AM15
AJ16

2

M6
10K_0402_5%

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54

+3VALW

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

2
2 1K_0402_5%
2 10K_0402_5%
10K_0402_5%

FCH_SPI_CS1#
FCH_SPI_WP#
FCH_SPI_HOLD#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

@ R36
FCH_SPI_CLK

GBE_MDIO

1

@ C23
2
1
2
10_0402_5%
10P_0402_50V8J

VIN0/GPIO175
HW MONITOR

FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

VIN1/GPIO176
VIN2/SDATI_1/GPIO177
VIN3/SDATO_1/GPIO178
VIN4/SLOAD_1/GPIO179

TEMPIN0/GPIO171

GBE_MDIO

GBE_PHY_INTR
GBE_COL
GBE_PHY_INTR

GBE_CRS

TEMPIN1/GPIO172

2 150_0402_1%

R897 1

2 150_0402_1%

R898 1

2 150_0402_1%

FCH_CRT_G 27
2

FCH_CRT_B 27
27
27

FCH_CRT_DDC_SDA 27
FCH_CRT_DDC_SCL 27
R901 1

2 715_0402_1%

ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
2
100_0402_1%

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1
R904
3

10K_0402_5%

R8
P1

2
10K_0402_5%

10K_0402_5%

R7
N4

+FCH_VDDAN_33_DAC_R
FCH_CRT_HPD

10K_0402_5%

R6
L2

8
8
8
8
8
8
8
8

FCH_CRT_HPD 10

R5
M3

+VDDAN_11_ML

ML_VGA_TXP0
ML_VGA_TXN0
ML_VGA_TXP1
ML_VGA_TXN1
ML_VGA_TXP2
ML_VGA_TXN2
ML_VGA_TXP3
ML_VGA_TXN3

FCH_CRT_HPD

N2

10K_0402_5%

R9

VIN7/GBE_LED3/GPIO182

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

FCH_CRT_R 27

FCH_CRT_HSYNC
FCH_CRT_VSYNC

U28 AUXCAL 1
R903
T31
T33
T29
T28
R32
R30
P29
P28

10K_0402_5%

R10

10K_0402_5%

R11

@
1

GL-02/10/2011: Please enabled integrated pull-up/pull-down and left unconnected.

10K_0402_5%
2

R12

TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174

R896 1

V28
V29

M5

1
R892
1
R893
1
R894
1
R895

Add SYS BIOS ROM
20101111

M33
N32

VIN6/GBE_STAT3/GPIO181

2
10K_0402_5%

FCH_SPI_CLK

M28
N30

M1

NC1
NC2
NC3
NC4
NC5

FCH_SPI_MISO
FCH_SPI_MOSI
1
2 0_0402_5%
FCH_SPI_CS1#
FCH_SPI_WP#

M29

P3

1
R891

Change to PD 20101112

L32

VIN5/SCLK_1/GPIO180

1

+3VALW
GBE_RXERR

L30

C29

FCH_SPI_CLK
FCH_SPI_MOSI
FCH_SPI_MISO

Add for EMI 201011291330

FCH_SPI_CLK_R R35

K31

8
6
5
2

MX25L1606EM2I-12G SOP 8P
SA000041N00
GBE_COL
GBE_CRS

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9
V6
V5
V3
T6
V1

C466
1

U28
1
R626 1
R934 1
R935

GBE_RXERR
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161

SPI ROM

1

SATA_TX0P
SATA_TX0N

33 SATA_DTX_C_SRX_N0
33 SATA_DTX_C_SRX_P0

VGA DAC

ODD

33 SATA_STX_DRX_P0
33 SATA_STX_DRX_N0

SERIAL ATA

HDD1

AK19
AM19

10K_0402_5%

AG16
AH10
A28
G27
L4

HUDSON-M2_FCBGA656
M2@

4

4

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Hudson-M2/M3-SATA/GBE/HWM
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

15

of

49

A

B

C

D

E

STRAP PINS
1

PULL
HIGH

PCI_CLK1

PCI_CLK3

PCI_CLK4

LPC_CLK0

LPC_CLK1

EC_PWM2

ALLOW
PCIE GEN2

USE
DEBUG
STRAPS

NON_FUSION
CLOCK MODE

EC
ENABLED

CLKGEN
ENABLED

LPC ROM

DEFAULT

PULL
LOW

DEFAULT

FORCE
PCIE GEN1

IGNORE
DEBUG
STRAP

FUSION
CLOCK
MODE

EC
DISABLED

DEFAULT

DEFAULT

DEFAULT

RTC_CLK
S5 PLUS
MODE
DISABLED

1

If support ML DAC power down when no VGA plug

DEFAULT

SPI ROM

CLKGEN
DISABLE

L47
1
2
FBMA-L11-201209-221LMA30T_0805

S5 PLUS
MODE
ENABLED

30mil

220 ohm
+3VS

+FCH_VDDAN_33_DAC

+FCH_VDDAN_33_DAC_R

DEFAULT

220 ohm

1
2

1
2

1
2

1
2

1
2

1
2

1

R911 10K_0402_5%

@

+3VALW

R910 10K_0402_5%

2

+3VALW

R909 10K_0402_5%

@

+3VALW

R908 10K_0402_5%

@

+3VALW

R907 10K_0402_5%

10K_0402_5%

@

+3VS
R906 10K_0402_5%

R905

13 PCI_CLK1
2

+3VS

2

1

+3VS

VGA_PD#

2

AO3413 Vgs(max)=1V

1
R912

C1210

C1209

1
2
FBMA-L11-201209-221LMA30T_0805

1

2

0.1U_0402_16V4Z

1

2.2U_0603_6.3V4Z

@ L48
@ Q39 3
@Q39
AP2301GN-HF_SOT23-3

2
0_0402_5%

+1.1VS

+FCH_VDDAN_11_MLDAC

@ Q40 3
AP2301GN-HF_SOT23-3

@
1
R913

1

2
0_0402_5%

30mil

13 PCI_CLK3

2

2

13 PCI_CLK4
13,36 LPC_CLK0_EC

VGA_PD#
+3VS

13 LPC_CLK1

PCI_AD23

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

BYPASS
PCI PLL

ENABLE
ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

1
2

@

R930 2.2K_0402_5%

@

R929 2.2K_0402_5%

@

R928 2.2K_0402_5%

@

R927 2.2K_0402_5%

@

R926 2.2K_0402_5%

4

1

PCI_AD24

13

DISABLE PCI
MEM BOOT

2

PCI_AD25

13

USE DEFAULT
PCIE STRAPS

1

PCI_AD26

13

USE FC
PLL

2

PCI_AD27

13

DISABLE
ILA
AUTORUN

1

13

PCI_AD23

2

PULL
LOW

PCI_AD24

USE PCI
PLL

1

PULL
HIGH

PCI_AD25

1

6

2

2

1

3

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/04

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

2

4

Issued Date

A

4

2

2
1U_0402_6.3V4Z

1

PCI_AD27

2

PCI_AD26

3

2
1

2
1

1
2

1
2

1
2

1
2

1
2

1
2

1
2
3

1

Q41A
DMN66D0LDW-7_SOT363-6

1

R925
C1212
2.2K_0402_5%

@

C1211
1U_0402_6.3V4Z

5

VGA_PD

Q41B
DMN66D0LDW-7_SOT363-6

14

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

VGA_PD#

2

Check VGA_PD states

DEBUG STRAPS

R914
100K_0402_5%

@

R924
0_0402_5%

@

R923
1K_0402_5%

VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off

R916
100K_0402_5%

@

R922 2.2K_0402_5%

R921 2.2K_0402_5%

@

R920 10K_0402_5%

R919 10K_0402_5%

R918 10K_0402_5%

R917 10K_0402_5%

R915 10K_0402_5%

@

1

14 EC_PWM2
13,36 RTC_CLK

C

D

Title

Hudson-M2/M3-STRAP
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

16

of

49

B

C

D

E

C1218 / C1219 / C1247 Change to SE00000I10
20101228

+VCC_FCH_R
U25C

PCI/GPIO I/O

CORE S0
CLKGEN I/O

1

2

2

1

2

C1247

2

1

C1246

MAIN LINK

+1.1VS
1
R25

2
0_0603_5%

1
R938

2
0_0805_5%

1
R941

2
0_0805_5%

+1.1VS

1337mA+AVDD_SATA
.1U_0402_16V7K

2

1

C1245

SERIAL ATA

2

C1237

1

1

2

22U_0805_6.3V6M

PCI EXPRESS

2

2.2U_0603_6.3V4Z

2

C1236

1

.1U_0402_16V7K

+3VALW

59mA

+VDDIO_33_S

2

1

2

C1282

2

1

1

2

1U_0402_6.3V6K

1

C1252

N18
L19
M18
V12
V13
Y12
Y13
W11

1U_0402_6.3V6K

GBE LAN

HUDSON-2
A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18

1088mA
.1U_0402_16V7K

C1235

3.3V_S5 I/O

C1219

C1230

1

2.2U_0603_6.3V4Z

2

.1U_0402_16V7K

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

22U_0805_6.3V6M

C1217

C1226

1

.1U_0402_16V7K

C1225

.1U_0402_16V7K

VDDIO_GBE_S_1
VDDIO_GBE_S_2

2.2U_0603_6.3V4Z

C1216

.1U_0402_16V7K

C1215

1

10mils

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

U25E

+1.1VS

C1251

1

2
0_0402_5%

R26

change to four 1uf-AMD request
20110212
+3VALW

10mils

G24

5mA

+VDDXL_3.3V

2

1

2

L28
1
2
MBK1608221YZF_2P

220 ohm

USB

+1.1VALW

10mils

187mA

+VDDCR_1.1V

2

C1265

1

1

2

1
R1145

2.2U_0603_6.3V4Z

C1264

VDDCR_11_S_1
VDDCR_11_S_2

N20
M20

1U_0402_6.3V6K

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

C1261

C1260

1

2.2U_0603_6.3V4Z

VDDXL_33_S

.1U_0402_16V7K

2

2

+AVDD_SATA

1U_0402_6.3V6K

1

2

C1244

2

C1263

1

VDDIO_33_GBE_S

10mils

U12
U13

1

1U_0402_6.3V6K

2

2

C1234

C1257

1

.1U_0402_16V7K

C1256

2

10U_0603_6.3V6M

1

VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4

30mils

G7
H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11

1

1U_0402_6.3V6K

AA9
AA10

2

1

60mils

C1250

2
0_0402_5%

10U_0603_6.3V6M

2

VDDPL_11_DAC

2

+PCIE_VDDR_FCH

1U_0402_6.3V6K

AB11
AA11

.1U_0402_16V7K

C1262

C1267

2

220 ohm
.1U_0402_16V7K

C1266

2.2U_0603_6.3V4Z

2

1

AB10

+VDDAN_11_USB_S
2.2U_0603_6.3V4Z

+3VS

1

2

1

140mA

1
2
MBK1608221YZF_2P

220 ohm

2

+1.1VALW
L57

L22
+VDDPL_33_SATA
1
2
MBK1608221YZF_2P

1

C1255

2

2

C1254

C1259

1

1

1U_0402_6.3V6K

C1253

220 ohm/2A
.1U_0402_16V7K

C1258

2

2.2U_0603_6.3V4Z

1

2

Y22
V23
V24
V25

+VDDAN_33_USB
1U_0402_6.3V6K

+3VS

220 ohm

1

1
R945

L54
658mA
1
2
FBMA-L11-201209-221LMA30T_0805

L15
+VDDPL_33_PCIE
1
2
MBK1608221YZF_2P

1

R1242 change to 2.2uf-AMD request
20110212

+3VALW

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

1

+PCIE_VDDR_FCH

C1243

2

V21

2

1U_0402_6.3V6K

C1249

2

1

.1U_0402_16V7K

C1248

1

2.2U_0603_6.3V4Z

L7
2 +FCH_VDDPL_33_USB_S
0_0603_5%

LDO_CAP

20mils

2.2U_0603_6.3V4Z

2

change to 0ohm-AMD request
20110212

3

1

C1242
.1U_0402_16V7K

2
0_0603_5%

+VDDAN_33_USB
1

VDDPL_33_SATA

10mils

C1241
4.7U_0603_6.3V6K

2

VDDPL_33_PCIE

+VDDAN_11_ML

226mA
1
R1148

M31

+VDDPL_11_DAC

2
0_0402_5%

C1240

M3@
2

2

220 ohm/2A

2
2.2U_0603_6.3V4Z

2

1

2
0_0805_5%

340mA

50mils

VDDPL_33_USB_S

@
1
C1232

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

2

1

VDDPL_33_SSUSB_S

C1233

C1239

M3@

1

.1U_0402_16V7K

C1238

1

2.2U_0603_6.3V4Z

220 ohm

L24
7mA
1
2 +VDDPL_11_DAC_L
1
MBK1608221YZF_2P
R24

AG28

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

1

1U_0402_6.3V6K

10mils

LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA
supply for the RGB outputs
For A11: Cap = 1nF
For A12, Cap = DNI
+FCH_VDDAN_11_MLDAC

1
2 +FCH_VDDPL_33_SSUSB_S
MBK1608221YZF_2P

D7

AH29

93mA

VDDAN_33_DAC

.1U_0402_16V7K

10mils

+VDDPL_33_PCIE

VDDPL_33_ML

2

1

+1.1VS_CKVDD
C1224

43mA

+FCH_VDDPL_33_USB_S

L18

VDDPL_33_DAC

2

1

1
R937

+1.1VS_CKVDD

20mils

VDDPL_33_SYS

1

1U_0402_6.3V6K

10mils

H26
J25
K24
L22
M22
N21
N22
P22

2

C1214

17mA

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

1

1U_0402_6.3V6K

10mils

M2@ 10_0402_5% +FCH_VDDPL_33_SSUSB_S

T14
T17
T20
U16
U18
V14
V17
V20
Y17

C1223

20mA

R936 2

50mils

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

1U_0402_6.3V6K

VDDPL_33_SSUSB_S
For Hudson3 USB3.0 only
For Hudson2, connect to GND

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10

C1213

2

M3@L6
M3@
L6

.1U_0402_16V7K

1

+3VALW

C1221

2

.1U_0402_16V7K

220 ohm

10mils

+VDDPL_33_DAC
2
V22
0_0402_5%
10mils
+VDDPL_33_ML
2
U22
0_0402_5%
200mA R23
10mils
+FCH_VDDAN_33_DAC_R
T22
1

20mA R22

1

C1231

C1227

1

2.2U_0603_6.3V4Z

1
2
MBK1608221YZF_2P

10mils

20mA

+FCH_VDDPL_33_MLDAC

@ L4

2

HUDSON-2

AB17
AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16
H24

2 +FCH_VDDPL_33_MLDAC
0_0603_5%

R19

+3VS

2

1

47mA
+VDDPL_3.3V

+FCH_VDDAN_33_DAC_R
1

2

1

.1U_0402_16V7K

2

2

C1220

1

1

.1U_0402_16V7K

.1U_0402_16V7K

2

C1229

C1222

1

2.2U_0603_6.3V4Z

220 ohm

1

1

C1228

C1218

+VDDPL_3.3V

1
2
MBK1608221YZF_2P

+VDDIO_33_PCIGP

2
0_0603_5%

R20

L3

22U_0805_6.3V6M

1

+3VS

+3VS

+1.1VS

1007mA

10mils

1U_0402_6.3V6K

131mA

2
0_0603_5%

N8
K25
H25

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSAN_HWM
VSSXL

VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC

VSSPL_SYS
EFUSE

+1.1VALW
L59

197mA

10mils

VDDPL_11_SYS_S

J24

1

2

3

T21
L28
K33
N28
R6

L29

70mA

+VDDPL_1.1V

2

C1272

1

1

2

HUDSON-M2_FCBGA656
M2@

1
2
MBK1608221YZF_2P

.1U_0402_16V7K

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

C1271

2

T12
T13

2.2U_0603_6.3V4Z

2

1

.1U_0402_16V7K

1

C1270

2

C1269

1

.1U_0402_16V7K

C1268

220 ohm

2.2U_0603_6.3V4Z

1
2
MBK1608221YZF_2P

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

+1.1VALW

10mils

+VDDCR_1.1V_USB

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GROUND

A

220 ohm

Connected to VSS through a dedicated via.

+3VALW
+FCH_VDD_11_SSUSB_S

20mils

+VDDCR_11_SSUSB
C1281

1

M3@
2

1

M3@
2

.1U_0402_16V7K

C1280

1

M3@
2

.1U_0402_16V7K

1
2

1
2

USB SS

+FCH_VDD_11_SSUSB_S

B

C1279

1

M3@
2

1U_0402_6.3V6K

C1278

M3@ 2
2 L61 M3@ 1
1
R1150
0_0603_5%
FBMA-L11-201209-221LMA30T_0805

C1473

2

VDDCR_11_SSUSB_S_1
VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3
VDDCR_11_SSUSB_S_4

12mA

+VDDAN_33_HWM

1

30mils

N16
N17
P17
M17

M8

1

2

.1U_0402_16V7K

VDDAN_33_HWM_S

C1472

.1U_0402_16V7K

C1275

.1U_0402_16V7K

1

M3@
2

10mils

VDDAN_11_SSUSB_S_1
VDDAN_11_SSUSB_S_2
VDDAN_11_SSUSB_S_3
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S_5

1

2
0_0402_5%

1

2
0_0402_5%

R27

AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

+3VS

10mils

VDDIO_AZ_S

AA4

1
C1276
1
C1277

HUDSON-M2_FCBGA656
M2@

R28
2
2.2U_0603_6.3V4Z
2
.1U_0402_16V7K

2010/08/04

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

4

VDDIO_AZ_S should be tied to
+3.3/1.5V_S5 rail if Wake on Ring
is supported

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

26mA

+VDDIO_AZ

POWER

424mA

42 ohm/4A

A

1

M3@
2

10U_0603_6.3V6M

+1.1VALW

1

M3@
2

C1274

M2@
C1281
0_0402_5%

C1273

4

M2@
C1275
0_0402_5%

40mils

1U_0402_6.3V6K

For FCH M2 - BOM option
VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S
Connected to VSS.

P16
M14
N14
P13
P14

+VDDAN_SSUSB

M3@ 2
0_0603_5%

2.2U_0603_6.3V4Z

282mA

1
R1149

D

Title

Hudson-M2/M3-POWER/GND
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Sheet

Tuesday, February 22, 2011
E

17

of

49

A

B

C

D

GFX PCIE LANE REVERSAL
PCIE_FTX_C_GRX_P[0..7]

6 PCIE_FTX_C_GRX_P[0..7]

U8A
PCIE_GTX_C_FRX_N[0..7]

PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_GTX_FRX_P0
PCIE_GTX_FRX_N0

C580 1
C291

2
1
VGA@

Y35
W 36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W 33
W 32

PCIE_GTX_FRX_P1
PCIE_GTX_FRX_N1

C247 1
C473

2
1
VGA@

PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2

W 38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33
U32

PCIE_GTX_FRX_P2
PCIE_GTX_FRX_N2

C572 1
C288

2
1
VGA@

PCIE_RX3P
PCIE_RX3N

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7

P35
N36

PCIE_RX7P
PCIE_RX7N

N38
M37

PCIE_RX8P
PCIE_RX8N

2

U30
U29

PCIE_GTX_FRX_P3
PCIE_GTX_FRX_N3

C579 1
C316

6

0.1U_0402_16V7K
0.1U_0402_16V7K

2

2
VGA@

2
VGA@

2
1
VGA@

2
VGA@

PCIE_TX4P
PCIE_TX4N

T33
T32

PCIE_GTX_FRX_P4
PCIE_GTX_FRX_N4

C287 1
C228

2
1
VGA@

PCIE_TX5P
PCIE_TX5N

T30
T29

PCIE_GTX_FRX_P5
PCIE_GTX_FRX_N5

C224 1
C576

2
1
VGA@

PCIE_TX6P
PCIE_TX6N

P33
P32

PCIE_GTX_FRX_P6
PCIE_GTX_FRX_N6

C295 1
C472

2
1
VGA@

PCIE_TX7P
PCIE_TX7N

P30
P29

PCIE_GTX_FRX_P7
PCIE_GTX_FRX_N7

C242 1
C468

2
1
VGA@

PCIE_TX8P
PCIE_TX8N

N33
N32

PCIE_TX9P
PCIE_TX9N

N30
N29

PCIE_TX10P
PCIE_TX10N

L33
L32

PCIE_TX11P
PCIE_TX11N

L30
L29

PCIE_TX12P
PCIE_TX12N

K33
K32

PCI EXPRESS INTERFACE

PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4

PCIE_TX3P
PCIE_TX3N

PCIE_GTX_C_FRX_N[0..7]

2
VGA@

2
VGA@

2
VGA@

2

LVDS CONTROL

L38
K37

PCIE_RX10P
PCIE_RX10N

K35
J36

PCIE_RX11P
PCIE_RX11N

J38
H37

PCIE_RX12P
PCIE_RX12N

H35
G36

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

J33
J32

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

AK35
AL36

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

AJ38
AK37

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

AP34
AR34

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW 37
AU35

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

TXOUT_L3P
TXOUT_L3N

AN36
AP37

2 10K_0402_5%
2 10K_0402_5%

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7

1

For UMA Mux.

LVTMDP

2

2160809000A11SEYMOU_FCBGA962
VGA@

+3VSG

@
R394
2.2K_0402_5%

VGA@
U21

PE_GPIO0

2

B

1

A

Y

4

3

VGA_RST#

G

13

13,29,32 PLT_RST#

3

3

P

2

PCIE_RX9P
PCIE_RX9N

AK27
AJ27

PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0

VGA@

M35
L36

R386 1 VGA@
R387 1 VGA@

VARY_BL
DIGON

5

V35
U36

6

VGA@

PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1

PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3

PCIE_GTX_C_FRX_P[0..7]

1

1


LCD PWM (pulse width modulated)
output to adjust LCD brightness
Active High ,external PD need

U8G
PCIE_GTX_C_FRX_P[0..7]

PCIE_FTX_C_GRX_N[0..7]

6 PCIE_FTX_C_GRX_N[0..7]

E


Controls panel digital power on/off.
Active High ,external PD need

NC7SZ08P5X_NL_SC70-5

CLOCK

AB35
AA36

13 CLK_PEG_VGA
13 CLK_PEG_VGA#

PCIE_REFCLKP
PCIE_REFCLKN

1 @
R159

2
0_0402_5%

CALIBRATION

2
1
R389 VGA@ 10K_0402_5%
VGA_RST#

AH16
AA30

PW RGOOD

PCIE_CALRP

Y30

VGA_PCIE_CALRP

R388 1

PCIE_CALRN

Y29

VGA_PCIE_CALRN

R390 1

VGA@
VGA@

2

1.27K_0402_1%

2

2K_0402_1%

+1.0VSG

PERSTB
2160809000A11SEYMOU_FCBGA962
VGA@

4

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/07/12

Issued Date

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Vancouver_ PCIE / LVDS
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Sheet

Tuesday, February 22, 2011
E

18

of

49

A

B

C

D

E

U8B

Setting

1

GPIO1

PCI Express Transmitter De-emphasis Enable (Internal PD)
0: Tx de-emphasis diabled
1: Tx de-emphasis enabled

CONFIG[2]

GPIO13

CONFIG[1]

GPIO12

GPIO13,12,11 (config 2,1,0) : (Internal PD)
a) If BIOS_ROM_EN = 1, then Config[2:0] defines
the ROM type.

CONFIG[0]

GPIO11

TX_DEEMPH_EN
1

b) If BIOS_ROM_EN = 0, then Config[2:0] defines
the primary memory aperture size.

AUD[1]

HSYNC

AUD(0)

VSYNC

H2SYNC

(GENLK_CLK)

GPIO8

GPIO21

1
2

1

1
2

2

1

1

Internal use only. THIS PAD HAS AN INTERNAL
PULL-DOWN AND MUST BE 0 V AT RESET. The
pad may be left unconnected

NC on Park,
Robson and Seymour

DNI

1
2

1

1
2

2

Move to
DDCCLK_AUX3P,DDCDATA_AUX3N,

AK26
AJ26

GPIO6 voltage control signal ,No use can NC

SWAPLOCKA
SWAPLOCKB

TX1P_DPA1P
TX1M_DPA1N

AU26
AV25

TX2P_DPA0P
TX2M_DPA0N

AT27
AR26

TXCBP_DPB3P
TXCBM_DPB3N

AR30
AT29

TX3P_DPB2P
TX3M_DPB2N

DPB

TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N

AT33
AU32

TXCCP_DPC3P
TXCCM_DPC3N

AU14
AV13

TX0P_DPC2P
TX0M_DPC2N
DPC

DPD

TX1P_DPC1P
TX1M_DPC1N

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4
VGA_ENBKL

2 VGA@ 1
R413 10K_0402_5%

GPIO7 Controls backlight on/off.
Active High ,need external PD

ROM

if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD

GPU_VID0

THM_ALERT#

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

VGA_GPIO0
VGA_GPIO1
VGA_GPIO2
VGA_GPIO3
VGA_GPIO4

R405
R406
R408
R409

1 VGA@
@
1
@
1
@
1

2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
3K_0402_5%

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13
GPIO_22_ROMCSB

48

Reserved

GPU_VID1

GPU_VID1

GPIO_22_ROMCSB
T30
T32
T18
T33
T34
T17

External BIOS device
ON(1)/OFF(0) inter PD
Internal Debug
no use can floating
ON(1)/OFF(0)
Stereo Sync
no use can NC
For ATI Cross fire
no use can NC

AK24

+1.8VSG

R430 1 VGA@

2 499_0402_1%

R431 1 VGA@

2 249_0402_1%

TX2P_DPC0P
TX2M_DPC0N

AT17
AR16
AU20
AT19

NC_TX3P_DPD2P
NC_TX3M_DPD2N

AT21
AR20

NC_TX4P_DPD1P
NC_TX4M_DPD1N

AU22
AV21

NC_TX5P_DPD0P
NC_TX5M_DPD0N

AT23
AR22

R
RB

AD39
AD37

GPIO_0
GPIO_1
G
GPIO_2
GB
GPIO_3_SMBDATA
GPIO_4_SMBCLK
B
GPIO_5_AC_BATT
BB
DAC1
GPIO_6
GPIO_7_BLON
HSYNC
GPIO_8_ROMSO
VSYNC
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
RSET
GPIO_12
70mA AVDD
GPIO_13
GPIO_14_HPD2
AVSSQ
GPIO_15_PWRCNTL_0
100mA VDD1DI
GPIO_16
GPIO_17_THERMAL_INT
VSS1DI
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
R2/NC
GPIO_21_BB_EN
R2B/NC
GPIO_22_ROMCSB
GPIO_23_CLKREQB
G2/NC
JTAG_TRSTB
G2B/NC
JTAG_TDI
JTAG_TCK
B2/NC
JTAG_TMS
B2B/NC
JTAG_TDO
GENERICA
GENERICB
C/NC
GENERICC
Y/NC
GENERICD
COMP/NC
GENERICE_HPD4
DAC2
NC_GENERICF_HPD5
NC_GENERICG_HPD6
H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

1 VGA@ 1 VGA@

2

2

R443
@
0_0402_5%

@

A2VDDQ/NC

27MCLK
AV33
XTALOUT AU34

XO_IN

AW34

XO_IN2

AW35

1

2

XTALIN
XTALOUT

XO_IN2

THERMAL

AD34
AE34
AC33
AC34

+VDD1DI

TS_A/NC

AJ32
AJ33

TSVDD
TSVSS

20mA

1

2
AC30
AC31
AD30
AD31

VGA@ 1 VGA@ 1 VGA@ 1

AF30
AF31

2

AC32
AD32
AF32
AD29
AC29

T2
T3

AG31
AG32
AG33

10mil

AD33

2

AA29

2

1

2

1

2

L9

2

+3VSG

AUD Strap

Back compatibility(Manhattan)
2 0_0402_5%
2 0_0402_5%

+A2VDD

R70

1 @

2 0_0402_5%

+3VSG

+A2VDDQ

R256 1 @

2 0_0402_5%
1 @

+1.8VSG

2

+VDD1DI

1 @

1 @

2

2

Whistler and Seymour
Except A2VSSQ change to TSVSSQ,
others are NC

3

GPIO8 Serial-ROM output from ROM.
GPIO9 Serial-ROM input to ROM.
GPIO10 Serial-ROM clock to ROM.
GPIO22 erternal BIOS-ROM enable

AN20
AM20

AL29
AM29

GPIO8,GPIO9,GPIO10 no use can NC
GPIO22
Enable need 3K PH ,no use must NC

NC on Park,
Robson and Seymour

AN21
AM21

DDC6CLK
DDC6DATA

AJ30
AJ31

NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N

AK30
AK29

B

if GPIO22 High ,GPIO 11-13->CFG[0:2]
Config ROM type ,GPU has internal PD
if GPIO22 Low ,GPIO 11-13->CFG[0:2]
Config Primary memory-aperture size
CFG[3:0]
128MB 000
256MB 001 *
64MB 010

NC on Park,
Robson and Seymour
4

2160809000A11SEYMOU_FCBGA962
VGA@

VGA@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2 10K_0402_5%
2 10K_0402_5%

AMD ref:120ohm/0.3A
SM010030010
200ma 120ohm@100mhz DCR 0.2

AM19
AL19

AL30
AM30

R417 1 @
R418 1 @

NC on Whistler
and Seymour

1
+1.8VSG
VGA@
BLM18AG121SN1D_0603

R77 1 @
R209 1 @

1
2
R436 VGA@ 715_0402_1%

DDCCLK_AUX3P
DDCDATA_AUX3N

VSYNC
HSYNC

AMD ref:120ohm/0.3A

+VDD2DI
VSS2DI

AF33

NC_DDCCLK_AUX4P
NC_DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

10mil

2
VGA@

VGA@

HSYNC:VSYNC
11: Audio for both DisplayPort and HDMI

L8
BLM18AG121SN1D_0603
1
+1.8VSG
VGA@

10mil
VGA@

AM27
AL27

TS_FDO

499_0402_1%

2
VGA@

AM26
AN26

AUX2P
AUX2N

1

+AVDD

AUX1P
AUX1N

XO_IN

AL31

R414

AB34

DDC1CLK
DDC1DATA

DDC2CLK
DDC2DATA

DPLUS
DMINUS

2

C352
0.1U_0402_16V4Z

2

VGA@
C351
1U_0402_6.3V6K

C350
10U_0603_6.3V6M

2

10mil

+TSVDD

1

AF29
AG29
AK32

4

120ohm/0.3A

PLL/CLOCK
DPLL_VDDC

0_0402_5%

Future ASIC call MLPS
OLD ASIC is Fan PWM
L12
BLM18AG121SN1D_0603
2
1
VGA@
1
VGA@

R2SET/NC

DDC/AUX

AN31

EC_SMB_DA2 6,26,36

AC36 HSYNC
AC38 VSYNC

DPLL_PVDD
DPLL_PVSS 75mA

125mA

GPU_THERM_D+
GPU_THERM_D-

+1.8VSG

A2VDD/NC

VREFG

R444

2

VGA@
C354
18P_0402_50V8J

2

2

27MHZ_16PF_X5H027000FG1H
VGA@
C353
18P_0402_50V8J

2

1

2

20mil

1

AMD ref:470ohm/1A

VGA@ Y3
2
1

C347
1U_0402_6.3V6K

+DPLL_VDDC
1 VGA@ 1 VGA@ 1 VGA@
C346
0.1U_0402_16V4Z

1
1M_0402_5%

VGA@ L11
2
1
BLM18AG121SN1D_0603

C345
10U_0603_6.3V6M

2
R445

27MCLK

2

AM32
AN32

EC_SMB_DA2

DMN66D0LDW-7_SOT363-6

C344
10U_0603_6.3V6M

1

C341
1U_0402_6.3V6K

VGA@
C339
10U_0603_6.3V6M

EC_SMB_CK2 6,26,36

AF37
AE38

C343
0.1U_0402_16V4Z

+DPLL_PVDD

VGA@
3

4

EC_SMB_CK2

DMN66D0LDW-7_SOT363-6

AE36
AD35

10mil

A2VSSQ/TSVSSQ

+1.0VSG
VGA@
XTALOUT

2mA

VDD2DI/NC
VSS2DI/NC

20mil
C340
0.1U_0402_16V4Z

AMD ref:470ohm/1A

6
Q8A

NC on Park,
Robson and Seymour

10mil

HPD1

100mA

+VGA_VREF AH13

+3VSG

Not share via for other GND

20mil

2 0.1U_0402_16V4Z

1

2
4.7K_0402_5%

VGA@

1

Q8B

SCL
SDA

VGA@

VGA@ L10
2
1
BLM18AG121SN1D_0603

1
R391 VGA@

R393
4.7K_0402_5%
VGA@

VGA_SMB_DA2

C342
1U_0402_6.3V6K

C335

SM010030010
200ma 120ohm@100mhz DCR 0.2
+1.8VSG

THM_ALERT#

5

AU16
AV15

NC_TXCDP_DPD3P
NC_TXCDM_DPD3N

100mA
3

GND

AT15
AR14

C334
10U_0603_6.3V6M

2
2
2
2
2

THERM#

VGA_SMB_DA2

6

ADM1032ARMZ-2REEL_MSOP8

VGA_SMB_CK2

C333
0.1U_0402_16V4Z

1 VGA@
1 VGA@
1 VGA@
@
1
@
1

ALERT#

VGA_SMB_CK2

7

1

C332
1U_0402_6.3V6K

R395
R396
R397
R398
R401

D-

8

+3VSG

C331
22U_0805_6.3V6M

48

Critical temperature fault

4

SDATA

R392
4.7K_0402_5%
VGA@

C330
0.1U_0402_16V4Z

+3VSG

GPU_VID0

3

SCLK

D+

+3VSG

C329
1U_0402_6.3V6K

GPIO6,15,16,20
Voltage control signal
GPIO6,15 no use can NC
Thermal monitor interrupt

VGA_GPIO11
VGA_GPIO12
VGA_GPIO13

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

2

VDD

2

AV31
AU30
AR32
AT31

GENERAL PURPOSE I/O

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3
X76@
R435
10K_0402_5%

X76@
R434
10K_0402_5%

X76@
R433
10K_0402_5%

R432
10K_0402_5%

X76@

X76@

AJ21
AK21

NC_DVPCNTL_MVP_0
NC_DVPCNTL_MVP_1
NC_DVPCNTL_0
NC_DVPCNTL_1
NC_DVPCNTL_2
NC_DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
NC_DVPDATA_17
NC_DVPDATA_18
NC_DVPDATA_19
NC_DVPDATA_20
NC_DVPDATA_21
NC_DVPDATA_22
NC_DVPDATA_23

I2C

GPIO5 fast-power reduction:
HW control will casue display disturb
should use SW method control

R429
10K_0402_5%

X76@
R428
10K_0402_5%

X76@
R427
10K_0402_5%

R426
10K_0402_5%

X76@

2

00

Global Swap Lock on
Multiple GPUs

2

1

0

VRAM ID

+1.8VSG

2

VRAM_ID0
VRAM_ID1
VRAM_ID2
VRAM_ID3

001

00: No audio function;
10: Audio for DisplayPort only;
01: Audio for DisplayPort and HDMI if adapter is detected;
11: Audio for both DisplayPort and HDMI
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on
1= Advertises the PCI-E device as 5.0 GT/s capable at power-on
5.0 GT/s capability will be controlled by software

BIF_GEN2_EN GPIO2
RESERVED

1

memory apertures
CONFIG[3:0]
128 MB 000
256 MB 001 *
64 MB 010

Enable external BIOS ROM device (Internal PD)
0: Diable, 1: Enable

BIOS_ROM_EN GPIO22

NC on Park,
Robson and Seymour
NC on Park, Robson

AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AT25
AR24

GPU_THERM_D+
2200P_0402_50V7K
1
2
C325 VGA@
GPU_THERM_D-

2

GPIO0

DPA

1
1 VGA@

5

TX_PWRS_ENB

0

Transmitter Power Saving Enable (Internal PD)
0: 50% Tx output swing
1: full Tx output swing

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

AU24
AV23

2

GPIO9

U9 VGA@

TXCAP_DPA3P
TXCAM_DPA3N

2

VGA_DIS

VGA Disable determines (Internal PD)
0: VGA Controller capacity enabled
1: The device will not be recognized as the system’s VGA controller

External VGA Thermal Sensor

+3VSG

Don't have this strap on
Whistler and Seymour

0

C324
0.1U_0402_16V4Z

VIP Device Strap Enable indicates to the software driver (Internal PD)
V2SYNC 0: Driver would ignore the value sampled on VHAD_0 during reset
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device

VIP_DEVICE_EN

1

Pin Straps description 

1

Strap Name

C

D

Title

Vancouver_Strape/DP/HDMI//CRT
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011
E

Sheet

19

of

49

MVREFSA

1

2

VGA@

2

VGA@

2

+1.5VSG

R454
R455
R456
R457
R458
R460

1 VGA@
1 VGA@
1 VGA@
1 VGA@
1 VGA@
1 VGA@

2
L27
2 243_0402_1% N12
2 243_0402_1% AG12
243_0402_1%
2
M12
2 243_0402_1% M27
2 243_0402_1% AH12
243_0402_1%

NC_MVREFDA
NC_MVREFSA

NC_CKEA0
NC_CKEA1

NC_MEM_CALRN0
MEM_CALRN1
NC_MEM_CALRN2

NC_WEA0B
NC_WEA1B

MEM_CALRP1
NC_MEM_CALRP0
NC_MEM_CALRP2

NC_MAA0_8
NC_MAA1_8

J14
H14

CLKA1
CLKA1#

K23
K19

RASA0#
RASA1#

K20
K17

CASA0#
CASA1#

K24
K27

CSA0#_0

M13
K16

CSA1#_0

K21
J20

CKEA0
CKEA1

K26
L15

WEA0#
WEA1#

H23
J19

QSA[0..7]

23

MVREFDB

1

R449 VGA@
100_0402_1%

QSA#[0..7]

QSA#[0..7]

VGA@

2

23
+1.5VSG

R451
VGA@
40.2_0402_1%
ODTA0
ODTA1

23
23

CLKA0
CLKA0#

23
23

CLKA1
CLKA1#

23
23

15mil
MVREFSB

RASA0#
RASA1#

23
23

CASA0#
CASA1#

23
23

CSA0#_0

23

CSA1#_0

23

CKEA0
CKEA1

23
23

WEA0#
WEA1#

23
23

MAA13

1

R453
VGA@
100_0402_1%

VGA@

2

MVREFDB Y12
MVREFSB AA12
R459
5.11K_0402_1%
TESTEN
2 VGA@ 1

23

TEST_MCLK
TEST_YCLK

2160809000A11SEYMOU_FCBGA962
VGA@

2

2

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

RASB0B
RASB1B

T10
Y10

RASB0#
RASB1#

CASB0B
CASB1B

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B

CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

WEB0B
WEB1B
AD28
AK10
AL10

C361
0.1U_0402_16V4Z

@

C360
0.1U_0402_16V4Z

3

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MEMORY INTERFACE B

CLKA0
CLKA0#

1

L18
L20

H27
G27

15mil

2

MVREFDA
MVREFSA

ODTA0
ODTA1

QSA[0..7]

C358
0.1U_0402_16V4Z

100_0402_1%

C357
0.1U_0402_16V4Z

R452

1

J21
G19

VGA@

MAB[0..12]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

TESTEN

MAB0_8
MAB1_8

CLKTESTA
CLKTESTB

DRAM_RST

1

1

QSB[0..7]

T8
W8

R461 10_0402_5%
1
2
VGA@

AH11

DQMB#[0..7]

24

24
24

CLKB1
CLKB1#

24
24

RASB0#
RASB1#

24
24

CASB0#
CASB1#

24
24

CSB0#_0

24

CSB1#_0

24

CKEB0
CKEB1

24
24

WEB0#
WEB1#

24
24

MAB13

24

24

24

2

2
VGA@ 51.1_0402_1%

VRAM_RST# 23,24

R463

VGA@

1

3

C359

VGA@
2160809000A11SEYMOU_FCBGA962
VGA@

5.11K_0402_1%

2

120P_0402_50V8

Place all these components very close
to GPU (Within 25mm) and
keep all component close to
each Other (within5mm) except Rser2

2

2

24
24

CLKB0
CLKB0#

R462

24

QSB#[0..7]

ODTB0
ODTB1

1

B_BA[0..2]

QSB[0..7]

QSB#[0..7]

R465
@
51.1_0402_1%

Note:
route 50ohms single-ended
and 100ohms diff
and keep short
REF137-03 suggest

1

B_BA[0..2]

DQMB#[0..7]

@

R464
@
51.1_0402_1%

MAB[0..12] 24

2

2

15mil

R447
40.2_0402_1%

DDR2
GDDR5/GDDR3
DDR3

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

1

VGA@

QSA#0
QSA#1
QSA#2
QSA#3
QSA#4
QSA#5
QSA#6
QSA#7

23

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

E

GDDR5

R450
40.2_0402_1%

A34
E30
E26
C20
C16
C12
J11
F8

DQMA#[0..7]

+1.5VSG
DQMA#[0..7]

1

1

+1.5VSG

C34
D29
D25
E20
E16
E12
J10
D7

QSA0
QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

23

1

VGA@

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

A_BA[0..2]

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

1

1
2

2

A32
C32
D23
E22
C14
A14
E10
D9

A_BA[0..2]

U8D
DDR2
GDDR3/GDDR5
DDR3

MDB[0..63]

MDB[0..63]

C356
0.1U_0402_16V4Z

100_0402_1%

1

C355
0.1U_0402_16V4Z

VGA@

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
A_BA2
A_BA0
A_BA1

24

2

2

15mil
MVREFDA

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

MAA[0..12] 23

1

VGA@
40.2_0402_1%

NC_DQA0_0/DQA_0
NC_MAA0_0/MAA_0
NC_DQA0_1/DQA_1
NC_MAA0_1/MAA_1
NC_DQA0_2/DQA_2
NC_MAA0_2/MAA_2
NC_DQA0_3/DQA_3
NC_MAA0_3/MAA_3
NC_DQA0_4/DQA_4
NC_MAA0_4/MAA_4
NC_DQA0_5/DQA_5
NC_MAA0_5/MAA_5
NC_DQA0_6/DQA_6
NC_MAA0_6/MAA_6
NC_DQA0_7/DQA_7
NC_MAA0_7/MAA_7
NC_DQA0_8/DQA_8
NC_MAA1_0/MAA_8
NC_DQA0_9/DQA_9
NC_MAA1_1/MAA_9
NC_DQA0_10/DQA_10
NC_MAA1_2/MAA_10
NC_DQA0_11/DQA_11
NC_MAA1_3/MAA_11
NC_DQA0_12/DQA_12
NC_MAA1_4/MAA_12
NC_DQA0_13/DQA_13
NC_MAA1_5/MAA_13_BA2
NC_DQA0_14/DQA_14
NC_MAA1_6/MAA_14_BA0
NC_DQA0_15/DQA_15
NC_MAA1_7/MAA_A15_BA1
NC_DQA0_16/DQA_16
NC_DQA0_17/DQA_17
NC_WCKA0_0/DQMA_0
NC_DQA0_18/DQA_18
NC_WCKA0B_0/DQMA_1
NC_DQA0_19/DQA_19
NC_WCKA0_1/DQMA_2
NC_DQA0_20/DQA_20
NC_WCKA0B_1/DQMA_3
NC_DQA0_21/DQA_21
NC_WCKA1_0/DQMA_4
NC_DQA0_22/DQA_22
NC_WCKA1B_0/DQMA_5
NC_DQA0_23/DQA_23
NC_WCKA1_1/DQMA_6
NC_DQA0_24/DQA_24
NC_WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
NC_DQA0_25/DQA_25
NC_DQA0_26/DQA_26 NC_EDCA0_0/QSA_0/RDQSA_0
NC_DQA0_27/DQA_27 NC_EDCA0_1/QSA_1/RDQSA_1
NC_DQA0_28/DQA_28 NC_EDCA0_2/QSA_2/RDQSA_2
NC_DQA0_29/DQA_29 NC_EDCA0_3/QSA_3/RDQSA_3
NC_DQA0_30/DQA_30 NC_EDCA1_0/QSA_4/RDQSA_4
NC_DQA0_31/DQA_31 NC_EDCA1_1/QSA_5/RDQSA_5
NC_DQA1_0/DQA_32
NC_EDCA1_2/QSA_6/RDQSA_6
NC_DQA1_1/DQA_33
NC_EDCA1_3/QSA_7/RDQSA_7
NC_DQA1_2/DQA_34
NC_DQA1_3/DQA_35 NC_DDBIA0_0/QSA_0B/WDQSA_0
NC_DQA1_4/DQA_36 NC_DDBIA0_1/QSA_1B/WDQSA_1
NC_DQA1_5/DQA_37 NC_DDBIA0_2/QSA_2B/WDQSA_2
NC_DQA1_6/DQA_38 NC_DDBIA0_3/QSA_3B/WDQSA_3
NC_DQA1_7/DQA_39 NC_DDBIA1_0/QSA_4B/WDQSA_4
NC_DQA1_8/DQA_40 NC_DDBIA1_1/QSA_5B/WDQSA_5
NC_DQA1_9/DQA_41 NC_DDBIA1_2/QSA_6B/WDQSA_6
NC_DQA1_10/DQA_42NC_DDBIA1_3/QSA_7B/WDQSA_7
NC_DQA1_11/DQA_43
NC_DQA1_12/DQA_44
NC_ADBIA0/ODTA0
NC_DQA1_13/DQA_45
NC_ADBIA1/ODTA1
NC_DQA1_14/DQA_46
NC_DQA1_15/DQA_47
NC_CLKA0
NC_DQA1_16/DQA_48
NC_CLKA0B
NC_DQA1_17/DQA_49
NC_DQA1_18/DQA_50
NC_CLKA1
NC_DQA1_19/DQA_51
NC_CLKA1B
NC_DQA1_20/DQA_52
NC_DQA1_21/DQA_53
NC_RASA0B
NC_DQA1_22/DQA_54
NC_RASA1B
NC_DQA1_23/DQA_55
NC_DQA1_24/DQA_56
NC_CASA0B
NC_DQA1_25/DQA_57
NC_CASA1B
NC_DQA1_26/DQA_58
NC_DQA1_27/DQA_59
NC_CSA0B_0
NC_DQA1_28/DQA_60
NC_CSA0B_1
NC_DQA1_29/DQA_61
NC_DQA1_30/DQA_62
NC_CSA1B_0
NC_DQA1_31/DQA_63
NC_CSA1B_1

MAA[0..12]

2

R446

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DDR2
GDDR5/GDDR3
DDR3

D

1

1

+1.5VSG

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

C

GDDR5

1

R448

U8C
DDR2
GDDR3/GDDR5
DDR3

MDA[0..63]

MDA[0..63]

MEMORY INTERFACE A

23

B

2

A

Park&Seymour is single channel for
memory (channel B only)

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Vancouver_Memory
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

20

of

49

A

B

C

D

：

Seymour/Whistler
PCIE_VDDR,PCIE_PVDD can combian to PCIE_VDDR

U8E
+1.5VSG

2

1

20mil

1
2

1

VGA@
2

Granville PRO VDDC:47A
Madison PRO VDDC+VDDCI=31.3A
Whistler PRO VDDC+VDDCI=24A
SeymourXT VDDC+VDDCI=14.2A
RobsonXT VDDC+VDDCI=12.9A

2

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
3

(GDDR3/DDR3 1.12V@4A VDDCI)
(GDDR5 1.12V@16A VDDCI)

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

SM01000BY00 5000ma 120ohm@100mhz DCR 0.02

160mil

+VDDCI
VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

2

2

2

2

2

VGA@

VGA@

VGA@

VGA@

VGA@

1

1

1

1

1

2

2

2

2

2

2
1
VGA@
L19
FBMA-L11-201209-121LMA50T_0805
2
1
VGA@
L21
FBMA-L11-201209-121LMA50T_0805

+VGA_CORE

Seymour/Whistler

C465
10U_0603_6.3V6M

FB_GND

1

VGA@
2

VGA@
2

C457
1U_0402_6.3V6K

@
R466
0_0402_5%

2

C464
10U_0603_6.3V6M

FB_VDDCI

AH29

1

C463
10U_0603_6.3V6M

FB_GND

VGA@

C462
0.1U_0402_16V4Z

FB_VDDC

NC 20101116

2

1

VGA@
2

2

+VGA_CORE

BIF_VDDC
Park/Madison:Connect to VDDC
Seymour/Whisler:
dGPU operating:VDDC
BACO mode:+1.0V

C461
1U_0402_6.3V6K

AF28
AG28

1

VGA@

1

VGA@
2

VGA@

C456
1U_0402_6.3V6K

10mil

2

2

VGA@
2

C455
1U_0402_6.3V6K

GCORE_SEN

1

VGA@

1

VGA@

VGA@
2

C454
1U_0402_6.3V6K

VOLTAGE
SENESE

2

2

1

2010/04/27
non-BACO design,N27,T27
connect BIF_VDDC to VDDC
For BACO design

Granville VDDCI:4.6A
VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
5A VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

1

VGA@

VGA@

C453
1U_0402_6.3V6K

GCORE_SEN

120mA

SPVSS

1

VGA@
2

2

C452
1U_0402_6.3V6K

48

SPV10

2

C451
1U_0402_6.3V6K

2

AN9
AN10

2

C450
1U_0402_6.3V6K

2

75mA

1

1

VGA@

+BIF_VDDC

C449
1U_0402_6.3V6K

2

470ohm/1A

SM010030010
200ma 120ohm@100mhz DCR 0.2

+SPV10

VGA@

SPV18

+BIF_VDDC

C448
1U_0402_6.3V6K

1

C447
0.1U_0402_16V4Z

VGA@
1

C446
1U_0402_6.3V6K

VGA@
1

150mA

AM10

VGA@

2

2

VGA@

1

C425
1U_0402_6.3V6K

2

BLM18AG121SN1D_0603
VGA@

+SPV_18

1

VGA@

1

2

1

C414
1U_0402_6.3V6K

+1.0VSG

C445
10U_0603_6.3V6M

2

L18

2

VGA@

2

VGA@

1

C424
1U_0402_6.3V6K

VGA@
1

C460
0.1U_0402_16V4Z

2

C459
1U_0402_6.3V6K

C458
10U_0603_6.3V6M

2

VGA@
1

MPV18#1
MPV18#2

1
VGA@

1

VGA@

2

1

C413
1U_0402_6.3V6K

10mil
VGA@
1

H7
H8

2

VGA@

2

1

C423
1U_0402_6.3V6K

L20
2
1
BLM18AG121SN1D_0603
VGA@

+MPV_18

1
VGA@

VGA@

1

C412
1U_0402_6.3V6K

+1.8VSG

20mil

2

1

C434
10U_0603_6.3V6M

SM010030010
200ma 120ohm@100mhz DCR 0.2

PLL

VGA@

1

C422
1U_0402_6.3V6K

2

1

C411
1U_0402_6.3V6K

2

C395
10U_0603_6.3V6M

2

+1.0VSG

Granville VDDC:47A

C433
10U_0603_6.3V6M

2

NC_VDDRHB
NC_VSSRHB

2

C421
1U_0402_6.3V6K

2

V12
U12

2

C410
1U_0402_6.3V6K

VGA@
1

C444
0.1U_0402_16V4Z

VGA@
1

C443
1U_0402_6.3V6K

VGA@
1

C442
0.1U_0402_16V4Z

VGA@
1

C441
1U_0402_6.3V6K

3

VGA@
1

C440
10U_0603_6.3V6M

L17
2
1
BLM18AG121SN1D_0603
VGA@

NC_VDDRHA
NC_VSSRHA

2

C394
1U_0402_6.3V6K

+1.8VSG

M20
M21

2

C432
10U_0603_6.3V6M

SM010030010
200ma 120ohm@100mhz DCR 0.2

2

C420
1U_0402_6.3V6K

470ohm/1A

2

C409
1U_0402_6.3V6K

170mA

2

C370
1U_0402_6.3V6K

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

2

C431
10U_0603_6.3V6M

AD12
AF11
AF12
AG11

VGA@
1

C419
1U_0402_6.3V6K

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

VGA@
1

C408
1U_0402_6.3V6K

+VDDR4_5

60mA

VGA@
1

C369
1U_0402_6.3V6K

AF13
AF15
AG13
AG15

20mil

VGA@
1

C430
10U_0603_6.3V6M

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

VGA@
1

C418
1U_0402_6.3V6K

2

AF23
AF24
AG23
AG24

1

VGA@
1

C407
1U_0402_6.3V6K

10mil

1
+1.8VSG
L13 VGA@
FBMA-L11-201209-221LMA30T_0805

220ohm/2A

VGA@
1

C429
10U_0603_6.3V6M

2

VGA@

C439
0.1U_0402_16V4Z

2

2

219mA

I/O

VGA@
1

C438
1U_0402_6.3V6K

VGA@

VGA@
1

C437
10U_0603_6.3V6M

VGA@
1

2

1

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

2

VGA@
1

C428
10U_0603_6.3V6M

1

L16

VGA@
C426
1U_0402_6.3V6K

2

+1.8VSG

120ohm/0.3ABLM18AG121SN1D_0603

C415
10U_0603_6.3V6M

2

SM010030010
300ma 120ohm@100mhz DCR 0.3

1

VGA@

C427
0.1U_0402_16V4Z

1

AF26
AF27
AG26
AG27

2

2

C393
1U_0402_6.3V6K

20mil
+VDD_CT

+3VSG
2

LEVEL
TRANSLATION

2

C417
1U_0402_6.3V6K

VGA@

2

2

C416
1U_0402_6.3V6K

2

1

POWER

Ref137-12~ remove Bead

C403
1U_0402_6.3V6K

C402
10U_0603_6.3V6M

2

VGA@

2

C368
1U_0402_6.3V6K

1

VGA@

C404
0.1U_0402_16V4Z

1

VGA@

2

C406
1U_0402_6.3V6K

120ohm/0.3A

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

VGA@
1

C405
1U_0402_6.3V6K

2

+1.8VSG

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
47A VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
55mA VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

VGA@
1

C392
1U_0402_6.3V6K

2

3400mA 2A

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

+PCIE_VDDR
VGA@ VGA@
1
1

C391
1U_0402_6.3V6K

1
L14
BLM18AG121SN1D_0603

2

C401
1U_0402_6.3V6K

2

C400
1U_0402_6.3V6K

2

C399
1U_0402_6.3V6K

2

C398
1U_0402_6.3V6K

2

C397
10U_0603_6.3V6M

C373
10U_0603_6.3V6M

2

C372
10U_0603_6.3V6M

2

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VGA@
1

C384
10U_0603_6.3V6M

2

VGA@
1

C365
1U_0402_6.3V6K

2

SM010014520 3000ma 220ohm@100mhz DCR 0.04

40mil

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

C383
1U_0402_6.3V6K

2

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
440mA PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

C364
1U_0402_6.3V6K

2

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

C382
0.1U_0402_16V4Z

2

C390
1U_0402_6.3V6K

2

C389
1U_0402_6.3V6K

2

C367
1U_0402_6.3V6K

VGA@
1

C388
1U_0402_6.3V6K

VGA@
1

C387
1U_0402_6.3V6K

VGA@
1

C386
1U_0402_6.3V6K

VGA@
1

C366
1U_0402_6.3V6K

VGA@
1

PCIE
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

C381
0.1U_0402_16V4Z

2

C363
1U_0402_6.3V6K

C380
1U_0402_6.3V6K

C379
1U_0402_6.3V6K

2

VGA@
1

C371
10U_0603_6.3V6M

SM010030010
300ma 120ohm@100mhz DCR 0.3

2

MEM I/O

VGA@
1

VGA@
1

C385
1U_0402_6.3V6K

2

2

VGA@
1

VGA@
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1

C396
10U_0603_6.3V6M

VGA@

2

VGA@
1

VGA@
1

1

1

2

VGA@
1

C378
1U_0402_6.3V6K

C374 change to SF000002Z00
20101228

2

VGA@
1

C377
1U_0402_6.3V6K

2

VGA@
1

C362
1U_0402_6.3V6K

2

VGA@
1

C376
1U_0402_6.3V6K

+

C375
1U_0402_6.3V6K

VGA@
1

1
VGA@
C374
330U_2.5V_M

E

2160809000A11SEYMOU_FCBGA962
VGA@

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

Deciphered Date

2012/07/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Title

Vancouver_Power/GND
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

21

of

49

A

B

U8F

1

U8H
DP C/D POWER

Manhatann:300mA
Seymour:150mA

20mil
+DPABCD_VDD18

AP20
AP21

AP13
AT13
AN17
AP16
AP17
AW14
AW16

20mil
+DPABCD_VDD18

AP22
AP23

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

DP A/B POWER

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AN24
AP24

AP31
AP32

20mil
+DPABCD_VDD18

20mil
+DPABCD_VDD10

+DPABCD_VDD10

+DPABCD_VDD18

AN33
AP33

+DPABCD_VDD10

1 VGA@ 1 VGA@ 1 VGA@

25
2

PX_EN: PU at P.20
SBIOS will control VGA power on/off.
High :BACO mode enable
LOW:BACO disable

2

2

AH34
AJ34

DPAB_CALR

AW28

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

AU28
AV27

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

AF34
AG34

DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS
AK33
AK34

+DPABCD_VDD18

+DPABCD_VDD18

AF39
AH39
AK39
AL34
AM34

+DPABCD_VDD18

AV19
AR18

+DPABCD_VDD18

AM37
AN38

AL38
AM35

2

2

+1.0VSG
2

FootPrint

10mil

10mil

10mil

10mil
3

+DPEF_VDD18

20mA

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2
DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS

C483
0.1U_0402_16V4Z

2

AU18
AV17

L25
MBK1608221YZF_2P
2
1
VGA@

220mA

R468
150_0402_1%
2
VGA@

20mA

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

1 VGA@ 1 VGA@ 1 VGA@

2

1

20mA
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

20mil
+DPEF_VDD10

2

AV29
AR28

+1.8VSG

FootPrint

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

2

20mA
AL33
AM33

2

VGA@

1 VGA@ 1 VGA@ 1 VGA@

20mA

DP mode:220mA
LVDS mode:240mA

L27
MBK1608221YZF_2P
2
1
VGA@

20mil

20mA

AN34
AP39
AR39
AU37

20mil

FootPrint

DPCD_CALR

20mil
+DPEF_VDD10

+DPEF_VDD18

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

+1.0VSG

AW18

1

C477
10U_0603_6.3V6M

FootPrint
PX_EN

AN29
AP29
AP30
AW30
AW32

2

VGA@

20mil

AP25
AP26

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

20mil
+DPEF_VDD18
C480
0.1U_0402_16V4Z

PX_EN

L26
MBK1608221YZF_2P
2
1
VGA@

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

1

C476
1U_0402_6.3V6K

+1.8VSG

R467
150_0402_1%
2
1
VGA@

DP mode:300mA
LVDS mode:440mA

AN19
AP18
AP19
AW20
AW22

2

VGA@

C475
0.1U_0402_16V4Z

SM01000BL00
1000ma 470ohm@100mhz DCR 0.2

AP14
AP15

1

AN27
AP27
AP28
AW24
AW26

20mil
Manhatann:220mA
Seymour:110mA

L23
MBK1608221YZF_2P
2
1
VGA@

300mA

C471
1U_0402_6.3V6K

20mil
+DPABCD_VDD10

C482
1U_0402_6.3V6K

A

1

+DPEF_VDD18

10mil

10mil

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

R470
2

1 AM39
VGA@
150_0402_1%

DPEF_CALR
2160809000A11SEYMOU_FCBGA962
VGA@

Park/Madison :AL21left NC

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

2160809000A11SEYMOU_FCBGA962
VGA@

REF137-13 update

DPx-VSSR,DPx_PVSS can combian to DP_VSSR
(Manhatann should have individual GND)
where x is A,B,C,D,E,F

C479
1U_0402_6.3V6K

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

E

C470
0.1U_0402_16V4Z

GND

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

C481
10U_0603_6.3V6M

4

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

C478
10U_0603_6.3V6M

3

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

D

：

Seymour/Whistler
DPA_VDD10,DPB_VDD10
can combian to DPAB_VDD10
DPC_VDD10,DPD_VDD10
can combian to DPCD_VDD10
DPE_VDD10,DPD_VDD10
can combian to DPEF_VDD10

C469
10U_0603_6.3V6M

2

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

C

DPA_VDD18,DPA_PVDD,DPB_VDD18,DPB_PVDD
can combian to DPAB_VDD18
DPC_VDD18,DPC_PVDD,DPD_VDD18,DPD_PVDD
can combian to DPCD_VDD18
(DPD_VDD18,DPD_PVDD not applicable on Robson/Park)
DPE_VDD18,DPE_PVDD,DPF_VDD18,DPF_PVDD
can combian to DPEF_VDD18

A39
AW1
AW39

Seymour/Whistler:
AL21:PX_EN
use to control discreate GPU regulators
for power express BACO mode
Support BACO:
output High3.3V:turn off regulators (BACO mode on)
output Low0V:turn on regulators (BACO mode off)
need PD resistor
No support BACO:
left NC
B

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/07/12

2012/07/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

D

Title

Vancouver_Power/GND
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

22

of

49

C

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

Pull high for Madison and Park...

R476
4.99K_0402_1% VGA@

QSA#4
QSA#5

G3
B7

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

E7
D3

J1
L1
J9
L9

R473
243_0402_1%
VGA@

ODTA1_1
CSA1#_0
RASA1#
CASA1#
WEA1#

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

QSA6
QSA7

F3
C7

DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA#6
DQMA#7

E7
D3

DQSL
DQSU

QSA#6
QSA#7

G3
B7

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

R478
4.99K_0402_1% VGA@

J1
L1
J9
L9

R474
243_0402_1%
VGA@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

+1.5VSG

R477
4.99K_0402_1% VGA@

A1
A8
C1
C9
D2
E9
F1
H2
H9

+1.5VSG

R479
4.99K_0402_1% VGA@

MDA63
MDA58
MDA60
MDA59
MDA61
MDA56
MDA62
MDA57

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

R480
VGA@
4.99K_0402_1%

1

+1.5VSG

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

2

B1
B9
D1
D8
E2
E8
F9
G1
G9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

R481
4.99K_0402_1% VGA@

+1.5VSG

R482
4.99K_0402_1% VGA@
3

2

15mil

15mil
VREFDA_Q1

1

VREFCA_A1

2

VGA@

1

2

R488
4.99K_0402_1%
VGA@

1

VREFCA_A2

C485
VGA@

+1.5VSG

2

R489
4.99K_0402_1%
VGA@

C486
VGA@

1

2

15mil

VREFDA_Q2

R490
4.99K_0402_1%
VGA@

C487
VGA@

+1.5VSG

1

2

15mil

VREFCA_A3
R491
4.99K_0402_1%
VGA@

C488
VGA@

1

2

15mil

VREFDA_Q3
R492
C489
4.99K_0402_1%
VGA@

1

VREFCA_A4

VGA@

2

R493
4.99K_0402_1%
VGA@

15mil

1

C490

VREFDA_Q4

VGA@

2

R494
C491
4.99K_0402_1%
VGA@

1

0.1U_0402_16V4Z

C484

15mil

0.1U_0402_16V4Z

R487
4.99K_0402_1%
VGA@

15mil

0.1U_0402_16V4Z

ODTA1_1

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DQMA#4
DQMA#5

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

0.1U_0402_16V4Z

R486
56_0402_1%
2
VGA@

ZQ/ZQ0

F3
C7

0.1U_0402_16V4Z

R485
0_0402_5%
ODTA1 2
1
1
VGA@

RESET

0.1U_0402_16V4Z

ODTA1

R475
4.99K_0402_1% VGA@

0.1U_0402_16V4Z

20

R484
VGA@
56_0402_1%
ODTA0 2
1
1
2
R483
0_0402_5% VGA@

DQSL
DQSU

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

+1.5VSG

0.1U_0402_16V4Z

ODTA0

J1
L1
J9
L9

R472
243_0402_1%
VGA@

1

ODTA0_1

20

L8

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

+1.5VSG

3

VRAM_RST# T2

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

2

R471
243_0402_1%
VGA@

ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

QSA4
QSA5

CK
CK
CKE/CKE0

D7
C3
C8
C2
A7
A2
B8
A3

2

J1
L1
J9
L9

RESET

G3
B7

DML
DMU

CSA1#_0
RASA1#
CASA1#
WEA1#

J7
K7
K9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

1

1

L8

QSA#3
QSA#1

DQSL
DQSU

20
20
20
20

CLKA1
CLKA1#
CKEA1
+1.5VSG

MDA48
MDA51
MDA55
MDA54
MDA50
MDA52
MDA49
MDA53

2

T2

E7
D3

ODT/ODT0
CS/CS0
RAS
CAS
WE

BA0
BA1
BA2

E3
F7
F2
F8
H3
H8
G2
H7

1

VRAM_RST#

20,24 VRAM_RST#

DQSL
DQSU

DQMA#3
DQMA#1

K1
L2
J3
K3
L3

M2
N8
M3

2

G3
B7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

CK
CK
CKE/CKE0

A_BA0
A_BA1
A_BA2

+1.5VSG

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

QSA#2
QSA#0

F3
C7

J7
K7
K9

B2
D9
G7
K2
K8
N1
N9
R1
R9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

2

QSA#[7..0]

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

QSA3
QSA1

CLKA1
CLKA1#
CKEA1
ODTA1_1

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

20

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

20

DML
DMU

K1
L2
J3
K3
L3

+1.5VSG

MDA43
MDA44
MDA40
MDA45
MDA42
MDA46
MDA41
MDA47

VREFCA
VREFDQ

2

E7
D3

DQSL
DQSU

ODTA0_1
CSA0#_0
RASA0#
CASA0#
WEA0#

BA0
BA1
BA2

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

1

DQMA#2
DQMA#0

2

ODT/ODT0
CS/CS0
RAS
CAS
WE

A1
A8
C1
C9
D2
E9
F1
H2
H9

M2
N8
M3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A4
VREFDA_Q4

2

QSA[7..0]

CK
CK
CKE/CKE0

A_BA0
A_BA1
A_BA2

+1.5VSG

2

20

F3
C7

J7
K7
K9

B2
D9
G7
K2
K8
N1
N9
R1
R9

MDA35
MDA32
MDA38
MDA34
MDA37
MDA36
MDA39
MDA33

2

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQMA#[7..0]
QSA2
QSA0

CLKA0
CLKA0#
CKEA0
+1.5VSG

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

E3
F7
F2
F8
H3
H8
G2
H7

1

ODT/ODT0
CS/CS0
RAS
CAS
WE

BA0
BA1
BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

1

20

CSA0#_0
RASA0#
CASA0#
WEA0#

K1
L2
J3
K3
L3

M2
N8
M3

VREFCA
VREFDQ

2

20
20
20
20

CK
CK
CKE/CKE0

A_BA0
A_BA1
A_BA2

+1.5VSG

MDA15
MDA11
MDA14
MDA10
MDA13
MDA9
MDA12
MDA8

M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

1

ODTA0_1

MAA[13..0]

J7
K7
K9

B2
D9
G7
K2
K8
N1
N9
R1
R9

D7
C3
C8
C2
A7
A2
B8
A3

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

U14

2

CLKA0
CLKA0#

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA_A3
VREFDA_Q3

1

CKEA0

BA0
BA1
BA2

MDA25
MDA30
MDA24
MDA29
MDA26
MDA31
MDA27
MDA28

2

20

M2
N8
M3

MDA[0..63]

MDA[0..63]

20

A_BA0
A_BA1
A_BA2

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

20

20
20
20

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

X76L04@

MDA0
MDA5
MDA1
MDA7
MDA3
MDA4
MDA2
MDA6

VREFCA
VREFDQ

1

2GVRAM-HYNIX

X76L03@

D7
C3
C8
C2
A7
A2
B8
A3

M8
H1

2

1GVRAM-HYNIX

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

1

ZZZ4

VREFCA_A2
VREFDA_Q2

2

ZZZ3
1

MDA22
MDA19
MDA21
MDA18
MDA23
MDA16
MDA20
MDA17

1

X76L02@

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

1

X76L01@

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

2

2GVRAM-SAM

VREFCA
VREFDQ

1

1GVRAM-SAM

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

E

U13

2

VREFCA_A1 M8
VREFDA_Q1 H1

ZZZ2

2

ZZZ1

D

U12

1

B

U11

1

A

VGA@

2

+1.5VSG
+1.5VSG

2

2

2

2

2

2

2

2

2

2

1
VGA@

2
56_0402_1%
1
VGA@

C521
0.01U_0402_16V7K

2

2

2

2

2

2

2

2

2

2

2

4

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

VGA@
1

2

C518
10U_0603_6.3V6M

2

VGA@

VGA@
1

C517
10U_0603_6.3V6M

1
R498

VGA@
1

C520
10U_0603_6.3V6M

CLKA1#

VGA@
1

C519
10U_0603_6.3V6M

20

2
56_0402_1%

VGA@
1
C516
10U_0603_6.3V6M

1
R497

VGA@
1
C515
10U_0603_6.3V6M

CLKA1

VGA@
1
C514
10U_0603_6.3V6M

VGA@
20

VGA@
1
C513
10U_0603_6.3V6M

2
4

+1.5VSG

+1.5VSG
C512
0.01U_0402_16V7K

VGA@
1

2010/07/12

2012/07/12

Deciphered Date

Title

VRAM_DDR3 / Channel A

2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

C511
1U_0402_6.3V6K

2

VGA@
1

C510
1U_0402_6.3V6K

2

VGA@
1

C509
1U_0402_6.3V6K

2

VGA@
1

C508
1U_0402_6.3V6K

2

2
56_0402_1%

VGA@
1

C507
1U_0402_6.3V6K

2

VGA@

C506
1U_0402_6.3V6K

VGA@
1

C505
1U_0402_6.3V6K

VGA@
1

C504
1U_0402_6.3V6K

VGA@
1

C503
1U_0402_6.3V6K

VGA@
1

C502
1U_0402_6.3V6K

VGA@
1

C501
1U_0402_6.3V6K

VGA@
1

C500
1U_0402_6.3V6K

VGA@
1

C499
1U_0402_6.3V6K

VGA@
1

C498
1U_0402_6.3V6K

VGA@
1

C497
1U_0402_6.3V6K

1
R496

VGA@
1

C496
1U_0402_6.3V6K

CLKA0#

VGA@
1

C495
1U_0402_6.3V6K

20

2
56_0402_1%

VGA@
1

C494
1U_0402_6.3V6K

1
R495

VGA@
1

C493
1U_0402_6.3V6K

CLKA0

VGA@
1

C492
1U_0402_6.3V6K

VGA@
20

VGA@
1

D

Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

23

of

49

A

B

C

U15
VREFCB_A1 M8
VREFDB_Q1 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

1

B_BA0
B_BA1
B_BA2

20

CKEB0

CLKB0
CLKB0#

MAB[13..0]

20

ODTB0_1
20
20
20
20

DQMB#[7..0]

MDB26
MDB28
MDB27
MDB31
MDB25
MDB30
MDB24
MDB29

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB12
MDB11
MDB13
MDB9
MDB14
MDB8

M2
N8
M3

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

CSB0#_0
RASB0#
CASB0#
WEB0#

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB0
CLKB0#
CKEB0

J7
K7
K9

CK
CK
CKE/CKE0

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

DQSL
DQSU

+1.5VSG
ODTB0_1
CSB0#_0
RASB0#
CASB0#
WEB0#

A1
A8
C1
C9
D2
E9
F1
H2
H9

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB22
MDB20
MDB21
MDB18
MDB19
MDB17
MDB23
MDB16

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB1
MDB6
MDB0
MDB4
MDB3
MDB7
MDB2
MDB5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

J7
K7
K9

QSB3
QSB1

VREFCB_A2 M8
VREFDB_Q2 H1

VREFCB_A3 M8
VREFDB_Q3 H1
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

20

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

B_BA0
B_BA1
B_BA2

M2
N8
M3

BA0
BA1
BA2

CLKB1
CLKB1#

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

CKEB1
ODTB1_1

A1
A8
C1
C9
D2
E9
F1
H2
H9

20
20
20
20

CSB1#_0
RASB1#
CASB1#
WEB1#
QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDB35
MDB37
MDB34
MDB39
MDB33
MDB38
MDB32
MDB36

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB43
MDB47
MDB41
MDB45
MDB40
MDB46
MDB42

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

VREFCA
VREFDQ

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

+1.5VSG

U18

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

CLKB1
CLKB1#
CKEB1

J7
K7
K9

CK
CK
CKE/CKE0

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

F3
C7

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B2
D9
G7
K2
K8
N1
N9
R1
R9

1

+1.5VSG

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU

+1.5VSG

A1
A8
C1
C9
D2
E9
F1
H2
H9

B1
B9
D1
D8
E2
E8
F9
G1
G9

R500
243_0402_1%

+1.5VSG

J1
L1
J9
L9

VGA@

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VRAM_RST#

L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R501
243_0402_1%

DQSL
DQSU

RESET
ZQ/ZQ0
NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VGA@

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

+1.5VSG

T2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VRAM_RST#

B1
B9
D1
D8
E2
E8
F9
G1
G9

R502
243_0402_1%

R524

1

1

1

2

2

VREFDB_Q2

VREFCB_A3

2

R519
4.99K_0402_1%

VREFDB_Q3

1

2

R520
4.99K_0402_1%

C527
VGA@
VGA@

1

2

R521
4.99K_0402_1%

C

2

+1.5VSG

VGA@

1

2

1
VGA@ VGA@
2

1

2

VGA@
1

VGA@
1

VGA@
1

VGA@
1

2

2

2

2

2

VGA@
C558
10U_0603_6.3V6M

B

1

C550
1U_0402_6.3V6K

2

4

Compal Electronics, Inc.
2012/07/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

C529
VGA@
VGA@

VGA@
1

Compal Secret Data
2010/07/12

2

C549
1U_0402_6.3V6K

2

2

Issued Date

VREFDB_Q4

R522
4.99K_0402_1%

C548
1U_0402_6.3V6K

2

1

Security Classification

1

C547
1U_0402_6.3V6K

2

C557
10U_0603_6.3V6M

2

2

C556
10U_0603_6.3V6M

2

2

VGA@
1

C546
1U_0402_6.3V6K

2

VGA@
1

C555
10U_0603_6.3V6M

C559
0.01U_0402_16V7K

2

VGA@
1

C553
10U_0603_6.3V6M

2

2

2

C554
10U_0603_6.3V6M

VGA@

2

1 VGA@

C552
10U_0603_6.3V6M

1

2

1 VGA@ 1 VGA@ 1 VGA@
C551
10U_0603_6.3V6M

R525
56_0402_1%
1
2
VGA@
R526
56_0402_1%
1
2
VGA@

+1.5VSG

VGA@
1

C545
1U_0402_6.3V6K

2

VGA@
1

C544
1U_0402_6.3V6K

2

C528
VGA@
VGA@

+1.5VSG

C543
1U_0402_6.3V6K

2

VGA@
1

C542
1U_0402_6.3V6K

2

VGA@
1

C541
1U_0402_6.3V6K

2

VGA@
1

C540
1U_0402_6.3V6K

C530
0.01U_0402_16V7K

VGA@
1

C539
1U_0402_6.3V6K

2

VGA@
1

C538
1U_0402_6.3V6K

VGA@
1

3

VGA@

VREFCB_A4

1

C526
VGA@
VGA@

2

1

2

C525
VGA@
VGA@

1

1
2

R518
4.99K_0402_1%

2

1

C537
1U_0402_6.3V6K

VGA@
1

C536
1U_0402_6.3V6K

VGA@
1

R510
4.99K_0402_1%

VGA@

2

2

1

1
2

C524
VGA@
VGA@

C535
1U_0402_6.3V6K

VGA@
1

C534
1U_0402_6.3V6K

VGA@
1

C533
1U_0402_6.3V6K

VGA@
VGA@

CLKB1#

R509
4.99K_0402_1%

VGA@

+1.5VSG

56_0402_1%
2
1

CLKB1

R508
4.99K_0402_1%

VGA@

+1.5VSG

C532
1U_0402_6.3V6K

1

2

+1.5VSG

C531
1U_0402_6.3V6K

CLKB0#

VREFCB_A2
R517
4.99K_0402_1%

R507
4.99K_0402_1%

0.1U_0402_16V4Z

R523 56_0402_1%
2
VGA@

1

B1
B9
D1
D8
E2
E8
F9
G1
G9

+1.5VSG

0.1U_0402_16V4Z

1

2

C523
VGA@
VGA@

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

+1.5VSG

0.1U_0402_16V4Z

CLKB0

VREFDB_Q1

R516
4.99K_0402_1%

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

0.1U_0402_16V4Z

ODTB1_1

1

VGA@

0.1U_0402_16V4Z

0_0402_5%

R515
C522
4.99K_0402_1% VGA@
VGA@

0.1U_0402_16V4Z

R514
56_0402_1%
2
VGA@

0.1U_0402_16V4Z

1

0.1U_0402_16V4Z

VGA@
ODTB1 R513

VGA@

1

VREFCB_A1

0_0402_5%

ODTB1

VGA@

ZQ/ZQ0

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

+1.5VSG

1

1

1

R512
56_0402_1%
2
VGA@

RESET

J1
L1
J9
L9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@

R506
4.99K_0402_1%

2

1

2

VGA@
ODTB0 R511

R505
4.99K_0402_1%

2

ODTB0

2

3

R504
4.99K_0402_1%

T2

VGA@

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

L8

+1.5VSG
R503
4.99K_0402_1% VGA@

DML
DMU

1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

L8

DML
DMU

2

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VRAM_RST# T2

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

1

ZQ/ZQ0

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

RESET

DML
DMU

1

DQSL
DQSU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96
X76@
+1.5VSG

ODTB0_1

20

BA0
BA1
BA2

QSB6
QSB7

MDB55
MDB49
MDB52
MDB50
MDB53
MDB48
MDB54
MDB51

2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

2

VGA@

J1
L1
J9
L9

Pull high for Madison and Park...

4

M2
N8
M3

ODTB1_1
CSB1#_0
RASB1#
CASB1#
WEB1#

A1
A8
C1
C9
D2
E9
F1
H2
H9

E3
F7
F2
F8
H3
H8
G2
H7

1

1
R499
243_0402_1%

20

B_BA0
B_BA1
B_BA2

2

T2
L8

20

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

1

VRAM_RST#

20,23 VRAM_RST#

20

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VSG

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

2

QSB#[7..0]

DML
DMU

1

20

20

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

+1.5VSG

2

2

20

VREFCB_A4 M8
VREFDB_Q4 H1

QSB[7..0]

1

20

E3
F7
F2
F8
H3
H8
G2
H7

MDB[0..63]

MDB[0..63]

20

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

VREFCA
VREFDQ

E

U17

2

20

20
20
20

D

U16

D

Title

VRAM_DDR3 / Channel B
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

24

of

49

5

4

3

Power Sequence of Whistler and Seymour
SUSP#
+3VSG
(JUMP form +3VS)
10ms

VGA_ON
VGA_PWR_ON

D

1.5_VDDC_PWREN
+VGA_CORE
+1.5VSG

2

VGA Muxless with BACO Status Mapping table
Normal mode
BACO mode
PX_EN
0
1
1.5_VDDC_PWREN
1
0
VDDC_EN
1
0
1.0_EN
0
1
+3.3VSG
ON
ON
+1.8VSG
ON
ON
+1.0VSG
ON
ON
+VGA_CORE
ON
OFF
+1.5VSG
ON
OFF
+BIF_VDDC
+VGA_CORE
+1.0VSG

1

VGA Power Enable Signal Mapping table
Whislter
VGA_PWR_ON source signal
VGA_ON
+3.3VSG
SUSP#
+1.8VSG
VGA_PWR_ON
+1.0VSG
VGA_PWR_ON
Combine with +VGA_CORE
+VDDCI
+VGA_CORE
1.5_VDDC_PWREN
1.5_VDDC_PWREN
+1.5VSG

D

+1.0VSG
+1.8VSG

20ms

For PX sequence, >2mS delay is required between
PE_GPIO1 and VGA_PWR_ON
@
R649 1
+3VS

PE_GPIO1
C

>2ms

+3VS

R650 1

B

3

1

VGA@
R652
5.11K_0402_1%

S

1.5_VDD_PWREN

1.5_VDD_PWREN 38,48

NC7SZ08P5X_NL_SC70-5

3
1

D

1 VGA@ 2
2
R651
0_0402_5% G

PX_EN

4

Y
A

VGA@

22

P

2
2 10K_0402_5% 1

G

VGA_PWR_ON

C

VGA@
U19

5

VGA_PWR_ON

2 0_0402_5%

C1103 VGA@
0.1U_0402_16V4Z
1
2

VGA@
Q22
2N7002_SOT23
+5VS

2

+5VS

VGA_PWR_ON 38,42,45

1

1.0_EN

B

P

1 VGA@ 2
2
R655
0_0402_5%
1

Y
A

4

2

G

1.5_VDD_PWREN
13,48 VGA_PWRGD

NC7SZ08P5X_NL_SC70-5

3

From +VGA_CORE regulator

5

Q23B
VGA@
DMN66D0LDW-7_SOT363-6

VGA@
U20

Q23A
VGA@
DMN66D0LDW-7_SOT363-6

B

VDDC_EN

+3VS

3

VGA@ C1104
0.1U_0402_16V4Z
2
1

1
2
10K_0402_1%

5

13,36 PE_GPIO1

VGA@
R654
1K_0402_5%
1

VGA@
R653
1K_0402_5%

@
R119

4

VGA_PWR_ON

2

2

1 VGA@ 2
R111
0_0402_5%

6

VGA_ON

1

Delay SUSP# 10ms
36

For VGA Power on control

+BIF_VDDC
Q24
D

S

3

1

AO3416_SOT23-3

VGA@

20mil

1

30mil

3

AO3416_SOT23-3

@
1
R656

2
0_0805_5%

1
2
G

G

2

+VGA_CORE

Q25
S

VGA@

D

+1.0VSG

B

VGA@
C1105
2 22U_0805_6.3V6M

1.0_EN

C1105 Change to SE00000I10
20101228
2
G
D

S

+VGA_CORE

1
VGA@
Q26
AO3416_SOT23-3

1
D

30mil

3
A

3
VGA@
Q27
AO3416_SOT23-3
S

G

2

VDDC_EN

AO3416 NMOS
Vgs(th)(Max)= 1V
Rds(on)(Max)= 22m ohm @Vgs=4.5V

A

Q24 / Q25 / Q26 / Q27 change to SB00000FG10
20101228

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/04

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

VGA power sequence and BACO
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
1

25

of

49

5

4

3

2

1

EEROM
+3VS

+3VS_PS
+3VS_PS

40mil

40mil
R1160

0_0603_5%
U2

+3VS_PS

8
7
6
5

U46
+1.2VS_PS
+1.2VS_PS

60mil
R1172

L78 2
1 SWR_VDD
FBMA-L11-201209-221LMA30T_0805
@ L77 1
2 SWR_LX
4.7UH_PG031B-4R7MS_1.1A_20%

0_0603_5%

40mil

3

60mil 13
18

60mil 12
60mil 11
27
7

DP_V33

TXEC+
TXEC-

SWR_VDD
PVCC

TXE2+
TXE2-

21
22

APU_TXOUT2+
APU_TXOUT2-

TXE1+
TXE1-

23
24

APU_TXOUT1+
APU_TXOUT1-

TXE0+
TXE0-

25
26

APU_TXOUT0+
APU_TXOUT0-

Power

60mil

D

L76 2
1 DP_V33
FBMA-L11-201209-221LMA30T_0805

APU_TXOUT_CLK+
APU_TXOUT_CLK-

SWR_LX
SWR_VCCK
VCCK
DP_V12

LVDS

+1.2VS

19
20

MIIC_SCL_R
MIIC_SDA_R

APU_TXOUT_CLK+ 27
APU_TXOUT_CLK- 27

8
8

DP0_TXP0_C
DP0_TXN0_C

DP0_AUXP_C
DP0_AUXN_C
DP0_TXP0_C
DP0_TXN0_C

D

APU_TXOUT0+ 27
APU_TXOUT0- 27

+3VS_PS
APU_LVDS_DAT

LANE0P
LANE0N

1

14
15
16
17

1
R1161
1
R1162

2
0_0402_5%
2
0_0402_5%

1
R1164

TL_INVT_PWM 27
TL_ENVDD 27
APU_INVT_PWM 10,27
TL_BKOFF# 27,36

MIIC_SCL

1
R1165

MIIC_SDA

1
R1166

CSCL
CSCL
CSDA

9
10
32

2

1

LVDS_HPD

Close to P18

R1168
100K_0402_5%

2

HPD

LVDS
EDID
ROM

DP_REXT
DP_GND

MIICSCL0
MIICSDA0

31
30

GND

33

APU_LVDS_CLK
APU_LVDS_DAT
MIIC_SCL
1
MIIC_SDA R17 1
R3

APU_LVDS_CLK 27
APU_LVDS_DAT 27

CSDA

1
R1170

MIIC_SCL_R
2
MIIC_SDA_R
0_0402_5%
2
0_0402_5%
+3VS_PS

RTD2132S-GR_QFN32_5X5
2
CSDA

@
Q90A

1

Change to 12Kohm 1% (DG ref.)
20101114

2

1
R1167

1

R30
12K_0402_1%

MIICSCL1
MIICDA1

29
28

1
C29

0.1U_0402_16V4Z

1
C28

2

0.1U_0402_16V4Z

C27

22U_0805_6.3V6M

1

2

SWR_VDD

8
4

CIICSCL1
CIICSDA1

Other

Reserved for EC programming ROM
Need EC confirm

2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%

R1163
APU_LVDS_CLK

GPIO(PWM OUT)
GPIO(Panel_VCC)
GPIO(PWM IN)
GPIO(BL_EN)

2

10

C

5
6

AUX_P
AUX_N

1
2
3
4

APU_TXOUT1+ 27
APU_TXOUT1- 27

RTD2132S
2
1

GPIO

C4

2

1

DP0_AUXP_C
DP0_AUXN_C

DP-IN

0.1U_0402_16V4Z

1
C25

C20
2

0.1U_0402_16V4Z

10U_0603_6.3V6M

1

8
8

A0
A1
A2
GND

CAT24C64WI-GT3_SO8

APU_TXOUT2+ 27
APU_TXOUT2- 27

Close to Pin3
DP_V33

VCC
WP
SCL
SDA

C

EC_SMB_DA2

6

EC_SMB_DA2 6,19,36

DMN66D0LDW-7_SOT363-6
1
R1169

2
0_0402_5%

5

Close to Pin13
+1.2VS_PS

Close to L3

CSCL

4

@
Q90B
3

EC_SMB_CK2

EC_SMB_CK2 6,19,36

DMN66D0LDW-7_SOT363-6
1
R1171

1
C31

2

0.1U_0402_16V4Z

1
C30

2

0.1U_0402_16V4Z

1
C2

2

0.1U_0402_16V4Z
C1489

22U_0805_6.3V6M

1

Close to Pin7

2
0_0402_5%

2

For upgrade Firmwave

Close to
Pin27

B

B

MIIC_SCL

@
1
2
R1175 4.7K_0402_5%

A

A

Compal Secret Data

Security Classification
Issued Date

2010/08/04

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

LVDS Translator - RTD2132S
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
1

26

of

49

4

3

2

D1

3

HSYNC_L
1

2
1

VSYNC_L

YSDA0502C 3P C/A SOT-23
@
VGA_DDC_DATA_C

W=40mils

1
3

+CRT_VCC

3

2

C1573

1

2

C1574

1

2

For EMI
2

C1576

1

2

C1577

2

JCRT1

+CRT_VCC

1
1

2

5
4

1
2
R1650 0_0603_5%

FCH_CRT_DDC_SCL

15 FCH_CRT_DDC_SCL

U88
74AHCT1G125GW_SOT353-5

C1583

1

2

Close to APU

C1584 1

2

2

4

3

FCH_CRT_DDC_SDA
R4
1

2

DMN66D0LDW-7_SOT363-6

FCH_CRT_DDC_SCL
R31 1

For AMD DG-47520-1-10

For EMI, close to JLVDS1.
+LCDVDD

C1586
2

R1656
2

C1589

30
30

DMIC_CLK
DMIC_DATA

Q99B
2N7002DW-7-F_SOT363-6

5

26 APU_TXOUT2R21
26 APU_TXOUT2+
0_0402_5%
@
26 APU_TXOUT_CLK26 APU_TXOUT_CLK+

14
14

+3VS

20_0402_5%

W=60mils

+LCDVDD
+3VS

2

1

1

AZC199-02SPR7G_SOT23-3

R1655 1

@

3

AZC199-02SPR7G_SOT23-3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

B

G1
G2
G3
G4
G5

41
42
43
44
45

HONDA_LVD-A40SFYG+
CONN@

ESD

INVTPWM
1

36 EC_INVT_PWM

2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

JLVDS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

A

BKOFF#

D8
1

RB751V_SOD323
2

R1657
10K_0402_5%

DISPOFF#
2

BKOFF#

10,26 APU_INVT_PWM

2 0_0402_5%

TL_INVT_PWM 1
R722
R1654 1 @

For EMI, close to JLVDS1.

C122
2

R719 1 @

2 0_0402_5%

1

36

R718 1

26 TL_INVT_PWM

R1677
10K_0402_5%

Compal Secret Data

Security Classification

Issued Date

2

A

TL_BKOFF#

@
2

D14
1

@
RB751V_SOD323
2

R1670
10K_0402_5%

1

Panel PWM Control

+3VS

@ D29

1

@ D30
1

Panel Backlight Control

2

2

3

3

26 APU_LVDS_CLK
26 APU_LVDS_DAT

INVTPWM
DISPOFF#

2

@ 1
C1590

2

1
2

2

2

R1662
@

2.2K_0402_5%

R1661
@

100K_0402_5%

2.2K_0402_5%

1

R1660

26,36 TL_BKOFF#

Camera

USB20_N2
USB20_P2

USB20_N2
USB20_P2

0.1U_0402_16V4Z

R712 1

2
0_0402_5%

0.047U_0402_16V7K

26 APU_TXOUT126 APU_TXOUT1+

3

26 TL_ENVDD

2N7002DW-7-F_SOT363-6
Q99A

2

@

1

10 APU_ENVDD

R1659 1 @

2
1
220K_0402_1%

C19

1

0.1U_0402_16V4Z

22P_0402_50V8J

S

1

2
G
2

2

2

W=60mils

4.7U_0805_10V4Z

C1588

3

2

1
C1585
4.7U_0805_10V4Z

26 APU_TXOUT026 APU_TXOUT0+

4

2

1

0.1U_0402_16V4Z

1

6 2

C1587
B

1

1

3

D

1
R1653
47K_0402_5%

R1652
100_0805_5%

W=60mils

L119 1
B+_L
2
FBMA-L11-201209-221LMA30T_0805

B+

+3VS
Q93
SI2301BDS-T1-E3_SOT23-3

1

1

+LCDVDD

1

2

680P_0402_50V7K @
1

+5VALW

VGA_DDC_CLK_C

C1582
@

VGA_DDC_DATA_C
2
0_0402_5%
VGA_DDC_CLK_C
2
0_0402_5%

Panel LCDVDD Control
+LCDVDD

1

VGA_DDC_CLK_C

C

CONN@

VGA_DDC_DATA_C

C1581
@

@

Q101B

15P_0402_50V8J

3

Y

1

VSYNC_L

15P_0402_50V8J

A

16
17

100P_0402_50V8J

C1580
Q101A
DMN66D0LDW-7_SOT363-6
@

5
1
P
OE#

2

G

2

15 FCH_CRT_VSYNC

G
G

SUYIN_070546FR015S263ZR

VGA_DDC_DATA_C

6

100P_0402_50V8J

1

2
1K_0402_5%

CRT_VSYNC_D

R1646
47K_0402_5%
100P_0402_50V8J

R1648 1

2

FCH_CRT_DDC_SDA

15 FCH_CRT_DDC_SDA

R1642
47K_0402_5%

2

R1645

R1644

2

U87
74AHCT1G125GW_SOT353-5

+CRT_VCC

FCH_CRT_VSYNC_R
1
R1651 0_0402_5%

HSYNC_L
BLUE
VSYNC_L

1
HSYNC_L

1
2
R1643 0_0603_5%

2

CRT_HSYNC_D

4

C

C1579
1
2
0.1U_0402_16V4Z

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

T69 PAD

RED

DDC_MD2

2.2K_0402_5%
@

3

Y

0.1U_0402_16V4Z

+CRT_VCC

+3VS

1

A

2

1

2
1K_0402_5%

2.2K_0402_5%
@

2

2

1
C1571
@

BLUE
1

5
1
P
OE#

FCH_CRT_HSYNC_R
1
R1641 0_0402_5%

G

2

D

SMD1812P075TF .75A 13.2V
RB491D_SOT23-3
1
C1570

GREEN

+CRT_VCC
C1578
R1640 1
1
2
0.1U_0402_16V4Z

15 FCH_CRT_HSYNC

3

GREEN

10P_0402_50V8J

1

W=40mils

2

RED

10P_0402_50V8J

C1572

C1575
10P_0402_50V8J

R1639

10P_0402_50V8J

1

R1638

2

2

R1637

10P_0402_50V8J

CRT_B_R

1

2
0_0402_5%

L116
1
2
CHILISIN NBQ160808T-800Y-N 0603
L117
1
2
CHILISIN NBQ160808T-800Y-N 0603
L118
1
2
CHILISIN NBQ160808T-800Y-N 0603
150_0402_1%

2
0_0402_5%

1 R1636

150_0402_1%

1 R1635

2

FCH_CRT_B

CRT_G_R

1

15 FCH_CRT_B

CRT_R_R

150_0402_1%

15 FCH_CRT_G

2
0_0402_5%

1 R1634

L115
1+5VS_CRTVCC
1

2

ESD

D

FCH_CRT_G

D4

YSDA0502C 3P C/A SOT-23

@

YSDA0502C 3P C/A SOT-23
@

FCH_CRT_R

3

VOUT

AP2230_SOT23-3

2

VGA_DDC_CLK_C

1

VIN
@

2

+CRT_VCC

15 FCH_CRT_R

Q92
1

YSDA0502C 3P C/A SOT-23
D6

D2
RED

+5VS

3
@

0.1U_0402_16V4Z

2

GND

BLUE
GREEN

2

CRT

1

D3

10P_0402_50V8J

5

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P10-LVDS/CRT CONN
Size
C
Date:

5

4

3

2

Compal Electronics, Inc.
Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
1

27

of

49

5

4

3

2

1

+5VS

Q95
D

@
1
C1591

+HDMI_5V_OUT

2

1

470K_0402_5%

2

1

1
2

1

2

W=40mils

1

0.5A_15V_SMD1812P050TF
1
C1592

SI3456BDV-T1-E3 1N TSOP6
2

D

EN_HDMI

S

D

HDMI_SDATA

C1601 1

2

0.1U_0402_16V7K

1

S
2

2

D

S
G

8 APU_HDMI_DATA

1

R1679
Q96
SSM3K7002FU_SC70-3

2
G

38,45 SUSP

Q36
BSH111 1N_SOT23-3

3

D

1.5M_0402_5%

1

1
3

8 APU_HDMI_CLK

HDMI_SCLK

3

G

2

2

1
2

1
2

R1678

R750

R749

2K_0402_1%

2K_0402_1%

R748
0_0402_5%

R746

R745

4.7K_0402_5%

4.7K_0402_5%

D

+VSB

G

2

+HDMI_5V_OUT
F2
+HDMI_5V

3

+1.5VS

1U_0603_10V6K

+1.5VS

1U_0603_10V4Z

S

6
5
2
1

4

Q33
BSH111 1N_SOT23-3

+3VS
2

+HDMI_5V_OUT
JHDMI1
HDMI_HPD

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R755
0_0402_5%

1

1

HDMI_SDATA
HDMI_SCLK

1
R762

HDMI_HPD
2
150K_0402_5%

E

HDMI_R_CK+
HDMI_R_D0-

1

3

2
B

Q34
MMBT3904_NL_SOT23-3

HDMI_R_D0+
HDMI_R_D1-

@
R768
365K_0402_1%

HDMI_R_D1+
HDMI_R_D2-

2

10 APU_HDMI_HPD
1

C

HDMI_R_CK-

C

Q34 change to SB000006A00
20101228

HDMI_R_D2+

R775
10K_0402_5%

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23
C

2

SUYIN_100042MR019S153ZL
CONN@

UMA use 604 ohm
VGA use 499 ohm

Near the connector
6 PCIE_FTX_GRX_N12
6 PCIE_FTX_GRX_P12
6 PCIE_FTX_GRX_N13
6 PCIE_FTX_GRX_P13

2
2

1 0.1U_0402_16V7K HDMI_C_TX2- R784 1
1 0.1U_0402_16V7K HDMI_C_TX2+ R786 1

2
2

604_0402_1%
604_0402_1%

C1168
C1169

2
2

1 0.1U_0402_16V7K HDMI_C_TX1- R788 1
1 0.1U_0402_16V7K HDMI_C_TX1+ R790 1

2
2

604_0402_1%
604_0402_1%

R756 1

HDMI_C_CLK+

2
3

1

2
2

1 0.1U_0402_16V7K HDMI_C_TX0- R792 1
1 0.1U_0402_16V7K HDMI_C_TX0+ R795 1

2
2

604_0402_1%
604_0402_1%

C1172
C1173

2
2

1 0.1U_0402_16V7K HDMI_C_CLK- R797 1
1 0.1U_0402_16V7K HDMI_C_CLK+ R799 1

2
2

604_0402_1%
604_0402_1%

2
G

+HDMI_5V_OUT
B

HDMI_C_TX0-

D

S

HDMI_C_TX0+

R801

3
HDMI_R_CK+
0_0402_5%

1

2
3

1

HDMI_R_D0-

0_0402_5%

2

@ L39
WCM2012F2SF-900T04_0805
4 4
Q35

2

2

R769 1
1

1

6 PCIE_FTX_GRX_N15
6 PCIE_FTX_GRX_P15

C1170
C1171

3

6 PCIE_FTX_GRX_N14
6 PCIE_FTX_GRX_P14

HDMI_R_CK-

0_0402_5%

2

1 1
@ L38
WCM2012F2SF-900T04_0805
4 4
R765

1

From APU

HDMI_C_CLK-

C1166
C1167

2
3
HDMI_R_D0+

2

R779

B

0_0402_5%

SSM3K7002FU_SC70-3
HDMI_C_TX1-

R781 1

HDMI_R_D1-

0_0402_5%

2

100K_0402_5%
2

1 1
@ L40
WCM2012F2SF-900T04_0805
4 4
HDMI_C_TX1+

2
3

1

HDMI_R_D1+
0_0402_5%

R783 1

109

HDMI_R_D1+

HDMI_R_D0+

D13
1 1

HDMI_R_D1+
HDMI_R_D1HDMI_R_D2+

2 2

98

HDMI_R_D1-

HDMI_R_D0-

4 4

77

HDMI_R_D2+

HDMI_R_CK+

HDMI_R_D2-

5 5

66

HDMI_R_D2-

HDMI_R_CK-

HDMI_C_TX2+
HDMI_R_D0+

2 2

98

HDMI_R_D0-

4 4

77

HDMI_R_CK+

5 5

66

HDMI_R_CK-

3 3

8

8

3

3
HDMI_R_D2+
0_0402_5%

D32
HDMI_HPD

6

5

+5VS

A

4

+HDMI_5V_OUT
L15ESDL5V0NA-4 SLP2510P8

2

2

R794
109

3 3

2

1

L15ESDL5V0NA-4 SLP2510P8

I/O4

I/O2

VDD

GND

I/O3

I/O1

HDMI_SDATA

2

1

A

HDMI_SCLK

For ESD request.

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/08/04

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

3

AZC099-04S.R7G_SOT23-6

For ESD request.

5

HDMI_R_D2-

0_0402_5%

2

1 1
@ L41
WCM2012F2SF-900T04_0805
4 4
D11
1 1

3

2

R782
HDMI_C_TX2-

2

3

2

Title

HDMI Connector
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
1

28

of

49

4

2

2

2

1
1

1
C1616

1

1
C1615

0.1U_0402_16V7K

2

1
C1614

D

2

1

C1621

2

1

C1622

2

1

C1623

2

2

S

D

These caps close to Pin 12,27,39,42,47,48
+LAN_IO
+LAN_IO

W=40mils

R560

2

1

2

R553
10K_0402_5%

1

1

2
G

C1625

R658
1

C1626
2

1

+LAN_EVDD10

2

0_0603_5%
1


C1627

1

C1628

2

2

Q91
2N7002_SOT23
U49
22

6 PCIE_DTX_C_FRX_N0

C1630 1

20.1U_0402_16V7K

PCIE_FRX_DTX_N0

23
17
18

6 PCIE_FTX_C_DRX_P0
6 PCIE_FTX_C_DRX_N0

HSOP
HSON

LED3/EEDO
LED1/EESK
LED0

31
37
40

EECS/SCL
EEDI/SDA

30
32

HSIP
HSIN

R5511
R6601

2 10K_0402_5%
2 10K_0402_5%

+LAN_VDD

C

16

14 LAN_CLKREQ#
13,18,32 PLT_RST#

25

PERSTB

13 CLK_PCIE_LAN
13 CLK_PCIE_LAN#

19
20

REFCLK_P
REFCLK_N

+3VS

XTLO

43

XTLI

44

LAN_WAKE#

R661
1

CLKREQB

ISOLATEB

2

28
26

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

2
R662
15K_0402_5%
1

+LAN_IO

2
1 0_0402_5%
+LAN_IO
R647
3.3V : Enable switching regulator
0V
: Disable switching regulator

R568
B

1

2 10K_0402_5%
2 1K_0402_5%

R563 1

14
15
38
33

+LAN_VDDREG

34
35

2 2.49K_0402_1%

46

2
24
49

0_0603_5%
R546
1 @
2

C

W=60mils

LAN_MDIP0
LAN_MDIN0
LAN_MDIP1
LAN_MDIN1
LAN_MDIP2
LAN_MDIN2
LAN_MDIP3
LAN_MDIN3

1
C1631
2

1
C1632
2

12P_0402_50V8J
1

CKXTAL2

DVDD10
DVDD10
DVDD10

13
29
41

C1634

These components close to Pin 36
( Should be place within 200 mils )

+LAN_VDD

LANWAKEB
ISOLATEB

DVDD33
DVDD33

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

AVDD33
AVDD33
AVDD33
AVDD33

27
39
12
42
47
48

+LAN_IO

EVDD10
VDDREG
VDDREG

AVDD10
AVDD10
AVDD10
AVDD10

RSET
GND
PGND

REGOUT

21

+LAN_EVDD10

3
6
9
45
36

LAN_MDIP1

6

I/O4

LAN_MDIN0

3

I/O2

+LAN_VDD
5

+LAN_IO

VDD

2

GND

2

1

0_0402_5%
Y6
25MHZ_12PF_X5H025000FC1H-H
XTLO

2

JLAN1

RJ45_TX3-

8

RJ45_TX3+

7

RJ45_RX1-

6

RJ45_TX2-

5

RJ45_TX2+

4

RJ45_RX1+

3

RJ45_TX0-

2

RJ45_TX0+

1

PR4PR4+
PR2PR3PR3+
PR2+
PR1PR1+
SHLD1

+LAN_SROUT1.05

+LAN_SROUT1.05 LAN_MDIN1
37

4

I/O3

LAN_MDIP0

1

I/O1

XTLI

10P_0402_50V8J

D18

ENSWREG

R550

C1633
2

1

CKXTAL1

1K_0402_5%
R561 1
R562 1

1
2
4
5
7
8
10
11

2

PCIE_FRX_DTX_P0

1

20.1U_0402_16V7K

4.7U_0603_6.3V6K

C1629 1

0.1U_0402_16V7K

6 PCIE_DTX_C_FRX_P0



D

2
LAN_WAKE#

3
S

1

14,32,36 FCH_PCIE_WAKE#

W=20mils

+LAN_VDD

+LAN_VDDREG

0_0603_5%

R1620
10K_0402_5%

1

2

1U_0402_6.3V6K

C1624
0.1U_0603_25V7K

0.1U_0402_16V7K


S

0.1U_0402_16V7K

1

4.7U_0603_6.3V6K

1
1

2

1

C1620

These caps close to Pin 3,6,9,13,29,41,45

Q30
SSM3K7002FU_SC70-3
3

2
EN_WOL#

1

C1619

SSM3K7002FU_SC70-3

R534
1
2 EN_WOL#
220K_0402_5%~N

2
G

EN_WOL
2

36

1

C1618

Q54
2
G

R533
100K_0402_5%

D

C1617

0.1U_0402_16V7K


R1106
470_0603_5%

3

D

2

1
C1613

0.1U_0402_16V7K

2

2

1
C1612

0.1U_0402_16V7K

C1611

0.1U_0402_16V7K

2

G

1

AO3419L_SOT23-3

0.1U_0402_16V7K

1

1

2

+5VALW

1.5A

D

S

C1610
1U_0402_6.3V6K

+LAN_VDD

2

+LAN_IO
Q29
3

0.1U_0402_16V7K


1

0.1U_0402_16V7K


1

1

0.1U_0402_16V7K


2

JUMP_43X118

0.1U_0402_16V7K

@

2

+LAN_IO

0.1U_0402_16V7K


2

+3VALW

3

W=60mils

0.1U_0402_16V7K


J8

W=60mils

0.1U_0402_16V7K


5

SHLD2

9

B

10

AZC099-04S.R7G_SOT23-6
RTL8111E-VL-CGT_QFN48_6X6

SANTA_130452-C

0_0603_5%

GND_LAN

@
GND_LAN

TS1
D38

C1635 1

2

0.01U_0402_16V7K

+V_DAC
LAN_MDIN3
LAN_MDIP3

1
2
3

+V_DAC
LAN_MDIN2
LAN_MDIP2

4
5
6

+V_DAC
LAN_MDIN1
LAN_MDIP1

7
8
9

+V_DAC
LAN_MDIN0
LAN_MDIP0

10
11
12

MCT1
MX1+
MX1-

24
23
22

TCT2
TD2+
TD2-

MCT2
MX2+
MX2-

21
20
19

TCT3
TD3+
TD3-

MCT3
MX3+
MX3-

TCT1
TD1+
TD1-

TCT4
TD4+
TD4-

MCT4
MX4+
MX4-

18
17
16
15
14
13

R549 1
R1529 1
R1530 1
R552 1

RJ45_TX3RJ45_TX3+

2
2
2
2

75_0603_1%
75_0603_1%
75_0603_1%
75_0603_1%

RJ45_TX0+ 1

2

2

RJ45_TX0-

PD10943-T7_SOD323-2

RJ45_TX2RJ45_TX2+

D19
2

RJ45_RX1RJ45_RX1+

LAN_MDIP3

6

C1636
1000P_1206_2KV7K

1

I/O4

I/O2

3

LAN_MDIP2

RJ45_RX1+ 1

5

+LAN_IO

VDD

GND

2

RJ45_TX2+ 1

GND_LAN
RJ45_TX0RJ45_TX0+

LAN_MDIN3

BOTH_GST5009-LF

A

D21

@
1

LSE-200NX3216TRLF_1206-2
2

D22

@
1

LSE-200NX3216TRLF_1206-2
2

D31

@
1

LSE-200NX3216TRLF_1206-2
2

D34

@
1

LSE-200NX3216TRLF_1206-2
2

4

I/O3

I/O1

ESD
4

2

1

1

RJ45_TX3+ 1

1

For ESD request.

Issued Date

ESD
2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

2

RJ45_RX1-

2

RJ45_TX2-

PD10943-T7_SOD323-2

2

2

RJ45_TX3-

PD10943-T7_SOD323-2

SOD323 package
A

Compal Secret Data
2010/06/30

2

PD10943-T7_SOD323-2
2

@
D41

LAN_MDIN2

@@

Security Classification
GND_LAN

1
@
D40

AZC099-04S.R7G_SOT23-6

5

1
D39

Title

Compal Electronics, Inc.
P25-LAN RTL8111E

Size Document Number
Custom QBL60 LA-7552P
Date:

Rev
0.02
Sheet

Tuesday, February 22, 2011
1

29

of

49

A

B

C

D

E

F

G

H

+5VS_PVDD

2

27
36

DMIC_DATA

DMIC_DATA

DMIC_CLK

DMIC_CLK

R1543 1
L121 1

EMI request 12.24
EC_MUTE#

EC_MUTE#

R1545 1

HP_JD

HDA_RST_AUDIO#

+1.5VS

1
1 C1480

SPKOUT_R2

R1536 1

2 0_0603_5%

SPK_R2

2
0.22U_0603_16V7K
@

2
0.22U_0603_16V7K
@
1U_0603_10V6K

2

1
C1484

2
0.22U_0603_16V7K
@

1

HP_OUTL
HP_OUTR

MIC2_L
MIC2_R

HDA_SYNC_AUDIO
2
C1494
@

GPIO0/DMIC_DATA

SYNC

10

HDA_SYNC_AUDIO

BCLK

6

HDA_BITCLK_AUDIO_R 1 R1590

GPIO1/DMIC_CLK
SDATA_OUT
PD#

SDATA_IN

RESET#

EAPD
SPDIFO

PCBEEP

1
R1538
@
2

32
33

MIC1_L
MIC1_R

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO

5

HDA_SDOUT_AUDIO

8

HDA_SDIN_AUDIO1 R1546 2
33_0402_5%

2
0_0402_5%

1

1
C1492
@

2

R1541
R1542

2
2

SPK_L1
SPK_L2
SPK_R1
SPK_R2

0_0402_5%

10U_0805_10V6K

Close to JSPK1

1 R1547

48

0_0402_5%

14

+USB_VCCB

HDA_BITCLK_AUDIO 14
+MIC1_VREFO_R
+MIC1_VREFO_L

1 2.2K_0402_1%
1 2.2K_0402_1%

ACES_87213-1400G

HDA_SDIN0 14

2

EAPD

14
14

MIC2_VREFO
SENSE B
CBP

MIC1_VREFO_R
LDO_CAP

CBN

VREF

MIC1_VREFO_L

JDREF

PVSS2
PVSS1
DVSS2
DVSS1

CPVEE
AVSS1
AVSS2

USB20_N1
USB20_P1

36
MIC_JD

L109
MIC2

20

1
1

29
30
28

+MIC1_VREFO_R

27

AC97_VREF

19

AC_JDREF

34
26
37

1 R1552 2
20K_0402_1%
1
2
C1498
2.2U_0603_16V6K

1
C1499

1

C1500

2

2

1
C1501
2

MIC-2
BLM18PG121SN1D_0603
2 MIC-1
BLM18PG121SN1D_0603
1
1
2

L110
MIC1

SENSE A

37
37
37
37

2

HDA_SDOUT_AUDIO 14

47

SPK_L1
SPK_L2
SPK_R1
SPK_R2

22P_0402_50V8J

HP_OUT_L
HP_OUT_R

43
42
49
7

SPK_R1

10P_0402_50V8J

SPKOUT_R1
SPKOUT_R2

36

3

0.1U_0402_16V7K

38

25

45
44

1
2
35
C1497 2.2U_0603_16V6K
31

2 0_0603_5%

1
C1478

+5VS

AVDD2

AVDD1

39

46
PVDD2

SPK_OUT_R+
SPK_OUT_R-

18

+MIC1_VREFO_L

PVDD1

LINE2_L
LINE2_R

13

R1535 1

@

14
15

11

SPKOUT_R1

C1491
SPKOUT_L1
SPKOUT_L2

4

2

HDA_SDOUT_AUDIO
2

40
41

3

2

2
1
MBK1608800YZF 0603

U50

SPK_OUT_L+
SPK_OUT_L-

MONO_OUT
SENSE_A

2

LINE1_L
LINE1_R

2

1

C1487

23
24

12
1 R1548 2
20K_0402_1%
2 R1549 1
39.2K_0402_1%

9

1
PD#

2 0_0402_5%

DVDD_IO

DVDD

DMIC_CLK_CODEC
2
FBMA-L10-160808-301LMT_2P

14 HDA_RST_AUDIO#

MIC_JD

2

2 0_0402_5% DMIC_DATA_CODEC

SPK_L2

C1495
220P_0402_50V7K

10U_0805_10V6K

27

1

C1486

0.1U_0402_16V7K

MIC2

C1485

2 C1490 4.7U_0603_6.3V6K MIC1_C 21
MIC2_C 22
2 C1493 4.7U_0603_6.3V6K
16
17

2 0_0603_5%

1

10U_0805_10V6K

MIC1_R 1
2
1K_0402_5%
MIC2_R 1
1 R1540 2
1K_0402_5%
1 R1539

2

R1533 1

L108

@

MIC1

C1505

SPKOUT_L2

+5VS_PVDD +VDDA

1

0.1U_0402_16V7K

2

10U_0603_6.3V6M

C1488

1

2

1
2
0.22U_0603_16V7K
@
1U_0603_10V6K

1 C24

@ C1483

+3VS_DVDD

1

2

2

0.1U_0402_16V7K

2

1
C1482

10U_0603_6.3V6M

1

R1537
2
1
0_0603_5%

C1477

SPK_L1

2 0_0603_5%

@ C1474

+3VS_DVDD_R

C1481

+3VS

2

R1532 1

10P_0402_50V8J

R1534
2
1
0_0603_5%

+3VS_DVDD

0.1U_0402_16V7K

1

C1476

1

0.1U_0402_16V7K

C1475

1

0.1U_0402_16V7K

1

10U_0805_10V6K

SPKOUT_L1

R1531
2
1
0_0805_5%

+5VS

2

2

HP_JD
HPR
HPL

C1496
220P_0402_50V7K

14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1
JAU1

3

1

ALC269-GR_QFN48_7X7

4.7K_0402_5%
R1553 @

HP_OUTR 1

L111
1

2

2

L112
HDA_RST_AUDIO#

1

R1554
75_0603_1%
2 HP_R

@
0.1U_0402_16V7K
C1503

2

R1556 1

2 0_0402_5%

R1557 1 @

2 0_0402_5%

R1558 1 @

2 0_0402_5%

R1559 1 @

2 0_0402_5%

HP_OUTL 1 R1555 2 HP_L
75_0603_1%

1

2

HPR
BLM18PG121SN1D_0603
HPL
BLM18PG121SN1D_0603
1
1

C1502
470P_0402_50V7K

2

2

C1504
470P_0402_50V7K

@

4

4

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

E

F

Title

P26-HD CODEC ALC259
Size Document Number
Custom QBL60 LA-7552P
Date:

Tuesday, February 22, 2011
G

Rev
0.03
Sheet

30
H

of

49

5

4

3

2

1

Card Reader RTS5137
(only SD/MMC/MS function)
+3VS

+3VS_CR

D

R1560

2 0_0603_5%

1

30mil

D

@

14
14

+RREF & +VREF need 12mils
1

2

2

12mil

U51

+RREF

1

REFE

2
3

DM
DP

+3VS_CR
4
5
30mil +CARDPWR
+VREG
6
1
10mil
C1512
7
1U_0402_6.3V6K
SDWP_MSCLK
1 R529
2 SDWP_MSCLK_R8
2
0_0402_5% MS_INS#
9
SDD1
10
SDD0
11
MSD3
12

C1511

1
0.1U_0402_16V4Z

GPIO0

3V3_IN
CARD_3V3
V18
NC
SP1
SP2
SP3
SP4
SP5

25

C1510
4.7U_0805_10V4Z

1
100P_0402_50V8J
2
6.2K_0603_1%
USB20_N4
USB20_N4
USB20_P4
USB20_P4

EPAD

2
C1507
R1733 1

17

CLK_IN

24

NC

23

SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6

22
21
20
19
18
16
15
14
13

@
1
R1561
CLK_SD_48M

2
1
10_0402_5% @
@C1509
C1509

2
10P_0402_50V8J

CLK_SD_48M 13

MS_BS
SDD2
SDD3_MSD1
SDCMD
MSD0
SDCLKMSD2 1
R441
SDCD#

EMI
SDCLK_MSD2
2
0_0402_5%

RTS5137-GR_QFN24_4X4

Card Reader Connector

SDCLK_MSD2

C

@
C787
1
2
0.1U_0402_16V4Z

C

+CARDPWR

30mil
SDWP_MSCLK

2

@

1

1

R1562
100K_0402_5%

2

1
C1514
0.1U_0402_16V4Z

C1515
0.1U_0402_16V4Z

2

1

2

@
C788
1
2
0.1U_0402_16V4Z

+CARDPWR
JCR1

C1513
0.1U_0402_16V4Z

Close to connector

Close to U51

EMI

SDCD#
SDWP_MSCLK
SDD1
SDD0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

MS_BS
SDCLK_MSD2
MSD0

MS_INS#
MSD3
SDCMD
SDD3_MSD1
SDD2
B

22
23

SD-CD
SD-WP
SD-D1
SD-D0
MS-GND
SD-GND
MS-BS
SD-CLK
MS-D1
MS-D0
SD-VCC
MS-D2
SD-GND
MS-INS
MS-D3
SD-CMD
MS-SCLK
MS-VCC
SD-D3
MS-GND
SD-D2

B

GND
GND
TAITW_R009-142-HM
CONN@

A

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

P27-RTS5137 Media Card Controller
Size Document Number
Custom
QBL60
Date:

Rev
0.03

LA-7552P

Tuesday, February 22, 2011

Sheet
1

31

of

49

A

B

C

D

E

W=60mils

Mini-Express Card for WLAN/WiMAX(Half)

+3VS_WLAN

+3VALW

+1.5VS

14 MINI1_CLKREQ#

2 0_0402_5%

BT_ONR1594 1
@
MINI1_CLKREQ#

2 0_0402_5%

WLAN_WAKE#

C124

EMI

2
10P_0402_50V8J
@

PCI_RST#_R
CLK_PCI_DB

R530
1CLK_PCI_DB

2

6 PCIE_DTX_C_FRX_N1
6 PCIE_DTX_C_FRX_P1

0_0402_5%
@

6 PCIE_FTX_C_DRX_N1
6 PCIE_FTX_C_DRX_P1
+3VS_WLAN

15

BT_ON

53

For EC to detect
debug card insert.

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1

2

2

2

2

1
C1517
0.1U_0402_16V4Z

C1518
0.1U_0402_16V4Z

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

R663
100K_0402_5%
1

1

R1567 1
R1568 1

FCH_SMCLK0_R
FCH_SMDAT0_R

@

2
2

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
0_0402_5%
0_0402_5%

R1569 1
R1570 1

2 @ 0_0402_5%
2 @ 0_0402_5%

R1571 1
R1572 1

2 @ 0_0402_5%
2 @ 0_0402_5%

36,38

0_0402_5%
2
1 R1577 WLAN_LED#
2
1 R1575 BT_LED#
0_0402_5%

S

2
0_0402_5%

Q32
SSM3K7002FU_SC70-3

2
G

SUSP#

R115

1

C1663
0.1U_0603_25V7K

2

WL_OFF# 15
WL_OFF#_EC 36
PLT_RST# 13,18,29
+3VALW
+3VS

Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.

FCH_SCLK0 11,12,14
FCH_SDATA0 11,12,14

USB20_N3 14
USB20_P3 14
WLAN_R_LED#
BT_R_LED#

D

LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

WLAN_LED# 36
BT_LED# 36

R1573
R1574
R1576
R1578
R1579
R1580

1
1
1
1
1
1

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#

LPC_FRAME# 13,36
LPC_AD3 13,36
LPC_AD2 13,36
LPC_AD1 13,36
LPC_AD0 13,36
CLK_PCI_DB

13

54

GND2

BELLW_80003-1021

2

36 EC_TX_P80_DATA
36 EC_RX_P80_CLK

100_0402_1%
R1581
EC_TX_P80_DATA 1
2 EC_TX_P80_DATA_R
EC_RX_P80_CLK 1
2 EC_RX_P80_CLK_R
@ R1582
100_0402_1%
BT_ON R1566 1
2 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1

@
C1516
0.1U_0402_16V4Z

1

R1565 1

13 CLK_PCIE_MINI1#
13 CLK_PCIE_MINI1

1

1

JMINI1

2

1

FCH_PCIE_WAKE#

1
R1564
0_1206_5%

3

14,29,36

1 0_1206_5%

2

@

1

R1563 2

@

AO3413_SOT23-3

2

+5VALW

Mini-Express Card(WLAN/WiMAX)

1 0_1206_5%

2

1

C1664
1U_0402_6.3V6K

+1.5VS

+3VS_WLAN

R1596

1

G

+3VALW
+3VS

D

S

Q31
3

1

R1583
100K_0402_5%

2

2

2

+5VALW

R669
10K_0402_5%

Add to prevent leakage issue.
1

LED

LED1

White
35,36 PWR_LED#

1

2

2
300_0402_5%

1
R1584

+5VALW

19-217/T1D-DP1Q2QY/3T 0603 WHITE
D26

Orange
36 CHARGE_LED1#

LED2

BATT_LOW_LED#

3

36 CHARGE_LED0#

BATT_CHG_LED#

White

PWR_LED#

@

2
1

1

O
W

2

2
300_0402_5%

1
R1585

+3VALW

4

2
300_0402_5%

1
R1586

+3VALW

3
YSDA0502C 3P C/A SOT-23
D36

HT-297DQ/GQ 0603 AMB/YG

CHARGE_LED1#

2

CHARGE_LED0#

3

@
1

D24
WLAN_R_LED#

3

1

@

Green
2

WLAN_D_LED#

RB751V_SOD323
@
D25
BT_R_LED#

1

LED3
1

2

2
300_0402_5%

1
R1588

+3VS

YSDA0502C 3P C/A SOT-23
D37
@

19-21SYGC/S530-E3/TR8 0603 Y/G

WLAN_D_LED#

2

SATA_LED#

3

1

2

RB751V_SOD323

36 RF_LED#

R1589 1

3

YSDA0502C 3P C/A SOT-23
D35

2 0_0402_5%
36,37 NUM_LED#

NUM_LED#

2

CAPS_LED#

3

@
1

LED4

Green
15 SATA_LED#

1

2

2
300_0402_5%

1
R1591

YSDA0502C 3P C/A SOT-23

+3VS

19-21SYGC/S530-E3/TR8 0603 Y/G

ESD

LED6

Green
36 CAPS_LED#

1

2

2
300_0402_5%

1
R1593

+3VS

4

4

19-21SYGC/S530-E3/TR8 0603 Y/G

Compal Secret Data

Security Classification

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P28-Mini PCIE/LED
Size

B

C

D

Document Number

Rev
0.03

QBL60 LA-7552P
Date:

A

Compal Electronics, Inc.

Sheet

Tuesday, February 22, 2011
E

32

of

49

A

B

C

D

E

F

G

H

SATA HDD Conn.
JHDD1
SATA_STX_DRX_P0
SATA_STX_DRX_N0

15 SATA_STX_DRX_P0
15 SATA_STX_DRX_N0
15 SATA_DTX_C_SRX_N0
15 SATA_DTX_C_SRX_P0

1

C656 1
C658 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_STX_C_DRX_P0
SATA_STX_C_DRX_N0

SATA_DTX_C_SRX_N0 C1519 1
SATA_DTX_C_SRX_P0 C1520 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

+3VS

1

2

+5VS

R1595 1

10U_0603_6.3V6M
C660

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C661

2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

C22

+5VS_HDD

2 0_0805_5%

1

C662

2

1

C663

2

1U_0402_6.3V4Z

1
2
3
4
5
6
7

1

2

GND
A+
AGND
BB+
GND

1

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12 GND1
V12 GND2
V12

23
24

SUYIN_127043FR022S21MZR

1000P_0402_50V7K

2

2

SATA ODD FFC Conn.
JODD1

1
1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_STX_C_DRX_P1
SATA_STX_C_DRX_N1

C1521 1
C1522 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_SRX_N1
SATA_DTX_SRX_P1

C648
C649

15 SATA_STX_DRX_P1
15 SATA_STX_DRX_N1
15 SATA_DTX_C_SRX_N1
15 SATA_DTX_C_SRX_P1

80mils

+5VS

1
R1598

+3VS

+5VS_ODD
2
0_0805_5%
@
1
2
R670
10K_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13

GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND
GND

15
14

OCTEK_SLS-13DC1G_RV

3

3

4

4

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

Compal Electronics, Inc.

Compal Secret Data

Security Classification

E

F

Title

P29-HDD & ODD CONN
Size
B

Document Number

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011
G

Sheet

33
H

of

49

A

1

B

C

D

E

1

+5VALW

C707

2

10.1U_0402_16V4Z

USB_ON#

1
2
3
4

GND
IN
IN
EN#

USB20_P10 1

8
7
6
5

OUT
OUT
OUT
OC#

USB20_N10 4

Low Active

1
4

2
3

2

USB20_P10_C

3

USB20_N10_C

+USB_VCCA

1

S COM FI_ KINGCORE WCM-2012HS-900T

USB_OC0# 14

C708
470P_0402_50V7K

L58

1

AP2301MPG-13 MSOP 8P

Left USB Conn.

L55

+USB_VCCA

U54

C710
@ 1000P_0402_50V7K

2

USB20_P0

1

USB20_N0

4

1

2

2

4

3

3

USB20_P0_C
USB20_N0_C

2

W=80mils
14
14

2

JUSB1
USB20_N10
USB20_P10

USB20_N10
1 USB20_P10

2 R666
2 R664
@
@

C709
47U_0805_6.3V

1 0_0402_5% USB20_N10_C
1 0_0402_5% USB20_P10_C

+USB_VCCA

2

C714

2

10.1U_0402_16V4Z
36
USB_ON#

USB_ON#

1
2
3
4

OUT
OUT
OUT
OC#

8
7
6
5

1
C711
470P_0402_50V7K

USB_OC1# 14

1

AP2301MPG-13 MSOP 8P

Low Active

GND1
GND2
GND3
GND4

W=80mils

JUSB2

+USB_VCCB

GND
IN
IN
EN#

5
6
7
8

Left USB Conn.

EMI request
U55

VCC
DD+
GND

SUYIN_020173MR004S50DZL
CONN@

S COM FI_ KINGCORE WCM-2012HS-900T
+5VALW

1
2
3
4

2

14
14

1

2

2 R665
2 R667
@
@

USB20_N0
USB20_P0

C712
47U_0805_6.3V

1 0_0402_5%
1 0_0402_5%

USB20_N0_C
USB20_P0_C

C713
@ 1000P_0402_50V7K

1
2
3
4

VCC
DD+
GND

5
6
7
8

GND1
GND2
GND3
GND4

2

SUYIN_020173MR004S50DZL
CONN@

2

D20
@

2 R673
L60

USB20_P10_C

I/O4

I/O2

3

5

VDD

GND

2

I/O3

I/O1

1

USB20_P0_C

1 0_0402_5%
+5VALW

M3@

14 USB30_MTX_C_DRX_P0

USB30_MTX_C_DRX_P0

1

1

2

2

USB30_MTX_C_DRX_P0_C

14 USB30_MTX_C_DRX_N0

USB30_MTX_C_DRX_N0

4

4

3

3

USB30_MTX_C_DRX_N0_C

USB20_N10_C
3

6

4

USB20_N0_C
3

AZC099-04S.R7G_SOT23-6

WCM-2012HS-900T

2 R672

For ESD request.

1 0_0402_5%

@

2 R675
14 USB30_MRX_DTX_P0

14 USB30_MRX_DTX_N0

USB30_MRX_DTX_P0
USB30_MRX_DTX_N0

@
1 0_0402_5%

L62

M3@

1

1

2

2

USB30_MRX_DTX_P0_C

4

4

3

3

USB30_MRX_DTX_N0_C

USB30_MTX_C_DRX_P0_C

D5
1 1

109

USB30_MTX_C_DRX_P0_C

USB30_MTX_C_DRX_N0_C

2 2

98

USB30_MTX_C_DRX_N0_C

USB30_MRX_DTX_P0_C

4 4

77

USB30_MRX_DTX_P0_C

USB30_MRX_DTX_N0_C

5 5

66

USB30_MRX_DTX_N0_C

WCM-2012HS-900T

2 R674

3 3
8

1 0_0402_5%

@

YSCLAMP0524P_SLP2510P8-10-9

4

4

M3@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Deciphered Date

2012/06/30

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

D

P32-USB/BT/USBsub
Size Document Number
Custom

Rev
0.03

QBL60 LA-7552P

Date:

Tuesday, February 22, 2011

Sheet
E

34

of

49

5

4

ON/OFF switch

3

2

Power Button

Fan Control Circuit
+3VS

2
100K_0402_5%

2

1

D12

4

8
7
6
5

FAN_SPEED

2

ON/OFF#

36

3

51_ON#

40

1

C702
1000P_0402_50V7K~N

C701

1

C700

1

U53

1

R527

ON/OFFBTN#

2

R668
10K_0402_5%

D

SW 3
SMT1-05-A_4P
1
3

+5VS

2

+3VALW

TOP Side

1

1

GND
GND
GND
GND

EN
VIN
VOUT
VSET

1
2
3
4

D

ACES_85205-0300N

2.2U_0603_106K
1000P_0402_50V7K~N

2

+5VS_FAN

1

APL5607KI-TRG_SO8

2

2

36

FAN_SPEED

FAN_SPEED

C703
10U_0603_6.3V6M

5
4

GND
GND

3
2
1

3
2
1
JFAN1

DAN202UT106_SC70-3

6
5

Change to SC600000B00
C773

36

2

CONN@

FAN_SET

EC_ON

EC_ON

R528

4

Q28
2
G

D

S
SSM3K7002FU_SC70-3

1

10K_0402_5%

6
5

2

36

2

SW 4
SMT1-05-A_4P
1
3

1

Bottom Side

3

1000P_0402_50V7K
1

C

C

EC BIOS ROM
+3VALW

2
0_0603_5%

C1370 1

2 0.1U_0402_16V4Z

+SPI_VCC
PW R_LED# 32,36
+5VALW
LID_SW # 36
+3VALW

LID_SW #

@ C1374

2
R1055

U42
EC_SPICS#/FSEL#
R1050 1
2 4.7K_0402_5%
R1052 1
2 4.7K_0402_5%

36 EC_SPICS#/FSEL#
+3VALW

1
EC_SPI_W P# 3
EC_SPI_HOLD#7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

EC_SPICLK_R
EC_SO_SPI_SI_R
EC_SI_SPI_SO_R

@

R1051 1
R1053 1
R1054 1

1
0_0402_5%
33P_0402_50V8K
2 0_0402_5%
EC_SPICLK 36
2 0_0402_5%
EC_SO_SPI_SI 36
2 0_0402_5%
EC_SI_SPI_SO 36

MX25L1606EM2I-12G SOP 8P
SA000041N00

3

ACES_85201-06051

1
R1049

ON/OFFBTN#

2

JBTN1
1 1
2 2
3 3
4 4
5 5
6 6
GND 7
GND 8

1

PJSOT24CH_SOT23-3
D27
B

B

@

A

A

Compal Secret Data

Security Classification
2010/06/30

Issued Date

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
P31-KB /SW/TP/Lid

Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
1

35

of

49

5

4

3

2

1

+3VALW

C1347

2
2
0.1U_0402_16V4Z

C1348

2
2
0.1U_0402_16V4Z

L65
1
2+EC_VCCA
BLM18AG601SN1D_2P
1

2

C1349
1000P_0402_50V7K
1
1

C1350

1000P_0402_50V7K

13,16 LPC_CLK0_EC

2
R1011
2
C1353

+3VALW

13

1
47K_0402_5%
1
0.1U_0402_16V4Z

A_RST#

14

KSO[0..15]

EC_SCI#

LPC_CLK0_EC
A_RST#

12
13
37
EC_SCI#
20
1
2
38
@ R1015
10K_0402_5%
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

KSO[0..15] 37

KSI[0..7]

KSI[0..7]

C

37

@
+3VALW
+3VS

+3VALW

1
R1020
1
R1021
1
R1022
1
R1023

@
@
@

2
2.2K_0402_5%
EC_SMB_CK2
2
2.2K_0402_5%
EC_SMB_DA2
2
2.2K_0402_5%
2
2.2K_0402_5%

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

PWM Output
AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

68
70
71
72

FAN_SET
IREF
CHGVADJ

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
USB_ON#
W LAN_LED#
BT_LED#
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

EN_W OL
VLDT_EN
LID_SW #

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

100
101
102
103
104
105
106
107
108

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_PME#
FCH_PW RGD
BKOFF#

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

PE_GPIO1
ENBKL
EAPD
EC_THERM#
SUSP#
PBTN_OUT#
1 @
2 TL_BKOFF#
R29 0_0402_5%

V18R

124

PS2 Interface

14
14
14

SLP_S3#
SLP_S5#
EC_SMI#

1
R1036

RTC_CLK

1

13,16

R1037
100K_0402_5%

NUM_LED#

OSC

4

OSC

NC

@
X2

1

@
C1362
15P_0402_50V8J

2

EC_CRY1
2 EC_CRY2
0_0402_5%

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

GPIO
SM Bus

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

C1358
22P_0402_50V8J

1

32.768KHZ_12.5PF_Q13MC14610002

C1360
2

100P_0402_50V8J
ECAGND
1
BATT_TEMP 40

ADP_I
39
AD_BID0 37
+3VS
FCH_PW RGD 1
R1035

FAN_SET 35
IREF
39
CHGVADJ 39

GPI

XCLK1
XCLK0

VGATE
47
EN_W OL 29
VLDT_EN 38,46
LID_SW # 35

1
R1018
1
R1019

C

EC_SPICLK 35
EC_SPICLK_L 1
R1033

2
0_0402_5%

EC_SI_SPI_SO 35
EC_SO_SPI_SI 35

@
C1357 33P_0402_50V8K

Reserve for EMI, close to EC
35

Delay EC_PWROK 50ms
for VGA criterial
FSTCHG 39
CHARGE_LED0# 32
CAPS_LED# 32
CHARGE_LED1# 32
PW R_LED# 32,35
SYSON
38,43
VR_ON
47
ACIN
39

CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
PW R_LED#
SYSON
VR_ON
ACIN

ACIN

C1363
2

100P_0402_50V8J
1

ENBKL
1
100K_0402_5%

2
R1034

B

@

EC_RSMRST# 14
EC_LID_OUT# 14
EC_ON
35
FCH_PW RGD 14
BKOFF#
27
W L_OFF#_EC 32
RF_LED# 32
VGA_ON 25

Delay SUSP# 10ms

1

2

PE_GPIO1 13,25
ENBKL
10
EAPD
30
EC_THERM# 8,13,47
SUSP#
32,38
PBTN_OUT# 14
TL_BKOFF# 26,27

R1032
10K_0402_5%
@

C1359
14,29,32 FCH_PCIE_W AKE#

4.7U_0603_6.3V6K

1 @
2
R2 0_0402_5%

EC_PME#

20mil

L66
ECAGND 1
2
FBM-11-160808-601-T_0603

A

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/08/04

Deciphered Date

2010/08/04

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

2
4.7K_0402_5%
2
4.7K_0402_5%

TP_DATA

EC_SPICS#/FSEL#

KB930QF A1 LQFP 128P

Issued Date

5

2
10K_0402_5%
+5VS

TP_CLK

EC_MUTE# 30
USB_ON# 34
W LAN_LED# 32
BT_LED# 32
TP_CLK 37
TP_DATA 37

EC_SPICLK_L

@

+3VALW

3

2

NC

1

2

2

EC_CRY2

2

@
C1361
15P_0402_50V8J
1

EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#

32,37 NUM_LED#

EC_CRY1

A

EC_INVT_PW M
FAN_SPEED

32 EC_TX_P80_DATA
32 EC_RX_P80_CLK
35
ON/OFF#

EC_SCI#

2
10K_0402_5%

SLP_S3#
SLP_S5#
EC_SMI#

27 EC_INVT_PW M
35 FAN_SPEED

+3VS

1
R1623

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

GND
GND
GND
GND
GND

BATT
APU/VGA

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

ADP_I
AD_BID0

SPI Device Interface
SPI Flash ROM

39

BATT_TEMP

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

11
24
35
94
113

B

1
R1027
1
R1028
1
R1029
1
R1030
1
R37
1
R1619
@
1
R1617
1
R1616

40
40
6,19,26
6,19,26

ACOFF

63
64
65
66
75
76

+3VALW
EC_SMB_CK1
2
2.2K_0402_5%
EC_SMB_DA1
2
2.2K_0402_5%
KSO1
2
47K_0402_5%
KSO2
2
47K_0402_5%
LID_SW #
2
10K_0402_5%
USB_ON#
2
10K_0402_5%
EC_SMI#
2
10K_0402_5%
EC_MUTE#
2
10K_0402_5%

ACOFF

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

DA Output

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

21
23
26
27

AGND

1
33_0402_5%

1
2
3
4
5
7
8
10

69

@ C1352
22P_0402_50V8J
@
2
1
2
R1014

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

D

AVCC

VCC
VCC
VCC
VCC
VCC
VCC

U31

0.1U_0402_16V4Z

67

9
22
33
96
111
125

D

14
EC_GA20
14 EC_KBRST#
13
SERIRQ
13,32 LPC_FRAME#
13,32
LPC_AD3
13,32
LPC_AD2
13,32
LPC_AD1
13,32
LPC_AD0

C1351

2

1

0.1U_0402_16V4Z
1
2

2

0.1U_0402_16V4Z
1 C1346
1
C1345

ECAGND

1

3

2

Title

EC ENE KB930
Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
1

36

of

49

INT_KBD Conn.
P9 FS1 PWR/GND

36
36

ID

ACES_88514-02401-071

26
25
2 @ 100P_0402_50V8J

KSO6

C1547 1

2 @ 100P_0402_50V8J

KSI2

C1548 1

2 @ 100P_0402_50V8J

KSO8

C1549 1

2 @ 100P_0402_50V8J

KSO5

C1550 1

2 @ 100P_0402_50V8J

KSO13

C1551 1

2 @ 100P_0402_50V8J

KSI3

C1552 1

2 @ 100P_0402_50V8J

KSO12

C1553 1

2 @ 100P_0402_50V8J

KSO14

C1554 1

2 @ 100P_0402_50V8J

KSO11

C1555 1

2 @ 100P_0402_50V8J

KSI7

C1556 1

2 @ 100P_0402_50V8J

KSO10

C1557 1

2 @ 100P_0402_50V8J

KSI6

C1558 1

2 @ 100P_0402_50V8J

KSO3

C1559 1

2 @ 100P_0402_50V8J

KSI5

C1560 1

2 @ 100P_0402_50V8J

KSO4

C1561 1

2 @ 100P_0402_50V8J

KSI4

C1562 1

2 @ 100P_0402_50V8J

KSI0

C1563 1

2 @ 100P_0402_50V8J

KSO9

C1564 1

2 @ 100P_0402_50V8J

KSO0

C1565 1

2 @ 100P_0402_50V8J

KSI1

C1566 1

2 @ 100P_0402_50V8J

KSO15
KSO0
KSO7
KSO5
KSO2
KSO4
KSO8
KSO6
KSO11
KSO10
KSO12
KSI3
KSI0
KSI2
KSI4
KSI6
KSI7
KSI1
KSI5
KSO13
KSO1
KSO3
KSO9
KSO14

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CONN PIN define need double check

GND2
GND1

0

R01 SR

100K

0

0V

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JKB1
CONN@

1

R02 ER

100K

8.2K

0.25V

2

R03 PR

100K

18K

0.5V

3

R10 MP

100K

33K

0.82V

+CPU_CORE
+VGA_CORE

1

1

C435

+

2

1

C436

+

+

+

2

VGA@

1

C474

2

VGA@

2
+3VALW

1
+

2

1
+

2

1
+

2

1
+

2

@

Ra
36

AD_BID0

AD_BID0

330U_D2_2V_Y

2 @ 100P_0402_50V8J

C1545 1

C1014
330U_D2_2V_Y

C1544 1

KSO7

Vab

C995
330U_D2_2V_Y

KSO1

2 @ 100P_0402_50V8J

Rb

C999
330U_D2_2V_Y

2 @ 100P_0402_50V8J

C1546 1

Ra

C994
330U_D2_2V_Y

C1543 1

KSO15

BRD ID

C993

KSO2

330U_D2_2V_Y

KSO[0..15]

330U_D2_2V_Y

KSI[0..7]

KSO[0..15]

330U_D2_2V_Y

KSI[0..7]

R1024

1

2 100K_0402_5%

R1026

1

2 0_0402_5%

Rb

VGA@

+5VS

To TP/B Conn.
ZZZ
C1567
0.1U_0402_16V4Z
JTP1

@

@

H9
H_3P8
@

H10
H_4P3
@

1

@

H8
H_3P8

1

@

H6
H_3P0

1

7
8

H5
H_3P8

1

GND1
GND2

H4
H_3P0

1

H2
H_3P8

PCB

1

@
@
C1568
C1569
100P_0402_50V8J
100P_0402_50V8J
2

1
2
3
4
5
6

@

ACES_85201-06051
H12
H_3P0

H13
H_3P0

H14
H_4P3

H15
H_4P3

H16
H_3P0

H18
H_3P8

H22
H_7P0
@

@

1

@

1

1

1

@

@

H23
H_3P3
@

@

H1
H_2P7X5P0N

YSDA0502C 3P C/A SOT-23

@

H3
H_10P0X6P0N

H7
H_3P0

@

H17
H_2P7N
@

1

@

1

H21
H_3P0
@

1

2

3

3

2

D10

@

1

H20
H_3P0
@

@

For ESD.
Close to JSPK1

D9

YSDA0502C 3P C/A SOT-23

@

1

H19
H_3P0

ACES_85205-04001
CONN@

For ESD.
Close to JTP1

@

1

YSDA0502C 3P C/A SOT-23

YSDA0502C 3P C/A SOT-23

1
2
3
4
G5
G6

1

1
2
3
4
5
6

1

SPK_R1
SPK_R2
SPK_L1
SPK_L2

SPK_R1
SPK_R2
SPK_L1
SPK_L2

1

30
30
30
30

1

@

1

D28

@

1

D17

1

2

3

2

3

H11
H_4P3
JSPK1

1

2

SW/L
SW/R

1

1

1

1

1
2
3
4
5
6

TP_CLK
TP_DATA

1

@

GND_LAN
FD1

1

FD3

FD4

4

3

DTSGZML-63N-Q-T-R_5P

1

3

2

1

4

SW/R

1

1

DTSGZML-63N-Q-T-R_5P

FD2

SW6

2

1

SW5
SW/L

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

FIDUCIAL_C40M80

5

TP_CLK
TP_DATA

5

36
36

Close to LED1

1
C1644

Close to LED2

1
C1645

Close to LED3

29 +LAN_SROUT1.05

+LAN_SROUT1.05

+LAN_VDD

L120

W=60mils
1

1
C1646

Close to LED4

W=60mils
2

1
C1647

4.7UH_1008HC-472EJFS-A_5%_1008

Close to LED5

1
C1648

These components close to Pin 36
( Should be place within 200 mils )

2
0.1U_0603_25V7K
2
0.1U_0603_25V7K
2
0.1U_0603_25V7K
2
0.1U_0603_25V7K
2
0.1U_0603_25V7K

For ESD.
Cap to LED gap is 1.2mm.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/11/25

Deciphered Date

2011/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

P33-Other IO/USB (right)
Size Document Number
Custom

Rev
0.02

QBL50 LA-7551P

Date: Tuesday, February 22, 2011

Sheet

37

of

49

2
1
S

2
SUSP

32,36

SUSP#

1

SUSP

2
G

2
G
S

2

S

2

SUSP

1

SSM3K7002FU_SC70-3

D

Q58

3

D

Q53
2
G

1

28,45

SSM3K7002FU_SC70-3

R1108
100K_0402_5%

1
D

1

+5VALW

C1451
0.1U_0603_25V7K

2
2

SSM3K7002FU_SC70-3

1

2
2

1

R1104
100K_0402_5%

D

3

1
1
3

2
3

Q52
2
G

SYSON

R1109
10K_0402_5%

SSM3K7002FU_SC70-3

1

R1102
10K_0402_5%


SSM3K7002FU_SC70-3

36,43

R1110
470_0603_5%
1 1

4

C1452

2

1

C1455

1U_0402_6.3V4Z

10U_0603_6.3V6M

1

S

3

VLDT_EN#

1
3

U40
SI4800BDY-T1-GE3_SO8
1
2
3

C1454

C1453

Q59
SUSP

S

36,46 VLDT_EN
Q57
2
G

SYSON#

+3VS

3VS_GATE
1
200K_0402_5%

2
R1112

+VSB

10U_0603_6.3V6M

10U_0603_6.3V6M

2

2

D

1

VLDT_EN#

S

+3VALW

2

D

1.1VS_GATE

2
47K_0402_5%

Q64 D
2
G

S
SSM3K7002FU_SC70-3

C1450
0.1U_0603_25V7K

+3VALW TO +3VS (3.3A)

1

1
R1105

Q51
2
G

R1098
100K_0402_5%

2

+VSB

SSM3K7002FU_SC70-3

1

1 1

2

1
1
3

3

2

8
7
6
5

4

1

2
1
2

4
1

Q56
2
G

2

S

SSM3K7002FU_SC70-3

D

VLDT_EN#
R1101
470_0603_5%

S
1

SUSP

2

2

1

C1449

SUSP

1

C1447

Q55
2
G

1

1
2
3

1U_0402_6.3V4Z

5VS_GATE
2
100K_0402_5%

1
R1103

R1100
1K_0402_5%

R1097
100K_0402_5%

8
7
6
5

10U_0603_6.3V6M

D

1

+VSB

+1.1VS

C1448

R1099
470_0603_5%

10U_0603_6.3V6M

2

C1444

1U_0603_10V6K

1

C1446

2

+1.1VALW

+5VALW

U39
AO4430L_SO8
10U_0805_10V4Z

2

1
C1445

C1443

10U_0805_10V4Z

10U_0805_10V4Z

1

+1.1VALW TO +1.1VS (1.1A)

+5VS

U38
SI4800BDY-T1-GE3_SO8
8
1
7
2
6
3
5

E

+5VALW

3

+5VALW

D

1

+5VALW TO +5VS (5A)

C

SSM3K7002FU_SC70-3

B

2

A

VGA Power

2

+1.5V to +1.5VSG (1.5A)

C1456
0.1U_0603_25V7K

+1.5V

+1.5VSG

1 1

D

4

2

SSM3K7002FU_SC70-3

3

2

+5VALW

C1462
VGA@
0.1U_0603_25V7K

2

1

1

3

3

S
S
SSM3K7002FU_SC70-3

3

1.5VSG_GATE
1 VGA@ 2
R1118 100K_0402_5%

Q74 D
1.5_VDDC_PWREN# 2
1
2
VGA@ R1120 47K_0402_5%
G
VGA@
S
SSM3K7002FU_SC70-3
1
VGA@
C1464
0.1U_0402_16V7K
2

SUSP

2 1.5_VDDC_PWREN#
G
VGA@
SSM3K7002FU_SC70-3

R1119
100K_0402_5%
VGA_PWR_ON#

1

25,42,45 VGA_PWR_ON

+VGA_CORE

+1.8VSG

R1123
100K_0402_5%

+1.2VS

D

S

2
G

Q68
2N7002_SOT23

2
1

2

Q62
VLDT_EN#

R1131
100K_0402_5%

@ PJ14
1

2

2

+3VSG
1.5_VDDC_PWREN#

JUMP_43X118

25,48 1.5_VDD_PWREN
1

1

1

+3VS

1


S
SSM3K7002FU_SC70-3

D

3

2
G

2

2
A

S

2
G

Q77
2N7002_SOT23
4

R1134
10K_0402_5%
2

1
1

SUSP


SSM3K7002FU_SC70-3

3

3

S

D

Q72
2
G


SSM3K7002FU_SC70-3

+5VALW

Change to Jump
201012062000

R1137
470_0603_5%

1
1

SYSON#

1

3

3

3
2

2
G
S

D

Q71

VGA_PWR_ON#

+3VS to +3VSG (3.3A)

+0.75VS

R1136
470_0603_5%

1
1

D

2
G

VGA@
S
SSM3K7002FU_SC70-3

+2.5VS

R1135
470_0603_5%

D

Q65

1.5_VDDC_PWREN#

VGA@
S
SSM3K7002FU_SC70-3

+1.5V
4

1
2
G

VGA@
S
SSM3K7002FU_SC70-3

D

Q66

VGA_PWR_ON#

VGA@

Q70
2
G

S

2010/08/04

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

SUSP


SSM3K7002FU_SC70-3

2010/08/04

Deciphered Date

Title

DC Interface

3

2
G

R1128
470_0603_5%

3

D

Q67

1

1

1

D

R1127
470_0603_5%

1

R1126
470_0603_5%
VGA@

1

R1125
470_0603_5%
VGA@

2

2

2

2

+1.0VSG

3

1

+VSB

Q73

1

2
1

2
1

VGA@
R1114
470_0603_5%

3

3

2
G

Q61
2
G

2

1
VGA@
C1458
1U_0402_6.3V4Z
2

S

1

2
1
1

C1463
0.22U_0603_16V4Z

D

D

2

1

VGA@ C1457

2
1
47K_0402_5%

2

2

1

10U_0603_6.3V6M

Q60

R1117
470_0603_5%

1

VGA@
C1460

R1122

1

C1461

10U_0603_6.3V6M

R1116
100K_0402_5%

SUSP#

+1.5VS

AP2301GN-HF_SOT23-3
Q63
3
1

10U_0603_6.3V6M
VGA@ C1459

+1.5V

10U_0603_6.3V6M

+1.5V TO +1.5VS (1.5A)

1
2
3

2

U41
VGA@
AO4430L_SO8
8
7
6
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

C

D

Size
B
Date:

Document Number

Rev
0.03

QBL60 LA-7552P
Tuesday, February 22, 2011

Sheet
E

38

of

49

B

C

PL1
HCB2012KF-121T50_0805
1
2

2

X7R type

1

PC5
0.1U_0603_16V7K

PR1
22K_0402_1%

1

1

PC4
100P_0402_50V8J

PU1
1

VCC TMSNS1

8

2

GND RHYST1

7

3

OT1 TMSNS2

6

OT2 RHYST2

5

1

OTP_N_001
OTP_N_002

2

1
PR2

22.1K_0402_1%

1

2

1
2

1

VL

PC3
1000P_0402_50V7K

@ACES_88323-0471

PC2
100P_0402_50V8J

4

2

3

4

1

2

3

PC1
1000P_0402_50V7K

2

2

1

1

1

PH1 under CPU botten side :
CPU thermal protection at 92 +-3 degree C
Recovery at 80 +-3 degree C

VIN

PL2
HCB2012KF-121T50_0805
1
2

ADPIN

PJPDC1

D

2

A

OTP_N_003

VMB

PJP2

3

2

@SUYIN_200275MR009G186ZL

2

1

VS_ON 42

0_0402_5%

1

BATT+

PC6
1000P_0402_50V7K

2

1
2
PD1

2

PR27
1K_0402_1%

2

PC7
0.01U_0402_25V7K

2

1

1

GND
GND

EC_SMCA
EC_SMDA
TS_A

PH1
100K_0402_1%_NCP15W F104F03RC

PR4
PL4
HCB2012KF-121T50_0805
1
2

1
2
3
4
5
6
7
8
9

@PJSOT24CW_SOT323-3

10
11

G718TM1U_SOT23-8
2

PL3
HCB2012KF-121T50_0805
1
2

1
2
3
4
5
6
7
8
9

4

PD2

VL

PR13
100K_0402_1%
BATT_TEMP 36

1K_0402_1%
42,45

1

SPOK

2

1

3

PR16
0_0402_5%
2VSB_N_002 2
G

S

1

VSB_N_001

3

2

VIN

D

PQ1
TP0610K-T1-GE3_SOT23-3

PQ2
SSM3K7002FU_SC70-3

PC10
0.1U_0402_16V7K

2

1

1

1VSB_N_003

+3VALW

3

2

2

1

100K_0402_5%
PR30

1

PR12
22K_0402_1%
1
2

PC9
0.1U_0603_25V7K

EC_SMB_DA1 36
PR29

+VSBP

1

2

EC_SMB_CK1 36

2

@PJSOT24CW _SOT323-3

2

PC8
0.22U_0603_25V7K

1
PR31
100_0402_1%

2
1
PR10
100K_0402_1%

PR28
100_0402_1%
1
2

3

B+

1
3

2

2

PD3
RLS4148_LL34-2
VS_N_001
1

1

1

+VSB

(120mA,40mils ,Via NO.= 1)

2

PR18
68_1206_5%

1

VS

PC12
0.1U_0603_25V7K

2

2

PC11
0.22U_0603_25V7K

2

2

PR21
100K_0402_1%

1

1

1

3

2

@JUMP_43X39

PQ3
PR17
TP0610K-T1-GE3_SOT23-368_1206_5%
N1

2

1

1

1

PD4
RLS4148_LL34-2

2

2

BATT+

PJ2
+VSBP

4

4

35

1

2
PR22
22K_0402_1%

51_ON#

VS_N_002

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

DCIN / BATT CONN / OTP
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B
Date:

Tuesday, February 22, 2011
D

Sheet

40

of

44

B

C

PC115
1
2

5

ICOMP

CSIN

20

6

VCOMP

CSIP

19

ICM

PHASE

18

LX_CHG

8

VREF

UGATE

17

DH_CHG

CHG_CHLIM

9

CHLIM

BOOT

16

6251aclim

10

ACLIM

VDDP

15

11

VADJ

LGATE

14

GND

PGND

13

CHG_VCOMP

2

Rtop
PR128
20K_0402_1%

36 CHGVADJ

12

DL_CHG

1

26251VDD

1

1

3

4

PD106
RB751V-40TE17_SOD323-2

6251VDDP

1CHG_SNUB2

6251VREF 1
2
226K_0402_1%

1

PQ110

2

2 ACPRN
G
PQ109
@SSM3K7002FU_SC70-3
2

PL101
10UH +-20% MSCDRI-104A-100M-E
CHG
1
2

PC121
0.1U_0603_25V7K
BST_CHGA 2
1

PR127

S

2

PR122
2.2_0603_1%

PR126
0_0603_5%
BST_CHG 1

PC114
@2200P_0402_25V7K

PQ108
AON7408L_DFN8-5

4

5
6251VREF

CHG_N_006

D
5

2
1

CSOP

1

1
2
PC120
0.1U_0402_16V7K

4

PC106
2200P_0402_25V7K

1
2

PC105
0.1U_0402_25V6
2
1

1CHG_N_0081

21

100_0402_1%
2 CHG_ICM 7

PR111
14.3K_0402_1%

1
2

CSOP

DCIN

CELLS

2

CHG_N_001

1

PR102
0.02_1206_1%
4

2

3

BATT+
PC101
10U_0805_25V6K
2
1

PR123

PC110
1000P_0402_50V7K
2
1

2

4

CSON

AON7406L_DFN8-5

PR129
4.7_0603_5%
PC123
4.7U_0805_6.3V6K

2

3

22

3
2
1

PR104
140K_0402_1%

CSON

PR118
20_0603_5%
CHG_CSON 1
2
PC113
0.047U_0603_16V7K
CHG_CSOP 1
2
PR119
20_0603_5%
CHG_CSIN
2
1
PC118
PR120
0.1U_0603_25V7K
20_0603_5%
CHG_CSIP
1
2

2

PQ111
DTC115EUA_SC70-3

2

EN

PQ106
DTC115EUA_SC70-3

ACPRN

1

ACOFF

3

2

ACOFF

2

36

10K_0402_1%
2

1

PR103
150K_0402_1%

PC122
0.01U_0402_25V7K
2
1

2

IREF

1

36

ADP_I

23

2

36

ACSET ACPRN

6800P_0402_25V7K
CHG_ICOMP
2

1

PC120 must close EC pin.

2

PR115
100K_0402_1%
1
2

PR125
@4.7_1206_5%

0.01U_0402_25V7K

1

PACIN

PR124
22K_0402_5%
1
2

24

PC112
1U_0603_25V6K
1
2

1

4

5

PR121
1

DCIN

VIN

ISL6251AHAZ-T QSOP 24P

PC124
@680P_0402_50V7K

PC117
1
2

VDD

CHG_VADJ

CHG_N_009

1

6251_EN
PR130
0_0402_5%
1
2

PR110
47K_0402_1%
1
2
PR112
10K_0402_1%

3
2
1

PC116
1

SSM6N7002FU_US6

2

10_1206_5%

1

PR105
10K_0402_1%
1
2
2

PQ107B

2S: Float
3S: GND

PU101

8
7
6
5

CHG_N_005

2

2

2
3CHG_N_002

1

SSM6N7002FU_US6

PR113

1

1

PR117

2

6

3

PR116
150K_0402_1%

PQ107A
2

PD101
CHG_VIN 1

PC109
2.2U_0603_6.3V6K
2
1
1

FSTCHG

100K_0402_1%

36

RB751V-40TE17_SOD323-2

ACSETIN

PR114
10K_0402_1%
2
1

ACSETIN

PC111
@10U_0805_25V6K
2
1

1
2

1
2

PQ105
DTC115EUA_SC70-3

1

CHG_N_001

2

PR108
191K_0402_1%
1
2

6251VDD

CHG_N_003

PQ103
AO4407AL 1P SO8
1
2
3

CSIN

3

CSIP

PR107
200K_0402_1%

PC108
0.1U_0603_25V7K

2

2

1

PR109
47K_0402_1%

1CHG_N_010

1

PQ104
DTA144EUA_SC70-3

2

VIN

3

1

8
7
6
5

B+
CHG_B+

PL102
1.2UH_1231AS-H-1R2N=P3_2.9A_30%
2
1
PC104
10U_0805_25V6K
2
1

1
2
3

4

8
7
6
5

PR101
0.02_1206_1%
1
4

PC107
5600P_0402_25V7K
1
2

VIN

P3

PQ102
AO4409L_SO8
1
2
3

4

P2

PQ101
AO4435L_SO8

@10U_0805_25V6K

PC102
10U_0805_25V6K
2
1

B+

3

(B+ 6A,240mils ,Via NO.= 12)

D

PC103
4.7U_0805_25V6-K
2
1

A

PR106
22K_0402_1%

3

1

3

1

1

6251VDD

PR131
47K_0402_1%

PR132
10K_0402_1%

ACIN

36

PACIN

C

ACPRN

PQ112

2
B

1

1

2

Iada=0~4.737A(90W);CP=4.03A;where Racdet=0.020ohm,where Rtop=12.4K
90W for Dis:Rtop:SD00000AJ80
Iada=0~3.421A(65W);CP=2.91A;where Racdet=0.020ohm,where Rtop=226K
65W for UMA:Rtop:SD034226380
Astro2010_01_15 need confirm P/N

2

CP= 85%*Iada;

PR133
10K_0402_1%
1
2

PR136
20K_0402_1%
2

3

E
MMBT3904W H NPN SOT323-3

4

CP mode
Vaclim=VREF*(Rbot//Rinternal/(Rtop//Rinternal+Rbot//Rinternal))
when 90W Vaclim=2.39*(20K//152K/(20K//152K+12.4K//152K))=1.44966V
when 65W Vaclim=2.39*(20K//152K/(20K//152K+226K//152K))=0.38914V
Iinput=(1/Racdet)*((0.05*Vaclim/VREF+0.05))
when 90W,Iinput=(1/0.02)*(0.05*1.44966/2.39+0.05)=4.02A
when 65W,Iinput=(1/0.02)*(0.05*0.38914/2.39+0.05)=2.92A

CC=0.25A~3A

4

CHGVADJ=(Vcell-4)/0.10627

IREF=1.016*Icharge

Vcell

IREF=0.254V~3.048V

4V

VCHLIM need over 95mV

4.2V

CHGVADJ
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0V
1.882V

2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

CHARGER
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B
Date:

Tuesday, February 22, 2011
D

Sheet

41

of

44

A

B

C

D

E

1

2VREF_6182

1

LX_5V

19

LG_5V

3
2
1

2
SPOK

18

5

1
2

PC306
10U_0805_25V6K

PL305
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
1
2
1

UG_5V

20

40,45

4
SNUB_5V

PR314
499K_0402_1%
2

21

2

RT8205LZQW(2) WQFN 24P PWM

AO4468L_SO8

1
PC318
4.7U_0805_10V6K

1
+ PC305
150U_B2_6.3VM_R35M

1

2

1

PC320
1U_0603_10V6K

+5VALWP

2

2

1

PR315
95.3K_0402_1%

PQ306
AO4406AL_SO8

VL

3
2
1

EN0

PR313
@4.7_1206_5%

LGATE1

22

4
PR309
PC315
2.2_0402_5%
0.1U_0402_10V7K
BST_5V 1
2 BST1_5V 1
2

PC317
@680P_0402_50V7K

LGATE2

23

PQ305
AON7408L_DFN8-5

5
6
7
8

PHASE1

24

NC

PHASE2

VREG5

UGATE1

PC312
2200P_0402_50V7K
2
1

ENTRIP1
2

3

1
ENTRIP1

FB1

REF

TONSEL

4

ENTRIP2
5

6

FB2

BOOT1

UGATE2

17

1

BOOT2

13

B++

B++

PR307
165K_0402_1%
2

PGOOD

EN

4

PR306
20K_0402_1%
2

VO1

VREG3

16

8
7
6
5

12

2

2

LG_3V
PQ304

PR305
30.9K_0402_1%
2

1

1

+

11

2

1

LX_3V

1
2
3

+3VALWP

PR312
PC316
@4.7_1206_5%
@680P_0402_50V7K
2
1 SNUB_3V
2
1

PL303
4.7UH_FMJ-0630T-4R7 HF_5.5A_20%
2
1

VO2

15

1
2
3

PC314
8
0.1U_0402_10V7K
PR308
BST1_3V 1
1
2
2 BST_3V 9
2.2_0402_5%
UG_3V 10

VIN

7

2

PC303
150U_B2_6.3VM_R35M

P PAD

GND

25
2

4

1

PU301

PC313
10U_0805_6.3V6M

FB_5V 1

SKIPSEL

PQ303
AON7408L_DFN8-5

2

ENTRIP2

PR303
133K_0402_1%
1

5

1
2

PC304
4.7U_0805_25V6-K

PC310
2200P_0402_50V7K
2
1

PC309
0.1U_0402_25V6
2
1

1
2

PC322
@680P_0402_50V7K

+3VLP

2

FB_3V

14

PL301
HCB2012KF-121T50_0805
1

1

PR302
20K_0402_1%
1
2

B++

B+

2

PC311
0.1U_0402_25V6
2
1

PR301
13.7K_0402_1%
1

1

2

PC308
1U_0603_16V6K

2

B++
3

PC319
0.1U_0603_25V7K

3

G

N_3_5V_001

2

5

3

D
PQ307A
SSM6N7002FU_US6

D

4

6

ENTRIP2

ENTRIP1

2VREF_6182

S

PQ307B
SSM6N7002FU_US6

G

+3VLP

+CHGRTC
PJP302

1

S

2

PAD-OPEN 2x2m

PJP306

1

+5VALWP

1

VL

2

+5VALW

(5A,200mils ,Via NO.= 10)

+5VALW

(5A,200mils ,Via NO.= 10)

PAD-OPEN 4x4m
PJP305
2

VL
PJP301

PQ308
DTC115EUA_SC70-3

1

+3VALWP

2

1
PAD-OPEN 2x2m

+3VALW

(4A,120mils ,Via NO.= 8)

PAD-OPEN 4x4m

4

EC:+3VL, reserve PR319, install PR318, PR320 100K
EC:+3VALW, reserve PR318, install PR319, PR320 42.2K

Compal Secret Data

Security Classification
2007/08/02

Issued Date

2008/08/02

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2

PAD-OPEN 4x4m
PJP303

3

PC321
2.2U_0603_10V6K

4

2

PR317
100K_0402_5%

1

2

1

2

PR319
100K_0402_1%

2

1

2
1
PR320
42.2K_0402_1%

VS

1

40 VS_ON

+5VALWP

1

B

C

D

Title

Compal Electronics, Inc.
3.3VALWP/5VALWP

Size Document Number
Custom
Date:

Rev
0.1

LAXXXX

Tuesday, February 22, 2011

Sheet
E

42

of

44

A

B

C

D

1

1

1
2

 VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V

PC402
22U_0805_6.3VAM

2

1

1
PR402
10K_0402_1%

PC401
22U_0805_6.3VAM

SY8033BDBC_DFN10_3X3

PR401
20K_0402_1%

PC404
68P_0402_50V8J
2
1

1.8VSP_FB

2

6

1

NC

TP

2

PR405
@47K_0402_5%

7

11

EN_1.8VSP

1

2

2

1

PR404 0_0402_5%

FB

+1.8VSGP

2

2

EN

3

1

5

LX

PR403
4.7_1206_5%

SVIN

PC405
@0.1U_0402_10V7K

25,38,46 VGA_PWR_ON

1

2

PL401
1UH_VLS252012T-1R0N1R7_2.4A_30%
1
2

1.8VSP_LX

2

PVIN

8

2

PC406
680P_0402_50V7K
SNUB_1.8VSP
2
1

9

LX

NC

PVIN

1

PC403
22U_0805_6.3VAM

10

2

1

1.8VSP_VIN

4

PU401

HCB1608KF-121T30_0603
1
2

PG

PL402
+5VALW

PJP401
1

+1.8VSGP

2

+1.8VSG

(2A, 80mils, Via NO.= 4)

PAD-OPEN 3x3m
3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

+1.8VSGP
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B
Date:

Tuesday, February 22, 2011
D

Sheet

43

of

44

5

4

3

2

1

D

D

0_0402_5%

B+

PR502
2.15K_0402_1%

3
2
1
11
10

LGATE

9

TRIP_1.5V 1

PR508

+5VALW
LG_1.5V

2

1

1
2

1
2

2200P_0402_50V7K
PC506

1
2

2

1

PC504
@4.7U_0805_25V6-K

2

+1.5VP
C

15.4K_0402_1%

1

PGOOD

CS
VDDP

PL501
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

+5VALW
PC510
4.7U_0805_10V6K

PQ502
FDS6690AS-G_SO8

4

2

3
2
1

2

RT8209MGQW _W QFN14_3P5X3P5

PR509
@4.7_1206_5%

6

PHASE

LX_1.5V

2

FB

UG_1.5V

12

1SNUB_1.5V

NC

14

1

VDD

5

1

4

13

PQ501
AON7408L_DFN8-5

1
+ PC501
220U_6.3VM_R15

2

PC511
@680P_0402_50V7K

2.21K_0402_1%

PC509
4.7U_0603_10V6K

2

FB_1.5V

2

4

5
6
7
8

PR501

2

1

1

PGND

1

+1.5VP

8

V5FILT_1.5V

2

PR507
100_0402_1%

7

+5VALW 1

VOUT

GND

+1.5VP

UGATE

2

TON

3

1

PC508
0.1U_0402_10V7K

BOOT

2

C

EN/DEM

PU501
PR506
255K_0402_1%
1
2TON_1.5V

15

PR504
2.2_0402_5%
BST_1.5V 1
2BST1_1.5V

+5VALW

PC503
10U_0805_25V6K

5

2

1

PC505
@0.1U_0402_10V7K

PL502
HCB1608KF-121T30_0603
2
1

PC512
@680P_0402_50V7K

EN_1.5V

1

PC507
0.1U_0402_25V6

1.5V_B+
PR503

2

36,38 SYSON

PJP502

B

1

B

2
@PAD-OPEN 4x4m
PJP501

+1.5VP

1

2

+1.5V

(8A,320mils ,Via NO.= 16)

@PAD-OPEN 4x4m

A

A

Compal Secret Data

Security Classification
2007/05/29

Issued Date

Deciphered Date

2008/05/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
+1.5VP

Size

Document Number

Rev
0.1

LAXXXX
Date:

Tuesday, February 22, 2011

Sheet
1

44

of

44

5

4

3

2

D

1

D

1.1V_B+
PR703

SPOK

0_0402_5%

B+

PL702
HCB1608KF-121T30_0603
2
1

EN_1.1V

1
PC704
@0.1U_0402_10V7K

3
2
1
VDDP

10

LGATE

9

PR708
+5VALW
LG_1.1V

15K_0402_1%
2
+5VALW
PQ702
PC709
4.7U_0805_10V6K

AO4468L_SO8
4

2

3
2
1

2

RT8209MGQW _W QFN14_3P5X3P5

1
2

PC711
@680P_0402_50V7K

PC706
0.1U_0402_25V6

1
2

PC705
2200P_0402_50V7K
2
1

PC702
10U_0805_25V6K

2

TRIP_1.1V 1

+1.1VALW

1
+

PR706
@100K_0402_5%

1

11

1

CS

PL701
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

2

PHASE

LX_1.1V

PR709
@4.7_1206_5%

UG_1.1V

12

1SNUB_1.1V

14

NC

BOOT

13

PQ701
AON7408L_DFN8-5

5
6
7
8

PGOOD

UGATE

1

FB

6

4

PC701
220U_D2_2VY_R15M

C

2

PC710
@680P_0402_50V7K

PR702
10K_0402_1%

1

5
FB_1.1V

2
2

PC707
0.1U_0402_10V7K

2

2

VDD

PGND

PR701

4.64K_0402_1%

VOUT

4

7

+1.1VALW

1

PC708
4.7U_0603_6.3V6M

1
1

PR707
100_0402_1%
C

V5FILT_1.1V

2

2

+5VALW 1

TON

3

8

+1.1VALW

2

EN/DEM

PR705
255K_0402_1%
1
2TON_1.1V

GND

PU701

15

PR704
2.2_0402_5%
BST_1.1V 1
2 BST1_1.1V 1

+5VALW

1

5

2

1

40,42

2

B

B

A

A

Compal Secret Data

Security Classification
2009/12/01

Issued Date

Deciphered Date

2010/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR+1.1VALWP

Size
Document Number
Custom

Rev
0.1

LAXXXX

Date:

Tuesday, February 22, 2011

Sheet
1

45

of

44

5

4

3

2

1

+1.5V

VIN

NC

8

GND

NC

7

VREF VCNTL

6

VOUT

NC

5

TP

9

+3VALW

PR601
1K_0402_1%

D

2

4

1

3

2

PC601
4.7U_0805_6.3V6K

2

D

2
1

1

PU601
1

PC603
1U_0603_10V6K

APL5336KAI-TRL_SOP8P8

2
G
S

1

0_0402_5%

+0.75VSP
1

10.75VS_N_002

PR602
1K_0402_1%
2

2

3

28,38 SUSP

D

2

1

PQ602
SSM3K7002FU_SC70-3
PR604

2
1
PC604
0.1U_0402_16V7K

1

VREF_G2992

PC605
10U_0805_6.3V6M

2

PC606
@0.1U_0402_10V7K

PJP601

C

2

(2A,80mils ,Via NO.= 4)

+0.75VS

PU603
APL5508-25DC-TRL_SOT89-3
2

+3VS

IN

OUT

3

+2.5VSP
1

PC607
1U_0402_6.3V6K

2

1

2

1

GND

1

PAD-OPEN 3x3m

PR605
@150_1206_5%
2

1

+0.75VSP

PC608
4.7U_0805_6.3V6K

C

+5VALW

2
2

1

1

1

B

2

2

PR610
1.82K_0402_1%

PR611
7.32K_0402_1%

2

+2.5VS

PC615
22U_0805_6.3V6M

2

2

PC613
0.1U_0402_16V7K

PD601
1

FB

2
PAD-OPEN 3x3m

+1.0VSP
1

EN
POK

3
4

PC614
180P_0402_50V8J

8
7

VOUT
VOUT
GND

1

VCNTL
VIN
VIN

1

1

2

1
VGA_PWR_ON

PR609
15K_0402_1%
1
2

+2.5VSP

APL5930KAI-TRG_SO8

6
5
9

1

25,38,43

PJP602
PU602

2

PC611
4.7U_0805_6.3V6K

B

PC612
1U_0603_10V6K

+1.5V

@1SS355_SOD323-2

PJP603
1

+1.0VSP

2

+1.0VSG

(2.5A,100mils ,Via NO.= 5)

PAD-OPEN 3x3m

A

A

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
PWR 0.75VSP/1.0VSP/2.5VSP

Size

Document Number

Rev
0.1

LAXXXX
Date:

Tuesday, February 22, 2011

Sheet
1

46

of

44

A

B

C

D

1

1

1.2V_B+

3
2
1
UG_1.2V

PHASE

12

LX_1.2V
TRIP_1.2V 1 PR808

11
10

LGATE

9

2

+5VALW
LG_1.2V

1
2

1

PC811
@680P_0402_50V7K

+1.2VS

PL801
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
15K_0402_1%

+5VALW

1

PR809
@4.7_1206_5%

PC809
4.7U_0805_10V6K

PQ802
IRF8707TRPBF_SO8
4

RT8209MGQW _W QFN14_3P5X3P5

2

PC810
@680P_0402_50V7K

2

3
2
1

+

PC801

CS
VDDP

PQ801
AON7408L_DFN8-5

220U_D2_2VY_R15M

BOOT

NC

7

PR802
5.36K_0402_1%

13

2

1

PGOOD

4

5
6
7
8

6

14

1

FB

1

3.24K_0402_1%

5

2

1

FB_1.2V

2

VDD

UGATE

2

1

VOUT

4

1

PC807
0.1U_0402_10V7K

2

PC808
4.7U_0603_6.3V6M

+1.2VS
1

PR807
100_0402_1%

PR801

PGND

V5FILT_1.2V

2

2

+5VALW 1

TON

3

8

+1.2VS
+5VALW

2

EN/DEM

PR805
255K_0402_1%
1
2TON_1.2V

GND

PU801

15

PR804
2.2_0402_5%
BST_1.2V 1
2BST1_1.2V

PC806
0.1U_0402_25V6

2

2

5

2

1

PC804
@0.1U_0402_10V7K

PC802
10U_0805_25V6K
2
1

0_0402_5%

B+

PL802
HCB1608KF-121T30_0603
2
1

EN_1.2V

1

1SNUB_1.2V 2

2

VLDT_EN

2200P_0402_50V7K
PC805
2
1

PR803
36,38

3

3

4

4

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/01/23

Deciphered Date

2010/01/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

+1.2VSP
Size

Document Number

Rev
0.1

NCL61 LA-6321P M/B
Date:

Tuesday, February 22, 2011
D

Sheet

47

of

44

5

4

3

2

1

PL204
HCB2012KF-121T50_0805
1
2

PROG1_CPU 1

5

1

1

PLACE NEAR Phase1 choke

PC243
2200P_0402_50V7K
2
1

PC242
0.01U_0402_25V7K
2
1

PC224
10U_0805_25V6K
2
1

PC223
10U_0805_25V6K
2
1
PC222
10U_0805_25V6K
2
1

3
2
1

PL201
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4

PHASE1
PC260
0.1U_0603_50V7K
1BOOT1_1 2
1

PQ202

VSUMLGATE1

4

PC262
0.1U_0603_50V7K

PC264
1000P_0402_50V7K

1

PH201
PR247
10K_0402_5%_ERTJ0ER103J 2.2_0603_5%
BOOT1 2

3
2
1

2

PC263
@330P_0402_50V7K

4
TPCA8065-H_PPAK56-8-5

1

1
2

8 APU_VDD_RUN_FB_L
PR252
10_0402_5%
2
1

5

1
PR244
976_0402_1%
2
1

PQ201
UGATE1

ISEN1

2 PR245 1
10K_0402_1%

VSUM+

2 PR250 1
3.65K_0805_1%

PR249
4.7_1206_5%

2

2

PC227
100U_25V_M

VSUMG-_1

VSUMG+_1

49

24
VIN_CPU

1

22

2

PC250
0.22U_0603_25V7K

VSUM+
PR240
4.99_0402_1%

PC261
@330P_0402_50V7K

8 APU_VDD_SEN

B

CPU_B+

SNUB_CPU1

VSUM-

VSUM-_2

If the layout of each phase to CPU
is symmetric, the two res. can be
removed.
They are used for phase current
balance adjustment.

1

PR248
10_0402_5%
2
1

+CPU_CORE

1 PR222 2 ISEN1
10K_0402_1%

PC246
680P_0402_50V7K

5

2.26K_0402_1%

3

PR231
1_0402_1%
VSUM- 2
1

PR2351
CPU_B+
0_0603_5%
1
+5VS
PR237
1_0603_5%

1PH201_CPU 2

PR242
1

PC230
@100U_25V_M

1

1

2

2

VSUM+ 2 PR230 1
3.65K_0805_1%

2

TP

VIN

VDD

4

2 PR220 1
10K_0402_1%

PR228
4.7_1206_5%

PR251
1_0402_1%
2
1

VSUM-

3

1 PR246 2 ISEN2
10K_0402_1%

VSUM-_1

PC265
680P_0402_50V7K

A

2

A

2
VSUM+_1

25

LGATE2

ISEN2
PQ204

PC253
2200P_0402_50V7K
2
1

BOOT1

PC244
0.1U_0603_50V7K
1BOOT2_12
1

VSUM+_2

UGATE1

26

PR226
2.2_0603_5%
BOOT2 2

TPCA8059-H_PPAK56-8-5

+CPU_CORE

1

27

2

143K_0402_1%

2

2

PHASE1

ISEN2

PC257
0.22U_0402_10V6K
2
1

470P_0402_50V7K

PR241
1

2

1000P_0402_50V7K
PC256
0.22U_0402_10V6K
2
1

PC255
1COMP_CPU_12

3
2
1

LGATE1

28

2

324_0402_1%

ISEN1

2

LGATE_NB

29

PC259
2
1

2

68P_0402_50V8J

PC252
1FB_CPU_1
2
1

2

PC258
2
1

PR239

2
0_0402_5%

PC254
0.01U_0402_25V7K
2
1

PWM3

PR224

1

30

3
2
1

6267_VCCP1

PR234
6.65K_0402_1%

0.22U_0402_16V7K

PC251
2
1

PC249

FB_CPU
PR238
@10_0402_5%
2
1

23

33P_0402_50V8J
2

1U_0603_10V6K
1 VDD_CPU

PC248
1

ISUMN_CPU

2

1

COMP_CPU

2

Rfset(Kohm)=(Period(uS))-0.29)*2.65

PC247
1000P_0402_50V7K

ISEN3_FB2_CPU

1
PR236
8.06K_0402_1%

PROG1

2

21

20

19

18

PH202 470K_0402_5%_TSM0B474J4702RE
VW_CPU

B

ISUMP

ISUMN

RTN

VSEN

ISEN1

ISEN2

ISEN3/FB2

1

17

PLACE NEAR Phase1 L-MOS

NTC

16

2

12

FB

PR233 27.4K_0402_1%
NTC_CPU
1

15

2

COMP

3.83K_0402_1%
1PH202_CPU

VW

2

BOOT1

14

PR232

UG1

PROC_HOT

1

31

PL202
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4

PHASE2

PC221
10U_0805_25V6K
2
1

PH1

LGATE2

TPCA8065-H_PPAK56-8-5

2

ENABLE

PHASE2

32

4

SNUB_CPU2

LG1

PGOOD

11

CPU_B+

1

10

VGATE

8,13,36 EC_THERM#

PR214
1_0402_1%
2
1

TPCA8059-H_PPAK56-8-5

9

VR_ON

VSUMG-

5
PWM3

SVC

13

36

36

PR213
3.65K_0805_1%
2
1

3
2
1

PWROK

8

33

1U_0603_10V6K

LG2
VCCP

ISL6267HRZ-T_QFN48_6X6

UGATE2

0_0402_5%

PH2

BOOT2

34

6267_VCCP1 2

VW_NB

35

UGATE2
PR219
0_0603_5%

PC245
2
1

7

SNUB_NB 2

1
2

38

39

37
LG1_NB

PH1_NB

UG1_NB

PROG2 1

44

41

NTC_NB

ISUMN_NB

45

46

RTN_NB

VSEN_NB

48

UG2

36

2

APU_SVC

BOOT2

COMP_NB

SVD

VSUMG+

C

PGOOD_NB

6

+CPU_CORE_NB

PQ203

PWM2_NB

FB_NB

5

2

3

+5VS

PR218
2

4

PR205
4.7_1206_5%

PC237
680P_0402_50V7K

PR243
2
1
12.1K_0402_1%

2

8

VW_NB
PR223 0_0402_5%
2
1 SDA
PR227 0_0402_5%
2
1 ALERT#
PR229 0_0402_5%
2
1 SCLK

APU_SVD

13 APU_PWRGD_L

PR225
@100K_0402_5%

3

4

PR215
PC240
2.2_0603_5%
0.1U_0603_50V7K
2
1BOOST1_NB1 2
1

0.01U_0402_16V7K

1

8

2

COMP_NB

NTC_NB

ISUMN_NB

1
PR221
100K_0402_5%

FB2_NB

ISUMP_NB

FB_NB
+3VS

ISEN1_NB

1

ISEN2_NB

PU201

47

1

Rfset(Kohm)=(Period(uS))-0.29)*2.65
C

43

PC241
1000P_0402_50V7K

1

PR216
8.06K_0402_1%

42

2

2

+5VS

2
PR217
BOOT1_NB 6.65K_0402_1%

1

PC239
1000P_0402_50V7K

PR210
324_0402_1%

40

2

1FB_NB_12

2

PROG2

1

PC238
100P_0402_50V8J

PL203
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
1
4

2
TPCA8059-H_PPAK56-8-5

2

PQ206
VSUMG-

PH204
470K_0402_5%_TSM0B474J4702RE
PC235
1
2
0.1U_0603_50V7K
PR211
27.4K_0402_1%
NTC_NB_1
1
2
1
2
PR212
3.83K_0402_1%

BOOT1_NB

2
1
PR206
845_0402_1%

2

+

D

PHASE_NB

10K_0402_5%_ERTJ0ER103J

1
@ PR209
@PR209
@10_0402_5%

2

1

4

PH203

PR208
2.26K_0402_1%
2
1

+

TPCA8065-H_PPAK56-8-5

PLACE NEAR NB L-MOS
PC236
PR207
470P_0402_50V7K
143K_0402_1%
2
1COMP_NB_1
2
1

PC229
2200P_0402_50V7K
2
1

5
UGATE_NB

5

1

PC266
@330P_0402_50V7K

B+

1

PQ205

3
2
1

1

PR201

2

11K_0402_1%
PR203
2.61K_0402_1%
1PH203_NB 2
1

PR204
10_0402_5%
2
1

2

PC232
@330P_0402_50V7K

1

8 APU_VDDNB_SEN
+CPU_CORE_NB

PC234
2
1

8 APU_VDDNB_RUN_FB_L

0.047U_0402_16V7K

1

2

2

D

PC233
2
1

PC231
1000P_0402_50V7K

0.1U_0402_10V7K

VSUMG+
PR202
10_0402_5%
2
1

PL205
HCB2012KF-121T50_0805
1
2

PC228
0.01U_0402_25V7K
2
1

PC226
10U_0805_25V6K
2
1

PLACE NEAR NB choke

PC225
10U_0805_25V6K
2
1

CPU_B+

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/11/11

Deciphered Date

2011/11/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

PWR_+CPU_CORE/+CPU_CORE_NB
Size

Document Number

Rev
0.1

PEQAE LA-7291P M/B
Date:

Tuesday, February 22, 2011
1

Sheet

48

of

1

A

B

PL902
HCB2012KF-121T50_0805
1
2

V5IN

7

DRVL

6

RF

TP

1
2
0_0603_5%

5

1

V5IN_VGA

+5VALW

DL_VGA

11

RT8237CZQW (2) W DFN

PQ902
PC919
2.2U_0603_6.3V6K

PQ903

4

4

3
2
1

PR910
@4.7_1206_5%

1

PC918

+

0.1U_0402_10V7K

2

2

PC920
@680P_0402_50V7K

2

PR911
470K_0402_1%

3
2
1

TPCA8059-H_PPAK56-8-5

2

1

+VGA_CORE

PC901
330U_D2_2V_Y

VFB

PR909

PL901
0.36UH_PDME104T-R36MS0R825_37A_20%
1
2

2

LX_VGA

1

8

2

SW

1SNUB_VGA

EN

1
2BST1_VGA
2.2_0603_5%
0.1U_0603_25V7K

@TPCA8065-H_PPAK56-8-5

DH_VGA

3
2
1

BST_VGA

9

1

RF_VGA

5

10

DRVH

TPCA8059-H_PPAK56-8-5

4

VBST

TRIP

4

5

FB_VGA

PGOOD

2

2

0_0402_5%

1

25,38 1.5_VDD_PW REN

2

PC917
@.1U_0402_16V7K

1 PR908

PR9072TRIP_VGA 2
1
73.2K_0402_1%
EN_VGA 3

PC916
1
2

2

1

13,25 VGA_PW RGD

PR906

5

1

4
PU901

PQ906

3
2
1

PQ901

PR905
10K_0402_1%

TPCA8065-H_PPAK56-8-5

5

1
2

2

1

PC913
@4.7U_0805_25V6-K
2
1

1
2

PC915
2200P_0402_50V7K

2

1

PC914
0.1U_0402_25V6

PC923
@680P_0402_50V7K

+3VS

10U_0805_25V6K
PC911
2
1

1

D

VGA_B+

10U_0805_25V6K
PC912
2
1

B+

C

PR912
+VGA_CORE1

GPU VID0

Whistler Pro

X

L

1.0V

X

H

0.9V

H

L

H

H

6.19K_0402_1%

S

1

PQ905

SSM3K7002FU_SC70-3

2

PR916
@10K_0402_5%

PR914
10K_0402_1%
2

PR917
5.1K_0402_1%
2

19

1

GPU_VID0_1 1

GPU_VID0

2

2
G

PC922
.1U_0402_16V7K

2

1

D

PR918
@10K_0402_5%
3

1

FB0_VGA 1

2
1

GPU_VID1

+3VSG

3

1
2

2

GCORE_SEN 21

1

PC921
@.1U_0402_16V7K

S

1

1

1
2GPU_VID1_1
G

PR913
@10K_0402_1%

1

100_0402_1%

PR902
6.98K_0402_1%

2

GPU VID1

PR915
@5.1K_0402_1%
19

3

@SSM3K7002FU_SC70-3
PQ904

Rtrip = 73.2K, OCP = 34.42A

PR903

+3VSG

D

3

Rrf = 470K, FSW = 290KHz

2

PR904
@10K_0402_1%
FB1_VGA1
2

2.94K_0402_1%
1
2

PR901

2

4

4

Compal Secret Data

Security Classification
Issued Date

2007/05/29

Deciphered Date

200810/11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

B

C

Title

Compal Electronics, Inc.
VGA_CORE

Size

Document Number

Rev
0.1

LAXXXX
Date:

Tuesday, February 22, 2011
D

Sheet

49

of

44

5

4

Version change list (P.I.R. List)

Item

3

2

Power section

Reason for change

1

Page 1 of 1

PG#

Modify List

Date

Phase

1
2
D

D

3

4

5
6
7

C

C

B

B

A

A

Compal Secret Data

Security Classification

Issued Date

2008/09/15

2010/12/31

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

4

3

2

Title

Compal Electronics, Inc.
Changed-List History

Size

Document Number

Rev
1.0

LA-4902P
Date:

Sheet

Tuesday, February 22, 2011
1

50

of

47



---

Source Exif Data:

File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.4
Linearized                      : No
Page Count                      : 49
Producer                        : GPL Ghostscript 8.15
Create Date                     : 2011:02:24 10:14:58
Modify Date                     : 2011:02:24 10:14:58
Title                           : la-7551pr01-0217a (Restored)
Creator                         : PScript5.dll Version 5.2.2
Author                          : ShouYi_Ho

EXIF Metadata provided by EXIF.tools