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ASSOCIATE
Te chni ca 1 Fe fe re nce Mi nua 1
Revision 3.0
for
System versions 3.0

Direct Comments Concerning this manual to:
DATA TECHNOLOGY INDUSTRIES, SAN LEANDRO, CALIFORNIA

(415) 638-1206

July, 1982

Data Technology/GNAT Computers Inc.

This Revi sion a pplie s to:
ASSOCIATE Version 3.0
ASSOCIATE PLUS
1000 CPU Board Revision G and H
1005 CRT Board through Revision G
PROM Monitor Version 5.07
CRT PROM Ve rsion 1.7 through 1. A
Character PROM Version SF and 60
Ke yboa rd PROM Ve rsi on 3, 4
The major change for Revision 3.0 is the name change to the ASSOCIATE.
The ASSOCJ;ATE is built by GNAT Computers Inc. and sold as the ASSOCIATE
through Data Technology Industries. Systems having F revision boards
should re fe r to rna nual revision 1.4 or 1.5.
Version 3.0 of the ASSOCIATE uses the H revision of the 1000 CPU board.
The main changes on this board are in the area of the data separator which

now uses a rede signed analog device to improve the reading of the double
tracking disk drives on the ASSOCIATE PLUS.
Copyright (c) 1980, 1981, 1982 by GNAT Computers Inc and IBta Technology
Industrie s. All rights re se rved. No part of this pubUca tion or the
software which it de scribes may be reproduced, transmi tted, transcribed,
or translated into any language or computer language, in any form or by
any means, me chanical, e Ie ctranic, magne tic, optical, or othe rwise wi thout
the written consent of GNAT Computers Inc.
Considerable time and expense has been expended in development of the
software described herein. It has been made available at a reasonable
price. Accordingly, we are seriously concerned about any unauthorized
copying or u'se thereof and will take any and all available legal action
against copying or distribution of this product.

Printed in the United States of Anerica

APPENDIX 1.

RFVISION STATUS

This Manual Revision applies to:
ASSOCIATE Re vi si on 3.0
CRT- PROM Ve rsion 1. 7. 1. 8. 1. 9, LA
Ke yboa rd PROM Ve rsi on 4
File na lTI! ( .COM

if not specified)

PROM Monitor 5.06. 5.07
Character PROM 5F.60
CP/M and Bios Rev:
2.2.4

Ve rs10n
Numbe r
2.0
2.00
2.0
2.02
2.03
3.01
2.2
2.10
n/a
1.2
3.47

Ve ndor
C

· ···
····· ··
··
··
··
. ·· · ·
··
·
·
·
·
·
.·
··
·
·
·· · · · ·· ·· ··
·
·
·
·
·······
·· · · ·
···
·· · · ·· ·· ··· ··
··
··
···
·· ·
··
········
· · · · · · · ··
·
·· ··
· · · ··
·
· . . · 1.0
· · · · · · ··
WM
· ·· ··
··
·

ASH
BANR
BAUD
COMPARE
COpy
D
DDT
DUMP
ED
EJEC
FOR}",A T
FREE
I~ITSYS

LOAD
PIP
PRINT
SIOPORTS.LIB
S TDDEFS • LIB
STAT
SUBMIT
SYSGEN
T9511
TAPl'
TBAUD
TCRT
TCTC
TDISK
TDMA
TINE
TINT
TPAT
TPIO
TRS232
TRTC
TSERIAL
TSPD • • • • •
VPRINT
(optional)
WH.RLP
XSUB

C ~ CP/M Utility.

U
U
U

U
U
C

U
C
U
U
C
U
C
C
U

• 1.0
1.53
n/a
1.5
2.03

U
U
C
C
U
U
T
T
T
T
T
T
T
T
T
T
T
T
T
U
U

n/a
• n/a
2.05
2.1
1.9
1.0
1.6
1.2
2.12
1.04
1.05
1.02
1.00
1.02
2.03
1.02
1.02
1.0
1.07A
1.07 A
2.0

= ASSOCIATE

Utility. T
ASSOCIATE Test Routine
ASSOCIATE FEATURES

ASSOCIATE FEATURES

GENERAL
Attractive Da sktop Cabine t
Portable
Selectric Style Keyboard
Software Dafinable Function Keys
Accounting Style Nune ric Pad
Low Gla re Sc ree n
Full Screen Editing
HARDWARE
Z80A CPU
6SK RAM
700K Mass Storage on Dual Min1fIoppys
Optional 1.6 Megabytes
Optional Hard Disk
DMA Data Transfer
Hard Disk Interface for Additional Mass Storage
2 RS232 Serial Ports (Printer and Modem)
1 RS449 Serial Communication Port to SOaK Baud
ProgralTl11Bble Baud Rates
Separate CRT Microprocessor
IEEE 488 GPIB Parallel 1/0*
High Speed Arithne tic Processor*
SOFTtolARE
PROM Resident Disk Boot and Diagnostic Monitor
CP/M** Version 2 Disk Operating System
Screen-Oriented Editor
Word Processing Program*
Business Softwa re *
Communications Soft~re*
Extensive Softwa re Support*
BASIC
FORTRAN
PASCAL
RATFOR
PL/l
COBOL
ASSEMBLER
"C"

*Optional
**Tradema rk of Dig1 tal Fe sea rch

TABLE OF CONTENTS
1.

INTRODUCTION.

1-1

SYSTEM ARCHITECTURE

2-1

2.1

Electrical 2.1.1
2.1.2
2.1.3
2.1.4
2.1.5

2.2

Wiring & Power Supply •••

····• · ··• ··

and ~mory Assignne nt
RESET
System Timing
CPU and Instruction Se t
CPU Jumpe r Table

·.....
3.1 DMA Controlle r. • •
• •
·• • · · ••
3.2 Arithme tic Processor.·
· ·Tiner.
·· ·
··
3.3 Interrupt Controller and
3.4 IEEE 488 GPIB I/O
• · ·
·
3.5 High Speed Paralle 1· I/O
· • ···
3.6
I/O RS449 •
· · ·· ·
. 3.7 Console •
·
3.8 Modem I/O ·
.
• •
·· ·· ·· ·· ·· · · · .
3.9 List IE vice I/O
3.10 Floppy Disk
• ·
·
·
·
·
3.11 Status and Control.
• •
·
·
·
3.12 RealTime Clock
······
· · ··
3.13 Baud Rate Generator
• · · • · • ·
·
3.14 RAM On Control.
· · · · · ·· ·· ·· ·· ·· ··
3.15 Se rial I/O Assignment
3.16 S
SumtIB ry • .
• ·
· · ·(Cable
3.17 System In te rconne·c tion
· · · ·· ·• ··
VIDEO PROCESSOR BOARD.
·····
·····
4.1 Internal Architecture
·......
4.2 Keyboa rd I/O. • •
4.3 Utility I/O • • • • •
·;'.· .. . . . . .
4.4 CPU Inte rface • • • • • •
4.5 Character Generator and Video Interface
U!PUT/ OUTPUT • • • • •

4.6

2-2

~mory

~twork

2-1

POW! r Supply
Ba tte ry Backup Option
POW! r Up/PoW! r Down
110/220 Option
Line Filt~ring

CPU BOard
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5

AlC

Light Pen Interface • •

• ••••

3-1
3-1
3-2
3-4
3-4

3-6
3-7
3-9
3-9
3-11
3-12
3-13
3-14

3-16
3-17
3-17

3-18
3-18
4-1
4-1
4-3
4-3
4-4
4-5

4-6

VIDEO PROCESSOR OPERATION.
5.1
5.2
5.3
5.4

5.5
5.6

CRT Display FOl'llBt.
Control Seqtences ••
Soft Key Op!ra tion ••
CRT M! mo ry Alloca tion
CRT PROM Entry Points •
ASCII Chart • • • • • • •

KEYBOARD •

PROM MONITOR •
7.J

5-1

5-2
5-10

...

5-12
5-12
5-13

6-1

... ............. .

PROM Monitor Op! ra tor Comm nds.
PROM Monitor Entry Points • • • •

7.2
8.

5-1

7-1
7-1
7-8

SERVICE PROCEDURES • • • • • •

8-1

8.1
8.2

8-1
8-4

Trouble Shooti ng Cha rt • • • •
Diagnostics • • • • • • • • • • • • • •

8.2.1

TRS232/
TSERIAL
8.2.2 TPIO
8.2.3 TAPU
8.2.4 TBAUD
8.2.5 TPAT
8.2.6 TCTC
8.2.7 TCRT
8.2.8 TDISK
8.2.9 TDMA
8.2.10 TINT
8.2.11 TRTC
8.2.12 TSPD

8.3
8.4

Serial Port Test
Serial Port Test
Parallel Port Test ••
Arithme tic Processor Unit
Baud Rate Cenerator Test
Pattern Test • • • •
Counte r Tine r Te s t .
CRT Test • • • • •
Disk Drive Te st. •
Direct ~2mory Access Test ••
Interrupt Thst • • • • • • •
Peal Tine Clock Test • • • •
Rotational Speed Disk Test •

Disassembly and Peassembly
Fe turn of M! te ria I
••••

. . . .. .. .. .. ..

APPENDIX
A.

ASSOCIATE Wiring Diagram·
1000 CPU Boa rd Assembly Diagram
1000 CPU Board Schema tic Diagram - 5 page s
1005 CRT Board Assembly Diagram
1005 CRT Boa rd Schema tic Diagram

Enginee ri ng Cha nge Orde rs

OPTIONAL INFORMATION - Available To Qualified OEM's
BIOS Assembly Listing
GNAT Monitor Assembly Listing
Video Processor Assembly Listing
Keyboard PROM Listing
Characte r Ce ne ra tor PROM Listing

8-4

8-4
8-5
8-5
8-6
8-6

8'-7
8-7
8-8
8-8
8-8
8-9
8-9
8-10
8-12

Bibliography
F.J. Adams and T. Swanson, "ASSOCIATE ,Operator's Handbook",
Computers/Data Technology, San leandro, CA 1982

GNAT

Digital Research, "CP/M 2.0 User's Guide for CP/M 1.4 Owners", Digital
Research, Pacific Grove, California, 1979
Intel Corporation, "MCS-aO Family of Single Chip Microcomputers User's
Manual", Intel Corporation, Santa Clara, California, 1978
Kernigan and Plauger, "Software Tools"
Micropro, "WordMaster Release 1.06", Micropro International Corp., 'San
Rafael, Cali fornia, 1978
Micropro, "Wordsta rUse r's Guide", Micropro Inte rna tional Corp., San
Rafael, California, 1979
Microsoft, "COBOL-80 Use r's Manual", Microsoft, Bellevue, Washington
Microsoft, "FORTRAN-80 Use r's Manual", Microsoft, Bellevue, Washington
MITS, Inc., "Microsoft BASIC Reference Manual", MITS, Inc., 1977
MOSTEK, "MOSTEK

zao

Bowles, Kenneth L.

lhndbook", MOSTEK Corp., Carrollton, Texas, 1977
"Problem Solving Using PASCAL", Springer-Verlag

Jensen, Kathleen and Niklaus Wirth.
Springe r-Verlag

"PASCAL User

~nual

and Report"

REFERENCED DATA SREETS
MOSTEK Z80 Handbook
INTEL MCS 80 Users Handbook
CP/M Disk Operating System Manua 1
WordMaster Screen Editor Manual
Advanced Micro Devices
9517A DMA Controlle r, 951lA APU, 26LS30 RS449 Drive r
26LS32 RS449 Rece iva r
Mostek 4116 RAM
Western Digital 1793 Disk Controller
Texas Instrunent 9914 IEEE Controller
Tandon 1M 100-2 Disk Drive s
C.ITOR CRT Monitor
Intel 8251 USART; 8155 RAM, Tine r, I/O
Bosche rt OL65 POlie r Supply or OSC OS65 XL PoW! r Supply
Keytronics Keyboard
Corcom 6J4 Line Filter or 6Jl, 3V1 ,Corcom

ASSOCIATE Technical Reference Hanual

1. Introduction

Cha pte r 1
INTRODUCTION

Purpose
This reference manual provides a detailed operating description of the
ASSOCIATE.
It is intended for technical users and contains complete
informa tion on modi fica tion, ope ration of optional fea ture s, inte rfaclng
to other devices, and services available to the System 10 user. Another
publication, the ASSOCIATE Ope ra tor's Handbook, should be referred to for
standard operation and an overall view of the ASSOCIATE.
The ASSOCIATE
The ASSOCIATE is a full function microcomputer built for the small
businesses, communication, and front end terminal applications.
Extensive I/O capabilities include three RS232 Ports, one of which
alternatively can be configured as RS449, an optional IEEE 488 Bus
interface, and a high ,speed parallelirtterface for a. hard disk. The I/O
enables the ASSOCIATE to be a useful tool for laboratory, commun-ication,
and mass storage functions. Wi th the Com muni ca tions Softwa re Package, the
ASSOCIATE becomes an excellent "Smart Terminal" for mainframe
preprocessing and data entry.
A wide variety of software 1s available for use on the ASSOCIATE.
Extensive business software is available through the Business Software
Library; specialized business software can be custom written for users
with particular requirelll!nts.
With CP/M, BASIC, Fortran, and assembly language, software can be easily
developed on the system by OEM's for their specialized applications.
The
word processing software features full screen-oriented editing,
cursor movement control, and automatic file manage III! nt. The function keys
are defined for operations such as line delete, file up 1 screen, and move
ri gh t 1 word.
Optional word processing software provides right-hand margin control,
proportional spacing, and paging. These features plus others make the
ASSOCIATE an outstanding computer for business and documentation purposes.

1-.1

ASSOCIATE Technical Reference Manual

This page intentionally blank.

1-2

1. I<:ntroduction

.;..

t\rcilit~cturt:

Chapte r 2

SYSTEM ARCHITECTURE
This chapter contains information about the architecture of the ASSOCIATE,
both electrical and logical.
Different components of the system and their interconnections are illustrated in Figure 1, "Functional Block Diagram." A full representation of
the electrical and logical architecture is contained 1n the schematics
included as Appe ndix A. As will be noted, boards are designed for maximum
utilization of the board and system area.

TO
TO
I'IIINTfIl MODEM
!tsm RS212
SERIAL SERIAL

drbl

OPTIONAL
ARITHMETIC
PROCESSOR

~
l

.. ,

INTrRVAL
TlMEII

_..

651(
!tAM

r:--

-_. --

SERIAL
SIO

I--

r ---

AOORESS
DAM
CONTROL

I
I

zao CPU

IlK PHANTOM
I
PROM
. ,,'

VIDEO
110

"--

VIDEO
PROCESSOR

~(~80ARD

DMA
CONTROLLER

HARD DISK
''ITERFACE

DISK
CONTROllER

I
!

TO HARD D'SK
CONTROLLER

CISK - lOOK

I 'm.

BUS INTERrACE

CPlB

MAIN PROCESSOR
BOARD

BUS

CISK - lOOK

Figure 1.

Functiona 1 Block Diagram

2-1

ASSOCIATE Technical Reference Manual

2.1

2. Architecture

Electrical--A/C Wiring and Power Supply

The ASSOCIATE uses a swi tching powe r supply.
supply are as shown in Table 2-1.
Table 2-1.
Voltage
+12
-12
+ 5
+12

Spe ci fica tions for the powe r

Power Supply Specifications
Current Rating
.5 AMP

.15 AMP
6 AMP
1.8A (3 Amp Surge)
(Disk Drive s)

The supply is sufficient for internal operation, however, it is not recommended that peripheral devices requiring more than 0.5 amps at +5 or 0.1
amp at +- 12 volts be powered by this supply. For details on the power
supply connection see "System Wi ring Diagram" in Appe ndix A.

2.1.2

110/220 Option

The ASSOCIATE may be wired for 220 volt operation as outlined below.
These changes are to installed by a qualified technician only. Failure to
strictly observe all items may cause considerable damage to the computer
and void the warranty on the unit.
-

1. Remove Jumper JPl from the system power supply if supply is a
Boschert or set switch to 220 volt position for the OSC supply. The
power supply is located below the disk drives. See Section 8.3 for
access instructions.
2. Remove and reinstall voltage se Ie ctor ca rd to the 240 volt position. This card is located on the AC connector at the rear of
the unit.- Note: This must show the 1!Q volt label toward the top.
3. Plainly.!!!!1.!!:!!. system above the AC connector as being modified
for 220 volt ope ra tion.
2.1.3

Line Filtering

The incoming AlC line is filtered with a capacitive inductive line filter.
This reduces the system's susceptibility to extraneous RFI and also
suppresses emissions by the system itself.

2-2

ASSOCIATE Te chnical Re fe re nce

2.2

rva nual

2. Archi te ct ure

CPU Boa rd

Ce ntral to the ASSOCIATE CPU Boa rd is the Z80 mic roproce ssor which is
completely supported by a number of features including 6SK RAM memory,
AM9517 DMA Controller, Floppy Disk Controller, 4 Serial I/O Ports, and
optional items - Parallel I/O, AM9S11 or AM9S12 Arithmetic Processor, Peal
Time Clock, and IEEE 488 I/O.
A complete vi.ew of the CPU board is
available in the "Assembly 1000 CPU" in Appendix A. The CPU board is
built to fully utilize the capability of the Z80 microprocessor through
extensive use of intelligent support controllers.
Memory, CPU, and
general purpose system features are described in this chapter; 110
fea ture s a re de scri bed in Cha pte r 3.

2 •2• 1

t1! mo ry

The CPU board contains 65K of Read/Write RAM and a 2K PROM ove day
controlled by restart hardware and software.
On RESET the system comes up in restart mode, which disables RAM and
e na ble s PROM until code in the PROM mont tor at F800H ena ble s RAM. The
first instruction in the PROM is a JMP to "BEGIN".
The second
instruction, an OUT DOH, which enables RAM, thereby giving an initial
operating configuration of 63K RAM and 2K PROM. The OUT DOH also sets the
modem baud rate. The memory is normally reconfigured under the Disk
Operating System to 6SK RAM and OK PROM. See Section 3.11 Status and
Control for ope ra tional de tails.
The PROM Monitor normally loads the Disk Operating System upon power up or
reset. The Disk Operating System can then immediately execute a user
program. This capability gives users, without technical expertise, the
ability to start the system and immediately run a dedicated program; it
also provides the opportunity to go directly back into an application
program after a power failure.
The physical layout of memory, in terms of address range and bit number,
is illustrated in the "Assembly 1000 CPU" in Appendix A. Thus, if memory
fails the memory test (operator command T under Section 7.1), the location
of the particular memory chip to be replaced can be quickly determined
from the assembly diagram.
Seve ral areas of memory are used for va rious functions by the Monitor and
Operating System. These are:

Ta ble 2.1
0000H-0002H
0003H
0004H
000SH-0007H

D008H-ODDAH

t1!mory Assignne nts

Jump to PROM Monitor or
Jump to BIOS + 3 in Operating System (Warm Boot)
I/O assignnent byte
Cur re nt 1 ogi cal di sk nurnbe rand use r numbe r
BDOS entry in Operating System
(locations 6 and 7 are top of user RAM in both
monitor and DOS)
Unused

2-3

ASSOCIATE Te chnica 1 Re fe re nee

OOOBH
OOOCH
OOODH
OOOEH
OOOFH
OOlOH-OOlFH
0020H-0027H
0028H-002BH
002CH-002FH
0030H-0037H
0038H-003AH
003BH-003FH
0040H-004FH
00SOH-007FH
0080H-OOFFH

nua 1

2. Architecture

La tch port status
System Status (Reserved)
CRT line counter (Reserved)
Exte oded IOBYTE
Poe se rved
Inte rrupt Ve ctors
Ports 72H, 70H, (SIO)
Interrupt Vectors
Ports 20H, 21H, 22H, 23H (CTC) .
Unused
Interrupt Vectors
Ports SOH, S2H, (PIO)
Unused - reserved by CP/M
Jump to PROM Monitor Tra p Entry
Unused - re se rve d by CP/M
Interrupt Vectors
Ports 62H, 60H, (SIO)
Unuse d - re se rve d by CP/M
DOS Boot loade r

In Monitor Operation:
-F7D9H
F7D9H-F7FOH
F7FIH-F7FFH
F800H-FFFFH

Monitor Stack
Monitor Workspace
Tra p Ex! t Code
PROM Monitor

In DOS Ope ration: (6lK)
OlOOH-D7FFH
0800H-DFFFH
EEOOH-EDFFH
EEOOH-FFFFH
2.2.2

Normal Use r Area (TPA)
Console Comnand Processor (CCP)
Disk Operating System (BDOS)
System I/O Drivers (BIOS)

Reset

After a RESET the PROM monitor will attempt to load the first 128 bytes of
Track a Sector 1 from the disk 1n the lower drive (A) into memory
beginning at location 80H. This will normally be a boot for the Disk
Operating System. If a the Disk Operating System is not found, a second
reset will take the system to the monitor command level. Two resets in
rapid succession will also take the operator to the monitor command level.
There are four ways of generating a RESET in the ASSOCIATE:
,

1. Manual - This RESET is generated by 'momentarily depressing SI on
the main CPU Board (see "Assembly 1000" schematic); Sl i9 accessible
on the back right of the unit. This resets both the CRT and the Main
Processor.
2. Yeyboard - This RESET is generated through the video processor by
keying in the Control-Shift-RST. This rese,ts only the main CPU Board
and not the video processor.

2-4

ASSOCIATE Technical Reference M:!.nual

2. Architecture

3. Power Failure - This RESET is exactly the same as the Manual
RESET.
It is activated by power detection circuitry when a power
fail is detected. This feature is on 1000G and later CPU boards.
4.
Software - The two software reset functions are defined in
Section 3.11, Internal Status and Control; these resets affect only
the floppy controller and the 9511 Arithmetic Processor.

2.2.3

System Timing

The main system timing is de rived from a 16 MHz oscUla tor. This is
divided for distribution to the 8 MHz, 4 MHz, 1 MHz, and 1/2 MHz signals
used throughout the board. The most used signal for system timing is 4
MHz; this signal has the necessary circuitry to insure that the Z80A has
the required levels and transition speed for proper clocking.
Baud rate generation for serial ports is accomplished through a separate
crystal; the frequency of that crystal (4.9152 MHz) is an even multiple of
standard baud rates.
A dual software programmable divider described in
Section 3.13 gives the actual baud rates to the serial I/O devices.
Circuitry is provided on the board to take care of the disk drive timing
requirements. The following digital delays are used:
Motor Turn On. If the drive motors are off, a one second delay is
introduced in the head load command to allow time for motor sta rtup.
Motor Turn Off. If the floppy disk controller is not accessed for
128 seconds the disks are deselected and the motor on signal i~
deactivated. The disk motor turn off timing may be optionally set at
other values as follows:

JP35 Motor Turn Off De lay
Pin
Pin
Pin
All

5 jumpe red to pin 6
3 jumpe red to pin 4
1 jumpe red to pin 2
open

128
64
32
No

second (no mal)
second
second
turnoff

Screen Blanking. The CRT display 101111 be turned off 20 minutes afte r
the last CRT activity. The purpose of this turn off is to extend CRT
phosphet' life. The timeout is user programmable - See Section 5.2
for the procedure. The screen will turn back on when any keyboard
key is pressed or the CPU sends a character to the video processor.
2.2.4

CPU & Instruction Set

For detailed information on the Z80 microprocessor refer to "MOSTEK
Microcomputer: Z80 Data Book." Based on N-Channel MOS technology, the
2-5

ASSOCIATE Technical Feference Manual

2. Archi te ct ure

280A-CPU is packaged in an industry standard 40-pin Dual In-Line Package.
Significant features include a single power ,supply (+5V) , a single system
clock signal, mUltiple interrupt capability, and dynamic memory refresh.
Software generation on the ASSOCIATE is simplified through the 280's 158
instructions, unlimited subroutine nesting, vectored interrupts, and DMA
capabilities. Product development and system design are enhanced by the
extensive set of instructions and the varied addressing modes of the 280,
as we 11 as its capability of directly addressing 65K 8-bit words of
memory. For a detailed description of the Operating System software aids
for assembly program production, refer to the "CP/M Disk Operating System
Minual."
The 280 maintains full software compatibility with the 8080
microprocessor, since the 280 instruction set is a superset of the 8080
instruction set.
The Z80 has additional addressing modes, a larger
instruction set, and extended registers.
The internal architecture of the 280 consists of eighteen8-bit registers,
four 16-bit registers, arithmetic and logic unit (ALU), and instruction
registe r.

2.2.5

CPU Jumper Table

The following table summarizes the jumper options for the G and H revision
CPU board.

2-6

ASSOCIATE Technical Reference Minual

2. Archi te cture

Table 2.3 Jumper Lefinition and Lefaults for 1000G,H CPU
JP PG DEFAULT
NAME-FUNCTION
II
II
1
1
1
1
1
1
2

1 used
1 open
4 open
4 oJ:en
4 open
4 oJ:e n
4 open output

4
4
4

5
6
7
7A
7B
7C
7D
8

4
4
4
4

open
opert
open
oJ:en
open
enabled

3
3
3
9
3
10 3
11 3
12 3
12A 3

open
open
2-3
2-3
2-3
1-2
2-3

13A
13B
14
15

3
3
3
3

oJ:en
open
enabled
open
2-3 RS423
open
open
enabled
enabled
ope n
enablea
1,2,3, ope n

15A 3
15B 3
15C 3
16 4

4
16A 4

17
18
19
20
20A
21
22

3
3
3
3
22A 3

grounded
grounded
grounded
RS423
grounded

4-5
6-7
not used
open
not used
te st points
open
1-2 sclkO
1-2 sclkl
open
open
1-2 sclkO

pi ns 1 and 2 used by i nve rte r in re se t
pin 3 O.C.re se t output
pin 4 O.C. linen from 74S287 - PIa Control signal
pin S O.C. /outg from 748287 - PIa Control signal
pi n 6 O.C. / wa it from 745287 - PIa Cont rol signa 1
pin 7 O.C. /tack from 745287 - PIa Control signal
pin 2 open 8304 PIa port A output mode
pin 2 to 1 8304 PIa port A input mode
pin 2 to 3 8304 controlled by latch bit D2
74S287 address inputs-l to 2 AS to B7
3 to 4 A6 to Bl, 5 to 6 A7 to BO
PIa port B Cia ta DO-D7
PIO port A da ta 00-07
parallel DMA port data DO-D7
pin 2 P2 pin 49, pin 1 +5volts, pin 3 ground
ne t'WOrk I/O Jl Remote Gnd to chassis ground
no connection
network I/O pin 8, Carrier Letect Signal
network I/O pin 17, RSET
RS422 input option, N! t'WOrk Rece ive r Option
RS422 input option, Network Receiver Option
RS422 input option, N! twork Rece ive r Option
1-2 26LS30 in RS423 mode, 2-3 in RS422 mode
RS422 input option, N! twork Rece ive r Option
RS422 input option, Network Receiver Option
1-2 list/network port -12volts on pin 10
3-4 list/network port +12volts on pin 9
list I/O J2 Remote Gnd to chassis ground
list I/O pin 6, rata Se t Ready signal
26L530 Vee 1-2 ground of RS422, 2-3 -Svo'rts for RS423
1-2 modem port -12volts on pin 10
3-4 modem port +12volts on pin 9
1-2 modem I/O tse t signal
3-4 mode m 1/ a rse t signa 1
modem I/O pin 8, Carrier Le teet signal
modem I/O Remote Gnd to chassis ground
1 ground, 2 active low pa ralle 1 output enable,
3 PIa port B bit 0 for output control
output enable active low,4-2 for active hi
6-7 for /dreqO from PIa port B bit 3
PIa strobes-l astb, 2 bstb, 3 ardy, 4 nc, 5 brdy
pin
S10
SIO
S10
SIO
SIO
SIO

1
1
0
0
0
0
0

console serial receive data, pin 2 xmit data
sync A
A Modem rece ive clock
B List Levice clock
rtcb 1-2 to tset driver to list pin 15
rtcb 3-4 to rse t drive r to list pin 17
A Modem xmi t clock
2-7

ASSOCIATE Technical Reference Manual

24
25
26
27
28
29
30
31
31A
32
33
34
35
3SA
36
37
38
39
40
40A
41
41A
41B
42

5
4
3
3
3
3
5
3
4

5
1

5
5

open
1-2 enabled
te st points
1-2 sclkO
1-2 RS232
1-2 RS232
1-2 RS232
2-3 01
open
open
1-2 enabled
open
5-6 128 sec
open
open

1793 pin 29 TG43
IEEE488 da ta bus enable
da ta bus 00-07
network clock internal, 2-3 for external
network I/O txd inversion, 2-3 for non inversion
ne twork I/O dt r inve rsion, 2-3 for non inve rs10n
ne twork I/O cts inve rsion, 2-3 for non inve rsion
1793 clock, 1-2 for 02 speed
SIO 1 sync A
RTC /stdbyint
disk ready input
spare inverters in IC 4N
motor off delay, 3-4 for 64 se c, 1-2 for 32 se c
1 62.5Khz clock, 2500Khz clock
status input buffer bit 5, IC 5L 74LS244
Drive Side Source Se le ct

not used
1

1
1

1
1
1
1
4
1
4

1
4
1
1

open
test points
1-2 02
test point
open
open
3-4
open
open
9-10
open
13-14
15-16
17-18
open
test point

In the above table:

2-8

2. Architecture

Double Density Jumpe r, Single Density Open
/nmi zao CPU signal
1 /rd, 2 /wr zao CPU signals
9517a clock, 2-3 for 01
/busak zao CPU signal
spare nand gate IC 6S
1-2 spare input to /dint3
3-4 9511 /end to /dint~ .
5-6 /ex_it to /wait
7-8 9511 /svreq to /dint2
9-10 rtcrdy to /lIBit
11-12 /rtcint to /dint3, RTC Interrupt
13-14 /pause to /_it
15-16 /i to /dint2 (external inte rrupt)
17-18 /ieee to /dint3
disk I/O connector spare pins
/raw data
O.c. • Open Collector Output
/ in front signal name indicates inve rted signal

ASSOCIATE Technical Refe rence Manual

3. Input/Output

Chapter 3
INPUT/OUTPUT

The I/O addressing field of the ASSOCIATE is entire ly committed on the
main CPU Board:
there is no provision for direct external user access to
the 280 data bus.
Communication with the external world is handled
through the five connectors located at the back of the unit. The file
S10PORTS.LIB on the system distribution diskette contains
further
informa tion on the standa rd port name sand assignme nts.
Table 3-1 below describes the address range and assignments of devices
addressed through the I/O instructions.

Table 3-1.

I/O Addresses and Assignuents

Address

Signal' Name

Function

OOH-OFH
10H-1FH
20H-2FH
30H-3FH
40H-4FH
SOH-SFH
60H-61H
62H-63H
70H-71H
72H-73H
80H-8FH
90H-9FH
AOH-AFH
BOH-BFH
COH-CFH
DOH-DFH

59517
59511
CTC
59914
PDMAI
PlOO
5101
SID1
5100
5100
S1793
PDMAO
LATCH
RTCO
RCTCI
BAUDO

IliA Controlle r

EOH-EFH
FOH-FFR

BAUD1
Not Used

Arithm! tic Processor
Inte rrupt Controlle r. Tiner
IEEE 488 Controlle r
Paralle 1 DMA lB ta Port 1
Parallel I/O
N! t'NOrk I/O RS449
Console (CRT)
Modem RS232
List RS232
Floppy Disk Cantrolle r
Pa ralle I DMA ra ta Po rt 0
Status and Cantrol
Peal Tiue Clock 0
Real Tine Clock 1
Mode m Clock. RAM on Control
RS449 Clock
List Clock

Refer to the specific lBta Sheet for I/O sub-maps and operational details
of a pa rti cula r de vice.
3.1

DMA Controller OOH-OFH

The DNA Controller is an Advanced MicroD:!vices AM9517A chip.
This chip
provides direct memory access to system memory (through four channels) for
the following high-speed devices:
1)
2)
3)
4)

High speed Parallel I/O (Channel 0)
Floppy Disk I/O (Channell)
IEEE Bus Interface (Channel 2)
Network Serial I/O (Channel 3)

3-1

ASSOCIATE Technical Reference Manual

3. Input/Output

The fourth channel can also be used for memory to memory transfe r. For
further details concerning the DMA Controller. refer to Advanced
MicroIRlvices AN9517A data sheet.
The AM9517A uses all 16 addresses of its block of 16; it is further
divided into four blocks of two addresses each, where each block of
addresses conesponds to one channel of DMA control. This is followed by
a sub-block of control registers occupying eight addresses. For each
channel, the function of the addresses are:

3.2

Base current address

Base curre nt word count

Arithuetic Processor 10R.llR

The Ari thme tic Proce ssor Option 9511/9512 provide s the ASSOCIATE wi th a
complete high ~rformance arithmetic processor. It considerably enhances
the a ri thme ticcomputa tional speed of the syste m a nd include s not only
floating-point, but fixed-point processing as well.
In addition to add,
subtract, multiply, and divide operations the 9511 includes transcendental
functions and control and conversion commands.
The 9512 is a four function (add, subtract, multiply, and divide)
processor'which provides single precision (32 bit) and double precision
(64 bit) operations in the IEEE floating point standard. This option is
specified as APU-2 when ordering.
The Ari thme tic Processor occupies two address loca tions (lOR and IlH) in
,the Z80 addtessing field. O~ration requires that the operands be wl'itten
on the processor's stack at location 10H followed by the issuance of a
command to the command word at location llR. Two, four, or eight byte
values are written with the least significant byte first. All required
bytes must be read or written in sequence for proper operation. The
desired operation code is then output to the Processor command port (11H)
and the processor will calculate the result. The result can be read afte l'
completion at port lOR most sign1ficantbyte first.
Completion of the processing is indicated in two ways. Port 11R serves as
the status register which can be read for completion status; or the end of
processing may be signaled by an interrupt.
The pause jumper JP42 must have pins 13 and 14 jumpered for proper
operation with the 9511 or 9512. This jumperwlll cause the Z80 to enter
a wait state in order to synchronize the slower read and write timing of
the APU.
The user is cautioned that no attempt to read the result of the
calculation should be made before the calculation 1s complete. The wait
timeout logic will override the APU and an invalid result will be
returned.

3-2

ASSOCIATE Technical Reference Manual

3. Input/Output

There is a jumper option for interrupt and wait operation of
Arithmetic Processor.
The AM9511 uses DINT2 (interrupt 2 into
interrupt controller); that interrupt is normally driven by the
function and by a service request. Three jumper options are available
use with the APU as de scri bed below:

the
the
END
for

Jumpe r Pin JP42APU Jumpe r Options
Pin 13 Jumpereq to 14
Pin 7 Jumpe red to 8
Pin 3 Jumpered to 4

APU Pause gene ra te s CPU Wiit
APU SVREQactivates Interru'pt 2
APU END activa te s Inte rropt 2

The Arithmetic Processor may be reset under software control at any time.
Tt is sent a reset by the po_r up sequence.
A zero in Bit 3 (APURES) of
the Control Word at Addre ss AOH re se ts the APU. The APURES bit should be
held to zero for 50 microsec. When using this reset be sure to get the
status of the control latch from location OOaBH in memory for the setting
of the other bits in the control word.
Two sets of standard software are supplied on diske tte with the APU
option. These are the 9511 test routines and the 9511 Fortran Library
subroutines.
The .fi1e containing .the tes.t routi.ne source is named
TAPU.MAC. It is written in zao assembly code.
The Fortran Library subroutines are in the file APUILREL. These can be
linked into a Fortran program by linking this file in front of the
FORLIB.REL.
The APU11.REL file contains the following entry points,
normally taken from the FORTRAN libra ry:
Table 3-2
ENTRY POINT

APUll.REL Subroutine Library Functions
FUNCTION

~ rform APU Fe se t
add. real and inte8l! r
add real and real
divide real by integer
$da
Sdb
di vide rea 1 by real
exponentiation of real by intege r
Sea
exponentiation of real by real
Seb
multiply real by intege r
$m
mUltiply real by real
5mb
subtract intege r from rea 1
Ssa
$sb
subt ract real from real
convert integer to real
Sca ,float
$ch ,int ,i fix
conve rt real to intege r

RSTAPU

$aa
$ab

sqrt
sin
cos
tan
asin

real
real
real
real
real

square root
sine
cosine
tange nt
arcsine

acos
atan
alog10
alog
exp

real
real
real
real
real

arccosine
arctangent
log base 10
log base e
e**X

3-3

3. Input/Output

ASSOCIATE Te chnical Re fe re nee M! nual
3.3

Interrupt Controller and ThaI' 20H-23H:

The Interrupt Controller provides system timing and manages inputs for the
For
various interrupts that can be gene rated by othe r I/O device s.
de tailed informa tion re fe I' to- the Da ta Shee t on the MK3882/ Z80A CTC. The
Inte rrupt Controlle r can do three diffe rent $ubse ts of ope ra tions:
1. Direct Interrupt Controller. The four devices which utilize the
CTC for interrupt control are connected to the trigger inputs as
follows:
a.
b.
c.
d.

DMA Controlle r Inte rrupt ReqU! st-Trigge r
-Trigger
Floppy Disk Controlle r/
-Trigaa I'
9511 Ari thme tic Processor/
PO"8r fail
-Trigge r
IEEE Bus Controlle r/
Feal Tim Clock

1
2

2. Interrupt Priority Enabling. The CTC is the highest priority
device on the interrupt enable daisy chain. The PIO is the second
device, SIO til is third, and SIO #0 is lowest priority.
3. Timer Operation.
Any of the four CTC channels may be used as a
·timer its corresponding trigger input is not enabled. The slowest
freqU!ncy timeout available is 62.5 Hz.
See Section 2.2.1 Memory for the IIJ!mory map recommended for the interrupt
vectors.
3.4

IEEE - 488 GPIB 30H-37H

The IEEE 488 GPIB Interface Option gives the ability to communicate over
the general purpose interface bus. The option is designed around the
Texas Instrument TMS 9914 GPIB Interface chip. The 9914 allows operation
as a bus controller or as a listener/talker. A complete description of
this chip and an introduction to the bus itself are given in the 9914 data
shee ts.
Sample software for use on the GPIB is s~pplied on diskette with the
option and summarized in this manual.
The TMS 9914 occupies a block of 8 addresses 1n the addressing field.
These addresses are 30R to 37R. A complete description of the function of
each of these addresses is given in detail 1n the TMS 9914 data sheets.
A jumper option is available on the CPU board to either enable or disable
a resistor termination network for the CPIB., As the :ASSOCIATE is normally
expected to be at the end of the GPIB cable, the termination resistor
network is normally enabled. The termination enable option is JP25
located next to Ie2B.

ASSOCIATE Technical Reference

Jumpe r JP25
1 jumj:ered to 2
2 jumj:e red to 3

~nual

3. Input/Output

Te rmina tor Ena ble
Terminator enabled. (Normal)
Terminator disabled. Clad on
ba ck of boa rd be twee n pins
1 and 2 must be cut!

The IEEE controller may be operated under interrupt control on CTC channel
3. This option is control at Jumper Pin Block JP42 as described below.
The 9914 must be programmed to generate the desired interrupt output on
pin 9 and the CTC must be programmed to use channel 3 as an external
interrupt input.
Jumpe I." JP42

IEEE Inte rrupt Req\J!St Option

17 jumpe red to 18
17 ope n to 18

Interrupt connected. (Nonral)
Interrupt not connected
(clad on boa rd must be cut)

The 9517A hand shake lines DREQ2 and DACK2 will perform data transfers
between the 9914 and memory as programmed by the third DMA controller
channel. Use of this feature requires the appropriate programming to be
done for the 9517A DMA Controller chip.
With the GPIB option, sample software is provided for demonstration of its
use. Currently, three sets of software are provided on disk. The first
se t is a collection of subroutines which may be called from Basic or
Fortran. These subroutines illustrate how to initialize the TMS 9914 and
how to put data on the bus and take data off the bus. The file names are:
488SUBS.DOC
488SUBS.MAC

Docutll! nta tion file
Subroutine source code

The second sample software is a Rational Fortran (RATFOR)
program which
is used to transfe I." da ta from a IEEE 488 tape de ck to the microcompute r's
floppy disks. This program named TAPE488.RAT uses many of the utility
subroutines described above.

The third set of sample software is a program to test the IEEE port. The
T488.MAC tests the IEEE-488 option and demonstrates the use of DMA and
interrupts with the 9914 device.
In orde r for the T488.MAC to run, a
second ASSOCIATE connected to the system under test must also be running
the T488.MAC program.

3.5

High Speed Parallel I/O ;OH-53H, 90H,

High speed parallel I/O is optionally available through the rear panel
connector P2 for inte rfacing to such devices as a hard disk.
The
interface consists of two 8-bit bidirectional data channels and eight-bits
of control signals.
These functions are provided by an MK3881/Z80A-PIO,
bidirectional drivers and a 748287 control PROM. This PROM can be defined
for the application the parallel port is used on. A resistor pullup
network is normally installed if the PROM functions are not required.
3-5

ASSQCIATE Technical Reference Manual

3. Input/Output

Several options are available for operating the parallel interface in
different modes for different devices.
These include jumper pin blocks
JP1, JP2, JP3, JP4, JP5, JP6, JP7, and JP16. See Schematic and Assembly
drawings for de tails.
DMA control signals from Port 90H and DMA chanml 0 are used as inputs for
the control PROM.
WAIT LOGIC (lC1B) allows external devices to hold the system bus for up to
15.5 microseconds during CPU or DMA data transfers.
It may also be
controlled by the 74LS287 PROM and jumpe r options.
Further details on configurations for different external devices will be
give n in Application Notes for those devices.
Ieftnition of Pinouts of the external connector is listed in the following
table; all s1gnals are active low.

Ta ble 4-3.

Fa ral1e 1 II 0

Pin /I

NaD

Function

1
3
5
7

PCQ
PCI

Parallel Control Signal
Pa ralle 1 Control stgnal
Paralle 1 Control Signal
Paral1el Control Signal
Paralle 1 Control Signa 1
Pa ral1e I. Control Signal
Parallel Control Signal
Parallel Control Signal
Pa ralle 1 da ta 0
P&ralle I da ta 1
Parallel data 2
Parallel data 3
Pa ralle I da ta 4
Parallel data 5
Parallel data 6
Pa ralle 1 da ta 7
High Speed Parallel rata 0
High Speed Parallel rata 1
High Spee d Fa ralle I ra ta 2
High Speed Parallel rata 3
HighSpee d Fa ralle 1 rata 4
High Speed Pa ralle I ra ta 5
High Speed Parallel rata 6
High Speed Parallel rata 7
Spare (+5 volts optional)
Ground

PC2
PC3

PC4

11
13
15
17

PC5
PC6
PC7
PDQ
POI
PD2
PD3
PD4
PD5
PD6
PD7
RDO

19
21
23
25
27

29
31
33
35
37
39
41
43
45
47
49
2-50 EVEN

HDI
RD2
HD3
HD4
HD5
HD6

HD7
SPARE
GND

When installing the PIO option, cut JP18 6 from 7. With the PIO not in
the system, this jumper is necessary to pass interrupt requests through to
the interrupt controlle r.

3-6

ASSOCIATE Technical Reference M:lnual

3.6

3. Input/Out put

r-.etwork I/O 60H, 61H

This serial output port provides I/O for network communication
applications wi th RS449 protocol. This protocol provide s se~ ral feature s
not ava ila ble in RS232:
highe r s~ed and diffe re ntial drive.
The RS449
is a combined specification for RS422 and RS423.
The following
description is in terms of the RS422 and RS423.
Port 60H is data and Port 61H is status and control. The N!twork I/O baud
rate is software programmable by the baud rate generator addressed at Port
DOHand described in Section 3.13. Note that its clock is shared by the
modem port. When used with the serial manifold external clocking should I:e
selected using JPI7.
The N!twork Port can also be optionally configured
to operate in RS232 protocol. When setup as RS232 the port functions as a
Data Set. For each ·of the different protocols the following table defines
the functions of the connector.
The normal configuration for C Revision and later boards is RS232.
Table 3-4.
Pin"

1
2
3
4

5
6
7
9
10
14
17
18
19
20
24

Pinouts of Different Specs

RS422

RS423

Ground
Tx Da ta Rx Data Request to Send Rx Clock +
Rx Da ta +
Signal Ground
+12
Exte rnal
-12
Exte rna I
Tx I:a ta +
Rx Clock La ta Te rminal Rdy +
Fe que st to Se nd +
La ta Te rmi nal Rdy Clock In Clock In +

RS232

Ground
Tx I:a ta
Rx rata
Reqll!st to Send
Clea r to Se nd
Da ta Se t Rdy
Signal Ground
Powe r
POWie r
Not Used
Rx Clock
Not Used
Not Used
I:a ta Te rml nal Rdy
Clock In
Not Used

Ground
Tx rata (in)
Rx ra ta ( ou t )
Reqll!st to Send (in)
Clear to Send (out)
La ta Se t Rdy (out)
Signa I Ground

Not Used
Rx Clock
Not Used
Not Used
Lata Set
Clock In
Not Used

The mode option defines the operation of the 26LS30

Jumpe r JP11.
RS423 or RS232
RS422

(in)
(out)
(in)
(i n)
Ready (in)
(in)
(in)

dri~r

as follows:

Dri ve r Mode Se Ie ct
2 Jumpered to l(nornel)
2 Jumpe red to 3

Inputs to the receivers may be changed by the jumper options JP8, JP9,
JP10, and JP12. For single ended mode s (RS232 and RS423) the + input of
the recei~r is grounded. The jum~r options are:
Jumpe rs JP8, JP9, JPI0, JP12.
RS423 or RS232
RS422

Receive r Options

2 Jumpered to 3 (normal)
2 Jum~ red to 1

3-7

ASSOCIATE Te chnical Re fe re nce

~la

nua I

3. Input/Output

Transmitte d ra ta may be inve rted by use of Option JP28. For RS232 it must
be inverted for proper RS232 level signals. The clad must be cut on the
back side of the circuit board if the inverted option is implemented.
Jumper JP28.

Transmitted rata Inversion Option

Inve rted (RS232)
Noninve rting (RS422, RS423)

2 J umpe re d to I (no rma I )
2 Jumpe red to 3

The Natwork port also has a clock option as follows:

Jumper JP27.

Auxiliary Clock Option
2 Jumpe red to 1 (no rnal)
2 Jumpe red to 3

Inte rna I Mode m Clock
Exte rna I Clock

inputs of the ne twork port have an option for installing te rmina tion
resistors. These resistors RTI through RT4, located next to device IN,
can be used in either the RS422 or RS423 mode. See the schematic and
assembly drawings for furthe r informa tion.
The

The slew rate control option allows output slew rate to be controlled by
capacitors CSI through CS4 located between devices IP and P4. For value
determination refer to the 26LS30 rata Sheet.
For applications requiring a small amount of external power at + and - 12
volts, a jumper option JP13 provides po~r to pins 9 and 10 of the serial
conne ctor.
Jumper JP13 +and -12 volt
JP13 1-2 for -12 on pin 10

3.7

po~r

option

JP13 3-4 for +12 on pin 9

Console 1/ a 62H, 63H

The Console I/O transfers data between the CPU board and the Video and
keyboard processor. One-half of an SIO device (2G) handles the RS232
protocol for data transfer. The clocking for this half of the SIO is
supplied by the Video Processor.
Refer to Chapter 5 on the Video
Processor Board for complete information from the Video Board side of the
I/O.
Port 62H is data and Port 63H is Status and Control.
The following table reflects pinouts from the CPU Board end of
the Process:

3-8

ASSOCIATE Technical Reference t1!nual

Table 3-5.
Pin II
1,2,3,4,7,8
10,16,17,19,20
6
9
11
12
13
14
15
18
5
3.8

3. Input/Output

Video I/O Pinouts

Name

Function

GND

Ground

DTR
TxD
RxD
TRxC
CTS
RTS

ra ta Te rmi na 1 Ready (from CPU)
Tra nsmi t ra ta (from CPU)
Receive rata (into CPU)
Transmitter Receive Clock
Clear to Send (into CPU)
Request to Send (from CPU)
External Reset (into CPU)
Vide 0 Re sa t (from CPU)
No Connection

EX~ESET

MODEM I/O 70H z 71H

The Modem I/O is handled by half of the SIO device at location 2H and is
configured according to the EIA specifications for a rata 'Ie rminal. 70R
is data "and Port'71H-isStatus andControl.-Refe-r to the'Data book
describing the MK3884/Z80-SIO and the appropriate schematics for
a ddi tional de tail.
The modem port baud rate is software programmable by the baud rate
generator at Port DOH and described in Section 3.13. Note that this baud
rate generator is shared with the N!twork I/O Port.
Connection to a modem is made through P3, a male OB25P connector.
following table describes pinouts for the modem I/O:
Table 3-6.

The

MODEM I/O Pinouts

Pin II

Naue

Function

1
2
3
4
5
6
7
9
10
15

GND
TxD
RxD
RTS
CTS
DSR
GND
+12
-12
TSET

RSET

20
23

OTR
OSRS

STSET

Chassis Ground
Tra nsmi t of Da ta ( ou t )
Receive rata (1n)
Reque st to Se nd (out)
Clear to Send (1n)
ra ta Se t Ready (1n)
Signal Ground
Exte rna 1 PO"l! r - Jumpe r JP15 3-4
Exte rna 1 PO"l! r - Jumpe r JP15 1-2
Transmitter Signal Eleuent
Timing (1n)
Receiver Signal elenent
Timing (in)
rata 'Ierminal Ready (out)
rata Set Ready Secondary
(te rminated with 22K to +12)
Source Tra n smi t te r Signa 1
element Timing (out)

3-9

ASSOCIATE Technical Reference Manual

3. Input/Output

There are two jumper options available with modem I/O on the timing
clocks. One set of jumper pads controls the receive clock and one set is
for the transmit clock.
The Transmitter Clock option is identified as JP23 on the PROM and Serial
I/O schematic in Appendix A.
The transmitte r clock can be sourced
internally or externally, but it is normally jumpered for internal.
I

Jumpe r JP23.

Modem Transmitte r Clock Option

Internal
External
Receive r

2 Jumpe red to 1 (norma I)
2 Jumpered to 3
Open

To use the external option the clad on the back of the circuit board must
be cut between pins 1 and 2.
The Receiver Clock option jumpers are identified as JP21. The clock is
normally jumpered to the internal clock but may be jumpe red to the
external receiver element timing signal or to the transmitter clock.
Jumpe r JP21.

Modem Ieceiver Clock Option

Internal
External
Transmitter

, 2 Jumpe ted to 3 (norma 1)
2 Jumpe red to 1
2 Jumpe red to 4

To use the external option, the clad on the back of the circuit board must
be cut be tween pins 2 and 3.

For applications requiring'a small amount "of external power at + and - 12
volts, a jumper option JPlS provides power to pins 9 and 10 of the serial
connector.
Jumper JP1S

+ and -12 volt power option

JP1S 1~2 for -12 on pii-10
3.9

JPlS 3-4 for +12 on pin 9

List 72H,73H

The list function is handled by half of the SIO device at location 2H and
it is designed to match EIA rata Set specifications. The interfacing chip
is an MK3884/Z80A-SIO.
Port 72H is data and Port 73H is Status and
Control.
The list baud rate is selectable using the baud rate generator at Port EOH
described in Section 3.13 of this manual. Connection to a printer is made
through J3, a female DB2SS connector. The following table describes
pinouts for the pr1~te r:

3-10

ASSOCIATE Te chnical Re fe re nee

Ta.ble 3-7.
Pin #

Name

GND
TxD

3
4
5
6
7
9
10
15

RTS
CTS
DSR
GND
+12
-12
TSET

RSET

20
21

OTR

~1a

Function
Chassis Ground
Tra nsmi tra ta (in)
Peceive rata (out)
. Peque st to Se nd (in)
Clear to Send (out)
ra ta Se t Ready (out)
Signal Ground
External ?oW!r - Jumper JP13 3-4
External POller - Jumper JP13 1";2
Transmitter Signal Element
Timing (out)
Peceiver Signal eletrent
Timi ng (out)
rata Terminal Peady (in)
Signal Quality ~ tector
( Dr i ve n by a 22 K re sis tor t 0
+12V)
Ring Indica tor
(Driven by a 22K resistor to
+12V)
rata Signal Rate Selector
(Driven by a 22K resistor to
+12V)
Exte rna I Clock (in)

SQD
RI
OSRS

TSET

3. Input/Output

List I/O Pinouts

RxD

nua I

Clock Source Option. Jumper Pin Block JP22 gives the option of driving
the list 510 from the inte rna I Baud Rate gene ra tor or exte rnally from Pin
24 on the list device connector.
Jumpe r JP22.

List

Internal
Exte rnal

~vice

Clock Option

2 Jumpered to 1 (norml)
2 Jumpe red to 3

To use the exte rnal option the clad on the back of the circui t board must
be cut be tween pins 1 and 2.
For applications requiring a small amount of exte rna I POWl'! r at + and - 12
volts, a jumper option JP13 provides power to pins 9 and 10 of the serial
connector.
JP13

+and -12 volt power option

JP13 1-2 for -12 on pin 10

JP13 3-4 for +12 on pin 9

3-11

3. Input/Output

ASSOCIATE Technical Reference Manual

3.10

Floppy Disk 80H-83H

The floppy disk controller provides I/O to run the double-sided. doubledensity floppy disk drives. The controller chip is a Western Digital
1793B-02; re fe r to the da ta shee t for de tails on its ope ra tion.
The chip is normally run under DMA control as DMA device 1. Refer to
section 3.1 "DMA Controller" for information.
It can also be run unde r
inte rrupt control; an interrupt request is drive a from inte rrupt reque st
signal DINTl - refer to section 3.3 "Interrupt Controllerll for operation.
Inte rface to the floppy disk is through Connector PS.
defines the pinouts; all signals are active low:

Ta ble 3-8.

floppy Disk Pinout

Pin II

Name

SPARE
HEAD LOAD
SPARE
INDEX PULSE
DSl
DS2
SPARE
MOTOR ON
DIRC IN

4
6
8

10
12
14
16
18
20
22

24
26

The following table

STEP
WRITE DATA
WRITE GATE
TRACK 0

30
32
34

WR PROTECT
READ DATA
SIDE SELECT
READY

1-33 ODD

GROUND

Function
Loadi ng of head
Timi ng Signal from Di sk
Disk Select One
Disk Se le ct Two
Turns on the Sele cted Hotor
Di re ction in ToW! rd Ce nte r of
Disk (Low-I-ead Pulled in
tOWl rd Ce nte r)
Track Step
I:8 ta Goes on Disk
retection of Track Zero for
the Disk
Write Protect
Read I:8 ta
Side Select
Indicates to 1793 that
disk drives are ready
Ground Shield

An option is provided on the board for selecting control of Side Source
Select:

Jumper JP37 Side Se le ct Sour ce
Pia 2 jumpered to Pin 1

Side Select sourced from Control
la tch (norma 1)

Pin 2 jumpered to Pin 3

3-12

Side Select sourced from 1797
(Clad betloeen 1 and 2 must be cut)

ASSOCIATE Technical Reference Manual

3.11

3. Input/Output

Status and Control AOH

The main CPU has a single byte stored in an 8 bit latch used to control
This latch is set to all O's by a RESET.
The lII!mory location aBH is reserved to store the status of this byte. This
byte, written using an OUT instruction to AOH, has the following functions:

key functions in the system.

Ta ble 3-9.
Bi

Function

Signa I Na III!

a
2

DS1
DS2
T/R

APURES

TG19

SIDE SELECT

PROMEN

DISK RESET

Control Functions

Drive Se le'ct (Drive A)
I-ON
Drive Select (Drive B)
I-ON
Parallel Port A Direction Control
a-receive,
1 • transmit
Reset the 9511 Arithmetic
a-Pese t
Processor
"Track greater than 19,"
I-Write Pre camp on
use d by Wri te
.Pre compe nsa tion
Disk Side Select
I-Back side
(0 is bottom, 1 is top)
PROM Enable
a-Enable
(0 is PROM enable,
1 is PROM disable)
Floppy Disk Controller Reset O-Reset

Status is read by the processor at address AOH with the function of the
bits as follows:

Ta ble 3-10.
Bit II

Signal

0
1
5
7

INTRQ
HLT
Spare
DRQ

Naae

Status Bits
Function
Disk Controlle r Done
l2ad Loaded'
IC 5L Pin 13 (JP 36)
Disk Controlle r rata Rudy

A "1" indicates that the sta ted action has occurred.

3.12

Peal Time Clock BOH,COH

The Real Time Clock (RTC) option provides the ASSOCIATE with time information ranging from thousandths of seconds to months. It is available for
Systems using "F" revision or later CPU boards.
The option is based on the MM58167 clock chip with rechargeable nicad
batteries to keep the time information valid even when the computer is
turned off or unplugged.

3-13

ASSOCIATE Technical Reference Manual
The RTC occupies a block of 32 addresses.
assigned as follows:
Table 3-11.

Naue
ctrsm
ctrsth
ctrsec
ctrmin
ctrhr
,ctrdow
ctrday
ctrmon
latsm
12 tsth
latsec
latmin
lathr
la tdow
latday
la tmon
rtclsr
rtcicr
rtctrr
rtcltr
rtcsts
rtcgo
rtcstby
rtctst

OCOR
OClR
OC2R
OC3R
OC4R
OCSR
aC6H
acnt
aC8R
aC9R
aCAH
aCBR
aCCH
aCDR
OCEH

ocm

OBOH
OBlR
OB2H
OB3H
OB4H
OBSH
OB6H
OBFH

These addresses BaR to COR are

Real Tim Clock Functions
Function

Addre ss
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

3. Input/Output

_.j

Counter - thousandths of seconds
Counter - tenths and hundredths of Seconds
Counter - seconds
Counter - minute s
Counter - hours
Counte r - day of the W!e k
Counter - day of the month
Counte r - months
latch - thousandths of seconds
La tch - tenths and hundredths of seconds
latch - seconds
latch - minutes
latch - hours
latch - day of the week
Latch - day of the month
latch - months
Inte rrupt sta tus regi ste r
Interrupt control register
counte r rese t
12 tch re se t
status bit
"Go" comuand
Standby interrupt
Test mode

Two software programs are provided with the Real Time Clock option. These
are: TRTC.COM, a routine that allows the operator to manually set and
test all the parameters of the clock operation, and TIME.COM, a sample
routine to display the curre nt time on the moni tor.
The system time may be se t or re se t using the 'T' option in the TRTC
program.
In response to prompts from this routine the user sets the
. current hour, minute, second, day, day of week, and month. Once set, the
current time is always available by doing an input from the proper counter
as shown in the above table or by executing the program 'THtE'. Day 1 of
the week is Sunday.
The NICAD batteries and charging circuit provide a 10 to one ratio for
backup versus on time.
This ratio is set by the 330 current charge
resistor R7. When the system is first used with new batteries, the AC
power should be left on continuously for the first t.eek.
The voltage at
pin 24 of the 58167 device should be greater than 3.4 volts with the AC
power off. If the voltage is lower than this, the batteries need to be
charged or replaced. 500 hours of back-up is available from fully charged
batte des.
The Real Time Clock chip can be programmed to generate an interrupt at a
preset time. To enable the interrupt, jumper pins 11 and 12 togetrer on
3-14

.-\SSOCIATE Technical Reference

~nual

3. Input/Output

jumper pad JP42 located between 7L and 7K.
This ties the regular
interrupt output of the MH58167 to Trigger 3 interrupt input of the CTC
Interrupt controller. The CTCchannel 3 must be set for a count of 1 to
act as an inte rrupt controlle r.
Jumper Pin Block JP42

RTC Inte rrupt Ope ra tion

Pin 11 jumpe red to 12
Pin 11 open to 12

RTC Interrupt Enabled
RTC In te rru pt Di sa ble d
(NorTllll)

The standby interrupt output from the device,
a vaila ble on Jumpe r Pin JP32.

normally not used is

A variable capacitor (C6) on the board allows minor adjustments of the
clock rate of the Real Time Clock. The capacitor is located at the edge
of the board next to the Clock chip at location 35. The procedure for
setting the time is as follows:
Check time against a standard to determine the number of seconds per day
of error. Then select the '5' option in the TRTC program. A series of
hex numbers will be provided which should stabilize to a value between
FFEOH and 001FH. This number is the Peal Time Clock offset in seconds per
day.
If the Clock is running too slow, adjust C6 to increase this numbe r
by one for each second per day the Clock was slow (0001 is greater than
FFFF). After adjustment, 90 seconds is required for the number displayed
to stabilize.
3.13

Baud Fa te Ge ne ra tor DOH ,EOH

Baud Rate Generation is done by a dual software controlled timer whose
source crystal frequency is 4.9152 MHz.
The normal assignment of serial ports to the Baud Rate Generator is shown
in Table 3-12. This assignnent may be optionally changed as'described in
the section for each of the individual devices.
Table 3-12.

Se rial Function
List D!vice
Modem
~twork

Video

No rm 1 Ba ud Ra te Generator Setup
Baud Rate
Gene ra tor Address
EOH
DOH
DOH
Exte rnal

D!fa ult Rate
9600
300
300
48000

Each port of the baud rate generator uses only four bits of the byte
written to it. The port at DOH uses only the four least significant bits.
EOH Port uses the four most significant.
In the following table the left
and right nybbles are shown to be duplicates, which simplifies operations:
an "OUT" instruction with the data from this table to port DOH or EOH will
se t the ba ud ra te for tha t de vice:

3-15

ASSOCIATE Technical Reference Mlnual
Table 3-13.
Byte

3. Input/Output

Baud Rate lo1ith 16x clock
Baud Rate

50
75
110
134.5
150
300
600
1200
lS00
2000
24bo
3600
4S00
7200
9600
19200

00
11

22
33
44
55
66
77

8S.
99
AA

BB
CC

DO
EE
FF

For example in the PROM l'tonitor the procedure to set the List device to
1200 baud is:
QO:EO,77

(the monitor provides the colon)

or to set the modem port to 9600 baud:

QO:DO,EE
The baud rate generator is\.reset upon power up, CTRL-SHlFT-RST, or a
manual reset from the rear panel. It is not changed by a CTRL-C w~rm
re boot.

3.14

Ram gn Control

An Output instruction to location DOH will clear the restart Flip/Flop
thereby enabling RAM and restricting PROM addressing to locations FaOOH to
FFFFH. No software p~ov1sion is made to disable RAM once it is enabled.

3.15

Serial I/O Assignuent

The CP/M Device assignments are described in the table below •. The left
side is the logical name and the right side of the assignment being the
CP /M ftmction.
CON:
LST:
PUN:

RDR:

•

•
•

Monitor display and keyboard
Printe r device output
Punch device output
Reade r device input

This assignment is controlled by two oytes referred to as lOBYTE and
EXTlOB stored in memory locations 0003 and 0004. The default values are

3-16

ASSOCIATE Technical Reference Manual

3. Input/Output

11101000 (E8 HEX) and 00000000. Each of the CP/M functions is controlled
by two bits out of each byte.
The following table shows all the possible
device assignrre nts for each of the functions:
The bit pattern in IOBYTE determines the physical port assigned toeach
logical de vice.
LST:

PUN:

RDR:

CON:

OOxxxxxx

xxOOxxxx

xxxxOOxx

xxxxxxOO

62hex

Olxxxxxx

xxOlxxxx

xxxxOlxx

xxxxxxOl

60hex

lOxxxxxx

xxlOxxxx

xxxxlOxx

xxxxxxlO 1
' - 1 - --.-.-- I
I 70hex
I

Back Panel
Connec·tor

1------------1------------1------------1------------1

Internal
CRT

N!! twork

1------------1------------1------------1------------1
I

70hex

-- 1

70hex

Port

···1oIodem
Port

I------------I-------~---I------------I------------I

1 llxxxxxx

1
1

1 xxllxxxx

I
72hex

72hex

1 xxxxllxx

1 xxxxxxil

72hex

----------------------

Ust
Port

The bit pattern in IOBEXT determines the driver assigned to each logical
device.
LST:

PUN:

RDR:

CON:

OOxxxxxx

xxOOxxxx

xxxxOOxx

xxxxxxOO

iostd

xxxxOlxx

xxxxxxOl

iostd

1------------1------------1------------1------------1
Olxxxxxx
iosq

xxOlxxxx
iosq

iosq

remote

1------------1------------1------------1------------1
lOxxxxxx

xx 1Oxxxx

xxxxlOxx

xxxxxxlO

iodiab

iodlab

iostd

llxxxxxx

xxllxxxx

xxxxllxx

xxxxxxil

1------------1------------1------------1------------1
null

null

Drive r
Il! fini tion
Std is the
standard
assignnents
SQ indica tes a
Control-S and
Control-Q handsha ke output
Diab 1s driver
for Diablo
printe r
Re rno te Il'e a ns
that the Modem
Port 1s paralle I
with the CRT

3-17

£2

3.16

Set-Up

l'l(llll/(iUL :,UL

Summary

The ZBO-SIO is a mult-funct:ton peripheral component designed to satisfy a
wide variety of serial data communications requirements. The normal set
up of the SIO is 1 start bit, 8 data bits, 1 stop bit, no parity, and x16
clock divider. The SIO 8 write registers and 3 read registers whose
functions are defined below:

WRITE REGISTER 0
03

o
o
o
o

0
0

o
o
o
o

I
0
I
0
I

o
o

01
0
0

00
0

[[,71 Del 051 041 °1~1

1
1
0
2
I
3
0
4
o 1
5
I
0
6
1
I
I
7
NULL COOE
SENO A80RT (SOLC)
RESET EXT. STATUS INTERRUPTS
CHANNEL RESET
RESET R.INT ON FIRST CHARACTEr<
RESET T.INT PENOI.NG
ERROR RESET
RETURN FROM INT (CH.A.(JNl VI

WRITE REGISTER 1

I I
i
I

I
I
I
NULlCOOE
'IESET R. CRC CHECKER
AESET T. CRC GENERATOR
f'ESET r. UNOERRUN/EOM LATCH

I
- I
.

I ' ,
:

I L

Rx ENABLE
L--SYNCCHAR,,;,
LOAD INHIBli

i
1.-_ _ _ _ _

ADDRESS SEAlMOOE (SDLC)
RM CRC ENABU
ENTER HUNT I,"

I
a o

ih
R.
Rx
Rx

'
L
I

i
'

5 BITS/CHARACTER
7 BITSltHARACTER'
6 BIT$i.cHARAGTEftc
a BITS/CHARACTER
-...;.1)
"
", ,

3-1R

va'

STATUS AFFECTS
VECTOR {CH·B·ONL YI
Rx INT DISABLE
Rx INT ON FIRST CHARACTER
ONLY
INT 0 N ALL R. CHARACTE RS
(PARITY AFFE<;TS vECTOR)
INT ON A. LL R, CHARACTERS
(PARITY DOES NOT AFFECT
vECTOR)

PARITY ENABLE
_ _ PARITY EvEN/ODD
a 0 SYNC MODES ENABLE
a 1 I STOP BIT/CHARACTER
t
0
I Y, STOP BITS/CHARACTER
1
I
2 STOP BITS/CHARACTER
0
BITS SYNC CHARACTER
a I 16 BIT SYNC CHARACTER
SDLCMOOE (01l11110SYNC FLAGI
1 EXTERNAL SYNC MOOE
XI CLOCK MOOE
x 16 CLOCK MODE
XJ2 CLOCK MQOE
:\64 CLOCK MODE

' - - - - - - - - AUTO ENABLE',

a a
o 1
a

L..:: Tx INT ENABLE

' -_ _ _ _ _ _ V4
1 . - - -_ _ _ _ _ v5

'-----------ve
I.------______

·CAN ONLY BE WRITTEN INTO CHANNEL'

WAIT/READY ON R/T
' - - - - - - WAIT FN/RE/,OY F!I:
1.-_ _ _ _ _ _ IVAIT.'REACY E:,;"SLE

:3;: '~ci~ ::-5 :-j4To31 [)2i 0Ii 001
•

o
0

OLe

WRITE REGISTER 4

WRliE REGISTER 3

WR.TE REGISTER 2·

or' ¢1O,9l eXT 'NT e..

WRITE REGISTER 5

1.-_ _ _

a a
a 1
a
'-OTR

Tx CRC ENAoBL,
RTS
S'OD:,c RC'1 Ii

' - - - - - T. E'~ABLE
'--------SENO BRE;.. ...
Tx 5 BITS (OR LESS)/CHARACTER
Tx 7 aITS/CHARACTER
Tx 6 BITS/CHARACTER
Tx B BITS,CHARACTER

WRITE REGISTER 6

I I,

I
,

':
. I
!

WRITE' REGISTER 7

'~ II

:'---SYNC
SYNC BIT 0
BIT 1

II..-----SYNC
SYNC BIT 2
BIT 3

10
11
12
13
14
15

•

'-FOR SDLC IT MUST.BE PROGRAMME .
TO "01111110" FOR FLAG RECOGNtT:

READ REGISTER 2 (Channel BQ(1ly)

:,:..J-~":;':;.L.::;~::r--'-=r"-T--"-r-'Rx CHARACTER AVAILABLE
INT PENDING·
I..-_ _ _ T. eUFFER EMPTY
'---_ _ _ _ OCD
I..-_ _ _ _ _ SYNC/HUNT
_ _ _ _ _ _ CTS

00
1..-_ __ _:

~fl

l-----V3
INTERRUPT
' - - - - - - V 4 . VECTOR

1--_ _ _ _ _ _ _ _ SENDING CRC/SYNC
_ _ _ _ _ _ _ _ _ _ BREAK/ABORT
. :;.N ONLY BE REAO BY CHANNel.

L-.

I· "

~--SYNC BIT
I..-----SYNCBIT
' - - - - - - - S Y N C BIT
,
SYNC BIT
SYNC BIT
'--_ _ _ _ _ _ _ _ _ SYNC BIT

SYNCBIT4 •
SYNC BIT 5
SYNC BIT 5
' - - - - - - - - - - SYNC BIT 7
• ALSO SOLC ADDRESS FIELD

~EAD

I
SYNC BIT 8
'--SYNC BIT 9

'---------\'5 I
1..---------V6 i

----------V7

READ REGISTER'

;-D"7Tolii OS! D4! ()3! 0·2......!-O-'~!-DO~:
iTlT-T-·"j-~--c.ALL 51::;:"
I;
"
,FIELD BiTS
I i : , ~ . : iN PRE'.!!C:US

I ;
'I

i1 :
'0
0

a
1

--PARITY ERROR
L - R . OvERRUN ERROR
'--_ _ _ CRe/FRAMING ERROR
' - - - - - E N O OF FRAME (SOLei

3.17

3
4

BYTE
0

I·FiELC a;7~ :r,
SECOND PR EV IGUS
BYTE

a
8
8
'RESIDUE DATA

System Interfacing (Cables)

Several cables are available from t() fiicilitate connecting the .\SSOCIATE
to external devices.
Several of the most commonly used cables are listed
belolo.' for reference.
All sign3l line nomemclature used is defined
according to EIA RS232C conventions.
The (in) or (out) is loIith rl! ference
to the microcomputer hardware, for example 'lny line labeled (out) will
have ck'lta coming from the CPU processor bOArd.

3-19

ASSOCIATE Te chnica 1 Re fe re nce Ma nua 1

3. Input/Output

CA-60 ASSOCIATE to NEC Printe r
This cable is used to connect the the ASSOCIATE List Port to the NEC
Printer. This cable is an adapter to the NEC supplied cable. It is used
so that no changes are required in the NEC cable. The wiring in the cable
is one to one exce pt for pin 20 as follows: ,
CA-60 Ca ble - ASSOCIATE to NEC Spinwri te r
DB25S (NEC Cable)

DB25P (List Port)
Pin

Pin II

Function
Olas Ground
Ix Data (in)
Rx Data (out)
.que st to Send (in)
Clear to Send (out)
Da ta Se t Ready (out)
Sig Ground
.c'd line sig (out)
Data Te rminal .ady (in)

1
2

3
4
5
6
·7

8
20

1
2

3
4
5
6
7
8
19

CA-61 ASSOCIATE to TTY Model 40 Line Printer
This cabJ4 is used to connect the the ASSOCIATE Ust Port to the Teletype
Model 40 line Printer. The wiring is one to one except for pin 4 as
follows:
CA-61 ASSOCIATE to TTY Mode 1 40 Line Printer
DB25S (TTY 40)

DB25P (List Port)
Function

Pin'
1

2
~.

4.
6
7
20

Olas Ground
Ix Data (1n)
ax Data-c{out)
lequest to Send (in)
Da ta Se t·· P.aady:~.( o~t;()
Sig .GrQuruL
""
Da ta Te tu.F.ady ,(-in>.·,:

Pin II

1
2
3
14
6
7,

CA-62 ASSOCIATE, to. MODEM
This cable is used.to connect the the ASSOCIATt Modem Port to a modem.
This is a standard EIA - RS232C extension cable. It can also be used to
connect.the List or Network-po.re to any RS232C Data Terminal Equipment
such asan ASSOCIATE Terminal or the modem port of another ASSOCIATE. The
wiring in the cable 1s o~ to:.one.as follows:
.

3-20

ASSOCIATE Technical Reference :1anual

3. Input/Output

CA-62 ASSOCIATE to NODEM Cable
DB2SS (MODEM Port)

Pin If
1
2
3
4
5
6
7
8
15
17
20
24

DB2SP (MODEM)

Function

Pin II
1
2

Chas Ground
Tx ra ta (out)
Rx ra ta (in)
Request to Send (out)
Clear to Send (in)
ra ta Se t !eady (in)
Sig Ground
Rec'd line sig (in)
Trans Clock (in)
Re c Clock (in)
rata Term !eady (out)
Trans Clock (out)

3
4
5
6
7
8
15
17
20
24

CA-63 ASSOCIATE to .Terminal
This cable is used to connect the the ASSOCIATE Natwork or List Port to a
Terminal device with a female connector such as an ADM3A. The wiring in
the cable is one to one as follows:
CA-63 ASSOCIATE to Te rminal Cable
DB25P (MODEM)

DB25P
(NETWORK or LIST PORT)
Pin II
1
2
3
4
5
6
7
8
15
17
20
24

Function
Chas Ground
Tx rata (in)
Rx rata (out)
Request to Send (in)
Clear to Send (out)
ra ta Se t Ready (out)
Sig Ground
!ec'd line sig (out)
Trans Clock (out)
!e c Clock (out)
ra ta Te rm Peady (in)
Trans Clock (in)

Pin /I
1
2
3
4
5
6
7
8
15
17
20
24

CA-65 ASSOC IATE to TI Hode 1 820 Pri nte r
This cable is used to connect the the ASSOCIATE List Port to the Texas
Instrument Model 820 Printer.
The wiring 1s one to one except for pin 4
as follows:

3-21

ASSOCIATE Technical Reference Manual

3. Input/Output

CA-65 ASSOCIATE to TI Hode I 820 Printe r
DB25P (TI 820)

DB25P (List Port)
Pin II

Pin II

Function
Chas Ground
Tx rata (in)
Rx Da ta (out)
Request to Send (in)
Da ta Se t Ready (out)
Sig Ground
Oi rrie r Da t (out)
Da ta Te rm leady (in)

2
3
4

7
8
20

1
2
3
11
6
7
8
20

The Secondary Request To Send dgnal from the printer is tied to the List
port Request To Send.

The TI 820 is a programmable printer. To program it for operation with
the ASSOCIATE, lift the cover, slide the "configure" switch to the local
position and proceed with the programming. Start by typing in a
and then a which will put the printer in full duplex reverse channel
mode. The suggested baud rate is 9600 programmable by-typing 28
. No other parameters need changing. Set the "configure" switch
back to its normal position for ope ration. See the TI manual for comple te
programming details.
QUME Printer Operation
The QUME Sprint 5 printer will C.onnect directly __ or through aCA-62 cable
to the List port. The Qume should be se t up a s follows:

Front Pa ne 1 Swi tche s
Reset
Baud Rate
Duple x
Parity
Reset
Auto LF
Mntel!
Char Spac
Form length
Top of Form
Form Feed

Inside Switches
Both swl tched to the Ie ft
side of the unit.

- 1200
- Full
- r-tl rk

Modem - off
Ra,te - Hi

-Off
- Standard
- your choice
- 11 is standard

A Qume Sprint 9 is connected to the ASSOCIA'1;E by a 1: 1 ca ble. The WordSta r
setup for the Sprint 9 1s the same as the Sprint 5. For normal Sprint 9
operation withthe ASSOCIATE, the internal options are set as follows:
A-a A-7 A-6 A-S A-4 A-3 A-2 A-I
on on on off off on on on

3-22

a-8 B-7 B-6 B-s B-4 B-1 B-2 B-I
on 'on on on on on on off

Chapte r 4
VIDEO PROCESSOR BOARD

The video processor board provides control of the ASSOCIATE CRT and
keyboard. The video processor board is built to enable the CRT to run as
a stand alone te minal. A separate manual is available describing the lOT
Te rminal ve rsion of the ASSOCIATE.
Key chips on the video processor board are the Intel 8085 Microprocessor
and Motorola 6845 CRT Controlle r. Re fe r to the appropriate ma nufacture r's
manual for detailed information on these chips.
The processor has lK of
local RAM for temporary storage. The 2K video RAM is dual-ported, so
e it he r the 8085 or CRTC can address it. The CRT controlle r controls readout of RAM into the video generator, and the 8085 processor can both read
a nd write into video RAM.

Two 2K PROM chips provide program storage and character generation for the
video processor. The program is stored in the first 2K of the memory of
the 8085 and begins execution immediately upon power up. The second PROM
is used as a character generator for the 8 x" 12 dotmatrtx character set.
Standard PROMs are TMS2516's. TMS2532's can be used with no hardware
changes if more extensive CRT control programs are needed.
Use of a
TMS2532 for alternate character sets requires IC30 pin 18 to be jumpered
to an I/O pin on the 8155. A program for generation of custom character
se t sis ava 11a ble from ra ta Te chnology.
All data going to the main processor is transferred via a serial line,
with the video processor providing the clock Signals to-the main CPU
Board. The video processor board has two parallel data channels, one for
the keyboard and are for the utility port. The utility port is a general
purpose pa rallel port which can be used for a second ke ybea rd.
The video processor board has on it a
"Control C:' character.

bell normally activated by a

The video proce ssor boa rd is mounted, ve rtically, in the back of the CRT.
Access to the video processor board is accomplished by removing the front
panel assembly as described in Section 8 of this manual.
Sections in this chapter include descriptions of the video processor
board's Internal Architecture (including a memory map), keyboard I/O,
Utility I/O, CPU Interface, Video generator interface, and operational
cha racte ristics.

4-1

ASSOCIATE Technical Reference
4.1

~tlnual

4. Video Board

Internal Architecture

The peripheral devices on the video processor board are addressed by
me mary mapping as shown in the following. table:
Table 4-1.

Video Processor Boa rd Mtmory Map

Address

Il! vice

Il! scd pHon

0000-07FF
1000-13FF

CPU PROM
CPU RAM

2000-27FF
3000

VRAM
RESET OUT

4000-40FF
4800-4803
4804-4805
5000-5001
6000
7000-7001

8155 RAM
8155 I/O
8155 TIMER
8251 USART
BELL.
CRTC

Stores Program for CPU
CPU RAM ~ Scratch area for
8085 Microprocessor
Video RAM
Generates a RESET to the main
CPU board
CPU RAM scratch area
Utility and keyboard I/O
Ba ud Rate Ce IIi! ra tor
Inte rface to the Ma in CPU Boa rd
Bell
CRT Controlle r

An option is available to allow substitution of an 8156 for the 8155 I/O
device •
8155/8156 Option
. CE jumpered to 5
CE jumpe red to 6

8155 device (norual)
8156 device

For operation with the 8156, the clad be t\08en CE and 5 must be cut.
The CRT Controller and I/O devices drive the processor through the
interrupts. The following table specifies the interrupt priority:

Ta ble 4-2.
Priority

4-2

Interrupts and Priority

Interrupt Name

VSYNC

TRAP

2
3
4
S

RxRDY
TxRDY

R7.5
R6.5
RS.5
INTR

INTA
INTB

Ie scription

Ve rtical Sync
Rece ive Data 'from CPU
Receive Data from Utility
Re ce i ve Da ta from I<'e yboa rd
Transmi tte r to CPU Ready

ASSOCIATE·Te chnical Refe re nee Ma nual

4.2

4. Video Board

Ke rboa rd I/O

Keyboard I/O is handled through the 8155 I/O and Timer. When a key is
pushed, i t generates a strobe signal which clocks the keyboard data into
the 8155. The 8155 will in turn generate both an interrupt and a data
ready flag to ttl! processor. Under normal software the Video Processor is
interrupt driven, but could alternatively operate in a polled fashion.
Refer to the Intel data sheet for complete information on the 8155.
Refer to the keyboard table in Chapter 7 of this reference manual for a
complete description of data transmitted by different keys.
The following table describes the various pinout functions of the keyboard
I/O. A 20 pin 3M ribbon cable is used to attach the keyboard. This cable
also supplies power for the keyboard electronics.
Table 4-3.

Keyboard I/O Pinouts

Pin II

Name

Function

1
3
5
7

ASTB
ARDY

11
13
15
17
19
2-8 Even
10,12
14,16
18,20

4.3

PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAD
GND
+5V
+12V
-12V

ra ta a varIable fiom keyboard
~yboard transmi t ena ble
rata bit 7
rata bit 6
rata bit 5
rata bit 4
rata bit 3
rata bit 2
rata bit 1
. rata bit 0
Ground
Power
POW! r
Power

Utility I/O

The utility I/O is designed to be a general purpose port which can be used
to attach an additional keyboard.
The following ta ble de. scribe s the va rious pinout functions of the utili ty
port. A 20 pin 3M ribbon cable is used to attach to the port:

4-3

ASSOCIATE Technical Reference Manual

Table 4-4.

Utility I/O Pinouts

Pin IF

Name

Function

1
3

BSTB
BRDY
PA7
PA6
PAS
PA4
PA3
PA2
PAl
PAO
GND
+5V
+12V
-12V

La ta a va ila ble from keyboard
feyboard transmi t enable
rata bit 7
rata bi t 6
rata bit 5
Lata bit 4
Lata bit 3
rata bit 2
Lata bit 1
rata bit 0
Ground
POW! r
Power
POW! r

5
7
9
11

13
15
17
19
2-8 Even
10,12
14,16
18,20
4.4

4. Vi de 0 Boa rd

CPU Inte rface

An 8251 chip is used for the communication interface between the video
processor board and the main CPU; it follows RS232 standard serial
protocol. By having standard RS232 protocol t~ CRT/keyboard can function
as a standalone te rminal, similar in capability to an enhanced ADM 3A in
terms of interaction with another computer.
The connection be ttoeen the video processor board and the CPU Board is made

through a 20-pin ribbon cable which connects to P6 on tl'2 CPU Board and J1
on the video board.
The following table describes Pin functions for the CPU Interface.
direction references are to tl'2 host CPU.
Table 4-5.

Interface Pinout

Pin Ii

NallB

Function

1,2,3,4,7
5
6
9
11
13
14
15
17
18

GND

Ground
Lata Terminal Ready (to CPU)
La ta Se t Ready (from CPU)
Re ce i ve La ta (from CPU)
Transmi t La ta (to CPU)
Request to Send (from CPU)
Clear to Send (to CPU)
Re se tOut (to CPU)
Clock (to CPU)
Re se t in (from CPU)

DTR
DSR
RxD
TxD
RTS
CTS
RESOT
CLOCK
RESIN

All

A re se t from the ke yboa rd (control shi ft RST) doe s not re se t t he vide 0
processor, it merely transmits the reset through to the main CPU. See

Section 2.2.2 for further information on resets.

4-4

ASSOCIATE Technical Reference

4. Video Board

~nual

Two options are available on the Serial I/O clock.
below IelO is for the clock source signal:

The first located

Clock Source Option.
BDR jumpe red to IN
BRR jumpered to EX

Inte rnal clock
External clock

The clock source is normally internal; to use an external clock the jumper
clad on the back of the circuit board must be cut.
The second option selects the frequency of the input into the Baud Rate
divider. The source timing normally is 2.304 MHz but may be jumpered to
4.608 MHz. The faster source clock will allow operation at a higher baud
rate but does exceed specification for the standard 8155 time r.
Clock Rate Option
CK jumpe red to .02
CK jumpe red to 04

. 2 MHz source ( no rna I)
4 MHz source

To implement the 4 MHz option the ciad to 02 must be cut on the back of
the ci rcui t boa rd.

4 .5

Cha ra c te r Ce ne ra tor a nd Vi de 0 In te rfa ce

Video display infor1ll8 tion from the Vide 0 RAM-is passed through a 2716 PROM
used as a character generator.
It is then combined with cursor
information and transmitted to the CRT via connector P3 as EIA composite
video. The board is configured to allow operation with a 2732 PROM
the re by doubling the characte r se t. To operate with a 2732 pin 18 must be
connected to the proper level. It is normally connected to ground.

Table 4-7.

Video Connector P3

Pin #

NaUl!

Function

1
2

VID
VER
HOR
GND

I.e rtical Sync
Hort zonta 1 Sync

3
4

Video
Ground

4-5

ASSOCIATE Technical Reference Hanual

4. Video Board

Three options are available in the video generator section.

They are:

Composi te Vide 0
Horizontal and 'vertical Sync
add to video
No sync inforuation adele d
to video (normal)

E jumpered to D,
E jumpered to F

To add sync inform tion, jumpe r be t-.een F and E.
The following options have been changed on differing levels of
the ECO list for de tails - Se ction 2.2.6

ECOs.

See

. Attribute Option
CA7 jumpered to INT
CA7 jumpered to REV

The eight bit attribute is
foreground/background (norma l)
The eight bit attribute is
reverse/normal video

To operate the eight bit attribute in the reverse/normal mode the clad
be twee n CA7 jumpe red to INT must be cut.
Video Mode
B jumpe red to A

Cha racte rs are di spla ye d whi te
on bla ck ba ckground ' (no rma l)
Characters are displayed black
on white background

B jumpe red to C

To change the display mode the clad be tween B and A must be cut. It is
possible to jumper this option to unused pins on the 8155 and switch modes
unde r softwa re control.
4.6

Light Pen Interface

Interface to a standard light pen may be made by connecting to P4 on the
Video Processor board. The light pen input may be either active high or
active low depending on the invert option as follows:
Light Fe n Invert Option

4-6

Jump! red to

High

Active high signal

Jump! red to

Low

Active 10 signal

ASSOCIATE Technical Reference Manual

5. Vide 0 Ope ra tion

eM pte r 5

VIDEO PROCESSOR OPERATION

This Chapte r de scribes software and control characte ristics of the vide 0
processor.
The following subjects are covered:
CRT Display Format,
Control Sequences, Use of "Soft" keys, CRT Memory Data Areas, CRT PROM
Entry Points, and Down-Loading a Program into the CRT.

5.1

CRT Display Format

The CRT has an 80 column, 24 line display area.
Characters may be
displayed in background (normal intensity) or foreground (high intensity
or reverse video) with background as the default display mode.
Foreground/Background can be invoked in two ways:
The first method is to use control sequences to select either
foreground or background mode. Once a mode has been selected, all
displayable characters sent to the CRT will be displayed in that'
mode.
The second 1II!thod is to use the high-order bit of characters sent to
the CRT. !fa character with the high order bit is received by the
CRT, i t will be displayed in the opposite of the currently selected
mode.
The CRT can also display a twenty-fifth line which does not scroll with
the othe r tloenty-fout.
This line can display up to eighty characte rs or
72 cha racte rs plus time-of-day clock. Control of informa tion displayed in
the twenty-fifth line is described later in this Chapter.
The CRT is capable of displaying 128 different characters. Each character
can be displayed in either foreground or background.
96 of these
characters, the "printable" characters, hex values 20H to 7FH, are
displayed by Simply sending the character to the CRT.
To display one of
the other 32 special characters OOH to 1FH, an ESCAPE character is sent
followed by a byte wi th the va lue of 60H added to the va lue of the
character to display.
The character will display in foreground or
background, whichever is the currently selected mode.
If follOWing the
ESCAPE character, the value EOR added to the value of the special
character is sent, the character will display in the opposite of the
currently selected mode.
The standard set of special characters is designed for use in
communication applications. These are shown on the table on the next
page.
An alternative set of graphic characters (see chart next page) can
be ordered by specifing the graphic character set with your order.
The 32 special characters may also be displayed with the alternate
attribute set by setting the eigth bit. For example the character 80H
will display as NU in the opposite attribute.

5-1

ASSOCIATE Technical Reference Manual

5. Vide 0 Ope ra tion

CHARGEN is a program that allows design of custom character sets. With
this program the user can create custom character set files that can then
be programmed into the character generator PROM.
Contact the Data
Technology marketing department for further information.
The 32 s.pecial characters are listed in thi;! following cable:

Table 5.1A

Character

DOH
01H
02H
03H

04H
aSH
06H
07H
08H
09H

OA
OB
DC
00

OE
OF
10
11

12
13

14
15
16

17
18
19

lA
IB
lC

IE
IF

Special Character display

Bytes to Transmit
HEX
DECIMAL
ESC 60H

ESC 61H
ESC 62H
ESC 63H
ESC 64H
ESC 6sH
ESC 66H
ESC 67H
ESC 68H
ESC 69H
ESC 6AH
ESC 6BH
ESC 6CH
ESC 60H
ESC 6EH
ESC 6FH
ESC 70H
ESC 7lH
ESC 72H
ESC 73H
ESC 74H
ESC 75H
ESC 76H
ESC 77H

ESC 78H
ESC 79H
ESC 7AH
ESC 7BH
ESC 7CH
ESC 70H
ESC 7EH
ESC 7FH

ESC
ESC
ESC
ESC

96
97
98
99

ESC 100
ESC 101
ESC 102
ESC 103
ESC 104
ESC 105
ESC 106

ESC 107

ESC 108
ESC 109
ESC 110
ESC III
ESC 112
ESC 113
ESC 114
ESC 115
ESC 116
ESC 117
ESC 118
ESC 119
ESC 120
ESC 121
ESC 122
ESC 123

ESC 124
ESC 125
ESC 126
ESC 127

Naue

NULL
SOH
STX
ETX

EOT
ENQ
ACK

BELL
BACKSPACE
HORIZONTAL TAB
LINE FEED
VERTICAL TAB
FORM FEED
CARRIAGE RETIIRN
SO
SI
DLE
DCl
DC2
DC3
DC4

NU
SH
Sx

EX
ET
EQ
AK

BL
BS

LF
VT
FF

So
S1
DL

D2
D3
D4

NAK

SYN

ETB

EB
CN

CAN

EM
SUB

ESC

GS
RS
US

The alternate graphics set is shown on the following page:

5-2

Standard
Display

,r---

J.
J.

4'"'.
:..
.....,
.~

(>1
~,

&;i
00

'-'-

---.'~-,

(D'

f-'
III

::J
,....

0
.~

....

tJ;I

it'

t'i;

"III

:;;

"III

"".

.,
;J

ro
?

CIl

:l>

....
0

,. .

·~I

,. ..,

(J( "\

;II
f-'

~
'1

II)

"'1/II
fC

"
V'

L.1

,....:
c.:.

.,~

I
L")

ASSOCIATE Technical Reference Manual

5.2

5. Vide a Ope ra tion

Control Sequences

The CPU sends commands to the CRT in the form of control sequences.
Control sequence may be in the form of single or multiple characters;
mult iple-characte r control seque nces begin wi th an ESCAPE cha racte r.
If
an invalid character follows the ESCAPE, both characters are ignored, and
the CRT resumes processing wi th the next characte r.
Single-Character Control Sequences

HEX
VALUE

S-4

DECIMAL ASCII
VALUE
NAME

Function in CRT
Sound a udi ble tone.•

BELL

Move cursor le ft one column. If the cursor is on
the first column of a row othe r than the top row, it
will move to the last column of the next higher row.

Move cursor down one row. If the cursor is on the
last row, the screen scrolls up one line.

Move the cursor right one column. If the cursor is
in the la st column of a row .athe r tha n the bot tom
row, it moves to the first column on the next lower
row.

Move cursor to the first column of the current row.

Unlock keyboard. This only functions if the keyboard
lock/unlock is enabled -~see below.

Lock keyboard. This only functions i f the keyboard
lock/unlock is enabled -- see below.

SUB

Clear screen and send cursor to home position.

ESC

Lead-in character fat multi-character control
sequence.

Send cursor to home position.

Move cursor up one row.
row, it does not move.

If the cursor is on the top

ASSOCIATE Technical Reference Manual

5. Vide 0 Ope ra tion

/·lulti-Character Control Seqtences
The ESCAPE lead-in character is not shown. A '(p)' indicates that the
sequence takes further characters as parameters.
An '(r)' indicates that
the CRT will re turn one or more cha racte rs to the host CPU in response to
the control seqtence.
HEX DECIMAL ASCII
VALUE VALUE
NAME

Function in CRT

Set Foreground. The characters that follow will
display at high intensity.

Clear screen from cursor position to end of screen.

Clear screen from cursor position to end of line.

Insert line at cursor position .. The line with the·
cursor and all lines below the cursor scroll down
one line. A b.lank line is inserted at the cursor
position and the cursor is positioned a t the beginning of the new line.

Delete
cursor
scroll
of the
of the
line.

Set Background. The characters that follow will
display at normal intensity.

(p)

line at cursor position. The line with the
is deleted and all lines below the cursor
up. A blank line is inserted at the bottom
screen. The cursor remains on the same line
screen, but moves to the beginning of the

Se t baud ra te.
The parameter is a hexadecimal
cha racte r (O-F) in ASCII) which selects the baud
ra te to be used be twee n the CRT a nd the CPU from the
following ta ble:
ASCII
Digit

0
1
2
3
4
5
6

7
8
9

I-t!x
Digit

30H
31H
32H
33H
34H
35H
36H
37H
38H
39H

Baud Rate
Se le cted
Top speed

48000
38400
28800
19200
9600
4800
2400
1200
300

5-5

ASSOCIATE Technical Reference

(

(p)

~nual

5. Vide 0 Ope ra tion

Set time of day. The- parameter is a string lJith
the following form:
HHMMSS
HHMM
HH
IJhere HH sets the hour, MM the minute, and S5 the
seconds. Each field is sent as two ASCII digits.
The is required as a delimiter and will not be
processed with its usual meaning.
For example. the parameter string (in ASCII) to set
10:30:15 a.m. is:
(103015
Any omitted parameter will be set to zero.
To have the Time of Day appea r on the scree n. three
separate functions must be done; Set Time of Day,
Turn on the 25th Line, a'nd Turn Clock Display on.
For example to se t and display the time to 10:30: 15
a .m. from t he Ope ra ti ng Syste m:
(103015
8
2

)

(p)

Se t Time of Day
Turn on 25t h Line

Turn on Clock Display

Write 25th line and turn it on.
string has the following form:

The parameter

(eighty characters>
or

The 25th line buffer is cleared to all spaces, and
then the characters are written into the buffer. If
more tha neigh ty cha ra cte rs are se n t wi t hout a
carriage return. the first eighty will be written
into the 25th line.
Any following cha racte rs will
be treated wi th their norma 1 significance, meaning
that they will probably be written to the screen at
the cursor position.

5-6

Turn off 25th line. The data is retained and may be
redisplayed by using the sequence to turn the 25th
line on

(p,r) Read Memory. This seq18 nee causes the CRT to re turn
to the host CPUa string'of hexadecimal characters
in ASCII representing the contents of
me mory
starting at the requested address. Thus for each

ASSOCIATE Technical Feference Manual

S. Vide 0 Ope ra tion

byte of memory data requested two characters are
returned.
The first character of each pair
re presents the most significant nybble of each byte.
The pa rame te r string 1s:

The "address l l consists of four ASCII hexadecimal
characters representing 2 bytes of address; the low
order address byte, most significant nybble first.
The "length" isa single ASCII hexadecimal character
requesting the number of bytes to be returned. If

the character is

(0)

sixteen bytes are read.

The string returned
following form:

the

host CPU has the

whe re "addre ss" consists of four ASCII hexadecimal
characters representing 2 bytes of address; the low
orde r address, most significant nibble first.
The "data" consists of pairs of ASCII hexadecimal
characters, with each pair representing 1 byte of
date. The first character of each pair represents
the most significant nybble of each byte.
Memory write continues until the CRT receives a nonHEX cha racte r.

(p)

Transfer to address.
form:

The parameter string has the

where "address" is the same as for the memory read
and me mory write sequence s.
The CRT then calls to the address specified.
user may use a RET instruction to return.

(r)

The

Read cursor address.
The CRT sends three ASCII
characters to the host CPU:

5-7

ASSOCIATE Technical Reference Manual

5. Video Operation

The relationship betTNeen the sent characters and the
value of the position is as follows:
row
• - 20R
where all values are bytes in hex.
2F

Reset soft keys. This sequence resets all soft keys
to the ir de fault seque nce s.

Enable keyboard lock/unlock.
This sequence enable s
the ke yboard lock and unlock seque nces (ASCI I
cha racte rs 50 and 5 I) a nd unlocks the ke yboa rd.
The CRT is initialized with the keyboard unlocked
and the keyboard lock disabled. The keyboard will
not lock un til an e na ble ke yboa rd lock se que nee 1 s
.sent to the CRT, followed by a lock keyboard
sequence.

Disable keyboard lOCk/unlock.
This sequence
disable s the ke yboa rd lock a nd unlock seque nce s
(A SCI I c ha r act e r s 50 and 5 I) and un 1 0 c k s the
keyboard.

Clock display on. The clock is displayed on the
25th line, at the right.
The 2Sth line must be
enabled using the sequence 8 or .

Clock display off. The clock display is turned off.
The rest of the 25th U ne is unaffected.

(r)

Read light pen.
The last CRT display address
sensed by the light pen is returned in a string of
the form
xxwwzzyy which indicates how many characters are to
be read back. If is zero, sixteen bytes
are returned.

(p) Position cursor.
following form:

The parameter string has the

and - row + 20H

Disables the "toggle" function of the RST key.

,26402520

Re-enables the "toggle" function of the RST key.

5-9

ASSOCIATE Technical Reference Manual

Vide 0 Ope ra tion

(ESC), 1940xx(CR)

Changes the number of minutes until the screen goes
blank to xx (value in hexadecimal).

(ESC),3E40xx(CR>

Sets the minimum time between characters sent to main
CPU from video board to xx msec. This is implemented
on CRT PROM 1.8 and la te r.

(ESC),3F4001(CR)

Disables Auto-~wl1ne function.
This is imple1l8nted on CRT PROM 1.8 and later.

(ESC>,OOl 12 lOA09220070COC9(CR>(ESC>-OO 1 1 Turns off cursor blink. This is
an example of a call ,to a program to a program in the
CRT RAM •.
(E5C>-oOOO
5.3

Comple tely resets video board by forcing CRT processor
to branch to location 2JI! roo

Use of Soft Ke ys

The soft (or programmable) keys are the nume ric pad keys and the top row
of keys (FO-F9, cursor movement and HOME, but not R5T). These are the
keys whose transmitted code s may be modified.

"Soft" keys 8Inerate default codes, but they may be individually "loaded"
with a variable-length string of characters. After a soft key has been
loaded, whenever that key is depressed, the CRT sends to the host CPU the
string that was loaded into that key, as if the operator had entered the
string of characters.
These keys may be loaded with the KEYLOADER Programmable Function Key
program (PFK) or as de scribed below.
Each soft key can be loaded with up to four chara,cter strings.
To
illustrate, i f four strings were loaded into the soft key Fa, A string may
be selected by entering either Fa, shift-Fa, ctrl-FO, or ctrl-shift-FO.
These four combinations are called the four "levels" of the soft key.
Or
a soft key may be immune to shift and cntl by loading the same character
string into one or more levels of that key. As will be explained later,
in this case, only one copy of the string needs to exi st in the RAM
storage of the CRT.
All the soft keys have a standard default code which is a single character
with the high order bit set. For example, the default code for each
numeric pad (no control, no shift) key is the character shown on the
key top. The default code for the cursor control keys is the character
that causes the cursor to mo,.. in the direction shown on the key top. See
the Table 6.1 for the default codes. fQr each soft key.
Each level of each soft key generates a specific code between 0 and 127,
called the "soft key code." This code, the value listed in Table 6.1,
minus 80H, is used to index into the soft l,COI00811(CR)
(se t soft ke y pointe r)
(ESC>,08110480(CR)
(write soft key stri ng)

Example 2:

Program
generate

Function Key Cntl-FO and ctrl-shift-FO to both
the string 'RUN XYZ(CR>'.

The soft key pointer for ctrl-FO is at 1040H.

The soft key pointer for ctrl-shift-FO is at 1000H.
The soft key string is 52564E2058595AODBO.
Assull2 tre loea tion of the soft key string will be 1100H.
Then the following seque nee will se t the keys:
(ESC>,40100011(CR>
(set soft key pointer for
ctrl-FO)
(ESC>,00100011(CR>
(se t soft key pointe r for
ctrl-shift-FO)
(ESC> .00 1152564E20585 9SAOD80(CR> (write softke y s tri ng)
Example 3: Program Function Key FO is to generate a "0 (04H).
Shift-FO is to generate "W"D (1704H).
The soft key pointer for FO is at 10COH.
The soft key pointe r for shift-FO is at 1080H.
The soft key string for FO is 0480.
TIe soft key string for shift-FO is 170480.
Since the string for FO is a right-hand substring of the
string for shift-FO, the two strings can share memory.
Assume the' location of the soft key string for shift-FO will

5-11

ASSOCIATE Technical Peference Manual

5 • Vide 0 Op! ra tion

be 1107H.
The location of the soft key string for FO will be 1108H.
Then the following sequence will set the keys:
(set soft key pointer for Fa)

(se t soft key pointe r for shif.t-FO)

,07l1170480(CR>
(write soft key string)
Table 5.2
Key

Normal

SOFT KEY PO INTER CHART
Shift

Ctrl

Ctrl-Shift

lOCO
10C2
10C4
10C6
lOC8

1080
1082
1084
1086
1088

1040
1042
1044
1046
1048

1000
1002
1004
1006
1008

10CA
10CC
10CE
lODE
1002

108A
108C
108E
109E
1092

104A
104C
104E
lOSE
1052

100A
lOOC
100E
101E
1012

1090
1094
1096
1098
109C

1050
1054
10:36
1058
10lC

1000
1004
1006
1008
10DC

Function keys:
Fn
Fn
Fn
Fn
Fn

key
key
key
key
key

0
1
2
3
4

Fn keyS

Fn
Fn
Fn
Fn

key
key
key
key

6
7
8
9

Cursor movement keys:
Back
Down
Up
left
Home
Numeric

1010
1014
1016
1018
10:3C
~

keys:

0
1
2
:3
4

1060
1062
1064
1066
1068

10AO
10A2
10A4
10A6
10A8

10EO
10E2
10E4
10E6
.10E8

1020
1022
1024
1026
1028

106A
106C
106E
1070
1072

10M
lOAC
lOA[
lOBO
10B2

10EA
10EC
10EE
10FO
10F2

IOU
102C
102E
10:30
10:32

10BA
10B6
10BC
109A
10B4
10B8

10FA
10F6
lOFC
10:3A
10F4
10F8

l07A
1076
107C
10DA
1034
10:38

7
8
9

10SA
1056
10SC
ENTER
lOLA
"uncle r-O" 1074
"under-ENTER" 1078

5-12

ASSOCIATE Te chnical Fe fe re nce Ha nua 1

5.4

5. Vide 0 Ope ra tion

CRT Memory Allocation

The following data areas are defined:
HEX
ADDRESS

NAME

USAGE CRT Prom Ve rston II
Sof~, Bey _pointe r a rea.
User'area.
Buffer for 25th-line.
CPU out queue 'control block.
Beyboard in queue control block.

0021H-0023H
1000H-10FFH
1100H-DABH
1 3BOH-l3FFH
4000H-4005H
4006H-400BH

Column numbe r of cursor (0 •• 79).
Row number of cursor (0 •• 23).
Intensity flag. 80H. Normal intensity,
OON • High intensity.
Absolute cursor addre ss
last light pen address sensed
Current start of screen display area
, Relative cursor address-

400CH
400DH
400EH

XPOS
YPOS
INTEN

400FH-4010H
4013H-4014H
4011H-4012H
4013H-4014H

ABSIO
LITEPEN
CRTBAS
CRSPO.s

4019H
4021H
4022H
4023H
402FH

TIMEOFF : Number of minutes till screen blank
L25ENAB
Non-ze ro enable s 25th line
CLOCKFLAG Non-zero enables clock display
KBLFLAG
Non-ze ro locks Ie yboa rd
HOURS
Hours counte r

4030H
4031H
4032H
4036H-403DH

MINS
SECS
C60THS
UPCLOCK

5.5

Minutes counter
Seconds counte r
60t hs of a se conci coun te r
ASCII unpacked clock field HH:MM:SS

CRT PROM Entry Points

The following entry points into the PROM code are de fined for down-loaded
progra ms to use:
HEX ADDR

Function pe rformed

07ESH

Fills memory starting at HL with the value in 'B', for as
many bytes as specified in 'C'.
If the value in 'c' is
ze ro, 256 bytes will be filled.

07E8H

&!t cursor position from relative cursor position in HL.

07EBH

Set cursor pOSition from x and y values in XPOS and YPOS.
(x • column 0 •• 79; y . row 1) •• 23)

07EEH

Put character in 'e' into CRT memory at cursor location and
advance cursor.

5-13

ASSOCIATE Technical Fefe rence Mlnual

5-14

5. Vide 0 Ope ra tion

07FlH

Send character in
'c' to host as·two ASCII bytes
representing a hex value.

07F4H

Returns t in 'C't the hex value of the hexascii digit in
'C'. C-latch set if not valid hex digit.

07F7H

Put characte r in 'e' into output queue.

07FAH

Return with character in 'c' from queue given by HL.
latch is set i f no characters were in queue.

07FDH

Branch, using value in 'A' as an index,
sequences branch table.

Z-

into control

ASCII CODe CHART
11

S
13

NUL

DL.E

SOH

STX

ETX

EOT

ENQ

ACK

BEL

DC2

•

SYN

23
I

•

CAN

(

·s
t,.

t
117

18'

••

W
72

tIS

u
11 •

1ft

tf3

IIELL

.
c

11.

113

112

T
II

R
17

:It

ETB

1
LOW Y"
XLOY

1
1

4
37

'5'

.LOWX

NAK

••

2
35

.
S
1

DC4

DC3 "

DC1

HIGH X & y
GRAPHIC INPUT

CONTROL
It

"""

,,
,
"

" " fJ

lZf

x
r

BACKSPACe

I1
1

LF "

SUB

VT "

ESC

RETURN

1-.

r~ I

RS
IS

··
·,

J
5•

[

N
13

m
14

123

{

;1.

124

•
~

11'

125

}

126
~

lr.\r
IN!I:

]

122

....

j .., ;'

121

Z
7S

>
?

Y
74

.27

)
2.

127
RUDOUT

(DELI

Nute thllt clllu:r "LOY" column may be used lor thc XLOY byte. sInce bll 5 Is not used.

S-IG"

ASSOCIATE Technical Peference Manual

6. Keyboa I'd

Chapte I' 6
KEYBOARD

The ASSOCIATE keyboard is a selectric style keyboard with .enhancements.
It interfaces to the video processor board; for details (see Section 4.2,
"Keyboard I/O").
Two keys have "local" functions which cause an immediate operation by the
CRT processor. These keys are:
Local clear (control-delete), clears the CRT screen without
affecting the host CPU. The 25th line remains unchanged.
Local clear (control-shift-dele te), clears the CRT screen and
the 25th line. The clock display remains unchanged.
Toggle key (RST, shift-RST, and control-RST) stops/starts the
transfer of data to the CPU by toggling the Clear to Send (CTS)
to the CPU.
Reset host key (Control-Shift-RST) unconditionally resets the
host CPU.
The following features are also standard with the keyboard:
1)

Redefinition of Keyboard - Keyboard PROM can be changed to
change the codes generated by keyboard characters.

Electro-Capacitive Keyboard - The ASSOCIATE has an electrocapacitive keyboard •. No mechanical contact is required to enter
a character; a change of capacitance is detected on the
underside of the board and that enters the character.
Pressing
a key changes the capacitance.
All capacitive sensing is
handled by a keyboard controller on the keyboard circuit board.

Repeat Functions - When a key is pressed the character is sent
immediately to the video processor. If the key is held down for
longer than 1/2 second the character is repeated at the rate of
10 cha ra cte rs pe r second.

CRT 25th Line - The CRT"s 25th line can be downloaded in order
to create prompts directly above the keyboard.

Selectric Format
selectric forma t.

Accounting Style Numeric Pad - The keyboard has an accounting
style numeric pad with double wide zero and an ENTER key (the
default value is the same as RETURN). The keypad keys are soft
keys that can be downloaded from the host CPU as de scribed in
Cha pte I' S.

- The

ASSOCIATE Keyboard

is a

standard

6-1

· Ma nual
ASSOCIATE Te chnical Re fe re nee
7)

Special Purpose ¥ays - Several special purpose keys, such as
escape, tilde, carat, and insert, are on the keyboard. All 128
ASCII codes (0 to 7FH) can be generated from the keyboard.

Cap Lock Key - The keyboard has a CAP LOCK key. The CAP LOCK
causes all alpha characters to be transmitted as capital
letters. It does not affect operation of the shift for nonalpha characte rs.
.

Function
Keys - Four separate levels are possible on the
function keys:
NORMAL, SHIFT, CONTROL, and SHIFT CONTROL.
Addi tional functions can be downloaded from the host CPU as
de scd bed in Cha pte r 5.

10)

Cursor Control - There are four cursor control keys (LEFT,
RICHT, UP, DOWN) plus a HOME key. Cursor control keys do not
alter information, they reposition the cursor in the
corresponding manner. HOME sends the cursor to the upper left
corner of the screen. These five function keys can also be down
loaded from tl'8 host CPU.

The table on the following page defines the eight standard
for each key in terms of the ASCII code generated:

6-2

6. ¥ayboard

combinations

ASSOCIATE Technical Re fe re nce Ma nua 1
Key

•

]

{
}

Number

Normal

Shift

Ctrl

Ctrl-Shift

2D
3D
5B
5D
3B

SF
2B
7B
7D
5C

.3D
5B
ID
3B

IF
2B
7B
7D
lC

3A
2C

22
3C
3E
3F

3A
2C
2E
2F

22
3C
3E
3F

CO
C1
C2

AO
Al
A2

80
81
82
83
84

C5
C6
C7
CF
C9

31
49
50
66

67
82
83
84

<
>
?

6. Keyboard

Function keys:
Fn key
key
Fn key
Fn key
Fn key

0
1
2
3
4

1
2
3
4
5

EO
El
E2
E3
E4

Fn
Fn
Fn
Fn

5
6
7
8
9

8
9
10

E5
E6
E7
EF
E9

key
key
key
key
Fn key

85
86
87
8F
89

A6
A7
AF

Cursor move me nt ke ys:
Back
Down

Left

Home
Nume ric
0

1
2
3
4

13
14
15
16
17

.e!!!.

E8
EA

CB
CC
CE

9B
AC
8E

0·

90
91
92
93
94

EC
EE

ke ys:

86
69
70..
71

5
6
7
8
9

36
54
88

ENTER

88
8A
8B
8C
9E

53
34

.,' n.

j'unde r-O" ·'87"under-~N'l'ERtI 89

80
B1
82
B3
84

01
·. .·02
03
D4

FO
F1
F2
F3
F4

BS
B6
B7
B8
89

OS
06
07
08
09

FS
F6
F7
F8
F9

DO
DB
DE

AB
AE
8D
BA
BC

CD
DA

FB
FE
90
FA

95
96
97
98
99
BD
BB'
BE
ED
9A
9C

ASS:OC IA TE Te ch n1 ca I Fe fe re nce : I1l

nua I

7. Monitor

Chapter 7
PROM MONITOR
This section contains an overall description of the PROM Monitor and how
it functions in the ASSOCIATE. At powe l' up, 01' RESET, RAM is disabled and
the system begins execution in the PROM at location O.
The first
instruction is a jump into the FaOO range and the second is an OUT DOH
enabling RAM thereby entering its normal operating configuration.
Entry
into the PROM monitor disables the interrupts.
The System Monitor will
t,hen attempt to boot the Disk Operating System. If the Disk Operating
System cannot be loaded. a second RESET will take the Monitor to the
command level.
To boot the Disk Operating System from Drive A, type the monitor command
After boot to disk, software can be used to disable PROM so that a
full 65K of RAM will be available (see 3.2.1 Memory and 4.11 Status and
Control for further detail). Return to the PROM Monitor from the CP/M
Disk Operating system is accomplished by executing the program MNTR, which
enables PROM and returns control to the PROM Monitor.

"A".

The following de scription of functions available in the PROM Monitor is in
two parts:
first, a brief introduction and complete listing of operator
commands available through the PROM Monitor are presented; second,
functions used by Monitor commands and also available to the user are
described.

7.1

PROM Monitor Operator Commands

The PROM Monitor Operator Commands encompass manY,useful functions for
working with memory and I/O. The commands perform functions such as
testing, displaying, and changing memory, calculations involving
addresses, performing basic I/O, and examining and changing registers.
These commands are de signed to give use rs a great deal of powe I' in working
with the processor at a machine level. The following table summarizes
ope ra tor comma nds availa,ble through the PROM Monitor:

7-1

7. Monitor

ASSOCIATE Technical Reference Manual
SumllB ry of Commnds
ComllBnd

Function

Boot Disk Operating System
Drive A(bottom)
Boot Disk Ope rating System
Drive B( top)
Call Exte rna I Subroutine
Display M!mory in Hlx and ASCII
Fill Memory
Co to Addre ss
(optionally se t breakpoints)
Compute Hex Sum and D1ffe rence
Calcula te Check Value for.
Memory Range (to de te rmine
i f amory accidentally modified)
Move a Block of 1III!mory
Calculate Relative Offset
Make the ASSOCIATE a Te rminal
Que ry I/O
Read a Hex Tape
Display/Alter Memory
Test Mamory (de structive)
~rify One Memory Block Against Anothe r
Examine/Modify CPU Registers
Search Memory for String

C
D
F
G
H
K

o
P
Q

R
S
T
V
X
Y

Page

If the PROM Monitor is entered at startup or RESET, the System attempts to
load the Disk Opera-ting System. If the DOS is not-succe ssfullr loaded a
second RESET will give control to the Monitor command level. The message
"GNAT System 10 Monitor Ver X,f' will be displayed followed by the Monitor
prompt "?". Afte r exe cuting each ope ra tor comma nd, wi th the exce ption of
A (Boot to Disk) and, sometimes C (Go to), the prompt character is
displayed. PROM Monitor Commands can be interrupted, to abort execution,
by issuing a Control C. When Control C interrupts the execution of..[ , [ ,,
This command displays the contents of memory beginning at start-address
and ending with the end-address.
M:!mory is displayed in hexadecimal and
ASCII with 16 bytes per CRT line. The starting location is displayed in
hexadecimal at the beginning of each line.
F
Fill
Syntax:

~mory

F ] [ , ]]
This command allows transfer to another program while retaining some

7-3

ASSOCIATE Technical Reference Manual

7. Monitor

Monitor control by set.ting breakpoints. A simple transfer to another
program is executed if only transfer-address is specified on the command
line. To set breakpoints, one or two addresses are added to the command.
Note that this feature is softwa re controlled, and breakpoints must occur
on instruction OP-CODE in RAM.
When a breakpoint is reached, the
breakpoint address is printed and a Monitor prompt is give n. Execution of
the program can be continued byentering G or G, if another
breakpoint is to be implemented. The breakpoint is implemented by
insertion of a RST7 instruction at the desired break location. After
encountering the breakpoint the original instruction is restored. The
processor status (contents of all registers) is saved in the monitor work
space area.
H
Compute I9x Sum and Diffe rence
Syntax:
H,
This command computes and displays the sum (start-number + end-number) and
difference (start-number - end-number) of two hexadecimal numbers, where
the numbers range between OOOOH and FFFFH. If start-number is less than
end-numbe r, the result is equal to start-numbe r +lOOOOH - end-numbe r.
K
Calculate Check Value for M!mory Range
Syntax:
K ,
This command computes and prints a 16-bit check value for a me mary range:
it is useful for determining if a memory range has been accidentally
modified.
The check value is calculated by the CRC equation:
g(x)-X(16)+X(12)+X(S)+X.
M
Move a Block of M!mory
Syn tax: M,,
This command moves the contents of a block of memory beginning at startaddress and ending at. end-addre.ss to another block of memory starting. a~:
destination-address. Caution should be used with this command in order to
prevent the unintentional destruction of memory locations which should
remain unchanged. Note that wrap around from FFFFH to OOOOH takes place
if the source or destination block: of.me1l!o.ry goes past FFFFH.
...
.\

Calculate i\!lative Offset
Syntax:
O(jump-address> , .

This command calculates offset Jor relative jump instructions. Jump~
address is the address of the jump instruction, and destination-address . :is.
the address of the instruction ju"mped to. If destination is out of tll~;
2,56 byte range ,an ''XX'' will be printed.

7-4

.<\$SOCIATE Technical Reference

~nual

7. Monitor

.1"

Port Echo
S:1nt.ax:
P(se rial-port> ,

1'he·c:.ASSOCIATE becomes a terminal with connection through the MODEM, LIST,
or N"ETWORK I/O PORT. The CTRL-SHIFT-RST KEY will cause an exit to the
Monitor. For
QI J

This command reads check-summed hex files in the normal Intel format. A
bias can be added, which will cause the object code to be placed in a
location other than its intended execution location. The bias is added to
what would have been the normal loading location and wUl wraparound to
enable loading any program anywhere in memory. If non zero transfer
address is received, the monitor transfers control directly to the
program.
S
Display / Alte r li!mory
Syntax:
S
This command displays, and allows modification of, memory on a byte-bybyte basis. The byte at the start-address is displayed in hexadecimal; if
the value of start-address location is to be changed, the· new value is
entered followed bya space, otherwise entering onlya space will cause
display of the hexadecimal value at the next location. To terminate
execution of this command, enter a RETURN. The system adds a carriage

7-5

ASSOCIATE Te chnical Re fe re nce Ma nua I

7. Monitor

return and line feed before displaying continuation locations with address
ending wi th a ze ro or eight; the present address location is printed afte r
each system issued carriage return and line feed.
T
Te·st Memory (t'estructive)
Syntax:
T,
This command uses a very fast pseudo-binary sequence generator with a
period of 256 bytes to test memory. The period is relatively prime to 256
and, thus, provides a good test of pattern sensitivity. Note that each
number in. the range 0-255 is generated by the algorithm; therefore. each
bit in the range is tested to see if both ze ro and one bits can be written
into it. Error information is displayed in the form of an address and bit
number. The· memory chip with the location which failed the test can be
quickly determined by reference to the appropriate schematic.
V
Ve rify memory
Syntax: .
V , ,
This command compares the contents of the block of memory delineated by
start-address and end-address to the block of me mory beginning at compa readdress; wraparound takes place if the compared addresses exceed FFFFH.
Differences in the contents of the two memory blocks are reported in the
form of address and the contents of the two locations.
X
Examine/Modify CPU Registe rs
Syntax:
-Xl'] []
This command disp1.8ystne' contents of the CPU tegisters; i f thereglstername is specified, contents of the register can be changed (or not) by
spe c1fying the ne w conte nts or a space. To di splay the norma 1 syste m
status enter only an X. To display the additional zao registers, enter
Jr. Single "prime" registe rs may be examined and modified in the same way
as w~th "unprimed" registe rs de scribed above.

y
Search ~mory
Syntax:
Y
This command searches all memory starting at location zero for the byte
string specified by search-string. Hex characters ate separated by commas
in specifying the search-string and up to 255 may be indicated. The
starting address of each byte string found to be identical to searchstring is displayed by the command.
7.2

PROM Monitor Entry Points

The following fun~tions ate available to user programs andean simpltti
the handling ()f I/O fi:'om systetn to syscem; they are a !so used by PR.O~
Monitor operator commands. The ,ful\ctions are accessed by calling to' ffje
loca'tion spec:ified 1n the Assembly lis'~ing.,
Whatever the cur,rently

7-6

ASSOCIATE Te chnical Re fe re nce Ha nua 1

7. Honi tor

assigned device, these functions will perform the specified I/O operation
and return to the calling program. Register conventions are as follows
for any input or output device: the character to be output is in the C
register and the return character will be in the A register after input or
output. rre functions are:

ADDRESS
F803
F806
F809
F80C
F80F
F812
F8lS
F818
F8lE
F824
F826
F829
F82C

NAME

CI
RI
CO
PO
LO
CSTS
IOCHK
IOSET
USET
DATE
TRAP

PRINT
BOOT

FUNCTION

PARAMETER

"A" RETURNED WITH CHAR
CONSOLE INPUT
READER INPUT
"A" RETURNED WITH CHAR
"C" OUTPUT TO CONSOLE
CONSOLE OUTPUT
PUNCH OUTPUT
" C" OUTPUT TO PUNCH
LIST OUTPUT
"c" OUTPUT TO LIST
"A" RETURNED WITH STATUS
CONSOLE STATUS
I/O CHECK
"A" RETURNED WITH IOBYTE
I/O SET
"c" PUT INTO IOBYTE LOCATION
INITIALIZE I/O
NONE
DATE CODE ID
NONE
RESTART BREAKPOINT
PRINT ON CONSOLE PRINT FROM DE TILL 00 FOUND
NONE
LOAD FIRST SECTOR AND RUN

7-7

ASSOCIATE Technical Reference Mlnual

8. Se rvi ce Proce dure s

Chapte r 8

SERVICE PROCEDURES

This chapter describesthe service procedures for troubleshooting and
testing the ASSOCIATE compute r family. This informa tion is intended only
for tre technically oriented and experienced service parson.
You will find that this manual will give you most of the information you
need to troubleshoot and repair the ASSOCIATE on a module basis. Repairing the various modules is a Depot function and should be referred to your
nearest Depot Repair facility. Field repair should be limited to replaceme nt of the module s only.
Ope ration of the machine will give you most of the initial clues you need
to troubleshoot problems. Carefully note any symptoms. Try to duplicate
the problem, using the ope ra tions which we re in progress when trouble wa s
first noted. Many problems can be traced to imprope r ope ration or fa ulty
software/media. A list of potential troubles and the appropriate actions
follows.
SOME THINGS TO REMEMBER

*****************************************************************
***
CAUTION
***
***
r:a. nge rous vol ta ge s !.E!. pre se n t :!:!!. !h!! ~
** *
***
It is advised that pe rsonnel working inside of the
***
*** ASSOCIATE or any electrical equipment should NOT wear ***
***
me tal je we lry or wa tches.
***
***
Dalot unscrew metal parts,disconnect cable s,
***
***
orremove components wi th the powe ron.
***
*****************************************************************
Obse rve ca ble conne ct or pola rity-The pin 1 arrows on jack and cable connector must align.
HOW TO USE THE TROUBLESHOOTING CHART TO SOLVE PROBLEMS
Before consulting the TROUBLESHOOTING CHART, attempt to verbalize the
difficulty you have encountered in a meaningful sentence. For example,
"It doesn't work." is not nearly as descriptive as, "Fan does not run and
video display is dark." The first statement isn't ve ry helpful but the
second statement might have a simple solution as: "Is the unit plugged
into a working 120 VAC outlet?" or "Is the AC Line fuse blown?"
Now that you have a description of the problem, see column 1 of the
TROUBLESHOOTING CHART for a match. Column 2 will explain the possible
failure and column 3 will tell you what to check.
If you need furthe r i nforma tion afte r the TROUBLES.HOOTING CHART ha s
directed you to a possible solution, see the column 4 for a FIGure or
SECtion number to refer you more tests or the probable cause of the
trouble.

8-1

~ference

ASSOCIATE Technical

I-lanual

8. Service Procedures

ASSOCIATE TROUBLESHOOTING CHECK-LIST

PROBLEM DESCRIPTION

PROBABLE CAUSE

REPAIR ACTION

~!Q

I
I

Continuous beep

Keys beep when pushed
Cooling fan inaudible

I
I
I
I
I
I
I
I
I

Sticking keyboard
key
Video Processor
failure

Fsfit jamaed key
Ad jus t ke yboa rd
Replace 1005 pcb

Ille gal ope ra tion
BIOS fa ilure

Che ck Ope r. M! n.
Run diagnostics

I No 120 VAC pOtNe r
I Blown fuse

I Fan lmplugged/bad

SEC 8.2
SEC 8.3.1

Plug unit in
Che ck poW! r fuse
Check connection
or re place

SEC 8.3

No disk drive noise
but fan is OK

Auto poW! r-ciown
Bad diske tte
Not rebooting "A"
Disk drive failure
POW! r Supply fail

30 sec inactivity
Fsboot another 01'2
CTRL-SHFT-RESET
Replace drive assy
Re place supply

CP/M
CP/M
CP/M
SEC 8.3.2

Unusual noise

Bad fa n bea r1 ng
Disk drive fail
or diskette fail
POW! r supply fail

Re place fan
POWER DOWN NOW!!I
and re place
adjust or replace

I
I
I
I
I
I
I
Adjust pow. supply I
Fan working?
I
Run Disk tests
I
Re place 1005 boa rd I
I
Ole ck Ope r. Ml nua 11
Clean/replace kybdl
Run Disk Te sts
I
Replace 1005 boardl
I
Run TPAT test
I
Replace 1005 board I
Adjust it 10tNe r
I
I
Run HTEST
I
Re place 1000 board t

SEC 8.3

Cha racte r dot fade
or twinkle

Incorrect char appears

Imprope r boldface
or high intensity
raste r
Typ!d char app!ars in
more than OD! place
a t the salll! tine
Typed char appears in
more than OD! place
a t the same tine

8-2

POtNe r fa ilure
Unit is too hot
Vide a proce ss fa 11
Imprope r SHFT/CTRL
Sticking kybd keys
I CPU fa i lure
I Vide 0 proce ss fail
I
I Vide 0 proce ss fa il
I
I Brightness too high
I
I ~mory failure on
I lIBin CPU board
I
I '
I ~mory failure on
I vide 0 boa rd
I

I
t
I

Run TCRT
Re place 1005 boardt

SEC 8.3.2

DEPOT*
Sys disk
SEC 8.3.1
SEC 8.2
Sys disk
SEC 8.3.1
Sys disk
SEC 8.3.1
Below CRT
Monitor
SEC 8.1
Sys Disk
SEC 8.3.1

AS SOC lATE Te chnica I Re fe re nce }la. nua I

PROBLEM DESCRIPTION
Missing characters
inoperative keys

Garbage displayed

PROBABLE CAUSE

8. Se rvi ce Procedure s

REPAIR ACTION

1
1

Correct ~ Sys.?1 Check diskette
1 Keyboard/video fail 1 Replace kybd/l0051
1 CPU non-operative
I Video process fail
1 PoW! r Supply fail
I

1 Replace 1000 boardl
1 Replace 1005 boardl
1 Adjust/replace
1
I
I

Bad raste r. stre tched I CRT out of adjust 1 Adjust/Re place
I
compressed. deformed 1 Video process fail 1 Run TPAT test
1
l i R e place 1005 boa rd I
or .rolling chars.
1 PoW! r supply fail 1 Adjust/replace
1

Sc ree n bla nk

I Uni t turned on?
I Plug i nit urn on
I
1 Brightness too low I Adjust brighter
I
1 Video process fail I Run TPAT te st
1
I
I Replace 1005 board I
I CPU inoperative
I Replace 1000 boardl
1 PoW!r Supply fail
I Adjust/replace
1

I
1
I
I
Cursor not present
I Does keyboard work? YES? Bad Diskette
(cursor might be turned 1
Run MTEST
off by softlo8 re - try
I
NO? Bad 1005 or
to reboot)
I
1000 boa rds
I
1

Cursor doe s not blink

Keys don't respond

Si ngle ke y fa 11s

REFER TO

I
I
I
I

I
I

CP/M
SEC 2
SEC 8.1
SEC 8.3.1
SEC 8.4.2
DEPOT*
DEPOT*
Sys di sk
SEC 8.3.1
SEC 8.3.2
DEPOT*
CP/M
Below CRT
Sys disk
SEC 8.3.1
SEC 8.1
SEC 8.3.1
DEPOT*

CP/M
Monitor
SEC 8.3.1
SEC 8.1
DEPOT*

I Doe s ke yboa rd wo rk?
I

YE S? Run MTEST
NO? Failed 1005

I
1

I
-I

I
I
I
1

During a prog. run?
Try running tests
Doe s un! t boot?
Run another program
Fa ile d CPU/Vide 0

Stri ke CNTL-S once
Pe rform disk test
Try re booti ng
Bad diske tte
Re place 1005/1000

Run anotlv!r prog.
Mamory fail
Sticking key
CPU failure
Video process fail
Keyboard failure

Bad diskette
Run MTEST
Clea n/re place
Run Disk tests
Re place
Replace

Key held down or
sticking
Video process fail

Auto REPEAT
I
Clea n/re place
I
Run Disk te sts
I
Fe place 1005 boardl

I
I

Moni tor
SEC 8.3.1

CP/M
Sys di sk
CP/M
CP/M
SEC 2

I
I
1
1

I
I

Moni tor
SEC 8.2
Sys disk
SEC 8.3.1
SEC 8.2

Mult iple ke ystroke s

SEC 8.2
Sys di sk
SEC 8.3.1

8-3

ASSOCIATE Te chn1cal Re fe re nce
8.2

~fanual

8. Se rvice Procedures

Diagnostics

The following tests are used to check out various components. Errors are
indicated by the audible tone and asterisks at the beginning of the
displayed error line.
Upon error the programs will wait for' an operator
input before proceeding. The tests are generally invoked by entering the
name of the test at the System level followed by a Carriage Return.
Prompts will ask for essential user-supplied information.
8.2.1

TSERIAL, TRS232 - Serial Port Test

These two programs perform the same tests on serial ports; they should be
utilized whenever a user wants to check the correct action of a serial
port--ports 60H, 70H or 72H. TSERIAL automatically tests the indicated
ports. TRS232 tests individual ports as directed by the operator. In
order to use these tests, a loop-back plug with the following pins
connected together is required:

2 - 3,
4 - 5,
6 - 20

Txra ta to Rxra ta
RTS to CTS
DSR to DTR (CD)

The test is invoked from CP/M by the following:

AO)TRS232

AO)TSERlAL

TRS232 will inquire for the numbe r:
TEST PORT /I IN HEX If tre port is error free:

BAUD RATE • xxx
NO DATA ERRORS DETECTED
PORT 70 TEST COMPLETE
To return to CP/M, reply to the port II query with any character
which is not a hex numbe r.
Error nessages which my appear include:

***
***
***
***
***

8-4

CD/DSR not going on
CD/DSR not going off
CTS not going on
CTS not going off
Time out error (possibly

non~x1stent

port)

ASSOCIATE Technical Peference Manual

8.2.2

8. S! rvi ce Proce dure s

TPIO

TPIO tests the the operation of the Parallel I/O port. For proper
operation, !PIO must have the TFX003 test fixture installed in the 50-pin
parallel 'connector on the back panel.
The test fixture is a parallel loopback plug with the following pins
connecte d:

I I I I I I

The PIO te st is invoked by:

AO>TPIO
The program will re spond wi th

TPIO - TEST PIO VI.OO as of 29-Mirch-80
Te st Comple te
or give one of the following errors:

***
***
***

Output error - (port). rata • ww, Port II xx • yy. Error - zz
Input error - (port). rata • ww, Port # xx • yy. Error" zz
Tiueout, data-vv, Port ww (Output)-xx, Port yy (Input)-zz

8.2.3

TAPU,T9512

- Arithme tic Processor Te st

These programs test the optional arithme tic proce ssor--AM951Ior AM9512.
TAPU rePeatedly tests the AM9511 operations of: multiply, divide, SIN,
ARCTANGENT, exponentiation, and power. T9512 repeatedly tests of the
operations of add, subtract, multiply, and divide. The results of each
function is compared with the expected result stored in the program.
Any
error is indicated by a printout of actual result and anticipated result.

Se tup re quire s tha t the
installed. To invoke:

AM9511 or. AM9512 and re qui red

jumpe rs

AO>TAPU
or
AO>T9512
Type any character to. abort the test.
result from this test:

***

9511 (function) e rror- xxxxxxxx

The following error message may

expe ctedresult-yyyyyyyy

8-5

ASSOCIATE Technical Reference Manual

8.2.4

TBAUD

8. Se rvi ce Procedure s

- Baud Rate Generator Test

This diagnostic tests each port through all 16 possible baud rates.
A
software timing loop measures the time between sending successive
characters at a given baud rate and compares that value with an expected
value, giving a resolution of about 35 usec. Any difference is an error.
If the test fails, port number, baud rate, expected result, and actual
result are displayed. The test should be ['un when errors are detected in
t ryi ng to se t ba ud ra te.
Se tup require s se rial loopback plugs on ports 70 and 72.
by tre following:

TBAUD is invoked

AO>TBAUD
Error IIessages which may appear are:

***
***

Timeout, Baud rate xxx, baud port yy, test values-(expected)
(actual) possibly no loop back
Error, ~ud rate xxxx, baud port yy, test values - (expected)
(actua 1)

8.2.5

TPAT

- Pa t te rn Te s t

TPAT causes the video board to fill up every character position on the
CRT--all 25 lines and 80 characters. In addition it shows every character
in the character PROH at both high and low intensity. This program allows
inspection of the characte r se t and the CRT raste r. To invoke:
AO>TPAT
To get out of the Pattern Test enter a Control-Shift-RST or press the
Re se t swi tch on the back of the ASSOCIATE.

8.2.6

TCTe

- Counte r Time r Te st

This test checks the counter timer chip'to determine if it interrupts and
times at the proper rate. There are four different timer circuits in the
chip. For testing, each timer circuit is set up for a different rate. The
program is then set to exe cute for a specified amount of time.
The
interrupts over that period of time are counted; if the count doesn't
come out exactly right, TCTC indicates that the test failed. The Counter
Time r Te st is invoked from CP/M by tre following:
AO)TCTC
The system will reply as follows when the Counter Timer checks out with no
problem:
CTC - Test System 10 CTC Chip
CTC Te st Comple te
The error rre ssage is:

8-6

V1.1 as of 23-JAN-80

8. Service Procedures

ASSOCIATE Technical Reference Nanual

*** CTC Ce st fa iled
Actual:
(ctO) (etl) (ct2) (ctJ) (other ints)
Ex pe c te d: ( c to) ( C t 1) ( c t 2 ) ( c t 3) ( 0 t he r in t s )
8.2.7

TCRT

- CRT Test

This test exercises the CRT processor.

It consists of several subtests:

PROM checksum. A checksum is made of che PROM data and compared
against a table in the TCRT program. In the event
of an error,
a message is printed on the screen and the
test holds at that
point.
RAM. The CRT scratchpad RAM is tested.
printed on the screen.

Any errors decected are

VIDEO RAM is tested in two parts.
The top half of Che screen is
cesced first. If any erros are detected, the erring locacions are
listed in the bottom half. Upon successful completion the bottom
half is tested in the same manne r.
To invoke TCRT, enter the following:
AO)TCRT
To end the test, enter two Control C's.
The error nessage is:

Ram error(s) at vvvv •• wwww • • xxxx • • yyyy • • zzzz
8.2.8

TDISK

- Disk Drive Test

TDISK provides options for testing the disk drives;
the options are
indica ted after prompts during exe cution of the diagnostic program.
The
program indicaces sectors and tracks under test. At the end of each
pass, TDISK displays the number of accumulated errors. The number of read
a ttempts is de termined by the system BIOS. With the normal ten try BIOS
the error ra te should be 1e ss than one error pe r 1000 passe s.

* *********************************************************

*
*
*
*

Note:

Testing destroys all data on a disk.
Exercise care in disk selection.

*
*
*
*

***********************************************************

To see if a disk can be read, DUMP validate can be used.
To invoke TDISK:
AO)TDISK
Control C aborts the test.

8-7

ASSOCIATE Technical Pc!ference :1anual

8.2.9

R. Se rvice Procedure s

TDMA

This program tests the memory-to-memory DMA function. The process is
accomplished by repetitively testing DMA memory-to-memory transfers. To
use :
AO)TDMA
Test results may include the following error messages:

***
***

DMA modified location xxxx from yy to zz
DMA transfer error at xxxx should be yy but is zz

8.2.10

TINT

This program tests that all interrupt-generating devices can generate
inte rrupts simultane ously.
TI1e process include s configuring de vice s for
interrupts and testing if each device generates interrupts.
TI1e devices are configured as follows:
SIO
PIO
CTC

Ports 60, 70, and 72 se tup for transmi t and
re ce i ve interrupt s.
Se t.up as 1n TPIO
Setup as in TCTC, but with lower frequency
i£!terrupts.

Loop back test fixtures are required in the serial and parallel ports.
After delaying for a specified number of software loops, the program tests
if all devices have generated interrupts.
To use:
AO)TINT
ssage s which my appear:

Test result error

lie

***
***
***
***
***
***
***
***
***
***
***
***

from
from
from
from
from
from
from
from
from
from
from
from

8-8

No
No
No
No
No
No
No
No
No
No
No
~o

inte rrupts
inte rrupts
inte rrupts
inte rrupts
inte rrupts
inte rrupts
inte rrupts
interrupts
inte rrupts
iote rrupts
inte rrupts
inte rrupts

eTC
GTC
eTC
CTe
PIO
PIO
SIO
SIO
SIO
SIO
SIO
SIO

port
port
port
port
port
port
port
port
port
port
port
port

0
1

2
3
A
B

70 - rece ive
70 - xmit
72 - receive
72 - xmit
60 - rece ive
60 - xmit

ASSOCIATE Technical Reference I1lnual

8.2.11

TRTC - Test Real Tiue Clock Option

TRTC exe rcise s and tests the real time clock option,
the following functions:

1.
2.
3.

The program pe rforms

Displays the current tim.
Monitors any interrupts generated by the Real Till'8 Clock
Allows the user to set the til!l! and date.
Allows the user to set the RTC interrupt msk.
Allows the user to reset each individual counter and latch
Performs the system clock test. This test compares the
RTC timing wi th the system clock timing.
Pe rforms the "pulse test" for fine tuning the Real Time
Clock crystal.

5.
6.
7.

USER ENTRY

COMPUTER RESPONSE

TRTC

8.2.12

8. Service Procedures

.mE. -

Computer prompts user with options

Test Disk Rotational Speed

TSPD tests the rotational speed of either the A or B disk drive.
e.cuted by:

It is

AO)TSPD
A prompt menu gives the user the choice of running the rotational test,
selecUng the drive to test, or returning to the Operating System. Using
the System clock the test operates by measuring the time it takes the
diskette to make five revolutions (one second's worth). This time 1s
converted to Revolution per Minute for display on the screen. an error
message will be displayed i f no Index Pulse is found.
Tandon and MPI specify 1.5% speed tolerance on the disk drives.
corresponds to an error of + or - 4.5 RPM.
8.3

Disassembly

This

Reassembly

This se ction provide s informa tion for disassembly and reassembly of the
major components of the ASSOCIATE.
Again, only qualified technical
personnell should attempt to disassemble the Microcomputer. Improper
reassembly or operation may damage the unit and void the warranty.

*****************************************************************
. ***
CAUTION
***
ra nge rous vol ta ge s !!!. pre se nt .!.!! ~ ~
***
***
It is advised that pe rsonnel working inside of the
***
***
*** ASSOCIATE or any electrical equipment should NOT wear ***
tretal jewelry or watches.
***
***
Donat unscrew metal parts,disconnect cables,
***
***
orremove components with the po lie ron.
***
***
******************.**********************************************
8-9

ASSOCIATE Te chnical !,",

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