ATmega128 Manual

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Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture

•

•
•
•

– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
– 128K Bytes of In-System Self-programmable Flash program memory
– 4K Bytes EEPROM
– 4K Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
Operating Voltages
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
Speed Grades
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128

8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L

Rev. 2467P–AVR–08/07

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2(ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1(RD)
PG0(WR)

(OC2/OC1C) PB7
TOSC2/PG3
TOSC1/PG4
RESET
VCC
GND
XTAL2
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T2) PD7

PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/INT7) PE7
(SS) PB0
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC0) PB4
(OC1A) PB5
(OC1B) PB6

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49

AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)

Figure 1. Pinout ATmega128

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Pin
Configurations

Note:

Overview

The Pinout figure applies to both TQFP and MLF packages. The bottom pad under the QFN/MLF
package should be soldered to ground.

The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega128
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Block Diagram

PC0 - PC7

RESET

PA0 - PA7

XTAL1

PF0 - PF7

XTAL2

Figure 2. Block Diagram

VCC
GND
PORTA DRIVERS

PORTF DRIVERS

DATA DIR.
REG. PORTF

DATA REGISTER
PORTF

PORTC DRIVERS

DATA DIR.
REG. PORTA

DATA REGISTER
PORTA

DATA REGISTER
PORTC

DATA DIR.
REG. PORTC

8-BIT DATA BUS

AVCC

CALIB. OSC
INTERNAL
OSCILLATOR

ADC

AGND
AREF

OSCILLATOR
PROGRAM
COUNTER

STACK
POINTER

WATCHDOG
TIMER

ON-CHIP DEBUG

PROGRAM
FLASH

SRAM

MCU CONTROL
REGISTER

BOUNDARYSCAN

INSTRUCTION
REGISTER

JTAG TAP

OSCILLATOR

TIMING AND
CONTROL

TIMER/
COUNTERS

GENERAL
PURPOSE
REGISTERS
X

PEN

PROGRAMMING
LOGIC

INSTRUCTION
DECODER

CONTROL
LINES

INTERRUPT
UNIT

ALU

EEPROM

STATUS
REGISTER

SPI

+
-

ANALOG
COMPARATOR

USART0

DATA REGISTER
PORTE

DATA DIR.
REG. PORTE

PORTE DRIVERS

PE0 - PE7

DATA REGISTER
PORTB

DATA DIR.
REG. PORTB

PORTB DRIVERS

PB0 - PB7

USART1

DATA REGISTER
PORTD

TWO-WIRE SERIAL
INTERFACE

DATA DIR.
REG. PORTD

DATA REG.
PORTG

DATA DIR.
REG. PORTG

PORTD DRIVERS

PORTG DRIVERS

PD0 - PD7

PG0 - PG4

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2467P–AVR–08/07

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible
Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial
Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable
gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.
1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and
programming and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode,
both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega128 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.

ATmega103 and
ATmega128
Compatibility

The ATmega128 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O locations reserved in the AVR instruction set. To ensure backward compatibility
with the ATmega103, all I/O locations present in ATmega103 have the same location in
ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60
to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using
LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the
increased number of interrupt vectors might be a problem if the code uses absolute addresses.
To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the
internal RAM is located as in ATmega103. Also, the Extended Interrupt vectors are removed.
The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on
current Printed Circuit Boards. The application note “Replacing ATmega103 by ATmega128”
describes what the user should be aware of replacing the ATmega103 by an ATmega128.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
ATmega103
Compatibility Mode

By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103
regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below:
•

One USART instead of two, Asynchronous mode only. Only the eight least significant bits of
the Baud Rate Register is available.

•

One 16 bits Timer/Counter with two compare registers instead of two 16-bit Timer/Counters
with three compare registers.

•

Two-wire serial interface is not supported.

•

Port C is output only.

•

Port G serves alternate functions only (not a general I/O port).

•

Port F serves as digital input only in addition to analog input to the ADC.

•

Boot Loader capabilities is not supported.

•

It is not possible to adjust the frequency of the internal calibrated RC Oscillator.

•

The External Memory Interface can not release any Address pins for general I/O, neither
configure different wait-states to different External Memory Address sections.

In addition, there are some other minor differences to make it more compatible to ATmega103:
•

Only EXTRF and PORF exists in MCUCSR.

•

Timed sequence not required for Watchdog Time-out change.

•

External Interrupt pins 3 - 0 serve as level interrupt only.

•

USART has no FIFO buffer, so data overrun comes earlier.

Unused I/O bits in ATmega103 should be written to 0 to ensure same operation in ATmega128.

Pin Descriptions
VCC

Digital supply voltage.

GND

Ground.

Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega128 as listed on page
73.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega128 as listed on page
74.

Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

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2467P–AVR–08/07

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega128 as listed on page 77. In
ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated
when a reset condition becomes active.
Note:

Port D (PD7..PD0)

The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not
programmed before they are put on the PCB, PORTC will be output during first power up, and until
the ATmega103 compatibility mode is disabled.

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega128 as listed on page
78.

Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega128 as listed on page
81.

Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a Reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input Port only.

Port G (PG4..PG0)

Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features.
The port G pins are tri-stated when a reset condition becomes active, even if the clock is not
running.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the external
memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 =
1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not
running. PG3 and PG4 are oscillator pins.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page
51. Shorter pulses are not guaranteed to generate a reset.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting Oscillator amplifier.

AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.

AREF

AREF is the analog reference pin for the A/D Converter.

PEN

PEN is a programming enable pin for the SPI Serial Programming mode, and is internally pulled
high . By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN has no function during normal operation.

7
2467P–AVR–08/07

Resources

A comprehensive set of development tools, application notes, and datasheets are available for
download on http://www.atmel.com/avr.
Note:

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
About Code
Examples

This datasheet contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and
interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.
For I/O registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

9
2467P–AVR–08/07

AVR CPU Core
Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals and handle interrupts.

Architectural
Overview

Figure 3. Block Diagram of the AVR Architecture
Data Bus 8-bit

Flash
Program
Memory

Program
Counter

Status
and Control

32 x 8
General
Purpose
Registrers

Control Lines

Direct Addressing

Instruction
Decoder

Indirect Addressing

Instruction
Register

Interrupt
Unit
SPI
Unit
Watchdog
Timer

ALU

Analog
Comparator

I/O Module1

Data
SRAM

I/O Module 2

I/O Module n
EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
The fast-access Register file contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register file, the operation is executed,
and the result is stored back in the Register file – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-register, Y-register and Z-register, described later in
this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM instruction that writes into the Application Flash Memory section must
reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack
Pointer – SP – is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the Status Register. All interrupts have a separate interrupt vector in the
interrupt vector table. The interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address, the higher the priority.
The I/O memory space contains 64 addresses which can be accessed directly, or as the Data
Space locations following those of the Register file, $20 - $5F. In addition, the ATmega128 has
Extended I/O space from $60 - $FF in SRAM where only the ST/STS/STD and LD/LDS/LDD
instructions can be used.

ALU – Arithmetic
Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR status Register – SREG – is defined as:
Bit

Read/Write

R/W

Initial Value

SREG

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2467P–AVR–08/07

• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared in
software with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register file by the BLD
instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a half carry in some arithmetic operations. Half carry is useful in
BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N

⊕V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.

General Purpose
Register File

The Register file is optimized for the AVR Enhanced RISC instruction set. In order to achieve the
required performance and flexibility, the following input/output schemes are supported by the
Register file:
•

One 8-bit output operand and one 8-bit result input

•

Two 8-bit output operands and one 8-bit result input

•

Two 8-bit output operands and one 16-bit result input

•

One 16-bit output operand and one 16-bit result input

Figure 4 on page 12 shows the structure of the 32 general purpose working registers in the
CPU.

Figure 4. AVR CPU General Purpose Working Registers
7

Addr.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
R0

$00

$01

$02

…
R13

$0D

General

R14

$0E

Purpose

R15

$0F

Working

R16

$10

Registers

R17

$11

…
R26

$1A

X-register Low Byte

R27

$1B

X-register High Byte

R28

$1C

Y-register Low Byte

R29

$1D

Y-register High Byte

R30

$1E

Z-register Low Byte

R31

$1F

Z-register High Byte

Most of the instructions operating on the Register file have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.
X-register, Y-register,
and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect
address registers X, Y, and Z are described in Figure 5.
Figure 5. The X-, Y-, and Z-registers
15
X - register

XL
0

R27 ($1B)

15
Y - register

15
7
R31 ($1F)

0
0

R26 ($1A)

YL
0

R29 ($1D)

Z - register

0
0

R28 ($1C)

ZL
0

0
0

R30 ($1E)

In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).

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2467P–AVR–08/07

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPH

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

R/W

–

––

–

RAMPZ0

Read/Write

R/W

Initial Value

Read/Write

Initial Value

RAM Page Z Select
Register – RAMPZ

Bit

RAMPZ

• Bits 7..1 – Res: Reserved Bits
These are reserved bits and will always read as zero. When writing to this address location,
write these bits to zero for compatibility with future devices.
• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer
The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Zpointer. As the ATmega128 does not support more than 64K of SRAM memory, this register is
used only to select which page in the program memory is accessed when the ELPM/SPM
instruction is used. The different settings of the RAMPZ0 bit have the following effects:
RAMPZ0 = 0:

Program memory address $0000 - $7FFF (lower 64K bytes) is
accessed by ELPM/SPM

RAMPZ0 = 1:

Program memory address $8000 - $FFFF (higher 64K bytes) is
accessed by ELPM/SPM

Note that LPM is not affected by the RAMPZ setting.

Instruction
Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register file concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6. The Parallel Instruction Fetches and Instruction Executions
T1

clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register file. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 7. Single Cycle ALU Operation
T1

clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back

Reset and
Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate reset
vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Programming” on page 286 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The interrupt vectors can be moved to the start of the boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information.
The Reset vector can also be moved to the start of the boot Flash section by programming the
BOOTRST fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page
273.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.

15
2467P–AVR–08/07

There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual interrupt vector
in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the global interrupt enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
cli

; store SREG value

; disable interrupts during timed sequence

sbi EECR, EEMWE

; start EEPROM write

sbi EECR, EEWE
out SREG, r16

; restore SREG value (I-bit)

C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<
...

...

; Set stack pointer to top of RAM

; Enable interrupts
xxx
...

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
When the BOOTRST fuse is unprogrammed, the Boot section size set to 8K bytes and the
IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and
general program setup for the Reset and Interrupt Vector Addresses is:
Address LabelsCode
$0000

Comments

RESET:ldi

r16,high(RAMEND); Main program start

$0001

out

SPH,r16

$0002

ldi

r16,low(RAMEND)

; Set stack pointer to top of RAM

$0003
$0004

out
sei

SPL,r16

$0005

; Enable interrupts
xxx

;
.org $F002
$F002

jmp

EXT_INT0

; IRQ0 Handler

$F004

jmp

EXT_INT1

; IRQ1 Handler

...

;

$F044

jmp

SPM_RDY

; Store Program Memory Ready Handler

When the BOOTRST fuse is programmed and the Boot section size set to 8K bytes, the most
typical and general program setup for the Reset and Interrupt Vector Addresses is:
Address

LabelsCode

Comments

.org $0002
$0002

jmp

EXT_INT0

; IRQ0 Handler

$0004

jmp

EXT_INT1

; IRQ1 Handler

...

;

$0044

jmp

SPM_RDY

; Store Program Memory Ready Handler

;
.org $F000
$F000
RESET: ldi

r16,high(RAMEND); Main program start

$F001

out

SPH,r16

$F002

ldi

r16,low(RAMEND)

$F003
$F004

out
sei

SPL,r16

$F005

; Set stack pointer to top of RAM

; Enable interrupts
xxx

When the BOOTRST fuse is programmed, the Boot section size set to 8K bytes and the IVSEL
bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general
program setup for the Reset and Interrupt Vector Addresses is:
Address

Labels

Code

Comments

;
.org $F000
$F000
$F002

jmp
jmp

RESET
EXT_INT0

; Reset handler
; IRQ0 Handler

$F004

jmp

EXT_INT1

; IRQ1 Handler

...

;

$F044

jmp

SPM_RDY ; Store Program Memory Ready Handler

$F046

RESET: ldi

$F047

out

SPH,r16

$F048

ldi

r16,low(RAMEND)

r16,high(RAMEND); Main program start
; Set stack pointer to top of RAM

63
2467P–AVR–08/07

Moving Interrupts
Between Application
and Boot Space
MCU Control Register
– MCUCR

$F049
$F04A

out
sei

SPL,r16

$F04B

; Enable interrupts
xxx

The General Interrupt Control Register controls the placement of the interrupt vector table.

Bit

SRE

SRW10

SM1

SM0

SM2

IVSEL

IVCE

Read/Write

R/W

Initial Value

MCUCR

• Bit 1 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the Flash
memory. When this bit is set (one), the interrupt vectors are moved to the beginning of the Boot
Loader section of the flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ fuses. Refer to the section “Boot Loader Support – Read-While-Write
Self-Programming” on page 273 for details. To avoid unintentional changes of interrupt vector
tables, a special write procedure must be followed to change the IVSEL bit:
1. Write the Interrupt Vector Change Enable (IVCE) bit to one.
2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled
in the cycle IVCE is set, and they remain disabled until after the instruction following the write to
IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status
Register is unaffected by the automatic disabling.
Note:

If interrupt vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,
interrupts are disabled while executing from the Application section. If interrupt vectors are placed
in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while
executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-WhileWrite Self-Programming” on page 273 for details on Boot Lock bits.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
• Bit 0 – IVCE: Interrupt Vector Change Enable
The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by
hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable
interrupts, as explained in the IVSEL description above. See Code Example below.
Assembly Code Example
Move_interrupts:
; Enable change of interrupt vectors
ldi r16, (1< CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler
also use prescaling. A Prescaler Reset will affect the prescaler period for all Timer/Counters it is
connected to.

External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock
(clkT1/clkT2/clkT3). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure
59 shows a functional equivalent block diagram of the Tn synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch
is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT2/clkT3 pulse for each positive (CSn2:0 = 7) or negative (CSn2:0 = 6) edge it detects.
Figure 59. Tn Pin Sampling

D Q

Tn_sync
(To Clock
Select Logic)

LE
clk I/O
Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn pin to the counter is updated.
Enabling and disabling of the clock input must be done when Tn has been stable for at least one
system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

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2467P–AVR–08/07

Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 60. Prescaler for Timer/Counter1, Timer/Counter2, and Timer/Counter3
CK

PSR321

Special Function IO
Register – SFIOR

CS30

CS20

CS31

CS21

CS10
CS11

CS32

CS22

CS12

TIMER/COUNTER3 CLOCK SOURCE
clkT3

Note:

CK/1024

CK/64

CK/8

CK/256

10-BIT T/C PRESCALER

Clear

TIMER/COUNTER2 CLOCK SOURCE
clkT2

TIMER/COUNTER1 CLOCK SOURCE
clkT1

The synchronization logic on the input pins (T3/T2/T1) is shown in Figure 59.

Bit

TSM

–

ACME

PUD

PSR0

PSR321

Read/Write

R/W

Initial Value

SFIOR

• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR0 and PSR321 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted
and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSR0 and PSR321 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
When this bit is one, the Timer/Counter3, Timer/Counter1, and Timer/Counter2 prescaler will be
reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note
that Timer/Counter3, Timer/Counter1, and Timer/Counter2 share the same prescaler and a
reset of this prescaler will affect all three timers.

144

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
8-bit
Timer/Counter2
with PWM

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
• Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 61. For the actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible I/O registers, including
I/O bits and I/O pins, are shown in bold. The device-specific I/O register and bit locations are
listed in the “8-bit Timer/Counter Register Description” on page 157.
Figure 61. 8-Bit Timer/Counter Block Diagram

TCCRn

count

TOVn
(Int.Req.)

clear

Control Logic

direction

clk Tn

Clock Select
Edge
Detector

DATA BUS

BOTTOM

TOP

( From Prescaler )
Timer/Counter
TCNTn

= 0xFF

OCn
(Int.Req.)

Waveform
Generation

OCn

OCRn

Registers

The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers. Interrupt
request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag
Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other
timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T2 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the clock select logic is referred to as the timer clock (clkT2).

145
2467P–AVR–08/07

The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the waveform generator to generate
a PWM or variable frequency output on the Output Compare Pin (OC2). See “Output Compare
Unit” on page 147. for details. The compare match event will also set the compare flag (OCF2)
which can be used to generate an output compare interrupt request.
Definitions

Many register and bit references in this document are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 2. However, when using the register or bit
defines in a program, the precise form must be used (i.e., TCNT2 for accessing Timer/Counter2
counter value and so on).
The definitions in Table 63 are also used extensively throughout the document.
Table 63. Definitions
BOTTOM

The counter reaches the BOTTOM when it becomes 0x00.

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The
assignment is dependent on the mode of operation.

Timer/Counter
Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the clock select logic which is controlled by the clock select (CS22:0) bits located
in the Timer/Counter Control Register (TCCR2). For details on clock sources and prescaler, see
“Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers” on page 143.

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
62 shows a block diagram of the counter and its surroundings.
Figure 62. Counter Unit Block Diagram
TOVn
(Int.Req.)

DATA BUS

Clock Select
count
TCNTn

clear

Control Logic

Edge
Detector

clkTn

direction
( From Prescaler )
bottom

top

Signal description (internal signals):

146

count

Increment or decrement TCNT2 by 1.

direction

Select between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clkTn

Timer/Counter clock, referred to as clkT0 in the following.

top

Signalize that TCNT2 has reached maximum value.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
bottom

Signalize that TCNT2 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source,
selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the
timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in
the Timer/Counter Control Register (TCCR2). There are close connections between how the
counter behaves (counts) and how waveforms are generated on the output compare output
OC2. For more details about advanced counting sequences and waveform generation, see
“Modes of Operation” on page 149.
The Timer/Counter overflow (TOV2) flag is set according to the mode of operation selected by
the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

Output Compare
Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register
(OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the
output compare flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1 and global interrupt flag in SREG is set), the output compare flag generates an output compare interrupt. The
OCF2 flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 flag
can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the
WGM21:0 bits and compare output mode (COM21:0) bits. The max and bottom signals are used
by the waveform generator for handling the special cases of the extreme values in some modes
of operation (see “Modes of Operation” on page 149). Figure 63 shows a block diagram of the
output compare unit.
Figure 63. Output Compare Unit, Block Diagram

DATA BUS

OCRn

TCNTn

= (8-bit Comparator )
OCFn (Int.Req.)
top
bottom

Waveform Generator

OCn

FOCn

WGMn1:0

COMn1:0

The OCR2 Register is double buffered when using any of the pulse width modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-

147
2467P–AVR–08/07

ering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register
to either top or bottom of the counting sequence. The synchronization prevents the occurrence
of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR2 Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR2 buffer Register, and if double buffering is disabled
the CPU will access the OCR2 directly.
Force Output
Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the force output compare (FOC2) bit. Forcing compare match will not set the
OCF2 flag or reload/clear the timer, but the OC2 pin will be updated as if a real compare match
had occurred (the COM21:0 bits settings define whether the OC2 pin is set, cleared or toggled).

Compare Match
Blocking by TCNT2
Write

All CPU write operations to the TCNT2 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR2 to be initialized
to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is
enabled.

Using the Output
Compare Unit

Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT2 when using the output compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT2
equals the OCR2 value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is
downcounting.
The setup of the OC2 should be performed before setting the Data Direction Register for the port
pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare
(FOC2) strobe bits in normal mode. The OC2 Register keeps its value even when changing
between waveform generation modes.
Be aware that the COM21:0 bits are not double buffered together with the compare value.
Changing the COM21:0 bits will take effect immediately.

Compare Match
Output Unit

148

The Compare Output mode (COM21:0) bits have two functions. The waveform generator uses
the COM21:0 bits for defining the output compare (OC2) state at the next compare match. Also,
the COM21:0 bits control the OC2 pin output source. Figure 64 shows a simplified schematic of
the logic affected by the COM21:0 bit setting. The I/O registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT)
that are affected by the COM21:0 bits are shown. When referring to the OC2 state, the reference
is for the internal OC2 Register, not the OC2 pin. If a System Reset occur, the OC2 Register is
reset to “0”.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 64. Compare Match Output Unit, Schematic

COMn1
COMn0
FOCn

Waveform
Generator

Q
1

OCn

DATA BUS

OCn
Pin

PORT
D

DDR
clk I/O

The general I/O port function is overridden by the output compare (OC2) from the waveform
generator if either of the COM21:0 bits are set. However, the OC2 pin direction (input or output)
is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as output before the OC2 value is visible on the
pin. The port override function is independent of the Waveform Generation mode.
The design of the output compare pin logic allows initialization of the OC2 state before the output is enabled. Note that some COM21:0 bit settings are reserved for certain modes of
operation. See “8-bit Timer/Counter Register Description” on page 157.
Compare Output Mode
and Waveform
Generation

The waveform generator uses the COM21:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM21:0 = 0 tells the waveform generator that no action on the OC2
Register is to be performed on the next compare match. For compare output actions in the nonPWM modes refer to Table 65 on page 158. For fast PWM mode, refer to Table 66 on page 158,
and for phase correct PWM refer to Table 67 on page 158.
A change of the COM21:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC2 strobe bits.

Modes of
Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output
mode (COM21:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM21:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM21:0 bits control whether the output should be set, cleared, or toggled at a compare
match (see “Compare Match Output Unit” on page 148).
For detailed timing information refer to Figure 68, Figure 69, Figure 70, and Figure 71 in
“Timer/Counter Timing Diagrams” on page 155.

Normal Mode

The simplest mode of operation is the normal mode (WGM21:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply

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2467P–AVR–08/07

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter overflow flag (TOV2) will be set in the same
timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOV2 flag, the timer resolution can be increased by software. There
are no special cases to consider in the normal mode, a new counter value can be written
anytime.
The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in normal mode is not recommended, since this will occupy
too much of the CPU time.
Clear Timer on
Compare Match (CTC)
Mode

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT2) matches the OCR2. The OCR2 defines the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 65. The counter value (TCNT2)
increases until a compare match occurs between TCNT2 and OCR2 and then counter (TCNT2)
is cleared.
Figure 65. CTC Mode, Timing Diagram
OCn Interrupt Flag Set

TCNTn

OCn
(Toggle)
Period

(COMn1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF2 flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the
TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR2 is lower than the current
value of TCNT2, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical
level on each compare match by setting the compare output mode bits to toggle mode
(COM21:0 = 1). The OC2 value will not be visible on the port pin unless the data direction for the
pin is set to output. The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2
when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation:
f clk_I/O
f OCn = ---------------------------------------------2 ⋅ N ⋅ ( 1 + OCRn )

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ATmega128(L)
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ATmega128(L)
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In
non-inverting Compare Output mode, the output compare (OC2) is cleared on the compare
match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the
output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 66. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare
matches between OCR2 and TCNT2.
Figure 66. Fast PWM Mode, Timing Diagram
OCRn Interrupt Flag Set

OCRn Update
and
TOVn Interrupt Flag Set

TCNTn

OCn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

Period

The Timer/Counter overflow flag (TOV2) is set each time the counter reaches Max If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can
be generated by setting the COM21:0 to 3 (see Table 66 on page 158). The actual OC2 value
will only be visible on the port pin if the data direction for the port pin is set as output. The PWM
waveform is generated by setting (or clearing) the OC2 Register at the compare match between
OCR2 and TCNT2, and clearing (or setting) the OC2 Register at the timer clock cycle the
counter is cleared (changes from MAX to BOTTOM).

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The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnPWM = ----------------N ⋅ 256
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be
a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2 equal to MAX will result in a
constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC2 to toggle its logical level on each compare match (COM21:0 = 1). The waveform
generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero. This feature is similar to the OC2 toggle in CTC mode, except the double buffer feature of the output
compare unit is enabled in the fast PWM mode.

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ATmega128(L)
Phase Correct PWM
Mode

The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope operation.
The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In noninverting Compare Output mode, the output compare (OC2) is cleared on the compare match
between TCNT2 and OCR2 while counting up, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has
lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The PWM resolution for the phase correct PWM mode is fixed to 8 bits. In phase correct PWM
mode the counter is incremented until the counter value matches Max When the counter
reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one
timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 67.
The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.
Figure 67. Phase Correct PWM Mode, Timing Diagram
OCn Interrupt Flag Set

OCRn Update

TOVn Interrupt Flag Set

TCNTn

OCn

(COMn1:0 = 2)

OCn

(COMn1:0 = 3)

Period

The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 67 on page 158). The actual OC2
value will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC2 Register at the compare match
between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the OC2
Register at compare match between OCR2 and TCNT2 when the counter decrements. The

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PWM frequency for the output when using phase correct PWM can be calculated by the following equation:
f clk_I/O
f OCnPCPWM = ----------------N ⋅ 510
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of Period 2 in Figure 67 OCn has a transition from high to low even though there
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without a Compare Match:

154

•

OCR2A changes its value from MAX, like in Figure 67. When the OCR2A value is MAX the
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match.

•

The timer starts counting from a value higher than the one in OCR2A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Timer/Counter
Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT2) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 68 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 68. Timer/Counter Timing Diagram, no Prescaling

clkI/O
clkTn

(clkI/O /1)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 69 shows the same timing data, but with the prescaler enabled.
Figure 69. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

Figure 70 shows the setting of OCF2 in all modes except CTC mode.

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Figure 70. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn

OCRn - 1

OCRn

OCRn + 1

OCRn + 2

OCRn Value

OCFn

Figure 71 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
Figure 71. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8)

clkI/O
clkTn

(clkI/O /8)

TCNTn
(CTC)
OCRn

TOP - 1

TOP

BOTTOM

BOTTOM + 1

TOP

OCFn

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ATmega128(L)
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ATmega128(L)
8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR2

Bit

FOC2

WGM20

COM21

COM20

WGM21

CS22

CS21

CS20

Read/Write

R/W

Initial Value

TCCR2

• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written
when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate compare match is forced on the waveform generation unit. The OC2 output is changed according to
its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the Timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See Table 64 and “Modes of Operation” on
page 149.
Table 64. Waveform Generation Mode Bit Description
Mode

WGM21
(CTC2)

WGM20
(PWM2)

1
2
3
Note:

Timer/Counter Mode
of Operation

TOP

Update of
OCR2 at

TOV2 Flag
Set on

Normal

0xFF

Immediate

MAX

PWM, Phase Correct

0xFF

TOP

BOTTOM

CTC

OCR2

Immediate

MAX

1
1
Fast PWM
0xFF
BOTTOM
MAX
The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.

• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare Pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC2 pin must be
set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the WGM21:0
bit setting. Table 65 shows the COM21:0 bit functionality when the WGM21:0 bits are set to a
normal or CTC mode (non-PWM).

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Table 65. Compare Output Mode, Non-PWM Mode
COM21

COM20

Description

Normal port operation, OC2 disconnected.

Toggle OC2 on compare match

Clear OC2 on compare match

Set OC2 on compare match

Table 66 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Table 66. Compare Output Mode, Fast PWM Mode(1)
COM21

COM20

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match, set OC2 at BOTTOM,
(non-inverting mode)

Note:

Description

Set OC2 on compare match, clear OC2 at BOTTOM,
(inverting mode)
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare
match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 151
for more details.

Table 67 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase correct
PWM mode.
Table 67. Compare Output Mode, Phase Correct PWM Mode(1)
COM21

COM20

Normal port operation, OC2 disconnected.

Reserved

Clear OC2 on compare match when up-counting. Set OC2 on compare
match when downcounting.

Note:

Description

Set OC2 on compare match when up-counting. Clear OC2 on compare
match when downcounting.
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare
match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page
153 for more details.

• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter.
Table 68. Clock Select Bit Description

158

CS22

CS21

CS20

Description

No clock source (Timer/Counter stopped)

clkI/O/(No prescaling)

clkI/O/8 (From prescaler)

clkI/O/64 (From prescaler)

clkI/O/256 (From prescaler)

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table 68. Clock Select Bit Description
CS22

CS21

CS20

Description

clkI/O/1024 (From prescaler)

External clock source on T2 pin. Clock on falling edge

External clock source on T2 pin. Clock on rising edge

If external pin modes are used for the Timer/Counter2, transitions on the T2 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
Timer/Counter
Register – TCNT2

Bit

TCNT2[7:0]

TCNT2

Read/Write

R/W

Initial Value

The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a compare match between TCNT2 and the OCR2 Register.
Output Compare
Register – OCR2

Bit

OCR2[7:0]

OCR2

Read/Write

R/W

Initial Value

The Output Compare Register contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an output compare interrupt, or to
generate a waveform output on the OC2 pin.
Timer/Counter
Interrupt Mask
Register – TIMSK

Bit

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

Read/Write

R/W

Initial Value

TIMSK

• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter2 occurs, i.e., when the OCF2 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
Timer/Counter
Interrupt Flag Register
– TIFR

Bit

Read/Write

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

R/W

TIFR

159
2467P–AVR–08/07

Initial Value

• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the
data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF2 is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and
OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The bit TOV2 is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared
by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In
PWM mode, this bit is set when Timer/Counter2 changes counting direction at $00.

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ATmega128(L)
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ATmega128(L)
Output
Compare
Modulator
(OCM1C2)
Overview

The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier
frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit
Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter2. For more details
about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)”
on page 112 and “8-bit Timer/Counter2 with PWM” on page 145. Note that this feature is not
available in ATmega103 compatibility mode.
Figure 72. Output Compare Modulator, Block Diagram
Timer/Counter 1

OC1C

Timer/Counter 2

OC1C /
OC2 / PB7

OC2

When the modulator is enabled, the two output compare channels are modulated together as
shown in the block diagram (Figure 72).

Description

The Output Compare unit 1C and Output Compare unit 2 shares the PB7 port pin for output. The
outputs of the Output Compare units (OC1C and OC2) overrides the normal PORTB7 Register
when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and
OC2 are enabled at the same time, the modulator is automatically enabled.
The functional equivalent schematic of the modulator is shown on Figure 73. The schematic
includes part of the Timer/Counter units and the port B pin 7 output driver circuit.
Figure 73. Output Compare Modulator, Schematic
COM21
COM20

Vcc

COM1C1
COM1C0

( From Waveform Generator )

Modulator

OC1C

Pin
0

( From Waveform Generator )

OC1C /
OC2 / PB7

OC2
D

PORTB7

DDRB7
DATABUS

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When the modulator is enabled the type of modulation (logical AND or OR) can be selected by
the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the
COMnx1:0 bit setting.
Timing Example

Figure 74 illustrates the modulator in action. In this example the Timer/Counter1 is set to operate
in fast PWM mode (non-inverted) and Timer/Counter2 uses CTC waveform mode with toggle
Compare Output mode (COMnx1:0 = 1).
Figure 74. Output Compare Modulator, Timing Diagram
clk I/O
OC1C
(FPWM Mode)

OC2
(CTC Mode)

PB7
(PORTB7 = 0)

PB7
(PORTB7 = 1)

(Period)

In this example, Timer/Counter2 provides the carrier, while the modulating signal is generated
by the Output Compare unit C of the Timer/Counter1.
The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is
equal to the number of system clock cycles of one period of the carrier (OC2). In this example
the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure
74 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2
high time is one cycle longer than the period 3 high time, but the result on the PB7 output is
equal in both periods.

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ATmega128(L)
Serial
Peripheral
Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega128 and peripheral devices or between several AVR devices. The ATmega128 SPI
includes the following features:
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
Figure 75. SPI Block Diagram

SPI2X

DIVIDER
/2/4/8/16/32/64/128

Note:

Refer to Figure 1 on page 2 and Table 30 on page 74 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 76. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective Shift Registers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.

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When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the 8 bits
into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is
requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the
end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the
buffer register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of transmission
flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is
requested. The Slave may continue to place new data to be sent into SPDR before reading the
incoming data. The last incoming byte will be kept in the buffer register for later use.
Figure 76. SPI Master-Slave Interconnection

SHIFT
ENABLE

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the minimum low and high period should be:
Low period: Longer than 2 CPU clock cycles.
High period: Longer than 2 CPU clock cycles.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 69. For more details on automatic port overrides, refer to “Alternate Port
Functions” on page 71.
Table 69. SPI Pin Overrides(1)
Pin

164

Direction, Master SPI

Direction, Slave SPI

MOSI

User Defined

Input

MISO

Input

User Defined

SCK

User Defined

Input

User Defined

Input

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Note:

1. See “Alternate Functions of Port B” on page 74 for a detailed description of how to define the
direction of the user defined SPI pins.

The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual data direction
register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. For example, if MOSI is placed on pin PB5, replace
DD_MOSI with DDB5 and DDR_SPI with DDRB.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi

r17,(1<>8);
UBRRL = (unsigned char)ubrr;
/* Enable receiver and transmitter */
UCSRB = (1<> 1) & 0x01;
return ((resh << 8) | resl);
}

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ATmega128(L)
Note:

Receive Compete Flag
and Interrupt

1. See “About Code Examples” on page 9..
The receive function example reads all the I/O registers into the register file before any computation is done. This gives an optimal receive buffer utilization since the buffer location read will
be free to accept new data as early as possible.

The USART Receiver has one flag that indicates the receiver state.
The Receive Complete (RXC) flag indicates if there are unread data present in the receive
buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXEN = 0),
the receive buffer will be flushed and consequently the RXC bit will become zero.
When the Receive Complete Interrupt Enable (RXCIE) in UCSRB is set, the USART Receive
Complete Interrupt will be executed as long as the RXC flag is set (provided that global interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine
must read the received data from UDR in order to clear the RXC flag, otherwise a new interrupt
will occur once the interrupt routine terminates.

Receiver Error Flags

The USART receiver has three error flags: Frame Error (FE), Data OverRun (DOR) and Parity
Error (UPE). All can be accessed by reading UCSRA. Common for the error flags is that they are
located in the receive buffer together with the frame for which they indicate the error status. Due
to the buffering of the error flags, the UCSRA must be read before the receive buffer (UDR),
since reading the UDR I/O location changes the buffer read location. Another equality for the
error flags is that they can not be altered by software doing a write to the flag location. However,
all flags must be set to zero when the UCSRA is written for upward compatibility of future
USART implementations. None of the error flags can generate interrupts.
The Frame Error (FE) flag indicates the state of the first stop bit of the next readable frame
stored in the receive buffer. The FE flag is zero when the stop bit was correctly read (as one),
and the FE flag will be one when the stop bit was incorrect (zero). This flag can be used for
detecting out-of-sync conditions, detecting break conditions and protocol handling. The FE flag
is not affected by the setting of the USBS bit in UCSRC since the receiver ignores all, except for
the first, stop bits. For compatibility with future devices, always set this bit to zero when writing to
UCSRA.
The Data OverRun (DOR) flag indicates data loss due to a receiver buffer full condition. A data
overrun occurs when the receive buffer is full (two characters), it is a new character waiting in
the Receive Shift Register, and a new start bit is detected. If the DOR flag is set there was one
or more serial frame lost between the frame last read from UDR, and the next frame read from
UDR. For compatibility with future devices, always write this bit to zero when writing to UCSRA.
The DOR flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer.
The Parity Error (UPE) flag indicates that the next frame in the receive buffer had a parity error
when received. If parity check is not enabled the UPE bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRA. For more details see
“Parity Bit Calculation” on page 176 and “Parity Checker” on page 184.

183
2467P–AVR–08/07

Parity Checker

The parity checker is active when the high USART Parity mode (UPM1) bit is set. Type of parity
check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the parity
checker calculates the parity of the data bits in incoming frames and compares the result with
the parity bit from the serial frame. The result of the check is stored in the receive buffer together
with the received data and stop bits. The Parity Error (UPE) flag can then be read by software to
check if the frame had a Parity Error.
The UPE bit is set if the next character that can be read from the receive buffer had a parIty
Error when received and the parity checking was enabled at that point (UPM1 = 1). This bit is
valid until the Receive buffer (UDR) is read.

Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing
receptions will therefore be lost. When disabled (i.e., the RXEN is set to zero) the receiver will no
longer override the normal function of the RxD port pin. The receiver buffer FIFO will be flushed
when the receiver is disabled. Remaining data in the buffer will be lost
Flushing the Receive
Buffer

The receiver buffer FIFO will be flushed when the receiver is disabled, i.e. the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal
operation, due to for instance an error condition, read the UDR I/O location until the RXC flag is
cleared. The following code example shows how to flush the receive buffer.
Assembly Code Example(1)
USART_Flush:
sbis UCSRA, RXC
ret
in

r16, UDR

rjmp USART_Flush

C Code Example(1)
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRA & (1< 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck ≥ 12 MHz
SPI Serial
Programming
Algorithm

When writing serial data to the ATmega128, data is clocked on the rising edge of SCK.
When reading data from the ATmega128, data is clocked on the falling edge of SCK. See Figure
145 for timing details.
To program and verify the ATmega128 in the SPI Serial Programming mode, the following
sequence is recommended (See four byte instruction formats in Table 145):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
As an alternative to using the RESET signal, PEN can be held low during Power-on
Reset while SCK is set to “0”. In this case, only the PEN value at Power-on Reset is
important. If the programmer cannot guarantee that SCK is held low during power-up, the
PEN method cannot be used. The device must be powered down in order to commence
normal operation when using this method.
2. Wait for at least 20 ms and enable SPI Serial Programming by sending the Programming
Enable serial instruction to pin MOSI.

301
2467P–AVR–08/07

3. The SPI Serial Programming instructions will not work if the communication is out of synchronization. When in sync. the second byte ($53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all FOUR
bytes of the instruction must be transmitted. If the $53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The page size is found in Table 124 on
page 292. The memory page is loaded one byte at a time by supplying the 7 LSB of the
address and data together with the Load Program Memory Page instruction. To ensure
correct loading of the page, the data low byte must be loaded before data high byte is
applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. If polling is not used, the
user must wait at least tWD_FLASH before issuing the next page. (See Table 128).
Note: If other commands than polling (read) are applied before any write operation (Flash,
EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming.
5. The EEPROM array is programmed one byte at a time by supplying the address and data
together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least tWD_EEPROM before issuing the next byte. (See Table 128). In a chip erased device,
no $FFs in the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Data Polling Flash

When a page is being programmed into the Flash, reading an address location within the page
being programmed will give the value $FF. At the time the device is ready for a new page, the
programmed value will read correctly. This is used to determine when the next page can be written. Note that the entire page is written simultaneously and any address within the page can be
used for polling. Data polling of the Flash will not work for the value $FF, so when programming
this value, the user will have to wait for at least tWD_FLASH before programming the next page. As
a chip-erased device contains $FF in all locations, programming of addresses that are meant to
contain $FF, can be skipped. See Table 128 for tWD_FLASH value

Data Polling EEPROM

When a new byte has been written and is being programmed into EEPROM, reading the
address location being programmed will give the value $FF. At the time the device is ready for a
new byte, the programmed value will read correctly. This is used to determine when the next
byte can be written. This will not work for the value $FF, but the user should have the following in
mind: As a chip-erased device contains $FF in all locations, programming of addresses that are
meant to contain $FF, can be skipped. This does not apply if the EEPROM is re-programmed
without chip-erasing the device. In this case, data polling cannot be used for the value $FF, and
the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 128
for tWD_EEPROM value.

302

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table 128. Minimum Wait Delay before Writing the Next Flash or EEPROM Location, VCC = 5 V
± 10%
Symbol

Minimum Wait Delay

tWD_FUSE

4.5 ms

tWD_FLASH

5 ms

tWD_EEPROM

10 ms

tWD_ERASE

10 ms

Figure 145. .SPI Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)

MSB

LSB

SERIAL DATA OUTPUT
(MISO)

MSB

LSB

SERIAL CLOCK INPUT
(SCK)
SAMPLE

303
2467P–AVR–08/07

Table 129. SPI Serial Programming Instruction Set
Instruction Format
Instruction

Byte 1

Byte 2

Byte 3

Byte4

Programming Enable

1010 1100

0101 0011

xxxx xxxx

Enable SPI Serial Programming after RESET
goes low.

Chip Erase

1010 1100

100x xxxx

xxxx xxxx

Chip Erase EEPROM and Flash.

Read Program
Memory

0010 H000

aaaa aaaa

bbbb bbbb

oooo oooo

Load Program
Memory Page

0100 H000

xxxx xxxx

xbbb bbbb

iiii iiii

Write Program
Memory Page

0100 1100

aaaa aaaa

bxxx xxxx

xxxx xxxx

Read EEPROM
Memory

1010 0000

xxxx aaaa

bbbb bbbb

oooo oooo

Write EEPROM
Memory

1100 0000

xxxx aaaa

bbbb bbbb

iiii iiii

Read Lock bits

0101 1000

0000 0000

xxxx xxxx

xxoo oooo

Write Lock bits

1010 1100

111x xxxx

xxxx xxxx

11ii iiii

Read Signature Byte

0011 0000

xxxx xxxx

xxxx xxbb

oooo oooo

Write Fuse bits

1010 1100

1010 0000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.
See Table 119 on page 288 for details.

Write Fuse High Bits

1010 1100

1010 1000

xxxx xxxx

iiii iiii

Set bits = “0” to program, “1” to unprogram.
See Table 118 on page 288 for details.

Write Extended Fuse
bits

1010 1100

1010 0100

xxxx xxxx

xxxx xxii

Set bits = “0” to program, “1” to unprogram.
See Table 119 on page 288 for details.

Read Fuse bits

0101 0000

0000 0000

xxxx xxxx

oooo oooo

Read Fuse bits. “0” = programmed, “1” =
unprogrammed. See Table 119 on page
288 for details.

Read Extendend
Fuse bits

0101 0000

0000 1000

xxxx xxxx

oooo oooo

Read Extended Fuse bits. “0” = pro-grammed,
“1” = unprogrammed. See Table 119 on
page 288 for details.

Read Fuse High Bits

0101 1000

0000 1000

xxxx xxxx

oooo oooo

Read Fuse high bits. “0” = pro-grammed, “1” =
unprogrammed. See Table 118 on page
288 for details.

Read Calibration Byte

0011 1000

xxxx xxxx

0000 00bb

oooo oooo

Read Calibration Byte o at address b.

Note:

304

Operation

Read H (high or low) data o from Program
memory at word address a:b.
Write H (high or low) data i to Program
Memory page at word address b. Data low
byte must be loaded before data high byte is
applied within the same address.
Write Program Memory Page at address a:b.
Read data o from EEPROM memory at
address a:b.
Write data i to EEPROM memory at address
a:b.
Read Lock bits. “0” = programmed, “1” =
unprogrammed. See Table 115 on page
286 for details.
Write Lock bits. Set bits = “0” to program Lock
bits. See Table 115 on page 286 for details.
Read Signature Byte o at address b.

a = address high bits
b = address low bits
H = 0 - Low byte, 1 - High Byte
o = data out
i = data in
x = don’t care

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
SPI Serial
Programming
Characteristics

For characteristics of the SPI module, see “SPI Timing Characteristics” on page 322.

Programming Via
the JTAG Interface

Programming through the JTAG interface requires control of the four JTAG specific pins: TCK,
TMS, TDI, and TDO. Control of the Reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN fuse must be programmed. The device is
default shipped with the Fuse programmed. In addition, the JTD bit in MCUCSR must be
cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit
will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in running mode while still allowing InSystem Programming via the JTAG interface. Note that this technique can not be used when
using the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must
be dedicated for this purpose.
As a definition in this data sheet, the LSB is shifted in and out first of all Shift Registers.

Programming Specific
JTAG Instructions

The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions
useful for Programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format. The text
describes which data register is selected as path between TDI and TDO for each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be
used as an idle state between JTAG sequences. The state machine sequence for changing the
instruction word is shown in Figure 146.

305
2467P–AVR–08/07

Figure 146. State Machine Sequence for Changing the Instruction Word
1

Test-Logic-Reset
0

Run-Test/Idle

Select-DR Scan

Select-IR Scan
0

0
1

Capture-DR

Capture-IR
0

0
Shift-DR

Shift-IR

1
1

Pause-DR

Pause-IR
1

1
0

Exit2-DR

Exit2-IR
1

1
Update-DR

AVR_RESET ($C)

Exit1-IR

Exit1-DR

Update-IR
0

The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking
the device out from the Reset mode. The TAP controller is not reset by this instruction. The one
bit Reset Register is selected as Data Register. Note that the reset will be active as long as there
is a logic 'one' in the Reset Chain. The output from this chain is not latched.
The active states are:
•

PROG_ENABLE ($4)

306

Shift-DR: The Reset Register is shifted by the TCK input.

The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16bit Programming Enable Register is selected as data register. The active states are the
following:
•

Shift-DR: the programming enable signature is shifted into the data register.

•

Update-DR: the programming enable signature is compared to the correct value, and
Programming mode is entered if the signature is valid.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
PROG_COMMANDS
($5)

PROG_PAGELOAD
($6)

The AVR specific public JTAG instruction for entering programming commands via the JTAG
port. The 15-bit Programming Command Register is selected as data register. The active states
are the following:
•

Capture-DR: the result of the previous command is loaded into the data register.

•

Shift-DR: the data register is shifted by the TCK input, shifting out the result of the previous
command and shifting in the new command.

•

Update-DR: the programming command is applied to the Flash inputs.

•

Run-Test/Idle: one clock cycle is generated, executing the applied command.

The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port.
The 2048-bit Virtual Flash Page Load Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page. Internally the Shift Register is 8bit. Unlike most JTAG instructions, the Update-DR state is not used to transfer data from the
Shift Register. The data are automatically transferred to the Flash page buffer byte by byte in the
Shift-DR state by an internal state machine. This is the only active state:
•

Shift-DR: Flash page data are shifted in from TDI by the TCK input, and automatically
loaded into the Flash page one byte at a time.

Note:

PROG_PAGEREAD
($7)

The AVR specific public JTAG instruction to read one full Flash data page via the JTAG port.
The 2056-bit Virtual Flash Page Read Register is selected as data register. This is a virtual scan
chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit. Unlike most JTAG instructions, the Capture-DR state is not used to transfer data to
the Shift Register. The data are automatically transferred from the Flash page buffer byte by
byte in the Shift-DR state by an internal state machine. This is the only active state:
•

Shift-DR: Flash data are automatically read one byte at a time and shifted out on TDO by the
TCK input. The TDI input is ignored.

Note:

Data Registers

The JTAG instruction PROG_PAGELOAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.

The JTAG instruction PROG_PAGEREAD can only be used if the AVR device is the first device in
JTAG scan chain. If the AVR cannot be the first device in the scan chain, the byte-wise programming algorithm must be used.

The data registers are selected by the JTAG instruction registers described in section “Programming Specific JTAG Instructions” on page 305. The data registers relevant for programming
operations are:
•

Reset Register

•

Programming Enable Register

•

Programming Command Register

•

Virtual Flash Page Load Register

•

Virtual Flash Page Read Register

307
2467P–AVR–08/07

Reset Register

The Reset Register is a Test Data Register used to reset the part during programming. It is
required to reset the part before entering programming mode.
A high value in the Reset Register corresponds to pulling the external Reset low. The part is
reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-Out Period (refer to “Clock
Sources” on page 37) after releasing the Reset Register. The output from this Data Register is
not latched, so the reset will take place immediately, as shown in Figure 123 on page 254.

Programming Enable
Register

The Programming Enable Register is a 16-bit register. The contents of this register is compared
to the programming enable signature, binary code 1010_0011_0111_0000. When the contents
of the register is equal to the programming enable signature, programming via the JTAG port is
enabled. The Register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode.
Figure 147. Programming Enable Register
TDI

D
A
T
A

$A370

Programming enable

ClockDR & PROG_ENABLE

TDO

308

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Programming
Command Register

The Programming Command Register is a 15-bit register. This register is used to serially shift in
programming commands, and to serially shift out the result of the previous command, if any. The
JTAG Programming Instruction Set is shown in Table 130. The state sequence when shifting in
the programming commands is illustrated in Figure 149.
Figure 148. Programming Command Register
TDI

S
T
R
O
B
E
S

A
D
D
R
E
S
S
/
D
A
T
A

Flash
EEPROM
Fuses
Lock Bits

TDO

309
2467P–AVR–08/07

Table 130. JTAG Programming Instruction
Set a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction

TDI sequence

TDO sequence

1a. Chip erase

0100011_10000000
0110001_10000000
0110011_10000000
0110011_10000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

1b. Poll for chip erase complete

0110011_10000000

xxxxxox_xxxxxxxx

2a. Enter Flash Write

0100011_00010000

xxxxxxx_xxxxxxxx

2b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

2c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

2d. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

2e. Load Data High Byte

0010111_iiiiiiii

xxxxxxx_xxxxxxxx

2f. Latch Data

0110111_00000000
1110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

2g. Write Flash Page

0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

2h. Poll for Page Write complete

0110111_00000000

xxxxxox_xxxxxxxx

(2)

3a. Enter Flash Read

0100011_00000010

xxxxxxx_xxxxxxxx

3b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

3c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

3d. Read Data Low and High Byte

0110010_00000000
0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo

4a. Enter EEPROM Write

0100011_00010001

xxxxxxx_xxxxxxxx

4b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

4c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

4d. Load Data Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

4e. Latch Data

0110111_00000000
1110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

4f. Write EEPROM Page

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

4g. Poll for Page Write complete

0110011_00000000

xxxxxox_xxxxxxxx

(2)

5a. Enter EEPROM Read

0100011_00000011

xxxxxxx_xxxxxxxx

5b. Load Address High Byte

0000111_aaaaaaaa

xxxxxxx_xxxxxxxx

310

Notes

(2)

(9)

low byte
high byte

(9)

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table 130. JTAG Programming Instruction (Continued)
Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction

TDI sequence

TDO sequence

5c. Load Address Low Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

5d. Read Data Byte

0110011_bbbbbbbb
0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

0100011_01000000

xxxxxxx_xxxxxxxx

6b. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(3)

6c. Write Fuse Extended byte

0111011_00000000
0111001_00000000
0111011_00000000
0111011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

6d. Poll for Fuse Write complete

0110111_00000000

xxxxxox_xxxxxxxx

(2)

6e. Load Data Low Byte(7)

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(3)

6f. Write Fuse High byte

0110111_00000000
0110101_00000000
0110111_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

6g. Poll for Fuse Write complete

0110111_00000000

xxxxxox_xxxxxxxx

(2)

6h. Load Data Low Byte

0010011_iiiiiiii

xxxxxxx_xxxxxxxx

(3)

6i. Write Fuse Low byte

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

6j. Poll for Fuse Write complete

0110011_00000000

xxxxxox_xxxxxxxx

(2)

7a. Enter Lock bit Write

0100011_00100000

xxxxxxx_xxxxxxxx

7b. Load Data Byte

0010011_11iiiiii

xxxxxxx_xxxxxxxx

(4)

7c. Write Lock bits

0110011_00000000
0110001_00000000
0110011_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx
xxxxxxx_xxxxxxxx

(1)

7d. Poll for Lock bit Write complete

0110011_00000000

xxxxxox_xxxxxxxx

(2)

8a. Enter Fuse/Lock bit Read

0100011_00000100

xxxxxxx_xxxxxxxx

8b. Read Extended Fuse Byte(6)

0111010_00000000
0111011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

8c. Read Fuse High Byte(7)

0111110_00000000
0111111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

8d. Read Fuse Low Byte(8)

0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

8e. Read Lock bits(9)

0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_xxoooooo

6a. Enter Fuse Write
(6)

(7)

(9)

Notes

(5)

311
2467P–AVR–08/07

Table 130. JTAG Programming Instruction (Continued)
Set (Continued) a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
Instruction

TDI sequence

TDO sequence

Notes

8f. Read Fuses and Lock bits

0111010_00000000
0111110_00000000
0110010_00000000
0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo
xxxxxxx_oooooooo

(5)
fuse ext. byte
fuse high byte
fuse low byte
lock bits

9a. Enter Signature Byte Read

0100011_00001000

xxxxxxx_xxxxxxxx

9b. Load Address Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

9c. Read Signature Byte

0110010_00000000
0110011_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

10a. Enter Calibration Byte Read

0100011_00001000

xxxxxxx_xxxxxxxx

10b. Load Address Byte

0000011_bbbbbbbb

xxxxxxx_xxxxxxxx

10c. Read Calibration Byte

0110110_00000000
0110111_00000000

xxxxxxx_xxxxxxxx
xxxxxxx_oooooooo

11a. Load No Operation Command
Notes:

312

0100011_00000000
xxxxxxx_xxxxxxxx
0110011_00000000
xxxxxxx_xxxxxxxx
1. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is
normally the case).
2. Repeat until o = “1”.
3. Set bits to “0” to program the corresponding fuse, “1” to unprogram the Fuse.
4. Set bits to “0” to program the corresponding lock bit, “1” to leave the Lock bit unchanged.
5. “0” = programmed, “1” = unprogrammed.
6. The bit mapping for Fuses Extended byte is listed in Table 117 on page 287
7. The bit mapping for Fuses High byte is listed in Table 118 on page 288
8. The bit mapping for Fuses Low byte is listed in Table 119 on page 288
9. The bit mapping for Lock bits byte is listed in Table 115 on page 286
10. Address bits exceeding PCMSB and EEAMSB (Table 123 and Table 124) are don’t care

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 149. State Machine Sequence for Changing/Reading the Data Word
1

Test-Logic-Reset
0

Run-Test/Idle

Select-DR Scan

Select-IR Scan
0

0
1

Capture-DR

Capture-IR
0

0
Shift-DR

Shift-IR

1
1

Pause-DR

Pause-IR
1

1
0

Exit2-DR

Exit2-IR
1

1
Update-DR

Virtual Flash Page
Load Register

Exit1-IR

Exit1-DR

Update-IR
0

The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of
bits in one Flash page. Internally the Shift Register is 8-bit, and the data are automatically transferred to the Flash page buffer byte by byte. Shift in all instruction words in the page, starting
with the LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. This provides an efficient way to load the entire Flash page buffer before executing
Page Write.

313
2467P–AVR–08/07

Figure 150. Virtual Flash Page Load Register
STROBES

TDI

State
machine
ADDRESS

Flash
EEPROM
Fuses
Lock Bits
D
A
T
A

TDO

Virtual Flash Page
Read Register

The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of
bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically
transferred from the Flash data page byte by byte. The first eight cycles are used to transfer the
first byte to the internal Shift Register, and the bits that are shifted out during these 8 cycles
should be ignored. Following this initialization, data are shifted out starting with the LSB of the
first instruction in the page and ending with the MSB of the last instruction in the page. This provides an efficient way to read one full Flash page to verify programming.
Figure 151. Virtual Flash Page Read Register
STROBES

TDI

State
machine
ADDRESS

Flash
EEPROM
Fuses
Lock Bits
D
A
T
A

TDO

Programming
Algorithm

314

All references below of type “1a”, “1b”, and so on, refer to Table 130.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Entering Programming
Mode

1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register.

Leaving Programming
Mode

1. Enter JTAG instruction PROG_COMMANDS.

2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming
Enable Register.

2. Disable all programming instructions by using no operation instruction 11a.
3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming
Enable Register.
4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register.

Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS.
2. Start chip erase using programming instruction 1a.
3. Poll for chip erase complete using programming instruction 1b, or wait for tWLRH_CE (refer
to Table Note: on page 299).
Programming the
Flash

Before programming the Flash a Chip Erase must be performed. See “Performing Chip Erase”
on page 315.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load address high byte using programming instruction 2b.
4. Load address low byte using programming instruction 2c.
5. Load data using programming instructions 2d, 2e and 2f.
6. Repeat steps 4 and 5 for all instruction words in the page.
7. Write the page using programming instruction 2g.
8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to
Table Note: on page 299).
9. Repeat steps 3 to 7 until all data have been programmed.
A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash write using programming instruction 2a.
3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to
Table 123 on page 291) is used to address within one page and must be written as 0.
4. Enter JTAG instruction PROG_PAGELOAD.
5. Load the entire page by shifting in all instruction words in the page, starting with the LSB
of the first instruction in the page and ending with the MSB of the last instruction in the
page.
6. Enter JTAG instruction PROG_COMMANDS.
7. Write the page using programming instruction 2g.
8. Poll for Flash write complete using programming instruction 2h, or wait for tWLRH (refer to
Table Note: on page 299).
9. Repeat steps 3 to 8 until all data have been programmed.

315
2467P–AVR–08/07

Reading the Flash

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load address using programming instructions 3b and 3c.
4. Read data using programming instruction 3d.
5. Repeat steps 3 and 4 until all data have been read.
A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction:
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Flash read using programming instruction 3a.
3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to
Table 123 on page 291) is used to address within one page and must be written as 0.
4. Enter JTAG instruction PROG_PAGEREAD.
5. Read the entire page by shifting out all instruction words in the page, starting with the
LSB of the first instruction in the page and ending with the MSB of the last instruction in
the page. Remember that the first 8 bits shifted out should be ignored.
6. Enter JTAG instruction PROG_COMMANDS.
7. Repeat steps 3 to 6 until all data have been read.

Programming the
EEPROM

Before programming the EEPROM a Chip Erase must be performed. See “Performing Chip
Erase” on page 315.
1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM write using programming instruction 4a.
3. Load address high byte using programming instruction 4b.
4. Load address low byte using programming instruction 4c.
5. Load data using programming instructions 4d and 4e.
6. Repeat steps 4 and 5 for all data bytes in the page.
7. Write the data using programming instruction 4f.
8. Poll for EEPROM write complete using programming instruction 4g, or wait for tWLRH
(refer to Table Note: on page 299).
9. Repeat steps 3 to 8 until all data have been programmed.
Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM

Reading the EEPROM

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable EEPROM read using programming instruction 5a.
3. Load address using programming instructions 5b and 5c.
4. Read data using programming instruction 5d.
5. Repeat steps 3 and 4 until all data have been read.
Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM

316

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Programming the
Fuses

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse write using programming instruction 6a.
3. Load data byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse.
4. Write Extended Fuse byte using programming instruction 6c.
5. Poll for Fuse write complete using programming instruction 6d, or wait for tWLRH (refer to
Table Note: on page 299).
6. Load data byte using programming instructions 6e. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse.
7. Write Fuse high byte using programming instruction 6f.
8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to
Table Note: on page 299).
9. Load data byte using programming instructions 6h. A “0” will program the fuse, a “1” will
unprogram the fuse.
10. Write Fuse low byte using programming instruction 6i.
11. Poll for Fuse write complete using programming instruction 6j, or wait for tWLRH (refer to
Table Note: on page 299).

Programming the Lock
Bits

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Lock bit write using programming instruction 7a.
3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding lock bit, a “1” will leave the lock bit unchanged.
4. Write Lock bits using programming instruction 7c.
5. Poll for Lock bit write complete using programming instruction 7d, or wait for tWLRH (refer
to Table Note: on page 299).

Reading the Fuses
and Lock Bits

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Fuse/Lock bit read using programming instruction 8a.
3. To read all Fuses and Lock bits, use programming instruction 8f.
To only read Extended Fuse byte, use programming instruction 8b.
To only read Fuse high byte, use programming instruction 8c.
To only read Fuse low byte, use programming instruction 8d.
To only read Lock bits, use programming instruction 8e.

Reading the Signature
Bytes

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Signature byte read using programming instruction 9a.
3. Load address $00 using programming instruction 9b.
4. Read first signature byte using programming instruction 9c.
5. Repeat steps 3 and 4 with address $01 and address $02 to read the second and third
signature bytes, respectively.

Reading the
Calibration Byte

1. Enter JTAG instruction PROG_COMMANDS.
2. Enable Calibration byte read using programming instruction 10a.
3. Load address $00 using programming instruction 10b.
4. Read the calibration byte using programming instruction 10c.

317
2467P–AVR–08/07

Electrical Characteristics
Note:

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C

*NOTICE:

Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V

Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins..................... 200.0 - 400.0mA

DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol

Parameter

Condition

Min

VIL

Input Low Voltage except
XTAL1 and RESET pins

VCC=2.7 - 5.5.

VIH

Input High Voltage except
XTAL1 and RESET pins

VIL1

Max

Units

-0.5

0.2 VCC(1)

VCC=2.7 - 5.5.

0.6 VCC(2)

VCC + 0.5

Input Low Voltage
XTAL1 pin

VCC=2.7 - 5.5.

-0.5

0.1 VCC(1)

VIH1

Input High Voltage XTAL1
pin

VCC=2.7 - 5.5.

0.7 VCC(2)

VCC + 0.5

VIL2

Input Low Voltage
RESET pin

VCC=2.7 - 5.5.

-0.5

0.2 VCC(1)

VIH2

Input High Voltage
RESET pin

VCC=2.7 - 5.5.

0.85 VCC(2)

VCC + 0.5

VOL

Output Low Voltage(3)
(Ports A,B,C,D, E, F, G)

IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V

0.7
0.5

V
V

VOH

Output High Voltage(4)
(Ports A,B,C,D, E, F, G)

IOH = -20 mA, VCC = 5V
IOH = -10 mA, VCC = 3V

IIL

Input Leakage
Current I/O Pin

Vcc = 5.5V, pin low
(absolute value)

1.0

µA

IIH

Input Leakage
Current I/O Pin

Vcc = 5.5V, pin high
(absolute value)

1.0

µA

RRST

Reset Pull-up Resistor

kΩ

RPEN

PEN Pull-up Resistor

kΩ

RPU

I/O Pin Pull-up Resistor

kΩ

318

Typ

4.2
2.2

V
V

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
TA = -40°C to 85°C, VCC = 2.7V to 5.5V (unless otherwise noted) (Continued)
Symbol

Parameter

Condition

Power Supply Current
ICC

Power-down mode

Max

Units

Active 4 MHz, VCC = 3V
(ATmega128L)

5.5

Active 8 MHz, VCC = 5V
(ATmega128)

Idle 4 MHz, VCC = 3V
(ATmega128L)

2.5

Idle 8 MHz, VCC = 5V
(ATmega128)

< 15

µA

WDT disabled, VCC = 3V

µA

Analog Comparator
Input Offset Voltage

VCC = 5V
Vin = VCC/2

IACLK

Analog Comparator
Input Leakage Current

VCC = 5V
Vin = VCC/2

Notes:

1.
2.
3.

Typ

WDT enabled, VCC = 3V

VACIO

tACPD

Min

-50

750
Analog Comparator
VCC = 2.7V
ns
500
Propagation Delay
VCC = 5.0V
“Max” means the highest value where the pin is guaranteed to be read as low
“Min” means the lowest value where the pin is guaranteed to be read as high
Although each I/O port can sink more than the test conditions (20 mA at VCC = 5V, 10 mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
TQFP and QFN/MLF Package:
1] The sum of all IOL, for all ports, should not exceed 400 mA.
2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA.
3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA.
4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA.
5] The sum of all IOL, for ports F0 - F7, should not exceed 100 mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
Although each I/O port can source more than the test conditions (20 mA at Vcc = 5V, 10 mA at Vcc = 3V) under steady state
conditions (non-transient), the following must be observed:
TQFP and QFN/MLF Package:
1] The sum of all IOH, for all ports, should not exceed 400 mA.
2] The sum of all IOH, for ports A0 - A7, G2, C3 - C7 should not exceed 100 mA.
3] The sum of all IOH, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 100 mA.
4] The sum of all IOH, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 100 mA.
5] The sum of all IOH, for ports F0 - F7, should not exceed 100 mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.

External Clock
Drive Waveforms

Figure 152. External Clock Drive Waveforms

V IH1
V IL1

319
2467P–AVR–08/07

External Clock
Drive

Table 131. External Clock Drive
VCC = 2.7V to 5.5V

VCC = 4.5V to 5.5V

Min

Max

Min

Max

Units

MHz

Symbol

Parameter

1/tCLCL

Oscillator Frequency

tCLCL

Clock Period

125

62.5

tCHCX

High Time

tCLCX

Low Time

tCLCH

Rise Time

1.6

0.5

μs

tCHCL

Fall Time

1.6

0.5

μs

ΔtCLCL

Change in period from
one clock cycle to the
next

Table 132. External RC Oscillator, Typical Frequencies

Notes:

320

R [kΩ](1)

C [pF]

f(2)

650 kHz

10
22
2.0 MHz
1. R should be in the range 3 kΩ - 100 kΩ, and C should be at least 20 pF. The C values given in
the table includes pin capacitance. This will vary with package type.
2. The frequency will vary with package type and board layout.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Two-wire Serial Interface Characteristics
Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega128 Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 153.
Table 133. Two-wire Serial Bus Requirements
Symbol

Parameter

VIL
VIH
Vhys

(1)

Min

Max

Units

Input Low-voltage

-0.5

0.3 VCC

Input High-voltage

0.7 VCC

VCC + 0.5

–

0.4

20 + 0.1Cb(3)(2)

300

(3)(2)

250

(2)

Hysteresis of Schmitt Trigger Inputs

VOL(1)

Output Low-voltage

tr(1)

Rise Time for both SDA and SCL

tof(1)

Output Fall Time from VIHmin to VILmax

tSP(1)

Spikes Suppressed by Input Filter

Input Current each I/O Pin

Ci(1)

Capacitance for each I/O Pin
SCL Clock Frequency

fSCL

0.05 VCC
3 mA sink current

Hold Time (repeated) START Condition

tLOW

Low Period of the SCL Clock

tHIGH

High period of the SCL clock

tSU;STA

Set-up time for a repeated START condition

tHD;DAT

Data hold time

tSU;DAT

Data setup time

tSU;STO

Setup time for STOP condition

tBUF
1.
2.
3.
4.

(2)

(3)

10 pF < Cb < 400 pF

20 + 0.1Cb
0

0.1 VCC < Vi < 0.9 VCC

-10

µA

–

400

kHz

fSCL ≤ 100 kHz

V CC – 0,4V
---------------------------3mA

1000ns
------------------Cb

fSCL > 100 kHz

V CC – 0,4V
---------------------------3mA

300ns
---------------Cb

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

(6)

fSCL ≤ 100 kHz

4.7

–

µs

(7)

fSCL > 100 kHz

1.3

–

µs

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

fSCL ≤ 100 kHz

4.7

–

µs

fSCL > 100 kHz

0.6

–

µs

fSCL ≤ 100 kHz

3.45

µs

fSCL > 100 kHz

0.9

µs

fSCL ≤ 100 kHz

250

–

fSCL > 100 kHz

100

–

fSCL ≤ 100 kHz

4.0

–

µs

fSCL > 100 kHz

0.6

–

µs

4.7

–

µs

fCK(4)

> max(16fSCL, 250kHz)

Value of Pull-up resistor

tHD;STA

Notes:

Condition

Bus free time between a STOP and START
fSCL ≤ 100 kHz
condition
In ATmega128, this parameter is characterized and not 100% tested.
Required only for fSCL > 100 kHz.
Cb = capacitance of one bus line in pF.
fCK = CPU clock frequency

(5)

321
2467P–AVR–08/07

5. This requirement applies to all ATmega128 Two-wire Serial Interface operation. Other devices
connected to the Two-wire Serial Bus need only obey the general fSCL requirement.
6. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/fSCL - 2/fCK),
thus fCK must be greater than 6 MHz for the low time requirement to be strictly met at fSCL =
100 kHz.
7. The actual low period generated by the ATmega128 Two-wire Serial Interface is (1/fSCL - 2/fCK),
thus the low time requirement will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still,
ATmega128 devices connected to the bus may communicate at full speed (400 kHz) with other
ATmega128 devices, as well as any other device with a proper tLOW acceptance margin.

Figure 153. Two-wire Serial Bus Timing
tHIGH

tof

tLOW

SCL
tSU;STA

tHD;STA

tHD;DAT

tSU;DAT

tSU;STO

SDA

tBUF

SPI Timing
Characteristics

See Figure 154 and Figure 155 for details.
Table 134. SPI Timing Parameters
Description

Mode

SCK period

Master

See Table 72

SCK high/low

Master

50% duty cycle

Rise/Fall time

Master

3.6

Setup

Master

Hold

Master

Out to SCK

Master

0.5 • tsck

SCK to out

Master

SCK to out high

Master

SS low to out

Slave

SCK period

Slave

4 • tck

Slave

2 • tck

11
12

Rise/Fall time

Slave

Setup

Slave

Hold

Slave

SCK to out

Slave

SCK to SS high

Slave

SS high to tri-state

Slave

SS low to SCK

Slave

Note:

322

SCK high/low

(1)

Min

Typ

Max

1.6

µs

20
10
2 • tck

1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK >12 MHz

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 154. SPI Interface Timing Requirements (Master Mode)
SS
6

SCK
(CPOL = 0)
2

SCK
(CPOL = 1)
4

MISO
(Data Input)

MSB

...

LSB

MOSI
(Data Output)

MSB

...

LSB

Figure 155. SPI Interface Timing Requirements (Slave Mode)
18

SS
10

SCK
(CPOL = 0)
11

SCK
(CPOL = 1)
13

MOSI
(Data Input)

MSB

...

LSB
17

MISO
(Data Output)

MSB

...

LSB

323
2467P–AVR–08/07

ADC Characteristics
Table 135. ADC Characteristics, Single Ended Channels
Symbol

Parameter

Condition

Resolution

Single Ended Conversion

Typ(1)

Bits
LSB

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 1 MHz

3.25

LSB

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz
Noise Reduction mode

1.5

LSB

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 1 MHz
Noise Reduction mode

3.75

LSB

Integral Non-Linearity (INL)

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz

0.75

LSB

Differential Non-Linearity (DNL)

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz

0.5

LSB

Gain Error

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz

LSB

Offset error

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz

LSB

Clock Frequency

Conversion Time

Analog Supply Voltage

VREF

Reference Voltage
Input Voltage

1000

VINT

Internal Voltage Reference

RREF

Reference Input Resistance

RAIN

Analog Input Resistance

kHz

260

µs
(3)

(2)

VCC - 0.3

VCC + 0.3

2.0

AVCC

GND

VREF

38.5

kHz

2.7

Input Bandwidth

324

Units

1.5

AVCC

Notes:

Max(1)

Single Ended Conversion
VREF = 4V, VCC = 4V
ADC clock = 200 kHz

Absolute Accuracy
(Including INL, DNL, Quantization Error, Gain
and Offset Error)

VIN

Min(1)

2.3

2.56
32

kΩ

100

MΩ

1. Values are guidelines only.
2. Minimum for AVCC is 2.7V.
3. Maximum for AVCC is 5.5V

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table 136. ADC Characteristics, Differential Channels
Symbol

Parameter

Max(1)

Units

Bits

Gain = 10x

Bits

Gain = 200x

Bits

Condition
Gain =

Resolution

Absolute Accuracy

Integral Non-Linearity (INL)
(Accuracy after Calibration for Offset and
Gain Error)

Offset Error

LSB

Gain = 10x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Gain = 200x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

1.5

LSB

Gain = 10x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Gain = 200x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

1.5

Gain = 10x

1.5

Gain = 200x

0.5

Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Gain = 10x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Gain = 200x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

LSB

Clock Frequency

200

Conversion Time

260

µs

VCC + 0.3

2.0

AVCC - 0.5

GND

VCC

Input Differential Voltage

-VREF/Gain

VREF/Gain

ADC Conversion Output

-511

511

LSB

Analog Supply Voltage

VREF

Reference Voltage

VDIFF

kHz

(3)

AVCC

VIN

Typ(1)

Gain = 1x
VREF = 4V, VCC = 5V
ADC clock = 50 - 200 kHz

Gain =
Gain Error

Min(1)

Input Voltage

Input Bandwidth

VCC - 0.3(2)

kHz

325
2467P–AVR–08/07

Table 136. ADC Characteristics, Differential Channels (Continued)
Symbol

Parameter

VINT

Internal Voltage Reference

RREF

Reference Input Resistance

RAIN

Analog Input Resistance

Notes:

326

Condition

Min(1)

Typ(1)

Max(1)

Units

2.3

2.56

2.7

kΩ

100

MΩ

1. Values are guidelines only.
2. Minimum for AVCC is 2.7V.
3. Maximum for AVCC is 5.5V.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
External Data Memory Timing
Table 137. External Data Memory Characteristics, 4.5 - 5.5 Volts, No Wait-state
8 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tLHLL

ALE Pulse Width

115

1.0tCLCL-10

tAVLL

Address Valid A to ALE Low

57.5

0.5tCLCL-5(1)

tLLAX_ST

Address Hold After ALE Low,
write access

tLLAX_LD

Address Hold after ALE Low,
read access

ns
ns
(1)

tAVLLC

Address Valid C to ALE Low

57.5

0.5tCLCL-5

tAVRL

Address Valid to RD Low

115

1.0tCLCL-10

tAVWL

Address Valid to WR Low

115

1.0tCLCL-10

tLLWL

ALE Low to WR Low

47.5

tLLRL

ALE Low to RD Low

tDVRH

Data Setup to RD High

tRLDV

Read Low to Data Valid

tRHDX

Data Hold After RD High

tRLRH

RD Pulse Width

47.5

67.5

0.5tCLCL-15(2)

0.5tCLCL+5(2)

67.5

(2)

0.5tCLCL-15

0.5tCLCL+5

1.0tCLCL-50

115

1.0tCLCL-10

ns
ns

tDVWL

Data Setup to WR Low

42.5

tWHDX

Data Hold After WR High

115

1.0tCLCL-10

tDVWH

Data Valid to WR High

125

1.0tCLCL

tWLWH

WR Pulse Width

115

1.0tCLCL-10

Notes:

0.5tCLCL-20

(1)

1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 138. External Data Memory Characteristics, 4.5 - 5.5 Volts, 1 Cycle Wait-state
8 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

240

2.0tCLCL-10

tDVWH

Data Valid to WR High

240

2.0tCLCL

tWLWH

WR Pulse Width

240

2.0tCLCL-10

200

2.0tCLCL-50

327
2467P–AVR–08/07

Table 139. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

365

3.0tCLCL-10

tDVWH

Data Valid to WR High

375

3.0tCLCL

tWLWH

WR Pulse Width

365

3.0tCLCL-10

325

3.0tCLCL-50

Table 140. External Data Memory Characteristics, 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

365

3.0tCLCL-10

tWHDX

Data Hold After WR High

240

2.0tCLCL-10

tDVWH

Data Valid to WR High

375

3.0tCLCL

tWLWH

WR Pulse Width

365

3.0tCLCL-10

325

3.0tCLCL-50

Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tLHLL

ALE Pulse Width

235

tCLCL-15

tAVLL

Address Valid A to ALE Low

115

0.5tCLCL-10(1)

tLLAX_ST

Address Hold After ALE Low,
write access

tLLAX_LD

Address Hold after ALE Low,
read access

ns
(1)

tAVLLC

Address Valid C to ALE Low

115

tAVRL

Address Valid to RD Low

235

1.0tCLCL-15

tAVWL

Address Valid to WR Low

235

1.0tCLCL-15

tLLWL

ALE Low to WR Low

115

tLLRL

ALE Low to RD Low

115

tDVRH

Data Setup to RD High

tRLDV

Read Low to Data Valid

tRHDX

Data Hold After RD High

328

0.5tCLCL-10

130
130

0.5tCLCL-10

(2)

0.5tCLCL-10

(2)

ns
ns
0.5tCLCL+5

(2)

0.5tCLCL+5

(2)

45
190

ns
1.0tCLCL-60

ns
ns

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table 141. External Data Memory Characteristics, 2.7 - 5.5 Volts, No Wait-state (Continued)
4 MHz Oscillator

Symbol

Parameter

Min

tRLRH

RD Pulse Width

235

Max

Variable Oscillator
Min

Max

1.0tCLCL-15

Unit
ns

(1)

tDVWL

Data Setup to WR Low

105

tWHDX

Data Hold After WR High

235

1.0tCLCL-15

tDVWH

Data Valid to WR High

250

1.0tCLCL

0.5tCLCL-20

WR Pulse Width
235
1.0tCLCL-15
16 tWLWH
Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.

Table 142. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

485

2.0tCLCL-15

tDVWH

Data Valid to WR High

500

2.0tCLCL

tWLWH

WR Pulse Width

485

2.0tCLCL-15

440

2.0tCLCL-60

Table 143. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

735

3.0tCLCL-15

tDVWH

Data Valid to WR High

750

3.0tCLCL

tWLWH

WR Pulse Width

735

3.0tCLCL-15

690

3.0tCLCL-60

Table 144. External Data Memory Characteristics, 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1
4 MHz Oscillator
Min

Max

Variable Oscillator

Symbol

Parameter

Min

Max

Unit

1/tCLCL

Oscillator Frequency

0.0

MHz

tRLDV

Read Low to Data Valid

tRLRH

RD Pulse Width

735

3.0tCLCL-15

tWHDX

Data Hold After WR High

485

2.0tCLCL-15

tDVWH

Data Valid to WR High

750

3.0tCLCL

tWLWH

WR Pulse Width

735

3.0tCLCL-15

690

3.0tCLCL-60

329
2467P–AVR–08/07

Figure 156. External Memory Timing (SRWn1 = 0, SRWn0 = 0
T1

System Clock (CLKCPU )
1

ALE
4

A15:8

Prev. addr.

Address
15

DA7:0

Prev. data

Address

13
XX

Data
14

Write

WR
9

DA7:0 (XMBK = 0)

Data

Read

Address

10
8

Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
T1

System Clock (CLKCPU )
1

ALE
4

A15:8

Prev. addr.

Address
15
3a

DA7:0

Prev. data

Address

13
Data

Write

WR
3b

Address

Data

Read

DA7:0 (XMBK = 0)

10
8

330

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 158. External Memory Timing (SRWn1 = 1, SRWn0 = 0)
T1

System Clock (CLKCPU )
1

ALE
4

A15:8

7
Address

Prev. addr.

DA7:0

Prev. data

Address

13
XX

Data
14

Write

WR
9

DA7:0 (XMBK = 0)

Address

Read

Data
10
8

Figure 159. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1)
T1

System Clock (CLKCPU )
1

ALE
4

A15:8

7
Address

Prev. addr.

DA7:0

Prev. data

Address

13
XX

Data
14

Write

WR
9

3b
Address

Data

Read

DA7:0 (XMBK = 0)

10
8

Note:

1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the
RAM (internal or external).

331
2467P–AVR–08/07

ATmega128
Typical
Characteristics

The following charts show typical behavior. These figures are not tested during manufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock
source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.

Active Supply Current

Figure 160. Active Supply Current vs. Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
3.5

5.5 V

5.0 V
4.5 V
4.0 V
3.3 V
2.7 V

ICC (mA)

2.5
2
1.5
1
0.5
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency (MHz)

332

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 161. Active Supply Current vs. Frequency (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
45
40

5.0 V

4.5 V

ICC (mA)

30
25
20

4.0 V

3.6 V
3.3 V
3.0 V
2.7 V

10
5
0
0

Frequency (MHz)

Figure 162. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
4

25 ˚C
-40 ˚C
85 ˚C

ICC (mA)

3.5

2.5

1.5
2.5

3.5

4.5

5.5

VCC (V)

333
2467P–AVR–08/07

Figure 163. Active Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz
8

-40 °C
25 °C
85 °C

7
6

ICC (mA)

5
4
3
2
1
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 164. Active Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz
14

-40 °C
25 °C
85 °C

ICC (mA)

0
2.5

3.5

4.5

5.5

VCC (V)

334

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 165. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
25

-40 °C
25 °C
85 °C

ICC (mA)

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 166. Active Supply Current vs. VCC (32 kHz External Oscillator)
ACTIVE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR
140

120

25 °C

ICC (uA)

100

0
2.5

3.5

4.5

5.5

VCC (V)

335
2467P–AVR–08/07

Idle Supply Current

Figure 167. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz
1.4

1.2

5.5 V

ICC (mA)

5.0 V
4.5 V

0.8

4.0 V
3.6 V
3.3 V
3.0 V
2.7 V

0.6

0.4

0.2

0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency (MHz)

Figure 168. Idle Supply Current vs. Frequency (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz

5.5 V
20

5.0 V
4.5 V

ICC (mA)

4.0 V

3.6 V
3.3 V
5

3.0 V
2.7 V

0
0

Frequency (MHz)

336

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 169. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
1.6

85 °C
25 °C
-40 °C

1.4
1.2

ICC (mA)

1
0.8
0.6
0.4
0.2
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 170. Idle Supply Current vs. VCC (Internal RC Oscillator, 2 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 2 MHz
3

85 °C
25 °C
-40 °C

2.5

ICC (mA)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

337
2467P–AVR–08/07

Figure 171. Idle Supply Current vs. VCC (Internal RC Oscillator, 4 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 4 MHz
6

-40 °C
25 °C
85 °C

ICC (mA)

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 172. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
12

-40 °C
25 °C
85 °C

ICC (mA)

0
2.5

3.5

4.5

5.5

VCC (V)

338

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 173. Idle Supply Current vs. VCC (32 kHz External Oscillator)
IDLE SUPPLY CURRENT vs. VCC
32 kHz EXTERNAL OSCILLATOR
60

25 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

Power-down Supply
Current

Figure 174. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
4.5
4

85 ˚C

3.5

ICC (uA)

3
2.5
2
1.5

-40 ˚C
25 ˚C

1
0.5
0
2.5

3.5

4.5

5.5

VCC (V)

339
2467P–AVR–08/07

Figure 175. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
35
30

85 ˚C
25 ˚C
-40 ˚C

ICC (uA)

25
20
15
10
5
0
2.5

3.5

4.5

5.5

VCC (V)

Power-save Supply
Current

Figure 176. Power-save Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-SAVE SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
16

25 °C
14
12

ICC (uA)

10
8
6
4
2
0
2.5

3.5

4.5

5.5

VCC (V)

340

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Standby Supply
Current

Figure 177. Standby Supply Current vs. VCC,
STANDBY SUPPLY CURRENT vs. VCC
0.2

6 MHz Xtal

0.18

6 MHz Res

0.16
0.14

4 MHz Res
4 MHz Xtal

ICC (mA)

0.12
0.1

2 MHz Res
2 MHz Xtal

0.08

455 kHz Res
1 MHz Res

0.06
0.04
0.02
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 178. Standby Supply Current vs. VCC (CKOPT programmed)
STANDBY SUPPLY CURRENT vs. VCC
CKOPT programmed
2.5

16 MHz Xtal
2

12 MHz Xtal

1.5

ICC (mA)

6 MHz Xtal
4 MHz Xtal

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

341
2467P–AVR–08/07

Pin Pull-up

Figure 179. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V
160
140

85 °C

25 °C

120

-40 °C
IOP (uA)

100
80
60
40
20
0
0

0.5

1.5

2.5

3.5

4.5

VOP (V)

Figure 180. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V
80

85 °C 25 °C
70
60

-40 °C

IOP (uA)

50
40
30
20
10
0
0

0.5

1.5

2.5

VOP (V)

342

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Pin Driver Strength

Figure 181. I/O Pin Source Current vs. Output Voltage (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
90
80

-40 °C

25 °C

IOH (mA)

85 °C

50
40
30
20
10
0
2.5

3.5

4.5

VOH (V)

Figure 182. I/O Pin Source Current vs. Output Voltage (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
30

-40 °C
25

25 °C
85 °C

IOH (mA)

0
0.5

1.5

2.5

VOH (V)

343
2467P–AVR–08/07

Figure 183. I/O Pin Sink Current vs. Output Voltage (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V
90

-40 °C

25 °C

IOL (mA)

85 °C

50
40
30
20
10
0
0

0.5

1.5

2.5

VOL (V)

Figure 184. I/O Pin Sink Current vs. Output Voltage, VCC = 2.7V
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V
35

-40 °C
30

25 °C
25

IOL (mA)

85 °C
20

0
0

0.5

1.5

2.5

VOL (V)

344

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Pin Thresholds and
Hysteresis

Figure 185. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2.2

-40 °C
25 °C
85 °C

Threshold (V)

1.8

1.6

1.4

1.2

1
2.5

3.5

4.5

5.5

VCC (V)

Figure 186. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘0’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
1.6

-40 °C
25 °C
85 °C

1.5

Threshold (V)

1.4
1.3
1.2
1.1
1
0.9
0.8
2.5

3.5

4.5

5.5

VCC (V)

345
2467P–AVR–08/07

Figure 187. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.7

85 °C
25 °C
-40 °C

0.6

Input Hysteresis (V)

0.5

0.4

0.3

0.2

0.1

0
2.5

3.5

4.5

5.5

VCC (V)

BOD Thresholds and
Analog Comparator
Offset

Figure 188. BOD Threshold vs. Temperature (BODLEVEL is 4.0V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 4.0 V
4.4

4.2

Threshold (V)

Rising VCC
4

Falling VCC
3.8

3.6

3.4
-60

-40

-20

100

Temperature (C)

346

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 189. BOD Threshold vs. Temperature (BODLEVEL is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 2.7 V
3

2.8

Threshold (V)

Rising VCC
2.6

Falling VCC
2.4

2.2

2
-60

-40

-20

100

Temperature (C)

Figure 190. Bandgap Voltage vs. Operating Voltage
BANDGAP VOLTAGE vs. VCC
1.275

85 °C

1.27

Bandgap Voltage (V)

-40 °C
1.265

25 °C

1.26

1.255

1.25
2.5

3.5

4.5

5.5

VCC (V)

347
2467P–AVR–08/07

Internal Oscillator
Speed

Figure 191. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
1220

-40 °C
25 °C

1200

85 °C
1180

FRC (kHz)

1160
1140
1120
1100
1080
1060
2.5

3.5

4.5

5.5

VCC (V)

Figure 192. Calibrated 1 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
1.02

5.5 V
5.0 V
4.5 V
4.0 V
3.6 V
3.3 V

FRC (MHz)

0.98

0.96

0.94

2.7 V

0.92

0.9
-60

-40

-20

100

Temperature

348

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 193. Calibrated 1 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 1MHz RC OSCILLATOR FREQUENCY vs. Vcc
1.02

-40 ˚C
25 ˚C
85 ˚C

FRC (MHz)

0.98

0.96

0.94

0.92

0.9
2.5

3.5

4.5

5.5

VCC (V)

Figure 194. 1 MHz RC Oscillator Frequency vs. Osccal Value
1MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
1.5

25 ˚C

1.4
1.3
1.2
FRC (MHz)

1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0

112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE

349
2467P–AVR–08/07

Figure 195. Calibrated 2 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
2.05

5.5 V
5.0 V

FRC (MHz)

1.95

4.5 V
4.0 V

1.9

3.6 V
3.3 V

1.85

2.7 V

1.8

1.75
-60

-40

-20

100

Temperature

Figure 196. Calibrated 2 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 2MHz RC OSCILLATOR FREQUENCY vs. Vcc
2.05

-40 ˚C
25 ˚C

FRC (MHz)

85 ˚C

1.95

1.9

1.85

1.8
2.5

3.5

4.5

5.5

VCC (V)

350

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 197. 2 MHz RC Oscillator Frequency vs. Osccal Value
2MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
4

25 °C

3.5

FRC (MHz)

3
2.5
2
1.5
1
0.5
0
0

112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE

Figure 198. Calibrated 4 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4.1
4.05
4

5.5 V
5.0 V
4.5 V

FRC (MHz)

3.95
3.9
3.85

4.0 V

3.8

3.6 V
3.3 V

3.75
3.7

2.7 V

3.65
3.6
-60

-40

-20

100

Temperature

351
2467P–AVR–08/07

Figure 199. Calibrated 4 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc
4.1

-40 ˚C

4.05

25 ˚C

85 ˚C

FRC (MHz)

3.95
3.9
3.85
3.8
3.75
3.7
3.65
3.6
2.5

3.5

4.5

5.5

VCC (V)

Figure 200. 4 MHz RC Oscillator Frequency vs. Osccal Value
4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
9
8

25 ˚C

FRC (MHz)

6
5
4
3
2
1
0
0

112 128 144 160 176 192 208 224 240
OSCCAL VALUE

352

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 201. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.4
8.2
8

5.5 V

FRC (MHz)

7.8

5.0 V

7.6

4.5 V
7.4

4.0 V

7.2

3.6 V

3.3 V

6.8

2.7 V

6.6
-60

-40

-20

100

Temperature

Figure 202. Calibrated 8 MHz RC Oscillator Frequency vs. VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc
8.4
8.2

-40 ˚C

25 ˚C
85 ˚C

FRC (MHz)

7.8
7.6
7.4
7.2
7
6.8
6.6
2.5

3.5

4.5

5.5

VCC (V)

353
2467P–AVR–08/07

Figure 203. 8 MHz RC Oscillator Frequency vs. Osccal Value
8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
16

25 °C
14

FRC (MHz)

12
10
8
6
4
2
0
0

112 128 144 160 176 192 208 224 240 256
OSCCAL VALUE

Current Consumption
of Peripheral Units

Figure 204. Brownout Detector Current vs. VCC
BROWNOUT DETECTOR CURRENT vs. VCC
25

-40 °C
25 °C
85 °C

ICC (uA)

0
2.5

3.5

4.5

5.5

VCC (V)

354

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 205. ADC Current vs. AVCC (ADC at 50 kHz)
ADC CURRENT vs. AVCC
ADC AT 50KHz
600

-40 °C
25 °C
85 °C

500

ICC (uA)

400

300

200

100

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 206. ADC Current vs. AVCC (ADC at 1 MHz)
AREF CURRENT vs. AVCC
250

25 °C
85 °C
-40 °C

200

ICC (uA)

150

100

0
2.5

3.5

4.5

5.5

VCC (V)

355
2467P–AVR–08/07

Figure 207. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. VCC
100

85 °C
90

25 °C
-40 °C

80
70

ICC (uA)

60
50
40
30
20
10
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 208. Programming Current vs. VCC
PROGRAMMING CURRENT vs. VCC
9

-40 ˚C

8
7

25 ˚C

ICC (mA)

85 ˚C

5
4
3
2
1
0
2.5

3.5

4.5

5.5

VCC (V)

356

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Current Consumption
in Reset and Reset
Pulse width

Figure 209. Reset Supply Current vs. VCC (0.1 - 1.0 MHz, Excluding Current Through The
Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
4.5
4

5.5 V

3.5

5.0 V
4.5 V
4.0 V
3.6 V
3.3 V
3.0 V
2.7 V

ICC (mA)

3
2.5
2
1.5
1
0.5
0
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Frequency (MHz)

Figure 210. Reset Supply Current vs. VCC (1 - 20 MHz, Excluding Current Through The Reset
Pull-up)
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP
40
35

5.5 V

5.0 V
4.5 V

ICC (mA)

4.0 V
20

3.6 V
3.3 V
3.0 V
2.7 V

15
10
5
0
0

Frequency (MHz)

357
2467P–AVR–08/07

Figure 211. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5.0V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
120

25 °C

-40 °C
100

85 °C
IRESET (uA)

0
0

VRESET (V)

Figure 212. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V
60

25 °C

-40 °C
50

85 °C

IRESET (uA)

0
0

0.5

1.5

2.5

VRESET (V)

358

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Figure 213. Reset Input Threshold Voltage vs. VCC (VIH, Reset Pin Read as ‘1’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1'
2.5

Threshold (V)

-40 °C
1.5

25 °C
85 °C

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

Figure 214. Reset Input Threshold Voltage vs. VCC (VIL, Reset Pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5

-40 ˚C
25 ˚C
85 ˚C

Threshold (V)

1.5

0.5

0
2.5

3.5

4.5

5.5

VCC (V)

359
2467P–AVR–08/07

Figure 215. Reset Input Pin Hysteresis vs. VCC
RESET INPUT PIN HYSTERESIS vs. VCC
0.5
0.45

-40 ˚C

Input Hysteresis (mV)

0.4
0.35
0.3
0.25
0.2

25 ˚C
0.15
0.1

85 ˚C

0.05
0
2.5

3.5

4.5

5.5

VCC (V)

Figure 216. Reset Pulse width vs. VCC (External Clock, 1 MHz)
RESET PULSE WIDTH vs. VCC
External Clock, 1 MHz
1.2

Pulsewidth (us)

0.8

0.6

85 °C
25 °C
-40 °C

0.4

0.2

0
2.5

3.5

4.5

5.5

VCC (V)

360

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Register Summary
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

($FF)

Reserved

–

..
($9E)

Reserved

–

Reserved

–

($9D)

UCSR1C

–

UMSEL1

UPM11

UPM10

USBS1

UCSZ11

UCSZ10

UCPOL1

($9C)

UDR1

USART1 I/O Data Register

Page

191
189

($9B)

UCSR1A

RXC1

TXC1

UDRE1

FE1

DOR1

UPE1

U2X1

MPCM1

189

($9A)

UCSR1B

RXCIE1

TXCIE1

UDRIE1

RXEN1

TXEN1

UCSZ12

RXB81

TXB81

190

($99)

UBRR1L

($98)

UBRR1H

–

USART1 Baud Rate Register Low

192
USART1 Baud Rate Register High

192

($97)

Reserved

–

($96)

Reserved

–

($95)
($94)

UCSR0C

–

UMSEL0

UPM01

UPM00

USBS0

UCSZ01

UCSZ00

UCPOL0

Reserved

–

($93)

Reserved

–

($92)

Reserved

–

($91)

Reserved

–

($90)

UBRR0H

–

($8F)

Reserved

–

USART0 Baud Rate Register High

191

192

($8E)

Reserved

–

($8D)

Reserved

–

($8C)

TCCR3C

FOC3A

FOC3B

FOC3C

–

137

($8B)

TCCR3A

COM3A1

COM3A0

COM3B1

COM3B0

COM3C1

COM3C0

WGM31

WGM30

133

ICNC3

ICES3

–

WGM33

WGM32

CS32

CS31

CS30

136

($8A)

TCCR3B

($89)

TCNT3H

Timer/Counter3 – Counter Register High Byte

138

($88)

TCNT3L

Timer/Counter3 – Counter Register Low Byte

138

($87)

OCR3AH

Timer/Counter3 – Output Compare Register A High Byte

138

($86)

OCR3AL

Timer/Counter3 – Output Compare Register A Low Byte

138

($85)

OCR3BH

Timer/Counter3 – Output Compare Register B High Byte

139

($84)

OCR3BL

Timer/Counter3 – Output Compare Register B Low Byte

139

($83)

OCR3CH

Timer/Counter3 – Output Compare Register C High Byte

139

($82)

OCR3CL

Timer/Counter3 – Output Compare Register C Low Byte

139

($81)

ICR3H

Timer/Counter3 – Input Capture Register High Byte

139

($80)
($7F)

ICR3L

Timer/Counter3 – Input Capture Register Low Byte

Reserved

–

139
–

–

($7E)

Reserved

–

($7D)

ETIMSK

–

TICIE3

OCIE3A

OCIE3B

TOIE3

OCIE3C

OCIE1C

140

($7C)
($7B)

ETIFR

–

ICF3

OCF3A

OCF3B

TOV3

OCF3C

OCF1C

141

Reserved

–

($7A)

TCCR1C

FOC1A

FOC1B

FOC1C

–

($79)

OCR1CH

Timer/Counter1 – Output Compare Register C High Byte

138

($78)
($77)

OCR1CL

Timer/Counter1 – Output Compare Register C Low Byte

138

Reserved

–

($76)

Reserved

–

($75)

Reserved

–

($74)

TWCR

TWINT

TWEA

TWSTA

TWSTO

TWWC

TWEN

–

TWIE

206

($73)

TWDR

($72)

TWAR

TWA6

TWA5

TWA4

TWS7

TWS6

TWS5

Two-wire Serial Interface Data Register

208

TWA3

TWA2

TWA1

TWA0

TWGCE

208

TWS4

TWS3

–

TWPS1

TWPS0

207

($71)

TWSR

($70)

TWBR

Two-wire Serial Interface Bit Rate Register

($6F)
($6E)

OSCCAL

Oscillator Calibration Register

Reserved

137

206
42

–

($6D)

XMCRA

–

SRL2

SRL1

SRL0

SRW01

SRW00

SRW11

($6C)

XMCRB

XMBK

–

XMM2

XMM1

–
31
XMM0

($6B)

Reserved

–

($6A)
($69)

EICRA

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

Reserved

–

($68)

SPMCSR

SPMIE

RWWSB

–

RWWSRE

BLBSET

PGWRT

PGERS

SPMEN

($67)

Reserved

–

($66)

Reserved

–

($65)

PORTG

–

PORTG4

PORTG3

PORTG2

PORTG1

PORTG0

($64)

DDRG

–

DDG4

DDG3

DDG2

DDG1

DDG0

90
277

($63)

PING

–

PING4

PING3

PING2

PING1

PING0

($62)

PORTF

PORTF7

PORTF6

PORTF5

PORTF4

PORTF3

PORTF2

PORTF1

PORTF0

361
2467P–AVR–08/07

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

($61)

DDRF

DDF7

DDF6

DDF5

DDF4

DDF3

DDF2

DDF1

DDF0

($60)

Reserved

–

$3F ($5F)

SREG

$3E ($5E)

SPH

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

$3D ($5D)

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

$3C ($5C)

XDIV

XDIVEN

XDIV6

XDIV5

XDIV4

XDIV3

XDIV2

XDIV1

XDIV0

$3B ($5B)

RAMPZ

–

RAMPZ0

$3A ($5A)

EICRB

ISC71

ISC70

ISC61

ISC60

ISC51

ISC50

ISC41

ISC40

$39 ($59)

EIMSK

INT7

INT6

INT5

INT4

INT3

INT2

INT1

INT0

$38 ($58)

EIFR

INTF7

INTF6

INTF5

INTF4

INTF3

INTF

INTF1

INTF0

$37 ($57)

TIMSK

OCIE2

TOIE2

TICIE1

OCIE1A

OCIE1B

TOIE1

OCIE0

TOIE0

109, 139, 159

$36 ($56)

TIFR

OCF2

TOV2

ICF1

OCF1A

OCF1B

TOV1

OCF0

TOV0

109, 141, 159

$35 ($55)

MCUCR

SRE

SRW10

SM1

SM0

SM2

IVSEL

IVCE

31, 45, 64

$34 ($54)

MCUCSR

JTD

–

JTRF

WDRF

BORF

EXTRF

PORF

54, 254

$33 ($53)

TCCR0

FOC0

WGM00

COM01

COM00

WGM01

CS02

CS01

CS00

$32 ($52)

TCNT0

$31 ($51)

OCR0

$30 ($50)

ASSR

–

AS0

TCN0UB

OCR0UB

TCR0UB

Timer/Counter0 (8 Bit)

104
106

Timer/Counter0 Output Compare Register

106
107

$2F ($4F)

TCCR1A

COM1A1

COM1A0

COM1B1

COM1B0

COM1C1

COM1C0

WGM11

WGM10

133

$2E ($4E)

TCCR1B

ICNC1

ICES1

–

WGM13

WGM12

CS12

CS11

CS10

136

$2D ($4D)

TCNT1H

Timer/Counter1 – Counter Register High Byte

$2C ($4C)

TCNT1L

Timer/Counter1 – Counter Register Low Byte

138

$2B ($4B)

OCR1AH

Timer/Counter1 – Output Compare Register A High Byte

138

$2A ($4A)

OCR1AL

Timer/Counter1 – Output Compare Register A Low Byte

138

$29 ($49)

OCR1BH

Timer/Counter1 – Output Compare Register B High Byte

138

$28 ($48)

OCR1BL

Timer/Counter1 – Output Compare Register B Low Byte

138

$27 ($47)

ICR1H

Timer/Counter1 – Input Capture Register High Byte

139

$26 ($46)

ICR1L

$25 ($45)

TCCR2

Timer/Counter1 – Input Capture Register Low Byte

$24 ($44)

TCNT2

Timer/Counter2 (8 Bit)

$23 ($43)

OCR2

Timer/Counter2 Output Compare Register

$22 ($42)

OCDR

$21 ($41)
$20 ($40)

FOC2

WGM20

COM21

COM20

IDRD/OCDR7

OCDR6

OCDR5

OCDR4

WDTCR

–

SFIOR

TSM

–

WGM21

CS22

139
CS21

CS20

157
159
159

OCDR3

OCDR2

OCDR1

WDCE

WDE

WDP2

WDP1

WDP0

–

ACME

PUD

PSR0

PSR321

73, 110, 144, 227

–

OCDR0

EEPROM Address Register High

251

$1F ($3F)

EEARH

$1E ($3E)

EEARL

EEPROM Address Register Low Byte

21
21

$1D ($3D)

EEDR

EEPROM Data Register

$1C ($3C)

EECR

–

EERIE

EEMWE

EEWE

EERE

$1B ($3B)

PORTA

PORTA7

PORTA6

PORTA5

PORTA4

PORTA3

PORTA2

PORTA1

PORTA0

22
87

$1A ($3A)

DDRA

DDA7

DDA6

DDA5

DDA4

DDA3

DDA2

DDA1

DDA0

$19 ($39)

PINA

PINA7

PINA6

PINA5

PINA4

PINA3

PINA2

PINA1

PINA0

$18 ($38)

PORTB

PORTB7

PORTB6

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

$17 ($37)

DDRB

DDB7

DDB6

DDB5

DDB4

DDB3

DDB2

DDB1

DDB0

$16 ($36)

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

$15 ($35)

PORTC

PORTC7

PORTC6

PORTC5

PORTC4

PORTC3

PORTC2

PORTC1

PORTC0

$14 ($34)

DDRC

DDC7

DDC6

DDC5

DDC4

DDC3

DDC2

DDC1

DDC0

$13 ($33)

PINC

PINC7

PINC6

PINC5

PINC4

PINC3

PINC2

PINC1

PINC0

$12 ($32)

PORTD

PORTD7

PORTD6

PORTD5

PORTD4

PORTD3

PORTD2

PORTD1

PORTD0

$11 ($31)

DDRD

DDD7

DDD6

DDD5

DDD4

DDD3

DDD2

DDD1

DDD0

$10 ($30)

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

–

SPI2X

169

MSTR

CPOL

CPHA

SPR1

SPR0

$0F ($2F)

SPDR

$0E ($2E)

SPSR

SPIF

WCOL

–

$0D ($2D)

SPCR

SPIE

SPE

DORD

$0C ($2C)

UDR0

$0B ($2B)

UCSR0A

RXC0

TXC0

UDRE0

FE0

DOR0

UPE0

U2X0

MPCM0

189

$0A ($2A)

UCSR0B

RXCIE0

TXCIE0

UDRIE0

RXEN0

TXEN0

UCSZ02

RXB80

TXB80

190

$09 ($29)

UBRR0L

$08 ($28)

ACSR

ACD

ACBG

ACO

ACI

ACIE

ACIC

ACIS1

ACIS0

227

$07 ($27)

ADMUX

REFS1

REFS0

ADLAR

MUX4

MUX3

MUX2

MUX1

MUX0

242

$06 ($26)

ADCSRA

ADEN

ADSC

ADFR

ADIF

ADIE

ADPS2

ADPS1

ADPS0

244

$05 ($25)

ADCH

ADC Data Register High Byte

245

$04 ($24)

ADCL

ADC Data Register Low byte

245

$03 ($23)

PORTE

PORTE7

PORTE6

PORTE5

PORTE4

PORTE3

PORTE2

PORTE1

PORTE0

$02 ($22)

DDRE

DDE7

DDE6

DDE5

DDE4

DDE3

DDE2

DDE1

DDE0

362

SPI Data Register

169

USART0 I/O Data Register

167
189

USART0 Baud Rate Register Low

192

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Register Summary (Continued)
Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

$01 ($21)

PINE

PINE7

PINE6

PINE5

PINE4

PINE3

PINE2

PINE1

PINE0

$00 ($20)

PINF

PINF7

PINF6

PINF5

PINF4

PINF3

PINF2

PINF1

PINF0

Notes:

Page

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.

363
2467P–AVR–08/07

Instruction Set Summary
Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS
ADD

Rd, Rr

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

ADC

Rd, Rr

Add with Carry two Registers

Rd ← Rd + Rr + C

Z,C,N,V,H

ADIW

Rdl,K

Add Immediate to Word

Rdh:Rdl ← Rdh:Rdl + K

Z,C,N,V,S

SUB

Rd, Rr

Subtract two Registers

Rd ← Rd - Rr

Z,C,N,V,H

SUBI

Rd, K

Subtract Constant from Register

Rd ← Rd - K

Z,C,N,V,H

SBC

Rd, Rr

Subtract with Carry two Registers

Rd ← Rd - Rr - C

Z,C,N,V,H

SBCI

Rd, K

Subtract with Carry Constant from Reg.

Rd ← Rd - K - C

Z,C,N,V,H

SBIW

Rdl,K

Subtract Immediate from Word

Rdh:Rdl ← Rdh:Rdl - K

Z,C,N,V,S

AND

Rd, Rr

Logical AND Registers

Rd ← Rd • Rr

Z,N,V

ANDI

Rd, K

Logical AND Register and Constant

Rd ← Rd • K

Z,N,V

Rd, Rr

Logical OR Registers

Rd ← Rd v Rr

Z,N,V

ORI

Rd, K

Logical OR Register and Constant

Rd ← Rd v K

Z,N,V

EOR

Rd, Rr

Exclusive OR Registers

Rd ← Rd ⊕ Rr

Z,N,V

COM

One’s Complement

Rd ← $FF − Rd

Z,C,N,V

NEG

Two’s Complement

Rd ← $00 − Rd

Z,C,N,V,H

SBR

Rd,K

Set Bit(s) in Register

Rd ← Rd v K

Z,N,V

CBR

Rd,K

Clear Bit(s) in Register

Rd ← Rd • ($FF - K)

Z,N,V

INC

Increment

Rd ← Rd + 1

Z,N,V

DEC

Decrement

Rd ← Rd − 1

Z,N,V

TST

Test for Zero or Minus

Rd ← Rd • Rd

Z,N,V

CLR

Clear Register

Rd ← Rd ⊕ Rd

Z,N,V

SER

Set Register

Rd ← $FF

None

MUL

Rd, Rr

Multiply Unsigned

R1:R0 ← Rd x Rr

Z,C

MULS

Rd, Rr

Multiply Signed

R1:R0 ← Rd x Rr

Z,C

MULSU

Rd, Rr

Multiply Signed with Unsigned

R1:R0 ← Rd x Rr

Z,C

FMUL

Rd, Rr

Fractional Multiply Unsigned

R1:R0 ← (Rd x Rr) <<

1
R1:R0 ← (Rd x Rr) << 1
R1:R0 ← (Rd x Rr) << 1

Z,C

2
2

FMULS

Rd, Rr

Fractional Multiply Signed

FMULSU

Rd, Rr

Fractional Multiply Signed with Unsigned

BRANCH INSTRUCTIONS
RJMP

IJMP

Relative Jump

PC ← PC + k + 1

None

Indirect Jump to (Z)

PC ← Z

None

JMP

Direct Jump

PC ← k

None

RCALL

Relative Subroutine Call

PC ← PC + k + 1

None

Indirect Call to (Z)

PC ← Z

None

Direct Subroutine Call

PC ← k

None

RET

Subroutine Return

PC ← STACK

None

RETI

Interrupt Return

PC ← STACK

ICALL
CALL

CPSE

Rd,Rr

Compare, Skip if Equal

if (Rd = Rr) PC ← PC + 2 or 3

None

Rd,Rr

Compare

Rd − Rr

Z, N,V,C,H

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

Z, N,V,C,H

CPI

Rd,K

Compare Register with Immediate

Rd − K

Z, N,V,C,H

SBRC

Rr, b

Skip if Bit in Register Cleared

if (Rr(b)=0) PC ← PC + 2 or 3

None

1/2/3

1
1/2/3

SBRS

Rr, b

Skip if Bit in Register is Set

if (Rr(b)=1) PC ← PC + 2 or 3

None

1/2/3

SBIC

P, b

Skip if Bit in I/O Register Cleared

if (P(b)=0) PC ← PC + 2 or 3

None

1/2/3

SBIS

P, b

Skip if Bit in I/O Register is Set

if (P(b)=1) PC ← PC + 2 or 3

None

1/2/3

BRBS

s, k

Branch if Status Flag Set

if (SREG(s) = 1) then PC←PC+k + 1

None

1/2

BRBC

s, k

Branch if Status Flag Cleared

if (SREG(s) = 0) then PC←PC+k + 1

None

1/2

BREQ

Branch if Equal

if (Z = 1) then PC ← PC + k + 1

None

1/2

BRNE

Branch if Not Equal

if (Z = 0) then PC ← PC + k + 1

None

1/2

BRCS

Branch if Carry Set

if (C = 1) then PC ← PC + k + 1

None

1/2

BRCC

Branch if Carry Cleared

if (C = 0) then PC ← PC + k + 1

None

1/2

BRSH

Branch if Same or Higher

if (C = 0) then PC ← PC + k + 1

None

1/2

BRLO

Branch if Lower

if (C = 1) then PC ← PC + k + 1

None

1/2

BRMI

Branch if Minus

if (N = 1) then PC ← PC + k + 1

None

1/2

BRPL

Branch if Plus

if (N = 0) then PC ← PC + k + 1

None

1/2

BRGE

Branch if Greater or Equal, Signed

if (N ⊕ V= 0) then PC ← PC + k + 1

None

1/2

BRLT

Branch if Less Than Zero, Signed

if (N ⊕ V= 1) then PC ← PC + k + 1

None

1/2

BRHS

Branch if Half Carry Flag Set

if (H = 1) then PC ← PC + k + 1

None

1/2

BRHC

Branch if Half Carry Flag Cleared

if (H = 0) then PC ← PC + k + 1

None

1/2

BRTS

Branch if T Flag Set

if (T = 1) then PC ← PC + k + 1

None

1/2

BRTC

Branch if T Flag Cleared

if (T = 0) then PC ← PC + k + 1

None

1/2

BRVS

Branch if Overflow Flag is Set

if (V = 1) then PC ← PC + k + 1

None

1/2

BRVC

Branch if Overflow Flag is Cleared

if (V = 0) then PC ← PC + k + 1

None

1/2

364

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Instruction Set Summary (Continued)
Mnemonics

Operands

Description

Operation

Flags

BRIE

Branch if Interrupt Enabled

if ( I = 1) then PC ← PC + k + 1

None

#Clocks
1/2

BRID

Branch if Interrupt Disabled

if ( I = 0) then PC ← PC + k + 1

None

1/2

Rd ← Rr
Rd+1:Rd ← Rr+1:Rr

None

1
1

DATA TRANSFER INSTRUCTIONS
MOV

Rd, Rr

Move Between Registers

MOVW

Rd, Rr

Copy Register Word

LDI

Rd, K

Load Immediate

Rd ← K

None

Rd, X

Load Indirect

Rd ← (X)

None

Rd, X+

Load Indirect and Post-Inc.

Rd ← (X), X ← X + 1

None

Rd, - X

Load Indirect and Pre-Dec.

X ← X - 1, Rd ← (X)

None

Rd, Y

Load Indirect

Rd ← (Y)

None

Rd, Y+

Load Indirect and Post-Inc.

Rd ← (Y), Y ← Y + 1

None

Rd, - Y

Load Indirect and Pre-Dec.

Y ← Y - 1, Rd ← (Y)

None

LDD

Rd,Y+q

Load Indirect with Displacement

Rd ← (Y + q)

None

Rd, Z

Load Indirect

Rd ← (Z)

None

Rd, Z+

Load Indirect and Post-Inc.

Rd ← (Z), Z ← Z+1

None

Rd, -Z

Load Indirect and Pre-Dec.

Z ← Z - 1, Rd ← (Z)

None

LDD

Rd, Z+q

Load Indirect with Displacement

Rd ← (Z + q)

None

LDS

Rd, k

Load Direct from SRAM

Rd ← (k)

None

X, Rr

Store Indirect

(X) ← Rr

None

X+, Rr

Store Indirect and Post-Inc.

(X) ← Rr, X ← X + 1

None

- X, Rr

Store Indirect and Pre-Dec.

X ← X - 1, (X) ← Rr

None

Y, Rr

Store Indirect

(Y) ← Rr

None

Y+, Rr

Store Indirect and Post-Inc.

(Y) ← Rr, Y ← Y + 1

None

- Y, Rr

Store Indirect and Pre-Dec.

Y ← Y - 1, (Y) ← Rr

None

STD

Y+q,Rr

Store Indirect with Displacement

(Y + q) ← Rr

None

Z, Rr

Store Indirect

(Z) ← Rr

None

Z+, Rr

Store Indirect and Post-Inc.

(Z) ← Rr, Z ← Z + 1

None

-Z, Rr

Store Indirect and Pre-Dec.

Z ← Z - 1, (Z) ← Rr

None

STD

Z+q,Rr

Store Indirect with Displacement

(Z + q) ← Rr

None

STS

k, Rr

Store Direct to SRAM

(k) ← Rr

None

Load Program Memory

R0 ← (Z)

None

LPM
LPM

Rd, Z

Load Program Memory

Rd ← (Z)

None

LPM

Rd, Z+

Load Program Memory and Post-Inc

Rd ← (Z), Z ← Z+1

None

3
3

Extended Load Program Memory

R0 ← (RAMPZ:Z)

None

ELPM

Rd, Z

Extended Load Program Memory

Rd ← (RAMPZ:Z)

None

ELPM

Rd, Z+

Extended Load Program Memory and Post-Inc

Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1

None

Store Program Memory

(Z) ← R1:R0

None

Rd, P

In Port

Rd ← P

None

OUT

P, Rr

Out Port

P ← Rr

None

PUSH

Push Register on Stack

STACK ← Rr

None

POP

Pop Register from Stack

Rd ← STACK

None

ELPM

SPM

BIT AND BIT-TEST INSTRUCTIONS
SBI

P,b

Set Bit in I/O Register

I/O(P,b) ← 1

None

CBI

P,b

Clear Bit in I/O Register

I/O(P,b) ← 0

None

LSL

Logical Shift Left

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

Logical Shift Right

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

ROL

Rotate Left Through Carry

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

ROR

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

ASR

Arithmetic Shift Right

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

SWAP

Swap Nibbles

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

BSET

Flag Set

SREG(s) ← 1

SREG(s)

BCLR

Flag Clear

SREG(s) ← 0

SREG(s)

BST

Rr, b

Bit Store from Register to T

T ← Rr(b)

BLD

Rd, b

Bit load from T to Register

Rd(b) ← T

None

SEC

Set Carry

C←1

CLC

Clear Carry

C←0

SEN

Set Negative Flag

N←1

CLN

Clear Negative Flag

N←0

SEZ

Set Zero Flag

Z←1

CLZ

Clear Zero Flag

Z←0

SEI

Global Interrupt Enable

I←1

CLI

Global Interrupt Disable

I←0

SES

Set Signed Test Flag

S←1

CLS

Clear Signed Test Flag

S←0

365
2467P–AVR–08/07

Instruction Set Summary (Continued)
Mnemonics

Description

Operation

Flags

SEV

Operands

Set Twos Complement Overflow.

V←1

#Clocks
1

CLV

Clear Twos Complement Overflow

V←0

SET

Set T in SREG

T←1

CLT

Clear T in SREG

T←0

SEH
CLH

Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG

H←1
H←0

H
H

1
1

MCU CONTROL INSTRUCTIONS
NOP

No Operation

None

SLEEP

Sleep

(see specific descr. for Sleep function)

None

WDR
BREAK

Watchdog Reset
Break

(see specific descr. for WDR/timer)
For On-chip Debug Only

None
None

1
N/A

366

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Ordering Information
Speed (MHz)

Notes:

Power Supply

2.7 - 5.5V

4.5 - 5.5V

Ordering Code

Package(1)

ATmega128L-8AC
ATmega128L-8MC

64A
64M1

Commercial
(0oC to 70oC)

ATmega128L-8AI
ATmega128L-8AU(2)
ATmega128L-8MI
ATmega128L-8MU(2)

64A
64A
64M1
64M1

Industrial
(-40oC to 85oC)

ATmega128-16AC
ATmega128-16MC

64A
64M1

Commercial
(0oC to 70oC)

ATmega128-16AI
ATmega128-16AU(2)
ATmega128-16MI
ATmega128-16MU(2)

64A
64A
64M1
64M1

Industrial
(-40oC to 85oC)

Operation Range

1. The device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

Package Type
64A

64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1

64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

367
2467P–AVR–08/07

Packaging Information
64A

PIN 1
B
PIN 1 IDENTIFIER

D1
D
C

0°~7°
A1

L
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL

Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.

MIN

NOM

MAX

–

1.20

0.05

–

0.15

0.95

1.00

1.05

15.75

16.00

16.25

13.90

14.00

14.10

15.75

16.00

16.25

13.90

14.00

14.10

0.30

–

0.45

0.09

–

0.20

0.45

–

0.75

NOTE

Note 2

0.80 TYP

10/5/2001

368

2325 Orchard Parkway
San Jose, CA 95131

TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

DRAWING NO.

REV.

64A

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
64M1

Marked Pin# 1 ID

SEATING PLANE

TOP VIEW

A
K

0.08 C

Pin #1 Corner

1
2
3

Option A

SIDE VIEW

Pin #1
Triangle

COMMON DIMENSIONS
(Unit of Measure = mm)

E2
Option B

Option C

Pin #1
Chamfer
(C 0.30)

Pin #1
Notch
(0.20 R)

BOTTOM VIEW

Note: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.

SYMBOL

MIN

NOM

MAX

0.80

0.90

1.00
0.05

–

0.02

0.18

0.25

0.30

8.90

9.00

9.10

5.20

5.40

5.60

8.90

9.00

9.10

5.20

5.40

5.60

NOTE

0.50 BSC

0.35

0.40

0.45

1.25

1.40

1.55

5/25/06

2325 Orchard Parkway
San Jose, CA 95131

TITLE
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.
64M1

REV.
G

369
2467P–AVR–08/07

Errata

The revision letter in this section refers to the revision of the ATmega128 device.

ATmega128 Rev. M •
•
•
•
•
•

First Analog Comparator conversion may be delayed
Interrupts may be lost when writing the timer registers in the asynchronous timer
Stabilizing time needed when changing XDIV Register
Stabilizing time needed when changing OSCCAL Register
IDCODE masks data from TDI input
Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request

1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2
3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT

370

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; set global interrupt enable

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
4. Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
–

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction
or by entering the Test-Logic-Reset state of the TAP controller to read out the
contents of its Device ID Register and possibly data from succeeding devices of the
scan chain. Issue the BYPASS instruction to the ATmega128 while reading the
Device ID Registers of preceding devices of the boundary scan chain.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. L

•
•
•
•
•
•

371
2467P–AVR–08/07

3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; set global interrupt enable

4. Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround

372

–

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.

ATmega128 Rev. I

•
•
•
•
•
•

373
2467P–AVR–08/07

Assembly Code Example:
CLI
OUT

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; clear global interrupt enable

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

ATmega128 Rev. H •
•
•
•
•
•

374

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising VCC, the first Analog Comparator conversion will
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2
3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; clear global interrupt enable

375
2467P–AVR–08/07

5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
–

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

ATmega128 Rev. G •
•
•
•
•
•

376

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI
OUT

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; set global interrupt enable

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

377
2467P–AVR–08/07

ATmega128 Rev. F

•
•
•
•
•
•

378

; clear global interrupt enable
XDIV, temp

; set new prescale value

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

NOP

; no operation

SEI

; set global interrupt enable

ATmega128(L)
2467P–AVR–08/07

If ATmega128 is the only device in the scan chain, the problem is not visible.

–

If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega128 must be the fist device in the chain.

379
2467P–AVR–08/07

Datasheet
Revision
History

Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.

Changes from Rev. 1. Updated “Features” on page 1.
2467O-10/06 to
2. Added “Data Retention” on page 8.
Rev.
2467P-08/07
3. Updated Table 60 on page 134 and Table 95 on page 235.
4. Updated “C Code Example(1)” on page 177.
5. Updated Figure 114 on page 238.
6. Updated “XTAL Divide Control Register – XDIV” on page 37.
7. Updated “Errata” on page 370.
8. Updated Table 34 on page 77.
9. Updated “Slave Mode” on page 167.

Changes from Rev. 1. Added note to “Timer/Counter Oscillator” on page 44.
2467N-03/06 to
2. Updated “Fast PWM Mode” on page 125.
Rev.
2467O-10/06
3. Updated Table 52 on page 105, Table 54 on page 105, Table 59 on page 134, Table 61
on page 135, Table 64 on page 157, and Table 66 on page 158.
4. Updated “Errata” on page 370.

Changes from Rev. 1. Updated note for Figure 1 on page 2.
2467M-11/04 to
2. Updated “Alternate Functions of Port D” on page 78.
Rev.
2467N-03/06
3. Updated “Alternate Functions of Port G” on page 85.
4. Updated “Phase Correct PWM Mode” on page 101.
5. Updated Table 59 on page 134, Table 60 on page 134.
6. Updated “Bit 2 – TOV3: Timer/Counter3, Overflow Flag” on page 142.
7. Updated “Serial Peripheral Interface – SPI” on page 163.
8. Updated Features in “Analog to Digital Converter” on page 230
9. Added note in “Input Channel and Gain Selections” on page 243.
10. Updated “Errata” on page 370.

380

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Changes from Rev. 1. Removed “analog ground”, replaced by “ground”.
2467L-05/04 to
2. Updated Table 11 on page 41, Table 114 on page 285, Table 128 on page 303, and
Rev.
Table 132 on page 320. Updated Figure 114 on page 238.
2467M-11/04
3. Added note to “Port C (PC7..PC0)” on page 5.
4. Updated “Ordering Information” on page 367.

Changes from Rev. 1. Removed “Preliminary” and “TBD” from the datasheet, replaced occurrences of ICx
with ICPx.
2467K-03/04 to
Rev.
2. Updated Table 8 on page 39, Table 19 on page 51, Table 22 on page 57, Table 96 on
2467L-05/04
page 242, Table 126 on page 299, Table 128 on page 303, Table 132 on page 320, and
Table 134 on page 322.
3. Updated “External Memory Interface” on page 26.
4. Updated “Device Identification Register” on page 253.
5. Updated “Electrical Characteristics” on page 318.
6. Updated “ADC Characteristics” on page 324.
7. Updated “ATmega128 Typical Characteristics” on page 332.
8. Updated “Ordering Information” on page 367.

Changes from Rev. 1. Updated “Errata” on page 370.
2467J-12/03 to
Rev.
2467K-03/04
Changes from Rev. 1. Updated “Calibrated Internal RC Oscillator” on page 42.
2467I-09/03 to Rev.
2467J-12/03
Changes from Rev. 1. Updated note in “XTAL Divide Control Register – XDIV” on page 37.
2467H-02/03 to
2. Updated “JTAG Interface and On-chip Debug System” on page 49.
Rev. 2467I-09/03
3. Updated values for VBOT (BODLEVEL = 1) in Table 19 on page 51.
4. Updated “Test Access Port – TAP” on page 246 regarding JTAGEN.
5. Updated description for the JTD bit on page 255.
6. Added a note regarding JTAGEN fuse to Table 118 on page 288.
7. Updated RPU values in “DC Characteristics” on page 318.

381
2467P–AVR–08/07

8. Added a proposal for solving problems regarding the JTAG instruction IDCODE in
“Errata” on page 370.

Changes from Rev. 1. Corrected the names of the two Prescaler bits in the SFIOR Register.
2467G-09/02 to
2. Added Chip Erase as a first step under “Programming the Flash” on page 315 and
Rev. 2467H-02/03
“Programming the EEPROM” on page 316.

3. Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz
Crystal Oscillator” application note, which do not exist.
4. Corrected OCn waveforms in Figure 52 on page 126.
5. Various minor Timer1 corrections.
6. Added information about PWM symmetry for Timer0 and Timer2.
7. Various minor TWI corrections.
8. Added reference to Table 124 on page 292 from both SPI Serial Programming and Self
Programming to inform about the Flash Page size.
9. Added note under “Filling the Temporary Buffer (Page Loading)” on page 280 about
writing to the EEPROM during an SPM Page load.
10. Removed ADHSM completely.
11. Added section “EEPROM Write During Power-down Sleep Mode” on page 25.
12. Updated drawings in “Packaging Information” on page 368.

Changes from Rev. 1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
2467F-09/02 to
Rev. 2467G-09/02
Changes from Rev. 1. Added 64-pad QFN/MLF Package and updated “Ordering Information” on page 367.
2467E-04/02 to
2. Added the section “Using all Locations of External Memory Smaller than 64 KB” on
Rev. 2467F-09/02
page 33.

3. Added the section “Default Clock Source” on page 38.
4. Renamed SPMCR to SPMCSR in entire document.
5. When using external clock there are some limitations regards to change of frequency.
This is descried in “External Clock” on page 43 and Table 131, “External Clock
Drive,” on page 320.
6. Added a sub section regarding OCD-system and power consumption in the section
“Minimizing Power Consumption” on page 48.

382

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
7. Corrected typo (WGM-bit setting) for:
“Fast PWM Mode” on page 99 (Timer/Counter0).
“Phase Correct PWM Mode” on page 101 (Timer/Counter0).
“Fast PWM Mode” on page 151 (Timer/Counter2).
“Phase Correct PWM Mode” on page 153 (Timer/Counter2).
8. Corrected Table 81 on page 192 (USART).
9. Corrected Table 102 on page 259 (Boundary-Scan)
10. Updated Vil parameter in “DC Characteristics” on page 318.

Changes from Rev. 1. Updated the Characterization Data in Section “ATmega128 Typical Characteristics”
on page 332.
2467D-03/02 to
Rev. 2467E-04/02
2. Updated the following tables:

Table 19 on page 51, Table 20 on page 55, Table 68 on page 158, Table 102 on page 259,
and Table 136 on page 328.
3. Updated Description of OSCCAL Calibration Byte.
In the data sheet, it was not explained how to take advantage of the calibration bytes for 2,
4, and 8 MHz Oscillator selections. This is now added in the following sections:
Improved description of “Oscillator Calibration Register – OSCCAL” on page 42 and “Calibration Byte” on page 289.

Changes from Rev. 1. Added more information about “ATmega103 Compatibility Mode” on page 5.
2467C-02/02 to
2. Updated Table 2, “EEPROM Programming Time,” on page 23.
Rev. 2467D-03/02
3. Updated typical Start-up Time in Table 7 on page 38, Table 9 and Table 10 on page 40,
Table 12 on page 41, Table 14 on page 42, and Table 16 on page 43.
4. Updated Table 22 on page 57 with typical WDT Time-out.
5. Corrected description of ADSC bit in “ADC Control and Status Register A – ADCSRA”
on page 244.
6. Improved description on how to do a polarity check of the ADC differential results in
“ADC Conversion Result” on page 241.
7. Corrected JTAG version numbers in “JTAG Version Numbers” on page 256.
8. Improved description of addressing during SPM (usage of RAMPZ) on “Addressing
the Flash During Self-Programming” on page 278, “Performing Page Erase by SPM”
on page 280, and “Performing a Page Write” on page 280.
9. Added not regarding OCDEN Fuse below Table 118 on page 288.

383
2467P–AVR–08/07

10. Updated Programming Figures:
Figure 135 on page 290 and Figure 144 on page 301 are updated to also reflect that AVCC
must be connected during Programming mode. Figure 139 on page 297 added to illustrate
how to program the fuses.
11. Added a note regarding usage of the PROG_PAGELOAD and PROG_PAGEREAD
instructions on page 307.
12. Added Calibrated RC Oscillator characterization curves in section “ATmega128 Typical Characteristics” on page 332.
13. Updated “Two-wire Serial Interface” section.
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit
Rate Generator Unit” on page 204. Added the description at the end of “Address Match Unit”
on page 205.
14. Added a note regarding usage of Timer/Counter0 combined with the clock. See
“XTAL Divide Control Register – XDIV” on page 37.

Changes from Rev. 1. Corrected Description of Alternate Functions of Port G
2467B-09/01 to
Corrected description of TOSC1 and TOSC2 in “Alternate Functions of Port G” on page 85.
Rev. 2467C-02/02
2. Added JTAG Version Numbers for rev. F and rev. G
Updated Table 100 on page 256.
3

Added Some Preliminary Test Limits and Characterization Data
Removed some of the TBD's in the following tables and pages:
Table 19 on page 51, Table 20 on page 55, “DC Characteristics” on page 318, Table 131 on
page 320, Table 134 on page 322, and Table 136 on page 328.

4. Corrected “Ordering Information” on page 367.
5. Added some Characterization Data in Section “ATmega128 Typical Characteristics”
on page 332.
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
See “Leaving Programming Mode” on page 315.
7. Added Description on How to Access the Extended Fuse Byte Through JTAG Programming Mode.
See “Programming the Fuses” on page 317 and “Reading the Fuses and Lock Bits” on page
317.

384

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Table of
Contents

Features 1
Pin Configurations 2
Overview 2
Block Diagram 3
ATmega103 and ATmega128 Compatibility 4
Pin Descriptions 5

Resources 8
Data Retention 8
About Code Examples 9
AVR CPU Core 10
Introduction 10
Architectural Overview 10
ALU – Arithmetic Logic Unit 11
Status Register 11
General Purpose Register File 12
Stack Pointer 14
Instruction Execution Timing 14
Reset and Interrupt Handling 15

AVR ATmega128 Memories 18
In-System Reprogrammable Flash Program Memory 18
SRAM Data Memory 19
EEPROM Data Memory 21
I/O Memory 26
External Memory Interface 26

System Clock and Clock Options 36
Clock Systems and their Distribution 36
Clock Sources 37
Default Clock Source 38
Crystal Oscillator 39
Low-frequency Crystal Oscillator 40
External RC Oscillator 40
Calibrated Internal RC Oscillator 42
External Clock 43
Timer/Counter Oscillator 44

i
2467P–AVR–08/07

Power Management and Sleep Modes 45
Idle Mode 46
ADC Noise Reduction Mode 46
Power-down Mode 46
Power-save Mode 46
Standby Mode 47
Extended Standby Mode 47
Minimizing Power Consumption 48

System Control and Reset 50
Internal Voltage Reference 54
Watchdog Timer 55
Timed Sequences for Changing the Configuration of the Watchdog Timer 58

Interrupts 60
Interrupt Vectors in ATmega128 60

I/O Ports 66
Introduction 66
Ports as General Digital I/O 67
Alternate Port Functions 71
Register Description for I/O Ports 87

External Interrupts 90
8-bit Timer/Counter0 with PWM and Asynchronous Operation 93
Overview 93
Timer/Counter Clock Sources 94
Counter Unit 94
Output Compare Unit 95
Compare Match Output Unit 97
Modes of Operation 98
Timer/Counter Timing Diagrams 102
8-bit Timer/Counter Register Description 104
Asynchronous Operation of the Timer/Counter 107
Timer/Counter Prescaler 110

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) 112
Overview 112
Accessing 16-bit Registers 115
Timer/Counter Clock Sources 118
Counter Unit 118
Input Capture Unit 119
Output Compare Units 121
Compare Match Output Unit 123
Modes of Operation 124
Timer/Counter Timing Diagrams 131
16-bit Timer/Counter Register Description 133

Timer/Counter3, Timer/Counter2, and Timer/Counter1 Prescalers
143
8-bit Timer/Counter2 with PWM 145
Overview 145
Timer/Counter Clock Sources 146
Counter Unit 146
Output Compare Unit 147
Compare Match Output Unit 148
Modes of Operation 149
Timer/Counter Timing Diagrams 155
8-bit Timer/Counter Register Description 157

Output Compare Modulator (OCM1C2) 161
Overview 161
Description 161

Serial Peripheral Interface – SPI 163
SS Pin Functionality 167
Data Modes 170

USART 171
Overview 171
Clock Generation 173
Frame Formats 176
USART Initialization 177
Data Transmission – The USART Transmitter 178
Data Reception – The USART Receiver 180
Multi-processor Communication Mode 187
USART Register Description 189
Examples of Baud Rate Setting 194

iii
2467P–AVR–08/07

Two-wire Serial Interface 198
Features 198
Two-wire Serial Interface Bus Definition 198
Data Transfer and Frame Format 199
Multi-master Bus Systems, Arbitration and Synchronization 201
Overview of the TWI Module 204
TWI Register Description 206
Using the TWI 208
Transmission Modes 213
Multi-master Systems and Arbitration 225

Analog Comparator 227
Analog Comparator Multiplexed Input 228

Analog to Digital Converter 230
Features 230
Operation 232
Starting a Conversion 232
Prescaling and Conversion Timing 233
Changing Channel or Reference Selection 235
ADC Noise Canceler 236
ADC Conversion Result 241

JTAG Interface and On-chip Debug System 246
Features 246
Overview 246
Test Access Port – TAP 246
TAP Controller 248
Using the Boundary-scan Chain 249
Using the On-chip Debug System 249
On-chip Debug Specific JTAG Instructions 250
On-chip Debug Related Register in I/O Memory 251
Using the JTAG Programming Capabilities 251
Bibliography 251
IEEE 1149.1 (JTAG) Boundary-scan 252
Features 252
System Overview 252
Data Registers 252
Boundary-scan Specific JTAG Instructions 254
Boundary-scan Related Register in I/O Memory 255
Boundary-scan Chain 255
ATmega128 Boundary-scan Order 266
Boundary-scan Description Language Files 272

ATmega128(L)
2467P–AVR–08/07

ATmega128(L)
Boot Loader Support – Read-While-Write Self-Programming 273
Boot Loader Features 273
Application and Boot Loader Flash Sections 273
Read-While-Write and No Read-While-Write Flash Sections 273
Boot Loader Lock Bits 275
Entering the Boot Loader Program 276
Addressing the Flash During Self-Programming 278
Self-Programming the Flash 279

Memory Programming 286
Program and Data Memory Lock Bits 286
Fuse Bits 287
Signature Bytes 289
Calibration Byte 289
Parallel Programming Parameters, Pin Mapping, and Commands 290
Parallel Programming 292
Serial Downloading 300
SPI Serial Programming Pin Mapping 300
Programming Via the JTAG Interface 305

Electrical Characteristics 318
Absolute Maximum Ratings* 318
DC Characteristics 318
External Clock Drive Waveforms 319
External Clock Drive 320
Two-wire Serial Interface Characteristics 321
SPI Timing Characteristics 322
ADC Characteristics 324
External Data Memory Timing 327

ATmega128 Typical Characteristics 332
Register Summary 361
Instruction Set Summary 364
Ordering Information 367
Packaging Information 368
64A 368
64M1 369

v
2467P–AVR–08/07

Errata 370
ATmega128 Rev. M 370
ATmega128 Rev. L 371
ATmega128 Rev. I 373
ATmega128 Rev. H 374
ATmega128 Rev. G 376
ATmega128 Rev. F 378

Datasheet Revision History 380
Changes from Rev. 2467O-10/06 to Rev.2467P-08/07 380
Changes from Rev. 2467N-03/06 to Rev.2467O-10/06 380
Changes from Rev. 2467M-11/04 to Rev.2467N-03/06 380
Changes from Rev. 2467L-05/04 to Rev.2467M-11/04 381
Changes from Rev. 2467K-03/04 to Rev.2467L-05/04 381
Changes from Rev. 2467J-12/03 to Rev.2467K-03/04 381
Changes from Rev. 2467I-09/03 to Rev.2467J-12/03 381
Changes from Rev. 2467H-02/03 to Rev. 2467I-09/03 381
Changes from Rev. 2467G-09/02 to Rev. 2467H-02/03 382
Changes from Rev. 2467F-09/02 to Rev. 2467G-09/02 382
Changes from Rev. 2467E-04/02 to Rev. 2467F-09/02 382
Changes from Rev. 2467D-03/02 to Rev. 2467E-04/02 383
Changes from Rev. 2467C-02/02 to Rev. 2467D-03/02 383
Changes from Rev. 2467B-09/01 to Rev. 2467C-02/02 384

Table of Contents i

ATmega128(L)
2467P–AVR–08/07

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