XMEGA AU Manual Atmel 8331 8 And 16 Bit AVR Microcontroller

Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual

XMEGA-AU_Manual

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1. About the Manual
- 1.1 Reading the Manual
- 1.2 Resources
- 1.3 Recommended Reading
2. Overview
- 2.1 Block Diagram
3. AVR CPU
- 3.1 Features
- 3.2 Overview
- 3.3 Architectural Overview
- 3.4 ALU - Arithmetic Logic Unit
  - 3.4.1 Hardware Multiplier
- 3.5 Program Flow
- 3.6 Instruction Execution Timing
- 3.7 Status Register
- 3.8 Stack and Stack Pointer
- 3.9 Register File
  - 3.9.1 The X-, Y-, and Z- Registers
- 3.10 RAMP and Extended Indirect Registers
- 3.11 Accessing 16-bit Registers
  - 3.11.1 Accessing 24- and 32-bit Registers
- 3.12 Configuration Change Protection
  - 3.12.1 Sequence for write operation to protected I/O registers
  - 3.12.2 Sequence for execution of protected SPM/LPM
- 3.13 Fuse Lock
- 3.14 Register Descriptions
- 3.15 Register Summary
4. Memories
- 4.1 Features
- 4.2 Overview
- 4.3 Flash Program Memory
  - 4.3.1 Application Section
  - 4.3.2 Application Table Section
  - 4.3.3 Boot Loader Section
  - 4.3.4 Production Signature Row
  - 4.3.5 User Signature Row
- 4.4 Fuses and Lockbits
- 4.5 Data Memory
- 4.6 Internal SRAM
- 4.7 EEPROM
- 4.8 I/O Memory
  - 4.8.1 General Purpose I/O Registers
- 4.9 External Memory
- 4.10 Data Memory and Bus Arbitration
  - 4.10.1 Bus Priority
- 4.11 Memory Timing
- 4.12 Device ID and Revision
- 4.13 JTAG Disable
- 4.14 I/O Memory Protection
- 4.15 Register Description – NVM Controller
  - 4.15.1 ADDR0 – Address register 0
  - 4.15.2 ADDR1 – Address register 1
  - 4.15.3 ADDR2 – Address register 2
  - 4.15.4 DATA0 – Data register 0
  - 4.15.5 DATA1 – Data register 1
  - 4.15.6 DATA2 – Data register 2
  - 4.15.7 CMD – Command Register
  - 4.15.8 CTRLA – Control register A
  - 4.15.9 CTRLB – Control register B
  - 4.15.10 INTCTRL – Interrupt Control register
  - 4.15.11 STATUS – Status register
  - 4.15.12 LOCKBITS – Lock Bit register
- 4.16 Register Descriptions – Fuses and Lock bits
  - 4.16.1 FUSEBYTE0 – Fuse Byte 0
  - 4.16.2 FUSEBYTE1 – Fuse Byte1
  - 4.16.3 FUSEBYTE2 – Fuse Byte2
  - 4.16.4 FUSEBYTE4 – Fuse Byte4
  - 4.16.5 FUSEBYTE5 – Fuse Byte 5
  - 4.16.6 LOCKBITS – Lock Bit register
- 4.17 Register Description – Production Signature Row
  - 4.17.1 RCOSC2M – Internal 2MHz Oscillator Calibration register
  - 4.17.2 RCOSC2MA – Internal 2MHz Oscillator Calibration register
  - 4.17.3 RCOSC32K – Internal 32.768kHz Oscillator Calibration register
  - 4.17.4 RCOSC32M – Internal 32MHz Oscillator Calibration register
  - 4.17.5 RCOSC32MA – Internal 32MHz RC Oscillator Calibration register
  - 4.17.6 LOTNUM0 – Lot Number register 0
  - 4.17.7 LOTNUM1 – Lot Number register 1
  - 4.17.8 LOTNUM2 – Lot Number register 2
  - 4.17.9 LOTNUM3- Lot Number register 3
  - 4.17.10 LOTNUM4 – Lot Number register 4
  - 4.17.11 LOTNUM5 – Lot Number register 5
  - 4.17.12 WAFNUM – Wafer Number register
  - 4.17.13 COORDX0 – Wafer Coordinate X register 0
  - 4.17.14 COORDX1 – Wafer Coordinate X register 1
  - 4.17.15 COORDY0 – Wafer Coordinate Y register 0
  - 4.17.16 COORDY1 – Wafer Coordinate Y register 1
  - 4.17.17 USBCAL0 – USB Calibration register 0
  - 4.17.18 USBCAL1 – USB Pad Calibration register 1
  - 4.17.19 RCOSC48M – USB RCOSC Calibration
  - 4.17.20 ADCACAL0 – ADCA Calibration register 0
  - 4.17.21 ADCACAL1 – ADCA Calibration register 1
  - 4.17.22 ADCBCAL0 – ADCB Calibration register 0
  - 4.17.23 ADCBCAL1 – ADCB Calibration register 1
  - 4.17.24 TEMPSENSE0 – Temperature Sensor Calibration register 0
  - 4.17.25 TEMPSENSE1 – Temperature Sensor Calibration register 1
  - 4.17.26 DACA0OFFCAL – DACA Offset Calibration register
  - 4.17.27 DACA0GAINCAL – DACA Gain Calibration register
  - 4.17.28 DACB0OFFCAL – DACB Offset Calibration register
  - 4.17.29 DACB0GAINCAL – DACB Gain Calibration register
  - 4.17.30 DACA1OFFCAL – DACA Offset Calibration register
  - 4.17.31 DACA1GAINCAL – DACA Gain Calibration register
  - 4.17.32 DACB1OFFCAL – DACB Offset Calibration register
  - 4.17.33 DACB1GAINCAL – DACB Gain Calibration register
- 4.18 Register Description – General Purpose I/O Memory
  - 4.18.1 GPIORn – General Purpose I/O register n
- 4.19 Register Description – External Memory
- 4.20 Register Descriptions – MCU Control
  - 4.20.1 DEVID0 – Device ID register 0
  - 4.20.2 DEVID1 – Device ID register 1
  - 4.20.3 DEVID2 – Device ID register 2
  - 4.20.4 REVID – Revision ID
  - 4.20.5 JTAGUID – JTAG User ID register
  - 4.20.6 MCUCR – Control register
  - 4.20.7 ANAINIT – Analog Initialization register
  - 4.20.8 EVSYSLOCK – Event System Lock register
  - 4.20.9 AWEXLOCK – Advanced Waveform Extension Lock register
- 4.21 Register summary – NVM controller
- 4.22 Register summary – Fuses and Lock Bits
- 4.23 Register summary – Production Signature Row
- 4.24 Register summary – General Purpose I/O registers
- 4.25 Register summary – MCU control
- 4.26 Interrupt vector summary – NVM Controller
5. DMAC - Direct Memory Access Controller
- 5.1 Features
- 5.2 Overview
- 5.3 DMA Transaction
  - 5.3.1 Block Transfer and Repeat
  - 5.3.2 Burst Transfer
- 5.4 Transfer Triggers
- 5.5 Addressing
- 5.6 Priority Between Channels
- 5.7 Double Buffering
- 5.8 Transfer Buffers
- 5.9 Error detection
- 5.10 Software Reset
- 5.11 Protection
- 5.12 Interrupts
- 5.13 Register Description – DMA Controller
- 5.14 Register Description – DMA Channel
- 5.15 Register Summary – DMA Controller
- 5.16 Register Summary – DMA Channel
- 5.17 Interrupt vector summary
6. Event System
- 6.1 Features
- 6.2 Overview
- 6.3 Events
- 6.4 Event Routing Network
- 6.5 Event Timing
- 6.6 Filtering
- 6.7 Quadrature Decoder
  - 6.7.1 Quadrature Operation
  - 6.7.2 QDEC Setup
- 6.8 Register Description
- 6.9 Register Summary
7. System Clock and Clock Options
- 7.1 Features
- 7.2 Overview
- 7.3 Clock Distribution
- 7.4 Clock Sources
  - 7.4.1 Internal Oscillators
  - 7.4.2 External Clock Sources
- 7.5 System Clock Selection and Prescalers
- 7.6 PLL with 1x-31x Multiplication Factor
- 7.7 DFLL 2MHz and DFLL 32MHz
- 7.8 PLL and External Clock Source Failure Monitor
- 7.9 Register Description – Clock
- 7.10 Register Description – Oscillator
- 7.11 Register Description – DFLL32M/DFLL2M
- 7.12 Register summary – Clock
- 7.13 Register summary – Oscillator
- 7.14 Register summary – DFLL32M/DFLL2M
- 7.15 Oscillator failure interrupt vector summary
8. Power Management and Sleep Modes
- 8.1 Features
- 8.2 Overview
- 8.3 Sleep Modes
- 8.4 Power Reduction Registers
- 8.5 Minimizing Power Consumption
- 8.6 Register Description – Sleep
  - 8.6.1 CTRL – Control register
- 8.7 Register Description – Power Reduction
- 8.8 Register summary – Sleep
- 8.9 Register summary – Power reduction
9. Reset System
- 9.1 Features
- 9.2 Overview
- 9.3 Reset Sequence
  - 9.3.1 Reset Counter
  - 9.3.2 Oscillator Startup
- 9.4 Reset Sources
- 9.5 Register Description
  - 9.5.1 STATUS – Status register
  - 9.5.2 CTRL – Control register
- 9.6 Register summary
10. Battery Backup System
- 10.1 Features
- 10.2 Overview
- 10.3 Battery Backup System
- 10.4 Configuration
- 10.5 Operation
  - 10.5.1 Main Power Loss
  - 10.5.2 Main Power Restore and Start-up Sequence
- 10.6 Register Description
- 10.7 Register summary
11. WDT – Watchdog Timer
- 11.1 Features
- 11.2 Overview
- 11.3 Normal Mode Operation
- 11.4 Window Mode Operation
- 11.5 Watchdog Timer Clock
- 11.6 Configuration Protection and Lock
- 11.7 Registers Description
- 11.8 Register summary
12. Interrupts and Programmable Multilevel Interrupt Controller
- 12.1 Features
- 12.2 Overview
- 12.3 Operation
- 12.4 Interrupts
  - 12.4.1 NMI – Non-Maskable Interrupts
  - 12.4.2 Interrupt Response Time
- 12.5 Interrupt level
- 12.6 Interrupt priority
  - 12.6.1 Static priority
  - 12.6.2 Round-robin Scheduling
- 12.7 Interrupt vector locations
- 12.8 Register description
- 12.9 Register summary
13. I/O Ports
- 13.1 Features
- 13.2 Overview
- 13.3 I/O Pin Use and Configuration
- 13.4 Reading the Pin Value
- 13.5 Input Sense Configuration
- 13.6 Port Interrupt
- 13.7 Port Event
- 13.8 Alternate Port Functions
- 13.9 Slew Rate Control
- 13.10 Clock and Event Output
- 13.11 Multi-pin configuration
- 13.12 Virtual Ports
- 13.13 Register Descriptions – Ports
- 13.14 Register Descriptions – Port Configuration
- 13.15 Register Descriptions – Virtual Port
- 13.16 Register summary – Ports
- 13.17 Register summary – Port Configuration
- 13.18 Register summary – Virtual Ports
- 13.19 Interrupt vector summary – Ports
14. TC0/1 – 16-bit Timer/Counter Type 0 and 1
- 14.1 Features
- 14.2 Overview
  - 14.2.1 Definitions
- 14.3 Block Diagram
- 14.4 Clock and Event Sources
- 14.5 Double Buffering
- 14.6 Counter Operation
- 14.7 Capture Channel
- 14.8 Compare Channel
- 14.9 Interrupts and events
- 14.10 DMA Support
- 14.11 Timer/Counter Commands
- 14.12 Register Description
- 14.13 Register summary
- 14.14 Interrupt vector summary
15. TC2 – 16-bit Timer/Counter Type 2
- 15.1 Features
- 15.2 Overview
- 15.3 Block Diagram
- 15.4 Clock Sources
- 15.5 Counter Operation
  - 15.5.1 Changing the Period
- 15.6 Compare Channel
- 15.7 Interrupts and Events
- 15.8 DMA Support
- 15.9 Timer/Counter Commands
- 15.10 Register description
- 15.11 Register summary
- 15.12 Interrupt vector summary
16. AWeX – Advanced Waveform Extension
- 16.1 Features
- 16.2 Overview
- 16.3 Port Override
- 16.4 Dead-time Insertion
- 16.5 Pattern Generation
- 16.6 Fault Protection
- 16.7 Register Description
- 16.8 Register summary
17. Hi-Res – High-Resolution Extension
- 17.1 Features
- 17.2 Overview
- 17.3 Register Description
  - 17.3.1 CTRLA – Control register A
- 17.4 Register summary
18. RTC – Real-Time Counter
- 18.1 Features
- 18.2 Overview
  - 18.2.1 Clock Domains
  - 18.2.2 Interrupts and Events
- 18.3 Register Descriptions
- 18.4 Register summary
- 18.5 Interrupt Vector Summary
19. RTC32 – 32-bit Real-Time Counter
- 19.1 Features
- 19.2 Overview
- 19.3 Register Descriptions
- 19.4 Register summary
- 19.5 Interrupt vector summary
20. USB – Universal Serial Bus Interface
- 20.1 Features
- 20.2 Overview
- 20.3 Operation
  - 20.3.1 Start of Frame
  - 20.3.2 SETUP
  - 20.3.3 OUT
  - 20.3.4 IN
- 20.4 SRAM Memory Mapping
- 20.5 Clock Generation
- 20.6 Ping-pong Operation
- 20.7 Multipacket Transfers
  - 20.7.1 For Input Endpoints
  - 20.7.2 For Output Endpoints
- 20.8 Auto Zero Length Packet
- 20.9 Transaction Complete FIFO
- 20.10 Interrupts and Events
  - 20.10.1 Transaction Complete Interrupt
  - 20.10.2 Bus Event Interrupt
  - 20.10.3 Events
- 20.11 VBUS Detection
- 20.12 On-chip Debug
- 20.13 Operating voltage
- 20.14 Register Description – USB
  - 20.14.1 CTRLA – Control register A
  - 20.14.2 CTRLB – Control register B
  - 20.14.3 STATUS – Status register
  - 20.14.4 ADDR – Address register
  - 20.14.5 FIFOWP – FIFO Write Pointer register
  - 20.14.6 FIFORP – FIFO Read Pointer register
  - 20.14.7 EPPTRL – Endpoint Configuration Table Pointer Low
  - 20.14.8 EPPTRH – Endpoint Configuration Table Pointer High
  - 20.14.9 INTCTRLA – Interrupt Control register A
  - 20.14.10 INTCTRLB – Interrupt Control register B
  - 20.14.11 INTFLAGSACLR/ INTFLAGSASET – Clear/ Set Interrupt Flag register A
  - 20.14.12 INTFLAGSBCLR/INTFLAGSBSET – Clear/Set Interrupt Flag register B
  - 20.14.13 CAL0 – Calibration Low
  - 20.14.14 CAL1 – Calibration High
- 20.15 Register Description – USB Endpoint
  - 20.15.1 STATUS – Status register
  - 20.15.2 CTRL – Control
  - 20.15.3 CNTL – Counter Low
  - 20.15.4 CNTH – Counter High
  - 20.15.5 DATAPTRL – Data Pointer register Low
  - 20.15.6 DATAPTRH – Data Pointer register High
  - 20.15.7 AUXDATAL – Auxiliary Data register Low
  - 20.15.8 AUXDATAH – Auxiliary Data register High
- 20.16 Register Description – Frame
  - 20.16.1 FRAMENUML – Frame Number register Low
  - 20.16.2 FRAMENUMH – Frame Number register High
- 20.17 Register summary – USB module
- 20.18 Register summary – USB endpoint
- 20.19 Register summary – Frame
- 20.20 USB Interrupt vector summary
21. TWI – Two-Wire Interface
- 21.1 Features
- 21.2 Overview
- 21.3 General TWI Bus Concepts
- 21.4 TWI Bus State Logic
- 21.5 TWI Master Operation
- 21.6 TWI Slave Operation
- 21.7 Enabling External Driver Interface
- 21.8 Register Description – TWI
  - 21.8.1 CTRL – Common Control register
- 21.9 Register Description – TWI Master
- 21.10 Register Description – TWI Slave
- 21.11 Register summary – TWI
- 21.12 Register summary – TWI master
- 21.13 Register summary – TWI slave
- 21.14 Interrupt vector summary
22. SPI – Serial Peripheral Interface
- 22.1 Features
- 22.2 Overview
- 22.3 Master Mode
- 22.4 Slave Mode
- 22.5 Data Modes
- 22.6 DMA Support
- 22.7 Register Description
- 22.8 Register summary
- 22.9 Interrupt vector summary
23. USART
- 23.1 Features
- 23.2 Overview
- 23.3 Clock Generation
- 23.4 Frame Formats
  - 23.4.1 Parity Bit Calculation
  - 23.4.2 SPI Frame Formats
- 23.5 USART Initialization
- 23.6 Data Transmission - The USART Transmitter
  - 23.6.1 Sending Frames
  - 23.6.2 Disabling the Transmitter
- 23.7 Data Reception - The USART Receiver
- 23.8 Asynchronous Data Reception
- 23.9 Fractional Baud Rate Generation
- 23.10 USART in Master SPI Mode
- 23.11 USART SPI vs. SPI
- 23.12 Multiprocessor Communication Mode
  - 23.12.1 Using Multiprocessor Communication Mode
- 23.13 IRCOM Mode of Operation
- 23.14 DMA Support
- 23.15 Register Description
- 23.16 Register summary
  - 23.16.1 Register description – USART
  - 23.16.2 Register description – USART in SPI Master Mode
- 23.17 Interrupt vector summary
24. IRCOM – IR Communication Module
- 24.1 Features
- 24.2 Overview
- 24.3 Event System Filtering
- 24.4 Registers Description
- 24.5 Register summary
25. AES and DES Crypto Engines
- 25.1 Features
- 25.2 Overview
- 25.3 DES Instruction
- 25.4 AES Crypto Module
  - 25.4.1 Key and State Memory
  - 25.4.2 DMA Support
- 25.5 Register Description – AES
- 25.6 Register summary – AES
- 25.7 Interrupt vector summary
26. CRC – Cyclic Redundancy Check Generator
- 26.1 Features
- 26.2 Overview
- 26.3 Operation
- 26.4 CRC on Flash memory
- 26.5 CRC on DMA Data
- 26.6 CRC using the I/O Interface
- 26.7 Register Description
- 26.8 Register summary
27. EBI – External Bus Interface
- 27.1 Features
- 27.2 Overview
- 27.3 Chip Select
- 27.4 EBI Clock
- 27.5 SRAM Configuration
- 27.6 SRAM LPC Configuration
  - 27.6.1 Multiplexing Data with Address Byte 0
  - 27.6.2 Multiplexing Data with Address Byte 0 and 1
- 27.7 SDRAM Configuration
- 27.8 Combined SRAM & SDRAM Configuration
- 27.9 I/O Pin and Pin-out Configuration
- 27.10 Register Description – EBI
- 27.11 Register Description – EBI Chip Select
- 27.12 Register summary – EBI
- 27.13 Register summary – EBI chip select
28. ADC – Analog-to-Digital Converter
- 28.1 Features
- 28.2 Overview
- 28.3 Input Sources
  - 28.3.1 Differential Input
  - 28.3.2 Differential Input with Gain
  - 28.3.3 Single-ended Input
  - 28.3.4 Internal Inputs
- 28.4 ADC Channels
- 28.5 Voltage Reference Selection
- 28.6 Conversion Result
- 28.7 Compare Function
- 28.8 Starting a Conversion
  - 28.8.1 Input Source Scan
- 28.9 ADC Clock and Conversion Timing
  - 28.9.1 Single Conversion without Gain
  - 28.9.2 Single Conversion with Gain
  - 28.9.3 Single Conversions on Two ADC Channels
  - 28.9.4 Single Conversions on Two ADC Channels, CH0 with Gain
  - 28.9.5 Single Conversions on Two ADC Channels, CH1 with Gain
  - 28.9.6 Free Running Mode on Two ADC Channels with Gain
- 28.10 ADC Input Model
  - 28.10.1 Gain Stage Impedance mode
- 28.11 DMA Transfer
- 28.12 Interrupts and Events
- 28.13 Calibration
- 28.14 Channel Priority
- 28.15 Synchronous Sampling
  - 28.15.1 Synchronous sampling of two ADC inputs
  - 28.15.2 Synchronous sampling on event
  - 28.15.3 Synchronous sampling of two ADCs
- 28.16 Register Description – ADC
  - 28.16.1 CTRLA – Control register A
  - 28.16.2 CTRLB – ADC Control register B
  - 28.16.3 REFCTRL – Reference Control register
  - 28.16.4 EVCTRL – Event Control register
  - 28.16.5 PRESCALER – Clock Prescaler register
  - 28.16.6 INTFLAGS – Interrupt Flag register
  - 28.16.7 TEMP – Temporary register
  - 28.16.8 CALL – Calibration Value register
  - 28.16.9 CALH – Calibration Value register
  - 28.16.10 CHnRESH – Channel n Result register High
  - 28.16.11 CHnRESL – Channel n Result register Low
    - 28.16.11.1 12-/8-bit Mode
    - 28.16.11.2 12-bit Mode, Left Adjusted
  - 28.16.12 CMPH – Compare register High
  - 28.16.13 CMPL – Compare register Low
- 28.17 Register Description – ADC Channel
  - 28.17.1 CTRL – Channel Control register
  - 28.17.2 MUXCTRL – ADC Channel MUX Control registers
  - 28.17.3 INTCTRL – Channel Interrupt Control registers
  - 28.17.4 INTFLAGS – ADC Channel Interrupt Flag registers
  - 28.17.5 RESH – Channel n Result register High
  - 28.17.6 RESL – Channel n Result register Low
    - 28.17.6.1 12-/8-bit Mode
    - 28.17.6.2 12-bit Mode, Left Adjusted
  - 28.17.7 SCAN – Channel Scan register
- 28.18 Register summary – ADC
- 28.19 Register summary – ADC channel
- 28.20 Interrupt vector summary
29. DAC – Digital to Analog Converter
- 29.1 Features
- 29.2 Overview
- 29.3 Voltage reference selection
- 29.4 Starting a Conversion
- 29.5 Output and output channels
- 29.6 DAC Output model
- 29.7 DAC clock
- 29.8 Low Power mode
- 29.9 Calibration
- 29.10 Register description
- 29.11 Register summary
30. AC – Analog Comparator
- 30.1 Features
- 30.2 Overview
- 30.3 Input Sources
  - 30.3.1 Pin Inputs
  - 30.3.2 Internal Inputs
- 30.4 Signal Compare
- 30.5 Interrupts and Events
- 30.6 Window Mode
- 30.7 Input Hysteresis
- 30.8 Propagation Delay vs. Power Consumption
- 30.9 Register Description
- 30.10 Register summary
- 30.11 Interrupt vector summary
31. IEEE 1149.1 JTAG Boundary Scan Interface
- 31.1 Features
- 31.2 Overview
- 31.3 TAP - Test Access Port
- 31.4 JTAG Instructions
- 31.5 Boundary Scan Chain
  - 31.5.1 Scanning the Port Pins
  - 31.5.2 Scanning the PDI Pins
- 31.6 Data Registers
32. Program and Debug Interface
- 32.1 Features
- 32.2 Overview
- 32.3 PDI Physical
- 32.4 JTAG Physical
- 32.5 PDI Controller
- 32.6 Register Description – PDI Instruction and Addressing Registers
- 32.7 Register Description – PDI Control and Status Registers
- 32.8 Register Summary
33. Memory Programming
- 33.1 Features
- 33.2 Overview
- 33.3 NVM Controller
- 33.4 NVM Commands
- 33.5 NVM Controller Busy Status
- 33.6 Flash and EEPROM Page Buffers
  - 33.6.1 Flash Page Buffer
  - 33.6.2 EEPROM Page Buffer
- 33.7 Flash and EEPROM Programming Sequences
  - 33.7.1 Flash Programming Sequence
  - 33.7.2 EEPROM Programming Sequence
- 33.8 Protection of NVM
- 33.9 Preventing NVM Corruption
- 33.10 CRC Functionality
- 33.11 Self-programming and Boot Loader Support
- 33.12 External Programming
- 33.13 Register Description
- 33.14 Register Summary
34. Peripheral Module Address Map
35. Instruction Set Summary
36. Appendix A: EBI Timing Diagrams
- 36.1 SRAM 3-Port ALE1 CS
- 36.2 SRAM 3-Port ALE12 CS
- 36.3 SRAM 4-Port ALE2 CS
- 36.4 SRAM 4- Port NOALE CS
- 36.5 LPC 2- Port ALE12 CS
- 36.6 LPC 3- Port ALE1 CS
- 36.7 LPC 2- Port ALE1 CS
- 36.8 SRAM 3- Port ALE1 no CS
- 36.9 SRAM 4- Port NOALE no CS
- 36.10 LPC 2- Port ALE12 no CS
- 36.11 SDRAM init
- 36.12 SDRAM 8-bit Write
- 36.13 SDRAM 8-bit read
- 36.14 SDRAM 4-bit write
- 36.15 SDRAM 4-bit read
- 36.16 SRAM refresh
37. Nomenclature
- 37.1 Symbols and operators
- 37.2 Numerical notation
  - 37.2 Numerical notation
- 37.3 Memory size and type
- 37.4 Register and bits
- 37.5 Abbreviations
- 37.6 Conventions
38. Datasheet Revision History
- 38.1 8331F – 04/2013
- 38.2 8331E – 01/2013
- 38.3 8331D – 12/2012
- 38.4 8331C – 04/2012
- 38.5 8331B – 03/12
- 38.6 8331A – 07/11
Table Of Contents

XMEGA AU Manual Atmel 8331 8 And 16 Bit AVR Microcontroller

Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual

Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual

Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual

Atmel-8331-8-and-16-bit-AVR-Microcontroller-XMEGA-AU_Manual

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