B03P 4760 0111A M2331K M2333K Micro Disk Drives CE Manual
B03P-4760-0111A M2331K-M2333K Micro-Disk Drives CE Manual B03P-4760-0111A M2331K-M2333K Micro-Disk Drives CE Manual
User Manual: B03P-4760-0111A M2331K-M2333K Micro-Disk Drives CE Manual
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REVIStON'ltEQ'!)R0
Edition
Date published
01
Jan., 1985
Revilld' c.ontents
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Specification No.: B03P·4760:Q'111 A
The contents of this manual is subject to change
without prior notice.
All Rights Reserved,
Copyright © 1985 FUJITSU LIMITED
B03'P·4760·0111A .. ;01
Comments concerning this manual to one of the following addresses:
FUJITSU LIMITED
I nternational Market; ng
Marunouchi '·6·1, Chiyoda·ku, Tokyo 100 JAPAN
TEL:
03·216·3211
FAX: 03·213·7174,03·21-6,9353 i; .,,~,\
'" :c,
TLX;
J 2 2 8 3 3 : ) l / 1 ' :':, ,~",
Cable: "FUJITSU LIMITED LIMITED';
FUJITSU AMERICA INC.
-,-?::~~ . .
3055 Orchard Drive, San Jose, California 95134-2017. U.S.A.
TEL:
408·988·8100
FAX: 408·945·1318
TLX:
230·176207
TWX: 910·338·2193
FUJI,TSU EUROPE LIMITED
54 Jermyn Street, London SWl Y 6NQ, ENGLAND
TEL.:
1·408·0043
FAX: '·629·9826
TLX:
263871 FT E RP G
FUJITSU ELECTRONIK GmbH
Sonnen StraBe 29.0·8000 Miinchen 2. F.R. GERMANY
TEL;
89·592891 - 4
FAX: 89·592895
TLX:
41·5213994
FUJITSU NORDIC A8
Kungsgaton 44, 111 35 Stockholm, SWEDEN
TEL:
8·231125
FAX: 8·106865
TLX:
54·13411
FUJITSU ITALIA S.p.A.
Via Lazzaroni. 4, 20124 Milano, ITALI A
TEL:
2·607·3601
FAX: 2·688·6637
TLX;
350142 FJITLY I
FUJITSU AUSTRALI,A L.IMITED
41 Mclaren Street, North Sydney, N.S.W, 2060. AUSTRALIA
TEL;
2·922·1822
FAX: 2·922·2653
TLX;
71·25233
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Preface
This manual explains how to operate, handle, and maintain the M23J1K/M2333K microdisk drives.
The information is· provided in 10 sections:
)
SECTION
SECTION
SECTION
SECTION
SECTION
SECTION
SECTION
SECTION
SECTION
SECTION
1
2
3
4
5
GENERAL OESCR IPTION
OPE RA nON
INSTALLATION
THEORY OF OPERATION :::,
TROUBLESHOOTING GUIDE
6 MArNTENANCE
7
SPARE PARTS .LIST
SIC DETAIL
:." .. ;,/
,.,;,
9, PARTS LIST
10
SCHEMATICS
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Table of Contents
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1.
1.1
1.1.1
1.1.2
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.2.6
1.3
1.3.1
1.3.2
Page
GENERAL DESCRIPTION ........................................ 1:1
. GENERAL DESCRiPTION ........................................ 1-1
General Description .............................................. 1-'
Features ........................................................ 1-1
SPECIFICATIONS ............................................... 1-2
Unit Specifications ............................................... 1-2
Physical Specifications ............................................ 1-2
Power Requirements ............................................. 1-2
Data Recording Specifications ...................................... 1-5
Reliability ..................................................... 1-6
Data Integrity ................................................... 1-6
CONFIGURATION .............................................. 1-10
Fundamental Unit Configuration ., .................................. 1-10
Options ................ ; ...................................... 1-12
2.
2.1
2.2
2.3
2.3.1
2.3.2
2.4
2.5
2.5.1
2.5.2
2.5.3
OPERATION ................................................... 2-1
GENERAL DESCRiPTION ........................................ 2-1
POWERING UP/DOWN ........................................... 2-1
CONTROL AND INDICATORS .................................... 2-1
Operator Panel (option) ........................................... 2-1
PCB Assembly .................................................. 2-2
Dual Channel PCB Assembly (Option) ................................ 2-5
POWER SUPPLY ................................................ 2-6
Main Line Switch ...........•...................•................ 2-6
Indicators (LEDs) ................................................ 2-6
Device Alarm ................................................... 2-6
3.
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
. 3.5
3.5.1
INSTALLATION ................................................ 3-1
GENERAL DESCRiPTION: ....................................... 3-1
UNPACKING ................................................... 3-1
VISUAL INSPECTION ............................................ 3-1
INSTALLATION ................................................ 3-1
Mounting Dimensions .... , ........................................ 3-1
Service Area .................................................... 3-5
Securing the Unit ................................................ 3-6
Cooling* ....................................................... 3-10
MOUNTING OF OPTIONS ........................................ 3-12
Mounting the fan unit ............................................ 3-12
Mounting the Panel Unit .......................................... 3-14
Installation Mounting Tray ...................... ; .................. 3-15
Mounting the Dual Channel Option .................................. 3-28
CABLING ..................................................... 3-30
Connectors Ori Unit Side .......................................... 3-30
Power Cable Connection .......................................... 3-30
Interface Cabling ............................... ; ................ 3-32
System Grounding ............................................... 3-34
MODE SELECT SETTING ......................................... 3-36
Disk Addressing ................................................. 3-37
Tag 4/5 Enable .............................. '.' .................. 3-38
File Protect .................................................... 3-38
Device Type (optional) ............................................ 3-39
ON-Side Switch (for vertical mount) ................................. 3-39
Sector Counting ................................................. 3-40
3.5.2
3.5.3
3.5.4
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
B03P-4760-0111A ... 01
v
3.8
3.9
SHIPPING .............. , , , ... , .. '.' . .. .· .. ·.. ,.,., .... , .. , ....... 3-42
STORAGE AND REPACKING " .,'.;....'.: ',: •.... '.' ......... , ..' ....• , 3-42
THEORY OF OPERATION., .. ': .......; .;.;::1';:.,•.•••••••••••••••• , , •••• , ••• 4-1
. GENERAL DESCRIPTION .............. ~t~" • • . . • • • • • • . . • • . • • . • . • • • • 4-1
MECHANICAL ASSEMBLIES. '.. '. :.', '" .. :; ...... , ............. '" .. 4-1
Disk Enclosure .......... .' .... " . "':.c.~' .. ~ '.' .... , ..................... 4-1
4,2.t; Air Circulation in DE .......... ; . .' :~'.: :: .................... , ...... 4·'
4.2.:rr) . Spindle Drive Motor ...... '.... ' .', ........ '.......................... 4-2
4.2-4 ..... Actuator Arm Assembly ... '.......... ' ............................... 4-2
4.3 '
MAGNETIC HEADS AND RECORDING MEDIA .. , , . , , .. , , .... , .. , .. , . 4-4
4.3.1<:', , Ma.gnetic Heads '.,., ... , .. ,. , ........ , ....... , , ...... , ..... , ...... 4·4
4.3.2
Recording Media (Magnetic Disk) ... , .... , . , , , , ... , ..... , , . , , . , , ...... 4·5
4.3.3 . Servo Track Format , .. , " ."
... , .... , , ........................ 4·5
4.3.4
Data Surface Format ......... , ......... , . , ....................... 4·12
4.3.5
Head and Surface Configuration ~ .................................... 4-12
4,4
FORMAT ....................................... , .•............. 4·13
4.4.1
Description .................... , ........ , ....................... 4-13
4.4.2
Fixed Sector Format ............................................. 4-14
4.4.3
Descripti.on of Format Parameters ...... , .......................... , . 4·15
4.5
INTERFACE .............. , ......... , ....................... , .. 4·16
4.5.1
Introduction .................................................... 4-16
4.5,2
I nterface Cabling ............................................. ". 4·17
4.5.3
Type and Name of Signal Lines ..................................... 4-18
4,5.4
Description of Signal Lines ......................................... 4-19
4.5.5
Timing ......................................................... 4-26
4.5.6
Read/Write Timing ............................................... 4-33
4.5.7
Interface Transmission ............................................ 4·36
4.5.8
Connectors and Cables ............................................ 4·40
4.5.9
Connector Pin Assignment ......................................... 4-41
4.6
ELECTRICAL CIRCUIT FUNCTION ........... ' .................. , .. 4-42
4.6.1
Start/Stop Control ............................................... 4-42
4.6.2
DC Motor Control ......... , ....................... , ............. 4·51
4.6.3
Unit Selection .............................. , ................... 4·57
4.6.4
Seek Control Logic Function ....................................... 4·65
4.6.5
Servo Circuit Function ............................................ 4·80
4.6.6
Index/Sector/Guard Band Generate FunctIon .......................... 4·'05
4.6.7
Head Selection ................ '.................................. 4-111
4.6.8
Read/Write Function ...................................... , ...... 4·113
4.6.9
VFO ................................................ , .......... 4·123
4.
4,1
4.2
4.2·,1-;.
5.
5.1
5.2
5.3
5.4
5.5
6.
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.3
6.4
6.5
vi
TROUBLESHOOTING GUIDE .... ; ................................ 5·1
INTRODUCTION ............................................... 5·'
ERROR STATUS ................ , ........................... , ... 5·1
FAULT ISOLATION LIST ..................................... , .. 5·3
TROUBLESHOOTING SYMBOL ......... :-.--: ....................... 5-6
TROUBLESHOOTING FLOW CHART ........ ; ...................... 5·6
MAINTENANCE ........ , ...... ; ................................ 6-1
INTRODUCTION ............................................... 6-1
GENERAL PRECAUTIONS ....................................... 6·1
Power On/Off, ................................................... 6-1
Parts Replacement ................................... , ......... , . 6·'
Dual Channel Switches ......................... , .............. , ... 6-1
Other ....................................................... , .. 6-1
MAINTENANCE TOOLS AND EQUIPMENT .... , ..................... 6·'
PREVENTIVE MAINTENANCE .............................. , ..... 6·1
PCB ASSEMBLY REPLACEMENT ................................ ~. 6-1
B03P-4760·01 ",A,.::Oi
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6.5.1
6.5.2
6.5.3
6.5.4
6.6
6.6.1
6.6.2
6.6.3
PCB Assembly Arrangement ..... ;............................ : ....... 6·1
KGFM PCB Assembly ReplacementProce!=lure ......................... 6·2
CZOM PCB Assy. Replacement Procedure .•........................... 6-3
TVQM PCB Assembly· Replacement· . . <:.0............................. :~ . 6-5 .~
PCB CHECK AND ADJUSTMENT'. ''::.: .. '. '........................ ',~ .6-6 '
Test Point Arrangement on PCB ..... '.'.:.,:. : . ; ................... ; :'.~'•. 6~6~' "
PCB Adjustment after PCB Replacement·. ',' ........................;, ..... 6:?O~'>
Electrical Measurement •.• ,' ......... .:.,' ..................... " . ~d~ 6-21~:'.
7.
SPARE PARTS LIST .. ~ ..•..... '.' . "~'.'.' .............•.... '" . 'J:'~':,~ • 7-l~:
SPARE PARTS LIST ..........• ',),' ~ .• ;",,' .. .; ..............•'. ; .? ",.\.... 7-,'
..
7.1
8.
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
LOGIC CONVENTIONS AND SYMBOLOGY·....... ~ .............. '~v.~':': . 8-1' ,
TTL Logic ....................................................... 8-1
ECL Logic ......................... :' .......... , ......•......... 8-2
Logic Symbology ................................................ 8-3
INTERCHANGEABILITY GUIDE .................................. 8-4
TTL IC Interchangeability ......................................... 8-4
EC L I C I nterchangeabil ity ......................................... 8-6
Linear I C Interchangeability ........................................ 8-6
FUJITSU Proprietary IC .......................................... 8-6
FUJITSU PROPRIETARY IC DETAIL ............................... 8-7
9.
'PARTS LIST ................................................... 9-l .;
:~fiJ~0~STION' : : : : : : :: : : : : :':::,: >::~::: :~: :::::-: :::: :::: :':;';,~:( ~J~:.
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BQ3P~1760.0111A ... 01
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Illustrations
FIGURE
1-2-1
1-2-2
1-2-3
1-24
1-2-5
1-3·1
1·3-2
1·3·3
1-34
1-3·5 (a)
1·3·5 (b)
1-3-6
1-3-7
1-3-8
1-3-9
1-3-10
1-3-11
1-3-12
1-3-13
1-3-14
1-3-15
1-3-16
1-3-17
1-3-18
2-3-1
2-3-2
24-1
2-5-1
3-2-1
34-1
34-2
34-3
344
34-5
34-6
34-7
34-8
34-9
3-5-1
3-5-2
3-5-3
3-54
\
)
3-5~5
3-5-6
3-5-7
3-5-8
3-5-9
\
l
3-5~10
+24V DC Load Current on Power Up Sequence .......................
Total +24V DC Load Current (Ready) ..............................
Positioning Time Profile ......•..................................
Media Defect Format 1 .........................................
Skip Displaced Format ...........•........................•.....
Fundamental Configuration ........ ; .............................
Block Diagram .................................................
Fan Unit .................. -. ............................-......
Optional Fan Unit Alarm ........................................
Power Supply Unit: B14L-5105-0100A ........................., ...
Power Supply Unit: B14L-5105-0154A#Al .........................
Panel Unit ...................................................
Mounting Dimensions of Panel Unit ................................
19" Rack Mount Installation .....................................
Mounting-Tray and Brackets .....................................
A-Cables for Daisy-Chain ........................................
Power Cable B660-0625-T327 A ...................................
Power Cable B660-1995-T041A ...................................
Cable B660-0625-T328A, T355A
(Fan unit - Power supply unit) ...................................
Cable B660-0625-T329A
(Dual Channel PCB assy. - Power supply unit) .......................
Cable B660-1995-T003A
(E501 A Panel unit - Drive unit connecting) .........................
Dual Channel Option (E401 A) ....................................
Dual Channel Option (E402A) ...................••...............
Dual Channel PCB Assembly Connector Location .....................
Page
1-3
1-4
1-5
1-8
1-9
1-10
1-11
1-14
1-15
1-15
1-16
1-17
1-18
1-19
1-20
1-21
1-22
1-22
1-22
1-23
1-23
1-24
1-25
1-26
Operator Panel (Optional) ....................................... '2-1
Fault Display Location on KGFM PCB ........................•.... 2-2
Dual Channel PCB Assembly ..................................... 2-5
Front View of Power Supply ...•................................. 2"6
External View of Carton ........................................ 3-2
Mounting direction .....•.. , .... .' ....................... , ....... 3-3
Mounting Dimensions of the Unit ................................. 3-4
Maintenance Access on the Unit .•................................. 3-5
Securing the Unit (Example 1) .•.......................•.......... 3-6
Securing the Unit (Example 2) ....•..•............................ 3-7
Form of the Stopper ........................................... 3-8
Dimensions of the_Screw Holes .•.....•........................... 3-9
Recommended Air Flow Posture .................................. 3·10
Examples of Installation Cooling .................................. 3-11
Mounting the Fan Unit .......................................... 3-13
Mounting the Panel Unit ........................................ 3-14
I nstallation in the 19-inch Rack ................................... 3-15
Bracket Assembly .............................................. 3-16
Bracket Assembly Mounting on the 19-inch Rack ........... , ......... 3-17
Mounting Tray to the Outer Rails ................................. 3-18
Rubber Cushion Mounting ........................................ 3-19
Bracket Mounting .............................................. 3-20
Cushion Support ....................................-. .......... 3-2~
Mounting the Unit ............................................. 3-22
B03P-4760-01 11 A ... 0 1
ix
3·5·11
3·5-12
3-5-13
3·5·14
3-5-15
3·5-16
3·5·17
3·5·18
3-5-19
3-6-1
3-6-2
3-6-3
3-6-4
3-6-5
3·6-6
3-6-7
3-6·8
3-7·1
3-1-2
3·7·3
3·74
3·7·5
3·7·6
4-2-1
4-2·2
4·2·3
4-3-1
4·3-2
4-3·3
4·34
4·3·5
4-3-6
4·3·7
4·3-8
44-1
4·5·'
4-5-2
4-5·3
4-5-4
4-5-5
4-5-6
4-5-7
4-5-8
4-5-9
4-5-10
4·5·'1
4·5·12
4·5-13
- 4·5·14
4-5-15
4-5-16
4·5-17
4·5-18
4-5-19
4·5·20
4-5-21
x
Mounting the Panel Unit ........................................ 3-23
Power Supply Unit Installation ................................... 3-24
Dual Channel Option Installation 1 ................................ 3-25
Dual Channel Option Installation 2 ................................ 3-25
Dual Channel Frame Mount .................. " ................
3-26
3-26
Dual Channel Cabling ......... ; ..........
Dual Channel Top Cover Fixing ................................... 3-27
Dual Channel Interface Cables Holding ............................. 3·27
Mounting the Dual Channel Option .......... , ..................... 3-29
Mounting Positions of Connectors ................................. 3-30
Pin Assignment and Voltages ..................................... 3-31
Power Cable (Specification: B660-0625·T327A) ...................... 3-31
System Interface Cabling .................
3·33
3-33
Interface Cabling ..........................
Cable Termination ..... -. ....................................... 3-34
SG Terminal ................................... '.' ............. 3-35
FG/SG Connection ............................................. 3·36
Mode Select Switch Location ..................................... 3-37
Disk Addressing ................... , ........................... 3-37
Tag 4/5 Enable ................................................ 3-38 File Protect .................................................. 3-38
Device Type .................................................. 3-39
On-Side ........................... -. ......................
3-39
0
•
0
••••••••••••••••••••••
0
• • • • • • • • • • • • • • • • • • • • • •
0
•••••••••••••••••••
0
••
Air Circulation Inside DE .....................................
4-'
Spindle Drive Motor ............................................ 4-2
Actuator Arm Assembly .............-....... -..................... 4-3
Read/Write Head ..
4-4
Tapered Flat Slider ............................................. 4-4
Servo Track Configurati-on ., ........................
4-6
Normal Bit Pattern ............
4-8
Index Bit Pattern .............................................. 4·9
Dual-Phase Composite Servo Signal ................................ 4-11
M2331 Surface Configuration ................
4-12
M2333 Surface Configuration .................................... 4-13
Fixed Sector Format ........................................... 4·14
I nterface Cabling ........................... : .................. 4·17
"A" Cable Signals .............................................. 4-18
"B" Cable Signals .............................................. 4-18
Storage Addressing M2331 K ..................................... 4-20
Storage Addressing M2333K ..................................... 4-20
Unit Select Timing .....•...........•........................... 4-26
Priority Select Timing ...........•....•......................... 4-27
Direct Seek Timing ............................................. 4-28
Same Cylinder Address .......................................... 4-28
Tag 1 to Tag 2 Timing .......................................... 4-29
Offset Plus/Minus Timing ........................................ 4·29
Fault Clear Timing ................ , ............................ 4-30
RTZ Timing ...................
4·30
Channel Ready Timing
4·31
Tag 4/5 Timing ................................................ 4-31
Index and Sector Timing ....................................... -. 4-32
Write Data and Write Clock Timing ................................. 4-32
1 F Read Clock and Read Data Timing .............................. 4-33
Format Write Timing '" ........................................ 4-33
4-34
Write DataTiming ................ ; " ........
Read DataTiming ....
4-34_
0
0
••
• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
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0
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0
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B03P-4760·01 11Ao .. 01
)
)
4-5·22
4·5·23
4·5·24
4·5-25
4-5·26
4~5·27
)
4·5-28
4·6·1
4-6·2
4·6·3
4·6·3
4·6·3
4-6·3
4·6-4
4-6-5
4-6·5
4-6-6
4-6-7
4-6-8
4-6·9
4·6·10
4-6·10
4-6-10
4-6·11
4·6·12
4-6·13
4·6·13
4-6-13
4-6·14
4-6·15
4-6·16
4·6·16
4-6-16
4-6-17
4·6-18
4-6-18
4-6-19
4-6-20
4-6-21
4-6-21
4-6-22
4,,(;-23
4-6·24
4·6·25
4-6-26
4-6-27
4-6-28
4-6·28
4-6-29
4-6-29
4-6-30
4-6·30
4-6-31
4-6-32
4-6-33
4-6·34 .
Write-To-Read Recovery Time .•.................................. 4-35
Head Select Transient ............•.............................. 4-35
1F Write Clock in Reading ....................................... 4-36
Driver Logic Diagram ,(SN751 10) ..•......... '.' .................... 4-37
Receiver Logic Diagram (SN75107175108) .......................... 4-37
Balanced Transmission of "A" Cable ............................... 4-38
Balanced Transmission "B" Cable ................................. 4-39
Start/Stop Control Block Diagram ................................. 4-44
Power-up Sequence Control Btock Diagram ..............•........... 4-45
Power-up Sequence Flow Chart (Sheet 1 of 4) ........................ 4-46
Power-up Sequence Flow Chart (Sheet 2 of 4) .............•.......... 4-47
Power·up Sequence Flow Chart (Sheet 3 of 4) ........................ 4-48
Power-up Sequence Flow Chart (Sheet 4 of 4) ........................ 4-49
Power-up Sequence Timing Chart ........ : ......................... 4-50
DC Motor Control Block Diagram (Sheet 1 of 2) ...................... 4,52
DC Motor Control Block Diagram (Sheet 2 of 2) ...................... 4-53
Power Up DC Motor Control ..................................... 4·55
DC Motor Accelerate/Inertia Mode Control ................•......... 4·56
Functional Block Diagram of Dual Channel .......................... 4-59
Functional Block Diagram of Select/Reserve ......................... 4-60
Select/Reserve Flow Chart (Sheet 1 of 3) .....................•...... 4-61
Select/Reserve F low Chart (Sheet 2 of 3) ............................ 4-62
Select/Reserve Flow Chart (Sheet 3 of 3) ............................ 4-63
Select/Reserve Timing Chart ..................................... 4-64
Seek Control Logic Block Diagram ................................. 4-67
Go To Zero Flow Chart (Sheet 1 of 3) ............................... 4-69
Go To Zero Flow Chart (Sheet 2 of 3) .............................. 4-70
Go To Zero Flow Chart (Sheet 3 of 3) .............................. 4-71
I nitial Seek Timing Chart ........................................ 4-72
Return To Zero Timing Chart .................................... 4·74
Direct Seek Flow Chart (Sheet 1 of 3) .............................. 4-76
Direct Seek Flow Chart (Sheet 2 of 3) .............................. 4-77
Direct Seek Flow Chart (Sheet 3 of 3) ..........................•... 4-78
Direct Seek Timing Chart ...... '.................................. 4·79
Position Sensing Block Diagram (Sheet 1 of 2) ........................ 4-81
Position Sensing Block Diagram (Sheet 2 of 2) ........................ 4-82
PLO and Peak Hold Timing Chart ................................. 4-84
Servo Signal to Position Signal Conversion ........................... 4-85
Servo Control Block Diagram (Sheet 1 of 2) ......................... 4~87
Servo Control Block Diagram (Sheet 2 of 2) ......................... 4-88
Position Deteet Timing Chart ..................................... 4-89
Velocity Generator Timing Chart .... ; .............. : .............. 4-90
Fine Position Generator Timing Chart .............................. 4-92
Direct Seek Target Velocity Generator .............................. 4-94
GTZ Target Velocity Generator ........................ '........... 4-95
Clamp Positon Timing Chart ..................................... 4-97
Direct Seek Signal Flow (Sheet 1 of 2) .............................. 4-99
Direct Seek Signal F low (Sheet 2 of 2) .............................. 4-100
GTZ Signal Flow (Sheet 1 of 2) ................................... 4-101
GTZ Signal Flow (Sheet 2 of 2) ....•.............................. 4-102
Linear Mode Signal Flow (Sheet' of 2) ............................. 4-' 03
Linear Mode Signal Flow (Sheet 2 of 2) ............................. 4-104
I ndex/Guard Band Patterns Detect B lock Diagram ..................... 4-106
Index Detect Timing Chart ....................................... 4-' 07
Guard Band Pulse Detect Timing Chart ............................. 4-109
Sector Generator Block Diagram .................................. 4-110
.B03P-4760·0111A ... 01
xi
4-6-35
4-6-36
4-6-37
4-6-38
4-6-39
4·640
4·641
4--6-42
4-6-43
4·6-44
4-6-45
4-6-46
4·6-47
4-6-48
4-6-49
4-6-50
4-6-51
4-6-52
5-5-1
5-5-1
5·5·2
5-5-3
5·5-4
5·5-4
5-5-4
5-5-4
5·5-4
5·5-4
5·5·5
5·5·5
5·5·5
5·5·5
5·5·5
5·5-5
5-5"6
5·5-6
5·5-6
5-5-6
5-5-6
5-5-6
5·5·7
6-5-7
5·5·7
5-5-7
5-5-7
5·5·7
5·5-8
5·5-8
5·5-8
5·5-8
5·5-8
6-5-1
6·5-2
6·5·3
6-S-4
6-5·5
xii
Sector Generator Timing Chart ................................... 4·110
Head Selection Block Diagram ................. ".................•. 4-112
Data Write ................................................... 4-113
Data Read ................................................... 4-114
2·7 Coding .............................................. ' ..... 4-114
Write Operation Block Diagram ................................... 4·116
2-7 Coding and Write Compensation Block Diagram ................... 4-118
Write Compensation Timing Chart ................................. 4·119
Read Write Bus Switch .......................................... 4-120
AGe Squelch Function ......................................... 4·121
Read Operation Block Diagram .' .................................. 4·122
VFO Block Diagram ............................................ 4-124
VFO Timing Chart ............................................. 4-126
Data Window Timing Chart ...................................... 4-127
VFO Control Logic Block Diagram ................................ 4-129
Initial VFO Control Timing Chart ..................•.............. 4-130
VFO Control Timing Chart" ...................................... 4-132
2-7 Decoder Block Diagram ...................................... 4·134
Alarm Flow Cnart (Sheet 1 of 2) .................................. 5·7
Alarm Flow Chart (Sheet 2 of 2) .................................. 5·8
Not Selected Flow Chart ........................................ 5·9
Not Power Ready F low Chart .................................... 5·10
Power-up Sequence Check F low Chart (Sheet 1 of 6) .................. 5·11
Power·up Sequence Check Flow Chart (Sheet 2 of 6) .................. 5·12
Power·up Sequence Check Flow Chart (Sheet 3 of 6) .................. 5·13
Power·up Sequence Check Flow Chart (Sheet 4 of 6) .................. 5·14
Power-up Sequence Check F low Chart (Sheet 5 of 6) .................. 5·15
Power-up Sequence Check Flow Chart (Sheet 6 of 6) .................. 5·16
Device Check F low Chart (Sheet 1 of 6) ............................ 5-17
Device Check F low Chart (Sheet 2 of 6) ............................ 5·18
Device Check F low Chart (Sheet 3 of 6) ............................ 5-19
Device Check Flow Chart (Sheet 4 of 6) ............................ 5·20
Device Check Flow Chart (Sheet 5 of 6) ............................ 5·21
Device Check Flow Chart (Sheet 6 of 6) ............................ 5-22
Seek Error Flow Chart (Sheet 1 of 6) ............................... 5·23
Seek Error Flow Chart (Sheet:2 of 6) .............................. 5·24
Seek Error Flow Chart (Sheet 3 of 6) ... ; .......................... 5·25
Seek Error Flow Chart (Sheet 4 of 6) ............................... 5-26
Seek Error Flow Chart (Sheet 5 of 6) ............................... 5-27
Seek Error Flow Chart (Sheet 6 of 6) ............................... 5·28
Read Error Flow Chart (Sheet 1 of 6) .............................. 5·29
Read Error Flow Chart (Sheet 2 of 6) ....•......................... 5-30
Read Error Flow Chart (Sheet 3 of 6) .............................. 5-31
Read Error Flow Chart (Sheet 4 of 6) .............................. 5"32
Read Error Flow Chart (Sheet 5 of 6) .............................. 5-33
Read Error Flow Chart (Sheet 6 of 6) .............................. 5·34
Dual Channel Malfunction Flow Chart (Sheet 10f 5) .................. 5·35
Dual Channel Malfunction Flow Chart (Sheet 2 of 5) .................. 5·36
Dual Channel Malfun,ction Flow Chart (Sheet 3 of 5) .................. 5-37
Dual Channel Malfunction Flow Chart (Sheet 4 of 5) .................. 5·38
Dual Channel Malfunction Flow Chart (Sheet 5 of 5) .................. 5·39
PCB Assy. Arrangement ......................................... 6·2
KGFM PCB Assembly Replacement ................................ 6·3
" CZOM PCB Replacement .................................... : ... 6-4
TI XM Connection ............................................. 6·5
TVQM PCB Assembly Replacement ................................ 6·6
B03P-4 760-0111 A ... 01
)
6-6-1
6-6-2
6-6-3
6-6-4
6-6-5
6-6-6
6-6-7
6-6-8
6-6-9
6-6-10
6-6-11
6-6-12
8-2-1
8-2-2
8-2-3
8-4-1
8-4-2
KGFM PCB Assembly Test Points ................................. 6-7
CZOM PCB Assembly Test Points Arrangement ....................... 6-12
XCGM PCB Assembly Test Points ................................. 6-17
Position Signal Gain Adjustment .................................. 6-20
Positioning Time Adjustment ..................................... 6-21
Read Output Measurement ....................................... 6-21
PLO Free-run Frequency Adjustment .............................. 6-22
Delayed Data One-shot Adjustment ................................ 6-23
Reference Pulse Adjustment ...................................... 6-23
Servo Pulse Window Adjustment .................................. 6-24
PlO Single-shot Adjustment .................................•... 6-23
DAC Output Adjustment ........................................ 6-25
9-'
9-2
M2331K/M2333K Micro Disk Drive .......................... '" ... 9-1
Frame Unit (1/2) .............................................. 9-3
Frame Unit (2/2) .............................................. 9-5
9-2
low Power Schottky I C level .................................... 8-1
TTL Schottky IC level ......................................... 8-2
ECl logic level ............................................... 8-3
B500 LSI Package ............................................. 8-11
MB 15238C Block Diagram ....................................... 8-12
)
B03p·4760·0111A ... 01
xiii
)
Tables
Page
1-2
1-2
1-2
1-5
1-12
1-13
1-24
TABLE
1-2-1
1-2-2
1-2-3
1-2-4
1-3-1
1-3-2
1-3-3
Basic Specifications ............................................
Physical Specifications ..........................................
DC Power Requirement .. " .....................................
Data Recording Specifications ....................................
Options ...............•.....................................
Specifications of fan units .......................................
Dual Channel Option ...........................................
2-3-1
Fault Indicator ................................................. 2-3
3-4-1
3-7-1
3-7-2
3-7-3
3-7-4
3-7-5
3-7-6
3-7-7
Thermal Check Point ........................................... 3-'0
Disk Addressing ............................................... 3-37
Tag 4/5 Enable ................................................ 3-38
File Protect .................................................. 3-38
Device Type .................................................. 3-39
On-Side Switch ................................................ 3-39
Sector Counting Keys ........................................... 3-40
Commonly Used Sector Counting ................................. 3-42
4-3-1
4-5-1
4-5-2
4-5-3
4-5-4
4-5-5
4-5-6
4-5-7
4-5-8
4-5-9
4-5-10
4-5-11
4-6-1
4-6-2
4-6-3
Index, IGB2, IGB1,and OGB Patterns .............................. 4-12
Tag/Bus Lines ................................................. 4-19
Status Lines Determined by Tag 4/5 ............................... 4-21
Fault/Seek Error Status ......................................... 4-24
Device Type Code ....... : ..................................... 4-24
SN75110 Function Table ........................................ 4-37
SN751 071751 08 Function Table .................................. 4-37
"A" Cable Connectors .......................................... 4-40
liB" Cable Connectors .......................................... 4-40
Cable."...................................................... 4-40
"A" Cable Pin Assignment ...... , ................................ 4-41
"B" Cable Pin Assignment ....................................... 4-41
Seek Malfunctions ............................................. 4-80
Translation Between N RZ and 2-7 Codes ............................ 4-115
Write Compensation Truth Table .................................. 4-117
5-2-1
5-2-2
5-3-1
5-4-1
Error Status .................................................. 5-'
Fault Indicator Definition ....................................... 5-2
Fault Isolation List ............................................. 5-3
Symbol of Flow Chart .......................................... 5-6
6-3-1
6-6-1
6-6-2
6-6-3
6-6-4
6-6-5
6-6-6
6-6-8
6-6-9
6-6-10
6-6-11
Maintenance Tools and Equipment ................................ 6-1
KGFM Test Points ................................. : ........... 6-8
KGFM Check Terminals ............................~: ........... 6-9
KGFM Potentiometer Function ................................... 6-11
KGFM Switch Function ......................................... 6-11
CZOM Test Point .............................................. 6-14
CZOM Potentiometer Function ................................... 6-16
CZOM Switch Function ......................................... 6-16
XCGM Test Terminals and Test Points .............................. 6-18
XCGM Test Points ............................................. 6-19
XCGM Switch Function ......................................... 6-19
Adjustment after PCB Replacement ................................ 6-20
7-1
Spare Parts List ............................................... 7-'
8-3-1
TTL Interchangeability ......................................... 8-4
6-6~7
B03P-4760-0111A ... 01
xv
8-3-2
8-3-3
8·34
8-4-'
EeL Interchangeability ......................................... 8-6
Linear I C Interchangeability ...................................... 8-6
FUJITSU Proprietary IC List ..................................... 8-6
MB15238C Pin Assignment ...................................... 8-11
9·'
9·2
9·2
M2331K/M2333K Micro Disk Drive .... " ........ " ................ 9-2
Frame Unit (Basic) ............................................. 9.4
Frame Unit (Option) ........................................... 9-6
)
)
xvi
B03P-4760-0111A ... 01
)
Section 1
General Description
)
)
)
)
)
1. GENERAL DESCRIPTION
1.1 GENERAL DESCRIPTION
1.1.1 General Description
This manual describes the Fujitsu 8-inch rigid disk drives M2331/M2333. These
units contain non-removable disks in a sealed module. A rotary actuator using a
closed loop servo performs head positioning.
These drives have floppy disk drive dimensions and can be mounted horizontally
two drives wide in a 19-inch rack (with 3 pitch) or mounted vertically in a system
cabinet.
The contact start/stop (CSS) type heads and media are of the whitney technology
type. These units feature high performa.nce, high reliability and low cost.
The maximum unformatted storage capacities of theM2331 and M2333 units are
168MB and 337MB, respectively.
The M2331 and M2333 utilize the modified SMD interface, thereby allowing the
drives to be added to an existing disk configuration.
By standardizing on the SMD interface, development time for controllers and
software will be substantially reduced. Fixed sector format can be used with the
M2331 and M2333.
.
)
To power the drives only DC voltages of +24, +5 and -12 volts are required. This
allows for international use. Total nominal power consumption is less than 160
watts.
1.1.2 Features
(1) High reliability
(a) Whitney type technology contact-start/stop (CSS) heads and media are
used.
(b) Each head has an LSI circuit on its arm to amplify the small signal thereby
reducing read errors by increasing the signal to noise ratio.
(c) The heads, media and positioning mechanism are sealed in a closed·loop
air filtration system.
(d) The electrical components located within the sealed disk area are minimized.
(2) Maintainability
No scheduled maintenance is required.
The use of a completely sealed -DE, a belt-eliminating built-in DC spindle
motor, as well as highly reliable printed circuit assemblies, the necessity of
maintenance is greatly reduced.
(3) Compact, Lightweight
This unit can be mounted, two drives across in a standard 19-inch rack. The
dimensions are almost floppy disk drive compatible. The weight of the unit is
approximately 31 pounds (14 kg). Mounting equipment for the 19-inch rack
can be provided as an option.
(4) Vertical/horizontal Mount Capability
These units are available to horizontal-mount by setting the ON-SI DE switch
to OFF, and vertica.l mount by setting the ON-SIDE switch to ON.
(5) Lowaccoustical noise level and low vibration allow for installation in an
office environment.
(6) Uses only DC voltages. No internal changes are necessary for changes in
frequency or power.
\
)
B03P-4760-0111A ... 01
1·1
1.2 SPECIFICATIONS
1.2.1 Unit Specifications
The basic specifications of the disk drive are as follows:
Table '·2·1 Basie Specifications
Spseification
Storage capacity
M2331K
B03B-476S-B001A
168M bytes
M2333K
B03B-476S·B003A
337M bytes
Model
1 .2,2 Physical Specifications
Table '·2·2 Physical Specifications
Conditions
Item
Dimension
Specifications
Height
127mm IS.O")
Width
216mm 18.S")
Depth
380mm (15.0")
Operating
SoC to 4CfC (41°F to 104°F)
NOIl·operating
-4{fC to
Gradient
Less than:!: lSoC/hour
Operating
20% to 80% RH
Non·operating
S% to 95% RH (Non-condensation)
Weight·
14 kg {31 Ibsl
Temperature
Humidity
Vibration resistance
Operating
slfc
1-40"F to 140°FI
Less than O.2G (3 to 60
Hzl (2 minutes in both
ways x 30-cycle sine wave)
Non-operating
Less than 0.4G (3 to 60 Hz) (2 minutes in both
ways x 30-cycle sine wave)
Transporting and
Less than 1SG (10 msl (non-cyclic)
storing
Altitude
Operating
Less than 3,OOOm
Non·operating
Less than 12,000m (40,000 feet)
Dust
(10,000 feet)
Less than 0.168 mg/m 3 (Stearic acid standard)
• OPtional units are excluded.
1.2.3 Power Requirements
The M2331K and M2333K requires +5V, -12V and +24V DC voltages from an
optional power supply or system power supply. Each load current required by
the drive is shown in Table 1-2-3.
Table '-2-3 DC Power Requirement
DC Volt.\JII
Lo~
Curr.nt IIMAc)
Lo.d Current (With Du.1 Portl
+5V ±5%
4.5A
5.5A
-12V
± 5%
3.5A
4.SA
+24V
± 10%
4.0 Arms (Effective, typical)
7.7 Ao-p (Maximum)
S.S Arms (POW ON; Effective typical)
Note: The D. C. return lines must be made electrically common AT the Power Supply when usin!! other
then the optional Fujitsu Power Supply. Failure to commonize these lines will result in premature
failure of the spindle motor circuit.
'·2
B03P-4760·01 11A ... 01
)
The load currents of +5V DC and -12V DC will be stable regardless of operation being performed within the disk drive, however, the load current of +24V
DC will be varied during a power up sequence or DC motor acceleration and/or
seek operation.
The +24V DC load current profile during power up sequence is shown in Figure
1-2-1.
10
(A)
8
7.7 Ao-p max
(270 ms)
Ready
'i'I
6
4
2
5
10
15
20
25
30
35
40
(sec.)
Figure 1-2-1 +24V DC Load Current on Power Up Sequence
The +24 DC load current profile during the repeated acceleration/inertia modes
of DC motor and/or seek operation after Ready status is shown in Figure 1-2-2.
B03P-4760-0111 A ... 01
1-3
IA)
TI
TA
TA
4
TA
~
16,7 ms x M
TI=16,7msxN
3
M'N: Integral 11 - 4)
DC Motor
Load
Current
M>N
2
Inertia
Acceleration
Acceleration
Inertia
0
822 Track Seek
~
IA)
35 ms
3
Seek
Load
Current
2
35 ms
35 ms
(~ (~ (r\
I
!
0
~
IA)
7
)
6
5
Total
Load
Current
4
3
2
o~--------------------------------------------------
Figure '·2·2 Total +24V DC Load Current (Ready)
1-4
B03p·4760·0111A ... 01
1.2.4 Data Recording Specifications
Data recording specifications are presented in Ta.ble 1-2-4.
Table 1·2-4 Data Recording Specifications
Specifications
Item
M2331
Storage capacity (unformatted)
M2333
337,100,800 bytes
168,550,400 bytes
Number of cylinders
823
823
5
10
Tracks per cylinder
Cylinder capacity
204,800 bytes
Track capacity
409,600 bytes
40,960 bytes
Average rotational latency
Positioning time:
8.3 ms
Track to track
5 ms
Average
20 ms
Maximum
40 ms
Rotational speed
3,600 rpm ± 1%
Transfer fate
2.458 MB/sec
Encoding method
RLL(2/7)
Interface data
NRZ
Recording densitY
19,734 BPI
Track density
683 TPI
<501 <40 sec
Start/Stoptime
Interface
Modified SMD
Number of sectors
128 (maximum)
ms
40
30
Positioning
Time
~
V
20
10
I
/
/
/"
V
-----
-----
/'
o
100
200
300
400
500
600
700
800
Cylinder
Difference
Figure 1-2-3 Positioning Time Profile
B03p·4760-0111A ... 01
1-5
1.2.5 Reliability
(1) Mean Time between Failure (MTBF)
The MTBF is defined as follows:
MTBF ::
\
)
Estimated Operating Hours
Number of Equipment Failures
The. MTBF shall exceed 20,000 hours (design value). Estimated operating
hours should not include any maintenance time. Equipment failures means
any stoppage or substandard performance of the equipment because of equipment malfunction, excluding that caused by operator error, cable failure, or
other failure not due to the equipment. To establish a meaningful MTBF,
operating hours must be greater than 6,000 hours and shall include field
performance data from all field sites.
For the purpose of this specification, equipment failures are defined as those
failures necessitating repair or replacement on an unscheduled basis.
(2) Mean Time to Repair (MTTR)
.
The mean time to repair shall not exceed 0.5 hour. It is defined as the time
for an adequately trained and competent service technician to diagnose and
'correct a malfunction.
(3) Preventive Maintenance Time
No scheduled maintenance is required.
(4) Service Life
The M2331/M2333 drive is designed to provide a useful life of five (5) years
before factory overhaul or replacement is required.
(5) DC Power Loss
Data integrity is assured in the event of a power loss (data is not assured during write operation).
1 ,2.6 Data Integrity
The following error rates assume that the M23311M2333 is being operated within
specification. Errors caused by media defects or equipment failures are excluded.
(1) Read Errors
Prior to determination of a read error rate, the data shall have been verified as
written correctly and all media defects flagged.
a. Recoverable Error Rate
A recoverable read error is one which can be read correctly within fifteen
retries when reading on track, and should not exceed ten per 10 11 bits.
b. Unrecoverable Error Rate
An unrecoverable read error is one which cannot be read correctly within
sixteen retries and should not exceed ten per 10 14 bits.
(2) Positioning Error.Rate
The positioning error which can be corrected within one retry should not exceed
ten per 108 seeks.
(3) Media Defects
A media defect is defined as a repetitive read error that occurs on a properly
adjusted drive within specific operating conditions.
Valid data must not be written over known media defects, therefore, sector/
track deal location or skip displacement techniques must be utilized.
a. Media Defect Characteristics
(a) The maximum number of defects per drive is as follows:
M2331 K (168MB): 300
M2333K (337MB): 600
(b) The maximum number of defective tracks per drive is as follows:
M2331K (168MB): 16
M2333K (337MB): 32
'·6
B03p·4760·0111 A .. ,01
)
)
A defective track is defined as a track having any of the following:
1. Two or four defects.
2. Defective logging areas
Note: No track shall have more than four defects.
b. Media defect free areas are defined as follows:
1. Cylinder 0, Head 0 through 2
2. Any error in logging area to extent defined in the Media Defect Format
(4) Media Defect Information
All drive will have a Med ia "Defect Ust which will list the following information.
1. Cyljnder Address
2. Head Address
3. Position (bytes from Index ±1 byte)
4. Length (bits ± 1 bit)
The above information will be listed by hexadecimal code. The maximum media
defect length at a'defect is64 bytes (512 bits).
(5) Media Defect Format
The drive will be formatted at the factory with a standard Media Defect Format.
The format consists of one part. The format is a hard-sectored format and is
normally included in the first 56 bytes following Index signal, as shown in
Figure 1-2-4 Format 1. The format rules are as follows:
1. A track which has more than one defect is defined and flagged as a defective
track. The first four media defects are logged.
2. If the beginning of a defect is located between Byte 10 to Byte 55 (HA 1 j
after Index, 60 bytes of zeros are added to gap 1 (90 bytes total).
In this case, if any part of a defect is located between Byte 60 and Byte 115
(HAl), the track is flagged as defective. Refer to Figure 1-2-5 Format 2.
3. If the track is defined as a defective track according to above-mentioned
Rules 1 or 2, the high order bit of the first cylinder address byte is set to 1.
Remaining information mayor may not be valid.
)
\
)
B03P-4760-0111A ... Ol
'-7
00
r--------~·
10
"~~:ECTS
(
Index
Byte
HOME AOORESS
10
31 32
2930
ZEROS
33
CYL
SYNC
119191
34
HD
43 44
3940
35 36
47 48
1ST
2ND
3RD
ZERC6 f - - - - - - ~--- - - - - --pas LEN
pas
LEN pas LEN
51
121
(301
OJ
a
w
~
J;.
Gap 1
l
--...i
m
a
6
....
-
(21
111
12J
111
(21
t
(2)
(2)
121
121
5253 55
4TH
----
..
------
pas
LEN
(21
(21
16
Bytes
l
~~----I
TB ZEROS
(Fa)
16
111
(31
)Ga p 2
v
DATA FIELD
(23B)
I
High order bit of 1
indicates Detective Trade
»
a
-"
HARD SECTORED FORMAT
... -
.---------.--------------------.-------~---~~-----
(56BI
Note 11
Position (PaS) of defect is in bytes after Index
21
Length (LEN) of defect is in bits :t 1 bit.
31
Unused defect locations are all zeros.
:I: 1
byte.
Figure 1-2-4 Media Defect Format 1
~
~
'----'
Index
10
co
o
W
"'0
.j".
"
OJ
o
6
tr
10
2930
5253 55
ZEROS
DATA FIELD
(30)
(23)
/
///
DEFECT
/ /,
69
89 90
ZEROS
DATA
(90)
L
Format 2
Note 1.
If a defect is with in this area, the track is deemed a defective.
Figure 1-2-5 Skip Displaced Format
ill
FIELD
(23)
»
o
112·
Note 1
115
lEROSI
(3)
.I
1.3 CONFIGURATION
1.3.1 Fundamental Unit Configuration
Figure 1-3-1 shows the fundamental configuration of the unit; Figure 1-3-2 shows
the block diagram.
PCB !Interface Circuitsl
PCB IRtw.
S'~o
Disk Platter
CO""O' CI''''''\
\.
5.0" (127mml
)
Disk Enclosure (DE)
15.0" (380mml
Shock Mounts
PCB
(Spindle-molor
Control Circuits)
M2331 Three disks in DE
M2333 Six disks in DE
Figure '·3-1 Fundamental C~nfiguration
\
/
,., 0
B03P·4760·0111A ... 01
r-
,..-
Address
Register
-----------------~
I
Read/Write
Circuit
P"t I
Disk Enclosure
~
.to.
Y
Ii;
>
.to.
.~
CD
a:
--~
;§
r-"!"
Seek
Control
f-f-
r--
Read/Write
Control
0
U
CD
'" '"
.... ::I
I-
Servo
Control
u
co
't:
co
o
CAl
-u
--
c
m
o
6
VFO
~
....CD
DC Motor
Control
>
.~
o
-"
yo
.....,...
I
I
.
f--
I
L ___
I
1r
DC Motor
a:
--~
INX/SCT
Generator
ii
r-~
Speed
Detector
L--
L.....
LED
Switch
Start-up
Control
Fault
Detector
I--'--
Figure 1-3-2 Block Diagram
1
lPre-Am p
- - - - - - - - 1 - - - - - _.:...I.
1
CD
»
.to.
0 ....
u
a: <{
i
l!!
.i>.
-...J
...y
>0
........
PLO
I
gc
Y
....
Power
Amplifier
1.3.2 Options
Optional items are presented in Table 1·3·1.
)
Tabl. '·3·' Options
Itwm No.
Component name
SPeeific.tion
IDrawing No.1
Remarks
'·1
Fan unit
B038-4740·EOO2A
10011' S/1 20V AC; 50/60 Hz
1·2
Fan unit
8038-4740·EOO3A
220/240V AC; 60 Hz
1-3
Fan unit
8038-474D-EOOSA
+24VDC
2·1
Power supply unit
B14L·Sl0S-Ql00A
B14L-Sl05-0154A
#At
100/1tSI120/220/240V AC.
With connectors for feeding power to fan
units and dual channel printed board
unit.
3·1
Cable
B660-106S-TOO6A
Interface cable (A)
60P flat cable
3·2
Cable
B660-106S-TOO8A
Interface cable (BI
26P flat cable
3-3
Cable
B660·1865·TO:20A
Interface cable (AI for :2 units daisy chain
3-4
Cable
B660·1865·T030A
Interface cable (AI for 3 units daisy crUI;n
3-5
Cable
B6SD-1B6S·T04OA
Interface cable (A) for 4 units daisy chain
3~
Cable
B66D-1865-TOSOA
Interface cable (A) for 5 units daisy ehain
3-7
Cable
8660·186S·T060A
Interlace cable (A) for 6 daisy chain
3-£1
Cable
B660· t865·T070A
Interface cable (A) for 7 units daisy chain
3-9
Cable
B660·1865·T080A
Interface cable (A) for 8 units daisy chain
4·1
Panel unit
B03B4S90·E501A
Flat key type control panel board
S-l
Mounting tray
B21 L·181 0-0001 A
For mounting two units of 19·inch rack
with 3 pitches (inside frame)
S·2
Mounting tray
B21 L·1810-OO02A
For mounting two units of 19·inch rack
with 3 pitches (inside framel. and the front
panel has the windows for operating the
panel unit.
S·l
Dual Channel
B03B-4760-1:40.1 A
To be mounted on optional PSU.
6·2
Dual Channel
B038-4760·E402A
To be mounted on driw unit.
'-1
Power cable
B660.Q625·T327 A
Drive unit - power supply unit connecting
7·2
Powereable
8660·1995-T041A
Drive unit and DC (+24V) Fan unit-power
supply unit connecting Cable.
8·1
Cable
B660.Q62S·T328A
E002A fan unit connecting
power supply unit
8·2
Cable
B660.Q62S·T35SA
E003A fan unit connecting
9·1
Cable
BElSO·t99S·T003A
E501A panel unit -
10·1
Cable
B6S0-<>62S·T329A
Dual channel PCB assy. unit connecting
Note:
drive unit connecting
Power supply
Items in the above table ilIre optional and not fundamental components of this unit. These items
must be ordered separately conforming to the above specifications as occasion demands.
(1) Fan Unit
The M2331 K/M2333K requires some means of cooling, since there is no internal
blower motor. For this purpose, optional fan units are available in the event
that adequate cooling is not provided within the mounting cabinet. This fan
unit is directly mountable onto the rear of the device using the existing screws
and taps.
'·12
B03p·4760·0111A ... 01
)
The fan unit may be ordered in the following voltage ratings: 100/115/120V
AC or 220/240V AC or +24V DC. When the input power of the fan unit is
supplied from the optional power supply unit, the 100/115/120V AC (B0384740-E002A) fan unit should be specified regardless of system AC Voltage.
The DC fan unit (B03B-4740-E005A) may be used with the optional power
supply unit. In this case, order power cable specification: B660-1995-T041A.
The Table 1-3-2 shows the specifications of fan units.
The Figure 1-3-3 shows the mounting status, of the fan unit.
Table '-3-2 Specifications of fan units
B03B4740-EOO2A
B03B-4740-EOO3A
Rated voltage
AC l15V
AC 230V
Frequency
50/60 Hz
SO/60Hz
50 Hz
0.26A or less
(standard : 0.18A)
0.14A or less
(standard: O.OSA)
60 Hz
0.20A or less
(standard: 0.12Al
0.10A or less
(standard: 0.06A)
50 Hz
0.27A or less
0.15A or less
60 Hz
0.21 A or less
O.llA or less
27W or less
27W or less
14W or less
15W or less
Consumption
19W or less
Phase/Pole
Single/2P
Single/2P
Environmental
condition
Same as of unit
Same as left
Thermal alarm
Blow-value detecting
method alarm
-
Motor protection
Impedance protect
Same as left
Weight
1 kg or less
1 kg or less
Note:
-
0.72 A or less
Starting current
60 Hz
DC24V
0.5 A or less
Ready current
50 Hz
B03B-4740-EOOSA
Same as left
Blow-value detecting
method alarm
1 kg or less
Values 'of voltage and current show in case of no·load state.
B03P-4760-0111A ... 01
, -13
-\
.
.....
Connector
"""
Interface cable IAI
. Interface cable (BI
Use existing taps on the drive unit
Power cable
Finger guard
=::.::':".:1
c=--
(Drive unitl
M233X
OJ
o
.
W
"'0
...,j,.
0)
o
6.....
Screw holes
for securing
the unit
»
o
- ___ ~ __ J
380
50
I'll
C"21
Fan alarm
Pin No.
FG terminal (only AC Fanl
'1: The overall length alter mounting rhe fan unit is 430 mm
(380 mm + 50 mml_
'2: Fan alarm specification
Type of contact point: Normal open
Contact capacity:
O.SA DC max_
200V De max_
• However,' tAl x e 'VI < 10W DC
Consumption:
4.2W lat l00V ACor 24V-DCI
Responce time:
5 - 300 sec.
Circuit:
See Fi~ure 1-3-4
'--'
B03B-4740-E002A
• B03B-4740·E003A
100/115/120V AC
220/240V AC
2
100/t15/120V AC
3
FG
4
FG
2201240V AC
5
ALARM (-21
6
ALARM '"21
B03B-4740-E005A
+24V Return
+ 24V DC
ALARM "21
ALARM '·2)
Figure 1-3-3 Fan Unit
'-...-/
~
r-----------------------~O
-
.A
.~
(Heater)
-
I
I
I
------------
-I
Fan Alarm
I
I
I
I
Fan Motor
I
I
I
I
L
) Alarm
I
I
[ I/UV9VV
---_.1---- _.JI
Fan
-
) ACor DC Input
Figure '-3-4 Optional Fan Unit Alarm
(2) Power Supply Unit
A power supply unit may either be mounted horizontally behind the disk drive
or may be mounted vertically. Figure 1-3-S shows the details of 1/0 terminals
and the external dimensions of the power supply unit.
Specification: B 14L-S1 OS-01 OOA, B 14L-S1 OS-01S4A#A 1
240
230
-:3
CN31
)
C30
.----0
-6I
o
.0-
.s::
I
TRM2
-0
D
o
r---r--~
:+1 -
-If"
-~
.
LO
LO
N
N
I
o
TRM1
CN32
W
...1.-_ _
~o
gj,
c::
.s::
'"
U
0
~--~--j
0
£
.~
-0-
-0-
30
~
,
o
6
60
130
Air flow
Fan
Figure 1-3·S (a) Power Supply Unit: B14L·S10S-0100A
B03P·4760·01 11 A ... 01
1·15
240
~~~.____________~2~3~0~__________~
."j
0
u
• ...
CN31
dCN3~ 0
:!1
i:
0
TAM2
0
<.>
~
>
0
'"'c"
-=U'"
...
Gl
Cl
I
CN32
o
I.
96
.1
'30
..
' Air flow
-I....,,;.......
..
"•1
,
,. I
'."i,
-'+"
I
Fan
TRM1:
TRM2:
CN31:
AC power input and alarm sending.
FG-SG coupling terminal. (Normally open)
Drive unit power feeding connector
(wr cable B660-0625·T327A (Option))
CN32:
Device Alarm feeding connector
(for cable B660-OS25·T328A/T355A (Option))
CN33:
Dual channel PCB unit power feeding connector
(for cable B660-OS25·T329A (Option))
AC input voltage selection from 100/115/120V AC to 220/240V AC is connector selectable.
Safety:
IEC380, ULlCSA
Figure 1-3·5 (b) Power Sul'ply Unit: S14L-5105-o154A#A 1
)
'·16
B03P·4760·0111A ... 01
TRM1: AC power input and alarm sending.
TRM2: FG-SG coupling terminal. (Normally open)
CN31: Drive unit power feeding connector
(for cable B660-0625-T327 A (Option))
CN32: Fan unit power feeding connector
(for cable B660-0625-T328A!T355A (Option))
CN33: Dual channel PCB unit power feeding connector
(for cable B660-0625-T329A (Option))
AC input voltage selection from 100/115/120V AC to 220/240V AC is switch
selectable.
Regardless of AC input' voltage, AC output voltage from CN2 (AC fan unit
power supplying connector) is kept 115V ~~~~ AC.
Therefore when using the optional power supply only the 115V AC fan is required.
(3) Panel Unit
The panel unit includes function lights which indicate power on, ready, write
protect, check, and also includes a write protect switch and a check clear switch.
Figure 1-3-6 shows the mounting dimensions and mounting status of panel unit
B03B-4590-E501 A.
97
12
75
is
ON
~
co
I
.f-
~
PTCT
C'l
....
24
105
31
Connector
(Operator panel)
Figure 1-3-6 Panel Unit
B03P-4760-0111A ... 01
1-17
Protection cover
(Attached to
the panel unit)
Panel unit
mounting screws
Connection
cable
:0
00 o.
00
~~------,"",,-'..:u' ~"
-
------.,)-------------------------\
--
-'-~--/
\ Mountingotray
Panel unit
Figure 1·3·7 Mounting Dimensions of Panel Unit
)
)
1 18
0
B03P 4760·0111 Aoo. 01
0
\
I
(4) 19" Rack Mount Installation
A mounting-tray with brackets is available to install two drives, side by side in a
19" rack, three pitches. It can also accommodate the optional fan units and/or
power supply units for each of the two drives.
M232XK (two units)
Mounting tray
(optio.n)
Panel unit (option)
Figure 1-3-8 19" Rack Mount Installation
The mounting-tray (inner frame) guided by brackets (outer frame) can be drawn
out forward. (Travel distance is approximately 24'1.
The 19" rack mounting method is illustrated in Figure '·3·8, And Figure 1-3-9
shows the' appearance when the units are mounted using the mounting-tray and
brackets.
B03p·4 760-0111 A ... 01
1-19
450 - 450 mm
.,.0
l"
"
/
I
I
I
U.
-'"'
:
--
~-.
0
'"
-.J
--~
~_. _ _(_Fa~_~ __
,---
.c:
r
-
'""
,.....-
j-
0
<'00
I
;:;
'"
I
I
I
I
I
~
C..:..
::l_
I
ON
I
I
I
::!E1ll
upper primed \
....
I
OI-
,
.......
I
I
I
.:
E
E
I
I
I
=6
~"
(Drive unit)
,(The
'---
/
I
C?
(5
:
0
u........!
0
"§
-r-'"r--
I
I
:
;,
I
I
I
-.J
..J
I
I
I
;:
,
--.I
I
:
Power Supply unit
"
"
~
)
I
I;
N
--r
--
rr
.j
I
I
)
I
I
I
I
I
t
ttL':-- __ ~
I
I
I
I
I
I
.1
.J
1=
~!r
(Panel Yni!)
~
r-N
® ~-'-.' .-.-~
-_. __ ._--'- - -
j
/
/
/
~==~ I
l
I
1 ~=.J
®
821 L·1810-0002A
821 L·1810·QOO1A
482
Front Panel: A component of mounting·tray
Note: Mounting-tray (0001 A) cannot accommodate the drive unit with Panel unit. )n'that case, 0002-type
must be specified.
Figure 1-3-9 Mounting-Tray and Brackets
)
1-20
B03P-4760-0111 A ... 01
(5) Cables
The interface cable (A) may be up to 30 m long (to the· final unit in case of daisy
chain mode). The length of the cable can be specified in 20 inches (508 mm)
increments.
The interface cable (8) may be up to 15 m long. The length of this cable can be
specified in 500 mm increments.
The (A) cables for daisy-chain connection shown at items 3-3 to 3-9 in Table
1-3-1 are of the forms as shown in Figure 1-3-10. Cable length ilL" (specifiable
by "#L") refers to the corresponding sections of the following drawings:
· For 8660-1865-T020A
0 ~
0
I.
L
I
I
508
(A)
· For 8660-1865-T030A
0
0 0 0
I
I
L
I.
508
(A)
I
508
0
i
•
(8)
· For 8660-1865-T040A
0 0 0 ~
0
I.
I
L
508
(A)
I
I
508
(8)
508
I
i
(C)
· For 8660-l865-T080A
0 0 0 0 0 0 0 0
0
I.
•
I
L
.1.
508
IAI
.1.
508
(8)
.1
508
I
I
I
ICI
508
(01
.1
508
lEI
.1.
508
IF)
.1
I
508
•i
IGI
The connectors at both ends are of close-end. while the intermediate connectors are of through-end.
Figure ,·3-10 A·Cables for Daisy-Chain
B03P·4760·0111 A ... 01
1-21
How to specify cable lengths
(For 3.5m: Example 1)
B660-1065-T008A
#L3R503
Cable specification 3.5 x 103 (mm)
(For 50cm: Example 2)
B660-0625-T327A
Cable specification
#L500RO
500 x 10° (mm)
The lengths of cables at Items 7, 8, 9 and 10 in Table '-3-' must also be specified.
L
Power supply
Unit
Figure 1·3·11 Power Cable B660-0625·T327A
L
I"
I
70
)
Drive Unit
/
/,00
Fan Unit
(DC Fan)
-::::::!:r!oo:=-uJ
Figure '·3·12 Power Cable B660·1995·T041A
Figure '·3·13 Cable B660-062S-T328A, T355A
(Fan unit - Power supply unit)
'·22
B03p·4760·0111A ... 01
\
Power Supply
200 \
\
\
)
Figure 1·3·14 Cable B66()"0625-T329A
(Dual Channel PCB assy. - Power supply unit)
Figure 1-3·15 Cable B660·1995-T003A
(E501A Panel unit - Drive unit connecting)
)
The length of this cable can be specified in 60 mm increments (Minimum length
is 90 mm.)
Operator Panel Connection
The KGFM PCB allows for connection of an optional control panel. At location
B30 on this PCB, there is a 14 pin DIP socket for the control panel connection.
Following is pin-out for this DIP socket.
PIN NUMBER
SIGNAL MNEMON IC
DEFINITION
1
+5V
+5 Volt
2
*FPTK
File Protect Switch
3
*CKCLR
Check Clear Switch
4
*LROY
Ready LED
5
OV
Signal Ground
6
*LUSLD
Unit Selected LE 0
7
OV
Signal Ground
8
OV
Signal Ground
9
*PWRDY
Power Ready LED
10
*LFPT
File Protect LED
11
*LDVCK
Device Check LED
12
OV
Signal Ground
13
OV
Signal Ground
14
+5V
+5 Volt
"*,, Indicates a low active signal.
B03P-4760·0111A ... 01
'·23
(6) Dual Channel PCB Assembly
This unit can be provided with a dual channel option to add the crosscall function. Versions are available which permit the mounting of this option on the
unit or the power supply.
)
Drive's height is:
In case of mounting on the unit; 154 mm
In case of mounting on the'power supply;
It is possible to be mounted in the 19·inch rack with 3-pitch by using the
optional power supply (B14L-5105-0100A), the mounting-tray (B21L·1810·
0001A or 0002A).
The specifications and the rating of dual channel option are shown in Table
1-3-3.
Table '·3-3 Dual Channel Option
Specifications
B03B-4761).E401 A
B03B-4760-E402A
Mounting location
On the power supply
On the unit
Input condition
+5V,5.5A
-12V,4.5A
(! ncluding the basic drivel
Note: The dual channel option is connected with optional
(See Item 1.3.2.5)
pOW0F
supply by ysing the connecting cable.
Dimensions after mounting of Dual channel PCB Assembly are shown in Figure
1-3-16 (E401A) or Figure 1-3-17 (E402A).
)
~ Main Line Switch
~
Power Supply
operator panel
Power Supply
B14L·51 05-01 ODA
Note: In case of mounting on the power supply. fix Brackets with screws on the power supply,
Figure '-3-16 Dual Channel Option (E401A)
'·24
B03P-4760-01 1 1A ... 01
)
(Unit: mm)
Note: In case of mounting on the unit, change the usual unit cover to the cover tor this option.
Figure '·3·17 Dual Channel Option (E402A)
)
)
B03P-4760-01 11A ... 01
1-25
Connector location on the PCB are shown in Figure 1.3.18.
)
Power Supply 'CN33
n
KGFM-CN2
KGFM'S3
KGFM'S5
( 14P)
(14P)
•
(26P)
CN24
.
c!J;
KGFM'S4 (14P)
.
KGFM'S2 (14P)
..
dtJ
S3
o
J
\J{'t
I.
321
TAMlo:Il
TM2!THMI I}
.-J 2 !1
CN23
3 2 1 Ach-8
c:::c:::J TR M3
TRM
cable
OCHBRSV LEDOCHARSV LED
OCHBSLD. LEDOCHBSLD LED
CN21
CN22
11'
Bch-A cable
Insert Ach-,A cable
to KGFM-CNl
\
I
~
I
!
.
,
,,
,-f ,-fVl
\
,
.".
"'0
s:
s:
0
::iyy
z
ZO
Z
0-
0
:DVl
0
~
~
:D
(j
(j
:t>
CIlZ
:t>
:t>z
,m
,m
:r
z
:r
Z
Figure '-3-18 Dual Channel PCB Assembly Connector Location
'026
B03P-4760-0111A ... Ol
Bch-B cable
)
Section 2
Operation
)
)
)
2 •. OPERATION
2.1 GENERAL DESCRIPTION
Two M233X Micro Disk Drives can be horizontally mounted in a 19 inch rack with
optional mounting tray. The M233X may also be built into a system cabinet and
mounted horizontally, vertically. A mounting tray is available.
The KGFM Printed-Circuit-Board Assembly in the M233X Micro Disk Drive is equipped
with Maintenance Aid LED's and a File Protect switch.
Powering up/down and the functions of the internal indicators (LED) and switches will
be described in this section. The functions of the LED's and switches on the optional
operator panel will also be described.
2.2 POWERING UP/DOWN
The M233XMicro Disk Drive is not equipped with a power ON/OFF switch. Powering
up/down of the M233XK typically performed by powering up/down the system.
When the disk unit is equipped with an optional power supply, powering up/down may
be performed by turning the power switch ON and OFF at the power supply.
2.3 CONTROL AND INDICATORS
2.3.1 Operator Panel (option)
The functions of the LED's and switches or optional operator panel (front panel)
is described below.
)
\
(BB
B)
Fig. 2·3·' Operator Panel (Optional)
(1) Power indicator: Red
This LED lights when the power is turned on.
(2) Ready indicator: Red
This LED indicates that the initial seek has performed or indicates the termination ofa Seek or RTZ operation.
(3) Check indicator: Red
This LED indicates any fault condition.
(4) Protect indicator: Red
This LED indicates that writing is inhibited.
(5) Protect (PTCT) switch: White
This key inhibites the write operation.
(6) Check clear switch: Gray (flat key)
This key resets a Device Check status.
B03p·4760·0111 A ... 01
2·1
I .
2.3.2 PCB Assembly
The unit contains fault display indicators (LED's) as shown in Figure 2-3-2.
these are location on KGFM PCB.
~DY
FPT EMG
/0001
)
Figure 2-3-2 Fault Display Location on KG FM PCB
2-2
B03p-4 760-0111 A ... 01
(1) ROY (Ready) indicator: Green
This ROY LED indicated that the initial seek has been performed or indicates
the termination of a Seek or RTZ operation.
(2) FPT (File Protect) indicator: Orange
This LED indicates that writing is inhibited.
(3) EMG (Emergency Retract) indicator: Red
This LED indicates DC Motor Fault (DMFT) or VCM Heat (VCMHT) condition.
DMFT condition - - - This LED is blinks on and off
VCMHT condition
This LED is turned on
(4) STSl to 4, STTG1 and STTG2 (Status and Status Tag): Red
The two-bit binary coded Status Tag 1 and 2 LED's have the following conditions.
)
_0_-
Status
Tag 2
Status
Tag 1
Condition
0
0
0
0==1
0
1
Fault
1
0
Seek Error
1
1
Normal Status
Not Ready (Under the power-up sequence)
Not Ready (Power-up Sequence Check)
The Status Tag 00 has the highest priority and Status Tag 11 has the lowest
priority.
Status 1, 2 and 4 LE D's are defined by the above Status Tag LED's as shown
in Table 2-3-1.
Table 2-3-' Fault Indicator
Status Tag
Status Bit
Status
2
Not Ready
0
1
0
Not Ready
cowerup)
Sequence
Check
Code
(Hex)
Fault or Normal Status
4
2
1
0
0
0
00
State 0
Power-on Reset Sequence.
0
0
1
01
State 1
+24V Supply Sequence.
0
1
1
03
State 3
Auto-lock Release Sequence.
0
1
0
02
State 2
DC
1
1
0
060
State 6
Accelerate Complete Sequence.
1
1
1
07
State 7
Initial Seek Sequence.
1
0
1
05
State 5
Ready state but this state is not indicatedo
0
0
1
ox
State 1
Indicates the condition to power up is not
correct.
0
1
1
OX
State 3
Ind icates the actuator lock is not released.
0
1
0
OX
State 2
Indicates the rotational speed is not to 94%
(nominal) within the specified time.
1
1
0
OX
State 6
Indicates the accelertion mode is nofOterminated
within the specified time.
1
1
1
OX
State 7
Indicates the intial seek is not terminated within
the specified time or is terminated incompletely.
1
0
1
OX
State 5
Indicates an abnormal current flows to owinding
of VCM or DC motoT.
Designation
Condition
Mo~or
Accelerate SeqUence.
0
0
H
1
B03P-4760-01 11A ... 01
2-3
Table 2·3-' Fault Indicator {Continued)
Status Tag
---
Status Bit
Status
2
Fault
Seek
Error
Normal
Status
2-4
a
1
1
1
1
Code
(Hex)
Fault or Normal Status
Designation
Condition
4
2
1
0
0
1
09
Control
Check 1
Indicates II read/write command is issued during
a busy condition ..
a
1
0
OA
Control
Check :2
Indicates a write command is issued duri09 a
fault/check condition.
0
1
1
OB
Write
off-track
Indicates an off-track condition occurs during
write operation.
1
a
0
OC
Write
Unsafe
Indicates a write operation cannot be performed
due to a write circuit fault.
1
0
,
00
Write
Protected
Indicates a write command is issued during
File-protected status.
1
1
0
OE
Read/Write
Multi
Indicates multiple heads are selected during a
read or write o~ration.
1
1
1
OF
emergel'lI:V
Indicates over-load current flows on VCM or
DC Motor.
0
a
1
11
RTZ
Time-out
Indicates an RTZ operation is not terminated
within the specified time.
D
1
a
12
Seek
Time-out
Indicates a Seek operation is not terminated
within the specified time.
0
1
1
13
Over-shoot
Indicates the head Over-shoots the target
cylinder during settling time. or the head moves
out during track following sequence in linear
mode.
1
a-- a
14
Seek Guard
Band
Indicates the guard band is detected during
seek operation.
1
0
1
15
Linear Mode
Guard Band
Indicates the guard band is detected during
. linear mode.
1
1
a
16
RTZ Outer
Guard Band
Indicates the outer guard band is detected
during RT, operation.
1
1
1
17
Illegal
Cylinder
Indicates an illegal cylinder address (>822)
is issued by the controller.
0
0
1
19
Selected
Indicates the drive ;s selected by the controller.
0
1
a
lA
Tag 415
Enabled
Indicates the optional tag 4/5 function is
enabled by the kay on the driva.
1
a
a
lC
Hard Sector
Mode
Indicates the sector mode is set to Hard Sector
by the key on the drive.
0
1
B03P-4760-0111A ... 01
)
2.4 Dual Channel PCB Assembly (Option)
Dual channel PCB assembly is shown in Figure 2-4-1.
)
. KGFM'CN2
(26P)
Power SuppIY'CN33
KGFM'S3
KGFM'S5
(14P)
(14P)
•
CN24
KGFM'S4 (14P)
c!
KGFM'S2 (14P)
dtJ
)
3 21
TRMlo:::IJ
I I I}
TF?~l
TjM2!
3 2 1 Ach-B
C::::CTRM3
TRM
cable
OCHBRSV. LEDOCHARSV LED
OCHBSLD. LEDOCHBSLD LED
CN21
CN22
'0
,
Bch-A cable
."
,....
-I
~
'I nsert Ach-A cable
to KGFM'CNl
0
2
\
\
,
,
., ,,.
"'0
;
--Itn
s:
0
20
2
0-
0
:otn
Bch-B cable
:0
~
~
::iyy
n
:r
:l>
CO2
2
m
;-
n
:r
:l>~
2
m
;-
Figure 2-4-1 Dual Channel PCB Assembly
(1) CHASLD LED (green)
Indicates that this unit is Selected by the Channel-A controller ..
(2) CHARSV LED (orange)
Indicates that this unit is Reserved by the Channel-A controller.
(3) CHBSLD LED (green)
Indicates that this unit is Selected by the Channel-B controller.
(4) CHBRSV LED (orange)
Indicates that this unit is Reserved by the Channel-B controller.
B03P-4760-0111A ... Ol
2-5
(5) CH-A Switch
DIS (Disable A):
Disconnects the unit from the Channel-A controller and disables it from sending and recieving all interface signals.
NORM (Normal A): Connects the unit to the Channel-A controller and enables it
to send and receive interface signals.
(6) CH-B Switch
DIS (Disable Bl:
Disconnects the unit from the Channel-S controller and disables it to send and receive all interface signals.
NORM (Normal B): Connects the unit to the Channel-B controller and enables it to
send and receive interface signals.
(7) R L TM Switch
RLTM ON:
When in "Release Timer On", Reserved and Priority Select are
released 500 ms (nominal) after the unit is deselected.
Note: Reserved and Priority Select can also be reteased by
the Release Command (TAG 3, BUS 9).
RLTM OFF:
When in "Release Timer Off", the. Reserved condition is
released from the controller by the Release Command (TAG 3,
BUS 9).
2.5 POWER SUPPLY
The optional power supply can be provided with the M233XK. The front viedw of the
power supply is shown in Figure 2-5-1.
2.5.1 Main Line Switch
This switch controls application of site AC power to the power supply. Turning
on the switch applies power to an optional fan unit and DC Power to the disk
ttrive.
J
2.5.2 Indicators (LEOs)
(1) Power On LED
The Power On LED indicates that AC input is applied to the power supply.
(2) Power Alarm LE D
The power alarm indicates the following malfunction has occurred on the power
supply:
• +5 VDC: Over-current, Over-voltage and Non-voltage
· -12 V DC: Over-current and Non-yoltage
• +24 VDC: Over-current and Non-yoltage
· Over heat within the power supply
)
2.5.3 Device Alarm
.
The Device Alarm indicates that the thermal switch has be closed on the optional
fan.
PSU: S14L·5105-0100A
PO~EH
FUSE
o
o
POWER
ALM
o
DEVICE
ALM
FG
o
3
r[j)
ALM
5
~
r:;.,
-&
MAIN LINE
SWITCH
~7.5A
INPUT VOl. TAGE FG
SELECT
II
0
II
SG
TRM2
.2
3
AC1COV t>C220vl@
ACl15V AC2I¥JV
t>Cl20V
Figure 2-5-1 Front View of Power Supply
2·6
B03P·4760-0111A ... Ol
+~~0mo
- ov
0
-12V 0
®I ~~glKO
+5V VOLT ADJ
)
PSU: B14L-5105-0154#A1
)
AC100V
ACl15V
ACl20V
TRM1
®
IN
puT
3
r-
ALM
O~
POWER
~TVOLTAGE
~ELECT
AC [
FG
POWER
sll ll·
sW1
MAIN LINE
SWITCH
7.5A
0
I
FG
ALM
DE~ICE
ALM
o
G
S2
AC220V®
AC240V.
+24V
+5V
TRM2
3
- OV
®I
rn
-12V
VOLT
CHECK
0
0
0
0
+5V VOLT ADJ
Figure 2·5·1 Front view of Power Supply Unit· continued
)
B03P-4760-0111A ... Ol
2-7
)
)
)
Section 3
Installation
)
)
3.
INSTALLATION
3.1 GENERAL DESCRIPTION
This section describes unpacking, installation, and cabling of the\M233XK when shipped
separately, and shipping precautions when the unit is delivered as a system.
3.2 UNPACKING
The M233XK is wrapped in a polyethylene bag, surrounded by cushions, and packed in
a carton. An exterior view of the carton is shown in Figure. 3-2-1.
(1) Store and open the carton on a flat surface. Ensure that the top of the box, indicated by a ''This Side Up" signs, is oriented correctly, and take out options.
Note: Don't store on the disk drive in the upside-down position.
(2) Take out the top cushion.
(3) Pull the M233XK out of the box by grasping its base.
Move the unit slowly and carefully, to prevent unnecessary shock.
(4) Store packing material for possible future use.
Note: When the difference in the storage (or shipping) environment and the unpacking environment exceeds 20°C (36°F), the carton should be allowed to .
stand at the unpacking site for more than 3 hours prior to unpacking to avoid
condensation.
Caution: When unpacking, don't place the M233XK on a bare floor directly to
avoid handling damage due to shocks. Place it on a suitable cushioning
material.
3.3 VISUAL INSPECTION
)
After unpacking, check the following.
(1) There shou Id be no cracks, rust or other damage that mars appearance and integrity.
(2) All parts should be firmly fixed, there should be no loose screws, etc.
(3) The attachments and options should be as ordered.
3.4 INSTALLATION
This unit may be mounted in a 19-inch rack or built into a system cabinet.
If mounting the M233XK in a standard 19-inch rack, the mounting tray and its brackets
are provided (as options). When the M233XK is built into a system cabinet, it can be
mounted horizontally, vertically or on-end. (Refer to Figure 3-4-1.)
·3.4.1 Mounting Dimensions
Figure 3-4-2 shows theM233XK dimensions and the structure of its frame.
B03p·4 760-0111 A ... 01
3·1
Space for OPtions and/or Accessaries
(ExcePt B-Cable)
(I n Case Fan Unit
Is Attached)
Unit Is Not
Attached)
L
Spa~er
)
!ib'-"::'~~+-
B cable
Figure 3·2·' External View of Carton
)
3-2
B03P-4760·01 11 A ... 01
(Up)
Printed Chrcult Boards
If
=:
,
=:.
.
:
.1... .
-. =
.=
r'~
~'~
~~
I~
(DE)
~.
~I
I~
(Base)
(Down)
(a)
HORIZONTAL MOUNTING
(Up)
(
~~
,)
D
"0
c:
w
c:
'"
u..
DO
(Down)
(b)
VERTICAL MOUNTING
NOTE:
This drive maybe mounted in the following orientations only:
,.
Horizontally (a)
peA boards up.
2.
Vertically (b)
On the left side of the unit as viewed from
the fan end of the drive.
Any position other than these is not acceptable and may cause unreliable
drive operation.
Figure 3·4·' Mounting direction
B03P·4760·0111A ... 01
3·3
Rubber sh'ock-isolator
(M4 PO.7 screw hole for fining),
216
\
,\
in
ffi]
~
'"
.§
:;
'"
OJ
.~
J;
>
'0
'"
.~
"
iii
'0
:5
.§'"
Qj
,I
VI
,I
70
E
'"
'0
C5
0
~
.~
0
CO
:
("l
'5
i:
U
"
~
'"
UJ
Q
'0
~
2i
.s:::;
'0
'"
'0
'ii!
'"
l!!
'0
c
.S
::>
tt
.§'"
~
70
.:::
,.
Q;
"0
c
'C" 0
'0
'"
"0
.;;;
Q;
'0
C
::I
(80)
=.,====-, '-====!====- ==....."'..-=====a
,...
(DE)
f777?'/;?'7i'7
N
Note:
200
0
Sections enclosed in
refer
to the dimensions of the setting frame which
can be adapted to width 210mm (Setting pitch).
I
(Dimensions are in millimeters)
Figure 34·2 Mounting Dimensions of the Unit
. B03P·4 760-0111 A ... 01
)
3.4.2 Service Area
Maintenance, securing for transportation, cable connection, are accessed as shown
below.
When determining the service area and where to install the locker, make sure that
there is enough room for maintenance work.
R
KGFM (Controller F)
CZOM (Controller 0)
)
P side: Maintenance operation on PCB (KGFM. CZOM)
Q side: Maintenance operation on PCB (TVQM)
Cab Ie connections
Securing the unit, (Refer to 3.4.4)
R side: Securing the unit, (Refer to 3.4,4)
Operating the panel unit (Optional!
Figure 34·3 Maintenance Access on the Unit
B03P-4 760-0111 A ... 01
3-5
3.4.3 Securing the Unit
.
When installing the unit, it is important that it does not touch any other hard
parts such as mounting plate when operating as well as non-operating (both
storage and shipping).
For this purpose, the unit is provided with screw hO.les on Q side and 5 side
(refer to Figure 3~4-3).
The holes are used to secure the unit to the mounting frame during shipment.
Examples of securing the unit are shown in Figure 3-4-4 and Figure 3-4-5.
Screw (M4)
:for Rubber Mounts
----------------:::7~~nrrTr"E§:=;:::tr- Elastic Material such
as Rubber
)
Mounting frame
M4 Screw (x 4) to be used
when transporting
Figure 3-4-4 Securing the Unit (Example 1)
)
3·6
B03P·4760·01 1 1A ... 01
Mounting frame
Rubber shock isolator
)
Elastic material
such as Proof Rubber
Drive unit
2.5 mm*
* Maintain this gap so there is no contact with the drive unit in case of shock or vibration.
Figure 3-4-5 Securing the Unit (Example 2)
B03P-4760-0111A .... 01
3-7
A more effectjve use of these holes is to attach some elastic materials as stoppers.
The stopper acts as a shock absorber, keeping a suitable clearance. The stopper
protects not only the device but also rubber shock isolators from damage. Figure
3-4-6 shows recommended form of the stopper. This stopper is effective when
operating as well as non-operating, and it is unnecessary to remove after shipping.
The screw hole dimensions on the unit are shown in Figure 3-4-7.
Example of "Stopper"
)
11.5)
Figure 3-4-6 Form of the Stopper
B03P-4760-0111A ... Ol
~
(1) R side
I
II
~ :IT
T
1r
'1
~
I
II>-
.r--
~
{ ~
0
Revision label
o
@
t
Manufacturing label
'X
~
co
;--
g
19
3-+-
\
6)
1\
"l
1-M4 PO. 7
180
(2) Q side
II
T-
......,
,J.
r-
I
K~
II
I
1..--
W
.-'
!~ 9-
I
\
I
I
\
I
TVQM PCA (Power amp.)
I
2-M4 PO. 7
180
(3) Q side
0
(with Fan Unit)
Pitch
A-B.
380mm
A-C
415mm
(2)
B
.--- ~~
==
'---
1J
t1~
I
--+--
{;:......,
~
I
.-
-
,,
0
0
I
i
',,-
-
\
2·M4 PO 7
188
\
Figure 3-4·7 Dimensions of the Screw Holes
B03P-4760-0111 A ... 01
3-9
3.4.4 Cooling·
This unit requires some means of cooling, since there is no internal blower motor.
Figure 3·4·8 shows the recommended air flow posture.
TVQM PCB
-..,-....----t---~,..---------1
==::;:,
,
c::::::
----'
I
1------""\..-r---.J----
VCM
SP. DC Motor
Figure 3-4-8 Recommended Air Flow Posture
.. For this purpose, an optional fan unit is available. This fan unit will removes
the generated heat most effectively. (Refer to 1.3.2.1)
The cooling condition can be confirmed by taking the surface· temperature of
some ICs and heat sinks.
The following IC's surface temperature must be kept under the temperature listed
on the Table 3-4-1.
Table 3-4-1 Thermal Check Point
Part No.
M189
On Board
KGFM PCB
Maximum surface
Temperature (Tcl
..
85°C
M10
M59
CZOM PCB
85°C
..
85°C
Q46
04
TVQM PCB
80·C
DE
65°C
Alminum base
(Bottom side)
•
Random seeking
•
Even on max. environment temperature (40°C)
Note:
85°C
Please refer to section 10 for check point location.
Figure 3-4·9 shows some examples of cooling installation.
3-10
B03P-4760-0111A ... 01
)
(a) Using optional fan unit
~
Cabinet
I;:;
~I
&
-----Drive
~
.----D-rlv-e--'"'TI-Z-,I
-.:::
IR~'Sld"
=,
•
Warmed air must be exhausted
directly out of the cabinet.
(b) Without optional fan unit
We recommend that the installation frame is shaped like a duct and the
cooling air flow path as follows:
E
E
a
E
E
~
N
E
E
E
E
E
a
E
co
co
a
=-
'
c:co •
..
-~
'c
>"'U
0 - Q.)
...
'" ¢~
a;£
U§~
"'0'"
.~ E g
U
CU
c:
c:
cuo-
e~:E
0.._..-
:::l
C
III
..
CI>
.c
CIl
c
.;:
C
::I
0
:IE
...
'>o"
U
-0
-0
J:
B03P·4760·0111A ... 01
3-13
3.5.2 Mounting the Panel Unit
Figure 3~S·2 shows panel unit mounting diagrams.
,
~'-
Bending (with forming pad)
I
I
I
CN2
Prevent slackening
PC board KGFM (top view)
Flear view of the panel unit
CNl
IC socket (51)
)
Note: To prevent the connection cable from sJ~kening under the panel unit or on the equipment Ot pIPe
board) • bend the cable at the rear of the panel un it as shown in the figure above.
Figure 3·5-2 Mounting the Panel Unit
3·14
B03P·4760·0111A ... Ol
3;5.3 Installation Mounting Tray
Two disk drive units can be installed. side by side, in 3 pitches (131 mm) of height,
in"a 19-inch rack using the optional mounting tray as shown in Figure 3-5-3.
M232XK
(Two side by side)
r--3 pitches
(131 mm)
r-;;;;:=======J
~
)
Mounting Tray
(optional)
Panel unit
(OPtional)
Note:
Refer to Section 1-3-24"
Figure 3-5-3 Installation in the 19-inch Rack
(1) Installation Mounting Tray in the 19-inch Rack
First, mount the bracket assembly on the 19 inch rack as follows. The bracket
assembly consists of a pair of right and left slide guides (outer rails).
Loosen 3 screws which hold the bracket in the back, so that it moves back
and forth. (See Figure 3-5-4.)
The installation frame can be mounted in the 19 inch rack with a depth of
mounting pitch ranging from 531 mm to 777 mm by adjusting the brackets.
When mounting the installation frame in the rack with a depth of 622 mm to
777 mm, secure the brackets as shown in Figure 3-5-4 (a).
For racks other than the above, secure the brakets as shown in Figure 3-5-4,
(b). The brackets are symmetrical, so a pair can be used for either (a) or (b).
(6) Remove tapped plates and hold them on the 19-inch rack post as shown in
Figure 3-5-5, (a).
@ Install left and right outer rails (bracket assembly) in the 19-inch rack.
Tighten the bracket mounting screws after adjusting bracket location to fit it
to the depth of the mounting pitch_ (See Figure 3-5-5, (b).)
"
CD
B03P-4760-0111A ... 01
3·15
®
Mount the outer rails using tapped plates with the bracket U-slots (in the
back and front) pressed against the tapped plate fixing screws. (See Figure
3-5-5, (c).)
Three bracket
mounting screws
Bracket
=+==:===
c:=::=======r:(S):::i:::t::::===
C::========:(~):::I
------~-------~
(a)
622 to 777
Bracket
r - -- - -
==::::r'=:JI-D,
4'
- -
-
- -
- -
-
---"
:
C
c:=::==~cti
I
--:i-
__ LL
~
C:::::::!,:::J(V
L ______
)
--r!
~
) _:-:I'II
__ - - _ _ - - -
-,-,-
(b)
u
Unit: mm
Note: The above figure ((a) and (b)) shows only the right slide guide (see from the frontl. The brackets in
(a) and (b) are symmetrical to each other.
Figure 3-5-4 Bracket Assembly
3-16
B03P-4760-0111A ... Ol
Bracket (j n proper
(location)
)
Bracket
mounting screw
Post
(19-inch racie)
)
(b)
(a)
Tighten the tapped plate
fixing screws with the
bracket U-slots pressed
against the screws.
(c)
Figure 3-5-5 Bracket Assembly Mounting on the 19-inch Rack
B03P-4760-0111A ... 01
3-17
@ Insert the mounting tray Hnner ram and check its movement. If it does
®
OJ
not slide freely, loosen the tapped plate holding screws and adjust outer rail
locations for their relative width.
Confirm that the inner .rail stops against the stopper when it is pulled out.
(The installation frame can be pulled out approximately 595 mm.)
Insert the mounting tray and fix it to the outer rails at the front left and
right. (See Figure 3-5-6).
Mount the front panel.
Fixing screw
..
Front panel is not
snown
Mounting Tray
(Inner rail)
)
Bracket assemblv
(Outer rail)
Figure 3-5-6 Mounting Tray to the Outer Rails
(2) Each Unit Installation on the Mounting Tray
a. Fan unit installation
Disk drive units installed on the Mounting Tray must have a fan unit. Refer
to Section 3.5.1.
b. Disk drive unit (with fan) installation
Mount the rubber stoppers, attached to the Mounting Tray, using taps
in the front and back of the drive unit as shown in Figure 3-5-7.
CD
)
3·18
B03P-4760·0111 A ... 01
Rubber Cushion
Manufacturin
Label
Revision
Label
(Front of The Drive Unit, Nameplate Side)
01===='
Rubber Stopper
' - - -.....v.------./
A ttaChed to the
installation frame
+
x
(Rear of The Drive
Unit, Fan Unit Side)
Rubber Cushion
Figure 3-5·7 Rubber Cushion Mounting
~ Attach the mounting brackets using taps (M4) for shock absorbing
@
@
mounts after setting the mounting brackets to disk drive unit location.
Note that the front and back brackets are different. Refer to Figure
3:5-8.
Remove the cushion stoppers from the Mounting Tray. (4 per installation frame (See Figure 3-5-9.)
Set the disk drive on the Mounting Tray. The disk drive unit can
temporarily ride on the front and back beams of the installation frame
(inner rail) without manual support using the mounting brackets and 4
cushion supports in the front and back. (See Figure 3-5-10.) Therefore,
even one person can install the drive unit on the Mounting Tray either
rem oved or on the rack (pu lied-out) .
In this state, attach each shock absorbing mount (For the inside shock
absorbing mount section, attach the mounting brackets already attached
on the shock absorb ing mounts.) See Figure 3-5-10.
B03P-4760-0111A ... Ol
3·19
\
Mounting
bracket
~J~;;;~~~~~~G~;~~~7
.
•
J
Mounting bracket
The figure below shows
mounting of the brackets
Shown have in black.
o
0
)
Flat head screw
(attached I
Shock absorbing
m!lunt
Mounting bracket
Mount ing bracket
(a) Mounting in the front of the
drive unit
(bl Mounting in the back of the
drive unit
Figure 3·5·8 Bracket Mouming
)
3·20
. B03P-4760·011 1A ... 01
'-=----'
Stopper support
Cushion (fixed 10
the drive unit)
CD
o
w
Mounting bracket screws
-+
.;,.
"
-..J
Front panel
mounting taps
(at left and
right)
OJ
o
-~+
6
l>
a
The Stopper cylindrical
section rides on here_o_ _ _ _ _ _ _ _ _J
(I n temporary
setting state)
m
3
2.
-$-$
Adjust the stopper support
location until uniform clearance
is obtained.
* The figure shows the right drive unit (seen from the front). The stopper supports of the left drive unit and .the back (fan sidel are the same.
Figure 3-5-9 Cushion Support
w
N
Attach the
mounting bracket
r
I
I
l-
Mounting the
front panel
!}
.n.
.!l..II.
Attach the
mounting brackets
I
~---~
3-22
[]1=:-
B03P·4760·0111A ... 01
-=0
I
~
@ Mount the Stopper supports that were removed in procedure
c.
(e), so that
clearances around the stopper including those in its front and back are
1.5 mm. See Figure 3-5-9.
@ If the panel unit is required, mount it. See Item (3).
(J) Mount the front panel.
Mounting the panel unit
The panel unit (optional) is mounted as shown in Section 3.5.2. When the
panel unit is used in the Mounting Tray, mount it as shown in the following figure.
When the panel unit is mounted, use the Mounting Tray (B030-1S10-0001A)
as the inner rail. (Refer to Section 1.3.2.4.) This type of Mounting Tray has
a blank panel on one side. When installing 2 drive units, this blank panel is
not used. When installing 1 drive unit, mount this blank panel in the unused
window.
Notes: 1. The protection cover on the installation frame edge protects
cables from damage. Mount it together with the panel unit as
shown in the following figure.
2. For cable forming, see Figure 3-5-2.
Protection cover
(Attached to
the panel unitl
Panel unit
mounting screws
@
O
00
i
@
00
Connection
cable
D
I@O
@
Panel unit
Figure
3-5-1'
Mounting the Panel Unit
d. Power supply unit installation
The power supply 'unit is mounted at the back of the Mounting Tray (inner
rail) using 4 screws. Even after the inner rail is mounted on the 19-inch rack,
the power supply unit can be installed if sufficient space is left.
B03P-4760-0111A .... 01
3·23
Power supply unit mounting screw
(Attached to the power supply unit)
.- 1I
.-
- -
/ --
-
-
-
----
- - - --- - -- ---
l,c
-
I~
:
I
I
f-
I
'-==
I
I
I
=--..,
,.,, II
I
,
I
I
\
\
Output
connector side
(Cooling fan)
I
\1
•,
I,
I
I
,
I
\
,I
(
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
'. .II
____
Operation and
maintenance
panel side
I
I
I
I
I
I
I
l-
F
I
F"
I
I
t-
VX'
"-
I
I
V)('
I
I
I
Dual channel OPtion
installation side
Power
suppty unit
I
I
,....
~
/V
---.,.
..
I
I
,
'
}'
,I''
I \
I
I
\
\
I
'-
,I
I
I
-- t--M
I
I
I
I
ounting Tray
(I nner rail)
I
I
I
F"--_..1
w...
,-h
..-
)
I
Note:
Refer to Section 1.3.2.5 for optimum cable lengths when the oPtional power supply unit
is installed.
Figure 3-5-12 Power Supply Unit Installation
e.
Dual channel option installation
The dual channel option can be mounted on the power supply unit. (Tap
locations for mounting are shown in Figure 1-3-5.)
Mount the bracket (2a) on the rail (1a) using screws SBD M3x5. The
left and right brackets and rails are symmetrically mounted.
@ Mount the spring (3a) on the rail (1a) using screws SBD M2x5. The left
and right brackets and rails are symmetrically mounted.
~ Mount the rails (1a) on the power supply unit using screws SSA M4x8.
@ Mount the guide (4a) at the back (operating section) of the power supply
unit using screws SBD M4x8.
® Mount the dual channel PC board on the frame (6a) using screws SBD
M3x5. (See Figure 3-5-14.)
CD
3-24
B03p·4760·0111A ... Ol
V
Bracket 12al
Ii
j
!
Rail11al
I
VI
!
Guide 14al
Figure 3·5·13 Dual Channel Option Installation 1
)
?
I
i
I
Frame 16al
Figure 3-5-14 Dual Channel Option Installation 2
B03P-4 760-0111 A ... 01
3-25
® Pressing PC board unit (PC board imd frame assembly) (12a) downward,
insert it until the springs deflect slightly. The PC board unit frame is
automatically latched at lugs of the brackets (2a) and locked. (See
Figure 3-5-15.)
)
Bracket
(2a)
Figure 3-5-15 Dual Channel Frame Mount
(2) Connect
CN25 on the PC board and CN33 on the power supply unit
with the connection cable (B660-0625-T329A). (See Figure 3-5-16.)
Connect interface cables (8a and 9a) between the drive unit (CZFM) and
the dual channel PC board.
Connect the A-channel cable B to the PC board, a.nd pull the cable out
behind. the power supply unit.
@ Remove the dual channel PC board from the rails and connect the
A-channel cable A to the drive unit (CZFM), and pull the ~able out
under the dual channel PC board and behind the power supply unit.
@Connect B-channel cables A and B to the back of the PC board (CN21
and CN22) and pull them out behind the power supply unit.
®
®
CZFM
r+-..I......I.I..--___--,
)
A-channel
....,..._.,..-.,,-_ _ _ _ _~ cable B
A·channel
cable A
Figure 3-5-16 Dual Channel C;sbling
)
3·26
B03p·4 760-0111 A.: .01
@ Attach the cover (11a) on the frame (6a) using screws S8D M3x5.
(11al
f6a1
Figure 3-5-17 Dual Channel Top Cover Fixing
@ Form the A- and 8-channel interface cables along the guide (4a) and hold
them with the cable retainer (13a).
.
I...-_-.,.._........_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--,._-,.-_...J..........
A-channel cable A
Guide (4al
B-channel
cable B
A-channel
cable B
I
)
I
Cable retainer
( 13al
~
B-channel cable A
Figure 3-5-18 Dual Channel Interface Cables Holding
* Part number of the dual channel option is 8038-4 760-E401 A.
B03P·4760·0111A ... 01
3-27
3.5.4 Mounting the Dual Channel Option
The procedure for mounting the dual channel option on the power supply (procedure B03B-4760-E401 A) was previously described in Subsection 3.5.3.2. This
subscription describes the procedure for mounting the option on the drive unit
(procedure B03B-4760-E402Al.
Mount the dual channel PCB on frame as shown in Figure 3·5·14.
@ Connect the drive unit (KGFM) to the PC board via the cable as shown in
Figure 3-5-16.
~ Insert cover between frame and the equipment from the front of the equipment, and fix cover.
@ Fix the frame with PCB with two screws (SBD M3 x 5).
@ Connect A-channel cable B (CN23).
® Attach cover 3b in the frame and fix with screw (SBD M4 x 6).
(J) Connect all other interface cable to channels A and B.
@ When mounting the optional fan unit to the drive unit, fix the interface cable
with the attached cable clamp.
CD
)
3·28
B03p·4760·0111 A ... 01
I
t
PCB
Cover
Figure 3-5-19 Mounting the Dual Channel Option
B03P-4760-0111A ... Ol
3·29
3.S CABLING
3.6.1 Connectors On Unit Side
Figure 3·6·1 shows the mounting positions of the interface connectors on the
drive side.
I nterface cable A (60Pl
(Rear of drive)
CN10
Figure 3-6-1 Mounting Positions of Connectors
Cables include an interface (A) cable SOP, an interface (B) cable 26P, and a power
cable.
Refer to Section 3.6.2 for additional information on the power cable.
3.6.2 Power Cable Connection
The M233XK uses only DC power, Connector specification for the unit, recom·
mended specifications for the cable, and pin assignment and voltages follows.
(1) Specification on the unit side
Header C63L-OB20-000B (2420-07 A-G manufactured by Molex Japan Co.,'
Ltd.)
(7P) x 2 pieces
(2) Recommended specifications on the cable side
Housing C63L-0820-0007 (2139-7 manufactured by Molex Japan Co., Ltd.)
(7P) x 2 pieces
Contact C63L-0820-0002 (2478-G L manufactured by Molex Japan Co.,
Ltd.)
(12 pieces)
Key C63L-0820·0001 (2560-1 manufactured by Molex Japan Co., Ltd.)
(2 pieces)
3·30
803P·4760·0111A ... Ol
(3) Pin assignment and voltages
Refer.to Figure 3-6-2.
)
01
07
07
/
/
To CN10
To CN9
(CN10)
(CN9)
1
OV
(-12 V RTN)
2
(Key)
3
4
OV
(-12 V RTN)
1
+5V
2
+5V
3
OV
(+24 V RTN)
-12V
4
ov
(+24 V RTN)
5
-12 V
5
+24 V
6
OV
(+5V RTN)
6
(Key)
7
OV
(+5 V RTN)
7
+24 V
Note: 1
2
3
Use AWG18 as the cable material.
The cable length must be less than 1.5m.
All "OV" must be connected together at power supply outputs.
Figure 3-6-2 Pin Assignment and Voltages
)
If the power supply (option: B14L-S10S-0100A or B14L-S10S-01S4#A1) is used,
the following power cable is provided. (refer to Figure 3-6-3)
Specification: B660-062S-T327 A or
B660-199S-T041A (with DC Fan Unit)
Specify the length of the power cable as follows [for 50 em (example)] :
B660-062S-T327 A
#LSOORO
Cable specification
500 x 10° (mm)
L
Power supply
Unit
Figure 3-S-3 Power Cable (Specification: BSS()'OS25-T327A)
B03P·4760-0111 A ... 01
3-31
3,6.3 Interface Cabling
Interface cables include cable (A) (60P) for control signals and cable (8) (26P) for
data signals.
(1) Cabling
Cables are connected with the system in the star (radial) mode or the daisychain mode, as shown in Figure 3·64. For the star mode, the line terminator
for cable (A) is necessary for every device. For the daisy chain mode only
the last device requires a line terminator.
The unit side of cables (A) and (B) use right angled connectors which have no
mal insertion preventive keys. Insert the cable to match the triangular marks
on the connectors, (at the number one) shown in Figure 3-6-5. Then lock
them from both sides with the locking lever.
If an optional fan unit is used, fix cables (AI an'd (8) at the upper section of
the fan unit, (as shown in Figure 3-5-18) using the fan cover/strain relief.
Con trol unit I
AO
A
BO
I C~
~
Al
A
I I
B1
A2
8
r-~
'/////A
MOO
~
8
LBr-
I I
A
A
1 r:~
M~
.:---
#2
B
B7
I'//~
,/.
A
A7
MOO
~
.....
I
rLLLLLA
MOO
#1
#0
B2
'.r7A
I I
8
A
J L~
~ terminator
Line
,
Used for
dual channel
oPtion only
AO
BO
A1
B1
A2
B2
A7
87
Control unit II
,I
a) Star-chain cabling
3·32
B03P-4760-0111A ... Ol
Control unit I
A
r-:]
80
B1
82
I
I
I
1
r+-
rAll 1-
1
8
A
1AI
MOO
#1
#0
8
~
MOO
MOO
I I
87
Lfj
A
A
1
I I
#2
8
B
TI I
I
J
J
81
80
[:>
----~
MOO
'///~
,-A...J
Go8
82
A
j
Line
terminator
J LBrUsed for
dual channel
>option
only
87
Control unit"
b)
Daisy-chain cabling
Figure 3-6-4 System Interface Cabling
Figure 3-6-5 Interface Cabling
B03P-4760-0111A ... 01
3·33
(2) Cable Termination
I ri the daisy~hain configuration, (A) cable signals must be terminated at the
last disk drive with four IC module-resistors packs as shown in Figure 3-6-6.
The four Ie module resistors packs are installed in all disk drives; therefore
they must be removed from the disk drives on which the line termination is
unnecessary.
eNl
)
KGFM PCB Assembly
Figure 3-6-6 Cable Termination
3.6.4 System Grounding
(1) This drive unit is uniformly grounded at the signal ground (SG) connector.
If FG and SG connection is required on the system, use the SG tap at the
back of the unit, shown in Figure 3-6-7.
The optional AC fan unit (B03B-4740-E002A, -E003A) is grounded at the FG
(Frame ground) connector, the SG (Signal ground) is separated from the FG
(Frame ground) with insulating bushings.
A grounding cable may be connected as shown in Figure 3-6-8, if it is required.
(2) The' FG and SG terminals are provided with the optional power supply unit.
Connecting or disconnecting FG and SG on the power supply unit can be
performed according'to system power distribution and system ground requirements.
3-34
B03P-4760-0111A ... 01
SG. terminal (M4 PO.7)
'\
I
(Top view of rear side)
)
Figure 3·6·7 SG Terminal
B03p·4760-0111A ... Ol
3-35
SG terminal
Fan unit
II
\
C
~
Drive unit ~
FG terminal
Figure 3-6-8 FG/SG Connection
3.7 MODE SELECT SETTING
When the M233X Micro Disk Drive is installed in the system, the customer must set
switch 1 through 3 according to system requirements; these switches determine, Disk
Logical Unit Number, Sector Mode, Tag 4/5 Enable, File Protect and Sector Counting,
Switch 1 through Switch 3 are located on the KGFM PCB Assembly, as shown in Figure
3-7-1.
3-36
B03P-4760-0111A ... 01
\
}
o
J
SW1 to 3
7
c:::::.
SWl
--0
c:::::::.
c:::::::.
4 c:::::::.
6
5
c:::::.
3
2 c:::::::.
1 c=JI
SW2
,
~
ON
OFF
SW3
00
(Top View)
Note: SWl consists of 10 keys, and SW2/3 are 7 keys respectively.
Figure 3-7-' Mode Select Switch Location
3.7.1 Disk Addressing
Disk Logical Unit Number 0 to 7 is selected by SW1 at location E3 on the KGFM
PCB assembly. Set the desired disk address with the three keys on SW1 using the
binary code as shown in Table 3-7-1.
Table 3-7-1 Disk Addressing
Key 1
Disk Address
Key
2
Key 3
21
2'
2'
0
OFF
OFF
OFF
1
ON
OFF
OFF
2
OFF
ON
OFF
3
ON
ON
OFF
4
OFF
OFF
ON
5
ON
OFF
ON
6
OFF
ON
ON
7
ON
ON
ON
SW1
12
31
t2J
03.
. Key 3
13
21
k'J
02.
. ... Key 2
14
1
I
t2J
01 . . . . . ...
ON
. Key 1
OFF
E3 (KGFM)
Figure 3-7-2 Disk Addressing
B03p·4760·0111A ... 01
3-37
3.7.2 Tag 4/5 Enable
The M233X provides op~ional Tag 4 and Tag 5 functions. The customer may
disable or enable these optional functions using Key 8 on SW 1 at location E3 on
the KGFM PCB assembly, Refer to Figure 3-7-3. Disabling the Tag 4 and Tag 5
functions inhibhs the receivers of Tag 4 and Tag 5 receivers on the interface.
Table 3-7-2 Tag 4/5 Enable
T3Ig 4/5
Key 8
Disable
OFF
Enable
ON
SW1
08 - - - - - - Key 8
13
ON
E3 (KGFMl
Figure 3-7·3 Tag 4/5 Enable
3.7.3 File Protect
When the customer desir.e~ to in,hibit the write operation, the File Protect key
may be set to the On position, uSing Key 9 on SW1 at location E3 on KGFM PCB
assembly. Refer to Figure 3-7-4.
Table 3-7-3 File Protect
File Protect
Key 9
Enable writing
OFF
Disable writing
ON
SWl
,--_-,,1%:.:.1:3
ON
-------- Key 9
OFF
E3(KGFM)
Figure 3-7·4 File Protect
3-38
S03P-4760-0111A ... Ol
3.7.4 Device Type (optional)
The device type, M2331 K or M2333K, can be selected by setting key 4, 5, 6 and
7 on SW1.
Table 3-7-4 Device Type
Device Type
Key 4
Key 5
Key 6
Key 7
M2331
OFF
OFF
ON
ON
M2333
OFF
ON
ON
ON
SW1
_______ Key 7
,----,-""f::.::J::::J
---
_h -
Key 6
------ Key 5
, - - _...
[:1.;..o/J
ON
u
-
-
u
Note: Tag 4/5 feature must be enabled to
obtain device type status.
Key 7 should be always "ON" if the drive
is a M2331 K/M2333K.
Key 4
OFF
E3 (KGFM)
Figure 3-7-5 Device Type
3.7.5 ON-Side Switch (for vertical mount)
When the drive is installed to the On-Side position, (Vertical mount) Key 10 must
be in the 'ON' position. When unit is horizontally mounted, Key 10 must be
'OFF'.
Table 3-7-5 On-Side Switch
Device Type
Key 10
Normal position
OFF
ON-Side position
ON
SW1
,--_<.;;v..:.J'2
ON
--- --- Key 1'0
OFF
E3 (KGFM)
Figure 3-7-6 On-Side
B03P-4760-0111 A ... 01
3-39
In addition short plugs (54, 55, 56) located on the CZOM PCB must be set as
follows:
__ Plug
:p/
/;!/
54
ON-SIDE
55
56
Normal installation
In normal (horizontal} installation, 54, 55 alid 56 must be open as in the above
figure.
3.7.6 Sector Counting
5ector count configuration switches 5W2 and 5W3 are .located at A25 and A23
respectively on the KGFM PCB assembly. Each key of 5W2 and 5W3 represents
the binary powers of the Byte Clock as shown in Table 3-7-6 .
. Table 3-7-6 Sector Counting Keys
SW2 Key No.
Value
SW3 Key No.
Value
1
2
1
256
2
4
2
512
3
8
3
1024
4
16
4
2048
5
32
5
4096
6
64
6
8192
7
128
7
16384
)
J
5W2 and SW3 keys must be set according to the desired even number of bytes per
sector. Knowing that the number of bytes possible on a track equals 40,960, any
sectoring requ irement from 1 to 128 sectors per track can be configured using the
following formulas:
(1) Calculation based on SectorslTrack
EXAMPLE
. (Calculations for 9 Sectors)
1)
40,960
Number of sectors
= Number of bytes
40:60
= 4,551
per sector
2) If the above calculation results in a remainder,
truncate the remainder and add one or two
the integer portion of "number of bytes
per sector" to get even number. ,_
4,551 + 1 = 4,552
EXAMPLE
(Calculations for 9 5ectors)
3·40
B03P-4760·0111 A ... Ol
)
3) Configure SW2 and SW3 to "number
of bytes per sector" less two to
allow for sector counter reset clock.
Keys must be "ON":
4,552 - 2
4,550
= 4,096+
Key #
5
256 + 128 + 64 + 4 + 2
1
SW3
4) To determine how many bytes (if
any) the last sector of each track will
be short, multiply "number of bytes
per sector" by "number of sectors"
and subtract 40,960.
= 4,550
7
6
2
SW2
4,552 x 9 = 40,968
-40,960
Last sector short 8 bytes
(2) Calculation based on Bytes/Sector
Example: 584 Bytes/Sector
1) Calculate the value to be set. = 16,384 - (Byte/Sector)
(Particular Value)
= 16,384 - 584
= 15,800
2) Select the keys must be OFF position referring to Table 3-7-6 after the
following calculation.
15,800=8,192+4,096+2,048+1,024+256+128+32+16+8
6
5
4
3
1 7 5 4 3
Keys must be "OFF":
)
SW3
SW2
3) Calculate the Sectors/Track
_ Bytes/Track
Sectors/Track- Bytes/Sector
_ 40,960
- 584
= 70,137
4) If the above calculation results in a remainder, truncate the remainder.
Th; integer portion means actual sectors per track.
Actual Sectors/Track = 70
5) Calculate.the number of the last sector (remainder).
Last Sector Length = 40,960 - (Bytes/Sector) x (Sectors/Track)
=40,960 - 584 x 70
= 80
B03P-4760-0111A ... 01
3,41
Table 3·7·7 Commonly Used Sector Counting
LAST SECTOR
NOOF
SeCTORS
SW2
1 234 5 6 7
1 2 :3 4
567
4
1 1 1 1 1 1 1
i
1
1
o
0 1 0
10,240
0
8
1
1
1
1
1
1
o
0
f
0 0
5,120
0
12
0
1
0 1 0 1 0
1
0 1 1 000
3,414
-8
16
1
1
1
1
o
2,560
0
24
1 0
0
1,708
-32
32
1 1 1 1 1 1 1
o
0 1
0
1,280
0
64
1
1 1 1 1 1 0
0
1
o
0 000
640
1
o
0 0 .0
128
1
1
1
SW3
0 1 000
1
1
1
1 0 1 0
1
0 1 1
1 1 1
1
1 1
o
0
o
o
0
0
o
o
o
0
BYTE/SECT
320
SHORi
0
,
0
3.8 SHIPPING
Perform the following operations when the M233XK is to be shipped mounted in a
19-i neh rack,
(1) Secure the unit:
We recommend to attach a elastic material to the mounting-frame side near the
rubber shock-isolator, so that excessive force is not applied to the isolators.
Refer to 3.4.4 for securing the unit.
(2) This process is required so that the shock applied to the unit during shipment
does not exceed 5G.
3.9 STORAGE AND REPACKING
When reshipping the unit, repack it in the original carton or a carton having equivalent
functions.
When the environmental conditions are severe and the unit is to be stored for an extended period of time, it should be packed in its box.
Units can be stacked three cartons high,
When storing unpacked units. avoid locations that are dusty or subject to extreme
environmental changes.
3·42
B03P-4760·0111A ... 01
Section 4
Theory of Operation
'\
)
4. THEORY OF OPERATION
4.1 GENERAL DESCRIPTION
The operation of the M233XK is divided into three parts. The first part (Section 4.2)
describes the mechanical assemblies of the unit. The second part (Section 4.3 and 4.4)
describes the magnetic heads and magnetic disks. The third part (Section 4.5 and 4.6)
describes the interface, servo circuit, R/W control, and other electronic controls.
4.2 MECHANICAL ASSEMBLIES
4.2.1 Disk Enclosure
The Disk Enclosure (DE) is a completely sealed unit containing the disks, spindle,
actuator, and heads.
The DE is sealed at the factory and must not be opened in the field.
4.2.2 Air Circulation in DE
As the Contact stop/start (CSS) head used in this disk unit has a very low flying
height, head crashes can be caused by microscopic foreign particles. To keep the
inside of 'the DE clean, the enclosure is completely sealed and clean air is supplied
through two filters. A breather filter is used for external air intake, while are·
circulation filter keeps the air inside the DE clean. Refer to Figure 4.2.1.
The breather filter is used for the following purposes:
(a) Prevention of negative pressure in the vicinity of the spindle when the disk
begins to rotate.
(b) Prevention of dust intake when the air in the DE contracts due to a tempera·
ture difference between the DE and its environment.
The re-circulation filter, attached to the closed loop duct in the DE, is used to
keep the air free of foreign particles. When a pressure difference is caused in the
DE by the rotation of the spindle, the air in the DE circulates through the closed
loop. Because it continually passes through this filter, the air is always kept clean.
These two filters can remove 99.97% of the dust particles (O.3pm min.).
Closed loop air circulation
Rotary actuator
\
Spindle
Disks'
I
\
;
/
'
\
'
Re-circulation filter (absolutel
\
Disk enclosure (aluminum castingl
,
Air inlet
\
Closed loop air circulation
Breather filter (absolutel
M2331
M2333
contains 3 disks in DE
contains 6 disks in DE'
Figure 4·2· 1 Air Circulation Inside DE
B03P-4760·0111A ... 01
4-'
4.2.3 Spindle Drive Motor
The spindle/drive motor' is an integral part of the chassis. It consists of seven
major components: Shaft, Hub, Bearings, Stator, Rotor, Antistatic Brush, and
Speed Sensor. Refer to Figure 4.2.2. The motor shaft is fixed within the motor
housing by upper and lower bearings which are sealed to prevent contamination
of the disk platter environment. The stator is fixed to the outer radius of the cast
motor housing. The hub is fixed to the top of the motor shaft. The rotor and disk
platters are fixed to the hub. The antistatic brush contacts the bottom of the
motor shaft and dissipates any electrostatic noise to the chassis. Hall-effect
sensors detects hub movement. The signal produced by this sensor is compared
with an oscillator clock on the PCB in order to maintain the normal RPM
rotational speed of 3,600 RPM, the special range.
Bearing
Ro.ter
Shaft
'-,
\
'''''" Stator
'/
Disks
\
'~
Speed sensor (hall·effect sensor) ~
)
Aluminum casting
Antistatic brush
Breather filter
Figure 4-2-2 Spindle Drive Motor
4.2.4 Actuator Arm Assembly
A low-power-consumption, rotary-type actuator is used to move the data heads
and servo head along a circular arc to the specified cylinder. A moving coil is
attached to the other end of the actuator arm and moves freely between fixed
permanent magnets without contact. When current is applied to the coil, the coil
and magnets interface and the actuator moves around the pivot. Refer to Figure
4.2.3.
The actuator performs the following types of motion, which are controlled by
servo feed·back current from the sento head.
4·2
B03p·4760·0111A ... Ol
(1) Seek
Heads are moved to the specified cylinder while counting track-crossing
signals.
(2) On Cylinder
Heads follow the specified tracks. The servo system prevents mispositioning
due to disturbances such as shock, vibration, or temperature changes.
The servo head is located on the lower surface of the bottom disk, where servo
information is pre-written at the factory.
This servo information is used as a control signal for the actuator; that is, it
provides track-crossing signals during a seek operation, track-following signals during On Cylinder operation, and timing information such as index and servo clock.
The heads are in contact with the disk surfaces during start and stop (CSS) at a
fixed position called the landing zone. This zone is on the innermost area of the
disk, separate from the recording zone. A spring force holds or fixes the actuator at this position. If no current is applied to the moving coil, the heads are
fixed at the landing zone to prevent CSS in the recording zones.
Once the disks attain the required rotational speed, an initial seek function
occurs. Current then flows in the coil and the heads are released from the
landing zone and moved to Cylinder O.
Actuator arm
/
Movable coil
\
I
)
)
Figure 4·2-3 Actuator Arm Assembly
B03p·4760-0111A ... 01
4-3
4.3 MAGNETIC HEADS AND RECORDING MEDIA
4.3.1 Magnetic Heads
To accomplish high density recording, Contact Start/Stop (CSS) flying heads are
employed. The heads fly on the surface air flow generated by the rotating disk.
The CSS system differs from the conventional ramp-load system in that the heads
are always over the recording media and rest on the disk surface when the disk is
not rotating.
Since, the head and disk make contact, the wear caused by this contact must be
minimized. Therefore, the CSS heads are lightly loaded and surface pressure is
reduced by using a tapered flat slider such as that shown in Figure 4·3-2. The
slider has three rails. The ajr intake end of the slider is tapered to obtain lift from
the air flowing over the disk surface. Read and write are -performed by a ferrite
core at the rear of the head, the minimum flying height position.
; - - ReadlWrite Gap
Slider
~
Load Spring
/
Disk Motion
Figure4-3-1 ReadlWrite Head
)
Air bearing taper
Read/Write gap
Ferrite core
.
Rail bevel
Coil
SU5pention attachment notch
Ferrite slider
Back gap
Figure 4·3·2 Tapered Flat Slider
4-4
B03P-4760·0111A ... 01
)
4.3.2 Recording Media (Magnetic Disk)
The data recording media are aluminum disks approximately 210 mm (8%
inches) in diameter and approximately 2 mm 05 mil) thicK, and are coatedwith a magnetic material. Since the M233XK employs ess heads, to prevent
wear the surface is coated with a special material. Up to six disks can be installed
for a maximum storage capacity of 337 MB. The bottom surface of the lowest
disk is for the servo area, on which the positioning data and clock signals are
recorded.
4.3.3 Servo Track Format
(1) Servo track configuration
The servo area is used to store the unique data patterns which generate the
Track Positioning, Index, Guard Band, and Clock signals. This data is recorded
on the disk before the unit is shipped from the factory.
The servo area consists of a combination of 0001, 0002, EVEN 1 and EVEN2
tracks. The physical placement of servo tracks is shown in Figure 4-3-3. The
servo tracks are divided into the following five parts:
a. Dead Space (OS or Landing Zone)
Dead Space is used for h·ead contact during start and stop. -OS consists of
five ~C-erased tracks and is recognized as Head Unloaded through the servo
circuit.
b. Inner Guard Band 2 (IGB2)
Inner Guard Band 2 is used for speed control during RTZ or Initial seek
sequence. IGB2 consists of six EVEN1-EVEN2 tracks, six OD01-EVEN2
tracks, six 0001 - 0002 tracks and six EVEN1- 0002 tracks (24 tracks
total).
c,. Inner Guard Band 1 (IGB1)
Inner Guard Band 1 is located between IGB2 and Cylinder 0, and is used for
speed control during RTZ or Initial Seek sequence. IGBl consists of four
EVEN1-EVEN2 tracks, four 0001-EVEN2 tracks, four 0001-0002
tracks and four EVEN1-0002 tracks (16 tracks total).
d. Servo Band
Servo Band is used for tracking to determine the center of each cylinder .•
The Servo Band consists of 207 EVEN1 -: EVEN2 tracks, 206 0001 EVEN2 tracks, 206 0001 - 0002 tracks, and 207 EVEN1 - 0002 tracks
(826 track total). However, 1-% inner tracks of Cylinder 0 and 1-% outer
tracks of Cylinder 822 are not utilized for corresponding data tracks.
e. Outer Guard Band (OGB)
The Outer guard Band is used to recognize that the head has passed through
the servo zone in an outward direction. OGB consists of three EVEN 1 EVEKl2 tracks, three 0001 - EVEN2 tracks, three 0001 .--:. 0002 tracks
and three EVEN1 - 0002 track minimum (12 tracks minimum total).
0
)
)
B03P-4760-0111A ... 01
4·5
r' -,
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m
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,
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\
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o
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"
\
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m
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\
\
\\ \\
\,
'.
\
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os
IG82
IG8.
Servo Band
OG8
DC Erased
8'" 8~
>- u>u
~
u
;;
II)
>
u
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a>
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u
to",
'J'.
f'<
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CD
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u
II
I Phase 1
07
I Phd'U 2
u>
Figure 4-3-3 Servo Track Configuration
',-/
'---'
-----
(2) Servo pattern
)
The servo signal is a unique "Dual-phase composite servo signal" which. creates
a high-performance positioning system. It is used to achieve angular positioning
(location with reference to the circumference of the disk) and radial positioning
(location with reference to the radius of the disk).
Angular positioning is determined by a series of sync bits which are written on
each track. Through a combination of Index Bit and Normal Bit; the "sync
pattern" is developed. A series of unique sync patterns is written at the factory
and used in the identification of specific disk regions. Refer to Figure 4-3-4 and
Figure 4-3-5. Index mark, OGB, IGB1, and IGB2 patterns are described in
paragraph 4.3.3 (3).
)
B03p·4760·01 1 1A ... 01
4·7
Index ·Pulse
Sync Pulse
Odd2 Pulse
Odd1 Pulse
Index Pulse
Even1 Pulse
ODD1·EVEN2
ODD1·0DD2
)
EVEN1·0DD2
EVEN1·EVEN2
One Cycle
3,25,,5)
(8·Data·~yte:
Figure 4·3-4 Normal Bit Pattern
4·8
B03P-4760·0111 A ... 01
)
Sync Pulse
Odd2 Pulse
Even2 Pulse
0001·EVEN2
0001-0002
EVEN1-0002
EVEN l-EVEN2
l O n e Cycle
8·Data-Byte-_ 3 .25J.lsi
Figure 4-3-5 Index Bit .p-attern
B03P-4 760-0 111 A .. . 01
4-9
Radial positioning information is provided by writing 0001-EVEN2, 000"10002, EVEN1-0002, and EVEN1-EVEN2 patterns, in that order, on the
servo surface.
)
During head movement, the servo circuit detects the amplitude changes between
0001 and EVEN1 peaks (phase 1). and between OOD2 and" EVEN2 peaks
(phase 2)' and then converts them into two position signals (phase 1: Normal,
phase 2: Quadruture) through the position sensing.
After head movement, the servo head, which has double the core width of the
data head, settles on the border of two types of servo patterns controlled by the
two I.east-significant bits of the target cylinder address. The servo circuit then
makes the 0001 (or 0002) peak equal to the EVEN1 (or EVEN 2) pea.k by
positioning the servo head on the center of the servo track. Re·fer to Figure
4-3-6.
)
)
4-10
B03P·4760·0111A ... Ol
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c:
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z
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x '"
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z
z
z
z
z
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z
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W:0-
tIl :ex X:XI
~R1
L
SN75110
R3
470 n
R2
SN751 07/75108
15 m max.
SN75110 Input
H
OV
SN75110 Output
I
L: -0.98V!
X,--_
I
- .....I----t-.--10ns,:S. To,:S. 35ns (at 10% - 90%)
SN751 07 Output _ _ _ _ _ _ _ _- - '
a)
Balanced Transmission of "8" cable
Note:
1.
2.
Cable shall be flat with characteristic impedance of 100 ± 10 ohms.
Line terminators are located on the receivers at the drive or control unit.
Rl and R2
are 82 ohms ± 5%, 1/10W.
3.
R3 ana R4 (470 ohms) are' located on the receiver side
470 n ± 5%, 1/10W. But to
improve the reliability of the transmission at the high transfer rate (over 2 MB/S), the
resistors R3 and R4 of the clock (WCLK, IFWCLK, IFRCLK) and Data (WDAT, RDAT)
Lines on the control unit and disk Drive should be eliminted.
4.
A bias network should be used to prevent disturbance conditions by power failure at
the control unit end of Unit Selected and Seek End signals as in b).
-5 V
15 kn
)
470n
USLDH
USLD
USLDL
)
15 kn
SN751 07/75108
+5 V
b) 8ias Network to Prevent Power Failure Disturbance
Figure 4-5-28 Balanced Transmission "B" Cable
B03P-4760·0111A ... Ol
4-39
(4) Channel Ready Driver
The Channel Ready signal must be issued so that data is protected during a
power failure of the control unit. Relay logic and passive terminations sometimes aid this requirement. If SN75110A drivers are used to -drive the Channel
Ready signal from the control unit, dual drivers should be connected in parallel,
and no 56 ohm termination to ground should be used at the control unit.
4.5.8 Connectors and Cables
(1) Connectors
a. "A" Cable connectors (60 positions)
Refer to Table 4-5-7.
Table 4·5·7 "A" Cable Connectors
Fujitsu Specification
Connector
Drive Side
FCN·702P060-AUlM
FCN-704P060-A UlM
FCN-705P060-AU/M
(Wire Wrapping)
(Straight}
(Right Angle)
Cable Side
FCN-707 JOSO-AU/B
FCN-707 J060-A UlO
(Closed End)
(Through End)
b. "8" Cable connectors (26 positions)
Refer to Table 4-5-8.
Table 4-5-8 "S" Cable Connectors
Fujitsu Specification
Connector
Drive Side
FCN· 702P026·A UlM
FCN-704P026-AU/M
FCN-705P026-AUlM
(Wire Wrapping)
(Straight)
(Right Angle)
Cable Side
FCN-707J026-AU/B
FCN-707J026-AU/O
(Closed End)
(Through End)
(2) Cable
Refer to Table 4-5-9,
Table 4-5·9 Cable
Cable
A
8
4-40
Specification
, 455-248-60 Spectra Strip
Zo=1000hms! 100hms
28 AWG, 7 strands
174-26 Ansley
I 3476-263M
Zo = 100 ohms ± 10 ohms I Zo = 130 ohms ± 15 ohms
28 AWG, 7 strands
128 AWG, 7 strands
B03P-4760-0111A ... 01
\
}
4.5.9 Connector Pin Assignment
(1) "A" Cable Connector 60 Pin
Refer to Table 4-5-10.
Table 4-5-10 "A" Cable Pin Assignment
Pin
1
Function
Pin
Function
Tag 1 L
31
Tag 1 H
2
Tag 2 L
32
Tag 2 H
3
Tag 3 L
33
Tag 3 H
4
Bus 0 L
34
Bus 0 H
5
Bus 1 L
35
Bus 1 H
6
Bus 2 L
36
Bus 2 H
7
Bus 3 L
37
Bus 3 H
8
Bus4 L
38
Bus 4 H
9
Bus 5 L
39
Bus 5 H
10
Bus 6 L
40
Bus 6 H
11
Bus 7 L
41
Bus 7 H
12
Bus 8 L
42
Bus 8 H
13
Bus9 L
43
Bus 9 H
14
Channel 1 Ready L
44
Channel Ready H
15
Status 3 L
45
Status 3 H
16
Status 2 L
46
Status 2 H
17
Status 1 L
47
Status 1 H
18
Index L
48
Index H
19
Status 0 L
49
Status 0 H
20
Status 5 L
50
Status 5 H
21
Busy L (Dual Channel Only)
51
Busy H (Dual Channel Only)
22
Unit Select Tag L
52
Unit Select Tag H
23
Unit Select 1 L
53
Unit Select 1 H
24
Unit Select 2 L
54
Unit Select 2 H
25
Sector L
55
Sector H
26
Unit Select 4 L
56
Unit Select 4 H
27
Tag 5 L (Selectable)
57
Tag 5 H (Selectable)
Status 4 H
28
Status 4 L
58
29
(Pick): Not used
59
(Hold): Not used
30
Tag 4 L (Selectable)
60
Tag 4 H (Selectable)
(2) "B" Cable Connector 26 Pin
Refer to Table 4-5-11.
Table 4-5-11 "B" Cable Pin Assingment
Pin
1
Function
Pin
Function
GND
14
1 F Write Clock H
2
1 F Write Clock L
15
GND
3
Read Data L
16
Read Data H
4
GND
17
1 F Read Clock H
5
1 F Read Clock L
18
GND
6
Write Clock L
19
Write Clock H
7
GND
20
Write Data H
8
Write Data L
9
Unit Selected H
22
Unit Selected L
Seek End H
. 21
GND
10
Seek End L
23
11
GND
24
Index H
12
Index L
25
GND
13
Sector L
26
Sector H
-B03p·4760·0111A ... 01
4-41
4.6 ELECTRICAL CIRCUIT FUNCTION
4.6.1 Start/Stop Control
DC powers of +5V, -12V and +24V are applied to the drive from the optional
power supply unit or system power. +12V required for servo circuit is regulated
from +24V on TVQM PCB "assembly.
)
The DC voltage monitor circuit (which monitors +5V, -12V, +24V and internal
+12V) issues Power Ready (PWRDY) signal through the delay circuit when these
voltages are within the specified range.
When +5V is supplied to the drive, the Crystal Oscillator circuit issues
15,72B,640 Hz clock signal, this clock signal is divided by eight and converted
into Control Clock 1 (CTCL 1) at 1,966,080 Hz frequency which controls DC
Motor Control circuit function. Then the CTCL 1 signal is divided by thirty-two
(32) and converted into Oscillator Clock (OSCLK) at 61,440 Hz (16.3;.LS interval)
which controls Power-up Sequence Cont~ol circuit function.
Disabling of PWRDY signal resets all registers and latches on the drive, and
also resets three latches at Power-up Sequence Control circuit, that is, Start
Sequence Latch 1, 2 and 4 (SSL 1, 2 and 4) signals which result in State O.
The PWRDY signal is applied to a delay circuit (45 .us) and consequently Delayed
Power Ready (DPWRDY) signal is issued to the Power-up Sequence Latch circuit.
The leading edge of DPWRDY signal sets SSL 1 latch and results State 1.
One hundred thirty milliseconds after enabling state 1, Emergency Retract
(EM RT) signal is reset, and the relays R L 1 and RL2 are activated on the TVQM
PCB assembly. The contacts r£ 11 to r£ 13 of R L 1 connect the DC Motor Poweramplifier and DC motor windings, the DC Motor Power-amplifier, however,
is not activated by disabling the later-mentioned ACDME signal at this state. The
contact RQ 14 of R L 1 applys +5V to the" solenoid of auto-lock, the auto-lock,
however, is not released at this state.
)
The contact rQ21 of RL2 applys +24V power to the VCM power amplifier.
°
One second after resetting EMRT signal, the circuit checks whether Accelerate DC
Motor (ACDM) signal which must be set at State is true or false. If ACDM is
true at this state, SSL2 latch is set and then the state moves to State 3. If not
true, the Sequence inhibit (Sal NH) latch is set.
One second after enabling State 3, Lock Release (LKRLS) signal is set and holds
for two seconds. The LKR LS signal activates relay R L3 and then +24V power is
supplied to the auto lock solenoid which releases the actuator lock of VCM. One
second after releasing the actuator lock, the circuit checks whether the current
flows through the solenoid coil or not. If correct, SSL 1 latch is reset and the
state moves to State 2. If not, SQINH latch is set.
One hundred-thirty milliseconds after enabling State 2, Accelerate DC Motor
Enable (ACDME) and Compress Active (COMPACT) which enables the acceleration at DC motor is set and the Spindle begins rotating with the aid of "Compress" action enabled by COMPACT signal which holds for 270 milliseconds.
During the Compress action, current flows through the VCM coil and the heads
are compressed toward center of the spindle on the landing zone. DC motor is
accelerated according to the phase of Speed Sensor outputs (three Hall-effect
elements), which is then converted into a Set Speed (STSPD) signal once per
revolution. When the rotational speed is up to 3,366 rpm (-6%), Speed Good
(SPGD) signal is issued. Going-true of SPGD signal during State 2 sets the SSL4
latch, and the state moves to State 6. If the rotational speed is not up to
3,366 rpm within fifty-two seconds, SQI NH latch is set. .
When the DC motor is further accelerated (up to 3,600 rpm), the DC Motor Control circuit changes to inertia mode from accelerate mode. Simultaneously a
4-42
B03p·4760-0111A ... 01
)
)
Start Pulse (STARTP) signal is issued, which initiates the internal initial seek
sequence. Going-true of STARTP signal during State 6 sets SSL 1 latch, and then
the state moves to State 7. If STARTP signal does not go true within sixteen
seconds, SOl NH latch is set.
The internal initial seek is performed in State 7. The detail of initial seek sequence is described in paragraph 4.6.4.1. The completion of the initial seek
sequence resets SSL2 latch, and then the state moves to State 5. The incompletion of the initial seek sequence sets SOl NH latch.
State 5 indicates that all power-up sequences are completed.
When DC Motor Fault (DMFL) or VCM Heat (VCMHT) malfunction occurs
during any state, or a specific malfunction has occurred during each power-up
sequence, the SOl NH latch and Device Check (DVCK) latch are set on the drive
and the condition is frozen at that state. Going-true of SOINH latch sets EMRT
signal and all relays are deactivated on TVOM PCB assembly.
When check clear (CKCLR) signal which is issued from the controller or the
optional operator panel during SOl NH State, SSL1, 2 and 4 are reset; and the
Power-up Sequence is initiated again.
The Start/Stop Control block diagram is shown in Figure 4-6-1, Power-up Sequence Control block diagram in Figure 4-6-2, Power-up Sequence flow chart in
Figure 4-6-3 and Power-up Sequence timing chart in Figure 4-6-4.
)
B03P-4760-0111 A ... 01
4-43
r--
.".
t
I
-------,----
I
I
I
I
I
I
Seek Control
Cireuil
-----------1---I
--------TB
I
I
~
-------1
+24V
~ ,~21
I
I
I
I
_ _ __
I
I
I
~:
.(').
I.
a:I
a
w
OSClK
"'0
Power-up
Sequence
Control
Circuit
.;..
.....e
en
0
6
.....
SPGD
STAR1P
~
ACDM
....
»
ACDME
I
b
I
----,.~f-H
rVII
~
DC
Motor
Power
Amplifier
I
I
rU2
, rll13
I
,
I
I'
Compa,ator.
! ·BRSNS
Brake
i
Cireuil i
lJ-.J\IV'.___-Q
PWRDY :
I
I
I
DC Voltage
Monilar Circuil
I
""'----7--
I
+5V
I
-12VI
+24V
I
I
t
I
L
+12V
+~Lr-I!-14-e~_r--r_~---------------J.
+24V
i
I
I
8
I
I
I
KGFM
CZOM
_ _ _ _ _ _ _ _ _ _ _ _ .1I _____
_
I
I
I
J
I
I
I
Autoiock
Solenoid
____
T
I
'lKlSD
_ I
--
I
DC Malar
Control
Circuit
I TVOM
- - - - - ..J __ -
- -
- -
- -
-
I
I
Disk Enclosure (DEI
________ L - -
I
____________________ J
Figure.4-6-1 Start/Stop Control Block Diagram
~
'....-/.
'---'
.~
I
\
SPGD/LK LSD/STARTP/PWRDY
V
•\
.---
.;
.--
SSLl
SSL4
I
I
STO - ST7
-0'
-j
Cl
0
-L..-
r
r(f)
f-~r-
en
-...J
a
OJ
o
w
-u
OSCLK
.J,.
"o
CJ)
6
POWER-UP
CONTROL
CLOCK
CIRCUIT
(AGO
1
»
r-.
TMRST
s:
(f)
I
OJ
00
(f)
'"
-j
0
~I----'\
-j
j
'-
»
JJ
1-----1
~
:
I
I
(f)
a
-j
-0
-
-
'I
(f)
s:
N
POWER-UP
SEQUENCE
DECODER
I----
\
~
SSL2
POWER-UP
SEQUENCE
LATCH
START/STOP
LATCH
I--
--
I----
--
I---
r-V
1-
--
EMRT
*LKLS
ACDME
-
o
I I
l'
"
L-\
POWER-UP
SEQUENCE
CHECK
CIRCUIT
SQiNH
--v'
t
DMFL
VCMHT
1
EMERGENCY
DETECTOR
,
--
EMGN
I
-""
.J,.
U1
Figure 4-6-2 Power-up Sequence Control Block Diagram
(From Sheet 4)
Power On
G
NO
Reset SSL 11
SSL.2
SSL4
(SSLl OJ
(SSL2 0)
(SSL4 OJ
State 0
(Power·on
Reset
Sequenc~)
YES
NO
)
(SSL1: 1J
(SSL2: OJ
(SSL4: OJ
State 1
(+24V
Supply
Sequence)
RLl/RL2: On
(To Sheet 2)
B
c
(To Sheet 4)
(To Sheet 4)
)
Figure 4-6-3 Power-up Sequence Flow Chart (Sheet 1 of 4)
446
B03P4 760-0111 A ... 01
(From Sheet 1)
Rl3: On
State 3
(Auto-lock
Release
Sequence)
Rl3: Off
)
No
Yes
State 2
(DC Motor
(Accelerate
Sequence)
E
D
ITo Sheet 3)
)
Reset CMPACT
ITo Sheet 41
Figure 4-6-3 Power-up Sequence Flow Chart (Sheet 2 of 4)
B03P-4760-0111A ... 01
4-47
(From Sheet 2)
)
Set
SSl1
(SSL1 1)
(SSL2 1)
(SSL4 1)
State 7
( Initial
Seek
Sequence)
)
I nitial Seek
Sequence
NO
(SKI)
YES
Reset SSL2
(SSl1: 1)
(SSL2: Q)
(SSL4: 1)
State 5
(Ready
Sequence)
Normal End
(To Sheet 4)
Figure 4-6-3 Power-up Sequence Flow
4-48
Cha~
B03P-4760-0111 A ... 01
(Sheet 3 of 4)
)
(From
(From (From
Sheet 1) Sheet 2) Sheet 3)
(From
Sheet 1)
YES
YES
Continue Sequence
Frozen That State
Set SQINH
Set DVCK
R L 1/2/3: Off .
YES
NO
G
Check End
(To Sheet 1)
Figure 4·6·3 Power·up Sequence Flow Chart (Sheet 4 of 4)
B03p·4760·0111 A .. . 01
4·49
)
)
)
"---/
f"
(11
o
Slille
. SSl1
l" 1 "I' 3 "I"
_----'I
I
o
2
__
u
____
---j_
6
'I"
7
-r
5
'r---1----- - - ----1
SSL2
SSL4
________________,-
PWRDY
~
-------------
-
Lu __
- - ------------
u
,
DPWRDY
,
I
L_J
r----'
EMRT
I
•
I
I
ro
0
w
-u
.h.
ACDM
0
LK.LS
»
LKLSD
-..J
OJ
____
~n~
_________________________________
6
:
a
CMPACT
______~n~______________________~----____-Jr-n
- . -
ACDME
SPGD
----------------------------____________________-JI
STARTP
----------________~______~n~__________
SKC
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -_ _ _ _ _ _ _...J'- _______________ _
r------:----I
,
(SOINHI
(CKCLRI
L__ _
"
II
-
--------------~----------~,~,
Figure 4-6-4
Power-up Sequence Timing Chart
4.6.2 DC Motor Control
The block diagram of DC Motor Control is shown in Figure 4-6-5.
As mentioned in Section 4.6.1 (Start/Stop Control), the ACDME signal initiates
the acceleration of the DC Motor according to the phase outputs of the Speed
Sensor. During the start-up sequence, the Current Limiter limits the windingflow current to 4.0A nominal by detecting the voltage level at the bleeder resistor.
When the spindle rotation is initiated by initial stage, the Speed Sensor output is
converted into TTL level signals (Phase At Band C: PHA, PHB and PHC), are
then applied to Speed Detect and DC Motor Fault Detect circuits. The PHA,
PHS, and PHC signals have two cycles per revolution.
The positive-going edge of PHA signal sets tlie next latch and the negative-going
edge of *PHB signal resets this latch; the latch output signal is then applied to the
Clock Synchronize and Divider circuits which generate Set Speed (STSPD) and
Timer Clock (TMCLK) signals once per revolution. The TMCLK signal resets the
Divide Counter at the leading edge, and is also applied to the Time-out Counter.
The STSPD signal is applied to the Speed Detect and Accelerate Latch circuits.
)
)
B03P-4760-0111A ... Ol
4-51
f'
(]I
N
...c-
D
L
CRYSTAL
OSCillATOR
DIVIDE
COUNTER
15.728.640 Hz
1,966,080 Hz
CTCll
DIVIDE
COUNTER
SPEED
DETECT
-;- 65536
13%
044
..
{30 Hzl
TL--------,
SPGD
STSPD
r
ACCELERATE
LATCH
~
"ACDM
~
CD
o
W
-0
j,.
START
PULSE
LATCH
"
m
o
6
'STARTP
"ACDME
»
PHA
a
~
FROM
SHEET 2
'PHS
PHC
LATCH
L-
CLOCK SYNC
AND
DIViDER
~
TMCL
9
DC MOTOR
FAULT
DETECT
Figure 4-6-5 DC Motor Control Block Diagram (Sheet 1 of 2)
DMFL
r-- - --,
+24V
- r-
I
he
I
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r-'
I
I
I
-\
DECODER
.
"ACDME
!
f
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I
I
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,
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i
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4
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m
o
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6
»
VREF
f"
o
)., C
<
CURRENT
LIMITER
t---
+5V
T
+2VDC
REGULATOR
--------
TO
SHEET 1
B
I
I
IL _ _ _ _ _ J
J,.
I
A
i
i
.......
DC MOTO
I
I
I
I
I
A
I
I
I
I
Disk Enclosure
I
I
I
I
I'
o
),
I
I
~
I
I
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MULTIPlEXER
AND
DRIVER
I
:
I
r-
r------------- ---1
I
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T
SPEED SENSOR (HALL·
EFECT ELEMENT)
I
I
I
I
I
L----C
-( )-c
>-
)-
- ;r-
PHA
"PHS
COMPARATOR
PHC
"'"
ci1
Figure 4-6-5 DC Motor Control Block Diagram (Sheet 2 of 2)
w
'"---
'-.-/
~
During the power-up sequence, the leading edge of the PWRDY signal sets the
044 signal which is final stage output of the Divide Counter {Divided by 65536).
The 044 signal inhibits the count-up function of the Divide Counter until the
counter is reset by the leading edge of the TMCLK signal, and also isciocked by
the leading edge of the STSPD signal. When the 044 signal goes true, this indicates that the rotational speed is slower than nominal speed. When the rotational
speed is within ±6% of nominal speed, the Speed Good (SPGD) signal goes true.
About thirty-five seconds after power on, when the 044 signal is false at the
leading edge of the STSPD signal, DC Motor control mode is changed to inertial
mode from accelerate mode. Simultaneously, the STARTP signal, which starts
the initial seek sequence, is issued at the first negative going-edge of the ACDM
signal. The DC Motor control then repeats the accelerate mode and inertia mode .
and maintains the rotational speed at 3,600 rpm ± 1%.
The timing chart of the DC Motor power-up sequence is shown in Figure 4-6-6.
I n accelerate mode the ACDM signal is set by the leaGiing edge of the STSPD
which clocks the 044 signal, and the PHA, *PHB and PHC signals are decoded
into binary signals. By combining of these decoder outputs, the power amplifier
drives the DC Motor windings as shown in Figure 4-6-7.
4-54
B03P-4760-0111A ... Ol
________________ 1
PWR ON
PWRDY
V
I
~
S"rt-",,,,,,","W
'f-I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
I
" "
ACDME
STSPD
TMCLK
044
en
0
SPGD
w
-0
./:.
-...J
O'l
0
STARTP
6
LJ
r-
PHA
PHC
STSPD
TMCLK
m
01
L _______________________ ,
I~
1'---_
L___~ I
'PHB
./>.
•
i
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»
6
r
I
TRM1-1
f
TRMl-2
_---Ir
~,
-t+l~
I.
TRM1-3
________
n~_______
n~
509 ns
.1
One Revolution
Figure 4-6-6 Power Up DC Motor Control
~
TAMl-16
TRMl-15
•
L.,_"
Two Revolutions
PHA
-PHS
...
PHC
I~_
°ACDME
---,~
________________________________________~
Decoder
Output
131 , 151416 1213
Current
Direction
Tl T2T3T4 TS T6
I, 1514 161 2131, 151416 12 13 I, 15 14 16 12 I
Accelerate mode
I nertia mode
+24 V
·1
"3
A
°4
T2
Tl
T5,2 ~
°6
)
\
\
', .... ,
"T4
°2
"6
S
"1
DC Motor
Windings
"S
"4
"S
"2 - - - - ( : l
°3 ----("::1
Decoder
Output
Multiplexer
and Driver
Power
Amplifier
Figure 4-6-7 DC Motor Accelerate/Inertia Mode Control
)
4·56
C
B03P·4760·0111A ... Ol
4.6.3 Unit Selection
The Micro Disk Drive must be selected before it will respond to any commands
from the control unit. Tag and Bus receivers are not enabled until the unit is
selected.
This describes the dual channel functions related to selection. They are as
follows:
• Unit address select
• Reserve
• Release
• Priority select (unconditional reserve)
• Disable with a maintenance switch
The functional block diagram of dual port is shown in Figure 4-6-8.
(1) Unit Address Select and Re~erve
A unit is selected or resenied in an identical sequence which is initiated by Unit
Select Tag (USL TG) and a unit address signal (Unit select 1, 2,4: USL 1,2(4).
However, this sequence cannot start when:
• The unit is selected and reserved by the opposite channel.
• The unit is not selected, but reserved by the opposite channel.
• The channel which has attempted to select the unit is disabled by the maintenance switch on the unit or because the unit is placed in the Priority Select
state by the opposite channel.
The select/reserve sequence is as follows:
Suppose that the unit is ready to be selected that is, none of the above three
conditions exists. A controller sends USLTG and USL 1, 2, 4 to the unit. If
the unit address from the channel-A controller agrees with the logical unit number
(LUN), the unit sends Unit Selected to the channel-A controller through cable B
when Channel-A Compare (CHACMP) is sent to the XCGM printed circuit board.
This sequence is the same as with the sihgle-port configuration.
Unless the unit is selected or reserved by channel-B and, as a result, is Busy,
CHACMP causes the Channel A Selected signal (CHASLD) to be sent in synchronization .with Clock 1 (CLK1) from the oscillator. CHASLD turns on the
Channel-A Enable (CHAENB) signal to make the driver/receiver for Channel-A
r'eady for transmission/reception, drive the LED to indicate CHASLD, switch
the WDA T IWCLK multiplexer to Channel-A, set Busy to indicate that the unit
is selected or reserved by the Channel-A controller, and trigger the Set Reserve
(STRSV) one-shot multivibrator to set the reserve latch.
If channel-A and B attempt to select a unit at the same time, CLK1 and CLK2
(clocks with the same frequency and different phases) determine which channel
is to access'the unit. As a result, Busy is s,et.
The STRSV one-shot multivibrator output sets the Channel A Reserved
(CHARSV) latch about 300 ns after CHASLD. This CHARSV signal turns on
the LED on the XCDM printed circuit board, sets BUSY A, and sets Seek End
B (SKENDB) to"1" before its transmission to Channel-B. SKEND to Channel-S
is kept "'" as long as the unit is reserved by Channel-A.
The unit is kept selected/reserved by Channel-A until Channel-A is disabled by
the maintenance switch or until USLTG becomes false. When Channel-S
attempts to select the unit, the unit sends BUSY A as a busy signal to Channel-B,
and sends also Unit Selected B (USLDS) to indicate that it is selected/reserved
by Channel-A.
Even when USL TG from Channel-A goes false after the select/reserve sequence,
the unit remains reserved by Channel-A. This reserved state is not reset until a
Release command comes from Channel-A, Channel-A is disabled by the main-
B03p·4 760-0111 A ... 01
4-57
)
tenance switch, Channel-B performs Priority Select, or the power is turned on/
off.
If the opposite channel control unit attempts to select a channel while it is
selected or reserved by the other channel control unit (Le. in Busy statel. Tried
Latch in the dual channel is set. Thus, at the time when the one channel becomes
neither selected nor reserved, Seek End goes faise for 30 p.s so that the opposite
channel, having been waiting, can interrupt.
)
If the unit is in Disabled state (realized by Priority Select from the opposite
channel or by Disable switch) and the other channel attempts to select the unit,
no signal response is activated.
The block diagram of the select/reserve circuit is shown in Figure 4-6-9, and the
related flowchart and timing chart are shown in Figures 4-6-10 and 4-6-11,
respectively.
)
4-58
B03P-4 760-0111 A .. .01
~--
Disable
Switch
(,
Channel B
Control
Unit
I--
N-
-"
Z
U
DVfRV
F=I Jl J1
v
II
[
<.
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o
W
-0
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'--
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Ae~e've
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DV!IlV
CHA/CHB
UNASV
6
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Busv
v
I-
I--
",v
VI
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Ol
USLTG
~
USL
1,2,4
~,$0/#df\;~~+wZ:0j0
CHACMP
(USLOI
Channel
A
t
BUSYA
w
"
~
.....
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CHAASV
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1
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CHASLO
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Ol
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6
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USLTG
a
USl
1,2,4
CHBCMP
Channel
B
IUSLOI
PUSy
"'NO
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J I II
~~:; ~
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/@:?1/1f//I/!//l//l///ff;;V-V~~.....-r---
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UK!
ClK2
CHBCMP
CHBSlO
Figure 4-6-11 Select/Reserve Timing Chart
f
2~r~--;---:----
(2) Release
The release command resets the reserved and priority select (unconditional
reserve) states. Release is executed by two functions described in the following.
One is a release command from a control unit (Tag 3 Bus bit 9) and the other
is Release Timer of the dual channel option.
a.
Release command (Tag 3, Bus bit 9)
Reserve and Priority Select (unconditional reserve) are reset by the leading
edge of Tag 3 and Bus Bit 9 sent from the control unit. Thus, it is possible
to be accessed from the control unit of the opposite channel.
, b.
Release Timer
If the switch on the dual channel is set to the RL TM position. The Release
function is en"abled by the unit itself. If unit Select Tag signal goes false
when the switch is being set to the R LTM position, the Release Timer one·
shot (500 ms) is triggered. The Reserve Latch is reset by the trailing edge of
the Release Pulse.
If the switch is set the ABSL (Absolute Reserve) side, the one-shot is
disabled.
(3) Priority Select (Unconditional Reserve)
Even if a unit is selected or reserved (except unconditional reserve) by a channel,
the opposite channel can switch the unit to its channel by issuing a Priority
Select (Unit Select Tag, unit address and Bus Bit 9) command.
This command sets the Unconditionally Reserved (UCRSV) latch to inhibit all
signals, Select/Reserve is given to the channel and, at the same time, the channel
which was previously connected is disconnected. Once it is set in an unconditional reserve state, all signals are disabled to the opposite channel.
The Unconditionally Reserve is released only by the release command given by
the channel with exclusive connection."
)
(4) Disable Switch
During maintenance the interface functions released to channels A and B can be
inhibited by using the maintenance switch on the XCGM printed circuit board.
This disable function can be done for the two channels separately.
4.6.4 Seek Control Logic Function
The MDD M233X has four types of seek modes: Initial Seek, Return To Zero
(RTZ), Direct Seek by Tag 1, and Linear Mode.
a. Initial l5eek Mode
The Initial Seek Mode positions th~ heads at Cylinder 0 during power-up
sequence.
b. "Return To Zero Mode
The Return To Zero (RTZ) mode moves the heads to Cylinder 0, regardless of
where they are when the RTZ command is received. Return To Zero mode is
essentially equivalent to the I nitial Seek mode; therefore, they are both
referred to as the Go To Zero (GTZ) mode.
c. Direct Seek Mode
" The Direct Seek mode causes a seek to the cylinder address specified by Bus
bit 0 to 9, Tag 1 signals from the control unit.
)
B03P-4760-0111A ... 01
4·65
(4) Linear Mode
Linear mode causes the heads to track the center of the specified cylinder
after the seek operation has been completed. An Offset operation is available in the Linear mode.
When a power failure or seek malfunction has occurred on the unit, each seek
mode is reset and the heads are returned to the Landing Zone by the retract
spring in the actuator assembly.
The Seek Control Logic block diagram is shown in Figure 4-6-12.
4·66
B03P·4760·0111A ... Ol
TAG'
P-:-
'\
I
I
NCAR
ILLEGAL CAR
A
NCAR' to 512
.J
DIFFERENCE
COUNTER
NCAR1,2
~
D1 to D256
:)
V
vi
1
* CLDF
DEOZ
r
FWD
PCAR
DLT3l
\
PCARl to 512
vi
1
~
T AG3
TXPL
COMMAND
DECODER
~
I
SRTZ
I
OFSET
II
vi
OFACT
"FAULT
DRLM
"'---
\
FAULT
DETECT
/
II
GTZ
~
ty-r-
I
SEEK
MODE
LATCH
I
SKEND
SKERR
I-I-I--
SEEK
STATUS
LATCH
-
SEEK ERROR
• DETECT
vt-~
VEOZ
1\~
ONTRK
INX
[7=-
~
DIRECTION
LATCH
1\
V
r--
...,
FWDD
r
I
TMCLK/OGB/IGB2/IGB1. HDLD
~
-----v
)
STARTP
1
~
PSDR
SKC
I
URDY
ONCYL
LNMD
L
FAULT
INDICATOR
.....
.7
SPEED
CONTROL
LATCH
LSPD
Figure 4-6-12 Seek Control logic Block Diagram
B03P·4760·0111A".Ol
4·67
(1) Initial Seek Mode
The Start Pulse (STARTP) is issued to the Seek Control circuit when the spindle
rotational speed has reached its nominal value. The STARTP signal sets State
7, Go To Zero Mode (GTZM), Under Sequence (UNSa), Drive Linear Motor
(DRLM), and Forward Drive (FWDD) latches, and resets the Low Speed (LSPD)
latch.
At the start of Initial Seek, the heads move toward the outside of the disk
(forward) at high speed by enabling FWDD and disabling Low Speed (LSPD).
)
When the heads have passed through the·IGB2 zone and enter the IGBl zone,
the heads are driven toward the outside of the disk at low speed by enabling the
FWDD and LSPD signals.
When the heads have passed through IGBl zone, the Position Drive (PSDR) goes
true, which changes the target velocity to the Position signal. When the velocity
reaches the capture range, Velocity Equal to Zero (VEaZ) signal goes true which
then resets the DRLM and PSDR latches and set the Linear Mode (LNMD) latch.
When the LNMD signal goes true, it keeps the heads precisely on the center of
Cylinder 0, that is, the first ODD1-EVENl and EVEN1-EVEN2 servo track.
The first Index signal under the linear mode triggers the Settling lone-shot
(STL 1 :2.0 ms). The trailing edge of the STL 1 signal sets the Seek End
(SKEND), On Cylinder (ONCYL), and Unit Ready (URDY) latches, and also
resets the GTZM, and UNSa latches.
If the initial seek has not been performed within 4 seconds after STARTP, the
Device Check goes true, Not Ready status is true. The Device Check Clear signal
under ti1e not ready status, which is commanded from the control unit or the
Check Clear key, will cause a retry of the Initial Seek sequence.
The Return To Zero (RTZ) command, with a complete servo-off sequence and
during the Ready status, initiates the Initial Seek sequence.
)
The Go To Zero flow chart is shown in Figure 4-6-13, and the timing chart for
Initial Seek is shown in Figure 4-6-14.
4-68
B03p·4760·0111A ... Ol
)
INITIAL
SEEK
YES
FROM SHEET 3
)
Ri:SET
SET
I NTMOT
URDY
GTZM
SET
RESET
DRLM
UNSQ
SKERR
SKC
PCAR
NCAR
SKEND
ONCYL
A
B
TO SHEET 2
TO SHEET 3
)
Figure 4-6-13 .Go To Zero Flow Chart (Sheet 1 of 3)
B03P-4760-0111A ... 01
4-69
FROM SHEET 1
C?
)
YES
NO
FWDD
SET
RESET LSPD
)
SET
LNMD
RESET DRLM
PSDR
TO SHEET 3
Figure 4-6-13 Go To Zero Flow Chart (Sheet 2 of 3)
4·70
B03P-4760-011 1A ... 01
FROM SHEET 2
FROM SHEET 1
NO
RESET
RESET
SET
GTZM
UNSQ
SKC
SKEND
ONCYL
SET
ST7
GTZM
UNSQ
URDY
SKC
SKEND
ONCYl
YES
NO
NO
NO
NO
NO
NO
SET
SET
SET
SKERR
SKEND
OVSHT,
RTOGB,
RESET
or
RESET
TMOT
LATCH
GTZM
DRLM
LNMD
PSDR
FWDD
LSPD
INTMOT
DVCK
SKERR
SKEND
GTZM
DRLM
LNMD
PSDR
FWDD
LSPD
NO
END
TO SHEET 1
)
Figure 4-6-13 Go To Zero Flow Chart (Sheet 3 of 3)
B03P·4760·0111A .. ,01
4-71
- -
---.-
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t= ~
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-.....
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4·72
---
o
(/)
Z
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Cl
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N
co
t:l
co
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CI.
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(/)
CI.
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ow
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Cl
~
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....I
:.:
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z
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(/)
B03P-4760·0111A ... 01
u
~
(/)
....I
Cl
u
w
>-
z
o
Z
:.:
(/)
>Cl
c::
:::J
z
o
(/)
CI.
(2) Return To Zero Mode
The Return To Zero mode is initiated by a Return To Zero (RTZ) command
from the control unit during Ready' status and linear mode.
\
}
The RTZ command sets GTZM, DRLM, and UNSQ tatches; resets SKEND,
ONCYL,andSeek Error (SKERR) latches; and resets Present Cylinder Address
Register (PCAR), Next Cylinder Address Register (NCAR), and Head Address
Register (HARj.
At the start of GTZM, the heads move toward the center of the disk (reverse)
at high speed by disabling the FWDD and LSPD signals.
When the heads have passed through the Servo Zone and enter the IGB1 zone,
they are driven toward the center of the disk at low speed.
When the heads enter the lGB2 zone, they are driven toward the perimeter
forward) at high speed. Upon entering the 1GB 1 zone again, they are driven
forward at low speed.
The subsequent sequence is equivalent to the Initial Seek Mode.
The RTZ timing chart is shown in Figure 4-6-15.
)
)
B03P·4760·0111 A ... 01
4·73
,
K
-
~.
_I - -
-
)
I
I - f--
1-
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a:
4-74
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N
I-
0
~
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atil
N
0
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o
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z
co
co
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a:
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B03p·4760·0111A .. ,Ol
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0
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Z
t.I.I
~
til
a:
a:
t.I.I
~
til
(3) Direct Seek Mode
Direct Seek mode is initiated by activating the Tag 1 signal.
The leading edge of Tag 1 sets the bus bits 0 to 9 into the Next Cylinder Address
Register (NCAR) when the bus contains an address of less than 822.
)
When the NCAR output is not equal to the Present Cylinder Address Register
(peAR) output at the trailing edge of the Tag 1 signal (Seek Start: SEKST), a
Direct Seek is initiated.
The SEKST signal resets the ONCYL, SKEND, LNMD, latches, and also sets the
SEKM, DRLM, UNSQ, and direction latches.
NCAR1 and 2 signals are applied to the Servo.Control circuit to determine the
phase of target cylinder.
The difference between NCAR and PCAR is equal to the number of cylinders
to be moved to the desired address. The difference counter outputs D 1 to
D256, Clamp Difference (CLDF) and Difference Less Than 31 (DL T31), is sent
to the servo control circuit to generate the target velocity.
When the NCAR is greater than PCAR, the forward direction is set, and when
the NCAR is less than the PCAR, the reverse direction is set using the FWDD
signal.
When the heads start to move to the desired address, the Track Crossing Pulse
(TXPL) is sent from the servo circuit to the PCAR counter every time the servo
head crosses a cylinder. The PCAR counter is increased by the trailing edge of
the TXPL signal in the forward direction, and is decreased in the reverse direction.
When the difference is equal to zero, the Position Drive (PSD R) signal is activated and the velocity follows the position signal. When the VEaZ signal goes
true, LNMD latch is set, and DRLM and PSDR latches are reset. The successive
ONTR signal triggers the Settling 1 (STL 1) one-shot (2.0 ms). The trailing edge
of STL 1 signal sets the ONCYL and SKEND latches and reset the SEKM and
UNSQ latches.
)
If NCAR is equal to PCAR at the leading edge of Tag 1, a No Motion Seek
(NOSEK) signal is activated and triggers Settling 2 (STL2: 5~s) one-shot. The
ONCYL and SKEND signals are reset by the trailing edge of the TAG 1 signal and
then ONCYL and SKEND signals go true at the trailing edge of STL2 signal.
If an illegal cylinder address (CAR> 822) is issued from the control unit, the
trailing edge of the TAG1 signal resets the ONCYL and SKEND signals and then
sets the Seek Error (SKER R) and SKEND signals immediately. The LNMD
latch is al~o reset and the heads move to the Landing Zone.
The Direct Seek flow chart is shown in Figure 4-6-16 and the timing chart is
shown in Figure 4-6-17.
)
B03P-4760-0111A ... 01
4-7b
NO
YES
YES
SET OVCK
(CTCK1)
)
NO
NO
TO SHEET 3
YES
B
TO SHEET 3
)
Figure 4-6·16· Direct Seek Flow Chart (Sheet 1 of 3)
4·76
B03P-4 760·0111 A ... 01
A
TO SHEET 2
FROM SHEET 1
NO
TO SHEET 3
FWDD
SET
RESET
DECREASE
DIFFENCE
COUNTER
BY TXPL
)
TO SHEET 3
)
Figure 4-6·16 .Direct Seek Flow Chart (Sheet 2 of 3)
B03p·4760-0111A ... 01
4-77
FROM SHEET 2
FROM SHEET 2
FROM SHEET 1
B
NO
NO
FROM SHEET 1
NO
YES
SET
SET
SKC
ONCYL
SKEND
RESET
)
SEKGB
OVSHT
TMOT
OR
ILCYL
LATCH
SEKM
UNSa
FWOD
DRLM
LNMD
PSDR
END
Figure 4-6·16 Direct Seek Flow Chart (Sheet 3 of 3)
4·78
B03P-4760·0"lA ... O'
-' -
.....
III
.=
(.)
=
C
's
i=
~
CIS
II)
en
..
~
CIS
is
....,...
cO
)
~
~
I
:::I
.~
L.L.
-
CJ
«:
r-
N
0
UJ
Cl
-
oUl
Z
::J
-.--1!!-......f---t--+-.... --+--~
~
...J
~
Cl
...J
a:
Cl
z
Cl
Cl
~
LI.
:.::
a:
r-
z
Cl
...J
Q,
x
r-
a:
Cl
Ul
Q,
...J
N
0
UJ
>
Ul
Cl
Z
c..
o
LI.
:>u
UJ
Ul
Ul
Cl
Ul
a..
r- Z
:.::
o
Z
...J
Z
I
)
B03p·4 760·0111 A, .. 01
4·79
(4) Servo aff Mode
If a seek malfunction shown in Table 4-6-1 occurrs in the drive, all servo modes
(lNSKM, GTZM, SEKM, and LNMD) are reset and the heads move to the Landing Zone by the mechanical force of the retract spring in the actuator assembly.
)
Table 4-6-1 Seek Malfunctions
ERROR
UNIT STATUS
Initial Seek Time Out
Rotational Speed High or Low
DC voltage fault
Time Out in Any Seek Mode
Over-shoot in Linear Mode
Any Guard Band in Seek .Mode
OGB in Go To Zero Mode
Any Guard Band in Linear Mode
Illegal Cylinder (CY > 822)
Not Ready
Not Ready
Not Ready
Seek Error
Seek Error
Seek Error
Seek Error
Seek Error
Seek Error
4.6.5 Servo Circuit Function
(1) Position Sensing
This section describes the Position Sensing functions from the output of the
servo head to generating the position signal. The Position Sensing block diagram
is shown in Figure 4-6-18.
The servo data written'on the servo surface is read by the servo head, amplified
through-the Head-Preamplifier (with a nominal gain of 35), 'and applied to the
Automatic, Gain Control (AGC) amplifier on CZOM PCB. The AGC amplifier
keeps the output constant with an AGC voltage from the Summing Amplifier,
even if the AGe input varies. The AGe output is applied to a Low Pass Filter
(LPF), which attenuates the unused high frequencies, and then is amplified
by the Carrier Amplifier. The Carrier ,Amplifier issues the Servo (SERVO)
signal of four-byte interval to the Level Slice'and Peak Hold circuits.
)
4-80
B03P-4760-0111 A ... 01
..
-... ......
AGC
,--
From Sheet 2
1
I
I
I
'OX
~
I
I
CARRIER
AMPLIFIER
SERVO
To Sheet 2
I
lOY
I
S ~rvo
H ead
1 +6 V
(Vcc)
I
I
I
I
I
I
L_
lOW PASS
Fll TER ilPF)
AGC
AMPLIFIER
I
PREAMPliFIER
___
Qi~ i.n~12s!olr~
VeC.VEE
SUPPLY
-4 V
(VEE)
I
____ -.J
OJ
o
CAl
"j:,.
r-------------------------~------------I
OJ
I
6
I
!
"
o
»
'------
LEVEL
SliCE
SVSLT
SYNC PULSE
DETECT
SVPl
I
PLOSS
.
PLOSS
I
I
I
o
PHASE COMP
AND
CHARGE PUMP I-----
I
From Sheet 2
·cn
I
PL01F
0
I
i
•
I
PLO
LATCH
PlOLT
I
I
I
I
I
i
,
I
GTZ
'START
I
OR
PlOFS
f'-'
I
I
i
I
I
L
_ JI
I ________________________________________
Phase Locked Oscillator (PLO)
-""
00
To Sheet 2
I
I
I
I
(From Seek Control Logic)
VCO
!
I
,
Vc
~
i
,--..
I
I
~
LPF
AND
BUFFER
Figure 4-6-18 Position Sensing Block Diagram (Sheet 1 of 21
~
-----./'
To Sheet 2
'-../
....
Co
F rom Sheet 1
'"
",.....".v'
PLOLT- - - LSI
r------------------------------------ ---------------,
I
I
F rOIil Sheet 1
. _....... ,.
DIVIDE
COUNTER
112F
,
I
I
I
INX
IGB2. 1GB 1.0GB
L _____________________
-----
. AGC
.
r-:.J
I
I
GTI
GT2
GT3
GT4
Seek control. R/W
control circuit
V
I
Cll5
TO,Sheet 1
SHIFT REG,
AND
DECODER
TIMING
COUNTER
I
I
·CT7 I
To Sheet 1
I
------------------~
OJ
o
w
-u
J,.
"
~ F rom Sheet 1
~--;,..
'SERVO
PEAK HOLD
AND
DETECT
6.....
.....
»
(:)
tFrom Servo Cantrall
ABSVL
-\
-/
BUFFER
OIP
EIP
SUMMING
AMPLIFIER
02P
E2P
VREF
HEAD LOADED
DETECT
COMPARATOR
~
L-..,.
-
DIFFERENTIAL
AMPLIFIER
POSN
L--+
DIFFERENTIAL
AMPLIFIER
+
Figure 4·6·18 Position Sensing Block Diagram (Sheet 2 of 2)
POSO
HOLD
The SE RVO signal is converted into the Servo Slice Output (SVSL T) signal at a
TTL level. The SVSLT signal triggers a 100 ns pulse at its trailing edge and the
trailing edge of this 100 ns pulse triggers the 320-ns-long Servo Pulse Window)
(SVPWD) one-shot. The SVPWD signal separates only the Sync Pulse, that is,
it separates the Servo Pulse (SVPLS) signal from the SVSLT signal. The SVPLS
Signal is appliedto the Phase Locked Oscillator (PLO).
The leading edge of the SVPLS Signal triggers PLOSS one-shot (1.5 ~s) and sets
the PLO Latch circuit. The PLO Latch is reset by the leading edge of the Count
7 (CT7) signal, which is the output signal of the Timing Counter, and issues the
PLO Latch (PLOLT) signal to the Phase Comparator circuit and the In"dex
Guard Bands sense circuit.
The PLOSS and PLOLT signals are applied to the Phase Comparator circuit of
PLO. The Phase Comparator issues an Increase (INC) signal when phase-lead
has occurred on the VCO output, or a Decrease (DEC) signal when phase-lead
has occurred on the VCO output. The INC and DEC signals are applied to the
Charge Pump circuit which converts the phase difference into a DC-Ievle signal.
The Charge Pump circuit issues a control voltage to the Voltage Controlled
Oscillator (VCO) through the Low Pass Filter (LPF). Thus, the PLO circuit
synchronizes with the SVP LS signal and generates a one-bit cell clock, that is,
the PL01 F signal. The PL01 F signal is applied to the VFO circuit and the
Timing Counter circuit.
The Timing Counter circuit divides the PL01 F signal by two into 1/2F signal.
The 1/2F signal generates the Gate 1, 2, 3, and 4 (GTl to GT4) signals Count
15 (CT15) and the CT7 signal, which resets the PLOL T signal.
The Peak Hold circuit holds the peak of the signals (Odd 1, Even 1, Odd 2 and
Even 2) enabled by the GT1 to GT4 timing signals. The Peak-hold outputs·
(Odd 1 peak, Even 1 peak, Odd 2 peak, and Even 2 peak) are applied to the
Summing Amplifier and two Differential Amplifier circuits.
The Differential Amplifiers issue the Position Normal (POSN) signal from Odd 1
peak and Even 1 peak signals, and the Position Quadrature (POSQ) signal from
Odd 2 peak and Even 2 peak signals. The Summing Amplifier issues the AGC
Control Voltage (AGC) signal for the AGC amplifier. When the AGC signal
exceeds the reference level, the Head Loaded (HDLD) signal is issued to the
seek control circuit. The timing chart for PLO and Peak Hold is shown in Figure
4-6-19. The conversion waveform from Servo signal to dual·phase position signal
is shown in Figure 4-6-20, which is valid when the servo head is moving.
)
)
B03P-4760·0111A ... 01
4·83
On Cylinder 0
SERVO
(TRM3-11
8Vp.p
j
SVSLT
(TRM3-1SI
100 ns
ONE·SHOT
SVPWD
(TRM3-101
SVPLS
(TRM3-121
PLOSS
(TRM3-41
/ ' Phase lag
PLOLT
(TRM3-61
'CT7
'INC
'DEC
_ _ _ _ _ _ _...,.,( Phase lead
.~I1____~r
~!l____~~
__________________\fn~:~l_______________________~~~;~________________
UJ
u
u
lU
'GTl
ITRM4-21
°GT2
ITRM4-31
°GT3
ITRM4-41
"GT4
(TRM4-111
OlP
-=::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::+2 V
E1P
~::::::::::::::::~::::::::::::::::::::::::::::::::::::::::::::::::::::::::::=+2V
02P
---------------------------------------------------------------------0 V
----------________________
____
-JI~------------------------
E2P
Figure 4-6·19 PLO and Peak Hold Timing Chart
4·84
B03P-4760·0111A ... Ol
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Z
B03P-4 760-0111 A ... 01
4·85
(2) Servo Control
The block diagram of the Servo Control cir~uit after Position Sensing is shown in
Figure 4-6-21.
a. Block Description
(a) Position Signal Slice
The dual-phase position signals, POSN and POSQ which are demodulated
through Position Sensing circuitry, are applied to a level slice circuit. The
Position Signal Slice circuit then issues NGTQ and NQGTZ signals which
are applied to Position Decoder, also issues an Off-track (OFTRK) signal
which indicates that the servo head positions off from the center of each
cylinder by ±9 /.Lm.
(b) Position Decoder
The Position Decoder circuit issues the two least-significant bits of the
current cylinder address, Present Address 2 and 1 (PAR2 and PAR1),
which are decoded by the NGTQ and NQGTZ ~ignals. The Position Decoder circuit also issues Select N Non-invert (SNN), Select Q Non-invert
(SQN), Select N I "vert (SN I), and Select Q Invert (SQI) signals, which
control the Velocity Generator circuit and Fine Position Generator
circuit.
(c) Track Crossing Pulse Generator
.
The Track Crossing Pulse Generator circuit issues a 5-/.Ls-wide Track
Crossing Pulse (TXPLS), which is generated by PAR2, PAR1, and OFTRK
signals, and which is applied to the Present Cylinder Address Register
(PCAR). The PCAR counts up the TXPLS signal when Forward Drive
(FWDD) signal is true, and counts down when FWDD signal is false.
The timing chart for items (a) through (c) is shown in Figure 4-6-22.
(d) Position Signal Differentiator
The Position Signal Differenttator circuit differentiates the dual-phase
position signals, POSN and POSQ, to generate the actual velocity from the
linear portion of the position signal.
(e) Velocity Generator
The SQI, SNI, SNN, and SQN signals, which are issued from the Position
Decoder circuit, pull out the linear portion of the position signals; the
composed signal and Current Sense (CSNS) signal are then converted into
the Velocity (VEL) signal.
(f) Absolute Velocity Generator
The Absolute Velocity Generator converts the velocity signal, with
polarity, into the Absolute Velocity (ABSVL) signal.
(g) V = 0 Detector
When the Equal signal on the Clamp Gate circuit goes true, and OFTRK
signal goes false, and when the velocity is within 1 cm/second, the
Velocity Equal to Zero (V = 0) signal is issued to the Seek 'Control circuit
and then the Seek mode is changed to Linear mode by terminating Seek
operation.
The timing chart of the Velocity Generator is shown in Figure 4-6-23.
)
4·86
B03p·4760·01 1 1 A ... 01
-
POSN
POSITION
SENSING
CIRCUIT
POSITION
SIGNAL
SLICER
-c
~ Ir-----------------"
LSI
I
N+Q>O!
POSITION
OECOOER
I
N>O
PO SO
!
I
1...
-"'
SNN - SON
SNI
I
TRACK CROSS"
PAR1
iNGPULSE
T
GENERATOR
PAR2:
-06-
'
~
SHOT
"
-VEL
~SQI
8
----~
~
POSITION
SIGNAL
OIFFERENTlATOR
1
I"
VELOCITY
GENERATOR
o
-=L
W
-0
.;:.
.....
SNN
SON
SNI
SOl
o
6
~
r-----------:
A
CLAMP
GATE
~
MISCELLANEOUSGATE
GTZ,OFAC}
LNMO,PSOR
ORLM,FWO
OGT512 /
'
-
V=O
,
:'PCLMP
*FWOF
*RVSF
9
+FNPOS
SW SMOOTHER
GENERATOR
SW
r---
SMTH
r
L
*RVEN
2
C
'----
3
ffi
ON TRACK
OEl"ECTOR
ONTRK
-FNPOS
-FNPOS
t..
PTZ,LNMO
PSOR,OFACT 6
ORLM,OFR'I.l
-V
-ABSVL
*FWEN
:*EOUAL
l
V=O
OETECTOR
-
/"
1
______ JI
L
+
. FNP.OS
*MCLMP
I
I
'"L-
-ABSVL
"EQUAL
---
LSI
I
UNSQ
I
'NCAR2 I
'NCAR1 I
SEEK
CONTROL
LOGIC
CIRCUIT
ABSOLUTE
VELOCITY
GENERATOR
C
FINE
POSITION
GENERATOR
CD
o
VREF
~
CSNS
al
»
TXPL
11
V
01 TO 0256
7
~
00
.....
Figure 4-6-21 Servo Control Block Diagram (Sheet 1 of 2)
~
,,--/.
~
..
~ /
8) -VEl
~
Co
CD
7') Dl TO D256
6' GTZ
I~"- ~
DAC
6) lNMD
d~
VElOCITY
ERROR I VER
DETECT
r6' OFRV
~'PSDR
R
6
CD
3
I
W
"'0
J:,..
1
-...J
en
g....
2
6
Y
ACCElERATE
DETECT
9-ABSVl
l!9
o
I
DGT512-
lSPD
OFA6}
'EOUAl
--FNPOS
'MClMP
+12V
'PClMP
-12V
'OFACT
TXPL
ClPOS
-I
SW
SW
sw
*LNMD
POSITION
ERROR
DETECT
lOW PASS
FILTER
I
»
,rD
r--
CLAMP
POSITION
GENERATOR
SW
~
FNVEL
I ACCl
PER
SW
POWER
DRIVE
MPX
SI
SW
6
-DA
lNMD
6
'DRlM
[
o....
FINE
.12)---.-1. VElOCITY IFNVEl
GENERATOR
§)---j
114
L--I
POWER
AMPLIFIER
DRIVER
POWER
AMPLIFIER
VCM
I
Disk
~nclosure
T
CURRENT
SENSE
I
CSNS,lt1
Figure 4-6-21 Servo Control Block Diagram .Sheet 2 of 2t
VCM HEAT
DETECT
VCMHT
CY9
eya
I
POSN
POSO
NGTO
NOGTZ - - - - - '
OFTRK
I
PAR2
,.
1
/
I
PAR1
I
·SOI
·SNI
.I
I
'SNN
I
I
,
,
I
I
I
I
I
I
I
'
,
I
I
,
·SON
I
I
I
I
I
5/J.s
TXPL
-----'
Figure 4-6-22 Position Detect Timing Chart
B03PA760·0111A ... Ol
4-89
POSN
POSO
CYQ
CY2
/,/
- ---" "
Differentiated _ _~
POSN
Differentiated
POSO
'{
'SOI
·SNI
I
'SNN
Ilf I
I LfJ I
I
I
I
)
·SON
4J II 14J I
I
/
W
II
I~
W
,
(
II
IY-J
I
"
I
/
//
-VEL
-ABSVL
V=Q
Figure 4-6·23 Velocity Generator Timing Chart
B03P-4760-0111 A ... 01
ILtJ
IYJ I
Wi
lfl
I
/
/
CSNS
4-90
14J
f
If
I
W
(h) Fine Position Generator
The Fine Position Generator circuit pulls out the Itnear portion, that is,
the Fine Position (FNPOS) signal from the POSN and POSQ signals
controlled by SQI, SNI, SNN, and SQN signals. The FNPOS signal is
applied to the Smoother, On Track Detector, and Clamp Position Detector circuits.
( i) Smoother Generator
The Smoother Generator circuit polarizes the FNPOS (the polarity of
signal which is in accord with the head movement direction) and issues the
Smoother (SMTH) signal. TheSMTH signal makes the DA signal smooth
through the Function Generator circuit (see item (I), below). When the
difference between NCAR and PCAR, however, is greater than 512 during
Direct Seek mode, or GTZ mode is activated then the SMTH signal is
deactivated.
'
(j) On Track Detector
The On Track Detector senses the servo head positions on the center of
each cylinder within ±5/lm and issues an On Track (ONTRK) signal to
seek control and fault detect logics.
The timing chart of Fine Position Generator is shown in Figure 4-6-24.
}
)
B03P-4760-0111A ... Ol
4-.91
, ,----CY2
/1
/'
'501
If
/I
'SNI
/(
JI
'SNN
·SON
f(
),
-FNPOS---/
FWDD -~
SMTH
ONTRK
Figure 4-6-24 Fine Position Generator Timing Chart
4·92
Ii
l.
B03P-4 760-0111 A ... 01
(k) DA Converter
The DA Converter DAC circuit generates the target velocity during Direct
Seek or GTZ operations. When the Direct Seek operation is performed,
the Difference Counter bits 01 to 0256 are applied to the DAC at the
beginning of the seek operation. When the servo head passes through a
cylinder, the TXPlS signal is issued and it decreases the Difference
Counter. When the Difference Counter output is equal to or greater than
512, the D1 to 0256 signal is clamped to 511 and the DAC output is
adjusted to be -7.3V.
)
When the GTZ operation is performed, GTZ and lSPD signals set a target
velocity through the DAC.
When the Offset operation is performed, OFACT and OFRVS signals set
the offset voltage to a value equivalent to ±3 ~m from the center of
cylinder. The DAC output, -DA signal, is applied to the Function Generator and Clamp Position circuits.
(I) Function Generator
When the Difference Counter output is less than 511, the Function Generator circuit converts the DAC output into a smooth waveform by adding
the SMTH signal. The Function Generator issues a Function (FUNC)
signal which is the optimum deceleration curve for positioning time and
the deceleration current profile.
When the servo control is changed to deceleration from acceleration, the
Function Generator adds tlie integrated ACCl signal to the FUNC signal
to avoid an excessive force to the actuator.
(m) Velocity Error Detector
The'Velocity Error Detector circuit issues the Velocity Error (VER)
signal, which is applied to the Power Amplifier, after comparing a target
velocity (FUNC) signal and actual velocity (VEL) signal. At the termination of Seek operation, the Clamped Position (ClPOS) signal is applied
to the Velocity Error Detector instead of the FUNC signal, which is
activated by the PSDR signal.
(n) Accelerate Detector
The Accelerate Detector output, that is, the Accelerate (ACCl) signal, is
set when the TXP l signal is equal to the DGT512 signal. The ACC l
signal is applied to the Function Generator circuit.
The timing chart of the Target Velocity Generator, for a Direct Seek
operation, is shown in Figure 4-6-25, and the timing chart for a GTZ
operation is shown in Figure 4-6-26.
B03PA760·0111A ... 01
4·93
)
POSN
POSO
-VEL
OV
",--""'-0 V
-DA
SMTH
)
TXPLS
FUNC
FWDD
I I II I
I I
'II
II
-.J_~~_oV
/'1
~-------------------------
:'l
VER
I'
"
r
Figure 4-6-25 Direct Seek Target Velocity Generator
B03P-4 760-0111 A ... 01
l
;::::J
ov
POS
)
-VEL----'----------------------------4r-----------------------------,--------OV
VER
......---OV
Figure 4-6·26 GTZ Target Velocity Generator
)
/
B03P-4760-0111A ... Ol
4·95
(p) Clamp Gate
_
The Clamp Gate circuit issues Minus Clamp Position (MCLMP), Plus Clamp
Position (PCLMP) and Equal (EQUAL) signals through the adder circuit,
which compares the two least-significant bits (NCAR2 and 1) of the target
cylinder (NCAR2 and NCAR 1) with PAR2. and PAR 1 signals from the
Position Decoder circuit.
(q) Clamp 'Position Generator
The Clamp Position Generator holds the position signal at specified levels
when the servo head is positioned within three cylinders of the target
cylinder address specified by the two least-significant bits of NCAR and
PAR. This extends the area controlled by the servo circuit.
The PCLMP signal sets the Calmped Position Signal (CLPOS) to +2 V, the
MCLMP is set to -2 V, and the EQUAL signal enables the FNPOS signaton
the C LPOS signal.
The CLPOS signal is applied to the Velocity Err9r Detector circuit when
the PSDR signal goes true atthe termination of Seek operation, and is then
applied to Low Pass Filter (LPF) when the servo head settles on the
specified cylinder.
The timing chart of Clamp Position is shown in Figure 4-6-27 ..
)
4·96
B03P4760·011 1A ... 01
CYQ
POSN
POSO
_
dI:ID..-.
CY2
GOlD"""",'
---.,
I
I
NCAR2
I
NCAR1
~
I I
I
I
PAR2
I
I
PAR1
I I I I I I I
~
I I I
I
UI
IlJSfl
I I I
-U
°MCLMP
I I I
I I
I I I I I I
I
I I
I I II II I I
*EOUALJU
·*PCLMP
I
I
I I I I I
I
I
I
I IWI I
I
UNSO
I
I
I I
I I I
I I
U
U
I I I
I I
I I I I
I
I
u
I I
I
I
I
I
I
I I
0
I
U
I
I I
I
I
I
I
I.
I
I
I
)
U
I I
-FNPOS ---++--l--f-t-jf-H-t+++++-t-+-+~---Io;;:--++-t--T+-t-H:-H-t-H----
+2 V
CLPOS
-
.... ---H--t---++-+---~---'--t--++---+--+-.--
Figure 4-6-27 Clamp Position Timing Chart
B03P-4760-0111A ... 01
4-97
(r) Low Pass Filter (LPF)
The servo circuits form a feed-back loop during track following after a
Seek operation using the position signal recovered from the servo head.
The LPF circuit attenuates unused high frequencies.
(s) Position Error Detector
The Position Error Detector pulls out the phase-compensated Position
Error (PER) signal.required for the feed-back loop during track following.
The PER signal is composed of FNVEL (phase-compensating) signal, and
an integrated position signal; improves stiffness and track following characteristics of lower frequencies.
(t) Power Drive Multiplexer
The Power Drive Multiplexer circuit passes through either the VER signal,
by activating DR LM 'signal during Direct seek or GTZ operation, or the
PER signal, by activating the LNMD signal during track following sequence.
(u) Power Amplifier Driver
The Power Amplifier Driver circuit drives the last stage of the power
amplifier. This circuit controls the base current to the power transistors
by comparing the input signal with the feed-back signal from the last-stage
transistor current.
(v) Power Amplifier
The Power Amplifier circuit is a current amplifier which drives the coil of
the Voice Coil Motor (VCM). Four transistors compose H-type circuit.
(w) Current Sense
The Current Sense circuit detects the VCM coil current through the
voltage bleeder resistors. The coil current is amplified by the differential
mode, and then the Current Sense (CSNS) signal is issued.
(x) VCM Heat Detect
The VCM Heat Detect circuit senses an abnormal current flowing through
the VCM coil or DC Motor windings.
)
The coil.current of the DC Motor windings current is integrated and converted into the VCM Heat Detect (VCMHT) signal.
b. Direct Seek Servo Control
During a Direct Seek with servo control, the servo head is driven high speed,
so that the actual velocity pulled out from the position signal through the
servo head is equal to the target velocity controlled by the Difference
Counter. Whenever the servo head has passed through each cylinder, th.e
target velocity is decreased for optimum speed control. The Direct Seek
signal flow is shol/Vn in Figure 4-6·28.
c. GTZ Servo Control
Wherever the head is positioned, GTZ Servo Control returns the head to
Cylinder O. The target velocity is given by the specified velocity, that is,
high speed is 7 cm/second and low speed is 2 cm/second.
The GTZ signal flow is shown in Figure 4-6-29.
d. Linear Mode Servo Control
When the servo head is positioned within capture distance from the specified
cylinder, the Servo Control mode is changed to Linear mode. During Linear
mod~ jtrack following), the feed-back loop is formed to minimize the
Position Error Signal.
When an Offset operation is performed, the offset voltage is applied to the
Position Error signal through the DAC.
The Linear mode signal flow is shown in Figure 4-6·30.
4·98
B03P-4760-Q111A ... 01
_L
OFTRK
LSI
r-------------------------'
POSN
POSITION
SENSING
CIRCUIT
I
N+O>O~
I
N >0
l
POSITION
SENSE
SLICER
PO SO
POSITION
DECODER
PARI
PAR2
~L---_----------SNN
SON
SNI
t-
TRA
CROSSING
PULSE
GENERATOR
~
-VEl
VELOCITY
GENERATOR
r-:
TXPL
__~ __ _
B
~
POSITION
SIGNAL
DIFFERENTIATOR
~
I ~r-----~------------.·18
VREF
ABSOLUTE
VELOCITY
GENERATOR
-c..-J+
-ABSVL
V=O
DETECTOR
V=o
~L-I_ _-..J
12)
CSNS
•I
SNN
SON
SNI
ID
o
~SOI
W
"'0
.i>.
~
.......
Ol
FINE
POSITION
GENERATOR
o
6
»
o
SEEK
CONTROL
LOGIC
CIRCUIT
co
LSI
r- -----------,
-!..
~
UN~O'
*NCAR2 ,
*NCAR! ,
L
CLAMP
GATE
I"MCLMP
I
,·PCI,.MP
, 2
I*EOUAL
"CJ3
TZ'
~
OFACT,
LNMD,
PSDR,
DRLM,
FWD,
DGT512
~
GTZ, lNM[l
:;s~':.i,06:~J 116
r
01 TO 0256. 17
"'"
'Ii:>
10
Figure 4-6-28 Direct Seek Signal Flow (Sheet 1 of 2)
~
'---"
,--./
------~
.. ~~~-----------------------------------------------------
'--u.,,'
f....
a
a
'FWOF
4
,
01 TO 0256
!)
GTl
OAC
lNMO
i
10
.--
0
FUNCTION
GENERATOR
SMTH
~
FUNC
-FUNC
~
ACCl
~RV
'PSOR
J>.
"
m
a
6
14
"'- SW
t-SW
t--
CLAMP
PQSITION)F
GENERATO
FNVEl
>----
0
'lNMD
9
POSITION
ERROR
DETECT
lOW PASS
Fil TER
PER
L H
SW
t-lNMO
-DA
6
SW
r-c
"DRlM
6
t--
r
FINE
VElOCITY
GENERATOR FNVEl 14
L
\j
POWER
AMPLIFIER
DRIVER
POWER
AMPLIFIER
I
I
at the direct seak terminated.
"V
SI
-
~
y
I
POWER
DRIVE
MPX
SW
o
:/
ACCl
9
~ SW
....
»
ACCELERATE
DETECT
-ABSVl DGT512-
0
~
-
SW
~
OFACTl
"tJ
•
I
VElOCITY
ERROR
DETECT
f--
TXPl
ClPOS
ro
w
SW
I
lSPO
a
SW
f--
I
I
6
'EQUAL
-FNPOS
'MClMP
+12V
'prl MP
-12V
'OFACT
VEL
8
VCM
Disk
I!nclosure
T
I
CURRENT
SENSE
VCM HEAT
DETECT
CSNS
12
~-----~
Figure 4-6-28 Direct Seek Signal Flow ISheet 2 of 21
VCMHT
O::~K_______
lSI
r
POSN
POSITION
SENSING
CIRCUIT
I
POSITION
SENSE
SLICER
POSO.
i
.
I
POSITION
DECODER
N+O>O!
LI-:-:-=i-,r=--~S~-~--- _,-_J -
I
,01
r-a
...---.r
~
POSITION
SiGNAL
DIFFERENTIATOR
12)
CSNS
PARI
PAR2 T
N>O
..
L.___ _
clJ@-
~~I
~
VELOCITY
GENERATOR
r
~~=:::::::::::;---'
SNN
SON
SNI
.. ,
OJ
o
w
~O~
-u
l.
--.I
m
FINE
POSITION
GENERATOR
o
6
»
o
r-----------~"MClMP
SEEK
CONTROL
lOGIC
CIRCUIT
I
~--:-:-'~
UNSO
':
"NCAR2 I
"NCARI II
CLAMP
GA TE
I
: 'PCLMP
2
• ( C J3
MISCELlANEOUS
GATES
--'
GTZ.lNMD
PSDR.OFACT
DRlM,OFRV
,
Dl to D256
f"
16
.17
~
o
Figure 4-6-29 GTZ Sign" Flow (Sheet 1 of 2)
~
,--,'
----/
"---'
f'
VEL
B )>----.,
y"FWDF
-'.
~
~ *RVSF
~D256_
GTZ
6)
6)
DAC
-I
lNMD
10) SMTH
·1
,...
D
)
ACll
FUNCTION
GENERATOR
-FUNC
.
IIdtl
L--'-_
_ _---I
-.---.-~SW. v~~~glriY
:~ SW
__-..J.I_
6 ') 'PSDR
ClPOS
R
I;
FUNC
h'
I .1
6) OFRV
5
-ABSVL
I VER
SW
q
TXPL:J
lSPD
DETECT
ACCElERATE
DETECT
DGT512--
ACCL
1---1
·r D
9
OFACTj
14
FNVEL
6
*LNMD
[U
o
W
3
"'0
en
...
»
-'
CLAMP
POSITION
-...!...!A':'-~--:-I"1 SW ENERATO~
.1>0
g'"
SW
sw
2
6>
I
'OFACT
_I
LOW PASS
FILTER
.~
a
(g>-----I GENERATOR
VELOCITY I FNVEL~
IFINE
13>----1
ERROR
DETECT
~
fdt
LNMD
6)>-.......,.................................~
-DA
L
l
POWER
AMPLIFIER
DRIVER
')
-y
T
I
Note:
PE~.r:J
POSITION
6
rlswi
*DRLM
POWER
DRIVE
MPX
Sl
r
POWER
AMPLIFIER
~
L'---r--....---'
VCM
Disk
Enclosure
T
CURRENT
SENSE
I
CSNS
signal is activated at the GTZ terminated.
Figure 4·6·29 GTZ Signal Flow (Sheet 2 of 2»
_ 112
VCM HEAT
DETECT
VCMHT
OFTRK
POSITION
SENSING
CIRCUIT
r ~O~I~I~~------L
®
SI
POSN
POSITION
SENSE
SLICER
POSO
N + 0 > 0:
DECODER
I
I
N>O
PAR2 1
lc
TRACK
CROSSING
PULSE
GENERATOR
,
-00
1- SNN
SON
SNI
• SOl
f---
PAR1
-VEL
8
- ~--~
POSITION
SIGNAL
DIFFERENTIATOR
12
VELOCITY
GENERATOR
r
~
CSNS
OJ
VREF
OFTRK
-
.....
m
~
o
A
r_~S~ ________ :l
i
SEEK
CONTROL
LOGIC
CIRCUIT
UNSO
I
I
·NCAR2
*NCARl
I
I
I
CLAMP
GA TE
I
-V
'--~
+FNPOS
SW SMOOTHER
GENERI-ATOR
SMTH _r
L
SW
*RVEN
C
L....,.
3
ffi
*RVSF
ONTRK
-FNPOS
t..
GTZ.lNMD
PSDA.DFACT
DAlM.OFAV
ON TRACK
DETECTOR
-FNPOS
11
6
V
7
Figure 4-6-30 Linear Mode Signal Flow (Sheet 1 of
w
r
2
01 TO 0256
f"
a
-ABSVL
9
~
1
,
: ·PCLMP
I
I
MISCELLANEOUS
GATES
I
*FWEN
L------------J*FWDF
GTZ
\
OFACT
LNMD.·
PSDR.
DRLM.
FWD,
DGT512
\/=0
~
FNPOS
·MCLMP
~·EOUAL
I
V=O
DETECTOR
-
V
-"
»'
+
C
FINE
POSITION
GENERATOR
a
6
-ABSVL
·EOUAL
~O~~
~
L--
ABSOLUTE
VELOCiTY
GENERATOR
®
SNN
SON
SNI
a
w
"tl
----!3
TXPL
SHOT
'-_/
21
'--"
f"
'FWDF
VEL
8
4
~
o
-""
'RVSF
5
~ 01 TO 0256
GTZ
i
LNMD
DAC
i
10
SMTH
ACCL
r-
0
OFRV
FUNCTION
GENERATOR
FUNC
'-'
-FUNC
"U
f;l
~
~
W
-0
~
-.,J
0>
o
6
~
SW
'PSDR
6
OJ
SW
VELOCITY
ERROR
DETECT
~f--
I
o
SW
>--
LSI'D
OFACT
c>~
'EOUAL
-FNPOS
'MCLMT
./ t12V
'" 'PCLMP
-12V
'OFACT
>
»
SW
f-SW
, f--
CLAMP
POSITION
CSW_DA
.
6
o
ACCL
0
'LNMD
FNVEl
6
LOW PASS
FIL TER
SW GENERAT01
_Cf--
DGT512~
-ABSVL
9
14
ACCELERATE
DETECT
L-
.
"
f(
<:
TXPL
CLPOS
POSITION
ERROR
DETECT
C
~T
LNMD
PER
SW
&TSW
6
-
'DRLM
POWER
DRiVE
MPX
'->
SI
--1
-
>--------0-
FINE
VElOCITY
GENERATOR·
>
I
I
L.
t..
POWER
AMPLIFIER
DRIVER
'\
j
POWER
AMPLIFIER
~
VCM
Disk
Eilclosure
-y
T
I
I
I
CURRENT
SENSE
VCM HEAT
DETECT
CSNS
12
signal.
Figure 4-6-30 Linear Mode Signal Flow ISheet 2 of 2)
VCMHT
4.6.6 Index/Sector/Guard Band Generate Function
(1) Index Detect
As described in the position sensing' discussion, the servo signal contains missing
Index Bits. The servo pulse (SVPL) is applied to the PLO which outputs a two
bit cell clock (PLO%F).
The PLO latch (PLOLT) signal is set by the leading edge of the SVPL signal and
reset by the leading edge of Count 7 (CT7). It is applied to a shift register in
the LSI (MB15238) and clocked by the positive-going edge of the CT7signal.
The shift register outputs are decoded, and then the Index (lNX) signal, two
Inner Guard Band pulse (lGB2P and IGBl P) signals, and the Outer Guard Band
pulse (OGBP) signals are detected by the combination of the decoder outputs.
The block diagram of Index and Guard Band pattern detect is shown in Figure
4·6·31. The timing chart of the Index signal processing is shown in Figure 4·6·32.
)
)
B03p·4760·0111A ... 01
4·105 .
f>
~
~
o
-
-;,~u
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -,
m
I
I
SV SLT
SYNCHRONIZED
SIGNAL
DETECTION 1-----0
--
I
I
PLO SIGNAL
SHOT
I
I
PHASE
COMPARATOR
I
r---
CHARGE
PUMP
LOW PASS
FILTER
f--
I
VCO
-
I
I
r---
I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I
I
I
~
'---
r-----------w
I
~
I
o
.j:..
~
m
o
6
....
~
»
o
I
I
I
-------- - - - - -
----------- -
-
-
-
- -
-
- - -
-
-
-
--
- - - - -,
-
i
LSI
(MB152381
I
I
PLO LATCH
I--
2 BYTCl
DIVIDE
COUNTER
'---------
.---
!
I
I
I
INX
!
AND
I
I
I
I
I
I
I
I
I
I
~
I
TIMING
COUNTER
A
SHIFT
REGISTER
I--
vi
~
DECORDER
-f\
-V
~ !GBf~
___
PATTERN
DETECTION
I
IGBP1
CGBP
MSDT
~
-~-------
I.
I
I
I
I
I
I
I
I
I
I
L ___ _
_
I
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ .J
Figure 4-6-31 Index/Guard Band Patterns Detect Block Diagram
PLO%F
INDEX PATTERN
SVPLS
eT7 .
'PLOL T
I /
OJ
o
w
.;,.
"
b
1·
/-!
SHIFT
REGISTER
OUTPUT
'-l
0>
o
6
_ _ _ _ _ _ _ _---'r~l
»
r
o
l~
INX (48)
__________________
MSDT
____________---'r~~~
INX (28)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'
n
': 0: normal bit
L
-,L--_____
_ _ _ _ _ _ _ _ _ _ _ _ _ _-:./_ _;-I.__
1: missing bit
88 Cell
f>
~
o
'-l
Figure 4-6-32 Index Detect Timing Chart
'-.../
~.
(2) Guard Band Detect
As described in Section 4.3.3, each guard band has a missing I ndex bit. When the
servo head is located on any guard band track, the servo PLO circuit develops
IGB2P, IGB1P, or OGBP and missing detect (MSDT) signals as shown in Figure
4-6-33.
The first pulse of the Guard Band Pu Ise sets the first flip-flop, and simultaneously
the MSDT signal loads 187 (decimal) on the Guard Band Reset counter clocked
by the four-byte interval Count 15 (CT15) signal. When the second pulse is
applied before the Guard Reset Counter issue the Reset Guard Band (RSTGB)
signal, the second pulse sets the second flip-flop; Guard Band signal (IGB2, IGBl
or OGB) is then issued to the seek control logic.
The output of each Guard Band latch is reset by a RSTGB signal. when the servo
head is not located over a guard band track and the Guard Band Reset counter
counts up to 255 (decimal).
The two stages of the flip-flop prevent the Guard Band signal from improper
detection of the Guard Band signals caused by media flaws.
)
4-108
B03P-4760·0111A ... Ol
--------
----- --
o
o
1::
..c:
'"
(,,)
C)
c
'E
i=
....u
$
G>
C
II
:;
a..
0
"C
Iii
al
...
0
'C
'"
::I
~
0
I'll
I'll
cD
~
...
G>
::I
.21
~
o
o
Qi
u
CD
~~-------------'vr------------'/
a:l
U1
lJ
B03p·4760-0111A ... Ol
3B4
l
\
j
I
I
I
I
1
HEAD
ADDRESS
REGISTER
HARl
HAR2
HRR4
~F!i
FF
WRITE DATA
DRIVER
,
I
I
HEAD
SELECT
DRIVER
,
HIC
t
I
I
I
I
I
l
,
I
r-t-I
I
I
1-1-I
I
CHIP
SELECT
DRIVER
K
, I hi
HIC
I
I
I
I
J~
f-\
hi
DATA
HEAD
B.9
DATA
HEAD
4107
~l
I
I
I
I
I
I
I
I
I
I
WRITE
CURRENT
I
I
,
I
I
I
t
I
I
I
I
I
I
I
I
I
I
I
I
I
UNSAFE
DETECT
I
M
11 hi
I
r-----J
o
SERVO
I---- HEAD
HIC
I
OJ
f---
I
I
J
WCLK
PRE
AMP
-------,
I
r---
I
I
~.:
flO
----------
I
I
DATA
HEAD
0103
I
I
I
,
I '
I ,
I
L__________ .!..n:e~a..':e5~~t~'~':..a~~~_='~e~~e::o~'2 ____ 1 _____ ~~Io.!! P~~ ______ J_ ~o!,~c:.!0!: _1 __ p'~K_ E_N~~O~':!F!.E____
Figure 4-6-40 Write Operation Block Diagram
J
(4) Write Compensation
When the bit density (BPI) is high on a disk surface, and a read operation is performed, a peak shift phenomenon appears, which tends to widen the narrow part of
the bit spacing because of mutual magnetic interference of the bits. When such a
phenomenon appears, reading of the data will deviate from the correct bit spacing,
causing errors. The write compensation circuit measures this peak shift beforehand
so the data is written by shifting the peak in the opposite direction of the peak shift
appearing during the read operation.
The N RZ write data (WDAT) sent from the control unit is clocked by the positivegoing edge of the WCLK signal. It is then synchronized with the internal one-bit
cell clock (CLKA) which is issued from the sync decision window circuit, comparing
the phase difference between *WCLK and VF02F by enabling the Write Enable
(WENB) signal.
.
The N RZ data synchronized with the internal clock is applied to 2-7 encoder circuit.
The output of the 2-7 encoder circuit is applied to six-bit shift register. Each output
of the six-bit shift register is applied to a write compensation circuit and then converted into 2-7 data pulse train with write compensation according to the truth table
(as shown in Table 4-6-3). The preshift timing of write compensation is defined by
Early (EY), on-Time (aT) and Late (L T) signals.
The block diagram and timing chart are given in Figure 4-6-41 and Figure 4-642.
Table 4-6-3 Write Compensation Truth Table
REGISTER STATUS
ENCWD
WRITE CaMP
ESR5
EV
2·7
aT
LT
DT
1
1
1
1
1
0
1
0
0
1
1
1
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
*
.
Note:
ESR2
EV:
aT:
L T:
DT:
.
*
.
1
1
)
0
Early Pulse
On·Time Pulse
Late Pulse
Data Pulse
)
B03P-4 760-0111 A ... 01
.
4-117
'---"
........f"
B
en
IveOI
t------- --------- ---- -
--- - ---
- - "'2
---
-
~
SYNC
DECISION t - - CLKA
WINDOW
2F
eLKB
o _FF
WelK
~
FF
t--
SYNGT
.
m
o
W
"lJ
J,..
.....
WE NB
------- -_._----
m
o
6
....
»
WD AT
L
FF
2-7
ENCODER
6- BIT SHIFT
REGISTER
ESR5
MPX
o
ESR2
ENCWD
DELAY
LVC
Figure 4-6-41 2-7 Coding ,and Write Compensation Block Diagram
_ _ "WOP
>LJ.J
I
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I
I
I
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I
/
I
I
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/
I
/
I
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/
I
/
I-
I
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t:ra
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J::.
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c
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B03P-4760·0111A ... 01
4·119
- (5) Read Operation
A read operation is initiated by enabling Tag 3 and Bus 1 (Read Gate: RG). The
analog read circuitry is enabled by disabling Write Enable (WEN B).
)
The OX, OY HIC (Head IC)outputs are applied to the Read/Write Bus Switch
IC (MB4316), amplified, and then sent to LPF (Low Pass Filter) circuit as shown
in Figure 4·6-43.
ox
To Head
Ie
DY
r;mE
I
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DRIVER
r-
~---I
----~--------I
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TO
LPF
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.WENS
L __________
~~~~~wi~
__________
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____ J
Figure 4-6-43 Read Write Bus Switch
)
The LPF attenuates the high-frequency noise; its output is then applied to the
Automatic Gain Control (AGe) -circuit.
The AGC circuit develops the control voltage to the AGC amplifier and holds
AGC output amplitude (200 mVp-p) at a constant level. The output of the
AGC amplifier is amplified to 2.0 Vp-p, and sent to the Pulse Shaper circuit.
After going false at WENB, the read circuit is activated; however, a read-transient which is caused by the DC unbalance of the read pre-amplifier will occur.
The profile of read after write transient from is shown in Figure 4-6-44.
)
4-120
B03P4760-0111A ... 01
WENS - - - - - _ . . . ,
READP~0;.~~~ -------~nMlliWVlm
( r---
j
AGe
OUTPUT
\
r
t
T
2.0 V pop
y
~
Figure 4-6-44 AGe Squelch Function
The AGe output signal is applied to Pulse Shaper which is the analog-todigital convertor circuit.
The block diagram is shown in Figure 4-6-45.
The output of PUlse Shaper which is Raw Data (RAWDT), is sent to the
VFO circuit.
.
)
)
B03p·4760·0111A ... 01
4·121
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0-3
J---t\
r---v
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---- +---
A/W Bus
Switch
IMB43161
---1-----;----_._.-
Data
Head
4-7
OJ
a
w
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en
a
6
Data
Head
8-9
~
n
~
n
AMP
IMB4311I
Hie
WENB
-------- -
_.
-
---------_ ...-- ------------
.---- --
.
---
-
Hie
_._--TDa."'l.1h
TDt..4'ln")
_____~i~!,
»
a.....
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Pulse shaper
I----
+AAWDT
---.-----1 lVC
ToVFO
---+ - ----
I--____ =AAWDT
-"._-- ---------
IMB431211
Slice Voltage
Figure 4-6-45 Read Operation Block Diagram
_._-
--1 - -----B
--J-- ----~
TP6
-
1200mV p-pl
I
f----. e----
TP5
1------ -.-...•
I
1--
--_._-
AGe
IMB43031
~
lPF
1
f2.0Vp-pl
./'
/'
4.6.9 VFO
(1) VFO and Data Separator
The Variable Frequency Oscillator (VFO) circuit synchronizes with a
PLO%F signal from the servo track during Not-Read operation and with the
Raw Data (RAWDT) signal, from the data track, during a read operation.
The block diagram of the VFO and Data Separator circuits is shown in
Figure 4-6-46.
)
The VFO are composed of the following circuit.
• VFO Input Multiplexer
• Time-Margin Measurement (TMG) One-Short
• Reference One-Shot
• Phase-compare Latch
• Phase Comparator and Charge Pump
• Low-Pass Filterand Buffer
• Voltage-Controlled Oscillator (VCO)
)
)
B03P-4 760-0111 A ... 01
4-123
----,--_....
'-..-/
f'
..:...
TP7
N
"""
TP10
VFOINPUT
PLOY,F
-F
---
--
- - - - - - - - - < 0 AND
RAWDT
SVMD
~
TMG
ONE-SHOT
AND
INH
0
:;:>
_CER
DR
DTiNI
DTlN2
- - - - - - - ---I--
REFERENCE
ONE-SHOT REFP
8NS
,-----
'--
PHASE-CMP
CHARGEPUMP
lPF and
BUFFER
Vc
VCO
i---
V
'---TP8
PHASE
COMPARE
9DLDT
r---
PCLO
f---
LATCH
-- 2FClK
ro
OFS
a
~ VF
.l:>
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- -----
Fl TSO
a
6
»
a
,
DV
+VF02F
.
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To Decoder
~_ _ _ _ _ _ _ _ _ _ _ _ _ _~~V~Q~_F____
'--_ _ _--.J
T'6
L....-
+2
f---
.
DTWD
L
DATA
WINDOW
+SPDT
DV
•
To Decoder
-SPOT
Figure 4-6-46 VFO Block Diagram
a. VFO Input Multiplexer
The VFO input multiplexer controls the VFO input. During an initial seek operation or a RTZ operation, this circuit inhibits an input of data into the VFO
circuit by enabling the Filter Squelch (FLTSO) signal. This causes the VCO to
oscillate at a free-running frequency. After an initial seek operation or a RTZ
operation, the VFO Input multiplexer controls the transmission of the PLO%F
or RAWDT signals into the VFO circuit.
.
During a non-read operation, the PLO%Fsignai is applied to the VFO circuits by
the enabling of the Servo Mode (SVMD) signal. During a read operation, the
RAWDT signal is applied to the VFO circuits by disabling the SVMD signal. The
VFO input multiplexer output, Data Input 1 (DTIN1), is applied to the TMG
One-shot circuit.
b. TMG One-shot
The TMG One-shot circuit issues a Data Input 2 (DTIN2) signal to the Phase
Comparator, and Reference One Shot circuit. It also issues Delayed Data
(DLDT) signal to the Data Window circuit. The timing relation between DTIN2
and DLDT signals adjusted by potentiometer RV2 determines the read margin.
(Refer to Figure 4-6-48)
c. Reference One-shot
The leading edge of the DTI N2 signal triggers the Reference One-shot, which
issues a 8 ns Reference Pulse (REFP) signal to the Phase Comparator Charge
Pump circuit.
d. Phase-Compare Latch
The leading edge of the DTI N2 aignal sets the Phase-Compare Latch and the
negative-going edge of -2F Clock (-2F CLK) resets it. The Phase-Compare
Latch issues a Phase-Compare Latch Output (PCLO) signal to the Phase_ Comparator Charge Pump c i r c u i t . e. Phase Comparator and Charge Pump
The Phase Comparator Charge Pump circuit issues a Decreas frequency (DEC)
signal when the VFO input phase is lagging, and an Increase frequency (INC)
signal when the VFO input phase is leading, comparing the phases between
DTI N2 signal and PCLO signal.
f.
)
The I NC or DEC signal drives the constant-current circuit to charge or discharge
the filter circuit (LPF and Buffer).
LPF and Buffer
The charge pump output is applied to a Low Pass Filter (LPF) and converted
into DC voltage to control the VCO. During an initial seek operation or RTZ
operation, the F L TSO signal clamps the charge pump output to OV to
recalibrate the VFO function.
During an initial data read operation, a VFO Fast-Sync (VFOFS) signal is issued
to the VFO circuit which increases the loop gain of the VFO circuit to widen the
pull-in range, and to shorten the pull-in time for synchronization to the RAWDT
signal. At termination of the data read operation, the same function is activated
for synchronization with the PLO%F signal.
The LPF and Buffer output is applied to two stages of an emitter-follower circuit. It controls the VCO frequency as a Control Voltage (Vc) signal.
g. Voltage Controlled Oscillator
The VCO issues ECL level output. Refer to Table 8.3.3.
I
/
B03P-4760-0111Aoo.Ol
.
4-125
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B03P-4760·0111 A ... Ol
N
lII:
During a Non-read operation, the VFO circuit synchronizes with the PLO output, PLO%F, and generates a VFO clock (VFOCKL). In Hard Sector mode, at
the beginning of a read operation, Read Gate is applied to the R G True Detect
circuit and is docked by the positive-going edge of the *CLK2 signal.
A rise read gate (RRG) signal, which is an output of the RG True Detect circuit,
is applied to 6 byte sh ift register. Its output then Load 20 on the lock-to-data
counter to generate a 6~byte lock-to-data (LDATA) signal. The leading edge of
the LDATA signal resets Servo Mode (SVMD) so that the VFO circuit synchronizes with RAWDT. Refer to Figure 4~6-51"
At the end of the Read Gate signal, a half byte Set Lock-To-PLO (SLPLO) signal
is issued and applied to the Lock-To-PLO Counter to generate a 6-byte Lock To
PLO (LPLO) signal. The LPLO signal sets Servo Mode (SVMD) so that the VFO
circuit synchronizes with PLO%F.
The LDATA and LPLO signals are converted into the VFO Fast-sync (VOFS)
signal and applied to the VFO LPF circuit to decrease the time constant of the
LPF. This promotes faster synchronization of the VFO circuit with RAWDT or
PLO%F.
)
)
B03P-4760-0111A. .. Ol
4-131
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(3) 2·7 Decoder
The 2·7 decoder converts the 2-7 data into NRZ data.
The 2-7 data synchronized with 2F clock sent from VFO circuit is input to an eightbit shift register, then sent to a decoder in which the 2-7 data is converted to N RZ
data according to the conversion table listed in Table 4·6·2.
A read command starts the decoder detecting all 1 gap data. When this data is
detected, the 2F clock is toggled to VFO clock (VFOCLK) to transfer the data. The
2-7 data is converted to NRZ data by gating VFOCLK. The NRZ data synchronized
with VFOCLK is sent to the controller.
Figure 4-6-52 shows the abbreviated block diagram of the 2~7 decoder.
)
)
B03p·4760·0111A ... 01
. 4·133
f"
w
~
.".
2F REAO Clock
From VFO
Clocked Read Data
8-bit Shift
Register
ALL "I"
Detector
12 - 71
Read gate
Lock to data
m
a
-
~
VFOCLK
w
~
.i:.
-.j
01
a
6
~
~
Gate Circuit
SYNC FF
~
RDAT (NRZ
a
A
VFOIF
l
I--~
A
OR
R/W Clock.
Generaior
Figure 4-6-52 2-7 Decoder Block Diagram
RWCLK
.
)
,
)
Section 5,
Troubleshooting Guide
)
5. TROUBLESHOOTING GUIDE
5.1 INTRODUCTION
This section will contain troubleshooting flow charts arranged according to the error
status on the disk unit and control unit.
Note: Before any operation is attempted, maintenance personnel should read carefully Section 6 (Maintenance) and fully understand the details of the procedures and tools required.
Check the following items in list before applying power to the unit after installation.
( 1 ) Ensure that the AC line conditions satisfy the power supply requirements.
(2 ) Ensure that the DC voltages satisfy the unit requirements.
( 3 ) I nspect the interface cables to ensure pin 1 on the cable goes to pin 1 of the connector at both the unit and at the control unit.
( 4 ) If the unit is in a daisy chain mode with one or more units, make sure that only
the last unit has a line terminator (L TN) installed.
( 5 ) Ensure that the desired logical unit number' (LUN) of the unit is selected on the
KGFM PCB, see Section 3.7.1 and that each LUN in the system is unique.
( 6) In the case of Hard Sector (fixed sector length), ensure that the correct sector
count is set on KGFM PCB, see Section 3.7.7.
( 7 ) Ensure that Tag 4/5 Enable or Disable is set, per the system configuration. See
Section 3.7.3.
( 8 ) Ensure that File Protect key is in the proper position to meet the system requirement, see Section 3.7.4 .
. ( 9 ) Ensure that Disable/Normal keys are correctly set to the Normal position. (Dual
Channel option)
(10) Ensure the Release Timer key is set to the desired position. (Dual channel option)
(11) Ensure that all PCB assemblies and cables are firmly seated.
5.2 ERROR STATUS
The disk unit, optional power supply unit (PSU), and/or the control unit will issue the
following statuses as shown in Table 5-2-1.
.
Table 5-2-1 Error Status
Error Status
Definition
Alarm
Power malfunction has occurred on the disk unit or optional
PSU.
OPtional PSU
Not Selected
The control unit cannot select the specified disk unit.
Disk Unit
Control Unit
Not Power Readv
(*PWRDY)
DC power is not sufficient for the specified voltage.
Disk Unit
(KGFMI
Power-up
Sequence Check
Power·up sequence is not completed.
Disk Unit
(KGFMI
Device Check
(DVCK)
DVCK indicates a fault condition has occurred in the disk
unit.
Disk Unit
(KGFMI
Seek Error
(SKERRI
SKERR status indicates that a seek malfunction has
occurred in the disk unit.
Disk Unit (KGFMI
Control Unit
Read Error
READ ERROR status result if a data error has occurred
in read operation.
Control Unit
Dual Channel
DUAL CHANNEL malfunction concerns Select/Reserve
functions.
Control Un it
B03P·4760·0111A ... Ol
i
Information Source
5·'
I
Maintenance persl?nnel can see the Power-up Sequence Check. Device Check (Fault) or
Seek Error status at Fault Indicator LEOs on KGFM PCB assembly. These LEOs are
defined as shown in Table 5·2·2.
Table 5-2·2 Fault Indicator Definition
Status Tag
Status Bit
Error
Code
error Status
2
Power-up
Sequence
Check
Device
Check
(Fault)
Seek
Error
1
2
1
0
1
1
03/08
Actuator Lock check (State 3)
0
1
0
02/0A
DC Motor Accelerate check (State 2)
1
1
0
OS/OE
Accelerate complete check (State 6)
1
1
1
07/0F
Initial seek check (State 7)
1
0
1
05/00
Emergency on Ready check
0
0
1
09
Control Check 1
0
1
0
OA
Control Check 2
0
1
1
OB
Write Off-track Check
1
0
0
OC
Write Unsafe Check
1
0
0
0
H
1
0
1
Description
4
,
1
00
Write Protect Check
1
,
0
OE
MaltipieHead Check
1
1
1
OF
Emergency (Conil8Cluently 05/001
0
0
1
11
RTZ Time-out Check
0
1
0
12
Seek Time-out Check
0
1
1
13
Over-shoot Check
1
0
0
14
Seek Guard Band Ckeck
1
0
1
15
I.inear Mode G.uard Band Check
1
1
0
16
RTZ outer Guard Band check
1
1
1
17
Illegal Cylinder Check
0
---------_.-
I
I
(!;)
ST Sf
e>
S'-r~1.
o
s-1'Slt
o
<; 7'76-(
o >-r-t (;. 7. •
--
5-2
B03P-4760-0111A ... 01
)
5.3 FAULT ISOLATION LIST
To isolate the fault, the possible faults defined by fault code and assembly to be replaced are listed in Table 5-3-1.
Table 5·3·' Fault Isolation List
Code
03/0B
Definition
Description
Description : indicates that the actuator was not released
during State 2, which was detected by no current flowing
through the solenoid.
Actuator Lock Check
(State 3)
Possible Fault:
CD Disconnection of CN12 on TVQM
® Actuator auto-lock fault (Drive)
® Relay RL1/RL3 fault (TVQM PCB)
0 Relay driver fault (CZOM PCB)
® Release detection fault (CZOM PCB)
® Power-up sequence control fault (KGFM)
02/0A
DC motor Accelerate check
(State 2)
Description: indicates that the rotational speed did not
come up to 94% speed within 50 seconds of State 2.
Possible Fault:
CD Disconnection of CN11 of TVQM PCB.
® Power amplifier fault (TVQM PCB)
® DC motor control fault (CZOM PCB)
0 +24V DC too low (Power Supply)
® DC motor itself fault (Drive)
® Power-up sequence control fault (KGFM)
06/0E
Description : indicates that the first acceleration of spindle
motor was not terminated within 16 seconds of State 6.
Accelerate complete check
(State 6)
Possible Fault:
CD Power amplifier fault (TVQM PCB)
® DC motor control fault (CZOM PCB)
® +24V DC too low (Power Supply)
0 DC motor itself fault (Drive)
® Power-up sequence control fault (KGFM)
)
07/0F
Description: indicates that initial seek was not completed
or not terminated within 4 seconds of State 7.
Initial Seek Check
(State 7)
Possible Fault:
CD Power amplifier fault (TVQM PCB)
® Actuator auto-lock fault (Drive)
® Position sensing fault including PLO (CZOM PCB)
0 Servo control fault (CZOM)
® Power-up sequence or seek control logics fault
(KGFM)
® Servo surface malfunction (Drive)
(!) VCM fault (Drive)
05/00
Emergency on Ready Check
Description : indicates that VCM/DC motor over-heat or
DC motor fault (sensor fault) occurred during Ready Status
(State 4). and consequently goes to not-ready status.
Possible Fau It:
CD Power amplifier fault (TVQM PCB)
® Servo control fault (CZOM PCB)
® Seek control logic fault (KGFM PCB)
0 VCM itself fault (Drive)
® DC motor control fault (CZOM PCB)
® DC motor phase detection fault (TVQM PCB)
(!) DC motor phase decoder fault (CZOM)
® Disconnection of CN11 of TVQM PCB
B03P-4760-0111A ... 01
5-3
Table 5·3·' Fault Isolation List (Continued)
Code
09
Definition
Description
Control Check 1
)
Description : indicates that illegal command was issued
from the control unit during not-ready status. head's
moving or seek error status.
Possible fau It:
822) were set on the drive.
Possible fault:
CD Illegal command from the control unit.
® Cylinder address register fault (KGFMi
® Line receiver fault (KGFM)
B03P-4760-0111A ... 01
5-5
5.4 TROUBLESHOOTING SYMBOL
The troubleshooting flow charts contain the procedures beginning with an error status,
to pursue trouble sources.
The following conventions are provided. to aid understanding the symbols used in this
trouble shooting flow charts as shown in Table 5~4-1.
Table 5-4-1 Svmbolof Flow Chart
Description
Symbol
(
,
)
Terminals. Starting point of the trouble.
~O
Decision. go ahead according with YES or NO. (Reference test point.)
possible fault (Refer to 5.3)
O.
0
Connector, go ahead same· numbered symbol in same sheet.
\)
Connector, go ahead same·numbered symbol in another sheet.
I
I
Process. perform activity gillen.
5.5 TROUBLESHOOTING FLOW CHART
In this paragraph, the following flow charts are provided.
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
5-5-1
5-5-2
5-5-3
5-5-4
5-5-5
5-5-6
5-5-7
5-5-8
Alarm
Not Selected
Not Power Ready
Power-up Sequence Check
Device Check
Seek Error
Read Error
Dual Channel
)
)
5·6
8031'-4760·0111 A ... 01
ALARM
NO
1. Disconnect CN32 on
PSU.
2. Re·power on
1. Disconnect CN31 and
CN33 on PSU.
(CN9 and CN10 on the)
disk unit
(To Sheet 2)
2. Re-power on
)
YES
NO
1. Reconnect CN31 and
CN33 on PSU.
(CN9 and CN10 on the)
disk unit
Replace oPtional
Fan unit
Replace oPtional
PSU
2. Replace CZFM PCB
3. Re-power on
YES
Restart
(To sheet 2)
Figure 5-5-1 Alarm Flow Chart (Sheet 1 of 2)
B03P-4760-0111 A ... 01
5-7
(From Sheet 1)
(From Sheet 1)
02
)
1.
Disconnect eN8.
1. Replace the fuse.
2.
Re-power on.
2.
Re-power on.
NO
NO
YES
YES
1. Replace CZOM
Replace TVQM
PCB.
2.
1.
Disconnect CN32
on PSU.
2.
Re..power on.
PCB
Re-power on.
YES
)
NO
Re·start
YES
NO
Replace DE or
Disk unit
Replace oPtional
Fan unit
Figure 5-5-1 Alarm Flow Chart (Sheet 2 of 2)
5-8
B03P-4760-0111A ... 01
Replace optional
PSU
NOT SELECTED
\
)
NO
Correct cabling
or LTN
YES
Driver/Receiver
fault
NO
Replace KGFM
PCB, or
Check the control
unit function.
NO
)
NO
YES
Unit Selection
Fault
Check the cables
or
Check the control
unit function.
Set the correct.
Replace KGFM
PCB
Disk Address
on KGFM PCB.
Figure 5·5-2 Not Selected Flow Chart
B03P-4760-0111A ... Ol
5·9
NOT
POWER READY
NO
NO
Replace
TVOM PCB
NO
YES
PWR DY detect
fault
NO
YES
Replace CZOM
PCB
)
Replace KGFM
. PCB
YES
NO
Refer to
ALARM flow chart
Adjust DC
voltage on PSU
Figure 5·5-3 Not Power Ready Flow Chart
5·10
B03P-4760·01 llA ... 01
Re-start
POWER-UP SEQUENCE CHECK
To Sheet 2
To Sheet 3
To Sheet 4
To Sheet 5
To Sheet 6
Figure 5-5-4 Power-up Sequence Check Flow Chart (Sheet 1 of 6)
B03P-4760-0111A ... 01
5-11
From Sheet 1_
)
NoG)
Connect CN 12
on TVQM PCB
NO@
Replace KGFM PCB
No
Replace TVQM
)
ves@
ves@
Replace the Drive
Replace CZOM PCB
Figure 5-54 Power-up Sequence Check Flow Chart (Sheet 2 of 6)
5·12
J
i
B03P-4760·0111A ... Ol
Restart
From Sheet 1
)
Connect CN11
Check the Power Supply
@NO
YES
Replace CZOM PCB
Replace TVQM PCB
NO
-
YES
)
YES@
Restart
NO
Replace KGFM PCB
YES@
NO
®
. Replace the Drive
Restart
Figure 5·54 Power-up Sequence Check Flow Cha" (Sheet 3 of 6)
B03P-4760-0111A ... 01
5-13
From Sheet 1
cr
)
@NO
YES
Replace TVQM PCB
YESG)
NO
Replace CZOM PCB
)
YES@
NO
Replace KGFM PCB
YES@)
NO
8)
Check the Power Supply
Replace the Drive
Figure 5-5-4 Power-up Sequence Check Flow Chart (Sheet 4 of 6)
5-14
B03P4760~0111A, .. 01
Restart
From Sheet 1
14
Replace TVQM PCB
YESG)
NO
Replace KGFM PCB
YES@)
NO
Replace CZOM PCB
NO
(3)
®
(2)
Replace the Drive
Restart
Figure 5-5-4 Power-up Sequence Check Flow Chart (Sheet 5 of 6)
B03P-4760-0111A ... 01
5-15
From Sheet 1
NO®
YES
Connect CN 11
on TVQM PCB
Replace TVQM PCB
VEsCD®
NO
Replace KGFM PCB
)
YES@)
NO
Replace CZOM PCB
VEs0®0
NO
o
Replace the Drive
Restart
Figure 5-5-4 Power-up Sequence Check Flow Cha" (Sheet 6 of 6)
)
5-16
B03P-4760-0111A •.. 01
DEVICE CHECK
To Sheet 2
To Sheet 3
To Sheet 4
To Sheet 5
To Sheet 6
Figure 5·5-5 Device Check Flow Chart (Sheet 1 of 6)
B03P-4760·0111A ... 01
5·17
From Sheet 1
Replace KGFM PCS
Correct cabling
YES@)
)
Check the control
unit function
Restart
Figure 5-5·5 Device Check Flow Chart (Sheet 2 of 6)
)
5·18
B03p·4760-0111 A ... 01
From Sheet 1
)
NO
YES
Check the ·FNPOS
signal on the cylinder
·FNPOS; :to.650-p max
Check the Offset
adjustment (RV12)
YES
YES
NO
)
Perform the adjustment
of specified item
Replace CZOM PCB
and perform the
specified adjustments
YES
CD
o
Replace the Drive
Restart
Figure 5·5·5 Device Check Flow Chart (Sheet 3 of 6) .
B03P·4760·0111A ... 01
5·19
.From Sheet 1
YES
Check the control unit
function
NO
YES
NO
CD
Replace CZOM PCB
and perform the
specified adjustme!1ts
)
YEsCD®0
NO
@
®
Replace the Drive
Replace CZOM PCB
Figure 5-5-5 Device Check Flow Chart (Sheet 4 of 6)
5·20
B03P-4760·0111A ... 01
Restart
From Sheet 1
)
NO@
1 YES
NO
®
Turn the switch off
)
ChecK the control unit
function
Replace KGFM PCB
Note) FPT (File Protect) switches are located on KGFM PCB assembly (SW1·Key 9) and an oPtional
operator panel.
Figure 5-5·5 Device Check Flow Chart (Sheet 5 of 6)
B03p·4760·0111A. _.01
5-21
From Sheet 1
NO
YES
Replace CZOM PCB
and perform the
specified adjustments
YESG)®
NO
o
Replace the Drive
Restart
Figure 5·5·5 Device Check Flow Chart (Sheet 6 of 6)
5·22
B03P4760·0111A ... 01
)
(
Error Code 11/12
RTZ/Seek Time out
)
To Sheet 2
Error Code 13
(
Over-shoot Check
)
To Sheet 3
Error Code 14
(
Seek Guard Band Check
(
linear Mode Guard Band Check
)
To Sheet 4
)
Error Code 15
)
To Sheet 5
Error Code 17
(
Illegal Cylinder Check
)
To Sheet 6
Error Code 16
(
RZ OGS Check
)
Figure 5-5·6 Seek Error Flow Chart (Sheet 1 of 6)
B03P-4760-0111A ... 01
5-23
From Sheet 1
31
Replace KGFM PCB
YES@
Replace CZDM PCB
and perform the
specified adjustments
)
YESG)
NO
®
Replace the Drive
Restart
F.igure 5-5-6 Seek Error Flow Chart (Sheet 2 of 6)
)
5-24
B03P-4760·0111A ... Ol
From Sheet 1
)
YES
Replace KGFM 'PCB .
NO
)
Replace CZOM PCB
and perform the
specified adjustment
YESCi)®
NO
(3)
8)
Check the Power Supply
Replace the Drive
Restart
Figure 5-5-6 Seek Error Flow Chart (Sheet 3 of 6)
B03P-4760-0111A ... 01
5-25
From Sheet"'
)
YES
NO
YES
YES
Replace CZOM PCB
and perform the
specified adjustment
)
YEsCD0
NO
®
Replace the Drive
Restart
Figure 5-5-6 Seek Error Flow Chart (Sheet 4 of 6)
B03P4760-0111A ... Ol
Replace KGFM PCB
From Sheet 1
34
Replace KGFM PCB
YES@
NO
Replace CZOM PCB
and perform the
specified adjustments
YEsCD0
NO
@
Replace the Drive
Restart
Figure 5-5·6 Seek Error Flow Chart (Sheet 5 of 6)
B03P4 760-0111 A ... 01
5-27
From Sheet 1
Check the cabl i ng
and LTN
NO
YES
Conec! the cabling
and LTN
NO
Check Tag 1
and Bus 0 - 9
signals
Restart
)
YES
o
Check the control
unit functions
Replace KGFM
PCB
Figure 5-5-6 Seek Error Flow Chart (Sheet 6 of 6)
5·28
i
I
I
B03P-4760·011 1A ... 01
Read Error
YES
NO
YES
NO
To Sheet 6
Format Tracks
RC
CYL
HIC
DA
HD
40
To Sheet 2
Note: 1)
2)
43
To Sheet 2
To Sheet 2
To Sheet 2
To Sheet 3
To Sheet 5
AA is Address Area
DA is Data Area.
Figure 5·5-7 Read Error Flow Chart (Sheet 1 of 6)
B03P-4760·0111A ... 01
5·29
From Sheet 1
From Sheet 1
~
NO
YES ,--.:.Y.:::E:::..S<-
NO
Check the control
un it function
Replace the Drive
Replace CZOM
PCB
Restart
From Sheet 1
From Sheet 1
)
~1
( CZOM )
TRM5·9·
YES
NO
Replace the Drive
Note
Replace KGFM
PCB
1)
If the noise exceeding 1.0Vo-p appears on -FNPOS
signal during Linear Mode, it is incorrect.
2)
One HIC
CSO:
CS1:
CS2:
Check the control
function
I
I'
i
track
chip has four/two heads.
HDO to 3
HD4t07
HD8 and 9
Figure 5-5-7 Read Error Flow Chart (Sheet 2 of 6)
5·30
Assign a spare
B03P-4760-0111A ... 01
)
From Sheet 1
From Sheet 5
NO
YES
NO
Replace KGFM PCB
Restan
Replace the Orive
Replace CZOM PCB
)
YES
Check the control
unit
Figure 5-5-7 Read Error Flow Chart (Sheet 3 of 6)
)
B03P-4760-0111 A ... 01
5-31
From Sheet 3 and 5
Head Error
YES
YES
NO
YES
)
NO
Replace CZOM PCB
Replace the Drive
Check the control
unit function
l1eplace KGFM PCB
Figure 5·5-7 Read Error Flow Chart (Sheet 4 of 6)
)
5·32
B03P·4760"0111 A ... 01
From Sheet 1
YES
~o
V
To Sheet 3
YES
To Sheet 6
YES
Assign spare
area track
To Sheet 4
Figure 5-5 7 Read Error Flow Chart (Sheet 5 of 6)
B03P-4 760-0111 A ... 01
5-33
From Sheet 1
~
P3.4on
CZOM Amplitude
~
)
NO
correct?
YES
~N_O______________~NO
From Sheet 5
YES
Repla.ce CZOM PCB
Replace the Drive
(CZOM)
NO
KGFM
(TRM7-03/TRM7-12)
)
YES
Restart
Ctreck the interface
cable
Replace KGFM PCB
Replace CZOM PCB
I
Check the control
unit
)
Figure 5-5-7 Read Error Flow Chart (Sheet 6 of 6)
5-34
B03P-4760·0111A ... 01
)
€UAL CHANNEL
Not Selected
1
CV
To Sheet 2
t
Selected but not Reserved
~
To Sheet 3
)
Selected but not Priority Selected
(Unconditionally Reserved)
~
To Sheet 4
t
Selected but not Released
._-_ .. -
.54
To Sheet 5
Figure 5·5·8 Dual Channel Malfunction Flow Chart (Sl)eet 1 of 5)
B03P·4760·0111A ... 01
5·35
From Sheet 1
NO
Correct Cabling
NO
( Maintenance)
Switch
YES
Set 10 the
desired position
YES
NO
Wait for Release
command from
the oPPOsite
channel
)
CHB
CHA
YES
XCGM
(CN28.01 )
NO
Replace KGFM
Replace XCGM
FigureS-S·S Dual Channel Malfunction Flow Chart (Sheet 2 of 5)
B03P-4 760-0111 A ... 01
From Sheet 1
52
)
Check an LED on
Dual Channel
NO
YES
Set the R l TM key
to the desired position
NO
YES
Replace XCGM
CHB
)
CHA
Replace KGFM
Replace XCGM
YES
NO
Restart
Check the Control
. Unit function
Figure 5-5-8 Dual Channel Malfunction Flow Chart (Sheet 3 of 5)
B03P-4760-0111A ... 01
5-37
From Sheet 1
53
. Check the following test point
Channel A Priority Selected CN2B·05
(DISCHB)
Channel 8 Priority Selected CN28·06
(DISCHA)
YES
CHB
Replace XCGM
CHA
Replace KGFM
NO
YES
. ReplaceXCGM
YES
NO
Restart
Check the Control
Unit function
Figure 5·5·8 Dual Channel Malfunction Flow Chart (Sheet 4 of 5)
5-38
B03P-4760-01 11A ... 01
From Sheet 1
54
')
YES
XCGM
(CN27-0B)
NO
YES
NO
CHB
CHA
)
Replace KGFM
NO
YES
Replace XCGM
Restart
Figure 5-5·8 Dual Channel Malfunction Flow Chart (Sheet 5 of 5)
B03P-4 760-011 1A _, ,01
5-39
-
)
I
)
)
Section 6 .
Maintenance
6. MAINTENANCE
6.1 INTRODUCTION
This section covers maintenance of the unit, and is divided into General Precautions,
Preventive Maintenance, Maintenance Equipment, Parts Replacement, and Electrical
Checks and Adjustment items.
6.2 GENERAL PRECAUTIONS
6.2.1 Power On/Off
(1) Visually check the condition of the device before turning the power on.
(2) Always turn the power off before removing or inserting printed circuit
boards or connectors.
(3) After maintenance, before turning the power on, ensure that all printed
circuit boards and connectors correctly seated and installed in the correct
position.
6.22 Parts Replacement
( 1) Use screwdrivers that match the size of the screws.
(2) Do not leave removed screws in the drive.
Caution: Never loosen the retaining clamps for the DE aluminum cover.
The DE must not be opened in the field. Screws marked with
paint on their heads must not be loosened.
6.2.3 Dual Channel Switches
(1) Turn the switches to the desired position according to system configuration.
(2) After maintenance, turn the maintenance switch to the Normal AlB
(NRA/NRB) position.
6.2.4 Other
(1) Use test equipment that has been correctly calibrated.
(2) Always record failure symptoms and remedies employed for later reference.
6.3 MAINTENANCE TOOLS AND EQUIPMENT
Table 6-3-1 Maintenance Tools and Equipment
Tool and equipment
Model
Oscilloscope
TEKTRON IX 475.
Osci 1I0scope probe (x 10)
TEKTRONIX P6053B. or equivalent
Or
equivalent
Digital multimeter
Screwdriver
6.4 PREVENTIVE MAINTENANCE
No preventive maintenance is required.
6.5 PCB ASSEMBLY REPLACEMENT
The parts required for maintenance are the three printed circuit bo?rd assemblies. (in
case that dual channel option is not mounted). (Refer to Section 7. Spare Parts.) This
section describes the removal of bad PCB.
6.5.1 PCB Assembly Arrangement
Three PCB assemblies are mounted on the DE as shown in Figure 6-5-1.
B03P·4760-0111A ... 01
6-1
KGFM (Controller F)
CZOM (Controller 0)
TVQM (Power Amp Q)
Figure 6·5·' PCB Assy. Arrangement
6.5.2 KGFM PCB Assembly Replacement Procedure
Refer to Figure 6-5-2.
To replace the KGFM PCB Assembly, proceed as follows:
(1) Removal
(A) Loosen screws "A" and remove the top cover.
(B) Disconnect wiring (CN3 and CN4) from the KGFM PCB assembly.
(C) Remove the six screws indicates in Figure 6-5-2.
(D) Remove the KGFM PCB assembly by lifting it.
(2) Installation
(A) Fasten the KGFM PCB Assembly to the side frame, six screws.
(B) Fasten connectors (CN3 and CN4).
(C) Install the top cover and tighten screws "A".
B03P-4 760-0 111 A ... 01
)
Top Cover
Remove these screws (6 pes)
to replace KGFM PCB.
A
)
Figure 6-5-2 KGFMPCB Assembly Replacement
6.5.3 CZOM PCB Assy. Replacement Procedure
To replace the CZOM PCB Assembly, proceed as follows:
Refer to Figure 6-5-3.
(1) Removal
(A) Loosen screws "B".
(B) Raise the KG FM PCB Assy. by lifting up the LIPper side-frame.
(C) Disconnect wiring (CN5, CN6, CN7, CNS, CN9, and CN10).
B03P-4760-0111A ... 01
6-3
(D)
Remove six scres and lift out the CZOM PCB Assembly. Be careful
not to damage CN15 on the TIXM (Through Connector).
The TIXM is connected to the CZOM PCB assembly at the back of the
board. Refer to Figure 6-5 4. CN15 will be disconnected by lifting the
CZOM PCB assembly.
)
Screw B
Remove these six screws
to replace CZOM PCB.
,
)
Figure 6·5·3 CZOM PCB Replacement
6·4
B03p·4760·0111A ... 01
CZOM PCB Assembly
/
CNl5
(CN7)
(CNS)
+
r~==~-\--:~
I
\ TIXM (Through Connector)
i
TVQMPCB
I
(Back View from Rear Side)
Figure 6-5-4 TlXM Connection
(2) I nstaflation
(A) Set the CZOM PCB assembly on the lower side-frame. Then, check that
CN 15 is connected correctly.
(B) Fasten the six screws, and fasten other connectors.
(Cl Tighten screws "B".
)
G.S.4 TVOM PCB Assembly Replacement
The TVOM PCB assembly is mounted on the rear side of DE. Refer to Figure
6.5.5.
(1) Removal
(A) Remove the Fan Unit (which is optional) or the cover by loosening the
the screws "E".
(B) Disconnect wiring (CN11, CN12, CN13, and CN14) from the DE and
the CZOM PCB assembly,
(C) Remove screws "F".
Note:
Be careful not to lose the isolating bushings, which fit around the
threaded portion of the screws of''. When replacing the TVQM PCB
assembly.
(2) I nsta Ilation
(A)
Fasten the TVQM PCB assembly to the DE with screws "F", At this
time, do not forget to fit the isolating bushings.
(B) Fasten connectors coming from the DE and the CZOM PCB assembly.
(C) Install the optional Fan Unit or the cover with screws "E".
B03p·4760·0111A ... Ol
Screw"e"
TVCM PCB
Cover or
oPtional fan unit
Figure 6-5-5 TVOM PCB Assembly Replacement
6.6 PCB CHECK AND ADJUSTMENT
6.6.1 Test Point Arrangement on PCB
Each PCB assembly is provided with test points and potentiometers to check
and/or adjust circuit functions.
(1) KGFM PCB assenibly
.
The test points and pt>tentiometers are located on the KGFM PCB assembly
as shown in Figure 6-6-1. Test points are listed in Table 6-6-', check terminals in Table 6-6-2, potentiometers in Table 6-6·3, and switch keys in
Table 6-6-4.
Caution: The short plugs listed in Table 6-6-2 must not be removed during
PCB replacement.
)
6·6
B03P·4760·0111A ... O~
-----7r1--Z;-N-J-~-~
I HC:2C'li
-
LL=___.-:~_____J~DD~
~~
.....,
tNJ
~~_ _J_
1
.....
'
en
00:
eo
en
00:
eo
...'"
l:
en
·0
...
C-
00"
I-
eo
U>
~
CI>
~
>
en
::c
E
00:
eo
~
U>
«
to
U
~O
)
Q.
:2
u...
C!l
~D
~
...cb
cb
CI>
:;
.E'
u...
~:
- ~:
OJ
eo
OJ
Cl
eo
~D
-
[]J
<:r
:s:=
r
~D
~=
ENJ
~
B03p·4750·0111A ... Ol
v~D
~
....J
5·7
Table 6-6-' KGFM Test Points
TRM4
Pin
Signal Name
Abbreviation
Pin
Abbreviation
Signal Name
09
STG2
Status Tag 2
08
OV
10
STGl
Status Tag 1
07
RDY
Ready
'1
12
STS4
Status Bit 4
06
FPT
File Protect
STS2
Status Bit 2
as
EMGN
13
STS1
Status Bit 1
04
14
Emergency Retract
03
15
16
Ground
02
I +5VDC
+5V
,
01
I
TRM5
Pin
Abbreviation
STLTRE (0)
08
STLTRE (1)
OFSTS (0)
07
OFSTS (1)
'SKSTL (1)
06
'SKSTL (0)
Pin
Abbreviation
09
10
11
Signal Name
12
OFINT (1)
05
OFZNT (0)
13
·SKIINH (1)
04
KSKIINH (0)
14
NMiNT 11)
03
NMINH (0)
15
ILCYTM (0)
02
I LCYLTM (1)
16
NOMSK 10)
01
NOMSK (1)
Signal Name
.
Note) The pins shown by .. - _ .. must be connected with Short-Plug (C63L·0790-o001).
)
)
6-8
B03p·4760·0111A ... 01
Table 6-6-2 KGFM Check Terminals
Test Points
Abbreviation
Signal Name
I
1
Signal
Level
Schematic
Code
AEl
TRM5-01
RGC
Rea.d Gate Control
TTL
TRM5-02
VCMHTL
VCM Heat Latch
TTL
AKl
TRMS-03
SKI
Seek In Complete
TTL
AK2
TRM5-04
OFSET
Offset
TTL
AEl
TRMS-05
RDMD
Read Mode
TTL
AM2
TRM5-OS
SCT
Sector
TTL
ALl
TRM5-07
SLD
Selected
TTL
AC1
TRM5-08
OV
Ground
TRM5-09
FLT
Fault
TTL
TRM5-10
RTZC
Return To Zero Control
TTL
AE1
TRM5·11
INX
Index
TTL
ALl
TRM5-12
PWRDYl
TRM5-13
SKEND
TRM5·14
WGC
TRM5·15
STCAR2
TRM5·1S
OV
TRMS-01
VFOFS1
TRMS-02
TRMS-03
A01
AKl
Power Ready 1
TTL
AGl
Seek End
TTL
AJl
Write Gate Control
TTL
AEl
Set Cylinder Address Register 2
TTL
Ground
AE1
i
i
A01
VFOFast Sync 1
TTL
DFWD
Drive Forward
TTL
AH2
LNMD
Linear Mode
TTL
AH2
AM2
TRMS-04
ROY
Raady
TTL
AJl
TRMS-05
DMFLL
DC Motor Fau It Latch
TTL
AKl
TRMS-OS
'OSCLK
Oscilator Clock
TTL
AGl
TRMS-07
DRLM
Drive Liner Mode
TTL
TRMS-08
OV
TRMS·09
ONCYL
On Cylinder
TTL
TRMS-10
SKERR
Seek Error
TTL
AJl
TRMS·11
SEKM
Seek Mode
TTL
AHl
Ground
AH1
A01
AJl
TRMS-12
V;O
Velocity Equal to Zero
TTL
AH1
TRMS-13
ILCYL
Illegal Cyl inder
TTL
AFl
TRMS-14
·VFOFS
VFO Fast Sync
TTL
AM2
TRMS-15
DEOZ
Differences Equal to Zero
TTL
AF2
TRM7-1S
OV
Ground
B03p·4760-0111A ... Ol
AOl
6·9
Table 6·6·2 KGFM Check Terminals (Continued)
)
Test Points
6·10
Abbreviation
Signal Name
Signal
Level
Schematic
Code
TRM7'{)1
DLSFD
Delav Low Spead
TTL
AH2
TRM7.Q2
SQINH
Sequence Inhibit
TTL
AG2
TRM7.Q3
"LPLO
Lock To PLO
TTL
AM1
TRM7'{)4
'SLPLO
Set Lock To PLO
TTL
AMl
TRMHl5
"VCTCLB
VFO Control Clock B
TTL
AHl
TRM7.Q6
"FLTSQ
Filter Squelch
TTL
AM2
TRM7.Q7
STLl
Settling 1
TTL
TRM7.QS
OV
TRM7.Q9·
PWRDY2
Power Readv Z
TTL
TRM7·10
SRSLD
Set Register Set Lock To Data
TTL
AM1
TRM7·11
ENWDP
Enable Wire Data Pulse
TTL
AM2
Ground
,
AJ1
AQ1
AG1
TRM7·12
"SLDATA
Set Lock to Dsta
TTL
AM1
TRM7·13
"VCTCLA
VFO Control Clock A
TTL
AH1
:2 Bvte Clock
TTL
AH1
Lock To DATA
TTL
AM1
TRM7·14
"28YTCLK
TRM7·15
"LDATA
TRM7·16
OV
Ground
AQl
TRMS.Q1
·PLO:28
PLO:2 Bit
TIL
AHl
TRMS'()2
GTZM
Go To Zero Mode
TTL
AH1
TRMS.Q3
'CKCLRK
Check Clear Key
TTL
ACl
TRMS'()4
"CLDF
Clsmp Difference
TTL
AF2
TRMS'{)5
PSDR
Position Drive
TTL
AH2
TRMS.Q6
·CV;::'384
Cvlinder ;::'384
TTL
AFl
TRMB-07
D160'F
Difference 16 or Offset
TTL
AF2
TRMS-08
OV
TRMS·09
"ACDME
TRMS·l0
DLT31
TRMS·11
·CMPRS
TRMS·12
"RLDR
TRM8·13
Ground
AQ1
Accelerate DC Motor Enable
TTL
AG2
Difference Less Than 31
TTL
AF2
Compress
TTl.
AG2
Relav Drive
TTL
AG2
CHACMP
Channel·A Compare
iTL
AC1
TRM8·14
°LKR l.S
Lock Release
TIL
AG2
TRMS-15
UNSQ
Under Sequence
TTL
AHl
TRM8-16
OV
Ground
B03P·4760·0111 A ... 01
AQ1
Table 6-6-2 KGFM Check Terminals (Continued)
Signal Name
Abbreviation
Test Points
Signal
Level
Schematic
Code
TRMS~1
WDAT2
Write Data 2
TTL
AN1
TRMS~2
ENCWD
Encord Write Data
TTL
AN2
TRM9~3
*WDTP
Write Data Pulse
TTL
AN3
TRMS-04
SETALL 1
Set All 1
TTL
AP1
TRMS~5
RDAT
Read Data
TTL
APl
TRM9~6
VFOCL
VFO Clock
TTL
APl
TRM9~7
TRM9~8
OV
Ground
AQ1
AQ1
TRM9~9
OV
Ground
TRM9-10
OV
Ground
AQ1
TRM9·11
OV
Ground
AQl
TRM9·12
OV
Ground
AQ1
TRM9·13
OV
Ground
AQl
TRM9·14
OV
Ground
AQ1
TRM9·15
OV
Ground
AQ1
TRM9-16
OV
Ground
AQ1
AQ1
W1
+5V
+5VDC
DC
W2
-5V
-5VDC
DC
A82
W3
LVC 5V
LVC +SVDC
DC
AQl
W4
-5.2V
-5.2VDC
DC
AQl
WS
-12V
-12VDC
DC
AB2
W6
OV
Ground
W7
OV
Ground
AQ1
W8
OV
Ground
AQ1
W9
OV
Ground
AQ1
Wl0
OV
Ground
AQ1
AQ1
Table 6·6·3 KGFM Potentiometer Function
Pot No.
Function/Adjustment
Reference TP
Settling 1 (2.0ms)
RV1
TRM7·7
Note; No adjustment is required when the KGFM PCB is replaced.
Table 6·6-4 KGFM Switch Function
No.
Function
Disk Addre".,ng
Device Type (When Tag 4/5 enabled)
I
I
FPT
On·side
SW2
SW3
TRMl
TRM2
i
I
Sector Cou nting
Reference TP
ii
I
Tag 4/5 Enable
SW1
I
None
TRM5·06 (SCT)
I TRM5·111INX)
1
Busy signal terminator
i
No~e
!
B03P·4760·0111A ... 01
6·11
,,'- _____ - _____ - ._ ... ----..I,,
~
CN15
eN8
TP1
D
o0
W3 (OV)
TP2
55
56
54
RVg
J1
8 TRM3
1
'-__....JI~
J2
9
DO
8 TRM1
I
Jl
9
16
RV10
16
-TP4
53
-
D
S2
RV5 RV3
W2
00
9u8 .
RV1D
16
RV6
o
TRM4
1
;..... TP6
-
TF'5
RV4
8
TRM6
o
1
9
51
TP3
)
16
8 TRM2
0
I
RV12
9
0
8 TRM5
16
1
I
9
TP10
16
-
0
TP7
RV7
RV11
RV8
0
0
~(OV)
TP8
I
/Tpg
RV20
CN5
CN6
Figure 6-6 2 CZOM PCB Assembly Test Points Arrangement
0
6 12
0
B03p 4 760 0111 A ... 01
0
0
(2) CZOM PCB assembly
The test points and potentiometers located on the CZOM PCB assembly are
shown in Figure 6-6-2. Test points are listed in Table 6-6-5, potentiometers in
Table 6-6-6 switches in Table 6-6-7.
B03P·4 760-0111 A ... O1
5-13
Table 6-6·5 CZOM Test Point
TP No.
Signal Name
Abbreviation
level
TP 1
WCA
Write Current A
Analog
TP 2
WCB
Write Current. S
Analog
TP 3
PROT1
Pre-amplifier Output 1
Analog
TP 4
PROT2
Pre-amplifier Output 2
Analog
TP 5
AGCOTl
AGe Output 1
Analog
TP 6
AGCOT2
AGC Output 2
Analog
TP 7
REFP
Reference Pulse
ECl
TP 8
DLOT
Delaved Data
ECl
TP 9
OTWD
Data Window
TP10
VFOVC
VFO Control Voltage
Schemiiltic Code
)
ECl
Analog
TRM1- 1
PHA
Phase A
TTL
TRM'- 2
-PHS
Phase S
TTL
TRM1- 3
PHC
Phase C
TTL
TRM1- 4
TRM'- 5
TRM1- 6
TRM1- 7
TRM'- 8
Ground
IOV)
TRM1- 9
TRM1-10
COntrOl Clock
'CTCl
TRM' . "
TRM'·t2
ITEST1)
TRM1-13
Q44
TTL
TTL
--.
Q44
TTL
TRM1·14
·STARTP
Start Pulse
TTL
TRM1·15
°TMCl
Timer Clock
TTL
TRM1·16
STSPO
Set Speed
TTL
TRM2· 1
• USF
+RAWDT
Unsafe
TTL
Raw Data
ECl
TRM2· 2
TRM2- 3
TRM2- 4
TRM:;!- 5
TRM:;!- 6
TRM2· 7
TRM2- 8
TRM2- 9
10\/1
Ground
• DIGl T
Diag latch
TTL
-RAWDT
Raw Data
ECl
TRM2·10
TRM2-'1
TRM2·12
TRM2-13
TRM2-14
TRM2-'5
TRM2-16
TRM3- 1
SERVO
Servo Signal
Analog
TRM3- 2·
SAGC
Servo AGC
Analog
TRM3- 4
PLOSS
PLO S,"gle·shot
TTL
TRM3- 5
-HOLD
Head loaded
TTL
TRM3- 3
TRM3- 6
PlOLT
PlO latch
TTL
TRM3· 7
POSN
Position N
Analog
IOV)
TRM3- 8
6-14
TRM3- 9
POSQ
TRM3·10
• SVPND
Ground
Position Q
Servo Pulse Window
B03P-4760·0111A ... Ol
Analog
TTL
)
Table 6-6·5 CZOM Test Point (Continued)
TPNo.
Signal Name
Abbreviation
TRM3·11
TTL
(TESTP)
TRM3·12
SVPL
Servo Pulse
TRM3·13
• PLOLT
PLO Latch
TRM3·14
- ABSVL
Absolute Velocity
TRM3·15
SVSLT
TRM3·16
TTL
TTL
Analog
TTL
Servo S I ice Out
TTL
(TEST2)
TRM4· 1
PLO 112 Frequency
TTL
TRM4· 2
• GTl
Gate 1
TTL
TRM4· 3
• GT2
Gate 2
TTL
TRM4· 4
• GT3
BYTCL
Gate 3
TTL
Byte Clock
TTL
PLO 1/2F
TRM4· 5
Schematic Code
Level
TRM4· 6
TRM4· 7
(OV)
TRM4· 9
Analog
PLO Control Voltage
PLOVC
TRM4· 8
Ground
*MSDT
Missing Detected
TTL
Gate 4
TTL
TRM4·10
TRM4·11
* GT4
TRM4·12
• IGB2P
I n'ler Guard Band 2 Pu Ise
TTL
TRM4·14
• OGBP
Outer Guard Band Pu Ise
TTL
TRM4-15
*IGB1P
Inner Guard Band 1 Pulse
TTL
I
I
TRM4·13
TRM4-16
TRM5· 1
PADR
TRM5· 2
- VEL
TRM5· 3
FNVEL
Power Amplifier Drive
Analog
Velocity
Analog
Fine Velocity
Analog
DAC Output
Analog
Clamp Position
Analog
TRM5· 4
TRM5· 5
- DAC
TRM5- 6
·TRM5· 7
CLPOS
(OVI
TRM5· 8
TRM5· 9
- FNPOS
Ground
Fine Position
Analog
TRM5-10
TRM5·11
TRM5·12
TRM5·13
PER
Position Error
Analog
TRM5·14
VER
Velocity Error
Analog
Function
Analog
TTL
TRM5·15
TRM5·16
-FUNC
TRM6- 1
OFTRK
Off-track
TRM6· 2
NOGTZ
N .;- 0 Greater Than Zero
TTL
TRM6· 3
NGTO
N Grealer Than Zero
TTL
Ou!'~r
TTL
,
TRM6- 4
TRM6· 5
* OGB
Guard Band
TRM6· 6
TRM6· 7
DRLM
(OVI
TRM6- 8
Dr.ive Linear Motor
TTL
Ground
TRM6· 9
FWD
Forward
TRM6-10
TXPL
Track ClosSlng Pulse
TTL
Raw Index
TTL
TRM6·11
!
• RINX
TRM6-12
• IGB2
TRM6-13
• IGBl
TTL
TTL
I nner Guard Band 2
i I nnerGuaro Band 1
i
i
TRM6·14
B03P-4760·0111A ... Ol
TTL
!
6·15
Table 6-6·5 CZaM Test Point (Continued)
TP No.
Signal Name
Abbreviation
level
TRMS-1S
V =0
VelocItY Equal To Zero
TTL
TRM6-16
ONTRK
On-track
Til
Wl
(TEST)
W2
(TESTOFST)
W3
(OV)
Ground
W4
(OV)
Ground
WS
(OV)
Ground
Schematic Code
Analog
Table 6·6-6 CZaM Potentiometer Function
Pot. No
Functionl Adjustment
Reference TP.
RV 1
VCO (PlOI Adjustment
TRM4-1/S2. S3
RV 2
Delayed Data One-shot
TPS/TP9
RV 3
Positioning Time Adjustment
RV 4
Position Signal Adjustment
TRM3-7
RV S
VelocitY Offset Adjustment
TRM5-2
RV 6
Write Current Adjustment
TP1/TP2
RV 7
Referenct Pulse Adjustment
RV S
VCO (VFO) Adjustment
RV 9
Servo Pulse Window Adjustment
RV10
PLO Single-shot Adiustment
TRM3-4
RV11
CAC Adjustment
TRMS-S
RV12
Fine Velocity Adjustment
TRM5·3
TP7
TP9
TRM3-10
Table 6·6·7 czaM Switch Function
Pot. No
Funetion! Adjustment
Reference T.P.
S1
Power Amplifier Cut
S2
VCO (PLO) Adjustment 1
TRM4·1/RVl
S3
VCO (PLO) Adjustment 2
TRM4·1/RVl
S4
Current Sense Offset (On-end)
SS
Power Amplifier Drive Offset A (On-end)
S6
Power Amplifier Drive Offset B (On-end)
Note) Short·plugS on Jl. J2 and J3 must not be removed.
(3) XCGM PCB Assembly
The test points and switches are located on XCGM PCB assembly as shown in
Figure 6·6·3. Test points are listed in Tables 6·6·8 and 6-6-9 and switch functions
in Table 6-6·10.
6-16
B03P4760·0111A ... Ol
)
m~m
to I-
-
_
N
N
(")
N
Z
Z
U
U
(")
~
"'"
Z
a:
N
I-
u
~D
C"l
m~m
ISW11
ISW21
to
-
ISW31
moom
to
-
16
I
W2
9
TRM6
8
CJ
N
z
U
_
W1 W3
~ ~
CJ Cl
)
N
a: a:
I- I-
~
~D D~
Figure 6·6·3 XCGM PCB Assembly Test Points
B03p·4760·0111A ... 01
6·17
Table 6-6-8 XCGM Test Terminals and Test Points
TRM4
Pin
Abbreviation
09
°TRGSUP (1)
Signal Name
I
)
Pin
Abbreviation
08
"TRGSVP (0)
Signal Name
I
I
10
RSVCL (1)
07
RSVCL (0)
11
OV
Ground
06
"RSVCL
12
OV
Ground
05
ClK2
Clock :2
13
OV
Ground
04
CLKl
Clock 1
14
ClK2 (1)
03
CLK2 (0)
.
15
ClKl (1)
02
CLKl (0)
16
PWROY (1)
01
PWROY (0)
i
Reserve Clock
TRM5
Pin
Abbreviation
09
RSTMP (1)
Signal Name
08
RSTMP (0)
10
°RSTMP (1)
07
°RSTMP (0)
Pin
.
Abbreviation
Signal Name
11
OV
06
RSTMP
. Release Timer Pulse
12
OV
05
°RSTMP
Release Timer Pulse
13
OV
04
°INTR
14
°INTR (1)
03
°INTR (0)
15
°TROS (1)
02
'TROS (0)
16
TROA (1)
01
TROA (0)
Interrupt
Note) The pins shown by .. - _ .. must be connected with ShortoPlug (C63l 0790"()001).
0
)
6 18
0
B03P 4760 0111A ... Ol
0
0
Table 6-6-9 XCGM Test Points
Test Points
Abbreviation
TRM6.Ql
°DISCHB2
TRM6.Q2
CHBCMP
Signal
Level
Schematic
Code
Disable Channel B2
TTL
XC2
Channel B Compare
TTL
XB3
Disable A Key
TTL
XC2
XC3
Signal Name
TRM6.Q3
TRM6.Q4
TRM6.Q5
DISAK
TRM6-06
TRM6.Q7
DISCHA
Disable Channel A
TTL
TRM6.Q8
DISCHB
Disable Channel B
TTL
XC3
TRM6.Q9
CHAENB2
Channel A Enable 2
TTL
XC2
TRM6-10
SKENDB
Seek End B
TTL
XC3
TRM6-11
TRM6-12
DISBK
TRM6-13
SKENDA
Disable B Key
TTL
XC2
Seek End A
TTL
XC3
TRM6-14
TRM6-15
*DISCHAl
Disable Channel A 1
TTL
XC2
RSTMK
Release Timer Key
TTL
TRM6-16
XC2
CHBENB
Channel B Enable
TTL
XC2
LCHASLD
Lamp Channel A Selected
TTL
XC1
TRM7.Q4
LCHBRSV
Lamp Channel B Reserved
TTL
XC1
TRM7.Q5
LCHARSV
La",!p Channel A Reserved
TTL
XC1
BUSYB
TTL
XC1
Lamp Channel B Selected
TTL
XC1
XCl
TRM7.Ql
TRM7.Q2
TRM7.Q3
TRM7.Q6
BUSYB
TRM7.Q7
LCHBSLD
TRM7.Q8
OV
TRM7.Q9
·CHBSLD
Channel 8 Selected
TTL
TRM7-10
*CHASLD
Channel A Selected
TTL
TRM7-11
BUSYA
TRM7-12
CHBRSV
Channel B Reserved
TTL
XC1
CHARSV
Channel A Reserved
TTL
XC1
+5V DC
DC
XC1
DC
XC4
Ground
BUSYA
XC1
XC1
TRM7-13
TRM7-14
TRM7-15
TRM7-16
+5V
W1
+5V
+5V DC
W2
OV
Ground
W3
-5V
XC4
-5V DC
DC
XB2
Table 6-6-10 XCGM Switch Function
Function
No.
SW1
Reference T. P.
ChannC'!-A Switch
SW2
Channel-B Switch
SW3
Release Timer Switch
None
None
----
TRM1
TRM2
Busy Signal Terminator
TRM3
Mode Selection
B03P-4760-0111A ... Ol
i
None
None
I
None
6-19
6.6.2 PCB Adjustment after PCB Replacement
Refer to Table 6-6·11 for the required adjustment when a PCB assembly is replaced.
Table 6-6Item
l'
Adjustment after PCB Replacement
Spare Part
KGFM (B1SB·9830-0010A)
1
I
2
Adjustment/Selection
I
CZOM (B lSB-9340-0020A)
(1)
Disk Adressing (SW 1)
(2)
Device Type (SW 1)
(3)
File Protect (SW 1)
(4)
TAG 4/5 Enable (SW 1)
(5)
Sector Counting (SW 2/SW 3)
I
I
IS)
ON·side (SW 1)
II
11 ) POSition Signal Adjustment (RV<),)
I
I
(21
Positioning Time Adjustment (RV31
(3)
ON-side ($4. 55. 5S)
3
TVOM (B16B·9250-0010AI
None
4
XCGM (B1SB-9930-0010A)
None
Caution
Do not adjust the unspecified potentiometers
at PCB replacement.
(1) Position Signal Gain Adjustment (CZOM-RV4)
CD Confirm that drive has normal status.
(2) Repeatedly issue an RTZ command from Cylinder O.
@ Connect the test point TRMS-7 (0 R LMl to one vertical input channel of an
oscilloscope and trigger with the positive-going edge of the signal on CZOM PCB
assembly (DC coupled).
@ Connect the test point TRM3-7 (POSN) to the other vertical channel of the
oscilloscope (DC coupled).
Adjust potentiometer RV4 so that POSN signal amplitude is 8.0V ± 0.1 V (peak·
to peak). Refer to Figure 6-6-4.
Note: On the Occasion that RTZ operation is not completed, rotate potentia·
meter RV3 a little.
®
DRLM
ITRM6-7)
POSN
~------B.O±O.l
ITRM3·7)
Figure 6-6-4 Position Signal Gain Adjustment
(2) Positioning Time Adjustment
CD Repeatedly issue an alternate seek command between Cylinder 0 and Cylinder
822 (decimal).
~ Connect the test point TRM5-4 ("'ACCL) to one vertical input channel of an
oscilloscope and trigger with the positive-going edge of the signal on CZOM PCB
6·20
B03p·4760·0111A ... Ol
v
assembly (DC coupled).
Q) Connect the test point TRM6-7 (DR LM) to the other channel.
® Adjust potentiometer RV3 so that the decelerate time (Tdc)
is 17,3ms ± 1ms,
+ACCL
(TRM5-4)
DRLM
(TRM6-7)
Tdc
i
i'
Tdc
= 17,3 ms ±
1 ms
Figure 6-6-5 Positioning Time Adjustment
6,6.3 Electrical Measurement
This paragraph describes electrical measurements,
(1) Read Output Measurement
Caution
Use the 0 V terminals near test points TP3 and TP4 on the CZOM PCB, and use
a 300 MHz wide band pass oscilloscope, Measurement error may occur if these
precautions are not followed,
,
Confirm that the specific track can be rewritten for the Read Output
measurement,
@ Write repetitive "1100" and "101101,101101" pattern ("CCCCCCCCB6DB6
DB616 ") to all records on the specific track, e,g, CE track or Cylinder
track,
@ Connect test points TP3 and TP4 on the CZOM PCB with differential mode
(inverted CH2 and add with CH1).
.
@) After writing, measure the peak-to-peak level V2F and V, F as shown in
Figure 6-6-6.
CD
o
V2F 2. 200 [T1VO-p
Resolution ReTia =
\~~~
It-
X
iOO I%i
2. 60%
Figure 6-6-6 Read Output Measurement
B03P-4760·0111A ... Ol
J,
!
6-21
(2) CZOM PCB
a. PLO Free-run Frequency Adjustment (RV1, S2 and 53)
1. Turn the power off.
2. Set S1 to the off position (2 to 3: off)
3. Clamp TRM3-16 (or W1) to OV firmly.
4. Turn the power on, and wait 70 seconds.
5. Connect the test point TRM4-7 (PLOVc) to an oscilloscope (DC coupled).
6. Adjust potentiometor RV1 so that TRM4-7 (PLOVc) signal is +2.5V ± 0.1 V.
7. Connect test point TRM4-5 (BYTCLK) to a frequency counter.
8. Select the proper capacitance as shown in Figure 6-6-7 so that the frequency
of TRM4-5 is closest to 1.229MHz as possible.
9. Finally adjust the potentiometer RV1 so that the frequency of TRM4-5 is
1.229MHz± 2%.
52
M73
LH24
53
S2
53
~I
3~
~ ::'
25PF
30PF
S3
52
3
'2
1
52
S3
~
2, .
3rnTI
35PF
40PF
"
~/
1
/;-'
(5124)
High
Frequency
- - - - - Low
RV1
CD
)
Figure 6-6-7 pta Free-run Frequency Adjustment
b. Delayed Data One-shot (RV2)
1. Confirm that unit has normal status.
2. Connect test point TP (DTWD) on CZOM PCB to one vertical input of an
oscilloscope (DC coupled).
3. Connect test point TP (D LDT) on CZOM PCB to the other vertical input.
4. Trigger with the positive-going edge of TP (DTWD).
5. Issue a read command to the drive.
6. Adjust the potentiometer RV2 so that the following T is 12ns ± 1ns.
Cautio.n
Use the same length of probe for measurement
of T.
Read error caused by measurement
error may occur it this precaution is not followed.
6-22
j
I
B03P-4 760-0111 A ... 01
-f
)
TP9
(DTWDI
TP8
(DLDT)
.
T
...'
T = 12 ns ± 1 ns
Figure 6-6-8 Delayed Data One-shot Adjustment
c. Velocity Offset Adjustment (RV5)
1. Confirm that unit has normal status.
2. Connect test point TRM5-2 (-VEL) to an oscilloscope.
3. Adjust potentiometer RV5 so that TRM5-2 (-VEL) signal is OV ±50mV with
linear mode on Cylinder O.
d. Write Current Adjustment (RV6)
1. Confirm that unit has a normal status.2. Connect TP1 (WCA) to channel of oscilloscope and connect TP2 (WCB) to
the other vertical input channel with invert mode set.
3. Add the two channels (differential mode).
4. Issue a write command on Cylinder 0 and Head O.
5. Adjust potentiometer RV6 so that the difference is 451 mV ± 1DmV.
e. Reference Pulse Adjustment (RV7)
1. Confirm that unit has a normal status.
2. Connect test point TP7 (REFP) signal to one channel of the oscilloscope
(DC coupled).
3. Trigger the oscilloscope with the positive-going edge of the test point signal.
4. Adjust potentiometer RV7 so that the following TREF is 8ns ±O.5ns.
,,-----,------------- -0.9V
I
50%
TP7
(REFPI
-f--
50%
--
--
I:
J
-1.8\/
(51 nsl
- P t:: F ~ B ns ± 0.5 ns
Figure 6-6-9 Reference Pulse Adjustment
B03P-4760-0111A ... Ol
6-23
f. VFO Free-run Frequency Adjustment (RV8)
1. Turn the power off.
2. Set S 1
the off position.
3. Clamp TRM7-06 (*FLTSQ) on KGFM PCB to OV firmly.
4. Turn the power on, and wait 70 seconds.
5. Connect the test point TP9(DTWD) to a frequency counter.
6. Adjust the potentiometer RV8 so that the frequency of TP9 (DTWD) signal
is 19.664MHz ±300KHz.
g. Servo Pulse Window Adjustment.(RV9)
1. Confirm that unit has normal status.
2. Connect the test point TRM3-1 0 to an oscilloscope.
3. Trigger by itself at the positive-going edge.
4. Adjust the potentiometer RV9 so that the following Tsvp is 320ns ± 10ns.
to
50%
1-----
TRM3-10
(SVPWD)
.1
TSVp
TSVp =320 ns ± 10 ns
Figure 6-6·10 Servo Pulse Window Adjustment
h. PLO Single-shot Adjustment (RV 10)
1. Confirm that unit has normal status.
2. Connect the test point TRM3-4 (PLOSS) to an oscilloscope.
3. Trigger by itself at the positive-going edge.
4. Adjust potentiometer RV10 so t~at the following Tss is 1.51ls ±O.1IJs.
I
I
,--
- : - 50%
TRM3·4
(PLOSS)
I~
TSS
TSS" 1.5 J,t.S
:;;
0.1
J,t.S
Figure 6-6-11 P!..O Single-shot Adjustment
)
6·24
B03P-4760-0111A ... 01
i. DAC Adjustment (RV1 i)
1. Confirm that unit has a normal status.
2. Issue the alternate seek command between Cylinder 0 and Cylinder 822
(decimal) repeatedly.
3. Connect the test point TRM6-7 (DR LM) to an oscilloscope and trigger with
positive-going edge of the signal. (DC coupled)
4. Connect the test point TRM5-5 (-DA) to the other channel at the oscilloscope. (DC coupled)
5. Adjust a potentiometer RV11 so that VOA is 7.3V ±O.3V as shown in Figure
6-6-12.
)
ORLM (TRM6-7l
-OA (TRM5-5l
1I VOA
;
VOA = 7 .3V ± O.3V
)
Figure 6·6-12 CAe Output Adjustment
j. Fine Velocity Offset Adjustment (RV12)
1. Confirm that unit has a normal status.
2. Connect test pointTRM5-3 (FNVEL) to an oscilloscope.
3. Adjust potentiometer RV12 so that TRM5-3 signal is OV ±50mV with linear
mode and without seek command on Cylinder O.
)
B03P·4760-0111A ... 01
6·25
)
Section 7
)
I
I
Spare Parts List
)
7. SPARE PARTS LIST
7.1 SPARE PARTS LIST
Refer to Table 7-1.
Table
Item
7·' Spare Parts List
Designation
I
Specification
1
Controller F(KGFM) PC8 Assembly
8168-9830-0010A#U
2
Controller O(CZOM) PCM Assembly
8168-9340-0020A#U
3
Power Amp Q(TVQM) PC8 Assembly
8168-9250-0010A#U
B03P-4760-0111A ... Ol
7-1
)
Section 8--ICDetails
8. IC DETAI lS
8.1 INTRODUCTION
This section describes functions of TTL, ECl, Linear and FUJITSU Proprietary IC's.
8.2 lOGIC CONVENTIONS AND SYMBOLOGY
8.2.1 TTL logic
M233XK Micro Disk Drive uses +5V Transistor-Transistor-logic. TIL logic is
defined in terms of standard POSITIVE lOGIC using the following definitions:
High = Logical "1"
Low = Logical "0"
The input/output logic of TTL are defined as follows:
(A) TTL Low Power Schottky IC Level
+7.0V
--,.......,.......,....~~.....-,.......,-
+5.25V
+2.0V
+D.8V
-O.3V
~~\SS\SSSSS~~.4V
"0"
INPUT
. Figure 8-2·'
OUTPUT
Low Power Schottky
Ie Level
B03P·4760·0111A ... Ol
8·1
(B) TTL Schottley IC level
+S.SV
......,....,.....,......,..-.-...,......,......,..- +5.25V
~/~
/;~+2.7V
/
+2.0V
+O.8V
t O.3V
"0"
-O.3V
INPUT
OUTPUT
Figure 8-2·2 TTL. Schottky
Ie Level
8.2.2 Eel logic
M233XK Mirco Disk Drive uses -S.2V ECl (Emitter-Coupled-logic). The high
impedance of the logic (input to differential amplifier) coupled with the low
impedance of the driving source (emitter·follower output) allows high DC fan~out.
High-speed operation and high fan-out is possible because all circuits are designed
'to operate in a 50 ohm system. Complementary outputs cause a function and its
complement to appear simultaneously at the device output, without the use of
external inverters. In a M233X each output is terminated by resistors. ECl logic
is defined in terms of standard POSITIVE lOGIC using the following definitions:
High = logical "1"
low = logical "0"
8·2
B03P·4760·0111A ... Ol
)
The input/output logic levels of Eel are defined as follows:
"
)
~-O.81V
-O.S1V
"1"
-O.9SV
-1.105V
-1.475V
.~~
"0"
~-1.63V
"
'.~
'
-1.S5V
INPUT
-1.S5V
OUTPUT
Figure 8-2-3 Eel logic Level'
8.2.3 Logic Symbology
The following conventions are provided to aid in understanding the symbology
used in this manual.
1) TTL
A
B
A
B
This indicates AND gate.
---11 )
_D-v
o
y= A'B
v
This indicates OR gate.
Y= A+B
A circle placed on any input line or on
the output line indicates that logical
"a" is the significant. state.
The absence of a circle, "1" is the significant state.
B03P-4 760-0111 A ... 01
8-3
2) Eel
A
I
B
r:
This indicates AND/NAND Gate.
Y=A'B""Z
A
This indicates OR/NOR gate.
Y=A+B=Z
8
o
This is equivalent to TTL.
3) All logic symbols on each logic diagram are identified by a sequential numbering and element type code.
For example:
M7S"
----~~~---M75*
LSOO
Fa
Sequential part number ON the parts list.
Abbreviation (marking) of the element code.
Physical location of element on p.e.B. assembly.
8.3 IC INTERCHANGEABILITY Gj)IDE
8.3.1
TTL IC Interchangeability
Table 8·3·' TTL Interchangeability
FUJITSU
Part Number
Direct
Replacement
Code
I
I
Functions
MB74LSOOM
L500
SN74L500N
Quad 2·;nput NAND
i
MB74LS02M
LS02
SN74LS02N
Quad 2·input NOR
I
MB74LS04M
L504
SN74LS04N
Hex Inverter
I
SN74LS05N
Hex Inverter with Open Collector
I
I
I
I
I
MB74LS05M
LS05
MB74LS08M
LS08
SN74LS08N
Quad 2·input AND
I
LS10
SN74LS10N
Triple 3·input NAND
I
!I
MB74LS10M
I
I
MB74LS11M
!
I..S11
SN74LS11N
Triple 3·input AND
MB74LSl4M
I
LS14
SN74LS14N
Hex Schmitt·Triggered Inverter
SN74LS27N
Triple 3·input NOR
5N74LS32N
Quad 2·input OR
MB74L527M
!
L527
I
MB74L532M
8-4
Page
I
!
L532
I
B03P-4760·01 11 A ... O1
I
!
I
i
Table 8-3-1 TTL Interchangeability (Continued)
FUJITSU
'Part Number
Direct
Replacement
Code
Functions
MB74LS37M
LS37
SN74LS37N
Quad 2-input NAND Buffer
MB74LS42M
LS42
SN74LS42N
4-line-to·10·line Decoder
MB74LS51M
LS51
SN74LS51N
Dual 2-wide 2-input AND-OR
INVERT
MB74LS54M
LS54
SN74LS54N
4-wide AND-OR-INVERT
MB74LS74AM
LS74
SN74LS74AN
Dual D-type Positive-Edge-Triggered
Flip-Flop
MB74LS85M
LS85
SN74LS85N
4-bit Magnitude Comparator
MB74LS86M
LS86
SN74LS86N
Quad 2·input EOR
SN74LS123N
Dual Retrigerable Monostable
Multivibrator with Clear
-
LS123
.
MB74LSl48M
LSl48
SN74LS148N
8-to-3 Priority Encoder
MB74LS153M
LS153
SN74LS153N
Dual 4-line-to-1-line Data
Selector/Mu Itiplexer
MB74LS161AM
LS161
SN74LS161AN
4-bit Binary Counter
MB74LS164M
LS164
SN74LS164N
8-bit Shift Register
MB74LS174M
LS174
SN74LS174N
Hex D-type Flip-Flop
MB74LS175M
LS175
SN74LS175N
Quad D-type Flip-Flop
MB74LS191M
LS191
SN74LS191N
4·bit Binary Up6Down Counter
-
LS221
SN74LS221N
Dual Monostable Multivibrator
with Clear
-
LS279
SN74LS279N
Quad S·R Latch
LS283
SN74LS283N
4·bit Fu Ii Adder
LS393
SN74LS393N
Dual 4-bit Binary Counters
MB434M
434
SN75451BP
MB436M
436
SN75453BP
LX16
SN75452BP
Dual 2·input AND Buffer with
Open·co liector
Dual 2·input OR Buffer with
Open-collector
Dual 2·input NAND Buffer with
Open-collector
MB84020BM
4020
MC14020BCP
14·Bit Binary Counter
MB74S00M
LH01
SN74S00N
Quad 2·input NAND
MB74S04M
LH04
SN74S04N
Hex Inverter
MB74S08M
S08
SN74S08N
Quad 2·input AND
-
LH10
SN74S112N
Dual J·K Negative-Edge.Triggered
Flip-Flop with Preset and Clear
-
LH2~
SN74S124N
Dual VCO
MB74S37M
S08
SN74S37N
Quad 2·input AND
MB74S51M
LH06
SN74S51N
Dual 2·wide 2·input AND·OR·
INVERT
-
S64
SN74S64N
4·2·3·2·input AND-OR·INVERT
S74
SN74S74N
Dual D·type Positive·Edge·
Triggered Flip·Flop
-
LH07
SN74S133N
13·input NAN D Gate
LH28
SN74S: 74N
Hex D·type Flip-Flop
LX32
SN7406N
Hex I nvetter Buffer
MB74LS283M
-
-
MB74S174M
Note 1)
2)
Remark
Direct Replacement is device from Texam Instruments Inc. except 4020.
Direct Replacement of 4020 is a device from MOTOROLA Semiconductor Product Inc.
B03p·4760·0111A ... Ol
8·5
8.3.2
EeL Ie Interchangeability
Table 8-3-2 Eel Interchangeability
FUJITSU
Part Number
Direct
Code
Functions
Replacement
MB10174C
174
MC10174L
Dual 4-to-' Multiplexer
MB10102C
102
MC10l02L
Quadruple 2-;nput NOR
MB10105C
105
MC10105L
Tfiple 2-3·2 Input ORINOR
MB10116C
116
MC10116l
Triple Receiver
MB10124C
124
MC10124L
Quadruple TTL to ECL Translator
MB10125C
125
MC10125l
Quadruple ECl to 'TTL Translator
MB10131C
131
MC10131 L
Dual O·type Master·Slave Flip-Flop
MB10101C
101
MC10101 L
Quad OR·NOR Gates
Remark
Note: Direct replacement is a device from MOTOROLA Semiconductor Prod oct inc.
8.3.3
Linear Ie Interchangeability
Table 8-3-3 Linear Ie Interchangeability
FUJITSU
Part Number
Code
MB3607M
A1458
MB4002M
A4002
~PC251C
(NEC)
Functions
High Speed Voltage Comparator
j.!PC271C (NEC)
311-type Voltage Comparator
A08:!
HA 17082PS
(HITACHI)
082·type·J·FET Dual Operational
Amplifier
A399
~PCl77C
(NEC)
339-type Voltage Comparator
A6l0
~PC610D
(NEC)
8-bit D/A Converter
A7812
A7952
3450
75108A
75110
3107
FUJITSU Proprietary
Remark
Dual 741·type Operational Amplifier
A311
A201
8.3.4
Direct
Replacement
DG201BK
(Siliconix)
,uPC14312H
(NEC)
/lPC16352H
(NEC)
MC3450L
(MOTOROLA)
SN75108AN
(Tl)
SN75110AN
(Tl)
H0103107
(HITACHI)
Quad SPST Analog Switch
7812-type
-I- 1 2V
Regu lator
7952-type -S.2V Regulator
Quad line Receiver
Dual line Receiver with
Ooen-co lIector
Dual Line Driver
ECL Voltage Controlled Oscillator
Ie
Table 8·3-4 FUJITSU Proprietary Ie List
FUJITSU
Classification
Part Number
MB4303C
A4303
MB4311C
A4311
MB4316C
A4316
MB4319C
A4319
MS1S238C
MB43121CR
Functions
Ramark
Code
15238
Analog
Master-S Iice
Analog
Master-Slice
Analog
Master-Slice
Analog
Master-Slice
Bipolar
500-Qate
AGC Amplifier
Peak Detecto r
ReadIWrite Bus Switch
Peak Hold
Servo Control Logic
DV18
Hybrid IC
Clock Driver
AM121
Analog
Master-Slice
Pu Ise Shaper
B03P-4760-0111A ... Ol
I
II
8.4 FUJITSU PROPRIETARY Ie DETAIL
(1) MB4002M
High Speed Differential Comparator
The MB4002M is a Differential Voltage Comparator .intended for applications requiring high accuracy and fast response times. The device is useful
as a variable threshold Schmitt trigger, a pulse height discriminator, a voltage comparator in high-speed AID converters, a memory sense amplifier or
a high-noise immunity line receiver. The output of the comparator is compatible with all integrated logic forms.
TOP VIEW
1: GND
2: INPUT (+)
3: INPUT (-)
4:
v-
5: NC
6: NC
7: OUTPUT
8: v+
(2) MB4303C
AGC Amplifier
The MB4303C is a Automatic-Gain-Control Amplifier with Differential
Inputs and Outputs. It contains another Differential Amplifier.
TOP VIEW
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11 :
'2:
'3:
'4:
'5:
'6:
B03p·4760-0' l'A ... O,
INPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
VR
VAGC
VG (GND)
Vee
INPUT1
INPUT1
GA
GB
VBB
INPUT2
Vee
8-7
(3) MB4311 C
Peak Detector
TOP VIEW
1:
6:
OUT1
OUT1
IN2
IN2
VH
VL
7:
SO
8:
GND
Vee
AGCG
CLA
,CAP
VAGC
IN'
IN1
Vee
2:
3:
4:
5:
9:
10:
11:
12:
13:
14:
15:
16:
(4) MB4316C
Read/Write Bus Switch
TOP VIEW
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
11:
12:
13:
14:
15:
16:
8·8
B03p·4760·0111A ... Ol
Vee2
GAN2
GANl
INS
IN4
OUTS
OUT6
GND
Veel
IN2
IN3
OUT4
OUT3
IN'
OUT2
OUT'
\/
(5) MB4319C
Peak Hold
1: REG1
2: VELOCITY
3: *GATE1
4: *GATE2
5: . *GATE3
.6: *GATE4
7: CARIE
8: GND
9: VEE
10: REG3
11: EVEN2
12: 0002
13: EVEN1
14: 0001
15: REG2
16: Vee
TOP VIEW
PH:
CC:
Peak Hold
Constant Current
(6) MB43121 C Pulse Shaper
)
This LSI has the following functions.
• Pulse Shaper (Analog to Digital Converter)
• Channel Select
• Write Data Driver
,-',
'''-'
(.~:,
-- ..-- , ,
;
~.
\
33 .• I
,..-,
I
I
I
'-
)
~
I
I·
..
; :
-'
,-!
,I -. I
\
I
~
.. 37'--
:-- , -'.-,I C~19
~.
I
I
)
B03P'4760·0111A ... 01
8·9
(7) DV18
Clock Driver
1:
16
.
15
13
14
12
11
10
.-,
......
,
'-'
,~,
'..... '
,-,
'.. <#'
2
3
9
3
4
5
....'-.'
.,-..''
6
7
N.C.
2:
ENS
3:
4:
5:
6:
7:
XEl
N.C .
N.C.
N.C.
XEZ
8:
9:
10:
11:
12:
13:
14:
15:
GND
N.C.
N.C.
N.C.
N.C.
OUT
N.C.
Vee
16:
N.C.
(8) M 815207C (8 ipolar 500 Gates LS I)
This LSI has the following functions.
• NRZ to MFM Encoder with Write Compensation
• MFM to NRZ Decoder (not used)
• PLONFO Phase Comparator (not used)
• Physical I ndex Detector (not used)
• Fault Detector
The package of 8500 LSI is shown in Figure 8-4-1. the pin assignment is
shown in Table 8-4-1, and the block diagram is shown in Figure 8-4-2.
8·'0
B03p·4760·0111A ... Ol
)
(9) MB15238C (Bipolar 500 Gates LSI)
This LSI has the following functions.
• PLO Latch
• Divide and Timing Counter
• Peak Hold Gate Decoder
• Index/Guard Band Pattern Decoder
• Guard Band Detector with Counter
• Polarity Control Gates Decoder
• 2-bit Full Adder
The package of B500 LSI is shown in Figure 8-4-1, the pin assignment is
shown in Table 8-4-1, and the block diagram is shown in Figure 8-4-2.
fRIT 641
(Top View)
Figure 8-4-1 8500 LSI Package
Table 8-4-1
Pin
No.
1/0
1
NC
2
9
a
a
a
a
a
a
a
a
10
I
11
I 0
12
3
M81S238C Pin Assignment
Name of
Terminal
Pin
No.
1/0
Name of
Terminal
Pin
No.
1/0
Name of
Terminal
Pin
No.
1/0
Name of
Terminal
-------
17
0
• SQN
33
0
* CNT15
49
a
• SQI
PLaCLK
18
a
• INX
34
I
*OGBQ
50
0
* FIGBl
• GTl
19
I
* CARl
35
a
CT7
51
I
NGTQ
* CT15
20
• alNX
36
I
vca2
52
• GT4
21
• SNI
37
NC
• GT3
22
• RSTGB
38
I
PWRDY
54
V
GND
CNT4
39
a
-------
53
a
I a
CT8F
55
• SNN
• EQUAL
40
a
a
• PCLMP
41
• MCLMP
42
PLaLT
23
• aGBP
24
SFRGA
25
• SEL 1 F
26
a
a
a
a
a
a
a
SFRGE
27
0
• PARl
a
CNTl
28
I
13
I
• RSTGB
29
14
I
• HDLD
30
a
a
15
I
NQGTZ
31
I
16
I
• CAR2
32
I
• MSDT
4
5
6
7
8
j
i
• MSDT
• EINX
XPL
GND
56
a
• GT2
57
I
• aFTRK
0
• PLaL T
58
I
• SVPMS
43
a
• IGBIP
59
a
• IGBl
• SKC
44
NC
I
• IGB2Q
• aGE
45
a
·IGB2P
61
VSS
·IGB2
46
I
-------
60
CNT7
62
• IGB1Q
47
V
+5V
48
I
• PLaL T
B03P-4 760-0111A ... 01
1
I
I
+5V
I
vcal
63
a
CNT64
64
I
PLaLT
8-11
.-
-.
--
PLOLT
~SVPMS
58
64
07
4li
47
PLOL
I
I
r-
PLO
Latch
• PLOL T
eT7
PLOL
• PLOLT
46
I
I
VCOl
VC02
·SEL1F
PWRDV
62
36
10
PL01F
CT.8F
Divide!
Timing
Counter
and
Decoder
38
CT7
·CT~
02
39
PL01F
CT.SF
35
--.0.4
CT7
'CT15
33
C; 1
• GT2
I
);!
• r.T3
• AT4
41
06
05
•
•
•
•
09
SFRGA
11
SFRGE
I
GT1
GT2
GT3
GT4
I
,,
'--
11
8
I
I
I
I
I
I . CNT15
i • MSDT
L
tG8
Reset
Counter
'---' t-
r-[
I
Shift
Register
1
i,
i ,
. "I
CNT1
--.C.NT4
;
...c.NIfi.4
• RSTG8
I
,
I
I'
:
i
.
-I
C.
• CAR2
• CARl
'~GaP
!
I III~
,
• SKC
"I
I
12
AND
GaTes
• SK!:;
B03P·4760·01 1 lA ... Ol
CNT1
CNT4
CNT64
, RSTG8
.~
I!
22
13
27
4
26
Full
Addp.rs
IG81
tG82
OG8
FIGST
I
56
Figure 8-4·2 MB1S238C Block Diagram
8·12
29..
-~
Lalct>
T6
•
•
•
•
::m
4
• OFTRK
i
59
Decoder
19
!'>
Gard 8and
Delect
15
°eAS:2 ,
'eFTR
4
~1
• PAR1
5i
4
• OINX
• EINX
• INX
'tGS1P
• 188~P
'0 B
• MSDT
~
• R ST,
G6
NOGTZ
NGTO
20
~
32·
I
I
,
I
Pettern
Detect
Index
Detect
!!:~
I
-
0
25
24
r
•
•
•
,
"
PAR1
501
SNI
SNN
SQN
XPL
• MCLMP
• PCLMP
, EQUAL
)
Section 9
Parts List
9, PARTS LIST
...
N
M
N
:E
...0,
N
9- 1
I
-1I
B03p·4760·01 1 1A .. _01
Table 9-1 M2321K/M2322K Micro Disk Drive
INDEX
NO.
COMPOSIT ION
S. OUANTITY
SPECIFICATION
DESCRIPTION
1
B03B-4765-BOOIA
M2331 K Micro-Disk Drive
1
B03B-4765-B003A
M2333K Micro-Disk Drive
1
1
B030-4760- TOOIA
M2331K Disk Drive Unit
1
1
B030-4 760-T002A
M2333K Disk Drive Unit
2
1
B030-4760-Vj31A
Frame Unit
3
1
C370-1270-0002
Manufacturing Name Label
4
1
C370-1270-0003
Revision Label
o
5
1
B03B-4740-E002A
Fan Unit (AC 115V) Option
-0
5
1
B030-4740-E005A
(DC 24V)
6
1
B03B-4760-E402A
CD
W
j,.
-...J
0>
o
6
~
a
(0
N
Dual Channel Option
Option
CHARACTER
REMARK
REVISION
10
W
6-9~
6-8 4
-'--,/
6-7
I
2-10
OJ
o
2-ii-21
W
"V
.;..
-..J
m
o
6
}>
2-15
o
5-1
e:><:::> "'-..
<::> •
2-26
<2-2:1>
IyL/,//.J
2-22
'--
~--...---
-,-
'-.0/
Table 9-2 Frame Unit (Basicl
INDEX
NO.
ro
o
w
".....
.j,.
m
o
6
~
~
:t>
6
ID
.j,.
COMPOSITION
S. QUANTITY
SPECIFICATION
DESCRIPTION
1
1
B030-4760- TOOIA
M2321 K Disk Drive ,Unit
1
1
B030-4760-T002A
M2322K Disk Drive Unit
2
1
B030-4760-V331A
Frame Unit
B030-4740-X310A
Plate
2·1
1
2·2
2
F6-SB D-4x6S-M-N 11 A
Screw
2·3
1
B030-4740-X309A
Plate
2-4
2
F6-SBD-4x6S-M-NI1A
Screw
2-5
1
B030-4740-W304A
Stopper
2-6
2
F6-SBD-4xBS-M -Nil A
Screw
2-7
1
B030-4740-W305A
Stopper
2-B
2
F6-SB D-4xBS-M-N 11 A
Screw
2-9
1
B030-4760-W332A
Frame Assy.
2-10
1
C300:"0010-X 176
Screw
2-11
1
B030-4760-W333A
Frame Assy.
2-12
1
C300-0010-X176
Screw
2-13
1
B030-4740-X312A
Hinge
2-14
1
B030-4740-X311A
Stopper
Con troll er 0
2·15
1
B 16B-9340-0020A #U
2-16
6
F6-SBD-4x6S-M-N 11 A
Screw
2-17
1
B 16B -9250-00 1OAHU
Power Amplifier Q
2-18
2
B030-4740-X046A
Bushing
2-19
2
F6-SBD-3x8S-M-N 11 A
Screw
2-20
1
B660-0625-T318A
Cable
2-21
1
B660-1 060-T118A #L80ROO
Cable
2-22
1
B16B-9830-0010A#U
Controller F
2-23
6
F6-SBD-3x6S-M-NI1A
Screw
2-24
2
B660-1990-T036AHL70ROO
Cable
2·25
2
F6-SBD-3x6S-M-Nll A
Screw
2-26
1
B030-4760-X331A
Cover
2-27
1
B030-4740-X047A
Cover
2-28
2
F6-SBD-4x6S-M-Mll A
Screw
3
1
C370-1270-0002A
Nameplate
4
1
C370-1270-0003A
Revision Label
CHARACTER
REMARK
REVISION
,
f.<
~
.'
"
--
:
."
..;
an
i
~
N
.1::
c
..
:::::I
'"
(lI
9-5
B03P-4760-01 11A ... 01
E
~
U.
N
eft
!
:=
.!iP
u.
)
Table 9-2 Frame Unit (Option I
..
INDEX
NO.
COMPOSITION
& OUANTITY
- - _..
SPECIFICATION
DESCRIPTION
5
1
1
B03B-4740-E002A
Fan Unit
5
1
1
B03B-4740-E004A
Fan Unit
5·1
1
B030-4740-V201 A
Fan Assy.
5·2
1
F6-SBD-4xBS-M-NII A
Screw
5·3
1
8030-4740--W204A
Retainer
F6-SBD-4xl0S-M-NI1A
Screw
B370-0950-0~09A
Label
Dual Channel
5·4
5·5
CHARACTER
_.-
--_._--_..-
REMARK
REVISION
r-
1
1
8038-4760-E402A
6·1
·1
B030-4740-X401A
Frame
6·2
1
F6-·S8D-3x6S-·M-NII A
Screw
6
1
.
6'3
4
B 16B-9930-001 OA #U
Crosscall G
o
6·4
1
F6--SBD-3x5S-M-NI1A
Screw
Cable
!D
W
-0
6·5
i
B660-1060-T096A#L2BORO
-...J
6·6
1
8660-1060-T097 A#L300RO
Cable
o
6·7
1
8030-4740-X404A
Cover
6·8
F6-S8D-3x6S-M-NI1A
Screw'
»
6·9
8370-0950-0454A
Label
~
en
6
o
"
;t
'i;
,
,
.
..
,
J
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