Bq24780S 1 To 4 Cell Hybrid Power Boost Mode Battery Charge Controller (Rev. C) BQ24780
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Product Folder Order Now Support & Community Tools & Software Technical Documents bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 bq24780S 1- to 4-Cell Hybrid Power Boost Mode Battery Charge Controller With Power and Processor Hot Monitoring 1 Features 2 Applications • • • • • 1 • • • • • • • • Industrial Innovative Charge Controller With Hybrid Power Boost Mode – Adapter and Battery Provides Power to System Together for Intel® CPU Turbo Mode – Ultra-Fast Transient Response of 150 µs to Enter Boost Mode – Hybrid Power Boost Mode from 4.5- to 24-V System – Charge 1- to 4-Cell Battery Pack from 4.5- to 24-V Adapter High Accuracy Power and Current Monitoring for CPU Throttling – Comprehensive PROCHOT Profile – ± 2% Current Monitor Accuracy – ± 5% System Power Monitor Accuracy (PMON) Automatic NMOS Power Source Selection from Adapter or Battery – ACFET Fast Turn on in 100 µs Programmable Input Current, Charge Voltage, Charge and Discharge Current Limit – ±0.4% Charge Voltage (16-mV step) – ±2% Input Current (128-mA/step) – ±2% Charge Current (64-mA/step) – ±2% Discharge Current (512-mA/step) High Integration – Battery LEARN Function – Battery Present Monitor – Boost Mode Indicator – Loop Compensation – BTST Diode Enhanced Safety Features for Overvoltage Protection, Overcurrent Protection, Battery, Inductor, and MOSFET Short-Circuit Protection Switching Frequency: 600 kHz, 800 kHz, and 1 MHz Realtime System Control on ILIM Pin to Limit Charge and Discharge Current 0.65 mA Adapter Standby Quiescent Current for Energy Star Notebook, Ultrabook, Detachable, and Tablet PC Handheld Terminal Industrial and Medical Equipment Portable Equipment 3 Description The bq24780S device is a high-efficiency, synchronous battery charger, offering low component count for space-constrained, multi-chemistry battery charging applications. The bq24780S device supports hybrid power boost mode (previously called "turbo boost mode"). It allows battery discharge energy to system when system power demand is temporarily higher than adapter maximum power level. Therefore, adapter does not crash. The bq24780S device uses two charge pumps to separately drive N-channel MOSFETs (ACFET, RBFET, and BATFET) for automatic system power source selection. Through SMBus, system power management microcontroller programs input current, charge current, discharge current, and charge voltage DACs with high regulation accuracies. The bq24780S device monitors adapter current (IADP), battery discharge current (IDCHG), and system power (PMON) for host to throttle back CPU speed or reduce system power when needed. The bq24780S device charges 1-, 2-, 3-, or 4-series Li+ cells. Device Information(1) PART NUMBER bq24780S PACKAGE BODY SIZE (NOM) 4.00 × 4.00 mm2 WQFN (28) (1) For all available packages, see the orderable addendum at the end of the data sheet. RAC Adapter 4.5-24V SYS Enhanced Safety: OCP, OVP, FET Short N-FET Driver N-FET Driver Adapter Detection SMBus Controls V & I with high accuracy SMBus bq24780S Hybrid Power Boost Charge Controller Battery Pack RSR 1S-4S HOST IADP, PROCHOT, PMON, IDCHG Integration: Loop Compensation; Soft-Start Comparator, BTST Diode 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 3 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings.............................................................. 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 6 Timing Requirements .............................................. 11 Typical Characteristics ............................................ 13 Detailed Description ............................................ 14 7.1 Overview ................................................................. 14 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 16 7.4 Device Functional Modes........................................ 22 7.5 Programming........................................................... 23 7.6 Register Maps ......................................................... 25 8 Application and Implementation ........................ 36 8.1 Application Information............................................ 36 8.2 Typical Applications ................................................ 36 9 Power Supply Recommendations...................... 44 10 Layout................................................................... 44 10.1 Layout Guidelines ................................................. 44 10.2 Layout Examples................................................... 45 11 Device and Documentation Support ................. 48 11.1 11.2 11.3 11.4 11.5 Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 48 48 48 48 48 12 Mechanical, Packaging, and Orderable Information ........................................................... 48 4 Revision History Changes from Revision B (April 2015) to Revision C • Page Full data sheet to product folder............................................................................................................................................. 1 Changes from Revision A (April 2015) to Revision B Page • Changed the Description for pin 22 (GND) in the Pin Functions table................................................................................... 4 • Changed the Thermal Pad to PowerPAD in the Pin Functions table..................................................................................... 4 • Changed 16X to 20X on the SRP and SRN pins of the Functional Block Diagram ............................................................ 15 • Changed C4 From: 0.01 μF To: 0.1 μF in Figure 17 ........................................................................................................... 36 Changes from Original (April 2015) to Revision A Page • Changed V(ACOC) in the Electrical Characteristics, MIN From: 190% To: 180%, MAX From: 215% To: 220% ..................... 9 • Changed "ChargeOption() bit [0] = 0" To: REG0x12[0] in Enable and Disable Charging.................................................... 17 • Changed " (REG0x12[1])" To: (REG0x12[0]=1) in Enable and Disable Charging ............................................................... 17 • Changed " REG0x12" To: "REG0x12[0]" in Battery Charging ............................................................................................ 22 • Changed Bit [10:9] in Table 9 From: 11: 8 ms To: 11: 800 µs ............................................................................................ 30 • Added sentence to Bit [7:6] in Table 9 " If REG0x15() is programmed..." ........................................................................... 30 • Changed text in Bit [5] of Table 9 From: "write 0x3C[2] = 1." To: "write 0x3C[2] = 0." ........................................................ 30 • Deleted text from Bit [5] of Table 9 "This function is not available in 1s battery."................................................................ 30 2 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 5 Pin Configuration and Functions VCC PHASE HIDRV BTST REGN LODRV GND 28 27 26 25 24 23 22 RUY Package 28-Pin WQFN Top View ACN 1 21 ILIM ACP 2 20 SRP CMSRC 3 19 SRN ACDRV 4 18 BATDRV Thermal Pad 13 14 CMPOUT BATPRES CMPIN 15 12 7 SCL IADP 11 TB_STAT SDA 16 10 6 PROCHOT ACDET 9 BATSRC PMON 17 8 5 IDCHG ACOK Pin Functions PIN DESCRIPTION NAME NUMBER ACN 1 Input current sense resistor negative input. Place an optional 0.01-µF ceramic capacitor from ACN to GND for common-mode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential mode filtering. ACP 2 Input current sense resistor positive input. Place a 0.1-µF ceramic capacitor from ACP to GND for commonmode filtering. Place a 0.1-µF ceramic capacitor from ACN to ACP to provide differential-mode filtering. CMSRC 3 ACDRV charge pump source input. Place a 4-kΩ resistor from CMSRC to the common source of ACFET (Q1) and RBFET (Q2) to limit the inrush current on CMSRC pin. ACDRV 4 Charge pump output to drive both adapter input N-channel MOSFET (ACFET) and reverse blocking N-channel MOSFET (RBFET). ACDRV voltage is 6 V above CMSRC when ACOK is HIGH. Place a 4-kΩ resistor from ACDRV to the gate of ACFET and RBFET limits the inrush current on ACDRV pin. ACOK 5 Active HIGH AC adapter detection open drain output. It is pulled HIGH to external pullup supply rail by external pullup resistor when a valid adapter is present (ACDET above 2.4 V, VCC above UVLO but below ACOV and VCC above BAT). If any of the above conditions is not valid, ACOK is pulled LOW by internal MOSFET. Connect a 10-kΩ pullup resistor from ACOK to the pullup supply rail. ACDET 6 Adapter detection input. Program adapter valid input threshold by connecting a resistor divider from adapter input to ACDET pin to GND pin. When ACDET pin is above 0.6 V and VCC is above UVLO, REGN LDO is present, ACOK comparator, input current buffer (IADP), discharge current buffer (IDCHG), independent comparator, and power monitor buffer (PMON) can be enabled with SMBus. When ACDET is above 2.4V, and VCC is above SRN but below ACOV, ACOK goes HIGH. IADP 7 Buffered adapter current output. V(IADP) = 20 or 40 × (V(ACP) – V(ACN)) The ratio of 20x and 40x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IADP pin to GND. This pin can be floating if this output is not in use. IDCHG 8 Buffered discharge current. V(IDCHG) = 8 or 16 × (V(SRN) – V(SRP)) The ratio of 8x or 16x is selectable with SMBus. Place 100-pF (or less) ceramic decoupling capacitor from IDSCHG pin to GND. This pin can be floating if this output is not in use. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 3 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Pin Functions (continued) PIN NUMBER PMON 9 Buffered total system power. The output current is proportional to the total power from the adapter and battery. The ratio is selectable through SMBus. Place a resistor from PMON pin to GND to generate PMON voltage. Place a 100-pF (or less) ceramic decoupling capacitor from PMON pin to GND. This pin can be floating if this output is not in use. PROCHOT 10 Active low, open-drain output of the processor hot indicator. The charger IC monitors events like adapter current, battery discharge current. After any event in the PROCHOT profile is triggered, a minimum 10-ms pulse is asserted. SDA 11 SMBus open-drain data I/O. Connect to SMBus data line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pullup resistor according to SMBus specifications. SCL 12 SMBus open-drain clock input. Connect to SMBus clock line from the host controller or smart battery. SMBus communication starts when VCC is above UVLO. Connect a 10-kΩ pullup resistor according to SMBus specifications. CMPIN 13 Input of independent comparator. Internal reference, output polarity and deglitch time is selectable by SMBus. Place a resistor between CMPIN and CMPOUT to program hysteresis when the polarity is HIGH. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. CMPOUT 14 Open-drain output of independent comparator. Place 10-kΩ pullup resistor from CMPOUT to pullup supply rail. Comparator reference, output polarity and deglitch time is selectable by SMBus. If comparator is not in use, CMPIN is tied to ground, and CMPOUT is left floating. BATPRES 15 Active low battery present input signal. Low indicates battery present, high indicates battery absent. The device exits the LEARN function and turns on ACFET/RBFET within 100 µs if BATPRES pin is pulled high. Upon BATPRES from LOW to HIGH, battery charging and hybrid power boost mode are disabled. The host can enable charging and hybrid power boost mode by write to REG0x14() and REG0x15() when BATPRES is HIGH TB_STAT 16 Active low, open-drain output for hybrid power boost mode indication. It is pulled low when the IC is operating in boost mode. Otherwise, it is pulled high. Connect a 10-kΩ pullup resistor from TB_STAT pin to the pullup supply rail. BATSRC 17 Connect to the source of N-channel BATFET. BATDRV voltage is 6 V above BATSRC to turn on BATFET. BATDRV 18 Charge pump output to drive N-channel MOSFET between battery and system (BATFET). BATDRV voltage is 6 V above BATSRC to turn on BATFET and power system from battery. BATDRV is shorted to BATSRC to turn off BATFET. Place a 4-kΩ resistor from BATDRV to the gate of BATFET limits the inrush current on BATDRV pin. SRN 19 Charge current sense resistor negative input. SRN pin is for battery voltage sensing as well. Connect SRN pin with a 0.1-µF ceramic capacitor to GND for common-mode filtering. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide differential mode filtering. SRP 20 Charge current sense resistor positive input. Connect a 0.1-µF ceramic capacitor from SRP to SRN to provide differential mode filtering. ILIM 21 Charge current and discharge current limit.VILIM = 20 × (VSRP – VSRN) for charge current and VILIM = 5 × (VSRN – VSRP) for discharge current. Program ILIM voltage by connecting a resistor divider from system reference 3.3-V rail to ILIM pin to GND pin. The lower of ILIM voltage and 0x14() (for charge) or 0x39 (for discharge) reference sets actual regulation limit. The minimum voltage on ILIM to enable charge or discharge current regulation is 120 mV. GND 22 IC ground. On PCB layout, connect to analog ground plane, and only connect to power ground plan through pad underneath IC. LODRV 23 Low-side power MOSFET driver output. Connect to low-side N-channel MOSFET gate. REGN 24 6-V linear regulator output supplied from VCC. The LDO is active when ACDET above 0.6 V, VCC above UVLO. Connect a ≥ 2.2-µF 0603 ceramic capacitor from REGN to GND. The diode between REGN and BTST is integrated. BTST 25 High-side power MOSFET driver power supply. Connect a 47-nF capacitor from BTST to PHASE. The diode between REGN and BTST is integrated inside the IC. HIDRV 26 High-side power MOSFET driver output. Connect to the high side N-channel MOSFET gate. PHASE 27 High-side power MOSFET driver source. Connect to the source of the high-side N-channel MOSFET. VCC 28 Input supply from adapter or battery. Use 10-Ω resistor and 1-µF capacitor to ground as a low pass filter to limit inrush current. A diode OR is connected to VCC. It powers charger IC from input adapter and battery. PowerPAD™ 4 DESCRIPTION NAME Exposed pad beneath the IC. Analog ground and power ground star-connected only at the PowerPAD plane. Always solder the PowerPAD to the board and have vias on the PowerPAD plane connecting to analog ground and power ground planes. It also serves as a thermal pad to dissipate the heat. Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) (2) SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC PHASE Voltage Differential voltage Voltage MIN MAX –0.3 30 –2 30 ACDET, SDA, SCL, LODRV, REGN, IADP, IDCHG, PMON, ILIM, ACOK, CMPIN, CMPOUT, BATPRES, TB_STAT –0.3 7 PROCHOT –0.3 5.7 BTST, HIDRV, ACDRV, BATDRV –0.3 36 BTST-PHASE, HIDRV-PHASE ACDRV-CMSRC, BATDRV-BATSRC –0.3 7 UNIT V V LODRV (2% duty cycle) –4 7 HIDRV (2% duty cycle) –4 36 V Voltage PHASE (2% duty cycle) –4 30 V Voltage REGN (5ms) –0.3 9 V Maximum differential voltage SRP–SRN, ACP–ACN –0.5 +0.5 V Junction temperature, TJ –40 155 °C Storage temperature, Tstg –55 155 °C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified pin. Consult Packaging Section of the data book for thermal limitations and considerations of packages. 6.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 V(ESD) (1) (2) Electrostatic discharge (1) Charged device model (CDM), per JEDEC specification JESD22C101 (2) UNIT ±2000 V ±500 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) SRN, SRP, ACN, ACP, CMSRC, VCC, BATSRC PHASE Voltage ACDET, SDA, SCL, LODRV, REGN, IADP, IDCHG, PMON, ILIM, ACOK, CMPIN, CMPOUT, BATPRES, TB_STAT PROCHOT MIN MAX 0 24 –2 24 0 6.5 –0.3 5 0 30 –0.4 +0.4 Junction temperature, TJ –20 125 Operating free-air temperature, TA –40 85 BTST, HIDRV, ACDRV, BATDRV Maximum difference SRP–SRN, ACP–ACN Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback UNIT V V °C 5 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 6.4 Thermal Information bq24780S THERMAL METRIC (1) RUY (WQFN) UNIT 28 PINS RθJA Junction-to-ambient thermal resistance 33.3 °C/W RθJCtop Junction-to-case (top) thermal resistance 29.7 °C/W RθJB Junction-to-board thermal resistance 6.5 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 6.5 °C/W RθJCbot Junction-to-case (bottom) thermal resistance 1.3 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 6.5 Electrical Characteristics 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPERATING CONDITIONS VVCC(OP) VCC/ACP/ACN operating voltage 4.5 24 V 19.2 V CHARGE VOLTAGE REGULATION VBAT(REG_RNG) Battery voltage 1.024 ChargeVoltage() = 0x41A0 16.8 –10°C-85°C –0.4% –40°C-125°C –0.5% ChargeVoltage() = 0x3130 VBAT(REG_ACC) Charge voltage regulation accuracy V 0.4% 0.5% 12.592 –10°C-85°C –0.4% –40°C-125°C –0.5% ChargeVoltage() = 0x20D0 V 0.4% 0.5% 8.4 –10°C-85°C –0.4% –40°C-125°C –0.6% ChargeVoltage() = 0x1060 V 0.4% 0.6% 4.192 V –10°C-85°C –0.5% 0.8% –40°C-125°C –0.7% 0.8% 0 81.28 CHARGE CURRENT REGULATION VIREG(CHG_RNG) Charge current regulation differential voltage VIREG(CHG) = VSRP – VSRN 4096 ChargeCurrent() = 0x1000 –2% Charge current regulation accuracy (SRN > 2.8 V) 512 ILGK(SRP-SRN) 6 SRP and SRN leakage mismatch Submit Documentation Feedback mA 10% 256 ChargeVoltage() = 0x20D0, 0x3031, 0x41A0 –16% ChargeVoltage() = 0x1060 –20% ChargeCurrent() = 0x0080 mA 3% –10% ChargeCurrent() = 0x0100 ChargeCurrent() = 0x00C0 2% –3% ChargeCurrent() = 0x0200 ICHRG(REG_ACC) mA 2048 ChargeCurrent() = 0x0800 mV mA 16% 20% 192 –20% mA 20% 128 mA –30% 30% –8 8 µA Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 Electrical Characteristics (continued) 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DISCHARGE CURRENT REGULATION V(IREG_CHG_RNG) Charge current regulation differential voltage VIREG(IDISCHG) = VSRN – VSRP ChargeCurrent() = 0x2000 ChargeCurrent() = 0x1000 I(DCHRG_REG_ACC) Discharge current regulation accuracy ChargeCurrent() = 0x0800 ChargeCurrent() = 0x0400 ChargeCurrent() = 0x0400 0 322.56 8192 –2% mV mA 2% 4096 –3% mA 3% 2048 –5% mA 5% 1024 –8% mA 8% 512 mA –10% 10% 0 80.64 INPUT CURRENT REGULATION V(IREG_DPM_RNG) Input current regulation differential voltage V(IREG_DPM) = V(ACP) – V(ACN) InputCurrent() = 0x1000 InputCurrent() = 0x0800 I(DPM_REG_ACC) Input current regulation accuracy InputCurrent() = 0x0400 InputCurrent() = 0x0200 ILGK(ACP-ARN) ACP and ACN leakage mismatch 4096 –2% mV mA 2% 2048 –3% mA 3% 1024 –5% mA 5% 512 mA –12% 12% –5 5 µA INPUT CURRENT SENSE AMPLIFIER V(IADP) IADP output voltage 0 3.3 I(IADP) IADPT output current 0 1 A(IADP) IADP sense amplifier gain V(IADP_ACC) Current sense amplifier gain accuracy V(IADP_CLAMP) IADP clamp voltage C(IADP) IADP output load capacitance V(IADP) / V(ACP-ACN), REG0x12[4] = 0 20 V/V V(ACP-ACN) = 40 mV –2% 2% V(ACP-ACN) = 20 mV –4% 4% V(ACP-ACN) ≥ 10 mV –7% 7% V(ACP-ACN) ≥ 5 mV –20% 20% V(ACP-ACN) ≥ 2.5 mV –30% 30% V(ACP-ACN) ≥ 1.5 mV –40% 40% 3 With 0 to 1mA load V mA 3.3 V 100 pF DISCHARGE CURRENT SENSE AMPLIFIER V(IDCHG) IDCHG output voltage 0 3.3 I(IDCHG) IDCHG output current 0 1 A(IDCHG) Current sense amplifier gain V(IDCHG)/V(SRN-SRP), REG0x12[3] = 1 V(SRN-SRP) = 40 mV V(IDCHG_ACC) Current sense output accuracy V(IDCHG_CLAMP) IDCHG clamp voltage C(IDCHG) IDCHG output load capacitance Copyright © 2015–2017, Texas Instruments Incorporated 16 –5% V/V 5% V(SRN-SRP) = 20 mV –9% 9% V(SRN-SRP) = 10 mV –17% 17% V(SRN-SRP) = 5 mV –34% 34% 3 With 0 to 1mA load V mA 3.3 V 100 pF Submit Documentation Feedback 7 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Electrical Characteristics (continued) 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM POWER SENSE AMPLIFIER V(PMON) PMON output voltage 0 3.3 V I(PMON) PMON output current 0 160 µA A(PMON) PMON system gain V(PMON)/(PIN + PBAT, REG0x3B[9] = 1 1 Adapter Only with System Power = 19.5V/45W Adapter Only with System Power = 12V/24W VPMON_ACC PMON Gain Accuracy (REG0x3B[9]=1) –4% µA/W 4% –6% 6% Adapter Only with System Power = 5V/9W –10% 10% Battery Only with System Power 11V/44W –4.5% 4.5% Battery Only with System Power 7.4V/29.8W –7% 7% Battery Only with System Power 3.7V/14.4W –10% 10% 3% 3.3% V 100 pF 6.3 V VPMON_CLAMP PMON clamp voltage CPMON Maximum output load capacitance With 0 to 1 mA V(REGN_REG) REGN regulator voltage VVCC > V(UVLO), V(ACDET) > V(wakeup_RISE) 5.7 6 I(REGN_LIM_Charging) REGN current limit when in charging mode V(REGN) = 0 V, VVCC > V(UVLO), in charging mode 80 100 VLDO(DROPOUT) REGN output voltage in dropout VVCC = 5 V, ILOAD = 20 mA 4.4 4.6 I(REGN_LIM) REGN current limit when not in charging VREGN = 0 V, VVCC > V(UVLO), Not in charging mode 13 I(REGN_TSHUT) REGN output under thermal shutdown VREGN = 5V 13 C(REGN) REGN output capacitor ILOAD = 100 µA to 50 mA REGN REGULATOR mA 4.75 V mA 23 mA 2.2 μF VCC UNDER VOLTAGE LOCKOUT COMPARATOR VVCC(UVLO) Input undervoltage rising threshold VVCC(UVLO_HYS) Input undervoltage falling hysteresis VCC rising 2.4 2.6 2.8 200 V mV QUIESCENT CURRENT VBAT = 16.8 V, VCC disconnected from battery, REG0x12[15] = 1 Current with battery only, TJ = 0 to 85°C, ISRN + ISRP + IBATSRC + IPHASE + IVCC + IACP + IACN IBAT Adapter current, IVCC + IACP + IACN + IACDRV + ICMSRC IAC 5 VBAT = 16.8 V, VCC connected from battery, REG0x12[15] = 1 25 VBAT = 16.8 V, VCC connect to battery, BATFET on, REG0x12[15] = 0, REGN = 0 V, Comparator and PROCHOT enabled, PMON disabled, TJ = 0 to 85°C 700 800 V(VCC_ULVO) < VVCC < V(ACOVP), V(ACDET) > 2.4 V, charge disabled 0.65 0.8 V(VCC_ULVO) < VVCC < V(ACOVP), V(ACDET) > 2.4 V, charge enabled, no switching 1.6 3 V(VCC_ULVO) < VVCC < V(ACOVP), V(ACDET) > 2.4 V, charge enabled, switching, MOSFET Qg 4nC 10 44 μA mA ACOK COMPARATOR V(ACOK_RISE) ACOK rising threshold VVCC > V(VCC_UVLO), ACDET ramps up V(ACOK_FALL) ACOK falling threshold VVCC > V(VCC_UVLO), ACDET ramps down 2.375 2.4 2.425 V 2.3 2.345 2.395 V(WAKEUP_RISE) WAKEUP detect rising threshold VVCC > V(VCC_UVLO), ACDET ramps up V 0.57 0.8 V(WAKEUP_FALL) WAKEUP detect falling threshold VVCC > V(VCC_UVLO), ACDET ramps down 0.3 0.51 V V VCC to SRN COMPARATOR (VCC_SRN) V(VCC-SRN_FALL) VCC-SRN falling threshold to turn off ACFET VCC ramps down to SRN –20 60 140 mV V(VCC-SRN VCC-SRN rising threshold to turn on ACFET VCC ramps up above SRN 170 260 360 mV _RISE) ACN to SRN COMPARATOR (ACN_SRN) V(ACN-SRN_FALL) ACN to BAT falling threshold VCC ramps up above SRN ACN ramps down towards SRN 120 200 280 mV V(ACN- SRN _RISE) ACN to BAT rising threshold to turn on BATFET ACN ramps above SRN 220 290 360 mV 8 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 Electrical Characteristics (continued) 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT reg0x37 bit [7] = 0 450 750 1200 mV reg0x37 bit [6] = 1 180 250 340 mV 24 26 28 V HIGH SIDE IFAULT COMPARATOR (IFAULT_HI) V(ACN_PH_RISE) ACN to PH rising threshold LOW SIDE IFAULT COMPARATOR (IFAULT_LOW) V(IFAULT_LO_RISE) PHASE to GND rising threshold INPUT OVERVOLTAGE COMPARATOR (ACOVP) V(ACOV) VCC overvoltage rising threshold VCC ramps up V(ACOV_HYS) VCC overvoltage falling hysteresis VCC ramps down 1 V INPUT OVERCURRENT COMPARATOR (ACOC) V(ACOC) Rising threshold w.r.t. ICRIT input current limit REG0x37[9] = 1 V(ACOC_CLAMP) ACOC threshold V(ACP) – V(ACN) 50 103% 180% 200% 220% 190 mV BAT OVERVOLTAGE COMPARATOR (BAT_OVP) VOVP(RISE) Overvoltage rising threshold as percentage of VBAT(REG) SRN ramps up VOVP(FALL) Overvoltage falling threshold as percentage of VBAT(REG) SRN ramps down IOVP Discharge resistor on SRP 104% 106% 102% VSRN > 6 V 6 VSRN = 4.5 V mA 2.5 CHARGE OVERCURRENT COMPARATOR (CHG_OCP) Cycle-by-cycle overcurrent limit, measured voltage between SRP and SRN VOCP(limit) ChargeCurrent() = 0x0xxxH 54 60 66 mV ChargeCurrent() = 0x1000H – 0x17C0H 80 90 100 mV ChargeCurrent() = 0x1800H – 0x1FC0H 110 120 130 mV 1 5 9 mV CHARGE UNDERCURRENT COMPARATOR (CHG_UCP) Cycle-by-cycle undercurrent falling threshold VUCP(FALL) SRP ramps down towards SRN LIGHT LOAD COMPARATOR (LIGHT_LOAD) VLL(FALL) Light load falling threshold SRP ramps down towards SRN 1.25 mV VLL(RISE_HYST) Light load rising hysteresis SRP ramps above SRN 1.25 mV BATTERY DEPLETION COMPARATOR (BAT_DEPL) Battery depletion falling threshold, as percentage of voltage regulation limit VBAT(DEPL_FALL) VBAT(DEPL_RISE_ HYST) Battery depletion rising hysteresis REG0x3B[15:14] = 00 56% 60% 64% REG0x3B[15:14] = 01 60% 64% 68% REG0x3B[15:14] = 10 64% 68% 72% REG0x3B[15:14] = 11 68% 72% 78% REG0x3B[15:14] = 00 225 305 400 REG0x3B[15:14] = 01 240 325 430 REG0x3B[15:14] = 10 255 345 450 REG0x3B[15:14] = 11 280 370 490 VBAT(DEPL_RDEG) Battery depletion rising deglitch Delay to turn on BATFET and turn off ACFET during LEARN cycle VBAT(DEPL_FDEG) Battery depletion falling deglitch Delay to turn off BATFET and turn on ACFET during LEARN cycle mV 600 ms 10 µs BATTERY LOWV COMPARATOR (BAT_LOWV) VBAT(LV_FALL) Battery LOWV falling threshold SRN ramps down VBAT(LV_RHYST) Battery LOWV rising hysteresis SRN ramps up IBAT(LV_RESET) Battery LOWV charge current limit Measure across SRP and SRN 2.3 2.5 2.8 V 200 mV 5 mV 155 °C 20 °C THERMAL SHUTDOWN COMPARATOR (TSHUT) TSHUT Thermal shutdown rising temperature Temperature ramps up TSHUT(HYS) Thermal shutdown hysteresis, falling Temperature ramps down VILIM(FALL) ILIM as converter enable falling threshold VILIM falling 60 75 90 mV VILIM(RISE) ILIM as converter enable rising threshold VILIM rising 90 105 120 mV ILIM COMPARATOR Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 9 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Electrical Characteristics (continued) 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INDEPENDENT COMPARATOR V(CMPOS) Comparator input offset V(CMPCM) Comparator input common-mode V(CMPREF) Comparator reference voltage (CMPIN falling) REG0x3B[7] = 0 V(CMPRISE) Comparator reference hysteresis REG0x3B[6] = 0 –4 4 0 6.5 V V 2.28 2.3 2.32 REG0x3B[7] = 1 1.18 1.2 1.22 100 mV V mV PWM OSCILLATOR FSW PWM switching frequency REG0x12[9:8] = 00 510 600 690 REG0x12[9:8] = 01 680 800 920 REG0x12[9:8] = 10 850 1000 1150 kHz BATFET GATE DRIVER (BATDRV) IBAT(FET) BATDRV charge pump current limit VBAT(DRV) – VBAT(SRC) = 5 V 40 60 Gate drive voltage on BATFET VBAT(DRV) – VBAT(SRC) when V(SRN) > VBAT(UVLO) 5.5 6.1 6.8 V 5 6.2 7.4 kΩ RBAT(DRV_OFF) BATDRV turn-off resistance RBAT(DRV_LOAD) Minimum Load between gate and source µA 500 kΩ ACFET GATE DRIVER (ACDRV) I(ACFET) ACDRV charge pump current limit V(ACDRV) – V(CMSRC) = 5 V 40 60 Gate drive voltage on ACFET V(ACDRV) – V(CMSRC) when VVCC > V(UVLO) 5.5 6.1 6.8 V 5 6.2 7.4 kΩ R(ACDRV_OFF) ACDRV turn-off resistance R(ACDRV_LOAD) Minimum load between gate and source µA 500 kΩ PWM HIGH SIDE DRIVER (HIDRV) RDS(HI_ON) High-side driver (HSD) turn-on resistance V(BTST) – V(PH) = 5.5 V 6 10 Ω RDS(HI_OFF) High-side driver (HSD) turn-off Resistance V(BTST) – V(PH) = 5.5 V 0.9 1.4 Ω V(BTST_REFRESH) Bootstrap refresh comparator threshold voltage V(BTST) – V(PH) when low side refresh pulse is requested 4.3 4.7 V 3.85 PWM LOW SIDE DRIVER (LODRV) RDS(LO_ON) Low-side driver (LSD) turn-on resistance 7.5 12 Ω RDS(LO_OFF) Low-side driver (LSD) turn-off resistance 0.75 1.25 Ω INTERNAL SOFT START ISTEP Soft start step size 64 mA tSTEP Soft start step time 400 µs PROCHOT V(ICRIT) ICRIT comparator threshold REG0x3C[15:11] = 01001, as percentage of input current limit, InputCurrent() = 0x1000 147% 150% 153% V(INOM) INOM comparator threshold as percentage of input current limit, InputCurrent()=0x0800 107% 110% 112% 163.84 167 IDCHG comparator threshold REG0x3D[15:11] = 10000, as voltage between SRN and SRP 160 V(IDCHG) REG0x3D[15:11] = 00100, as voltage between SRN and SRP 38 40.96 44 5.88 6 6.12 V 0.8 V V(VSYS) VSYS comparator threshold REG0x3C[7:6] = 01 mV LOGIC INPUT (SDA, SCL, BATPRES) VIN(LO) Input low threshold VIN(HI) Input high threshold VIN(LEAK) Input bias current V=7V 2.1 V –1 µA LOGIC OUTPUT OPEN DRAIN (ACOK, SDA, CMPOUT, TB_STAT) VO(LO) Output saturation voltage 5-mA drain current VO(LEAK) Leakage current V=7V –1 500 mV 1 µA 300 mV 1 µA LOGIC OUTPUT OPEN DRAIN (PROCHOT) VO(LEAK_PROCHOT) 10 Output saturation voltage 17-mA drain current Leakage current V = 5.5 V Submit Documentation Feedback –1 Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 6.6 Timing Requirements 4.5 V ≤ VVCC ≤ 24 V, –40°C ≤ TJ ≤ 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted) PARAMETER MIN TYP MAX UNIT VVCC > VVCC_UVLO, ACDET ramps up, 1st time or REG0x12[12] = 0 100 150 200 ms VVCC > VVCC_UVLO, ACDET ramps up, Not 1st time or REG0x12[12] = 1 0.9 1.3 1.7 s 3 µs 15 ms 1 µs ACOK COMPARATOR tACOK_RISE_DEG tACOK_FALL_DEG ACOK rising deglitch to turn on ACFET; VACDET > 2.4V [GBD] ACOK falling deglitch to turn off ACFET [GBD] VVCC > VVCC_UVLO, ACDET ramps down INPUT OVERCURRENT COMPARATOR (ACOC) tACOC_DEG Deglitch time to latch off ACFET 9 12 SMBus TIMING CHARACTERISTICS tR SCLK/SDATA rise time tF SCLK/SDATA fall time tW(H) SCLK pulse width high tW(L) SCLK pulse width low 4.7 µs tSU(STA) Setup time for start condition 4.7 µs tH(STA) Start condition hold time after which first clock pulse is generated 4 µs tSU(DAT) Data setup time 250 ns tH(DAT) Data hold time 300 ns tSU(STOP) Setup time for stop condition 4 µs t(BUF) Bus free time between start and stop condition 4.7 FS(CL) Clock frequency 10 100 kHz 35 ms 4 300 ns 50 µs µs HOST COMMUNICATION FAILURE ttimeout SMBus bus release timeout (1) 25 tBOOT Deglitch for watchdog reset signal 10 tWDI Watchdog timeout period, REG0x12 [14:13] = 01 (2) tWDI Watchdog timeout period, REG0x12 [14:13] = 10 (2) tWDI Watchdog timeout period, REG0x12 [14:13] = 11 (2) (default) 4 ms 5 6 70 88 105 140 175 210 s PWM DRIVER TIMING tDEADTIME_RISE Driver dead time from low side to high side 20 ns tDEADTIME_FALL Driver dead time from high side to low side 20 ns (1) (2) Devices participating in a transfer timeout when any clock low exceeds the 25-ms minimum timeout period. Devices that have detected a timeout condition must reset the communication no later than the 35-ms maximum timeout period. Both a master and a slave must adhere to the maximum value specified because it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms). User can adjust threshold through SMBus ChargeOption() REG0x12. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 11 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Figure 1. SMBus Communication Timing Waveforms 12 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 6.7 Typical Characteristics 100% 100% VBAT = 14.8 V VBAT = 11.1 V VBAT = 7.4 V 98% 98% 96% Efficiency 96% Efficiency VBAT = 3.7 V VBAT = 7.4 V 94% 94% 92% 92% 90% 90% 88% 88% 0 1 2 3 4 5 Charge Current (A) 6 7 0 8 1 2 D001 VIN = 20 V 3 4 5 Charge Current (A) 6 7 8 D002 VIN = 12 V Figure 2. Efficiency During Charging Figure 3. Efficiency During Charging 100% 100% VBAT = 3.7 V 95% 98% 90% Efficiency Efficiency 96% 94% 92% 85% 80% 75% 70% 90% VBAT = 3.7 V VBAT = 7.4 V VBAT = 11.1 V VBAT = 14.8 V 65% 88% 60% 0 1 2 3 4 5 Charge Current (A) 6 7 VIN = 5 V Figure 4. Efficiency During Charging Copyright © 2015–2017, Texas Instruments Incorporated 8 0 2 D003 4 6 Discharge Current (A) 8 10 D004 VIN = 20 V Figure 5. Efficiency During Boost Submit Documentation Feedback 13 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7 Detailed Description 7.1 Overview The bq24780S is a 1-4 cell battery charge controller with power selection for space-constrained, multi-chemistry portable applications such as notebook and detachable ultrabook. It supports wide input range of input sources from 4.5 V to 24 V, and 1-4 cell battery for a versatile solution. The bq24780S supports automatic system power source selection with separate drivers for n-channel MOSFETS on the adapter side and battery side. The bq24780S features Dynamic Power Management (DPM) to limit the input power and avoid AC adapter overloading. During battery charging, as the system power increases, the charging current will reduce to maintain total input current below adapter rating. If system power demand is temporarily exceeds adapter rating, the bq24780S supports hybrid power boost mode (previously called "turbo boost mode") to allow battery discharge energy to supplement system power. For details of hybrid power boost mode, refer to Device Functional Modes section. The bq24780S closely monitors system power (PMON), input current (IADP) and battery discharge current (IDCHG) with highly accurate current sense amplifiers. If current is too high, adapter or battery is removed, a PROCHOT signal is asserted to CPU so that the CPU optimizes its performance to the power available to the system. The SMBus controls input current, charge current and charge voltage registers with high resolution, high accuracy regulation limits. It also sets the PROCHOT timing and threshold profile to meet system requirements. 14 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.2 Functional Block Diagram 3.2V UVLO* VCC ACDRV CHARGE PUMP ACDRV ACDRV_CMSRC 28 CMSRC+5.9V EN_REGN ACGOOD ACDET 4 ACDRV 3 CMSRC 18 BATDRV 17 BATSRC 25 BTST 26 HIDRV 27 PHASE 24 REGN 23 LODRV 22 GND 15 BATPRES 10 PROCHOT 16 TB_STAT 6 0.6V ACOK_DRV WAKEUP* ACN SELECTOR LOGIC BATDRV CHARGE PUMP SRN+200mV ACOC ACOVP 26V EN_LEARN ACGOOD FET_LATCHOFF_EN VCC_SRN 2.4V ACOK bq24780S 5 ACOK_DRV *Threshold is adjustable by registers 150ms/1.3sec Rising Deglitch** VREF_IAC ACP 2 ACN 1 IADP 7 IDCHG 8 WD_TIMEOUT FBO 20X** WATCHDOG TIMER 175s** EN_CHRG EN_DPM 1X TYPE III COMPENSATION CHARGE_INHIBIT 16X/5 EAI DAC_VALID EAO EN_LEARN PWM 5X 200mV VREF_IDCHG SRP RAMP Frequency** 20 EN_BOOST Tj 16X SRN 19 BATOVP TSHUT 155C VREF_ICHG 6mA EN_CHRG SRP-SRN CHG_OCP ILIM 120mV ILIM 21 5mV EN_REGN CHG_UCP SRP-SRN VREF_VREG WAKEUP 10uA 1.25mV LIGHT_LOAD PWM DRIVER LOGIC SRP-SRN ACP_ACN VCC PMON 9 REGN LDO ACOC (ACP-ACN) BAT 2x ICRIT* (SRN-SRP) 4.3V REFRESH DAC_VALID CHARGE_INHIBIT EN_LEARN SDA 12 SMBUS Interface SCL 11 SRN BATOVP 104%VREF_VREG VREF_IAC VREF_IDCHG IADPT IDCHG VREF_VREG VREF_ICHG ChargeOption() ChargeCurrent() ChargeVoltage() InputCurrent() DischargeCurrent() ManufactureID() DeviceID() BTST_PH VSYS 2.5V PROC HOT detect BATLOWV SRN VCC VCC_SRN EN_BOOST EN_DPM SRN+275mV IREF_CMP** ACP-ACN FAST_DPM 107%xVREF_IAC FET_LATCHOFF_EN EN_SHIP ILIM CHG/ DCHG_EN 13 CMPIN 14 CMPOUT 120mV Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 15 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7.3 Feature Description 7.3.1 Device Power Up The bq24780S gets power from adapter or battery. After VCC is above its UVLO threshold, the device wakes up and starts communication. 7.3.1.1 Battery Only When VCC voltage is above UVLO, bq24780S powers up to turn on BATFET and starts SMBus communication. By default, bq24780S stays in low power mode (REG0x12[15] = 1) with lowest quiescent current. When REG0x12[15] is set to 0, the device enters performance mode. User can enable IDCHG buffer, PMON, PROCHOT or comparator through SMBus. REGN LDO is enabled (except for IDCHG buffer) for accurate reference. 7.3.1.2 Adapter Detect and ACOK Output An external resistor divider attenuates the adapter voltage before it goes to ACDET. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage, but lower than the maximum allowed adapter voltage. When ACDET is above 0.6V, all bias circuits are enabled. The open drain ACOK output can be pulled to external rail under the following conditions: • VVCC_UVLOZ < VVCC < ACOVP • VACDET > 2.4 V • VVCC – VSRN > VVCC_SRN_FALL + VVCC_SRN_HYST The REG0x37[11] tracks the status of ACOK pin. ACOK deglitch time is 150ms at the first time adapter plug-in, and 1.3 sec at the following plug-ins after VCC or SRN is above its UVLOZ. 7.3.1.2.1 Adapter Overvoltage (ACOVP) When the VCC pin voltage is higher than 26 V, it is considered adapter over voltage. ACOK is pulled low, and charge is disabled. ACFET/RBFET are turned off to disconnect the high voltage adapter to system during ACOVP. BATFET is turned on if turn-on conditions are valid. When VCC voltage falls below 24 V, it is considered as adapter voltage returns back to normal voltage. ACOK is pulled high by an external pullup resistor. BATFET is turned off and ACFET and RBFET is turned on to power the system from the adapter. 7.3.2 System Power Selection The bq24780S device automatically switches adapter or battery power to system. An automatic break-beforemake logic prevents shoot-through currents when the selectors switch. The ACDRV drives a pair of common-source (CMSRC) N-channel power MOSFETs (ACFET and RBFET) between adapter and ACP. The ACFET separates adapter from system and battery, and provides a limited di/dt when plugging in adapter by controlling the ACFET turn-on time. Meanwhile, it protects the adapter when the system or battery is shorted. The RBFET provides negative input voltage protection and battery discharge protection when adapter is shorted to ground, and minimizes system power dissipation with its low RDS(on) compared to a Schottky diode. When the adapter is not present, ACDRV is pulled to CMSRC to keep ACFET and RBFET off, disconnecting the adapter from the system. BATDRV stays at VBATSRC + 6 V to connect battery to system if all of the following conditions are valid: • VCC > VUVLO • VACN < VSRN + 200 mV • ACFET/RBFET off After the adapter plugs in, the system power source switches from battery to adapter if all of the following conditions are valid: • ACOK high • Not in LEARN mode • In LEARN mode and VSRN < battery depletion threshold 16 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 Feature Description (continued) The gate drive voltage on ACFET and RBFET is VCMSRC + 6 V. If the ACFET/RBFET have been turned on for 20 ms, and the voltage across gate and source is still less than 5.7 V, ACFET and RBFET are turned off. After 1.3s delay, it resumes turning on ACFET and RBFET. If such a failure is detected seven times within 90 seconds, ACFET/RBFET are latched off and an adapter removal and system shut down is required to force ACDET < 0.6 V to reset the IC. After IC reset from latch off, ACFET/RBFET can be turned on again. After 90 seconds, the failure counter is reset to zero to prevent latch off. To turn off ACFET/RBFET, one of the following conditions must be valid: • In LEARN mode and VSRN is above battery depletion threshold; • ACOK low To limit the adapter inrush current during ACFET turn-on, the Cgs and Cgd external capacitor of ACFET must be carefully selected following the guidelines below: • Minimize total capacitance on system • Cgs should be 40× or higher than Cgd to avoid ACFET false turn on during adapter hot plug-in • Fully turn on ACFET within 20 ms, otherwise, charger IC will consider turn-on failure • Check with MOSFET vendor on peak current rating • Place 4-kΩ resistor in series with ACDRV, CMSRC, and BATDRV pin to limit inrush current. 7.3.3 Enable and Disable Charging In charge mode, the following conditions have to be valid to start charge: • Charge is enabled through SMBus (REG0x12[0], default is 0, charge enabled) • ILIM pin voltage is higher than 120 mV • All ChargeCurrent(), ChargeVoltage() and InputCurrent() registers have valid value programmed • ACOK is valid (see Device Power Up for details) • ACFET and RBFET turn on and gate voltage is high enough (see System Power Selection for details) • VSRN does not exceed BATOVP threshold • IC temperature does not exceed TSHUT threshold • Not in ACOC condition (see Device Protections Features for details) One of the following conditions stops on-going charging: • Charge is inhibited through SMBus(REG0x12[0]=1) • ILIM pin voltage is lower than 60 mV • One of three registers is set to 0 or out of range • ACOK is pulled low (see Device Power Up for details) • ACFET turns off • VSRN exceeds BATOVP threshold • TSHUT IC temperature threshold is reached • ACOC is detected (see Device Protections Features for details) • Short circuit is detected (see Inductor Short, MOSFET Short Protection for details) • Watchdog timer expires if watchdog timer is enabled (see Charger Timeout for details) 7.3.3.1 Automatic Internal Soft-Start Charger Current Every time the charge is enabled, the charger automatically applies soft-start on charge current to avoid any overshoot or stress on the output capacitors or the power converter. The charge current starts at 128 mA, and the step size is 64 mA in CCM mode for a 10 mΩ current sensing resistor. Each step lasts around 400 μs in CCM mode, till it reaches the programmed charge current limit. No external components are needed for this function. During DCM mode, the soft start up current step size is larger and each step lasts for longer time period due to the intrinsic slow response of DCM mode. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 17 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Feature Description (continued) 7.3.4 Current and Power Monitor 7.3.4.1 High Accuracy Current Sense Amplifier (IADP and IDCHG) As an industry standard, a high-accuracy current sense amplifier (CSA) is used to monitor the input current (IADP) and the discharge current (IDCHG). IADP voltage is 20X or 40X the differential voltage across ACP and ACN. IDCHG voltage is 8X or 16X the differential voltage across SRN and SRP. After VCC is above UVLO and ACDET is above 0.6 V, IADP output becomes valid. . A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The CSA output voltage is clamped at 3.3 V. To lower the voltage on current monitoring, a resistor divider from CSA output to GND can be used and accuracy over temperature can still be achieved 7.3.4.2 High Accuracy Power Sense Amplifier (PMON) The bq24780S device monitors total available power from adapter and battery together. The ratio of PMON voltage and total power KPMON can be programmed in REG0x3B[9] with default 1 µA/W. The bq24780S device allows input sense resistor 2x or 1/2x of charge sense resistor by setting REG0x3B[13:12] to 1. IPMON = KPMON (VIN x IIN - VBAT x IBAT) (IBAT > 0 during charge; IBAT < 0 during discharge) (1) A resistor is connected on the PMON pin to converter output current to output voltage. A maximum 100-pF capacitor is recommended to connect on the output for decoupling high-frequency noise. An additional RC filter is optional, if additional filtering is desired. Note that adding filtering also adds additional response delay. The PMON output voltage is clamped to 3.3 V. 7.3.5 Processor Hot Indication for CPU Throttling When CPU is running turbo mode, the peak power may exceed total available power from adapter and battery. The adapter current and battery discharge overshoot, or system voltage drop indicates the system power may be too high. When the adapter or battery is removed, the remaining power source may not support the peak power in turbo mode. The processor hot function in bq24780S monitors these events, and PROCHOT pulse is asserted. The PROCHOT triggering events include: • ICRIT: adapter peak current • INOM: adapter average current (110% of input current limit) • IDCHG: battery discharge current • VSYS: system voltage on SRN for 2s - 4s battery • ACOK: upon adapter removal (ACOK pin HIGH to LOW) • BATPRES: upon battery removal (BATPRES pin LOW to HIGH) • CMPOUT: Independent comparator output (CMPOUT pin HIGH to LOW) The threshold of ICRIT, IDCHG or VSYS, and the deglitch time of ICRIT, INOM, IDCHG or CMPOUT are programmable through SMBus. Each triggering event can be individually enabled in REG0x3D[6:0]. 18 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 Feature Description (continued) ICRIT IADP Adjustable Deglitch 1.05 V INOM IDCHG 50W PROCHOT Ref_DCHG 10-ms Debounce Ref VSRP ≥10 ms 20-ms Deglitch ACOK BATPRES (One shot on rising edge) < 0.3 V CMPOUT (One shot on falling edge) Figure 6. PROCHOT Profile When any event in PROCHOT profile is triggered, PROCHOT is asserted low for minimum 10 ms (default REG0x3C[4:3]=10). At the end of the 10 ms, if the PROCHOT event is still active, the pulse gets extended. During one cycle of PROCHOT, all the triggering events are saved in status register REG0x3A[6:0] for easy test debug and system optimization. 7.3.6 Converter Operation The synchronous buck PWM converter uses a fixed frequency voltage control scheme and internal type III compensation network. The LC output filter gives a characteristic resonant frequency: 1 fo 2S LoCo (2) The resonant frequency, fo, is used to determine the compensation to ensure there is sufficient phase margin for the target bandwidth. The LC output filter should be selected to give a resonant frequency of 10- to 20-kHz nominal for the best performance. Suggested component value for a charge current of 800-kHz default switching frequency is shown in Table 1: Table 1. Suggest Component Value for Charge Current of 800-kHz Default Switching Frequency CHARGE CURRENT 2A 3A 4A 6A 8A Output Inductor Lo (µH) 6.8 or 8.2 5.6 or 6.8 3.3 or 4.7 3.3 2.2 Output Capacitor Co (µF) 20 20 20 30 40 Sense Resistor (mΩ) 10 10 10 10 10 Ceramic capacitors show a DC-bias effect. This effect reduces the effective capacitance when a DC-bias voltage is applied across a ceramic capacitor, as on the output capacitor of a charger. The effect may lead to a significant capacitance drop, especially for high output voltages and small capacitor packages. See the manufacturer's data sheet about the performance with a DC bias voltage applied. It may be necessary to choose a higher voltage rating or nominal capacitance value to get the required value at the operating point. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 19 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7.3.6.1 Continuous Conduction Mode (CCM) With sufficient charge current, the inductor current does not cross 0, which is defined as CCM. The controller starts a new cycle with ramp coming up from 200 mV. As long as EAO voltage is above the ramp voltage, the high-side MOSFET (HSFET) stays on. When the ramp voltage exceeds EAO voltage, HSFET turns off and lowside MOSFET (LSFET) turns on. At the end of the cycle, ramp gets reset and LSFET turns off, ready for the next cycle. There is always break-before-make logic during transition to prevent cross-conduction and shoot-through. During the dead time when both MOSFETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. During CCM, the inductor current always flows and creates a fixed two-pole system. Having the LSFET turn-on keeps the power dissipation low and allows safe charging at high currents. 7.3.6.2 Discontinuous Conduction Mode (DCM) During the HSFET off time when LSFET is on, the inductor current decreases. If the current goes to 0, the converter enters DCM. Every cycle, when the voltage across SRP and SRN falls below 5 mV (0.5 A on 10 mΩ), the undercurrent-protection comparator (UCP) turns off LSFET to avoid negative inductor current, which may boost the system through the body diode of HSFET. During DCM the loop response automatically changes. It changes to a single-pole system and the pole is proportional to the load current. 7.3.6.3 Non-Sync Mode and Light Load Comparator As the charge current is below 125 mA (on 10-mΩ sense resistor), the light load comparator keeps LSFET off. The converter enters non-sync mode. With LSFET, body diode blocks negative current in the inductor so that no current flows back to the input. As charge current rises above 250 mA, LSFET turns on again. 7.3.6.4 EMI Switching Frequency Adjust The charger switching frequency can be adjusted 600 kHz or 1 MHz to solve EMI issues through SMBus command REG0x12[9:8]. 7.3.7 Battery LEARN Cycle A battery LEARN cycle can be activated through the REG0x12[5]. When LEARN is enabled, the system receives power from the battery instead of the adapter turning off ACFET/RBFET and turning on BATFET. The LEARN function allows the battery to discharge in order to calibrate the battery gas gauge over a complete discharge and charge cycle. The controller automatically exits the LEARN cycle when the battery voltage is below the battery depletion threshold. The system switches back to adapter input by turning off BATFET and turning on ACFET/RBFET. After the LEARN cycle, REG0x12[5] is automatically reset to 0. When the battery is removed during LEARN mode, BATPRES rises from low to high and the device exits LEARN mode. ACFET/RBFET quickly turns on in 100µs to prevent the system from crashing. The turn-on triggered by BATPRES is faster than that triggered by battery depletion comparator. 7.3.8 Charger Timeout The bq24780S device includes a watchdog timer to terminate charging or hybrid power boost mode if the charger does not receive a write ChargeVoltage() or write ChargeCurrent() command within 175 s (adjustable through 0x12[14:13] command). If a watchdog timeout occurs, all register values keep unchanged, but converter is suspended. A write to ChargeVoltage(), or ChargeCurrent(), or change REG0x12[14:13] resets watchdog timer and resumes converter for charging or hybrid power boost mode. The watchdog timer can be disabled, or set to 5, 88, or 175 s through SMBus command REG0x12[14:13]). 20 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.3.9 Device Protections Features 7.3.9.1 Input Overcurrent Protection (ACOC) The bq24780S device cannot maintain the input current level if the charge current has been already reduced to 0. When the input current exceeds 1.25x or 2x of ICRIT set point (with 12-ms blank-out time), ACFET/RBFET is latches off and an adapter removal is required to force ACDET < 0.6 V to reset IC. After IC reset from latch off, ACFET/RBFET can be turned on again. The ACOC function threshold can be set to 1.25x or 2x of ICRIT (REG37[9]) current or disabled through SMBus command (REG0x37[10]). 7.3.9.2 Charge Overcurrent Protection (CHGOCP) The bq24780S device has cycle-by-cycle peak overcurrent protection. It monitors the voltage across SRP and SRN, and prevents the current from exceeding the threshold based on the charge current set point. The highside gate drive turns off for the rest of the cycle when over current is detected, and resumes when the next cycle starts. The charge OCP threshold is automatically set to 6, 9, and 12 A on a 10-mΩ current sensing resistor based on charge current register value. This prevents the threshold from being too high, which is not safe, or too low, which can be triggered in typical operation. Select proper inductance to prevent OCP triggering in typical operation due to high inductor current ripple. 7.3.9.3 Battery Overvoltage Protection (BATOVP) The bq24780S device does not allow the high-side and low-side MOSFET to turn-on when the battery voltage at SRN exceeds 104% of the regulation voltage set point. If BATOVP lasts over 30 ms, charger is completely disabled. This allows a quick response to an overvoltage condition – such as when the load is removed or the battery is disconnected. A 6-mA current sink from SRP to GND is only on during BATOVP and allows discharging the stored output inductor energy that is transferred to the output capacitors. 7.3.9.4 Battery Short When battery voltage on SRN falls below 2.5 V, the converter resets for 1 ms and resumes charge if all the enable conditions in the Enable and Disable Charging section are satisfied. This prevents overshoot current in the inductor, which can saturate the inductor and may damage the MOSFET. The charge current is limited to 0.5 A on 10-mΩ current sensing resistor when BATLOWV condition persists and LSFET keeps off. The LSFET turns on only for a refreshing pulse to charge BTST capacitor. 7.3.9.5 Thermal Shutdown Protection (TSHUT) The WQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off for self-protection whenever the junction temperature exceeds the 155°C. The charger stays off until the junction temperature falls below 135°C. During thermal shutdown, the REGN LDO current limit is reduced to 14 mA. Once the temperature falls below 135°C, charge can be resumed with soft start. 7.3.9.6 Inductor Short, MOSFET Short Protection The bq24780S device has a unique short circuit protection feature. Its cycle-by-cycle current monitoring feature is achieved through monitoring the voltage drop across RDS(on) of the MOSFETs after a certain amount of blanking time. In case of a MOSFET short or inductor short circuit, the overcurrent condition is sensed by two comparators and two counters are triggered. After seven short circuit events, the charger is latched off and ACFET and RBFET are turned off to disconnect the adapter from the system. BATFET is turned on to connect the battery pack to the system. To reset the charger from latch-off status, the IC VCC pin must be pulled below UVLO or the ACDET pin must be pulled below 0.6 V. This can be achieved by removing the adapter and shutting down the operation system. The low-side MOSFET Vds monitor circuit is enabled by REG0x37[7], and the threshold is 750 mV. The high-side MOSFET Vds monitor circuit is enabled by REG0x37[6], and the threshold is 250 mV. During boost function, the low-side MOSFET short circuit protection threshold is used for cycle-by-cycle current limiting, charger does not latch up. Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 21 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com Due to the amount of blanking time to prevent noise when MOSFET just turns on, the cycle-by-cycle charge overcurrent protection may detect high current and turn off MOSFET first before the short circuit protection circuit can detect short condition because the blanking time has not finished. In such a case, the charger may not be able to detect a short circuit and the counter may not be able to count to seven then latch off. Instead the charger may continuously keep switching with very narrow duty cycle to limit the cycle-by-cycle current peak value. However, the charger should still be safe and does not cause failure because the duty cycle is limited to a very short time and the MOSFET should still be inside the safety operation area. During a soft start period, it may take a long time instead of just seven switching cycles to detect short circuit based on the same blanking time reason. 7.4 Device Functional Modes 7.4.1 Battery Charging The bq24780S charges 1-4 cell battery in constant current (CC), and constant voltage (CV) mode. The host programs battery voltage in REG0x15(). According to battery voltage, the host programs appropriate charge current in REG0x14(). When battery is full or battery is not in good condition to charge, host terminates charge by setting REG0x12[0] to 1, or setting either ChargeVoltage() or ChargeCurrent() to zero. See the Feature Description section for details on charge enable conditions and register programming. 7.4.2 Hybrid Power Boost Mode The bq24780S device supports the hybrid power boost mode by allowing battery discharge energy to system when system power demand is temporarily higher than adapter maximum power level so the adapter does not crash. After device powers up, the REG0x37[2] is 0 to disable hybrid power boost mode. To enable hybrid power boost mode, host writes 1 to REG0x37[2]. The TB_STAT pin and REG0x37[1] indicate if the device is in hybrid power boost mode. To support hybrid power boost mode, input current must be set higher than 1536 mA for 10 mΩ input current sensing resistor. When input current is higher than 107% of input current limit in REG0x3F(), charger IC allows battery discharge and charger converter changes from buck converter to boost converter. During hybrid power boost mode the adapter current is regulated at input current limit level so that adapter will not crash. The battery discharge current depends on system current requirement and adapter current limit. The watchdog timer can be enabled to prevent converter running at hybrid power boost mode for too long. 7.4.2.1 Battery Discharge Current Regulation in Hybrid Power Boost Mode To keep the discharge current below battery OCP rating during boost mode, the bq24780S device supports discharge current regulation. After device powers up, the REG0x37[15] is 0 to disable discharge current regulation. To enable discharge current regulation, host writes 1 to REG0x37[15]. Once the battery discharge current is limited, the input current goes up to meet the system current requirement. The user can assert PROCHOT to detect input current increase (ICRIT or INOM), and request CPU throttling to lower the system power. 22 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.5 Programming 7.5.1 SMBus Interface The bq24780S device operates as a slave, receiving control inputs from the embedded controller host through the SMBus interface. The bq24780S device uses a simplified subset of the commands documented in System Management Bus Specification V1.1, which can be downloaded from www.smbus.org. The bq24780S device uses the SMBus read-word and write-word protocols (shown in Table 2 and Table 3) to communicate with the smart battery. The bq24780S device performs only as a SMBus slave device with address 0b00010010 (0x12H) and does not initiate communication on the bus. In addition, the device has two identification registers, a 16-bit device ID register (0xFFH) and a 16-bit manufacturer ID register (0xFEH). SMBus communication starts when VCC is above UVLO. The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications. Communication starts when the master signals a start condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a stop condition, which is a low-tohigh transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 7 and Figure 8 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and data bytes are transmitted between the start and stop conditions. The SDA state changes only while SCL is low, except for the start and stop conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24780S device because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle. The bq24780S supports the charger commands listed in Table 2. 7.5.1.1 SMBus Write-Word and Read-Word Protocols Table 2. Write-Word Format S (1) (2) (1) (2) (3) (4) (5) (6) SLAVE ADDRESS (1) (1) (3) W ACK COMMAND BYTE (1) ACK 7 bits 1b MSB LSB 0 1b 8 bits 0 MSB LSB (4) (5) LOW DATA BYTE (1) ACK 1b 8 bits 0 MSB LSB (4) (5) HIGH DATA BYTE (1) ACK 1b 8 bits 1b 0 MSB LSB 0 (4) (5) P (4) (5) (1) (6) Master to slave S = Start condition or repeated start condition W = Write bit (logic-low) Slave to master (shaded gray) ACK = Acknowledge (logic-low) P = Stop condition Table 3. Read-Word Format S (1) (2) (1) (2) (3) (4) (5) (6) (7) (8) W ACK COMMAND ACK S (1) SLAVE R (1) ACK LOW DATA ACK (4) (5) (4) (5) (2) (1) (5) BYTE (1) ADDRESS (1) (6) (4) (5) BYTE (4) SLAVE ADDRESS (1) (1) (3) 7 bits 1b 1b 8 bits 1b 7 bits 1b 1b 8 bits MSB LSB 0 0 MSB LSB 0 MSB LSB 1 0 MSB LSB HIGH DATA BYTE (4) NACK 1b 8 bits 1b 0 MSB LSB 1 (1) (7) P (1) (8) Master to slave S = Start condition or repeated start condition W = Write bit (logic-low) Slave to master (shaded gray) ACK = Acknowledge (logic-low) R = Read bit (logic-high) NACK = Not acknowledge (logic-high) P = Stop condition Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 23 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7.5.1.2 Timing Diagrams A B C D E F G H I J K L M tLOW tHIGH SMBCLK SMBDATA tSU:DAT tHD:DAT tSU:STA tHD:STA tHD:DAT tSU:STO tBUF A = Start condition H = LSB of data clocked into slave B = MSB of address clocked into slave I = Slave pulls SMBDATA line low C = LSB of address clocked into slave J = Acknowledge clocked into master D = R/W bit clocked into slave K = Acknowledge clock pulse E = Slave pulls SMBDATA line low L = Stop condition, data executed by slave F = ACKNOWLEDGE bit clocked into master M = New start condition G = MSB of data clocked into slave Figure 7. SMBus Write Timing A B C D E F G H I J K tLOW tHIGH SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT A = START CONDITION tHD:DAT tSU:DAT E = SLAVE PULLS SMBDATA LINE LOW tSU:STO tBUF I = ACKNOWLEDGE CLOCK PULSE A = Start condition G = MSB of data clocked into master B = MSB of address clocked into slave H = LSB of data clocked into master C = LSB of address clocked into slave I = Acknowledge clock pulse D = R/W bit clocked into slave J = Stop condition E = Slave pulls SMBDATA line low K = New start condition F = ACKNOWLEDGE bit clocked into master Figure 8. SMBus Read Timing 24 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.6 Register Maps 7.6.1 Battery-Charger Commands The bq24780S supports thirteen battery-charger commands that use either Write-Word or Read-Word protocols, as summarized in Table 4. ManufacturerID() and DeviceID() can be used to identify the bq24780S. The ManufacturerID() command always returns 0x0040H and the DeviceID() command always returns 0x0030H. Table 4. Battery Charger Command Summary REGISTER ADDRESS REGISTER NAME READ OR WRITE 0x12H ChargeOption0() Table 5 Read or Write Charge Options Control 0 DESCRIPTION 0xE108H 0x3BH ChargeOption1() Table 6 Read or Write Charge Options Control 1 0xC210H 0x38H ChargeOption2()Table 7 Read or Write Charge Options Control 2 0x0384H 0x37H ChargeOption3()Table 8 Read or Write Charge Options Control 3 0x1A40H 0x3CH ProchotOption0()Table 9 Read or Write PROCHOT Options Control 0 0x4A54H 0x3DH ProchotOption1() Table 10 Read or Write PROCHOT Options Control 1 0x8120H 0x3AH ProchotStatus() Table 11 Read Only PROCHOT status 0x0000H 0x14H ChargeCurrent() Table 12 Read or Write 7-bit Charge Current Setting 0x0000H 0x15H ChargeVoltage() Table 13 Read or Write 11-bit Charge Voltage Setting 0x39H DischargeCurrent() Table 15 Read or Write 6-bit Discharge Current Setting 0x1800H, or 6144mA 6-bit Input Current Setting 0x1000H, or 4096mA 0x3FH InputCurrent() Table 14 Read or Write 0xFEH ManufacturerID() Read Only Manufacturer ID 0xFFH DeviceID() Read Only Device ID Copyright © 2015–2017, Texas Instruments Incorporated POR STATE 0x0000H 0x0040H 0x30H Submit Documentation Feedback 25 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7.6.2 Setting Charger Options 7.6.2.1 ChargeOption0 Register Figure 9. ChargeOption0 Register (0x12H) 15 Low Power Mode Enable R/W 14 13 WATCHDOG Timer Adjust 12 11 Reserved R/W 7 6 10 9 8 Switching Frequency R Reserved 5 LEARN Mode Enable R R/W 4 IADP Amplifier Gain for Primary Input R/W R/W 3 IDCHG Amplifier Ratio 2 R/W Reserved 1 0 Charge Inhibit R R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 5. ChargeOption0 Register (0x12H) BIT BIT NAME [15] Low Power Mode Enable (EN_LWPWR) [14:13] WATCHDOG Timer Adjust (WDTMR_ADJ) [12:10] Reserved [9:8] Switching Frequency (PWM_FREQ) [7:6] Reserved [5] LEARN Mode Enable (EN_LEARN) [4] IADP Amplifier Gain for Primary Input (IADP_GAIN) [3] IDCHG Amplifier Gain (IDCHG_GAIN) [2:1] Reserved [0] Charge Inhibit (CHRG_INHIBIT) 26 Submit Documentation Feedback DESCRIPTION 0: IC in performance mode with battery only. The PROCHOT, current/power monitor buffer and independent comparator follow register setting. 1: IC in low power mode with battery only. IC is in the lowest quiescent current when this bit is enabled. PROCHOT, discharge current monitor buffer, power monitor buffer and independent comparator are disabled (default at POR) Set maximum delay between consecutive SMBus write charge voltage or charge current command. If IC does not receive write on REG0x14() or REG0x15() within the watchdog time period, the charger converter stops to disable charge and boost mode operation. After expiration, the timer will resume upon the write of REG0x14() or REG0x15(). The charge or boost operation will resume if all the other conditions are valid. 00: Disable watchdog timer 01: Enabled, 5 sec 10: Enabled, 88 sec 11: Enable watchdog timer (175 s) (default at POR) 0 - Reserved Converter switching frequency. 00: 600 kHz 01: 800 kHz (default at POR) 10: 1 MHz 11: Reserved 0 - Reserved Battery LEARN mode enable. In LEARN mode, ACFET and RBFET turns off and BATFET turns on. When /BATPRES is HIGH, IC exits LEARN mode and this bit is set back to 0. When the battery is depleted, the charger cannot enable LEARN mode 0: Disable LEARN mode (default at POR) 1: Enable LEARN mode Ratio of IADP pin voltage over the voltage across ACP and ACN. 0: 20X (default at POR) 1: 40X Ratio of IDCHG pin voltage over the voltage across SRN and SRP. 0: 8x with discharge current regulation range 0-32A. 0: 8x with discharge current regulation range 0-32A. 1: 16x with discharge current regulation range (default at POR) 0 - Reserved Charge inhibit. When this bit is 0, battery charging is enabled with valid value in REG0x14() and REG0x15() 0: Enable charge (default at POR) 1: Inhibit charge Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.6.3 ChargeOption1 Register Figure 10. ChargeOption1 Register (0x3BH) 15 14 BAT Depletion Comparator Threshold R/W 13 12 Input/Discharge Sense Resistor Ratio R R/W 11 EN_IDCHG 10 EN_PMON 9 PMON Gain 8 Reserved R/W R/W R/W R 7 Independent Comparator Reference 6 Independent Comparator Polarity 5 4 Independent Comparator Deglitch Time 3 Power Path Latchoff Enable 2 Reserved 0 Reserved R/W R/W R/W R/W R 1 Discharge SRN for Shipping Mode_EN R/W R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6. ChargeOption1 Register (0x3BH) BIT [15:14] BIT NAME Battery Depletion Threshold (BAT_DEPL_VTH) DESCRIPTION Battery over-discharge threshold.During LEARN cycle, when battery voltage is below the depletion threshold, the IC exits LEARN mode. During boost mode, when battery voltage is below the depletion threshold, the IC exits boost mode. 00: Falling threshold = 59.19% of voltage regulation limit (~2.486V/cell) 01: Falling threshold = 62.65% of voltage regulation limit (~2.631V/cell) 10: Falling threshold = 66.55% of voltage regulation limit (~2.795V/cell) 11: Falling threshold = 70.97% of voltage regulation limit (2.981V/cell) (default at POR) 0 - Adjust the PMON calculation with different input sense resistor RAC and charge sense resistor RSR. 00: RAC and RSR 1:1 (default at POR) 01: RAC and RSR 2:1 10: RAC and RSR 1:2 11: Reserved [13:12] (RSNS_RATIO) [11] EN_IDCHG IDCHG pin output enable. 0: Disable IDCHG output to minimize Iq (default at POR) 1: Enable IDCHG output [10] EN_PMON PMON pin output enable. 0: Disable PMON output to minimize Iq (default at POR) 1: Enable PMON output [9] PMON Gain (PMON_RATIO) [8] Reserved [7] Independent Comparator Reference (CMP_REF) [6] Independent Comparator Polarity (CMP_POL) [5:4] Ratio of PMON output current vs total input and battery power with 10 mΩ sense resistor. 0: 0.25 µA/W 1: 1 µA/W (default at POR) With the sense resistor is 20/10 mΩ, or 10/20 mΩ, or 20/20mΩ (RAC and RSR) 0: 0.5 µA/W 1: 2 µA/W (default at POR) 0 - Reserved Independent comparator internal reference. 0: 2.3 V (default at POR) 1: 1.2 V Independent comparator output polarity 0: When CMPIN is above internal threshold, CMPOUT is LOW (default at POR) 1: When CMPIN is above internal threshold, CMPOUT is HIGH Independent comparator deglitch time, applied on the edge where CMPOUT goes LOW. No deglitch time is applied on the rising edge of CMPOUT. Independent Comparator Deglitch 00: Independent comparator is disabled Time (CMP_DEG) 01: Independent comparator is enabled with output deglitch time 1 µs (default at POR) 10: Independent comparator is enabled with output deglitch time 2 ms 11: Independent comparator is enabled with output deglitch time 5 sec [3] Power Path Latch-off Enable (EN_FET_LATCHOFF ) [2] Reserved [1] Discharge SRN for Shipping Mode (EN_SHIP_DCHG) [0] Reserved When independent comparator is triggered, both ACFET/RBFET turn off. The latch off is cleared by either POR or write this bit to zero. 0: When independent comparator is triggered, no power path latch off (default at POR) 1: When independent comparator is triggered, power path latches off. 0 - Reserved Discharge SRN pin for 140 ms with minimum 5-mA current. When 140 ms is over, this bit is reset to 0. 0 : Disable discharge mode (default at POR) 1: Enable discharge mode 0 - Reserved Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 27 bq24780S SLUSC27C – APRIL 2015 – REVISED MARCH 2017 www.ti.com 7.6.4 ChargeOption2 Register Figure 11. ChargeOption2 Register (0x38H) 15 14 7 Independent External Current Limit Enable R/W 6 13 12 Reserved R 11 4 3 5 10 9 8 Reserved R Reserved 2 Reserved R R 1 0 Reserved R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 7. ChargeOption2 Register (0x38H) BIT BIT NAME [15:10] Reserved 0 – Reserved [9:8] Reserved 1 - Reserved [7] External Current Limit Enable (EN_EXTILIM) [6:3] Reserved 0 - Reserved [2] Reserved 1 - Reserved [1:0] Reserved 0 - Reserved 28 Submit Documentation Feedback DESCRIPTION External ILIM pin enable to set the charge and discharge current. 0: Charge/discharge current limit is set by REG0x14() and 0x39(). 1: Charge/discharge current limit is set by the lower value of ILIM pin and registers. (default at POR) Copyright © 2015–2017, Texas Instruments Incorporated bq24780S www.ti.com SLUSC27C – APRIL 2015 – REVISED MARCH 2017 7.6.5 ChargeOption3 Register Figure 12. ChargeOption3 Register (0x37H) 15 Discharge Current Regulation Enable R/W 14 13 12 ACOK Deglitch Time for Primary Input R/W 7 HSFET VDS Threshold 6 LSFET VDS Threshold 5 Fast DPM Threshold 4 3 Fast DPM Deglitch Time R/W R/W R/W R/W Reserved R 11 Adapter Present Indicator 10 ACOC Enable 9 ACOC Limit 8 Reserved R/W R/W R/W R 2 Hybrid Power Boost Mode Enable R/W 1 Boost Mode Indication 0 Reserved R/W R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8. ChargeOption3 Register (0x37H) BIT BIT NAME [15] Discharge Current Regulation Enable(EN_IDCHG_REG) [14:13] Reserved DESCRIPTION Battery discharge current regulation enable. 0: Disable discharge current regulation (default at POR) 1: Enable discharge current regulation 0 - Reserved Adjust ACOK rising edge deglitch time. After POR, the first time adapter plugs in, deglitch time is always 150 ms regardless of register bit. Starting from the 2nd time adapter plugs in, the deglitch time follows the bit setting. During system over-current, or system short when ACDET is pulled below 2.4 V, 1.3 sec deglitch time keeps ACFET/RBFET turn off long enough before the next turn on. 0: ACOK rising edge deglitch time 150ms 1: ACOK rising edge deglitch time 1.3 sec (default at POR) [12] ACOK Deglitch Time for Primary Input (ACOK_DEG ) [11] Adapter Present Indicator (ACOK_STAT ) [10] ACOC Enable (EN_ACOC) ACOC protection threshold by monitoring ACP_ACN voltage. 0: Disable ACOC (default at POR) 1: Enable ACOC [9] ACOC Limit (ACOC_VTH) ACOC protection threshold by monitoring ACP_ACN voltage. 0: 125% of ICRIT 1: 200% of ICRIT (default at POR) [8] Reserved [7] HSFET VDS Threshold (IFAULT_HI) MOSFET/inductor short protection by monitoring high side MOSFET drain-source voltage. 0: Disable (default at POR) 1: 750 mV [6] LSFET VDS Threshold (IFAULT_LO) MOSFET/inductor short protection by monitoring low side MOSFET drain-source voltage. Also as cycle-by-cycle current limit protection threshold during boost function. 0: Disable 1: 250 mV (default at POR) [5] Fast DPM Threshold (FDPM_VTH) [4:3] Fast DPM Deglitch Time (FDPM_DEG) [2] Input present indicator. Same logic as ACOK pin. This bit is read only. 0: AC adapter is not present 1: AC adapter is present 0 – Reserved Fast DPM comparator threshold to enter hybrid power boost mode. (Minimum DPM setting for boost mode: 1536 mA) 0: 107% (falling 93%)(
Source Exif Data:File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.4 Linearized : No Page Mode : UseOutlines Page Count : 56 Modify Date : 2017:04:29 18:14:17-05:00 Producer : iText 2.1.7 by 1T3XT Keywords : , SLUSC27, SLUSC27C Title : bq24780S 1 to 4-Cell Hybrid Power Boost Mode Battery Charge Controller (Rev. C) Author : Texas Instruments, Incorporated [SLUSC27,C.] Create Date : 2017:04:29 18:14:17-05:00 Creator : TopLeaf 8.0.017 Subject : Data SheetEXIF Metadata provided by EXIF.tools