Phase Locked Loops (ALTPLL) Megafunction User Guide C4 PLL
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Page Count: 68
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Contents
1. About this Megafunction
Device Family Support
Introduction
Features
Clock Domain Transfers
General Description
Stratix III and Cyclone III PLL New Features Description
Post-Scale Counter Cascading and Cascading PLLs
Common Applications
2. Getting Started
Using the MegaWizard Plug-In Manager
The ALTPLL Megafunction Page Descriptions (Excluding Stratix III and Cyclone III Devices)
ALTPLL Megafunction Page Descriptions (Stratix III and Cyclone III Devices Only)
Timing Analysis
Simulation
Simulating External Feedback Board Delay in Stratix II and Stratix II GX Devices
Design Examples
Design Files
Example 1: Differential Clock
Example 2: Generating Clock Signals
3. Specifications
Ports and Parameters
Additional Information
Document Revision History
Referenced Documents
How to Contact Altera
Typographic Conventions
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