Coffee Lake FSP Integration Guide

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CoffeeLake Intel(R) Firmware Support Package (FSP) Integration Guide
Wed Apr 17 2019 18:20:44
ii
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Contents
1 INTRODUCTION 1
2 FSP OVERVIEW 3
3 FSP INTEGRATION 5
4 FSP PORTING RECOMMENDATION 11
5 UPD PORTING GUIDE 13
6 FSP OUTPUT 15
7 FSP POSTCODE 19
8 Todo List 29
9 Deprecated List 31
10 Class Index 33
10.1 Class List ............................................... 33
11 File Index 35
11.1 File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
12 Class Documentation 37
12.1 AUDIO_AZALIA_VERB_TABLE Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.1.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.2 AZALIA_HEADER Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.2.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.3 CHIPSET_INIT_INFO Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.3.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.4 DIMM_INFO Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.4.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.5 FIRMWARE_VERSION Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.5.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.6 FIRMWARE_VERSION_INFO Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
iv CONTENTS
12.6.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.7 FIRMWARE_VERSION_INFO_HOB Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . 40
12.7.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.7.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.7.2.1 Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.8 FSP_M_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12.8.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.8.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.1 ActiveCoreCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.2 ApertureSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.3 ApStartupBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.4 Avx2RatioOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.5 Avx3RatioOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.6 BclkAdaptiveVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.7 BiosAcmBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.8.2.8 BiosAcmSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.9 BiosGuard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.10 BistOnReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.11 BootFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.12 ChHashEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.13 ChHashInterleaveBit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.14 ChHashMask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.8.2.15 CkeRankMapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.16 CleanMemory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.17 CmdRanksTerminated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.18 CoreMaxOcRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.19 CorePllVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.20 CoreVoltageAdaptive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.21 CoreVoltageMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
12.8.2.22 CoreVoltageOverride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.23 CpuRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.24 CpuTraceHubMemReg0Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.25 CpuTraceHubMemReg1Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.26 CpuTraceHubMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.27 DciUsb3TypecUfpDbg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.28 Ddr4MixedUDimm2DpcLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.8.2.29 DdrFreqLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.30 DisableDimmChannel0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.31 DisableDimmChannel1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.32 DisableMtrrProgram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CONTENTS v
12.8.2.33 DmiDeEmphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.34 DmiGen3EndPointHint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.35 DmiGen3EndPointPreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
12.8.2.36 DmiGen3ProgramStaticEq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.37 DmiGen3RootPortPreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.38 DpSscMarginEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.39 DualDimmPerChannelBoardType . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.40 EnableC6Dram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.41 EnableSgx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
12.8.2.42 EnBER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.43 EnCmdRate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.44 EpgEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.45 FClkFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.46 FivrEfficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.47 FivrFaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.48 ForceOltmOrRefresh2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
12.8.2.49 FreqSaGvLow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.50 FreqSaGvMid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.51 GdxcEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.52 GmAdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.53 GtPllVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.54 GtPsmiSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.55 GttMmAdr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
12.8.2.56 HobBufferSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.57 HotThresholdCh0Dimm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.58 HotThresholdCh0Dimm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.59 HotThresholdCh1Dimm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.60 HotThresholdCh1Dimm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.61 Idd3n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.62 Idd3p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
12.8.2.63 IgdDvmt50PreAlloc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.64 ImrRpSelection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.65 InitPcieAspmAfterOprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.66 InternalGfx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.67 IsvtIoPort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.68 JtagC10PowerGateDisable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.69 LpddrDramOdt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
12.8.2.70 McPllVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.71 MemoryTrace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.72 MmioSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
vi CONTENTS
12.8.2.73 OcLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.74 PcdDebugInterfaceFlags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.75 PcdIsaSerialUartBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.76 PcdSerialDebugBaudRate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.77 PcdSerialDebugLevel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
12.8.2.78 PcdSerialIoUartNumber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.79 PchLpcEnhancePort8xhDecoding . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.80 PchNumRsvdSmbusAddresses . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.81 PchPort80Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.82 PchSmbAlertEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.83 PchTraceHubMemReg0Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.84 PchTraceHubMemReg1Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
12.8.2.85 PchTraceHubMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.86 PcieImrSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.87 PcieRpEnableMask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.88 PeciC10Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.89 PeciSxReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.90 PegDataPtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
12.8.2.91 PegDisableSpreadSpectrumClocking . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.92 PlatformDebugConsent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.93 ProbelessTrace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.94 PwdwnIdleCounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.95 RankInterleave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.96 Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.97 RcompResistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
12.8.2.98 RcompTarget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.99 RealtimeMemoryTiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.100RefClk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.101RhSolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.102RingDownBin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.103RingMaxOcRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.104RingPllVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
12.8.2.105RingVoltageAdaptive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.106RingVoltageMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.107RingVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.108RingVoltageOverride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.109RMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.110RMTLoopCount . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.111RmtPerTask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
12.8.2.112SafeMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
CONTENTS vii
12.8.2.113SaGv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.114SaPllVoltageOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.115ScramblerSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.116SinitMemorySize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.117SkipMpInit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.118SmbusArpEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
12.8.2.119SmbusEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.120SpdAddressTable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.121SpdProfileSelected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.122TgaSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.123ThrtCkeMinTmr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.124ThrtCkeMinTmrLpddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.125TjMaxOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
12.8.2.126TrainTrace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.127tRTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.128TsegSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.129TsodAlarmwindowLockBit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.130TsodCriticalEventOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.131TsodCriticaltripLockBit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.132TsodEventMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
12.8.2.133TsodEventOutputControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.134TsodEventPolarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.135TsodManualEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.136TsodShutdownMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.137TsodTcritMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.138TvbRatioClipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.139TvbVoltageOptimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
12.8.2.140Txt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.141TxtDprMemoryBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.142TxtDprMemorySize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.143TxtHeapMemorySize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.144TxtImplemented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.145TxtLcpPdBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.146TxtLcpPdSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12.8.2.147UserBudgetEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.148UserThresholdEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.149VddVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.150VmxEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.151WarmThresholdCh0Dimm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.152WarmThresholdCh0Dimm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
viii CONTENTS
12.8.2.153WarmThresholdCh1Dimm0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
12.8.2.154WarmThresholdCh1Dimm1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.9 FSP_M_TEST_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.9.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.9.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.9.2.1 BdatEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
12.9.2.2 BdatTestType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.3 BiosSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.4 BypassPhySyncReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.5 DeltaT12PowerCycleDelayPreMem . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.6 DisableHeciRetry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.7 DisableMessageCheck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.8 DmiGen3EqPh2Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
12.9.2.9 DmiGen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.10 Gen3SwEqAlwaysAttempt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.11 Gen3SwEqEnableVocTest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.12 Gen3SwEqJitterDwellTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.13 Gen3SwEqJitterErrorTarget . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.14 Gen3SwEqNumberOfPresets . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
12.9.2.15 Gen3SwEqVocDwellTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.16 Gen3SwEqVocErrorTarget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.17 HeciCommunication2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.18 KtDeviceEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.19 LockPTMregs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.20 PanelPowerEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.21 Peg0Gen3EqPh2Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
12.9.2.22 Peg0Gen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.23 Peg1Gen3EqPh2Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.24 Peg1Gen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.25 Peg2Gen3EqPh2Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.26 Peg2Gen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.27 Peg3Gen3EqPh2Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
12.9.2.28 Peg3Gen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.29 PegGen3EndPointHint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.30 PegGen3EndPointPreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.31 PegGen3ProgramStaticEq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.32 PegGen3RootPortPreset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.33 PegGenerateBdatMarginTable . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
12.9.2.34 PegRxCemLoopbackLane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.35 PegRxCemNonProtocolAwareness . . . . . . . . . . . . . . . . . . . . . . . . 91
CONTENTS ix
12.9.2.36 ScanExtGfxForLegacyOpRom . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.37 SkipMbpHob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.38 SmbusDynamicPowerGating . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.39 SmbusSpdWriteDisable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.40 TotalFlashSize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12.9.2.41 tRd2RdDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.42 tRd2RdDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.43 tRd2RdDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.44 tRd2RdSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.45 tRd2WrDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.46 tRd2WrDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.47 tRd2WrDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.48 tRd2WrSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.9.2.49 tRRD_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.50 tRRD_S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.51 tWr2RdDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.52 tWr2RdDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.53 tWr2RdDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.54 tWr2RdSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.55 tWr2WrDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.9.2.56 tWr2WrDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.57 tWr2WrDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.58 tWr2WrSG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.59 tWTR_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.60 tWTR_S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.61 TxtAcheckRequest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.9.2.62 WdtDisableAndLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12.10FSP_S_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.10.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.1 AcLoadline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.2 AcousticNoiseMitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.3 AmtEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.4 AmtKvmEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.5 AmtSolEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.6 AsfEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
12.10.2.7 CpuMpHob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.8 DcLoadline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.9 DebugInterfaceEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.10DevIntConfigPtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
x CONTENTS
12.10.2.11DmiSuggestedSetting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.12DmiTS0TW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.13DmiTS1TW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
12.10.2.14DmiTS2TW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.15DmiTS3TW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.16EcCmdLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.17EcCmdProvisionEav . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.18Enable8254ClockGating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.19Enable8254ClockGatingOnS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.20EnableTcoTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.10.2.21EsataSpeedLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.22FastPkgCRampDisableFivr . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.23FastPkgCRampDisableGt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.24FastPkgCRampDisableIa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.25FastPkgCRampDisableSa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.26FivrRfiFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
12.10.2.27FivrSpreadSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.28ForcMebxSyncUp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.29FwProgress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.30GpioIrqRoute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.31Heci3Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.32IccMax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.33ImonOffset1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
12.10.2.34ImonSlope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.35ImonSlope1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.36IslVrCmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.37ManageabilityMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.38McivrRfiFrequencyAdjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.39McivrRfiFrequencyPrefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.40McivrSpreadSpectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
12.10.2.41MeUnconfigOnRtcClear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.42NumOfDevIntConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.43PchCnviMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.44PchCrid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.45PchDmiAspm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.46PchDmiAspmCtrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.47PchDmiTsawEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
12.10.2.48PchEnableComplianceMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.49PchEnableDbcObs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.50PchHdaAudioLinkDmic0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
CONTENTS xi
12.10.2.51PchHdaAudioLinkDmic1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.52PchHdaAudioLinkHda . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.53PchHdaAudioLinkSndw1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.54PchHdaAudioLinkSndw2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.10.2.55PchHdaAudioLinkSndw3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.56PchHdaAudioLinkSndw4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.57PchHdaAudioLinkSsp0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.58PchHdaAudioLinkSsp1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.59PchHdaAudioLinkSsp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.60PchHdaDspEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.61PchHdaDspUaaCompliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
12.10.2.62PchHdaIDispCodecDisconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.63PchHdaIDispLinkFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.64PchHdaIDispLinkTmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.65PchHdaLinkFrequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.66PchHdaPme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.67PchHdaSndwBufferRcomp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.68PchHdaVcType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.10.2.69PchHotEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.70PchIoApicEntry24_119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.71PchIoApicId . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.72PchIshGp0GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.73PchIshGp1GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.74PchIshGp2GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.75PchIshGp3GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.76PchIshGp4GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12.10.2.77PchIshGp5GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.78PchIshGp6GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.79PchIshGp7GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.80PchIshI2c0GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.81PchIshI2c1GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.82PchIshI2c2GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.83PchIshPdtUnlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
12.10.2.84PchIshSpiGpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.85PchIshUart0GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.86PchIshUart1GpioAssign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.87PchLanEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.88PchLanLtrEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.89PchLegacyIoLowLatency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.10.2.90PchLockDownBiosLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
xii CONTENTS
12.10.2.91PchLockDownRtcMemoryLock . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.92PchMemoryThrottlingEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.93PchPcieDeviceOverrideTablePtr . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.94PchPmDeepSxPol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.95PchPmDisableDsxAcPresentPulldown . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.96PchPmDisableNativePowerButton . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.97PchPmLanWakeFromDeepSx . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.10.2.98PchPmLpcClockRun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.99PchPmMeWakeSts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.100PchPmPciePllSsc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.101PchPmPcieWakeFromDeepSx . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.102PchPmPmeB0S5Dis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.103PchPmPwrBtnOverridePeriod . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.104PchPmPwrCycDur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.10.2.105PchPmSlpAMinAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.106PchPmSlpLanLowDc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.107PchPmSlpS0Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.108PchPmSlpS0Vm070VSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.109PchPmSlpS0Vm075VSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.110PchPmSlpS0VmRuntimeControl . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.111PchPmSlpS3MinAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.112PchPmSlpS4MinAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
12.10.2.113PchPmSlpStrchSusUp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.114PchPmSlpSusMinAssert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.115PchPmVrAlert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.116PchPmWolEnableOverride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.117PchPmWolOvrWkSts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.118PchPmWoWlanDeepSxEnable . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.119PchPmWoWlanEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
12.10.2.120PchPwrOptEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.121PchScsEmmcHs400DllDataValid . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.122PchScsEmmcHs400DriverStrength . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.123PchScsEmmcHs400TuningRequired . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.124PchSerialIoI2cPadsTermination . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.125PchSirqEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.126PchSirqMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
12.10.2.127PchStartFramePulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.128PchTsmicLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.129PchTTEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.130PchTTLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CONTENTS xiii
12.10.2.131PchTTState13Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.132PchUsbHsioFilterSel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.133PchUsbHsioRxTuningEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12.10.2.134PcieComplianceTestMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.135PcieDisableRootPortClockGating . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.136PcieEnablePeerMemoryWrite . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.137PcieEqPh3LaneParamCm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.138PcieEqPh3LaneParamCp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.139PcieRpAspm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.140PcieRpCompletionTimeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
12.10.2.141PcieRpDpcExtensionsMask . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.142PcieRpDpcMask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.143PcieRpFunctionSwap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.144PcieRpGen3EqPh3Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.145PcieRpImrEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.146PcieRpL1Substates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.147PcieRpPcieSpeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.10.2.148PcieRpPhysicalSlotNumber . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.149PcieRpPtmMask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.150PcieSwEqCoeffListCm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.151PcieSwEqCoeffListCp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.152PmcCpuC10GatePinEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.153PmcDbgMsgEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.154PmcModPhySusPgEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
12.10.2.155PmcPowerButtonDebounce . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.156PortUsb20Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.157PortUsb30Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.158PreWake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.159Psi1Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.160Psi2Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.161Psi3Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.10.2.162Psi3Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.163PsOnEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.164PsysOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.165PsysSlope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.166PxRcConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.167RemoteAssistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.168SataEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
12.10.2.169SataLedEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.170SataMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
xiv CONTENTS
12.10.2.171SataP0TDispFinit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.172SataP1TDispFinit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.173SataPortsDevSlp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.174SataPortsDmVal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.175SataPortsEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.176SataPwrOptEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.10.2.177SataRstHddUnlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.178SataRstInterrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.179SataRstIrrt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.180SataRstIrrtOnly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.181SataRstLedLocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.182SataRstOromUiBanner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.183SataRstPcieDeviceResetDelay . . . . . . . . . . . . . . . . . . . . . . . . . . 138
12.10.2.184SataRstRaid0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.185SataRstRaid1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.186SataRstRaid10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.187SataRstRaid5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.188SataRstRaidDeviceId . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.189SataRstSmartStorage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.190SataSalpSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.191SataThermalSuggestedSetting . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.10.2.192SciIrqSelect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.193ScsEmmcEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.194ScsEmmcHs400Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.195ScsSdCardEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.196ScsUfsEnabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.197SendEcCmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.198SendVrMbxCmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
12.10.2.199SerialIoDebugUartNumber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.200SerialIoDevMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.201SerialIoEnableDebugUartAfterPost . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.202SerialIoUart0PinMuxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.203ShowSpiController . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.204SiCsmFlag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.205SiNumberOfSsidTableEntry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.10.2.206SiSsidTablePtr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.207SkipMpInitDeprecated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.208SlowSlewRateForFivr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.209SlowSlewRateForGt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.210SlowSlewRateForIa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CONTENTS xv
12.10.2.211SlowSlewRateForSa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.212SlpS0DisQForDebug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.10.2.213SlpS0Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.214SlpS0WithGbeSupport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.215TcoIrqSelect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.216TdcPowerLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.217TdcTimeWindow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.218TetonGlacierMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.10.2.219TTSuggestedSetting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.220TurboMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.221TxtEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.222Usb2AfePehalfbit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.223Usb2AfePetxiset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.224Usb2AfePredeemp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.225Usb2AfeTxiset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.10.2.226Usb3HsioTxDeEmph . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.227Usb3HsioTxDeEmphEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.228Usb3HsioTxDownscaleAmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.229Usb3HsioTxDownscaleAmpEnable . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.230Usb3HsioTxRate0UniqTran . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.231Usb3HsioTxRate0UniqTranEnable . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.232Usb3HsioTxRate1UniqTran . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.10.2.233Usb3HsioTxRate1UniqTranEnable . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.234Usb3HsioTxRate2UniqTran . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.235Usb3HsioTxRate2UniqTranEnable . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.236Usb3HsioTxRate3UniqTran . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.237Usb3HsioTxRate3UniqTranEnable . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.238UsbPdoProgramming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.239VrPowerDeliveryDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.10.2.240VrVoltageLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10.2.241WatchDog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10.2.242WatchDogTimerBios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10.2.243WatchDogTimerOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.10.2.244XdciEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.11FSP_S_TEST_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
12.11.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.11.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.11.2.1 ApIdleManner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.11.2.2 AutoThermalReporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
12.11.2.3 C1e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
xvi CONTENTS
12.11.2.4 C1StateAutoDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.5 C1StateUnDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.6 C3StateAutoDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.7 C3StateUnDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.8 ConfigTdpBios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.9 CpuWakeUpTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.10CStatePreWake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
12.11.2.11CstCfgCtrIoMwaitRedirection . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.12Custom1ConfigTdpControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.13Custom1PowerLimit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.14Custom1PowerLimit1Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.15Custom1PowerLimit2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.16Custom1TurboActivationRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.17Custom2ConfigTdpControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
12.11.2.18Custom2PowerLimit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.19Custom2PowerLimit1Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.20Custom2PowerLimit2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.21Custom2TurboActivationRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.22Custom3ConfigTdpControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.23Custom3PowerLimit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.24Custom3PowerLimit1Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
12.11.2.25Custom3PowerLimit2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.26Custom3TurboActivationRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.27Cx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.28DebugInterfaceEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.29DebugInterfaceLockEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.30DisableProcHotOut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.31DisableVrThermalAlert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
12.11.2.32EightCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.33Eist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.34EnableItbm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.35EndOfPostMessage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.36EnergyEfficientPState . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.37EnergyEfficientTurbo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.38FiveCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
12.11.2.39FourCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.40HdcControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.41Hwp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.42HwpInterruptControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.43MachineCheckEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
CONTENTS xvii
12.11.2.44MaxRingRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.45MctpBroadcastCycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
12.11.2.46MinRingRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.47MlcStreamerPrefetcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.48MonitorMwaitEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.49NumberOfEntries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.50OneCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.51PchHdaResetWaitTimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.52PchLockDownBiosInterface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.11.2.53PchLockDownGlobalSmi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.54PchPmDisableEnergyReport . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.55PchSbAccessUnlock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.56PchUnlockGpioPads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.57PchXhciOcLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.58PcieEnablePort8xhDecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.59PcieRpDptp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
12.11.2.60PcieRpSlotPowerLimitScale . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.61PcieRpSlotPowerLimitValue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.62PcieRpUptp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.63PkgCStateDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.64PkgCStateLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.65PkgCStateUnDemotion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.66PmgCstCfgCtrlLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.67PowerLimit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.11.2.68PowerLimit1Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.69PowerLimit2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.70PowerLimit2Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.71PowerLimit3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.72PowerLimit4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.73ProcessorTraceEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.74ProcessorTraceMemBase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
12.11.2.75ProcessorTraceMemLength . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.76ProcessorTraceOutputScheme . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.77ProcHotResponse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.78PsysPmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.79PsysPowerLimit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.80PsysPowerLimit1Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.81PsysPowerLimit1Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.11.2.82PsysPowerLimit2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.83PsysPowerLimit2Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
xviii CONTENTS
12.11.2.84RaceToHalt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.85SataTestMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.86SevenCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.87SixCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.88StateRatio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
12.11.2.89StateRatioMax16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.90TccActivationOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.91TccOffsetClamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.92TccOffsetLock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.93TccOffsetTimeWindowForRatl . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.94ThreeCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.11.2.95ThreeStrikeCounterDisable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.11.2.96TimedMwait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.11.2.97TStates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.11.2.98TwoCoreRatioLimit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.12FSP_T_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.12.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.2.1 PcdSerialIoUart0PinMuxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.2.2 PcdSerialIoUartDebugEnable . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.12.2.3 PcdSerialIoUartNumber . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.13FSPM_UPD Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.13.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.14FSPS_UPD Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.14.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.15FSPT_CORE_UPD Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.15.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.16FSPT_UPD Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.16.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
12.17GPIO_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.17.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.17.2 Member Data Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.17.2.1 Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
12.17.2.2 ElectricalConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.3 HostSoftPadOwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.4 InterruptConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.5 LockConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.6 OutputState . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.7 PadMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
12.17.2.8 PowerConfig . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
CONTENTS xix
12.18HOB_USAGE_DATA_HOB Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.18.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.19MEMORY_PLATFORM_DATA Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.19.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.20SI_PCH_DEVICE_INTERRUPT_CONFIG Struct Reference . . . . . . . . . . . . . . . . . . . . . 176
12.20.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.21SMBIOS_CACHE_INFO Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
12.21.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.22SMBIOS_PROCESSOR_INFO Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
12.22.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
12.23SMBIOS_STRUCTURE Struct Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
12.23.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
13 File Documentation 181
13.1 FirmwareVersionInfoHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.1.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
13.2 FspFixedPcds.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.2.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.3 FspInfoHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.3.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
13.4 FspmUpd.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
13.4.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.5 FspsUpd.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
13.5.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
13.5.2 Enumeration Type Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13.5.2.1 SI_PCH_INT_PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13.6 FsptUpd.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
13.6.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.7 FspUpd.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
13.7.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.8 GpioConfig.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
13.8.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
13.8.2 Enumeration Type Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.8.2.1 GPIO_DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.8.2.2 GPIO_ELECTRICAL_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.8.2.3 GPIO_HARDWARE_DEFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.8.2.4 GPIO_HOSTSW_OWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
13.8.2.5 GPIO_INT_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.8.2.6 GPIO_LOCK_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
13.8.2.7 GPIO_OTHER_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
xx CONTENTS
13.8.2.8 GPIO_OUTPUT_STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.8.2.9 GPIO_PAD_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
13.8.2.10 GPIO_RESET_CONFIG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
13.9 GpioSampleDef.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
13.9.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.10HobUsageDataHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.10.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
13.11MemInfoHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
13.11.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.12SmbiosCacheInfoHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.12.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
13.13SmbiosProcessorInfoHob.h File Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
13.13.1 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Index 199
Chapter 1
INTRODUCTION
1 Introduction
1.1 Purpose
The purpose of this document is to describe the steps required to integrate the Intel® Firmware Support Package
(FSP) into a boot loader solution. It supports CoffeeLake platforms with CoffeeLake processor and CoffeeLake
Platform Controller Hub (PCH).
1.2 Intended Audience
This document is targeted at all platform and system developers who need to consume FSP binaries in their boot
loader solutions. This includes, but is not limited to: system BIOS developers, boot loader developers, system
integrators, as well as end users.
1.3 Related Documents
Platform Initialization (PI) Specification v1.4 located at http://www.uefi.org/specifications
Intel® Firmware Support Package: External Architecture Specification (EAS) v2.0 located at http-
://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.-
pdf
Boot Setting File Specification (BSF) v1.0 https://firmware.intel.com/sites/default/files/-
BSF_1_0.pdf
Binary Configuration Tool for Intel® Firmware Support Package available at http://www.intel.-
com/fsp
1.4 Acronyms and Terminology
Acronym Definition
BCT Binary Configuration Tool
BSF Boot Setting File
BSP Boot Strap Processor
BWG BIOS Writer's Guide
2 INTRODUCTION
CAR Cache As Ram
CRB Customer Reference Board
FIT Firmware Interface Table
FSP Firmware Support Package
FSP API Firmware Support Package Interface
FW Firmware
PCH Platform Controller Hub
PMC Power Management Controller
SBSP System BSP
SMI System Management Interrupt
SMM System Management Mode
SPI Serial Peripheral Interface
TSEG Memory Reserved at the Top of Memory to be used
as SMRAM
UPD Updatable Product Data
IED Intel Enhanced Debug
GTT Graphics Translation Table
BDSM Base Data Of Stolen Memory
PMRR Protected Memory Range Reporting
IOT Internal Observation Trace
MOT Memory Observation Trace
DPR DMA Protected Range
REMAP Remapped Memory Area
TOLUD Top of Low Usable Memory
TOUUD Top of Upper Usable Memory
Chapter 2
FSP OVERVIEW
FSP Overview
2.1 Technical Overview
The Intel® Firmware Support Package (FSP) provides chipset and processor initialization in a format that can easily
be incorporated into many existing boot loaders.
The FSP will perform the necessary initialization steps as documented in the BWG including initialization of the
CPU, memory controller, chipset and certain bus interfaces, if necessary.
FSP is not a stand-alone boot loader; therefore it needs to be integrated into a host boot loader to carry out other
boot loader functions, such as: initializing non-Intel components, conducting bus enumeration, and discovering
devices in the system and all industry standard initialization.
The FSP binary can be integrated easily into many different boot loaders, such as Coreboot, EDKII etc. and also
into the embedded OS directly.
Below are some required steps for the integration:
Customizing The static FSP configuration parameters are part of the FSP binary and can be customized by
external tools that will be provided by Intel.
Rebasing The FSP is not Position Independent Code (PIC) and the whole FSP has to be rebased if it is
placed at a location which is different from the preferred address during build process.
Placing Once the FSP binary is ready for integration, the boot loader build process needs to be modified to
place this FSP binary at the specific rebasing location identified above.
Interfacing The boot loader needs to add code to setup the operating environment for the FSP, call the FSP
with correct parameters and parse the FSP output to retrieve the necessary information returned by the FSP.
2.2 FSP Distribution Package
The FSP distribution package contains the following:
FSP Binary
FSP Integration Guide
BSF Configuration File
Data Structure Header File
The FSP configuration utility called BCT is available as a separate package. It can be downloaded from link
mentioned in Section 1.3.
4 FSP OVERVIEW
2.2.1 Package Layout
Docs (Auto generated)
CoffeeLake_FSP_Integration_Guide.pdf
CoffeeLake_FSP_Integration_Guide.chm
Include
FsptUpd.h,FspmUpd.h and FspsUpd.h (FSP UPD structure and related definitions)
GpioSampleDef.h (Sample enum definitions for Gpio table)
CoffeeLakeFspBinPkg.dec (EDKII declaration file for package)
Fsp.bsf (BSF file for configuring the data using BCT tool)
Fsp.fd (FSP Binary)
Chapter 3
FSP INTEGRATION
3 FSP Integration
3.1 Assumptions Used in this Document
The FSP for the CoffeeLake platform is built with a preferred base address given by PcdFspAreaBaseAddress and
so the reference code provided in the document assumes that the FSP is placed at this base address during the
final boot loader build. Users may rebase the FSP binary at a different location with Intel's Binary Configuration Tool
(BCT) before integrating to the boot loader.
For other assumptions and conventions, please refer section 8 in the FSP External Architecture Specification version
2.0.
3.2 Boot Flow
Please refer Chapter 7 in the FSP External Architecture Specification version 2.0 for Boot flow chart.
3.3 FSP INFO Header
The FSP has an Information Header that provides critical information that is required by the bootloader to suc-
cessfully interface with the FSP. The structure of the FSP Information Header is documented in the FSP External
Architecture Specification version 2.0 with a HeaderRevision of 3.
3.4 FSP Image ID and Revision
FSP information header contains an Image ID field and an Image Revision field that provide the identification and
revision information of the FSP binary. It is important to verify these fields while integrating the FSP as AP-
I parameters could change over different FSP IDs and revisions. All the FSP FV segments(FSP-T, FSP-M and
FSP-S) must have same FSP Image ID and revision number, using FV segments with different revision numbers in
a single FSP image is not valid. The FSP API parameters documented in this integration guide are applicable for
the Image ID and Revision specified as below.
The FSP ImageId string in the FSP information header is given by PcdFspImageIdString and the ImageRevision
field is given by SiliconInitVersionMajor|Minor|FspVersionRevision|FspVersionBuild (Ex:0x07020110).
3.5 FSP Global Data
FSP uses some amount of TempRam area to store FSP global data which contains some critical data like pointers to
FSP information headers and UPD configuration regions, FSP/Bootloader stack pointers required for stack switching
6 FSP INTEGRATION
etc. HPET Timer register(2) PcdGlobalDataPointerAddress is reserved to store address of this global data, and
hence boot loader should not use this register for any other purpose. If TempRAM initialization is done by boot
loader, then HPET has to be initialized to the base so that access to the register will work fine.
3.6 FSP APIs
This release of the CoffeeLake FSP supports the all APIs required by the FSP External Architecture Specification
version 2.0. The FSP information header contains the address offset for these APIs. Register usage is described in
the FSP External Architecture Specification version 2.0. Any usage not described by the specification is described
in the individual sections below.
The below sections will highlight any changes that are specific to this FSP release.
3.6.1 TempRamInit API
Please refer Chapter 8.5 in the FSP External Architecture Specification version 2.0 for complete details including
the prototype, parameters and return value details for this API.
TempRamInit does basic early initialization primarily setting up temporary RAM using cache. It returns ECX point-
ing to beginning of temporary memory and EDX pointing to end of temporary memory + 1. The total temporary
ram currently available is given by PcdTemporaryRamSize starting from the base address of PcdTemporaryRam-
Base. Out of total temporary memory avaiable, last PcdFspReservedBufferSize bytes of space reserved by FSP for
TempRamInit if temporary RAM initialization is done by FSP and remaining space from TemporaryRamBase(ECX)
to TemporaryRamBase+TemporaryRamSize-FspReservedBufferSize (EDX) is avaiable for both bootloader and
FSP binary.
TempRamInit∗∗ also sets up the code caching of the region passed CodeCacheBase and CodeCacheLength, which
are input parameters to TempRamInitApi. if 0 is passed in for CodeCacheBase, the base used will be 4 GB - 1 -
length to be code cached instead of starting from CodeCacheBase.
Note
: when programming MTRR CodeCacheLength will be reduced, if SKU LLC size is smaller than the requested.
It is a requirement for Firmware to have Firmware Interface Table (FIT), which contains pointers to each microcode
update. The microcode update is loaded for all logical processors before reset vector. If more than microcode
update for the CPU is present, the microcode update with the latest revision is loaded.
FSPT_UPD.MicrocodeRegionBase∗∗ and FSPT_UPD.MicrocodeRegionLength are input parameters to Temp-
RamInit API. If these values are 0, FSP will not attempt to update microcode. If a region is passed, then if a newer
microcode update revision is in the region, it will be loaded by the FSP.
MTRRs are programmed to the default values to have the following memory map:
Memory range Cache Attribute
0xFEF00000 - 0x00040000 Write back
CodeCacheBase - CodeCacheLength Write protect
3.6.2 FspMemoryInit API
Please refer to Chapter 8.6 in the FSP external Architecture Specification version 2.0 for the prototype, parameters
and return value details for this API.
The FspmUpdPtr is pointer to FSPM_UPD structure which is described in header file FspmUpd.h.
Boot Loader must pass valid CAR region for FSP stack use through FSPM_UPD.FspmArchUpd.StackBase and
FSPM_UPD.FspmArchUpd.StackSize UPDs.
The minimum FSP stack size required for this revision of FSP is 160KB, stack base is 0xFEF17F00 by default.
The base address of HECI device (Bus 0, Device 22, Function 0) is required to be initialized prior to perform Fsp-
MemoryInit flow. The default address is programmed to 0xFED1A000.
7
Calculate memory map determining memory regions TSEG, IED, GTT, BDSM, ME stolen, Uncore PMRR, IOT,
MOT, DPR, REMAP, TOLUD, TOUUD. Programming will be done at a different time.
3.6.3 TempRamExit API
Please refer to Chapter 8.7 in the FSP external Architecture Specification version 2.0 for the prototype, parameters
and return value details for this API.
If Boot Loader initializes the Temporary RAM (CAR) and skip calling TempRamInit API, it is expected that boot-
loader must skip calling this API and bootloader will tear down the temporary memory area setup in the cache and
bring the cache to normal mode of operation.
This revision of FSP doesn't have any fields/structure to pass as parameter for this API. Pass Null for TempRam-
ExitParamPtr.
At the end of TempRamExit the original code and data caching are disabled. FSP will reconfigure all MTRRs as
described in the table below for performance optimization.
Memory range Cache Attribute
0x00000000 - 0x0009FFFF Write back
0x000C0000 - Top of Low Memory Write back
0xFF000000 - 0xFFFFFFFF (Flash region) Write protect
Todo program 0x1000000000 - Top of High Memory |Write back
If the boot loader wish to reconfigure the MTRRs differently, it can be overridden immediately after this API call.
3.6.4 FspSiliconInit API
Please refer to Chapter 8.8 in the FSP external Architecture Specification version 2.0 for the prototype, parameters
and return value details for this API.
The FspsUpdPtr is pointer to FSPS_UPD structure which is described in header file FspsUpd.h.
It is expected that boot loader will program MTRRs for SBSP as needed after TempRamExit but before entering
FspSiliconInit. If MTRRs are not programmed properly, the boot performance might be impacted.
The region of 0x5_8000 - 0x5_8FFF is used by FspSilicionInit for starting APs. If this data is important to bootloader,
then bootloader needs to preserve it before calling FspSilicionInit.
It is a requirement for bootloader to have Firmware Interface Table (FIT), which contains pointers to each microcode.
The microcode is loaded for all cores before reset vector. If more than one microcode update for the CPU is present,
the latest revision is loaded.
MicrocodeRegionBase and MicrocodeRegionLength are both input parameters to TempRamInit and UPD for
SiliconInit API. UPD has priority and will be searched for a later revision than TempRamInit. If MicrocodeRegion-
Base and MicrocodeRegionLength values are 0, FSP will not attempt to update the microcode. If a microcode
region is passed, and if a later revision of microcode is present in this region, FSP will load it.
FSP initializes PCH audio including selecting HD Audio verb table and initializes Codec.
PCH required initialization is done for the following HECI, USB, HSIO, Integrated Sensor Hub, Camera, PCI Express,
Vt-d.
FSP initializes CPU features: XD, VMX, AES, IED, HDC, x(2)Apic, Intel® Processor Trace, Three strike counter,
Machine check, Cache pre-fetchers, Core PMRR, Power management.
Initializes HECI, DMI, Internal Graphics. Publish EFI_PEI_GRAPHICS_INFO_HOB during normal boot but this
HOB will not be published during S3 resume as FSP will not launch the PEI Graphics PEIM during S3 resume.
Programs SA Bars: MchBar, DmiBar, EpBar, GdxcBar, EDRAM (if supported). Please refer to section 2.-
8 (MemoryMap) for the corresponding Bar values. GttMmadr (0xDF000000) and GmAdr(0xC0000000) are tem-
porarily programmed and cleared after use in FSP.
8 FSP INTEGRATION
3.6.5 NotifyPhase API
Please refer Chapter 8.9 in the FSP External Architecture Specification version 2.0 for the prototype, parameters
and return value details for this API.
3.6.5.1 PostPciEnumeration Notification
This phase EnumInitPhaseAfterPciEnumeration is to be called after PCI enumeration but before execution of third
party code such as option ROMs. Currently, nothing is done in this phase, but in the future updates, programming
may be done in this phase.
3.6.5.2 ReadyToBoot Notification
This phase EnumInitPhaseReadyToBoot is to be called before giving control to boot. It includes some final initial-
ization steps recommended by the BWG, including power management settings, Send ME Message EOP (End of
Post).
3.6.5.3 EndOfFirmware Notification
This phase EnumInitEndOfFirmware is to be called before the firmware/preboot environment transfers management
of all system resources to the OS or next level execution environment. It includes final locking of chipset registers
3.7 Memory Map
Below diagram represents the memory map allocated by FSP including the FSP specific regions.
Figure 3.1: System Memory Map
9
/∗∗
10 FSP INTEGRATION
Chapter 4
FSP PORTING RECOMMENDATION
4 FSP Porting Recommendation
Here listed some notes or recommendation when porting with FSP.
4.1 Locking PAM register
FSP 2.0 introduced EndOfFirmware Notify phase callback which is a recommended place for locking PAM registers
so FSP by default implemented this way. If it is still too early to lock PAM registers then the PAM locking code inside
FSP can be disabled by UPD ->FSP_S_TEST_CONFIG ->SkipPamLock or SA policy ->_SI_PREMEM_PO-
LICY_STRUCT ->SA_MISC_PEI_CONFIG ->SkipPamLock, and platform or wrapper code should do the PAM
locking right before booting OS (so do it outside FSP instead) by programming one PCI config space register as
below.
This PAM locking step has to been applied in all boot paths including S3 resume. To lock PAM regsiter:
MmioOr32 (B0: D0: F0: Register 0x80, BIT0)
4.2 Locking SMRAM register
Since SMRAM locking is recommended to be locked before any 3rd party OpROM execution and highly depending
on platform code implementation, the FSP code by default will not lock it. The platform or FSP Wrapper code
should lock SMRAM by below programming step before any 3rd partiy OpRom execution (and should be locked in
S3 resume right before OS waking vector).
PciOr8 (B0: D0: F0: Register 0x88, BIT4); Note: it must be programmed by CF8/CFC Standard PCI access
mechanism. (MMIO access will not work)
4.3 Locking SMI register
Global SMI bit is recommended to be locked before any 3rd party OpROM execution and highly depending on
platform code implementation after SMM configuration. FSP by default will not lock it. Boot loader is responsible for
locking below regsiters after SMM configuration. Set AcpiBase + 0x30[0] to 1b to enable global SMI. Set PMC PCI
offset A0h[4] = 1b to lock SMI.
4.4 Verify below settings are correct for your platforms
PMC PciCfgSpace is not PCI compliant.FSP will hide the PMC controller to avoid external software or OS from
corrupting the BAR addresses. FSP will program the PMC controller IO and MMIO BAR's with below addresses.
Please use this addrerss in the wrapper code instead of reading from PMC controller.
12 FSP PORTING RECOMMENDATION
Register Values
ABASE 0x1800
PWRMBASE 0xFE000000
PCIEXBAR_BASE_ADDRESS 0xE0000000
Note
:
Boot Loader can use different value for PCIEXBAR_BASE_ADDRESS either by modifying the UPD
(under FSP-T) or by overriding the PCIEXBAR (B0:D0:F0:R60h) before calling FspMemoryInit Api.
Boot Loader should avoid using conflicting address when reprogramming PCIEXBAR_BASE_ADDR-
ESS than the recommended one.
4.5 FSP_STATUS_RESET_REQUIRED
As per FSP External Architecture Specification version 2.0, Any reset required in the FSP flow will be reported as
return status FSP_STATUS_RESET_REQUIREDx by the API.It is the bootloader responsibility to reset the system
according to the reset type requested.
Below table specifies the return status returned by FSP API and the requested reset type.
FSP_STATUS_RESET_REQUIRED Code Reset Type requested
0x40000001 Cold Reset
0x40000002 Warm Reset
0x40000003 Global Reset - Puts the system to Global reset
through Heci or Full Reset through PCH
0x40000004 Reserved
0x40000005 Reserved
0x40000006 Reserved
0x40000007 Reserved
0x40000008 Reserved
Chapter 5
UPD PORTING GUIDE
5 UPD porting guide
UPD porting guide:
UPD Dependency Description Value
EnableSgx CoffeeLake Platform Temporary workaround 2
PchTraceHubMode CoffeeLake Pch A0 BIOS workaround for
TraceHub power gating
issue on PCH A0
2
PchTraceHubMem-
Reg0Size
CoffeeLake Pch A0 BIOS workaround for
TraceHub power gating
issue on PCH A0
3
PchTraceHubMem-
Reg1Size
CoffeeLake Pch A0 BIOS workaround for
TraceHub power gating
issue on PCH A0
3
CstateLatencyControl1-
Irtl
Server platform Server platform should
has different setting
0x6B
PchPcieHsioRxSetCtle-
Enable
Board design Different board requires
different value
tune
PchPcieHsioRxSetCtle Board design Different board requires
different value
tune
PchSataHsioRxGen3-
EqBoostMagEnable
Board design Different board requires
different value
tune
PchSataHsioRxGen3-
EqBoostMag
Board design Different board requires
different value
tune
PchSataHsioTxGen1-
DownscaleAmpEnable
Board design Different board requires
different value
tune
PchSataHsioTxGen1-
DownscaleAmp
Board design Different board requires
different value
tune
PchSataHsioTxGen2-
DownscaleAmpEnable
Board design Different board requires
different value
tune
PchSataHsioTxGen2-
DownscaleAmp
Board design Different board requires
different value
tune
PchNumRsvdSmbus-
Addresses
Board design Different board requires
different value
tune
RsvdSmbusAddress-
TablePtr
Board design Different board requires
different value
tune
14 UPD PORTING GUIDE
BiosSize Board design Different board requires
different value
tune
Chapter 6
FSP OUTPUT
6 FSP Output
The FSP builds a series of data structures called the Hand-Off-Blocks (HOBs) as it progresses through initializing
the silicon.
Please refer to the Platform Initialization (PI) Specification - Volume 3: Shared Architectural Elements specification
for PI Architectural HOBs. Please refer Chapter 9 in the FSP External Architecture Specification version 2.0 for
details about FSP Architectural HOBs.
Below section describe the HOBs not covered in the above two specifications.
6.1 SMRAM Resource Descriptor HOB
The FSP will report the system SMRAM T-SEG range through a generic resource HOB if T-SEG is enabled. The
owner field of the HOB identifies the owner as T-SEG.
#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \
{ 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } }
6.2 SMBIOS INFO HOB
The FSP will report the SMBIOS through a HOB with below GUID. This information can be consumed by the
bootloader to produce the SMBIOS tables. These structures are included as part of MemInfoHob.h ,Smbios-
CacheInfoHob.h,SmbiosProcessorInfoHob.h &FirmwareVersionInfoHob.h
#define SI_MEMORY_INFO_DATA_HOB_GUID \
{ 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } };
typedef struct {
MrcDimmStatus Status; ///< See MrcDimmStatus for the definition of this field.
UINT8 DimmId;
UINT32 DimmCapacity; ///< DIMM size in MBytes.
UINT16 MfgId;
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4
20 bytes as per JEDEC Spec, so reserving 20 bytes
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS
structure creation.
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS
structure creation.
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for
SMBIOS structure creation.
UINT8 SpdSave[MAX_SPD_SAVE_DATA]; ///< Save SPD Manufacturing information needed for SMBIOS
structure creation.
}DIMM_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this channel should be used.
UINT8 ChannelId;
16 FSP OUTPUT
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
MRC_CH_TIMING Timing[MAX_PROFILE]; ///< The channel timing values.
DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
} CHANNEL_INFO;
typedef struct {
UINT8 Status; ///< Indicates whether this controller should be used.
UINT16 DeviceId; ///< The PCI device id of this memory controller.
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
} CONTROLLER_INFO;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
UINT8 Revision;
UINT16 DataWidth;
/// As defined in SMBIOS 3.0 spec
/// Section 7.18.2 and Table 75
UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
UINT32 Frequency; ///< The system’s common memory controller frequency in MT/s.
/// As defined in SMBIOS 3.0 spec
/// Section 7.17.3 and Table 72
UINT8 ErrorCorrectionType;
SiMrcVersion Version;
UINT32 FreqMax;
BOOLEAN EccSupport;
UINT8 MemoryProfile;
UINT32 TotalPhysicalMemorySize;
BOOLEAN XmpProfileEnable;
UINT8 Ratio;
UINT8 RefClk;
UINT32 VddVoltage[MAX_PROFILE];
CONTROLLER_INFO Controller[MAX_NODE];
} MEMORY_INFO_DATA_HOB;
#define SI_MEMORY_PLATFORM_DATA_HOB \
{ 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }
typedef struct {
UINT8 Revision;
UINT8 Reserved[3];
UINT32 BootMode;
UINT32 TsegSize;
UINT32 TsegBase;
UINT32 PrmrrSize;
UINT32 PrmrrBase;
UINT32 GttBase;
UINT32 MmioSize;
UINT32 PciEBaseAddress;
}MEMORY_PLATFORM_DATA;
typedef struct {
EFI_HOB_GUID_TYPE EfiHobGuidType;
MEMORY_PLATFORM_DATA Data;
UINT8 *Buffer;
} MEMORY_PLATFORM_DATA_HOB;
#define SMBIOS_CACHE_INFO_HOB_GUID \
{ 0xd805b74e, 0x1460, 0x4755, {0xbb, 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7} }
///
/// SMBIOS Cache Info HOB Structure
///
typedef struct {
UINT16 ProcessorSocketNumber;
UINT16 NumberOfCacheLevels; ///< Based on Number of Cache Types L1/L2/L3
UINT8 SocketDesignationStrIndex; ///< String Index in the string Buffer. Example "L1-CACHE"
UINT16 CacheConfiguration; ///< Format defined in SMBIOS Spec v3.0 Section7.8 Table36
UINT16 MaxCacheSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 InstalledSize; ///< Format defined in SMBIOS Spec v3.0 Section7.8.1
UINT16 SupportedSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT16 CurrentSramType; ///< Format defined in SMBIOS Spec v3.0 Section7.8.2
UINT8 CacheSpeed; ///< Cache Speed in nanoseconds. 0 if speed is unknown.
UINT8 ErrorCorrectionType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.3
UINT8 SystemCacheType; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.4
UINT8 Associativity; ///< ENUM Format defined in SMBIOS Spec v3.0 Section 7.8.5
///String Buffer - each string terminated by NULL "0x00"
///String buffer terminated by double NULL "0x0000"
}SMBIOS_CACHE_INFO;
#define SMBIOS_PROCESSOR_INFO_HOB_GUID \
{ 0xe6d73d92, 0xff56, 0x4146, {0xaf, 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71} }
///
/// SMBIOS Processor Info HOB Structure
17
///
typedef struct {
UINT16 TotalNumberOfSockets;
UINT16 CurrentSocketNumber;
UINT8 ProcessorType; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.1
///This info is used for both ProcessorFamily and ProcessorFamily2 fields
///See ENUM defined in SMBIOS Spec v3.0 Section 7.5.2
UINT16 ProcessorFamily;
UINT8 ProcessorManufacturerStrIndex; ///< Index of the String in the String Buffer
UINT64 ProcessorId; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.3
UINT8 ProcessorVersionStrIndex; ///< Index of the String in the String Buffer
UINT8 Voltage; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.4
UINT16 ExternalClockInMHz; ///< External Clock Frequency. Set to 0 if unknown.
UINT16 CurrentSpeedInMHz; ///< Snapshot of current processor speed during boot
UINT8 Status; ///< Format defined in the SMBIOS Spec v3.0 Table 21
UINT8 ProcessorUpgrade; ///< ENUM defined in SMBIOS Spec v3.0 Section 7.5.5
///This info is used for both CoreCount & CoreCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.6
UINT16 CoreCount;
///This info is used for both CoreEnabled & CoreEnabled2 fields
///See detailed description in SMBIOS Spec v3.0 Section 7.5.7
UINT16 EnabledCoreCount;
///This info is used for both ThreadCount & ThreadCount2 fields
/// See detailed description in SMBIOS Spec v3.0 Section 7.5.8
UINT16 ThreadCount;
UINT16 ProcessorCharacteristics; ///< Format defined in SMBIOS Spec v3.0 Section 7.5.9
/// String Buffer - each string terminated by NULL "0x00"
/// String buffer terminated by double NULL "0x0000"
}SMBIOS_PROCESSOR_INFO;
#define SMBIOS_FIRMWARE_VERSION_INFO_HOB_GUID \
{ 0x798e722e, 0x15b2, 0x4e13, { 0x8a, 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }}
///
/// Firmware Version Structure
///
typedef struct {
UINT8 MajorVersion;
UINT8 MinorVersion;
UINT8 Revision;
UINT16 BuildNumber;
}FIRMWARE_VERSION;
///
/// Firmware Version Information Structure
///
typedef struct {
UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware
version
}FIRMWARE_VERSION_INFO;
///
/// The Smbios structure header.
///
typedef struct {
UINT8 Type;
UINT8 Length;
UINT16 Handle;
}SMBIOS_STRUCTURE;
///
/// Firmware Version Information HOB Structure
///
typedef struct {
EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS
header of FVI HOB
UINT8 Count; ///< Offset 28 Number of FVI elements
included.
///
/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
///
}FIRMWARE_VERSION_INFO_HOB;
6.3 CHIPSETINIT INFO HOB
The FSP will report the ChipsetInit CRC through a HOB with below GUID. This information can be consumed by the
bootloader to check if ChipsetInit CRC is matched between BIOS and ME. These structures are included as part of
FspsUpd.h
18 FSP OUTPUT
#define CHIPSETINIT_INFO_HOB_GUID \
{ 0xc1392859, 0x1f65, 0x446e, { 0xb3, 0xf5, 0x84, 0x35, 0xfc, 0xc7, 0xd1, 0xc4 }}
///
/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
///
typedef struct {
UINT8 Revision;
UINT8 Rsvd[3];
UINT16 MeChipInitCrc;
UINT16 BiosChipInitCrc;
}CHIPSET_INIT_INFO;
6.4 HOB USAGE INFO HOB
The FSP will report the Hob memory usage through a HOB with below GUID. This information can be consumed by
the bootloader to check how many the temporary ram left.
#define HOB_USAGE_DATA_HOB_GUID \
{0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x20, 0xfc, 0x7c, 0xe1, 0xf6 }}
typedef struct {
EFI_PHYSICAL_ADDRESS EfiMemoryTop;
EFI_PHYSICAL_ADDRESS EfiMemoryBottom;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop;
EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom;
UINTN FreeMemory;
}HOB_USAGE_DATA_HOB;
Chapter 7
FSP POSTCODE
7 FSP PostCode
The FSP outputs 16 bit postcode to indicate which API and in which module the execution is happening.
Bit Range Description
Bit15 - Bit12 (X) used to indicate the phase/api under which the code
is executing
Bit11 - Bit8 (Y) used to indicate the module
Bit7 (ZZ bit 7) reserved for error
Bit6 - Bit0 (ZZ) individual codes
7.1 PostCode Info
Below diagram represents the 16 bit PostCode usage in FSP.
X Y ZZ
FSP API - 4 BITS (one Digit)
F - Tempraminit /SEC
E - Reserved
D - MemoryInit /Pre-Memory
C - Reserved
B - Tempramexit
A - Reserved
9 - SiliconInit /Post Memory
8 - Reserved
7 - Reserved
6 - Notify / Post PCIE Enumeration
5 - Reserved
4 - Notify / Ready To Boot
3 - Reserved
2 - Notify / End Of Firmware
1-0 - Reserved
Module - 4 BITS (one digit)
7 - Gfx PEIM
8 - FSP Common Code
9 - Silicon Common Code
A - System Agent
B - PCH
C - CPU
D - MRC
E - ME-BIOS
F - Reserved
Individual Codes
0x00 - API Entry
0x7F - API Exit
(Bit7 reserved for error)
7.1.1 TempRamInit API Status Codes (0xFxxx)
20 FSP POSTCODE
PostCode Module Description
0x0000 FSP TempRamInit API Entry (The
change in upper byte is due to not
enabling of the Port81 early in the
boot)
0x007F FSP TempRamInit API Exit
7.1.2 FspMemoryInit API Status Codes (0xDxxx)
PostCode Module Description
0xD800 FSP FspMemoryInit API Entry
0xD87F FSP FSpMemoryInit API Exit
0xDA00 SA Pre-Mem SaInit Entry
0xDA02 SA OverrideDev0Did Start
0xDA04 SA OverrideDev2Did Start
0xDA06 SA Programming SA Bars
0xDA08 SA Install SA HOBs
0xDA0A SA Reporting SA PCIe code version
0xDA0C SA SaSvInit Start
0xDA10 SA Initializing DMI
0xDA15 SA Initialize TCSS PreMem
0xDA1F SA Initializing DMI/OPI Max PayLoad
Size
0xDA20 SA Initializing SwitchableGraphics
0xDA30 SA Initializing SA PCIe
0xDA3F SA Programming PEG credit values
Start
0xDA40 SA Initializing DMI Tc/Vc mapping
0xDA42 SA CheckOffboardPcieVga
0xDA44 SA CheckAndInitializePegVga
0xDA50 SA Initializing Graphics
0xDA52 SA Initializing System Agent
Overclocking
0xDA7F SA Pre-Mem SaInit Exit
0xDB00 PCH Pre-Mem PchInit Entry
0xDB02 PCH Pre-Mem Disable PCH fused
controllers
0xDB15 PCH Pre-Mem SMBUS configuration
0xDB48 PCH Pre-Mem PchOnPolicyInstalled
Entry
0xDB49 PCH Pre-Mem Program HSIO
0xDB4A PCH Pre-Mem DCI configuration
0xDB4C PCH Pre-Mem Host DCI enabled
0xDB4D PCH Pre-Mem Trace Hub - Early
configuration
0xDB4E PCH Pre-Mem Trace Hub - Device
disabled
0xDB4F PCH Pre-Mem TraceHub -
Programming MSR
21
0xDB50 PCH Pre-Mem Trace Hub - Power
gating configuration
0xDB51 PCH Pre-Mem Trace Hub - Power
gating Trace Hub device and
locking HSWPGCR1 register
0xDB52 PCH Pre-Mem Initialize HPET timer
0xDB55 PCH Pre-Mem PchOnPolicyInstalled
Exit
0xDB7F PCH Pre-Mem PchInit Exit
0xDC00 CPU CPU Pre-Mem Entry
0xDC0F CPU CpuAddPreMemConfigBlocks
Done
0xDC20 CPU CpuOnPolicyInstalled Start
0xDC2F CPU XmmInit Start
0xDC3F CPU TxtInit Start
0xDC4F CPU Init CPU Straps
0xDC5F CPU Init Overclocking
0xDC6F CPU CPU Pre-Mem Exit
0x∗∗55 SA MRC_MEM_INIT_DONE
0x∗∗D5 SA MRC_MEM_INIT_DONE_WITH-
_ERRORS
0xDD00 SA MRC_INITIALIZATION_START
0xDD10 SA MRC_CMD_PLOT_2D
0xDD1B SA MRC_FAST_BOOT_PERMITTED
0xDD1C SA MRC_RESTORE_NON_TRAINI-
NG
0xDD1D SA MRC_PRINT_INPUT_PARAMS
0xDD1E SA MRC_SET_OVERRIDES_PSPD
0xDD20 SA MRC_SPD_PROCESSING
0xDD21 SA MRC_SET_OVERRIDES
0xDD22 SA MRC_MC_CAPABILITY
0xDD23 SA MRC_MC_CONFIG
0xDD24 SA MRC_MC_MEMORY_MAP
0xDD25 SA MRC_JEDEC_INIT_LPDDR3
0xDD26 SA MRC_RESET_SEQUENCE
0xDD27 SA MRC_PRE_TRAINING
0xDD28 SA MRC_EARLY_COMMAND
0xDD29 SA MRC_SENSE_AMP_OFFSET
0xDD2A SA MRC_READ_MPR
0xDD2B SA MRC_RECEIVE_ENABLE
0xDD2C SA MRC_JEDEC_WRITE_LEVELI-
NG
0xDD2D SA MRC_LPDDR_LATENCY_SET_B
0xDD2E SA MRC_WRITE_TIMING_1D
0xDD2F SA MRC_READ_TIMING_1D
0xDD30 SA MRC_DIMM_ODT
0xDD31 SA MRC_EARLY_WRITE_TIMING-
_2D
22 FSP POSTCODE
0xDD32 SA MRC_WRITE_DS
0xDD33 SA MRC_WRITE_EQ
0xDD34 SA MRC_EARLY_READ_TIMING_-
2D
0xDD35 SA MRC_READ_ODT
0xDD36 SA MRC_READ_EQ
0xDD37 SA MRC_READ_AMP_POWER
0xDD38 SA MRC_WRITE_TIMING_2D
0xDD39 SA MRC_READ_TIMING_2D
0xDD3A SA MRC_CMD_VREF
0xDD3B SA MRC_WRITE_VREF_2D
0xDD3C SA MRC_READ_VREF_2D
0xDD3D SA MRC_POST_TRAINING
0xDD3E SA MRC_LATE_COMMAND
0xDD3F SA MRC_ROUND_TRIP_LAT
0xDD40 SA MRC_TURN_AROUND
0xDD41 SA MRC_CMP_OPT
0xDD42 SA MRC_SAVE_MC_VALUES
0xDD43 SA MRC_RESTORE_TRAINING
0xDD44 SA MRC_RMT_TOOL
0xDD45 SA MRC_WRITE_SR
0xDD46 SA MRC_DIMM_RON
0xDD47 SA MRC_RCVEN_TIMING_1D
0xDD48 SA MRC_MR_FILL
0xDD49 SA MRC_PWR_MTR
0xDD4A SA MRC_DDR4_MAPPING
0xDD4B SA MRC_WRITE_VOLTAGE_1D
0xDD4C SA MRC_EARLY_RDMPR_TIMING-
_2D
0xDD4D SA MRC_FORCE_OLTM
0xDD50 SA MRC_MC_ACTIVATE
0xDD51 SA MRC_RH_PREVENTION
0xDD52 SA MRC_GET_MRC_DATA
0xDD53 SA Reserved
0xDD58 SA MRC_RETRAIN_CHECK
0xDD5A SA MRC_SA_GV_SWITCH
0xDD5B SA MRC_ALIAS_CHECK
0xDD5C SA MRC_ECC_CLEAN_START
0xDD5D SA MRC_DONE
0xDD5F SA MRC_CPGC_MEMORY_TEST
0xDD60 SA MRC_TXT_ALIAS_CHECK
0xDD61 SA MRC_ENG_PERF_GAIN
0xDD68 SA MRC_MEMORY_TEST
0xDD69 SA MRC_FILL_RMT_STRUCTURE
0xDD70 SA MRC_SELF_REFRESH_EXIT
0xDD71 SA MRC_NORMAL_MODE
0xDD7D SA MRC_SSA_PRE_STOP_POINT
0xDD7F SA MRC_SSA_STOP_POINT,
MRC_INITIALIZATION_END
23
0xDD90 SA MRC_CMD_PLOT_2D_ERROR
0xDD9B SA MRC_FAST_BOOT_PERMITTE-
D_ERROR
0xDD9C SA MRC_RESTORE_NON_TRAINI-
NG_ERROR
0xDD9D SA MRC_PRINT_INPUT_PARAMS-
_ERROR
0xDD9E SA MRC_SET_OVERRIDES_PSP-
D_ERROR
0xDDA0 SA MRC_SPD_PROCESSING_ER-
ROR
0xDDA1 SA MRC_SET_OVERRIDES_ERR-
OR
0xDDA2 SA MRC_MC_CAPABILITY_ERROR
0xDDA3 SA MRC_MC_CONFIG_ERROR
0xDDA4 SA MRC_MC_MEMORY_MAP_ER-
ROR
0xDDA5 SA MRC_JEDEC_INIT_LPDDR3_E-
RROR
0xDDA6 SA MRC_RESET_ERROR
0xDDA7 SA MRC_PRE_TRAINING_ERROR
0xDDA8 SA MRC_EARLY_COMMAND_ER-
ROR
0xDDA9 SA MRC_SENSE_AMP_OFFSET_-
ERROR
0xDDAA SA MRC_READ_MPR_ERROR
0xDDAB SA MRC_RECEIVE_ENABLE_ERR-
OR
0xDDAC SA MRC_JEDEC_WRITE_LEVELI-
NG_ERROR
0xDDAD SA MRC_LPDDR_LATENCY_SET_-
B_ERROR
0xDDAE SA MRC_WRITE_TIMING_1D_ER-
ROR
0xDDAF SA MRC_READ_TIMING_1D_ERR-
OR
0xDDB0 SA MRC_DIMM_ODT_ERROR
0xDDB1 SA MRC_EARLY_WRITE_TIMING-
_ERROR
0xDDB2 SA MRC_WRITE_DS_ERROR
0xDDB3 SA MRC_WRITE_EQ_ERROR
0xDDB4 SA MRC_EARLY_READ_TIMING_-
ERROR
0xDDB5 SA MRC_READ_ODT_ERROR
0xDDB6 SA MRC_READ_EQ_ERROR
0xDDB7 SA MRC_READ_AMP_POWER_E-
RROR
0xDDB8 SA MRC_WRITE_TIMING_2D_ER-
ROR
0xDDB9 SA MRC_READ_TIMING_2D_ERR-
OR
24 FSP POSTCODE
0xDDBA SA MRC_CMD_VREF_ERROR
0xDDBB SA MRC_WRITE_VREF_2D_ERR-
OR
0xDDBC SA MRC_READ_VREF_2D_ERROR
0xDDBD SA MRC_POST_TRAINING_ERROR
0xDDBE SA MRC_LATE_COMMAND_ERR-
OR
0xDDBF SA MRC_ROUND_TRIP_LAT_ERR-
OR
0xDDC0 SA MRC_TURN_AROUND_ERROR
0xDDC1 SA MRC_CMP_OPT_ERROR
0xDDC2 SA MRC_SAVE_MC_VALUES_ER-
ROR
0xDDC3 SA MRC_RESTORE_TRAINING_E-
RROR
0xDDC4 SA MRC_RMT_TOOL_ERROR
0xDDC5 SA MRC_WRITE_SR_ERROR
0xDDC6 SA MRC_DIMM_RON_ERROR
0xDDC7 SA MRC_RCVEN_TIMING_1D_ER-
ROR
0xDDC8 SA MRC_MR_FILL_ERROR
0xDDC9 SA MRC_PWR_MTR_ERROR
0xDDCA SA MRC_DDR4_MAPPING_ERROR
0xDDCB SA MRC_WRITE_VOLTAGE_1D_E-
RROR
0xDDCC SA MRC_EARLY_RDMPR_TIMING-
_2D_ERROR
0xDDCD SA MRC_FORCE_OLTM_ERROR
0xDDD0 SA MRC_MC_ACTIVATE_ERROR
0xDDD1 SA MRC_RH_PREVENTION_ERR-
OR
0xDDD2 SA MRC_GET_MRC_DATA_ERROR
0xDDD3 SA Reserved
0xDDD8 SA MRC_RETRAIN_CHECK_ERR-
OR
0xDDDA SA MRC_SA_GV_SWITCH_ERROR
0xDDDB SA MRC_ALIAS_CHECK_ERROR
0xDDDC SA MRC_ECC_CLEAN_ERROR
0xDDDD SA MRC_DONE_WITH_ERROR
0xDDDF SA MRC_CPGC_MEMORY_TEST_-
ERROR
0xDDE0 SA MRC_TXT_ALIAS_CHECK_ER-
ROR
0xDDE1 SA MRC_ENG_PERF_GAIN_ERR-
OR
0xDDE8 SA MRC_MEMORY_TEST_ERROR
0xDDE9 SA MRC_FILL_RMT_STRUCTURE-
_ERROR
0xDDF0 SA MRC_SELF_REFRESH_EXIT_-
ERROR
25
0xDDF1 SA MRC_MRC_NORMAL_MODE_-
ERROR
0xDDFD SA MRC_SSA_PRE_STOP_POINT-
_ERROR
0xDDFE SA MRC_NO_MEMORY_DETECT-
ED
7.1.3 TempRamExit API Status Codes (0xBxxx)
PostCode Module Description
0xB800 FSP TempRamExit API Entry
0xB87F FSP TempRamExit API Exit
7.1.4 FspSiliconInit API Status Codes (0x9xxx)
PostCode Module Description
0x9800 FSP FspSiliconInit API Entry
0x987F FSP FspSiliconInit API Exit
0x9A00 SA PostMem SaInit Entry
0x9A01 SA DeviceConfigure Start
0x9A02 SA UpdateSaHobPostMem Start
0x9A03 SA Initializing Pei Display
0x9A04 SA PeiGraphicsNotifyCallback Entry
0x9A05 SA CallPpiAndFillFrameBuffer
0x9A06 SA GraphicsPpiInit
0x9A07 SA GraphicsPpiGetMode
0x9A08 SA FillFrameBufferAndShowLogo
0x9A0F SA PeiGraphicsNotifyCallback Exit
0x9A14 SA Initializing SA IPU device
0x9A16 SA Initializing SA GNA device
0x9A1A SA SaProgramLlcWays Start
0x9A20 SA Initializing PciExpressInitPostMem
0x9A22 SA Initializing
ConfigureNorthIntelTraceHub
0x9A30 SA Initializing Vtd
0x9A31 SA Initializing TCSS
0x9A32 SA Initializing Pavp
0x9A34 SA PeiInstallSmmAccessPpi Start
0x9A36 SA EdramWa Start
0x9A4F SA Post-Mem SaInit Exit
0x9A50 SA SaSecurityLock Start
0x9A5F SA SaSecurityLock End
0x9A60 SA SaSResetComplete Entry
0x9A61 SA Set BIOS_RESET_CPL to indicate
all configurations complete
0x9A62 SA SaSvInit2 Start
0x9A63 SA GraphicsPmInit Start
0x9A64 SA SaPciPrint Start
26 FSP POSTCODE
0x9A6F SA SaSResetComplete Exit
0x9A70 SA SaS3ResumeAtEndOfPei Callback
Entry
0x9A7F SA SaS3ResumeAtEndOfPei Callback
Exit
0x9B00 PCH Post-Mem PchInit Entry
0x9B03 PCH Post-Mem Tune the USB 2.0
high-speed signals quality
0x9B04 PCH Post-Mem Tune the USB 3.0
signals quality
0x9B05 PCH Post-Mem Configure PCH xHCI
0x9B06 PCH Post-Mem Performs configuration
of PCH xHCI SSIC
0x9B07 PCH Post-Mem Configure PCH xHCI
after init
0x9B08 PCH Post-Mem Configures PCH USB
device (xDCI)
0x9B0A PCH Post-Mem DMI/OP-DMI
configuration
0x9B0B PCH Post-Mem Initialize P2SB
controller
0x9B0C PCH Post-Mem IOAPIC initialization
0x9B0D PCH Post-Mem PCH devices interrupt
configuration
0x9B0E PCH Post-Mem HD Audio initizalization
0x9B0F PCH Post-Mem HD Audio Codec
enumeration
0x9B10 PCH Post-Mem HD Audio Codec not
detected
0x9B13 PCH Post-Mem SCS initizalization
0x9B14 PCH Post-Mem ISH initizalization
0x9B15 PCH Post-Mem Configure SMBUS
power management
0x9B16 PCH Post-Mem Reserved
0x9B17 PCH Post-Mem Performing global reset
0x9B18 PCH Post-Mem Reserved
0x9B19 PCH Post-Mem Reserved
0x9B40 PCH Post-Mem OnEndOfPEI Entry
0x9B41 PCH Post-Mem Initialize Thermal
controller
0x9B42 PCH Post-Mem Configure Memory
Throttling
0x9B47 PCH Post-Mem OnEndOfPEI Exit
0x9B4D PCH Post-Mem Trace Hub - Memory
configuration
0x9B4E PCH Post-Mem Trace Hub - MSC0
configured
0x9B4F PCH Post-Mem Trace Hub - MSC1
configured
0x9B7F PCH Post-Mem PchInit Exit
0x9C00 CPU CPU Post-Mem Entry
27
0x9C09 CPU CpuAddConfigBlocks Done
0x9C0A CPU SetCpuStrapAndEarlyPowerOn-
Config
Start
0x9C13 CPU SetCpuStrapAndEarlyPowerOn-
Config
Reset
0x9C14 CPU SetCpuStrapAndEarlyPowerOn-
Config
Done
0x9C15 CPU CpuInit Start
0x9C16 CPU SgxInitializationPrePatchLoad
Start
0x9C17 CPU CollectProcessorFeature Start
0x9C18 CPU ProgramProcessorFeature Start
0x9C19 CPU ProgramProcessorFeature Done
0x9C20 CPU CpuInitPreResetCpl Start
0x9C21 CPU ProcessorsPrefetcherInitialization
Start
0x9C22 CPU InitRatl Start
0x9C23 CPU ConfigureSvidVrs Start
0x9C24 CPU ConfigurePidSettings Start
0x9C25 CPU SetBootFrequency Start
0x9C26 CPU CpuOcInitPreMem Start
0x9C27 CPU CpuOcInit Reset
0x9C28 CPU BiosGuardInit Start
0x9C29 CPU BiosGuardInit Reset
0x9C3F CPU CpuInitPreResetCpl Done
0x9C42 CPU SgxActivation Start
0x9C43 CPU InitializeCpuDataHob Start
0x9C44 CPU InitializeCpuDataHob Done
0x9C4F CPU CpuInit Done
0x9C50 CPU S3InitializeCpu Start
0x9C55 CPU MpRendezvousProcedure Start
0x9C56 CPU MpRendezvousProcedure Done
0x9C69 CPU S3InitializeCpu Done
0x9C6A CPU CpuPowerMgmtInit Start
0x9C71 CPU InitPpm
0x9C7F CPU CPU Post-Mem Exit
0x9C80 CPU ReloadMicrocodePatch Start
0x9C81 CPU ReloadMicrocodePatch Done
0x9C82 CPU ApSafePostMicrocodePatchInit
Start
0x9C83 CPU ApSafePostMicrocodePatchInit
Done
7.1.5 NotifyPhase API Status Codes (0x6xxx)
PostCode Module Description
0x6800 FSP NotifyPhase API Entry
0x687F FSP NotifyPhase API Exit
28 FSP POSTCODE
Chapter 8
Todo List
Page FSP INTEGRATION
program 0x1000000000 - Top of High Memory |Write back
30 Todo List
Chapter 9
Deprecated List
Member FSP_S_CONFIG::SkipMpInitDeprecated
SkipMpInit has been moved to FspmUpd $EN_DIS
Member FSP_S_TEST_CONFIG::DebugInterfaceEnable
Enable or Disable processor debug features; 0: Disable; 1: Enable. $EN_DIS
32 Deprecated List
Chapter 10
Class Index
10.1 Class List
Here are the classes, structs, unions and interfaces with brief descriptions:
AUDIO_AZALIA_VERB_TABLE
Audio Azalia Verb Table structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
AZALIA_HEADER
Azalia Header structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CHIPSET_INIT_INFO
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIO-
S ChipsetInit CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DIMM_INFO
Memory SMBIOS & OC Memory Data Hob . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FIRMWARE_VERSION
Firmware Version Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FIRMWARE_VERSION_INFO
Firmware Version Information Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FIRMWARE_VERSION_INFO_HOB
Firmware Version Information HOB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FSP_M_CONFIG
Fsp M Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FSP_M_TEST_CONFIG
Fsp M Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
FSP_S_CONFIG
Fsp S Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
FSP_S_TEST_CONFIG
Fsp S Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
FSP_T_CONFIG
Fsp T Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
FSPM_UPD
Fsp M UPD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
FSPS_UPD
Fsp S UPD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
FSPT_CORE_UPD
Fsp T Core UPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
FSPT_UPD
Fsp T UPD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
GPIO_CONFIG
GPIO configuration structure used for pin programming . . . . . . . . . . . . . . . . . . . . . 174
HOB_USAGE_DATA_HOB
Hob Usage Data Hob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
34 Class Index
MEMORY_PLATFORM_DATA
Memory Platform Data Hob . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SI_PCH_DEVICE_INTERRUPT_CONFIG
The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt
mode for PCH device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
SMBIOS_CACHE_INFO
SMBIOS Cache Info HOB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
SMBIOS_PROCESSOR_INFO
SMBIOS Processor Info HOB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
SMBIOS_STRUCTURE
The Smbios structure header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Chapter 11
File Index
11.1 File List
Here is a list of all documented files with brief descriptions:
FirmwareVersionInfoHob.h
Header file for Firmware Version Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
FspFixedPcds.h
This file lists all FixedAtBuild PCDs referenced in FSP integration guide . . . . . . . . . . . . 182
FspInfoHob.h
Header file for FSP Information HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
FspmUpd.h
Copyright (c) 2019, Intel Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
FspsUpd.h
Copyright (c) 2019, Intel Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
FsptUpd.h
Copyright (c) 2019, Intel Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
FspUpd.h
Copyright (c) 2019, Intel Corporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
GpioConfig.h
Header file for GpioConfig structure used by GPIO library . . . . . . . . . . . . . . . . . . . . 188
GpioSampleDef.h
Sample enum definitions for GPIO table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
HobUsageDataHob.h
Definitions for Hob Usage data HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
MemInfoHob.h
This file contains definitions required for creation of Memory S3 Save data, Memory Info data
and Memory Platform data hobs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
SmbiosCacheInfoHob.h
Header file for SMBIOS Cache Info HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
SmbiosProcessorInfoHob.h
Header file for SMBIOS Processor Info HOB . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
36 File Index
Chapter 12
Class Documentation
12.1 AUDIO_AZALIA_VERB_TABLE Struct Reference
Audio Azalia Verb Table structure.
#include <FspsUpd.h>
Collaboration diagram for AUDIO_AZALIA_VERB_TABLE:
AUDIO_AZALIA_VERB_TABLE
AZALIA_HEADER
Header
Public Attributes
AZALIA_HEADER Header
AZALIA PCH header.
UINT32 Data
Pointer to the data buffer. Its length is specified in the header.
12.1.1 Detailed Description
Audio Azalia Verb Table structure.
Definition at line 34 of file FspsUpd.h.
The documentation for this struct was generated from the following file:
FspsUpd.h
38 Class Documentation
12.2 AZALIA_HEADER Struct Reference
Azalia Header structure.
#include <FspsUpd.h>
Public Attributes
UINT16 VendorId
Codec Vendor ID.
UINT16 DeviceId
Codec Device ID.
UINT8 RevisionId
Revision ID of the codec. 0xFF matches any revision.
UINT8 SdiNum
SDI number, 0xFF matches any SDI.
UINT16 DataDwords
Number of data DWORDs pointed by the codec data buffer.
UINT32 Reserved
Reserved for future use. Must be set to 0.
12.2.1 Detailed Description
Azalia Header structure.
Definition at line 22 of file FspsUpd.h.
The documentation for this struct was generated from the following file:
FspsUpd.h
12.3 CHIPSET_INIT_INFO Struct Reference
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
#include <FspmUpd.h>
Public Attributes
UINT8 Revision
Chipset Init Info Revision.
UINT8 Rsvd [3]
Reserved.
UINT16 MeChipInitCrc
16 bit CRC value of MeChipInit Table
UINT16 BiosChipInitCrc
16 bit CRC value of PchChipInit Table
12.4 DIMM_INFO Struct Reference 39
12.3.1 Detailed Description
The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
Definition at line 24 of file FspmUpd.h.
The documentation for this struct was generated from the following file:
FspmUpd.h
12.4 DIMM_INFO Struct Reference
Memory SMBIOS & OC Memory Data Hob.
#include <MemInfoHob.h>
Public Attributes
UINT8 Status
See MrcDimmStatus for the definition of this field.
UINT32 DimmCapacity
DIMM size in MBytes.
UINT8 ModulePartNum [20]
Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes.
UINT8 RankInDimm
The number of ranks in this DIMM.
UINT8 SpdDramDeviceType
Save SPD DramDeviceType information needed for SMBIOS structure creation.
UINT8 SpdModuleType
Save SPD ModuleType information needed for SMBIOS structure creation.
UINT8 SpdModuleMemoryBusWidth
Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
UINT8 SpdSave [MAX_SPD_SAVE]
Save SPD Manufacturing information needed for SMBIOS structure creation.
UINT16 Speed
The maximum capable speed of the device, in MHz.
12.4.1 Detailed Description
Memory SMBIOS & OC Memory Data Hob.
Definition at line 170 of file MemInfoHob.h.
The documentation for this struct was generated from the following file:
MemInfoHob.h
12.5 FIRMWARE_VERSION Struct Reference
Firmware Version Structure.
#include <FirmwareVersionInfoHob.h>
40 Class Documentation
12.5.1 Detailed Description
Firmware Version Structure.
Definition at line 22 of file FirmwareVersionInfoHob.h.
The documentation for this struct was generated from the following file:
FirmwareVersionInfoHob.h
12.6 FIRMWARE_VERSION_INFO Struct Reference
Firmware Version Information Structure.
#include <FirmwareVersionInfoHob.h>
Collaboration diagram for FIRMWARE_VERSION_INFO:
FIRMWARE_VERSION_INFO
FIRMWARE_VERSION
Version
Public Attributes
UINT8 ComponentNameIndex
Offset 0 Index of Component Name.
UINT8 VersionStringIndex
Offset 1 Index of Version String.
FIRMWARE_VERSION Version
Offset 2-6 Firmware version.
12.6.1 Detailed Description
Firmware Version Information Structure.
Definition at line 32 of file FirmwareVersionInfoHob.h.
The documentation for this struct was generated from the following file:
FirmwareVersionInfoHob.h
12.7 FIRMWARE_VERSION_INFO_HOB Struct Reference
Firmware Version Information HOB Structure.
12.8 FSP_M_CONFIG Struct Reference 41
#include <FirmwareVersionInfoHob.h>
Collaboration diagram for FIRMWARE_VERSION_INFO_HOB:
FIRMWARE_VERSION_INFO_HOB
SMBIOS_STRUCTURE
SmbiosData
Public Attributes
EFI_HOB_GUID_TYPE Header
Offset 0-23 The header of FVI HOB.
SMBIOS_STRUCTURE SmbiosData
Offset 24-27 The SMBIOS header of FVI HOB.
UINT8 Count
Offset 28 Number of FVI elements included.
12.7.1 Detailed Description
Firmware Version Information HOB Structure.
Definition at line 52 of file FirmwareVersionInfoHob.h.
12.7.2 Member Data Documentation
12.7.2.1 UINT8 FIRMWARE_VERSION_INFO_HOB::Count
Offset 28 Number of FVI elements included.
Definition at line 55 of file FirmwareVersionInfoHob.h.
The documentation for this struct was generated from the following file:
FirmwareVersionInfoHob.h
12.8 FSP_M_CONFIG Struct Reference
Fsp M Configuration.
#include <FspmUpd.h>
42 Class Documentation
Public Attributes
UINT64 PlatformMemorySize
Offset 0x0040 - Platform Reserved Memory Size The minimum platform memory size required to pass control into
DXE.
UINT32 MemorySpdPtr00
Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0 Pointer to SPD data, will be used only when SpdAddress-
Table SPD Address are marked as 00.
UINT32 MemorySpdPtr01
Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1 Pointer to SPD data, will be used only when SpdAddress-
Table SPD Address are marked as 00.
UINT32 MemorySpdPtr10
Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0 Pointer to SPD data, will be used only when SpdAddress-
Table SPD Address are marked as 00.
UINT32 MemorySpdPtr11
Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1 Pointer to SPD data, will be used only when SpdAddress-
Table SPD Address are marked as 00.
UINT16 MemorySpdDataLen
Offset 0x0058 - SPD Data Length Length of SPD Data 0x100:256 Bytes, 0x200:512 Bytes.
UINT8 DqByteMapCh0 [12]
Offset 0x005A - Dq Byte Map CH0 Dq byte mapping between CPU and DRAM, Channel 0: board-dependent.
UINT8 DqByteMapCh1 [12]
Offset 0x0066 - Dq Byte Map CH1 Dq byte mapping between CPU and DRAM, Channel 1: board-dependent.
UINT8 DqsMapCpu2DramCh0 [8]
Offset 0x0072 - Dqs Map CPU to DRAM CH 0 Set Dqs mapping relationship between CPU and DRAM, Channel 0:
board-dependent.
UINT8 DqsMapCpu2DramCh1 [8]
Offset 0x007A - Dqs Map CPU to DRAM CH 1 Set Dqs mapping relationship between CPU and DRAM, Channel 1:
board-dependent.
UINT16 RcompResistor [3]
Offset 0x0082 - RcompResister settings Indicates RcompReister settings: CNL - 0's means MRC auto configured
based on Design Guidelines, otherwise input an Ohmic value per segment.
UINT16 RcompTarget [5]
Offset 0x0088 - RcompTarget settings RcompTarget settings: CNL - 0's mean MRC auto configured based on Design
Guidelines, otherwise input an Ohmic value per segment.
UINT8 DqPinsInterleaved
Offset 0x0092 - Dqs Pins Interleaved Setting Indicates DqPinsInterleaved setting: board-dependent $EN_DIS.
UINT8 CaVrefConfig
Offset 0x0093 - VREF_CA CA Vref routing: board-dependent 0:VREF_CA goes to both CH_A and CH_B, 1: VRE-
F_CA to CH_A and VREF_DQ_A to CH_B, 2:VREF_CA to CH_A and VREF_DQ_B to CH_B.
UINT8 SmramMask
Offset 0x0094 - Smram Mask The SMM Regions AB-SEG and/or H-SEG reserved 0: Neither, 1:AB-SEG, 2:H-SEG,
3: Both.
UINT8 MrcFastBoot
Offset 0x0095 - MRC Fast Boot Enables/Disable the MRC fast path thru the MRC $EN_DIS.
UINT8 RmtPerTask
Offset 0x0096 - Rank Margin Tool per Task This option enables the user to execute Rank Margin Tool per major
training step in the MRC.
UINT8 TrainTrace
Offset 0x0097 - Training Trace This option enables the trained state tracing feature in MRC.
UINT32 IedSize
Offset 0x0098 - Intel Enhanced Debug Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB S-
MRAM occupied 0 : Disable, 0x400000 : Enable.
UINT32 TsegSize
12.8 FSP_M_CONFIG Struct Reference 43
Offset 0x009C - Tseg Size Size of SMRAM memory reserved.
UINT16 MmioSize
Offset 0x00A0 - MMIO Size Size of MMIO space reserved for devices.
UINT8 ProbelessTrace
Offset 0x00A2 - Probeless Trace Probeless Trace: 0=Disabled, 1=Enable.
UINT8 GdxcIotSize
Offset 0x00A3 - GDXC IOT SIZE Size of IOT and MOT is in 8 MB chunks.
UINT8 GdxcMotSize
Offset 0x00A4 - GDXC MOT SIZE Size of IOT and MOT is in 8 MB chunks.
UINT8 SmbusEnable
Offset 0x00A5 - Enable SMBus Enable/disable SMBus controller.
UINT8 SpdAddressTable [4]
Offset 0x00A6 - Spd Address Tabl Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1.
UINT8 PlatformDebugConsent
Offset 0x00AA - Platform Debug Consent To 'opt-in' for debug, please select 'Enabled' with the desired debug probe
type.
UINT8 DciUsb3TypecUfpDbg
Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support This BIOS option enables kernel and plat-
form debug for USB3 interface over a UFP Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
UINT8 PchTraceHubMode
Offset 0x00AC - PCH Trace Hub Mode Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target
Debugger' if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
UINT8 PchTraceHubMemReg0Size
Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size Specify size of Pch trace memory region 0 buffer, the
size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.
UINT8 PchTraceHubMemReg1Size
Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size Specify size of Pch trace memory region 1 buffer, the
size can be 0, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.
UINT8 PchPreMemRsvd [9]
Offset 0x00AF - PchPreMemRsvd Reserved for PCH Pre-Mem Reserved $EN_DIS.
UINT8 IgdDvmt50PreAlloc
Offset 0x00B8 - Internal Graphics Pre-allocated Memory Size of memory preallocated for internal graphics.
UINT8 InternalGfx
Offset 0x00B9 - Internal Graphics Enable/disable internal graphics.
UINT8 ApertureSize
Offset 0x00BA - Aperture Size Select the Aperture Size.
UINT8 UserBd
Offset 0x00BB - Board Type MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/-
Mobile Halo, 7=UP Server 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server.
UINT8 SaGv
Offset 0x00BC - SA GV System Agent dynamic frequency support and when enabled memory will be training at two
different frequencies.
UINT8 UnusedUpdSpace0
Offset 0x00BD.
UINT16 DdrFreqLimit
Offset 0x00BE - DDR Frequency Limit Maximum Memory Frequency Selections in Mhz.
UINT16 FreqSaGvLow
Offset 0x00C0 - Low Frequency SAGV Low Frequency Selections in Mhz.
UINT16 FreqSaGvMid
Offset 0x00C2 - Mid Frequency SAGV Mid Frequency Selections in Mhz.
UINT8 RMT
Offset 0x00C4 - Rank Margin Tool Enable/disable Rank Margin Tool.
44 Class Documentation
UINT8 DisableDimmChannel0
Offset 0x00C5 - Channel A DIMM Control Channel A DIMM Control Support - Enable or Disable Dimms on Channel
A.
UINT8 DisableDimmChannel1
Offset 0x00C6 - Channel B DIMM Control Channel B DIMM Control Support - Enable or Disable Dimms on Channel
B.
UINT8 ScramblerSupport
Offset 0x00C7 - Scrambler Support This option enables data scrambling in memory.
UINT8 SkipMpInit
Offset 0x00C8 - Skip Multi-Processor Initialization When this is skipped, boot loader must initialize processors before
SilicionInit API.
UINT8 UnusedUpdSpace1 [15]
Offset 0x00C9.
UINT8 SpdProfileSelected
Offset 0x00D8 - SPD Profile Selected Select DIMM timing profile.
UINT8 RefClk
Offset 0x00D9 - Memory Reference Clock 100MHz, 133MHz.
UINT16 VddVoltage
Offset 0x00DA - Memory Voltage Memory Voltage Override (Vddq).
UINT8 Ratio
Offset 0x00DC - Memory Ratio Automatic or the frequency will equal ratio times reference clock.
UINT8 OddRatioMode
Offset 0x00DD - QCLK Odd Ratio Adds 133 or 100 MHz to QCLK frequency, depending on RefClk $EN_DIS.
UINT8 tCL
Offset 0x00DE - tCL CAS Latency, 0: AUTO, max: 31.
UINT8 tCWL
Offset 0x00DF - tCWL Min CAS Write Latency Delay Time, 0: AUTO, max: 34.
UINT8 tRCDtRP
Offset 0x00E0 - tRCD/tRP RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63.
UINT8 tRRD
Offset 0x00E1 - tRRD Min Row Active to Row Active Delay Time, 0: AUTO, max: 15.
UINT16 tFAW
Offset 0x00E2 - tFAW Min Four Activate Window Delay Time, 0: AUTO, max: 63.
UINT16 tRAS
Offset 0x00E4 - tRAS RAS Active Time, 0: AUTO, max: 64.
UINT16 tREFI
Offset 0x00E6 - tREFI Refresh Interval, 0: AUTO, max: 65535.
UINT16 tRFC
Offset 0x00E8 - tRFC Min Refresh Recovery Delay Time, 0: AUTO, max: 1023.
UINT8 tRTP
Offset 0x00EA - tRTP Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15.
UINT8 tWR
Offset 0x00EB - tWR Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24, 30, 34,
40 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, 34:34, 40:40.
UINT8 tWTR
Offset 0x00EC - tWTR Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28.
UINT8 NModeSupport
Offset 0x00ED - NMode System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N.
UINT8 DllBwEn0
Offset 0x00EE - DllBwEn[0] DllBwEn[0], for 1067 (0..7)
UINT8 DllBwEn1
12.8 FSP_M_CONFIG Struct Reference 45
Offset 0x00EF - DllBwEn[1] DllBwEn[1], for 1333 (0..7)
UINT8 DllBwEn2
Offset 0x00F0 - DllBwEn[2] DllBwEn[2], for 1600 (0..7)
UINT8 DllBwEn3
Offset 0x00F1 - DllBwEn[3] DllBwEn[3], for 1867 and up (0..7)
UINT8 IsvtIoPort
Offset 0x00F2 - ISVT IO Port Address ISVT IO Port Address.
UINT8 CpuTraceHubMode
Offset 0x00F3 - CPU Trace Hub Mode Select 'Target Debugger' if Trace Hub is used by target debugger software or
'Disable' trace hub functionality.
UINT8 CpuTraceHubMemReg0Size
Offset 0x00F4 - CPU Trace Hub Memory Region 0 CPU Trace Hub Memory Region 0, The avaliable memory size is
: 0MB, 1MB, 8MB, 64MB, 128MB, 256MB, 512MB.
UINT8 CpuTraceHubMemReg1Size
Offset 0x00F5 - CPU Trace Hub Memory Region 1 CPU Trace Hub Memory Region 1.
UINT8 PeciC10Reset
Offset 0x00F6 - Enable or Disable Peci C10 Reset command Enable or Disable Peci C10 Reset command.
UINT8 PeciSxReset
Offset 0x00F7 - Enable or Disable Peci Sx Reset command Enable or Disable Peci Sx Reset command; 0: Disable;
1: Enable.
UINT8 UnusedUpdSpace2 [4]
Offset 0x00F8.
UINT8 PchHdaEnable
Offset 0x00FC - Enable Intel HD Audio (Azalia) 0: Disable, 1: Enable (Default) Azalia controller $EN_DIS.
UINT8 PchIshEnable
Offset 0x00FD - Enable PCH ISH Controller 0: Disable, 1: Enable (Default) ISH Controller $EN_DIS.
UINT8 HeciTimeouts
Offset 0x00FE - HECI Timeouts 0: Disable, 1: Enable (Default) timeout check for HECI $EN_DIS.
UINT8 UnusedUpdSpace3
Offset 0x00FF.
UINT32 Heci1BarAddress
Offset 0x0100 - HECI1 BAR address BAR address of HECI1.
UINT32 Heci2BarAddress
Offset 0x0104 - HECI2 BAR address BAR address of HECI2.
UINT32 Heci3BarAddress
Offset 0x0108 - HECI3 BAR address BAR address of HECI3.
UINT16 SgDelayAfterPwrEn
Offset 0x010C - SG dGPU Power Delay SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum,
default is 300=300 microseconds.
UINT16 SgDelayAfterHoldReset
Offset 0x010E - SG dGPU Reset Delay SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum,
default is 100=100 microseconds.
UINT16 MmioSizeAdjustment
Offset 0x0110 - MMIO size adjustment for AUTO mode Positive number means increasing MMIO size, Negative value
means decreasing MMIO size: 0 (Default)=no change to AUTO mode MMIO size.
UINT8 DmiGen3ProgramStaticEq
Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming Program DMI Gen3 EQ Phase1 Static
Presets.
UINT8 Peg0Enable
Offset 0x0113 - Enable/Disable PEG 0 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon
SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable,
1:Enable, 2:AUTO.
UINT8 Peg1Enable
46 Class Documentation
Offset 0x0114 - Enable/Disable PEG 1 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon
SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable,
1:Enable, 2:AUTO.
UINT8 Peg2Enable
Offset 0x0115 - Enable/Disable PEG 2 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon
SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable,
1:Enable, 2:AUTO.
UINT8 Peg3Enable
Offset 0x0116 - Enable/Disable PEG 3 Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon
SKU permits it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise 0:Disable,
1:Enable, 2:AUTO.
UINT8 Peg0MaxLinkSpeed
Offset 0x0117 - PEG 0 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to
Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2,
3:Gen3.
UINT8 Peg1MaxLinkSpeed
Offset 0x0118 - PEG 1 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to
Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2,
3:Gen3.
UINT8 Peg2MaxLinkSpeed
Offset 0x0119 - PEG 2 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to
Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2,
3:Gen3.
UINT8 Peg3MaxLinkSpeed
Offset 0x011A - PEG 3 Max Link Speed Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to
Gen1 Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed 0:Auto, 1:Gen1, 2:Gen2,
3:Gen3.
UINT8 Peg0MaxLinkWidth
Offset 0x011B - PEG 0 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1,
(0x2): Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8.
UINT8 Peg1MaxLinkWidth
Offset 0x011C - PEG 1 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1,
(0x2): Limit Link to x2, (0x3):Limit Link to x4 0:Auto, 1:x1, 2:x2, 3:x4.
UINT8 Peg2MaxLinkWidth
Offset 0x011D - PEG 2 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1,
(0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
UINT8 Peg3MaxLinkWidth
Offset 0x011E - PEG 3 Max Link Width Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1,
(0x2): Limit Link to x2 0:Auto, 1:x1, 2:x2.
UINT8 Peg0PowerDownUnusedLanes
Offset 0x011F - Power down unused lanes on PEG 0 (0x0): Do not power down any lane, (0x1): Bios will power down
unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 Peg1PowerDownUnusedLanes
Offset 0x0120 - Power down unused lanes on PEG 1 (0x0): Do not power down any lane, (0x1): Bios will power down
unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 Peg2PowerDownUnusedLanes
Offset 0x0121 - Power down unused lanes on PEG 2 (0x0): Do not power down any lane, (0x1): Bios will power down
unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 Peg3PowerDownUnusedLanes
Offset 0x0122 - Power down unused lanes on PEG 3 (0x0): Do not power down any lane, (0x1): Bios will power down
unused lanes based on the max possible link width 0:No power saving, 1:Auto.
UINT8 InitPcieAspmAfterOprom
Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom Select when PCIe ASPM programming
will happen in relation to the Oprom.
UINT8 PegDisableSpreadSpectrumClocking
12.8 FSP_M_CONFIG Struct Reference 47
Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking.
UINT8 UnusedUpdSpace4 [3]
Offset 0x0125.
UINT8 DmiGen3RootPortPreset [8]
Offset 0x0128 - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane.
UINT8 DmiGen3EndPointPreset [8]
Offset 0x0130 - DMI Gen3 End port preset values per lane Used for programming DMI Gen3 preset values per lane.
UINT8 DmiGen3EndPointHint [8]
Offset 0x0138 - DMI Gen3 End port Hint values per lane Used for programming DMI Gen3 Hint values per lane.
UINT8 DmiGen3RxCtlePeaking [4]
Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control Range: 0-15, 0 is default for each bundle, must be specified
based upon platform design.
UINT8 TvbRatioClipping
Offset 0x0144 - Thermal Velocity Boost Ratio clipping 0(Default): Disabled, 1: Enabled.
UINT8 TvbVoltageOptimization
Offset 0x0145 - Thermal Velocity Boost voltage optimization 0: Disabled, 1: Enabled(Default).
UINT8 UnusedUpdSpace5 [2]
Offset 0x0146.
UINT8 PegGen3RxCtlePeaking [10]
Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control Range: 0-15, 12 is default for each bundle, must be specified
based upon platform design.
UINT32 PegDataPtr
Offset 0x0152 - Memory data pointer for saved preset search results The reference code will store the Gen3 Preset
Search results in the SaDataHob's PegData structure (SA_PEG_DATA) and platform code can save/restore this data
to skip preset search in the following boots.
UINT8 PegGpioData [28]
Offset 0x0156 - PEG PERST# GPIO information The reference code will use the information in this structure in order
to reset PCIe Gen3 devices during equalization, if necessary.
UINT8 PegRootPortHPE [4]
Offset 0x0172 - PCIe Hot Plug Enable/Disable per port 0(Default): Disable, 1: Enable.
UINT8 DmiDeEmphasis
Offset 0x0176 - DeEmphasis control for DMI DeEmphasis control for DMI.
UINT8 PrimaryDisplay
Offset 0x0177 - Selection of the primary display device 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO,
4=Switchable Graphics 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics.
UINT16 GttSize
Offset 0x0178 - Selection of iGFX GTT Memory size 1=2MB, 2=4MB, 3=8MB, Default is 3 1:2MB, 2:4MB, 3:8MB.
UINT32 GmAdr
Offset 0x017A - Temporary MMIO address for GMADR The reference code will use this as Temporary MMIO address
space to access GMADR Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to (GmAdr
+ ApertureSize).
UINT32 GttMmAdr
Offset 0x017E - Temporary MMIO address for GTTMMADR The reference code will use this as Temporary MM-
IO address space to access GTTMMADR Registers.Platform should provide conflict free Temporary MMIO Range:
GttMmAdr to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize).
UINT8 PsmiRegionSize
Offset 0x0182 - Selection of PSMI Region size 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB.
UINT8 SaRtd3Pcie0Gpio [24]
Offset 0x0183 - Switchable Graphics GPIO information for PEG 0 Switchable Graphics GPIO information for PEG 0,
for Reset, power and wake GPIOs.
UINT8 SaRtd3Pcie1Gpio [24]
48 Class Documentation
Offset 0x019B - Switchable Graphics GPIO information for PEG 1 Switchable Graphics GPIO information for PEG 1,
for Reset, power and wake GPIOs.
UINT8 SaRtd3Pcie2Gpio [24]
Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2 Switchable Graphics GPIO information for PEG 2,
for Reset, power and wake GPIOs.
UINT8 SaRtd3Pcie3Gpio [24]
Offset 0x01CB - Switchable Graphics GPIO information for PEG 3 Switchable Graphics GPIO information for PEG 3,
for Reset, power and wake GPIOs.
UINT8 TxtImplemented
Offset 0x01E3 - Enable/Disable MRC TXT dependency When enabled MRC execution will wait for TXT initialization
to be done first.
UINT8 SaOcSupport
Offset 0x01E4 - Enable/Disable SA OcSupport Enable: Enable SA OcSupport, Disable(Default): Disable SA Oc-
Support $EN_DIS.
UINT8 GtVoltageMode
Offset 0x01E5 - GT slice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT8 GtMaxOcRatio
Offset 0x01E6 - Maximum GTs turbo ratio override 0(Default)=Minimal/Auto, 60=Maximum.
UINT16 GtVoltageOffset
Offset 0x01E7 - The voltage offset applied to GT slice 0(Default)=Minimal, 1000=Maximum.
UINT16 GtVoltageOverride
Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies 0(De-
fault)=Minimal, 2000=Maximum.
UINT16 GtExtraTurboVoltage
Offset 0x01EB - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT16 SaVoltageOffset
Offset 0x01ED - voltage offset applied to the SA 0(Default)=Minimal, 1000=Maximum.
UINT8 RootPortIndex
Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU Root port Index number to indicate
which PCIe root port has dGPU.
UINT8 RealtimeMemoryTiming
Offset 0x01F0 - Realtime Memory Timing 0(Default): Disabled, 1: Enabled.
UINT8 SaIpuEnable
Offset 0x01F1 - Enable/Disable SA IPU Enable(Default): Enable SA IPU, Disable: Disable SA IPU $EN_DIS.
UINT8 SaIpuImrConfiguration
Offset 0x01F2 - IPU IMR Configuration 0:IPU Camera, 1:IPU Gen Default is 0 0:IPU Camera, 1:IPU Gen.
UINT8 GtPsmiSupport
Offset 0x01F3 - Selection of PSMI Support On/Off 0(Default) = FALSE, 1 = TRUE.
UINT8 GtusVoltageMode
Offset 0x01F4 - GT unslice Voltage Mode 0(Default): Adaptive, 1: Override 0: Adaptive, 1: Override.
UINT16 GtusVoltageOffset
Offset 0x01F5 - voltage offset applied to GT unslice 0(Default)=Minimal, 2000=Maximum.
UINT16 GtusVoltageOverride
Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies 0(Default)=Minimal,
2000=Maximum.
UINT16 GtusExtraTurboVoltage
Offset 0x01F9 - adaptive voltage applied during turbo frequencies 0(Default)=Minimal, 2000=Maximum.
UINT8 GtusMaxOcRatio
Offset 0x01FB - Maximum GTus turbo ratio override 0(Default)=Minimal, 60=Maximum.
UINT8 SaPreMemProductionRsvd [4]
Offset 0x01FC - SaPreMemProductionRsvd Reserved for SA Pre-Mem Production $EN_DIS.
UINT8 BistOnReset
12.8 FSP_M_CONFIG Struct Reference 49
Offset 0x0200 - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
UINT8 SkipStopPbet
Offset 0x0201 - Skip Stop PBET Timer Enable/Disable Skip Stop PBET Timer; 0: Disable; 1: Enable $EN_DIS.
UINT8 EnableC6Dram
Offset 0x0202 - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR
memory for C6DRAM power gating feature.
UINT8 OcSupport
Offset 0x0203 - Over clocking support Over clocking support; 0: Disable; 1: Enable $EN_DIS.
UINT8 OcLock
Offset 0x0204 - Over clocking Lock Over clocking Lock Enable/Disable; 0: Disable; 1: Enable.
UINT8 CoreMaxOcRatio
Offset 0x0205 - Maximum Core Turbo Ratio Override Maximum core turbo ratio override allows to increase CPU core
frequency beyond the fused max turbo ratio limit.
UINT8 CoreVoltageMode
Offset 0x0206 - Core voltage mode Core voltage mode; 0: Adaptive; 1: Override.
UINT8 DisableMtrrProgram
Offset 0x0207 - Program Cache Attributes Program Cache Attributes; 0: Program; 1: Disable Program.
UINT8 RingMaxOcRatio
Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr fre-
quency beyond the fused max turbo ratio limit.
UINT8 HyperThreading
Offset 0x0209 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_-
DIS.
UINT8 CpuRatio
Offset 0x020A - CPU ratio value CPU ratio value.
UINT8 BootFrequency
Offset 0x020B - Boot frequency Sets the boot frequency starting from reset vector.
UINT8 ActiveCoreCount
Offset 0x020C - Number of active cores Number of active cores(Depends on Number of cores).
UINT8 FClkFrequency
Offset 0x020D - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX).
UINT8 JtagC10PowerGateDisable
Offset 0x020E - Set JTAG power in C10 and deeper power states False: JTAG is power gated in C10 state.
UINT8 VmxEnable
Offset 0x020F - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable.
UINT8 Avx2RatioOffset
Offset 0x0210 - AVX2 Ratio Offset 0(Default)= No Offset.
UINT8 Avx3RatioOffset
Offset 0x0211 - AVX3 Ratio Offset 0(Default)= No Offset.
UINT8 BclkAdaptiveVoltage
Offset 0x0212 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency
when calculated.
UINT8 CorePllVoltageOffset
Offset 0x0213 - Core PLL voltage offset Core PLL voltage offset.
UINT16 CoreVoltageOverride
Offset 0x0214 - core voltage override The core voltage override which is applied to the entire range of cpu core
frequencies.
UINT16 CoreVoltageAdaptive
Offset 0x0216 - Core Turbo voltage Adaptive Extra Turbo voltage applied to the cpu core when the cpu is operating in
turbo mode.
UINT16 CoreVoltageOffset
50 Class Documentation
Offset 0x0218 - Core Turbo voltage Offset The voltage offset applied to the core while operating in turbo mode.Valid
Range 0 to 1000.
UINT8 RingDownBin
Offset 0x021A - Ring Downbin Ring Downbin enable/disable.
UINT8 RingVoltageMode
Offset 0x021B - Ring voltage mode Ring voltage mode; 0: Adaptive; 1: Override.
UINT16 RingVoltageOverride
Offset 0x021C - Ring voltage override The ring voltage override which is applied to the entire range of cpu ring
frequencies.
UINT16 RingVoltageAdaptive
Offset 0x021E - Ring Turbo voltage Adaptive Extra Turbo voltage applied to the cpu ring when the cpu is operating in
turbo mode.
UINT16 RingVoltageOffset
Offset 0x0220 - Ring Turbo voltage Offset The voltage offset applied to the ring while operating in turbo mode.
UINT8 TjMaxOffset
Offset 0x0222 - TjMax Offset TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
TjMax in the range of 62 to 115 deg Celsius.
UINT8 BiosGuard
Offset 0x0223 - BiosGuard Enable/Disable.
UINT8 BiosGuardToolsInterface
Offset 0x0224.
UINT8 EnableSgx
Offset 0x0225 - EnableSgx Enable/Disable.
UINT8 Txt
Offset 0x0226 - Txt Enable/Disable.
UINT8 DpSscMarginEnable
Offset 0x0227 - DpSscMarginEnable TYPE:{Combo Enable/Disable.
UINT32 PrmrrSize
Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256M-
B=0x10000000.
UINT32 SinitMemorySize
Offset 0x022C - SinitMemorySize Enable/Disable.
UINT32 TxtHeapMemorySize
Offset 0x0230 - TxtHeapMemorySize Enable/Disable.
UINT32 TxtDprMemorySize
Offset 0x0234 - TxtDprMemorySize Enable/Disable.
UINT64 TxtDprMemoryBase
Offset 0x0238 - TxtDprMemoryBase Enable/Disable.
UINT32 BiosAcmBase
Offset 0x0240 - BiosAcmBase Enable/Disable.
UINT32 BiosAcmSize
Offset 0x0244 - BiosAcmSize Enable/Disable.
UINT32 ApStartupBase
Offset 0x0248 - ApStartupBase Enable/Disable.
UINT32 TgaSize
Offset 0x024C - TgaSize Enable/Disable.
UINT64 TxtLcpPdBase
Offset 0x0250 - TxtLcpPdBase Enable/Disable.
UINT64 TxtLcpPdSize
Offset 0x0258 - TxtLcpPdSize Enable/Disable.
UINT8 IsTPMPresence
Offset 0x0260 - IsTPMPresence IsTPMPresence default values.
12.8 FSP_M_CONFIG Struct Reference 51
UINT8 ReservedSecurityPreMem [3]
Offset 0x0261 - ReservedSecurityPreMem Reserved for Security Pre-Mem $EN_DIS.
UINT32 VtdBaseAddress [3]
Offset 0x0264 - Base addresses for VT-d function MMIO access Base addresses for VT-d MMIO access per VT-d
engine.
UINT8 PchPcieHsioRxSetCtleEnable [24]
Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle Enable PCH PCIe Gen 3 Set CTLE Value.
UINT8 PchPcieHsioRxSetCtle [24]
Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value PCH PCIe Gen 3 Set CTLE Value.
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable [24]
Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override 0: Disable; 1:
Enable.
UINT8 PchPcieHsioTxGen1DownscaleAmp [24]
Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX
Output Downscale Amplitude Adjustment value.
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable [24]
Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override 0: Disable; 1:
Enable.
UINT8 PchPcieHsioTxGen2DownscaleAmp [24]
Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 2 TX
Output Downscale Amplitude Adjustment value.
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable [24]
Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override 0: Disable; 1:
Enable.
UINT8 PchPcieHsioTxGen3DownscaleAmp [24]
Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value PCH PCIe Gen 3 TX
Output Downscale Amplitude Adjustment value.
UINT8 PchPcieHsioTxGen1DeEmphEnable [24]
Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override 0: Disable;
1: Enable.
UINT8 PchPcieHsioTxGen1DeEmph [24]
Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value PCH PCIe Gen 1 TX Output
De-Emphasis Adjustment Setting.
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable [24]
Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override 0:
Disable; 1: Enable.
UINT8 PchPcieHsioTxGen2DeEmph3p5 [24]
Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX
Output -3.5dB De-Emphasis Adjustment Setting.
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable [24]
Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override 0:
Disable; 1: Enable.
UINT8 PchPcieHsioTxGen2DeEmph6p0 [24]
Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value PCH PCIe Gen 2 TX
Output -6.0dB De-Emphasis Adjustment Setting.
UINT8 PchSataHsioRxGen1EqBoostMagEnable [8]
Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0-
: Disable; 1: Enable.
UINT8 PchSataHsioRxGen1EqBoostMag [8]
Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO
SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 PchSataHsioRxGen2EqBoostMagEnable [8]
Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0-
: Disable; 1: Enable.
52 Class Documentation
UINT8 PchSataHsioRxGen2EqBoostMag [8]
Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO
SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 PchSataHsioRxGen3EqBoostMagEnable [8]
Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override 0-
: Disable; 1: Enable.
UINT8 PchSataHsioRxGen3EqBoostMag [8]
Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value PCH HSIO
SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
UINT8 PchSataHsioTxGen1DownscaleAmpEnable [8]
Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen1DownscaleAmp [8]
Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 1.5
Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 PchSataHsioTxGen2DownscaleAmpEnable [8]
Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen2DownscaleAmp [8]
Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 3.0
Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 PchSataHsioTxGen3DownscaleAmpEnable [8]
Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen3DownscaleAmp [8]
Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value PCH HSIO SATA 6.0
Gb/s TX Output Downscale Amplitude Adjustment value.
UINT8 PchSataHsioTxGen1DeEmphEnable [8]
Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen1DeEmph [8]
Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 1.5 Gb/s
TX Output De-Emphasis Adjustment Setting.
UINT8 PchSataHsioTxGen2DeEmphEnable [8]
Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen2DeEmph [8]
Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 3.0 Gb/s
TX Output De-Emphasis Adjustment Setting.
UINT8 PchSataHsioTxGen3DeEmphEnable [8]
Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override 0:
Disable; 1: Enable.
UINT8 PchSataHsioTxGen3DeEmph [8]
Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting PCH HSIO SATA 6.0 Gb/s
TX Output De-Emphasis Adjustment Setting.
UINT8 PchLpcEnhancePort8xhDecoding
Offset 0x0450 - PCH LPC Enhance the port 8xh decoding Original LPC only decodes one byte of port 80h.
UINT8 PchPort80Route
Offset 0x0451 - PCH Port80 Route Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
UINT8 SmbusArpEnable
Offset 0x0452 - Enable SMBus ARP support Enable SMBus ARP support.
UINT8 PchNumRsvdSmbusAddresses
Offset 0x0453 - Number of RsvdSmbusAddressTable.
UINT16 PchSmbusIoBase
12.8 FSP_M_CONFIG Struct Reference 53
Offset 0x0454 - SMBUS Base Address SMBUS Base Address (IO space).
UINT16 PcieImrSize
Offset 0x0456 - Size of PCIe IMR.
UINT32 RsvdSmbusAddressTablePtr
Offset 0x0458 - Point of RsvdSmbusAddressTable Array of addresses reserved for non-ARP-capable SMBus devices.
UINT32 PcieRpEnableMask
Offset 0x045C - Enable PCIE RP Mask Enable/disable PCIE Root Ports.
UINT8 PcieImrEnabled
Offset 0x0460 - Enable PCIe IMR 0:Disable, 1:Enable $EN_DIS.
UINT8 ImrRpSelection
Offset 0x0461 - Root port number for IMR.
UINT8 PchSmbAlertEnable
Offset 0x0462 - Enable SMBus Alert Pin Enable SMBus Alert Pin.
UINT8 ReservedPchPreMem [13]
Offset 0x0463 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS.
UINT8 PcdDebugInterfaceFlags
Offset 0x0470 - Debug Interfaces Debug Interfaces.
UINT8 PcdSerialIoUartNumber
Offset 0x0471 - PcdSerialIoUartNumber Select SerialIo Uart Controller for debug.
UINT8 PcdIsaSerialUartBase
Offset 0x0472 - ISA Serial Base selection Select ISA Serial Base address.
UINT8 GtPllVoltageOffset
Offset 0x0473 - GT PLL voltage offset Core PLL voltage offset.
UINT8 RingPllVoltageOffset
Offset 0x0474 - Ring PLL voltage offset Core PLL voltage offset.
UINT8 SaPllVoltageOffset
Offset 0x0475 - System Agent PLL voltage offset Core PLL voltage offset.
UINT8 McPllVoltageOffset
Offset 0x0476 - Memory Controller PLL voltage offset Core PLL voltage offset.
UINT8 MrcSafeConfig
Offset 0x0477 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS.
UINT8 PcdSerialDebugBaudRate
Offset 0x0478 - PcdSerialDebugBaudRate Baud Rate for Serial Debug Messages.
UINT8 HobBufferSize
Offset 0x0479 - HobBufferSize Size to set HOB Buffer.
UINT8 ECT
Offset 0x047A - Early Command Training Enables/Disable Early Command Training $EN_DIS.
UINT8 SOT
Offset 0x047B - SenseAmp Offset Training Enables/Disable SenseAmp Offset Training $EN_DIS.
UINT8 ERDMPRTC2D
Offset 0x047C - Early ReadMPR Timing Centering 2D Enables/Disable Early ReadMPR Timing Centering 2D $E-
N_DIS.
UINT8 RDMPRT
Offset 0x047D - Read MPR Training Enables/Disable Read MPR Training $EN_DIS.
UINT8 RCVET
Offset 0x047E - Receive Enable Training Enables/Disable Receive Enable Training $EN_DIS.
UINT8 JWRL
Offset 0x047F - Jedec Write Leveling Enables/Disable Jedec Write Leveling $EN_DIS.
UINT8 EWRTC2D
Offset 0x0480 - Early Write Time Centering 2D Enables/Disable Early Write Time Centering 2D $EN_DIS.
UINT8 ERDTC2D
54 Class Documentation
Offset 0x0481 - Early Read Time Centering 2D Enables/Disable Early Read Time Centering 2D $EN_DIS.
UINT8 WRTC1D
Offset 0x0482 - Write Timing Centering 1D Enables/Disable Write Timing Centering 1D $EN_DIS.
UINT8 WRVC1D
Offset 0x0483 - Write Voltage Centering 1D Enables/Disable Write Voltage Centering 1D $EN_DIS.
UINT8 RDTC1D
Offset 0x0484 - Read Timing Centering 1D Enables/Disable Read Timing Centering 1D $EN_DIS.
UINT8 DIMMODTT
Offset 0x0485 - Dimm ODT Training Enables/Disable Dimm ODT Training $EN_DIS.
UINT8 DIMMRONT
Offset 0x0486 - DIMM RON Training Enables/Disable DIMM RON Training $EN_DIS.
UINT8 WRDSEQT
Offset 0x0487 - Write Drive Strength/Equalization 2D Enables/Disable Write Drive Strength/Equalization 2D $EN_-
DIS.
UINT8 WRSRT
Offset 0x0488 - Write Slew Rate Training Enables/Disable Write Slew Rate Training $EN_DIS.
UINT8 RDODTT
Offset 0x0489 - Read ODT Training Enables/Disable Read ODT Training $EN_DIS.
UINT8 RDEQT
Offset 0x048A - Read Equalization Training Enables/Disable Read Equalization Training $EN_DIS.
UINT8 RDAPT
Offset 0x048B - Read Amplifier Training Enables/Disable Read Amplifier Training $EN_DIS.
UINT8 WRTC2D
Offset 0x048C - Write Timing Centering 2D Enables/Disable Write Timing Centering 2D $EN_DIS.
UINT8 RDTC2D
Offset 0x048D - Read Timing Centering 2D Enables/Disable Read Timing Centering 2D $EN_DIS.
UINT8 WRVC2D
Offset 0x048E - Write Voltage Centering 2D Enables/Disable Write Voltage Centering 2D $EN_DIS.
UINT8 RDVC2D
Offset 0x048F - Read Voltage Centering 2D Enables/Disable Read Voltage Centering 2D $EN_DIS.
UINT8 CMDVC
Offset 0x0490 - Command Voltage Centering Enables/Disable Command Voltage Centering $EN_DIS.
UINT8 LCT
Offset 0x0491 - Late Command Training Enables/Disable Late Command Training $EN_DIS.
UINT8 RTL
Offset 0x0492 - Round Trip Latency Training Enables/Disable Round Trip Latency Training $EN_DIS.
UINT8 TAT
Offset 0x0493 - Turn Around Timing Training Enables/Disable Turn Around Timing Training $EN_DIS.
UINT8 MEMTST
Offset 0x0494 - Memory Test Enables/Disable Memory Test $EN_DIS.
UINT8 ALIASCHK
Offset 0x0495 - DIMM SPD Alias Test Enables/Disable DIMM SPD Alias Test $EN_DIS.
UINT8 RCVENC1D
Offset 0x0496 - Receive Enable Centering 1D Enables/Disable Receive Enable Centering 1D $EN_DIS.
UINT8 RMC
Offset 0x0497 - Retrain Margin Check Enables/Disable Retrain Margin Check $EN_DIS.
UINT8 WRDSUDT
Offset 0x0498 - Write Drive Strength Up/Dn independently Enables/Disable Write Drive Strength Up/Dn independently
$EN_DIS.
UINT8 EccSupport
Offset 0x0499 - ECC Support Enables/Disable ECC Support $EN_DIS.
12.8 FSP_M_CONFIG Struct Reference 55
UINT8 RemapEnable
Offset 0x049A - Memory Remap Enables/Disable Memory Remap $EN_DIS.
UINT8 RankInterleave
Offset 0x049B - Rank Interleave support Enables/Disable Rank Interleave support.
UINT8 EnhancedInterleave
Offset 0x049C - Enhanced Interleave support Enables/Disable Enhanced Interleave support $EN_DIS.
UINT8 MemoryTrace
Offset 0x049D - Memory Trace Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode.
UINT8 ChHashEnable
Offset 0x049E - Ch Hash Support Enable/Disable Channel Hash Support.
UINT8 EnableExtts
Offset 0x049F - Extern Therm Status Enables/Disable Extern Therm Status $EN_DIS.
UINT8 EnableCltm
Offset 0x04A0 - Closed Loop Therm Manage Enables/Disable Closed Loop Therm Manage $EN_DIS.
UINT8 EnableOltm
Offset 0x04A1 - Open Loop Therm Manage Enables/Disable Open Loop Therm Manage $EN_DIS.
UINT8 EnablePwrDn
Offset 0x04A2 - DDR PowerDown and idle counter Enables/Disable DDR PowerDown and idle counter $EN_DIS.
UINT8 EnablePwrDnLpddr
Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR Enables/Disable DDR PowerDown and idle counter(For
LPDDR Only) $EN_DIS.
UINT8 UserPowerWeightsEn
Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values Enables/Disable Use
user provided power weights, scale factor, and channel power floor values $EN_DIS.
UINT8 RaplLim2Lock
Offset 0x04A5 - RAPL PL Lock Enables/Disable RAPL PL Lock $EN_DIS.
UINT8 RaplLim2Ena
Offset 0x04A6 - RAPL PL 2 enable Enables/Disable RAPL PL 2 enable $EN_DIS.
UINT8 RaplLim1Ena
Offset 0x04A7 - RAPL PL 1 enable Enables/Disable RAPL PL 1 enable $EN_DIS.
UINT8 SrefCfgEna
Offset 0x04A8 - SelfRefresh Enable Enables/Disable SelfRefresh Enable $EN_DIS.
UINT8 ThrtCkeMinDefeatLpddr
Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS.
UINT8 ThrtCkeMinDefeat
Offset 0x04AA - Throttler CKEMin Defeature Enables/Disable Throttler CKEMin Defeature $EN_DIS.
UINT8 RhPrevention
Offset 0x04AB - Enable RH Prevention Enables/Disable RH Prevention $EN_DIS.
UINT8 ExitOnFailure
Offset 0x04AC - Exit On Failure (MRC) Enables/Disable Exit On Failure (MRC) $EN_DIS.
UINT8 DdrThermalSensor
Offset 0x04AD - LPDDR Thermal Sensor Enables/Disable LPDDR Thermal Sensor $EN_DIS.
UINT8 Ddr4DdpSharedClock
Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP Select if CLK0 is shared between
Rank0 and Rank1 in DDR4 DDP $EN_DIS.
UINT8 Ddr4DdpSharedZq
Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP ESelect if ZQ pin is shared
between Rank0 and Rank1 in DDR4 DDP $EN_DIS.
UINT16 ChHashMask
Offset 0x04B0 - Ch Hash Mask Set the BIT(s) to be included in the XOR function.
UINT32 BClkFrequency
56 Class Documentation
Offset 0x04B2 - Base reference clock value Base reference clock value, in Hertz(Default is 125Hz) 100000000:100Hz,
125000000:125Hz, 167000000:167Hz, 250000000:250Hz.
UINT8 ChHashInterleaveBit
Offset 0x04B6 - Ch Hash Interleaved Bit Select the BIT to be used for Channel Interleaved mode.
UINT8 EnergyScaleFact
Offset 0x04B7 - Energy Scale Factor Energy Scale Factor, Default is 4.
UINT16 Idd3n
Offset 0x04B8 - EPG DIMM Idd3N Active standby current (Idd3N) in milliamps from datasheet.
UINT16 Idd3p
Offset 0x04BA - EPG DIMM Idd3P Active power-down current (Idd3P) in milliamps from datasheet.
UINT8 CMDSR
Offset 0x04BC - CMD Slew Rate Training Enable/Disable CMD Slew Rate Training $EN_DIS.
UINT8 CMDDSEQ
Offset 0x04BD - CMD Drive Strength and Tx Equalization Enable/Disable CMD Drive Strength and Tx Equalization
$EN_DIS.
UINT8 CMDNORM
Offset 0x04BE - CMD Normalization Enable/Disable CMD Normalization $EN_DIS.
UINT8 EWRDSEQ
Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training Enable/Disable Early DQ Write Drive
Strength and Equalization Training $EN_DIS.
UINT8 RhActProbability
Offset 0x04C0 - RH Activation Probability RH Activation Probability, Probability value is 1/2(inputvalue)
UINT8 RaplLim2WindX
Offset 0x04C1 - RAPL PL 2 WindowX Power PL 2 time window X value, (1/1024)(1+(x/4))(2y) (1=Def)
UINT8 RaplLim2WindY
Offset 0x04C2 - RAPL PL 2 WindowY Power PL 2 time window Y value, (1/1024)(1+(x/4))(2y) (1=Def)
UINT8 RaplLim1WindX
Offset 0x04C3 - RAPL PL 1 WindowX Power PL 1 time window X value, (1/1024)(1+(x/4))(2y) (0=Def)
UINT8 RaplLim1WindY
Offset 0x04C4 - RAPL PL 1 WindowY Power PL 1 time window Y value, (1/1024)(1+(x/4))(2y) (0=Def)
UINT16 RaplLim2Pwr
Offset 0x04C5 - RAPL PL 2 Power range[0;214-1]= [2047.875;0]in W, (222= Def)
UINT16 RaplLim1Pwr
Offset 0x04C7 - RAPL PL 1 Power range[0;214-1]= [2047.875;0]in W, (0= Def)
UINT8 WarmThresholdCh0Dimm0
Offset 0x04C9 - Warm Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmThresholdCh0Dimm1
Offset 0x04CA - Warm Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmThresholdCh1Dimm0
Offset 0x04CB - Warm Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmThresholdCh1Dimm1
Offset 0x04CC - Warm Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotThresholdCh0Dimm0
Offset 0x04CD - Hot Threshold Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotThresholdCh0Dimm1
Offset 0x04CE - Hot Threshold Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotThresholdCh1Dimm0
Offset 0x04CF - Hot Threshold Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotThresholdCh1Dimm1
Offset 0x04D0 - Hot Threshold Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmBudgetCh0Dimm0
12.8 FSP_M_CONFIG Struct Reference 57
Offset 0x04D1 - Warm Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmBudgetCh0Dimm1
Offset 0x04D2 - Warm Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmBudgetCh1Dimm0
Offset 0x04D3 - Warm Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 WarmBudgetCh1Dimm1
Offset 0x04D4 - Warm Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotBudgetCh0Dimm0
Offset 0x04D5 - Hot Budget Ch0 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotBudgetCh0Dimm1
Offset 0x04D6 - Hot Budget Ch0 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotBudgetCh1Dimm0
Offset 0x04D7 - Hot Budget Ch1 Dimm0 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 HotBudgetCh1Dimm1
Offset 0x04D8 - Hot Budget Ch1 Dimm1 range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM.
UINT8 IdleEnergyCh0Dimm0
Offset 0x04D9 - Idle Energy Ch0Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 IdleEnergyCh0Dimm1
Offset 0x04DA - Idle Energy Ch0Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 IdleEnergyCh1Dimm0
Offset 0x04DB - Idle Energy Ch1Dimm0 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 IdleEnergyCh1Dimm1
Offset 0x04DC - Idle Energy Ch1Dimm1 Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
UINT8 PdEnergyCh0Dimm0
Offset 0x04DD - PowerDown Energy Ch0Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5=
Def)
UINT8 PdEnergyCh0Dimm1
Offset 0x04DE - PowerDown Energy Ch0Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5=
Def)
UINT8 PdEnergyCh1Dimm0
Offset 0x04DF - PowerDown Energy Ch1Dimm0 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5=
Def)
UINT8 PdEnergyCh1Dimm1
Offset 0x04E0 - PowerDown Energy Ch1Dimm1 PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5=
Def)
UINT8 ActEnergyCh0Dimm0
Offset 0x04E1 - Activate Energy Ch0Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 ActEnergyCh0Dimm1
Offset 0x04E2 - Activate Energy Ch0Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 ActEnergyCh1Dimm0
Offset 0x04E3 - Activate Energy Ch1Dimm0 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 ActEnergyCh1Dimm1
Offset 0x04E4 - Activate Energy Ch1Dimm1 Activate Energy Contribution, range[255;0],(172= Def)
UINT8 RdEnergyCh0Dimm0
Offset 0x04E5 - Read Energy Ch0Dimm0 Read Energy Contribution, range[255;0],(212= Def)
UINT8 RdEnergyCh0Dimm1
Offset 0x04E6 - Read Energy Ch0Dimm1 Read Energy Contribution, range[255;0],(212= Def)
UINT8 RdEnergyCh1Dimm0
Offset 0x04E7 - Read Energy Ch1Dimm0 Read Energy Contribution, range[255;0],(212= Def)
UINT8 RdEnergyCh1Dimm1
Offset 0x04E8 - Read Energy Ch1Dimm1 Read Energy Contribution, range[255;0],(212= Def)
58 Class Documentation
UINT8 WrEnergyCh0Dimm0
Offset 0x04E9 - Write Energy Ch0Dimm0 Write Energy Contribution, range[255;0],(221= Def)
UINT8 WrEnergyCh0Dimm1
Offset 0x04EA - Write Energy Ch0Dimm1 Write Energy Contribution, range[255;0],(221= Def)
UINT8 WrEnergyCh1Dimm0
Offset 0x04EB - Write Energy Ch1Dimm0 Write Energy Contribution, range[255;0],(221= Def)
UINT8 WrEnergyCh1Dimm1
Offset 0x04EC - Write Energy Ch1Dimm1 Write Energy Contribution, range[255;0],(221= Def)
UINT8 ThrtCkeMinTmr
Offset 0x04ED - Throttler CKEMin Timer Timer value for CKEMin, range[255;0].
UINT8 CkeRankMapping
Offset 0x04EE - Cke Rank Mapping Bits [7:4] - Channel 1, bits [3:0] - Channel 0.
UINT8 RaplPwrFlCh0
Offset 0x04EF - Rapl Power Floor Ch0 Power budget ,range[255;0],(0= 5.3W Def)
UINT8 RaplPwrFlCh1
Offset 0x04F0 - Rapl Power Floor Ch1 Power budget ,range[255;0],(0= 5.3W Def)
UINT8 EnCmdRate
Offset 0x04F1 - Command Rate Support CMD Rate and Limit Support Option.
UINT8 Refresh2X
Offset 0x04F2 - REFRESH_2X_MODE 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC en-
ables 2xRef when Hot 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only.
UINT8 EpgEnable
Offset 0x04F3 - Energy Performance Gain Enable/disable(default) Energy Performance Gain.
UINT8 RhSolution
Offset 0x04F4 - Row Hammer Solution Type of method used to prevent Row Hammer.
UINT8 UserThresholdEnable
Offset 0x04F5 - User Manual Threshold Disabled: Predefined threshold will be used.
UINT8 UserBudgetEnable
Offset 0x04F6 - User Manual Budget Disabled: Configuration of memories will defined the Budget value.
UINT8 TsodTcritMax
Offset 0x04F7 - TcritMax Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor.
UINT8 TsodEventMode
Offset 0x04F8 - Event mode Disable:Comparator mode.
UINT8 TsodEventPolarity
Offset 0x04F9 - EVENT polarity Disable:Active LOW.
UINT8 TsodCriticalEventOnly
Offset 0x04FA - Critical event only Disable:Trips on alarm or critical.
UINT8 TsodEventOutputControl
Offset 0x04FB - Event output control Disable:Event output disable.
UINT8 TsodAlarmwindowLockBit
Offset 0x04FC - Alarm window lock bit Disable:Alarm trips are not locked and can be changed.
UINT8 TsodCriticaltripLockBit
Offset 0x04FD - Critical trip lock bit Disable:Critical trip is not locked and can be changed.
UINT8 TsodShutdownMode
Offset 0x04FE - Shutdown mode Disable:Temperature sensor enable.
UINT8 TsodThigMax
Offset 0x04FF - ThighMax Thigh = ThighMax (Default is 93)
UINT8 TsodManualEnable
Offset 0x0500 - User Manual Thig and Tcrit Disabled(Default): Temperature will be given by the configuration of
memories and 1x or 2xrefresh rate.
UINT8 ForceOltmOrRefresh2x
12.8 FSP_M_CONFIG Struct Reference 59
Offset 0x0501 - Force OLTM or 2X Refresh when needed Disabled(Default): = Force OLTM.
UINT8 PwdwnIdleCounter
Offset 0x0502 - Pwr Down Idle Timer The minimum value should = to the worst case Roundtrip delay + Burst_Length.
UINT8 CmdRanksTerminated
Offset 0x0503 - Bitmask of ranks that have CA bus terminated Offset 225 LPDDR4: Bitmask of ranks that have CA
bus terminated.
UINT8 GdxcEnable
Offset 0x0504 - GDXC MOT enable GDXC MOT enable.
UINT8 PcdSerialDebugLevel
Offset 0x0505 - PcdSerialDebugLevel Serial Debug Message Level.
UINT8 FivrFaults
Offset 0x0506 - Fivr Faults Fivr Faults; 0: Disabled; 1: Enabled.
UINT8 FivrEfficiency
Offset 0x0507 - Fivr Efficiency Fivr Efficiency Management; 0: Disabled; 1: Enabled.
UINT8 SafeMode
Offset 0x0508 - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.
UINT8 CleanMemory
Offset 0x0509 - Ask MRC to clear memory content Ask MRC to clear memory content 0: Do not Clear Memory; 1:
Clear Memory.
UINT8 LpDdrDqDqsReTraining
Offset 0x050A - LpDdrDqDqsReTraining Enables/Disable LpDdrDqDqsReTraining $EN_DIS.
UINT16 PostCodeOutputPort
Offset 0x050B - Post Code Output Port This option configures Post Code Output Port.
UINT8 RMTLoopCount
Offset 0x050D - RMTLoopCount Specifies the Loop Count to be used during Rank Margin Tool Testing.
UINT8 EnBER
Offset 0x050E - BER Support Enable/Disable the Rank Margin Tool interpolation/extrapolation.
UINT8 DualDimmPerChannelBoardType
Offset 0x050F - Dual Dimm Per-Channel Board Type Option to indicate if Board Layout includes One/Two DIMMs per
channel.
UINT8 Ddr4MixedUDimm2DpcLimit
Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM
Mixed Dimm 2DPC population.
UINT8 ReservedFspmUpdCfl [2]
Offset 0x0511 - CFL Reserved Reserved FspmConfig CFL $EN_DIS.
UINT8 MemTestOnWarmBoot
Offset 0x0513 - Memory Test on Warm Boot Run Base Memory Test on Warm Boot 0:Disable, 1:Enable.
UINT8 ThrtCkeMinTmrLpddr
Offset 0x0514 - Throttler CKEMin Timer - LPDDR Timer value for CKEMin (For LPDDR Only), range[255;0].
UINT8 X2ApicOptOut
Offset 0x0515 - State of X2APIC_OPT_OUT bit in the DMAR table 0=Disable/Clear, 1=Enable/Set $EN_DIS.
UINT8 MrcTrainOnWarm
Offset 0x0516 - MRC Force training on Warm Enables/Disable the MRC training on warm boot $EN_DIS.
UINT8 LpddrDramOdt
Offset 0x0517 - Lpddr Dram Odt Override Enable/Disable for the ODT logic for LPDDR3 memory.
UINT8 ReservedFspmUpd [7]
Offset 0x0518.
12.8.1 Detailed Description
Fsp M Configuration.
Definition at line 34 of file FspmUpd.h.
60 Class Documentation
12.8.2 Member Data Documentation
12.8.2.1 UINT8 FSP_M_CONFIG::ActiveCoreCount
Offset 0x020C - Number of active cores Number of active cores(Depends on Number of cores).
0: All;1: 1 ;2: 2 ;3: 3 0:All, 1:1, 2:2, 3:3
Definition at line 985 of file FspmUpd.h.
12.8.2.2 UINT8 FSP_M_CONFIG::ApertureSize
Offset 0x00BA - Aperture Size Select the Aperture Size.
0:128 MB, 1:256 MB, 2:512 MB
Definition at line 245 of file FspmUpd.h.
12.8.2.3 UINT32 FSP_M_CONFIG::ApStartupBase
Offset 0x0248 - ApStartupBase Enable/Disable.
0: Disable, define default value of BiosAcmBase , 1: enable
Definition at line 1152 of file FspmUpd.h.
12.8.2.4 UINT8 FSP_M_CONFIG::Avx2RatioOffset
Offset 0x0210 - AVX2 Ratio Offset 0(Default)= No Offset.
Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd
0x1B.
Definition at line 1011 of file FspmUpd.h.
12.8.2.5 UINT8 FSP_M_CONFIG::Avx3RatioOffset
Offset 0x0211 - AVX3 Ratio Offset 0(Default)= No Offset.
Range 0 - 31. Specifies number of bins to decrease AVX ratio vs. Core Ratio. Uses Mailbox MSR 0x150, cmd
0x1B.
Definition at line 1017 of file FspmUpd.h.
12.8.2.6 UINT8 FSP_M_CONFIG::BclkAdaptiveVoltage
Offset 0x0212 - BCLK Adaptive Voltage Enable When enabled, the CPU V/F curves are aware of BCLK frequency
when calculated.
0: Disable;1: Enable $EN_DIS
Definition at line 1024 of file FspmUpd.h.
12.8.2.7 UINT32 FSP_M_CONFIG::BiosAcmBase
Offset 0x0240 - BiosAcmBase Enable/Disable.
0: Disable, define default value of BiosAcmBase , 1: enable
Definition at line 1142 of file FspmUpd.h.
12.8 FSP_M_CONFIG Struct Reference 61
12.8.2.8 UINT32 FSP_M_CONFIG::BiosAcmSize
Offset 0x0244 - BiosAcmSize Enable/Disable.
0: Disable, define default value of BiosAcmSize , 1: enable
Definition at line 1147 of file FspmUpd.h.
12.8.2.9 UINT8 FSP_M_CONFIG::BiosGuard
Offset 0x0223 - BiosGuard Enable/Disable.
0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS
Definition at line 1088 of file FspmUpd.h.
12.8.2.10 UINT8 FSP_M_CONFIG::BistOnReset
Offset 0x0200 - BIST on Reset Enable or Disable BIST on Reset; 0: Disable; 1: Enable.
$EN_DIS
Definition at line 909 of file FspmUpd.h.
12.8.2.11 UINT8 FSP_M_CONFIG::BootFrequency
Offset 0x020B - Boot frequency Sets the boot frequency starting from reset vector.
0: Maximum battery performance.- 1: Maximum non-turbo performance.- 2: Turbo performance.
Note
If Turbo is selected BIOS will start in max non-turbo mode and switch to Turbo mode. 0:0, 1:1, 2:2
Definition at line 978 of file FspmUpd.h.
12.8.2.12 UINT8 FSP_M_CONFIG::ChHashEnable
Offset 0x049E - Ch Hash Support Enable/Disable Channel Hash Suppor