Compal LA 4182P
User Manual:
Open the PDF directly: View PDF 
.
Page Count: 48
| Download | |
| Open PDF In Browser | View PDF |
A B C D E 1 1 Compal Confidential 2 2 JALC0 Schematics Document AMD Griffin Processor with RS780M+SB700 (With ATI MXM/B) 2008-9-11 3 3 REV:2.0 4 4 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/04/04 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 1 of 48 A B C Compal Confidential AMD S1G2 Processor Fan Control Model Name : JALC0 D page 35 Memory BUS(DDRII) uPGA-638 Package HDMI Conn. page 16 LCD Conn. CRT page 15 200pin DDRII-SO-DIMM X2 Dual Channel page 8,9 BANK 0, 1, 2, 3 1.8V DDRII 533/667 page 4,5,6,7 1 E 1 Hyper Transport Link 16 x 16 page 17 Thermal Sensor ADM1032 ATI RS780 Clock Generator ICS9LPRS488B page 5 page 14 uFCBGA-1299 PCI-Express 1x MINI Card x2 TV-Tuner WLAN LAN(GbE) BCM5764M page 28 2 port 1,2 page 26 port 3 Card Reader JMB385 page 25 page 28,29 page 36 A link Express2 USB conn X3/4 USB port 0,7,2 port 4 RJ45 page 10,11,12,13 ATI SB700 3.3V 48MHz 5 in 1 socket PCI BUS page 28 page 28 Mini card X2 CMOS Camera Bluetooth Conn finger printer USB port 4 USB port 5 USB port 6 USB port 1 USB port 8,10 2 USB HD Audio BGA-676 3.3V 33 MHz Card Bus O2 OZ601 page 24 page 29 Cable Dock 3.3V 24.576MHz/48Mhz page 24 page 27 page 15 S-ATA page 18,19,20,21,22 MDC 1.5 Conn page 32 IDSEL:AD17 (PIRQE#, GNT#0, REQ#0) SATA HDD Conn. page LPC BUS 23 CDROM Conn. page 23 port 0 PCMCIA socket HDA Codec ALC268/888 page 33 Analog internal MIC port 2 Audio AMP page 34 ENE KB926 page 30 3 BTN/B Conn. RTC CKT. page 34 page 31 page 18 Int.KBD Touch Pad page 31 Power On/Off CKT. page 32 DC/DC Interface CKT. 3 Phone Jack x3 page 31 LED/B Conn. EC I/O Buffer page 31 BIOS page 31 page 31 USB/B Conn. USB port 2 page 37 page 28 Power Circuit DC/DC 4 page 39,40,41 42,43,44,45 4 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 2 of 48 A B C D SIGNAL STATE Voltage Rails 1 E SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.25VS 1.25V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF Vcc Ra/Rc/Re +2.5VS 2.5V switched power rail ON OFF OFF Board ID +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail for SB ON ON X +3V_LAN 3.3V power rail for LAN ON ON X +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON 0 1 2 3 4 5 6 7 Full ON 1 Board ID / SKU ID Table for AD channel 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V 2 2 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table Board ID 0 1 2 3 4 5 6 7 External PCI Devices Device IDSEL# AD17 PCMCIA Card bus 0 EC SM Bus1 address 3 Device Address Smart Battery 0001 011X b Interrupts PIRQE PCB Revision 0.1 0.2 0.3, 0.4, 1.0 2.0 BTO Item 5787 5764 ALC888VC ALC268 with docking w/o docking BOM Structure EEPROM@ FLASH@ 5787@ 5764@ 888@ ALC268@ Docking@ no docking@ EC SM Bus2 address Device EEPROM(24C16/02) 1010 000X b MXM GMT G781-1 REQ#/GNT# BTO Option Table 3 Address ADI ADM1032 1001 100X b CPU SB 1001 101X b 1001 101X b SB700 SM Bus 0 address SB700 SM Bus 1 address Device Address Clock Generator (ICS9LPRS365) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb Device Address New card Lan Minicard 4 4 Minicard HDMI switch 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 3 of 48 A B C D E 1 1 VLDT CAP. +1.2V_HT 250 mil 1 H_CADIP[0..15] 10 H_CADIP[0..15] H_CADOP[0..15] H_CADIN[0..15] 10 H_CADIN[0..15] H_CADON[0..15] H_CADOP[0..15] H_CADON[0..15] 10 2 10 C455 4.7U_0805_10V4Z 1 1 C133 4.7U_0805_10V4Z 2 C131 0.22U_0603_16V4Z 2 1 C451 0.22U_0603_16V4Z 2 1 C138 180P_0402_50V8J 2 1 C444 180P_0402_50V8J 2 Near CPU Socket +1.2V_HT +1.2V_HT JCPU1A 2 VLDT=500mA H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 3 HT LINK D1 D2 D3 D4 VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 AE2 AE3 AE4 AE5 1 C134 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 2 2 4.7U_0805_10V4Z 3 10 10 10 10 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 J3 J2 J5 K5 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 10 10 10 10 10 10 10 10 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 10 10 10 10 6090022100G_B Athlon 64 S1 Processor Socket 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 4 of 48 A B C D E Processor DDR2 Memory Interface PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH JCPU1C 9 DDRB_SDQ[63..0] MEM:DATA DDRA_CLK0 +1.8V 1 2 1 R77 1K_0402_1% DDRA_CLK0# 2 C219 1.5P_0402_50V9C 1 DDRA_CLK1 1 R75 1K_0402_1% 1 2 C168 1000P_0402_25V8J 1 C164 0.1U_0402_16V4Z 2 +MCH_REF 1 2 DDRA_CLK1# 2 C162 1.5P_0402_50V9C DDRB_CLK0 1 DDRB_CLK0# 2 C483 1.5P_0402_50V9C DDRB_CLK1 1 DDRB_CLK1# 2 C413 1.5P_0402_50V9C +0.9V +0.9V JCPU1B 2 Place them close to CPU within 1" +1.8V 8 8 R347 39.2_0402_1% 1 2 1 2 R338 39.2_0402_1% DDRA_ODT0 DDRA_ODT1 8 DDRA_SCS0# 8 DDRA_SCS1# 8 DDRA_CKE0 8 DDRA_CKE1 8 DDRA_CLK0 8 DDRA_CLK0# 8 DDRA_CLK1 8 DDRA_CLK1# 3 8 DDRA_SMA[15..0] 8 DDRA_SBS0# 8 DDRA_SBS1# 8 DDRA_SBS2# 8 DDRA_SRAS# 8 DDRA_SCAS# 8 DDRA_SWE# DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15 D10 C10 B10 AD10 VTT1 VTT2 VTT3 VTT4 AF10 AE10 MEMZP MEMZN MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 H16 RSVD_M1 T19 V22 U21 V19 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 T20 U19 U20 V20 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 J22 J20 MA_CKE0 MA_CKE1 W10 AC10 AB10 AA10 A10 VTT_SENSE Y10 MEMVREF W17 1 RSVD_M2 B18 MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 DDRB_ODT0 DDRB_ODT1 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 DDRB_SCS0# DDRB_SCS1# MB_CKE0 MB_CKE1 J25 H26 DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15 N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3 P22 R22 A17 A18 AF18 AF17 R26 R25 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 R257 2 0_0402_5% @ +0.9V +MCH_REF DDRB_ODT0 9 DDRB_ODT1 9 DDRB_SCS0# 9 DDRB_SCS1# 9 DDRB_CKE0 9 DDRB_CKE1 9 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# 9 9 9 9 9 DDRB_SDM[7..0] DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRB_SMA[15..0] 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 DDRB_SBS0# 9 DDRB_SBS1# 9 DDRB_SBS2# 9 DDRB_SRAS# 9 DDRB_SCAS# 9 DDRB_SWE# 9 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# Athlon 64 S1 Processor Socket DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# DDRA_SDQ[63..0] 8 1 2 DDRA_SDM[7..0] DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# 8 3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Athlon 64 S1 Processor Socket 6090022100G_B 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 5 of 48 A B +2.5VS 1 + C500 150U_D2_6.3VM C D +2.5VDDA L60 3300P_0402_50V7K 1 2 FBM_L11_201209_300L_0805 1 1 1 4.7U_0805_10V4Z C473 +1.8V C218 2 2 C220 0.22U_0603_16V4Z 2 1 R350 1 R351 2 10K_0402_5% 2 300_0402_5% B 2 2 E CPU_CLKIN_SC_P CPU_CLKIN_SC_N 2 3900P_0402_50V7K 1 1 C488 R396 169_0402_1% 1 C489 2 3900P_0402_50V7K +1.8VS 2 R81 R84 +1.2V_HT LDT_RST# 2 C482 0.01U_0402_25V4Z @ R92 +CPU_CORE_1 R78 2 R402 300_0402_5% AF4 AF5 AE6 SIC SID ALERT_L R6 P6 HT_REF0 HT_REF1 10_0402_5% 1 2CPU_VDD0_FB_H 1 2CPU_VDD0_FB_L 10_0402_5% 1 2 AF6 AC7 AA8 CPU_THERMTRIP#_R H_PROCHOT# 2 1 +1.8V R529 @ 300_0402_5% THERMDC_CPU 2 @ C604 THERMDA_CPU 2200P_0402_50V7K 1 THERMDC THERMDA W7 W8 CPU_SVC 45 CPU_SVD 45 45 CPU_VDD0_FB_H 45 CPU_VDD0_FB_L F6 E6 VDD0_FB_H VDD0_FB_L VDDIO_FB_H VDDIO_FB_L W9 Y9 45 CPU_VDD1_FB_H 45 CPU_VDD1_FB_L CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6 VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L H6 G6 CPU_VDDNB_FB_H CPU_VDDNB_FB_L DBREQ_L E10 CPU_DBREQ# TDO AE9 CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI 10_0402_5% 1 2CPU_VDD1_FB_H 1 2CPU_VDD1_FB_L 10_0402_5% DBRDY TMS TCK TRST_L TDI AD7 TEST23 T8 PAD T12 PAD CPU_TEST18 CPU_TEST19 H10 G9 TEST18 TEST19 T21 PAD T15 PAD CPU_TEST25H CPU_TEST25L PAD CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27 T25 PAD T3 PAD T23 PAD C481 0.01U_0402_25V4Z @ G10 AA9 AC9 AD9 AF9 CPU_TEST23 T2 H_PWRGD H_PWRGD THERMTRIP_L PROCHOT_L MEMHOT_L CPU_SVC CPU_SVD CPU_VDD0_FB_H CPU_VDD0_FB_L T24 PAD 1 18 R76 CPU_SIC CPU_SID 2 44.2_0402_1% CPU_HTREF0 2 44.2_0402_1% CPU_HTREF1 2 +1.8VS RESET_L PWROK LDTSTOP_L LDTREQ_L R407 2 0_0402_5% 1 T22 PAD CPU_TEST6 AB8 AF7 AE7 AE8 AC8 AF8 TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 C2 AA6 TEST9 TEST6 A3 A5 B3 B5 C1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 H_PROCHOT# 1 1 3 2 +CPU_CORE_NB TEST17 TEST16 TEST15 TEST14 D7 E7 F7 C7 CPU_TEST17 CPU_TEST16 CPU_TEST15 CPU_TEST14 TEST7 TEST10 C3 K8 CPU_TEST7 CPU_TEST10 TEST8 C4 CPU_TEST8 TEST29_H TEST29_L C9 C8 PAD PAD PAD PAD PAD PAD T18 T19 T11 T20 PAD PAD T13 T7 PAD T14 CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N R97 10_0402_5% 1 2 1 2 R102 10_0402_5% PAD PAD 2 T9 T10 +1.8V CPU_SVC CPU_SVD 1 R397 1 R398 2 1K_0402_5% 2 1K_0402_5% T17 T16 H18 H19 AA7 D5 C5 C221 0.01U_0402_25V4Z @ 1 2 3 4 5 6 7 8 9 10 11 12 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO LDT_STOP# HDT_RST# C410 @ 1 2 @ 1 2 1 2 R523 2CPU_SID @ 0_0402_5% R519 2 @ 0_0402_5% R520 2 @ 0_0402_5% @ FDV301N_NL_SOT23-3 3 1 1 D S Q32 1 2 3 1 1 R521 2 @ 0_0402_5% 1 R522 2 @ 0_0402_5% D R524 2CPU_SIC @ 0_0402_5% S 19 ICH_SCLK3 1 G +3VS EC_SMB_DA1 30,39 ICH_SMBCLK1 19,26 EC_SMB_CK1 30,39 Q33 @ FDV301N_NL_SOT23-3 1 C392 2 CPU_TEST24 1 SCLK 8 EC_SMB_CK2 D+ SDATA 7 EC_SMB_DA2 D- ALERT# 6 GND 5 VDD 2 THERMDC_CPU C399 1 2 2200P_0402_50V7K 3 4 THERM# 3 CPU_DBREQ# @ CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO @ @ +1.8V JP1 1 3 5 7 9 11 13 15 17 19 21 23 @ U24 THERMDA_CPU 2 300_0402_5% 2 300_0402_5% 2 300_0402_5% ICH_SMBDATA1 19,26 R346 2 +1.8V 2.2K_0402_5% CPU_TEST21 1 R488 1 R489 1 R490 +1.8V R345 2 1 2.2K_0402_5% G 1 19 ICH_SDATA3 +1.8V CPU_DBREQ# 34.8K_0402_1%~N 20K_0402_5% +1.8V 1 2 3 4 5 6 7 8 9 10 GND GND ACES_85201-1005N @ R348 @ 1 2 1 220_0402_5%R501 2 1 220_0402_5%R502 2 1 220_0402_5%R503 2 1 220_0402_5%R504 2 +3VS 0.1U_0402_16V4Z CPU_VDDNB_FB_H CPU_VDDNB_FB_L CPU_VDDNB_FB_H 45 CPU_VDDNB_FB_L 45 0.1U_0402_16V4Z EC_SMB_CK2 30 2 4 6 8 10 12 14 16 18 20 22 24 26 R335 2 @ 0_0402_5% 1 +3VS U23 HDT_RST# 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title 1 LDT_RST# SB_PWRGD 19,32 NC7SZ08P5X_NL_SC70-5 SCHEMATICS, M/B S4182 Date: C 2 A Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B B Y CONN@ SAMTEC_ASP-68200-07 EC_SMB_DA2 30 ADM1032ARMZ_MSOP8 A H_PROCHOT_R# 18 CPU_TDO 6090022100G_B R344 4 R104 2 0_0402_5% 1 JP29 R103 300_0402_5% 11,18 LDT_STOP# 1 2 300_0402_5% T5 T6 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 1 R383 +1.8V 2 +1.8VS E9 E8 PAD PAD J7 H8 TEST28_H TEST28_L H_THERMTRIP# 19 5 1 B7 A7 F10 C6 A6 A4 P LDT_RST# SVC SVD MAINPWON 39,40 MMBT3904_NL_SOT23-3 M11 W18 G 18 +CPU_CORE_0 R90 1 1 KEY1 KEY2 R334 2 @ 0_0402_5% R333 2 0_0402_5% 1 3 1 R403 300_0402_5% CLKIN_H CLKIN_L LDT_RST# H_PWRGD LDT_STOP# 11 CPU_LDT_REQ# 2 14 CLK_CPU_BCLK# VDDA1 VDDA2 A9 A8 3 C 14 CLK_CPU_BCLK F8 F9 CPU_THERMTRIP#_R 1 Q34 1 E JCPU1D 1 D Rev E 401561 Sheet Thursday, September 11, 2008 E 6 of 48 4 A B C D E JCPU1F VDD(+CPU_CORE) decoupling. +CPU_CORE_0 +CPU_CORE_1 1 1 + 1 + C40 330U_X_2VM_R6M 1 2 1 + C39 330U_X_2VM_R6M 2 C36 330U_X_2VM_R6M 2 + C37 330U_X_2VM_R6M 2 Near CPU Socket +CPU_CORE_0 +CPU_CORE_1 +CPU_CORE_NB 1 C194 22U_0805_6.3V6M 2 1 C206 22U_0805_6.3V6M 2 1 C199 22U_0805_6.3V6M 2 1 C205 22U_0805_6.3V6M 1 2 1 C179 22U_0805_6.3V6M 2 C180 22U_0805_6.3V6M 2 +CPU_CORE_0 1 1 C170 22U_0805_6.3V6M 2 1 C186 22U_0805_6.3V6M 2 +1.8V +CPU_CORE_1 C198 0.22U_0603_16V4Z 2 1 C195 0.01U_0402_25V4Z 2 1 JCPU1E +CPU_CORE_0 1 C196 180P_0402_50V8J 2 C185 0.22U_0603_16V4Z 2 1 C167 0.01U_0402_25V4Z 2 1 C163 180P_0402_50V8J 2 Under CPU Socket 2 G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 K16 M16 P16 T16 V16 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 +CPU_CORE_1 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 +1.8V 6090022100G_B Athlon 64 S1 Processor Socket VDDIO decoupling. +CPU_CORE_NB decoupling. +1.8V +CPU_CORE_NB 1 C188 22U_0805_6.3V6M 2 1 C210 22U_0805_6.3V6M 1 1 C197 0.22U_0603_16V4Z 2 2 1 C214 0.22U_0603_16V4Z 2 1 C175 C169 1 180P_0402_50V8J 180P_0402_50V8J 2 2 C183 22U_0805_6.3V6M 2 1 C191 22U_0805_6.3V6M 2 1 C207 22U_0805_6.3V6M 2 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 1 2 6090022100G_B Under CPU Socket Athlon 64 S1 Processor Socket Between CPU Socket and DIMM +1.8V +0.9V 3 1 C431 0.22U_0603_16V4Z 2 1 C430 0.22U_0603_16V4Z 2 C424 0.22U_0603_16V4Z 2 +1.8V 1 1 C421 0.01U_0402_25V4Z 2 1 C422 0.01U_0402_25V4Z 2 C517 C425 0.22U_0603_16V4Z C423 180P_0402_50V8J 1 C433 180P_0402_50V8J 2 C434 180P_0402_50V8J 2 2 +0.9V 1 2 C432 1 180P_0402_50V8J C407 4.7U_0805_10V4Z A: Add C165 and C176 to follow AMD Layout review recommand for EMI +1.8V C510 22U_0805_6.3V6M 2 1 2 C: Change to NBO CAP 1 220U_D2_4VM_R15 180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch> 3 Near Power Supply 1 + 2 +1.8V 1 1 VTT decoupling. 2 1 C406 4.7U_0805_10V4Z 2 1 C411 0.22U_0603_16V4Z 2 1 C412 0.22U_0603_16V4Z 2 1 C156 1000P_0402_25V8J 2 1 C155 1000P_0402_25V8J 2 1 C154 180P_0402_50V8J 2 1 C157 180P_0402_50V8J 2 Near CPU Socket Right side. +0.9V 1 1 2 1 C216 4.7U_0805_10V4Z 2 1 C151 4.7U_0805_10V4Z 2 1 C152 4.7U_0805_10V4Z 2 C217 4.7U_0805_10V4Z C: Change to NBO CAP + C149 330U_X_2VM_R6M 1 2 2 C499 4.7U_0805_10V4Z 1 C498 4.7U_0805_10V4Z 2 1 C491 0.22U_0603_16V4Z 2 1 C492 0.22U_0603_16V4Z 2 1 C478 1000P_0402_25V8J 2 1 C485 1000P_0402_25V8J 2 1 C479 180P_0402_50V8J 2 1 C486 180P_0402_50V8J 2 4 4 Near CPU Socket Left side. Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 7 of 48 A B +1.8V C D E +1.8V RESERVE +V_DDR_MCH_REF BUFFER CIRCUIT JDIMM1 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2 5 DDRA_SDQS2# 5 DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 2 DDRA_CKE0 5 DDRA_CKE0 5 DDRA_SBS2# DDRA_SBS2# DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1 5 5 DDRA_SBS0# DDRA_SWE# 5 5 DDRA_SCAS# DDRA_SCS1# 5 DDRA_ODT1 DDRA_SMA10 DDRA_SBS0# DDRA_SWE# DDRA_SCAS# DDRA_SCS1# DDRA_ODT1 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4# DDRA_SDQS4 5 DDRA_SDQS4# 5 DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 3 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6# DDRA_SDQS6 5 DDRA_SDQS6# 5 DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58 DDRA_SDQ59 ICH_SMBDATA0 ICH_SMBCLK0 9,14,16,19,28 ICH_SMBDATA0 9,14,16,19,28 ICH_SMBCLK0 +3VS 4 1 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND DDRA_SDQ6 DDRA_SDQ7 5 DDRA_SDM[0..7] 5 DDRA_SMA[0..15] 5 1 DDRA_SMA[0..15] DDRA_SDQ12 DDRA_SDQ13 DDRA_SDM1 +1.8V +0.9V RP12 DDRA_CLK0 5 DDRA_CLK0# 5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA11 DDRA_SMA15 DDRA_SDQ14 DDRA_SDQ15 1 C147 1 C192 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C176 1 C178 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C184 1 C182 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C140 1 C165 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SBS0# DDRA_SMA10 DDRA_SMA1 DDRA_SMA3 47_0804_8P4R_5% RP7 8 1 7 2 6 3 5 4 1 C190 1 C143 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SCS1# DDRA_ODT1 DDRA_SWE# DDRA_SCAS# 47_0804_8P4R_5% RP3 8 1 7 2 6 3 5 4 1 C153 1 C160 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z DDRA_SMA13 DDRA_ODT0 DDRA_SCS0# DDRA_SRAS# 47_0804_8P4R_5% RP4 1 8 2 7 3 6 4 5 1 C166 1 C145 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +1.8V 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204 DDRA_SDQ20 DDRA_SDQ21 R140 1K_0402_1% DDRA_SDM2 +V_DDR_MCH_REF DDRA_SDQ22 DDRA_SDQ23 1 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQS3# DDRA_SDQS3 C610 2 DDRA_SDQS3# 5 DDRA_SDQS3 5 1 2 DDRA_SDQ30 DDRA_SDQ31 DDRA_CKE1 DDRA_CKE0 DDRA_SBS2# DDRA_SMA14 DDRA_CKE1 1 2 +V_DDR_MCH_REF DDRA_SBS1# DDRA_SMA0 DDRA_SMA2 DDRA_SMA4 R138 1K_0402_1% DDRA_SMA5 DDRA_SMA8 DDRA_SMA9 DDRA_SMA12 DDRA_CKE1 5 DDRA_SMA15 DDRA_SMA14 DDRA_SMA11 DDRA_SMA7 DDRA_SMA6 DDRA_SMA4 DDRA_SMA2 DDRA_SMA0 DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# DDRA_ODT0 DDRA_SMA13 DDRA_SBS1# 5 DDRA_SRAS# 5 DDRA_SCS0# 5 DDRA_ODT0 5 1 2 3 4 8 7 6 5 47_0804_8P4R_5% RP13 8 1 7 2 6 3 5 4 47_0804_8P4R_5% RP8 1 8 2 7 3 6 4 5 47_0804_8P4R_5% RP11 8 1 7 2 6 3 5 4 C47 1 47_0804_8P4R_5% DDRA_SDQ36 DDRA_SDQ37 DDRA_SDM4 DDRA_SDQ38 DDRA_SDQ39 3 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQS5# DDRA_SDQS5 DDRA_SDQS5# 5 DDRA_SDQS5 5 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ52 DDRA_SDQ53 DDRA_CLK1 5 DDRA_CLK1# 5 DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQS7# DDRA_SDQS7 DDRA_SDQS7# 5 DDRA_SDQS7 5 DDRA_SDQ62 DDRA_SDQ63 R36 R33 1 1 DIMM1 REV H:5.2mm (BOT) 0.1U_0402_16V4Z 2 2 2.2U_0805_10V6K 2 10K_0402_5% 2 10K_0402_5% 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A 2 FOX_AS0A426-M2RN-7F CONN@ +3VS C33 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203 DDRA_SDQ[0..63] DDRA_SDM[0..7] 2 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ[0..63] DDRA_SDM0 1 DDRA_SDQS1# DDRA_SDQS1 5 DDRA_SDQS1# 5 DDRA_SDQS1 DDRA_SDQ4 DDRA_SDQ5 2 DDRA_SDQ8 DDRA_SDQ9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 DDRA_SDQ2 DDRA_SDQ3 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS C239 0.1U_0402_16V4Z 1 DDRA_SDQS0# DDRA_SDQS0 5 DDRA_SDQS0# 5 DDRA_SDQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS C238 1000P_0402_25V8J DDRA_SDQ0 DDRA_SDQ1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2.2U_0603_6.3V4Z +V_DDR_MCH_REF B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 8 of 48 A B +V_DDR_MCH_REF 2 1 D E +1.8V +1.8V 2.2U_0603_6.3V4Z 1 C611 C DDRB_SDQ[0..63] JDIMM2 DDRB_SDQ0 DDRB_SDQ1 5 DDRB_SDQS0# 5 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ8 DDRB_SDQ9 5 DDRB_SDQS1# 5 DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS1 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ16 DDRB_SDQ17 5 DDRB_SDQS2# 5 DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS2 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDM3 2 DDRB_SDQ26 DDRB_SDQ27 5 DDRB_CKE0 5 DDRB_SBS2# DDRB_CKE0 DDRB_SBS2# DDRB_SMA12 DDRB_SMA9 DDRB_SMA8 DDRB_SMA5 DDRB_SMA3 DDRB_SMA1 5 5 DDRB_SBS0# DDRB_SWE# 5 5 DDRB_SCAS# DDRB_SCS1# 5 DDRB_ODT1 DDRB_SMA10 DDRB_SBS0# DDRB_SWE# DDRB_SCAS# DDRB_SCS1# DDRB_ODT1 DDRB_SDQ32 DDRB_SDQ33 5 DDRB_SDQS4# 5 DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS4 DDRB_SDQ34 DDRB_SDQ35 3 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ48 DDRB_SDQ49 5 DDRB_SDQS6# 5 DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS6 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDM7 DDRB_SDQ58 DDRB_SDQ59 8,14,16,19,28 ICH_SMBDATA0 8,14,16,19,28 ICH_SMBCLK0 ICH_SMBDATA0 ICH_SMBCLK0 +3VS 4 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SDQ4 DDRB_SDQ5 DDRB_SDM[0..7] 5 5 DDRB_SDM0 DDRB_SMA[0..15] DDRB_SMA[0..15] DDRB_SDQ6 DDRB_SDQ7 5 1 DDRB_SDQ12 DDRB_SDQ13 +1.8V DDRB_SDM1 1 DDRB_CLK0 5 DDRB_CLK0# 5 330U_X_2VM_R6M C32 @ DDRB_SDQ14 DDRB_SDQ15 + +1.8V +0.9V RP5 DDRB_SRAS# DDRB_SMA0 DDRB_SMA2 DDRB_SMA4 2 1 2 3 4 DDRB_SDQ20 DDRB_SDQ21 8 7 6 5 2 C187 1 C171 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C146 1 C177 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C173 1 C158 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 47_0804_8P4R_5% RP9 DDRB_SMA6 DDRB_SMA7 DDRB_SMA11 DDRB_SMA14 DDRB_SDM2 DDRB_SDQ22 DDRB_SDQ23 1 2 3 4 8 7 6 5 47_0804_8P4R_5% DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQS3# DDRB_SDQS3 RP14 DDRB_CKE0 DDRB_SBS2# DDRB_SMA15 DDRB_CKE1 DDRB_SDQS3# 5 DDRB_SDQS3 5 8 7 6 5 DDRB_SDQ30 DDRB_SDQ31 DDRB_CKE1 1 2 3 4 2 47_0804_8P4R_5% RP10 DDRB_CKE1 5 DDRB_SMA8 DDRB_SMA5 DDRB_SMA12 DDRB_SMA9 DDRB_SMA15 DDRB_SMA14 DDRB_SMA11 DDRB_SMA7 DDRB_SMA6 8 7 6 5 1 2 3 4 2 C144 1 C141 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C161 1 C150 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C148 1 C189 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 C181 1 C193 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 47_0804_8P4R_5% RP6 DDRB_SMA4 DDRB_SMA2 DDRB_SMA0 DDRB_SBS0# DDRB_SMA10 DDRB_SMA3 DDRB_SMA1 DDRB_SBS1# DDRB_SRAS# DDRB_SCS0# DDRB_ODT0 DDRB_SMA13 DDRB_SBS1# 5 DDRB_SRAS# 5 DDRB_SCS0# 5 8 7 6 5 1 2 3 4 47_0804_8P4R_5% RP1 DDRB_ODT1 DDRB_SCS1# DDRB_SWE# DDRB_SCAS# DDRB_ODT0 5 DDRB_SDQ36 DDRB_SDQ37 8 7 6 5 1 2 3 4 47_0804_8P4R_5% RP2 DDRB_SDM4 DDRB_SMA13 DDRB_ODT0 DDRB_SCS0# DDRB_SBS1# DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQS5# DDRB_SDQS5 1 2 3 4 8 7 6 5 3 47_0804_8P4R_5% DDRB_SDQS5# 5 DDRB_SDQS5 5 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ52 DDRB_SDQ53 DDRB_CLK1 5 DDRB_CLK1# 5 DDRB_SDM6 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQS7# DDRB_SDQS7 DDRB_SDQS7# 5 DDRB_SDQS7 5 DDRB_SDQ62 DDRB_SDQ63 R330 1 R325 1 2 10K_0402_5% 2 10K_0402_5% +3VS 4 FOX_AS0A426-MARG-7F CONN@ DIMM1 REV H:9.2mm (BOT) Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Rev E 401561 Sheet Thursday, September 11, 2008 E 9 of 48 A B C D E U22B 28 28 28 28 26 26 25 25 PCIE_PTX_C_IRX_P1 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P4 PCIE_PTX_C_IRX_N4 18 18 18 18 18 18 18 18 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2 GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN) AC8 AB8 PART 2 OF 6 PCIE I/F GPP PCIE I/F SB TMDS_P2 TMDS_N2 TMDS_P1 TMDS_N1 TMDS_P0 TMDS_N0 TMDS_CLK TMDS_CLK# C382 1 0.1U_0402_16V7K 2 C378 1 2 0.1U_0402_16V7K C377 1 2 0.1U_0402_16V7K C374 1 0.1U_0402_16V7K 2 PCIE_ITX_PRX_P1 mini2@ mini2@C12 C12 PCIE_ITX_PRX_N1 mini2@ mini2@C11 C11 PCIE_ITX_PRX_P2 C5 PCIE_ITX_PRX_N2 C4 PCIE_ITX_PRX_P3 C6 PCIE_ITX_PRX_N3 C7 PCIE_ITX_PRX_P4 C14 PCIE_ITX_PRX_N4 C13 1 2 2 1 1 2 2 1 1 2 2 1 2 0.1U_0402_16V7K C372 1 2 0.1U_0402_16V7K C376 1 2 0.1U_0402_16V7K C375 1 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 1 1 C380 1 2 TMDS_P2_C 16 TMDS_N2_C 16 TMDS_P1_C 16 TMDS_N1_C 16 TMDS_P0_C 16 TMDS_N0_C 16 TMDS_CLK_C 16 TMDS_CLK#_C 16 1 New Card PCIE_ITX_C_PRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P4 PCIE_ITX_C_PRX_N4 28 28 28 28 26 26 25 25 2 TV Tuner WLAN GLAN Card Reader4 H_CADOP[0..15] 4 H_CADON[0..15] SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C R29 R32 C244 C242 C250 C251 C236 C234 C243 C241 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 1.27K_0402_1% 2K_0402_1% SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N 18 18 18 18 18 18 18 18 H_CADIP[0..15] H_CADIN[0..15] H_CADIP[0..15] 4 H_CADIN[0..15] 4 U22A +1.1VS RS780M_FCBGA528 RS780M Display Port Support (muxed on GFX) GFX_TX0,TX1,TX2 and TX3 DP0 AUX0 and HPD0 3 H_CADOP[0..15] H_CADON[0..15] GFX_TX4,TX5,TX6 and TX7 DP1 AUX1 and HPD1 4 4 4 4 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 4 4 4 4 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 1 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N T22 T23 AB23 AA22 HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N M22 M23 R21 R20 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 R67 2 301_0402_1%~D C23 A24 HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N H24 H25 L21 L20 HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N M24 M25 P19 R18 HT_RXCALP HT_RXCALN HT_TXCALP HT_TXCALN B24 B25 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART 1 OF 6 HYPER TRANSPORT CPU I/F 2 GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N PCIE I/F GFX 1 D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 RS780M_FCBGA528 0718 Place within 1" layout 1:2 3 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 4 4 4 4 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 4 4 4 4 R71 1 2 301_0402_1%~D 0718 Place within 1" layout 1:24 Compal Secret Data Security Classification 2007/09/14 Issued Date 4 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 10 of 48 A B C D E For RS780M A13 +3VS 1 C29 2.2U_0603_6.3V4Z 1 2 U22C 2 1 C142 2.2U_0603_6.3V4Z 2 +NB_PLLVDD L43 1 2 MBK2012221YZF 0805 1 +1.8VS +VDDA18HTPLL C400 2.2U_0603_6.3V4Z L24 1 2 MBK2012221YZF 0805 1 C136 2.2U_0603_6.3V4Z GMCH_CRT_R 17 GMCH_CRT_R +1.1VS GMCH_CRT_G 17 GMCH_CRT_G GMCH_CRT_B 17 GMCH_CRT_B R47 2 +NB_PLLVDD +NB_HTPVDD 2 +VDDA18PCIEPLL +VDDA18HTPLL L5 1 2 MBK2012221YZF 0805 1 C24 2.2U_0603_6.3V4Z 2 +1.8VS 2 R326 2 0_0402_5% 1 2 R38 4.7K_0402_5% 1 2 R39 4.7K_0402_5% 14 CLK_SBLINK_BCLK 14 CLK_SBLINK_BCLK# 3 GMCH_LCD_CLK 2 4.7K_0402_5% GMCH_LCD_DATA 2 4.7K_0402_5% 1 R323 1 R322 R316 R318 R312 R313 1 1 1 1 @ @ 2 2 2 2 @ 2 R327 +3VS 42 POWER_SEL 1 10K_0402_5% POWER_SEL 15 GMCH_LCD_CLK 15 GMCH_LCD_DATA 16 GMCH_DDC_DATA 16 GMCH_DDC_CLK 16 GMCH_DDC_CLK1 16 GMCH_DDC_DATA1 GMCH_LCD_CLK GMCH_LCD_DATA GMCH_DDC_DATA GMCH_DDC_CLK GMCH_DDC_CLK1 GMCH_DDC_DATA1 Strap pin 4.7K_0402_5% GMCH_DDC_CLK 4.7K_0402_5% GMCH_DDC_DATA 4.7K_0402_5% GMCH_DDC_CLK1 4.7K_0402_5% GMCH_DDC_DATA1 H17 VDDA18HTPLL SYSRESETb POWERGOOD LDTSTOPb ALLOW_LDTSTOP 14 CLK_NBGFX 14 CLK_NBGFX# +3VS PLLVDD(NC) PLLVDD18(NC) PLLVSS(NC) VDDA18PCIEPLL1 VDDA18PCIEPLL2 CLK_NBHT CLK_NBHT# 13 AUX_CAL Strap pin C25 C24 HT_REFCLKP HT_REFCLKN E11 F11 REFCLK_P/OSCIN(OSCIN) REFCLK_N(PWM_GPIO3) T2 T1 GFX_REFCLKP GFX_REFCLKN U1 U2 GPP_REFCLKP GPP_REFCLKN V4 V3 GPPSB_REFCLKP(SB_REFCLKP) GPPSB_REFCLKN(SB_REFCLKN) B9 A9 B8 A8 B7 A7 I2C_CLK I2C_DATA DDC_DATA0/AUX0N(NC) DDC_CLK0/AUX0P(NC) DDC_CLK1/AUX1P(NC) DDC_DATA1/AUX1N(NC) B10 STRP_DATA G11 RSVD C8 GMCH_TXOUT0+ GMCH_TXOUT0GMCH_TXOUT1+ GMCH_TXOUT1GMCH_TXOUT2+ GMCH_TXOUT2- 15 15 15 15 15 15 TXOUT_U0P(NC) TXOUT_U0N(NC) TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2) TXOUT_U2P(NC) TXOUT_U2N(NC) TXOUT_U3P(PCIE_RESET_GPIO5) TXOUT_U3N(NC) B18 A18 A17 B17 D20 D21 D18 D19 GMCH_TZOUT0+ GMCH_TZOUT0GMCH_TZOUT1+ GMCH_TZOUT1GMCH_TZOUT2+ GMCH_TZOUT2- 15 15 15 15 15 15 TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1) B16 A16 D16 D17 GMCH_TXCLK+ GMCH_TXCLKGMCH_TZCLK+ GMCH_TZCLK- DAC_RSET(PWM_GPIO1) D8 A10 NB_LDTSTOP# C10 NB_ALLOW_LDTSTOP C12 14 CLK_NB_14.318M +1.1VS DAC_HSYNC(PWM_GPIO4) DAC_VSYNC(PWM_GPIO6) DAC_SCL(PCE_RCALRN) DAC_SDA(PCE_TCALRN) A12 D14 B12 NB_RESET# 1 300_0402_5% 14 14 RED(DFT_GPIO0) REDb(NC) GREEN(DFT_GPIO1) GREENb(NC) BLUE(DFT_GPIO3) BLUEb(NC) D7 E7 +VDDA18PCIEPLL 1 R319 13,18,25,26,28,30 PLT_RST# 19 NB_PWRGD G18 G17 E18 F18 E19 F19 2 715_0402_1% G14 1 +NB_PLLVDD +NB_HTPVDD +1.8VS C_Pr(DFT_GPIO5) Y(DFT_GPIO2) COMP_Pb(DFT_GPIO4) GMCH_CRT_HSYNC A11 GMCH_CRT_VSYNC B11 GMCH_CRT_CLK F8 GMCH_CRT_DATA E8 13,17 GMCH_CRT_HSYNC 13,17 GMCH_CRT_VSYNC 17 GMCH_CRT_CLK 17 GMCH_CRT_DATA 2 E17 F17 F15 A22 B22 A21 B21 B20 A20 A19 B19 VDDLTP18(NC) VSSLTP18(NC) A13 B13 VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC) A15 B15 A14 B14 VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS) C14 D15 C16 C18 C20 E20 C22 LVDS_DIGON(PCE_TCALRP) LVDS_BLON(PCE_RCALRP) LVDS_ENA_BL(PWM_GPIO2) E9 F7 G12 MIS. TMDS_HPD(NC) HPD(NC) SUS_STAT#(PWM_GPIO5) AE8 AD8 TESTMODE D13 AUX_CAL(NC) 15 15 15 15 2 L49 1 2 MBC1608121YZF_0603 +VDDLT18 1 +VDDLT18 C100 0.1U_0402_16V4Z 1 2 +1.8VS C409 2.2U_0603_6.3V4Z +VDDLTP18 2 +1.8VS 2 C414 4.7U_0805_10V4Z 1 R11 1 R12 D9 D10 R6 D12 THERMALDIODE_P THERMALDIODE_N L45 1 2 1 MBC1608121YZF_0603 +VDDLTP18 2 20_0402_5% 0_0402_5% GMCH_ENVDD 15 ENBKL 30 1 R13 2 1.27K_0402_1% C78 2.2U_0603_6.3V4Z +AVDDQ 1 2 FBM-L11-201209-300LMA30T_0805 +NB_HTPVDD L10 1 2 MBK2012221YZF 0805 1 TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC) TXOUT_L2N(DBG_GPIO0) TXOUT_L3P(NC) TXOUT_L3N(DBG_GPIO2) PART 3 OF 6 1 R14 2 1.27K_0402_1% +1.8VS AVDD1(NC) AVDD2(NC) AVDDDI(NC) AVSSDI(NC) AVDDQ(NC) AVSSQ(NC) CRT/TVOUT L25 F12 E12 F14 G15 H15 H14 PLL PWR LVTM 2 PM C135 2.2U_0603_6.3V4Z +1.8VS AVDD=100mA CLOCKs 1 L7 +AVDD1 1 2 FBM-L11-201209-300LMA30T_0805 1 C605 +1.8VS 22U_0805_6.3V6M L23 @ 2 +AVDD2 1 2 FBM-L11-201209-300LMA30T_0805 1 GMCH_CRT_R 2 133_0402_1% GMCH_CRT_G 2 150_0402_1% GMCH_CRT_B 2 150_0402_1% 1 R55 1 R52 1 R58 HDMI_DET 16 @ 1 2 @ R261 0_0402_5% 2 1 10K_0402_5% 1 2 SUS_STAT# 19 R7 0_0402_5% Strap pin SUS_STAT_R# 13 NB_THERMAL_DA 20 NB temp to NB_THERMAL_DC 20 D_DVI_DET 16,37 3 SB 1 2 R343 1.8K_0402_5% RS780M_FCBGA528 +1.8VS +1.8VS +3VS 2 +3VS +1.8VS 2 toshiba no pull high 2 @ 3 NB_LDTSTOP# 1 Q53 NB_ALLOW_LDTSTOP 1 D FDV301N_NL_SOT23-3 FDV301N_NL_SOT23-3 0_0402_5% 1 2 R506 0_0402_5% 1 2 R85 4 1 @ 3 18 ALLOW_LDTSTOP S Q2 D S 6,18 LDT_STOP# 2 G 2 R411 300_0402_5% 0_0402_5% 1 2 R406 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A R505 4.7K_0402_5% G AMD check @ 1 6 CPU_LDT_REQ# 1 @ R86 4.7K_0402_5% B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 11 of 48 A B C D E U22F 2A FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX 1 C129 1 C108 1 C128 1 C117 1 C118 2 2 2 2 22U_0805_6.3V6M 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 FOR Version A11 pop 1.35VS A12 use 1.2V_HT C51 22U_0805_6.3V6M C44 22U_0805_6.3V6M 2 C26 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE 1 1 C52 1 C45 1 C46 2 2 2 2 2 22U_0805_6.3V6M 0.1U_0402_16V4Z 1 0.6A C43 2 0.1U_0402_16V4Z 0.64A F9 G9 AE11 AD11 +1.8VS +1.8VS C398 1U_0402_6.3V4Z J10 P10 K10 M10 L10 W9 H9 T10 R10 Y9 AA9 AB9 AD9 AE9 U10 VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15 VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC) VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC) VDD33_1(NC) VDD33_2(NC) +NB_CORE default is 1.35V K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16 1 2 +NB_CORE VDD_CORE=5A 7.6A 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 + 2 L12 M14 N13 P12 P15 R11 R14 T12 U14 U11 U15 V12 W11 W15 AC12 AA14 Y18 AB11 AB15 AB17 AB19 AE20 AB21 K11 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8 VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2 1 2 AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15 RS780M_FCBGA528 AE10 AA11 Y11 AD10 AB10 AC10 H11 H12 +3VS 1 RS780M_FCBGA528 1 L2 1 2 FBMA-L11-201209-221LMA30T_0805 L1 1 2 FBMA-L11-201209-221LMA30T_0805 +1.1VS 330U_D2E_2.5VM 1 L8 2A 2 1 FBMA-L11-201209-221LMA30T_0805 1 VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13 2 20.1U_0402_16V4Z 0.1U_0402_16V4Z C10 +1.8VS AE25 AD24 AC23 AB22 AA21 Y20 W19 V18 U17 T17 R17 P17 M17 1 1 PART 6/6 C86 0.1U_0402_16V4Z 1 C55 2 2 U22D 0.1U_0402_16V4Z PAR 4 OF 6 2 3 AB12 AE16 V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14 Y14 MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC) AD16 AE17 AD17 MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC) W12 Y12 AD18 AB13 AB18 V14 MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC) V15 W14 MEM_CKP(NC) MEM_CKN(NC) AE12 AD12 SBD_MEM/DVO_I/F 1 C42 C34 C18 2 VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7 C17 L20 +1.2V_HT H18 G19 F20 E21 D22 B23 A23 2 2 2 2 22U_0805_6.3V6M 2 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1 1 1 1 C89 C127 2 2 2 2 22U_0805_6.3V6M 0.1U_0402_16V4Z C25 C41 C30 C27 22U_0805_6.3V6M C132 0.68A 1 C88 C115 1 +1.1VS 2 222U_0805_6.3V6M 22U_0805_6.3V6M 0.1U_0402_16V4Z C121 1 1.1A C79 C139 1 1 C16 1 C15 0.1U_0402_16V4Z 1 +VDDA11PCIE A6 B6 C6 D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9 C97 2A PART 5/6 VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8 VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17 0.1U_0402_16V4Z 1 FBMA-L11-201209-221LMA30T_0805 VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7 C92 2 0.1U_0402_16V4Z +VDDHTRX J17 K16 L16 M16 P16 R16 T16 0.1U_0402_16V4Z L22 0.1U_0402_16V4Z L3 1 2 FBMA-L11-201209-221LMA30T_0805 VDDA_12=2.5A U22E 2 0.1U_0402_16V4Z C54 2 2 2 2 22U_0805_6.3V6M 0.1U_0402_16V4Z C90 1 C101 0.1U_0402_16V4Z 1 C106 0.1U_0402_16V4Z 1 C103 C93 1 C102 0.1U_0402_16V4Z 1 C95 C85 FBMA-L11-201209-221LMA30T_0805 0.68A VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27 GROUND 0.1U_0402_16V4Z +VDDHT 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z L14 2A +1.1VS POWER 1 A25 D23 E22 G22 G24 G25 H19 J22 L17 L22 L24 L25 M20 N22 P20 R19 R22 R24 R25 H20 U22 V19 W22 W24 W25 Y21 AD25 MEM_COMPP(NC) MEM_COMPN(NC) MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC) MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC) MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC) MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC) MEM_DQ12(NC) MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC) AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21 MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC) MEM_DQS1P(NC) MEM_DQS1N(NC) Y17 W18 AD20 AE21 MEM_DM0(NC) MEM_DM1/DVO_D8(NC) W17 AE19 IOPLLVDD18(NC) IOPLLVDD(NC) AE23 AE24 IOPLLVSS(NC) AD23 MEM_VREF(NC) 3 +1.8VS +1.1VS AE18 1 R349 2 0_0402_5% RS780M_FCBGA528 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Rev E 401561 Sheet Thursday, September 11, 2008 E 12 of 48 A B C D E DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb 2 R337 2 R336 @ 11,17 GMCH_CRT_VSYNC 1 1 3K_0402_5% 1 3K_0402_5% Enables the Test Debug Bus using GPIO. (VSYNC) 1 : Disable (RS780) 0 : Enable (Rs780) +3VS 1 DFT_GPIO1: LOAD_EEPROM_STRAPS 1 2 @R315 @ R315 150_0402_1% D20 @ CH751H-40_SC76 2 1 11 AUX_CAL RS780 DFT_GPIO1 11 SUS_STAT_R# Selects Loading of STRAPS from EPROM 1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected RS740/RX780: DFT_GPIO1 RS780:SUS_STAT PLT_RST# 11,18,25,26,28,30 2 2 RS780 use HSYNC to enable SIDE PORT RS780 use HSYNC to enable SIDE PORT 2 R332 @ 2 R331 11,17 GMCH_CRT_HSYNC 1 3K_0402_5% 1 3K_0402_5% +3VS RS740/RS780: Enables Side port memory ( RS780 use HSYNC#) 0. Enable (RS780) 1 : Disable(RS780) 3 3 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Rev E 401561 Sheet Thursday, September 11, 2008 E 13 of 48 5 4 3 2 1 +3VS_CLK L31 1 +3VS 2 FBMA-L11-201209-221LMA30T_0805 1 +VDDCLK_IO +1.2V_HT 2 1 C256 C267 0.1U_0402_16V4Z 1 C278 22U_0805_10V4Z 2 0.1U_0402_16V4Z 2 1 0.1U_0402_16V4Z 1 C295 1 C296 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 1 C262 C274 2 0.1U_0402_16V4Z 2 1 C266 0.1U_0402_16V4Z 1 C268 2 0.1U_0402_16V4Z 1 2 1 C294 2 0.1U_0402_16V4Z 2 C297 1U_0402_6.3V4Z L32 1 0.1U_0402_16V4Z 1 C264 2 1 FBMA-L11-201209-221LMA30T_0805 C260 1 0.1U_0402_16V4Z 1 C293 1 C298 0.1U_0402_16V4Z 1 C269 C280 0.1U_0402_16V4Z 1 C263 1U CLOSE PIN 69 D D 2 2 22U_0805_10V4Z 2 0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 +VDD48 L34 L78,L79,L80,L81 change to 600@100Mhz 1 +3VS 2 FBMA-L11-201209-221LMA30T_0805 1 C287 C292 1 2.2U_0805_10V6K L33 1 +3VS 2 0.1U_0402_16V4Z +3VS_CLKVDDA 2 2 +3VS_CLK FBMA-L11-201209-221LMA30T_0805 CLK_XTAL_OUT C258 22U_0805_10V4Z 2 CLK_XTAL_IN C265 0.1U_0402_16V4Z 2 1 U15 1 R161 8.2K_0402_5% ICS 9LPRS488 49 48 VDDA GNDA 62 66 VDDREF GNDREF SB_SRC_SLOW# 41 12 18 28 37 53 VDDSRC_IO VDDSRC_IO VDDATIG_IO VDDSB_SRC_IO VDDCPU_IO CPUKG0T_LPRS CPUKG0C_LPRS 56 55 CLK_CPU CLK_CPU# HTT0T_LPRS / 66 M HTT0C_LPRS / 66 M 60 59 CLK_HTT CLK_HTT# 3 17 29 38 44 54 61 69 VDDDOT VDDSRC VDDATIG VDDSB_SRC VDDSATA VDDCPU VDDHTT VDD48 SB_SRC0T_LPRS SB_SRC0C_LPRS 40 39 SB_SRC1T_LPRS SB_SRC1C_LPRS 35 34 ATIG0T_LPRS ATIG0C_LPRS 33 32 ATIG1T_LPRS ATIG1C_LPRS 31 30 ATIG2T_LPRS ATIG2C_LPRS 26 25 SRC0T_LPRS SRC0C_LPRS 23 22 SRC1T_LPRS SRC1C_LPRS 21 20 REF0/SEL_HTT66 SRC2T_LPRS SRC2C_LPRS 16 15 CLK_SRC2 CLK_SRC2# 1 R197 1 R196 2 2 0_0402_5% 0_0402_5% CLK_PCIE_MINI1 28 CLK_PCIE_MINI1# 28 MiniCard_1 48MHz_0 SRC3T_LPRS SRC3C_LPRS 14 13 CLK_SRC3 CLK_SRC3# 1 R210 1 R209 2 2 0_0402_5% 0_0402_5% CLK_PCIE_MINI2 28 CLK_PCIE_MINI2# 28 MiniCard_2 SRC4T_LPRS SRC4C_LPRS 10 9 CLK_SRC4 CLK_SRC4# 1 R200 1 R199 2 2 0_0402_5% 0_0402_5% CLK_SBLINK_BCLK 11 CLK_SBLINK_BCLK# 11 NB A LINK SRC5T_LPRS SRC5C_LPRS 8 7 CLK_SRC5 CLK_SRC5# 1 R208 1 R207 2 2 0_0402_5% 0_0402_5% 46 45 CLK_SRC6 CLK_SRC6# SMBCLK SMBDAT 1 2 ICH_SMBCLK0 8,9,16,19,28 ICH_SMBDATA0 8,9,16,19,28 2 1 SRC_SLOW C290 1 +VDDCLK_IO 22P_0402_50V8J 2 2 22P_0402_50V8J C +3VS_CLK MiniCard1 request R165 8.2K_0402_5% 1 2 +3VS_CLK R162 8.2K_0402_5% 1 2 Routing the trace at least 10mil +VDD48 24 28 MINI1_CLKREQ# MiniCard2 request 28 MINI2_CLKREQ# 1 R178 CLKREQ1# 50 CLKREQ2# 43 CLKREQ3# 42 CLKREQ4# 2 90.9_0402_1% 1 R179 @ 1 R260 11 CLK_NB_14.318M 30 CLK_14M_SIO 2 CLK_14.318M 63 158_0402_1% 64 2 SEL_SATA 0_0402_5% SEL_HT66 65 REF2/SEL_27 1 2 2 0_0402_5% 0_0402_5% 1 R175 1 R172 R169 261_0402_1%~D @ CPU 2 2 0_0402_5% 0_0402_5% CLK_NBHT 11 CLK_NBHT# 11 CLK_ATIG0 CLK_ATIG0# 1 R174 1 R176 2 2 0_0402_5% 0_0402_5% CLK_NBGFX 11 CLK_NBGFX# 11 CLK_SRC0 CLK_SRC0# 1 R189 1 R190 2 2 0_0402_5% 0_0402_5% CLK_PCIE_LAN 26 CLK_PCIE_LAN# 26 NB GFX GLAN REF1/SEL_SATA B 71 2 R193 1 CLK_48M 70 33_0402_5% 19 CLK_48M_USB 48MHz_1 CLK_XTAL_IN 67 X1 CLK_XTAL_OUT 68 X2 2 2 R181 8.2K_0402_5% @ R187 NEW CARD SRC 2 MINI2 SRC 3 MINI1 NB CLOCK INPUT TABLE NB CLOCKS PD# R1631 R1641 CLK_PCIE_READER 25 CLK_PCIE_READER# 25 RX780 2 2 0_0402_5% 0_0402_5% CLK_SBSRC_BCLK 18 CLK_SBSRC_BCLK# 18 SB RCLK RS780 HT_REFCLKP NC 100M DIFF 100M DIFF 100M DIFF 100M DIFF REFCLK_N 14M SE (3.3V) NC 14M SE (1.8V) NC 14M SE (1.1V) vref GFX_REFCLK 100M DIFF 100M DIFF 100M DIFF(IN/OUT)* GPP_REFCLK NC 100M DIFF NC 100M DIFF 100M DIFF HT_REFCLKN Card Reader B RS740 REFCLK_P GPPSB_REFCLK 100M DIFF 57 2 R173 1 8.2K_0402_5% +3VS_CLK C601 ICS9LPRS488AKLFT_MLF72_10x10 @ 2 1U_0402_6.3V4Z R188 8.2K_0402_5% A 1 1 R182 8.2K_0402_5% LAN SRC 1 5 4 2 2 SRC7T_LPRS/27MHz_SS SRC7C_LPRS/27MHz_NS 1 SEL_SATA SEL_HT66 A SRC6T/SATAT_LPRS SRC6C/SATAC_LPRS 1 1 8.2K_0402_5% @ GNDDOT GNDSRC GNDSRC GNDATIG GNDSB_SRC GNDSATA GNDCPU GNDHTT GND48 GNDPAD SRC 0 66M SE(SINGLE END) +3VS_CLK 6 11 19 27 36 47 52 58 72 73 R167 8.2K_0402_5% @ CLK_CPU_BCLK# 6 C CLKREQ0 # 51 1 R170 1 R168 1 0.1U_0402_16V4Z 1 1 14.31818MHZ_20P_6X1430004201 1 C288 CLK_CPU_BCLK 6 2 C2772 2 SRC_SLOW 2 +3VS_CLK Y4 1 configure as single-ended 66MHz output 0* configure as differential 100MHz output 1 configure as 27M and 27M_SS output 0* configure as SRC_7 output NB_OSC_14.318M SEL_HTT66 1* 100M SATA SRC6 output 0 SPREAD 100M SATA SRC6 output Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SEL_SATA * default Date: 5 Compal Electronics, Inc. 4 3 2 SCHEMATICS, M/B S4182 Rev E 401561 Sheet Thursday, September 11, 2008 1 14 of 48 5 4 3 2 1 LCD POWER CIRCUIT +LCDVDD +3VS 1 +3VALW W=60mils 1 R279 300_0603_5% 1 2 R288 100K_0402_5% 6 D D 4.7U_0805_10V4Z R284 1 2 0_0402_5% 2N7002DW-T/R7_SOT363-6 Q27B 5 AO3413_SOT23-3 Q28 1 2 +LCDVDD W=60mils 0.047U_0402_16V7K 2 1 1 4 11 GMCH_ENVDD 1 1K_0402_5% 1 C363 3 1 2 R287 G 2 D 2N7002DW-T/R7_SOT363-6 Q27A S 3 2 2 C360 1 C362 4.7U_0805_10V4Z 2 2 C361 0.1U_0402_16V4Z 2 R282 2.2K_0402_5% demo board pop 2.7k, tuun after bring up 1 +3VS DAC_BRIG 1 C356 1 C355 1 C354 R281 INVT_PWM C 30 BKOFF# BKOFF# 1 D17 2 RB751V_SOD323 2 4.7K_0402_5% DISPOFF# DISPOFF# 2 2 2 220P_0402_50V7K 220P_0402_50V7K C 220P_0402_50V7K LCD/PANEL BD. Conn. JLVDS1 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 +INVPWR_B+ +3VS 11 GMCH_LCD_CLK 11 GMCH_LCD_DATA 11 GMCH_TZOUT011 GMCH_TZOUT0+ 11 GMCH_TZOUT1+ 11 GMCH_TZOUT111 GMCH_TZOUT2+ 11 GMCH_TZOUT2- 19 19 11 GMCH_TZCLK11 GMCH_TZCLK+ 0_0603_5% R268 1 USB20_N5 R265 1 USB20_P5 0_0603_5% 2 2 USB20_CMOS_N5 USB20_CMOS_P5 B GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 DAC_BRIG INVT_PWM DISPOFF# DAC_BRIG 30 INVT_PWM 30 +LCDVDD W=60mils GMCH_TXOUT0- 11 GMCH_TXOUT0+ 11 GMCH_TXOUT1- 11 GMCH_TXOUT1+ 11 GMCH_TXOUT2+ 11 GMCH_TXOUT2- 11 GMCH_TXCLK- 11 GMCH_TXCLK+ 11 R525 1 2 0_0603_5% +3VS 2 0_0603_5% +3VALW B ACES_88242-4001 CONN@ R526 1 @ A A +INVPWR_B+ +LCDVDD L37 2 1 KC FBM-L11-201209-221LMAT_0805 W=40mils L38 2 1 KC FBM-L11-201209-221LMAT_0805 C351 1 1 B+ +3VS 1 1 680P_0402_50V7K 68P_0402_50V8J 2 2 2 C358 1 C359 C357 C352 2 0.1U_0402_16V4Z 10U_0805_10V4Z 2 0.1U_0402_16V4Z 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 1 15 of 48 5 4 3 2 1 JHDMI1 reserve HDMI I2C ESD diode HDMI_HPD 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +HDMI_5V_OUT HDMI_SDATA HDMI_SCLK +HDMI_5V_OUT HDMI_R_CK- 1 EC_DOCKIN# 17,27,30,33,37 EC_DOCKIN# HDMI_R_CK+ HDMI_R_D0- R83 R82 6.8K_0402_5% 6.8K_0402_5% 2 3 2 1 HDMI_R_D0+ HDMI_R_D1- HDMI_SCLK HDMI_R_D1+ HDMI_R_D2- BSH111 1N_SOT23-3 Q46 1 BSH111 1N_SOT23-3 Place Q48 HDMI_SDATA HDMI_R_D2+ TYCO_1939864-1 CONN@ closed to JHDMI1 TMDS_P0_C TMDS_N0_C 1 1 2 2 1 2 1 2 2 2 2 1 2 D 1 3 2 HDMI_DET 11 U9 SN74AHCT1G125GW_SOT353-5 3 S 1 3 S S 2 G Q37 2N7002_SOT23 S 3 2 G Q38 2N7002_SOT23 3 2 G Q4 2N7002_SOT23 C174 C420 0.1U_0402_16V4Z D7 +3VS OE F1 RB491D_SC59-3 2 1 1.1A_6VDC_FUSE C172 0.1U_0402_16V4Z 2 NOTE: L : D-->A H: D-->B T28 T27 +3VS +3VS A 2 4.7K_0402_5% 2 0_0402_5% 2 4.7K_0402_5% 2 0_0402_5% 2 4.7K_0402_5% 2 0_0402_5% 2 4.7K_0402_5% 2 0_0402_5% A1 T29 A0 A1 A2 A3 49 50 51 52 A0/S4 A1/S5 A2/S6 A3/S7 A2 A3 22 C608 2 2 4 4 3 3 2 0_0402_5% HDMI_R_CK+ HDMI_TX0- 1 R373 2 0_0402_5% HDMI_R_D0- @ 1 C609 L51 1 D3-_A D3+_A D2-_A D2+_A D1-_A D1+_A D0-_A D0+_A 37 38 40 41 43 44 46 47 NC T-pad 18 57 HDMI_TX2HDMI_TX2+ HDMI_TX1HDMI_TX1+ HDMI_TX0HDMI_TX0+ HDMI_CLKHDMI_CLK+ 2 2 2 2 0.1U_0402_16V4Z MS TEST_OUT TEST_IN OE PAD @ 1 0.1U_0402_16V4Z OE 1 17 54 56 MS A0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 +3VS @ 1 R355 1Docking@ R361 @ 1 R354 1Docking@ R360 @ 1 R353 1Docking@ R359 @ 1 R352 1Docking@ R358 3 14 21 27 30 33 39 42 45 53 +3VS C607 0.1U_0402_16V4Z SCL/S3 SDA/S2 @ 1 0.1U_0402_16V4Z 19 20 8,9,14,19,28 ICH_SMBCLK0 8,9,14,19,28 ICH_SMBDATA0 25 26 28 29 31 32 34 35 2 0.1U_0402_16V4Z SEL_OUT SEL_IN D3-_B D3+_B D2-_B D2+_B D1-_B D1+_B D0-_B D0+_B 2 0.1U_0402_16V4Z 16 55 PAD PAD 1 1 1 2 2 4 4 3 3 B AVDD D0+ D0D1+ D1D2+ D2D3+ D3- @ C606 HDMI_R_CK- 1 R371 @ WCM-2012-900T_0805 HDMI_TX0+ 1 R374 2 0_0402_5% HDMI_R_D0+ HDMI_TX1- 1 R375 2 0_0402_5% HDMI_R_D1- L52 D_DVI_TXD2- 37 D_DVI_TXD2+ 37 D_DVI_TXD1- 37 D_DVI_TXD1+ 37 D_DVI_TXD0- 37 D_DVI_TXD0+ 37 D_DVI_TXC- 37 D_DVI_TXC+ 37 1 1 2 2 4 4 3 3 @ WCM-2012-900T_0805 HDMI_TX1+ 1 R376 2 0_0402_5% HDMI_R_D1+ HDMI_TX2- 1 R378 2 0_0402_5% HDMI_R_D2- AVSS 2 6 11 15 24 36 48 4 5 7 8 9 10 12 13 TMDS_CLK_C TMDS_CLK#_C TMDS_P0_C TMDS_N0_C TMDS_P1_C TMDS_N1_C TMDS_P2_C TMDS_N2_C Docking@ Docking@ 1 1 C427 C429 23 10 10 10 10 10 10 10 10 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 U26 C HDMI_CLK+ +3VS_D80 B 1 @ WCM-2012-900T_0805 1 Docking@ D26 SS1040_SOD123 1 2 C428 2 0_0402_5% 1 W=40mils 1+HDMI_5V_OUT_11 2 +5VS 1 R369 2 C426 L50 +HDMI_5V_OUT MS 2 +3VS 1Docking@ 2 R356 4.7K_0402_5% @ 1 2 R362 0_0402_5% Docking@ 2 1 D24 RB751V_SOD323 1 2 R357Docking@4.7K_0402_5% 2 1 HDMI_CLK+3VS 2 G Q36 2N7002_SOT23 0.1U_0402_16V4Z HDMI_DET +3VS R79 100K_0402_5% R363 750_0402_1% 0.1U_0402_16V4Z 4 750_0402_1% 0.1U_0402_16V4Z Y R364 R366 R365 750_0402_1% 750_0402_1% 1 5 1 A G 2 P OE# C R367 750_0402_1% D D 1 2 1 R74 2.2K_0402_5% R368 750_0402_1% D D_DVI_DET 11,37 HDMI_HPD 0.1U_0402_16V4Z 2 1 1 1 2 MP:Update HDMI Hot Plug DET circuit. C159 R370 750_0402_1% +3VS TMDS_CLK_C TMDS_CLK#_C 1 TMDS_P1_C TMDS_N1_C 1 D S TMDS_P2_C TMDS_N2_C R372 750_0402_1% 1 Docking@ 2 R80 0_0402_5% D D_DVI_SDATA 37 BSH111 1N_SOT23-3 Q49 +HDMI_5V_OUT 20 21 22 23 1 2 GMCH_DDC_DATA 11 GMCH_DDC_DATA 3 D D_DVI_SCLK 37 BSH111 1N_SOT23-3 Q47 1 S 3 1 D G 11 GMCH_DDC_DATA1 2 0_0402_5% 3 S 1 2 R259 @ 0_0402_5% GMCH_DDC_DATA 1 R258 @ 2 2 2 G G GMCH_DDC_CLK 11 GMCH_DDC_CLK1 GMCH_DDC_CLK 11 GMCH_DDC_CLK R276 2K_0402_5% D R273 2K_0402_5% S EC_DOCKIN 37 EC_DOCKIN 1 1 D 2 G 2 +HDMI_5V_OUT 1 DDC to HDMI CONN DDC to Docking HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ L53 PI3HDMI412ADZBE_TQFN56_8X8 Docking@ 1 1 2 2 4 4 3 3 A @ WCM-2012-900T_0805 SMBus Address: 1100 000X (b) HDMI_TX2+ 2007/09/14 Issued Date HDMI_R_D2+ 2 0_0402_5% Compal Electronics, Inc. Compal Secret Data Security Classification 1 R381 2007/12/25 Deciphered Date Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev E 401561 Date: 5 4 3 2 Sheet Thursday, September 11, 2008 1 16 of 48 A B C D CRT Connector D5 D3 E W=40mils D2 +5VS +R_CRT_VCC +CRT_VCC D22 1 1 1 DAN217_SC59 DAN217_SC59 DAN217_SC59 F2 2 1 1 W=40mils 2 C397 0.1U_0402_16V4Z 2 3 2 3 2 3 2 RB491D_SC59-3 1.1A_6VDC_FUSE 1 +5VS 2 1 C114 2 CRT_G_2 2 0_0805_5% CRT_B_2 1 C91 C107 @ 2 1 2 @ A 1 L6 CRT_HSYNC_2 2 FCM1608C-121T_0603 1 L4 CRT_VSYNC_2 2 FCM1608C-121T_0603 C50 1 10K_0402_5% 1 1 C35 R27 100K_0402_5% 1 @ 2 100P_0402_50V8J 100P_0402_50V8J 2 DSUB_15 C404 3 1 C28 2 1 D_CRT_HSYNC 4 P 2 +CRT_VCC 2 U2 Y 4 D_CRT_VSYNC G A OE# 1 5 2 0.1U_0402_16V4Z 2 11,13 GMCH_CRT_VSYNC CRT_DET# 19,37 DSUB_12 SN74AHCT1G125DCKR_SC70-5 1 SUYIN_070549FR015S208CR CONN@ 2 100P_0402_50V8J +CRT_VCC C38 16 17 @ U5 Y 2 G 11,13 GMCH_CRT_HSYNC @ 100P_0402_50V8J 2 OE# P 2 1 2 R15 5 C19 2 0.1U_0402_16V4Z 2 1 C83 C31 +CRT_VCC 1 1 C98 2 2 150_0402_1% 1 C130 2 0_0805_5% 1 100P_0402_50V8J 1 1 JCRT1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 5P_0402_50V8C 2 C53 L12 CRT_R_2 5P_0402_50V8C 1 L17 CRT_B_1 2 FCM2012C-800_0805 12P_0402_50V8J 2 2 150_0402_1% C104 CRT_G_1 2 FCM2012C-800_0805 1 5P_0402_50V8C 1 5P_0402_50V8C C126 2 2 R45 5P_0402_50V8C 1 1 1 L9 150_0402_1% 1 2 0_0805_5% 1 5P_0402_50V8C L15 CRT_B R57 L21 12P_0402_50V8J CRT_G R66 CRT_R_1 2 FCM2012C-800_0805 1 L18 12P_0402_50V8J CRT_R 1 1 1 +CRT_VCC 3 SN74AHCT1G125DCKR_SC70-5 Place closed to chipset D_CRT_HSYNC 37 D_CRT_VSYNC 37 1 1 +3VS R291 6.8K_0402_5% R293 2 G GMCH_CRT_R R72 GMCH_CRT_G R73 GMCH_CRT_B R70 1no docking@ 2 0_0402_5% 1no docking@ 2 0_0402_5% 1no docking@ 2 0_0402_5% CRT_R CRT_G CRT_B GMCH_CRT_DATA 11 DSUB_15 2 R296 1 D 3 BSH111 1N_SOT23-3 @ Q50 1 2 G 3 33_0402_5% 3 3 GMCH_CRT_CLK 11 S 1 S R294 1 D DSUB_12 2 2 2 6.8K_0402_5% 33_0402_5% BSH111 1N_SOT23-3 @ Q51 public board write w/o PH +5VS 1 R298 1 R297 37 D_CRT_DATA 0.1U_0402_16V4Z 1 2 C137 Docking@ U8 16,27,30,33,37 EC_DOCKIN# 11 GMCH_CRT_R 11 GMCH_CRT_G 11 GMCH_CRT_B 1 15 SEL OE# 4 7 9 12 1A 2A 3A 4A 8 VCC 16 1B1 2B1 3B1 4B1 2 5 11 14 1B2 2B2 3B2 4B2 3 6 10 13 D_CRT_R D_CRT_G D_CRT_B 37 D_CRT_CLK GMCH_CRT_DATA 2 0_0402_5% GMCH_CRT_CLK 2 0_0402_5% D_CRT_R 37 D_CRT_G 37 D_CRT_B 37 CRT_R CRT_G CRT_B GND FSAV330MTC_TSSOP16 Docking@ 4 4 NOTE: L : A-->B1 H: A-->B2 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 17 of 48 A B 1 R135 C D E 2 A_RST# @ 8.2K_0402_5% U10A +PCIE_VDDR +1.2V_HT +3VALW C235 A_RST# 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 1 1 1 2 MBC1608121YZF_0603 1 C468 5 Y 1 A U22 U21 U19 V19 R20 R21 R18 R17 PCIE_RX0P PCIE_RX0N PCIE_RX1P PCIE_RX1N PCIE_RX2P PCIE_RX2N PCIE_RX3P PCIE_RX3N PCIE_CALRP PCIE_CALRN P24 PCIE_PVDD P25 PCIE_PVSS 1 Close to SB PLT_RST# 4 PLT_RST# 11,13,25,26,28,30 NC7SZ08P5X_NL_SC70-5 3 2 Part 1 of 5 PCIE_TX0P PCIE_TX0N PCIE_TX1P PCIE_TX1N PCIE_TX2P PCIE_TX2N PCIE_TX3P PCIE_TX3N 562_0402_1% T25 2.05K_0402_1% T24 C472 1U_0402_6.3V4Z SB700 A_RST# V23 V22 V24 V25 U25 U24 T23 T22 U11 P B SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C +SB_PCIEVDD 2 2 2.2U_0805_10V6K 0.1U_0402_16V4Z 2 @ R101 20M_0402_5% @R101 1 2 C201 SB_32KHI NB_HT_CLKP NB_HT_CLKN P17 M18 CPU_HT_CLKP CPU_HT_CLKN M23 M22 SLT_GFX_CLKP SLT_GFX_CLKN J19 J18 GPP_CLK0P GPP_CLK0N L20 L19 GPP_CLK1P GPP_CLK1N M19 M20 GPP_CLK2P GPP_CLK2N N22 P22 GPP_CLK3P GPP_CLK3N L18 25M_48M_66M_OSC J21 25M_X1 SCL 1.0 suggest NC J20 4 OUT NC 3 1 IN NC 2 SB_32KHI 2 32.768KHZ_12.5P_1TJS125BJ4A421P A3 25M_X2 X1 SB_32KHO 2 SB_32KHO 18P_0402_50V8J B3 Close to SB @ 1 R530 H_PROCHOT_R# 2 10K_0402_5% 11 ALLOW_LDTSTOP 6 H_PROCHOT_R# 6 H_PWRGD 6,11 LDT_STOP# 6 LDT_RST# H_PROCHOT_R# ALLOW_LDTSTP PROCHOT# LDT_PG LDT_STP# LDT_RST# PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5/GPIO41 P4 P3 P1 P2 T4 T3 PCIRST# N1 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1# REQ2# REQ3#/GPIO70 REQ4#/GPIO71 GNT0# GNT1# GNT2# GNT3#/GPIO72 GNT4#/GPIO73 CLKRUN# LOCK# U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3 Y2 AA2 AB4 AA1 AB3 AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5 INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36 AD3 AC4 AE2 AE3 LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/GNT5#/GPIO68 BMREQ#/REQ5#/GPIO65 SERIRQ RTCCLK INTRUDER_ALERT# VBAT R124 1 2 22_0402_5% CLK_PCI_PCM 24 PCI_CLK2 PCI_CLK3 PCI_CLK4 PCI_CLK5 2 R129 PCI_AD[0..31] 22 22 22 22 1 1 33_0402_5% PCI_RST# 24 PCI_AD[0..31] PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 22,24 @ R128 8.2K_0402_5% 2 PCI_CBE#0 24 PCI_CBE#1 24 PCI_CBE#2 24 PCI_CBE#3 24 PCI_FRAME# 24 PCI_DEVSEL# 24 PCI_IRDY# 24 PCI_TRDY# 24 PCI_PAR 24 PCI_STOP# 24 PCI_REQ0# PCI_REQ0# 24 PCI_GNT0# 24 1 2 R149 0_0402_5% PM_CLKRUN# 24,30 3 PCI_PIRQE# 24 G22 CLK_LPC_EC E22 H24 H23 J25 J24 H25 H22 AB8 AD7 V15 C3 C2 B2 R108 1 2 22_0402_5% LPC_AD0 30 LPC_AD1 30 LPC_AD2 30 LPC_AD3 30 LPC_FRAME# 30 CLK_PCI_EC CLK_PCI_EC 22,30 LPCCLK1 22,30 STRAP PIN EC & Debug LPC_DRQ1# 30 +RTCBATT SERIRQ 24,30 @ 1 R107 2 1M_0402_5% RTC_CLK 22 +RTCVCC R380 1K_0402_5% STRAP PIN +RTCVCC RTC +3VS F23 F24 F22 G25 G24 X2 LPC 1 2 0_0402_5% Y2 R91 20M_0603_5% C200 NB_DISP_CLKP NB_DISP_CLKN M24 M25 CPU 2 1 1 PCIE_RCLKP/NB_LNK_CLKP PCIE_RCLKN/NB_LNK_CLKN K23 K22 @ 1 R95 18P_0402_50V8J N25 N24 PCI INTERFACE 14 CLK_SBSRC_BCLK 14 CLK_SBSRC_BCLK# 1 33_0402_5% CLOCK GENERATOR @ RTC XTAL 2 R134 3 R127 R131 L59 1 G 2 2 2 2 2 2 2 2 2 1 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N 1 1 1 1 1 1 1 1 2 10 10 10 10 10 10 10 10 C245 C246 C240 C237 C232 C233 C230 C231 1 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N 2 10 10 10 10 10 10 10 10 PCI CLKS 1 N2 PCI EXPRESS INTERFACE A_RST# D14 3 1 S D H_PWRGD H_PWRGD_L 45 FDV301N_NL_SOT23-3 2007/09/14 Issued Date 2 R379 C339 0_0603_5% for Clear CMOS 2 2008/08/02 Deciphered Date Title 1 BAS40-04_SOT23-3 +CHGRTC Compal Electronics, Inc. SCHEMATICS, M/B S4182 Date: B C 4 2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. level shift to ISL6265 A 1 @ Compal Secret Data Security Classification Q39 2 W=20mils 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 1 G 2 R382 4.7K_0402_5% 1 C436 3 1 C442 1 1U_0402_6.3V4Z +3VS +1.8VS 4 2 510_0402_5% 2 1 R385 218S7EALA11FG_BGA528_SB700 D Rev E 401561 Sheet Thursday, September 11, 2008 E 18 of 48 A B C D E U10D SB_TEST0 26,28 SB_PCIE_WAKE# 25 CR_PE# 6 H_THERMTRIP# 11 NB_PWRGD CR_PE# H_THERMTRIP# NB_PWRGD EC_RSMRST# 30 EC_RSMRST# EC_RSMRST# 2 2.2K_0402_5% AE18 AD18 25 CR_WAKE# AA19 R4041 SKUID W17 2 +3VS @ 2.2K_0402_5% V17 R4101 2.2K_0402_5% W20 2 W21 33 SB_SPKR ICH_SMBCLK0 AA18 8,9,14,16,28 ICH_SMBCLK0 ICH_SMBDATA0 W18 8,9,14,16,28 ICH_SMBDATA0 ICH_SMBCLK1 K1 6,26 ICH_SMBCLK1 ICH_SMBDATA1 K2 6,26 ICH_SMBDATA1 AA20 Y18 C1 @ Y19 1 2 +3VS R531 4.7K_0402_5% G5 CR_WAKE# 1 2 C446 @ 1U_0402_6.3V4Z +3VS 2 R496 1 R408 R399 2 10K_0402_5% CR_WAKE# 1 2 2.2K_0402_5% ICH_SMBCLK0 1 2 2.2K_0402_5% ICH_SMBDATA0 +3VALW R497 1 @ 2 10K_0402_5% CR_PE# R111 1 @ 2 2.2K_0402_5% ICH_SMBCLK1 R110 1 @ 2 2.2K_0402_5% ICH_SMBDATA1 1 R409 1 R507 EC_LID_OUT# 30 EC_LID_OUT# R119 R115 R116 R120 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 33 HDA_RST_AUDIO# 32 HDA_RST_MDC# STRAP PIN @ @ @ 1 1 2 2 1 1 2 2 R121 R125 32 HDA_SYNC_MDC 33 HDA_SYNC_AUDIO R393 2 R391 2 R112 2 30,37 DOCKIN# EC_LID_OUT# HDA_SDOUT_MDC HDA_SDOUT_AUDIO HDA_SDIN0 HDA_SDIN1 3 USB_HSD11P USB_HSD11N H11 J10 USB20_P11 USB20_N11 USB_HSD10P USB_HSD10N E11 F11 USB20_P10 USB20_N10 USB_HSD9P USB_HSD9N A11 B11 USB20_P9 USB20_N9 USB_HSD8P USB_HSD8N C10 D10 USB20_P8 USB20_N8 USB_HSD7P USB_HSD7N G11 H12 USB20_P7 USB20_N7 USB_HSD6P USB_HSD6N E12 E14 USB_HSD5P USB_HSD5N C12 D12 USB_HSD4P USB_HSD4N B12 A12 USB_HSD3P USB_HSD3N G12 G14 USB20_P3 USB20_N3 USB_HSD2P USB_HSD2N H14 H15 USB20_P2 USB20_N2 USB_HSD1P USB_HSD1N A13 B13 USB_HSD0P USB_HSD0N B14 A14 IMC_GPIO8 IMC_GPIO9 IMC_PWM0/IMC_GPIO10 SCL2/IMC_GPIO11 SDA2/IMC_GPIO12 SCL3_LV/IMC_GPIO13 SDA3_LV/IMC_GPIO14 IMC_PWM1/IMC_GPIO15 IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17 A18 B18 F21 D21 F19 E20 E21 E19 D19 E18 IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25 G20 G21 D25 D24 C25 C24 B25 C23 IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41 B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18 RSMRST# SATA_IS0#/GPIO10 CLK_REQ3#/SATA_IS1#/GPIO6 SMARTVOLT1/SATA_IS2#/GPIO4 CLK_REQ0#/SATA_IS3#/GPIO0 CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39 CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40 SPKR/GPIO2 SCL0/GPOC0# SDA0/GPOC1# SCL1/GPOC2# SDA1/GPOC3# DDC1_SCL/GPIO9 DDC1_SDA/GPIO8 LLB#/GPIO66 SMARTVOLT2/SHUTDOWN#/GPIO5 DDR3_RST#/GEVENT7# SB_PCIE_WAKE# 2 10K_0402_5% @ 2 100K_0402_5% 33 HDA_BITCLK_AUDIO 32 HDA_BITCLK_MDC 32 33 33 32 F7 E8 R117 R113 HDA_BITCLK 28 USB_OC#2 29 USB_OC#0 USB_OC#2 USB_OC#0 HDA_SDOUT HDA_SDIN0 HDA_SDIN1 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 1 1 HDA_SYNC 2 2 1 1 B9 B8 A8 A9 E5 F8 E4 USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GPM5# USB_OC4#/IR_RX0/GPM4# USB_OC3#/IR_RX1/GPM3# USB_OC2#/GPM2# USB_OC1#/GPM1# USB_OC0#/GPM0# M1 M2 J7 J8 L8 M3 L6 M4 L5 AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO42 AZ_SDIN1/GPIO43 AZ_SDIN2/GPIO44 AZ_SDIN3/GPIO46 AZ_SYNC AZ_RST# AZ_DOCK_RST#/GPM8# INTEGRATED uC 1 R389 +3VALW D3 USB_FSD12P USB_FSD12N HDARST# 2 2 22 HDARST# 10K_0402_5% 1 10K_0402_5% 1 10K_0402_5% 1 HDA_SDIN0 HDA_SDIN1 HDA_BITCLK +3VS 1 R105 @ 2 2.2K_0402_5% H19 H20 H21 F25 IMC_GPIO0 IMC_GPIO1 SPI_CS2#/IMC_GPIO2 IDE_RST#/F_RST#/IMC_GPO3 D22 E24 E25 D23 IMC_GPIO4 IMC_GPIO5 IMC_GPIO6 IMC_GPIO7 USB20_P11 28 USB20_N11 28 USB-11 Fingerprint USB20_P10 28 USB20_N10 28 USB-10 MiniCard(TV tuner) USB20_P9 29 USB20_N9 29 USB-9 Bluetooth USB20_P8 28 USB20_N8 28 USB-8 WLAN USB20_P7 29 USB20_N7 29 USB-7 M/B connector USB-6 Bluetooth USB20_P5 USB20_N5 USB20_P5 15 USB20_N5 15 2 USB-5 USB Camera USB-4 右小板 USB20_P3 37 USB20_N3 37 USB-3 DOCK USB20_P2 28 USB20_N2 28 USB-2 右小板 USB-11 Fingerprint USB20_P0 USB20_N0 USB20_P0 29 USB20_N0 29 USB-0 ICH_SCLK3 6 ICH_SDATA3 6 GPIO16 22 GPIO17 22 STRAP PIN STRAP PIN 3 +3VALW 2 SB_TEST1 EC_GA20 EC_KBRST# EC_SCI# EC_SMI# 2 R390 R412 100K_0402_5% 1 30 30 30 30 SB_TEST2 E6 E7 USB_RCOMP 1 11.8K_0402_1% 2 Q40G 2N7002_SOT23 17,37 CRT_DET# CRT_DET 1 2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5% 2 @ 2.2K_0402_5% USB_FSD13P USB_FSD13N USB OC 1 R388 1 R387 1 R392 +3VALW G8 CLK_48M_USB 14 D 3 SUS_STAT# SB_TEST2 SB_TEST1 SB_TEST0 SB700 has internal PD USB_RCOMP USB MISC SUS_STAT# PM_SLP_S3# PM_SLP_S5# PBTN_OUT# SB_PWRGD SUS_STAT# C8 USB 1.1 30 30 30 6,32 11 2@ 100P_0402_25V8K 1 USBCLK/14M_25M_48M_OSC USB 2.0 2 4.7K_0402_5% CRT_DET demo circuit LID use RI# C204 1 2 @ 100_0402_5% 1 R100 Part 4 of 5 SB700 PCI_PME#/GEVENT4# RI#/EXTEVNT0# SLP_S2/GPM9# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD SUS_STAT# TEST2 TEST1 TEST0 GA20IN/GEVENT0# KBRST#/GEVENT1# LPC_PME#/GEVENT3# LPC_SMI#/EXTEVNT1# S3_STATE/GEVENT5# SYS_RESET#/GPM7# WAKE#/GEVENT8# BLINK/GPM6# SMBALERT#/THRMTRIP#/GEVENT2# NB_PWRGD HD AUDIO 1 R395 +3VS 2 NB_PWRGD 10K_0402_5% E1 E2 H7 F5 G1 H2 H1 K3 H5 H4 H3 Y15 W15 K4 K24 F1 J2 H6 F2 J6 W14 INTEGRATED uC @ 1 R155 +3VS EC_SWI# GPIO 30 ACPI / WAKE UP EVENTS 1 S 218S7EALA11FG_BGA528_SB700 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 19 of 48 A B C D E U10B 1 1 23 SATA_DTX_C_SRX_N2 23 SATA_DTX_C_SRX_P2 SATA_X1 1 C248 1 10P_0402_50V8J 2 1 2 R150 10M_0402_5% 2 10P_0402_50V8J 2 1 C249 2 R400 SATA_X2 +3VS R401 1 31 SATA_LED# +1.2V_HT SATA_TX1P SATA_TX1N AD11 AE11 SATA_RX1N SATA_RX1P AB12 AC12 SATA_TX2P SATA_TX2N AE12 AD12 SATA_RX2N SATA_RX2P AD13 AE13 SATA_TX3P SATA_TX3N AB14 AC14 SATA_RX3N SATA_RX3P AE14 AD14 SATA_TX4P SATA_TX4N AD15 AE15 SATA_RX4N SATA_RX4P AB16 AC16 SATA_TX5P SATA_TX5N AE16 AD16 Y3 2 25MHZ_20P AE10 AD10 V12 SATA_CAL Y12 SATA_X1 SATA_X2 AA12 SATA_X2 2 10K_0402_5% W11 SATA_ACT#/GPIO67 2 C613 2.2U_0603_6.3V4Z 2 1 C506 C497 2.2U_0603_6.3V4Z 2 AA11 PLLVDD_SATA W12 XTLVDD_SATA HW MONITOR @ 1 0.1U_0402_16V4Z +PLLVDD_SATA 1 +3VS L62 C493 1U_0402_6.3V4Z 3 +XTLVDD_SATA 2 0.1U_0402_16V4Z 2 1 BLM18PG121SN1D_0603 1 C496 1 2 SATA PWR L64 2 1 BLM18PG121SN1D_0603 AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23 1 R509 +3VALW D31 SBSPI@ 2 0_0603_5% 2 1 +SB_SPI_VCC CH751H-40_SC76 @ R510 SBSPI@ SB_SPI_CS# 1 C600 U34 SBSPI@ 1 0_0402_5% 2 R513 SB_SPI_HOLD# 2 R514 0.1U_0402_16V4Z 2 SBSPI@ R511 R512 SBSPI@ SBSPI@ 1 3 7 4 @ 1 0_0402_5% CE# WP# HOLD# VSS VDD SCK SI SO 8 6 5 2 SB_SPI_CLK SB_SPI_DATAOUT SB_SPI_DATAIN 2 MX25L8005M2C-15G_SOP8 SBSPI@ SATA_RX5N SATA_RX5P SATA_CAL 1 1K_0402_1% SATA_X1 IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23 IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30 1 2 10K_0402_5% SATA_STX_DRX_P1 SATA_STX_DRX_N1 IDE_IORDY IDE_IRQ IDE_A0 IDE_A1 IDE_A2 IDE_DACK# IDE_DRQ IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3# Part 2 of 5 1 2 10K_0402_5% 2 20_0402_5% 0_0402_5% SATA_RX0N SATA_RX0P AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24 2 1 1K_0402_1% 1 R4831 R485 23 SATA_STX_R_DRX_P2 23 SATA_STX_R_DRX_N2 SATA_TX0P SATA_TX0N AB10 AC10 ATA 66/100/133 23 SATA_DTX_C_SRX_N0 23 SATA_DTX_C_SRX_P0 SB700 AD9 AE9 SPI ROM 23 SATA_STX_R_DRX_P0 23 SATA_STX_R_DRX_N0 SATA_STX_DRX_P0 SATA_STX_DRX_N0 2 20_0402_5% 0_0402_5% SERIAL ATA 1 R1521 R151 SPI_DI/GPIO12 SPI_DO/GPIO11 SPI_CLK/GPIO47 SPI_HOLD#/GPIO31 SPI_CS1#/GPIO32 G6 D2 D1 F4 F3 LAN_RST#/GPIO13 ROM_RST#/GPIO14 U15 J1 FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49 M8 M5 M7 FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52 P5 P8 R8 TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63 TEMPIN3/TALERT#/GPIO64 C6 B6 A6 A5 B5 VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60 A4 B4 C4 D4 D5 D6 A7 B7 SB_SPI_DATAIN SB_SPI_DATAOUT SB_SPI_CLK SB_SPI_HOLD# SB_SPI_CS# NB_THERMAL_DC C203 @ @ @ NB_THERMAL_DC_R 1 NB_THERMAL_DA_R R98 1 R99 2 0_0402_5% 2 0_0402_5% NB_THERMAL_DA NB_THERMAL_DC 11 1 100P_0402_50V8J 2 NB_THERMAL_DA 11 EC_THERM# 30 D25 2 1 CH751H-40_SC76 R377 2 1 100K_0402_5% ACIN 30,36,38,41 +3VS 3 +3VALW AVDD F6 AVSS G7 +SB_AVDD 1 1 2 C447 0.1U_0402_16V4Z 218S7EALA11FG_BGA528_SB700 2 L55 2 1 BLM18PG121SN1D_0603 C438 2.2U_0603_6.3V4Z 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 20 of 48 A B C D E FOR Version A11 pop 1.2VALW, A12 use 1.2V_HT 1 @ 2 C508 22U_0805_6.3V6M C494 1 @ 2 0.1U_0402_16V4Z C501 1 @ 2 0.1U_0402_16V4Z C504 1 2 0.1U_0402_16V4Z @ VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4 +PCIE_VDDR +1.2V_HT C229 1 C480 1 +1.2V_HT P18 P19 P20 P21 R22 R24 R25 PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7 AA14 AB18 AA15 AA17 AC18 AD17 AE17 AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +1.2V_SATA L63 2 1 FBMA-L11-201209-221LMA30T_0805 1 C520 C509 1 C503 1 C505 1 C511 1 2 22U_0805_6.3V6M 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z L21 L22 L24 L25 3 2 2 2 2 2 2 2 AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5 PLL 1 1 1 1 1 1 1 A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z USB I/O C202 C211 C440 C439 C448 C441 C452 SB700 L28 2 1 BLM18PG121SN1D_0603 C461 1 2 1U_0402_6.3V4Z +1.2V_CKVDD C227 1 2 1U_0402_6.3V4Z C454 2 1 0.1U_0402_16V4Z C459 2 1 0.1U_0402_16V4Z C225 1 2 10U_0805_10V4Z +1.2V_HT +3VALW S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7 A17 A24 B17 J4 J5 L1 L2 +S5_3V S5_1.2V_1 S5_1.2V_2 G2 G4 +S5_1.2V 1 R405 2 0_0805_5% 1 2 C477 22U_0805_6.3V6M 1 2 C476 2.2U_0603_6.3V4Z 1 2 C4872 1 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2 C435 1 0.1U_0402_16V4Z 2 C465 1 0.1U_0402_16V4Z C463 A10 B10 2 C208 C213 2 1 2 1 C212 1K_0402_5% AE7 +V5_VREF J16 +AVDDCK_3.3V 2 C450 2 C449 0_0603_5% 1 V5_VREF AVDDC 0_0603_5% +1.2VALW L27 AVDDCK_3.3V AVDDCK_1.2V +1.2VALW L57 +1.2_USB USB_PHY_1.2V_1 USB_PHY_1.2V_2 L26 2 1 FBMA-L11-201209-221LMA30T_0805 U10E 2 +1.2VALW 0_0805_5% 2 +1.2V_HT 0_0805_5% 2 22U_0805_6.3V6M C475 1 C462 1 C474 1 C471 1 C470 1 C466 1 1 C515 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 1U_0402_6.3V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 +AVDD_USB +3VALW @ 1 R414 1 R415 +SB_VDD POWER L61 2 1 FBMA-L11-201209-221LMA30T_0805 1 2 C228 22U_0805_6.3V6M 1 2 C495 4.7U_0805_10V4Z C467 1 2 1U_0402_6.3V4Z 2 CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4 CORE S0 Y20 AA21 AA22 AE25 CLKGEN I/O +3VS 3.3V_S5 I/O 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 2 CORE S5 1 1 1 1 1 1 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 L15 M12 M14 N13 P12 P14 R11 R15 T16 Part 3 of 5 PCI/GPIO I/O C507 C469 C484 C502 C490 C460 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 IDE/FLSH I/O 2 22U_0805_6.3V6M A-LINK I/O 1 C512 SATA I/O +3VS 1 SB700 L9 M9 T15 U9 U16 U17 V8 W7 Y6 AA4 AB5 AB21 K17 E9 +AVDDC 2 2 1 C519 1U_0603_10V4Z 1 L54 2 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 218S7EALA11FG_BGA528_SB700 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M 0.1U_0402_16V4Z 1K_0402_5% 2 C513 +AVDDCK_1.2V 0.1U_0402_16V4Z 1 1 D27 1 1 R416 +5VS 2 +3VS C437 2 1 C445 A15 B15 C14 D8 D9 D11 D13 D14 D15 E15 F12 F14 G9 H9 H17 J9 J11 J12 J14 J15 K10 K12 K14 K15 AVSS_USB_1 AVSS_USB_2 AVSS_USB_3 AVSS_USB_4 AVSS_USB_5 AVSS_USB_6 AVSS_USB_7 AVSS_USB_8 AVSS_USB_9 AVSS_USB_10 AVSS_USB_11 AVSS_USB_12 AVSS_USB_13 AVSS_USB_14 AVSS_USB_15 AVSS_USB_16 AVSS_USB_17 AVSS_USB_18 AVSS_USB_19 AVSS_USB_20 AVSS_USB_21 AVSS_USB_22 AVSS_USB_23 AVSS_USB_24 F9 +3VALW 1 AVSS_SATA_1 AVSS_SATA_2 AVSS_SATA_3 AVSS_SATA_4 AVSS_SATA_5 AVSS_SATA_6 AVSS_SATA_7 AVSS_SATA_8 AVSS_SATA_9 AVSS_SATA_10 AVSS_SATA_11 AVSS_SATA_12 AVSS_SATA_13 AVSS_SATA_14 AVSS_SATA_15 AVSS_SATA_16 AVSS_SATA_17 AVSS_SATA_18 AVSS_SATA_19 AVSS_SATA_20 H18 J17 J22 K25 M16 M17 M21 P16 CH751H-40PT_SOD323-2 2 T10 U10 U11 U12 V11 V14 W9 Y9 Y11 Y14 Y17 AA9 AB9 AB11 AB13 AB15 AB17 AC8 AD8 AE8 PCIE_CK_VSS_1 PCIE_CK_VSS_2 PCIE_CK_VSS_3 PCIE_CK_VSS_4 PCIE_CK_VSS_5 PCIE_CK_VSS_6 PCIE_CK_VSS_7 PCIE_CK_VSS_8 AVSSC GROUND U10C VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21 Part 5 of 5 AVSSCK A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24 1 2 P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25 L17 3 218S7EALA11FG_BGA528_SB700 +AVDDCK_1.2V L56 2 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z +AVDDCK_3.3V +1.2V_HT 2 1 C443 2 1 C458 L58 2 1 BLM18PG121SN1D_0603 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z 2 1 C453 2 1 C457 +3VS 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 21 of 48 B C REQUIRED STRAPS NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 PCI_CLK5 CLK_PCI_EC LPC_CLK1 BOOTFAIL TIMER ENABLED USE DEBUG STRAPS RESERVED RESERVED ENABLE PCI MEM BOOT CLKGEN ENABLED 1 RTC_CLK AZ_RST_CD# EC ENABLED INTERNAL RTC DEFAULT PULL LOW BOOTFAIL TIMER DISABLED IGNORE DEBUG STRAPS DISABLE PCI CLKGEN MEM BOOT DISABLED DEFAULT DEFAULT DEFAULT R114 10K_0402_5% 2 1 +3VALW R384 10K_0402_5% 2 1 +3VALW R89 10K_0402_5% 2 1 +3VALW R109 10K_0402_5% 2 1 +3VALW R133 10K_0402_5% 2 1 +3VS DEFAULT R141 10K_0402_5% 2 1 +3VS EC DISABLED R126 10K_0402_5% 2 1 +3VS DEFAULT GP17 GP16 Internal pull up H,H = Reserved 1 H,L = SPI ROM EXT. RTC (PD on X1, apply 32KHz to RTC_CLK) R123 10K_0402_5% 2 1 +3VS E @ @ @ @ @ @ @ @ L,H = LPC ROM (Default L,NC) L,L = FWH ROM +3VALW +3VALW R88 2.2K_0402_5% 2 1 PULL HIGH D R87 2.2K_0402_5% 2 1 A @ 18 PCI_CLK2 18 PCI_CLK3 18 PCI_CLK4 18 PCI_CLK5 18,30 CLK_PCI_EC 18,30 LPCCLK1 18 RTC_CLK 19 HDARST# 19 GPIO17 19 GPIO16 @ R94 2.2K_0402_5% 2 1 @ R93 2.2K_0402_5% 2 1 R118 10K_0402_5% 2 1 R386 2.2K_0402_5% 2 1 @ R96 10K_0402_5% 2 1 R132 10K_0402_5% 2 1 @ R106 10K_0402_5% 2 1 R137 10K_0402_5% 2 1 R122 10K_0402_5% 2 1 2 R130 10K_0402_5% 2 1 2 DEBUG STRAPS PULL LOW PCI_AD24 PCI_AD23 USE IDE PLL USE DEFAULT PCIE STRAPS RESERVED DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT USE SHORT RESET BYPASS PCI PLL BYPASS ACPI BCLK BYPASS IDE PLL USE EEPROM PCIE STRAPS 3 @ @ @ @ R142 2.2K_0402_5% 2 1 @ R147 2.2K_0402_5% 2 1 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 R156 2.2K_0402_5% 2 1 18,24 18,24 18,24 18,24 18,24 18,24 PCI_AD25 USE ACPI BCLK R157 2.2K_0402_5% 2 1 3 PCI_AD26 USE PCI PLL R145 2.2K_0402_5% 2 1 PCI_AD28 PULL HIGH PCI_AD27 USE LONG RESET R148 2.2K_0402_5% 2 1 SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23] @ 4 4 Compal Secret Data Security Classification 2007/09/14 Issued Date 2008/08/02 Deciphered Date Title Compal Electronics, Inc. SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D Rev E 401561 Sheet Thursday, September 11, 2008 E 22 of 48 A B C D E F G H 1 1 SATA ODD Conn. JSATA1 C275 C273 20 SATA_STX_R_DRX_P2 20 SATA_STX_R_DRX_N2 1 1 C259 C257 20 SATA_DTX_C_SRX_N2 20 SATA_DTX_C_SRX_P2 SATA_STX_RC_DRX_P2 SATA_STX_RC_DRX_N2 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 2 0.01U_0402_25V7K 1 1 1 R160 0.1U_0402_16V4Z 1 2 2 2 @ 1K_0402_1% +5VS Placea caps. near ODD CONN. +5VS C253 C254 1 10U_0805_10V4Z 1 2 1000P_0402_50V7K SATA_DTX_SRX_N2 SATA_DTX_SRX_P2 1 C252 2 1 2 3 4 5 6 7 GND A+ AGND BB+ GND 8 9 10 11 12 13 DP +5V +5V MD GND GND GND GND 15 14 SANTA_206401-1_13P CONN@ C255 2 2 1U_0402_6.3V4Z SATA HDD Conn. JSATA3 C299 C301 20 SATA_STX_R_DRX_P0 20 SATA_STX_R_DRX_N0 20 SATA_DTX_C_SRX_N0 20 SATA_DTX_C_SRX_P0 3 SATA_STX_RC_DRX_P0 2 0.01U_0402_25V7K SATA_STX_RC_DRX_N0 2 0.01U_0402_25V7K 0.01U_0402_25V7K SATA_DTX_C_SRX_N0C304 1 2 SATA_DTX_SRX_N0 SATA_DTX_C_SRX_P0 C307 1 2 SATA_DTX_SRX_P0 1 1 0.01U_0402_25V7K +3VS +5VS 10U_0805_10V4Z 1 1 2 +5VS 0.1U_0402_16V4Z +3VS C336 1 C331 1 C333 1 1 C614 1 C615 C318 0.1U_0402_16V4Z 2 2 2 1000P_0402_50V7K 2 C328 2 2 1U_0402_6.3V4Z 0.1U_0402_16V4Z 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 GND HTX+ HTXGND HRXHRX+ GND 3 VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND VCC12 GND 24 23 0.1U_0402_16V4Z OCTEK_SAT-22SU1G_22P_NR-T for ESD issue 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/14 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS, M/B S4182 Document Number Date: A B C D E F Rev E 401561 Thursday, September 11, 2008 G Sheet 23 H of 48 A B C D PCI_AD[0..31] 18,22 PCI_AD[0..31] PCI_CBE#[0..3] 18 PCI_CBE#[0..3] +3VS 0.1U_0402_16V4Z +5VS IDSEL SELECT POWER-ON-STRAPPING (SEE NOTE & TABLE FOR OPTIONS) 1 10U_0805_10V4Z 1 C546 PCMCIA@ 2 1 C547 1 C523 PCMCIA@ PCMCIA@ 2 2 0.1U_0402_16V4Z 1 1 PCMCIA@ 2 C532 C545 PCMCIA@ 2 0.1U_0402_16V4Z NOTE: IDSEL SELECTION! 2 THIS DEVICE UTILIZES A "SELECTABLE IDSEL" SCHEME. IDSEL CAN BE CONNECTED INTERNALLY TO ONE OF THREE PCI AD LINES OR EXTERNAL IDSEL SIGNAL. 22K TO 47K PULL-UP & PULL-DOWN RESISTORS ARE REQUIRED TO BE CONNECTED TO PINS 123 & 124 TO SELECT ONE OF THE 4 POSSIBLE IDSEL CONNECTIONS. THE TABLE BELOW SHOWS THE 4 POSSIBLE COMBINATIONS. CONFIGURING IDSEL TO BE INTERNALLY CONNECTED ALLOWS FOR A FULL PARALLEL POWER MODE. IF AN EXTERNALLY CONNECTED IDSEL IS REQUIRED THEN AN INVERTER MUST BE CONNECTED TO VPP_PGM TO CREATE VPP_VCC. VCC5# (124) VPP_PGM (123) IDSEL SELECT DOWN DOWN AD18 DOWN UP AD20 UP DOWN AD25 64 77 97 115 UP UP 1 20 33 PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_AD17 1PCMCIA@ 2 R434 100_0402_5% PIN F4 3 18 CLK_PCI_PCM 18 PCI_DEVSEL# 18 PCI_FRAME# 18 PCI_IRDY# 18 PCI_TRDY# 18 PCI_STOP# 18 PCI_PAR 33 18,30 PM_CLKRUN# PCI_REQ0# PCI_GNT0# 18 PCI_RST# PCI_PME# 4 5 6 7 8 9 10 13 14 15 16 17 18 19 21 22 28 29 30 31 34 35 36 37 38 39 40 41 42 43 44 46 127 11 12 49 50 PCI_CBE#3 PCI_CBE#2 PCI_CBE#1 PCI_CBE#0 PCMCIA@ R427 1 2 33_0402_5% 26 27 23 24 25 47 48 PCM_SPK# PCM_SPK# 18 18 51 2 3 126 120 PM_CLKRUN# 1 PCMCIA@ 2 33K_0402_5% R432 1 PCMCIA@ 2 33K_0402_5% PCMCIA@ 2 4.7U_0805_10V4Z U29 1 PCMCIA@ 2 0.1U_0402_16V4Z 1 C533 1 C536 PCMCIA@ 2 1 PCMCIA@ 2 +S1_VCC 0.1U_0402_16V4Z 1 R433 5 6 7 8 U30 +3VS C522 C534 1 PCMCIA@ 2 0.1U_0402_16V4Z 10U_0805_10V4Z 1 PCMCIA@ 2 0.1U_0402_16V4Z +3VS C551 C537 2 PCMCIA@ 1 R419 0_0402_5% 55 54 53 52 VCC5#/VCCD0#/SDATA VCC3#/VCCD1#/SCLK VPP_PGM/VPPD0/SLATCH 124 125 123 D10/CAD31 D9/CAD30 D1/CAD29 D8/CAD28 D0/CAD27 A0/CAD26 A1/CAD25 A2/CAD24 A3/CAD23 A4/CAD22 A5/CAD21 A6/CAD20 A25/CAD19 A7/CAD18 A24/CAD17 A17/CAD16 IOW#/CAD15 A9/CAD14 IORD#/CAD13 A11/CAD12 OE#/CAD11 CE2#/CAD10 A10/CAD9 D15/CAD8 D7/CAD7 D13/CAD6 D6/CAD5 D12/CAD4 D5/CAD3 D11/CAD2 D4/CAD1 D3/CAD0 103 102 101 100 99 110 109 108 106 105 104 118 95 94 93 75 73 74 71 72 70 69 68 85 84 82 83 80 81 78 79 76 S1_D10 S1_D9 S1_D1 S1_D8 S1_D0 S1_A0 S1_A1 S1_A2 S1_A3 S1_A4 S1_A5 S1_A6 S1_A25 S1_A7 S1_A24 S1_A17 S1_IOWR# S1_A9 S1_IORD# S1_A11 S1_OE# S1_CE2# S1_A10 S1_D15 S1_D7 S1_D13 S1_D6 S1_D12 S1_D5 S1_D11 S1_D4 S1_D3 A16/CCLK A23/CFRAME# A15/CIRDY# A22/CTRDY# A21/CDEVSEL# A20/CSTOP# A13/CPAR A14/CPERR# WAIT#/CSERR# INPACK#/CREQ# WE#/CGNT# RDY/IREQ#/CINT# A19/CBLOCK# WP/CCLKRUN# RESET/CRST# D2/RFU D14/RFU A18/RFU VS1/CVS1 VS2/CVS2 CD1#/CCD1# CD2#/CCD2# BVD2/LED/CAUDIO BVD1/STSCHG#/RI#/CSTSCHG 107 114 117 116 113 61 58 60 91 89 62 88 59 87 119 98 86 63 57 121 56 122 92 90 PCMCIA@ S1_A16 1 2 S1_A23 R431 33_0402_5% S1_A15 S1_A22 S1_A21 S1_A20 S1_A13 S1_A14 S1_WAIT# S1_INPACK# S1_WE# S1_RDY# S1_A19 S1_WP S1_RST S1_D2 S1_D14 S1_A18 S1_VS1 S1_VS2 S1_CD1# S1_CD2# S1_BVD2 S1_BVD1 REG#CCBE3# A12/CCBE2# A8/CCBE1# CE1/CCBE0# 111 112 66 67 S1_REG# S1_A12 S1_A8 S1_CE1# PCMCIA Socket OZ2210GN-B1_SO8 CONN@ PCI_VCC PCI_VCC PCI_VCC AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VPP_VCC/VPPD1/IDSEL C/BE3# C/BE2# C/BE1# C/BE0# PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR#/SPKR_OUT REQ# GNT# RST# PME#/RI_OUT# MF6 MF4 MF3 MF0 GND GND GND GND GND 18,30 SERIRQ 18 PCI_PIRQE# CORE_VCC CORE_VCC CORE_VCC CORE_VCC 4.7U_0805_10V4Z 1 2 3 4 VCC/VPP +3.3V VCC/VPP +3.3V VCC5# +5V VCC3# GND S1_D3 S1_CD1# S1_D4 S1_D11 S1_D5 S1_D12 S1_D6 S1_D13 S1_D7 S1_D14 S1_CE1# S1_D15 S1_A10 S1_CE2# S1_OE# S1_VS1 S1_A11 S1_IORD# S1_A9 S1_IOWR# S1_A8 S1_A17 S1_A13 S1_A18 S1_A14 S1_A19 S1_WE# S1_A20 S1_RDY# S1_A21 +S1_VCC 0.1U_0402_16V4Z C548 1 PCMCIA@ 2 C549 1 35 2 36 3 37 4 38 5 39 6 40 7 41 8 42 9 43 10 44 11 45 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 4.7U_0805_10V4Z 1 PCMCIA@ 2 +S1_VCC S1_A16 S1_A22 S1_A15 S1_A23 S1_A12 S1_A24 S1_A7 S1_A25 S1_A6 S1_VS2 S1_A5 S1_RST S1_A4 S1_WAIT# S1_A3 S1_INPACK# S1_A2 S1_REG# S1_A1 S1_BVD2 S1_A0 S1_BVD1 S1_D0 S1_D8 S1_D1 S1_D9 S1_D2 S1_D10 S1_WP S1_CD2# 32 45 65 96 128 OZ601TN_TQFP128~D 22K TO 47K PULL-UPS MUST BE PLACED ON INTA#, PME#, SERIRQ# & CLKRUN#. 4 JPCM1 GND GND DATA3 CD1# DATA4 DATA11 DATA5 DATA12 DATA6 DATA13 DATA7 DATA14 CE1# DATA15 ADD10 CE2# OE# VS1# ADD11 IORD# ADD9 IOWR# ADD8 ADD17 ADD13 ADD18 ADD14 ADD19 WE# ADD20 READY ADD21 VCC VCC VPP VPP ADD16 ADD22 ADD15 ADD23 ADD12 ADD24 ADD7 ADD25 ADD6 VS2# ADD5 RESET ADD4 WAIT# ADD3 INPACK# ADD2 REG# ADD1 BVD2 ADD0 BVD1 DATA0 DATA8 DATA1 DATA9 GND DATA2 GND DATA10 WP CD2# GND GND 2 3 (NEW) 69 70 SANTA_130601-7_LT 4 4 IN 1 Socket (HDQ70) Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/01/16 Deciphered Date 2008/01/16 Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C Rev E 401561 Thursday, September 11, 2008 D Sheet 24 of 48 5 4 3 2 1 MDIO PULL HIGH/LOW ? +3VS 40mil 0.1U_0402_16V4Z D +1.8VS +1.8VS_APVDD @ L65 1 2 MBK2012221YZF 0805 0.1U_0402_16V4Z 1 C530 1 C543 1 C525 1 C544 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 40mil 1 C538 2 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C529 1 C542 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z +3V_MCVCC 1 C524 1 C531 1 2 2 2 C535 XDWP_SDWP 1 R429 2 XD_RB 2 R421 1000P_0402_50V7K 1 10K_0402_5% D 10K_0402_5% +3VS XD_CLE U28 3 4 14 CLK_PCIE_READER# 14 CLK_PCIE_READER PCIE_ITX_C_PRX_N4 PCIE_ITX_C_PRX_P4 10 PCIE_ITX_C_PRX_N4 10 PCIE_ITX_C_PRX_P4 C527 1 C526 1 10 PCIE_PTX_C_IRX_N4 10 PCIE_PTX_C_IRX_P4 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 PCIE_PTX_IRX_N4 PCIE_PTX_IRX_P4 APRXN APRXP 11 12 APTXN APTXP 2 APREXT 8.2K_0402_5% 7 38 39 +3VS APCLKN APCLKP 9 8 15mil 1 R428 R430 30 30 D30 19 1 CR_WAKE# +3VS PCIES_EN PCIES JMB385 2 31 SEEDAT SEECLK 15 16 CR1_CD1N CR1_CD0N 17 CR1_PCTLN 21 5IN1_LED# XRSTN XTEST 13 14 40 mil 1 1 CR_PE# XDCD1#_MSCD# XDCD0#_SDCD# 2 CH751H-40PT_SOD323-2 MC_PWREN# 1K_0402_5% R491 19 CR_PE CR_PE 2 R534 1 0_0402_5% EC_CR_PE 1 2 PLT_RST# 5 10 30 DV33 DV33 DV33 DV18 DV18 19 20 44 18 37 MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 MDIO8 MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 48 47 46 45 43 42 41 40 29 28 27 26 25 23 22 NC NC NC 34 35 36 APREXT C 11,13,18,26,28,30 APVDD APV18 TAV33 APGND GND GND GND GND CR1_LEDN +1.8VS_APVDD +3VS 1 2 10K_0402_5% XDCD0#_SDCD# 1 R423 2 XDCD1#_MSCD# 1 R424 2 XD_RE 1 2 1 2 4.7K_0402_5% 4.7K_0402_5% +1.8VS_APVDD XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SDCMD_MSBS_XDWE# XDCE_SDCLK_MSCLK_R XDWP_SDWP XD_CLE XD_D4 XD_D5 XD_D6 XD_D7 XD_RE XD_RB XD_ALE R425 2XDCE_SDCLK_MSCLK 22_0402_5% 1 R508 XD_ALE R422 200K_0402_5% 200K_0402_5% C602 33P_0402_50V8K C 6 D28 24 31 32 33 XDCD0#_SDCD# 2 XDCD1#_MSCD# 3 1 DAN202UT106_SC70-3 XD_CD# C521 270P_0402_50V7K D R533 2 G Q52 1 S 3 1 C616 @ 2N7002_SOT23 JMB385-LGEZ0A_LQFP48_7X7 CR_PE 2 1M_0402_5% @ 4 IN 1 Socket Push Type(New) 2.2U_0805_10V6K Memory Card Power Switch 2 B B JREAD1 +3V_MCVCC R426 1 +3V_MCVCC XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_D4 XD_D5 XD_D6 XD_D7 2 0_0805_5% +3VS U27 1 2 3 4 @ OUT OUT OUT FLG 40mil 8 7 6 5 C541 1 1 MC_PWREN# GND IN IN EN# C528 1 3 TPS2061DRG4_SO8 R420 300_0603_5% C540 1 C539 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z @ SDCMD_MSBS_XDWE# 34 XDWP_SDWP 33 XD_ALE 35 XD_CD# 40 XD_RB 39 XD_RE 38 XDCE_SDCLK_MSCLK 37 XD_CLE 36 11 31 2 G @ 1 2 MC_PWREN# D 3 4.7U_0805_10V4Z 2 A S 32 10 9 8 7 6 5 4 Q41 2N7002_SOT23 41 42 XD-VCC XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 7 IN 1 CONN XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE 7IN1 GND 7IN1 GND SD-VCC MS-VCC 21 28 SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW 20 14 12 30 29 27 23 18 16 25 1 XDCE_SDCLK_MSCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 (MMC XD_D4 (MMC XD_D5 (MMC XD_D6 (MMC XD_D7 SDCMD_MSBS_XDWE# XDCD0#_SDCD# SD-WP-SW 2 XDWP_SDWP MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS 26 17 15 19 24 22 13 XDCE_SDCLK_MSCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XDCD1#_MSCD# SDCMD_MSBS_XDWE# +3V_MCVCC Data Data Data Data Bit Bit Bit Bit 4) 5) 6) 7) 7IN1 GND 7IN1 GND A TAITW_R015-B10-LM Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Issued Date Deciphered Date 2008/09/20 Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev E 401561 Date: 5 4 3 2 Thursday, September 11, 2008 Sheet 1 25 of 48 A 1 R301 +3V_LAN +3V_LAN R307 1 2 1_1206_1% R304 1 2 1_1206_1% 2 LAN_PME# 4.7K_0402_5% 1 R42 +3V_LAN 2 0_1206_5% C 3 +3VALW B +3V_LAN_R 1 C379 1 C383 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z +1.2V_LAN 2 4 LAN_REGCTL12 1 Q31 MMJT9435T1G_SOT223 +3V_LAN D 60mil 1 1 1 1 C381 1 C94 1 C20 C385 1 1 1 C386 1 C389 1 C387 1 C388 1 C21 1 C87 1 C109 C113 C405 10U_0805_10V4Z 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3V_LAN 2 +3V_LAN +3V_LAN R44 2 R23 FLASH@ 4.7K_0402_5% R31 1 2 0_0402_5% 2 10K_0402_5% R310 1 2 1K_0402_5% 53 VMAIN_PRSNT +3V_LAN R19 2 1K_0402_5% 54 VAUX_PRSNT 1 59 10 PCIE_ITX_C_PRX_N3 10 PCIE_ITX_C_PRX_P3 10 PCIE_PTX_C_IRX_N3 C119 1 10 PCIE_PTX_C_IRX_P3 C120 1 19,28 SB_PCIE_WAKE# 30 EC_PME# 2 2 R40 1 R43 R48 1 1 @ 5 6,19 ICH_SMBDATA1 32 PCIE_RXD_N PCIE_ITX_C_PRX_P3 31 PCIE_RXD_P PCIE_PTX_IRX_N3 25 PCIE_TXD_N 0_0402_5% LAN_RESET# 2 0_0402_5% 2 0_0402_5% R309 4.7K_0402_5% 1 2 +3V_LAN 4 GPHY_PLLVDD PCIE_ITX_C_PRX_N3 PCIE_PTX_IRX_P3 +3V_LAN 3 35 0.1U_0402_16V7K 2 LAN_PME# 26 PERST 12 WAKE LAN_SMBCLK 58 SMB_CLK LAN_SMBDATA 57 SMB_DATA SPROM_WP +3V_LAN R305 4.7K_0402_5% 1 2 +3V_LAN 2 2 1 67 66 SCLK(EECLK) SI SO(EEDATA) CS 65 63 64 62 Q30A @ 2N7002DW-T/R7_SOT363-6 R306 1 2 0_0402_5% 14 18 37 LAN_REGCTL12 XTALVDD VDDIO VDDIO VDDIO VDDIO VDDIO 23 6 15 19 56 61 +LAN_XTALVDD VDDP VDDP/DC 17 68 VDDC VDDC VDDC VDDC VDDC VDDC 5 13 20 34 55 60 BIASVDD PCIE_PLLVDD PCIE_VDD/PLL PCIE_VDD 36 30 27 33 GPIO_0(SERIAL_DO) 7 GPIO_1(SERIAL_DI) 8 GPIO_2 9 UART_MODE +3V_LAN 1 2 XTALO 1 2 R64 @ 1 0_0402_5% 1 2 3 4 A0 A1 NC GND VCC WP SCL SDA 8 7 6 5 SPROM_WP SPROM_CLK SPROM_DOUT 20mil L48 1 2 BLM18AG601SN1D_0603 +LAN_PCIEPLLVDD 1 1 C111 C395 +Lan_VDDIO_1.2 +3V_LAN C110 1 0.1U_0402_16V4Z 1 C391 0.1U_0402_16V4Z 2 C396 0.1U_0402_16V4Z 2 20mil +LAN_PCIEVDD 1 1 C112 C394 +1.2V_LAN 0.1U_0402_16V4Z 2 +1.2V_LAN L41 1 2 BLM18AG601SN1D_0603 +1.2V_LAN 3 2 4.7U_0805_10V4Z L44 +LAN_BIASVDD +LAN_PCIEPLLVDD 1 2 BLM18AG601SN1D_0603 1 +LAN_PCIEVDD +3V_LAN 20mil +LAN_AVDD 1 C22 C402 0.1U_0402_16V4Z 2 C84 0.1U_0402_16V4Z 2 +LAN_AVDDL 1 C384 2 0.1U_0402_16V4Z C390 0.1U_0402_16V4Z 2 1 1 0.1U_0402_16V4Z 2 L40 1 2 BLM18AG601SN1D_0603 +1.2V_LAN 2 4.7U_0805_10V4Z +LAN_GPHYPLLVDD 1 1 C99 C105 R60 200_0402_1% L13 1 2 +3V_LAN BLM18AG601SN1D_0603 1 20mil LAN_MIDI1+ 27 LAN_MIDI2+ 27 XTALO L16 1 2 BLM18AG601SN1D_0603 +1.2V_LAN 2 4.7U_0805_10V4Z 4 2 Y1 2 L42 1 2 BLM18AG601SN1D_0603 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z 20mil 1 R50 R51 4.7K_0402_5%4.7K_0402_5% AT24C512N-10SU-2.7_SO8 EEPROM@ +Lan_VDDIO_1.2 LAN_XTALI 1 2 R49 4.7K_0402_5% EEPROM@ U7 +Lan_VDDIO_1.2 39 +LAN_AVDDL 44 46 51 +LAN_AVDDL 69 22 2 4.7K_0402_5% FLASH@ 2 4.7K_0402_5% EEPROM@ 2 +3V_LAN 1 0.1U_0402_16V4Z 2 EEPROM@ Pop if use FLASH 1 AVDDL AVDDL/T1_P REG_GND/S_IDDQ AVDDL/T2_P AVDDL PCIE_GND/VDD E- PAD XTALO LAN_ACTIVITY# 27 2 1.18K_0402_1% +3V_LAN +3V_LAN C96 BCM5764MKML_QFN68 4 C82 0.1U_0402_16V4Z FLASH@ +3V_LAN LAN_LINK# 27 +3V_LAN 38 45 +LAN_AVDDL 52 XTALI 1 2 16 R53 39K_0402_5% +LAN_PCIEVDD 24 LAN_RDAC 1 R46 AVDD/DC AVDD/AVDDL AVDD/DC 21 If BCM5788,R150 0 ohm 2 1 R25 0_0402_5% 2 1 R17 0_0402_5% SPROM_CLK SPROM_DIN R21 1 SPROM_DOUT SPROM_CS R22 1 REGCTL12 REGCTL25/12_IO RDAC 4 LAN_XTALI LAN_SMBCLK 1 LAN_MIDI2- 27 LAN_MIDI3- 27 LAN_MIDI3+ 27 LAN_MIDI3LAN_MIDI3+ SPROM_DIN 8 7 6 5 SO GND VCC WP# AT45DB011B-SU_SO8~N FLASH@ Pop if use EEPROM LAN_SMBDATA Q30B @ 2N7002DW-T/R7_SOT363-6 R308 1 2 0_0402_5% 6,19 ICH_SMBCLK1 LINKLED SPD100LED SPD1000LED TRAFFICLED PCIE_TXD_P 10 3 6 ENERGY_DET +LAN_GPHYPLLVDD 0.1U_0402_16V7K LAN_MIDI1- 27 +LAN_AVDD SI SCK RESET# CS# LOW PWR +3VS 30 ENERGY_DET 11,13,18,25,28,30 PLT_RST# 3 SPROM_CS 2 1 1 2 3 4 1 2 R28 U3 SPROM_DOUT SPROM_CLK 2 11 @ 30 LAN_LOWPWR LAN_MIDI0- 27 LAN_MIDI0+ 27 1 29 LAN_MIDI0LAN_MIDI0+ +LAN_AVDD 2 14 CLK_PCIE_LAN 41 40 42 43 48 47 49 50 1 14 CLK_PCIE_LAN# TRD0_N PCIE_REFCLK_N TRD0_P TRD1_N/AVDD PCIE_REFCLK_P TRD1_P/T1_N TRD2_N/AVDD CLKREQ TRD2_P/T2_N TRD3_N TRD3_P 1 U4 28 EEPROM@ 4.7K_0402_5% 2 LAN_XTALO 25MHZ_20P C123 27P_0402_50V8J 1 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification C124 27P_0402_50V8J 2 2006/12/25 Deciphered Date 2007/12/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS, M/B S4182 Rev E 401561 Date: A B C Thursday, September 11, 2008 D Sheet 26 of 48 A B C D +3V_LAN 0.1U_0402_16V4Z 1 C373 C371 0.1U_0402_16V4Z Docking@ Docking@ 2 2 1 L_LAN_LINK# LAN_MIDI0+ LAN_MIDI0+ 2 A0 LAN_MIDI0- LAN_MIDI0- 3 A1 2B1 3B1 43 42 D_LAN_MDI1+ 37 D_LAN_MDI1- 37 26 LAN_MIDI1+ LAN_MIDI1+ 7 A2 4B1 5B1 37 36 D_LAN_MDI2+ 37 D_LAN_MDI2- 37 LAN_MIDI1- LAN_MIDI1- 8 A3 6B1 7B1 32 31 D_LAN_MDI3+ 37 D_LAN_MDI3- 37 26 LAN_MIDI2+ LAN_MIDI2+ 11 A4 LAN_MIDI2- LAN_MIDI2- 12 D_LAN_ACTIVITY# D_LAN_LINK# 37 26 A5 0LED1 1LED1 2LED1 22 23 52 26 LAN_MIDI3+ LAN_MIDI3+ 14 A6 0B2 1B2 46 45 L_LAN_MIDI0+ L_LAN_MIDI0- 26 LAN_MIDI3- LAN_MIDI3- 15 A7 2B2 3B2 41 40 L_LAN_MIDI1+ L_LAN_MIDI1- 26 LAN_ACTIVITY# 26 LAN_LINK# LAN_ACTIVITY# LAN_LINK# 4B2 5B2 35 34 L_LAN_MIDI2+ L_LAN_MIDI2- 19 20 54 LED0 LED1 LED2 6B2 7B2 30 29 L_LAN_MIDI3+ L_LAN_MIDI3- 0LED2 1LED2 2LED2 25 26 51 L_LAN_ACTIVITY# L_LAN_LINK# L : A-->B1 H: A-->B2 PAD_GND GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 57 3 2 C1 220P_0402_50V7K JRJ45 12 Amber LED+ 2 1 R1 1K_0402_5% L_LAN_ACTIVITY# 11 8 +3V_LAN R8 Amber LED- 7 PR4+ RJ45_MIDI1- 6 PR2- RJ45_MIDI2- 5 PR3- RJ45_MIDI2+ 4 PR3+ RJ45_MIDI1+ 3 PR2+ RJ45_MIDI0- 2 PR1- RJ45_MIDI0+ 1 PR1+ 2 10 1 1K_0402_5% 9 SHLD2 16 SHLD1 15 PR4- RJ45_MIDI3+ L_LAN_LINK# 1 6 9 13 16 21 24 28 33 39 44 49 53 55 NOTE: NC 1 RJ45_MIDI3- SEL 5 @ PSOT24C-LF-T7_SOT23-3 D19 37 +3V_LAN 17 2 @ PSOT24C-LF-T7_SOT23-3 D18 1 D_LAN_MDI0+ 37 D_LAN_MDI0- 37 1 48 47 26 16,17,30,33,37 EC_DOCKIN# 2 1 0B1 1B1 26 26 3 2 56 50 38 27 18 10 4 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 1 L_LAN_ACTIVITY# U1 PI3L500-AZFEX_TQFN56_11X5 Docking@ Guide Pin 2 SHLD2 14 SHLD1 13 Green LEDGreen LED+ FOX_JM36113-L2R8-7F CONN@ C3 LAN_ACTIVITY# LAN_LINK# 1 R481 1no docking@ 2 0_0402_5% L_LAN_ACTIVITY# R482 1no docking@ 2 0_0402_5% L_LAN_LINK# 2 220P_0402_50V7K RJ45_GND 1 LANGND 1 2 C9 1000P_1206_2KV7K 1 C8 2 2 40mil C2 4.7U_0805_10V4Z 0.1U_0402_16V4Z 3 3 T1 LAN_MIDI0+ R3031no docking@ 2 0_0402_5% LAN_MIDI0- R3021no docking@ 2 0_0402_5% L_LAN_MIDI0+ L_LAN_MIDI0- LAN_MIDI1+ R3001no docking@ 2 0_0402_5% LAN_MIDI1- R2991no docking@ 2 0_0402_5% L_LAN_MIDI1+ L_LAN_MIDI1- LAN_MIDI2+ R2951no docking@ 2 0_0402_5% LAN_MIDI2- R2921no docking@ 2 0_0402_5% L_LAN_MIDI2+ L_LAN_MIDI2- LAN_MIDI3+ R2901no docking@ 2 0_0402_5% LAN_MIDI3- R2891no docking@ 2 0_0402_5% L_LAN_MIDI3+ L_LAN_MIDI3- 1 2 3 4 5 6 7 8 9 10 11 12 TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 24 23 22 21 20 19 18 17 16 15 14 13 RJ45_MIDI0+ RJ45_MIDI0LAN_ACTIVITY# 1 2 C367 68P_0402_50V8J @ LAN_LINK# 1 2 C368 68P_0402_50V8J @ RJ45_MIDI1+ RJ45_MIDI1RJ45_MIDI2+ RJ45_MIDI2RJ45_MIDI3+ RJ45_MIDI3- 350uH_GSL5009LF 1 1 For EMI C364 1 C366 1 C369 1 R4 75_0402_1% C370 R5 75_0402_1% 2 4 2 0.1U_0402_16V4Z 2 2 1 1 2 R3 75_0402_1% 2 4 2 1 0.1U_0402_16V4Z 2 R2 75_0402_1% 0.1U_0402_16V4Z RJ45_GND 0.1U_0402_16V4Z 40mil Place close to TCT pin Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2006/12/25 Deciphered Date 2007/12/25 Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Rev E 401561 Date: A B C Thursday, September 11, 2008 D Sheet 27 of 48 A B C D For Wireless LAN +3VS For TV-Tuner/HW MPEG +1.5VS +3VS +3VS 1 2 1 C335 4.7U_0805_10V4Z 2 1 C332 0.1U_0402_16V4Z 2 E 1 C550 4.7U_0805_10V4Z 2 1 C337 0.1U_0402_16V4Z 2 1 C552 0.1U_0402_16V4Z C334 1 0.1U_0402_16V4Z 2 2 +1.5VS C327 mini2@ 4.7U_0805_10V4Z 1 2 1 C341 mini2@ 0.1U_0402_16V4Z 2 +5VS C329 mini2@ 4.7U_0805_10V4Z 1 2 C317 mini2@ 0.1U_0402_16V4Z 1 2 C330 mini2@ 0.1U_0402_16V4Z 1 2 C590 mini2@ 0.1U_0402_16V4Z +5VS 1 1 Jmini1 R234 1 @ 2 0_0402_5% WLAN_BT_DATA WLAN_BT_CLK 14 CLK_PCIE_MINI1# 14 CLK_PCIE_MINI1 10 PCIE_PTX_C_IRX_N2 10 PCIE_PTX_C_IRX_P2 10 PCIE_ITX_C_PRX_N2 10 PCIE_ITX_C_PRX_P2 +3VS 0_0402_5% R231 1 2 30 E51RXD_P80CLK E51TXD_P80DATA_R E51RXD_P80CLK 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 SB_PCIE_WAKE# 1 @ 2 R467 0_0402_5% +3VS +1.5VS 14 MINI2_CLKREQ# 14 CLK_PCIE_MINI2# 14 CLK_PCIE_MINI2 WL_OFF# PLT_RST# R233 1 R232 1 WL_OFF# 30 PLT_RST# 11,13,18,25,26,30 +3VS 10 PCIE_PTX_C_IRX_N1 +3VALW 10 PCIE_PTX_C_IRX_P1 2 0_0603_5% 2 0_0603_5% @ ICH_SMBCLK0 ICH_SMBDATA0 ICH_SMBCLK0 8,9,14,16,19 ICH_SMBDATA0 8,9,14,16,19 10 PCIE_ITX_C_PRX_N1 10 PCIE_ITX_C_PRX_P1 USB20_N8 19 USB20_P8 19 +3VS (MINI1_LED#) MINI1_LED# 31 (9~16mA) R517 100K_0402_5% @ 1 3 5 7 9 11 13 15 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 FOX_AS0B226-S99N-7F CONN@ 53 54 55 56 53 54 55 56 G1 G2 G3 G3 2 1 3 5 7 9 11 13 15 2 30 E51TXD_P80DATA 1 3 5 7 9 11 13 15 +3VS +1.5VS PLT_RST# ICH_SMBCLK0 ICH_SMBDATA0 USB20_N10 19 USB20_P10 19 (MINI1_LED#) 2 G1 G2 G3 G3 29 WLAN_BT_DATA 29 WLAN_BT_CLK 14 MINI1_CLKREQ# 1 SB_PCIE_WAKE# 19,26 SB_PCIE_WAKE# Jmini2 5.2 mm 高 FOX_AS0B226-S99N-7F CONN@ +3VALW 9.2 mm 高 Mini Card Power Rating Auxiliary Power (mA) Normal Peak Normal +3VS 1000 750 +3V 330 250 250 (wake enable) +1.5VS 500 375 5 (Not wake enable) Fingerprint Conn 1 R527 2 +3VS @ R528 0_0603_5% 2 +3VALW 1 Primary Power (mA) 0_0603_5% Power 3 3 JP7 19 19 USB20_N11 USB20_P11 USB20_N11 USB20_P11 C226 0.1U_0402_16V4Z 2 1 6 5 4 3 2 1 To USB/B Connector 1 2 3 GND 4 GND 5 6 7 8 ACES_85201-04051 CONN@ 80mil JP9 9 10 G2 G1 4 3 2 1 1 2 3 4 5 6 7 8 +5VALW SYSON# USB20_N2 USB20_P2 29,36,37,44 USB20_N2 19 USB20_P2 19 USB_OC#2 19 ACES_87212-08G0L CONN@ D9 USB20_N11 +5VALW C365 1 +3VS 4.7U_0805_10V4Z 2 4 6 CH3 5 Vp 4 CH4 CH2 3 Vn 2 CH1 1 4 USB20_P11 CM1293-04SO_SOT23-6 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 28 of 48 A B C D E 1 1 2 2 +USB_VCCA +USB_VCCA +USB_VCCA W=80mils 1 + 2 R139 Bluetooth Conn. 150U_D2_6.3VM 2 @ 2 1 C456 470P_0402_50V7K 2 0_0402_5% R143 L29 +3VS 19 USB20_N0 USB20_P0 USB20_N0 USB20_P0 1 4 JUSB1 1 2 4 3 2 3 USB20_N0_1 USB20_P0_1 WCM2012F2S-900T04_0805 1 C324 C325 3 D G 2 C326 1 @ 2 0_0402_5% 1U_0603_10V4Z 2 AO3413_SOT23-3 Q15 1 2 3 4 VCC DD+ GND 5 6 7 8 GND1 GND2 GND3 GND4 19 USB20_N7 19 USB20_P7 USB20_N7 470P_0402_50V7K 1 @ 2 0_0402_5% USB20_P7 4 4 3 3 1 1 L30 2 2 R146 1 @ 2 JUSB2 USB20_N7_1 USB20_P7_1 0_0402_5% 1 2 3 4 VCC DD+ GND 5 6 7 8 GND1 GND2 GND3 GND4 SUYIN_020173MR004G565ZR CONN@ SUYIN_020173MR004G565ZR CONN@ 3 D10 USB20_P7_1 6 CH3 5 Vp W=40mils CH2 3 Vn 2 CH1 1 USB20_N0_1 +BT_VCC 0.1U_0402_16V4Z +USB_VCCA 1 C314 R220 300_0603_5% 4.7U_0805_10V4Z 2 0.1U_0402_16V4Z 1 2 USB20_P0_1 4 CH4 +3VALW D Q14 2N7002_SOT23 2 G 3 USB20_N7_1 CM1293-04SO_SOT23-6 +5VALW S U12 C247 1 2 3 4 1 GND IN IN EN# +USB_VCCA 80mil 8 7 6 5 OUT OUT OUT FLG 1 C312 1 R418 100K_0402_5% 2 BT_ON# 2 10K_0402_5% S 30 3 1 R228 1 R136 0.1U_0402_16V4Z W=80mils C518 WCM2012F2S-900T04_0805 19 +3VALW 1 1 C464 R417 1 2 10K_0402_5% USB_OC#0 19 TPS2061DRG4_SO8 +BT_VCC 4.7U_0805_10V4Z 2 JP10 4 19 19 1 2 3 4 5 6 7 8 USB20_P9 USB20_N9 28 WLAN_BT_DATA 28 WLAN_BT_CLK 1 GND 2 3 4 5 6 7 8 GND 9 1 28,36,37,44 SYSON# C516 0.1U_0402_16V4Z 2 4 10 ACES_87213-0800G CONN@ 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification for 線材,7, 8pin不打 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 29 of 48 4 3 2 1 For EC Tools +3VALW L36 2 2 0.1U_0402_16V4Z +3VALW EC_PME# 2 10K_0402_5% 1 2 3 4 1 2 3 4 KSO[0..17] 31 0.1U_0402_16V4Z VR_ON 2 1 100K_0402_5% 2 TP_CLK 4.7K_0402_5% 2 TP_DATA 4.7K_0402_5% +5VALW 1 R211 1 R214 1 R215 1 R212 EC_SMB_CK1 2 4.7K_0402_5% EC_SMB_DA1 2 4.7K_0402_5% EC_SMB_CK2 2 4.7K_0402_5% EC_SMB_DA2 2 4.7K_0402_5% 6,39 6,39 6 6 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 1 R186 2 4.7K_0402_5% PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# 26 EC_PME# 26 ENERGY_DET 35 FAN_SPEED1 29 BT_ON# +5VS 32 ON/OFF 31 PWR_SUSP_LED 31 NUM_LED# +3VS JP28 A EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 77 78 79 80 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 EC_CRY1 EC_CRY2 EC_MUTE SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 97 98 99 109 3S/4S# 65W/90W# SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# 119 120 126 128 EC_SPICLK EC_SPICS#/FSEL# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 73 74 89 90 91 92 93 95 121 127 FSTCHG BATT_GRN_LED# CAPS_LED# BATT_AMB_LED# PWR_LED SYSON VR_ON ACIN EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 GPO BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 100 101 102 103 104 105 106 107 108 PS2 Interface 122 123 SPI Flash ROM GPIO SM Bus PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A 2 0_0402_5% 2 0_0402_5% GPI PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 110 112 114 115 116 117 118 V18R 124 XCLK1 XCLK0 R218 KB926QFB1_LQFP128_14X14 2 DAC_BRIG 15 EN_DFAN1 35 IREF 41 CALIBRATE# 41 1 AD_PID0 1 R217 100K_0402_5% EC_MUTE 34 LAN_LOWPWR 26 C308 0.1U_0402_16V4Z 2 C DOCKIN# 19,37 BT_LED# 31 TP_CLK 31 TP_DATA 31 TP_CLK TP_DATA @ 3S/4S# 41 65W/90W# 41 EC_VLDT_EN 32 +3VALW 65W/90W# 2 R184 EC_CR_PE 25 EC_SI_SPI_SO 31 EC_SO_SPI_SI 31 EC_SPICLK 31 EC_SPICS#/FSEL# 31 R226 100K_0402_5% Ra FSTCHG 41 BATT_GRN_LED# 31 CAPS_LED# 31 BATT_AMB_LED# 31 PWR_LED 31 SYSON 36,43 VR_ON 45 ACIN 20,36,38,41 EC_PWROK BKOFF# WL_OFF# ENBKL EAPD SUSP# PBTN_OUT# 1 AD_BID0 1 R225 33K_0402_5% Rb EC_RSMRST# 19 EC_LID_OUT# 19 EC_ON 32 EC_SWI# 19 EC_PWROK 32 BKOFF# 15 WL_OFF# 28 WL_SW# 31 EC_DOCKIN# 16,17,27,33,37 EC_LID_OUT# EC_ON 1 100K_0402_5% +3VALW C316 2 0.1U_0402_16V4Z B EC_CRY1 EC_CRY2 2 2 C283 VGATE 45 ENBKL 11 EAPD 33 EC_THERM# 20 SUSP# 32,36,44 PBTN_OUT# 19 BT_SW# 31 1 1 C282 15P_0402_50V8J X1 32.768KHZ_12.5P_MC-306 C284 4.7U_0805_10V4Z 2 BATT_TEMP 20mil L35 ECAGND 2 1 FBM-L11-160808-800LMT_0603 BATT_OVP ACIN C322 2 C323 2 C285 2 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 A LPCCLK1 18,22 Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/14 Issued Date Deciphered Date 2007/12/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. ACES_85201-20051 @ Date: 5 Analog Project ID definition, JALC0 =>1 JALB0 =>0 1 25 15P_0402_50V8J LPC_DRQ1# 18 PLT_RST# R263 1 R262 1 SERIRQ CR_PE AD_PID0 SPI Device Interface GND GND GND GND GND CLK_14M_SIO 14 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# 83 84 85 86 87 88 11 24 35 94 113 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F +3VALW 2 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED NUM_LED# DAC_BRIG EN_DFAN1 IREF DA Output 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 EC_PME# 68 70 71 72 BATT_OVP 41 ADP_I 41 100K_0402_5% B 19 19 19 31 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F AD_BID0 3S/4S# BATT_TEMP 39 1 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 +5VS 1 R205 1 R201 EC_SCI# 41 ECAGND 2 1 C321 0.01U_0402_16V7K IN C 19 EC_SCI# 18,24 PM_CLKRUN# 2 1 R224 47K_0402_5% 2 1 C320 0.1U_0402_16V4Z AD ACOFF NC +3VALW PLT_RST# PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D BATT_TEMP BATT_OVP 2 11,13,18,25,26,28 12 13 37 20 38 BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 63 64 65 66 75 76 PWM Output INVT_PWM 15 BEEP# 33 2 18,22 CLK_PCI_EC INVT_PWM BEEP# 1 LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 21 23 26 27 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 2 1 @ 33_0402_5% GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & MISC 1 R206 2 1 2 3 4 5 7 8 10 AGND C303 @ 22P_0402_50V8J 2 1 19 EC_GA20 19 EC_KBRST# 18,24 SERIRQ 18 LPC_FRAME# 18 LPC_AD3 18 LPC_AD2 18 LPC_AD1 18 LPC_AD0 69 LID_SW# 1 100K_0402_5% E51RXD_P80CLK 28 E51TXD_P80DATA 28 D R518 2 R213 Place on RAM door E51RXD_P80CLK E51TXD_P80DATA ACES_85205-0400 @ AVCC @ 1 R216 VCC VCC VCC VCC VCC VCC U16 KSO[0..17] C313 31 67 9 22 33 96 111 125 D KSI[0..7] 4 C300 JP11 KSI[0..7] OUT C309 2 2 0.1U_0402_16V4Z +3VALW 1 2+EC_VCCA 2 FBM-L11-160808-800LMT_0603 1 C281 C279 1000P_0402_50V7K 1000P_0402_50V7K 1 1 2 0.1U_0402_16V4Z 1 2 NC 0.1U_0402_16V4Z 1 C289 1 C319 ECAGND 1 3 5 4 3 2 SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 Sheet 1 30 of 48 C302 1 1 R198 0_0603_5% +3VALW 2 0.1U_0402_16V4Z U18 +SPI_VCC U19 30 EC_SPICS#/FSEL# EC_SPICS#/FSEL# 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD# R223 1 R202 1 +3VALW 1 3 7 4 EC_SPICS#/FSEL# SPI_WP# SPI_HOLD# @ CE# WP# HOLD# VSS 8 6 R203 1 5 R204 1 2 R222 1 VDD SCK SI SO 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% 1 3 7 4 EC_SPICLK 30 EC_SO_SPI_SI 30 EC_SI_SPI_SO 30 KSI[0..7] To TP/B Conn. +SPI_VCC EC_SPICLK EC_SO_SPI_SI EC_SI_SPI_SO 8 6 5 2 CONN@ ACES_85201-0605 +5VS 30 30 Reserved for BIOS simulator. Footprint SO8 KSI[0..7] KSO[0..17] VDD SCK SI SO MX25L1005AMC-12G_SOP8 MX25L8005M2C-15G_SOP8 INT_KBD Conn. SBSPI@ CE# WP# HOLD# VSS 1 C223 30 100P_0402_50V8J KSO[0..17] 30 1 2 3 4 5 6 JP13 TP_CLK TP_DATA LEFT_BTN# RIGHT_BTN# 1 TP_CLK TP_DATA 2 2 C224 100P_0402_50V8J JP15 TP_DATA (Right) 28 27 +5VS TP_CLK 3 C222 D8 @ PSOT24C_SOT23 0.1U_0402_16V4Z JALA0 To POWER/B(BTN/B) +3VALW +5VS CONN@ ACES_85201-1205 12 11 10 9 8 7 6 5 4 3 2 1 JP16 ACES_88747-2601 CONN@ LEFT_BTN# 3 SW1 SMT1-05-A_4P 1 RIGHT_BTN#3 SW2 SMT1-05-A_4P 1 4 2 4 2 +5VALW KSO0 KSI2 KSI3 KSI4 LID_SW# PWR_SUSP_LED# PWR_LED# 5 6 KSO0 G2 KSO1 G1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 2 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 5 6 (Left) 30 +5VS ON/OFFBTN# 32 PWR_LED# C215 PWR_SUSP_LED# 1 2 1 2 100P_0402_50V8J KSO12 C68 1 2 100P_0402_50V8J KSO4 C60 1 2 100P_0402_50V8J KSI0 C72 1 2 100P_0402_50V8J KSO3 C59 1 2 100P_0402_50V8J KSO11 C67 1 2 100P_0402_50V8J KSI4 C76 1 2 100P_0402_50V8J KSO10 C66 1 2 100P_0402_50V8J KSO2 C58 1 2 100P_0402_50V8J KSI1 C73 1 2 100P_0402_50V8J KSO1 C57 1 2 100P_0402_50V8J KSI2 C74 1 2 100P_0402_50V8J KSO0 C56 1 2 100P_0402_50V8J KSO9 C65 1 2 100P_0402_50V8J KSI5 C77 1 2 100P_0402_50V8J KSI3 C75 1 2 100P_0402_50V8J KSI6 C49 1 2 100P_0402_50V8J KSO8 C64 1 2 100P_0402_50V8J KSI7 C80 1 2 100P_0402_50V8J Compal Footprint 2 4 453_0402_1% R249 2 240_0402_5% 2 1 R256 100K_0402_5% JP17 1 2 3 4 5 6 7 8 9 10 C209 KSO0 KSI1 KSI5 KSI6 KSI7 0.1U_0402_16V4Z CAPS_LED# 30 NUM_LED# 30 MEDIA_LED# +3VS +3VS KSO0 PWR_LED# MEDIA_LED# KSI1 PRESENTATION KSI2 Program_BTN# EMAIL_BTN# KSI4 IE_BTN# KSI5 E-KEY_BTN# KSI6 SYNC KSI7 LOCK 2 240_0402_5% 3 BATT_AMB_LED# BATT_AMB_LED# 30 1 BATT_GRN_LED# BATT_GRN_LED# 30 5IN1_LED# 25 4 SATA_LED# 20 +3VS +3VALW Wireless SWITCH D15 DAN217_SC59 @ BT SWITCH +3VALW D16 DAN217_SC59 @ R247 100K_0402_5% 2 R251 A 2 4 453_0402_1% YG +5VALW 1 R252 1 3 +3VALW 1 KSI3 R492 10K_0402_1% @ 6 Q6B 2N7002DW-T/R7_SOT363-6 HT-297DQ-GQ_AMB-YG +5VALW R246 100K_0402_5% Q6A 2N7002DW-T/R7_SOT363-6 PWR_SUSP_LED# 2N7002DW-T/R7_SOT363-6 Q22B 5 30 PWR_SUSP_LED ACES_85201-10051 CONN@ LED1 15" ONLY 2N7002DW-T/R7_SOT363-6 Q22A 2 PWR_LED +3VALW WL_SW# +3VALW R248 100K_0402_5% 30 BT_SW# 30 2 0_0402_5% MINI1_LED# 28 5 5 SW3 2 1 5 6 2 3 2 4 4 3 2 5 6 6 HSS110_4P HSS110_4P (BLUE) LED3 300_0402_5% 6 SW4 R255 +5VS 4 3 2 1 1 R253 HT-191UD_Amber_0603 150_0402_5% 4 1WL_R_LED# 2 1 (AMB) LED4 1 3 2 2 R254 +3VS 1 LED2 1 1 +5VS 3 YG 1 R250 A 3 30 +5VS HT-297DQ-GQ_AMB-YG +5VALW 4 To FUN/B(LED/B) 3 100P_0402_50V8J 4 2 2 1 C61 1 C62 KSO5 1 KSO6 100P_0402_50V8J 2 100P_0402_50V8J 3 2 1 1 C69 2 C70 KSO13 1 KSO14 2 100P_0402_50V8J 2 2 5 1 1 C63 2 KSO7 1 100P_0402_50V8J 1 2 3 1 2 C71 6 0.1U_0402_16V4Z KSO15 1 HT-191NBQA_BLUE_0603 BT_LED# Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification BT_LED# 30 2007/09/14 Deciphered Date 2007/12/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 Sheet 31 of 48 A B C D E Power Button ON/OFF switch HDA MDC Conn. +3VALW TOP Side R227 R229 +3VALW 1 2 @ 10K_0603_5% 1 2 @ 10K_0603_5% 2 1 R221 100K_0402_5% D13 ON/OFFBTN# 2 ON/OFF 30 3 51_ON# 38 1 19 HDA_SYNC_MDC 19 HDA_SDIN1 19 HDA_RST_MDC# R235 1 2 HDA_SDIN1_MDC 33_0402_5% 1 3 5 7 9 11 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 2 4 6 8 10 12 1 R237 HDA_BITCLK_MDC 19 R236 0_0402_5% C315 2 D12 ACES_88018-124G CONN@ 2 GND GND GND GND GND GND 13 14 15 16 17 18 1 @SW5 @ SW5 SMT1-05-A_4P 1 3 4 1U_0603_10V4Z +3VALW DAN202UT106_SC70-3 2 2 2 0_0402_5% 1 C340 1 31 ON/OFFBTN# 19 HDA_SDOUT_MDC 1 Bottom Side 1 20mil JMDC1 1 C338 Connector for MDC Rev1.5 RLZ20A_LL34 2 22P_0402_50V8J 1 2 6 5 1000P_0402_50V7K 1 EC_ON EC_ON For EMI D Q16 2 G 3 2 30 R230 S 2N7002_SOT23 10K_0402_5% 2 1 2 Power ON Circuit For South Bridge +3VS +3VALW 1 +3VALW S 14 P G 2 3 I @ @C291 @ C291 1U_0805_25V4Z O 4 1 R191 2 @ 0_0402_5% SB_PWRGD 6,19 @ 7 2 G @ Q10 2N7002_SOT23 O 7 SUSP 3 36 I 2 U14B SN74LVC14APWLE_TSSOP14 G 2 1 1 D U14A SN74LVC14APWLE_TSSOP14 P 14 @ R192 180K_0402_5% 1 30 1 R194 EC_PWROK 2 0_0402_5% 3 3 +3VS For +1.2HT +3VALW 1 +3VALW O 6 9 14 I @ 8 2 0_0402_5% VLDT_EN 36,42,43 1 R166 2 0_0402_5% 14 U14F SN74LVC14APWLE_TSSOP14 P 14 @ +3VALW U14E SN74LVC14APWLE_TSSOP14 P 13 I O G O 10 7 @ 12 @ 7 I G 11 1 R171 @ 30 EC_VLDT_EN 1 +3VALW 4 O G I 7 0.1U_0402_16V4Z 2 G @ C286 U14D SN74LVC14APWLE_TSSOP14 P P 5 2 RB751V_SOD323 U14C SN74LVC14APWLE_TSSOP14 7 SUSP# 1 30,36,44 SUSP# 10K_0402_1% D11 2 @ 14 @ R195 4 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 32 of 48 A B C D E F G H 1 +VDDA R462 10K_0402_5% 1 2 +5VAMP C589 1 +5VS 2 1U_0402_6.3V4Z R464 10K_0402_5% 2 1 2 560_0402_5% 1 1U_0402_6.3V4Z C573 1 1U_0402_6.3V4Z BEEP# 2 1 2 1 R466 Q43 2 B E 3 560_0402_5% 1 R451 BYP 4 G9191-475T1U_SOT23-5 1 2 C587 4.75V C591 2 ALC268 2SC2411K_SOT23 268@ 888VC@ MIC2_VREFO 2 560_0402_5% D29 RB751V_SOD323 10mil HD Audio Codec 2 2 R454 10K_0402_5% C560 L66 MBK1608121YZF_0603 1 2 +3VS_DVDD 1 R443 2.2K_0402_5% +3VS 15mil 1 C557 10U_0805_10V4Z 0.1U_0402_16V4Z 2 2 INT_MIC_R 1 +AVDD_HDA C570 15 INT_MIC C580 C581 34 LINE_L-SURR_L C584 34 LINE_R-SURR_R 34 MIC1_L 34 MIC1_R C585 C582 C583 1 MIC2_C_L 16 4.7U_0805_6.3V6K MIC2_C_R 17 4.7U_0805_6.3V6K LINE_C_L 23 4.7U_0805_6.3V6K LINE_C_R 24 4.7U_0805_6.3V6K 18 2 1 2 1 2 1 2 1 2 1 2 +3VS 16,17,27,30,37 EC_DOCKIN# 34 HP_PLUG# R472 2 1 39.2K_0402_1% LINEIN_PLUG# MIC_PLUG# R475 1 R447 2 2 10K_0402_1% 1 20K_0402_1% 37 SENSE_A 30 SPDIF EAPD 1 R438 2 34 LINEIN_PLUG# 34 MIC_PLUG# HP_PLUG# Impedance R444 0_0402_5% 268@ Codec Signals 39 MIC2_R HP_OUT_R 41 LINE1_L NC 45 LINE1_R 46 20 CD_R NC 44 19 CD_GND 6 SDATA_IN 8 AMP_RIGHT 34 JP23 HP_LEFT-FRONT_LEFT 34 HP_RIGHT-FRONT_RIGHT HP_RIGHT-FRONT_RIGHT INT_MIC_R 1 R498 34 1 2 3 4 2 0_0603_5% D6 SM05T1G_SOT23-3 @ 1 R445 2 1 10_0402_5% For EMI 2 C566 22P_0402_50V8J HDA_BITCLK_AUDIO MIC1_R PCBEEP MONO_OUT 29 GPIO1 31 MIC1_VREFO_L 28 SYNC SDATA_OUT 47 EAPD G1 G2 5 6 R499 0_0603_5% 19 HDA_SDIN0_AUDIO MIC1_VREFO_R 32 MIC2_VREFO 30 VREF 27 JDREF 40 NC 33 AVSS1 AVSS2 26 42 SPDIFO DVSS1 DVSS2 1 2 R446 33_0402_5% HDA_SDIN0 19 37 LINE1_VREFO RESET# GPIO0 GPIO3 SENSE A SENSE B 1 2 3 4 ACES_88266-04001 CONN@ MIC1_L 2 3 13 34 2SPDIF_R 48 0_0402_5% 4 7 BIT_CLK AMP_LEFT 34 3 10mil MIC1_VREFO_L MIC1_VREFO_R MIC2_VREFO CODEC_VREF 10mil 1 C568 C565 10U_0805_10V4Z 2 R439 20K_0402_1% 1 0.1U_0402_16V4Z 2 close codec ALC268-GR_LQFP48_9X9 1 R480 2 0_0805_5% 1 R477 2 0_0805_5% 1 R436 2 0_0805_5% 1 R470 2 0_0805_5% 1 R479 2 0_0805_5% 1 R437 2 0_0805_5% 1 Sense Pin HP_OUT_L 43 5 19 HDA_SDOUT_AUDIO 1 100K_0402_5% 1 2 D32 RB751V_SOD323 HP_LEFT-FRONT_LEFT LINE_OUT_R MIC2_L NC NC 10 2 R516 AMP_RIGHT DMIC_CLK 11 19 HDA_SYNC_AUDIO AMP_LEFT CD_L MIC1_C_L 21 4.7U_0805_6.3V6K MIC1_C_R 22 4.7U_0805_6.3V6K MONO_IN 12 19 HDA_RST_AUDIO# 3 35 36 1 R456 1K_0402_1% 2 1 2 15mil LINE_OUT_L 1 INT_MIC_R NC 1 C569 10U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 14 220P_0402_50V7K 2 MIC_PLUG# R455 1 Docking@ 2 0_0402_5% 1 C564 +3VS 3 U31 +1.5VS_DVDD 2 1 2 0.1U_0402_16V4Z 1 2 9 C567 2 L67 MBK1608121YZF_0603 1 2 2 1 DVDD C559 10U_0805_10V4Z DVDD_IO 37 D_MIC_PLUG# HP_PLUG# 10mil 40mil 38 R476 1 Docking@ 2 0_0402_5% LINEIN_PLUG# 0.1U_0402_16V4Z 1 1 C558 25 R473 1 Docking@ 2 0_0402_5% 37 D_LINEIN_PLUG# L68 1 2 FBM-L11-160808-800LMT_0603 AVDD2 37 D_HP_PLUG# +VDDA AVDD1 2 1 4.7U_0805_10V4Z 0.01U_0402_16V7K 1 2 1 C572 1 1U_0402_6.3V4Z SB_SPKR SHDN +VDDA 1 BOM Option 2 2.4K_0402_1% ALC888S-VC 19 3 OUT GND MONO_IN 2 1 30 2 40mil 5 C588 C R452 1 1 L69 1 C586 C592 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z IN 1 C571 1 1U_0402_6.3V4Z PCM_SPK# (output = 300 mA) U33 1 2 24 R450 2 1 60mil L70 1 2 KC FBM-L11-201209-221LMAT_0805 SENSE A 4 SENSE B 39.2K PORT-A (PIN 39, 41) 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) 5.1K PORT-D (PIN 35, 36) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) DGND AGND GND 2006/12/25 2007/12/25 Deciphered Date SCHEMATICS, M/B S4182 Document Number C D E F Rev E 401561 Date: B GNDA Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A GND Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date GNDA Thursday, September 11, 2008 G Sheet 33 H of 48 4 C D E Int. Speaker Conn. +5VAMP W=40mil VDD HP EN 4 6 INR_H INL_H HP_R HP_L 17 18 HPOUT_R HPOUT_L CVSS 15 VSS 16 GND PGND PGND CGND GND 2 23 7 13 29 2 C575 12 14 CP+ CP- 25 BIAS D4 SM05T1G_SOT23-3 @ 1 1 C576 1U_0603_10V4Z 2 R463 100K_0402_5% @ SPDIF_PLUG# EC_MUTE 3 G1 G2 Right HP_PLUG# @ Q42B 2N7002DW-T/R7_SOT363-6 5 S/PDIF Out JACK LINE Out/Headphone Out 1 1 1 2 3 4 @ Q42A 2N7002DW-T/R7_SOT363-6 2 D 2 0.01U_0402_16V7K 1 2 ACES_88266-02001 CONN@ R465 100K_0402_5% @ 1 2.2U_0805_10V6K 2 S 1 1 2 +5VAMP APA2057A_TSSOP28 1 C577 SPK_R+ SPK_R- 2 0_0603_5% 2 0_0603_5% 1 1 3 BEEP Left +5VAMP /SD 28 G1 G2 4 1U_0603_10V4Z 2 26 3 4 2 VOL_AMP 39K_0402_5% R69 R68 3 24 2 1 2 ACES_88266-02001 CONN@ 1 1 19 2 100K_0402_5% 8 9 SPKL+ SPKL- R449 1 LOUT+ LOUT- 1 C563 1 20 10 ROUT+ ROUT- /AMP EN VOL_AMP R453 100K_0402_1% 2 11 INR_A INL_A 27 HP_RIGHT_R 39K_0402_5% HP_LEFT_R 1 2 JP20 SPKR+ SPKRSPKR+ SPKR- 2 100K_0402_5% R440 R461 30K_0402_5% 20mil R448 1 2 D1 SM05T1G_SOT23-3 @ 1 1 +5VAMP Gain= 14dB 2 4.7U_0805_10V4Z 22 21 R441 SPK_L+ SPK_L- 6 1 C579 2 0_0603_5% 2 0_0603_5% 1 1 2 HP_RIGHT_C 2 2.2U_0805_10V6K HP_LEFT_C 2 2.2U_0805_10V6K JP19 1 R9 R10 1 +5VAMP 33 HP_LEFT-FRONT_LEFT 3 5 2 HPF Fc = 604Hz HP_RIGHT-FRONT_RIGHT 1 C554 HP_LEFT-FRONT_LEFT 1 C553 U32 560_0402_5% 2 560_0402_5% 33 HP_RIGHT-FRONT_RIGHT 2 PVDD PVDD 1 AMP_RIGHT_C 1U_0402_6.3V4Z AMP_LEFT_C 1U_0402_6.3V4Z 2 HVDD 1 C562 AMP_LEFT_C-1 1 2 1 C556 C561 0.47U_0603_16V4Z R435 R442 CVDD AMP_LEFT 1 1 1 AMP_RIGHT 33 0.1U_0402_16V4Z C555 0.47U_0603_16V4Z AMP_RIGHT_C-1 1 2 1 33 2 0.1U_0402_16V4Z C578 2 C574 SPKL+ SPKL- 3 +3VS 2 B 2 A 2 G Q44 2N7002_SOT23 EC_MUTE 30 JHP1 2 8 7 R493 33 37 AUDIO_GNDA 1 R478 2 0_0603_5% HP_PLUG# 2 HP_PLUG# For Docking 37 37 D_HPOUT_L D_HPOUT_R D_HPOUT_L D_HPOUT_R R278 Docking@ 47_0603_1% R280 Docking@ 47_0603_1% HPOUT_R R468 HPOUT_L R469 HPOUT_L HPOUT_R HPOUT_R_1 1 54.9_0402_1%L72 HPOUT_L_1 1 54.9_0402_1%L71 SPDIF_PLUG# 1 5 0_0402_5% 4 2 HPOUT_R_2 FBM-11-160808-700T_0603 2 HPOUT_L_2 FBM-11-160808-700T_0603 3 6 2 1 SINGA_2SJ-E351-S03 CONN@ For Docking 37 37 D_LINE_L D_LINE_R 1 1 330P_0402_50V7K 330P_0402_50V7K D_LINE_L D_LINE_R R274 Docking@ 47_0603_1% R277 Docking@ 47_0603_1% LINE_R-SURR_R LINE_L-SURR_L D_MIC_L D_MIC_R R283 Docking@ 47_0603_1% R286 Docking@ 47_0603_1% MIC1_R MIC1_L C593 C595 2 2 For Docking 37 37 D_MIC_L D_MIC_R LINE-IN JACK JLINE1 8 7 3 LINEIN_PLUG# 33 LINEIN_PLUG# 33 LINE_R-SURR_R LINE_R-SURR_R LINE_L-SURR_L 33 LINE_L-SURR_L 2 R460 2 R459 1 1K_0402_1% 1 1K_0402_1% L75 1 FBM-11-160808-700T_0603 LINE_R_R 2 1 L76 LINE_L_R 2 FBM-11-160808-700T_0603 1 1 C599 220P_0402_50V7K 2 2 3 5 4 3 6 2 1 SINGA_2SJ-E351-S03 CONN@ C598 220P_0402_50V7K (HDA Jack) MIC JACK MIC1_VREFO_R 33 MIC1_R 33 MIC1_L MIC1_L 2 1 R458 1K_0402_1% 2 1 R457 1K_0402_1% 2 FBM-11-160808-700T_0603 1 L73 1 L74 1 C597 220P_0402_50V7K MIC1_L_1 2006/12/25 2 (HDA Jack) Compal Electronics, Inc. 2007/12/25 Deciphered Date Title Date: B C 4 SINGA_2SJ-E351-S01 CONN@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 3 6 2 1 1 C596 220P_0402_50V7K Compal Secret Data Security Classification Issued Date 2 5 4 MIC1_R_1 2 FBM-11-160808-700T_0603 4 MIC_PLUG# MIC_PLUG# 2 MIC1_R 33 R471 2.2K_0402_5% 2 R474 2.2K_0402_5% 8 7 1 1 MIC1_VREFO_L JMIC1 D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 34 of 48 FAN1 Conn H2 H_3P3 H5 H_3P3 @ H34 H_3P0 @ 1 @ H33 H_3P0 1 @ H15 H_3P0 1 @ H14 H_3P0 1 @ H13 H_3P0 1 @ H12 H_3P0 1 @ H11 H_3P0 1 H10 H_3P0 1 @ H1 H_3P3 +5VS @ H16 H_3P3 @ 1 @ 1 1 @ 1 +5VS 10U_0805_10V4Z 2 @ 1 C419 1 H9 H_3P0 1 1 H8 H_3P0 U25 8 7 6 5 D21 1 G993P1UF_SOP8 Change to SC1BAS16000 2 BAS16_SOT23-3 C401 10U_0805_10V4Z 1 2 C612 0.1U_0402_16V4Z +3VS C393 1000P_0402_50V7K 1 2 H27 H_4P2 H28 H_4P2 H29 H_4P2 30 FAN_SPEED1 1 C23 1000P_0402_50V7K JP26 @ @ 1 40mil +VCC_FAN1 1 R20 10K_0402_5% 1 @ 1 2 3 ACES_85205-03001 CONN@ 2 FD2 @ FIDUCIAL_C40M80 FD3 @ FIDUCIAL_C40M80 FD4 @ FIDUCIAL_C40M80 @ FIDUCIAL_C40M80 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date 1 FD1 @ 1 @ H32 H_4P6X4P1N 1 H31 H_4P1N 1 2 GND GND GND GND 1 1 VEN VIN VO VSET 2 1 2 3 4 +VCC_FAN1 1 300_0402_5% 1 2 R532 1 EN_DFAN1 2 30 D23 1SS355_SOD323-2 2007/09/14 Deciphered Date 2007/12/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 Sheet 35 of 48 A B C D E +5VALW TO +5VS +5VALW +5VALW 2 +5VS R240 100K_0402_5% U20 R244 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z 10U_0805_10V4Z 2 2 10U_0805_10V4Z SYSON# 28,29,37,44 SYSON# 30,43 SYSON SYSON 5VS_GATE 3 S D SUSP R487 200K_0402_5% @ 1 2 R243 100K_0402_5% C344 0.1U_0603_25V7K +5VALW 1 2 2 S D Q55 @ 3 3 2 Q17G 2N7002_SOT23 2 SUSP G Q21 2N7002_SOT23 S 2N7002_SOT23 R241 100K_0402_5% U17 2 2 1 10U_0805_10V4Z 2 2 10U_0805_10V4Z U21 R219 470_0603_5% C348 D 5VS_GATE S S S G 2 1 2 3 4 C350 SI4856ADY_SO8 2 SUSP G Q13 2N7002_SOT23 1 C353 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 2 10U_0805_10V4Z R269 470_0603_5% D +VSB 3V_GATE 2 1 R275 150K_0402_5% 1 +1.8V to +1.8VS +1.8V 1 D D D D 1 3 S 8 7 6 5 2 C310 VLDT_EN# 2 Q25G 2N7002_SOT23 +1.8VS D R494 S S 3 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 C305 AO4468_SO8 1M_0402_5% 1 C311 R245 10K_0402_5% +1.2V_HT 1 2 2 VLDT_EN# G Q24 2N7002_SOT23 C349 0.1U_0603_25V7K 2 1 3 C306 +1.2VALW 1 2 3 4 S S S G 1 1 2 D D D D S Q20 2N7002_SOT23 1 +3VS 8 7 6 5 D 2 G SUSP# 1 +3VALW 30,32,44 1 +3VALW TO +3VS SUSP SUSP 3 32 1 2 G 20,30,38,41 ACIN 1 2 1 1 2 1 R238 200K_0402_5% S Q19 2N7002_SOT23 1 D +VSB D 2 G 1 1 C343 1 1 2 C342 AO4468_SO8 1 1 1 C345 1 2 3 4 S S S G 3 1 D D D D 1 C346 8 7 6 5 1 C271 1 R180 470_0603_5% 10U_0805_10V4Z 2 2 1U_0603_10V4Z SI4856ADY_SO8 R495 2 3 Q9 S 2N7002_SOT23 R239 100K_0402_5% 3 1 2 C276 D S Q18 2N7002_SOT23 2 G 32,42,43 VLDT_EN 0.1U_0603_25V7K 3 1 VLDT_EN# 1 D 2 G S 2.2M_0402_5% 1 1 SUSP 2N7002_SOT23 2 SUSP G Q11 2N7002_SOT23 1 1.8VS_GATE 2 1 R177 510K_0402_5% +5VALW D 3 +VSB S Q56 1 SI4856/AO4430 D 2 G 1 10U_0805_10V4Z 2 2 10U_0805_10V4Z ACIN 2 C270 3 1 C261 1 2 3 4 S S S G 1 1 D D D D 3 C272 8 7 6 5 2 U13 S Q57 2 1 +1.1VS 2 G 2N7002_SOT23 2 ACIN 3 R242 10K_0402_5% D 1 1 R515 470_0603_5% D S 3 2 VLDT_EN# G Q54 2N7002_SOT23 R158 470_0603_5% 1 1 4 D 2 SYSON# G Q7 2N7002_SOT23 S 3 D 2 SUSP G Q5 2N7002_SOT23 S 2 2 1 1 1 S +1.8V R159 470_0603_5% 3 3 D 2 SUSP G Q12 2N7002_SOT23 3 D S R144 470_0603_5% 1 1 1 R185 470_0603_5% 4 +0.9V 2 +2.5VS 2 +1.5VS 2 SYSON# G Q8 2N7002_SOT23 2007/09/14 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/12/25 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C D SCHEMATICS, M/B S4182 Document Number Rev E 401561 Sheet Thursday, September 11, 2008 E 36 of 48 +3VALW +3VALW 1 1 2 R266 10K_0402_5% Docking@ 2 R264 Docking@ 10K_0402_5% 1 EC_DOCKIN 16 D Q23 2N7002_SOT23 Docking@ 2 G 3 16,17,27,30,33 EC_DOCKIN# S +5VALW 1 22U_0805_10V4Z C603 @ 2 10/15 Acer DVR 1028 Rev0.3 JDOCK2 ACER DOCK Normal 19V_5A 5V_USB_3A 33 34 35 36 37 38 39 40 41 42 43 44 45 LIN_IN_DT# LIN_IN_L LIN_IN_R MIC_DT# MIC_L MIC_R GNDA DOCK_DT1# SPDIF GND LAN_2 LAN_2# GND 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND USB USB# USB_EN# RESERVED VGA_DT# LAN_PWR LAN_ACT LAN_LINK GND LAN_0 LAN_0# GND LAN_1 LAN_1# GND LAN_3 LAN_3# GND 71 72 GND GND 1 +3VALW 2 R267 10K_0402_5% 19,30 DOCKIN# 1 33 C347 Docking@ 2 33 D_LINEIN_PLUG# 34 D_LINE_L 34 D_LINE_R 33 D_MIC_PLUG# 34 D_MIC_L 34 D_MIC_R 34 AUDIO_GNDA 0.1U_0402_16V4Z SPDIF D_LAN_MDI2+ D_LAN_MDI2- 27 D_LAN_MDI2+ 27 D_LAN_MDI2- USB20_P3 USB20_N3 19 USB20_P3 19 USB20_N3 28,29,36,44 SYSON# 17,19 CRT_DET# R285 1 +3V_LAN 27 D_LAN_ACTIVITY# 27 D_LAN_LINK# AUDIO_GNDA DOCKIN# @ 2 0_0603_5% +LAN_VCC 27 D_LAN_MDI0+ 27 D_LAN_MDI0- D_LAN_MDI0+ D_LAN_MDI0- 27 D_LAN_MDI1+ 27 D_LAN_MDI1- D_LAN_MDI1+ D_LAN_MDI1- 27 D_LAN_MDI3+ 27 D_LAN_MDI3- D_LAN_MDI3+ D_LAN_MDI3- 46 P3 47 (67) 48 49 33 50 34 51 35 52 36 53 37 54 38 55 39 56 40 57 41 58 42 59 43 60 44 61 45 62 63 P4 64 (68) GND GND 65 66 GND DVI_CLK DVI_CLK# GND DVI_TX0 DVI_TX0# GND DVI_TX1 DVI_TX1# GND DVI_TX2 DVI_TX2# GND VGA_R GND VGA_G GND VGA_B GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 DOCK_DT2# HP_L HP_R HP_DT# GNDA DVI_DT DVI_DCDT DVI_DDCCK VGA_VS VGA_HS VGA_DDCCK VGA_DDCDT 5V_S0 20 21 22 23 24 25 26 27 28 29 30 31 32 GND GND 69 70 1 P1 (65) 2 3 4 20 5 21 6 22 7 23 24 8 9 25 26 10 27 11 28 12 29 13 30 14 31 15 32 16 17 P2 18 (66) 19 ACER DVR1027 Rev: 0.5 D_DVI_TXC+ 16 D_DVI_TXC- 16 D_DVI_TXD0+ 16 D_DVI_TXD0- 16 D_DVI_TXD1+ 16 D_DVI_TXD1- 16 D_DVI_TXD2+ 16 D_DVI_TXD2- 16 D_CRT_R 17 D_CRT_G 17 D_CRT_B 17 DOCK_DT2# AUDIO_GNDA R270 1 Docking@ 2 1K_0402_5% D_HPOUT_L 34 D_HPOUT_R 34 D_HP_PLUG# 33 Docking@ R272 1 D_DVI_DET 2 0_0402_5% D_DVI_SDATA 16 D_DVI_SCLK 16 D_CRT_VSYNC 17 D_CRT_HSYNC 17 D_CRT_CLK 17 D_CRT_DATA 17 D_DVI_DET 11,16 1 +5VALW 67 68 100K_0402_5% +5VS R271 @ 2 DOCK_B+ JAE_SP07-10207-22_68P-T Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/14 Deciphered Date 2007/12/25 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SCHEMATICS, M/B S4182 Rev E 401561 Date: Thursday, September 11, 2008 Sheet 37 of 48 A B C D PD11 2 DOCK_B+ 1 1 3 PDS1040-13_POWERDI5-3 2 @PC158 @ PC158 470P_0402_50V7K SP02000EF00 PJP1 1 1 1 2 2 2 1 1 2 2 PR8 10K_0402_5% 2 2 PR6 20K_0402_1% 8 3 - 1 PC6 1000P_0402_50V7K RTCVREF 2 Vin Dectector Min. H-->L 16.976V L-->H 17.430V + PBJ1 PR5 22K_0402_5% 1 2 PC5 0.1U_0603_25V7K 2 1 LM358DT_SO8 RTC Battery 2 + 0 PD3 RLZ4.3B_LL34 10K_0402_5% 2 E&T_4510-E04C-01R 1 1 P 2 PR4 0_0402_5% G 1 20,30,41 ACIN PU1A 4 PC4 100P_0402_50V8J PR3 84.5K_0402_1% PD2 RB751V 2 2 PC3 1000P_0402_50V7K PC160 470P_0402_50V7K PC2 100P_0402_50V8J VIN PR2 10K_0402_5% JUMP_43X79 PC1 1000P_0402_50V7K VS VIN 1 1 1 1 1 @ 2 1 2 2 2 2 VIN PJ1 DC_IN_S2 2 1 3 2 3 1 4 2 4 PR7 1 PL1 SMB3025500YA_2P 1 DC_IN_S1 PC159 470P_0402_50V7K 2 1 5 1 G1 PR1 1M_0402_1% 1 2 2 6 1 G2 2 1 +RTCBATT 1 +RTCBATT Typ 17.525V 17.901V Max. 17.728V 18.384V @ MAXEL_ML1220T10 SP093MX0000 PJ2 VIN 2 +3VALWP 2 @ 2 PJ3 1 1 1 3 VS 1 2 +VSBP PC8 0.1U_0603_25V7K 2 1 GND PC9 10U_0805_10V4Z 2 +NB_COREP +VSB +1.1VSP 2 2 N2 2 2 2 2 1 1 +1.1VS (1.9A,80mils ,Via NO.=4) PJ9 1 1 +1.2VALW +2.5VSP 2 2 1 1 +2.5VS @ JUMP_43X118 (1.0A,40mils ,Via NO.=2) PJ11 1 1 +NB_CORE +1.5VSP 2 2 1 1 +1.5VS @ JUMP_43X118 (1.0A,40mils ,Via NO.=2) @ JUMP_43X118 (8.8A,360mils ,Via NO.=18) PC10 1 4 1U_0805_25V4Z Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/06/22 Deciphered Date 2008/06/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A +0.9V @ JUMP_43X118 @ JUMP_43X118 PJ19 2 2 1 1 1 IN 1 2 2 4 1 PJ10 G920AT24U_SOT89-3 OUT 1 PJ7 1 (3.94A,160mils ,Via NO.=8) 1 3 2 @ JUMP_43X118 PU2 3.3V 2 (2A,80mils ,Via NO.= 4) PJ8 2 +1.2VALWP 2 PR13 22K_0402_1% PR16 560_0603_5% 1 2 +1.8V @ JUMP_43X79 (120mA,40mils ,Via NO.= 2) PR14 200_0603_5% PR15 560_0603_5% 1 2 1 PJ5 2 +0.9VP @ JUMP_43X39 2 PC7 0.22U_0603_25V7K @ PC167 @PC167 470P_0402_50V7K RTCVREF +CHGRTC +5VALW (8.61A,400mils ,Via NO.= 20) 1 51_ON# 1 JUMP_43X118 PJ6 1 1 2 2 32 1 1 (12.06A,480mils ,Via NO.=24) 470P_0402_50V7K 2 1 N1 PR12 100K_0402_1% 2 2 @ JUMP_43X118 3 PR10 68_1206_5% 2 PR11 200_0603_5% 1 2 PR9 68_1206_5% @ 1 CHGRTCP PQ1 TP0610K-T1-E3_SOT23-3 2 +5VALWP 2 PD5 RLS4148_LL34-2 PC165 1 PJ4 +1.2VALW 1 1 1 2 2 BATT+ 2 +1.8VP (8.61A,400mils ,Via NO.= 20) PD4 RLS4148_LL34-2 3 +3VALW JUMP_43X118 B C SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 D Sheet 38 of 48 A B C PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C VMB PL2 SMB3025500YA_2P 1 2 BATT_S1 D BATT+ VL VL 1 2 PC13 0.01U_0402_25V7K PR17 100K_0402_1% TM_REF1 2 10 11 11 12 12 13 13 14 14 16 16 2 15 17 17 18 18 19 19 20 20 RLS4148_LL34-2 LM393DG_SO8 4 PR26 1K_0402_1% 2 BATT_TEMP 30 2 1 VL PR23 100K_0402_1% PR25 100K_0402_1% PR21 2 15 O 1 3 8 10 - PD6 2 1 1 8 9 1 7 9 2 7 +3VALWP PC15 1000P_0402_50V7K 6 1 4 6 2 4 5 PR22 11.3K_0402_1% 3 5 1 3 2 2 PC14 0.22U_0603_16V7K 2 1 1 2 1 PQ2 DTC115EUA_SC70-3 PU3A + P 3 1 1 8 PR19 18K_0402_1% 1 2 PJP2 PR24 6.49K_0402_1% 2 1 1 MAINPWON 6,40 PR18 100K_0402_1% 1 2 G PC11 0.1U_0603_25V7K 2 PH1 100K_0603_1%_TH11-4H104FT 1 1 2 1 PC12 1000P_0402_50V7K 2 2 1 VL EC_SMCA 2 1 EC_SMB_CK1 6,30 100_0402_1% 2 SUYIN_200109MS020G209ZR PH2 near main Battery CONN : BAT. thermal protection at 92 degree C Recovery at 56 degree C PR20 EC_SMDA 2 1 EC_SMB_DA1 6,30 100_0402_1% 2 VL 1 PQ3 TP0610K-T1-E3_SOT23-3 VL 2 @ 5 + 6 - @ PR32 11.3K_0402_1% PU3B @PD7 @ PD7 2 7 G O 4 1 @ PC18 0.22U_0603_16V7K 1 TM_REF1 P 8 @PR30 @ PR30 18K_0402_1% 1 2 2 1 1 2 2 @ @ PR27 100K_0402_1% 1 3 RLS4148_LL34-2 LM393DG_SO8 2 2 VL 2 PR31 22K_0402_1% 1 2 PC16 0.22U_0603_25V7K 3 2 1 PR29 100K_0402_1% B+ @ PH2 100K_0603_1%_TH11-4H104FT +VSBP 1 PC17 0.1U_0603_25V7K 3 @ PR28 @PR28 100K_0402_1% 1 2 1 VL 1 PR34 0_0402_5% 2 D 3 1 POK S PQ4 SSM3K7002F_SC59-3 2 G 2 1 40,42 PC19 0.1U_0402_16V7K 1 PR33 100K_0402_1% @ 4 4 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/6/22 Deciphered Date 2008/6/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 D Sheet 39 of 48 5 4 3 ISL6237_B+ PHASE2 PC32 PHASE1 16 0.1U_0603_25V7K LX5 LGATE1 18 DL5 4 DL3 23 FB3 VL @ LGATE2 30 OUT2 32 REFIN2 PGND 22 OUT1 10 FB1 11 BYP 9 SKIP 29 2VREF_ISL6237 1 2 1 @ 1 + PC35 C 150U_D2E_6.3VM_R18 1 25 PQ8 AO4712_SO8 1 PR41 63.4K_0402_1% 2 PR39 0_0603_5% LX3 PC25 2200P_0402_50V7K 2 1 3 2 1 BST5A 2 @ PR37 4.7_1206_5% 2 1 7 17 5 6 7 8 VCC LDO 3 6 VIN DH5 BOOT1 2 PR43 10K_0402_1% 1 2 2 PR42 10K_0402_1% BOOT2 19 15 PC31 0.1U_0603_25V7K @ 1 24 PVCC UGATE1 3 2 1 1 4 PR38 1 BST3A 0_0603_5% UGATE2 PL3 2 1 8.2UH_PCMB063T-8R2MS_4.5A_20% PC29 1U_0603_10V6K 1 2 2 2 2 TP 26 D +5VALWP 1 8 7 6 5 PQ7 AO4712_SO8 33 PQ6 AO4466_SO8 4 PC34 680P_0603_50V7K 2 1 C DH3 1 2 3 2 1 + PC33 680P_0603_50V7K 2 1 2 1 PR40 0_0402_5% +3VALWP PU4 @ PR36 4.7_1206_5% 2 1 PL4 1 2 8.2UH_PCMB063T-8R2MS_4.5A_20% 4.7U_0805_6.3V6K PC28 2 1 1U_0603_10V6K PC27 1 2 2 1 PC26 0.1U_0603_25V7K PC24 4.7U_1206_25V6K 2 1 5 6 7 8 8 7 6 5 VL PQ5 AO4466_SO8 4 1 2 3 PC166 470P_0402_50V7K PC22 2200P_0402_50V7K 2 1 2 1 @ JUMP_43X118 PC21 4.7U_1206_25V6K 2 1 1 1 PC20 4.7U_1206_25V6K 2 1 2 PC23 4.7U_1206_25V6K 2 1 PR35 0_0805_5% 1 2 PJ12 2 PC30 330U_D3L_6.3VM_R25M 1 ISL6237_B+ B+ D 2 FB5 REF PC36 0.22U_0603_10V7K 8 LDOREFIN @ PR44 2 PR45 1 20 4 14 2 POK2 28 EN_LDO POK1 13 EN1 ILIM1 12 POK 39,42 PR48 ILM1 2 330K_0402_1% 1 B GND 21 TON ILIM2 31 ILIM2 2 1 330K_0402_1% ISL6237IRZ-T_QFN32_5X5 1 2 NC 5 EN2 PR53 0_0402_5% +5VALWP Ipeak=8.444A ; Imax=5.91A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =10.147A ~ 11.980A Delta I=1.96A (Freq=400KHz) 2VREF_ISL6237 2 PC161 1U_0603_6.3V6M 2 1 2VREF_ISL6237 1 1 2 3 1 @ PR55 47K_0402_5% 1 2 PC38 0.047U_0402_16V7K PR54 0_0402_5% 2 1 MAINPWON 1 2 PR52 806K_0603_1% 1 2 6,39 2 @ PR50 0_0402_5% PR51 0_0402_5% 2 27 VL PD12 1SS355_SOD323-2 NC VL PR49 PC39 0.047U_0402_16V7K 2 1 2 B 1 PR47 200K_0402_5% 1 2 PR46 100K_0402_1% 1 2 PC37 0.22U_0603_25V7K PD8 RLZ5.1B_LL34 1 2 VS 0_0402_5% 1 0_0402_5% 2 @ PQ38 TP0610K-T1-E3_SOT23-3 5 A 1 A +3.3VALWP Ipeak=8.444A ; Imax=5.91A Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =10.134A ~ 11.967A Delta I=1.934A (Freq=300KHz) Compal Electronics, Inc. Compal Secret Data Security Classification 2007/06/22 Issued Date Deciphered Date 2008/06/22 Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Thursday, September 11, 2008 Date: Rev E 401561 4 3 2 Sheet 1 40 of 48 A B ACSET 6 ACSET 1 1 OVPSET Fsw : 300KHz 8 OVPSET 9 AGND 21 24751_VREF 10 CELLS 20 CELLS VREF 11 VDAC SRSET 16 SRSET IADAPT 15 PR76 10_0603_5% 1 2 1 2 1 2 2 2 2 1 @ PR75 100K_0402_1% 2 PC64 @0.01U_0402_25V7K 1 2 PR74 100K_0402_1% 1 1 30 Calibrate# D 2 @ 2 1 PR85 221K_0402_1% CHGEN# D S PQ18 SSM3K7002F_SC59-3 2 G 30 FSTCHG PQ19 RHU002N06_SOT323-3 2 G PR83 100K_0402_1% 1 PQ17 SI2301BDS-T1-E3_SOT23-3 VADJ 3 PR84 100K_0402_1% PR82 1 2 0_0402_5% 1 1 1 1 3 PR189 4.3K_0402_5% 4 1 PR66 100K_0402_1% PQ16 SSM3K7002F_SC59-3 @ 24751_VREF 2 6 S 2 G 24751_VREF REGN 1 - 0 D ACIN 20,30,38 PR80 887K_0402_1% 3 5 @PR188 @ PR188 0_0402_5% 1 2 2 + 3 3 ACGOOD# VMB 2 3 30 1 1 P PU1B G 8 2 PR195 340K_0402_1% 2 1 PQ40 SSM3K7002F_SC59-3 7 IREF 30 ADP_I S VS PR79 10K_0402_1% 1 2 24751_VREF PR73 2 1 17.4K_0402_1% 2 1 PQ39 SSM3K7002F_SC59-3 1 3 S D 1 1 2 BATDRV PC65 100P_0402_50V8J LM358DT_SO8 D 14 PQ14_GATE 3 1 D PC60 @0.1U_0603_25V7K CC=0.2~4.26A Iref=0.77448*Icharge Iref=0.155~3.3V ICHG setting D PQ37 SSM3K7002F_SC59-3 2 65W/90W# G ACGOOD G BATT_OVP 13 BQ24751ARHDR_QFN28_5X5 2 G PC59 0.1U_0603_25V7K PC63 0.1U_0603_25V7K S 30 29 2 /BATDRV 2 G ACSET PR183 100K_0402_1% TP VADJ 24751_VREF PR194 100K_0402_1% 2 1 PC168 ACOFF 1 2 BATT-OVP=0.111*BATT+ 17 2 PR196 200K_0402_1% 2 1 24751_VREF LI-4S :18V----BATT-OVP=1.998V SE_CHG- BAT 2 1 PR72 100K_0402_1% 0.1U_0402_16V7K SE_CHG+ 2 1 ACSET 12 ACGOOD# 3 19 18 1 VADJ PQ14 SI2301BDS-T1-E3_SOT23-3 RTCVREF LI-3S :13.5V----BATT-OVP=1.5V 2 30 1 1 2 PC62 0.1U_0603_25V7K SRP 2 2 30 PR63 64.9K_0402_1% 1 2 ACOFF SRN PC67 0.01U_0402_25V7K PQ14_GATE 2 3S/4S# G PQ15 SSM3K7002F_SC59-3 @ PC61 1U_0603_10V6K 3 PR71 100K_0402_1% 1 3 LEARN PC58 0.1U_0402_16V7K 1 2 1 2 2 Cells selector 30 22 2 24751_VREF D 4 PGND PR68 54.9K_0402_1% 1 1 1 24751_VREF 23 2 1 2 1 PR78 PR77 499K_0402_1% 340K_0402_1% 4 Cell PR70 0_0402_5% CELLS S DL_CHG LODRV 2 1 PR81 105K_0402_1% 3 Cell VREF PC66 0.01U_0402_25V7K GND 1 2 CELLS 3 2 24751_VREF BATT+ 1 2 2 @ PR69 100K_0402_1% 2 2 7 ACOP PC57 0.47U_0603_16V7K 1 Input UVP : 17.26V PQ13 AO4466_SO8 4 3 2 1 2 1 PR67 340K_0402_1% Input OVP : 22.3V PC55 1U_0603_10V6K 2 65W adapter Iadapter=(Vacset/Vvdac)*(0.1/PR48)=2.90A 2 PR65 4.7_1206_5% 24 REGN Iadapter=(Vacset/Vvdac)*(0.1/PR48)=4.04A 2 2 PR64 54.9K_0402_1% 90W adapter 1 PC51 RLS4148_LL34-2 0.1U_0603_25V7K REGN 2 Icharge=(Vsrset/Vvdac)*(0.1/PR36) 1 PR62 PL5 0.02_2512_1% 10UH_PCMB104T-100MS_6A_20% 1 2 1 4 1 LX_CHG PD10 2 2 25 3 2 1 PH PC53 10U_1206_25V6M ACDRV ACDET 5 6 7 8 4 5 1 ACDRV 1 DH_CHG 2 26 PC52 10U_1206_25V6M HIDRV 1 ACN ACP 1 PQ12 AO4407_SO8 4 1 2 3 /BATDRV PQ11 AO4466_SO8 4 3 2 1 ACN ACP PR57 100K_0402_1% 2 PR61 2.2_0603_5% 1 2 1 BTST PC45 2200P_0402_25V7K 27 1 BTST PC43 4.7U_1206_25V6K 2 PC48 0.1U_0603_25V7K 1 2 1 PVCC 5 6 7 8 28 PC40 0.01U_0402_25V7K PC56 680P_0603_50V8J 2 CHGEN PC49 @0.1U_0603_25V7K ACDET CHG_B+ 1 1 PVCC PU5 1 1 1 2 PC47 0.1U_0603_25V7K 2 JUMP_43X118 PC42 4.7U_1206_25V6K @ 5 6 7 8 3 2 4 2 1 1 4 PR60 340K_0402_1% PC50 2.2U_0805_25V6K 2 @PD9 @ PD9 RLZ24B_LL34 PJ13 1 PC46 0.1U_0402_16V7K 1 2 2 1 2 1 PR182 3.3_1210_5% PR56 0.015_2512_1% 8 7 6 5 PR59 100K_0402_1% 2 2 1 1 2 PC41 0.01U_0603_50V7K PC44 0.01U_0402_25V7K 2 1 4 1 1 2 3 CHGEN# PR58 3.3_1210_5% 1 1 2 3 D B+ PQ10 AO4407_SO8 8 7 6 5 2 PQ9 AO4407_SO8 VIN C 4 S S PR80 PR85 4.0V L @ 0 4.1V L 887K 221K 4.2V H 887K 221K Charger ADJ CP setting Calibrate# Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/06/22 Deciphered Date 2008/06/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C SCHEMATICS, M/B S4182 Document Number Rev E 401561 Thursday, September 11, 2008 D Sheet 41 of 48 A B C D LOW 1.1V PC68 1U_0402_6.3V6K +5VALW PL6 PC69 1U_0402_6.3V6K 1 B+ PR89 1 1 1 1 S 2 +5VALW @ 2.2_0603_1% 2 PR92 1 1 2 2 PR93 1 8 2 2 2 3 4 1 1 1 1 27 VIN2 VIN1 2 FB2 FSET2 VO1 VCC2 28 VCC1 PGOOD2 FSET1 FB1 PGOOD1 2 PR95 18.2K_0402_1% 29 PR99 1 ISL6228_B+ GND_T PR98 86.6K_0402_1% 2 PC75 1000P_0402_50V7K 5 FB1_NB_COREP 1 1 10_0603_1% PR94 22K_0402_1% 6 7 PR97 102K_0402_1% 1 2 2 PC74 1000P_0402_50V7K 2 PR96 3.3K_0402_5% 2 1 PC71 0.1U_0603_25V7K 10_0603_1% PC76 1000P_0402_25V8J 2 1 1 ISL6228_B+ 1 ISL6228_B+ 2 1 PC72 @ 0.1U_0402_16V7K PC70 0.1U_0603_25V7K PQ20 @ SSM3K7002F_SC59-3 2 PC73 0.01U_0402_25V7K S 2 G 2 @ D 2 1 11 POWER_SEL 1 PQ21 @ SSM3K7002F_SC59-3 1 2 2 PR91 G @ 0_0402_5% 3 2 D 3 2.2_0603_1% 2 FBMA-L11-322513-151LMA50T_1210 PC162 470P_0402_50V7K 2 1 PR88 2 +5VALW PR90 @ 0_0402_5% 1 2 2 PR86 12K_0402_1% PC163 470P_0402_50V7K 2 1 1 @ PR87 @ 10K_0402_1% 1 2 2 1.0V 1 FB1_NB_COREP HIGH 1 POWER_SEL PR100 66.5K_0402_1% PR101 PC77 3.3K_0402_5% 1000P_0402_25V8J 2 1 1 2 1 7.87K_0402_1% ISL6228_B+ PR102 PR104 7.87K_0402_1% 4 1 PC79 4.7U_1206_25V6K 2 8 7 6 5 1 2 OCSET1 VO2 1 26 NB_COREP_EN 11 EN1 PU6 OCSET2 25 EN2 24 ISL6228_B+ ISL6228HRTZ-T_QFN28_4X4 LG_NB_COREP AO4932_SO8 1 PR107 8.06K_0402_1% 1 2 PL8 1.8UH_1164AY-1R8N=P3_9.5A_30% 1 2 0_0603_5% 2 2 1 1 2 3 4 PC89 1 2 0.1U_0402_16V7K +1.2VALWP 3 1 PC87 330U_D2E_2.5VM 2 BST_1.2V 1 2 1 2 +5VALW 1 PC92 1U_0402_6.3V6K + 2 PC88 680P_0603_50V8J LG_1.2V 1.1VP Ipeak=8.9A ; Imax=6.23A DCR=6m ohm (max) Rocset=(Iocp*DCR)/10E-06=7.87K ohm Iocp=10.089A(1.3*DCR) Csen=L/(Rocset*DCR)=0.022uF STB_SB 39,40 POK 1.2VP Ipeak=3.94A ; Imax=2.758A DCR=10m ohm (max) Rocset=(Iocp*DCR)/10E-06=8.06K ohm Iocp=6.716A(1.2*DCR) Csen=L/(Rocset*DCR)=0.022uF PR113 @ 0_0402_5% 1 2 2 1.2V_EN 1 2 PR114 0_0402_5% 1 1 2 PC91 1U_0402_6.3V6K D2 D2 G1 S1 21 PVCC2 20 19 PGND2 PGND1 18 15 +5VALW NB_COREP_EN G2 S2/D1 S2/D1 S2/D1 PR110 4.7_1206_5% PR112 PC90 0.1U_0402_10V7K 32,36,43 VLDT_EN UG_1.2V 22 8 7 6 5 BOOT2 UGATE2 LGATE2 BOOT1 17 1BST_NB_COREP14 PR108 0_0603_5% LGATE1 1 2 16 1 2 3 2 PC86 0.1U_0402_16V7K 1 4 S S S 1 G 2 3 PR111 47K_0402_1% 2 1 LX_1.2V 23 1 PHASE2 2 UGATE1 1 13 PVCC1 2 PC85 680P_0603_50V8J UG_NB_COREP PR109 0_0603_5% PQ24 FDS6670AS_NL_SO8 D D D D PR106 4.7_1206_5% 2 + 2 8 7 6 5 1 PC83 330U_D2E_2.5VM 1 PC82 0.022U_0402_16V7K PQ23 PC84 4.7U_1206_25V6K PHASE1 1.2V_EN 2 12 PC81 4.7U_1206_25V6K LX_NB_COREP 2 1UH_MSCDRI-104R-1R0N-F_11A_30% 2 8.06K_0402_1% 1 +NB_COREP 2 PR103 10 1 2 3 1 PL7 1 1 71.5K_0402_1% PR105 0_0603_5% +1.1V FB2_1.2V 2 2 PQ22 AO4466_SO8 PC78 4.7U_1206_25V6K 2 1 9 PC80 0.022U_0402_16V7K 1 2 2 Freq=366KHz Rfset=1/(1.5E-10 * Freq)=18.2K @ PC93 0.01U_0402_25V7K 4 4 Freq=303KHz Rfset=1/(1.5E-10 * Freq)=22K Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/06/22 Deciphered Date 2008/06/22 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: A B C SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 D Sheet 42 of 48 5 4 3 2 1 PJ14 PR115 200K_0402_5% 1 2 15 11 V5DRV 10 DL_1.8V 9 S S S DRVL PQ27 FDS6670AS_NL_SO8 4 G 2 1 2 TPS51117RGYR_QFN14_3.5x3.5 1 PGND 8 GND PGOOD 1 @ PR190 4.7_1206_5% +5VALW 2 PC101 1U_0603_10V6K 2 3 2 1 14 12 PR119 17.4K_0402_1% 1 @PC99 @ PC99 47P_0402_50V8J 1 2 B+ +1.8VP 1 VFB LX_1.8V LL TRIP 0.1U_0603_25V7K PC100 4.7U_0805_10V6K 1 + 2 5 DH_1.8V 1 V5FILT 13 2 VOUT 4 DRVH 2 5 6 7 8 3 7 +5VALW C 1 D PL9 1UH_MSCDRI-104R-1R0N-F_11A_30% 1 2 PC96 BST_1.8V-1 1 D D D D TON VBST 2 6 PR118 0_0603_1% 1 2 1 @ JUMP_43X118 PC98 330U_D2E_2.5VM 2 @ PC164 680P_0603_50V8J 3 2 1 PC97 @0.1U_0402_16V7K PR117 0_0603_1% 1 2 2 2 PR187 47K_0402_5% TP 1 EN_PSV PU7 1 SYSON 1 30,36 2 4 BST_1.8V PR116 0_0402_5% 1 2 2 PC95 4.7U_1206_25V6K PQ26 AO4466_SO8 2 5 6 7 8 1 D PC94 4.7U_1206_25V6K 51117_B+ C 1 PR120 14K_0402_1% 1 2 2 PR121 10K_0402_1% VFB=0.75V Vo=VFB*(1+PR120/PR121)=1.8V Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.1E-07 Freq=305KHz Cesr=15m ohm Ipeak=12.6A Imax=8.82A Delta I=((19-1.8)*(1.8/19))/(L*Freq)=5.332A Vtrip=Rtrip*10uA=0.24V Iocp-min=Vtrip/Rdsonmax*1.4+2.666=17.573A Iocp-max=Vtrip/Rdsontyp*1.2+2.666=26.908A Iocp=17.573~26.908A +5VALW 1 B 2 2 1 2 6 FB 2 VIN 9 +1.1VSP @PR123 @ PR123 1.3K_0402_1% 1 3 1 4 VOUT @ APL5912-KAC-TRL_SO8 1 @ PC104 0.01U_0402_25V7K 22U_0805_6.3V6M 2 VOUT PC105 2 1 EN @ PC103 @PC103 4.7U_0805_6.3V6K 2 @ PC106 @PC106 1U_0603_10V6K 8 @ PR186 47K_0402_5% VIN 5 2 1 VLDT_EN 1 32,36,42 VLDT_EN 0_0402_5% 1 2 VCNTL POK GND 7 @PR122 @ PR122 1 @PU8 @ PU8 2 @ PC102 1U_0402_6.3V6K 1 1 PJ15 JUMP_43X118 @ 2 B +1.2VALW 2 @PR124 @ PR124 3K_0402_1% A A 2007/06/22 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/06/22 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 Sheet 1 43 of 48 5 4 3 2 1 D D (500mA,40mils ,Via NO.= 1) PU9 APL5508-25DC-TRL_SOT89-3 3 +2.5VSP 1 1 OUT GND 2 2 IN @ PR126 150_1206_5% 2 2 1 2 2 1 1 JUMP_43X79 @ PC108 1U_0603_6.3V6M 1 +3VS PC110 4.7U_0805_6.3V6K PJ16 C C 1 +1.8V 1 +1.8V PJ17 @ JUMP_43X79 6 NC 5 3 VREF NC 7 4 VOUT NC 8 TP 9 +3VALW 1 VCNTL GND 1 2 2 VIN 2 2 PC114 1U_0402_6.3V6K B 2 PQ28 SSM3K7002F_SC59-3 @ 1 1 2 1 S +0.9VP 2 2 1 2 PC118 @ 0.1U_0402_16V7K PR129 1K_0402_1% PC116 0.1U_0402_16V7K 1 PC117 0.01U_0402_25V7K 2 APL5915KAI-TRL_SO8 2 PR132 1.54K_0402_1% D 2 G 2 9 1 VIN 28,29,36,37 SYSON# @ PR131 0_0402_5% 1 2 3 FB 2 +1.5VSP 1 3 1 4 VOUT 1 VOUT APL5331KAC-TRL_SO8 2 1 GND 1 EN PR128 1K_0402_1% PC115 4.7U_0805_6.3V6K 2 PC121 0.1U_0402_16V7K @ PR184 47K_0402_5% 1 SUSP# 8 1 30,32,36 10K_0402_1% 1 2 5 PC119 22U_0805_6.3V6M POK VIN 2 7 PR130 1 6 PU11 VCNTL B PU10 1 2 PC113 4.7U_0805_6.3V6K 2 PC112 1U_0402_6.3V6K PJ18 @ JUMP_43X79 2 1 1 1 2 +5VALW PC120 10U_0805_6.3V6M 2 PR133 1.74K_0402_1% A A 2007/6/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/6/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 Sheet 1 44 of 48 4 3 2 1 PR140 10_0402_5% 1 2 +CPU_CORE_NB 1 PC155 2200P_0402_50V7K 2 1 PC152 0.01U_0402_25V7K 2 1 BOOT1 2 4 3 2 1 4 2 3 2 1 VW1 2 1 PC146 1000P_0402_50V7K 2 1 COMP1 2 PC148 180P_0402_50V8J PR177 2 1 PC150 2 1 PR178 6.81K_0402_1% 2 1 PR179 1K_0402_5% 2 1 54.9K_0402_1% 1200P_0402_50V7K 1 PC142 680P_0603_50V7K PR180 1 2 1 PC143 2 1 +CPU_CORE_1 Design Current: 12.6A Max current: 18A OCP_min:24A PC149 1000P_0402_50V7K PR181 6.81K_0402_1% 2 1 PC151 2 1 1 PR170 2 4.02K_0402_1% 0.1U_0402_16V7K @PH4 @ PH4 2 1 2 PR173 1 10_0402_5% @ 10K_0603_5%_TSM1A103J4302RE A PR176 1K_0402_5% 2 1 1 PR169 4.7_1206_5% PQ36 AO4456_SO8 3 2 1 DIFF_1 PR175 PC147 255_0402_1% 4700P_0402_25V7K FB_1 2 1 2 1 PR168 16.2K_0402_1% 1 PQ35 AO4456_SO8 4 2 PR172 1 10_0402_5% +CPU_CORE_1 2 5 6 7 8 PC141 0.22U_0603_10V7K 1 2 1 PL13 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 2 2 5 6 7 8 PR163 2.2_0603_5% BOOT1 1 2 1 RTN1 ISN1 1 B ISP1 2 PC145 180P_0402_50V8J +CPU_CORE_0 Design Current: 12.6A Max current: 18A OCP_min:24A PHASE1 LGATE1 COMP0 PC156 2200P_0402_50V7K 2 1 1 2 3 2 1 PQ34 SI7686DP-T1-E3_SO8 UGATE1 VSEN1 VW0 PR174 PC144 255_0402_1% 4700P_0402_25V7K FB_0 2 1 2 1 PC153 0.01U_0402_25V7K 2 1 3 2 1 5 TP CPU_B+ 49 24 ISN1 ISP1 23 ISP1 VW1 22 21 FB1 20 19 18 17 LGATE0 ISN0 UGATE1 25 ISN1 26 BOOT1 COMP1 UGATE1 VW0 VDIFF1 COMP0 12 VSEN1 11 RTN1 PHASE1 PC138 1U_0603_16V6K PC137 2 1 ISP0 LGATE1 1 PR155 2 4.02K_0402_1% 0.1U_0402_16V7K @PH3 @ PH3 2 1 2 PR159 1 10_0402_5% 10K_0603_5%_TSM1A103J4302RE @ PC157 2200P_0402_50V7K 2 1 28 PC136 680P_0603_50V7K PC154 0.01U_0402_25V7K 2 1 29 PGND1 PC139 10U_1206_25V6M 2 1 LGATE1 LGATE0 3 2 1 30 1 31 PVCC PQ33 AO4456_SO8 4 2 LGATE0 PQ32 AO4456_SO8 4 +5VS C +CPU_CORE_0 PR151 16.2K_0402_1% PR154 4.7_1206_5% 1 2 PHASE0 32 PC135 0.22U_0603_10V7K PC140 10U_1206_25V6M 2 1 33 PGND0 PL12 0.36UH_PCMC104T-R36MN1R17_30A_20% 1 2 2 5 6 7 8 PHASE0 PR150 2.2_0603_5% BOOT0 1 2 1 5 6 7 8 UGATE0 27 RTN0 4 PC134 10U_1206_25V6M 2 1 PQ31 SI7686DP-T1-E3_SO8 UGATE0 PC133 10U_1206_25V6M 2 1 5 CPU_VDDNB_FB_L 6 1 37 UGATE_NB 39 38 PHASE_NB 40 42 43 44 46 45 47 41 PGND_NB LGATE_NB BOOT0 PHASE1 +CPU_CORE_1 DIFF_0 35 34 FB0 PR171 0_0402_5% 2 1 6 CPU_VDD1_FB_H BOOT0 UGATE0 10 PR166 6 CPU_VDD1_FB_L BOOT_NB 1 2 PR167 10_0402_5% 6 CPU_VDD0_FB_L 36 BOOT_NB ISL6265IRZ-T_QFN48_6X6~D 13 6 CPU_VDD0_FB_H OCSET_NB VDIFF0 RTN_NB OCSET 9 FSET_NB 8 VSEN_NB RBIAS FB_NB ENABLE 7 COMP_NB 6 ISP0 ISN0 PR160 0_0402_5% VSEN0 2 1 PR161 +CPU_CORE_0 2 1 10_0402_5% 2 PR164 1 RTN0 0_0402_5% 2 PR165 1 0_0402_5% B PC130 220U_D2_4VM 2 PHASE0 10_0402_5% SVC VSEN0 1 82.5K_0402_1% SVD 5 16 PR158 4 15 2 PWROK ISP0 PR157 34.8K_0402_1% 2 1 3 VCC 48 VIN VR_ON PGOOD 2 30 2 1 PR156 0_0402_5% 1 2 @PR192 @ PR192 0_0402_5% CPU_SVC OFS/VFIXEN 2 ISN0 6 CPU_SVD 1 14 6 + PC131 @ 680P_0603_50V7K CPU_B+ PR148 10_0402_5% PU12 PR153 1 2 0_0402_5% 1 2 @PR191 @ PR191 0_0402_5% 2 1 PR152 0_0402_5% 1 2 @PR193 @ PR193 0_0402_5% 18 H_PWRGD_L 1 6 1 PR145 0_0402_5% 2 1 2 VGATE +VDDNB Design Current: 2.1A Max current: 3A OCP_min:5A 1 UGATE_NB 2 30 PQ30 AO4712_SO8 LGATE_NB PR149 @ 105K_0402_1% C D +CPU_CORE_NB PHASE_NB 2 2 1 1 2 PR147 105K_0402_1% PR138 @ 4.7_1206_5% 2 PC129 0.22U_0603_10V7K 4 2 PR146 @ 10K_0402_1% PL11 3.3UH_SIQB74B-3R3PF_5.9A_20% 1 2 + 2 PHASE_NB 2 PR144 @ 105K_0402_1% LGATE_NB CPU_VDDNB_FB_H PR142 11.3K_0402_1% 2 1 PC132 0.1U_0402_25V6 1 PR143 0_0402_5% PR136 2.2_0603_5% BOOT_NB 1 2 1 PR141 0_0402_5% 2 1 2 PR139 2_0603_5% +3VS 1 +5VS PHASE_NB B+ 1 3 2 1 1 PQ29 AO4466_SO8 4 1 2 PR137 22K_0402_1% 2 1 2 PC128 0.1U_0402_25V6 CPU_B+ UGATE_NB PC127 1000P_0402_50V7K 2 1 1 +5VS D 1 PC123 1200P_0402_50V7K PL10 HCB4532KF-800T90_1812 1 2 2 PR135 2_0603_5% 1 2 5 6 7 8 2 3 2 1 1 PR134 44.2K_0402_1% 5 6 7 8 2 PC124 10U_1206_25V6M 2 1 CPU_B+ PC122 33P_0402_50V8K 2 1 PC125 220U_25V_M 5 A 54.9K_0402_1% 1200P_0402_50V7K 2007/6/12 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2008/6/12 Deciphered Date Title SCHEMATICS, M/B S4182 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Friday, September 12, 2008 Date: Rev E 401561 5 4 3 2 Sheet 1 45 of 48 NO DATE PAGE MODIFICATION LIST PURPOSE ------------------------------------------------------------------------------------------------------------7/9 DCIN Change PL1 to bead coil link to SM010008E10 7/9 DCIN Link RTC battery symbol link to SP093MX0000 7/9 Battery conn Change PL2 to bead coil link to SM010008E10 7/9 Battery conn Change PD3,PD4 to RLS4148 For low cost 7/9 Battery conn Change PU2 pin8 to VL Design change 7/9 Charger Delete avoid PQ6 false turn-on when AC plug-in 7/9 Charger Change PQ7,PQ9 to AO4466 For low cost 7/9 Charger Change PU4 pin8 to +5VALW Design change 7/9 Charger Unpop PC28, PC37 avoid interfere by other signal 7/9 3V/5V Change PR54 and PC51 Add design margine 7/9 3V/5V Change MOSFET to AO4466+AO4712 For low cost 7/9 1.8V/1.5V Change MOSFET to AO4466+AO4712 For low cost 7/9 1.8V/1.5V Change PR75 to 2.2ohm Design change 7/9 1.05V/1.25V/0.9V Change MOSFET to AO4466+AO4712 For low cost PU3 PVCC resistor and change PC26 to 1U 7/9 1.05V/1.25V/0.9V 7/9 1.05V/1.25V/0.9V Change PU7 PVCC source to +5VS Design change 7/9 1.05V/1.25V/0.9V Change PC105,PC108 size to 0805 For low cost 7/9 CPU CORE Change input MLCC to 4pcs Design change 7/9 CPU CORE Unpop PC111 Reserve for high frequency noise 7/10 Charger Change PR38, PR39 and unpop PC32 increase resistor to reduce power loss on resistor divider 7/10 Charger Change PR45, PR47 and unpop PC41 increase resistor to reduce power loss on resistor divider 7/10 Charger Change PR43 to 100K increase resistor to reduce power loss 7/10 3V/5V Change PR65 to 100K_1% Let BOM clear 7/10 Charger/0.9V Change PQ4,PQ11,PQ12,PQ13,PQ24 to SB000009080 For low cost 8/1 Charger Change PR30 to 0.015ohm and PR38 to 80.6K Change over power protection point Change PC94 to 330U Decrease overshoot Compal Secret Data Security Classification Issued Date 2005/06/01 Deciphered Date 2006/06/01 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Compal Electronics, Inc. SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 Sheet 46 of 48 5 4 3 2 1 NO DATE PAGE MODIFICATION LIST PURPOSE ----------------------------------------------------------------------------------------------------------------------------------------------12/19 D P.6 Change C500 p/n P.6 R403, R402,R103 pull +1.8VS P.6 unpop Q32, Q33,R344,R348,C410 voltage leackage issue P.6 CPU_test21, CPU_test24 pull low 300 ohm, CPU_DBREQ#pull high 300 ohm +1.8V CPU issue P.7 C517 change p/n common part P.11 U22.B8 and U22.A8 swap HDMI I2C error P.11 R411 pull +1.8VS voltage leackage issue P.12 POP L20 , Del L19 and +1.35V ciruit fixed chipset ver:A11 issue P.15 pop R187 , del R188 fixed system unstable issue P.16 C351 type change form 0603 to 0402 common part P.17 Q3, Q26 change to BSH111 common part R273,R276 change to 2K DVI issue common part pop R80 , del R362,R357,R352,R353,R354,R355 common part change Q4,Q36,Q37,Q38 p/n P.18 B A common part change D22 p/n common part Change Q29 p/n C D C P.19 POP U11, C235, del R134 add driving P.20 add CR_PE# , CR_WAKE# net JM385 D3e function P.21 Change CRT_det pin for coding P.21 change R377 to 100k for AC LED issue P.22 POP R413, Del R415 fixed chipset ver:A11 issue P.23 change R88 to 2.2k fixed can't boot issue P.25 U30,46 connect to PCI_AD0, U30.127 connect to R434 fixed PCMCIA card P.26 add CR_PE# , CR_WAKE# net JM385 D3e function P.26 DEL L65 use J385 internal power fn. P.27 del colayout 5787 circuit for IEEE fail issue P.28 change T1 p/n common part P.29 Del TV_therm net no need in the circuit P.30 del USB_OC#1 net and C514, R413 no need in the circuit P.31 U16.76 as NC pin no need in the circuit P.31 pop C284 for KB926 C0 version P.32 change SW3, SW4 p/n and circuit ID desing change P.33 del R177 , pop R166 udpate sequency P.35 change C553,C554 to 2.2 u for audio performance issue P.35 Change JHP1 connector package ID desing change P.37 add R487,R494,R495 design change P.38 update docking pin define P.38 del R271, change R272 to 0 ohm issue B common design for DVI detect issue A Compal Secret Data Security Classification Issued Date 2007/11/08 Deciphered Date 2008/11/8 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 Sheet 1 47 of 48 5 4 3 2 1 NO DATE PAGE MODIFICATION LIST PURPOSE ----------------------------------------------------------------------------------------------------------------------------------------------- D C 1/31 P.6 POP CPU internal themal sensor schematic 1/31 P.11 change R55 to 133 ohm 1/31 P.14 Add C601 1/31 P.19 Change CRT_DET to U10.H7 D 1/31 P.33 Change R500 to D32, add R516 1/31 P.34 Change HP left and right chanel 1/31 P.36 reserve ACin sigal to power MOS 2/13 P.28 add R517 pull high at mini card 2/13 P.31 updated LED1, LED2 symbol 2/13 P.30 add R518 100k pull low on VR_ON 2/14 P.6 add R519, R520,521,522,R523,R524 in DTS 3/24 P.33 For EMI request,Change R445 to SD028100A80 3/24 P.12 Change C95,C139,C129,C44,C26,C15,C16,C17,C18 to SE000000I10 (22U) 3/24 P.19 change USB port 4/16 P.34 change R278,R280,R274,R277,R283,R286 to 47 ohm 4/16 P.6 reserve memhot# pull high 4/16 P.18 reserve prochot# pull high +3VS at S/B 4/16 P.19 reserve GPIO5 pull high at S/B 4/23 P.20 reserve R613 4/28 P.6 DTS unpop , del C410,R344, R348, R520,R522, Q32, Q33 C 4/28 P.6 del R528 , pop R527, change finger printer power 5/19 P.25 add R533,C616 delay circuit 5/19 P.23 add C614,C615 for ESD issue 6/2 P.30 board ID change 6/2 P.30 add CR_PE delay signal to card reader 7/21 P.7 add C149 and change to SGA00001Q80 for CRT issue 7/21 P.36 add Q56 , Q57 ; add for ASF B B R494 and change to SD028100480 ; add R494 and change to SD028100480 ; add R4945 and change to SD028220480 for power issue A A Compal Secret Data Security Classification Issued Date 2007/11/08 Deciphered Date 2008/11/8 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: 5 4 3 2 Compal Electronics, Inc. SCHEMATICS, M/B S4182 Document Number Rev E 401561 Friday, September 12, 2008 Sheet 1 48 of 48
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.5 Linearized : Yes Encryption : Standard V2.3 (128-bit) User Access : Print, Extract Page Count : 48 XMP Toolkit : XMP toolkit 2.9.1-13, framework 1.6 About : uuid:a89e9870-e0e3-4681-89bd-accd489a9973 Producer : Acrobat Distiller 6.0 (Windows) Create Date : 2008:09:12 09:34:38+08:00 Modify Date : 2008:09:12 09:38:57+08:00 Metadata Date : 2008:09:12 09:38:57+08:00 Document ID : uuid:00334616-0699-45bb-ae06-d27d84bf84d9 Format : application/pdf Title : untitledEXIF Metadata provided by EXIF.tools