KALG0 DD2 0427BOM 1 Compal LA 4493P
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A B C www.bufanxiu.com D E 1 1 Compal Confidential 2 2 KALH0 /KAL90+ /KALG0 M/B Schematics Document Intel Penryn Processor with Cantiga + DDRIII + ICH9M 2009-3-4 3 3 REV:1.0 4 4 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification D Title Size Document Number Custom Date: Cover Page KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 1 of 53 A B Compal Confidential C Intel Penryn Processor Fan Control Model Name : KALH0/KALG0/KAL90+ page 40 uPGA-478 Package (Socket P) page 1 HDMI Conn. LCD Conn. page 24,30 page 22 page 23 LVDS TMDS Dual Channel BANK 0, 1, 2, 3 1.5V DDRIII 800/1066 DMI USB conn x3 C-Link page 17,18,19,20,21 PCI-Express Intel ICH9-M LAN(GbE) MINI Card x2 WLAN, Robson2 Bluetooth Conn CMOS Camera Finger Print page 34 page 35 page 22 AES1610 3.3V 48MHz 2 USB page 32 page 34 page 25,26,27,28 GMCH HDA page 35 port 2 RJ45 ESATA Conn. page 35 page 33 HD Audio BGA-676 New Card Socket LS-4494P USB port 0, 2, 5 3.3V 24.576MHz/48Mhz S-ATA ATHEROS AR8121 page 13,14 page 7,8,9,10,11,12,13 page 31 2 page 16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 16X VGA ICS9LPRS387 1 uFCBGA-1329 PCI-Express Card Reader JMB385 Clock Generator EMC 1402 H_D#(0..63) Intel Cantiga LVDS Thermal Sensor 4,5,6 667/800/1066MHz CRT Conn. E page 4 FSB H_A#(3..35) www.bufanxiu.com D port 1 port 0 CDROM Conn. page 29 SATA HDD Conn. page 29 MDC 1.5 Conn page 38 page 08 HDA Codec VGA HDA ALC888S-VC page 39 page 18 Audio AMP LPC BUS page 40 3 3 Phone Jack x3 ENE KB926 page 40 page 36 RTC CKT. page 38 KALG0 page 38 DC/DC Interface CKT. page 44 Power Circuit DC/DC page 44,45,46,47,48 ,49,50,51 Int.KBD Touch Pad Media/B Conn. Power On/Off CKT. 4 KAL90+ LS-4493P LS-4498P FUN Conn. KALH0 page 37 LS-4495P EC I/O Buffer USB/B Conn. USB port 1 LS-4492P LS-4495P page 37 USB/B Conn. USB port 1 BIOS page 37 LS-4921P page 37 FUN Conn. LS-5042P E_KEY/B Conn. LED/B Conn. LS-4495P FINGERPRINT/Comm page 38 LS-5041P USB/B Conn. LS-4494P CIR 4 Media/B Conn. USB port 1 POWER SW 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification Page 43 D Title Size B Date: Document Number Block Diagrams KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 2 of 53 A B C STATE Voltage Rails 1 2 E SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON Clock ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit. N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.25VS 1.25V switched power rail ON OFF OFF +1.5V 1.5V power rail for HDA/DDR3 ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V GM LVDS MODULE ON ON OFF Vcc Ra/Rc/Re +1.8VS 1.8V switched power rail ON OFF OFF Board ID +1.1VS 1.1V switched power rail ON OFF OFF 0 1 2 3 4 5 6 7 +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail for SB ON ON X +3V_LAN 3.3V power rail for LAN ON ON X +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON +VGA_CORE Core voltage for GPU ON OFF OFF IDSEL# EC SM Bus1 address Device Address Smart Battery 0001 011X b MEDIA CONSOLE 1010 000X b REQ#/GNT# V AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Board ID 0 1 2 3 4 5 6 7 Interrupts EC SM Bus2 address Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC 2 External PCI Devices Device BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 1A BTO Item KAL90 UMA PM@ ALC888VC ALC888VB AR8121 AR8112 ALC268 GL40 GM45 KAL90-G0 KAL90-H0 KALG0 KALH0 ALC268 Address ADI ADT7421 1001 100X b NB9M THERMAL SENSOR ICH9M SM Bus address Device Address Clock Generator (ICS9LPRS387, SLG8SP556V) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb BOM Configuration Table Project KAL90-UMA KAL90-Dis KALH0-GM45 KALH0-GL40 KALH0-PM45 KAL90+ -UMA KAL90+ -Dis 1 Board ID / SKU ID Table for AD channel Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 www.bufanxiu.com D SIGNAL BOM Configuration XXXXXXXXXX:KAL90@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KAL90@/PM@/888VC@/8121@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GL40@ XXXXXXXXXX:KALH0@/PM@/888VC@/8121@ BOM Structure KAL90@ GM@ PM@ 888VC@ 888VB@ 8121@ 8112@ 268@ GL40@ GM45@ KAL90_G0@ KAL90_H0@ KALG0@ KALH0@ 268@ KAL90_90+@ KAL90_H0_G0@ KAL90+_G0 KALH0_G0 KAL90_G0_90+@ KAL90_H0_90+@ 3 KAL90+_PCB@ KALG0_PCB@ GM@/888VC@/8121@/GM45@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@ PM@/888VC@/8121@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@/PM45@ KALG0 -UMA(GL40) KALG0 -Dis KALG0@/GM@/888VC@/8121@/GL40@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0@/PM@/888VC@/8121@/PM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0 -UMA(GM45) KALG0@/GM@/888VC@/8121@/GM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0 -DIS(GM45) KALG0@/PM@/888VC@/8121@/GM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ 4 4 KALG0 LAN to AR-8131------- 8121@ Change to 8131@ 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification D Title Size B Date: Document Number Notes List KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 3 of 53 5 www.bufanxiu.com 2 1 H_A#[3..35] H_A#[3..35] H_REQ#[0..4] <7> H_REQ#[0..4] H_RS#[0..2] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 K3 H2 K2 J3 L1 H_ADSTB#0 H_ADSTB#1 <26> <26> <26> H_A20M# H_FERR# H_IGNNE# A6 A5 C4 <26> H_STPCLK# <26> H_INTR <26> H_NMI <26> H_SMI# D5 C6 B4 A3 C DEFER# DRDY# DBSY# BR0# LOCK# HIT# HITM# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# IERR# INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# <7> H_DRDY# <7> H_DBSY# <7> F1 <7> <7> <7> H_BR0# <7> H_INIT# <26> D H_IERR# D20 B3 H4 H_LOCK# <7> H_RESET# H_RS#0 H_RS#1 H_RS#2 C1 F3 F4 G3 G2 H_RESET# <7> H_TRDY# <7> G6 E4 H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 <7> <7> XDP_BPM#5 XDP_TCK XDP_TDI XDP_TMS XDP_TRST# XDP_DBRESET# C XDP_DBRESET# <27> +1.05VS THERMAL PROCHOT# THERMDA THERMDC THERMTRIP# STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 D2 D22 D3 F6 B ADS# BNR# BPRI# ICH <7> Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP_1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 JCPU1A CONTROL J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP_0 D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 XDP/ITP SIGNALS <7> H_RS#[0..2] <7> 3 H CLK BCLK[0] BCLK[1] H_PROCHOT# H_THERMDA H_THERMDC D21 A24 B25 C7 XDP_TDI R2 1 2 54.9_0402_1% XDP_TMS R3 1 2 54.9_0402_1% XDP_BPM#5 R5 1 2 54.9_0402_1% H_PROCHOT# R13 2 1 56_0402_5% H_IERR# R18 2 1 56_0402_5% XDP_TRST# R7 2 1 54.9_0402_1% XDP_TCK R8 1 2 54.9_0402_1% left NC if no ITP H_THERMTRIP# <8,26> A22 A21 @ 39Ohm CLK_CPU_BCLK <16> CLK_CPU_BCLK# <16> Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil RESERVED <7> 4 B Penryn CONN@ +3VS BSEL1 BSEL0 BCLK 0 0 0 266 1 1 1 1 R17 @ 56_0402_5% 200 166 2200P_0402_50V7K 2 H_THERMDC B E 3 1 C H_PROCHOT# A 1 C3 2 0 0 U1 H_THERMDA 2 0 +1.05VS 1 BSEL2 C2 0.1U_0402_16V4Z 1 2 OCP# VDD 2 3 4 SMDATA DN ALERT# THERM# 8 SMCLK DP EC_SMB_CK2 <18,36,37> 7 6 5 GND EC_SMB_DA2 <18,36,37> 1 2 R1133 10K_0402_5% +3VS EMC1402-1-ACZL-TR_MSOP8 <27> A Q1 MMBT3904_SOT23-3 @ Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size B Date: Compal Electronics, Inc. Document Number Penryn (1/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 4 of 53 5 4 3 H_D#[0..63] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 2 +1.05VS 1 R27 1K_0402_1% R29 2K_0402_1% R21 R22 H_DSTBN#1 H_DSTBP#1 H_DINV#1 2 2 C1477 1 @ @ @ GTL_REF0 TEST1 1K_0402_5% TEST2 1K_0402_5% TEST3 @ PAD T1 0.1U_0402_16V4Z TEST4 2 TEST5 @ PAD T2 1 1 1 Width=4 mil , Spacing: 15mil (55Ohm) 2 Trace Close CPU < 0.5' <7> <7> <7> <16> CPU_BSEL0 <16> CPU_BSEL1 <16> CPU_BSEL2 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] Penryn DATA GRP 1 C H_DSTBN#0 H_DSTBP#0 H_DINV#0 MISC D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DATA GRP 2 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DATA GRP 3 <7> <7> <7> E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP 0 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 D JCPU1B COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#[0..63] <7> +CPU_CORE H_DSTBN#2 <7> H_DSTBP#2 <7> H_DINV#2 <7> H_DSTBN#3 <7> H_DSTBP#3 <7> H_DINV#3 <7> COMP0 COMP1 COMP2 COMP3 R26 R25 R24 R23 1 1 1 1 H_PWRGOOD H_CPUSLP# 2 2 2 2 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP# <8,26,50> H_DPSLP# <26> H_DPWR# <7> H_PWRGOOD <26> H_CPUSLP# <7> PSI# <50> CONN@ TRACE CLOSELY CPU < 0.5' COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) B www.bufanxiu.com 2 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 1 JCPU1C VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] Penryn AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] +CPU_CORE D C G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] +1.05VS 20mils B26 C26 VCCA[01] VCCA[02] 1 AD6 AF5 AE5 AF4 AE3 AF3 AE2 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE AF7 VCCSENSE AE7 VSSSENSE CONN@ CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 1 R28 C7 C8 <50> <50> 0.01U_0402_16V7K <50> 2 2 <50> <50> 10U_0805_10V4Z <50> <50> 2 100_0402_1% B +CPU_CORE VCCSENSE <50> VSSSENSE <50> R30 . +1.5VS 1 1 2 100_0402_1% A A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size B Date: Compal Electronics, Inc. Document Number Penryn (2/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 5 of 53 4 1 +CPU_CORE D 1 2 + C55 900P_PFAF250E128MNTTE_2.5VM 3 4 +CPU_CORE C426 2 1 C427 2 1 C428 2 1 C429 2 1 10U_0805_6.3V6M 2 1 10U_0805_6.3V6M C425 10U_0805_6.3V6M 2 1 10U_0805_6.3V6M C416 10U_0805_6.3V6M 1 10U_0805_6.3V6M C C430 2 1 +CPU-CORE Decoupling SPCAP,Polymer MLCC 0805 X5R C,uF ESR, mohm ESL,nH 4X330uF 6m ohm/4 1.8nH/6 32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32 A + C1478 2 1 C45 2 1 C46 2 1 C47 2 1 C48 2 1 C49 2 1 C50 2 A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z CONN@ 0.1U_0402_16V4Z +1.05VS . 5 C431 2 B 0.1U_0402_16V4Z Penryn www.bufanxiu.com 2 0.1U_0402_16V4Z B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 0.1U_0402_16V4Z C VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 10U_0805_6.3V6M D JCPU1D 330U_D2E_2.5VM_R15 A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 3 10U_0805_6.3V6M 5 3 2 Title Size B Date: Compal Electronics, Inc. Document Number Penryn (3/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 6 of 53 4 3 <5> H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 D 1 +1.05VS 2 H_SWING 2 R47 221_0402_1% 1 R55 100_0402_1% width=10mil C59 0.1U_0402_16V4Z 2 1 C H_RCOMP 1 width=10mil 2 R54 24.9_0402_1% B H_SWING H_RCOMP C5 E3 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 R46 1K_0402_1% 1 1 width:spacing=10mil:20mil (<0.5") <4> H_RESET# <5> H_CPUSLP# 1 2 R52 2K_0402_1% H_RESET# H_CPUSLP# C12 E11 H_AVREF A11 B11 C58 @ 0.1U_0402_16V4Z H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_SWING H_RCOMP H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 2 +1.05VS F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 1 H_A#[3..35] <4> U2A H_D#[0..63] www.bufanxiu.com 2 HOST 5 H_CPURST# H_CPUSLP# H_RS#_0 H_RS#_1 H_RS#_2 H_AVREF H_DVREF CANTIGA ES_FCBGA1329 A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# J8 L3 Y13 Y1 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 L10 M7 AA5 AE6 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 B15 K13 F13 B13 B14 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 B6 F12 C8 H_RS#0 H_RS#1 H_RS#2 D H_ADS# <4> H_ADSTB#0 <4> H_ADSTB#1 <4> H_BNR# <4> H_BPRI# <4> H_BR0# <4> H_DEFER# <4> H_DBSY# <4> CLK_MCH_BCLK <16> CLK_MCH_BCLK# <16> H_DPWR# <5> H_DRDY# <4> H_HIT# <4> H_HITM# <4> H_LOCK# <4> H_TRDY# <4> H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 C <5> <5> <5> <5> <5> <5> <5> <5> B H_DSTBP#0 <5> H_DSTBP#1 <5> H_DSTBP#2 <5> H_DSTBP#3 <5> H_REQ#[0..4] <4> H_RS#[0..2] <4> GM45@ 2 within 100mil to Ball A11,B11 A A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size B Date: Compal Electronics, Inc. Cantiga GMCH(1/7)-GTL Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 7 of Rev 1.0 53 3 C SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 Use VGATE for GMCH_PWROK VGATE @ 1 R1139 ICH_PWROK 1 R1140 <16,27,50> VGATE <27> ICH_PWROK GMCH_PWROK 2 0_0402_5% 2 0_0402_5% MCH_CFG_12 MCH_CFG_13 MCH_CFG_16 R1143 1 R1144 1 R1145 1 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 BG22 BH21 SMRCOMP SMRCOMP# BF28 BH28 SM_RCOMP_VOH SM_RCOMP_VOL AV42 AR36 BF17 BC36 SM_PWROK SM_REXT B38 A38 E41 F41 CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 AE40 AE38 AE48 AH40 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 AE35 AE43 AE46 AH42 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 AD35 AE44 AF46 AH43 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 R34 R35 1 1 1 2 For Cantiga R33 <14> <14> <15> <15> DDR2 +1.8V +1.8V 2 80.6_0402_1% 2 80.6_0402_1% 20mil SM_VREF 1 R36 2 0_0402_5% 1 2 499_0402_1% DDR2 CLK_DREF_96M <16> CLK_DREF_96M# <16> CLK_DREF_SSC <16> CLK_DREF_SSC# <16> 1 330_0402_5% 2 B E 2 Q75 2 B MMBT3904_SOT23-3 E Q76 MMBT3904_SOT23-3 C57 0.1U_0402_16V4Z 2 <27> <27> <27> <27> DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 <27> <27> <27> <27> DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 <27> <27> <27> <27> DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 <27> <27> <27> <27> N28 M28 G36 E36 K36 H36 SDVO_SCLK SDVO_SDATA MCH_CLKREQ# B12 MCH_TSATN# 1 CL_RST#0 <27> TSATN# HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC B28 B30 B29 C29 A28 HDA_BITCLK_MCH HDA_RST_MCH# HDA_SDIN2_MCH HDA_SDOUT_MCH HDA_SYNC_MCH 1 2 1 C56 SDVO_SCLK <30> SDVO_SDATA <30> MCH_CLKREQ# <16> MCH_ICH_SYNC# <27> R43 2 2 0_0402_5% 0_0402_5% 0 = PCIe Loopback Enable 1 = Disable * (Default) 00 01 10 11 = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation * (Default) B L_DDC_DATA 0 = No SDVO Card Present * (Default) 1 = SDVO Card Present 0 = LFP Disable * (Default) 1 = LFP Card Present; PCIE disable DDPC_CTRLDATA 0 = Digital DisplayPort Disable * (Default) 1 = Digital DisplayPort Device Present MCH_CFG_5 MCH_CFG_6 MCH_CFG_9 MCH_CFG_10 MCH_CFG_12 MCH_CFG_13 MCH_CFG_16 HDA_SDIN2 <26> <26> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. @ @ @ @ @ @ @ @ 1 2.21K_0402_1% 1 4.02K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% 1 2.21K_0402_1% R73 R75 2 @ 2 @ 1 4.02K_0402_1% 1 4.02K_0402_1% +3VS Compal Electronics, Inc. Compal Secret Data 2009/12/31 2 R1146 2 R79 2 R81 2 R84 2 R86 2 R77 2 R78 2 R1149 A MCH_CFG_19 MCH_CFG_20 2 * (Default) 0 = Dynamic ODT Disabled 1 = Dynamic ODT Enabled * (Default) 0 = Normal Operation * (Default) 1 = DMI Lane Reversal Enable 0 = Only PCIE or SDVO is operational. * (Default) 1 = PCIE/SDVO are operating simu. MCH_CFG_7 Deciphered Date * (Default) CFG10 Notice: Please check HDA power rail to select HDA controller. 3 R1137 1 PM@ R1138 1 PM@ CFG9 GM45@ 2008/11/24 CLK_DREF_SSC CLK_DREF_SSC# C R44 HDA_BITCLK_MCH <26> HDA_RST_MCH# <26> GM@ 2 1 R1151 33_0402_5% HDA_SDOUT_MCH <26> HDA_SYNC_MCH 0_0402_5% 0_0402_5% 1 = iTPM Host Interface is Disabled 0 = Lane Reversal Enable 1 = Normal Operation * (Default) CFG[13:12] 0.1U_0402_16V4Z MISC DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# 2 2 0 = iTPM Host Interface is enabled CFG6 CL_CLK0 <27> CL_DATA0 <27> CL_VREF R1134 1 PM@ R1136 1 PM@ 0 = DMI x 2 1 = DMI x 4 CFG5 C34 ICH_PWROK CLK_DREF_96M CLK_DREF_96M# 011 = FSB667 010 = FSB800 000 = FSB1067 CFG[2:0] +1.05VS CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF 2 Strap Pin Table CFG20 (PCIE/SDVO select) AH37 AH36 AN36 AJ35 AH34 1 as close as possible to the related balls SDVO_CTRLDATA GFX_VR_EN D SM_RCOMP_VOL C53 R48 1K_0402_1% @ B33 B32 G33 F33 E33 Issued Date 4 2 CFG19 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 Security Classification 5 1 2 2 +DIMM_VREF 0_0402_5% 2 ME CANTIGA ES_FCBGA1329 HDA 2 3 2 1 C 1 C 3 2 R1152 MCH_TSATN# MCH_TSATN_EC# <36> 1 1 R1148 1K_0402_5% R1150 54.9_0402_1% A R1147 1K_0402_5% 1 +1.05VS 1 +3VS NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 NC +3VS BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 1 R1135 CLK_MCH_3GPLL <16> CLK_MCH_3GPLL# <16> DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 C54 C51 R45 1K_0402_1% @ R37 2 1 3.01K_0402_1% 80 Ohm 2 1 0.01U_0402_16V7K BD17 AY17 BF15 AY13 <14> <14> <15> <15> C52 2.2U_0603_6.3V6K DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# SM_DRAMRST# would be needed for DDR3 only 2 <17,25,27,31,32,36> PLT_RST# <4,26> H_THERMTRIP# <27,50> PM_DPRSLPVR 2 0_0402_5% 2 0_0402_5% PM R1141 1 R1142 1 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 BA17 AY16 AV16 AR13 R32 <14> <14> <15> <15> CFG16 B <27> PM_SYNC# <5,26,50> H_DPRSTP# <14> PM_EXTTS#0 <15> PM_EXTTS#1 DMI R29 B7 N33 P32 AT40 AT11 T20 R32 MCH_CFG_9 MCH_CFG_10 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 GRAPHICS VID PM_SYNC#_R PM_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 GMCH_PWROK 2 100_0402_5% MCH_RSTIN# THERMTRIP#_R 2 0_0402_5% DPRSLPVR_R 2 0_0402_5% MCH_CFG_5 MCH_CFG_6 MCH_CFG_7 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 CFG MCH_CFG_19 MCH_CFG_20 2 PM_EXTTS#0 10K_0402_5% 2 PM_EXTTS#1 10K_0402_5% 2 MCH_CLKREQ# 10K_0402_5% 1 R38 1 R39 1 R40 +3VS MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 <16> MCH_CLKSEL0 <16> MCH_CLKSEL1 <16> MCH_CLKSEL2 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 SM_RCOMP_VOH 1 0.01U_0402_16V7K SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BC28 AY28 AY36 BB36 R31 1K_0402_1% <14> <14> <15> <15> 2 1 1K_0402_1% SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# 2 SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 AR24 AR21 AU24 AV20 <14> <14> <15> <15> 1 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 2 RSVD22 RSVD23 RSVD24 RSVD25 CLK BG23 BF23 BH18 BF18 RSVD20 SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 AP24 AT21 AV24 AU20 DDR2 1 AY21 RSVD15 RSVD16 RSVD17 RSVD B31 B2 M1 1 +1.8V 1K_0402_1% All RSVD balls on GMCH should be left No Connect. SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 COMPENSATION D RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 DDR CLK/ CONTROL/ M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 www.bufanxiu.com 2 DDR2 U2B 2.2U_0603_6.3V6K 4 511_0402_1% 5 Title Cantiga GMCH(2/7)-DMI/DDR Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet 8 of 53 Rev 1.0 4 B DDRB_SDQ[0..63] DDRB_SDM[0..7] DDRB_SMA[0..14] D SA_BS_0 SA_BS_1 SA_BS_2 SA_RAS# SA_CAS# SA_WE# BD21 BG18 AT25 DDRA_SBS0# <14> DDRA_SBS1# <14> DDRA_SBS2# <14> BB20 BD20 AY20 DDRA_SRAS# <14> DDRA_SCAS# <14> DDRA_SWE# <14> AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 A SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 MEMORY SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> <14> U2E AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 SB_RAS# SB_CAS# SB_WE# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 B U2D AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SYSTEM C <15> DDRB_SMA[0..14] 1 MEMORY DDRA_SMA[0..14] <14> DDRA_SMA[0..14] DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 <15> DDRB_SDM[0..7] DDR D <15> DDRB_SDQ[0..63] DDRA_SDM[0..7] <14> DDRA_SDM[0..7] www.bufanxiu.com 2 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SYSTEM DDRA_SDQ[0..63] <14> DDRA_SDQ[0..63] 3 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 DDR 5 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 CANTIGA ES_FCBGA1329 GM45@ BC16 BB17 BB33 DDRB_SBS0# <15> DDRB_SBS1# <15> DDRB_SBS2# <15> AU17 BG16 BF14 DDRB_SRAS# <15> DDRB_SCAS# <15> DDRB_SWE# <15> AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 C DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> <15> B CANTIGA ES_FCBGA1329 GM45@ A A Compal Secret Data Security Classification 2008/03/28 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size B Date: Compal Electronics, Inc. Cantiga GMCH(3/7)-DDR Document Number KAL90 Monday, April 27, 2009 Sheet 1 9 of Rev 0.1 53 5 4 3 www.bufanxiu.com 2 1 U2C <22> GMCH_LCD_CLK <22> GMCH_LCD_DATA <22> GMCH_ENVDD D R1155 1 GM@ L32 G32 M32 M33 K33 J33 M29 C44 B43 E37 E38 GMCH_TXCLKGMCH_TXCLK+ C41 C40 B37 A37 GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2- H47 E46 G40 A40 GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+ H48 D45 F40 B40 <22> GMCH_TXCLK<22> GMCH_TXCLK+ <22> GMCH_TXOUT0<22> GMCH_TXOUT1<22> GMCH_TXOUT2<22> GMCH_TXOUT0+ <22> GMCH_TXOUT1+ <22> GMCH_TXOUT2+ A41 H38 G37 J37 B42 G38 F37 K37 C PEG_COMPI PEG_COMPO LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 Change to 0Ohm when use PM chip GMCH_TV_COMPS GMCH_TV_LUMA 2 1 C31 E32 Change to 0Ohm when use PM chip <23> GMCH_CRT_B <23> GMCH_CRT_R B <23> GMCH_CRT_HSYNC <23> GMCH_CRT_VSYNC +3VS R1164 1 GM@ 2 2.2K_0402_5% GMCH_LCD_CLK R1166 1 GM@ 2 2.2K_0402_5% GMCH_LCD_DATA R1167 1 GM@ 2 10K_0402_5% LCTLB_DATA R1168 1 GM@ 2 10K_0402_5% LCTLA_CLK R1169 1 GM@ 2 2.2K_0402_5% GMCH_CRT_CLK R1170 1 GM@ 2 2.2K_0402_5% GMCH_CRT_DATA 1 1 1 150_0402_1% G28 150_0402_1% J28 150_0402_1% G29 GMCH_CRT_CLK GMCH_CRT_DATA <23> GMCH_CRT_CLK <23> GMCH_CRT_DATA 2 R1162 PM@ 1 2 R1163 PM@ 1 CRT_IREF 0_0402_5% H32 J32 J29 E29 L29 0_0402_5% TV_DCONSEL_0 TV_DCONSEL_1 CRT_BLUE PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 CRT_GREEN CRT_RED CRT_IRTN VGA 2 GM@ R1159 2 GM@ R1160 2 GM@ R1161 <23> GMCH_CRT_G E28 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC PEG_COMP 10mils R57 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 1 C1290 1 C1292 1 C1294 1 C1296 1 C1298 1 C1300 1 C1302 1 C1304 1 C1306 1 C1308 1 C1310 1 C1312 1 C1314 1 C1316 1 C1318 1 C1320 1 2 +1.05VS 49.9_0402_1% PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_GTX_C_MRX_N[0..15] PCIE_GTX_C_MRX_P[0..15] HDMI_PCIE_MTX_C_GRX_N[0..3] HDMI_PCIE_MTX_C_GRX_P[0..3] PCIE_MTX_C_GRX_N[0..15] <17> D PCIE_MTX_C_GRX_P[0..15] <17> PCIE_GTX_C_MRX_N[0..15] <17> PCIE_GTX_C_MRX_P[0..15] <17> HDMI_PCIE_MTX_C_GRX_N[0..3] <30> HDMI_PCIE_MTX_C_GRX_P[0..3] <30> CLOSE SPLIT POINT PCIE_MTX_GRX_N0 1 2 HDMI_PCIE_MTX_C_GRX_N0 GM@ C1321 0.1U_0402_16V7K PCIE_MTX_GRX_N1 1 2 HDMI_PCIE_MTX_C_GRX_N1 GM@ C1322 0.1U_0402_16V7K PCIE_MTX_GRX_N2 1 2 HDMI_PCIE_MTX_C_GRX_N2 GM@ C1323 0.1U_0402_16V7K PCIE_MTX_GRX_N3 1 2 HDMI_PCIE_MTX_C_GRX_N3 GM@ C1324 0.1U_0402_16V7K PCIE_MTX_GRX_P0 1 2 HDMI_PCIE_MTX_C_GRX_P0 GM@ C1325 0.1U_0402_16V7K PCIE_MTX_GRX_P1 1 2 HDMI_PCIE_MTX_C_GRX_P1 GM@ C1326 0.1U_0402_16V7K PCIE_MTX_GRX_P2 1 2 HDMI_PCIE_MTX_C_GRX_P2 GM@ C1327 0.1U_0402_16V7K PCIE_MTX_GRX_P3 1 2 HDMI_PCIE_MTX_C_GRX_P3 GM@ C1328 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3 2 1 TMDS_B_HPD# <30> R1171 GM@ 0_0402_5% C C1289 1 2 PM@ 0.1U_0402_16V7K C1291 1 2 PM@ 0.1U_0402_16V7K C1293 1 0.1U_0402_16V7K 2 PM@ C1295 1 2 PM@ 0.1U_0402_16V7K C1297 1 2 PM@ 0.1U_0402_16V7K C1299 1 PM@ 0.1U_0402_16V7K 2 C1301 1 2 PM@ 0.1U_0402_16V7K C1303 1 2 PM@ 0.1U_0402_16V7K 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 C1305 1 2 PM@ 0.1U_0402_16V7K C1307 1 2 PM@ 0.1U_0402_16V7K C1309 1 2 PM@ 0.1U_0402_16V7K C1311 1 2 PM@ 0.1U_0402_16V7K C1313 1 PM@ 0.1U_0402_16V7K 2 C1315 1 2 PM@ 0.1U_0402_16V7K C1317 1 2 PM@ 0.1U_0402_16V7K C1319 1 2 PM@ 0.1U_0402_16V7K 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PM@ 0.1U_0402_16V7K 2 PCIE_MTX_C_GRX_P5 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 2 PM@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 B 2 1 TV_DCONSEL_0 TV_DCONSEL_1 TV_RTN PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 T37 T36 R1165 1.02K_0402_1% GM@ CANTIGA ES_FCBGA1329 GM45@ 1 2 H24 R108 R93 75_0402_1% 75_0402_1% GM@ GM@ 1 R107 75_0402_1% GM@ TVA_DAC TVB_DAC TVC_DAC TV 2 GMCH_TV_CRMA F25 H25 K25 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 LVDS LVDS_IBG 2.37K_0402_1% 2 1 R1153 GM@ 0_0402_5% 2 L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN GRAPHICS ENBKL LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA PCI-EXPRESS <18,36> <22> DPST_PWM 1 2 R1154 GM@ 0_0402_5% A A R1173 1 2 100K_0402_5% Compal Secret Data Security Classification LBKLT_EN 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Cantiga GMCH(4/7)-VGA/LVDS/TV Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 10 of 53 5 4 U2F A 1 U2G C125 AG34 AC34 AB34 AA34 Y34 V34 U34 AM33 AK33 AJ33 AG33 AF33 2 1 + C1485 GM@ C1482 GM@ 2 C1483 GM@ 2 C1484 GM@ 2 1 C1480 GM@ 2 AE33 AC33 AA33 Y33 W33 V33 U33 AH28 AF28 AC28 AA28 AJ26 AG26 AE26 AC26 AH25 AG25 AF25 AG24 AJ23 AH23 AF23 T32 0.1U_0402_16V4Z C1481 GM@ 2 1 0.1U_0402_16V4Z C1479 GM@ 1 10U_0805_10V4Z R1175 PM@ 10U_0805_10V4Z 2 2 1 Cavity Capacitors 330U_D2E_2.5VM_R15 1 J2 @ JUMP_43X79 0_0402_5% 1 1 1U_0402_6.3V6K 2 0.47U_0603_16V4Z 1 2 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 C +1.05VS Place close to the GMCH 2 1 C123 2 NCTF 2 1 C130 VCC 2 1 C122 DDR2 0.1U_0402_16V4Z + C126 10U_0805_10V4Z 1 VCC_SM: 2600mA (330UF*1, 22UF*2, 0.1UF*1) 10U_0805_10V4Z +1.8V Place on the edge Reference PILLAR_ROCK CRB Rev1.0 VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7 AV44 BA37 AM40 AV21 AY5 AM10 BB13 VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7 1 C139 GM45@ 1 C1490 @ 2 0.1U_0402_16V7K 1 C1489 @ 2 0.1U_0402_16V7K 1 C1488 @ 2 0.1U_0402_16V7K 1 C1487 @ 2 0.1U_0402_16V7K 1 C1486 @ 2 0.1U_0402_16V7K VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 VCC_SM_AW16 VCC_SM_AT13 CANTIGA ES_FCBGA1329 C140 1 2 C141 1 2 C142 1 2 C143 1 2 C144 1 2 C145 1 2 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8 VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44 AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23 B GM45@ A Compal Electronics, Inc. Compal Secret Data Security Classification 5 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 POWER C133 0.1U_0402_16V4Z 0.22U_0402_6.3V6K 0.22U_0402_6.3V6K 10U_0805_10V4Z 220U_D2_4VM_R15 C132 VCC_AXG: 6326.84mA (330UF*2, 22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2) +VGFX_CORE 1 2 R1174 GM@ 0_0805_5% 2 CANTIGA ES_FCBGA1329 2 2 330U_D2E_2.5VM_R15 VCC VCC_AXG_SENSE VSS_AXG_SENSE 2 C124 1U_0402_6.3V6K AJ14 AH14 1 + C131 1U_0402_6.3V6K VCC_AXG_SENSE VSS_AXG_SENSE 1 0.47U_0603_16V4Z PAD PAD J1 @ JUMP_43X79 1 +1.05VS GFX @ T4 @ T5 D +1.05VS Cavity Capacitors 0.22U_0402_6.3V6K B VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC: 1930.4mA (GMCH), 1210.34mA (MCH) (270UF*1, 22UF*1, 0.22UF*2, 0.1UF*1) +1.05VS VCC Y26 AE25 AB25 AA25 AE24 AC24 AA24 Y24 AE23 AC23 AB23 AA23 AJ21 AG21 AE21 AC21 AA21 Y21 AH20 AF20 AE20 AC20 AB20 AA20 T17 T16 AM15 AL15 AE15 AJ15 AH15 AG15 AF15 AB15 AA15 Y15 V15 U15 AN14 AM14 U14 T14 Place close to the GMCH 0.22U_0402_6.3V6K +VGFX_CORE W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16 0.1U_0402_16V7K VCC_SM_AT13 VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC POWER VCC_SM_AW16 BA36 BB24 BD16 BB21 AW16 AW13 AT13 VCC_AXG_NTCF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8 VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55 VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60 0.1U_0402_16V7K C VCC_SM_BA36 VCC_SM_BB24 VCC_SM_BD16 1 VCC CORE GFX NCTF SM Pins BA36, BB24, BD16, BB21, AW16, AW13, AT13 could be left NC for DDR2 board. VCC Reference PILLAR_ROCK CRB Rev1.0 2600mA VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC SM LF D www.bufanxiu.com 2 +VGFX_CORE +1.8V AP33 AN33 BH32 BG32 BF32 BD32 BC32 BB32 BA32 AY32 AW32 AV32 AU32 AT32 AR32 AP32 AN32 BH31 BG31 BF31 BG30 BH29 BG29 BF29 BD29 BC29 BB29 BA29 AY29 AW29 AV29 AU29 AT29 AR29 AP29 3 2 Title Cantiga GMCH(5/7)-VCC Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet 11 of Rev 1.0 53 5 4 3 +1.05VS_HPLL No CIS Symbol +1.05VS_PEGPLL VCCA_PEG_PLL: 1 C1504 L21 1 2 MBK1608221YZF_0603 2 1 1 2 C1503 R1181 10U_0805_6.3V6M 1_0402_1% +1.05VS Close to Ball A26, B27 (0.1UF*1) 2 +1.05VS_A_SM Please check Power source if want support IAMT VCCA_DAC_BG: 2.6833333mA (0.1UF*1, 0.01UF*1) 1 2 R100 0_0805_5% +3VS_DACBG 1 2 R103 0_0603_5% 1 R1184 0_0402_5% PM@ 1 0.1U_0402_16V4Z C96 1 +1.05VS_A_SM_CK 1 VCCA_SM_CK: 24mA (22UF*1, 2.2UF*1, 0.1UF*1) VCCA_TV_DAC: 40mA (0.1UF*1, 0.01UF*1 for each DAC) 1 1 C102 C103 C105 @ 2.2U_0603_6.3V6K 0.1U_0402_16V4Z 2 2 2 22U_0805_6.3V6M NO_STUFF +1.5VS VCCD_HDA: 50mA (0.1UF*1) +1.5VS_HDA 1 2 R1188 GM@ 0_0402_5% R1189 0_0402_5% PM@ 1 R1187 0_0402_5% PM@ A32 1 C1518 Close to A32 GM@ 0.1U_0402_16V4Z 2 +1.5VS_TVDAC M25 +1.5VS_QDAC L28 2 1 1 C1517 C1516 GM@ GM@ 0.1U_0402_16V4Z 2 2 0.01U_0402_16V7K 1 L24 1 2 MBK1608221YZF_0603 2 +3VS 180Ohm@100MHzGM@ B24 A24 +3VS_TVDAC +3VS_TVDAC +1.05VS_HPLL 1 2 L25 MBK1608221YZF_0603 C1520 1 C1521 1 180Ohm@100MHz 1 C1525 +1.5VS_QDAC 1 0.1U_0402_16V4Z 2 2 0.01U_0402_16V7K M38 L37 1 2 R1191 GM@ 0_0603_5% 1 C1522 GM@ 10U_0805_6.3V6M 2 R1195 0_0402_5% @ VTT 2 C81 1 2 0.47U_0603_16V4Z 1 2.2U_0603_6.3V6K 4.7U_0805_10V4Z 4.7U_0805_10V4Z 220U_D2_4VM_R15 CRT 24mA VCCA_TV_DAC_1 VCCA_TV_DAC_2 50mA VCCD_TVDAC 48.363mA VCCD_QDAC 157.2mA VCCD_HPLL 50mA VCCD_PEG_PLL 60.31mA VCCD_LVDS_1 VCCD_LVDS_2 VCC_AXF_1 VCC_AXF_2 VCC_AXF_3 VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4 118.8mA VCC_TX_LVDS 105.3mA VCC_HV_1 VCC_HV_2 VCC_HV_3 1782mA 87.79mA 1 C1523 GM@ 1U_0402_6.3V6K 2 D Please check Power source if want support IAMT 1 2 R1180 0_0603_5% +1.05VS 1U_0402_6.3V6K 2 VCC_SM_CK: 119.85mA (10UF*1, 0.1UF*1) 1uH 30% VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5 456mA VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4 1 2 BF21 BH20 BG20 BF20 C35 B35 A35 VCC_HV: 105.3mA 1 2 V48 U48 V47 U47 U46 +3VS +1.8V_TX_LVDS 0.1uH 20% 1 2 R1183 GM@ 1 0_0603_5% C1512 C1513 GM@ GM@ 1000P_0402_50V7K 2 2 10U_0805_10V4Z +1.8V 1 C107 Please check Power source if want support IAMT 0.1U_0402_16V4Z +1.05VS_PEG: 1782mA +1.05VS_PEG (220UF*1, 22UF*1, 4.7UF*1) 1 1 + C1515 C1514 10U_0805_10V4Z 2 AH48 AF48 AH47 AG47 1 2 1 2 R1182 C1508 1_0402_1% 10U_0805_6.3V6M 0.1U_0402_16V4Z R1185 PM@ 0_0402_5% +1.05VS_DMI VCC_DMI: 456mA (0.1UF*1) 1 2 VTTLF1 VTTLF2 VTTLF3 1 2 +1.8V L22 MBK1608121YZF_0603 C1507 +1.8V_TX_LVDS: 118.8mA (22UF*1, 1000PF*1) K47 DDR2 C1519 2 1 R1186 0_0805_5% 2 +1.05VS B 220U_D2_4VM_R15 +1.05VS 1 2 R1190 0_0805_5% 0.1U_0402_16V4Z VTTLF_CAP1 A8 VTTLF_CAP2 L1 AB2 VTTLF_CAP3 C110 1 C111 1 C112 1 0.47U_0603_16V4Z 0.47U_0603_16V4Z 2 2 2 0.47U_0603_16V4Z GM45@ R1192 0_0402_5% PM@ 2 2008/11/24 Issued Date 3 A R1194 D8 +1.05VS 1 1 2 +3VS 10_0603_5% CH751H-40PT_SOD323-2 Compal Electronics, Inc. Compal Secret Data Security Classification 4 1 C1506 B22 B21 A21 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 2 C82 C CANTIGA ES_FCBGA1329 +1.8V_LVDS 1 VCC_AXF: 321.35mA (10UF*1, 1UF*1) 1 C1505 @ 10U_0805_6.3V6M 2 VCCD_LVDS: 60.311111mA (1UF*1) 1 C1524 +1.8V 2 +1.5VS 1 2 R1193 100_0603_1% AA47 VCCD_PEG_PLL: 50mA (0.1UF*1) Also power for internal Thermal Sensor VCCD_QDAC: 48.363mA (0.1UF*1, 0.01UF*1) AF1 +1.05VS_PEGPLL Please check Power source if want support IAMT 0.1U_0402_16V4Z 2 2 0.022U_0402_16V7K A VCCD_HPLL: 157.2mA (0.1UF*1) C80 +1.8V_SM_CK VCCA_SM_CK_1 VCCA_SM_CK_2 VCCA_SM_CK_3 VCCA_SM_CK_4 VCCA_SM_CK_5 VCCA_SM_CK_NCTF_1 VCCA_SM_CK_NCTF_2 VCCA_SM_CK_NCTF_3 VCCA_SM_CK_NCTF_4 VCCA_SM_CK_NCTF_5 VCCA_SM_CK_NCTF_6 VCCA_SM_CK_NCTF_7 VCCA_SM_CK_NCTF_8 58.696mA 1 2 +1.05VS_AXF POWER 480mA VCCA_SM_1 VCCA_SM_2 VCCA_SM_3 VCCA_SM_4 VCCA_SM_5 VCCA_SM_6 VCCA_SM_7 VCCA_SM_8 VCCA_SM_9 VCC_HDA 2 C72 1 +1.5VS +1.5VS_TVDAC 50mA VCCA_PEG_PLL + 2 VCCD_TVDAC: 58.696mA (0.1UF*1, 0.01UF*1) AR20 AP20 AN20 AR17 AP17 AN17 AT16 AR16 AP16 AP28 AN28 AP25 AN25 AN24 AM28 AM26 AM25 AL25 AM24 AL24 AM23 AL23 1 Close to Ball A25 B 0.414mA VCCA_PEG_BG 50mA C97 4.7U_0805_10V4Z 2 2 2 22U_0805_6.3V6M 1U_0402_6.3V6K Please check Power source if want support IAMT +1.05VS 2 L23 GM@ MBK1608221YZF_0603 1 1 1 C1509 C1510 C1511 GM@ GM@ GM@ 0.1U_0402_16V4Z 10U_0805_6.3V6M 2 2 2 0.01U_0402_16V7K C95 + C94 @ 220U_D2_4VM_R15 2 2 1 +3VS 1 AA48 VCCA_SM: (22UF*2, 4.7UF*1, 1UF*1) C +1.05VS AD48 VSSA_LVDS 1 C71 1 VCCA_PEG_BG: 0.414mA (0.1UF*1) C89 0.1U_0402_16V4Z 2 13.2mA VCCA_LVDS U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1 2 1 R1179 0_0402_5% PM@ 2 C1502 GM@ 0.01U_0402_16V7K 2 1 Please check Power source if want support IAMT +3VS 1 J47 AXF J48 139.2mA VCCA_MPLL HV VCCA_LVDS: 13.2mA (1000PF*1) +VCCA_PEG_BG 24mA VCCA_HPLL PEG VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1) +1.5VS R97 0_0402_5% 1 2 1 C1499 GM@ 1000P_0402_50V7K 2 VCCA_DPLLB DMI +1.05VS_MPLL AE1 VTTLF AD1 PLL +1.05VS_HPLL +1.8V_TX_LVDS 64.8mA VCCA_DPLLA A PEG A LVDS +3VS_CRTDAC +3VS R96 @ 0_0402_5% 1 2 L48 VSSA_DAC_BG SM CK F47 VCCA_DAC_BG A CK C1498 22U_0805_6.3V6M 2 1 2 L20 GM@ MBK1608301YZF_0603 1 C1500 1 GM@ + C1501 0.1U_0402_16V4Z 2 GM@ 220U_D2_4VM_R15 2 1 1 C1497 R1178 GM@ 0_0402_5% C1496 PM@ +1.05VS_DPLLA 2 2 10U_0805_10V4Z GM@ 0.1U_0402_16V4Z +1.05VS_DPLLB 2 1 B25 A SM 2 0.1U_0402_16V4Z A25 +3VS_DACBG 2 2.69mA TV 1 L18 GM@ 0_1210_5% VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VCCA_CRT_DAC_1 VCCA_CRT_DAC_2 HDA +1.05VS_DPLLB 1 C1495 B27 A26 D TV/CRT 2 R1177 0.5_0603_1% www.bufanxiu.com VTT: 852mA (270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1) +1.05VS 852mA 73mA LVDS 1 L19 1 2 MBK1608121YZF_0603 VCCA_MPLL: 139.2mA (22UF*1, 0.1UF*1) U2H 1 1 C1494 R1176 + C1493 GM@ 0_0402_5% GM@ PM@ 2 220U_D2_4VM_R15 +3VS_CRTDAC 2 0.1U_0402_16V4Z VCCA_DPLLA VCCA_DPLLB: 64.8mA (220UF*1, 0.1UF*1) Please check Power source if want support IAMT 120Ohm@100MHz 2 1 C1492 1 L17 GM@ 0_1210_5% +1.05VS 4.7U_0805_10V4Z 2 2 0.1U_0402_16V4Z +1.05VS_MPLL D 1 2 (4.7UF*1, 0.1UF*1) Please check Power source if want support IAMT 1 +1.05VS_DPLLA +1.05VS 1 L16 1 2 MBK1608121YZF_0603 1 C1491 VCCA_HPLL: 24mA 2 2 Title Crestline GMCH (6/7)-VCC Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet 12 of Rev 1.0 53 5 4 3 C B VSS VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23 AJ6 BG21 L12 AW21 AU21 AP21 AN21 AH21 AF21 AB21 R21 M21 J21 G21 BC20 BA20 AW20 AT20 AJ20 AG20 Y20 N20 K20 F20 C20 A20 BG19 A18 BG17 BC17 AW17 AT17 R17 M17 H17 C17 BA16 AU16 AN16 N16 K16 G16 E16 BG15 AC15 W15 A15 BG14 AA14 C14 BG13 BC13 BA13 AN13 AJ13 AE13 N13 L13 G13 E13 BF12 AV12 AT12 AM12 AA12 J12 A12 BD11 BB11 AY11 AN11 AH11 Y11 N11 G11 C11 BG10 AV10 AT10 AJ10 AE10 AA10 M10 BF9 BC9 AN9 AM9 AD9 G9 B9 BH8 BB8 AV8 AT8 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS VSS_235 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_351 VSS_352 VSS_353 VSS_354 VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS NCTF D VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS SCB AU48 AR48 AL48 BB47 AW47 AN47 AJ47 AF47 AD47 AB47 Y47 T47 N47 L47 G47 BD46 BA46 AY46 AV46 AR46 AM46 V46 R46 P46 H46 F46 BF44 AH44 AD44 AA44 Y44 U44 T44 M44 F44 BC43 AV43 AU43 AM43 J43 C43 BG42 AY42 AT42 AN42 AJ42 AE42 N42 L42 BD41 AU41 AM41 AH41 AD41 AA41 Y41 U41 T41 M41 G41 B41 BG40 BB40 AV40 AN40 H40 E40 AT39 AM39 AJ39 AE39 N39 L39 B39 BH38 BC38 BA38 AU38 AH38 AD38 AA38 Y38 U38 T38 J38 F38 C38 BF37 BB37 AW37 AT37 AN37 AJ37 H37 C37 BG36 BD36 AK15 AU36 www.bufanxiu.com 2 1 U2J NC U2I CANTIGA ES_FCBGA1329 GM45@ NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42 AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4 D BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1 C U24 U28 U25 U29 AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17 B BH48 BH1 A48 C1 A3 E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48 CANTIGA ES_FCBGA1329 GM45@ A A 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Compal Electronics, Inc. Compal Secret Data Security Classification 2 Title Cantiga GMCH(1/7)-GTL Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet 13 of Rev 1.0 53 5 4 +1.8V 3 +1.8V DDRA_SDQ2 DDRA_SDQ3 D DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQS1# DDRA_SDQS1 <9> DDRA_SDQS1# <9> DDRA_SDQS1 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2 <9> DDRA_SDQS2# <9> DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 C DDRA_CKE0 <8> DDRA_CKE0 DDRA_SBS2# <9> DDRA_SBS2# DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1 DDRA_SMA10 DDRA_SBS0# DDRA_SWE# <9> DDRA_SBS0# <9> DDRA_SWE# DDRA_SCAS# DDRA_SCS1# <9> DDRA_SCAS# <8> DDRA_SCS1# DDRA_ODT1 <8> DDRA_ODT1 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4# DDRA_SDQS4 <9> DDRA_SDQS4# <9> DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ41 B DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6# DDRA_SDQS6 <9> DDRA_SDQS6# <9> DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58 DDRA_SDQ59 D_CK_SDATA D_CK_SCLK <15> D_CK_SDATA <15> D_CK_SCLK +3VS 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 +DIMM_VREF DDRA_SDQ4 DDRA_SDQ5 1 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 20mils R1196 DDRA_SDM0 1 DDRA_SDQ6 DDRA_SDQ7 2 DDRA_SDQ12 DDRA_SDQ13 1K_0402_1% C151 20mils 2 <9> DDRA_SDQS0# <9> DDRA_SDQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS To SODIMM and GMCH +DIMM_VREF 0.1U_0402_16V4Z 1 DDRA_SDQS0# DDRA_SDQS0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 D R1197 DDRA_SDM1 1K_0402_1% 2 DDRA_SDQ0 DDRA_SDQ1 1 +1.8V JDIMM1 +DIMM_VREF www.bufanxiu.com 2 DDRA_CLK0 <8> DDRA_CLK0# <8> DDRA_SDQ14 DDRA_SDQ15 DDRA_SMA[0..14] <9> DDRA_SMA[0..14] DDRA_SDQ[0..63] <9> DDRA_SDQ[0..63] DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2 DDRA_SDM[0..7] <9> DDRA_SDM[0..7] +1.8V PM_EXTTS#0 <8> DDRA_SDQ22 DDRA_SDQ23 C152 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQS3# DDRA_SDQS3 +0.9VS DDRA_CKE1 <8> DDRA_SMA14 DDRA_SMA11 DDRA_SMA7 DDRA_SMA6 DDRA_SMA4 DDRA_SMA2 DDRA_SMA0 DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# DDRA_ODT0 DDRA_SMA13 DDRA_ODT0 <8> DDRA_SDM4 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQS5# <9> DDRA_SDQS5 <9> DDRA_SDQ46 DDRA_SDQ47 DDRA_CLK1 <8> DDRA_CLK1# <8> DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQS7# <9> DDRA_SDQS7 <9> DDRA_SDQ62 DDRA_SDQ63 R116 1 R115 1 C153 1 C154 1 C155 1 +1.8V 4 3 56_0404_4P2R_5% DDRA_SMA12 1 DDRA_SMA9 2 RP2 4 3 56_0404_4P2R_5% DDRA_SMA8 DDRA_SMA5 1 2 4 3 56_0404_4P2R_5% 1 2 4 3 56_0404_4P2R_5% DDRA_SMA10 1 DDRA_SBS0# 2 RP5 4 3 56_0404_4P2R_5% DDRA_SWE# 1 DDRA_SCAS# 2 RP6 4 3 56_0404_4P2R_5% DDRA_SCS1# 1 DDRA_ODT1 2 RP7 4 3 56_0404_4P2R_5% DDRA_SMA14 1 DDRA_SMA11 2 RP8 4 3 56_0404_4P2R_5% DDRA_SMA7 DDRA_SMA6 1 2 4 3 56_0404_4P2R_5% 1 2 RP10 4 3 56_0404_4P2R_5% DDRA_SMA0 1 DDRA_SBS1# 2 RP11 4 3 56_0404_4P2R_5% C168 DDRA_SRAS# 1 DDRA_SCS0# 2 RP12 4 3 56_0404_4P2R_5% 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z DDRA_SMA13 1 DDRA_ODT0 2 RP13 4 3 56_0404_4P2R_5% DDRA_CKE1 2 56_0402_5% DDRA_SMA4 DDRA_SMA2 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQS7# DDRA_SDQS7 1 DDRA_CKE0 1 DDRA_SBS2# 2 RP1 DDRA_SMA3 DDRA_SMA1 DDRA_SBS1# <9> DDRA_SRAS# <9> DDRA_SCS0# <8> DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQS5# DDRA_SDQS5 C147 DDRA_SDQS3# <9> DDRA_SDQS3 <9> DDRA_SDQ30 DDRA_SDQ31 DDRA_CKE1 1 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2 2 2 2 2 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K RP3 RP4 RP9 1 R1198 C156 1 C148 1 C149 1 C157 C 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS C158 1 C159 1 C160 1 C161 1 C162 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS C163 1 1 C164 C165 1 C166 1 C167 1 B 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS 1 C169 1 C170 1 2 10K_0402_5% 2 10K_0402_5% FOX_ASOA426-M4R-TR A +3VS C171 1 A CONN@ C172 1 DIMM1 REV H:5.6mm (BOT) 0.1U_0402_16V4Z 2 2 2.2U_0603_6.3V6K 2008/03/28 Issued Date 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Compal Electronics, Inc. Compal Secret Data Security Classification 2 Title Size B Date: Document Number DDRII-SODIMM0 KAL90 Monday, April 27, 2009 1 Sheet 14 Rev 0.1 of 53 A B C +DIMM_VREF +1.8V DDRB_SDQ0 DDRB_SDQ5 1 <9> DDRB_SDQS0# <9> DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS0 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ8 DDRB_SDQ9 <9> DDRB_SDQS1# <9> DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS1 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ16 DDRB_SDQ17 <9> DDRB_SDQS2# <9> DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS2 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDM3 DDRB_SDQ26 DDRB_SDQ27 2 <8> DDRB_CKE0 <9> DDRB_SBS2# DDRB_CKE0 DDRB_SBS2# DDRB_SMA12 DDRB_SMA9 DDRB_SMA8 DDRB_SMA5 DDRB_SMA3 DDRB_SMA1 <9> DDRB_SBS0# <9> DDRB_SWE# <9> DDRB_SCAS# <8> DDRB_SCS1# <8> DDRB_ODT1 DDRB_SMA10 DDRB_SBS0# DDRB_SWE# DDRB_SCAS# DDRB_SCS1# DDRB_ODT1 DDRB_SDQ32 DDRB_SDQ33 <9> DDRB_SDQS4# <9> DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS4 DDRB_SDQ34 DDRB_SDQ35 3 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDM5 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ48 DDRB_SDQ49 <9> DDRB_SDQS6# <9> DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS6 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDM7 DDRB_SDQ58 DDRB_SDQ59 <14> D_CK_SDATA <14> D_CK_SCLK 4 D_CK_SDATA D_CK_SCLK +3VS 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD C173 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SA0 SA1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDRB_SDQ4 DDRB_SDQ1 1 E +1.8V +1.8V JDIMM2 +DIMM_VREF www.bufanxiu.com D C182 1 1 + 2.2U_0603_6.3V6K 2 2 0.1U_0402_16V4Z 1 C1526 + 2 DDRB_SDM0 C1527 @ 2 330U_D2E_2.5VM_R15 330U_D2E_2.5VM_R15 DDRB_SDQ6 DDRB_SDQ7 1 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDM1 DDRB_CLK0 <8> DDRB_CLK0# <8> DDRB_SDQ14 DDRB_SDQ15 <9> DDRB_SMA[0..14] <9> DDRB_SDQ[0..63] DDRB_SMA[0..14] DDRB_SDQ[0..63] DDRB_SDM[0..7] <9> DDRB_SDM[0..7] DDRB_SDQ20 DDRB_SDQ21 DDRB_SDM2 PM_EXTTS#1 <8> DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQS3# DDRB_SDQS3 DDRB_SDQS3# <9> DDRB_SDQS3 <9> +0.9VS DDRB_SDQ30 DDRB_SDQ31 2 DDRB_SBS2# DDRB_CKE0 1 2 RP14 4 3 56_0404_4P2R_5% DDRB_SMA14 DDRB_SMA12 DDRB_SMA9 DDRB_SMA11 DDRB_SMA7 DDRB_SMA6 1 2 RP15 4 3 56_0404_4P2R_5% DDRB_SMA5 DDRB_SMA8 DDRB_SMA4 DDRB_SMA2 DDRB_SMA0 1 2 RP16 4 3 56_0404_4P2R_5% DDRB_SMA3 DDRB_SMA1 1 2 RP17 4 3 56_0404_4P2R_5% DDRB_SBS1# <9> DDRB_SRAS# <9> DDRB_SCS0# <8> DDRB_SMA10 DDRB_SBS0# 1 2 RP18 4 3 56_0404_4P2R_5% DDRB_ODT0 <8> DDRB_SWE# DDRB_SCAS# 1 2 RP19 4 3 56_0404_4P2R_5% DDRB_SCS1# DDRB_ODT1 1 2 RP20 4 3 56_0404_4P2R_5% DDRB_SMA11 DDRB_SMA14 1 2 RP21 4 3 56_0404_4P2R_5% DDRB_SMA6 DDRB_SMA7 1 2 RP22 4 3 56_0404_4P2R_5% DDRB_SMA2 DDRB_SMA4 1 2 RP23 4 3 56_0404_4P2R_5% DDRB_SBS1# DDRB_SMA0 1 2 RP24 4 3 56_0404_4P2R_5% DDRB_SCS0# DDRB_SRAS# 1 2 RP25 4 3 56_0404_4P2R_5% DDRB_SMA13 DDRB_ODT0 1 2 RP26 4 3 56_0404_4P2R_5% DDRB_CKE1 1 R1199 DDRB_CKE1 DDRB_CKE1 <8> DDRB_SBS1# DDRB_SRAS# DDRB_SCS0# DDRB_ODT0 DDRB_SMA13 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDM4 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQS5# DDRB_SDQS5 DDRB_SDQS5# <9> DDRB_SDQS5 <9> DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ52 DDRB_SDQ53 DDRB_CLK1 <8> DDRB_CLK1# <8> DDRB_SDM6 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQS7# DDRB_SDQS7 DDRB_SDQS7# <9> DDRB_SDQS7 <9> 2 56_0402_5% 2 10K_0402_5% 2 10K_0402_5% C174 1 C175 1 C176 1 C183 1 C177 1 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K 2 2 2 2 2 2.2U_0603_6.3V6K 2.2U_0603_6.3V6K +1.8V C178 1 C179 1 C180 1 C181 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS C184 1 C185 1 C186 1 C187 1 C188 1 3 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS C189 1 C190 1 C191 1 C192 1 C193 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z +0.9VS C194 1 C195 1 C196 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z DDRB_SDQ62 DDRB_SDQ63 R119 1 R118 1 +1.8V +3VS 4 FOX_AS0A426-N8RN-7F CONN@ DIMM2 REV H:10.1mm (BOT) 2008/03/28 Issued Date 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification D Title Size B Date: Document Number DDRII-SODIMM1 KAL90 Monday, April 27, 2009 E Sheet 15 Rev 0.1 of 53 1 0 0 0 266 100 33.3 0 1 0 200 100 33.3 0 1 1 166 100 33.3 L56 2 1 KC FBM-L11-201209-221LMAT_0805 1 1 1 C1883 C1884 C1882 10U_0805_10V4Z 2 2 2 +1.05VS Table : ICS9LPRS387 CLK_REQ# Control PCIEX10 PCIEX0 CR#_6(MCH) PCIEX6 PCIEX1 CR#_4(NEW CARD) PCIEX4 CR#_9(MINI CARDII) PCIEX9 1 2 C1886 1 2 2 GM@ 1CLK_DREF_SSC# R1827 0_0402_5% 1 2 6 27M_CLK <18> 19 CLK_DREF_SSC# <8> 72 12 CLK_DREF_SSC#_1 2 PM@ 1 R1828 0_0402_5% 27 27M_SSC <18> 55 52 +CLK_VDDSRC Must Close to CLKGEN PIN 28,29 38 62 CLK_PCI2=1, Trusted Mode Enable(No overclocking allowed) @ 1 R1585 23 C1888 1 2 C1889 1 2 VDDREF ICS9LPRS387, PN:SA000020H10 SLG8SP556V, PN:SA000020K00 1 CLK_PCI4 GM@ 2 1 R1587 10K_0402_5% VDDCPU CPUT0_LPR_F VDDPCI CPUC0_LPR_F VDDPLL3 CPUT1_LPR_F VDDSRC CPUC1_LPR_F <27> H_STP_PCI# C1899 1 @ @ 3 S CK_PWRGD For EMI 10/9 1 2 R1597 @ 1K_0402_5% CLK_PCI_ICH R1590 2 1 33_0402_5% 0_0402_5% 2 0_0402_5% 2 <27> CK_PWRGD <8,27,50> VGATE 1 R1591 1 R1592 @ CLK_PCI2 14 CLK_PCI3 15 CLK_PCI4 16 CLK_PCI5 17 CK505_PWRGD1 1 CLK_XTALIN 27P_0402_50V8J R1593 @ 56_0402_5% 1 2 R1598 0_0402_5% 54 C1901 27P_0402_50V8J 1 2 CLK_XTALOUT Y1 14.31818MHz_20P_FSX8L14.318181M20FDB 2 2 1 3 H_STP_PCI# 1 33_0402_5% C1900 1 2 R1595 1K_0402_5% 1 2 53 13 CLK_PCI_LPC R1589 2 +1.05VS R1594 2.2K_0402_5% CLKSEL0 1 2 H_STP_CPU# CLK_ENABLE# <50> <25> CLK_PCI_ICH 10P_0402_50V8J CLK_PCI_ICH 2 CPU_BSEL0 <5> <27> CLK_ICH_48M CLK_ICH_48M R1596 2 1 33_0402_5% CLK_ICH_14M R1599 2 1 3 1 33_0402_5% 20 2 CLKSEL2 A 7 S CPU_BSEL1 <5> 3 18 D_CK_SDATA 22 30 +3VS 1 3 S <27,32,34,35> ICH_SMBCLK 26 R1608 4.7K_0402_5% 1 2 +3VS 2 G 1 2 R1613 0_0402_5% 69 Q107 2N7002_SOT23 D 2 1 2 R1612 @ 0_0402_5% 11 CLKSEL1 R1602 4.7K_0402_5% 1 2 +3VS 2 G MCH_CLKSEL1 <8> <27,32,34,35> ICH_SMBDATA R1609 @ 1K_0402_5% R1611 1K_0402_5% 1 2 VDDPLL3_IO 27MHz_NonSS/SRCT1_LPR/SE1 VDDCPU_IO 27MHz_SS/SRCC1_LPR/SE2 VDD96_IO SRCT2_LPR/SATAT_LPR SRCC2_LPR/SATAC_LPR CPU_STOP# PCI_STOP# SRCT3_LPR PCI1 SRCT4_LPR PCI2/TME SRCC4_LPR PCI3 SRCT6_LPR PCI4/27_SELECT SRCC6_LPR PCI_F5/ITP_EN SRCT7_LPR CK_PWRGD/PD# SRCC7_LPR X1 CPUT2_ITP_LPR/SRCT8_LPR X2 CPUC2_ITP_LPR/SRCC8_LPR NC SRCT9_LPR USB_48MHz/FSLA SRCT10_LPR FSLB/TEST_MODE SRCC10_LPR FSLC/TEST_SEL/REF0 REF1 SRCT11_LPR SRCC11_LPR D 2 1 2 R1605 0_0402_5% 1 R1610 10K_0402_5% CLKSEL2 1 2 4 CLKSEL0 +3VS +1.05VS 4 5 8 R1600 @ 1K_0402_5% 1 1 2 R1604 @ 0_0402_5% VDDSRC_IO SRCC9_LPR +1.05VS R1601 1K_0402_5% 1 2 SRCC0_LPR/DOTC_96_LPR MCH_CLKSEL0 <8> <27> CLK_ICH_14M CLKSEL1 VDDSRC_IO 1 2 G Q106 @ 2N7002_SOT23 10P_0402_50V8J CLK_PCI_LPC 2 SRCT0_LPR/DOTT_96_LPR SRCC3_LPR <36> CLK_PCI_LPC C1898 1 VDDSRC_IO D CLK_PCI4=0, Pin28, 29 is SRC_CLK Pin24, 25 is DOT96_CLK 2 10K_0402_5% <27> H_STP_CPU# CK505_PWRGD 34 59 D_CK_SCLK 42 73 Q108 2N7002_SOT23 D_CK_SDATA 10 D_CK_SCLK 71 CLK_CPU_BCLK 70 CLK_CPU_BCLK# 68 CLK_MCH_BCLK 67 CLK_MCH_BCLK# 24 CLK_DREF_96M 25 CLK_DREF_96M# 28 CLK_DREF_SSC_1 29 CLK_DREF_SSC#_1 32 CLK_PCIE_SATA 33 CLK_PCIE_SATA# 35 CLK_PCIE_ICH 36 CLK_PCIE_ICH# 39 CLK_PCIE_CARD 40 CLK_PCIE_CARD# 57 CLK_MCH_3GPLL 56 CLK_MCH_3GPLL# 61 CLK_PCIE_VGA 60 CLK_PCIE_VGA# 64 CLK_PCIE_READER 63 CLK_PCIE_READER# 44 CLK_PCIE_MINI2 45 CLK_PCIE_MINI2# 50 CLK_PCIE_MINI1 51 CLK_PCIE_MINI1# 48 CLK_PCIE_LAN 47 CLK_PCIE_LAN# GNDREF CR#3 GNDPCI CR#4 GND48 CR#6 GND CR7# GND CR#9 GNDSRC CR10# GNDSRC CR#11 GNDSRC GND_THERMAL_PAD CR#A 37 41 58 65 43 49 C CLK_SMBCLK CLK_CPU_BCLK <4> CLK_CPU_BCLK# <4> CLK_MCH_BCLK <7> CLK_MCH_BCLK# <7> CLK_DREF_96M <8> CLK_DREF_96M# <8> VGA: disable this pair by BIOS VGA: disable this pair by BIOS CLK_PCIE_SATA <26> 2 CLK_PCIE_SATA# <26> CLK_PCIE_ICH <27> CLK_PCIE_ICH# <27> CLK_PCIE_CARD <35> CLK_PCIE_CARD# <35> CLK_MCH_3GPLL <8> CLK_MCH_3GPLL# <8> CLK_PCIE_VGA <17> CLK_PCIE_VGA# <17> UMA: disable this pair by BIOS CLK_PCIE_READER <31> CLK_PCIE_READER# CLK_PCIE_MINI2 CLK_PCIE_MINI2# CLK_PCIE_MINI1 CLK_PCIE_LAN# 3 <34> <34> CLK_PCIE_MINI1# CLK_PCIE_LAN <31> <34> <34> <32> <32> 1 R1603 2 10K_0402_5% +3VS 1 R1606 1 R1607 2 10K_0402_5% 2 10K_0402_5% EXP_CLKREQ# <35> MCH_CLKREQ# <8> (Pull High to +3VS at GMCH side) +3VS +3VS MINI2_CLKREQ# <34> MINI1_CLKREQ# <34> 46 21 (Pull High to +3VS at ICH side) 4 SATA_CLKREQ# <27> D Compal Electronics, Inc. Compal Secret Data 2008/11/24 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B CLK_SMBDATA ICS9LPRS387BKLFT_MLF72_10x10 Issued Date CPU_BSEL2 <5> 9 GNDCPU Security Classification MCH_CLKSEL2 <8> Clock Generator 1 SDATA SCLK VDD48 2 R1583 @ 10K_0402_5% CLK_PCI5=0, Pin63,64 is SRC_CLK CLK_PCI5=1, Pin63,64 is ITP_CLK @ 1 R1588 66 +3VS CLK_PCI5 2 10K_0402_5% 1 R1586 2 31 mount to Enable ITP_CLK 2 10K_0402_5% H L57 2 1 KC FBM-L11-201209-221LMAT_0805 1 1 1 1 1 1 1 1 C1891 C1892 C1893 C1894 C1895 C1896 C1897 C1890 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z 2 2 2 2 2 2 2 2 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +3VS CLK_PCI4 PM@ 2 1 R1829 10K_0402_5% CLK_PCI2 1 2 R1584 10K_0402_5% www.bufanxiu.com G U43 CLK_DREF_SSC <8> CLK_DREF_SSC_1 R1756 0_0402_5% PM@ 1 2 SRC7(VGA_CLK): Discrete VGA[Enable] UMA[Disable] C1887 +CLK_VDD R1755 0_0402_5% 2 GM@ 1 CLK_DREF_SSC Free-Run CR#_10(WLAN) C1885 +3VS 0.1U_0402_16V4Z PCI MHz 0.1U_0402_16V4Z SRC MHz F +CLK_VDD 0.1U_0402_16V4Z CPU MHz E 0.1U_0402_16V4Z FSLA D +CLK_VDDSRC 0.1U_0402_16V4Z FSLB CLKSEL2 CLKSEL1 CLKSEL0 C 10U_0805_10V4Z FSLC B 0.1U_0402_16V4Z A E F Title Clock Generator (CK505) Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 G Sheet 16 H of Rev 1.0 53 A B C www.bufanxiu.com D LVDS & DAC Interface E PEG Interface U17F NB9M-GS_BGA_533P COMMON PEX_TX0 PEX_TX0 AE12 AF12 PEX_RX0 PEX_RX0 PM@ C270 PM@ C271 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP1 PEX_TXN1 AD12 AC12 PEX_TX1 PEX_TX1 AG12 AG13 PEX_RX1 PEX_RX1 AB11 AB12 PEX_TX2 PEX_TX2 AF13 AE13 PEX_RX2 PEX_RX2 <10> PCIE_MTX_C_GRX_P1 <10> PCIE_MTX_C_GRX_N1 <10> PCIE_GTX_C_MRX_P2 <10> PCIE_GTX_C_MRX_N2 PM@ C281 PM@ C282 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP2 PEX_TXN2 <10> PCIE_MTX_C_GRX_P2 <10> PCIE_MTX_C_GRX_N2 <10> PCIE_GTX_C_MRX_P3 <10> PCIE_GTX_C_MRX_N3 PM@ C283 PM@ C284 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP3 PEX_TXN3 AD13 AD14 PEX_TX3 PEX_TX3 AE15 AF15 PEX_RX3 PEX_RX3 PM@ C291 PM@ C292 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP4 PEX_TXN4 AD15 AC15 PEX_TX4 PEX_TX4 AG15 AG16 PEX_RX4 PEX_RX4 PM@ C293 PM@ C294 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP5 PEX_TXN5 AB14 AB15 PEX_TX5 PEX_TX5 AF16 AE16 PEX_RX5 PEX_RX5 <10> PCIE_MTX_C_GRX_P3 <10> PCIE_MTX_C_GRX_N3 <10> PCIE_GTX_C_MRX_P4 <10> PCIE_GTX_C_MRX_N4 <10> PCIE_MTX_C_GRX_P4 <10> PCIE_MTX_C_GRX_N4 <10> PCIE_GTX_C_MRX_P5 <10> PCIE_GTX_C_MRX_N5 U17D <10> PCIE_MTX_C_GRX_P5 <10> PCIE_MTX_C_GRX_N5 NB9M-GS_BGA_533P COMMON 1 R206 PM@ <10> PCIE_GTX_C_MRX_P6 <10> PCIE_GTX_C_MRX_N6 5/13 DACC DACC_VDD 2 W5 10K_0402_5% R6 DACC_VREF V6 DACC_RSET PM@ C301 PM@ C302 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP6 PEX_TXN6 AC16 AD16 PEX_TX6 PEX_TX6 AE18 AF18 PEX_RX6 PEX_RX6 PM@ C303 PM@ C304 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP7 PEX_TXN7 AD17 AD18 PEX_TX7 PEX_TX7 AG18 AG19 PEX_RX7 PEX_RX7 AC18 AB18 PEX_TX8 PEX_TX8 AF19 AE19 PEX_RX8 PEX_RX8 AB19 AB20 PEX_TX9 PEX_TX9 AE21 AF21 PEX_RX9 PEX_RX9 AD19 AD20 PEX_TX10 PEX_TX10 AG21 AG22 PEX_RX10 PEX_RX10 AD21 AC21 PEX_TX11 PEX_TX11 AF22 AE22 PEX_RX11 PEX_RX11 AB21 AB22 PEX_TX12 PEX_TX12 AE24 AF24 PEX_RX12 PEX_RX12 AC22 AD22 PEX_TX13 PEX_TX13 AG24 AF25 PEX_RX13 PEX_RX13 AD23 AD24 PEX_TX14 PEX_TX14 <10> PCIE_MTX_C_GRX_P6 <10> PCIE_MTX_C_GRX_N6 DAC C DACC_HSYNC DACC_VSYNC U6 U4 DACC_RED T5 DACC_GREEN T4 DACC_BLUE R4 <10> PCIE_GTX_C_MRX_P7 <10> PCIE_GTX_C_MRX_N7 <10> PCIE_MTX_C_GRX_P7 <10> PCIE_MTX_C_GRX_N7 <10> PCIE_GTX_C_MRX_P8 <10> PCIE_GTX_C_MRX_N8 PM@ C305 PM@ C306 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP8 PEX_TXN8 <10> PCIE_MTX_C_GRX_P8 <10> PCIE_MTX_C_GRX_N8 <10> PCIE_GTX_C_MRX_P9 <10> PCIE_GTX_C_MRX_N9 PM@ 3 PM@ C307 PM@ C308 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP9 PEX_TXN9 <10> PCIE_MTX_C_GRX_P9 <10> PCIE_MTX_C_GRX_N9 DACA_RSET R207 PM@ <10> PCIE_GTX_C_MRX_P11 <10> PCIE_GTX_C_MRX_N11 DAC A DACA_HSYNC DACA_VSYNC AD2 AD1 DACA_RED AE2 DACA_GREEN AE3 DACA_BLUE AD3 R210 PM@ 2 DACB_VDD 10K_0402_5% #SI Remove TV out D7 R195 PM@ R196 PM@ R197 PM@ 2 150_0402_1% 1 4 TV-OUT 150_0402_1% NB9M-GS_BGA_533P COMMON 150_0402_1% PM@ U17E VGA_CRT_HSYNC VGA_CRT_VSYNC 1 1 DACA_VREF 1 2 C321 PM@ AF1 AE1 <10> PCIE_GTX_C_MRX_P10 <10> PCIE_GTX_C_MRX_N10 4/13 DACB DACB_VDD G6 DACB_VREF F8 DACB_RSET PM@ C309 PM@ C310 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP10 PEX_TXN10 VGA_CRT_R <23> VGA_CRT_G <23> VGA_CRT_B <23> PM@ C315 PM@ C316 DACB_CSYNC D6 DACB_RED F7 DACB_GREEN E7 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP11 PEX_TXN11 <23> <10> PCIE_MTX_C_GRX_P11 <23> <10> PCIE_MTX_C_GRX_N11 <10> PCIE_GTX_C_MRX_P12 <10> PCIE_GTX_C_MRX_N12 PM@ C322 PM@ C323 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP12 PEX_TXN12 <10> PCIE_MTX_C_GRX_P12 <10> PCIE_MTX_C_GRX_N12 <10> PCIE_GTX_C_MRX_P13 <10> PCIE_GTX_C_MRX_N13 PM@ C324 PM@ C326 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP13 PEX_TXN13 PM@ C328 PM@ C329 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP14 PEX_TXN14 AG25 AG26 PEX_RX14 PEX_RX14 PM@ C330 PM@ C331 1 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z PEX_TXP15 AE25 PEX_TXN15 AE26 PEX_TX15 PEX_TX15 AF27 AE27 PEX_RX15 PEX_RX15 <10> PCIE_MTX_C_GRX_P13 <10> PCIE_MTX_C_GRX_N13 <10> PCIE_GTX_C_MRX_P14 <10> PCIE_GTX_C_MRX_N14 <10> PCIE_MTX_C_GRX_P14 <10> PCIE_MTX_C_GRX_N14 <10> PCIE_GTX_C_MRX_P15 <10> PCIE_GTX_C_MRX_N15 <10> PCIE_MTX_C_GRX_P15 <10> PCIE_MTX_C_GRX_N15 DAC B 1 1 <10> PCIE_MTX_C_GRX_P10 <10> PCIE_MTX_C_GRX_N10 2 2 C320 PM@ 1 124_0402_1% 2 C319 PM@ 1 0.1U_0402_16V4Z 2 C317 PM@ 1 470P_0402_50V7K DACA_VREF 1 CRT 1 L9 PM@ AG2 3/13 DACA DACA_VDD 2 DACA_VDD 1 4700P_0402_25V7K 2 1U_0402_6.3V6K +3VS NB9M-GS_BGA_533P COMMON 150 mA 2 U17C BLM18PG181SN1D_0603 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD J10 J12 J13 J9 L9 M11 M17 M9 N11 N12 N13 N14 N15 N16 N17 N19 N9 P11 P12 P13 P14 P15 P16 P17 R11 R12 R13 R14 R15 R16 R17 R9 T11 T17 T9 U19 U9 W10 W12 W13 W18 W19 W9 VDD_SENSE GND_SENSE W15 W16 VDD33 VDD33 VDD33 VDD33 VDD33 VDD33 A12 B12 C12 D12 E12 F12 PEX_PLLVDD AF9 2 1 0.47U_0402_6.3V6K 0.47U_0402_6.3V6K 4.7U_0603_6.3V6M 1U_0603_10V4Z 0.1U_0402_16V4Z C262 PM@ 1 1 1U_0603_10V4Z C263 PM@ 2 1 C245 PM@ 2 1 C255 PM@ 1 2 C264 PM@ 2 +VGA_CORE 1 C273 PM@ 2 C274 PM@ C286 PM@ 1 2 C275 PM@ C287 PM@ 1 2 C276 PM@ C288 PM@ 1 2 0.1U_0402_16V4Z AD10 AD11 1 2 C277 PM@ 1 2 C278 PM@ 2 22u X 3 1 PM@ C285 PM@ 2 1 C295 PM@ 2 R392 1 1 1 2 2 C296 PM@ 1 2 1 2 C297 PM@ 1 2 1 2 C298 PM@ 1 0.47u X 7 C289 PM@ 0.1u X 7 2 0.47U_0402_6.3V6K PEX_TXP0 PEX_TXN0 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 22U_0805_6.3V6M 1 PM@ 1 1 <10> PCIE_MTX_C_GRX_P0 <10> PCIE_MTX_C_GRX_N0 <10> PCIE_GTX_C_MRX_P1 <10> PCIE_GTX_C_MRX_N1 PEX_REFCLK PEX_REFCLK PM@ C265 PM@ C268 0.47U_0402_6.3V6K C280 PM@ VGA_TXCLK- <22> VGA_TXCLK+ <22> PEX_RST 1 0.1U_0402_16V4Z AB2 AB3 AD9 AB10 AC10 C254 PM@ 2 C259 PM@ 22U_0805_6.3V6M AD4 AC4 IFPB_TXC IFPB_TXC PEX_RST# PEX_REFCLKP PEX_REFCLKN 1 1.920 Amps 2 0.47U_0402_6.3V6K 2 2 2 4700P_0402_25V7K 1 C279 PM@ 470P_0402_50V7K B <16> CLK_PCIE_VGA <16> CLK_PCIE_VGA# <10> PCIE_GTX_C_MRX_P0 <10> PCIE_GTX_C_MRX_N0 2 2 C249 PM@ 10U_0805_6.3V6M IFPA_TXC IFPA_TXC CLOCK 1 PLT_RST# AA1 AB1 IFPB_TXD7 IFPB_TXD7 A <8,25,27,31,32,36> 2 1 0.1U_0402_16V4Z AA3 AA2 C258 PM@ 22U_0805_6.3V6M IFPB_TXD6 IFPB_TXD6 C253 PM@ 1 +1.1VS 1 0.47U_0402_6.3V6K IFPB_IOVDD 2 C252 PM@ 2 1 2 C299 PM@ 1 2 C300 PM@ 0_0402_5% 2 +NVVDD_SENSE 3 +3VS 110 mA VDD33 1 2 C1476 PM@ 1U_0603_10V4Z IFPA_IOVDD V2 1 1 2 C314 PM@ 1 2 C311 PM@ 120mA PEX_PLLDVDD PEX_TSTCLK_OUT PEX_TSTCLK_OUT RFU PEX_TERMP AF10 AE10 1 2 1 2 C327 PM@ @ R208 1 2 C325 PM@ 1 2 C446 PM@ 1U_0402_6.3V6K V3 IFPB_IOVDD R204 PM@ 0_0402_5% AB13 AB16 AB17 AB7 AB8 AB9 AC13 AC7 AD6 AE6 AF6 AG6 0.47U_0402_6.3V6K W2 W3 PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ RFU 4.7U_0603_6.3V6M IFPB_TXD5 IFPB_TXD5 B IFPA_IOVDD AE9 C244 PM@ 2 0.1U_0402_16V4Z V1 W1 0.1U_0402_16V4Z IFPB_TXD4 IFPB_TXD4 1 AC9 AD7 AD8 AE7 AF7 AG7 0.47U_0402_6.3V6K 1 AB5 AB4 PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD 0.47U_0402_6.3V6K C267 PM@ IFPA_TXD3 IFPA_TXD3 1/13 PCI_EXPRESS 0.1U_0402_16V4Z 2 <22> <22> 0.01U_0402_25V7K C266 PM@ 470P_0402_50V7K 2 2 4700P_0402_25V7K C251 PM@ 1 4.7U_0603_6.3V6M 1 VGA_TXOUT2VGA_TXOUT2+ 600 mA 0.1U_0402_16V4Z 100 mA 1 Y4 W4 +1.1VS U17A NB9M-GS_BGA_533P COMMON 0.1U_0402_16V4Z +VDD_MEM18 2 IFPA_TXD2 IFPA_TXD2 DATA #SI Change to +VDDMEM18 L8 PM@ BLM18PG181SN1D_0603 <22> <22> A 1 R205 @ <22> <22> VGA_TXOUT1VGA_TXOUT1+ 1U_0603_10V4Z IFPAB_PLLVDD IFPAB_RSET VGA_TXOUT0VGA_TXOUT0+ AA4 AA5 0.1U_0402_16V4Z 1 AD5 AB6 V4 V5 IFPA_TXD1 IFPA_TXD1 0.1U_0402_16V4Z 2 C248 PM@ 2 2 C247 PM@ 2 1K_0402_1% C246 PM@ 1 470P_0402_50V7K 2 1 4700P_0402_25V7K C257 PM@ IFPAB_PLLVDD IFPAB_RSET 1 L7 PM@ 4.7U_0603_6.3V6M 1 4.7U_0603_6.3V6M 2 1 IFPA_TXD0 IFPA_TXD0 0.47U_0402_6.3V6K +VDD_MEM18 100mA BLM18PG181SN1D_0603 4.7U_0603_6.3V6M 6/13 IFPAB 0.1U_0402_16V4Z #SI Change to +VDDMEM18 1 2 1 +1.1VS L10 PM@ BLM18PG181SN1D_0603 C447 PM@ 200_0402_1% 2 AG9 AG10 1 2 R209 PM@ 2.49K_0402_1% PM@ 4 DACB_BLUE E6 #SI Remove TV out Compal Secret Data Security Classification Issued Date PM@ 2008/11/24 Deciphered Date 2009/12/31 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Compal Electronics, Inc. PEG & LVDS & DAC Size Document Number Custom KALH0/KALG0/KAL90+ Date: Monday, April 27, 2009 E Sheet 17 of Rev 1.0 53 4 3 2 #PV2 change R213,R215 form 10K to 2.2K. RFU F6 1 2 VCC WP SCL SDA 8 7 6 5 C1474 1 C1475 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z VGA_HDMI_TXCVGA_HDMI_TXC+ TXD2 TXD2 IFPC_L2 IFPC_L2 K4 HDMI_C_TX0L4 HDMI_C_TX0+ PM@ PM@ C1468 1 C1469 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z VGA_HDMI_TXD0VGA_HDMI_TXD0+ <24> <24> TXD2 TXD2 TXD1 TXD1 IFPC_L1 IFPC_L1 M4 HDMI_C_TX1M5 HDMI_C_TX1+ PM@ PM@ C1470 1 C1471 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z VGA_HDMI_TXD1VGA_HDMI_TXD1+ <24> <24> TXC TXC TXC TXC IFPC_L0 IFPC_L0 N4 HDMI_C_TX2P4 HDMI_C_TX2+ PM@ PM@ C1472 1 C1473 1 2 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z VGA_HDMI_TXD2VGA_HDMI_TXD2+ <24> <24> 1K_0402_1% 2 1 470P_0402_50V7K PM@ PM@ TXD1 TXD1 G5 G4 Must near connector for eye pattern <24> <24> D PM@ 1 2 @ R222 +3VS 1 @ 2 VGA_THERMDC 3 THERM#_VGA 2200P_0402_50V7K 10K_0402_5% R224 @ VGA_THERMDA 4 U6 VDD D+ DTHERM# SCLK SDATA ALERT# GND 8 1 2 VGA_SM_CLK 7 VGA_SM_DA 6 THERM_SCI# E H6 IFPE_IOVDD THERM_SCI# 5 ADM1032ARMZ REEL_MSOP8 @ 2 10K_0402_5% DVI DP IFPE_PLLVDD IFPE_RSET IFPE_AUX IFPE_AUX D4 D3 B4 B3 TXD0 TXD0 TXD0 TXD0 IFPE_L3 IFPE_L3 TXD1 TXD1 TXD2 TXD2 IFPE_L2 IFPE_L2 C4 C3 TXD2 TXD2 TXD1 TXD1 IFPE_L1 IFPE_L1 D5 E4 TXC TXC TXC TXC IFPE_L0 IFPE_L0 F4 F5 1 C350 N6 M6 R219 PM@ 10K_0402_5% 1 HDCP_SCL 2 AT24C16BN PM@ PM@ R212 Closed to VGA 1 10K_0402_5% R223 @ U17G 2 1 HDCP_WP IFPC_IOVDD 2 C348 @ 0.1U_0402_16V4Z 10K_0402_5% R221 PM@ HDCP_WP HDCP_SCL HDCP_SDA J4 HDMI_C_CLKH4 HDMI_C_CLK+ MXM 2 A0 A1 A2 GND 2 PM@ R236 1 2 3 4 1 PM@ R234 2 U7 IFPC_L3 IFPC_L3 8/13 IFPE VGA Thermal Sensor ADM1032ARMZ #SI2 change to pull hi 1 C 2 C351 PM@ 1 0.1U_0402_16V4Z HDCP ROM +3VS 2 TXD0 TXD0 NB9M-GS_BGA_533P COMMON 10K_0402_5% R218 PM@ +3VS +3VS 1 1 AC6 PM@ 1 2 R220 PM@ 2 J6 1 RFU_GND SPDIF_IN IFPC_IOVDD 1 1 TXD0 TXD0 AD25 2 2 RFU RFU 2 @ 2 1 TESTMODE C15 D15 1 C349 0.01U_0402_25V7K 10K_0402_5% R217 @ PM@ C341 PM@ C340 1 J5 L13 PM@ C C347 +3VS N5 RFU 36K_0402_5% SPDIF <39> SPDIF_HDMI SPDIF 1 R215 PM@ DP IFPC_AUX IFPC_AUX PM@ BUFRST F9 +3VS 2 2.2K_0402_5% DVI 1K_0402_5% STRAP_REF_MIOB MXM IFPC_PLLVDD IFPC_RSET 1K_0402_5% F10 P6 R5 385 mA BLM18PG181SN1D_0603 470P_0402_50V7K 2 40.2K_0402_1% R216 PM@ +1.1VS C346 1 +3VS 2 PM@ STRAP_REF_3V3 2 4700P_0402_25V7K F11 R213 2.2K_0402_5% PM@ 1 2 HDCP_SCL HDCP_SDA 2 C343 2 A3 A4 2 C342 1 A10 ROM_SI C10 ROM_SO C9 ROM_SCLK 1 PM@ I2CH_SCL I2CH_SDA B10 ROM_CS# 1 4.7U_0603_6.3V6M ROM_SI ROM_SO ROM_SCLK 1 PM@ C338 STRAP0 STRAP1 STRAP2 1 IFPC_PLLVDD IFPC_RSET 1 PM@ R214 PM@ 40.2K_0402_1% D ROM_CS C7 B9 A9 PM@ STRAP0 STRAP1 STRAP2 C337 11/13 MISC 7/13 IFPC 160 mA BLM18PG181SN1D_0603 L12 PM@ 1U_0402_6.3V6K 2 2 4700P_0402_25V7K +VDD_MEM18 R211 @ 10K_0402_5% NB9M-GS_BGA_533P COMMON 1 NB9M-GS_BGA_533P COMMON 4.7U_0603_6.3V6M 1 U17L www.bufanxiu.com 2 U17H #SI Change to +VDDMEM18 +3VS 1U_0402_6.3V6K 5 C PM@ +3VS U17K NB9M-GS_BGA_533P COMMON 36 mA GPU_PLLVDD 1 2 C352 PM@ 2 C353 PM@ 2 1 2 C354 PM@ 1 2 C355 PM@ PLLVDD K6 VID_PLLVDD L6 SP_PLLVDD D11 <4,36,37> XTAL_SSIN XTAL_OUTBUFF E9 1 XTAL_IN XTAL_OUT C357 @ 18P_0402_50V8J B XTALIN 27M_CLK 1 <16> E10XTALOUT PM@ C356 18P_0402_50V8J 2 @ I/O ACTIVE 0_0402_5% 1 EC_SMB_DA2 GPIO0 IN N/A Primary DVI Hot-plug GPIO1 IN N/A 2nd DVI Hot-plug GPIO2 OUT H Panel Back-Light PWM R229 GPIO3 10K_0402_5% PM@ R239 <4,36,37> 1 EC_SMB_CK2 Straps MULTI LEVEL STRAPS STRAP0 STRAP1 STRAP2 ROM_SI ROM_SO ROM_SCLK R242 +3VS 0_0402_5% PM@ OUT H Panel Power Enable GPIO4 OUT H Panel Back-Light Enable GPIO5 OUT N/A NVVDD VID0 OUT N/A NVVDD VID1 GPIO7 OUT N/A FBVDD VID0 GPIO8 IN L Thermal Alert GPIO9 OUT L FAN PWM GPIO10 OUT N/A FBVref Select GPIO11 OUT N/A SLI SYNCO GPIO12 IN N/A AC Detect GPIO13 OUT L PS Control or HDMI_CEC GPIO14 OUT H PS Control @ 2 5.1K_0402_5% 1 1 PM@ R243 DDR2 Resistor Locating 16MX16 Hynix 16MX16 Samsung 32MX16 Hynix 32MX16 Samsung 64MX16 Samsung 64MX16 Hynix R248 20 Kohms 10 Kohms 45 Kohms 30 Kohms 10 Kohms 5.1 Kohms Value R246 R248 R250 R252 1 PM@ 2 10K_0402_1% @ 2 5.1K_0402_5% 1 1 PM512M@2 R245 R247 5.1K_0402_5% R249 @ 2 5.1K_0402_5% R251 1 1 PM@ 2 15K_0402_5% R253 DDC2_CLK DDC2_DATA 2K_0402_5% 1 PM@ 2K_0402_5% 1 PM@ 2 R231 2 R232 U17M VGA_THERMDC VGA_THERMDA @ @ @ @ @ T6 T7 T8 T9 T10 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST PAD PAD PAD PAD PAD 1 R240 D8 THERMDN D9 THERMDP AF3 AF4 AG4 AE4 AG3 JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST 2 10K_0402_5% PM@ 0_0402_5% DDC2_CLK 2 DDC2_DATA 2 0_0402_5% @ @ R225 VGA_SM_CLK VGA_SM_DA 1 1 T1 T2 R226 GPU_VID0 GPU_VID1 0 0 0.9 V 0 1 1.09 V 1 0 1.2V I2CA_SCL I2CA_SDA R1 VGA_DDC_CLK T3 VGA_DDC_DATA I2CB_SCL I2CB_SDA R2 R3 I2CB_SCL I2CB_SDA I2CC_SCL I2CC_SDA A2 B1 DDC2_CLK DDC2_DATA I2CD_SCL I2CD_SDA N2 N3 I2CE_SCL I2CE_SDA Y6 W6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 I2CS_SCL I2CS_SDA Core Voltage Level VGA_DDC_CLK VGA_DDC_DATA PAD PAD I2CC_SCL I2CC_SDA LVDS <22> <22> VGA_HDMI_SCLK VGA_HDMI_SDATA I2CE_SCL I2CE_SDA PAD PAD N1 G1 C1 M2 ENVDD M3 K3 K2 J2 C2 THERMAL ALERT M1 SINN_GPIO9 D2 D1 J3 J1 K1 F3 G3 G2 F1 F2 HDMI B <24,30> <24,30> T43 @ T44 @ HDMI_DET ENVDD ENBKL GPU_VID0 GPU_VID1 1 PM@ 1 PM@ CRT <23> <23> T36 @ T37 @ <24,30> <22> <10,36> <51> <51> 2 R396 2 R395 0_0402_5% THERM#_VGA 0_0402_5% THERM_SCI# PM@ U17I NB9M-GS_BGA_533P COMMON HD AUDIO 10/13 HDAUDIO 2 45.3K_0402_1% @ 2 5.1K_0402_5% 1 PM@ 2 24.9K_0402_5% 1 HDA_BCLK A7 HDA_SYNC HDA_SDI HDA_SDO HDA_RST B7 A6 B6 C6 HDA_BITCLK_VGA HDA_SDIN2_R R399 33_0402_5% 9/21 R329 near GPU @ 2 5.1K_0402_5% 1 9/21 R237, R238, R240, R241 near ICH PM@ 2 5.1K_0402_5% 1 PM@ Issued Date 1 R237 2 4 3 <26> 2008/11/24 Deciphered Date 2 A HDA_SYNC_VGA <26> HDA_SDIN3 <26> HDA_SDOUT_VGA <26> HDA_RST_VGA# <26> 2 @ 10K_0402_5% Compal Secret Data Security Classification @ 2 5.1K_0402_5% 1 1 PM@ 2009/12/31 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 2 R227 2 R230 9/13 I2C_GPIO_THERM_JTAG 2 GPIO6 2K_0402_5% 1 PM@ 2K_0402_5% 1 PM@ VGA_SM_CLK 2 NB9M-GS_BGA_533P COMMON A R244 VGA_SM_DA 2 PM@ USAGE 2 R235 10K_0402_5% @ 1 2 XTALIN D10 R228 10K_0402_5% PM@ GPIO 1 <16> 27M_SSC 2 2 C497 4.7U_0603_6.3V6M PM@ 1 K5 1 1 22U_0805_6.3V6M C1528 PM@ 1 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z L14 0.1U_0402_16V4Z PM@ 1U_0402_6.3V6K 2 R238 12/13 XTAL_PLL BLM18PG181SN1D_0603 +1.1VS VGA_DDC_CLK VGA_DDC_DATA Title Compal Electronics, Inc. Straps & HDMI Size Document Number Custom KALH0/KALG0/KAL90+ Date: Monday, April 27, 2009 1 Rev 1.0 Sheet 18 of 53 www.bufanxiu.com A VRAM Interface PJP1 1 +VDD_MEM18 2 +1.8VS PAD-OPEN 3x3m @ U17J NB9M-GS_BGA_533P COMMON 1 <20> DQMA[3..0] <21> DQMA[7..4] <20> QSA[3..0] <21> QSA[7..4] <20> QSA#[3..0] <21> QSA#[7..4] CMDA[30..0] PM@ C368 2 4.7U_0603_6.3V6M C365 PM@ C375 PM@ 1 2 13/13 GND_NC 0.1U_0402_16V4Z 1 1 2 0.022U_0402_16V7K PM@ C367 2 4.7U_0603_6.3V6M C364 PM@ C374 1 PM@ 2 0.1U_0402_16V4Z 1 2 1U_0402_6.3V6K PM@ C360 2 0.1U_0402_16V4Z C363 PM@ C373 1 PM@ 2 0.022U_0402_16V7K 1 2 1 <20,21> CMDA0 CMDA1 CMDA2 CMDA3 CMDA4 CMDA5 CMDA6 CMDA7 CMDA8 CMDA9 CMDA10 CMDA11 CMDA12 CMDA13 CMDA14 CMDA15 CMDA16 CMDA17 CMDA18 CMDA19 CMDA20 CMDA21 CMDA22 CMDA23 CMDA24 CMDA25 CMDA26 CMDA27 CMDA28 CMDA29 CMDA30 9/18 add R for nvidia R1131 10K_0402_5% CMDA12 1 R254 PM@ 2 R257 @ 1 PM@ 2 <20> <20> <21> <21> +VDD_MEM18 30_0402_1% 2 R256 2 2 30_0402_1% PM@ 2 R255 @ PM@ R1132 10K_0402_5% CMDA11 CLKA0 CLKA0# CLKA1 CLKA1# 1 1 1U_0402_6.3V6K PM@ C359 1 2 0.022U_0402_16V7K M22 C362 FBA_DEBUG PM@ 1 1 4700P_0402_25V7K B16 2 C372 FB_CAL_TERM_GND 1 2 PM@ 1 1 0.1U_0402_16V4Z A15 PM@ C366 B15 FB_CAL_PU_GND 2 0.022U_0402_16V7K FB_CAL_PD_VDDQ C369 FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 PM@ B24 D25 E18 A18 R22 R27 Y24 AA27 F24 F23 N24 N23 1 4700P_0402_25V7K QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1 2 2 C371 FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 1 1 2 PM@ A24 C25 E19 A19 T22 T27 AA24 AA26 2 1 4700P_0402_25V7K QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 F26 J24 F25 M23 N27 M27 K26 J25 J27 G23 G26 J23 M25 K27 G25 L24 K23 K24 G22 K25 H22 M26 H24 F27 J26 G24 G27 M24 K22 J22 L22 PM@ C358 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 RFU RFU 1 2 0.022U_0402_16V7K D23 C26 D19 B19 T24 T26 AA23 AB27 A13 B13 C13 D13 D14 E13 F13 F14 F15 F16 F17 F19 F22 H23 H26 J15 J16 J18 J19 L19 L23 L26 M19 N22 U22 Y22 C361 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ FBVDDQ 1 PM@ FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 4700P_0402_25V7K D21 C22 B22 A22 C24 B25 A25 A26 D22 E22 E24 D24 D26 D27 C27 B27 D16 E16 D17 F18 D20 F20 E21 F21 C16 B18 C18 D18 C19 C21 B21 A21 P22 P24 R23 R24 T23 U24 V23 V24 N25 N26 R25 R26 T25 V26 V25 V27 V22 W22 W23 W24 AA22 AB23 AB24 AC24 W25 W26 W27 AA25 AB25 AB26 AD26 AD27 C370 MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 PM@ MDA[63..48] NB9M-GS_BGA_533P COMMON +VDD_MEM18 2/13 FRAME_BUFFER 4700P_0402_25V7K MDA[47..32] 40.2_0402_1% AC11 AC14 AC17 AC2 AC20 AC23 AC26 AC5 AC8 AF11 AF14 AF17 AF2 AF20 AF23 AF26 AF5 AF8 B11 B14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND B17 B2 B20 B23 B26 B5 B8 E11 E14 E17 E2 E20 E23 E26 E5 E8 H2 H5 J11 J14 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND J17 K19 K9 L11 L12 L13 L14 L15 L16 L17 L2 L5 M12 M13 M14 M15 M16 P19 P2 P23 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND P26 P5 P9 T12 T13 T14 T15 T16 U11 U12 U13 U14 U15 U16 U17 U2 U23 U26 U5 V19 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND V9 W11 W14 W17 Y2 Y23 Y26 Y5 GND GND GND GND GND GND GND GND NC NC NC NC AA6 AC19 E15 T6 1 +VDD_MEM18 10K_0402_5% PM@ 1 2 R259 @ 1K_0402_1% FB_VREF Rb 2 C378 @ 2 2 1 2 1 2 1 2 1 L15 PM@ BLM18PG181SN1D_0603 +1.1VS C394 1 PM@ A16 1 FB_PLLAVDD C379 T19 PM@ R19 4.7U_0603_6.3V6M Rt PM@ C377 0.01U_0402_25V7K FB_PLLAVDD FB_DLLAVDD 1 @ 2 R258 1K_0402_1% C376 +VDD_MEM18 PM@ <21> MDA[63..48] MDA[31..16] 1U_0402_6.3V6K <21> MDA[47..32] U17B 0.1U_0402_16V4Z <20> MDA[31..16] #SI2 change to short pad MDA[15..0] 0.1U_0402_16V4Z <20> MDA[15..0] PM@ Compal Secret Data Security Classification Issued Date 2008/11/24 Deciphered Date 2009/12/31 T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A Title Compal Electronics, Inc. VRAM / GND Size Document Number Custom KALH0/KALG0/KAL90+ Date: Monday, April 27, 2009 Sheet Rev 1.0 19 of 53 5 4 3 www.bufanxiu.com 2 1 DATA Bus VRAM DDR2 chips (256MB & 512MB) Address 32Mx16 DDR2 400MHz *4==>256MB 64Mx16 DDR2 400MHz*4==>512MB 32..63 0..31 CMD0 A3 CMD1 A0 CMD2 A2 CMD3 A1 A0 A1 CMD4 D CMD5 A4 QSA#[7..0] CMD6 A5 DQMA[7..0] CMD7 <19,21> QSA#[7..0] <19,21> DQMA[7..0] A3 QSA[7..0] <19,21> QSA[7..0] MDA[63..0] CMD8 CS# CMDA[30..0] CMD9 WE# WE# CMD10 BA0 BA0 CMD11 CKE CKE CMD12 ODT ODT CMD14 A12 A12 CMD15 RAS# RAS# CMD16 A11 A11 <19,21> MDA[63..0] <19,21> CMDA[30..0] D CS# CMD13 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA22 CMDA24 CMDA0 CMDA2 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 CLKA0# CLKA0 K8 J8 CMDA11 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA2 DQMA0 +VDD_MEM18 CMDA12 K9 QSA2 QSA#2 F7 E8 QSA0 QSA#0 B7 A8 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CK CK VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CKE CS WE RAS VDD VDD VDD VDD VDD CAS LDM UDM VDDL VSSDL ODT R260 1K_0402_1% PM@ 500 (MIL) 1 2 MAX MEM_VREF0 J2 A2 E2 L1 R3 R7 R8 1 R262 1K_0402_1% PM@ CMDA27 2 C385 0.1U_0402_16V4Z 2 PM@ A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 LDQS LDQS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ UDQS UDQS VREF NC NC NC NC NC NC VSS VSS VSS VSS VSS U9 CMDA10 CMDA18 L2 L3 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA22 CMDA24 CMDA0 CMDA2 CMDA3 CMDA1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 CLKA0# CLKA0 +VDD_MEM18 A1 E1 J9 M9 R1 CMDA8 L8 CMDA9 K3 CMDA15 K7 1 1 2 0.1U_0402_16V4Z A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 2 C384 4.7U_0603_6.3V6M PM@ #PV reserve CMD27 to suport 64M x 16 MAX 500 (MIL) F3 B3 CMDA12 K9 QSA1 QSA#1 F7 E8 QSA3 QSA#3 B7 A8 MEM_VREF0 J2 A3 E3 J3 N1 P9 CK CK CS WE RAS VDD VDD VDD VDD VDD CAS LDM UDM VDDL VSSDL ODT MDA27 MDA28 MDA24 MDA31 MDA30 MDA25 MDA29 MDA26 MDA15 MDA9 MDA12 MDA8 MDA11 MDA13 MDA10 MDA14 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 +VDD_MEM18 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ UDQS UDQS VREF NC NC NC NC NC NC VSS VSS VSS VSS VSS CMD17 A10 A10 CMD18 BA1 BA1 CMD19 A8 A8 CMD20 A9 A9 CMD21 A6 A6 CMD22 A5 CMD23 A7 C A7 CMD24 A4 CMD25 CAS# CAS# CMD26 A13 A13 CMD27 BA2 BA2 CMD28 CMD29 CMD30 A1 E1 J9 M9 R1 J1 J7 1 1 C381 PM@ LDQS LDQS A2 E2 L1 R3 R7 R8 CMDA27 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CKE L7 DQMA1 DQMA3 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 K2 CMDA25 J1 J7 BA0 BA1 K8 J8 CMDA11 C383 PM@ 1 B F3 B3 BA0 BA1 MDA7 MDA0 MDA5 MDA2 MDA3 MDA4 MDA1 MDA6 MDA23 MDA18 MDA20 MDA16 MDA17 MDA21 MDA19 MDA22 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 2 0.1U_0402_16V4Z A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 C382 4.7U_0603_6.3V6M PM@ 2 B <19> CLKA0 CLKA0 1 L2 L3 R261 475_0402_1% PM@ A3 E3 J3 N1 P9 2 C U8 CMDA10 CMDA18 <19> CLKA0# CLKA0# (SSTL-1.8) VREF = .5*VDDQ HY5PS1G1631CFR-25 FBGA 84P HY5PS1G1631CFR-25 FBGA 84P PM512M@ PM512M@ DDR BGA MEMORY DDR2 BGA MEMORY 2 1 C393 PM@ 2 0.01U_0402_16V7K 2 1 C392 PM@ 0.01U_0402_16V7K 2 1 C391 PM@ 2008/11/24 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 A Compal Secret Data Security Classification Issued Date 2 1 C390 PM@ 0.1U_0402_16V4Z 2 1 C389 PM@ 4.7U_0603_6.3V6M 2 1 C388 PM@ 0.1U_0402_16V4Z 2 1 C387 PM@ 0.01U_0402_16V7K 2 1 C386 PM@ 0.01U_0402_16V7K 2 1 C402 PM@ 1000P_0402_50V7K 2 1 C401 PM@ 0.01U_0402_16V7K 2 1 C400 PM@ 0.1U_0402_16V4Z 2 1 C399 PM@ 0.1U_0402_16V4Z 2 1 C398 PM@ 4.7U_0603_6.3V6M 2 1 C397 PM@ 0.1U_0402_16V4Z 2 1 C396 PM@ 0.01U_0402_16V7K C395 PM@ +VDD_MEM18 0.01U_0402_16V7K 1 A 1000P_0402_50V7K +VDD_MEM18 2 Title Size Date: Compal Electronics, Inc. VRAM 1 Document Number Rev 0.1 KAL90 Monday, April 27, 2009 1 Sheet 7 of 16 5 4 3 www.bufanxiu.com 2 1 DATA Bus VRAM DDR2 chips (256MB & 512MB) 32Mx16 DDR2 400MHz *4==>256MB 64Mx16 DDR2 400MHz*4==>512MB D DQMA[7..0] <19,20> DQMA[7..0] CMDA[30..0] <19,20> CMDA[30..0] <19,20> QSA#[7..0] <19,20> QSA[7..0] <19,20> MDA[63..0] 32..63 0..31 Address CMD0 A3 CMD1 A0 CMD2 A2 CMD3 A1 A0 A1 CMD4 A3 CMD5 A4 CMD6 A5 QSA#[7..0] CMD7 QSA[7..0] CMD8 CS# CS# MDA[63..0] CMD9 WE# WE# CMD10 BA0 BA0 CMD11 CKE CKE CMD12 ODT ODT D CMD13 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA5 DQMA4 F3 B3 CMDA12 B QSA5 QSA#5 F7 E8 QSA4 QSA#4 B7 A8 CKE CS WE RAS 1 2 R266 1K_0402_1% PM@ 2 R268 1K_0402_1% PM@ MAX 500 (MIL) MEM_VREF1 1 2 CMDA27 C407 0.1U_0402_16V4Z PM@ J2 A2 E2 L1 R3 R7 R8 A1 E1 J9 M9 R1 VDD VDD VDD VDD VDD CAS LDM UDM J1 J7 VDDL VSSDL ODT 1 1 C405 PM@ LDQS LDQS A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 1 +VDD_MEM18 K9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ UDQS UDQS VREF NC NC NC NC NC NC CLKA1# CLKA1 +VDD_MEM18 2 0.1U_0402_16V4Z 2 C406 4.7U_0603_6.3V6M PM@ #PV reserve CMD27 to suport 64M x 16 MAX 500 (MIL) CMDA11 K2 CMDA8 L8 CMDA9 K3 CMDA15 K7 CMDA25 L7 DQMA6 DQMA7 F3 B3 CMDA12 K9 QSA6 QSA#6 F7 E8 QSA7 QSA#7 B7 A8 MEM_VREF1 A3 E3 J3 N1 P9 VSS VSS VSS VSS VSS K8 J8 J2 A2 E2 L1 R3 R7 R8 CMDA27 HY5PS1G1631CFR-25 FBGA 84P PM512M@ 2 1 C410 PM@ 2 0.01U_0402_16V7K 2 1 C409 PM@ 0.01U_0402_16V7K 2 1 C408 PM@ 1000P_0402_50V7K 2 1 C424 PM@ 0.01U_0402_16V7K 2 1 C423 PM@ 0.1U_0402_16V4Z 2 1 C422 PM@ 0.1U_0402_16V4Z 2 1 C421 PM@ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CKE CS WE RAS VDD VDD VDD VDD VDD CAS LDM UDM VDDL VSSDL ODT LDQS LDQS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ UDQS UDQS VREF NC NC NC NC NC NC VSS VSS VSS VSS VSS +VDD_MEM18 1 C411 PM@ A11 A10 CMD18 BA1 BA1 CMD19 A8 A8 CMD20 A9 A9 CMD21 A6 A6 CMD22 A5 CMD23 A7 CMD24 A4 C A7 CMD25 CAS# CAS# CMD26 A13 A13 CMD27 BA2 BA2 CMD28 CMD29 CMD30 A1 E1 J9 M9 R1 J1 J7 1 1 C403 PM@ 2 2 0.1U_0402_16V4Z A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 B C404 4.7U_0603_6.3V6M PM@ <19> CLKA1 CLKA1 R267 475_0402_1% PM@ A3 E3 J3 N1 P9 <19> Issued Date 2 1 C412 PM@ 2 1 C413 PM@ 2 1 C414 PM@ 2 1 C415 PM@ 2 CLKA1# CLKA1# 2008/11/24 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 3 A Compal Secret Data Security Classification 5 A11 A10 DDR BGA MEMORY +VDD_MEM18 4.7U_0603_6.3V6M 2 1 C420 PM@ 0.1U_0402_16V4Z 2 1 C419 PM@ 0.01U_0402_16V7K 2 1 C418 PM@ 0.01U_0402_16V7K C417 PM@ 1000P_0402_50V7K 1 A CK CK A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 CMD16 CMD17 HY5PS1G1631CFR-25 FBGA 84P PM512M@ DDR2 BGA MEMORY +VDD_MEM18 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 RAS# 1 CMDA11 CK CK A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 A12 RAS# 2 K8 J8 CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA6 CMDA5 CMDA4 CMDA13 CMDA3 CMDA1 BA0 BA1 A12 CMD15 0.01U_0402_16V7K CLKA1# CLKA1 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 L2 L3 0.01U_0402_16V7K R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 MDA59 MDA60 MDA58 MDA62 MDA63 MDA56 MDA61 MDA57 MDA51 MDA53 MDA48 MDA55 MDA52 MDA49 MDA54 MDA50 0.1U_0402_16V4Z CMDA14 CMDA16 CMDA17 CMDA20 CMDA19 CMDA23 CMDA21 CMDA6 CMDA5 CMDA4 CMDA13 CMDA3 CMDA1 BA0 BA1 U11 CMDA10 CMDA18 4.7U_0603_6.3V6M L2 L3 MDA39 MDA32 MDA38 MDA34 MDA33 MDA37 MDA35 MDA36 MDA44 MDA43 MDA47 MDA40 MDA41 MDA46 MDA42 MDA45 0.1U_0402_16V4Z C U10 CMDA10 CMDA18 CMD14 2 Title Size Date: Compal Electronics, Inc. VRAM 2 Document Number Rev 0.1 KAL90 Monday, April 27, 2009 1 Sheet 8 of 16 5 4 3 www.bufanxiu.com 2 1 +3VS 5 2 G @ INVTPWM 2 R1617 10K_0402_5% Q111 2N7002_SOT23 +LCDVDD 1 C1904 4.7U_0805_10V4Z 2 @ 3 1 S 3 1 D +3VS 2 For GMCH DPST C1905 0.1U_0402_16V4Z 2 R1620 100K_0402_5% DPST_PWM <10> 4.7U_0805_10V4Z W=60mils 1 2 C1902 Q110 AO3413_SOT23-3 1 C1903 2 2N7002DW-T/R7_SOT363-6 0.047U_0402_16V7K 1 1 2 0_0402_5% 2 A 3 1 2 6 2 1 R1619 1 PM@ ENVDD Q109A 2 0_0402_5% Y D G 1 3 2 2 1 R1616 1K_0402_5% 4 5 G <18> 2 D R1618 1 GM@ 1 S 2N7002DW-T/R7_SOT363-6 GM@ 4 NC7SZ14P5X_NL_SC70-5 R1615 100K_0402_5% Q109B <10> GMCH_ENVDD INVTPWM W=60mils R1614 300_0603_5% 1 U44 +3VS +3V NC LCD POWER CIRCUIT +LCDVDD P D C C TXOUT0+ TXOUT0- 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ I2CC_SCL I2CC_SDA 1 2 RP47 GMCH_LCD_CLK 4 GMCH_LCD_DATA 3 GM@ 0_0404_4P2R_5% TXOUT0+ TXOUT0- 2 1 RP48 2 1 RP49 2 1 RP50 2 1 RP51 3 4 GM@ 3 4 GM@ 3 4 GM@ 3 4 GM@ +3VS TXOUT2+ TXOUT2- 1 TXOUT1TXOUT1+ TXCLKTXCLK+ R1621 1 L58 2 1 KC FBM-L11-201209-221LMAT_0805 C1908 1 DAC_BRIG INVTPWM DISPOFF# C1910 1 C1906 1 C1907 1 C1909 2 2 2 220P_0402_50V7K 220P_0402_50V7K 220P_0402_50V7K LCD/PANEL BD. Conn. B JLVDS1 +INVPWR_B+ +3VS <18> I2CC_SCL <18> I2CC_SDA I2CC_SCL I2CC_SDA 1 R1767 @ 2 0_0402_5% LED PANEL PIN1&34 SHORT USB20_N3 USB20_P3 VGA_TXCLK- <17> VGA_TXCLK+ <17> B+ 680P_0402_50V7K 68P_0402_50V8J 2 2 <27> <27> VGA_TXOUT2+ <17> VGA_TXOUT2- <17> DISPOFF# L59 2 1 KC FBM-L11-201209-221LMAT_0805 1 VGA_TXOUT1- <17> VGA_TXOUT1+ <17> CH751H-40PT_SOD323-2 +INVPWR_B+ W=40mils 2 2 BKOFF# BKOFF# VGA_TXOUT0+ <17> VGA_TXOUT0- <17> 4.7K_0402_5% D34 <36> VGA_TXOUT0+ VGA_TXOUT00_0404_4P2R_5% VGA_TXOUT1VGA_TXOUT1+ 0_0404_4P2R_5% VGA_TXOUT2+ VGA_TXOUT20_0404_4P2R_5% VGA_TXCLKVGA_TXCLK+ 0_0404_4P2R_5% 1 2 RP43 1 2 RP44 1 2 RP45 1 2 RP46 R1623 0_0402_5% 1 2USB20_CMOS_N6 1 2USB20_CMOS_P6 R1624 0_0402_5% 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 B TXOUT1TXOUT1+ DAC_BRIG 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GMCH_LCD_CLK <10> GMCH_LCD_DATA <10> DAC_BRIG <36> INVTPWM R1622 1 DISPOFF# PM@ 2 0_0402_5% TXOUT2+ TXOUT2- INVT_PWM <36> TXCLKTXCLK+ +LCDVDD W=60mils TXOUT0TXOUT0+ +3VS TXOUT1TXOUT1+ 1 TXOUT2+ TXOUT2- 2 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% GMCH_TXOUT0+ GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT1+ GMCH_TXOUT2+ GMCH_TXOUT2GMCH_TXCLKGMCH_TXCLK+ GMCH_TXOUT0+ <10> GMCH_TXOUT0- <10> GMCH_TXOUT1- <10> GMCH_TXOUT1+ <10> GMCH_TXOUT2+ <10> GMCH_TXOUT2- <10> GMCH_TXCLK- <10> GMCH_TXCLK+ <10> +LCDVDD 1 C1911 0.1U_0402_16V4Z 2 1 C1912 10U_0805_10V4Z 2 C1913 0.1U_0402_16V4Z TXCLKTXCLK+ +3VS ACES_88242-4001 CONN@ A A 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Compal Electronics, Inc. Compal Secret Data Security Classification 2 Title LVDS Connector Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet Rev 1.0 22 of 53 A B C CRT Connector D35 D36 D37 +R_CRT_VCC 1 1 1 D38 2 1 1 W=40mils 2 1.1A_6VDC_FUSE 1 C1914 0.1U_0402_16V4Z 2 3 2 3 2 3 +CRT_VCC F1 RB491D_SC59-3 2 E W=40mils +5VS DAN217_SC59 DAN217_SC59 DAN217_SC59 1 www.bufanxiu.com D +3VS 1 JCRT1 150_0402_1% C1916 2 10P_0402_50V8J 1 2 C1917 1 C1918 2 10P_0402_50V8J 1 1 C1919 L65 C1920 1 2 FCM2012C-800_0805 CRT_G_2 1 2 FCM2012C-800_0805 CRT_B_2 1 2 2 2 22P_0402_50V8J 22P_0402_50V8J 22P_0402_50V8J 10P_0402_50V8J +CRT_VCC P 2 A 1 2 1 2 C1923 10P_0402_50V8J GM@ 1 L4 2 10_0603_5% C1924 1 L5 2 10_0603_5% CRT_HSYNC_2 CRT_VSYNC_2 1 1 C1925 10P_0402_50V8J 2 1 10K_0402_5% 2 Y 3 CONN@ R1630 100K_0402_5% 1 C1928 2 68P_0402_50V8J DSUB_15 2 1 2 74AHCT1G125GW_SOT353-5 GND GND SUYIN_070546FR015S263ZR CRT_DET# <27> DSUB_12 10P_0402_50V8J CRT_HSYNC_1 4 2 100P_0402_50V8J C1926 U45 RGND ID0 Red GGND SDA Green BGND Hsync Blue +5V Vsync res SGND SCL GND 16 17 1 G CRT_HSYNC 1 2 R1631 5 2 0.1U_0402_16V4Z OE# 1 C1927 2 change to 12pf for Discrete change to 15pf for Discrete 2 1 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 2 2 2 150_0402_1% 1 C1915 L63 CRT_B_1 2 FCM2012C-800_0805 CRT_R_2 1 R1627 150_0402_1% CRT_G_1 2 FCM2012C-800_0805 1 2 FCM2012C-800_0805 10P_0402_50V8J 1 R1626 1 1 C1922 L64 1 1 2 R1625 L61 GM@ L62 CRT_B CRT_R_1 2 FCM2012C-800_0805 C1921 CRT_G 1 10P_0402_50V8J L60 GM@ CRT_R C1929 +CRT_VCC 68P_0402_50V8J 5 A U46 Y 4 CRT_VSYNC_1 3 G 2 P CRT_VSYNC OE# 2 0.1U_0402_16V4Z 1 +CRT_VCC 1 C1930 74AHCT1G125GW_SOT353-5 +CRT_VCC pull-up 2.2k on GPU side 1 PM@ 2 R1634 0_0402_5% VGA_DDC_DATA <18> 2 2 R1633 4.7K_0402_5% 2 R1632 4.7K_0402_5% 3 G 3 pull-up 10k on AMD M82M MXM side +3VS 1 1 Place closed to chipset R1637 1 GM@ 2 30.1_0402_1% CRT_HSYNC <10> GMCH_CRT_B R1638 1 GM@ 2 0_0402_5% CRT_B <10> GMCH_CRT_G R1640 1 GM@ 2 0_0402_5% CRT_G <10> GMCH_CRT_R R1641 1 GM@ 2 0_0402_5% CRT_R 1 2 GM@ R1636 3 Q112 2N7002_SOT23 DSUB_15 1 0_0402_5% GMCH_CRT_DATA <10> 2 <10> GMCH_CRT_HSYNC DSUB_12 G CRT_VSYNC 1 3 S 30.1_0402_1% S 2 D R1635 1 GM@ D <10> GMCH_CRT_VSYNC Q113 2N7002_SOT23 2 GM@ 1 R1639 0_0402_5% 1 PM@ R1642 2 GMCH_CRT_CLK <10> VGA_DDC_CLK <18> 0_0402_5% pull-up 2.2k on GPU side <17> VGA_CRT_VSYNC R1643 1 PM@ 2 0_0402_5% CRT_VSYNC <17> VGA_CRT_HSYNC R1644 1 PM@ 2 0_0402_5% CRT_HSYNC <17> VGA_CRT_B R1645 1 PM@ 2 0_0402_5% CRT_B <17> VGA_CRT_G R1646 1 PM@ 2 0_0402_5% CRT_G <17> VGA_CRT_R R1647 1 PM@ 2 0_0402_5% CRT_R pull-up 10k on AMD M82M MXM side 4 4 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification D Title Size B Date: CRT Connector Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 23 of 53 5 4 3 www.bufanxiu.com 2 1 DIP +HDMI_5V_OUT DDC to HDMI CONN +3VS HDMI_HPD VGA_HDMI_SDATA VGA_HDMI_SDATA 3 1 2 2 2.2K_0402_5% 2 2.2K_0402_5% HDMI_R_CKHDMI_R_CK+ HDMI_R_D0HDMI_R_D0+ HDMI_R_D1- D R1652 1 R1653 1 @ HDMI_SCLK HDMI_SDATA 1 S +3VS +5VS HDMI_SDATA HDMI_SCLK Q114 BSH111_SOT23 G <18,30> VGA_HDMI_SDATA R1650 4.7K_0402_5% D 3 2 VGA_HDMI_SCLK 2 VGA_HDMI_SCLK S <18,30> VGA_HDMI_SCLK 2 2.2K_0402_5% 2 2.2K_0402_5% 2 R1648 1 R1651 1 @ G +3VS +5VS D R1649 4.7K_0402_5% 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 +HDMI_5V_OUT 1 1 3.3V Level Q115 BSH111_SOT23 HDMI_R_D1+ HDMI_R_D2- Place closed to JHDMI1 HDMI_R_D2+ JHDMI1 HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKGND CK_shield GND CK+ GND D0GND D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+ D 20 21 22 23 TYCO_1939864-1 CONN@ MP:Update HDMI Hot Plug DET circuit. +HDMI_5V_OUT HDMI_HPD 1 @ 2 R104 0_0603_5% 3 C 1 2 +HDMI_5V_OUT 0.1U_0402_16V4Z HDMI_DET <18,30> C1932 4 Y HDMI_DET +3VS G A U47 2 1 R1654 2.2K_0402_5% R1655 1 2 100K_0402_5% 2 2 R65 0_0402_5% @ 1 1 5 P 0.1U_0402_16V4Z 2 OE# C1931 1 2 +5VS D39 1 +HDMI_5V RB491D_SC59-3 1 F2 W=40mils HDMI_CLK- 2 1.1A_6VDC_FUSE C1933 0.1U_0402_16V4Z 74AHCT1G125GW_SOT353-5 1 R1656 1 L66 1 2 4 @ HDMI--PM TO GM U68 Y 4 GM@ 74AHCT1G125GW_SOT353-5 B R1692 2 1 1.2K_0402_5% GM@ <18> VGA_HDMI_TXD1+ <18> VGA_HDMI_TXD1- HDMI_DET# <30> <18> VGA_HDMI_TXD2+ <18> VGA_HDMI_TXD2- 2.2K_0402_5% 2 1 GM@ R1681 OE# 1 R1680 5 P <18> VGA_HDMI_TXD0+ <18> VGA_HDMI_TXD0- G A 3 2.2K_0402_5% GM@ 2 1 2 1 2 RP55 1 2 RP52 1 2 RP54 1 2 RP53 <18> VGA_HDMI_TXC+ <18> VGA_HDMI_TXC- 4 3 PM@ 4 3 PM@ 4 3 PM@ 4 3 PM@ 1 2 RP59 1 2 RP56 1 2 RP58 1 2 RP57 <30> UMA_DVI_TXC+ <30> UMA_DVI_TXC<30> UMA_DVI_TXD0+ <30> UMA_DVI_TXD0<30> UMA_DVI_TXD1+ <30> UMA_DVI_TXD1<30> UMA_DVI_TXD2+ <30> UMA_DVI_TXD2- 4 3 GM@ 4 3 GM@ 4 3 GM@ 4 3 GM@ 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% 0_0404_4P2R_5% HDMI_CLK+ HDMI_CLK- 1 R1658 2 0_0402_5% HDMI_R_D0- 1 4 @ HDMI_TX2+ HDMI_TX2- 4 1 2 4 3 2 3 WCM-2012-900T_0805 1 R1659 2 0_0402_5% HDMI_R_D0+ HDMI_TX1- 1 R1660 2 0_0402_5% HDMI_R_D1B L68 1 HDMI_TX1+ HDMI_TX1- 4 @ HDMI_TX2+ HDMI_TX2- 1 2 4 3 2 3 WCM-2012-900T_0805 HDMI_TX1+ 1 R1661 2 0_0402_5% HDMI_R_D1+ HDMI_TX2- 1 R1662 2 0_0402_5% HDMI_R_D2- @ HDMI_TX2+ L69 1 2 4 3 2 3 WCM-2012-900T_0805 1 R1663 HDMI_R_D2+ 2 0_0402_5% A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 L67 HDMI_TX0+ HDMI_TX0+ HDMI_TX0- 499_0402_1% PM@ R967 2 1 499_0402_1% PM@ R966 2 1 499_0402_1% PM@ R965 2 1 499_0402_1% PM@ R964 2 1 499_0402_1% PM@ R963 2 1 499_0402_1% PM@ R962 2 1 499_0402_1% PM@ R961 2 1 499_0402_1% PM@ R960 2 1 1 3 S Q74 2N7002_SOT23 2 +3VS G PM@ 3 HDMI_TX0- 4 D 3 WCM-2012-900T_0805 HDMI_R_CK+ 1 #SI2 add 2N7002 to GND 4 2 2 0_0402_5% HDMI_TX1+ HDMI_TX1- HDMI_CLKHDMI_CLK+ HDMI_TX0HDMI_TX0+ HDMI_TX1HDMI_TX1+ HDMI_TX2HDMI_TX2+ A 2 1 R1657 HDMI_TX0+ HDMI_TX0- HDMI_CLK+ HDMI_CLK- C 1 HDMI_CLK+ +HDMI_5V_OUT HDMI_HPD HDMI_R_CK- 2 0_0402_5% 3 2 Title Compal Electronics, Inc. HDMI Connector Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 24 of 53 5 4 3 www.bufanxiu.com 2 1 DMI for ESI-compatible operation +3VS PCI_GNT#1 PCI_DEVSEL# PCI_FRAME# PCI_REQ#1 PCI_REQ#2 D 8.2K_1206_8P4R_5% 1 2 3 4 RP37 D11 C8 D9 E12 E9 C9 E10 B7 C7 C5 G11 F8 F11 E7 A3 D2 F10 D5 D10 B3 F7 C3 F3 F4 C1 G7 H7 D1 G5 H6 G1 H3 PCI_PLOCK# PCI_IRDY# PCI_PERR# PCI_PIRQB# 8 7 6 5 8.2K_1206_8P4R_5% +3VS 1 2 3 4 RP38 PCI_PIRQG# PCI_REQ#0 PCI_PIRQH# PCI_PIRQE# 8 7 6 5 8.2K_1206_8P4R_5% C 1 2 3 4 RP39 PCI_PIRQF# PCI_SERR# PCI_PIRQA# PCI_PIRQC# 8 7 6 5 8.2K_1206_8P4R_5% 1 2 3 4 RP40 PCI_STOP# PCI_PIRQD# PCI_REQ#3 PCI_TRDY# 8 7 6 5 PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# 8.2K_1206_8P4R_5% J5 E1 J6 C4 U23B AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 PCI REQ0# GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55 C/BE0# C/BE1# C/BE2# C/BE3# IRDY# PAR PCIRST# DEVSEL# PERR# PLOCK# SERR# STOP# TRDY# FRAME# PLTRST# PCICLK PME# F1 G4 B6 A7 F13 F12 E6 F6 PCI_REQ#0 PCI_GNT#0 PCI_REQ#1 PCI_GNT#1 PCI_REQ#2 PCI_GNT#2 PCI_REQ#3 PCI_GNT#3 PAD T11 @ PAD T12 @ D8 B4 D6 A5 PCI_CBE#0 PCI_CBE#1 PCI_CBE#2 PCI_CBE#3 PAD PAD PAD PAD D3 E3 R1 C6 E4 C2 J4 A4 F5 D7 PCI_IRDY# PCI_PAR PCI_RST# PCI_DEVSEL# PCI_PERR# PCI_PLOCK# PCI_SERR# PCI_STOP# PCI_TRDY# PCI_FRAME# T13 @ T14 @ T15 @ T16 @ C14 D4 R2 PLT_RST# CLK_PCI_ICH @ PAD T17 PCI_RST# <35> Place closely pin B10 CLK_PCI_ICH 2 8 7 6 5 Low= DMI for ESI-compatible operation High= Default* (Internal pull-up) R1276 10_0402_5% @ PLT_RST# <8,17,27,31,32,36> CLK_PCI_ICH <16> C1573 10P_0402_50V8J @ Interrupt I/F PIRQA# PIRQB# PIRQC# PIRQD# ICH9-M ES_FCBGA676 1 2 PCI_PIRQE# PCI_PIRQF# PCI_PIRQG# PCI_PIRQH# H4 K6 F2 G2 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5 C 1 1 2 3 4 D RP36 A16 Swap Override Strap Low= A16 swap override Enable High= Default* PCI_GNT#3 R1277 1 B 2 1K_0402_5% PCI_GNT#3 @ B Boot BIOS Loaction 1 1 0 PCI 1 1 LPC* R1280 R1281 SPI 1 @ 2 1K_0402_5% PCI_GNT#0 1 @ 2 1K_0402_5% A P Y 4 PLT_RST_BUF# <34> R1278 100K_0402_5% 2 0 1 NC7SZ08P5X_NL_SC70-5 1 SPI_CS#1 U24 2 B G PCI_GNT#0 PLT_RST# 3 Boot BIOS Strap 5 +3VS SPI_CS#1 <27> A A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size Date: Compal Electronics, Inc. Document Number ICH9M(1/4)-PCI KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 25 of 53 4 3 +RTCVCC IN 4 1 +RTCVCC 1 2 R1287 20K_0402_5% 1 +RTCVCC close to RAM door 2 ICH_INTVRMEN High = Internal VR Enable +RTCVCC close to RAM door 1 2 R1290 @ 10K_0603_5% 1 2 R1291 @ 10K_0603_5% 1 2 1U_0603_10V6K C1577 1 2 1U_0603_10V6K C1576 SHORT Keep CMOS OPEN Keep ME RTC Registers OPEN C23 C24 A25 F20 C22 ICH_INTVRMEN B22 A22 RTCX1 RTCX2 INTVRMEN LAN100_SLP E25 C13 1 PROJECT_ID2 +1.5VS_PCIE_ICH 2 R1299 <38> HDA_BITCLK_MDC SATA_LED# R1300 <38> HDA_SYNC_MDC C R1301 <38> HDA_RST_MDC# R1302 +3V 1 <39> <38> <8> <18> R1305 10K_0402_5% @ <38> HDA_SDOUT_MDC GLAN_COMP 2 24.9_0402_1% HDA_BITCLK_ICH 2 33_0402_5% HDA_SYNC_ICH 2 33_0402_5% HDA_RST_ICH# 2 33_0402_5% 1 1 1 1 HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 1 2 HDA_SDOUT_ICH 33_0402_5% 2 R1306 PROJECT_ID2 1 2 R1307 10K_0402_5% SATA for HDD <29> SATA_DTX_C_IRX_N0 <29> SATA_DTX_C_IRX_P0 SATA for ODD <29> SATA_DTX_C_IRX_N1 <29> SATA_DTX_C_IRX_P1 GPIO56 GLAN_COMPI GLAN_COMPO INIT# INTR RCIN# NMI SMI# STPCLK# THRMTRIP# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 AG5 TP12 HDA_SDOUT AG7 AE8 AH13 AJ13 AG14 AF14 IGNNE# HDA_RST# AF4 AG4 AH3 AE5 SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 FERR# CPUPWRGD HDA_BIT_CLK HDA_SYNC AE7 AJ16 AH16 AF17 AG17 DPRSTP# DPSLP# LAN_TXD_0 LAN_TXD_1 LAN_TXD_2 AF6 AH4 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 A20GATE A20M# LAN_RXD0 LAN_RXD1 LAN_RXD2 B28 B27 AG8 LDRQ0# LDRQ1#/GPIO23 LAN_RSTSYNC B10 SATA_LED# <43> SATA_LED# FWH4/LFRAME# GLAN_CLK F14 G13 D14 R1297 FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 RTCRST# SRTCRST# INTRUDER# D13 D12 E13 10K_0402_5% R1291 +1.05VS U23A ICH_RTCRST# ICH_SRTCRST# SM_INTRUDER# +3VS 1 H_DPRSTP# R1284 H_DPSLP# R1286 Reset r1290 for power on then shut down issue ICH_RTCX2 1 2 R1288 20K_0402_5% TPM Settings LPC OUT NC C1575 18P_0402_50V8J 2 1 D R1289 332K_0402_1% NC Clear ME RTC Registers CPU SM_INTRUDER# 2 SHORT RTC 32.768KHZ_12.5P_MC-306 R1290 LAN / GLAN 3 1M_0402_5% 2 X1 CMOS Settings Clear CMOS IHDA R1283 ICH_RTCX1 R1285 10M_0402_5% 2 1 1 C1574 18P_0402_50V8J 2 1 www.bufanxiu.com 2 SATA4RXN SATA4RXP SATA4TXN SATA4TXP HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO34 SATALED# SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA_CLKN SATA_CLKP SATARBIAS# SATARBIAS SATA 5 SATA1RXN SATA1RXP SATA1TXN SATA1TXP K5 K4 L6 K2 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 K3 LPC_FRAME# J3 J1 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 2 2 1 @ 1 @ 56_0402_5% 56_0402_5% D <36> <36> <36> <36> LPC_FRAME# <36> R1292 2 N7 AJ27 EC_GA20 H_A20M# AJ25 AE23 DPRSTP# R1293 1 DPSLP# R1294 1 AJ26 FERR# AD22 H_PWRGOOD AF25 H_IGNNE# AE22 AG25 L3 H_INIT# H_INTR EC_KBRST# AF23 AF24 H_NMI H_SMI# AH27 H_STPCLK# AG26 THRMTRIP_ICH# 1 10K_0402_5% +3VS EC_GA20 <36> H_A20M# <4> 0_0402_5% H_DPRSTP# 0_0402_5% H_DPSLP# 2 2 1 R1295 H_DPRSTP# <5,8,50> H_DPSLP# <5> H_FERR# 2 56_0402_5% H_FERR# <4> H_PWRGOOD <5> 2 R1296 1 56_0402_5% 2 R1298 1 10K_0402_5% +1.05VS H_IGNNE# <4> H_INIT# H_INTR <4> <4> H_NMI H_SMI# <4> <4> R258 need to place within 2" of ICH9M R257 must be place within 2" of R258 w/o stub. H_STPCLK# <4> R1303 1 +3VS EC_KBRST# <36> 2 54.9_0402_1% H_THERMTRIP# AG27 2 R1304 C H_THERMTRIP# <4,8> 1 56_0402_5% +1.05VS AH11 AJ11 AG12 AF12 SATA_DTX_C_IRX_N5 SATA_DTX_C_IRX_P5 SATA_ITX_DRX_N5 SATA_ITX_DRX_P5 AH9 AJ9 AE10 AF10 AH18 AJ18 AJ7 AH7 CLK_PCIE_SATA# CLK_PCIE_SATA SATARBIAS SATA_DTX_C_IRX_N5 <35> SATA_DTX_C_IRX_P5 <35> CLK_PCIE_SATA# <16> CLK_PCIE_SATA <16> R1308 1 10mils width less than 500mils 2 24.9_0402_1% ICH9-M ES_FCBGA676 ID0 ID1 0 0 0 KAL90+ 1 0 0 KALH0 0 1 0 KALG0 1 1 0 HDA_BITCLK_ICH 2 33_0402_5% HDA_SYNC_ICH 2 33_0402_5% HDA_RST_ICH# 2 33_0402_5% HDA_SDOUT_ICH 2 33_0402_5% 1 R1313 GM@ 1 R1314 GM@ 1 R1315 GM@ 1 R1316 HDA_BITCLK_ICH 2 33_0402_5% HDA_SYNC_ICH 2 33_0402_5% HDA_RST_ICH# 2 33_0402_5% HDA_SDOUT_ICH 2 33_0402_5% <39> HDA_BITCLK_AUDIO ID2 KAL90 1 R1309 1 R1310 1 R1311 1 R1312 <39> HDA_SYNC_AUDIO HDA for AUDIO <39> HDA_RST_AUDIO# <39> HDA_SDOUT_AUDIO <8> HDA_BITCLK_MCH <8> HDA_SYNC_MCH HDA for GMCH <8> HDA_RST_MCH# <8> HDA_SDOUT_MCH GM@ close ICH9 SATA_ITX_DRX_N0 SATA_ITX_DRX_P0 SATA_ITX_DRX_N1 SATA_ITX_DRX_P1 SATA_ITX_DRX_N5 SATA_ITX_DRX_P5 B 1 C1578 1 C1579 SATA_ITX_C_DRX_N0 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P0 2 0.01U_0402_16V7K 1 C1580 1 C1581 SATA_ITX_C_DRX_N1 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P1 2 0.01U_0402_16V7K 1 C1582 1 C1583 SATA_ITX_C_DRX_N5 2 0.01U_0402_16V7K SATA_ITX_C_DRX_P5 2 0.01U_0402_16V7K SATA_ITX_C_DRX_N0 <29> SATA_ITX_C_DRX_P0 <29> SATA_ITX_C_DRX_N1 <29> SATA_ITX_C_DRX_P1 <29> MAINPWON SATA_ITX_C_DRX_N5 <35> SATA_ITX_C_DRX_P5 <35> +VCC_HDA_ICH R1317 @ 330_0402_5% 1 2 +1.05VS R1319 1K_0402_5% @ <18> HDA_SYNC_VGA HDA for VGA HDA_SDOUT_ICH <18> HDA_SDOUT_VGA ICH_TP3 A <18> HDA_RST_VGA# HDA_BITCLK_ICH 2 PM@33_0402_5% HDA_SYNC_ICH 2 PM@33_0402_5% HDA_RST_ICH# 2 PM@33_0402_5% HDA_SDOUT_ICH 2 PM@33_0402_5% <27> XOR Chain Entrance Strap R1323 1K_0402_5% @ ICH_TP3 5 HDA_SDOUT 0 RSVD 0 1 Enter XOR Chain 1 0 Normal Operation 1 1 Set PCIE port config bit 1 4 E Q89 2SC2411K_SOT23 @ H_THERMTRIP# Flash Descriptor Security Override Strap GPIO33 Description 0 C 2 B 3 1 R1318 1 R1320 1 R1321 1 R1322 <18> HDA_BITCLK_VGA <45,46> 1 PROJECT_ID B A Low= Descriptor Security override High= Default* (Internal pull-up) Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 3 2 Title Compal Electronics, Inc. ICH9M(2/4)-LAN,IDELPC,RTC Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 26 of 53 Rev 1.0 4 3 www.bufanxiu.com 2 1 Place closely pin B2 <36> PM_CLKRUN# VGATE <8,16,50> VGATE @ T20 1 1 2 R1355 10K_0402_5% @ 2 TP11 GPIO1 GPIO6 GPIO7 GPIO8 GPIO12 GPIO13 GPIO17 GPIO18 GPIO20 SCLOCK/GPIO22 GPIO27 GPIO28 SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49 GPIO57/CLGPIO5 USB_OC#10 USB_OC#3 USB_OC#7 USB_OC#6 8 7 6 5 SPKR MCH_SYNC# TP3 TP8 TP9 TP10 PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_PRX_N1 PCIE_ITX_PRX_P1 N29 N28 P27 P26 <34> PCIE_PTX_C_IRX_N2 <34> PCIE_PTX_C_IRX_P2 PCIE_ITX_C_PRX_N2 <34> PCIE_ITX_C_PRX_P2 C1588 2 C1589 2 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P2 L29 L28 M27 M26 J29 J28 K27 K26 C1590 2 C1591 2 1 1 PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_PRX_N3 0.1U_0402_16V7K PCIE_ITX_PRX_P3 0.1U_0402_16V7K <34> <34> <34> <34> PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_C_PRX_N4 PCIE_ITX_C_PRX_P4 C1592 2 C1593 2 1 1 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_PTX_C_IRX_N4 PCIE_PTX_C_IRX_P4 PCIE_ITX_PRX_N4 PCIE_ITX_PRX_P4 G29 G28 H27 H26 <31> <31> Reader<31> <31> PCIE_PTX_C_IRX_N5 PCIE_PTX_C_IRX_P5 PCIE_ITX_C_PRX_N5 PCIE_ITX_C_PRX_P5 1 1 PCIE_PTX_C_IRX_N5 PCIE_PTX_C_IRX_P5 PCIE_ITX_PRX_N5 0.1U_0402_16V7K PCIE_ITX_PRX_P5 0.1U_0402_16V7K E29 E28 F27 F26 C1594 2 C1595 2 ICH_SPI_CLK R1380 1 @ ICH_SPI_CS0# R1383 1 @ 2 CRT_DET <23> CRT_DET# 2 Q91 G 2N7002_SOT23 Low= Disable* High= iTPM enable by MCH strap ICH SPI ROM for HDCP D S 2 15_0402_5% 2 15_0402_5% <25> ICH_SPI_MOSI ICH_SPI_MISO R1384 1 @ R1385 1 @ 2 15_0402_5% 2 15_0402_5% DMI Termination Voltage GPIO49 Low= Desktop used High= Mobile* (Internal pull-up) 5 CL_DATA0 CL_DATA1 B13 R3 PBTN_OUT# D20 LAN_RST# ICH_PWROK B16 PM_SLP_M# @ D23 D24 F23 ICH_SPI_MOSI_R ICH_SPI_MISO_R D25 E23 USB_OC#0 CP_PE# USB_OC#1 USB_OC#3 USBRBIAS 2 1 R1388 Within 500 mils 22.6_0402_1% CS# WP# HOLD# GND VCC SCLK SI SO 8 6 5 2 ICH_SPI_CLK ICH_SPI_MOSI ICH_SPI_MISO ICH_GPIO13 2 R1406 CP_PE# 1 0_0402_5% 4 1 R1336 2 10K_0402_5% ICH_PWROK 1 R1341 2 10K_0402_5% EC_PWROK 1 R1346 2 10K_0402_5% PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 T21 @ 1 0_0402_5% +3VS @ CL_DATA0 <8> U26 ICH_PWROK CL_VREF0_ICH CL_VREF1_ICH 4 B A Y NC7SZ08P5X_NL_SC70-5 2 EC_PWROK 1 VGATE ICH_GPIO24 ICH_GPIO10 ICH_ACIN ICH_GPIO9 DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP DMI_CLKN DMI_CLKP SPI_CLK SPI_CS0# SPI_CS1#GPIO58/CLGPIO6 SPI_MOSI SPI_MISO OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31 OC8#/GPIO44 OC9#/GPIO45 OC10#/GPIO46 OC11#/GPIO47 AG2 AG1 SPI USB USBRBIAS USBRBIAS# PAD T24 @ C PAD T25 @ 2 1 +3V R1359 100K_0402_5% 2 1 ACIN D12 CH751H-40PT_SOD323-2 R1357 2 SB_RSMRST# <36,42,43,44,47> USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P V27 V26 U29 U28 DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0 Y27 Y26 W29 W28 DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1 AB27 AB26 AA29 AA28 DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2 AD27 AD26 AC29 AC28 DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3 T26 T25 CLK_PCIE_ICH# CLK_PCIE_ICH AF29 AF28 DMI_IRCOMP AC5 AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2 USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3 USB20_N4 USB20_P4 USB20_N5 USB20_P5 USB20_N6 USB20_P6 USB20_N7 USB20_P7 USB20_N8 USB20_P8 USB20_N9 USB20_P9 USB20_N10 USB20_P10 USB20_N11 USB20_P11 DMI_MTX_IRX_N0 DMI_MTX_IRX_P0 DMI_ITX_MRX_N0 DMI_ITX_MRX_P0 <8> <8> <8> <8> DMI_MTX_IRX_N1 DMI_MTX_IRX_P1 DMI_ITX_MRX_N1 DMI_ITX_MRX_P1 <8> <8> <8> <8> DMI_MTX_IRX_N2 DMI_MTX_IRX_P2 DMI_ITX_MRX_N2 DMI_ITX_MRX_P2 <8> <8> <8> <8> DMI_MTX_IRX_N3 DMI_MTX_IRX_P3 DMI_ITX_MRX_N3 DMI_ITX_MRX_P3 <8> <8> <8> <8> 2008/11/24 1 0_0402_5% 1 Q90 3 EC_RSMRST# <36> 1 R1365 2 4.7K_0402_5% +3V D13A 1 6 2 BAV99DW-7_SOT363 D13B 4 3 5 R1373 2.2K_0402_5% BAV99DW-7_SOT363 B +3VS CLK_PCIE_ICH# <16> CLK_PCIE_ICH <16> R1379 24.9_0402_1% 1 2 R1377 3.24K_0402_1% Within 500 mils +1.5VS_PCIE_ICH USB20_N0 <34> USB20_P0 <34> USB/B USB20_N1 <34,35> ESATA/USB CONN USB20_P1 <34,35> PAD T29 @ PAD T30 @ USB20_N3 <22> USB20_P3 <22> CMOS Camera PAD T45 @ PAD T46 @ USB20_N5 <35> USB20_P5 <35> New Card USB20_N6 <34> USB20_P6 <34> USB CONN PAD T47 @ PAD T49 @ USB20_N8 <35> USB20_P8 <35> Bluetooth USB20_N9 <35> USB20_P9 <35> Finger Print USB20_N10 <34> USB20_P10 <34> Mini Card(WLAN) USB20_N11 <34> USB20_P11 <34> Mini Card(TV-Tuner) CL_VREF0_ICH C1596 2009/12/31 Deciphered Date 2 1 +3V R1386 3.24K_0402_1% CL_VREF1_ICH C1597 1 0.1U_0402_16V4Z 2 Title R1381 453_0402_1% 0.1U_0402_16V4Z 2 No Reboot Strap Compal Secret Data Security Classification 3 @ Low= Default* SB_SPKR High= "No Reboot" ICH9-M ES_FCBGA676 Issued Date EC_PWROK <36,38> CL_RST#0 <8> DMI_ZCOMP DMI_IRCOMP PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP D No used Integrated LAN, connecting LAN_RST# to GND R1349 2 PAD CL_CLK0 <8> PERN2 PERP2 PETN2 PETP2 C1584 10P_0402_50V8J @ CK_PWRGD <16> F22 C19 PERN1 PERP1 PETN1 PETP1 2 PLT_RST# <8,17,25,31,32,36> THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SPI ROM Footprint 150mil 2 LAN_RST# R1364 10K_0402_5% N4 N5 N6 P6 M1 N2 M4 M3 N3 N1 P5 P3 USB_OC#5 USB_OC#6 USB_OC#7 USB_OC#8 USB_OC#9 USB_OC#10 USB_OC#11 1 1 2 0_0402_5% 1 C1585 10P_0402_50V8J @ PM_DPRSLPVR <8,50> F24 B19 A16 C18 C11 C20 MEM_LED/GPIO24 GPIO10/SUS_PWR_ACK GPIO14/AC_PRESENT WOL_EN/GPIO9 2 <8> 2 100_0402_5% F21 D18 CL_RST0# CL_RST1# 1 PM_SLP_S3# <36> PM_SLP_S4# <36> PM_SLP_S5# <36> CK_PWRGD R6 @ PBTN_OUT# <36> 1 R1344 SB_RSMRST# C25 A19 CL_VREF0 CL_VREF1 T19 ICH_PWROK 1 R1338 PM_BATLOW# U27 @ 1 3 7 4 MX25L4005AMC-12G_SO8 If ICH SPI not used, Left NC ICH_SPI_CLK_R ICH_SPI_CS0#_R SPI_CS#1 <34> USB_OC#0 <35> CP_PE# <35> USB_OC#1 +3VS ICH_SPI_CS0# ICH_SPI_WP# 2 ICH_SPI_HOLD# 2 DPRSLPVR R5 CL_CLK0 CL_CLK1 C29 C28 D27 D26 R1382 10K_0402_5% High: CRT Plugged Internal TPM Strap +3VS R1389 3.3K_0402_5% @ 1 R1390 1 @ 3.3K_0402_5% ICH_PWROK M2 U23D 0.1U_0402_16V7K 0.1U_0402_16V7K <35> USB_OC#6 A G20 D22 RSMRST# SLP_M# PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3 For Robson2 10K_1206_8P4R_5% SPI_MOSI LAN_RST# CLPWROK 1 1 1 RP42 BATLOW# PWRBTN# CK_PWRGD <32> <32> LAN <32> <32> For PCIE For Card 10K_1206_8P4R_5% DPRSLPVR/GPIO16 C10 S4_STATE# PAD 2 SATA GPIO VRMPWRGD PWROK C1586 2 C1587 2 For Wireless LAN<34> USB_OC#5 USB_OC#9 USB_OC#8 USB_OC#11 8 7 6 5 1 2 3 4 M7 AJ24 B21 AH20 AJ20 AJ21 ICH_TP8 ICH_TP9 ICH_TP10 WAKE# SERIRQ THRM# +3VS RP41 1 2 3 4 A20 AG19 AH21 AG21 A21 C12 C21 AE18 K1 AF8 AJ22 A9 D19 L1 AE19 AG22 AF21 AH24 A8 SB_SPKR PAD PAD PAD D21 CLKRUN# S4_STATE#/GPIO26 PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# R1328 10_0402_5% @ 2 For Express 2 CP_PE# 10K_0402_5% 2 USB_OC#0 10K_0402_5% 1 R1376 @ 1 R1378 1 ICH_VGATE 0_0402_5% ICH_TP11 2 R1343 STP_PCI# STP_CPU# PCIE_PTX_C_IRX_N1 PCIE_PTX_C_IRX_P1 PCIE_ITX_C_PRX_N1 PCIE_ITX_C_PRX_P1 <35> <35> Card<35> <35> 1 +3V <39> SB_SPKR <8> MCH_ICH_SYNC# R1361 <26> ICH_TP3 100K_0402_5% @ T26 @ T27 @ T28 E20 M5 AJ23 SMBALERT#/GPIO11 SUS_CLK C16 E16 G17 ICH9-M ES_FCBGA676 PROJECT_ID0 1 2 R1370 KAL90+_G0@ 10K_0402_5% 1 2 R1371 KAL90_H0@ 10K_0402_5% 1 2 R1401 KALH0_G0@ 10K_0402_5% PROJECT_ID1 1 2 R1372 KAL90_90+@ 10K_0402_5% PM_DPRSLPVR 1 2 R1374 @ 100K_0402_5% ICH_GPIO49 1 2 R1375 @ 1K_0402_5% B ICH_GPIO57 3 C L4 ICH_GPIO13 ICH_GPIO17 ICH_GPIO18 ICH_GPIO20 CR_WAKE# ICH_GPIO27 ICH_GPIO28 SATA_CLKREQ# ICH_GPIO38 ICH_GPIO39 ICH_GPIO48 ICH_GPIO49 ICH_GPIO57 <31> CR_WAKE# @ T22 PAD @ T23 PAD <16> SATA_CLKREQ# +3V PM_CLKRUN# OCP# CRT_DET CR_CPPE# EC_SMI# <31> CR_CPPE# <36> EC_SMI# <36> EC_SCI# ICH_SMBCLK 2 2.2K_0402_5% ICH_SMBDATA 2 2.2K_0402_5% EC_SWI# 2 10K_0402_5% ICH_SMLINK0 2 10K_0402_5% ICH_SMLINK1 2 10K_0402_5% LINKALERT# 2 10K_0402_5% XDP_DBRESET# 2 10K_0402_5% 2 ICH_PCIE_WAKE# 1K_0402_5% PM_BATLOW# 2 8.2K_0402_5% EC_LID_OUT# 2 10K_0402_5% ICH_GPIO10 2 10K_0402_5% ICH_GPIO13 2 10K_0402_5% S4_STATE# 2 10K_0402_5% A14 E19 PAD OCP# +3V 1 R1351 1 R1352 1 R1353 1 R1354 1 R1356 1 R1358 1 R1360 1 R1362 1 R1363 1 R1366 1 R1367 1 R1368 1 R1369 @ H_STP_PCI# H_STP_CPU# ICH_PCIE_WAKE# SERIRQ EC_THERM# <34,35> ICH_PCIE_WAKE# <36> SERIRQ <36> EC_THERM# <4> A17 PMSYNC#/GPIO0 P1 R1333 10_0402_5% @ CLK_ICH_14M <16> CLK_ICH_48M <16> MMBT3906_SOT23-3 C 2 B E <16> H_STP_PCI# <16> H_STP_CPU# EC_LID_OUT# SUSCLK SLP_S3# SLP_S4# SLP_S5# CLK_ICH_14M CLK_ICH_48M CLK_ICH_14M 5 @ <36> EC_LID_OUT# SUS_STAT#/LPCPD# SYS_RESET# H1 AF3 P @ <8> PM_SYNC# M6 CLK14 CLK48 G @ R4 G19 PM_SYNC# clocks 2 10K_0402_5% 3 @ SUS_STAT# XDP_DBRESET# RI# Place closely pin AC1 CLK_ICH_48M 1 @ PAD F19 PROJECT_ID1 PROJECT_ID0 R1325 1 2 @ @ T18 <4> XDP_DBRESET# EC_SWI# SMB AH23 AF19 AE21 AD20 SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37 Direct Media Interface @ EC_SWI# SMBCLK SMBDATA LINKALERT#/GPIO60/CLGPIO4 SMLINK0 SMLINK1 PCI - Express @ <36> G16 A13 E17 C17 B18 SYS / GPIO @ U23C ICH_SMBCLK ICH_SMBDATA LINKALERT# ICH_SMLINK0 ICH_SMLINK1 <16,32,34,35> ICH_SMBCLK <16,32,34,35> ICH_SMBDATA Power MGT D SERIRQ 2 10K_0402_5% PM_CLKRUN# 2 8.2K_0402_5% EC_THERM# 2 8.2K_0402_5% H_STP_PCI# 2 10K_0402_5% H_STP_CPU# 2 10K_0402_5% SB_SPKR 2 1K_0402_5% CR_WAKE# 2 10K_0402_5% ICH_SPI_MOSI 2 1K_0402_5% OCP# 2 10K_0402_5% CR_CPPE# 2 10K_0402_5% ICH_GPIO17 2 10K_0402_5% ICH_GPIO18 2 10K_0402_5% ICH_GPIO20 2 10K_0402_5% SATA_CLKREQ# 2 10K_0402_5% ICH_GPIO38 2 10K_0402_5% ICH_GPIO39 2 10K_0402_5% ICH_GPIO48 2 10K_0402_5% MISC GPIO Controller Link 1 R1324 1 R1332 1 R1326 1 R1327 1 R1329 1 R1334 1 R1330 1 R1331 1 R1335 1 R1337 1 R1339 1 R1340 1 R1342 1 R1345 1 R1347 1 R1348 1 R1350 1 5 +3VS R1387 453_0402_1% A Compal Electronics, Inc. ICH9M(3/4)-USB,GPIO,PCIE Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet 27 of 53 Rev 1.0 5 4 CH751H-40PT_SOD323-2 +ICH_V5REF_SUS 2 C1605 1U_0402_6.3V6K +1.5VS_PCIE_ICH (220UF*1, 22UF*2, 2.2UF*1) L38 2 1 KC FBM-L11-201209-221LMAT_0805 1 +1.5VS C1607 + C1608 220U_D2_4VM_R15 2 1 2 C1609 1 C1610 10U_0805_10V4Z 2 10U_0805_10V4Z 2.2U_0603_6.3V6K +1.5VS_SATAPLL_ICH C L39 1 2 MBK1608301YZF_0603 +1.5VS 1 (10UF*1, 1UF*1) 1 C1620 C1621 10U_0805_10V4Z 2 2 1U_0402_6.3V6K AJ19 +1.5VS S 3 +5VALW G 2 <42> SBPWR_EN# 1 Q92 AO3413_SOT23-3 2 1 C1624 D 1 0.1U_0402_16V4Z 1 2 1U_0402_6.3V6K 2 1U_0402_6.3V6K +5V AC16 AD15 AD16 AE15 AF15 AG15 AH15 AJ15 B AC9 AC18 AC19 AC21 G10 G9 AC12 AC13 AC14 close to AC7 AJ5 +1.5VS 1 0.1U_0402_16V4Z 2 C1632 1 AA7 AB6 AB7 AC6 AC7 close to AJ5 2 0.1U_0402_16V4Z +3VS R1398 0_0603_5% 1 C1634 +1.5VS R1399 0.1U_0402_16V4Z (10UF*1, 0_0603_5%1 A10 A11 A12 B12 +VCC_GLANPLL_ICH A27 C1639 D28 D29 E26 E27 C1638 2.2UF*1) 10U_0805_10V4Z 2 2.2U_0603_6.3V6K +1.5VS R1400 (4.7UF*1) 0_0603_5% C1640 A26 +VCCGLAN_ICH VCC3_3[01] VCC3_3[02] VCC3_3[07] VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16] VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14] VCCSUSHDA VCCSATAPLL VCC1_5_A[01] VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08] VCC3_3[03] VCC3_3[04] VCC3_3[05] VCC3_3[06] VCCHDA VCCSUS1_05[1] VCCSUS1_05[2] VCCSUS1_5[1] VCCSUS1_5[2] VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04] VCCSUS3_3[05] L37 1 2 MBK1608301YZF_0603 1 VCC1_5_A[21] VCC1_5_A[22] VCC1_5_A[23] VCC1_5_A[24] VCC1_5_A[25] VCCUSBPLL VCCLAN1_05[1] VCCLAN1_05[2] VCCCL1_05 VCCCL1_5 VCCLAN3_3[1] VCCLAN3_3[2] VCCGLAN1_5[1] VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4] VCCGLAN3_3 VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20] VCCCL3_3[1] VCCCL3_3[2] +1.5VS (10UF*1, 0.01UF*1) C1604 C1603 10U_0805_10V4Z 2 0.01U_0402_16V7K +1.05VS (4.7UF*1) 1 4.7U_0805_10V4Z R29 2 W23 Y23 AB23 AC23 C1611 AG29 AJ6 AC10 C1612 4.7U_0805_10V4Z 1 2 +1.05VS 1 C1613 (4.7UF*1, 0.1UF*2) 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z AD19 AF20 AG24 AC20 close to AG29 B9 F9 G3 G6 J2 J7 K7 C1614 1 2 C1615 close to AD19 1 2 C1616 1 2 close to AJ6 close to G6 C1617 1 2 C1618 1 2 close to B9 1 2 +3VS close to K7 R1394 PM@ AJ3 1 AC8 TP_VCCSUS1_05_ICH_1 F17 TP_VCCSUS1_05_ICH_2 PAD PAD @ T31 @ T32 AD8 TP_VCCSUS1_5_ICH_1 PAD @ T33 F18 C1619 +VCC_HDA_ICH AJ4 2 R1395 C1622 1 A18 D16 D17 E22 2 R1396 PM@ 1 C1626 0.1U_0402_16V4Z 2 +3VS +1.5VS 0.1U_0402_16V4Z 0_0603_5% R1397 GM@ 0_0603_5% C1627 0.1U_0402_16V4Z AF1 +3V +1.5V Check Power Source +3V T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7 G22 G23 0_0603_5% GM@0_0603_5% +VCCSUS_HDA_ICH +VCCSUS1_5_ICH_INT_2 C1629 0.022U_0402_16V7K VCC1_5_A[20] VCCGLANPLL 2 C1628 VCC1_5_A[18] VCC1_5_A[19] VCC1_5_A[26] VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30] 0.1U_0402_16V4Z +1.5VS_DMIPLL_ICH VCC1_5_A[17] GLAN POWER 2 A 2 1 +VCCLAN1_05_INT_ICH C1633 0.1U_0402_16V4Z +VCCLAN_ICH V_CPU_IO[1] V_CPU_IO[2] USB CORE C1631 VCC_DMI[1] VCC_DMI[2] ATX AC11 AD11 AE11 AF11 AG10 AG11 AH10 AJ10 VCCDMIPLL 1 0.1U_0402_16V4Z C1606 ARX C1625 C1623 VCCA3GP 1 2 C1601 0.1U_0402_16V4Z D15 1 1 1 R1393 R1391 @ 100_0402_1% 10_0402_5% VCC1_5_B[01] VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49] 1 0.1U_0402_16V4Z +3V V5REF_SUS C1600 0.1U_0402_16V4Z C1602 1U_0402_6.3V6K AE1 AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29 F25 G25 H24 H25 J24 J25 K24 K25 L23 L24 L25 M24 M25 N23 N24 N25 P24 P25 R24 R25 R26 R27 T24 T27 T28 T29 U24 U25 V24 V25 U23 W24 W25 K23 Y24 Y25 V5REF 0.1U_0402_16V4Z +ICH_V5REF_SUS +ICH_V5REF 2 +5V 2 2 +5VALW A6 VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16] VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26] 0.1U_0402_16V4Z +ICH_V5REF 1 2 1 U23E +1.05VS 0.1U_0402_16V4Z 1 CORE C1599 0.1U_0402_16V4Z 2 2 1U_0402_6.3V6K VCCP_CORE 1 1 PCI C1598 D14 CH751H-40PT_SOD323-2 VCCPSUS 2 2 1 R1392 100_0402_1% VCCRTC A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18 1 C1630 1 (0.1UF*1, 0.022UF*2) 0.1U_0402_16V4Z 2 2 0.022U_0402_16V7K close to A18 close to T1 +VCCCL1_05_INT_ICH +VCCCL1_5_INT_ICH C1635 @ 1U_0402_6.3V6K A24 B24 +3VS 1 C1637 @ 2 1 C1636 2 1 +3VS H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25 VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] D C B A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29 VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12] ICH9-M ES_FCBGA676 0.1U_0402_16V4Z A (1UF*1, 0.1UF*1) Compal Secret Data Security Classification 2008/11/24 Issued Date 4 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] (0.1UF*1) 2 0.1U_0402_16V4Z 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 AA26 AA27 AA3 AA6 AB1 AA23 AB28 AB29 AB4 AB5 AC17 AC26 AC27 AC3 AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29 AD4 AD5 AD6 AD7 AD9 AE12 AE13 AE14 AE16 AE17 AE2 AE20 AE24 AE3 AE4 AE6 AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27 AF5 AF7 AF9 AG13 AG16 AG18 AG20 AG23 AG3 AG6 AG9 AH12 AH14 AH17 AH19 AH2 AH22 AH25 AH28 AH5 AH8 AJ12 AJ14 AJ17 AJ8 B11 B14 B17 B2 B20 B23 B5 B8 C26 C27 E11 E14 E18 E2 E21 E24 E5 E8 F16 F28 F29 G12 G14 G18 G21 G24 G26 G27 G8 H2 H23 H28 H29 ICH9-M ES_FCBGA676 4.7U_0805_10V4Z www.bufanxiu.com 2 U23F A23 +RTCVCC D 3 +3VS VCCPUSB +5VS 3 2 Title Compal Electronics, Inc. ICH9M(4/4)-POWER&GND Size Document Number Custom Date: KALH0/KALG0/KAL90+ Sheet Monday, April 27, 2009 1 28 of Rev 1.0 53 5 4 3 +5VS C1934 2 1 2 1000P_0402_50V7K D 1 +3VS 0.1U_0402_16V4Z 1 www.bufanxiu.com 2 C1935 0.1U_0402_16V4Z 1 1 C1936 2 1 C1937 2 10U_0805_10V4Z 1 C1938 2 C1939 2 1000P_0402_50V7K 10U_0805_10V4Z D SATA HDD Conn. <26> SATA_DTX_C_IRX_N0 <26> SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 1 C1940 SATA_DTX_IRX_N0 2 0.01U_0402_16V7K 1 C1941 SATA_DTX_IRX_P0 2 0.01U_0402_16V7K JSATA1 1 2 3 4 5 6 7 SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0 <26> SATA_ITX_C_DRX_P0 <26> SATA_ITX_C_DRX_N0 SATA_DTX_IRX_N0 SATA_DTX_IRX_P0 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 +3VS +5VS C GND HTX+ HTXGND HRXHRX+ GND VCC3.3 VCC3.3 VCC3.3 GND GND GND VCC5 VCC5 VCC5 GND RESERVED GND VCC12 VCC12 GND VCC12 GND C 24 23 OCTEK_SAT-22SU1G_NR CONN@ C1942 2 1 C1943 2 10U_0805_10V4Z 1 0.1U_0402_16V4Z 1000P_0402_50V7K +5VS 1 C1944 2 SATA ODD Conn. B B JSATA2 SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1 <26> SATA_ITX_C_DRX_P1 <26> SATA_ITX_C_DRX_N1 SATA_DTX_IRX_N1 SATA_DTX_IRX_P1 R1664 1 @ 2 1K_0402_1% +5VS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND GND 16 17 OCTEK_SLS-13DB1G_NR A <26> SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_N1 1 C1945 SATA_DTX_IRX_N1 2 0.01U_0402_16V7K <26> SATA_DTX_C_IRX_P1 SATA_DTX_C_IRX_P1 1 C1946 SATA_DTX_IRX_P1 2 0.01U_0402_16V7K CONN@ A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. HDD & ODD Connector Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 29 Rev 1.0 of 53 5 4 3 2 PCIE_MTX_C_GRX_N[0..15] 20071029: C1 (10U_0805) close to JP1.Pin 226, 228, 230 20071029: C2, C3, C4, C5, C6, C7, C8 (0.1U_0402) close to U1 VCC (+3VS) pins (one Pin one Capacitor) PCIE_MTX_C_GRX_P[0..15] 1 PCIE_MTX_C_GRX_N[0..15] <10,17> PCIE_MTX_C_GRX_P[0..15] <10,17> www.bufanxiu.com 1 C2174 GM@ 2 1 2 C2175 GM@ 1 C2176 GM@ 2 1 C2177 GM@ 2 0.1U_0402_16V4Z C2173 GM@ 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z C2172 GM@ 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z C2171 GM@ 2 0.1U_0402_16V4Z 1 0.1U_0402_16V4Z 10U_0805_10V4Z +3VS 1 C2178 GM@ 2 20071210: R3 change to 0_0402_1% (Old-10K) D U67 GM@ +3VS OE# 20071210: R6 change to 1K_0402_1% (Old - 1.2K) @ @ 2 4.7K_0402_5% 2 4.7K_0402_5% R1895 R1894 1 1 @ 2 4.7K_0402_5% GM@ 2 4.7K_0402_5% R1873 2.2K_0402_5% GM@ 2 499_0402_1% To GMCH SDVO_SDATA 6 <24> UMA_DVI_TXD2+ <24> UMA_DVI_TXD2<24> UMA_DVI_TXD1+ <24> UMA_DVI_TXD1<24> UMA_DVI_TXD0+ <24> UMA_DVI_TXD0- 2 UMA_DVI_TXD2- R1878 1 GM@ 68_0402_5% 2 UMA_DVI_TXD1- R1879 1 GM@ 68_0402_5% 2 UMA_DVI_TXD0- R1880 1 GM@ 68_0402_5% 2 16 17 UMA_DVI_TXD1+ UMA_DVI_TXD1- 19 20 UMA_DVI_TXD0+ UMA_DVI_TXD0- 1 C2179 1 C2180 1 C2181 1 C2182 UMA_DVI_TXC+ 0.5P_0402_50V8D 2 UMA_DVI_TXD2+ 0.5P_0402_50V8D OUT_D4+ OUT_D4- IN_D4+ IN_D4- OUT_D3+ OUT_D3- IN_D3+ IN_D3- OUT_D2+ OUT_D2- IN_D2+ IN_D2- OUT_D1+ OUT_D1- UMA_DVI_TXD0+ 0.5P_0402_50V8D IN_D1+ IN_D1- 2 4.7K_0402_5% 2 4.7K_0402_5% R1892 R1891 1 1 @ @ 2 4.7K_0402_5% 2 4.7K_0402_5% 20080118 (JAL90_PVT): Add R17 for Inverting Current 1 HDMI_PCIE_MTX_C_GRX_P3 HDMI_PCIE_MTX_C_GRX_N3 45 44 HDMI_PCIE_MTX_C_GRX_P0 HDMI_PCIE_MTX_C_GRX_N0 20071026: Del R4 (0_0402_5%) for D_DVI_DET remove. +3VS 42 41 HDMI_PCIE_MTX_C_GRX_P1 HDMI_PCIE_MTX_C_GRX_N1 39 38 HDMI_PCIE_MTX_C_GRX_P2 HDMI_PCIE_MTX_C_GRX_N2 C HDMI_PCIE_MTX_C_GRX_N[0..3] kal90+ 2 20080128_PVT (change to B version): SA00001U900 (CH7318A-BF-TR) SA00001U910 (CH7318B-BF-TR) TMDS_B_HPD# D S 1 2 G <10> Q139 2N7002_SOT23 @ R1883 7.5K_0402_1% @ 2 2 R1884 20K_0402_5% @ HDMI_PCIE_MTX_C_GRX_P[0..3] HDMI_PCIE_MTX_C_GRX_N[0..3] <10> HDMI_PCIE_MTX_C_GRX_P[0..3] <10> Intel Cantiga TMDS Pin Definition R1881 20K_0402_5% @ R1882 GM@ 0_0402_5% HPD_7318 +3VS 20071031: Add U1. 49 (THERMAL_GND) to GND Plane +3VS B 20071026: C9,C10,C11,C12Change P/N to SA00000AU00 (0.5P_0402_50V8D) 20080130_PVT C9,C10,C11,C12Change P/N to SE00000HA00 (0.5P 50V C NPO 0402) 2 4.7K_0402_5% @ @ 48 47 GND GND GND GND GND GND GND GND GND GND PAD 2 2 1 GM@ 1 1 <18,24> <18,24> RT_EN# GM@ GM@ R1868 R1889 R1893 PS8101TQFN48G_QFN48_7X7 2 UMA_DVI_TXD1+ 0.5P_0402_50V8D 34 35 HDMI_DET SCL 1 5 12 18 24 27 31 36 37 43 49 GM@ 30 32 <18,24> VGA_HDMI_SDATA SDA 22 23 GM@ VGA_HDMI_SCLK 1 R1877 1 GM@ 68_0402_5% UMA_DVI_TXD2+ UMA_DVI_TXD2- AS Short PASSS 20071210: R9~R12 change to 68_0402_5% (Old - 6.8) UMA_DVI_TXC- 13 14 <24> 29 1 Trace UMA_DVI_TXC+ UMA_DVI_TXC- CFG0 CFG1 HDMI_DET# HPD# 10 <24> UMA_DVI_TXC+ <24> UMA_DVI_TXC- DDC_EN HDMI_DET# 28 REXT 7 9 C HPD_SINK PC1 PC0 8 SDVO_SCLK <8> SDVO_SCLK SDA_SINK 25 2 <8> SDVO_SDATA 4 3 1 GM@ R50 HPD_7318 2 2 R1872 2.2K_0402_5% GM@ 1 1 SCL_SINK 1 1 1 +3VS R1887 R1890 VCC VCC VCC VCC VCC VCC VCC VCC 3 +3VS 2 11 15 21 26 33 40 46 D TMDS_B_CLK TMDS_B_CLK# PEG_TXP_3 PEG_TXN_3 TMDS_B_DATA0 TMDS_B_DATA0# PEG_TXP_2 PEG_TXN_2 TMDS_B_DATA1 TMDS_B_DATA1# PEG_TXP_1 PEG_TXN_1 TMDS_B_DATA2 TMDS_B_DATA2# PEG_TXP_0 PEG_TXN_0 TMDS_B_HPD# PEG_RXP_3 B A A Issued Date 2008/11/24 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 Compal Electronics, Inc. Compal Secret Data Security Classification 2 Title Size C Date: HDMI/DVI CH7318 Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 1 Sheet Rev 1.0 30 of 53 5 4 3 www.bufanxiu.com 2 1 MDIO PULL HIGH/LOW ? C1952 2 1 C1953 2 1 C1955 2 1 C1954 2 1 C256 @ 2 0.1U_0402_16V4Z 2 1 4.7U_0603_6.3V6M 2 C1951 1000P_0402_50V7K 1 0.1U_0402_16V4Z +1.8VS 1 C1950 +3V_MCVCC 40mil 0.1U_0402_16V4Z 2 L70 MBK1608121YZF_0603 1 2 @ 0.1U_0402_16V4Z 2 1 C1949 +1.8VS_APVDD 22U_0805_6.3V6M 2 1 C1948 0.1U_0402_16V4Z 1 C1947 0.1U_0402_16V4Z 40mil 0.1U_0402_16V4Z D 0.1U_0402_16V4Z +3VS 1 C1980 @ 2 C1956 1 C1957 1 <27> PCIE_PTX_C_IRX_N5 <27> PCIE_PTX_C_IRX_P5 2 2 PCIE_PTX_IRX_N5 PCIE_PTX_IRX_P5 0.1U_0402_16V7K 0.1U_0402_16V7K R1670 1 9 8 2 8.2K_0402_1% 11 12 APREXT APREXT 12 mil 7 38 39 +3VS APCLKN APCLKP APVDD APV18 TAV33 APRXN APRXP DV33 DV33 DV33 DV18 DV18 APTXN APTXP APREXT PCIES_EN PCIES JMB385 C 1 2 <8,17,25,27,32,36> PLT_RST# 1 <27> CR_CPPE# <27> CR_WAKE# @ R1674 2 0_0402_5% T39 PAD @ 13 14 TP_SEECLK D40 @ CH751H-40PT_SOD323-2 1 2 XDCD1#_MSCD# XDCD0#_SDCD# 15 16 1 R1675 @ 0_0402_5% +3V_MCPWR 17 2 MC_PWREN# 40 mil 21 <43> 5IN1_LED# XRSTN XTEST SEEDAT SEECLK MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 MDIO8 MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14 NC NC NC CR1_CD1N CR1_CD0N APGND CR1_PCTLN GND GND GND GND CR1_LEDN 5 10 30 +1.8VS_APVDD +3VS 19 20 44 18 37 2 XD_RB 2 R1666 48 47 46 45 43 42 41 40 29 28 27 26 25 23 22 1 10K_0402_5% 10K_0402_5% D 10K_0402_5% 1 2 XDCD0#_SDCD# 1 R1668 2 XDCD1#_MSCD# 1 R1669 2 XD_RE 1 2 1 2 R1667 10K_0402_5% 4.7K_0402_5% 4.7K_0402_5% +1.8VS_APVDD XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 SDCMD_MSBS_XDWE# MDIO5 R1672 1 XDWP_SDWP XD_CLE XD_D4 XD_D5 XD_D6 XD_D7 XD_RE XD_RB XD_ALE 2 22_0402_5% XDCE_SDCLK_MSCLK R1671 XD_ALE R1673 200K_0402_5% 200K_0402_5% C 34 35 36 6 XDCD0#_SDCD# 24 31 32 33 XDCD1#_MSCD# 1 JMB385-LGEZ0B_LQFP48_7X7 2 C448 @ 2 1U_0402_6.3V6K PCIE_ITX_C_PRX_N5 PCIE_ITX_C_PRX_P5 <27> PCIE_ITX_C_PRX_N5 <27> PCIE_ITX_C_PRX_P5 XDWP_SDWP 1 R1665 XD_CLE 1U_0402_6.3V6K 3 4 2 +3VS U48 <16> CLK_PCIE_READER# <16> CLK_PCIE_READER SDCMD_MSBS_XDWE#1 R1690 3 1 2 D41 1 XD_CD# C1958 DAN202UT106_SC70-3 C449 @ 270P_0402_50V7K 4 IN 1 Socket Push Type(New) B Memory Card Power Switch @ GND IN IN EN# OUT OUT OUT FLG 40mil 8 7 6 5 2 C1959 1 1 +3V_MCPWR U49 C1961 1 2 C1979 1 @ 4.7U_0805_10V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z 1 2 TPS2061DRG4_SO8 R1676 @ 300_0603_5% C1960 1 C1975 1 @ D +3V_MCPWR 2 0.1U_0402_16V4Z 1 2 3 4 C1973 1 @ 0.1U_0402_16V4Z +3V_MCVCC 0.1U_0402_16V4Z +3VS 3 +3V_MCVCC XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XD_D4 XD_D5 XD_D6 XD_D7 SDCMD_MSBS_XDWE# 34 XDWP_SDWP 33 XD_ALE 35 XD_CD# 40 XD_RB 39 XD_RE 38 XDCE_SDCLK_MSCLK 37 XD_CLE 36 Q116 @ 2N7002_SOT23 2 G 32 10 9 8 7 6 5 4 11 31 3 S 41 42 A +3V_MCPWR 1 2 1 R1677 2 0_0805_5% B JREAD1 XD-VCC SD-VCC MS-VCC XD-D0 XD-D1 XD-D2 XD-D3 XD-D4 XD-D5 XD-D6 XD-D7 7 IN 1 CONN XD-WE XD-WP XD-ALE XD-CD XD-R/B XD-RE XD-CE XD-CLE SD-WP-SW MS-SCLK MS-DATA0 MS-DATA1 MS-DATA2 MS-DATA3 MS-INS MS-BS 7IN1 GND 7IN1 GND 7IN1 GND 7IN1 GND TAITW_R015-B10-LM +3V_MCVCC +3V_MCVCC 20 14 12 30 29 27 23 18 16 25 1 XDCE_SDCLK_MSCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 (MMC XD_D4 (MMC XD_D5 (MMC XD_D6 (MMC XD_D7 SDCMD_MSBS_XDWE# XDCD0#_SDCD# 2 XDWP_SDWP 26 17 15 19 24 22 13 XDCE_SDCLK_MSCLK XD_SD_MS_D0 XD_SD_MS_D1 XD_SD_MS_D2 XD_SD_MS_D3 XDCD1#_MSCD# SDCMD_MSBS_XDWE# Data Data Data Data Bit Bit Bit Bit 4) 5) 6) 7) A CONN@ C1962 4.7U_0805_10V4Z Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 SD_CLK SD-DAT0 SD-DAT1 SD-DAT2 SD-DAT3 SD-DAT4 SD-DAT5 SD-DAT6 SD-DAT7 SD-CMD SD-CD-SW 21 28 4 3 2 Title Compal Electronics, Inc. Card Reader JMB385 Size Document Number Custom Date: KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 31 Rev 1.0 of 53 A B www.bufanxiu.com C D +3V_LAN +3V_LAN 2 Q117 1 Place Close to Pin 2 R60 2 +2.5V_VDDH 0_0402_5% CTR12 1 C199 0.1U_0402_16V4Z 2 8131@ 1 1 2 2 1 C1972 0.1U_0402_16V4Z 8121@ +3V_LAN 2 0_0603_5% +1.8_VDD/LX 1U_0402_6.3V4Z 1 1 VDDHO/VDD18O/VDD18O TWSI_DATA TWSI_CLK LED_LINK10_100n LED_ACTn 2 8131@ 6 0.1U_0402_16V7K CTR12 <8,17,25,27,31,36> 5 3 PLT_RST# VDD3V VDD3V/VDDHO/VDDHO SPI_CS/LED_DUPLEXn/LED_DUPLEXn SPI_DI/NC/LED_Link1000n VDDLO/CTR12/CTR12 REFCLKN REFCLKP PERSTn TXN0/TXN0/TRXN0 TXP0/TXP0/TRXP0 RXN1/RXN1/TRXN1 RXP1/RXP1/TRXP1 NC/NC/TRXN2 NC/NC/TRXP2 NC/NC/TRXN3 NC/NC/TRXP3 8121@ 2 1 C1983 VAUX/VREF 1000P_0402_50V7K <27> <27> <27> <27> <36> EC_PME# PCIE_PTX_C_IRX_N3 PCIE_PTX_C_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3 C1984 C1985 1 1 7 4 37 38 44 43 PCIE_PTX_IRX_N3 PCIE_PTX_IRX_P3 PCIE_ITX_C_PRX_N3 PCIE_ITX_C_PRX_P3 2 0.1U_0402_16V7K 2 0.1U_0402_16V7K XTALO LAN_XTALI 9 10 34 35 <16,27,34,35> ICH_SMBCLK +3V_LAN <16,27,34,35> ICH_SMBDATA 3 1 31 33 2 R1706 4.7K_0402_1% 49 R1708 1 2 2.37K_0402_1% 12 VAUX_AVL/VBG1P18/VBG1P18 WAKEn TX_N TX_P RX_N RX_P XTLO XTLI AR8121/8131 TESTMODE NC SMCLK SMDATA AVDDL0 AVDDL1 AVDDL2 DVDDL/AVDDL/AVDDL AVDDL3 AVDDL4 AVDDL5 DVDDL0 AVDDL/DVDDL/DVDDL DVDDL1 SPI_CLK/DVDDL/DVDDL GND SPI_DO/AVDDH/AVDDH AVDDH0 AVDDH1 RBIAS 30 29 48 47 LAN_ACTIVITY# 27 26 PAD T51 <33> @ 1000_LINK_LED 40 41 14 13 18 17 21 20 24 23 LAN_MIDI0+ R1678 LAN_MIDI0R1679 LAN_MIDI1+ R1682 LAN_MIDI1R1683 LAN_MIDI2+ R1684 LAN_MIDI2R1687 LAN_MIDI3+ R1689 LAN_MIDI3R1691 TWSI_SDA TWSI_SCL 10/100_LINK_LED CLK_PCIE_LAN# <16> CLK_PCIE_LAN <16> LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+ 42 39 36 22 16 11 8 +AVDDVCO2 +1.2_AVDDL 46 45 32 28 +1.2_DVDDL 25 19 15 +2.5V_VDDH LAN_MIDI0LAN_MIDI0+ LAN_MIDI1LAN_MIDI1+ LAN_MIDI2LAN_MIDI2+ LAN_MIDI3LAN_MIDI3+ <33> <33> <33> <33> <33> <33> <33> <33> 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 49.9_0402_1% 2 1 R1697 TWSI_SCL TWSI_SDA 1 2 C1963 0.1U_0402_16V4Z 1 2 C1964 0.1U_0402_16V4Z 1 2 C1965 0.1U_0402_16V4Z 1 2 C1969 0.1U_0402_16V4Z 49.9_0402_1% 2 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% Place Close to Pin151925 C1061 close to Pin15 +2.5V_VDDH +AVDDVCO1 +1.2_AVDDL 1 2 1 C213 C1977 8 7 6 5 VCC WP SCL SDA U51 60mil +2.5V_VDDH/VDD17 1U_0402_6.3V4Z A0 A1 A2 GND 1 2 0.1U_0402_16V4Z 1 1 2 3 4 <33> C212 1 LAN_LINK# AT24C02BN-SH-T_SO8 +3V_LAN 2 1 0.1U_0402_16V4Z 8121@ 2 2 3 Place Close to LAN chip C1976 C1978 1000_LINK_LED CHP202UPT_SOT323-3 2 8121@ +2.5V_VDDH 2 1 8121@ 2 R59 2 R1695 1 +2.5V_VDDH/VDD17 C211 8131@ 2 1 8131@ 2 R58 0_0603_5% C198 10U_0805_10V4Z 8131@ 1 0.1U_0402_16V4Z C197 1 U50 @ 1U_0402_6.3V4Z +AVDD_CEN 2 4.7K_0402_1% D42 10/100_LINK_LED 1 C1974 2 S INDUC_ 4.7UH +-20% SIA4012-4R7M 4.7K_0402_1% 0_0603_5% 8131@ 1 L6 +3V_LAN +1.8_VDD/LX 1 8121@ 2 R63 1 NJT4030PT1G_SOT223 8121@ +1.2_AVDDL C1971 10U_0805_10V4Z 8121@ <33> +AVDD_CEN 8131@ R1688 10K_0402_1% 8121@ 0.1U_0402_16V4Z 2 C1966 0.1U_0402_16V4Z 8121@ 1 1 1 0.1U_0402_16V4Z 2 C1999 C1998 1 1U_0402_6.3V4Z C1997 2 10U_0805_10V4Z 2 1 4 2 1 1 10U_0805_10V4Z C1996 0_1206_5% 2 60mil 2 R1707 3 1 +3VALW 2 3 +1.2_AVDDL 8121@ 1 L71 +1.2_DVDDL 2 FBMA-L11-201209-221LMA30T_0805 AR8121-AL1E_QFN48_6X6 SA000031Z00 S IC AR8131-AL1E QFN 48P E-LAN CTRL 1 2 C210 2 1 25MHZ_20P 2 1 2 1 1 2 1U_0402_6.3V4Z C1968 1 1000P_0402_50V7K +AVDDVCO1 +AVDDVCO2 2 R1862 0_0603_5% 8131@ 1 C1970 0.1U_0402_16V4Z 2 4 8121 2 LAN_XTALO C1994 27P_0402_50V8J @ 2 0_0603_5% 2 0.1U_0402_16V4Z C214 2 1 0.1U_0402_16V4Z C208 1 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z 2 1 C207 8121@ C206 2 1 0.1U_0402_16V4Z 8121@ 1 1U_0402_6.3V4Z 2 C205 C204 2 1 0.1U_0402_16V4Z C203 2 1 0.1U_0402_16V4Z C202 2 1 0.1U_0402_16V4Z Y2 1 1 4 2 1 0.1U_0402_16V4Z R61 0_0402_5% 1 C201 2 XTALO 1 R1686 L75 8121@ 4.7UH_1008HC-472EJFS-A_5%_1008 +1.2_AVDDL +1.2_DVDDL C200 8131@ 1U_0402_6.3V4Z LAN_XTALI 2 Place Close to Pin816223639 C1066 and C1067 close to Pin8 8131@ Place Close to Pin 28324546 C1750 and C1730 close to Pin46 C1072 close to Pin45 1 R1685 0_0603_5% C1967 8121@ SA000025M00 S IC AR8121-AL1E QFN 48P E-LAN CTRL If not overclocking , R1685 & L75 stuffed and R1686 & R1862 removed 8131 If not overclocking , R1685 & R1862 stuffed and R1686 & L75 removed 1 2 C1995 27P_0402_50V8J Compal Secret Data Security Classification Issued Date 2008/11/24 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Title Compal Electronics, Inc. Size Document Number Custom Date: Atheros AR8131 KALH0/KALG0/KAL90+ Sheet Monday, April 27, 2009 D 32 of Rev 1.0 53 4 3 1 +3V_LAN T40 LAN_MIDI1+ L_LAN_MIDI1+ L_LAN_MIDI1- LAN_MIDI1- L_LAN_MIDI2+ L_LAN_MIDI2- <32> LAN_MIDI2+ LAN_MIDI2+ LAN_MIDI2- L_LAN_MIDI3+ L_LAN_MIDI3- <32> LAN_MIDI2- 24 23 22 21 20 19 18 17 16 15 14 13 2 2 2 1 2 L_LAN_ACTIVITY# D RJ45_MIDI1+ RJ45_MIDI1RJ45_MIDI2+ RJ45_MIDI2- 8121@ 1 2 R64 0_0402_5% pull down circuit : more power saving in no-overclocking mode RJ45_MIDI3+ RJ45_MIDI3- 2 1 75_0402_1% R1710 2 1 75_0402_1% R1711 1 75_0402_1% R1712 1 75_0402_1% R1713 1 8131@ 2 R62 0_0402_5% L_LAN_ACTIVITY# 2 1 R1863 8131@ 510_0402_5% <32> LAN_ACTIVITY# 5.1K_0402_5% 2 1 1 2 8121@ 1 R1709 510_0402_5% R1864 8131@ 2 1 2 RJ45_MIDI0+ RJ45_MIDI0- 2 C 1 +AVDD_CEN 0.1U_0402_16V4Z <32> +AVDD_CEN C2006 LAN_MIDI3- C2005 <32> LAN_MIDI3- MCT1 MX1+ MX1MCT2 MX2+ MX2MCT3 MX3+ MX3MCT4 MX4+ MX4- 8121@ 0.1U_0402_16V4Z LAN_MIDI3+ 0.1U_0402_16V4Z <32> LAN_MIDI3+ TCT1 TD1+ TD1TCT2 TD2+ TD2TCT3 TD3+ TD3TCT4 TD4+ TD4- 350uH_GSL5009-1 LF C2003 <32> LAN_MIDI1- 1 2 3 4 5 6 7 8 9 10 11 12 C2004 <32> LAN_MIDI1+ L_LAN_MIDI0+ L_LAN_MIDI0- 0.1U_0402_16V4Z <32> LAN_MIDI0+ <32> LAN_MIDI0- LAN_MIDI0+ LAN_MIDI0- 1 C2002 8121@ 220P_0402_50V7K LAN AR8121/8112 D www.bufanxiu.com 2 220P_0402_50V7K 5 2 1 C2170 8131@ RJ45_GND 40mil 12 11 RJ45_MIDI3- 8 RJ45_MIDI3+ 7 RJ45_MIDI1- 6 RJ45_MIDI2- 5 RJ45_MIDI2+ 4 RJ45_MIDI1+ 3 RJ45_MIDI0- 2 RJ45_MIDI0+ 1 L_LAN_LINK# <32> LAN_LINK# 2 R1714 +3V_LAN Place close to TCT pin 10 1 510_0402_5% 9 1 JPJ1 Yellow LEDYellow LED+ Guide Pin PR4PR4+ PR2PR3PR3+ PR2+ PR1- SHLD2 PR1+ SHLD1 Green LED- 14 C 13 Green LED+ SUYIN_100073FR012G101ZL CONN@ 2 C2007 220P_0402_50V7K RJ45_GND 1 2 C2008 1000P_1206_2KV7K LANGND 1 1 2 C2009 2 40mil C2010 4.7U_0805_10V4Z 0.1U_0402_16V4Z B B L_LAN_ACTIVITY# 1 2 C2011 @ 68P_0402_50V8J L_LAN_LINK# 1 2 C2012 @ 68P_0402_50V8J For EMI A A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Size B Date: Compal Electronics, Inc. LAN Magnetic & RJ45 Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 33 Rev 1.0 of 53 A B C www.bufanxiu.com D E For Robson2 +1.5VS 1 +3VS C2013 1 4.7U_0805_10V4Z 2 KAL90_90+@ 2 C2014 0.1U_0402_16V4Z KAL90_90+@ 1 2 1 C2015 0.1U_0402_16V4Z KAL90_90+@ 2 C2016 4.7U_0805_10V4Z KAL90_90+@ 1 2 Mini Card Power Rating C2017 0.1U_0402_16V4Z KAL90_90+@ Power 1 JMINI1 1 3 5 7 9 11 13 15 <16> MINI1_CLKREQ# <16> CLK_PCIE_MINI1# <16> CLK_PCIE_MINI1 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 <27> PCIE_PTX_C_IRX_N4 <27> PCIE_PTX_C_IRX_P4 <27> PCIE_ITX_C_PRX_N4 <27> PCIE_ITX_C_PRX_P4 +3VS For MINICARD Port80 Debug <36> E51TXD_P80DATA <36> E51RXD_P80CLK E51TXD_P80DATA E51RXD_P80CLK R1717 1 2 0_0402_5% CL_RST#1_R KAL90_90+@ 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 +3VS +1.5VS 53 54 55 56 Auxiliary Power (mA) Peak Normal +3VS 1000 750 +3V 330 250 250 (wake enable) +1.5VS 500 375 5 (Not wake enable) Normal 1 USB CONN. 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 PLT_RST_BUF# PLT_RST_BUF# <25> +USB_VCCA MINI1_SMBCLK MINI1_SMBDATA R1715 1 R1716 1 2 0_0402_5% ICH_SMBCLK 2 0_0402_5% ICH_SMBDATA @ @ W=80mils +USB_VCCA ICH_SMBCLK <16,27,32,35> ICH_SMBDATA <16,27,32,35> 1 1 C2018 C2019 150U_B2_6.3VM_R35M @ 470P_0402_50V7K 2 + USB20_N10 <27> USB20_P10 <27> 2 (LED_WWAN#) (LED_WLAN#) JUSB1 <27> <27> G1 G2 G3 G3 2 2 4 6 8 10 12 14 16 Primary Power (mA) 1 2 3 4 USB20_N6 USB20_P6 USB20_N6 USB20_P6 FOX_AS0B226-S99N-7F CONN@ 5 6 7 8 4 USB20_N6 VIN GND1 GND2 GND3 GND4 IO1 IO2 GND 2 USB20_P6 1 PRTR5V0U2X_SOT143-4 KAL90_90+@ For Wireless LAN +3VS_WLAN 3 2 SUYIN_020173MR004G565ZR CONN@ D62 +USB_VCCA VCC DD+ GND +USB_VCCA +1.5VS COAL LAY JP17 +3VS_WLAN R1718 1 R1719 1 @ 2 0_1206_5% +3VS 2 0_1206_5% +3V 1 2 1 C2020 4.7U_0805_10V4Z 2 1 C2021 0.1U_0402_16V4Z 2 1 C2022 0.1U_0402_16V4Z 3 R1720 1 @ 2 0_0402_5% WLAN_BT_DATA <27,35> ICH_PCIE_WAKE# <35> WLAN_BT_DATA <35> WLAN_BT_CLK <16> MINI2_CLKREQ# WLAN_BT_CLK <16> CLK_PCIE_MINI2# <16> CLK_PCIE_MINI2 <27> PCIE_PTX_C_IRX_N2 <27> PCIE_PTX_C_IRX_P2 <27> PCIE_ITX_C_PRX_N2 <27> PCIE_ITX_C_PRX_P2 +3VS_WLAN For MINICARD Port80 Debug R1725 1 2 0_0402_5% CL_RST#2_R 4.7U_0805_10V4Z 2 1 C2024 0.1U_0402_16V4Z 2 C2025 JUSB2 0.1U_0402_16V4Z JMINI2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 (WAKE#) 1 3 5 7 9 11 13 15 2 4 6 8 10 12 14 16 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 53 54 55 56 4 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 5 6 7 8 +3VS_WLAN +1.5VS WL_OFF# PLT_RST_BUF# +3V_WLAN R1721 1 R1722 1 3 GND1 GND2 GND3 GND4 MINI2_SMBCLK R1723 1 MINI2_SMBDATA R1724 1 WL_OFF# <36> 2 0_0603_5% 2 0_0603_5% @ +3VS +3V To USB/B Connector 2 0_0402_5% ICH_SMBCLK 2 0_0402_5% ICH_SMBDATA @ @ USB20_N11 <27> USB20_P11 <27> (LED_WWAN#) (LED_WLAN#) MINI1_LED# 80mil JP15 1 2 3 4 5 6 7 8 GND GND <37> (9~16mA) FOX_AS0B226-S99N-7F 1 2 3 4 5 6 7 8 9 10 +5VALW +5VALW SYSON# USB20_N0 USB20_P0 <35,42> C2026 USB20_N0 <27> USB20_P0 <27> 1 4.7U_0805_10V4Z 2 USB_OC#0 <27> 4 ACES_85201-08051 CONN@ Compal Secret Data Security Classification 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B VCC DD+ GND SUYIN_020173MR004G565ZR CONN@ CONN@ A 1 2 3 4 USB20_N1 USB20_P1 <27,35> USB20_N1 <27,35> USB20_P1 G1 G2 G3 G3 E51TXD_P80DATA E51RXD_P80CLK 2 1 C2023 C D Title Size B Date: Compal Electronics, Inc. MINI CARD (WLAN & Robson2) Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet 34 of 53 Rev 1.0 A B C www.bufanxiu.com D E New Card Power Switch STBY# 7 GND G577NSR91U_TQFN20_4x4 +3VS 5 CLKREQ1# 2 2 KAL90_H0_90+@ D S B A NC7SZ32P5X_NL_SC70-5 Q118 2N7002_SOT23 KAL90_H0_90+@ RCLKEN1 2 G +1.5VS +3V 1 2 C2032 1 2 JEXP1 0.1U_0402_16V4Z KAL90_H0_90+@ 1 R1726 10K_0402_5% KAL90_H0_90+@ 10U_0805_10V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z +3VS RCLKEN 2 +3VS 21 Thermal_Pad C2031 1 CPUSB# 2 Imax = 0.75A 1 KAL90_H0_90+@ 16 NC CPPE# PERST1# 8 PERST# 2 1 G Vcc 1 CP_PE# 10 (Internal Pull High to AUXIN) CP_USB# 9 (Internal Pull High to AUXIN) RCLKEN1 18 19 OC# SHDN# 2 C2030 KAL90_H0_90+@ SUSP# SYSRST# 2 KAL90_H0_90+@ 20 +3VALW_CARD C2029 1 <27> <27> PERST1# +3VS_CARD C2033 KAL90_H0_90+@ 0.1U_0402_16V4Z 4 CLKREQ1# CP_PE# <27> CP_PE# <16> CLK_PCIE_CARD# <16> CLK_PCIE_CARD <27> PCIE_PTX_C_IRX_N1 <27> PCIE_PTX_C_IRX_P1 EXP_CLKREQ# <16> KAL90_H0_90+@ <27> PCIE_ITX_C_PRX_N1 <27> PCIE_ITX_C_PRX_P1 GND USB_DUSB_D+ CPUSB# RSV RSV SMB_CLK SMB_DATA +1.5V +1.5V WAKE# +3.3VAUX PERST# +3.3V +3.3V CLKREQ# CPPE# REFCLKREFCLK+ GND PERn0 PERp0 GND PETn0 PETp0 GND 27 28 GND GND 1 GND GND 29 30 SANTA_131851-A_LT CONN@ 1 1 1 C2034 C2035 C2036 KAL90_H0_90+@ KAL90_H0_90+@ KAL90_H0_90+@ 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 2 2 2 2 +3V +3VS 2 6 5 4 3 2 1 2 KAL90_G0_90+@ C2037 0.1U_0402_16V4Z 2 1 USB20_N9 USB20_P9 3 <27> USB20_N9 <27> USB20_P9 2 R578 0_0603_5% KAL90_G0_90+@ 2 R577 0_0603_5% @ D44 SM05T1G_SOT23-3 Bluetooth Conn. Finger Print Conn. ESATA CONN JP16 G2 G1 4 3 2 1 +USB_VCCA ACES_85201-04051 CONN@ W=60mils 1 @ C2038 + 150U_Y_6.3VM @ 2 1 +3VALW CP_USB# <27,34> ICH_PCIE_WAKE# +3VALW_CARD U53 Y USB20_N5 USB20_P5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 <16,27,32,34> ICH_SMBCLK <16,27,32,34> ICH_SMBDATA +1.5VS_CARD 3 <36,38,42,51> SUSP# 6 SYSON 40mil 15 AUX_OUT C2028 +1.5VS_CARD Imax = 1.35A 0.1U_0402_16V4Z PCI_RST# PCI_RST# <36,42,48> SYSON AUX_IN C2027 +3VS_CARD 1 1 17 60mils 3 5 3.3Vout 3.3Vout 1 1 +3V 3.3Vin 3.3Vin Imax = 0.275A +1.5VS_CARD 3 2 4 +3VS_CARD 1 <25> +3VS 11 13 1.5Vout 1.5Vout 10U_0805_10V4Z 1 1.5Vin 1.5Vin New Card Socket (Left/TOP) +3VALW_CARD KAL90_H0_90+@ 12 14 +1.5VS 40mil KAL90_H0_90+@ U52 +3VS 1000P_0402_50V7K 1 1 C2039 C2040 2 0.1U_0402_16V4Z 2 JP17 1 1 2 10K_0402_5% 2 1 USB20_N1 3 VIN IO1 1 IO2 GND PRTR5V0U2X_SOT143-4 KAL90_90+@ Q119 AO3413_SOT23-3 W=40mils 0.1U_0402_16V4Z 2 +USB_VCCA 1U_0603_10V4Z SATA_ITX_C_DRX_P5 SATA_ITX_C_DRX_N5 <26> SATA_ITX_C_DRX_P5 <26> SATA_ITX_C_DRX_N5 C2044 2 C2045 2 <26> SATA_DTX_C_IRX_N5 <26> SATA_DTX_C_IRX_P5 +BT_VCC 1 1 C2047 R1728 4.7U_0805_10V4Z 300_0603_5% 2 2 0.1U_0402_16V4Z 1 D SATA_ITX_C_DRX_N5 Q120 2N7002_SOT23 3 2 G VIN 3 IO1 IO2 GND 4 3 12 13 14 15 1 PRTR5V0U2X_SOT143-4 KAL90_90+@ S +3V JP18 1 2 3 4 5 6 7 8 1 GND 2 3 4 5 6 7 8 GND 80mil +5VALW 9 +USB_VCCA U54 1 2 3 4 D61 4 +5VALW SATA_IRX_DTX_P5 10 3 VIN IO1 IO2 GND 2 SATA_IRX_DTX_N5 C2048 1 PRTR5V0U2X_SOT143-4 KAL90_90+@ ACES_87213-0800G CONN@ 1 4.7U_0805_10V4Z 2 GND IN IN EN# OUT OUT OUT FLG R1730 0_0402_5% 1 2 R1729 100K_0402_5% 8 7 6 5 2 R1754 10_0402_5%2 @ 1 2 R1768 0_0402_5% @ GND A+ ESATA AGND SHIELD BSHIELD B+ SHIELD GND SHIELD SATA_ITX_C_DRX_P5 2 +BT_VCC <34> WLAN_BT_DATA <34> WLAN_BT_CLK 5 6 7 8 9 10 11 USB D60 4 +5VALW USB20_P8 USB20_N8 SATA_IRX_DTX_N5 SATA_IRX_DTX_P5 0.01U_0402_25V7K 0.01U_0402_25V7K 1 1 VBUS DD+ GND TYCO_1909574-1 CONN@ 2 C2046 <27> <27> 1 2 3 4 USB20_N1 USB20_P1 <27,34> USB20_N1 <27,34> USB20_P1 USB20_P1 2 1 C2043 2 4 1 1 R1727 1 BT_ON# D59 C2042 G <36> D 3 3 0.1U_0402_16V4Z 2 S C2041 TPS2061DRG4_SO8 1 2 R1731 10K_0402_5% USB_OC#1 <27> USB_OC#6 <27> 1 2 4 C2049 0.1U_0402_16V4Z <34,42> SYSON# Compal Secret Data Security Classification 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Size B Date: Compal Electronics, Inc. NEW CARD & eSATA Connector Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet 35 of 53 Rev 1.0 4 3 C2056 1000P_0402_50V7K C2051 2 <38> 1 RCIRRX D45 2 EC_RCIRRX CH751H-40PT_SOD323-2 +5VS 2 TP_CLK 4.7K_0402_5% 2 TP_DATA 4.7K_0402_5% 1 R1741 1 R1743 <37,45> <37,45> <4,18,37> <4,18,37> +3VALW B 2 EC_SMB_CK1 4.7K_0402_5% 2 EC_SMB_DA1 4.7K_0402_5% 1 R1745 1 R1746 R1769 2 @ 1 R1747 <27> PM_SLP_S3# <27> PM_SLP_S5# <27> EC_SMI# <37> LID_SW# 1 EC_I2C_INT2 10K_0402_5% 2 LID_SW# 100K_0402_5% <32> EC_PME# <8> MCH_TSATN_EC# <41> FAN_SPEED1 <35> BT_ON# <38> ON/OFF <43> PWR_SUSP_LED <37,43> NUM_LED# +3VS EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# EC_GPIOB EC_GPIOC EC_PME# FAN_SPEED1 BT_ON# E51TXD_P80DATA E51RXD_P80CLK ON/OFF PWR_SUSP_LED NUM_LED# 6 14 15 16 17 18 19 25 28 29 30 31 32 34 36 EC_CRY1 EC_CRY2 122 123 2 EC_SMB_CK2 2.2K_0402_5% 2 EC_SMB_DA2 2.2K_0402_5% <37> EC_ESB_CK <37> EC_ESB_DA SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F PS2 Interface SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 SPI Device Interface SPI Flash ROM SM Bus PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A 1 R1750 1 R1751 1 R1752 1 R1753 2 @ 4.7K_0402_5% 2 @ 4.7K_0402_5% 2 @ 0_0402_5% 2 @ 0_0402_5% SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 GPIO EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 GPO ICH_PWROK/GPXO06 BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 GPI XCLK1 XCLK0 PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 V18R 11 24 35 94 113 +3VS A 77 78 79 80 KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int. K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 GND GND GND GND GND 1 R1748 1 R1749 EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F DA Output 63 64 65 66 75 76 BATT_TEMP BATT_OVP 68 70 71 72 DAC_BRIG EN_DFAN1 IREF 83 84 85 86 87 88 EC_MUTE EC_I2C_INT2 97 98 99 109 3S/4S# 65W/90W# SBPWR_EN ID_JAL90_JAW50# 119 120 126 128 EC_SPIDI/FWR# EC_SPIDO/FRD# EC_SPICLK EC_SPICS#/FSEL# 73 74 89 90 91 92 93 95 121 127 100 101 102 103 104 105 106 107 108 110 112 114 115 116 117 118 INVT_PWM <22> BEEP# <39> PAD T41 @ ACOFF <47>ECAGND 2 1 C2059 0.01U_0402_16V7K BATT_OVP <47> ADP_I <47> AD_BID0 1 R1734 2 4.7K_0402_5% PAD T48 @ PAD T42 @ +3VALW ID_JAL90_JAW50# 2 R1737 @ 2 R1738 @ 100K_0402_5% DAC_BRIG <22> EN_DFAN1 <41> IREF <47> CALIBRATE# <47> EC_MUTE <40> EC_I2C_INT2 <38> PGD_IN <50> BT_LED# <37> TP_CLK <37> TP_DATA <37> TP_CLK TP_DATA 65W/90W# 2 R1740 3S/4S# <47> 65W/90W# <47> SBPWR_EN <42,48> EC_LID_OUT# EC_ON EC_PWROK BKOFF# WL_OFF# ON_0FF_TP LED# BATTERY_LED# Rb 2 AD_BID0 R1744 1 8.2K_0402_5% C2061 C2060 0.1U_0402_16V4Z 2 B EC_CRY1 EC_CRY2 1 1 15P_0402_50V8J 2 PM_SLP_S4# <27> ENBKL <10,18> EAPD <39> EC_THERM# <27> SUSP# <35,38,42,51> PBTN_OUT# <27> MC_RST# <37> SUSP# PBTN_OUT# MC_RST# 1 R1742 100K_0402_5% Ra ENBKL EAPD 1 100K_0402_5% +3VALW ON_0FF_TP SW# <37> FSTCHG <47> BATT_RED_LED# <37> CAPS_LED# <43> BATT_Yellow Green_LED# <37> PWR_LED <43> SYSON <35,42,48> VR_ON <38,50> ACIN <27,42,43,44,47> EC_RSMRST# <27> EC_LID_OUT# <27> EC_ON <38> EC_SWI# <27> EC_PWROK <27,38> BKOFF# <22> WL_OFF# <34> ON_0FF_TP LED# <37> BATTERY_LED# <37> C Analog Board ID definition, Please see page 3. EC_SI_SPI_SO <37> EC_SO_SPI_SI <37> EC_SPICLK <37> EC_SPICS#/FSEL# <37> EC_RCIRRX ON_0FF_TP SW# FSTCHG BATT_RED_LED# CAPS_LED# BATT_Yellow Green_LED# PWR_LED SYSON VR_ON ACIN 1 100K_0402_5% 1 +3VALW C2062 15P_0402_50V8J 2 X2 32.768KHZ_12.5P_MC-306 124 KB926QFC0_LQFP128_14X14 For KB926 C0 reversion C2063 1U_0402_6.3V6K C2064 BATT_TEMP 2 C2065 BATT_OVP 2 C2066 ACIN 2 20mil L74 ECAGND 2 1 FBM-L11-160808-800LMT_0603 100P_0402_50V8J 1 100P_0402_50V8J 1 100P_0402_50V8J 1 A EC_GPIOB EC_GPIOC Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 3S/4S# BATT_TEMP <45> 4 1 1 R1739 10K_0402_5% R1840 47K_0402_5% 1 2 R1841 47K_0402_5% 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 INVT_PWM BEEP# 1 2 C 2 +3VALW +3VALW +3VALW KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 AD PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A Input AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 21 23 26 27 IN EC_SCI# <27> EC_SCI# <27> PM_CLKRUN# 2 1 R1736 47K_0402_5% 2 1 C2058 0.1U_0402_16V4Z PWM Output MISC 69 +3VALW 12 13 37 20 38 <8,17,25,27,31,32> PLT_RST# INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 OUT <16> CLK_PCI_LPC LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 D NC 1 ACES_85205-0400 @ 1 10K_0402_5% NC @ GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & 2 3 R1735 2 1 2 3 4 5 7 8 10 AGND C2057 @ 22P_0402_50V8J 2 1 <26> EC_GA20 <26> EC_KBRST# <27> SERIRQ <26> LPC_FRAME# <26> LPC_AD3 <26> LPC_AD2 33_0402_5% <26> LPC_AD1 <26> LPC_AD0 R1733 E51RXD_P80CLK <34> E51TXD_P80DATA <34> AVCC VCC VCC VCC VCC VCC VCC U55 ENBKL Place on RAM door E51RXD_P80CLK E51TXD_P80DATA 67 9 22 33 96 111 125 D 9/21 add R for nvidia 0.1U_0402_16V4Z 1 2 3 4 1 2 3 4 2 2 2 0.1U_0402_16V4Z C2055 1000P_0402_50V7K 1 1 +3VALW JP19 1 2 C2054 <37> KSO[0..17] <37> 1 2 2 0.1U_0402_16V4Z EC_PME# 2 10K_0402_5% 1 R1732 C2050 KSI[0..7] KSO[0..17] ECAGND +3VALW KSI[0..7] L73 1 2 +EC_VCCA 2 FBM-L11-160808-800LMT_0603 0.1U_0402_16V4Z 1 2 1 For EC Tools 1 0.1U_0402_16V4Z 1 1 C2053 1 C2052 www.bufanxiu.com 2 +3VALW 2 5 4 3 2 Title Size B Date: Compal Electronics, Inc. Document Number EC ENE KB926 KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 Rev 1.0 36 of 53 www.bufanxiu.com +3VALW 1 C2067 1 2 R1757 0_0603_5% EC_SPICS#/FSEL# SPI_WP# SPI_HOLD# 2 0.1U_0402_16V4Z +SPI_VCC <36> EC_SPICS#/FSEL# EC_SPICS#/FSEL# R1758 1 R1760 1 +3VALW 1 3 7 4 2 4.7K_0402_5% SPI_WP# 2 4.7K_0402_5% SPI_HOLD# U57 CE# WP# HOLD# VSS VDD SCK SI SO 1 3 7 4 To TP/B Conn. U56 CS# WP# HOLD# GND +SPI_VCC EC_SPICLK_R EC_SO_SPI_SI EC_SI_SPI_SO 8 6 5 2 VCC SCLK SI SO <36> <36> +5VS TP_CLK TP_DATA MX25L512AMC-12G_SO8 8 6 5 2 EC_SPICLK_R R1759 1 R1761 1 R1762 1 2 0_0402_5% 2 0_0402_5% 2 0_0402_5% Reserved for BIOS simulator. @ Footprint SO8 EC_SPICLK <36> EC_SO_SPI_SI <36> EC_SI_SPI_SO <36> C2068 100P_0402_50V8J +3VS 1 1 2 2 C2069 100P_0402_50V8J JP21 6 5 4 3 2 1 8 7 8 7 KALH0 TP SW ACES_85201-0605 LEFT_BTN# 3 CONN@ SW4 KALH0@ SMT1-05-A_4P 4 1 RIGHT_BTN# 3 2 4 SW5 KALH0@ SMT1-05-A_4P 1 2 KSI[0..7] KSO[0..17] (Right) (Right) 100P_0402_50V8J KSO14 C2075 1 2 100P_0402_50V8J KSO13 C2077 1 2 100P_0402_50V8J KSO12 C2080 1 2 100P_0402_50V8J KSI0 C2081 1 2 100P_0402_50V8J KSO11 C2083 1 2 100P_0402_50V8J KSO10 C2085 1 2 100P_0402_50V8J KSI1 C2087 1 2 100P_0402_50V8J LEFT_BTN# 4 <4,18,36> EC_SMB_CK2 <4,18,36> EC_SMB_DA2 R1846 R1847 <36> EC_ESB_CK G1 G2 <36> 2 2 0_0402_5% 0_0402_5% kAL90_90+@ R1766 1 2 0_0402_5% MEDIA_CK 1 kAL90_90+@ 2 0_0402_5% MC_RST# MC_RST# 1 0_0402_5% 1@ 1 @ R1765 <36,45> EC_SMB_DA1 <38> EC_I2C_INT1 ACES_85201-26051 CONN@ 0_0402_5% 1 KALH0@ 2 R1764 <36,45> EC_SMB_CK1 27 28 R105 0_0603_5% 1 KALH0@ 2 R1763 <36> EC_ESB_DA 1 To Media/B Conn. KSO16 C2071 1 2 100P_0402_50V8J KSO17 C2072 1 2 100P_0402_50V8J KSO7 C2074 1 2 100P_0402_50V8J KSO6 C2076 1 2 100P_0402_50V8J KSO5 C2079 1 2 100P_0402_50V8J KSO4 C2078 1 2 100P_0402_50V8J KSO3 C2082 1 2 100P_0402_50V8J KSI4 C2084 1 2 100P_0402_50V8J KSO2 C2086 1 2 100P_0402_50V8J 100P_0402_50V8J KSO9 C2091 1 2 100P_0402_50V8J KSO1 C2088 1 2 100P_0402_50V8J KSI3 C2094 1 2 100P_0402_50V8J KSO0 C2090 1 2 100P_0402_50V8J KSO8 C2097 1 2 100P_0402_50V8J KSI5 C2092 1 2 100P_0402_50V8J KSI6 C2095 1 2 100P_0402_50V8J KSI7 C2098 1 2 100P_0402_50V8J 1 C2093 @ 0.1U_0402_16V4Z MEDIA_DA MC_RST+# 2 @ R1790 0_0402_5% R1808 10K_0402_5% @ 1 2 3 4 5 6 7 8 9 10 kAL90_90+@ FB_KSI4 R1834 R1835 1 2 1 2 0_0402_5% R1832 R1833 1 1 NUM_LED# 2 0_0402_5% <36,43> KSI3 2 MEDIA_LED# KALH0@ 0_0402_5% <43> 1 2 3 4 5 6 7 8 9 10 GND GND WL_BTN# KSI2 BT_BTN# KSI3 EMAIL_BTN# KSI4 IE_BTN# KSI5 E-KEY_BTN# 1 2 3 4 5 6 7 8 GND GND 2 866_0402_1% 4 KALG0@ +5VALW +5VALW 1 KALG0@ R1774 LED2 2 330_0402_5% 1 R1775 2 866_0402_1% KALG0@ A 3PWR_SUSP_LED# HT-297UD/CB _BLUE/AMB_0603 2 4 YG A PWR_SUSP_LED# 2 <43> C2103 footpint not right 0.1U_0402_16V4Z 1 OUTPUT Blue 1 3 BATT_RED_LED# BATT_Yellow Green_LED# AMB HT-297DQ-GQ_AMB-YG kAL90_90+@ 5 6 +5VS +3VS MINI1_LED# BT_LED# <34> <36> ACES_85201-1005N CONN@ 1 2 3 4 5 6 7 8 9 10 +5VS +3VS MINI1_LED# FB_KSI4 BT_LED# FB_KSI3 MINI1_LED# BT_LED# <34> <36> FOR EMI BATT_RED_LED# KSI5 U58 A3212ELHLT-T_SOT23W-3 <36> BATT_Yellow Green_LED# R1770 10K_0402_5% 1 1 R1773 MINI1_LED# KSI1 FB_KSI4 KSO0 KSI2 BT_LED# FB_KSI3 JP28 +3VS 1 R1771 47K_0402_5% 3 2 +5VALW <36> 1 2 3 4 5 6 7 8 9 10 11 12 KALH0 KSI1 <43> 2 1 PWR_LED# BATTERY_LED# 1 2 3 4 5 6 7 8 9 10 GND GND Lid Switch VDD 3 PWR_LED# +5VS KSO4 KSO2 KSO3 KSI5 KSI6 BATTERY_LED# BT_LED# MINI1_LED# ACES_85201-1005N CONN@ +3VALW 1 KAL90 JP26 1 2 3 4 5 6 7 8 9 10 11 12 CONN@ ACES_85201-08051 GND 2 B 2 KSO0 KALH0@ 0_0402_5% kAL90_90+@ FB_KSI3 FN/B KALG0 JP29 ACES_85201-08051 CONN@ KSI4 1 D48 1 1 4 330_0402_5% 2 1 4 KAL90_G0_90+@ 5 6 1 2 3 4 5 6 7 8 GND GND To BTN/B Conn. LED1 2 2 SW2 SMT1-05-A_4P JP22 (Hall Effect Switch) 1 R1772 RIGHT_BTN# 3 kAL90_90+@ 0_0603_5% R109 INT_KBD 2 +5VALW 1 KALG0 C2089 1 KALG0@ 3 +5VS +3VS MCVCC KSI2 Compal Footprint 3 2 KAL90 TP SW SW1 SMT1-05-A_4P KAL90_G0_90+@ 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 1 2 3 4 CONN@ +3VALW C2073 1 D46 @ PSOT24C_SOT23 0.1U_0402_16V4Z JP25 E&T_6905-E04N-00R <36> 2 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 27 28 ACES_85201-26051 CONN@ KSO15 1 2 3 4 TP_DATA C2070 JP30 (Left) G1 G2 e-key/B <36> KSO0 KSI5 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ON_0FF_TP LED# KALH0@ 0_0603_5% R106 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 HT-121UD_AMBER R1861 2ON_0FF_TP LED# 1.5K 0402 5% KALG0@ 2 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 1 <36> KSO[0..17] JP23 (Left) 1 5 6 KSI[0..7] INT_KBD Conn. +5VS KALG0@ 5 6 KALG0@ 2 2 1 4 TP_CLK LED13 2 <36> ON_0FF_TP SW# ENE suggestion SPI Frequency over 66MHz SST: 50MHz MXIC: 70MHz ST: 40MHz +5VS R1860 SW6 47K_0402_5% KALG0@ SMT1-05-A_4P ON_0FF_TP SW# 3 1 5 6 1 MX25L8005M2C-15G_SOP8 6 5 4 3 2 1 TP_CLK TP_DATA LEFT_BTN# RIGHT_BTN# 2 LID_SW# RB751V_SOD323 2 LID_SW# <36> C2111 10P_0402_50V8J <36> 2 MINI1_LED# C2099 1 BT_LED# C2100 1 KSO0 C2104 1 KSI1 C2106 1 KSI2 C2108 1 KSI3 C2110 1 KSI4 C2113 1 @ @ @ @ @ @ @ @ 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J 2 100P_0402_50V8J Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date @ C2101 1 2008/11/24 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size C Date: BIOS, I/O Port & K/B Connector Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 37 of 53 Rev 1.0 A B C www.bufanxiu.com D E Power Button ON/OFF switch HDA MDC Conn. TOP Side 10K_0603_5% 2 @ R1780 10K_0603_5% D49 ON/OFFBTN# <43> ON/OFFBTN# 2 1 ON/OFF <36> 51ON# <44> 51ON# 3 1 3 5 7 9 11 <26> HDA_SDOUT_MDC 100K_0402_5% Bottom Side 15mil JMDC1 2 @ <26> HDA_SYNC_MDC <26> HDA_SDIN1 <26> HDA_RST_MDC# R1781 1 HDA_SDIN1_MDC 33_0402_5% 2 1 3 5 7 9 11 2 4 6 8 10 12 2 4 6 8 10 12 +MDC_VCC HDA_BITCLK_MDC 1 1 1 R1836 kAL90_90+@ 510K_0402_5% R1783 <37> EC_I2C_INT1 1 2 1 Q122 2 G D S 2N7002_SOT23 <26> D S 2N7002_SOT23 C2115 22P_0402_50V8J For EMI Q124 kAL90_90+@ 2 G 3 S 2N7002_SOT23 1 1 D 3 EC_ON EC_ON 2 <36> 10K_0402_5% 10K_0402_5% 2 R1838 kAL90_90+@ R1845 KALH0@ 1 2 RLZ20A_LL34 2 1000P_0402_50V7K 1 MCVCC +3VS 2 3 D50 1 1U_0603_10V4Z 2 MCVCC C2116 C2114 R1782 0_0402_5% DAN202UT106_SC70-3 2 2 +3V ACES_88018-124N CONN@ 51ON# 1 1 PM@ 2 +3V R1776 0_0402_5% 1 2 +1.5V R1778 0_0402_5% GM@ 1 R1779 1 +3V +3VALW 2 1 R1777 1 1 Q138 kAL90_90+@ 2 G 1 10K_0402_5% 2 2 2 +3VALW Power ON Circuit R1837 D47 +3VALW 1 10K_0402_5% @ 2 EC_I2C_INT2 <36> 1 +3VALW @ 1 +3VS 3 14 P 2 O I SYS_PWROK 4 O G I 1SS355_SOD323-2 U59B SN74LVC14APWLE_TSSOP14 R42 1 R1785 @ 2 0_0402_5% 1 2 0_0402_5% EC_PWROK <27,36> For South Bridge 7 2 C2117 1U_0603_10V6K @ 1 P 2 CH751H-40PT_SOD323-2 G VR_ON 2 7 <36,50> 14 R1784 @ 180K_0402_5% D51 @ 1 U59A SN74LVC14APWLE_TSSOP14 1 +3VS +3VALW O 8 1 VS_ON 3 R1789 100_0805_5% kAL90_90+@ <48,49> 2 14 P I G 14 P 9 For +VCCP/+1.05VS 3 1 1 1 C2119 4.7U_0805_10V4Z kAL90_90+@2 IR1 kAL90_90+@ 4 Vs OUT 2 GND GND TSOP36236TR_4P RCIRRX 1 RCIRRX +RTCBATT <36> C2121 1000P_0402_50V7K 2 kAL90_90+@ R1788 1K_0402_5% 1 1 S 6 U59D SN74LVC14APWLE_TSSOP14 2 C2118 0.1U_0402_16V7K O 7 2 G Q123 2N7002_SOT23 2 D SUSP I 7 SUSP 3 <42,49> 5 G R1787 10K_0402_1% 1 2 1 <35,36,42,51> SUSP# 2 3 U59C SN74LVC14APWLE_TSSOP14 CIR +3VALW 1 +3VALW R1786 @ 10K_0402_1% D52 2 3 +RTCVCC BAS40-04_SOT23-3 1 2 +CHGRTC C2122 0.1U_0402_16V4Z 4 4 Compal Secret Data Security Classification 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C D Title Size B Date: Compal Electronics, Inc. Power OK, Reset,RTC, CIR, MDC Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 38 of 53 A B C D E F www.bufanxiu.com G H +VDDA 1 +5VAMP R1528 10K_0402_5% C1833 1U_0402_6.3V6K R1529 10K_0402_5% 2SC2411K_SOT23 268@ 888VB@ 888VC@ HD Audio Codec D29 CH751H-40PT_SOD323-2 +AVDD_HDA 15 MIC2_C_L 1 2 C1845 KALH0@ 4.7U_0603_6.3V6M MIC2_C_R 1 2 C1846 KALH0@ 4.7U_0603_6.3V6M LINE_L LINE_C_L 1 2 C1847 4.7U_0603_6.3V6M LINE_R LINE_C_R 1 2 C1848 4.7U_0603_6.3V6M R49 1K_0402_5% 2 1 INT_MIC_R KALH0@ DMIC_CLK_R <40> LINE_L <40> LINE_R 16 17 23 24 18 20 19 <40> MIC1_L <40> MIC1_R MIC1_L MIC1_C_L 2 4.7U_0603_6.3V6M MIC1_C_R 2 4.7U_0603_6.3V6M MONO_IN 1 C1851 1 C1852 MIC1_R Sense Pin SENSE A 4 SENSE B Impedance HDA_GPIO0 HDA_GPIO3 SENSE_A 2 10K_0402_1% 1 20K_0402_1% R1545 2 1 39.2K_0402_1% <40> Codec Signals 39.2K PORT-A (PIN 39, 41) 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) 5.1K PORT-D (PIN 35, 36) 39.2K PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) SPDIF 5 <26> HDA_SDOUT_AUDIO R1543 1 R1544 2 <36> 100P_0402_50V8J 1 2 C1857 DMIC_DATA 1 2 KAL90_G0_90+@ 1 R1548 2 R1549 888VB@ 1 2 R1552 KALH0@ 2 3 13 34 47 EAPD 1 R1546 0_0402_5% 0_0402_5% 0_0402_5% <18> SPDIF_HDMI 12 10 <26> HDA_SYNC_AUDIO Place close to Codec 22 11 <26> HDA_RST_AUDIO# 3 21 2SPDIF_R 48 0_0402_5% 4 7 9 1 DVDD U41 DVDD_IO 2 38 2 14 <40> HP_PLUG# C1840 LINE2-L FRONT_L LINE2-R FRONT_R MIC2_L SURR_L MIC2_R SURR_R LINE1_L SIDE_L LINE1_R SIDE_R CD_L CENTER CD_R LFE CD_GND BITCLK MIC1_L MIC1_R SDATA_IN PCBEEP PIN37_VREFO LINE1_VREFO RESET# SYNC SDATA_OUT LINE2_VREFO MIC1_VREFO_L MIC1_VREFO_R SPDIFO2 GPIO0/DMIC_CLK MIC2_VREFO SENSE A SENSE B VREF SPDIFI/EAPD JDREF SPDIFO SENSE C GPIO1/DMIC_DATA DVSS AVSS1 AVSS2 1 C1843 L48 MBK1608121YZF_0603 1 2 GM@ +1.5VS B 35 AMP_LEFT 36 AMP_RIGHT 39 HP_LEFT 41 2 HP_RIGHT AMP_LEFT <40> HP_RIGHT DMIC_CLK_268 1 R1538 @ For EMI 43 44 1 R1539 2 1 0_0402_5% 2 T38 DMIC_CLK_R <40> DMIC_DATA_R R1537 KALH0@ 0_0603_5% @ DMIC_CLK 0_0402_5% HDA_BITCLK_AUDIO HDA_SDIN0_AUDIO 1 R1540 2 33_0402_5% HDA_SDIN0 29 10mil 28 Digital MIC +3VS MIC1_VREFO_R 30 MIC2_VREFO CODEC_VREF 27 40 33 26 42 D JP13 KAL90_90+@ DMIC_CLK R1541 DMIC_CLK_R 0_0603_5% DMIC_DATA DMIC_DATA_R R1542 0_0603_5% KAL90_G0_90+@ MIC1_VREFO_L 32 C1849 220P_0402_50V7K 2 KALH0@ <26> <26> 37 31 1 2 C1850 22P_0402_50V8J 6 8 15mil HP_LEFT <40> PAD 46 R1535 2.2K_0402_5% KALH0@ AMP_RIGHT <40> 45 1 1 C1855 C1856 0.1U_0402_16V4Z 10U_0805_10V4Z 2 2 R1547 20K_0402_1% 1 2 3 4 1 2 3 4 3 5 6 G1 G2 ACES_88266-04001 CONN@ D30 SM05T1G_SOT23-3 @ 1 For ESD 10/11 2 10mil HDA_GPIO0 0_0402_5% 2 C1854 220P_0402_50V8J 1 C1853 220P_0402_50V8J 1 R1550 2 0_0805_5% 1 R1551 2 0_0805_5% 1 R1553 2 0_0805_5% 1 R1554 2 0_0805_5% 1 R1555 2 0_0805_5% 1 R1556 2 0_0805_5% 0_0402_5% GND GNDA 2008/11/24 2009/12/31 Deciphered Date E F GND GNDA Compal Electronics, Inc. Compal Secret Data Security Classification C G1 G2 MIC2_VREFO THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A 1 2 ACES_88266-02001 CONN@ C1844 DMIC_DATA HDA_GPIO3 1888VB@ 2 R1559 0_0402_5% DMIC_CLK 1 2 R1560 FBMA-L10-160808-301LMT_0603 KAL90_G0_90+@ Issued Date 1 2 3 4 AGND DMIC_DATA 1 2 R1557 @ SPDIF_HDMI 1 2 R1558 888VC@ JP24 DMIC_DATA_R DMIC_CLK_R 0.1U_0402_16V4Z 10U_0805_10V4Z 2 2 ALC888S-VC_LQFP48_7x7 888VC@ DGND ANALOG MIC +3VS R1534 0_0603_5% PM@ +1.5VS_DVDD 1 AVDD1 2 0.1U_0402_16V4Z 1 C1842 25 1 C1841 10U_0805_10V4Z 10mil AVDD2 L49 1 2 FBM-L11-160808-800LMT_0603 +VDDA <40> LINEIN_PLUG# <40> MIC_PLUG# 1 C1839 0.1U_0402_16V4Z 2 2 10U_0805_10V4Z 40mil L47 MBK1608121YZF_0603 1 2 +3VS_DVDD 1 2 2 10mil 1 1U_0402_6.3V6K 1 2 R1531 1.3K_0402_1% 1 0.01U_0402_16V7K 2 R1533 10K_0402_5% 2 C1835 4.75V 4.7U_0805_10V4Z 2 R1532 560_0402_5% 1 C1834 2 1 E +VDDA 1 4 3 560_0402_5% BYP 1 2 1U_0402_6.3V6K Q103 2 B SHDN 1 SB_SPKR C 2 BOM Option ALC268 ALC888S-VB ALC888S-VC MONO_IN 1 <27> R1530 GND 40mil 5 G9191-475T1U_SOT23-5 2 1U_0402_6.3V6K C1838 1 C1836 1 2 1 1 3 2 3 OUT 2 1 C1837 1 BEEP# 1 <36> 2 IN 2 2 1 2 (output = 300 mA) U40 1 1 1 L46 1 C1831 C1832 2 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 2 0.1U_0402_16V4Z 2 1 1 60mil L45 1 2 KC FBM-L11-201209-221LMAT_0805 +5VS Title Size B Date: HD Audio Codec ALC888S-VC Document Number KALH0/KALG0/KAL90+ G Monday, April 27, 2009 Sheet 39 H of 53 Rev 1.0 4 C 2 1 C1873 S 3 1 1 2 0.01U_0402_16V7K 2 EC_MUTE G Q104 2N7002_SOT23 25 2 2 1 1 20 10 19 +5VAMP /SD CVSS BEEP VSS CP+ CP- GND PGND PGND CGND GND BIAS 15 HP_PLUG# 16 1 2 23 7 13 29 C1872 1U_0603_10V4Z R1572 100K_0402_5% R1573 100K_0402_5% Q105 AO3413_SOT23-3 2 SPDIF_PLUG# 2 C1874 APA2057A_TSSOP28 2.2U_0603_10V6K Q44B 2N7002DW-T/R7_SOT363-6 5 Q44A 2N7002DW-T/R7_SOT363-6 2 D33 PJDLC05_SOT23-3 +5VSPDIF 20mil Gain= 10dB 2 HP_PLUG# <39> 3 11 1 VDD HPOUT_R HPOUT_L For ESD 10/11 1 +5VAMP 1 EC_MUTE <36> 17 18 CONN@ 4 12 14 1 C1871 1U_0603_10V4Z 2 D R1574 100K_0402_1% 26 HP_R HP_L INR_H INL_H 5 6 C1875 R1575 56.2_0603_1% HPOUT_L 1 HPOUT_L_1 1 2 L51 HPOUT_R 1 HPOUT_R_1 1 2 L50 R1576 56.2_0603_1% 1 For ESD Protect S/PDIF Out JACK LINE Out/Headphone Out 1 VOL_AMP 39K_0402_5% 4 6 G1 G2 C1866 220P_0402_50V8K 1 2 C1867 1 220P_0402_50V8K 2 C1868 220P_0402_50V8K 2 2 2 D63 PJDLC05_SOT23-3 @ C1876 330P_0402_50V7K 330P_0402_50V7K 1 1 HPOUT_L_2 2 FBM-11-160808-700T_0603 HPOUT_R_2 2 FBM-11-160808-700T_0603 SPDIF_PLUG# <39> 5 4 7 8 10 SPDIF SPDIF +5VSPDIF 1 C1877 100P_0402_50V8J 2 JHP1 1 2 6 3 3 HP_RIGHT_R 39K_0402_5% HP_LEFT_R SPKL+ SPKL- 2 2 8 9 2 R1570 2 LOUT+ LOUT- HP EN 6 1 R1569 /AMP EN SPKR+ SPKR- 1 2 3 4 ACES_88266-04001 1 2 1 24 22 21 2 1 27 2 100K_0402_5% 28 VOL_AMP 2 1 2 100K_0402_5% R1568 1 ROUT+ ROUT- 1 R1571 43K_0402_1% HP_RIGHT_C 2 4.7U_0603_6.3V6M HP_LEFT_C 2 4.7U_0603_6.3V6M R1567 1 INR_A INL_A JP14 1 2 3 4 1 C1865 220P_0402_50V8K D31 SM05T1G_SOT23-3 @ D32 SM05T1G_SOT23-3 @ 2 <39> HP_LEFT 3 5 E SPK_L+ SPK_LSPK_R+ SPK_R- 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% 3 2.2K_0402_5% 2 2 2 2 3 1 HP_RIGHT 1 C1869 HP_LEFT 1 C1870 <39> HP_RIGHT U42 2 2 1 +5VAMP +5VAMP 2 AMP_RIGHT_C 1U_0402_6.3V6K 2 AMP_LEFT_C 1U_0402_6.3V6K 1 R1565 2.2K_0402_5% HPF Fc = 154Hz C1864 PVDD PVDD R1566 C1862 HVDD 1 AMP_LEFT_C-1 CVDD AMP_RIGHT_C-1 R1561 1 R1562 1 R1563 1 R1564 1 1 1 C1858 0.1U_0402_16V4Z 2 1 1 2 C1863 0.47U_0603_16V4Z <39> AMP_LEFT SPKL+ SPKLSPKR+ SPKR- D <39> AMP_RIGHT 20mil 1 C1859 C1860 0.1U_0402_16V4Z 2 2 4.7U_0805_10V4Z S C1861 0.47U_0603_16V4Z 1 2 W=40mil 1 1 www.bufanxiu.com Int. Speaker Conn. 3 +3VS D 2 +5VAMP 3 B G A 9 2 SINGA_2SJ-E373-T01 CONN@ <39> LINEIN_PLUG# 1 LINE-IN JACK <39> LINE_L 1 LINE_L_1 1 2 L53 KAL90_G0_90+@ FBM-11-160808-700T_06031 <39> MIC1_L 1 2 R1582 75_0603_1% 4 MIC JACK MIC1_L_1 1 2 L55 FBM-11-160808-700T_0603 1 C1880 220P_0402_50V7K 8 7 R1580 2.2K_0402_5% 5 4 MIC1_R_R 3 6 2 1 MIC1_L_R 1 C1881 2 JMIC1 MIC1_VREFO_R 2 1 MIC1_R R1579 2.2K_0402_5% L54 FBM-11-160808-700T_0603 MIC1_R_1 1 2 2 <39> (HDA Jack) <39> MIC_PLUG# MIC1_VREFO_L R1581 75_0603_1% 1 2 SINGA_2SJ-E351-S03 CONN@ C1879 220P_0402_50V7K 2 KAL90_G0_90+@ 2 3 For ESD I/O status: a. input/output mount 75 ohm b. input only mount 1K ohm C1878 220P_0402_50V7K KAL90_G0_90+@ LINE_L_R 3 3 6 2 1 1 KAL90_G0_90+@ 4 LINE_R_R 1 2 2 R1578 75_0603_1% LINEIN_PLUG# 5 3 LINE_R 3 2 <39> D64 PJDLC05_SOT23-3 KAL90_G0_90+@ KAL90_G0_90+@ R1577 L52 KAL90_G0_90+@ 75_0603_1% FBM-11-160808-700T_0603 LINE_R_1 1 1 2 2 JLINE1 8 7 SINGA_2SJ-E351-S01 CONN@ D65 2 PJDLC05_SOT23-3 4 (HDA Jack) 1 220P_0402_50V7K 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B Compal Electronics, Inc. Compal Secret Data Security Classification C D Title Size B Date: Amplifier & Audio Jack Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 40 E Rev 1.0 of 53 www.bufanxiu.com FAN1 Conn +5VS +5VS 10U_0805_10V4Z 2 1 C2124 1 H12 H_4P2 @ H7 H_3P2 H8 H_3P2 @ 1 1 @ 1 @ 1 1 H11 H_4P2 @ H6 H_3P2 @ H13 H_3P7N @ @ 1 1 H10 H_4P2 1 @ 1 H9 H_4P2 C2126 1000P_0402_50V7K 1 2 H5 H_3P2 @ 1 2 H4 H_3P2 @ 1 2 +3VS H3 H_3P2 @ BAS16_SOT23-3 C2125 10U_0805_10V4Z 1 2 2 @ H21 H_3P2 @ H22 H_3P2 @ H23 H_3P2 @ H_7P0 H25 H26 H_3P2 H_3P2 H_3P2 @ @ @ 1 H20 H_3P2 1 @ 1 H19 H_3P2 1 ACES_85205-03001 CONN@ @ 1 H18 H_3P2 1 @ 1 H17 H_3P2 1 2 3 1 C2127 1000P_0402_50V7K JP27 1 40mil +VCC_FAN1 <36> FAN_SPEED1 1 R1791 10K_0402_5% 1 H1 H_3P2 D54 1 APL5605KI-TRL SOP 8P 1 2 1 1 H34 H_5P5X4P3N @ @ FD4 @ 1 FD3 @ 1 FD2 @ 1 FD1 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 Compal Electronics, Inc. Compal Secret Data Security Classification Issued Date H33 H_10P0X6P0N @ 1 H29 H30 H_4P7X3P7N H_5P1X4P1N @ @ 1 0.1U_0402_16V4Z C60 D53 1SS355_SOD323-2 8 7 6 5 1 1 GND GND GND GND 2 <36> EN_DFAN1 VEN VIN VO VSET 1 U60 1 2 3 4 +VCC_FAN1 2 R41 1 300_0402_5% 2008/11/24 Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Title Size B Date: FAN & COVER LIGHT& Screw Hole Document Number KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet Rev 1.0 41 of 53 A B C SUSP 2 2 1 C2136 R1794 470_0603_5% SYSON# <34,35> SYSON# 6 10U_0805_10V4Z 2 2 1U_0603_10V4Z 1 1 Q39A SBPWR_EN# SBPWR_EN# R1797 100K_0402_5% 2N7002DW-T/R7_SOT363-6 C2138 0.1U_0603_25V7K 2 2N7002DW-T/R7_SOT363-6 R1848 100K_0402_5% @ 1 SUSP 0_0402_5% 2 R1402 <38,49> @ S C2149 C2150 10U_0805_10V4Z 2 2 10U_0805_10V4Z 1 3 1 2 2 4 3 1 1 C2146 2 C2145 1 10U_0805_10V4Z 2 2 1U_0603_10V4Z SI4800BDY-T1-E3_SO8 3 SI4856/AO4430 2 1 R1803 470_0603_5% 1 2 1 R1800 10K_0402_5% +1.5VS 5 6 7 8 2N7002DW-T/R7_SOT363-6 3 SI4856ADY_SO8 PM@ 1 PM@ R1802 1 2 470_0603_5% 1 1U_0603_10V4Z 1 2 3 4 PM@ C2144 S S S G PM@ C2143 2 +1.5V U65 D D D D 10U_0805_10V4Z 1 10U_0805_10V4Z PM@ C2148 PM@ C2147 2 10U_0805_10V4Z 1 +1.8VS U64 2 Q31B 5 <35,36,38,51> SUSP# +1.5V to +1.5VS +1.8V to +1.8VS 8 7 6 5 SUSP SUSP G Q128 2N7002_SOT23 <51> NVVDD_PWRGD +1.8V R1798 100K_0402_5% 1 1 D 2 VGA_SUSP +5VALW 2 2 RTCVREF 4 3 S 5VS_GATE 2 SUSP G Q125 2N7002_SOT23 @ 1 0_0402_5% 2 R1405 3 D VGA_SUSP R1404 4.7K_0402_5% @ 2 2 1 1 R1799 470_0603_5% 2 R1403 4.7K_0402_5% @ 2 4 2 SI4800BDY-T1-E3_SO8 C2140 1 1U_0603_10V4Z 2 3 2 1 1 C2139 10U_0805_10V4Z C2142 5 6 7 8 10U_0805_10V4Z 2 10U_0805_10V4Z C2141 2 1 +5VS +3VS U63 1 +3VS 1 +3VALW TO +3VS +3VALW 1 1 1 2 5 Q31A 2 1 Q39B 2N7002DW-T/R7_SOT363-6 3V_GATE 2 1 R1796 200K_0402_5% +VSB 4 SUSP 6 5 SYSON <35,36,48> SYSON 1 SI4800BDY-T1-E3_SO8 1 3 1 2 3 2 1 1 C2135 2 C2137 1 2 10U_0805_10V4Z 4 1 C2134 R1792 100K_0402_5% 5 6 7 8 3 1 470_0603_5% R1793 Q30A 0.1U_0603_25V7K 2 2N7002DW-T/R7_SOT363-6 2 4 4 2 Q30B 2N7002DW-T/R7_SOT363-6 5VS_GATE 2 1 R1795 200K_0402_5% +VSB C2133 1U_0603_10V4Z 2 10U_0805_10V4Z 2 2 SI4800BDY-T1-E3_SO8 1 +5VALW +3V U62 3 2 1 1 C2132 6 1 1 C2131 10U_0805_10V4Z 1 10U_0805_10V4Z U61 C2130 +3VALW +5VS 5 6 7 8 E +3VALW TO +3V_SB(ICH8M AUX Power) +5VALW TO +5VS +5VALW www.bufanxiu.com D 6 1 5 SUSP 2 Q19B 2N7002DW-T/R7_SOT363-6 1.5VS_GATE 2 1 R1806 510K_0402_5% R1801 100K_0402_5% 4 C2152 0.1U_0603_25V7K 2 Q19A 2N7002DW-T/R7_SOT363-6 1 R1825 2.2M_0402_1% @ S 1 D 2 G 2N7002_SOT23 Q137 @ R1804 100K_0402_5% 2 <27,36,43,44,47> ACIN D 2 G Q126 S 2N7002_SOT23 <36,48> SBPWR_EN 1 1 2N7002_SOT23 Q136 PM@ 3 3 S 1 2 D SBPWR_EN# <28> SBPWR_EN# 2 2 3 1 +VSB 3 2 VGA_SUSP R1824 2.2M_0402_1% PM@ 2 G <27,36,43,44,47> ACIN 1 5 SUSP 1 1 1 Q14A VGA_SUSP 2 2N7002DW-T/R7_SOT363-6 6 910K_0402_5%~D Q14B 2N7002DW-T/R7_SOT363-6 PM@ 4 PM@ C2151 R1805 3 1.8VS_GATE 2 0.1U_0603_25V7K +5VALW 1 PM@ +VSB 2 D S 2 SUSP G Q130 2N7002_SOT23 @ S 2 SYSON# G Q131 2N7002_SOT23 S 3 2 SUSP G Q129 2N7002_SOT23 3 S 3 2 SUSP G Q127 2N7002_SOT23 3 3 S 4 1 D 1 D 1 D 1 D 1 1 R1812 470_0603_5% @ 1 R1811 470_0603_5% 1 R1810 470_0603_5% @ 1 R1809 470_0603_5% +1.5V 2 2 +1.8V 1 R1807 470_0603_5% 4 +0.9VS 2 +1.05VS 2 +1.5VS 2 SYSON# G Q132 2N7002_SOT23 @ 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B C Compal Electronics, Inc. Compal Secret Data Security Classification D Title Size B Date: Document Number DC Interface KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 42 of 53 5 4 3 www.bufanxiu.com 2 1 Enlightener LED +5VALW 2 2 (BLUE) 1 +5VALW 2 2 LED10 HT-191NBQA_BLUE_0603 KAL90_G0_90+@ 1 1 ACIN# (BLUE) R1814 220_0402_5% 1 2 KAL90_90+@ R1816 1 2 453_0402_1% KAL90_90+@ +5VALW LED5 HT-191NBQA_BLUE_0603 KAL90_G0_90+@ ON/OFF LED RIGHT (BLUE) R1826 1.5K 0402 5% KALG0@ 1 R1813 499_0402_1% KALG0@ D ON/OFF LED LEFT +5VALW (BLUE) LED3 2 B 1 4 A 3 PWR_SUSP_LED# +5VALW NUM_LED 2 2 2 R1842 KALH0@ 220_0402_5% 1 2 LED12 KALH0@ R1823 866_0402_1% KALG0@ +5VALW 3 PWR_SUSP_LED# R1818 220_0402_5% 1 2 KAL90_90+@ 3 R1843 KALH0@ 453_0402_1% 1 2 2 R1844 KALH0@ 220_0402_5% 1 2 1 NUM_LED# <36,37> CAPS_LED# B 1 4 A 3 PWR_LED# PWR_SUSP_LED# HT-297UD/CB _BLUE/AMB_0603 KAL90_90+@ FOR EMI (BLUE) PWR_SUSP_LED# PWR_SUSP_LED# C2158 1 @ C 2 100P_0402_50V8J PWR_LED# C2155 1 @ 2 100P_0402_50V8J ON/OFFBTN# C2160 1 @ 2 100P_0402_50V8J NUM_LED# C2162 1 2 100P_0402_50V8J CAPS_LED# C2167 1 @ 2 100P_0402_50V8J MEDIA_LED# C2165 1 @ 2 100P_0402_50V8J PWR_LED# 1 NB 2 (AMB) PWR_LED# LED9 HT-191NBQA_BLUE_0603 KAL90_G0_90+@ 1 NUM_LED# PWR_SUSP_LED# <37> LED6 1 R1819 2 453_0402_1% KAL90_90+@ +5VALW PWR_SUSP_LED# HT-210UD/NB_AMB/BLUE 2 1 2 UD LED8 HT-191NBQA_BLUE_0603 KAL90_G0_90+@ 1 LED7 HT-191NBQA_BLUE_0603 KAL90_G0_90+@ 1 (BLUE) 2 1 2 1 R1839 KALH0@ 453_0402_1% 1 2 (AMB) HT-210UD/NB_AMB/BLUE R1822 866_0402_1% KALG0@ MEDIA_LED# 3 1 NB +5VS (BLUE) 2 2 (BLUE) @ A D PWR_LED# <37> HT-297UD/CB _BLUE/AMB_0603 KAL90_90+@ +5VALW LED11 KALH0@ CAPS_LED +5VS R1821 866_0402_1% KALG0@ 4 PWR_LED# ON/OFF LED DOWN ON/OFFBTN# <38> +5VALW R1820 10K_0402_5% 1 (AMB) UD +5VS 1 R1817 2 453_0402_1% KAL90_90+@ B (BLUE) ON/OFFBTN# 5 6 4 MEDIA_LED LED4 2 ON/OFF Button SW3 EVQPLHA15_4P 3 1 C R1815 220_0402_5% 1 2 KAL90_90+@ +5VALW HT-297UD/CB _BLUE/AMB_0603 KAL90_90+@ (AMB) ACIN# PWR_LED# @ CAPS_LED# <36> 6 PWR_LED# Q133A 2N7002DW-T/R7_SOT363-6 B ON/OFFBTN# 2 <36> PWR_LED B 1 R1831 10K_0402_5% 2 D58 2 2 ACIN# D57 3 D56 2 3 NUM_LED# 2 3 PWR_SUSP_LED# D55 CAPS_LED# 1 MEDIA_LED# 3 PWR_LED# PJMBZ6V8_3P_C/A_SOT-23 KAL90_G0_90+@ 3 PJMBZ6V8_3P_C/A_SOT-23 KAL90_G0_90+@ 1 1 1 1 PWR_SUSP_LED# PJMBZ6V8_3P_C/A_SOT-23 PJSOT24C_3P_C/A_SOT-23 Q133B 2N7002DW-T/R7_SOT363-6 5 R1830 ACIN# 1 D 2 A <31> 1 5IN1_LED# SATA_LED# +3VS 2 G ACIN <27,36,42,44,47> A 6 4 3 5 <26> SATA_LED# Q134A 2N7002DW-T/R7_SOT363-6 Q135 KAL90_G0_90+@ 2N7002_SOT23 S 10K_0402_5% 3 +3VS D4 USE PJSOT24C 3P C/A SOT-23 SCA00000E00 24V 2 D1 D2 D3 USE PANJIT PJMBZ6V8 SCA00000I00 6.8V MEDIA_LED# Q134B 2N7002DW-T/R7_SOT363-6 MEDIA_LED# <37> Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 1 <36> PWR_SUSP_LED 4 3 2 Title Compal Electronics, Inc. Size Document Number Custom Date: PWR/B KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet 1 43 Rev 1.0 of 53 A www.bufanxiu.com C D DC231000500 1 VIN 1 PR3 84.5K_0402_1% 1 1 2 2 2 1 1 3 2 - 2 PD3 GLZ4.3B_LL34-2 2 PR7 10K_0402_1% + 0 2 8 2 1 PU1A LM358DT_SO8 2 1 PC6 0.1U_0603_25V7K 2 PR5 22K_0402_5% P 2 PR209 10K_0402_1% 1 1 <27,36,42,43,47> ACIN 1 PC1 1000P_0402_50V7K PR4 0_0402_5% G 1 2 PC4 100P_0402_50V8J PC2 100P_0402_50V8J 2 PC3 1000P_0402_50V7K 1 1 1 2 PJP3 VIN 4 @ PR2 10K_0402_5% 2 3 2 VS 1 2 DC_IN_S2 1 PR6 20K_0402_1% VIN PL1 SMB3025500YA_2P DC_IN_S1 1 G G 1 PR1 1M_0402_1%SINGA_2DC-G756I200 2 1 B PC5 1000P_0402_50V7K PR8 10K_0402_1% 1 PR123 1 2 RTCVREF 2 10_0603_5% MCVCC PQ25 @ SI2301BDS-T1-E3_SOT23-3 3 S 1 2 1 D 3 G 2 2 PR122 @ 200K_0402_1% S 2 1 D Min. H-->L 16.976V L-->H 17.430V RTCVREF D D 1 G PR102 200K_0402_1% @ Vin Dectector PQ28 @ SI2301BDS-T1-E3_SOT23-3 3 S 1 1 +3VALWP Typ 17.525V 17.901V 2 Max. 17.728V 18.384V 2 2 G PQ45 @ 2N7002W-T/R7_SOT323-3 2 SPOK G @ PQ46 2N7002W-T/R7_SOT323-3 PJ2 2 +3VALWP <45,46> 2 PJ3 1 1 +3VALW 2 +1.5VP 2 JUMP_43X118 3 S PJ4 VIN 2 +5VALWP 3 2 1 1 +1.5V JUMP_43X118 PJ5 1 1 +5VALW 2 +0.9VSP 2 1 1 +0.9VS 3 JUMP_43X79 2 JUMP_43X118 PD4 LL4148_LL34-2 1 N1 2 1 1 PQ1 TP0610K-T1-E3_SOT23-3 PR11 200_0603_5% PR9 68_1206_5% 3 VS 1 PC8 0.1U_0603_25V7K 2 +1.05VSP - + PBJ1 2 1 +RTCBATT +RTCBATT 3.3V OUT IN GND PC9 10U_0805_10V4Z 1 +1.05VS +1.8V 2 2 2 PJ18 1 1 +1.05VS 2 +1.1VSP 2 1 1 2 1 1 +1.1VS JUMP_43X118 PJ20 2 +1.8V 1 1 JUMP_43X118 +VGA_CORE +VGA_COREP PJ21 2 2 1 1 +VGA_CORE JUMP_43X118 4 2 N2 Issued Date B Compal Electronics, Inc. Compal Secret Data Security Classification PC10 1U_0805_25V4Z 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A PJ17 +1.8VP JUMP_43X118 1 3 1 1 2 2 1 1 1 1 JUMP_43X118 2 PR16 560_0603_5% 2 2 JUMP_43X118 PR14 200_0603_5% PU2 G920AT24U_SOT89-3 1 1 2 PR15 560_0603_5% +CHGRTC 2 PJ16 +VGA_COREP 4 2 2 +1.05VSP ML1220T13RE 2 RTCVREF PJ7 +1.8VP JUMP_43X118 2 2 1 <38> 51ON# +VSB PJ8 2 1 PR13 22K_0402_1% PC7 0.22U_0603_25V7K 1 1 PR10 68_1206_5% 1 2 PR12 100K_0402_1% 2 JUMP_43X39 1 CHGRTCP 1 2 2 2 BATT+ PJ6 2 +VSBP 1 PD5 LL4148_LL34-2 C Title Size Document Number Custom Date: DCIN & DETECTOR KALG0- Sheet Monday, April 27, 2009 D 44 Rev 0.1 of 53 A B www.bufanxiu.com C D PH1 under CPU botten side : CPU thermal protection at 96 degree C Recovery at 60 degree C VL VL VL 2 VMB PR17 47K_0402_1% 1 PR18 47K_0402_1% 1 1 2 3 TM_REF1 2 + - 2 PU3A LM393DG_SO8 1 2 3 LL4148_LL34-2 PR23 100K_0402_1% 2 1 VL 1 1 2 PR25 100K_0402_1% 2 2 PR26 1K_0402_1% PC15 1000P_0402_50V7K 1 1 +3VALWP PR22 15.4K_0402_1% 1 1 2 2 PR24 6.49K_0402_1% 2 1 PR21 100_0402_1% 1 PR20 100_0402_1% PC14 0.22U_0603_16V7K 2 2 1 O <26,46> PQ2 DTC115EUA_SC70-3 PD6 4 SUYIN_250133MR007G115ZL 2 8 PR19 13.7K_0402_1% P PC13 0.01U_0402_25V7K G PC12 1000P_0402_50V7K 1 MAINPWON 1 PC11 0.1U_0603_25V7K 1 PH1 100K_0603_1%_TH11-4H104FT 2 EC_SMCA EC_SMDA BATT+ 2 2 1 1 PL2 SMB3025500YA_2P BATT_S1 1 1 2 3 4 5 6 7 2 1 2 3 4 5 6 7 1 PJP2 2 1 2 2 BATT_TEMP <36> PH2 near main Battery CONN : BAT. thermal protection at 79 degree C Recovery at 47 degree C EC_SMB_CK1 <36,37> EC_SMB_DA1 <36,37> 2 VL @ PR27 47K_0402_1% @ PR28 47K_0402_1% 1 2 VL 6 + P 5 TM_REF1 1 @ 2 - G 1 8 @ PR30 13.7K_0402_1% 4 @ PR32 15.4K_0402_1% 7 2 1 3 PU3B LM393DG_SO8 2 2 @ PC18 0.22U_0603_16V7K @ PD7 LL4148_LL34-2 O 1 1 2 2 @ @ PH2 100K_0603_1%_TH11-4H104FT 2 2 +VSBP 1 PC17 0.1U_0603_25V7K 1 2 PR31 22K_0402_1% VL 2 3 1 1 PR29 100K_0402_1% PC16 0.22U_1206_25V7K 3 B+ 1 2 PQ3 TP0610K-T1-E3_SOT23-3 1 VL 1 PQ4 2 D S 2 2 1 G PC19 0.1U_0402_16V7K 1 PR34 0_0402_5% 1 <44,46> SPOK 3 PR33 100K_0402_1% 2N7002W-T/R7_SOT323-3 @ 4 4 Issued Date 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. A B Compal Electronics, Inc. Compal Secret Data Security Classification C Title BATTERY CONN / OTP Size Document Number Custom Date: KALG0- Sheet Monday, April 27, 2009 D 45 Rev 0.1 of 53 5 4 3 www.bufanxiu.com 2 1 ISL6237_B+ ISL6237_B+ DRVL2 DRVL1 32 1 PGND VOUT2 VOUT1 REFIN2 1 1 VSW LDOREFIN SKIPSEL EN_LDO PGOOD1 GND TRIP2 21 2 TONSE 5 EN2 TRIP1 VREF3 EN1 1 2VREF_ISL6237 1 1 2 3 3 2 1 22 11 PC25 2200P_0402_50V7K 2 1 2 + PC35 C 150U_D2E_6.3VM_R18 9 @PR44 @ PR44 2 29 PR45 1 28 0_0402_5% 1 VL 0_0402_5% 2 13 12 ILM1 PR48 330K_0402_1% 2 1 31 ILIM2 2 SN0806081RHBR_QFN32_5X5 SPOK <44,45> B 1 PR49 200K_0402_1% +5VALWP Ipeak=7A ; Imax=4.9A Choke DCRmax=60m ohm, DCRtyp=54m ohm Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 330K)/10=165mV Ilimit=165mV/18m ~ 165mV/15m =9.167A ~ 11A Iocp=Ilimit+Delta I/2 =10.147A ~ 11.980A Delta I=1.123A (Freq=400KHz) PR53 0_0402_5% 1 A Compal Secret Data 2007/09/20 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4 PC24 4.7U_1206_25V6K 2 1 FB5 @PC39 @ PC39 0.047U_0402_16V7K Security Classification 5 1 2 10 PQ35 TP0610K-T1-E3_SOT23-3 2 A PC38 0.047U_0402_16V7-K 1 1 @PR55 @ PR55 47K_0402_5% 1 2 PGOOD2 1 2 PR54 0_0402_5% 2 1 DL5 2VREF_ISL6237 2 2 PR51 0_0402_5% 2 @ PR50 @PR50 0_0402_5% 2 1 27 VL PR52 806K_0603_1% <26,45> MAINPWON 14 PC37 0.22U_0603_25V7K 2 PD12 1SS355_SOD323-2 2 4 NC PC143 1U_0603_10V6K 1 2 20 PR46 100K_0402_1% 1 2 PR47 200K_0402_5% 1 2 PD8 GLZ5.1B_LL34-2 1 2 LX5 18 VREF2 0.22U_0603_10V7K 8 1 B +3.3VALWP Ipeak=4.33A ; Imax=3.1A;Iocp=5.2A Choke DCRmax=60m ohm, DCRtyp=54m ohm Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Vlimit=(5E-06 * 200K)/10=100mV Ilimit=100mV/18m ~ 100mV/15m =5.56A ~ 6.67A VS Iocp=Ilimit+Delta I/2 =6.12A ~ 7.23A Delta I=1.108A (Freq=300KHz) 2 FB1 16 4 1 LL1 PQ8 AO4712_SO8 PR41 63.4K_0402_1% LL2 2VREF_ISL6237 PC36 DH5 PR40 0_0603_5% BST5A 2 1 25 30 VL 17 PC32 0.1U_0603_25V7K 2 FB3 @ PR42 @PR42 10K_0402_1% 15 PR43 10K_0402_1% 1 2 VBST1 5 6 7 8 7 LDO 3 6 VIN VBST2 PR39 4.7_1206_5% 2 1 23 DRVH1 PC29 1U_0603_10V6K 1 2 19 PL4 8.2UH +-20% FDV0630-8R2M=P3 3.7A 2 1 PC34 680P_0402_50V7K 2 1 DL3 V5DRV DRVH2 D +5VALWP 2 24 V5FILT 2 1 BST3A 0_0603_5% PC31 0.1U_0603_25V7K LX3 TP PQ6 AO4466_SO8 4 PC28 4.7U_0603_6.3V6M 2 1 PC27 1U_0603_10V6K 1 2 VL 3 2 1 PC33 680P_0402_50V7K 26 1 2 3 1 1 4 2 2 C DH3 PR37 2 1 PQ7 AO4712_SO8 2 PR38 0_0402_5% + 2 PC30 330U_D2E_6.3VM_R25M 1 PU4 33 PR36 4.7_1206_5% 1 1 PC23 4.7U_1206_25V6K 2 1 5 6 7 8 8 7 6 5 PL3 8.2UH +-20% FDV0630-8R2M=P3 3.7A 1 2 +3VALWP PC26 0.1U_0603_25V7K 1 2 3 PC20 4.7U_1206_25V6K 2 1 PC41 2200P_0402_50V7K 2 1 PQ5 AO4466_SO8 4 8 7 6 5 1 JUMP_43X118 PC22 2200P_0402_50V7K 2 1 2 PR35 0_0805_5% 1 2 1 2 PJ10 PC21 4.7U_1206_25V6K 2 1 B+ PC92 2200P_0402_50V7K 2 1 D 2 3 2 Title Compal Electronics, Inc. +5VALWP/+3VALWP Size Document Number Custom Date: KALG0- Monday, April 27, 2009 Sheet 1 46 Rev 0.1 of 53 A B DH_CHG 25 LX_CHG PD10 ACOP <36> 10 SRN 1 VDAC 12 2 VMB ACGOOD 14 15 1 2 2 1 3 2 1 2 1 2 1 5 6 7 8 2 2 2 1 3 1 1 1 3 S VADJ 2 24751_VREF 1 2 2 1 2 <36> FSTCHG G 2N7002W-T/R7_SOT323-3 PR86 100K_0402_1% 2 G S PQ18 2N7002W-T/R7_SOT323-3 1 S 1 G 4 2 1 3 S 2 CHGEN# D 3 1 PR81 100K_0402_1% D 2 3 PC144 1000P_0402_50V7K 1 2 @ PR177 4.3K_0402_5% 1 2 PR82 100K_0402_1% 1 1 G PR80 0_0402_5% <27,36,42,43,44> @ PQ16 2N7002W-T/R7_SOT323-3 2 2 PQ17 SI2301BDS-T1-E3_SOT23-3 2N7002W-T/R7_SOT323-3 REGN ACGOOD# 2 S ACIN D PR78 887K_0402_1% PR84 221K_0402_1% 1 D G 1 2 1 1 PQ36 2 2N7002W-T/R7_SOT323-3 G 24751_VREF 2 2 @ PR75 100K_0402_1% @ PR176 0_0402_5% <36> 1 3 1 S PQ37 ADP_I <36> CALIBRATE# D PQ20 65W/90W# 24751_VREF 3 PQ19 4 <36> IREF=0.7748*Icharge PQ15_GATE 2 1 2 D 3 PC66 0.01U_0402_25V7K 2 2 1 4 PC163 0.1U_0402_16V7K ACOFF 1 2 PR181 340K_0402_1% 6 1 8 5 ACSET PR85 100K_0402_1% IREF <36> @ PC63 @PC63 0.01U_0402_25V7K 2 PR76 499K_0402_1% 24751_VREF PR180 200K_0402_1% 24751_VREF PR79 105K_0402_1% PR73 100K_0402_1% 2 For 2200mA, Icharge=0.8C=0.8*2*2.2=3.52A For 2400mA, Icharge=0.8C=0.8*2.4*2=3.84A Icharge=(Vsrset/Vdac)*(0.1/PR62) IREF=((100k/(100K+17.4K))/3.3)*(0.1/0.02)=Icharge G PR83 64.9K_0402_1% 24751_VREF 1 2 1 1 D - 2 S + 0 SRSET PR72 10_0603_5% PC64 100P_0402_50V8J 1 7 P 2 PU1B LM358DT_SO8 G PR77 10K_0402_1% Icharge Setting PR71 17.4K_0402_1% BQ24751ARHDR_QFN28_5X5 2 Per cell=4.5V 1 PR74 340K_0402_1% PR179 100K_0402_1% 2 BATT-OVP=0.1112*VMB PC61 0.1U_0603_25V7K ICHG setting 16 SRSET BATDRV 2 LI-3S :13.5V----BATT-OVP=1.5012V <36> BATT_OVP 2 29 TP 1 /BATDRV 1 BATT-OVP=0.1112*VMB 1 Fsw : 300KHz VS LI-4S :18.0V----BATT-OVP=2.001V PC65 0.01U_0402_25V7K Input OVP : 22.3V SE_CHG- VADJ IADAPT Input UVP : 17.26V SE_CHG+ 18 1 VADJ 13 CP POINT=(1.436V/3.3V)*(0.1/0.015)=2.901A 19 @PC59 @PC59 0.1U_0603_25V7K 17 BAT ACGOOD# Vacset=3.3*(50K/(50K+64.9K))=1.436V CELLS 1 2 SRP 11 PR70 100K_0402_1% ACSET PC58 0.1U_0603_25V7K 20 1 2 PC62 0.1U_0603_25V7K 65W adapter R=(100K*100K)/(100K+100K)=50K 3 2 2 <36> VREF PC60 1U_0603_10V6K RTCVREF 1 CP point=Iadapter*85% CP Point=(Vacset/Vvdac)*(0.1/PR56)=4.04A 1 ACOFF 2 CELLS 24751_VREF PR69 100K_0402_1% 1 2PQ15_GATE 2 90W adapter Vacset=3.3*(100K/(64.9K+100K))=2.001V PC55 680P_0402_50V7K 1 1 24751_VREF PQ15 SI2301BDS-T1-E3_SOT23-3 CP Point Setting PC57 0.1U_0402_16V7K 21 LEARN 3 2 PR68 54.9K_0402_1% Cells selector AGND DL_CHG 22 PGND OVPSET 9 2 3 S PQ13 AO4466_SO8 4 1 3S/4S# G 8 4 2 1 2 PC54 1U_0603_10V6K 23 LODRV BATT+ 0.02_1206_1% 1 1 7 PR62 2 @ PR64 4.7_1206_5% 24 REGN 1 2 OVPSET @ PQ14 2N7002W-T/R7_SOT323-3 3 1 D 1 PR67 340K_0402_1% 1 2 1 2 CELLS 2 ACSET PC56 0.47U_0603_16V7K 2 PR66 0_0402_5% 1 6 1 4 Cell ACSET 2 2 VREF @ PR65 47K_0402_1% PR63 54.9K_0402_1% 2 3 Cell 1 PC51 LL4148_LL34-2 0.1U_0603_25V7K REGN 2 GND PL5 10UH_PCMB104T-100MS_6A_20% 1 1 2 2 PH 1 ACDRV ACDET 1 2 CELLS 4 5 6 7 8 26 /BATDRV PQ11 AO4466_SO8 4 1 4 5 HIDRV 2 @ ACDRV ACN ACP PR61 0_0603_5% 1 1 2 BTST 1 PQ12 SI4835DDY-T1-E3_SO8 PC53 10U_1206_25V6M 27 PR57 100K_0402_1% 2 1 ACDET 2 3 BTST 2 PC40 0.01U_0402_25V7K PC52 10U_1206_25V6M 1 PC44 2200P_0402_25V7K PVCC Place close to back to back MOS 24751_VREF PC48 0.1U_0603_25V7K 28 PC43 4.7U_1206_25V6K PVCC 1 2 CHGEN @PC49 @ PC49 0.1U_0603_25V7K ACN ACP CHG_B+ 1 3 2 1 PC47 0.1U_0603_25V7K 1 PC42 4.7U_1206_25V6K 1 2 2 2 2 1 2 PU5 2 2 JUMP_43X118 1 1 1 1 PC46 0.1U_0402_16V7K PR60 340K_0402_1% PC50 2.2U_0805_25V6K 2 CHGEN# PR59 100K_0402_1% 2 2 1 PC45 0.01U_0402_25V7K PR174 3.3_1210_5% PJ11 PR56 1 0.015_1206_1% 2 5 6 7 8 8 7 6 5 4 2 1 1 1 2 3 4 1 1 2 3 PR58 3.3_1210_5% B+ PQ10 AO4407A_SO8 8 7 6 5 D 3 2 1 PQ9 AO4407A_SO8 VIN www.bufanxiu.com C 2N7002W-T/R7_SOT323-3 CP setting A Charger ADJ Calibrate# PR78 PR84 4.0V L @ @ 4.1V L 887K 221K 4.2V H @ @ B Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C Title Size Document Number Custom Date: CHARGER KALG0- Sheet Monday, April 27, 2009 D Rev 0.1 47 of 53 A B www.bufanxiu.com C D PJ15 JUMP_43X118 PR88 2.2_0603_1% 1 2 2 1 PR89 10_0603_1% 8 6228_1.05VO1 2 2 1 1 PR92 18.2K_0402_1% 1 2 VIN2 3 VCC2 4 6 ISL6228_B+ FB1 GND_T 29 PGOOD2 PR98 3.3K_0402_5% PR97 22.6K_0402_1% 28 OCSET_1.05V 10 1.05V_EN 11 VO1 FB2 OCSET1 VO2 PQ21 AO4466_SO8 UGATE2 22 BOOT2 2 1 2 PR105 14.7K_0402_1% LG_1.05V S S S LG_1.8V @ PR178 0_0402_5% 1 1.05V_EN 2 2 PR112 0_0402_5% 1 <38,49> VS_ON @ PC94 @PC94 0.1U_0402_16V7K +1.8VP 1 1 2 + PC88 330U_D2E_2.5VM 2 @ PC89 680P_0402_50V7K 4 2 Issued Date Compal Electronics, Inc. Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. B 3 2 PL12 1UH_FDV0630-1R0M-P3_10.3A_20% DCR 10m ohm(max) Cout ESR=15m ohm 1.8VP( Ibudget=9.91A ) Ipeak=9A, Imax=6.3 A Fsw=1/1.5E-10*18.2k =366K Vo=Vref*((PR97+PR99)/PR97) Iocp=9*1.2=10.8A Iocp*DCR=(Rocset*9.5uA)=10.67*1.3*10m; Roset=14.78K now chose Roset=14.7K Csen=L/(DCR*Roset)=1uH/(10m*14.7k); Csen=8.16nF now chose Csen=8200pF Iocp_min=(14.7K*9.5uA)/(10m ohm*1.3) =10.74A Iocp_max=(14.7*10.5uA)/(10m ohm )=15.43A 1 <36,42> SBPWR_EN 1 2 PC86 1U_0402_6.3V6K 1 @ PR108 4.7_1206_5% 2 1 G 3 2 1 2 1 2 1 2 +5VALW 4 PQ24 FDS6670AS_NL_SO8 5 6 7 8 D D D D BST_1.8V 1 PC87 0.1U_0402_16V7K Cout ESR=15m ohm A PC82 8200P_0402_25V7K 1 LX_1.8V 21 PVCC2 20 LGATE2 19 PGND2 PGND1 18 15 17 PC84 0.1U_0402_16V7K PC85 1U_0402_6.3V6K 1.05VSP ( Ibudget=17.47A) OCP Seting Fsw=1/1.5E-10*22k =303K Vo=Vref*((PR95+PR94)/PR94) Ipeak=13.29A, Imax=9.31A Iocp=13.29*1.2=15.95A Delta I=4.09A Iocp*DCR=(Rocset*9.5uA)=(15.95*1.3*10m; Roset=21.8K now chose Roset=22K Csen=L/(DCR*Roset)=1uH/(10m*22k); Csen=0.00523uF now chose Csen=5600pF Iocp_min=(22K*9.5uA)/(10m ohm*1.3) =16.07A Iocp_max=(22K*10.5uA/(10m ohm )=23.1A PQ23 AO4466_SO8 UG_1.8V 2 23 4 BOOT1 +5VALW 4 2 2 PHASE2 <35,36,42>ISL6228_B+ 1 PR106 0_0603_5% 1 BST_1.05V14 UGATE1 LGATE1 1 2 13 SYSON 2 @ PC78 0.01U_0402_25V7K PC79 4.7U_1206_25V6K EN2 1 24 1 PR103 0_0402_5% PHASE1 16 S S S 1 2 3 1 12 PR109 0_0603_5% DCR 10m ohm(max) 2 OCSET_1.8V 25 1 4 2 3 1 PC81 4.7U_1206_25V6K OCSET2 PU6 PQ22 FDS6670AS_NL_SO8 2 FB_1.8V 2 PR100 14.7K_0402_1% 3 2 1 1 2 3 D D D D G PC83 @ 680P_0402_50V7K LX_1.05V UG_1.05V 2 1 5 6 7 8 EN1 PVCC1 + PL6 1UH +-20% FDV0630-1R0M=P3 10.3A PR104 @ 4.7_1206_5% 2 1 2 Vref=0.6V 4 8 7 6 5 1 2 1 1 1 2 6228_1.8VO2 26 1 PR99 45.3K_0402_1% FB_1.8V-1 27 ISL6228HRTZ-T_QFN28_4X4 +1.05VSP PC80 330U_D2E_2.5VM 8 7 6 5 1 2 PR101 22K_0402_1% 9 PC77 4.7U_1206_25V6K 1 2 2 1 2 PC75 5600P_0402_25V7K PC76 4.7U_1206_25V6K ISL6228_B++ PC74 1000P_0402_50V7K 2 1 2 1 2 PR96 22K_0402_1% VCC1 FB_1.05V-1 1 FSET1 2 7 PR95 45.3K_0402_1% FB_1.05V PC69 0.1U_0603_25V7K 2 1 PR94 59K_0402_1% 1 PR90 10_0603_1% 1 2 PR91 22K_0402_1% 1 2 2 1 PGOOD1 1 PC71 1000P_0402_50V7K +5VALW PC73 1000P_0402_50V7K 2 1 2 PR93 3.3K_0402_5% 2 PC72 1000P_0402_50V7K 1 1 1 1 2 PC70 0.1U_0603_25V7K ISL6228_B++ 2 2 +5VALW 1 PR87 2.2_0603_1% ISL6228_B+ PC68 1U_0402_6.3V6K 2 1 1 PC105 2200P_0402_50V7K 1 2 PC102 2200P_0402_50V7K 2 2 PJ12 JUMP_43X118 2 B+ 1 1 PC67 1U_0402_6.3V6K 2 ISL6228_B++ FSET2 1 1 5 2 VIN1 2 B+ C Title Size Document Number Custom Date: 1.8VP / 1.05VSP KALG0- Sheet Monday, April 27, 2009 D Rev 0.1 48 of 53 www.bufanxiu.com 2 1 PR110 0_0402_5% 2 PR113 0_0603_5% 1 2 1 2 3 4 D2 D2 G1 S1 DL_1.5V 14 DH_1.5V 12 LX_1.5V 1 +1.5VP 2 1 + +5VALW 11 10 9 1 2.2UH +-20% FDV0630-2R2M=P3 7.2A PL8 PC95 330U_D2E_2.5VM 2 DL_1.5V 2 TPS51117RGYR_QFN14_3.5x3.5 1 1 15 TP VBST DRVL 13 D 2 G2 S2/D1 S2/D1 S2/D1 B+ 1 1 PC97 4.7U_0805_10V6K 2 PC98 1U_0603_10V6K C 2 TRIP V5DRV 7 @ PC96 47P_0402_50V8J 2 1 1 LL VFB=0.75V VFB PGOOD DRVH 1 PC93 0.1U_0603_25V7K 2BST_1.5V-1 1 2 2 6 PR114 300_0603_5% V5FILT BST_1.5V 1 5 VOUT PGND 4 8 3 TON EN_PSV PU7 GND 2 @ PC90 0.01U_0402_25V7K 2 +5VALW PQ26 8 7 6 5 AO4932_SO8 1 PR115 6.49K_0402_1% 2 1 1 <38,48> VS_ON DH_1.5V PR111 300K_0402_5% 2 PC106 2200P_0402_50V7K D PJ13 JUMP_43X118 2 1 1 51117_B+ 2 3 PC107 2200P_0402_50V7K 4 PC91 4.7U_1206_25V6K 5 C PR116 10K_0402_1% 2 1 1 PR117 10K_0402_1% 1 2 +1.8V 2 PJ14 JUMP_43X79 1 3 PR118 1K_0402_1% 4 VCNTL GND NC REFEN NC VOUT NC GND 2 1 PC99 4.7U_0603_6.3V6M VIN +3VALW 6 5 1 2 7 2 2 PU8 1 2 Cout ESR=15m ohm ( Ibudget=3.46A ) MOS Rds(on)=19.6 m ohm Ipeak=2.84A, Imax=2A Iocp=3.48A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=2.4A =>1/2DeltaI=1.2A Vtrip=Rtrip*10uA=6.49K*10uA=0.0649V Iocpmin=Vtrip/Rdsonmax*1.2+1.46A =0.0649/(0.0196*1.2)+1.2=2.76A+1.2A=3.96A Iocpmax=(0.0649/(0.016))+1.2A=5.26A Iocp=3.96~5.26A 8 PC100 1U_0402_6.3V6K 9 2 2 3 G PR120 2N7002W-T/R7_SOT323-3 S 1K_0402_1% B 1 +0.9VSP 1 2 PC103 0.1U_0402_16V7K 1 1 2 D 2 1 PQ27 2 <38,42> SUSP PR119 0_0402_5% PC101 0.1U_0402_16V7K RT9173DPSP_SO8 1 B 1 VFB=0.75V Vo=VFB*(1+PR116/PR117)=0.75*(1+10K/10K)=1.5V Ton=300K Fsw=262KHz PC104 10U_0805_6.3V6M A A 2007/09/20 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 Compal Electronics, Inc. Compal Secret Data Security Classification 3 2 Title +1.5VP/+0.9VSP Size Document Number Custom Date: Rev 0.1 KALG0- Sheet Monday, April 27, 2009 1 49 of 53 5 4 3 www.bufanxiu.com 2 1 +5VS 2 2 PR169 0_0402_5% 1 2 PR172 1K_0402_1% 2 CPU_B+ 1 2 PC116 1000P_0603_50V7K 1 2 2 1 PC114 2200P_0402_50V7K 1 PC113 10U_1206_25V6M 2 PC112 10U_1206_25V6M 5 3 2 1 1 1 2 1 2 1 2 1 1 3 1 4 2 PR156 1_0402_5% @ PR159 0_0603_5% 2 PR155 10K_0402_1% 1 2 PR157 3.65K_0805_1% 1 1 2 1 1 2 PR154 6.8_1206_5% 5 6 7 8 2 PR144 10K_0402_1% 1 2 PR143 3.65K_0805_1% 1 PC120 680P_0402_50V7K PR142 6.8_1206_5% 1 2 PL11 0.36UH_PCMC104T-R36MN1R17_30A_20% 2 VSUM 1 2 PC132 0.22U_0603_10V7K ISEN2 VCC_PRM B 2 1 2 PR173 4.42K_0402_1% 1 2 PH3 10KB_0603_5%_ERTJ1VR103J 1 1 5 6 7 8 +5VS 3 2 1 2 1_0603_5% C 2 2 PC139 180P_0402_50V8J 1 4 VCC_PRM CPU_B+ PR168 2.61K_0402_1% 1 2 PR170 20_0402_5% PC138 0.01U_0603_50V7K 2 1 <5> VSSSENSE 3 2 1 PQ32 SI7686DP-T1-E3_SO8 PQ34 AO4456_SO8 2 VSUM @ PC137 @PC137 0.022U_0603_50V7K PR171 11K_0402_1% 2 4 +CPU_CORE 2 PC117 1000P_0603_50V7K BOOT_CPU2 1 2 1 2 PR152 0_0603_5% PC127 0.22U_0603_10V7K U_CPU2-1 1 1 PC124 2200P_0402_50V7K 26 1 2 PR145 1_0402_5% 1 27 UGATE_CPU2-1 @ PR146 0_0603_5% 2 PHASE_CPU2 3 VSUM 2 2 28 2 PR121 0_0603_5% 29 4 2 PC121 0.22U_0603_10V7K ISEN1 PC123 10U_1206_25V6M LGATE_CPU2 30 PC122 10U_1206_25V6M 31 3 2 1 2 LGATE_CPU1 32 5 33 LGATE_CPU1 3 2 1 PHASE_CPU1 34 PC129 680P_0402_50V7K 1 820P_0402_50V7K 2 1 3 2 1 1 5 6 7 8 UGATE_CPU1 35 25 PQ31 AO4456_SO8 4 1 D PC115 220U_25V_M PC135 0.1U_0603_25V7K 1 1 2 +CPU_CORE PC136 2 PR167 20_0402_5% 5 6 7 8 2 1 2 ISEN1 4 1 + PL10 0.36UH_PCMC104T-R36MN1R17_30A_20% PHASE_CPU1 2 36 24 ISEN2 23 VDD 22 GND 21 VIN 20 1 2 1 <5> VCCSENSE 1 2 1 PQ29 SI7686DP-T1-E3_SO8 4 PC131 1U_0402_6.3V6K 1 PR165 1K_0402_1% PR166 0_0402_5% U_CPU1 PC119 0.22U_0603_10V7K PR164 10_0603_5% 2 1 B 1 1 4 1 PC134 1000P_0402_50V7K 2 2 2 1 2 PR163 255_0402_1% 1 PR107 0_0603_5% LGATE_CPU2 2 PC110 2.2U_0603_6.3V6K PQ33 AO4456_SO8 PR158 2 220P_0402_50V7K 1 PC109 0.022U_0402_16V7K ISEN1 ISEN2 2 1 1 PC133 2 1 2 @ PR161 0_0402_5% PR162 1K_0402_1% 1 2 37 VID0 38 VID1 39 VID2 40 VID3 41 VID4 42 VID5 VSUM NC PC128 1000P_0402_50V7K PR160 97.6K_0402_1% PC130 470P_0402_50V7K <5> PR133 0_0402_5% 1 2 PR132 0_0402_5% 1 2 PR131 0_0402_5% 1 2 PR130 0_0402_5% 1 2 PR137 0_0402_5% 1 2 PR136 0_0402_5% 1 43 45 46 44 VR_ON DPRSLPVR VID6 VO 19 13 2 DFB FB2 17 12 BOOT2 2 1 47 48 FB DROOP 1 UGATE2 16 2 PHASE2 COMP 11 6.81K_0402_1% LGATE2 PGND2 RTN 1 1000P_0402_50V7K PR153 PVCC PU10 ISL6262ACRZ-T_QFN48_7X7 VW 10 2 LGATE1 OCSET 9 13K_0402_1% PGND1 SOFT 8 2 RBIAS 15 PC125 0.022U_0603_25V7K UGATE1 NTC 7 PC126 CPU_VID0 PL9 FBMA-L18-453215-900LMA90T_1812 PQ30 AO4456_SO8 BOOT1 VR_TT# 6 1 <5> PR138 0_0603_5% BOOT_CPU1 1 PHASE1 VSEN C PR151 <5> CPU_VID1 LGATE_CPU1 4 5 1 CPU_VID2 UGATE_CPU1 PMON VDIFF PR149 147K_0402_1% 2 3V3 PSI# 3 1 DPRSTP# 2 VR_TT# CLK_EN# PGOOD 14 20_0402_5% 2 0_0402_5% 2 1 2 49 GND PC118 1U_0402_6.3V6K 1 2 PR140 1.91K_0402_1% 2 1 1 VGATE PR147 1 2 2 +3VS 1@ PR148 PR129 0_0402_5% 2 0_0402_5% 1 18 PR134 +3VS PSI# 2 1 <16> CLK_ENABLE# <5> <5> 0_0402_5% PR135 0_0402_5% PR128 PGD_IN 0_0402_5% 1 <5,8,26> H_DPRSTP# <36> <5> CPU_VID3 1 2 PR127 <8,16,27> CPU_VID4 B+ CPU_B+ PR125 1_0603_5% 2 1 <8,27> PM_DPRSLPVR PR139 499_0402_1% <5> 1 PR126 499_0402_1% D CPU_VID5 1 VR_ON <5> LGATE_CPU2 <36,38> CPU_VID6 VCC_PRM PC140 0.1U_0402_16V7K 1 PC142 0.22U_0603_10V7K A PC141 2 1 0.22U_0402_6.3V6K A 1 2 2 2007/09/20 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 Compal Electronics, Inc. Compal Secret Data Security Classification 3 2 Title +CPU_CORE Size Document Number Custom Date: Rev 0.1 KALG0- Sheet Monday, April 27, 2009 1 50 of 53 5 4 3 www.bufanxiu.com 2 1 PL13 B+_core DH_VCORE BST_VCORE 1 PR184 0_0603_5% DH_VCORE-1 2 2 1 0_0603_5% +5VS 2 PC166 0.1U_0603_25V7K D 1 <42> NVVDD_PWRGD 1 SI7636DP-T1-E3_SO8 4 G 3 2 1 2 S S S G PC171 @ 680P_0603_50V7K 1 1 1 1 1 PR194 2 +NVVDD_SENSE 0_0402_5% C PR193 3K_0402_1% Rds=4.8mOHM VFB=0.6V +3VS 2 2 PC173 0.01U_0402_25V7K + 2 PR197 9.76K_0402_1% 2 PR196 2 @ PR211 40.2K_0402_1% 2 2 GPU_VID1 <18> PR200 10K_0402_1% PC175 0.022U_0402_25V7K 1 1 2 1 3 2 1 2N7002W-T/R7_SOT323-3 G S 10K_0402_5% 1 PQ41D PR198 5.9K_0402_1% PR199 10K_0402_1% 2 1 1 PC174 2 2200P_0402_25V7K 1 2 22P_0402_50V8J PC172 PR195 22K_0402_1% 1 PC169 2 ISL6268CAZ-T_SSOP16 +VGA_COREP PR192 4 VO 10 9 7 6 2 0.1U_0402_16V7K C SI7636DP-T1-E3_SO8 2 6.19K_0402_1% FSET 1 PC170 PR190 ISEN_VCORE 1 11 1 2 ISEN 2 PR191 @ 4.7_1206_5% S S S EN FB 5 PQ40 D PQ39 5 5 12 D 2 2 100K_0402_1% 0.56UH_ETQP4LR56WFC_21A_20% 1 PGND 1 1 PL14 DL_VCORE 13 470U_D_2.5VM_R7M LG 2 VCC 1 1 4 COMP SUSP# DCR=3m OHM 1 2 SUSP# 4 2.2U_0603_6.3V6K PC168 2.2U_0603_6.3V6K PR187 10K_0402_5% PR189 <35,36,38,42> 6269_VCORE 2 PVCC PR186 2 4.7_0603_5% 1 2 PC167 14 6269_VCORE @ 1 BOOT UG 2 15 16 1 2 VIN PQ38 SI7686DP-T1-E3_SO8 3 2 1 +3VS PHASE 3 PGOOD GND PU12 8 PR185 0_0603_5% 10_0402_1% PR182 10K_0402_1% 1 PR183 1 1 1 2 VGA_CORE Imax=9.247A Ipeak=13.21A Iocp=15.852A LX_VCORE 2 D 6269_VCORE PC165 10U_1206_25V6M 2 1 PC164 10U_1206_25V6M FBMA-L11-322513-201LMA40T_1210 3 2 1 2 5 1 B+ PR201 6.04K_0402_1% B +3VS 2 +1.8VS 2 PCIE_OK B @ PR210 10K_0402_5% 1 GPU_VID0 2 GPU_VID0 GPU_VID1 Core Voltage Level 0 0 0.9 V 0 1 1.09 V <18> PR204 10K_0402_1% 2 0.022U_0402_25V7K 1 S IC APL5913-KAC-TRL SO 8P 1 PC179 2 PR207 1.15K_0402_1% 9 PC182 22U_0805_6.3V6M 0.01U_0402_25V7K 1 0 1.2V 1 1 1.35 V A @ PC181 22U_1206_6.3V6M 1 0.1U_0402_16V7K 2 PR208 3K_0402_1% Compal Secret Data Security Classification Issued Date 2007/12/18 2008/12/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 1 3 1 2 2 2 PC180 VIN 2 2 1 FB +1.1VSP 1 2 PR212 @ 10K_0402_5% 2 NVVDD_PWRGD A EN 3 1 8 PC178 10U_0805_10V4Z 2 2 5 4 1 G 10K_0402_1% PC177 M86-M 1 1 1 VIN VOUT VOUT 10K_0402_1% SUSP# GND SUSP# 1 <35,36,38,42> POK PR202 2 S 1U_0402_6.3V6K 6 PU13 7 VCNTL @ 10K_0402_5% PR206 PC176 D 2 1 2 2 2 PR205 2 4.7K_0402_5% PR203 1 PQ42 2N7002W-T/R7_SOT323-3 1 +3VS PJ19 JUMP_43X79 @ 1 1 1 +5VS 4 3 2 Title Compal Electronics, Inc. VGA_CORE/1.1VSP Size Document Number Custom KALG0- MXM Date: Monday, April 27, 2009 Sheet 1 51 Rev 0.1 of 53 5 4 3 Version change list (P.I.R. List) Item D Fixed Issue Reason for change www.bufanxiu.com 2 Rev. PG# Modify List 1 Page 1 of 2 for PWR Date Phase 1 Change PR196 value VGA OCP 0.3 50 change the resistance value of pr196 from 57.6K to 40.2K 2009/02/06 PVT 2 Change PL14 value prevent OVP occur 0.3 50 change the inductance value of pL14 from 1uH to 0.56 uH 2009/02/06 PVT 0.3 45 change part number to SA00002V400 2009/02/06 PVT 3 Change PU4 IC part number vender suggestion D 4 5 6 7 C 8 C 9 10 11 12 13 14 B 15 B 16 17 18 19 20 21 22 A 23 A Compal Secret Data Security Classification Issued Date 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Size Document Number Custom Date: KAL90 PIR (PWR) Monday, April 27, 2009 Sheet 1 Rev 0.1 52 of 53 5 4 3 www.bufanxiu.com 2 1 B --> C Change List 0220------------------Page 6, Change C98 BOM structure to @ D C B A 0218--------------Page 20, Add R569 with BOM structure @ Page 23, R34, R38, R40, R53, R54, R55 change BOM structure to @ Page 31, Change R215 to 18K Update Power Schematics D 0213----------------------------------Page 11, Delete R113 Add J1 JUMP_43X79 with BOM structure @ Page 31, R558, R559 0 ohm with BOM structure @ R560, R561 4.7K with BOM structure @ Page 32, R562, R563 0 ohm with BOM Structure @ R564, R565 0 ohm Page 38, Delete C619 Add R566, R567, R568 0_0603 with BOM Structure JAL90@ 0204---------------------------------Page 12, Change L31 to MBK1608301YZF_0603 with BOM structure GM@ Change R163 to 0_0805_5% Page 23, Change BOM Structure of U5 to @ Page 27, Change BOM Structure of R555 and R550 to @ Page 33, Change R217 to 31.6K_0402_1% Change C313 to 1U_0603_10V6K Page 34, Change R503 to FBMA-L10-160808-301LMT_0603 01/31--------------------------------Page 23, Delete U10 01/29--------------------------------Page 23, Change R152 BOM Structure to @ 01/24-------------------------------Page 4, Change U8 to SA00001Z700 (EMC1402) Page 33, Change C338 to SE076104K80 Page 35, Mount C584 01/23--------------------------------Page 38 Delete F3, R558~560, C609~614 01/22------------------------------------Page 11, Delete R79 Change J1 Symbol to JUMP_43X79 Page 33, Add R557 10K (Check) Change R245 BOM Structure with @ Page 38, Add C609~614, R558~560 (Check) C607,608, 615~619 (Check) 01/17------------------------------------Page 11, Add R79 0_0805 Update Power Schematics 01/16-----------------------------------Page 11, Delete R79 0_0805 Add J1 JUMP_43X79 Page 16, Change C296, R301 to 27P_0402 Page 19, Change L17, L19, L21 BOM structure to GM@ Page 23, Mount U29, R339 Add U10 with BOM structure @ (Co-lay with U5) Change R340 Bom structure to @ Change U5 to MX25L4005AMC-12G_SO8 (SA00002A900) Page 27, Change U26, C420 BOM structure to @ Change R550 to 0_0402 Add R555 0_0402 Page 32, Change R269 to 240_0402_5%, R267 to 453_0402_1% Change R268 pin1 connect to +5VALW Page 33, Change R217 to 18K_0402_1% with BOM structure PM@ Page 35, Add R551,R552, R553, R554 75_0603_1% with BOM structure JAL90@ Add D32 PJDLC05_SOT23-3 Page 38, Add F3 3A_15VDC_SMD2920P300TF/15 Page 49, Add R551,R552, R553, R554 1K_0603_1% with BOM structure 268@ Add L17, L19, L21 0_0805 with BOM structure PM@ Update U38 (ALC268-VB1-GR ) PN:SA00001GD10 for JAW50 C B A Compal Secret Data Security Classification 2008/03/28 Issued Date Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 5 4 3 2 Title Compal Electronics, Inc. Size Document Number Custom Date: KAL90 HW PIR1 Monday, April 27, 2009 Rev 0.1 Sheet 1 53 of 53
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File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No Page Count : 53 Producer : GNU Ghostscript 7.06; modified using iTextSharp 5.0.5 (c) 1T3XT BVBA Title : KALG0- DD2 0427BOM-1 Creator : PScript5.dll Version 5.2.2 Create Date : 4/28/2009 10:36:4 Author : mason_wang Modify Date : 2012:06:09 09:58:38+08:00EXIF Metadata provided by EXIF.tools