QAU20_LA 8441P01_1114_G Compal LA 8441P
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A
B
C
D
E
1
1
Compal Confidential
2
2
QAU20 M/B Schematics Document
Date : 2011/11/08
3
3
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/08/03
Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Cover Page
Size
B
Date:
Document Number
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
E
1
of
46
A
B
C
D
Compal Confidential
E
Memory BUS(DDRIII)
0RGHO1DPH 4$8
)LOH1DPH /$3
,QWHO,Y\%ULGJH
^ϬϬϬϬϰZ:ϭϬ;ϭ͘ϯ',njͿ
1.5V DDRIII 1066/1333/1600 for CR
1.5V DDRIII 1066/1333 for HR
Channel A
(256MX16) X4 chips
2GB/4GB chips
8/93URFHVVRU
)&%*$
1
Page 11
1
Page 4~10
FDI x8
DMI x4
USB3.0
LVDS
/9'6&RQQ
Page 23
HDMI
0LQL+'0,&RQQ
SMBus
&DPHUD)URQW 0
USB
USB
Page 20
1)&
0XUDWD/;5:+)$$
86%&RQQ
Page 26
,QWHO
Page 23
&DPHUD%DFN 0
**36
2
PCIE2
:/$1%70LQL3&,(
Page 22
6DQGLVNL66'
Port 0
+''RQ'RFNLQJ
SATA
$QDORJ0,&$UUD\
7R,2ERDUGFRQQ
6$14
SATA
'RFNLQJ&RQQ
$/& 49&
+'$&RGHF
SLQ%*$
2
6,0&DUG
Page 25
3DQWKHU3RLQW3&+
&DUG5HDGHU
576 ,2ERDUG
Page 24
:RKP
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USB
USB
'RFNLQJ&RQQ
.H\ERDUG
HDA
USB
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Page 29
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Page 12
SPI
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A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
Issued Date
4
2009/08/01
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
C
D
Title
Block Diagrams
Size Document Number
Custom
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
E
2
of
46
A
B
QAZ50 (LA-8101P Ver:0.1)
2011/08/19 Modify
Voltage Rails
Power Plane
1
C
Description
S1
S3
S5
VIN
Adapter power supply (19V)
N/A
N/A
N/A
BATT+
Battery power supply (7.2V)
N/A
N/A
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+VCCSA
Voltage for CPU SA RALL
ON
OFF
OFF
+VGFX_CORE
Core voltage for UMA graphic
ON
OFF
OFF
+0.75VS
+0.75VP to +0.75VS switched power rail for DDR terminator
ON
OFF
OFF
+CHGRTC
BATT+ or Vin to +CHGRTC always on power rail for sequence control
ON
ON
ON*
+RTCVCC
RTC power
ON
ON
ON
+VCCP
+VCCP (1.05V ) power for PCH
ON
OFF
OFF
+1.5V
+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)
ON
ON
OFF
+1.5VS
+1.5VS switched power rail
ON
OFF
OFF
+LG_OUT
SIGNAL
STATE
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
E
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
Voltage for LCD Panel Backlight LED Power
ON
OFF
+1.8VS
(+5VALW ) to 1.8V switched power rail to PCH & GPU
ON
OFF
OFF
+3VALW
+3VALW always on power rail
ON
ON
ON*
+3VALW_EC
+3VALW always to KBC
ON
ON
ON*
+LAN_IO
+3VALW to +LAN_IO power rail for LAN
ON
ON
ON*
+3V_PCH
+3VALW to +3V_PCH power rail for PCH (Short Jumper)
ON
ON
ON*
+3VS
+3VALW to +3VS power rail
ON
OFF
OFF
+5VALW
+5VALWP to +5VALW power rail
ON
ON
ON*
Device
Address
+5V_PCH
+5VALW to +5V_PCH power rail for PCH (Short resister)
ON
ON
ON*
Smart Battery
0001 011X b
+5VS
+5VALW to +5VS switched power rail
ON
OFF
OFF
1
OFF
EC SM Bus1 address
EC SM Bus2 address
2
SMBUS Control Table
SOURCE
EC_SMB_CK1
EC_SMB_DA1
KB9012
EC_SMB_CK2
EC_SMB_DA2
KB9012
PCH_SMBCLK
PCH_SMBDATA
PCH
PCH_SMLCLK
PCH_SMLDATA
PCH (Reserve)
1010 0110b
2011/07/28 Modify
BATT
MINI1
(mSATA)
V
X
X
X
MINI2
(WLan1)
X
X
EC_SMB_CK2
PCH_SMBCLK
EC_SMB_DA2
PCH_SMBDATA
X
O
X
V
CLKOUT DESTINATION
PCI0
PCH_LPBACK
PCI1
PCI_LPC
X
V
V
V
O
X
X
X
X
X
PCI3
None
PCI4
None
SATA
DESTINATION
UHCI0
SATA0
m-SATA,JSSD1
SATA1
None
SATA2
None
SATA3
None
SATA4
None
EHCI1
UHCI2
CLK
DESTINATION
FLEX CLOCKS
CLKOUT_PCIE0
10/100/1G LAN
CLKOUTFLEX0
4
CLKOUTFLEX1
None
CLKOUT_PCIE2
None
CLKOUTFLEX2
None
CLKOUT_PCIE3
CARD READER
CLKOUTFLEX3
None
None
CLKOUT_PCIE6
None
CLKOUT_PCIE7
None
EHCI2
SATA5
None
2011/08/19 Modify
: means Digital Ground
Option
@
CONN@
CR UMA
X
X
USB 3.0
Mini Card(WLAN)
Camera
Test Point (RH274,RH310)
2 External
USB Port
USB/B ( External)
USB/B ( External)
4
USB/B ( External)
None
Issued Date
2009/08/01
Deciphered Date
Compal Electronics, Inc.
2011/10/18
Title
Notes List
Size
C
Date:
B
3
USB/B ( External)
USB/B ( External)
Port
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
4
: means Analog Ground
Security Classification
CLKOUT_PEG_B
UHCI5
UHCI6
Symbol Note :
None
CLKOUT_PCIE5
UHCI4
None
MINI CARD WLAN
CLKOUT_PCIE4
UHCI3
DESTINATION
CLKOUT_PCIE1
2 External
USB Port
USB 2.0 USB 1.1 Port
UHCI1
DIFFERENTIAL
2011/07/12 Check
USB Port Table
None
PCI2
PCH
2
Address
Device
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
3
D
C
D
Document Number
LA-8441P
Rev
0.1
Monday, November 14, 2011
Sheet
E
3
of
46
5
4
3
2
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with max length = 500 mils
- typical impedance = 14.5 mohms
+VCCP
1
D
M2
P6
P1
P10
{14}
{14}
{14}
{14}
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
N3
P7
P3
P11
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
{14}
{14}
{14}
{14}
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
K1
M8
N4
R2
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
{14}
{14}
{14}
{14}
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
K3
M7
P4
T3
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
U7
W11
W1
AA6
W6
V4
Y2
AC9
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
U6
W10
W3
AA7
W7
T4
AA3
AC8
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
U11
FDI0_FSYNC
FDI1_FSYNC
FDI_INT
1
{14} FDI_INT
AA10
AG8
{14} FDI_LSYNC0
{14} FDI_LSYNC1
FDI0_LSYNC
FDI1_LSYNC
2
RC2
24.9_0402_1%
B
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
EDP_COMP
+VCCP
RC86 1
@
2 10K_0402_5%
AF3
AD2
AG11
AG4
AF4
AC1
AA4
AE10
AE6
eDP_AUX#
eDP_AUX
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
eDP
AC3
AC4
AE11
AE7
eDP_COMPIO
eDP_ICOMPO
eDP_HPD#
PEG_COMP
H22
J21
B22
D21
A19
D17
B14
D13
A11
B10
G8
A8
B6
H8
E5
K7
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PCI EXPRESS -- GRAPHICS
AA11
AC12
{14} FDI_FSYNC0
{14} FDI_FSYNC1
G3
G1
G4
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
Intel(R) FDI
+VCCP
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI
C
{14}
{14}
{14}
{14}
D
2
RC1
24.9_0402_1%
UCPU1A
1
K22
K19
C21
D19
C19
D16
C13
D12
C11
C9
F8
C8
C5
H6
F6
K6
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
C
G22
C23
D23
F21
H19
C17
K15
F17
F14
A15
J14
H13
M10
F10
D9
J4
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
F22
A23
D24
E21
G19
B18
K17
G17
E14
C15
K13
G13
K10
G10
D8
K4
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B
IVY-BRIDGE_BGA1023
SA00004SX00
A
A
Compal Secret Data
Security Classification
Issued Date
2010/04/26
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
Size Document Number
Custom
Rev
0.1
LA-8101P
Date:
Monday, November 14, 2011
Sheet
1
4
of
46
5
4
3
2
1
Buffered reset to CPU
+3VS
+VCCP
CC1
0.1U_0402_16V4Z
1
1
NC
Y
BUFO_CPU_RST#
G
A
4
+3VS
D
RC4
43_0402_1%
1
2 BUF_CPU_RST#
XDP_DBRESET#
RC5
1 1K_0402_5%
2
circuit check 10k
1
PLT_RST# 2
@
RC6
0_0402_5%
3
{15,25,28} PLT_RST#
UC1
P
1
RC3
75_0402_5%
2
5
2
D
2
SN74LVC1G07DCKR_SC70-5
1
PROC_DETECT#
RC7
@
PAD
+VCCP
T5
CATERR#
A48
PECI
THERMAL
C49
Processor Pullups
@
RC8
1 62_0402_5% H_PROCHOT#
2
C
{16,28} H_PECI
{28} H_PROCHOT#
RC11
1
RC10
2 H_PROCHOT#_R
56_0402_5%
1 10K_0402_5% H_CPUPWRGD_R
2
H_THEMTRIP#
{16} H_THRMTRIP#
C45
D45
PROCHOT#
BCLK
BCLK#
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
DDR3
MISC
PROC_SELECT#
2
C57
10K_0402_5%
{16} H_SNB_IVB#
PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this
signal to determine if the processor is present
MISC
F49
CLOCKS
UCPU1B
This pin is for compability with future
platforms. A pull up resistor to VCCIO is
required if connected to the DF_TVS strap
on the PCH.
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
C48
1
RC16
2 H_CPUPWRGD_R
0_0402_5%
B46
PM_SYS_PWRGD_BUF 1
RC18
For EMI Request
CC4
1
2 PM_DRAM_PWRGD_R BE45
130_0402_5%
2H_CPUPWRGD
0.1U_0402_16V4Z
BUF_CPU_RST#
D44
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET#
B
CC5
1
2XDP_DBRESET#
0.1U_0402_16V4Z
TCK
TMS
TRST#
JTAG & BPM
H_PM_SYNC_R
2
0_0402_5%
PWR MANAGEMENT
{16} H_CPUPWRGD
1
RC13
AG3
AG1
CLK_CPU_DMI {13}
CLK_CPU_DMI# {13}
RC12 1
RC35 1
2 1K_0402_1%
2 1K_0402_1%
AT30 H_DRAMRST#
BF44
BE43
BG43
+VCCP
H_DRAMRST# {6}
C
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
THERMTRIP#
PRDY#
PREQ#
{14} H_PM_SYNC
J3
H2
TDI
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
N53
N55
L56
L55
J58
M60
L59
K58
G58
E55
E59
G55
G59
H60
J59
J61
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#_R 1 RC17
XDP_BPM#4_R RC19
XDP_BPM#5_R RC20
XDP_BPM#6_R RC21
XDP_BPM#7_R RC22
1
1
1
1
2 0_0402_5%
@
@
@
@
2
2
2
2
XDP_DBRESET#
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
XDP_DBRESET# {14}
CFG12
CFG13
CFG14
CFG15
{7}
{7}
{7}
{7}
B
CC5 near RC17
IVY-BRIDGE_BGA1023
SA00004SX00
DDR3 Compensation Signals
Follow PBL22 LA-7391 PR04
+3VS
Modify
+3V_PCH
2011/10/03
SM_RCOMP0 RC23 2
1
2
2
@
2
2
B
O
A
PM_SYS_PWRGD_BUF
4
3
1
RC28
1
+3V_PCH
@
RC29
39_0402_5%
2
Part Number = SA00003Y000
{9} RUN_ON_CPU1.5VS3#
1 2
200_0402_5%
D
3
Modify
2011/10/03
PU/PD for JTAG signals
+VCCP
XDP_TMS
RC30
2
1 51_0402_5%
XDP_TDI
RC31
2
1 51_0402_5%
XDP_TDO
RC32
2
1 51_0402_5%
XDP_TCK
RC33
2
1 51_0402_5%
XDP_TRST# RC34
2
1 51_0402_5%
P
1
{14} PM_DRAM_PWRGD
A
RC25
200_0402_5%
UC2
74AHC1G09GW_TSSOP5
G
{14} SYS_PWROK
5
RC27
0_0402_5%
1
2
+1.5V_CPU_VDDQ
CC2
0.1U_0402_16V4Z
1
1
RC84
10K_0402_5%
1 140_0402_1%
SM_RCOMP1 RC24 2
1 25.5_0402_1%
SD00000X700
SM_RCOMP2 RC26 2
1 200_0402_1%
S
RUN_ON_CPU1.5VS3#
2
G
@
QC1
2N7002_SOT23
A
Compal Secret Data
Security Classification
Issued Date
2010/4/26
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
Size Document Number
Custom
Rev
0.1
LA-8101P
Date:
Monday, November 14, 2011
Sheet
1
5
of
46
5
4
3
2
UCPU1C
1
UCPU1D
{11} DDR_A_D[0..63]
C
B
{11} DDR_A_BS0
{11} DDR_A_BS1
{11} DDR_A_BS2
BD37
BF36
BA28
{11} DDR_A_CAS#
{11} DDR_A_RAS#
{11} DDR_A_WE#
BE39
BD39
AT41
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
AU36
AV36
AY26
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
BB40
BC41
SA_CS#[0]
SA_CS#[1]
1
2
36.5_0402_1%
1
2
36.5_0402_1%
RC82
SA_ODT[0]
SA_ODT[1]
AY40
BA41
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
AL11
AR8
AV11
AT17
AV45
AY51
AT55
AK55
M_CLK_DDR0 {11}
M_CLK_DDR#0 {11}
DDR_CKE0_DIMMA {11}
M_CLK_DDR1
M_CLK_DDR#1
1
2
RC81
36.5_0402_1%
AT40
AU40
BB26
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
RC83
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
AL4
AL1
AN3
AR4
AK4
AK3
AN4
AR1
AU4
AT2
AV4
BA4
AU3
AR3
AY2
BA3
BE9
BD9
BD13
BF12
BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58
AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59
AM60
AL59
AF61
AH60
+0.75VS
DDR_CS0_DIMMA# {11}
+0.75VS
M_ODT0 {11}
+0.75VS
DDR_A_DQS#[0..7]
{11}
30.1_0402_1%
0.1U_0402_16V4Z
RC87
M_CLK_DDR1
2
CC11
1
2
1
1
M_CLK_DDR#1
2
CC10
2P_0402_50V8C
2 RC88
1
30.1_0402_1%
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
AJ11
AR10
AY11
AU17
AW45
AV51
AT56
AK54
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS[0..7]
{11}
BG35
BB34
BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32
BE37
BA30
BC30
AW41
AY28
AU26
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
DDR_A_MA[0..15] {11}
BG39
BD42
AT22
AV43
BF40
BD45
IVY-BRIDGE_BGA1023
SA00004SX00
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
BA34
AY34
AR22
D
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
SB_CS#[0]
SB_CS#[1]
DDR SYSTEM MEMORY B
D
AG6
AJ6
AP11
AL6
AJ10
AJ8
AL8
AL7
AR11
AP6
AU6
AV9
AR6
AP8
AT13
AU13
BC7
BB7
BA13
BB11
BA7
BA9
BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56
DDR SYSTEM MEMORY A
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
SB_CAS#
SB_RAS#
SB_WE#
BE41
BE47
SB_ODT[0]
SB_ODT[1]
AT43
BG47
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
AL3
AV3
BG11
BD17
BG51
BA59
AT60
AK59
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
SB_BS[0]
SB_BS[1]
SB_BS[2]
BA36
BB36
BF27
C
AM2
AV1
BE11
BD18
BE51
BA61
AR59
AK61
BF32
BE33
BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28
BD43
AT28
AV28
BD46
AT26
AU22
B
IVY-BRIDGE_BGA1023
SA00004SX00
1
+1.5V
RC36
1K_0402_5%
RC37
1K_0402_5%
2
2
D
S
H_DRAMRST#
DDR3_DRAMRST#_R
1
QC2
BSS138_NL_SOT23-3
3
2
{5} H_DRAMRST#
DDR3_DRAMRST# {11}
1
2
G
RC38
4.99K_0402_1%
1
A
@
{9,13} DRAMRST_CNTRL_PCH
RC39
0_0402_5%
1
2
1 RC53
{28} DRAMRST_CNTRL_EC
A
DRAMRST_CNTRL
2
0_0402_5%
1
2
Compal Secret Data
Security Classification
CC3
0.047U_0402_16V4Z
Issued Date
2010/04/26
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
Size Document Number
Custom
Rev
0.1
LA-8101P
Date:
Sheet
Monday, November 14, 2011
1
6
of
46
5
4
3
2
1
CFG Straps for Processor
1
CFG2
2
RC40
1K_0402_1%
D
D
PEG Static Lane Reversal - CFG2 is for the 16x
1: Normal Operation; Lane #
socket pin map definition
CFG2
*
definition matches
0:Lane Reversed
1
CFG4
+CPU_CORE
RC44
1
2
RC45
+VGFX_CORE
1
2
RC43
VCC_VAL_SENSEH43
249.9_0402_1%
VSS_VAL_SENSEK43
1
49.9_0402_1%
2 49.9_0402_1% VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
1
49.9_0402_1%
1
RC9
F48
G48
RC47
1K_0402_1%
@
BA19
AV19
AT21
BB21
BB19
AY21
BA22
AY22
AU19
AU21
BD21
BD22
BD25
BD26
BG22
BE22
BG26
BE26
BF23
BE24
M13
M14
U14
W14
P13
*
CFG4
C
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
CFG6
RSVD39
RSVD40
VCC_VAL_SENSE
VSS_VAL_SENSE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VCC_DIE_SENSE
RSVD47
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD6
RSVD7
DC_TEST_A4
DC_TEST_C4
DC_TEST_D3
DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61
DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58
DC_TEST_BG4
DC_TEST_BG3
DC_TEST_BE3
DC_TEST_BG1
DC_TEST_BE1
DC_TEST_BD1
1
H48
K48
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
Display Port Presence Strap
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
AT49
K24
CFG5
@ RC48
1K_0402_1%
AH2
AG13
AM14
AM15
@ RC49
1K_0402_1%
N50
A4
C4
D3
D1
A58
A59
C59
A61
C61
D61
BD61
BE61
BE59
BG61
BG59
BG58
BG4
BG3
BE3
BG1
BE1
BD1
PCIE Port Bifurcation Straps
DC_TEST_C4_D3
These pins are for solder joint
reliability and non-critical to
function. For BGA only.
DC_TEST_A59_C59
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG[6:5]
*10: x8, x8 - Device 1 function 1 enabled ; function 2
B
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DC_TEST_A61_C61
DC_TEST_BE59_BE61
DC_TEST_BG59_BG61
CFG7
DC_TEST_BE3_BG3
@RC50
@
RC50
1K_0402_1%
DC_TEST_BE1_BG1
2
2
B
RC46
1K_0402_1%
@
2
1
CPU_RSVD6
CPU_RSVD7
T25
2
0_0402_5%
H45
K45
N42
L42
L45
L47
1
RC42
RSVD30
RSVD31
RSVD32
RSVD33
CLK_RES_ITP {13}
CLK_RES_ITP# {13}
1
{5}
{5}
{5}
{5}
N59
N58
2
T8
T14
T15
T16
CFG12
CFG13
CFG14
CFG15
T17
T18
BCLK_ITP
BCLK_ITP#
2
C
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RC41
1K_0402_1%
@
1
T11
B50
C51
B54
D53
A51
C53
C55
H49
A55
H51
K49
K53
F53
G53
L51
F51
D52
L53
RESERVED
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
T9
T6
2
UCPU1E
IVY-BRIDGE_BGA1023
SA00004SX00
PEG DEFER TRAINING
CFG7
*
1: (Default) PEG Train immediately following
xxRESETB de assertion
0: PEG Wait for BIOS for training
A
Compal Secret Data
Security Classification
Issued Date
2010/04/26
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
A
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
Size Document Number
Custom
Date:
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
7
of
46
4
3
UCPU1F
2
POWER
+VCCP
ULV type CPU
18A
+CPU_CORE
AF46
AG48
AG50
AG51
AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15
VCCIO50
VCCIO51
W16
W17
D
C
+VCCP
1
RC51
1
2
RC52
75_0402_5%
@
2
0_0805_5%
VCCIO_SEL
BC22
Voltage selection for VCCIO: For Huron
River platforms, this pin must be pulled high
on the motherboard.
VCCP_PWRCTRL_R
choose low or high
+VCCP
+VCCP
+1.05VS_VCCPQ
B
AM25
AN22
RC55
130_0402_5%
1
2
0_0805_5%
2
1U_0402_6.3V6K
RC56
75_0402_5%
SVID
2
1
CC73
+VCCP
1
VCCPQE[1]
VCCPQE[2]
RC54
1
B
VCCIO[1]
VCCIO[3]
VCCIO[4]
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCIO[9]
VCCIO[10]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
+VCCP
QUIET
RAILS
C
VCC[1]
VCC[2]
VCC[3]
VCC[4]
VCC[5]
VCC[6]
VCC[7]
VCC[8]
VCC[9]
VCC[10]
VCC[11]
VCC[12]
VCC[13]
VCC[14]
VCC[15]
VCC[16]
VCC[17]
VCC[18]
VCC[19]
VCC[20]
VCC[21]
VCC[22]
VCC[23]
VCC[24]
VCC[25]
VCC[26]
VCC[27]
VCC[28]
VCC[29]
VCC[30]
VCC[31]
VCC[32]
VCC[33]
VCC[34]
VCC[35]
VCC[36]
VCC[37]
VCC[38]
VCC[39]
VCC[40]
VCC[41]
VCC[42]
VCC[43]
VCC[44]
VCC[45]
VCC[46]
VCC[47]
VCC[48]
VCC[49]
VCC[50]
VCC[51]
VCC[52]
VCC[53]
VCC[54]
VCC[55]
VCC[56]
VCC[57]
VCC[58]
VCC[59]
VCC[60]
VCC[61]
VCC[62]
VCC[63]
VCC[64]
VCC[66]
VCC[67]
VCC[68]
VCC[69]
VCC[70]
VCC[71]
VCC[72]
VCC[73]
VCC[74]
VCC[75]
VCC[76]
CORE SUPPLY
A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38
PEG IO AND DDR IO
28A
D
1
2
5
VIDALERT#
VIDSCLK
VIDSOUT
A44
B43
C44
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
RC57 1
RC58 1
RC59 1
2 43_0402_1%
2 0_0402_5%
2 0_0402_5%
VR_SVID_ALRT# {43}
VR_SVID_CLK {43}
VR_SVID_DATA {43}
+CPU_CORE
RC63
AN16 VCCIO_SENSE_R
AN17
2
2
0_0402_5%
0_0402_5%
VCCSENSE {43}
VSSSENSE {43}
1
RC65 1
2
+VCCP
10_0402_1%
0_0402_5%
2
RC64
100_0402_1%
VCCIO_SENSE {39}
2
2
VCCIO_SENSE
VSS_SENSE_VCCIO
A
F43 VCCSENSE_R RC61 1
G43 VSSSENSE_R RC62 1
Place the PU
resistors close to CPU
1
VCC_SENSE
VSS_SENSE
2
100_0402_1%
1
SENSE LINES
1
RC60
10_0402_1%
RC66
SD034100A80
Place the PU
resistors close to VR
A
IVY-BRIDGE_BGA1023
SA00004SX00
Compal Secret Data
Security Classification
Issued Date
2010/04/26
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
Size Document Number
Custom
Rev
0.1
LA-8101P
Date:
Monday, November 14, 2011
Sheet
1
8
of
46
5
4
3
2
1
+V_SM_VREF should
have 20 mil trace width
+1.5V_CPU_VDDQ
+1.5V
+V_SM_VREF_CNT
2
QC9
2
G
{6,13} DRAMRST_CNTRL_PCH
1
2
D
+VREF0
+VREFB
3
S BSS138_NL_SOT23-3
0_0402_5%~D 2
@
1 RC115
0_0402_5%~D 2
@
1 RC116
1
1
BE7 +V_DDR_REFA_R
BG7 +V_DDR_REFB_R
1
VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
AY43
2
2
3
2
1
2
1
2
1
2
1
2
1
2
CC99
10U_0603_6.3V6M
2
1
CC98
10U_0603_6.3V6M
2
1
CC97
10U_0603_6.3V6M
2
1
CC96
10U_0603_6.3V6M
2
1
CC95
10U_0603_6.3V6M
2
1
CC94
10U_0603_6.3V6M
2
1
CC93
10U_0603_6.3V6M
2
1
CC103
10U_0603_6.3V6M
2
1
1U_0402_6.3V6K
CC102
2
1
1U_0402_6.3V6K
CC101
2
1
1U_0402_6.3V6K
CC92
2
1
1U_0402_6.3V6K
CC91
2
1
1U_0402_6.3V6K
CC90
1
1U_0402_6.3V6K
CC89
1
+
CC100
330U_D2_2V_Y
2
C
+1.5V_CPU_VDDQ Source
+1.5V
QC4
AON7212L_DFN8-5
+1.5V_CPU_VDDQ
1
2
3
1
+VSB
+3VALW
5
RC70
100K_0402_5%
RC71
470_0603_5%
2
1
- 1.5V RAILS
DRAMRST_CNTRL_PCH
2
G
5A
1U_0402_6.3V6K
CC88
DDR3
QC10 D
RC117
1K_0402_1%
@
BSS138_NL_SOT23-3 S
+1.5V_CPU_VDDQ
AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33
1U_0402_6.3V6K
CC87
VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]
VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]
1U_0402_6.3V6K
CC86
RC72
100K_0402_5%
RUN_ON_CPU1.5VS3
1
D
2
SB00000AR10
2N7002DWH_SOT363-6
QC5B
RC73
330K_0402_5%
+1.5V_CPU_VDDQ
4
@ RC75
0_0402_5%
1
2
SUSP#
5
6
{28,31,39,40,41}
RUN_ON_CPU1.5VS3#
2
1
{28} CPU1.5V_S3_GATE
RC74
0_0402_5%
1
2
1
C
SM_VREF
RC118
1K_0402_1%
@
GRAPHICS
Ʉ
VAXG[1]
VAXG[2]
VAXG[3]
VAXG[4]
VAXG[5]
VAXG[6]
VAXG[7]
VAXG[8]
VAXG[9]
VAXG[10]
VAXG[11]
VAXG[12]
VAXG[13]
VAXG[14]
VAXG[15]
VAXG[16]
VAXG[17]
VAXG[18]
VAXG[19]
VAXG[20]
VAXG[21]
VAXG[22]
VAXG[23]
VAXG[24]
VAXG[25]
VAXG[26]
VAXG[27]
VAXG[28]
VAXG[29]
VAXG[30]
VAXG[31]
VAXG[32]
VAXG[33]
VAXG[34]
VAXG[35]
VAXG[36]
VAXG[37]
VAXG[38]
VAXG[39]
VAXG[40]
VAXG[41]
VAXG[42]
VAXG[43]
VAXG[44]
VAXG[45]
VAXG[46]
VAXG[47]
VAXG[48]
VAXG[49]
VAXG[50]
VAXG[51]
VAXG[52]
VAXG[53]
VAXG[54]
VAXG[55]
VAXG[56]
1U_0402_6.3V6K
CC85
AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46
N45
P47
P48
P50
P51
P52
P53
P55
P56
P61
T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61
3
Ʉ
Can connect to GND if motherboard only
supports external graphics and if GFX VR is not
stuffed in a common motherboard design,
VAXG can be left floating in a common
motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed
D
POWER
26A
1
UCPU1G
RC69
1K_0402_1%
@
1
RUN_ON_CPU1.5VS3
2
+VGFX_CORE
2
1 0.1U_0402_10V7K
1
2
QC6
2
G
1
CC118
RUN_ON_CPU1.5VS3#
S
3
CC75
D
+V_SM_VREF
3
@ QC3
AP2302GN-HF_SOT23-3
RC89
1K_0402_1%
4
1 0.1U_0402_10V7K
1
2
2
CC74
2
+1.5V
1
+1.5V_CPU_VDDQ
RC68
1K_0402_1%
@
2
RC85
1K_0402_1%
1
1
RC67
0_0402_5%
2
1
@
SB570020110
2N7002E-T1-E3_SOT23-3
2
0.1U_0402_16V4Z
QC5A
SB00000AR10
RUN_ON_CPU1.5VS3#
{5}
Follow DG 0.71 page 6
2N7002DWH_SOT363-6
VAXG_SENSE
VSSAXG_SENSE
2
2
1
2
6A
+VCCSA
L17
L21
N16
N20
N22
P17
P20
R16
R18
R21
U15
V16
V17
V18
V21
W20
VCCPLL[1]
VCCPLL[2]
VCCPLL[3]
VCCSA[1]
VCCSA[2]
VCCSA[3]
VCCSA[4]
VCCSA[5]
VCCSA[6]
VCCSA[7]
VCCSA[8]
VCCSA[9]
VCCSA[10]
VCCSA[11]
VCCSA[12]
VCCSA[13]
VCCSA[14]
VCCSA[15]
VCCSA[16]
IVY-BRIDGE_BGA1023
SA00004SX00
A
SENSE LINES
+VCCSA
1
CC122
1U_0402_6.3V6K
+
CC121
1U_0402_6.3V6K
1
CC120
BB3
BC1
BC4
VCCSA VID
lines
+1.8VS_VCCPLL
SA RAIL
RC77
0_0805_5%
2
330U_D2_2VM_R6M
1
1.8V RAIL
+1.8VS
VID[0]
0
0
1
1
AM28
AN26
2
SENSE
LINES
F45
G45
{43} VCC_AXG_SENSE
{43} VSS_AXG_SENSE
B
QUIET RAILS
RC76
0_0603_5%
VCCDQ[1]
VCCDQ[2]
1U_0402_6.3V6K
1
B
2
CC119
VDDQ_SENSE
VSS_SENSE_VDDQ
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VID[1]
0
1
0
1
BC43
BA43
U10 VCCSA_SENSE
1
@ RC78
2
0_0402_5%
RC79 2 VCCSA_VID0
D48 0_0402_5%
1
D49
1
2 VCCSA_VID1
RC80 0_0402_5%
2011
Yes
Yes
No
No
0.90 V
0.80 V
0.725 V
0.675 V
VCCSA_VID0
VCCSA_VID1
{38}
{38}
2012
Yes
Yes
Yes
Yes
A
Compal Secret Data
Security Classification
Issued Date
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
5
4
3
2
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
9
of
46
5
4
3
2
1
UCPU1H
UCPU1I
C
B
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13
BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53
BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35
D4
D40
D43
D46
D50
D54
D58
D6
E25
E29
E3
E35
E40
F13
F15
F19
F29
F35
F40
F55
G51
G6
G61
H10
H14
H17
H21
H4
H53
H58
J1
J49
J55
K11
K21
K51
K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61
M11
M15
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS
NCTF
D
A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53
A9
AA1
AA13
AA50
AA51
AA52
AA53
AA55
AA56
AA8
AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46
AC6
AD17
AD20
AD4
AD61
AE13
AE8
AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61
AG7
AH4
AH58
AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48
AJ7
AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61
AM13
AM20
AM22
AM26
AM30
AM34
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
D
C
A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61
B
IVY-BRIDGE_BGA1023
SA00004SX00
A
A
Compal Secret Data
Security Classification
IVY-BRIDGE_BGA1023
SA00004SX00
2010/04/26
Issued Date
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
Size
A3
Date:
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
10
of
46
5
4
3
2
1
DDR_A_MA[0..15]
{6} DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
{6} DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
{6} DDR_A_DQS[0..7]
DDR_A_D[0..63]
{6} DDR_A_D[0..63]
D
D
+VREF0
+VREF0
+VREF1
+VREF1
+VREF0
+VREF1
+VREF0
+VREF1
UD2
{6}
{6}
{6}
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M3
N9
M4
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
{6} M_CLK_DDR0
{6} M_CLK_DDR#0
{6} DDR_CKE0_DIMMA
{6}
M_ODT0
{6} DDR_CS0_DIMMA#
{6} DDR_A_RAS#
{6} DDR_A_CAS#
{6} DDR_A_WE#
M_CLK_DDR0
M_CLK_DDR#0
DDR_CKE0_DIMMA
J8
K8
K10
M_ODT0
DDR_CS0_DIMMA#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#
K2
L3
J4
K4
L4
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE
ODT
CS
RAS
CAS
WE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C
DDR_A_DQS0
DDR_A_DQS1
F4
C8
DDR_A_DM0
DDR_A_DM1
E8
D4
DDR_A_DQS#0
DDR_A_DQS#1
G4
B8
DDR3_DRAMRST#
{6} DDR3_DRAMRST#
240_0402_1%
240_0402_1%1
T3
2 R225
L9
J2
L2
J10
L10
DDR_A_MA15
M8
DQSL
DQSU
DML
DMU
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
D8
C4
C9
C3
A8
A3
B9
A4
DDR_A_D15
DDR_A_D12
DDR_A_D14
DDR_A_D8
DDR_A_D10
DDR_A_D13
DDR_A_D11
DDR_A_D9
1
CD3
2
B3
D10
G8
K3
K9
N2
N10
R2
R10
CD4
1
2
+1.5V
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M3
N9
M4
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0_DIMMA K10
M_ODT0
K2
DDR_CS0_DIMMA# L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
A2
A9
C2
C10
D3
E10
F2
H3
H10
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
DDR_A_DQS2
DDR_A_DQS3
F4
C8
DDR_A_DM2
DDR_A_DM3
E8
D4
DDR_A_DQS#2
DDR_A_DQS#3
G4
B8
DDR3_DRAMRST#
1
2 RD1
240_0402_1%
T3
L9
J2
L2
J10
L10
B2
B10
D2
D9
E3
E9
F10
G2
G10
DDR_A_MA15
M8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
NC
E4
F8
F3
F9
H4
H9
G3
H8
DDR_A_D19
DDR_A_D17
DDR_A_D18
DDR_A_D23
DDR_A_D21
DDR_A_D20
DDR_A_D22
DDR_A_D16
D8
C4
C9
C3
A8
A3
B9
A4
DDR_A_D27
DDR_A_D30
DDR_A_D25
DDR_A_D29
DDR_A_D31
DDR_A_D24
DDR_A_D26
DDR_A_D28
M9
H2
1
CD5
2
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B3
D10
G8
K3
K9
N2
N10
R2
R10
CD6
1
2
+1.5V
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M3
N9
M4
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0_DIMMA K10
A2
A9
C2
C10
D3
E10
F2
H3
H10
M_ODT0
K2
DDR_CS0_DIMMA# L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
DDR_A_DQS4
DDR_A_DQS5
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
F4
C8
DDR_A_DM4
DDR_A_DM5
E8
D4
DDR_A_DQS#4
DDR_A_DQS#5
G4
B8
DDR3_DRAMRST#
1
B2
B10
D2
D9
E3
E9
F10
G2
G10
2 RD2
240_0402_1%
L9
J2
L2
J10
L10
DDR_A_MA15
M8
96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
T3
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
NC
NC
NC
NC
NC
UD4
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
E4
F8
F3
F9
H4
H9
G3
H8
DDR_A_D39
DDR_A_D34
DDR_A_D35
DDR_A_D38
DDR_A_D32
DDR_A_D37
DDR_A_D36
DDR_A_D33
D8
C4
C9
C3
A8
A3
B9
A4
DDR_A_D47
DDR_A_D41
DDR_A_D43
DDR_A_D44
DDR_A_D42
DDR_A_D45
DDR_A_D46
DDR_A_D40
B3
D10
G8
K3
K9
N2
N10
R2
R10
M9
H2
1
CD7
2
CD8
1
2
0.1U_0402_16V4Z
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
DDR_A_D6
DDR_A_D1
DDR_A_D7
DDR_A_D2
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D0
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
0.1U_0402_16V4Z
2
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
E4
F8
F3
F9
H4
H9
G3
H8
VREFCA
VREFDQ
0.1U_0402_16V4Z
1
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
CD2
0.1U_0402_16V4Z
1
CD1
VREFCA
VREFDQ
0.1U_0402_16V4Z
M9
H2
UD3
M9
H2
0.1U_0402_16V4Z
UD1
+1.5V
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
N4
P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
M3
N9
M4
VREFCA
VREFDQ
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
F4
C8
DDR_A_DM6
DDR_A_DM7
E8
D4
DDR_A_DQS#6
DDR_A_DQS#7
G4
B8
DDR3_DRAMRST#
B2
B10
D2
D9
E3
E9
F10
G2
G10
DML
DMU
RESET
L9
ZQ
J2
L2
J10
L10
DDR_A_MA15
NC
NC
NC
NC
M8
96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
DDR_A_D59
DDR_A_D56
DDR_A_D58
DDR_A_D57
DDR_A_D63
DDR_A_D61
DDR_A_D62
DDR_A_D60
+1.5V
C
B2
B10
D2
D9
E3
E9
F10
G2
G10
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
D8
C4
C9
C3
A8
A3
B9
A4
A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQSL
DQSU
DDR_A_D54
DDR_A_D49
DDR_A_D55
DDR_A_D51
DDR_A_D53
DDR_A_D48
DDR_A_D50
DDR_A_D52
A2
A9
C2
C10
D3
E10
F2
H3
H10
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQSL
DQSU
T3
2 RD3
240_0402_1%
1
ODT
CS
RAS
CAS
WE
E4
F8
F3
F9
H4
H9
G3
H8
B3
D10
G8
K3
K9
N2
N10
R2
R10
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CK
CK
CKE
M_ODT0
K2
DDR_CS0_DIMMA# L3
DDR_A_RAS#
J4
DDR_A_CAS#
K4
DDR_A_WE#
L4
DDR_A_DQS6
DDR_A_DQS7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
M_CLK_DDR0
J8
M_CLK_DDR#0
K8
DDR_CKE0_DIMMA K10
A2
A9
C2
C10
D3
E10
F2
H3
H10
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
96-BALL
SDRAM DDR3L
H5TC4G63MFR-PBA_FBGA96
B
B
+0.75VS
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
RD11
RD10
RD12
RD13
RD14
RD15
RD16
RD17
2
2
2
2
2
2
2
2
1
+VREF0
RD19
2
30.1_0402_1%
30.1_0402_1%
2
RD8
1K_0402_1%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
1
RD9
1K_0402_1%
2
3
2
2
1
2
Compal Secret Data
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
1
A
Security Classification
Issued Date
1
CD38
0.1U_0402_16V4Z
LA-8441P
5
+VREF1
+VREF1
RD18
5
6
7
8 36_0804_8P4R_5%
RPD6
RPD7
4
36_0404_4P2R_5%
3
1
1
1
1
1
1
1
1
RD5
1K_0402_1%
+VREF0
1
5
6
7
8 36_0804_8P4R_5%
RPD5
1
A
+1.5V
RD4
1K_0402_1%
2.2U_0603_6.3V6K
CD35
1
2
CD37
1.8P_0402_50V8
0.1U_0402_16V4Z
CD34
DDR_A_BS1
2
2.2U_0603_6.3V6K
CD33
4
3
2
1
+1.5V
1
M_CLK_DDR#0
0.1U_0402_16V4Z
CD32
DDR_A_MA13
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
M_CLK_DDR0
1
4
3
2
1
2
2
DDR_A_MA5
DDR_A_MA11
DDR_A_MA9
DDR_A_MA14
1
2
5
6
7
8 36_0804_8P4R_5%
RPD4
2
1
4
3
2
1
1
2
DDR_A_MA3
DDR_A_MA1
DDR_A_MA2
DDR_A_MA4
2
1
5
6
7
8 36_0804_8P4R_5%
RPD3
1
2
4
3
2
1
2
1
DDR_A_BS0
DDR_A_MA12
DDR_A_MA0
DDR_A_MA15
1
CD12
1U_0402_6.3V6K
2
5
6
7
8 36_0804_8P4R_5%
RPD2
CD11
1U_0402_6.3V6K
1
10U_0603_6.3V6M
2
CD31
1
10U_0603_6.3V6M
2
CD30
1U_0402_6.3V6K
2
1
10U_0603_6.3V6M
1
CD29
2
1U_0402_6.3V6K
2
1
CD28
2
1
CD27
2 SGA00004400
1
1U_0402_6.3V6K
CD24
330U_B2_2.5VM_R15M
CD26
+
1U_0402_6.3V6K
2
CD25
2
1
CD23
0.1U_0402_16V7K
2
1
CD22
0.1U_0402_16V7K
2
1
CD21
0.1U_0402_16V7K
2
1
CD20
0.1U_0402_16V7K
2
1
CD19
10U_0603_6.3V6M
2
1
CD18
10U_0603_6.3V6M
2
1
CD17
10U_0603_6.3V6M
2
1
CD16
10U_0603_6.3V6M
1
CD15
10U_0603_6.3V6M
2
CD14
10U_0603_6.3V6M
1
1
5
6
7
8 36_0804_8P4R_5%
RPD1
4
3
2
1
CD10
1U_0402_6.3V6K
+1.5V
4
3
2
1
DDR_A_WE#
DDR_A_MA10
DDR_CS0_DIMMA#
DDR_A_BS2
CD9
1U_0402_6.3V6K
+0.75VS
DDR_A_RAS#
DDR_A_CAS#
M_ODT0
DDR_CKE0_DIMMA
Title
DDRIII ON BOARD CHIPS
Size
D
Document Number
Date:
Monday, November 14, 2011
1
Rev
0.1
Sheet
11
of
46
5
4
3
2
1
PCH_RTCX1
4
1
OSC
NC
NC
3
YH1
2
2
CH2
32.768KHZ_12.5PF_Q13MC14610002
18P_0402_50V8J
D
1
PCH_RTCX2
2
10M_0402_5%
OSC
1
RH115
1
CH3
18P_0402_50V8J
+RTCVCC
2
RH116 1
D
SM_INTRUDER#
2
1M_0402_5%
UH1A
far away hot spot
PCH_SRTCRST#
G22
SM_INTRUDER#
K22
CLRP2
PCH_INTVRMEN
SHORT PADS
ME CMOS
CLP1 & CLP2 place near DIMM
INTRUDER#
C17
INTVRMEN
2
{30}
G
HDA_SPKR
N34
HDA_SYNC
L34
HDA_SPKR
T10
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SYNC
1
HDA_SDIN0
1
G34
1
@
2
0_0402_5%
+3VS
C34
2
10K_0402_5% HDA_SDOUT
RH148
1
{27} NFC_EN_1V8
1
HDA_SDOUT
2
33_0402_5%
RH125
SPKR
HDA_RST#
HDA_SDIN0
HDA_SDIN2
HDA_SDIN3
A36
HDA_SDO
HDA_DOCK_EN# / GPIO33
H7
JTAG_TMS
SATAICOMPO
PCH_JTAG_TDI
K5
PCH_JTAG_TDO
H1
1
RH150
T3
SPI_CLK
PCH_SPI_CS#
Y14
SPI_CS0#
RH135
100_0402_1%
T1
SPI_CS1#
PCH_SPI_SI
V4
SPI_MOSI
PCH_SPI_SO
U3
SPI_MISO
PCH_JTAG_TCK
V5
SATAICOMPI
LPC_FRAME#
SERIRQ
{28}
SERIRQ
{28}
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
{26}
{26}
{26}
{26}
iSSD
AM10
AM8
AP11
AP10
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
{29}
{29}
{29}
{29}
mSATA
AD7
AD5
AH5
AH4
+RTCVCC
PCH_INTVRMEN RH126
2
1 330K_0402_5%
@
C
1 330K_0402_5%
+1.05VS_VCC_SATA
Y11
Y10
VRM enable
VRM disable
SATA_COMP
1
RH130
2
37.4_0402_1%
2
49.9_0402_1%
+3VS
PCH_GPIO19
BBS_BIT0_R RH16
+1.05VS_SATA3
AB12
SATA3COMPI
AB13
SATA3_COMP
1
RH132
AH1
RBIAS_SATA3
1
RH137
2
750_0402_1%
1 10K_0402_5%
2
SERIRQ
RH131
2
1 10K_0402_5%
PCH_GPIO21
RH136
2
1 10K_0402_5%
SATA_LED#
RH138
2
1 10K_0402_5%
+3VS
P3
SATA_LED#
SATA0GP / GPIO21
V14
PCH_GPIO21
SATA1GP / GPIO19
P1
BBS_BIT0_R
SATALED#
T39
HDA_SPKR RH139
@
T35 PAD~D
@
2
1 1K_0402_5%
LOW=Default
Reboot
*HIGH=No
PANTHER-POINT_FCBGA989
B
HDA_SDO
SPI ROM FOR ME ( 4MByte )
@
RH151
1
2
INTVRMEN
Part Number = SA00004NQ20
@
CH1
2
1
PCH_INTVRMEN RH124
* HL烉
烉Integrated
Integrated
SATA3RCOMPO
SATA3RBIAS
{28}
{28}
{28}
{28}
AM3
AM1
AP7
AP5
Y3
Y1
AB3
AB1
PCH_JTAG_TMS
PCH_JTAG_TDI
LPC_FRAME#
Y7
Y5
AD3
AD1
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
PCH_SPI_CLK
D36
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
E36
K36
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
JTAG_TCK
JTAG_TDO
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
AB8
AB10
AF3
AF1
J3
JTAG_TDI
C38
A38
B37
C37
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
PCH_JTAG_TCK
1
2
51_0402_5%
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
HDA_DOCK_RST# / GPIO13
@ RH129
200_0402_5%
RH134
100_0402_1%
2
2
RH133
100_0402_1%
C36
N32
1
PCH_JTAG_TMS
1
1
PCH_JTAG_TDO
@ RH128
200_0402_5%
2
@ RH127
200_0402_5%
2 PCH_GPIO33
0_0402_5%
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
HDA_SDIN1
A34
+3V_PCH
1
+3V_PCH
1
+3V_PCH
2
HDA_SDOUT
2
0_0402_5%
SERIRQ
HDA_SYNC
SPI
{30} HDA_SDOUT_AUDIO
B
1
RH123
2
ME_EN
RH158
2
{28}
LDRQ0#
LDRQ1# / GPIO23
HDA_BCLK
2
1
C
RH122
FWH4 / LFRAME#
SRTCRST#
SATA
SB000002X00
{30}
BSS138W-7-F_SOT323-3
RH13
1M_0402_5%
RTCRST#
D
S
HDA_BIT_CLK
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
2
1
1
QH1
3
2 HDA_SYNC_R
RH121
33_0402_5%
D20
+5VS
1
{30} HDA_SYNC_AUDIO
PCH_RTCRST#
RTCX2
IHDA
RH120
HDA_RST#
2
33_0402_5%
C20
JTAG
HDA_BIT_CLK
2
33_0402_5%
1
{30} HDA_RST_AUDIO#
2
2
RH119
1
{30} HDA_BITCLK_AUDIO
PCH_RTCX2
RTCX1
SATA 6G
CH5
1U_0603_10V4Z
A20
CMOS
CLRP1
SHORT PADS
2
CH4
1U_0603_10V4Z
1
2
RH117 20K_0402_5%
1
2
RH118 20K_0402_5%
PCH_RTCX1
1
1
RTC
+RTCVCC
+3V_PCH
ME debug mode , this signal has a weak internal PD
2PCH_SPI_CLK
33_0402_5%
HDA_SDOUT
L=>security measures defined in the Flash
Descriptor will be in effect (default)
22P_0402_50V8J
@
2
1 1K_0402_5%
= Disabled
*Low
High = Enabled
H=>Flash Descriptor Security will be overridden
Reserve for EMI please close to U48
RH140
HDA_SYNC
+3V_PCH
2
SPI ROM FOR ME
RH141
3.3K_0402_5%
( 4MByte )
+3V_PCH
+3V_PCH
1
@
This signal has a weak internal pull-down
On Die PLL VR is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
0_0402_5%
PCH_SPI_CS#
RH142 1
2
PCH_SPI_SO
RH143 1
2 33_0402_5%
1
2
+3V_PCH
RH145
3.3K_0402_5%
SPI BIOS Pinout
(1)CS#
(2)DO
(3)WP#
(4)GND
A
UH2
PCH_SPI_CS#_R 1
PCH_SPI_SO_R 2
PCH_SPI_WP#
3
4
CS#
DO
WP#
GND
VCC
HOLD#
CLK
DI
+3VLP
+RTCVCC
8
7
6
5
PCH_SPI_HOLD#
2
PCH_SPI_CLK_R
2
RH146
PCH_SPI_SI_R
1
W25Q32BVSSIG_SO8
33_0402_5%
PCB Footprint = W25Q32BVSSIG_SO8
1 RH144 3.3K_0402_5%
1 PCH_SPI_CLK
33_0402_5%
2 PCH_SPI_SI
RH147
1
HDA_SYNC
CH6
0.1U_0402_16V4Z
1
W=20mils R171
2
RH149
2
1 1K_0402_5%
2
0_0402_5%
Delete RTC Battery add 0ohm
(5)DIO
(6)CLK
(7)HOLD#
(8)VCC
A
W25X32
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH (1/8) SATA,HDA,SPI, LPC
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
1
Sheet
12
of
46
5
4
3
2
1
+3V_PCH
PCH_HOT#
SMBDATA
SMBCLK
SML0CLK
UH1B
+3VS
SML1ALERT# / PCHHOT# / GPIO74
SML1CLK / GPIO58
SML1DATA / GPIO75
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CL_CLK1
MiniWLAN (Mini Card)--->
+3VS
RH178
RH179
RH180
1 0_0402_5%
1 0_0402_5%
1 10K_0402_5%
2
2
2
J2
PCIE_MINI1#
PCIE_MINI1
MINI1CLK_REQ#
{22} MINI1_CLKREQ#
AB49
AB47
PCIECLKRQ0# / GPIO73
M1
AA48
AA47
2 RH174
+3VS
1 10K_0402_5%
V10
CLKOUT_PCIE1N
CLKOUT_PCIE1P
DRAMRST_CNTRL_PCH
A12
DRAMRST_CNTRL_PCH
C8
SML0CLK
DRAMRST_CNTRL_PCH
{6,9}
G12 SML0DATA
PCH_HOT#
C13
E14
PCH_HOT#
{28}
SML1CLK
CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M
M16 SML1DATA
20090512
add double mosfet prevent
ATI M92 electric leakage
M7
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
PCIECLKRQ1# / GPIO18
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
PCIECLKRQ2# / GPIO20
A8
Y43
Y45
+3V_PCH
RH181
2
1 10K_0402_5%
RH182 1
2 10K_0402_5%
L12
V45
V46
+3V_PCH
L14
AB42
AB40
B
+3V_PCH
RH183 1
2 10K_0402_5%
E6
V40
V42
+3V_PCH
RH185
2 10K_0402_5%
1
T13
XTAL25_IN
2
1M_0402_5%
+3V_PCH
YH2
1
2
{7} CLK_RES_ITP#
{7} CLK_RES_ITP
2
RH189 1
RH190
RH191
2
2
GPIO46
2 10K_0402_5%
@
@
1 0_0402_5%
1 0_0402_5%
CLK_BCLK_ITP#
CLK_BCLK_ITP
25MHZ_20PF_7A25000012
1
CH13
2
18P_0402_50V8J
CH12
18P_0402_50V8J
1
V38
V37
XTAL25_OUT
1
RH187
K12
AK14
AK13
@
RH193
2
33_0402_5%
1
1
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH
PCH_GPIO47
M10
10K_0402_5%
2
1
C
+3V_PCH
AB37
AB38
+3VS
AV22 CLK_CPU_DMI#_PCH
AU22 CLK_CPU_DMI_PCH
RH172
RH173
2
2
1 0_0402_5% CLK_CPU_DMI#
1 0_0402_5% CLK_CPU_DMI
CLKIN_GND1_N
CLKIN_GND1_P
PCIECLKRQ3# / GPIO25
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKOUT_PCIE4N
CLKOUT_PCIE4P
AM12
AM13
RH208
2.2K_0402_5%
SB00000AR10
2N7002DWH_SOT363-6
BF18 CLKIN_DMI#
BE18 CLKIN_DMI
6
CLKOUT_PCIE5N
CLKOUT_PCIE5P
REFCLK14IN
PCIECLKRQ5# / GPIO44
CLKIN_PCILOOPBACK
QH3A
G24 CLKIN_DOT96#
E24 CLKIN_DOT96
RH200 @
1
2
0_0402_5%
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
XTAL25_IN
XTAL25_OUT
CLK_PCH_14M
4
PCH_SML1DATA
{28}
CLK_PCI_LPBACK
{15}
XTAL25_IN
XTAL25_OUT
B
PEG_B_CLKRQ# / GPIO56
+3VS
XCLK_RCOMP
{28}
2N7002DWH_SOT363-6
QH3B
RH232
1
2
0_0402_5%
@
H45 CLK_PCI_LPBACK
V47
V49
PCH_SML1CLK
3
AK7 CLKIN_SATA#
AK5 CLKIN_SATA
K45
RH198
2.2K_0402_5%
1
BJ30 CLKIN_DMI2#
BG30 CLKIN_DMI2
SML1DATA
CLKIN_SATA_N
CLKIN_SATA_P
PCIECLKRQ4# / GPIO26
+3VS
CLK_CPU_DMI# {5}
CLK_CPU_DMI {5}
Y47
XCLK_RCOMP
CLKOUT_PCIE6N
CLKOUT_PCIE6P
1
RH184
2
90.9_0402_1%
+3VS
+1.05VS_VCCDIFFCLKN
PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
K43
+3VS
RH186
2.2K_0402_5%
F47
SB00000AR10
2N7002DWH_SOT363-6
H47
K49
DGPU_PRSNT#
1
RH18
2
10K_0402_5%
SMBCLK
RH188
2.2K_0402_5%
6
1
PCH_SMBCLK
{21,22,27}
QH2A
Pull High to UMA Mode
RH192 @
1
2
0_0402_5%
@
CH14
1
2
22P_0402_50V8J
SMBDATA
3
4
PCH_SMBDATA
{21,22,27}
2N7002DWH_SOT363-6
QH2B
RH194
1
2
0_0402_5%
@
Reserve for EMI please close to UH1
@
RH195
CLK_PCI_LPBACK 2
33_0402_5%
2
2
2
2
2
2
2
2
2
T11
PANTHER-POINT_FCBGA989
Part Number = SA00004NQ20
CLK_PCH_14M
1
1
1
1
1
1
1
1
1
2
1 10K_0402_5%
CLKOUT_PCIE3N
CLKOUT_PCIE3P
FLEX CLOCKS
2 RH175
+3VS
RH162
RH163
RH164
RH165
RH166
RH167
RH168
RH169
RH170
P10
SML1CLK
Y37
Y36
D
RH8
PEG_A_CLKRQ# / GPIO47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
{25} CDCLK_REQ#
{22} CLK_PCIE_MINI1#
{22} CLK_PCIE_MINI1
SML1DATA
{21}
2
1 10K_0402_5%
Y40
Y39
CL_RST1#
PCH_I2C2_SMBA
2
PCIE_CD#
PCIE_CD
SMBDATA
SML1CLK
PCH_I2C2_SMBA
0_0402_5%
1
RH177 2
+3V_PCH
1 0_0402_5%
1 0_0402_5%
2
2
CL_DATA1
CLOCKS
RH4
RH5
{25} CLK_PCIE_CD#
{25} CLK_PCIE_CD
C9
Total device
C
Card Reader--->
1
1
PERN6
PERP6
PETN6
PETP6
SML0DATA
RH14 2
2
BE38
BC38
AW38
AY38
PERN5
PERP5
PETN5
PETP5
SML0CLK
SMBCLK
1
BG40
BJ40
AY40
BB40
PERN4
PERP4
PETN4
PETP4
SML0ALERT# / GPIO60
H14
SML0DATA
1
BJ38
BG38
AU36
AV36
PERN3
PERP3
PETN3
PETP3
210K_0402_5%
5
BG37
BH37
AY36
BB36
SMBDATA
RH155 1
5
BF36
BE36
AY34
BB34
PERN2
PERP2
PETN2
PETP2
SMBALERT#
2
BG36
BJ36
AV34
AU34
SMBCLK
E12
2
10K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
10K_0402_5%
2
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
1
1
BE34
BF34
BB32
AY32
SMBALERT# / GPIO11
SMBUS
CH83
CH82
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PERN1
PERP1
PETN1
PETP1
Link
--->
{22} PCIE_PRX_DTX_N2
{22} PCIE_PRX_DTX_P2
{22} PCIE_PTX_C_DRX_N2
{22} PCIE_PTX_C_DRX_P2
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
BG34
BJ34
AV32
AU32
Controller
MiniWLAN
CH10 1
CH11 1
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCI-E*
PCIE Card Reader
D
{25} PCIE_PRX_DTX_N1
{25} PCIE_PRX_DTX_P1
{25} PCIE_PTX_C_DRX_N1
{25} PCIE_PTX_C_DRX_P1
1
RH19
1
RH152
1
RH153
1
RH156
1
RH157
1
RH159
1
RH160
1
RH161
@
CH15
1
2
22P_0402_50V8J
Reserve for EMI please close to
UH1
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (2/8) PCIE, SMBUS, CLK
Size
5
4
3
2
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
13
of
46
5
4
3
2
1
UH1C
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
BC24
BE20
BG18
BG20
{4}
{4}
{4}
{4}
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BE24
BC20
BJ18
BJ20
{4}
{4}
{4}
{4}
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
AW24
AW20
BB18
AV18
{4}
{4}
{4}
{4}
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
AY24
AY20
AY18
AU18
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI
D
{4}
{4}
{4}
{4}
FDI_INT
+VCCP
BJ24
DMI_IRCOMP
2
49.9_0402_1%
RBIAS_CPY
2
750_0402_1%
1
RH196
1
RH197
BG25
BH21
DMI_ZCOMP
FDI_FSYNC0
DMI_IRCOMP
FDI_FSYNC1
DMI2RBIAS
FDI_LSYNC0
4mil width and place
within 500mil of the PCH
FDI_LSYNC1
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
{4}
{4}
{4}
{4}
{4}
{4}
{4}
{4}
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
FDI_INT
D
{4}
FDI_FSYNC0
{4}
FDI_FSYNC1
{4}
FDI_LSYNC0
{4}
FDI_LSYNC1
{4}
UH1D
2 SUSACK#_R
0_0402_5%~D
1
XDP_DBRESET#
{5} XDP_DBRESET#
C
{5}
SYS_PWROK
SYS_PWROK
1
1 RH203
PCH_APWROK
0_0402_5%
PM_PWROK_R
L22
1 RH11
2 0_0402_5%
PCH_APWROK_R
1
2
@
0_0402_5%
L10
2
RH204
PM_DRAM_PWRGD
PCH_RSMRST#
1
RH206
{28} PCH_RSMRST#
2PCH_RSMRST#_R
0_0402_5%
2 SUSWARN#_R
0_0402_5%
1
{28} SUSWARN#
{28,37}
P12
0_0402_5%
{5} PM_DRAM_PWRGD
{28}
K3
2
RH202
PCH_PWROK
{28} PCH_PWROK
C12
RH279
2 PBTN_OUT#_R
0_0402_5%
DH2
2 ACIN_R
1
PBTN_OUT#
RH209
1
ACIN
SCS00000Z00
RB751V-40_SOD323-2
PCH_GPIO72
B13
C21
K16
E20
H20
E10
RI#
A10
SYS_RESET#
SYS_PWROK
PWROK
APWROK
DRAMPWROK
RSMRST#
DPWROK
WAKE#
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUSWARN#/SUSPWRDNACK/GPIO30
SLP_S3#
PWRBTN#
SLP_A#
ACPRESENT / GPIO31
SLP_SUS#
BATLOW# / GPIO72
PMSYNCH
RI#
PCH_GPIO72
RH210
1
2 10K_0402_5%
RI#
RH211
1
2 10K_0402_5%
WAKE#
RH212
1
2 1K_0402_5%
DSWODVREN
DSWODVREN
B9
WAKE#
1
2
RH201
{23}
PCH_PCIE_WAKE#
0_0402_5%
{22}
SLP_LAN# / GPIO29
G8
SUS_STAT#
PCH_LCD_CLK
PCH_LCD_DATA
{23} PCH_LCD_CLK
{23} PCH_LCD_DATA
N14
SUSCLK
2
RH205
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
SUSCLK_R
{28}
PM_SLP_S4#
{28}
PM_SLP_S3#
{28}
{23} PCH_TXCLK{23} PCH_TXCLK+
{23} PCH_TXOUT0{23} PCH_TXOUT1{23} PCH_TXOUT2{23} PCH_TXOUT0+
{23} PCH_TXOUT1+
{23} PCH_TXOUT2+
SLP_SUS#
H_PM_SYNC
H_PM_SYNC
T4
K14
1
RH207
{28}
PAD~D
SLP_SUS#
G16
PAD~D
PM_SLP_S5#
T19
G10
AP14
1
0_0402_5%
PAD~D
T37
2LVD_VREF
0_0402_5%
T45
P39
PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-
AN48
AM47
AK47
AJ48
PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+
AN47
AM49
AK49
AJ47
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AF40
AF39
{5}
LVDSB_CLK#
LVDSB_CLK
AH45
AH47
AF49
AF45
Check EC for S3 S4 LED
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AH43
AH49
AF47
AF43
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
+RTCVCC
ACIN_R
RH214
1
2 200K_0402_5%
SUSWARN#_R
RH216
1
2 10K_0402_5%
PCH_RSMRST#
RH217
1
2 10K_0402_5%
RH213
RH215
N48
P49
T49
1 330K_0402_5%
2
HDMI
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
mDP
M47
M49
CRT_IREF
RH220
1K_0402_0.5%
3
IN2
1
2 8.2K_0402_5%
RH219
1
2 2.2K_0402_5% CTRL_CLK
RH221
1
2 2.2K_0402_5% CTRL_DATA
OUT
4
{20}
{20}
{20}
{20}
{20}
{20}
{20}
{20}
{20}
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
B
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
PANTHER-POINT_FCBGA989
EC Request
on 20110309
Part Number = SA00004NQ20
MC74VHC1G08DFT2G_SC70-5
1 10K_0402_5%
SYS_PWROK
1
RH224
1
RH225
A
2
2.37K_0402_1%
2
100K_0402_5%
2
100K_0402_5%
LVDS_IBG
PCH_ENVDD
ENBKL
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (3/8) DMI,FDI,PM,GFX,DP
Size
4
3
2
Document Number
Rev
0.1
LA-8441P
Date:
5
PCH_HDMI_HPD
PCH_HDMI_N2
PCH_HDMI_P2
PCH_HDMI_N1
PCH_HDMI_P1
PCH_HDMI_N0
PCH_HDMI_P0
PCH_HDMI_N3
PCH_HDMI_P3
RH308
10K_0402_5%
1
2
PM_CLKRUN#
SYS_PWROK
RH222
RH223
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
{20}
{20}
2
IN1
DAC_IREF
CRT_IRTN
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AT49
AT47
AT40
PCH_HDMI_CLK
PCH_HDMI_DAT
1
5
2
PM_CLKRUN#
RH218
UH3
VCC
1
GND
PCH_PWROK
VGATE
DMC
P38
M39
2
@
+3VS
CRT_HSYNC
CRT_VSYNC
T43
T42
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
1
+3VS
{43}
CRT_DDC_CLK
CRT_DDC_DATA
CRT
T39
M40
DSWODVREN - On Die DSW VR Enable
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_CTRLCLK
DDPD_CTRLDATA
@
* HL烉
烉Enable
Disable
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_CTRLCLK
DDPC_CTRLDATA
CRT_BLUE
CRT_GREEN
CRT_RED
1 330K_0402_5%
2
AM42
AM40
AP39
AP40
C
LVD_IBG
LVD_VBG
{28}
PAD~D
AP43
AP45
L_CTRL_CLK
L_CTRL_DATA
AE48
AE47
AK39
AK40
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
AF37
AF36
PCH_TXCLKPCH_TXCLK+
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
T40
K47
CTRL_CLK
CTRL_DATA
T36
L_BKLTEN
L_VDD_EN
P45
DPST_PWM
PM_CLKRUN#
N3
J47
M45
LVDS_IBG
PANTHER-POINT_FCBGA989
Part Number = SA00004NQ20
+3V_PCH
B
SUSACK#
E22 PCH_DPWROK
ENBKL
{28}
ENBKL
{23} PCH_ENVDD
PCH_RSMRST#
2 0_0402_5%
PCH_DPWROK {28}
LVDS
RH273
SUSACK#
System Power Management
{28}
@1 RH199
Digital Display Interface
DSWVRMEN
For Deep S3
DSWODVREN
A18
Monday, November 14, 2011
Sheet
1
14
of
46
5
4
3
+3VS
W W AN_RADIO_OFF#
BT_OFF#
DP_CBL_DET
FFS_INT1
1
2
3
4
8.2K_0804_8P4R_5%
RPH4
8
7
6
5
PCI_PIRQA#
1
8.2K_0804_8P4R_5%
RH7
2 8.2K_0402_5%
GPIO3
1
RH6
2 8.2K_0402_5%
DGPU_HOLD_RST#
1 RH235
2 10K_0402_5%
UW B_OFF#
1 RH236
2 10K_0402_5%
DGPU_PW R_EN
1 RH237
2 10K_0402_5%
GPIO53
1
RH17 2 8.2K_0402_5%
C
VCC
5
{24} USB3_TX1_P
{27} USB3_TX2_P
OUT
IN1
1
IN2
2
SA00000OH00
UH4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
MC74VHC1G08DFT2G_SC70-5
{29}
GPS_OFF#
GPS_OFF#
RH301
1
{22} PCH_W L_OFF#
{5,25,28} PLT_RST#
CLK_PCI_LPBACK
CLK_PCI_EC
RH230
RH231
PIRQA#
PIRQB#
PIRQC#
PIRQD#
W W AN_RADIO_OFF# D47
2 0_0402_5% GPIO53 E42
PCH_W L_OFF#
F46
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
FFS_INT1
GPIO3
DP_CBL_DET
BT_OFF#
G42
G40
C42
D44
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
T7
K10
PME#
@
PLT_RST#
1 22_0402_5%
2 22_0402_5%
PAD~D T10 @
PAD~D T12 @
PAD~D T13 @
2
1
K40
K38
H38
G38
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
PAD~D
{13} CLK_PCI_LPBACK
{28} CLK_PCI_EC
USB3Rn1
USB3Rn2
USB3Rn3
USB3Rn4
USB3Rp1
USB3Rp2
USB3Rp3
USB3Rp4
USB3Tn1
USB3Tn2
USB3Tn3
USB3Tn4
USB3Tp1
USB3Tp2
USB3Tp3
USB3Tp4
DGPU_HOLD_RST# C46
UW B_OFF#
C44
DGPU_PW R_EN
E40
{29} UW B_OFF#
PCB Footprint = MC74VHC1G08DFT2G_SC70-5
B
TP21
TP22
TP23
TP24
PLT_RST#
2
RH234
100K_0402_5%
3
1
GND
4
{22,26} PLT_RST_BUF#
B21
M20
AY16
BG46
CLK_PCI0
CLK_PCI1
C6
H49
H43
J48
K42
H40
USB
2
+3VS
1
@
RH233
10K_0402_5%
{24} USB3_RX1_P
{27} USB3_RX2_P
{24} USB3_TX1_N
{27} USB3_TX2_N
+3VS
TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
BE28
BC30
BE32
BJ32
BC28
BE30
BF32
BG32
AV26
BB26
AU28
AY30
AU26
AY26
AV28
AW30
{24} USB3_RX1_N
{27} USB3_RX2_N
External USB 3.0
BG26
BJ26
BH25
BJ16
BG16
AH38
AH37
AK43
AK45
C18
N30
H3
AH12
AM4
AM5
Y13
K24
L24
AB46
AB45
RSVD
8
7
6
5
PCI
D
1
2
3
4
1
UH1E
RPH3
PCH_W L_OFF#
PCI_PIRQB#
PCI_PIRQD#
PCI_PIRQC#
2
PLTRST#
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
RSVD1
RSVD2
RSVD3
RSVD4
AY7
AV7
AU3
BG4
RSVD5
RSVD6
AT10
BC8
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
RSVD23
RSVD24
AV5
AV10
RSVD25
AT8
RSVD26
RSVD27
AY5
BA2
RSVD28
RSVD29
AT12
BF3
Intel Anti-Theft Techonlogy
High=Endabled
NV_ALE
Low=Disable(floating)
D
*
+1.8VS
NV_ALE
RH228
2 1K_0402_5%
1
NV_ALE
C
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
USBRBIAS#
C33
USBRBIAS
B33
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
A14
K20
B17
C16
L16
A16
D14
C14
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7
RH274 1
RH310 1
USB20_N10
USB20_P10
@
@
{24}
{24}
{27}
{27}
{29}
{29}
{21}
{21}
{22}
{22}
{29}
{29}
{29}
{29}
{29}
{29}
To Cradle for Display link
External USB
Touch Sensor
Sensor
MPCIE-WLAN
Mini PCIE 3G
CAM1 >>1.3M
CAM2 >> 2M
2 0_0402_5%
2 0_0402_5%
USB20_N10 {24}
USB20_P10 {24}
To Cradle USB HUB
B
+3V_PCH
RPH1
USBRBIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
Within 500 mils
1
RH229
{27}
2
22.6_0402_1%
USB_OC0# 4
USB_OC1# 3
USB_OC2# 2
USB_OC3# 1
USB_OC0#
USB_OC1#
5
6
7
8
10K_1206_8P4R_5%
RPH2
4
5
3
6
2
7
1
8
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#
(For USB Port 9)
10K_1206_8P4R_5%
RH10
1
2
0_0402_5%
LAN_PLUGIN
Part Number = SA00004NQ20
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Issued Date
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH (4/8) PCI, USB, NVRAM
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
15
of
46
5
4
3
2
1
2
RH154
GPIO6
H36
E38
C10
GPIO8
EC_SCI#_R
1 0_0402_5%
EC_SMI#_R
1 0_0402_5%
GPIO8
2
2
@
{28} EC_LID_OUT#
A42
1
0_0402_5%
TACH4 / GPIO68
C40
@ T21
PAD~D
TACH1 / GPIO1
TACH5 / GPIO69
B41
@ T22
PAD~D
TACH2 / GPIO6
TACH6 / GPIO70
C41
@ T23
PAD~D
+3VS
TACH3 / GPIO7
TACH7 / GPIO71
A40
@ T24
PAD~D
C4
LAN_PHY_PWR_CTRL / GPIO12
PCH_GPIO15
G2
GPIO15
U2
A20GATE
PECI
SATA4GP / GPIO16
2 GPIO28
1K_0402_5%
1
RH241
{27}
1
RH28
NFC_IRQ#
{40} DDR3L_EN
DS3@ 1
RH36
{28} DS3_WAKE#
PCH_GPIO37
FDI TERMINATION VOLTAGE OVERRIDE
DDR3_TYPE
DDR3_2G
+3VS
RH245
2
2
@
{21} PCH_GPIO_PA0
{21} PCH_GPIO_NRST
LOW - Tx, Rx terminated
to same voltage
(DC Coupling Mode)
10K_0402_5%
SCLOCK / GPIO22
GPIO24
E16
GPIO27
P8
GPIO28
DS3_WAKE#_R
GPIO28
1
RH15
{22} PCH_BT_ON#
*
T5
E8
2
0_0402_5%
@
C
2 PCH_GPIO22
0_0402_5%
DDR3L_EN
1 1K_0402_5%
PCH_GPIO37
1
PCH_GPIO37
2 STP_PCI#
0_0402_5%
PCH_GPIO35
K1
K4
GPIO35
GPIO36
V8
SATA2GP / GPIO36
PCH_GPIO37
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
PCH_GPIO38
2
0_0402_5%
PCH_GPIO39
2
0_0402_5%
PCH_GPIO48
2
0_0402_5%
GPIO49
2
0_0402_5%
HDD_DETECT#
1
RH30
1
RH31
1
RH32
1
RH33
THRMTRIP#
AY10
H_THRMTRIP#
NV_CLE
2
1K_0402_5%
RH227
TS_VSS1
TS_VSS2
AK11
TS_VSS3
AH10
INIT3_3V
TS_VSS4
AK10
This signal has weak internal
PU, can't pull low
BG48
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
VSS_NCTF_19
BJ4
VSS_NCTF_20
BJ44
VSS_NCTF_21
BJ45
VSS_NCTF_22
BJ46
VSS_NCTF_23
BJ5
2
RH240
H_THRMTRIP#
{5}
@
RH242
10K_0402_5%
1
H_SNB_IVB#
{5}
CLOSE TO THE BRANCHING POINT
C
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_6
VSS_NCTF_24
BJ6
B3
VSS_NCTF_7
VSS_NCTF_25
C2
B47
VSS_NCTF_8
VSS_NCTF_26
C48
BD1
VSS_NCTF_9
VSS_NCTF_27
D1
BD49
VSS_NCTF_10
VSS_NCTF_28
D49
BE1
VSS_NCTF_11
VSS_NCTF_29
E1
VSS_NCTF_30
E49
VSS_NCTF_31
F1
VSS_NCTF_32
F49
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
+3VS
GPIO6
1 RH243
2 10K_0402_5%
GPIO1
1 RH244
2 10K_0402_5%
GPIO16
1 RH247
2 10K_0402_5%
1
2 10K_0402_5%
+3VALW
GPIO8
A6
2 10K_0402_5%
{5}
NV_CLE
VSS_NCTF_16
BF49
2.2K_0402_5%
RH226
{28}
H_CPUPWRGD
AY1
GPIO57
VSS_NCTF_5
{5,28}
AH8
SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_4
H_PECI
EC_KBRST#
Weak internal
PU,Do not pull low
DF_TVS
V3
A5
2
RH239
{28}
H_THERMTRIP#_C 1
390_0402_5%
INIT3_3V#
STP_PCI# / GPIO34
A46
1
0_0402_5%
@
T14
INIT3_3V#
D6
BE49
1
AY11
BG2
BF1
DDR3_TYPE
PROCPWRGD
VSS_NCTF_15
A45
+3VS
EC_KBRST#
SDATAOUT1 / GPIO48
RH246
B
P5
P37
A4
For DDR3
need check
AU16
NC_1
A44
Reference Chicklist V1.5, GPIO37
unused, Pull Down 10K Ohm
TACH0 / GPIO17
GATEA20
PCH_PECI_R
1
烉烉On-Die
voltage regulator enable
On-Die PLL Voltage Regulator disable
+1.8VS
P4
2
*
H
L
D40
CPU/MISC
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
T20 @
NCTF
PAD~D
GPIO
RCIN#
GPIO28
D
RH238
10K_0402_5%
DMC_DET#
GPIO16
DMI Termination Voltage
Set to Vcc when HIGH
NV_CLE
Set to Vss when LOW
1
RH176
RH171
GPIO1
2
EC_SCI#
EC_SMI#
EC_SCI#
EC_SMI#
T7
1
{28}
{28}
D
BMBUSY# / GPIO0
2
UH1F
GPIO0
RH257
+3V_PCH
HDD_DETECT#
1
DMC_DET#
1
2 10K_0402_5%
RH249
2 10K_0402_5%
RH251
PCH_GPIO15
2 1K_0402_5%
1
RH252
EC_SMI#
B
2 10K_0402_5%
1
RH253
+3VS
Part Number = SA00004NQ20
RH287
PANTHER-POINT_FCBGA989
10K_0402_5%
2
DDR3_2G
1
RH248
GPIO0
Next Version ,Reference
Chicklist V1.5, GPIO36 unused,
Pull Down 10K Ohm
PCH_GPIO28 needs to be connected to XDP_FN8
PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16
RH254
1
@
1
2 10K_0402_5%
RH12
GPIO36
2 10K_0402_5%
GPIO36
1
2 10K_0402_5%
RH255
2011/08/22 Modify
STP_PCI#
1
PCH_GPIO22
1
2 10K_0402_5%
RH256
2 10K_0402_5%
RH258
Please refer to Huron River Debug Board DG 0.5
PCH_GPIO38
2 10K_0402_5%
1
RH259
PCH_GPIO39
2 10K_0402_5%
1
RH260
PCH_GPIO35
2 10K_0402_5%
1
RH261
GPIO49
2 10K_0402_5%
1
RH262
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH (5/8) GPIO, CPU, MISC
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
16
of
46
5
4
3
2
1
PCH Power Rail Table
+VCCP
POWER
UH1G
+3VS
Voltage Rail
Voltage
AN19
+VCCP
U47
2
1mA
VCCALVDS
VSSALVDS
VCCTX_LVDS[1]
VCCTX_LVDS[2]
60mA
VCCTX_LVDS[4]
AK36 +VCCA_LVDS
2
CH22
10U_0805_6.3V6M
SE093106M80
RH263
Near AP43
0.1UH_MLF1608DR10KT_10%_1608
LH2
2
1
CH25
1
1
0.1uH inductor, 200mA
AM38
AP36
CH24
0.01U_0402_16V7K
2
0.01U_0402_16V7K2
V5REF
5
0.001
V5REF_Sus
5
0.001
Vcc3_3
3.3
0.266
VccADAC
3.3
0.001
VccADPLLA
1.05
0.08
VccADPLLB
1.05
0.08
VccCore
1.05
1.3
VccDMI
1.05
0.042
VccIO
1.05
2.925
VccASW
1.05
1.01
VccSPI
3.3
0.02
VccDSW
3.3
0.003
VccpNAND
1.8
0.19
VccRTC
3.3
6 uA
VccSus3_3
3.3
0.119
2 0.022_0805_1%
1
+1.8VS
+VCCTX_LVDS
CH23 1
0.001
D
+3VS
AK37
AM37
1.05
V_PROC_IO
2
1
BLM18PG181SN1D_2P
1
1
2
1
CH21
0.1U_0402_10V7K
VSSADAC
+VCCADAC
U48
CH20
0.01U_0402_16V7K
CRT
VCCADAC
VCCTX_LVDS[3]
+VCCP
S0 Iccmax
Current (A)
LH1
1mA
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
VCCCORE[16]
VCCCORE[17]
LVDS
2
AA23
AC23
AD21
AD23
AF21
AF23
AG21
AG23
AG24
AG26
AG27
AG29
AJ23
AJ26
AJ27
AJ29
AJ31
VCC CORE
2
1
CH16
1U_0402_6.3V6K
1
CH19
1U_0402_6.3V6K
2
CH18
1U_0402_6.3V6K
1
CH17
10U_0805_6.3V6M
SE093106M80
D
1
2
1300mA
2
22U_0805_6.3V6M
AP37
VCCIO[28]
Place CH27 Near BJ22 pin
AN17
AN26
AN27
+V1.05S_VCC_EXP
C
AP21
RH9
1
2
0_0805_5%
2
1
2
CH32
1U_0402_6.3V6K
2
1
CH31
1U_0402_6.3V6K
2
2
0_0805_5%
RH268
1
CH30
1U_0402_6.3V6K
1
CH28
10U_0805_6.3V6M
SE093106M80
CH29
1U_0402_6.3V6K
1
1
+3VS
AP23
AP24
AP26
AT24
AN33
VCCIO[15]
VCCIO[16]
VCCIO[17]
VCCIO[18]
VCC3_3[6]
V33
VCC3_3[7]
V34
+3VS_VCC3_3_6
1
2
0_0805_5%
CH26
0.1U_0402_10V7K
2
2925mA
VCCIO[19]
VCCVRM[3]
+VCCAFDI_VRM
AT16
+VCCP_VCCDMI
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCIO[24]
VCCDMI[1]
20mA
VCCCLKDMI
AT20 +VCCP_VCCDMI
1
1
AB36 +1.05VS_VCC_DMI_CCI
1
2
+VCCP
2
VCCIO[26]
VCCDFTERM[1]
190mA
VCC3_3[3]
CH35
AP16
VCCVRM[2]
Place CH53 Near BG6 pin
+1.05VS_VCCAPLL_FDI
1
0_0603_5%
1
@
B
2
+VCCP
BG6
RH271
1
2 +1.05VS_VCCDPLL_FDI AP17
0_0805_5%
+VCCP_VCCDMI
AU20
VccAFDIPLL
VCCIO[27]
VCCDMI[2]
FDI
@
CH37
1U_0402_6.3V6K
2
RH270
2
AG16
VCCDFTERM[2]
VCCDFTERM[3]
2 1U_0402_6.3V6K
CH34
1U_0402_6.3V6K
+VCCPNAND
VCCDFTERM[4]
20mA
VCCSPI
AG17
AJ16
1
AJ17
V1
2
1
2
RH269
0_0805_5%
RH272
1
+3V_VCCPSPI
1
C
0_0805_5%
CH33
+VCCP
VCCIO[25]
0.1U_0402_10V7K
+VCCAFDI_VRM
RH267
1
2
0_0805_5%
CH36
0.1U_0402_10V7K
1
BH29
+VCCP
RH266
VCCIO[20]
DFT / SPI
+3VS_VCCA3GBG
+3VS
1
2
AN34
HVCMOS
AN16
AN21
+VCCP
RH265
VCCIO
@
CH27
10U_0805_6.3V6M
SE093106M80
VCCAPLLEXP
1
@
BJ22
DMI
+VCCAPLLEXP
1
0_0603_5%
2
2
RH264
2
+1.8VS
+3VS
VccSusHDA
3.3 / 1.5
VccVRM
1.8 / 1.5
0.01
0.16
VccCLKDMI
1.05
0.02
VccSSC
1.05
0.095
VccDIFFCLKN
1.05
0.055
VccALVDS
3.3
0.001
VccTX_LVDS
1.8
0.06
0_0805_5%
B
CH38
1U_0402_6.3V6K
2
Part Number = SA00004NQ20
PANTHER-POINT_FCBGA989
VCCVRM = 160mA detal waiting for newest spec
+VCCAFDI_VRM
+1.5VS
2
RH275
1
0_0603_5%
+VCCAFDI_VRM
VCCVRM==>1.5V FOR mobile
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH (6/8) PWR
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
17
of
46
5
4
3
2
1
VCC3_3 = 266mA detal waiting for newest spec
VCCDMI = 42mA detal waiting for newest spec
+VCCP
2
AA21
AA27
CH51
22U_0805_6.3V6M
SE000000I10
2
2
CH50
22U_0805_6.3V6M
SE000000I10
AA29
AA31
C
AC26
1
2
1
2
AC27
CH55
1U_0402_6.3V6K
2
CH54
1U_0402_6.3V6K
1
CH53
1U_0402_6.3V6K
+VCCP
1
AC29
AC31
AD29
2
RH291
AD31
W21
@
2
10UH_LB2012T100MR_20%
1
2
+3VS_VCC_CLKF33
1
2
W24
CH61
1U_0402_6.3V6K
1
W23
CH59
10U_0805_10V4Z
LH4
DCPSUS[3]
VCCSUS3_3[10]
VCCASW[2]
W26
W29
W31
W33
VCCIO[34]
1010mA
1mA V5REF_SUS
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
DCPSUS[4]
VCCSUS3_3[1]
1mA V5REF
VCCASW[16]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCC3_3[1]
VCC3_3[8]
+VCCRTCEXT
2
RH295
@
1
+1.05VM_VCCSUS
1
0_0603_5%
N16
VCC3_3[4]
+VCCAFDI_VRM
Y49
1
V23
2
V24
P24
2
RH281
+3V_VCCAUBG
1
2
+1.05VS_VCCAUPLL
T26
M26
+PCH_V5REF_SUS
AN23
+VCCA_USBSUS
AN24
+3V_VCCPSUS
2
RH286
1
+3V_PCH
0_0603_5%
2
1
+3V_PCH
RH282
0_0603_5%
1
1
0_0603_5%
+3V_VCCPSUS
N20
N22
P20
VCCASW[20]
VCCVRM[4]
VCCIO[13]
2
2
1
AF13
2
1
C
DH4
RB751V-40_SOD323-2
SCS00000Z00
+PCH_V5REF_RUN
1
2
CH57
1U_0603_10V6K
+3VS
1
0_0603_5%
CH60
0.1U_0402_10V7K
+1.05VS_SATA3
RH294
0_0603_5%
CH62
0.1U_0402_10V7K
2
1
2
+1.05VS_SATA3
1
+VCCP
0_0805_5%
CH63
1U_0402_6.3V6K
AH13
AH14
RH288
100_0402_5%
+3V_PCH
2
RH292
1
+VCC3_3_2
CH49
0.1U_0603_25V7K
+3VS
1
0_0805_5%
+3VS_VCCPPCI
AJ2
+PCH_V5REF_SUS
1
+5VS
2
RH290
2
W16
T34
DH3
RB751V-40_SOD323-2
SCS00000Z00
2
CH58
0.1U_0402_10V7K
AA16
2
DCPRTC
2
RH284
100_0402_5%
+3VS
+3VS_VCCPCORE
1
P22
+3V_PCH
1
CH56
1U_0402_6.3V6K
+3VS
VCC3_3[2]
@
+VCCP
RH289
0_0603_5%
2
1
RH293
VCCASW[19]
+5V_PCH
+VCCA_USBSUS
+PCH_V5REF_RUN
P34
VCCASW[18]
VCCIO[12]
CH64
0.1U_0402_10V7K
T24
VCCASW[17]
VCCIO[5]
+VCCP
+3V_VCCPUSB
T23
2
VCCSUS3_3[9]
VCCASW[1]
1
1
AA26
0_0805_5%
VCCIO[14]
VCCSUS3_3[6]
AA19
AA24
+3VS
VCCSUS3_3[8]
1
@
1U_0402_6.3V6K
VCCAPLLDMI2
1
CH45
AL24
VCCSUS3_3[7]
2
+VCCSUS1
119mA
1
2
0_0603_5%
T29
VCC3_3[5]
1
1
RH283
2
T27
2
2
CH40
1U_0402_6.3V6K
P28
1
AL29
+VCCP
2
+VCCDPLL_CPY
+VCCP
VCCIO[33]
1
0_0603_5%
CH48
1U_0402_6.3V6K
T38
BH23
VCCIO[32]
2
RH285
1
CH52
CH43
10U_0805_10V4Z
+3VS_VCC_CLKF33
+VCCAPLL_CPY_PCH
DCPSUSBYP
P26
0.1U_0402_10V7K
V12
+1.05VS_VCCUSBCORE
N26
CH47
0.1U_0402_10V7K
+VCCAPLL_CPY
VCCIO[30]
CH44
0.1U_0402_10V7K
2
0_0805_5%
@
VCCIO[29]
3mA
VCCDSW3_3
1
1
VCCACLK
VCCIO[31]
+PCH_VCCDSW
1
@
0.1U_0402_10V7K
LH3
10UH_LB2012T100MR_20%
1
2
@
1
T16
2
0.1U_0402_10V7K
RH280
+VCCPDSW
2
CH42 2
+VCCP
AD49
1
CH39
USB
2
0_0603_5%
POWER
UH1J
PCI/GPIO/LPC
1
RH277
D
+VCCACLK
1
0_0603_5%
@
2
RH276
+3VALW
Clock and Miscellaneous
D
2
+VCCP
VCCAPLLSATA
VCCVRM[1]
VCCSSC
AF11
1
+VCCAFDI_VRM
+1.05VS_VCC_SATA
55mA
VCCIO[2]
VCCIO[4]
95mA
+1.05VS_VCC_SATA
2
1
AD17
CH71
4.7U_0603_6.3V6K
2
1
2
BJ8
+RTCVCC
A22
1
+
2
CH78
220U_B2_2.5VM_R35
+1.05VS_VCCA_A_DPL
1
2
+1.05VS_VCCA_B_DPL
1
2
1
+
2
1
2
V_PROC_IO 1mA
1
2
1
2
VCCRTC
VCCASW[22]
MISC
2
DCPSUS[1]
DCPSUS[2]
VCCASW[23]
VCCASW[21]
10mA VCCSUSHDA
1
B
CH73 Near AK1 pin
+VCCP
+VCCP
T21
V21
T19
+VCCSUSHDA
P32
2
RH305
CH77
1U_0402_6.3V6K
2
Part Number = SA00004NQ20
@
1
0_0603_5%
+3V_PCH
If it support 3.3V audio signals
POP:RH228
Depop RH233/RH234
If it support 1.5V audio signals
POP:RH233/RH234
Depop R228
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PCH (7/8) PWR
Size
4
3
2
Document Number
Rev
0.1
LA-8441P
Date:
5
+VCCP
0_0805_5%
1
PANTHER-POINT_FCBGA989
@ RH297
2
0_0805_5%
CH66
10U_0805_10V4Z
@
Place
RH306
150_0402_1%
2
1
1
2
HDA
1
CH46
1U_0402_6.3V6K
1
AC17
DCPSST
CPU
@
2
+V_CPU_IO
T17
V19
2
RH299
AC16
1
CH70
0.1U_0402_10V7K
LH5
10UH_LB2012T100MR_20%
1
2 +VCCSATAPLL_R
@
+VCCSATAPLL
+VCCAFDI_VRM
AK1
CH68
1U_0402_6.3V6K
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
SATA
80mA
RTC
CH69
1U_0402_6.3V6K
V16
CH76
1U_0402_6.3V6K
1
+VCCA_DPLL_L
1
2
LH7
10UH_LB2012T100MR_20%
AG33
CH75
0.1U_0402_10V7K
1
2
2
0_0603_5%
+1.05VS_SSCVCC
+VCCSST
+1.05VM_VCCSUS
2
A
80mA
VCCADPLLB
2
LH6
10UH_LB2012T100MR_20%
1
2
2
VCCADPLLA
VCCIO[3]
CH74
0.1U_0402_10V7K
1
0_0603_5%
+VCCP
1
RH303
+1.05VS_VCCDIFFCLKN
1
0_0603_5% 1
CH73
0.1U_0402_10V7K
2
RH300
AF17
AF33
AF34
AG34
+1.05VS_VCCDIFFCLKN
1U_0402_6.3V6K
CH67
1U_0402_6.3V6K
+VCCP
0_0805_5%
BF47
AF14
CH81
1U_0402_6.3V6K
2
2
RH298
CH80
220U_B2_2.5VM_R35
+VCCP
1
RH307
BD47
+1.05VS_VCCA_B_DPL
CH65
CH72
0.1U_0402_10V7K
1
+VCCP
+1.05VS_VCCA_A_DPL
+VCCDIFFCLK
1
0_0603_5%
CH79
1U_0402_6.3V6K
2
RH296
B
VCCIO[6]
Monday, November 14, 2011
Sheet
1
18
of
46
5
4
3
2
1
UH1I
AY4
AY42
AY46
AY8
B11
B15
B19
B23
B27
B31
B35
B39
B7
F45
BB12
BB16
BB20
BB22
BB24
BB28
BB30
BB38
BB4
BB46
BC14
BC18
BC2
BC22
BC26
BC32
BC34
BC36
BC40
BC42
BC48
BD46
BD5
BE22
BE26
BE40
BF10
BF12
BF16
BF20
BF22
BF24
BF26
BF28
BD3
BF30
BF38
BF40
BF8
BG17
BG21
BG33
BG44
BG8
BH11
BH15
BH17
BH19
H10
BH27
BH31
BH33
BH35
BH39
BH43
BH7
D3
D12
D16
D18
D22
D24
D26
D30
D32
D34
D38
D42
D8
E18
E26
G18
G20
G26
G28
G36
G48
H12
H18
H22
H24
H26
H30
H32
H34
F3
D
C
B
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
UH1H
H5
AA17
AA2
AA3
AA33
AA34
AB11
AB14
AB39
AB4
AB43
AB5
AB7
AC19
AC2
AC21
AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39
AD4
AD40
AD42
AD43
AD45
AD46
AD8
AE2
AE3
AF10
AF12
AD14
AD16
AF16
AF19
AF24
AF26
AF27
AF29
AF31
AF38
AF4
AF42
AF46
AF5
AF7
AF8
AG19
AG2
AG31
AG48
AH11
AH3
AH36
AH39
AH40
AH42
AH46
AH7
AJ19
AJ21
AJ24
AJ33
AJ34
AK12
AK3
VSS[0]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
D
AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28
C
B
PANTHER-POINT_FCBGA989
Part Number = SA00004NQ20
PANTHER-POINT_FCBGA989
A
A
Part Number = SA00004NQ20
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
2011/10/18
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
PCH (8/8) VSS
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
19
of
46
4
3
0.1U_0402_16V7K 1
0.1U_0402_16V7K 1
2
2
C5
C6
PCH_HDMI_P1
PCH_HDMI_N1
PCH_HDMI_P1 {14}
PCH_HDMI_N1 {14}
PCH_HDMI_P0_C
PCH_HDMI_N0_C
0.1U_0402_16V7K 1
0.1U_0402_16V7K 1
2
2
C7
C8
PCH_HDMI_P0
PCH_HDMI_N0
PCH_HDMI_P0 {14}
PCH_HDMI_N0 {14}
2
2
2
2
1
2
+5VS
D11
2
C
+3VS
3
1
2
2
HDMI_DETECT
1
1
2
0_0402_5%
HDMI_R_CK+
2
0_0402_5%
HDMI_R_D0+
2
@
PCH_HDMI_P0_C
R21
1
D2
BAV99-7-F_SOT23-3
@
R20
100K_0402_5%
@
C
2
L2
MBK1608221YZF_2P
HP_DETECT
1
2
1
SSM3K7002FU_SC70-3
2
1
1
1
Q3
{14} PCH_HDMI_HPD
R18
1
2
10K_0402_5%
2
R19
3
@
1
2
C10
220P_0402_50V7K
3
3
Place closed to JHDMI1
2
4
R16
1M_0402_5%
D
4
WCM-2012-900T_0805
L1
1
HDMI_R_CK-
S
PCH_HDMI_P3_C
0_0402_5%
2
2
@
1
G
1
SM070001310 400ma 90ohm@100mhz DCR 0.3
+5VS_HDMI
C1154
0.1U_0402_16V4Z
Q2
S
2N7002_SOT23
R15
100K_0402_5%
C1153
22N_0402_16V7K
5V PULL UP IN CONNECTER SIDE
D
2
G
RB411DT146_SOT23-3
1
0_0402_5%
1
2
R14
1
2
W=40mils
+3VS
R17
+HDMI_5V_OUT
HDMI_SDATA
2N7002DWH_SOT363-6
SB00000AR10 Q1A
PCH_HDMI_N3_C
D
NET: HDMIRES_GND
WIDTH>20 mils
3
6
1
R12
1
R10 680_0402_5%
HDMI_L_SDATA
R9 680_0402_5%
{14} PCH_HDMI_DAT
2.2K_0402_5%
2
0_0402_5%
R8 680_0402_5%
1
2
R7 680_0402_5%
1
R11
R6 680_0402_5%
2N7002DWH_SOT363-6
SB00000AR10
+3VS
2
HDMI_SCLK
1
PCH_HDMI_P1_C
PCH_HDMI_N1_C
1
PCH_HDMI_P2 {14}
PCH_HDMI_N2 {14}
1
PCH_HDMI_P2
PCH_HDMI_N2
1
C3
C4
R5 680_0402_5%
3
2
2
1
HDMI_L_SCLK
0.1U_0402_16V7K 1
0.1U_0402_16V7K 1
R4 680_0402_5%
2
0_0402_5%
R2
PCH_HDMI_P2_C
PCH_HDMI_N2_C
R3 680_0402_5%
1
{14} PCH_HDMI_CLK
Q1B
4
PCH_HDMI_P3 {14}
PCH_HDMI_N3 {14}
HDMIRES_GND
D
PCH_HDMI_P3
PCH_HDMI_N3
2
5
Follow Intel
Feedback putting
2.2K ohm
C1
C2
1
2
2
2
2
2.2K_0402_5%
R1
1
1
0.1U_0402_16V7K 1
0.1U_0402_16V7K 1
1
HDMI
2
PCH_HDMI_P3_C
PCH_HDMI_N3_C
+3VS
2
5
5V Level
+HDMI_5V_OUT
PCH_HDMI_N0_C
R24
2
4
3
3
1
PCH_HDMI_N1_C
R25
2
0_0402_5%
HDMI_R_D0-
@
2
0_0402_5%
HDMI_R_D1-
1
PCH_HDMI_P1_C
R26
1
PCH_HDMI_P2_C
R27
1
3
3
2
2
C11
2
2
0_0402_5%
HDMI_R_D1+
2
0_0402_5%
HDMI_R_D2+
@
1
L5
WCM-2012-900T_0805
4
PCH_HDMI_N2_C
R28
@
1
2
2
4
3
3
1
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+HDMI_5V_OUT
1
2
HDMI_SDATA
HDMI_SCLK
HDMI_R_CK-
C12
HDMI_R_CK+
HDMI_R_D0HDMI_R_D0+
HDMI_R_D1HDMI_R_D1+
HDMI_R_D2HDMI_R_D2+
1
2
G23
G22
G21
G20
23
22
21
20
HDMI_R_D2A
CONN@
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BELLW_80082-5021
0_0402_5%
@
A
B
JHDMI1
HP_DETECT
10P_0402_50V8J
4
@
R23
2.2K_0402_5%
10P_0402_50V8J
4
WCM-2012-900T_0805
L4
1
1
@
R22
@
FKDQJHFRQQ
1
2
2
B
1
2.2K_0402_5%
2
1
+3VS
1
L3
WCM-2012-900T_0805
4
4
3
2
HDMI Conn
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
20
of
46
5
4
3
2
1
G-SENSOR E-COMPASS
MCU_STM32F103RD
+3VS
US4
+3VS
7
1
4
1
INT2
1
I2C_CLK
2 G_INT1
RS15 0_0402_5%
2 G_INT2
RS16 0_0402_5%
1
1
2
2
US7
GND
PCH_GPIO_PA0
C1
USBD-
E1
D-Out
A3
Pup
Pup
GYROSCOPE
RS7
2.2K_0402_5%
+3VS
EMIF02-USB01F2_FLIP CHIP8
1
1
+3VS
D+Out
RS6
2.2K_0402_5%
3
1 RS3
2
0_0402_5%
4
5
GYRO_INT2
GYRO_INT1
1 RS20
2
0_0402_5%
1
2
RS19
0_0402_5%
6
7
SDA/SDI/SDO
RES_3
SDO/SA0
RES_4
CS
GND
DRDY
PLLFILT
INT
RES_5
2
10
11
{13,22,27} PCH_SMBCLK
{13,22,27} PCH_SMBDATA
{13} PCH_I2C2_SMBA
12
13
14
15
+3VS
CS4
1
2
CS5
1
2
PD2
NRST
BOOT0
Vref+
Vbat
OSC_IN
OSC_OUT
A1
E8
F8
D6
H6
H5
E1
E2
E3
D1
A2
B3
C4
C8
B8
B7
+3VS
RS4
100K_0402_5%
1
1
2
{16}
CS11
2
D8
D7
1 RS5
1 RS44
2
0_0402_5%
1
2
20K_0402_5%
+3VS
C
RS45 2
0_0402_5%
YS1
1
2
12MHZ_16PF_7A12000026
1
1
2
2
CS9
0.1U_0402_16V4Z
2
CS8
0.1U_0402_16V4Z
2
CS7
0.1U_0402_16V4Z
CS6
0.1U_0402_16V4Z
2
B
1
PCH_GPIO_NRST
0.1U_0402_16V4Z
C7
A6
F7
C6
+3VS
1
PCH_GPIO_NRST
2
0_0402_5%
A3
2
RS33
1
RS34
1
@
CS13
2
1
CS33
10U_0402_6.3V6M
CS3
0.1U_0402_16V4Z
1
PC0
PC1
PC2
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
8.2P_0402_50V8D
16
STM32F103RDY6TR_WLCSP64
2
CS10
CS12
RES_0
VDD
L3G4200DTR_LGA16_4X4
I2C_CLK
I2C_DATA
9
1
8.2P_0402_50V8D
8
RES_2
0.47U_0402_16V4Z
I2C_DATA
RES_1
SCL/SPC
PA0-WKUP
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
D
0.1U_0402_16V4Z
1
2
VDD_IO
2
10K_0402_5%
1
0.01U_0402_16V7K
2
0_0603_5%
I2C_CLK
2
US5
1RS25
C
Vbus
USB20_P3
USB20_N3
GND
{15}
{15}
D2
US37
USBD+
1 RS31 @2 0_0402_5%
F6
E6
H8
G7
H7
E5
G5
G4
C3
E4
D+In
D2
Pup
D3
D-In E3
USBD-_ESD 1RS17 0_0402_5%
USBD-_R C1
2
USBD+_ESD 1RS18 0_0402_5%
USBD+_R C2
2
DZ B2
1RS13 0_0402_5%
2
D4
TS1
1RS14 0_0402_5%
2
B2
TS2
C3
G_INT1
H4
G_INT2
F4
GYRO_INT1
H3
GYRO_INT2
A4
B4
A5
B5
C5
D5
B6
PCH_I2C2_SCL
1 RS21 @2 0_0402_5%
G3
PCH_I2C2_SDA
1 RS22 @2 0_0402_5%
F3
PCH_I2C2_SMBA
1 RS30 @2 0_0402_5%
G2
PS_OUT
G1
to I/O board {29}
conn. PS_OUT
DRDY
F2
ALS_INT
F1
{16} PCH_GPIO_PA0
LSM303DLHCTR_LGA14_3X5
RS29
5
1
Peserved
Peserved
Peserved
Peserved
2
2
8
9
10
11
SCL
INT1
0_0603_5%
2
0.22U_0402_16V7K
DRDY
SETP
SETC
3
G6
A8
A1
H1
G8
12
13
2
I2C_DATA
SDA
CS1
0.1U_0402_16V4Z
1
+3VS
14
Vdd
C1
CS31
10U_0402_6.3V6M
CS30
D
Vdd_IO
VDD_4
VDD_3
VDD_2
VDD_1
VDDA
2
1
0_0603_5%
6
VSS_4
VSS_3
BYPASS/VSS_2
VSS_1
VSSA
1RS23
F5
A7
B1
H2
E7
CS2
4.7U_0402_6.3V6M
1
2
B
Ambient Light Sensor
1
+3VS
+3VS
RS12
2.2K_0402_5%
3
2
1
2
10U_0402_6.3V6M
CS32
0.1U_0402_16V4Z
CS19
A
1
VDD
2
U1
LED CATHODE
2
I2C_CLK
6
SCLK
INT
4
I2C_DATA
5
SDAT
GND
1
ALS_INT
CM3623A3OP-AD_OPLGA6_1P8X2P35
A
Security Classification
Issued Date
Compal Secret Data
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
Sensor
Size Document Number
Custom LA-8441P
Date:
Rev
0.1
Sheet
Monday, November 14, 2011
1
21
of
46
5
4
3
2
For Wireless LAN
D
2
C86
1
1
1
C87
@
0.1U_0402_16V4Z
SE000006R80
4.7U_0805_25V6-K 2
2
C40
4.7U_0805_25V6-K
C45
2
C85
0.1U_0402_16V4Z
1
+1.5VS_WLAN
R82
1
+3VALW
R85
0_0805_5%
2
1
60mil
2
1
+1.5VS
+3VS_WLAN
R83
0_0805_5%
2
1
@
1
+3VS
1
2
0_0603_5%
2
1
C41
0.1U_0402_16V4Z
C83
0.1U_0402_16V4Z
2
1
C84
0.1U_0402_16V4Z
2
D
SE000006R80
0.1U_0402_16V4Z
+1.5VS_WLAN
+1.5VS
1
R890
RB19 1
{28} EC_PME#
+3VS
R5133
2 0_0402_5%
1
JWLAN1
RB18 1
{14} PCH_PCIE_WAKE#
@
2 0_0402_5%
MINI1_CLKREQ#
{13} MINI1_CLKREQ#
{13} CLK_PCIE_MINI1#
{13} CLK_PCIE_MINI1
C
{13} PCIE_PRX_DTX_N2
{13} PCIE_PRX_DTX_P2
{13} PCIE_PTX_C_DRX_N2
{13} PCIE_PTX_C_DRX_P2
WLAN/ WiFi
+3VS_WLAN
2
0_0805_5%
+3VS_WLAN
R436 1
R438 1
1
{28} E51TXD_P80DATA
{28} E51RXD_P80CLK
2
2
0_0402_5%
BTooth_OFF#_R
0_0402_5%
Debug card using
@
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
G1
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
G2
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
2
0_0603_1%
C
R91
0_0402_5% 1
PLT_RST_BUF#
2
PCH_WL_OFF# {15}
PLT_RST_BUF# {15,26}
PCH_SMBCLK {13,21,27}
PCH_SMBDATA {13,21,27}
USB20_N4 {15}
USB20_P4 {15}
AOAC
W=60mils
+3VS_WLAN
+3VALW
ACES_88956-5204
CONN@
R437
100K_0402_5%
Q19
B
D
1
AO3413L_SOT23-3
S
3
G
C42
1U_0402_6.3V6K
1
2
2
B
2
R50
470K_0402_5%
BTooth_OFF#_R
1
PCH_BT_ON# 2
G
A
Primary Power (mA)
2
S
Q21
R49
SSM3K7002FU_SC70-3
2
G
AOAC_ON
S
Auxiliary Power (mA)
Peak
Normal
+3VS
1000
750
+3V
330
250
250 (wake enable)
+1.5VS
500
375
5 (Not wake enable)
A
Normal
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
D
1
3
Mini Card Power Rating
Power
{28}
Q20
2N7002_SOT23-3
ON_AOAC
1
{16} PCH_BT_ON#
D
3
1
PCH_BT_ON
1.5M_0402_5%
1K_0402_0.5%~D
R54
1
2
2
+5VALW
4
3
2
MiniCard WLan Conn
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
22
of
46
5
4
3
2
1
LCD POWER CIRCUIT
+LCDVDD
+3VS
+3VS
W=60mils
1
2
G
3
1
R63
1K_0402_5%
2
1
S
2
S
3
W=60mils
C61
0.047U_0402_16V7K
C55
4.7U_0805_25V6-K
SE000006R80
Q7
AO3413L_SOT23-3
1 220P_0402_50V7K INVTPWM
2
1 220P_0402_50V7K DISPOFF#
1
2
+3VS
1
C57
10U_0603_6.3V6M
C58
1
2
2
G
C56
0.1U_0402_16V4Z
+3VS
D
1
1
2
2
2
R62
100K_0402_5%
D
Q6
2N7002E-T1-E3_SOT23-3
SB570020110
2
C67
D
1
R61
300_0603_5%
C66
+LCDVDD
1
D
Place closed to JLVDS1
+LCDVDD
0.1U_0402_16V4Z
W=60mils
C62
2
G
SE000006R80
Q8
2N7002E-T1-E3_SOT23-3
SB570020110
1
PCH_ENVDD
3
{14} PCH_ENVDD
1
2
1
2
D
2
S
R64
1
2 1K_0402_5%
R65
1
2 1K_0402_5%
@ C64
@C64
10P_0402_50V8J
C63
0.1U_0402_16V4Z
PCH_LCD_CLK
1
PCH_LCD_DATA
1
@ C65
10P_0402_50V8J
2
2
4.7U_0805_25V6-K
C
C
JLVDS1
+LCDVDD
+LCDVDD
+3VS
EDID
LCD
1
091211 ADD R734 Fix CPT 4sec shut down flash issue
PCH_TXOUT2PCH_TXOUT2+
{14} PCH_TXOUT2{14} PCH_TXOUT2+
R69
100K_0402_5%
2
1
PCH_TXCLKPCH_TXCLK+
{14} PCH_TXCLK{14} PCH_TXCLK+
2
R68
0_0402_5%
2
R67
0_0402_5%
@
PCH_TXOUT1PCH_TXOUT1+
{14} PCH_TXOUT1{14} PCH_TXOUT1+
+3VS
1
+5VS
PCH_LCD_CLK
PCH_LCD_DATA
PCH_TXOUT0PCH_TXOUT0+
{14} PCH_LCD_CLK
{14} PCH_LCD_DATA
{14} PCH_TXOUT0{14} PCH_TXOUT0+
2 0_0402_5%
A
3
2
Y
4
DPST_PWM_1
1
U2
74AHCT1G125GW_SOT353-5
R71
2
0_0402_5%
R73
INVTPWM
{28} BKOFF#
2009/12/15
change P/N to SA00000U500
BKOFF#
LCD Panel Backlight
1
2 0_0402_5%
1
1 R197
P
DPST_PWM
OE#
INVT_PWM
{14}
G
{28}
@
1 R198
5
B
1
INVTPWM
DISPOFF#
2
0_0402_5%
B+
R72
10K_0402_5%
2
VBIOS PWM SETTING
CHANGE TO NORMAL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
GND
GND
GND
GND
GND
B
STARC_111H30-000000-G4-R
CONN@
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/06
Deciphered Date
2011/10/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
LVDS Connector
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
23
of
46
5
4
3
7R&UDGOHERDUGFRQQ
2
ADPIN
1
ADPIN
MB_IN_DET
EC_ON
{28,29,36} EC_ON
C
MB_IN
MB_IN
Q22
MMBT3904_NL_SOT23-3
2
B
E
D
3
FAN_SPEED_CRADLE
FAN_CRADLE
FAN_SPEED_CRADLE {28}
FAN_CRADLE {28}
USB3_RX1_N {15}
USB3_RX1_P {15}
To Cradle Display link
USB3_TX1_N {15}
USB3_TX1_P {15}
USB20_N0
USB20_P0
USB20_N0 {15}
USB20_P0 {15}
USB20_N10
USB20_P10
USB20_N10 {15}
USB20_P10 {15}
To Cradle USB HUB
SPKOUT_R1
SPKOUT_R2
SPKOUT_L2
SPKOUT_L1
ACES_91009-08001
CONN@
B
7RKRPHNH\FRQQ
D17
3
TP_CLK
TP_DATA
TP_CLK
TP_DATA
C
{28}
2
Touch pad
{28}
{28}
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
C
SPKOUT_R1
SPKOUT_R2
SPKOUT_L2
SPKOUT_L1
{30}
{30}
{30}
{30}
D18
1
DOCK_IN_DET#
DOCK_ACIN_DET
MB_IN_DET
{28} DOCK_IN_DET#
{28} DOCK_ACIN_DET
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
AZ5125-02S.R7G_SOT23-3
)RUFUDGOH%$77
EC_SMB_CK1
EC_SMB_DA1
{28,35,37} EC_SMB_CK1
{28,35,37} EC_SMB_DA1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
AZ5125-02S.R7G_SOT23-3
3
1
2
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
1
JCRAD1
B
JHOME1
{28} HOME_KEY
HOME_KEY
1
2
3
4
1
2
3
4
G5
G6
5
6
ACES_88514-00401-071
CONN@
A
A
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/26
Issued Date
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
Title
To cradle/B Connector
Size
A4
Date:
2
Document Number
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
24
1
of
46
A
B
C
D
U22
1
1
HSIP
RREF
48
{13} PCIE_PTX_C_DRX_N1
2
HSIN
3V3_IN
47
{13} CLK_PCIE_CD
3
REFCLKP
CLK_REQ#
46
{13} CLK_PCIE_CD#
4
REFCLKN
PERST#
45
5
AV12
EEDO
44
6
HSOP
EECS
43
7
HSON
EESK
42
1
4.7U_0603_6.3V6K
2 PCIE_PRX_C_DTX_P1
0.1U_0402_10V7K
2 PCIE_PRX_C_DTX_N1
0.1U_0402_10V7K
1
{13} PCIE_PRX_DTX_P1
C197
1
{13} PCIE_PRX_DTX_N1
C198
+ODR_PWR
1
C201
20 mils AV12
2
2
0.1U_0402_10V7K
+3VS
2
20 mils
@
2
1
2
DV33_18
SD_D1_R
SD_D0_R
1
C208
2
5P_0402_50V8C
SD_CLK_R 1
R207
SD_CMD_R
8
GND
GPIO/EEDI
41
9
DV12
MS_INS#
40
Card1_3V3
SD_CD#
39
10
C206
0.1U_0402_10V7K
1
C205
4.7U_0603_6.3V6K
2
1
C203
0.1U_0402_10V7K
2
C202
10U_0603_6.3V6M
1
20 mils DV12
40 mils
40 mils
SD_CLK
2
33_0402_5%
SD_D3_R
+3VS
10 mils R201
{13} PCIE_PTX_C_DRX_P1
C193
E
11
3V3_IN
SP15
38
12
Card2_3V3
SP14
37
13
XD_CD#
SP13
36
14
DV33_18
SP12
35
15
GND
SP11
34
16
SP1
SP10
33
17
SP2
SP9
32
18
SP3
SP8
31
19
SP4
SP7
30
20
SD_D1
SP6
29
21
SD_D0
SP5
28
22
SD_CLK
DV12_S
27
GND
26
SD_D2
25
23
SD_CMD
24
SD_D3
RREF
2
1 6.2K_0603_1%
40 mils
2
C199
1
0.1U_0402_10V7K
CDCLK_REQ# {13}
1
PLT_RST# {5,15,28}
SD_CD#
SP15_SDWP_XDD7
2
C207
1
2
4.7U_0603_6.3V6K
DV12_S
20 mils
1
C209
2
0.1U_0402_10V7K
SD_D2_R
RTS5209-GR_LQFP48_7X7
SA000042A00
+ODR_PWR
3
1
2
2
MOLEX_1040310811
CONN@
1
2
1
2
1
2
C196
0.1U_0402_10V7K
11
12
13
14
1
C200
0.1U_0402_10V7K
SD_D0_R
SD_D1_R
SD_CD#
SP15_SDWP_XDD7
@
C195
10U_0603_6.3V6M
check
SD_CLK_R
DAT2
CD
CMD
VDD
CLK
VSS
DAT0
GND
DAT1
GND
DETECT1GND
DETECT2GND
C194
0.1U_0402_10V7K
+ODR_PWR
1
2
3
4
5
6
7
8
9
10
R202
100K_0402_5%
JSD1
SD_D2_R
SD_D3_R
SD_CMD_R
3
Close to connector
Change to SD connector 10.26
4
4
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/26
Deciphered Date
2011/10/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Card Reader 2 in 1
Size
B
Date:
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
E
25
of
46
A
B
C
D
Main core supply (3.3V)
Close to ball K13, K14
+3VS
Close to ball N2
+3VS_iSSD
R226
+VCCQ_iSSD
iSSD P5 Reserved 1.8V
+1.8VS
P5@
1 R227
2
0_0603_5%
VOUT
FB
3
EN
P4@
1
2
C225
10U_0603_6.3V6M
P4@
APL5317
1
1U_0402_6.3V6K
1
2
P4@
C221
R230
1
2
1 0_0402_5% P4@
{12} SATA_PRX_DTX_P0
{12} SATA_PRX_DTX_N0
C222 1
C223 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_IRX_C_DTX_P0
SATA_IRX_C_DTX_N0
0.1U_0402_16V4Z
2 @
2
R231
{12} SATA_PTX_DRX_N0
{12} SATA_PTX_DRX_P0
2K_0402_5%
C226 1
C227 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
H1
G1
SATA_TX_P
SATA_TX_N
C1
F1
J1
SATA_VSS1
SATA_VSS2
SATA_VSS3
E1
D1
SATA_RX_N
SATA_RX_P
VCCQ3
VCCQ2
VCCQ1
L13
K13
K14
H5
E14
E13
A6
B5
G10
F10
E10
E9
E8
E7
VCC14
VCC13
VCC12
VCC11
VCC10
VCC9
VCC8
VCC7
VCC6
VCC5
VCC4
VCC3
VCC2
VCC1
K10
J10
H10
K7
K6
K5
J5
VDDC4
VDDC3
VDDC2
VDDC1
N2
BG_VIN
SATA
interface
P4@
+3VS_iSSD
1
Controller core supply (1.0V)
+1.5VS
R233
10K_0402_5%
U28
1
5
1
1 R234
2
0_0603_5%
1
GND
2
VOUT
0_0402_5%
4 FB
R236
VIN
G9141T
1
0_0402_5%
@
2
R235
0.1U_0402_16V7K
EVT 20110706
Reserve 0 ohm to
iSSD Reset
0.1U_0402_16V4Z
@
R242
L14
ISSD_PLTRST#
B3
2
1
A7
2
1
R237 10K_0402_5%
0_0402_5% R239 P4@
N6
1
2
N4
EVT 20110708
Reserve P5
B9
B10
1
2
0_0402_5% R241 P4@
DAS
VDDC_CTRL
PWR_RESETN
PD1
Controller
FCEn2_M
FCEn2
FCEn0_M
FCEn0
10K_0402_5%
2
P5@
PAD
PAD
PAD
PAD
PAD
1
2K_0402_5%
iSSD P5 Reserved 1.2V
T42
T43
T44
T45
T46
M12
A9
A10
A11
A12
TP0
JTAG_CLK
JTAG_DO
JTAG_DI
JTAG_TMS
A3
B4
XTAL_OUT
XTAL_IN
Debug
+3VS_iSSD
2
1
2
+VDDC_iSSD
2
1
BLM15BB221SN1D 0402
+3.3V_SATA
2
1
C235
0.1U_0402_16V7K
MAG40
MAG39
MAG38
MAG37
MAG36
MAG35
MAG34
MAG33
MAG32
MAG31
MAG30
MAG29
MAG28
MAG27
MAG26
+VDDC_iSSD
C236
1 0.1U_0402_16V7K
1
1
2
2
1
BLM15BB221SN1D 0402
+1V_SATA
2
1
C239
0.1U_0402_16V7K
MAG40
MAG39
MAG38
MAG37
MAG36
MAG35
MAG34
MAG33
MAG32
MAG31
MAG30
MAG29
MAG28
MAG27
MAG26
SDIS4BH-004G_TFBGA157
R247 1
A1
A2
B1
A5
A13
A14
B13
B14
C13
D13
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
2
C238
C237
2
1U_0402_6.3V6K
R246
+PLL_DVDD
1
BLM15BB221SN1D 0402
1U_0402_6.3V6K
R245
Crystal
B8
N5
B2
A4
P5
A8
F13
H14
F14
C14
B11
B12
N3
M2
P4
P3
M13
M14
P10
N11
P8
N9
P6
N13
N12
P9
N10
N7
P12
P11
P7
N8
J14
J13
L2
L1
K1
MAG1
MAG2
MAG3
MAG4
MAG5
MAG6
MAG7
MAG8
MAG9
MAG10
MAG11
MAG12
MAG13
MAG14
MAG15
MAG16
MAG17
MAG18
MAG19
MAG20
MAG21
MAG22
MAG23
MAG24
MAG25
MAG1
MAG2
MAG3
MAG4
MAG5
MAG6
MAG7
MAG8
MAG9
MAG10
MAG11
MAG12
MAG13
MAG14
MAG15
MAG16
MAG17
MAG18
MAG19
MAG20
MAG21
MAG22
MAG23
MAG24
MAG25
2
T41 PAD
EVT 20110708
Reserve P5
Pin TP0
3
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
C232
1 0.1U_0402_16V7K
3
1
1U_0402_6.3V6K
2
C234
+PLL_AVDD
1
BLM15BB221SN1D 0402
C233
2
25M_XTAL_OUT
25M_XTAL_IN
R244
1U_0402_6.3V6K
R243
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DNU13
DNU14
DNU15
DNU16
DNU17
DNU18
DNU19
DNU20
DNU21
DNU22
DNU23
DNU24
DNU25
DNU26
DNU27
DNU28
DNU29
DNU30
DNU31
DNU32
DNU33
DNU34
DNU35
DNU36
DNU39
N14
P14
P13
P2
P1
F2
K8
K9
G13
D14
G14
H13
J2
K2
N1
M1
B6
C2
+VDDC_iSSD
2
1
10K_0402_5%
0_0402_5% R248 P4@
1
2
C229
2
2
R240
1
{15,22} PLT_RST_BUF#
C228
R238
1
2
1 0_0402_5%
C231
2
2
C230
10U_0603_6.3V6M
1U_0402_6.3V6K
1
2
3
EN
P4@
TFBGA157_iSSD_16X20
2
R232
B7
+VDDC_iSSD
2
2
1
POWER
2
GND
3K_0402_5%
R229
4
P4@
+3VS_iSSD
1
VIN
5
C224
1
+3VS
+3VS_iSSD +VDDC_iSSD +VCCQ_iSSD
U26
2
1 R228
2
0_0603_5%
SATA_VDDC2
SATA_VDDC1
IO core supply (2.0V)
G5
E6
F5
E5
U27
PLL_AVSS
PLL_DVSS
PLL_AVDD
PLL_DVDD
Close to ball H10, J10, K10
Close to ball J5, K5, K6, K7
Close to ball H5
H2
G2
2
+PLL_DVDD
+PLL_AVDD
1
+3.3V_SATA
2
1
+1V_SATA
2
2
C220
2.2U_0402_6.3V6M
2
1
C219
0.1U_0402_16V7K
2
1
C218
1U_0402_6.3V6K
2
1
C217
10U_0603_6.3V6M
2
1
+VCCQ_iSSD
C216
1U_0402_6.3V6K
2
1
C215
10U_0603_6.3V6M
Close to ball E13, E14, H14
1
C214
10U_0603_6.3V6M
2
1
1
C213
10U_0603_6.3V6M
1
C212
10U_0603_6.3V6M
C211
1U_0402_6.3V6K
0_0603_5%
SATA_VCC2
SATA_VCC1
+VDDC_iSSD
2
E2
D2
1
2 1M_0402_5%
Y2
25MHZ_12PF_FSX3M25.000000M12FAQ
25M_XTAL_OUT
1
1
2
25M_XTAL_IN
3
4
C241
C240
4
2
1
4
15P_0402_50V8J
15P_0402_50V8J
2
Sandisk suggest Crystal is Seam type
EVT 20110708
Change to Seam type Crystal
25 MHz,12pF,30 ppm
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/08/27
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
Sandisk iSSD
Size Document Number
Custom
Rev
0.3
LA-8441P
Date:
Monday, November 14, 2011
D
Sheet
26
of
46
A
B
C
D
USB3.0
2
+
C90
G547I2P81U_MSOP8
SA00003TV00
2
U8 CEN#
R190
4.7K_0402_5%
1
C91
2
1
C92
2
{15}
{15}
+5VALW
R210
10K_0402_5%
2
U8
8
7
6
5
USB20_N1
USB20_P1
2
CB
TDM
TDP
VCC
@
SW _USB20_P1
2
USB_OC0#
R88
1
2
0_0402_5%
4
3
DLW 21SN670HQ2L_4P
SM070001R00 L20
1
2
USB3_RX2_N
{15} USB3_RX2_N
R75
R76
1
2
1
USB_OC0# {15}
USB3RXDP2_C
SWP
0_0402_5%
D9
1
9
USB3RXDN2_C
USB3RXDP2_C
2
8
USB3RXDP2_C
USB3TXDN2_C
4
7
USB3TXDN2_C
USB3TXDP2_C
5
6
USB3TXDP2_C
1
1
2
2
4
4
3
3
JUSB1
USB3TXDP2_C
9
1
8
3
7
2
6
4
5
USB3TXDN2_C
1
R70
@
2 0_0402_5%
+3VS
2
R286
10K_0201_5%
U36
NFC_ANT1
NFC_ANT2
1
NFC_EN_1V8
10
9
NFC_SW P_1V8
R291 2 NFC_SIMVCC_1V8
1
0_0201_5% @
16
15
ANT1
ANT2
VEN
VEN_MON
SWIO
SIMVCC
1
R289
10K_0201_5%
2
{12} NFC_EN_1V8
VIh>1.1V
VIL<0.4V
4
5
2
3
6
21
20
19
Default Pull Low 10K
Reserve for NFC SIM Power
25
26
27
NC
NC
NC
NC
NC
NC
GND
GND
GND
VCC
PVDD
PMUVCC
11
13
14
GPIO4
18
IFSEL1
IFSEL2
8
7
IRQ
IFO
IF1
IF2
IF3
17
1
22
23
24
GND
GND
GND
GND
GND
GND
GND
12
28
29
30
31
32
33
GND
1
2
1
C187
0.1U_0402_10V7K
Low
High
Function
NFC Transfer
Data to PCH
GND
R2941
High
R155 1
NFC_ADR1
NFC_ADR2
A
3
3
1
2
1
2
C242
0.1U_0402_10V7K
GND
GND
NFC_IRQ
D
S
2
G
GND
3
{16}
Q18
BSS138W -7-F_SOT323-3
SB000002X00
ANT Finetune Cap
GND
NFC_ANT1
1 NFC_ANT1_C
C338
NFC_ANT2
/&^ >ϭ
/&^ >Ϯ
/&^ddh^
/&Ϭ
/&ϭ
/&Ϯ
/&ϯ
'E
'E
hZd
E
Zy
E
dy
Ws
'E
/Ϯ
Zϭ ZϮ
^
^>
'E
Ws
^W/
E^^
DK^/
^<
D/^K
Ws
Ws
^W/
E^^
DK^/
^<
D/^K
Deciphered Date
C
2
22P_0201_25V8
NFC_ANT2_C
JNFC1
1
2
1
2
3
4
GND1
GND2
ACES_50281-0020N-001
CONN@
4
Compal Electronics, Inc.
Compal Secret Data
2010/04/26
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
1
C190
0.1U_0402_10V7K
20_0201_5%
21K_0402_5%
R2921
20_0201_5%
R2931
20_0201_5%
PCH_SMBDATA {13,21,22}
PCH_SMBCLK {13,21,22}
Security Classification
NFC No
Data to PCH
2
NFC_IRQ#
Issued Date
Low
2
1
GND
LXRW HFAA-001_33P
NFC_IRQ#
ACON_TARA4-9K1311
CONN@
D10
C192
1U_0402_6.3V4Z
2
2
L26
FBMA-L11-160808-800LMT_0603
1
2
C189
1U_0402_6.3V4Z
1
C188
1U_0402_6.3V4Z
1
2
FBMA-L11-160808-800LMT_0603
10
11
12
13
GND
GND
GND
GND
+1.8VS
NFC_1V8
@
USB3RXDN2_C
NFC_3V3
L25
3
2
2
USB3TXDN2_C
USB3RXDP2_C
SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-
1
2
+1.8VS
NFC_IRQ
AZC199-02SPR7G_SOT23-3
YSCLAMP0524P_SLP2510P8-10-9
Part Number = SC300001D00
3
NFC
4
USB20_N1_C
1
{15} USB3_TX2_N
)ROORZ(0,5HTXHVW
8
USB3TXDP2_C
4
DLW 21SN670HQ2L_4P
SM070001R00 L19
1
0.1U_0402_10V7K
USB3_TX2_N
2
1 C94 USB3TXDP2
USB20_P1_C
3
{15} USB3_TX2_P
0_0402_5%
R66 @
2
USB3TXDN2 1
USB20_N1_C
+USB_AS
SWP
USB3RXDN2_C
@
0.1U_0402_10V7K
USB3_TX2_P2
1 C93
USB20_P1_C
W CM2012F2S-900T04_0805
SM070001310
R89 1
0_0402_5%
2
@
SW _USB20_N1
USB3RXDN2_C
3
2
0_0402_5%
2
L22
@
USB3_RX2_P
U8 CEN#
1
0_0402_5%
1
0_0402_5%
{15} USB3_RX2_P
R79
C54
0.1U_0402_16V4Z
R94
1
2
U8 CEN#_R 2
SW _USB20_N1
SW _USB20_P1
1
2
3
4
9
CEN
DM
DP
GND
GND
MAX14566EETA+_TDFN-EP8_2X2
SA000045Z10
1
2
0.1U_0402_16V4Z
1
1000P_0402_50V7K
C89
0.1U_0402_16V4Z
2
1
GND VOUT
VIN VOUT
VIN VOUT
EN
FLG
8
7
6
5
1
C88
1000P_0402_50V7K
1
1
1
2
3
4
150U_B2_6.3VM_R45M
U4
W=80mils
1
@
W=80mils
+USB_AS
2.1A
0.1U_0603_50V_X7R
C138
+5VALW
0_0402_5%
R101
USB_EN#
2
1
USB20_N1
USB20_P1
USB_EN#
1
{28}
E
D
Title
USB Con & Daughter Con
Size
A3
Date:
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
E
27
of
46
5
4
1
1
2
1
1
+5VS
1
C105
1000P_0402_50V7K
2
2
C104
1000P_0402_50V7K
2
1
C103
0.1U_0402_16V4Z
2
C102
0.1U_0402_16V4Z
2
1
C101
0.1U_0402_16V4Z
10K_0402_5%
EC_KBRST#
2
1
1
2
L9
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA
+3VALW_EC
1
C100
0.1U_0402_16V4Z
R90
+3VS
R98
0_0805_5%
2
ECAGND
+3VALW
3
2
TP_CLK
R102
1
2
4.7K_0402_5%
TP_DATA
R107
1
2
4.7K_0402_5%
C106
0.1U_0402_16V4Z
+3VS
D
+3VLP
BKOFF#
R109
1
2 10K_0402_5%
DOCK_IN_DET#
R114
1
2 10K_0402_5%
D
R113
1
2 2.2K_0402_5%
R174
1
2 10K_0402_5%
R125
+3VS
EC_SMB_CK1
{15} CLK_PCI_EC
{5,15,25} PLT_RST#
HOME_KEY
{16}
{22}
EC_PME#
2 10K_0402_5%
1
R120
EC_SMB_DA1
2 2.2K_0402_5%
EC_SCI#
AOAC_ON
CLK_PCI_EC
PLT_RST#
EC_RST#
EC_SCI#
AOAC_ON
12
13
37
20
38
{29}
{24} HOME_KEY
{29}
VOL_UP#
{29} VOL_DOWN#
D_LOCK#
R200 2
ENE_EDI_CS_R
R136 1
ENE_EDI_CLK_R R129 1
ENE_EDI_DI_R
R142 1
ENE_EDI_DO_R
R140 1
D_LOCK#
1
2
2
2
2
HOME_KEY
VOL_UP#
VOL_DOWN#
0_0402_5%
0_0402_5% ENE_EDI_CS
0_0402_5% ENE_EDI_CLK
0_0402_5% ENE_EDI_DI
0_0402_5% ENE_EDI_DO
C
R126
1
R127
1
R128
1
R130
1
100K_0402_5%
2 PLT_RST#
10K_0402_5%
2 PCH_DPWROK
10K_0402_5%
2 PCH_PWROK
10K_0402_5%
2 VR_ON
KSO3
{24,35,37} EC_SMB_CK1
{24,35,37} EC_SMB_DA1
{13} PCH_SML1CLK
{13} PCH_SML1DATA
JECDG1
KSO3
ENE_EDI_DI_R
ENE_EDI_DO_R
ENE_EDI_CS_R
ENE_EDI_CLK_R
EC_TX
EC_RX
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
EC_SMB_CK1
EC_SMB_DA1
R121 1
R122 1
2 0_0402_5%
2 0_0402_5%
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
{14} PM_SLP_S3#
{14} PM_SLP_S5#
{16}
EC_SMI#
{31} PCH_PWR_EN
{14} PCH_DPWROK
GND1
GND2
ACES_50521-0084N-P01
CONN@
near JECDG1 conn.
B
EC_TX
R149 1
@
2
E51TXD_P80DATA
0_0402_5%
EC_RX
R150 1
@
2
E51RXD_P80CLK
0_0402_5%
PCH_DPWROK
R212 1
{23}
INVT_PWM
{29} FAN_SPEED1
{24} FAN_SPEED_CRADLE
{22} E51TXD_P80DATA
{22} E51RXD_P80CLK
{14} PCH_PWROK
{14}
@
EC_GPIOB
20_0402_5%
FAN_SPEED1
FAN_SPEED_CRADLE
E51TXD_P80DATA
E51RXD_P80CLK
PCH_PWROK
77
78
79
80
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
122
123
SUSCLK_R
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A
XCLKI/GPIO5D
XCLKO/GPIO5E
EC_GPIOB
1
2
C46
@
20P_0402_50V8
KB9012QF-A3_LQFP128_14X14
SA00004OB20
67
BEEP#
1 R213
0_0402_5% 2
C108 2
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43
63
64
65
66
75
76
BATT_TEMP
0_0402_5% 2
ADP_I
R60
{30}
PCH_DPWROK
1 100P_0402_50V8J
ADP_I
PCH_DPWROK
DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F
PS2 Interface
CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
ME_EN/GPXIOA02
VCIN0_PH/GPXIOD00
SUSACK#
EN_DFAN1
FAN_CRADLE
83
84
85
86
87
88
EC_MUTE#
USB_EN#
R74 2
ECAGND
PCH_HOT#
97
98
99
109
SPI Device Interface
SPI Flash ROM
GPIO
Bus
GPIO
SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A
EC_ACIN
C109
ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59
EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11
AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
V18R
20mil
{14,37}
1 100P_0402_50V8J
VR_HOT
VR_HOT
R118
0_0402_5%
2
1
H_PROCHOT#_EC
H_PROCHOT#
D
S
2
G
{16}
+3VLP
0_0402_5% 2
SYSON
VR_ON
PM_SLP_S4#
1
1
1
1
PCH_RSMRST#
110
112
114
115
116
117
118
EC_ACIN
EC_ON
ON/OFF
LID_SW#
SUSP#
124
+V18R
9012Pin102
H_PROCHOT#_EC
0_0402_5%
2 R222
BKOFF#
PBTN_OUT#
SUSWARN#
SA_PGOOD
{35} VCIN1_PH
R220
0_0402_5%
2
1
9012Pin102
R203
47K_0402_5%
2
1
{35}
{24}
ENBKL
DOCK_IN_DET#
DOCK_ACIN_DET
R218 1
100
101
102
103
104
105
106
107
108
C
CPU1.5V_S3_GATE {9}
DRAMRST_CNTRL_EC
{6}
ME_EN
{12}
2
VCIN0_PH
R221
MB_IN
R134
R137
R138
R217
2
2
2
2
{5}
2N7002_SOT23
Q10
TP_CLK
{24}
TP_DATA {24}
MB_IN
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
{13}
{14}
EN_DFAN1 {29}
FAN_CRADLE {24}
EC_MUTE# {30}
USB_EN# {27}
1 0_0402_5%
DS3_WAKE#
CPU1.5V_S3_GATE
DRAMRST_CNTRL_EC
ME_EN
9012Pin109 1
0_0402_5%
119
120
126
128
73
74
89
90
91
92
93
95
121
127
SUSACK#
TP_CLK
TP_DATA
ACIN
SCS00000Z00
RB751V-40_SOD323-2
{14}
{35,37}
1 0_0402_5%
68
70
71
72
1
BATT_TEMP {35}
EC_PME# {22}
1 R124
2
ENBKL {14}
DOCK_IN_DET# {24}
DOCK_ACIN_DET {24}
BATT_CHG_LED# {29}
RFLED#
PWR_LED#
BATT_LOW_LED#
SYSON {31,39,40}
VR_ON
{43}
PM_SLP_S4# {14}
{29}
PCH_RSMRST# {14}
EC_LID_OUT# {16}
1
VCOUT0_PH
BKOFF#
{23}
PBTN_OUT# {14}
SUSWARN# {14}
SA_PGOOD {38}
{36}
B
EC_ON
ON/OFF
LID_SW#
SUSP#
1
R123
2
DS3@
1 R4934 2
0_0402_5%
SLP_SUS#
D5
{43}
DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
100K_0402_5%
2 R55
1
{14} SLP_SUS#
AD Input
CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D
1 200K_0402_5%
2
2
21
23
26
27
PWM Output
2 10K_0402_5% EC_SCI#
1
R112
GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
AGND/AGND
1
EC_SMI#
2 1K_0402_5%
69
R111
@
GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0LPC & MISC
GND/GND
GND/GND
GND/GND
GND/GND
GND0
1
1
2
3
4
5
7
8
10
1
10/1 ENE Recommand
R110
GATEA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
3
{16}
GATEA20
{16} EC_KBRST#
{12}
SERIRQ
{12} LPC_FRAME#
{12}
LPC_AD3
{12}
LPC_AD2
{12}
LPC_AD1
{12}
LPC_AD0
1
+3VALW
+3VLP
EC_VDD/AVCC
U5
0.1U_0402_16V4Z
1
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC
EC_RST#
1 47K_0402_5%
C107 2
11
24
35
94
113
R106 2
+3VALW
9
22
33
96
111
125
For KB9012
H_PECI
2
43_0402_1%
{24,29,36}
{29}
{29}
{9,31,39,40,41}
H_PECI
{5,16}
C113
SE000006R80
4.7U_0805_25V6-K
L10
ECAGND 2
1
FBMA-L11-160808-800LMT_0603
A
A
Compal Secret Data
Security Classification
Issued Date
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Size
C
Date:
5
4
3
2
Compal Electronics, Inc.
EC ENE-KB930 & 9012
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
28
of
46
+3VALW
7R,2%RDUGFRQQ
+3VLP
+3VALW
+5VALW
92/80(6:
+3VS +3VALW
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
{12} SATA_PRX_DTX_N1
{12} SATA_PRX_DTX_P1
mSATA
{12} SATA_PTX_DRX_N1
{12} SATA_PTX_DRX_P1
1
BAV70W _SOT323-3
SC600000B00
EC_ON
D
2
G
3
2
{24,28,36} EC_ON
R132
G Lock
LID SW
Power LED
S
Q11
2N7002E-T1-E3_SOT23-3
SB570020110
D_LOCK
LID_SW #
{28} D_LOCK#
{28} LID_SW #
{28} BATT_LOW _LED#
{28} BATT_CHG_LED#
1
10K_0402_5%
D_MIC
Audio HP
)$1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
{15} UW B_OFF#
{15}
GPS_OFF#
{30} DMIC_DATA
{30} DMIC_CLK
ON/OFFBTN#
UW B_OFF#
GPS_OFF#
EXT_MIC_L2
HPL
HPR
HP_JD
{30} EXT_MIC_L2
{30}
HPL
{30}
HPR
{30}
HP_JD
+5VS
C167
1
10U_0603_6.3V6M
2
U11
2
R172
+VCC_FAN1
1
300_0402_5%
GND
GND
GND
GND
0_0805_5%
2
0_0805_5%
AGND
8
7
6
5
GND
APL5607KI-TRG_SO8
1
2
EN
VIN
VOUT
VSET
C168
0.1U_0402_16V4Z
1
{28} VOL_DOW N#
SKRELGE010_2P
+3VS
0_0402_5%
2
1
JCMA1
1
2
3
4
5
6
7
8
9
10
11
12
R29
L6
JFAN1
1
2
3
C171
1000P_0402_50V7K
{15}
1
2 GND
3 GND
USB20_P6
USB20_N6
USB20_P6
3
USB20_N6
2
3
4
4
USB20_P6_R
USB20_N6_R
1
2
@ 1
W CM-2012HS-900T_0805
4
5
2
1
0_0402_5%
R30
ACES_88231-03041
CONN@
ACES_50463-0104A-001
D1
PJESDZ6V8-2G_SOT-523-3
@
CONN@
1
2
1
2
3
4
5
6
7
8
9
10
GND
GND
2
2
40mil
1
VOL_UP#
VOL_DOW N#
SW 1
&0$FRQQ
{15}
+VCC_FAN1
R384
AGND
R173
10K_0402_5%
{28} FAN_SPEED1
R383
GND
C170
1000P_0402_50V7K
1
2
1
SKRELGE010_2P
VOL_DOW N#
C169
10U_0603_6.3V6M
1
2
+3VS
SW2
GND
3
EN_DFAN1
1
2
3
4
+3VS
VOL_UP#
VOL_UP#
ACES_88194-3041
CONN@
Reserved
for2 TEST
1
R169
1
R168
GND
GND
10K_0402_5%
1
2
{28}
USB20_N5
USB20_P5
USB20_N5
USB20_P5
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2
ON/OFF
1
3
{28}
{15}
{15}
PS_OUT
PS_OUT
{28}
1
SIM card
2
ON/OFFBTN#
R141
100K_0402_5%
{21}
1
D6
For P sensor
32
31
2
1
@
R170
100K_0402_5%
1
R131
100K_0402_5%
2
2
2
JIO1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10K_0402_5%
1
2
212))%71
0_0402_5%
@
2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%
1
1
{15}
USB20_P7
{15}
USB20_N7
USB20_P7
USB20_N7
3
2
3
4
JCMA2
4
USB20_P7_R
USB20_N7_R
1
2
3
4
5
6
1
@ 1
W CM-2012HS-900T_0805
2
2
0_0402_5%
1
R32
1
2
3
4
5 G1
6 G2
7
8
ACES_88460-00601-P01
CONN@
D7
PJESDZ6V8-2G_SOT-523-3
@
@
1
@
FD2
@
@ FIDUCIAL_C40M80
FD3
1
FD1
1
R92 1
R87 1
R86 1
@
@
FIDUCIAL_C40M80
FD4
@
FIDUCIAL_C40M80
1
H11
H13
H_5P2x4P2
H_5P2x4P2
HOLEA HOLEA
1
TS_RES
TS_STOP
TS_FLASH
@
R31
L8
H6
H7
H_4P4 H_4P4
HOLEAHOLEA
@
1
2
H10
H12
H_3P3 H_3P3
HOLEAHOLEA
@
2
1
@
@
1
@
1
1
H9
H_3P3
HOLEA
1
ACES_87036-1001-CP
CONN@
H8
H_3P3
HOLEA
@
H5
H_2P5
HOLEA
1
1
2
3
4
5
6
7
8
9
10
GND
GND
@
H3
H4
H_2P5 H_2P5
HOLEAHOLEA
1
TS_STOP
TS_RES
1
2
3
4
5
6
7
8
9
10
11
12
H2
H_2P5
HOLEA
1
TS_FLASH
USB20_P2
USB20_N2
USB20_P2
USB20_N2
1
JTS1
1
H1
H_2P8
HOLEA
1
+3VS
{15}
{15}
+3VS
+B3[+B3[+B3[
+B3[3[+B3[
3
7RXFK6FUHHQ&211
Issued Date
@
FIDUCIAL_C40M80
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
I/O Port / CMA / FAN
Size
A3
Date:
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
29
of
46
A
B
C
D
place close to chip
AGND
+3VS_DVDD
EXT_MIC_MV_R
39.2K_0402_1%
1
R145
2
1
COMBJACK
2
0_0402_5%
100P_0402_50V8J
2
1 20K_0402_1%
MONO_IN
AC_JDREF 2 R152
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
CBP
R148
HP_JD
HP_JD
{29}
0RGLI\
MIC1_VREFO_L
1 C143
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
{12}
{12}
R146
2.2K_0402_5%
1
C162
2
@
EXT_MIC_MV_R
)ROORZ(0,5HTXHVW
L15
R214
1
2
1K_0402_5%
2
R135
+PVDD
600 mA
C122
0.1U_0402_16V4Z
GND
2
2
1
C124
0.1U_0402_16V4Z
AGND
1
1
2
1
R153
22K_0402_5%
+5VS
0_0603_5%
C125
2 10U_0805_10V4Z
2
EXT_MIC_L2
1
BK1608HS601-T_2P
1
100P_0402_50V8J
SENSE_A
External MIC
1
C132
1
C137
100P_0402_50V8J
25
38
AVDD2
AVDD1
CPVEE
9
ALC269Q-VC2-GR
Part Number = SA000028N60
PCB Footprint = ALC269Q-VC2-GR_QFN48_6X6
10mil
20
47
48
12
19
10
6
36
2
4.7U_0603_6.3V6K
2
4.7U_0603_6.3V6K
100P_0402_50V8J
1
U7
MIC1_R
13
18
MONO-OUT(PORT-H)
EAPD/COMB-JACK
SPDIF-OUT
PCBEEP
JDREF
SYNC
BCLK
CBP
RESET#
LDO-CAP
VREF
PD#
CBN
2.2U_0603_6.3V4Z
MIC1_L
21
22
23
24
PVDD2
C144
14
15
Sense A
Sense B
37
R103
4.7K_0402_5%
2
7
MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO
SDATA-OUT
SDATA-IN
2
16
17
MIC1-L(PORT-B-L)
MIC1-R(PORT-B-R)
LINE1-L(PORT-C-L)
LINE1-R(PORT-C-R)
PVDD1
11
28
27
4
35
1
AGND
46
31
30
29
5
8
SPK-OUT-R+
SPK-OUT-RSPK-OUT-LSPK-OUT-L+
39
MIC1_VREFO_L
@
1
2
R147
0_0402_5%
HDA_SDOUT_AUDIO
{12} HDA_SDOUT_AUDIO
HDA_SDIN0
SDIN_CODEC
2
1
{12} HDA_SDIN0
33_0402_5%
R144
HDA_RST_AUDIO#
{12} HDA_RST_AUDIO#
10U_0805_10V6M 2
1 C151
AC_VREF
PD#
1
2
EC_MUTE#
CBN
R143
0_0402_5%
1
2 CBP
+5VS
49
MIC2-R(PORT-F-L)
MIC2-R(PORT-F-R)
PVSS2
45
44
41
40
2
{28}
SPKOUT_R1
SPKOUT_R2
SPKOUT_L2
SPKOUT_L1
SPKOUT_R1
SPKOUT_R2
SPKOUT_L2
SPKOUT_L1
2
2
ALC269Q-VC2-GR_QFN48_6X6
10U_0805_10V4Z 0.1U_0402_16V4Z
LINE2-R(PORT-E-L)
LINE2-R(PORT-E-R)
GPIO0/DMIC-DATA
GPIO1/DMIC-CLK
AVSS2
{24}
{24}
{24}
{24}
C136
1
place close to chip
HPOUT-L(PORT-A-L)
HPOUT-R(PORT-A-R)
PVSS1
2
3
1
C134
THERMAL PAD
42
32
33
{29} DMIC_DATA
{29} DMIC_CLK
26
HP_OUTL
HP_OUTR
Headphone
DVDD-IO
DVDD
GND
R133
0.1U_0402_16V4Z 2
1
FBMH1608HM601-T
SM01000B200
1
C131
68 mA
1
34
2
1
2
2
43
C128
+AVDD
C146
35 mA
place close
to chip
1
DVSS
C120
1
1
CPVEE
1U_0402_6.3V6K
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
AVSS1
R139
2
1
0_0603_5%
+3VS
E
C145
2
1
C147
2
R151
AC_VREF
0.1U_0402_16V4Z
0RGLI\
COMBJACK
1
2
EXT_MIC_L2
EXT_MIC_L2 {29}
22K_0402_5%
1
C150
2
2
1U_0402_6.3V6K
1
C149
1
C148
2 10U_0603_6.3V6M
3
3
1
@
1
C161
@
1
HP_OUTR
1 R157
BLM15AG121SN1D_L0402_2P
2 HP_R
1
2
75_0603_1%
L16
HP_OUTL
1 R158
2 HP_L
1
75_0603_1%
L17
C156
470P_0402_50V7K_X7R
1
HPR
HPL
2
BLM15AG121SN1D_L0402_2P
W=10mils
+AVDD
R156
10K_0402_5%
2
2
1
1
HPR
{29}
HPL
{29}
C157
470P_0402_50V7K_X7R
AGND
C153
2
@
C160
HDA_BITCLK_AUDIO
2
10P_0402_50V8J
2
C159
HDA_SDOUT_AUDIO
2
10P_0402_50V8J
HDA_SYNC_AUDIO
10P_0402_50V8J
W=10mils
2
1
1
1U_0603_10V4Z
R159
10K_0402_5%
2
560_0402_5%
1
R154
CA31 1
2 0.1U_0402_16V4Z
Q13
2
B
3
E
2
0_0805_5%
2
0_0805_5%
C158
1
2
HDA_SPKR
R164
1
1U_0603_10V4Z
1
R163
2
560_0402_5%
2
1
HDA_SPKR
SB Beep
GND
D8
RB751V_SOD323
2
47K_0402_5%
R165
10K_0402_5%
2
1
R166
1
R167
HDA_RST_AUDIO#
1
{12}
4
2SC2411K_SC59
R162
2.4K_0402_5%
C142
0.1U_0402_16V7K
4
1
2 0.1U_0402_16V4Z
1U_0603_10V4Z
1
2
C
)ROORZ(0,5HTXHVW
2
2 0.1U_0402_16V4Z
CA29 1
MONO_IN
2
2
47K_0402_5%
CA27 1
+3VS
C155
1
1U_0603_10V4Z
R160
4.7K_0402_1%
R161
1
1
2
EC Beep
C154
1
2
BEEP#
2
BEEP#
1
{28}
AGND
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
HD AUDIO CODEC ALC269Q_VC2
Size
C
Date:
A
B
C
D
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
E
30
of
46
C
+5VALW
+3VALW to +3VS
+5VS
+3VALW
Q5508
AO4478L 1N SO8
S
+VSB
1
100K_0402_5%
2
1
Q5509
2 SUSP
G
2N7002_SOT23-3
SUSP
D
1
S
Q5510
2N7002_SOT23-3
2
2
G
2
1
C5519
10U_0805_10V4Z~D
1
C5536
2
2
8
7
6
5
1
C5514
10U_0805_10V4Z~D
2
R5507
1
+VSB
@
R5525
0_0402_5%
PCH_PW R_EN#
1
2
3
C5518
10U_0805_10V4Z~D
D
1
S
Q5511
2N7002_SOT23-3
2
2
G
1
1
C5522
2
100K_0402_5%
2
1
R5506
D
@
R5524
0_0402_5%
2
C5517
10U_0805_10V4Z~D
1
3
C5511
10U_0805_10V4Z~D
1
2
3
4
2
1
1U_0603_10V4Z
8
7
6
5
2
R5504
470_0603_5%
1
2
1
3
Q5507
2N7002_SOT23-3
2
1
3
S
2
G
C5521
1
4
1
+3V_PCH
Q5506
AO4478L 1N SO8
C5537
0.1U_0603_50V_X7R
D
+3VALW
+3VS
C5535
0.1U_0603_50V_X7R
SUSP
100K_0402_5%
2
2
C5520
0.1U_0603_50V_X7R
1
1
+5VS_D
R5505
+VSB
C5513
10U_0805_10V4Z~D
1
2
3
C5532
10U_0805_10V4Z~D
C5512
1U_0603_10V4Z
1
2
1
+3VALW to +3V_PCH
Q5505
AO4478L 1N SO8
1
2
3
10U_0805_10V4Z~D
1
8
7
6
5
E
C5538
2
1U_0603_10V4Z
+5VALW to +5VS
D
10U_0805_10V4Z~D
B
4
A
1
@
R5526
0_0402_5%
+5V_PCH
R5527
@
0_0402_5%
+5VALW
+5VALW
1
+5VALW
2
1
+5VALW to +5V_PCH
2
Q5515
2
2
2
1
S
Q5512
2N7002_SOT23-3
2
G
{9,28,39,40,41} SUSP#
1
S
1
R5515
10K_0402_5%
2
2
R5517
10K_0402_5%
D
3
2
1
Q5513
2N7002_SOT23-3
3
1
1
1
2
SUSP
D
2
G
{28,39,40} SYSON
R5509
100K_0402_5%
C5540
0.1U_0603_50V_X7R
R5511
20K_0402_5%~D
@
2
2
SYSON#
C5541
0.1U_0603_50V_X7R
AO3413_SOT23
1
C5543
0.1U_0603_50V_X7R
1
G
PCH_PW R_EN#
R5510
100K_0402_5%
20mil
D
S
3
@
3
3
+3VS
R5518
R5513
470_0402_5%
470_0402_5%
2
S
6
Q5527A
SUSP
2
1
1
PCB
D
2
G
2N7002DW-7-F_SOT363-6
4
Q5514
SYSON#
3
3
2
4
R5519
100K_0402_5%
5
2N7002DW-7-F_SOT363-6
1 2
3
1
Q5528B
SUSP
+1.5VS_D
Q5529
SSM3K7002FU_SC70-3
+1.5V_D
S
+3VS_D
D
2
G
SSM3K7002FU_SC70-3
2
2
1
470_0402_5%
R5516
100K_0402_5%
PCH_PW R_EN#
1
1
1
R5514
{28} PCH_PW R_EN
+1.5VS
+1.5V
+5VALW
4
ZZZ1
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/04/26
Issued Date
LA-8441P
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DA80000SF00
A
B
C
D
Title
DC Interface
Size
A3
Date:
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
E
31
of
46
5
4
3
2
1
EN_DFAN1
VCOUT0_PH
QAZ50 Power Rail
2011/10/03
+5VALW
+5VALWP
B++
EC_ON
U11 ,
APL5607
RH278
+5VALW
R13
PL7
PU4
RT8205
PL5
B+
PCH_PWR_EN
PJP3
+5V_PCH
U25
SLG59M232
PL6
+3VALW
PJP4
+3VALW
+3VALWP
+3VALW
D
+5VS
U24
SLG59M232
+3VS
+3V_PCH
J1
+3VLP
+5VALW
+3V_PCH
HDMI_5V_OUT
F1
SUSP#
D
+5VALW
+VCC_FAN1
+5V_PCH
+3VALW
VTTPWRGOOD
ADPIN
Vin
P3
P2
PL10
P1
PU11
TPS51461
PL15
+VCCSA
EN_WOL
Q4
C
JDCIN1
PL1
PD7
PQ8
SUSP#
PR32
PL8
PU3
ISL9519
BATT+
PU5
SY8032
C
PL9
+1.8VSP
PJP6
+1.8VS
CPU1.5V_S3_GATE
SUSP#
PL17
BATT++
+LAN_IO
PU17
SY8032
PL19
+1.5VSP
PJP7
+1.5VS
PU17
SY8032
+1.5VS_CPU_VDDQ
SUSP
VCOMP1
SYSON
PL4
PJP12
PD6
+1.5V
PU9
RTS8207
PL14
+1.5VP
Q14
+1.5VS
+1.5V
PJP13
B+
PJPB1
PL2
PQ10
PR42
+0.75VS
SUSP#
B
PU8 ,
TPS51212
PL11
B+
PL13
B
+VCCP
CPU_B+
PL901
PU901
RT8165B
B+
PL902
PQ907
PL905
L7
+VGFX_CORE
DISPOFF#
PD12
B+
+CPU_CORE
GFX_B+
PL18
INVPWR_B+
PQ901
PU6
TPS61187
PL16
+LG_VOUT
A
A
Compal Secret Data
Security Classification
Issued Date
2010/04/26
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
Power Sequence
Size
C
Date:
5
4
3
2
Compal Electronics, Inc.
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
32
of
46
A4
B7
10
5
PBTN_OUT#
106
6
PM_SLP_S3#
127 PM_SLP_S4#
14 PM_SLP_S5#
BKOFF#
105
108
L10 L22
C21
SYS_PWROK
14
PCH_PWROK
10
14
4
PCH_RSMRST#
E20
SYS_PWROK (NC)
H4
6
11
B13
PM_DRAM_PWRGD
D10
C6
12
AND Gate OD
UC2
PM_DRAM_PWRGD_R
7409
H_CPUPWRGD
AY10
F4
V
PU6 ,TPS61187
+LG_VOUT (+40V)
for LED LCD
V
C
16
P12
RH204(NC)
100
114
UH1
PCH_APWROK
107
B6
ON/OFF
DISPOFF#
112
V
Power Switch
A5
R212(NC)
D
E22
PCH_PWROK (RH11)
32
PLT_RST#
BUF_CPU_RST#
UC1
BE45
B46
CPU
13
15
7407
UCPU1
D44
C
Buffer OD
32 121 97 116
V
EC_ON
PCH
V
B1
2
18
V
4
V V
B7
+3VALW
+5VALW
PCH_DPWROK
VV
13
2
95
SYSON
7
SYSON
V
RT8205
A5
PCH_RSMRST(RH199)
V
B5
V
B+
A3
PU4
VV
ISL9519
B2
V
A2
V V
BATT
MODE
BATT++
PU3
V
V V
VIN
D
V
AC
MODE
+3VALW
+5VALW
3
U5
EC 9012 A3
A1
1
U25,
SLG59M232
V
13
PCH_PWR_EN#
2
16
2
V
PLT_RST#
V
15
3
V
4
V V
5
AND
7408 Gate
UH3
PU9 ,RT8207 +1.5VP
(1.35V , 1.5V)
7
U24 +3VS,+5VS
SLG59M232
PU9 ,RT8207
+0.75VSP
PU5 ,+1.8VS
SY8032
SUSP#,SUSP
V
B
10
VTTPWRGOOD
PU11,TPS51461
+VCCSA (+0.85V)
B
8b
V
SA_PGOOD
For PCH 1.5V
Q14,AO3413
(Support DDR3L
+1.5VS (Switch) Function)
V
8
8a
V
V
8
14
PCH_PWROK
SUSP#,SUSP
PU8,+VCCP
1.05V ,
TPS51212
VGATE
VV
8
V
8b
SUSP#,SUSP
10
PCH_PWROK
SA_PGOOD
SYSON (NC)
PU17,+1.5VS,
SY8032
V
LA-8101P Power Sequence
2011/10/03
For Chief River
QC4 ,AO4728L
+1.5V_CPU_VDDQ
9
PU901,RT8165B
+CPU_CORE,
+VGFX_CORE
A
V
A
V
VR_ON
V
7.5
CPU1.5V_S3_GATE
LA-8441P
Compal Secret Data
Security Classification
2010/04/26
Issued Date
Deciphered Date
2011/10/18
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Size
A3
Date:
EE PIR
Document Number
Rev
0.1
LA-8101P
Monday, November 14, 2011
Sheet
1
33
of
46
5
4
3
ADPIN
2
1
VIN
PL1
HCB2012KF-121T50_0805
2
D
2011/07/12
deletet pre-charge circuit
PC4
1000P_0402_50V7K
2
1
1000P_0402_50V7K
1
PC2
2
1
2
PC1
100P_0402_50V8J
1
PC3
100P_0402_50V8J
2
1
D
2011/10/17
change to DCIN connector
2011/10/21
delete the DCIN connector for QAU20
C
C
2011/07/06
for KB9012 only, delete the 51_ON# circuit
B
B
2011/06/27
change PU1 from SOT89-3 to SOT23-5
2011/10/26
delete the RTC battery and the +CHGRTC circuit
A
A
Compal Secret Data
Security Classification
Issued Date
2009/12/01
2010/12/31
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PWR-DCIN / Vin Detector
Size Document Number
Custom
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
34
of
46
5
PJPB1 battery connector
2011/07/06
change 14 pin to 12pin
2011/07/12
swap the BATT+ and GND
change 12 pin to 14 pin
2011/07/20
change the battey pin definition
3
PH1 under CPU botten side :
CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C
BATT+
PL2
HCB4532VF-800T90_2P
2
1
BATT++
1
BATT++
For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 --> Remove PU1 circuit, but keep PR18
PH1, PR79, PQ19, PR21,PR88, PR87
VCIN0_PH-->NTC_V
VCIN1_PH-->Turbo_V
1
PC9
0.01U_0402_25V7K
2
2
PC10
1000P_0402_50V7K
BI
PR17
1K_0402_1%
PJPB1
2011/10/24
delete G718 circuit for EN9012
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
+3VALW
Place clsoe to EC pin
PR19
6.49K_0402_1%
2BATT_TEMP
BATT_TEMP {28}
2
PR20
1K_0402_1%
+3VLP
+3VALW
C
PC12
.1U_0402_16V7K
VCIN1_PH {28}
1
1
1
1
2
EC_SMB_DA1 {24,28,37}
ACES_88231-14001
Part Number = SP02000I400
@
1
ADP_I {28,37}
EC_SMB_CK1 {24,28,37}
PR90 @
20.5K_0402_1%
PR86
20.5K_0402_1%
PR79
10K_0402_1%
2
2
PR23
1 100_0402_1%
2
2
1
2
C
1
D
BATT+
PJPB1 battery
connector
2011/10/20 , Power 4
modify to SP02000I400
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND
GND
2
2011/10/20
change to PL2 Bead
2011/11/08
change to SM01000JR00
2
D
4
VCIN0_PH {28}
PR24
100_0402_1%
1
1
PR21
10K_0402_1%
2
PH1
100K_0402_1%_NCP15WF104F03RC
B
B
PQ77
TP0610K-T1-E3_SOT23-3
3
1
+VSB
2
@
@P
PC245
0.1U_0603_25V7K
2
1
2
1
2
VL
PC241
C241
0.22U_0603_25V7K
PR263
22K_0402_1%
1
2
2
1
PR262
100K_0402_1%
B+
2
A
1
D
3
SPOK
1
{36}
PR265
1K_0402_5%
1
2
S
2011/11/14
add +VSPB circuit for HW
PQ78
SSM3K7002FU_SC70-3
2
G
PC240
1U_0402_6.3V6K
1
PR264
100K_0402_1%
A
Compal Secret Data
Security Classification
Issued Date
2009/12/01
2010/12/31
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PWR-BATTERY CONN
Size Document Number
Custom
Rev
0.1
LA-8441P
Date:
Sheet
Monday, November 14, 2011
1
35
of
46
A
B
C
D
E
2VREF_6182
2011/11/04
change PL5 to PJP5
PC45
1U_0603_10V6K
PR55
13.7K_0402_1%
1
B++
B+
2
PR57
20K_0402_1%
1
2
1
FB_3V
FB_5V 1
1
2011/10/21
Add to PC121,PC122
change PQ14:8065,PQ16:8059
change PC56 & Add PC123
2
1
1
2011/10/20
change to PL6,PL7 choke
2011/11/09
re-link PQ13
PR56
30.9K_0402_1%
2
PR58
20K_0402_1%
2
B++
LGATE1
LG_5V
NC
PQ16
4
18
VIN
VREG5
17
16
GND
15
EN
13
19
PL7
1UH_PCMB062D-1R0MS_9A_20%
1
2
1
2
3
3
2
1
1
TPCA8059-H_PPAK56-8-5
2
1
2
PC60
4.7U_0805_10V6K
N_3_5V_001
5VALWP
TDC 6.1A
Peak Current 8.8A
OCP current 10.5A
PC61
0.1U_0603_25V7K
2VREF_6182
1
4
2
PR68
100K_0402_5%
VL
+
2
2011/03/18
Change Cout from D2
type to B2 type
(PC56/PC55)
PJP4
+3VALWP
1
2
+3VALW
(4A,120mils ,Via NO.= 6)
+5VALW
(5A,180mils ,Via NO.= 9)
PAD-OPEN 4x4m
PJP3
+5VALWP
PR71
0_0402_5%
1
2
1
2
1
PC123
150U_D2_6.3VY_R15M
PAD-OPEN 4x4m
{28} VCOUT0_PH
PQ18
PDTC115EU_SOT323-3
4
1
+
2011/03/18
Delete one jump for 3/5 V ourput
2011/11/09
PC123 need close to CPU_CORE input
2
4
3
1
2
PC124
4.7U_0603_6.3V6K
2
Compal Secret Data
Security Classification
2007/08/02
Issued Date
2008/08/02
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
1
2011/03/18
Change Low side
MOSFET from SO-8 to
DFN8-5 (PQ15/PQ16)
SSM6N7002FU-2N_SOT363-6
1
+5VALWP
3
5
PR84
0_0402_5%
1
2
@
1
1
2
PC59
1U_0402_10V6K
2
1
B++
2
ENTRIP2
3
@
PQ17B
2
2
1
PR83
402K_0402_1%
LX_5V
@
SSM6N7002FU-2N_SOT363-6
@
20
TPCA8065-H_PPAK56-8-5
PC56
150U_D2_6.3VY_R15M
LGATE2
2
PC58
680P_0603_50V7K
PHASE1
14
5
1
PHASE2
VL
ENTRIP1
2
21
AON7702L_DFN8-5
PQ17A
{24,28,29} EC_ON
B+
22
UGATE1
BST_5V 1 PR62 2
2.2_0603_5%
UG_5V
PC54
0.22U_0603_16V7K
BST1_5V 1
2
RT8205LZQW(2) WQFN 24P PWM
6
3
12
BOOT1
UGATE2
5
4
SPOK {35}
PR64
4.7_1206_5%
2
1
24
23
BOOT2
PR69
0_0402_5%
1
2
PR67
200K_0402_1%
@
3.3VALWP
TDC 6A
Peak Current 8.6A
OCP current 10.3A
1
2
LG_3V
4
SNUB_3V
+
11
PQ15
2
1
9
UG_3V 10
LX_3V
@
PC57
680P_0603_50V7K
PC55
150U_B2_6.3VM_R35M
+3VALWP
PR63
4.7_1206_5%
PL6
4.7UH_PCMB062D-4R7MS_5A_20%
1
2
BST_3V
PC49
0.1U_0402_25V6
2
1
PC50
2200P_0402_50V7K
2
1
PC51
4.7U_0805_25V6-K
2
1
PC121
4.7U_0805_25V6-K
2
1
PC122
4.7U_0805_25V6-K
2
1
ENTRIP1
3
2
FB1
REF
4
5
1
VO1
PGOOD
SNUB_5V
VREG3
3
2
1
VO2
8
SKIPSEL
PC53
0.22U_0603_16V7K
BST1_3V 1 PR61 2
1
2
2.2_0603_5%
PQ14
5
7
1
2
3
2
ENTRIP1
P PAD
2
25
PR60
48.7K_0402_1%
2
1
TONSEL
1
PU4
PC52
10U_0805_6.3V6M
4
6
PQ13
AON7408L_DFN8-5
2
ENTRIP2
5
1
2
PC48
4.7U_0805_25V6-K
PC47
2200P_0402_50V7K
2
1
PR59
140K_0402_1%
1
FB2
+3VLP
2
PAD-OPEN 4x4m
PC46
0.1U_0402_25V6
2
1
1
ENTRIP2
PJP5
B
C
D
Title
Compal Electronics, Inc.
PWR-3VALWP/5VALWP
Size Document Number
Custom
Date:
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
E
36
of
46
5
4
PQ8
P1
1
2
2
CSOP
4
1
499K_0402_1%
1
2
PC96
10U_0805_25V6K
1
2
PC105
10U_0805_25V6K
2
1
PR82
0_0402_5%
1
2
PR107
2.2_0402_1%
1
2
PC71
10U_0805_25V6K
1
2
PC83
1U_0402_16V6K
PC77
10U_0805_25V6K
1
2
2
3
2
1
2
PC104
1U_0402_6.3V6K
C
PR118
BGATE
1
2
0_0402_5%
1000P_0402_50V7K
2
1
2
PR108
10K_0402_1%
PC99
PC95
1U_0603_10V6K
2
PR120
2
ACIN
{14,28}
1
2
0.1U_0402_10V7K
10K_0402_1%
2
1
1
2
5
1
29
PC97
1
{28,35}
@
+3VLP
B
2
PC84
0.1U_0402_10V7K
PR114
PR105
+3VLP
B
2
BATT+
5
10K_0402_1%
EC_SMB_CK1
EC_SMB_DA1
PR121
0_0402_5%
3
VCOMP1
ISL9519_VDD
15
VFB
2
3K_0402_1%
1
1
1
2
17 CSON
16 BGATE
PC40
680P_0402_50V7K
4.7_0603_5%
18 CSOP
1
ACOK
AGND
19
14
RST#
13
12
SCL
VFB
VSMB
AGND
PR96
1
1
{24,28,35}
470P_0402_50V7K
PR80
{24,28,35}
1 2
2
2
PC100
2
4
1
2
3
2
BGATE
VCOMP
1000P_0402_50V7K
PQ10
AON7403L_DFN8-5
PR42
0.01_1206_1%
1
CSON
CELL
PC98
20
1U_0603_10V6K
2
1
ISL9519HRTZ-T_TQFN28_4X4
ICOMP
21 LGATE
PR116
56K_0402_1%
VCOMP1
3
2
1
5
PGND
PHASE
UGATE
BOOT
1
23
22
24
26
25
27
CSOP
1
1 2
1
SGATE
VFSW
PC74
1
28
VDD
11
VCOMP 7
2
ADET
SDA
2
6
CSIN
CSIP
5
VDDP
AMON
4
1
PR43
4.7_1206_5%
LGATE 4
LGATE
8
1
2
0.1U_0402_25V6
1000P_0402_25V8J
2 1K_0402_1%
2
SX34H_SMA2
2
10U_0805_25V6K
PL4
6.8UH_PCMB062D-6R8MS_4A_20%
2
1
PQ12
AON7702L_DFN8-5
DCIN
9
3
AGATE
10
2
1
PR81
100K_0402_1%
1
2
1
2
PR94
1
RB751V-40_SOD323-2
PR119
150K_0402_1%
2
1
AGATE
51.1K_0402_1%
2
ADET
1
CSON
2
PD6
2
PC76
10U_0805_25V6K
1
PQ11
2 PC102
0.22U_0402_10V6K
1
PGND
AGATE 1
DCIN
PR89 1K_0402_1%
BOOT
10_0805_1%
PU3
PHASE
PC85
2
UGATE
PR46
1
PR115
0_0402_5%
2
PC103
AON7408L_DFN8-5
1
0_0603_5%
CSIN
PC79
1
2011/10/20
change to PL4 choke 8.2uH->6.8uH
B+
PR111
BOOT
ICOMP
PC106
0.068U_0402_10V6K
PC78
0.1U_0402_25V6
1
2
UGATE 4
CSIP
PR92 1
+3VLP
PC81
1
2
0.047U_0402_16V7K
PD14
D
2
2
PC107
0.1U_0402_25V6
2
1
VIN
C
1
1
1
2
1500P_0402_50V7K
2
PR112
10_0402_1%
CSIN
0.022U_0402_25V7K
PR113
10_0402_1%
PC80
10U_0805_25V6K
4
1
2
1
PC75
CSIP
200K_0402_1%
PC69
1
2
0.02_1206_1%
2
3
PC108
10U_0805_25V6K
1
1
4
SX34H_SMA2
PR85
1
PR32
5
2
1
1
D
P2
AON7403L_DFN8-5
1
2
3
PC33
10U_0805_25V6K
2
2
PC70
10U_0805_25V6K
P3
PD7
VIN
3
ADP_I
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2011/11/5
Deciphered Date
2010/12/01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
charger
Size Document Number
2005/4/21
C
Date:
5
4
3
2
Rev
0.2
PA-8441P
Monday, November 14, 2011
1
Sheet
37
of
46
5
4
3
1
VID [0]
0
0
1
1
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
+3VS
VID[1]
0
1
0
1
VCCSA Vout
0.9V
0.8V
0.725V
0.675V
D
PR195
1K_0402_5%
2
1
PR122
100K_0402_5%
1
D
2
output voltage adjustable network
+VCCSA_PWRGD
2
VCCSA_VID1 {9}
1
2
13
PL15
0.47UH +-20% PCMB061H-R47MS 11A
1
2
PC119
22U_0805_6.3V6M
1
2
2
SW
24
7
@
PC110
22U_0805_6.3V6M
1
2
PR129
4.7_1206_5%
8
VIN
@
PC181
2200P_0402_50V7K
2
1
SW
PC116
1000P_0603_50V7K
PC117
22U_0805_6.3V6M
1
2
9
PC185
22U_0805_6.3V6M
1
2
1
10
PC161
22U_0805_6.3V6M
1
2
SW
C
+VCCSA
PC179
0.1U_0402_10V7K
2
1
+VCCSA_PHASE
PR128
PC228
2.2_0603_5%
0.22U_0603_16V7K
2+VCCSA_BT_1 1
2
PC114
22U_0805_6.3V6M
1
2
11
VIN
23
MODE
TP
6
SLEW
VOUT
5
4
1
2011/07/12
change jump to Bead
COMP
VIN
VREF
+VCCSA_PWR_SRC
+VCCSA_BT 1
1 2
22
1
12
PGND
TPS51461RGER_QFN24_4X4
2
2011/11/08
change to SH00000PX00 (H=1.8mm) No Link
EN
14
15
VID1
PGOOD
VID0
16
SW
21
3
10U_0805_6.3V6M
PC120
1
BST
SW
GND
+VCCSA_PWR_SRC
10U_0805_6.3V6M
PC115
0.1U_0603_25V7K
PC229
1
2
2
VTTPWRGOOD {39}
PGND
2
+3VALW
2200P_0402_50V7K
PC111
PL10
17
PGND
20
HCB1608KF-121T30_0603
1
2
V5FILT
18
V5DRV
19
C
2
PR127
0_0402_5%
1
2
+VCCSA_EN
@ PC230
.1U_0402_16V7K
PU11
1
+VCCSA_VID0
2
1
PC184
1U_0603_10V6K
+VCCSA_PWRGD
PR126
10_0402_1%
2
1
PC180
2.2U_0603_10V7K
1
2
+VCCSA_VID1
{28} SA_PGOOD
+5VALW
+VCC_SAP
TDC 4.2A
Peak Current 6A
OCP current 7.2A
VCCSA_VID0 {9}
PR176
1K_0402_5%
2
1
25
@
PR130
2
1
33K_0402_5%
2
PR131
100_0402_5%
2
1
FB_+VCCSA
PC112
1
0.22U_0402_10V6K
2
PC113
3300P_0402_50V7K
B
1
2
PR133
10K_0402_5%
1
PC118
0.01U_0402_25V7K
1
2
AGND
the GND via need to take care
B
2011/07/12
delete output jump
delete AGND jump
A
A
Compal Secret Data
Security Classification
Issued Date
2010/07/20
Deciphered Date
2011/07/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Title
PWR-VCC_SAP
Size
C
Date:
5
4
3
2
Compal Electronics, Inc.
Document Number
Rev
0.1
LA-8441P
Monday, November 14, 2011
1
Sheet
38
of
46
5
4
3
2
1
PL11
HCB1608KF-121T30_0603
1
2
PGOOD
VBST
10
2
TRIP
DRVH
9
UG_+V1.05SP
EN_+V1.05SP
3
EN
SW
8
SW _+V1.05SP
3
FB_+V1.05SP
4
VFB
V5IN
7
+V1.05SP_5V
4
RF_+V1.05SP
5
RF
DRVL
6
LG_+V1.05SP
1
TP
1
PC89
4.7U_0805_25V6-K
1
2
@
PC91
1U_0603_10V6K
PR101
4.7_1206_5%
2
TPS51212DSCR_SON10_3X3
PL13
1UH_PCMB062D-1R0MS_9A_20%
1
2
SW 1_+V1.05SP
1
@
2
PC94
2
1
1000P_0603_50V7K
+VCCP
1
+
2
2
@ PC93
.1U_0402_16V7K
11
PR102
470K_0402_1%
1
{28,31,40} SYSON
+5VALW
7
6
5
8
PR31 @
0_0402_5%
1
2
D
2
2
{9,28,31,40,41} SUSP#
BST_+V1.05SP
1
1
PR100
0_0402_5%
1
2
PQ22
CSD87351Q5D_SON8
TRIP_+V1.05SP
{38} VTTPWRGOOD
1
2 PR99
40.2K_0402_1%
PU8
PC90
0.22U_0603_16V7K
1
2
2011/07/12
chagne jump from
4*4 to 3*3
2011/07/15
change jump to Bead
PC92
220U_B2_2.5VM_R15M
2
EE Modify
PR98
1
2
2.2_0603_5%
B+
1
1
PR203
10K_0402_5%
PC88
4.7U_0805_25V6-K
2
1
+3VS
D
PC86
0.1U_0402_25V6
2
1
2011/06/30
combine High
and Low side
MOSFET
PC87
2200P_0402_50V7K
2
1
+V1.05SP_B+
PC109
.1U_0402_16V7K
PC136
1
2
PR33 @
0_0402_5%
1
2
+VCCP
.1U_0402_16V7K
PR103
@
4.99K_0402_1%
2
1
PR117
100_0402_1%
1
2
VCCIO_SENSE
{8}
2
+V1.05SP
TDC 10.6A
Peak Current 15.2A
OCP current 18A
1
PR104
10K_0402_1%
2011/07/15
Delete output jump
+VCCP
1
+
2
PC73
330U_D2_2V_Y
Rds_on=3.8m~4.8m ohm
1/2 delta IL=1.05*(19-1.05)/(2*1u*290k)=1.71A
IOCP=62k*10u/(8*4.8m)+1.71=18A
B
C
2
C
1
+
B
PC72 @
330U_B2_2.5VM_R15M
2
A
A
Compal Secret Data
Security Classification
Issued Date
2010/07/20
Deciphered Date
2011/07/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PWR-+VCCP
Size
Document Number
Custom
Date:
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
1
39
of
46
4
Mode
S5
S3
S0
1.5Volt +/- 5%
TDC 4.48A
Peak Current 6.4A
OCP current 7.68A
SYSON
L
H
H
SUSP#
L
L
H
+0.75V_P
off
off
on
2
+V_DDR_REF
off
on
on
0.75Volt +/- 5%
TDC 0.525A
Peak Current 0.75A
OCP Current 0.9A
Note: S3 - sleep ; S5 - power off
2011/07/12
delete input jump
PL12
PJP13 @
1.5V_B+
1
+1.5V
1
D
+0.75VS
15
LGATE
14
PGND
13
CS
1
PU9
2
20
19
VTT
BOOT
VLDOIN
4
18
16
DL_1.5V
17
SW _1.5V
PAD
21
VTTGND
1
VTTSNS
2
GND
3
VTTREF
4
VDDQ
5
1
DH_1.5V
0.22U_0603_16V7K
2
PC235
1
PQ24
2
JUMP_1x3m
+1.5VP
BOOT_1.5V
UGATE
+1.5VP
5
1
2
PC239
2200P_0402_50V7K
1
2
PC237
0.1U_0402_25V6
1
2
2
1
PC232
4.7U_0805_25V6-K
2011/07/18
change jump to bead
PC233
4.7U_0805_25V6-K
PR200
1
2
2.2_0603_5%
2
+1.5VP
2
HCB1608KF-121T30_0603
1
2
PHASE
B+
1
PC238
10U_0805_6.3V6M
D
3
PC227
10U_0805_6.3V6M
5
AON7408L_DFN8-5
0_0402_5%
1
2
PC226
.1U_0402_16V7K
2
PR214
40.2K_0402_1%
1
PR209
8.06K_0402_1%
2
1
PR210
10K_0402_1%
PQ33B
S3_1.5V
PC242
.1U_0402_16V7K
5
SSM6N7002FU-2N_SOT363-6
4
2
PC236
0.033U_0402_16V7K
6
7
PR205
1M_0402_1%
1
2
S5_1.5V
1
2011/09/22
reserve the FFS (boot from RAM)
add +3VLP and VL signal
FB_+1.5V
2
2
1
{28,31,39} SYSON
+1.5VP
2
1.5V_B+
PR211
C
1
VL
1
PR206
0_0603_5%
1
PR208 @
0_0603_5%
1
2
PR213
2
VDD
+V_DDR_REF
+V_DDR_REF
2
+5VALW
+3VLP
11
8
AON7702L_DFN8-5
@
0_0402_5%
VDDP
9
1
2
3
VDD_1.5V
1U_0603_10V6K
PC225
12
FB
2
PR202
5.1_0603_5%
2 PC231
1U_0603_10V6K
S3
1
+5VALW
1
S5
2
10
4
1
TON
VL
PGOOD
1
2
3
5
PQ25
RT8207MZQW _W QFN20_3X3
3 1
@
CS_1.5V
PR204 @
5.1_0603_5%
1
2
PR207
4.7_1206_5%
2
PR201
14K_0402_1%
1
2
2
@
0.1U_0603_25V7K
PC234
1
1
+
1SNUB_1.5V
C
2
PC101
220U_B2_2.5VM_R15M
PL14
1UH_PCMB062D-1R0MS_9A_20%
1
2
{9,28,31,39,41} SUSP#
2
+1.5VP
PR212
B
1
0_0402_5%
B
PR216
10K_0402_1%
+3VS
1
2
2
+3VS
6
10K_0402_1%
1
2
Compal Secret Data
Issued Date
2010/07/20
Deciphered Date
2011/07/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
SSM6N7002FU-2N_SOT363-6
1
2
PR217 @
10K_0402_1%
A
Security Classification
2
1
PR220
PQ33A
2
4700P_0402_25V7K
PR218 @
10K_0402_1%
DDR3L_EN {16}
1
10K_0402_1%
PR219
10K_0402_1%
1
1
1
2
PR221
2
DDR3L_EN = High => DDR3L,
DDR3L_EN = Low => DDR3
Compal Electronics, Inc.
PWR-1.5VP/0.75VSP
Size
Document Number
Custom
Date:
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
1
40
of
46
A
B
C
D
1
2
A
2011/07/18
change the choke to 2520 type
PJP6
1
+1.8VSP
1
2
+1.8VS
PAD-OPEN 3x3m
2
SNUB_1.8VSP
PC63 @
680P_0603_50V7K
1
1
PR74 @
4.7_1206_5%
PU5
IN
5
PG
GND
2
6
FB
EN
1
PL9
1UH_PHT32251B-1R0MS_2.34A_20%
1
2
1.8VSP_LX
3
LX
(2A, 80mils, Via NO.= 4)
1
SY8032ABC_SOT23-6
EN_1.8VSP
2
1
1
1
2
1
1.8VSP_FB
PR78
10K_0402_1%
2
20K_0402_1%
PC68
0.1U_0402_10V7K
@
PR77
47K_0402_5%
2
PR76
0_0402_5%
PR75
+1.8VSP
@
2
22P_0402_50V8J
2
2
1
PC65
1
VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
+1.8VSP
1
4
2
PC64
22U_0805_6.3V6M
2
1
1.8VSP_VIN
PC67
22U_0805_6.3V6M
HCB1608KF-121T30_0603
1
2
PC66
22U_0805_6.3V6M
PL8
+3VALW
SUSP#
2
2
SNUB_1.5VSP
1
2
{9,28,31,39,40} SUSP#
PC140 @
680P_0603_50V7K
2011/07/18
change the choke to 2520 type
PJP7
+1.5VSP
1
2
+1.5VS
2
PAD-OPEN 3x3m
1
PR95 @
4.7_1206_5%
PL17
PU17
3
HCB1608KF-121T30_0603
1
2
1.5VSP_VIN
PC224
22U_0805_6.3V6M
4
IN
5
PG
GND
2
6
FB
EN
1
PL19
1UH_PHT32251B-1R0MS_2.34A_20%
1
2
1.5VSP_LX
3
LX
3
(2A, 80mils, Via NO.= 4)
1
2
1
PC141
22U_0805_6.3V6M
2
2
1
1
1.5VSP_FB
PR268
10K_0402_1%
2
20K_0402_1%
2
1
@
PR270
47K_0402_5%
PC221
22U_0805_6.3V6M
1
PR269
0_0402_5%
PR267
1
@
2
22P_0402_50V8J
2
2
1
PC222
0.1U_0402_10V7K
EN_1.5VSP
PC223
+1.5VSP
VFB=0.6V
Vo=VFB*(1+PR401/PR402)=0.6*(1+20K/10K)=1.8V
+1.5VSP
SY8032ABC_SOT23-6
2
1
+3VALW
SUSP#
4
4
LA-7531P
Compal Secret Data
Security Classification
Issued Date
2009/01/23
Deciphered Date
2010/01/23
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
Title
Compal Electronics, Inc.
PWR-1.8VSP/1.5VSP
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
D
Sheet
41
of
46
5
4
3
2
1
2011/10/24
delete the panel power circuit
D
D
C
C
B
B
A
A
Compal Secret Data
Security Classification
Issued Date
2008/09/15
Deciphered Date
2009/09/15
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Compal Electronics, Inc.
PWR - PIR
Size
Document Number
Rev
0.1
LA-8441P
Date:
Monday, November 14, 2011
Sheet
1
42
of
46
4
PR272
2
1
PR319
7.5K_0402_1%
2
2
1
PR304
15.4K_0402_1%
2
VX
F4
ISENSE
VX
F3
PWM
VX
B1
VDD
VX
F1
A2
GND
VX
D4
E1
VSS
VX
D3
E2
VSS
VX
D2
@
E3
VSS
VX
D
PC250
1U_0603_10V6K
2
1
PC281
22U_0805_6.3V6M
2
1
0.1UH_PCMB061H-R10MS_18A_20%
F2
PL20
PHASE_CPU
1
+CPU_CORE
2
@
D1
2
VT1324SFCX_CSP35
@
PR301
4.7_0805_5%
B4
H4
H3
H2
TS_FAULT#
B2
B3
VCC_core
TDC 52A
Peak Current 94A
OCP current 116A
Load line -1.9mV/A
VX
VX
VX
BST
VDDH
VDDH
VDDH
VDDH
A1
IPH1_1
PWM1_1
@
H1
TSFAULT#1
+5VALW
2011/11/07
change to SH00000PY00
TSFAULT#2 {44}
IPH2_1
1
PR300 1.96K_0402_1%
PC259 @
10P_0402_50V8J
C
1
VGFX_SENSE_N
VGFX_SENSE_P
VX
E4
G1
G2
G3
G4
J1
J2
J3
J4
1
2
PR296
390_0402_1%
1
2
PR295
20K_0402_1%
PC253
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PR287
10_0402_1%
1
A4
2
2
PR290
825_0402_1%
2
PR289
280_0402_1%
1
1
2
PR292
196_0402_1%
1
2
PR288
61.9K_0402_1%
1
2
PR291
0_0402_1%
1
C1
C2
C3
C4
+1.8VS
VR_SVID_DATA {8}
PR320
680_0402_1%
2
2
1
PC263
22P_0402_50V8J
1
2
PR315
0_0402_1%
2
1
2
1
PR325
PC266
22P_0402_50V8J
1
2
@ PC272
PR324
@
1000P_0402_50V7K 30.1K_0402_1%
1
2
1
2
1
2
1
+5VALW
2
PU18
PC282
22U_0805_6.3V6M
2
1
1
825_0402_1%
2
PR332 @
30.1K_0402_1%
1
2
2
PC273 @
1000P_0402_50V7K
1
2
1
1
PR318
10K_0402_1%
1
2
B
VR_SVID_ALRT# {8}
PR285
PC265
22P_0402_50V8J
1
2
PC268
680P_0402_50V7K
PC244
0.1U_0402_25V6K
2
PAD-OPEN 1x3m
PC261
0.01U_0402_50V7K
1
2
1
PR306
1 MRAMP2
PC262
3300P_0402_25V7K
1
2
PR309
15K_0402_1%
1
2
PC243
0.22U_0603_10V7K
1
2
1
56.2K_0402_1%
2
VR_HOT {28}
VR_SVID_CLK {8}
2
MRAMP2
SENSE1+
SENSE1A_ERR1
A2_IN1
A2_OUT1
A3_IN1
A3_OUT1
A3_OUT2
A3_IN2
A2_OUT2
A2_IN2
A_ERR2
PR305
1 MRAMP1
0_0402_5%
2
PWM2_1 {44}
VT1318MFQX_QFN48_6X6
13
14
15
16
17
18
19
20
21
22
23
24
43K_0402_1%
2
PC264
33P_0402_50V8J
1
2
VR_TT
2
1
PR323 0_0402_1%
PR307
2.7K_0402_1%
+VGFX_CORE
36
35
34
33
32
31
30
29
28
27
26
25
PR313
487_0402_1%
+CPU_CORE
R_SEL[2]
R_SEL[3]
R_REF
IPH2_2
R_SEL[5]
PWM2_2
PWM2_1
TS_FAULT#2
IPH2_1
MRAMP2
SENSE2+
SENSE2-
PJP14
PR277
1
VCORE_SENSE_P
VCORE_SENSE_N
VERR1
VI2_1
VO2_1
VI3_1
VO3_1
VO3_2
VI3_2
VO2_2
VI2_2
VERR2
@PC258
@
PC258
10P_0402_50V8J
VDD3
VDD
VDD
VIN_UVLO
PWM1_3
PWM1_2
PWM1_1
TS_FAULT#1
IPH1_3
IPH1_2
IPH1_1
MRAMP1
1
2
PR303
13K_0402_1%
C
2
1
MRAMP1
130_0402_1%
1
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
1
PR308
3.24K_0402_1%
2
1
PR321
0_0402_1%
@ PR275
1
75_0402_5%
1
PR314
665_0402_1%
PWM1_1
1
2
3
4
5
6
7
8
9
10
11
12
ALERT
VDIO
VCLK
VR_ON1
PG2
PG1
VR_TT
48
47
46
45
44
43
42
41
40
39
38
37
49
R_SEL[6]
VR_READY2
VR_READY1
VR_TT#
R_SEL[4]
ALERT#
VDIO
VCLK
VR_ENABLE
R_OSC
R_SEL[0]
R_SEL[1]
1
2
PR293
1.96K_0402_1%
TP
2
IPH1_1
PC252
0.1U_0402_16V4Z
PU19
VIN_UVLO
TSFAULT#1
PR280
1
PR283
1
PR284
1
1
1
VGATE {14}
2
PR282
84.5_0402_1%
+3VALW
PR286
10_0402_1%
2
+1.8VS
PG1
PC251
1U_0603_10V6K
2
1
D
1
2
2
PR278
2
PG2
+VCCP
PC254
470P_0603_50V8J
1
2
1
@ PR276
2
PR279
0_0402_5%
2
1
1
1
PR297
0_0402_5%
1
2
1
1
PR274
1K_0402_5%
PR273
1K_0402_5%
PR281
0_0402_5%
2
1
54.9_0402_1%
VR_ON1
2
2
PC255
4.7U_0603_6.3V6K
2
1
0_0402_5%
2
1
PR271
1
3
0.1U_0402_16V4Z
VR_ON
2
{28}
2
5
+3VS
PR322
1K_0402_1%
2
1
PC270
1000P_0402_50V7K
1
2
PR316
7.87K_0402_1%
2
1
1
PR312
30.1K_0402_1%
2
PR317
10K_0402_1%
2
B
IPH2_1 {44}
IMON_GFX
PR326
750_0402_1%
1
2
887K_0402_1%
1
IPH1_1
IMON_CORE
VIN_UVLO
2
Local sense put on HW site
PR327
100K_0402_5%
{9} VSS_AXG_SENSE
Local sense put on HW site
1
0.1U_0402_16V4Z
2
1
PC271
{8}
VSSSENSE
1
PR329
0_0402_1%
2
VCORE_SENSE_N
{9} VCC_AXG_SENSE
A
{8}
VCCSENSE
1
PR331
0_0402_1%
2
1
1
PR328
0_0402_1%
2
VGFX_SENSE_N
PR330
0_0402_1%
2
VGFX_SENSE_P
A
VCORE_SENSE_P
Compal Secret Data
Security Classification
Issued Date
2010/07/20
2011/07/20
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
+CPU_CORE
Size Document Number
Custom
Date:
Rev
0.1
LA-8441P
Sheet
Monday, November 14, 2011
1
43
of
46
5
4
3
2
1
D
D
{43} TSFAULT#2
{43} IPH2_1
PC278
0.22U_0603_10V7K
1
2
A1
B2
PAD-OPEN 1x3m
+5VALW
@
VCC_GFXCORE
TDC 38A
Peak Current 46A
OCP current 57.18A
Load line -3.9mV/A
VX
VX
VX
H4
H3
H2
B4
BST
H1
TS_FAULT#
VX
F4
ISENSE
VX
F3
B3
PWM
VX
F2
B1
VDD
VX
F1
PHASE_GFX
A2
GND
VX
D4
@
E1
VSS
VX
D3
E2
VSS
VX
D2
E3
VSS
VX
D1
0.1UH_PCMB061H-R10MS_18A_20%
1
2
PL21
2
VT1324SFCX_CSP35
B
2
C
VX
PC286
470P_0603_50V8J
1
2
1
VCC
E4
G1
G2
G3
G4
J1
J2
J3
J4
@
A4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PR335
0_0402_5%
1
2
PC285
4.7U_0603_6.3V6K
2
1
0.1U_0402_16V4Z
2
PC287
1
2
PR334
10_0402_1%
1
C
VDDH
VDDH
VDDH
VDDH
C1
C2
C3
C4
PU20
+VGFX_CORE
@
PR336
4.7_0805_5%
+1.8VS
PC284
1U_0603_10V6K
2
1
PC279
22U_0805_6.3V6M
2
1
{43} PWM2_1
PC280
22U_0805_6.3V6M
2
1
PJP17
1
2011/11/07
change to SH00000PY00
B
A
A
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
2010/07/20
Deciphered Date
2011/07/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
+VGFX_CORE
Size
B
Date:
Document Number
Rev
0.1
LA-8441P
Monday, November 14, 2011
Sheet
1
44
of
46
5
4
+CPU_CORE
3
2
+CPU_CORE
1
+VGFX_CORE
+VCCSA
+VCCSA
1
+VCCSA
PC306
22U_0805_6.3V6M
PC192 +
330U_D2_2V_Y
+VGFX_CORE
1
2
2
2
1
1
1
2
2
2
1
1
1
2
2
PC343
22U_0805_6.3V6M
2
2
PC342
22U_0805_6.3V6M
1
1
1
2
2
2
PC341
22U_0805_6.3V6M
PC344
22U_0805_6.3V6M
1
1
PC355
22U_0805_6.3V6M
2
PC354
22U_0805_6.3V6M
2
PC353
22U_0805_6.3V6M
2
2
PC352
22U_0805_6.3V6M
1
1
1
2
PC351
22U_0805_6.3V6M
PC356
22U_0805_6.3V6M
1
2
2
1
2
1
2
1
2
2
1
1
2
1
2
1
2
1
2
2
PC314
1U_0402_6.3V6K
1
1
2
1
2
1
2
1
2
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
PC371
1U_0402_6.3V6K
2
2
1
2
1
1
2
1
2
2
1
PC26
1U_0402_6.3V6K
1
2
1
PC37
1U_0402_6.3V6K
2
1
PC31
1U_0402_6.3V6K
2
2
1
2
1
2
1
2
PC35
1U_0402_6.3V6K
2
2
1
B
PC15
1U_0402_6.3V6K
1
2
1
PC41
1U_0402_6.3V6K
2
1
PC43
1U_0402_6.3V6K
1
PC44
1U_0402_6.3V6K
2
2
2
PC29
1U_0402_6.3V6K
2
1
PC13
1U_0402_6.3V6K
1
PC39
1U_0402_6.3V6K
2
1
PC134
1U_0402_6.3V6K
PC366
1U_0402_6.3V6K
2
1
PC82
1U_0402_6.3V6K
PC345
2.2U_0402_6.3V6M
1
PC30
1U_0402_6.3V6K
PC363
2.2U_0402_6.3V6M
PC25
1U_0402_6.3V6K
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Compal Secret Data
Security Classification
Issued Date
2010/07/20
Deciphered Date
2011/07/20
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
Process Decoupling
Size
A3
Date:
Document Number
Rev
0.1
QAU00
Monday, November 14, 2011
Sheet
1
45
of
46
5
4
3
2
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5HY
D
D
C
C
B
B
A
A
Compal Secret Data
Security Classification
2008/09/15
Issued Date
2009/09/15
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Title
Compal Electronics, Inc.
PWR - PIR
Size
Document Number
Rev
0.1
LA-8101P
Date:
Sheet
Monday, November 14, 2011
1
46
of
46
Source Exif Data:
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