Compcontrol_CC 74_DMA SCSI_Interface_Module_Jan86 Compcontrol CC 74 DMA SCSI Interface Module Jan86

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~-~

MANUAL CC-74

VERSION 1.3

I

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•

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.",
1

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DMA-SCSI
INTERFACE MODULE
January 1986

~

I

II

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I

Copyright
Copyright (c) 1986 by COMPCONTROL B.V .. All rights reserved. No part of this
publication may be reproduced. transmitted. transcribed. stored in a retrieval system.
or translated into any language or computer language. in any form or by any means.
elect.ronic. mechanical. magnetic. optical. chemical.. manual or otherwise. without the
prior
written
permission of COMPCONTROL B.V .• Post Office Box 193. 5600 AD
EINDHOVEN-HOLLAND.

Disclaimer
The information in this document has been carefully checked and is believed to be
entirely reliable. However. no responsebility is assumed for inaccuracies. Compcontrol
B.V. makes no representations or warranties with respect to the contents hereof and
specifically disclaims any implied warranties of merchantability or fitness for any
particular purpose. Furthermore. Compcontrol B.V. reserves the right to make changes to
any product herein to improve reliability. function or design. without obligation of
Compcontrol B.V. to notify any person of such revision or changes. Compcontrol B.V.
does not assume any liability arising out of applications or use of any product or
circuit described herein: neither does it convey any license under its patent rights
nor the rights of others.

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CC-74 DMA-SCSI INTERFACE MODULE

•

TABLE OF CONTENTS

•

PAGE

•

CHAPTER 1
1.1
1.2
1.3

•

CHAPTER 2

•

2.1
2.2

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3.1
3.2
3.3
3.4
3.5
3.6

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CHAPTER 4

III

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I

iii

1

.j

4.1
4.2
4.2.1
4.2.2
4.3
4.4
4.5
4.6
4.7
4.8
CHAPTER 5

iii
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CHAPTER 3

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I

II1II

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iii
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I
I

5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.8.1
5.8.2

GENERAL INFORMATION
Introduction
Features
General Description

1-1
1-1
1-2

SPECIFICATION
VMEbus Options
SCSI Bus Options

2-1
2-1

INSTALLATION INSTRUCTIONS
Introduction
Address Selection
DMA Clock Selection
SCSI ID Address Selection
External DMA Devices
SCSI Bus Termination

3-1
3-1
3-2
3-2
3-2
3-3

THEORY OF OPERATION
Introduction
DMA Controller
MPU Mode
DMA Mode
VMEbus Interface
Address Decoding
DTB Requester
Interrupter
External DMA Devices
SCSI Interface

4-1
4-1
4-1
4-1
4-2
4-2
4-2
4-3
4-3
4-3

PROGRAMMING CONSIDERATIONS
Introduction
Memory Map
Reset
Interrupts
Bus Request
Control Register
AM Code Generation
Programming the CC74 Module
Programming The DMA Controller
Programming The SCSI Protocol Controller

5-1
5-1
5-1
5-2
5-3
5-3
5-3
5-4
5-4
5-6

APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX
APPENDIX

A
B
C
D
E
F
G
H
I

Block Diagram
Schematic Diagram
Component Layout
List of Components
Connector Pin Assignments
Memory Map
DMA Controller Registers
SCSI Controller Registers
Control Register
J CC74 Program Example
K Data Sheet 68450 DMAC
L Data Sheet 5385/6 SCSI 'Controller

A-I
B-1

C-1
D-1

E-1
F-1
G-I
H-!

1-1
J-1
K.,.!

L-1

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•
•
CHAPTER 1

•

GENERAL INFORMATION

•

•
•
•
•

•

1.1 Introduction
The CC74 module interfaces the VMEbus and Small Computer System
Interface (SCSI) with each other. Th~s manual gives a full
description of the hardware and software for users and system
programmers. For specific details about the VMEbus,
SCSI bus,
SCSI
protocol Controller or DMA controller,
the following
documents may also be consulted.
-

VMEbus specification manual
SCSI specification manual (ANSC X3T9.2)
SCSI protocol controller user's guide (see appendix L)
SCSI protocol controller data sheet (see appendix L)
DMA controller data sheet (see appendix K)

1.2 Features
..'1

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•

•

.
•
~
I

The CC74 VME-SCSI interface module features the high-performance
68450 DMA Controller and the NCR 5386 SCSI Protocol Controller .
The SCSI Protocol Controller conforms to the ANSC X3T9.2 Small
Computer System Interface standard.
SCSI features:
..;
-

Asynchronous data transfer up to 1.5 MByte/s
Supports both Initiator and Target role
Parity generation with optional checking
Supports Arbitration and Reselection
Controls all bus signals, including Reset
DMA or programmed I/O transfers
Block transfers up to 16 MByte

VME features:
- DMA Controller supports I/O to memory, memory to I/O
and memory to memory transfers
- Optimal bus width utilization for mixed byte and word
transfers
- Programmable Interrupt and Bus Request levels
- Programmable Interrupt vectors
- Interrupts VMEbus when SCSI bus requires service
- 23 bit addresses, 16 data lines and 6 AM code lines
- Highly reliable data transfer by error detect, error
interrupt vector and exception features

..

~

Manual CC74 Ver 1.3

1-1

January 1986

All SCSI I/O
connector and
connector.

signals are available on the I/O pins of the P2
also on a SCSI-compatible 50-pin flat cable

1.3 General Description
The Small Computer System Interface (SCSI) is a de facto industry
standard and is used to interconnect small computers with each
other and with intelligent peripherals such as hard disks,
flexible disks, magnetic tape devices etc. The standard defines
the bus protocol, the bus drivers, cables and connectors and the
command set. The CC74 module is a full implementation of the SCSI
standard and may act as an Initiator or Target on the SCSI bus.
The 8-bit data transfers between the SCSI bus and the VMEbus can
be handled by any DTB master or by the local DMA controller. The
DMA controller can also be used for memory to memory transfers on
the VMEbus and may be used by a RAM disk routine. The CC74 has a
four-level Bus Requester and a seven-level Interrupter, which are
both software programmable. The normal and error interrupt vector
can also be dynamically installed.

c

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Manual CC74 Ver 1.3

1-2

January 1986

c

•

CHAPTER 2
SPECIFICATION

2.1 VHEbus Options
1,

Data transfer options:
- DTB MASTER
- DTB SLAVE

A24,A16; 016,08
A24,A16; D16,D8

Requester options:
~

I

•
~

•
1

- Anyone of R(O) R(l) R(2) R(3)
- RWD

(DYN)

Interrupter options:
- Anyone of I(l) 1(2) 1(3) 1(4) 1(5) 1(6) 1(7)
- Normal interrupt vector (DYN)
- Error interrupt vector (DYN)

(DYN)

Environmental conditions:
- operating temperature 0-70 degrees C
- max operating humidity 90 %
Power supply requirements:
- 3.0 A max (2.7 A typ) at 5 VDC
Physical configuration options:

•

- NEXP
2.2 SCSI Bus Options
The following options are implemented on the CC74 module.

•

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Supports ANSC X3T9.2 SCSI standard
Supports Arbitration and Reselection
Single-ended drivers and receivers
Non-shielded cable option
Performs both Initiator and Target role
Parity generation with optional checking
Controls all SCSI bus signals

-~

l

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Manual CC74 Ver 1.3

2-1

January 1986

c

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III

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CHAPTER 3
INSTALLATION INSTRUCTIONS

•

•

•
•
•

•

3.1 Introduction
This chapter gives all necessary preparation and installation
instructions for the CC74 VME-SCSI interface module.
The module
can be· used in VMEbus systems and configuration options are
selected by jumpers and switches. All settings are illustrated as
seen from the component side with both VMEbus
connectors
downwards. Jumper blocks are drawn using ' 0 ' for each pin except
pin 1 which is identified as '*'
3.2 Address Selection
Jumper blocks JBl and JB2 are used for the address modifier
selection. JBl when installed will make the CC74 module respond
to supervisory access only.

*

JB1:

supervisory or
non-privileged access

o

*

JB1:

supervisory-only access

o

JB2 is used to select standard or short address decoding.

•

•

JB2:

*---0

JB2:

*

0---0

0---0

o

standard addressing
short addressing

Switches Sl-S4 are hexadecimal switches used to select the base
address of the module. Sl selects the most significant nibble, so
the address lines A23-A20 are selected by Sl, A19-A16 by S2,
A15-A12 by S3 and All-A9 are selected by S4. Note that S4 selects
3 address lines and thus has only 8 significant positions (only
even numbers). Also note that Sl and S2 are not significant when
JB2 is installed for short addressing.

Manual CC74 Ver 1.3

3-1

January 1986

3.3 DMA Clock Selection
Jumper JB3 is used to select the OMA clock input. When an 8 MHz
OMAC is used, a derivative of the system clock can be used. When
a 10 MHz OMAC is used, the SCSI Controller clock may be used and
for other clock rates the optional oscillator U18 must be
installed. Jumper JB3 must be set according to the installed OMAC
type.
*---0

JB3:

0

0

0

0

*

0

OMA clock-rate defined by U18

•

•
i

JB3:

JB3:

8 MHz OMA clock rate

0---0
0

0

*

0

0

0

10 MHz DMA clock rate

0---0

3.4 SCSI ID Address Selection
Any Initiator or Target module on the SCSI bus must have a unique
IO-bit. Eight 10 bits are defined and can be selected with jumper
JB4. Only one jumper must be placed at JB4.
ID bit

7

6

S

4

3

2

1

o

o

o

o

o

o

o

o

*

o

o

JB4:
o

o

o

o

o

I

o

10 bit 2

selected

c
3.5 External DMA Devices
The jumpers involved with external DMA devices are JBS,
JB6 and
JB7. The programmable control lines can be used for input or
output. JBS is used to select the direction of the PCL2 control
line.
Manual CC74 Ver 1.3

3-2

January 1986

•i

It

JB5:

II

•

*

o

o

o

I

PCL2 configured as input

*---0

JB5:

PCL2 configured as output
0---0

•
JB6 selects the direction of the PCL3 control line.

•

*

0

0

0

JB6:

•
-~

I

PCL3 configured as input

*---0

•

•
III

JB6:

PCL3 configured as output
0---0

JB7 is used to select the direction of the DONE signal.
*

0

0

0

JB7:

I

DONE configured as input

j
!

III

*---0

JB7:

DONE configured as output
0---0

III

Jumpers JB5, JB6 and JB7 can be removed when not using the option
for external DMA devices. When using this option it is necessary
that there shall be no conflicts between the programmed direction
and the installed jumper settings of the control lines.

III

3.6 SCSI Bus Termination

•
II
.. ~

lilt
-~

lilt
--~

The SCSI bus consists of a 50-pole flat cable which may be 'daisy
chained' to a maximum of eight Initiator and/or Target devices.
Both devices at the ends of the cable should have installed
terminating networks and all other devices must not have these
networks. The CC74 module has the two relevant resistor networks,
RNI and RN2,
installed in sockets, and these networks must be
removed when the module is not at the end of the daisy chain.
In some SCSI bus systems, the power of the terminating networks
is supplied by a 'Terminating Power Supply' via pole 26 of the
SCSI cable. This pin is referred to as 'TRMPWR'.
Jumper JB8 is
used to select the power source for the on-board resistor
networks.

Manual CC74 Ver 1.3

3-3

January 1986

~

~

JB8:

*
I

0

VMEbus power connected to on-board
resistor networks

0

~
II

~

*
JB8:

0

I

SCSI bus 'TRMPWR' connected to on-board
resistor networks

~
~

0

~

.~
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•~
~
C
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I.
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C
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I.

C

C

C

C
Manual CC74 Ver 1.3

3-4

January 1986

C
,.

•
CHAPTER 4

•

THEORY OF OPERATION

4.1 Introduction
This chapter gives a global explanation of the functional blocks
as shown in appendix A. The schematic diagrams are given in
appendix B. The main functions of the CC74 module are 'performed
by the 68450 DMAC and the NCR 5386 SCSI Protocol Controller.
These two parts are fully described in the
manufacturers
documentation included in appendix K and L.
4.2 DMA Controller

•

•

The 68450 DMAC has three modes of operation.
In the MPU mode, the DMAC is selected by an external bus master,
through a chip select or interrupt acknowledge. The bus master is
writing or reading the contents of the DMAC internal registers.
In the DMA mode, the DMAC is the current bus master and is
transferring data or preparing for the data transfer.
In the IDLE mode, the DMAC is in a state other than MPU or DMA
mode. A Read/Write access or transfer request will change the
mode into MPU or DMA respectively.
4.2.1 MPU Mode

•

•

In MPU mode,
an access is made to one of the DMAC internal
registers. The registers can be accessed by byte or word. There
are 64 bytes defined per channel and each channel has 17
registers. There are four channels available, so the DMAC takes
256 bytes in the memory map. The address lines Al through A7 and
the data strobes determine which register will be selected.
When an interrupt acknowledge cycle is performed the
DMA
controller puts the contents of the normal or error interrupt
vector register of the highest channel requesting an interrupt on
the data bus. The DMAC uses a multiplexed address/data bus,
demultiplexing is done by U7-UIO with the control signals DDIR
(Data DIRection), DBEN (Data Bus ENable) and UAS (Upper Address
Strobe).

-~

•

4.2.2 DMA Mode

•

When in DMA mode,
the DMAC is the current VMEbus master and
activates the OWN line; this will enable the buffers of the
VMEbus interface.
Transfer modes used for DMA are defined as
follows:

~

I

Manual CC74 Ver 1.3

4-1

January 1986

~

•
i

Dual addressing with auto request:
- transfer byte or word from memory to holding register.
- transfer byte or word from holding register to memory.
Single addressing with request acknowledge handshake:
- transfer byte from SCSI PC to memory (using
transfer byte from SCSI PC to memory (using
transfer byte from memory to SCSI PC (using
transfer byte from memory to SCSI PC (using

00-07).
08-0lS).
00-07).
08-015).

Timing and control signals are generated by UlS, U16 and U29.
4.3 VMEbus Interface
The main part of the interface to the VMEbus is given in the
schematic diagram (Appendix B, sheet I). The address and data
lines are shown with their respective buffers to the VMEbus. The
control signals for these buffers are; GVME to enable the data
buffer on the VMEbus, FROMVME to control the data direction of
the data buffers,
and OWNL wich is used to enable the address
buffers. These control signals are generated by U29 (sheet 7).
The multiplexing of the address and data lines is performed by
the DMAC using the signals UAS (Upper Address Strobe), DDIR (Data
DIRection) and DBEN (Data Bus ENable). The control lines on the
VMEbus are buffered by U14, U26 and U27 (sheet 4). The generation
of DTACK (when in MPU mode) is performed by U1S (sheet 7) and
buffered by U24 and U30. A shift register US2 is used for the
DTACK timing.
4.4 Address Decoding
The address decoder is given in the schematic diagram of sheet 2
and uses the address lines A9-A23 and AM code lines AMO-AMS. The
LIACK signal is used to inhibit address decoding when an lACK
cycle is performed. Jumper JB2 is used to enable standard or
short
addressing,
and
JBl to select supervisory-only or
non-privileged access. The remaining modifier codes select data
I/O access.
4.5 DTB Requester
The onboard DTB requester consists of two parts, the requester
logic U20 and the chaining logic U2l. The bus request logic, when
activated by LDBR (Local DMA Bus Request) will assert one of the
BRx outputs depending on the installed request level (REQLVO,
REQLV1). Now it will wait for a Bus Grant (BGT) from the chaining
logic. The chaining logic checks the incoming BGxIN signals from
the VMEbus and determines if the incoming signals must be chained
toBGxOUT or should be used locally. Latch U19 is used to
guarantee a valid BGxIN signal for the chaining logic. The level
of bus request is software-selectable and is discussed in chapter
5.5.

Manual CC74 Ver 1.3

4-2

January 1986

•
•
I

•

4.6 Interrupter
The Interrupter U22 (sheet 3) uses the latched VMEbus signals.
This circuit asserts one of the seven VMEbus interrupt signals
(IRQI-IRQ7) when a local OMA interrupt (LIRQOMA) is received. The
interrupt level is determined by IRQLVO-IRQLV2 and is software
selectable (see chapter 5.4). When an interrupt has been asserted
the interrupter waits for an Interrupt acknowledge cycle on the
VMEbus. Then the interrupt level will be checked and when a match
is found IACKSEL will be asserted, otherwise IACKOUT is asserted.
The OMA controller will generate the proper interrupt vector,
when necessary. When an interrupt acknowledge cycle for the OMAC
is performed, the interrupter releases the VMEbus IRQ line and
will only respond to another IRQOMA, after negation of LIRQOMA
for at least two clock cycles (125 ns).

•
4.7 External OMA Devices

•

•
,

•

The 68450 is a four channel OMAC and only two channels are used
by the SCSI interface. The control lines of the two unused
channels are connected to the P2 connector. The direction of
these signals can be selected by jumpers. The two channels may
therefore be used by other devices on other modules via control
lines on the P2 connector. Care should be taken here to prevent
conflicts with the VMEbus specification; however, relatively
simple I/O modules may take advantage of these OMA channels.

1I

•
•

-~

4.8 SCSI Interface
The SCSI protocol controller used is the NCR 5385 (or NCR 5386).
Sheet 5 of the schematic diagrams shows the complete interface.
SCSI bus buffering is performed by U42 through U47. Units U40 and
U41 are used for driving one of the eight data lines on the SCSI
bus during arbitration. JB4 selects which data line will be
driven during arbitration, the so called 10 address. U36 encodes
the JB4 setting into three 10 signals 100, 101 and 102, used by
the SCSI PC. U39 (sheet 6)- is a 10 MHz clock oscillator for the
SCSI PC clock. Connector P3 is a flat cable connector which has
the proper SCSI bus pin definitions. Connector P2 is the standard
VMEbus I/O connector which has also all SCSI bus signals
connected. An optional module CC85 is available to interface a
50-pin SCSI bus flat cable to the P2 connector.

-~

•
Manual CC74 Ver 1.3

•
-~

4-3

January 1986

.
,

•
CHAPTER 5

•

PROGRAMMING CONSIDERATIONS

•

•

5.1 Introduction
This section contains all necessary information for system
programmers to take full advantage of .the features of the CC74
module. Additional information may be found in the respective
data sheets of the SCSI protocol controller (NCR 5385/6) and the
DMA controller (68450). For system programmers who want to write
their
own CC74 driver software,
a full understanding and
experience is required. The source code of a sample driver
routine for this module is found in Appendix J.

•
5.2 Memory Map
The memory map is given in Appendix F. The module takes $200
(=512) byte locations, starting at the selected base address. The
first 256 locations are used for the DMA controller and the
second block is partially used by the SCSI controller (16 bytes)
and the local control register (1 byte). Both the SCSI controller
and the control register are 8 bits wide and are accessed at odd
memory locations. Both are duplicated an arbitrary number of
times in the memory map. The recommended address locations for
use by system programmers are given below.
BDMAC
CNTREG
B SCSI

equ
equ
equ

CC74 BASE+O
CC74-BASE+$100
CC74-BASE+$120

base address for DMAC
address of control reg.
base address for SCSI PC

CC74_BASE depends on the address select switches Sl-S4. Note that
the byte wide registers respond at odd addresses only. The
registers within the DMAC and SC$I PC can be accessed by using
B DMAC and B SCSI as the respective register base addresses and
declaring each-register as an offset from these addresses (see
Appendices G and H)
5.3 Reset
-~

•

The SYSRES* signal from the VMEbus will reset the DMAC, SCSI PC,
DTB Requester and the local Control Register. When the DMAC
recognizes Reset,
it relinquishes the bus, clears the GCR and
resets the DCR, OCR, SCR, CCR, CSR, CPR and CER of all channels.
The interrupt vector registers are set to $OF (uninitialized
interrupt vector number). When SYSRES* is active,
the SCSI
Protocol Controller is forced into a reset state. All current
operations are terminated
and
internal
storage
elements
(registers,
counters etc.) are cleared. A 'chip reset command'
Manual CC74 Ver 1.3

5-1

January 1986

loaded into the SCSI PC performs the same operation as the
hardware reset. The DTB Requester falls into the idle state after
reset, which means that all output signals are negated (no bus
requests active). The local control register will be cleared
after reset and all output lines will be low. This disables the
interrupt request level, the bus request level will be 0 and the
SCSI reset signal will NOT be activated. The SeSI reset signal
when activated (by a write instruction to the Control register)
will reset the SCSI PC, which will then release all bus signals
within a 'bus clear delay'. The Interrupt handler attached to the
CC74 module can be informed about the SCSI Reset condition with
an interrupt request. The PCLl line of the DMAC is used for this
purpose.
5.4 Interrupts
All interrupts from the CC74 module are generated by the DMAC.
These interrupts can be caused by several conditions such as
channel operation complete, PCL transition or Bus error. Each
channel may generate its own normal interrupt vector or an error
interrupt vector. An error interrupt vector is generated when a
DMA transfer is terminated by a bus error response or when an
address error occurs. In the case of an error, the present values
of the Memory Address, Device Address and Base Address registers,
the Memory Transfer and Base Transfer counters, and Control,
Status and Error registers will be available. The interrupt
signal of the SCSI PC is connected to the PCLO input of the DMAC
and may also cause an interrupt on the VMEbus. The interrupt
signal from the DMAC is sent to the Interrupter which will assert
the proper interrupt request line. The interrupt level is
selected by the Control Register outputs IRQLVO, IRQLVI and
IRQLV2 (3 binary encoded level outputs).
IRQLV2

IRQLVI

IRQLVO

c

c

INTERRUPT LEVEL

------------------------ ----------------(disabled)

0
0
0
0

0
0

0

1
1

0

2

1

3

1
1
1
1

0
0

0

4

1

1
1

0

5
6

1

7

1

1

Bit 3 of the Control Register may be used to disable the DMAC IRQ
line. This bit is used by the interrupt routine as follows.
-disable IRQ line (set bit 3).
-process the normal interrupt routine.
-disable IRQ line (clear bit 3).
This procedure is necessary to guarantee the proper working of
the Interrupter.

C
~
~
~

~

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Manual CC74 Ver 1.3

5-2

January 1986

•

•

•
•
•
•
.~

..

5.5 Bus Request
When the DMA controller needs control of the bus it will generate
a DMA Bus Request to the DTB requester. The level on which the
DTB requester will generate a Bus Request on the VMEbus depends
on the REQLVO, REQLVI outputs of the control register (2 binary
encoded level outputs).
REQLVI

REQLVO

o

o

o

1

1
2
3

o
1
1

BUS REQUEST LEVEL

o
1

The DMAC controls VMEbus utilization and request interval timing.
The Burst Transfer Mode, Cycle Steal Mode with or without hold,
Burst time and Bandwidth Ratio are also under software control .
5.6 Control Register

-~

.
.
..
..
..

The Control Register performs several functions. It is used to
select the levels for the DTB Requester and the Interrupter and
to enable/disable the DMA IRQ line. It is also used for
monitoring the SCSI Reset line (LRSTI) and may be used to
activate the SCSI Reset line (LRSTO). Note that when LRSTI is '1'
and LRSTO was written as '0', means that another device on the
SCSI bus is asserting the reset line. The following table shows
the bit assignments of the Control Register.
BIT

READ

WRITE

FUNCTION

IRQLVI
IRQLV2
ENIRQ
REQLVO
REQLVI
Spare
LRSTI

IRQLVl
IRQLV2
ENIRQ
REQLVO
REQLVI
Spare
LRSTO

Interrupt Request Level

----------------------------------------------------IRQLVO
IRQLVO
0
1

2
3
4
5
6
7

Enable DMA IRQ
DTB Request Level
Not used
SCSI Reset

5.7 AM Code Generation
When the DMA Controller is in the DMA mode, it will generate
Function Codes on its FCO-FC2 lines. These lines are software
programmable for source, destination and base address access (see
chapter 5.8.1). A translation of these lines is made to generate
the six Address Modifier code lines on the VMEbus. The following
table shows the translation and function of the respective lines.

..
-~

Manual CC74 Ver 1.3

5-3

January 1986

FC2 FC1 FCO

AM5 AM4 AM3 AM2 AMI AMO

FUNCTION

------------- --------------------------- ----------------0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

1
1
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1
1
1
1
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-1
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short
stand
stand
stand
short
stand
stand
stand

n.p.
n.p.
n.p.
n.p.
priv
priv
priv
priv

I/O
data
prog
prog
I/O
data
prog
prog

5.8 Programming the CC74 Module
Programming the CC74 module can be divided into two main
sections: programming the DMAC, and programming the SCSI Protocol
Controller. It is also necessary to program the desired interrupt
and bus request level as discussed in chapter 5.4 and 5.5
respectively. In chapter 5.8.1 the programming of the DMAC is
discussed. Chapter 5.8.2 discusses the programming of the SCSI
PC. A programming example is given in Appendix J.
5.8.1 Programming The DMA Controller
The 68450 DMAC has internal control registers and performs the
required operation by means of control words written in these
registers by the MPU. A normal programming sequence can be
divided into three phases.
The Initiation phase: MPU sets up control
address and transfer counts.
The

registers,

transfer

Transfer Phase: DMAC receives requests and transfers data.
The DMAC writes the transfer status into the error
register and the internal status register after the
completion of the transfer.

The Termination Phase: The MPU checks the post-transfer status.

~

~

c

short

c

The Device Control Register designates an external I/O device. It
will set the external request generation method, the
device type, the device port size, and
PCL
line
operation.

c

The internal registers are shown
description is given below.

in

Appendix

G

and

a

The Operation Control Register designates the transfer operation.
It designates the data transfer direction, the operand
size, the chain operation types, and
the
request
generation method.

C
..
~

Ia.
Manual CC74 Ver 1.3

5-4

January 1986

..
:

•

The

~

The Channel Control Register designates the channel operation. It
designates
operation start, the continuous-operation
setting, HALT, abort, and the interrupt enable/disable.

~

•

Sequence Control Register designates the increment/decrement
sequence of both memory
and
device
(source
and
destination) addresses.

The Channel Status Register contains the channel status. It shows
channel operation completion, block transfer completion,
normal termination, the error status, the channel active
state, and PCL signal line information.

I

The Channel Error
occurred.

I

The

•

•
•

•

•

Channel Priority
channel.

indicates

Register

what

determines

error

types

have

the priority of the

The Memory Transfer Counter is a l6-bit register to hold transfer
counts. The block size (transfer count) is written when
one data block is transferred. When multiple blocks are
transferred in Continuous Mode or Chaining Modes, the
next block size is automatically loaded in the MTC after
completion of the previous block transfer.
The Base Transfer Counter is used in Continuous Mode and Array
Chaining Mode. In Continuous Mode the first block size is
stored in the MTC and the second block size in the BTC.
The content of the BTC is copied into the MTC after
completion of the first block transfer. When more than
two blocks are transferred in this mode, the BTC and BAR
(described later) are rewritten and the CNT bit in the
CSR is set again during the second (or third) block
transfer. In Array Chaining Mode, the BTC holds the
number of blocks being transferred.
The Memory Address Register contains the memory address being
output for each transfer cycle. In block transfer, the
beginning address of the block is written in the MAR as
an initial value. And the content of the MAR varies
according to the contents of the OCR and the SIZE bits in
the SCR after one operand transfer. In Continuous Mode
and Chain Modes, the MAR is rewritten according to the
BAR or the array information in memory when a block
transfer completes.
The

•

Register

Device Address Register is used to address an I/O device (or
to address memory, in memory-to-memory transfer). The DAR
is used only in Dual Addressing Mode, and changes its
content according to the SCR and according to the SIZE
bits in the OCR.

The Base Address Register is used in Continuous Mode and Chain
Modes. In Continuous Mode, the start address of the
second block is written in the BAR. This BAR is used in
Manual CC74 Ver 1.3

5-5

January 1986

the same way as
address where the
contained.

the BTC. In Chain Modes, it keeps the
information of the next block is

The Memory Function Code, Device Function Code, and Base Function
Code Registers are used together with the MAR, DAR, and
BAR respectively. The MFC, DFC, and BFC are used with the
same purpose as the FC outputs from the MPU. This makes
it possible to transfer data between supervisor program
area and user data area, for example. A translation is
made to generate VMEbus AM codes from the Function Codes,
this is discussed in section 5.7.
The

Normal and Error Interrupt Vectors keep the vector numbers
outputted in the vector number fetch cycle (Interrupt
Acknowledge Cycle). When no error has occurred (ERR bit
of CSR is not set), the DMAC outputs the NIV contents.
When an error has occured (ERR=l), the DMAC outputs the
EIV contents.

The General Control Register is common to all four channels and
determines the DMAC's bus use ratio and sample interval
in limited Rate Auto-Request Mode. In Maximum Rate
Auto-Request Mode, the DMAC takes the bus mastership and
transfers all operands until they are exhausted. In this
mode, when the higher priority channels request transfer,
the channel with the Maxixmum Rate Auto-Request stops its
transfer temporarily and the higher priority channel is
serviced. The Maximum Rate channel resumes its transfer
after the priority channel has been serviced.
After the DMAC is properly initialized, a transfer is started by
setting the STR bit in the Channel Control Register. When the
DMAC completes a transfer operation, the COC (Channel Operation
Complete) bit in the CSR is set. If an error occurs during the
transfer, the ERR bit is also set. If the INT (Interrupt Enable)
bit has been set, the DMAC will issue an interrupt request when
the COC bit is set. If Interrupts are disabled, the MPU should
poll the COC bit. The transfer termination routine should check
for errors. Error routines should be programmed case by case
according to their applications. For bus error and address error,
the CER (Channel Error Register) can show which address register
caused the error and the address where the error occurred is kept
in the address register. The CER also shows which of the transfer
counters between the MTC and BTC caused the error.
5.8.2 Programming The SCSI Protocol Controller
The SCSI Protocol Controller has a set of 13 internal 8 bit
registers, which are used to read or write data, status and
control information. A summary of the SCSI registers is given in
appendix H. Note that some registers are read only. A normal
programming sequence where the CC74 module act as an Initiator on
the SCSI bus is as follows.

Manual CC74 Ver 1.3

5-6

January 1986

•
•

•
•

•

•
•

•

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.

Arbitration phase; Initiator arbitrates for the bus.
Selection phase; Initiator selects a Target.
Prepare SCSI chip and DMAC for data transfer.
Message-In phase (optional).
Command phase; give command to Target.
Data phase; transfer data (optional).
Status phase; get status from Target.
Receive command complete message.
Wait for disconnection.
Check for errors.

When the CC74 module acts as a Target, the programming sequence
can be as given below.
1.
2.
3.
4.
5.
6.
7.
8.
9.

Wait for selection.
Initiate a Message-In phase (optional).
Command phase; get command from Initiator.
perform command.
Data phase; transfer data (optional).
Status phase; send status to Initiator.
Message phase; send message to Initiator.
Disconnect initiator.
Idle mode.

Before any operations are performed, an Internal Diagnostic
Command should be given and status information checked for
succesful completion. After power-on
Reset,
the
Internal
Diagnostic Command is automatically executed.

~

i,

•
•

•

Manual CC74 Ver 1.3

•

5-7

January 1986

i

II

c

c

.

"
I
.i;

APPENDIX A

•

BLOCK DIAGRAM

,,~

•
--~

•
.-

•
C<

•
"

•

II

SCSI CONNECTOR

-*-i

VMEbus P2

1

III
S(SI BUS

\'

"
III

,.
III

.
~

"'1:

.-

,

ADDRESS
DE[ODER

684513

II

I

I
!

OMAC

F

\

I

DATA

&

'Ooms
BUS
BUFFERS

I

I BUS
I

I

1

L

I

LO[Al DATA BUS

II

I

DATA BUS
BUFFER

i

I

•

I

iNTERFACE

(ONTROl

I

BUFFER

.~

REGISTER

AC:JRESS BUS

ADDRESS BUS

SCSI

(ONTROL

II

CONTROL BUS

DTB REQUESTER

BUFFER

INTERRUPTER

"

I

VMEbus

.

..
•
--

-'l

Appendix CC74

A-1

January 1986

•
I

III

,.

..
!

APPENDIX B
SCHEMATIC DIAGRAM

•

•
•
-$1

•

Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet
Sheet

1
2
3
4
5
6
7
8
9

10
11
12

DMAC-VMEbus interface
Chip select logic
Interrupter / Bus requester
VMEbus interface
SCSI interface
SCSI-DMA transfer & control logic
Local data path
68450 DMAC / NCR 5386
SCSIbus connector / power supply
Decoupling
VMEbus connector PI
VMEbus connector P2

-~

-'l

l1li

III

..

.
-,.

Appendix CC74

•

B-1

January 1986

c

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CJ
~

EJ
0

EJ

00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00

000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000

('.J

000

CL

000
000
000
000
000
000
000
000
000
000

o~~

•

-=>

CD

0

>-

<:>
=>zV>

Q..

C>

o

~

000
000
000

o

•

..
.~.

Appendix CC74

C-1

January 1986

[
~
-

~

~

~
~
~
~

c

c
c
c

c

c
c

c

c

14

~
"

APPENDIX D

•

LIST OF COMPONENTS

~

•
'.

•
~

•
•

•
.~

..
-~
,

III
~'"

•
.~

•
.,.

•

..
~

.
~

.~

III

.
..~

-411

•
:~

iii

..
.~

,~

.-

r,

INTEGRATED CIRCUITS
Ul
U2
U3
U4
U5
U6
U7
U8
U9
UIO
Ull
U12
U13
U14
U15
U16
U17
U18
U19
U20
U2l
U22
U23
U24
U25
U26
U27
U28
U29
U30
U3l
U32
U33
U34
U35
U36
U37
U38
U39
U40
U4l
U42
U43
U44
U45
U46
U47
Appendix CC74

H068450-8
74S244, AS244, F244
74S244, AS244, F244
74LS373
74ALS645A-l
74ALS645A-l
74ALS645
74ALS645
74LS373
74LS373
74LS688, AMD2521
74LS688, AMD2521
74LS688, AMD2521
74S244, AS244, F244
PAL20L8A-2
FPLA82Sl53
74F74
XTAL Oscillator (optional)
AM2982l, 74AS821
PAL16R6A-2
PAL16R6A-2
PAL16R4A-2
74LS138
74LS641-l
74LS64l-l
74LS244, ALS244, AS244
74LS244, ALS244, AS244
74LS74
PAL20L8A-2
74S38
74LS273
74LS645
74LS645
74LS645
74LS04
74LS148
74LS240
NCR5386
XTAL Oscillator (10 Mc)
74S38
74S38
74LS640-l
74S38
74LS240
74S38
74S38
74LS240
0-1

January 1986

U48
U49
U50
U51
U52
U53

74LS125
PAL16L8A-2
74LS244, ALS244, AS244
74LS14
74LS164
74F244, AS244, S244

RESISTOR NETWORKS
RN1
RN2
RN3
RN4
RN5
RN6
RN7
RN8

220/330 Ohm
220/330 Ohm
3.9 K 10 Pin SIP
3.9 K 10 Pin SIP
390 10 Pin SIP
390 10 Pin SIP
3.9 K 10 Pin SIP
3.9 K 10 Pin SIP

MISCELLANEOUS
R1
R2
C1
C5
02-056
SlS2
S3
S4
PI
P2
P3
JB1
JB2
JB3
JB4
JB5
JB6
JB7

Resistor 330 Ohm
Resistor 330 Ohm
E1co 47uF 16V
Capacitor 220 pF
Decoup1ing Capacitor 0.1 uF
Binary Coded Hex Switch
Binary Coded Hex Switch
Binary Coded Hex Switch
Binary Coded Hex Switch
96 Pin DIN41612 Connector
96 Pin DIN41612 Connector
50 Pin Jumper Block (2 X 25)
2 Pin Jumper Block (1 X 2)
4 Pin Jumper Block (1 X 4)
3 Pin Jumper Block (1 X 3)
16 Pin Jumper Block (2 X 8)
4 Pin Jumper Block (2 X 2)
4 Pin Jumper Block (2 X 2)
4 Pin Jumper Block (2 X 2)

NOTE: Some parts may have been replaced by their equivalent types.

Appendix CC74

D-2

January 1986

•
•
APPENDIX E
CONNECTOR PIN ASSIGNMENTS

Pin Assignments PI

II
-.i\

II

III

--------------------------------------------------------PIN
NUMBER
1

2
3
4
5

6
7

8
9
III
-i,j

..
III

.

CC74

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

ROW A
SIGNAL
MNEMONIC

ROW B
SIGNAL
MNEMONIC

DOO
DOl
D02
D03
D04
D05
D06
D07
GND
SYSCLK
GND
DS1*
DSO*
WRITE*
GND
DTACK*
GND
AS*
GND
IACK*
IACKIN*
IACKOUT*
AM4
A07
A06
A05
A04
A03
A02
A01

BBSY*
BCLR*
BGOIN*
BGOOUT*
BG1IN*
BG10UT*
BG2IN*
BG20UT*
BG3IN*
BG30UT*
BRO*
BR1*
BR2*
BR3*
AMO
AM1
AM2
AM3
GND
GND
IRQ7*
IRQ6*
IRQ5*
IRQ4*
IRQ3*
IRQ2*
IRQ1*

+5 Volts

+5 Volts

ROW C
SIGNAL
MNEMONIC
D08
D09
D10
D11
D12
D13
D14
D15
GND
BERR*
SYSRESET*
AM5
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
All
A10
A09
A08
+5 Volts

---------------------------------------------------------

Appendix CC74

E-1

January 1986

-Pin Assignments P2

CC74

--------------------------------------------------------PIN
NUMBER

ROW A
SIGNAL
MNEMONIC

ROW B
SIGNAL
MNEMONIC

-DBO
-DB1
-DB2
-DB3
-DB4
-DB5
-DB6
-DB7
-DBP
GND
GND
GND
TRMPWR
GND
GND
-ATN
GND
-BSY
-ACK
-RST
-MSG
-SEL
-C/D
-REQ
-I/O
+5 Volts
REQ2
ACK2
PCL2
DONE
GND

+5 Volts
GND

ROW C
SIGNAL
MNEMONIC

----------- -------------- --------------- -------------1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

GND
+5 Volts

GND

GND
+5 Volts

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

ill

..

I

ill
I

.

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5 volts
REQ3
ACK3
PCL3
DTCP2
GND

---------------------------------------------------------

c
Appendix CC74

E-2

January 1986

I

"'"

II

•

•

Pin Assignments P3

•

------------------------------------PIN NR.
Description
--------------- --------------------2

..

-OBO
-OB1
-OB2
-OB3
-OB4
-OB5
-OB6
-OB7
-OBP
GROUND
GROUND
GROUND
TRMPWR
GROUND
GROUND
-ATN
GROUND
-BSY
-ACK
-RST
-MSG

4
6
8

10
12
14
16
18

•

20

22
24
26
28

30
32
34
36
38

•

40
42
44
46

•

CC74

-SEL
-C/D
-REQ
-I/O

48
50

------------------------------------II1II

Note : All odd pins are connected to ground, except pin 25.
Pin 25 is not connected.

l

•

'~
I

Appendix CC74

f~
I

E-3

January 1986

c
.c

c

•
APPENDIX F

•

MEMORY MAP

I

•
•

All addresses are offset from the hardware installed base adrress
of the CC74 module.

$000
DMA CONTROLLER
REGISTERS

•
-~

•
•

$OFF
$100
CONTROL REGISTER

one 8 bit register,
16 times duplicated
at odd addresses.

SCSI PC REGISTERS

sixteen 8 bit
registers at odd
addresses.

$llF

$120
$13F
$140
CONTROL REGISTER

$15F

•

$160
SCSI PC REGISTERS

$17F
$180
CONTROL REGISTER

S19F

•

.

SlAO
SCSI PC REGISTER

$lBF
$lCO
CONTROL REGS ITER

III

$lDF
$lEO

III

SCSI PC REGISTER

$lFF

•
Appendix CC74

F-1

January 1986

~

~
~
~
~

~

r

III

~
~

c
~""
-,

c

c
c
c

c

c
c
c

c
~

I

APPENDIX G

•

DMA CONTROLLER REGISTERS

•
•

$00

•

$3E

$01
CHANNEL 0
$3F

$41

$40
CHANNEL 1

•

$7F

$7E

•

$80

.

$BE

$81
CHANNEL 2
$BF
$C1

$CO

CHANNEL 3
III

$FE

GCR

$FF

III

~

•

•

Note:

The

General Control Register only resides at address

The following table shows the register arrangement of channel O.
Each register can be accessed by byte or word. However when STR
bit in CCR is set, only byte access is possible.

•

$00

.

$02
$04
$06

high

low

CSR {)

CER 0

$01
$03

I
OCR 0
--------------------------SCR 0
I
CCR 0
DCR 0

$05
$07

III

$09

$08
III

$FF

$OA

~

MTC 0

SOB

Table continued on next page

-~

Appendix CC74

G-1

January 1986

DMAC Register Table continued

SOC

MAR 0 (H)

$00

$OE

MAR 0 (L)

$OF

$10

$11

$12

$13

$14

DAR 0 (H)

$15

$16

DAR 0 (L)

$17

$18
$lA

$19
BTC 0

$1B

$lC

BAR 0 (H)

$10

$lE

BAR 0 (L)

$lF

$20

$21

$22

$23

$24

NIV 0

$25

$26

EIV 0

$27

$28

MFC 0

$29

$2A

$2B

$2C

CPR 0

$2F

$2E
DFC 0

$30

$31

$32

$33

$34

$35

$36

$37
BFC 0

$38

$3B

$3e

$3D

$3E

$3F

G-2

c
c

$39

$3A

Appendix CC74

c
c

$2D

Januar:~

1986

c
c

•

DNA CONTROLLER REGISTER DEFINITIONS

•
..

CSR
CER
OCR
OCR
SCR
CCR
NIV
EIV
CPR
MFC
DFC
BFC
MTC
BTC
MAR
DAR
BAR
GCR

.
•

•

Channel status Register
Channel Error Register
Device Control Register
Operation Control Register
Sequence Control Register
Channel Control Register
Normal Interrupt Vector
Error Interrupt vector
Channel Priority Register
Memory Function Codes
Device Function Codes
Base Function Codes
Memory Transfer Counter
Base Transfer Counter
Memory Address Register
Device Address Register
Base Address Register
General Control Register

III

III

.
..~

•

.
..

~

III

III

Appendix CC74

G-3

January 1986

I

I

APPENDIX H

•
~

SCSI CONTROLLER REGISTERS

All addresses are offset from the base address of the CC74 module.

•
$120

•

--------------------------DATNCR1

$121

COMNCR

$123

CNTNCR

$125

DESIDNCR

$127

AUXNCR

$129

lDNCR

$12B

lRQNCR

$12D

------------SRCIDNCR

$12F

DATNCR2

$131

DIAGNCR

$133
$135

•

$137

$13E

Appendix CC74

TCHINCR

$139

TCMINCR

$13B

TCLONCR

$13D

RESERVED

$13F

---------------------------

H-1

.January 1986

NCR 5385/6 REGISTER DEFINITIONS
DATNCRl
COMNCR
CNTNCR
DESIDNCR
AUXNCR
IDNCR
IRQNCR
SRCIDNCR
DATNCR2
DIAGNCR
TCHINCR
TCMINCR
TCLONCR

DATA REGISTER 1
COMMAND REGISTER
CONTROL REGISTER
DESTINATION ID REGISTER
AUXILIARY STATUS
ID REGISTER
INTERRUPT REGISTER
SOURCE ID REGISTER
DATA REGISTER 2 (NCR 5386 only)!
DIAGNOSTIC STATUS
TRANSFER COUNTER HIGH BYTE (MSEI)
TRANSFER COUNTER MIDDLE BYTE
TRANSFER COUNTER LOW BYTE (LSB)

..
i

III

c
c

c

Appendix CC74

B-2

..

•
I

INTERNAL REGISTERS
10 REGISTER

COMMAND REGISTER

7 6

5 4 3

2

0

765 432

0

I I I I I I I I I

1'--....1_-'--1-'1 ....1_ _ _ _ Command Code
00000
00001
00010
00011
00100
00101

I

•

•

.

,

INTERRUPT REGISTER

F unCllOn Complete
BusSerw:e
' - - - - Otsconnected
L...._ _ _ Selected
'--_ _ _ _ _ Resel&ded
'--_ _ _ _ _ _ _ (Used lor Testability)
'--_ _ _ _ _ _ _ _ Invaltd Command
L -_ _ _ _ _ _ _ _ _ _

Not Used

SOURCE 10 REGISTER

7

I

' - - - - - - - - - - - - - Single Byte T,ansfer

5

6

4

3

2

0

1-1-1-1 1 I

1-

III

I

' - - - - - - - - - - - - - - - DMA Mode

Source 10
10 VaIKI

CONTROl REGISTER

DIAGNOSTIC STATUS REGISTER

7 6 543 2

-"

ReseleCl Enabje
~-- Parity Enable
L-_ _ _ _ Phase Valid on REO"

•

0

I 1-\ I I I I I I
I I I

Sell-diagnost>c S1atus

.....- - - - - Reserved for
Synchronized Opera lion "

000

001
010
011
100
101
1 10
111

DESTINATION 10 REGISTER

7

6 543 2

0

1-1-1-1-1 11 I
1-'
. . -1_. .1____

•

Destination 10

001
010
011
100

AUXILIARY STATUS REGISTER

o

4

Successful CornpIeIIOn
Unc:ondtionaI Branch Fall
Data Reg Flill F aoIed
Inrti31 ConcitJons tncorrect

InrtoaI Command BIts Incorrect
Oiagnostic Flag FaoIed
Data Tumaround Faded
Nor Used

Diagnost>c Command Status

~-------------- Parity Thru Enable"

•

o

7 6 543 2

' - - - - - - - - - - - - - Reserved (MUST BE A ZERO)

SeIec1 Enabje

•

DevICe 10

Otsc:onnecl
Pause
SatATN
Message Accepted
Chop 0tsabIed

01000 Select w/ATN
01001 Select wlo ATN
01010 ReseIeCI
01011 DiagnoshC Data Turnaround
01100 R8C8MI Command
01101 ReclllVe Data
01110 RecetVe Message Out
01111 RecetVed Unspecified Inlo 0u1
10000 Send Status
10001 Send Data
10010 Send Message In
10011 Send Unspectfied Inlo In
10100 T ,ansfer Into
10101 T ,ansfer Pad

II

,..
,.

I I I

Chop Reset

Turnaround
Turnaround
Turnaround
Turnaround

Mlscompare (IMial)
Mlscompare (FIOal)

Good Panty
Bad Panty

Self-diagnost>c c(,mpIete

Data Register II Full"

.
..

Transfer Counter Zero
'--_ _ _ Paused

TRANSFER COUNTER

'-----110

'--_ _ _ _ _ C/D
'--_ _ _ _ _ _ _ MSG
L-_ _ _ _ _ _ _ _ _

Panty Error

AI

AO

o
o

o
I

o

SELECTED BYTE
Most Stgntficant Byte
Middle Byte
Least Stgntficant Byte

" -_ _ _ _ _ _ _ _ _ _ Data Register I Full

• NCR 5386 ONLY

--~

Appendix CC74

H-3

January 1986

c

c
c

c
~

I

•
.~

•
APPENDIX I

•

CONTROL REGISTER

•
•

•

CONTROL REGISTER (bit)

7

6

543

2

1

0

$101

•

IRQLVO
IRQLV1
IRQLV2
ENIRQ
REQLVO
REQLV1
spare
LRST

-~

•

IRQ LEVEL
IRQ ENABLE
REQUEST LEVEL
SCSI RESET

•

•

•
•
•

•
•
•

.
-~

..•~

III

Appendix CC74

1-1

January 1986

..

•
APPENDIX J

•

CC74 PROGRAM EXAMPLE

•

..
•
•
.-~

~
I

•
III

.
III

.
.
III

.
..

.

Appendix CC74

J-1

January 1986

•
•
•

•
•

PROGRAM EXAMPLE FOR CC-74
DMA-SCSI INTERFACE MODULE

•

•
•
•

•
•

The programs included in this manual are provided for
users and system programmers who want to write their own
SCSI driver routines for the CC-74 module. The two program
listings which are given in this document are; a program
with test routines, and a complete device driver for the
OS-9/68K* operating system. Both programs are written in
assembler and use the systype.d file for the global system
definitions.
Users are free to use this information as it is, or make
changes to the programs as seem appropriate to fit their
application.
Compcontrol disclaims any implied warranties and assumes
no responsibility for inaccuracies.
* - OS-9/68K is a registered trademark of Microware
Systems Corporation.

•
•
•
•

III
I

iii

!II

•

Page

systype.d

01/23/86 18:11

•

.

• System definition for CompControl CC74

SCSI interface board (OMA)

opt -1

•••••••••

..

• Edition History
date
cOlllllents

•

· --------•

01/04/85

first implementation CC74 system equates

•
III

• board base address
CC74_BASE equ $fffeOO
• hardware control register cc-74
CQNTROL74 equ $101 offset from cc-74 base

III

..

,

• NCR 5385 register offset def's
OATHCR
equ $121 data register to scsi bus
COMNCR
equ $123 command register
CNTNCR
equ $125 control register
OESIDNCR equ $127 destination id register
equ $129 auxiliary status register
AUXNCR
equ $12B id register
equ $120 interrupt register
SRCIDNCR equ $12F source id register
OIAGNCR equ $133 diagnostic status register
IONCR

•

.
..
-~

IRQNCR

TFRNCR

TCMONCR
TCMINCR

TCLENCR

equ $139 transfer counter register
equ $139 transfer counter most sign. byte
equ $13B transfer counter middle byte
equ $130 transfer counter least sign. byte

68450 base address
• DMA
CHNLO equ $00
CHNL1 equ $40
CHNL2 equ $80
CHNL3 equ $CO

GENCR equ CHNLO+$FF

III

III

-.,

68450 device definitions
• DMA
CSR equ 0 channel status register
CER equ 1 channel error register
OCR equ 4 device control register
OCR equ 5 operation control register
SCR equ 6 sequence control register

l1li

..
..
-J,

CHCR equ 7 channel control register
MTC equ $A memory transfer counter
MAR equ $C memory address register

OAR equ $14 device address register
BTR equ $lA base transfer register
BAR equ $lC base address register
NIV equ $25 normal interrupt vector
EIV equ $27 error interrupt vector
CPR equ $20 channel priority register

by

OJB

1

eystype.d

01/23/86 18: 11

Page

:1:

~
~
til

MFC equ $l9 • .-ory function codes
DPe equ $31 device function codes
aPe equ $39 base function codes

~
~

!II

~

•
• device control register (RIW)

•

~

BuratMod equ $00 burst transfer .ade
StealMod equ $80 cycle steal aode without hold
StealBld equ $CO cycle steal aode with hold
Dev68000
Devc6800
DevAck
DevAckRy

equ
equ
equ
equ

$00
$10
$20
$30

68000 compatible device. explicitly addressed
6800 compatible device. explicitly addressed
device with -ACK. implicitly addressed
device with -ACK and -READY. implicitly addressed

Dev8Bit equ $00 device pOrt 8 bit
Dev16Bit equ $08 device port 16 bit
DeVSiz_B equ 3 bit number of device port size

~
~

~

""~
~
~
II
i,

Statlnp
StatInpI
StartPls
AbortInp

equ
equ
equ
equ

0
1
2
3

status input - peripheral ctl line
status input with interrupt
start pulse. negative 1/8 clk
abort input

page

r
III

.
~

-

I

- Operation control register (RIW)

~

MemToDev equ $00 transfer from aemory to device
DevToMem equ $80 transfer frca device to memory
XfrDir_B equ 7 transfer direction bit number
ByteSize equ $00 operation size - byte
WordSize equ $10 operation size - word
LongSize equ $20 9peration size • long
ChainDis equ $0 chain operation disabled
ChainArr equ $8 array chaining enabled
ChainLnk equ $C linked chaining enabled
AuReqLim
AuReqMax
Reqlnit
ReqlnitA

II

equ 0
equ 1
equ 2
equ 3

auto
auto
-REQ
auto

request at rate set by GCR
request at aaximum rate
line intitiates all operand transfers
request first xfr. -REQ for all others

III

C

•i.
I

~
I
III

C

-.~

- Sequence Control Register (R/W)

,.

MemNoCnt equ 0 memory address register does not count
MemCntUp equ 4 memory address register counts up

I.

-

I~

~

I

~

r

01/23/86 18:ll

.y.type.d

•
MelaCntDn equ 8 IHIIIOry addre •• regi.ter count. down

i

DevNoCnt equ 0 device addre •• regi.ter doe. not count
DevCntUp equ 1 device addre •• regi.ter count. up
DevCntDn equ 2 device addre•• regi.ter count. down

I

•

•

.

•

•

• Channel Control Register (R/W)

NoOpPend equ $00 no operation is pending
StartOp equ $80 start operation
Start_B equ 7 bit number of start operation bit
NoContin equ $00 no continue operation is pending
ContinOp equ $40 continue operation
Contin_B equ 6 bit number of continue op bit

..
-ij

II1II
-~

•

OpNoHalt equ $00 operation not halted
OpBalted equ $20 operation halted
Balted_B equ 5 bit number of halted op bit
NoAbort
OpAbort
Abort B

equ $00 operation not aborted
equ $10 operation aborted
equ
bit number of abort op bit

"

IntrptDi equ 0 interrupts disabled
IntrptEn equ 8 interrupts enabled
Intrpt_B equ 3 bit nwaber of interrupt enable
page

•

•

• Channel Status Register (R/W)

•
•
•

writing a one into any bit clears that status
any written zero bits do not affect the status

•

•

•

OpNoComp equ $00 operation incomplete
OperComp equ $80 operation complete
OpComp_B equ 7 bit number of operation complete bit
BlkNoCmp equ $00 block transfer incomplete
BlkComp equ $40 block transfer complete
BlkCmp_B equ 6 bit number of block transfer complete bit
DevTrmAb equ $00 device termination abnormal
DevTrmNo equ $20 device termination normal
DevTrm_B equ 5 bit number of device termination status

•

•

ErrorSet equ $10 error occurred and is noted in CER
Error_B equ 4 bit number of error flag bit
ActiveCh equ 8 channel considered active

Page

3

ay.type.d

01/:Z3/86 18:11.

Page

4

Active_B equ 3 bit nUliber of active channel Uag bit
PCLTrana aqu 2 tranaition occurred on -PCL
PCLTrn_B equ 1 bit number of PCL tranaition Uag bit
equ 0 -PCL line low
PCLHigh equ 1 -PCL line high
PCLSta_B equ 0 bit number of -PCL status bit

PCLLow

•..

-

- Channel Error Register (R only)

-

ErConfig equ $01 configuration error
ErOpTimg equ $02 operation timing error
ErAdrMem equ $05 memory address error
ErAdrDev equ $06 device address error
ErAdrBas equ $07 base address error
ErBusMem equ $09 memory bus error
ErBusDev equ $OA device bus error
ErBusBas equ $OB base bus error

,.

.

ErCntMem equ $OD memory count error
ErCntDev equ $OE device count error
ErCntBas equ $OF base count error
ErEAbort equ $10 external abort
ErSAbort equ $11 software abort
page

*

* Cbannel Priority Register (R/W)

-

CbPriorO
CbPrior1
ChPrior2
CbPrior3

equ
equ
equ
equ

0
1
2
3

channel
channel
channel
channel

priority
priority
priority
priority

of
of
of
of

zero
one
two
three

*

*
*

Function Code Registers (R/W)

UserData
UserProg
SupvData
SupvProg

equ
equ
equ
equ

1 user data address access

2 user program address access
5 supervis_or data address access
6 supervisor program address access

c

*

c

•

01/23/86 18:11

8ptype.d

•
•

•

• General Control Regiater (R/W)

•
BuratTim equ $C mask for burst time
BandwRat equ $3 mask for bandwidth ratio
opt 1

•

.

..

.
III

.
..

.
..

~

•

•
•

• end of file

Page

5

rII

c

Microware OS-9/68000 Reaident Macro Aaaembler Vl.5

86/01/23

17:47

Page

1

tataca1.a
tatncr - OS-9/68000 CC-74 Teat Routinea

•
•

00001

nam

tatncr

00002

ttl

OS-9/68000

00006 •
00007 • Created at:

08 january 1985

•

00008 • Created by:

D. J. Bosma and N. Noordam

•

00011
00012

•

00009 •
00010

•
•

use

defsfile
1

00013
00014

00000001 Edition
00000101 Typ_Lang

aet
set

00015

00008000 Attr Rev

set

(Prgrm« 8) +Objct
(ReEnt«8)+0'

psect

tstncr.Typ_Lang.Attr_Rev.Edition.l00.Start
$20

00016
00017

•

CC-74 Teat Routinea

00003 •
00004 • Teating CC-74 with NCR 5385 with Xebec controller S 1410-A
00005· uaing DMA controller 68450 and non atandard Irq routine

00018
00019

00000020 SPACE

equ

00020

00000020 space

equ

$20

00021

OOOOOOOd CR

equ

SOd

00022

OOOOOOOd cr

equ

00023

OOOOOOOa LF

equ

SOd
$Oa
$Oa

00024

OOOOOOOa I f

equ

00025

00000000 Stdln

equ

0

00026

00000001 StdOut

equ

1

00027

00000002 StdErr
0000004a EscFlg

equ

2

equ

CHNL1+MTC

0000004e SavSts

equ

CHNLl+MAR

00028
00029

Use this registers for irq communication

00030

•

00031
00033
00034

III

.
.
..
-~

.
..
--01

-~

•
•

vsect

00032

00035
00036
00037
00038
00039
00040

00000000 Char Buf:
OOOOOOOa HD cmd:
OOOOOOOb HDysn:
OOOOOOOe HD blk:

ds.b
ds.b
ds.b
ds.b
ds.b

OOOOOOOf HD ctrl:
00000010 HD status: ds.b
00000011 HD_msg:
ds.b

00041

00000012 HD_buffer: ds.b
00000112 HD sense: ds.b

00042
00043

00000116 Drive no:
00000000

ds.b

10
1
3
1
1
1
1
256
4
1

ends

00044 •
00045 • Start of program. display menu
00046 *
movea.l IICC74_BASE.a5
00047 0000 2a7c Start:
OOfffeOO

get base addres of CC-74

00048 0006 6100
05dO

bsr

Init74

init ee-74

00049 OOOa 6400

bee

Menu

no error's

001a
00050 OOOe 4lfa
Ocfa

lea

msg2(pe).aO

00051 0012 303e
0001

move.w

IIStdOut.dO

00052 0016 223e
00000019

move. 1

IIszmsg2.dl

00053 001e-4e40
0000

os9

I$Write

00054 0020 4281

clr.l

d1

print "init cc-74 error"

Mieroware OS-9/68000 Resident Macro Aas . .bler Vl.5 86/01/23 17:47
tataeat .•
tatner - OS-9/68000 CC-74 Teat Routines
00055 0022-4.40
os9
F$Exit
atop test prog
0000
00056 0026 41f. Menu:
lea
_gl(pc) ••O
Ob36
00057 002. 303e
IIOve .•
'StdOut.dO
0001
00058 002e 223e
IIOve.l
.sz.sgl.cU
000001ae
00059 0034-Ce40
oa9
I$Write
print menu
0000

00060 0038 303e
0000
00061 003e 7202
00062 003e 41ee

Menu1

Menu2

Menu3

Menu4

MenuS

Menu6

2

~

~
~
~
~

move .•

'Stdln.dO

moveq
lea

'2.d!
Cbar_Buf(a6).aO

os9

I$ReadLn

move.b

Cbar_Buf(a6).dO

ClIp. b

"I' .dO

bne.a
bar

Menu1
Testl

bra.s
cmp.b

Menu
"2' .dO

bne.s
bsr

Menu2
Test2

C

bra.s
ClIp. b

Menu
"3' .dO

C

bne.s
bsr

Menu3
Test3

C

bra.s
cmp.b

Menu
"4' .dO

bne.s
bsr

Menu4
TeaU

bra.s
ClIp. b

Menu
"5' .dO

bne.s
bsr

MenuS
TestS

bra.s
ClIp. b

Menu
"6' .dO

bne.s
bsr

Menu6
Test6

bra.s
ClIp. b

Menu
"7' .dO

.

bne.s
bsr

Menu7
Test7

C

bra.s

Menu

~

0000

00063 0042-4840
0000
00064 0046 102e
0000
00065 004a b03e
0031
00066 004e 6606
00067 0050 6100
0176
00068 0054 60dO
00069 0056 b03e
0032
00070 005a 6606
00071 005e 6100
026e
00072 0060 60c4
00073 0062 b03e
0033
00074 0066 6606
00075 0068 6100
02ea
00076 006e 60b8
00077 006e b03e
0034
00078 0072 6606
00079 0074 6100
0328
00080 0078 60ae
00081 007a b03e
0035
00082 007e 6606
00083 0080 6100
0386
00084 0084 60aO
00085 0086 b03e
0036
00086 008a 6606
00087 008e 6100
03f2
00088 0090 6094
00089 0092 b03e
0037
00090 0096 6606
00091 0098 6100
045e
00092 00ge 6088

:Page

get one character

~

.~
~
~

C
C

C

C
C
r-

C
~

I

J
I

iii

.1
.
.
.
..

Microware 08-9/68000 Resident Mscro Aas . .bler Vl.S
tstscsi.s

-j

1

'I

iii

1

III

.
-~

'1!

III

.

1I
I

..

11:41

Page

tstncr - OS-9/68000 CC-14 Te.t Routines
00093 00ge b03c Menu1
ClIp. b
"8' .dO
0038
00094 00.2 6608
bne .•
Menu8
00095 00s4 6100
b.r
Te.ta
04bc
00096 00a8 6000

"I

'I

86/01/23

brs

Menu

U1c
00091 OOac b03c Menu8
0039
00098 OObO 6608

cmp.b

"9' .dO

bne.s

Menu9

00099 00b2 6100

bsr

Test9

bra

Menu

andi.b

I$df.dO

cmp.b

"A' .dO

bne.s

MenuA

bsr

Buffl

bra

Menu

cmp.b

"B' .dO

0518
00100 00b6 6000
ff6e
00101 OOba 0200 Menu9
OOdf
00102 OObe b03c

make upper case

0041
00103 00c2 6608
00104 00c4 6100
0046
00105 00c8 6000
ffSe
00106 OOce b03e MenuA
0042
00101 OOdO 6608
00108 00d2 6100
OObe
00109 00d6 6000

bne.s

MenuB

bsr

Buff2

bra

Menu

cmp.b

"C' .dO

bne.s
bsr

MenuC

bra

Menu

cmp.b

I'D' .dO

ff4e
00110 OOda b03e MenuB
0043
00111 OOde 6608
00112 OOeO 6100
0818
00113 00e4 6000

Askid

ff40

!

~

II
;;

..
..
..
..
~

c4

.,

•
.

..
-i1

00114 00e8 b03e MenuC
0044
00115 OOec 6608
00116 OOee 6100

bne.s

MenuD

bsr

Askdn

0856
00117 00f2 6000

bra

Menu -

ff32
00118 00f6 41ta MenuD

lea

msg4 (pc) • aO

IIOve.w

IStdOut.dO

IIOve.l

Iszmsg4.d1

os9

I$Write

bra

Menu

OeS2
00119 OOfa 303e
0001
00120 OOfe 223e
00000009
00121 0104=4e40

print "What?"

0000
00122 0108 6000
ff1e
00123
00124
00125

*
*
*
*

Buffl
Show the HD_buffer

00126
00127 010e 6100 Buff1:
00ge

bsr

wrerlf

00128 0110 43ee

lea

HD_buffer(a6).a1 HD buffer start buffer

3

lticrowere 05-9/68000 Reaident Macro Aa. . .b1er V1.5
t.tec.t.e

86/01/23

17:'7Peoe

"

t.tncr - 05-9/68000 CC-7' Te.t Routine.
0012
00129 0114 2'3c
OOOOOOOf

IIIOve.1

115.d2

Number of line'. (16)

00130 011e 263c buff11
OOOOOOOf

IIIOve.1

115.d3

Number of byte./1tlrle

00131 0120 'lee buff12
0000

lea

Ch.r_Buf(a6) .aO start output buff'!r

00132 012' 5688
00133 0126 10bc

addq.l

13.eO

move.b

'$20. (aO)

0020
00134 012a 113c

move.b

I$20.-(aO)

III
II

put two spaces in 'outputbuffer

0020
00135 012e 1a19
00136 0130 283c

move.b

(a1) •• d5

get first byte

IIIOve.l

'1.d4

number of nibbles

IIIOve.b

d5.d6

use d3 a. scratch

lsr.l
and1.b

l4.d5
I$f.d6

get nibble for next loop

OOOf
00140 013e de3e

add.b

I$30.d6

0030
00141 0142 be3e

cmp.b

'$39.d6

00142 0146 6304
00143 0148 de3e

bls .•
add.b

bufn4

0007
00144 014c 1106 buff14
00145 014e 51ce

move.b
dbra

d6.-{aO)
d4.buff13

ffe6
00146 0152 303c

IIIOve.w

IStdOut.dO

0001
00147 0156 223c

move. 1

'4.ill

os9

I$Write

00149 0160 51cb

dbra

d3.buff12

ffbe
00150 0164 6100

bsr

wrcrlf

0044
00151 0168 SIca

dbra

d2.buff11

ffbO
00152 016c 6100

bsr

wrerlf

003c
00153 0170 41fa

lea

msg7(pc).aO

00154 0174 303e

move.w

IStdOut.dO

0001
00155 0178 223e

move. 1

Iszmsg7.d1

OOOOOOOe
00156 017e&4e40

os9

I$Write

0000
00157 0182 303c

move.w

IStdOut.dO

00000001
00137 0136 lc05 buff13
00138 0138 e88d
00139 013a 0206

0039

III

l7.d6

next nibble

number of bytes

00000004
00148 015c=4e40
0000
next byte

next line

Oe29

0001
00158 0186 7201

moveq.l

Il.ill

00159 0188 41ee

lea

Char_Buf(a6),aO

00160 018c a 4e40
0000

os9

I$ReadLn

00161 0190 4e75

rts

0000

00162
00163

*
*

Buff2

•

Microware OS-9/68000 Reaident Macro Aaa . .bler Vl.5

86/01/23

17:47

Page

5

tatacai.a
tstncr - OS-9/68000 CC-74 Test Routines

•
•
:.

•
•
--~

•
•

.
..

00164·

Fill HD_buffer with constant

00165 •
00166 0192 6100 Buff2:

bsr

AakCon

0724
00167 0196 6510

bca.s

00168 0198 41ee

lea

error. leave
buff22
HD_buffer(a6).aO

0012
00169 019c 223c

IIOve.l

'63.d1

HD_butter size divided by 4
fill with constant

get constant. return in dO

0000003f
00170 01a2 20cO buff21

IIOve.1

dO. (aO) +

00171 01a4 51c9

dbra

dl.buff21

fffc
00172 01a8 4e75 buff22

rts

00173 •
00174 • CR/LF
print cr/lf
00175 •
00176 •
00177 01aa 41ee wrcrlf

lea

Char_Buf(a6).aO

0000
00178 01ae 5288
00179 01bO 10bc

addq.l

l1.aO

move.b

'$Od.(aO)

OOOd
00180 01M 113c

move.b

'$Oa.-(aO)

OOOa
00181 01b8 303c

move.w

'StdOut.dO

00182 01bc 223c
00000002

move. 1

'2.d1

00183 01c2=4e40

os9

I$Write

0000
00184 01c6 4e75

rts

0001

.
.
:01

write CR/LF

00185 •
00186 • TEST1 : internal diagnostic
00187 *
ram test
init drive characteristics
00188 *
00189 *
00190 01c8 2d7c Test1:
IIOve.l
,0.HD_cmd(a6) clr psn
00000000
OOOa
00191 01dO 102e
IIOve.b
Drive_no(a6).dO
0116
00192 01d4 812e

or.b

dO.HDysn(a6)

DIOve.b

'$e4.HD_cmd(a6) diagn cmd

OOOb

•
•
..

~

00193 01d8 1d7c
00e4000a
. 00194 01de 43ee

lea

HD_cmd(a6).a1

cmd ptr

OOOa
00195 01e2 323c

move.w

'6.dl

get count

0006
00196 01e6 6100

bsr

NCRcmd

045a
00197 Olea 6530
00198 01ec 47ee

bcs.s
lea

test11ex
HD_status(a6).a3

0010
00199 OlfO 6100

bsr

NCRstatus

04ea
....~

•

00200 Olt4 47ee
0011

lea

00201 Olt8 6100
0500

bsr

NCRmsg

00202 Oltc 082e

btst

'1.HD_status(a6)

Microw.re OS-9/68000 Reaident Macro Aaa . .bler V1.S 86/01/23 17:47 P.ge
tatacai .•
tatncr - OS-9/68000 CC-74 Teat Routinea
00010010
00203 0202 6700
beq
teatl2
akip if no error
001.
00204 0206 uta
le.
emag1(pc) •• 0
Obf9
00205 020. 303c
.ove.w
'StdOut.dO
0001
00206 020e 223c
.ove.l
•• zemag1.dl
00000025
00207 0214-4e40
089
I$Write
write error message
0000
00208 0218 6100
bar
Ben. tat
060.
00209 021c 4e75 test11ex
rts
00210
00211 * start of ram test
00212 021e Id7c test12:
move.b
'$eO.HD_cmd(a6)
OOeOOOOa
00213 0224 43ee
lea
HD_cmd(a6).al cmd ptr
OOOa
00214 0228 323c
move.w
'6.d1
eount
0006
00215 022c 6100
bsr
HCRcmd
0414
00216 0230 6530
bcs.s
test12ex
00217 0232 47ee
lea
HD_status(a6).a3
0010
00218 0236 6100
bsr
HCRstatus
04a4
00219 023a 47ee
lea
HD_msg(a6).a3
0011
00220 023e 6100
bsr
HCRmsg
04ba
00221 0242 082e
btst
fLHD_status(a6)
00010010
beq
00222 0248 6700
test13
skip if no error
001a
00223 024e 4lfa
lea
emsg2(pc).aO
Obd8
00224 0250 303c
move.w
'StdOut.dO
0001
00225 0254 2239
move.l
szemsg2.d1
0000001a
os9
00226 025a=4e40
I$Write
0000
00227 025e 6100
bsr
senstat
05c4
00228 0262 4e75 test12ex
rts
00229
00230 * start init drive parameters
00231 0264 ld7c testl3:
move.b
'$Oe. HD_cmd (a6) init drive param
OOOeOOOa
lea
HD_cmd(a6).al
00232 026a 43ee
OOOa
00233 026e 323e
move.w
f6.dl
0006
00234 0272 6100
bsr
HCRcmd
03ee
00235 0276 653e
bes.s
test13ex
lea
HD-par88(pe).a2 get param table
00236 0278 45fa
08de

6

..
i

II

..
..
ill

III
i

II

•

Mierovare OS-9/68000 Reaident Macro As.embler V1.5
tat.eai._

86/01/23

17:47

Page

tatner - OS-9/68000 CC-74 Teat Routin ••
00237 027e 3Ue
move.w
18.d2
0008
HCRd_twr
00238 0280 6100
bar

~

I
'I

•
.:1

•

052a
00239 0284 47ee

lea

HD_atatua(a6).a3

00240 0288 6100

bar

HCRatatua

0452
00241 028e 47ee

lea

HD_mag(a6) ,a3

bar

NCRmag

00243 0294 082e
00010010

btst

I1.HD_atatus(a6)

00244 029a 6700

beq

test14

001a
00245 02ge 41ta

lea

emsg3(pe) .aO

move.w

IStdOut.dO

move. 1

Iszemsg3. dl

os9

I$Write

bsr

senstat

0010

0011

j

•
~

•
4i

00242 0290 6100
0468

•

00246 02a2 303e

'1

0001

..
..
'ill

~

,.
>i!

III

'.
•
ccl

III

ObaO

00247 02a6 223e
00000027
00248 02ae-4e40
0000
00249 02bO 6100
0572
00250 02M 4e75 test13ex
00251
00252 02b6 41fa test14
Oa6b
00253 02ba 303e

lea

msg3(pe) .aO

move.w

IStdOut.dO

00254 02be 223c
00000027
00255 02c4-4e40
0000

move. 1

Iszmsg3.dl

os9

I$Write

00256 02c8 4e75
00257

rts

0001

00258
00259 •
00260 • Test2
Test drive ready command

00261 •
i~

III

..
.
.
'.~

I

~~

..
:::;~

~

III
..

; ~

rts

00262 •
00263 • Input
00264 •
00265 • Exit
00266 •
00267 02ca 2d7c Test2:
00000000

move. 1

'0.HD_cmd(a6)

clr psn

move.b

Drive_no(a6).dO

or.b

dO.HDysn(a6)

00270 02da 1d7c
OOOOOOOa

move.b

'$00.HD_cmd(a6) Test drive ready cmd

00271 02eO 43ee
OOOa

lea

HD_cmd(a6).al

cmd ptr

00272 02e4 323c
0006
00273 02e8 6100

move.w

1t6.dl

get count

bsr

HCRcmd

OOOa
00268 02d2 102e
0116
00269 02d6 812e
OOOb

7

Microw.r. 05-9/68000 Resident Macro Aaa . .bler V1.5

86/01/23

17:47

Page

tatacai ••
tatncr - 05-9/68000 CC-74 Teat Routine.
0358
00274 02.c 6530
00275 02 •• 47••

bea.a
1 ••

t.at2ex
RD_atatua(.6).a3

00276 02f2 6100
03e8

bar

NCRatatua

00277 02f6 47••

lea

BD_mag(a6).a3

00278 02fa 6100

bar

NCRmag

03ta
00279 02fe 082e

btat

fl.RD_status(a6)

beq

test21

lea

emsg4(pc) .aO

move.w

,gtdOut.dO

00283 0310 223c
00000022

move. 1

Iszemsg4.d1

00284 0316:4e40

os9

I$Write

0000
00285 031a 6100

bsr

senstat

00286 031e 4e75 test2ex
00287 0320 41fa test21
OaOl

rts
lea

msg3(pc).aO

00288 0324 303c

move.w

,gtdOut.dO

move.l

'szmsg3.d1

os9

I$Write

0010

0011

00010010
00280 0304 6700

skip if no error

001a
00281 0308 41ta
Ob5d
00282 030c 303c
0001

write error message

0508

0001
00289 0328 223c
00000027
00290 032e=4e40
0000
00291 0332 4e75

rts

00292 •
00293 • Test3
Format Drive
00294 •
Input
00295 •
00296 •
00297 • Exit
00298 •
00299 0334 2d7c Test3:

clr psn

move.l

'0.RD_emd(a6)

move.b

Drive_no(a6).dO

00301 0340 812e
OOOb

or.b

dO.RDysn(a6)

00302 0344 1d7e
0004000a

move.b

'$04.BO_emd(a6) Format Drive emd

00303 034a 43ee

lea

BO_emd(a6).al

emd ptr

00304 034e 323c
0006

move.w

'6.dl

get count

00305 0352 6100
02ee
00306 0356 6530

bsr

HCRemd

bes.s

test3ex

00307 0358 47ee
0010

lea

RO_status(a6).a3

00308 035c 6100
037e

bsr

HCRstatus

00000000
OOOa
00300 033c 102e
0116

OOOa

8

•
"I

•

•
"

•
•

•

Microw.ra OS-9/68000 Reaident Macro Aaa . .bler Vl.S
tatacai .•
tatncr - OS-9/68000 CC-74 Taat Routine.
HD__ g(a6) .a3
00309 0360 47ae
l.a

li

•

bar

NCRma"

0394
00311 0368 082e
00010010

btat

.1.RD_atatua(e6)

00312 036e 6700

-~

..
' '1

~

.
.J

'"

•

beq

teat31

lea

emsgS(pc) .aO

.ave."

'StdOut.dO

.ave. I

.szemsg5.d1

os9

I$Write

00317 0384 6100
04ge

bar

senstat

00318 0388 4e75 test3ex

rts

00319 038a 4Ha test31
0997

lea

msg3(pc) .aO

00320 038e 303c

.ave."

'StdOut.dO

lIIOVe.1

Iszmsg3.dl

089

I$Write

00313 0372 4Ha
00314 0376 303c
0001
00315 037a 223c
OOOOOOH
. 00316 0380-4e40

0001
00321 0392 223c
00000027
00322 0398 .. 4e40
0000
00323 039c 4e75
00324
00325
00326
00327
00328
00329

*
*
*
*
*
*
*

Input
Exit

00330
00331 03ge 2d7c Test4:
00000000

lIIOVe.l

'0.HD_cmd(a6)

IDOve.b

Drive_no(a6).dO

or.b

dO.HDysn(a6)

IDOve.b

'Se3.HD_cmd(a6) Drive Diagnostic cmd

00335 03M 43ee
OOOa

lea

RD_cmd(a6).al

cmd ptr

00336 03b8 323c
0006

.ave.w

'6.dl

get eount

~jt

00337 03bc 6100

bsr

HCRcmd

•

clr psn

OOOa
00332 03a6 102e
00333 03aa 8l2e

.

rts

Test4
Drive Diagnostic

•
'i

write error message

0000

0116

•

skip if no error

OblS

~

.~

OOOb
00334 03ae ld7c
00e3000a

0284
00338 03eO 6530

bes.s

test4ex

lea

RD_status(a6).a3

·-4

00339 03e2 47ee
0010

•

00340 03c6 6100
0314

bsr

HCRstatus

~

00341 03ea 47ee
0011

lea

HD_msg(a6) .a3

00342 03ee 6100
032a

bsr

HCRmsg

00343 03d2 082e
00010010

btst

n.RD_status(a6)

III

.
4

·11

Page

001a

-~

•

17:47

0011
00310 0364 6100

~

.

86/01/23

9

~

86/01/23

Microwsre OS-9/68000 Resident Macro Aaseabler Vl.5

17:47

Page

10

i:

~

tstscat..
tstncr - OS-9/68000 CC-74 Teat Routines
beq
test31

00344 03d8 6700

skip it no error

ttbO
00345 03dc Ute

~

~

Ie.

_g6(pc) .sO

00346 03eO 303c
0001

IIOve .•

'StdOut.dO

00347 03e4 223c

IIOve.1

lazemsg6.dl

os9

I$Write

bsr

senstat

•
..

~

Oaca

00000022
00348 03ea-4e40

write error messag'e

0000
00349 03ee 6100

~

0434
00350 03t2 4e75 test4ex

rts

00351 03t4 4Ua test41

lea

msg3(pc).aO

move.w

'StdOut.dO

move. I

Iszmsg3.dl

os9

I$Write

III
I

092d

00352 03t8 303c

~

0001
00353 03fc 223c

.
I

00000027
00354 0402=4e40

..~

0000
00355 0406 4e75
00356
00357

rts

*
*
*

~

TestS
Read One Sector
00358
Input
00359 •
00360 •
00361 • Exit
00362 •
00363 0408 6100 TestS:

~
~

bsr

AskPsn

return in dO
error in PSN
store psn

058a
00364 040c 6570

bes.s

test52

00365 040e 2d40

move.l

dO.HD_cmd(a6)

move.b

Drive_Do(a6).dO

or.b

dO. HDJ>sn (a6)

OOOa
00366 0412 102e

~

.
.~
II
I

II

0116
00367 0416 812e

~

OOOb
00368 041a Id7c

II
move.b

1$08.HD_cmd(a6) Read sector(s) cmd

00369 0420 43ee
OOOa

lea

HD_ClBd(a6).a1

cmd ptr

00370 0424 323c

move .•

16.en

get eount

bsr

NCRcmd

0008000a

0006
00371 0428 6100

~

~
~

~

0218
00372 042e 653c

bes.s

test5ex

00373 042e 343c
0100

move .•

1f$100.d2

00374 0432 45ee
0012

lea

HD_buffer(a6).a2

00375 0436 6100

bsr

NCRdatrd

00376 043a 47ee
0010

lea

HD_status(a6).a3

00377 043e 6100
02ge

bsr

NCRstatus

00378 0442 47ee
0011

lea

HD_msg(a6).a3

00379 0446 6100
02b2

bsr

NCRmsg

02fc

~

I

II

C

,.
I

III

....
I

r

I~

..

"

•
~

•
•

•
..

III
Cj

•
~

•
~

•
lj

•

.
"1

:~

iii

.
-~

-'"

•

..
..
'1

~

.
..
;~

-~

-~-~

III

.
:~

~
iC~

Microwar. OS-9/68000 R.sident Macro Aas . .b1.r Vl.5 86/01/23 17:47 Page
tstscsi.a
t.tncr - OS-9/68000 CC-74 T•• t Routin.s
00380 044a 082.
btat
I1.HD_status(a6)
00010010
00381 0450 6700
beq
t.st51
skip if no error
001a
00382 0454 Ufa
1.a
...g7(pc).aO
Oa74
00383 0458 303c
IIOve .•
'StdOut.dO
0001
00384 045c 223c
move. 1
"z_g7.dl
00000021
00385 0462-4e40
os9
I$Write
write error meBaage
0000
00386 0466 6100
bar
aenstat
03be
00387 046a 4e75 test5ex
rts
00388 046c Ufa test 51
lea
IISg3 (pc) • aO
08b5
00389 0470 303c
DIOve ••
'StdOut.dO
0001
00390 0474 223c
DIOVe.l
Iszmag3,dl
00000027
00391 047a-4e40
os9
I$Write
0000
00392 047e 4e75 teBt52
rts
00393 *
00394 * Test6
00395 *
Write One Sector
00396 * Input
00397 *
00398 * Exit
00399 *
00400 0480 6100 Test6:
bsr
AskPBn
return in dO
0512
00401 0484 6570
bes.s
test62
error in PSH
00402 0486 2d40
DIOVe.1
dO. BD_ emd(a6) store psn
OOOa
00403 048a 102e
DIOve.b
Drive_no (a6) ,dO
0116
00404 048e 812e
or.b
dO, BDJlsn (a6)
OOOb
00405 0492 Id7c
IIOve.b
'$Oa,BD_emd(a6) Wr~te sector(s) emd
OOOaOOOa
00406 0498 43ee
lea
BD_and(a6).al cmd ptr
OOOa
00407 049c 323c
DIOve.w
16.d1
get count
0006
00408 04aO 6100
bsr
HCRemd
01aO
00409 04a4 653c
bCB.S
test6ex
00410 04a6 343c
DIOve.w
'$100.d2
0100
00411 04aa 45ee
lea
BD_buffer(a6).a2
0012
00412 04ae 6100
bBr
HCRdatwr
02fc
00413 04b2 47ee
lea
BD_status(a6).a3
0010
00414 04b6 6100
bsr
HCRstatus
0224
00415 04ba 47ee
lea
RD_mag(a6) •• 3
0011

11

~crovar.

05-9/68000 Reaident Macro Aaaembler Vl.S 86/01/23
tatacai .•
tatncr - 05-9/68000 CC-74 T.at Routinea
00416 04be 6100
NCRIIIag
bar
023a
00417 04c2 012.
fl.RD_atatua(.6)
btat

17:47

Page

00010010
00418 04c8 6700

001a
00419 OCcc 41ta
Oald
00420 04dO 303c

akip if no error

~

~

r

lea

t!IIISg8(pc) .aO

IIOve ••

'StdOut.dO

IIOve.1

Iszemsg8.dl

os9

I$Write

bar

senstat

~

rts
lea

BlSg3(pc) .aO

~

IIOve.w

IStdOut.dO

IIOve.1

Iszmsg3.dl

os9

I$Write

II

~

~

r.
write error messallie

II

0000

00423 04de 6100

I

teat61

00000022

00422 04da-4e40

~

I

beq

0001

00421 04d4 223c

12

0344
00424 04e2 4e7S test6ex

00425 04e4 41fa test61
083d
00426 04e8 303c
0001
00427 04ec 223c
00000027
00428 04f2-4e40
0000
00429 04f6 4e75 test62

~

.
II
~

rts

!II
~

00430 •
00431 • Test7
Seek to Sector command
00432 •
00433 • Input
00434 •
00435 • Exit
00436 •
00437 04f8 6100 Test7:
049a
00438 04fc 6562
00439 04fe 2d40
OOOa
00440 0502 102e
0116
00441 0506 812e
OOOb
00442 050a 1d7c
OOObOOOa
00443 0510 43ee
OOOa
00444 0514 323c
0006
6100
00445 0518
0128
00446 051c 652e
00447 051e 47ee
0010
00448 0522 6100
01b8
00449 0526 47ee
0011
00450 052a 6100
Olee
00451 052e 082e
00010010

bsr

AskPsn

return in dO

bes.s
IIOve .l.

test72
dO. RD_cmd (a6)

error in PSN
store psn

RIOve.b

Drive_no(a6).dO

or.b

dO.RDysn(a6)

IIOve.b

'SOb.RD_cmd(a6) Seek sector cmd

lea

RD_cmd(a6).al.

cmd ptr

move.w

16.dl

get count

bsr

NCRcmd

bes.s
l.ea

test7ex
RD_status(a6).a3

bsr

HCRstatus

lea

RD_BlSg(a6) .a3

bsr

NCRmsg

btst

Il.RD_status(a6)

-.~
r
III

r'

~

.
..
~

~

r-III
~
ill
~
I

I.

C

C

..

~
~

I
~

•
:;I

•

,.

•

,.

•
~

•
;j

II
11

•
-~

.j
~
III
~

III
~

•
:iI

•
c~

•
.~

•
-4\

•
~

•

..
.~

.
~

~

Microvare 08-9/68000 Reaident Macro Aaa . .bler VI.5 86/01/23 17:47 Page
tat.c.i ••
t.tncr - 08-9/68000 CC-74 T.at Routin ••
00452 0534 6718
beq.s
t •• t71
skip it no .rror
00453 0536 uta
1••
"'g9(pc) ••0
09d5
00454 053. 303c
IIOve.w
'StdOut.dO
0001
00455 053e 223c
IIOve.l
lazemsg9.dl
00000020
00456 0544-4e40
0.9
I$Write
write error mesaage
0000
00457 0548 6100
bar
aenatat
02da
00458 054c 4e75 test7ex
rt.
00459 054e uta teat7l.
lea
msg3(pc) .aO
07d3
00460 0552 303c
move .•
'StdOut.dO
0001
00461 0556 223c
move. 1
'azmsg3.dl
00000027
00462 055c-4e40
os9
I$Write
0000
00463 0560 4e75 test72
rts
00464 •
00465 • Test8
Recalibrate command
00466 •
00467 • Input
00468 •
00469 • Exit
00470 •
00471 0562 2d7c Test8:
00000000
OOOa
00472 056a 102e
0116
00473 056e 812e
OOOb
00474 0572 1d7c
0001000a
00475 0578 43ee
OOOa
00476 057c 323c
0006
00477 0580 6100
OOcO
00478 0584 6530
00479 0586 47ee
0010
00480 058a 6100
0150
00481 058e 47ee
0011
00482 0592 6100
0166
00483 0596 082e
00010010
00484 059c 6700
001a
00485 05aO 41ta
098b
00486 05a4 303c
0001
00487 05a8 223c

move. 1

'0.BD_cmd(a6)

move.b

Drive_no(a6).dO

or.b

dO. BD-psn (a6)

move.b

'$01.HD_cmd(a6) Recalibrate cmd

lea

HD_cmd(a6).a1

cmd ptr

lIOVe.w

'6.dl

get count

bsr

NCRcmd

bcs.s
lea

test8ex
RD_status(a6).a3

bsr

NCRstatus

lea

RD_asg(a6) .a3

bsr

NCRmsg

btst

'1.HD_status(a6)

beq

test81

lea

emsglO(pc).aO

move .•

IStdOut.dO

move. 1

hzemsg10.dl

clr psn

skip if no error

13

Microware OS-9/68000 Resident Macro Asaembler VI.5 86/01/23 17:47 Page
tatacaL.
tatncr - OS-9/68000 CC-74 Teat Routinea
0000001d
00488 05. . -4e40
oa9
I$Write
wri te error meaaa,le
0000
00489 05b2 6100
0270

bar

.en.t.t

00490 05b6 4875 teat8ex

rt.
lea

ID8g3(pc).aO

.ove.w

'StdOut.dO

move. I

'azmBg3.dl

089

I$Write

00491 05b8 41fa test81
0769
00(92 05bc 303c
0001
00493 05cO 223c
00000027
00494 05c6-4e40
0000
00495 05ca 4e75

II

rtB

00496 •
00497 • exit routine test9
00498 •
00499 000005cc Test9
00500 OScc 08ad
00030101
00501 OSd2 4281
00502 05d4-4e40
0000
00503

equ

•

bclr

'3.CONTROL74 (as) disable irq

clr.l
os9

dl
F$Exit

return to os9

00504 •
00505 * Init74:
00506 •
00507 • Following is the Initialise routine
00508 •
00509 * The NCR chip and the SCSI bus are reset
00510 •
00511 • entry: as z base address of CC-74
a6 * static storage pointer
00512 •
carry set on error
00513 • exit
NCR diagnostic register in d3
00514 •
00515 *
00516 05d8 08ed InU74:
00070101
00517 05de 08ad
00070101
00518 05e4 1b7c
00000123
00519 05ea 203c
000001Se
00520 05fO 51c8 lnit741
0004
00521 05f4 6046
00522 05f6 082d InU744
00070133
00523 05fc 67f2
00524 OSfe 162d
0133
00525 0602 b63c
0080
00526 0606 6634
00527 0608 41fa
049a

14

bset

'7.CONTROL74(a5) Reset SCSI bus

bclr

'7.CONTROL74 (as) clr reset bit

move.b

'0.COMNCR(a5)

NCR chip reset

move. 1

'350.dO

Init timout

dbra

dO.lnU744

Time out?

bra.s
btst

Init742
yes
'7.DIAGNCR(a5) wait for command

beq.s
move.b

InU741
DIAGNCR(a5) .d3 get diagnostic results

cmp.b

'$80.d3

bne.s
lea

Init742
lrqEntry(pc).aO

00528 060c 23c8
00000200

move. I

aO.$200

00529 0612 Ib7c

IDOve.b

'0.DESIDNCR(a5) Bet default target id

r.~ady

Microware OS-9/68000 Resident Macro Assembler V1.5

•

86/01/23

17:47

Page

15

tstscsi .•
tatncr - OS-9/68000 CC-74 T.st Routin.s
00000127
.ove.b
'0.Drive_Do(a6) set default drive nr.
00530 0618 1d7c

•

00000116
00531 061e 1d7c

..

~

•

aove.b

'$c5.HD_ctrl(a6) init control field. retries and step-ra

00532 0624 1d7c
0001000e

aove.b

'1.RD_blk(a6)

00533 062a 1b7c
00360101
00534 0630 08ed
00030101
00535 0636 023c
OOfe
·00536 063a 4e75
00537
00538 063c 003c Init142
0001
00539 0640 4e75
00540
00541

aove.b

'$36. CONTROL 74 (a5) set bus request level 3. irq level 6

bset

'3.CONTROL74 (a5) enable irq

andi.b

I$fe.ccr

clear carry no error

'l.ccr

set carry, error occured

t.
00c5000f

•

•

•

.
.
.
.
..

.
III

III
-~

III

..
..

init block count. always one block

rts
ori.b
rts

00542 •
00543 • start of subroutines
00544 •
00545 • NCRcmd : give the NCR5385 a command
00546 • entry : a1 cmd pointer
as base address CC14
00547 •
a6 static storage
00548 •
dl byte count (word)
00549 •
00550 •
00551 0642 3fOl NCRcmd:
aove.w
dl.-(sp)
save byte count
00552 0644 422d
clr.b
TFRNCR(a5)
0139
clr.b
TFRNCR+2(a5)
00553 0648 422d
013b
00554 064c Ib1c
aove.b
l$ff.TFRNCR+4(a5) arbitration time out
00ff013d
bsr
Testlrq
is there an interrupt pending
00555 0652 6100 ncmdO
0246
bne.s
ncmdO
yes reset by reading irq again
00556 0656 66fa
00551
ncmdl
00558.
move.b 1$04.COMNCR(a5) 'Soft reset ??'
00559 0658 Ib1c
aove.b
'$09,COMNCR(a5) select XEBEC
00090123
00560 065e 6100
0244
00561 0662 OcOl
0001
00562 0666 610c
00563 0668 OcOl
0004
00564 066c 6100
003a
00565 0610 6000
0050
00566 0614 6100 ncmdc
022e
00561 0618 32lf
00568 061a 1b41
013d
6100 ncmd2
061e
00569
021a

bsr

Waitlrq

bit #0 'function complete' should be set

cmpi.b

Il.dl

beq.s
cmpi.b

ncmdc
l4.dl

'function complete' was set

beq

Timouterr

'disconnected set' no response

bra

Invalirq

'some bit set'

bsr

WaitIrq

bit #1 'bus service' should be set

move.w
move.b

(sp)+.dl
restore byte count
d1.TFRNCR+4(aS) init transfer count

bsr

Testlrq

is there an interrupt pending

Microware OS-9/68000 Resident Macro A.s . .bIer Vl.S 86/01/23 17:47 Page
16
tstscai .•
tstncr - OS-9/68000 CC-74 Test Routine.
00570 0682 66f.
bne.s
nc.d2
yes reset by reading irq again
00571 0684 Ib7c
.ove.b
'$14.COMNCR{.5) tr.nsfer info cm~
00HOll3
00572 068a 102d nc.d3
.ove.b
AUXNCR(.5).dO
0129
00573 068. 0800

btat

'7.dO

bne.s
btst

.1.

ncmd3
dO

wait for data reg full _ 0

bne.s
move.b
move.b

ncmd4
(al)+.dO
dO.DATNCR(a5)

transfer count ze.r01
no. do another byte

bra.s
move.w

ncmd3
'O.dO

0007
00574 0692 66f6

00575 0694 0800
0001
00576 0698 6608
00577 069a 1019

00578 069c lMO
0121
00579 06aO 60e8
00580 06a2 303c ncmd4
0000
00581 06a6 4e75
00582
00583
Timouterr:
00584 06a8 41fa
08f8
00585 06ac 303c

rts

lea

emsg14(pc).aO

move.w

'StdOut.dO

00586 06bO 223c

move. I

Iszemsg14.d1

0000001a
00587 06b6-4e40

os9

I$Write

00588 06ba 321f
00589 06bc-003c

move.w
ori.b

(sp)+.d1
,earry.ccr

0000
00590 06cO 4e75

rts

0001

0000

restore byte coun'c

00591
00592

Invalirq:

00593 06c2 41fa

08f8
00594 06c6 303c
0001
00595 06ca 223c

lea

emsg15(pc).aO

move.w

'StdOut.dO

move. I

.szemsg15.d1

move.w
os9

(sp)+.dl
I$Write

ori.b

.earry.ccr

c

00000025

00596 06dO 321f
00597 06d2=4e40
0000
00598 06d6=003c
0000
00599 06da 4e75
00600 ..
00601 .. NCRstatus
00602 .. entry : a3
00603 ..
as
00604 ..
a6

restore byte coun't

rts
get status byte
status ptr
base address
static storage

00605 ..

00606 06dc 1b7c NCRstatus: move.b
'l,TFRNCR+4(a5) transfer count i:~ 1
0001013d
00607
Nstatus1
00608 .. bsr TestIrq Is there an interrupt
00609 06e2 1b7c
move.b
'$14.eOMNCR(a5) transfer info cmd
00140123
00610 06e8 6100
bsr
TestIrq
Is there an inter:rupt
01bO
00611 06ec 0800
btst
'7.dO
test if data full ncr

•

•
•

•
•
:~

•
•

•

•

..
•

.
..
..

..
.."l

Microware 05-9/68000 Resident Macro A. .embler Vl.5

86/01/23

17:41

Page

17

tatacai.a
tatncr - 05-9/68000 CC-74 Teat Routinea
0007
00612 06fO 67fO

beq.a

Nat.tua1

00613 06f2 102d

.ove.b

DATNCR(a5).dO

.ove.b

dO. (a3)

0121
00614 06f6 1680
00615 06f8 4e75
00616

No dsta received

rta

00617 •
00618 • NCRmsg : get message byte
00619 • entry : a3 mesaage ptr
as base address
00620 •
a6 atatic storage
00621 •
00622 •
00623 06fa Ib7c NCRmsg:
move.b
'1.TFRNCR+4(a5) transfer count is 1
0001013d
00624
NCRmsgl
00625 0700 102d
move.b
COMNGR(a5).dO test if command register is 00
0123
00626 0704 6706
beq.s
NCRmsg2
00627 0706 Ib7c
move.b
'$04.COMNCR(a5) message accepted cmd
00040123
00628
NCRmsg2
00629 • bar TestIrq Ia there an interrupt
00630 070c 1b7c
move.b
'$14.COMNCR(a5) transfer info cmd
00140123
00631 0712 6100
bar
Is there an interrupt
TestIrq
0186
00632 0716 0800
btat
test if data full ncr
'7.dO
0007
00633 071a 67e4
No data received. try to give command aga
beq.a
NCRmsg1
in
00634 071c 102d
move.b
DATNCR(a5).dO
0121
00635 0720 1680
move.b
dO. (a3)
00636 0722 1b7c
move.b
'$04.COMNCR(a5) message accepted cmd
00040123
00637
NCRmsg3
00638 0728 6100
bsr
Wait Irq
SCSI should be disconnected
017a
00639 072c Oc01
0004
00640 0730 66f6
00641 0732 4e75
00642

cmpi.b

'4.dl

bne.s
rts

NCRmsg3

Irq not from disconnect

00643 •
00644 • NCRdatrd : get data bytes
00645 • entry : a2 data pointer
a5 base address
00646 •
a6 static storage
00647 *
d2.w count
00648 *
00649 *
00650 0734 3602 NCRdatrd:
00651 0736 1M2
013d
00652 073a e04a
00653 073c 1M2
013b
00654 0740 3b7c
0000004a
00655 0746 1b7c
00e10004
00656 074c 1b7c

move.w
move.b

save for later
d2.d3
d2.TFRNCR+4(a5) least sign. byte transfer count

lsr.w
move.b

'8.d2
most sign. byte
d2.TFRNCR+2(a5) store it

move.w

'$00.EscFlg(a5) clear escflag

move.b

'(StealHld+DevAck+Dev8Bit+StatlnpI).DCR+CHNLO(a5)

move.b

'(DevTOMem+ByteSize+ChainDis+Reqlnit).OCR+CHNLO(a5)

Nicroware OS-9/68000 Reaident Macro Aaa . .bler Vl.S

86/01/23

17:47

Page

18

tat.caL.
tatncr - OS-9/68000 CC-74 Teat Routinea
00820005
00657 0752 1b7c

IIOve. b

• (MemCntUp+DevNoCnt) • SCR+CHNLO (as,)

00040006
00658 0758 Ib7c
00800025

IIOve.b

'$80.NIV+CHNLO{a5) Uaer vector $eO

00659 075e 1b7c

IIOve.b

'$80.EIV+CHNLO(aS) Uaer vector $81

~

00800027
00660 0764 1b7c

. move.b

'UaerData.DFC+CHNLO(aS)

•

move.b

'UserData.MFC+CHNLO(aS)

II

move.b

'ChPriorO.CPR+CHNLO(aS)

move.b

'$ff. CSR+CHNLO (as) clear all bits

move.l

a2.MAR+CHNLO(aS)

move. I

I(CC74_BASE+DATNCR).DAR+CHNLO(aS)

move.w

d3.MTC+CHNLO(aS)

move.b

I(StartOp+lntrptEn).CHCR+CHNLO(aSI don't start. enable i

bsr

TestIrq

move.b

I$94.COMNCR(aS) give command. irq occurs

btst

lOpComp_B.CSR+CHNLO(aS) operation completed

00010031
00661 076a 1b7c

I

00010029
00662 0770 1b7c

I

III

0000002d
00663 0776 1b7c
OOffOOOO
00664 077c 2b4a
OOOc
00665 0780 2b7c
00ffff21
0014
00666 0788 3M3
OOOa
00667 078c 1b7c
rq
00880007
00668 0792 6100

read irq

0106
00669 0796 1b7c
00940123
00670 079c 082d datrdl
00070000
00671 01a2 6606
00612 07a4 302d

bne.s

datrd2

yes. branch

move.w

EscFIg(aS).dO

set in Irq routine if no data phase occur

ed

.
c
I

004a
00673 07a8 67f2
00614 07aa 4e7S datrd2
00675
00676 it

beq.s

datrdl

no error

move.w

d2.d3

save for later

move.b

d2.TFRNCR+4(aS) least sign. byte transfer count

00686 01b4 1M2

lsr.w
move.b

f8.d2
most sign. byte
d2.TFRNCR+2(aS) store it

013b
00681 01b8 3b7c

move.w

f$OO.EscFlg(aS} clear escflag

00688 07be 1b7c
00e10004

move.b

I(SteaIHld+DevAck+Dev8Bit+StatInpl).DCR+CHNLO(a5)

00689 07c4 1b7c
00020005

move.b

I(MemToDev+ByteSize+ChainDis+Reqln.it).OCR+CHNLO(a5}

00690 07ca 1b7c
00040006

move.b

I(MemCntUp+DevNoCnt).SCR+CHNLO(a5)

00691 07dO 1b7c
00800025

move.b

1$80.NIV+CHNLO(a5) User vector $80

00692 07d6 1b7c
00800027

move.b

f$80.EIV+CHNLO(aS) User vector $81

00677
00678

it

00619

it

it

rts

NCRdatwr : send data bytes
entry : a2 data pointer
as base address

00680

it

a6 static storage

00681

it

d2.w count

00682

it

00683 07ac 3602 NCRdatwr:
00684 07ae 1M2
Ol3d
00685 07b2 e04a

0000004a

!

I

II

II

•
•
•

•
•

•

19
Microware 0$-9/68000 Reaident Macro Aaa . .bler Vl.S 86/01/23 17:47 Page
tatacai .•
tatncr - OS-9/68000 CC-74 T.at Routine.
00693 07dc Ib7c
.av•. b
'Ua.rD.ta.DFC+CHNLO(.S)
00010031
00694 07.2 Ib7c
.av•. b
'Ua.rData. MFC+CHNLO (as)
00010029
.ave.b
'ChPriorO.CPR+CHNLO(aS)
00695 07e8 Ib7c
0000002d
.ave.b
'$ff.CSR+CHNLO(aS) clear all bit.
00696 07ee Ib7c
OOffOOOO
.ave. 1
a2.MAR+CHNLO(a5)
00697 07f4 2b4a
OOOc
.ave. 1
f(CC74_BASE+DATNCR).DAR+CHHLO(aS)
00698 07f8 2b7c
00ffff21
0014
.ave.w
d3.MTC+CHNLO(aS)
00699 0800 3b43
OOOa
move.b
I(StartOp+IntrptEn).CHCR+CHHLO(aS) don't start. enable i
00700 0804 Ib7c
rq
00880007
bsr
00701 080a 6100
TestIrq
read irq
008e
00702 080e lb7c
.ave.b
'$94.COMNCR(aS) give command. irq occurs
00940123
btst
lOpComp_B.CSR+CHHLO(a5) operation completed
00703 0814 082d datwrl
00070000
00704 081a 6606
bne.s
datwr2
yes. branch
00705 081c 302d
mave.w
EscFlg(aS).dO set in Irq routine if no data phase occur
ed
004a
beq.s
00706 0820 67f2
datwrl
no error
00707 0822 4e7S datwr2
rts
00708
00709
00710 •
00711 • Sense Status command

III

..

Should be called if another command returns with an error
00712 •
00713 • Entry: as base address
a6 static storage
00714 •
00715 •
00716 0824 Id7c senstat:
0003000a
00717 082a 022e
OOlfOOOb
00718 0830 43ee
OOOa
00719 0834 323c

IIOve.b

1$03. BD_ cmd ( a6 ) Set command byte

andi.b

1$1f .BD.....Psn(a6) clear drive bit

lea

BD_cmd(a6).al

IIOve.w

l6.dl

bsr

HCRcmd

bcs.s
IIOve.w

sens2
'4.d2

lea

BD_sense(a6).a2

bsr

HCRdatrd

lea

BD_status(a6).a3

bsr

HCRstatuB

lea

BD_msg(a6) .a3

bsr

HCRmsg

0006

00720 0838 6100
fe08
00721 083c 6SSa
00722 083e 343c
0004
00723 0842 45ee
0112
00724 0846 6100
feec
00725 084a 47ee
0010
00726 084e 6100
fe8c
00727 0852 47ee
0011
00728 0856 6100

fea2

Execute command

IUcroware OS-9/68000 Resident Macro A. . .bler Vl..5

86/01/23

17:47

Page

20

tataca1..
tatncr - OS-9/68000 CC-74 Teat Routinea
00729 085a 082e
btat
11.BD_atatua(a6)
00010010
00730 0860 6624
00731 0862 4Ha
057c
00732 0866 303c
0001
00733 086a 223c
00000021
00734 0870-4e40
0000
00735 0874 222e
0112
00736 0878 303c
0001
00737 087c 41ee
0000
00738 0880 6100
Olea
00739 0884 6012
00740 0886 41fa sensl
06c2
00741 088a 303c
0001
00742 088e 223c
0000001e
00743 0894-4e40
0000
00744 0898 4e75 sens2
00745
00746
00747

lea

aenal
_gO(pc) .aO

move. v

IStdOUt.dO

move.l

lazemagO.dl

oa9

I$Write

move. 1

BD_aense(a6).dl

move."

IStdOut.dO

lea

Char_Buf(a6).aO

bsr

OUthex

bra.a
lea

aena2
emsgll(pc) .aO

move."

fStdOUt.dO

move. 1

fszemsgl1. dl

os9

I$Write

*
*
*
*
*

•

atart of "Error cI:>de"

rts

/l1li

*

I

* TestIrq
00748 *
00749 089a 102d TestIrq:
0129
00750 08ge 122d
012d
00751 08a2 4e75
00752
00753
00754

bne.a

r

move.b

AUXNCR(aS).dO

get auxiliary register NCR

move.b

IRQNCR(a5).dl

get interrup register NCR

rts

c

WaitIrq

00755
Poll IRQ line NCR chip via DMA controller
00756
00757
00758 08a4 102d WaitIrq:
move.b
CSR(a5).dO
0000
00759 08a8 0800
btst
fO.dO
0000
bne.s
WaitIrq
00760 08ac 66f6
00761 08ae 102d
move.b
AUXNCR(a5) .dO
0129
move.b
IRQNCR(a5).d1
00762 08b2 122d
012d
rts
00763 08b6 4e75
00764 *
00765 * AskCon
00766 *
Ask for the fill constant
00767 * Input : none
00768 * Exit : dO.l fill constant
00769 *
Carry clr if no error
00770 08b8 41fa AskCon:
lea
msg6(pc).aO

..
,

get status registE,r dina channel 0
irq NCR occurred
no. try again
get auxiliary register NCR

III

c

get interrup register NCR

c

•
~

•
~

•
'i

I

Mierow.re 09-9/68000 Reaident Macro Aa . . .bler V1.5
tataeai .•

86/01/23

17:41

Page

tatner - OS-9/68000 CC-14 Te.t Routine.
04b.
00111 08be 303e
IIOve .•
'StdOut,dO
0001
00112 08eO 223e
IIOve.l
'az_g6,dl
00000021
00113 08e6-4e40
0000
00114 08e. 303e

oa9

I$Write

IIOve.w

.StdIn.dO

IIOveq

19.dl

lea

Char_But(a6).aO

0000
00111 08d4 6100

b.r

Inhex

0106
00118 08d8 6400

bee

askeonl

001a
00119 08de Uta

lea

emsg13(pe).aO

IIOve.w

'StdOut.dO

IIIOve.l

.szemsg13.dl

os9

I$Write

ori.b

'l.eer

Print 'give con'

0000
l

I

II
.~

..

00115 08ee 1209
00116 08dO Uee

06a2
00180 08eO 303e
0001

•
-"

.
..
..
~

If

.
-.'l

~l

III

..

- ~

II

..
4

"

•
-'i

l1li
..

- ~

00181 08e4 223e
00000022
00182 08ea-4e40
00183 08ee 003e
0001
00184 08f2 4e15

rts

00185 08t4 023e askeon1

andi.b

OOfe
00186 08f8 4e15

rts

00181
00788

'$te.eer

*
*
*

Askid
00789
00790 08fa 41fa Askid:

lea

msg8(pe) .aO

04ad
00791 08fe 303e

IDOve.w

'StdOut.dO

0001
00792 0902 223e

IDOve.1

Iszmsg8.dl

0000001a
00793 0908=4e40

os9

I$Write

00794 090e 303e

IIOve.w

'StdIn.dO

0000
00795 0910 1202

IIOveq

00796 0912 41ee

lea

'2.dl
Char_Buf(a6).aO

0000
00797 0916=4e40

os9

I$ReadLn

0000
00798 091a 6516
00799 09le 102e

bes.s

Askid3

IDOve. b

Char_Buf(a6).dO

0000
00800 0920 0400

subi.b

1$30.dO

bes.s

Askid3

cmpi.b

1$07.dO

'ii!

0007
00803 092a 6206
00804 092e 1b40

bhi.s
move.b

Askid3

.
"'iii

get idnr

0030
00801 0924 650e
00802 0926 OeOO

,--.-

Print 'give target id'

0000

l1li

II1II

Print error message

0000

dO.DESIDNCR(a5)

0127
00805 0930 4e75
00806 0932 41£a Askid3

rts
lea

emsg16(pe).aO

negative result (0

21

Mieroware 05-9/68000 Reaident Maero Asaembler Vl.S
tat.ca1..
t.tner - OS-9/68000 CC-74 Te.t Routine.
06ad
00807 0936 303e
.ave.w
'StdOut.dO
0001
00808 093. ll3e
000000Ie
00809 0940-4 . . 0
0000
00810 0944 4e7S

.ave.l

•• zemagl6.dl

0.9

I$Write

86/01/23

17:47

Page

22

rt.

00811 •
00812 • Ask Drive no
00813 •
00814 0946 Ufa Aakdn:
047b
00815 094a 303e
0001
00816 094e 223e
0000001d
00817 0954.4e40
0000
00818 0958 303e
0000
00819 095e 7202
00820 095e 41ee
0000
00821 0962-4e40
0000
00822 0966 6518
00823 0968 102e
0000
00824 096e 0400
0030
00825 0970 650e
00826 0972 OcOO
0001
00827 0976 6208
00828 0978 eb08
00829 097a Id40
0116
00830 097e 4e75
00831 0980 41fa Askdn3
067d
00832 0984 303c
0001
00833 0988 223c
00000021

lea

msg9(pe).aO

.ave.w

'StdOut.dO

move.l

.azmag9.dl

os9

I$Write

move.w

'StdIn.dO

moveq
lea

'2.d1
Char_Buf(a6).aO

os9

I$ReadLn

bes.s
move.b

Askdn3
Char_Buf(a6) ,dO

subi.b

I$30.dO

bes.s
cmpLb

Askdn3

bhLs
l.sl..b

Askdn3

Print 'give drive llumber: '

get drivenr

negative result <0

'$01. dO

move.b

'5.dO
dO. Drive_no(a6)

rts
lea

emsg17(pc).aO

move.w

IStdOut.dO

move.l.

Iszemsgl7. d1

00834 098e=4e40
os9
I$Write
0000
00835 0992 4e75
rts
00836 ..
00837 .. AskPsn
00838 ..
Ask for the Physical Sector number
00839 .. Input : none
00840 .. Exit : _dO.l OOOxxxxxx.xxxxxxxx.xxxxxxxx.xxxxxxxx PSN
00841 ..
Carry clr if no error
00842 0994 41fa AskPsn:
lea
msg5(pc).aO
03bd
move.w
IStdOut.dO
00843 0998 303c
0001
move.l.
IszmsgS.dl
00844 099c 223c
00000021
I$Write
os9
Print 'give psn'
00845 09a2-4e40

c

N1erowar. OS-9/68000 Reaident Macro Aaa . .bler Vl.S

86/01/23

17:47

Page

23

tataeai .•
tatner - OS-9/68000 CC-74 T.at Routin.a
0000
00846 09.6 303e

IIOV •• "

'Stdln.dO
'9.dl

0000
00847 09 •• 7209

IIOveq

III

00848 09.e 41.e

1 ••

.

00849 09bO 6100

0000
bar

Inhex

bce

aakpan1

lea

emsg12(pc).aO

00852 09be 303e

DIOve.w

'StdOut.dO

0001
00853 0geO 223e

move. 1

lazemsg12.d1

.

00854 09c6-4e40
0000

os9

I$Write

ori.b

'l,ccr

..

00855 09ca 003c
0001
00856 09ce 4e7S

rts
andi.l

'$Hffff.dO

andi.b

'$fe.cer

002a
00850 09b4 6400
001a
00851 09b8 Uf.

III

OS.e

III

00000018

00857 09dO 0280 askpsn1
OOlfffff
00858 09d6 023c

III

Print error message

clear drive nr

OOfe
00859 09da 4e75
00860
00861
00862
00863

.
.

00864
00865
00866
00867

rts

*
*
*

Following are the special hex input and output routines not found in 059

*
*
*

lnhex:

*

input

00868
00869

*
*

00870

*

00871

*

dO.w path number
dl.l max number of bytes to read inclusief 
(aO) start address of input buffer

exit

: dO.1 hex long word padded with zero's
earry set on error

00872 *
00873 09de 48e7 lnhex:
0040

IIOvem.l

al.-(sp)

save used registers

00874 0geO=4e40
0000
00875 0ge4 6402

os9

I$ReadLn

get ascii string

bee.s

lnhexl

see if error

III

00876 0ge6 603e
00877 0ge8 2248 lnhexl

bra.s

Inhex5
aO.a1

yes, leave routine with carry set

.

00878 0gea 5381

.l,dl

00879 0gee d3e1

subi.l
add.l

dl.al

discard 
a1 ptr to end buffer

00880 0gee 4281

clr.l

00881 09fO Oe10 Inhex2

cmpi.b

dl
Ispace.(aO)

set hex output to zero
skip leading zero's

Inhex3

was it space
bump input pointer

"I
i

III

..
•

move. 1

aO ptr to start buffer

0020
00882 09f4 6608
00883 09f6 5288
00884 09f8 b3c8

bne.s
addq.l
cmpa.l

00885 09fa 671e

beq.s

00886 09fe 60f2
00887 09fe 1010 Inhex3

bra.s
move.b

00888 OaOO 6100
002e

bsr

00889 Oa04 651e

bcs.s

InhexS

error occured if set

00890 Oa06 e989

Isl.l

'4.dl

shift d1 for next nibble

l1.aO
aO,a1

last?

Inhex4
Inhex2

yes. leave
get next

(aO).dO

we got some character

Asehex

convert ascii to hex

Microware 05-9/68000 Resident Macro Asaembler Vl.5

86/01/23

17:47

J'age

24

tatacai .•
tatncr - 05-9/68000 CC-74 T.st Routinea
00891 0.08 cOb<:
and.l
',Ot.dO

mask to be aure

OOOOOOOf
00892 O.Oe 4280

add.l

dO.dl

aet loweat nibble

00893 0.10 5288

addq.l

l1.aO

bump pointer

00894 Oal2 b3c8

aspa.l

aO.al

laat?

00895 0.14 6702

beq.a

Inhex4

00896 Oal6 60e6

bra.a

Inhex3

yea. leave
get next

00897 Oa18 200} Inhex4
00898 OaIa 4edf

move. 1
lIOVem.l

dl.dO
(ap)+.al

leave with no error

00899 Oale 023c

andi.b

'$fe.ccr

OOfe
00900 Oa22 4e75

rts

0200

00901 Oa24 2001 Inhex5
00902 0826 4edf
0200
00903 Oa2a 003c
0001
00904 Oa2e 4e75
00905
00906

move. 1
movem.l

dl.dO
(_p)+.al

ori.b

.Lccr

leave with error

rts

*

*
*
*

Aschex:

00907
00908
00909

*

exit

00910

*
*

input

dO ascii character
dO converted to hex if no error
carry set if error

00911
00912 Oa30 2fOO Aschex:
00913 Oa32 b03c
0061
00914 Oa36 6dOa
00915 Oa38 b03e

move.l

dO.-(sp)

save for a while

cmp.b

"a' .dO

check for lower calse

blt.s
cmp.b

Aschexl

~

" f ' .dO

I

III

0066
00916 Oa3e 6204

bhLs

Aschex1

00917 Oa3e 0200

andi.b

#$df.dO

was lower case. ma:lte upper case

OOdf
00918 Oa42 0400 Aschex1

subi.b

1S30.dO

first step to hex 'lTalue

00919 Oa46 651c
00920 Oa48 OcOO
0009

bcs .•
cmpi.b

Aschex3

negative result. i,s not numerical hex

00921 Oa4c 630e
00922 Oa4e OcOO

bls.s
cmpi.b

Aschexl

0011
00923 Oa52 6510

bcs.s

Aschex3

00924 Oa54 OeOO

cmpLb

'$16.dO

00925 Oa58 620a

bhLs

Aschex3

00926 Oa5a Sf00
00927 Oa5e 588f Aschex2

subi.b

1$7.dO

addq.l

lt4.sp

00928 Oa5e 023c
OOfe
00929 Oa62 4e75
00930 Oa64 201f Aschex3

andi.b

'$fe.ccr

discard saved dO on stack
no error. clear carry

rts
move.l

(sp)+.dO

get original character

00931 Oa66 003c
0001

ori.b

'Lccr

error. not hex. set carry

00932 Oa6a 4e75

rts

0030
'$09.dO
test if in range 0-9

'$lLdO
test if >9 en (A

0016

00933
00934
00935
00936
00937

*
*
*

Outhex

*
*

input: dO.w path number
(aO) start address of buffer

test if in range A-F

""
I

.

Microware 05-9/68000 Reaident Macro Aaa . .bler V1.5

86/01/23

11:41

Page

25

tatacai .•
tatncr - 05-9/68000 CC-14 Teat Routinea
00938 •

II

dl

long word to output
number of by tea written

00939 • exit : d1
00940 •

carry .et if error

00941 •
00942 Oa6c 48e1 Outhex:

•

movem.l

d2/d3.-(ap)

aave uaed regiaters

00943 Oa10 5e88

addq.l

'7.aO

set to end of buffer to write

00944 Oa12 243c
00000001

move. I

'1.d2

set loop count is eigth

00945 Oa18 2601 Outhex1

move. I

dl.d3

use d3 as scratch

00946 Oa1a e889

lar.l

14.41

get nibble for next loop in position

00941 Oa1c 0203

andi.b

'$f.d3

mask lowes nibble

OOOf
00948 Oa80 d63c

add.b

'$30.d3

get to range 0-9

00949 Oa84 b63c
0039

cmp.b

'$39.d3

is i t higher

00950 Oa88 6304
00951 Oa8a d63c
0001

bls.s

Outhex2

no

add.b

'7.dJ

get to range A-F

00952 Oa8e 1103 Outhex2

move.b

dJ.-(aO)

store byte in write buffer

00953 Oa90 SIca

dbra

d2.0uthex1

get next until all eigth done

move.l

'$8.41

number of bytes

00955 Oa9a-4e40

os9

I$Write

aO set to start

0000
00956 Oage 4cdf

movem.l

(sp)+.d2/d3

OOOc
00951 Oaa2 4e15

rts

3000

-~

•

•
•

0030

•
11
I

If

ffe6
00954 Oa94 223c
00000008

III

00958
00959
00960
00961

•
•

•
• Irq routine
• This routine becomes enabled in the NCRdatrd and NCRdatwr
• It checks the NCR chip for the 'Bus Phase' and initiate

00962 • the 'Transfer Info command' until the bus phase is the
00963 • data phase. Then the DMA is enabled and we wait for the
00964 •

•

'status phase'

00965 •
00966 Oaa4 48e7 IrqEntry:
f8fc
00961 Oaa8 2a7c

III

dO-d4/aO-a5.-(sp) save registers

movea.J.

'CC74_BASE.a5

btst

'3.CONTROL74 (a5)

OOHfeOO
00968 Oaae 082d
00030101

III

movem.l

00969 OaM 6710

beq.s

irqenO

00970 Oab6 102d

move.b

CHNLO+CSR(a5).dO

btst

1000omp_B.dO

bne.s
btst

irqen3

beq.s

irqen1

movem.l

(sp)+.dO-d4/aO-a5

00977 Oaca 4879
q's
00000200

pea.l

$200

00978 OadO 4ef9
00083230

jmp

$83230

0000

III

00971 Oaba 0800
0007
00972 Oabe 6676
00973 OacO 0800

III

00974 Oac4 6710

Irq from dma pcl line occured

irqenO

00975

III

IPCLSts_B.dO

0000

00976 Oac6 4cdf
3Uf

III

III
:"l

00979

irqenl

do the same as os9 does for unexpected ir

26
Micro-are 09-9/68000 Resident Macro Aas. .bler Vl.S 86/01/23 17:47 Page
tataeai.a
tatner - 05-9/68000 CC-14 Teat Routinea
00980 Oad6 08ad
belr
13.CONTROL74(aS) toggle ENlRO
00030101
.ove.b
l$rf.CRNLO+CSR(aS) clear interrupt cauae
00981 Oade lb7e
oorroooo
.ove.b
AUlNCR(aS).dO
00982 Oae2 102d
0129
IIOve. b
lRQNCR(aS) • dl
00983 Oae6 122d
012d
00984 Oaea 08ed
baet
13.CONTROL74 (as)
00030101
IIOve.b
dO.d3
00985 Oaro 1600
00986 Oaf2 e18b
la1.1
'8.d3
00987 Oaf4 d600
add.b
dO.d3
move .•
00988 Oaf6 3M3
d3.SavSta(aS)
004e
mask off msg. c/d and i/o line
andi.b
00989 Oafa 0200
'$38.dO
0038
cmp.b
test Data Out phase
00990 Oafe b03c
'$00. dO
0000
beq.s
00991 Ob02 6718
irqen2
cmp.b
test Data In phase
00992 Ob04 b03e
'$08.dO
0008

beq.s
cmp.b

irqen2
I$18.dO

beq.s
RIOve.b

irqen3
'$94.COMNCR(aS) give transfer info command. dma

00997 Ob16 4cdf

movem.l

(sp)+.dO-d4/aO-a5

3f1f
00998 Obla 4e73
00999 Oblc Ib7c irqen2

rte
RIOve.b

'$94.COMNCR(aS) give transfer info command. dma

01000 Ob22 082d
00030000

btst

'Active_B.CHNLO+CSR(aS) test if c.nannel already started

01001 Ob28 6606
01002 Ob2a 08ed

bne.s
bset

irqen4
yes. started
'Start_B.CHNLO+CBCR(aS) enable dma controller

RIOvem.1

(sp)+.dO-d4/aO-aS

rte
RIOve.b

I(StealBld+DevAck+Dev8Bit+StatInp).CHNLO+DCR(aS)

00993 Ob08 6712
00994 ObOa bOle

test Status phase

0018

00995 ObOe 6726
00996 Obl0 Ib7e
00940123

00940123

00070007
01003 Ob30 4cdf irqen4

3flf
01004 Ob34 4e73
01005 Ob36 Ib7c irqen3
00e00004
01006 Ob3c 08ad

bclr

00030007
01007 OM2 1b7c

00ff004a
01008 OM8 4cdf
3f1f
01009 OMc 4e73
01010 *
01011 * parameter table
01012 *
BD-par85
01013
01
01014 OMe
b8
01015 OMf
06
01016 Ob50
00
01017 ObSl
10
01018 ObS2
00
01019 Ob53
80
01020 ObS4

move.b

'$ff.EscFlg(aS)

RIOvem.1

(sp)+.dO-d4/aO-aS

rte

dc .. b
dc.b
dc.b
dc.b
dc.b
dc.b
dc.b

$01
$B8
$06
$00
$10
$00
$80

I

Microw.re 09-9/68000 Reaident Macro Aaaembler Vl.S
tatacat.a
tatncr - 09-9/68000 CC-74 T.at Routinea
dc.b
01021 ObSS
Ob
SOB
01022
01023
RDJlar88
01024 ObS6
dc.b
$02
02
dc.b
01025 ObS7
64
$64
01026 ObS8
04
dc.b
$04
01027 ObS9
02
dc.b
$02
01028 ObS.
64
dc.b
$64
Oi029 ObSb
00
dc.b
$00
01030 ObSc
dc.b
80
$80
01031 ObSd
Ob
dc.b
SOB
01032
01033

"
•
'l

.~

I
~

II

-.

•

86/01/23

17:47

Pave

27

~.j

•
"i

•
~

•
.~

•

,..
I

"'I

..

.
.~

-~J

•
~

II
.~

II
\~

II

01034
. 01035
01036
01037
01038
01039

•
• lies sages
•
ObSe OdOa IIsgl
Ob60 OdOa
Ob62 5465
7374696e
67204343
2d373420
6d6f6475
6c652077
69746820
4e43S235
33383520
616e6420
58454245
43205331
34313041
01040 Ob94 OdOa
01041 Ob96 OdOa
01042 Ob98 2020
20202031
203a2069
6e697469
616c697a
6S20636f
6e74726f
6c6c6S72
20616e64
20647269
7665
01043 ObcO OdOa
01044 Obc2 2020
20202032
203a2074

dc.b
dc.b
dc.b

CR.LF
CR.LF
"Testing CC-74 module with HCRS385 and XEBEC S1410A"

dc.b
dc.b
dc.b

CR.LF
CR.LF

dc.b
dc.b

CR.LF

dc.b
dc.b

CR.LF

dc.b
dc.b

CR.LF

1

initialize controller and drive"

2

test drive ready"

3

format drive"

4

drive diagnostic"

65737420
:;11

.l

.-

01045 Obdb
01046 Obdd

'11

III
.~

III
:"-'1

01047 Obf2
01048 Ob!4

64726976
65207265
616479
OdOa
2020
20202033
203a2066
6!726d61
74206472
697665
OdOa
2020

Microware OS-9/68000 Resident Macro Assembler V1.5
tatscsi ••

86/01/23

17:47

:Page

tatncr - OS-9/68000 CC-74 Teat Routinea
20202034

28

r
I

~

~

I

II

20382064
72697665

•~

20646961
676e6t73
746963
01049 OcOd OdOa
01050 OcOf 2020

dc.b

CR.LF

dc.b

~

5

read one aector"

20202035
203a2072

II

..

65616420
6f6e6520
73656374
6f72
01051 Oc27 OdOa
01052 Oc29 2020

dc.b
dc.b

II
~

CR.LF
6

write one sector"

20202036

II
t

20382077

III

72697465
206f6e65
20736563
746f72
01053 Oc42 OdOa
01054 Oc44 2020

II

I

iii

dc.b

CR.LF

dc.b

7

seek to sector"

~

recalibrate"

.
.

20202037
20382073
65656b20

dc.b
dc.b

~

CR.LF
8

20202038
203a2072
6563616c
69627261
7465
01057 Oc71 OdOa
01058 Oc73 2020

--

II
dc.b
dc.b

..
i

CR.LF
9

exit"

20202039

~

20382065
786974
01059 Oc80 OdOa
01060 Oc82 2020

~
~

746f2073
6563746f
72
01055 Oc5b OdOa
01056 Oc5d 2020

~

~
dc.b
dc.b

CR.LF
a

show buffer"

~

20202061
203a2073

III

686f7720

.
~

62756666
6572
01061 Oc96 Od08

dc.b

01062 Oc98 2020

dc.b

CR.LF
b

fill buffer with constant"

20202062
203a2066
696c6c20
62756666

.r~
i
ill

65722077
69746820
636t6e73

III

I-

74616e74
01063 Ocba OdOa

dc.b

01064 Ocbc 2020

dc.b

CR.LF
c

change target id"

.
!II

!III
I

I

I

Microware OS-9/68000 Reaident Macro Aaa . .bler Vl.5
tatacaL.

86/01/23

17:47

Page

tatncr - OS-9/68000 CC-74 Teat Routin.a
20202063
203.2063
68616867
65207461

•

72676574
206964

•

01065 Ocd5 OdO.
01066 Ocd7 2020

dc.b

CR.LF

dc.b

d

change drive number"

20202064
20382063
68616e67
65206472
69766520

II

6e756d62
6572

II

01067 Oct3 OdOa
01068 Oct5 OdOa
01069 Oct7 2020

dc.b
dc.b

CR.LF
CR.LF

dc.b

test number ? "

20202074
65737420
6e756d62

01070
01071

.

6572203f
20
0000018c szmsgl

01072 OdOa OdOa _g2
01073 OdOc 2a28

equ

--lI8g1

dc.b
dc.b

CR.LF

dc.b

CR.LF
--lI8g2

"-- CC74 init error **"

20434337
3420696e
69742065

II1II

II1II

72726f72
202a2a
01074 0d21 OdOa
01075 00000019 szmsg2
01076
01077 0d23 OdOa I18g3
01078 0d25 5375

II

equ
dc.b
dc.b

CR.LF

dc.b

CR.LF

equ

*-msg3

dc.b
dc.b

CR.LF
"What?"

dc.b

CR.LF

equ

*-msg4

dc.b
dc.b

CR.LF
CR.LF
"Give Physical Sector Number: "

·Successfull completion of this test"

63636573
7366756c
6c20636f
6d706c65

II

74696t6e
206f6620
74686973

~.:jjj

•

20746573
74
01079 Od48 OdOa
01080 00000027 szmsg3
01081

•
III

•
III

01082 Od4a OdOa msg4
01083 Od4c 5768
61743f
01084 Od51 OdOa
01085
01086

00000009 szmsg4

01087 Od53 OdOa mag5
01088 Od55 OdOa
01089 Od57 4769
76652050
68797369
63616c20

dc.b

29

Microwar. 08-9/68000 Reaident Macro Aaaeabler Vi.S
tatacal.e

86/01/23

17:47

:Page

30

tatncr - OS-9/68000 OC-74 T.at Routinea
53656374
6f7:1:104.
756d6:l65
723.20
01090 000000:11 az. . gS
equ
*-..g5
01091
01092 Od74 OdOa . .g6
dc.b
CR.Ll
01093 Od76 OdO.
dc.b
CR.Ll
01094 Od78 4769
dc.b
"Give constant to fill buffer with: "
76652063
6f6e7374
616e7UO
746t2066

696c6c20
62756666
65722077
6974683a
20
00000027 szmsg6

01095
01096
01097 Od9b OdO. msg7
01098 Od9d OdOa
01099 Od9f 436f
6e74696e
75653a20
01100 OOOOOOOe szmsg7
01101
01102 Oda9 OdOa msg8
01103 Odab OdO.
01104 Odad 4769
76652074
61726765
74206964
2028302d
37293a20
01105 0000001. szmsg8
01106
01107 Odc3 OdO. msg9
01108 Odc5 OdO.
01109 Odc7 4769
76652064
72697665
206e756d
62657220
28302d31
293.20
01110 0000001d szmsg9

01111 •
01112 • error messages
01113 •
01114 OdeO OdO. emsgO
01115 Ode2 OdO.
01116 Ode4 2.2a
2053656e
73652053
74617475
73206572
726f7220
636f6465
203820
01117 00000021 szemsgO

equ

·-msg6

dc.b
dc.b
dc.b

CR.LF
CR.LF
"Continue:

equ

*-msg7

dc.b
dc.b
dc.b

CR.Ll
CR.Ll
"Give target id (0-7) : "

equ

*-msg8

dc.b
dc.b
dc.b

CR.Ll
CR.Ll
"Give drive number (0-1): •

equ

*-msg9

dc.b
dc.b
dc.b

CR.LF
CR.LF
"** Sense Status error code

equ

*-emsgO

.

c
c

•ill
I

~

•
iii

•
--i

..
•
~

.
iiiIi

.
"Ii
.'11

..
~

,
.I

..
~

~

•

.
.
iiIIII

~

~

III
-~

iii

,.

.
~

II
~

~
~

Microwere OS-9/68000 Reaident Macro Aaa . .bler V1.5 86/01/23 17:47 'age·
tatac.i.a
t.tncr - OS-9/68000 CC-74 Te.t Routine.
01118
dc.b
01119 Oe01 OdOa . . .gl
CR.LF
dc.b
01120 Oe03 OdOa
CR.LF
~ee Internal diagnoatic error ee M
dc.b
01121 Oe05 2e2a
20496e74
65726e61
6c206469
61676e6f
73746963
20657272
6f72202a
2a
dc.b
01122 Oe24 OdO.
CR.U
e-emsg1
equ
01123 00000025 azemsg1
01124
dc.b
01125 Oe26 OdO. emsg2
CR.U
01126 Oe28 OdOa
dc.b
CR.LF
M** Ram test error **"
01127 Oe2a 2a2•
dc.b
2052616d
20746573
74206572
726f7220
2a2 •
01128 Oe3e OdOa
dc.b
CR.U
01129 0000001. azemsg2
equ
*-emsg2
01130
01131 Oe40 OdOa emsg3
dc.b
CR.U
01132 0842 OdOa
dc.b
CR.U
M** Init drive parameters error .*M
01133 Oe44 2a2a
dc.b
20496e69
74206472
69766520
70617261
6d657465
72732065
72726f72
202a2a
01134 Oe65 OdOa
dc.b
CR.U
equ
01135 00000027 azemsg3
*-emsg3
01136
01137 Oe67 OdOa emsg4
dc.b
CR.U
01138 Oe69 OdOa
dc.b
CR.U
M** Test Drive Ready error **M
01139 Oe6b 2a2a
dc.b
20546573
74204472
69766520
52656164
79206572
726f7220
282a
dc.b
01140 Oe87 OdOa
CR.LF
equ
*-emsg4
01141 00000022 azemsg4
01142
CR.U
01143 Oe89 OdOa em8g5
dc.b
dc.b
CR.LF
01144 Oe8b OdOa
M** Format Drive error **M
dc.b
01145 Oe8d 2a2a
20466f72
6d617420
44726976
65206572
726f7220

31

ft1croware OS-9/68000 Resident Racro Ass. .b1er V1.5 86/01/23 17:47
tstsc.i .•
tstncr - 05-9/68000 CC-74 T••t Routin••
202.2.
01146 0.&6 OdO.
dc.b
CR. LIP
01147 OOOOOOlf sa ...g5
.qu
·-_g5
01148
01149 0 ••8 OdO. "'06
dc.b
CR. LIP
01150 0 ••• OdO.
dc.b
CR. LIP
01151 O•• c 2.2.
••• Driv. Diagnostic error •• dc.b
20447269
76652044
6961676e
6f737469
63206572
726f7220
2.2a
01152 Oec8 OdO.
dc.b
CR. LIP
01153 00000022 szemsg6
equ
·-emsg6
01154
01155 Oeca OdOa emsg7
dc.b
CR.LF
01156 Oecc OdOa
dc.b
CR.LF
01157 Oece 2a2a
••• Read One Sector error •••
dc.b
20526561

64204f6e
·65205365
63746f72
20657272
6f72202a
2a
01158 Oee9 OdO.
01159 00000021 szemsg7
01160
01161 Oeeb OdOa emsg8
01162 Oeed OdOa
01163 Oeef 2a2a
20577269
7465204f
6e652053
6563746f
72206572
726f7220
2a2.
01164 OfOb OdO.
01165 00000022 szemsg8
01166
01167 OfOd OdO. emso9
01168 Of Of OdO.
·01169 Ofl1 2a2a
20536565
6b20746f
20536563
746f7220
6572726f
72202a2.
01170 Of2b OdO.
01171 00000020 szemsg9
01172
01173 Of2d OdO. emsg10
01174 Of2f OdO.
01175 Of31 2a2a
20526563
616c6962
72617465

dc.b
equ

CR.LF

dc.b
dc.b
dc.b

CR.LF
CR.LF

dc.b
equ

CR. LIP

dc.b
dc.b
dc.b

CR.LF
CR.LF

dc.b
equ

CR.LF

dc.b
dc.b
dc.b

CR.LF
CR. LIP

·-emsg7

••• Write One Sector error •• -

·-emsg8

- •• Seek to Sector error •••

*-emsg9

w••

Recalibrate error *.fl

Page

32

•

Microware OS-9/68000 Reaident Macro Aaa . .b1er VI,S

86/01/23

17:47

Page

tataca! ••
tatncr - OS-9/68000 CC-74 Teat Routinea

"'

206S7172

I

6t71101a
1.

-"

•
,~

II
::ti

01176 OU8 OdO.

dc.b

01177

equ

0000001d azemag10

CR.LF
"-_ag10

01178
01179 Ot4a OdO. emagll

dc.b

CR.LF

01180 Ot4c OdO.

dc.b

01181 OUe 2.2.
2053656e

dc.b

CR.LF
Senae Statua Error

dc.b

CR.LF

equ

"-emsg11

dc.b
dc.b

CR.LF

w".

""w

73652053
74617475

•

73204572

-~

•

726t7220

'ill

2.2.
01182 Of66 OdO.
01183 0000001e Bzemsg11

•

01184
01185 Of68 OdOa emsg12

~

•

01186 Of6. OdO.
01187 Of6c 2a2a

dc.b

CR.LF
••• Error in PSN

dc.b
equ

CR.LF
"-emsg12

dc.b
dc.b
dc.b

CR.LF
CR.LF
Error in fill constant •••

dc.b
equ

CR.LF
·-emsg13

dc.b

CR.LF

dc.b
dc.b

CR.LF
••• Time out error •••

dc.b
equ

CR.LF
·-emsg14

dc.b

CR.LF

dc.b
dc.b

CR.LF
Illegal interrupt occured

UW

20457272
6f722069
6e205053

;'1

III
-~

,
I

III

•

4e202a2a
01188 Of7e OdOa
01189 00000018 Bzemsg12
01190
01191 Of80 OdOa emsg13
01192 Of82 OdOa
01193 Of84 2a2a
20457272
6f722069

"'i

III

6e206669
6c6c2063
6f6e7374

OJ

616e7420

III
4i

III
'\I

•
-~

•
.~

•

.
.~

-~

2a2a
01194 OfaO OdOa
01195
01196

00000022 szemsg13

01197 Ofa2 OdOa emsg14
01198 Ofa4 OdOa
01199 Ofa6 2a2a
2054696d
65206f75
74206572
726f7220
2a2a
01200 Ofba OdOa
01201 0000001a szemsg14
01202
01203 Ofbc OdOa emsg15
01204 Ofbe OdOa
01205 Of cO 2a2a
20496c6c
6567616c

III

20696e74
65727275

~

7074206f
63637572

III
--'I

w..

w••

.*"

33

Microwere OS-9/68000 Reaident Macro Aaa . .bler Vl.5
tataca! .•
tat ncr - 05-9/68000 CC-74 Teat Routine.
6564202.

86/01/23

17:47

Page

34

l.

01206
01207
01208
01209
01210
01211

Ofdf OdO.
00000025 az: __ g15

dc.b
equ

CR. LlI'

Ofel OdO. emag16
Ofe3 OdO.
Ofe5 2e2.
20457272
6f722069
6e207461
72676574
20696420
2.2.
01212 Offd OdO.
01213 0000001e szemsg16
01214
01215 Offf OdOs eDlSg17
01216 1001 OdOs
01217 1003 2a2a
20457272
6f722069
6e206472
69766520
6e756d62
6572202a
2a
01218 101e OdOa
01219 00000021 sZeDISg17
01220
01221 00001020

dc.b
dc.b
dc.b

CR.LlI'
CR. LlI'

dc.b
equ

CR.LF

dc.b
dc.b
dc.b

CR.LF
CR.LF

dc.b
equ

CR.LlI'

*-_g15

.** Error 1n target 1d **.

*-emsg16

.** Error in drive number **"

*-emsg17

ends

c

i

Microware 05-9/68000 Reaident Macro Aa ...bler V1.S

•

86/01/23

18:18

Page

1

rbc74x10c80.a
Diak Driver - Device Driver Por CC74 VME acai controller
00001
n_
Dbk
Driver
00002
ttl
Device
Driver For CC74 YME acai controller

•

00003 • Editon Hiatory
00004
00005· ,
Date

''I

•

By

Calaenta

00006 •
--------- -----------------------------------------------00007 • 00 85/01/21 Fiat attempt to complete new aet up
N.N.
Uaea acai NCR 5385 and dmac MC68450.
00008 •
wvv
00009 • 01 85/05/22 Added code to uae Xebec 1401 controller

•

00010 • 02
00011 •
00012 •
00013 •

•

.-

85/07/30 Added aome error exits. aome cleanup.
added drive' init at 'init drive' Bubr.
added aecond error table tor 1401.
added direct command in 'PutStat' subr.
Tested with xebeq 1410. 1410a. 1401 and SCSI
chip NCR 5385(E) as target.
85/10/11 Changed code tor 1401 to CC-80

00014 •
00015 •
00016 • 03
00017
00018 00000003 Edition
00019
00020 OOOOOeOl Typ_Lang
00021 00008000 Attr_Rev
00022
00023
00024
00025
00007

H.H.
NN

equ

3

set
set

(Drivr«8)+Objct Device Driver In Assembly Language

psect

Hcr.Typ_Lang.Attr_Rev.Edition.O.DiskEnt

use

defsfile

current edition number

(ReEnt«8)+0

00008
00026 •• Edition 2 changes

III

III

00027
00028
00029
00030

•
• these equates are usefull in de direct command mode
• they refer to the block structure used. if this
• block structure is changed. be sure these are also

00031 • updated

•

.
II

II

..
..
•

00032 •
00033 0000000,0 CMD_PTR
00034 00000004 CMD_SIZ
00035 00000006 DATA_PTR
00036 OOOOOOOa DATA_SIZ
00037
00038

OOOOOOOc STAT_PTR
00000010 STAT_SIZ

00039
00040
00041

00000012
00000016
00000018
0000001c
0000001e

MSG_PTR
MSG_SIZ
ERR PTR
ERR_SIZ
CNT_DAT

00042
00043
00044
00045 •• 3NN start change
00046
00047
00048
00049
00050
00051
00052
00053
00054
00055
00056
00057
00058
00059

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

00
04
06
10

4
2
4
2

12
16

" bytes
2 bytes
4 bytes

18
22
24
28
30

2
4
2
2

bytes
bytes
bytes
bytes

bytes
bytes
bytes
bytes

*

*
*
*

Mode offset equates. useful in accessing Hode byte's
for descripter cc-80
Offset in initialization tables for floppy's

o

00000000 M_ResO
00000001 M_Type

equ
equ

00000002 M Res2
00000003 M BlkL

equ
equ

00000004 M DensO
00000005 M NoBO
00000008 M Res8

equ
equ
equ

4

5
8

density code track 0 OO.Ol-sd 02-dd
number of blocks track 0
reserved

00000009 M BlkSO

equ

9

block size track 0

1

2
3

reserved
media type OO=Ol=S"ss 02-S"ds 80.81-8"ss 82=S"ds
reserved
length of blok list (- 16)

OS-9/68oo0 Re.ident Macro Aa ...bler Vl.5 86/01/23 18:18 Page
2
rbc74xl.0c80. a
Disk Driver - Device Driver For CC7. VMS sc.i controller
00060
equ
den.ity code track 10
00061 ooOooOOc "_Den.l
U
equ
number of blocks track 10
00062 ooOOOOOd "_NoB1
13
equ
16
re.erved
00063 00000010 "_Re.16
equ
block .ize track 10
17
00064 00000011 "_BlkS1
00065
equ
20
gap length track 0
00066 00000014 "_GapO
equ
gap length format track 0
00067 00000015 "_FGapO
U
22gap length track 10
equ
00068 00000016 "_Gap1
gap length format track 10
23
equ
00069 00000017 "_Fgap1
step rate
equ
00070 00000018 "_Step
2.
00071 00000019 "_HIt
equ
25
head load time
26
00072 00000018 "_Rut
equ
head unload time
00073 0000001b "_MotOn
motor on timing
27
equ
equ
motor off timing
0007. 0000001d "_MotOff
29
equ
starting sector number
31
00075 0000001t "_Sect
starting cilinder number
equ
00076 00000020 "_Cit
32
highest block address
equ
00077 00000021 "_"axBlk
33
retry count for read
equ
00078 00000024 "_RetryR
36
retry count for write
equ
37
00079 00000025 "_RetryW
equ
38
00080 00000026 "_RetryF
retry count for format
00081 00000027 "_Res39
reserved
equ
39
00082
00083 •• Edition 2 end changes
00084

~croware

00086

*

00087
00088
00089
00090
00091
00092
00093
00094
00095
00096
00097
00098
00099
00100
00101
00102
00103
00104
00105
00106
00107
00108
00109
00110
00111
00112
00113
00114
00115
00116
00117
00118
00119
00120

•

*
*
*

CC74 Definitions
board base address
OOfffeOO CC74_BASE equ

$fffeOO

hardware control register cc-74
00000101 CONTROL74 equ
$101

offset from cc-74 base

NCR 5385 register offset def' s
00000121 DATNCR
equ
$121
00000123 COMNCR
equ
$123
00000125 CNTNCR
equ
$125
00000127 DESIDNCR
equ
$127
00000129 AUXNCR
equ
$129
0000012b IDNCR
equ
$128
0000012d IRgNCR
equ
$12D
equ
$12F
0000012f SRCIDNCR
00000133 DIAGNCR
$133
equ
00000139 TFRNCR
$139
equ
00000139 TCMONCR
$139
equ
equ
$138
0000013b TCMINCR
0000013d TCLENCR
$13D
equ

data register to scsi bus
command register
control register
destination id register
auxiliary status register
id register
interrupt register
source id register
diagnostic status register
transfer counter register
transfer counter most sign. byte
transfer counter middle byte
transfer counter least sign. byte

* DNA 68450 base address
00000000
00000040
00000080
OOOOOOcO
OOOOOOff

CHNLO
CHNL1
CHNL2
CHNL3
GENCR

equ
equ
equ
equ
equ

$00
$40
$80
$CO
CBNLO + $FF

*

DNA 68450 device definitions
o
equ
00000000 CSR
1
equ
00000001 CER
4
equ
00000004 OCR
equ
5
00000005 OCR

channel status register
channel error register
device control register
operation control register

•

•
•
. to 
1 trom  to 
bit 1 - 0 no data phase expected
1 data pbase expected

00958 •
00959 *

00962
00963

*

10 size ot data block

*
*

00960 •
00961 *

(4 bytea)

04 aize ot command block (2 bytes)
06 data block ptr
(4 bytes)

00947 •

•

- ptr to sasi cmd block

(*)

not used in this implementation of direct cmd.

*

*

return: if ERROR then CCzset and (dl.w)-Error-code

else CC-clr
00964 •
00965
DirectClDd
00966 042a,,2869
movea.l

PD_RGS(al).a4

point to user reg. stack.

0000

•

•
•

•

00967 042e-42ac

clr.l

R$dO(a4)

assume no error.

0000
00968 0432-286c
0000

movea.l

R$aO (84) • a4

point to command block struct

00969 0436 41ea
0904

lea

HD_cmd(a2).aO

00970 043a 266c

movea.l

CMD_PTR(a4).a3 point to command block

0000
043e
303c
00971
0005

move.w

15.dO

00972 0442 10db Dcmnd05

move.b

(a3)+.(aO)+

00973 0444 51c8

dbra

dO.Dcmnd05

fffc
00974 0448 323c

move.w

1$6.dl

lea

HD.,.:cmd(a2) .a5

00976 0450=266a
0000

movea.l

V_PORT (a2) .a3

00977 0454 6100
0316

bar

HCRcmd

00978 0458 6500
0058

bca

Dcmndl5

00979 045c 342c
001e

move.w

CHT_DAT(a4) .d2

00980 0460 0802

btst

11.d2

beq.s
movea.l

Dcmnd25
no data pbase
DATA_PTR(a4).a5 get data block pointer

move.w

DATA_SIZ(a4).dl get size

0

0006
00975 044c 4bea

•
•

•

•

copy command to static storage

0904

0001
00981 0464 671a
00982 0466 2a6c
0006
00983 046a 322c

Microware 05-9/68000 Resident Macro Asa. .bler Vl.S 86/01/23 18:19 Page
rbc74x10c80.a
Disk Driver - Device Driver For OC74 VME sc.i controller
OOOa
lIOVe.b
assume (III. . > to (dev>
00984 046e 103c
'MeaToDev.dO
0000
00985 0472 0802
btat
'0.d2
0000
Ik::IIInd20
00986 0416 6104
beq .•
.ove. b
00981 0478 103c
'DevToMena. dO
0080
bsr
NCRdJIIa
00988 047c 6100 Dcnmd20
03b4
BD_BtatuB(a2).a5
00989 0480 4bea Dcnmd25
lea
090a
NCRJItatuB
00990 0484 6100
bBr
0358
. BD_lII8g(a2) .a5
lea
00991 0488 4bea
090b
bsr
NCRmsg
00992 048c 6100
036c
00993 * Edition 2 change
btst
'ErrStat.BD_atatus(a2)
00994 0490 082a
0001090a
Dcmnd90
00995 0496 671c
beq.s
Benatat
00996 0498 6100
bsr
041c
.ovea.l ERR_PTR(a4) .a3 point to error block
00991 049c 266c
0018
00998 04aO 303c
IIIOve.w
'$3.dO
0003
00999 04a4 41ea
BD_sense(a2}.aO
lea
090c
(aO)+.(a3)+
copy error details
01000 04a8 16d8 DcnmdlO
IIIOve. b
01001 04aa 51c8
dbra
dO. DcmndlO
fffc
01002 04ae-003c
ori
'Carry.ccr
0000
01003 04b2 4e15 Dcnmdl5
rts
leave with carry set and D1 with error code
01004 04b4 7000 Dcnmd90
IIIOveq.l 'O.dO
01005 04b6 4e75
rts
leave with carry clear. dO also clr.
01006 ** Edition 2 end change
01001

..
:

•

•
•
•

..
•

Microware 09-9/68000 Resident Macro Aas . .bler Vl.5 86/01/23
rbc74xl0c80. a
Disk Driver - Device Driver For CC7C VME scsi controller
01009 •
01010 ••••••••••••••••••••••••••••••••••••••••

•

•
•
•
•

..
..
....

29

01013 •
01014 ·Initialise controller from drive parameter. in patb de.criptor
01015 •
01016 ·Input: (al) • path descriptor
- 01017·
(a2)
Static .torage
01018
01019
01020
01021
01022
01023
0102C
01025

01027

..'1

Page

01011 •
01012 ·lIflDRV

01026

•

18:19

01028
01029
01030

•
• 3D cbange.
InitOriv
OCb8 7200
OCba.1229
0000
04be 4882
04cO 6716
04c2·4829
0000
04c6 6bOO
00e4
04ca-M69
0000
04ce 6<&46
04dO 032a
093a
04d4 6700
00d6

moveq
move.b

10.41
PO_DRV(al) .41

clear all of dl
get drive number

tat.l
beq.s
tst.b

d2

IniDrv10
PD_TYP(al)

sector O?
.. yes
hard disk?

bad

IniDrv90

•. yes. DO action

cmp.w

PD_TOS(al) .d2

in track O?

bcc.s
btat

IniDrv20
dl.V_TrO(a2)

•• no
already on track O?

beq

IniOrv90

.. yes. no action

01031
01032
IniDrv10
01033 • Going to track 0 or going to aector 0 of bard disk
01034 04d8-4a29
tst.b
PO_TYP(a1)
bard disk?
0000
bpI
01035 04dc 6800
IniOrv1s
.. no
0030
01036 04eO 48e7

movem.l

dO/d2-d7/aO-a6.-(a7)

btfe
01037 04e4-2a69

movea.l

PO_OEV(a1).a5

get device table pointer

01038 04e8 .. 2a6d

IIOvea.l

V$DESC(a5).a5

point to descriptor

0000
01039 04ec 7000
01040 04ee-302d

IIOveq
move.w

lO.dO
M$DevCon(a5).dO get offset to init bytes

addq
adda.l
lea

point past byte count
12.dO
set up pointer to init bytes
dO.a5
V_IntBuf(a2),a4 point to buffer

IDOveq
IDOve.b
dbra

17.dO
(a5)+.(84)+
dO, IniDrv12

number of bytes - 1

bar

Doinit

do the command

movem.1

(a7)+,dO/d2-d7/aO-86

bra

IniDrv95

bcIr

dl.V_TrO(a2)

bra

IniDrv25

0000

0000
01041 04t2 5440

01042 04f4 dbcO
01043 04f6 4gea
0912

01044 04fa 7007
01045 OUc 18dd IniDrv12
01046 04fe slc8
fffc
01047 0502 6100
OOac
01048 0506 4cdf
7ffd
01049 050a 6000
00a2
01050 050e 03aa IniDrv15
093a
6000
0512
01051

do all bytes

.ay on track 0

Ricroware 08-9/68000
rbc74x10clO .•

a..ident

Macro Aaaeabler Vl.5

86/01/23

18:19

Page

30

Diak Driver - Device Driver For CC74 YME acai controller
OOOa
01052
1niDrv20
01053
01054 0516 03e.
baet
.lre.dy otf track 07 (.et flag if not)
093.
01055 051. 6600
0090

bne

IniDrv90

01056 051e 48e7 1niDrv25
btte
01057 0522-2069
0000
01058 0526-2a69
0000
01059 052a-2a6d
0000
01060 052. 7000
01061 0530-302d
0000
01062 0534 5440
01063 0536 dbcO
01064 0538 4gea
0912
01065 053c 103c
0027
01066 0540 18dd IniDrv30
01067 0542 51c8
fftc
01068 0546 4bea
0912
01069 054a 102d
0001
01070 054e 0200
OOfO
01071 0552-0828
00000000
01072 0558 6706
01073 OSSa 0000
0002
01074 055e 6004
01075 0560 0000 IniDrv40
0001
01076 0564 Ib40 IniDrv50
0001
01077 0568.0828

.ov... l

dO/d2-d7/aO-a6.-(a7)

.ovea.l

PD_DTB(al) .aO

point to current drive table

.ovea.l

PD_DEV(al).a5

get device table pointer

.ovea.l

V$DESC(a5) •• 5

point to descriptor

.oveq
.ove ••

'O.dO
M$DeVCon(a5).dO get offset to init bytes

addq
adda.l
lea

'2.dO
point past byte count
dO.a5
set up pointer to init by!;es
V_IntBuf(a2).a4 point to buffer

.ove.b

'39.dO

number of bytes

.ove.b
dbra

(a5)+. (a4)+
dO. IniDrv30

copy descriptor to buffer

lea

V_IntBuf(a2).a5 point to Init buffer again

move.b

M_Type(a5).dO

get number of sides from table

andi.b

'$fO.dO

clear number of heads

btst

.Side_Bit.DD_FMT(aO) double sided?

.• yea. no action

II

beq.s

In1Orv40

.. no

ori.b

'$02.dO

double sided

!

-I

•.
I

bra.s
ori.b

IniDrv50
'$01. dO

single sided

.ove.b

dO.M_Type(a5)

restore number of heads in table

btst

.Dens_Bit.DD_FMT(aO) double density?

bne.s
move. 1

IniDrv60
.. yes
"_DensO(a5)."_Dens1(a5) Rest of media is like track 0

move. 1

M_Res8(a5)."_Res16(aS) Copy param's

01081 057c 3b6d
00140016
IniDrv60
01082

move.w

"_GapO(aS).M_Gap1(aS)

01083 0582 7cOO
01084 0584-3c29

moveq
move..

d6
PD_ CYL (a1). d6

btst

.Side_Bit.DD_FMT(aO) double sided?

beq.s

IniDrv61
ll.d6

00010000
01078 056e 6612
01079 0570 2b6d
0004000c
01080 0576 2b6d
00080010

0000
01085 0588-0828
00000000
01086 058e 6702
01087 0590 e34e
IniDrv61
01088

lsI .•

'0.

calculate number of
get number of cyl' s

no
double cyl's

sector:~

I

•

•

•

•

•

..

..

..
...

..
.~

31
Microware OS-9/68000 Resident Macro Aase.bler Yl.5 86/01/23 18:19 Page
rbc74z10c80. a
Disk Driver - Device Driver Por OC74 YMI scsi controller
01089 0592 5386
subq.1
11. d6
ignore track 0
01090 0594 cced
.u1u..
"_1081.1(a5).d6 we ba. . it a~t
OOOe
add .•
01091 0598 dc6d
"_.080.1(aS).d6 add count fro. track 0
0006
01092 OS9c 3IM6
.av...
d6."_MaxBlk.l(aS) .ave on .ax blocks
0022
01093 OSaO 6100
bsr
do tbe cOllllland
Ooinit
000.
01094 0584 4cdf
.av... l (a7) •• 40/42-47/aO-a6
7ffd
01095 05a8 6000
bra
IniDrv95
0004
IniDrv90
01096
lIOVeq
clear carry
01097 05ac 7200
'O.eil
01098 05ae 4e75 IniDrv95
rt.
01099 • 3NN end changes
01100
01101 • Init Drive
01102 •
01103 • 3NN cbanges
01104
Ooinit
01105 05bO 48e7
1IOV. . . 1
40/42-d1/aO-a6.-(a1)
bffe
01106 05IM-266a
IIOvea.l V_PORT(a2) .a3 point to port
0000
01107 05b8 157c
move.b
'C$MIRI,BD_ead(a2) init drive params
000c0904
01108 05be-1029
move.b
PD_DRV(a1).dO
0000
01109 05c2 e408
lsr.b
make it controller number
'2.dO
01110 05c4 670c
beq.s
OoinlO
was 1410
01111 OSc6 157c
lIOVe. b
'C$MODE. BD_ CIIId ( a2) is CC-80
00150904
01112 05cc 157c
IIOve.b
,40.V_All(a2)
00280908
01113
Ooin10
01114 • Edition 2 change
01115 0542-1029
.ave.b
PD_DRV(a1).dO
0000
01116 05d6 0200
andi.b
'$03.dO
0003
lsl.b
,s,dO
01111 05da eb08
IIOve.b
dO.BD-psn(a2)
01118 05dc 1540
0905
01119 • Edition 2 end change
lea
BD_ead(a2).a5
01120 05eO 4bea
0904
byte count
IIOve.w
I'.eil
01121 05e4 323c
0006
bsr
NCRead
01122 05e8 6100
0182
Ooinit20
bcs
01123 05ec 6500
003e
V_IntBuf(a2).a5
lea
01124 05fO 4bea
0912
IIOve ••
byte count
01125 05f4 323c
'8.eil
0008
IIOve.b
PD_DRV(a1).40
01126 05f8-1029
0000
make it controller number
lsr.b
12.dO
01121 05fc e408

Microware 08-9/68000 Reaident Macro Aaa.-bler ¥l.S 86/01/23 18:19
rbc74x10caO ••
Diak Driver - Device Driver Por CC74 YME aCBi CODtroller
01128 OSte 6704
beq.a
Ooin20
.aa lUO
01129 0600 323c
lIOVe..
'40. cU
byte COWlt
0028
01130
OoiD20
bar
RCRwr
01131 0604 6100
02d8
le_
RD_at.tua(a2).aS
01132 0608 4be.
090a
IICR8tatua
01133 060c 6100
bar
01dO
RD__ g(a2) .as
le_
01134 0610 4be_
090b
01135 0614 6100
01...
01136 t Edition 2 change
01137 0618 082a
0001090_
01138 061e 670a
01139 0620 6100
02f..
01140 0624 fcdf
7ffd
01141 0628 4e75
01142
01143 062& 7200 Ooinitl0
0114f 062c 4cdf Ooinit20
7tfd
01145 0630 4e75
01146 • 3RR end change.
01147
01148

bar

RCRIIIsg

blat

'ErrSt_t.RD_Btatu8(_2)

beq.a
bar

Ooinit10
senatat

8IOvem.l

(a7)+.dO/42-d7/_0-&6

Page

32

r

..
""~

~
~
~

.
C

• • no error

.
~

~
~

rtB
8IOveq
8IOvem.l
rtB

'O.d!
(&7)+.dO/42-d7/aO-a6

C

C
C
1'1
~

.
1'1

~
C
C
C

C
C

C
r-

Microware 05-9/68000 Re.ident Macro Aa.eabler Vl.S 86/01/23
rbe74a10c80. a
Diak Driver - Device Driver Por CC74 VMI acsi controller

•
•

..
..

01152 •
01153 • Input:
01154
01155
01156
01157
01158
01159
01160
01161
01162

•
•
•
•
• Exit
•
•

(al.1)·
(a2.1) •
(a5.1) •
(42.1) •

path descriptor
device atatic storage
buffer pointer
Logical Sector Nu.ber

(cc) • Carry set on error elae cleared
(41 .• ) • Error code if error elae cleared

RdSector
0632 48e7
0004
0636 123c
0008
063a 6100
OOac
063e-266a
0000
0642 323c
0006
0646 4bea
0904
064a 6100
0120
• Edition 2 change
064e 653a
0650 323c
0100
0654 2a57
0656 103e

.ov_.l

a5.-(sp)

.ove.b

le$RBLK.dl

bar

SetUp

.ove.l

V_PORT(a2).a3

IIOve ••

16.41

get count

lea

BD_cmd(a2).a5

cmd ptr

bar

RCRcmd

bea.s
IIOve..

RdSee90
1$100.41

IIOve.l
.ove.b

(sp).a5
IDevToM_.dO

01174 065a 6100
01d6
01175 • bar RCRrd
01176 065e 4bea
090a

bsr

RCRdma

lea

BD_status(a2).a5

01177 0662 6100

bsr

RCRstatus

01164
01165
01166
01167
01168
01169
01170
01171

•

01172
01173

Read sector(a) cmd

should calculate number

0080

01178
01179

01180
01181
01182

017a
0666 4bea
090b
066a 6100
018e
• Edition 2 change
066e 082a
0001090.
0674 670a

01183 0676 6100

lea
bsr

RCRmsg

btst

'ErrStat.BD_status(a2)

beq.a
bsr

-RdSeclO
senstat

02ge

•

Page

01150 •
01151 • Read One Sector

01163

,.

18:19

01184 067. 4edf

01185 067e
01186 0680

•

01187 0684

•

01188 0688
01189 068a

01190 068e

2000
4e75
323c RdSec10
0000
4cdf
2000
4e75
4cdf RdSec90
2000
4e75

IDOvem.l

(sp) •• a5

rts
IDOve .•

'0.d1

IDOv_.l

(sp) •• as

rts
IDOvem.l

(sp) •• a5

rts

33

Nicroware OS-9/680oo .e.ideDt Macro Aaa..bler Vl.S

86/01/23

18:19

Page

rbc74xlOc&0. a

Diak Driver - Device Driver Por CC74 YMI acai controller
01191

c

r

ill
~

I

III

•

Microware 08-9/68000 Reaident Macro A8aa.b1er Vl.5 86/01/23
rbe74al.OdO.&
Diak Driver - Device Driver lor CC74 VMS acai controller

•

01193 •
01194 • Write ODe Sector

II

•
.~

II

•

•

..

Ii

Ii

II

01195
01196
01197
01198
01199
01200
·01201
01202
01203
01204
01205

•
• Input:
•
•
•
•
• bit
•
•

(al.1)
(a2.1)
(as.1)
(42.1)

•
•
•
•

18:19

Page

patb deacriptor
device atatic storage
buffer pointer
Logical Sector Nuaber

(cc) - Carry set on error e1ae cleared
(41.v) - Error code if error else cleared

WrSector
0690 48e7
.evem.l
0004
01206 • Edition 2 change
01207 • bea.a WrSec90 error
01208 0694 123c
.eve.b
OOOa
01209 0698 6100
bsr
004e
01210 069c-266a
IIOve.l
0000
01211 06aO 323c
.eve.v
0006
01212 06&4 4bes
lea
0904
01213 06a8 6100
bar
00c2
01214 • Edition 2 cbange
01215 06ac 6534
bes.s
01216 06ae 323c
IIOve.v
0100
01217 06b2 2aS7
IIOve.l
01218 06b4 103c
.eve.b
0000
01219 06b8 6100
bar
0118
01220 • bsr RCRvr
01221 06bc 4bea
lea
090a
01222 06cO 6100
bar
Ollc
01223 06c4 4bea
lea
090b
01224 06c8 6100
bar
0130
01225 • Edition 2 change
01226 06cc 082a
btat
0001090a
01221 0642 610a
beq.B
01228 06d4 6100
bsr
0240
IIOvem.l
01229 06d8 4cdf
2000
01230 06dc 4e1S
rts
IIOve.v
01231 06de 323c WrSecl0
0000
IIOv_.l
01232 06e2 "cdf WrSec90
2000
rta
01233 06e6 4e75
01234

a5.-(ap)

'C$WBIJI(.41

Write sector(a) cmd

SetUp
V_PORT(a2).a3
'6.41

get count

BD_ald(a2) .as

cmd ptr

HCRaId

WrSec90
'$100.41
(ap).aS
'MeiaToDev.dO
HCRdllla

BD_Btatus(a2).aS
HCRstatuB
BD_lISg(a2) .as
HCRmsg

IErrStat;BD_status(a2)
WrSecl0
senBtat
(sp) •• aS

'0.41
(ap) •• aS

35

Nicrowar. 08-9/61000 R. .ident Macro A8a.abler VI.5 86/01/23
rbc:74x10dO.a
Diak Driver - Devic. Driver For CC74 YME acai controller

18:19

01236 •
01237 •

S.t Up eo..and Butter

01238 •
01239 •

Tbi. aubroutine .et. up the ca.mand butter uaing the

Page

~16

01240 • rega paaaad by the caller.
01241 •
01242 • Input:
01243 •
(a2) • addre.a ot atatic .torage
01244
01245
01246
01247
01248

•
(eU.b) - eo-&nd Code
•
(41.1) - Phyaical Sector 1
•
(dl.b) - Block count / Interleave
• Edition 2 cbange
•
(dl.b) - no longer needed. no .ore interleave.

01249 • Returna: Nothing
01250 •
SetUp
01251
01252 06e8 163c

.ove.b

11,dl

assume one block to read

t.t.b

PD_TYP(al)

Hard Diak 1

0001
01253 06ec-4a29
0000

..
JIll

01254 • 3NN cbange
01255 06fO 6b48
01256 06t2 48e7

bBi..

.. yes

.ave..l

SetUp25
d6/85,-(a7)

.ovea.l

PD_DEV(81),a5

get device table pointer

movea.l

V$DESC(a5),a5

get descriptor

.oveq
meve.w

'0,d6
MSDeVCon(a5).d6 offset to !nit bytes

8ddq
adda.l
c.p.w

12,d6
d6,85
PD_TOS(al),d2

past byte count
point to mode bytes
in Track 0 1

01264 070c 651a
01265 070e-2069

bes.s
.ave. 1

SetUpl0
PD_DTB(al),aO

.. yes,always single Density
get drive table

0000
01266 0712·0828

btst

lDens_Bit,DD_FMT(aO) double Density 1

beq.s
cmpi.w

SetUpl0
.. no
'256.M_BlkSO+l(a5) IBM 11

beq.s
add.w

SetUp20
PD_TOS(al),d2

bra.s

SetUp20

cmpi.w

,256.M_BlkSO+1(a5) IBM 11

beq.s
lsl.l
move.b

SetUp20
11,d2
'2,dl

movem.l

(87)+,d6/85

move. 1

d2,HD_cmd(82)

buffer the logical sector #

move.b

eU.HD_cmd(82)

buffer command

0204
01257 06t6-2a69
0000
01258 06ta-2a6d
0000
01259 06fe 7cOO
01260 0700.3c2d
0000
01261 0704 5446
01262 0706 dbe6
01263 0708-b469
0000

.
~

I

00010000
01267 0718 670e
01268 071a Oc6d
0100000a

01269 0720 6714
01270 0722-d469
0000
01271 0726· 600e
01272

no
add Track 0 Sectors

SetUpl0

01273 0728 Oc6d
0100000a
01274 072e 6706
01275 0730 e38a
01276 0732 163c
0002
01271 0736 4cdf SetUp20
2040

no
double sector number
two sectors/block

01278 • 3NN end changes

01279 073a 2542 SetUp25
0904
01280 013e 1541
0904

•

•
-'I;

•
•

•

•
•

Microware 05-9/68000 Reaident Macro Aaa. .bler Vl.5 86/01/23 18:19 Page
37
rbc74x10caO .•
Diak Driver - Device Driver For CC74 YME acai controller
01281 0742-1569
.ov•. b
PD_STP(al).BD_ctrl(a2) Load The Standard Option 8yte
00000909
ia it a read command ?
01282 0748 OcOl
a.pi. b
'C$R8IJC d1
0008
01283 074c 6706
beq.a
SetUp30
.. yea
andi.b
'$8F.BD_ctrl(a2) clear 'a' retry bit on other than read
01284 074e 022a
00bf0909
01285
SetUp30
01286 0754-1229
.ove.b
PD_DRV(a1).d1 get drive'
0000
01287 0758 0201
andi.b
clear higher bits
'$03.d1
0003
01288 075c ebOg
1al.b
adjust drive
'5.d1
01289 075e 822a
or.b
BD'-psn (a2) • dl Or Into MS8's Of Address

,

0905

01290 0762 1541
0905
01291 0766 1543

IIOve.b

dl.RDJlsn(a2)

IIOve.b

d3.RD_blk(a2)

Number of blocksl Interleave

0908

•
I

•
•
•
-~

•
•

•
III

III

•
•
•

•

01292
SetUpEx
01293 076a 4.75
01294 * 3NN end change
01295
01296

rts

Return

N1croware 08-9/68000 Re.ident Macro Aa • .-bler Vl.S 86/01/23
rbc74l1l10c80. a
Di.k Driver - Device Driver Por CC74 YMI .c.i controller

18:19

Page

38

01298
01299
01300
01301
01302
01303
01304
01305
01306
01307

•
•
• RCRead : give the NCRS385 a co..and
• entry : as ead pointer
a3 ba.e addre.. CC74
•
a2 .tatic storsge
•
dl
.• byte count
•
•
076c 3fOl RCRc.d:
save byte count
.ave..
dl.-(ap)
076e 422b
tilllout • 10000 * 1024 * Clt)ck period NCR
clr.b
TFRNCR(a3)
0139
01308 0772 323c
(Which is 100 Dsec)
.ave..
'10000.dl
2710
01309 0776 038b
movep.. dl.TFRNCR+2(a3) Timout • 1 sec.
013b
01310 077a 6100 ncmdO
bsr
Testlrq
is there an interrupt pend:~ng
0282
01311 077e 66fa
bne.s
yes reset by reading irq auain
ncmdO
01312 * Edition 2 change
01313 *ncmdl move.b '$04.COMNCR(a3) 'Soft reset ??'
01314 0780.1029
move.b
PD_DRV(al).dO get drive nr.
0000
01315 0784 e408
lsr.b
make it controller number
'2.dO
01316 0786 1740
move.b
dO.DESIDNCR(a3) set target id
0127
01317 078a 177c
move.b
'$09. COMMCR ( a3 ) select XEBEC
00090123
01318 0790 6100
bsr
WaitIrq
bit 10 'function complete' should beset
0288
01319 0794 0801
btst
is it set ?
'O.dl.
0000
01320 0798 6738
beq.s
nccmd9
.. no. not ready
01321 079a 6100
bsr
WaitIrq
bit .1 'bus service' should be set
027e
01322 07ge 321f
move.w
(sp)+.dl.
restore byte count
01323 07aO 422b
clr.b
TFRNCR(a3)
0139
01324 07a4 422b
clr.b
TFRNCR.+2(a3)
013b
01325 07a8 1741
JaOve.b
dl.. TFRMCR+4 (a3) init transfer count
013d
01326 07ac 6100 nc:ad2
is there an interrupt pendillg
bsr
Testlrq
0250
yes reset by reading irq again
01327 07bO 66fa
bne.s
nC81d2
01328 07b2 177c
JaOve.b
'$14 • COMMCR (a3 ) transfer info and
00140123
move.b
AUXNCR(a3) .dO
01329 07b8 102b nand3
0129
01330 07bc 0800
btst
'7.dO
0007
wait for data reg full • 0
bne.s
01331 07cO 66f6
ncmdl
dO
btst
01332 07c2 0800
0001
transfer count zero?
bne.s
nand4
01333 07c6 6606
(a5)+.DATNCR(a3) no. do another byte
IIIOve.b
01334 07c8 175d
0121
bra.s
ncmd3
01335 07cc 60ea
JaOveq
01336 07ce 7200 ncmd4
'0. dl.
rts
01337 07dO 4e75
nccmd9
01338
restore stack
IIIOve. w
{sp)+.dl.
01339 07d2 32lf

.1.

~

II

..
,

Nicroware OS-9/68000 Re.ident Macro Aa ...bler V1.S 86/01/23 18:19 Page
rbc74x.10c80 .•
Diak Driver - Device Driver 'or CC74 VME acai controller
01340 07d4-323c
.ave..
'E$NotRdy.dl
flag unit Dot ready
0000
01341 07d8.003c
or!
.earry.ccr
0000
01342 07dc 4e7s
rt.
01343
01344

•
•
•
•

•
-~
I

-TC,
Al - A,. Fe. - F~

•

HIBYT£.I5i5'ili. Mm. ~ - AaG:

Figure 1 Test Loads

~. ~

- PCL.. BGACK

• AC ELECTRICAL SPECIFICATION (VCC.S.OV±S%.VSS.OV.T.-O-+70°Ct
No.

•

•

f

2

.

2

6

2

8

250

500

167

2

Clock Width "Low"

teL

115

250

75

3

.

Clock Width "High"

115

250

75

125
55
55

500
250
250

Clock Fall TIme

teH
tCf

500
250
250

5

Clock Rise TIme

ter

-

6

Asynchronous Input Setup TIme

tASI

30

7

Data In to OS In "Low"

tolOSL

8

Oat. In to Clock "Low" (Setup TIme)

tOICL

OS In "High" to Data In Valid

tOSHOI

.
.

-

Clock "High" to DOIR "High" IMPU Write)

tCHOAHM

90

CloCk "Low" to OBEN "Low (MPU Cycle)

tCLOBLM

-

80
80
80

Clock "Low" to OBEN "High" IMPU Cycle)

teLOBHM

-

-

DOTR "High" Impedance

tOSHOAZ

17

OS In "High" to OBEN "High" Impedance

tOSHOBZ

18

Clock "High" to Data Out Valid (MPU Reaell

tCHOVM

19

OS In "High" to Oata "High" Impedance

tOSHOZ

20

Clock "Low" to DTACK "Low"

tcLOTL

-21

OS In "High" to OT ACK "High"

tOSHOTH

-

i5'fACK "High"

22

OS In "High" to

23

OTACK "Low" to OS In "High"

24

REO Width "Low"

25

Clock "High" to SR "Low"

26

Clock "High" to SR "High"

Impedance

I
I

BR "Low" to SG "Low"

28

BA "Low" to MPU Cycle End lAS In "High")

29

MPU Cycle End (AS In "High", to BGACK "Low"

-35

36
37

38

I

AEO "Low" to B'GACi( "Low"
I~ance

90
120
120

-

,
I

tASHBL
tCHBL

i

I
!

teLBZ

Clock "High" to Address/FC/ Oata Invalid

teHAZn

Clock. "Low" to Address "High" Impedance

tCLAZ

UAS "High" to Address Inv.lid

tUHAI

!

4.5

II

,

-

I
I

I

0

i 12.0
-

I

50

70

lIS

100

-

80

lIS

100

-

80

lIS

100

lIS

120

lIS

80

4.5

-

90

12.0

120

-

-

-

i

5.5

II

80

I

-

120

-

0
2.0

80

90

120

I

lIS

80

2.0

5.5

80

100
120

tOO
0

CO

lIS

lIS

-

0

lIS
lIS

70

0

0

111

111

-

-

70

140

-

111

70

90
220

0

-

111

10

-

80
80
200

lCO

-

-

111

10

lIS

-

-

I
I

I

-

111

111

90

-

0

I
I

tCHAV
tCHAZx

I

0

111

80

120

90
90

I -

teHBRH

15

MHz

80

-

-

2.0

-

0

100

160

140

0

tCHBRL

tAEQLBL

Clock. "High" to Address/FC Valid

90

tOTl.OSH

i tCHBH

I Clock "High" to Address/FC/Data "High" Impedance

I
I
I

tOSHOTZ

tBRLASH
I

Clock. "High" to BGACK "High"
Clock. "Low" to SGACK "High"

Fig. 2-6

tBFlLBGL II

Clock "High" to SGACK "Low"

II

I

I

I tREQL

27

34

0

90

13

I

25

-

120

20

-

0

tCHORLM

12

32
33

-

25

Clock "High" to DOIR "Low" IMPU Write)

Clock "High" to OBEN "High" Impedance Off

I

0

-

10

100

11

31

30

-

tCHOBZO

tCHORZO

30

-

0

-

10

-

Clock "High" to OOIR "High" Impedance Off

I

10

-

120

10

I

10

min

Unit

max

teyc

OS In "High" to

•

8 MHz

max

Clock Period

16

•

6 MHz

max

1

15

•

min

Frequenc:y of Operation

9

•

4MHz

Test
Condition

Symbol

min

14

..

Item

tOO

-

I
I
I

0
0

4.5

i
I I
;

70

lIS

70
180

lIS

111

-

Clk. Per.

70

lIS

70

ns

5.5
70

-

70

12.0

-

-

lIS

-

80

I
I
I
I

Clk. Per.

1

i

30

80

-

ns

ns
ns

eo
0

lIS

j C1k~Per.

120

-

ns
ns

I
II

ns
ns
lIS

Ito be continued)

eHITACHI

3

HD68450·4.HD68450·6.HD68450·8-----------~------_ _ _ __

No.

-

Item

38

~. ~ "Hi~" to Addr. ./FC/Oete Inv8licl

tSHAZ

.to
41

Address/FC Velid to 2. OS ··l.ow·· IAeed'
Clock "High" to VA! ··l.ow··

'AVSL

42

Clock "Hiett" tID ua"High"
Clock "Low" tID

Clock "High" to ~, lZ "low"

45
46
47
q
41

Clock "l.ow" to

AS, 151" "High"
Clock "l.ow" to~. 151" "Hi~" I~

80

tCLSH

90
120

tCLSZ

tOSL

50
51
52

liS "High" tID ANi "High"

tSHAH

Clock "High" to RNi "Hi~"

teHAL
tcHAH

53

Clock "low" to RNi "High" Irnpedence

tCLAZ

54

Address/FC Velid to RNi "low"

tAVAL

65
58

Rm "Low" to tiS "low" (Write)
Clock "Low" to <5WN "Low"

tCLOL

Clock "High" to R/W"low"

57

Clock '"Low" to OWN "High"
Clock "High" to OWR "High" Impedence

tcHOZ

58

Clock "High to OOIR "Low" (Reed)

tcHOAL

60
61
62
63
64
65
66
67

Clock "High" to DOIR '"High"

tcHOAH

Clock' "Low" to OBEN "low"
Clock "Low" to DiEN"High"

:

tcLOBH
tCLOBZ

90
90
120

Un.t

me.

30'
30

-

M

nl

n.

80

70

80

70

100
70

80
60

80

70

100

80

n.
n.

60

M

n.
n.
M

255
190

nl

n.

CO

80
80

70
70

100

80

ns
ns
M

ns

25
120

50
170

90
90
120

80
80
100

90
90

80

M

ns
70
70

nl

80

ns
ns

M

80

70
70

120
90
90
120

100

80

M

80
80

70
70

M.

100

80

M

ns
ns

Clock "Low" to OBEN '"High" Impedance
Clock "High" to iiiBY'fE "Low"

tCHHIL

90

Clock "High" to HIBYTE "High"

leHHIH

90
90
120

80
80
80

70
70
70

ns
ns

100

80

M

tCHACl

90

80

tCHACH

90
90

80
80

90
90

80
··80

120

100

Clock "Low" to HIBYTE "Low"
Clock "Low" to HIBYTE "High" Impedance
Clock "High" to ACK "Low"
Clock "High" to ACK "High"

Fig. 2-6

tclHll

I telHIZ

I

Clock "Low" to ACK "low"

tClACL

Clock '"High" to OTC '"Low"

tcHOTL

Clock "High" tID OTC ..H .....

tCHOTH

Clock "Low" to OTC ''High'' Impedance

lelOTZ
tOTCL

DTC Width "Low"
Clock "Low" to PCl "Low" 11 /8 Clock)
Clock "Low" to PCl "High" 11 /8 Clock)
PCl Width "Low" (1/8 Clock)
OTACK "low" to Dete In (Setup Time)
0 ... In to Clock "Low" (Setup Time)

II

min

265
50

285

tcLOAZ
tCLOBL

8MH,

max

350

110

tCLOH

Clock "Low" to DOIR "High" Impedance

87

I

-

1

70

80

5045
420
60

tALSL

58

81
82
83
84
85
86

CO
CO

teLUZ

"6$Wldth"low"

78

50
50

tCHSl

tCLOSL
tASL

68
70
71
75
76
77

mIn

90
90
120

Clock "Low" to OS "low" (Write)
AS Width "low"

IMHz

min'

teHUL
tCHUH

un "Hiett" Irnpedenca

43
44

68

4 MHz
me.

Symbol

tcLPL

90

telPH
tpCLL

90
4.0

30

OS "High" to Detll Invalid (Hold Time)

tSHOI

i5S "High" to OTACK "High"

tSHOAH

o
o

.

91

OOIR "Low" to 08EN "low"

92

OBEN "High" to OOIR "High"

93

OTACK Width "Hi~"

50

tBECOAL

I tBECL I
!

I
I tOTH

I

•

70
70
70
70
70

I
I

80
80

2.0
50
50
50
10

ns
Clk. Per.

70
70

15

o
50
2.0
CO
CO
40
10

M

ns
M

4.0

25

o

ns
M

1.0

4.0

240

ns
M

80

180

tOALOf
tOICL

:~~::.::~::C.~~

1.0

1.0 I

ns

160

o
o
50
2.0
30
30

Clk.Per.

90

M

-

ns

1~ I :
- i,

ns

-

I

Clk.Per.

-

I

-

1

ns
ns
ns

- I

ns

- i,
,
!

HITACHI

r

.
.

-----------------------H068450·4.H068450·6.HD68450·8

~

.
.

I

Figure 2 Input Clock Waveform
2

cue:

3

•

5

28 29 30 31

32

I

2

3

•

5

8

19

7

20 21

22 23

2. 25

28

Ii

\

I

I

I

l!!f
f x

J!.I '\
",

I

I

J

~

4

~

i

1

\
~

I

I

n
,
n
1

~1- ~

~

J

I.~
or

I

~

OTACK

1

\1

~

.~

~

DBEN

J

;

2,-

\$

lOS

DOIR

\

!

1,

I

\'"

UOS

jA.
I

!

I

R/W

MPU WRITE CYCLE

K

!

\~

-~

..
..

27

I

~

AS

CS

..

26

MPU READ CYCLE

~

1

2' 25

~~r--r,~~~~~~ ~

1

J

8

~

:r~i

~
il'
---!

~

I
:I

3 •.

~

I

!

.ro~

Figure 3 AC Electrical Waveforms - MPU ReadJWrite

ClK

•

-------~1'
REO

(f.a;"iI Edge Pick-upj

,~+_--__'!t
I I
I

~
____

Ir'~·- - - -________~"______________________~~~--~----+'------

.~

II

l.,or-'

---1""

~8]: +~--__!~------------__--I-~~r~:---4I-----D~.BCGK_----~----------i-:::::1~~--~I------~---------__--_-iIS~~----~~--_~~i
~
~
-!..t'~
BR

"""

!i

1

I

i

u

_ __ _

I

=
BUSCYde:=====~t=======M=PU~~C~~~~===========:====:-~~~1
;;;;;;;;~;;;;;;;;~(::~D~M~A~3~yde~:::»~==~~
~
Ln
I
!

ill

DTC ____

ClK
I

iii

(NOTES)

Cycle

~==================~~====================~i~----~~__

,) Setup time for the asynchronous inputs BG, BGACK BEe. - BEC,. CS, lACK, AS, UOS, lOS, and RtW guarantees their recognition
at the next falling edge of the clock. Setup time for
REC., peL. - PCl •. OT ACK, and DONE guarantees thetr recognition
at the next rising ed!r- of the clock.
2) Timing measurements for Input pins are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts.
Timing measurements for Output pins are referenced to and from a low voltage of 0.5 ~olts and a high voltage of 2.4 volts.
3) These waveforms should only be referenced in regard to the edge-to~ge measurement of the timing specifications. They Me not
intended as a functional description of the input and output si;nals. Refer to other functional descriptions and their related diagrams
for device operation.

Ri

UAS
AS

I~

"\.

- 018

·'0

u os
L

).

ANd Cydt

~

WN

)(

•

~

J

, J,

OIR
OeEN

. HiiYii

~
n-

A Cleo

CK,

,

~
~

~
"

~

J~

~J

fi

t
~

\

,

..,!.

ttl.

ri

~.

~

I

,

-

@I-

-

8 l-

\~
-

JH
~
I

J~

@

~

~

f

\______ --1

________~~---------1~------II

Figure 5 AC Electrical Waveforms - DMA ReadlWrite (Singl!. Cycle)

6

.

~

,

I

ts
9

{$

€

DONE _ _ _ _ _ _ _ _~\===:::::::;:--~I

IREO

r1t

,

"

~

t-"-

CK
TC

~

0
8

-

-

\

Write Cycle

os

R,"Ii

I\J\-

eHITACHI

III
I

iii

•

-----------------------HD68450-4,HD68450-6.HD68450-8

•

2

CL K F \ J \ J \ . J r ' J \ F

•
•

FCo- Fez
A1

I

10

r

AS

r

UOS

r

LOS

R/W

"-

'",

-0OIR

'"
'"

-..!L

./

"'"
~----

ltt

,

,

f

~
r
I

YTE

/

\

"-

I
I
J

\.
\

fh

i..0 I -

\

- {:

J

J.

-

~

10

-~

@

~
~

:£
"-

I

I

I

\

r

ACK
it

PCl
BEC

"-

I

\

9

r

BEN

OTC

f

/

----<
I

WN
0-

!\

"'"

Write Cycle

ACK

.
.

I

./

"'"

-

l1li

7

./

"-

.

I

i'-1~~~~~

ANd Cvele

'"
'"
/

Oeta In

.

S

"-

011

•

4

-.

K

-

III

3

I

.r!\

\

-

@

-

~

1#

.J

I

6

J
0

J
I

Figure 6 Electrical Waveforms - DMA Readl'Write (Dual Cycle)

•

.
...~

.

•

HITACHI

7

I

Mil

H068450-4.H068450-6.H068450-8----------------------•

GENERAL DESCRIPTION

This document derma the HD684S0. a four channel DNA
ControDer. The operation of each channel is independent of the
other channels. The controDer IUpports sinaJe-eddress or dual·
address tnnsfen. The controller IUpports unchained, may
chained, or link chained operations. The device interface includes lines for requestin&, ac:knowledJinl, and providina in·
cidental control for the device.
The DMAC functions by transfel'ling a series of operands
between memory and device; operand sizes can be byte, word,
or lon& word. A block is a sequence of operands; the number of
operands in a block is detennined by the transfer count. A
single channel operation may involve the transfer of several
blocks of data between memory and device.

NOTE:
Throughout the specification, signals are discussed using the
terms active and inactive or asserted or negated independent
of whether the signal is active in the logic one state or the logic
zero state_
•

SIGNAL DESCRIPTION

The (oRowing section identifieS the signals used in connect·
ing to the HMCS68000 bus and peripherals using the DMA

controDer. Each signal has a basic definition of itl UK. a detailed
description of the operation of each signal is contained in IUb·
sequent 1eCtions. Specific limin8 information ia also contained
in subsequent sections.
_
In the foUowing derulitions, ~'MP1J mode" refen to the state
when the DMAC is chip selected. Thee tenn "DNA mode" refen
to the state when the DMAC assumes ownership of the bus.
The DNAC is in the "IDLE mode" at all other times.
•

Input/Output
Active high

A. -A23/ ...
Do -015 <~

...
A 1-A7 <....

I

..

~

•

LOS
UOS
R/W
OTACK

FUNCTION CODES (FCo thrOUih FC2 )
OutpUt
Actiw high

REQ2
Aa<2

BR

BG

Three-sutable

In the MPU mode. the low order :seven address lines specify
which of the internal registers is accessed. The address map for
these registers is shown in Table 1. During a DMA bus cycle•
Al - A, are outputs containing the low order address bits of
the location being accessed.

CS

BGACK

PCLz

IRQ
lACK

REa:,
ACK3
PCL3

OWN
UAS
HIBYTE
OBEN
OOIR

Three-sut.t)le

These output signals provide the nmction codes during DMA
bus cycles. They are three-stated wMe in MPU mode or IDLE
mode.
• CLOCK (ClK)
Input

This is the HMCS68000 system clock and must not be gated
off at any time. Transferring to or from the DMAC registers,
sampling of channel request lines.md gating of all control
lines are done intemaUy in conjunction with the CLK input.

Bmi

• CHIP SELECT (CS)

BEC1
BECz

OTC
Input
Active low

FCo
FC,
FCz

This input signal is used to select the DMAC for programmed
transfers to and from the DMAC. The DMAC is deselected when
the CS input is inactive. If the CS input is asserted during a bus
cycle which is generated by the DMAC, the DMAC internally
terminates the bus cycle, signals an address error, but does not
perfonn an operation. Tltis protects DMAC registen during
bus cycles which are generated by itself. However, bus cycles

II

GNO(2)

Figure 7 Input and Output Signals

8

ADDRESS 8US (AI through A,I
Input/Output
Actiw high

CLOCK

II

Th~.t)I.

These Jines are time multiplexed Iror data and address leads.
The lines DDIR, DBEN, UAS and OWN are used to control the
demultiplexing of the data/address :lines with external gating.
This is explained in a later section.
The bi-directional data lines (Do ~~ DIS) are used to transfer
data between the MPU, DMAC, memory and peripheral devices.
Address Jines are outputs to addre!;J memory and peripheral
devices.
•

Vcd2)

ADDRESS DATA BUS (A.lO o through Au/DIS)

•

HITACHI

I

-----------------------HOS84S0-4.HOS8450-S.HOS8450-8

•

senerated by any other bus masters. including other DMACs.
may address and change the DMAC's internal registen and.
consequently. the operation of the DMAC.
•

•
•

ADDRESS STROBE lAS)
Input/Output
Ac:tive low

In the MPU or IDLE modes, this signal is monitored by the
DMAC if it is requesting, and has been granted. pemtission to
become bus master. In the DMA mode, this signaJ is an output
indicating that the DMAC has placed a valid address on the bus.
•

•
•

Three·".t.bl.

Input/OutPUt
Act.ve low

•

UPPER DATA STROBE CUDS)

•

OWN (OWN)

Input/Output

I

.

These lines are extensions of the address lines indicating
which byte or bytes of data (LSB, MSB) of the addressed word
are being addressed
DATA TRANSFER ACKNOWLEDGE (DTACK)

Active low

This line is asserted by the DMAC during DMA mode. It is
used to control the output of the transparent latch used to
latch the address lines. This line may also be used to control
the direction of bi-directionaJ buffen when the loads on
AS, IDS. UDS, R/W and other signals exceed the drive of the
OMAC pins. It is three-stated during the MPU mode and the
IDLE mode.
•

DATA DIRECTION (DDIR)
Output

•

In the MPU mode DTACK is an output indicating that the
DMAC has completed the requested data transfer (read or
write).
In the DMA mode, the DMAC monitors DTACK to deter·
mine when a data transfer has completed. In the event that a
preemptory bus exception occun prior to or concurrent with
DTACK, the DrACK response is ignored and the bus exception
honored. In the IDU mode, this signal is held in three-state.

Three-statable

This line controls the direction of data through.,a bidirec. tional buffer on the data bus. It is three-stated during the IDLE
mode.
•

BUS EXCEPTION CONTROLS (BEC a through BE~ )
Input
Active low

These lines provide an encoded signal indicating some exceptional bus condition. See Page 3S for details on bus exceptions.

DATA BUS ENABLE (DBEN)
Output

Three-statable

Active low

•

•

Three-stet.ble

Active low

•

Three-statable

LOWER DATA STROBE (LOS)

Input/Output

III

Three·lIt.table

Thr1!e-st.table

iii

Output

ThrM1t.tabl.

Read/Write (R!W) is an input in the MPU mode and an out·
put during the DMA mode. In the MPU mode. it is used to
control the direction of data flow through the DMAC's inputl
output data bus interface. In the DMA mode. R/W is an output
to memory and I/O controUers. It is held three·stated during
IDLE mode.

Input/Output
Active low

This line is an output to latch the upper address bits on the
multiplexed data/address lines. Further explanation is given in
later sections and diagrams. It is three-stated during the MPU
mode and the IDLE mode.

..

REAOIWRITE IRIN)

UPPER ADDRESS STROBE (UASI
Output
Active low

•

•

•

Three-statable

BUS REQUEST (BR)

Active low

Output

This line controls the output of bidirectionaJ buffen on the

.
.
..

multiplexed data/address bus. It is three-stated during the IDLE
mode.
•

Active low

The Bus Request (BR) output is generated by the DMAC to
request ownership of the bus.

HIGH BYTE (HIBYTE)
•
Output

BUS GRANT (BG)

Three-statable

Active low

Input
Active low

This line is used when the operand size is byte in the implicit

addreSSing operation. It is asserted when data is present on the
upper eight bits of the data bus. It is three·stated during the
MPU mode and the IDLE mode.

The Bus Grant (BG) input indicates to the DMAC that it
is to be the next bus master. This signal is originated by the
MPU and propagated via a daisy chain or other arbitration
mechanism. The DMAC cannot assume ownership until both

eHITACHI
:~

9

H0684S0-4.H0684S0-6.H0684S0-8-----------------------

B and IGACK bKome inactive. Once the DMAC acquire.
the bus. it doe. DOt continue to monitor the Ie input.
•

• DONE (DONI)
Input/OutpUt
Actiw low

BUS GRANT ACKNOWLEDGE (BGACK)

- The one ~ output is normally high and goes low concurrent with }XXi if that channel's operation is completed u a
result of that transfer. As an input. it allows the device to indiBUI Grant Acknowledge

(BGACK) is a bidirectional control

tiDe. M an output. it is pnerated by the DMAC to indicate
that it is the bus master.
M an input. BGACK is monitored by the DMAC in order
to determine whether or not the current bus master is a DMA
deYice or not. BGACR must be inactive before the DMAC may
assume ownership of the bus.
•

INTERRUPT REQUEST (IRQ)
Output
Active low

Open drain

cate a normal termination of the oper:ation.
• DEVICE TRANSFER COMPLETE (OTe)
Output
Actiwlow

The single device transfer ccmplete output is normally high
and goes low to signal to the device that the data transfer is
complete. On a write to memory operation, it indicates that
the data has been successfuDy stored, On a read from memory
operation, it indicates that the data ill present at the device and
should be latched.

Interrupt Request (IRQ) is used to interrupt the MPU.
•
•

INTERNAL ORGANIZATION
The DMAC has four largely ind~pendent DMA channels.
Each channel has its own set of channt!l registers. These registers
defme and control the activity of the DMAC in processing a
channel operation.

INTERRUPT ACKNOWLEDGE (lACK)
Input
Active low

Interrupt acknowledge (tACK) is an input to the DMAC
indicating that the current bus cycle is an interrupt acknowledge cycle. By the MPU, the DMAC responds with the contents
of the nonnal or exception interrupt vector register of the
bigbest priority channel requesting an interrupt. 1ACJC is not
serviced if the DMAC has not generated IRQ.

--.....

..... •

..::::.;.

...:.

~::;;;

:::...

~

...:-..-:.::

• CHANNEL REQUEST (REQo thrOU1lh~)
Input
Falling edge or actiw low

..

The four REQx inputs (REQo - REQ3) are falling edge sensitive inputs when the request mode is cycle steal. The ImOX
inputs are low level sensitive when the request mode is.burst.
•

..
r

_

~--

(CPR)

.. T_C-. . . T .......

c....

o.r....--_._

I

(OCR)
(SCR)

-=--

----- .
I

r

CHANNEL ACKNOWLEDGE (ACK o through~)
Output
Active low

I

(CER)
IOCR I
(CCR)

------

One Set Per Channel

(CSR)

,

(NIV)
IEIVI
(MFC)
loFC)

IBFC)
(MTC)

(BTC)
(MAR)
toAR)

(BAR)

One Per oMAC -+ ~..::-_IIGCR)

Non·1hretHtatable

The four ACK,x lines (ACK o - ACK 3) indicate to a request·
ing peripheral device that the bus has been acquired and that
the requested bus cycle is beginning. The· ACKi line may be
used as part of the enable circuit for bus interface to the pe-

Fi~re

8 Internal Re9 sters

ripheral
•
•

PERIPHERAL CONTROL (PCl o 1froI.ql PCl 3 )
Input/Output
Active low

Three~tatable

The four PCIX lines (PCLo - PCL3 ) are multi·purpose lines
which may be individU2lly programmed to be a START output,
an Enable Clock, READY, ABORT, STArus, or INTERRUPT
input.

10

REGISTER ORGANIZATION
The internal accessible register organization is represented in
Table 1. Address space not used wilthin the address map is
reseTVed for future expansion. A read from a reseTVed IlXation
in the map results in a read from the "nuD register". The nuD
register returns all ones for data and results in a normal bus
cycle. A write to one of these locations results in a normal bus
cycle but no write occurs. Unused bits of a defmed register read

as zeros.

eHITACHI

•

•

-----------------------H068450-4.H068450-6.H068450-8

•

Tlbl, 1

DMAC Regist.r Addre.i,. AIIlgnmentl
7 6

Aevl~

•

•

0IannaI Error Regm.r
Deva Control Reginar
()paration Control Regilt1tr
Sequence Control Regimr
Ch--' Control Regin.r
Memory T~ Co\Inter
Memory Add,.... Regimr
o..nc. Add,.. Regimr
. . . T rwtIfer Co\Inter
B_ Add,.... Aaviner

c
c
c
c
c
c
c
c
c
c
c

•

Nol'1Nll Interrvpt Vector
Error Intarrvpt Vector
OIannel Priof'ity Reginar

c c
c c
c c

Memory Function Codes
Devic:a Function Codes

c c
c c
c c

0Ian... Status Reg.,

•

. . . Function Codes

,

Gene,., Control Aavimr

c
c
c
c
c
c
c
c
c
c
c

Add,..'i"
5 4 3 2 ,
-0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1

,

0

Mode

0 0 0 0
0 0 0 1
0 1 0 0
0 1 0 1
0 1 1 0
1
0
1 0
b
1 1 I
0 1
1 0 1 b
1 1

R!WR
R!W
RNI
RNI
RNI
ANI
ANI
ANI
ANI
RrN

1 0

ANI
RNI
ANI

,

• ••
••

0 0
0 0
0

,

1 1
1 0

0 1 0 0 1
1 0 0 0 1
1 1 1 0 0 1

1 1

1 1

1 1

1

01 Statu. Input with Interrupt
10 Start Pube. NeptiYe 1{8 CLK
11 Abort Input

o

Bit 2 Not UMd
OPERATION CONTROL REGISTER (OCR)
The OCR is an operation oriented register. The OIR bit

•

defmes the cUrection of the transfer, to or from memory. The
SIZE bits define the size of the operand and how the transfer
count and .ddress registen are to be handled. The CHAIN bits
tells the I;>MAC if any or what type of chaining is to be performed. The REQG bits defme how requests for transfen are
generated. Chaining and requests are discussed in • later section.

7

6

DIR

0

I I I

Am
ANI
AIW

DIR

1

o

.:

..>l

•

whether the channel is in burst or cycle steal request
mode. The Dn'P bits defme what type of device is on the
channel. If the Dn'P bits are programmed to be a HMCS6800
device the PCL defmition is ignored and the per; line is an
Enable clock input. If the DTYP bits are programmed to be a
device with READY, the PeL definition is ignored and the PeL
line is a ready input (active low). The DPS bit defmes what
port size the device has. The PeL bits define the function of
the PO: line. When the content of the DTYP bits implies
HMCS6800 compatible device, or Device with ACK and
READY, the content of the PeL bits is disregarded. The XRM
bits are ignored if an luto request mode in the OCR is selected.

III

III

00
01
10
11
REQG

•

7

6

XRM

III

5

4

3

o

2

DTYP

XRM

•

DTYP

•
DPS

•

.

o
MAC

Transfer from memory to device
TraMfer from device to memory

Byte
Word
Longword
(undefmed. reserved)

Chain operation is disabled
(undefmed, reserved)
Anay chaining
Linked chaining

DMA Request Generation Method
00 Auto-request at rate limited by General Control
Register (GCR)
01 Auto-request at maximum rate
- 10 REQ line initiates an operand transfer
11 Auto-request the first operand, external request
for subsequent operands

HMCS68000 compatible device, explicitly addressed
HMCS6800 compatible device, explicitly addressed
Device with AOC implicitly addressed
Device with ACK and READY, implicitly address

7

6

5

4

o

o

o

o

DAC

P,ripheral Control line
00 Status Input (can be read by reading CSR)

•

HITACHI

2

MAC

1

0

DAC

Memory Address Count

Memory address register does not count
Memory address register counts up
Memory address register counts down
(undefmed, reserved)

Device Address Register Count

00
01
10
11

8 Bit Port
16 Bit Port

3

Bits 7, 6, 5. 4 Not Used
00
01
10
11

Device Port Siz,

o
1

Pel

(undefined, reserved)
Cycle Steal Mode without Hold
Cycle Steal Mode with Hold

Device Type

00
01
10
11

REQG

addresses.

PCl

External Request Mode
Burst Transfer Mode

00
01
10
11

0

SEQUENCE CONTROL REGISTER (SCR)
The SCR is used to defme the sequencing of memory device

... ~

III

CHAIN

SIZE

1

CHAIN Chaining Operation

specifieS

III

2

Operation Size

00
01
10
11

DEVICE CONTROL REGISTER (OCR)

3

Bit 6 Unused

SIZE

The OCR is. device oriented control register. The XRM bits

4

Direction

o

Am

cc: 00 - Channel #0. 01 - Channel . ,
10 - Channel .2. 11 - Channel .3
00 - High>----

Oo-O's

XOo-XDlI

-------~({==:::J}}I}_)- - -

XOo-XO,.

_n--«(

c:::-

u

DmK

OTACK

eLK

m

g-w.
IJ

~

n1 .2. fl3 4..f'Lr··
5.
23242528272829303132

\\\

\\\
________
r-

I'
»>

======::J)--C

CLK~_._
1 2 3 4 5 8 7 8

\\\

>>>

181920212223242528

Figure 10 MPU Write to DMAC - Word

Figure 9 MPU Read from DMAC - Word
INOTESI
11 The ~ eQuation includes data strobe.
21 0."" 011 reprnent the multiplexed address/dau pins which are
YIIId for data only during MPU mode.

31 XO. - XOu is the Ixtarnal or 68000 system data bus. i.e. on the
41
51
8)

71

81

system side of the data buffers.
Cyde lengths reflect the resporue of the current HD68000 MPU.
In the MPU re~ from DMAC mode. the OMAC will not give
OTAcK until the data is guaranteed valid on the system data bus for
one half clock.
During the MPU reed. the DMAC must relTlOW signals within one
clock .tter AI is negllted.
_
The DMAC will negate ~ within one clock .ner AS is ne~.
During the MPU write to DMAC. the DOIR line will be driven low
to direct the data buffers toward to OMAC before the buffers ••

Figure 11 indicates the DMAC bus arbitration timing. The
DMAC~rts BR: to request the bus mastership. The MPU
issues BG to grant the ownership in the next bus cycle. After
the end of the current cycle, the DMAC starts its own bus cycle
accompanied with the dead cycles.

---

enabled.
91 The DMAC will latch the data (MPU writa to DMAC) before _rt·
ing l:)'TA"l!K. Once the data is latched the OMAC will negate ~
8nd ~ in the pc-oper order.

es-

101
will be remowd within one clock after AS is ne;atad.
11 I Nota tMt D!STR .nd "DIm must driw out of tristate when (3 is
detllCtlld .nd then must be ,.·triStllted at the end of the cycle.
121 The clock reference snown in this diagram is the CPU clock.

eHITACHI

13

HD88450-4.HD88450-8.HD88450-8---------------

0- - - - - -

nJ1..J0Lrl. 1...JL 1..J'L l.JlJL.IL
I
..
L_
_
I
------

CLKSLrLr

IR\
R
r.8GIr'lAI""JIIC~k

-,-- _

.. ~

-c::::::x:::
:
::::x::: ::::r----c:
."
_
_
..
r''-----

~~~LES

}--.

nwR
CONTROL
BUS
CLKSLrLr

--C
: " "..
-

I

_---J

\,----

n.slJ-Lrl. UL l..SL 1.S1J"1..1'L

---Non DMAC---+--'Oeld
(NOTES)

..

I

DMAC Cycles

I

Oead--+-Non DMAC

1) No. the timing of the OWN 1ignII. It will drive 8CtIw one MIt dock prior 10 the Nrt of the fim DMAC cyde. h will drive lnIICtiw one
helf dock .,., the end of the . . OMAC cyde. At this _
time. eI' other control IigneII will triltMa. (). . heIf clock .,., this. the
tMfllignel will triatIte.
2} CONTROL BUS ret.rs to the control pins such .lS8Dl. AS. AfK. etc. on the OMAC.
3} 'I1f IigneI will be nepted one clock .t18r ~ IigneI is . .r18d.

Figure 11 DMAC Bus Arbitration Timing

• DEVICE!DMAC COMMUNICATION

the PCT bit of the Channel Status Regi.'lter.

Communication between peripheral devices and the DMAC
is accommodated by fIVe signal Jines. Each channel has a request
(REO). an acknowledge (~). and a peripheral control tine
(PCI). The last two Jines. the
and DTC lines. are shared
unong the four channels.

nom

(1) REQUEST (Ifm)

A channel can make a request for service by asserting the
individual channel request line.

JiCL AS AN INTERRUPT
The ]5(%' line may also be prograuuned to generate an inter·
rupt on a negative transition.
enables an interrupt which
is requested if the PCT bit of the CSR is set.

nus

'PC[ AS A STARTING CLOCK PULSE
The ~line may be programmed to output a single pulse.

The duration of the active low pulse is eight clock cycles, and
starts when the channel is activated.

(2) ACKNOWLEDGE (ACK)
Each channel has an acknowledge Jine which is activated
during transfers to or from the device. This Jine is used to
implk:itly address the device which is transferring the data.
It may also be used to control the buffering circuits between
the device and the HMCS68000 bus.
(3) PERIPHERAL CONTROL LINE -(PeL)

Pel AS AN ABORT INPUT
The ~ line may be programmed to be an negative transi-

II
~

tion abort in t which terminates an 0 peration by signaling the
abort err r.
n this function has been programmed.
~
lliie is only active after the channel has been start~e
negative transition must remain stab Ie in a low level for a
minimum of two DMAC dock cycles.

II

PeL AS AN ENABLE INPUT
If the DTYP bits are programmed tel be a HMCS6800 device,

C

JJZ

~

Each channel has a peripheral control Jine. The function of

this Jine is quite fleXIble. and is determined by the programmed
state of DCR.
The DTYP bits of the OCR deflne what type of device is
on the channel. If the DTYP bits are progranuned to be a
HMCS6800 device. the PCL derwtion is ignored and the 'PCl:
line is an Enable clock input. If the DTYP bits are programmed
to be a device with READY, the PCL definition is ignored and
the PCLJine is a ready input.
_
The PCL line is active at all times when the PeL line is pre>grammed as a Status input, Interrupt input. a Ready input, or
an Enable input. When programmed to be an Abort input it is
only active after the channel has been started.

PCL

AS A STATUS INPUT

The lieL line may be programmed as a status input. The
status level can be determined by reading the PeS bit in the
CSR. If a negative transition~ and remains stable for two
DMAC clock cycles on the PeL line. the PCT bit of the CSR
is set.
bit is cleared by resetting the DMAC or writing to

nus

14

the PCL definition is ignored and the PCL line is an Enable
clock input. The Enable clock downtime must be as long as
fIVe clock cycles. and mwt be high tor a minimum of three
DMAC clock cycles. but need not be synchronous with the
clock.

PeL AS A READY INPUT
If the DTYP bits are programmed to be a device with

READY. the

PeL definition is ignored and the PCL line is a
READY input. The READY is an active low input.

(4) DONE
DONE is an active low signal which is asserted when the
memory transfer count is exhausted, and there are no more
links te pick up in a chaining operatic)D or the continue bit is
not set. It is asserted and negated coincident with the acknowl·
edge signal of the last operand part.

eHITACHI

•
•
II

•
•

•

•

-----------------------H068450-4.H068450-6.H068450-8
The DMAC abo monitOR the state of the OONE line wlUle
acknowleclpna I device. If the devic:e aaerts
the DMAC
will tenninate the operation after the tnnsfer of the cunent
operand. The DMAC terminates the operation by clwnin& the
ACT bit of the CSR. and lettina the COC and NDT bits of the
CSR. If both the DMAC and the deVice aaertl 150m. the
device tennination is not recognized. but the channel operation
does tenninate.

nmm.

(5) DATA TRANSFER COMPLETE
"i5TC is an active low signal wlUch is asserted when the Ictual
data transfer is ~ccomp1ished. If data is being transferred from
the device,
is asserted to indicate that the dlta is valid It
the device, and should be latched. If a preemptory bus exception terminates the bus cycle, 1rOC is not asserted. 15fC is an
active signal whenever the DMAC is a bus master. It is asserted
for both memory and peripheral DMAC initiated transfers.
• REQUESTS
Requests activate the DMAC to transfer an operand. The
REQG bits of the OCR determine the manner in which requests
are generated. Requests may be externaIly generated by circuitry in the device, or internally generated by the auto-request
mecbanism. Usually a single operation uses only one method
of request generation, but an operation can auto-request the
fust transfer and then wait for the device to request further
transfers.

nre

(1) AUTO-REQUEST TRANSFERS
. 'IlI

J
•

•

The auto-request mechanism pro~des generation of requests
within the DMAC. These requests ean be generated at either
of two rates: maximum-rate. so that the channel always has a
request pending, or limited-rate. The limited rate auto-request
feature functions by monitoring the bus utiliz.ation.
AUTO-REQUEST BUS UTILIZATION
The DMAC monitors bus utilization to control the limitedrate auto-request (LRAR) feature. This monitoring is also used
to detennine when an external request device has paused.
The DMAC divides time into equal length sample intervals
by counting clock cycles. The end of one sample interval marks
the beginning of the next. During a sample interval, the DMAC
notes bus and channel activity. At the end of the interval,
decisions are made which affect channel operations during the
next sample interval. as shown in Figure 12.

•

TlME~

Previous

Sample Interval

•
•

•
•

Current
Sample Interval

LRAR
Interval

Next
Sample Interval

I

Figure 12 DMAC Sample Intervals

Based on the DMA activity during a sample interval, the
DMAC allows limited-rate auto-requests for some initial portion
of the next sample interval. The length of the sample interval.
and the portion of the sample interval during which limited
rate auto-requests can be made are controlled by the BT and
BR parameters in the GeR. The length in clock cycles of the
subinterval during which the DMAC aDows limited-rate auto(BT+4).
requests is controlled by the BT. The number is
For example, if BT equals NO and the DMA utilization of
the bus was low during the previous sample interval. then the

2-·

•

DMAC aeneratel u many auto-requelt transfers u is poSlibJe
during the flnt 64 c:Ioct cycles of the current sample interval.
The ratio of the length of the sample interval to the length
of the limited-rate luto-request interval is controDed by the
BR bits. This same parameter is UIed to determine the level
of DMA bus utilization during the sample interval. If the frac·
tion of DMA clock cyclel durin8 a sample interval exceeds
the programmed utilization level. the DMAC will not allow
limited-rate auto-requests during the next sample interval.
Either ratio is 2·· (BR+l) (2 raised to the BR+I power). For
example. if BR equals llIREE, then at most one out of 16
clock cycles during I sample interval can be a DMA cycle. and
still the DMAC would allow limited-rate auto-requests during
the next sample interval. The DMAC monitors BGACk
during each clock cycle to determine whether or not that clod
cycle is used by a DMA device. If the BGACK input is active,
the DMAC assumes that that clodc cycle is for a DMA device.
If it is inactive, the DMAC assumes that it is not I DMA cycle .
The sample intetYal length is not a direct parameter, but is
equal to
(BT+BR+5) clock cycles. Thus the sample internl
can vary from 32 to 2048 clock cycles.

2--

AUTO-REQUEST
If the REQG bits in the OCR indicate auto-request It the
maximum rate, the DMAC acquires the bus after the operation
is started and transfers data until channel termination. The
DMAC does not relinquish the bus until termination. If a
request is made by another channel of equal or higher priority.
the DMAC services that channel and then resumes the autorequest sequence.
If the REQG bits indicate auto-request at a limited rate,
the channel generates requests only during the limited rate
auto-request interval and then only when the bus utilization
was below the required threshould during the previous sample
interval. As a consequence, if an auto-request at maximum rate
transfer is started, no limited rate auto-requests are generated
before the termination of the maximum rate auto-request
operation.
The ACK. PeL and DTC lines are held inactive during an
auto-request operation if the device type is HMCS68000 c0mpatible. Consequently. any channel may be used for the autorequest function in addition to its normal application without
disturbing any peripheral devices connected to that channel.
Refer to Figure 13 for more specific timing diagrams.
(2) EXTERNAL REQUESTS
If the REQG bits of the OCR indicate that the REO line
generates requests, the transfer requests are generated externally. The request line associated with each channel allows the
device to externally generate requests for DMA transfers. When
the device wants an operand transferred. it makes a request by
asserting the request line. The external request mode is deter·
mined by the XRM bits of the OCR, which allows both burst
and cycle steal request modes. The burst request mode allov..s
a channel to request the transfer of multiple operands using
consecutive bus cycles. The cycle steal request mode allo~
a channel to request the transfer of a single operand.
BURST REQUEST RECOGNITION
In the burst request mode. the 1rnQ line is an active low
input. The device requests an operand transfer by asserting
REQ. The DMAC services the request by arbitrating for the
HMCS68000 bus, obtaining the bus, and notifying the peripher·
al by asserting the acknowledge line. If the request line is active

HITACHI

15

H068450-4.H068450-6.H068450-8----------------,------when the DMAC uaerts acknowledge. and remains active It
least until the DMAC asserts device transfer complete. the
DMAC recognizes a valid request for another operand. wruch
will be transfemd during the next bus cycle if the channel has
priority. If the request line is neglted before the DMAC asserts
devi<:e complete, the DMAC determines there is no valid request
for an operand transfer, and no transfers are generated for that
channel. Channels of the same or higher priority within the
same DMA Controller may have DMA operand transfer requests
serviced during this mode.
If the request is negated before the fU'St transfer cycle has
started. the cycle will terminate with the DMAC returning the
bus.
.
Refer to Figure 14 for more specific timing diagrams.
CYCLE STEAL REQUEST RECOGNITION
In the cycle steal request mode, the device requests an
operand transfer by generating a falling edge on the REQ line.
The DMAC services a request by arbitrating for the bus, obtaining the bus and notifying the peripheral by asserting the acknowledge line.
After an request edge has been asserted it must remain at
the assertion level at least two clock cycles. The request line
must be inactive at least one clock cycle before a request is
made. If another request from the channel is received before
the flJ'St operand part of a fonner request is acknowledged,
the second request is not recognized.
After the DMAC completes the transfer, it may service
another channel, relinquish the bus, or hold the bus and wait
for another request. If there are pending requests from other
channels, one of the requesting channels is serviced. If there
are no requests, the XRM bits determine whether the DMAC

will relinquish the bus. or retain ownership.
If the XRM bits specify cycle steal with hold. the DMAC will
retain ownership. The bus is not giw.n up for arbitration until
the channel operation terminates 01' until the device pauses.
The device is determined to have pI,used if it doe~ not make
any requests during the next full sample interval. The sample
interval counter is free running and ill not reset or modified by
this mode of operation. The sample interval counter is the same
counter that is used for limited Rate Auto Request and is
programmed via the GeR.
If the XRM bits specify cycle steal without hold. the DMAC
will relinquish the bus. If the device generates a request before
DMAC asserts DTC for the last opel'and part, the DMAC will
retain ownership of the bus, and that request will be serviced
before the DMAC relinquishes the bus.
Refer to Figure IS and Figure 16 for more specific timing
diagrams.
REQUEST RECOGNITION IN DUAl·ADDRESS TRANS·
FERS
In a following section dual-address !transfers are defmed. Dual
address transfer is an exception to the request recognition
rules in the previous paragraphs. Refer to the Explicitly Addressed Device section for infonnation.
(3) MIXED REOUEST GENERATION
A single channel can mix the two request generation meth·
ods. By appropriately programming the REQG bits of the OCR.
when the channel is started, the DMAC auto-requests the fust
transfer. Subsequent requests are then generated externally
by the device. The ACJ( and PCL lines perfonn their normal
functions in this operation.

U
'Ilhr-

CLK

20 21 2223 242526272829

XDI
III/

ill

R.W
OWN
oOIR

m

\\\
11/

OBEN
HIBYTE
oTACK
oTC

fJJ

III

\\\

ffT

\\\

'"

\\\

r\\\

'UL.llJ

~

i

II

UTLJl{-

ACK
CLKUL.f1Jl..J
1234567B

.......- - R e a d - - - r - - - - - W n t e - - -___- - - R e . d - - - . . . - from Memory
to Memory
from Memory
(NOTE)

,) Note that ACK. DONE. DTC. and HIBYTE are always inactive in this mode. For comments on the other signals. see not" on the dual
addressing mode with 8 bit device as source.

Figure 13 DMAC Auto Request Read - Write - Read Cycles

16

eHITACHI

r
II

•

-----------------------H068450-4.H0684S0-6.H068450-8

I

•
•
•
-Non OMAC-t---oead --t---oMAC Cycles---t-Other Master -r--oMAC-.......-ldleand Rearbitration Cycles

•

INOTE)

1)

Note tNit in the diagrams showing request timing it is _mid that only one chenne! illCtiw.

Figure 14 oMAC Burst Mode Request Timing

•

•

tnruuu

~----

ru1flI1Jl.fl.Il
L.J

L _________,~~--------BG
\
,r------~a~--------------·\ _______I
~BG.....A~C~K~---~=====\\-......I
4a~~
r ----~
n

~~~lES===:::»---(~~~~}--+-{~~~~~>---<::}- --<~===\>___<--;
ACK--------------------'\\
oTC

'

0

a"

U- -- - _______..!\\=::::;-~/~/----

U

~~---

r1JUUlfUUlJ

ClKJ1Jlfl
Micro Cleanup

-Non oMAC-f--oead-+--- DMAC Cycles,----+-I- Other Master -+-1---- oMAC Cycles-and Aearbitration
INOTES)

II1II

In this mode the device must ~rt REO one clock before the assertion edge of OTC of the last bus cycle at' 10. the bus.
The ~signal is edge triggered.
2) The time labeled "micro cleanup" is the time it takes for the intemallequencer to start another bus cycle if no other channel has
requesu pending.
1)

Figure 15 oMAC Cycle Steal Mode Request Timing

II1II
.~

II1II

•

•

ClKJlIl.
REO"'LJ
BR--,
BG----'"::-\-------J
=BG"-:A"-':C=K

----~

•
•

11

r-

\

}
(
~~~~;:'~j~~~~~::::::~~~~
~~
U
\\
I
'U....lrt-!----.!==:::;:Ul""n------~=i\"'"J;

CYClES-_ --Jr------(L~----......,j~~
BUS

ACK-----------~
OTC -

-

OONE---

•

I

I

M

ClKI1.Il
-Non oMAC---t""-- Dead -~-------

I

I

Figure 16 OMAC Cycle Steal-Hold Mode Request Timing

CHITACHI

17

HD68450·4.HD68450·6.HD68450·8---------------------• DATA TRANSFERS
(1) DEVICE PROTOCOLS
AD DMAC data transfers are IllUmed to be between memory IDd MOther device. 1be word "memory" means a 16-bit

HMCS68000 bus compati»le device. By propanunina the OCR.
the characteristics of the device may be usiped. Each channel
caD

communicate usins IDY of the foDowine protocola.

DTYP Device Type
.
00 HMCS68000 compatible device} Dual Addressina
01 HMCS6800 compatible device
10 Device with Atr
11 Device with "EJ{ and READY

}

Ci ....I..

......-

AdA~ ..

....- .

DUAL ADDRESSING
HMCS68000 and HMCS6800 compatible devices may be
explicitly addressed. This means that before the peripheral
transfers data, a data register within the device must be addressed. Because the address bus is used to address the peripheral,
the data cannot be directly transferred to/from the memory
because the memory also requires addressing. Instead, the data
is transfemd from the source to the DMAC and held in an
intemal DMAC holding register. A second bus transfer between
the DMAC and the destination is then required to complete
the operation. Because both the source and destination of the
transfer are explicitly addressed, this protocol is also called
dual-addressed.

Request Recognition in Dual-Address Transfers
The request recognition protocols defmed in a previous section apply to dual-address operations. Requests are rec::ognjzed
during the transfer to/from the DMAC holding register and the

peripheral u dacrl»ecl in the request protocol IeCtion. This
requires the request to be . .rted before the Iipal
DTC ia _ned, to haft request recopition for the next cycle.
~ocol

Durina the ponion of the operatic1n when the operand or
operand part is transferred between the DMAC holdina resister
IDd memory. requests are also recoplZed. Du~ the transfer between memory and the holdine rqister, J5Tf is not Ulerted,
10 it may DOt be UIed u reference point for request recognition
duriD& this ponion of the operation. Howner, requests will be
re~ if they are Ulerted prior to the portion of the cycle
where DTC would have been asserted. This point is one half
dock cycle before the upper and lower ,data strobes are nesated.
HMCS88000 Compatl»le Dewice Transhn
In this operation, when a request is received, the bus is

~

..

I'

obtained and the transfer completed using the HMCS68000 bus
protocol u shown in Fipres 17 and 18. Refer to Figures 19
through 22 for timing information.

HMCS6800 Compdble Device Transfel1
When a channel is programmed to perform HMCS6800
compat.ible transfers, the PC[" line for that channel is defmed
as an Enable doc:Jc input. The DMAC performs data transfers
between itself and the device usina the HMCS6800 bus protocol,
with the Mr output providins the valid memory address
signal. This operation is necessary mice the HMCS6800 bus
is synchronous and the HMCS68000 bus is asynchronous.
Figure 23 illustrates this protocol. This operation provides
DMAC compatibility with existing HMCS6800 and other
synchronous devices. Refer to F"JlUre:l 24 and 25 for timing
information. Figure 44 illustrates a sample circuit diagram of
a tw0-6800 device system.

III
i
ill

HMCS88000 Dwiol

Add,... Device
1) Set R/Wto RMd

2) Piece AdcIrea on A, - Au
3) Piece Function Codes on
Fe. -F~
4) Aaert Add,.. Strobe cA§)
5) "-rt \JppIr 0 ... Strobe
(Ul5!) .net lowIr 0 ...
StrObe

ems)

6) Aaert AdmowIldgl lACK)

I

i
Prill"! 0 ...
1) Dec:odI Adena
2) Piece 0 ... on O. 3) Aaert 0 ... Trwwfer
Acknowtedgt COTACK)

C.,.

~

I

II

I

c

Acquire 0 ...
1)

LoIct 0 ... into Holding

Register
2) Aaert Device Transfer
Complete COTC)
3) Negetl tmS and ~
4) Negetl AS, ACK end DTC
I

1)

I
,Terminate Cycle
Rlmow 0 ... from Oil - Oil

2) Negate~

,

Stirt Next Cycle

Figure 17 Word Read Cycle Flowchart HMCS68000 Type Device

18

•

HITACHI

•
-----------------------H068450-4.H068450-6.H068450·8

.

OMAC
Add.... 0..,_

III

'1 Place Add.... on A, - Au
21 Piece Function Codes on
FC. - FC,

31 A_n Add.... Strobe Inl
41 Set Rfii to Write

III

51 PI. . Data on O. - 0 \I

61 "-rt Acknowledge I~I 71 Asart Upper Data Strobe

IUDS) and Lo_r Data
Strobe IIDSI

~·~------------------------------------------------------~i
ACQpt Data

•

1) Decode Add....
21 Store Data on O. - D ••
3) ~rt Oeta Transfer
Acknowledge lOT ACKI

•

..

I
Terminate Output Transfer
11 Asart O..,ice Transfer
Complete IOTCI
21 Negate 'iJ6!' and LOS
31 Negate AS. AcK and OTC
41 Remove Data from O. - Ou
5) Set Rm to Read
I
T.rminate Cycle
11 Negate OTACK

,

.~

Start Next Cycle

Figure 18 Word Write Cycle Flowchart HMCS68000 Type Device

III

ClK

Ae-A23
Do-015

XOO-XOI5

liAS
AS

•

ODS

ADDRESS OUT DATA IN ADDRESS OUT

--:un

VH
==:;n~~1

lnun>

.J
.J

to
to

,n,n

m .JJ

..

----lJ1l11

P11

llJ1)-

m..J]

m m

\\\

R.W

DATA OUT

YIlI. mz
lmm----lJ1m
m.--1JJ

'1lll
-::::JIlr--,
II

Dual Addressing Mode with 8 Bit Device as Destination (Read-Write Cycles)

DMAC (MASTERI

HMCS6800 DniCI

Initiate Cycle
1) Start a normal Read or Write
Cycle
2) Monitor Enable until it is low
3) Assert Acknowledge lACK)

I

I

'1

Transfer Data
11 Wait until Enable is ective
21 Transfer the Data

II·

II

..
..
iii

~

.
~

I

I
Terminate Cycle

~

1) The

master waits until Enable

goes low.
2) Assert Device Transfer Complete

(OTCI
(On a Read cycle the
data is latched as clock goes low
when l5TC is asserted.)
3) Negate ii$. UOS. LOS. ACK
and

l5TC

I

Start Next Cycle

Figure 23 HMCS6800 Cycle Flowchart

~

•

.
<1i

:'"

eHITACHI

21

I"

•
H068450-4.H068450·6.H068450·8----------------------eLK

"--Au

0" - 0 ••

xo,,-xo ..
UAS

As
UOS

i:DS

R'W
OWN

n

\\

OOIR

o

DiiEN
HIBYTE

5tACK

OTC
ffi

o

\\

ACK
INIE)
CLK

(NOTESI

11
21
31
41
51

The DMAC should latch the data during clock 19.
The I~ should allow back to back operations on successive e pulses is possible.
The ACK low to E high time should be at least 250 ns worst case.
The clock reference shown above is the OMAC clock.
The e clock duty cycle shown above is an example. A 40% duty cycle is acceptable (4 UP. 6 down lilce HD680001.
The E clock must be low for a minimum of 5 clock cycles.

Figure 24 6800 Compatible Dual Addressing Mode (Read Cycle)

lIUUUl

10· 11 12 1314 15 16 1718 19 2021 22 23 24 2526 27 :!8

-----rr:.:

-----~~---------------------(::
DATA OUT
AOO OUT

/I

\~\

________________________________________________________

~U---

\\

rr-

o

~

I

iIII

\\

rr~-

l

9 10111213141516171819202122232425262728

- - - - - - - - - S v n c on

m

W T f t e - - - -_ _

to 6800 DevIce

Figure 25 6800 Compatible Dual Addressing Mode (Write Cycle)

22

CHITACHI

•

•
•
•
•

-----------------------H0684S0-4.H0684S0-6.H0684S0-8
An E..mple of • Dual Add,•• T ransf.,

In this mode. a data transfer from the source (memory) iI
done acc:ordina to the 6th row of Table 2, since the port . of the memory is always 16·bits. A data transfer to the destiration (device) is done ICCOrdina to the 3rd row of Table 2.
Table 3 shows the data transfer sequence.
The memory map of this example is shown in Table 4. Tbe
operand consists of BYTE A through BYTE D in memory
of Table 4. Prior to the tnnsfer, MAlt and DAR are set to
00000o 12 and 00000 108 respectively. The operand is transferred to the 8 bit port device accordina to the order of transfer
number in Table 3.

This section contains an example of a dual address transfer
using Table 7 of Dual-Address Sequencing. The table is reproduced here as Table 2. The transfer mode of this example is the
follow1ng:
I. [)evice Port size =8 bits
2. Operand size =Long Word (32 bits)
3. Memory to [)evice Transfer
4. Source (Memory) Counts up, Destination (Device) Counts

Down

S. Memory Transfer Counter =2

•

•

Table 2 Dual-Address Sequencing (Table 7)
Row No.

Port Size

1

8

2

8

!

,

LONG

4

16

I

BYTE

5

16

i

WORD

I

:ID

I

16

I

BYTE

WORD

II

'])

Address Increment

I

+

.

-

A

i

+2

0

-2

A.A+2

!i

+4

0

-2

!

+8

0

-8
-10

I

+P

0

-P

+2

0

-2

+4

0

Operand Part Addresses

,

i,:

8

i
I

Part Size

BYTE

.'il

•

Operand Size

I

BYTE

I

BYTE
-4

i

PACK

!

i
i

I

A, A+2, A+4, A+6
-3 -5 -7 -8

i

A

I

WORD

LONG

I

,

A

I

WORD
-2

I

I

!

A,A+2
-1 -6

-9

I

-4

Table 3 An Example of a Data Transfer for One Operand
SRC: Source (Memory), DST Destination (Device). HR: Holding Register (DMAC Internal Reg.)
Transfer
No.

II

.
.

0

-,

HR -+DST

2
I

3

WORD
-2

00000012

SRC-+ HR

I

BYTE
00000108
-4
-3 II

i HR -+ DST

0000010A

BYTE

-5

-4

,!,

00000014
46

WORD
·2

i

I

4

SRC-+ HR

,

5

.
.
..
..

DMAC Registers after Transfer

Data Size
on Bus

Address
Output

Data Transfer

6

6'

HR

~

DST

HR -+ DST

0000010E

48

I
I

DAR
00000108

00000014

00000108

00000014

0000010A

00000014
00000016
-9

OOQOO10C
4'0 i
0000010C
1
!,

00000016

0000010E

00000016

00000110

00000016

00000110

!

i
,

Comment

MAR
00000012

Initial Register Setting
Higher order 16 bits of operand is
fetched.
I

I

-'0

Higher order 16 bits of operand is
transferred.
Lower order 16 bits of operand is
fetched
Lower order 16 bits of operand is
transferred.
MAR, DAR are pointing the next
operand addresses when the
transfer is complete.

Mode: Port size = 8, Operand size = Long Word, Memory to Device. Soun:a (Memory) Counts Up, Destination (Devicel Counts Down

eHITACHI

23

H068450-4.H068450-6,H068450-8----------------------Tlble 4
ADDRESS

I

00000010
00000012
00000014

BYTE A
-1
BYTE C

-6

ADDRESS

ADDRESS

I

00000011

00000106

T BYTE -1B

00000013

00000108

I

00000015

0000010A

00000017

0000010C

-5
BYTE C
-7

0000010E

BYTE 0

-

BYTE 0

-6

I

00000016

Memory Mlp for the EXlmple of the Dlt. Trlnsfer

I
Source (Memory)

BYTE A
-3
BYTE B

-8

00000110

I

00000107

I
I

00000109
0000010B

I

00000100

I

000001 OF

I

00000111

I

Destination ([)evice)

SINGLE ADDRESSING MODE
Implicitly addressed devices do not require addressing of
data register before data may be transferred. Transfers between
memory and these devices are controlled by the request/acknowledge protocol. Such peripherals require only one bus
cycle to transfer data between themselves and memory, and the
DMAC internal holding register is not used. Because only the
memory is addressed during a data transfer, this protocol is
also called single-address.
Device with ACK Transfers
Under this protocol, the device is not explicitly addressed and
communication is performed with a two signal request/acknowledge handshake. When a request is generated using the request

11

61

.
i

Memory

DMAC

2)
31
41
51

method programmed in the control :registers, the DMAC obtains
the bus and responds with acknowledge. The DMAC asserts
all HMCS68000 bus control signa!s needed for the transfer.
When the transfer is from memory to a device, data is valid
when DTACK is asserted and remains valid until the data
strobes are negated. The assertion of DTC from the DMAC may
be used to latch the data, as the data strobes are not removed
until 1/2 clock-after the assertion ofUTC.
When the transfer is from devioe to memory, data must be
valid on the HMCS68000 bus befom the DMAC asserts the data
strobes. The data strobes are a5selted one clock period after
ACK is asserted. Further defutition IDf this protocol is explained
in Figures 26, 27 and timing diagrams in Figures 28 and 29.

AddI'HS Memory
Set R IW to Read
Place AddI'HS on A, - Au
Place Function Codes on FC. - FC.
Assen AddI'HS Strobe (n)
Assen Upper Data Strobe (Ufim
and Lo_r Qata Strobe (05m
L'_ _(~CK)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I
Assen Acknowledge
Pre_nt Oata
1) Decode Address
21 Place Data on O. - 0 ..
31 Assert Data Transfer Acknowledge
(OTACKI

i

II

,

ill

Acquire~

11 Load Data
i

Terminate Transfer
11 Assert Device Transfer Complete
(OTC)
2) Negate Ui5S andi:'6S
31 Negate AS, ACK and OTC

,

I

Terminate Cycle
11 Negate OTACK

,

Start Next AYde

Figure 26 Word from Memory to Device with ACK

24

eHITACHI

•
•

-----------------------HD68450·4.HD68450·8.HD88450·8
OMAC
Addre. Memory
11 Piece Addre. on AI - An
21 PI-=- Function CocIet on Fe. - FC.
31 A_" Add,.. Strobl (All
41 Set Rill to Write
51 At.n Acknowtedtl (ml

I~--------------------------------------------------------~I

•

Pl'ftInt Oau

11 PI-=- Oau on O. - Oil

I

I

Enabla Data
11 Assen Upper Data Strobe (0511

,

and Lo_r Oau Strobe (roil

•

•

I

AcceptOau
11 Dec:oc» Address
21 Load Data
31 ~ata Transfer Acknowledge
(OTACK)

I

Tarminate Transfer
11 Allen Device Trensfer Complete (OTCI
2) Negate ~ Ind [OS
3) Negate~.

ACK and ~
I

I

Tarminate Cycle
11 Negate of ACK

I

I
Sun Next Cycle

•

Figure 27 Word from Device with ACK to Memory

..~

•

ClK
FCo-FCz

-~

110

A,-A,

III

UAS
UOS

\\\
\\\

lOS

\\\

AS

'&-.JJJ

m
10
m

RW

III

)

;;===~n~ll>---1e" Data.
1) AlMrt Upper Data Strobe IUOSI
~ Lower Data Strobe I~I

I

i

Acx:ept Data
11 Decode Address
2) Load Data
31 Assert Date Transfer
Acknowledge lOT ACKI

I

I

Terminate Transfer
11 Assert Device Transfer Complete

1i5'fC1
21 Negate Dl5Sand LOS

31 Negate~. ACK and

I

otc
j
Terminate Cycle
1) Negate OT ACK

Start Next Cycle

Figure 31

Word from Device wi1h ACK and READY to Memory

:=.JJJJ
=:::::JIll

'I/O

un )

L
'IJIC.
'flIL:.
!7lC

--m..J
JJ
\\\

\)L

0/

ULJ11

J

m

CLK

12'314151617181920212223242526'~728

1234
FCc-Fez
A,-A7

Aa- AZl
XDo-XOI5

UAS
AS

1111

=:JIll)
_~lllJJlIH~U~====~/l~m~1/)---

\\\

ill
\~ll~

orr-

______________~n,-

OWN

HIBYTE

OT£K

~(REAOY)

fTr--~\\:::\====::;:;:;:-__~nr

iii

1JLJLr-

..

=--'1J~~__\~\\~:::::;;:;-------A;!:,- _ _ _-......
ffiw_ _ _ _.LlJa,r____________~~\~==~m-~~________~\~\\~========~--~Izr-

OTC
ACK

.
i

ODIR
OBEN

w-_______________

nr-

~w

L

elK

i

II
~
i

10111213 ~4'5161718192021 22232425262728

INOTES)

----Memory to DeVIce
DeVIce to Memory-----Byte from Do - D1
Byte from Oa- 0'5
11 With the exception of the notes below. these cycles are identical to the normal single addressing mode cych!S. See the comments on
the 8 bit single addressing mode transfer.
21 In the Memory to Device transfer only. the READY (PeL) line is used as a "second DTACK" i.e. both REJ~DY and DT ACK are
reQuired to terminate the cycle.
31 In the Device to Memory transfer. the READY input is used to delay the assertion of the data strobes. Onc'~ READY is detected.
the data strobes are asserted and DT ACK is sampled to terminate the cycle. AS is asserted at the beginning of the cycle as usual.

Figure 32 Single Addressing Mode with 8 Bit Devices as Sources and Destinations wi1h PCl Used as a READY Input (Read·Write Cycles)

28

eHITACHI

.
~

•
-----------------------H068450·4,H068450·6.H068450.8
(2) OPERANDS AND ADDRESSING
Three factors enter into how the actual data is handled:
port size. operand size and address Jequencinll·

SIZE

PORT SIZE
The OCR is used to program the device port size

The operand size is the number of bits of data to be tramferred to honor a single request. Multiple bus cycles may be
required to transfer the operand through the device port. A
byte operand consists of 8 bits of data, a word operand consists
of 16 bits of data, a long word operand consists of 32 bits of
data. The transfer counter counts the number of operands
transferred.
For single·address operations, the port size and the operand
size must be the same. 68000 and 6800 type devices may not
use byte operands when the port size is 16 bits and the request
generation method is the request pin. (REQG = 10 or 11)

-~

DPS

Operand Size
00 Byte
01 Word
10 Long word
II (undefmed, reserved)

Device Port Size
o 8 bit port
1 ,6 bit port

The port size is the number of bits of data which the device
can transfer in a single bus cycle. During a DMAC bus cycle,
a 16-bit port transfers 16 bits of data on Do -D 15 • while an
8·bit port transfers 8 bits of data. either on Do - D7 or on Ds
..... ~ s. The memory is always assumed to have a port size of 16.
OPERAND SIZE
OCR is used to program the operand size.

Table 5 Operation Combinations
Addressing

•

68000,6800
68000,6800
68000,6800
with AaON£ line while the
device was being acknowledged. This bit is cleared only by
writing the channel status register or resetting the DMAC.
ERR
This bit is used to report the occurrence of error conditions.
It is set if any errors have been signaled. This bit is cleared only
by writing the channel status register or resetting the DMAC.
ACT
This is the channel active bit. It is asserted after the channel
has been started. The bit remains set until the channel operation
terminates. This bit is unaffected by write operations.

C!)HITACHI

31

•

H0684S0-4.H0684S0-6.H0684S0-8-----------------------

~

the same priority scheme defmed for channel operations.
The interrupt vector returned 10 the MPU comes from
either the normal or the error intterrupt Yector register. The
normal interrupt register is used urness the ERR bit of CSR is
let. in which case the mor int~mJPt vector register is used.
The content of the interrupt vector reper is placed on Do 0.,. and DTACK. is asserted to ind.icate that the vector is on the
data bus. If • reset bus exception tXc:un. all interrupt vector
registers are Jet to $OF (binary 0000 1111), the value of the
uninitialized interrupt vector.

(2) INTERRUPTS
The (NT bit of the CCR determines it an interrupt can be
generated. The interrupt request II pnerated if INT is let and
the bits COC or BTC are let in the CSR or the PCT bit is let
and the PCL line is programmed to be an interrupt input.
If a channel has an interrupt ~. the DMAC makes an
interrupt request by asserting the IRQ output. If the DMAC
has an interrupt request pending. and receives an ~ from
the MPU the DMAC provides an intenupt vector. If multiple
channels have interrupt requests pending. the determination
of which channel presents its interrupt vector is made using

..

~

L
•

Sl.I1J1j---

CLK

1 2

AI -A7

3

~

23 2~ 2S 26 27 282930 31 32

S 6

-{(

})}-

_____--.MInr______.lIJnr-

\\\
\\\

.III

RiW

____________

~nr-

\\\
~-----

OOIR
OBEN

De-DIs
0 0 -0,.

m

----.r-----

\\\

m

»------ ----~_«
---;;~~====~;;-_____)YJ»----«i({(:::=::J}))}-

c

---------~'Sn'______J~~
ClK

Jl.JlJlJ---1

2

3 4

S 6

23 24 2S 26 27 28 29 30 31 32

• MPX A.-A .. /D.-D 15 pins

Interrupt Vector Register is
(NOTES)

Ou~ut.

1) This ~cle is simi!. to the chip selec:t cycle exc:ept it is triggem by lACK. See the notes on the chip selec:t cycle.
2) lACK will be negated within one doclr. after AS is negated.
31 The clock referenced above is the CPU cloc:lt.

Figure 34 MPU lACK Cycle to OMAC

32

eHITACHI

...
,

•
•

•
il

•

----------------------HOS84S0-4.HOS84S0-S.HOS84S0-8
(3t MULTIPLE BLOCK OPERATION

LINKED CHAINING

When the memory transfer counter is exhausted. there are
further blocks to be transferred if the channel is chained and the
chain is not exhausted. The DMAC provides the remltialization
of the memory address register and the memory transfer count·
er in these cases.

CONTINUED OPERATIONS
When the memory transfer counter is exhausted and the con·
tinue bit of the CCR is set, the DMAC performs a continuation
of the channel operation. The base address, base function code,
and base transfer count registers are copied into the memory
address, memory function code, and memory transfer count
registers. The block transfer complete (BTC) bit of the CSR
is set, the continue bit is reset, and the channel begins a new
block transfer. If the memory transfer counter is loaded with
a terminal count, the count error is signaled.

ARRAY CHAINING

•

•
-~

•
•

This type of chaining uses an array in memory consisting of
memory addresses and transfer counts. Each entry in the array
is six bytes long and, consists of four bytes of address followed
by two bytes of transfer count. The beginning address of this
array is in the base address register, and the number of entries in
the array is in the base transfer counter. Before starting any
block transfers, the DMAC fetches the entry currently pointed
to by the base address register. The address information is
placed in the memory address register, and the count information is placed in the memory transfer counter. As each chaining
entry is fetched, the base transfer counter is decremented by
one. After the chaining entry is fetched, the base address
register is incremented to point the next entry. When the
base transfer counter reaches a terminal count, the chain is
exhausted, and the entry just fetched determines the last block
of the channel operation.
The memory format for supporting the Array Chaining is
shown in Figure 35. The array must start at an even address,
or the entry fetch results is an address error. If a terminal count
is loaded into the memory transfer counter, the count error
is signaled. Since the base registers may be read by the MPU,
appropriate error recovery information is available should the
DMAC encounter an error anywhere in the chain.

This type of chaining uses a list in memory consisting of
memory address, transfl!r counts. and link addresses. Each entry
in the chain list is ten bytes long. and consists of four bytes of
- memory address, two bytes of transfer count and four bytes of
link address. The address of the
entry in the list is in the
base address register. and the bue transfer counter is unUJed.
Before starting any block transfers. the DMAC fetches the
entry currently pointed to by the base address register. The
address infonnation is placed in the memory address register,
the count information is placed in the memory transfer counter •
and the link address replaces the current contents of the bue
address register. The channel then begiils a new blode transfer.
As each chaining ently is fetched, the update base address
register is examined for the terminal link which has all 32 bits
equal to zero. When the new base address is the terminal ad·
dress, the chain is exhausted, and the entry just fetched deter·
mines the last block of the channel operation.
The memory fonnat for this type of chaining is shown in
Figure 36. This type of chaining allows entries to be easily
removed or inserted without having to reorganize data within
It-te chain. Since the end of the chain is indicated by a terminal
link, the number of entries in the array need not be specif'Jed
to the DMAC. All entries in the array must start at even address,
or the entry fetch results in an address error. If a terminal count
is loaded into the memory transfer counter, the count error is
signaled. Becaused the MPU can read all of the DMAC registers,
all necessary error recovery information is available to the
operating system.

rust

Table 8 Chaining Mode Address/Count Information
Base Addr.
Register

Base TC

Completed
When

Array Chaining

BA of Array

No. of
Entries
In Array

Base Transfer
Counter - 0

linked Chaining

BA of Array

-

Chaining Mode

•
•
4I

.

•
•

GHITACHI

Pointer =0

HD68450-4.HD68450·6.HD68450·8---------------------_

Memory

Array RAM
(list)

DeYa Addr...
Base Addr...
Base Tflnsfer Count

fn
l

{

Block 0

{

Block B

o

HD68450

DMAC
aIock C

{

Block A

.
III

Figure 35 Array Chain Transfer

Memory

1

Supplies:
Device Address
Base Address

Array RAM
(list)

Block C

n
Base Address

Memory

Address A I. bytesl
MemorY

Count A 12 bylesl
LiiiKto
B •• bytes)

Memory

Address C

~

o.femory

,. {
c:

~

Block A

HD68450

DMAC

Count C
-0rrerTnlnatorl

Memory
A""rKS B
Memory

Count B
l _ to
C

n0

/

/;~~J

\\ \r~{

DeVIce

or

BlockB

..
...

Memory

Figure 36

34

linked Array Chain Transfer

•

HITACHI

..
!

•
•

•
•
.~
!

•
•

•

-----------------------H068450-4.H068450-8.H088450-S
(4) BUS EXCEnlON CONDITIONS

m

•

HALT
The balt exception causes the DMAC to complete the opention in propess and three4tate the bus. It does not rearbitrlte
for the bus until this exception is remowd. When halt is nepted, the DMAC resumes normal opention.
Refe.r to Figure 38 for more specifIC timing diagram.
BUS ERROR
The bus error exception is generated by external circuitry
to indicate the current transfer cannot be successfully c0mpleted and is to be aborted. The recognition of this exception
during a DMAC bus cycle signals the internal bus error con·
dition for the channel for which the current bus cycle is being

run.
Refer to Figure 39 for more s~ific timing diagmn.

RETRY
The retry exception causes the DMAC to terminate the
present operation and retry that operation when retry is re-

I ANYSTATE~

RESETTING
r--lALL CHANNELS

-~

•

w.u.

and thus will not honor lIlY requests UDtiJ
it is remond. Howner. the DMAC ItiD recopizes requnu.
The relenoed bus exceptions are not \lied by the DMAC, they
should not be Ulerted durina DMAC opentions, u the relUlt
may be unpredictable.

conditJoft

The DMAC has three lines (or bus exception conditions.
A priority encoder can be uled to aenerate thele Iipala. In
order to JUanntee reliable decoding, the DMAC ftrifles that
the incoming code has been stable (or two DMAC dock cycles
before acting on it. The lines are- encoded In the (oUowina
manner (0· active) .
2 10
1 1 1 - No exception condition
110-Halt
I 0 I - Bus error
1 0 0 - Retry
o I I - Relinquish bus and retry
o 1 0 - (undefmed, reserved)
o 0 I - (undefmed, reserved)
000 - Rext
These signals indicate the presence of bus exceptions. All
bus exceptions except halt are preemptory. The occurrence
of a preemptory bus exception during a DMAC bus cycle forces
the DMAC to terminate the bus cycle in an orderly manner_
The preemptory bus exception must anive prior to or in coincidence with DTACK in order to be recognized as an abnonnal
bus termination. Here coincident means meeting the same let
up requirements for the same sampling edge of the clock. The
DMAC does not generate any bus cycles if a bus exception

NON
HLT. BER. RTY. RRT

-i

IDLE MODE

~.HLTI~)

I

IDLE MODE
WAITING FOR

~

NON

~

SER

~CLEAR

~ClEAR

DMAC YIELDS BUS

I--

------DMAC OWNS BUS

REO REON

-

•
..~

NON

I RRT

TO RETRY

•
•

IDLE MODE
WAITING FOR

HLT.RRT

DMA MODE
NO ACTIVE
CYCLE

I

l

:-

NON

RRT. HLT

RRT. HLT

DMA MODE
WAITINGFOR
BEC CLEAR

~

-- - -- -

-----DMA MODE
WAITING FOR
BEC CLEAR
TO RETRY

BER

BEA. RTY
NON

BER

START
RTY

•

I

DMA MODE
US CYCLE ACTIV

DTACK. NON

1m)

NON

DTACK. HLT (i5'l'Cl

Figure 37 Bus Exception Flow Diagram

•

•

HITACHI

35

HD68450·4.HD68450·6.H068450·8----------------------JDOYed. The bua is not reUnquiahed for rearbitration and the
operation it reinitiated when retry it removed.
Refer to Fipre .-0 for more specific timing diagram.
RELINQUISH AND RETRY

The relinquish and retry exc:eption causes the DMAC to
t.hree-state all bus master controls and when the exception is
removed, rearbitrate for the bus to retry the previous operation.
Refer to Figure 4) for more specifIC timing diagram.

RESET
The relet exc:eption provides I melns of resettinl and uutializ.ing the DMAC from an external source. If the DMAC is
bus master when the reset is rec:eived. the DMAC relinquishes
the bus. Reset clean GeR. OCR. OCR. SCR. CCR. CSR. CPR.
and CER for all channels. This resets STR. CNT. ACT and the
interrupt generation bits and clean the status and error registers.
The interrupt vector registers are set to SOF. the HD68000
uninitialized interrupt vector number.

ClK
A 0 BUS
OAS
AS

UoS
lOS

JJ
JJ
JJ

RW
OWN

rrDi1t

\\

l>Bm
HIBYTE

DTACK

I

\\

--------------------~~----~---------------

---.l1J

t\U.~

_ _ _ _ _lUqr -

\\

LOr-

oTC

L~

....
l\ _______
III-

~

HALT

(BECo-BEC2)·
BGACK
BR

\\\\\\\\\\\\\\\\

..ur-

\\

..ur-

/U

------------------------~----~---------------.-----

·,I....____ Uf
.MI

- \1....______.111;1

BG
ClK

--+---- Read -----to-from Device

- - - - i - - Write----·+---

- - - Halt Asserted --'----+-• BEe. (NOTES)

BE~

to Memory

--+---- Continue

- Halt Code

The following notes refer to all bus exceptions.
_ __
11 The Bus Exception will be acted upon if it is detected INTE RNALL Y before or at the same time as OT ACK.
_
2) The Bus Exception pins must be stable for two clocks before the OMAC will take any action. In addition. if 1he BEC pins are moving
but are not stable. and a OTACK is also received. the OMAC will wait for the BEC pins to resolve (remain stable for two docks)
before terminating the cycle. If the BE'Cpins resolve to an exception code. the OMAC will act accordingly. If they resolve to the
normal mode. the OMAC will terminate if a of ACK is received and will continue normal operation.
NOTE; As long as the BEe pins are moving the OMAC will not start another cycle.
31 If possible. the OMAC should allow exceptions to be honored if they are asserted after of ACK is asserted but before the cycle has
finished terminating.
41 If a cycle is not running. the Retry and Berr exceptions will be ignored except that no bus cycles are started cIS long as anything is
detected on the BEC pins.
The following refer to the Halt exception only.
_ __
51 If halt is receMld during a cycle, it does not terminate the operation. OT A':K is still required.
61 If helt is receMld when no bus cycle is running, the OMAC will simply give up the bus if it owns it.
71 The OMAC will not attempt to fe-acquire the bus until HALT has been ~ted.

.

•

Figure 38 Halt Operation

36

eHITACHI

•
i

•
."1

iii

-----------------------H068450·4.H068450·6.H068450·8
.j!

•

elK
A 0 BUS

."1

•

UAS

il

AS

II

UOS
LOS

~

,

J
J

--'
\\\.

R.W

III

,,

Q

I

\\\
\\\

o

OWN

~

OOIR

~

(I

--.J

II

DBEN

m

\\\

-N

.
.
..
"-1

"

II

II

HIBYTE

III
OlACK

\\\
\\\

()

\\,\\\\,\\\\\\\\\~

--'

OlC

__________-MI

.'l

BERR'

Il

~w"

ACK

IJ""rg------iJU------

\\\\\\\\"'\\\\\\"'"

ClK
1

~

2

3

4

5

8

7

8

9 1011 12 13 14 15 16 17 18 19

- - - 1 - - - - Serr on Write

to Device

.

~
31 323334:353637

Ildle\. • Error,
Recovery
Cycle

OtherOlannels

01

';;j

III

..
..

• BEe. -1E'e; - Bus Error Code
•• Single and Dual Cycle Source Address Error - 24 clocks
DWlI Cycle Destination Addr_ Error - 28 clocks
(NOTES)

In the case of preemptory bus exception. the bus cycle will always terminate immediately. but normally; i.e. it will sequence off • if
a OTACK had been received. DTC will not be alerted.
2) In the case of a Berr. the DMAC will not terminate the cycle until the SEC pins " - been SUbIe in the Berr code for _least two clocks,
even if a DTACK is also received.
3) See the bus exception comments below the Halt diagram.
1)

Figure 39 Berr Operation

-~

III

..
•

•

HITACHI

37

H068450·4,H068450·e.H068450·8---------------------ClK
A,D BUS

OAS

.JJ
mrn JJ
~ --11l
AS

mm
\\\

ill

ill

RiW
~

~
DBEN

\\\

m

ill

m
HI

m

ill

\\\

u\
ill

m

~

---1l1

---1JJ'"---

•
!
ill

m

========================================:========
0/

\\\

HIBYTE
DTACK
l5Tt

m
\\\

m

\\\

\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\111

HI

m

m
\\\ m
m

,.
..
,

ClK
- - i - - - - - W r i t e - - - - + - - Bus Idle --+----Write Retry

to Device
Retry Asserted

(NOTESI

11 In the _ ~mptory bus exception. the bus cycle should always terminate irnrned~ly. but norm .. ty; i.e. it should IIquenaI
off • if • DTACK had _n rKei~
21 In the _
of • R~MAC should not tarminata the c:ycte until the BEe pins h_ been stable in title Retry c:odI for at s..t
one dock. even if • DTACK is also rec::eiwd.
31 See the bus exception commenu below the Halt d~

..
I

Figure 40 Retry Operation

..

III

III

38

eHITACHI

•
•

----------------------HD68450-4.HD68450-6.H068450-8
CLK

•

J

AiD BUS
UAS

•

AS
UDS

•

LOS

::::xw

,

~

J
J
J

\

r

\

r--'

,

,

lmm

DBEN

,--..

\\

HIBYTE
DTACK

\\

\.

/I

USSUS~i.muunny

~

"

At"K

msms~~

SGACK

I

\

r\..

UI

,

I'
\

BR

!

'-

I

0'fC

RlINQ-

I
I

,...,
, ,
I

\

---'I

~

~

I'

\\

"

I

I

~

OWN

•

",..,

I'

R/W

•

~

I

m;

•

CLK

-,.

--4----Read----oI-Other
Relinquish and Retry
Master and
Asserted
Rearbitration

Read Retry-'----

• BEC;-nc, - Relinquish.net Retry Code
(NOTES)

.

1) In the c.e~plOry bus exception. the bus cycle thould . . . , . w.nnindl immed~.Iv. but norrNIlv; i.e. it thould .-quence
off. if a OTACK hm been rKeNed.
2) In the c:.a of a Relinquish and Retry. the DMAC should not tarmiMte the cycle until the IR pins " - been stable in the Relinquish
.net Retry code for at ' - t two clocks. awn if a ~ ill allo ...-iwd.
3) See the bus exception comments below the Haft di.-m.

Figure 41

Relinquish and Retry Operation

•

eHITACHI

39

r

.

H0684S0-4.H0684S0-6.H0684S0-8---------------,------He CONTROLS

the external abort for that channel will be .nored after
a DONE input from the I/O device is receiVed during the
thannel's I/O device-to-t1'M~mory data transfer cycle.
After the DONE input. the dwmel wiU accept external
abort when the channel is properly reinitialized and is
restarted.
_ )( _

If the HEr controb are &llerted to a state that is undefmedl
reserved. this venion of the DMAC wiD enter a wait state and
resume operation when the exception is removed.

(3) ERROR CONDITIONS
When an error is signaled on a channel, all activity on that
channel is stopped. The ACT bit of the CSR is cleared. and the
COC bit is set. The ERR bit of the CSR is set, and the error
code indicated in the CER AD pending operations are cleared.
so that both the STR and CNT bits of CCR are cleared.
SOURCES OF ERRORS "
Enumerated below are the error signals and their source~.
ConfJgUration Error
A confJgUntion error is signaled if chaining is programmed
and the continue bit is also set. ConfIgUration error is signaled
if DTYP specUJes a single-address transfer, and the device port
size is not the same as the operand size. ConflgUr:ation error is
signaled if DTYP is 68000 or 6800, DPS is 16 bits, SIZE is 8
bits. and REQG is 10 or 11 (request pin). Setting an undefmed
confJgUntion will signal a confIgUration error. The undefmed
confIgUrations are: XPM =01, MAC = 11, DAC = 11, CHAIN =
01. SIZE = 11.
Operation Tuning Error
An operation timing error is signaled if an attempt is made
to continue an operation without STR being simultaneously
set or if the channel is not active. Oper:ation timing error is
signaled if an attempt to set STR is made with ACT, COCo
BTC. NPT, or ERR asserted. Operation timing error is signaled
if an attempt to write to the OCR, OCR. SCR. GCR, MAR.
DAR or MTC is made with STR or ACT asserted. Operation
timing error is signaled if an attempt to assert CNT is made
when CHAIN is 10 or 11 (chaining modes). Operation timing
error is signaled if an attempt to assert CNT is made when BTC
and ACT are asserted.
Address Error
Address error is signaled if an odd address operation is attempted with word or long word operands or if CS or lACK is
asserted while the DMAC is bus master. The address error is
asserted after the odd address is encountered. this is consistent
with the processor operation.
BusEnor
A Bus error occurred during the last bus cycle generated by
the channel.
Count Error
A count error is signaled if the memory or base transfer
count registers are initialized with terminal count. A count
error is signaled if a terminal count is encountered during continue or chain processing.
Abort
An abort error is signaled if the PCL line was confIgUred as
an abort input and made an active transition, or if the channel
operation was aborted by the SAB bit of the CCR.
Note:
When the PCL line is used as an abort input, the PeT
bit should be cleared prior to starting the channeL If the
PCT bit is set prior to the channel being started, the
DMAC will recogllize this as an external abort when the
channel is started.
When the transfer mode is set to dual addressing
mode. the transfer direction is set to I/O device to memory, and PCL signal is set to external about input mode,

40

ERROR RECOVERY PROCEDURES
If an. error occurs during a DMA transfer, appropriate information is available to the operatilllg system to allow a "soft
failure"' operation. The operating system must be able to
determine how much data was transferred, where the data was
transferred to, and what type of em.r occurred.
The information available to the operating system consists of
the present values of the Memory Address, Device Address and
Base Address Registers, the Memory Transfer and Base T~sfer Counters, and control. status, and error registers. After the
successful completion of any transfer, the memory and device
address registers points to the location of the next operand to
be transferred and the memory tnmsfer counter contains the
nwnber of operands yet to be transferred. If an error occurs
during a transfer, that transfer has not completed and the registers contain the values they had before the transfer was
attempted. If the channel oper:ation uses chaining. the Base
Address Register points to the next chain entry to be serviced,
unless the termination occurred while attempting to fetch an
entry in the chain. In that case, the Base Address Register points
to the entry being fetched.

~

~

~

~

II
II

MULTIPLE ERRORS
X
II
The DMAC wiD log the fust error encountered in the channel III
error resister. If an error is pending in the error register and
another error is encountered the second error will not be logged.
This is true in the case of an error pending and an attempt is ~
made to set the STR bit. In this C3lOC the Operation timing error ~
is not logged in the error register but the error is recognized
intemaDy and the channel is not started.

c

• CHANNEL PRIORITIES
Each channel has a priority level, determined by the contents
of the Channel Priority Register (CPR). The priority of a chan· JIll
nel is a number from 0 to 3, with 0 being the highest priority ~
level. When multiple requests are pending at the DMAC. the
channel with the highest priority receives fJJSt service. The
priority of a channel is independent of the device protocol or f"
the request mechanism for that channel. If there are several
requesting channels at the highest priority level, a round-robin
resolution is used, that is, as long .IS these channels continue to
have requests, the DMAC does oper.md transfers in rotation.
~

I.

•

..

APPLICATIONS INFORMATICIN
This section contains examples of how to interface various
1/0 devices to a HMCS68000/DMAC based system.
f"
Figure 42 shows an example of how to demultiplex the ad· -.
dress/data bus.
Figure 43 indicates the exampll~ of how to latch the data, ~
when the DMAC has two channels which operate in 6800 mode. I
Figure 44 indicates the example of inter-device connection II
in the HMCS68000 system.

eHITACHI

..
•
- - - - - - - - - - - - - - - - - - - - - - HD68450-4.HD68450-6.HD68450-8

.

Yo •

Vi<

•

1741.SOlI

!Wtii

L--:J

lAS

III

AI-AD

21

AI-A..

7...537)

Vee

•

I

0.-0.,.

....-

Vee

Hoea.50

7...52. .

ISRlII
GImI

0.-0.

E
II

741.5245

~

0.-0..

C£
Dill

OMA
CONTROlLEII

Figure 42 Required Multiplexed Data/Address Hardware for the Bus Control Logic

~

•

_T_

D.-D~

1
u
1&1

o-.-

..

.. r - - -

A4-Au

./-

Cf

r=-o-odIor

III

Ai

L---

E

I

III

_T_

o.-D~

III

o..;.

J

..--

i

A,-Au

!

III

8

./-

I

~ o-odIor
AS

liS

l......-

E

I
ACK;
~

~

~
-'

III

i r

I
III

i

I!
,

I

6E

I

II

G
74LS373

,

D. -D~ ./

..

~

III

V

ID
-CD

lQ

'1Q

r- me;
~~
~

t:.

......

M

0.--0. )
-y

D.-Oil

8US

"

CONTROL
LOGIC
rF . .,.421

AS

~

RJii
HDIIC60
DMAC

I

.... 'lYe
-

~1IlDti

.... -A ..

Figure 43 An Example of Connection with Peripheral Devices in 6800 Mode

•

HITACHI

41

HD68450-4.HD68450·6.HD68450·8----------------------

0.111 & Address

r-

r-

Do-Ol'

Aa-Au

Bus Interf.c:e

r-

..
.

r-r--

r-v

.. :!!4

§ ~ ~~i ~

----

-

OM A
Device
Control

-

---

-

"0
10

,/'-

<~~

'-

~o l~·nne,
#0

A,-A7

P'CG

I
I
I

fS
AS
,...,.....

:~~~ ~nnel
J5Cl1

Ami
ACKz

PCG

H068450

DMAC
OIInnel
#2

Decoder

l""-

I""-

,

r--

Ii
laiC

~ ~

G)

~

System
Control

§~

f:=

r-

l""-

MPU

UOS
R;W

D'TACK
ERROR
JIll

..
..

r--

.

"

A, -An

r-v-_t--- Cc:'...
lAS _____ t - - - RC'...
__

rc -~

~

rr-r-r-r-

t-t-t-t--

e

~i=~

I""I""-

I""-

D'S;

~

II

c

fAi~

k-

I""-

r--

AS
lOS
UDS
R/W
DTACK

00-0,&
R/IN
DTACK

'---

--'"

II

los

3
A.

.

AS

I""-

~

FCo-FC2

H068466'"

A,-Au

.

r-

l""-

000

-"-

-

---

j--

00-0,5

--

rrr-

iRa r-lACK t - -

Do-O"

t-t-t-t--

l""-

FCo-FCz

.

t--

l""-

3,..

--"

Memory.&
Memory Control Unit

l""-

BECo-BEC2

~

CLK

~
l""-

L.....
UO!:
R!W
DTACK

~ ~.nnel
#3

A K3
PCL3

I:~~

rt-

r-

~

A

r--

OTCJ

CPG

~I

~

..
..

68000
Peripheral

LSI

RE:S

ma
RES
00-07

_ I - t - C~;
I- reo RC''

AS ... _

.

6800
PI!ripheral LSI
R/IN

I

IPlo-IPLz

t

VPA
VMA
E

3,

r-

f--

t-t-t--

l""-

E

§=~
c...
t--

...

I""I""-

11m

ill

""-

~

"'-

'"-

Figure 44 An Example of Jnter~vice Connection in the HMCS08000 System

42

...
•

HITACHI

ill

•
Hitachi Microcomputer Device Technical Information
September, 1982

:iii

•

Revision of HD68450 Data Sheet

•
•

Content
Page
Replace the mnemonic for pin 21, "I REO" with ·'IRO".
Revise the value of "Power Dissipation" .
Before:
Revised:
I.OW typ., 1.7SW max.
lAW typ., 2.0W max.
at Ta = :5 degrees C and V IT
Revise the following items of "AC Electrical Specification".
r\o. 94 and 95 are newly added.

.I
3

..

Item

Symbol

16

OS In "High" to DDIR
"High" Impedance
OS In "High" to DBEN
"High" Impedance
Clock "High" to Data
Out Valid (MPU Read)
. OS In "High" 10 DT ACK
: "High"
Clock "High" to
Address/FC Valid
Clock "High" to Address/Fe/'
Data "High" Impedance
Address In to AS
In "Low"
AS, OS In "High" to
Address Invalid

t DSHDRZ

max
160

6MHz
min
max
140

1DSHDBZ

160

140

120

tCHDVM

240

170

130

1DSHDTH

140

130

110

tCHAV

160

140

120

t CHAZx

140

120

100

17
-~

18
21

.

34

35
94

I
.

5
5
14

35

~O

..

Revised Value (ns)

No.

4MHz
min

•

= 5.0V

95

8MHz
min

t AIASL

O'

0

0

t SIHAIV

0

0

0

max
120

Ignore indices "91" and "92" in "Figure 3. AC Electrical Waveforms-MPU ReadfWrite".
Replace index "25" with "23" in "Figure 3, AC Electrical WavefonTIs-MPU Read/Write" .
Delete the following sentence from the paragraph titled "PCl AS A..~ ABORT INPUT':
When this function has been programmed, the PCl line is only active after the channel has been
staned.
Add the following comment to "Figure 37, Bus Exception Flow Diagram":
When the DMAC is in "IDLE MODE WAITING FOR BEC CLEAR", (BER or RTY is assened'
in this state) the MPU cannot access the DMAC registers. BER or RTY must be negated before
the ~IPl' accesses the DMAC. The MPU can access the DMAC registers while HlT or RRT is
assened.
Add the following sentence after the 6th line from the top of the right column (ending with" ...
and is restarted."):
In order to detect an external abort of the above kind. the user is advised to examine the PCT
bit of the channel status register (CSR) along with the ERR bit. If the PCT bit is set and ERR bit
is reset. then he can conclude that an external abort has occured in the DONE cycle and take an
appropreate action .

III

.

HITACHI reserves the right to make changes to any products herein to unprove functioning or deSign. Although the mforma·
tion in this document has been carefully reviewed and is believed to be reliable. HITACHI does not assume any liability arising
out of the applicatIOn or use of any product or clfcuit descnbed herein; neither does It convey any license under its patent TIghts
nor the rights or others.

42

Rcplacc the conlcnt of thc 'iccllOn tltkd .. ~tUL TlPLE ERRORS" with the foJlowlO~ sentencc:
The DMAC dctects and sel"\'Ices mulllpk crro~. howcver the content of CER (channel error
register) retains the lirst error that the channel has encountered regardless of what type of
errors occur after the lirst one.
The follow 109 changc has to be made on "Figure 43 An Example of Connection with Peripheral
Devices in 6800 Modc":
The AND gate input to OE of 74LSJ73 should be changed to a NAND gate. Change "Ao - A23" to "A, - A:.1"
Change "D~ - D-" to "Do - O~~
Replace HD 68450 with HD 68000

MPU

~

..
I

MPU

(Lower left block of page)

eHITACHI
HlTACHJ.eUROPE
MONCHEN.HEADQUARTER
Hitachi Electronic Components

EuropeGmbH
Hans-Pinsel-Stra6e 3
8013 Haar b. Mundlen
• (089) 4614-0
Tetex: 5-22593
Tetefax: (089) 463151

HITACHI-UNITED KINGDOM
LONDON. HEADQUARTER
Hitacni Electronic Components

(UK) ltd.
Hitec House.
221-225 Station-Road
Harrow, Middlesex. HAl 2XL
.01·8611414
Telex: 936293
Telefax:01-8636646

HITACHI-EUROPE
DOSSELDORF
Hitachi Electronic Components
Europe GmbH
KOnigsallee 6
4000 DUsseldorf 1
:(0211)84995
Telex: 8-584536
Telefax: (0211) 324612

HITACHI-UNITED KINGDOM
STOCKHOLM
Hitachi ElectronIC Components
(UK) Ltd.
Box 1602. 16311 5panga
Hankadalsgatan 10 Kista
.. 0046-87510035
Telex: 14106 (Hitecst 5)
Telefax: OS- 7515073

HITACHI-EUROPE
. STUTTGART
Hllachi ElectronIC Components
Europe GmbH
FabrikstraBe 17
7024 Filderstadt
: (0711) 772011
Telex: 7-255267

HITACHI-EUROPE
PARIS
Hitachi Electronic Components
Europe GmbH
Bureau de Representation E,n France
95-101, Rue Charles-Michels
F-93200 Saint Denis
'3' 01 -8216015
Telex: 611387
Telefax: 01-2436997

HITACHI-EUROPE
MIlANO
Hitachi ElectronIC ~
Europe GmbH
Via B. Davanzati. 27 ~
1-20158 Milano
: 02-3763024
Telex: 320343
Telefax: 02-683730

•

A-12'82-<16.UP450

P1nled In Welt~ermany

ill

1'1

I

•
APPENDIX L

•

DATA SHEET 5385/6 SCSI CONTROLLER

•
•

•
•

•
";
I

II1II

..

.

,

•

•

•
•
Appendix CC74

•

L-1

January 1986

..
.

•.
!

.II

,.
i

II

.•

.
..
III
i

III

III

·

~

-

-

- .- ...

-. r

.

------~"

~

........ ~--.

.
...- ......

~~-

•
1

•

...~.----------.....................
NCR 5385E SCSI

•
~

Protocol Controller

...................

.~,------~

Data Sheet

..
•
•
-~

..
•

•
-",

..
•

.
Microelectronics Division, Colorado Springs

•

.- .

_.'~'_"""_

~._

. __- .,____ ____·__.___. . _r_-e__.....__._. _. . . '- ___ ____'____________
~

~

Copyright © 1985. by NCR Corportation
Dayton. Ohio
All Rights Reserved Printed In U.S.A.

~!""'

,.
II

This document contains the latest information available at the time of publication. HowElver.
NCR reserves the right to modify the contents of this material at any time. Also, a/l features.
functions and operations described herein may not be marketed by NCR in all parts otthe
world. Therefore, before using this document, consult your NCR representative or NCR oUice
for the information that is applicable and current.

Q

'~

,

.
.
..
.
.
~-

. ---

._--

-

-"",',.

"--

.

TABLE OF CONTENTS

'I

III

"

.
-

,

III

.
4

II1II

..

SECTION
PAGE
1.
GENERAL DESCRiPTION ........................................................ 3
2.
PIN DESCRIPTION .............................................................. 5
2.1
Microprocessor Interface Signals ........................................ 5
2.2
SCSI Interface Signals ................................................... 6
3.
ELECTRICAL CHARACTERISTICS ............................................... 8
4.
INTERNAL REGISTERS .......................................................... 9
4.0
General ................................................................. 9
4.1
Data Register ........................................................... 9
4.2
Command Register ...................................................... 9
4.3
Control Register ......................................................... 10
4.4
Destination 10 Register .................................................. 11
4.5
Auxiliary Status Register. ................................................ 11
4.6
10 Register .............................................................. 13
4.7
Interrupt Register. ...... '" .............................................. 14
4.8
Source 10 Register....................................................... 16
4.9
Diagnostic Status Register. .............................................. 17
4.9.1
Self-Diagnostic Status Code Summary .................................... 18
4.10
Transfer Counter ................... , .................................... 18
5.
COMMANDS .................................................................. 19
5.1
Command Format ....................................................... 19
5.2
Command Type ......................................................... 20
5.3
Invalid Command ........................................................ 21
5.4
Command Summary ..................................................... 21
5.5
Command Definitions ................................................... 22
5.5.1
Chip Reset .............................................................. 22
5.5.2
Disconnect .............................................................. 22
5.5.3
Pause ................................................................... 22
5.5.4
Set ATN ................................................................. 23
5.5.5
Message Accepted ...................................................... 23
5.5.6
Chip Disable ............................................................ 23
5.5.7
Select w/ATN ............................................................ 24
5.5.8
Select w/o ATN ................................................ , ......... 24
5.5.9
Reselect ................................................................ 25
5.5.10 Diagnostic Data Turnaround ............................................. 26
5.5.11 Receive Commands .................................................... 27
5.5.12 Send Commands ....................................................... 28
5.5.13 Transfer Info ............................................................ 29
5.5.14 Transfer Pad ........................................................... 30

II

-:{~

.

1

~
~
I

III

,

III

,

6

7.
8.

BUS INITIATED FUNCTIONS ..................................................... 31
_6.1
Selection ...... .- ........................................................ 31
6.2
Reselection .......... " ......................................... , ....... 31
INITIALiZATION ......................................................... , ....... 32
EXTERNAL CHIP TIMINGS ............................................... , ....... 33
8.1
Microprocessor Interface ........................................ , ....... 33
8.1.1
Clock ................................................................... 33
8.1.2
Reset ................................................ , ........... " ....... 33
8.1.3
MPU Write ...................................... .- ....................... 34
8.1.4
MPU Read ....................................................... , ....... 34
8.1.5
DMA Write ...................................................... , ....... 35
8.1.6
DMA Read ...................................................... , ....... 35
8.1.7
Interrupt ........................................................ , ....... 36
8.2
SCSI Interface ................................................... , ....... 37
8.2.1
Selection (Initiator) ...................................................... 37
8.2.2
Selection (Target) ........................................................ 39
8.2.3
Reselection (Initiator) .................................................... 40
8.2.4
Reselection (Target) ..................................................... 41
8.2.5
Information Transfer Phase Input (Initiator) ................................ 43
8.2.6
Information Transfer Phase Input (Target) ................................. 44
8.2.7
Information Transfer Phase Output (Initiator) .............................. 45
8.2.8
Information Transfer Output (Target) ...................................... 46
8.2.9
Bus Release From Selection (Initiator) .................................... 47
8.2.10
Bus Release From Selection (Target) ..................................... 48
8.2.11
Bus Release From Information Phase (Initiator) ........................... 49
8.2.12
Bus Release From Information Phase (Target) ............................ 50

II

•

.
!II

III
,

ill
III
III

C
III

~

.-.
I

..
III
I

:

~
II
~

I.
III
III

III
II
III

II

II

..
~

~
III

.
~

2

..
.III
III
I
I

;---- ..

-.-: ....

----

SECTION 1
GENERAL DESCRIPTION

•
.
~
•
..

The NCR SCSI Protocol Controller (SPC) is designed to accomodate the Small Computer Systems
Interface (SCSI) as defined by the ANSI X3T9.2 committee. The SPC operates in both the Initiator and
Target roles and can therefore be used in host adapter and control unit designs. This device supports
arbitration, including reselection, and is intended to be used in systems that require either open collector
or differential pair transceivers.

•

The NCR 5385E SCSI Protocol Controller communicates with the system microprocessor as a
peripheral device. The chip is controlled by reading and writing several internal registers which may be
addressed as standard or memory mapped 1/0. A 24·bit Transfer Counter and the appropriate handshake
signals accommodate large DMA transfers with minimal processor intervention. Since the NCR 5385E
Interrupts the MPU when it detects a bus condition that requires servicing, the MPU is freed from polling
or contrOlling any of the SCSI bus signals.

•

Below is a list of important features:

•
'W

SCSI INTERFACE
·Supports ANSI X3T9.2 SCSI Standard

MPU INTERFACE
·Versatile MPU Bus Interface

·
·
•
·
•
·

·
·
·
·
·

Asynchronous data transfers to 1.5 MBPS
Supports both Initiator and Target roles
Parity generation with optional checking
Supports arbitration
Controls all bus signals except Reset
Doubly·buffered Data Register

Memory or I/O mapped MPU interface
DMA or programmed I/O transfers
24·bit Internal Transfer Counter
Programmable (Re)Selection timeouts
Interrupts MPU on all bus conditions
requiring service

....

•

.
.
.
.~

1DREQ

OMA
CONTROL DACK

BSYIN
BSYOUT
SELIN
SElOUT

R
REGISTER
ADDRESSING

~

SCSI DATA BUS

",,---.,, W/PARITY

CS

4

.

U L - _......

WR
AO
AI
A2
A3

NCR

ATN

5385E

ACK
REQ

sPC

MSG

SCSI CONTROLS
W/O RESET

DATA BUS

1/0

~~~
SBEN

MASTER
SIGNALS

tBUS GATING

·11

ARB

•
tNT

1/0

C/O
MSG
ACK
REQ
ID2

C/O

~

D2
01
0(21
RESET
ATN
IGS

lITo iO' z}IO STRAP

101

iOO"
ARB

CLK
BSYIN
SELIN
INT
SBEN

CS

A0
AI

GNO
III

FIG. 1.1 FUNCTIONAL PIN GROUPINCi
3

vee
03

D4
05
D6
D7
BS'tOUT
887
SB6
SB5
SB4
SB3
882
S81

SBQ)
SSP

SELOJT

1m

WR
DREQ
TGS
DACK
A3
A2

FIG. 1.2 PINOUT

ATN
BSYIN
BSYOJT
SELIN
SElOUT

tH:Q

0::

AO<
110

0

t-

z

<.>

INTERNAL
REGISTERS

0::

w
<.>
z
w

MSG

c/o

....

A3
A2
AI
A0

LOGIC

..J
0

REQ

00<

HIGH
SPEED

WIN ARB

, ~~

Ym

'CS

CS

m

WR

T

~
en

INT
RE-

SET

SB~

SB7

,,

SBP

TGS

.........

SBEN

ARB

rrn
i02

I

,,

I

I~I~I

IGS

100

'-1"

-.

rJ

,

i soy~c~~<1 .1

~~

n

=,

,,

n

I

II

~I

L.LII

I. '...."'..'-.. .........
' _1

',

D~·D7

~00·07

II

elK
vee

1\

GNO

t.=..i

FIG. 1.3

NCR S38SE
BLOCK DIAGRAM

-":::J

r:'J

..--~

~

..-=-w ...,

.--.. .--..

W'.-cw

~

W'~

11"-"

..--.

.-.

.--.

~

-=-

----

,"' ----

---

\

,~

- --,.

---'-

I

-i

I

SECTION 2
I

PIN DESCRIPTION

•

2.1

•

ClK

16

Symmetrical square wave signal which generates internal chip timing .
Maximum frequency is 10 MHz.

RESET

4

When high (1), this signal forces the chip into a reset state. All current
operations are terminated. Internal storage elements are cleared and
self-diagnostics are performed.

00-07

3-1
47·43

.

MICROPROCESSOR INTERFACE SIGNALS

~

III
~

II
~

These signals comprise an active high data bus. It is intended that these
signals be connected to the microprocessor data bus.

INT

19

This signal is used to interrupt the microprocessor for various bus
conditions that require service. INT is set high for request and cleared
when the chip is reset or the Interrupt Register is read.

WR

30

Write pulse (active low) is used to strobe data from the data bus into an
internal register which has been selected.

RO

31

Read pulse (active low) is used to read data from an internal register
that has been selected. The contents of the register is strobed onto
the data bus.

CS

21

When low (0), this signal enables reading from or writing to the internal
register which has been selected.

II
~

II
."1

III
~
I

II
-iii

AO-A3

.-

22,23,25, 26 These signals are used in conjunction with CS, to address all the
internal registers .

OREO

29

Data request. When high (1), this signal indicates that the internal Data
Register has a byte to transfer (inputting from the SCSI bus) or needs a
byte to transfer (outputting to the SCSI bus). This signal becomes
active only if the OMA mode bit in the Command Register is on. It is
cleared when OACK becomes active.

OACK

27

Data acknowledge. When low (0), this signal resets OREO and selects
the Data Register for input or output. OACK acts as a chip select for the
Data Register when in the OMA mode. OACK and CS must never be
active at the same time.

.~

II

1
II
'l

.j
~

II

,.
II
~

II

~
II
-'I

.
·~il

5

..r
III
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ill

2.2

SCSI INTERFACE SIGNALS

100 ·102

14·12

These active low signals determine the three-bit code of the SCSI bus
10 assigned to the chip. External pullup resistors are required orny if
tied to switches or straps.

34-41, 33

Active high data bus. These signals comprise the SCSI data bus and are
intended to be connected to the external SCSI bus transceivers.

BSYIN

17

When high (1), this signal indicates to the chip that the SCSI BSY signal
is active.

BSYOUT

42

When high (1), the chip is asserting the BSY signal to the SCSI bus.

SELIN

18

When high (1), this signal indicates to the chip that the SCSI SEl signal
Is active.

SElOUT

32

When high (1), the chip Is asserting the SEl signal to the SCSI bus.

ATN

5

INITIATOR ROLE: The chip asserts this signal when the microprocessor
requests the attention condition or a parity error has bElen detected in
a byte received from the SCSI bus.
TARGET ROLE: This signal is an input which indicates the state of the
ATN signal on the SCSI bus.

ACK

10

INITIATOR ROLE: The chip asserts this signal in response to REO for
a byte transfer on the SCSI bus.
TARGET ROLE: This signal is an input which, when ac1ive, indicates a
response to the REO signal.

REO

11

INITIATOR ROLE: This signal is an input which, when active, indicates
that the Target is requesting a byte transfer on the SCSI bus.
TARGET ROLE: Asserted by the chip to request a byte transfer on the
SCSI bus.

9,8,7

INITIATOR ROLE: These signals are inputs which indic:ate the current
SCSI bus phase.
TARGET ROLE: The chip drives these signals to indic:ate the current
bus phase.

IGS

6

Initiator Group Select. When high (1), this Signal indicates to the external
SCSI drivers that the chip is controlling in the Initiator role. Its purpose
is to enable the external drivers for ATN and ACK.

TGS

28

Target Group Select. When high (1), this signal indicates to the external
SCSI drivers that the chip is contrOlling in the Target role. Its purpose
is to enable the external drivers for REO, MSG, C/O, anclllO.

SBo-SB7, SBP

MSG, CIO, I/O

6

.""
I

•
20

SCSI data Bus Enable. When low (0), this signal directly enables the
external SCSI data bus drivers.

15

Arbitration phase. When high (1), this signal enables the external
circuitry to place the 10 bit on the SCSI bus lor the Arbitration phase.

,~

•

ARB

•
.. POWER SIGNALS

•
'4

•

VCC

48

+5 V input

GND

24

Signal reference input

~

iii
~

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.:<4

..
..
'.~

.

..

.
.
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•

..
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.fill

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7

SECTION 3
ELECTRICAL CHARACTERISTICS
OPERATING CONDITIONS
PARAMETER

SYMBOL

MIN

MAX

UNITS

Supply Voltage
Supply Current
Ambient Temp.

VOO
100
TA

4.75

5.25
300
70

VOC
rnA
'C

MIN

MAX

UNITS

2.0
-0.3

5.25
0.8
10
-10

Voc
Vee
/olA

0

INPUT SIGNAL REQUIREMENTS
PARAMETER

CONDITIONS

High-level Input, V,H
Low-level Input, V,L
High-level Input Current, IIH
Low-level Input Current, IlL

VIH=5.25V
VIL=OV

OUTPUT SIGNAL REQUIREMENTS
PARAMETER

(Except SBEN , IGS, 8Qd TGS)

CONDITIONS

High-level Output Voltage, VOH
Low-level Output Voltage, VOL

.uA

VOO=4.75V @
IOH= -400..uA
VOO=4.75V @
IOL=2.0mA

MIN

MAX

2.4

0.4

-

~

-=:J

seEN, IGS, and TGS SIGNALS
PARAMETER

CONDITIONS

MIN

High-level Output Voltage, VOH

VOO=4.75V @
IOH = -400.uA
VOO=4.75V @
IOL=4.0mA

2.4

Low-level Output Voltage, VOL

.

PRELIMINARY
Notice: Thll II not a final spaclflcation.
Soma parametrIC limits.,. lubjactto change.

8

MAX

0.4

-

UNITS

:l
Vee

I

-1

•

SECTION 4
INTERNAL REGISTERS

•
•

4.0

GENERAL

The NCR SCSI Protocol Controller has a set of internal registers which are used by the microprocessor
to direct the operation of the SCSI bus. These registers are read (written) by activating CS with an address on A3-AO and then issuing a RD/(WR) pulse. They can be made to appear to a microprocessor as
standard I/O ports or as memory-mapped 110 ports depending on the external circuitry that controls
CS. The following sections describe the operation of these internal registers.
REGISTER SUMMARY
A3

A2

A1

AO

RIW

REGISTER NAME

0
0

0
1
0
1
0
1
0
1

1
1

1
1

1
1

1
1

0
0
1
1
0
0
1
1
0
0
0
1
1

RIW
RIW

0
0
0
0
0
1

0
0
0
0
1
1
1
1
0

Data Register
Command Register
Control Register
Destination 10
Auxiliary Status
10 Register
Interrupt Register
Source 10
Diagnostic Status
Transfer Counter (MSB)
Transfer Counter (2nd BYTE)
Transfer Counter (LSB)
Reserved for Testability

--I

0

•

•

•

•

4.1

•
)

1

0
1

R
R
R
R
R
RIW
RIW
RIW

RIW

DATA REGISTER

The Data Register is used to transfer SCSI commands, data, status and message bytes between the
microprocessor data bus and the SCSI bus. This is an eight-bit register which is doubly-buffered in order
to support maximum throughput. In the non-DMA mode, the microprocessor reads from (writes to) the
Data Register by activating CS with A3-AO =0000 and issuing a RD/(WR) pulse. A bit has been included
in the Auxiliary Status Register to indicate when the Data Register is full. In the DMA mode, the DMA
logic reads from (writes to) the Data Register by responding to DREQ with DACK and issuing a RD/(WR)
pulse. The SCSI bus reads from or writes to the Data Register when the chip is connected as an Initiator
or Target and the bus is in one of the Information Transfer Phases.

4_2

•

1

0

RIW

RIW

COMMAND REGISTER

The Command Register is an eight-bit register used to give commands to the SCSI chip. The microprocessor can write to (read from) the Command Register by activating CS with A3-AO = 0001 and
issuing a WR/(RD) pulse. Writing to the Command Register causes the chip to execute the command
that is written. The Command Register can be read; however, the chip resets the Command Register
when it sets an Interrupt. Therefore, one cannot guarantee that the data in the register will be correct
after loading an interrupting command or enabling selection or reselection. To be safe, a copy of the
last command issued should be stored in the microprocessor's memory. Immediate commands are not
stored.

->lJ

The contents of the Command Register are described in a later section (See page 19, COMMANDS).

9

III

""
~
4.3

,'"

CONTROL REGISTER

This eight·bit read/write register is used for enabling certain modes of operation for the! SCSI Protocol
Controller. The microprocessor reads from (writes to) the Control Register by activating CS with A3-AO
=0010 and issuing a RD (WR) pulse.

~

II

.

II
~
~
~

76543210

ill

' - - - - Select Enable
~---- Reselect Enable
'--_ _ _ _ _ Parity Enable

r-""
III
II

•I.
i

--II""
7-3

Reserved

BIT

2

Parity Enable

When the parity enable bit is a "1", the chip generates and
checks parity on all transfers on the SCSI bus. When the
parity enable bit is a "0", the chip generates but does not check
parity on bus transfers.

BIT

1

Reselect Enable

When this bit is a "1", the chip will respond to any attempt by
a Target to reselect it. When the bit is a "0", the chip will ignore
all attempts to reselect it.

BIT

0

Select Enable

When this bit is a "1", the chip will respond to altempt to select.
it as a Target. When it is a "0", the chip will ignol"e all selections.

NOTE:

.
.""
~

BIT

After being reset and completing self·diagnostics, the control register will c()ntain all zeros.

II
II
!II
~

!II

.
III

~

II,

•
!II
~

~
II
10

""~
i

-~.

I

~

4.4

III

The Destination 10 Register is an eight-bit register that is used to program the SCSI bus address of the
destination device prior to issuing a Select or Reselect command to the chip. Bits 0-2 specify the address
and bits 3-7 are always zeroes. The 10 register is written (read) by activating CS with A3-AO equal to
"0011 ,.' and then pulsing WR (RD).

DESTINATION 10 REGISTER

I

76543210

•

..
L..--L---L.---uestination 10

,

•
•

•

4.5

AUXILIARY STATUS REGISTER

The Auxiliary Status Register is an eight-bit read-only register. It contains bits which indicate the status
of the chip's operational condition. Some of these bits are used to determine the reason for interrupts.
Therefore, the Auxiliary Status Register should always be read prior to reading the Interrupt Register
when servicing interrupts. After the Interrupt Register is read, the Auxiliary Status Register bits needed
to service the interrupt may change.
The Auxiliary Status Register is read by activating CS with A3-AO
individual bits of the Auxiliary Status Register are defined below.

= 0100 and

then pulSing RD. The

•
•

76543210

I I II I 111'-1

•
N ot Used
T ransfer Counter Zero
p aused

I
I

I

I

•

,

1/o
.r
...,10
M SG
p arity Error
' - - - - - - - - - - - - - - D a t a Register Full

I

•
11

~

!

•
~

,r

~

I.

BIT

7

Data Register Full

This bit indicates the status of the Data Registm and must be
monitored by the microprocessor during non-DMA mode commands that use the Data Register. When the DMA mode bit in the
Command Register is off (0) and the command bei!ng executed is
one of Send, Receive or Transfer Info commands (r,efer to Section
5.0 page 19, COMMANDS), data is transferred to (from) the chip
by writing (reading) the Data Register. Data Register Full is set
on (1) when data is written and turned off (0) whEin data is read.
Therefore, Data _Register Full should be on before taking data
from the chip, and off when sending data to the chip.
The Data Register Full bit is always reset (to 0) at the time an
interrupting type command is loaded into the Command
Register. Therefore, when issuing such commands, the Command Register should be loaded prior to loading the Data
Register and monitoring the Data Register Full flag.

~
~

~
III

..
.
I

II

.

.
.~

BIT

6

Parity Error

When this bit is one, it indicates that the chip has detected a
parity error on a byte of data received across tt'le SCSI bus. It
can be set when the chip is executing one of the Receive
commands or the Transfer Info command (when the transfer is
an input). This bit is reset after the Interrupt Register is read.

BIT

3-5

I/O, C/O, MSG

These bits indicate the status of the SCSI I/O, C/O, and MSG
Signals at all times. They define the Information Phase type being
requested by the Target. These signals are siglnificant when
servicing interrupts and the chip is logically connected to the
bus in the Initiator role. An interrupt will occur with any phase
change. This allows the Initiator to prepare for the next phase
of data transfer. These bits are only held while INT is active.
The bits are coded as follows:

II

1/0 CIO MSG BUS PHASE
Data Out
0
0
0
1
Unspecified Info Out
0
0
1
Command
0
0
1
1
Message Out
0
Data In
1
0
0
1
Unspecified Into In
1
0
1
1
Status
0
1
1
1
Message In

..

~
~

!II

II

~

ill
~

•I.
I

~

IIII
III

.
~

i

~

~

,.

12

.
.-.

..
..
..
-"I

"I

BIT

2

Paused

When on (1), this bit indicates that the chip has aborted the
command being executed in response to the Pause command.
It Is turned off when the Interrupting type command code is
loaded into the Command Register.

- BIT

1

Transfer Counter Zero

This bit is provided to indicate the status of the 24-bit Transfer
Counter. When on (1), it indicates that the Transfer Counter is
equal to zero. It is intended to facilitate interrupt servicing.

BIT

0

Not Used

~

~
-"1

III
-~

.

NOTE:

..

4.6

I

..
..
..

The Auxiliary Status Register will contain the following pattern after a Reset and self-diagnostics: 00xxx010.
.
.

10 REGISTER

The 10 Register is an eight-bit read~nly register that indicates the logical SCSI bus address occupied by
the chip. Bit 0-2 directly reflect the logical inversion of the chip 10 input signals 100-\02. The 10 Register
is active high whereas the 10 input signals are active low. The 10 Register allows the microprocessor to
read the chip's SCSI bus address which would normally be strapped in hardware. Bits 3·7 of the 10
Register will always be zeroes. The 10 Register is read by activating CS with A3-AO == 0101 and then
pulsing RD .

76543210
\0\0\01 0 1 0 11

II

---L.I-Ll--oevice 10

L-I

..

.
'1
II

-"

13

~

.~
4.7

r-

r

INTERRUPT REGISTER

The Interrupt Register Is an eight-bit read-only register. It is used in conjunction with the Auxiliary Status
Register to determine the reason for an Interrupt condition. This register Is read by activating CS with
A3-AO = 0110 and then pulsing RD. When the Interrupt Register is read, it automatically resets itself
(after the read is complete) and enables the chip for a new interrupt condition. Since the Parity Error
- bit in the Auxiliary Status Register is reset after a read of the Interrupt Register, and sincle 110, C/O, and
MSG are only held while INT is active, the Auxiliary Status Register should always be read prior to reading
the Interrupt Register.

~
~

.~

If a Selected or Reselected interrupt occurs after issuing a command that would normally cause an
interrupt, the chip will ignore the last command issued. This allows the microprocessor to service the
Selected or Reselected interrupt prior to proceeding with the other operation. An example of this
situation is when the microprocessor issues a command to select a Target at about the same time
another Target reselects the chip. If the chip sees the reselection first, the microprocessor will receive
an Interrupt for the reselection, and the chip will ignore the Select command, which would now be invalid
since the chip is now logically connected on the SCSI bus to another device.

C
C

Individual interrupt conditions are described below. (Note: that for all cases, an interrupt condition is
on, when the corresponding bit is a one (1), and off when zero (0).)

C

.~
~

7 6 5 4 3
I

I

I

I

I

(

210
I

I

I

'~

l-

I

,--Function Complete
Bus Service
0 isconnected
S elected
Reselected
(Used for Testability)
In valid Command
" ot Used
1'1

e
r..
C
~

II

C

C
-~

~

-.~
14

c
~

I
:iI

•

BIT

7

Not Used

May be either (1) or (0).

••

BIT

6

Invalid Command

When on (1), this bit indicates that the last command loaded
into the Command Register is not valid.

BIT

5

Not Used

(Reserved for testability)

BIT

4

Reselected ..

This interrupt will be on (1) when the chip has been reselected
by another SCSI device. After setting this interrupt, the chip is
logically connected to the bus in an Initiator role and is waiting
for the Target to send REO or disconnect from the bus.

BIT

3

Selected ..

This interrupt will be on (1) whenever the chip has been selected
by another SCSI device .

•
iI

•
']j

•
.'iiI

•

.
.
.

After setting this interrupt, the chip is logically connected to
the bus in the Target role and is waiting for a command to be
loaded into the Command Register.

.~

* The chip will become selected (reselected) only if the 10 data

byte put on the SCSI bus during the Selection (Reselection)
Phase has good parity and not more than one 10 other than the
chip's own 10 is on.

. .~

I

'I

BIT

2

Disconnected

This interrupt will be set on (1) when the chip is connected to
the bus in the Initiator role and the Target disconnects or when
the chip is executing a Select or Reselect command and the
destination device does not respond before the Transfer Counter
times out.

BIT

1

Bus Service

When the chip is logically connected to the bus in the Initiator
role, this bit will be set on (1) whenever the Target sends a REO
which the chip cannot automatically handle. This happens when
the first REO for connection is received or when the chip is
executing a Transfer Info or Transfer Pad command and either
the Transfer Counter is zero or the Target changes the Information Phase type.

.
..
.~

A Bus Service interrupt may also be set if a phase change occurs
before REO is seen. This early notification will allow the Initiator
extra time to prepare for a phase change in some unbuffered
systems. (Note: that the chip may generate Bus Service
Interrupts for phases that never request transfers. This is not
an error condition, merely transitional status of 110, C/O, and MSG.)

•

If the chip is logically connected in the Target role, this bit
will be set on (1) whenever the Initiator asserts ATN. When
indicating ATN the Bus Service interrupt may occur by itself,
with a Selected interrupt, or with a Function Complete interrupt.

.
BIT

0

Function Complete

If

When this bit is on (1), it indicates that the last interrupting
command has completed. It is the normal successful completion
interrupt for Select, Reselect, Send and Receive commands
(Refer to Section 5.0 page 19, COMMANDS). During any of the
Receive commands, it is set on (1) along with the parity error
bit as soon as a parity error is detected. A Bus Service Interrupt
may also occur simultaneously with the Function Complete if
an ATN signal was activated during a Send or a Receive command.

.

The Function Complete interrupt is also generated at the end
of a Message In phase for a Transfer Info command. (See
TRANSFER INFO command, page 29 for details.)

15
If

,...

.
i

~

.

-4.8

~

..
i

SOURCE 10 REGISTER

The Source 10 Register is an eight-bit read-only register which contains the three-bit enc:oded 10 of the
last device which Selected or Reselected the chip. The following is the format of the Source 10 Register.

III
II

~

I-

"
"
II

II

--"""""--'-- Source 10
Valid

II
I

~---------IO

III

.."
The 10 Valid bit indicates that the source device placed its own 10 bit on the SCSI bus during the Selection
Phase. The SPC chip has encoded the source 10 and placed it in bits 2-0. This information remains
valid until the chip disconnects from the SCSI bus, at this time the 10 Valid bit is reset.·

II

•
"
II

II
,
II
II
II

II
II
II

ill

.

II

II
,

II.
III
,

II

~

I

II

16

~
II

!II

...
...

-

•
•
./;!IIIj

_

..
II

,

III

..
ill
~

I

III

36

..
I

ill

•
~

• 8.2

SCSI INTERFACE

'" 8.2.1

SELECTION (INITIATOR)
DESCRIPTION

MIN

tBF
tBIA(5)
tSLA
tBIBO (5)
tecD
tAD
tpc
tBID (5)

Bus Free
BSYIN low to ARB high
SElOUT high to ARB low & 10 bit Disabled
BSYIN low to BSYOUT high
Bus Clear Delay
Arbitration Delay
Priority check to SElOUT
BSYIN low to 10 bit high

385
1.2
3.2
1.2

tADV
tSI

Arbitration Data Valid to Priority Check
SElOUT to IGS

0
2.0

tlDBl
tBOBI
tBSl
tOlD

Target ID high to BSYOUT low
BSYOUT low to BSYIN low
BSYIN high to SElOUT low
SBEN active to Bus enabled

NAME

•

,.
..~-----~-----~T-~--'~:~!~~~~.~::~~
"~~>-!.8~====~~
~~k'
• 11

~

~-=:

.-__+---=2'-1 ""

,.

3

3

---

6

I

,.......5V

-----.,

"1

-08(6

6
08(51

~.'"

'7

3 --":::::.--~~--":.:~ 6

~

74L5138

2',

1

rt-!.1t.::AI=-===,JL-!.7---l~-"'->l9d~-'

,6

:7
_____ ~)

r,td' --:>

~
,,)......:':.-_--.
5

3

~'
~ L4J: ~

~b2>-..!.!.-------'

._ I.',
10

_ _ _ _ _..,

11

~;>

h l4-!

(21 74LSOO

:

~,

M;:=~---~--~:

'------,

,L. _ _ _ _ _ _ _ _ _ ...

3

·08(')

7

·08(31
08(3)

,

~

·08(21
08(21

-08(1'
OB(11
102

11'

11/31

,.

·OBIO'
OBtOI

74lS04

~"1)S87

14(),S86

·08(P'

(391585
(38)584

DBW,

(371583
(36)582
(351581
(34ISBO

·AC'"
ACt(

1331SBP

CC

a::!!

(.)~
Zcc

'"

II)

(611GS
POlACK
(5,ATN

3

r

- - - - - -- -,

·ATN

"TN

(28)TGS
(91 ... SG
(B)C D

·MSG
MSG

ml.o
-iii

•

L_________ J

("IREO
14218SVOUT
(1718SV'N
()2'SElOUT

3

,- -

--

- -., 6

P81SEUN
(20IS8EN
I 15iARB

. C/O

·VO
1/0

.
-iii

·REO
REO

,

sv

':3 ~ =.:------------:..:;
~i
41

I

6

·BSV
8SV

-.,,

6

·SEL
SEl

-"
l.!H ~

TO RESP

lOGIC

___....___4~_,2,

11L.

7

~

l

_ _ _ _ _ _ _ _ ...J

TI75165
OR
NA TIONAl3695

Figure 6.1 Suggested Interface to SCSI Differential Transceivers

29

-RST
RST

-

r--'"d

~

~

+5V

?-

(13)

10

3 AO

13

2 AI

14

~--

I A2

15

i~

10

r(e

,}1,...:/
I

12

'~3

~
2

--

la.

1m"

12

9

~II

1

2

(S)

GS

5

9~

(28 TGS

5

8/

9

II
'~
'f~

(37) SB3

S
[,,4

o

6./

(39) SBS
(381 SB4

(1/6) 74LS04

U)

(40) SB6

~~

(36) SB2

:~

(35) SBI

h

(34)

2
_4

(7) 10
(8) :10

(9)

~9

~SG

(11 REO

II

'"'12""

~

\.11
J

...

REo..

r.~4:8-,

9/

11

5

T

I

7/

13

1'4,/L'S

~ ____

1:~ __

5/

,+5V

17

2/-

I 74lS240

9
1
12

(10) ACK

2
4

(51 ATN

5

-esv

\.8

SEL

J

K.

11

RST

../

~3

...

-liCK ..

../

~S

-IITN

../

(H/2) 7438

~~

(1/41 74LS125.

__~

14

14:;';

16

~

io

.

(RESET LOGIC)
(RESET LOGIC)

I

I

;"

9:7

-------.---- .. ------

(112) 74LS240

-08(P)

2

4~6
5
If ==.J'

(18) SElIN._

L ___

I

,

L - - , r-=-:\. -/

I

J

15

I

I

- -

I
I

I

I

12
11
13
(2) 74LSI25

(\7) BSYIN.

I

-----~~----

'VI

9

I

I
I

I

-- ~--~2

I L_~__
I

12./ 8

MSG

-+-----.

I
I
I
I
I

I

(32) SELOUT

___ ... _.c..!~

-08(01

4

I

(42) BSYOUT

~~
~_

16./

2

(33) SBP • •
110..

/"

14./ 6

I

12

(1/2) 74LS125

~~3

I
I

'!~

se0

8

...

D~II

r--187~2-;

,---,-~2

(411SB7

seEN.

--08(21

~

13~ II
12
/"
(2)7438

../

...

-08(31

4-(6
5
/"
1_ 8

/

(IS) ARB

(20)

-08(41

2

"",6

(21 74LS03

(12) 102

..

/"

1~3

/

...

-08(61
-08(51

,~-<"

II

10 i""',. 8
@,.,
/

74LS138

""

1~~8

~3

5

-08(7)

2
/"
4r-\. 6

~6

~

-

II

;:v

>-()-

(14)

~

F

..---

4

fl-

3
/

---~-

19

+~

I
I

7:

13

I

NC~ ~ ~C
I
I

NC

~NC
~
L ___
~

.JI

74LS240

--11

'---11

.--.

~

11

...

.

.,. ••

..

Figure 6.2 NCR 8310 Equivalent Circuit

~

...

,.

..

.-.

••• •• •• .--. .-.

...

)

.---. .- ...

.-WI

..

1m

•

JiAi

•

~

..,:

_.1>0

--.. ,.;

__

--1Iti

•

>iJ

__

liiJ

__~

I[

.....J

Il

~

I[

._~

•

~

•

... :lI.J

__.J

ARB
SB7

(48) •
(41)

(3)

(

DB7

)

.(40)

SB6

(42) •

(4)

(

DB6

)

.(38)

SB5
SB4

(43) :
(44)

(5)
(6)

(
(

DB5
DB4

)
)

• (37)

SB3

(45) •

(7)

(

DB3

)

DB2

)

(36)

SB2

(46) •

NCR

(8)

(

• (35)
• (34)

SB1
SBO

(47) •
(1) •

8310

(9)
(10)

( DB1 )
( DBO )

• (33)

SBP

(2) •

(11)

(

DBP )

SBEN

(34) •

.. (5)

ATN

(30).

.. (10)
(6)
(28)

ACK
IGS
TGS
MSG

(26) •
(12) •
(14).
(27)

(18)
1(17)

(
(

ATN )
ACK )

C/O

(29) •

I/O
AEO

(36) •
(28)

~

U)

..!iL _

(15),
• (41)

~ (39)

NCR
5385E/86

Jl/!

(20)

.... (9)(8)
.. (7)
(11)
• (17)

.

.

.. (42)

BSYIN

(25)·

BSYOUT

(31).

• (18)

SELIN

(32)

SELOUT
ASTIN.

RSTOUT

(22)
(21)
(20)

( MSG )
( C/O)
(
110 )

1(23)

( REO)

I (16)

(

BSY )

(15)

(

SEL )

1(19)

(

AST )

(24)

(32).
(38)
(33)

1

Figure 6.3 Slngle·Ended Interface Using the NCR 8310 Driver/Receiver Chip

SCSI
BUS

-t...J

It. . ..1

It.

...
APPENDIX A
NCR 5385E/8S SCSI PROTOCOL CONTROLLER REGISTER AND
COMMAND SUMMARY

c

REGISTER SUMMARY
A3

A2

A1

AO

R/W

REGISTER NAME

0
0
0
0
0
0
0
0

0
0
0
0

0
0

0

1
1

0

1

0
0

0

1

0
0

RNI
RNI
RNI
RNI
R
R
R
R
R
R
RNI
RfW
RfW
RNI

Data Register I
Command Register
Control Register
Destination 10
Auxiliary Status
10 Register
Interrupt Register
Source 10
Data Register II·
Diagnostic Status
Transfer Counter (MSB)
Transfer Counter (2nd BYTE)
Transfer Counter (LSB)
Reserved for Testability

1

1

1
1

0

1
1

1

1

1

1

0
0
0
0

0
1

0
1

0

1

COMMAND CODE

00000
00001
00010
00011
00100
·00101
00110-00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110-11111

II

II
II

COMMAND SUMMARY

·NCR 5386 ONLY
INT = INTERRUPTING
IMM = IMMEDIATE

III

D
T

= DISCONNECTED
= CONNECTED AS A TARGET

I

= CONNECTED

AS AN INITIATOR

COMMAND

TYPE

VALID STATES

Chip Reset
Disconnect
Paused
Set ATN
Message Accepted
Chip Disable
Reserved

IMM
IMM
IMM
IMM
IMM
IMM
IMM

D,I,T
I,T
D,T
I

..

1

II

D,I,T

II

Select wi ATN
Select wlo ATN
Reselect
Diagnostic
Receive Command
Receive Data
Receive Message Out
Receive Unspecified Info Out
Send Status
Send Data
Send Message Out
Send Unspecified Info In
Transfer Info
Transfer Pad
Reserved

INT
INT
INT
INT
INT
INT
INT
INT
INT
tNT
INT
INT
INT
INT
INT

D
D.
D
D
T
T
T
T
T
T
T
T
I

II

..

.

II

..

32

L

•
APPENDIX B
INTERNAL REGISTERS

•
COMMAND REGISTER

IL-.,JI,--..lI.,JI'--L-I_ _ _ Command Code

III

o

432

FunctlOl'l Complete
L -_ _
L -_ _ _ _
L -_ _ _ _ _

Bus Service
Disconnec1ed
Sefected

Reselected

L-_ _ _ _ _ _ (Used lor Testabtfity)
L _ _ _ _ _ _ _ _ _ Invalid Command
L-_ _ _ _ _ _ _ _ _
d

Sefect WI ATN
Sefect wlO ATN
Reselect
DiagnostIC Data T umaround
Receive Command
Receive Data
Receive Message Out
Received Unspecified Inlo OUI
Send Status
Send Data
Send Message In
Send Unspecified Info In
Transler Inlo
Transler Pad

tNTERRUPT REGISTER

e

01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101

I I I Devoce 10

s

Chip Reset
Disconnec1
Pause
Set ATN
Message Accepted
Chip Disabled

0

U

00000
00001
00010
00011
00100
00101

SOURCE 10 REGISTER

7

Reserved (MUST BE A ZERO)

.

432

765

I I I I I I I I J

~

•

10 REGISTER

7 6 5 4 320

6

4

5

3

I I - 1-1-1-1

Single Byte Transler

2

0

1

I

III

L-_ _ _ _ _ _ _ _ _ _ _ _ _ OMA Mode

I

Source 10
10 Valid

CONTROL REGISTER

o

.

DIAGNOSTIC STATUS REGISTER

o

7 6 5 4 3 2
Selec1 Enable
Resetect Enable

' - - - - Parity Enable
Phase Valid on REO"
L-_ _ _ _ _ _ Reserved for

I 1-1 I I I I I I
I I I

L-_ _ _ _

SetI-diagnostic Status

Synchronized Operation"

000
001
010
011
100
101
110
111

DESTINATION 10 REGISTER

7 6 5 4 320

I 1-1-1-1-1 1I I

. I
.~

L-..J...-I
1 -------I-

DestInation 10

DiagnostIC Command Status

L
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Panty Thru Enable-

•

Successful Completion
UnconcitionaJ Branch Fail
Data Reg. Full Failed
IMia! Condtions Incorrec1
Initial Command Bits Incorrect
Diagnostic Flag Failed
Data Turnaround Failed
Not Used

001 Turnaround
010 Turnaround
011 Turnaround
lOOT umaround

AUXILIARY STATUS REGISTER

Miscompare (InitIal)
Miscompare (Final)
Good Parity

Bad Parity

Self-diagnostic Complete

Data RegIster" Full"

..

~

•

Transler Counter Zero
' -_ _ _ Paused

TRANSFER COUNTER

' - - _ _ _ 110
' - - -_ _ _ _ CID

A3

' -_ _ _ _ _ _ _ MSG
L _ _ _ _ _ _ _ _ _ Parity Error

L _ _ _ _ _ _ _ _ _ _ _ Data RegIster t Full

• NCR 5386 ONLY

33

A2

Al

AO

o
o

0
1

o

SELECTED BYTE
Most Significant Byte
Middle Byte
Least SIgnificant Byte

II

..
..
APPENDIX C
INITIATOR/TARGET ROLE FLOWCHART

INITIALIZATION

DL

DISCONNECTED
IDLE LOOP

I~
ERROR

NO

DECODE &
IMPLEMENT
OTHER HOST
ADAPTER CONTROL
COMMANDS

6

INITIATOR
SELECTS
TARGET
W/ATN

DECODE &
IMI'LEMENT
OTHER HOST
ADAPTER
COMMANDS

III

..

.
III

III
I

III

...

..
...
34

II

•
INITIATOR/TARGET ROLE FLOWCHART
.~

•
•

INITIATOR
SENDS
"IDENTIFY"
MESSAGE

..~

!

*
INITIATOR
IDLE LOOP

!If

PREPARE CHIP
AND EXTERNAL
CIRCUITRY FOR
NEXT PHASE

•

UPDATE
WORKING
POINTERS

RECEIVE
MESSAGE

.
Ii

COPY
CURRENT
POINTERS
TO SAVED
POINTERS

YES

.

DECODE
OTHER
MESSAGES

..
..
..~

..~

..

USING THE
SOURCE 10,
RETRIEVE
SAVED
POINTERS

NO

35

INITIATOR/TARGET ROLE FLOWCHART

SET-UP
NCR 5385
TO RECEIVE
MESSAGE OUT

,.

.
I

SEND
"SAVE STATE"
MESSAGE

,.
III
SAVE INITIATOR
ID & DETERMINE
IF RESELECTION
IS SUPPORTED

SET
DISCONNECT
FLAG

..
...
I

•
III

r..
36

INITIATOR/TARGET ROLE FLOWCHART (Continued)
I

•
SEND
"DISCONNECT
MESSAGE"

•
~

•
q

•
YES

•

.."
-~

II
-;1

.

TARGET
RESELECTS
INITIATOR

.
.
'1

,lii

II
- ~1

•

TARGET
SENDS
"IDENTIFY'
MESSAGE

."

•
.~

.-

NO

.
.
-11

-11

.
-cil

i

37

ISSUE
DISCONNECT
COMMAND
TO CHIP

-

.
i

•

INITIATOR/TARGET ROLE FLOWCHART (Continued)

-,~
"

I
,~

I.
,~

II

~Q

r~

ERROR

II
I

..
~

II

,.

.

II

SEND

STATUS

!

BYTE

III
~

.
II
III

l1li

I

II
II
TARGET

III

SENDS
"COMMAND
COMPLETE"

l1li

MESSAGE

II

III

_NO

I

II
III
III

.
~

-C
38

.
~

I

l1li
I
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