Xilinx Constraints Guide
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- Software Manuals
- Constraints Guide
- About This Guide
- Table of Contents
- Introduction
- Constraint Types
- Entry Strategies for Xilinx Constraints
- Timing Constraint Strategies
- Third-Party Constraints
- Xilinx Constraints
- Constraint Information
- Alphabetized List of Xilinx Constraints
- AREA_GROUP
- ASYNC_REG
- BLKNM
- BEL
- BUFG (CPLD)
- COLLAPSE
- COMPGRP
- CONFIG
- CONFIG_MODE
- COOL_CLK
- DATA_GATE
- DCI_VALUE
- Directed Routing
- DISABLE
- DRIVE
- DROP_SPEC
- ENABLE
- FAST
- FEEDBACK
- FILE
- FLOAT
- FROM-THRU-TO
- FROM-TO
- HBLKNM
- HU_SET
- IFD_DELAY_VALUE
- IBUF_DELAY_VALUE
- INREG
- IOB
- IOBDELAY
- IOSTANDARD
- KEEP
- KEEP_HIERARCHY
- KEEPER
- LOC
- LOCATE
- LOCK_PINS
- MAP
- MAXDELAY
- MAXPT
- MAXSKEW
- NODELAY
- NOREDUCE
- OFFSET
- OPEN_DRAIN
- OPT_EFFORT
- OPTIMIZE
- PERIOD
- PIN
- PRIORITY
- PROHIBIT
- PULLDOWN
- PULLUP
- PWR_MODE
- REG
- RLOC
- RLOC_ORIGIN
- RLOC_RANGE
- SAVE NET FLAG
- SCHMITT_TRIGGER
- SIM_COLLISION_CHECK
- SLEW
- SLOW
- SYSTEM_JITTER
- TEMPERATURE
- TIG
- TIMEGRP
- TIMESPEC
- TNM
- TNM_NET
- TPSYNC
- TPTHRU
- TSidentifier
- U_SET
- USE_RLOC
- USELOWSKEWLINES
- VOLTAGE
- VREF
- WIREAND
- XBLKNM