Coprocessor Instruction Set Architecture Reference Manual
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- Introduction
- Instructions Terminology and State
- Overview of the Intel® Xeon Phi Coprocessor Instruction Set Architecture Extensions
- What are vectors?
- Vector mask registers
- Understanding Intel® Xeon Phi Coprocessor Instruction Set Architecture
- Intel® Xeon Phi Coprocessor Instruction Set Architecture Vector Instructions
- Intel® Xeon Phi Coprocessor Instruction Set Architecture Vector Memory Instructions:
- Intel® Xeon Phi Coprocessor Instruction Set Architecture vector mask Instructions
- Intel® Xeon Phi Coprocessor Instruction Set Architecture New Scalar Instructions
- Intel® Xeon Phi Coprocessor Instruction Set Architecture Swizzles and Converts
- Static Rounding Mode
- Intel® Xeon Phi coprocessor Execution Environments
- Overview of the Intel® Xeon Phi Coprocessor Instruction Set Architecture Extensions
- Intel® Xeon Phi Coprocessor Instruction Set Architecture Format
- Floating-Point Environment, Memory Addressing, and Processor State
- Overview
- Denormal Flushing Control
- Extended Addressing Displacements
- Swizzle/up-conversion exceptions
- Accessing uncacheable memory
- Floating-point Notes
- Intel® Xeon Phi Coprocessor Instruction Set Architecture State Save
- Intel® Xeon Phi Coprocessor Instruction Set Architecture Processor State After Reset
- Instruction Set Reference
- Instruction Descriptions
- Vector Mask Instructions
- JKNZD - Jump near if mask is not zero
- JKZD - Jump near if mask is zero
- KAND - AND Vector Mask
- KANDN - AND NOT Vector Mask
- KANDNR - Reverse AND NOT Vector Mask
- KCONCATH - Pack and Move High Vector Mask
- KCONCATL - Pack and Move Low Vector Mask
- KEXTRACT - Extract Vector Mask From Register
- KMERGE2L1H - Swap and Merge High Element Portion and Low Portion of Vector Masks
- KMERGE2L1L - Move Low Element Portion into High Portion of Vector Mask
- KMOV - Move Vector Mask
- KNOT - Not Vector Mask
- KOR - OR Vector Masks
- KORTEST - OR Vector Mask And Set EFLAGS
- KXNOR - XNOR Vector Masks
- KXOR - XOR Vector Masks
- Vector Instructions
- VADDNPD - Add and Negate Float64 Vectors
- VADDNPS - Add and Negate Float32 Vectors
- VADDPD - Add Float64 Vectors
- VADDPS - Add Float32 Vectors
- VADDSETSPS - Add Float32 Vectors and Set Mask to Sign
- VALIGND - Align Doubleword Vectors
- VBLENDMPD - Blend Float64 Vectors using the Instruction Mask
- VBLENDMPS - Blend Float32 Vectors using the Instruction Mask
- VBROADCASTF32X4 - Broadcast 4xFloat32 Vector
- VBROADCASTF64X4 - Broadcast 4xFloat64 Vector
- VBROADCASTI32X4 - Broadcast 4xInt32 Vector
- VBROADCASTI64X4 - Broadcast 4xInt64 Vector
- VBROADCASTSD - Broadcast Float64 Vector
- VBROADCASTSS - Broadcast Float32 Vector
- VCMPPD - Compare Float64 Vectors and Set Vector Mask
- VCMPPS - Compare Float32 Vectors and Set Vector Mask
- VCVTDQ2PD - Convert Int32 Vector to Float64 Vector
- VCVTFXPNTDQ2PS - Convert Fixed Point Int32 Vector to Float32 Vector
- VCVTFXPNTPD2DQ - Convert Float64 Vector to Fixed Point Int32 Vector
- VCVTFXPNTPD2UDQ - Convert Float64 Vector to Fixed Point Uint32 Vector
- VCVTFXPNTPS2DQ - Convert Float32 Vector to Fixed Point Int32 Vector
- VCVTFXPNTPS2UDQ - Convert Float32 Vector to Fixed Point Uint32 Vector
- VCVTFXPNTUDQ2PS - Convert Fixed Point Uint32 Vector to Float32 Vector
- VCVTPD2PS - Convert Float64 Vector to Float32 Vector
- VCVTPS2PD - Convert Float32 Vector to Float64 Vector
- VCVTUDQ2PD - Convert Uint32 Vector to Float64 Vector
- VEXP223PS - Base-2 Exponential Calculation of Float32 Vector
- VFIXUPNANPD - Fix Up Special Float64 Vector Numbers With NaN Passthrough
- VFIXUPNANPS - Fix Up Special Float32 Vector Numbers With NaN Passthrough
- VFMADD132PD - Multiply Destination By Second Source and Add To First Source Float64 Vectors
- VFMADD132PS - Multiply Destination By Second Source and Add To First Source Float32 Vectors
- VFMADD213PD - Multiply First Source By Destination and Add Second Source Float64 Vectors
- VFMADD213PS - Multiply First Source By Destination and Add Second Source Float32 Vectors
- VFMADD231PD - Multiply First Source By Second Source and Add To Destination Float64 Vectors
- VFMADD231PS - Multiply First Source By Second Source and Add To Destination Float32 Vectors
- VFMADD233PS - Multiply First Source By Specially Swizzled Second Source and Add To Second Source Float32 Vectors
- VFMSUB132PD - Multiply Destination By Second Source and Subtract First Source Float64 Vectors
- VFMSUB132PS - Multiply Destination By Second Source and Subtract First Source Float32 Vectors
- VFMSUB213PD - Multiply First Source By Destination and Subtract Second Source Float64 Vectors
- VFMSUB213PS - Multiply First Source By Destination and Subtract Second Source Float32 Vectors
- VFMSUB231PD - Multiply First Source By Second Source and Subtract Destination Float64 Vectors
- VFMSUB231PS - Multiply First Source By Second Source and Subtract Destination Float32 Vectors
- VFNMADD132PD - Multiply Destination By Second Source and Subtract From First Source Float64 Vectors
- VFNMADD132PS - Multiply Destination By Second Source and Subtract From First Source Float32 Vectors
- VFNMADD213PD - Multiply First Source By Destination and Subtract From Second Source Float64 Vectors
- VFNMADD213PS - Multiply First Source By Destination and Subtract From Second Source Float32 Vectors
- VFNMADD231PD - Multiply First Source By Second Source and Subtract From Destination Float64 Vectors
- VFNMADD231PS - Multiply First Source By Second Source and Subtract From Destination Float32 Vectors
- VFNMSUB132PD - Multiply Destination By Second Source, Negate, and Subtract First Source Float64 Vectors
- VFNMSUB132PS - Multiply Destination By Second Source, Negate, and Subtract First Source Float32 Vectors
- VFNMSUB213PD - Multiply First Source By Destination, Negate, and Subtract Second Source Float64 Vectors
- VFNMSUB213PS - Multiply First Source By Destination, Negate, and Subtract Second Source Float32 Vectors
- VFNMSUB231PD - Multiply First Source By Second Source, Negate, and Subtract Destination Float64 Vectors
- VFNMSUB231PS - Multiply First Source By Second Source, Negate, and Subtract Destination Float32 Vectors
- VGATHERDPD - Gather Float64 Vector With Signed Dword Indices
- VGATHERDPS - Gather Float32 Vector With Signed Dword Indices
- VGATHERPF0DPS - Gather Prefetch Float32 Vector With Signed Dword Indices Into L1
- VGATHERPF0HINTDPD - Gather Prefetch Float64 Vector Hint With Signed Dword Indices
- VGATHERPF0HINTDPS - Gather Prefetch Float32 Vector Hint With Signed Dword Indices
- VGATHERPF1DPS - Gather Prefetch Float32 Vector With Signed Dword Indices Into L2
- VGETEXPPD - Extract Float64 Vector of Exponents from Float64 Vector
- VGETEXPPS - Extract Float32 Vector of Exponents from Float32 Vector
- VGETMANTPD - Extract Float64 Vector of Normalized Mantissas from Float64 Vector
- VGETMANTPS - Extract Float32 Vector of Normalized Mantissas from Float32 Vector
- VGMAXABSPS - Absolute Maximum of Float32 Vectors
- VGMAXPD - Maximum of Float64 Vectors
- VGMAXPS - Maximum of Float32 Vectors
- VGMINPD - Minimum of Float64 Vectors
- VGMINPS - Minimum of Float32 Vectors
- VLOADUNPACKHD - Load Unaligned High And Unpack To Doubleword Vector
- VLOADUNPACKHPD - Load Unaligned High And Unpack To Float64 Vector
- VLOADUNPACKHPS - Load Unaligned High And Unpack To Float32 Vector
- VLOADUNPACKHQ - Load Unaligned High And Unpack To Int64 Vector
- VLOADUNPACKLD - Load Unaligned Low And Unpack To Doubleword Vector
- VLOADUNPACKLPD - Load Unaligned Low And Unpack To Float64 Vector
- VLOADUNPACKLPS - Load Unaligned Low And Unpack To Float32 Vector
- VLOADUNPACKLQ - Load Unaligned Low And Unpack To Int64 Vector
- VLOG2PS - Vector Logarithm Base-2 of Float32 Vector
- VMOVAPD - Move Aligned Float64 Vector
- VMOVAPS - Move Aligned Float32 Vector
- VMOVDQA32 - Move Aligned Int32 Vector
- VMOVDQA64 - Move Aligned Int64 Vector
- VMOVNRAPD - Store Aligned Float64 Vector With No-Read Hint
- VMOVNRAPS - Store Aligned Float32 Vector With No-Read Hint
- VMOVNRNGOAPD - Non-globally Ordered Store Aligned Float64 Vector With No-Read Hint
- VMOVNRNGOAPS - Non-globally Ordered Store Aligned Float32 Vector With No-Read Hint
- VMULPD - Multiply Float64 Vectors
- VMULPS - Multiply Float32 Vectors
- VPACKSTOREHD - Pack And Store Unaligned High From Int32 Vector
- VPACKSTOREHPD - Pack And Store Unaligned High From Float64 Vector
- VPACKSTOREHPS - Pack And Store Unaligned High From Float32 Vector
- VPACKSTOREHQ - Pack And Store Unaligned High From Int64 Vector
- VPACKSTORELD - Pack and Store Unaligned Low From Int32 Vector
- VPACKSTORELPD - Pack and Store Unaligned Low From Float64 Vector
- VPACKSTORELPS - Pack and Store Unaligned Low From Float32 Vector
- VPACKSTORELQ - Pack and Store Unaligned Low From Int64 Vector
- VPADCD - Add Int32 Vectors with Carry
- VPADDD - Add Int32 Vectors
- VPADDSETCD - Add Int32 Vectors and Set Mask to Carry
- VPADDSETSD - Add Int32 Vectors and Set Mask to Sign
- VPANDD - Bitwise AND Int32 Vectors
- VPANDND - Bitwise AND NOT Int32 Vectors
- VPANDNQ - Bitwise AND NOT Int64 Vectors
- VPANDQ - Bitwise AND Int64 Vectors
- VPBLENDMD - Blend Int32 Vectors using the Instruction Mask
- VPBLENDMQ - Blend Int64 Vectors using the Instruction Mask
- VPBROADCASTD - Broadcast Int32 Vector
- VPBROADCASTQ - Broadcast Int64 Vector
- VPCMPD - Compare Int32 Vectors and Set Vector Mask
- VPCMPEQD - Compare Equal Int32 Vectors and Set Vector Mask
- VPCMPGTD - Compare Greater Than Int32 Vectors and Set Vector Mask
- VPCMPLTD - Compare Less Than Int32 Vectors and Set Vector Mask
- VPCMPUD - Compare Uint32 Vectors and Set Vector Mask
- VPERMD - Permutes Int32 Vectors
- VPERMF32X4 - Shuffle Vector Dqwords
- VPGATHERDD - Gather Int32 Vector With Signed Dword Indices
- VPGATHERDQ - Gather Int64 Vector With Signed Dword Indices
- VPMADD231D - Multiply First Source By Second Source and Add To Destination Int32 Vectors
- VPMADD233D - Multiply First Source By Specially Swizzled Second Source and Add To Second Source Int32 Vectors
- VPMAXSD - Maximum of Int32 Vectors
- VPMAXUD - Maximum of Uint32 Vectors
- VPMINSD - Minimum of Int32 Vectors
- VPMINUD - Minimum of Uint32 Vectors
- VPMULHD - Multiply Int32 Vectors And Store High Result
- VPMULHUD - Multiply Uint32 Vectors And Store High Result
- VPMULLD - Multiply Int32 Vectors And Store Low Result
- VPORD - Bitwise OR Int32 Vectors
- VPORQ - Bitwise OR Int64 Vectors
- VPSBBD - Subtract Int32 Vectors with Borrow
- VPSBBRD - Reverse Subtract Int32 Vectors with Borrow
- VPSCATTERDD - Scatter Int32 Vector With Signed Dword Indices
- VPSCATTERDQ - Scatter Int64 Vector With Signed Dword Indices
- VPSHUFD - Shuffle Vector Doublewords
- VPSLLD - Shift Int32 Vector Immediate Left Logical
- VPSLLVD - Shift Int32 Vector Left Logical
- VPSRAD - Shift Int32 Vector Immediate Right Arithmetic
- VPSRAVD - Shift Int32 Vector Right Arithmetic
- VPSRLD - Shift Int32 Vector Immediate Right Logical
- VPSRLVD - Shift Int32 Vector Right Logical
- VPSUBD - Subtract Int32 Vectors
- VPSUBRD - Reverse Subtract Int32 Vectors
- VPSUBRSETBD - Reverse Subtract Int32 Vectors and Set Borrow
- VPSUBSETBD - Subtract Int32 Vectors and Set Borrow
- VPTESTMD - Logical AND Int32 Vectors and Set Vector Mask
- VPXORD - Bitwise XOR Int32 Vectors
- VPXORQ - Bitwise XOR Int64 Vectors
- VRCP23PS - Reciprocal of Float32 Vector
- VRNDFXPNTPD - Round Float64 Vector
- VRNDFXPNTPS - Round Float32 Vector
- VRSQRT23PS - Vector Reciprocal Square Root of Float32 Vector
- VSCALEPS - Scale Float32 Vectors
- VSCATTERDPD - Scatter Float64 Vector With Signed Dword Indices
- VSCATTERDPS - Scatter Float32 Vector With Signed Dword Indices
- VSCATTERPF0DPS - Scatter Prefetch Float32 Vector With Signed Dword Indices Into L1
- VSCATTERPF0HINTDPD - Scatter Prefetch Float64 Vector Hint With Signed Dword Indices
- VSCATTERPF0HINTDPS - Scatter Prefetch Float32 Vector Hint With Signed Dword Indices
- VSCATTERPF1DPS - Scatter Prefetch Float32 Vector With Signed Dword Indices Into L2
- VSUBPD - Subtract Float64 Vectors
- VSUBPS - Subtract Float32 Vectors
- VSUBRPD - Reverse Subtract Float64 Vectors
- VSUBRPS - Reverse Subtract Float32 Vectors
- Scalar Instruction Descriptions
- CLEVICT0 - Evict L1 line
- CLEVICT1 - Evict L2 line
- DELAY - Stall Thread
- LZCNT - Leading Zero Count
- POPCNT - Return the Count of Number of Bits Set to 1
- SPFLT - Set performance monitor filtering mask
- TZCNT - Trailing Zero Count
- TZCNTI - Initialized Trailing Zero Count
- VPREFETCH0 - Prefetch memory line using T0 hint
- VPREFETCH1 - Prefetch memory line using T1 hint
- VPREFETCH2 - Prefetch memory line using T2 hint
- VPREFETCHE0 - Prefetch memory line using T0 hint, with intent to write
- VPREFETCHE1 - Prefetch memory line using T1 hint, with intent to write
- VPREFETCHE2 - Prefetch memory line using T2 hint, with intent to write
- VPREFETCHENTA - Prefetch memory line using NTA hint, with intent to write
- VPREFETCHNTA - Prefetch memory line using NTA hint
- Intel® Xeon Phi coprocessor 64 bit Mode Scalar Instruction Support
- 64 bit Mode General-Purpose and X87 Instructions
- Intel® Xeon Phi coprocessor 64 bit Mode Limitations
- LDMXCSR - Load MXCSR Register
- FXRSTOR - Restore x87 FPU and MXCSR State
- FXSAVE - Save x87 FPU and MXCSR State
- RDPMC - Read Performance-Monitoring Counters
- STMXCSR - Store MXCSR Register
- CPUID - CPUID Identification
- Floating-Point Exception Summary
- Instruction Attributes and Categories
- Conversion Instruction Families
- Df32 Family of Instructions
- Df64 Family of Instructions
- Di32 Family of Instructions
- Di64 Family of Instructions
- Sf32 Family of Instructions
- Sf64 Family of Instructions
- Si32 Family of Instructions
- Si64 Family of Instructions
- Uf32 Family of Instructions
- Uf64 Family of Instructions
- Ui32 Family of Instructions
- Ui64 Family of Instructions
- Conversion Instruction Families
- Non-faulting Undefined Opcodes
- General Templates
- Mask Operation Templates
- Mask m0 - Template
- Mask m1 - Template
- Mask m2 - Template
- Mask m3 - Template
- Mask m4 - Template
- Mask m5 - Template
- Vector Operation Templates
- Vector v0 - Template
- Vector v1 - Template
- Vector v10 - Template
- Vector v11 - Template
- Vector v2 - Template
- Vector v3 - Template
- Vector v4 - Template
- Vector v5 - Template
- Vector v6 - Template
- Vector v7 - Template
- Vector v8 - Template
- Vector v9 - Template
- Scalar Operation Templates
- Scalar s0 - Template
- Scalar s1 - Template