ARM® Cortex®‑M3 Processor Technical Reference Manual Cortex M3
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- ARM® Cortex®‑M3 Processor Technical Reference Manual
- Contents
- Preface
- 1 : Introduction
- 2 : Functional Description
- 3 : Programmers Model
- 4 : System Control
- 5 : Memory Protection Unit
- 6 : Nested Vectored Interrupt Controller
- 7 : Debug
- 8 : Data Watchpoint and Trace Unit
- 9 : Instrumentation Trace Macrocell Unit
- 10 : Embedded Trace Macrocell
- 10.1 : About the ETM
- 10.2 : ETM functional description
- 10.3 : ETM Programmers model
- 10.3.1 : Modes of operation and execution
- 10.3.2 : ETM register summary table
- 10.3.3 : Main Control Register, ETMCR
- 10.3.4 : Configuration Code Register, ETMCCR
- 10.3.5 : System Configuration Register, ETMSCR
- 10.3.6 : TraceEnable Control 1 Register, ETMTECR1 characteristics
- 10.3.7 : ID Register, ETMIDR characteristics
- 10.3.8 : Configuration Code Extension Register, ETMCCER characteristics
- 10.3.9 : TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
- 10.3.10 : Device Power-Down Status Register, ETMPDSR
- 10.3.11 : Integration Test Miscellaneous Inputs, ITMISCIN
- 10.3.12 : Integration Test Trigger Out, ITTRIGOUT
- 10.3.13 : ETM Integration Test ATB Control 2, ETM_ITATBCTR2
- 10.3.14 : ETM Integration Test ATB Control 0, ETM_ITATBCTR0
- 11 : Trace Port Interface Unit
- 11.1 : About the TPIU
- 11.2 : TPIU functional description
- 11.3 : TPIU programmers model
- 11.3.1 : Asynchronous Clock Prescaler Register, TPIU_ACPR
- 11.3.2 : Formatter and Flush Status Register, TPIU_FFSR
- 11.3.3 : Formatter and Flush Control Register, TPIU_FFCR
- 11.3.4 : TRIGGER
- 11.3.5 : Integration ETM Data
- 11.3.6 : ITATBCTR2
- 11.3.7 : Integration ITM Data
- 11.3.8 : ITATBCTR0
- 11.3.9 : Integration Mode Control, TPIU_ITCTRL
- 11.3.10 : TPIU_DEVID
- 11.3.11 : TPIU_DEVTYPE
- A : Revisions