DEC 10 H5EC D PDP RP10 Disk Pack Synchronizer Maintenance Manual Volume 1
DEC-10-H5EC-D PDP-10 RP10 Disk Pack Synchronizer Maintenance Manual Volume 1 DEC-10-H5EC-D PDP-10 RP10 Disk Pack Synchronizer Maintenance Manual Volume 1
User Manual: DEC-10-H5EC-D PDP-10 RP10 Disk Pack Synchronizer Maintenance Manual Volume 1
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Digital Equipment Corporation Maynard, Massachusetts PDP-10 Maintenance Manual DEC-IO-HSEC-D (1) PDP-10 RP10 DISK PACK SYNCHRONIZER MAINTENANCE MANUAL VOLUME 1 DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS 1st Edition November 1969 2nd Printing May 1970 2nd Edition November 1970 3rd Edition August 1971 Copyright © 1969, 1970, 1971 by Digital Equipment Corporation The material in this manual is for information purposes and is subject to change without notice. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC FLIP CHIP DIGITAL PDP FOCAL COMPUTER LAB CONTENTS Page CHAPTER I GENERAL INFORMATION l.l lntroduction 1-1 1.2 Specifications 1-1 1.2.1 Physical I-I 1.2.2 Environmental 1-2 1.2.3 Electrical 1-2 1.2.4 Performance 1-3 1.3 Interface Req uirements 1-3 1.3.1 1.3.2 RPIO/RPOI/02 Interface 1-3 RPIO/DFIO Interface RP I 0/1(0 Interface Disk Pack/Disk Pack Interface Equipment Supplied Reference Documents Glossary 1-5 1.3.3 1.3.4 1.4 1.5 1.6 1-5 1-6 1-8 1-8 1-8 CHAPTER 2 INSTALLATION 2.1 2-1 2.2 General Unpacking 2.2.1 Special Handling 2-1 2.2.2 Inspection 2-1 2.2.3 2.3 2.4 Power Requirements Installation Procedure 2-1 2-2 Turn-On and Checkout Procedures 2-4 2-1 CHAPTER 3 OPERATION 3.1 General 3-1 3.2 Controls and Indicators Operation 3-1 3.3 3.3.1 3.4 3.4.1 3.4.2 Loading, Unloading, and Storage of RPOIP/02P Disk Packs Programming RPO 1/02 Disk Pack Characteristics RPIO Programming 3.4.2.1 3.4.2.2 DATAO Information 3.4.2.3 CONO Information CONI Information 3.4.2.4 3-6 3-6 3-7 3-7 3-11 3-12 3-16 DATAl Information 3-17 3-18 iii CONTENTS (Cont) Page CHAPTER 4 THEORY OF OPERATION 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 4.4 4.5 4.6 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.7.6 4.8 4.8.1 4.8.2 4.8.2.1 4.8.2.2 4.8.2.3 4.8.2.4 4.8.2.5 4.8.2.6 4.8.3 4.8.4 4.9 4.9.1 4.9.2 4.9.3 4.9.4 4.9.5 4.1 0 4.1 0.1 4.11 4.11.1 4.11.2 4.11.3 4.11.4 4.11.5 4.11.6 General General Block Diagram Discussion Sequence of Operation Write Data or Read Data Write Headers and Data (Format) Local/Remote RPIO Recording Technique RPOI/02 Addressing Method RP I 0 Register Organization RP I 0 Registers Assembly Register Assembly Register Data Gate Condition Register Data Address Register Longitudinal Parity Register Shift Register RPIO Control Circuits Channel Control Data Transfer Control Read Data Write Data Write Headers and Data Clear Attentions Restore Seek I/O Bus Control RPIO Read Data Separator RPIO Counters Sector Counters Sector Counter Buffer Sector Counter Control Pulses Sector Counter Multiplexer Word Counters RPIO Comparators Header Compare and Designation Error RPIO Data Flow Starting Recognizing Headers Reading Data Writing Data Commanding the Drive Reading Multiple Sectors 4-1 4-1 4-1 4-2 4-4 4-4 4-5 4-5 4-6 4-6 4-6 4-7 4-10 4-13 4-13 4-13 4-13 4-13 4-17 4-17 4-19 4-19 4-19 4-19 4-22 4-22 4-23 4-28 4-29 4-29 4-29 4-31 4-31 4-34 4-34 4-34 4-34 4-37 4-37 4-38 4-38 4-38 iv CONTENTS (Cont) Page 4.11.7 4.11. 7.1 4.11.7.2 4.11.8 4.11.8.1 4.11.8.2 4.11.9 4.11.10 4. 11.11 4-39 4-39 4-39 4-39 4-39 4-39 4-39 4-39 4-40 Loading Words Header Words Data Words Transferring Words Write Header Write Data Writing Headers Generating Parity Terminating CHAPTER 5 MAINTENANCE 5.1 5.2 5.2.1 5.2.1.1 5.2.1.2 5.2.1.3 5.2.1.4 I 5.3 5.3.1 5.3.2 5.3.2.1 5.3.3 5.3.3.1 5.3.4 5.3.4.1 5.3.4.2 5.3.4.3 5.3.4.4 5.3.4.5 5.3.4.6 5.3.4.7 Introduction Preventive Maintenance Preventiw Maintenance Procedures Mechanical Checks Test Equipment Required Electrical Checks Electronic Checks Corrective Maintenance General Corrective Procedures Diagnostic Testing Vibration Tests Adjustment Procedures Read Data Separator Calibration General Troubleshooting Guides Disk Pack Compatibility Proper Use of C.E. Packs Search Errors Parity Errors Failure to Restore Disk Pack Reliability Test Map Limitations Cleaning 5-1 5-1 5-1 5-1 5-1 5-2 5-3 5-4 5-4 5-5 5-5 5-5 5-5 5-9 5-9 5-9 5-10 5-11 5-11 5-11 5-11 CHAPTER 6 DRAWINGS 6.1 General 6-1 v ILLUSTRA nONS Figure No. 1-1 1-2 1-3 1-4 1-5 1-6 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 * 3-13 3-14 * 3-15 4-1 4-2 4-3 4-4 4-5 4-6 * 4-7 4-8 4-9 * 4-10 * 4-11 * 4-12 4-13 * 4-14 4-15 4-16 4-17 4-18 4-19 4-20 Title Art No. DEC Type RP 10 Disk Pack Synchronizer Typical PDP-l 0 System with RPIO Disk Pack Synchronizer RPI OIDFI O/RPOI /RP02/I/O Interface RP I O/RPO 1/02 Electrical Interface RP I 0 Interface Wiring Diagram RPIO Cable Diagram RP I 0 Overall Dimensions RPI0-RPOI/RP02 Signal and Power Connections RP I 0 Controls and Indicators RPOI /RP02 Disk Pack Characteristics RPI0/RPOI/RP02 Data Control Signals RPOI/RP02 Data Format DATAO Instruction Word Format Position Instruction Word Recalibrate Instruction Word Read Data Instruction Word Write Data Instruction Word Write Header and Data Instruction Word Clear Attentions Instruction Word No Op Instruction Word DA T AI Instruction Word Format CONO Instruction Word Format CONI Instruction Word Format RP 10 General Block Diagram RP I 0 Active and Inactive Functions RP I 0 Register Organization RP I 0 Assembly Register Simplified Block Diagram RPIO Assembly Register Data Gate, Simplified Block Diagram RP I 0 Condition Register, Block Diagram RPIO Data Address Register, Block Diagram RP I 0 Longitudinal Parity Register, Block Diagram RP 10 Shift Register, Block Diagram DTC OP Decoding, Block Diagram DTC Read Data Command, Block Diagram DTC Write Data Command, Block Diagram DTC Write Headers and Data Command, Block Diagram DTC Clear Attentions Command, Block Diagram DTC Restore Command, Block Diagram Tag and Bus Line Strobe Waveforms DTC Seek Command, Block Diagram Sources of Jitter in Disk Playback VFO Startup Waveform RDS DATA WIND Waveform * * Denotes figures revised since the November 1970 printing. vi 10-0160 10-0162 10-0163 10-0177 10-0161 10-0019 10-0534 10-0165 10-0166 10-0168 10-0170 10-0169 10-0171 10-0167 10-0159 10-0108 10-0507 10-0508 10-0509 10-0511 10-0512 10-0513 10-0514 10-0515 10-0516 10-0517 10-0518 10-0519 10-0520 10-0535 10-0538 10-0537 10-0687 Page 1-1 1-2 1-4 1-4 1-6 1-7 2-4 2-5 3-1 3-8 3-9 3-10 3-12 3-12 3-13 3-13 3-14 3-15 3-15 3-16 3-17 3-17 3-19 4-2 4-3 4-7 4-9 4-10 4-11 4-14 4-15 4-16 4-18 4-18 4-20 4-20 4-21 4-21 4-22 4-22 4-24 4-25 4-25 ILLUSTRATIONS (Cont) Figure No. * 4-21 4-22 * 4-23 4-24 * 4-25 4-26 4-27 * 4-28 * 4-29 **5-1 **5-2 Art No. Title RPIO Read Data Separator, Block Diagram RDS Error Flops Waveforms Optimum Window Generation Waveforms RPIO Sector Counter, Block Diagram RPIO Sector Counter Buffer, Block Diagram RPIO Sector Counter Control Pulses, Simplified Block Diagram RPIO Sector Counter Multiplexer, Block Diagram RPIO Word Counters Block Diagram RPIO Header Compare and Designation Error, Simplified Block Diagram RDS Waveform No.1 RDS Waveform No.2 Page 10-0522 10-0523 10-0524 10-0525 10-0526 10-0527 10-0528 10-0529 4-27 4-28 4-28 4-29 4-30 4-31 4-32 4-33 10-0530 10-0688 10-0689 4-35 5-7 5-7 TABLES Table No. 1-1 1-2 1-3 1-4 1-5 2-1 3-1 4-1 5-1 5-2 5-3 5-4 5-5 6-1 Title Page RPOI/02 Features Compatible with RPIO Logic Configuration RPIOjRPOI and RP02 Interface Chart RPlO/DFlO Interface Chart RPIO/I/O Interface Chart Equipment Supplied RPOI/RP02 Power Requirements RPIO Controls and Indicators Data Transfer Control Commands Test Equipment Required Power Supply Output Checks Critical Delay Modules DFIO Voltage Margins RPIO Voltage Margins RPIO Engineering Drawings 1-3 *Denotes figures revised since the November 1970 printing. **Denotes figures added since the November 1970 printing. vii 1-5 1-5 1-6 1-8 2"2 3-2 4-36 5-2 5-2 5-3 5-3 5-4 6-1 Chapter 1 General Information 1.1 INTRODUCTION The RPlO Disk Pack Synchronizer, shown in Figure 1-1, provides the interface logic between the DFIO Data Channel and as many as eight of the DEC Type RPO I or RP02 Disk Pack Drives. The RPIO operates under control of the PDP-I a I/O Bus and, in turn, controls the RPO I or RP02 (see Figure 1-2). These units provide the PDP-I a computer with on-line auxiliary storage for between 1.28 and 40 million 36-bit words. Direct access to core memory is obtained through the DFIO Data Channel. The RPIO is housed in a 19-in. cabinet containing eight module racks. Indicator and switch panels are located on the top front of the unit. These comprise monitoring and switch register facilities for data, address, and control. The unit contains the standard margin check voltage bracket, + 10 and -15 V dc power supplies and power control, and built-in cooling fans. The RPIO is shipped complete and factory tested including all interconnecting cabling to the PDP-I a and the RPOl/02 Disk Packs. Two types are available: the RPIO-A for 60-Hz operation, and the RPIO-B for 50-Hz operation. 1.2 SPECIFICATIONS Physical, environmental, electrical, and performance specifications for the RPIO Disk Pack Synchronizer are given in the paragraphs that follow. 1.2.1 Physical Dimensions Width Height Depth Weight = 21 in. = 69 in. = 27 in. = 390 Ib Service Access Dimensions Front Rear 36 in. 36 in. Figure I-I DEC Type RPIO Disk Pack Synchronizer I-I CONSOLE PAPER TELETAPE PRINTER READER MEMORY MODULE (8,192 WORDS) - ~ MEMORY MODULE (16,384 WORDS) r- ~~ r-< INPUTI OUTPUT BUS TO OTH ER PERIPHERALS PDP-10 CENTRAL PROCESSOR r------i-----'-----, MEMORY EXT I I I I PROT. : ORDE'R : FAST I AND I CODE I MEMORY: I REL. I I I 1.. ______ 1 ______ !.. ______ J : UP TO 2 62,144 WORDS 1 MEMORY 0 MODULE PAPER TAPE PUNCH DATA CHANNEL OF to ~(CONTROLLER DISK PACK r-< RP10 H I--< r- --f~ , , : 1 1 MEMORY 0 MODULE : DISK PACK I DISK PACK J ) RP01 AND lOR RP02 , UP TO 8 UP TO 8 DEVICES ~ 10-01eo ~.~ =MC10 Figure 1-2 Typical PDP-l 0 System with RP 10 Disk Pack Synchronizer 1.2.2 Environmental The RPIO operates under normal conditions of humidity, shock, and vibration. Recommended Ambient Operating Temperature = 60° to 95°F Storage Temperature = 40° to 110°F Humidity = 20% to 80% Relative Wet Bulb = 78°F (Max) 1.2.3 Electrical Power Requirement at Line Cord 115 Vac, I-phase, 60 Hz@ 8.0A Power/Heat Dissipation = 9000W/3000 Btu/Hr Internal Power - From 4 self-contained Type 728 Power Supplies and one self-contained Type 844 Power Control. +10 Vdc -15 Vdc U nit Cable Lengths 50 ft (Max) 1-2 1.2.4 Performance Word Transfer Time When synchronizing RPO I = 30 JlS When synchronizing RP02 = 15 JlS Positioning Time Track-to-track = 20 ms Average = 50 ms Maximum = 80 ms Latency Time Average = 12.5 ms Maximum = 25 ms 1.3 INTERFACE REQUIREMENTS The RP I 0 Synchronizer is designed to interface with any of the RPO I /02 Disk Pack options listed in Table I-I. Figure 1-3 is the Interface Block Diagram for the system. A complete description of the RPO I /02 is contained in the vendor manuals for the Disk Drives. These manuals are supplied with each piece of peripheral equipment. Table 1-1 RPOl/02 Features Compatible with RPIO Logic Configuration Feature Variations Input Voltage and Frequency 208/230 Vac ± 10%, 60 Hz ± 1/2 Hz 220/380 Vac ± 10%,50 Hz ±2 Hz NOTE All drives in a given system must be driven by the same voltage and the same frequency. Recording Density (bit cell time) RPOI = 800 ns RP02 = 400 ns Number of Drives RPOI=I-8 RP02 = I - 8 NOTE May be intermixed. 1.3.1 RPlO/RPOI/02 Interface There are two cable assemblies through which the RPIO connects to the RPOI or RP02 Disk Pack (see Figures 1-4 and 1-5); these assemblies and their functions are listed in Table 1-2. The electrical specification of the RPI O/RPO 1/02 interface is shown in Figure 1-4. 1-3 MEMORY BUS DFIO DATA CHANNEL I/O BUS CHANNEL BUS I I L_ _J CHANNEL BUS TO NEXT DEVICE KAIO CENTRAL PROCESSOR I/O BUS TO NEXT DEVICE RPIO DISK PACK SYNCH RON I Z E R SIGNAL BUS CABLE UNIT BUS CABLES SIGNAL BUS CABLES RPOI/02 RPOI/02 ----- ~---.... ------ AC POWER UP TO EIGHT 10-01-62 Figure 1-3 RPIO/DFIO/RPOI/RP02/I/O Interface OF 10 DATA CHANN E L WOl2 WOl2 C"I A B L E f CABLE t I A I B #2 w -'~# u "t::~ o~ - '" ~ o ~ - It) 0 '" PDP-IO I/O BUS II G796 G796 IX) C\I ~ ";:~ ~ '" ~ ~ '" N CD CABLE #3 W250 W250 G796 G796 WB51 W851 W021 W021 '" it) It) IX) IX) ~ ~ it) It) IX) IX) ~ - '" ~ RPIO SYNCHRONIZER IX) '" ~ ~ ~ on IX) '"on ~ ~ ~ It) RP 01/02 DISK PACKS on IX) IX) w w -'''' ~II .:.Jro ~II u u 10-0163 Figure 1-4 RP lO/RPO I /02 Electrical Interface 1-4 Table 1-2 RPI0/RPOI and RP02 Interface Chart Between RPI0 Function RPOI/02 Cable Type P/R-21 13 Address and Control Bus Lines Cylinder Address Bus Lines G796-G796 P/R-22 15 Tag lines, Unit Select, Write Data, +36 Vdc in, Controlled Ground, 'Attention', Unit Selected, Ready, On-Line, Index Pulse, Sector Pulse, File Unsafe, Seek Incomplete, End of Cylinder, Read Data, Read Only, Write Current Sense. G796-G796 The RPIO feeds the Disk Pack with eight multifunction address and control bus lines, three tag lines, a unit select line, a write data line, sequence out, +5V to terminator, and controlled ground. The Disk Pack feeds the RPIO with 'attention', ready, on-line, index pulse, sector pulse, file unsafe, seek incomplete, end of cylinder, read data coax, eight cylinder address lines, read only, and selected unit sector pulse. 1.3.2 RPlO/DFI0 Interface There are three cable assemblies through which the RPIO connects to the DFIO Data Channel (see Figures 1-5 and 1-6). These assemblies and their functions are listed in Table 1-3. Table 1-3 RPIO/DFIO Interface Chart Between RPIO DFIO Function Cable Type P/R-1/2 K/L-31/32 Chan Cable No. 1 W250-W012 P/R-ll K-21 Chan Cable No.2 G796-G796 P/R-12 L-21 Chan Cable No.3 G796-G796 1.3.3 RPIO/I/O Interface There are two cable assemblies through which the RPIO connects to the PDP-lO I/O Bus (see Figures 1-5 and 1-6). These cable assemblies are listed in Table 1-4; the signals they carry are also included. 1-5 Table 1-4 RPI0/1/0 Interface Chart Between RPIO Cable Type Function I/O Bus P/R-13/ 14/17/18 Cable I lOB 00-3S W2S0-WOI2 P/R-IS/ 16/19/20 Cable 2 lOB Reset, IOBD DR SPLIT, IC lOS 03-09, DATAO, DATAl, CONO, CONI, RDIPLS, RDl DATA, PI 1-7 W2S0-WOI2 1.3.4 Disk Pack/Disk Pack Interface . Two cable assemblies run serially between all Disk Pack Units. These cables carry sequence out plus all signal and control interconnections between the RPlO and the first Disk Pack. The sequence out from the RPlO is relayed to the next drive when this drive is up to speed and is drawing its running current (not more than SA, RPO I, or 7 A, RP02). RPOI RPIO RP02 RPIO 10-0177 Figure I-S RPIO Interface Wiring Diagram 1-6 . DF10 DATA CHANNEL N ~ ~~ . Z . . w ~ " ;; ; u r W N ~ ~ • 0 • " 0 1 ~ ;; > ~ ~ ~> ~ ! 0~ ~ % u ~ o z u • ~ ~ > ~ • u ~ z c 8 0 '" '" .. ·", ! 8~ E;;: .., " ~ 2 > 0 ~ > % u u ~ ~ Z 0 u ~ ~ 0 0 ·" . : . c c u ~ ~ > 2 % z z z z % ~ ~ > ~ ~ 0 ~ 0 ~ -' e : :>c z > ~ ~ "z "z ~ c ~ ~ z ~ > ~ ~ 0 ~ '"" ~ z c z z > z z > c c ~ c% c % % ~ U ~ •8 0 u .. 0 ~ > c ~ u u u ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ u u ~ 0 •z ~ > " 0 ~ ~ 0 u u ~ ~ 0 " ~ z ~ > ~ ~ . .• . 0 ~ ~ ~ 0 " ~ ~ " > ~ c ~ ~ 0 " ~ ~ .. .. · . " .. .. .. n N z ~ ~ > ~ z ~ z 0 u > z N ~ u ~ z > z u ~ z 0 0 > c ~ c ~ ~ c z Z > % % •. 8 ~ 0 ~ ~ or > c > ~ u u ~ u u u u u • • u u u u u u u .. w 0 u u ~ % u ~ % % u u or ~ N ~ 0 ~ 0 0 0 0 0 0 0 0 0 ~ N ~ 0 0 z z z z% z% 0 % u ~ ~ c c ~ c ~ .·. % u ~ % u u u or ~ c !; W250 WOIZ lOB 00- 08 R13(W85,1 10809-17 0 lOB 00-08 PI7(W8511 ~ 10809-'7 R17(W85t1 N lOB 18-26 l.A8L!:;" P14(W851l G796 ~ osec ue A14(W8511 osec ue osec ue R18(W8511 ossc us 4 ossc us 5 ossc us 6 -H'-":.:':::"::'-'#:..:''------H-' -I+-------H-' -I+-------H-' Ie IDS 03(0)-05101 ossc us 7 -Y--------Hof Ie IDS 05111-09111 OSSC CYL ADR REG 01 W250 lOB 27- 35 Ie 108 RESET W250 } •••• w.") IOSD OR SPL IT RISlw8511 lOB OR SPLIT ... } p •• (we." Ie IDe DATAO SET I )""..." Ie lOB CONO CLEAR Ie lOB CONO SET Ie lOB OATAI CABLE #2 CABl£IIZ Ie lOB CONI RPIO DISK SYNCHRONIZER _CAIILE#3- ~I+----+---I 12B-IlJ----G~7'_i.~.'__l osec CYL ADR REG 64 OSBC SEQUENCE OUT P22 (We.21! (SHIELD GROUND) ------++-+__~ OSBC SET HEAO TAG LINE ---+l-!-tJ~ (108 ROI PULSE) osec SET CYL TAG LINE IIOB RDI OATAI OSBC CONTROLS TAG LINE RISlw8511 CXR lOB PII-7 OSSC SEL UNIT READY :.: UJ o OSBC CYL AOR REG 32 OSBC CYL ADR REG :.: ~ CY L ADR REG 04 osec CYL ADR REG 16 A19(W8511 Ie IDS OM 1i-09(1) UJ (J OSSC CYL ADR REG 08 Ie lOB OATAO CLEAR 11. 0 11. OSSC Ie IDS 03(01-0510) 0 I ossc cY L ADR REG 02 Ie rOB RESET 0 _A-_ _ _ _ _ _ _G_7 .....:.J I PI8(W95' I lOB 27-35 lOB 18-26 ..... DSRC uR 0 ---++-+~ ---~++--I N o 11. II:: ..... o 11. II:: ::c,:-_+f--I--I -----'--='-'-''---1++-+ OS BC S E L UN I T ON 1I N E "-,,"-,--:,,:.. Ie lOB OATAO CLEAR )... ... Ie lOB OATAO SfT Ie IDe CONO CLEAR , , Ie lOB CONO SET Ie lOB DATAl IC 10e CONI osec 5EL INDEX osec SEL FILE UNSAFE - - - - + + - + - - - 1 OSBC SEL UNIT SK INC ----1++-+ OSSC SEl EO CYL -----++""G7'*."""'.--1 osec SEL SEC PLS -----4J.="'--I (loe RDI PULSE) W250 A20 (W851) to-OUSt Figure 1-6 RPIO Cable Diagram 1-7 1.4 EQUIPMENT SUPPLIED Table 1-5 lists the equipment supplied with the RPIO Disk Pack Synchronizer. Table 1-5 Equipment Supplied Quantity Per Equipment 1 Description Part Type No. Synchronizer Quantity Per Equipment Description I Cable G796 to G796 C-IA-7005469-13 RPIO Part Type No. 2 Cables W250 to WOl2 D-IA-7005459-12 I Cable G796 to G796 C-IA-7005469-6 5 Cables W250 to WO 12 D-IA-7005459-24 I Cable G796 to G796 C-IA-7005469-7 2 Cables W250 to WOl2 D-IA-7005459-15 1 Cable, Grounding 1 Cable W250 to WO 12 D-IA-7005459-8 I set Spare Modules 2 Cables W250 to WO 12 D-IA-7005459-11 1 set Diagnostic Tapes MAINDEC 10-D50B MAINDEC 10-DSMA MAINDEC 10-D5NB 2 Cables G796 to G796 C-IA-7005469-10 1 ea. Maintenance Manual (2 volumes) DEC-IO-H5EB-D 1 Cable G796 to G796 1 set Engineering Drawings C-IA-7005469-2 1.5 REFERENCE DOCUMENTS The following documents supplement the information contained in this manual: PDP-IO System Reference Manual DFIO Data Channel Maintenance Manual PDP-1O Site Preparation Guide PDP-IO Interface Manual Vendor Manual for RPOljRP02 Disk Pack Drive This material is available from the nearest DEC Field Office or from: Digital Equipment Corporation Direct Mail Department 146 Main Street Maynard, Massachusetts 01754 1.6 GLOSSARY The abbreviations used throughout this manual are defined in Volume II of this manual. 1-8 Chapter 2 Installation 2.1 GENERAL This chapter contains information required for installation of the RPIO Disk Pack Synchronizer. The installation procedures are not complex because the RPIO is shipped complete and factory tested. When the equipment is received, all modules are in place and, all intra-bay cabling has been installed. The unit has been tested extensively while operating as part of a standard PDP-I 0 System. Turn-on and checkout procedures are included herein to conflfnl operation of the equipment after it has been installed. The equipment rack should be located as near as possible to the DFIO Data Channel, preferably next to the DFIO frame. Bolt the equipment rack to the main rack in four places using the hardware provided. Cable lengths and the location of the RPOI/RP02 drives are the major factors governing placement of the RPIO. 2.2 UNPACKING The following paragraphs describe the RP I 0 unpacking procedures. 2.2.1 Special Handling No special handling procedures are required for the RPIO beyond the normal care afforded any piece of scientific equipment of comparable size and weight. However, particular care should be exercised in the use of cranes or hoists to prevent damage to the unit. 2.2.2 Inspection On receipt of the equipment, inspect it for visible damage such as dents and abrasions that may have occurred in transit. Inspect the logic modules for foreign matter that may have lodged in them during shipment. Any damage should be reported immediately to both the Carrier and Digital Equipment Corporation. Check the contents of the carton with the shipping document and with Table 1-5 of this handbook. Immediately report any omissions or incorrect parts to Digital Equipment Corporation. 2.2.3 Power Requirements The RPIO is equipped with self-contained power supplies and power control. The + 10 Vdc and -IS Vdc requirements of the unit are provided by four DEC Type 728 Power Supplies and a DEC Type 844 Power Control. Modifications for accommodating either 50- or 60-Hz operation are made within the basic unit. These are designated as RPlO-A for 60-Hz and RPIO-B for 50-Hz operation. Power is supplied from an 8A, liS Vac, single-phase source. The RPO I /02 Drives require a three-phase line. Power requirements per phase are listed in Table 2-1. 2-1 Table 2-1 RPOI/RP02 Power Requirements Type of Drive Number of Drives RPOI 1-3 8A 4-6 16A 7 or 8 23A RP02 12A 24A 36A NOTE Three-phase power is required for from one through any number of drives. Each unit is a single-phase device but is connected on a phase rotation basis. PDP-I 0 Systems operate from three-phase, Y-connected, 4-wire plus earth ground power mains. Standard voltages are liS /200 Vac ±10%, 60 Hz ±1/2 Hz and 230/400 Vac ±10%, 50Hz ±I /2 Hz. Other common voltages can also be accommodated. A system earth ground connection must be supplied through the power cords in addition to the ground bus requirement. The RPIO is supplied with terminal lugs, a 3-wire cord, and in North America, a 5-wire Hubbell #3521 male plug (mates with Hubbell #3520). One wall power cord is required for every RPOI/02. Terminal lugs are suitable for No. IOta No. 18 AWG wire (0.04 to 0.12 in., I to 3 mm). 2.3 INSTALLATION PROCEDURE To install the RPlO, proceed as follows: Procedure Step Ensure that all power is removed from the PDP-I 0 System and from the RPO 1/02 Disk Packs. 2 Remove the shipping skid from the bottom of the rack and discard it. 3 Remove the front and rear panel doors, and both side panels from the RPIO. NOTE Overall dimensions are given in Figure 2-1. 4 Set the rack in place next to the OF I 0 Data Channel and lower the floor pads on both units to prevent rolling. S Bolt the RPIO rack (in four places) to the DFIO rack already in place. 6 Install the grounding cable to the bottom horizontal rack member. Tie the ground lead to the next grounded rack or to a system grounding bus. 7 Install separate grounds (No.4 standard PDP-IO ground bus) from each drive to the RPIO (star ground system). 8 Connect cables according to the site plan and cabling list supplied with each installation (see Figure 2-2). 2-2 Procedure Step 8 (Cont) NOTE Inspect all cable connectors for shipping and handling damage; install them carefully and securely. All power and signal cables should be routed 1 ft apart, if possible. Power and signal cables should cross at a 90° angle. 9 Locate the drives and level each to within 5° . 10 Connect the remote tum-on power cable from the lower REMOTE CONTROL power outlet on the power control unit of the preceding rack to the upper REMOTE CONTROL power receptacle of the RPIO. 11 Connect the Margin Check Remote Control Cable from J 1 of the preceding Power Connector Assembly Bracket to 12 of the same bracket on the RPIO. NOTE If the RPIO is the last unit in the Margin Check bus, install the terminating plug in 11 of the RPIO Power Connector Assembly Bracket. 12 Connect the RPIO power cable, already connected and secured to the Power Control Unit, to the system source of ac power. 13 Install any I/O bus termination plugs required (refer to DEC-lO-HIFB-D, PDP-I0 Interface Manual). 14 Replace side panels and panel doors. 15 On the drives, carefully remove tape from heads (installed for shipping purposes). 16 Inspect each head to ascertain that it is resting on the proper launching block. 17 Before attempting ON-LINE operation, Head and Servo Alignment must be checked and, if necessary, adjusted with C.E. Packs and an OFF-LINE Tester. See considerations in Paragraph 5.3.4. To load a disk pack on the drive, refer to Paragraph 3.3.1. 18 Using the OFF-LINE Tester perform the following steps on each drive as described in the Vendor Maintenance Manual: 1. 2. 3. Adjust voltage and high/low voltage sense. Adjust positioner as described in Vendor Manual. Perform head alignment with C.E. Pack after completing a Thermal Equilibrium Procedure as described in Paragraph 5.3.4.2d. NOTE When using the OFF-LINE Tester, do not have either a cable or terminator block on 'signal out'. 2-3 114--- 21" ---I ------[---- 27" ------] ---I 69" FRONT VIEW SIDE VIEW 10-0019 Figure 2-1 RPIO Overall Dimensions 2.4 TURN-ON AND CHECKOUT PROCEDURES When the RPIO has been installed, verify its operation by proceeding as follows: Step Procedure Set all switches on switch panel to the down position. Make certain that all margin check switches are in the OFF position. 2 Apply power to PDP-IO computer system and RPOI/02 Disk Pack Drives. The POWER indicator lamp should light. 3 Set LOCAL/OFF/REMOTE switch on the DEC Type 844 Power Control panel to LOCAL position. 4 Set PWR circuit breaker and the power switch located on Power Control panel to ON. The cooling fans should begin to operate. 5 Refer to the MAINDEC Diagnostic Routine and RPIO System Test Procedure to conduct final checkout of RPIO Synchronizer. NOTE Run diagnostics and reliability programs using scratch packs or maintenance packs. Scratch packs used for reliability testing must be Mapped before they can be used with Monitor system because the entire surface is subject to writing by Reliability Test. 2-4 Step Procedure 6 Refer to Chapter 5 for any adjustments required during, or as a result of, this installation procedure. Adjustment procedures for the drives are contained in applicable Vendor Manuals. RP10\ I _I I I I I I ONE R PO 1 TRACK 0 I 2 3 ~~~TORS TRACK 4 ""O,~ / 132 WORDS ~ HEADER -/.. ~TRAILER DATA FIELD 'tJ o SYNCHRONIZATION DATA WORD o DATA WORDS 1-126 DATA WORD 127 CONTENTS TAIL LPR (POSTAMBLEI 10- 0166 Figure 3-4 RPOI/RP02 Data Format Data formats for information recorded on the disks are arranged as shown in Figure 3-4. These data formats consist of a twenty-word header field on the RPO I (thirty-two on RP02), a data field of 132 words, followed by a two-word trailer. The first 18 words in the RPO 1 header field (30 words in RP02) consist of zeros to allow the read circuitry to synchronize with the data. The 19th (31 st on RP02) word contains an octal one (000000000001). The last header field word comprises the addressing field. The first three words in the data field function as a READ DISENABLE/WRITE ENABLE field. The next data field word is used for synchronization, and contains an octal one (00000000000 I). These words are followed by 128 36-bit words, each followed by its own 37th parity bit. The first word in the trailer field contains the contents of the longitudinal parity register, and the last word (tail or post amble) contains a second LPR. NOTE When executing a Write Header command, the lrrst 24 words in an RPOI or the lrrst 36 words in an RP02 are written without parity. Therefore, both bits must be in data and the lrrst bit of the word following the header is interpreted as the parity bit of the header when read back. Addressing is effected by the 18-bit partitioned binary number, defined as word two in the header. The partitioning has been selected to provide sequential access to the entire memory with a minimum of positioning operations. The Exec area (Figure 3-4) is determined by the executive program (monitor, operating system) and is ignored by the interface, except for parity checking. The cylinder address, an unsigned binary number which functions as the track address (positioner), contains eight bits to describe the 313 8 tracks. The outer track cylinder is represented by 000 8 , and the inner track cylinder is represented by 312 8 . The surface address, a five-bit, unsigned binary number, selects one of 10 disk surfaces for the RPO I (codes 008 to 118 are legal), and selects one of 20 disk surfaces for the RP02 (codes 00 8 to 23 8 are legal). Other codes are illegal (nonexistent). The sector address, a five-bit, unsigned binary number, selects the proper sector on a track. One of five sectors is selected on the RPO I (codes 00 8 to 048 are legal), and one of 10 sectors on the RP02 (00 8 to 118 are legal). Other codes are illegal (nonexistent). In the RPO I /02 there is one record per sector (see Figure 3-4). The sector mark defines the beginning of a record. All records are fixed length with a data field of 128 36-bit words plus parity. A header field associated with each record is used to identify the record and ensure that cylinder, surface, and sector selection is correct before writing or reading a record. 3.4.2 RPIO Programming The RPIO modes of operation are position (seek cylinder), recalibrate, read data, write data, write header and data, and clear attentions. Channel instructions must be placed in memory prior to initiating a data transfer in the synchronizer. 3-11 3.4.2.1 DATAO Information (see Figure 3-5) - A DATAO 250 instruction either performs a positioning operation or initiates a data transfer, if the synchronizer is not already busy. The RPIO is capable of executing the six instructions mentioned in the preceding paragraph. The instructions are described below (DATAO 254 is used if a second RP lOis installed in a PDP-I 0 System). Position Instruction (seek cylinder) - The Position instruction word, shown in Figure 3-6, is divided into four fields: Q. ( 1) Op Code: The Op Code is 4 8 , (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Cylinder: The Cylinder field specifies the cylinder sought. Codes 000 8 through 3128 are legal. Others are nonexistent. (4) Bits 14-35: These bits are spares. Execution of a position instruction requires 3 to 5 IlS of synchronizer time and 20 to 150 ms of drive time. Positioning is controlled by a difference count of the present address register and the cylinder address register that is loaded by this instruction. When a zero difference count (compare) is reached, the heads are positioned. o 23 13 14 56 5 BITS 8 BITS \3 BITS 13 BITS 1 23 24 25 18 19 1 0 1 2 0 1 2 0 1 2 3 4 5 6 7 o I 23 4 \:.........-I '---..",--J ~ ~ OP DRIVE CYLINDER SURFACE OR SPARES OR SPARES I o 5 BITS I 234 '-----' SECTOR OR SPARES 26 27 I 34 35 8 BITS B:TI B:TJ BIT 76543210 ~ ICWA OR ATTENTIONS I BIT WRITE EVE~OR PARITY INTO SPARE MEMORY LONGITUDINAL} CHANNEL DATA DISAB LE PARITY ERROR STOP DISK WORD Figure 3-5 DATAO Instruction Word Format o 2 3 1314 5 6 22 BITS OP DRIVE CYLINDER i Figure 3-6 Position Instruction Word b. Recalibrate Instruction - the Recalibrate instruction word, shown in Figure 3-7, is divided into three fields: (J) Op Code: The Op Code is 78' (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Bits 6-35: These bits are spares. 3-12 Execution of a recalibrate instruction moves the positioner ,to cylinder zero by force. Positioning is not controlled by the difference count from the current address register, which may be wrong. c. Read Data Instruction - The Read Data instruction word, shown in Figure 3-8, is divided into ten fields: ( 1) Op Code: The Op Code is 0 8 , (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Cylinder: The Cylinder field specifies the cylinder on which the data to be read resides. Codes 000 8 through 3128 are legal. Other cylinders are nonexistent. NOTE The heads must have been previously positioned; this field is for verification only. (4) Surface: The Surface field indicates the recording surface on which the data to be read resides. Codes 008 through 118 are legal on RPO 1. Codes 00 8 through 23 8 are legal on RP02. All others are nonexistent. (5) Sector: The Sector field indicates the sector on which the data to be read resides. Codes 00 8 through 048 are legal on RPO 1. Codes 00 8 through 118 are legal on RP02. All others are nonexistent. (6) Bit 24: This bit is set to 1 to disable longitudinal parity error stop. If not disabled, the discovery of a longitudinal parity error stops data transmission and sets the longitudinal parity error bit. (7) Bit 25: This bit is a spare. (8) Bit 26: This bit is set to 1 to disable the disk word parity error stop. If not disabled, the discovery of a disk word parity error stops data transmission and sets the disk word parity error bit. (9) ICWA: The IeWA field specifies bits 27-34 of the Initial Control Word Address. All binary values above 178 are legal. NOTE The channel cannot access the fast registers. (10) Bit 35: This bit, when set, causes the channel to write even parity into memory on all data words read from the disk. The Read Data instruction causes data to be read until either the channel shuts down or the end of the cylinder is reached. o 2 3 56 35 30 BITS ~ OP DRIVE SPARES (0-0170 Figure 3-7 Recalibrate Instruction Word BBITS CYLINDER Figure 3-8 Read Data Instruction Word 3-13 d. Write Data Instruction - The Write Data instruction word, shown in Figure 3-9, is divided into ten fields: ( 1) Op Code: The Op Code is 18 . (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Cylinder: The Cylinder field specifies the cylinder on which the data is to be written. Codes 000 8 through 3128 are legal. Other cylinders are nonexistent. NOTE The heads must have been previously positioned. This field is for verification only. (4) Surface: The Surface field indicates the recording surface on which the data is to be written. Codes 00 8 through 118 are legal on RPOI. Codes 00 8 through 23 8 are legal on RP02. All others are nonexistent. (5) Sector: The Sector field indicates the sector on which data is to be written. Codes 00 8 through 048 are legal on RPO I. Codes 008 through 118 are legal on RP02. All others are nonexistent. (6) Bit 24: This bit is a spare. (7) Bit 25: This bit is set to I to disable channel data word parity error stop. If not disabled, the discovery of a channel data word parity error stops data transmission and sets the channel data word parity error bit. (8) Bit 26: This bit is a spare. (9) lCWA: The ICWA field specifies bits 27-34 of the initial control word address. All binary values above 178 are legal. NOTE The channel cannot access the fast registers. ( 10) Bit 35: This bit is a spare. This instruction causes data to be written until either the channel shuts down or until the end of the cylinder is reached. NOTE If the last (or only) sector to be written is shorter than 128 words, the remainder of the field is fdIed with words "aU zeros." Figure 3-9 Write Data Instruction Word 3-14 e. Write Header and Data Instruction - The Write Header and Data instruction word, shown in Figure 3-10, is divided into nine fields: (1) Op Code: The Op Code is 38' (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Surface: The Surface field indicates the recording surface on which the headers and data are to be written. Codes 008 through 118 are legal on RPOI. Codes 00 8 through 23 8 are legal on RP02. All others are nonexistent. (4) Bits 19-24: These bits are spares. (5) Bit 25: This bit is set to 1 to disable channel data word parity error stop. If not disabled, the discovery of a channel data word parity error stops data transmission and sets the channel data word parity error bit. (6) Bit 26: This bit is a spare. (7) ICWA: The ICWA field specifies bits 27-34 of the initial control word address. All binary values above 178 are legal. NOTE The channel cannot access fast registers. (8) Bit 35: This bit is a spare. This instruction formats the disk. The RPIO searches for an index mark, then writes header and data fields as shown in Figure 3-4. The programmer supplies headers and data as described in Paragraph 3.4.1. The synchronizer writes one track of headers and data and adds the data word parity bits and the trailer field. f. Clear Attentions Instruction - The Clear Attentions instruction word, shown in Figure 3-11, is divided into five fields: (1) Op Code: The Op Code is 58' (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Bits 6-26: These bits are spares. (4) Bits 27-34: These bits clear attentions 0-7, respectively. (5) Bit 35: This bit is a spare. a alTS CYLINDER Figure 3-10 Write Header and Data Instruction Word o 2 3 56 ttl OP DRIVE 2627 21 BITS 3435 BBITS ~ " SPARES ATTENTIONS Figure 3-11 Clear Attentions Instruction Word 3-15 ' [ SPARE g. No Op Instruction - The No Op instruction word, shown in Figure 3-12, is divided into three fields: (1) Op Code: The Op Code is 6 8 , (2) Drive: The Drive field indicates the disk drive addressed. All codes are legal if the drives exist. (3) Bits 6-35: These bits are spares. o 2 3 35 56 30 BITS SPARES Figure 3-12 No Op Instruction Word 3.4.2.2 DATAl Information - A DATAl 250/254 Instruction supplies the programmer with information concerning the disk and cylinder selected, as defined below and illustrated in Figure 3-13 (250 for RPOI or 254 for RP02): a. Disk Selected - This field indicates the disk most recently selected by a legal DATAO. lOB 0-2 b. Cylinder Address Register - This field displays the contents of the drive's cylinder address register. lOB 3-10 c. Seek Incomplete - This bit indicates that the drive was unable to complete the most recent position command addressed to it. The error recovery procedure is: issue a recalibrate command, which clears this error condition. lOB II d. On Cylinder - This bit indicates that the heads are positioned on the cylinder specified by the cylinder address register bits of this instruction word, and that data transfer may proceed. lOB 12 e. On Line - This bit indicates that]) the ENABLE/DISABLE switch is in the ENABLE position, 2) a disk pack is mounted, 3) tl!le dust cover is closed, 4) the spindle is up to operating speed, and 5) the heads are mounted on the disk. IO B 13 f. File Unsafe - This bit indicates that either 1) a head is selected when not on a cylinder, 2) more than one head has been selected simultaneously, 3) read and write were selected at the same time, 4) write and/or erase were selectedwhenthe file was not ready, 5) write current was sensed when write was not selected, 6) write was selected with no write current, 7) erase current was sensed without erase being selected, or 8) write was selected without erase current. lOB 14 NOTE The interface provides hardware to prevent any of these conditions from being caused by programming errors. To clear this bit, depress the STOP and START buttons. A full power-down/power-up sequence, requiring over one minute, must follow. g. No Such Drive - When this bit is true, it indicates that the drive addressed does not exist. In this case, the other bits of this instruction word are meaningless. lOB 15 h. Read Only - When this bit is true, it indicates that the drive's READ-WRITE/READ ONLY switch is in the READ ONLY position. lOB 16 i. Write Header Lockout - This bit, when set, prevents headers from being written. lOB 17 3-16 j. Sector Counter - These bits indicate the state of this disk's sector counter. The sector counter is cleared by an Index Pulse and counts sector pulses. lOB 18-22 k. Attentions - These indicate which drives are requesting an interrupt due to Seek Incomplete or Seek Complete. lOB 27-34 3.4.2.3 CONO Information - A CONO command is illustrated in Figure 3-14 and described below: a. Clear: These bits perform the following clear operations; (1) Bit 20: When this bit is set to aI, it clears the power supply failure (PS FAIL) flag (2) Bit 21: When this bit is set to aI, it clears the search error (SRCH) flag. (3) Bit 22: When this bit is set to aI, it clears the overrun (OVERRUN) flag. (4) Bit 23: When this bit is set to aI, it clears the no such memory location (NXM) flag. (5) Bit 24: When this bit is set to aI, it clears the Channel Control Word Parity Error only if the power supply fail conditions have been corrected. (CCPE), the Disk Sector Parity Error (DSPE), the Disk Word Parity Error (DISK WDPE), and the Channel Data Parity Error (CDPE) flags. (6) Bit 25: This bit is a spare. (7) Bit 26: When this bit is set to aI, it clears the Illegal Write (ILL WR) flag. (8) Bit 27: When this bit is set to a 1, it clears the Illegal Command While Busy (ILL COM) flag. (9) Bit 28: When this bit is set to a 1, it clears the Sector Designation Error (SEC DE) flag. (10) Bit 29: When this bit is set to aI, it clears the Surface Designation Error (SURF DE) flag. o 1 23 1 11 BIT BIT BIT 8 BITS ~ DISK SELECTED CYLINDER ADDRESS REGISTER WRITE HEADER LOCKOUT READ ONLY NO SUCH DRIVE FILE UNSAFE ON LI NE ON CYLINDER SEEK INCOMPLETE 10-0169 Figure 3-13 DATAl Instruction Word Format (Revised) o 20 BITS SPARES STOP WRITE CHAN"IEL CONTROL INTO MEMORY/CLEAR CONTROL WORD TRANSFER COMPLETE 10-0171 Figure 3-14 CONO Instruction Word Format 3-17 b. Write Channel Control Word into Memory: This bit causes the data channel to store the current contents of the data address register and the control word address register into memory location B + I where B (an even number) is the Initial Channel Control Word Address. The corresponding CONI bit signifies completion of the operation. Any channel termination causes the control word to be written, but CONI bit 30 will only be set when the operation was requested by the synchronizer via CONO. This bit, when it is set to a I, clears the Control Word Transfer Complete (CWX: CaMP) flag. lOB 30 c. This bit stops transmission immediately. Part of last word and last sector transmitted is in determinant. lOB 31 d. Clear: This bit clears the Done (DONE) flag. IOB32 e. PI 0, I, 2: (PI Assignment) These bits assign a priority interrupt channel to the synchronizer. lOB 33-35 3.4.2.4 CONI Information - A CONI command is illustrated in Figure 3-15 and described in the following paragraphs: I a. Channel Control Word Parity Error - This bit indicates that the Channel Control Word contained a parity error. This error condition cannot be disabled. The error flag is cleared by a CONO with bit 24 set to a 1. lOB 14 b. Disk Sector Parity Error - This bit indicates that the checksum bits, at the end of a sector which has been read by the most recent read data command, do not yield a modulo-two sum of 1. Unless disabled, this error terminates data transmission. The error flag is cleared by a CON a with bit 24 set to a 1. lOB 15 c. Channel Data Word Parity Error - This bit indicates that the word read from memory during execution of the most recent write data or write header and data instruction contained incorrect parity. Unless disabled, this error terminates data transmission. If the instruction was write data, the remainder of the sector is filled with Os and correct parity is added. If the instruction was write header and data, the results are indeterminate. lOB 16 d. Disk Word Parity Error - This bit indicates that the word read from the disk during execution of the most recent read data instruction contained incorrect parity. Unless disabled, this error terminates data transmission. lOB 17 e. Search Complete - This bit indicates that the search for the sector to be read or written has been completed. lOB 18 f. End of Cylinder - When this bit is set to I, it indicates that the most recently executed read data, write data, or write header and data instruction attempted to transfer too much data and, as a result, incremented the head address register past the last surface on the disk. On the RPO I, the register is incremented to 128' On the RP02, the register is incremented to 24 8 , This bit is cleared by the next data transfer instruction to the same disk drive. lOB 19 g. Power Supply Failure - This bit indicates that the interface power supply voltages are out of tolerance. When this occurs, the interface terminates at the end of the current sector and turns on both the done bit and the power supply failure bit. The power supply failure bit cannot be cleared until the error condition has been corrected. lOB 20 h. Search Error - This bit indicates that the cylinder, surface, and sector fields of the most recently executed read data or write data instruction could not be matched (compared) with corresponding fields of any sector on the addressed track. This could occur because either 1) there was a bad spot in the header field, 2) the instruction contained the wrong fields, 3) the program did not previously position the heads to the proper cylinder, 4) the disk drive positioning mechanism is in need of adjustment, 5) the PDP-IO System has failed, or 6) a header was read incorrectly after search complete was set during a multiple sector transfer. lOB 21 3-18 o 13 14 BITS SPARES 14 15 16 '7 18 19 20 21 1 1 1 1 1 1 1 1 BIT BIT BIT BIT BIT BIT BIT BIT 22 23 24 25 26 27 28 29 30 31 32 1 1 1 1 1 1 1 1 1 1 BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT 35 14 BITS l ,~ PI BUSY CONTROL WORD TRANSFER COMPLETE SURFACE DESIGNATION ERROR SECTOR DESIGNATION ERROR ILLEGAL COMMAND WHILE BUSY ILLEGAL WRITE DISK NOT READY PARITY ERROR (14-17) NO SUCH MEMORY LOCATION CHANNEL TOO SLOW SEARCH ERROR POWER SUPPLY FAILURE END OF CYLINDER SEARCH COMPLETE DISK WORD PARITY ERROR CHANNEL DATA WORD PARITY ERROR DISK SECTOR PARITY ERROR CHANNEL CONTROL WORD PARITY ERROR l 10-0167 Figure 3-15 CONI Instruction Word Format (Revised) i. Channel Too Slow - This bit indicates that the channel failed to respond to a request for a data word, or failed to accept a data word fast enough during a data transfer. If the instruction was a read data, data transmission is terminated. If the instruction was a write data, the remainder of the sector is filled with Os and proper parity is added. If the instruction was a write header and data, the results are indeterminate. lOB 22 j. No Such Memory Location - This bit indicates that the channel attempted to access a nonexistent memory location. lOB 23 k. Parity Error (14-17) - This bit (24) is true when anyone of bits 14 through 17 are true. Clearing this bit clears bits 14 through 17. lOB 24 I. Disk Not Ready - lOB 25 m. Illegal Write - This bit indicates that a write header and data or write data instruction was received which addressed a disk drive whose READ-WRITE/READ ONLY switch was in the READ ONLY position, or a WRITE was in process when sector pulse was received. lOB 26 n. Illegal Command While Busy - A DATAO to the RPIO was issued while BUSY flag was on. The second command is ignored. lOB 27 o. Sector Designation Error - This bit indicates that the sector addressed by the most recent read data or write data instruction does not exist (greater than 048 on the RP01 and greater than 118 on the RP02). lOB 28 p. Surface Designation Error - This bit indicates that the surface addressed by the most recent read data, write data,. or write header and data instruction does not exist (greater than 118 on the RPOI and greater than 23 8 on the RP02). lOB 29 q. Control Word Transfer Complete - This bit indicates that the channel control word was written into memory only when that request was made by the synchronizer via CONO. lOB 30 3-19 r. Busy - This bit indicates that the synchronizer is currently executing a data transfer command. lOB 31 s. PI Enable - This bit indicates that the PI condition has been enabled. It is the result of (DONE VATTENTIONS)I\-BUSY. lOB 32 t. PI 0, 1, 2 - (PI Assignment) These bits indicate the priority interrupt channel currently assigned to the RPIO. lOB 33-35 3-20 Chapter 4 Theory of Operation 4.1 GENERAL This chapter discusses the principles of operation of the RPIO Disk Pack Synchronizer. A general block diagram discussion, a brief sequence of operation, and functional descriptions of the various operational circuits used in the synchronizer are also included. 4.2 GENERAL BLOCK DIAGRAM DISCUSSION The RPIO Disk Pack Synchronizer is shown in general block diagram form in Figure 4-1. The RPIO acts as an intermediary between the I/O Bus, the DFIO Data Channel, and the RPOI, or RP02 Disk Pack Drive. For purposes of this discussion, a knowledge of the PDP-I 0 I/O Bus, the DF I 0 timing diagrams, and the operation of the RPO I /02 Disk Pack Drives is assumed. The PDP-I 0 Processor communicates with the RPIO Disk Pack Synchrcrmizer via four basic I/O instructions; ]) Conditions Out (CONO) which transmits the control word to the RPIO control register thereby specifying the desired operation, 2) Conditions In (CONI) which transmits the contents of the RPIO control and/or status register to the processor, 3) Data Out (DATAO) which transmits processor data to the RPIO data register, and 4) Data In (DATAl) which transmits the contents of the RPIO status and drive address registers to the processor. The RPIO communicates with the RPOI or RP02 Disk Pack via the 35 tines shown in Figure 4-1. There are eight address and control lines; three tag lines; and one line each for sequence out, unit select, controlled ground, and write data. These lines carry information from the synchronizer to the disk. The disk communicates with the synchronizer over eight cylinder address lines; and one line each for attention, unit selected, ready, on-line, index pulse, sector pulse, file unsafe, seek incomplete, end-of-cylinder, read data coax, heads extended, and read only. In the PDP-l 0 System, several RPIO Disk Pack Synchronizers can be attached to one data channel. As shown in Figure 4-2, the RPIO will gate nothing onto the channel bus until it receives the CHANNEL BUSY signal from the data channel. While inactive, the RPIO relays CHANNEL BUSY, CHANNEL START, and SAWRITE in the appropriate directions on the channel bus. On receipt of - CHANNEL BUSY, it asserts its own CHANNEL START and SAWRITE, and becomes active. 4.3 SEQUENCE OF OPERATION In these discussions, reference is made to the flow charts and logic diagrams listed in Chapter 6 and contained in Volume 2 of this manual. These are general descriptions intended to clarify some of the more obscure points in the diagrams. They do not trace each signal on a gate-by-gate basis. 4-1 ATTENTION 1 LINE UNIT SELECTED 1 LINE READY 1 LINE DATA 0 ON-LINE 1 LINE INDEX PULSE 1 LINE SECTOR PULSE ll1NE I FILE UNSAFE 1 LINE DATAl SEQUENCE OUT 1 LINE ADDRESS e.CONTROL 8 LINES RP10 DISK PACK SYNCHRONIZER PDP-l0 PROCESSOR CONO RPO 1 OR RP02 DISK PACK UNIT SELECT 1 LINE WRITE DATA 1 LINE TAG 3 LINES CONTROLLED GND ~ ~ OTHER PACKS 35 LINES 1 LINE SEEK INCOMPLETE 1 LINE END OF CYLINDER 1 LINE CONI READ DATA COAX 1 LINE I HEADS EXTENDED 1 LINE CYLINDER ADDRESS 8 LINES READ ONLY 1 LINE 10- Or5g Figure 4-1 RP 10 General Block Diagram The RPlO receives commands (instructions) via DATAO 250 (254 for a second RPlO in a PDP-l 0 System). The Flow Chart FCS (Start) describes the receipt and decoding of instructions. Note that !BC INITIAL CLEAR does not clear SR or SR BUF registers. If the command is a No Op or Clear Attentions, execution is completed. If it is a Restore (recalibrate), or Seek, the RPIO exits through S2 to execute the command. If the command received is a Data Transfer, the RPIO exits through S5 to clear and set the head register in the drive, and through S4 to start the data channel. When the RPIO receives control of the data channel, it exits from FCCC through CC2 to begin data transfer. 4.3.1 Write Data or Read Data I I If the command is Write Data or Read Data, DTC SEARCH is set and the RPI 0 begins searching for the sector addressed by the DAR CYL, DAR SURF, and DAR SEC registers. The 10-Jls delay DTC SECTOR DLY allows the drive's head register to be incremented in a multiple track operation before setting DTC READ REFUSE. (The term REFUSE denotes useless information and not the act of rejection.) DTC READ HEADER is set by the first I-bit read off the disk after the 350-Jls delay for DTC SEARCH SYNC times out. The delay is included so that DTC READ HEADER cannot be set by a I which might be read before the READ DATA SEPARATOR is in sync. When DTC READ HEADER is set, the next 36 bits are read into the LPR register. These bits and the 37th are exclusive ORed into the DTC PARITY flop. When the DTC PAR CON flop turns off, a 600-ns delay is fired that allows time for the LPR to shift the last character in, and for all signals to settle. 4-2 I When DTC SRCH COMP STROB times out, the state of the DTC PARITY flop and the HCDE HEADER COMPARE signals are sampled. If they are correct, they set DTC SEARCH COMP and clear DTC SEARCH. HCDE HEADER COMPARE is true when the contents of the low-order 18 bits of the LPR match the contents of DAR CYL, DAR SURF, and DAR SEC registers. On a multiple sector read or write, the RPIO checks the cylinder and the parity bits, but does not check sector and surface bits. TO OTHER [/0 DEVICES rl_._ CHANNEL BUSY CHANNEL START SAWRITE ACTIVE lIO DEVICE uu INACTIVE 1/0 DEVICE TO OTHER I/O DEVICES INACTIVE RPIO CHANNEL BUS TO OTHER 1/0 DEVICES .---_L.....,CHAN TO OTHER B U f Y h I/O DEVICES CHANNEL START SAWRITE INACTIVE INACTIVE I/O DEVICE I/O DEVICE ACTIVE RP10 10-0108 Figure 4-2 RPIO Active and Inactive Functions If the operation is write data, the RP I 0 exits from FCSC to FCRW. The 3-J..I.s delay prevents the write current from destroying the last few bits of the header. Four 36-bit words (consisting of Os) are then written without parity. Following this, the DTC PAR CONT flop is set and a 1 is written as a trigger for subsequent read operations. This field is written during every write to ensure that the Read Data Separator is lined up with data. A lack of alignment can occur for two reasons; 1) the gap is discontinuous, and therefore the signal is unpredictable, or 2) the speed of the drive on which the header was written differs from that of the drive on which data was written. 4-3 After DTC WRITE DATA is set, the RPIO exits to the FCM2 subroutine to write the data. It returns when the I 28-word word counter overflows and the WDC WORD COUNT EQ 00 becomes true. At this time, DTC WRITE LPR is set and DTC WRITE DATA is cleared. The RPIO again exits to the FCM2 subroutine to write the contents of the LPR on the disk twice. The second LPR is written as guard bits to ensure that the last bits of the LPR are not destroyed when write current is removed. The DTC SET WRITE is then cleared and the tunnel erase heads must be turned off after write is removed or FILE UNSAFE will occur. The tunnel erase is used to narrow the width of the data track as written by the read/write poles. This prevents crosstalk between tracks. At this point, DTC GAP is set. If the channel has terminated during the write operation, or if there has been an OVERRUN, or CHAN DATA PE, the operation is shut down. Otherwise, the RPIO waits for the next DSBC SEL UNIT SEC PLS and continues on FCSC. If the operation is read data, the RPIO exits through SC2. The Read Data Separator is enabled by DTC BETA GAP, during which it resyncs in preparation for a read data operation. DTC BETA GAP is cleared in 44 JlS for an RP02 or in 88 JlS for an RPOI. At that time, if DTC SEARCH COMP is cleared, it is an indication that the RPIO has not completed its seek operation. At this time, DTC READ GAP, which was set by the trailing edge of DTC SRCH COMP STROBE, is cleared and the RPIO waits for the next DSBC SEL UNIT SEC PLS to try again. If DTC SEARCH COMP has been set by DTC SRCH COMP STROBE, however, the RPIO waits for the first I-bit from the disk, which signals the start of the data area. When the first I-bit is received, DTC READ DATA is set, clearing DTC READ GAP and the RPIO exits from FCRW to FCMI subroutine. It returns when 128 words have been read, and the WDC WORD COUNT register overflows to O. DTC READ LPR is then set, and DTC READ DATA is cleared. After reading one more word, sector parity is checked. If any bit of the LPR register is zero, CXR DISK SEC PE is set. In either case, DTC GAP is set, and the RPIO waits for the next DSBC SEL UNIT SEC PLS and then continues on FCSC. 4.32 Write Headers and Data (Format) If the command is write headers and data (Format), the RPIO exits from FCSC to FCWH where it waits, first for a DSBC SEL INDEX pulse and then for a DSBC SELECTED SECTOR. After a delay, it sets DTC WRITE HEADER, and exits to the FCM2 subroutine to write 36 words (24 in RPOI) without parity. The RPIO then exits to FCRW, sets DTC WRITE DATA, clears DTC WRITE HEADER, and returns to FCM2 to write 128 words with parity. When the WDC WORD COUNT register overflows to zero, the RPIO returns to FCWH, sets DTC WRITE LPR, clears DTC WRITE DATA, and exits to FCM2 to write the LPR on the disk twice. NOTE The second writing of the contents of the LPR is a convenient way to write gu~d bits. After the second LPR is written, the RPIO returns to FCWH, clears DTC WRITE LPR, keeps the erase heads turned on for 20 JlS, sets DTC GAP and waits for the next DSBC SELECTED SECTOR. 4.3.3 Local/Remote Local and Remote mode operation are straightforward and can be followed directly on FCL. Major differences in the two modes are listed below: a. Local Mode ( 1) The DAR CYL register is tied to the CYLINDER switches. (2) CC ACTIVE BUF is held off so that the data channel is not started. (3) The AR is loaded from the 'pATA switches rather than from the AR CHNDOO-35 Channel Data Lines. 4-4 (4) The Initial Control Word Address is not loaded. (5) The RPIO is logically disconnected from the PDP-lO I/O bus (it will not respond to its device code and will not set its DONE and PI Enable signals). (6) IBC SET DAR ETC does not fire, therefore, the status registers are not set by information present on the I/O bus. b. Remote Mode (J) DTC FINISH clears IBC BUSY, sets IBC DONE, and interrupts the PDP-lO on the assigned PI Channel; whereas in Local Mode, DTC FINISH clears IBC BUSY and, if the SWP STOP switch is not depressed, the entire operation is repeated after a 100-J,Ls delay. 4.4 RPIO RECORDING TECHNIQUE Disk pack systems are susceptible to a phenomenon termed "pulse crowding." This phenomenon can occur when a series of I s are recorded on a track. As the pulse density increases, the location of the recorded I s crowd each other with the result that they may actually reside either ahead of, or in back of, the location in which they were recorded. The resultant locations can shift in either direction; consequently, a means is provided in the RPIO to read through a precisely-timed "window", enabling original timing to be recovered. The RPIO uses a double-frequency, nonreturn-to-zero (NRZ) recording technique. A S-MHz clock signal is divided to produce two 2.S-MHz signals with a 180 degree phase relationship (see DWG RPIO-O-RDS). When writing, the leading 2.S-MHz signal continuously records I bits on the disk surface, while the trailing signal samples the data to produce data bits. If the data to be written is continuous Os, a 2.5-MHz signciJ. is recorded on the disk surface. If the data to be written is continuous Is, then a S.O-MHz signal is recorded. Therefore, for any given data cell, the recorded frequency is either 5 MHz for a I data bit, or 2.5 MHz for a 0 data bit. To recover data recorded in this manner, the Os rate frequency component must be removed, which is done by using a phase-locked oscillator (RDS) similar to a sample-and-hold circuit. The RDS samples the Os rate pattern in the preamble of each record, phase-locking on this pattern, and then maintains phase through the record, making only minor corrections with the use of the Os rate component of each data cell. The RDS then removes the Os rate component with which it is familiar, leaving only the recovered data. The Os rate component (2.5 MHz for RP02 or 1.25 MHz for RPOI) removed from the raw data stored on the disk is also used. This signal is the main source of timing in the RPIO Synchronizer. The RPO I /02 has no clock track; this system provides self-clocking. 4.5 RPOI/02 ADDRESSING METHOD The RPO I /02 Disk Pack consists of six (or eleven respectively) evenly-spaced recording platters mounted on a single shaft. The top- and bottom-most surfaces are not used for recording; instead, the bottom surface has a metal disk attached to it. The disk contains twenty evenly-spaced notches with an additional notch termed the Index. A circuit that is designed to detect these notches, also divides the pulses they produce into either five or ten equal sectors. These sectors are addressed by a five-bit register which is part of the Data Address Register (see DWG RPIO-O-DAR). The sector addresses are coded 008 through 048 when using an RPOI drive, and 008 through 118 when using an RP02 drive. All other codes are illegal and, if given, result in the appropriate interrupts. 4-5 A separate read/write head is provided for each of the inner recording surfaces. These heads are mounted in parallel and in vertical alignment to each other and are attached to a common head tower. The heads are selected by an additional five-bit register in the Data Address Register designated DAR SURFOO-04. Head addresses are coded 00 8 through 118 for the RPOI drives, and 00 8 through 23 8 for RP02 drives. All other codes are illegal and, if given, result in the appropriate interrupts. The position of all heads, vertically aligned with respect to the vertical axis that passes through the center of all surfaces, is called a cylinder. Head positioning is controlled by a linear positioning motor and detenting mechanism that is designed to stop the heads at anyone of 203 different cylinder locations. These cylinders are coded 00 8 through 3128 from the outer-most cylinder to the inner-most cylinder, respectively. Cylinders are addressed by an eight-bit register called DAR CYLO 1-128 in the Data Address Register. The intersection of a cylinder, head, and sector address defines a unique sector that is the smallest addressable unit in the system. Each sector has a header word that uniquely defines that sector. 4.6 RPIO REGISTER ORGANIZATION The register organization of the RPI 0 is given in Figure 4-3. The various signals which control the flow of data originate in the Data Transfer Control (DTC). Serial information from or to the disk is assembled or dispersed by the six-bit Shift Register. The data is then processed in parallel, through the Shift Register Buffer, and is transferred to or from the Assembly Register and Longitudinal Parity Register in six-bit bytes. In read mode, DTC READ BIT translates information bit-by-bit as it is read from the disk. Each bit enters the shift register at SR5 and is shifted through the register by DTC SHIFT SR. When the register is filled, DTC LD BUFFER FM SR transfers the six-bit byte to the SR BUF where it loads AR30-35 at a DTC SHIFT AR time. It also exclusive ORs the byte into LPR 30-35 by DTC LOAD LPR. Subsequent bytes are then assembled by DTC SHIFT AR, DTC LOAD LPR, and DTC SHIFT LPR. At the end of six byte transfers, the AR contains the word read, and the LPR contains the parity for that word. In write mode, the first six bits of a 36-bit word, which has been previously assembled in the AR, is loaded by a Is transfer into the SR by DTC LD SR FM AR and into SR BUF by DTC LD BUFFER FM AR. While these six bits are being serially transferred to the disk by DTC SHIFT SR, they are also exclusive ORed into LPR30-35 by DTC LOAD LPR. At the end of the six transfers, the contents of the AR are written on the disk, and the LPR contains the parity for that word. Thus, the SR must be cleared before loading. It is cleared by WRITE ENABLE, which feeds Os into the SR during each shift. Only five shifts are used during a write; therefore, the state of SRO is indeterminate during a load from the AR, and it is jam transfemed. When DTC LD SR FM LPR is issued, the contents of the LPR are written on the disk through the Shift Register by DTC SHIFT SR. 4.7 RPI0 REGISTERS 4.7.1 Assembly Register The RPIO Assembly Register is shown in Figure 4-4 and in DWG RPIO-O-AR. The register is arranged in groups of six flops, each group individually feeding the next lower-order group of six. Input is at AR30-35 by ARD3035 H or ~ARD30-35 HANDed with DTC SHIFT AR H. Each flop can also be set by its individual panel switch (SWP DATA SWOO-35 H) if ANDed with ~IBC LOAD TEST H. The setting of each flop, when ANDed with CC DATA STROBE L, results in the AR CHND XX L version of that bit. When AR CHND XX Lis ANDed with DTC DATA RCVR EN L, it direct sets the flop from which it originated. 4-6 CD CD DTC SHIFT AR ® DTC SHIFT LPR ® DTC LOAD LPR CD @ LD BUFFER FM AR ® DTC LD S R F MAR (1) DTC LD ® SR FM LPR ® DTC SHIFT SR CD ® DTC LD BUFFER FM SR ® DTC CD ® ® CD 30 31 32 33 34 CD CD - 35 AR 30-35 LOADED FROM SR BUF 0-5 IN "READ" ® DI~~ , " SR 0-5 LOADED FROM AR 0-5 I N "WRITE" I0 -O~07 Figure 4-3 RP I 0 Register Organization 4.7.2 Assembly Register Data Gate The RPlO Assembly Register Data Gate is shown in Figure 4-5 and DWG RPlO-O-ARD. The data gate connects the Assembly Register output and the Shift Register Buffer, and functions as an input switcher for the AR. The register consists of four sets of six AND gates and two sets of six OR gates; One set of OR gates feeds the set inputs of AR30-35 with ARD30-35 H. The other set of OR gates feeds ~ARD30-35 to the AR reset inputs. Input to the AR Data Gate is either from the Shift Register Buffer (SR BUFO-5) or the output of the Assembly Register (AROO-05). Inputs from the AR are enabled by the write condition (DTC WRITE ENABLE L) while inputs from the Shift Register Buffer are enabled by the read condition (DTC READ ENABLE L). 4-7 CC DATA STROBE L -lBC DTC SHIFT AR H LOAD TEST H ,..-.------ DTC DATA RCVR EN L DTC CLEAR ARH I • I I I I I • ~ ARD 30 H -ARD 30 H SWP DATA__ SW 30 H SWP DATA SW 25-28 H SWP DATA SW 18-23 H --+ -ARD 3b34 H -4. SWP DATA SW 12-17 H --+ SWP DATA SW 01-04 H -r - L r;:-L.:.:.. I-1 SWP DATA SW 24 H AR 30 --- rt AR CHND 30L IN ~ r;:- I-- - -- -- - -- -t ~ - 1 AR 24 , f.- -~- - - - -- l - - --- -+ - - - - -- -- -~ I-- r----I -ARD 35 H SW~ DAT. SW3 H r;; -L.:... r-; l..:. Jr G~ f--I AR 35 0 '---- SWP DATA SW 29 H AR II I---' CH~D 35 L IN .rt;" L..:.:.. .r--;\ l."::" ~ I L I I I I f.1 AR 29 0 '---- -- l ~ AR CHND 29 L IN I I I I TO AR 23 TO AR 23 -. ---II ct II r;- SWP DATA SW 00 H AR 06 kh- r;- 0 t I I I ~ - ~- -- r I I I ! FROM AR 17 I FROM ARI7 AR OO I--- ~ ~- t - -, I I .-L I I I I AR 01-04 SAME I I I I I - -- - -- - - -l - -- _J r---' II I-- ~ I--1 I SWP DATA SW05 H AR " 0 L...-- AR CHND 07-10 L IN T I I I I + - AR CHND 01-04 L IN T I I I I 1 0 -L....:.:... I--- -- - - I""-- -L:- AR CHND 06 L IN AR CHND 00 L IN ~ ~ [Z ~ 1 --- I I L ______ -.J I : AR07-IO SAME I I I CC DATA STROBE L OTC SHIFT AR H I I I I II FROM AR 12 I I I I I I I I I I t I AR 25-28 SAME I I [Z TO AR 18 AR 18-23 a AR 12-17 SAME I AR 31-34 SAME I FROM AR 12 TO AR 18 I I I I I I I I I AR CHND 24 L IN J I I .....--: ARD 35 H I 0 L....:.:. I I I - -L dJ 0 I ARD 31-34 H SWP DATA SW 7-10 H J" ~ ~ r SWP DATA SW 31-34 H IA -t.::.. I I I I I II I AR iI LOAD TEST H • I r-- CLE~P I I -/I - -IBC DTC DATA RCVR EN l DTC -, ~ II t-- ~ -rt;" L..:.:.. r--;\ -L.:... kh- ~ I AR CHND 18-23 L a 12-17 L IN AR CHND 25-28 L IN AR CHND 31-34 L IN AR CHND" L IN AR CHND 05 L IN 9 10- 0508 AR 05 0 '---- Figure 4-4 RPIO Assembly Register Simplified Block Diagram 4-9 OTC WRITE ENABLE L OTC READ ENABLE L AROO (0) L AR 00 (n L I I I I I THRU I 'V ARO 30H ARO 30H SR BUF 0(0) L I THRU I I I SR BUF 0(1) L I I I THRU AR 05 (0) L I I I I I THRU I THRU AR 05 (1) L I THRU I I 'VARO 35 H I I SR BUF 5 (0) L I I SR BUF 5 (1) L I ARO 35H Figure 4-5 RPIO Assembly Register Data Gate, Simplified Block Diagram 4.7.3 Condition Register The RPIO Condition Register is shown in Figure 4-6 and in DWG RPIO-O-CXR. This register monitors various conditions in the controller, raises indications when these conditions are in error, and provides a means of clearing the conditions or controlling them remotely. In the condition register, all flops are cleared by IBC INITIAL CLEAR except the three error stop disabling flops (DSPE, CDPE, DWPE), which are cleared by IBC GEN CLR (1) H, and the three priority interrupt flops (PI0-2), which are cleared by IBC CON CLR H. During a CONO command, the CXR PIO-2 flops are conditioned by the state of IOBD 33-35 HANDed with IBC CONSET H. When the outputs of PI0-2 are decoded, they determine the priority interrupt channel assigned to the RPIO (CXR lOB PIl-7 H). During a CONI command, the priority interrupt channel currently assigned is indicated. The decoder is enabled by CXR PI ENABLE H, which is the combination of either IBC DONE (1) H or any DTC ATTNO-7 (1) HANDed with IBC BUSY (0) Land IBC LOCAL (0) L. IOBD 35 H, when set during a Read Data instruction and ANDed with IBC SET DAR ETC A, H, sets CXR WRITE EVEN PAR flop. This flop causes the channel to write even parity into memory on all data words read from the disk. The output CXR PARITY ER L is the OR of CXR CHAN DATA PE( I) H, CXR CHAN CONT PE( I) H, and CXR DISK SEC PE(1) H. The disk sector parity error flop is set by CXR SEC PARITY ERROR H 600 ns after DTC READ LPR goes false, thus indicating that the checksum bits at the end of a sector (which has been read by the most recent Read Data command) do not yield a modulo-two sum of I. 4-10 CC STRT SCH L IC NO SUCH MEM L lOBO 24 H DTC DATA STROBE L IBC INITIAL CLEAR CH IBC CON SET H IBC SET DAR ETC A H IBC INITIAL CLEAR CH CC ILLEGAL WRITE H IBC GEN CLEAR (I) H IBC CON SET H IBC BUSY (1) H /\ CXR ' NON EX MEM 0 lOBO 23 H IC DATA PARITY ERROR L IBC CONSET H DTC PAR CONT (1) L DTC READ DATA (1) L CXR' DIS DSPE STOP 0 DTC PARITY (0) L CXR ' DISK WD PE O /\ lOBO 24 H CXR ' CHAN DATA PE 0 lOBO 25 H CXR PARITY ER L IC CON PAR ERROR L 1 CXR DIS COPE STOP 0 '" CC PREVENT TEST H lOBO 26H IBC BUSY (1) H IBC DEVICE SELECTED L lBC DATAO SET L lOBO 26 H 1 CXR CHAN CONT PE 0 LPR 00-35 (0) CXR SEC PAR ITY ERROR H DTC OVERRUN H CXR 01 SK sEc PE 1 CXR OVERRUN 0 IOBD 22 H 0 IC WR CON WD COMP L DTC READ LPR (0) H I lOBO 30 H IBC CON CLR H CXR CW XFER COMP 0 C C)(R DISK NOT ROY H V 1--.....- _ C)(R DISK NOT ROY L IBC POWER CLEAR H - - - - - - - - - , PS FAI L MODULE DTC ATTN 0-7(1)H lOBO 35H IBC CONSET H - - - - - . /\ 1 CXR WRITE EVEN PAR 0 IBC DONE (1) H lOBO 20 H - CXR PS FAIL o ......._OJ IBC BUSY (0) L DTC SEARCH (1) L IBC LOCAL (0) L lOBO 33 H 3 "'Dsec SEL UNIT READY H "'Dsec SEL UNIT ON LINE H DSBC SEL FILE UNSAFE H _ CXR PI ENABLE H CXR PI ENABLE L CXR lOB PI 7 H DSBC SEL INDEX L CXR SEARCH ERO 0 lOBO 21H CXR lOB PI 6 H lOBO 34 H CXR lOB PI 5 H CXRIOBPI4H CXRIOBPl3H IOBD 35 H /\ CXR SEARCH ERI 0 CXR rOB PI 2 H CXR lOB PI 1 H CXR SEARCH ER2 f\ 0 Figure 4-6 RPIO Condition Register, Block Diagram 4- I I The channel control parity error flop is direct set by IC CON PAR ERROR Land CC STRTSCH L. It is cleared during a CONO by IOBD 24 H, which also clears the channel data parity error flop. The CXR CHAN DATA PE flop is direct set when IC DATA PARITY ERROR Lis ANDed with CC STRTSCH H. IC DATA PARITY ERROR L is true during a CONI when either Channel Data Word Parity Error, Channel Control Word Parity Error, Disk Word Parity Error, or Disk Sector Parity Error are true. The flop is cleared during a CO NO by the combination of IBC CON SET Hand IOBD 24 H, which, in turn, clears the parity error conditions (lOBD 14-17 of that same word). The CXR DISK WD PE flop is cleared when IOBD 24 H is true and is direct set on a DTC DATA STROBE L by ANDing DTC PAR CONT(1) L with DTC READ DATA (1) L and DTC PARITY (0) L. The CXR NON EX MEM flop is direct set by IC NO SUCH MEM and CC STRTSCH L. During a CONI, this flop indicates that the channel attempted to access a nonexistent memory location. During a CONO, the flop is reset by the combination of IOBD 23 Hand IBC CONSET H. The CXR CW XFER COMP flop is direct set by IC WR CON WD COMPL. This condition causes the channel to store the current contents of the data address register and the control word address register in memory location B + 1, where B (an even number) is the Initial Channel Control Word Address. The corresponding CONI bit, IOBD 30, indicates that the operation is complete. Any channel termination causes the control word to be written, but CONI bit 30 is only set when the operation was requested during a CONO. The Search Error flops (CXR SEARCH ERO-2) count DSBC SEL INDEX L pulses from the disk presently in search mode (DTC SEARCH (1) L). During a CONI, they indicate that the cylinder, surface, and sector fields of the most recently executed read data or write data instruction could not be compared with corresponding fields of any sector on the addressed track. If SRCH COMP was set and a header (other than the first header in a multiple sector operation) was read incorrectly, bit 2 will be set. If IOBD 21 H is set during a CONO, it is ANDed with IBC CONSET H to reset all three flops, thereby clearing the SRCH flag. I There are three flops that can be set during a DA TAO instruction to disable certain parity error stops to data transmission. IOBD 24 H, when set during a Read Data instruction, is ANDed with IBC SET DAR ETC A H to set CXR DIS DSPE STOP. Under this condition, a longitudinal parity error sets the longitudinal parity error bit, but will not terminate data transmission. When IOBD 25 H is set during a Write Data instruction or a Write Header and Data instruction, it prevents a channel data word parity error from stopping transmission. IOBD 25 H is ANDed with IBC SET DAR ETC A H to set the CXR DIS CDPE STOP flop. If IOBD 26 H is set during a Read Data instruction, it will disable the disk word parity error stop in a similar manner by setting the CXR DIS DWPE STOP flop. I The CXR ILLEGAL WRITE flop is set by CC ILLEGAL WRITE L when either IBC BUSY is true or CC PREVENT TEST is false. During a CONI, this indicates that a Write Header and Data or Write Data instruction addressed a disk drive whose READ-WRITE/READ ONLY switch was in the READ ONLY position, or it indicates that a write operation was in process when a sector pulse was received. This flop can be reset during a CONO by setting IOBD 26 H at IBC CONSET H time, thereby clearing the ILL WR flag. The CXR ILL COM WL BUSY flop is set during IBC DATAO SET L by IBC DEVICE SELECTED Land IBC BUSY (1) H, thus indicating that a DATAO was issued while the BUSY flag was up. This causes the second command to be ignored. It is reset during a CONO (IBC CONSET H) by IOBD 27 H, which clears the ILL COM flag. CXR OVERRUN is set by DTC OVERRUN H to indicate, during a CONI, that the channel failed to respond to a request for a data word, or failed to accept a data word fast enough during a data transfer. During a CONO, IOBD 22 HANDed with IBC CONSET H clears the OVERRUN flag by resetting this flop. 4-12 Whenever the interface power supply voltages are out of tolerance, the PS FAIL module will direct set the CXR PS FAIL flop and turn on DONE causing the transfer to terminate at the end of the current sector. This flop cannot be reset until power supply voltages are within tolerance. At that time, 10BD 20 HANDed with IBC CON SET H clears the PS FAIL flop. CXR DISK NOT RDY is an output of the condition register. This signal results from either DSBC FILE UNSAFE, -DSBC SEL UNIT READY H, or ..... DSBC SEL UNIT ON LINE H. 4.7.4 Data Address Register The RPIO Data Address Register is shown in Figure 4-7 and in DWG RPIO-O-DAR. This register defines the entire data address and consists of four sub-registers to describe the drive selected (3 bits), the cylinder desired (8 bits), the surface on which the data resides (5 bits), and the specific sector to be located (5 bits). The setting of the flops is effected either by switch panel controls which direct set the appropriate flops during local mode operation (lBC LOCAL (I) L), or by the individual states of 10BD bits 03-23 received during a DAT AO and enabled by IBC SET DAR ETC A/B H. All flops are cleared by IBC INITIAL CLEAR A/B H. 4.7.5 Longitudinal Parity Register The RPIO Longitudinal Parity Register is shown in simplified form in Figure 4-8 and in DWG RPIO-O-LPR. Data from SR BUF00-05 is exclusive ORed and applied to LPR30-35 by DTC LOAD LPR H. On receipt of each DTC SHiFf LPR B or C, the contents of each column of flops are shifted to the next lower order set of six flops. LPROO-05 are tied back to LPR30-35 through AND/OR gating. All flops are cleared by DTC CLEAR LPR H. 4.7.6 Shift Register The RPIO Shift Register is shown in simplified form in Figure 4-9 and in DWG RPIO-O-SR. The circuit comprises a six-bit shift register interconnected to a six-bit shift register buffer. Input is at SR5. SR BUFOO-05 flops are all direct set by the OR of SRO-5 and AROO-05, each ANDed by its DTC enabling signal. The signals designated as SRO-5(L)L and SR BUFOO-05(L) L feed individual lights on the indicator panel. 4.8 RPI0 Control Circuits 4.8.1 Channel Control The RPIO Channel Control is shown in DWG RPIO-O-CC. The circuit serves as an interface with the DFIO Data Channel. In order for the RPIO to gain access to the data channel, it must transmit CHANNEL START to the channel and it must receive CHANNEL BUSY from the channel. If the synchronizer is not actively engaged with the data channel, it relays the CHANNEL START and CHANNEL BUSY to another I/O device and is prevented from generating its own CHANNEL START. I Either the RPI 0 or the DFIO can terminate operation. If the DFIO terminates operation, it removes CHANNEL BUSY, and the RPIO negates CHANNEL START. Ifthe RPIO terminates operation, it removes CHANNEL START, and the DFIO negates CHANNEL BUSY. At this time, the RPIO inhibits the generation or relaying of CHANNEL START for 500 ns, a requirement imposed by the DFIO. In operation, the RPIO requests access by generating CHANNEL START and is answered by CHANNEL BUSY from the channel. This acknowledges that the RPIO has access. The RPIO then generates DEVICE PULSE, which transfers the ICWA to the channel where it is processed and evaluated. When this is completed, data transfer begins, the direction of which is determined by SAWRITE. 4-13 IBC LOCAL (1) L SWP DRIVE 0 L ---10 lOBO 04 H SWP DRIVE 2 L ---10 1 ,,1 ~ lOBO 03 H SWP DRIVE 1 L IBC INITIAL CLEAR BH IBC IBC SET INITIAL DAR ETC CLEAR AH AH ~ -2J IJ\l p lOBO 05 H 8- 1 lOBO 06 H DAR DRIVE 00 0 DAR SU 07 L - 06 L '-- 8- 05 L 1 BINARY TO OCTAL CONV. DAR DRIVE 01 0 C~ti2B L -- ~~t 64 --.--. 03 L 02 L 1 DAR DRIVE 02 0 OIL -SWP CYL 64 L ~~t 32H 10BD19H SWP SEC - pr 8- .-P 10BO 20 H .- SWP SEC 02 L ~ lOBO 21 H SWP SEC 03 L lOBO 22 H SWP SEC lOBO 23 H - 8- .--r;-, L:J lOBO 09 H lOBO 14 H f--1 ~ 1 DAR SEC 02 0 '-- 8- P SWP SURF 01 L---IO ~ lOBO 15 H '-1 SWP SURF 02 L - - ~ lOBO 16 H ~~~F 03 L lOBO 17 H ---10 ~ 8 DAR SEC 03 '-- 8- F--1 SWP SURF 04 L 1 DAR SURF 00 0 I-- 8- lOBO lB H DAR SEC 04 0 I DAR SURF 01 I--- P SWP CYL OB H 10BD 10 H -SWP CYL OB L ~~~04 H - tr;"t p J-;l -- ~. ~ P t"f;1 p - fA1 - P ~ j....:..:...I 8- 8- f-----..J 1 DAR SURF 02 -SWP CYL 04 L ~ SWP CYL 02 H ~ 10B012 H DAR SURF 03 -SWP CYL 02 L 0 I-- 8- -- I,\l P ~ .....:..:.J I ~ 1 SWP CYL 01 H lOBO 13 H - I,\lI,\l - P p DAR SURF 04 ~ "-- t";l - lOBO II H I.l -~ -SWP CYL 16 L F--- 0 0 04 L ~ 1,:1 DAR SEC 01 f--- 8- 1;1 DAR SEC 00 0 0 I;:l ~ 1 L SWP CYL 16 H ~ f--- I;:l 01 L IBC SET DAR ETC B f--- P lOBO OB H C~~P32 SWP SURF OOL - 1;1 P ..........I;l 00 L l...-- SWP SEC 00 L ~ 04 L f--- IBC INITIAL CLEAR CH H r;, 10BD 07 H - 8- p" I SWPCYL 12B.H--+--Oo ~ -SWP CYL 01 L -- f-;;:l 8- 1 DAR CYL 12B 0 I I--- 8- 1 DAR CYL 64 0 I ~ ~ 8- I DAR CYL 32 0 I I-~ ~ 1 DAR CYL 16 0 I I--- 8I ~ f-1 DAR CYL OB 0 I--- 8- F-----l 1 DAR CYL 04 0 I - 8I 8- I--1 DAR CYL 02 0 I--~ 1 DAR CYL 01 ~ L.J Figure 4-7 RPIO Data Address Register, Block Diagram (Revised) 4-14 ~ 10-0511 DTC CLEAR LPR DTC SHIFT LPR DTC LOAD LPR ---+---, ~ ~+-------------~----------------------------~----+------, SR aUF 00 (1 ) H TO } LPR 24 ---+-... LPR 00 o ~ ~+-----------+-------~----------------~~~----~------~ SR aUF 01 (1) H _.J -.r- SR aUF 02 (1) H - ' SR aUF 03 (1) H SR aUF 04 (1 ) H LPR LPR 31-34 II SAME ----L _ ---+-... 06~29 LpR 01-04 SAME SAME II I _--.J -I 1 SR aUF 05 (I) H -I ~---._ LPR 35 FROM{ LPR 01----+- 11 o ~ ~--------------------------------~ 10-0512 Figure 4-8 RPlO Longitudinal Parity Register, Block Diagram 4-15 DTC DTC LOAD SHIFT SR FM SRL LPR L DTC LOAD SR FM AR L AR05 (t) L rr;t LPR05 (0) L OTC READ BIT (t) L ----0 DTC WRITE ENABLE L ~ DTC READ BIT (0) L AI ~ ...:.:J DTC LOAD BUF FM AR L DTC LOAD BUF FM SR L ";l ~~ ..:.:..J SR5 (LI L ~ SR BUF05 III L I SR BUF 05 SR5 $-~ ~ ~ AR05(0)L L.J AR04 (I) L tAl ~ LPR04 (0) L ~ ~ ~ 0 L-- I;l f-:.:-J ~&r---;- SR41LIL ~ SR BUF 04 (Ll L I SR BUF 04 SR4 G: 0 '--- i;0 AR04 (0) L LPROI- 03 (0) L AROI-03 (t) L Iro I ~- ~ -- - - - - - - - - - - - -r- - SR3 A FROM L ( OI ~ -- -- FROM SRI (1) - - -- - - - - - - - -- - - -r- - rt;L LPROO (0) L L-J ~ L.:.J ~&----;- -- -- SR BUFOI-03ILl L ~ SROILIL tJP -y-~ DTC SR JAM H t"f:l L.J ~ Figure 4-9 RPlO Shift Register, Block Diagram 4-16 --- --.J 5RI-3 (LI L t-;J SRO AROO (01 L "I -r TO SR3 A (SAME AS A BOVE I AROO (11 L " 0 L-- SR BUFOO III L I SR BUF 00 0 ----; IO~ 0513 Synchronization of transfers between the Data Channel and the RPIO is achieved by a CHANNEL PULSE issued by the channel and DEVICE PULSE generated by the RPIO. Regardless of the direction of transfer, these pulses alternate on each word transferred and perform a bookkeeping function on that transfer. When the channel has a word ready for transfer during a write, it issues a CHANNEL PULSE to the RPIO implying that it may take the word. When the RPIO has taken that word, it sends a DEVICE PULSE to the channel indicating that it is ready for the next word. When the next word is ready, the Data Channel issues another CHANNEL PULSE; when that word is transferred, the RPIO issues another DEVICE PULSE. This dialogue continues until the desired number of words have been transferred. When the channel is ready to receive a word from the RPIO during a read, it issues a CHANNEL PULSE to the RPIO indicating its readiness. When the RPIO places the word on line, it sends a DEVICE PULSE to the channel indicating that it may take that word. When transfer is complete, the Data Channel issues another CHANNEL PULSE; when that word is on line, the RPIO issues another DEVICE PULSE. This dialogue continues until the desired number of words have been transferred. The CHANNEL and DEVICE pulses alternate under normal operation; this fact is used as a bookkeeping arrangement on transfer. If any pulse occurs twice without the other, an error or overrun is indicated. At termination, the data channel sets IDLE and removes the CHANNEL BUSY which results in the resetting of the CC ACTIVE flop in the RPIO. 4.8.2 Data Transfer Control The RPIO Data Transfer Control is shown in DWG RPIO-O-DTC. This circuit functions as a traffic manager; it determines the mode of operation of the synchronizer and the direction in which information will flow between Disk and Processor. As shown in Figure 4-10, the DTC OP CODE 00-02 flops are cleared by IBC INITIAL CLEAR A H. These OP CODE flops can be either set by IOBDOO-02 H in combination with IBC SET DAR ETC B H, or direct set by SWP OPO-2 L when ANDed with IBC LOAD TEST C L. When the outputs are decoded, they result in one of various operation commands to the device. 4.8.2.1 Read Data - If DTC READ DATA COM H is decoded, it sets the DTC SEARCH flop if ANDed with CC STRTSCH H and enables the DTC READ GAP flop to be set after the header is read when triggered by the leading edge of -DTC SRCH COMP STRB H (see Figure 4-11). Note that each flop pertai!1S to a portion of the disk format. I I a. When DTC SEARCH flop sets, it ANDs with DTC SEARCH SYNC H to set DTC READ REFUSE (DTC SEARCH SYNC is DTC SECTOR DL Y H + 350 J.Ls). When the READ REFUSE flop sets, it conditions the setting of DTC READ HEADER flop which is set on receipt of DTC READ CLOCK PULSE L if DTC READ BIT (I) L is present and if the READ HEADER flop is reset at that time. b. When DTC READ GAP flop.,sets, it ANDs with DTC BETA GAP H (the OR of DTC SRCH COMP STROB H and either DTC RPOI H or DTC RP02 H) and DTC SET READ DATA H to set DTC READ DATA flop. The ORed delays (88 J.LS for RPOI and 44 J.LS for RP02) are adjusted for the relative gap widths at nominal rotating speeds for each disk type. When DTC SET RD/WR LPR H is present, DTC READ DATA (I) L sets DTC READ LPR flop when WDC WORD COUNT EQ 00 L is asserted, thereby signalling the end of data. When the LPR flop sets, it resets the DTC READ DATA flop. 4-17 IBC LOAD TEST C L SWP OP 0 L IBC INITIAL CLEAR A H 1\ lOBO 00 H I oTC OP CODE 000 oTC READ DATA COM H OTC WRITE DATA COM H SWP OP 1 L lOBO 01 H DTC READ IMAGE COM H 1\ 1 OTC OP CODE 01 0 SWP OP 2 L oTC WRITE HoR COM H DECODER OTC SEEK COM H II OTC CLEAR ATTN H lOBO 02 H 1 OTC OP CODE 02 0 IBC SET DAR ETC BH oTC NO OP H OTC RESTORE H -=- IO·O~14 Figure 4-10 DTC OP Decoding, Block Diagram (Revised) oTC READ DATA COM H CC STRTSCH H oTC SEARCH SYNC H oTC READ CLOCK PULSE L 1\ OTC SEARCH oTC READ REFUSE 0 0 OTC READ HEADER 0 oTC READ BIT (1) L -OTC SRCH COMP STRB H 1\ oTC READ GAP 1\ OTC READ DATA 0 oTC READ LPR 0 OTC BETA GAP H 0 oTC SET RO/WR LPR H lo-oele Figure 4-11 DTC Read Data Command, Block Diagram (Revised) 4-18 4.8.2.2 Write Data - If a DTC WRITE DATA COM H is decoded, it sets the DTC SEARCH flop if ANDed with CC STRTSCH H, and enables setting of the WRITE GAP flop after the header is read (see Fi!ure 4-12). NOTE Each flop pertains to a portion of the disk format; the synchronizer must read a header before writing data. a. When DTC SEARCH flop sets, it sets READ REFUSE flop and, in turn, sets READ HEADER flop in the same manner as in a read data operation. Assertion of DTC CLR READ HDR H resets DTC READ HEADER flop. After a 3-J.I.s delay, DTC READ HEADER (0) H sets WRITE GAP (the delay prevents the header parity bit from being destroyed). b. When WRITE GAP flops sets, it conditions the setting of DTC WRITE DATA flop. WDC DATA WD CT04 (I) LANDed with the condition DTC PAR CONT-+O, sets the DTC WRITE DATA flop to indicate that a sync bit has just been written. DTC WRITE DATA (1) H resets DTC WRITE GAP flop and conditions the setting of DTC WRITE LPR. When DTC SET RD/WR LPR H goes High, WRITE LPR will set, thereby clearing DTC WRITE DATA flop. I I 2.8.2.3 Write Headers and Data - If a DTC WRITE HDR COM H is decoded (see Figure 4-13), it conditions DTC W H INDEX flop which sets when DSBC SEL INDEX goes High. In addition, DTC WRITE HDR COM H enables DTC WRITE DATA flop to set on a DTC WRITE CLOCK DLY L when either (a) WDC DATA WD CTOI and 04 are on a I and an RP02 is in use (-DTC RPOI L), or (b) WDC DATA WD CT02 and 03 are on a I and an RPOI is in use (DTC RPOI L). a. When DTC W H INDEX flop sets (it can only be set if the DTC W H LOCKOUT switch is disabled), it ANDs with DTC SECTOR DL Y H to set DTC WRITE HEADER flop. (DTC SECTOR DLY is a 10-J.I.s delay on DTC SELECTED SECTOR II /\ IBC BUSY (1) H to allow setting of Head Register in multiple sector reads and writes.) DTC WRITE HEADER (1) H then asserts DTC WRITE ENABLE L. If CC ACTIVE is false at this time, it asserts DTC OVERRUN H and also ANDs with IBC LOCAL (0) L to generate DTC SHIFT CT 0 PLS H/L. In addition, it generates DTC SET WRITE Hand ORs with DTC WRITE DATA (1) H to yield DTC WRITE HDR /\ DATAL which conditions the setting of DTC PREVENT TERM flop. b. When DTC WRITE DATA flop sets, it resets DTC WRITE HEADER and sets DTC WRITE LPR flop when WDC WORD COUNT EQ 00 L is asserted. The setting of WRITE LPR flop resets DTC WRITE DATA. The DTC WRITE LPR flop resets when WDC DATA WD CT06 (I) Hand DTC PAR CONT (0) H coincide. 4.8.2.4 Oear Attentions - If lOBO 00, 01, and 02 are decoded as 101 (the CLEAR ATTENTIONS command), 1 IBC SET DAR ETC B produces DTC CLEAR ATTN. When combined with IOBD 27-34, this resets any of the DTC ATTN flip-flops (see Figure 4-14). Note that if an IBC CLEAR ATTN H or an IC CROBAR H is received, all DTC ATTN flops will be cleared simultaneously. These flops are set by DTC ATTN 00-07 H, representing up to eight possible drives. The DTC ATTN signals are received as MPX ATTN 00-07 L from the multiplexer and are inverted prior to being applied to their respective flops. 4.8.2.5 Restore - If DTC RESTORE H is decoded, it ANDs with IBC SET DAR ETC DL Y H to generate the DTC TAG and BUS LINE strobes (see Figure 4-15). In addition, DTC RESTORE H is ANDed with DTC BUS LINE STROBE H and is sent to the disk as DSBC UB 6 L. 4-19 >-t SECTOR --<350 SEC PULSE ,. DTC WRITE DATA COM H C C STRTSCH H DTC READ CLOCK PULSE L DTC SEARCH SYNC H 1\ DTC PAR CONT (0) H DTC SET RD/WR LPR H DTC SEARCH COMP (I) L 1 DTC WRITE LPR o 3j1sec 10-0516 Figure 4-12 DTC Write Data Command, Block Diagram (Revised) DTC WRITE HDR COM CC IBC ACTIVE LOCAL (0) (0) DTC SECTOR DLY H H H L 1--4--_ DTC OVERRUN H ~-+-_ DTC WRITE ENABLE L DSBC SEL INDEX H - - - - - . I 1\ DTC SHIFT CT 0 PLS H 1------<.. DTC WRITE HEADER DTC WH INDEX o o 1----_ r EQ 00 L DTC PREVENT TERM - DTC RPOI L o WDC DATA WD CT 01 (1) L WDC DATA WD CT 02 (1) L DTC WRITE HDR V DATA L WDC WORD COUNT LOCKOUT WDC DATA WD CT 04 (1) L ~---. DTC SET WRITE H DTC WRITE LPR DTC WRITE DATA o o WDC DATA WD CT 03 (1) L DTC RPOI L DTC PAR CONT (0) WDC DATA WD CT H 06 (1)H Figure 4-13 DTC Write Headers and Data Command, Block Diagram 4-20 10-0517 The Tag Lines indicate how information present on the Bus Lines is to be used. The Bus Lines contain either control information or address information. The Tag and Bus Line Strobe waveforms are shown in Figure 4-16. Note that on input of either DTC SET HD ADV (I) L, DTC SET HD REG (I) L, DTC CLEAR HD REG (I) L, DTC SET CYL (1) H, DTC SEEK START (1) L, or DTC RESTORE H as described above, the resultant signal encounters various delays that control the set and reset times of an S202 Type flop. The resultant Tag and Bus Line Strobes are sent to the disk drivers shown in DWG RPIO-O-DSBC along with their appropriate disk commands where they are decoded. The Bus Line Strobes condition the gates. Then, in the middle of the Bus Line Strobe, when the lines have had time to settle, the Tag Lines strobe the information down the line to the disk. IBC CLEAR ATTN H DTC ATTN 00 H - - - IC -THRU- - CROBAR H DTC -ATTN - 07 H o o DTC CA\~ANR_~r-'-- - - - THRU - - - - ............. H lOBD IOBD 27 34 10 -0518 Figure 4-14 DTC Clear Attentions Command, Block Diagram (Revised) DTC RESTORE H TO OSBC 'V ",J IBC SET DAR ETC DLY H 1~s -\. - OTC TAG LINE STROBE L - DTC TAG LINE STROBE H 1~s 1 DTC BUS LINE STROBE L 0 OTC BUS LINE STROBE H S202 DTC DTC DTC OTC DTC SET HD ADV (1) L SET HD REG (1) L CLEAR HD REG (1) H SET CYL (1) L SEEK START ] V :l -t [ \. 1~s J-10-0519 Figure 4-15 DTC Restore Command, Block Diagram 4-21 4.8.2.6 Seek - If a DTC SEEK COM H is decoded, it ANDs with IBC SET DAR ETC DLY to set DTC SET CYL flop (see Figure 4-17). When DTC SET CYL flop sets, it initiates the BUS LINE STROBEs and conditions the setting of DTC SEEK START flop by -DTC BUS LINE STROBE H. DTC SEEK START (1) Lis ANDed with DTC BUS LINE STROBE H in DWG RPIO-O-DSBC where it is sent to the disk as DSBC UB 2 L. INPUT - _...... OTC BUS liNE STROBE L - - . . . , -OTC TAG liNE STROBE l - - - - -...... OTC BUS LINE STROBE H - -......... -OTC TAG LINE STROBE H - - - - - - , to-0520 Figure 4-16 Tag and Bus Line Strobe Waveforms OTC SEEK COM H IBC SETOAR ETC OlY l TO OSBC -OTC BUS LINE STROBE H TAGS BUS LINE STROBE DELAYS 1 - - - - - TO OSBC 10-0535 Figure 4-17 DTC Seek Command, Block Diagram 4.8.3 I/O Bus Control The RPIO I/O Bus Control regulates the interchange of data and control signals on the bidirectional I/O bus lines which carry data and status information, device selection codes, and control signals between the RPIO Synchronizer and the PDP-l 0 Processor (see DWG RPIO-O-IBC). The device select code bits IC IOS03-09 L are ANDed with IBC LOCAL (0) L to yield IBC DEVICE SELECTED Hand IBC DEVICE SELECTED L. If the selection bits contain the RPIO device selection code (250 or 254) and if the RPIO is not in local mode, the RPIO is selected. This is the basic activating level for all RPIO functions. The performance of all basic instructions depends on the presence of this level. When the READIN or RESET switch is pressed on the PDP-lO Processor or when a programmed reset is issued, IC lOB RESET L is generated, which halts all motion in the RPIO and clears all conditions that initiate an interrupt. This condition prevails until the RPIO is reactivated by a CONO command. 4-22 In the RPIO, IC lOB RESET LANDed with IBC LOCAL (0) L, results in IBC POWER CLEAR Hand L which is used in the following ways in the device; a. To direct set IBC GEN CLR. b. To generate, after hIs delay, IBC CLEAR ATTN. c. To assert IBC CON CLR H which is ANDed with IOBD 32H to set IBC DONE. d. To set IBC DONE. e. To set IBC STOP. f. To reset IBC LOCAL. The IBC LOCAL START flop is held in the direct reset condition when the switch panel START switch is in the o condition ("'SWP START L), the switch panel STOP switch has been depressed (lBC STOP (1) L), and IBC BUSY is on a O. By activating the START switch (SWP START H), the IBC LOCAL START flop will set. As a result, the IBC STOP flop resets and the IBC GEN CLR flop is set (if -SWP OPOO L is present). IBC GEN CLEAR (1) L conditions the set gate on IBC LOCAL flop, which can then be direct set by SWP LOCAL SET L. 4.8.4 RPIO Read Data Separator The Read Data Separator (RDS) is shown in DWG RPlO-O-RDS. This circuit enables the controller to read information from any disk pack that has been previously recorded by an RPIO, irrespective of drive speed differentials between time of write and time of read, or any other variables that might cause the recorded data to reside on the disk in an unpredictable manner (provided those variables are within certain predetermined limits). During a read, the circuit supplies the controller with clock pulses (via Data Window ~ 0) and DATA OUT pulses (indicating that a 1 bit was read). A crystal clock is used to strobe data pulses and clock pulses at the time the data is recorded; consequently, the average frequency of data read from the disk should be constant. However, in reality it is not. Due to a phenomenon called "bit shift", timing between individual pulses varies somewhat because of speed variations in drives and a phenomenon inherent to magnetic devices termed "pulse crowding." Figure 4-18 illustrates the effects of these variables. In "a" of Figure 4-18, the ideal theoretical waveforms are shown for raw data consisting of all Os, Os and 1s, and all 1s. In "b", the effects of pulse crowding are shown wherein the location of a pulse just recorded will be displaced by the next recorded pulse. The pulse crowding effect becomes more pronounced the closer pulses occur to one another. Because of this effect 1) there appears to be no displacement of clock pulses when recording an all Os data pattern, 2) there is a predictable + and - shift of clock pulses either side of 1s in an alternate data pattern, and 3) there is an unpredictable variance in clock pulses when recording an all 1s data pattern. In "c" of Figure 4-18, the effect of drive speed differentials is shown on an all Os data pattern, first with speed of write greater than speed of read, and then with the opposite conditions true. In the third waveform of "c", the effect of pulse crowding has been added to a speed variation. NOTE The individual shifts of clocks from their normal positions vary from pulse to pulse producing an overall variance called "jitter." 4-23 CLOCK DATA CLOCK DATA ~ RAW DATA 0 S CLOCK ~ DATA CLOCK ~ DATA CLOCK ~ DATA ~ - - - - - - 1 AL --"1-"---1A'----"O-"---JAL--"-1"---..JAL--,,O-.---1AL--.1 - . - - } IDEAL A RAW DATA 0S/1. _ _ _ _ _J "1" "1" "1" "I" "I" '0' '0' '0' '0' '0' WAVEFORMS RAW DATA 1. _ _ _ _ _J RAW DATA O. B ----....J~"---.-I.----.J~ --.-O-,---J~I....--'-I-.--J~"---.-o,----l~"---'~-I'--} A ~, A" n A A --J1,1'--..:..--...J!'! I:L-...J:I_:-_J 'I': -:+~f":;I' ~-~:"I' 1Hi-'I'-..j-~~ '!,. ... 1'Tl, RAW DATA Oslls _ _ _ _ L_---'_~L__.J:I'---___'_...J _ _ _J..j, _oJ: RAW DATA 15 :,--':"', ~-tJ. ~ I : --;6:-- ~ I RAW DATA Os ---: --:ll~ I ~ ~ "Q" 110" ~ r- I "a" ~ CROWDING ........ ~ I ~:-- ~ I ~ "0 II --..... "0" _..J:AI;-: -.J~L---'--,,-O'-' ....L:_ _ _ _ _..... ....J~L~------..J,A~~----. . . A~~____. ...:!...JAL~ . . ___.! .W<~R ~iFEF~~ENTIALS ':""--"-0'-' ---"o-"-.J:AI.::---,,o-" RAW DATA Os _ _ _ _ _ _ , "0" ----:.,-H----, -.:!::. --..J~'----"-,---In. . ~ II ~ _.!!.W>::.!!R} ONLY ....:..J:, "1" RAW DATA O./ls _ _ _ PULSE- I r- ------....L---"o-,,---.J:A~' , c I II ONLY "1" _....In ... ll..... ,t' t PC ~'. ~ "0" "1" ~'--...:---InL-....:W::.:<~R SPEED ~ : ~6~ t ~ 6. ;... +P.c. VARY' jiTTER + DIRECTION ~ --iVARIANtE:,- 10-0538 Figure 4-18 Sources of Jitter in Disk Playback There is no guarantee that an individual disk pack will always be read on the same drive on which it was written, or that the drive speed of write will be exactly the same as the speed of read even on the same drive. Therefore, a means must be provided that enables the controller to read data in a jitter environment provided the jitter does not exceed certain specified limits. The reading of this data is accomplished by a timed sampling method called "windowing" in which the controller is forced to read during a variable period of time after the average occurrence of each clock pulse. The time period is a function of the deviation of each clock pulse from normal with respect to the deviation of the previous clock pulse. A one-shot type of separator cannot be used because a single value measured from one pulse cannot be found which provides a full window for the next and only the next pulse. However, because bit shift is measured by the time difference (either plus or minus) from the time a bit was recorded, windowing can be achieved if the window generator is aligned with the time each pulse was recorded rather than on the actual pulse detected and by aligning on the average of the clock bits coming in rather than on each succeeding bit. I This averaging is achieved by the VFO clock circuit comprising: flops RDS ERR A and B, the module B410, and the analog circuit G589 or G590. In operation, the VFO clock frequency slows down before the first sync field because no pulses have been coming in (0 frequency). Thus, the VFO clock requires considerable time to come up to frequency (see Figure 4-19). For this reason, the first sync field in the format must be approximately 350 !1S. The second sync field need not be as long (88 !1S for RPO I and 44 !1S for RP02) because the VFO clock is up to frequency and needs only to realign itself slightly as a result of the switching discontinuity from reading the header to writing data. 4-24 SLOW START UP ON FREQUENCY BEFORE SYNC FIELD 10-0537 Figure 4-19 VFO Startup Waveform During each sync field the RDS must use all clock pulses received to achieve synchronization. Window generation must be disabled at these times because misalignment can mask some clock pulses. The signal RDS SYNC FIELD ENBL is generated during these periods to bypass window selection. This signal is removed after sufficient time has passed to ensure that the window is in alignment. To provide the averaging effect, the data window is toggled by the VFO clock rather than by incoming clock pulses that contain the jitter. The RDS ERR A and B flops serve as a phase comparator. When these two flops are in different states, correction voltage is applied to the VFO clock. The correction voltage, resulting in either faster or slower VFO operation, is determined by the flop set to a 1. Neither flop remains on a 1 for any length of time. When both flops are on ai, a clear pulse is generated which resets both flops. Thus, the amount of time one flop is on a 1 while the other is on a 0 represents the time difference between the pulses that set the flops. The correction voltage that is applied forces the pulses to align. The two set pulses are generated by RDS DIVIDE 2 --+ 1 and RDS CLOCK DL Y. The RDS DATA WIND and RDS CLOCK WIND are toggled by the VFO clock through RDS DIVIDE 2, which halves the clock frequency; therefore, the comparator can control the toggling rate. The data window's edge is aligned to RDS CLOCK OUT (see Figure 4-20) while the clock window is aligned to RDS DIVIDE 2 --+ I and the data pulse may fall anywhere within the data window. DTC SET READ L is applied to the clear inputs to ensure that the DTC READ BIT is cleared when executing a write. THESE ARE THE TWO SIGNALS ALIGNED ROS OATA WIND RDS CLOCK OUT _ ' - -_ _' - -_ _- ' -_ _- ' - - RQS DATA our _ _-'-_ _-'-_ _-'-_ _ Figure 4-20 RDS DATA WIND Waveform A block diagram of the Read Data Separator is shown in Figure 4-21. The functional elements include a pulse shaper, a sync separator, a window positioner, a phase comparator, and a separate differential amplifier/filter for each voltage controlled oscillator (VCO). Two VCO's are provided; one for RPOI drives, the other for RP02 drives. In addition, the RDS contains a frequency divider and an optimizer that loops back to control output gating of incoming data. During the preamble or synchronization period, the input from the disk (MPX RAW DATA H) is fed to two AND gates each of which is enabled by the type of disk drive not in use. If an RP02 is in use, the gate enabled by ~DTC RPOI ENABLE H is turned on. If an RPOI is used, the opposite is true. 4-25 ----, I I -OTC RPOI ENABLE H - ; - - - - - , ROS DATA IN L ~---------------------------------------------------------------- ROS ~TA OUT H MPX RAW DATA H -...-....... - OTC RP02 ENABLE H - t - - - - - ' .....J -lr II OTC BE TA GAP OTC SEARCH SYNC H -r-----i OPTIMIZATION ROS ~~~~ I-_+-+----i o II "I -f--------' I 1 ROS CLOCK WI NO "'~+-----i II L ______________ .J OTCSET a REAOL---------------------------~------------~~+_------~ r-;INDOWPostrioNI';;G - - - - OTC RP02ENABLEL - - - --- --, I I --------------------------------~~~---_r-~I~I-_+_rt_----~---------------------------------~~--_, II II II " ~~-+-+--- RDS EXT DATA WIND ~__.....- - - - ROS __ I I I CLOCK OUT H ___ ---___ ----_---_--___ ----_----_---___ ----=:.-_-~--_-_--._J OTC RPOI ENABLEL -;-------------------------------r----~-r~-.~L_--_-----~-_--- I I L I L 1 RDS ERR A I I I v ____ J veo FAST o r---+---=----, VCO SLOW r----------------~ "-- 10-0522 - • Ad just able delays .....J RDS CLOCK DLY H I I L L Figure 4-21 RPIO Read Data Separator, Block Diagram (Revision I) 4-27 I The RDS CLOCK DLY H is used as a reference signal in setting RDS ERR B, while RDS DIVIDE 2 is used to set RDS ERR A. Ifboth RDS ERROR flops are set, a signal is generated that resets both flops. As such, they function as a phase comparator (see Figure 4-22). OUT OF PHASE OF IN PHASE OUT PHASE RDS ERRA ri. ..JL --1i RDS ERRS ----1t, , -+ J""1. I I 10-0525 Figure 4-22 RDS Error Flops Waveforms The outputs of RDS ERR A and B are fed to two differential amplifiers; each provides control voltage for individual voltage controlled oscillators (VCOs). Only one VCO is enabled at any time by the type of drive in use. The differential amplifiers are equipped with low-pass fIlters that remove jitter and random frequencies in the pulse train, thereby effectively averaging the frequency of the incoming bits. Any difference in the set times of RDS ERR A and RDS ERR B appears as a differential input to the differential amplifiers and causes an output to the VCO of such a polarity as to correct the error in VCO frequency, thereby synchronizing the VCO to the incoming clock bits. The frequency of each VCO is set at the I s rate component of the disk drive it serves. Consequently, VCO SLOW is set to operate at approximately 2.5 MHz while VCO FAST operates at approximately 5.0 MHz. The output from the enabled oscillator is used to complement a frequency divider flop (RDS DIVIDE 2) whose Is output, in turn, is applied to a window gating network (see Figure 4-23). ---JIolL.__..J!clL.__..JIolL.__.... RDS DATA IN _ _ Ic"lL_ __ ROS DATA W I N O - - - - - - - ' " " ' " DATA CLOCK WIND - - - - - - - - , RDS DIVIDE 2 - - - - - - - ' ROS DATA OUT ROS CLOCK OUT --------+----' -------1 Figure 4-23 Optimum Window Generation Waveforms The RDS DIVIDE 2 (I) pulse train, which is essentially a clock window, is applied to the RDS DATA WIND and RDS CLOCK WIND flops in complemented fashion through a latching arrangement of gates. The RDS DATA WIND and RDS CLOCK WIND flops are reset by the separated clock pulse RDS CLOCK OUT H. On the TE of RDS CLOCK OUT, the data window is opened and the clock window is closed. These conditions prevail until the RDS DIVIDE 2 once again transitions to the I state. At this time, the data window is closed and the clock window is opened. .. .i When the data window has been generated, the two delay lines associated with RDS CLOCK DLY H are adjusted to set the data and clock pulses in the center of their respective gating waveforms. 4.9 RPIO COUNTERS The sector and word counters are described in the following paragraphs. 4-28 4.9.1 Sector Counters The RP I 0 sector counter consists of eight separate sector counters which operate independently to count sectors on eight possible Disk Pack Drives (see Figure 4-24 and DWG RPIO-O-SC). Each counter utilizes the raw sector pulse train from its associated drive; a pulse that is detected by the transducer and from which index pulses have not been removed. If two pulses less than 350 JiS apart are detected, the logic interprets this as an index pulse or sector O. This detected index pulse then forms SCC X CLR PLS H, which is used to clear the sector counter. The SCC X + I pulse is formed from all other sector pulses (other than at index time) and is used to increment the sector counters. SCCO +1 PLS H SCCO CLR PLSH------~--------------~--------+_------------~---------J SCCI-S+l PLS H l SCCI-S CLR PLS H 1----------------, I I SAME AS ABOVE AND BELOW 1 L..- _ _ _ _ _ _ _ _ _ _ _ _ _ _ ---I SCC7+1 PLS H SCC7CLRPLSH------~--------------~--------+_------------~---------J 10-0525 Figure 4-24 RPlO Sector Counter, Block Diagram 4.9.2 Sector Counter Buffer I The RPI 0 Sector Counter Buffer is shown in Figure 4-25 and in DWG RPI O-O-SCB. The state of the selected sector counter is fed into the buffer from the multiplexer by SCB FM SC REG JAM L. This normally occurs 250 ns after the selected sector counter has changed its count. However, when IBC DOD CHis true (this is the time when the sector counter bits are being strobed onto the I/O bus), the sector counter buffer is prevented from changing. An SCB FM SC REG JAM L may have been suppressed during that time; therefore, an SCB FM SC REG JAM L is unconditionally generated on -IBC DOD C H. IBC DATAO SET L is used to update the Sector Counter Buffer with the DATAO that selects the drive. This prevents transfer of the old sector count back to the processor with a DATAl, when de-selecting one drive and then selecting a new one. I 4.9.3 Sector Counter Control Pulses A simplified block diagram of the RP 10 Sector Counter Control Pulses circuit is shown in Figure 4-26. Thedetailed logic appears in DWG RPIO-O-SCC. This circuit comprises eight identical sections of logic. Each section receives the DTC SEC PLS X L for a particular drive, and produces three control signals. The signal SCC X 4-29 CHANGE COUNT L is the result of inversion, pulse amplification, and reinversion. Each sector pulse is also delayed by 500 MS, ANDed with the output of the pulse amplifier, and inverted to produce SCCO + I PLS H. The output of the delay (-SCC X SS) is also ANDed with the inverted output of the pulse amplifier to yield SCC X CLR PLS H. These outputs are then applied to the sector counter and the sector counter multiplexer. lBC DATAO SET L - - - - . I SCM CHANGE COUNT L -IBC DOD C H SCM BIT 0 L ----_-+---------! -----------------------+1 1\ SCB BUF 0 0 -SCM BIT 0 H - - - - - - - 1\ SCM BIT 1 L - - - - - - - - - - - - - - 1\ SCB BUF 1 0 -SCM BIT I H SCM BIT 2 L ------------------------+1 1\ - - - - - - - - - - - - - - - - - - - - - - - + 1 1\ SCB BUF 2 0 -SCM BIT 2 H ---------------------1 1\ SCM BIT 3 L -----------------------+1 1\ SCB BUF 3 0 -SCM BIT 3 H SCM BI T 4 L - - - - - - - - - - - - - - - - - - - - - - - + 1 1\ -----------------------1 SCB BUF 4 -SCM BIT 4 H o ---------------------1 'O-O~26 Figure 4-25 RPIO Sector Counter Buffer, Block Diagram (Revised) 4-30 OTC SEC PLS 00 L --~---t----<-t 500". t-----1I----+--+-------- SCC 0 CHANGE COUNT L t----,I----+-------- SCC 0+1 PLS H '----------1 " -( SCC 055) OTC SEC PLS 01-06 L 1--------- I ---------- l + -t- (SAME AS ABOVE) L ---------- I· t---1--+---t--------- OTC SEC PLS 07 L t--f---+--------1--_ _ _ _ _-1 " t-------- SCC 0 CLR PLS H SCC 1-6 CHANGE COUNT L SCC 1+1-6+1 PLS H SCC 1-6 CLR PLS H SCC 7 CHANGE COUNT L SCC 7+1 PLS H SCC 7 CLR PLS H -(SCC 7 SS) 10-0527 Figure 4-26 RPIO Sector Counter Control Pulses, Simplified Block Diagram 4.9.4 Sector Counter Multiplexer The RPIO Sector Counter Multiplexer (DWG RPIO-O-SCM) is shown in block diagram form in Figure 4-27. The Sector Counter Multiplexer selects the outputs from one of the sector counters contained in the RPIO (eight counters are provided; one for each drive). Selection is determined by the DAR SEL DRIVE 0-7 L signals - each DAR SEL DRIVE signal corresponds to a specific disk drive. The DAR SEL DRIVE signals also enable selection of one of the eight SCC CHANGE COUNT L signals. 4.9.5 Word Counters The RPIO Word Counters are shown in block diagram form in Figure 4-28 and in DWG RPIO-O-WDC. The circuit contains two 3-bit ring-tail counters that count the six bits per byte and the six bytes per word being shifted. The circuit also contains a modulo 128 counter to count the number of words in each data field. Input is from DTC SHIFT BIT CNT L. This signal is generated in the Data Transfer Control and results from either DTC READ IMAGE (1) Land DTC READ CLOCK PULSE L; DTC WRITE CLOCK L, DTC WRITE ENABLE L, and DTC PAR CaNT (0) L; or DTC READ ENABLE L, DTC READ CLOCK PULSE L, and DTC PAR CaNT (0) L. Each DTC SHIFT BIT CNT L increments the WDC BIT SHFTCT counter by 1. At the count of 5, the gated inputs to WDC WD CT + I A & Band WDC BYTE CT + 1 become enabled. The next DTC SHIFT BIT CNT sets the three flip-flops at the same time that the bit shift counter returns to 0, producing DTC BIT SHFTCT EQ O. Setting WDC BYTE CT +1 produces an increment input to the BYTE SHFTCT counter, thus, causing it to increment by 1. The three + 1 flip-flops are cleared by DTC DATA CLOCK DLY and reset again at each BIT SHFTCT of 5. If WDC BYTE SHFTCT EQ 5 is true when the +1 flip-flops are set, the WDC DATA WD CT register increments by 1. Each complete cycle of the BYTE SHFTCT register increments the word counter until it reaches overflow at word 128. This produces WDC WORD COUNT EQ 0 L, which indicates the end of a particular data field. 4-31 DAR SEL DRIVE OL SC 0 BITO (0) L ~ DAR SEL DRIVE IL DAR SEL DRIVE 2L DAR SEL DRIVE :5L DAR SEL DRIVE 4L DAR SEL DRIVE 5L DAR S.EL DRIVE 7L ! r,;1.:':'" SC I BIT 0 (0) L v ~ L.:... SC 2 BITO (0) L L.:... (0) L "'SCM ...- BIT 0 H JA1 SC 4 BITO "L.:... (0) L ! ~ l_:~ SC 5 BIT 0 (0) L v -rt: -L.:.:.... SC 6 BIT 0 (0) L (0) L ... _t....-_~_.Io...._ --~_i.oo--_~--t-- "'SCM BITI H I I 2---.1 (0) L L"'SCM BIT 2 H I SAME AS ABOVE SCO-7 i BIT:5~ (0) L - r .rt\ -L.:. SC 7 BIT 0 SC 0-7 BIT 1 (O)L - f .r;- SC :5 BIT 0 SC 0-7 BIT DAR SEL DRIVE 6L I SC 0-7 BIT 4 _ _ ---oJI----- (0) L "'SCM BIT :5H "'SCM BIT4H SCC 0 CHANGE COUNT L SCC I CHANGE COUNT L SCC 2 CHANGE COUNT L SCC :5 CHANGE COUNT L SCC 4 CHANGE COUNT L SCC 5 CHANGE COUNT L SCC 6 CHANGE COUNT L " .... V " " SCM CHANGE COUNT H '\0 " " V 10-0528 SCC 7 CHANGE COUNT L Figure 4-27 RPIO Sector Counter Multiplexer, Block Diagram The bit and byte count flops are cleared by DTC CLEAR SHFTCT H. The word count flops are cleared by WDC CLEAR DATA WD CT H, which is the ORed result of DTC SELECTED SECTOR, DTC WRITE GAP, or DTC WRITE HEADER. 4-32 HFTCT H DTC SHIFT BIT CNT woe -<0 8- hJ"Il ~. r" ~ f" ~ N :;.ti ~ 0 .j:>. W 0- w .... ... '---;" WDC BIT SHFT CTOO 0 BYTE SHFT WDC BIT SHFT CT DI Dt-- A f-- 0 ~ ~J r+ WDC BIT A ~ ::l F-;;- -0 IWD00CTor-- L-- f- II~ f- tp- ~ i3 ,...., WDC BYTE SHFTCT EQO H t--- fA f- f- J woc WD CT +IA DTC BI SHFTC OD (I) I 1 r-- WOC DATA WD CT ~ tr 02 0 t-- f- CT02 0 '-WOC WOCT+IB I-- '---- WDC DATA WO CT ~ rrn f--'- I-- 1--.- A t---- t - 03 0 I-- A 01 I woc WD CT +IB 01 J I BYTE WOCCT +1 AI ° I-I-A I-- J Al f- WOC DATA WO CT 04 0 A fA t- DTC BI SHFTC 01 (0) I r--- r-----OTC WRITE GAP (I) H DTC WRITE GAP (0) H --=::l..-. =:3 I V I ~ W ~ i-J t-- '"Af- r----"j" f- DTC SELECTED SECTOR H tT 'I ~f- ------;- f r III ~ A I--- A r--- r-----"j : DTC SHIF BIT CNT I WDCT 01 0 r-- I-- I-- DTC DATA ClOC OlY o- A WDC BYTE SHFT ~. '-' 7f""- A :;.ti CD '"0- f- A ~ ~ ~ ~ r-- WDC ~~ WDC BYTE SHFT CTDbt-- ;;! 0 t-II--- 7d[n DATA 8- r-,J A 0 L--- ..... CD ~ WDC BIT SHFTCT EQO H WOC DATA II ,.. ~ ~J tp- WD~ (") 7 -0------;L-- ~ ~I r-- WOC BYTE SHFTCT E05 l :g~T+1A- BYTE CT+l- 8- ~J 00 :E 0 ..& ~~ L- WOC DATA WD CT ~ 05 0 t-t-- GJ 1 WOC DATA WO CT ~~ WOC CLEAR DATA OTC WRITE HEADER (0) 10-0529 WDC WORD COUNT EOO l 4.10 RPI0 COMPARATORS 4.10.1 Header Compare and Designation Error The RPI 0 Header Comparator and the circuit that brings up a designation error are shown in Figure 4-29 and in DWG RPIO-O-HCDE. Header comparison is indicated by no output (HCDE HEADER COMPARE L) from the composite AND/OR gating associated with cylinder and surface/sector comparison. The comparison operation is split in two to provide header protection by continuous monitoring of cylinder address (-HCDE CYL COMP H). Protection is realized any time a lack of cylinder comparison is combined with the completed search operation (DTC SEARCH COMP (1) L) to generate HCDE HDR READ ER H. This error condition immediately terminates operation by setting CXR SEARCH ER 2 on -DTC SRCH COMP STROB H, which fires DTC FINISH and shuts down the controller. The states of each cylinder, surface, and sector flop in the data address register are individually ANDed with the opposite state of equivalent bits in the LPR. The results of each ANDing are ORed to produce an output if any one bit state does not compare with its counterpart. Logic is provided to indicate that a drive, not included in the system, has been designated (HCDE DRIVE DES ERROR H). The SEL DRIVE signals from the data address register are applied to an OR gate in this comparator. The input to the gate can be jumpered for any illegal drives, thereby producing an error indication if one of these drives is commanded. The sector and surface designation error portion of this circuit contains a flop for each error. These flops are set by decoding the appropriate flops in the data address register. The error flops are reset by ANDing IBC CON CLR H with 10BD 28 H for sector designation error and 10BD 29 H for surface designation error. Signal DTC RPOI L is applied to the designation error logic to allow decoding of illegal addresses for either an RPOI or an RP02 drive. The setting of each flop is conditioned by the ANDing of DTC OP CODEOO (0) Land IBC SET DAR ETC DLY L. Both designation error flops are cleared by IBC INITIAL CLEAR C H. 4.11 RPIO DATA FLOW The flow diagrams contained in Volume 2 of this manual are discussed in the following paragraphs. 4.11.1 Starting On receipt of DATAO 250 or 254, IC lOB DATAO CLEAR generates IBC INITIAL CLEAR if IBC BUSY and CC ACTIVE are both false. The assertion of IBC INITIAL CLEAR generates CLR IBC GEN CLR if 10BD 00 is false when IBC LOCAL is false. The INITIAL CLEAR signal also clears ILLEGAL WRITE, ILL COM WL BUSY, OVERRUN, DISK WD PE, DISK SEC PE, PARITY ERROR, PREVENT TERM, WRITE EVEN PAR, SEARCH ER 0-2, NON EX MEM, CHAN DATA PE, CHAN CONT PE, and CW XFER COMP in the Condition Register; the cylinder, surface, sector, and drive registers in the DAR; and the OP CODE register in the DTC. In addition, when IBC INITIAL CLEAR is asserted, it clears SET CYL, SEEK START, NO SECTOR, INDEX, SET HD ADV, CLEAR HD REG, SET HD REG, HEAD SET, CHN PLS BUF, and DTC4 CI3M, also in the Data Transfer Control and it clears IBC DONE and both sector and surface designation errors in the HCDE. When IBC INITIAL CLEAR is generated, it results in DTC CLEAR A and B which clear ARO-17 and ARI8-35, respectively. It is used also to generate DTC CLEAR SHFTCT (which, in turn, clears the bit and byte counters) and to generate the DTC CLEAR PAR PLS which results in DTC CLEAR PARITY and CLR DTC PAR CONT. With all of the above conditions cleared, receipt of IC lOB DAT AO SET results in IBC DATAO SET. If the controller is busy, IBC BUSY is set. This signal ANDed with IBC DEVICE SELECTED (true only if IBC LOCAL is false) generates the ILL COM WL BUSY condition to indicate that a command was given to the control before it finished a previous command. If the synchronizer is not busy (lBC BUSY (0)), IBC SET DAR ETC A and B is generated. 4-34 DAR SEC 04 (1) H lBC CON CLR H DAR SEC 03 (1) H DAR SEC 02 (1) L lBC INITIAL CLEAR CH DAR SEC 01 (1) H 1--_-+---1---- DAR SEC 00 (1) L HCDE SEC DES ER H DAR SEC 01 (1) H HCDE SEC DES ER DAR SEC 02 (1) L DAR SEC 03 (1) L lOBO 28 H o --~----------------------------------r_~ A DTC RPOI L DTC OP CODE 00 (0) L lBC SET DAR ETC DLY L DAR SURF 01 (1) L DAR SURF 00 (1) H DAR SURF 03 (1) H 1-_-1---1------11----- HCDE SURF DES ER H DAR SURF 00 (1) L HCDE SURF DES ER DAR SURF 01 (1) H DAR SURF 02 (1) H lOBO 29 H DAR SEL DRIVE 01-07 H o ---;.~GJI-------------------------. HCDE DRIVE DES ERROR H DAR CYL 01-128 (0) L LPR 18-25 (1) L 1----------.--------_ '" HCDE CYL DAR CYL 01-128 (1) L COM P H 1------.. HCDE HDR READ ER H LPR 18-25 (0) L DAR SURF 00-04 (0) L '" HCDE SURF/SECT COMP H LPR 26-30 (1) L DTC PARITY (O)H DAR SURF 00-04 (1) L LPR 26-30 (0) L DAR SEC 00- 04 (0) L DTC SEARCH COMP (1) L LPR 31-35 (1) L DAR SEC 00-04 (I) L 10-0530 LPR 31-35 (0) L Figure 4-29 RPIO Header Compare and Designation Error, Simplified Block Diagram (Revised) 4-35 The A version of this signal loads the drive and cylinder registers in the DAR and sets disable stops in the condition register for Disk Sector Parity Error (if IOBD 24 is set), Channel Data Parity Error (if IOBD 25 is set), or Disk Word Parity Error (if IOBD 26 is set), and SET CXR WRITE EVEN PAR (if IOBD 35 is set). The B version of IBC SET DAR ETC sets the Surface, Sector, and Op Code Registers in the DAR. The Op codes are directed to the Data Transfer Control where they are decoded into the commands listed in Table 4-1. Table 4-1 Data Transfer Control Commands DTC OP CODE Bits DTCCommand 0 1 2 0 0 0 Read Data 0 0 I Write Data 0 I 0 (Not Used) 0 I I Write Hdr I 0 0 Seek I 0 I Clear Attn I 1 0 NoOp I I I Restore (Recalibrate) If the decoded command is NO OP or CLEAR ATTN, the commands are executed. If the command is RESTORE or SEEK and the controller is in Local Mode, IBC LOCAL START (DWG RPIO-O-FCL) will assert CLR IBC SET DAR ETC DLY. If the RPIO is not in Local Mode (IBC LOCAL (0», IBC BUSY (0) and IBC DEVICE SELECTED will assert CLR IBC SET DAR ETC DLY, which is combined with IBC LOCAL (0) to generate SET IBC LOAD ICWA. This ICWA signal then loads the Initial Control Word Address contained in IOBD 27-34 into bits 27-34 of the Assembly Register. After a 500 ns delay, SET IBC SET DAR ETC DLY generates CLR IBC LOAD ICWA and with DTC CLR ATTN clears the appropriate ATTN 0-7, as specified by IOBD 27-34. If a seek command is decoded, SET IBC SET DAR ETC DL Y sets DTC SET CYL which, in turn, starts the Seek operation. If a restore command is given, SET IBC SET DAR ETC DLY sets DTC BUS LINE STROBE directly, thus enabling DSBC UB 6 to execute the command. When a data transfer command is received (OP Code 00 on a 0), SET IBC SET DAR ETC DLY triggers CC PREVENT TEST. If HCDE SEC DES ER is asserted at this time, 1-+ HCDE SEC DES ER results. If HCDE SURF DES ER is asserted at this time, 1-+ HCDE SURF DES ER results. Either of these conditions raises DTC FINISH, thereby terminating operation. When CC PREVENT TEST fires, it starts the I J1S CC PREVENT TEST TIMEOUT. At the end of this delay, the conditions for CC PREVENT START are checked. The channel will not start (CC PREVENT START) if a drive designation error has been detected (HCDE DRIVE DES ERROR), the power supply voltage has dropped (CXR PS FAIL (1», a sector designation error has been indicated (HCDE SEC DES ER), the disk is not ready (CXR DISK NOT RDY), or a surface designation error has been detected (HCDE SURF DES ER). In addition, the channel will not start if the drive is in read only mode (DSBC SEL UNIT RD ONLY) and either of the two write conditions has been commanded (DTC or CODE 00(0) " DTC or CODE 02 (l ». 4-36 If CC PREVENT START is true, IBC DONE and IBC GEN CLR are both set. This condition generates CXR PI ENABLE if IBC BUSY and IBC LOCAL are both false and clears DIS DSPE STOP, DIS CDPE STOP, and DISABLE DWPE STOP in the condition register. IfCC PREVENT START is not true, IBC BUSY and CC ACTIVE BUF are set. This condition sets CC ACTIVE after 40 ns, if IC CHAN STARTED is on a 0 (proceed on DWG RP 1O-O-FCCC to start the channel). In addition, the combination of IBC BUSY (1) and CC ACTIVE BUF (1) sets DTC CLEAR HD REG if DTC OP CODE 0 is false, thereby clearing and setting the head register in the drive as shown in DWG RPIO-O-FCDC. If CC ILLEGAL WRITE is asserted at the time of CC PREVENT TEST TIMEOUT, CXR ILLEGAL WRITE is set. 4.11.2 Recognizing Headers CC ACTIVE BUFF sets as a result of CC PREVENT TEST Hand -CC PREVENT START to indicate that the RPIO is ready to assume control of the data channel as soon as the channel is free. If CC CHAN STARTED is on a 0 (indicating that no device further down the daisy chain is accessing the channel), CC ACTIVE sets. This condition results in CC CHAN START OUT and, when the channel is ready, it sends IC CHAN BUSY IN to the RPIO. At this point, the RPIO has control of the data channel and asserts CC STRT SCH. Assertion of CC STRT SCH sets DTC SEARCH and the RPIO then waits for the fIrst sec.tor pulse. On receipt of the sector pulse, DTC SECTOR DLY H is triggered. This delay allows the drive head register to increment during multiple surface data transfers (see Paragraph 4.11.6). The delay then triggers a 350-#lS delay (DTC SEARCH SYNC) which sets READ REFUSE. When READ REFUSE sets, it turns on the read circuitry (see Paragraph 4.11.5). The separator's window is bypassed during this time, but after the delay times out, DTC READ HEADER is conditioned for setting by detection of a 1 bit and the window bypass is removed. The 36 bits following the 1 bit are read into the LPR (see Paragraph 4.11.7), and when a full word has been loaded, the Byte Counter and Bit Counter return to O. At this time, DTC PAR CaNT sets indicating that the parity bit is about to be read. The clock pulse following the parity bit clears PAR CaNT (see Paragraph 4.11.10), and when parity control clears, DTC SRCH CMPR STRB is triggered. This strobe has a 600 ns delay to allow for gate delays throughout the compare circuitry. When it times out, DTC SRCH CaMP is set if no parity error occurred and the headers compare. The headers are checked via HCDE COMPARE signal which determines if the address bit is a 1 and the data bit it 0, or the address bit is a 0 and the data bit a 1. If either of these conditions is true for any bit between 18 and 35, HCDE HEADER CaMP is false. The data bits in the LPR are checked against the address bits in the DAR. If they compare, DTC SRCH CaMP sets, and DTC SEARCH clears. If they do not compare, DTC SEARCH remains set. An R302 delay is fIred unconditionally ~88 #lS for RPOI or 44 #lS for RP02) producing BETA GAP. The BETA GAP bypasses window selection in the separator to allow resynchronization of the separator. This is necessary due to the discontinuity between the header portion, which is written once, and the data portion, which can be written any time on any drive. At this point, the flow changes to either a read or a write. 4.11.3 Reading Data When DTC SRCH CaMP STRB times out (after the header has been read), it sets READ GAP. However, if DTC SRCH CaMP did not set, DTC READ GAP clears when BETA GAP times out and the controller waits for the next sector pulse. If DTC SRCH CaMP did set, READ GAP remains set, and the detection of the fIrst 1 bit then sets READ DATA. After 200 8 words are read with parity (see Paragraph 4.11.7), DTC READ LPR sets, and the next 37 bits are exclusive ORed into LPR 0-35 and LPR 36 (see Paragraph 4.11.10). When DTC PAR CaNT switches to a 0, indicating that the 37th bit has been read, DTC READ LPR clears thereby setting DTC GAP and triggering a 600-ns delay. The delay, in turn, sets CXR DISK SEC P E if any LPR bit is not on a 1. 4-37 4.11.4 Writing Data After SEARCH COMP has been set, the transition of DTC READ HEADER to 0 sets DTC WRITE GAP after a delay of 3 [JS. This delay ensures that the first bits written will not destroy the last few bits of the header. When WRITE GAP sets, the controller writes Os onto the disk without parity. After four words of Os have been written, WRITE DATA is set, and parity control switches to a 1. Parity is then written for the last sync word (this parity bit is the 1 bit that sets READ DATA during a read operation). After 2008 words of data are written (see Paragraph 4.11.8), DTC WRITE LPR sets, and the contents of the LPR are written on the disk. The controller then writes a second LPR as guard bits and, after this has been done, DTC GAP sets. The DTC ERASE flop, which controls erase current in the drive, is turned off 20 [JS after writing has stopped to allow data that was written to pass under the erase heads before they are turned off. 4.11.5 Commanding the Drive Drive commands and data are sent out on the same eight bus lines. Three tag lines indicate whether the information on these lines is data or commands. The information on the bus lines is strobed into the drive by bringing up the tag signal in the middle of the command. The only exceptions to this are read and write commands. When either of these commands is issued, both the bus line and tag line remain true throughout the time that read or write is true. These commands are executed by making SET WRITE or SET READ true by ORing the various write flops or read flops. NOTE All read or write flops are cleared by the next flop transition to a 1 state. This ensures that SET WRITE or SET READ do not momentarily go false if one flop should be slow. 4.11.6 Reading Multiple Sectors Multiple sector reads are performed only in on-line mode (not local). During on-line operations, normal termi- I nations are performed via the channel going -BUSY. If the channel stays active after transferring a sector, the RPl O continues reading. When DTC SRCH COMP STRB H is fired, if the cylinder portion of the succeeding header was read incorrectly, CXR SRCH ER 2 is set. This causes DTC FINISH to fire and shut down the controller. If the last sector read was sector 9 (4 in RPO 1), the controller moves down one surface. An advance head command to the drive, which increments the drive's head register by 1, accomplishes this move. The controller enables to determine which sector it is reading or writing after the first sector; therefore, the program must keep track of surfaces and sectors. After reading sector 9 (4 in RPO 1), an index pulse occurs that sets DTC INDEX. The next sector pulse then sets DTC ADV HEAD, which increments the drive's head register. If reading is initiated on sector 9 (4 in RPO 1), the index pulse occurs before DTC SRCH COMP sets and DTC INDEX is set by DTC SRCH COMPo NOTE The index pulse occurs within 500 ns of the sector pulse for sector 9 (4 in RP01), and not sector zero. If the heads are advanced when the drive is on the last surface, the drive sends back EOC (End of Cylinder), which terminates operation. 4-38 4.11. 7 Loading Words 4.11.7.1 Header Words - When DTC READ HEADER sets, header bits are shifted into the SR, and the Bit Counter is incremented (the bit counter is a counter that returns to 0 after six counts). When the Bit Counter returns to zero, the SR is loaded into the LPR (it is actually an exclusive-OR operation, but the LPR has already been cleared). The Byte Counter is incremented each time the Bit Counter returns to O. When the Byte Counter returns to 0, the Word Counter is incremented. When the Byte and Bit Counters both return to 0, a full header word has been read. 4.11.7.2 Data Words - Data words are loaded in the same fashion as header words except that they are loaded into the AR as well as the LPR. Each time the AR is full, the RPIO issues a device pulse indicating to the channel that data is on the lines. The channel responds with a channel pulse when it is ready to receive another word. DTC SUPR BUF LD is used to prevent the buffer from being loaded during the fIrst byte of data, because the Byte Counter is on a zero. Each parity bit is exclusive ORed into LPR 36. 4.11.8 Transferring Words 4.11.8.1 Write Header - The header words are loaded into the SR and SR BUF directly from the AR. The Bit, Byte, and Word Counters function exactly as they do in reading. 4.11.8.2 Write Data - Each data word is loaded into the AR by a channel pulse, only after a device pulse has been issued to the data channel indicating that the RPlO is ready to receive that word. The LPR is loaded only from the SR BUF. 4.11.9 Writing Headers The WRITE HEADER command starts with sector zero and writes around the pack. It is impossible to write any sector without first having written sector zero. This is mainly a software function. The controller starts writing on the sector following index and writes 36-bit words continuously until the second sync fIeld has been written, at which time the WRITE DATA mode is entered. The controller writes without parity; if parity were used, the sync fIeld would contain Is. Thus, because the header is checked for correct parity, the first bit of the first word following the header word appears as the parity bit. The software must calculate parity and supply the correct bit. This operation continues for each sector. 4.11.10 Generating Parity The PARITY CONTROL flop toggles to a 1 each time 36 bits have been read, except during the sync zones, which are indicated by READ REFUSE (1), READ GAP (1), WRITE HEADER (1), or WRITE GAP (1). The PARITY flop is toggled for each 1 bit read or written. If this flop is on a 0 at the end of 36 bits (PARITY CONTROL -+ 1), a 1 is written. During read, the parity bit toggles both the PARITY flop and the LPR 36 flop. This operation is required because LPR 36 (parity bit of LPR word) is read differently than it is written. LPR 36 is written as the parity of the LPR word but is read as the exclusive OR of the parity bits of all the data words. 4-39 4.11.11 Terminating All terminations occur when DTC FINISH is generated. Gate conditions that fire DTC FINISH are listed below by triggers. Each gate indicates a different condition. CXR SEARCH ERR (1) - Indicates that three index pulses have been received since attempting to read a header and, therefore, the header can not be found or read. CXR ILL WRITE (1) - Indicates that a write operation was commanded on a writelocked drive. CXR DISK NOT RD Y - Indicates that the controller tried to communicate with a drive that was not ready. A file unsafe condition will cause this termination. CXR DISK SEC P E - Indicates that a disk sector parity error occurred, and that the stop disable was not set. CXR DISK WD P E - Indicates that a disk word parity error occurred, and that the stop disable was not set. IBC CONSET - Indicates a programmed halt. HCDE SURF DES ER (1) - Indicates that the data transfer command specified a nonexistent surface. DTC GAP (1 )"(CC ACTIVE (O)VCC INHIBIT (1 M;XR PS FAIL) - The combination of these conditions terminates all write operations and normal read operations. DTC GAP prevents termination until the controller is between sectors. It terminates if CC ACTIVE (0) (data transfer complete), CC INHIBIT (1) (overrun or channel data parity error), or CXR PS FAIL (1) (power supply failure) are true. The presence of CC PREVENT TERM 0 prevents termination during a write until the next sector pulse is received. This operation allows erase to stay on longer than write. DSBC SEL UNIT EO CYL - Indicates that a data transfer did not terminate via the data channel before the drive head register was incremented past its last surface. CC ACTIVE (O)"CHN PULS BUF (0) - Indicates that channel access was lost and gained prior to receiving the first channel pulse. HCDE SEC DES ER (1) - Indicates that the read command specified a nonexistent sector. 4-40 Chapter 5 Maintenance 5.1 INTRODUCTION Maintenance of the RPIO conforms to the accepted maintenance procedures of all electronic equipment presently in use, i.e., an optimum amount of preventive procedures, performed on a routine schedule, can eliminate many costly equipment breakdowns and can forecast failures before they occur. When a specific item does fail, the design of the equipment allows for quick replacement of modular elements, thus restoring the main equipment to service in a minimum of time. A design objective of the RPI 0 Disk Pack Synchronizer is to provide a dependable and relatively maintenance-free assembly. This chapter contains both preventive and corrective procedures. 5.2 PREVENTIVE MAINTENANCE Preventive maintenance consists of tasks performed at periodic intervals to ensure proper equipment operation and minimum unscheduled downtime. These tasks consist of visual inspection, operational checks, adjustment, and replacement of marginal components. The preventive maintenance schedule depends on the environmental and operating conditions that exist at the installation site. Under normal environmental and work-load conditions, the recommended preventive maintenance schedule consists of inspection and cleaning every 600 hours of operation or every 4 months, whichever occurs first. However, relatively extreme conditions of temperature, humidity, dust, and/or abnormally heavy work loads demand more frequent maintenance. 5.2.1 Preventive Maintenance Procedures Preventive maintenance procedures for the RPOI and RP02 Disk Pack Drives are not included in this manual. For these procedures refer to the Vendor maintenance manual supplied with the equipment. 5.2.1.1 Mechanical Checks - Inspect the RPIO periodically as follows: a. Visually inspect the unit for general condition. b. Clean the interior and exterior of the rack using a vacuum cleaner or clean cloth moistened in nonflammable solvent. c. Inspect all wiring and cables for cuts, breaks, frays, deterioration, kinks, strain, and mechanical security. Tape, solder, or replace any defective wiring or cable covering. 5.2.1.2 Test Equipment Required - Maintenance activities for the RPI 0 require the standard test equipment and special materials listed in Table 5-1, in addition to standard hand tools, cleaners, test cables and probes. Special test equipment required for any adjustments are given as part of the adjustment procedures. 5-1 Table 5-1 Test Equipment Required Equipment Manufacturer Designation Multimeter Triplett or Simpson Model 630-NA or 260 Oscilloscope Tektronix Type 453 Clip-on Current Probe Tektronix Type P6016 XIO Probe Tektronix P6008 Recessed tip, 0.065 in. for wirewrap terminals Tektronix 206-052 Hand Unwrapping Tool Gardner-Denver 500130 Hand-Operated Wire-Wrap Tool with a 26263 bit for 24 AWG Wire and 18840 Sleeve Gardner-Denver 14HIC Module Extender DEC Type W980 Diagnostic Self-Test Routine DEC MAINDEC-IO-D5MA MAINDEC-IO-D5NB MAINDEC-IO-D50B 5.2.1.3 Electrical Checks - Perform the power supply output checks described in Table 5-2. Use a multimeter to make the output voltage measurements with the normal load connected. Use an oscilloscope to measure the ripple content on all dc outputs of the supply. Voltage measurements should be made at the logic racks. The +10 and -15 Vdc power supplies are not adjustable; therefore, if any output voltage or ripple content is not within specifications, consider the power supply defective and initiate troubleshooting procedures. Table 5-2 Power Supply Output Checks Measurement Terminals at Power Supply Output Acceplable Output Range (V) Nominal Output (Vdc) Maximum Output Ripple (mVrms) Red (+) to Black (-) +10 +9.5 to 11.0 800 Black (+) to Blue (-) -15 -14.5 to -16.0 100 NOTE This power supply is the Type 728 (728A for 50 Hz) located at the bottom of the RPIO rack. 5-2 5.2.1.4 Electronic Cheeks - Perform the following electronic checks. a. Critical Delays - Check the critical delays in the RPI0 every six months to determine that they are still within specified tolerances. These delays are listed in Table 5-3, also included in Table 5-3 is a list of allowable tolerances for each module. Replace or adjust any modules that are found to be out of tolerance. b. Margins - Check the margins for the RPIO and its companion DFIO every six months. Refer to the Margin Check Paragraph in the PDP-I 0 KAI0 Central Processor Maintenance Manual, Volume I, and to Tables 5-4 and 5-5. NOTE Before margining the RPIO, remove power and remove the W505 (PS FAIL) Module at location M02. Replace the module after margining. Table 5-3 Critical Delay Modules Drawing No. Module Type Signal Name Location Nominal Value Tolerance DTC TAG LINE STROBE F30E-M I ItS ±20% DTC-3 R302} R302 IBC-2 R302 H25E-M 500ns ±20% IBC-2 R302 IBC SET DAR ETC DLY IBC LOAD TEST B20N-V 21lS ±20% DTC-3 Table 5-4 DFIO Voltage Margins Voltage -15V +lOV Rack Row A B tttc tD E ttF ttH J K L Low High Low High 2.5 2.5 3.0 3.5 2.5 6.0 6.0 2.5 2.5 2.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 tThe B130 Modules limit the + lOY margins of panel D. ttThe B68S Modules limit the +10V margins ofpane1s F and H. tttThe R303 Module for NON-EXMEM limits the +10V margins of panel C. 5-3 Table 5-5 RPIO Voltage Margins Voltage +10V Rack Row A B C D E F H tJ K L tM ttN ttP ttR ttts tttT -15V Low High Low High 2.5 2.5 2.5 2.5 2.5 2.5 2.5 6.0 2.5 2.5 6.0 6.5 6.5 6.5 7.5 7.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 17.5 14.0 14.0 14.0 15.0 15.0 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 -12 tB68S limits +10V margins of panel J. ttWS91 and W692 limit +10V margins of panels N, P, and R. tttB410 limits +10V margins of panels S and T. 5.3 CORRECTIVE MAINTENANCE The logic description provided in this manual permits the use of standard troubleshooting techniques for isolating the trouble quickly and efficiently. For economical maintenance under most conditions, replace the inoperative module with a spare module and return the defective module to DEC for repair or replacement. 5.3.1 General Corrective Procedures Before beginning troubleshooting procedures, make certain that the processor portion of the PDP-lO, the DFI0, and I/O Interface are operating properly. Refer to the specific maintenance manual to determine the status. Also examine the maintenance log to determine if the fault has occurred before and note what steps were taken to correct the condition. Note also if a cyclic condition has occurred. Visually inspect the physical and electrical security of all cables, connectors, modules, and wiring. Check the indicator lamps for operation and their glass covers for cleanliness. In particular, check the security of ground connections between racks. Faulty grounds can produce a variety of faults. 5-4 5.3.2 Diagnostic Testing DEC provides special diagnostic programs (MAINDECs) to assist in localizing faults within the equipment. Functionally, the programs fall into two categories: test and reliability. Test programs isolate genuine go/no-go type hardware failures that are easily recognizable, while the reliability programs isolate failures that are more difficult to detect because they are marginal in nature and/or occur infrequently or sporadically. The family of test programs are written so that, when run successively, they test the equipment beginning with small portions of the hardware and gradually expand until they involve the entire machine. To accomplish this, they are built around instructions and portions of instructions whose demands on equipment capabilities progress from simple transfers and skips to the most involved data manipulations and computations. As portions of the system are proven operable, they become available to succeeding tests for use in checking out unproven portions of the machine. To perform a diagnostic routine on the RPIO alone, run tests MAINDEC-IO-DSMA and MAINDEC-IO-DSNB. If the RPlO is operating correctly, both tests should run without failure. 5.3.2.1 Vibration Tests - Many malfunctions can be located by performing a voltage margin check while running diagnostics. The RP 10 should be margined while running D5MA or D50B. The associated DF I 0 should be margined while running D5NB. In addition, a vibration test may be performed while margining the RPlO and DFIO together. 5.3.3 Adjustment Procedures The following adjustment procedures must be performed when it has been determined by diagnostics and troubleshooting techniques that a specific element is at fault but does not need replacement. 5.3.3.1 Read Data Separator Calibration - If parity errors are occurring from random drives, surfaces, or bits, the read data separator (RDS) is probably at fault. This failure can be caused by a bad module or by poor alignment. Ifit is determined that a module is at fault, the module should be replaced with one known to be good; otherwise, the following procedure should be performed. The purpose of this calibration procedure is to adjust the variable elements of the RDS so that data being read from the disk pack drive is correctly separated into data bits and clock bits under all combinations of bit shift and speed variations from the drive, and worst case circuit conditions in the RDS. All delays used in the portion of the circuitry required for operation from RP02 drives are also active when RPOI drives are being used. Therefore, all adjustments for operation with an RP02 are always required, even if RPOI drives alone are to be used. The calibration procedure is carried out using the crystal clock in the controller, and a drive is not required in order to set up the read data separator. The jumpers connected in steps 2 and 3 of the procedure ensure that all necessary signals are present. Equipment required for this calibration procedure is as follows: a. Dual-trace oscilloscope, Tektronix Type 453, Tektronix Type 454, or equivalent. b. Oscilloscope probes fitted with short (i.e., 3-in. or less) grounding leads. c. Jumper leads, 5 red jumpers (4-in.) and I yellow/white jumper (24-in.). 5-S NOTE The differential delay between probes should be less than 2 ns. This should be checked by connecting both probes to a convenient waveform (e.g., T22 H), setting the oscilloscope time base to 5 ns/div. (10 ns/div., if using 453) and measuring the delay between the channels at the -1.5V level. The following calibration procedure must be strictly adhered to. Make all adjustments as precisely as possible. Step 1 2 Procedure Remove Module Type B152 at location 129. Connect the following pins to ground: a. E32 (DTC RPOI L) b. CIOF (DTC READ HEADER (I) H) c. L22N (DTC WRITE HEADER (l) H) d. L24N (DTC READ CLOCK PULSE L) e. SI51 (Provides RDS SYNC FIELD ENB L) 3 Connect K24U (CRYSTAL CLOCK OUTPUT, 400 ns period) to S251 (MPX RAW DATA H). 4 Set oscilloscope to trigger internally from channel I; set vertical sensitivity to 1V/div. and time base to 50 ns/div. negative trigger. 5 Connect channell to T22H and adjust lower potentiometer on module B41 0 in location T22 until negative-going pulse width on oscilloscope is 50 ns measured at -1.5V points. 6 Connect S25E (MPX RAW DATA H) to ground, place channell on T29V, set for positive trigger, and adjust module B312 at location T29 until width of the pulse to ground is 50 ns measured at -1.5V points. Remove ground on S25E. 7 Connect T22V to ground. 8 Connect channel I to T22H. Set time base for 100 ns/div. Adjust upper potentiometer on module B410 in location T22 until pulses occur at intervals of 200 ns. Remove ground on T22V. 9 Connect channell to S24L and channel 2 to S24V. Adjust B312 at location S24 until the delay between S24L and S24V is 80 ns. 10 Connect channel I (only channel I is needed) to S28P and adjust B312 at location T25 until the square-wave seen at S28P is 200 ns to -3V and 200 ns to ground. II Set oscilloscope to I V/div. Set to negative trigger, internally from channel I. Set the time base to 10 ns/div. for A453 and 5 ns/div. for A454. 12 Connect channel I to S32M and channel 2 to T30H. Adjust B312 in location S24 until the falling edge of channel I waveform is aligned with the rising edge of ch31J.nel 2. Measure at -1.5V (see Figure 5-1). 5-6 _------GND CHI - - _ -+--+--+-IE--I--+-+-- t. 5 V CH2 10- 0 . . . Figure 5-1 RDS Waveform No.1 Procedure Step 13 Set time base 20 ns/div. and connect channell to M30S. Adjust calibrate control on time base until the pulses are exactly 10 divisions apart on the oscilloscope face measured at -1.5V points. (If the pulses cannot be adjusted to 10 div apart, repeat using 50 ns/div. range setting.) NOTE The time base is now calibrated on this range to be 20 nsf div. Do not move the calibrate control or the range (time/ div) control for the remainder of the RP02 procedure unless instructed to do so. 14 With channel 1 connected to T24D (RDS ERR A (0) H), and channel 2 connected to T24N (RDS ERR B (0) H), and time base set for 20 ns/div, adjust the upper potentiometer on module B410 in location T22 until the waveforms seen on channel I and channel 2 are exactly the same. ("Exactly", in this context means within the limits of oscilloscope resolution and operator ability.) 15 Connect channell to S32M (RDS CLOCK WIND (0) L), set for negative trigger, connect channel 2 to S32L and adjust B312 module at location T2s until the delay between the negative-going edge of channell and channel 2 is equal to 105 ns measured at 1.5V point (see Figure 5-2). CHI I I I I I I I+--TI-.... ~I TI=I05ns RP02 TI=I92ns RPOI 10-0"9 Figure 5-2 RDS Waveform No.2 16 Remove the following jumper to ground: E32D 5-7 Step Procedure 17 If the RPOI is not to be used with the system, remove the following jumpers: a. CIOF to ground b. L22N to ground c. L24N to ground d. S15J to ground e. K24U to S25J Replace the module Type B152 at location J29. NOTE This completes the calibration of the RP02 section of the RDS. 18 lethe RPOI is to be used with the system, proceed as follows: a. Jumper point E32H to ground. b. Check that the following points are connected: CIOF to ground L22N to ground L24N to ground SI5J to ground K24U to S25J c. Check that the module Type BI52 is removed from location J29. 19 Set oscilloscope to trigger internally from channell, vertical sensitivity set to 1 V/div, and time base on 50 ns negative trigger. 20 Connect channell to S22H and adjust lower potentiometer on module B41 0 in location S22 until pulse width on oscilloscope is 50 ns measured at the -1.5V points. 21 Connect channell to S32L (RDS DATA IN L), connect channel 2 to T27N and . adjust module B312 in location T26 until delay between channell and channel 2 is 250 ns. 22 Connect S22V to ground. 23 Connect channell to S22H. Set oscilloscope time base to 200 ns/div. Adjust upper potentiometer on module Type B410 in location S22 until pulses occur at 400 ns intervals. Remove S22V from ground. 24 Connect channell to S28P and adjust B312 at location T26 until the square-wave seen at S28P is 400 ns to -3V and 400 ns to ground. 25 Set time base on oscilloscope to 50 ns/div. Connect channell to M30S and adjust calibrate control on the oscilloscope time base until the pulses are exactly 10 divisions apart on the oscilloscope face measured at the -1.5V points. NOTE The time base is now calibrated on this range to be 40 ns/div. Do not move the calibrate control or the range (time/div.) control for the remainder of the RPOI procedure unless instructed to do so. 5-8 Step Procedure 26 Connect channell to T24D and channel 2 to T24N. Set time base for 100 ns/div. and adjust the upper potentiometer on module B410 in location S22 until the waveforms seen on channell and channel 2 are exactly the same. 27 Connect channell to S32M (RDS CLOCK WIND (0) L) set for negative trigger. Connect channel 2 to S32L and adjust B312 module in location T26 until the negative-going edges of channel I and channel 2 are 192 ns apart. Measure at the -1.5V point (see Figure 5-2). NOTE This completes the calibration of the RPOI system. 28 Remove the following jumpers: a. E32H to ground b. CIOF to ground c. L22N to ground d. L24N to ground e. S15J to ground f, K24U to S25J 29 Replace module Type B152 in location 129. The following adjustments are performed in the preceding calibration procedure: Step 5 adjusts the output pulse from B410 to a width of 50 ns. Step 6 adjusts the delay line in T29 so that incoming pulses, which are 70 ns ± 15 ns, are standardiied to a 50 ns pulse width before being fed to the remainder of the RDS circuitry. Step 7 adjusts the variable input resistor of the B41 0 clock to a setting at which a phase lock condition can be obtained in the phase lock loop. This phase lock loop consists of the B410 voltage controlled oscillator, phase error comparator flip-flops (called RD RDS ERR A and RDS ERR B), and a differential error amplifier and filter GS89 or G590. Step 10 adjusts the delay which is used to set the data and clock pulses correctly with respect to their gating waveforms. The gating waveforms are generated by the flip-flops S28 and T32, and ensure that all data bits are gated out of S32H (RDS DATA OUT H), and all clock bits are gated out of S32N. Step 14 adjusts the width of the gating waveform which is used to gate the data bits and clock bits. Step IS finally adjusts the setting of the variable input resistor in B41 0 so that the phase lock loop achieves its lock with a phase error of zero degrees between the internal oscillator (B41O) and the incoming serial stream of data and clock bits. Step 20 adjusts the width of the output pulse from B410 to 50 ns. Step 22 adjusts the variable input resistor of B410 to a setting which allows a phase lock condition to be established between the B4l 0 internal oscillator and the incoming clock and data bits. 5-9 Step 26 provides a final adjustment to the variable input resistor of B410 to establish the optimum phase lock condition between the incoming serial stream of data and clock bits and the B 140 internal oscillator. Step 27 adjusts the delay used to set the data bits and clock bits correctly to their respective gating waveforms. 5.3.4 General Troubleshooting Guides The following paragraphs contain suggested methods of correcting recurring problems. Also, refer to DEC Field Service Manuals and DEC Tech Tips published periodically. 5.3.4.1 Disk Pack Compatibility - To determine if two disk packs are compatible, run CTEST and swap packs as directed. If any errors occur, the drives are considered to be incompatible. NOTE Before running compatibility tests, the drive should have passed all diagnostics with a pack formatted on that drive. If the drives are found to be incompatible, they should be aligned as described in the Vendor Maintenance Manual. CAUTION C.E. (Customer Engineering) Packs are not indestructable. Their specially recorded track can be destroyed rendering the pack unusable. Extreme care should be exercised in their use. C.E. Packs should only be used when aligning heads or checking head alignment. They should never be used for any other troubleshooting or alignment procedures. 5.3.4.2 Proper Use of C.E. Packs - The following procedures should protect and may extend indefinitely the usable life of C.E. Packs. For both RPO I and RP02: Procedure Step Do not connect the tester until all power has been removed from the drive. CAUTION Before cables are removed, all power must fast be removed from ail drives (via SI) as well as from the RPlO. Failure to do so can result in damage to the steering diodes in the power sequencing network. 2 Set the drive to READ ONLY condition. CAUTION Always disable write amp by switching to READ ONLY before using C.E. Packs to insure safety of specially recorded elliptical tracks. 3 Apply power to drive the S I, then apply power to tester. 4 Press UNIT DESELECT on tester. NOTE This step is necessary to prevent accidental writing over the test track, which would effectively destroy its usefulness. 5-10 For RPOI only: Step Procedure Remove HEAD SELECT (switch 4 on tester). 2 Remove all head plugs. 3 Insert head alignment plug into desired head socket. 4 Mount the C.E. Pack on the drive. CAUTION Whenever a different head is to be tested, or a head plug removed or inserted, always remove HEAD SELECf level (switch 4 on the tester). It is also recommended to position off cylinder 73 when repositioning the Head Alignment Plug. For RP02 only: Step Procedure Note that the Head Alignment Plug is not used with the RP02. 2 It is not necessary to remove a head plug while the C.E. Pack is on the drive. Head and Pack Thermal Equilibrium: Procedure Step Before heads are adjusted, thermal equilibrium procedures should be followed. The temperature stabilization cycle, which assures standard operating temperature during head alignment, consists of fIrst running the drive with C.E. Pack installed and all covers on for one hour and 15 minutes, then running the drive with C.E. Pack installed and the two top covers off for an additional 20 minutes before attempting alignment. 2 Use only the special tools for maintenance (Le., beryllium screwdriver, torque wrench, etc). NOTE All RPO 1 and RP02 Vendor Manuals are serialized and contain specifIc information pertaining to that drive (i.e., ECO's, updated prints, etc). Each manual must be maintained as Engineering Documentation. When a C.E. pack is used on a Memorex drive, the READY signal will not occur. Therefore, jump B05 test point three to ground. This indicates to the drive logic than an index pack is being used, instead of a sectored pack. 5.3.4.3 Search Errors - Search Errors can be caused by a variety of conditions. A known formatted pack should be run. If search errors occur on only specifIc surfaces of a drive, the read logic should be checked. If search errors occur from all drives, the RDS operation should be checked. To do this, sync off 109M (DTC SEARCH) going high and view L21 N (DTC READ BIT). This bit should be on a 1 for approximately 100 IlS for RP02s and for 250 IlS for RPO 1s. If DTC READ BIT is not on a 0 after 100 IlS (250 IlS for RPO I), or if it never transitions to a I, the separator is at fault. However, if READ BIT performs correctly the Header Compare, LPR, Header Read Control, or Shift Register is at fault. 5-11 5.3.4.4 Parity Errors - If parity errors occur from one drive, the read or write logic in that drive should be checked. If all parity errors occur from word 0, the RDS Sync Field Enable is probably not being produced. If errors do not exhibit a repetitive pattern, the RDS is at fault. If an AR bit is faulty, this is particularly easy to see and scope in local mode. Remember that the controller tries to read headers three times before terminating; therefore, the separator's operation can be quite marginal before search errors occur. 5.3.4.5 Failure to Restore - If the Memorex drive fails to restore, the logic can be checked by moving the actuator by hand. Proceed as follows: Step Procedure Connect the off-line tester. 2 Remove power from bobbin. 3 Install a jumper to prevent T2 from becoming true (Seek Incomplete). 4 Wiggle head assembly at full forward stop. This gives a forward velocity signal that is needed to complete the restore sequence. The code 202 should now be seen in the cylinder address lights (force count). 5 Move the coil backwards by hand. Observe that the address register counts down. 6 When address reaches 0, the detent should pick. NOTE The address might not reach 0 because the pull may not be smooth causing a tooth to be counted more than once. 5.3.4.6 Disk Pack Reliability Test Map Limitations - The MAP routine in MAINDEC 10-D5OB cannot guarantee detection of all weak or bad spots on the disk pack surface. The best procedure for developing an initial list of questionable or faulty disk pack sectors is to note all failures relating to data errors during acceptance and to enter the MAP data manually using the manual entry feature of D50B's MAP routine. The MAP routine will write the map data onto the appropriate sectors of the pack for Monitor reference. 5.3.4.7 Oeaning - For trouble-free operation take the same environmental care as is indicated for tapes (refer to Paragraph 6.10 in the PDP-l 0 System Reference Manual). In particular, the heads and the packs should be kept clean. Materials and equipment needed for cleaning are as follows. a. Lint-free wipers (cloth or paper), such as Kimwipes Type 900-S, Stock No. 3415 (about 8 x 5 in.) b. Isopropyl alcohol, at least 90%, such as Merck or NF (99% by weight) or Lilly (91% by volume) NOTE Store alcohol in its original container or in a glass jar. c. Q-tips and pipe cleaners d. Wooden tongue depressors, 6 x % in. NOTE Do not use plastic depressors (the alcohol softens them). e. A high-intensity light or other strong light source t; A piece of white cardboard or stiff paper (8Y2 x 11 in.). 5-12 Inspect the heads for dirt accumulation at least twice monthly (weekly for around-the-clock operation). When necessary, clean them carefuIly with a Q-tip soaked in alcohol, and clean out the two holes in each head with a pipe cleaner, also soaked in alcohol. Keep all cabinet and pack filters clean and fresh. Dirty heads can be caused by poor head flight due to poor air flow through the pack or cabinet. Always replace a single head that collects dirt while others in the same drive remain clean. Do not clean all of the packs at an installation just for the sake of cleaning them. If a pack is subject to random errors, or if vital information that is not duplicated elsewhere cannot be retrieved, and the problem is not alleviated by cleaning the heads, then clean the pack. In any event, depending on environmental conditions, test all packs every few months by cleaning a couple of surfaces at random in each; clean all surfaces in any pack in which dirt is discovered. To clean a pack, mount it on a drive from which the upper case panels have been removed or on a free-standing spindle mechanism that allows the pack to be turned by hand with the cover removed. Place the light with the white cardboard as a background so that plenty of light shines into the pack. Follow this procedure for cleaning each surface. Step Procedure Position the light so the surface is clearly visible. 2 Wrap a fresh wiper around a depressor with wiper extending 3/8 in. beyond the wood at one end. 3 Soak one side of the wrapped depressor with the alcohol (be sure to wet the full width of the depressor). 4 Spin the pack by hand at 40-60 rpm (use the flat top surface of the plastic bezel on the top of the pack). 5 With the pack spinning, insert the prepared depressor with the protected end toward the center, and press the wet side against the surface. Maintain the pack spin while applying about 5- 10 pounds pressure against the surface; wet the surface across the full width of the tracks. The pressure may be lightened as the surface dries, but be sure to keep the wiper on the surface with the pack spinning until the surface is completely dry and has a high gloss. Keep the pack spinning while removing the depressor, and check the wiper for dirt. 6 Inspect the surface carefuIly for scratches. If a scratch corresponds in position to a bad sector as determined by the program, then further cleaning is unlikely to make the sector usable. WARNING Do not attempt to use the drive motor when cleaning a pack. Always turn drive power off and spin the pack manually. Do not clean a pack if either the pack or the alcohol is below 40°F (otherwise water vapor might condense on the surface). 5-13 Chapter 6 Drawings 6.1 GENERAL The RPIO engineering drawings and an accompanying signal glossary are included in Volume 2 of this maintenance manual. A list of engineering drawings is provided in Table 6-1. Table 6-1 RPI0 Engineering Drawings Number Title A-ML-RPlO-A RPIO Master Drawing List D-DI-RPIO-O-l RPIO Drawing Index List D-UA-RPIO-O-O RPIO Unit Assembly A-PL-RP 10-0-0 A-PL-RPIO-O-MC RPIO Parts List Parts List Disk File Interface A-PL-7006194-0-0 Wired Assembly RPIO A-PL-7006195-0-0 Cable Set RPIO Flow Chart Asynchronous and Sector Counters D-FD-RPIO-O-FCA D-FD-RPIO-O-FCCC D-FD-RPIO-O-FCCI D-FD-RPIO-O-FCDC D-FD-RPIO-O-FCE D-FD-RPIO-O-FCL D-FD-RPIO-O-FCMI D-FD-RPlO-0-FCM2 D-FD-RPIO-O-FCRI D-FD-RPIO-O-FCRW D-FD-RPiO-O-FCS D-FD-RPIO-O-FCSC D-FD-RPIO-O-FCWH Flow Chart Channel Control Flow Chart Channel Interface Flow Chart Disk Control Flow Chart End Flow Chart Local Data Transfer Control Micro I Data Transfer Control Micro 2 Flow Chart Register Interconnections Flow Chart Read/Write Flow Chart Start Flow Chart Search Flow Chart WR Headers and Data D-BS-RPIO-O-ARD Assembly Register Assembly Register Data Gate D-BS-RP 1O-O-CC Channel Control D-BS-RPIO-O-CXR Condition Register D-BS-RPIO-O-DAR Da ta Address Register D-BS-RPIO-O-DSBC Disk Signal Bus Connectors D-BS-RPI O-O-DTC Data Transfer Control D-BS-RP I O-O-AR 6-1 Table 6-1 (Cont) RPI0 Engineering Drawings Number Title D-BS-RPIO-O-HCDE Header Compare and Designation Error D-BS-RPIO-O-IBC I/O Bus Control Interconnecting Cables D-IC-RPIO-O-IC D-IC-RPIO-O-INDC D-BS-RPIO-O-IOB D-BS-RPIO-O-IOBD Indicators lOB Transmitter D-BS-RPIO-O-LPR lOB Data Receiver Longitudinal Parity Register D-BS-RPIO-O-MPX Multiplexer D-BS-RPIO-O-RDS Read Data Separator D-BS-RPIO-O-RDS Read Data Separator Calibrations D-BS-RPIO-O-SC Sector Counter D-BS-RPIO-O-SCB Sector Counter Buffer D-BS-RPIO-O-SCCC Sector Counter Control Pulses D-BS-RPIO-O-SCM Sector Counter Multiplexer D-BS-RPIO-O-SR Shift Register D-IC-RPIO-O-SWP Switch Panel D-CL-RPIO-O-TERM Pulse and Level Terminations D-BS-RPIO-O-WDC Word Counters D-MU-RPIO-O-AD Module Utilization A-D D-MU-RPIO-O-EJ Module Utilization E-J D-MU-RPIO-O-KN Module Utilization K-N D-MU-RPIO-O-PT Module Utilization P-T D-IC-RPIO-O-3 C-AD-7006 I 95-0-0 Wiring Power DC and AC Wired Assembly (RPIO) Cable Set (RPIO) D-SP-RPIO-O-CEPT CE Pack Tracks D-AD-7006194-0-0 6-2 READER'S COMMENTS RPIO DISK PACK SYNCHRONIZER MAINTENANCE MANUAL DEC-IO-HSEC-D (1) Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications. What is your general reaction to this manual? In your judgement is it complete. accurate. well organized. well written. etc~ Is it easy to usery _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ What features are most useful? What faults do you find with the manual? Does this manual satisfy the need you think it was intended to satisfy? Does it satisfy your needs? Why? _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Would you please indicate any factual errors you have found. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Please describe your position. Name _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Organization _ _ _ _ _ _ _ _ _ _ _ _ _ __ Street _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Department _ _ _ _ _ _ _ _ _ _ _ _ _ __ City _ _ _ _ _ _ _ _ _ _ _ _ State _ _ _ _ _ _ _ _ _ _ _ _ __ Zip or Country _ _ __ - - - - - - - -- - - - - - - - - - - - - - - - - - - Fold Here - - - - - - - - - - - - - - - - - - - - - - Do Not Tear - Fold Here and Staple - - - - - - - - - - - - - FIRST CLASS PERMIT NO 33 MAYNARD. MASS. BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STAHS Postage will be paid by: mamaama Digital Equipment Corporation Technical Documentation Department 146 Main Street (A & M Building) Maynard, Massachusetts 01754 - Digital Equipment Corporation Maynard, Massachusetts printed in U.S.A.
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