DEC 11 H05AA B D PDP 05, 10 Computer Manual

DEC-11-H05AA-B-D PDP-11-05, 11-10 Computer Manual DEC-11-H05AA-B-D PDP-11-05, 11-10 Computer Manual

User Manual: DEC-11-H05AA-B-D PDP-11-05, 11-10 Computer Manual

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PDP-11 105,11/10
computer manual

DEC-J J-HOSAA-8-D

PDP-11 105,11/10
computer manual

digital equipment corporation • maynard. massachusetts

1st Edition, February 1973
2nd Printing, September 1973
3rd Printing, July 1974
4th Printing, September 1974

The material in this manual is for informational
purposes and is subject to change without notice.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS

PDP
FOCAL
COMPUTER LAB

CONTENTS
Page

PART 1 - COMPUTER DESCRIPTION
CHAPTER 1

COMPUTER COMPONENTS

1.1
1.2
1.2.1
1.2.2
1.2.2.1
1.2.2.2
1.2.3
1.2.4
1.3
1.4

Introduction
Computer Components
KDll-B Processor
Core Memory
Memory Organization
Memory Specification
Power Supply
.... .
Backplane . . . . . . .
MEI1-L Core Memory System
Extension Mounting Box

CHAPTER 2

UNIBUS

2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.4.1
2.4.2
2.4.3

Introduction
Unibus Structure . . . .
Bidirectional Lines
Master/Slave Relationship
Interlocked Communication
Peripheral Device Organization and Control
Unibus Control Arbitration
Priority Transfer Requests
Processor Interrupts
Data Transfers . . . . . .

CHAPTER 3

UNPACKING AND INSTALLATION

3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.5

Introduction . . . . .
Unpacking
.... .
Mechanical Description
Installation . . . . . .
Mounting Computer on Installed Slides
Securing Computer to Cabinet Rack
Installation of I/O Cables
Interchangeable Peripheral Slots
Side and Top Cover Installation
AC Power Supply Connection
Connecting to Voltages Other than 115V
Quality of AC Power.source
Cabinet Power Control . . . . . .
Installation Certification . . . . .
Warranty Service (Domestic Only)

3.6
3.7
3.7.1
3.7.2
3.8
3.9
3.10

1-1
1-1
1-1
1-1
1-2
1-2
1-2
1-2
1-5
1-5

iii

2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-2
2-3
2-3

3-1
3-1
3-1

3-6
3-6
3-6
3-6
3-7
3-7
3-7
3-7
3-7
3-7
3-8
3-9

CONTENTS (Cont)
Page
CHAPTER 4

COMPUTER OPERATION

4.1

Introduction . . . . . .
Power Switch Operation
Function Switches "
Address/Data Switches
Console Indicators ..
Console Operation ..
Load Address Switch
Examine Switch
Deposit Switch . . .
ENABLE/HALT Switch
ST ART Switch .. . . .
Continue Switch . . . .
Unconditional Computer and Unibus Initialization
Loading Programs from Paper Tape . . . . .
The Bootstrap Loader . . . . . . . . .
Loading the Loader Into Memory
Loading Bootstrap Tapes . .
Bootstrap Loader Operation .. .
The Absolute Loader . . . . . . . . . .
Loading the Loader Into Memory
Loading Absolute Tapes
Memory Dumps . . . . .
Operating Procedures
Output Formats
Storage Maps . . . .

4.2
4.3

4.4
4.5

4.6
4.6.1

4.6.2
4.6.3

4.6.4
4.6.5
4.6.6
4.7
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.1.3
4.8.2
4.8.2.1
4.8.2.2
4.8.3
4.8.3.1
4.8.3.2
4.8.3.3

4-1
4-1

4-2
4-2
4-2
4-2

4-2
4-2
4-4

4-4

4-4
4-5
4-5
4-5

4-6
4-7
4-8
4-9
4-10
.4-10
. 4-10

4-12
4-12
4-13
4-13

PART 2 - KDll-B PROCESSOR
CHAPTERS

PROCESSOR GENERAL DESCRIPTION

5.1
5.2
5.3
5.5
5.5.1
5.5.2
5.5.3

Introduction . . . . . .
KD 11-B Definition . . . . . . . . .
KD 11-B and the Unibus
KDII-B as an Instruction Interpreter
KDll-B Print Set
......... .
Medium and Large Scale Integrated Circuit Representations
Microprogram Documentation .
Read-Only Memory (ROM) Maps
............ .

CHAPTER 6

INSTRUCTION SET

6.1
6.2
6.2.1
6.2.2
6.3

Introduction . . .
Addressing Modes. .
Introduction .
Instruction Timing
PDP-ll/05 Instructions
Instruction Set Differences

5.4

6.4

5-1
5-1
5-1
5-2
5-3
5-5

5-5
5-5

6-1

6-1
6-1
6-2

6-2
6-2

CONTENTS (Cont)
Page
CHAPTER 7

CONSOLE DESCRIPTION

7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.5.1
7.3.5.2
7.3.5.3

Introduction . . . . . . .
General Description
ADDRESS/DATA Register Logic
Control Switch Logic
Detailed Description
Multiplexer
Clock . . . . .
Counter
Display Buffer and Driver
Control Switches and Logic
Normal Operating Mode
Panel Lock Mode . . . .
Power Loss During Operation

CHAPTER 8

KDll-B DETAILED DESCRIPTION

8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.6.1
8.3.6.2
8.3.6.3
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.5
8.6
8.6.1
8.6.2
8.6.2.1
8.6.2.2

Introduction . . . . . . . . . . . .
ROMs as Generalized Gates
KD11-B Data Path, Simplified Description
Data Path (DP) Detailed Description
DP Data Polarities
Data Path Control (DPC) ..
A-Multiplexer
...... .
Arithmetic Logic Unit (ALU)
B Register . . . . . . . . .
Functional Description
BLEG Operations That Provide Input to the ALU
BREG Shifting Operations
Byte Instructions . . . . . . . . . . . . .
Scratch Pad Memory . . . . . . . . . . .
Scratch Pad Memory Address Multiplexer
Processor Status Word Register
Constants Generator ..
Console Switch Register
Console Multiplexer
Instruction Decoding . . . . .
Introduction . . . . . .
Double Operand Instructions
Branch on Unary .. . . . .
PDP-II Branch Instruction .
Operate Instructions .
Auxiliary ALU Control
Processor Clock
Unibus Control . . . .
DATI Timing ..
DATI Operation
DA TIP Operation
DATIP Logic . .

7-1
7-1
7-1
7-1
7-2
7-2
7-3
7-4
7-6
7-7
7-8
7-9
7-9

·
·
·
·
·
·

8-1
8-1
8-3
8-3
8-3
8-4
84
8-7
8-10
8-10
8-13
8-14
8-16
8-16
8-19
8-20
8-26
8-26
8-27
8-28
8-28
8-28
8-30
8-30
8-30
8-30
8-31
8-33
8-33
8-34
8-35
8-36

CONTENTS (Cont)
Page

8.6.3
8.6.4
8.6.5
8.7
8.8
8.9
8.10
8.11
8.11.1
8.11.2
8.11.3
8.12

DATa
Byte Operations
Bus Errors
Internal Unibus Addresses
Bus Requests . . . . . . .
Non-Processor Requests (NPR)
Serial Communications Line Description (SCL)
Line Clock . . . .
Introduction ..
Flag Control
Interrupt Control
Power Fail . . . . . .

CHAPTER 9

MICROPROGRAM CONTROL

9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.6
9.7
9.8

Introduction . . . . . . . . .
Microprogrammed Versus Conventional Control
Control Store
........ .
Branching Within Microroutines
Microprogram Flow
Flow Chart Notation
Interrupts and Traps
Console Functions .
Microprogram Symbolic Listing
Microprogram Binary Listing . . .
Microprogram Cross Reference Listing

CHAPTER 10

KDll-B AND CONSOLE MAINTENANCE

10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11

Introduction ..
Diagnostics . . . . .
Types of Failures . .
Suggested Equipment
Procedures . . . . .
Adjustments
KDlI-B Print Function Table
External Clock Inputs
KMll Maintenance Panel
Using KMll Maintenance Panel
Console Maintenance . . . . . .

8-36
8-36
8-37
8-37
8-39
8-41
8-41
8-43
8-43
8-43
8-44
8-45

·
·
·
·
·

9-1
9-1
9-1
9-7
9-10
9-11
9-17
9-18
9-20
9-20
9-24

10-1
10-1
10-1
10-1
10-2
10-3
10-4
10-6
10-6
10-9
10-10

PART 3 - MMll-K AND MMll-L MEMORIES
CHAPTER II

MMII-K AND L GENERAL DESCRIPTION

11.1
11.2
11.2.1
11.2.2
11.2.3

Introduction . . . . . . .
General Description
Physical Description
Specifications
Functional Description

11-1
11-1
11-1
11-1
11-4

CONTENTS (Cont)
Page
11.2.3 .1
11.2.3.2
11.2.3.3
11.2.4
11.2.4.1
11.2.4.2
11.2.4.3
11.2.4.4

GI10 Control Module
G231 Driver Module .
H213 or H214 Stack Module
Basic Memory Operations
Data In (DATI) Cycle
Data In, Pause (DATIP) Cycle
Data Out (DATO) Cycle . . .
Data Out, Byte (DATOB) Cycle

CHAPTER 12

MMll-K AND L DETAILED DESCRIPTION

12.1
12.2
12.3
12.4
12.4.1
12.4.2
12.4.3
12.4.3.1
12.4.3.2
12.4.3.3
12.4.3.4
12.5
12.5.1
12.5.2
12.5.3
12.5.4
12.5.5
12.6
12.7
12.8
12.9
12.9.1
12.9.2
12.9.3
12.9.4
12.9.5
12.9.6
12.9.7
12.9.8

Introduction .. .
Core Array . . . . . . . .
Memory Operation . . . .
Device and Word Selection
Memory Organization and Addressing Conventions
Device Selector . . . . . . . . . . . . . . . .
Word Selection . . . . . . . . . . . . . . . .
Word Address Register and Gating Logic
X- and Y-Line Decoding . . . . . . . .
Drivers and Switches . . . . . . . . . .
Word Address Decoding and Selection Sequence
Read/Write Current Generation and Sensing
Read/Write Operations . . .
X- and Y-Current Generators
Inhibit Driver
Sense Amplifier
Memory Data Register
Stack Discharge Circuit
DC LO Circuit . . . . . . .
Operating Mode Selection Logic
Control Logic . . . . . . . . .
Timing Circuit . . . . . .
Slave Synchronization (SSYN) Circuit
Pause/Write Restart Circuit
Strobe Generating Circuit
Data In (DATI) Operation
Data In Pause (DATIP) Operation
Data Out (DA TO) Operation . . .
Data Out Byte (DATOB) Operation

CHAPTER 13

MEMORY MAINTENANCE

13.1
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.2

Introduction . . . . .
Preventive Maintenance
Initial Procedures
Checking Output of Current Generators
Corrective Maintenance . . . . . . . . .
Strobe Delay Check and Adjustment
Corrective Maintenance Aids . . . .

vii

11-4
11-6
11-6
11-7
11-7
11-7
11-7
11-7

12-1
12·1
12-1
12·4
12-6
12-8
12·11
12·12
12·13
12·15
12·17
12·19
12·19
12-21
12·22
12·23
12·24
12-24
12·26
12·26
12·27
12·28
12·33
12·34
12-37
12-39
12·41
12·41
12-41

13·1
13-1
13·1
13·2
13-2
13·2
13-2

CONTENTS (Cont)
Page
13.4
13.4.1
13.4.2
13.4.3
13.4.4
13.4.S

Programming Tests .. . . . . . . . . . . . . .
Address Test Up (MAINDEC-ll-DIAA)
Address Test Down (MAINDEC-l1-DIBA)
No Dual Address Test (MAINDEC-ll-DICA)
Basic Memory Patterns Test (MAINDEC-ll-DIDA)
Worst-Case Noise Test (MAINDEC-ll-DIGA)

13-9
13-9
13-9
13-9
l3-9
13-10

PART 4 - POWER SUPPLY
CHAPTER 14

POWER SUPPLY GENERAL DESCRIPTION

14.1
14.2
14.2.l
14.2.2
14.2.3
14.2.4
14.2.S
14.3

Introduction . . . . . .
Physical Description
Power Control Unit
Power Chassis Assembly
DC Regulator Module
DC Cable
AC Cable ..
Specifications

CHAPTER 15

POWER SUPPLY DETAILED DESCRIPTION

IS .1
IS.2
IS.3
IS.3.1
IS.3.2
IS.3.3
IS.3.4
IS.3.S
15.3.6

Introduction . . . . . . . . . .
AC Input Circuit . . . . . . . .
DC Regulator Module Operation
Generation of ±Raw DC
LTC L Circuit . . . . . .
BUS AC LO L and BUS DC LO L Circuits
+ ISV Regulator Circuit
+SV Regulator Circuit
-15V Regulator Circuit

CHAPTER 16

POWER SUPPLY MAINTENANCE

16.1
16.2
16.3
16.4
16.4.l
16.4.2
16.4.3
16.S

Introduction . . .
Adjustments
Circuit Waveforms
Troubleshooting
Troubleshooting Rules
Troubleshooting Hints
Troubleshooting Chart
Parts Identification . . . . .

APPENDIX A

INTEGRATED CIRCUIT DESCRIPTIONS

A.1
A.2
A.3
A.4

Introduction . . . . . . . . . . . . .
8266 2-Input, 4-Bit Digital Multiplexer
7413 Dual NAND Schmitt Triggers
7473 Dual J-K Master-Slave Flip-Flops
7474 Dual D-Type Edge-Triggered Flip-Flops
747S 4-Bit Bistable Latch . . . . . . . . . .

A.5

A.6

14-1
14-1
14-1
14-2
14-3
14-S
14-S
14-6

IS-1
IS-1
IS-1
IS-S
IS-6
IS-6
IS-7
IS-7
IS-9

16-1
16-1
16-1
16-4
16-4
16-4
16-4
16-6

viii

A-I
A-3
A-4
A-S
A-6
A-7

CONTENTS (Cont)
Page
A.7
A.8
A.9
A.lO
A.ll
A.l2
A.l3
A.l4
A.l5
A.16
A.17
A.l8
A.l9

7489 64·Bit Read/Write Memory
74121 Monostable Multivibrator
74150 Data Selector Multiplexer
74153 DuaI4-Line-to-l-Line Data Selectors/Multiplexers
74154 4-Line-to-16-Line Decoders/Demultiplexers
74157/74S158 Quadruple 2-Line-to-l-Line Multiplexer .
74174 Hex/74175 Quad D-Type Flip-Flops with Clear
74181 Arithmetic Logic Unit/Function Generator (ALU)
74182 Look-Ahead Carry Generator . . . . . . . . . . .
74193 Synchronous 4-Bit Up/Down Counter (Dual Clock with Clear)
74194 4-Bit Bidirectional Universal Shift Registers
.....
7528 Dual Sense Amplifiers with Preamplifier Test Points ..
9602 Dual Retriggerable Monostable Multivibrator with Clear

. A-8
. A-9
A-lO
A-12
A-13

A-14
A-15
A-16
A-19
A-21
A-23
A-24
A-25

COMPUTER CONNECTORS
APPENDIX B
SUPPLEMENT I PDP-II/OS, 11/10 10-1/2 INCH MOUNTING BOX AND POWER SYSTEM
SUPPLEMENT 2 DESCRIPTION OF DATA PATHS MODULE M7260 REVISION M
SUPPLEMENT 3 DESCRIPTION OF CONTROL LOGIC AND MICROPROGRAM MODULE M7261 REVISION R
ILLUSTRATIONS
Figure No.
1-1
1-2
1-3
1-4
3-1
3-2
3-3

34
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3

54
5-5
5-6
5-7
6-1
6-2
7-1
7-2
7-3

Title
Module Utilization Diagram for Configuration 1 (16K)
Module Utilization Diagram For Configuration 2 (8K)
Computer Backplane Connector and Pin Designations
Module Contact Designations
Computer Packaging . . . . . . . . . . .
Computer Mounting Box . . . . . . . . .
Computer Box With Top Cover Removed
Computer Box with Top and Side Covers Removed
Computer Chassis (showing peripheral cables and the Unibus)
Mounting Box Without Modules . . . . . . . . . . . .
Rear of Computer With Cable Strain Reliefs . . . . . .
Typical Cabinet Power Control System Wiring Diagram
Console Illustrating Switch Movements
Loading and Verifying the Bootstrap Loader
Loading Bootstrap Tapes Into Memory
Absolute Format . . . . . . . . . . . . . .
Bootstrap Format . . . . . . . . . . . . .
KDII-B With Interconnections to Memory and Peripherals
KDII-B Processor Block Diagram . . . . . . . . . .
Instruction Interpreter Block Diagram . . . . . . . .
Typical Small Scale Integrated Circuit Representations
DPF LOAD IR L Signal . . . . . . . . . . .
ALU, MSI Circuit Type 74181 Representation
..... .
E068 ROM Map Example
Addressing Mode Instruction Formats
PDP-II Instruction Formats . . . . .
Console Functional Block Diagram
Console Clock, Schematic and Timing Diagram
Coun ter, Simplified Logic Diagram
ix

Page
1-3
1-3
1-4
1-5
3-2
3-3
3-3
3-4
3-4
3-5
3-5
3-8
4-1
4-8
4-9
4-13
4-14
5-2
5-2
5-3
5-4
5-4

5-5
5-6
6-2
6-18
7-2
7-4
7-5

ILLUSTRATIONS (Cont)
Figure No.

74
7-5
7-6
8-1
8-2
8-3

84
8-5
8-6
8-7

8-8
8-9
8-10
8-11

8-12
8-13
8-14
8-15
8-16
8-17
8-18
8-19
9-1
9-2
9-3
9-4
9-5
9-6
9-7
10-1
11-1
11-2
11-3
11-4

12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14

Title
Display Buffer and Driver, Simplified Logic Diagram
LED Driver Circuit . . . . . . . . . . . . . . . . .
Control Switches and Bounce Buffers, Logic Diagram
1024-Bit and 256-Bit ROMs . . . . . . . .
32 X 8 ROM used as Generalized Gate .. .
KDlI-B Simplified Data Path Block Diagram
KDI1-B Detailed Block Diagram .
74181 Pin and Signal Designations ..
74182 Pin and Signal Designations ..
Arithmetic Logic Unit Block Diagram
B Register and Output Logic . . . . .
B Register Shift Signal Inputs . . . . .
Byte Format for Shifting Instructions
Block Diagram and Function Table for Scratch Pad Memory
Logic For Determing C and V Bits .
Console Multiplexer Block Diagram
Processor Clock Timing Diagram
DATI and DATa Timing .
Unibus Address Decoding
Bus Request (BR) Timing
Double-Buffering Data Flow
BUS AC La and BUS DC La Timing Diagram
Control Store Word Bit and Field Format
KDlI-B Simplified Flow Diagram . . . . . .
Excerpt from Microprogram Flow (K-NL-KDII-B-l)
CMP #15, CHAR (022767), Simplified Flow Diagram
Excerpt of (K-WL-KDII-B-2) Microprogram Symbolic Listing
Excerpt of Microprogram Binary Listing (K-W-KDII-B-3)
Generation of SPM Enabling Signals . . . . . .
KMll Maintenance Module, KDII-B Overlays .
Component Side of Gil 0 Control Module .'..
Component Side of G231 Driver Module
Component Side of 8K H214 Stack Module
MMII-K, L Memory Block Diagram
Three-Wire Memory Configuration . . . . .
Hysteresis Loop for Core . . . . . . . . . .
Three-Wire 3D Memory, Four Mats Shown for a 16-Word 4-Bit Memory
Device and Word Address Selection Logic, Block Diagram
Memory Organization for 8K Words . . . . . . . . . . .
Address Assignments For Three Banks of 8K Words Each
Jumper Configuration For A Specific Memory Address
Device Decoding Guide
.............. .
Type 8251 Decoder, Pin Designation and Truth Table
Decoding of Read/Write Switches and Drivers Y4-Y7
Switch or Driver Base Drive Circuit . . . . . .
V-Line Selection Stack Diode Matrix
....... .
Typical V-Line Read/Write Switches and Drivers
Interconnection of Unibus, Data Register, Sense Amplifier,
and Inhibit Driver . . . . . . . . . . . . . . . . . . . . .

Page
7-7
7-7
7-8
8-1
8-2
8-3
8-5
8-8

8-8
8-9
· 8-12

8-15
8-17
8-18

8-25
8-27
8-32
· 8-34
· 8-38
8-39
8-42

845
9-2
9-10
· 9-11

·
·
·
·

9-13
9-21
9-22
9-24
10-7
11-2
11-2
11-3
11-5
12-2

12-3
12-5
12-6
12-7
12-8
12-10
12-10
12-13
12-14
12-15
12-16
12-17
12-20

ILLUSTRATIONS (Cont)
Figure No.
12-15
12-16
12-17
12-18
12-19
12-20
12-21
12-22
12-23
12-24
12-25
12-26
13-1

13-2
13-3
13-4
14-1
14-2
14-3
144
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
16-1
16-2

Title
Y-Current Generator and Reference Voltage Supply . . . . . .
Sense Amplifier and Inhibit Driver . . . . . . . . . . . . . . .
Type 7528 Dual Sense Amplifiers With Preamplifier Test Points
........ .
Stack Discharge Circuit
DC LO Circuit, Schematic Diagram
Basic Timing and Control Signal Functions
TWID Hand TNAR H Control Logic
Generation of MSEL RESET L
Slave Sync (SSYN) Circuit . . . . .
Pause/Write Restart Circuit
Strobe Generating Circuit and Timing Diagram for STROBE H
Flow Chart For Memory Operation
Strobe Pulse Waveform . . . . . .
Troubleshooting Chart . . . . . .
MM11-K Sense/Inhibit Waveforms
Drive Waveforms . . . . . . . . .
Power Chassis Assembly (with DC Regulator Module)
Power Supply Assembly (with DC Regulator Module Removed)
DC Regulator Module (Top View) . . . . . . . . . . .
DC Regulator Module (Bottom View In Mounting Box)
Detailed AC Interconnection Diagram . . . . . . .
115V Connections - Simplified Schematic Diagram
230V Connection Diagram .. .
Regulator Module Block Diagram
Rectifier and LTC L Circuits ..
BUS AC LO and BUS DC LO Circuits
+ 15V Regulator Circuit
+5V Regulator Circuit . . . . . .
-15V Regulator Circuit
.... .
+5V Regulator Circuit Waveforms
-15V Regulator Circuit Waveforms

Page
12-21
12-23
12-24
12-25
12-26
12-29
12-31
12-32
12-35
12-37
12-38
12-40
13-2
13-3
13-5

13-7
14-2
14-3
144
14-4
15-2
15-3
15-3
154
15-5
15-6
15-7
15-8
15-9
16-2
16-3

TABLES
Table No.
4-1
4-2
4-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
7-1
7-2

Title
Significance of ADDRESS/DAT A Indicators
Bootstrap Loader Instructions
Memory Bank Assignments
Addressing Modes . . . . .
Addressing Times
.... .
Single Operand Instructions
Double Operand Instructions
Program Control Instructions
Operate Group Instructions
Condition Code Operators .
PDP-II Differences
Scan Address Signal Generation
Counter States . . . . . . . . .

Page
4-3
4-6
4-6
6-3
64
6-5
6-9
6-12
6-17
6-18
6-19

7-3
7-6

TABLES (Cont)
Table No.
8-1

8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
9-1
9-2
9-3
10-1
10-2
10-3
10-4
11-1
12-1
12-2
12-3
12-4
12-5
14-1
14-2
14-3
16-1
A-I
B-1

Title
ALU Control Signals . . . . . . .
Control Store Signals for BLEG Operations
Register Utilization in SPM
SPM Address Line Signals . . . . . .
SPAM Input Data Sources . . . . . .
Processor Status Word Bit Assignments
Effect of E066 Outputs DPG CMP+BIT L, DPG MOVE L, and DPG BYTE L
Auxiliary Control for Binary and Unary Instructions
Unibus Addresses
.... .
Trap Priorities . . . . . . . .
KDII-B Control Store Fields
Microprogram Branches (BUT)
Flow Notation Glossary
Test Equipment and Tools ..
Baud Rate Adjustment . . . .
Engineering Drawing Print List and Functions
KM-l and KM-2 Overlay Designations
MMII-K and L Memory SpeCifications
Addressing Functions . . . . . . . .
Enabling Signals for Word Register Gating
Word Address Decoding Signals
Selection of Bus Transactions . . . . .
Generation of Memory Operating Signals
Power Supply Input SpeCifications . . .
Power Supply Output Specifications . .
Mechanical and Environmental SpeCifications
Troubleshooting Chart
Integrated Circuits
Connectors . . . . . .

xii

Page
8-10
8-13
8-17
8-19
8-19
8-20
8-29
8-31
8-38
8-40
9-2
9-7
9-12
10-2
10-4
10-4
10-8
11-3
12-4
12-12
12-18
12-27
12-28
. 14-6
. 14-7
14-10
16-5
A-I
B-1

FOREWORD

This manual describes the PDP-ll/OS and PDP-ll/lO Computers. The PDP-ll/OS and PDP-ll/lO are electrically
identical. The PDP-II/OS is specified for the Original Equipment Manufacturer (OEM) market and the PDP-I 1/10 is
specified for the end user market.
The PDP-II/OS is available in two versions: one provides a maximum of 8K words of core memory and the other
provides a maximum of 16K words of core memory. The PDP-I 1/10 is available only with a maximum of 8K words
of core memory.
This manual is divided into four parts.
Part 1
Part 2
Part 3
Part 4

Computer Description
KDII-B Processor
MMII-K, MMII-L Memories
Power Supply

Chapter outlines of each part are shown below.
Part 1

COMPUTER DESCRIPTION
Chapter 1
Chapter 2
Chapter 3
Chapter 4

Part 2

KDll-B PROCESSOR
Chapter S
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10

Part 3

Computer Components
Unibus
Unpacking and Installation
Operation

Processor General Description
Instruction Set
Console Description
KDII-B Detailed Description
Microprogram Control
KDII-B and Console Maintenance

MMII-K and MMII-LMEMORIES
Chapter 11
Chapter 12
Chapter 13

MMII-K and L General Description
MM11-K and L Detailed DeSCription
Memory Maintenance

xiii

Part 4

POWER SUPPLY
Chapter 14
Chapter 15
Chapter 16

Power Supply General Description
Power Supply Detailed Description
Power Supply Maintenance

A bound volume of engineering drawings is supplied with each computer.
The following related documents are valuable as references.
PDP-11/OS, 11/10 Processor Handbook
PDP-II Peripherals and Interfacing Handbook
PDP-II Paper-Tape Software Programming Handbook
(Document No. DEC-II-GGPB-D)

xiv

PART 1
COMPUTER DESCRIPTION
Part 1 provides a general physical description of the PDP-ll/OS and PDP-ll/l0
computers. Unibus operation is discussed prior to the discussions of computer
installation and operation. The chapters of Part 1 are:
Chapter 1 Chapter 2 Chapter 3 Chapter 4 -

Computer Components
Unibus
Unpacking and Installation
Operation

CHAPTER 1
COMPUTER COMPONENTS

1.1 INTRODUCTION

This chapter briefly describes the major components of the PDP-II/OS, 11/10 Computer. It includes module
utilization diagrams for both computer configurations and a backplane connector and pin designation diagram.
1.2 COMPUTER COMPONENTS

The computer consists of a mounting box, console, processor, core memory, prewired backplane, power supply,
fans, and interconnecting cables. The processor is contained on two modules, and each 4K or 8K memory is
contained on three modules.
1.2.1 KDll-B Processor
The processor comprises the M7260 Data Path Module and the M7261 Control Logic and Microprogram Module.
They are hex height modules which measure 8-1/2 inches long by 15 inches high. A hex height module contains six
edge connectors (A-F).
All the processor functional components are contained on these modules. The M7260 Data Path Module
contains: data path logic, processor status word logic, auxiliary arithmetic logic unit control, instruction register and
decoding logic, and serial communications line interface. The M7261 Control Logic and Microprogram Module
contains: internal address detecting logic, stack control logic, Unibus control logic, priority arbitration logic, Unibus
drivers and receivers, microbranch logic, microprogram counter, control store logic, power fail logic, line clock, and
processor clock.
The serial communications line (SCL) interface is directly connected to the desired serial communications device. It
can operate at speeds of 110-300 baud and is program compatible with the KL11 Teletype Control Interface
option. The SCL is compatible with the LA30 DECwriter at 30 characters per second, the VTOS Alphanumeric CRT
Display Terminal at 30 characters per second, and the Teletype Model 33 ASR at 10 characters per second.
The line time clock (LTC) allows the program to measure time by sensing the 50 Hz or 60 Hz ac line frequency. This
clock is program compatible with the KWII-L line Time Clock option.
The line time clock and the serial communications line interface are not connected to the Unibus; they use an
internal bus and can be addressed only by the processor and the console.
1.2.2 Core Memory
The PDP-ll /05 is available in two versions: one provides a maximum of 8K words of core memory and the other
provides a maximum of 16K words. The PDP-l 1/10 is available only with a maximum of 8K words of core memory.
A separate add-on core memory system (MEll-L) is available to provide an additional 8K, 16K, or 24K words of
core memory. A PDP-II/OS or PDP-l 1/10 processor provides program control for a maximum of 32K words of
memory; there fore, the self-contained memory plus the ME 11-L must not be greater than 32K words.

1-1

Configuration 1 is the 16K version (Figure 1-1). Unibus M930 Terminator Modules are installed in slots A2-B2 and
A5-B5. If other peripherals are to be connected to the computer, the terminator module in slot A2-B2 must be
replaced with a BCllA Unibus cable, and a terminator module must be installed in the last device in the system. Slot
Cl-Fl provides the only space for a small peripheral controller. If this slot is not used, A Gn7 Grant Continuity
Module must be installed in slot Dl. If a small peripheral controller is to be installed, the Gn7 module must be
removed first. Slots Al and BI are wired for the KMII Maintenance Module. The core memories (3 modules each)
are physically interchangeable as systems.

Configuration 2 is the 8K version (Figure 1-2). Unibus M930 Terminator Modules are installed in slots A3-B3 and
A5-B5. If required, a BCllA Unibus cable can be installed in place of the terminator in slot A3-B3. Slots Cl-Fl
C2-F2, C3-F3, and C4-F4 can be used for small peripheral controllers. Slot Al-Bl is wired for a DFll
Communications Line Adapter that provides signal conditioning for communications devices using signals that are
not TTL compatible. Slots A2 and B2 are wired for the KMll Maintenance Module.

Figure 1-3 shows the backplane connector block configuration as viewed from the wirewrap pin side. The pin
arrangement for each connector block is identical. It represents the total pins (36) available on the double-sided edge
connector of a single height module. Connector Al is shown in detail. Module contact designations are shown in
Figure 1-4.

PIN LAYOUT PER BLOCK

. . • . • . • .. . • .. • • .. .
• . . . • • • . •

U
S
P
M
K
H
E
C
A
V • T • R • N • L • J • F • 0 • B •

•

9
V lEW FROM WIRE WRAP PIN SIDE
11- 1220

Figure 1-3 Computer Backplane Connector and Pin Designations

1-4

\0' ' " ""

18 CONTACTS

U
T

SIDE 1
CONTAINS
COMPONENTS

S
R
P

NOTES:
1. Side 1 is component side.
2. Each side contains
18 contacts that are designated
A-V (omitting G,I,O,Q,W,X,Y,Z)
3. A complete designation contains
a connector le)ter prefix,
contact letter,ond side suffix number.
for exomp Ie: A02

N
M
L
K
J
H
F

o
C
B
A

11-1568

Figure 1-4 Module Contact Designations

1.3 MEll-L CORE MEMORY SYSTEM
Additional core memory is available for the computer in the self-contained add-on MEII-L Core Memory System.
The basic MEll-L consists of an 8K MMll-L memory and power supply installed in a mounting box. It is
expandable to 16K words or 24K words maximum by adding one or two more MMll-L memories. The MEII-L uses
the same backplane construction as the computer. Nine slots are provided and they are wired to accommodate three
MMll-L memories. These core memories (3 modules each) are physically interchangeable as systems and as
individual modules within a system for troubleshooting purposes. If only one memory is used, the modules must be
installed in the three bottom slots (7, 8, and 9).

1.4 EXTENSION MOUNTING BOX
Additional interface logic for the computer is installed in an extension mounting box identical to those used for the
rest of the PDP-II family. A rack-mounted box (BAII-ES) or a tabletop box (BAII-EC) can be used. The mounting
box contains cooling fans, filter, and power cord. Space is provided to install six system units and an H720 Power
Supply. Details of the extension mounting box, system units, and H720 Power Supply are included in the PDP-ll

Peripherals and Inter/acing Handbook.

1-5

CHAPTER 2
UNIBUS

2.1 INTRODUCTION
'This chapter describes in general the operation of the Unibus.
The following documents, in conjunction with this manual, will aid the reader in understanding interface techniques
and the overall PDP-ll system.
a.
b.
c.

PDP-II/OS, 11/10 Processor Handbook
PDP-II Peripherals and Interfacing Handbook
Digital Logic Handbook

All communication between PDP-II system components is through the high-speed Unibus. The Unibus operational
concepts are vital to the understanding of the hardware and software implications of the Unibus.
2.2 UNIBUS STRUCTURE
The Unibus is a single common path that connects the processor, memory, and all peripherals. Addresses, data, and
control information are transmitted along the 56 lines of the bus.
Every device on the Unibus employs the same form of communication; thus, the processor uses the same set of
signals to communicate with memory and with peripheral devices. Peripheral devices also communicate with the
processor, memory, or other peripheral devices via the same set of signals.
All instructions applied to data in memory can be applied equally well to data in peripheral device registers, enabling
peripheral device registers to be manipulated by the processor with the same flexibility as memory. This feature is
especially powerful, conSidering the capability of PDP-II instructions to process data in any memory location as
though it were an accumulator.
2.2.1 Bidirectional Lines
Most Unibus lines are bidirectional, allowing input lines to also be driven as output lines. This is significant in that a
peripheral device register can be either read or used for transfer operations. Thus, the same register can be used for
both input and output functions.
2.2.2 Master/Slave Relationship
Communication between two devices on the bus is based on a master/slave relationship. During any bus operation,
one device, referred to as the bus master, has control of the bus when communicating with another device, the slave.
A typical example of this relationship is the processor (master) transferring data to memory (slave). Master/slave
relationships are dynamic. The processor, for example, passes bus control to a disk; the disk, as master, then
communicates with a slave memory.
2-1

The Unibus is used by the processor and all I/O devices; thus, a priority structure determines which device gains
control of the bus. Consequently, every device on the Unibus capable of becoming bus master has an assigned
priority. When two devices capable of becoming bus master have identical priority values and simultaneously request
use of the bus, the device that is electrically closest to the bus receives control.
2.2.3 Interlocked Communication
Communication on the Unibus is interlocked between devices. Each control signal issued by the master device must
be acknowledged by a response from the slave to complete the transfer. Consequently, communication is
independent of the physical bus length and the response time of the master and slave devices. The maximum transfer
rate on the Unibus, with optimum device design, is one I6-bit word every 400 ns or 2.5 million I6-bit words per
second.
2.3 PERIPHERAL DEVICE ORGANIZATION AND CONTROL
Peripheral device registers are assigned addresses similar to memory; thus, all PDP-II instructions that address
memory locations can become I/O instructions, enabling data registers in peripheral devices to take advantage of all
the arithmetic power of the processor.
The PDP-II controls devices differently than most computer systems. Control functions are assigned to a register
address, and then the individual bits within that register can cause control operations to occur. For example, the
command to make the paper-tape reader read a frame of tape is provided by setting a bit (the reader enable bit) in
the control register of the device. Instructions such as MOV and BIS may be used for this purpose. Status conditions
are also handled by the assignment of bits within this register, and the status is checked with TST, BIT, and CMP
instructions.
2.4 UNIBUS CONTROL ARBITRATION
The Unibus is capable of performing two basic and parallel tasks in order to allow transfers by multiple peripherals
at maximum speed. The first is the actual transfer of data between the current bus master and its addressed slave.
The second is the selection of the next bus master, the peripheral which will be allowed to assert control as soon as
the bus becomes free. It is important to note that the granting of future 'mastership is in no way influenced by either
the current master or its method of obtaining the bus. It is this fact which allows these functions to be performed in
parallel and allows transfers on the bus at a maximum rate.
2.4.1 Priority Transfer Requests
To gain mastership of the Unibus, a peripheral must first make a request to the processor for the bus and then wait
for its selection. The processor contains the logic necessary to arbitrate these requests because normally there are
several requests pending at any given time.
There are two classes of requests: bus requests and non-processor requests. A bus request (BR) is simply a request
by a peripheral to obtain control of the Unibus with the understanding by the processor that the peripheral may end
its use of the bus with a processor interrupt. An interrupt is a command to the processor to begin executing a new
routine pointed to by a location selected by a device. A non-processor request (NPR) is similarily a request for the
bus, but with the exception that it may not interrupt the processor. Since the granting of an NPR cannot affect the
execution of the processor, it can occur during or between instructions. BRs however, by possibly causing execution
to be diverted to a totally new routine, can only be granted between instructions. In this way, NPRs are assigned
priority over any BR.
Between bus requests, there are four .levels of priority created by four separate request lines. They are assigned
priority levels 4 through 7; BR4 is the lowest and BR7 is the highest. These levels are associated with the program
controlled priority level of the processor controlled by bits 7,6, and 5 of the processor status register. Only BRs on
a priority level higher than the level of the processor are eligible for receiving a bus grant. Thus, during high priority
program tasks, all or selected Unibus requests (hence interrupts~ can be inhibited by raising the level of the processor
priority.
2-2

Another form of priority arbitration occurs through the system configuration. When the processor grants a request,
the grant travels along the bus until it reaches the first requesting device which terminates the grant. Therefore, along
the same grant line, the device electrically nearest the processor has the highest priority. Also note that in the
KDII-B, the internal line clock is logically the last device on BR6, and the serial communication line interface is
logically the last device on BR4.
After a requesting device receives a bus grant it asserts its selection as next bus master until the bus is free, thus
inhibiting other requests from being granted. When the bus becomes free, the selected device asserts control of the
bus and relinquishes its selection as next bus master so that the priority arbitration among pending requests may
continue.
2.4.2 Processor Interrupts
After gaining control of the bus through a BR, a device can perform one or more transfers on the bus and/or request
a processor interrupt. This is typically requested after a device has completed a given task; e.g., typing a character or
completing a block data transfer through NPRs. If a peripheral wishes to interrupt the processor, it must assert the
interrupt after gaining control of the bus but before relinquishing its selection as next bus master. Thus the processor
knows that it may not fetch the next instruction, but must wait for the interrupt to be completed. Along with
asserting the interrupt, the device asserts the unique memory address, known as the interrupt vector address,
containing the starting address of the device service routine. Address vector +2 contains the new processor status
word (PSW) to be used by the processor when beginning the service routine. After recognizing the interrupt, the
processor reads the vector address and saves it in an internal register. It then pushes the current PSW and program
counter onto the stack and loads the new program counter (PC) and PSW from the vector address specified. The
service routine is then executed.

NOTE
These operations are performed automatically and no
device polling is required to determine which routine to
execute.

The device service routine can cause the processor to resume the interrupted process by executing the return from
interrupt (RTI) instruction which pops the top two words from the processor stack and transfers them back to the
PC and PS registers.
2.4.3 Data Transfers
After asserting control of the Unibus, the device does not release control until it has completed either one or more
data transfers or an interrupt. Typically, only one transfer is completed each time the device gains control of the bus
because few single devices can give or receive information at the maximum Unibus rate. Holding the bus for multiple
transfers inhibits other devices from using the bus.
A transfer is initiated by the master device asserting a slave address and control signals on the bus and a master or
address validity signal. The appropriate slave recognizes the valid address, reads or writes the data, and responds with
a transfer complete signal. The master recognizes the transfer complete, sends or accepts data, and drops the address
validating signal. It can then assert a new address and repeat the process or release control of the bus completely.
The importance of this type of structure is that it enables direct device-ta-device transfers without any interaction
from the central processor. An NPR device, such as a high speed CRT display, can gain fast access to the bus and
transfer data at high rates while refreshing itself from memory without slowing down the processor.

2-3

CHAPTER 3
UNPACKING AND INST ALLATION

3.1 INTRODUCTION
The computer is shipped ready to operate in either a protective box or a 19-inch cabinet. Unless required by
peripherals, there are no special shipping mounts internal to the computer. Prior to final electrical testing, each
computer is thermal cycled, vibrated, and subjected to mechanical shock with all modules in place.
Basic computers are shipped in the package illustrated in Figure 3-1. Sufficient hardware is included in the shipping
carton to rack mount the computer.
3.2 UNPACKING

Remove the computer from the box and remove the protective plastic cover from the console. Slide mounts are
attached to the computer, but mounting screws are packed in a bag located in the same box. Also included is one
83600 Serial Communication Line (SCL) cable and two keys for the console lock. The 83600 SCL cable has a Berg
127009-0, 40-pin connector on one end that matches the SCL output connector on the computer. The other end of
the 83600 SCL cable terminates in a Mate-N-Lok 1209340 which matches that used on the VT05, LA30, and Model
33 ASR Teletype@.
If the computer was ordered as a system with options requiring small peripheral controllers, the controllers may be
inside the computer box. Small peripheral controllers are used to interface options such as a line printer or
paper-tape reader/punch, as well as to implement a device such as a programmable clock.
Mter removing the computer from its package, it should be inspected for damage. It is advisable to save the packing
carton in case it is necessary to return the unit for service.
A computer shipped in a 19-inch cabinet is locked in place by a metal lock attached to the rear of each slide
assembly. Each lock is J-shaped and is attached by an 8-32 screw that passes through the slot in the chassis section of
the slide and is threaded into the longer leg of the lock. The shorter leg is hooked around the end of the cabinet
section of the slide to prevent extension of the slide. Both locks must be removed in order to slide the computer out
of the cabinet. Retain the locks and screws for re-use if the equipment is to be shipped or moved any distance.
3.3 MECHANICAL DESCRIPTION

Figure 3-2 illustrates the 5-1/4 by 19 by 20 inch computer mounting box, including rack-mountable slide and
console. The removable top cover of the mounting box is fastened by four Cam-Lock screws. The removable side
panel is fastened by four Phillips-head screws.
Figure 3-3 shows the mounting box with the top cover removed. The backplane unit divides the power supply from
the module side of the mounting box. The internal SCL cable runs from the backplane under the power supply unit
to the rear of the mounting box.
®reletype is a registered trademark of the Teletype Corporation.
3-1

FOAM

FOLDED CORRUGATED
--LAMINATED CEE

PDP-11/05
BEZEL PROTECTOR

POLYETHYLENE BAG

PDP-11/05

20 x 13 x 40

11-1223

Figure 3-1 Computer Packaging

3-2

RENOYABlE TOP

COVE~

Figure 3-2 Computer Mounting Box

Figure 3-3 Computer Box With Top Cover Removed
3-3

Figure 3-4 shows the mounting box with top cover and side panel off, and the processor and memory modules
plugged in. In this case, the computer is a Configuration 2 machine, using an MMII-L, 8K memory unit. Three small
peripheral controllers are shown with the external cables attached. A G727 Grant Continuity Card is in the top
peripheral slot and an M930 Unibus Terminator Card is in slot A3, B3. In Figure 3-5, the Unibus cable is in place,
replacing the Unibus terminator card.
Figure 3-6 shows the mounting box without modules. The path of the console cable is under the M7260 Processor
Module, then up and over to plug into the top of the M7260. The module guides aid in inserting the modules into
proper slots.
Figure 3-7 is a rear view of the mounting box with attached rack-mountable slides. If the computer contains
peripheral controllers outside the mounting box, the Unibus is extended from under the top cover. The power
control circuit breaker protects the power supply from overload. It is rated at 7 A for llOV units or 4A on 230V.
The SCL connector and ac remote power control connectors are also shown.

UNIBUS TERMINATOR

FRONT.

SMAlL.PEJlfPHERAI... eONTROLLER

Figure 3-4 Computer Box with Top and Side Covers Removed
UNIBUS CAttLE AND UNIBUS CABLE CLAMP

Figure 3-5 Computer Chassis (showing peripheral cables and the Unibus)

3-4

GENTER
:,;~'U;

Cif

'::.iL c: T

CONSOLE CABLE CONNeCTOR

Figure 3-6 Mounting Box Without Modules

L:Nf:. Cr'Ni.
:;IFlCU:T f)Hf: c,X (' '''.>,SSEMBLY

P(flf;;~gl G~;::rr f~C~.. ~

;~NC

GJ\5~Nf:-~'f YOlj.i'£!~

(;O"ITf?OL

'~~CiNTk\J;TS

Figure 3-7 Rear of Computer With Cable Strain Reliefs
3-5

SLOT C

3.4 INSTALLATION
The computer mounts in a standard 19-inch wide by 25-inch deep equipment bay. The computer is mounted on
slides for easy service. To mount the unit, first attach the fixed portion of the slides to the cabinet; the fixed portion
of the slides can be removed from the computer by actuating the slide release shown in Figure 3-4. Be sure to mount
the slides so that the fixed guides are parallel and level with the ground.

3.4.1 Mounting Computer on Installed Slides
Once the slide guides have been securely fastened in the cabinet using all eight screws, lift the computer and slide it
carefully onto the slide guides until the slide release locks. Lift the slide release and push the computer fully into the
rack, being careful not to tear any existing cabling.
Slightly loosen all eight cabinet slide mounting screws. Slide the computer back and forth several times to allow the
slides to assume an optimum position. Push the computer into the cabinet as far as possible, leaving access to the
front mounting screws. Tighten all eight cabinet slide mounting screws. Slide the computer back and forth and check
for binding of the slides. If there is binding, repeat the above procedure until it is eliminated.
The computer should then be fully extended until the slide release locks. As shown in Figure 3-4, the panel on the
module side of the computer should be removed to permit installation of I/O cables and the Unibus if required. The
panel is removed by loosening and removing four Phillips-head screws.

3.4.2 Securing Computer to Cabinet Rack
If the rack-mounted computer is used in a moving environment, it must be secured to the cabinet rack to prevent the
machine from moving on its slides. This option, if desired, is implemented as follows:
1.

Remove the console bezel from the computer by removing the four screws at the rear of the bezel, being
careful not to tear the cable that connects the console and processor.

Drill the partial 7/3 2-inch holes at each top inside comer of the bezel through from the rear of the bezel.

Counter-bore the 7/32-inch holes at the front of the console bezel 1/2 inch in diameter to a depth to
accommodate the full head of a 10-32 machine screw.

Replace the console bezel.

Use two 10-32 by 2-inch Phillips-head screws and two Tinnerman nuts (PN 9007786) to secure the
computer to the cabinet rack through the bezel holes at the desired rack position.

To make the 10-32 by 2-inch Phillips-head screws captive, machine a 1/8-inch deep by 1/8-inch wide
groove, in each 10-32 by 2-inch Phillips-head screw just above the threads toward the head and insert a
1/8 I.D. O-ring in each groove.

3.4.3 Installation of I/O Cables
Flat and round I/O cables should be fed through the universal I/O cable clamp shown in Figure 3-6 for strain relief.
They should then be connected to the appropriate small peripheral controllers. Note that the strain relief clamp
prevents tension on the cables from damaging the connector block inside the computer. The wide Unibus cable, if
required, should be folded as shown in Figure 3-5 and routed over and through a clamp attached to the top of the
fan as shown in Figure 3-7. Note that there is a guide extending from the fan that prevents the Unibus cable from
blocking air flow to the computer.

3-6

As shown in Figure 34, systems in which the Unibus is terminated in the computer box must have an M930
Terminator Card in slot A3-B3 as well as in slot A5-B5.

3.5 INTERCHANGEABLE PERIPHERAL SLOTS
The four peripheral slots in Configuration 2 are identical; therefore, it is possible to arrange the small peripheral
controllers for the best mechanical convenience. For example, to diagnose a failure in a small peripheral controller, it
may be convenient to place the selected option in the top slot where its components will be exposed.

3.6 SIDE AND TOP COVER INSTALLATION
Figures 34 and 3-5 show the computer ready for installation of the side cover. Note that the console cable is folded
into a flat loop in order to clear the side cover. Attached to the side cover is the continuation of the left-hand slide.
All four 8-32 screws that hold the cover in place should be inserted and tightened securely. The top cover can now
be installed using the four Cam-Lock screws.

3.7 AC POWER SUPPLY CONNECTION
Computers designed for use on 115-Vac circuits are equipped with a 3-prong connector, which, when inserted into a
properly wired 115-Vac outlet, grounds the case of the computer. It is unsafe to operate the computer unless the
case is grounded since normal leakage current from the power supply flows into metal parts of the chassis.
If the integrity of the ground circuit is questionable, the user is advised to measure the potential between the
computer case and a known ground with an ac voltmeter.

3.7.1 Connecting to Voltages Other than 115V
The computer will operate at voltages ranging from 95V to 135V and from 190V to 270V (47 Hz - 63 Hz),
providing the proper power control is attached to the computer. The computer is ordered for nominal voltages of
115V or 230V. The standard 3-prong connector for 115V is identical to that found on most household appliances. A
standard 3-prong connector is also used for 230V.
On installations outside of the United States or where the National Electrical Code does not govern building wiring,
the user is advised to proceed with caution.

3.7.2 Quality of AC Power Source
Computer systems consisting of CPU, memory, and peripherals are often sensitive to the interference present on
some ac power lines. If a computer system is to be installed in an electrically "noisy" environment, it may be
necessary to condition the ac power line. DEC Field Service Engineers can assist customers in determining if their ac
line is satisfactory.

3.8 CABINET POWER CONTROL
Provisions have been made for the computer switch to operate a cabinet power control. This feature permits the
computer key lock switch to control the power supply for peripherals attached to the computer (Part 4). The power
control contacts are closed when the key lock switch is in the POWER or PANEL LOCK positions. The wiring
diagram for a typical cabinet power control system is shown in Figure 3-8. The power control contacts of the
computer may be used to switch a maximum of 230V at 4A.

3-7

r------,

I
I
I
I

----,
I

.-+--_TO MOTOR

------,

CABINET

I (1\POWER
L.\.V CONTROL

TO
I
CONTROLLER
POWER •
SUPPLY

TO
I
CONTROLLER
POWER
SUPPLY

I
1

: o-t-=-:----=-:

t-<>+-r+o-+-=----=-JI-O+-.-+o-+=-t-+..........t-<>+-=-+ot-=---=-t<>. -

L0 ~S::~E:' _...J 0

.......
/
/'

rlHe--f-o-H-+o-t----'

POWER CONTROL BUS SWITCH

CABINET THERMOSTAT

POWER
CONTROL

~~ ~

@ PRO'::S~

.----LEl

~ ~ == ~+:g
-

C~~tE

0
11-1225

Figure 3-8 Typical Cabinet Power Control System Wiring Diagram

3.9 INSTALLATION CERTIFICATION
Once the computer has been installed, it is strongly recommended that a system diagnostic be run to ensure that the
equipment operates correctly and that installation has been properly performed. Because system configurations
widely vary, no one diagnostic will completely exercise all the attached devices.
The MAINDEC User's Manual that comes with the diagnostic package should be consulted for the appropriate
diagnostic to be run, depending upon the attached devices. The MAINDEC User's Manual lists the devices that each
diagnostic will exercise. The three system exercisers presently available are T17 System Exerciser
(MAINDEC-II-DZKAP) for relatively small systems, General Test Program (MAINDEC-II-DZQGA) for medium to
large systems, and Communications Test Program (MAINDEC-II-DZQCA) for communications-oriented systems. At
least one of the above diagnostics and, if appropriate, the other two, should be used to verify system operation.
Once the diagnostic is selected, the respective diagnostic write-up should be consulted for specific operating
instructions. If the user is not familiar with console operation and/or procedures for loading paper tapes, he should
read Chapter 4 of this manual.

3-8

3.10 WARRANTY SERVICE (Domestic Only)
If the machine is still covered under the 30 day return-to-factory warranty, and it is desired to return it for factory
service, the following procedure should be used. If the machine is no longer on warranty, the local DEC Field Service
office should be contacted.
1.

Call the Maynard, Massachusetts Repair Depot, Telephone 617-897-5111, X4079 Or X2135.

The caller will receive an RA (Return Authorization) number, which must appear on the shipping label
of the package being returned.

Package the machine in an equivalent shipping container, similar to the one the computer arrived in. If
possible, use the original computer shipping container.

Send the machine to the following address:
Digital Equipment Corporation
146 Main Street
Maynard, Massachusetts 01754
Att: Depot Repair, Bldg, 21-4
RA#XXXX

3-9

CHAPTER 4
COMPUTER OPERATION

4.1 INTRODUCTION
This chapter assumes that the computer is installed and connected to the ac power line. It is also assumed that the
reader has access to the appropriate diagnostic materials, and a copy of the absolute loader paper tape. It is further
assumed that the user is using paper tapes to load software and diagnostics. For systems that have mass storage
services, i.e., disks or DECtape, the user should refer to the appropriate software manuals for mass storage operating
systems.
4.2 POWER SWITCH OPERATION
The key lock power switch shown in Figure 4-1 has three positions:
OFF - Fully counterclockwise
POWER - 90° clockwise from OFF
PANEL LOCK - 1800 clockwise from OFF
In the OFF position, ac power is removed from the primary of the computer power supply, and the cabinet power
control contacts are open-circuited. In the other two positions, the ac power is applied to the computer power
supply and the cabinet power control contacts are short-circuited. In the POWER position, the console function
switches (the right six switches in Figure 4-1) are fully operative. In the PANEL LOCK position, the console
function switches have no effect on the computer's operation. PANEL LOCK is used to secure a running computer
from mischievous tampering.

Figure 4-1 Console Illustrating Switch Movements
4-1

4.3 FUNCTION SWITCHES
The right six switches in Figure 4-1 are called function switches. They are listed below in order of their appearance
from left to right.
1.

2.
3.
4.
5.
6.

LOAD ADRS (load address)
EXAM (examine)
CONT(continue)
ENABLE/HALT
START
DEP (deposit)

Function switches 1 through 5 are actuated by being depressed as is the ENABLE/HALT switch in Figure'4-l. The
DEP switch must be lifted for actuation. All of the function switches, with the exception of ENABLE/HALT, are
spring loaded and return to their rest state when released.
4.4 ADDRESS/DATA SWITCHES
The 16 ADDRESS/DATA switches are to the left of the function switches (Figure 4-1). These 2-position switches
represent a manually set flip-flop register with the up position representing a logical 1 and the down position a
logical O. The ADDRESS/DATA switches may be used in conjunction with the function switches or in conjunction
with a program stored in the computer's memory. The ADDRESS/DATA switches are often referred to as the
Switch Register in DEC documentation. In Figure 4-1, the contents of the Switch Register is equal to 200 8 because
bit 7 is set to a 1 and all others are set to a O.
4.5 CONSOLE INDICATORS
There are 17 indicators on the computer console. The contents of the 16 ADDRESS/DATA lights either represent a
16-bit Unibus address or the contents of a 16-bit Unibus address. Note that the state of the ADDRESS/DATA lights
is defined only when the computer RUN light is not illuminated.
4.6 CONSOLE OPERATION
The follOwing paragraphs describe the operation of the function switches. Table 4-1 indicates the meaning of the
ADDRESS/DATA lights for all cases where the contents of these lights are defined.
4.6.1 Load Address Switch
Depressing the LOAD ADRS switch when the computer is halted causes the contents of the Switch Register to be
stored in a temporary register within the computer. This data is also displayed in the ADDRESS/DATA lights for
verification. The load address operation performs the following functions:
a.
b.
c.

Selects a Unibus address for a subsequent examine operation.
Selects a Unibus Address for a subsequent deposit operation.
Selects the starting address of a program.

4.6.2 Examine Switch
The EXAM switch permits the display of the contents of a selected Unibus address in the ADDRESS/DATA lights.
Select the appropriate address in the Switch Register and depress the LOAD ADRS switch. Then depress and release
the EXAM switch. The contents of the selected address will then be displayed in the ADDRESS/DATA lights.
Several features are built into the examine function to aid in programming the computer.
a.
b.

While the EXAM switch is depressed, the address to be examined is displayed. The data itself is displayed
when the switch is released.
If the EXAM switch is repeatedly depressed, the Unibus address is incremented by two on each
depression * . This permits the examination of a list of addresses without repeated load address
operations.

*The Unibus address is incremented by one when examining general registers.
4-2

Table 4-1
Significance of ADDRESS/DATA Indicators
Action

Qualification

Information Displayed In
ADDRESS/DATA Indicators

1. ENABLE/HALT switch in
HALT position

1. Contents of location (24)8

2. ENABLE/HALT switch in
ENABLE position

2. Undefined - depends on
contents of memory

Load Address

LOAD ADRS switch depressed

Contents of Switch Register

Examine

1. EXAM switch depressed

1. Unibus address that is to
be examined

2. EXAM switch released

2. Contents of Unibus address
that was examined

1. DEP switch raised

1. Unibus address that is to
be deposited

2. DEP switch released

2. Contents of Switch Register
which is the data deposited

Power On

Deposit

RUN Light On
Program Halt

Program
Execution

c.
d.

Undefined
1. ENABLE/HALT switch
in HALT position

1. Address of instruction to
be executed when CONT
switch is actuated

2. HALT instruction
executed

2. Same as 1

3. Double bus error which
is two successive attempts
to access non-existent
memory or improper odd
byte address.

3. Contents of program
counter (R7) at time
double bus error occurred

1. START switch depressed

1. Address of last load address

2. CONT switch depressed

2. Address of instruction to be
executed

If an attempt is made to examine non-existent memory, it is necessary to perform the initialize
operation explained in Paragraph 4.7.
Only full words are displayed in the ADDRESS/DATA lights; thus, bit 0, the byte address bit, is ignored
when using the EXAM switch with the following exception. Note that the general registers are located
on byte addresses. Therefore, when examining the general registers, address bit 0 is recognized and the
increment feature is modified such that sequential registers may be examined by repeated use of the
EXAM switch.

4-3

Note that the EXAM switch has no effect while the computer is in the RUN state or when the key operated power
switch is in the PANEL LOCK position.
4.6.3 Deposit Switch
The physical operation of the DEP switch requires that it be lifted for actuation. The DEP switch permits the
contents of the Switch Register to be deposited in a Unibus address, which is typically specified by a previous load
address operation. To deposit the instruction BRANCH SELF (777 8) in location 200 8 , first set the Switch Register
to 2008 as shown in Figure 4-1 and actuate the LOAD ADRS switch. Set the Switch Register to 7778 then lift and
release the DEP switch.
Several additional features are built into the deposit function:
a.

While the DEP switch is actuated, the Unibus address to be effected is displayed in the
ADDRESS/DATA lights. When the switch is released, the data deposited is displayed for verification.

If the DEP switch is repeatedly depressed, the Unibus address is incremented by two on each
depression*. This permits the depositing of an entire program with only one load address operation.

If an attempt is made to deposit into non-existent memory, it is necessary to perform the initialize
operation l:xplained in Paragraph 4.1.

All deposit operations affect full 16-bit words. Bit 0 of the address is used only when depositing into
general registers, otherwise, bit 0 of the address is ignored.

4.6.4 ENABLE/HALT Switch
Place the ENABLE/HALT switch in the HALT position (Figure 4-1); the computer will halt at the end of the
current instruction, providing the key switch is not in the PANEL WCK position. All interrupts and traps will be
executed prior to halting. This switch may be used in conjunction with the CONT switch to step through programs
(Paragraph 4.6.6). With the ENABLE/HALT switch in the ENABLE position, programs may be executed once
started by: actuating the START switch, actuating the CONT switch, and the auto-restart power-up sequence.
4.6.5 START Switch
The sequence for starting a program from the console is as follows:
1.
2.
3.
4.

Set the starting address of the program in the Switch Register.
Depress the LOAD ADRS switch.
Position the ENABLE/HALT switch in the ENABLE position.
Depress and release the START switch.

While the START switch is depressed, the following actions occur:
1.

An initialize signal is generated on the Unibus. This initialize signal serves to reset all peripherals.

The program status word is reset to zero.

The program counter, R7, is loaded with the last address loaded with the LOAD ADRS switch.

When the START switch is released, program execution begins with the instruction contained in the location
specified by R7 and the RUN light is turned on. If the ENABLE/HALT switch is in the HALT position, the
computer remains in the HALT state following the release of the START switch.
*The Unibus address is incremented by one when depositing into general registers.
4-4

Observe the following precautions when using the START switch:
a.

If the keylock is not in the PANEL LOCK position, depressing the START switch while a program is
running initializes the computer system and restarts the program.

It is good practice to precede every program start with a load address operation.

A program should not be started at an odd address or the first fetch operation will be aborted and an
odd address trap will be attempted. If the stack pointer, R6, is not properly set up, the program in
memory may be destroyed.

4.6.6 Continue Switch
The CONT switch is used to continue a program without altering the program counter, R7, or the machine state. To
continue a halted program, depress and release the CONT switch. The program is resumed when the CONT switch is
released.
The CONT switch is used with the ENABLE/HALT switch to step through programs one instruction at a time. If the
CONT switch is actuated while the ENABLE/HALT switch is in the HALT position (Figure 4·1), a single instruction
will be executed. Note that interrupts are serviced in single instruction mode. In single step mode, the address of the
next instruction to be executed is displayed in the lights.
4.7 UNCONDITIONAL COMPUTER AND UNIBUS INITIALIZA:rION
Unconditional initialization of the computer system usually occurs because of an attempt to examine from, or
deposit into, non·existent memory from the console. However, a peripheral or processor error may occur that can
only be overcome by initializing the system from the console. The procedure is simply to depress the START switch
with the ENABLE/HALT switch in the HALT position.
4.8 LOADING PROGRAMS FROM PAPER TAPE
When the computer is first received, the content of its memory is not defined (it knows absolutely nothing, not even
how to receive paper-tape input). However, the computer can accept data when toggled directly into core using the
console switches. The Bootstrap Loader program is the first program to be loaded, and therefore must be toggled
into core. The loaders described in this section facilitate the loading of programs from either the low or high speed
paper-tape reader. The low speed reader is part of the Model 33 ASR Teletype and is operated via the SCL. The high
speed reader is DEC part number PC·11.
The Bootstrap Loader program instructs the computer to accept and store in core data that is punched on paper
tape in bootstrap format. The Bootstrap Loader is used to load very short paper·tape programs of 162 8 16-bit words
or less (primarily the Absolute Loader and Memory Dump programs). Programs longer than 162 8 16·bit words must
be assembled into absolute binary format using the PAL-11A Assembler and loaded into memory using the Absolute
Loader.
The Absolute Loader (Paragraph 4.8.2) is a system program that enables data punched on paper·tape in absolute
binary format to be loaded into any available memory bank. It is used primarily to load the paper·tape system
software (excluding certain subprograms) and object programs assembled with PAL-llA.
The loader programs are loaded into the upper most area of available memory so that they will be available for USe
with system and user programs. When writing programs, the locations used by the loaders should not be used
without restoring their contents; otherwise, the loaders will have to be reloaded because the object program will have
altered them.
Memory Dump programs are used to print or punch the contents of speCified areas of memory. For example, when
developing or debugging user programs, it is often necessary to get a copy of the program or portions of memory.
4-5

There are two dump programs supplied in the paper-tape software system: DUMPIT, which prints or punches the
octal representation of all or specified portions of memory; and DUMPAB, which punches all or specified portion of
memory in absolute binary format suitable for loading with the Absolute Loader.
4.8.1 The Bootstrap Loader
The Bootstrap Loader should be loaded (toggled) into the highest memory bank. The locations and corresponding
instructions of the Bootstrap Loader are listed in Table 4-2 and explained below.

Table 4-2
Bootstrap Loader Instructions
Location

Instruction

XX7744
XX7746
XX7750
XX7752
XX7754
XX7756
XX7760
XX7762
XX7764
XX7766
XX7770
XX7772
XX7774
XX7776

016701
000026
012702
000352
005211
105711
100376
116162
000002
XX7400
005267
177756
000765
YYyYy

In Table 4-2, XX represents the highest available memory bank. For example, the first location of the loader would
be as indicated in Table 4-3, depending on memory size, and XX in all subsequent locations would be the same as
the first.
Note in Table 4-3 that the contents of location XX7766 should reflect the appropriate memory bank in the same
manner as the preceding locations.

Table 4-3
Memory Bank Assignments
Location

Memory Bank

Memory Size

017744
037744
057744
077744
117744
137744
157744

0
1
2
3
4
5
6

4K
8K
12K
16K
20K
24K
28K

4-6

The contents of location XX7776 (YYYYYY in the instruction column of Table 4-2) should contain the device
status register address of the paper-tape reader to be used when loading the bootstrap formatted tapes. Either
paper-tape reader may be used, and the associated address is specified as follows:
Teletype Paper-Tape Reader - 177560
High Speed Paper-Tape Reader - 177550
4.8.1.1 Loading the Loader Into Memory - With the computer initialized for use as described in Paragraph 4.7,
toggle in the Bootstrap Loader as explained below.
1.

Set XX7744 in the Switch Register (SR) and press LOAD ADRS switch (XX7744 will be displayed).

Set the first instruction, 01670l, in the SR and lift DEP switch (016701 will be displayed).
NOTE
When depositing data into consecutive words, the DEP switch
automatically increments the address to the next word.

Set the next instruction, 000026, in the SR and lift DEP switch. Continue to deposit subsequent
instructions.

Deposit the desired device status register address in location XX7776 , the last location of the Bootstrap
'
Loader.

NOTE
It is a good programming practice to verify that all instructions

are stored correctly. Proceed to Step 6.
6.

Set XX7744 in the SR and press LOAD ADRS switch.

Press and release EXAM switch (the octal instruction in location XX7744 will be displayed so that it can
be compared to the correct instruction, 016701). If the instruction is correct, proceed to Step 8,
otherwise go to Step 10.

Press EXAM switch. The instruction of the location displayed in the ADDRESS/DATA indicators with
the switch depressed will be displayed when the switch is released. Compare the indicator contents to
the instruction at the proper location.

Repeat Step 8 until all instructions have been verified or go to Step 10 if the correct instruction is not
displayed.

NOTE
Whenever an incorrect instruction is displayed, it can be
corrected by performing Steps 10 and 11.
10.

With the incorrect instruction displayed in the ADDRESS/DATA register, set the correct instruction in
the SR and lift DEP switch. The contents of the SR will be deposited in the location displayed with the
key lifted.

11.

Press EXAM switch to ensure that the instruction was correctly stored.

The Bootstrap Loader is now in core. The procedures above are illustrated in the flow chart of Figure 4-2.

4-7

Verify

11- 1219

Figure 4-2 Loading and Verifying the Bootstrap Loader

4.8.1.2 Loading Bootstrap Tapes - Any paper tape punched in bootstrap format is referred to as a bootstrap tape
and is loaded into memory using the Bootstrap Loader. Bootstrap tapes begin with about two feet of special
bootstrap leader code (ASCII code 351, not blank leader tape as is required by the Absolute Loader).
With the Bootstrap Loader in memory, it will load the bootstrap tape into memory starting anywhere between
location XX7400 and location XX7743; i.e., 162 8 words. The paper-tape input device used is specified in location
XX7776. Bootstrap tapes are loaded into memory as explained below:
1.

Set the ENABLE/HALT switch to HALT.

Place the bootstrap tape in the specified reader with the special bootstrap leader code over the reader
sensors (under the reader station).

Set the SR to XX7744 (the starting address of the Bootstrap Loader) and press LOAD ADRS switch.

Set the ENABLE/HALT switch to ENABLE.

Press START switch. The bootstrap tape will pass through the reader as data is being loaded into
memory.
4-8

The bootstrap tape stops after the last frame of data (Figure 4-5) has been read into memory. The
program on the bootstrap is now in memory.

The procedures above are illustrated in the flowchart of Figure 4-3.

- - - - - - - -1...__

S_e_e_F_i9_u_re_4_-_2_ _

~------~------~

Code 351 must be
over Reader sensors

11-1218

Figure 4-3 Loading Bootstrap Tapes Into Memory

If the bootstrap tape does not read in immediately after depressing the START switch, it is due to one of the
following reasons:
a.
b.
c.
d.

Bootstrap Loader not correctly loaded
Using the wrong input device
Code 351 not directly over the reader sensors
Bootstrap tape not properly positioned in reader

4.8.1.3 Bootstrap Loader Operation - The Bootstrap Loader source program is shown below. The starting address
in the example denotes that the program is to be loaded into memory bank zero (a 4K system).

The Bootstrap Loader source program is a brief but fairly complex example of the PAL-IIA Assembly Language.
Explanations of the program and PAL-II A are found in the PDP-II Paper-Tape Software Programming Handbook,
DEC-II-GGPB-D.

4-9

017744
017750
017754
017756
017760
017762

000001

Rl=%1

000002

R2 %2

017400

LOAD=17400

017744

.-17744

016701
000026
012702
000352
005211
105711

START:

MOV DEVICE, Rl

LOOP:

MOV # .-LOAD+2, R2

ENABLE:
WAIT:

INC@Rl
TSTD@Rl
BPL WAIT
MOVB 2(Rl), LOAD (R2)

017774

100376
116162
000002
017400
005267
177756
000765

BRNCH:

BRLOOP

017776

000000

DEVICE:

017770

INC LOOP+2

;USED FOR THE DEVICE
;ADDRESS
;USED FOR THE LOAD AD;DRESS DISPLACEMENT
;DATA MAY BE LOADED NO
;LOWER THAN THIS
;START ADDRESS OF THE
;BOOTSTRAP LOADER
;PICK UP DEVICE ADDRESS,
;PLACE IN Rl
;PICK UP ADDRESS
;DISPLACEMENT
;ENABLE THE PAPER TAPE
;READER
;WAIT UNTIL FRAME
;IS AVAILABLE
;STORE FRAME READ
;FROM TAPE IN MEMORY
;INCREMENT LOAD ADDRESS
;DISPLACEMENT
;GO BACK AND READ MORE
;DATA
;ADDRESS OF INPUT DEVICE

4.8.2 The Absolute Loader
The Absolute Loader is a system program that enables data punched on paper tape in absolute binary format to be
loaded into any memory bank. It is used primarily to load the paper-tape system software (excluding certain
subprograms) and object programs assembled with PAL-IIA. The major features of the Absolute Loader include:
a.

Testing of the checksum on the input tape to ensure complete, accurate loads

Starting the loaded program upon completion of loading without additional user action, as specified by
the .END in the program just loaded

Specifying the load address of position independent programs at load time rather than at assembly time,
by using the desired loader Switch Register option.

4.8.2.1 Loading the Loader Into Memory - The Absolute Loader is supplied on punched paper-tape in bootstrap
format, therefore, the Bootstrap Loader is used to load the Absolute Loader into memory. It occupies locations
XX7474 through XX7743, and its starting address is XX7500. The Absolute Loader program is 72 10 words long,
and is loaded adjacent to the Bootstrap Loader.
4.8.2.2 Loading Absolute Tapes - Any paper-tape punched in absolute format is referred to as an absolute tape,
and is loaded into memory using the Absolute Loader. When using the Absolute Loader, there are two methods of
loading available: normal and relocated.
A normal load occurs when the data is loaded and placed in memory according to the load addresses on the object
tape. It is specified by setting bit 0 of the Switch Register to 0 immediately before starting the load.

4-10

There are two types of relocated loads:
a.

Loading to continue from where the loader left off after the previous load. This type is used, when the
object program being loaded is contained on more than one tape. It is specified by setting the Switch
Register to 000001 immediately before starting the load.

Loading into a specific area of memory. This is normally used when loading position independent
programs. A position independent program is one that can be loaded and run anywhere in available
memory. The program is written using the position independent instruction format. The type ofload is
specified by setting the Switch Register to the load address and adding 1 to it (i.e., setting bit 0 to 1).

Optional Switch Register settings for the three types of loads are listed below.
Switch Register
Bits 1-14
Bit 0

Type of Load

(ignored)

Normal

Relocated - continue
loading where left off
Relocated - load in
specified area of memory

nnnnn
(specified
address)

The absolute tape may be loaded using either paper-tape reader. The desired reader is specified in the last word of
available memory (XX7776). The input device status word may be changed at any time prior to loading the absolute
tape. With the Absolute Loader in memory, absolute tapes are loaded as explained below:
1.

Set the ENABLE/HALT switch to HALT. To use an input device other than that used for loading the
Absolute Loader, change the address of the device status word (in location XX7776) to reflect the
desired device; i.e., 177560 for the Teletype reader or 177550 for the high-speed reader.

Set the SR to XX7500 and press LOAD ADRS switch.

Set the SR to reflect the desired type of load.

Place the absolute tape in the proper reader with blank leader tape directly over the reader sensors.

Set ENABLE/HALT switch to ENABLE.

Press START switch. The absolute tape will begin passing through the reader station as data is being
loaded into memory.

If the absolute tape does not begin passing through the reader station, the Absolute Loader is not in memory
correctly. Reload the loader and start over at Step 1. If it halts in the middle of the tape, a checksum error occurred
in the last block of data read in.

Normally, the absolute tape will stop passing through the reader station when it encounters the transfer address as
generated by the statement .END, denoting the end of a program. If the system halts after loading, check that the
low byte of RO is 0*_ If so, the tape is correctly loaded. If not 0, a checksum error has occurred in the block of data
just loaded, indicating that some data was incorrectly loaded. The tape should be reloaded starting at Step 1.
*To read RO, load address 177700 and press EXAM switch.
4-11

4.8.3 Memory Dumps
A Memory Dump program is a system program that enables the contents of all or any specified portion of memory
to be dumped (print or punch) onto the teletype printer and/or punch, line printer, or high speed punch. There are
two dump programs available in the paper-tape software system:
a.

DUMPIT, which dumps the octal representation of the contents of specified portions of memory onto
the teleprinter, low speed punch, high speed punch, or line printer.

DUMPAB, which dumps the absolute binary code of the contents of specified portions of memory onto
the low speed or high speed punch.

Both dump programs are supplied on punched paper tape in bootstrap and absolute binary formats. Paragraph
4.8.1.3 explains how the Absolute Loader is loaded over the bootstrap tapes. The absolute binary tapes are position
independent and may be loaded and run anywhere in memory as explained in Paragraph 4.8.2.2. DUMPIT and
DUMPAB are very similar in function; they differ primarily in the type of output they produce.
4.8.3.1 Operating Procedures - Neither dump program will punch leader or trailer tape, but DUMPAB will always
punch ten blank frames of tape at the start of each block of data dumped.
The operating procedures for both dump programs follow:
1.

Select the dump program desired and place it in the reader specified by location XX7776 (Paragraph
4.8.l ).

If a bootstrap tape is selected, load it using the Bootstrap Loader (Paragraph 4.8.l.2). When the
computer halts, go to Step 4.

If an absolute binary tape is selected, load it using the Absolute Loader (Paragraph 4.8.2.2), relocating as

desired.
Place the proper start address in the Switch Register, press LOAD ADRS and START switches. (The
start addresses are shown in Paragraph 4.8.3.3.)
4.

When the computer halts, enter the address of the desired output device status register in the Switch
Register and press CaNT switch (low speed punch and teleprinter = 177564; high speed punch =
177554; line printer = 177514).

When the computer halts, enter in the Switch Register the address of the first byte to be dumped and
press CaNT switch. This address must be even when using DUMPIT.

When the computer halts again, enter in the Switch Register the address of the last byte to be dumped
and press CaNT switch. When using the low speed punch, set the punch to ON before pressing CaNT
switch.

Dumping will now proceed on the selected output device.

When dumping is complete, the computer will halt.

If further dumping is desired, proceed to Step 5. It is not necessary to respecify the output device address except
when changing to another output device. In such a case, proceed to the second paragraph of Step 3 to restart.

If DUMPAB is being used, a transfer block must be generated as described below. If a tape read by the Absolute
Loader does not have a transfer block, the loader will wait in an input loop. In such a case, the program may be
4-12

manually initiated, however, this practice is not recommended because there is no guarantee that load errors will not
occur when the end of the tape is read.
The transfer block is generated by performing Step 5 with the transfer address in the Switch Register, and Step 6
with the transfer address minus 1 in the Switch Register. If the tape is not to be self-starting, an odd-numbered
address must be specified in Step 5 (e.g., 000001).
The dump programs use all eight general registers and do not restore their original contents. Therefore, after a dump,
the general registers should be loaded as necessary prior to their use by subsequent programs.

4.8.3.2 Output Fonnats - The octal output from DUMPIT is in the following format:

xxxxxx>yyyyyy yyyyyy yyyyyy yyyyyy yyyyyy yyyyyy
Where XXXXXX is the address of the first location printed or punched, and yyyyyy are words of data, the first of
which starts at location XXXXXX. This is the format for every line of output. There are only eight words of data
per line, but there can be as many lines as needed to complete the dump.
The output from DUMPAB is in absolute binary.
4.8.3.3 Storage Maps - The DUMPIT program is 87 words long. When used in absolute format, the storage map is
as shown in Figure 4-4.

XX7776
Bootstrap Loader

XX7744
Absolute Loader

XX7500
XX7474

Loader Stack Space

XXXXXX+256
DUMPIT
XXXXXX

Two-word Stack Space
XXXXXX= desired load address = start address
Figure 4-4 Absolute Format

4-13

When used in bootstrap format, the storage map is as shown in Figure 4-5.

XX7776
Bootstrap Loader
XX7744

DUMPIT
start
address

= XX7440
XX7473
Two-word Stack Space

Figure 4-5 Bootstrap Format

4-14

PART 2
KDII-B PROCESSOR
Part 2 provides both general and detailed descriptions of the KDII-B processor and its
console, a description of the PDP-II instruction set, a description of the KDII-B
microprogram, and maintenance information. The chapters in Part 2 are:
Chapter 5 - Processor General Description
Chapter 6 - Instruction Set
Chapter 7 - Console Description
Chapter 8 - KD Il-B Detailed Description
Chapter 9 - Microprogram Control
Chapter 10 - KDII-B and Console Maintenance
The general description of the KDII-B consists of 'defining the processor and
illustrating its use with peripherals and the Unibus. The KD Il-B processor print set
found in the Engineering Drawing Manual is often referenced in the KDII-B logic
description.

CHAPTER 5
PROCESSOR GENERAL DESCRIPTION

5.1 INTRODUCTION
This chapter provides a brief definition of the KD lI-B processor. It also lists the logic prints that are referenced in
subsequent paragraphs and explains the symbology and notations used in these prints. A sample ROM map listing is
included.
5.2 KDII-B DEFINITION
The KD1I-B is a program compatible with the KAII used in the PDP-II/IS and PDP-1I/20, although the KD11-B
executes instructions somewhat more slowly. The instruction set of the KD11-B is described in detail in Chapter 6,
along with some slight differences between the KD11-B and the KAll (PDP-11/20).
PhYSically the KDlI-B consists of two 8-1/2 by 15 inch modules, the M7260 and M7261. Each module contains
approximately 100 dual in-line integrated circuits of the 14-, 16-, and 24-pin variety. There is one MOS-LSI 40-pin
integrated circuit used on the M7260. This MOS circuit is the serial communication line (SCL) receiver and
transmitter. All other integrated circuits used on the KD11-B are bipolar. The connections between the two modules
are made through the backplane.
The KDlI-B programmer's console interfaces to the processor via a 40-conductor cable that is attached to the
M7260 module. The console is described in detail in Chapter 7.
5.3 KDll-B AND THE UNIBUS
The processor is interfaced with memory and most peripherals by the Unibus as shown in Figure 5-1. The KDI1-B is
capable of arbitrating bus requests (BR) and non-processor requests (NPR) as they are asserted onto the Unibus by
the connected peripherals.
The line clock and the serial communications line (SCL) do not interface with the processor via the Unibus in the
traditional PDP-II sense; both connect to the KD11-B through an internal bus. For most programs, these peripherals
are indistinguishable from their appearance on other PDP-II implementations. In other words, the program may
access the line clock and the serial communications line by using instructions that move data to and from the Unibus
address speCified for these peripheral options in the PDP-ll Peripherals and Interfacing Handbook. These Unibus
addresses are as follows:
a.
b.
c.
d.
e.

Line Clock Status Register Address = 177546
SCL Receiver Status Register Address = 177560
SeL Receiver Buffer Register Address = 177562
SCL Transmitter Status Register Address = 177564
SCL Transmitter Buffer Register Address = 177566

5-1

.-----1

KDll-B
PROCESSOR t----;..;...;..;;;.;..;,;.;.;.;.;;:.....:;;.:;..::..----,/

MEMORY

U
PERIPHERAL
(ANALOGI
DIGITAL
CONVERTER)

PERIPHERAL
(DISK)

1-_-,

I----J

11-1199

Figure 5-1 KDll-B With Interconnections to Memory and Peripherals

It is not possible for the line clock and SCL to be addressed by any devices attached to the Unibus other than the
KD ll-B processor. For example, it is not possible to perform NPRs to the SCL from another peripheral such as the
DECtape unit.

The SCL input/output is available for connection to such devices as the LA30 DECwriter, the VT05 CRT Terminal,
or the Model 33 ASR Teletype. These SCL input/output signals interface at the fingers of the processor's M7260
module via a Berg connector located on the rear of the computer chassis as shown in Chapter 3.
5.4 KDll-B AS AN INSTRUCTION INTERPRETER
Figure 5-2 illustrates the division of the KD1I-B into Unibus control and instruction interpreter. This division is
significant because in the KDlI-B the Unibus control is implemented as a block of logic that is relatively
independent of the rest of the processor.

INSTRUCTION
INTERPRETER

UNIBUS
CONTROL

11-1210

Figure 5-2 KD1I-B Processor Block Diagram
5-2

In Figure 5-3, the instruction interpreter is further divided into a data path (DP), a data path control (DPC), and a
control store (CS). Whenever power is .applied to the computer, the DPC continually executes a program that is
stored in the es. All instructions, interrupt sequences, and console functions are performed by the DPC when
executing a microprogram contained in the CS. The Unibus control and the DP are facilities used by the DPC in the
course of performing its tasks. The program contained in the CS is referred to as the microprogram.

DATA
PATH

CONTROL
STORE
(CS)

CONTROL
(OPC)

DATA
PATH
( DP)
11-1214

Figure 5-3 Instruction Interpreter Block Diagram

5.5 KD11-B PRINT SET
Throughout the remainder of Part 2, frequent references are made to the drawings in the KD Il-B print set located in
the Engineering Drawing Manual. Each print with its respective engineering drawing number is listed as follows:
a.

The Data Path (M7260): D-CS-M7260-O-Ol (9 sheets, DPA to DPHl)

The Control Module (M7261): D-CS-M726I-O-01 (11 sheets, CONA to CONJ)

The Console: D-CS-5409766-0-l

Microprogram Flow listing: K-MP-KDlI-B-l

Microprogram Symbolic listing: K-MP-KDlI-B-2

Microprogram Binary Listing: K-MP-KDII-B-3

Microprogram Cross Reference Listing: K-MP-KDII-B4

Read-Only Memory Maps (ROM): K-RL-M7260-8, K-RL-M7261-8

For this discussion, the prints are referenced by the deSignations DPA through DPH for the M7260, and CONA
through CONF for the M7261. As a general rule, all small scale integrated circuits are shown as individual logic
equivalent gates or flip-flops, with pin numbers deSignated. Figure 54 shows an example of a positive NAND gate
and a D-type flip-flop.
The E094 contained within the gate (Figure 54) indicates the physical location of the dual in-line integrated circuit
on the appropriate module. Integrated circuit pins are referenced, using the notation E09403. The first three digits
after the E refer to the location of the integrated circuit on the module, and the next two digits are the pin number
on that integrated circuit. The prefix of the output signal, in this case DPF, indicates the print name on which the
gate appears; the prefix of the input signal indicates the print page from which the input signal originates (e.g., DPG,
DPF). The particular gate illustrated in Figure 54 appears on drawing F (D-CS-M7260-0-0l, sheet 7). The gate
appearing on print DPF is physically located on the M7260 module; however, the input signals come from prints
DPG and DPF, and therefore the input signals originate on the M7260 module. Note that signal names with the
prefix CONC might originate on CONC or CONCl. Similarly, signal names with the prefix DPH might originate on
DPH or DPHl.

5-3

-"--i§

DPG CAL SOURCE L _ _
E094
DPF AUX CONTROL H _ _....:2'-1 7400

- - - 3 DPF SOP L

0) 2 Input Positive Nand Gate.

DPE R59 H
10
DPE T BIT (I) H

DPF LOAD IR L

E091
T DEL
7474

OB
09
08

DPE T DE L ( I) H
DPE T DE L (1) L
DPE T DE L (0) L
DPE T DE L (0) H

b) Typical 7474 Flip -Flop
11-1198

Figure 5-4 Typical Small Scale Integrated Circuit Representations

Figure 5-4 depicts a typical 7474 flip-flop which appears on drawing DPE (D-CS-M7260-0-1, sheet 6). Several
important points are shown: the name of the flip-flop (TDEL); the print it appears on (DPE); and its physical
location (E091). Four possible output signal names are available from the two physical outputs of the flip-flop:

Physical Output

Signal Names

DPE TDEL (1)H
DPE TDEL (l)L

DPE TDEL (O)L
DPE TDEL (O)L

To clock a 7474 flip-flop there must be a pulse input of some duration (tp) to the clock pin. The clock signal for the
7474 flip-flop is shown in Figure 5-5. Note that the signal DPF LOAD IR L is a negative-going pulse. Since the 7474
flip-flop is clocked on the rising edge of a signal, the flip-flop T DEL is clocked on the trailing edge of DPF LOAD
IR L.

+3V-----....,

L.-_ _ _

FLIP-FLOP ALTERED ON
TRAILI NG EDGE OF SIGNAL.

I-- tp---j
11-1201

Figure 5-5 DPF LOAD IR L Signal

5-4

5.5.1 Medium and Large Scale Integrated Circuit Representations
MSI and LSI integrated circuits (Figure 5-6) are represented in the KDII-B print set as rectangles with inputs on the
left and outputs on the right. Control lines often enter the IC from the bottom. The functional descriptions of the
KDII-B MSI and LSI ICs are contained in Appendix A.

CONTROL OUTPUTS

74181

ALU

INPUTS

OUTPUTS

E18

Cin

CONTROL IN PUTS
11- 1197

Figure 5-6 ALU, MSI Circuit Type 74181 Representation

5.5.2 Microprogram Documentation
The microprogram is documented at three levels in the print set. The first level is the microprogram flow listing
(K-MP-KDN-B-l), at this level, the microprogram is described in terms of register transfers. The microprogram
symbolic listing (K-MP-KD11-B-2) shows how the microprogram accomplishes each step. (References in the
microprogram listing are symbolic; e.g., scratch pad address = R7.) The binary equivalent is shown in the
microprogram binary listing (K-MP-KDII-B-3), which actually shows the binary contents of each word of the
microprogram. The microprogram cross reference listing lists the microprogram by address (K-MP-KDII-B-4). The
microprogram is discussed in detail in Chapter 9.

5.5.3 Read-Only Memory (ROM) Maps
Figure 5-7 is a typical ROM map listing. ROM map listings for the ROMs used in the KDII-B processor are provided
in the Engineering Drawing Manual (K-RL-M7260-8 and K-RL-M7261-8).

5-5

II =y8

OCTAl. DECIMAL
ADDRESS ADORESS
"~0

121

001

liH'J2

003

~~4

005

5
6

006

0"17

010

011
012

013
014

015
"'16
017
1212e
021
022

1
8
9

H!
11
12
13
14
15
16
17
18

EOC8 A
00000
00001

'-'112)01"
C!leH?J11
C!let10"
012)101
0011 0

"'0111
0100 0
010131
eJ1010
e!1011
01U"
QJl101

0111fc:?

"1111
10el00

1(212101
lel01"

2123

024

20
21

au"

all~

025
026
021
0:50

23
24

033

25
26
27

12134

0:55

29
3121
31

031
12132

036
031

1 liH?J11

1011211

10111
1100"
11e101
1101 0

11e111
11113 0
11101

1111"
11111

(~lN '9)
(~IN .7)

CONA INT TRAN SYNC L
CONA REG ADDR L
"/( =Y6 (PIN #6) CONA RECEIVE L
"'It =y5 (PIN #5) CON A TRANSMIT L
"',/( aY4 (PIN #4) eDNA LOAO MODEM PSW L
""'/( .y3 (PIN #3) eONA LOAD L eLK PSW L
" " " / ( aY2 (PIN #2) CONG SP WRITE L
"""'/C =Y1 (PIN #1) CONG LOAD PSW L
"."",
OCTAL
.""".
DATA
11111111
377
11111111
377
11111111
377
11111111
377
01111110
176 PSW ,TRAN OUT 9A ' 177776
11111111
377 PSW ,TRAN OUT,BAR
01111011
173 I.CLK ,HUNOUT
11111111
377 I.CLK ,TRANOUT.B4R
0121111101
12175 GR .TRANOUT BA I 1771XX
113111111
277 GR ,TRANOUT,8AR
01111111
177 ODD BYTE (I,.CI.K/rK/TP)
11111111
377
11111111
377
11111111
377
ell111111
177 SWR ,TRANOUT 8A'17157~
11111111
377 SWR ,TRANOUT.8AR
01~10111
127 TKS ,TRANOUT 8A_1715613
11~11111
337 TKS ,TRANOUT,8AR
0111210111
147 TPS ,TRANOUT 8A=177564
11101111
357 TPS ,TRANOUT.BAR
01~11111
137 TK8 ,TRANOUT 8A_177562
11~11111
337 TKB .TRANOUT.BAR
0111211111
157 TPB ,TRANOUT 8AI177566
11101111
357 TPB .TRANOUT.8AR
11111111
377
11111111
377
11111111
377
11111111
377
11111111
377
11111111
377
11111111
377
11111111
377

.Ic .Y?

, f , , ,

.",/( A(PIN #10) IS eDNA TRAN OUT L
f,'/C B(pI~ #11) IS V3 OF F025
',/(-C(P!N #12) IS V2 OF F02?
'/( D(PIN #13) IS Vl OF F025
I( E~PIN #14) IS Y4 OF F025
Figure 5-7 E068 ROM Map Example

5-6

CHAPTER 6
INSTRUCTION SET

6.1 INTRODUCTION
The KD lI-B is defined by its instruction set. The sequences of processor operations are selected according to the
instruction decoding. This chapter contains tables that describe the PDP-II instructions and instruction set
addressing modes. Instruction set differences between the PDP-II/OS, 11/10 and PDP-II /20 are listed in Table 6-8.
6.2 ADDRESSING MODES
6.2.1 Introduction
Data stored in memory must be accessed and manipulated. Data handling is specified by a PDP-II instruction (MOV,
ADD, etc.) which usually indicates:
a.

The function (operation code).

A general purpose register for locating the source operand and/or a general purpose register for locating
the destination operand.

An addressing mode [to specify how the selected register(s) is to be used].

A large portion of the data handled by a computer is usually structured in character strings, arrays, lists, etc. Thus,
the PDP-II is designed to handle structured data effiCiently and flexibly. The general registers may be used with an
instruction in any of the following ways:
a.

As accumulators. The data to be manipulated resides within the register.

As pointers. The contents of the register are the address of the operand, rather than the operand itself.

As pointers that automatically step through core locations. Automatically stepping forward through
consecutive core locations is termed autoincrement addreSSing; automatically stepping backwards is
termed autodecrement addreSSing. These modes are particularly useful for processing tabular data.

As index registers. In this instance, the contents of the register and the word following the instruction
are summed to produce the address of the operand. This allows easy access to variable entries in a list.

PDP-lIs also have instruction addressing mode combinations that facilitate temporary data storage structures for
convenient handling of data that must be frequently accessed. This is known as the "stack".

6-1

In the PDP-ll any register can be used as a stack pointer under program control; however, certain instructions
associated with subroutine linkage and interrupt service automatically use register 6 as a hardware stack pointer. For
this reason, R6 is frequently referred to as the SP.
Two types of instructions utilize the addressing modes: single operand and double operand. Figure 6-1 shows the
formats of these two types of instructions. The addressing modes are listed in Table 6-1.
6.2.2 Instruction Timing
The PDP· 11 is an asynchronous processor in which, in many cases, memory and processor operations are overlapped.
The execution time for an instruction is the sum of a basic instruction time and the time to determine and fetch the
source and/or destination operands. Table 6-2 shows the addressing times required for the various modes of
addressing source and destination operands. All times stated are subject to ±IO% variation.

***
Rn

'--1_5__________________~r_-------------------6~A
-

T
OP CODE

t
DESTINATION ADDRESS FIELD

* =SPECIFIES DIRECT OR INDIRECT ADDRESS
*,,=SPECIFIES HOW REGISTER WILL BE USED
ONE OF 8 GENERAL PURPOSE REGISTERS

_It = SPECIFIES

(a)

~P COD~
15

_It

MO~E

(Q)

T
SOURCE ADDRESS FIELD

DESTINATION ADDRESS FIELD

,,= DIRECTIDEFERRED BIT FOR SOURCE AND DESTINATION ADDRESS
""= SPECIFIES HOW SELECTEO REGISTERS ARE TO BE USED
*** = SPECIFIES A GENERAL REGISTER

(b)
11-1227

Figure 6-1 Addressing Mode Instruction Formats

6.3 PDP-II/OS INSTRUCTIONS
The PDP-II instructions can be divided into five groupings:
a.
b.
c.
d.
e.

Single Operand Instructions (shifts, multiple precision instructions, rotates)
Double Operand Instructions (arithmetic and logical instructions)
Program Control Instructions (branches, subroutines, traps)
Operate Group Instructions (processor control operations)
Condition Codes Operators (processor status word bit instructions)

Tables 6-3 through 6-7 list each instruction, including byte instructions for the respective instruction groups. Figure
6-2 shows the six different instruction formats of the instruction set, and the individual instructions in each format.

6.4 INSTRUCTION SET DIFFERENCES
Table 6-8 lists the differences between the PDP-I 1/20 and PDP-II/OS instruction sets.

6·2

Table 6-1
Addressing Modes
Binary
Code

Name

Assembler
Syntax

Function
DIRECT MODES

000

010

Autoincrement

(Rn) +

100

Autodecrement

-(Rn)

110

Index

X(Rn)

Value X (stored in a word following the instruction) is added
to (Rn) to produce address of operand. Neither X nor (Rn)
are modified.
DEFERRED MODES

001

@Rn
or (Rn)

all

Autoincrement
Deferred

@(Rn)+

Register is first used as a pointer to a word containing the
address of the operand, then incremented (always by two;
even for byte instructions).

101

Au todecremen t

@-(Rn)

Register is decremented (always by two; even for byte instructions) and then used as a pointer to a word containing
the address of the operand.

111

Index Deferred

@X(Rn)

Value X (stored in a word following the instruction) and (Rn)
are added and the sum is used as a pointer to a word containing the address of the operand. Neither X nor (Rn) are
modified.
PC ADDRESSING

010

Immediate

Operand follows instruction.

all

Absolute

@#A

Absolute address follows instruction.

110

Relative

Address of A, relative to the instruction, follows the instruction.

111

Relative Deferred

Address of location containing address of A, relative to the
instruction, follows the instruction.

Rn = Register
X, n, A = next program counter (PC) word (constant)

6-3

Table 6-2
Addressing Times
Time (ps)

Addressing Format
Mode

Description

Symbolic

Source *

Destination**

@Ror(R)

0.9

2.4

Au toincrement

(R) +

0.9

2.4

Autoincrement
Deferred

@(R)+

2.4

3.4

Autodecrement

- (R)

0.9

2.4

Autodecrement
Deferred

@- (R)

2.4

3.4

Indexed

±X(R)

2.4

3.4

Index Deferred

@±X(R)
or @(R)

3.4

4.7

*
**

For Source time, add 1.3 J.l.S for odd byte addressing.
For destination time, modify as follows:

a. Add 1.3 J.l.S for odd byte addressing with a non-modifying
instruction.
b. Add 2.4 J.l.S for odd byte addressing with a modify~ng
instruction.
c. Subtract 1.2 J.l.S for a non-modifYing instruction.

6-4

Table 6-3
Single Operand Instructions
Mnemonic/
Instruction Time

0'-

OP Code

Description

Condition Codes

Operation

CLR
CLRB
3.4 .us

0050DD*
1050DD

(dst)t ..- 0

N:
Z:
V:
C:

Contents of specified destination are replaced with zeroes.

COM
COMB
3.4 .us

005IDD
105IDD

(dst)..- n (dst)

N: set if most significant
bit of result is 0
Z: set if result is 0
V: cleared
C: set

Replaces the contents of the destination address by their
logical complement (each bit equal to 0 set and each bit equal
to 1 cleared).

INC
INCB
3.4 .us

0052DD
1052DD

(dst)..- (dst) + 1

N:
Z:
V:
C:

set if result is less than 0
set if result is 0
set if (dst) was 077777
not effected

Add 1 to the contents of the destination.

DEC
DECB
3.4 .us

0053DD
1053DD

(dst)..- (dst)-1

N:
Z:
V:
C:

set if result is less than 0
set if result is 0
set if (dst) was 100000
not effected

Subtract 1 from the contents of the destination.

NEG
NEGB
3.4 .us

0054DD
1054DD

(dst)..- -(dst)

N:
Z:
V:
C:

set if result is less than
set if result is a
set if result is 100000
cleared if result is a

ADC
ADCB
3.4 .us

0055DD
1055DD

(dst)..- (dst) + C

N: set if result is less than a
Z: set if result is a
V: set if (dst) is 077777 and
C is 1
C: set if (dst) is 177777 and
Cis 1

cleared
set
cleared
cleared

Replaces the contents of the destination address by its 2's com
plement. Note that 100000 is replaced by itself.

Adds the contents of the C-bit into the destination. This permi ts
the carry from the addition of the low order words/bytes to bE
carried into the high order result.

Table 6-3 (Cont)
Single Operand Instructions
Mnemonic!
Instruction Time

OPCode

Condition Codes

Operation

Description

N:
Z:
V:
C:

set if result is less than 0
set if result is 0
set if (dst) was 100000
cleared if (dst) is 0 and C
is 1

Subtracts the contents of the C-bit from the destination. This
permits the carry from the subtraction of the low order wordsl
bytes to be subtracted from the high order part of the result.

N:
Z:
V:
C:

set if result is less than 0
set if result is 0
cleared
cleared

Sets the condition codes Nand Z according to the contents of
the destination address.

SBC
SBCB
3.41-1s

0056DD
1056DD

(dst) ~ (dst) -C

TST
TSTB
3.41-1s

0057DD
1057DD

(dst)

ROR
RORB
3.41-1s

0060DD

(dst) ~ (dst)
rotate right
one place.

N: set if high order bit of
the result is set
Z: set if all bits of result
are 0
V: loaded with the exclusiveOR of the N-bit and the
C-bit as set by ROR

Rotates all bits of the destination right one place. The low
order bit is loaded into the C-bit and the previous contents of
the C-bit are loaded into the high order bit of the destination.

ROL
ROLB
3.4l-1s

006IDD
106IDD

(dst) ~ (dst)
rotate left
one place.

N: set if the high order bit of
the result word is set
(result < 0); cleared
otherwise
Z: set if all bits of the
result word = 0; cleared
otherwise
V: loaded with the exclusiveOR of the N-bit and C-bit
(as set by the completion
of the rotate operation)
C: loaded with the high order
bit of the destination

Rotate all bits of the destination left one place. The high
order bit is loaded into the C-bit of the status word and the
previous contents of the C-bit are loaded into the low order
bit of the destination.

(dst)

Table 6-3 (Cont)
Single Operand Instructions
Mnemonic/
Instruction Time

OP Code

Operation

Condition Codes

ASR
ASRB
3.4 ps

0062DD
1062DD

(dst) +- (dst)
shifted one
place to the
right.

N: set if the high order bit
of the result is set
(result < 0); cleared
otherwise
Z: set if the result = 0;
cleared otherwise
V: loaded from the exclusiveOR of the N-bit and C-bit
(as set by the completion
of the shift operation).
C: loaded from low order bit
of the destination

ASL
ASLB
3.4 ps

0063DD
lO63DD

(dst) +- (dst)
shifted one
place to the left.

N: set if high order bit of the
(result < 0); cleared

Description

Shifts all bits of the destination right one place. The high
order bit is replicated. The C-bit is loaded from the low order
bit of the destination. ASR performs signed division of the
destination by two.

Shifts all bits of the destination left one place. The low order
bit is loaded with a O. The C-bit of the status word is loaded
otherwi~e
from the high order bit of the destination. ASL performs a
Z: set if the result = 0; cleared signed multiplication of the destination by 2 with overflow
otherwise
indication.
V: loaded with the exclusiveOR of the N-bit and C-bit
and C-bit (as set by the
completion of the shift
operation)
C: loaded with the high order
bit of the destination

- - -----------

Table 6-3 (Cont)
Single Operand Instructions
Mnemonic/
Instruction Time

OPCode

Operation

JMP
1.0 p.s

000100

SWAB
4.3 p.s

0003DD

Byte I/Byte 0
Byte O/Byte 1

(dst)

Condition Codes

Description

Not effected.

JMP provides more flexible program branching than provided
with the branch instruction. Control may be transferred to any
location in memory (no range limitation) and can be accomplished with the full flexibility of the addressing modes, with
the exception of register mode O. Execution of a jump with
mode 0 will cause an illegal instruction condition. (Program
control cannot be transferred to a register.) Register deferred
mode is legal and will cause program control to be transferred
to the address held in the specified register. Note that instructions are word data and must therefore be fetched from
an even numbered address. A boundary error trap condition
will result when the processor attempts to fetch an instruction
from an odd address.

N: set if high order bit of
low order byte (bit 7)
of result is set, cl eared
otherwise
Z: set if low order byte
of result = 0; cleared
otherwise
V: cleared
C; cleared

Exchanges high order byte and low order byte of the destinatio n
word (destination must be a word address).

DD = destination (address mode and register)

t (dst) = destination contents

Table 6-4
Double Operand Instructions
Mnemonic/
Instruction Time

OP Code

MOV
MOVB

01SSDD*
11SSDD

02SSDD
12SSDD

Operation

Condition Codes

Description

(dst) +- (src) t

N: set if (src) < 0; cleared
otherwise
Z: set if (src) = 0; cleared
otherwise
V: cleared
C: not effected

Word: Moves the source operand to the destination location.
The previous contents of the destination are lost. The source
operand is not effected.
Byte: Same as MOV The MOVB to a resistor (unique among
byte instructions) extends the most significant bit of the low
order byte (sign extension). Otherwise MOVB operates on
bytes exactly as MOV operates on words.

(src) - (dst)
[in detail,
(src) + ~
(dst) + 1]

N: set if result < 0; cleared
otherwise
Z: set if result = 0; cleared
otherwise
V: set if there was arithmetic
overflow, i.e., operands
were of opposite signs
and the sign of the destination was the same
as the sign of the result;
cleared otherwise
C: cleared if there was a
carry from the most significant bit of the result;
set otherwise

Compares the source and destination operands and sets the
condition codes, which may then be used for arithmetic and
logical conditional branches. Both operands are uneffected.
The only action is to set the condition codes. The compare is
customarily followed by a conditional branch instruction. Note
that unlike the subtract instruction the order of operation is
(src) - (dst), not (dst) - (src).

3.711s
3.111s mode 0

CMP
CMPB
3.711s
0-

-b

-----

Table 64 (Cont)
Double Operand Instructions
Mnemonic/
Instruction Time

OP Code

Operation

Condition Codes

Description

BIT
BITB
3.7 J.J.s

03SSDD
13SSDD

(src) 1\ (dst)

N: set if high order bit of
result set; cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C: not effected

Performs logical AND comparison of the source and destinatic n
operands and modifies condition codes accordingly. Neither
the source nor destination operands are effected. The BIT instruction may be used to test whether any of the correspondin g
bits that are set in the destination are clear in the source.

BIC
BICB
3.7 J.J.s

04SSDD
14SSDD

(dst) ~ ~ (src)
1\ (dst)

N: set if high order bit of
result set, cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C; not effected

Clears each bit in the destination that corresponds to a set bit
in the source. The original contents of the destination are lost.
The contents of the source are uneffected.

BIS
BISB
3.7 J.J.s

OSSSDD
lSSSDD

(dst) ~ (src)
1\ (dst)

N: set if high order bit of
result set; cleared otherwise
Z: set if result = 0; cleared
otherwise
V: cleared
C: not effected

Performs inclusive-OR operation between the source and destination operands and leaves the result at the destination
address; i.e., corresponding bits set in the destination. The
contents of the destination are lost.

ADD

06SSDD

(dst) ~ (src)
+ (dst)

N: set if result 0; cleared
otherwise
Z: set if result = 0; cleared
otherwise

Adds the source operand to the destination operand and stores
the result at the destination address. The original contents of
the destination are lost. The contents of the source are not
effected. Two's complement addition is performed.

'?'
o

-----------

Table 6-4 (Cont)
Double Operand Instructions
Mnemonic/
Instruction Time

OP Code

Operation

ADD (Cont)

Condition Codes

Description

V: set if there was arithmetic
overflow as a result of the
operation; that is both
operands were of the same
sign and the result was of
the opposite sign; cl eared
otherwise
C: set if there was a carry from
the most significant bit of
the result, cleared otherwise

9'
.-

SUB
3.7 ps

16SSDD

----_.

= source (address mode and register)

t (src) = source contents

N: set if result < 0; cleared
otherwise
Z: set if result = 0; cleared
otherwise
V: set if there was arithmetic
overflow as a result of
the operation, i.e., if
operands were of opposite signs and the sign
of the source was the
same as the sign of the
result, cleared otherwise
C: cleared if there was a
carry from the most
significant bit of the
result; set otherwise

(dst) +-- (dst)(src) in detail,
(dst) + - (src)
+ 1 (dst)

... _-_.-

Subtracts the source operand from the destination operand and
leaves the result at the destination address. The original contents
of the destination are lost. The contents of the source are not
effected. In double precision arithmetic, the C-bit, when set,
indicates a borrow.

Table 6-5
Program Control Instructions
Mnemonic/
Instruction Time

OP Code

BR
2.5 J.1s

000400
xxxt

BNE
1.9 J.1S no branch
2.5 J.1S branch

001000
xxx

BEQ
1 .9 J.1S no branch
2.5 J.1S branch

001400
xxx

BGE
1.9 fJ.S no branch
2.5 fJ.S branch

002000
xxx

Operation

Condition Codes

Description

PC ~PC +
(2 X offset)

Uneffected

Provides a way of transferring program control within a range
of -128 to +127 words with a one word instruction. It is an
unconditional branch.

PC~PC+

Uneffected

Tests the state of the Z-bit and causes a branch if the Z-bit is
is clear. BNE is the complementary operation to BEQ. It is
used to test inequality following a CMP, to test that some bits
set in the destination were also in the source, following a BIT,
and generally, to test that the result of the previous operation
was not o.

PC+-PC+
(2 X offset) if
Z=l

Uneffected

Tests the state of the Z-bit and causes a branch if Z is set. As
an example, it is used to test equality following a CMP operation, to test that no bits set in the destination were also set in
the source following a BIT operation, and generally, to test
that the result of the previous operation was o.

PC~PC+

Uneffected

Causes a branch if N and V are either both clear or both set.
BGE is the complementary operation to BLT. Thus, BGE
always causes a branch when it follows an operation that
caused addition to two positive numbers. BGE also causes a
branch on a 0 result.

(2 X offset)
ifZ = 0

(2 X offset) if
NvV=O

Table 6-5 (Cont)
Program Control Instructions
Mnemonic!
Instruction Time
BLT
1.9 I1S no branch
2.5 I1S branch

Cf'

BGT
1.911s no branch
2.5 I1S branch

OP Code

Operation

Condition Codes

Description

002400
xxx

PC+-PC+
(2 X offset) if
NV::: 1

Uneffected

Causes a branch if the exclusive-OR of the N- and V-bits are 1.
Thus, BLT always branches following an operation that added
two negative numbers, even if overflow occurred. In particular,
BLT always causes a branch if it follows a CMP instruction
operating on a negative source and a positive destination (even
if overflow occurred). Further, BLT never causes a branch when
it follows a CMP instruction operating on a positive source and
negative destination. BLT does not cause a branch if the result
of the previous operation was 0 (without overflow).

003000

PC+-PC+
(2 X offset)
ifZv(N¥
V)::: 0

Uneffected

Operation of BGT is similar to BGE, except BGT does not
cause a branch on a 0 result.

xxx

BLE
1.9 I1S no branch
2.5 I1S branch

003400
xxx

PC+-PC+
(2 X offset) if
Z v (NVV)
::: 1

Uneffected

Operation is similar to BLT but in addition will cause a branch
if the result of the previous operation was O.

BPL
1.9 I1S no branch
2.5 I1S branch

100000
xxx

PC+-PC+
(2 X offset) if
N:::O

Uneffected

Tests the state of the N-bit and causes a branch if N is clear.
BPL is the complementary operation of BMI.

100400

PC +- PC +
(2 X offset) if
N:::l

Uneffected

Tests the state of the N-bit and causes a branch if N is set. It is
used to test the sign (most significant bit) of the result of the
previous operation.

BMI
1.9 I1S no branch
2.5 I1S branch

xxx

Table 6-5 (Cont)
Program Control Instructions
I

Mnemonic/
Instruction Time

'?'

"'"

OP Code

Operation

Condition Codes

Description

BHI
1.9 p.s no branch
2.5 p.s branch

101000
xxx

PC ~PC +
(2 X offset) if
C=O

Uneffected

Causes a branch if the previous operation causes neither a carry
nor a 0 result. This will happen in comparison (CMP) operations
as long as the source has a higher unsigned value than the
destination.

BLOS
1.9 p.s no branch
2.5 p.s branch

101400
xxx

PC~PC+

Uneffected

Causes a branch if the previous operation caused either a carry
or a 0 result. BLOS is the complementary operation to BHI.
The branch occurs in comparison operations as long as the
source is equal to or has a lower unsigned value than the
destination. Comparison of unsigned values with the CMP
instruction to be tested for "higher or same" and "higher" by
a simple test of the C-bit.

BVC
1.9 p.s no branch
2.5 p.s branch

102000
xxx

PC~PC+

Uneffected

Tests the state of the V -bit and causes a branch if the V -bit is
clear. BVC is complementary operation to BVS.

BVS
1.9 J,ls no branch
2.5 J,lS branch

102400
xxx

Uneffected

Tests the state of V -bit (overflow) and causes a branch if the
V-bit is set. BVS is used to detect arithmetic overflow in the
previous operation.

BCC
BHlS
1.9 J,lS no branch
2.5 J,ls branch

103000
xxx

Uneffected

Tests the state of the C-bit and causes a branch if C is clear.
BCC is the complementary operation to BCS.

BCS
BLO
1 .9 J,lS no branch
2.5 J,ls branch

103400
xxx

Uneffected

Tests the state of the C-bit and causes a branch if C is set. It is
used to test for a carry in the result of a previous operation.

---

(2 X offset) if
CvZ=1

(2 X offset) if
V=O
PC~PC+

(2 X offset) if
V=1
PC~PC+

(2 X offset) if
C=O

PC~PC+

(2 X offset) if
C=1

Table 6-5 (Cont)
Program Control Instruction
Mnemonic/
Instruction Time
JRS
3.8,us

OP Code

Operation

004RDD

(tmp) +- (dst)
(tmp is an internal processor
register)
-I- (SP) +- reg
(push reg contents onto processor stack)
reg +- PC PC
holds location following JSR; this
address PC +(tmp), now put In
(reg)

'1'
......
VI

Condition Codes
Uneffected

Description
In execution of the JSR, the old contents of the specified
register (the linkage pOinter) are automatically pushed onto
the processor stack and new linkage information placed in
the register. Thus, subroutines nested within subroutines to any
depth may all be called with the same linkage register. There
is no need either to plan the maximum depth at which any
particular subroutine will be called or to include instructions
in each routine to save and restore the linkage pointer. Further,
since all linkages are saved in a re-entrant manner on the processor stack. execution of a subroutine may be interrupted,
and the same subroutine re-entered and executed by an interrupt service routine. Execution of the initial subroutine can
then be resumed when other requests are satisfied. This process (called nesting) can proceed to any level.
JSR PC, dst is a special case of the PDP-II subroutine call
suitable for subroutine calls that transmit parameters.

RTS
3.8 tlS

0OO20R

PC +- (reg)
(reg) +- SP t

Uneffected

Loads contents of register into PC and pops the top element
of the processor stack into the specified register.
Return from a non-re-entrant subroutine is typically made
through the same register that was used in its call. Thus, a
subroutine called with a JSR PC, dst exits with an RTS PC,
and a subroutine called with a JSR RS, dst may pick up
parameters with addressing modes (RS) +, X (RS), or @X (RS)
and finally exit, with an RTS RS.

Table 6-5 (Cont)
Program Control Instructions
Mnemonic/
Instruction Time

OPCode

Operation

Condition Codes

Description

(No mnemonic)
8.2 J.1s

000003

J- (SP) +- PS
J-,(SP) +- PC
PC +- (14)
PS +- (16)

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Performs a trap sequence with a trap vector address of 14. Used
to call debugging aids. The user is cautioned against employing
code 000003 in programs run under these debugging aids.

lOT
8.2 J.1S

000004

t (SP) +- PS
J- (SP) +- PC
PC +- (20)
PS +- (22)

N: loaded from trap vector
Z: loaded from trap vector
C: loaded from trap vector

Performs a trap sequence with a trap vector address of 20. Used
to call the I/O executive routine lOX in the paper-tape software
system, and for error reporting in the disk operating system.

EMT

104000

t (SP) +- PS
t (SP) +- PC

N:
Z:
V:
C:

All operation codes from 104000 to 104377 are EMT instructions and may be used to transmit information to the emulating
routine (e.g., function to be performed). The trap vector for
EMT is at address 30; the new central processor status (PS) is
taken from the word at address 32.

8.2 J.1s

PC +- (30)
PS +- (32)

?'
......
0\

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

CAUTION
EMT is used frequently by DEC system software and
is therefore not recommended for general use.
TRAP
8.2 J.1S

104400 to
104777

t
t

(SP) +- PS
(SP) +- PC
PC +- (34)
PS +- (36)

N:
Z:
V:
C:

loaded from trap vector
loaded from trap vector
loaded from trap vector
loaded from trap vector

Operation codes from 104400 to 104777 are TRAP instructions
TRAPs and EMTs are identical in operation, except that the
trap vector for TRAP is at address 34.
NOTE
Since DEC software makes frequent use of EMT, the
TRAP instruction is recommended for general use.

NOTE: Condition Codes are uneffected by these instructions
txxx = offset, 8 bits (0-7) of instruction format
R ='register (linkage pointer)

Table 6-6
Operate Group Instructions
Mnemonic/
Instruction Time

OPCode

Condition Codes

Operation

Description

HALT
1.81J.s

000000

Not effected

Causes the processor operation to cease. The console is given
control of the processor. The console data lights display the
address of the HALT instruction plus two. Transfers on the
Unibus are terminated immediately. The PC points to the next
instruction to be executed. Pressing the CON key on the console
causes processor operation to resume. No INIT signal is given.

WAIT
1.81J.s

000001

Not effected

Provides a way for the processor to relinquish use of the bus
while it waits for an external interrupt. Having been given a
WAIT command, the processor will not compete for bus by
fetching instructions or operands from memory. This permits
higher transfer rates between device and memory, since no
processor induced latencies will be encountered by bus requests from the device. In WAIT, as in all instructions, the PC
points to the next instruction following the WAIT operation.
Thus, when an interrupt causes the PC and PS to be pushed onto
the stack, the address of the next instruction following the
WAIT is saved. The exit from the interrupt routine (i.e., execution of an RTI instruction) will cause resumption of the interrupted process at the instruction following the WAIT.

RTI
4.41J.s

000002

PC (SP)
PSW (SP)

N: loaded from processor stack
Z: loaded from processor stack
V: loaded from processor stack
C: loaded from processor stack

Used to exit from an interrupt or trap service routine. The PC
and PSW are restored (popped) from the processor stack. If a
trace trap is pending, the first instruction after the RTI will be
executed prior to the next T trap.

RESET
20ms

000005

PC (SP)
PSW (SP)

Not effected

Sends INIT on the Unibus for 20 ms. All devices on the Unibus
are reset to their state at power-up.

9'
.....
-...I

--------

------

--_..

---

~~---

-------

---

Table 6-7
Condition Code Operators
Mnemonic/
Instruction Time
CLC
CLZ
CLN
CLV
Set all CCs
Clear all CCs
Clear V and C
No operation
No operation
2.51ls

OP Code

Description

000241
000242
000244
000250
000261
000262
000264
000270
000277
000257
000243
000240
000260

Set and clear condition code bits. Selectable combination of
these bits may be cleared or set together. Condition code bits
corresponding to bits in the condition code operator (bits 0-3)
are modified according to the sense of bit 4, the set/clear bit
of the operator; i.e., set the bit specified by bit 0, 1,2, or 3 if
bit 4 is a 1. Clear corresponding bits if bit 4 = O.

1. Single Operand Group (CLR,CLRB,COM,COMB,INC,1 NCB, DEC,DECB,NEG, NEGB, ADC,ADCB,SBC,SBCB, TST,TSTB, ROR, RORB, ROL ,ROLB.ASR, ASRB,
ASL, ASLB, JMP, SWAB)
OP Code

Dst

2. Double Operand Group( BIT,BITB,BIC,BICB,BIS,BISB,ADD,SUB)
OP Code

Src

dst

I
12

I
6

3.Program Control Group
a. Branch (a II branch instructions)
OP Code

offset

I
15

b.Jump To Subroutine (JSR)
~----------------------~----------~-------------------,

reg

Src/dst

c.Subroutine Return (RTS)

reg

d. Traps (break point, lOT, EMT, TRAP)
OP CODE

4.0perate Groupe (HALT,WAIT,RTI,RESET)
~-------------------------------------------------------,
OP CODE

5.Condition Code Operators (all condition code instructions)

c
11·1226

Figure 6-2 PDP-II Instruction Formats

6-18

Table 6-8
PDP-II Differences
PDP-lI/IS, PDP-I 1/20
OPR %R, (R) +/-(R), source operand is %R after autoincrement/autodecrement of DEST register only when source and destination registers are
the same.

OPR %R, (R) +/- R source operand is %R before autoincrement/autodecrement of DEST register whether source or destination registers are the
same or not.

Example:
12700MOV # 100, RO 100
10020 MOV RO, (RO) + 0 HALT

Example:
12700 MOV #100, RO 100
10020 MOV RO, (RO) + 0 HALT

After Execution:

RO = 102
LOCIOO = 102

'?'
......
\C;

PDP-II/OS, PDP-I 1/10

RO = 102
LOCI00 = 100
(Note that LOClOO is now 100)

OPR %R, @-(R) /@ (R) + uses Rafter autodecrement/autoincrement
as source operand.

OPR %R, @-(R) /@ (R) + uses R before autodecrement/autoincrement as
source operand.

MOV PC, LOC stores PC of INST +4 in LOC.

MOV PC, LOC stores PC of INST +2 in LOC.

SWAB does not change V.

Swab clears V.

Program halt displays PC of halt instruction in ADDRESS lights. DATA
lights display (RO).

Displays next PC.

Byte ops to the odd byte of the PS cause odd address trap.

Byte ops to odd byte of PS do not trap. Not all bits may exist.

The RESET instruction clears the RUN light such that program loops
that make frequent use of RESET may not appear to be running.

RESET does not clear the RUN light.

Power fail during RESET instruction is not recognized until after the
instruction is finished (70 IDS). Too late, so don't use RESET. RESET
instruction consists of 70 ms pause with INIT occurring during first
20 ms.

Power fail immediately ends the RESET instructions and traps if an INIT
is in progress (22 ms). A minimum INIT of 300 ns occurs if the instruction
aborted. Power fail during RESET fetch is fatal: no power-down sequence.

Table 6-8 (Cont)
PDP-II Differences
PDP-lItiS, PDP-lI/20
The first instruction in an interrupt service routine is guaranteed to be
executed.

The first instruction in an interrupt routine will not be executed if another
interrupt occurs at a higher priority level than was assumed by the first
interrupt.

Sequence of internal processor traps, external interrupts, HALT and
WAIT:

Sequences:

BUS ERROR Trap
Odd Address
Data Time Out
HALT Instruction for Console Operation

N
o

PDP-II/OS, PDP-II/IO

TRAP Instructions: Illegal or Reserved Instructions,
TRTT, lOT, EMT, TRAP
TRACE TRAP: T-bit of processor status
OVFL Trap: Stack overflow
PWR FAIL Trap: Power down
CONSOLE BUS REQUEST: Console operation after HALT switch
UNIBUS BUS REQUEST: Peripheral Request, compared with Processor
Priority - usually an interrupt occurs.
WAIT LOOP: Loop on a WAIT instruction in IR until an interrupt allows
exit. A CONSOLE BUS REQUEST returns to this loop after being
honored.

BUS ERROR Traps
HALT Instruction
TRAP Instructions
OVFLTrap
PWR Fail Trap
UNIBUS BUS REQUESTS
CONSOLE STOP
(HALT switch)
WAIT LOOP

CHAPTER 7
CONSOLE DESCRIPTION

7.1 IN1RODUCTION
This chapter provides a general and a detailed description of the console logic. The general description is keyed to
the block diagram level, the detailed description covers the theory of operation of the console logic. The function
and use of the console controls are discussed in Chapter 4.
7.2 GENERAL DESCRIPTION
The console logic is divided into two sections: address/data register logic, and control switch logic. All the console
logic is contained on one printed circuit board, which also contains the switches and indicators.
7.2.1 ADDRESS/DATA Register Logic
During manual console operation, data and addresses are generated by positioning the 16 ADDRESS/DATA Register
switches. The switches are 2-position toggle type: the down position grounds the switch and provides a low signal to
the processor logic; the up position provides a high signal to the processor logic by connecting the switch to +5V.
The ADDRESS/DATA Register logic samples the 16 bits (address or data) from the B-Ieg of the processor data
section and displays them via the ADDRESS/DATA Register indicators (Figure 7-1). The address/data multiplexer
scans the processor 16-bit B-Ieg signals and provides a serialized output to the Buffer Register. The output of the
register consists of 16 signals that are buffered and sent to the 16 ADDRESS/DATA indicators. The buffer has two
modes of operation that are controlled by the SHIFT/HOLD signal from the 16-bit synchronous counter. In the
shift (scan) mode, serialized data from a scan operation is shifted into the register; this operation takes 16 f.lS. At the
end of this time, the register enters the hold (display) mode for 240 f.lS, during which time the register contents are
displayed. This process is continuous and a scan pulse display sequence takes 256 f.lS. The information that is
scanned (multiplexer input) remains stable for a long time compared to the 256-f.ls cycle for the register; therefore,
the multiplexer scans relatively stable information that can be displayed.
In addition to supplying the SHIFT/HOLD signal that controls the buffer register, the counter also generates the
four scan address signals that select the multiplexer inputs.
The clock provides pulses to clock the counter and Buffer Register. It starts when power is applied and is
self-sustaining thereafter.
7.2.2 Control Switch Logic
The six console control switches allow programming functions to be performed manually. They are: load address
(LOAD ADRS), examine (EXAM), continue (CONT), deposit (DEP), START, and HALT/ENABLE. The switches
provide signals to the processor logic, which actually controls the functions.

7-1

A bounce buffer is connected across the output contacts of each switch to eliminate interruptions of the output
signal due to contact bounce when the switch is activated. The bounce buffer is a latch constructed of two
cross-coupled inverters.
The control switch logic senses a power·up signal (PUP) and PANEL LOCK signal to ensure control switch lockout
during the panel lock mode, and to eliminate program interruption after a power interruption With the
HALT/ENABLE switch left inadvertently in the HALT position during operation in the panel lock mode.

RUN

--IINDI~~~OR

16 ADDRESS/DATA
SWITCH SIGNALS
TO PROCESSOR

+5V

00
16-BITS FROM BADDRESS/DATA
LEG OF PROCESSOR
MULTIPLEXER
DATA SECTION

SERIAL
OUTPUT
6 FUNCTION
SWITCH SIGNALS
TO PROCESSOR

11-0954

Figure 7·1 Console Functional Block Diagram

7.3 DETAILED DESCRIPTION
This paragraph provides a detailed description of the console logic. Each major functional unit is discussed separately
and with regard to its interrelation with other functional units.
Both detailed and simplified logic diagrams are used to support the text. The Simplified logic diagrams are included
in this chapter; however, the detailed logic diagrams are part of the print set that is supplied with each computer.
Three drawings are referenced, and they are identified as D-CS·5409766·0·l, sheets 1,2, and 3. In this discussion,
the drawings are referenced by the C·numbers located in the title box and shown below:
Sheet 1 - Display Buffer and Driver (C·l)
Sheet 2 - Control Keys (C.3)
Sheet 3 - Scan Control and Switch Register (C·2)
7.3.1 Multiplexer
The multiplexer, located on the processor M7260 module, scans the 16 bits in the B·leg of the processor data
section. The information on these lines can be data bits or address bits. It is serialized in the multiplexer and
transmitted over the console cable to the buffer.

7·2

The multiplexer is a Type 74150 Data Selector/Multiplexer (1-of-16). It has 16 inputs (Eo through El 5) and a single
output. Four SCAN ADRS lines from the counter are the data select lines for the multiplexer: 4 bits give 16 unique
combinations. A low strobe signal enables the selected input to the output; however, the signal is inverted at the
output.
The four SCAN ADRS lines select the input lines on an equivalent number basis. For example, if the SCAN ADRS
lines represent decimal 5, input 5 is selected and enabled to the serial output. The SCAN ADRS lines from the
counter are inverted before being sent to the multiplexer. When the counter state is zero (0000), the SCAN ADRS
lines indicate 15 (1111) and multiplexer input 15 is selected. This ensures that input 15 is shifted into the proper bit
position in the buffer after a scan operation is complete. Table 7-1 shows the relationship between the counter state
and SCAN ADRS signals.

Table 7-1
Scan Address Signal Generation
Counter State

SCAN ADRS

MUX Line Scanned

0000 (0)
0001 (110)
0010 (2 10 )

1111 (15 10 )
1110(14 10 )
1101 (13 10 )

15
14
13

1110(14 10 )
1111 (15 10 )

0001 (110)
0000 (0)

7.3.2 Clock
The console clock provides pulses to clock the Counter and Shift Register (drawing C-2). It is a simple oscillator that
generates high level clock pulses. Two retriggerable monostable multivibrators (Type 74123) are connected
back-to-back to form a simple oscillator (Figure 7-2). The Q output of each is used to trigger the other. The clock
starts when power is applied to the processor and is self-sustaining thereafter.
One 74123 IC package (E4) contains two separate and identical units identified as 1 and 2. Output 1Q (pin 13) is
connected to input 2A (pin 9) and output 2Q (pin 5) is fed back to input lA (pin 1). The complementary Q outputs
are not used, nor are the CLEAR inputs. Input 2B is held high by application of +5V via resistor R18; therefore, unit
2 can be triggered only by a high-to-low level transition at input 2A (see truth table in Figure 7-2). Input 1B (pin 2)
is connected to signal PUP from the processor. This signal is low when power is off and is high when power is on.
When PUP is low, the clock output is inhibited regardless of the state of input 1A. When PUP goes high during the
power-up sequence, it triggers the first high level pulse at output 1Q. The high-to-Iow level transition of this pulse
triggers the first high level pulse at output 2Q (see timing diagram in Figure 7·2). Because both B·inputs are high, tbe
feedback connection (2Q to 1A) allows each unit to trigger on the high-to-low transition at its A input. This
produces a continuous string of positive pulses (CLK signal) at output 2Q. Pulse generation is self-sustaining as long
as PUP is high.
The counter is clocked on the low-to-high clock pulse transition and the Shift Register is clocked on the high-to-Iow
clock pulse transition. The period between clock pulses allows time for the serial data from the multiplexer to settle
down. This is important because the serial data is sent to the Shift Register via a cable connection.

7-3

PUP

20
2B
74123
E4

ClK TO COUNTER
AND SHIFT
REGISTER

74123
E4

RIB

TRUTH TABLE
14

15
RI9

NOTES:
I. H=High level, l=low level (bolh sleady slale)
2 .• =Transilion from low 10 high level
3. +=Transilion from high 10 low level
4. X = Irrelevanl (any inpul, including Iransil ion)
5. SL =One high level pulse

R20

+5V

n
n

•

START SIGNAL PUP
INPUT I B

1ST STAGE OUTPUT/
2ND STAGE
INPUT 2A/IO

CLOCK OUTPUT /
1ST STAGE
FEEDBACK 20/IA _ _- - I
11-0949

Figure 7-2 Console Clock, Schematic and Timing Diagram
7.3.3 Counter
The counter provides four scan address lines that are the data select lines for the data/address multiplexer (drawing
C-2), It also provides a control signal (SHIFT DISPLAY) to the Shift Register, which places it in the hold mode.
Two Type 74193 Synchronous 4-Bit Up/Down Counters (E6 and E8) are cascaded to provide an 8-bit counter
(Figure 7-3). Cascading is accomplished by connecting the CARRY output (pin 12) of the first counter to the
COUNT UP input (pin 5) of the second counter. The counter is used only in the count-up mode; therefore, the
COUNT DOWN input is disabled by connecting it to +5V, and the BORROW output is not used.
The preset feature is not used; thus, the LOAD input (pin 11) is disabled by connecting it to +5V. The CLEAR input
is not used so that the counter cannot be forced to 0 by an outside signal.
When the clock starts, the counter starts counting through its 256 states. It counts continuously as long as the clock
is running.
Two modes of operation occur during one complete counting sequence (256 states) before overflow (all Os) occurs
and the sequence repeats. Output A of the first 4-bit section (E6) is the least significant bit; output D2 of the second
4-bit section (E8) is the most significant bit. The first section advances from 0 through 15 (16 counts), overflows
(goes to 0), and starts over. At overflow, a pulse from the CARRY output of the first section is sent to the COUNT
UP input of the second section, which increments the second section by 1. After 16 overflows, the counter is full (all
8 bits are Is) which represents 255 10 or 256 counts. The next clock pulse causes both sections to overflow, which
sets the counter to 0 and the sequence repeats.

SCAN ADRS 01

12 SCAN ADRS 02

SHIFT
DISPLAY

CLOCKS_ _--"5, UP CNT
4
11

SCAN ADRS 08

llJI

AT OVERFLOW
CRYP-----------""-I:

ON CNT

7!1\3
COUNTER
LOAD 1s1 SECTION

~~ ~~
LOAD

7J1~3
COUNTER
2nd SECTION

INVERTERS
CONNECTED IN
WIRED-OR
CONFIGURATION
f =A 2+B2+C2+D 2
SHIFT DISPLAY
IS HIGH ONLY
WHEN A-oB 2.C 2 •
AND O2 ARE LOW.

DISABLES ON CNT AND LOAD
11-0950

+5V

Figure 7-3 Counter, Simplified Logic Diagram

The output of the first counter section is the 4-bit scan address [SCAN ADRS 01 (1) L, 02 (1) L, 04 (1) L, and 08
(1) L]. The lines go to four Type 7404 Inverters (ES) and then to the select inputs of the data/address multiplexer_
As the first section of the counter sequences through its 16 states, these lines cause the multiplexer to scan its 16
input lines and send the data serially to the Shift Register. Each of the four outputs of the second counter section
goes to a Type 7416 Inverter Driver (E7). The open collectors of these inverters are connected together in a
wired-OR configuration. The output is the SHIFT DISPLAY H signal, which is high only when all inverter inputs
(E8 counter outputs) are low (0). The SHIFT DISPLAY H signal is a control signal input to the Shift Register. When
it is low, the register is in the hold mode; when it is high, the register shifts serial data in to the right. The second
counter section is 0 only during states 0 through 15. During this period, SHIFT DISPLAY H is high, and the Shift
Register accepts serial data from the multiplexer and shifts it right. This data represents a complete scan of the 16
inputs to the multiplexer that are placed in the Shift Register. At state 16, a 1 is present in the second counter
section. From this state, up to and including state 255, one or more Is are present in the second counter section.
The counter states are shown in Table 7-2. During this period, SHIFT DISPLAY H is low, and the Shift Register is in
the hold mode. The data is static and is available for display.

A counter state change occurs in apprOximately IllS; therefore, the scan mode takes 16 IlS and the hold mode lasts
for 240 J1S. During manual console operation, data and addresses are generated by positioning switches. The
information on the multiplexer input remains stable for a long time in comparison to the 256 IlS required for a
counter scan/hold cycle. In effect, the multiplexer continually scans relatively stable information that can be
displayed as static rather than transient information.

7-5

•

Table 7-2
Counter States
Counter States
Counter
State
(Decimal)

2nd Section
C
B
A

lst Section
A
C
B

Remarks

0
1
2
3
4
5

0
0
0
0
0
0

0
0
0
0
1
1

0
0
I
1
0
0

0
1
0
1
0
1

.....

15
16
17
18

0
0
0
0

0
1
1
1

1
0
0
0

1
0
0
1

1
0
1
0

:::

31
32

0
0

0
1

1
0

239
240

1
1

1
0

255
0

1
0

States 0--15 are
scan mode. Data
) is obtained and
loaded into Shift
Register.

States 16-255 are
hold mode. Data
is held in Shift
Register for
display.

1
+-

Counter overflow

7.3.4 Display Buffer and Driver
The display buffer and driver logic consists of a 16-bit buffer and 16 inverter drivers for the ADDRESS/DATA
Register lights (drawing C-1).
The 16-bit buffer is composed of four Type 8271 4-Bit Registers (Ell, EI0, E13, and EI5). They are connected in a
shift-right configuration with a serial data input; the last bit output (DO) of the preceding section is connected to
the series data input (DS) of the following section (Figure 74). The parallel data inputs are not used. The reset input
(RD) is disabled by connecting it to +5V. The LOAD input (pin 10) is connected to ground (logic 0), and the SHIFT
input (pin 13) is connected to the SHIFT DISPLAY H signal from the counter. With the LOAD input held low, the
operating mode of the buffer is controlled by the SHIFT input. When the SHIFT DISPLAY H signal is high, the
buffer accepts data and shifts right; this is the console scan mode. When the SHIFT DISPLAY signal is low, the
buffer holds the data; this is the console display mode.
Each Shift Register output signal is sent to a Type 7416 Inverter Driver to illuminate an associated light-emitting
diode (LED). The 16 LEDs are the indicators for the ADDRESS/DATA Register display. A high output from the
buffer causes the LED to illuminate, which indicates that the associated bit is a logical 1. The final stage of a 7416
inverter has an open collector that is connected to an LED, which in turn is connected to +5V via a current-limiting
resistor (Figure 7-5). When the inverter input is low (logical 0 = OV), no current can flow through the LED because
there is no conducting path to ground through the transistor; therefore, the LED is not illuminated. A high (logical
1) inverter input puts a positive voltage on the base of the transistor, which turns it on. Current flows from the +5V
source through the resistor, LED, and transistor emitter to ground, which illuminates the LED.
7-6

1 7416

TYPICAL CIRCUIT (16 TOTAL)
2

+5V

lED 1

BUF 00 (1) H

5
SER IAl~
DS
DAT A
13
,----:..;:. SHIFT
lD
rAD ClK
11

A1 B1 C1 D1

8271
Ell

A2 B2 C2

' - - DS

L.....-

DS
r - - SHIFT

8271
El0

SHIFT

.---

.--

IfID ClK

A3 B3 C3 ~

A4 B4 C4 D4
L.....-

r - - SHIFT 8271
E15
.-- lD
AD ClK

8271
E13

AD ClK

+5V

~
SHIFT
DISPLAY

CLOCK
11-0951

Figure 7-4 Display Buffer and Driver, Simplified Logic Diagram

7416 INVERTER / DRIVER
(FINAL TRANSISTOR SHOW)

HIGH INPUT
FROM BUFFER

lED

~----~~------~----~~------~+5V

r------------------I CONDUCTING PATH WITH A HIGH INPUT
I
I

+
11-0952

Figure 7-5 LED Driver Circuit

7.3.5 Control Switches and Logic
The console contains six control switches (drawing C-3). The HALT/ENABLE switch is a 2-position toggle type;
HALT is the down position and ENABLE is the up position. The other five switches are momentary action type.
They are: load address (LOAD ADRS), examine (EXAM), continue (CaNT), deposit (DEP) and START. The DEP
switch is activated when it is lifted; the others are activated when they are depressed.
A bounce buffer is connected across the output contacts of each switch to eliminate interruptions of the output
signal due to contact bounce when the switch is activated. The bounce buffer is a latch constructed of two
cross-coupled 7416 inverter buffer/drivers. When the switch is activated, the output signal is latched and any contact
bounce, with accompanying signal loss, does not alter the output signal.
For the momentary action switches, the output is asserted low (logical 0) when the switch is activated. For the
HALT/ENABLE switch, the output is asserted low when the switch is in the HALT position.

7-7

The input of each switch is connected to the output of a 7417 Open-Collector Non-Inverting Buffer. The inputs of
all the 7417 buffers are connected to the output of a very simple logic network that detects power on/off and panel
lock on/off. Power is sensed by monitoring the power-up signal (PUP L) from the processor. Panel lock is sensed by
monitoring the PANEL LOCK signal from the OFF/POWER/PANEL LOCK switch on the console front panel. Panel
lock is a mode of operation that disables all console control switches, it prevents inadvertent switch operation from
disturbing a running program.
7.3.5.1 Nonnal Operating Mode - Normal operation is performed with PANEL LOCK off. This discussion is
referenced to engineering drawing C-3 and Figure 7-6, which is a simplified logic diagram.

r - - - - - - - - - - - - - - - - - - - - - - - - - - KEY LOAD ADRS

(1) L

, - - - - - - - - - - - - - - - - - KEY HLT ENS (1) L
KEY DEP (1) L
NOTES:
S= Lalch sel inpul
R= Lalch resel inpul
Q =Lalch oUlpuI
SET:S=O,R=1,Q=1
RESET: S=1,R=O,Q= 0

r1---~~-----~~-----~----------._-----~~+5V

S1 DEP

S6 LD ADRS

PUP L

+5V

PART OF ON/OFF/PANEL LOCK SWITCH
SWITCH CLOSED:PANEL LOCK =0 (PANEL LOCK OFF)
SWITCH OPEN' PANEL LOCK=1 (PANEL LOCK ON)
11-0953

Figure 7-6 Control Switches and Bounce Buffers, Logic Diagram

The switch input logic network is composed of one 7404 Inverter (ES) and one 7416 Open-Collector Inverter (E7).
The output of E7 is connected to PANEL LOCK, which is controlled by the key-operated ON/OFF/PANEL LOCK
switch on the console panel. When the switch is in the PANEL LOCK position, the panel lock mode is activated and
the PANEL LOCK signal is high (logical 1). When the switch is in the ON position, the PANEL LOCK signal is low
(logical 0). This is accomplished by grounding the PANEL LOCK signal in this switch position. The output of E7
(pin 6), which represents the state of input PUP L, is connected to the PANEL LOCK signal line. This point is the
input to all switch 7417 buffers (E3). It is high only when PUP L and PANEL LOCK are both high.
With PANEL LOCK off, the PANEL LOCK signal is low and the input to each switch is low. [Refer to momentary
action switch S6 (LOAD ADRS), which is typical of the five switches of this type.] The set input of the latch is the
rest terminal, and the reset input is the active terminal. With S6 in the rest position, a 0 is placed on the set input of
the latch (E2 pin 13). The latch is set (S=O, R=I, Q=I) and the output (E2 pin 12) is high, which is the non-asserted
state of the switch output [KEY LOAD ADRS (1) L = 1]. With S6 in the active position, a 0 is placed on the reset
input of the latch (E2 pin 11). The latch is reset (S=I, R=O, Q=O) and the output (E2 pin 12) is low, which is the
asserted state of the switch output [KEY LOAD ADRS (1) L = 0]. Note that the DEP switch (S1) is electrically
identical to S6 but its active position is up rather than down.
7-8

With the HALT/ENABLE switch (S3) in the ENABLE (up) position, the latch is set and the switch output signal
KEY HLT ENB (1) L = 1, which is its non-asserted state. This state allows a program to run. In the HALT (down)
position, KEY HLT ENB (1) L = 0 is the asserted state and halts an operating program. Type 7416 Open-Collector
Inverter E9 is used for power loss compensation and is described in a subsequent paragraph. In the normal operating
mode, it has no effect on the switch operation.
7.3.5.2 Panel Lock Mode - In the panel lock mode, the PANEL LOCK signal is high (+5V via resistor R42). All
switch inputs are now high. Panel lock is applied after a program has started in the normal operating mode. All
momentary action switches are in the rest position; switch outputs are high (not asserted) because the latches have
been set previously (S=O, R=l, Q=l). The HALT/ENABLE switch is in the ENABLE position; the switch output is
high (not asserted) because the latch has been set previously (S=O, R=l, Q=I). With respect to the momentary action
switches, the high on the switch input has no effect if the switch is moved to the active position, because it puts a 1
on the reset input of the latch whose reset input is already a 1. With respect to the HALT/ENABLE switch, the high
on the switch input has no effect if the switch is moved to the HALT position because it puts a 1 on the reset input
of the latch whose reset input is already a 1. Remember that the momentary action switch latches had been set (S=O,
R=I, Q=I), and the HALT/ENABLE switch latch had also been set.
In this mode of operation, inadvertent switch operation cannot halt or otherwise alter a running program.
7.3.5.3 Power Loss During Operation - The processor contains a power fail circuit that allows the computer to
tolerate an ac power loss without adverse effects. If a power loss occurs in the normal operating mode (panel lock
off), the switches perform the functions determined by their current positions as soon as the +5V logic supply
voltage is reestablished. PANEL LOCK = 0 is the signal that provides normal switch operation in this case.
If a power loss occurs in the panel lock mode, a forcing signal is required to ensure that the latches are driven to the
states commensurate with the switch positions before the PANEL LOCK signal is applied again. Without the forcing
signal, the latches could be set or reset in a random manner not related to switch position as the +5V logic supply
voltage is reestablished.
As ac power is restored, PUP L is forced low for approximately 70 ms. This applies a 0 to the switch inputs to force
the latches to the states commensurate with the switch positions: all momentary action switches are not asserted
and KEY HLT ENB (1) L is not asserted (HALT/ENABLE switch in ENABLE position). The processor resumes
operation and when PUP L goes high again, the panel lock mode is reestablished.

If the HALT/ENABLE switch is inadvertently placed in the HALT position during processor operation in the panel
lock mode, the processor does not halt. However, if a power loss occurs with the switch in the HALT position, PUP
L going low during the power-up sequence resets the latch and its output, KEY HLT ENB (1) L, is low, which halts
the program. When PUP L goes high again and the panel lock mode is reestablished, the 1 on the switch input does
not set the latch or eliminate the HALT signal.
Open-collector inverter E9 solves this problem. When PUP L goes high during the power-up sequence, the I on the
switch input is also inverted by E9 and a 0 is placed on the set input (E1 pin 1) of the latch. The latch is set and its
output is not asserted [KEY HLT ENB (1) L = 1], which allows the processor to resume operation even though the
switch is in the HALT position.

7-9

CHAPTER 8
KDII-B DETAILED DESCRIPTION

8.1 INTRODUCTION
This chapter describes the logic and physical implementation of the KDll-B data path (DP), data path control
(DPC), Unibus control, serial communications line (SCL), and the line clock. Extensive use is made of bipolar,
medium and large scale integrated circuits in the processor. There are 28 read-only memories (ROMs) used in the
KDll -B. Details of the microprogram are described in Chapter 9.
8.2 ROMs AS GENERALIZED GATES
With the increasing availability of inexpensive bipolar ROMs, it is possible to replace rather complex combinational
logic structures with one or two l6-pin dual in-line integrated circuits. In the processor, extensive use is made of two
different ROM formats. As shown in Figure 8-1, one format stores 256 bits (b), arranged in 32 words of 8 bits each.

+5V
CONA BA 04 (1) H
CONA BA 06 (1) H
CONA BA 07 (1) H
CONA BA 05 (1) H
CONA BA 13 (1) H
CONA BA 11

(1) H

CONA BA 00 (1) H
CONA BA 02 (1) H

03
15
01
02
07
05
06
04

+5V

MO (1)
R16

A7
M3 (1)
A6
A5

23-A02A2
INTN
ADDRS
M2 (1)
DECODE

A2
A1

M1 (1)

MO(1)

eDNA INT
o H

M1 (1)

CONG ENAB PSW L

eONG ENAB SPR L

09
23-A09A1
DATI
ADDRS
DECODE

M2 (1)
M3 (1)

M4(1)
M7 (1)

CONG ENAB SPL L
R43

M5 (1)

M6 (1)

CONA ENAB SWITCH REG L
CONA ENAB MODEN PSW L

(0) 1024 BIT ROM (256 WORDS X 4 BITS

06
07

CONA ENAB L CLK

PSW L

CONA ENAB ALU L
CONA INT TRAN SYNC L

(b) 256 BIT ROM (32 WORDS X 8 BITS)
11-1196

Figure 8-1

1024-Bit and 256-Bit ROMs

The other format stores 1024 bits (ay, arranged in 256 words of 4 bits each. The 32-word ROM has 5 address lines, 1
output enable line, and 8 outputs. The 256-word ROM has 8 address lines, 2 output enable lines, and 4 outputs.
Both devices have open-collector outputs.
Figure 8-2 illustrates the use of a 32 X 8 ROM as a generalized gate. In the example, a 32 X 8 ROM is used as a
5-input priority encoder. The output of the priority encoder follows the following equation:

8-1

OUTPUT

V0 if IO = 1
V I if IO = a and 11 = 1
V2 ifIa = 11 = a and 12 = 1

V4 if IO = 11 = 12 = I3 = a and 14 = 1
A similar priority encoder is used in the KDII-B on print CONE where it is necessary to decide which switch
function to perform if more than one console switch is depressed.

~~1

V4 L

Y3
B

32xa

C
D

OUTPUTS

V3 L

AT LEAST 1 INPUT L

Y7
ya

GREATER THAN 1 INPUT L
NOT USED
11-1183

1 of 5 Priority Encoder

Truth Table

a
a
a
a

a
a

a
1
a

Address
Octal

a
1
2
3

a
1
a
a

a
a

a
a
a
a

a
1

a
a
a

a
a
a
a

Figure 8-2 32 X 8 ROM used as Generalized Gate

8-2

Many situations arise in which five or fewer input conditions result in combinations of eight or fewer output
conditions where a 32 X 8 ROM is used for implementing the function. Similar applications apply to 256 X 4
ROMs. For example, the KDll-B uses one 256 X 4 ROM to test all of the PDP-ll conditional branch instructions
against the C, N, V, and Z condition code bits. The branch decode ROM may be found on print DPG in position
E059.
8.3 KDII-8 DATA PATH, SIMPLIFIED DESCRIP110N

Figure 8-3 contains a simplified diagram of the KDll-B data path. The heart of the DP is an arithmetic-logic unit
(ALU), which is capable of performing 16 Boolean operations and 16 different arithmetic operations on two 16-bit
binary variables. The inputs to the ALU are storage registers on the A-leg input and the B-Ieg input. The output of
the ALU feeds into a switch that is capable of introducing external data into the DP from the Unibus.

UNIBUS INPUT - - -

A LEG
-STORAGE
REGIS TERS

DATA
SWITCH

rL
ARITHMETIC
LOGIC
UNIT

B LEG
STORAGE
REGISTERS

LJ
-

UNIBUS
OUTPUT

DATA FLOW
11-1195

Figure 8-3 KDII-B Simplified Data Path Block Diagram

8.3.1 Data Path (DP) Detailed Description

Figure 84 is a detailed block diagram of the KDll-B DP. The logic for all elements of the DP shown in Figure 84,
with the exception of the Bus Address Register and associated Unibus drivers, is found in prints DPA through DPHI.
It is important to recognize that this DP consists of a number of interconnected registers that are capable, when
properly controlled, of executing the PDP-II instruction set defined in Chapter 6.
8.3.2 DP Data Polarities
It is useful to note the data polarity at various places in the processor. There are two signal levels used in the
KDII-B. A high Signal is represented by a voltage of +3V to +5V. A low signal is represented by a voltage between
OV and O.4V. Positive and negative data polarities are defined as follows:

Negative Data Pol::.rity: Logic 1 =Low Signal =O-O.4V
Logic 0 High Signal 3-SV

Positive Data Polarity: Logic 1 =High Signal = 3-5V
Logic 0 = Low Signal = O-O.4V

8-3

Data polarity is negative on the Unibus and within the dotted lines surrounding the ALU as shown in Figure 8-4.
Throughout the remainder of the processor the data polarity is generally positive. In the KDII-B print set, the
polarity of the asserted logic signal is' given. For example, the signal DPF LOAD IR L is asserted, true, or logic I,
when it is at OV (low signal).
8.3.3 Data Path Control (DPC)
The DPC is shown in Figure 8-4 at the left side of the drawing. All functions performed by the processor, including
instruction interpretation, trap handling, and Switch Register (SR) function execution, depend upon the contents of
the control store (CS). For each PDP-II action performed by the KDII-B, the DPC executes a sequence of
microsteps stored in the CS.
The microprogram contained in the CS consists of a series of microroutines which, when executed in the proper
sequence, enable the KDII-B to perform as a PDP-II processor. Details of the microprogram are described in
Chapter 9.
The CS consists of ten 256 X 4 bipolar ROMs, shown on prints CONF and CONGo The outputs of the ROMs are
used to control the registers and arithmetic elements in the DP. The current control step (microstep) is stored in a
microprogram counter (MPC). The MPC is an 8-bit latch that is loaded at intervals of approximately 300 ns with a
number generated by the output of the NXT field of the CS, wire-ORed with the outputs of the microbranch
network.
8.3.4 A-Multiplexer
The A-Multiplexer (AMUX) is a 2-word, I6-bit multiplexer composed of four Type 8266 2-Input, 4-Bit Digital
Multiplexers. The AMUX representation is contained in four logic prints as shown below.
AMUX
Designation

E009
EOU
EOI3
E015

DPA
DPB
DPC
DPD

The A-word input to the AMUX is the output of the ALU, and the B-word input consists of the Unibus data lines D
(15 :00). These data signals are taken from the Unibus via four Type 380 Quad 2-Input NOR Gates (called bus
receivers). The receiver designations and locations are listed below.
Receiver
Designation
EOOI
E003
E005
E007

Unibus
Data Bits
BUS
BUS
BUS
BUS

DOO-D03
D04-D07
D08-DII
Dl2-DI5

DPA
DPB
DPC
DPD

The AMUX A-input is inverting and the B-input is non-inverting. Word selection is based on the state of select signal
inputs SO and SI as shown in the following truth table.
Select Signals

Output

f3, f2, f1, fO

L
L
H
H

L
H
L
H

B
A
B

DATA PATH CONTROL (DPC)

IRS
IRD

ROM
BA

FLAG
CONTROL

'5 ~ iJ..A-rC 1/

\"\ (~rLwtl..

PI. ...

A1m.Ls.-,;~
j4;t tA/... I r"J..f.y.l?1I., ,

'CH

SERIAL INPUT DATA
SERIAL OUTPUT DATA

<15'00>

<7'0>

8
16

I
CONSOLE
DISPLAY
<111,00>

NXT<39,32>

DATO

I POLARITY

DATI

---,

r:NEGAriVE
1DATA

SCAN
AD DRS.

MSY N
SSYN
C<1 : 0 > BBS Y
NPR
NPG
SAC K
7:4>BR
7:4>BG
INT R
INlT
AC L0
DC L 0

STATE

r---~L~~~~n-_,':--~L~~~~-~~!---'
ARITHMETIC LOGIC
UNIT
(ALU)

I
I

PAUSE

UNIBUS
CONTROL
(BC)

<
<

PSW
AUX ROM

TIMING

MAIN ROM (CS)

....

UNI BUS CONTROL LINES

...

2
BUS ADDRESS
REGISTER (BA)

INTERNAL
ADDRESS
DECODER

CONTROL
FIE LOS I--~I--<",
FOR DP
AND BC

DATA PATH
CONTROL (OPC)
LINES

PSW
SR
L CLK
S CL
SPM

NOTE'
Unibus including drivers and
receivers hove negative
dolo polo rile,

UNIBUS ADDRESS LINES <17:00>

UNIBUS DATA LINES < 15:00>

11-1194

Figure 84 KDII-B Detailed Block Diagram

8-5

Select signal SO is CONA ENAB ALU Hand Sl is DPA RUN GND L. Signal DPA RUN GND L is connected to
ground so it is always low; therefore, signal CONA ENAB ALU H controls the selection of the input. When it is low,
the B-input is selected, and when it is high, the A-input is selected.
The 16-bit output of the AMUX is sent to several places as shown below.

Destination

Bus Address Register
Unibus Drivers
Instruction Register
B-Register
Scratch Pad Memory
PSW Logic
SCL Control Logic
Line Clock

CONA
DPA-DPD
DPF
DPA-DPD
DPA-DPD
DPE
DPH
CONI

8.3.5 Arithmetic Logic Unit (ALU)
The arithmetic logic unit (ALU) is the heart of the data path logic. It performs 16 Boolean operations and 16
arithmetic operations on two 16-bit words. Not all of these arithmetic and logic operations are in the KDII-B; Table
9-1 lists the operations that are used. The truth table for the 74181 ALU (Appendix A) shows all the operations that
are available.
The ALU is composed of four Type 74181 Arithmetic Logic Unit/Function Generators and one Type 74182
Look-Ahead Carry Generator. The symbolic representation of the ALU is contained on four logic prints as shown
below.

Device

Component
Designation

74181
74181
74181
74181
74182

E018
E0l9
E020
E022
E032

Print
DPA
DPB
DPC
DPD
Sections shown on
prints DPA, DPB,
DPC, and DPD.

Figures 8-5 and 8-6 show the signal and pin designations for the 74181 and 74182, respectively.
For clarity, a detailed block diagram of the ALU is shown in Figure 8-7. The 16-bit A-word input is fed by ALEG
(15 :00) and the 16-bit B-word input is fed by BLEG (15 :00). Each leg is driven by several sources that are
connected in a wired-OR configuration. The ALEG sources are: scratch pad memory, constants generator, processor
status word logic, console Switch Register, and serial communications line. The BLEG sources are: B register, sign
extension logic and +1 logic. Each of these sources is discussed in subsequent paragraphs. The 16-bit ALU output is
sent to the A-word input of the AMIDe The AMUX is a 2-word, 16-bit multiplexer composed of four Type 8266
2-Input, 4-Bit Digital Multiplexers. The source of the B-word input to the AMUX is Unibus data bits D (15:00).

8-7

COMPARATOR OUTPUT
CARRY OUT PUT
CARRY GEN ERATE OUTPUT
14
18
19
20
21

WORD A AND
WORD 8 INPUTS

23
1
2

161,7 l'5

A=8 COUT

A3
82

74181
ARITHMETIC
LOGIC UNIT /
FUNCTION
GENERATOR

CARRY PRO PAGATE OUTPUT

81
Al

12
11

AO
S3

tFU~~I~~

SO
6
1,

SELECT
INPUTS

13
11
FUNCTION
OUTPUTS

10
9

CIN

CARRY INP UT
MODE CON TROL INPUT
11-1559

Figure 8-5 74181 Pin and Signal Designations

CARRY I NPUT
1,3
CN
3
CARRY
GENERATE
INPUTS

1
14

5
4

CARRY
PROPAGATE
INPUTS

2
15

GO
C N +X

CN+Y

G2
G3
PO
PI

74182
LOOK-AHEAD
CARRY
GENERATOR

CN+Z

12
11

} CARRY OUTPUTS

10
7

CARRY GENERATE OUTPUT
CARRY PROPAGATE OUTPUT

11-1558

Figure 8-6 74182 Pin and Signal Designations

The ALU is controlled by six input signals (Table 8-1) that select the mode (logic or arithmetic) and the desired
function. All control bit combinations versus functions are listed in the 74181 truth table in Appendix A. The
primary source for the control signals is the control store logic (print CONF). A wire-ORed connection allows the
control signals to also be obtained from the auxiliary ALU control (print DPF) and the IR decoding logic (print
DPG). The four function select signals (CONF ALU SO L-S3 L) are buffered and inverted by Type 7437 NAND
Buffers (print DPA) before they are sent to the ALU select inputs. After buffering, they are identified as DPA ALU
SO H-S3 H. Mode signal CONF ALU MODE H is sent directly to the ALU. The carry input signal (CONF CIN H) is
sent to one input of exclusive-OR gate E081 (print DPA). The output of this gate is signal DPA ALU CIN 00 Hand
is sent to the carry inputs of both the 74181 ALU and 74182 carry generators. This signal is also controlled by
Signals DPF COP Land DPE COUT (1) L. They are inputs to NOR gate E080 which supplies the other input to
exclusive-OR gate E081. Signal DPF COP L is an output of E061 SOP AUX CTL ROM 23-A03A1 (print DPF) in the
auxiliary ALU control logic. Signal DPE COUT (1) L is an output of E052 COUT flip-flop (print DPE) in the PSW
logic.

8-8

ARITHMETIC LOGIC UNIT
COMPOSED OF 4 TYPE
74181 ALU'S AND 1 TYPE
74182 LOOK AHEAD CARRY
GENERATOR. PERFORMS
ARITHMETIC FUNCTIONS
AND LOGIC FUNCTIONS

I~-------------------~I

CONF CIN H
OPF COP L

HIGH BYTE
COMPARATOR
OUTPUT. USED
WITH LOW BYTE
COMPARATOR
OUTPUT TO SET
Z CONDITION CODE

}-..--l---I Cn

AMUX COMPOSED
OF 4 TYPE 8266
4-BIT MULTIPLEXERS

74182
LOOK AHEAD CARRY GENERATOR
E032

I
I

.--------+---..
,--;IC-OPC8-15:0

OPA ALU CIN 00 H----"----,

OPA ALEG 00-03 L

OPO
ALEG
12-15L

OPA 8LEG 00-03 L

OPO
8LEG
12-15L

FUNCTION
OUTPUTS 12-15

f MuL~IPLEx"ER'I

(TWO 16-BIT'
INPUTS)

"\. ~
8266
AMUX
E009

*BUS
012-15H

II
OPO
AMUX
12-15 H

FUNCTION OUTPUTS 08-11

L __ _

___________ -.J

MODE SELECTION.
M IS HIGH FOR
ARITHMETIC
FUNCTIONS AND
LOW FOR LOGIC
FUNCTIONS

*BUS
008-11H

8266
AMUX
EOll

OPC
AMUX
08-11H

8266
AMUX
E013

OPB
AMUX
04-07H

FUNCTION OUTPUTS 04 - 07

*BUS
004-07H
*FROM UNIBUS VIA
BUS RECEIVERS

FUNCTION OUTPUTS 00-03

"IS
000-03H

DPA
AMUX
00-03H

11-1566

Figure 8-7 Arithmetic Logic Unit Block Diagram

Table 8-1
ALU Control Signals

Name
Control Store
Control Store
DOP Aux Cont
SOP Aux Cont
r-IR Decode

Signal Source
Number
Designation
ROM23-AIIA2
ROM23-A06A2
ROM23-A02Al
ROM23-A03Al
ROM23-A05Al

EI04
E094
E053
E061
E066

Print
CONF
CONF
DPF
DPF
DPG

Control Signal
CONF
CONF
CONF
CONF
CONF
CONF

ALUS3 H
ALUS2 H
ALUSI H
ALUSO H
ALU MODE H
CINH

X
X
X
X
X
X

X
X

The A-B terminal of each 74181 ALU is an open-collector comparator output that is high when the input words are
equal and the ALU is in the subtract mode. These outputs are wire-ANDed for each data byte to generate equality
signals that are used in forming the Z condition code. Signal DPA 0-7=0 H indicates that the inputs to the low data
byte are equal to zero. Signal DPA 8-15=0 H indicates that the inputs to the high data byte are equal to zero.
8.3.6 B Register
8.3.6.1 Functional Description - The B register (BREG) is the only storage register in the B-leg of the ALU. The
BREG is used as a general purpose register to store the results of any operation that requires data to be read from
the SPM. It is used as a shift-left/shift-right register to perform rotate, shift, and byte instructions.
The BREG output is attached to additional logic to permit its lower byte to be Sign-extended during execution of
byte and branch instructions. Logic is also provided to place the constant +1 on the B-leg. This operation is used in
the process of incrementing or decrementing the general registers by 2. This discussion covers the BREG and the
additional logic.
The BREG consists of four Type 74194 4-Bit Bidirectional Universal Shift Registers. The register designations and
locations are listed below.
74194
Designation

E044
E045
E035
E038

DPA
DPB
DPC
DPD

8-10

The additional logic required for the sign extension and +1 operations is listed below.

Device
74HOI
74HOI
7404
7400
74S158
74S158

Component
Designation

E036 (4)
E087
E073
E037 (4)
E039
E040

DPA
DPA
DPA
DPB
DPC
DPD

For clarity, a simplified logic diagram of the BREG and associated logic is shown in Figure 8-8. The inputs to the
BREG consist of the 16 bits from the AMUX. They are identified as:
DPA AMUX 00 H - 03 H
DPB AMUX 04 H - 07 H
DPC AMUX 08 H - 11 H
DPD AMUX 12 H - 15 H
The corresponding BREG outputs are:
DPA BREG 00 (1) H - 03 (1) H
DPB BREG 04 (1) H - 07 (1) H
DPC BREG 08 (1) H -11 (1) H
DPD BREG 12 (1) H - 15 (1) H
The BREG is clocked by DPA PROC CLOCK L, which is processor clock signal CONJ PROC CLOCK H that has
been buffered and inverted by gate E083 pin 03 (print DPA).
The type of operation performed by the BREG is determined by the states of mode control inputs SI and SO as
shown below.
Mode Control
SI
SO

H
L

H
H

Operation
Parallel Load
Shift Right (towards LSB)
Shift Left (towards MSB)
Hold (clock inhibited)

The BREG is loaded when both mode control inputs (SI and SO) are high. These inputs are selected by control store
field BRG (CS word bits 04 and 05). The signals are: CONG B MODE 01 H (bit 04) that is sent to input SI; and
CONG B MODE 00 H (bit 05) that is sent to input SO. Shift-right, shift-left, and hold operations are also controlled
by the BRG field (see CS word format in drawing D-CS-M7261-0-1, sheet 13). The shift-right (SR) and shift-left (SL)
inputs are the serial data inputs that are used only during shifting operations. They are discussed in subsequent
paragraphs.
The eight bits that constitute the low byte of the BREG are sent to NAND gates whose outputs are sent to the
B-word input of the ALU. Bits DPA BREG 00 (1) H-03 (1) H are connected to Type 74HOI High Speed NAND
Gates which have open-collector outputs. An open-collector gate is used because the +1 logic is wire-ORed to bit
BREG 00 (1) H. Bits DPB BREG 04 (1) H-07 (1) H are connected to 7400 NAND gates. All eight bits are enabled by
signal CONG BBOT H which is one of two bits of the B-Ieg control field of the control store word. It is generated by
CS ROM El06 (print CONG).
8-11

CO NG BMOOE OOH
CONG BMOOE 01H
OPO AMUX 15H

~
51

OPO BREG 15(1) H

14( 1) H
BREG
E038

13H
12H

>---- A2
Bl

1
51

OPC BREG l1C 1 ) H

BREG
E035

09(I)H

ClR ClK 5l

B2
~

08(1) H

10l
BlEG
MUX
E039

09l

OPE RIGHT 5HIFT 07 H

06H
BREG
E045

05( 1) H

06l

H:0

04( 11 H

r--

T
+5V

- ; \ , OPB BlEG 07L
E037 ) 0 - - - - - - -

06(1) H

CLR ClK 5L

08l
5

OPB BREG
07( 1) H

04H

AO
E

•

CO NG BTOP H

05H

OPC BlEGlll

+5V

08H

10(11 H

12l

AO
E

10H

OPB AMUX 07H

13l

09H

BlEG
MUX
E040

'-----

OPC AMUX 11 H

14l

12(1 )H

ClR ClK 5l

13( llH

OPA PROC CLOCK l

OPO BlEG 15l

14H

---

05L

E037)

IE037)
•

04L

OPA BREG

~~~~~~~~~~~~0~3~(~li)H~~
__r-~--~
.::
50 5R
.'\.
02(1) H

~~~~

01C 1 ) H

-~~~~~Cl~K~5L~~

OPA BlEG 03L
E036 ) 0 - - - - - - -

~-...,
02L
~)O-------

LL---f-1

OIL

UE03:,)O-----~~
~

OO(I)H
_
~~~-~~r-~~

OPE 5ERIAL 5HIFT H

E073

CONG BBOT H

OOL
rOPA+1H

EO 87 jC)-....--"JVY--

+ 5V

CONB INH+1L
11-1564

Figure 8-8 B Register and Output Logic

8-12

The eight bits that constitute the high byte of the BREG are sent to the B-word inputs of the BLEG MUX. The
A-word inputs of the BLEG MUX are connected in common to DPB BREG 07 (1) H. The BLEG MUX is composed
of two Type 748158 2-line-to-l-Line Multiplexers. Input word selection is controlled by the select (8) input when
the enable (E) input is asserted low as shown below.

Enable (E)
Input

Select (S)
Input

Output

X
L
H

H
A-word
B-word

H
L
L

The select (8) signal is CONG BTOP H, which is the other bit of the B-Ieg control field of the control store word. It
is generated by C8 ROM E095. The enable (E) signal is DPA+l H from the +1 logic.
The + 1 logic consists of inverter E073 and NAND gate E087. When activated, the output of E087 puts a + 1 in bit
DPA BREG 00 (1) H via a wired-OR connection with the output of the NAND gate associated with this bit from
the BREG.
8.3.6.2 BLEG Operations That Provide Input to the ALU - The following discussion covers the three operating
modes of the BLEG that provide input data to the ALU. The modes are: BREG unmodified, BREG sign extended,
and generation of the constant +1. The output of the BREG is gated onto the BLEG in a manner dictated by the
BLEG mode of operation. The circuits involved are the BLEG MUX, + 1 logic, and gates E036 and E037 on the
outputs of BREG bits 00-07. The discussion is not concerned with the operation of the BREG.
Control of the BLEG operating mode is provided by control store field BLG. This field is physically split in the C8
word as shown in Table 8-2.

Table 8-2
Control Store Signals for BLEG Operations
Control Store
Bit
Field

ROM
No.

Name

Output Signal
Function

BTP

E095

CONGBTOPH

Controls BREG
output bits
08-15 (high byte)

BBT

EI06

CONGBBOTH

Controls BREG
output bits
00-07 (low byte)

The following truth table shows the states of C8 bits 14 and 16 for the three BLEG modes.
Bit 16
BDT

Bit 14
DTP

DLEGMode

H
L
L

BREG Unmodified
Sign Extend BREG
Generate Constant +1

H
L

8-13

In the BREG unmodified mode, it is desired to place the unmodified contents of the BREG on the BLEG. Control
store field BLG makes both CONG BTOP Hand CONG BBOT H high. Signal CONG BBOT H enables the low byte
of the BREG onto the BLEG via gates Eb36 and E037. Signal CONG BBOT H is inverted by E073 and is identified
as DPA +1 H. It is the enabling signal for the BLEG MUX (E039 and E040). In this case, it is low and enables the
BLEG MUX. The select (S) signal for the BLEG MUX is CONG BTOP H, which is high. This selects the B-word input
of the BLEG MUX which is the high byte of the BREG output. Thus, the 16-bit output of the BREG is transferred
to the BLEG unmodified.
In the BREG sign-extended mode, it is desired to place the unmodified low byte of the BREG on the BLEG and sign
extend the high byte, which makes bits 08-15 the same as bit 07. The sign-extended high byte is also placed on the
BLEG. Control store field BLG makes CONG BBOT H high and CONG BTOP H low. Signal CONG BBOT H enables
the low byte of the BREG onto the BLEG via gates E036 and E037.
Bit 07 [DPB BREG 07 (1) H] from the BREG is sent to all eight A-inputs of the BLEG MUX. The BLEG MUX is
enabled by DP A + 1 H which is low. Select Signal CONG BTOP H is low which selects the A-word of the BLEG MUX.
This is the high byte of the B-Ieg but all eight bits are identical and equal to the state of DPB BREG 07 (1) H. The
sign of bit 07 is extended to bits 08-15 and these bits, along with unmodified bits 00-07, are transferred to the B-leg.
In the +1 operation, it is desired to place the constant +1 on the BLEG. The constant +1 is placed in the LSB
position (bit 00) and all other bits (01-15) are forced to O. Control store field BLG makes CONG BBOT Hand
CONG BTOP H both low. Signal CONG BBOT H disables the E036 and E037 gates, which drives BLEG bits 00-07
high. Signal CONG BBOT H is also inverted by E073 to produce DPA +1 H, which is high. Signal CONB INH +1 L
controls the activation of the +1 logic. It is high and is ANDed with DPA +1 H to produce a low at the output of
NAND gate E087. This output is wire-ORed with the E036 NAND gate associated with bit 00. This action pulls the
wire-ORed connection low, which makes bit 00 low. Bits 01-07 remain high. Signal DPA +1 H is high, so it disables
the BLEG MUX and drives all its outputs high (bits 08-15). This operation places the constant +1 onto the BLEG.
The BLEG is the input to the B-word of the ALU that uses negative logic. The + 1 operation can be readily seen by
looking at the BLEG bits with respect to their logical states as follows:
BLEG 00 =Low =Logical 1
BLEG 01-15 = High = Logical 0
8.3.6.3 BREG Shifting Operations - The BREG is used as a left/right shift register to perform rotate, shift, and
odd byte instructions. The following discussion covers the shifting process and generation of the serial shift input for
the ASL, ASR, ROL, and ROR instructions. An explanation of the BREG operation during the performance of byte
instructions is discussed separately.
The key to this discussion is the symbolic representation of the bit structure of the BREG as shown in Figure 8-9.
Each of the four 74194 Shift Registers that make up the BREG has a shift-left (SL) serial input and a shift-right
(SR) serial input. The SL input is connected to the lowest order bit and the SR input is connected to the highest
order bit. The four devices are interconnected to provide shift-left and shift-right paths for the 16-bit BREG. For
clarity, the parallel inputs and outputs are not shown.
Mode control signals CONG BMODE 00 Hand CONG BMODE 01 H select a shift-left or shift-right operation. In
shifting operations that deal with instructions ASL, ASR, ROL, and ROR, the same source is used for serial input
data for a shift left or a shift right.
The SL serial input goes to BREG bit 00 and the SR serial input goes to BREG bit 15. When SL or SR is enabled,
the other input is disabled. The signal name for the serial data input is DPE SERIAL SHFT H which is the f} output
of ROT MUX 1 E048 (print DPE). Depending on the instruction being processed, DPE SERIAL SHFT H can load
the appropriate BREG serial input with a 0 (for ASL), bit 15 of the BREG output (for ASR), or the C-bit (for ROL
and ROR).

8-14

OPE SERIAL SHFT H-\

OPE RIGHT 5HFT 07 H
(From bit 08 output of
BREG via BYTE MUX for
shift and rotate word

Shift left serial input

instruction)

Shift right serial input

B Register Bit Structure

TRUTH TABLE
OPA RUN GNO L

ASL

OPO BREG 15 ( \) H

A5R
ROT

ROL
OPE COUT ( \) H

~~:~

OPE 5ERIAL 5HFT H

ROR
51

Funct.(f\ )

ROR

ASR

ROL

ASL

OPA ALU 5\ H - - - - - - '
OPA ALU 50 H - - - - - - - - '

Generation of OPE SERIAL SHj;T H

Instruction

Value ofDPE
SERIAL SHFT H

Remarks

ASL

DPARUNGNDL

o to BREG bit 0 via SL input

ASR

DPD BREG 15 (I) H

Bit 15 of BREG output to bit 15 of
BREG via SR input

ROL

DPE COUT (1) H

C bit to BREG bit 0 via SL input

ROR

DPE COUT (1) H

C bit to BREG bit 15 via SR input

Figure 8-9 B Register Shift Signal Inputs

The values of DPE SERIAL SHFT H and the truth table for the ROT MUX 1 are shown in Figure 8-9.
This register handles byte shifting also as required by instructions ASLB, ASRB, ROLB, and RORB. Signal DPE
RIGHT SHFT 07 H is used as a serial right (SR) input to bit 07 to handle replication of bit 07 for an ASRB
instruction and to load the previous contents of the C-bit for an RORB instruction. This signal is also required to
perform the word shifting for instructions ASR and ROR because there is no direct connection between bits 08 and
07 for :t shift-right operation. Signal DPE RIGHT SHFT 07 H is generated by BYTE MUX E047 and it represents
BREG output bit 08 (DPC BREG 08 H) during word instructions ASR and ROR.
8-15

The shifting requirements for the ASL, ASR, ROL, and ROR instructions are described briefly below.

Arithmetic Shift Left (ASL) - Shifts all bits left one place. Bit 0 loaded with a O.
The BREG is shifted left one place. ROT MUX I selects ASL input (DPA RUN GND L) which is logical 0 because it
is connected to gro.und. OPE SERIAL SHFT H = 0 and is loaded into BREG bit 00 via the SL input.

Arithmetic Shift Right (ASR) - Shifts all bits right one place. Bit 15 is loaded with BREG output bit 15.
The BREG is shifted right one place. ROT MUX I selects ASR input [DPD BREG 15 (1) H] , which is output bit 15
of the BREG. DPE SERIAL SHFf H equals the bit 15 output of the BREG and is loaded into BREG bit 15 via the
SR input. This is replication of bit 15. DPE RIGHT SHFT 07 H equals the bit 08 output of the BREG and is loaded
into BREG bit 07 via the SR input to provide the connection from bit 08 to bit 07.

Rotate Left (ROL) - Rotates all bits left one place. Bit 00 loaded with C-bit.
The BREG is shifted left one place. ROT MUX 1 selects ROL input [DPE COUT (1) "H] , which is the value of the
C-bit prior to execution of the instruction. DPE SERIAL SHFT H equals this value of the C-bit and is loaded into
BREG bit 00 via the SL input.

Rotate Right (ROR) - Rotates all bits right one place. Bit 15 loaded with C-bit.
The BREG is shifted right one place. ROT MUX 1 selects ROR input [DPE COUT (1) H] , which is the value of the
C-bit prior to e~ecution of the the instruction. DPE SERIAL SHFT H equals this value of the C-bit and is loaded
into bit 15 via the SR input. DPE RIGHT SHFT 07 H equals the bit 08 output of the BREG and is loaded into
BREG bit 07 via the SR input to provide the connection from bit 08 to bit 07.
In each of these instructions, the C-bit is loaded with a new value from the BREG. This function is discussed in the
description of the PSW logic.
8.3.7 Byte Instructions
For the correct execution of all instructions that operate on data, the least significant bit of both the source and
destination must line up with bit 0 of the A-leg and B-leg, respectively. This same rule applies even if the instruction
being executed is a byte operation. For even bytes this is no problem, since the data received from the Unibus has
the least significant bit of the low order byte lined up properly. For odd bytes, it is necessary to shift the data word
right eight bit positions to properly line up the data. Then if the destination is an odd byte, the data must be shifted
eight bits left before it is restored to its proper memory location. This operation is illustrated in the example in
Figure 8-10 with the associated processor flow.
8.3.8 Scratch Pad Memory
The scratch pad memory (SPM) is a 16-word by 16-bit random access read/write bipolar memory composed of four
Type 7489 16-word by 4-Bit Memory Units. A block diagram of the SPM is shown in Figure 8-11. The SPM
representation is contained on four logic prints as shown below.
SPM
Designation

EOI0
EOl2
E014
E016

DPA
DPB
DPC
DPD

8-16

,BISB INSTRUCTION
153737 BISB 0001, ODD
401 0001 ADDRESS (BYTE)
403 0002 ADDRESS (BYTE)

KDII-B (print CONL) Flow
Get word from 400 into BREG
.IShift BREG right 8 places
.ISign Extend BREG
.IStore contents of BREG in RlO
.IGet word from 402 into BREG (use DATIP)
.IShift BREG right 8 places
.ISign Extend BREG
.I-

401

400

SHIFT B TIMES

I SIGN

EXTENDED

401

403

402

R (10]

SHIFT 8 TIMES

I SIGN

EXTENDED

403

B REG

8 - R [10],OPB

I SIGN

B~R100PB

.IRotate BREG left 8 places
.IDeposit B in 403

EXTENDED

403

SHIFT 8 TIMES

t_____. . ~DATOB
.

L--_ _4_o_3_ _....

'1 -, 217

Figure 8-10 Byte Format for Shifting Instructions

The 16-word by 16-bit organization of the SPM provides 16 storage registers that are utilized as shown in Table 8-3.

Table 8-3
Register Utilization in SPM
Register Number

Designation

RO-RS
R6
R7
R8 and R9
RlO
R11
R12
R13-R16
R17

General Purpose
Processor Stack Pointer
Program Counter
Unused
Source Operand Storage
Destination Operand Storage
Interrupt Vector
Unused
Load Address Storage

The SPM data inputs are the AMUX outputs: DPA AMUX 00 H-03 H, DPB AMUX 04 H-07 H, DPC AMUX 08 H-11
H, and DPD AMUX 12 H-1S H. The SPM outputs are the 16 ALEG bits (ALEG 00-15) which are sent to the A-word
input of the ALU.
The SPM address line input signals are generated by the scratch pad address multiplexers (SPAM) as shown in Table

8-4.

8-17

3 ENABLE SIGNALS
TO SELECT SPM
OPERAT I NG MODE

CONG ENAB SPL L

TO A-WORD
11 PUT OF
All . 16 BITS
TOTAL

CONG ENAB SPR L
DPA SP WRITE L

oPA AMUX
o OH-03H
-"
[

...

;r,

TO ALU
E018

7489
SPM
EOIO

Mi---

...

DPB AMUX
04H-07H
to..

c::::::::...

7489
SPM
E012

TO ALU
EOl9
to..

CONB SPA 03 H
CONB SPA 02 H

...
0

--V

TO ALU
EO 20
7489
SPM
EOl4

[

...

ALEG
08L -11 L

A3 A2 AI AO

1I
1

DPD AMUX
12H-15H

..}

ALEG
04L-07L

ALEG
00L-03L

90
......

DPC AMUX
08H-IIH

...}

~
E

J\.

...

TO ALU
E022

7489
SPM
EOl6

~
ALEG ..
12L-15L

A3 A2 At AO

CONB SPA 01 H
CONB SPA 00 H

4 ADDRESS LINES
TO SELECT
SPM WORD

7489 FUNCTION TABLE
ENABLES
E

OPERATION
WRITE

CONDITION OF OUTPUTS
COMPLEMENT OF DATA INPUTS

READ

COMPLEMENT OF SELECTED WORD

INHIBIT STORAGE

COMPLEMENT OF DATA INPUTS

EO NOTHiIII"---- -HIGH
------_._._---

11-1563

Figure 8-11 Block Diagram and Function Table for Scratch Pad Memory

Table 8-4
SPM Address Line Signals
Source

Signal
CONB
CONB
CONB
CONB

SPA MUX EOS6
SPA MUX EOS6
SPA MUX EOS7
SPA MUX EOS7

SPAOOH
SPA 01 H
SPA 02H
SPA 03 H

(print CONB)
(print CONB)
(print CONB)
(print CONB)

Two enable inputs control the SPM mode of operation: input W (memory enable) and input E (write enable). The
SPM function table is shown in Figure 8-11. Signal DPA SP WRITE L is the W-input. There are two E-input signals:
CONG ENAB SPR L for the low byte (bits 00-07), and CONG ENAB SPL L for the high byte (bits 08-15). This
allows word or byte operations to be performed on the SPM.
8.3.9 Scratch Pad Memory Address Multiplexer
The SP AM generates the four address signals that select the desired SPM word. The SPAM consists of two Type
74153 Dual 4-Line-to-1 Line Data Multiplexers. The SPAM is shown in print CONB (EOS6 and EOS7). Each of the
four 4-line-to-1-line multiplexers (two per 74153 package) has a common strobe input signal (CONH RUN GND L)
and common address input signals (CONG SPA MUX 00 Hand CONG SPA MUX 01 H). Four data input sources are
used and they are connected so that when the SPAM is addressed and strobed, it generates one 4-bit output, selected
from one of the four sources. Table 8-5 lists the sources of the SPAM input data that are a function of the state of
the processor.

Table 8-5
SPAM Input Data Sources

Function

SPAM
Input

Source
Print

Source

,
Source Operand Register
Selection

Instruction Register
Bits 06-08

DPF

Destination Operand
Register Selection

Instruction Register
Bits 00-02

1)PF

General Purpose
Register Selection
From Console

Bus Address Register
Bits 00-03

CONA

Control Store ROM
Bits 12, 18,21,22

CONG

The SPAM address inputs are Sl (signal CONG SPA MUX 01 H) and SO (signal CONG SPA MUX 00 H). They are
generated by CS ROM 23-A13A2 (E106).

8-19

The data input selected is a function of the states of SI and SO as shown below.
Address Inputs
SI

L
L
H
H

L
H
L
H

Output
A
B
C
D

8.3.10 Processor Status Word Register
The processor status word register (PSW) contains information on the current priority of the processor, the result of
the previous operation, and indicates a processor trap during debugging. The PSW bit assignments and use are shown
in Table 8-6.

Table 8-6
Processor Status Word Bit Assignments
Bit

Name

07-05

Priority

Set the processor priority.

Trace

When set, the processor traps the trace trap vector. Used for program debugging.

Set when the result of the last data manipulation is negative.

Set when the result of the last data manipulation is zero.

Set when the result of the last data manipulation produces an overflow.

Set when the result of the last data manipulation produces a carry from the most
significant bit.

Use

The PSW is loaded as a result of instruction execution, program traps, I/O interrupts, and returns to main-line code.
In the case of a program trap, interrupt, or return, the PSW is loaded with the second word of the vector from the
Unibus data lines via the AMUX. Otherwise, the PSW is loaded through a network of multiplexers and combinational
logic that is controlled by the particular instruction being executed.
The PSW is an 8-bit flip-flop register (print DPE). The condition code bits (N, Z, V, and C) are stored in 7474 D-type
flip-flops (E050 and E051). The priority bits and T-bit are stored in a 74175 quad D-type flip-flop called PSW 7:4
(E042). The output of the T-bit flip-flop is sent to another flip-flop (T DEL) which is used as the trap flag.
The input source for the condition code bits is the output of the condition code multiplexer (CC MUX). The CC
MUX (E052 print DPE) is a Type 74157 Quad 2-Line-to-l-Line Multiplexer. One of the two 4-bit inputs is selected
by the states of the strobe (E) and select (S) inputs. When E is low and S is high, the B-input is selected to the
D-inputs of the condition code flip-flops (NEG, ZERO, VBIT, and COUT). The B-input consists of AMUX outputs

8-20

DPA AMUX 00 H-03 H. When E and S are both low, the A-input is selected. The A-input consists of signals from the
ROT CC MUX (E056 print DPE) and the C and V BIT ROM (E082 print DPF). These devices are part of the logic
used in setting the condition codes as a function of instruction execution and are described in detail in subsequent
paragraphs.
The input source for the priority bits (PSW 05-07) consists of AMUX outputs DPB AMUX 05 H-07 H which are sent
to D-inputs Dl, D2, and D3 of E042. Signal DPB AMUX 04 H is sent to D-input DO of E042 as the source of the
T-bit.
The PSW is loaded when the flip-flops are clocked. Each bit is clocked by the processor clock signal CON] PROC
CLOCK H which is free running as long as the clock is not inhibited. Clock control is provided by gating other
signals with CON] PROC CLOCK H. These Signals and the PSW bits that they control are shown below.
Control Signal

PSW Bit

CONG LOAD PSW L
DPF AUX DEL (1) L
DPF C CLK DEL (1) L

N, Z, V, C, T and Priority
N, Z, and V
C

The logic that determines the condition code bits (C, V, N, and Z) and loads them in the PSW register is shown in
prints DPE and DPF.
This discussion covers the determination and loading of the condition code bits as a result of instruction execution.
Two categories of instructions are discussed: normal arithmetic instructions, and rotate and shift instructions.
Before discussing specific examples in these categories, the functional units of the logic are described briefly.

CCMUX
As mentioned previously, the condition code bits are loaded from the outputs of the CC MUX (E052, print DPE).
The CC MUX is a Type 74157 Quad 2-Line-to-1-Line Multiplexer. Only the 4-bit A-input is used during instruction
execution. The A-input is selected when the E-input and the S-input are both low. The E-input is the strobe and
must be low to enable the multiplexer. It is connected to CONH PROC INIT H from the power fail circuit which is
low when power is up. The S-input selects the input (A or B) and is connected to DPF AUX DEL (1) L which is
control store bit CONF AUX CONTROL L that has been stored in flip-flop E054 (print DPF). Signal CONF AUX
CONTROL L is the AUX field (bit 24) of the control store word. It is generated by CS ROM E094 (print CONF)
and enables the auxiliary ALU control when it is low. This is the desired condition to select input A of the CC MUX.
C and V BIT ROM
The C and V BIT ROM (E082, print DPF) calculates the values of the C-bit and V-bit for normal arithmetic
instructions. The DPF SET COUT H output is modified by 3-input NAND gate E067 only during the execution of a
subtract instruction. For shift and rotate instructions, the C-bit is determined by the two NAND gates wire-ORed to
the DPF SET COUT L output of the C and V BIT ROM. For these instructions, the V-bit is determined by the
exclusive-OR gate and NAND gate connected to the DPF SET V L output of the C and V BIT ROM. The five inputs
to the C and V BIT ROM are delayed the equivalent of one clock pulse by being sent to hex flip-flops E054 and
E093 before being sent to the ROM. The delay is required to allow time for the C and V BIT ROM to settle. These
input Signals come from three sources: the B-Ieg, ROT CC MUX (E068), and SOP AUX CTL ROM (E068).

ROTCCMUX
The ROT CC MUX (E056, print DPE) determines the value of the N-bit and Z-bit. It is a Type 74153 Dual
4-Line-to-l-Line Multiplexer. The outputs are DPE NEG H (for the N-bit) and DPE SET Z H (for the Z-bit). These
outputs are delayed by flip-flop E054 before being applied to the CC MUX whose outputs condition the D-inputs of
NEG flip-flop E052 and ZERO flip-flop E050. The inputs of both sections of the ROT CC MUX are a function of
the category of instruction being executed.

8-21

Instruction
Category

Input
Designation

Rotate Byte
Byte (not Rotate)
Rotate (not Byte)
Not Byte or Rotate

BR
BR
BR
BR

The enabling or strobe (STB1 and STB2) inputs for the ROT ec MUX are both connected to ground which enables
the multiplexer. Inputs SI and S2 are the address inputs and are c~mmon to both sections. The data inputs are
selected by the states of SI and S2 according to the following truth table.
Address Inputs

L
L
H
H

L
H
L
H

Selected
Input
BR
BR

BR
BR

Input SI is connected to DPG BYTE H, which is an inverted output of IR decoding ROM E069. Input SO is
connected to DPF ROT ATE H, which is an inverted output of SOP AUX eTL ROM E068. This signal is a function
of the instruction register output.
The data signal inputs to the ROT ce MUX are shown below.

ROT CC MUX Input Signals
For DPE NEG H Output Section
Pin

Desig

13
11

BR
BR

12
10

BR
BR

ROT CC MUX Input Signals
For DPE SET Z H Output Section
Signal

Signal

Desig

DPE ROT NEG H

04
06

BR
BR

DPA 0-7

Output of gate
E055 pin 10 (zero
detector for BLEG
bits 01-06)

Output of gate E055
pin 13 (zero detector
for BLEG bits 01-14

)

DPBAMUX07H
DPDAMUX 15H

8-22

= OB
= OFf

DPE 0-15

ROTMUX2
The ROT MUX 2 (E049, print DPE) generates outputs which are used in computing the
arithmetic shift instruc,:ioas ASL and ASR, and rotate instructions ROL and ROR. It is
4-Line-to-l-Line Multiplexer. Ou:put ))PE ROT COUT H is sent to flip-flop E093 and then to
DPF). Output DPE ROT NEG H is sent to input BR (pin 11) and input BR (pin 13) of the
inputs of both sections 0::' tfle ROT MUX 2 are a function of the specific type of instruction
instructions are listcd Dclow.

Instruction

Input

Arithmetic Shift Left
Arithmctic Shift Right
;:Zotate Left
Rotate Right

ASL
ASR
ROL
ROR

C-bit and N-bI! for
a Type 74153 Duai
the C-bi~ logic (print
ROT CC MUX. Inc
bell1g executcd. The

The enabling inputs (STBI and ~';TBO) are both connected to ground which enables the multiplexer. The data inputs
are selected by the states of address inpms Sl and SO according to the following truth table.

Address Inputs
SI

L
L
H

Selected
Inputs

ROR
ASR
ROL
ASL

L
H

The address inputs are connected to DPA ALU SI H (input S1) and DPA ALU SO H (input SO) which are inverted
and buffered control store bits 28 and 29 from CS ROM EI04 (print CONF). The actual signals are CONF ALU Sl
Land CONF ALU SO L which are part of the ALU field that picks the function to be performed by the ALU. These
signals can be used by ROT MUX 1 and ROT MUX 2 because the ALU and these multiplexers are never used
simultaneously. The data signal inputs to the ROT MUX 2 are shown below.

ROT MUX 2 Input Signals For
DPE ROT NEG H Output Section

ROT MUX 2 Input Signals For
DPE ROT COUT H Output Section
Pin

Desig
~~-

Signal

ASL

Desig

ASL

ROL

ASR

DPD BREG 15 (1) H

ROR

DPE COUT (1) H

} DPE L SHIFT SIGN II

} DPD BREG 15 (I)"
12

ROL

ASR

Signal

f-.----

} DPA BREG 00 (I) H
10

ROR

8-23

ROTMUX 1
The ROT MUX 1 (E048, print DPE) generates the enabling signal for the rotate and shift zero-detection logic and
generates a serial input signal for the BREG. It is a Type 74153 DuaI4-Line-to-l-Line Multiplexer. Output Fo (pin
07) is the enabling signal for the BLEG zero-detection gates E029 and E031. Output DPE SERIAL SHIFT H is a
serial input signal for the BREG. It is also sent to the input of the BYTE MUX (E047, print DPE). The inputs to the
ROT MUX 1 are a function of ASL, ASR, ROL, and ROR instruction execution. This multiplexer uses the same
enabling signals and truth table as the ROT MUX 2. The data signal inputs to the ROT MUX 1 are shown below.

ROT MUX 1 Input Signals For
OPE SERIAL SHFT H Output Section

ROT MUX 1 Input Signals For Output
Section That Enables Gate E029

Oesig

Signal

Oesig

ASL

DPARUNGNDL

ASL

DPA BLEG 00 L

ROL

Output of gate EOSS
pin 04 (BROO'COUT)

05
06

ASR
ROR

DPD BLEG 15 L
Output of gate EOSS
pin 01 (BRIS-COUT)

}
10

ROR

ASR

OPE COUT (1) II

DPD BREG 15 (1) H

Signal

The following example covers the determination of the condition code bits for the negate (NEG) instruction. When
the NEG instruction is executed, the disposition of the condition code bits is as follows:
C ~ cleared if the result is 0; set otherwise
V ~ set if the result is 100000; cleared otherwise
Z ~ set if the result is 0; cleared otherwise
N ~ set if the result is less than 0; cleared otherwise
The condition code bits depend on the result produced by the instruction. For this example, assume that the result
is 001000 8 ,
The C-bit should be set because the result is not zero, and the V-bit should be cleared because the result is not
100000 8 , The C and V BIT ROM calculates the C and V bits: DPF SET COUT H is high and DPF SET V H is low.
Verification of these Signals is accomplished by checking the outputs of the C and V BIT ROM back to their sources,
which are the associated ROM maps.
The N-bit should be cleared because the result is greater than zero. The NEG instruction is not a byte and not a
rotate instruction: therefore, the BR input of the ROT CC MUX is selected, which is DPD AMUX 15 H for the top
section of this dual multiplexer. This signal is low so ROT CC MUX output DPE NEG H is low. This signal is delayed
by flip-flop EOS4 and its output is sent to the CC MUX to load a 0 into the NEG flip-flop EOSI (N-bit is cleared).
The Z-bit should be cleared because the result is not zero.
The BR input of the ROT CC MUX is selected: DPE 0-15 = 0 H for the bottom section of the multiplexer. This
signal is low because all bits of the result are not zero; therefore, output DPE SET Z H is low. This output is delayed
by flip-flop EOS4 and its output is sent· to the CC MUX to load a 0 into the ZERO flip-flop EOSI (l-bit cleared).
The following example covers the determination of the condition bits for the arithmetic shift-right (ASR)
instruction. This instruction requires the use of some additional PSW logic.

8-24

When the ASR instruction is executed, the disposition of the condition code bits is as follows.
C - loaded from the low order bit (00)

loaded with the exclusive·OR of the N-bit and the C-bit at completion of the shift operation.

Z - set if the result is 0; cleared otherwise.
N - set if the result is less than 0; cleared otherwise.
The condition code bits depend on the result produced by the instruction. For this example, assume that the result
is 000002 8 ,
For this instruction, input ASR is selected for both sections of ROT MUX 1 and ROT MUX 2. Input BR is selected
for ROT CC MUX because the ASR instruction is not a byte but it is considered to be a rotate instruction.
First, consider the C-bit, which is loaded from the low order bit. The output of the top section of ROT MUX 2 is
DPE ROT COUT H. In this example, the selected input is DPD BREG 00 (1) H, which is low because bit 00 of the
result is low: this makes output DPE ROT COUT H low. It is sent to flip-flop E093 and then on to the C-bit logic
(print DPF) as DPF ROT C DEL (1) H. For the ASR instruction, C and V BIT TOM E082 is disabled by holding its
enabling Signal high.
Determination of the C-bit is handled by NAND gates E092 (2), E067 and exclusive-OR gate E08 (Figure 8-12). The
two E092 gates are wire-ORed with the DPF SET COUT L output of the C and V BIT ROM. For the ASR
instruction, DPF SET C DEL (1) H is low and is sent to both inputs of one of the E092 gates. This produces a high
at E092 pin 08 which is one gate of the wired-OR connection. Signal DPF ROT DEL (1) H is sent to one input (pin
12) of the other E092 gate. It is high, which means that the output of this gate (pin 11) is controlled by signal DPF
ROT C DEL (1) H to input pin 13. This signal is low so the wired-OR connection (DPF SET COUT L) is high. Signal
DPF :::r:T COUT L is sent to pin 10 of exclusive-OR gate E08l. The other input (pin 09) of this gate is high because
a subtract instruction is not being executed. The exclusive-OR output is low. This is signal DPF SET COUT H and it
is sent to the CC MUX to reset COUT flip-flop EOSl. Thus, the C-bit is loaded with a 0 from the low order bit (00).

Signal high for
ASR instruction

Signa I low for
ASR instruction

Wire - ORed connection.
Gates control C bit
when ROM disabled.
DPF ROT DEL (1) H

-----'=-r-"'I

DPF ROT C DEL (1)H

---1....___ ~

DPF SET C DEL (1)H

--.....,:-=-f

DPF IR 15 (1) H
DPF IR 14(1)H
DPF IR 13 (1) H

Detects SUB
instruction.
Output high
when not SUB

r------,06
1-'-"------'-''-1.

E082

Cay
BIT
ROM

Signal high during
ASR instruction to
disable ROM

07 DPF SET V L

ENB

DPF SET V H

DPF DISAB VROM DEL (1) H - - - - - '

E>elusive- OR
of Cand N bits
DPF ROT DEL(1)H - - - - - '
Signal high for
ASR instruction

Figure 8-12 Logic For Determining C and V Bits
(Example Shown for .ASR Instruction)
8-25

11-'565

Next, consider the N-bit, which is cleared because the result is greater than 0 (bit 15 is a 0). Output f 1 of ROT CC
MUX is DPE NEG H. In this example, the selected input (BR) is DPE ROT NEG H. This is output fo of ROT MUX
2, and in this case, the selected input (ASR) is DPD BREG 15 (l) H which is low because bit 15 of the result is low.
Output fo, which is DPE ROT NEG H, is low and as a result, DPE NEG H from the ROT CC MUX is low. This signal
is delayed by flip-flop E054 and its output [DPF NEG DEL (l) H] is sent to the CC MUX to reset NEG flip-flop
EOSI (N-bit cleared). Signal DPF NEG DEL (1) H is also sent to the logic that determines the V-bit.
Next, consider the V-bit, which is the exclusive-OR of the N-bit and the C-bit. As mentioned, the C and V BIT ROM
is disabled during the execution of the ASR instruction. Determination of the V-bit is handled by exclusive-OR gate
E081, NAND gate E092 and inverter E073. The exclusive-OR gat~ performs the exclusive-OR function of the Nand
C bits and its output is connected to the DPF SET V L output of the C and V BIT ROM. This output is inverted by
E073 to produce DPF SET V H. The inputs to exclusive-OR gate E081 are DPF ROT C DEL (1) Hand DPF NEG
DEL (1) H which are both low (refer to previous discussions of C-bit and N.bit). The output (pin 03) of the
exclusive-OR gate is low and is sent to pin 05 of NAND gate E092. The other input of this gate is DPF ROT DEL (l)
H and it is high during execution of the ASR instruction. The output of this gate is high and it is inverted by E073
to produce DPF SET V H which is low. This signal is sent to the CC MUX to reset V BIT flip-flop EOSl. Thus, the
V-bit is loaded with the exclusive-OR of the C and N bits, which is zero.
Finally, consider the Z-bit, which is cleared because the result is not zero. Output fo of ROT CC MUX is DPE SET Z
H. In this example, the selected input (BR) comes from gate E055 pin 13, which is an output of the rotate and shift
zero-detection logic. Gate E055 produces a low because the enabling signal for this logic is not asserted. The enabling
signal comes from output fo of ROT MUX 1 that selects DPD BLEG 15 L for an ASR instruction. In this case, bit
15 is low; therefore, DPE SET Z H is low. This signal is delayed by flip-flop EOS4 and its output is sent to the CC
MUX to reset ZERO flip-flop EOSI. Thus the Z-bit is cleared.
8.3.11 Constants Generator
The constants generator consists of a single 32-word by 8-bit ROM attached to the A-leg of the ALU. It is identified
as E02S CONSTANTS (part number 23·AOl AI) and is shown on print DPB. The outputs of the constants generator
are addresses of trap vectors and the complement of the address of the console switch register. Each output is an
8-bit word that is sent to the low order byte of the ALU A-leg. The eight bits are identified as DPB ALEG 00 L-07
L.
Four of the five inputs to the constants generator are CONB SPA 00 H-03 H which are generated by the SPAM
(EOS6 and EOS7, print CONB). It is possible for both the constants generator and the SPM to use these signals
because they are never used Simultaneously. The fifth input is CONG SP WRITE H, which is also used by the SPM. It
is an inverted output of control store ROM E09S (part number 23-A07A2) in print CONGo
The enabling input for the constants generator is CONE ALLOW CONSTANTS L which is an output of the BUT
DECODE multiplexer E078 (print CONE). This multiplexer is driven by control store ROM ElOS (part number
23-AI2A2) in print CONGo
The contents of the constants generator are shown in ROM listing K-RL-M7260-O-8. sheet 2.
8.3.12 Console Switch Register
The settings of the 16 switches in the console Switch Register are transmitted in parallel via a cable to the Berg
connector on the M7260 Data Paths Module. On the console (print 5409766-0-1, sheet 3), these signals are
identified as SW 00 (1) H-SWIS (1) H. On the M7260 module, these signals are identified as EXTRA SWITCH REG
00 H-IS H.

8-26

These signals enter the data path via four Type 74HOI Quad 2-Input NAND Gates as shown below.
Bits

Gate

00-03
04-07
08-11
12-15

E028
E024
E021
E023

DPA
DPB
DPC
DPD

The gates are enabled by DPA ENAB SWITCH REG H, which is the output of 7437 NAND buffer gate E083 (print
DPA). The input to this gate is CONA ENAB SWITCH REG L, which is an output of DATI ADDRS DECODE ROM
E069 (part number 23-A09Al) in print CONA.
8.3.13 Console Multiplexer
The console multiplexer scans the 16 bits in the BLEG, serializes the information, and transmits it via a cable to the
console Buffer Register. It is a 74150 data/selector multiplexer and is identified as E30 CONSOLE MUX (print
DPE). Figure 8-13 is a block diagram of the console multiplexer and its input source.

DPA RUN GND L
DPD BLEG 12L-15L
74S158
E040
BLEG
MUX

DPD AMUX 12H -15H
From BREG E038

DPC AMUX 8H-l1 H
From BREG E035

74S158
E039
BLEG
MUX

STB

DPC BLEG 8L-l1 L

...

74150

74HOI
E037
NAND
GATES

DP8 AMUX 4H-7H
From BREG E045

DPA AMUX OH-3H
From BREG E044

74HOI
E036
NAND
GATES

DPB BLEG 4L-7L

CONSOLE
MUX

SERIAL To Console
DATA
Buffer
Register

DPA BLEG DL-3L

SO
MSB

"'Inverted {EXTA SCAN ADDRS 01 (1) H
Outputs EXTA SCAN ADDRS 02 (1) H
From

Console
Coun ter

EXTA SCAN ADDRS 04(1) H - - - . . J
EXT A SCAN ADDRS 08 (1) H - - - - - - '

"Via Cable Connection

11-1561

Figure 8-13 Console Multiplexer Block Diagram

The CONSOLE MUX (E30 print DPE) selects one of sixteen inputs in accordance with the states of the four data
select lines (SO-S3). A low strobe signal enables the selected input to the output in the inverter state.
The high byte input (D8-D15) of the CONSOLE MUX comes from the output of the BLEG multiplexer. These
signals are DPC BLEG 8-11 and DPD BLEG 12-15 L. The low byte input (DO-D7) comes from the open-collector
NAND gates (E036 and E037, prints DPA and DPB) that are driven by the B register. The four data select inputs
(SO-S3) are the inverted outputs of the console counter (E6 print 5409766-0-1, sheet 3). These signals are EXT A
SCAN ADDRS 01 (1) H, -02 (1) H, -04 (1) H, and -08 (1) H. They are decoded as a BCD number with 08 (1) H

8-27

being the most significant digit. These lines select the input lines on an equivalent basis; for example, a decoded
decimal 6 selects input D6. The strobe signal DPA RUN GND L is held low to enable the selected input to the
output.
8.4 INSTRUCTION DECODING
8.4.1 Introduction
Two methods are used to control instruction decoding. One uses microroutine selection and the other uses auxiliary
ALU control. Dual control is required because of the large number of instructions that require source/destination
calculations. Auxiliary ALU control is evoked whenever the microcode executes the action B+-RIO OP B as a result
of a specific instruction.
There are two prerequisites to a thorough understanding of the instruction decoding procedure. One is a knowledge
of the microbranching process (Chapter 9) and the other is a knowledge of the PDP-II instruction format (Chapter
6).
Certain facts concerning the PDP-II instruction set are listed below.
a.

In general, the PDP-II operation code is variable from 4 to 16 bits.

Instructions are decoded from the most significant part of the word towards the least significant part of
the word beginning with the most significant four bits.

There are a number of instructions that require two address calculations and a larger number that require
only one address calculation. There are also a number of instructions that require address calculations,
but do not operate on data.

All OP codes that are not implemented in the KDII-B processor must be trapped.

There are illegal combinations of instructions and address modes that must be trapped.

There exists a list of exceptions in the execution of instructions having to do with both the treatment of
data and the setting of condition codes in the program status word.

8.4.2 Double Operand Instructions
Double operand instructions are decoded by ROM E066 (print DPG). Four inputs to E066 are DPF IR 12 (1) H DPF IR 15 (1) H; these are outputs of the Instruction Register (E058, print DPF) which represent the OP code of a
double operand instruction. The fifth input is CONE BUI' DESTINATION L which is an output of the E078 BUI'
DECODE demultiplexer. The inputs to E078 are CONG BUI' 00 L - CONG BUI' 03 L which are the four bits of the
BUI' field of the control store word. When a double operand instruction is decoded, E066 output signal DPG CAL
SOURCE L is asserted. This signal is ANDed with CONE BUI' IR DECODE L at gate E079 to produce signal CONF
MPC 07 L at pin 11 of quad NAND gate EOn. The output of gate E079 is ANDed with DPF IR 09 (1) H, DPF IR
10 (1) H, and DPF IR 11 (1) H to produce CONF MPC 01 L, CONF MPC 02 L, and CONF MPC 03 L at the three
remaining sections of quad NAND gate EOn (lower center section of print DPG). These four signals represent four
bits of the 8-bit NXT field of the control store word and cause a microcode branch.
ROM E066 also generates DPG CMP + BIT L which indicates that the instruction does not modify the destination
operand. Output signals DPG MOVE Land DPG BYTE L are used in the microbranch logic (print CONE). Table 8-7
explains the use of these Signals.

8-28

Table 8-7
Effect of E066 Outputs DPG CMP+BIT L,
DPG MOVE L, and DPG BYTE L

Instruction

E066 Output
Signal

Effect

Remarks

CMP

DPG CMP+BIT L

Set condition
codes

Destination is not modified; therefore, DATIP is not
required.

BIT

DPG CMP+BIT L

Set condition
codes

Destination is not modified; therefore, DATIP is not
required.

MOVB

DPGMOVL
DPG BYTE L

If the destination is a register, (i.e., destination mode
0) the result is sign extended; i.e., the sign of the low
order byte is extended through the upper byte.

(ANY)
BYTE

DPGBYTEL

Bit 0 of the address word must be used in
determining which microroutine to use position
source and destination data. See Chapter 9, for
details.

For a binary operand instruction, the source operand is stored in RIO and the destination operand is temporarily
stored in the B register. Then the control step B +- RIO OP B is performed. The ALU can perform the operation
A-leg minus B-leg, but not the converse. The CMP instruction requires the operation source minus destination, which
is equivalent to A-leg minus B-leg; however, the SUB instruction requires the operation destination minus source.
This is accomplished by storing the complement of the source in RIO for the SUB instruction only. The signal
CONE BUT DESTINATION L is an input to E066. The microprogram issues CONE BUT DESTINATION L,
whenever the SOURCE operand is stored in RIO. If the current instruction is a SUB, E066 issues the signals DPG
DIS ALU S BITS H, CONF ALU SO L, and CONF ALU S2 L. This causes the complement of the BREG to be
sorted in RIO. When control step B +- RIO OP B is performed for the subtract instruction, the ALU operation is
A-leg plus B-leg plus 1, which is equivalent to destination minus source.
When the microprogram has completed the source calculation and retrieved the source operand for a binary operand
instruction, it generates the signal CONE BUT DESTINATION L. This signal is ORed and inverted to produce CONE
BUT DESTINATION H. The MOV, MOVB, CMP and BIT instructions are detected at the control steps listed below:
BitPattems

Instruction Class

Asserted Signals

(11) = (9) = (8) = 1 +
(10) = 0

Unary Potential TST

DPG CAL DEST L +
DPG 54 L

(10:08)=0+(11)=0

Branch

DPG CAL BRANCH L

(15:08) = 0

Other

DPG ODD BYTE = OL

Two instructions in the other class require destination calculations: JMP and SWAB. These instructions are
detected by ROM E074 shown in the lower left-hand corner of DPG. Standard unary instructions that affect or test
the destination (with the exception of SWAB) are treated as binary instructions; i.e., the instruction is fetched, the
operand is fetched, the operation is performed, and the operand is returned. The logic that decodes the operation for
B +- RIO OP B is shown on print DPF. For unary operand instructions, the destination operand is copied into both
RIO and B.

8-29

8.4.3 Branch On Unary
11Iere are three formats of instructions that require destination address calculations. The majority of the microcode
destination routines are shared by all of the instructions that have destination fields. ROM E071, shown in upper
right-hand corner of print DPG, is used to differentiate between the various instructions that use the microcode
destination routines.
E071 is also used to detect illegal instruction combinations, which are defined as JMP or JSR and used with
destination mode O. The microcode flow chart shows that in microstep DO-2 a test is made for unary and illegal
instructions by asserting the signal CONE BUT UNARY L. CONE BUT UNARY L produces the signal CONE ENAB
UNARY L, which enables E07I (print DPG) to cause a microprogram branch. At other points in the microprogram
such as D2-3, a test is made for a legal JSR or JMP instruction by the assertion of the signal CONE JMP + JSR L.
The asserted signal CONE JMP + JSR L alters the input to E071 such that microroutines for legal JSR and JMP
instructions are used. Signal CONE JMP + JSR L also causes the generation of the signal CONE ENAB UNARY L,
which enables E071.
The effect of ROM E07I (part number 23-AIOA1) is determined by observing its data pattern shown in drawing
K-RL-M7260-O-8, sheet 9.
8.4.4 PDP-II Branch Instruction
PDP-II conditioned branch instructions are completely decoded by ,E059, shown on print DPG. E059 is enabled by
the Signal DPG CAL BRANCH L, which is asserted by E069 according to a previously discussed algorithm. IR (I 5)
and IR (I0:08) along with the condition codes N, Z, V,. and C completely determine the branch instruction
disposition. The offset of a branch instruction is sign-extended in microstep F-5 and shifted left one place in
microstep B-1. All successful branch instructions are interpreted by the microroutine that begins in B-1, while all
unsuccessful branch instructions are interpreted by the microroutine that begins in B2-1.
8.4.5 Operate Instructions
Operate instructions and instructions that set and clear condition codes are decoded by E074 and E064. NOPS, set
condition code instructions, and clear condition code instructions all proceed from step F-5 to step CCM-I in the
microprogram. At step CCM-2, the microprogram performs a BUT DESTINATION to examine IR (4). Set condition
code instructions and the NOP-260 proceed with step SC-l while clear condition code instructions and the NOP-240
proceed with step CC-1. Also in step CCM-l, the B register is loaded with the contents of the instruction ANDed
with 17 8 , This procedure zeroes all but the least Significant four bits of the instruction copy contained in the B
register. Remember that the instruction is loaded into both the IR and B register in step F-4. If the instruction is a
SET COND CODE type, the operation is PSW ~ B or PSW in step SC-l. Similarly, for clear condition code
instructions, PSW ~ B and not PSW is performed in step CC-!. Even though the entire PSW is reloaded, only the
least significant four bits are effected by the sequence just described.
Other operate instructions such as WAIT, RTI, and HALT are decoded completely when BUT IR DECODE is issued
during micro step F-5.
8.4.6 Auxiliary ALU Control
The auxiliary ALU control consists of the ROMs E053, E061, and E068 shown on print DPF. These ROMs
determine the operation to be performed whenever the microcode executes the action B ~RlO OP B. E053 decodes
binary operand instructions while the other two ROMs decode unary operand instructions. Table 8-8 shows the
auxiliary control outputs for binary and unary instructions.

8-30

Table 8-8
Auxiliary Control for Binary and Unary Instructions
Condition Codes
Inst.

NandZ

ALU
Function

CIN

MaY (B)

Load

Cleared

Not Effected

A Logical

Load

CMP (B)

Load

Load like SUBTRACT

A - B-1

Load

BIT (B)

Load

Oeared

Not Effected

A+B

Load

BIC (B)

Load

Oeared

Not Effected

-A+B

Load

BIS (B)

Load

Cleared

Not Effected

Load

ADD

Load

Set if OP's same sign
and result different.

Set if carry out

A plus B

Load

SUB

Load

+-(-)=- )
Set
-(-)(+)=+

Set if Carry

A plus B

Load

CLR(B)

Load

Oeared (like ADD)

Clear

Load

COM (B)

Load

Oeared

Set

-B Logical

Load

INC (B)

Load

Set if dst held 100000
before OP

Not Effected

A,A.

Load

NEG (B)

Load

Set if result is 100000

Oeared if result is 0;
set otherwise

A - B-1

Load

ADC (B)

Load

Set if dst was 077777
and C = 1.

Set if dst was 177777
and C = 1.

A Arithmetic

Load

SBC (B)

Load

Set if dst was 100000.

Oeared if dst was 0
and C = 1; set otherwise.

A-B

-C

TST (B)

Load

Oeared

A Logical

ROR(B)

Z +- (C:01)
N+-C

NEllC

(0)

Shift Right

ROL(B)

Z (14:C)
N +- (14)

NEllC

(15)
B (7)

Shift Left

ASR(B)

Z+-(15:01)
N+-N

NEllC

C +- (15)

Shift Right

ASL(B)

Z +- (14:01)
N +- (14)

C +- (15)

Shift Left

Load

8.S PROCESSOR CLOCK
The KDII-B processor clock is shown in print CONJ. A single astable oscillator is used to generate a pulse train to
which the entire processor is synchronized. Since it is a fully clocked processor, events that result in the alteration of
storage registers occur only on a defined edge of the processor clock pulse.

8-31

The logic diagram for the processor clock is shown in print CON]. A timing diagram is shown in Figure 8-14. NAND
Schmitt trigger EOI9 is connected as an astable multivibrator (oscillator). It does not require a trigger and is free
running as soon as +5V is applied to its input via resistor RI. The period of the oscillator pulse output should be set
for 150 ns. Adjustable resistor RIO is used to set the period. The oscillator can be disabled by a low signal from
NAND gate E13 pin 13. This low signal is asserted during the time that a ~nibus transaction is in process. The
processor clock is disabled during this time. The oscillator output is sent to one input of 2-input NAND gate E027.
The other input (pin 13) is held high by +5V via resistor R3. The oscillator pulses are inverted by E027 and are sent
to the triggering input of one-shot E009. During maintenance with the KMII Maintenance Module installed, gate
E027 allows the processor clock to be single stepped. The oscillator input is connected to +5V via Rl and to pin
FVl on the M7261 module. This input is grounded by the maintenance module to disable the oscillator. Input pin
13 on gate E027 is connected to +5V via R3 and to pin FU2 on the M7261. A switch on the maintenance module
grounds this line (CON] S CLK ON L) to provide a positive transition at the output of E027 to trigger the one-shot.
This action provides a single processor clock pulse.

I+- 150ns --I
Inverted Osclliator Output
E027 Pin 11

(2) ~
--l

I-Output of One-Shot
E 009 Pin 10

1--40-60ns
Inverted to Give CONJ BC CLOCK
L Double Inverted to Give CONJ
BC CLOCK H

~150ns---+\

0~U I

O-Output of One-Shot
E009 Pin 09(Clocks E044)

I-Output of Flip Flop
E044 Pin 05

0LJ

/""
..f - - - -

0.0.

u u

I-

L--_ _

300ns

I nverted to Give CONJ ALLOW
~

PC L

-----.j_/

CONJ UNG PROC CLOCK L
Inverted to Give CONJ UNG
PROC CLOCK H

and CONC CKOFF (1) Lore ANDed to give CONJ PROC CLOCK L
which is inverted to Qive CONJ PROC CLOCK H.
When CONC CKOFF(1)L is Low.these clock
pulses are inhibited.
The period of clock pulses CONJ UNG PROC CLOCK L.- Hand
CONJ PROC CLOCK L.-H is reduced to 150ns when signal
CONF F SHIFT L is asserted.

11-1562

Figure 8-14 Processor Clock Timing Diagram

During normal operation, the oscillator output is fed to pin 12 of one-shot E009. The other input (pin 11) is held
high by CONI R5 H. This line is connected to +5V via resistor R5 (print CONI). With pin 11 high, a positive
transition at pin 12 triggers one-shot E009. A positive pulse is generated at output pin 10 and a negative pulse is
generated at output pin 9. These pulses are 40-60 ns wide. A pulse is initiated on every positive transition of the
inverted oscillator output (E027 pin 11). The positive pulse from the one-shot is sent to high speed NAND buffer
E054. The inverted pulse from the output (pin 08) of E054 is called CON] BC CLOCK L. This signal is inverted and
buffered by another E054 high speed NAND buffer whose output (pin 06) is called CON] BC CLOCK H. These two
clock signals have IS0-ns periods and are buffered to provide increased fanout capability.
The negative pulse from the one-shot is sent to the clock (C) input of flip-flop E044. The I-input of the flip-flop is
fed back to its D-input via 2-input NAND gate E045. Normally, the other input of this gate (CONF F SHFT L) is
high so the I-output is inverted before being fed back to D-input. The clear input (pin 01) and the preset input (pin
04) of the flip-flop are kept disabled by CON] R24 H, which is connected to +5V via resistor R24. This is a toggle
8-32

configuration and the flip-flop changes state on every positive transition of the clock pulse. The l-output of the
flip-flop represents a division by 2 of the oscillator output; i.e., a bipolar pulse train with a period of 300 ns. This
signal is sent to NAND gate E064 where it is inverted to generate CON J ALLOW PC L. The I-output of the flip-flop
is also sent to NAND gate E045 and high speed NAND buffer E055. At gate E045, the flip-flop l-output is ANDed
with the positive output of the one-shot to generate a 40-60 ns negative pulse every 300 ns that is called CONJ UNG
PROC CLOCK L. This signal is inverted by open-collector inverter E061 to produce CONJ UNG PROC CLOCK H.
At gate E055, the flip-flop I-output, the positive output of the one-shot, and signal CON CKOFF (1) L are ANDed
to generate another 40-60 ns negative pulse every 300 ns. This signal is called CONJ PROC CLOCK L and is buffered
to provide increased fanout capability. Signal CONJ PROC CLOCK L is inverted by high speed NAND buffer E055
to produce CONJ PROC CLOCK H. These clock signals are inhibited when CON CKOFF (1) L is low. This occurs
when the processor is awaiting the completion of a Unibus interrupt or a RESET instruction. Signal CONC CKOFF
(1) L is an output of CKOFF flip-flop E080 (print CONC) and is low when the flip-flop is set. This redefined
flip-flop is set when its D-input (CONG CKOFF L) is low. This signal is the CKO field of the control store word and
is generated by CS ROM E107 (print CONG).
As previously mentioned, the l-output of flip-flop E044 is sent to I-input of NAND gate E045. The other input is
CONF FSHFT L, which was previously identified as CONF SPARE L. It is generated by CS ROM E094 and is a field
of the control store word. Normally, this signal is high and flip-flop E044 performs its divide-by-2 function to
provide a 300-ns period for clock signals CONJ UNG PROC CLOCK Land H, and CONJ PROC CLOCK Land H.
During a non-processor request (NPR) transaction, the NPR latency time is reduced by speeding up the B register
shifting operations by decreasing the period of the CONJ PROC CLOCK Land H pulses from 300 ns to 150 ns. This
is accomplished by asserting CONF FSHFT L at the input to E045. When this signal is low, the D-input to flip-flop
E044 is always high so that the divide-by-2 function is not enabled. The periods of CONJ PROC CLOCK Land Hare
now the same as the period of the one-shot output which is 150 ns.
8.6 UNIBUS CONTROL
The Unibus control (BC) is found in prints CONC and CONCI, and the majority of Unibus drivers are found in print
CONDo The microprogram requests the BC to perform DATI, DATIP, DATa, and DATOB operations and to
retrieve interrupt vectors. At the request of peripherals attached to the Unibus, the BC arbitrates BRs and NPRs. The
BC is also responsible for detecting and causing a trap, whenever there is an attempt by the processor to address
non-existent memory or to access odd addresses illegally.
The BC operates in parallel with the DP. The microprogram may request a DATI and then perform other tasks, such
as incrementing R7, as long as the Bus Address Register is unchanged. The Unibus control proceeds with the DATI
until the slave sync signal (SSYN) is returned from the slave device. At this point, the BC waits for the microprogram
to set the CKOFF flip-flop shown on print CONC. This signal indicates that the microprogram is ready to accept
Unibus data. If the microprogram sets CKOFF before SSYN is received, the BC inhibits the oscillator until SSYN is
received or a Unibus timeout occurs.
8.6.1 DATI Timing
A DATI is used by the processor to retrieve data from devices attached to the Unibus. Figure 8-15 contains a timing
diagram of the Unibus control signals for a DATI bus operation. Signals BBSY, CO, Cl, and the address lines may be
set by the processor or bus master, whenever it is determined that the Unibus is free for use. The Unibus is free for
use by the processor when the follOwing equation is true:
BUS FREE = (-BBSy) ('"'-NPR) ("SACK)
Once BBSY, CO, Cl, and the address lines are asserted, the master device must wait at least 150 ns before issuing
MSYN. During this time, the address and control lines of the Unibus are settling, so that when MSYN is issued, there
will be no confusion regarding the device addressed or the direction of the data transfer. After MSYN is asserted, the
BC must wait until SSYN returns from the Unibus and CKOFF is asserted. This indicates that data is available on the

8-33

Unibus and the microprogram is ready to accept that data. Once the processor has strobed the data from the Unibus
into a storage element, normally the B register, the signal MSYN is not asserted. BBSY, Cl, CO, and the address are
maintained for 150 ns after MSYN is not asserted.

PROCESSOR ENABLES ADDRESS
AND CONTROL LINES HERE FOR
DATI(P)-FOR DATO (B). DATA IS
ALSO ENABLED HERE.

DATA STROBED HERE

-I

CONJ BC CLK H

I-

40n5

ADDRESS AND CONTROL
LINES REMOVED HERE.
DATA IS REMOVED IF BUS
OPERATION WAS DATO(B).

1--150n5

--!

'-,.,

JlL-,,-----,n nL_---InL_---Irl Ii
Jl'--___~_____________..JnL_____.;._
I

I
I

CONJ PROC CLK H

CONJ DATI L

CONJ DATI (1)H

~----------~--~I

BUS BSSY L

BUS MSYN L

CONG CKOFF L

CONC CLR MSYN H _ _ _ _ _ _ _"--_ _ _ _:....-_ _ _....J

CONC CKOFF (1) H

CONC ADV ENAB (1) H

-... DATI-140ns :.DATO-350ns

BUS SSYN L
OR
CONA INT TRAN SYNC L - - - - ,
(OCCURS
WHEN
INTERNAl;.,
REGISTER ARE ADDRESSED)
L _ _ _ _....;...._ _ _ _..!-_ _ _ _!...-_ _ _.....J

11-1191

Figure 8-15 DATI and DATa Timing

8.6.2 DATI Operation
The microprogram requests a DATI by asserting the signal CONG DATI L, which is the input to E05309 on print
CONC. On the next processor clock following the assertion of CONG DATI L, the flip-flop DATI E017 on CONC is
set. If the Unibus is free, BBSY is set.

8-34

Simultaneous with the assertion of CONC BBSY (1) L, the bus address drivers (print COND) enable the contents of
the Bus Address (BA) Register onto the Unibus address lines. The bus drivers for BUS Al6 and BUS Al7 are
automatically enabled by the following equation:
BUS Al6 and BUS Al7 = (AI5) (AI4) (Al3) (BBSY)
This allows PDP-II processors, such as the KDII-B, that do not have extensive memory management facilities, to
address peripheral registers that are located between 124K and 128K in the address space.
The MSYN flip-flop, E060 on print CONC, is normally set 150 ns after the issuance of BBSY. The setting of MSYN
triggers a 9602 one-shot E025, shown at the lower left side of print CONC. This one-shot, which has a pulse width of
25 ns, is used to detect attempts at addressing non-existent memory by the processor. If SSYN does not appear on
the bus before the signal CONC DAT TO (1) L is asserted by E034, the microprogram is forced to execute an error
trap sequence.
SSYN is strobed into the holding register E005, shown on print CONCI, and generates the Signal CONC SSYN (1) H.
CONC SSYN (1) H enables an OR gate (E06208 shown in the center of print CONC). At this point, the following
conditions exist:
a.

BBSY, CO, CI, and MSYN are being applied to the Unibus by the KDll-B.

An address is enabled on the bus address lines by the processor.

Data is being driven onto the Unibus data lines by the addressed device or memory location.

SSYN is being generated by the addressed device.

The addressed peripheral device must maintain both its data and SSYN on the bus as long as MSYN is asserted. The
Unibus control removes MSYN from the bus within 300 ns after SSYN and CKOFF are both set. The gating
structure for removing MSYN can be traced back from the K-input to the MSYN flip-flop (E060 on print CONC).
If MSYN, CKOFF, and the oscillator divider flip-flop are all set, and the BC is waiting for SSYN, the oscillator input
is inhibited and the oscillator stops. When SSYN is asserted, the input is released and MSYN is cleared This method
of synchronization causes no extra delay or flip-flop setup problem.

8.6.2.1 DATIP Operation - Note that the sequence for DATI and DATIP are almost identical. DATIP is used by
the processor to prevent the modification of a memory location by a device other than the processor, while the
processor is operating on that memory location. To further understand the need for DATIP, consider the operation
of the DMll, a 16-line Asynchronous Serial Line Multiplexer (DEC-II-HOMA-D). The Buffer Active Register in the
DMII indicates status information and initiates message transmission. To begin the transmission of a message, the
processor sets a 1 in the DMll Buffer Active Register. When the message has been transmitted, the DMll performs
an NPR transfer to its own status register and clears the appropriate channel status bit.
Typically, the program to set an appropriate bit in the DMII status register will use a BIS instruction. To execute
this instruction, the processor must first execute a DATIP to the address of the DM 11 status register and obtain a
copy of the current contents of the status register. The specified bit is then set in the copy of the DMII status
register that is held by the processor. Finally, the processor performs a DATa to the status register and returns the
altered copy of the status register to the DMII.
If, for instance, at the time of the DATIP, channels 0, 1, and 2 were active, the processor would retrieve a status
word of 000007 8 . Suppose the program desired to activate channel 4; the return status word would equal 000027 8 .
If channels 0, 1, or 2 completed their transmission between the time the processor issued the DATIP and the DATa
and the processor permitted the DMII to clear its status register before the DATa cycle of the BIS instruction, it is
obvious that the copy of the DMll status register held by the processor would be invalid.
8-35

Memories manufactured by DEC inhibit the normal restore cycle when a DATIP is issued. Therefore, when the
following DATO is issued, the memory does not have to wait for the completion of the previous restore cycle before
continuing with the DATO operation. However, the processor must inhibit NPRs from issuing a DATIP to the
completion of the following DATO. Therefore DATIP operations lengthen the worst case NPR latency of the
processor.
8.6.2.2 DATIP Logic - The BC executes a DATIP whenever the flip-flops DATI and DATIP (E017 and EOO8 on
print CONC) are simultaneously set by the microprogram. The equation for setting DATIP, E017, is as follows:
(SET DATIP E063, pin 12) = (CONG ENAB IN PAUSE L) +-(DPG ENAB NON MOD H)
(CONI ALLOW PC L)
Signal number 1 is an indication that the microprogram anticipates the need for a DATIP. Signal number 2 confirms
that the current instruction in the IR is one that requires the destination to be restored. The instructions TST, CMP,
BIT, JMP, and JSR can never result in the modification of the destination by the processor. Therefore, it is not
necessary to use the DATIP operation during the execution of these instructions. Signal number 3 ensures that
DATIP is set on a processor clock rather than a BC clock. DATIP remains set following the transfer and inhibits the
setting of NPG flip-flop E00712. It is directly cleared when the processor enables the destination data during the
next DATO, and NPRs are again allowed to be granted.
8.6.3 DATO
DATO differs from DATI in that for a DATO the Unibus data lines are driven by the processor. Figure 8-14 shows
that data is maintained on the bus for the duration of BBSY. In the KDII-B, a DATO operation requires
cooperation between the BC and the microprogram. The steps executed by the microprogram for a DATO operation
are illustrated in flow chart example shown below. Note that CK OFF and DATO must be set simultaneously, and
that the microprogram control step that follows the DATO speCification must enable the data from the appropriate
storage register through the ALU and AMUX.

LOC

NXT

DATO Starts

334

065

DI-5DATO;ALBYT;CKOFF
/GET TO Dl-6 FROM DO-18 VIA
GOTO

DATA Put on Unibus

065

305

DI-6 DRIVERS B; GOTO B2-2
(BUT SERVICE)

The microprogram initiates a DATO operation by setting the DATO flip-flop (EOI7 on print CONC). The 7400 gate,
E007, generates the signal CONC DAT ENAB L, which enables the data drivers shown on prints DPA, DPB, DPC,
and DPD, and also clears DATIP.
8.6.4 Byte Operations
Byte operations have the following Significance to the KDII-B Unibus control (Be):
a.
b.

An odd address may be placed on the Unibus.
For a DATOB, both CO and Cl are enabled.

Byte operations have the follOwing significance on the Unibus slave:
a.
b.

No Significance for DATIP operations.
For DATOB operations, only the upper or lower eight bits of the addressed location should be altered.
8-36

NOTE
The master must properly position the data during a DATOB
operation. For instance, if the operation is a DATOB to the
odd byte of a location, the data must appear on Unibus data
lines (15:08).

In the processor, the ALLOW BYTE flip-flop (E043 on print CONC) permits odd addresses and generates the
appropriate CO and CI signals. The microprogram attempts to set the ALLOW BYTE flip-flop, whenever the
possibility of a legal odd address or DATOB is antiCipated, by asserting the Signal, CONG ALLOW BYTE L. The
signal DPG BYTE L (shown as an input to E06303 on print CONC) confirms that the current instruction (IR) is a
byte operation.
8.6.5 Bus Errors
The following situations cause the bus error trap sequence to be executed:
a.

An attempt to illegally address an odd location in the memory space. For instance if the contents of R7
is odd at the beginning of an instruction fetch, a bus error trap will be executed because instructions
must start at even addresses.

An attempt to access non-existent locations in the memory space. A non-existent location is recognized
when SSYN does not appear on the bus within 25 /JS of the setting of MSYN by the processor.

Either type of bus error causes the BE flip-flop, E050 on print CONC, to be set. The BE flip-flop inhibits the signal
CONC MSYN OUT H which removes MSYN from the Unibus whenever a bus error is detected. The signal CONC
BUS ERROR (1) H causes the 256 X 4 ROMs (E092 and EI02 on print CONF) that generate the next address for
the microprogram to be disabled. This forces the microprogram to execute its next control step from micro address
OIOs·
A double bus error is defined by two successive unsuccessful attempts at addressing the memory. On the second
successive bus error, the microprogram is forced to location 11 Os by the simultaneous setting of the BE and DBE
flip-flops (E050 and E060 on print CONC). The microprogram in the KDII-B is designed to cause a processor halt
after two successive bus errors.
8.7 INTERNAL UNIBUS ADDRESSES
All presently implemented PDP-II processors, including the KD II-B, contain internal registers that have associated
addresses in the Unibus address space. To the program executed by the processor, the internal registers are
indistinguishable from peripheral or memory registers. However, access to the internal registers is not available to
devices attached to the Unibus other than the processor.
In the KDII-B, the concept of internal registers has been expanded to include the serial communications line control
and the line clock. Table 8-9 lists the internal Unibus addresses.
Attempts to address internal Unibus addresses are detected by the logic detailed on print CONA and illustrated in
Figure 8-16. A characteristic of all addresses listed in Table 8-9 is that the odd byte of the address is equal to 377 s .
The signal CONA INT BUS ADDRS L, generated by E039, indicates that the odd byte of the currently addressed
register is 377 s and that the bus address may be that of an internal register.
The read-only memories of ICs E030, E069, and E068 decode the least significant eight bits of the Unibus address to
determine which, if any, of the internal registers are currently being accessed.

8-37

Table 8·9
Unibus Addresses
Function

Octal Address
177700
177701
}
177707
177710
177717
177776
177570
177571
177560
177562
177564
177566
177546

Gen"al

"gi"'" RO thmugh R7

Hidden registers used by the microprogram
Program status register
Console switch register
Odd byte of console switch register
Receiver or keyboard status register
Receiver or keyboard buffer
Transmitter or printer status register
Transmitter or printer buffer
Line clock status register
+5V
01
MO (1)
MI (1)
CONA INT 0 H

CONA INT I H

A6
M2 (1)
AI

23-A09AI
F069
DATI
ADDRS
DECODE
A2

CONA INT 2 H

CONA INT 3 H

M3 (I)
M4 (I)
M7 (I)

A3
M5 (I)

CONA SA 09 (1) H

----.!.L

CONA SA OB (1) H

---1L

eONA SA 10 (1) H

CONA I NT

-QL ~

CONA SA 15 (1) H ~
14 (I) H
05
CONA SA 12 U) H

eONA BA

eONA SA

13 (1) H ~

eONA SA

II (1) H

CONA TRAN IN L

AO
M6(1)

CONG ENAB PSW L
02
CONG ENAS SSR L
03

09r

eONA ENAS ALU L
07
CONA INT TRAN SYNC L

+5V
MO (I)

~ A6

~ A4

eONA SA 00 U) H ~ A3

M3(1)

23-AOA2
F030
INTN
ADDRS
DECODE

~ A2

eONA SA 01 (1) H ~

M2 (1)

Ml (I)

MOU)

r
r

MI (I)
CONA INT 0 H

CONA INT 1 H

CDNA INT 2 H

CONA INT 3 H

M3(1)
23-AOAI
F06S
DATO
ADDRS
DECODE

M2(1)

CONA SA 03 (I) HI~ AO

M50)

CONG LOAD PSW L

r
r
,~
,r

04
03

M4 (I)

r--!Q
M7 (1)

Y,4 1'3

Figure 8·16 Unibus Address Decoding

8·38

M6 (1)

AI
CONA TRAN OUT L -

CONA RUN GND H

CONA ENAS L CLK PSW L

-----2L

eONA SA 07 (1) H ~ A5

eONA SA 02 (1) H

eONA ENAS MODEM PSW L

-r

ADDRS 2

eONA SA 04 (1) H ~ A7

eONA SA 05 (I) H

CONA ENAS SWITCH REG L

+5V

CONA SA 06 U) H

eONG ENAS SPL L

07
09

eONG SP WRITE L
CONA LOAD MODEM PSW L
CONA LOAD L CLK PSW L
CONA RECEIVE L
eONA XMIT L
eONA REG ADDR L
eONA INT TRAN SYNC L

11-1190

The timing diagram contained in Figure 8-17 shows that the signal CONA INT TRAN SYNC L replaces SSYN for
internal registers_ Note that bus addresses, C1, CO, and MSYN are driven onto the Unibus during attempts to address
internal registers_ However, the signals generated by ROMs E068 and E069 reconfigure the data path (DP) such that
during a DATI from 177776, for example, the PSW is enabled onto the DP_

,
Be ---.:,

CONJ BC
CLOCK H _ _ _ _---I

PROC ClOCKH __________~rlL

BR l

L-_~

I-_-----J

1-_ _ '

____________~rlL__________~

~L_ _ _ _ _ _ _ _ _ _ _~~------~\r~-----------------------

CONE
S E R V ICE H ____________-'

~ (j

BG H ______________________________..J

-l

BUS SACK l

1--101'5

\h
BUS TIN T R l

IL-----------f)

---------+l---,

BUS SSYN l
NOTE:
BC designates beginning of BC clock pulse train

DATA 'MUST BE
AVAI lABlE HERE

~r----

-'--STROBE VECTOR
HERE
11-1188

Figure 8-17 Bus Request (BR) Timing

During transfers to and from the processor, to registers and to memory, data to or from the BREG is normally
inhibited. The reason is that most of the elements contained on the A-leg may be addressed with their corresponding
Unibus address. Therefore, almost any data transfer may be from or to the DP. Since it is not possible to both read
and write into the DP on the same clock pulse, it is necessary for the microprogram to receive and transmit Unibus
data from the BREG.
In order to understand the decoding sequence for ROMs F030, F068, and E069, it is necessary to refer to the ROM
maps (K-RL-M7260-8 and K-RL-M7261-8).

8.8 BUS REQUESTS
The KD11-B responds to bus requests (BRs) in a manner similar to that of the other PDP-II processors. Peripherals
may request the use of the Unibus in order to make data transfers or to interrupt the current processor program by
asserting a signal on one of four BR lines, numbered 4, 5, 6, and 7 in order of increasing priority. For example, if
two devices, one at priority 5 and the other at priority 7, assert BRs simultaneously, the device at priority 7 is
serviced first. Furthermore, if the processor priority, determined by (07:05) of the PSW, is at leve14, only devices
that request BRs at levels higher than 4, such as BR 7, BR 6, or BR 5, are serviced. Table 8-10 contains the order of
priorities for all BRs and other traps.

8-39

Table 8-10
Trap Priorities
Priority
Highest

Lowest

Service Priorities

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.

T-bit trap
Stack overflow
Power fail
BR7
BR6
Internal line clock
BR5
BR4
UART receive
UART transmit
Console stop
Next instruction fetch

Since a BR can cause a program interrupt, it may be serviced only after the completion of the current instruction in
the IR. A device that requests a program interrupt must at the appropriate time place a vector address on the Unibus
data lines. The processor first stacks away the current contents of PSW and R7; then a new R7 is loaded from the
contents of the vector address, and a new PSW is loaded from the contents of the vector address plus two. An
example of the flow that handles a BR is as follows:
LOC

NXT

*BUS GRANT SERVICE
/GET TO BG-I FROM BUT SERVICE

040

305

BG-I BUT INTERRUPT; GO TO B2-2 (BUT SERVICE
-I/IF INTERRUPT GO TO INT-I
IIF NO INTERRUPT FALL THROUGH TO B2-2

LOC

NXT

*INTERRUPT SERVICING
/GET TO INT-I FROM BG-2 VIA BUT INT (TRUE)

325

246

INT-l R(12) +- UNIBUS DATA; SET SLAVE SYNC; GO TO ET-3

LOC
246
247
226
251
252
253
254
255
256
257

NXT
247
226
251
252
253
254
255
256
257
305

-I-

ET-3 B, BA +- R(6) - 2; ENAB OVER
ET-5 R(6) +- B; CK OFF; DATO
ET-6 DRIVERS +- PS
ET-7 B, BA +- R(6) - 2; ENAB OVER
ET-8 R(6) +- B; CK OFF; DATO
ET-9 DRIVERS +- PC
ET-IO BA +- R(12); DATI; CK OFF
ET-ll PC +- UNIBUS DATA
ET-I2 BA +- R(12) + 2; DATI, CK OFF
ET-I3 PS +- UNIBUS DATA; GO TO B2-2 (SERVICE)

The microprogram indicates the end of instruction execution by asserting the signal CONE BUT SERVICE L. BRs
are arbitrated by the ROM EOl2 (shown on print CONCI). If there is an impending BR, the signal CONC BR
GRANT H is asserted by E02208 (print CONCI). When CONE BUT SERVICE L is issued, the appropriate BG is
clocked into the storage register (E02I). Simultaneously, the microprogram address is forced to the bus grant
sequence by the logic shown on print CONE.

840

In the KDll-B, interrupts for the SCL and the line clock are not entered the same way as interrupts from other
devices attached to the Unibus. Interrupts from the SCL and line clock are handled in the same manner as power fail
and stack overflow traps. For all of these events, the microprogram address is altered when CONC BUT SERVICE L
is issued to force the microprogram into the appropriate routine, which simulates the appropriate interrupt or trap.
The appropriate vector address for SCL and line clock interrupts are generated by the constants generator, which is
the E025 ROM shown on print DPB.
8.9 NON-PROCESSOR REQUESTS (NPR)
NPRs are a facility of the Unibus that permit devices on the Unibus to communicate with each other with minimal
participation of the processor. The processor's function in servicing an NPR is simply to give up control of the bus in
a manner that does not disturb the execution of an instruction by the processor. For example, the processor may
not relinquish the bus following a DATIP.
An NPR is received through a bus receiver (print COND) and clocked into storage register E005 (print CONC1). If
conditions are appropriate to permit an NPG to be issued by the KDll-B, the signal CONC SET NPG H is issued by
E01406. CONC SET NPG H is generated according to the following equation:

CONC SET NPG H = (+-DATIP) • (+-SACK DELAYED) • RUN
The signal CONC SET NPG H causes flip-flop E033 to be set, which in turn causes NPG to be placed on the Unibus.
Note that both NPGs and BGs will be issued by the KD ll-B for a period of 10 JJS. If the requesting device does not
respond with SACK within this period, the 9602 timer IC (shown in the upper right-hand corner of CONC1) trips,
causing flip-flop E034 to be set. This in turn causes the pending BG or NPG to be cancelled, and the processor to
continue operation.

8.10 SERIAL COMMUNICATIONS LINE DESCRIPTION (SCL)
The SCL of the KDll-B is essentially program compatible with the KL11 teletype control. The heart of the serial
communications line logic (prints DPH and DPHl) is the Universal Asynchronous Receiver Transmitter (UART), an
MaS-LSI IC. The UART is easily recognized on the M7260 module because it is the only 40-pin dual in-line package
used in the KDII-B. The UART is the only IC in the processor that requires two supply voltages, +5V and -12V.
The -12V supply (print DPH) for the UART is generated by placing four diodes in series with the -15V supplied by
the power supply.
The additional circuitry other than the UART (prints DPH and DPHl) serves the following purposes:
a.

Generation of the reader RUN signal that is used to control the low speed paper-tape reader found on
Model ASR 33 Teletypes.

Generation of status bits and interrupts to make the KDI1-B SCL program compatible with the KL1l.

Generation of the 20-mA current loop necessary to operate Model ASR 33 Teletypes, VT05s, and
LA30s.

An important feature of the KDll-B SCL is double buffering. An understanding of double buffering (Figure 8·18)
may be gained by studying the programming example provided. In order to receive or transmit data at the maximum
rate, it is only necessary to empty or fill the appropriate UART buffer once every character time. Conversely, on
single-buffered devices such as the KL11, it is necessary to empty or fill the appropriate buffer in one bit time.

8-41

RECE I VE R
SERIAL INPUT

SHIFT REGISTER

R C D B U F FER (RCDBl

I
I

AL EG

AMUX

TRANSMITTER

XMIT BUFFER (XMITBll

SHIFT REGISTER

I
I

SERIAL OUTPUT

11- 11 89

Figure 8-18 Double-Buffering Data Flow

The following programs are sample programs which utilize the UART. The first program simply echoes a character
received from the UART into the transmitter of the UART. The second program illustrates the proper use of the
RESET instruction, following an instruction that caused the SCL to transmit a character. RESET should not be
issued until the last desired character has cleared the UART transmitter shift register.
UART Sample Programs
LOOP:

TSTB
BPL
TSTB
BPL
MOVB

RCDSTA

TSTB
BPL
MOVB
TSTB
BPL
RESET

XMITST

XMITST
RCDB,XMIT

NULL,XMIT
XMITST

; Test for a received character
; Go to Loop if no character
; Test the XMIT condition
; echo character
; If at this point it is desirable to issue a
; RESET it is necessary to send a null
; character to ensure that the desired
; character has been completely transmitted

; When null character is
; clear of the
;XMITB

On print DPH, the transmitter DONE flag is seen only as an indication that the transmitter buffer is empty (TBMT).
The TBMT flag will set at least one character time before the UART has finished transmitting the last character
received. A RESET instruction that occurs while a character is in the process of being transmitted aborts that
character transfer. Therefore, the only safe way to issue RESET instructions, following an instruction that has
transmitted a character through the UART, is to transmit a null character prior to issuing the RESET instruction.
Some care must be used in selecting the null character since it may be garbled by the RESET instruction. When the

842

null character clears the UART transmitter buffer, it is safe to issue the RESET instruction. When the SCL
maintenance mode is enabled by setting the transmitter status bit (2), the serial output is fed back into the serial
input just as in a standard KLll. The transmitter status register address is 177564 8 . The SCL always appears to the
program as the last device at the BR4 interrupt level.
There is a provision in the SCL control (print DPH) to disable the internal clock and to provide an external clock for
the UART. External clocks consisting of TTL-compatible signals must be square waves of up to 160 kHz. The clock
frequency must always be 16 times the SCL baud rate.

8.11 LINE CLOCK
8.11.1 Introduction
The line clock allows the program to measure time by sensing the frequency (50 Hz or 60 Hz) of the ac input power.
The sensing signal is generated by the power supply. It is a positive, approximate square wave developed from the ac
input waveform. For a 60-Hz supply, this signal occurs at a rate of 16.7 ms; the rate for a 50-Hz supply is 20 ms.
Each sensing signal generates a flag that can be read on Unibus data bit 07 and can be cleared only by program
control. A line clock interrupt signal is generated concurrent with the flag signal, provided the interrupt enable bit is
set by the program. This interrupt signal is used in the processor priority arbitration logic. An interrupt enable flag is
generated and can be read on Unibus data bit 06.
The line clock is not connected to the Unibus. It uses an internal bus and can be accessed only by the processor and
console; however, to the operating program, the line clock is indistinquishable from other devices that are attached
to the Unibus. This is accomplished by logic that decodes the address of the line clock on the Unibus as an internal
address.
The line control logic is shown in print CONI. It can be divided into two sections: flag control and interrupt
control. Each section is described in detail in subsequent paragraphs.
8.11.2 Flag Control
The flag control logic is shown in the top of print CONI. Signal PWR SUPPLY L CLK INT H is the sensing signal
from the power supply. This signal is generated by a resistor-Zener clipper circuit. The positive half cycle is clipped
at approximately +4V and the negative half cycle is clipped at approximately -I V. This produces a clipped sine wave
(approximate square wave) with a pulse height of nearly +5V (base line at -I V). These positive pulses occur every
16.7 ms for a 60-Hz input and every 20 ms for a 50-Hz input.
Signal PWR SUPPLY L CLK INT H is sent to the input of NAND Schmitt trigger EOI9. Each positive input is
converted to a clean negative square pulse at the output. The positive-going edge of this pulse clocks the CLOCK
flip-flop E036. This is a redefined flip-flop with its D-input connected to ground (CONH RUN GND L). When
clocked, the flip-flop is set and its I-output (pin 06) is high. This signal is sent to the input (pin 02) of Unibus driver
E03. The output of this driver is the line clock flag signal BUS D07L. It can be read during a DATI operation by
providing an enabling signal to pin 03 from gate E067. This gate is enabled when both inputs are low. The inputs
are: CONC BBSY (1) L which is asserted when the BBSY flip-flop E043 (print CONC) is set; and CONA ENAB L
CLK PSWL which is generated by DATI ADDRS DECODE ROM E069 (print CONA).
The flag can be cleared only by program control. It is accomplished by signal CONI CLR CLOCK L via the clear
input (pin 04) of the CLOCK flip-flop. This signal is generated at the output (pin 03) of NAND gate E027. One
input of this gate is the inversion of DPB AMUX 07 H via gate E065 pin 12. The other input to E027 is the resul t of
ANDing CONA LOAD L CLK PSWL and CONJ PROC CLOCK L. Signal CONA LOAD L CLK PSW L is generated
by DATa ADDRS DECODE E068 (print CONA). It is low when the line clock address is decoded. When this signal
is ANDed with a low clock pulse (CONJ PROC CLOCK L), input 02 of E027 is high. If the flag is to be cleared, the
program generates a low on DPB AMUX 07 H. This signal is inverted and places a high on pin 0 I of E027. The
output (pin 03) of E027 is CONI CLR CLOCK L, which is low, and the CLOCK flip-flop is cleared.

843

8.11.3 Interrupt Control
The interrupt control logic is shown on the bottom of print CONI. The Schmitt trigger output also clocks LC INT
flip-flop E08 which is a redefined flip-flop with its D-input connected to ground (CONH RUN GND L). When
clocked, the flip-flop is set and its I-output (pin 06) is high. This signal is sent to the D-input of LC INT SYNC
flip-flop EOI8. This flip-flop is clocked by CON] PROC CLOCK L. When clocked, the I-output of the LC INT
SYNC flip-flop is high. This signal is sent to pin 05 of NAND gate E027. This gate generates signal CONI L CLK INT
L that is used in the processor priority arbitration logic. It can be regarded as an internal BR signal. Signal CONI L
CLK INT L is asserted when both inputs (pins 04 and 05) are high. Pin 05 is high as discussed above and pin 04 is
high when the program sets the interrupt enable bit and the processor priority is not 6 or 7. The logic for qualifying
pin 04 is discussed below.
The high output (pin 01) of E026 is inverted by NAND gate E045 pin 08 and used to clock INT ENAB flip-flop
E035. To set the interrupt enable bit, the program generates a high on DPB AMUX 06 H which is the D-input of the
INT ENB flip-flop. When clocked, the INT ENB flip-flop is set and its a-output (pin 08) is low. This signal is sent to
pin 11 of gate E026. The other input of this gate comes from the output of NOR gate E049 which is low when
either or both of its inputs are high. The inputs are DPE PSW 07 (0) Hand DPE PSW 06 (0) H. They come from the
a-outputs of PSW (07:04) flip-flop E042 (print DPE). This flip-flop stores the current priority of the processor in
bits 07,06, and as. The two outputs used are the complement of bits 07 and 06 of the priority word. The qualifying
condition for the interrupt control logic is that the processor priority not be 6 or 7. That is, the output of gate E049
is low when the processor priority is not 6 or 7. This condition is verified as shown below.
Priority Bits DPB AMUX 07 H, 06 H
and 05 H to PSW (07:04) flip-flop

Priority

7
6
5
4
3
2
1
a

1
1
1
1
a
a
D

Complement of Bits 07 and 06 from PSW
(07:04) flip-flop

PSW Bits
06

1
1
a
0
1
1
0
0

1
a
1
0
1
a
1
a

0
a
a
a
1
1
1
1

~)
I"'"
1
a
0
1
1

NOR Gate E049 Disabled
(Output High)

NOR Gate E049 Enabled
(Output Low)

...

The low output of NOR gate E049 is sent to input pin 12 of E026. The other input is low because the INT ENAB
flip-flop is set. This generates a high at the output of E026 (pin 13) which is sent to pin 04 of E027. The other input
(pin 05) of E027 is also high which asserts CONI L CLK INTL.
The I-output of INT ENAB flip-flop E035 is sent to pin 06 of Unibus driver E03. The output of this driver is the
state of the interrupt enable bit; however, it is deSignated BUS D06L. This bit can be read during a DATI operation
by enabling the gate with the output of E067, which is explained in the flag control discussion.
When the interrupt is serviced, the microprogram performs a BUT SERVICE which asserts Signal CONE L CLK SER
L from the INT INTR ACK ROM (E090 print CONE). This low signal is gated with a low clock pulse (CONJ PROC
CLOCK L) at pins 09 and 08 of E026 to produce a high output (pin 10). This high is sent to pin 06 of NOR gate
E026 where it is inverted and used to clear the LC INT flip-flop via its clear input (pin 10). When the LC INT
flip-flop is cleared, it sends a low signal to the D input of the LC INIT SYNC flip-flop. On the next clock pulse
(CONJ PROC CLOCK L), the LC INT SYNC flip-flop is reset and the interrupt signal CONI L CLK INT is cleared.

8-44

Some programs assert the interrupt enable bit and keep it asserted. In the case of the line clock, the interrupt signal
CONI L CLK INT L cannot be asserted even if the INT ENAB, LC INT, and LC INT SYNC flip-flops are set as long
as the processor priority is 6 or 7. If the priority is lowered below 6 with these flip-flops set, CONI L CLK INT L
could be asserted. This possibility is circumvented by clearing the LC INT flip-flop every time the program clears the
CLOCK flip-flop in the flag control section. This is accomplished by CONI CLR CLOCK L which is generated at
E027 pin 03 and is sent to the clear input (pin 10) of LC INT flip-flop E018 via gates E041 and E026.
The CLOCK flip-flop and LC INT flip-flop are also directly cleared by CONC BUS INIT L which is generated during
the power-up sequence, during a RESET instruction, or when the console START switch is depressed.
8.12 POWER FAIL
The KDII-B power fail/auto restart circuitry (print CONH) serves the following purposes:
a.

Initializes the microprogram, the Unibus control (BC), and the Unibus to a known state immediately
after power is applied to the computer.

Notifies the microprogram of an impending power failure.

Prevents the processor from responding to an impending power failure for 2 ms after initial startup.

The actual power fail/auto restart sequences are microprogram routines. The operation of the power fail/auto restart
circuitry depends on the proper sequenCing of two bus signals: AC La and DC W. Because of the electrical
properties of the Unibus drivers and receivers, the entire computer system must be powered up for the machine to
operate. Therefore, the processor is notified of a power fail in peripherals as well as in its own ac source.
The notification of power status of any PDP-II system component is transmitted from each device by the signals
BUS AC La L and BUS DC La L (Figure 8-19). The power-up sequence shows that BUS DC W Lis unasserted
before BUS AC La L is unasserted. When BUS DC W L is not asserted, it is assumed that the power in every
component of the system is sufficient to operate. When BUS AC La L is not asserted, there is sufficient stored
energy in the regulator capacitors of the power supply to operate the computer for 5 ms, should power be shut
down immediately.

BUS AC LO L

BUS DC LO L

+5V
OV _ _ _ _ _ _...J

~r__,~-------___

+3V

OV _ _--'

--l t.t IINIT

POWER UP

I t.tl>Orns

~'--------

-l

l-t.t2>7rns

_ _---oJ

I--- 70 rna --l
____________-...J~I--~~I_____________
f-2ms-j

PDWN

~6.6ma-j

Figure 8-19 BUS AC LO and BUS DC LO Timing Diagram

8-45

As power is shut down, note that BUS AC LO L is asserted first. BUS AC LO L is an indicator that warns the
processor of an impending power failure. When BUS DC LO L is asserted, it must be assumed that the computer
system can no longer operate predictably. Memories manufactured by DEC use BUS DC LO L as a switch signal.
When BUS DC LO L is asserted, these memories turn themselves off even if power is available. Time b,. +2 (Figure
8-19) is the time delay between the assertion of BUS AC LO L and the assertion of BUS DC LO L; it must be greater
than 7 ms. This allows for power to be rapidly cycled on and off. According to PDP-II speCifications, upon system
startup, a minimum of 2-ms run time is guaranteed before a power fail trap occurs, even if the line power is removed
simultaneously with the beginning of the power-up sequence. After the power fail trap occurs, a minimum of 2-ms
run time is guaranteed before the system shuts down. Given the tolerances permitted in the timing circuitry used in
most equipment, b,. +2 must be greater than 7 ms.
When an impending power fail is sensed, a program trap occurs that causes the present contents of R7 and the PSW
to be pushed onto the memory stack, as determined by the contents of R6. R7 is then loaded with the contents of
memory location 24 8 , and the PSW is loaded with the contents of location 26 8 , Processing is continued with the
new R7 and PSW. The program must prepare for the impending power failure by storing away volatile registers and
reloading location 248 and 26 8 with a power-up vector. This vector points to the beginning of a restart routine.
When power is restored, the processor loads R 7 with the contents of location 248 and the PSW with the contents of
location 26 8, Note that no stacking is performed on an auto restart. The HALT switch is also ignored if the console
lock is set. After loading R7 and the PSW, processing continues if the HALT switch is not depressed. Presumedly,
the program will prepare locations 248 and 26 8 for another power failure. If the HALT switch is depressed and the
console lock is not enabled, the processor powers up in the halt state.
Schematics of the power fail, auto restart, and bus reset logic are found on print CONH. As shown on Figure 8-18,
E07106 generates a 70-ms processor INIT pulse as soon as BUS DC LO Lis nonasserted after power is applied to the
computer. At the end of 70 ms, the PUP one-shot, IC E08209, is fired if BUS AC LO L is not asserted. At this point,
the processor begins to load R7 and the PSW if the HALT switch is not depressed. The PUP one-shot generates a
2-ms pulse, during which time the assertion of BUS AC LO L is not recognized.
After PUP has been reset, the assertion of BUS AC LO L fires the one-shot E08206. Flip-flop E09708 is set by the
leading edge of the one-shot's pulse. Note that E09708 is not synchronized to the processor clock. Flip-flop E09706
generates the signal CONH PDWN SYNC (1) L, which is synchronized to the processor clock. A power fail trap can
be recognized by the microprogram whenever CONE BUT SERVICE L is issued. The various traps are arbitrated by
the ROM FlOl (print CONE).
If a momentary power failure occurs which causes the assertion of BUS AC LO L but does not cause the assertion of
BUS DC LO L, the processor will restart when the PDWN (0) L one-shot times out, retriggering the INIT one-shot
simul taneously with DC LO H becoming nonasserted.

8-46

CHAPTER 9
MICROPROGRAM CONTROL

9.1 INTRODUCTION
This chapter describes the microprogram control implemented in the KDII-B processor. The flow notation used in
the microprogram flow section of the prints is described in Paragraph 9.5.1. The difference between microprogram
control and conventional control in a computer processor is described in Paragraph 9.2. Paragraph 9.3 describes the
KDI1-B control store (CS) structure; Paragraph 9.4 describes the technique of branching within microroutines in the
CS; and Paragraph 9.5 describes the microprogram flow, including instruction interpretation, Unibus control
coordination, interrupts, traps, and console functions.
9.2 MICROPROGRAMMED VERSUS CONVENTIONAL CONTROL
The control section of a conventional computer is a complex collection of specialized logic circuits. These circuits
generate the timing signals that constitute the major and minor time states of a machine cycle. During each time
state, these control signals configure the data path (DP), determine function performed within the arithmetic/logic
units (ALU), influence the Unibus control (BC), etc. Major disadvantages associated with this conventional approach
are its complexity, the large amount of logic required, its inflexibility, and difficulty of making modifications.
A microprogrammed processor such as the KDI1-B results in a reduction in the amount and complexity of the
control logic, while facilitating a systematically implemented and easily modified control section. Basically, a
microprogram involves the execution of a sequence of microsteps from the control store (ROMs). Execution of a
microstep causes the assertion of a set of control signals specified in the control store word associated with that
microstep. By executing appropriate sequences of microsteps (known as a microroutine), the KDII-B can be made
to interrupt PDP-II instructions. Other functions such as console functions, interrupts, and traps are also
accomplished by specialized microroutines.

9.3 CONTROL STORE
Figure 9-1 shows the format of the KDII-B control store (CS) word. There are 256 such words, each having the
same fields. The fields, the possible values they may contain, and the significance of each value are described in
Table 9-1. The CS is shown on prints CONF and CONGo
An explanation of the notation will aid in relating the CS word to the reset of the print set. Each field within the CS
has been given a name (e.g., BUT, BRG, ALG, ... ,ALU. NXT). These field names are used throughout
documentation of the microprogram.
The signal coming from each bit is named according to the convention used in the print set. Note that several signals
may be associated with a single field (e.g., the BUT field controls four signals: CONG BUT 01 L, CONG BUT 00 L,

CONG BUT 02 L, and CONG BUT 03 L).

9-1

CONG ALLOW BYTE L

CONG DATO L

CONG CKOFF L

CONG DATI L

CONG ROM SPA 02 H

CONG ROM ALEG 1 L

CONG SP WRITE L

CONG ROM ALEG 0 L

CONG BTOP H

CQNG BMODE 00 H

CONG BA CLOCK L

CONG BMODE 01 H

CONG BBOT H

CONG BUT 01 L

CONG SPA MUX 01 H

CONG BUT 00 L

CONG SPA MUX 00 H

CONG BUT 03 L

---'~--E095---'~--EI07---'~--E093--~~--

CONF ALU S2 L

CONF ALU SI L

CONF ALU S3 L

CONF ALU SO L

CONF MPC 00 L

CONF ALU MODE H

CONF MPC 01 L

CONF CIN H

CONF MPC 02 L

CONF SPARE L

CONF MPC 03 L

CONF AUX CONTROL L

CONF MPC 04 L

CONG LOAD PSW L

CONF MPC 05 L

CONG ROM SPA 01 H

CONF MPC 06 L

CONG ROM SPA 03 H
CONG ENAB
IN PAUSE L

CONF MPC 07 L
30

29
ALU

--~--- E 103 ---1014--- E 104 ---.."",1.>--- E094 --~~-11-1216

Figure 9-1 Control Store Word Bit and Field Format

Table 9-1
KD11-B Control Store Fields
Field
BUT

Description
Branch on microtest. The BUT field has two uses: a) specify microprogram conditional branches, and b) as an encoded miscellaneous field. The values this field
can assume are grouped by these two uses.
Branching within the microprogram is accomplished by wiring conditional signals
with the open-collector outputs of the NXT field of the CS. Each BUT condition
has the minimum number of control bits required. This makes the range of branching restrictive, but it minimizes logic (print CONE). Table 9-2 lists the microstep in
which each BUT is performed, the possible conditions, and resulting destination of
the microprogram branch.
Microprogram conditional branches:

NON

No effect

9-2

Table 9-1 (Cont)
KDII-B Control Store Fields
Description

Field
BUT
(Cont)

JSRMP

Microprogram branch on JMP or JSR instruction

IRD

Microprogram branch on results of Instruction Register Decode

BYT

Microprogram branch to distinguish: a) byte and non-byte instructions, and
b) odd/ even byte references

DST

Microprogram branches on destination mode IR (5: 3)

MOV

Microprogram branch to distinguish both MOV and MOVB from other instructions

INT

Microprogram branch on interrupt to be processed

UNY

Microprogram branch to distinguish unary instructions

Microprogram branch dependent on console switch action

NMD

Microprogram branches to distinguish non-modifying instructions (e.g., CMP,
TST, etc.)

SRV

Microprogram branch at end of instruction sequence to determine if any
condition requires service before going off to fetch next instruction

... -_.

'\~,
.,..J".

;
,

.•.. ',

Miscellaneous encoded field:

411·-..... _-

CON

Enable the constants ROM on the A-leg

INI

Trigger BUS INIT L during the RESET instruction

SVS

Set SSYN on Unibus during the interrupt sequence

ENO

Enable the stack overflow detection logic

IRC

Clock data into the instruction register

BRG

ALG

~,/.

__ .... -

Control the B register
H

Hold, do not modify.

Load.

Shift right once.

Shift left once.
A-leg control; determines what is enabled onto the A-inputs of the ALU

9-3

Table 9-1 (Cont)
KDlI-B Control Store Fields
Description

Field
ALG
(Cont)

Scratch pad

NUL

Nothing

SPR

Low orders eight bits (right half) of the scratch pad

PSW

Program Status Word
Initiation of Unibus transfer

TNS
NON

No effect
Initiate DATI

Initiate DATO

Initiate DATIP
Allow byte reference on current Unibus transfer.

ABT
NO
YES

Inhibit the processor clock until pending Unibus transfer is complete.

CKO
OFF

No effect

ON
Scratch pad address. This field is physically split in the control store word. It is
made up of:

SPA

SPA = SPO = CS (18)
SPI = CS (22)
SP2=CS(12)
SP3 = CS (21)
Scratch pad address (RO through RI7)
Scratch pad control function

SPF

BLG

REA

Scratch pad contents not modified

WRI

Write into scratch pad
B-leg control. Determines what is enabled onto the B-input of the ALU. This field is
physically split in control store word.

9-4

Table 9·1 (Cont)
KDll·B Control Store Fields
Description

Field
BLG
(Cont)

BLG = BTP (B Top· Upper Byte) = CS (14)
BBT (B Bottom· Lower Byte) = CS (16)
BRG

B register

SEX

B register sign extended. Bit 7 of the B register is propagated from bit 7 to bit 15.

The constant
Bus Address Register Control

BAR
H

Hold, do not modify.

Load.

SAM

Scratch pad address multiplexer control. This field is physically split in the control
store word.
SAM = SMO (19)
SMI (17)
ROM

Scratch pad address taken from control store word (see SPA field)

IRS

Scratch pad address taken from source register bits of Instruction Register, IR
(8:6).

IRD

Scratch pad address taken from destination register bits of Instruction Register, IR
(2:0).

BAR

Scratch pad address taken from Bus Address Register low order three bits, BA
15:0).
Program Stat~Word-.c.ontrol

PSW
H

Hold

Load

AUX

Auxiliary ALU control enabled
OFF
ON

CRI

Enable carry in to ALU
OFF
ON

9·5

Table 9-1 (Cont)

KDlI-B Control Store Fields
Field
ALU

Description
ALU function

A logical

A arithmetic

AandB

ABBAR

A and ones complement of B

ZERO

Output zero

AORB

Aor B

B logical

A+B

A plus B

AXORB

A exclusive or B

A-B-l

A minus B minus 1

BBAR

1's complement of B

-1

Output the constant minus one

A-I

A minus one

ABAR

1's complement of A

ASL

Arithmetic shift B left

ROL

Rotate B left

ASR

Arithmetic shift Bright

ROR

Rotate Bright

These are used during shift and
rotate instructions to control
the serial shift inputs to the
B register.

A field may contain anyone of a number of different alternative bit patterns. To facilitate microprogramming, these
alternatives have been given symbolic names, making it possible to work with the microprogram at a symbolic level
rather than in binary. For example (Table 9-1), one of the alternative values that can be assigned to the ALU field is
OR (A or B). This value corresponds to a bit pattern of 01001 [CS (37:33) = 01001].
The data word output from the CS is determined by the contents of the MPC registers (E091 and E102 shown on
print CONF).

9-6

9.4 BRANCHING WITHIN MICROROUTINES
A microroutine is composed of a sequence of microsteps. Every microstep specifies the location of the next
microstep in a sequence, namely, the NXT field. During the execution of a microstep, the signals resulting from the
NXT field are loaded into the MPC (microprogram counter). The MPC specifies the location from which the next
micro step will be executed (print CONF). Conditional branching within a microroutine is accomplished by
wire-DRing signals into those signals coming from the NXT field, while they are being loaded into the MPC. Each
branch condition controls the minimum number of bits required. This restricts the range of branching, but it
minimizes the logic (print CONE). This provides control for all the bits in the MPC. Table 9-2 shows the location of
each microcode branch, the destination, and associated conditions.
In general, microsteps are not executed from numerically sequential locations. This extra degree of complexity (and
an extra eight bits in each CS word to specify the NXT location) enables the minimization of logic.
Table 9-2
Microprogram Branches (BUT)
Source

BUT
IRD (IR decode)

DST (destination)*

F-5

Destination

Comment

SO-l through S7-1

All double operand instructions

DO-l through D7-1

Single operand instructions

B-1

Branch, change PC

B2-2D

Branch, PC unchanged

MCC-l

Set or 0 clear condition codes

Rl-l

RTS

R2-1

RTI

W-l

WAIT

H-l

HALT

ET-l

EMT

BT-l

Break Point Trap

IT-I

lOT

T-l

Trap

RT-l

Reserved instruction

RST-l

RESET

SO-2, SBE-2

DO-I through D7-1

CCM-2

CC-l

Clear condition codes

SC-l

Set condition codes

• Always have a branching destination (i.e., NXT field always modified).

9-7

Table 9-2 (Cont)
Microprogram Branches (BUT)
BUT
BYT (byte)

MOVE

NMD (non-modifying)

SRV (service)

Source

Destination

Comment

SO-\

SBE-I

Byte source data (Mode 0)

SI-2

SBE-I

Even byte source data

SBO-I

Odd byte source data

DBO-I

Byte instruction other than MOVE

MB-O

MOVB instruction (BYTE)

DO-3A

MOV instruction (NOT BYTE)

DO-3, DO-3A

B2-2A

Non-modifying instruction TST, CMP, Bit

DI-4

B2-2B

DBO-2

B2-2

DO-IO

B2-2C

DO-I

B-3, B2-2
B2-2A, B2-2B
B2-2C, B2-2D,
CC-I, CS-3,
DO-4, DBO-3,
11-2,12-8,
MB-2, SC-I

In order of priority
highest to lowest

BT-I

T-bit trap

ERT-IA

Stack overflow trap

PF-I

Power fail

BG-I

BR 7 (bus request level)

BG-I

BR6

LC-I

Internal line clock

BG-I

BR5

BG-I

BR4

URTR

UAR T. Receive

URTX

DART Transmit

9-8

Table 9-2 (Cont)
Microprogram Branches (BUT)
BUT

Source

SRV
(Cont)

SW (switch)

H-2

Destination

Comment

H-l

Console STOP

F-l

None of the above

W-l

When executing WAIT instruction, LOOP
ON W-l instead of going to F-l.

CS-l

Start

CCS-l

Continue

CEl-l

Examine 1st.

CE2-1

Examine

CDl-l

Deposit 1st.

CD2-1

Deposit

CL-l

Load

H-2

None

CEl-l

Loop until examine is

releas~d.

INT (interrupt)

BG-l

INT-l

Interrupt service

JSRMP

Dl-l, D2-3,
D3-5, D6-5

11-1

JMP instruction mode of operation to
change PC.

D6-5

J2-1

JSR instruction

INITIALIZE

RST-l

UNY (unary)

DO-2

Dl-3

DBO-l

Initialize computer RESET instruction.
ERT-l

JMP or JSR Mode 0 - illegal instruction

SB1-l

SWAB

Ul-l

Other unary

SB2-1

SWAB

U2-1

Other unary

U3-1

Unary other than JMP, JSR, or SWAB

9-9

Table 9-2 (Cont)
Microprogram Branches (BUT)
Source

BUT

UNY
(Cont)

Comment

Destination

DE-J

US-J

Unary other than JMP, JSR, or SWAB

DO-9

U4-1

Unary other than JMP, JSR, or SWAB

NON (none)

No branch test

9.5 MICROPROGRAM FLOW
The microprogram flow chart is shown in full detail in engineering drawing K-MP-KDII-B-l. Figure 9-2 is a
simplified flow that provides an overview and aids in using the detailed flow. No attempt is made in this manual to
trace through each path of the microcode. An explanation of the detailed flow notation is provided along with
examples to illustrate instruction interpretation, interrupts and traps, and console functions.

START
SOURCE
CALCULATED SOURCE
ADDR. SET SOURCE
DATA POSITION FOR
BYTE INST.

HALT

CONTINUE
EMT

EXAMINE 1ST
BREAKPOINT
TRAP
EXAMINE NEXT
lOT
DESTINATION
CALCULATED DEST ADDJl
~T DEST DA-m POSITI
R BYTE INST PERFORM
OPERATION REPLACE
DATA AS REQUIRED

DEPOSIT 1ST
TRAP

DEPOSIT NEXT
RESET

11-1212

Figure 9-2 KDII-B Simplified Flow Diagram
9-10

9.5.1 Flow Chart Notation
Figure 9-3 illustrates an excerpt from the microprogram flow section of the prints. Notice that the listing is grouped
into microroutines (source mode 0 through mode 3); these microroutines start with an identifying comment, the
first character of which (disregarding the LOC and NXT columns) is an asterisk. Other comment lines begin with a
slash.

LOC

NXT

201

007

001

* SOURCE MODE 0 (REGISTER), GET SOURCE DATA
/ GET TO SO-1 FROM F-S VIA BUT IR DECODE IR 11:9 = 0
SO-1 B R[S]; BUT BYTE
/ IF BYTE INST GOTO SBE-I (MUST BE EVEN BYTE)
SO-2 R[10] B; BUT DESTINATION
/ IF IR S:3 = 0 GOTO DO-l
/
= 1
Dl-l
/
2
D2-1
/
=3
D3-1
/
/

/
/
LOC

NXT

203

244

007

LOC

NXT

20S
301

301
014

214

244

LOC

NXT

207

016

216

017

= 4
= S
=6

D4-1

D7-1

DS-l
06.. 1

* SOURCE MODE 1 (REG. DEFERRED) GET SOURCE DATA
/ GET TO SI-1 FROM F-S VIA BUT IR DECODE IR 11:9
SI-I BA R[S];DATI;CKOFF;ALBYT
/ GET TO SI-2 FROM S2-3 VIA GOTO
/
S3-S
/
S6-S
SI-2 B UNIBUS DATA; BUT BYTE; GOTO SO-2
/ IF ODD BYTE GOTO SBO-l
/ IF EVEN BYTE GOTO SBE-I
/ IF NOT BYTE FALL THROUGH TO SO-2
* SOURCE MODE 2 (AUTO-INC.) GET SOURCE DATA
/ GET TO S2-1 FROM F-S VIA BUT IR DECODE IR 11:9 = 2
S2-1 BA R[S]; DATI; ALBYT
S2-2 B R[S]+l+BYTE. BAR
/ GET TO S2-3 FROM S4-1 VIA GOTO
S2-3 R[S] 8; CKOFF; GOTO SI-2

* SOURCE MODE 3 (AUTO-INC DEFERRED) GET SOURCE DATA
/ GET TO S3-1 FROM F-S VIA BUT IR DECODE IR 11:9 = 3
S3-1 BA R[S]; DATI (MUST BE AN EVEN ADDRESS HERE)
S3-2 B R[S] +2

Figure 9-3 Excerpt from Microprogram Flow (K-NL-KDll-B-I)

All microsteps have mnemonic names such as SO-I (source mode 0, step I), S2-2 (source mode 2, step 2), etc. A
microroutine will often weave back and reuse part of another. For example, the source mode I routine weaves back
into the source mode 0 routine by the GOTO SO-2 in SI-2 (Figure 9-3).

9-11

To the left of every microstep is the location of that step in the CS (in octal) and the contents of the NXT field.
Observe the microprogram counter (MPC) while single stepping through the microprogram. The LOC and NXT
columns provide useful information relating to the path taken by the microprogram.
The flow is well commented and should be self-explanatory. Table 9-3 is a useful glossary of flow notation.

Table 9-3
Flow Notation Glossary
Definition

Designation
BA

Bus Address Register
Assignment operator
Separator

DATI

Initiate DATI operation on Unibus.

Plus, the arithmetic operator

Program Counter = R 7

CKOFF

Set the Clock Off bit of the control store.

B-Ieg register

Instruction Register

BSex

B-Ieg register sign extended (bit 7 repeated in bits 8 through 15)

R [S]

Scratch Pad Register specified by the source portion of the current instruction [IR (8:6)].

R [D]

-Scratch Pad Register specified by the destination portion of the current instruction [IR

(2:0)].
R [n]

Scratch Pad Register n specified by the control ROM

BUT

Branch on micro test

ALBYT

Allow byte Unibus reference

BYTE.BAR

A signal indicating the absence of a byte in instruction

ENABOVER

Enable the stack overflow detection logic (working BUT)

DATO

Initiate DATO operation on Unibus.

DATIP

Initiate DATIP operation on Unibus.

INIT

Initialize the logic (working BUT).

9-12

Table 9-3 (Cont)
Flow Notation Glossary
Designation

Definition

SVS

Set slave sync (working BUT).

IRC

Clock the Instruction Register (working BUT).

K [n]

That location of the constants chip (on the data path A-leg) containing the value n.

R [10] OPB

ALU function determined by the auxiliary ALU control logic as a function of the
instruction currently in the Instruction Register.

GOTOX

NXT field is to contain the address of X. Unconditional GOTO.

To illustrate the interpretation of PDP-II instructions, the execution of a CMP instruction is traced through the
microcode. The machine is in the RUN state (i.e., the machine is executing instructions) and the instruction is
located in memory location 1000.
Location

Assembler Symbolic

Octal

1000
1002
1004

CMP #15, CHAR

022767
000015
000100

1106

CHAR: WORDO

This instruction compares the literal 15 to the contents of CHAR and sets the condition code accordingly. Source
mode is immediate (mode 2, register 7 = PC) and destination mode is relative (mode 6, register 7 =PC). Figure 9-4
shows the Simplified flow for the CMP example.
CONSOLE
(START OR CONTINUE)

BUT SERVICE

(ADDRESS MODE 6)

FETCH
11-1215

Figure 9-4 CMP # 15, CHAR (022767), Simplified Flow Diagram
9-13

First the instruction is fetched from memory (microsteps F-1 through F-5). This is the same fetch microroutine used
to get each instruction from memory and update the PC.
Location

NXT

Microstep
Name

Action

062

053

F-l

BA +- PC: DATI

/Load the Bus Address Register (BA) with
the contents of the PC (R 7) and initiate a
DATI by the Unibus control (BC).

053

365

F-2

B+- PC+2

/Load the B register with the contents of the
PC+2.

365

364

F-3

PC +- B; CKOFF

/Update the PC. CKOFF inhibits execution
of the next microstep until the pending
Unibus transfer (DATI, initiated in F-l) is
complete.

364

061

B, IR +- UNIBUS DATA

/Load the data from the Unibus (instruction
fetched from memory) into the B register
and Instruction Register (IR).

061

001

F-5

B +- B SEX; BUT
IRDECODE

/Sign extend the low order eight bits of the
copy of the instruction in the B register
(used in branch instruction interpretation)
and branch on microtest (BUT) determined
by the IR decode logic. Note that NXT (F-5)
= 1 which is the CS location of the RESERVED instruction microroutine. If the IR
decode logic does not recognize the instruction, no signals are wire-ORed into the MPC
and the RESERVED instruction microroutine (RT -1) is executed by the microprogram. In this example, CMP is recognized
(by the IR decode logic) and 204 is wireORed with NXT (F-5 = 1) to cause the MPC
to be loaded with 205, the location of the
microroutine which operates on source
mode 2 (S2-1).

Comment

Since the instruction is of the double operand group, the next step is to get the source data. Source mode 2 is
autoincrement. (Autoincrement implies one level of deferred addressing.) When used with R7 (the PC), it becomes
an immediate mode.
Location

NXT

205

301

Microstep
Name
S2-1

Action

BA +- R [S];
DATI;ALBYT

9-14

Comment

/Load the BA with the contents of the
register speCified by IR (08:06). The register
will contain the location of the source data
(1002) in this example. Initiate a Unibus
DATI to actually get the data. ALBYT will
allow an odd Unibus transfer, if the IR

Location

NXT

Microstep
Name

Action

Comment
contains
contains
ALBYT,
odd BA
9.3).

a byte instruction and the BA
an odd address. Without the
a Unibus transfer that addresses an
results in a bus error (Paragraph

301

014

S2-2

B +- R [S] + 1 +
BYTE.BAR

/For byte instructions, the autoincrement is
by one, for non-byte instructions, autoincrement is by two. BYTE BAR indicates
that BLG (S2-2) = + 1, and this signal is
conditioned by the logic, such that it is true
(+ 1) only when the IR does not contain a
byte instruction. So actually, R [S] is on the
A-leg of the ALU, CARRY IN is enabled,
and the + 1 constant (enabled only if the IR
does not contain a byte instruction) is on
the B-leg. The ALU function is A + B.

014

244

S2-3

R [S] +-B;

/Update the register which is to be autoincremented. Inhibit the processor clock
until the DATI initiated in S2-1 is complete.
From here, the microroutine is woven back
intoSl-2 [i.e.,NXT (S2-3) =Sl-2].

244

007

Sl-2

B +- UNIBUS DATA;

/Load the source data which has come in
from memory into the B register. The
microcode at this point joins the microroutine associated with source mode 0
(SO-2). Not a byte instruction, so go to SO-2.

007

001

SO-2

R [10] +- B;
BUT DESTINATION

/Source data is stored in the scratch pad
register, R [10], while the destination data
is retrieved. BUT DESTINATION will cause
a microcode branch dependent on IR (3:5).
In this case, the destination mode of 6 will
cause 114 to be wire-ORed into the NXT
(SO-2) = 1, such that the MPC will be loaded
with 115 = LOC (D6-1).

The microroutine starting in D6-1 will get the destination data and perform the operation indicated by the OP code
of the instruction. Mode 6, when used with the PC, requires that the index contained in the word currently pointed
to by the PC be added to the updated PC (address of the index word plus two) to get the location of the source data.
Location

NXT

115

075

D6-1

BA +- PC; DATI

/Initiate the Unibus transfer to get the index
word from memory.

075

077

D6-2

B+-PC+2

/Prepare to update PC to next word.

Microstep
Name

Action

9-15

Comment

Location

NXT

Microstep
Name

Action

Comment

077

057

D6-3

PC +- B; CKOFF

/Update the PC and inhibit the processor
clock until the Unibus DATI initiated in
D6-1 is complete.

057

300

D64

B +- UNIBUS DATA

/Receive the index word into the B register.

300

200

D6-s

B, BA+-B+R
(D); DATI;
BUT JSRMP;
ALBYT; CKOFF;
GOTODl-2

/The actual location of the destination data
is formed by adding the index (in the B
register) to the destination register [IR
(2:0)] , which is the PC in the example. This
address is loaded into the BA, and a DATI is
issued to retrieve the data from memory. As
in S2-1, ALBYT makes odd byte Unibus
transfers legal. BUT JSRMP involves a
collection of logic which examines the contents of the IR to see if the instruction is a
JMP or JSR. If either of these instructions
are present, the appropriate bit is wire-ORed
with NXT (D6-s) =Dl-2 into the MPC, such
that the MPC is loaded with JI-I or 12-1,
respectively for JMP or JSR instruction. In
the example, neither of these instructions
are present and the MPC is loaded with NXT
(D6-s) = Dl-2. CKOFF inhibits the processor clock until the DATI initiated in this
microstep is complete. Note that this is the
first time in this example that memory
reference has not been overlapped with
microprograms.

200

210

Dl-2

D +- UNIBUS DATA;
BUT BYTE

/Receive the destination data from memory.
If the instruction had been a byte instruction (e.g., CMPB), the microprogram would
be diverted to DO-I (for odd byte address)
to get the byte operand into the right half of
the B register. This is not the case in this
example.

210

143

DI-3

R [11] +- B;
BUT UNARY

/It is at this point in the microroutine that a

B+-R [10] OPB;
BUT NON MOD

/This rnicrostep allows the AUX ALU
control ROM (print DPF) to: 1) cause the
ALU to perform the appropriate function,
and 2) set or clear condition codes in

163

334

Dl4

branch occurs for unary instructions (e.g.,
SWAB, CLR, COM, etc.). Unary instructions
would have caused the BUT IR DECODE
done in F-S to take the appropriate destination rnicroroutine (there is no source field
in a unary instruction). R [II] is used in
unary instruction interpretation.

9-16

Location

NXT

Microstep
Name

Comment

Action

accordance with the instruction in the IR
and the results of the ALU operation. In the
example, it is the setting of condition codes
which count. Since CMP is an instruction
that does not modify memory, (NONMOD),
the microprogram is ready to branch to the
microstep in which a BUT SERVICE is
done. If the instruction requires a memory
modification (e.g., MOV, ADD, INC., etc.),
Dl-5 and Dl-6 are executed before going to
BUT SERVICE.

335

040

B2-2B

/ At the end of each instruction, various
situations that attempt to intervene before
the next instruction are tested. Their priorities are arbitrated in the F101 ROM shown
on print CONE. These conditions and their
relative priorities are as follows:

BUT SERVICE

High priority

I.
2.

T-bit trap
Stack overflow
3. Power fail
4. Bus request level 7
5. Bus request level 6
6. Internal line clock
7. Bus request level 5
8. Bus request level 4
9. UART receive
10. UART transmit
II. Console stop
Low priority 12. Next instruction

If no condition with a higher priority exists,
the microprogram proceeds to F-1 and commences with the fetch of the next instruction.

This completes the example of the microprogram interpretation of CMP #S, CHAR. It may be useful to trace this or
some other instruction through the detailed flow (K-WL-KD11-B-l).
9.5.2 Interrupts and Traps
Interrupts and traps are also accomplished by the microprogram. Interrupts are sent from Unibus devices; bus
requests (BR) are received by the BC. At the end of each instruction (not microstep), if a BR is present, and if it has
the highest priority (see microstep B2-2 in previous example), the microprogram goes to BG-I. In BG-1, a BUT
INTERRUPT is done to distinguish BRs that are associated with interrupts from those that are not. If an interrupt is
required, the microcode is diverted to INT -1 where the interrupt vector location is loaded into R (I2) from the
Unibus data lines. At this point, the microprogram joins the ET-2 microroutine, which stacks the PSW and PC and
retrieves a new PSW and PC from the interrupt vector words. At the end of microroutine ET-13, another BUT
SERVICE is done to determine if anything (e.g., another higher priority interrupt or the occurrence of stack
overflow) is asserted. If none are, the microprogram proceeds to F-1 where it commences to fetch the next
instruction.
9-17

Power fail trap, stack overflow trap, and T-bit traps are also recognized during BUT SERVICE. Each of these
routines has a microroutine associated with it that loads the B register with the appropriate trap vector location
(from the constants ROM, E025 on print DPB). In each case, the microprogram joins the ET-2 micro routine which
stacks the PSW and PC and loads the new PSW and PC, just as with external interrupts. The main difference is that
the vector location comes from the constants ROM rather than from the UNIBUS DATA.
Bus error traps are treated differently since they may prevent an instruction from being completed. When a bus error
is detected, the NXT field of the CS (E092 and E103 on print CONG) is disabled, and the microprogram is forced to
ERT-l. This micro routine picks up the respective trap vector location from the constants ROM, and from that point
on, operates like all other traps. The difference is the method in which the microprogram gets to ERT-l.
9.5.3 Console Functions
When the processor is in the HALT state, the microprogram is looping on microstep H-2 doing BUT SWITCH. As a
console switch is activated, the microprogram branches to an associated microroutine. Additional logic intervenes to
distinguish the first of a sequence of examines or deposits. This is illustrated in the following examples.
Assume that the console operator wants to examine locations 1000 and 1002. The processor is in the HALT state,
with the microprogram looping on microstep H-2. First the operator must set the switches to 1000 and depress
WAD ADRS. The BUT SWITCH then causes the microprogram to branch to CL-l.

Location

NXT

302

300

H-2

BUT SWITCH

/Loop on H-2 waiting for switch action.
When LOAD ADRS is depressed, branch to
CLot.

311

375

CL-l

BA +- K [207].
BAR *;DATI;
CKOFF

/The SR is logically on the Unibus at
location 177570. This constant is obtained
from the 8-bit wide constants ROM (F25 on
DPB print) by taking 207 and forming the
complement through the ALU on the way to
the BA. A request for the contents of the SR
is initiated (DATI) and the processor clock is
inhi bited until the data is available
(CKOFF).

375

367

CL-2

B +- UNIBUS DATA

/Since the SR is physically on the A-leg of
the data path (DP) (prints DPA, DPB, DPC,
and DPD), it cannot be written directly into
register 17 of the scratch pad; instead, it is
first loaded into the B register.

367

302

CL-3

R [17] +- B;
GOTO H-2

/Load SR into the Load Address Register, R
[17] . Microprogram goes to H-2.

BUT SWITCH;
GOTO,H-2

/Loop here looking for switch activity. The
microprogram loops on CL-l, CL-2, CL-3,
and H-2 as long as LOAD ADR is depressed.

Microstep
Name

H-2

*(207). BAR

Action

= 1's complement of 207

9·18

Comment

Now the operator has loaded 1000 from the SR into the Load Address Register R [17]. The lights are attached to
the B register and will display the loaded address.
To examine location 1000, the operator depresses EXAM. As long as the EXAM switch is depressed, the location to
be examined is displayed in the lights. When it is released, the contents of that location are displayed.
Action

Comment

Location

NXT

Microstep
Name

317

307

CEI-I

BA,8+-R [17];
BUT SWITCH

/The lights are connected to the B-Ieg. By
loading the B register with the contents of
the Load Address Register, R [17], the
address of the location is displayed. The BA
is also loaded for subsequent retrieving of
the data. BUT SWITCH causes the microprogram to loop on CEl-l until EXAM is
released.

307

326

CEl-2

DATI;CKOFF

/When the switch is released, the data is
requested from the Unibus, and the processor clock is inhibited until it is available.

326

302

CEl-3

B +- UNIBUS DATA;
GOTO H-2

/Display the data by loading it into the B
register and return to the H-2 microprogram
loop to await the next switch action.

While the microprogram loops in H-2, the B register remains unchanged and the contents of location 1000 are
displayed. When EXAM is depressed a second time, the logic associated with FlOO (print CONE) causes BUT
SWITCH in H-2 to branch the microcode to CE2-l. In this case, the Load Address Register must be incremented
before using its contents.
Microstep
Name

Action

Comment

Location

NXT

302

300

H-2

BUT SWITCH

/Loop waiting for switch action.

315

371

CE2-l

B+-R[17]+2

/Increment the Load Address Register so
that sequential words can be examined.

371

317

R[17]+-B;
GOTO CEl-l

/Update R [17]. The rest of this microroutine merges with CEl-i.

317

307

CEl-}

BA, B +- R [17];
BUT SWITCH

307

326

CEl-2

DATI;CKOFF

326

302

CEl-3

B +- UNIBUS DATA;
GOTOH-2

CE2-2

This completes the example of console function microroutines. The remaining console functions are quite similar.

9-19

9.6 MICROPROGRAM SYMBOLIC LISTING
The microprogram section of the prints (K-MP-KDll-B-l through 4) contains four useful tools. Paragraph 9.5
describes the microprogram flow. Flow is probably the most useful level to work with the microprogram when
tracing through processor action on any specific operation. Flow tells what happens in each microstep and why. To
determine how a microstep accomplishes its task, refer to the Microprogram Symbolic Listing (K-MP-KDII-B-2), an
excerpt of which is shown in Figure 9-5. In this listing, microsteps are listed alphabetically (e.g., F-l, F-2 ...). Each
of the CS fields described in Table 9-1 is listed along with its symbolic values. For example, in F-2 of the example in
Paragraph 9.5.2, flow indicates:
F-2

PC + 2

The symbolic listing is useful for determining how this is to be accomplished in terms of CS fields (e.g., ALU
function). Refer to the excerpt in Figure 9-5 and scan the alphabetically-ordered list of names for F-2.

A-leg
ALU function
B-leg
B Register
Carry In

(ALG)
(ALU)
(BLG)
(BRG)
(CRI)

SP (scratch pad)
A+B
+ 1 (the constant)
L (load)
ON

Scratch Pad Address
Scratch Pad Function

(SPA)
(SPF)

R7 (the PC)
REA (read)

Next MPC

(NXT)

= F-3 (go to F-3 next)

B ~ PC + 2 is accomplished by gating register 7 (the PC) onto the A-leg of the ALU, gating + 1 onto the B-leg, and
causing the ALUto perform an A + B operation (=R7 + 1) with Carry In enabled (=R7 + 1 + carry in). The B register
is loaded with the results, and the MPC is loaded with the address of F-3, which is the next microstep.
Only eight of a total of eighteen fields are described in the above example. The rest of the fields have values but they
are not of immediate interest.
9.7 MICROPROGRAM BINARY LISTING
In addition to the flow and symbolic listing, a binary listing of the CS is included in the microprogram section of the
prints (K-MP-KDlI-B-3). An excerpt is shown in Figure 9-6. As in the symbolic listing, the binary listing is
alphabetically ordered by microstep name. The fields are located across the top of the listing; however, they relate
closely to the actual signals (Figure 9-1). A high is represented by a 1 in this listing.
From the previous example, flow indicates F-l B ~ PC + 2. The symbolic listing shows that the ALU function to
accomplish this is A + B; the binary listing shows the actual logic level value of CONF ALU S3 L, CONF ALU S2 L,
CONF ALU Sl L, CONF ALU SO L, and CONF ALU MODE H (Figure 9-1 and 9-6). Notice that these five signals
are grouped together under the heading ALU. They physically come from chips E104 and E094. The binary listing is
spaced to show signals grouped both by field (ALU) and chip (E104 and E094).
If the PC is not being properly incremented during program execution, the flow may be used to determine what is
supposed to happen during the fetch microroutine; the symbolic listing is used to determine how it is to be
accomplished. If the symbolic listing does not identify the problem, use the binary listing and an oscilloscope probe
to locate the incorrect signal and/or malfunctioning chip.

9-20

KDll-B MICROPROGRAM SYMBOLIC LISTING
AUX BAR BLG BRG BUT CON CKO CRI

NAME

LaC ABT ALG ALU

DO-9
ERT-l
ERT1A
ERTlB

132
010
046
153

NO
NO
NO
NO

SP
NUL
NUL
NUL

BL
AL
AL
AL

OFF
OFF
OFF
OFF

H
H
H
H

SEX
BRG
BRG
BRG

L
L
L
L

UNY
CON
CON
CON

NON
4
4
4

OFF
OFF
OFF
OFF

ET-l
ET-l0
ET-ll
ET-12

011
254
255
256

NO
NO
NO
NO

NUL
SP
SP
SP

AL
AL
AL
A+B

OFF
OFF
OFF
OFF

H
L
L
L

BRG
BRG
BRG
+1

L
H
L
L

CON
IRC
NON
NON

30
NON
NON
NON

ET-13
ET-2
ET-3
ET-5

257
245
246
247

NO
NO
NO
NO

SP
SP
SP
SP

AL
BL
A-B-1
BL

OFF
OFF
OFF
OFF

H
H
L
H

BRG
BRG
+1
BRG

L
H
L
H

NON
NON
END
NON

ET-6
ET-7
ET-8
ET-9

226
251
252
253

NO
NO
NO
NO

PSW AL
SP
A-B-1
SP
BL
AL
SP

OFF
OFF
OFF
OFF

H
L
H
H

BRG
+1
BRG
BRG

H
L
H
H

ET2-2
ET2-3
ET2-5
ET2-6

003
036
037

NO
NO
NO
NO

SP
BL
SP
A-B-1
SP
BL
PSW AL

OFF
OFF
OFF
OFF

H
L
H
H

BRG
+1
BRG
BRG

ET2-7
F-1
F-2
F-3

051
062
053
365

NO
NO
NO
NO

SP
SP
SP
SP

A-B-1
AL
A+B
BL

OFF
OFF
OFF
OFF

L
L
H
H

F4
F-5
H-1
H-2

364
061
041
302

NO
NO
NO
NO

NUL
SP
SP
SP

AL
BL
AL
AL

OFF
OFF
OFF
OFF

INT-1
IT-1
Jl-1
J1-2

325
273
204
260

NO
NO
NO
NO

SP
NUL
SP
SP

AL
AL
AL
BL

J2-1
J2-1 A
J2-2
J2-3

212
261
262
214

NO
NO
NO
NO

SP
SP
SP
SP

J2-4
J2-5
J2-6
J2-7

206
216
263
264

NO
NO
NO
NO

J2-8
LO-1
MB-O
MB-l

265
042
154
242

NO
NO
NO
NO

004

PSW SAM SPA

SPF

TNS NXT

OFF
OFF
OFF
OFF

H
H
H
H

ROM
ROM
ROM
ROM

Rll
RO
RO
RO

WRI
WRI
WRI
WRI

NON
NON
NON
NON

A145
ET-2
ET2-2
ET-2

OFF
ON
OFF
ON

OFF
OFF
OFF
ON

H
H
H
H

ROM
ROM
ROM
ROM

RO
R12
R7
R12

WRI
REA
WRI
REA

NON
I
NON
I

ET-2
ET-ll
ET-12
ET-13

NON
NON
NON
NON

OFF
OFF
OFF
ON

OFF
OFF
OFF
OFF

L
H
H
H

ROM
ROM
ROM
ROM

RO
R12
R6
R6

REA
WRI
REA
WRI

NON
NON
NON
a

B2-2
ET-3
ET-5
ET-6

NON
END
NON
NON

NON
NON
NON
NON

OFF
OFF
ON
OFF

OFF
OFF
OFF
OFF

H
H
H
H

ROM
ROM
ROM
ROM

RO
R6
R6
R7

REA
REA
WRI
REA

NON
NON
a
NON

ET-7
ET-8
ET-9
ET-l0

L
L
H
H

NON
NON
NON
NON

OFF
OFF
ON
OFF

OFF
OFF
OFF
OFF

H
H
H
H

ROM
ROM
ROM
ROM

R12
R6
R6
RO

WRI
REA
WRI
REA

NON
NON
a
NON

ET2-3
ET2-5
ET2-6
ET2-7

+1
BRG
+1
BRG

L
H
L
H

NON
NON
NON
NON

OFF
OFF
OFF
ON

OFF
OFF
ON
OFF

H
H
H
H

ROM
ROM
ROM
ROM

R6
R7
R7
R7

REA
REA
REA
WRI

NON
I
NON
NON

ET-8
F-2
F-3
F4

H
H
H
L

BRG
SEX
BRG
BRG

L
L
L
H

IRC
IRD
NON
SW

NON
NON
NON
NON

OFF
OFF
OFF
OFF

H
H
H
H

BAR
ROM
ROM
ROM

RO
RO
R7
R17

REA
REA
REA
REA

NON
NON
NON
NON

F-5
RT-l
H-2
06-5

OFF
OFF
OFF
OFF

H
H
H
H

BRG
BRG
BRG
BRG

H
L
H
H

SVS
CON
NON
SRV

NON
20
NON
NON

OFF
OFF
OFF
OFF

H
H
H
H

ROM
ROM
ROM
ROM

R12
RO
RO
R7

WRI
WRI
REA
WRI

NON
NON
NON
NON

ET-3
ET-2
Jl-2
BG-l

AL
BL
A-B-l
BL

OFF
OFF
OFF
OFF

H
H
L
H

BRG
BRG
+1
BRG

H
H
L
H

NON
NON
NON
NON

OFF
OFF
OFF
ON

OFF
OFF
OFF
OFF

H
H
H
H

ROM
ROM
ROM
ROM

RO
Rll
R6
R6

REA
WRI
REA
WRI

NON
NON
NON
a

J2-1A
J2-2
J2-3
J24

SP
SP
SP
SP

AL
AL
BL
AL

OFF
OFF
OFF
OFF

H
H
H
H

BRG
BRG
BRG
BRG

H
L
H
L

ENO
NON
NON
NON

NON
NON
NON
NON

OFF
OFF
OFF
OFF

H
H
H
H

IRS
ROM
IRS
ROM

RO
R7
RO
Rl1

REA
REA
WRI
REA

NON
HaN
NON
NON

J2-5
J2-6
J2-7
J2-8

SP
NUL
SP
SP

BL
AL
AL
ABAR

OFF
OFF
OFF
ON

H
H
H
H

BRG
BRG
BRG
BRG

H
L
H
L

SRV
CON
NON
NON

NON
100
NON
NON

OFF
OFF
ON
OFF

OFF
OFF
OFF
ON

H
H
H
H

ROM
ROM
ROM
ROM

R7
RO
RO
R10

WRI
WRI
REA
REA

NON
NON
NON
NON

BG-l
ET-2
MB-l
MB-2

Figure 9-5 Excerpt of (K-WL-KDlI-B-2) Microprogram Symbolic Listing

9-21

N
A
M

L
0
C

00-lB
00-2
00-3
00-4

143
123
124
125

1100
1010
1010
1010

00-5
00-6
00-7
00-8

126
127
132
131

00-9
ERT-l
ERT1A
ERT1B

N
X
T

A
L
U

CFA
RRU
I EX

P SS 0
S P PI
W13P

1010
1011
1010
1001

0000
0000
0000
0000

1 001
1 001
1001
1 001

1001
1 001
1001
1 001

10 1
10 1
1 01
10 1

1
1
1
1

110
110
~ 10
110

1010
1010
1010
1010

1000
0111
0110
0101

0000
0000
0000
0000

1 001
1 001
1 001
1 001

1 001
1 001
1 001
1001

10
10
10
10

1
1
1
1

132
012
046
153

1001
0101
lml
0101

1010
1010
1100
1010

0101
0000
0000
0000

1 001
1 001
1 001
1 001

10 11
1101
1 1 01
110 1

11
10
10
10

1
1
1
1

ET-l
ET-l0
ET-l1
ET-12

011
254
255
256

0101 1010 0000
0101 0010 0000
0101 0001 0000
0101 0000 0110

1 001
1 001
1 001
01 01

1
1
1
1

ET-13
ET-2
ET-3
ET-5

257
245
247
247

0011
0101
0110
0110

0000
0101
0101
0101

1 001
1 001
1 001
1 001

ET-6
ET-7
ET-8
ET-9

226
251
252
253

0101 0110 0000
0101 0101 1001
0101 0100 0101
0101 0011 0000

ET2-2
ET2-3
ET2-5
ET2-6

003
036
037

1111
1110
1110
1101

1011
0001
0000
0110

ET2-7
F-l
F-2
F-3

051
062
053
365

0101
1101
0000
0000

F-4
F-5
H-l
H-2

364
061
041
302

INT-l
IT-l
Jl-l
Jl-2

325
273
204
260

004

S SS B
MPMB
001 T

BBSS
ATPP
RP F2

CAT
KBN
OTS

G G

0001
1 1 11
1 1 11
1 1 11

11
11
11
11

01
10
00
10

1111
1111
1111
1111

10
10
10
10

1
1
1
1

11
11
11
11

10
10
10
10

1111
1111
1111
1111

1
1
1
1

1000
1 1 01
110 1
1 1 01

1
1
1
1

11
11
11
11

11
10
10
10

11
11
11
11

1010
1101
1101
1101

10 11
10 11
1111
1 01 0

1110
01 1 0
01 01
01 1 0

11
01
11
01

11
10
11
10

10
11
11
11

11
00
11
11

1101
0000
1111
1111

0001
1111
110 1
110 1

10
10
10
10

1
1
1
1

110
1 00
10 1
10 1

11
11
01
01

11
11
11
11

11
00
00
00

1111
1111
1111
1111

1 001
0001
1 001
1001

1 001
110 1
110 1
1101

10 11
1 01 0
10 11
1111

1
o
1
1

110
111
10 1
111

11
11
01
11

00
11
11
11

00
11
00
00

1111
0100
1111
1111

0101
1001
0101
0000

1 001
0001
1 001
1 001

1111
1 1 01
1101
1 001

10 11
1 01 0
10 11
10 11

1
o
1
1

1 00
111
10 1
110

11
11
01
11

11
11
11
00

11
11
00
00

1111
1111
1111
1111

0131
0100
1010
1011

1001
0000
0110
0101

0001
1 001
01 01
1 001

1
1
1
1

1 01 0
1111
1110
1111

o
o
1
1

11
11
11
10

11
11
11
01

11
10
11
11

11
11
11
11

11
00
11
001

1111
1111
1111
1111

1100
1111
0011
0011

1110
1110
1101
1111

0000
0101
0000
0000

1 001
1 001
1 001
1 001

1 001
1 001
1101
1111

0001
10 1 1
1111
1111

1110
1 01 0
o111
o111

1
1
1
1

11
11
11
11

10
11
11
11

11
11
11
00

0000
0111
1111
0110

0101
0101
0100
1101

1001
1010
1111
1111

0000
0000
0000
0101

1 001
1001
1 001
1001

1111
1 001
1 001
1101

10
10
10
11

1 1 00
1111
11 10
110 1

11
11
11
11

11
10
11
11

00
11
00
00

1000
1101
1111
1100

1010
1001
1001
1001

10
11
10
11

10
10
10
10

1
1
1
1

A B
L R

B
U
T

Figure 9-6 Excerpt of Microprogram Binary Listing (K-W-KD II-B-3)

The following example is used to show the interrelation of the microprogram listings and the logic prints in checking
the generation of control signals from the CS ROMs. SpeCifically, the example deals with the generation of the SPM
enabling signals during a microprogram step that requires an SPM read operation. It is a simplified example because
only the SPM enabling signals are examined in detail. The address lines, input data, and output data are not
examined.

9-22

The example chosen is step CCM-2 of the microprogram symbolic listing (print KDII-B-2, sheet 2). The items of
interest in this example are as follows.
Name

Location

ALG

CKO

SPF

CCM-2

350

OFF

REA

The step's name is CCM-2 and its location in the CS ROMs is 350 8 , Table 9-1 describes the CS fields.
The ALG field is the A-leg control and determines what is enabled onto the A-inputs of the ALU. In this case, SP
indicates the contents of the scratch pad memory.
The CKO field determines whether the processor clock is running or is inhibited until the pending Unibus transfer is
complete. The notation OFF means that the CKO field has no effect, so the processor clock is running.
The SPF field determines the scratch pad memory control function. The notation REA means that a read operation
is selected.
The binary equivalents of the CS field bits are obtained from the microprogramming binary listing (print KDl1-B-3,
sheet 2).
Name

Location

SPF

CKO

CCM-2

350

1
(13)

(11)

ALG
I I
(07,06)

The CS field bit is shown below the binary representation. The CS field bits run from 00-39, starting with 00 at the
right.
In this example, the four signals generated from CS fields ALG, CKO, and SPF are all logical 1.
Refer to Figure 9-1 to determine the signal associated with these fields and the designation of the CS ROM that
generates the signal.
The following information is obtained from Figure 9-1.
Field

Bit

ALG
ALG
CKO
SPF

06
07
11

Signal
CONG
CONG
CONG
CONG

ROM ALEG 0 L
ROM ALEG 1 L
CKOFF L
SP WRITE L

ROM
E093
E093
EI07
E095

As previously stated, the purpose of this example is to verify the generation of the SPM enabling signals during a
microprogram step that requires an SPM read operation. The last step in the procedure is to trace the signal flow
through the logic prints. As a visual aid, all the logic involved is shown in a Simplified logic diagram (Figure 9-7). The
one exception is the processor clock logic which is not discussed in detail.

In accordance with the function table for the 7489 SPM, during a read operation the E-input is low and the W-input
is high (Figure 8-11). This means that signal DPA SP WRITE L must be high and CONG ENAB SPL Land CONG
ENAB SPR L must both be low because a word is being read. Signal DPA SP WRITE L is generated by NAND gate
E070 (print DPA) which has two inputs. One input is CON] PROC CLOCK H which is active because the clock is

9-23

PRINT CONG

PRINT DPA
CONG SP WRITE L

23-A07A2
E095
II

CONG SP WRITE H

*
L ______ _
DPA SP WRITE L

eONJ PROe CLOCK H

ROM

23-A05A2 09
eONG ROM ALEG 0 L
E093
D---=-=---"-'''''-'-'='''--''--=---,

CONG ROM ALEG 1 L

eONG ENAB SPL L

eONG ENAB SPR L

ROM

* SPM ENABLING

SIGNALS
1\-1560

Figure 9-7 Generation of SPM Enabling Signals
running; therefore, it is high when a clock pulse is generated. The other input is CONG SP WRITE H and must be
low to generate DPA SP WRITE L = 1. Signal CONG SP WRITE H is the inversion of CONG SP WRITE L which is
generated by CS ROM E095. In this example, the microprogramming binary listing states that CONG SP WRITE L =
1. This signal is inverted by E079 to give CONG SP WRITE H = 0 which is the desired input to E070 (print DPA).
Signal CONG ENAB SPR L is the inversion ofCONG ROM ALEG 0 L, which is generated by CS ROM E093. In this
example, the microprogramming binary listing states that CONG ROM ALEG 0 L = 1. This signal is inverted by
E077 to give CONG ENAB SPR L =0, which is the desired signal.
Signal CONG ROM ALEG 0 L = 1 is also an input to NAND gate E086. The other input is CONG ROM ALEG 1 L =
1 as stated in the microprogramming binary listing. These signals produce CONG ENAB SPL L =0 at the output of
E086, which is the desired signal.
The signals generated by the CS ROMs can be checked by examining the ROM listing (print M7261-0-8). The listing
is by ROM part number.
In this example, examine octal address 350 for each ROM referenced to determine the state of the desired signal.
The ROM part numbers are listed below.
Output Signal

ROM Part No.

ROM Designation

23-A05A2

E093

{ CONG ROM ALEG 0 L
CONG ROM ALEG 1 L

23-A07A2

E095

CONG SP WRITE L

23-A14A2

El07

CONGCKOH L

9.8 MICROPROGRAM CROSS REFERENCE LISTING
The microstep name (e.g., F-2) is the key that ties the flow, symbolic, and binary listings together. When working
with the processor, it is often useful to determine the name of a microstep from a location or vice versa. This
information is provided in the cross reference listings (K-MP-KDII-B4 in the microprogram section of the prints).

9-24

CHAPTER 10
KDII-B AND CONSOLE MAINTENANCE

10.1 INTRODUCTION
This chapter describes techniques for isolating and repairing failures in the KDII-B and the console. The basic
procedures are aimed at differentiating between failures in the processor and the remainder of the computer. If the
processor is at fault, it is necessary to determine which of the two KD-Il B modules is defective. The KMII
maintenance panel may be used in conjunction with the KDll-B documentation to isolate failure to specific
integrated circuits.
The easiest method of isolating failures and determining if a system will function under worst-case conditions is to
use diagnostic programs that have been designed by DEC to test the processor and memory. For most DEC
computers, it is possible to assemble a hierarchy of diagnostics that progressively tests more and more of the
computer. With large systems, it is possible to test the KDII-B beyond its performance specifications. Diagnostic
programs are written and commented in a manner that guides the user in determining computer malfunctions.
This chapter also describes special techniques for troubleshooting the KDII-B. The exact determination of failures
and their repair requires careful application of the tools described in this chapter, in addition to a general knowledge
of PDP-II systems. A section on console maintenance provides a console troubleshooting procedure.
10.2 DIAGNOSTICS
The diagnostic programs supplied by DEC prOvide a rigorous test of the computer that can indicate the need for
service even before a failure occurs. Preventive maintenance is especially important on machines that include
mechanical components, such as line printers or tape drives.
10.3 TYPES OF FAILURES
Failures can be broken down into three classes: basic, complex, and peripheral. A basic failure of the processor,
memory, or program read-in device does not permit diagnostic software to be loaded; thus, fault isolation and repair
in a computer with a basic failure requires an elementary approach. A complex failure typically occurs only with
programs that generate interaction on the Unibus between several peripherals and the processor. DEC proVides a
number of system diagnostics, such as the General Test Program (GTP) and the Communications Test Program
(CTP), that are useful in isolating complex failures.
Often the failure is caused by a peripheral problem that is unrelated to the processor or memory. In this case, the
processor itself may be used as a troubleshooting tool. For example, a diagnostic program is available that tests the
alignment of a TUI0 Magnetic Tape Drive and reports Significant parameters via the serial communications line
(SCL).
10.4 SUGGESTED EQUIPMENT
Table 10-1 provides a list of test equipment, maintenance devices, and tools used to perform the processor
maintenance procedures and adjustments.

10-1

Table 10-1
Test Equipment and Tools
Equipment
Test Equipment:

Devices:

Description

Oscilloscope

Tektronix Model 453 (or equivalent)

Volt-ohmmeter

Triplett Model 630 (or equivalent)

Extender Board

Three W984A Double Extender
Boards

Maintenance Module Set

One W130 (two are desirable)
One W131 (two are desirable)

Maintenance Module Overlays

KMI-DEC Part No. 55-09081-9
KM2-DEC Part No. 55-09081-10

IC Test Clip
Tools:

Small Flatblade Screwdriver

10.5 PROCEDURES
It is useful to know the precise condition of the computer at the time of the failure. The user is advised to record the

state of the computer, in as much detail as needed, to reproduce the problem when a failure occurs. At least the
following information should be noted:
a.
b.
c.
d.

Any peripherals attached to the Unibus not usually present.
The name of the program running when the failure occurred.
The state of the processor indicators ( console) when the failure occurred.
If pOSSible, the sequence of events preceding the failure should be noted.

When running a program on the KDII-B for the first time, it should be noted that certain subtle differences exist
among the several PDP-II processors that can cause problems when non-standard programming practices are used. A
list of differences between the KDII-B and other PDP-II processors is contained in Table 6-8.
Once it is established that a hardware failure exists, the following checks are advised before dismantling the
computer:
1.

Verify that the power supply is attached to a live ac source and is functioning normally.

Verify that the Unibus is properly routed.

Be certain that grant continuity cards are properly placed whenever missing peripherals would break the
BUS GRANT lines.

Be certain that no Unibus address conflicts exist.

10-2

Programs can be executed from the scratch pad memory (SP) locations, and if processor problems are suspected, this
procedure should be tried to isolate the problem. Communication between the console and processor must be
functioning properly in order to use this procedure, and is the first thing to check when a processor problem is
suspected. Executing programs from the SP is advantageous for troubleshooting or checking the processor. When
executing a program from the SP, the PC (R7) is incremented by one; however, BR instructions always modify the
PC by multiples of two. Consequently, a BR instruction must be carefully used in a program to prevent the PC from
being modified to an incorrect address. An example of a simple program that loops on two SP register locations is as
follows:
Address

Instruction

Octal

1177700 (RO)
177701 (Rl)

NOP
BR.-l *

000240
000777

To load the above program from the console, perform the following steps:
1.

Enter 177700 in the Switch Register and depress LOAD ADRS (this is the address of register 0).

Enter 000240 in the Switch REgister and lift DEP. (This places a NOP instruction in RO.)

Enter 000777 in the Switch Register and lift DEP.

Enter 177700 in the Switch Register and depress LOAD ADRS (this specifies the starting address).

Lift ENABLE/HALT to the ENABLE position.

Depress START. The RUN light should come on. The program is now being executed.

If ENABLE/HALT is pressed, the ADDRESS/DATA display should contain either 177700 or 177701.

When executing programs from the SP (registers), do not use the registers used by the processor (R6, R7, RIO, Rll,
R12, and R17).
10.6 ADJUSTMENTS
Adjustments to the processor are as follows:
1.

The processor clock should have a 310-ns period. Adjust, if necessary, performing the following
procedures:
a.

Extend the M7261 module.

With an oscilloscope, observe the processor clock at E045 pin 6.

Adjust the potentiometer on the M7261 until the processor clock period is 310 ns.

Remove oscilloscope probe and reinsert the M7261 module.

* 777. is normally a BR self-instruction. However, when executed from the SP, it is a BR. -1, because the SP registers are located
on BYTE ADDRESSES.

10-3

The SCL clock frequency should be 16 times the desired baud rate. Adjust, if necessary, using the
following procedure:
a.

Extend the M7260 module.

With an oscilloscope, observe the SCL clock at E084 pin 6.

Adjust potentiometer R74 for 16 times the desired baud rate, according to Table 10·2.

Remove oscilloscope probe and reinsert the M7260 module.

Table 10·2
Baud Rate Adjustment
Baud Rate

Period (J.ls)

110
150
300

568
416
208

Frequency (Hz)
1760
2400
4800

An alternate method for adjusting the SCL clock that does not require extending the module, is to run any program,
such as T·17, that causes a continuous stream of characters to be printed on the console. The potentiometer on the
M7260 should then be adjusted to the center of the range for which satisfactory characters are printed.
10.7 KD11·B PRINT FUNCTION TABLE
The principles of operation of the KD11·B logic are described in Chapter 8. The microprogram is described in
Chapter 7. The KD11·B print set is described in Chapter 7. The KDll·B print set is described in ChapterS. Table
10·3 lists each engineering drawing for the KDll·B processor and describes the functions of the items shown on that
drawing.

Table 10-3
Engineering Drawing Print List and Functions
Print Designation

Function of Logic on Print

Print Title

D-CS·M7260·0·01
DPA

Data Path (3:0)

This print contains the least Significant four bits of the DP
components, including the ALU, the scratch pad, the B
register, the AMUX, Unibus data drivers and receivers, and
additional A·leg gating for the PSW and console switches.
Prints DPB, DPC, and DPD contain the three other 4·bit
parts of the data path.

DPB

Data Path (7:4)

In addition to the items mentioned above, DPB contains
the constants generator.

10-4

Table 10-3 (Cont)
Engineering Drawing Print List and Functions

D-CS-M7260-0-01
(Cont)
DPC

Function of Logic on Print

Print Title

Print Designation

Data Path (11 :8)

Same as DPA

DPD

Data Path (15:12)

Same as DPA

OPE

PSW

OPE contains the 8-bit PSW and the multiplexers required
to load it. Rotate multiplexers are also shown on OPE. The
console (MUX shown in the lower right-hand corner of
DPE) converts the data presented on the B-leg into a serial
bit stream for the console display.

DPF

AUX ALU CONTROL

In addition to the auxiliary ALU control, the Instruction
Register (IR) and the C- and V-bit encoder are shown on
DPF.

DPG

IRDECODE

The major elements of the IR decoder are shown on DPG.

DPH
and
DPHI

SCLCONTROL

The UART and other elements of the SCL control are
shown on DPH and DPHI.

CONA

INT ADDR

The Bus Address Register (BR) is shown on the left side of
CONA. On the right half of the print, the logic required to
detect reference to internal registers is diagrammed.

CONB

ST ACK FLOW AND
SPAM

The left half of CONB contains the Scratch Pad Address
Multiplexer (SPAM) while the right side contains the stack
overflow and RUN flip-flops.

CONC

UNIBUS CONTROL
(BC)

Data requests flip-flops are shown towards the left edge of
CONe. The lower right-hand quarter of the print contains
bus error and CKOFF flip-flops. The 9602 that detects
non-existent memory is shown in the lower left-hand corner
ofCONC.

CONCI

PRIORITY
ARBITRAnON

The priority arbitration logic for bus requests is shown
along the bottom edge ofCONCl. Towards the left and top
of CONC I are three 4-bit latches used to hold signals
received from the Unibus. The 9602 shown on the upper
right of CONC I is used to clear the bus if SACK is not
received 22 J1S after NPG or BG.

CO NO

DRIVE AND
RECEIVERS

COND contains all of the Unibus drivers and receivers
except those used for the data lines and two drivers used
for the line clock circuit.

D-CS-M 7261-0-0 I

10-5

Table 10-3 (Cont)
Engineering Drawing Print List and Functions
Function of Logic on Print

Print Title

Print Designation
D-CS-M7261-0-01
(Cont)

MICRO BRANCH
LOGIC

A 4-to-16 line decoder associated with the BUT field of the

CONF

MPC

Sixteen bits of the CS are shown on the left side of CONF.
The MPC is along the right edge of the print.

CONG

CONTROL STORE (CS)

The remaining 23 bits of the CS are shown on CONGo

CONH

POWER FAIL

Initialize and power fail circuitry is shown on CONH. The
9602 contained in the lower left-hand corner of CONH
generates bus instructions during the RESET instruction.

CONI

LINECWCK

The circuit equivalent to the KWI1-L is contained on
CONI.

CONJ

PROCESSOR CLOCK

The circuit consisting of E19, R2, RIO, and Cl15
comprises the oscillator that generates the processor clock.
The input to E02713 is used by the KMll to generate
clock signals from an external source.

CONE

microprogram is located in the upper left of CONE. The
function, switch buffers, and decoders are shown in the
upper middle and upper right. Two flip-flops associated
with the console EXAM and DEP keys are shown in the
lower left and lower center in the trap arbitration logic.

10.8 EXTERNAL CLOCK INPUTS
External clock inputs and corresponding internal clock disables are provided for the serial communications line
(SCL) clock and the processor clock. The external input for the SCL clock permits the reception and transmission of
serial asynchronous data at rates up to 10,000 baud. High baud rate signals should be input on pin FMl of the
M7260, rather than the low frequency input on pin FN1. The SCL clock, its external disable, and external clock
input are shown on print DPH.
The external clock input for the processor clock permits the synchronization of two processors or the use of a
manual clock. The manual clock input and the internal processor clock disable are shown on print CONJ.

10.9 KMll MAINTENANCE PANEL
The discussion to this point has not considered the backplane or configuration. Every KDll-B contains the
necessary logic to permit single step operation; however, the use of these facilities depends on the specific
configuration. Two module slots are provided in the computer for the maintenance panel. Figure 10-1 contains a
diagram of the KM11 overlays for slots KM-1 and KM-2 in the computer backplane (Figures 1-2 and 1-3). Table 10-4
provides deSCription of the overlay deSignations. Note the following:
a.

The KM-1 switches have the same function in slots KM-1 and KM-2.

When the manual clock is enabled, bus error time outs are disabled. Nonexistent memory trap cannot
occur in manual mode.

10-6

Each actuation of the manual clock with line EY1 of the M7261 grounded produces bus control (BC)
clock. It normally requires two BC clock pulses to advance the microprogram counter (MPC) to the next
address.

The MPC is duplicated on both KM11 slots. This permits the user who has only one KMll to plug the
unit into either KM-1 or KM-2.

The MPC displayed on the KM11 is the address of the next microstep to be selected and not the present
one.

Some lights on the maintenance panel indicate the assertion of a signal when illuminated and others
indicate nonassertion when illuminated. This fact is indicated on the KM11 overlay drawing by the letter
B for bright or D for dim appearing under each indicator light.
B =bright for assertion (logic 1)
D = dim for assertion (logic 1)

The wiring for KM-1 appears in slot A2, and the wiring for KM-2 appears in slot B2 for a Configuration 2
backplane. KM-1 and KM-2 are wired to slots Al and B1, respectively, for a Configuration 1 backplane.

KM-1 is the more useful configuration and should be used to begin any repair attempts requiring the use of the
maintenance panel. The console indicators display the B-Ieg input to the ALU, and the KM-1 configuration
maintenance panel displays the output of the AMUX. If the ALU and AMUX are functioning, it is possible to
deduce the contents of the A-leg by observing the console and the maintenance panel.

MPC
3 D
2
1

0
0

0 0

AMUX
70

6
5

0
0

3 8
2
1

8
B

0 8

6
5

8
B

118
10

8
8

8 8

15 8 BUT
JR 0
BBUS"I
0
SSYN
13 B
0
MSYN
12 8
0

,--

BUS SSYN

M,-,
ClK
I

'-'

AC lO

- M ClK

PUlSE-

EN-

(0) KM-l OVERLAY

.----. ,....---.,
AlU

MPC
3 D

SPAD

6 0

0
0

AUXC MSYN
S3 0 ALUM
8
0
0
CIN BUT SSYN
02 8 S20
8 JJ 0
0
EAlU
CI
01
B~
SID
8
0
8 1..1 0
00 8 SOD SPWR CNST CO
0
8
0

03 8

(b) KM-2 OVERLAY
NOTE:
o = Dim when asserted.
B = Bright when _rted.

BUS SSYN

,,-'\

,_/

M,~~K
I

AC lO

M ClK

'-'

PUlSE-

EN-

11-1271

Figure 10-1 KMll Maintenance Module, KDll-B Overlays

10-7

Table 10-4
KM-l and KM-2 Overlay Designations
Display

Definition
KM-IOVERLAY

MPC (7:0)
AMUX (15:0)

The 16-bit C!ll!P.l!.t of the AMUX.

BUTIR

BUT IR DECODE signal. When asserted, the microprogram is at F-5 and does a
branch on the contents of the IR.

BBUSY

BUS BUSY. When asserted, BBSY indicates that a device has control of the Unibus.

SSYN

1'.

\'k \,

-'.~

(" t: ,," ...:, ..:

BUS SLAVE SYNC. When asserted, SSYN indicates that the Unibus slave device
has responded to the master.

MSYN

BUS MASTER SYNC. When asserted, MSYN indicates that the master device on
the Unibus is informing the selected slave that address and control information are
present.

BUS SSYN

When actuated in the direction of the arrow (ON), SWITCH BUS SSYN asserts BUS
SLAVE SYN as long as the switch is ON.

ACLO

When actuated in the direction of the arrow (ON), AC LO asserts BUS AC LO as
long as the switch is ON.

M CLKPULSE
(Manual Clock Pulse)

Each actuation in the direction of the arrow (ON), the processor generates one bus
control clock, provided that CLK EN switch has been actuated. Two actuations will
generate a processor clock.

MCLKEN

When actuated in the direction of the arrow (ON), it disables the processor clock
logic and allows the M CLK PULSE switch to generate processor clocks.
KM-2 OVERLAY

MPC 7 through 0

The address of the next microinstruction to be executed.

SPAD
(Scratch pad Address)

The address of the register (location) in the scratch pad memory.

ALU S3 through SO
ALUM
c.

These five signals together indicate the function that the ALU is performing.

L..

~\,

0\,

\\\ .. ..,

""'t"':~

J.:; ~".M

~
1,. _ ..____
"AL,.I ~I.~-.~.
~."
•• A

;~-~

,I, \ ...

CIN

Carry in signal to bit 0 of the ALU.

EALU

Enable ALU is the signal that switches the AMUX from inputting the Unibus data
lines to inputting at the output of the ALU.
~h\, .
,\.
"f..
U t.ll i2,L
/\
-r ,,-/ku
r Iv' ':.

10-8

Table 10-4 (Cont)
KM-l and KM-2 Overlay Designations
Definition

Display
SPWR

Sf'F

Scratch Pad Write indicates that the SPM is doing a write function as opposed to a
read.

AUXCNTRL

Auxiliary Control enables the AUX ALU ROMs on print DPF.

BUT J J

Signifies that a branch test for a JMP or JSR instruction is occurring.

BUT UN

Signifies that a branch test for a unary instruction is occurring.

CNST

Signifies that the constants ROM, F025 on M7260, is enabled.

MSYN

Same as MSYN on KM-1

SSYN

Same as SSYN on KM-1

C1 and CO

BUS C1 and CO together signify the type of Unibus cycle that is occurring:
C1

o
o

0
1

DATI
DATIP
DATa
DATOB

10.10 USING KMll MAINTENANCE PANEL
Assume that the maintenance panel is plugged into slot A2 for the KM-l overlay configuration. The M CLK EN
switch must be activated in the direction of the arrow, which disables the processor M CLK PULSE. The following
example uses the sequence of microsteps described in Paragraph 9.5.3.
With the HALT switch depressed, hold down the START switch. Toggle the M CLK PULSE switch advance two
times, then release the START switch and toggle two more times. The processor should now be in microstep CS-2.
The MPC should read 321 8 , which is the contents of the NXT field of LaC 100 8 of the CS. Repeated actuation of
the M CLK PULSE switch should cause the microprogram to proceed as follows:

Location
100
322
321
41
302

NXT (MICRO PC)

Step Name

322
321
40 + 1*
302
300+ 2

CS-1
CS-2
CS-3
H-1
H-2

*In step CS-3 the NXT field contains 40. However, if the HALT switch is depressed, a 1 is ORed into the NXT field to cause a
branch to H-1.

10-9

10.11 CONSOLE MAINTENANCE
If any malfunctions are suspected in the console display logic, the console may be put into service mode. This mode
of operation induces known data into the serial data line from the computer to verify that the counters, clock, and
shift registers of the console logic on the console board are functioning properly. If the data on the console display
does not match the known data, then the closed loop can be probed with an oscilloscope to determine the faulty
area.
The procedure takes the four Scan Address lines and feeds them one at a time into the serial data output line, the
address/data multiplexer is bypassed. Since the clock is free running, each scan address line displays a known data
pattern in the console lights. The troubleshooting procedure for the console is as follows:
1.

Make certain the computer power is off.

Disconnect the console cable connector from the M7260 module and then turn on the computer power.

After Step 2 is completed, the data pattern 1777778 should be displayed on the console lights.

At the Berg cable connector that plugs into the M7260 module, use a piece of small gauge wire and
jumper pin F (signal DAK, serial output line) to pin B2 (ground). All the console lights should be off.
Remove the jumper before proceeding to the next step.

At the cable connector, jumper pin F (signal DAK) to pin N (SCAN ADDRESS 01). The pattern
displayed on the lights, should be 052525 8 . Remove the jumper before proceeding to the next step.

At the cable connector, jumper pin F to pin L (SCAN ADDRESS 02). The pattern displayed on the
lights should be 031463 8. Remove the jumper before proceeding to the next step.

At the cable connector, jumper pin F to pin J (SCAN ADDRESS 04). The pattern displayed on the
lights should be 007417 8. Remove jumper before proceeding to the next step.

At the cable connector, jumper pin F to pin D (SCAN ADDRESS 08). The pattern displayed on the
lights should be 000377 8. Remove jumper after completing the step.

10-10

PART 3
MMII-K AND MMII-L MEMORIES
Part 3 provides both general and detailed descriptions of the MMll-K and MMll-L
core memories that are used in the PDP-II/05 and PDP-II /1 O. Maintenance
information is also included. The chapters of Part 3 are:

Chapter 11 - MM ll-K and L General Description
Chapter 12 - MMIl-K and L Detailed Description
Chapter 13 - Memory Maintenance

CHAPTER 11
MMII-K AND L GENERAL DESCRIPTION

11.1 INTRODUCTION
This chapter provides the user with the theory of operation and logic diagrams necessary to understand and maintain
the MMII-K and MMII-L Read/Write Core Memories. The level of discussion assumes that the reader is familiar
with basic digital computer theory. Both general and detailed descriptions of the core memories are included.
Although memory control signals and data pass through the Unibus, it is beyond the scope of this discussion to
describe the operation of the Unibus. A detailed description of the Unibus is presented in the PDP-II Peripherals
and Interfacing Handbook.

A complete set of engineering logic drawings is shipped with each core memory. These drawings are bound in a
separate volume entitled MMII-K and L Core Memories, Engineering Drawings. The drawings reflect the latest print
revisions and correspond to the specific memory shipped to the user.
11.2 GENERAL DESCRIPTION
This paragraph provides a physical description and speCifications for the memory. The major functional units of each
memory are briefly described, and the basic memory operations are discussed.
11.2.1 Physical Description
The MMII-K provides 4096 (4K) 16-bit words: the MMll-L provides SI92 (SK) 16-bit words. Both configurations
require three standard S-I/2 inch wide modules: two are hex-height and one is quad-height.
The quad-height module contains the memory stack: module H213 for 4K; and module H214 for SK. One
hex-height module (G 110) contains the control logic, inhibit drivers, sense amplifiers, and 16-bit data register; the
other hex-height module (G 231) contains the address selection logic, current generator, and switches and drivers.
Pin-to-pin compatibility exists between the C, D, E, and F connectors of both these modules are also compatible
with the standard Unibus pin assignments.
It is recommended that the G231 Driver Module be installed between the GIIO Control Module and the H213 or
H214 Stack Module. Photographs of the component sides of the modules are shown in Figures 11-1, 11-2, and 11-3.

11.2.2 Specifications
The general memory specifications are listed in Table 11-1.

11-1

Figure 11-1 Component Side of GIlD Control Module

Figure 11-2 Component Side of G231 Driver Module
11-2

HANDLE (4)

Figure 11-3 Component Side of 8K H214 Stack Module

Table 11-1
MMII-K and L Memory Specifications
Type:
. Magnetic core, read/write, coincident current, random access.
Organization:
Planar, 3D, 3-wire
Capacity:
4096 (4K) words for MM ll-K
8192 (8K) words for MMII-L
Access Time and Cycle Time:
Bus Mode
Cycle Time
DATI
DATIP
DATODATOB
(pAUSE L)
DATO-DATOB
(pAUSE H)

Access Time

900ns
450 ns
900ns

400ns
400ns
200 ns

450 ns

200ns

11-3

Table 11-1 (Cont)
MMll-K and L Memory Specifications
x-V Current Margins:
±6% @ 0° C, ±7% @ 25° C, ±6% @ 50° C
Strobe Pulse Margins:
±30 ns @ 0° C, ±40 ns

25° C, ±30 ns

50° C

Voltage Requirements:
+5V ±5% with less than 0.05V ripple
-15V ±5% with less than 0.05V ripple
Average Current Requirements:
Stand by
+5V: 1.7A
-15V: 0.5A
Memory Active
+5V: 3.4A
-15V: 6.0A
Power Dissipation (worst case):
Control Module (GllO): ~ 60W
Drive Module (G231): ~ 40W
Stack Module (H213 or H214): ~ 20W
Total at maximum repetition rate: 120W
Environment:
Ambient temperature: 0° C to 50° C (32° F to 122° F)
Relative Humidity: 0-90% (non-condensing)

11.2.3 Functional Description
The memory is a read/write, random access, coincident current, magnetic core type with a cycle time of 900 ns and
an access time of 400 ns. It is organized in a 3D, 3-wire planar configuration. Word length is 16 bits, and the memory
is offered in two word capacities: the MMl1-K contains 4096 (4K) words, and MMII-L contains 8192 (8K) words.
The major functional units of the memory (Figure 11-4) are briefly described in the following paragraphs.
11.2.3.1 GIl 0 Control Module - The GIl 0 Control Module contains the memory control circuits, inhibit drivers,
sense amplifiers, data register, threshold circuit, -5V supply, and device selector.

Memory Control Circuits - Control circuits are prOvided to acknowledge the request of the master
device, determine which of the four basic operations (DATI, DATlP, DATO or DATOB) is to be
performed, and set up the appropriate timing and control logic to perform the desired read or write
operation. If a byte operation has been selected, address line AOO L determines the byte to be selected.
The actual read or write operation is selected by control lines (COO and COl). The memory control logic
also transfers data to and from the Unibus.

Inhibit Driver - Each bit mat contains a single inhibit/sense line that passes through all cores on the mat.
To write a 0 into a selected bit, an inhibit current is passed through the inhibit/sense line that cancels the
write current in the V-line. The core does not switch, so it remains in the 0 state. With no inhibit
current, the currents in the X- and V-lines switch the core to the 1 state.

11-4

--.-

UNIBUS

H213,214 MEMORY STACK 4 OR 8K X 16 BIT

GilD CONTROL AND DATA LOOPS MODULE

----------BYTE MASKING

~----------------

16 DATA LOOPS

16 CIRCUITS
STROBE 0
BUS AD L -

RESET 0

LOAD 0

a 1 H --'
a I L ---l
a I H ---I

DATA FF REG

I--BUS IN I T L _
BUS DCLO
BUS DATA (0-15)
BUS CO L, Cl
BUS MSYN

L
L
L
L

BUS SSYN L BUS Al L,A14 L -

BUS A15 L,16 L,17 L -

Ij~~~jjjjj I

INHIBIT DRIVER
SENSE AMP
BUS DRIVER

-1

4096 CORES FOR 4K }
8192 CORES FOR 8K

TIMING CHAIN
TINH H---l
MODE CONTROLS
DATA
BUS RECEIVERS
OUT H

x -Y

---+I
DATA H --I

~~~t~iOR

INTERLEAVE CONTROL

DIODE MATR ICES
X DRIVE LINES
Y DRIVE LINES

PRO 0

IIIII

01 ~I~ ~

PER BIT

-----r~N_-

NWD 0

SS 0

IIcroO

SS 1

;;3

HUI-I-O::

BUS RECEIVERS
ADDRESS LATCHES
FIRST LEVEL DECODE

u,
BUS A2,3,4,5,6,7,} _
8,9,10,11,12,13

----J
TOR ----J A2 ,3

SS 2

IADDREssl

BITS 1 CKTS
I USED
I
1------

SS 3

ADDRESS

YPRD 0-7}

--l IOH YNWD 0-7
READ-WRITE -J A4 ,5,6
YSS 0-7

YDR 0-7

TSS

f-- -

-,
~

BUS DCLO L -

DISCHARGE
CIRCUIT

i~~~~s ,~~,~)_I

I
_ _ ---1.

H'--++-f-

--.---+---+._--'

YSS 0 -7

-STACK-I

A789 XPRD 0-7}
"
XNWD 0-7

READ'GND--..l
I
WRITE' -15V
DC LO 1 - - - - - I A 1 0 , 1 1
XSS 0-15
CKT - - '
CJR~EYNT - 1 12 ,13 0-7 FOR 4K
·1 GENERATOR

TRANSISTOR)'
1
---.I

PRO 1 -----r----t~__,
N WD 1

____ _

.
VOLT REF CIRCUIT
CURRENT CONTROL a
TEMPERATURE
_
_ _ _COMPENSATION
___ _

XDR 0-7

1/ / I
I I

XSS 0-15

I I

~I ~~.~~ ;I~~;I
__

~---------------Rl
THERMISTER
RESISTOR

RTI

G231 DRIVER MODULE
11-1148

Figure 11-4 MM11-K, L Memory Block Diagram

Sense Amplifiers - During a read operation, the sense amplifier picks up a voltage induced in the
sense/inhibit winding when a core is switched from a 1 to a O. This signal is detected and amplified by
the sense amplifier whose output sets a data register flip-flop to store a 1. In effect, a 1 is read but the
core is switched to the 0 state. Cores which were previously set to 0 are not effected.

Data Register - The data register is a 16-bit flip-flop register used to store the contents of a word after it
is destructively read out of the memory; the same word can then be written back into memory
(restored) when in the DATI mode. The register is also used to accept data from the Unibus lines to
accommodate the loading of incoming data into the core memory during the DATO or DATOB cycles.

Device Selector - The device address is decoded in the device selector to determine if the memory bank
has been addressed.

Threshold Circuit and -5 V Supply - The threshold circuit provides a reference threshold voltage to the
sense amplifiers. During a read operation, if the threshold voltage (20 mY) is exceeded, the sense
amplifier produces an output. The - 5V supply provides a negative voltage for the sense amplifiers.

11.2.3.2 G231 Driver Module - The G231 Driver Module contains the address selection logic, switches and drivers,
current generator, stack discharge circuit, and DC W protection circuit.

Address Selection Logic - The core memory receives an 18-bit address from the master device. The
address is latched and decoded to determine if the memory is the selected device and to determine the
core location specifically addressed. If the operation is a byte operation, bus line ADO L indicates the
byte to be used. The X- and V-portion of the address is decoded through selection switches and a diode
matrix to enable passage of read/write current through the selected X- and Y-drive ~ines of the memory.
The coincidence of these currents selects the specific 16-bit core memory location desired.

Switches and Drivers - The switches and drivers direct the flow of current through the magnetic cores to
ensure the proper polarity for the desired function. This action is necessary because a single read/write
line is used, and the current for a write operation is opposite in polarity to the current r~quired for a
read operation. There are separate switches and drivers for the read and write circuits in the selection
matrix.

Current Generators - X- and Y -current generators provides the current necessary to change the state of
the magnetic cores. The linear rise time and amplitude of the output-current waveform have been
selected to provide optimum switching of the core states and maximum signal-to-noise ratio for a wide
range of temperatures.

Stack Discharge Circuit - The stack discharge circuit maintains the proper stack charge voltage during
operation: approximately OV during a read operation and apprOximately -14V during a write
operation.

DC LO Protection Circuit - If any dc voltage is out of tolerance, DC W is asserted on the Unibus. It is
sensed by the DC LO protection circuit, which inhibits the memory operation by opening the -15V line
to the current source. This prevents spurious memory operation.

11.2.3.3 H213 or H214 Stack Module - The stack module contains the ferrite core array and the X-V diode
matrices. For the 4K memory (H213), 16 core mats are used, each wired in a 64 X 64 matrix; 16 core mats, each
wired in a 128 X 64 matrix are used for the 8K memory (H214). The stack also contains the resistor/thermistor
combination to control the X-V current generator temperature compensation.

11-6

11.2.4 Basic Memory Operations
The core memory has four basic modes of operation. The main function of the memory is simply to read and write
data. Additional modes are provided, however, to allow for byte operation and to eliminate the restore cycle when it
is not needed, thereby increasing overall system efficiency. The four basic memory operations are:
a.
b.
c.
d.

Read/restore (DATI)
Read pause (DATIP)
Write (DATO)
Write byte (DATOB).

These four modes are discussed briefly in the following paragraphs.
NOTE
In the following discussions, all operations refer to the master
(controlling) device. For example, the term "data out"
indicates data flowing out of the master and into the memory.
11.2.4.1 Data In (DATI) Cycle - The DATI cycle is a read/restore memory cycle. During this operation, the
memory reads the information from the selected core location, transfers it to the Unibus, and then writes the
information back into the memory location. This last step is necessary because the core memory is a destructive
readout device. During the first part of the cycle, the memory loads the data into a register; at the same time, the
memory applies the data to the Unibus. Then, during the second part of the cycle, the memory takes the data from
the register and writes it back into the addressed memory location.
11.2.4.2 Data In, Pause (DATIP) Cycle - Normally in reading from memory, the information is destroyed in the
particular location accessed, and the data must be restored. However, sometimes it is not actually necessary to
restore the information after reading, because the location is to have new data written into it. In this instance,
eliminating the restore operation decreases the memory cycle time by approximately 50 percent. The DATIP
operation is used for this purpose. The data is read from memory and the restore cycle is inhibited. Because no
restore cycle is used, a DATIP must always be followed by a write cycle (either DATO or DATOB) on the same
address or data in both addresses will be destroyed. If a DATIP is not followed by a DATO or DATOB, the memory
controller will be unable to control the bus, and other devices will be unable to access the bus (this is known as
hanging the bus).
11.2.4.3 Data Out (DATO) Cycle - The DATO cycle is a write memory cycle used by the master device to transfer
data into core memory. To ensure that proper data is stored, the memory unit must first be cleared by reading the
cores (thereby setting them all to 0) before writing in the new data. During a normal DATO, the memory first
performs the read operation to clear the cores and then performs a write cycle to transfer data from the bus into the
selected core location. If a DATO follows a DATIP (rather than a DATI), the sequence is not the same. The DATIP
clears core and generates a pause flag; the DATO skips the read cycle and immediately begins the write cycle. This
process reduces DATO cycle time by approximately 50 percent.
11.2.4.4 Data Out, Byte (DATOB) Cycle - The DATOB cycle is similar in function to the DATO cycle, except
that during DATOB data is transferred into the core memory from the bus in byte form rather than as a full word.
During the read cycle, the non-selected byte is saved by reading it into the data register while the selected byte is
transferred into the register from the bus. During the write cycle, only the selected byte portion of the word is
loaded into the memory location from the bus. At the same time, the non-selected byte is restored from the data
register into the memory location. In effect, the memory is first cleared and then Simultaneously performs a restore
cycle for the non-selected byte and a write cycle for the selected byte. This mode can follow a DATIP as described
above.

11-7

CHAPTER 12
MM11-K AND L DETAILED DESCRIPTION
12.1 INTRODUCTION
This chapter provides a detailed description of the MMI1-K and L memories. The discussion is related to the 8K
memory (MM11-L). The description of the 4K memory (MM11-K) is basically the same; only the differences are
discussed.
The detailed description covers the core array, device and word selection, switches and drivers, current generation,
stack discharge circuit, DC LO circuit, sense/inhibit circuitry, control and timing logic, and memory operating
cycles.
12.2 CORE ARRAY
The ferrite-core array for the 8K memory consists of 16 mats arranged in a planar configuration. Each mat contains
8192 ferrite cores arranged in a 128 X 64 array. Each mat represents a single bit position of a word. This planar
configuration provides a total of 8192 16-bit word locations. The 4K memory core array consists of 16 mats each
arranged in a 64 X 64 planar configuration to provide a total of 4096 16-bit word locations. Each ferrite core can
assume a stable magnetic state corresponding to either a binary lora binary O. Even if power is removed from the
core, the core retains its state until changed by appropriate control signals. The outside diameter of each core is 18
mil; the inside diameter is approximately 11 mil. Each core is 4.5 mil thick.
Selection and switching of the cores is provided by three wires traversing each core in a special selection technique.
An X-axis read/write winding passes through all cores in each horizontal row for all 16 mats. A Y-axis read/write
winding passes through all cores in each vertical row for all 16 mats. Through the use of selection circuits which
control the current applied to specific X-V windings, anyone of the 8192 or 4096 word locations can be addressed
for writing data into memory or reading data out of memory. A third line passes through each core on a mat to
provide the sense/inhibit functions. There is one sense/inhibit line per mat. This single sense/inhibit line, as well as
the selection circuits, are discussed in subsequent paragraphs.
12.3 MEMORY OPERATION
Figure 12-1 illustrates a typical portion of the core memory. An X- and V-winding pass through each core in the
mat. The current passing through anyone winding is such that no single winding produces a magnetic field strong
enough to cause a core to change its magnetic state. Only the reinforcing magnetic field caused by the coincident
current of both an X- and V-winding can cause the core located at the point of intersection to change states. It is this
principle that allows the relatively simple winding arrangement to select one and only one memory core out of the
total contained on each mat. The current passing through either an X- or V-winding is referred to as the half-select
current.
A half-select current passing through the X3 winding (Figure 12-1) from left to right produces a magnetic field that
tends to change all cores in that horizontal row from the 0 to 1 state. The flux produced by the current is, however,
insufficient to complete the state transition in any core. Simultaneously passing a half-select current through the Y2
winding from top to bottom produces the same effect on all cores in that particular vertical row. Note, however,
that both currents pass through only one core which is located at the intersection of the X3 and Y2 windings. This is

12-1

INHIBIT
CURRENT DRIVER
Y2

------------Ir-f-I--::oI1
FERRITE
~CORES

X7 _---------~.,.:..+-="

X6 4-----------~~r-~~}_--------------------------~~~

4-----------~~~~I~ ~------------------------~~~~>I~

r-----------

X4 4-----------~~r-71~ ~------------------------~~~~rl~

r-----------

SELECTED
~CORE

Im/2 X3 4-----------~~~~IJ ~------------------------~___T~.IV~------------

X2 4-----------~~+-~ J-------------------------~~~~~~ ~-----------

.~----------_7.~

_-------- SEN SE/ INHIBIT _________
_
LINES
TO SENSE AMPLIFIER
TERMINATION

11-0079

Figure 12-1 Three-Wire Memory Configuration

the selected core and the combined current values are sufficient to change the state of the core. The arrows in Figure
12-1 show current direction for the write cycle. All X- and Y-windings are arranged in such a manner that whenever
a half-select current is passed through each, the resultant magnetic fields combine in the core at the point of
intersection. This combined, full-select current ensures that the selected core is left in the binary 1 state. The
currents used to select the core are referred to as write currents. A typical hystersis loop for a core is shown in
Figure 12-2.

12-2

HYSTERESIS LOOP FOR CORE

- -

FLUX STORED OR SWITCHED

INHIBIT OR
READ HALF SELECT
I
I

-1- ____ _
I

- - "I"DISTURBED
1

1
1
1

WRITE
FULL
SELECT
FLUX
CHANGE
FOR I AT
READ
TIME

I WR TE
DRIVE CURRENT

READ
FULL
SELECT

1
I

I
I

{

"0" DISTURBED--

"0" UNDISTURBED--

L____

I
HALF SELECT WRITE

FLUX CHANGE AT READ {
TIME FOR A "0':
NOTE NO SWITCHING
TAKES PLACE.

"0" OUTPUT COMES DURING I RISE TIME
AND IS A FUNCTION OF IT AND CURRENT
AMPLITUDE.
"0" OUTPUT ex: A ...!... OR ex:
/ ____ -'L--':.O"_""-'--------'?''---"""'\

"I" OUTPUT SWITCHES AT THE
CORE TIME CONSTANT AND IS
PRIMARILY DEPENDENT ON
CURRENT AMPLITUDE. IT WILL
SWITCH FASTER AND GROW AS
RISE TIME IS DECREASED.

I
I
I
I

I
I
I

I
I

DOTTED LINES SHOW HOW
OUTPUTS WOULD BEHAVE
WITH DIFFERENT CURRENTS

11-00888

Figure 12-2 Hysteresis Loop for Core

In the MMI1-K and L Core Memories, the X3 windings in all 16 mats are connected in series as are the Y2 windings.
Therefore, whenever a full-select current flows through a selected core on one mat, it also flows through an identical
core on the other 15 mats. The X3-Y2 cores on all mats switch to a binary 1, causing each of the 16 cores to become
one bit of a 16-bit storage cell.

12-3

Because of the serial nature of the X-V windings, a method is used that allows cores to remain in the 0 state during a
write operation; otherwise, every 16-bit word selected would be allIs. The method used in the MMII-K and L Core
Memories is to first clear all cores to the 0 state by reading and then, by using an inhibit winding during the write
operation, to inhibit cores on particular mats. The inhibited cores remain Os even when identical cores on other mats
are set to I.
The half-select current for the inhibit lines is applied from an inhibit current driver, which is a switch and a resistor
between the inhibit line and -ISV. The current in the inhibit line flows in the opposite direction from the write
current in all V-lines and cancels out the write current in any V-line. There is a separate inhibit driver for each
memory mat, and each mat represents one bit position of a word; thus, selected bits can be inhibited to produce any
combination of binary Is and Os desired in the 16-bit word. It must be remembered that the inhibit function is
active only during write time.
The sense/inhibit lines are also used to read out information in a selected 16-bit memory cell. The specific core is
selected at read time in the same manner as during the write cycle with one notable exception: the X- and
V-currents are in the opposite direction. These opposite half-select currents cause all cores previously set to I to
change to 0; cores previously set to 0 are not effected. Whenever the core changes from I to 0, the flux change
induces a current in the sense winding of that mat. This current is detected and amplified by a sense amplifier. The
amplifier output is strobed into the data register for eventual transfer to the Unibus. Figure 12-3 shows a 16-word by
4-bit planar memory. The MMII-L Core Memory (SK) functions in the same manner, except that it has 128 X-lines,
64 V-lines, and 16 core mats. The core stringing is identical, and the sense windings are strung through allSI92 cores
with the interchange between X63 and X64 instead of between XI and X2. For the 4K memory, the interchange is
between X31 and X32 and it has 64 X-lines and 64 V-lines.
12.4 DEVICE AND WORD SELECTION
When the processor or a peripheral device attempts to perform a transaction with the memory, the processor asserts
an IS-bit address on Unibus address lines A (17:00). Six of these 18 bits [AOI and A (17: 13)] indicate the address
of the memory as a device. Depending on the memory configuration, only four or five bit combinations of these bits
are used as shown in Table 12-1. Eleven of the 12 remaining bits [A (12:02)] plus AOI and A13 indicate the address
of a specific word within the memory. Address bit AOO is used to select the byte (S bits) transaction when in
DATOBmode.

Table 12-1
Addressing Functions
Bus Address

. AOO
AOI
A02, A03, A01H*
A04, AOS, A06
A07, A08, A09
AlO,All,AI2
Al3
A14
AIS,AI6,AI7

Function
4KMode

8KMode

Controls byte mode
Becomes AOIH to G231
Decode Y-Drivers
Decode Y -Switches
Decode X-Drivers
Decode X-Switches
Goes to device selector
Goes to device selector
Goes to device selector

Controls byte mode
Becomes AOIH to G231
Decode Y-Drivers
Decode Y-Switches
Decode X-Drivers
Decode X-Switches
Decode X-Switches
Goes to device selector
Goes to device selector

*AO 1H is not a Unibus signal.
12-4

ARROWS SHOW CURRENT
OUR ING WRITE TIME

TOP VIEW OF CORE MATS

XSW

R
W
R
W
R
W
R

1/
/1/

X2
~

Xl
XO

" I'" "

/1/

'- I'I'-

"- i'

XDR

l"-

I'- /
'- /

/
Y2

"- i"-

1"-

" 1"-

"- 1"-

" '"

/1/
/

I"-

"
"f"

i"-

1/
/1/

I'"

"f"i"-

I'-

f'-

/
/

/ 1/

V
/

/1/
/1/

'" >-< "---'-

1"-

t-INTERCHANG E
IS FOR NOISE
CANCELLATIO N

SA SB

THERE IS 1 SENSE INHIBIT
WINDING PER MAT

INH
YSW

YSW

W R
W R
YDR

W R

YDR

SENSE-INH LINE

X LINE

BONDING MEDIUM
GROUND PLANE

)" '0'"
DETAILS OF CORE STRINGING

Figure 12-3 Three-Wire 3D Memory, Four Mats Shown for a 16-Word 4-Bit Memory

12-5

1 1 -OQ88A

The memory address is decoded by the device selection circuit on the GllO Control Module. The word address is
stored in a register on the G231 Driver Module whose output is decoded to activate the X·Y line switches and drivers
which select the addressed word. These circuits contain jumpers which are included or excluded to establish a
specific device address and select 4K· or 8K·word capacity. Jumpers are provided to select interleaved or
non·interleaved operation for the 8K model; however, the memory is to be operated in the non·interleaved mode
only.
Table 12·1 lists the function of each address bit. Figure 124 is a Simplified block diagram of the device and word
address selection circuits.

/'.

ICONTROL MODULE Gll0
DCLOL

A<17:14>1

)
AOO,AOI

DEVICE
SELECTOR

DSEL H

TO CONTROL LOGIC

A13

l- - -

,DRIVER
MODULE G231

N
1
B
U
S

I- A01 H

-- -- -

--~

,
,
I

A131

A03H 8 L
A09H 8 L
/

NAND
GATES

TOR H

I
A<12:02>

."
/

WORD
ADDRESS
REGISTER

A13 (1) 8(0)
A12(1l8(0)
A06(1) 8(0)

I
I
I

A011:f,A02H,A04H,A05H,A07H,A08H,A10H,Al1H

)

TO DECODERS
FOR x-v
SWITCHES
AND DRIVERS

A06(1)L,A06 (O)L
(A12H·A13H) L
(A12L'AI3H) L

(AI2H ·AI3Ll L
(AI2L'AI3L)L

ADDRESS
GATING

TSS H

I
-1090

"
Figure 124 Device and Word Address Selection Logic, Block Diagram
12.4.1 Memory Organization and Addressing Conventions

Prior to a detailed discussion of the address selection logic, it is important to understand memory organization and
addressing conventions.
The memory is organized in 16·bit words each consisting of two 8·bit bytes. The bytes are identified as low and high
as shown below.

15
MSB

08 07
DATA BITS 0<15:00>

00
LSB
11-1174

12-6

Each byte is addressable and has its own address location: low bytes are even numbered and high bytes are odd
numbered. Words are addressed at even numbered locations only; the high (odd) byte is automatically included.
For example, an 8K word memory has 8192 words or 16,384 bytes; therefore, 16,384 locations are assigned. The
address locations are specified as 6-digit octal numbers. The 16,384 locations for the 8K memory are deSignated
000000 through 037777. Figure 12-5 shows the organization for an 8K memory.

BI7

115

I
..

16 BIT WORD

I
I
I

HIGH BYTE

•

LOW BYTE

000001

000000

000003

000002

000005

000004

037773

037772

037775

037774

037777

037776
11-1091

Figure 12-5 Memory Organization for 8K Words

The address selection logic responds to the binary equivalent of the octal address. The binary equivalent of 017772
is shown in the following example.

ADDRESS BITS A<17:00>

OCTAL
f r -1173

Each memory bank (4K or 8K words) requires its own unique device address. For example, assume that a system
contains three 8K memory banks (Figure 12-6). The device selector for the 8K non-interleaved memory decodes
four address lines [A (17: 14)]. Examination of the binary states of these bits for the three memory banks shows
that the changes in the states of bits AI4 and AIS allow the selection of a unique combination for each bank. The
combination, which is the device address, is hardware-selected by jumpers in the device selector.

12-7

000000 . . . - - - - - - ,
037777'--_ _ _- '
040000 . . . - - - - - - ,

077 7 77 '--_ _ _- '
100000 ,...----....,
137777'--_ _ _- '

17 I 16 I 15
14 I 13 I 12
BIT POSITION
r--+--t--+--r--+-~
0
0
0
0
0
BINARY

L I

{

lSi ADDRESS

OCTAL

r--'-~--r-~-~-'

BANKI

0
0
0
0
1
1
LAST ADD R E SS r---'--0--"---+---'--3--"---l

lSi ADDRESS
{

BANK2

I
I

o
o

r--'-~--r-~-~-'

0
0
0 11
1
1
LAST ADDRESS r--'--0---'---+---'--7-'---l

I
{

BANK 3

lSi ADDRESS

""--'-~--~--~--r-~

0
0
1
0
1
1
LAST ADD RE SS r---'---"'-----Ir----J.-3 ---'----l
11-1092

Figure 12-6 Address Assignments For Three Banks of 8K Words Each

During system operation, the processor generates the binary equivalent of the octal address on Unibus address lines
A (17:00). The processor uses positive logic and the Unibus uses negative logic. With this in mind, the following is
included to remind the reader of the negative logic convention of the Unibus.
Processor (Positive Logic)
Signal Asserted: High = Logical 1 = +3V
Signal at Rest: Low = Logical 0 = OV
Unibus (Negative Logic)
Signal Asserted: Low =Logical 1 =OV
Signal at Rest: High =Logical 0 =+3V
12.4.2 Device Selector
The device selector located on the Gll0 Control Module (drawing G 110-0-1, sheet 2) shows a logic diagram of the
device selector in the 4K configuration.

12-8

Address bits AOI and A (17: 13) are decoded in the device selector to provide the device selection signal D SEL H
that is used in the control logic. Two combinations of these bits are decoded, depending on the memory
configuration as shown below.

Memory Configuration

Address Bits

4K Words
8K Words

A{17:13)
A (17:14)

Obviously, the memory capacity is determined by the stack module: H213 for 4K words and H214 for 8K words.
The same control module is used for both 4K and 8K memories; therefore, two jumpers (W9 and WID) are provided
to include or exclude address bit A13 commensurate with the memory word size. Two jumpers (13 and J4) on the
G231 Driver Module (drawing G231-O-1, sheet 2) are provided for A13 inclusion or exclusion in the word addressing
logic. The same driver module is used for both memory capacities. In the 4K word size, the components associated
with the additional X-line read and write switches needed for 8K words may be removed. Two jumpers (W7 and W8)
in the device selection logic on the control module are used to select interleaved or non-interleaved operation of the
8K memory. They are configured to provide non-interleaved operation only.
Each memory bank (4K or 8K) must. have its own unique device address. Five jumpers (W2-W6) in the device
selector provide this capability. On drawing G 11 0-0-1, sheet 2, all the jumpers are shown in place and the device
selector responds only when high signals appear on the Unibus address lines A (17: 13). Some jumpers can be
removed to allow the device selector to respond to a particular combination of high and low signals on these address
lines.
All highs at the inputs of the 7380 Unibus receivers (E 12 and E23) give lows at their outputs. Each receiver output
goes to one input of a type 8242 Exclusive-NOR gate. Because of jumpers W7 and W8, bit A14 is decoded for 4K
and 8K configurations. An additional receiver is used to sense BUS DC ill L, and its output (E23 pin 14) is sent to
an 8242 gate (E24 pin S). BUS DC LO L is asserted only when the dc voltages from the power supply drop below
specified limits.
The other input of the 8242 gates associated with bits A14, A13, AlS, A16 and A17 can be connected to +SV or
ground, depending on whether or not jumpers W2-W6 are installed. The input is low (ground) with the jumper in;
with the jumper removed, the input is high (+SV). Each 8242 gate is used as a digital comparator; its output is high
only when both inputs are identical. The 8242 gates have open collectors and they are connected in common;
therefore, the comparator output D SEL H is high only when all gates detect matched inputs (both lows or both
highs).
An installed jumper requires a low signal at the output of the 7380 Unibus receiver. The 7380 is connected as an
inverter so this signal is reflected as a high on the Unibus (logical or asserted state for the Unibus). To configure the
jumpers for a specific device address, find the binary equivalent of the assigned octal address and insert a jumper in
each bit position that contains a O. A specific jumper configuration is shown in Figure 12-7.
The previous discussion dealt with the 4K memory configuration of the device selector as shown in drawing
Gil 0-0-1, sheet 2. Address bits A (17: 13) are decoded and the output of bit AD 1 Unibus receiver (E23 pin 2) is sent
via jumper W8 to the word address register as AOI H.
In the 8K memory configuration, jumper W9 is removed and WID is installed. This removes bit Al3 from the input
of Unibus receiver E12 on GIlD and replaces it with +SV via resistor RI07. This receiver output (pin 14) always
remains low so that jumper WS must remain installed to ensure a match on pins 12 and 13 of gate E13. The jumper
configurations for memory systems up to 128K words are shown in Figure 12-8.
12-9

PROCESSOR STATE (POSITIVE LOGIC)
ASSERTED: H=I=+3V
REST: L=O=OV

+5V

BUS STATE (NEGATIVE LOGIC)
ASSERTED: L=I=OV
REST: H=0=+3V

Rl08
R122
COMMON
COLLECTOR
RESISTOR

BUS A14 L --~rJ--"

o SEL H

Rl09
W4
BUS A15 L

:=jD-C

---1-.-!...cr--"
-=

ASSERTED
ONLY
IF ALL
GATE
OUTPUTS
ARE HIGH

TRUTH TABLE
A B
C

ONLY A14 AND A15 SHOWN.
A <17:16>HAVE JUMPERS ALSO.

USED AS A 01 GITAL
COMPARATOR.
OUTPUT IS HIGH
ONLY WHEN BOTH
I NPUTS MATCH.

8242 EXCLUSIVE NOR ELEMENT

ASSIGNED ADDRESS 040004

BIT POSITION
OCTAL
OCTAL

__~__+-~__- L__+-~__- L__+-~__-L__+-~~-L__+-~L--L__~BINARY
o

BITS A <17:14> ARE DECODED FOR DEVICE SELECTION

L----'----'----I NSTALL JUMPERS IN THESE BIT POSITIONS
tt -t093

Figure 12-7 Jumper Configuration For A Specific Memory Address

COfHROL MODULE Gl10
COMPONENT SIDE
SHOWING PHYSICAL
LOCATION OF
JUMPERS

A
A

NOTES:
1. Jumper WI is for test purposes only. It must be installed for normal operation.
2. Jumper Wl1 should be removed for normal operation. When installed the ",emory
responds to DATI only,regardless of state of control lines COO and COL
3. Jumpers W7 and W8 must remain in the factory installed positions.
4. When used as an 8k bank, jumpers W5 and WIO must be installed and jumper
W9 must be removed.
5. When used as a 4k bank, jumper Wl0 must be removed and jumper W9 must be
installed. Jumper W5 determines the location of the bank on the bus.

CONNECTOR EDGE

Figure 12-8 Device Decoding Guide
12-10

/1-1/49

Device Address Jumpers
Memory
Bank (Words)

Machine
Address (Words)

W5
A13

W6
A14orAOl

W4
A15

W3
A16

W2
A17L

0-4K
4-8K
8-12K
12-16K
16-20K
20-24K
24-28K
28-32K
32-36K
36-40K
40-44K
44-48K
48-52K
52-56K
56-60K
60-64K
64-68K
68-72K
72-76K
76-80K
80-84K
84-88K
88-92K
92-96K
96-100K
100-104K
104-108K
108-112K
112-116K
116-120K
120-124K
124-128K

000000-017776
020000-037776
040000-057776
060000-077776
100000-117776
120000-137776
140000-157776
160000-177776
200000-217776
220000-237776
240000-257776
260000-277776
300000-317776
320000-337776
340000-357776
360000-377776
400000-417776
420000-437776
440000-457776
460000-477776
500000-517776
520000-537776
540000-557776
560000-577776
600000-617776
620000-637776
640000-657776
660000-677776
700000-717776
720000-737776
740000-757776
760000-777776

IN
IN

IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT

IN
OUT

OUT
OUT

IN
IN
OUT
OUT

OUT
OUT
OUT
OUT

IN
IN
IN
IN
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

Figure 12-8 Device Decoding Guide (Cont)

12.4.3 Word Selection
Word selection requires two levels of decoding. The word address bits are placed in the 13-bit word address
register: 12 bits are used for a 4K memory, and 13 bits are used for an 8K memory. Some bits from the register
output are combined in a gating network. The outputs from the gating network and some outputs directly from the
register are used as inputs to a group of decoders (Figure 124). The outputs of the decoders select the proper X- and
V-read/write switches and drivers.
12-11

12.4.3.1 Word Address Register and Gating Logic - The word address register and gating logic are contained on the
G231 Driver Module. The circuit schematic is shown in drawing G 231-0-1, sheet 2. The register is composed of 13
74H74 dual D-type edge-triggered flip-flops. They are identified as Ell, E12, E13, E14, E18, E19, and E20. The
output (pin 3) of gate E9 provides a high signal on the preset input (pin 4 or pin 10) of each flip-flop, which
prevents direct presetting of the flip-flop. Direct clearing of each flip-flop is prevented by a high signal on the clear
input (pin 1 or pin 13) via the output (pin 2) of gate E9. The register cannot be directly cleared or preset; its output
responds only to the signal at its data (D) input.
Address bits A (13 :02) are picked off the Unibus via type 7380 receivers (E15, E16, and E 17). The receiver outputs
are sent to the corresponding flip-flop D-inputs. The input to the receiver associated with bit A13 has two
sources: Unibus signal BUS A13 L via jumper J4, or +5V via jumper 13. These jumpers are associated with the
memory word size. A 4K memory requires 13 in and J4 out; an 8K memory requires J4 in and 13 out. Because BUS
A13 L is used on the G110 module as part of the device selector, this arrangement prevents loading BUS A13 L
twice per memory bank.
The Ell flip-flop associated with bit A01 receives its input from the device selector (drawing G 110-0-1, sheet 2).
The input signal is AOI H, which is obtained from bit A01 Unibus receiver for both 4K and 8K memories.
The register flip-flops are clocked synchronously by CLK 1 H from the control logic (drawing G 110-0-1, sheet 2).
Clocking occurs on the positive-going edge of CLK 1 H. The generation and timing of this clock signal is discussed in
Paragraph 12.9.1. When the register is clocked, the outputs of flip-flops AOl, A02, A04, A05, A07, A08, AlO and
All are sent to the type 8251 X-Y decoders on the G231 Driver Module (drawing G231-0-1, sheets 3 and 4). The
outputs of flip-flops A06, A12, and A13 are combined in a group of six type 74H1O NAND gates (three E22s, and
three E25s), which are enabled by signal TSS .H. Table 12-2 lists the states of flip-flops A06, A12, and A13 that are
required to enable these gates. The outputs of flip-flops A03 and A09 are gated with TDR H in high-speed 2-input
NAND gates and then applied to the decoders for the drivers only. The six signals listed in Table 12-2 are sent only
to the X-Y line read/write switch decoders on the driver module.

Table 12-2
Enabling Signals for Word Register Gating
Output Signals
Gate
E22
E22
E22
E25
E25
E25

pin 12
pin 8
pin 6
pin 12
pin 8
pin 6

Asserted Signal
(A06H) L
A06L
(A12H· AI3H) L
(AI2L • A13H) L
(A12H • A13L) L
(A12L • A13L) L

Enabling Signals
FF A06

FF Al2

FF A13

Set
Reset
X
X
X
X

X
X
Set
Reset
Set
Reset

X
X
Set
Set
Reset
Reset

Signal ISS H is generated at the output (pin 3) of negative input OR gate E4 during a read or write operation. During
a read operation, the enabling signal is produced at NAND gate E4, pin 8 by ANDing READ Hand TNAR H. During
.a write operation, the enabling signal is produced at NAND gate E4, pin 6 by ANDing WRITE Hand TWID H.
Signals READ, TNAR and TWID are generated by the control logic on the GllO Control Module. WRITE is the
complement of READ (produced by inverter E6). Signal READ H comes from the 1 output of R/W flip-flop E13
(drawing G 110-0-1, sheet 2); the READ H signal is produced when the flip-flop is set. When the R/W flip-flop is
cleared, READ H is low and is inverted by E6 to produce WRITE H.

12-12

12.4.3.2 X- and Y- Line Decoding - The basic decoding unit is a Type 8251 BCD-to·Decimal Decoder that converts
a 4-bit BCD input code to a one-of-ten output; however, only eight outputs are used. Figure 12-9 shows an 8251 and
associated truth table. The inputs are DO, Dl, D2, and D3; they are weighted 1,2,4, and 8 with DO being the least
significant bit. The outputs are 0-7 and are mutually exclusive. The selected output is low and all others are high.

7
15

.... 4
3

TO READ
SWITCHESI
DRIVERS

+5V

}

TO WRITE
SWITCHESI
DRIVERS

8251

}

TRUTH TABLE
INPUTS

OUTPUTS

1
1

,, , , ,

03 02 01 DO 0

0
1

1
X

1
1

0
1

X'IRREVELANT
11-1095

Figure 12-9 Type 8251 Decoder, Pin Designation and Truth Table

For the 8K memory, ten decoders are used: six for the X-axis and four for the Y-axis. Each decoder controls four
read/write switch pairs. Each pair is associated with a specific switch or driver. This switch matrix is combined with
the stack X-V diode matrix to allow selection of any location out of the total 8192 locations (stack drawing
DCS-H214-O-1 for interconnections).
For the 4K memory, eight decoders are used, four for each axis. The stack X-diode matrix is halved to allow
selection of any location out of the total 4096 locations (stack drawing DCS-H213-O-1 for interconnections). A
discussion of the configuration and operation of the switches and diode matrices is given in Paragraph 12.4.3.3.
The X- and V-line switches are first differentiated as switches and drivers. The drivers are those switches that are
connected to the diode end of the stack. Drivers and switches are further differentiated by function: either read or
write. Another differentiation is made by polarity: negative or positive, depending on the physical connection. Read
drivers and write switches are connected to the current generator outputs and are considered positive; write drivers
and read switches are connected to -15Vand are considered negative.
Figure 12-10 shows the decoders associated with V-line read and write switches 4-7 and V-line read and write
drivers 4-7. (Refer also to the truth table in Figure 12-9.) In both decoders (E28 for switches and E8 for drivers),
the signal to input D3 selects the block of switch pairs. This signal must be low for any output to be selected. The
signal to input D2, which is READ L for all decoders, controls the selection of read or write Switches/drivers. When

12-13

READ L is low, outputs 0-3 are selected: these are read switches and read drivers. When READ L is high, outputs
4-7 are selected: these are write switches and write drivers. The four combinations of the states of inputs DO and
Dl select the particular switch/driver.

7
3
A06 H

YS7 WRITE SW
L

YS7 READ SW

I
I

03
6
READ L

4
It

I YS6 WRITE SW
YS6 READ SW

I
I

E28
A05 H 14

3
01

5
12
1

YS5 WRITE SW
YS5 READ SW

A04 H 15

DO
4

9
YS4 WRITE SW
13

YS4 READ SW

I
I

DECODER FOR READ AND WRITE SWITCHES YS4-YS7

3
TOR
A03

:cr
READ L

to
5

YP READ DR7
YN WR ITE DR7

03
11
2

1
02

YP READ DR6

YN WRITE DR6

E8
12

A02 H 14
01

1
5

AOI H 15

YP READ DR5
3

YN WRI TE OR5

I
I

DO
13
0
4

YP READ DR4

YN WRITE DR4

DECODER FOR READ AND WRITE DRIVERS Y4-Y7
11-1096

Figure 12-10 Decoding of Read/Write Switches and Drivers Y4-Y7

The four driver decoders (E3, E8, E43, and E46 on drawing G231-O-1, sheets 3 and 4) have a NAND gate connected
to input D3. Signal TDR H is an input to each gate; therefore, the driver decoders cannot be enabled unless TDR H
is high. This signal is generated on the G231 Driver Module (drawing G231-O-1, sheet 2, coordinates A-8) by ANDing
TWID H and READ H or TNAR H and WRITE H.
Each switch/driver is connected to the decoder output through a transformer-coupled base drive circuit. When the
decoder output is at ground (low), the switch/driver is turned on; it is turned off when the decoder output is at
+3.5V (high). The base drive circuit for write switch YS7 shown in Figure 12-11 is typical.
In this example, the decoder inputs have selected output 7, which is at ground. Current it flows into this decoder
output circuit from the +5V supply via resistor Rll and the primary winding (terminals 4 and 3) of transformer T8.
The value of i l is determined by the value of Rll and the voltage reflected into the transformer primary
(approximately IV). An equal current i2 is induced in the base-emitter circuit of write switch E29, which is

12-14

connected to the transformer secondary winding (terminals 13 and 14). This current turns on E29. All the base
current for E29 is provided by this circuit: h is the collector current. When the decoder is turned off, its output
pull-up transistor tries to drive the turn-off current i4 in the opposite direction. This reverse current removes the
forward bias from the base of E29 and turns it off. Capacitor C30 allows the decoder to pump reverse current i4 into
the transformer primary; it also speeds up turn-on current it. Diode Dl prevents reverse breakdown of the
base-emitter junction of E29; it also protects the decoder output.

+5V

8251
DECODER
E28
+5V

017

FROM

r------tt---I4-- CURRENT
GENERATOR

TO
STACK

PORTION OF
OUTPUT 7
11-1097

Figure 12-11 Switch or Driver Base Drive Circuit

12.4.3.3 Drivers and Switches - Drivers and switches direct the current through the X- and V-lines in the proper
direction as selected by the read and write operations.
For an 8K memory, 16 pairs of read/write switches and 8 pairs of read/write drivers are provided in the X-axis; 8
pairs of read/write switches and 8 pairs of read/write drivers are provided in the Y-axis. In conjunction with the
stack diode matrix (drawing H214.Q-l, sheet 2), one driver and anyone of 16 switches select 16 lines in the X-axis;
one driver and anyone of eight switches select eight lines in the Y-axis. This allows selection of 128 lines in the
X-axis and 64 lines in the Y-axis. This provides a 128 X 64 matrix that selects any location out of 8192 locations.
For a 4K memory, eight pairs of read/write switches and eight pairs ofread/write drivers are provided for each axis
(X and V). One driver and anyone of eight switches select eight lines in both axes, which allows selection of 64 lines
in each axis and provides a 64 X 64 matrix that selects any location out of 4096 locations. The size of the X-diode
matrix for the 4K memory is one half the size of the corresponding matrix for the 8K memory (drawing H213.Q-I,
sheet 2). In both memories, the diodes prevent sneak currents in the stack and steer all switched current into the
selected stack line.
Figure 12-12 is one fourth of a V-selection matrix showing the interconnection of the diodes and the lines from the
switches and drivers. It also shows how four pairs of switches and drivers are connected to select 16 locations. Refer
to drawing H213.Q-l, sheet 2 for an extension of this method that uses eight pairs of swi tches and drivers to select
64 locations.
Figure 12-12 shows four pairs of drivers and four pairs of switches for the Y-axis only; polarities are shown for
convenience. The diodes are identified to assist in associating them with the drivers and switches. Each line from a
twin diode interconnection to a read/write switch pair passes through 64 cores and represents one line on each bit
12-15

mat. Assume that a write operation is to be performed and the word address decoders have selected write switch
WYSOO and write driver YNWDI. The Y-current generator sends current through write switch WYSOO (conventional
flow), which puts a positive voltage on the anodes of diodes 03W, 02W, 01 Wand OOW. The non-selected write
drivers (YNWD3, YNWD2, and YNWDO) provide a positive voltage on the cathodes of their associated diodes (03W,
02W and ~OW, respectively), which reverse biases them and prevents conduction. Write driver YNWDl, which has
been selected, turns on and makes the cathode of diode 01 W negative with respect to the anode that forward biases
it. The diode conducts and allows current to flow to write driver YNWDI. A half-select current now flows through
this line that links 64 cores per bit mat (1024 total for 16 mats).

SWITCHES
!RYSOO

LWYSOO
IRYSOI

DRIVERS

I-33W

23W

l3W

03W

33R

23R

13R

03R

l WYS02

32W

22W

12W

02W

IRYS03

32R

22R

12R

02R

31W

21W

llW

01W

31R

21R

11 R

01R

30W

20W

lOW

OOW

30R

20R

lOR

OOR

+ I WYSOl
! RYS02

I--+

+ I WYS03

33W

I/2W
64 CORE S/MAT
OR 1024 TOTAL
FOR EAC H LINE

! YNW03!

! YPRD3 ! +

l YNWD2 I
l YPRD2 J +
I YNWDll

I YPRDI

I +

! YNWDO!

33R

1/2 R

TYPICAL JUNCTION

I YPRDO I +

Y-AX IS 4x4 SECTION (16 LOCATIONS)
11-1098

Figure 12-12 Y-Line Selection Stack Diode Matrix

Figure 12-13 is a simplified schema tic of two pairs of switches and drivers interconnected with the core stack and
current generator. Read/write switches YS07 and read/write drivers YD7 are used as examples. These switches and
drivers are chosen for convenience. For a read or write operation, there are 64 switch/driver combinations available
on the Y-axis and 128 on the X-axis. For a read operation, decoder E8 selects positive read driver E7 via transformer
T3; and decoder E28 selects negative read switch E26 via transformer T7. Both E7 and E26 are turned on when they
are selected. E7 conducts and removes the reverse bias on diode D67, which allows current from the Y-current
generator to flow through D67, E7, the associated matrix diode, and the cores on the selected line. After passing
through the cores, the current flows through E26 and R27 to the -15V line. For a write operation, decoder E28
selects positive write switch E29 via transformer T8; and decoder E8 selects negative write drivers EIO via
transformer T4. Both E29 and EIO are turned on. E29 conducts and removes the reverse bias on diode D17, which
allows current from the Y-current to flow through D17, E29, and the cores in the opposite direction. After passing
through the cores, the current flows through the associated matrix diode, ElO, and R140 to the -15V line. Read
current flow is shown as a solid line; a broken line shows write current flow.
12-16

+5V
WRITE
CURRENT
I Y-CURRENT
, GENERATOR

READ
CURRENT

060

061
017

067
-15V

R141

.J\I'v"v-_ _

POS READ DRIVER
YPRD7

_--"!V\r

+5V

E29

~__.JII O~8

~~ DECODER~ II
T3'-----..

DECODER

T
8 DIODE
PAIRS
TO STACK
DISCHARGE
CIRCUIT

1024 CORES
(64/MAT)

R150

_-.J\IV\r_- Vo

+ 5 V -'Vv'V-_
NEG WRITE DRIVER
YNWD7

El0

r-------..J

~~ DECODE~ II '--__..

~__.JII [)~8DECODER

R140

-15V

NEG READ SWITCH
YS07

E26

I
I
I
I

-15V

Figure 12-13 Typical V-Line Read/Write Switches and Drivers

12.4.3.4 Word Address Decoding and Selection Sequence - This paragraph takes a specific word address through
the decoding and X- and Y-line selection sequence.
The word address is 017772, and it is assumed that a specific memory bank has been selected. The binary equivalent
of the address is shown below. A read operation is to be performed.

ADDRESS BITS A<17:00>

t--t--t--t--+--+-+--+-'-+--t-'-+--I--!--I--!-----1I--t--I--t

BIT POSITION

OCTAL
, 1-1173

Bits A (13:01) are used to decode the word address. Bit A01 is sent to the device selector (drawing G 110-0-1, sheet
2) and appears at word address flip-flop Ell, pin 2 as AO 1 H (drawing G231-0-1, sheet 2). Bits A (12: 02) are sent to
the Unibus receivers, which are inputs to the associated word address flip-flops. Bit A13 is not used. The input to the
Unibus receiver associated with this bit is connected directly to +5V through jumper 13 (for a 4K memory, 13 is in
and J4 is out). Table 12-3 shows the state of bits A (13:01) and the decoding signals generated by the word address
flip-flops after they are clocked.
12-17

Table 12-3
Word Address Decoding Signals
Address
Bit

Unibus
Receiver
Input

Receiver
Output

Flip-Flop
State

Flip-Flop
Output Signals

AOI
A02
A03
A04
A05
A06
A07
A08
A09
A10
All
A12
A13

L
H
L
L
L
L
L
L
L
L
L
L

H
L
H
H
H
H
H
H
H
H
H
H

set
reset
set
set
set
set
set
set
set
set
set
set
reset

AOlH =H
A02H = L
A03H = H, A03L = L
A04H=H
A05H =H
A06H = H, A06L = L
A07H =H
A08H";H
A09H = H, A09L = L
A10H=H
AllH=H
A12H = H, A12L = L
A13H = L, A13L = H

The output signals from flip-flops A06, A12, and A13 are not used directly from the flip-flops; they are sent to
gating logic (E22 and E25) and are ANDed with signal TSS H. In this case, only two out of a possible six signals are
generated: A06H is low from E22, pin 12 and (A12H . A13L) L is low from E25, pin 8. These signals and the
outputs from the other word address flip-flops are sent to the inputs of the type 8251 decoders to select the
appropriate switches and drivers. READ L is an input to each 8251 decoder. A read operation is to be performed;
therefore, READ L is low.
The decoders, switches, and drivers are shown in drawing G231-0-1, sheets 3 and 4. Using the decoding signals in
Table 12-3 and the operating characteristics of the decoders, it is possible to determine which decoders have been
selected for word address 017772. A decoder is selected only when its D3 input is low. In this case, the selected
decoders are E34 and E46 for the X-line (drawing G231-O-1, sheet 3), and E23 and E8 for the V-line (drawing
G231-O-1, sheet 4). READ L is low and is sent to input D2 of each decoder; it selects read drivers and switches in
this case. To verify this point, refer to the truth table and diagram in Figure 12-9. Decoder inputs DO and D1 select
the particular switch or driver as shown below.
a.

Decoder E34
D1 is high, DO is high: selects output 3 (pin 10), which is read switch XS07.

Decoder E46
D1 is high, DO is high: selects output 3 (pin 10), which is read driver XPRD7.

Decoder E23
D1 is high, DO is high: selects output 3 (pin 10), which is read switch YS03.

Decoder E8
D1 is low, DO is high: selects output 1 (pin 12), which is read driver XPRD5.

The last step is to follow the outputs of the drivers and switches to the stack diode matrix (drawing H213'()-1, sheet
2). For the X-line, the circuit is from driver XPRD7 to diode junction E7-11, across termination 35 to switch XS07.

12-18

For the Y-line, the circuit is from driver YPRD5 to diode junction E4-9, across termination 15 to switch YS03. The
termination indicates the point on the stack printed circuit board where the X- or Y-line is soldered. Physically, the
wire that is connected across the termination is strung through 64 cores per bit mat (total of 1024 cores in series for
16-bit memory).

12.5 READ/WRITE CURRENT GENERATION AND SENSING
In addition to the addressing and control logic, four functional units are involved in generating current to switch the
cores and detect their state. The X- and Y-line current generators supply the drive current (via switches and drivers);
the inhibit drivers allow Os to be written during a write operation; the sense amplifiers detect Is during a read
operation; and the memory data register (MDR) temporarily stores data to be written or data that has been read
from the memory. The follOwing paragraphs describe each functional unit and their interrelationship.

12.5.1 Read/Write Operations
The read/write operations are discussed in terms of the interrelation of the current generator, inhibit drivers, sense
amplifiers, and memory data register. Details of operation of each functional unit are discussed in subsequent
paragraphs. Several control signals are mentioned; however, details of their generation and timing are described in
Paragraph 12.8.
For clarity, one data bit (D07) of the selected word is discussed and the text is referenced to Figure 12-14, which is
a Simplified block diagram. Detailed logic for the memory data register (MDR), Unibus receivers and drivers, sense
amplifiers, and inhibit drivers for all 16 data bits is shown on drawing GIl 0-0-1, sheets 3 and 4.
During a read operation, half-select currents flow in the X- and Y-lines for the selected word in each bit mat. These
currents flow opposite to the write currents; therefore, cores in the 1 state are switched to the 0 state, and cores in
the 0 state are unchanged. Switching the core from the 1 state to the 0 state induces a voltage pulse in the sense
winding. This pulse is detected by sense amplifier E52 as a differential voltage on input pins 6 and 7 that exceeds the
threshold reference voltage. This pulse is amplified and when STROBE 0 H is generated at pin 11, the output of
sense amplifier E52 goes high. Just prior to the strobe signal, the control logic generates RESET 0 L, which clears
(resets) flip-flop E54. The sense amplifier output is inverted by E56 and sent to the preset input (pin 10) of MDR
flip-flop E54. A low on the preset input sets the flip-flop: its I-output (pin 9) is a high and its O-output (pin 8) is a
low. The high from pin 9 of the flip-flop is sent to input pin 1 of the Unibus driver E21. The other input to this gate
is the data out Signal. When the control logic generates DATA OUT H, the output of E21 is low (logical 0 for
memory logic and logical 1 for Unibus logic). This is the readout of bit D07 and is sent to the requesting device via
the Unibus. Timing diagrams for the sense operation are also shown in Figure 12-14.
The read operation is destructive: all cores at the specified location are now O. The data that was read must be
restored by a write operation, which immediately follows the read operation. Flip-flop E54 is still in the set state;
therefore, its O-output (pin 8), which is low, is sent to input pin 9 of NAND gate E53. The control logic generates
the inhibit driver control signal TINHO H, which is the other input to gate E53. The gate is not asserted (pin 8 is
high), and the inhibit driver is not turned on. With no inhibit current in the inhibit line to oppose the half-select
Y-Hne current, a 1 is written back into the appropriate cores.
In this example, if bit D07 is a 0 in core, it does not switch during the read operation and the output of sense
amplifier E52 does not go high. Flip-flop E54 remains cleared (reset): its I-output (pin 9) is low and its O-output
(pin 8) is high. When the control logic generates DATA OUT H, the output of Unibus driver E21 is high (logical I
for memory logic and logical 0 for Unibus logic). The O-output of flip-flop E54, which is high, is sent to NAND gate
E53. During the subsequent write operation, TINHO H is generated, producing a low output signal at E53, pin 8 to
activate the inhibit driver which in turn produces a current that opposes the Y-line current and prevents a I from
being written into this bit of the selected word.

12-19

STROBE 0 H

SENSE
AMP
INPUT
NETWORK

10
12

PRE

0
E54
BIT 007

LOAD 0 H

CLK

CLR

DATA OUT H

007

007
RESET 0 L
UNIBUS DATA LINES 0<15:00>

THRESHOLD
VOLTAGE

SENSE AMP INPUT
FROM STACK

SENSE LINE
OUTPUT E52 (6-7)
RESET 0 L

STROBE H

u
__________~Il~_______________
__________~GJ~________________
1

SENSE AMP
OUTPUT

E56 OUTPUT

~~---------------

~----,I ~n
E54
(
OUTPUTS 0 - - - - - - - '

r~--------

DATA OUT H

_____

_________________

n - -

n n

__ - - - -

E21 OUTPUT
TO UNIBUS

11-1100

Figure 12-14 Interconnection of Unibus, Data Register, Sense Amplifier, and Inhibit Driver

The read/write operation that has been discussed is a read/restore operation (DATI). The requesting device wants to
read a word from memory, and as an internal requirement, the memory must restore the word by writing it back
into core. In this case, the MDR flip-flops are preset by the sense amplifier outputs when Is are read from the core.
The MDR flip-flop outputs are used in the subsequent write (restore) operation to control the inhibit drivers. If the
requesting device wants to write a word into memory (DATO), it must load the data into the MDR flip-flops. The
12-20

requesting device then asserts the data on the Unibus, from which it is picked off via Unibus receivers. In this
example, bit D07 is sent to pin 7 of Unibus receiver EI0. Bit 007 is inverted by the receiver and sent to the D-input
(pin 12) of flip-flop E54. At the start of the DATO operation, the control logic generates LOAD 0 H, which clocks
the flip-flop. If the D-input is high, E54 is set and its O-output is low. Control gate E53 is not asserted by TINHO H,
and the inhibit driver is not turned on. A 1 is written into the selected core. If the D-input is low, E54 is reset and its
O-output is high. Control gate E53 is asserted by TINHO H, and the inhibit driver is turned on. A 0 is written into
the selected core. Because RESET and STROBE are inactive in this mode, the read operation is used only to
magnetically clear all the cores to the 0 state.
12.5.2

x- and Y-Current Generators

Two identical current generators are provided: one each for the X- and V-drive lines. They generate the current
pulses that are used during read and write operations to switch the cores. The current generators and associated
reference voltage supply are shown in drawing G231-0-1, sheet 2. Figure 12-15 shows the V-current generator and
reference voltage supply.

+5V

R83

R85

C52

R86

TWIO H

R84
C51

r-------,
MOUNTED ON STACK

~M!.C~~

TO Y AXIS

...J

HlX)-......--4J~SWITCHES AND
DRIVERS

+5V

R87

R88

060

R89
061

058

C48

R94
062

R90

R91

R92

-15V

R95

063

R93

-15V
"-1101

Figure 12-15 Y-Current Generator and Reference Voltage Supply

Optimum core Switching requires repeatable current pulses of constant amplitude with a linear rise time. The current
generator and reference voltage circuit provide current pulses that meet these requirements. The amplitude of the
output current pulse is determined by the reference voltage circuit; the rise time is determined by an RC circuit in
the current generator; and pulse duration is determined by the length of the triggering pulse TWID H.

12-21

During the quiescent state of the current generator, input transistor QB is on; its collector voltage is 4.7V, and it is
connected to the cathode of diode 062, which reverse biases it. The anode of 062 is connected to the emitter of
transistor Q4, which is the output of the reference voltage circuit. In this state, 062 blocks the output from the
reference voltage circuit to the current generator. With QB on, both output transistors Q9 and QI0 are turned off,
and the current generator is off.
Operation of the current generator is triggered by a high TWID H signal from the control logic. TWID H is double
inverted by two E6 inverters and sent to the base of QB, which turns it off. When QB is cut off, capacitor C52 starts
charging, which provides base drive to output transistors Q9 and QI0 and they begin to conduct. With QB off, its
collector goes negative until it reaches the forward bias level of 062, which is the value of the reference voltage
minus the voltage drop across 062. The rise time of the current pulse is determined by the time constant of C52,
RB7, and RBB. The amplitude of the pulse is determined by the value of the reference voltage. When TWID H goes
low again, the current generator is turned off and the output pulse is terminated.
A resistor network in the base circuit of Q4 (in the reference supply) is used to set the amplitude of the current
generator to approximately 410 rnA. The total resistance of parallel network R90, R91, and R92 is changed by the
configuration of jumpers 11 and 12. The amplitude of the current generator output pulse is factory set as close as
possible to 410 rnA at 25°C. It should not be changed in the field.
The base circuit of Q4 is temperature compensated by a resistor and thermistor that are mounted on the stack. This
ensures that the amplitude of the current generator output pulse remains within specified tolerances over a
temperature range of O°C to 50°C. This temperature compensation is approximately -O.B mAtC.
12.5.3 Inhibit Driver
A detailed schematic of the inhibit driver for bit D07 is shown in Figure 12-16; it is typical of all 16 inhibit drivers
(drawing Gil 0-0-1, sheets 3 and 4).
When the inhibit driver is off, none of the currents shown in the schematic are flowing. Transistor Q7 is held off by
the negative voltage on its base. The output of NAND gate E53 goes low (ground) when this inhibit driver is
selected. Current h flows into the output circuit of E53 from the +5V supply via resistor RB7 and the primary
winding (terminals 15 and 16) of transformer TB. An equal current is induced in the base-emitter circuit of Q7,
which is connected to the transformer secondary winding (terminals 1 and 2). This base current overcomes the
reverse bias voltage and turns on Q7. Current h and therefore induced-current h are determined by resistor RB7 and
the reflected base-emitter voltage Vbe of Q7. When Q7 is turned on, current flows from ground through Balun
transformer T7, isolation diodes D13 and Dl4, and the sense/inhibit winding to the common inhibit terminal
(07IN). The Balun transformer balances the two inhibit half-currents. At terminal 07IN, the full inhibit current
flows through resistor R72 and Q7 to -15V. The value for the inhibit current is calculated as follows:
i inh ~ 15V - Vce sat Q7 - Vbe diodes
R72 + R core mat
~ 15 -0.8 -1.2

13
17.5 = 740 rnA

Each leg of the sense/inhibit winding sees half the inhibit current: approximately 370 rnA. Capacitor C55 decreases
the rise time of the current.
The inhibit driver is turned off when the output (pin 8) of gate E53 goes from low to high. At turn-off time, the
back emf caused by the stack inductive reactance tries to drive the collector of Q7 highly positive; however, diode
D43 clamps this voltage to ground. When the output of E53 goes high (approximately +3.2V), its output pull-up
transistor (an integral part of the gate circuit) tries to drive the turn-off current i4 in the opposite direction through
the transformer primary winding. An equal current induced in the secondary winding removes the forward bias from

12-22

the base of 07 and turns it off. With 07 off, all dynamic current flow ceases in the circuit and the negative voltage
on the base of 07 keeps the circuit turned off until the output of gate ES3 goes low again.
Capacitor C74 allows the gate to pump reverse current i4 into the transformer primary; it also helps to decrease the
turn·on time of 07. Diode DS9 prevents reverse breakdown of the emitter junction of 07.

+5V
STROBE 0 H

R58
VTH

07SB
Ot4

Rt4

5
013

~
~

C40

MOR 007
t2
Rt3

07IN

R57

TO E54

XO
i INH

22mV

R43

-5V
07SA
-t5V

i INH

TINH 0 H
007 (0) H
C74

+5V
11-1102

Figure 12·16 Sense Amplifier and Inhibit Driver

12.5.4 Sense Amplifier
A detailed schematic of the sense amplifier circuit for bit D07 is shown in Figure 12·16; this circuit is typical of all
16 sense amplifier circuits (drawing Gll 0-0· 1, sheets 3 and 4). The circuit consists of the sense amplifier,
terminating network for the sense/inhibit winding, and threshold voltage network.
The sense amplifier input (ES2, pin 6 and 7) is across the sense/inhibit winding (points 07SB and 07SA). Resistors
R13 and R14 are matched to terminate the sense/inhibit line in the desired impedance. Practically speaking, during
the sense operation, the inhibit driver connection is an open circuit through the driver transistor 07. The effect of
the inhibit driver circuit, Balun transformer T7, and isolation diodes 013 and 014 can be ignored during the sense
operation, because the diodes are reverse biased.
Sense amplifier E52 is one half of a dual IC package (type 7528). A simplified block diagram of the package is
shown in Figure 12·17. The two identical circuits are marked 1 and 2. Each one consists of a preamplifier and sense

12·23

amplifier. The output of the preamplifier is available as a test point to observe the amplified core signal and to
facilitate accurate strobe timing. Both circuits share a reference voltage (or threshold voltage) amplifier (pins 4 and
5). In this application, pin 4 is grounded and a positive threshold voltage of approximately 20 mV is supplied to pin
5. This voltage is obtained from the +5V supply through resistor voltage divider R57 and R58; C40 is a bypass
capacitor. Operation of the sense amplifier is discussed in Paragraph 12.5.1.

CIRCUIT 1

DIFF-INPUT{+V
THRESHOLD
VOLTAGE

STROBE H

11- 1'03

Figure 12-17 Type 7528 Dual Sense Amplifiers With Preamplifier Test Points

12.5.5 Memory Data Register
The memory data register (MDR) is a 16-bit flip-flop register that is used to store a word after it is read out of the
memory; or to store a word from the Unibus prior to its being written into the memory. The MDR is composed of
eight 74H74 dual high-speed D-type flip-flops: bits DOO-D07 are shown in drawing G 110-0-1, sheet 3 and are
identified as E54, E57, E60, and E63; bits D08-DI5 are shown in drawing G 110-0-1, sheet 4 and are identified as
E42, E45, E48, and E51.
At the start of a memory operation, the MDR is cleared directly via the clear input (pin
flip-flop: the clear Signal is RESET 0 L for bits DOO-D07 and RESET I L for bits D08-DI5.

or pin 13) of each

The operation of the MDR during a read/restore operation (DATI) and a write operation (DATa) is discussed in
Paragraph 12.5.1.
12.6 STACK DISCHARGE CIRCUlT
The stack discharge circuit assists the stack capacitance in recovering and shortens the rise time of the stack current.
It also reduces unwanted currents in the seven unselected lines associated with the selected driver.
Figure 12-18 shows the stack discharge circuit. Its output is taken from the emitter of transistor Q2 and goes to the
junction of each X- and Y-read/write switch pair via a resistor. This common interconnection is labeled Vo. It is
desired that Vo '=" OV (ground) during a read operation; and VO '=" -15V during a write operation. The effective stack
capacitance associated with each line is shown as Cstack.

12-24

+5V

READ H

-15V
TO ALL OTHER READ/WRITE
SWITCH PAIRS IN X AND
Y AXES
11-1104

Figure 12-18 Stack Discharge Circuit

During a write operation, READ H is low; it is inverted and ANDed with TWID H at NAND gate E4. The low output
(pin 11) of E4 is inverted by E6 and sent to the cathode of diode D51, which reverse biases it. The emitter of Ql
becomes more positive, overcomes the constant positive base bias, and turns on transistor Ql. When Ql conducts, it
provides base drive for Q3, which also turns on. When Q3 conducts, it reduces the base drive on Q2 and it turns off.
The emitter voltage of Q2 goes to approximately -14V, which is Vo on the switch node for the stack. Diode D57
prevents hard saturation of Q3; diode D55 holds Q2 off. During a write operation, Vo = -14V and the stack
discharge circuit is considered to be turned on (input transistor Ql is on).
During a read operation, READ H is high: it is inverted and ANDed with TWID H at NAND gate E4. The gate is not
asserted and its output (pin 11) is high. This signal is inverted by E6 and sent to the cathode of diode D51, which
forward biases it. The voltage on the emitter of Q 1 produced by the current through R 77 and D51 is not enough to
overcome the constant positive bias and Ql is turned off. With Ql off, Q3100ses its base drive and turns off. Now,
D55 cannot hold Q2 off. As long as the stack capacitance is charged negatively, base current exists for Q2 and it
remains on. The stack capacitance now charges in the positive direction until it reaches ground potential. During a
read operation, Vo ~ OV and the stack discharge circuit is considered to be off (input transistor Ql is off).
Figure 12-13 shows how the stack discharge circuit reduces unwanted currents on the seven unselected lines
associated with the selected driver.
During a read operation, the stack discharge circuit is off and Vo = OV. The current generator drives the read driver
node of the stack towards ground; the current generator output is clamped to ground by diode D61. The anodes of
the eight read diodes are at ground. The stack discharge circuit is on and the cathodes of the seven unselected diodes
are also at ground, which back biases them off. The read switch pulls the cathode of the selected line towards -14V,
which forward biases it and allows conduction through the diode. Current flows only through the selected line.
Reverse biasing of the diodes in the unselected lines prevents current from flowing between the unselected nodes and
the selected read driver. The stack discharge circuit performs the same task during the write operation by back
biasing the anodes of the diodes in the unselected lines with -14V.

12-25

12.7 DC LO CIRCUIT
A circuit on the G231 Driver Module (drawing G231-O-l, sheet 2) opens the -15V supply line to the cnrrent
generators when power is interrupted to the power supply. When power is interrupted, the +5V supply is lost and
the operation of all logic is indeterminate. In this state, it is necessary to cut off the -15V supply to the X- and
V-line current generators to prevent them from destroying stored data. The circuit that performs the -15V cutoff is
called the DC LO circuit (Figure 12-19).

+5V

BUS DC LO L
150n O.4V
FROM UNIBUS ---'R"'9""S-="-'-f-l

1.5K
+5V ....JVVIr--......-H
R97

,....-:~--

-15V TO CURRENT GENERATORS

""'-=>'--- -15V FROM SUPPLY
11-1105

Figure 12-19 DC LO Circuit, Schematic Diagram

The -15V supply for the X- and V-line current generators passes through transistor Q7 in the DC LO circuit. Q7
must be turned on for the -15V to reach the current generators. The circuit monitors BUS DC LO L from the power
supply via the Unibus. This Signal is sent to the base of transistor Q5. When power is on, BUS DC LO L is high (not
asserted).
The voltage across R96 forward biases Q5 and it turns on, which turns on Q6. The conduction through Q5 and Q6
forward biases Q7 which turns it on. The -15V flows through Q7 to the X- and V-line current generators.
When power is interrupted, BUS DC LO L goes low (asserted). Q5 is now reverse biased and it turns off, which turns
off Q6. With Q5 and Q6 off, Q7 is also turned off, which opens the -15V line to the current generators. This circuit
still functions when BUS DC LO L is asserted even if the +5V supply drops to zero.
12.8 OPERATING MODE SELECTION LOGIC
When the memory is addressed by the master device, one of four bus transactions is selected. The transaction (or
operation) selected is determined by the states of control bits COl and COO and address bit AOO as placed on the
Unibus by the master device. Table 12-4 shows the states of these bits for each transaction.
The logic that decodes the mode and byte control bits is shown in drawing GllO-0-l, sheet 2; it appears at the
bottom of the sheet and is identified as the byte masking logic. Bits BUS COl, BUS COO, and BUS AOO are taken
from the Unibus to three E29 receivers. One input of each gate associated with COl and COO is connected to the
output of the PROTECT LOW gate (E29 pin 3). Both inputs to this gate are tied to +5V so that its output is always
low. For troubleshooting purposes, a jumper (WIt) can be installed that makes the gate output high, which allows
only DATI operations to be performed regardless of the states of bits COl and COO. This jumper hardwires the
memory as a read-only device.

12-26

Table 12-4
Selection of Bus Transactions

Octal

Byte
Control
AOO

Data from memory to master. Memory
performs operations.

DATIP

Data from memory to master. Restore
operation is inhibited. Must be
followed by DATO or DATOB: Read
operation is inhibited.

Data Out

DATO

Data from master to memory (words).

Data Out,
High Byte

DATOB

Data from master to memory. High
byte on data lines D (15:08).

Data Out,
Low Byte

DATOB

Data from master to memory. Low
byte on data lines D (07:00).

Mode Control
Transaction

Mnemonic

Data In

DATI

Data In,
Pause

C (01 :00)

Function

The outputs of the three E29 receivers (COl, COO, and AOO) are sent to the byte masking logic to generate LOAD 0
H and LOAD 1 H and to qualify a group of gates, which are enabled by control signals to generate RESET 0 L,
RESET 1 L, STROBE 0 H, STROBE 1 H, and DATA OUT H. The logic also conditions the D-input of the PAUSE
flip-flop (E4, pin 12) to allow it to be set or reset. It also applies conditioning signals to the wired-AND that provides
the clocking signal to the slave synchronization (SSYN) flip-flop. The PAUSE flip-flop and the SSYN flip-flop are
part of the control logic.
The Signals generated for each bus transaction are shown in Table 12-5. The memory operational sequences are
discussed in subsequent paragraphs. To avoid confusion in interpreting the transactions listed in Table 12-5, the
purpose of the PAUSE flip-flop is discussed briefly. During DATIP, the PAUSE flip-flop is set during the read
operation, which inhibits the restore (write) operation. The DATIP must be followed by a DATO or DATOB on the
same address. The DATO or DATOB that follows a DATIP is shorter than a standard DATO or DATOB because the
initial read operation is eliminated. In Table 12-5, the sufflx PAUSE L identifies the standard transactions; the sufflx
PAUSE H identifies the DATO and DATOB transactions that must follow a DATIP.
12.9 CONTROL LOGIC
The control logic generates the precisely timed signals that initiate and stop the memory operations that are
requested as a result of the decoding of the bus transaction. The heart of the control logic is the delay line timing
circuit. For better understanding, the timing circuit, slave sync circuit, pause/write restart circuit, and strobe
generating circuit are described separately. Each bus transaction is also discussed in detail. The discussion is to the
detailed logic level but the signals are not traced through each component. The text is referenced to logic drawing
GllD-0-1, sheet 2 and the timing diagrams in drawing MMII-L-3.

12-27

Table 12-5
Generation of Memory Operating Signals

Mode

Byte
Control
AOO

Mode
State of
Control
PAUSE
COl COO Flip-Flop

Signals Generated

....

[.1.l

Q:l

~
Eo-<

Q:l

~
Eo-<

Operation Sequence

:c:
0
Eo-<

[.1.l
CJ:l

CJ:l

....
Eo-<

:;j

....
:;j

.....:I

[.1.l
CJ:l

!;
0

<:
Eo-<
<:

DATI

Reset

Read-Restore.

DATIP

ResetSet

Read-Pause. Restore inhibited by PAUSE flip-flo p.

DATO
PAUSE L

Reset

Clear-Write.

DATO

Set

Write. Must follow DATIP.

DATOB
PAUSE L

Reset

Clear-Write selected byte
O. Clear-Restore nonselected byte 1.

DATOB
PAUSEH

Set

Write selected byte O. Restore non-selected byte 1.
Must follow DATIP.

DATOB
PAUSE L

Reset

Clear-Write selected byte
1. Clear-restore nonselected byte O.

DATOB
PAUSEH

Set

Write selected byte 1. Restore non-selected byte O.
Must follow DATIP.

12.9.1 Timing Circuit
The heart of the memory control logic is the timing circuit. When activated, it generates a series of precisely timed
signals that control memory operation. The major component of the timing circuit is a delay line (DLl) with
multiple 25-ns taps (drawing CIIO-O-I, sheet 2). The delay line outputs are gated to produce the control signals.
Figure 12-20 shows the timing of the delay line outputs and the timing of the control signals obtained by gating
these outputs. A brief statement of the function of each control signal is included. Absolute timing is obtained from
the engineering timing diagram (drawing MMII-L-3). The discussion is referenced to Figure 12-20 and the control
logic drawing GIl 0-0-1.
When the system is turned on, the processor asserts BUS INIT L on the Unibus. This initializing signal is sent to pins
6 and 7 of bus receiver E7. It is inverted by E7 to produce a high, which is sent to pins 9 and 10 of the memory
select reset (MSEL RESET) gate EI6. The output (pin 8) of EI6 is low and is used to clear (reset) MSEL flip-flop E2
via the 100-ns delay DL3. The output of E7 is also inverted by E18 to provide a low that clears read/write (R/W)
flip-flop E3. The output of E7 is also inverted by EI5 to provide a low that clears PAUSE flip-flop E4. The low

12-28

100

150

200

250

300

350

400

450n5

lL________________________...Jr!
11. . _____-'

BUS MSYN L

{INITIATES MEMORY CYCLE, RESeTS SSVN FF E4

5
DL1 DELAY
LINE TAPS

GATED TOGETHER AS SHOWN BELOW

--li

L..-...._ _ _

DEL FF RES L
(6L- BH) E27-P6

{ RESETS DELAY FF E28 BOTH IN READ AND WRITE.

RESET H
(2L-4H-READ H) E7-P3

{

RESETS DATA FF's (BITSO-15) AND STARTS STROBE DELAY.
useD ONLY DURING READ.

{ CONTROLS SWITCH TIMING DURING READ AND DRIVER TIMING DURING WRITE.

CONTROLS lORH DURING READ AND TSSH DURING WRITE. CONTROLS
{ CURRENT GENERATOR AND STACK DISCHARGE TIMING. useD AS TINH DURING
WRITE CYCLE.

MSEL RESET H

+_-------------------------'

MODE; AT END OF WRITE CYCLE IN ALL OTHER MODES.

R/W RESET H
(BH-9L) ~E2~6~-~P~I~0~--------------------------------~

=E~I7~-~P~3~__

{ GATES SENSE AMPS TO DATA LATCHES DURING REAOCVClE.
TRAILING EDGE SETSSSVN FF E4 DURING DATI· DATIP MODES.

_r-----------------------J.,

{ GENERATES NARROW WIDTH (35 ns) STROBE PULSE FROM TRAILING EDGE OF
STROBE DELAY.

STROBE OS l:;E2~B::...-.!.P~9_____J

READ H

{ RESETS R/W (READIWRITE) FF E3 AT ENDOF READ CYCLE.

{ ADJUSTED TO GIVE PROPER DELAY FROM READ CURRENT TO STROBE.

STROBE DEL L E36-P1

STROBE H

RESETS MSEl (MEMORY SELECTED) FF E2 AT END OF READ CYCLE IN DATIP

{

(6H-BL)E:2:6~-~P~I~3__

E3-P9

WRITE
RESTART L E25-P3

CLKI H

{

CLOCKS DELAY FF E28 TO START WRITE TIMING CHAIN.
DOES NOT OCCUR IN DATIP.

{

Ef4-P6

CLOCKS (R/W, AD, CO, CI FFI ON G110, (Al·A13 FF) ON G231 IN ALL MODES.
IN DATO AND DATOB MODES, IT BECOMES LOADO, 1H.

CLK2 H EI5- P4

CLK SSYN H E4-P3

LOAD L

DATO, DATO B

{ SETS SSYN FF E4 AS SHOWN.

{STROBES DATA FROM BUS TO DATA FF 0·151N DATO AND DATOB MODES.

E34-PII

DATAOUT H E~6~-~P~3~--------------------------------___
SSYN H E5-P2

DATA OUT H STROBES DATA FROM DATA FF 0·15 TO UNIBUS IN DATI AND DATIP
{ MODES.
SSYN H BECOMES BUS SSYN L. WHICH KEEPS MSEL FF FROM SETTING.

TIMING CHAIN READ OR WRITE
"-1108

Figure 12-20 Basic Timing and Control Signal Functions

12-29

output of EI5 is double inverted by two E38 gates to clear the DEL flip-flop E28. The master places the address,
mode control state, and data (if required) on the Unibus. The device address is decoded and DSEL H is generated
and sent to pin 13 of El, which is one of four input signals (pins 10, 11, 12, and l3). Pin 11 is high via the a-output
of MSEL flip-flop E2. SSYN flip-flop E4 is preset, making pin 10 of El high via its I-output (pin 5). When the
master asserts BUS MSYN L to bus receiver E23, pin 12 of El is high also. The output of El (pin 8) goes low and is
sent to pin 13 of E5, pins 4 and 5 of E14, and pin I of delay line DL2. EI4 inverts the low from EI to start the
positive eLK 1 H pulse. DL2 provides a 30-ns delay for the low signal from El, which is inverted by EI5 to start the
positive eLK 2 H pulse. The output (pin 3) of DL2 is also sent to the preset input (pin 4) of MSEL flip-flop E2, and
pin 6 goes low which in tum is fed back to pin 10 of EI to disable it. The output (pin 8) of El is now high, and this
signal terminates both clock pulses (eLK 1 H and eLK 2 H) via gates EI4 and E15. These pulses are approximately
50-ns wide.
Gate E5 also inverts the low from El because pin 12 (WRITE RESTART L) of E5 is high. The positive transition at
the output (pin II) of E5 clocks delay (DEL) flip-flop E28 which sets it. Pin 5 of E28 is high and is connected to
pins I and 2 of DLl driver gate E34. The low from the E34 output (pin 3) is the input to delay line DLl. This signal
remains low for approximately 225 ns until DEL flip-flop E28 is cleared by DELAY FF RESET L. This provides a
negative pulse that propagates through the delay line and can be picked off at 25-ns intervals.
DLl taps 2,4,5,6,7,8, and 9 are used to generate control signals. Figure 12-20 depicts each control signal and
relates it to logic drawing G 110-0-1, sheet 2.
DELAY FF RESET
Tap 6L is inverted by E15 and sent to pins 3 and 5 of 3-input NAND gate E27; the third input (pin 4) is tap 8H. The
output (pin 6) of E27 clears the DEL flip-flop E28; however, it is ORed with INIT L in gate E28 (pins 9 and 10) and
inverted by E38, pin II so that either (6L . 8H) or BUS INIT L can produce DELAY FF RESET L, which clears
E28 via its clear input (pin I). This signal is generated in both read and write operations.
RESETH
Tap 2L, tap 4H, and Signal READ H are gated to generate RESET H, which triggers the strobe delay circuit and
generates RESET a L and RESET 1 L during the read operation only. Tap 4H and READ H (high during read
operation) are ANDed at pins 10 and 9 of E17. The low output of E17 is ANDed with tap 2L in gate E7. The high
output (pin 3) is RESET H.

TWID Hand TNAR H
The a-output of DEL flip-flop E28 is ORed with tap 5L and tap 7L in separate gates (EI4) to produce signals TWlD
Hand TNAR H. Tap 5L is sent to pin 13 of E14; the other input to this gate (pin 12) is from the a-output of DEL
flip-flop E28. Tap 7L is sent to pin 10 of another E14 gate; pin 9 of this gate is also connected to the a-output of
DEL flip-flop E28. These gates are 2-input NAND gates (type 7437); however, they are shown as logically equivalent
negative-input OR gates, because it is desired to have them asserted high (logical 1) when TWlD H or TNAR H is
asserted.
At the start of a read or write cycle, just before E28 is set, TNAR and TWID are low because both inputs to each
gate are high. E28 is set and pins 12 and 9 of E 14 go low; TNAR and TWID are both high, which starts the positive
TNAR and TWID pulses Simultaneously. When taps 5 and 7 go low (E28 is still set), TNAR and TWlD remain high.
At the end of the read or write cycle, E28 is cleared (taps 5 and 7 are still low) and TNAR and TWID still remain
high. When tap 5 is high again, TNAR goes low because both inputs (pins 12 and 13) of E14 are high. This
terminates the positive TNAR pulse. Approximately 50-ns later, tap 7 is high again and TWID goes low, terminating
the positive TWID pulse. In summary, TNAR Hand TWID H are started together by setting DEL flip-flop E28
before taps 5 and 7 are low; TNAR Hand TWID H are not effected when taps 5 and 7 go low. Signals TNAR Hand
TWID H are terminated when taps 5 and 7 return high. The intervening cl~aring of E28 does not affect TNAR H or
TWIDH.

12-30

Signals TNAR Hand TWID H provide various control functions related to the operation of the switches, drivers,
current generators, inhibit drivers, and stack discharge circuit. At this point, the discussion digresses to follow TNAR
Hand TWID H through some additional logic in order to understand their functions. The logic is spread throughout
several engineering drawings. To simplify the discussion, all the logic is shown in Figure 12-21.

READ H

TWID H

READ H

READ L

TO X - AND Y CURRENT
GENERATORS

9 E6

TO STACK
DISCHARGE CIRCUIT
I-ON
O-OFF

WRITE H

Gl10-0-1 SH2

TO ALL SWITCH AND
DRIVER DECODERS

- - -,
I
--

I
I
I

L
R/WFF
E3 PIN B
O-READ
I_WRITE

TO DRIVER
DECODERS ONLY

- -

- - - -,
TINH OH

TINH I H

L_ - TO INHIBIT DRIVERS
FOR BITS D
TO INHIBIT DRIVERS
FOR BITS D<15:08>

- - r 1-1146

Figure 12-21 TWlD Hand TNAR H Control Logic

Signal TWID H is ANDed with the O-output (pin 8) of R/W flip-flop E3 at pins 9 and 10 of gate E25. With TWID H
high, E25 is asserted only when E3, pin 8 is high; this occurs only during a write operation. The output (pin 8) of
E25 is inverted by E14 to procure TINH 0 Hand TINH 1 H. The output of E14 is physically divided into two
paths: TINH 0 H activates the inhibit drivers for bits D (07:00), and TINH 1 H activates the inhibit drivers for bits
D (15 :08). These signals do not leave the control module because the inhibit drivers are also on this module.
Signals TWID Hand TNAR H leave the control module (GllO) and are sent to the drive module (G23l). TWID His
sent to pin- 4 of E2R, and TNAR H is sent to pin 2 of E2W. Gates E2 and E4 are marked Wand R in Figure 12-21 to
show their association with write or read operations. READ H is sent from the I-output (pin 9) of R/W flip-flop E3
on the control module to pin 9 of inverter E6 on the driver module. READ H is high during a read operation and
low during a write operation. Assume that a read operation is selected. READ H is high at pin 9 of E6 and is sent to
pin 5 of E2R to be ANDed with TWID H. This gate is asserted and its low output is sent to pin 12 of negative-input
NOR gate E2, which inverts it to produce TDR H. This signal is a decoding input for the memory read/write drivers
only. Gate E2W is not asserted because WRITE H, which is the inversion of READ H, is low. Therefore, TWID H
controls decoding signal TDR H during a read operation. During a write operation, READ H is low and WRITE His
high. Signal TDR H is asserted via the output of gate E2W, using the ANDing of WRITE Hand TNAR H. Decoding
signal TDR H is controlled by TNAR H during a write operation.

12-31

A similar logic network is used to control signal TSS H, which enables six decoding signals that are in turn used to
control memory read/write switches only. When gates E4W, E4R, and E4 are used, TSS H is generated at the output
(pin 3) of E4. During a read operation, TNAR H controls enabling signal TSS H; signal TWID H controls TSS H
during a write operation.
TWID H controls the operation of the X- and Y-current generators. During read and write operations, when TWID H
is high, the signal is double inverted by two E6 inverters to turn both current generators on.
The TWID H signal also controls the operation of the stack discharge circuit. It is ANDed with WRITE H at pins 13
and 12 of NAND gate E4. The output (pin 11) of E4 is inverted by E6 to control the stack discharge circuit. This
circuit is considered to be turned on when the output (pin 2) of E6 is high. This occurs during a write operation
when TWID H and WRITE H are both high.
Although not part of the timing circuit, Figure 12-21 shows READ H inverted by two E6 inverters to become READ
L, which is a decoding input to all 8251 decoders for the memory switches and drivers. During a read operation,
READ H is high and READ L is low, which selects only read switches and drivers; conversely, during a write
operation, READ L is high, which selects only write switches and drivers (Paragraph 12.4.3.2).
MSELRESET
The memory select (MSEL) flip-flop E2 is cleared (reset) at the end of a read operation in DATIP mode and at the
end of a write operation in all other modes (DATI, DATO, and DATOB) by signal MSEL RESET L. The MSEL
RESET L signal is generated at the output (pin 8) of gate E16 (a type 74H53 2-2-2-3 input AND-OR-invert gate).
Three of its four AND inputs are used to facilitate the various methods used in generating MSEL RESET L (Figure
12-22).
When the system is turned on, the processor asserts BUS INIT L on the Unibus. The output of bus receiver E7 is
high; this high output is sent to pins 9 and 10 of E16 to generate MSEL RESET L at its output (pin 8). The MSEL
RESET L signal is passed through a IOO-ns delay line (DL3) to the clear input (pin 1) of MSEL flip-flop E2, which
directly clears (resets) it. All memory operations start with E2 cleared; however, this flip· flop is set approximately
75 ns after the processor asserts BUS MSYN L. It remains set until it is cleared by one of the following operations.

E26 PIN 4
1 ONLY
IN DATIP
R/W FF E3 PIN 9
1-0UTPUT

12
13

DL1 TAP 8

MSEL RESET L
TO CLEAR INPUT
OF MSEL FF E2

DL1 TAP 6

BUS I NIT L ---~~2
U
"

Failure
Symptom

onI

Memory Does Not
Respond to MSYNL

"'" E'"
en

:::l

;;

Memory Hangs Bus

'-=>-

I.l..<
>--l
<"-l

0.
0

.e.

i:i:

0.
0

i:i:

.9-

c;ja
a 0

::E

"-l
en

i:i:
Z
>en
en

-l

u
0.
0

i:i:

.e.

"-l
en

i:i:

<
c...

0.
0

i:i:

.9-

C<:.."!

C<:

~if

<
"-l

"u,.0..
,,,=

"-l

0
C<:
fen

-l

f"-l
en

"-l

C<:

-l

X
X

!30
<
f<
a

u au

" '"u>
E

U
-l

r.;::

0
::.-

Z 0
~'t;

-l "
<
i:!
~f-

0.'"

~g
"t:Jf-"
.~
"
:::l
~a en
" 0

"
C<:

<.I)

COO
COl

'"
~
a'"
-l

"0
E ~

>..<=

:.a o..c
.5 Nf-

:.::l

"
:.::l
en
-'"
u

eli'"

"'"

~
-'"
u

eli'"

"0;

i:5

"
C<:

-'"
u

eli'"

"5
,g '"e?
. <'"=

"0
0

"s
~

_..<=
'"

"
enf-

u
"0

"u i:5

~
>-~

, "
XC<:

i:!

E-;<

;><:

u
a

;><:

"5
-'"
u u

i.:l

'"
i.:l

v:)

'" 0...

- -

en
en
C<:

en
en
>-

C<:

en
en

C<:

-l

...
"0.E
:::l

'"
0:.
-'"
u

,..~

>
on
+

>
on

DATa Fails

DATIP Fails

Many Bits Fail

Picks Bits

Drops Bits

Hi
X

+5
FA2
X

2 Bits Fail

X
X

1 Bit Fails

4 Bits Fail

Byte Failures

Fails All Addresses

. <=

AI-A3 Common

A4-A6 Common

A7-A9Common

AIO-AI3 Common

X
X
X
X

READ Waveforms
Wrong
WRITE Waveforms
Wrong

No Inhibit

Location

C = Gil 0 Sense Control
{ S = Stack
D= G231 Driver

X = Indicates Circuit Not Operable
Lo = Measured Parameter Too Low or Early
Hi = Measured Parameter Too High or Late

Figure 13-2 Troubleshooting Chart

13-3

READ

WRITE

rr----------~A~----------~

rr----------~A~----------~,

,,------~--------f

-",1-----:----1'

Gll0 MODULE
+5V

IG214 MODULE

I GIl 0

I SA

MEMORY
4096 CORES

MODULE
TERMINATION

SENSE AMP
TP
-12V

OPEN INH. OR SENSE

-------------

~OR~ ~,______________________;l~----------~I_G_N_D____________________~I_1.5V
2V
SENSE IINH
WINDING
8K CORE MAT

FROM MDR
FLIP-FLOP
TINH H@

I
I

SB
DATA IN

>---~--------------------~---------

INHIBIT
BASE DRIVER

LOAD

-t!lV

y
INHIBIT DRIVER

RESET L
UNIBUS

11-1151

STROBE

®
0
DATA ON BUS FROM OTHER UNITS WILL ALSO APPEAR HERE

U
11-1152

Figure 13-3 MMII-K Sense/Inhibit Waveforms

13-5

+5V

TWID H

16.9.0.

READ

WRITE

OPEN LI NE

CURRENT GENERATOR

VREF

+5V

OPEN LINE

I ~OR WPS - l C ; ::~
lJ-

,; CURRENT LOOP

15V
-25V

INOP RNS

+5V

OPEN LINE

+5V

--OR WNDR-:
OPEN LINE

INOP WPS

TO DECODER

®
®

L-_ _ _ _ _ _--I.

......'lNIr-.()

-15 V

MEMORY
CORES

0-15V

~+5V®

- -- - Dotted line show possible
failure waveforms.

+1.5V
11-1154

*TDR H

8251
DECODER

AX
READ L

AX
AX

(ONLY
ONE
OUTPUT 1 > - - - - - -......
SHOWN)

5.1D.

Indicates module conn pin.

*TDR H and NAND
gate are used on

(VB- VA) follows waveform
shown below.

-15V

driver decoders only.

11-1153

Figure 13-4 Drive Waveforms

13-7

13.4 PROGRAMMING TESTS
Certain DEC programs may be used to test various memory operations as an aid to troubleshooting. The purpose of
each of these memory-related test programs, as well as the program abstract, is given in the following paragraphs.
Each program contains instructions for use.
13.4.1 Address Test Up (MAINDEC-ll-DIAA)
The purpose of the Address Test Up program is to demonstrate that the selected memory area is capable of basic
read and write operations when address propagation is upward through memory. This test program writes the
address of each memory location (within the test limits) into itself and then increments through memory until the
address corresponding to the high limit is reached. After this location has been written, the memory enters the read
cycle. The read cycle starts with the high limit location and reads and compares each word location, decrementing
down to the low limit location. The program halts on an error.
The program ensures that all addresses are selectable and can also be used to isolate bad switches, wiring errors, or
address selection errors. It will also find double selection errors when two bus addresses select the same core address.
13.4.2 Address Test Down (MAINDEC-ll-DIBA)
The purpose of the Address Test Down program is to demonstrate that the selected memory area is capable of basic
read and write operations when address propagation is downward through memory. It is a companion test to the
Address Test Up program (Paragraph 13.4.l).
This test program writes the address of each location into itself, downward through memory. After writing down,
the program reads and checks back up through the memory test area. The program halts on an error.
The Address Test Down program resides in the high portion of core memory. It does not check memory below
address 100, as these locations are reserved for trap and vector locations. The program verifies that all modules can
perform their basic functions, checks that all addresses are selectable, and can also be used to isolate faulty switches,
wiring errors, or address selection errors.
13.4.3 No Dual Address Test (MAINDEC-ll-DICA)
The purpose of the No Dual Address Test program is to check the unique selection of each memory address tested.
This test is divided into two parts. The first portion of the test fills the test field with Is and writes as into the first
test location. This is followed by a read check from this location. The program then checks each field location to
ensure there are no variations from the 1s configuration. Upon completion of this test, the test location pointer is
incremented. The next location is then write/read exercised with as, and the test field rechecked for any change in
content. When the selected test field has been tested in this mode, the program sets a flag and the second portion of
the test is begun. The program fills the test field with as and the field is then tested with a write/read exercised with
Is.
This program checks for faulty switches or wiring errors, checks the complete address selection scheme, and checks
all 16 bits in the data field for 1s and as operation.
13.4.4 Basic Memory Patterns Test (MAINDEC-II-DIDA)
The Basic Memory Patterns Test program has two main purposes:
a.

Verify that the selected memory test field is capable of writing and reading fixed data patterns.

Verify that the memory plane is properly strung.

13-9

This test program writes a specific pattern throughout a given memory zone, then reads the pattern back and
compares it with the original for correctness. If the pattern read fails to compare correctly with the original, the
program initiates a call to the error subroutine. After completely checking the pattern, the program continues on to
the next pattern test.
13.4.5 Worst-Case Noise Test (MAINDEC-ll-DIGA)
The purpose of the Worst-Case Noise Test program is to generate the maximum possible amount of plane noise
during execution of memory reference instructions to check system operation under worst-case conditions.
This test program is designed to produce the greatest amount of plane noise possible during memory read and write
cycles. The noise parameters are affected by a number of factors. The noise generated is distributed across the core
plane algebraically and adds to the normal dynamic noise present on the sense lines. This can cause misreading of
data (within the plane) that is in the low (1) or high (0) category. The sense windings of most memories are such
that worst-case patterns can be caused by alternately writing -1 and 0 data configurations throughout memory. Under
these conditions, worst-case noise is generated by performing a read, write, complement operation at each location.
The test is repeated after complementing all of the pattern data stored in the memory test zone; thus, all cores are
tested for worst-case as both 1s and Os. The pattern or its complement is written into the memory test zone as
determined by the exclusive-OR between address bits 3 and 9.
The Worst-Case Noise Test program is divided into two parts. Part 1 is run first and, during this part of the program,
a -1 configuration is written into all locations having an address with an exclusive-OR state between bits 3 and 9. All
other locations are loaded with the 0 configuration. After the test zone has been loaded, the memory is rescanned.
This time, each location is read, complemented, read, and complemented (RCRC). Any location detected as being
disturbed by a previous RCRC operation is flagged as an error. Upon conclusion of the read scan loop, the program
automatically switches to Part 2.
During Part 2 of the program, the data patterns stored in memory are complemented. In other words, 0 patterns are
stored in locations having addresses with an exclusive-OR between bits 3 and 9. All other locations are loaded with
the -1 configuration.
The exclusive-OR pattern distribution for Parts 1 and 2 is summarized for reference as follows:
Part 1
Exclusive-OR (3 and 9) = 1 pattern
No Exclusive-OR (3 and 9) = 0 pattern
Part 2
Exclusive-OR (3 and 9) = 0 pattern
No Exclusive-OR (3 and 9) = -1 pattern
After memory is loaded, it is scanned again with a read, complement, read, complement (RCRC) loop as previously
described. Any location detected as being disturbed by a previous RCRC operation is flagged as an error.
Before writing or reading any location (in either part of the program), the program issues a call to subroutine
XORCK (exclusive-OR check) that tests bits 3 and 9 and sets the XORFLG if the exclusive-OR condition is present.
Subroutine ERRORA is called for any location disturbed from the -1 configuration; subroutine ERRORB is called
for any location disturbed from the 0 configuration.
The program prints out errors and repeats when complete without interruption. Upon completion, the program rings
the teletype bell and then halts if switch 12 is present. A continue from the halt initiates another pass.
If the program indicates an error, use the troubleshooting chart as a guide to locate the fault.

13·] 0

PART 4
POWER SUPPLY

Part 4 provides specifications and a general physical description of the power supply.
A detailed circuit description and maintenance information are also included. The
chapters of Part 4 are:

Chapter 14 - Power Supply General Description
Chapter 15 - Power Supply Detailed Description
Chapter 16 - Power Supply Maintenance

CHAPTER 14
POWER SUPPLY GENERAL DESCRIPTION
14.1 INTRODUCTION
The power supply is a forced air-cooled unit that converts single-phase l15V or 230V nominal, 47-63 Hz line voltage
to the three regulated output voltages required by the computer. The output voltages and their principal uses and
characteristics are:

Characteristics

Use

Voltage
+15V

Communication Circuits

Series regulated and overcurrent protected.

+5V

IC Logic

Switching regulated and overvoltage and overcurrent protected.

-15V

Core Memory

Switching regulated and overvoltage and overcurrent protected.

The power supply is used in conjunction with the BC05HXX (l15V) or BC05JXX (230V) Power Control
Assemblies, which contain a line cord, circuit breaker, and RFI capacitors. Line cord length is specified in the part
number; e.g., l15V, 6 feet is designated BCOSH06.
The power circuitry also generates BUS AC LO L and DC LO L power fail early warning signals, and the LTC L
real-time clock synchronizing signal.
A thermal control mounted on the heat sink will interrupt the ac input should the heat sink temperature become
excessive due to fan failure or other cause.
14.2 PHYSICAL DESCRIPTION
The power supply comprises three major subassemblies and two cables:
assembly, dc regulator module, dc cable, and ac cable.

the power control unit, power chassis

14.2.1 Power Control Unit
The power control unit (drawing H400-0-O) is mounted to the rear of the computer by two screws. It contains line
cord, circuit breaker, RFI capacitors, 115V or 230V connections for the power supply transformer, and an output
6-socket Mate-N-Lok connector. Physically, it consists of a sheet metal bracket and a slide-on cover that is locked in
place by one screw. A single pole thermal breaker and a line cord strain-relief grommet are mounted on the. flange of
the bracket, making the line cord and breaker reset button accessible on the rear of the computer.

14·1

A small printed circuit card is mounted directly to the breaker terminals. This card interconnects and mounts the
RFI dual-disc ceramic capacitor, the output Mate-N-Lok connector and three fast-tabs for ac input and ground
connections. A dual fast-tab is connected directly to the bracket. The black and white line cord wires are connected
via fast-tab to the PC card; the green (ground) line cord wire is connected to the dual fast-tab, which in turn is
connected to the third fast-tab on the PC card.
The 115V and 230V models differ in only two respects: breaker current rating and (printed circuit) jumpers for
parallel or series connection of the power supply transformer primaries. Power control part numbers are: BC05HXX
- 115V, 7A; and BC05JXX - 230V, 4A; where XX denotes line cord length; e.g., BC05H06 has a 6 foot line cord.
14.2.2 Power Chassis Assembly
The 700 8731 Power Chassis Assembly (Figures 14-1 and 14-2) consists of a long, inverted V-shaped chassis,
700-8726 power transformer, and a 5-inch fan. It is secured to the bottom of the computer by f.our 8-32 by 3/8 inch
Phillips pan-head bolts.

:; Cti ~ ~trr Vt:t.. T :i·(iE
. [\OJUS ~ ~;~r:rrr 7tJTtr~,!r~Oitrf€"EB,';

~,l

i'
niliHl\!!D~i'A"i
~'iiA·rf~· ·)\J~t()K

cr)~~r-\~f~,~T(~f't

Figure 14-1 Power Chassis Assembly (with DC Regulator Module)

14-2

Mtn'E"N·I.OR

CONNECTOR

CONNE.(;TOR

Figure 14-2 Power Supply Assembly (with DC Regulator Module Removed)

The chassis is mounted to the right of the connector blocks, when viewed from the front, and airflow is from front
to rear. The fan is held to one end of the chassis by two screws; the transformer is held to the other end by four
mounting studs. The transformer may be removed by loosening four nuts, which are accessible through large holes
on the bottom of the power chassis.
The dc regulator module is mounted to the chassis assembly by six screws and must be removed for cable access. The
dc cable enters a slot on the connector block side of the chassis; the ac cable enters a slot on the other side.
Connections to the fan are made by small fast-tabs; connections to the transformer are made via Mate-N-Lok
connectors: 6-pin for primary, 3-socket for secondary.
14.2.3 DC Regulator Module
The 5409728 DC Regulator Module (Figures 14-3 and 144) is a printed circuit assembly, mounted to the power
chassis assembly by four 6-32 by 9/16 inch and two 6-32 by 1/4 inch Phillips pan-head screws.

14-3

POWER SUPPLY FAN

THERMOSTAT
MATE-N·LOK CONNECTOR

POWER CONTROL
MATE~·lOK

CONNECTOR

Figure 14·3 DC Regulator Module (Top View)
DC REGULATOR MODULE

Figure 144 DC Regulator Module (Bottom View In Mounting Box)

14·4

Computers that were shipped during the first three or four months of production use a dc regulator module
designated 5409728-YA-O; later shipments use a module designated 5409728-0-0, E revision. There are differences in
component values on the two modules. The discussion of the dc regulator module circuits in this manual is directed
to the later module, designated 5409728-0-0. Engineering drawings applicable to the module used are shipped with
the equipment. These drawings provide schematics and component values of the dc regulator module.
This module contains all the circuitry between the transformer secondary winding and the power supply output
cable. The transformer secondary 3-socket Mate-N-Lok connector is plugged into a mating connector that is soldered
directly to the printed circuit board and is accessible underneath it. The 9-pin Mate-N-Lok connector on the dc
output cable to the computer is similarly mated to a connector underneath the other end of the board.
The dc regulator module may be probed for troubleshooting purposes from the top; all points on the circuit are
available. It may also be removed from the top for cable access and for parts replacement by removing the six
mounting screws.
The printed circuit is approximately 5 by 10 inches, with about half of the top surface devoted to the heat sink. The
power transistors and power rectifiers are bolted to two shelves on the sides of the heat sink and make contact with
the circuit board directly underneath via solder and screw connections. The heat sink is hard anodized for electrical
insulation.
The other half of the top surface is devoted to interconnecting and mounting the balance of the circuit. Three small
output voltage adjustment potentiometers are accessible on this top portion of the board.
Two small pico fuses are mounted on the top of the PC board on the fan end. These fast-acting fuses will typically
only blow when some component is defective or when the +5V or -15V is too high. The two input filter capacitors
are held to the underside of the board by a bracket and are connected to the circuit via jumper tabs on the fan end.
The +5V and -15V output filter capacitors and inductors are also mounted under the board, the former by screws
and the latter by nuts.
Care must be taken to ensure that all electrical and mechanical connections are secure. In manufacturing, the
hardware is tightened with a torquing device set to 12 inch-pounds.
14.2.4 DC Cable
This is a simple cable connecting the computer module to the dc power module via a 9-pin Mate-N-Lok. The latter is
made accessible by loosening the six mounting screws and lifting out the dc module. Cable access is through a slot on
the computer module side of the power chassis.
14.2.5 AC Cable
This cable interconnects all ac portions of the computer chassis (Figures 14-1 through 14-4). The ac portions of the
computer chassis are as follows:
a.
b.
c.
d.
e.
f.

Power Supply Fan - two fast-tabs
Power Supply Thermostat - one 2-pin Mate-N-Lok
Memory Section Fan - two fast-tabs
Transformer Primary - one 6-socket Mate-N-Lok
Power Control - one 6-pin Mate-N-Lok
PDP-II System AC Power Control - two 3-pin Mate-N-Lok connectors on rear of computer.

The ac cable is located on the right-hand side and rear of the computer and is inherently shielded by the power
supply chassis and the computer chassis.

14-5

14.3 Specifications
Tables 14-1. 14-2. and 14-3 list all the power supply specifications according to input, output, and mechanical and
environmental specifications.

Table 14-1
Power Supply Input Specifications
Parameters

Specifications

*Input Voltage (1 phase, 2 wires and ground)

9S-13S/190-270V

Input Frequency

47-63 Hz

Input Current

S/2.5A RMS

Input Power

32SWat full load

Inrush

80/40A peak, 1 cycle

Rise Time of Output Voltages

30 ms max. at full load, low line

Input Overvoltage Transient

180/360V, 1 sec
360/nOV, 1 ms

Storage After Line Failure

2S ms min., starting at low line, full load

Input Breaker (part of BCOS Power Control)

7A/4A single-pole, manually reset, thermal

Thermostat Mounted on Heat Sink (opens
transformer and fan power)

277V 7.2A contacts
Opens 98-lOSoC
Automatically resets S6-69°C

Input Connections

Line cord on BCOS Power Control, length
and plug type specified with BCOS
(Paragraph 2.2.1.1)

Turn-On/Turn-Off

Application or removal of power

Hipot (input to chassis and output)

2.1 kV/dc, 60 sec

*Input voltage selection, 11SV or 23DV, is made by specifying the appropriate AC Input Box, DEC Model BCDS.
All specifications are with respect to the BCDS input.

14-6

Table 14-2
Power Supply Output Specifications
Parameter

Specification
+15V

Load Range
Static
Dynamic

0-lA
0-lA

Max. Bypass Capacitance in load for 30 ms turn-on

SOOmF

Overvoltage protection

None

Current limit at 25°C

1.3A to 1.7A (-6.2 mArC)

Backup Fuse

lSA (also used for +SV)

Adjustment

±S% min.

Regulation (All causes including line, load,
ripple, noise, drift, ambient temperature)

±S%

+5V
Load Range
Static
Dynamic #1
Dynamic #2

0-lSA
±SA (within 0-17 A load range)
No load - full load

Max. Bypass Capacitance in load for 30-ms
turn-on

2000 JJ.F

Overvoltage Crowbar (blows fuse)

S.7-6.8V actuate (7V abs. max. output)

Current Limit at 25°C

24-29.4A (-0.1 ArC)

Backup Fuse (series with raw dc)

ISA

Adjustment Range

±S% min.

Regulation
Line
Static Load
Dynamic Load #1
Dynamic Load #2
Ripple and Noise
1000 Hour Drift
Temperature (0-60°)

±0.5%
3%
±2%
±1O%
4% peak-to-peak
±O.2S%
±1%

14-7

Table 14-2 (Cont)
Power Supply Output Specifications
Parameter

Specification
-15V

Load Range
Static
Dynamic #1
Dynamic #2

0-7A
!:II = SA (O.5A/J1s)
No load - full load (O.SA/J1s)

Max. Bypass Capacitance in load for 30-ms
turn-on
Overvoltage Crowbar (blows fuse)

17.4-20.SV (22V abs. max. output)

Current Limit at 2SoC

10-13.3A (-0.03AtC)

Backup Fuse (series with raw dc)

Adjustment Range

±S% min.

Regulation
Line and Static Load
Dynamic Load #1
Dynamic Load #2
Ripple and Noise
1000 Hour Drift
Temperature (0-60°C)

±1%
±2.5%
±3%
3% peak-to-peak
±0.2S%
±1%
BUS DC LO L and BUS AC LO L

Static Performance at Full Load
(for 230V connection, double below voltages)
BUS DC LO L goes to high

74-80 Vac line voltage

BUS AC LO L goes to high

8-11 V higher

BUS AC LO L drops to low

80-86 Vac line voltage

BUS DC LO L drops to low

7-10V lower

Hysteresis (contained in above specifications)

3-4 Vac

Output voltages still good

70 Vac line voltage

14-8

Table 14-2 (Cont)
Power Supply Output Specifications
Parameter

Specification
BUS DC LO L and BUS AC LO L (Cont)
Dynamic Performance

Worst case on power-up is high line,
full load.

~r-------------------------------POWER

,
,

________________________ SLOWEST OUTPUT

~
I
~

COMES UP

I-- 30ms-+i
MA X

1"'1-------------------

L2ms"':

r- MI N

BUS DC LO L

,...---_____________ B US A C LO L

NOMINAL

Worst case on power-down is low line,
full load.

11- 1094

~~---------,,
:-1--------..
2~,~s---,

_____________________ POWER DOWN

...:

FASTEST OUTPUT

GOES DOWN

: 5ms I

MIN

BUS AC LO L

!-,- - - - - - - - - - - - - - - - - - . : . . . . . . - - - - -

I 5msJ_

~MINr

1ms M I N :
BUS DC LO L
11- 1099

Output Characteristics

Open Collector

50 rnA sinking capability
+OAV max. offset

Pull-Up Voltage on Unibus

5V nominal, 180S1 impedance

Rise and Fall Times

1 J,1S max.
Outputs shall remain in 0 state
subsequent to power failure until power
is restored despite Unibus pulling
voltages remaining.

14-9

Table 14-3
Mechanical and Environmental Specifications
Specification

Parameter
Weight
DC Regulator

71b approx.

Power Chassis Assembly including AC
Regulator Module

18 Ib approx.

Dimensions

16.50 in. length
5.19 in. width
3.25 in. height

Cooling Means

IntegralS in. fan

Minimum Cooling RequiremellLs

375 CFM through heat sink
250 CFM over caps, chokes, and transformer

Rated Heat Sink Temperature
Shock, Non-Operating

40G (duration 30 ms) 1/2 sine in each of
six orientations

Vibration, Non-Operating

1.89G RMS average, 8G peak; varying from
10 to 50 Hz, 8 dB/octave roll-off 50-200 Hz;
each of six directions

Ambient Temperature

o to +60°C operating
-40 to +71 °c storage

Relative Humidity

95% max. (without condensation)

Altitude

10K ft

Output parameters are specified at the pins of the 9-pin Mate-N-Lok connector (Figure 14-5) which plugs into the
output connector on the 5409728 module. All output voltages are given with respect to the common ground pin on
this connector. IR drops in the distribution wiring are minimized to achieve good regulation at the load.
Pin 1 BUS AC LO L
Pin 2 Common
Pin 3 +5V output
Pin 4 LTCL (Clock Signal)
Pin 5 + 15V output
Pin 6 BUS DC LO L
Pin 7 Not used
Pin 8 Not used
Pin 9 -I5V output

NOTES:

The circuit connected to pins 7 and 8 is not used in the PDP-II.

Pin 2 is not connected to chassis within the power supply. Chassis ground is made at the
backplane.
Figure 14-5 Output Connector, 5409728 Regulator Module

14-10

CHAPTER 15
POWER SUPPLY DETAILED DESCRIPTION
15.1 INTRODUCTION

The power supply is divided into two sections: the ac input circuit and the dc regulator module. A detailed
description to the circuit level is provided for each section. The ac input circuit description discusses the power
supply interconnections, power control, power switch, transformer, power control circuit breaker, and the power
supply thermostat. The dc regulator module operation description discusses the generation at the circuit level of
each of the five power supply outputs.
15.2 AC INPUT CIRCUIT

A detailed ac interconnection diagram is shown in Figure 15-1. Figures 15-2 and 15-3 give this information in
schematic form.
The line cord: single pole breaker, RFI capacitors, and connections for transformer 115V or 230V wiring are
contained in the power control unit. To select 115V input or 230V input, use the BC05H or BC051 power control
unit, respectively.
A 3-section managed keyswitch is employed and mounted on the console. One section interrupts the power to the
transformer primary. A second section is wired to two 3-pin Mate-N-Loks; if the PDP-II cabinet power control bus
is plugged into one of these connectors, the keyswitch will turn on the Whole cabinet as well as the computer. The
other three-pin Mate-N-Lok is provided for daisy-chaining in the cabinet power control system. The third section of
the keyswitch is for Panel Lock and is described in Chapter 4.
The transformer is rated for 47-63 Hz and is equipped with two windings that are connected by the power control in
parallel for 115V operation and in series for 230V. The fans are connected across half of the primary so that they
are always provided with 115V nominal. There is an electrostatic shield between primary and secondary of the
transformer.
The power control circuit breaker contains a single-pole thermal circuit breaker that protects against input overload
and is reset by pressing a button on the rear of the computer.
The thermostat is mounted on the power supply heat sink. If the heat sink temperature rises to about lOO°C, the
thermostat will open one side of the primary circuit and de-energize the power supply. It will automatically reset at
about 64°C.
15.3 DC REGULATOR MODULE OPERATION

The discussion of the DC Regulator Module circuits in this manual is directed to the module deSignated
5409728-0-0, rather than the earlier module deSignated 5409728-YA-O. A block diagram of this module is shown in
Figure 15-4. The center tapped output of the power transformer is applied to positive and negative rectifier and
filter circuits. The rectifier circuits produce +28V and -28V nominal raw dc voltages which are unregulated but well
filtered by the input storage capacitors.

15-1

r--

t--2
BACK 13
PANEL TO
J5
CABINET
POWER
,...CONTROL
0- I - -

n
L.J

J4LJ
3

-J6

'--'

COMPUTER {
FAN

Jl0[

G-

OJII

v-----

N
(
1

2
INPUT

L.---

~
5
6

r--

.--

Ip3
2

I
0

---

'-'

'-P4

4---

I
2
3
4
5

'----..

I
'-'I

1
~

Ir-

.--

l....-

REGULATOR
MODULE
5409728

12-10601

r--

THERMAL
CUTOUT

I-PI

r--,
T

INPUT
8C05HXX (115V)

H400B

C LO L
ROUND
5V
TC L
15V
C LO L
NOT USED
15V

r--,

2
3
4
5
6

r--

I
2
3
4
5
6
7
8
9

J2
- - - -..

H400A

L..J

)

Jr l
'-- f-I-

.--

l
nl
L..J

I JI 2

PWR
SUPPLY
FAN

ON /OFF
WITCH

INPUT

I
2
3
4
5
6

BC05JXX(230V)
11-1045

Figure 15-1 Detailed AC Interconnection Diagram

KEYSWITCH
REMOTE TURN-ON

KEYSWITCHo{'o
PANEL LOCK I
I
I

I
KEYSWITCH :
oorA
ON-OFF
C
N.C.
7A
o-----{ T }-~---.....- - - - . - - - - ,
BREAKER

MOUNTED ON
HEAT SINK

POWER
SUPPLY
FAN

RFI
CAP.

54-09728

DC REGULATOR
MODULE

115V
LINE
PLUG

RFI
CAP.
COMPUTER
FAN

11 -1136

Figure 15·2 115V Connections - Simplified Schematic Diagram

00----4I----.ro-------{
KEYSWITCH
AC ON-OFF

T N.C.

BREAKER

RFJ
CAP.

230V
LINE
PLUG

I
I

DC
REGULATOR
MODULE

RFJ
CAP.

I
I
.,J.
tt-1137

Figure 15·3 230V Connection Diagram

15·3

POSITIVE RECTIFIER
FILTER AND FUSE

(+)RAW
DC

• +15V OUTPUT

VOLTAGE
DETECTION

OVER CURRENT
DETECTION

VOLTAGE
DETECTION

•

J:,..

CENTER TAPPED
AC FROM
TRANSFORMER
SECONDARY

POSITIVE
AUXILLIARY
AC/DC LO
RECTIFIER

• +15V OUTPUT

OPEN COLLECTOR
CURRENT SINK

DC LO L

OPEN COLLECTOR
CURRENT SINK

AC LO L

TIMING
AND FILTER
CAPACITOR

RESISTOR-ZENER
CLIPPER

NEGATIVE
RECTIFIER,FILTER
AND FUSE

•

~--------------------------------.. LTC L

(-) RAW DC

• -15V OUTPUT

(\-1046

Figure 15-4 Regulator Module Block Diagram

The +28V dc is used by an efficient switching regulator circuit to produce the +5V dc output. Provisions for
overcurrent detection are incorporated in the regulator circuit so that excess current is limited when there is a
malfunction in the load. The +5V output is also protected against overvoltage by a crowbar circuit which limits the
output to under 7V; before the output gets to this value the crowbar circuit blows the fuse in the output circuit of
the rectifier.
The - 28V dc is used by the -15V circuit, which is similar in operation to the +5V regulator circuit. The -15V
crowbar circuit limits the output to 22V.
The LTC L Real-Time Clock synchronizing signal is generated by a simple Zener clipper that is fed from the
transformer secondary.
The BUS AC LO L and BUS DC LO L signals are used to warn the Unibus of imminent power failure. Circuits on the
regulator module detect the transformer secondary voltage and generate two timed TTL-compatible open-collector
signals that are used for power fail functions by devices on the Unibus.
15.3.1 Generation of ±Raw OC
As stated in the previous paragraph, the centertapped transformer secondary voltage is rectified and filtered prior to
being fed to the three dc regulators.
The circuitry involved is shown in Figure 15-5. The bridge rectifier Dl4 is mounted on the heat sink and the input
capacitors Cl and C2 are mounted on the bottom of the regulator module. These capacitors filter the input dc and
are large enough to provide at least 25-ms storage when the input power is shut off or fails.

R45
4.7K
1/2W

NSS-351
2BVAC
47-63Hz
FROM
TRANSFORMER
SECONDARY

~_---<...---o

lP----_

TO+ 5V
REGULATOR CIRCUIT

R44.7K
1/2W

TO AC LO
AND DC LO
CIRCUITS

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....--<":II

p _ _-_TO-15V REGULATOR
CIRCUIT
11-1177

Figure 15-5 Rectifier and LTC L Circuits

A fuse is used on each output to protect the regulator and load during faults. The fuses will not normally blow when
a regulator output is shorted because the three outputs are electronically overcurrent protected. However, the
appropriate fuse will blow in case of +5V or -15V overvoltage crowbar or in case of failure in one of the overcurrent
circuits.

15-5

The resistor across each fuse provides a slow (100 - 150 seconds) discharge of C1 or C2 after the power is turned off
in case a fuse blows. The capacitors are placed ahead of the fuse to limit the energy in any fault and thus better
protect the outputs.
15.3.2 LTC L Circuit
The LTC L Real-Time Clock synchronizing Signal (Figure 15-3) is generated by a Zener clipper circuit. The output
waveform is a square (clipped sine) wave at line frequency. For one polarity of output sine wave, D13 clips at about
+3.9V and in the other polarity Dl3 clips at its forward voltage of -O.7V.
15.3.3 BUS AC LO L and BUS DC LO L Circuits
The circuitry shown in Figure 15-6 is employed to generate the timed Unibus power status signals specified in Table
14-2. These are used for power fail functions. The transformer secondary voltage is rectified by Dl and D2 and
ftltered by C9 and Rl, R14.

01
IN4004
28VAC,47-63Hz FROM
TRANSFORMER SECONDARY

{

Rt
lK
t%

20/,-F
5%

--~--~~~--~----~----~----~~
02
IN4004

Rt4
tK
1%

~JK

f----'J:..:2=<:5 +15V.1A OUTPUT
08
1N753A
+ C16
47,..1
6.2V
R37
20V
R36
464
1%

CI8

R38
10K

680 P

\\-0968

Figure 15-7 + 15V Regulator Circuit

R35 acts as the +15V voltage adjustment potentiometer. C18 is a high frequency stabilization capacitor. Q2 is the
overload detector; when the output current reaches 1.5A nominal, the voltage across R33 is sufficient to cause Q2 to
conduct. This removes base drive from Q1 and causes the regulator to current limit.
15.3.5 +5V Regulator Circuit
The +5V regulator is similar to the + 15V regulator in that the sampled output voltage is compared to the voltage
across a reference Zener by a voltage detector transistor, which in turn controls the drivers for the main pass
transistor. The +5V regulator circuit is shown in Figure 15-8. An over-current circuit is likewise employed.

15-7

R41
0.025
LI
7W,3%
tOO/LH
J2-3 +5V,15A
r---~~~~~--~~r(~r---~A~------~2UO~A~~~r---~r---~~B~ OUTPUT
R40
5.1
OtO,20A
FAST
R39
RECOVERY
5.1
011

lN5624
02
IN752A,
5.6V
R52

R54

0.1

5W
all

C32AX135
R49
147

R47
6BK

R53
100

C5
6.B.uF
35V
CW

tOV,10%

C17
6.B.uF
35V

R50

~-----*----~--~100

R16
330

R51
100

R44
330

3% P.T.C.

11- 1[75

Figure 15-8 +5V Regulator Circuit

The viewing chain consists of R49, 50, 51 and the reference Zener is D9, which is fed by R44. QlO is the detector
amplifier. The pass transistor Q6 and first stage driver Q7 are mounted on the heat sink. The predriver Q8 is turned
on by R46. The current is diverted from the base of Q8 by off-driver Q9, which is controlled by QlO. The +l5Vand
+5V regulators are similar in operation; i.e., a tendency for the output voltage to rise results in more conduction
through QlO and resultant limiting of conduction through Q6.
Here the similarity ends. The +5V circuit is a regulator that operates in the SWitching mode for increased efficiency.
To get the regulator to switch, positive feedback is applied to the voltage detector input via R47. Thus the whole
regulator acts as a power Schmitt trigger and is either completely turned on or turned off, depending on whether the
output voltage is too high or too low. When Q6 is on, it supplies current through filter choke L1 to the output
smoothing capacitor C7 and the load. When Q6 is off, the L1 current decays through commutating diode DI0,
which becomes forward biased by the back emf of Ll. The waveform across DI0 is a 30V nominal rectangular pulse
train. The filtered output across C7 is thus +5 Vdc with about a 200-mV peak-ta-peak lO-kHz nominal sawtooth of
super-imposed ripple. At the crest of the ripple, Q6 turns off and at the valley Q6 turns on. This switching mode of
operation limits the diSSipation in the circuit to the saturated forward losses of Q6 and DI0 and the switching losses
of Q6. The resultant high efficiency allows the heat sink to be small and the number 8 power semiconductors to be
few.
R50 is the voltage adjustment potentiometer. R51 is a positive temperature coefficient wire-wound resistor that
compensates for the fact that the QI0 base-emitter junction and the reference diode D9 both have negative voltage
temperature coefficients. Q5 current, limited by R39, 40, detects the overcurrent signal generated across resistor
R41, which is in series with the Q6 collector.

15-8

Output fault current is limited to a safe value because conduction of Q5 makes the reference voltage across D9
decrease to zero. This causes QI0 to conduct and shuts down the regulator. C5 is an averaging capacitor, which is
necessary in the circuit because the current through R41 is pulsating.
High frequency bypass capacitors are used on input and output of the regulator, C3 and C6, respectively. C4 is used
to slow down the turn-on of Q6 to allow DIO to recover from the on state without a large reverse current spike.

10 the event a malfunction causes the output voltage to increase beyond about 6.8V nominal, Zener diode D2 will
conduct and fire silicon-controlled rectifier Qll. This will crowbar the output voltage to a low value through Dll
and will blow fuse Fl in the rectifier circuit through R52.
15.3.6 -15V Regulator Circuit
The -15V regulator circuit is shown in Figure 15-9. It is essentially the complement of the +5V regulator circuit and
differs only in minor detail.

-28V
FROM
RECTIF IER

C10
1",F

R28
4.7K

R29
lK

1/2W

C19
2.21lF
35V
R58
330

"~~V

•

C15
O.OIIlF

1/2W

C14
3000ilF
25V

C13
lJlF
R25
383
1%

R57
10K

R31
100

R26
100

R24
68K

1N753A

Cll

J22:/ GROUND
OUTPUT

R27
464
1%

05, 20A
FAST
RECOVERY

~~~~5

MAC~~~!

o.033~F

~'
2
R30
10

100V

C12
2.21lF
35V

R22
0.2
5W

-:" 07, 18V
lN5248B

XA05

021

~05

R21
10
R20
10
R19
0.06
5W

R23
100

06
I N5824

045H8

L2
~

022
2N5302

200~H

J2-9J' -15V,7A
OUTPUT

~1-0970

Figure 15-9 -15V Regulator Circuit

The crowbar device is a Triac Q27 instead of an SCR. No temperature compensating resistor is required because Q26
and D4 track each other, as in the +15V regulator (Paragraph 15.3.4). The detailed interconnection of the drivers
and the circuit values are different. The -15V output voltage is adjusted by potentiometer R26.

15-9

CHAPTER 16
POWER SUPPLY MAINTENANCE
16.1 INTRODUCTION
Information is provided in this chapter to maintain the power supply. This consists of adjustments, circuit
waveforms, troubleshooting, and parts identification. The adjustments consist of three output potentiometers. The
circuit waveforms provide a guide to proper operation at various places in the circuit. The troubleshooting section
provides rules, hints, and a troubleshooting chart as a maintenance aid in isolating power supply malfunctions.
Finally, the parts identification section provides a directive to obtaining parts information for the entire power
supply unit through a parts location directory to the mechanical engineering drawings in the Engineering Drawing

Manual.
16.2 ADJUSTMENTS
Three adjustments to the power supply adjust the three dc output voltages: +15V, +5V, and -15V. A small
screwdriver is all that is required. Clockwise adjustment of any of the potentiometers increases voltage, and the
potentiometers are located on the top side of the de regulator module. The potentiometer designations are:
a.
b.
c.

R35 - +15V
R50- +5V
R26 - -15V

In performing any of these adjustments note the following:

CAUTION
Do not adjust voltages beyond their 105 percent rating

and adjust slowly in order to avoid overvoltage crowbar,
which will blow de output fuses.
2.

Do use a calibrated voltmeter; preferably a digital
voltmeter. Voltages should be adjusted to their center
values: +15.0, +5.0, and -15.0, ail under load at the de
cable termination on the system unit.

16.3 CIRCUIT WAVEFORMS
The two basic regulator circuits used on the dc regulator module generate +5V and -15V. Figure 16-1 shows six
waveforms of the +5V regulator circuit taken at two points (A and B) in the circuit (Figure 14-6). Waveforms a, b,
and c are taken at point A, which is the +5V circuit, Q6 transistor output. Waveforms d, e, and f are taken at point
B, which is +5V power supply output (12-3). Figure 16-1 also indicates the load conditions and time scales for each
waveform. Figure 16-2 shows six waveforms of the -15V regulator circuit taken at two points (C and D) in the
circuit (Figure 14-7). Waveforms a, b, and c are taken at point C, which is the -15V power supply output (12-9). The
load conditions and time scales of the respective waveforms are indicated in Figure 16-2. These waveforms were
taken on a Tektronix Model 453 Oscilloscope. All waveforms are with respect to 12-2, power common.
16-1

a) Point A, No load,
2 ms /div, and
10V/div.

d) Point B, No load,
2 ms/div, and
50 mV/div.

b) Point A, No load,
20 Jls/div, and
10V/div.

e) Point B, No load,
20 Jls/div, and
50 mV/div.

c) Point A, 20A load,
20 Jls/div, and
10V/div.

f) Point B, 20A load,

Jls/div, and
50 mV/div.

Figure 16-1 +5V Regulator Circuit Waveforms

\6-2

a) Point C, No load,
5 ms/div, and
10V/div.

d) Point 0, No load,
5 ms/div, and
50 mV/div.

b) Point C, No load,
50 I1S/div, and
10V/div.

e) Point 0, No load,
50 I1S/div, and
50 mV/div.

c) Point C, 5A load,
50 I1S/div, and
10V/div.

f) Point 0, 5A load,

50 I1S/div, and
50 mV/div.

Figure 16-2 -15V Regulator Circuit Waveforms

16-3

16.4 TROUBLESHOOTING
Troubleshooting information for the power supply consists of troubleshooting rules, hints, and a troubleshooting
chart. This information provides a maintenance aid to isolating power supply malfunctions (drawing
D-CS-S409728-0-1 ).
16.4.1 Troubleshooting Rules
Troubleshooting rules for the power supply are as follows:
a.

Make certain that power is turned off and unplugged before servicing the power supply.

Ensure that input capacitors Cl and C2 are discharged before servicing the power supply. A 10 to lOOn,
lOW resistor can be used to hasten the discharge of the capacitors. (Be sure power is off.)

The dc regulator module is not internally grounded to the chassis; therefore, shorts to ground can be
located after disconnecting the dc output cable to the system unit.

The dc output fuses F I and F2 can be replaced without removing the dc regulator module. Before
unsoldering fuses, observe cautions described in Steps a and b.

For proper operation, all hardware must be secured tightly to about 12 inch-pounds (i.e., capacitors,
chokes, semiconductors). All hardware should be replaced with identical hardware replacement parts.

The dc.regulator module may be removed from the top of the power chassis assembly while the latter is
still bolted to the computer chassis. The dc regulator module is held in place by six screws.

When replacing power semiconductor components that are secured to the heat sink, apply a thin coat of
Wakefield #128 compound or Dow Silicon Grease to the heat sink contact side (bottom) of the
semiconductor. Insulating wafers are not required.

16.4.2 Troubleshooting Hints
CAUTION
Unplug computer before servicing.

The most likely source of power supply malfunction is the dc regulator module. A quick remedy for a malfunction
may be to replace this entire module. The problem, however, could be a short in the system unit or possibly a
defective component or other problem in the ac input circuit.
The +SV and -ISV regulators contain overvoltage detection circuitry. If RSO or R26 are adjusted too far clockwise,
the corresponding crowbar circuit will trip and blow fuses. To correct this condition: adjust the potentiometer fully
counterclockwise, replace the blown fuse, and re-adjust per Paragraph 16.2.
Make a visual examination of the circuitry. Check for burnt resistors, cracked transistors, burnt printed circuit board
etch, oil leaking from capacitors, and loose connections. A visual check can be a quick method of locating the cause
of a malfunction.
16.4.3 Troubleshooting Chart
In checking the various areas of the power supply, the rules listed in Paragraph 16.4.1 should be followed. The
waveforms referenced in Paragraph 16.3 provide a comparison for the troubleshooting readings. Table 16-1 provides
the dc regulator troubleshooting chart.

16-4

Table 16-1
Troubleshooting Chart
Cause

Problem

No +5V and + 15V output

Flopened*
D14 or transformer opened*
+5V adjusted too high*

+5V Output Too Low

Q5, D9, QI0, Q9, Qll, 012, or DIO
Shorted C5 or C7 shorted
R49, R50, R46, or R44 opened
Q6, Q7, Q8, or 011 shorted
A9, QI0, or D9 opened*
R51, or R50 opened

+15V Output Too High

Ql shorted
E8 opened
R35 or R36 opened

No -15V Output

F2 opened
D14 or transformer opened

-15V Output Too Low

-15V adjusted too high*
Q25, D4, Q26, Q21, Q27, D7 or D5 shorted
C14 or C12 shorted
R22, R26, R25, or R29 opened
Q22, Q23, Q24, or D6 shorted
Q25, Q26, or D4 opened

BUS AC LO L Will Not Go High

Q13, Q14, or Q15 shorted
Q16 or D3 opened
R7, R3, R6, or R8 opened
C9 shorted

BUS AC LO L Will Not Go Low
and/or acts erratically on
power-on/power-off

Q13, Q14, or Q16 opened
Q15 or D3 shorted
R12, R13, R7, or RIO opened

BUS DC LO L Will Not Go High

Q19, Q20, or Q18 shorted
Q 17 or D3 opened
R7, R2, or R6 opened
C9 shorted

BUS DC LO L Will Not Go Low

Q19, Q20, of Q17 opened
Q 17 or D3 opened
R7, R3, or R6 opened
C9 shorted

"'These causes make the crowbar rue, which in turn, blows the appropriate fuse.

16-5

Table 16-1 (Cont)
Troubleshooting Chart
Problem

Cause

BUS DC LO L Will Not Go Low
and/or acts erratically on
power-on/power-off

Q19, Q20, or Q17 opened

No LTC L Signal

R55 opened
D13 shorted

LTC L Going Too High

D13 opened

Q 18 or D3 shorted
R9, RIO, Rll, or R8 opened

16.5 PARTS IDENTIFICATION
Parts identification for the power supply is provided in the Engineering Drawing Manual. This includes the assembly
drawings with associated parts lists, which list the respective unit parts, their part designation, and their OEC part
numbers. These drawings and the respective drawing numbers are as follows:
a.

Power Supply Chassis: E-IA·5309816·0-0

Power Control Board 115V: C·IA-S409824-0-0
230V: C-IA-S40982S-0-0

OC Regulator Module: E-IA-S409728-0-0
0-CS-S409728-0-1 (schematic)

Power Supply Assembly and Fan: 0-AO-7003731-0-0

AC Input Box Assembly: 0-UA-H400-0-0

Line Set 115 Vac 7A: C-UA-BCOSH-O-O
230 Vac SA: C-UA-BCOSJ-O-O

16-6

APPENDIX A
INTEGRATED CIRCUIT DESCRIPTIONS

A.I INTRODUCTION
The MSI and LSI integrated circuits (ICs) which are shown in the engineering drawings are discussed in the following
paragraphs. The descriptions include a pin location diagram, simplified logic diagram, and truth table. These
descriptions are intended as maintenance aids for troubleshooting to the IC level. Table A-I lists the ICs by part
number, name, and respective paragraph number.

Table A-I
Integrated Circuits
Manufacturer
Part Number

Name

DEC
Part Number

Para.

8266

19-09934

2-Input, 4-Bit Digital
Multiplexer

A.2

7413

19-09989

Dual NAND Schmitt Triggers

A.3

7473

19-05587

Dual 1-K Master-Slave
Flip-Flops

A.4

7474

19-05547

Dual D-Type, Edge-Triggered
Flip-Flops

A.5

7475

19-09050

4-Bit Bistable Latch

A.6

7489

19-10396

64-Bit Read/Write Memory

A.7

74121

19-10230

Monostable Multivibrator

A.8

74150

19-10153

Data Selector Multiplexer

A.9

74153

19-09927

DuaI4-Line-to-l-Line Data
Selectors/Multiplexers

A.lO

74154

19-09701

4-Line-to-16-Line Decoders/
Demultiplexers

A.ll

A-I

Table A-I (Cont)
Integrated Circuits
Manufacturer
Part Number

DEC
Part Number

Name

Para

74157/74S158

19-10655/
19-10656

Quadruple 2-Line-to-l-Line
Multiplexer

A.12

74174/74175

19-10652/
19-10651

D-Type Flip-Flops, Hex/Quad
with Clear

A.13

74181

19-09982

Arithmetic Logic Unit/Function
Generator (ALU)

A.14

74182

19-10019

Look-Ahead Carry Generator

A.l5

74193

19-10018

Synchronous 4-Bit Up/Down
Counter (Dual Clock with Clear)

A.16

74194

19-10623

4-Bit Bidirectional Universal
Shift Registers

A.l7

7528

19-10687

Dual Sense Amplifiers with
Preamplifier Test Points

A.18

9602

19-09374

Dual Retriggerable Monostable
Multivibrator with Clear

A.19

A-2

A.2 8266 2-INPUT, 4-BIT DIGITAL MULTIPLEXER
Truth Table
Output

Select Lines

tn (0,1 ,2,3)

o
o

o
1

INPUTS

OUTPUTS

SELECT
INPUT

~,-A----..

INPUTS

OUTPUTS

INPUTS

~ SELECT GND
INPUTS

INPUT

11-1109

r---------S 0 0---"----1

SlO--~------------~

L _________ _
fO
11-0632

A-3

A.3 7413 DUAL NAND SCHMITI TRIGGERS

GND

POSITIVE LOGIC: Y= ABCD
11-1114

A-4

A.4 7473 DUAL J-K MASTER-SLAVE FliP-FLOPS

GNO

0000808
I
I
I
I

~l
Q
r-

I
t
f--

.,..

UP
COUNT

OAT
INPUT ~~

CARRY
OUTPUT

PRESET
-0

QAt

::D

-0

-I-

DOWN
COUNT

BORROW
OUTPUT

----I

[

DATA a
INPUT A

-0

OUTPUT Q
A

-<::T

QA l l

~
rPR&v

-OOUTPU

-<::T
QSt-1

~
DATA
INP UT C

~~J

DATA
INPUT 0

CLEAR

~
QCh

J]
---,

L[j

~
QD

..1

~-l

...L
LOAD

-L
A-22

-oOU TPUT QC

--OT

-<::T

-0

OUTPUT QD

a~n

b!j

-0641

A.17 74194 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS

CLEAR SHIFT

ABC

INPUT

INPUTS

CLOCK

SHIFT

GND

S~~11t '----PA-R~A~LL-E-L---' S~~~rL
INPUT

" -1121

A-23

A.18 7528 DUAL SENSE AMPLIFIERS WITH PREAMPLIFIER TEST POINTS

TRUTH TABLE
INPUTS
A
S

DEFINITION OF LOGIC LEVEL

OUTPUT

INPUT

At
S

VIO>VT MAX VIOVIH MIN VIa::

>a::

:::;:

>a::

:::;:

ia::
:::;:

ia::

!i0..

...J
a::

a::

:::;:
III

u
et
rn

I--

::;:

>a::

:::;:
W

:::;:

;£

0..

;£

~
N,LOK
CCNNr:CfOl=!

6712-13

Figure 3-7 BCOST Line Set, Cover Removed

P.CUNE
C';)HD

CIRCUIT aREAl(Ei'i
RE!}ET BUrrC.- .2-

L.. _ _ _

AC LO

I---

LTC

•8 •8
•9 •9

+5V(l)

PS:3
(5409498)

T:3

r - - - -,
COMPUTER
I
BACK PLANE

J2L

•5

POWER
SUPPLY
FAN

'-- I -

[

~
I

+15V

I
2:30V LI NE SET
5A

JIL

GND (l)

J:3

THERMOSTAT

POWER DISTRI RUT ION
BOARD

H2-PI

HI-JI

PSI
(5409728)

DC LO

} ACINPUT

WWll
t!J[!][I

mmr:
~

TO RACK MOUNTE D
POWER CONTROLLER

SIGNAL

..f!.!!

CONN

AC LO
DC LO
LTC
+15V
-15V
+5V(1)
+5V(2)
GND( 1)
GND(2)

2
I
7

JI- J5
JI- J5
JI- J5

8
:3
9
9
4
4

JI-J5
JI- J5
JI SJ2
J:3- J5
JI-J5
JI- J5

JI-J5

NOTES:
1. HI indica'.. power supply horne •• (E-IA-7009207-0-0)

H2-

2. H2 indicates power distribution board
harn •• s (E-IA-7009208-0-0)

H2 -P7 0
TO CONSOLE
SWITCH

2
LOGIC
FAN

:3
L..-

11-2021

Figure 3-10 Power System Interconnection Diagram

3-13

~5v~e -;;
lOA

I
115V {
47-63Hz
Power

Phase .-..
Ground
Neutral

**
I

I
I

""---

L -

~
3

8
Note:
For simplicity. intermediate connections involving TBI and Kl are not shown.

2
11-1890

Figure 3-11 Power Application Using 115 V Line Set

I
I
230V {
47-63Hz
Power

-::e -;; --,
r-

Ground

Neutral

I
I

•5
I

-J5

L __

230V

Phase ~

8
Note:
For simplicity. intermediate connections involving TBI and Klare not shown.

2
II - 1891

Figure 3-12 Power Application Using 230 V Line Set

3-15

GNO(2)

+5V(2)

-15V

+ 5V(2)

L
L5

LTC

L~ L~ L~
2

+15V

GNO( 1)

OCLO

ACLO

+ 5V(1)
GNO (2)

L-

,....,
~
2
3
~

4
~

8
~

'--'

11 -1889

Figure 3-13 Power Distribution Board Circuit Schematic

Table 3-1
Power Distribution Board Signals
Source
H744
5 V Regulator

Signal
{ +5 V (2)
GND (2)
r

5409728
dc Regulator

Notes:

DCLO
ACLO
LTC
+5 V (1)
+15 V
-15 V
"GND (1)

Destination
13, J4, and J5 pin 9
11-J5 pin 4**
11-J5 pin 1*
11-J5 pin 2
11-J5 pin 7
11 and 12 pin 9
11-J5 pin 8
11-J5pin3
11-J5 pin 4**

*Connected to each Mate-N-Lok via a jumper.
**Electrically connected on the board. Pins 5 and 6 on 11-J5 are spares.

CAUTION
Output +5 V (1) is generated by the 5409728 regulator and is
available on connectors 11 and 12. Output +5 V (2) is
generated by the H744 Regulator and is available on
connectors 13-J5. These supplies are separate and should not
be connected together.
3-16

The current ratings for the power supply outputs are shown below. The ratings listed are maximum; that is, for a
particular output, the sum of the loads on the connectors used must not exceed the specified value.
5409728 dc regulator
+5 V (1) on connectors Jl and 12 is 20 A total
+15V on connectors Jl-J5 is 1 A total
-1 S V on connectors J I-J 5 is 8 A total
H744 Regulator
+5 V (2) on connectors 13, J4, and JS is 20 A total
Parallel connections of +5 V (2) and GND (2), using Faston tabs on the power distribution board, are provided to
connect these outputs to the computer console printed circuit board.
The power distribution board contains a DC LO jumper for each connector (Jl-JS). Only one DC LO connection is
required per mounting box. In the basic computer, jumper WI is installed to bring the DC LO signal to the
backplane because the processor power harness connects the backplane to the power distribution board at connector
J1.
A jumper for each connector is provided because it is possible to mount a backplane in any position and connect it
to any power distribution board connector.
The requirement for only one installed DC LO jumper per box is emphasized in the following special case.
Assume that a PDP-ll/OS mounting box is to be used as an expander box with a DBII-A Bus Repeater installed
along with other options. Unlike previous expansion boxes, the PDP-II/OS box allows the DBll-A to be installed in
any position. When connected to the appropriate distribution board connector, the associated DC LO jumper is
installed. All other DC LO jumpers must be open to prevent latching up of the DC LO circuit by looping through the
power harness if more than one jumper is installed.
Options for the basic computer include a pre-wired backplane and specific power harness to connect the backplane
to the power distribution board (Table 3-2).

Table 3-2
Option Power Harnesses
Option

Power Harness

MFII-L
DDII-B
DDlI-A

70-09206
70-09099
70-09205*

*Not shipped with computer.
Harness must be ordered
separately to install customer's
DOll-A.

3-17

• +15V OUTPUT

•

POSITIVE RECTIFIER
FUSE
FILTER AND

VOLTAGE
DETECTION

OVER CURRENT
DETECTION

VOLTAGE
DETECTION

,(+) RAW

•

CENTER TAPPED
AC FROM
TRANSFORMER
SECONDARY

POSITIVE
AUXILLIARY
AC/DC LO
RECTIFIER

• +5V OUTPUT

OPEN COLLECTOR
CURRENT SINK

DC LO L

OPEN COLLECTOR
CURRENT SINK

AC LO L

TIMING
AND FILTER
CAPACITOR

RESISTOR-ZENER
CLIPPER

NEGATIVE
RECTIFIER. FILTER
AND FUSE

•

~------------------------------~.

(-) RAW DC

LTC L

• -15V OUTPUT

(1-1046

Figure 3-14 DC Regulator Block Diagram

The DD11-A and DD11-B are pre-wired backplanes used to mount up to four small peripheral interfaces (equivalent
to four quad boards). The DDI1-B is a later version of the DD11-A that uses Faston tabs on the wire-wrap pin side
to connect with the power harness. The DDI1-A uses a power harness that contains a cable connector module which
plugs into the connector side of the backplane. The DDI1-A is not shipped with the computer; rather, the later
DD11-B version is used. If the customer has a DD11-A and wants to install it in the computer, he must order power
harness 70-09205.
The KDll-B Processor requires 8.0 A at +5 V and 1 A at -15 V. The power requirements for the MFll-LMemory
are listed below.
MFll-L
Capacity

Current
at +5 V

8K
16K
24K

3.4 A
4.9 A
6.4 A

Current
at -15 V
6.0 A
6.5A
7.0A

3.4.4 DC Regulator (PSI)
3.4.4.1 Functional Operation - A block diagram of the dc regulator is shown in Figure 3-14. The center tapped
output of the power transformer is applied to positive and negative rectifier and filter circuits. The rectifier circuits
produce +39 V and -29 V nominal raw dc voltages, which are unregulated but well filtered by the input storage
capacitors.
The +39 V is used by an efficient switching regulator circuit to produce the +5 V output. Provisions for overcurrent
detection are incorporated in the regulator circuit so that excess current is limited when there is a malfunction in the
load. The +5 V output is also protected against overvoltage by a crowbar circuit which limits the output to an
absolute maximum of 7 V; at approximately 6 V, the crowbar circuit blows fuse Fl in the output circuit of the
rectifier.
The + 15 V output is produced by a series regulator circuit. It has no overvoltage protection circuit. Fuse F1 is used
for protection in case of a malfunction in the + 15 V regulator.
The - 39 V is used by the -15 V circuit, which is similar in operation to the +5 V regulator circuit. The -15 V
crowbar circuit limits the output to an absolute maximum of -22 V. At approximately -19 V, the crowbar circuit
blows fuse F2 in the output circuit of the rectifier.
The real-time clock synchronizing signal (LTC L) is generated by a simple Zener clipper that is fed from the
transformer secondary.
The BUS AC LO L and BUS DC LO L Signals are used to warn the Unibus of imminent power failure. Circuits detect
the transformer secondary voltage and generate two timed TTL-compatible open-collector signals that are used for
power fail functions by devices on the Unibus.
3.4.4.2 Generation of Raw DC Voltages - As stated in the previous paragraph, the centertapped transformer
secondary voltage is rectified and filtered prior to being fed to the three dc regulators.
The circuitry is shown in Figure 3-1S. Bridge rectifier Dl4 is mounted on the heat sink and input capacitors CI and
C2 are mounted on the bottom of the regulator module. These capacitors filter the input dc and are large enough to
provide power storage for at least 25 ms when the input power is shut off or fails.

3-19

J1-3

R45
4.7K
1/2W

NSS-351

2aVAC
47-63Hz
FROM
TRANSFORMER
SECONDARY

~_-------40--_TO -15V REGULATOR

CIRCUIT

11- 1177

Figure 3-15 Rectifier and LTC Circuits

Two fuses are used to protect the regula tor and load during faults. A 15 A fuse protects both the +5 V and + 15 V
outputs and a 5 A fuse protects the -15 V output. Normally, the fuses do not blow when a regulator output is
shorted because the three outputs are electrically overcurrent protected. However, the appropriate fuse does blow in
case of +5 V or -15 V overvoltage crowbar or in case of failure in one of the overcurrent circuits.
The resistor across each fuse provides a slow (100 - 150 seconds) discharge of C 1 or C2 when the power is turned
off after a fuse has blown. The capacitors are placed ahead of the fuse to limit the energy in any fault and thus
better protect the outputs.
3.4.4.3 LTC L Circuit - The LTC L real-time clock synchronizing signal (Figure 3-15) is generated by a Zener
clipper circuit. The output waveform is a clipped sine wave at line frequency. For the positive half of the output sine
wave, D13 clips at about +3.9 V and for the negative halfD13 clips at its forward voltage of-0.7 V.
3.4.4.4 BUS AC LO L and BUS DC LO L Circuits - The circuitry shown in Figure 3-16 is used to generate the
timed Unibus power status signals that are used for power fail function.
The transformer secondary voltage is rectified by Dl and D2 and filtered by C9 and Rl, R14. Circuit parameters are
chosen so that the voltage across C9 rises slower than the three regulated output voltages on powerup and decays
faster than the three regulated output voltages on powerdown.
Two differential amplifier circuits are used to detect power status: Q17, Q18 generates BUS DC LO L; and Q15,
Q16 generates BUS AC LO L. Both differential amplifiers share a common reference Zener diode D3, which is fed
approximately 1 rnA by R3.
As C9 charges subsequent to powerup, first Q17, Q18, and then Q15, Q16 change state; the reverse is true during
powerdown. When C9 starts to charge, Q 17 and Q 16 are on and Q 15 and Q 18 are not conducting. As C9 charges
further, Q18 starts to conduct into R7 and raises the voltage on the cathode of D3. This acts as positive feedback
and snaps Q17 off and Q18 on more solidly. A few milliseconds later, the voltage across C9 has risen sufficiently for
the same process to take place in differential amplifier Q15, Q16. The status of each differential amplifier is
followed by the germanium transistor open-collector output stages Q19, Q20 for BUS DC LO L, and Q13, Ql4 for
BUS AC LO L. These stages clamp the Unibus at about +0.4 V until the differential amplifier circuits sequentially
signal them across Rll and R12 that power is up. The outputs then rise to about +5 V as dictated by the Unibus
loading and pull-up termination resistors.
3-20

The sequence is as follows:
powerup ~ then BUS DC LO L = 0 ~ then BUS AC LO L = 0
0= high (+3 V)
powerdown ~ then BUS AC LO L = 1 ~ then BUS DC LO L = 1
1 = low (+0.4 V)
During a power-down sequence, after BUS AC LO L goes low, there is sufficient storage in capacitors Cl and C2 to
maintain output voltage long enough to permit the power fail circuit to operate. The open collector stages are
designed to clamp the Unibus to 0.4 V maximum, even when there is no ac input to the regulator. They are
inherently biased on by Rl1 and R12 until the differential amplifiers signal that power is OK.

Z8VAC,47-63Hz FROM{
TRANSFORMER SECONDARY

Dl
IN4004

Rl
lK
1%

DZ
IN4004

R14
1K
1%

C9
20/LF

R6
10K 1%
+ 11.4V

R2
10K 1%

BUS

---l~--'Wv--'

BUS
AC LO L
OUTPUT

J2-6 DC LO L
~----e~-< OUTPUT

J2-1

Rll
10K
1%

r----e>----,

D3
5.1V
R1Z
10K
1%

Ri3
470

R7
lK 1%
11-1176

Figure 3-16 BUS AC LO and BUS DC LO Circuits

3.4.4.5 +15 V Regulator Circuit - The + 15 V regulator shown in Figure 3-17 is a simple series regulator. The pass
transistor Ql is a high-gain power Darlington type and is mounted on the heat sink. Base drive current is supplied to
Ql via R38. Q3 limits the value of this current to the required value by shunting it away from the Ql base. Voltage
detector amplifier Q4 biases on Q3 and thus limits current in Ql. The +15 V output voltage is sampled on the
viewing chain R34, R35, R36 and compared to the voltage across reference Zener D8, which is fed by R37. If the
output tries to increase from the regulated value, the emitter of Q4 is made more negative (relatively) than its base
and conduction through Q4 increases. This increases the conduction through Q3 and causes Ql to shut down
sufficiently to restore the output voltage to the regulated value. Ambient temperature compensation of the voltage
detector is essentially flat since D8 has a +2 mVt C temperature coefficient and the base emitter junction of Q4 has
a -2 mVt C temperature coefficient.
R35 is the +15 V voltage adjustment potentiometer and C18 is a high frequency stabilization capacitor. Q2 is the
overload detector; when the output current reaches 1.5 A nominal, the voltage across R33 is sufficient to cause Q2
to conduct which removes base drive from QI and causes the regulator to current limit.

3-21

+39V FROM RECTIFIER---..--'VVv---<_----,,..;.....

r-~.___----__=_----~----<_...:J:..:2'--5"<+15V. OUTPUT
08
lN753A
6.2V
R37 IK

CI6

:i!v'

R36

464
1%

CI8
680 P

R38
10K
R56
10K

It-0968

Figure 3-17 +15 V Regulator Circuit

3.4.4.6 +5 V Regulator Circuit - The +5 V regulator is similar to the +15 V regulator in that the sampled output
voltage is compared to the voltage across a reference Zener by a voltage detector transistor, which, in turn, controls
the drivers for the main pass transistor. An overcurrent circuit is used also. The +5 V regulator circuit is shown in
Figure 3-18.

Figure 3-18 +5 V Regulator Circuit

3-22

The viewing chain consists of R49, R50, and R51. The reference Zener is D9, which is fed by R44. Q10 is the
detector amplifier. The pass transistor Q6 and first stage driver Q7 are mounted on the heat sink. The predriver Q8 is
turned on by R46. The current is diverted from the base of Q8 by off-driver Q9, which is controlled by QlO. The
+15 V and the +5 V regulators are similar in operation; i.e., a tendency for the output voltage to rise results in more
conduction through QI0 and resultant limiting of conduction through Q6.
Here the similarity ends. The +5 V regulator operates in the switching mode for increased efficiency. To get the
regulator to switch, positive feedback is applied to the voltage detector input via R47. Thus, the whole regulator acts
as a power Schmitt trigger and is either completely turned on or turned off, depending on whether the output
voltage is too high or too low. When Q6 is on, it supplies current through filter choke Ll to the output smoothing
capacitor C7 and the load. When Q6 is off, the Ll current decays through commutating diode DI0, which becomes
forward biased by the back emf of Ll. The waveform across DlO is a 30 V nominal rectangular pulse train. The
filtered output across C7 is thus +5 Vdc with about a 200 mV peak-to-peak 10 kHz nominal sawtooth of
superimposed ripple. At the crest of the ripple, Q6 turns off and at the valley Q6 turns on. This switching mode of
operation limits the diSSipation in the circuit to the saturated forward losses of Q6 and DI0 and the switching losses
of Q6. The resultant high efficiency allows the use of a small heat sink and relatively few power transistors.
R50 is the voltage adjustment potentiometer. R51 is a positive temperature coefficient wire-wound resistor that
compensates for the fact that the QI0 base-emitter junction and the reference diode D9 both have negative voltage
temperature coefficients. Q5 current, limited by R39 and R40, detects the overcurrent signal generated across
resistor R41, which is in series with the Q6 collector.
Output fault current is limited to a safe value because conduction of Q5 makes the reference voltage across D9
decrease to zero. This causes QlO to conduct and shuts down the regulator. C5 is an averaging capacitor, which is
necessary in the circuit because the current through R41 is pulsating.
High frequency bypass capacitors are used on the input and output of the regulator (C3 and C6, respectively) and C4
is used to slow down the turn-on of Q6 to allow DlO to recover from the on state without a large reverse current
spike.
If a malfunction causes the output voltage to increase beyond about 6 V, Zener diode D2 conducts and fires
silicon-controlled rectifier Q11. This crowbars the output voltage to a low value through D11 and blows fuse Fl in
the rectifier circuit through R52.

3.4.4.7 -15V Regulator Circuit-The -15V regulator circuit is shown in Figure 3-19. It is essentially the
complement of the +5 V regulator circuit and differs only in the following minor details.
a.

The crowbar device is a Triac (Q27) instead of an SCR. No temperature compensating resistor is required
because Q26 and D4 track each other, as in the +15 V regulator.

The detailed interconnection of the drivers and the circuit values are different.

The -15 V output voltage is adjusted by potentiometer R26.

3.4.5 +5 V Regulator (PS2)
3.4.5.1 Functional Operation - A functional block diagram of the +5 V regulator is shown in Figure 3-20. The
28 Vac from the secondary of transformer T2 is full wave rectified and filtered. This raw dc voltage (approximately
39 V) is used by a switching regulator circuit to produce the +5 V output. An overcurrent detection circuit is
incorporated in the regulator circuit to limit excess current when there is a fault in the load. The +5 V output is also
protected against overvoltage by a crowbar circuit that limits the voltage to +7 V. Before the output reaches +7 V,
the crowbar circuit blows the fuse in the rectifier output. A circuit schematic of the +5 V regulator is shown in
Figure 3-21 and is referenced in the subsequent paragraphs.

3-23

-39V
FROM
RECTIFIER

J2-2
R28
4.7K
1/2W

R29
IK

CI9
2.21'F
35V

~
330

XA55

04
6.2V
1N753A

GROUND
OUTPUT

0.221'F
'5

•

R26
100
II2W
CI4
3000l'F
25V

cn
1}JF
R25
383
1%

R31
100

50V

R24
68K

R57

C11
o.033)lF
100V

R27
464
1%

05.20A
FAST
RECOVERY

~~i~5

MACI~~~l! 2

R30
10

CI2
2.21lF
3~V

+"
R22
0.2
5W

07.18V
IN 52488

XA05

021

~05

R21
10

R23
100

06
I N5624

045H8

R20
10

L2
lOOI'H
lOA

RI9
0.06
5W
3%WW

022
2N5302

-""

J2-9./ -15V
OUTPUT
11

Figure 3·19 - 15 V Regulator Circuit

+5V
t-.....- - - -.....- .... OUTPUT

INPUT

1 1-' 892

Figure 3·20 +5 V Regulator (PS2) Functional Block Diagram

3·24

~0970

Fl
15A

R4
02.5W

02
2N5302

r[ilI
7

I
L_

~-,

c31
+
Cl
';::'::; 31 KJL F
50V

R13.9K
lW 10%

.05 JL F T
R5
10

I
I
I

G\) ~~SA55

Rll

~6%

'--'

R6
10K

15V

rlC4

05
NSR8117

07
MCR649P-2

Cl0-l-

+_L +1

C8/f' 6KJLF
C;T
6KJLF
10V
10V
08
0664

MPSA55

.01 JLF

C7
;::f:;:.OIJLF
20%

-'- Cl1
T2700PF

.T·05 JL F

R22
680

R21 ~
5.1~

R24
10
lW

O~f?

RIO
150

lN474~1j

I JJ~

MPSA05

+15V

R23
100

~03
lMA
5.1V

3,4./
\.

R3
12K

R25
18K

R7
18.2K
1/8W,1%
07
2N6028

V+

4
R8
1K

C6
2.2JLF ;:: f:;:

112

04
0664

-=-

R9
27
R19
7.5K
1/8W,1%

GNo

R17
750
1/8W,1%
R14
200

R6
lK

C12,*
56PF

R26
1.5K

+5V

60JLH

¥03
10
045H8

+1
C2 T
15JLF

2.5

::;::::

MPSA~~~

R12
150

R2
820
lW,10%

~-~.13

Vz
El
oEC723

VREF

COMP

V-

C5.#3
56PF

R18
511
1/8W,I%
6

R15
10K

-=-

V SENSE
------

------

---

1 '-1894

Figure 3-21 +5 V Regulator (PS2) Circuit Schematic

3.4.5.2 Generation of Raw DC Voltage - The 28 Vac from transformer T2 is applied to full wave rectifier DI via
pins 6 and 7 of connector 11. The rectifier output is approximately +39 V and is filtered by capacitor CI. Resistor
RI is a bleeder resistor and dissipates the charge on Cl during shutdown. The IS A fuse (FI) protects the regulator
and load during faults. Normally, the fuse does not blow when the regulator output is shorted because the output is
protected against overcurrent operation. The fuse does blow if the crowbar circuit fires or in case of failure in the
overcurrent protection circuit.
3.4.5.3 Regulator Circuit - The regulated +5 V is sampled by resistors Rl9 and R7. The magnitude of this voltage
is compared to a precision 5 V reference voltage produced by voltage regulator EI and voltage divider R17, R14, and
R18. This regulator responds to ±O.05 V differences between the sensed output and the reference.
EI is an integrated circuit in a 14-pin dual in-line package. A simplified equivalent circuit and package configuration
are shown in Figure 3-22.

FREQUENCY
COMPENSATION

V+

INVE~J~~~ o - - - - - - - - - - - + - - - .
V REF 0 - - - - - + - - - - - - ,

r - - - - - - o Vc

SERIES PASS
TRANSISTOR
........- - - - - 0 V OUT

L------ovz
C

VA - Voltage Reference Amplifier
B- Error Amplifier
C -Current Limiter

CURRENT CURRENT
LIMIT
SENSE

Simplified Schematic

FREQ COMP

CURR LIM
CURR SENSE

V+

INV OUTPUT

Vc
Vout

NON-INV OUTPUT

Vref

V-

Pin Designations

t 1-1895

Figure 3-22 Voltage Regulator (El) Equivalent Circuit and Package Configuration

3-26

The +5 V output passes through transistor Q2 to the output filter (C8, C9, and Ll) and to the load. Q2 is called the
pass transistor and is mounted on the heat sink. Transistor Q2 is operated in the switched mode; therefore, it is
either on or off. It is controlled by drivers Q5, Q4, and Q3 that are controlled by voltage regulator El. A simplified
+5 V regulator circuit and associated waveforms are shown in Figure 3-23 to illustrate the operation of a switching
regulator.

+39V

POWER

OFF

1
1

:
1

1
1
1

---I--r-----;

-----02 ON

1
1
1

1
1

1
1
1'-----'

02 OFF

~5~5V

+::---~
11- 0098

+5V

L1
+ 39 V - - - - - - £

~L-_ _ _ _ _~_ _ _ _ _ _~rn~_ _ _ _ _ _~~~______- .___

4.95V-5.05V
05
C9

LOAD

11-0097

Figure 3-23 Simplified 5 V Switching Regulator Schematic and Waveforms

When power is applied, the drivers tum on Q2 and the output voltage starts to rise toward +39 V. Because of
inductor Ll in the circuit, the voltage rise is relatively slow. When the output voltage reaches 5.05 V, El signals the
drivers to cut off Q2. As the field associated with Ll starts to collapse, Ll current flows through the load to ground
and returns to the other side of Ll through comrnutating diode D5, which is forward biased by the Ll back emf.
The output voltage decays, and when it reaches 4.95 V, EI signals the drivers to turn on Q2 and current is supplied
through Ll to C8 and C9 and the load. The output voltage rises and when it reaches 5.05 V, El again signals the

3-27

drivers to cut off Q2. The circuit oscillates in this manner and generates a 39 V p-p rectangular pulse train across
diode D5. The regulator circuit acts like a power Schmitt trigger and is either on or off depending on whether the
output voltage is too low or too high. The filtered output across C8 and C9 is thus +5 V with about a 100 mV p-p
10 kHz nominal sawtooth of superimposed ripple. The output filter is an averaging device so the rectangular pulse
train appears as an average voltage (+5 V nominal) at the output terminal.
If the load increases, the output voltage decays faster and Q2 turns on sooner so that the waveform frequency (duty
cycle) increases. Conversely, if the load decreases, the waveform frequency (duty cycle) decreases.
The driving chain for Q2 consists of first stage driver Q3, predriver Q4, and off driver Q5, which is controlled by El.
Off driver Q5 diverts current from the base of Q4 and thus controls it. Q5, R2, and Zener diode D2 are used to
generate +15 V for the operation of El from the +39 V raw input.
3.4.5.4 Overcurrent Protection Circuit - The regulator is protected from damage by high current due to a fault
(short circuit) in the load. The current is limited to about 30 A by the overcurrent protection circuit that consists of
Ql, R3 through R6, R25, R27, Q7, and C4.
The current drawn by the load through pass transistor Q2 is sensed by monitoring the voltage drop across 0.02 n
resistor R4 that is in series with the +39 V raw voltage. If the current exceeds 30 A, the drop across R4 increases and
forward biases QI and it turns on. Capacitor C4 charges and overcomes the bias on Q7 which turns it on. This action
turns on EI which, in tum, cuts off pass transistor Q2. The forward bias on QI is reduced and it turns off. Capacitor
C4 discharges and holds EI off for a period of time during which the current drops nearly to zero. When C4
discharges, EI turns on to re-establish the output voltage. If the fault still exists, the overcurrent circuit tums off Q2
again. As long as the fault exists, the regulator oscillates in this mode and limits output current to approximately
30 A.
3.4.5.5 OvervoItage Crowbar Circuit - The +5 V is used to power digital logic devices that must be protected
against voltage in excess of 7.0 V. This protection is provided by the overvoltage crowbar circuit that consists of
silicon controlled rectifier D7, Zener diode D3, diode D8, Q6, R22, R23, and C7.
During normal operation, the trigger input to SCR D7 is at ground potential because the voltage across Zener diode
is less than the 5.1 V required to cause it to conduct. If a malfunction occurs that increases the output voltage above
6.0 V, Zener D3 turns on which forward biases Q6. When Q6 conducts, resistor R23 in the SCR gate circuit draws
current and turns on D7. The +5 V output is short circuited to ground. Capacitor C7 bypasses R23 to ground so that
line transients of short duration that might cause D3 and D4 to conduct do not fire the crowbar.
3.5 POWER SUPPLY MAINTENANCE
3.5.1 Introduction
Power supply maintenance information includes the follOWing items:
a.
b.
c.

Checking and adjusting voltages
Removing power supply
Troubleshooting procedures

3.5.2 Checking and Adjusting Voltages
The power supply has four adjustable output voltages. Three voltages [+5 V (1), + 15 V, and -15 V] are associated
with the 5409728 DC Regulator and one [+5 V (2)] is associated with the H744 +5 V Regulator.

3-28

The computer must be extended more than half way out of the cabinet to provide access to all four adjustments.
The three de regulator adjustments are located in a vertical line midway on the right side of the computer; from top
to bottom they are +15 V, +5 V and -15 V. The H744 Regulator adjustment is located on the bottom of the
computer approximately 15 in. from the front and 1-1/2 in. from the right side. In each case, access is provided
through holes in the computer mounting box and power supply chassis (Figure 3-24).

ADJUSTING TOOL
+15V ADJUSTMENT

+5VADJUSTMENT

·15V ADJUSTMENT

6712-2

Figure 3-24 Power Supply Adjustments

All adjustments are controlled by potentiometers with slotted-head shafts that are conveniently rotated using a small
blade type screw-driver. Clockwise rotation increases the voltage in each case. The output voltages should be checked
and adjusted as close to nominal as possible. The nominal values and allowable tolerances are shown below.
5409728 Regulator Output Voltages
Nominal Value and Tolerance

Equivalent Range

5.0V±5%
15.0V±5%
-15.0 V± 5%

4.75 V to 5.25 V
14.25 V to 15.75 V
-14.25 Vto-15.75 V
3-29

H744 Regulator Output Voltage
Nominal Value and Tolerance
5.0 V± 5%

Equivalent Range
4.75 V to 5.25 V

When adjusting the voltages, use a digital voltmeter and measure the output under load at the connectors (Faston
tabs) on the pin side of the computer backplanes. These connectors are reached conveniently by extending the
computer from the cabinet, locking it in the 90° front up position and removing the bottom cover.
Observe the following cautions when adjusting the output voltages.
1.

Do not adjust the voltages beyond the 105% rating to avoid activating the overvoltage protection
(crowbar) circuit. In the case of the H744 Regulator, the +5 V output is drastically reduced when the
crowbar fires but the fuse does not blow. In the case of the 5409728 Regulator, fuse Fl (15 A) blows if
the +5 V output is adjusted too high; and fuse F2 (10 A) blows if the -15 V output is adjusted too high.
These crowbar circuits are designed to blow the fuses when activated. The +15 V output has no
overvoltage protection circuit but it uses fuse F 1 for protection in case of a malfunction in the +15 V
supply.

The two +5 V outputs, +5 V(1) from the 5409728 Regulator and +5 V(2) from the H744 Regulator,
must not be shorted together. Output +5 V(l) is available on power distribution board connectors 11
and J2; and output +5 V(2) is available on connectors 13, J4, and J5 of this board.

3.5.3 Power Supply Removal
The following procedure must be used to prevent damage to the power supply during removal from the mounting
box:
1.

Turn off power.

Remove the two screws that hold the line set to the rear of the mounting box, withdraw the line set
slowly, and disconnect line set connector J5 from power supply harness connector HI-PI (Figure 3-25).

Remove the six screws on the right side of the mounting box that hold the power supply chassis to the
mounting box (Figure 3-26). Disconnect the console cable connector from the Berg connector on the
M7260 module and move the cable away from the power supply cover. Remove the four screws that
secure the cover and remove it from the power supply.

Disconnect the following connectors that are accessible at the rear of the power supply (Figure 3-27).
a.

Power Supply harness connector HI-J2 from power distribution harness connector H2-P3.

Power distribution harness connector H2-P2 from transformer connector T2-11 (2 red and 2 black
wires).
CAUTION
The dc regulator output connector PSI-J2 is still connected
but it is not accessible.

3-30

Lift the power supply chassis slowly upward until it is free of the compartment in the mounting box
(Figure 3-28). Rest the bottom of the power supply chassis on the top of the mounting box and remove
power distribution harness connector H2-Pl from dc regulator output connector PS1-J2 (Figure 3-29).

Place the power supply on a bench. Be careful when lifting and carrying the power supply because its
center of gravity is near the front end.

POWEfi SUP!'!... Y
H·~m\!tm~

Cf.J!V.i\'!':;ClOf< HH'"!

6712-1

Figure 3-25 Disconnecting Line Set From Power Supply

3-31

f'Olilil:'R SUfif'L'I
\\.f1QUN1~iz\jG

SCREVi]S{Z}

(:O~S{)L-t:

CJ\Sr..E.

StJPPt'to{
COVHI

~'rC)V'"JER

}'OWER Ol!:::! fUaWfIOl\,
6712-5

iiJ.\RNESS
COi\l!\\ECTOfl Ii:.:·!":;!

P()~\:ER 3tJl~rjt·'r· r~.c\nr~H:·S~;-

COl"NECTOft

I\'hf~

()t)~JV-ER D1S-'1'H~gVYH)N

Tf\t~N8FQt1Mt;~?

H,~RNH~S

CO!\!N:ECTOR T::i:-.Jl
f2 tHE.u AN~):~ ElLAC~

CC1Nf'~ECT(Hi H2'·?::~

t;.--\qRE:.;'l

Figure 3-26 Removing Power Supply Mounting Screws

6712-6

Figure 3-27 Removing Power Distribution Harness
Connectors H2-P2 and H2-P3

3-33

POWER DISTRIBUTION
HARNESS CONNECTOR H2-Pl

DC REGULATOR OUTPUT
CONNECTOR PS1-J2

6712·8

6712-7

Figure 3-29 Disconnecting DC Regulator Output Connector

Figure 3-28 Lifting Power Supply From Mounting Box

3-35

3.5.4 Troubleshooting Procedures
3.5.4.1 Introduction - Most of the troubleshooting information presented relates to the components 5409728
Regulator and H744 Regulator.
Troubleshooting the other power system components such as the line set, relay, transformers, connectors, etc., can
be accomplished by performing an electrical continuity check using the power system interconnection diagram
(Figure 3·10).
3.5.4.2 Troubleshooting Hints
WARNING
Dangerous voltages (115 or 230 Vac) are present in the power
system. Be careful when servicing these circuits.

Because of the physical configuration of the power supply, very little troubleshooting can be performed with the
power supply installed. Voltages can be checked under load on the pin side of the computer backplane. For some
malfunctions, the problem can be isolated to the load or power supply by disconnecting the backplane cable and
checking the power supply outputs at the power distribution board connectors. Refer to the power distribution
board circuit schematic (Figure 3· 13) and list of Signals (Table 3·1).
The most likely source of a power supply malfunction is the 5409728 Regulator or the H744 Regulator. A quick
remedy for a malfunction in either of these regulators is to replace the complete unit. The replacement regulator
may need adjustment to compensate for the load. If the new regulator is initially adjusted too high, it may activate
the crowbar circuit. In the case of the H744 Regulator, no output is generated. In the case of the 5409728
Regulator, no output is generated and the +5 V fuse or -15 V fuse blows. If this should happen, remove power and
rotate the appropriate voltage adjustment fully counterclockwise. Replace the fuse, if required, and apply power.
Adjust the output to the recommended value per Paragraph 3.5.2.
NOTE
When replacing or swapping the 5409728 DC Regulator (PSI),
etch revision D or later must be used. Earlier etch revisions,
such as revision C which is used in the 5-1/4 in. PDP-II/OS,
11/10 Computer, must not be installed because of insufficient
current capacity.

3.5.4.3 Troubleshooting the 5409728 Regulator - Table 3·3 is a troubleshooting chart for the 5409728 Regulator.
It should be used with Figures 3·15 through 3·19 or regulator schematic drawing D·CS·5409728·0·1 in the print set.
A visual check is a valuable aid in locating the cause of a malfunction. Check for loose connections, burned resistors,
burned printed circuit board etch, cracked transistors or leaky capacitors.
As an additional aid to troubleshooting the 5409728 Regulator, waveform photos are provided for the +5 V and
-15 V outputs. These waveforms were taken on a Tektronix Model 453 Oscilloscope. All waveforms are with respect
to power common (12 pin 2).

3-37

Table 3-3
5409728 Regulator Troubleshooting Chart
Problem

Cause

No +S V and +IS V output

Flopen
D14 or transformer Tl open
+5 V adjusted too high*

+S V Output Too Low

Q5, 09, QlO, Q9, Qll, D12, or DIO shorted
C5 or C7 shorted
R49, R50, R46, or R44 open
Q6, Q7, Q8, or Dll shorted
Q9, QlO, or 09 open*
R5l or R50 open

+15 V Output Too High

Ql shorted
D8 open
R35 or R36 open

No -15 V Output

F2 open
D14 or transformer Tl open

-15 V Output Too Low

-15 V adjusted too high*
Q25, 04, Q26, Q21, Q27, D7, or D5 shorted
C14 or C12 shorted
R22, R26, R25, or R29 open
Q22, Q23, Q24, or D6 shorted
Q25, Q26, or 04 open

BUS AC LO L Will Not Go High

Q13, Q14, or Q15 shorted
Q16 or D3 open
R7, R3, R6, or R8 open
C9 shorted

BUS AC LO L Will Not Go Low
and/or acts erratically on
poweron/poweroff

Q13, Q14, or Q16 open
Q 15 or D3 shorted
R12, R13, R7, or RIO open

BUS DC LO L Will Not Go High

Q19, Q20, or Q18 shorted
Q17 or D3 open
R7, R2, or R6 open
C9 shorted

BUS DC LO L Will Not Go Low

Q19, Q20, or Q17 open
Q18 or D3 open
R7, R3, or R6 open
C9 shorted

3-38

Table 3-3 (Cont)
5409728 Regulator Troubleshooting Chart
Cause

Problem
BUS DC LO L Will Not Go Low
and/or acts erratically on
poweron/poweroff

Q19, Q20, or Q17 open
Q 18 or D3 shorted
R9, RIO, Rll, or R8 open

No LTC L Signal

R55 open
DB shorted

LTC L Going Too High

013 open

*These causes make the crowbar fIre, which, in turn, blows the appropriate fuse.

Figure 3-30 shows six wavefonns for the +5 V output taken at points A and B in the circuit (Figure 3-18). Point A is
the output of pass transistor Q6 and point B is the +5 V output (12 pin 3). Wavefonns a, b, and c are taken at point
A and wavefonns d, e, and f are taken at point B. Figure 3-31 shows six wavefonns for the -15 V output taken at
points C and D in the circuit (Figure 3-19). Point C is the output of pass transistor Q22 and point D is the -15 V
output (J2 pin 9). Wavefonns a, b, and c are taken at point C and waveforms d, e and f are taken at point D.
3.5.4.4 Troubleshooting the H744 Regulator - The design of the +5 V H744 Regulator is similar to the +5 V
portion of the 5409728 Regulator. In general, the same troubleshooting procedures and fault isolation techniques
apply to both regulators.
Some specific troubleshooting procedures are listed for the H744. Refer to Figure 3-21 which is the H744 circuit
schematic.
a.

A regulator that provides no output, or low output, without causing fuse Fl to blow is probably
working into a short-circuited output. Check for a short circuit in the load or a component failure in the
crowbar circuit.

A regulator that provides no output and has fuse Fl blown usually indicates a fault in the pass transistor
or its driver network. Proceed as follows:
1.

Check for scorching of the etched board in the area of Q3 and Q4. Check the associated
base-emitter bleeder resistors for damage.

Check pass transistor Q2, drive transistors Q3 and Q4, and level shifter Q5 with an ohmmeter. The
fault could be caused by continuous base drive to Q4.

The fault could be caused by an external short-circuit that holds precision voltage regulator El in
conduction. EI pin 4 to ground should measure approximately 20K n. EI pin 5 to ground should
measure approximately 1.5K n.

Check for shorts to ground at the fuse terminals and components mounted on the heat sink.

3-39

d) Point B, No load,
2 ms/div, and
50mV/div.

a) Point A, No load,
2 ms /div, and
10V/div.

e) Point B, No load,
20 I's/div, and
50 mV/div.

b) Point A, No load,
20 I's/div, and
10V/div.

f) Point B, 20A load,

c) Point A, 20A load,
20 I's/div, and
10V/div.

I's/div, and
50 mV/div.

Figure 3-30 +5 V Regulator Circuit Waveforms

340

a) Point C, No load,
5 msJdiv, and
10V/div.

d) Point 0, No load,
5 msldiv, and
50mV/div.

b) Point C, No load,
50 "sldiv, and
10V/div.

e) Point 0, No load,
50 "sJdiv, and
50 mV/div.

c) Point C, 5A load,
50 "sldiv, and
10V/div.

f) Point 0, 5A load,

50 "sldiv, and
50mV/div.

Figure 3·31 -15 V Regulator Circuit Waveforms

341

APPENDIX A
DC REGULATOR 5409728 SPECIFICATIONS
This appendix gives the detailed specifications for the 5409728 DC Regulator. They are tabulated by categories:
input, output, and mechanical, and environmental.
Table A-I
Input Specifications
Specifications

Parameters
Input Voltage (1 phase, 2 wires and ground)*

95-135/190-270 V

Input Frequency

47-63 Hz

Input Current

5/2.5 Arms

Input Power

325 W at full load

Inrush

80/40 A peak, 1 cycle

Rise Time of Output Voltages

30 ms max. at full load, low line

Input Overvoltage Transient

180/360 V, 1 second
360/720 V, 1 ms

Storage After Line Failure

25 ms min., starting at low line, full load

Input Breaker (part of BC05line set)

10 A/5 A single-pole, manually reset, thermal

Thermostat Mounted on heat sink (opens
transformer and fan power)

277 V, 7.2 A contacts
Opens 98°-105° C
Automatically resets 56°-69° C

Input Connections

line cord on BC05line set, length and plug
type specified with BC05

Turn-On/Turn-Off

Application or removal of power

Hipot (input to chassis and output)

2.1 kV/dc, 60 seconds

*Input voltage selection, 115 or 230 V, is made by specifying the appropriate line set, DEC Model BC05T or
BC05U. All specifications are with respect to the BC05 input.

A-I

Table A-2
Output Specifications
Parameter

Specification
+15 V

Load Range
Static
Dynamic

0-1 A
0-1 A

Max. Bypass Capacitance in load for 30 ms turn-on

SOOmF

Overvoitage protection

None

Current limit at 2So C

1.3 A to 1.7 A (-6.2

Backup Fuse

IS A (also used for +S V)

Adjustment

±S% min.

Regulation (All causes including line, load, ripple,
noise, drift, ambient temperature)

±S%

mAt C)

+5V
Load Range
Static
Dynamic #1
Dynamic #2

a-IS A
±S A (within 0-17 A load range)
No load - full load

Max. Bypass Capacitance in load for 30-ms turn-on

2000 pF

Overvoitage Crowbar (blows fuse)

S.7-6.8 V actuate (7 V abs. max. output)

Current Limit at 2So C

24-29.4 A (-0.1

Backup Fuse (series with raw dc)

IS A

Adjustment Range

±S%min.

Regulation
Line
Static Load
Dynamic Load #1
Dynamic Load #2
Ripple and Noise
1000 Hour Drift
Temperature (0-60°)

±O.S%
3%
±2%
±IO%
4% peak-to-peak
±0.2S%
±1%

A-2

At C)

Table A-2 (Cont)
Output Specifications
Parameter

Specification
-15V

Load Range
Static
Dynamic #1
Dynamic #2

0-7 A
t.I = 5 A (0.5 A/p.s)
No load - full load (0.5 A/p.s)

Max. Bypass Capacitance in load for 30·ms turn·on

1000p.F

Overvoltage Crowbar (blows fuse)

17.4-20.5 V (22 V abs. max. output)

Current Limit at 25° C

10-13.3 A (-0.03

Backup Fuse (series with raw dc)

Adjustment Range

±S% min.

Regulation
Line and Static Load
Dynamic Load #1
Dynamic Load #2
Ripple and Noise
1000 Hour Drift
Temperature (0-60° C)

±1%
±2.5%
±3%
3% peak·to·peak
±0.2S%
±1%

At C)

BUS DC LO L and BUS AC LO L
Static Performance at Full Load
(for 230 V connection, double voltages below)

BUS DC LO L goes to high

74-80 Vac line voltage

BUS AC LO L goes to high

8-11 V higher

BUS AC LO L drops to low

80-86 Vac line voltage

BUS DC LO L drops to low

7-10 V lower

Hysteresis (contained in above specifications)

3-4 Vac

Output voltages still good

70 Vac line voltage

A-3

Table A-2 (Cont)
Output Specifications
Parameter

Specification
BUS DC LO L and BUS AC LO L (Cont)
Dynamic Performance

Worst case on power-up is high line, full load.

~r--------------- POWER ON

---.V
I

- ._ _ _ _ _ _ _ _ _ _ _ SLOWEST OUTPUT
I
COMES UP

t"",---------

I-- 3Oms.....!I

MAX

BUS DC LO L

L2ms'-:
r-MIN

r - - - - - - - - - B U S AC LO L

NOMINAL

Worst case on power-down is low line, full load.

11-1094

I!-_______________

POWER DOWN

i·>-----..
2~~s----~.: ~

FASTEST OUTPUT
' \ GOES DOWN

I
I

~5m0
MIN"1

. _ _ _ _ _ _ _ _- - . :_ __
L

BUS AC LO L

j"
I

5ms_l_

I
:MIN

1m. M I N :
BUS DC LO L
11- r 099

Output Characteristics
Open Collector

50 rnA sinking capability
+0.4 V max. offset

Pull-Up Voltage on Unibus

5 V nominal, 180 n impedance

Rise and Fall Times

1 J.1.s max.
Outputs shall remain in 0 state subsequent
to power failure until power is restored
despite Unibus pulling voltages remaining.

TableA-3
Mechanical and Environmental Specifications
Parameter

Specification

Weight

7lb approx.
18 Ib approx.

Dimensions

10.50 in. length
5.19 in. width
3.25 in. height

Minimum Cooling Requirements

375 fe/min through heat sink
250 fe /min over caps, chokes, and transformer

Rated Heat Sink Temperature

95 0 C max.

Shock, Non-Operating

40 G (duration 30 ms) 1/2 sine in each of six
orientations

Vibration, Non-Operating

1.89 G rms average, 8 G peak; varying from
10 to 50 Hz, 8 dB/octave roll-off 50-200 Hz;
each of six directions

Ambient Temperature

o to +60

C operating
-40 to +71 0 C storage

Relative Humidity

95% max. (without condensation)

Altitude

lOKft

A-5

APPENDIX B
CABLE CONNECTORS

B.1 INTRODUCTION
This appendix lists the pin and signal designations for the serial communications line (SCL) interface, console cable,
and Unibus cable/jumper.
8.2 SERIAL COMMUNICATIONS LINE INTERFACE
Identification of the SCL interface is covered in detail. The 70-08360 SCL cable contains an 8-pin Mate-N-Lok
connector on one end that mates with the cable on the serial communications device. The other end contains a
40-pin Berg female connector that mates with a 40-pin Berg male connector on the M9970 Cable Card that is
inserted in slots CI-Ol in the computer backplane. The signals are wired, via the pin side of the backplane, to the
M7260 Data Paths module. Table B-1 contains pin and signal designations at these points and a description of each
signal. Figure B-1 shows the 70-08360 cable and Berg connector on the M9970.
8.3 CONSOLE CABLE
Console cable BC08R-03 is a 3-ft flat cable with 40-pin female Berg connectors on each end. Table B-2 lists the pin
and signal designations for the console cable.
B.4 UNIBUS CABLE/JUMPER
Table B-3 lists the pin and signal designations for the Unibus BCllA Cable and Unibus M920 Jumper.

B-1

MALE BERG CONNECTOR _ _~,
ON M9970 MODULE

P 5

\
\

~ t.I

e: ~

\
\

\
FEMALE BERG CONNECTOR _ _-~\
ON 70- 08360 CABLE

(

MATE-N-LOCK CONNECTOR
ON 70 - 08360 CABLE

11-2076

Figure B-1 SCL Cable 70-08360

B-2

Table B-1
SCL Interface Pin and Signal Designations

70-08360 CABLE
SIGNAL NAME

MATE-N-LOK PIN
ON 70-08360
CABLE

BERG PIN
ON 70-08360
CABLE

BERG PIN
ONM9970
CABLE CARD

SIGNAL NAME
ONM7260
MODULE

M7260
PIN

SIGNAL
DESCRIPTION

SER 0 + (20 rnA)

DPHSERO L

FE2

+20 rnA SERIAL OUT (from computer)

SER 0 - (20 rnA)

DPH SER 0-15 L

FJ2

- 20 rnA SERIAL OUT

SER IN + (20 rnA)

DPHSERIN H

FNI

+20 rnA SERIAL IN (to computer)

SER IN - (20 rnA)

DPH SI-I5 L

FPI

- 20 rnA SERIAL IN

READER RUN + (20 rnA)

DPH RDR ENAB L

FK2

+20 rnA TTY READER ENABLE

READER RUN - (20 rnA)

DPH RE-I5 L

FRI

- 20 rnA TTY READER ENABLE

SER 0 (TTL)

DPHSEROH

DFI

SERIAL DATA OUT (from computer)

NOTE 1

SER IN (TTL)

FS SER IN H

FMl

SERIAL DATA IN (to computer)

NOTE 1

CLK IN (TTL)

FSCLKL

FHI

EXTERNAL CLOCK INPUT FOR SCL

NOTE 1,2

CLK DISAB (TTL)

FS CLK DISAB L

FH2

DISABLE LINE FOR INTERNAL SCL
CLOCK

NOTE 1,3

20 rnA INTERLOCK

H,E

NOT USED ON THIS INTERFACE

+5 V

+5 V POWER AVAILABLE EXTERNALLY

+15 V

+15 V POWER AVAILABLE EXTERNALLY

GROUND

A,B,UU,VV

LOGIC GROUND

NOTE 1: These signals are TTL compatible.
NOTE 2: Externally supplied SCL CLOCK must be 16 times desired buad rate
(max. baud rate is 10,000 baud).
NOTE 3: This signal must be asserted low to disable internal clock if the external TTL CLOCK is to be used.

B-3

Table B-2
BC08R-03 Console Cable Pin
and Signal Designations

PP
BB
DD

FF
JJ
LL
NN

RR
IT
J
L
N
R
T
V
X

Z
HH
KK
MM
SS
CC
C
E
H
K
M
P
S

Designations
Signals
DAKH
SWIS(1)H
SWI4(1)H
SW 13 (1) H
SW I2(1)H
SW 11 (1) H
SW 10 (1) H
SW 09 (1) H
SW 08 (1) H
SW 07 (1) H
SW 06 (1) H
SW OS (1) H
SW04(1)H
SW 03 (1) H
SW 02 (1) H
SWOI (1)H
SW 00 (1) H
SCAN ADRS 01 (1) L
SCAN ADRS 02 (1) L
SCAN ADRS 03 (1) L
SCAN ADRS 04 (1) L
PUPL
RUNL
KEY LOAD ADRS (1) L
KEY EXAM (1) L
KEY CaNT (1) L
KEY HLT ENB (1) L
KEY START (1) L
KEYDEP(1) L

B-S

Table B-3
Unibus BCIIA Cable/M920 Jumper
Pin and Signal Designations

Pin
AAI
AA2
ABI
AB2
ACI
AC2
ADI
AD2
AEI
AE2
AFI
AF2
AHI
AH2
AJI
AJ2
AKI
AK2
ALl
AL2
AMI
AM2
ANI
AN2
API
AP2
ARI
AR2
ASI
AS2
ATl
AT2
AUl
AU2
AVI
AV2

Designation
Signals

INIT L
POWER(+S V)
INTRL
GROUND
DOOL
GROUND
D02L
DOl L
D04L
D03L
D06L
DOS L
D08L
D07L
DlOL
D09L
D12 L
Dll L
D14L
DI3 L
PAL
DIS L
GROUND
PB L
GROUND
BBSYL
GROUND
SACKL
GROUND
NPRL
GROUND
BR 7L
NPGH
BR6L
BG7H
GROUND

BAI
BA2
BBI
BB2
BCI
BC2
BDI
BD2
BEl
BE2
BFl
BF2
BHl
BH2
BJI
BJ2
BKI
BK2
BLl
BL2
BMI
BM2
BNI
BN2
BPI
BP2
BRI
BR2
BSI
BS2
BTl
BT2
BUl
BU2
BVI
BV2

B-6

Designation
Signals
BG6H
POWER(+S V)
BGSH
GROUND
BRS L
GROUND
GROUND
BR4L
GROUND
BG4H
ACLOL
DCLOL
AOIL
AOOL
A03 L
A02L
AOS L
A04L
A07L
A06L
A09L
A08L
All L
AlOL
A13 L
A12L
AIS L
AI4L
AI7 L
AI6 L
GROUND
Cl L
SSYNL
CO L
MSYNL
GROUND

PDP-II/OS, 11/10
SUPPLEMENT I
DEC-II-HOSAA-8-D

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DEC-II-HOSAA-B-D
SUPPLEMENT 2

description of data paths
module M7260 revision M

digital equipment corporation • maynard massachusetts
t

1st Edition, August 1973
2nd Printing, September 1973
3rd Printing, july 1974

Copyright © 1973, 1974 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.

Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL

UNIBUS

PDP
FOCAL
COMPUTER LAB

INTRODUCTION
This publication is a supplement to the PDP-11/05, 11/10 Computer Manual (DEC-11-HOSAA-B-D). It discusses the
differences between the latest M7260 Data Paths Module (Revision M) and previous M7260 modules. This latest
module is manufactured to etch board revision C, which has a completely different layout than previous modules.
All revisions of the M7260 module are functionally interchangeable. The M revision contains several circuit improvements and uses medium scale integration (MS!) to perform some functions that were performed previously by small
scale integration (SSI). Substitution of MSI devices for SSI devices produces less interconnections.
The functional operation of this module is described in Chapter 8 KD11-B Detailed Description and Chapter 9
Microprogram Control of the referenced manual. Because of the new layout, the component designations (E numbers) on the M revision module are different than those referenced in the PDP-II/OS, 11/10 Computer Manual,
DEC-11-HOSAA-B-D.
This supplement discusses only the significant changes that occur in the M revision. Each change is discussed as a
separate item. Detailed logic prints are included in the separately supplied print set; specificallY, drawing
D-CS-M7260-0-1 RevM, Sheets 1-12. Revision F is the previous module referenced in the discussion.

1. Use of Resistor Network Instead of Discrete Resistors for Pull UptpuU Down
Resistors network, part number 1311003-02, is used instead of discrete pull up/pull down resistors. It is a hybrid
thick fIlm resistor divider network in a 16-pin DIP. The package consists of 14 identical circuits (Figure 1). Each
circuit consists of an Rl resistor (330 il) and R2 resistor (680 Q) connected in series between +5 V and ground.
Connection to the logic device is made between Rl and R2.
Four networks (E042, E045 , E060, E084) are used on the module. Refer to drawing D-CS-M7260-O-1, Rev M, sheets
4,5,6,7,9, and 10.
2. Use of 8838 Quad Bus Transceivers Instead of 380 Quad Bus Receivers
and 8881 Quad Bus Drivers
Four 8838 quad bus transceivers replace four 380 quad bus receivers and four 8881 quad bus drivers. Sixteen Unibus
receivers/drivers are contained in four 16-pin DIP ICs instead of eight 14-pin DIP ICs. Figure 2 shows a signal/pin
designation diagram for the 8838 and a schematic of one transceiver with the common driver enabling gate.
These devices are designated EOl, E02, E03, and E05. Refer to draWing D-CS-M7260-O-1. Rev M, sheets 4, 5, 6, and

7.
3. Addition of Switch Register Multiplexers in ALEG
at Output of Scratch Pad Memories
Four 8266 2-input, 4-bit multiplexers have been added between the scratch pad memories and the arithmetic logic
units (ALU). Each multiplexeris identified as SWITCH REG MUX. They are designated E033, E034, E035, and
E036. Refer to drawing D-CS-M7260-0-1, Rev M, sheets 4, 5, 6, and 7.
Figure 3 shows SWITCH REG MUX E036 for ALEG bits 00-03. The switch register signals from the console cable
are sent directly to the A inputs of E036. In earlier modules, the switch register signals were sent to 74HOI NAND
gates that were wired-ORed to the ALEG. These gates have been removed in the revision M module.
The outputs of SPM E040 are sent to the B inputs of SWITCH REG MUX E036. Input selection (Aor B) is made
by select lines SI and SO. The multiplexer outputs are sent to the A inputs of ALU E027.
The scratch pad memories E037, E038, E039, and E040 have been changed from type 3101A to type 7489, which
are less expensive devices.
4. Addition of BLEG Multiplexer for BLEG Bits 00-03
A type 74S158 2-line to I-line multiplexer (E021) has been added to the output of BREG EOI5, which handles
BLEG bits 00-03 (Figure 4). It replaces five type 74HOI NAND gates and four pull-up resistors that are used in
earlier modules. Refer to drawing D-CS-M7260-O-1, Rev M, sheet 4.
The three operating modes of the BLEG that provide input data to the ALU remain the same. The modes are:
BREG unmodified, sign extend BREG, and generation of the constant + 1.
S. Provision for Adding a CONSTANTS ROM for ALEG Bits 08-15.
Provisions have been made in the etched circuit at location E043 to accommodate a 32 X 8 bit ROM. This ROM
would serve as a constants generator for ALEG bits 08-15. Refer to drawing D-CS-M7260-O-1, Rev M, sheet 6.
6. Changes In Auxiliary Control Logic and Processor Status Word Logic
The basic enabling signal for the auxiliary control mode is CONF AUX CONTROL L. The pulse width of this signal
has been extended to 600 ns. This provides adequate time for the inputs to CC MUX multiplexer E062 and C & V
BIT ROM E060 to settle. This allows removal of the two type 74174 hex flip-flops that are used in earlier modules
to delay these input signals.

+5V

GND

....-

8
Each R I = 330 ahms
Each R 2 =680 ohms

eircuit

Schematic

Pin Designations
11-2083

Figure 1 Resistor Network (1311003"()2) Circuit Schematic and Pin Designations

BUS 1
DATA IN 1
DATA OUT 1
BUS 2
DATA IN 2
DATA OUT 2
ENABLE A
GROUND

Vee
BUS 4
DATA IN 4
DATA OUT 4
BUS 3
DATA IN 3
DATA OUT 3
ENABLE B

,.....-- ... 1
(

BUS 1

,"m"~- j [?:-OATAO""
-

DATAINI

ENABLE B

ONE OF FOUR
11-1860

Figure 2 8838 Quad Bus Transceivers

In the processor status word (pSW) logic, type 74175 quad flip-flop E056 replaces three type 7474 D-type flip-flops.Refer to drawing D-CS-M7260-Q-1, Rev M, sheet 8. The flip-flops are associated with the N, Z, and V bits of the
PSW. The function of the logic has not changed. Use of the 74175 requires fewer interconnections on the module.
A few additional minor changes to the PSW logic are described below.
a.

CC MUX E062 has its enable (E) input permanently connected to ground. When the select (S) input is
low, input word A is selected; and when S is high, input word B is selected. The select (S) signal is
CONF AUX CONTROL L, rather than its delayed counterpart.

Signal DPF C CLK L to E057 pin 12 is used rather than its delayed counterpart.

From sWItch
register bits 00-03

,---A---,
01

~ A2
14
From output
of SPM E04o.
ALEG bits
00-03

SWITCH
REG MUX

----...Q§... AI
05

TRUTH TABLE
13

8266
E036

To A inputs
of ALU E027
04

12
fO

BO
S1

OUTPUT

L
L

L
H

Bn
An

H
H

L
H

Bn
Inh

J 07

DPA SP WRITE H

SELECT
INPUTS

DPA ENAB SWIT CH REG H

11-2082

Figure 3 Typical Switch Register Multiplexer

~
13
From out puts
of BREG E015
BREG 00 (1) H
through
BREG 03 (0 H

~
06

~
-= 10

04
f3

A3
B2
74S158
E021

A2
Bl

INPUTS

OUTPUT

09
fO

CONBINH + 1 L---1.! AO
S

~'5
CONG BB OT H

TRUTH TABLE
To B inputs
of ALU E027
BLEG bits 00-03

BLEG
MUX

1
11-2081

Figure 4 Multiplexer for BLEG Bits 00-03

7. Changes In the Serial Communications Line (SCL) Logic
Several changes have been made in the SCL logic. They are described below. The two most significant changes are a
new oscillator and new baud selection logic. Refer to drawing D-CS-M7260-O-1 , Rev M, sheets 11 and 12.
a.

To ensure proper set-up of the transmitter and receiver interrupt logic circuits, a different method is used
to clear the TBMT and DA flip-flops (sheet 12). In previous modules, the TBMT flip-flop is cleared
directly by the XMIT INT flip-flop. Similarly, the DA flip-flop is cleared directly by the RCD INT flipflop. In the Rev M module, the TBMT and DA flip-flops are cleared at the same time as the XMIT INT
and RCD INT flip-flops, respectively.

Three outputs of the universal asynchronous receiver/transmitter (UART) are buffered by type 7408
AND gates (sheet 11). They are the serial output (SO), data available flag (DA), and the transmitter
buffer empty flag (TMBT).

Clock signal DPH TTY CLK H is brought out to module pin ED2 (sheet 11). This signal can be accessed
on the pin side of the backplane during servicing.

One-shot E076 has been added to provide a longer RDA (Received Data Available) pulse to the UART.
When triggered, the one-shot generates a negative pulse of approximately 1.2 [.1S duration.

The Rev M module incorporates a new high stability oscillator (sheet 11).

Two type 9602 retriggerable one-shots are interconnected to form a simple oscillator that generates the SCL clock
signal (Figure 5). The oscillator starts when signal DPH B INIT L is released (goes high) and is self-sustaining thereafter. It has a gated input that allows initialize signal DPH B INIT L to inhibit the clock when it is asserted.
Both 9602s are in the same package (EIOO) and are identified as A and B in this discussion. To ensure stability, the
+5 V power to these one-shots is ftltered by R22, R27, C Ill, and C 112. The clear inputs (pins 03 and 13) are not
used so they are permanently pulled up to +5 V.
Each one-shot triggers on a negative (falling) edge at input pin 05/11 while input 04/12 is held permanently low
(connected to ground).
The output pulse width is determined by the RC network connected across pins 14/2 and 15/1. For one-shot B
(pins 2 and 1), the values are chosen to provide a pulse width of 10 I1S. For one-shot A (pins 14 and 15), the pulse
width is variable from about 22 to 4411S. Potentiometer R21 is used to perform the adjustment.
As power is applied and DPH B INIT L is asserted, both one-shots are at rest; therefore, the 0 output (pin 09) of oneshot A is high. This signal is sent to the triggering input of one-shot B and is also fed back to pin 13 of NAND gate
E097. When DPH B INIT L is released (goes high), the output of E099 goes low and triggers one-shot A. A negative
pulse is generated at the 0 output of one-shot A. Assume that R21 is adjusted to give a pulse width of 26 [.1S. The
negative-going leading edge of this pulse triggers one-shot B, which produces a 10 I1S positive pulse at its 1 output
(pin 06). When one-shot A times out, its output goes high and, because of the feedback connection, it is triggered
again. There is a delay of approximately 25 ns before it triggers again and subsequently causes one-shot B to trigger
again. The pulse width of one-shot A determines the period of clock signal DPH TTY CLK (1) H. In this case, 10 I1S
clock pulses are produced at a period of 2611s, which is a frequency of 38.4 kHz.
A simplified timing diagram is shown in Figure 5.

TRUTH TABLE FOR
9602 ONE-SHOT
INPUT
PIN NO.
05/11

OUTPUT
PIN NO.

04/12 06/10 07/09

1""1.

.n.

One - shot A determines
period of clock signal.
Period is adjustable by
potentiometer R 21

DPH B INIT L

One - shot B determines
pulse width of clock
signal

TTY CLK(1) H

R24

+5V
R22

R27

Cl12pCl11
Filtered +5 V power
for one -shots A ond B

HJ
INIT L
to E097 L

A OUTPUT
PIN 09

:l n -In

25ns

I-"T=26/-,S

B OUTPUT
PIN 06

H
L
TIMING DIAGRAM
11-2084

Figure 5 SeL Oscillator Schematic and Timing Diagram

The Rev M module incorporates switch selectable baud rates (sheet 11).

Signal DPH TTY CLK (l) H is used to create the clock for the universal asynchronous receiver/transmitter (UART).
This signal is first sent to a counter whose outputs are selected by a switch to provide five different UART clock
rates. The UART receiver and transmitter clocks must operate at a rate 16 times the value of the desired baud rate
because the UART samples incoming data 16 times per second. The frequency in Hz of a particular UART clock is
found by multiplying the desired baud rate by 16.
Signal DPH TTY CLK (l) H from the oscillator is sent to the clock 1 (CI) input of 4-bit binary counter E095
(Figure 6). It is a type 74197 that is connected as a 4-bit ripple-through counter. The clock input (C 1) is divided by
2,4,8, and 16 at outputs RO{l), Rl(I), R2{l) and R3{l), respectively. Load inputs DO, Dl, D2, and 03 are all connected to ground so the counter cannot be preset. The counter is cleared (all outputs go to 0) when DPH B INIT L
is asserted.
The oscillator output, DPH TTY CLK (l) H, and counter outputs are connected to a single pole rotary switch whose
output is one of five frequencies as shown below:
Switch Position

Output Frequency

01
02
03
04
05

Oscillator
Oscillator + 2
Oscillator + 4
Oscillator + 8
Oscillator + 16

The switch output is sent to pin 01 of NAND gate E099. The other input (pin 02) of this gate is pulled high except
when an external clock is used rather than the one on the M7260 module. Under these conditions, the clock signal
as chosen by the switch appears inverted at the output (pin 03) of E099. This clock signal is sent to pin 04 of another
E099 NAND gate, which is shown as the logically equivalent negative input OR gate. The other input (pin 05) of this
gate is also high except when an external clock is used; therefore, the clock signal is inverted again and appears as
DPH TTY CLK H at pin 06 of the second E099 gate. The signal clocks the UART receiver and transmitter and counter
E088 which generates signal DPH START H.
Two commonly used baud ranges are obtained by selecting 26 p.s or 35.5 p.s as the period of the oscillator output
(Table 1).
An external clock can be used instead of the clock on the M7260 module. The module clock is disabled by a low
level on pin FH2 (Figure 6). The disabling signal is called FS CLK DISAB L. The external clock is connected to
pin FHI and is called FS CLK L. The inverted external clock signal appears at pin 06 of E099.
Table I
Baud Selection

Switch Position

Baud

1 (OSC output)
2 (OSC + 2)
3 (OSC +4)
4 (OSC+8)
5 (OSC + 16)

2400
1200
600
300
150

Range I
Period*

26p.s
52 J.lS
104p.s
208 p.s
416 J.lS

Baud

Range 2
Period*

1760
880
440
220
100

35.5 p.s
71 p.s
142 J.lS
284p.s
568 J.lS

*Period of clock signal DPH TrY elK H observed on backplane pin E02D2.

Connected as 4 bit ripple
through counter. Oscillator

output is divided by 2.4,
8 and 16.

11
03
10
04
Oscillator
output

R3(1)

D3
74197

R2(1)

D2
Dl

R H1 )
E095

RO(1)

12
02

Switch used to
select baud rate.

09
05

Output signal to
clock U ART.

DPH B INIT L
DPH TTY CLK (1) H _ _ _ _ _ _-+-_ _ _ _ _ _ _ _ _---.J

06 E02D2
DPH TTY CLK H

FS CLK DISAB L ..:.F...:.H.:..:2=---_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---'
FS

CLKL~F~H~I

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
Observe signal at
~in E02D2 during

Low signal on pin FH2 disables
module clock. External clock
can be connected to pin F H 1

oscillator

adjustment

\ 1 - 2080

Figure 6 Baud Selection Logic

BAUD RA TE ADJUSTMENT
Use the following procedure to adjust the baud rate for the serial communications line.
1.

Tum power off.

Extend the computer out of the cabinet until the chassis slide lock clicks.

Remove the mounting box top and bottom covers.

Remove the M7260 module. Using a small blade type screwdriver, tum the baud adjustment switch
(S1) fully counterclockwise, which is position 1. Refer to Table 1 to determine the switch position
for the selected baud rate. Set the switch to the proper position and insert the M7260 module into
the backplane.

Tum power on.

Connect an oscilloscope probe to backplane pin E02D2 to observe signal DPH TTY CLK H (Figure 6).
This is the UART clock signal; its frequency is 16 times the baud rate.

Adjust the SCL oscillator frequency to match the selected baud rate in accordance with Table 1. This
table lists the period of clock signal DPH TTY CLK H versus baud rate for two adjustment ranges. For
example, assume that in step 4 the baud switch was set to position 4 to select 300 baud in range 1. The
corresponding clock signal period is 20811S. It is set by adjusting potentiometer R21 on the M7260
module, which is accessible with the module installed. The clock period is displayed on the oscilloscope.
Clockwise adjustment decreases the period and counterclockwise adjustment increases the period.
NOTE
Once this adjustment is made, other baud rates within the same
range can be selected by changing only the baud switch position.
If the new baud rate is in the other range, steps 1 through 7 must
be performed because switching ranges requires a change in the
period of the clock signal.

Remove the oscilloscope probe, replace the mounting box top and bottom covers and push the computer
back in the rack. Signal DPH TTY CLK (1) H is the output of the SCL oscillator. After the adjustment
procedure is completed, the period of this signal is 2611S for range I and 35.511S for range 2. This signal
is accessible for observation only by extending the M7260 module and directly probing EIOO pin 06.

DEC-II-HOSAA-B-D
SUPPLEMENT 3

description of control logic
and microprogram module
M7261 revision R

digital equipment corporation · maynard, massachusetts

1st Edition January 1974
2nd Printing July 1974

The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no responsibility for any errors which may appear in this
manual.
Printed in U.S.A.

The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
UNIBUS

PDP
FOCAL
COMPUTER LAB

INTRODUCTION

This publication is a supplement to the PDP-11/05, 11/10 Computer Manual (DEC-II-HOSAA-B-D). It discusses the
differences between the latest M7261 Control Logic and Microprogram Module (Revision R) and previous M7261
modules. This latest module is manufactured to etch board revision F, which has a completely different layout than
previous modules.
All revisions of the M7261 module are functionally interchangeable. The R revision contains several circuit improvements.
The functional operation of this module is described in Chapter 8, KDII-B Detailed Description, and Chapter 9,
Microprogram Control, of the referenced manual. Because of the new layout, the component designations (E numbers)
on the R revision module are different than those referenced in the PDP-11/05, 11/10 Computer Manual.
This supplement discusses only the significant changes that occur in the R revision. Each change is discussed as a
separate item. Detailed logic prints are included in the separately supplied printed set; specifically, drawing
D-CS-M7261-0-1 Revision R, Sheets 1-14.

Use of Resistor Network Instead of Discrete Resistors for Pull Up/Pull Down

Resistor network, part number 1311003-02, is used instead of discrete pull up resistors. It is a hybrid thick film
resistor divider network in a 16-pin DIP. The package consists of 14 identical circuits (Figure 1). Each circuit consists of an Rl resistor (330 Sl) and R2 resistor (680 Sl) connected in series between +5 V and ground. Connection
to the logic device is made between Rl and R2.
Six networks (E54, E82, E92, E93, E95 and E 100) are used on the module. Refer to drawing D-CS-M7261-0-1,
sheets 3,4,6,8,9,10,12, and 13.

+5V

>--

GND

>--

r--

>--

8
Each R 1= 330 ohms
Each R 2 = 680 ohms

Circuit Schematic

2345678
Pin DesiQnatlons
11-2083

Figure 1 Resistor Network (1311003-02) Circuit Schematic and Pin Designation

Addition of Circuit Selectively Disables the Internal SCL Interface

A simple circuit has been added to selectively disable the internal SCL interface, if the user desires to control a serial
communications device with a separate interface using the standard console addresses given below.
The circuit is shown in print CONA, which contains the internal address detection logic. For convenience, the disabling circuit is also shown in Figure 2.

777560 }
777562
777564
777566

SCL REGISTER
ADDRESSES
DECODED BY
BA REGISTER

05104103 BA BITS

High signal
disables ROM

I I I I I III I BINARY
6

IL i

OCTAL

--======

L I_ _ _ _ _

CONA BA03(1)L -

CONA
CONA BA04(0lL
BA 05(0lL --

L
L

TO ENABLING INPUTS
B
t---'--- OF INTN ADDRS
DECODE ROM E53

i - - - - - E82-1
I
I
I
IL ________
=
JI

+5V

r<>-;W;;;I:-<>----------------
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