DEC 12 SRZB D_PDP 12_System_Reference_Manual_Aug71 D PDP System Reference Manual Aug71
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Digital Equipment Corporation Maynard, Massachusetts ~nmnomn PDP-12 SYSTEM REFERENCE MANUAL DEC-12-SRZB-D PDP-12 SYSTEM REFERENCE MANUAL DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS 1st Printing (Preliminary) June 1970 2nd Printing (Revised) July 1970 3rd Printing (Revised) August 1971 Copyright © 1971 by Digital Equipment Corporation The material in this manual is for reference only. Instruction times, operating speeds, and the like are provided solely as reference information, and are subject to change at any time without prior notice. The drawings, specifications, and descriptions herein are the property of Digital Equipment Corporation, and shall not be reproduced or copied in whole or in part as the basis for the manufacture or sale of items without written permission. The following are trademarks of Digital Equipment Corporation, Maynard, Massachusetts: DEC FLIP CHIP DIGITAL PDP FOCAL COMPUTER LAB CONTENTS Chapter Page CHAPTER 1 GENERAL DESCRIPTION 1.1 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 1.2 Description System Central Processor Memory Operating Modes Input/Output Facilities and Display Symbols and Abbreviations 1-1 1-1 1-3 1-4 1-4 1-5 1-6 CHAPTER 2 CONTROLS AND INDICATORS 2.1 2.2 2.3 2.4 2.5 PDP-12 Console Controls and Indicators Data Terminal CRT Display, Type VRl 2 LINCtape Transport, Type TU5 5 Teletype, Model 33 ASR 2-1 2-1 2-1 2-1 2-1 CHAPTER 3 LINC MODE PROGRAMMING 3.1 3.1.1 3.1.2 3.1.3 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.3.I 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.3.9 3.3.10 Organization of Memory General Program Counter Instruction and Data Field Registers Memory Addressing Methods General Direct Addressing Indirect Addressing: {3-Class Addressing: a-Class LINC Mode Instructions Instruction Formats Instruction Descriptions Full-Word Instructions Full-Word Logic Full-Word Comparison Half-Word Operations a-Class Operations Program Control Shift and Rotate Operations Skips 3-1 3-1 3-2 3-2 3-3 3-3 3-3 3-3 3:-6 3-6 3-6 3-7 3-7 3-11 3-12 3-13 3-14 3-15 3-16 3-19 iii CONTENTS (cont) Page Chapter 3.3.11 3.3.12 3.3.13 3.3.14 3.3.15 3.3.16 3.3.17 3.4 3.4.1 3.4.2 3.4.3 3.4.4 3.5 3.5.l 3.5.2 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7 3.6.8 3.6.9 3.6.10 ~.6.11 3.6.12 3.6.13 3.6.14 Miscellaneous Console Switches Mode Control Input/Output Bus Memory Address Control Special Functions Instruction Trap CRT Display, Type VR12 Point Displays Character Displays Half-Size Characters Character Set Data Terminal Analog Inputs Relays LINCtape Type TC 12 Organization of Data Programming Tape Motion LINCtape Instructions Extended Operations Extended Address Format Extended Units Tape Interrupt Enable No Pause Condition Hold Unit Motion MARK Condition Maintenance Mode Tape Trap Tape Word Skip 3-21 3-22 3-22 3-23 3-24 3-29 3-30 3-31 3-32 3-32 3-33 3-33 3-35 3-35 3-36 3-37 3-37 3-41 3-42 3-43 3-45 3-46 3-47 3-47 3-48 3-48 3-48 3-49 3-49 3-49 CHAPTER4 8 MODE PROGRAMMING 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.4 4.4.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 4.6 iv Organization of Memory Organization Page 0 Extended Memory Memory Addressing Methods Direct Addressing Indirect Addressing Au to indexing 8 Mode Instructions Memory Reference Instructions Operate Class Instructions Program Interrupt Operation Using the Program Interrupt Extended Arithmetic Element Type KE 12 Operation EAE Instructions EAE Programming Extended Memory 4-1 4-1 4-1 4-2 4-2 4-2 4-3 4-4 4-5 4-5 4-6 4-12 4-12 4-13 4-13 4-13 4-13 4-16 4-19 CONTENTS (cont) Chapter 4.6.1 4.6.2 4.6.3 Page Registers Instructions Programming 4-19 4-20 4-21 CHAPTER 5 INPUT/OUTPUT BUS DESCRIPTION 5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.4 5.4. l 5.4.2 5.4.3 5.4.4 5.4.5 Programmed Data Transfers and 1/0 Control Timing and IOP Generator Device Selector (DS) Input/Output Skip (IOS) Accumulator Input Data Transfers Output Data Transfers Program Interrupt Multi-Level Automatic Priority Interrupt Interrupts Push Restore-"POP" (REST-IOT 6771) Vectoring Maintenance Logic Programming Programming Restrictions Instruction List DM12 Data Break Transfers Single-Cycle Data Breaks Input Data Transfers Output Data Transfers Memory Increment Three-Cycle Data Breaks Interface Design and Construction PDP-12 Interface Modules M Series Flip Chip Modules Construction of Interfaces IOT Allocations Interface Connections 5-4 5-6 5-7 5-8 5-9 5-10 5-11 5-11 5-15 5-15 5-15 5-16 5-16 5-17 5-18 5-19 5-19 5-20 5-21 5-22 5-22 5-23 5-27 5-29 5-30 5-30 5-34 5-39 5-43 5-44 CHAPTER 6 PERIPHERAL DEVICES 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.2 6.2.1 6.2.2 6.3 6.3.l 6.3.2 Introduction Teletype Model 33 ASR Model 33 KSR Model 35 KSR Model 37 KSR Teletype Controls Real Time Clocks Real Time Interface, Type KWl 2-A KW12-B and KW12-C Fixed Interval Clocks Disk Storage Random Access Disk File, Types DF/DS32 and DF/DS32-D Disk Memory System Type RF /RS08 6-1 6-3 6-3 6-3 6-4 6-4 6-4 6-18 6-18 6-25 6-27 6-27 6-30 v CONTENTS (cont) Page Chapter 6.3.3 6.3.4 6.4 6.4.1 6.4.2 6.4.3 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.7 6.7.1 6.8 6.8.1 6.8.2 6.8.3 6.9 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 RK8 Disk Cartridge Memory System Disk Software Magnetic Tape Automatic Magnetic Tape Control, Type TC58 Magnetic Tape Transports LINCtape Option TCl 2-F Line Printers Line Printers and Control, Type LP 12 Line Printers and Control, Type LP08 Card Readers Card Reader and Control, Type CRl 2 Optional Mark Card Reader Type CM 12 Incremental Plotters Incremental Plotter and Control, Type XYl 2 Paper Tape High-Speed Paper-Tape Punch and Reader, Type PC 12 High-Speed Paper-Tape Punch, Type PPl 2 High-Speed Paper-Tape Reader, Type PR 12 Data Buffers Data Buffer Type DB 12-P, N Power Fail/Restart Power Failure Option, Type KP 12 Analog-To-Digital General Purpose Multiplexed Analog-to-Digital Converter System, Type AFO 1-A Digital-To-Analog Digital-to-Analog Converter, Type AAOl-A 6-38 6-44 6-45 6-45 6-54 6-57 6-59 6-59 6-60 6-63 6-63 6-66 6-68 6-68 6-71 6-71 6-71 6-72 6-73 6-73 6-74 6-74 6-76 6-76 6-82 6-82 CHAPTER 7 PROGRAM LIBRARY 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.1.17 7.1.18 7.1.19 7.1.20 7.2 7.2.1 vi PDP-12 Programs LAP 6 - DIAL Display Interactive Assembly Language (DEC-12-SE2D-D) Peripheral Interchange Program (PIP) QUANDA (DEC-12-FISA-D) DATAM (DEC-L8-FDAA-D) GRAPHA (DEC-L8-UGAA-D) FRQANA (DEC-L8-FANA-D) MAGSPY (DEC-12-UZSA-D) COMPAR (DEC-L8-EUCA-D) SEARCH (DEC-L8-EUSA-D) CONVERT (DEC-12-ESYB-D) MARK 12 (DEC-12-YITB-D) L8SIM (DEC-12-Sll B-D) FRED (DEC-12-FZFA-D) PRTC 12-F (DEC-YIY A-D) SIGAVG/SINPRE (DEC-12-UZ I A-D/DEC-12-UW4A-D) CATACAL (DEC-12-UWlA-D) NMRSIM (Nuclear Magnetic Resonance Simulation) (DEC-12-UWSA-D) ADTAPE/ ADCON (DEC-12-UW2A-D) TISA (DEC-l 2-UW3A-D) FOCAL12 PDP-8 Programs System Programs 7-1 7-1 7-3 7-3 7-3 7-3 7-3 7-3 7-3 7-3 7-3 7-4 7-4 7-4 7-4 7-4 7-4 7-4 7-5 7-5 7-5 7-5 7-5 CONTENTS (Cont) Chapter 7.2.2 7.2.3 7.3 7.4 Page Elementary Function Routines Utility Program DECUS Program Diagnostic Programs 7-7 7-9 7-10 7-27 APPENDIX A LINC MODE INSTRUCTIONS APPENDIX B 8 MODE INSTRUCTIONS APPENDIX C I/0 BUS INSTRUCTIONS APPENDIX D 8 MODE PERFORATED-TAPE LOADER APPENDIX E TAPE MAINTENANCE INSTRUCTIONS E.l E.2 E.2.1 E.2.2 E.2.3 E.2.4 General Tape Maintenance Instructions IOT 6141 IOT 6152 IOT 6154 IOT 6154 Detailed Transfer Information E-1 E-1 E-1 E-2 E-2 E-3 APPENDIX F TABLE OF CODES F. l F.2 F.3 F.4 F.5 F.6 Model 33/35 ASR/KSR Teletype Code Model 33 ASR/KSR Teletype Code in Binary Form LT-37 Transmit and Receive Code Table Card Reader Codes LP08 Line Printer Code LP 12 Automatic Line Printer Code F-1 F-2 F-3 F-5 F-6 F-7 APPENDIX G CABLE CONNECTIONS TO PDP-12 FRONT PANEL APPENDIXH MATHDATA INDEX vii TABLES Title Table No. Page 4-1 Central Processor Register Indicators Central Processor Major State Indicators Central Processor Miscellaneous Indicators Tape Processor Major State Indicators Tape Processor Miscellaneous Indicators Function of Computer Consoel Keys Toggle Switch Registers Individual Console Toggle Switches Analog Knobs and Power Switch Panel Relay and Analog Input Panel VR 12 Display Scope Controls TU55 Tape Transport Controls and Indicators Teletype Model 33 ASR Controls ASR-33 Character Set Display Pattern Summary of Addressing Methods in 8 Mode 2-3 2-3 2-3 2-4 2-4 2-5 2-7 2-7 2-9 2-9 2-11 2-12 2-14 3-34 4-4 5-1 Stack Register 5-16 5-2 M Series Module Summary Cable Connections to the PDP-12 1/0 Bus PT08 Specifications PT08 Device Codes DC02-E Specifications DF32 Instructions Compared with RF/RS08 Instructions Input Signal Scaling System Conversion Characteristics LINC Mode Instructions 8 Mode Memory Reference Instructions 8 Mode Group 1 Operate Microinstructions 8 Mode Group 2 Operate Microinstructions 8 Mode Extended Arithmetic Element Microinstructions IOT Instructions AC Bit Functions AC Bit Functions IOT 6154 Effect of Tape Maintenance Instructions Tape Maintenance Instruction Register Equals 10 8 Tape Maintenance Instruction Register Equals 11 8 Tape Maintenance Instruction Register Equals 12 8 Tape Maintenance Instruction Register Equals 13 8 Tape Maintenance Instruction Register Equals 148 Tape Maintenance Instruction Register Equals 15 8 Model 33/35 ASR/KSR Teletype Code (ASCII) in Octal Form Model 33 ASR/KSR Teletype Code (ASCII) in Binary Form 5-35 545 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 3-1 5-3 6-1 6-2 6-3 6-4 6-5 6-6 A-1 B-1 B-2 B-3 B-4 C-1 E-1 E-2 E-3 E-4 E-5 E-6 E-7 E-8 E-9 F-1 F-2 viii 6-10 6-11 6-14 6-35 6-77 6-79 A-1 B-1 B-3 B-3 B-4 C-1 E-1 E-2 E-2 E-3 E-4 E-4 E-4 E-5 E-5 F-1 F-2 TABLES (cont) Table No. F-3 F-4 F-5 F-6 G-1 Title LT-37 Transmit and Receive Code Table Card Reader Codes LP08 Line Printer Code LP12 Automatic Line Printer Code Cable Connections for PDP-12 Front Panel Page F-3 F-5 F-6 F-7 G-2 ix ILLUSTRATIONS Figure No. Frontispiece 1-1 2-1 2-2 2-3 2-4 2-5 2-6 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 5-1 5-2 5-3 x Title PDP-12 Program Data Processor PDP-12 Functional Block Diagram PDP-12 Operator Console Analog Knobs and Power Switch Panel Relay and Analog Input Panel Type VRl 2 CRT Display TU55 Tape Transport Control Panel Teletype Model 33 ASR Assignment of LINC Address within Memory Direct Address Instruction Format {J-Class Instruction Format {J-Class Format a-Class and Non-Memory Reference Format Rotate Left Rotate Right Scale Right QAC Transfer Path Data Path: IB, IF, DF, and AC Data Path, RMF Instruction Special Functions CRT Grid Display Pattern for DSC Relay Terminals and Corresponding AC Bits Standard LINCtape Format LINCtape Processor Information Paths LINCtape Instruction Format Extended Operations Buffer Bit Assignments Organization of Memory, 8 Mode Memory Reference Instruction Format Group I Operate Class Instruction Format Rotation Scheme for RAR, RTR, RAL, RTL Group II Operate Class Instruction Format EAE Instruction Format Shift Path for NMI, SHL Shift Path for ASR Shift Pa th for LSR Data Path to SF and AC Logic Symbols IOT Instruction Decoding Programmed Data Transfer Interface Block Diagram Page 1-2 2-2 2-8 2-10 2-10 2-11 2-13 3-1 3-3 3-4 3-6 3-6 3-17 3-17 3-18 3-22 3-27 3-28 3-29 3-31 3-33 3-36 3-38 3-40 3-41 3-45 4-2 4-3 4-7 4-8 4-10 4-13 4-15 4-16 4-16 4-20 5-3 5-4 5-5 ILLUSTRATIONS (cont) Figure No. Title Page 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 Programmed Data Tt:.ansfer Timing Generation of IOT Command Pulses by Device Selectors Typical Device Selector Use of IOS to Test the Status of an External Device Accumulator Input or Output Loading Data into the Accumulator from an External Device Loading a Six-Bit Word into an External Device from the AC Program Interrupt Request Signal Origin Multiple Inputs to IOS and PI Facilities 5-6 5-7 5-8 5-9 5-10 5-11 5-12 5-12 5-13 5-13 5-1.4 5-15 Illustration of Push and POP Operations 5-13 5-17 5-20 5-16 5-17 5-18 5-19 5-20 5-21 5-22 5-23 5-24 5-25 5-26 5-27 5-28 5-29 5-30 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 Vector Flow Diagram DM12 Cable D~agram Data Break Transfer Interface Single-Cycle Data Break Input Transfer Timing Device Interface Logic for Single-Cycle Data Break Input Transfer Single-Cycle Data Break Output Transfer Timing Device Interface Logic for Single-Cycle Data Break Output Transfer Memory Increment Data Break Timing Three-Cycle Data Break Timing Typical M111 /M906 Positive Input Circuit Typical M516 Positive Bus Receiver Input Circuit Typical M623/M906 Positive Output Circuit M660 Terminated Bus Driver Output Circuit M103 Device Selector Logic Circuit M 101 Bus Data Interface Logic Circuit 1/0 Bus Configuration 1/0 Cable Connections Relationship Between Paper Tape and Accumulator Punched Paper Tape Format for the Number 4 PT08 Equipment Configurations PT08 Program Response Time KW 12-A Real Time Interface KW 12-A Organization Simplified Input Synchronizer Logic Diagram KW 12-A Timing Diagram Automatic Restart Program Events Typical Power Failure Program Service Routine 5-21 5-23 5-24 5-25 5-26 5-27 5-29 5-31 5-31 5-32 5-32 5~33 5-34 540 5-41 6-3 6-4 6-11 6-13 6-18 6-19 6-20 6-21 6-75 6-75 xi - 00 00 PDP· 12 - 1 ' - 2 •. Progr~mmed flata Processor CHAPTER t GENERAL DESCRIPTION 1.1 DESCRIPTION 1.1.1 . System The PDP-12 (Programmed Data Processor-12) is a versatile digital computer which includes within its single central processor two distinct operating modes, each with its own complete instruction set. This versatility of the PDP-12 makes it, on the one hand, a laboratory-oriented machine with several built-in facilities for input/output, auxiliary storage, and control and sensing of external equipment; and on the other hand, a general-purpose computer with a flexible input/output capability to which numerous peripheral devices may be easily attached. The central processor logic is fully parallel, using a basic word length of 12 bits. The processor cycle time is 1.6 microseconds ±20%; most instructions require from 1 to 3 cycles for execution. Like its predecessor, the LINC-8, the PDP-12 operates in one mode as a LINC (Laboratory Instrument Computer) and in the other mode as a PDP-8 computer - specifically, a PDP-8/I. Unlike the LINC-8, however, the PDP-12 has one central processor, and both operating modes have equal status. (In the LINC-8, the LINC mode was subordinate to the PDP-8 mode.) The computer may be stopped and started in either mode, and programs may switch from one to the other at will. Computations in one mode are immediately available to programs operating in the other mode because only one set of processing registers is involved. The PDP-12 is offered in three configurations, A, B, and C, in order of decreasing capability. The two smaller systems, B and C, are expandable into the A configuration. The system discussed in this handbook is the PDP-12A. The capacity of basic core memory storage in the PDP-12 is 4096 ( 4K) 12-bit words which can be expanded to 32,768 (32K) 12-bit words. Figure 1-1 shows a system block diagram with many of the options and peripherals available, such as: LINCtape - Two TU55 tape transports or one TU56 dual drive transport controlled by a buffered subprocessor CRT Display - 6" x 9" screen, two intensification channels Analog Inputs - Eight external inputs, eight variable potentiometers Relay Buffer - Six relays for control of external equipment 1-1 - CARO READER N. r---- - -- ----------- ---, REMOTE VR12 (UP TO r- -1200' BCl2-A EXTENSION : CABLE) 1 r-:-----;-----I BASIC PDP-12 1 EXPANDER CABINETS H961C II I I I I POSITIVE DATA BREAK FACILITY ' POSITIVE ' ~L-~J " 1 I I I UP TO 2 .TRANSPORTS PDP-12A EXISTING OPTIONS 2 T~~ T~~~ I 5 I I I I IERAL EXPANDER VR12 DISPLAY VC12 I js~2;ER;;,, 1/0 BUS 1 I CR12 DBI 2 DC02-E TTY* STATION#2 ~ STATION#! TTY* STATION#O LP12 I p~i'~-iER TTY* STATION#3 LINE PRINTER AD12 m%~2P6~N.fsTAPEI : DWOB-A ADDITIONAL TU56 ' I~MTt~~u~~F I TC12 110 8 DATA BREAK CONV. TC12) NEGATIVE l/O BUS 11 I ""' I TC12-F I I I I T I I KP12 I ADDITIONAL OPTIONS IN SYSTEM CABINET 11 DP12 I XY12 I : I I I I I' II II ~~~~E~Hl:N ONE NEG.BUS MM81-A 00 ''~"" AF01-A A-D DMOl MEMORY MULTIPLEXER** '----~-----' RFOB DISK CONTROL DF32 DISK CONTROL DS32 DISK I I TC 58 MAG. TAPE CONTROL KWl2-A-----1,B,C RSOB DISK UPTO 4 DISK OPTIONS I rLj UP TO 7 DEVICES 2 DISKS PER CABINET MAXIMUM DS32 DISK KT 12 L.___- -___ ___._ - - AF04-A O-A CONVERTER ~ UP TO 32K KE12 1 - - - 1 { DEVICE CONN. TO DATA BREAK FACILITY - - - - - - ...J VP 12 A 12" INCR PLOTTER HOUSTON COMPLOT VP12 Bl2" INCR. PLOTTER HOUSTON COM PLOT VP12 C 30 INCR. PLOTTER HOUSTON COM PLOT DS32 I DISK I L L___________ ----------------~ TU20 TU10 MAGNETIC WITH TAPE UNIT TC5B 1------t•CONTROL MOUN TE TU30 INSIDE UP TO 8 MAGNETIC TAPE TRANSPORTS Figure 1-1. PDP-12 Functional Block Diagram NOTE * TTY OPTIONS AVAILABLE KSR33, ASR33 KSR 35, ASR35 NOTE** DM04 POSITIVE BUS MEMORY MULTIPLEXER ALSO AVAILABLE (DOES NOT REQUIRE DWOB-A) The PDP-12 is also equipped with a positive-logic, PDP-8/1-type, input/output (1/0) bus which can be used for interfacing all 8-family peripherals and options, as well as the standard Teletype® Model 33 ASR. 1.1. 2 Central Processor The central processor contains all the logic and registers required to carry out the functions of both operating modes of the PDP-12. The central processor can best be described in terms of its active registers: Accumulator(AC) 12 Bits This register contains data being operated upon. Its contents may be shifted or rotated right or left; incremented, cleared, or complemented; stored in memory or added to the contents of a memory register; and logically or arithmetically compared with the contents of any memory register. The AC holds the sum after an addition, and part of the product after a multiplication. The AC is also involved in the transfer of data to and from various other registers outside the central processor. Link ( L) 1 Bit The Link is an extension of the AC. When a carry occurs out of AC 00 during a 2's complement addition, the Link is complemented. It may be set or cleared independently of the AC under 8 mode control, and may or may not be included in shifting and rotating operations performed on the contents of the AC. Program Counter (PC) 12 Bits This register contains the address of the next instruction to be executed within the memory field selected by the Instruction Field Register (see below J. In 8 mode, the PC acts as a 12-bit counter; in LINC mode, it acts as a I 0-bit counter. Instruction Register (JR) 12 Bits This register contains the complete binary code of the instruction being executed. Memory Address Register (MA) 12 Bits This register contains the address for memory references. Whenever a core memory location is being accessed, either for reading or for writing, the MA contains the address of that location. Memory Buffer (MB) 12 Bits All information passing between memory and other registers in the PDP-12 must go through the Memory Buffer Register, whether the transfer involves the central processor, an external 1/0 device, or another memory register. Mode Status Register 1 Bit This register indicates the current operating mode (LINC or 8) of the central processor. ®Teletype is the registered trademark of the Teletype Corporation. 1-3 Instruction Field Register (IF) 5 Bits This register selects the memory field containing the executable program. In the LINC mode, it is used to designate one of up to thirty-two 1024-word segments. In the 8 mode, the three high-order bits of the IF are used to designate one of up to eight 4096-word fields. Data Field Register(DF) 5 Bits This register selects the memory field containing data to be indirectly accessed by the memory reference instructions of a program. The fields are specified in each mode in the same way that the IF specifies the Instruction Field. 1.1.3 Memory The principal unit of core memory is a module of 4096 (4K) 12-bit words. Additional modules of 4K words may be added, up to a total of eight, or 32,768 words. Within each module, the logical organization of memory depends on the operating mode. In the LINC mode, each module is divided into four 1024-word segments. At any given time, only two of these segments are active: the Instruction Field, which contains the executable program and the directly accessed data; and the Data Field, which contains only indirectly accessed data. Absolute addresses may be assigned and changed at will using the IF and DF described above. In the 8 mode, the memory field (a 4K module) is divided into 32 pages of 128 words each. Within a single page, data may be accessed directly; between pages, indirect addressing must be used. If more than 4K of memory is provided, the IF and DF registers specify the active fields. 1.1.4 Operating Modes The two operating modes, LINC and 8, are independent of each other, though they can be combined and intermixed within a program. The user can run programs from the already-existing libraries for the 8 family of computers, including the LINC-8. By using the 1/0 Handler (LINC-8 Simulator Trap Processor) program provided with the PDP-12 basic software, most programs written for the LINC-8 can be run without modification. (Some LINC-8 programs may require slight changes.) A complete software system designed for the PDP-12 allows the programmer to assemble coding for either or both modes in a single program. LINC Mode - In this mode, the instruction set of the classic LINC computer is implemented. In addition, several new provisions are available: Extended Tape Addressing - This allows the programmer to transfer information between LINCtape and any section of core, removing the restriction of data transfer to only specific segments of a given memory field. Other features include: a. Tape Interrupt, which connects the tape processor status to the Program Interrupt. b. No-pause, which permits the central processor to resume operation after initiating a tape transfer without waiting for completion. c. Hold-motion, which allows a unit to remain in motion after it has been deselected. I/O Bus Access - In LINC mode the user has immediate access to those devices activated by LINC instructions: analog inputs, Display, Relays, Sense Lines, and LINCtape. Devices connected to the I/O bus may be directly accessed from LINC mode programming by means of a special two-word instruction, in which the second word enables the bus and initiates the PDP-8 IOT timing chain. This second word is interpreted as a standard PDP-8 IOT instruction, but the program continues to operate in LINC mode. 1-4 Special Functions - The LINC programmer may, by setting certain flip-flops, a. Change the size of characters displayed on the CRT; b. Enable the program trap, which intercepts certain LINC instruction codes; c. Disable interrupts from the ASR-33; d. Speed the sampling of analog inputs; e. Clear the PDP-12 1/0 status by generating an 1/0 PRESET pulse. 8 Mode - In this mode, the user has available the entire PDP-8/1 instruction set. Interaction Between Modes - The user may switch from one mode to the other at will. In the LINC mode, execution of the instruction PDP causes the processor to change immediately to 8 mode operation, and all subsequent instructions are interpreted as PDP-8/I instructions. To switch from 8 mode to LINC mode, the IOT instruction LINC is used. 1.1. 5 Input/Output Facilities and Display There are two main paths for the transmission of data from the central processor or memory to peripheral devices. One path, which is controlled by LINC mode programming, leads to the CRT display, LINCtape, A-D converter, and relays. The other path, which is the 1/0 bus, leads to the ASR-33 and to a large number of optional devices, such as plotters, high-speed paper tape, magnetic tape, A-D, and card readers, disk storage, and line printers. Display - The Cathode Ray Tube has a 58.5-square-inch (6.5 x 9 inches) screen, on which individual points and whole characters may be displayed. The unit has two selectable channels, controlled by programming and by a switch on the display. Characters are plotted on a 4-point x 6-point matrix; a full character can be displayed with two instructions. Provision is made for displaying two sizes of characters. Data Terminal - A Data Terminal provides a flexible means of receiving analog inputs and controlling the operation of external equipment not internally interfaced to the PDP-12. Analog Inputs - Sixteen analog inputs feed a 10-bit A-D converter. A single LINC mode instruction samples any one of the 16 channels. Eight of the inputs are taken from phone jacks mounted on the Data Terminal Panel and fed through preamplifiers to the converter. The remaining eight are taken from continuously variable 10-turn potentiometers which are also mounted on the panel. A second set of 16 channels, with preamplifiers, may be added to the basic facility. Relay Buffer - Six relays, mounted on the data terminal panel, can be switched individually or in combination, by means of a LINC mode instruction. The relays may be used to start and stop operations in external equipment. The states of the relays can be read into the AC. Auxiliary Scope Connector - A connector mounted on the Data Terminal Panel is wired to accept an auxiliary CRT for displaying information. All display information (X, Y and Z) available to the internal display is also available at the remote connector. Sense Lines - These 12 digital sense lines may be individually tested with a LINC mode instruction. LJNCtape - Two TU55 transports (or one TU56 dual drive transport) are controlled by a fully-buffered tape processor; once initiated by the LINC program, tape operations are carried out independently of the central processor. Tapes normally are written and read in standard LINCtape format, though nonstandard formats may be used. A special hardware option, TC 12-F, permits the use of tapes with a different format, such as PDP-8 DECtape. In addition to the basic LINCtape commands, the PDP-12 also includes an Extended Operations facility, which 1-5 allows, among other features, the transmission of data between tape and any program-defined area of memory, and the addition of TU55 transports to a total of eight (or four dual drive TU56s). Input/Output (1/0) Bus - This connecting facility provides the control and data transmission path between the central processor and any peripheral device attached to the bus. Some devices, such as paper tape readers and punches, line printers, and incremental plotters, transfer data via the accumulator (AC). Others, including magnetic tape and disk, use the three-cycle or single-cycle Data Break for direct memory access. The 1/0 bus uses positive logic and accepts peripherals used with the 8 family of computers. The processor is prewired to accept the following 1/0 bus options: Extended Arithmetic Element (EAE), Type KE 12 Programmable Real-time Clocks, Type KW 12-A, B, or C Incremental Plotter and Control, Type XY 12 TTY /Data phone®, Type DP 12-A, B With the inclusion of the BAI 2 Peripheral Expander and the DW08A 1/0 and Bus Converter, many other devices can be added to the PDP-12 1/0 bus. The Peripheral Expander allows the addition of high-speed paper tape reader and punch, card reader, line printers, and optional communication interfaces. The Bus Converter provides for the addition of disk and IBM-compatible magnetic tape storage and A/D converters and associated multiplexers designed for the negative-logic PDP-8 1/0 Bus. Keyboard/Printer (Model 33 ASR) - An important means of direct communication between the user and the operating program is the Model 33 ASR Keyboard/Printer, standard on all configurations of the PDP-12. It is connected to the I/O bus, and can be accessed for input or output by programs in either operating mode. The Model 33 ASR is equipped with paper tape reader and punch; the reader and keyboard use the same input path and instructions, while the printer and punch use the same output path and instructions. The maximum transfer rate in either direction is 10 characters per second. The Model 33 ASR operates in full-duplex mode, that is data may be transmitted in both directions simultaneously. 1.2 SYMBOLS AND ABBREVIATIONS The following symbols and abbreviations are used throughout this handbook: AC, MB, PC, MQ, MA, L, IF, DF, IR Central Processor registers: Accumulator, Memory Buffer, Program Counter, Multiplier Quotient, Memory Address, Link, Instruction Field, Data Field, Instruction Register. R General representation of any register. C (R) The contents of register R. The content of bit j of register R. The contents of bits j through n, inclusive, of register R. ® Dataphone is a registered trademark of A.T.&T. 1-6 The contents of the left half of register R. The contents of the right half of register R. C (R) The one's complement of the contents of register R. y The effective address of an operand. I The Indirect address bit of an instruction. In the LINC mode, I represents bit 7; in the 8 mode, bit 3. C (R)-+C (S) The contents of register R replace those of register S. N-+C (R) The quantity N replaces the contents of register R. v Inclusive OR Exclusive OR A AND 1-7 CHAPTER 2 CONTROLS AND INDICATORS This chapter describes the function of the controls and indicators of the PDP-12 computer console, Data Terminal, Type VR12 CRT Display, Type TU55 LINCtape Transport, and Teletype Model 33 ASR. 2.1 PDP-12 CONSOLE CONTROLS AND INDICATORS Tables 2-1 through 2-8 describe the controls and indicators located on the console of the PDP-12. Figure 2-1 provides a front view of the console. 2.2 DATA TERMINAL The Data Terminal is the area behind the door on the left front of the PDP-12. Normally, up to four separate panels are placed here. A storage rack to hold LINC tapes may be placed in any of the unused spaces of the Data Terminal area. The four standard panels are: I. Power Switch Panel 2. Relay and Analog Input Panel 3. Analog Extension Panel 4. Clock Input Panel The first two are described in Tables 2-9 and 2-10 and illustrated in Figures 2-2 and 2-3; the last two are described with the associated options (AG 12 and KWl 2-A). 2.3 CRT DISPLAY, TYPE VR12 Table 2-11 lists the controls and indicators ·of the Type VRl 2 CRT Display. Figure 2-4 shows a front view of ~he CRT Display. 2.4 LINC TAPE TRANSPORT, TYPE TU55 Table 2-12 lists the functions of controls and indicators of the Type TU55 LINCtape transport. Figure 2-5 provides a front view of the transport. 2.5 TELETYPE, MODEL 33 ASR Table 2-13 lists the functions of controls of the Teletype, Model 33 ASR. Figure 2-6 provides a front view of the teletype. 2-1 Q) 0 rJl ~ 0 u .... 0 ~ .... Q) 0.. 0 -~ N i:l. 2-2 Table 2-1. Central Processor Register Indicators Indicator Bits Table 2-2. Central Processor Major State Indicators Indicator State INST FIELD 5 F Instruction Fetch DATA FIELD 5 D Deferred Address RELAYS 6 E Instruction Execution INSTRUCTION REGISTER 12 E2 Instruction Execution 2 PROGRAM COUNTER 12 INT Program Interrupt MEMORY ADDRESS 12 WC Word Count MULTIPLIER QUOTIENT 12 CA Current Address ACCUMULATOR 12 B Break TB Tape Break 1 LINK MEMORY BUFFER 12 Table 2-3. Central Processor Miscellaneous Indicators Indicators Interpretation When Lit SKIP Skip Flip-Flop is set FLO Overflow Flip-Flop is set 8MODE Processor is in the PDP-8 Mode LINC MODE Processor is in the LINC Mode RUN Processor is running AUTO Auto Restart Flip-Flop is set TRAP Trap flip-flop is set INT PAUSE An internal pause is occurring ION Program Interrupt facility enabled I/O PAUSE An 1/0 Pause is occurring 2-3 Table 2-4. Tape Processor Major State Indicators Indicator State I Idle s Search B Block c Check Word T Turn Around Table 2-5. Tape Processor Miscellaneous Indicators Indicator Interpretation Function IP In Progress Indicates that a tape operation is In Progress. XA Extended Address Mode Indicates that the processor is in the Extended Address mode. NP No Pause Mode Indicates that the processor is in the No Pause mode. MK Mark Flip-Flop Indicates that the Mark Flip-Flop is set. 3-bit Tape Instruction Register These three lights indicate the contents of the 3-bit Tape Instruction register. TAPE INST 2-4 Table 2-6. Function of Computer Console Keys Key Function 1/0 PRESET This switch causes the processor to halt when it is in Internal Pause state during a tape instruction, and sets processor mode to the state of the console MODE switch. The Inst Field register is set to 2 and the Data Field register is set to 3. 1/0 PRESET pulse and the 1/0 BUS INITIALIZE pulse clear all 1/0 device flags and operations. The AC and Link are cleared. DO This switch causes the processor to perform one instruction. In the LINC mode, the processor performs the instruction defined by the Left Switches (and the Right Switches, if it is a double word instruction). In the 8 mode, the processor performs the instruction defined by the Left Switches. START 20 This switch causes the processor to start at location 20 of the currently selected Instruction Field. START 400 This switch causes the processor to start at location 400 of the currently selected Instruction Field. START LS This switch causes the processor to start at the 15-bit address specified by the Left Switches and the Instruction Field Switches. CONT This switch causes the processor to resume operation. EXAM The contents of the Left Switches are transferred into the Memory Address register. The contents of the absolute core address designated by the Left Switches are displayed in the Memory Buffer register. STEP EXAM This switch increments the contents of the Memory Address register and displays the contents of this new address in the Memory Buffer register. This incrementing extends over 10 bits in LINC mode and 12 bits in 8 mode. FILL The contents of the Left Switches are transferred into the Memory Address register. The contents of the Right Switches are deposited into the memory location whose absolute address is designated by the Left Switches and the Instruction Field switches. FILL STEP Depressing this switch causes the contents of the Right Switches to be deposited into the memory location whose address is in the Memory Address register. Releasing this switch increments the contents of the Memory Address register. This incrementing extends over 10 bits in the LINC mode or 12 bits in the 8 mode. The Memory Buffer register then displays the contents of the location specified by the new contents of the Memory Address register. MODE This switch determines the mode (LINC or 8) to which the processor will be set when the 1/0 PRESET switch is activated. The MODE switch is effective only when the computer is not running. 2-5 Table 2-6. Function of Computer Console Keys (cont) Key Function AUTO This switch sets the AUTO RESTART flip-flop if it is held down at the same time one of the following keys is actuated: STEP EXAM, FILL STEP, DO, or CONT. The AUTO RESTART flip-flop causes the central processor to start automatically at the end of a variable time delay (determined by the console controls) after the central processor stops for any of the following reasons: a. SING STEP switch activated b. FETCH STOP address match c. EXEC STOP address match d. The end of a STEP EXAM operation e. The end of a FILL STEP operation f. The end of a DO switch operation The Auto Restart Flip-Flop is cleared by any of the following conditions: a. STOP switch pressed while processor is running b. DO, FILL STEP, or STEP EXAM switch activated and the AUTO switch not pressed c. A processor HLT instruction executed (either mode) d. I/O PRESET pulse is generated To start a program in AUTO RESTART mode: a. Start the program with the SING STEP switch up. With the AUTO key depressed, depress CONT. 2-6 Table 2-7. Toggle Switch Registers Register Bits Function LEFT SWITCHES 12 These switches form a 12-bit word which can be read into the accumulator with the LINC mode instruction LSW (517). This word also specifies the address to be examined when the EXAM switch is used, the address in to which data will be placed when the FILL switch is used, the stopping address for EXEC STOP and FETCH STOP functions, and the instruction to be performed when the DO switch is used. RIGHT SWITCHES 12 The contents of these switches form a 12-bit word which can be read into the accumulator with the LINC mode instruction RSW (516) or the 8 mode instruction OSR (7 404 ). This word also provides data to be stored in memory when the FILL or FILL STEP switches are used. When the DO switch is used, the Right Switches contain the second word of two-word instructions. INST FIELD 3 These are a high-order extension of the Left Switches. They provide addressing information for systems equipped with 8K or more of memory for the EXAM, FILL, START LS, EXEC STOP, and FETCH STOP functions. SENSE SWITCHES 6 These switches are individually interrogated by LINC mode skip instructions, thereby enabling console control of program branching. Table 2-8. Individual Console Toggle Switches Switch Function STOP This switch causes the processor to stop at the end of an instruction. For the purposes of the STOP switch, Traps, Interrupt, Tape Break, and single-cycle Data Break are considered to be single-cycle instructions. During a three-cycle Data Break, the processor is stopped after the Break cycle. SING STEP This switch causes the RUN flip-flop to be cleared, thereby disabling the timing circuits at the end of one cycle of operation. Thereafter, repeated operation of the CONT switch steps the program one cycle at a time so that the operator can observe the contents of registers in each major state. FETCH STOP This switch causes the processor to stop when the address designated by the Left Switches matches the current address in the Memory Address register during the Fetch cycle. For systems with more than 4K of memory, the Inst Field switches designate the three most significant bits of the address. 2-7 Table 2-8. Individual Console Toggle Switches (cont) Switch EXEC STOP Function This switch causes the processor to stop when the address designated by the Left Switches matches the current address in the Memory Address register during any computer cycle except a Fetch cycle. For systems having more than 4K of memory, the Inst Field switches designate the three most significant bits of the address. Figure 2-2. Analog Knobs and Power Switch Panel 2-8 Table 2-9. Analog Knobs and Power Switch Panel Panel Controls Function OFF /ON/LOCK This 3-position, key-locking switch is used to turn the PDP-12 on as well as inhibit console intervention during an operating program. When fully counterclockwise, the PDP-12 is off. When turned to the center position, the PDP-12 is turned on and the console activated. When the switch is fully clockwise, the PDP-12 is on, but console control functions are totally inhibited while the PDP-12 RUN light is on. Only the Left Switches, Right Switches, and Sense Switches remain operative. SPEAKER VOLUME The volume of the speaker is controlled by this knob. (The speaker, which is driven by AC bit 0, is added to the system when the AD 12 is included in the system configuration.) AUTO RESTART DELAY These two knobs control the delay period of Auto Restart after a processor stop due to an EXEC STOP, FETCH STOP, or SING STEP operation. (See AUTO switch description in Table 2-6.) COARSE and FINE ANALOG CHANNELS 0-7 (knobs) The COARSE delay selects overlapping ranges from 2.4 µs to .38 sec. The FINE control gives variation within a range of 20: 1 of the selected COARSE delay. These 10-turn potentiometers are connected to analog input channels 0-7 of the AD 12 Analog-tcrDigital Converter. These knobs therefore provide eight continually-variable parameters within the range of ±512 1 0 for program usage. Table 2-10. Relay and Analog Input Panel Terminals Function ANALOG CHANNELS 10-1 7 (Input Jacks) These are 3-conductor phone jacks providing± 1 Volt input connections for AD 12 Analog-to-Digital converter channels 10 8 -17 8 . RELAY REGISTER Contacts One set of form C contacts for each of the six system relays is available at the binding posts. EXTENSION SCOPE A 24-pin connector for an extension scope provides for remote operations, multiple displays, or photographing of display output. See Appendix G for pin connections and drive characteristics. 2-9 Figure 2-3. Relay and Analog Input Panel Figure 2-4. Type VR 12 CRT Display 2-10 Table 2-11. VR 12 Display Scope Controls Control Function CHANNEL Selects one or both channels for scope display. BRIGHTNESS Controls level of brightness. X GAIN Controls horizontal size of display. X POS Controls horizontal position of display. Y GAIN Controls vertical size of display. Y POS Controls vertical position of display. Figure 2-5. TU55 Tape Transport Control Panel 2-11 Table 2-12. TU55 Tape Transport Controls and Indicators Control or Indicator Forward Tape-motion Switch (designated in Figure 2-5 by arrow pointing to the left) Function Provides forward tape motion (i.e., from right to left) only if REMOTE/OFF /LOCAL switch is set to LOCAL. WRITE ENABLED/WRITE LOCK switch WRITE ENABLED Permits TCl 2 control system to write information on the TU55. WRITE LOCK Prevents writing. If TC 12 control system is commanded to write on tape while the WRITE LOCK is set, the control signals a TAPE NOT OK. WRITE ENABLED Lights when WRITE ENABLE/WRITE LOCK switch is in the WRITE ENABLE position. Unit Selector When this selector is dialed to one of the numerals and the REMOTE/OFF /LOCAL switch is set to REMOTE, the central processor may gain access to the unit. 0 I 2 3 4 5 6 7 OFF LINE When the selector is dialed to OFF LINE, the transport cannot be selected by the tape control. NOTE Some earlier units were equipped with a unit selector position 8, which is the same as unit 0. REMOTE/OFF /LOCAL Switch 2-12 REMOTE Permits tape processor to control the transport. OFF Removes power from reel motors and releases the brakes. This permits the operator to change the tape. Table 2-12. TUSS Tape Transport Controls and Indicators (cont) Control or Indicator Function LOCAL Permits the forward and reverse tape-motion switches to provide tape motion in direction of the arrows. The transport cannot be selected. REMOTE Indicator Lights only when transport is selected by the tape processor. Reverse Tape-motion Switch (designated in Figure 2-5 by arrow pointing to the right) Provides for motion in the reverse direction (i.e., from left to right), but only when REMOTE/OFF I LOCAL switch is on LOCAL. If both reverse and forward tape-motion switches are pressed simultaneously, reverse motion takes place. Figure 2-6. Teletype Model 33 ASR 2-13 Table 2-13. Teletype Model 33 ASR Controls Control Function Punch Controls REL Pushbutton Disengages the tape in the punch to allow removal or loading. B SP Pushbutton Backspaces the tape in the punch one space, allowing manual correction or rubout of the character just punched. ON and OFF Pushbuttons ON engages the punch for operation under local or program control. OFF removes the punch from control. Reader Control 2-14 ST ART /STOP /FREE In the FREE (lowest) position, the tape feed wheel is disengaged, and tape can be loaded or unloaded. In the STOP (center) position, the wheel is engaged but the reader cannot be operated. In the START (highest) position, the reader can be operated under local or program control. LINE/OFF /LOCAL Switch In the LINE position, the Teletype is energized and connected as an 1/0 device to the computer. In the OFF position, the Teletype is not energized. In the LOCAL position, the Teletype is energized for off-line operation, and signal connections to the processor are disconnected. Both LINE and LOCAL use of the Teletype require that the computer OFF/ON/LOCK switch is ON. CHAPTER 3 LINC MODE PROGRAMMING 3.1 ORGANIZATION OF MEMORY 3 .1.1 General The LINC mode instruction set deals with two 1024 10 -word Memory Fields. The INSTRUCTION FIELD is the 1024 1 0 -word section of memory from which programs are executed, and in which data may be directly or indirectly accessed. The DAT A FIELD is a second 1024 1 0 -word section of memory to which the LINC instruction set allows only indirect reference for data manipulation and storage. The physical locations of the Data Field and Instruction Field within the maximum 32,768 10 -word memory are specified by the contents of the 5-bit Data Field Register and the 5-bit Instruction Field Register. These are set and modified under program control or from the console; they need not be adjacent, or in any particular order, and can even be identical. With respect to a LINC program, addresses within a Field remain constant, regardless of the actual location of the Field. Addresses within the Instruction Field are 0000 through 1777 8 ; addresses within the Data Field are 2000 8 through 3777 8 . Thus, no matter where they are assigned, the two fields may be considered logically contiguous. The PDP-8 instruction set (described in Chapter 4) divides memory into 4096 1 0 -word Fields, which are specified by the most significant 3 bits of the Instruction Field and Data Field Registers. Therefore, the term Field designates a l 024 10 -word segment of memory in LINC mode, and a 4096 1 0 -word segment of memory in 8 mode. In Figure 3-1, the division of the first 4096 1 0 words of memory is shown, assuming LINC mode, INST FIELD = 01, DATA FIELD= 03. ABSOLUTE ADDRESS (OCTAL) FIELD LINC ADDRESS (OCTAL) 0000-1777 2000-3777 4000-5777 INST 0000-1777 6000-7777 DATA 2000-3777 , 2-0176 Figure 3-1. Assignment of LINC Addresses within Memory 3-1 3.1. 2 Program Counter The Program Counter acts as a 10-bit counter in the LINC mode, so that executable programs can be stored only in the Instruction Field. If the contents of PC 2 - 11 are incremented beyond 1777, they return to 0000; the two high-order bits of the PC are unaffected. Thus, incrementing C(PC) = 3777 yields C(PC) = 2000. Likewise, 5777 is incremented to 4000, and 7777 to 6000. This 10-bit indexing is very common in LINC mode operations. 3.1.3 Instruction and Data Field Registers These two 5-bit registers select the 1K segments to be used by the LINC program. The three high-order bits of each register are the three bits of the corresponding 8 mode Memory Field register. The contents of the IF and DF may be set, changed, or examined at any time by the use of LINC instructions. 3.1.3. l Instruction Field Reserved Locations - This field contains the executable program. The following registers are set aside in this field for special uses: Field Address Use 0000 Holds return address after execution of JMP. 0001 Holds horizontal coordinate during execution of DSC. 0001-0017 As [3-registers, used by indirect-reference instructions to hold the effective address of an operand. 0000-0017 As a-registers, used by SET, XSK, and DIS. 0020 Program start location when Start 20 key is pressed. 0400 Program start location when Start 400 key is pressed. When the instruction field is assigned to the lowest segment of memory (that is, when C(IF) = 00), the following registers are also reserved: Field Address Use 0000 0001 PDP-8 Interrupt locations (Paragraph 4.4) 0040 Holds return address after a program interrupt during LINC mode operation. 0041 Location to which control is transferred after a program interrupt during LINC mode operation. 0140 Holds return address after an instruction trap. 0141 Location to which control is transferred after an instruction trap. 3.1.3.1 Data Field Reserved Locations - There are no specially-reserved registers in this field. Its contents cannot be accessed directly; data.can be stored or retrieved only by indirect addressing. 3-2 3.2 MEMORY ADDRESSING METHODS 3. 2.1 General Almost every program, at some time during its execution, will need an item of data stored in memory. Such an operand can be obtained only by specifying the address of the register in which it is stored or to be stored. An instruction which requires a reference to memory can designate the desired location in two ways. It may include the address of the operand as part of the instruction itself and directly address the location of the operand. Or, the instruction may specify the address, not of the operand, but of a register containing the address of the operand, thus indirectly addressing the data storage register. The need for indirect addressing is readily apparent; with eleven bits required to specify a Data Field address, not much is left of a 12-bit word to use for instruction codes. It is necessary to reduce the number of address bits available within a memory reference instruction, and to use a limited set of directly addressable locations as pointers containing the effective address of the desired data. The LINC instruction set provides for both types of addressing. 3.2.2 Direct Addressing In LINC programming, direct access to memory registers is limited to the Instruction Field. A full address in this field requires ten bits (0000-1777), leaving only two bits for instruction codes. The three instructions, ADD, STC, and JMP, are described in detail in Paragraph 3.3. The format of a direct-address instruction is shown in Figure 3-2. Bits 0 and 1 are used for the operation code, bits 2-11 for the address. OPERATION CODE ADDRESS _ _J...___~~~~~~~~~~-A-~~~~~~~~~~ ~--y '\ 4 5 6 7 8 9 10 11 Figure 3-2. Direct Address Instruction Format 3.2.3 Indirect Addressing: {3-Class For access to registers in the Data Field, an indirect address is required. The instruction specifies one of a small set of special registers which are used to hold the effective addresses of desired data. The format of these /3-class instructions is shown in Figure 3-3. Bits 3-6 are available for operation codes; bits 8-11, together with bit 7, determine which of four addressing schemes is to be used. 3-3 0 ~ OPERATION CODE ~~~--A-~~~-, 3 4 5 6 p 7 8 9 10 11 . "-y-) Figure 3-3. {3-Class Instruction Format 3.2.3.1 .(3-Registers - In a .(3-class instruction, the contents of bits 8-11, when not zero, designate one of fifteen registers at locations 0001-0017 of the Instruction Field. The contents of the specified .(3-register are used to determine the effective address of the operand. When the contents of bits 8-11 are zero, the effective address is found in the register which immediately follows the referencing instruction. Bit 7, the I-Bit, determines the manner in which the register designated by bits 8-11 is to be used in locating the operand. There are four addressing schemes, described in the following table. Bit 7 (I) Bits 8-11 (.(3) 0 00 The contents of bits 1-11 of the immediately following the instruction. 00 The address of the register immediately following the instruction. The operand itself is in this register. 01-17 The contents of bits 1-11 of the designated {3-register. 01-17 The contents, incremented by 1, of bits 1-11 of the designated 13-register. Ten-bit indexing is used (see text). 0 Effective Address register In the first scheme, the register which follows the referencing instruction contains the effective address. In the second scheme, the operand itself is in that register. When either of these two schemes is used (that is, when the contents of bits 8-11 are zero), the program counter automatically skips over the register immediately following the instruction, and the next instruction is fetched from the second register following. The following examples illustrate the use of all four addressing schemes. The instruction STA (Store Accumulator) causes the contents of the AC to be stored in memory. The operation code for STA is 1040. The register R is the one which immediately follows that containing the STA instruction. (1) STA 0 3-4 Octal code: 1040 I=O, {3=00 Destination of C(AC): C(R)=2345 Location 2345 (Location 345 in the Data Field) Octal code: 1060 I=l, ,B=OO Destination of C(AC): (2) STA I 0 (3) STA 12 (4) STA I 12 Location R Octal code: 1025 I=O, ,6=12 Destination of C(AC): C(OOl 2)=3456 Octal code: 107 2 I=l, ,B=l 2 Destination of C(AC): C(OOl 2)=3456 Location 3456 (Location 1456 in the Data Field) Location 3457 (Location 1457 in the Data Field) (The contents of ,B-register 0012 are incremented by 1, and the result, 3457, is used as the effective address.) In the next example, the use of these addressing schemes in a program sequence is demonstrated. The instruction ADA (Add to Accumulator) adds the operand to the contents of the AC, leaving the result in the AC. The program sequence .~tarting at location l 000 adds the numbers N 1 , N2 , N3 , and N4 , leaving the sum in the AC. ADDRESS OCTAL CONTENTS 0007 1500 1500 REMARKS /REPLACED BY 1501 AFTER INDEXING *1000 1000 1100 ADA /INDIRECT THROUGH 1001, ADD Nl to C(AC) 1001 1477 1477 ADA /ADDRESS OF Nl 1002 1120 1003 3211 1004 1107 ADA 7 /INDIRECT THROUGH 7 TO 1500, ADDS N3 1005 1127 ADA I 7 /INDIRECT THROUGH 7, INDEXED, ADDS N4 1477 1234 NI, 1234 1500 1235 N3, 1235 1501 4321 N4, 4321 N2, /DIRECT TO 1003; ADDS N2 TO C(AC) 3211 *1477 3.2.3.2 ,B-Register Indexing - When the ,B-indexing scheme is used (I= 1, ,B =I= 00), effective addresses may specify registers in either memory field, but the ,B-register cannot be incremented from one field to the other. Indexing is only over ten bits, as it is in the PC; the two high-order bits are unaffected. Thus, the contents of the ,B-register will be incremented from 1777 to 0000, from 3 777 to 2000, from 5777 to 4000, and from 7777 to 6000. To change access from one field to the other, it is necessary to change the contents of bit 1 of the ,B-register. 3-5 Bit 0 of the J3-register has no effect in most indirect references, but it does have a special use in half-word operations, in multipiication, and in character display. 3.2.4 Addressing: a-Class Three LINC mode instructions - SET, XSK, and DIS - have specialized memory reference schemes. Although each of them accesses memory in a unique way, all make use of one of the registers in locations 0000 through 0017. These are called a-registers, to differentiate between these instructions and those of the ,8-class. SET and XSK are described in Section 3.3. DIS is described in Section 3.4. 3.3 LINC MODE INSTRUCTIONS (Complete list is provided in Appendix A.) 3.3.1 Instruction Formats There are three basic LINC mode instruction formats. 3.3.1.1 Direct Address (See Figure 3-2) - This class consists of the three instructions ADD, STC, and JMP. 3.3.1.2 Indirect Address, (3-class (See Figure 3-4) - This class consists of 15 (3-class instructions, with operation codes between 1000 and 1740. OPERATION 0 r--- p CODE _ _ _ ___,A _ _ _ __ ~ ( ~ \ 4 5 6 7 8 9 10 11 Figure 3-4. (3-Class Format 3.3.1.3 a-class and Others (See Figure 3-5) - There are 16 basic instructions in this group, and they have operation codes between 0000 and 0777. Each of these instructions has up to 32 variants, depending on the contents of bits 7-11. ALL ZEROS I r_ _ _ _A_ _ _ _\ 0 2 ~ 3 ' 4 5 y OPERATION CODE 9 l ' 10 y l OPERATION CODE, Q - REGISTER OR FUNCTION DESIGNATORS Figure 3-5. a-Class and Non-Memory Reference Format 3-6 ,, 3.3.2 Instruction Descriptions The descriptions are organized according to function and class, as follows: Full-word Data Transfers Full-word Arithmetic Full-word Logic Full-word Comparison Half-word Operations a-class Operations Program Control Shift and Rotate Skips Miscellaneous Console Switches Mode Control Switch 1/0 Bus Enable Memory Address Control Program Interrupt Special Functions STC, LDA, STA ADD,ADA,ADM,LAM,MUL BCL, BSE, BCO SAE, SRO LDH, STH, SHD SET,XSK JMP ROL, ROR, SCR APO, AZE, LZE, QLZ, FLO, SNS, SXL,KST,SKP,STD,TWC HLT,CLR,COM,NOP,QAC LSW, RSW PDP IOB LIF, LDF, IOB/IOTs IOB/IOTs, DJR ESF, SFA Instructions related to the Display, Data Terminal, and LINCtape are described in Sections 3.4, 3.5, and 3.6. In general, the description of each instruction is presented in the following manner: Mnemonic Form Octal code Execution time Operation Operation Performed The second line shows the general form of the instruction when used in a program. The octal code is that of the instruction itself, plus the octal value of any other elements which may be present, such as the I-bit or '3-register bits. (The I-bit, for example, being represented by bit 7, has an octal value of 20 when it is present.) 3.3.3 Full-Word Instructions 3.3.3. l Full-Word Data Transfers Accumulator and Memory. STC These three instructions move complete 12-bit words between the Store and Clear (Direct Address) Form: Octal code: Execution time: Operation: STC Y 4000+ y 3.2 µs Store the contents of the AC in register Y, then clear the AC. This is a direct address instruction; Y must be in the Instruction Field. 3-7 LDA Load Accumulator ((3-Class) Form: Octal code: Execution time: Operation: STA LDA I (3 1000 + 20I + (3 4.8 µs; 3. 2µs. when I = 1 and {3 = 00 Place the contents of register Y, where Y is the address specified by I and C({3), in the AC. The previous contents of the AC are lost; the contents of Y are unchanged. Store Accumulator ((3-Class) Form: Octal code: Execution time: Operation: STA I {3 1040 + 201 + (3 4.8 µs; 3. 2 µs. when I = 1 and {3 = 00 Store the contents of the AC in memory register Y, where Y is the address specified by I and C({3). The previous contents of Y are lost; the contents of the AC are not changed. 3.3.3.2 Full-Word Arithmetic - The instructions ADD, ADA, and ADM use one's complement arithmetic. If, as a result of an addition, a 1 is carried out of bit 0 of the sum, 1 is added to the sum. This end-around carry is the defining property of a one's complement addition. If there is no carry, the sum is left as is. Example 1: 2435 +1704 4341 Example 2: no carry; sum is left as is. 2435 +5704 (-2073) c1 ~4! end-around carry; 1 added to sum. 0342 In either case, the Link is not affected. The instruction LAM uses two's complement arithmetic. If a carry from bit 0 of the sum occurs, the Link is set to 1; the sum is left unaffected. 3.3.3.2.1 Overflow - In any LINC mode addition, a number is considered to be positive if its high-order bit (bit 0) is 0, and negative if this sign bit is 1. Whenever two addends of like sign produce a sum of opposite sign, overflow is said to occur. When this happens, the FLOW flip-flop is set to 1. If no overflow occurs, the FLOW flip-flop is set to 0. Overflow cannot, by definition, occur when the addends have unlike signs. Note that overflow and carry are not the same thing. 3.3.3.2. 2 Instructions ADD Add to Accumulator (Direct Address) Form: Octal code: Execution time: Operation: 3-8 ADD Y 2000 + y 3.2 µs The contents of register Y are added to the contents of the AC, using one's complement addition; the sum is left in the AC. The previous C(AC) are lost; the Link and C(Y) are not changed. ADA Add to Accumulator ({3-Class) Form: Octal code: Execution time: Operation: ADA I {3 1100 + 201 + {3 4.8 µs; 3.2 µs. when I= 1 and {3 = 00 The contents of register Y, as specified by I and C(/3), are added to the contents of the AC, using one's complement addition; the sum is left in the AC. The previous C(AC) are lost; the Link and C(Y) are not changed. ADM Add to Memory ({3-Class) Form: Octal code: Execution time: Operation: ADM I {3 1140 + 201 + {3 4.8 µs; 3. 2 µ.s. when I = 1 and (3 = 00 The contents of register Y, as specified by I and C((3), are added to the contents of the AC, using one's complement addition; the sum is left in both the AC and Y. The previous contents of both registers are lost; the Link is not changed. LAM Link Add to Memory ({3-Class) Form: Octal code: Execution time: LAM I {3 1200 + 201 + {3 4.8 µs; 3.2 µ.s. when I = 1 and (3 = 00 NOTE This description presents the logical sequence of events; in practice, the operations are carried out simultaneously. Operation: The contents of the Link are added to the contents of the AC, using two's complement addition; the sum is left in the AC. If there is a carry out of bit 0, the Link is set to 1; if not, the Link is cleared. Next, the contents of register Y, as specified by I and C((3), are added to the new contents of the AC, again using two's complement addition; the sum is left in both the AC and Y. If there is a carry from bit 0 this time, the Link is set to I; if not, the Link is unchanged. C(AC) = 3743 Example: (1) (2) Results: C(AC) +C(L) C(AC) + 3743 1 3744 3744 +6517 1 2463 C(AC) C(Y) C(L) C(Y) = 6517 C(L) = 1 no carry; Link is cleared. carry; Link is set to 1. 2463 2463 3-9 MUL Multiply ({3-Class) Form: Octal code: Execution time: Operation: MUL I f3 1240 + 20I + f3 9.6 µs; 8 µs. when I= 1 and f3 = 00 The contents of the AC (multiplicand) are multiplied by the contents of register Y (multiplier). The product is left in the AC and the MQ. The sign of the product appears in the Link and AC 0 . The multiplier and multiplicand are treated as 12-bit one's-complement numbers. If bit 0 of an operand is set to 1, the operand is negative. The sign of the product is always correct; that is, operands of like sign give a positive product, and operands of unlike sign give a negative product. Overflow cannot occur; the FLOW flip-flop is not affected by multiplication. Either integer or fractional operands may be specified, as follows: if bit 0 of the designated {3-register contains a 0, the operands are treated as integers; the binary points of both multiplier and multiplicand are considered to be to the right of bit 11. If C(f3 0 ) = 1, the operands are taken as fractions; the binary points are considered to be between bit 0 (sign) and bit 1. Note that when I = 1 and f3 = 00, there is no effective address. In this case, integer multiplication is performed. When integer multiplication is performed, the low-order 11 bits of the product appear in AC 1 _11 and the absolute value of the low order 11 bits of the product appears in MQ 0 _ 1 0 . The sign appears in AC 0 and the Link. The high-order bits of the product are lost. When fractional multiplication is performed, the high-order 11 bits of the product appear in AC 1 -i 1 and the absolute value of the low-order bits appears in bits MQ 0 - 1 0 . The sign appears in AC 0 and the Link. The contents of the MQ can be accessed by using the QAC instruction (see Paragraph 3.3.11 ). Examples: (1) (all octal form) Integers (a.) (b.) (c.) 3-10 0432 x0006 00003234 C(AC) C(Y) product 2764 x0153 00476374 2764 x7624 77301403 (= -153) (= -00476374) C(AC)=3234 C(MQ)=6470 C(AC)=2374 C(MQ)==4770 C(AC)=5403 (= -3154) C(MQ)=4770 (2) Fractions (a.) (b.) (c.) 0432 x0006 00003234 C(AC) C(Y) product C(AC)=OOOO C(MQ)=6470 2764 x0153 00476374 C(AC) C(Y) product C(AC)=Ol 17 C(MQ)=4770 2764 x7624 77301403 C(AC) C(Y) (-00476374) C(AC)=7660 C(MQ)=4770 3.3.4 Full-Word Logic In each of these Boolean functions, the operation is performed between corresponding bits of the AC and the operand, independent of the other bits in either word. BCL Bit Clear ({3-Class) BCL I {3 1540 + 201 + {3 4.8 µs; 3.2 µs. when I= 1 and {3 = 00 For each bit of the operand that is a 1, the corresponding bit of the AC is cleared to 0. For each operand bit that is a 0, the corresponding AC bit is unchanged. The operand is not changed. The following truth table gives the relationship between the corresponding bits, with the results of the comparison. Form: Octal code: Execution time: Operation: 0~01 I C(Yj) The Boolean statement of this relation is AC A Example ESE 0 0 Y. C(AC)=2307 C(Y) =1616 Result:=2 l 0 I 010011000111 001110001110 010001000001 Bit Set ({3-Class) Form: Octal code: Execution time: Operation: BSE I {3 1600 + 201 + {3 4.8 µs; 3. 2 µs. when I = 1 and {3 = 00 For each bit of the operand that is a 1, the corresponding bit of the AC is set to 1. For each operand bit that is 0, the corresponding AC bit is not changed. The operand is not affected. The truth table for this relation, which is the familiar inclusive OR, is as follows: 3-11 0 The Boolean statement of this relation is AC VY. Example C(AC)=2307 010011000111 001110001110 011111001111 C(Y) =1616 Result:=3717 BCO Bit Complement ((3-Class) Form: Octal code: Execution time: Operation: BCO I (3 1640 + 201 + (3 4.8 µs; 3.2 µ.s. when I= 1 and (3 = 00 For each bit of the operan_d that is a 1, the corresponding bit of the AC is complemented. For each operand bit that is 0, the corresponding AC bit is unchanged. The operand is not changed. The truth table for this relation, which is the exclusive OR, is as follows: 0 The Boolean statement of this relation is AC¥-Y. Example C(AC)=2307 C(Y) =1616 Result:=35 I I 010011000111 001110001110 011101001001 3.3.5 Full-Word Comparison In both of these operations, the next succeeding memory location in the program sequence is skipped if the stated condition is met. When (3 =I= 00, this presents no unusual circumstance. When (3 = 00, however, the memory location immediately following the skip instruction contains either the operand itself or its address. When such is the case, this location is automatically skipped, and the one beyond that is considered to be the next location in the program sequence. If a skip occurs under these conditions, the program will proceed from the third location following the skip instruction. SAE Skip If Accumulator Equal To Operand ((3-Class) Form: Octal code: Execution time: Operation: 3-12 SAE I {3 1440 + 201 + (3 4.8 µs; 3.2 µs. when I= 1 and (3 = 00 If the· contents of the Accumulator are equal to the contents of Y (where Y is specified by I and {3), the next instruction in the program sequence is skipped. Otherwise, the program continues without skipping. The contents of the AC and of Y are not changed. SRO Skip and Rotate Fann: Octal code: Execution time: Operation: Example: ADDRESS 0020 0021 0022 0023 (~-Class) SRO I {3 1500 + 201 + (3 4.8 µs; 3.2 µs. when I= 1 and {3 = 00 If bit 11 of the operand is 0, the contents of Y (that is, the operand) are rotated right one place and the next sequential instruction is skipped. Otherwise, the program proceeds without skipping. OCTAL 1520 3725 0016 0016 P, Pl, P2, P3, CONTENTS *20 SRO I 0 3725 NOP NOP REMARKS /THE OPERAND IS IN REG 21 /OPERAND BIT 11=1, SO NO SKIP /PROGRAM CONTINUES FROM HERE After the test is performed, the contents of Pl are rotated right one place; the result, which is retained in Pl, is 5752. If the instruction in register P were then to be executed again, the skip would occur, because the new contents of bit 11 of Pl equal 0. The program would then proceed from register P3, skipping the instruction in P2. 3.3.6 Half-Word Operations 3.3.6.1 Half-Word Addressing - The three instructions, LDH, STH, and SHD, operate on either half of a memory register, independent of the other half. The addressing scheme is basically that of other (3-class instructions, with the following difference: whenever bit 0 of the register containing the effective address holds a 0, the left half of the addressed operand is used; when bit 0 contains a 1, the right half is used. In either case, the data is transferred or compared between the designated half of the operand and the right half of the AC. The following examples demonstrate the effects of half-word addressing. The instruction LDH transfers the designated half of the operand into the right half of the AC; the left half of the AC is cleared. a. LDH 0 I = 0, (3 = 00. C(R) = 0370. (R is the register following LDH). The effective address is 0370. Because C(Ro) = 0, the contents of the left half of register 0370 are placed in the right half of the AC, and the left half of the AC is cleared. b. LDH 12 I = 0, {3 = 12, C(OO 12) = 43 70. Bit 0 of {3-register 12 contains a 1 ; therefore, the contents of the right half of register 03 70 are placed in the right half of the AC, and the left half of the AC is cleared. c. LDH I 0 I = I, {3 = 00. C(R) = 6527. This is a direct reference, so that there is no explicit effective address. In this case, the left half of the operand in register R is taken. In the example, the quantity 65 is placed in the right half of the AC, and the left half of the AC is cleared. d. LDH I 12 I= 1, {3 = 12. C(0012) = 0370. The effective address (that is, C(0012)) must be incremented before it is used. Instead of 1, however, 4000 is added to the contents of the {3-register (remember that the half-word indicator is in bit 0). Given the conditions specified above, the contents of {3-register 12 are first augmented from 0370 to 4370, and the right half of the operand in register 0370 is taken. If a second LDH I 12 is then executed, the {3-register is again incremented by 4000. The sum, which leaves C({3 0 )=O, results in a carry out of the high-order bit. The carry causes 1 to be added to the sum, resulting in a final effective address of 0371. The new operand is then taken from the left half of the new register. The indexing sequence is thus: left half, right half, left half of the next succeeding register, etc. Because the basic indexing scheme is operative only over bits 2-11 of the {3-register, half-word addressing proceeds from the right half of register 1777 to the left half of register 0000, and from the right half of register 3777 to the left half of register 2000. C({3) are thus incremented from 1777 to 5777 to 0000, and from 3777 to r/77 to 2000. 3-13 NOTE Another way of looking at the half-word indicator may help clarify this method of addressing. If the indicator is considered to be just to the right of bit 11, rather than in bit 0, it becomes apparent that half-word indexing is just like full-word indexing, with 1 added to the low-order bit (that is, the half-word indicator) each time. You can, if you like, imagine a binary point between the half-word indicator and bit 11 of the ,B-register, so that successive addresses might be read as 0370, 0370 1/2, 0371, 0371 1/2, 0372, etc. (Or, in octal, 0370.0, 0370.4, 0371.0, 0371.4, 0372.0, etc.) LDH Load Half Form: Octal code: Execution time: Operation: STH Store Half Form: Octal code: Execution time: Operation: SHD LDH I ,B 1300 + 201 + ,B 4.8 µs; 3.2 µs when I= 1 and ,B = 00 The contents of the designated half of register Y (where Y is specified by I and C(jJ)) are placed in the right half of the Accumulator. The left half of the AC is cleared. The previous C(AC) are lost. The contents of Y are not changed. STH I ,B 1340 + 201 + ,B 4.8 µs; 3.2 µs when I= 1 and ,B = 00 The contents of the right half of the Accumulator are stored in the designated half of register Y. The contents of the AC and of the other half of Y are not disturbed. Skip If Half Differs Form: Octal code: Execution time: Operation: SHD I ,B 1409 + 201 + ,B 4.8 µs; 3.2 µs when I= 1 and ,B ~ 00 If the contents of the designf}ted half of register Y are not equal to the contents of the right half of the AC, the next instruction in the program sequence is skipped; otherwise, the program proceeds without skipping. The contents of Y and of the AC are not changed. As in the other ,B-class skips (SAE, SRO), the register immediately following the SHD is automatically passed over when (3 = 00. 3.3. 7 a-Class Operations Each of these instructions uses the registers 0000-0017 in a unique way. A third a-class instruction, DIS, is described in Paragraph 3.4, CRT Display. SET Set a-Register Form: Octal code: Execution time: Operation: SET I a 0040 + 201 +a 6.4 µs; 4.8 us when I = 1 The contents of the a-register specified by bits 8-11 of the SET instruction are replaced by the operand, whose location is determined by the state of the I-bit, as follows: If I = 1, the operand is in the register immediately following that containing the SET instruction. 3-14 If I = 0, the effective address of the operand is in the register immediately following that containing the SET instruction. SET always requires two successive locations; the program always continues from the second register following, as in this example: Address Contents SET I 15 2537 p p+l p+2 Action /THE OPERAND IS IN REGISTER p+ 1 /OPERAND 2537 IS STORED IN REGISTER 15 /PROGRAM CONTINUES FROM THIS REGISTER The previous contents of the a-register are lost. The AC is not disturbed, and the contents of the register containing the operand are not changed. XSK Index and Skip Form: Octal code: Execution time: XSK I a 0200 + 201 +a 3.2 µs Operation: If I = 1, the contents of the designated a-register are incremented by 1, using 10-bit two's complement addition as in ~class indexing. If I = 0, a is left undisturbed. Then if the contents of bits 2-11 of the a-register are equal to 1777, the next instruction in the program sequence is skipped. Otherwise, the skip does not occur. When C(a) are incremented, the two high-order bits are not affected. Thus, 1777 is incremented to 0000, 3777 to 2000, etc. 3. 3. 8 Program Control IMP Jump Form: Octal code: Execution time: Operation: JMP y 6000+Y 3.2 µs when Y -=I= 0000; 1.6 µs when Y = 0000 The quantity Y is placed in PC 2 _1 i , and the next instruction is taken from register Y. The program proceeds from that point. If Y -=I= 0000, the 10-bit address of the register immediately following the JMP instruction (i.e., the contents of the Program Counter) is stored in location 0000 of the Instruction Field as a JMP instruction. This permits the JMP to be used not only as an unconditional transfer of program control, but also as a subroutine calling instruction. If Y = 0000, the jump is executed, but nothing is stored in register 0000. JMP 0 is used to return from a subroutine, as shown in the example. 3-15 Example ADDRESS OCTAL 0000 0000 0001 0000 0175 0176 0177 0016 0000 0000 0242 0243 0244 6000 0000 0000 0572 0573 0574 0575 CONTENTS 0000, 6175 0017 0000 0000 *0000 0000 *0175 NOP REMARKS /WILL CONTAIN 6573 AFTER JMP 175 IS /EXECUTED /START OF LINEAR SUBROUTINE WHICH /CONTAINS NO JMP INSTRUCTIONS *0242 JMP 0 /RETURN FROM SUBROUTINE *0572 JMP 175 NOP /JUMP TO SUBROUTINE AT REGISTER 0175 /SUBROUTINE RETURNS TO THIS LOCATION When JMP 175 is executed, C(PC 2 - 11 ) = 0573. This, combined with 6000 (the octal code for JMP), is placed in register 0000. When the subroutine has finished, JMP 0 transfers program control to register 0000, where JMP 573 is executed, returning control to the calling program. (At the same time, JMP 1 is stored in register 0000, but that is incidental to the actions of interest here.) When a new Instruction Field has been selected (see paragraph 3.3.14. Memory Address Control), the first JMP Y (Y =/:= 0000) following the field selection performs the actual switching of the field; the target register of the JMP is in the new field, and the return jump is stored in register 0000 of the new Instruction Field. JMP 0 has no effect on the field registers. 3.3.9 Shift and Rotate Operations These instructions rotate the contents of the Accumulator left or right, or shift them right (scaling), propagating the sign bit. A single instruction can cause a shift of up to 17 8 bit positions, or 1-1 /2 times the length of the AC. On shifts or rotations right, the MQ is treated as a 12-bit extension of the AC, so that bits shifted out of AC 11 enter MQ 0 , as shown in Figures 3-7 and 3-8. In all these operations, the Link is included when I = 1 and excluded when I= 0. Execution times depend on the number of positions shifted. ROL Rotate Left Form: Octal code: Execution time: Operation: 3-16 ROLIN 0240 + 20I + N, 0 ~ N -s;;;; 17 8 1.6 - 6.4 µs The contents of the AC are rotated left N places. If I = 1, the Link is included. The rotation scheme is shown in Figure 3-6. The contents of the MQ are not affected. I= 1 Figure 3.6. Rotate Left ROR Rotate Right Form: Octal code: Execution time: Operation: ROR I N 0300 + 20I + N, 0 < N < 17 8 1.6 - 6.4 µs The contents of the AC are shifted right N places. Bits shifted out of AC 11 enter MQ 0 , and are shifted down the MQ. Bits shifted out of MQ 11 are lost. If I = 1, the Link is included in the rotation. The scheme is shown in Figure 3-7. I=O L D LOST LOST 12-0116 Figure 3-7. Rotate Right 3-17 SCR Scale Right Form: Octal code: Exe cu ti on time: Operation: SCR I N 0340 + 201 + N, 0 ~ N ~ 17 8 1.6 - 6.4 µs The contents of the AC are shifted right N places. The sign bit (contents of AC 0 ) is not changed, and is placed in the N bits to the right of AC 0 . Bits shifted out of AC 11 enter MQ 0 , and are shifted down the MQ. Bits shifted out of MQ 11 are lost. If I= 1, bits shifted out of AC 11 also enter the Link, so that, at the completion of the operation, C(L) = C(MQ 0 ). If I= 0, the Link is unaffected. The shifting scheme is shown in Figure 3-8. Example: C(AC) = 4371 C(MQ) = 0000 Instruction: SCR I 6 Because I = 1, the Link will receive the contents of AC 11 at each shift. The result of the operation: C(AC) = 7743 The sign bit, which was 1, is loaded in the vacated bits (AC 1 _6 ) C(MQ) = 7100 Bits shifted out of the AC entered the MQ at the high-order end. C(L) =I The last bit shifted out of AC 1 1 was a 1. Check: C(L) = C(MQ 0 ). I=O L 0 AC 11 D LOST I =1 LOST Figure 3-8. Scale Right 3-18 3.3.10 Skips These instructions test the states of various registers, flip-flops, and external inputs. In every case, the next succeeding instruction in the program sequence is skipped if (1) I = 0 and the condition is met or (2) I = 1 and the condition is not met Otherwise, the program proceeds without skipping. The skip instructions (with the exception of the unconditional skip instruction, SKP) have an associated "skip condition", such as a register being cleared or one of the external digital inputs ("external levels") being asserted. If the skip condition is met (e.g., the register is cleared or the external level is asserted) at the time the instruction is executed, a skip occurs. This means that the next instruction is taken from the second location following the skip instruction, rather than from the usual location. Normally, the skip instruction is followed by a single-word instruction that is skipped or executed according to whether or not the tested condition was met. No distinction is made between single- and double-word instructions; if the skip instruction were followed by a double-word instruction, control would be transferred to the second word of the instruction if a skip occurs. Generally skip instructions should not be followed by double-word instructions. In the skip instructions discussed here, (but not in the "addressable" skips: SHD, SAE, and SRO), the i bit inverts the sense of the skip. That is, if the i bit is zero, the instruction skips only if the skip condition is met. If the i bit is a one, the skip occurs only if the condition is not met. APO Accumulator Positive Form: Octal code: Execution time: Condition: AZE Accumulator Zero Form: Octal code: Execution time: Condition: LZE AZE I 0450 + 201 1.6 µs The contents of the AC equal 0000 (+0) or 7777 (-0). Link Zero Form: Octal code: Execution time: Condition: QLZ APO I 0451+201 1.6 µs The sign bit (contents of AC 0 ) is 0, that is, C(AC) is a positive number. LZE I 0452 + 201 1.6 µs The contents of the Link equal 0. MQ Low-Order Bit Zero Form: Octal code: Execution time: Condition: QLZ I 0455 + 201 1.6 µs The contents of MQ 11 equal 0. (This is identical to the LINC-8 instruction, ZZZ.) 3-19 FLO Overflow Form: Octal code: Execution time: Condition: SKP FLO I 0454 + 201 1.6 µs The FLOW flip-flop is set to 1. When overflow occurs as the result of an addition (ADD, ADA, ADM, or LAM), the FLOW flip-flop is set to 1. If overflow does not occur as a result of the above instructions, the FLOW flip-flop is cleared. Skip Unconditionally Form: Octal code: Execution time: Condition: SKP I 0456 + 201 1.6 µs The next instruction is skipped unconditionally. (In LINC-8 and early PDP-12 assembly programs SKP was defined as 466.) The following skips test for various external input conditions. IBZ LINCtape Inter-Block Zone Form: Octal code: Execution time: Condition: SNS 0453 + 201 1.6 µs If the selected LINCtap> unit is in one of the inter-block zones and the tape is moving, the next instruction is skipped. This instruction will sense an IBZ only if the tape is in motion (i.e., only after a tape instruction with "I = 1"). Sense Switch Form: Octal code: Execution time: Condition: SXL IBZ I SNS I N 0440 + 201 + N, 0 < N < 5 1.6 µs Sense Switch N on the Operator's Console is set to 1. If I= 1, the skip will occur when the selected switch is set to 0. Skip On External Level Form: Octal code: Execution time: Condition: SXL I N 0400 + 201 + N, 0 < N < 17 8 1.6 µs An external input level is +3v. If I= 1, the skip will occur when the external level is at ground (OV). In the basic PDP-12, only three of these levels have been defined; the others are available for the user's options. When nothing is connected to the External Level Lines, they are preloaded to +3V. These external levels are digital inputs to the 1/0 bus, and should not be confused with the analog inputs to the A-D Converter. NOTE The connection for the External Level lines is made via the 1/0 Bus cables (see Chapter 5). 3-20 The three defined levels and their mnemonics are: SXL SXL SXL KST I I I 15 (KST) 16 (STD) 17 (TWC) Key Struck (See below) Tape Instruction Done (See Paragraph 3.6.9) Tape Word Complete (See Paragraph 3.6.14) Key Struck Form: Octal code: Execution time: Condition: KST I 0415 + 201 1.6 µs A key has been struck on the ASR-33 keyboard, the character code has been assembled in the Teletype buffer, and the Keyboard flag is raised. (The flag is cleared when the character is read into the AC.) 3.3.11 Miscellaneous These instructions perform various tasks. All are self-contained and require no memory references. HLT Halt Octal code: Execution time: Operation: CLR Clear Octal code: Execution time: Operation: COM 0017 1.6 µs The contents of the AC are complemented. Bits containing Os are changed to contain 1s, and vice versa. No other registers are affected. No Operation Octal code: Execution time: Operation: QAC 0011 1.6 µs The AC, MQ, and Link are cleared to zero. No other registers or flip-flops are affected. Complement AC Octal code: Execution time: Operation: NOP 0000 1. 6 µs to fetch and decode The computer stops. The contents of the AC, MQ, Link, and other active registers and flip-flops are not affected. The Program Counter contains the address of the register immediately following the HLT. If the operator presses CONTINUE, the program resumes from the point indicated by the C(PC). 0016 1.6 µs None. Nothing happens. NOP provides a 1.6-µs delay, and is often used to hold a place in the program for instructions which might be changed or added during the course of execution. Place MQ in AC Octal code: Execution time: Operation: 0005 1.6 µs The contents of MQ 0 _1 0 are placed in AC 1 - 11 • AC 0 is cleared. This instruction provides access to the low-order bits of a fractional product. Figure 3-9 shows the transfer path. 3-21 AC 0 _J SET TO ZERO 10 0 11 MQ Figure 3-9. QAC Transfer Path To obtain all 12 bits of the MQ, the following program sequence may be used: INSTRUCTION OCTAL CODE REMARKS * 0020 0005 0241 0475 6026 1620 0001 QAC ROL I QLZ JMP .+3 BSE I 0001 /C(MQ0-10) PLACED IN ACI-11 /ROT ATE C(AC) LEFT 1 PLACE, WITHOUT LINK. /SKIP IF C(MQl 1) = 1 /C(MQl 1) = 0. JUMP TO THIRD REGISTER BEYOND. /C(MQl 1) = 1. SET ACl l EQUAL TO 1. /OPERAND TO SET ACl l (QAC is identical to the LINC-8 instruction, ZTA.) 3.3.12 Console Switches These instructions provide access to the states of the switches in the Left and Right Switch Registers on the Operator's Console. The I-bit has no effect in these instructions. LSW Left Switches Octal code: Execution time: Operation: RSW 0517 1.6 µs The contents of the Left Switches Register on the Console are placed in the AC. The previous C(AC) are lost. Right Switches Octal code: Execution time: Operation: 0516 1.6 µs The contents of the Right Switches Register are placed in the AC. The previous C(AC) are lost. 3.3.13 Mode Control PDP Switch To The 8 Mode Octal code: Execution time: Operation: 3-22 0002 1.6 µs Beginning with the next succeeding instruction, the central processor will operate in the 8 mode; all subsequent instructions are interpreted as PDP-8 operations. A similar instruction, LINC ( 6141 ), in the PDP-8 mode instruction set, causes a switch to LINC mode. 3.3.14 Input/Output Bus In addition to the input and output devices controlled directly by LINC instructions (see Paragraphs 3.4, 3.5, and 3 .6), the LINC mode program also has direct access to any device connected to the PDP-12 I/O Bus. By using the special two-word enabling instruction, IOB, any 8 mode IOT instructions can be included within a LINC program sequence. JOB 1/0 Bus Enable Form: Octal code: Execution time: Operation: IOB (first word) IOT (second word) 0500 (first word) 5.9 µs The IOT timing chain is activated by the second word of this instruction. Bits 3-11 of this second word are interpreted as a PDP-8 IOT command; bits ~2 have no effect. Example 1: The following sequence may be used to read and store a character from the high-speed tape reader: IOB RRB STA 14 /ENABLE I/O BUS /READ TAPE READER BUFFER /STORE IN REGISTER SPECIFIED BY C(0014) Example 2: The following sequence waits for the high-speed reader flag and then reads the character buffer OCTAL CODE INSTRUCTION REMARKS 0500 6011 6020 0500 6016 *0020 IOB RSF JMP .-2 IOB RRB /ENABLE I/O BUS /SKIP IF HIGH-SPEED READER FLAG IS SET /NOT SET. GO BACK TWO SPACES /FLAG IS SET. ENABLE THE BUS, AND ... /READ THE CHARACTER Note that, in the skip loop, the program must jump back two locations, because the IOB must be executed each time. Several IOB/IOT pairs are used in LINC Memory Address Control and Program Interrupt operations. 3-23 3.3.15 Memory Address Control The two memory Fields used by a LINC program are program-selectable. The assignments are made by setting the two 5-bit Memory Field Registers, which can address any of 32 1024-word memory segments. Considered with respect to the physical configuration of memory, the three high-order bits of each Field Register determine which 4096-word memory bank is to be used, while the two low-order bits specify one of the four segments within that bank. The two LINC memory Fields need not be adjacent, or in any particular order. Normally, however, they would not be assigned to the same segment. In addition to the Instruction Field (IF) and Data Field (DF) Registers described in Chapter 1, the PDP-12 Memory Control contains two other registers of interest to the LINC mode programmer. 3.3.15.1 Instruction Field Buffer (IB) 5 Bits - This register holds the number specifying a new Instruction Field. Once loaded, its contents are transferred to the IF at the occurrence of the next JMP Y instruction. 3.3.15.2 Save Field Register (SF) 10 Bits - Whenever the Instruction Field is changed, either by programmed action or by a program interrupt or trap, the contents of the IF and DF are placed in the Save Field Register. From the SF, the Contents of the IF and DF can be restored, so that execution of an interrupted program, for example may be resumed. The contents of the SF may be read into the AC. (See also the Program Interrupt discussion in Paragraph 3.3.15.4.) For historical reasons the SF is also called Interrupt Buffer in some places. 3.3.15.3 Memory Control Programming - The Instruction Field and Data Field registers can be loaded directly, using LINC mode instructions. LIF Load LINC Instruction Field Buffer Form: Octal code: Execution time: Operation: LIF N 0600 + N, 0 ~ N ~ 37 8 1.6 µs The five-bit quantity N is placed in the Instruction Field Buffer (IB). The present contents of the IF and DF are transferred to the Save Field Register (SF). When the next JMP Y instruction (Y =I= 0000) is executed, N is transferred from the IB to the Instruction Field Register. The return JMP is stored in location 0000 of the new Instruction Field, and program control is transferred to register Y of the new Instruction Field. The automatic saving of the IF and DF in the Save Field Register is especially useful when subroutines are called across memory fields; that is, when a called subroutine is located in a memory field other than the current one. The subroutine may pick up the field information needed in obtaining arguments and generating subroutine returns by interrogating the Save Field Register. The execution of the LIF instruction will internally inhibit the execution of a Program Interrupt even if ION has been given. This Interrupt Inhibit lasts from the LIF instruction until the first LINC mode JMP instruction is fetched and executed in the newly selected Instruction Field. This allows the Save Field Register to be used for cross field subroutine linkage in programming which uses the Program Interrupt. Because LINK Instruction Trap (see Paragraph 3.3.17) also uses the Save Field Register for program linkage, an instruction which will be trapped must not be given between an LIF and the next JMP Y (Y f= 0000) if the cross field reference will ultimately need the Save Field Register linkage information. 3-24 Example: The program is operating in Field 2. Control is to be transferred to location 1000 of Field 5. Address Action p LIF 5 p+k JMP 1000 Contents / 5 IS PLACED IN THE IB /C(IF) AND C(DF) ARE PLACED IN THE SF /C(IB) ARE TRANSFERRED TO THE /IF. JMP P + K + 1 IS STORED IN REGISTER /0000 OF FIELD 5, AND THE PROGRAM /PROCEEDS FROM REGISTER 1000 OF FIELD 5 JMP 0 has no effect on the Memory Field registers. If it is used to return to a calling program in a different field, the change of field is effected by the JMP instruction stored in register 0000 of the subroutine's field. (LIF replaces the LINC-8 instruction, LMB) LDF Load LINC Data Field Register Form: Octal code: Execution time: Operation: LDF N 0640 + N, 0 ~ N ~ 37 8 1.6 µs The 5-bit quantity N is placed in the Data Field Register. All subsequent indirect references to the Data Field are made to the newly selected field. The previous C(DF) are lost. The contents of the other Memory Control registers are not affected. (LDF is identical to the LINC-8 instruction, UMB) The contents of the Memory Field Registers can be examined by using the following IOB/IOT pairs. JOB RIF .Q..ead Instruction Field Octal code: Execution time: Operation: 0500 6224 5.9 µs The contents of the Instruction Field Register are ORed into bits AC 6 _1 0 . The remaining AC bits are unaffected, and the contents of the IF are unchanged. NOTE When executed in LINC mode, the three IOT instructions, RIF, RDF, and RIB, are the only cases where an IOT has a slightly different function than when executed in 8 mode. For these instructions, all five bits of the IF and/or DF are read into the AC when in LINC mode, while only the most significant three bits of each are used in 8 mode. 3-25 IOB RDF Read Data Field Octal code: 0500 6214 5.9 µs The contents of the Data Field Register are ORed into bits AC 6 _ 1 0 . The remaining AC bits are unaffected, and the contents of the DF are not changed. Execution time: Operation: 3.3.15.4 Program Interrupt In LINC Mode - To facilitate the handling of data being transmitted to and from several peripheral devices, the PDP-12 includes a Program Interrupt Facility. When an external device is ready for servicing, a signal (flag) associated with that device is set. With Interrupt enabled, the following sequence of events will occur when a flag is set: 1. The instruction being executed at the time of the interrupt request is completed. 2. The contents of the Program Counter are stored in register 0040 of memory field 0 (regardless of the current Instruction Field assignment). 3. The contents of the Memory Field registers are placed in the Interrupt Buffer (Save Field Register). 4. Program execution proceeds from register 0041 of Memory Field 0. The normal procedure from this point calls for the interrupt service routine beginning in location 0041 to determine which device flag caused the interrupt request, perform the appropriate tasks, restore the Memory Field registers, re-enable the interrupt, and jump back to the interrupted program at the point where the Program Interrupt occurred. Whenever a change of LINC Instruction Field occurs, the Program Interrupt is inhibited (between Steps 1 and 2 above) until the first JMP is executed in the new field. This allows the programmer to obtain and save the contents of the SF after the Field change, before a waiting interrupt request destroys the contents of the SF. The interrupt control instructions and related memory field instructions are all IOB/IOT pairs. JOB ION Interrupt On Octal code: Execution time: Operation: 0500 6001 5.9 µs The Interrupt Facility is enabled immediately after the next succeeding instruction (following the ION) is executed. From that point on, any interrupt request will cause the sequence of events described above. If a device flag is already raised when the Interrupt is enabled, the waiting request is serviced immediately. The one-instruction delay before enabling the interrupt ensures that the interrupt service routine can return to an interrupted program before a new request is honored without losing its place. JOB !OF Interrupt Off Octal code: Execution time: Operation: 3-26 0500 6002 5.9 µs The Interrupt is disabled. The facility is disabled immediately; subsequent requests will not cause an interrupt until the facility is enabled again. The next two instructions are related to the Save Field Register, wherein the original contents of the IF and DF are stored whenever the contents of the IF are being changed, by an LIF instruction, or as the result of an Interrupt request or a Program Trap. INST. FIELD BUFFER 0 2 3 4 4 - - JMP AFTER LIF DATA FIELD - - - INTERRUPT, TRAP, LI F ACCUMULATOR 12-0118 Figure 3-10. Data Path: IB, IF, DF, and AC JOB RIB Read Interrupt Buffer Octal code: Execution time: Operation: 0500 6234 5.9 µ.s The contents of the Interrupt Buffer (Save Field Register) are ORed into bits AC 0 - 1 and AC 4 - 11 , as shown in Figure 3-10. AC 2 - 3 and the contents of the SF are unchanged. RIB is most commonly used immediately after a change of instruction field or a program trap, to save the record of the origin fields while the Program Interrupt is inhibited. (If inhibit were not provided, a waiting interrupt request could destroy the contents of the Save Field Register. The first JMP instruction executed after a trap or change of Instruction Field reenables the Interrupt.) JOB RMF Restore Memory Fields Octal code: 0500 Execution time: Operation: 5.9 µs, including IOB The contents of SF 5 - 9 are placed in the Data Field Register, and the contents of SF o-4 are placed in the Instruction Field Buffer. At the next occurrence of a JMP Y instruction (Y =I= 0000), the contents of the IB are transferred to the IF, effecting a return to the proper field after servicing an interrupt request. The data transfer path is shown in Figure 3-11. 624~ 3-27 INSTRUCTION FIELD 0 I I 2 3 I 4 r DATA FIELD REGISTER (JMPY) IB I 0 4 4 3 2 3 2 0 (RMF) t (RMF) 0 I I 2 3 I 4 5 6 7 8 9 SAVE FIELD REGISTER Figure 3-11. Data Path, RMF Instruction DJR Disable JMP Return Octal code: Execution time: Operation: 0006 1.6 µs DJR sets a flip-flop, preventing contents of location 0000 from being changed when the next and only the next LINC mode JMP is given. The DJR instruction is used when returning from Program Interrupt or Trap service routines. The DJR should be given prior to the ION instructions. This is useful because an interrupt can occur within a LINC mode subroutine that uses Location 0000 of its IF to retain the subroutine return; hence, it must not be destroyed. Example: A program operating in Field 7 is interrupted while the instruction in register 0531 is being executed. ( 1) C(PC) are stored in location 0040 of Field 0. (2) C(DF) and C(IF) are placed in the SF, as shown in Figure 3-10. (3) Program execution resumes in location 0041 of Field O; in other words, 00 is placed in the IF, and 0041 in PC 2 - 11 • ( 4) The interrupt is disabled. The interrupt service routine must do three things. First, it sets up a return jump enabling the program to get back to the point of the break. Next, it identifies the cause of the request and services the condition. Finally, it restores the conditions prevailing at the time the interrupt occurred and returns to the main program. The following sequence shows how these tasks may be accomplished. 3-28 ADDRESS OCTAL CONTENTS 0040 0041 0042 0043 0532 4000 2040 1620 *0040 0532 STC ACSAV ADD 0040 BSE I 0044 0045 6000 4071 6000 STC RTN 0046 0000 0047 0050 0051 0052 0053 0054 0055 0056 0057 0060 0000 0000 0000 0016 0016 0016 0016 0000 0000 0500 /CONTENTS OF PC AT TIME OF INTERRUPT /SAVE C(AC), THEN CLEAR AC /SAVED ADDRESS (0532) TO AC /MAKE JMP INSTRUCTION: C(AC) /V C(0044) /OCTAL CODE OF JMP INST. /STORE JMP 532 AT END OF SERVICE /ROUTINE /MAIN PART OF SERVICE ROUTINE, IF /NECESSARY /OTHER ACTIVE REGISTERS (MQ,L,ETC) /SHOULD BE SAVED ALSO NOP NOP NOP NOP /THE REST OF THE ROUTINE 0061 6244 0062 0063 0064 0065 0066 4076 2000 0006 0000 0000 0067 0070 0071 0072 0073 0074 0075 0076 0500 6001 6532 0000 0000 0000 0000 0000 REMARKS IOB /EXIT SEQUENCE, ENABLE IOT TIMING /CHAIN RMF / ... AND RESTORE MEMORY FIELDS, /(07 TO IB) STC TEMP /CLEAR AC WITHOUT DISTURBING MQ AND L ADDACSAV /RESTORE ORIGINAL C(AC) DJR /SET PROCESSOR SO THAT NEXT JMP INST /WILL NOT STORE IN LOCATION ZERO OF /MEMORY BANK TO WHICH JMP AT "RTN" /WILL GO IOB ION /RE-ENABLE INTERRUPT JMP 0532 /JMP TO ORIGINAL FIELD RTN, TEMP, RMF=6244 ION=6000 0000 3.3.16 Special Functions A set of six Special Functions allows the LINC programmer to establish any of five operating states, or generate an 1/0 PRESET pulse. The special functions are determined by AC 2 - 7 , as shown in Figure 3-12. AC I I I I 0 1 INSTRUCTION TRAP 2 J 3 4 5 6 I I } 7 L 1/0 PRESET PULSE DISABLE TELETYPE INTERRUPT TAPE TRAP FAST SAMPLE CHARACTER SIZE Figure 3-12. Special Functions 3-29 These functions have the following characteristics: 1. Instruction Trap Enable - Causes an immediate program interrupt to register 0141 when an undefined LINC instruction code is encountered. The instruction trap is described in detail in Paragraph 3.3.17. 2. Tape Trap - When this function and Instruction Trap Enable are both set, a program interrupt to register 0141 will occur whenever a LINCtape instruction or one of the other trapped codes is encountered. The LINCtape instruction is not executed. Tape Trap is described in detail in Paragraph 3.6.13. 3. Character Size - This function determines the size of a character displayed on the CRT by the DSC instruction. It is described in detail in Paragraph 3.4.1. 4. Fast Sample - This function reverses the order of events of the SAM instruction; i.e., read the converter buffer and initiate a new conversion, then continue without pausing (see Paragraph 3.5.1 ). 5. Disable Teletype lnterrnpt - Interrupt requests from the ASR-33 Keyboard or Printer are inhibited. No program interrupt will occur when either TTY flag is set even if the Interrupt Facility is enabled (see Chapter 6). 6. Generate 1/0 Preset - If this bit is set when the enabling instruction (ESF) is executed, an I/O PRESET pulse is generated clearing all device flags, disabling the Interrupt, clearing the Tape Extended Operations Buffer, and generating the TAPE PRESET pulse. Other Special Functions are cleared, or in the case of CHARACTER SIZE, set to full size. The active registers of the Central Processor are not affected, and the system continues to operate with RUN on. Any or all of these functions may be enabled at the same time, except that they are effectively nullified if I/O PRESET is given. All the Special Functions except I/O PRESET are controlled by flip-flops set from the designated AC bits; the states of these flip-flops may be examined at any time. ESF Enable Special Functions Octal code: Execution time: Operation: SFA 0004 1.6 µs The contents of AC 2 - 6 are placed in their respective flip-flops, as shown in Figure 3-12. For each AC bit set to 1, the corresponding function is enabled. For each AC bit set to 0, the corresponding function is disabled. If AC 7 is set to 1, the I/O PRESET pulse is generated. All Special Function bits are cleared (except ESF 04, Full Size Character, which is set to a 1) by I/O PRESET, either from the console or program control. Place Special Function Flip-Flops in AC Octal code: 0024 Execution time: 1.6 µs Operation: The contents of the Special Function flip-flops are placed in their respectively designated AC bits, as shown in Figure 3-12. AC 0 - 1 and 7 - 1 1 are cleared. 3.3.17 Instruction Trap Several sets of operation codes in the LINC repertoire are undefined. The LINC programmer can make use of these codes without having to hard-wire them, by means of subroutines and the Instruction Trap. When the Trap is enabled (ESF with C(AC 2 ) = I), any undefined LINC codes will cause a program trap. When the undefined code is encountered, program control is transferred to register 0141 of Memory Field 0, regardless of the current setting of the IF. The contents of the Program Counter are placed in register 140, and the contents of the IF and DF are placed in the Save Field Register. The subroutine beginning at 0141 can examine the trapped code (using the information stored in 0140 and the SF) to determine what program-defined operations are to be performed. (Also, see Paragraphs 3.3.15.3 and 3.3.15.4 for interaction with Program Interrupt. These are the undefined LINC codes which cause a program trap: Operate class Execute class Undefined Undefined 3-30 501-515, 521-535 740-747 540-577 1700-1737 The LINC codes 1700-1737 are considered as j3-class instructions. Therefore, when either a 1700 or 1720 instruction is encountered, the address contained in location 140 is the address of the trapped instruction incremented twice (trapped instruction address +2). All other undefined codes will cause location 140 to contain the address of the trapped instruction incremented once (trapped instruction + 1). Probably the most common use of the Instruction Trap is in the execution of programs written for the LINC-8. A LINC-8 Trap Simulator is provided in the basic PDP-12 software package. Close study of this program will be most helpful for the programmer wishing to use the Trap facility. The Trap facility is further useful for developing device-independent software. 3.3.17. l Tape Trap - When both the Tape Trap and Instruction Trap functions are enabled, the LINCtape instructions (codes 700-737) are trapped also. This is useful if the programmer wishes to substitute another external storage device, such as a Disk, for the LINCtape. 3.3.17.2 Program Interrupt and Instruction Trap - If the interrupt is enabled when an Instruction Trap occurs, the interrupt is inhibited until the execution of the first JMP after the trap. This permits the trap program to store the contents of the Save Field Register immediately after the trap, so that the record of where the trap took place is not destroyed by an interrupt request, which also causes the contents of the IF and DF to be placed in the SF (also see Paragraphs 3.3.15.3 and 3.3.15.4). 3.4 CRT DISPLAY, TYPE VR 12 The 6.5 inch x 9 inch rectangular screen of the PDP-12 CRT Display Type VR12 has a total display area of 58.5 square inches. Grid dimensions are 512 x 512 points. The horizontal distance between points is 0.0176 inches; the vertical distance is 0.0127 inches. The (0,0) grid point is at the midpoint of the left side of the screen, as shown in the schematic representation in Figure 3-13. Grid co-ordinates are given in octal. o,+377 - - - - - - - 111, +377 0,0 1----------11 777,0 0,-377 - - - - - - - 777,-377 Figure 3-13. CRT Grid The display system is fully buffered. Coordinates are held in two 9-bit buffers; during the execution of DSC, the pattern word is retained in a 12-bit Pattern Intensification Register. Either of two multiplexed intensification channels can be specified. A switch on the VR 12 front panel allows either or both channels to be displayed. Below the channel selector is a variable knob which allows the user to change the intensity of the displayed points. A level control located within the VRl 2 presets the maximum brightness level, preventing spot burns. A 24-contact connector on the Data Terminal Panel allows the user to connect an auxiliary scope (VR-l 2A CRT Display, Tektronix 561, or similar unit) for remote display of the same information sent to the main screen. The channel selectors can be independently set so that each scope displays one of the channels, thus allowing independent simultaneous displays on two scopes. A complete set of connection points for the VC12/VR12 display system is shown in Appendix G. 3-31 The output drive capability of the D-A converters is Ov to -5.85v capable of driving a load resistance of 1 kQ connected to ground. This allows up to 200 feet of cable for a remote VR-12. The absolute values of the D-A outputs are not held closer than ±0.3v but are stable to within 3.0%. The D-A converters are loaded by jam transfer. The D-A used to drive the scope is also available as a single-ended output to drive external devices. The Ov D-A point is equivalent to the lower left hand corner of the display screen. The LINC display instructions allow the programmer to display single grid points or a small array of points. In either case, the full buffering allows the program to proceed after the display operation has been initiated. If a subsequent display instruction is encountered before the previous display operation has been completed, the program will pause until the display control is free, then execute the new instruction. 3.4.1 Point Displays DIS Display (a-Class) DIS I a Form: Octal code: Execution time: 0140 +a, 0 ~a~ 17 8 3.2 µs; 23 µs for completion of display A single point on the screen is intensified. The vertical coordinate is specified by AC 3 _1 1 ; the horizontal coordinate by bits 3-11 of the designated a-register. If bit 0 of the a-register is set to 0, the point will be displayed on Channel O; if C(a 0 ) = I, the point will be displayed on Channel 1. If I = 0, the contents of a are taken as is. If I = 1, C(a) are first incremented by I, using 10-bit, two's complement addition. Bits 0 and I are not affected. 3.4.2 Character Displays DSC Display Character ({J-Class) Form: Octal code: Execution time: Operation: DSC I f3 1740 + 201 + {3, f3 ~ 2 ~ 17 8 4.8 µs when I= 1, f3 = 00; 6.4 µs when I= 0 or {3=t 00 Control completion time 20-56 µs. A vertical 2 x 6 array of points is displayed according to a pattern word stored in register Y (Y is defined as with other ~-class instructions). For each bit of the pattern that is a 1, the corresponding point is intensified; for each bit that is a 0, the corresponding point is left dark. In Figure 3-14, the circles represent the points of array; the small numbers refer to the corresponding bit positions of the pattern word. The small arrows show the order in which the pattern bits are examined and displayed. As with DIS, the vertical coordinate is held in the Accumulator. The horizontal coordinate is held in register 0001; for this reason, register 0001 cannot be used as a 13-register with DSC. The character may be displayed in either of two sizes: full size, in which the spacing between points in both directions is four grid positions, and half-size, in which the spacing is two positions. The following description assumes full-size characters. When a DSC instruction is executed, the following events occur: ( 1) The intensification pattern is transferred from Y to the display control Intensification Buffer. (2) The contents of AC 3 - 6 are placed in the display control Y-buffer; AC 7 - 11 are set to 30 8 • The contents of register 0001, the X-coordinate, are incremented by 108 , and transferred to the display control X-buffer. 3-32 The foregoing operations take 4.8 or 6.4 µs to do their work, after which the central processor is free to resume program execution. The remaining operations are performed by the display control. (3) The pattern word is examined in the order shown in Figure 3-14. The time required to scan and display the points varies according to the number of points to be intensified. Reaching the first point requires 20 µs, then 1 µs for each point to be left dark and 3 µs for each point to be displayed. This action continues until all points are intensified. Because of the manner in which the Y-coordinate is used, full-size character arrays may start only at coordinates which are multiples of 40s; e.g., 000, 040, 100, -100. Since the array itself is only 30s points high, this gives the programmer an automatic vertical spacing of 1Os points between the bottom of one line and the top of the one immediately below it. ,., •, ~' x I X+I09 {FULL SIZE) X+ 49 (HALF SIZE) I 2·0030 Figure 3-14. Display Pattern for DSC 3.4.3 Half-Size Characters If the programmer clears the CHARACTER SIZE bit of the Special Function Register [ESF with C(AC 4 ) = 0), all increments are by two grid positions, rather than four. AC 3 _7 provides the initial Y coordinate; after the two coordinates have been transferred to the display control's buffers, the contents of AC 8 - 11 will be 14s, and the X coordinate in register 0001 will be incremented by 4 instead of by I Os. Vertical spacing is likewise halved; arrays may start at intervals of 20 8 points, with 4 points between lines. I/O PRESET sets this bit of the Special Function Register to a 1 (full-size characters). 3 .4 .4 Character Set Any character that can be represented on a 4 x 6 grid (24 points) can be displayed by using two DSC instructions, with two consecutive storage words providing the complete 24-bit character pattern. Table 3-1 lists the display patterns for the ASR-33 character set. Nondisplayed characters have patterns of all zeros. The table entries, each consisting of two words, are arranged in order of ASCII codes. 3-33 Table 3-1. ASR-33 Character Set Display Pattern External ASCII Internal Code 245 45 % 246 46 & 211 47 TAB 250 50 ( 251 51 ) 252 52 * 253 53 + 254 54 255 55 256 56 257 57 I 260 60 0 261 61 1 262 62 2 263 63 3 264 64 4 265 65 5 266 66 6 267 67 7 270 70 8 271 71 9 272 72 273 73 3-34 Character ' - , Pattern Words External ASCII Internal Code Character Pattern Words 3114 0643 5166 0526 0000 0000 3600 0041 4100 0036 2050 0050 0404 0437 0500 0006 0404 0404 0001 0000 0601 4030 4136 3641 2101 0177 4523 2151 4122 2651 2414 0477 5172 0651 1506 4225 4443 6050 5126 2651 5122 3651 2200 0000 4601 0000 274 74 < 275 75 = 276 76 > 277 77 ? 301 01 A 302 02 B 303 03 c 304 04 D 305 05 E 306 06 F 307 07 G 310 10 H 311 11 I 312 12 j 313 13 K 314 14 L 315 15 M 316 16 N 317 17 0 320 20 p 321 21 Q 322 22 R 323 23 s 0412 2100 1212 1212 0021 1204 4020 2055 4477 7744 5177 2651 4136 2241 4177 3641 4577 4145 4477 4044 4136 2645 1077 7710 7741 0041 4142 4076 1077 4324 0177 0301 3077 7730 3077 7706 4177 7741 4477 3044 4276 0376 4477 3146 5121 4651 Table 3-1. ASR-33 Character Set Display Pattern (cont) External ASCII Internal Code 324 24 T 325 25 u 326 26 v 327 27 w Character 330 30 x 331 31 y 332 32 z 333 33 [ 334 34 \ Pattern Words External ASCII Internal Code 4040 4077 0177 7701 0176 7402 0677 7701 1463 6314 0770 7007 4543 6151 4177 0000 0204 1020 335 35 ] 336 36 t 212 37 LINE FEED 240 40 SPACE 241 41 ! 242, 42 " 215 43 RETURN 244 44 $ Character Pattern Words 0000 7741 0000 0000 0000 0000 0000 0000 7500 0000 7000 0070 0000 0000 4731 4275 3.5 DATA TERMINAL The Data Terminal provides analog inputs and relay-controlled outputs for use by LINC mode programs. The facility includes the following: Analog Inputs Relays Auxiliary Scope Connector Six teen channels Six relays for external equipment control 24-pin connector for an auxiliary CRT 3.5.1 Analog Inputs The AD 12 Analog-Digital Converter and Multiplexer consists of 16 input channels, a Sample and Hold, a multiplexer, and a 10-bit A-D converter. Eight of the channels are for external inputs via phone jacks. These feed through preamplifiers to the multiplexer. The acceptable voltage range of these inputs is± lv with a sensitivity of approximately 2 mv/count. The other eight channels are controlled by continuously variable knobs mounted on the Data Terminal. The knobs give ten turns stop-to-stop however, 7 turns provide the full 10-bit range to the converter (1-1/2 to 2 turns from each extreme is beyond the A-D range of -777 8 to +777 8 ). The knobs can be used to control speeds (as in the continuous display of data from tape), set threshold levels or other test parameters, etc. A single LINC mode instruction selects the input channel, initiates the conversion, and transfers the contents of the buffer into the AC. 3-35 SAM Sample Form: Octal code: Execution time: Operation: SAM N 0100 + N, 0 ~ N ~ 17 8 (Basic system); 0 ~ N ~ 37 8 (extended system) 18.2 µs (Normal mode); 1.6 µs (Fast sample mode) Input channel N is selected. In normal mode, the voltage level present at the input is sampled and converted to a 10-bit number (including sign), which is assembled in the converter buffer. When the conversion is complete, the contents of the buffer are transferred into AC 3 - 11 • 'The sign is placed in AC 0 - 2 • When the FAST SAMPLE Special Function is selected [ESF with C(AC 5 ) = 1], the order of events is reversed. The current contents of the converter buffer are transferred to the AC. Then the specified channel is selected and a new conversion is initiated. The results of this new conversion can be read by a subsequent SAM instruction, unless the KW 12-A Real Time Interface is selected to mode 4, 5, 6, or 7; in this case only, the KWl 2-A may initiate the A-D conversion. If a conversion is still in progress when the next SAM is encountered, the processor waits until the conversion is complete before executing the new SAM. 3.5.2 Relays Six DPDT relays mounted on the Data Terminal can be switched by LINC mode instructions, allowing the user to control the operation of various pieces of external equipment that are not interfaced directly with the PDP-12. The states of the relays can be examined at any time. One set of form C contacts for each of the relays is available at the binding posts on the Analog Input Panel as indicated in Figure 3-15. A second set of contacts is brought out to split lugs on the relay printed circuit board. N.C. ... COM N.O. I .. AC BIT RELAY I 0 0 0 0 0 0 0 6 2 0 0 8 3 0 0 0 0 9 4 0 0 10 5 0 0 0 0 41 7 11 12-0209 Figure 3-15. Relay Terminals and Corresponding AC Bits 3-36 ATR AC to Relays Octal code: Execution time: Operation: 0014 1.6 µs The contents of AC 6 • 1 1 are transferred to the Relay Buffer; the state of each relay is determined as follows: If the corresponding AC bit is 0, the relay is switched off. If the corresponding AC bit is 1, the relay is switched on. RTA Relays to AC Octal code: Execution time: Operation: 0015 1.6 µs The contents of the Relay Buffer are transferred into AC 6 - 1 1 . If the relay is off, the corresponding bit will be O; if it is on, the bit will be 1. Bits AC 0 • 5 are not changed. 3.6 LINCTAPE TYPE TC12 The basic LINCtape system consists of either two DECtape Transports Type TUSS or one DECtape Transport Type TU56 controlled by a fully buffered subprocessor. A single ten-channel tape head serves for both reading and writing. Information is redundantly recorded; one line of tape contains five bits, each recorded in two non-adjacent channels, as shown in Figure 3-16. Three bits are actual data; the other two provide control information for the tape processor. The Timing track determines the position of each recorded line. Four lines are required to accommodate a full 12-bit word; the corresponding Mark Track code identifies the nature of the data word. The recording technique and tape layout are described in detail in the PDP-12 Maintenance Manual. 3.6. l Organization of Data On a standard-format LINCtape, information is recorded in blocks of 256 12-bit words each, with identifying data at each end of the block. One reel of Standard format LINCtape has a capacity of 512 blocks, for a total of 131,072 1 0 words of data. (In other formats, this capacity may be extended to 225 ,000 1 0 words.) The organization of a tape is schematically presented in Figure 3-16. At each end of the tape is a long End Zone which allows the transport to reverse direction or come to rest without pulling the tape off the reel. Between the end zones and the terminal blocks, and between blocks, are Interblock Zones which can be sensed by the LINC instruction IBZ. An interblock zone is 5 words long. Figure 3-l 6B represents a typical block of 256 data words preceded and followed by control and identifying information. The serial bit sequence on the Mark Track, is decoded so that the control can determine whether the adjacent data bits form true data, checksum words, guard words, etc. The symbols BM, CM, GM, etc. (defined below), refer to these Mark Track bit patterns. 3-37 w w 00 532 10 BLOCKS r A. FULL TAPE ~~m1-1 LEADER (BLANK) END ZONE INTERBLOCK ZONE 5~~ I '-----y-----J'---y---..J I 20009 77779 END MARKS INTERBLOCK MARKS INTERBLOCK ZONE 11rrJ ~ IM(5) USEABLE BLOCKS ............. GUARD /WORD DATA (3778 DM) GM CM .............. 109 40009 END MARKS --...... --...... ............ .............. CM CM 256 DATA WORDS 1 2 3 1 2 3 m REVERSE BLOCK NUMBER ,..-...., ......... / 4 8 0 4 f t t ......... ......... TIMING TRACK t m m m m -r---.---.,.-----,,.--m--m--m---tf 0 § '--v-1 I m IM (5) ·- ---v---. t R B GM M "-v-1J ~ CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL TRAILER (BLANK) ............ I I I FM I I ~ >- --...... ~ ,,. C.1 WORD --...... CHECKSUM WORD FORWARD BLOCK NUMBER DATA DATA DATA DATA DATA DATA END ZONE INTER BLOCK MARKS ............ I '-y-1 ZONE '-----y----1'-----y-----J ............ I BM I BN IINTERBLOCK BN 0-7779 ~/~ 8. 1 BLOCK BN 10131014 1 5 9 2 MARK TRACK 3 6 7 10 11 1 2 5 3 7 11 8 9 6 10 m m m m m m m t t t t t t t m t m ( MARK TRACK + TIMING TRACK TAPE DIRECTION FWD - - - 12-0107 Figure 3-16. Standard LINCtape Format A block consists of 256 data words preceded and followed by control and identifying information, as shown in the second drawing in Figure 3-16. Block Number (BM) This identifies the block. On a standard LINCtape, block numbers are sequential, from 0000 through 0777 8 • Guard Word This protects the Block Number from transients when the read/write current is turned on and off, and allows time for the tape processor to switch from Search to Read or Write modes. (GM) Data Words (DM,FM) This is the information recorded on tape from core memory. The final Data Word is specially identified, to signal the end of the block. When writing a tape, this signal conditions the tape processor to write the checksum in the next word position. Checksum This is the two's complement of the 12-bit sum of all the data words in the block plus the constant 7777 8 • The result of adding the data sum to the checksum should be 0000; this provides a check (hence the name) on the accuracy of the transfer. (CM) Check Words (CM) Reverse Block Number (RBM) These are dummy words whose Mark Track code is the same as that for the Checksum. They are provided to insure that the Write current will be turned off before the Reverse Block Number is encountered. The Guard and Check words are not of general interest to the programmer except as they affect timing. This is the Block Number that identifies the block when tape is being searched in the reverse direction. Su bprocessor The LINCtape processor controls all information transfers between memory and tape. It is fully buffered; once an operation has been initiated by a LINC mode instruction, it is carried to completion by the tape processor. The central processor may either wait until the tape transfer is complete, or proceed immediately after the tape instruction has been initiated, testing at some later time for completion of the operation. Transfers are effected in either Standard or Extended modes. In Standard mode, transfers are made to and from fixed memory locations. Extended Operations provide for a flexible addressing facility, program interrupt, and additional tape units. As can be seen in Figure 3-17, the tape subprocessor contains seven registers which provide the transmission path for data and for control information. Data Path Read/Write Buffer (RWE), 12-Bits - When reading, the four lines of a data word are assembled in this register, in the bit positions shown in the third drawing of Figure 3-16. When writing, the contents of the RWB are disassembled and written on four consecutive lines of tape. Essentially, the RWB is a three-section shift register, with the three bits of a tape line entering (or leaving) the register at four-bit intervals, as indicated by the arrows in Figure 3-17. 3-39 SEARCH ONLY TBN 12 bits TMA 12 bits SHIFT REGISTER TB 12 bits ADDER WRITE TMA SETUP XOB READ/SEARCH 12 bits READ/ WRITE TB+TAC 12 bits TAC 12 bits LINCtape PROCESSOR AC CENTRAL PROCESSOR < MB >TAPE DATA _ _ __,_..CONTROL INFORMATION ( 12 BITS) 12-0105 Figure 3-17. LINCtape Processor Information Paths Tape Buffer (TB), 12 Bits - When reading, the assembled word is transferred from the RWB to the TB, and from there sent to the MB in the central processor. When writing, the direction is reversed; information from the MB enters the TB, and from there is placed in the RWB for disassembly onto the tape. Tape Accumulator (TAC), 12 Bits - As each data word is read or written, the data sum is accumulated in the TAC. When reading, this sum is added to the Checksum read from tape, to determine whether the transfer was completed accurately. When writing, the data sum is complemented when the final data word signal is received, and the resulting Checksum is written in the word position following the final data word. The contents of the TAC can be brought into the central processor AC, using the Linc mode TAC instruction. In searching operations. the TAC also holds the sum of the desired block number and the last block number read from tape. Control Registers In Standard mode operations, these registers are automatically set up; in Extended Operations, the program must set the XOB and TMA Setup Register. 3-40 Tape Block Number (TBN), 12 Bits - This contains the number of the block to be accessed in a data transfer. As the tape is searched, the Block Number read from tape is compared with that in the TBN; when the numbers match, the tape is positioned so that the transfer can begin. During group operations, the TBN contains the number of the first block to be accessed. Tape Memory Address (TMA), 12 Bits - This contains the address of the memory location to or from which the data is being transferred. In extended address mode, TMA is loaded from the TMA Setup Register at the beginning of a tape instruction; in Standard mode, the MBLK and TBLK information in the second tape instruction word are used to determine the initial contents of TMA. The TMA is incremented by I for each data word transferred. TMA Setup Register, 12 Bits - In Extended Address mode, the register retains the first memory address of the data to be transferred. If the transfer is not successful, the contents of TMA Setup are placed in the TMA, and the operation is repeated. The TMA Setup Register is loaded from the AC, using the TMA instruction. Extended Operations Buffer ( XOB) 12 Bits - The contents of this register determine which of the various extended tape operations are in effect. These include extended memory addressing, tape interrupt, the no-pause condition, hold motion, and extended units. 3.6.2 Programming The tape transfer operations are the same for both Standard and Extended Operation modes. Data may be read or written in single blocks or groups of contiguous blocks (in the extended address mode, only single blocks are transferred), with or without error-checking. Step-by-step searches can be performed, and block numbers can be identified without reading or writing data. All LINCtape instructions require two words. The first word specifies the operation to be performed, one of two tape units, and the motion of tape at the end of the operation. The second word gives the tape block number and in Standard mode also gives the memory block number. The structure of the two words is shown in Figure 3-18. FIRST WORD 0 1 2 1 3 I I I I I I 4 5 6 INSTRUCTION CODE .J MOTION I I I 0 1 8 9 j 10 I ,, I t t '- OPER~TION _J I LUNIT BLOCK NUMBER (EXTENDED ADDRESSING} MUST BE =O SECONOWORO 7 2 MEMORY BLOCK NUMBER (MBLK) 11 3 TAPE BLOCK NUMBER (TBLK) 12-0119 Figure 3-18. LINCtape Instruction Format 3-41 First Word The general instruction code for the LINCtape class is 0700. The particular operation to be performed is specified by bits 9-11 of the first word. In the basic system, one of the two TU55 units is selected by bit 8. If this bit is 0, the unit dialed to 0 is selected; if this bit is a 1, unit 1 is chosen. Bit 7 (the I-bit) is used to determine the state of the unit's motion when the operation is completed. See Paragraph 3.6.3 below. Second Word In Standard Addressing, bits 3-11 of the second word specify the number of the tape block to be accessed. Bits 0-2 specify one of four blocks of a LINC Memory Field to or from which data is to be transferred. These memory blocks are assigned to specific addresses in each field. There are four blocks in each LINC field, each being 256 words (1 tape block) long. The blocks are assigned as follows: Memory Block Number (MBLK) 0 1 2 3 4 5 6 7 LINC Memory Field Instruction Instruction Instruction Instruction Data Data Data Data Field Field Field Field Field Field Field Field LINC Field Addresses 0000-0377 0400-0777 1000-1377 1400-1777 2000-2377 2400-2777 3000-3377 3400-3777 In Standard Mode addressing, the contents of a tape block and a memory block correspond exactly. All single-block transfers are effected between the tape block and the memory block specified by the second word of the tape instruction. In group transfers, where several contiguous blocks are transferred, the second word is interpreted in a slightly different way. (See description of RCG and WCG instructions in Paragraph 3.6.4.) The two non-transfer instructions, MTB and CHK, use the second word in still different ways. 3.6.3 Tape Motion Tape is read or written in the forward direction. It may be searched in either the forward or backward direction. Bit 7 of the first word of a LINCtape instruction determines the motion of the tape when a LINCtape operation has been completed. If bit 7 (the I-bit) is set to a 1, the tape is left moving in the direction in which it was going at the completion of the operation. Except for searches backward, this will usually be the forward direction. If bit 7 is set to a 0, the tape processor enters the Turnaround State at the completion of the operation, which is the end of the Checkword State. When a block mark is encountered, the tape stops, leaving the Turnaround State and entering the Idle State. If a subsequent tape instruction occurs while the tape processor is in the Turnaround State, searching begins with the tape moving forward. 3-42 If the tape has stopped, a subsequent tape instruction will begin with tape motion in the backward direction. It will search backwards until a block number has been encountered. This first block number is used to determine the required direction to complete the instruction. NOTE The foregoing discussion applies only to tape motion at the completion of an instruction. It should not be confused with the NO PAUSE Extended Operation, which affects central processor action after a tape operation has begun. 3.6.4 LINCtape Instructions In the subsequent instruction descriptions, the following terms are used: Data sum two's complement sum of all 256 data words in a block Checksum two's complement of (Data sum + 7777 8 ) Transfer check Data sum + Checksum + 7777 8 If the transfer is successful, the transfer check= 7777 8 If not, the transfer check =f=. 7777 8 MBLK, TBLK As shown in Figure 3-18 NOTE It is assumed that Extended Address and NO PAUSE are not used in the following discussion. RDE Read Tape Form: Octal code: Execution time: Operation: RDC Read and Check Form: Octal code: Execution time: Operation: RCG RDE I U 0702 + 201 + IOU 3.2 µs Block TBLK is read from tape into memory block MBLK. The transfer check is left in the TAC and AC. The contents of the tape are unchanged. RDC I U 0700 + 201 +IOU 3.2 µs Block TBLK is read from tape into memory block MBLK. If the block is transferred correctly, the transfer check is left in the TAC and AC; otherwise, the operation is repeated. The information on tape is unchanged. Read and Check Group Form: Octal code: Execution time: Operation: RCG I U 0701 + 20I +JOU 3.2 µs Block TBLK is read from tape into the memory block designated by of TBLK; e.g., tape block 773 is read into memory block 3, tape block 7. The next consecutive tape blocks are read into successive memory follows tape block 777, and memory block 0 follows memory block 7. additional consecutive blocks to be transferred. the three low-order bits 027 into memory block blocks. Tape block 000 MBLK is the number of 3-43 Example: Transfer blocks 202-205 from unit 1 to memory, leaving the unit in motion at the end. Instruction Octal RCG I 3202 0731 3202 /READ AND CHECK GROUP INST /MBLK = 3, THE NUMBER OF ADDITIONAL BLOCKS /TBLK = 202. Data is transferred from tape block 202 into memory block 2, then from 203 to memory block 3, 204 to memory block 4, and 205 to memory block 5. Each block transfer is checked. If the transfer is successful, the transfer check (7777) is left in the TAC; otherwise, that block is repeated. If the entire group is transferred successfully, 7777 is left in the TAC and AC at the end of the operation. WR! Write Tape Form: Octal code: Execution time: Operation: WRC WRC I U 0704 + 20I + IOU 3.2 µ.s The contents of memory block MBLK are copied into block TBLK. If the transfer is successful, the transfer check (7777) is left in the TAC and PAC; otherwise, the operation is repeated. Write and Check Group Form: Octal code: Execution time: Operation: 3-44 3.2 µ.s The contents of memory block MBLK are copied into block TBLK; the transfer check is left in the TAC. The contents of memory are unchanged. Write and Check Form: Octal code: Execution time: Operation: WCG WRI I U 0706 + 201 + IOU WCG I U 0705 + 20I + IOU 3.2 µs MBLK is the number of additional consecutive memory blocks whose contents are written on tape. The low-order digit of TBLK specifies the first memory block to be accessed. The contents of this block are copied into block TBLK of tape. The contents of the next MBLK memory blocks are copied into the next successive tape blocks. Memory block 0 follows memory block 7, and tape block 000 follows block 777. The scheme is identical with that for RCG. If the transfer is successful, the transfer check (7777) is left in the TAC and AC; otherwise, the operation is repeated. The following two instructions do not transfer data. MTB Move Toward Block Form: Octal code: Execution time: Operation: CHK MTB I U 0703 + 201 + lOU 3.2 µs Subtract the first tape block number encountered (or reverse block number, if the tape is moving backwards) from TBLK, leaving the difference in the TAC and AC. If I = 0, the tape stops. If I= 1, the tape is left moving forward if the difference is positive or 0, and backward if negative. If motion = 0 when this instruction is given, it starts moving backward; otherwise it continues in the direction in which it had been going. The MBLK bits of the second word are ignored. Check one Tape Block Form: Octal code: Execution time: Operation: CHK I U 0707 + 20I + IOU 3.2 µs Find block BN, form its transfer check and leave it in the TAC and AC. The information on tape and the contents of memory are unchanged. The contents of the Tape Accumulator can be examined by using the following instructions. TAC Tape Accumulator to AC Octal code: Execution time: Operation: 0003 1.6 µs The contents of the Tape Accumulator are placed in the central processor AC. The previous C(AC) are lost; C(TAC) are unchanged. This instruction is used to verify transfer Checksums for NO PAUSE tape operations. Because this instruction uses the tape ADDER data path, 11. must not be given while a tape operation is in progress. 3.6.5 Extended Operations LINCtape Extended Operations give the programmer a more flexible addressing scheme for information transfers, additional control functions, and a tape processor maintenance facility. These operations are controlled by the contents of the Extended Operations Buffer, defined as shown in Figure 3-19. The XOB can be loaded from the AC and vice versa. The function of these bits is described in Paragraphs 3.3.6 through 3.6.12. EXTENDED OPERATIONS BUFFER (XOB) ·:=~~~ r , MARK CONDITION I ~XTENDED UNITS HOLD UNIT MOTION ENABLE TAPE - - - - - - - - - - - ' INTERRUPT MAINTEN~~~ - - - - - - - - - - - - ' ....___ _ _ _ _ DO NOT DURING ~USE EXECUTION .__________ ENABLE ~~6~~g~o MOOE Figure 3-19. Extended Operations Buffer Bit Assignments 3-45 AXO AC to XOB Octal code: Execution time: Operation: XOA 0001 1.6 µs The contents of the AC are placed in the Extended Operations Buffer. The previous C(XOB) are lost; C(AC) are unchanged. Changing these states while a tape operation is in progress may cause incorrect execution. XOB to AC Octal code: Execution time: Operation: 0021 1.6 µs The contents of the Extended Operations Buffer are placed in the AC. The previous C(AC) are lost; C(XOB) are unchanged. This instruction must not be given when the tape is in progress because the data path includes the tape ADDER. 3.6.6 Extended Address Format ; This facility releases the programmer from the limitation of block-to-block transfers, as described previously. Instead, a block transfer may begin in any register of any memory field, regardless of the settings of the Memory Field Registers. The first memory address affected in the data transfer is placed in the TMA Setup Register by the program, using the instruction TMA. When the Extended Address Mode is enabled (by setting bit 7 of the XOB to 1), all subsequent tape transfers are executed as follows. At the occurrence of a tape transfer instruction, the contents of the TMA Setup Register are placed in the TMA. The second word of the instruction is taken as an 11-bit block number, and placed in the TBN. The transfer is effected between tape and the designated area of the 4096-word memory bank specified by bits 0-2 of the XOB. The transfer is thus independent of the LINC Memory Field assignments. As in all extended memory operations, whether with tape or not, the transfer will not cross 4096 1 0 memory field bank boundaries; address 7777 is followed by address 0000. NOTE The group transfer instructions RCG and WCG cannot be used in extended address mode. TMA Load TMA Setup Register Octal code: Execution time: Operation: 3-46 0023 1.6 µs The contents of the AC are placed in the Tape Memory Address Setup Register. The previous contents of TMA Setup are lost; C(AC) are unchanged. This instruction must not be given when the tape is in progress because the data path includes the tape ADDER. Example: Read the contents of block 365 of unit 0 into memory, beginning at absolute location 105408 (0540 8 in the second 4096 10 -word bank of memory). Instruction Octal Code LDA 0540 TMA LDA 1020 AXO 1020 0540 0023 1020 1020 0001 /LOAD AC WITH STARTING ADDRESS /STARTING ADDRESS OF TARGET AREA /PLACE STARTING ADDRESS IN TMA SETUP /LOAD AC WITH EXTENDED OPERA TIO NS BITS /BANK 1; ENTER EXTENDED ADDRESS MODE /LOAD XOB FROM AC RDC 0365 0700 0365 /READ AND CHECK FROM UNIT 0 /BLOCK 365 Action The data will be read into registers 0540 8 - 1137 8 of the second 4096 10 -word bank of memory. 3.6.7 Extended Units The two Extended Units bits (XOB 1 0 - 11 ) may be thought of as an extension of the unit bit of a LINCtape instruction (bit 8). Taken together, the three bits can select one of up to eight transports which may be attached to the TC 12 tape control. The logical unit numbers are assigned by rotating the dials on the transports; they correspond to the unit select bits as follows: Extended Unit Bits (XOB) 11 10 0 0 0 0 0 0 0 0 Instruction Unit Bit 8 0 I 0 I 0 Transport Selected 0 I 2 3 4 5 0 6 7 3.6.8 Tape Interrupt Enable When this bit (XOB 5 ) is set, a program interrupt will occur whenever INTERRUPT is enabled and the TAPE DONE flag is set (i.e., the tape operation is completed). As with other LINC interrupts, control is transferred to register 0041 of memory field O; the contents of the PC are stored in register 0040. (If the central processor is in the 8 mode, the interrupt uses registers 0001 and 0000.) TAPE DONE is set by the completion of a tape instruction and cleared by the execution of a new tape instruction or the tape maintenance instruction LMR (IOT 6151) with AC 4 (1). (See Paragraph 3.6.9 and Appendix E.) 3-47 3.6.9 No Pause Condition Normally, the central processor waits until a tape operation is finished before proceeding. Such delays may be eliminated by setting the NO PAUSE condition bit (XOB 8 ). When this condition is enabled, the processor continues with the program as soon as the LINCtape instruction has been interpreted and the operation initiated. Subsequently, the program can monitor the Tape Done flag to determine when the operation has finished. The Tape Done flag is set when a tape operation has been completed and is cleared at the beginning of the next tape instruction. The flag can also be sensed and cleared by the following instructions. When in the no pause condition, a second tape instruction should not be used until the previous tape instruction has been completed. JOB LMR Load Maintenance Register Execution time: 0500 6151 5.9 µs (LINC mode) Operation: The maintenance IOT (see Appendix E) is used to test and clear the TAPE DONE flag. Octal code: (AC 0 5 = 1) Skip if Tape Done Flag is set. (AC 04 = 1) Clear Tape Done Flag Do not have other AC bits on a 1, as this instruction has many additional functions. STD Skip if Tape Done Form: Octal code: Execution time: Operation: STD I 0416 + 20I 1.6 µs If I = 0, skip the next instruction if no tape operation is in progress; otherwise, execute the next instruction. If I = 1, skip if an operation is still in progress. This instruction is identical to SXL I 16. Used in conjunction with the tape flag and tape interrupt, the NO PAUSE condition can save considerable amounts of time in central processor programming. When NO PAUSE is set, the Transfer Check is not placed in the accumulator at the end of tape instruction. The instruction TAC (see Paragraph 3.6.4) should be used to recover the Transfer Check. 3.6.10 Hold Unit Motion Normally, a tape transport stops as soon as another unit has been selected. When XOB 9 is set, however, the transport will continue in the direction it has been moving when the unit is deselected. This is a useful feature for certain operations involving several units, and must be used with caution. Note that it is not the same as the motion bit of a LINCtape instruction, which determines the motion state of a unit at the completion of an instruction only. NOTE With the Hold Unit Motion and No Pause bits both set, it is impossible to do two backto-back tape instructions and enable both units 0 and 1 for simultaneous motion. 3.6.11 MARK Condition This bit (XOB 4 ) is used in conjunction with the MARK switch on the operator's console to allow the MARK 12 program (see Chapter 7 on Program Library) to record Timing and Mark tracks on a new tape. The interaction between the switch and the XOB is designed to minimize the possibility of accidentally destroying a tape by enabling the MARK flip-flop. The flip-flop can be set only when the MARK switch is held down while an AXO instruction is being executed with AC 4 set to 1. 3-48 3.6.12 Maintenance Mode When XOB 6 is set, all timing signals and data are prevented from entering the tape control registers from the reader-writers. Instead, signals generated by IOT instructions are used as input to the tape control, in order to simulate the functions of the tape head and the tape processor. The Maintenance Mode is designed for diagnostic purposes and is not intended for general use. See Appendix E for a list of Maintenance Mode tape control instructions. 3.6.13 Tape Trap Whenever the TAPE TRAP and INSTRUCTION TRAP Special Functions are enabled (ESF with AC 2 - 3 set), LINCtape instructions are not executed. When one is encountered, a program trap to register 0140 of memory field O occurs. The Tape Trap is intended primarily for use with LINC-8 programs and the I/O Handler (LINC-8 Trap Simulator) to ensure compatibility. Also, device-independent software can make use of Tape Trap to substitute other mass storage devices, such as disks for LINCtape. 3.6.14 Tape Word Skip TWC Skip on Tape Word Complete Form: Octal code: Execution time: Operation: TWC I 0417 + 201 1.6 µs fhis instruction is used when formatting a tape using the MARK 12 Program. 3-49/3-50 CHAPTER 4 8 MODE PROGRAMMING 8-mode programming of the PDP-12 is covered in this chapter, which is divided into six sections: Organization of Memory, Memory Addressing Methods, PDP-8 Instructions, Program Interrupt, Extended Arithmetic Element, and ' Extended Memory. 4.1 ORGANIZATION OF MEMORY 4.1.1 Organization In the 8 mode, the basic 4096-word memory is divided into 32 pages of 128 words each for addressing purposes Within one of these pages, operands may be addressed directly by memory reference instructions. Access to operands across page boundaries (except for Page 0) requires indirect addressing. Executable programs may be stored in any page of memory, and program sequences may extend across several pages. The program counter is indexed over all 12 bits in the 8 mode, so that a straight-line program sequence will pass from the last word of a page to the first word of the next. A programmed jump across page boundaries, however, requires an indirect reference. The organization of one memory field in 8 mode is shown in Figure 4-1. 4.1.2 Page 0 The first page of memory (addresses 000-1 77) contains several registers reserved for special use, which the ,programmer must take into account. These are: Address 0000 0001 0010-0017 Use During a program interrupt, holds C(PC). Contains the first instruction to be executed after a program interrupt. Automatic index registers (see Paragraph 4.2.2). 4-1 PAGE (OCTAL) , 0 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 ~7 ADDRESSES 0000-0177 0200-0377 0400-0577 0600-0777 1000-1177 1200-1377 1400-1577 1600-1777 2000-2177 2200-2377 2400-2577 2600-2777 3000-3177 3200-3377 3400-3577 3600-3777 4000-4177 4200-4377 4400-4577 4600-4777 5000-5177 5200-5377 5400-5577 5600-5777 6000-6177 6200-6377 6400-6577 6600-6777 7000-7177 7200-7377 7400-7577 7600-7777 12-0121 Figure 4-1. Organization of Memory, 8 Mode 4.1.3 Extended Memory Additional 4K memory fields are organized in the same manner as the basic field. The Memory Field registers determine the assignment of fields (see Paragraph 4.6). 4.2 MEMORY ADDRESSING METHODS 4.2.1 Direct Addressing In the 8 mode, all memory reference instructions have the same structure, which is shown in Figure 4-2. 4-2 Note that only seven bits (5-11) are available for use as an address. This is just sufficient to give access to 128 registers, or exactly one page. The state of bit 4 of the instruction determines which of two possible pages the 7-bit page address references. If this bit is 1, the page address is on the current page; that is, the one in which the instruction itself is stored. If bit 4 is 0, the page address is on Page 0. Thus, a memory reference instruction has direct access to a total of 256 registers of memory; the 128 locations of Page 0, and those of the current page. Examples: To store the contents of the AC in register 150 of the current page: DCA 350 Octal code: 3350. The page address is 150; bit 4 (Page bit) set to 1 gives a total octal value of 350 for the address. To store the contents of the AC in register 150 of Page 0: DCA 150 Octal code: 3150. With the page bit set to 0, the complete octal address is 150. As one can see from these examples, it is useful to think of page addresses running from 000-1 77 on Page 0, and from 200-377 on the current page. 4.2.2 Indirect Addressing To gain access to registers outside of Page 0 or the current page, indirect addressing must be used. If bit 3 of a memory reference instruction is set to 1 (see Figure 4-2), the contents of the register designated by bits 5-11 are taken as the "effective" address of the operand. This is a full 12-bit number which gives the absolute address of any register in the 4K memory field. OPERATION COOE MEMORY PAGE A I 0 r"-.... \ 2 3 I I 4 ~ 6 7 8 9 10 t1 '-yJ INDIRECT ADDRESSING PAGE ADDRESS 12-0122 Figure 4-2. Memory Reference Instruction Format 4-3 In the following examples, as in normal 8 mode programming, the letter I is used as a mnemonic to represent the presence of a 1 in bit 3. Examples: a. To store the contents of the AC in register 100 of page 10 (absolute address 2100), using an effective address stored on the current page: Absolute Address Contents 0410 DCA I 300 0500 2100 Action /OCTAL CODE: 3700. THE /EFFECTIVE ADDRESS IS /CONTAINED IN REGISTER 500, /(PAGE ADDRESS 300) b. To store the C(AC) in register 2100, using an effective address stored in Page 0: Absolute Address Contents 0050 2100 0410 DCA I 50 Action /EFFECTIVE ADDRESS, STORED /ON PAGE 0 /OCTAL CODE: 3450. (BIT 4 = 0) Table 4-1. Summary of Addressing Methods in 8 Mode Bit 3 Bit 4 Effective Address 0 0 The operand is in Page 0 at the address specified by bits 5 through 11. The operand is in the current page at the address specified by bits 5 through 11. 0 0 The absolute address of the operand is taken from the contents of the location in Page 0 designated by bits 5 through 11. The absolute address of the operand is taken from the contents of the location in the current page designated by bits 5 through 11. 4.2.3 Autoindexing The eight registers in locations 10-17 of Page 0 have a special function when indirectly addressed. The contents of such a register are first incremented by 1; the result is taken as the effective address of the operand. This autoindexing feature allows the programmer to address a series of contiguous locations without extra address modification, as shown in the following example. 4-4 Example: To obtain the sum of 100 numbers stored in registers 1000-1077. Address Labe1 GO, LOOP, Instruction Operation CLA TAD LIST /CLEAR THE AC /PUT 777 IN AC (ADDRESS-I OF THE TABLE OF NUMBERS) DCA TAD DCA TAD /DEPOSIT IN AUTOINDEX REGISTER 10. (CLEARS AC) /PUT-I 00 IN AC (COUNT OF ADDENDS IN TABLE) /DEPOSIT IN REGISTER FOR COUNTING /C( 10) INCREMENTED BY 1, THEN USED AS /EFFECTIVE ADDRESS TO GET ADDEND FROM TABLE 10 COUNT INDEX I 10 END, IMP LOOP HLT /INCREMENT COUNT. IF RESULT IS 0000, SKIP /THE NEXT INSTRUCTION. /IF NOT FINISHED, GO BACK TO GET NEXT ADDEND /WHEN FINISHED, STOP; AC CONTAINS THE SUM LIST, COUNT, INDEX, 777 -100 0000 /ADDRESS-I OF TABLE OF ADDENDS /COUNT OF TABLES ENTRIES /HOLDS COUNT DURING EXECUTION OF PROGRAM ISZ INDEX When register 10 is first accessed, its contents are incremented from 777 to 1000, then used as the effective address to obtain the first addend. The next time around the loop, C( 10) is again incremented by 1, to 1001, for the next operand. At the end of the sequence, C(l 0) = 1077. 4.3 8 MODE INSTRUCTIONS (See Appendix B) 4.3. l Memory Reference Instructions There are six memory reference instructions: DCA, TAD, AND, ISZ, JMP, and JMS. All may use either direct or indirect addressing. When indirect addressing is specified, 1.6 microseconds is added to the execution time. DCA Deposit and Clear Accumulator Form: Octal code: Execution time: Operation: TAD DCA Y 3000 + y 3.2 µs The contents of the AC are deposited in register Y; the AC is then cleared to 0000. The previous C(Y) are lost. Two's Complement Add to Accumulator Form: Octal code: Execution time: Operation: TAD v 1000 + y 3.2 µs The contents of Y are added to the contents of the AC, using two's complement addition. If there is a carry out of bit 0, the Link is complemented; otherwise, the Link is unchanged. The previous contents of the AC are lost; the contents of Y are not changed. · 4-5 AND Logical AND to Accumulator Form: Octal code: Execution time: Operation: AND Y 0000 + y 3.2 µs The contents of the AC and the contents of Y are combined according to the Boolean AND relation, with the result left in the AC. The operation is performed on corresponding bits of each operand, independent of the other bits in the two operands. The truth table for the AND relation is shown below: 0 0 ~ I 0 1 When corresponding bits of AC and Y are both 1, the result is 1. Otherwise, the result is 0. The previous C(AC) are lost; the C(Y) are unchanged. ISZ Increment And Skip If Zero Form: Octal code: Execution time: Operation: JMP Jump Form: Octal code: Execution time: Operation: JMS ISZ Y 2000 + y 3.2 µs The contents of Y are incremented by 1. If the result is 0000, the next instruction in sequence is skipped; otherwise, the next instruction is executed. The contents of the AC are not affected. JMP Y 5000 + y 1.6 µs The address Y is placed in the PC, and the next instruction is taken from register Y; the program continues from that point. The contents of the AC are not affected. Jump to Subroutine Form: Octal code: Execution time: Operation: JMS Y 4000 + y 3.2 µs The contents of the PC are stored in Y. The address Y + 1 is placed in the PC, and the program continues from Y + 1. The contents of the AC are not affected. To return from the subroutine to the point at which the JMS was given (i.e., to the register immediately following the JMS), the instruction JMP I Y is executed. The contents of Y are taken as the effective address; since Y contains the PC stored at the time of the JMS, control returns to the calling program. 4.3.2 Operate Class Instructions This class is divided into two groups, I and II. Group I instructions include miscellaneous operations on the Accumulator and Link. Group II instructions include skips, program halt, and access to the console switches. 4-6 Operate class instructions are microprogrammable; they may be combined to provide several operations within a single instruction. However, combinations can be made only within a group; operations from different groups cannot be combined. To ease this restriction, the operation CLA (Clear the AC) is available in both groups. All Operate Class instructions require 1.6 microseconds for execution. 4.3.2.1 Operate Class: Group I - The microprogram structure of Group I instructions is shown in Figure 4-3. Any combination of these functions can be made, but the programmer must be aware of the order in which the operations are performed when the instruction is executed. This order is as follows: 1. 2. 3. 4. CLA, CLL CMA, CML IAC RAR,RAL,RTR,RTL Certain combinations of Group I operations are common enough to be assigned separate mnemonics. These are described in Paragraph 4.3.2.2. OPERATION CODE 7 A I '\ i 0 CLA CMA ~ ~ ROTATE1 ROTATE POSITION IF 0, AC AND L 2 POSITIONS RIGHT IF 1 ~ ~ I I I I I I I I '-yJ '-y-J '-y-J '-y-J '-y-J 3 CONTAINS 0 TO SPECIFY GROUP 1 4 ~ 6 CLL 7 CML 8 9 10 ROTATE AC AND L LEFT 11 IAC Figure 4-3. Group I Operate Class Instruction Format NOP No Operation Octal code: Operation: CLA Clear Accumulator Octal code: Operation: CLL 7200 The contents of the AC are cleared to 0000. Clear Link Octal code: Operation: CMA 7000 None. This instruction may be used to provide short delays ( 1.6 microseconds per instruction), or to hold a place for instructions to be inserted by the programmer. 7100 The content of the Link is cleared to 0. Complement Accumulator Octal code: Operation: 7040 The one's complement of the contents of the AC replaces the original contents of the AC. Each bit that is 0 becomes 1, and vice versa. 4-7 CML Complement Link Octal code: Operation: !AC Increment Accumulator Octal code: Operation: RAR 7012 The contents of the AC and Link, taken as a 13-bit register, are rotated two positions to the right. (See Figure 4-4.) This is the equivalent of two RAR instructions. Rotate Accumulator Left Octal code: Operation: RTL 7010 The contents of the AC and Link, taken as a 13-bit register, are rotated right one position. A bit rotated out of AC 11 enters the Link~ the bit rotated out of the Link enters AC 0 . (See Figure 4-4.) Rotate Two Places Right Octal code: Operation: RAL 7001 The contents of the AC are incremented by 1, using two's complement arithmetic. A carry out of bit 0 complements the Link. Rotate Accumulator Right Octal code: Operation: RTR 7020 The content of the Link is complemented. 7004 The contents of the AC and Link, taken as a 13-bit register, are rotated one place to the left. A bit leaving AC 0 enters the Link; a bit leaving the Link enters AC 1 1 . (See Figure 4-4.) Rotate Two Places Left Octal code: Operation: 7006 The contents of the AC and Link, taken as a 13-bit register, are rotated two positions left. (See Figure 4-4.) This is equivalent to two RAL instructions. L 0 AC 11 ~ 0 AC 11 ~ Figure 4-4. Rotation Scheme for RAR, RTR, RAL, RTL 4.3.2.2 Combined Operations: Group I - The following combined operations have been given separate mnemonics for programming convenience. 4-8 STA Set Accumulator (CLA + CMA) Octal code: Operation: STL 7120 Clear, then complement the Link. Resulting C(L) = 1. Complement and Increment Accumulator (CMA +/AC) Octal code: Operation: GLK = 7777. Set Link (CLL + CML) Octal code: Operation: CIA 7240 Clear, then complement the AC. Resulting C(AC) 7041 Complement the AC, then increment the result by 1. This gives the two's complement of the original C(AC). The two's complement of a number is defined as the one's complement plus 1. Get Link (CLA + RAL) Octal code: Operation: 7204 Clear the AC, then rotate one place left, thus putting the contents of the Link into AC 11 . This instruction is useful in multiple precision arithmetic. Other Useful Combinations - The programmer can place a number of selected constants in the AC by combining Group I operations as shown: Combination Octal Code 7201 7326 7325 7307 7327 7344 7346 7330 7332 7333 CLA CLA CLA CLA CLA STA STA CLA CLA CLA IAC STL STL CLL STL CLL CLL STL STL STL RTL IAC IAC IAC RAL RTL RAR RTR IAC Resulting C(AC) RAL RTL RTL RTR 0001 0002 0003 0004 0006 7776 (-2) 7775 (-3) 4000 2000 6000 4.3.2.3 Operate Class: Group II - The microprogram structure of Group II operations is shown in Figure 4-5. Any of these operations may be combined, but the programmer must be aware of the sequence of events. In addition, the sense of the skip instruction determines the manner in which combined skips are interpreted. If bit 8 is a 0, the logical OR of the tested conditions will cause a skip; if this bit is a 1, the logical AND of the conditions will cause the skip. In the first case, this means that the skip will occur if any one of the conditions tested is true; in the second case, the skip will occur only if all the conditions tested are true. The various combinations are described in Paragraph 4.3.2.4. The sequence of events in a Group II instruction is as follows: 1. 2. 3. 4. Skips CLA OSR HLT occurs after all other specified operations have been performed. 4-9 OPERATION CODE 7 A ; 0 \ 2 CLA SNA OR SZA DETERMINES SENSE OF SKIP HLT ~ ~ ~ ~ I 4 I I I I I I 10 I ,, '-y-1 '-y-1 3 5 6 7 '-y-' CONTAINS 1 TO SPECIFY GROUP 2 * SMA OR SPA SNL OR SZR 8 9 '-y-' '-y-1 OSR CONTAINS 0 TO SPECIFY OPERATE* CLASS THIS BIT DISTINGUISHES GROUP JI OPERATE CLASS INSTRUCTIONS FROM THE OPTIONAL EAE INSTRUCTION SET, IN WHICH THIS BIT IS SET TO 1. Figure 4-5. Group II Operate Class Instruction Format CLA ClearAC Octal code: Operation: SKP Skip Unconditionally Octal code: Operation: SNL 7450 The contents of the AC are not equal to 0000. Skip On Minus Accumulator Octal code: Skip condition: 4-10 7440 The contents of the AC equal 0000. Skip On Non-Zero Accumulator Octal code: Skip condition: SMA 7430 The contents of the Link equal 0. Skip On Zero Accumulator Octal code: Skip condition: SNA 7420 The contents of the Link equal 1. Skip On Zero Link Octal code: Skip condition: SZA 7410 The next instruction in the program sequence is unconditionally skipped. Skip On Non-Zero Link Octal code: Skip condition: SZL 7600 Clear the AC 7500 The contents of AC 0 equal 1. By convention, a negative number is one in which the most significant digit is 1. Thus, all numbers between 4000 and 7777, inclusive, are negative. The two's complement of such a number is its positive counterpart. In this sense, 7777 is equivalent to -1; 4000 is equivalent to -4000. The two's complement sum of a number and its two's complement is always zero. SPA Skip On Plus Accumulator Octal code: Skip condition: OSR 7510 The contents of AC 0 equal 0. By the convention described above, a number is positive if its most significant digit is 0. OR Switch Register With Accumulator 7404 The contents of the console switch register (Right Switches) are combined with the contents of the AC by the logical Inclusive OR reiation; the result is left in the AC. Octal code: Operation: If either bit of a corresponding pair is set to 1, the result is 1. The result is 0 only if both AC and SR bits are 0. This instruction is normally used with CLA to obtain the actual status of the Switches (see below). HLT Halt Octal code: Operation: LAS 7402 The processor stops. The PC contains the address of the register following the HLT instruction. The contents of the other processor registers are not affected. Load Accumulator From Switches ( CLA + OSR) Octal code: Operation: 7604 Clear the AC, then OR the contents of the Right Switches with C(AC). This places the status of the switches in the AC. If the switch is set to 1, the corresponding AC bit is set to 1. 4.3. 2.4 Combined Skips In Group 11 - The possible skip combinations are listed, with the conditions for a skip to occur. Combination SZA SZA SMA SZA SNL SMA SNL SMA SNL Octal Code A skip will occur if 7460 7540 7520 7560 C(AC)=OOOO, or C(L)= 1, or both C(AC)=OOOO, or C(AC 0 )= 1, or both C(AC 0 )=1, or C(L)= 1, or both C(AC)=OOOO, or C(AC 0 )=1, or C(L)=l, or any, or all of these. A skip will occur if and only if SNA SNA SPA SNA SZL SPA SZL SPA SZL 7470 7550 7530 7570 C(AC)=i=O and C(L)=O C(AC)#O and C(AC 0 )=0 C(AC 0 )=O and C(L)=O C(AC)#OOOO and C(AC 0 )=0 and C(L)=O If CLA is combined with any skip, the AC is cleared after the conditions have been tested. 4-11 4.3.2.5 Input/Output Transfer Class - These instructions, all of which have the basic operation code of 6000, are used to service peripheral devices, enable and disable the program interrupt, operate the memory extension control, change from 8 to LINC programming mode, and provide maintenance operations for the LINCtape subprocessor. Most of these instructions are described in Chapter 6 with their associated devices. The program interrupt and memory extension control are discussed with their respective instructions in Paragraphs 4.4 and 4.6 of this chapter. Mode Control - To change operating mode from 8 to LINC, the following IOT instruction is used. LINC Switch to LINC Mode Octal code: Execution time: Operation: 6141 4.25 µs Starting with the next succeeding instruction, the central processor will operate in LINC mode. 4.4 PROGRAM INTERRUPT 4.4.1 Operation To facilitate the handling of data transfers and the checking of peripheral device status, provision is made for interrupting a program when a given condition exists. In general, an interrupt occurs when a peripheral device flag is raised (i.e., when the device is available for service, when an operation has been completed, or when a specific condition, such as an alarm, occurs within the device). The Program Interrupt (PI) is enabled or disabled by the program. When it is disabled, a device flag must be sensed by means of a skip; the program is not interrupted. When the interrupt is enabled, any device flag that is connected to the interrupt system will cause the following sequence of events to occur when that flag is raised: 1. The instruction in progress at the time of the PI request is completed. 2. The contents of the program counter are stored in register 0000, and 0001 is placed in the PC. 3. Processing continues, beginning with the instruction in register 0001. 4. The PI facility is disabled. The two IOT instructions which control the PI facility are described below. ION Interrupt On Octal code: Execution time: Operation: 4-12 6001 4.25 µs The PI facility is enabled immediately after the instruction following the ION has been executed. If a PI request is waiting at the time of the ION, the interrupt will occur after the next instruction has been completed. The enabling is delayed in this manner so that a PI service routine can return to the interrupted program before a subsequent PI request destroys the contents of register 0000. /OF Interrupt Off Octal code: Execution time: Operation: 6002 4.25 µs The PI facility is disabled. Subsequent requests will not cause a Pl, although any flag causing a request may be sensed in the usual manner with an IOT skip. 4.4.2 Using the Program Interrupt Normally, when a PI occurs, the instruction in register 0001 is a JMP to a PI service routine, which examines the expected flags to determine which device or condition caused the request. The appropriate routine is then called to service the device. During this time, the PI facility is disabled. When the device service routine is completed, control normally returns to the PI handling routine for restoring the PI facility and exiting to the main program. The last two instructions of such a routine would be: ION JMP I 0 /ENABLE PI FACILITY /RETURN TO MAIN PROGRAM AT THE ADDRESS /STORED IN REGISTER 0000 The PI is not enabled until the JMP I 0 has been executed, so that the return to the main program is completed before a waiting request can cause another PI. NOTE Refer to Paragraph 3.3.15 for the discussion of additional aspects of Program Interrupt during LINC mode programming. 4.5 EXTENDED ARITHMETIC ELEMENT TYPE KE12 4.5.1 Operation The Extended Arithmetic Element (EAE), Type KE 12, adds a complete automatic multiplication and division facility to the PDP-12. Programming is provided by a class of 8 mode instructions. The AC and MQ are used to accommodate full 24-bit products and dividends, and the remainder and quotient after a division. Shifting, normalizing, and register setup instructions are included. All operands are treated as unsigned integers; the programmer must establish his own sign conventions. The normalizing instruction facilitates the writing of floating-point subroutines. 4.5.2 EAE Instructions The EAE instruction set has a basic operation code of 7401; some functions are microprogrammable, as in Operate Class instructions. The microprogram structure of the EAE class is shown in Figure 4-6. OPERATION CODE 74 3 MQA MQL CONTAINS 1 TO SPECIFY EAE GROUP ~ ~ ~ I I"-y--1I I "-y--1 4 5 6 7 8 \ CLA SCA I· I v 9 0 I 11 I 1=SCL 2•MUY 3=DVI 4•NMI 5 .. SHL 6=-ASR 7=LSR Figure 4-6. EAE Instruction Format 4-13 As with other microprogrammed instructions, EAE operations are performed in a given order. Operations can be combined in a single instruction, except that operations occurring at the same time cannot be combined with meaningful results. The order of events is as follows: 1. CLA 2. MQA, MQL, SCA 3. SCL, MUY, DVI, NMI, SHL, ASR, LSR CLA ClearAC Octal code: Execution time: Operation: CAM Clear AC and M Q Octal code: Execution time: Operation: MQA 7601 1.6 µs Clear the AC. The MQ and Link are unaffected. 7621 1.6 µs The AC and the MQ is cleared. Place MQ in AC Octal code: Execution time: Operation: 7501 1.6 µs The contents of the MQ are ORed into the AC. The C(MQ) are unchanged. NOTE All twelve bits are transferred; this is not identical to the LINC mode QAC instruction (Paragraph 3.3.11 ). MQL Load MQ/rom AC Octal code: Execution time: Operation: SCA 7421 1.6 µs The MQ is cleared. The contents of the AC are placed in the MQ. The previous C(MQ) are lost. The AC is cleared at the end of the instruction. Step Counter to AC Octal code: Execution time: Operation: 7441 1.6 µs The contents of the step counter are ORed inclusively with the contents of AC7-l l; the result is left in the AC. To obtain the actual step count, SCA is combined with CLA (combined operation code: 7641). All other EAE instructions, except NMI, require two words: the first contains the operation to be performed, the second contains the operand. In the following descriptions, the notation p + 1 designates the register containing the operand. SCL Load Step Counter Octal code: Execution time: Operation: 4-14 7403 3.2 µs The complement of the contents of bits 7-11 of p + 1 is placed in the SC. MUY Multiply Octal code: Execution time: Operation: DVI Divide Octal code: Execution time: Operation: NM! 7405 9.0 µs The number in the MQ is multiplied by the number in register p + 1. At the conclusion of this instruction the Link contains a 0. The most significant 12 bits of the product are in the AC and the least significant 12 bits are in the MQ. 7407 4.0 µs to 10.0 µs The 24-bit dividend is held in the AC (most significant part) and MQ (least significant part); the divisor is in register p + 1. At the conclusion of the division, the quotient is in the MQ, and the remainder in the AC. If the division was carried out, the Link is left clear. If either dividend or divisor is zero, the operation ends after one step and the Link is set to 1, to indicate that a divide overflow occurred. Normalize Octal code: Execution time: Operation: 7411 1.6 µs + 0.40 µs/step The AC and MQ are treated as a single 24-bit register. The combined contents of the AC and MQ are shifted left until C(AC 0 ) differs from C(AC 1 ) or until 6000 0000 is contained in the combined AC and MQ. Bits shifted out of AC 0 enter the Link; bits shifted out of the Link are lost. Zeros enter MQ 11 and are shifted up the registers. At the end of the operation, the SC contains the number of shifts performed, which is the exponent of the normalized floating point fraction. The shift pa th is shown in Figure 4-7. L 0 AC 11 LOST 0 Figure 4-7. Shift Path for NMI, SHL SHL Shift Left Octal code: Execution time: Operation: 7413 3.2 µs + 0.40 µs/step The combined contents of the Link, AC and MQ are shifted left N + I places, where N is the number contained in bits 7-11 of register p + 1. Bits shifted out of the Link are lost; zeros are shifted into MQ 11 and up the registers. The shift path is identical to that for NMI, as shown in Figure 4-7. 4-15 ASR Arithmetic Shift Right Octal code: Execution time: Operation: 7415 3.2 µs + 0.40 µs/step The combined contents of the AC and MQ are shifted right N + 1 places, where N is the number contained in bits 7-11 of register p + 1. The sign bit (AC 0 ) is reproduced in all vacated bit positions, and is also placed in the Link. Bits shifted out of MQ 11 are lost, as is the previous C(L). The shift path is shown in Figure 4-8. LOST 12-0108 Figure 4-8. Shift Path for ASR LSR Logical Shift Right Octal code: Execution time: Operation: 7417 3.2 µs + 0.40 µs/step The combined contents of the AC and MQ are shifted right N + I places, where N is the number contained in bits 7-11 of register p + 1. Bits shifted out of the MQ 11 are lost; zeros are shifted into the Link and down the register. The shift path is shown in Figure 4-9. 0 LOST Figure 4-9. Shift Path for LSR 4.5.3 EAE Programming 4.5.3.1 Multiplication - Multiplication is performed as follows: I. Load the AC with the multiplier using the TAD instruction. 2. Transfer the contents of the AC into the MQ using the MQL command. 4-16 3. Give the MUY command. Note that steps 2 and 3 can be combined into one instruction. The contents of the MQ are then multiplied by the contents of the next successive core memory location (p + 1). At the conclusion of the multiplication the most significant 12 bits of the product are held in the AC and the least significant bits are held in the MQ. This operation takes 9.0 microseconds; at the end of this time, the next instruction is executed. The following program examples demonstrate the operation of the EAE during multiplication: a. Multiplication of 12-bit Unsigned Numbers Enter with a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with high order half of product in a core memory location labelled HIGH, and with low order half of product in the AC. Program time is approximately 13 microseconds. MQL MUY MLTPLR, 0000 DCA HIGH MQA /LOAD MQ WITH MULTIPLICAND, INITIATE /MULTIPLICATION /MULTIPLIER /STORE HIGH ORDER PRODUCT /LOAD AC WITH LOW ORDER PRODUCT b. Multiplication of 12-Bit Signed Numbers, 24-Bit Signed Product Enter with a 12-bit multiplicand in AC and a 12-bit multiplier in core memory. Exit with signed 24-bit product in core memory locations designated HIGH and LOW. CLL SPA CMACMLIAC MQL TADMLTPLR SPA CMACMLIAC DCAMLTPLR RAL DCA SIGN MUY MLTPLR, 0000 DAC HIGH TAD SIGN RAR MQA SNL JMP LAST CLLCMA IAC DCA LOW TAD HIGH CMA SZL LAST, /MULTIPLICAND POSITIVE? /NO. FORM TWO'S COMPLEMENT /LOAD MULTIPLICAND INTO MQ /MULTIPLIER POSITIVE? /NO. FORM TWO'S COMPLEMENT /SA VE LINK AS SIGN INDICATOR /MULTIPLY /MULTIPLIER /LOAD LINK WITH SIGN INDICATOR /IS PRODUCT NEGATIVE? /NO, MULT DONE, EXIT /YES /COMPLEMENT RESULT /LINK USED TO COUPLE CARRY /FROM BIT 12 TO BIT 11 /OF DOUBLE-LENGTH PRODUCT IAC DCAHIGH SKP DCALOW 4-17 4.5.3.2 Division - Division is performed as follows: 1. Load the least significant 12 bits of the dividend into the AC using the TAD instruction, then transfer the contents of the AC into the MQ using the MQL command. 2. Load the most significant 12 bits of the dividend into the AC. 3. Give the DVI command. The 24-bit dividend contained in the AC and MQ is divided by the 12-bit divisor contained in the next successive core memory location (p + 1). This operation takes a maximum of 10.0 microseconds; when complete, a 12-bit quotient is held in the MQ, the 12-bit remainder is in the AC, and the Link holds a 0 if divide overflow did not occur. To prevent divide overflow, the divisor in the core memory must be greater than the 12 bits of the dividend held in the AC. When divide overflow occurs, the Link is set and the division is concluded after only one cycle. Therefore, the instruction following the divisor in core memory should be an SZL microinstruction to test for overflow. The instruction following the SZL may be a jump to a subroutine that services the overflow. This subroutine may cause the program to type out an error indication, rescale the divisor or the dividend, or perform other mathematical corrections, then repeat the divide routine. The following program examples demonstrate the use of the EAE in division. a. Division of 24-Bit Unsigned Numbers Enter with the low order 12 bits of the dividend in the AC and the high order 12 bits of the dividend in memory location labeled HIGH 12. The divisor is in memory location labeled DIVISOR upon entry. Exit with the quotient in the AC and the remainder in location labeled REMAIN. CLL MQL TAD HIGH 12 DVI DIVISOR, ( 12 BIT DIVISOR HERE) SZL JMP EXIT DCA REMAIN MQA /CLEAR LINK FOR OVERFLOW CHECK. /LOAD MQ WITH LOW ORDER DIVIDEND /LOAD AC WITH HIGH ORDER DIVIDEND /INITIATE DIVIDE /OVERFLOW? /YES - EXIT /NO - STORE REMAINDER ;AND LOAD AC WITH QUOTIENT b. Division of 24-Bit Signed Numbers Enter with the low order 12 bits of the dividend in memory location labeled LOW 12 and the high order 12 bits of the dividend in memory location labeled HIGH 12. The 12 bit divisor is in location labeled DIVISOR. Exit with the unsigned remainder in location labeled REMAIN, and the signed quotient in the AC. CLA CU TAD HIGH 12 SMA CLA JMP .+12 TAD LOW 12 CMA IAC DCA LOW 12 TAD HIGH 12 4-18 /CLEAR AC AND LINK /LOAD AC WITH HIGH ORDER DIVIDEND /DIVIDEND NEGATIVE? /NO - SKIP NEGATION /YES - LOAD AC WITH LOW ORDER DIVIDEND /NEGATE IT AND /STORE IT BACK /LOAD AC WITH HIGH ORDER DIVIDEND CMA SZL IAC DCA HIGH 12 CLL CML TAD DIVISOR SPA CMA CML IAC DCA DIVISOR SNL CMA CLL DCA SIGN TAD LOW 12 MQL TAD HIGH 12 DVI DIVISOR, (DIVISOR STORED HERE) SZL JMP EXIT DCA REMAIN MQA ISZ SIGN CMA IAC /NEGATE IT /WAS THERE A CARRY FROM LOW ORDER? /YES - INCREMENT HIGH ORDER /AND STORE IT BACK /SET LINK TO 1 FOR SIGN CHECK /LOAD AC WITH DIVISOR /IS IT POSITIVE? /NO - NEGATE IT /AND STORE IT BACK /CHECK LINK FOR SIGN OF RESULT /POSITIVE - STORE -1 IN SIGN /NEGATIVE - STORE 0 IN SIGN /GET LOW ORDER DIVIDEND /STORE IT IN MQ /LOAD AC WITH HIGH ORDER DIVIDEND /DIVIDE /OVERFLOW? /YES - EXIT ON OVERFLOW /NO - STORE UNSIGNED REMAINDER /LOAD AC WITH QUOTIENT /SHOULD QUOTIENT BE NEGATIVE? /YES - NEGATE IT 4.6 EXTENDED MEMORY When additional 4096-word memory banks are attached to the PDP-12, the Memory Extension Control provides access to the additional storage, both for programs and data. The registers of the Control are already built into the PDP-12; they are described in Paragraph 3.3.15 in relation to LINC mode memory control. In the 8 mode, the functions of these registers are the same, but only a portion of each register is used. The Instruction Field (IF), Data Field (DF), and Instruction Field Buffer (IB) registers are each five bits long; the two low-order bits of the 5-bit total pertain only to LINC mode programming operations. In 8 mode the Save Field register (Interrupt Buffer) uses only six bits; the four low-order bits are unused. 4.6.1 Registers 4.6.1. l Instruction Field Register (IF), 3 Bits - These three bits serve as an extension of the PC for determining the 4096-word field from which executable instructions are to be taken. All direct memory references are made to registers in the Instruction Field. With one exception, all JMP and JMS instructions, whether direct or indirect, are to registers within the Instruction Field. The exception is the first JMP or JMS executed after a CIF instruction is given. This causes the field to change. 4.6.1.2 Data Field Register {DF), 3 Bits - These three bits serve as an extension of the Memory Address register for determining which memory field contains the operands to be accessed by the memory reference instructions AND, TAD, DCA, and ISZ when indirect addressing is used. The Data Field and Instruction Field may be set to the same field. 4.6.1.3 Instruction Field Buffer (IB), 3 Bits - This serves as an input buffer for the IF. Except for a direct transfer from the console switches, all transfers into the IF must pass through the IB. When a CIF or RMF instruction is executed, information going to the IF is first placed in the IB. At the next occurrence of a JMP or JMS, the contents of the IB are transferred to the Instruction Field register, and programming continues in th~ new field, starting in the target register ·of the jump. 4-19 4.6.1.4 Save Field Register (SF), 6 Bits - Also called the Interrupt Buffer. When a program interrupt occurs, the contents of the IF and DF are stored in the Save Field register, as shown in Figure 4-10. After the PI has been serviced, an RMF instruction will cause the contents of the SF to be restored to the DF and IB. The SF can be examined by using the RIB instruction. 4.6.1.5 Break Field Register (BF), 3 Bits - When an external device requires extended memory for the transfer of data using the Data Break Facility, the contents of the BF specify the memory field to be accessed. 4.6.2 Instructions All Extended Memory IOT instructions require 4.3 microseconds for execution. ----, I ...__ _ _ _ _... - - - - .J I ~--.......- _....._ _ _ _ _"""'T"_ - - - - - - - - - .J r-------------1 L - - - - - - - - - - - - - - L--""--..__....__ _,__ _..__.AC 12-0113 Figure 4-10. Data Path to SF and AC CDF Change Data Field Octal code: Operation: CIF 62Nl, O~N~7 The quantity N is transferred to the Data Field register. All subsequent indirect memory references by AND, TAD, ISZ, and DCA are to the new field. Change Instruction Field Octal code: Operation: 61N2, O~N~7 The quantity N is transferred to the Instruction Field Buffer. At the occurrence of the next JMP or JMS instruction, whether direct or indirect, the contents of the IB are transferred to the IF. The effective address of the jump is placed in the PC, and the program continues from that address in the new Instruction Field. In both CIF and CDF, the number N occupies bits 6-8 of the instruction code. RDF Read Data Field Octal code: Operation: 4-20 6214 The contents of the Data Field register are ORed into AC 6 _8 • The other bits of the AC are unaffected. RIP Read Instruction Field 6224 The contents of the Instruction Field register are ORed into AC 6 - 8 . The other bits of the AC are unaffected. Octal code: Operation: RIB Read Interrupt Buffer 6234 The contents of the Save Field register (Interrupt Buffer) are transferred to the AC, as follows: Bits 0-2 (IF) are ORed into AC 6 - 8 ; bits 3-5 (DF) are ORed into AC9 - 11 . Octal code: Operation: RMF Restore Memory Field 6244 The contents of the Save Field register are placed in the Instruction Field Buffer and DF as follows: Bits 0-2 (original Instruction Field) are transferred to the IB; bits 3-5 (original Data Field) are restored to the Data Field register. This instruction is used to restore the Memory Field registers after a program interrupt has been serviced. Normally, the next instruction after the RMF would be JMP I O; the address of the interrupted program, stored in register 0000 of field 0, is placed in the PC, and the contents of the IB are placed in the Instruction Field register; the program thus returns to the main program with the Memory Fields restored to their original values. Octal code: Operation: 4.6.3 Programming All instructions, effective addresses, and directly-addressed operands are taken from the field specified by the contents of the Instruction Field Register. All indirectly-addressed operands are taken from (or are stored in) the field specified by the contents of the Data Field Register. The following chart shows the results of the four possible addressing combinations, when the IF and DF designate different memory fields. Instruction Bits Indirect Page 0 0 0 0 Fields IF DF Effective Address m n The operand is in Page 0 of Field m at the address specified by instruction bits 5-11. m n The operand is in the current page of Field m. m n The effective address of the operand is in Page 0 of Field m at the location specified by instruction bits 5-11 . The operand is in Field n, in the location specified by the contents of the effective address. m n The effective address is taken from the current page of Field m, at the location specified by instruction bits 5-11. The operand is in Field n, in the location specified by the contents of the effective address. 4-21 4.6.3. l Autoindexing - When any memory field is used as an Instruction Field, registers 10-17 of that field have autoindexing properties, just as the corresponding locations in field 0 do. This is necessary so that a program can operate correctly regardless of the actual memory field assigned by the IF. When an autoindex register is indirectly addressed, the resulting effective address is used to obtain the operand from the Data Field specified by the DF. Example: C(IF) = 2. C(DF) = 4. In field 4: In field 2: C(4326)= 1107 C(0012) = 4325 The instruction TAD C(AC) = 0. 12 is executed in field 2. C(OOl 2) + 1 ~ C(OOl 2). Resulting effective address is 4326. C( 432q) in field 4 are added to the AC. C(AC) = 1107 when the instruction is completed. 4.6.3.2 Calling A Subroutine Across Fields - The problem is to let the subroutine know which field contains the calling program, so that it can return to the proper point when it's finished. This is most easily done by setting the DF to the same field as the IF, then setting the IF to the field containing the subroutine, anct executing a JMS to read the subroutine. The subroutine uses the DF to indirectly obtain data from the calling field, then transfers the C(DF) back to the IF Buffer to return to the calling program. The following example shows a general procedure for doing this. /CALLING PROGRAM IN FIELD 2, SUBROUTINE IN FIELD 4 /CURRENT DATA FIELD IS 1 /CALLING SEQUENCE SAVES CURRENT DF, PUTS IF IN DF, CALLS /SUBROUTINE. ON RETURN, ORIGINAL DF IS RESTORED RESDF, CLA TAD KCDF RDF DCA RESDF TAD KCDF RIF DCA SETDF 0000 CIF 40 JMS I SUBADR 0000 /CDF INSTRUCTION TO AC /C(DF) TO AC 6-8 FORMS CDF IO (6211) /STORE IN SEQUENCE TO RESTORE DF /CDF TO AC /C(IF) TO AC 6-8 FORMS CDF 20 (6221) /STORE IN SEQUENCE TO SET DF /SETS DF TO CURRENT IF /SET IF BUFFER TO SUBROUTINE FIELD 4 /JUMP TO SUBROUTINE IN FIELD 4 /RESTORES ORIGINAL DF (FIELD 1) SUBADR, KCDF, SUBRTN CDF /ABSOLUTE ADDRESS OF SUBROUTINE /CONSTANT SETDF. /IN FIELD 4, THE SUBROUTINE HAS THE FOLLOWING GENERAL FORM SUBRTN, 0 TAD KCIF RDF DCA RESIF /C(PC) FROM CALLING PROGRAM /CIF INSTRUCTION TO AC /C(DF) TO AC 6-8 FORMS CIF 20 (6222) /STORE IN SEQUENCE TO RESTORE CALLING FIELD RESIF,'' 2.0 ,Ill 3.0 )U 4.0 ,Ill 12-0128 Figure 5-4. Programmed Data Transfer Timing Figure 5-4 indicates the timing of programmed data transfers. Devices which reqµire immediate service from the computer program, or which require too much computer time to discontinue the main program until transfer needs are met, can use the program interrupt (Pl) facility. In this mode of operation, the computer can initiate operation of I/O equipment and continue the main program until the device requests servicing. A signal input to the PI requesting a program interrupt causes storing of the conditions of the main program and initiates a subroutine to service the device. At the conclusion of this subroutine, the main program is reinstated until another interrupt request occurs. 5.1.l Timing and IOP Generator When the IR decoder detects an operation code of 6000 8 , it identifies an IOT instruction and the computer generates a slow cycle. The Slow Cycle signal is ANDed with TP4 to generate I/O Start and sets the I/O PAUSE flip-flop. The logic of the IOP generator consists of a re-entrant delay chain which generates three time states. These time states are gated with MB bits 11, 10, and 9 to generate IOP 1, IOP 2, and IOP 4, respectively. Note that an IOP is generated only if the corresponding MB bit is set although the 1/0 timing remains constant. At the end of each IOP, the state of the 1/0 interface is sampled by an I/O strobe pulse. Following the end of IOP 4 time, the PAUSE flip-flop is reset and the normal timing chain is restarted. 5-6 Unlike PDP-8/1, the PDP-12 does not make a timing distinction between internal 1/0 functions and normal 1/0, thus all 1/0 instructions cause the slow cycle. Instruction Bit IOP Pulse IOT Pulse Event Time 11 10 IOP 1 IOP 2 IOP 4 IOT 1 IOT 2 IOT4 1 2 3 9 Used Primarily For, But Not Restricted To Sampling Flags, Skipping. Clearing Flags, Clearing AC. Reading Buffers, Loading Buffers and Clearing Buffers. 5.1.2 Device Selector (OS) Bits 3 through 8 of an IOT instruction serve as a device or subdevice select code. Bus drivers in the processor buffer the 1 and 0 output signals of MB 3 _8 and distribute them to the interface connectors for bussed connection to all device selectors. Each DS is assigned a select code and is enabled only when the assigned code is present in the MB. When enabled, a DS regenerates IOP pulses as IOT command pulses and transmits these pulses to skip, input, or output gates within the device and/or to the processor to clear the AC. Each group of three command pulses requires a separate DS channel, and each DS channel requires a different select code (or 1/0 device address). Therefore, one 1/0 device can use several DS channels. Note that the processor produces the pulses identified as IOP 1, IOP 2, and IOP 4 and supplies them to all device selectors. The device selector produces pulses IOT 1, IOT 2, and IOT 4, which initiate a transfer or effect some control. Figure 5-5 shows generation of command pulses by several DS channels. IOT 6341 H IOT 6341 L 6 LINES FOR SELECT CODE 34 DEVICE SELECTOR 34 IOT 6342 H IOT 6342 L IOT 6344 H IOT 6344 L DEVICE 34 SELECTED 6 LINES FOR SELECT CODE 33 DEVICE SELECTOR 33 '-y-J 12 BMB LINES IOP LINES (BUSSED TO ALL DEVICE SELECTORS) 12-0124 Figure 5-5. Generation of IOT Command Pulses by Device Selectors 5-7 The logical representation for a typical channel of the DS, using channel 34, is shown in Figure 5-6. An 8-input AND gate is wired to receive the appropriate signal outputs from the MB 3 - 8 for select code 34, which. activates the channel. In the DS module, 6 input pins are connected to the complementary outputs of MB 3 - 8 , and 2 are open to receive subdevice or control condition signals as needed. Either the 1 or the 0 signal from each MB bit is connected to the AND gate when establishing the select code. The positive output of the AND gate indicates when the IOT instruction ~election selects the device, and can, therefore, enable circuit operations with the device. This output also enables three' power NAND gates, each of which produces a ground output pulse if the corresponding IOT pulse occurs. The ground output from each gate is an IOT command pulse identified by the select code and the number of the initiating IOP pulse. Three inverters receive the negative IOT pulses to produce complementary IOT output pulses. IOT 6344 H B lOP 4 H - - - - - - t IOT 6342 H BMB03 (O)H B IOP 2 H - - + - - - - - t BMB04 (1) H IOT 6341 H BMB05 (1) H B IOP 1 H --4-------t BMB06 (1) H BMB07 (0) H BMBOB (0) H AVAILABLE FOR { SUB-DEVICE ENCODING 634XH !DEVICE SELECT LINE USED FOR BAC INPUT GATING) !U-0111 Figure 5-6. Typical Device Selector (Device 34) An amplifier module can be connected in each channel of the DS to provide greater output drive. 5.1.3 Input/Output Skip (IOS) Generation of an IOS pulse can be used to test the condition or status of a device flag, and to continue to or skip the next sequential instruction based upon the results of this test. This operation is performed by a 2-input AND gate in the device connected as shown in Figure 5-7. One input of the skip gate receives the status level (flag output signal), the second input receives an IOT pulse, and the output drives the computer skip (designated SKIP BUSL) to ground when the skip conditions are fulfilled. The state of the skip bus is sampled at the end of each IOT. If the bus has been driven to ground, the contents of the program counter are incremented by 1 to advance the program count without executing the instruction at the current program count. In this manner, an IOT instruction can check the status of an I/O device flag and skip the next instruction if the device requires servicing. Programmed testing in this manner allows the routine to jump out of sequence to a subroutine that services the device tested. 5-8 PDP-12 BUILT-IN LOADS RECEIVER Si ------+---.-------t---~---------t--- PWR "ANO" GATES 4--- WITH OPEN COLLECTORS M623 OR EQUIVALENT OMIT THIS GATE IF "ONES TRANSFER" DESIRED I 81 ·011, Figure 5-9. Loading Data into the Accumulator from an External Device 5.1.6 Output Data Transfers The AC is loaded with a word (e.g., by a CLA TAD instruction sequence); then the IOT instruction is issued to transfer the word into the control or data register of the device by an IOT pulse (e.g., IOP 2), and operation of the device is initiated by another IOT pulse (e.g., IOP 4). The data word transferred in this manner can be a character to be operated upon, or can be a control word sampled by a status register to establish a control mode. The BAC lines should be gated by the select code at each device to prevent excessive loading. A special module, the MlOl, is provided for this purpose. Since the BAC interface bus lines continually present the status of the AC flip-flops, the receiving device can strobe them to sense the value in the accumulator. In Figure 5-10, a strobe pulse samples six bits of the accumulator to transfer to an external 6-bit data register. Since this is a jam transfer, it is not necessary to clear the external data register. The gates driving the external data register are part of the external device and are not supplied by the computer. The data register can contain any number of flip-flops up to a maximum of twelve. If more than twelve flip-flops are involved, two or more transfers must take place. Obviously the strobe pulse shown in Figure 5-10 must occur when the data to be placed in the external data register is held in the accumulator. This pulse, therefore, must be under computer control to effect synchronization with the operation or program of the computer. 5.1. 7. Program Interrupt (Pl) When a large amount of computing is required, the program should initiate operation of an 1/0 device, then continue the main program, rather than wait for the device to become ready to transfer data. The program interrupt facility, when enabled by the program, relieves the main program of the need for repeated flag checks by allowing the ready status of 1/0 device flags to automatically cause a program interrupt. When a program interrupt occurs, program control transfers to a subroutine that determines which device requested the interrupt, and initiates an appropriate service routine. 5-11 DATA REGISTER OF EXTERNAL DEVICE 0 0 C FF D FF 0 FF C C D FF D FF FF IOT (FROM Ml03) (STROBE PULSE) M111 INVERTERS (IF NEEDED) M101 INPUT GATES DEVICE SELECT LINE _ __.~--'----____,..__-+.----..._---1----_._-+-----_.--+------' (FROM 103) BAC INPUTS FROM COMPUTER 12-0198 Figure 5-10. Loading a Six-Bit Word into an External Device from the Accumulator In the example shown in Figure 5-11, a flag signal from a device status flip-flop operates a standard gate with no internal load. When the status flip-flop indicates the need for device service, the Program Interrupt Request bus is driven to ground and requests a program interrupt. INTERRUPT BUS M623 OR EQUIVALENT GATE GATE IS ACTIVATED WHEN FLIP-FLOP IS SET DEVICE FLAG OR STATUS FLIP- FLOP 0 I FLIP-FLOP IOT TO CLEAR FLAG 12-0135 Figure 5-11. Program Interrupt Request Signal Origin If only one device is connected to the PI facility, program control can be transferred directly to a routine that services the device when an interrupt occurs. This operation occurs as follows (example in 8 mode): Tag Address Instruction Remarks JMP SR /MAIN PROGRAM /MAIN PROGRAM CONTINUES /INTERRUPT REQUEST OCCURS /INTERRUPT OCCURS /PROGRAM COUNT (PC= 1003) IS /STORED IN 0000 /ENTER SERVICE ROUTINE 1000 1001 1002 0000 0001 5-12 SR, 2000 3001 3002 3003 3004 1003 1004 RMF ION JMP I 0000 /SERVICE SUBROUTINE FOR /INTERRUPTING DEVICE AND /SEQUENCE TO RESTORE AC, AND /RESTORE .LINK IF REQUIRED /RESTORE MEMORY FIELDS /TURN ON INTERRUPT /RETURN TO MAIN PROGRAM /MAIN PROGRAM CONTINUES In most PDP-12 systems, numerous devices are connected to the PI facility, so the routine beginning in core memory address 0001 must determine which device requested an interrupt. The interrupt routine determines the device requiring service by checking the flags of all equipment connected to the PI and transfers program control to a service routine for the first device encountered that has its flag in the state required to request a program interrupt. In other words, when program interrupt requests can originate in numerous devices, each device flag connected to the PI must also be connected to the IOS. DEVICE 2 FLAG INTERRUPT BUS SKIP BUS 81-0106 Figure 5-12. Multiple Inputs to IOS and PI Facilities 5-13 5.1. 7.1 Multiple Use of IOS and Pl - In common practice, more than one device is connected to the PI facility. In the basic PDP-12, the teletype flags are already connected. Therefore, since the computer receives a request that is the inclusive OR of requests from all devices connected to the PI, the IOS must identify the device making the request. When a program interrupt occurs, a routine is entered from address 0001 in 8 mode (0041 in Linc mode) to sequentially check the status of each flag connected to the PI and to transfer program control to an appropriate service routine for the device whose flag is requesting a program interrupt. Figure 5-12 shows JOS and PI connections for two typical devices. The following program example illustrates how the program interrupt routine determines the device requesting service (example in 8 mode): Tag Instruction Address Remarks 1000 1001 1002 /MAIN PROGRAM /MAIN PROGRAM CONTINUES /INTERRUPT REQUEST OCCURS INTERRUPT OCCURS 0000 0001 JMP FLGCK FLGCK, JOT 6341 SKP JMP SR34 IOT 6441 SKP JMP SR44 JOT 6541 SKP JMP SR54 /STORE PC (PC= 1003) /ENTER ROUTINE TO DETERMINE /WHICH DEVICE CAUSED INTERRUPT /SKIP IF DEVICE 34 IS REQUESTING /NO - TEST NEXT DEVICE /ENTER SERVICE ROUTINE 34 /SKIP IF DEVICE 44 IS REQUESTING /NO - TEST NEXT DEVICE /ENTER SERVICE ROUTINE 44 /SKIP IF DEVICE 54 IS REQUESTING /NO - TEST NEXT DEVICE /ENTER SERVICE ROUTINE 54 Assume that the device that caused the interrupt is an input device (e.g., tape reader). The following example of a device service routine might apply: Tag Instruction SR, DCA TEMP IOTXX DCA I 10 ISZ COUNT SKP JMPEND TAD TEMP RMF ION JMP I 0 5-14 Remarks /SAVE AC /TRANSFER DATA FROM DEVICE BUFFER TO AC /STORE IN MEMORY LIST /CHECK FOR END /NOT END /END. JUMP TO ROUTINE TO HANDLE /END OF LIST CONDITION /RESTORE LINK AND OTHER STATUS IF REQUIRED /RELOAD AC /RESTORE MEMORY FIELDS /TURN ON INTERRUPT /RETURN TO PROGRAM If the device that caused the interrupt was essentially an output device (receiving data from computer), the IOT then - DCA I 10 sequence might be replaced by a TAD I 10 - then - IOT sequence. 5.2 MULTI-LEVEL AUTOMATIC PRIORITY INTERRUPT The KF12B Multi-Level Automatic Priority Interrupt is designed to reduce the central processor overhead during the servicing of program interrupts. It is prewired in the EP section of the PDP-12 in racks P and R and utilizes approximately 55 M series modules. There are three major services provided automatically by the KFl 2B. a. Automatic determination of device priority and vectoring of interrupt service routines. b. Automatic saving and restoring of all major registers and machine status which include the following: PC, AC, IF, DF, MQ, LINK, FLOW, UF, MODE and the current processor level. c. Automatic stacking of the saved parameters permitting multiple levels of interrupts. Storing, or stacking, of parameters is called Pushing and restoring the CP to its original status prior to an interrupt is called Popping. The CP is in the break state for the duration of each operation. It takes five break cycles for each Push and five break cycles for a Pop. This does not affect the normal operation of the data break facility in the PDP-12. One data break device can be handled without the addition of a multiplexer. The KF 12B has the lowest priority on the bus and break requests from another device are acknowledged during push and restore operations. The KF 12B control has its own timing generator and is asynchronous with computer timing. A free running 5 mHz oscillator provides the various clocking pulses. An MISS decoder provides the enable levels to enable data on the bus. 5.2. I Interrupts Up to 15 levels of interrupts can be accommodated with each level having a two-word vector address. The interrupts can be accepted from a prewired option or from up to six external devices. A priority is assigned to each interrupt by a jumper module, M905 at location RI 6. Level 0 has the highest priority. Interrupts of a higher priority can occur after executing the first instruction in the interrupt service routine. When the KFI 2B is not enabled (API ON (0)), interrupts are processed through the interrupt cycle in the normal manner. The "TRAP" feature has not been modified by the KFl 2B, but caution should be exercised when using this feature. 5.2.2 Push When the level of the device requesting an interrupt is greater than the current machine level a Push operation is performed. The Push and Break Req flip-flops are set and the processor enters the Break cycle. The active registers and status levels are stored (pushed) in five consecutive memory locations specified by the contents of the STACK register. (Refer to Table 5-1.) The starting location of the stack is specified by the program (IOT 6776) and is automatically incremented during the push operation. The stack increments and decrements across field boundaries. The CP is always in 8 MODE at the completion of an interrupt-push operation. If the CP is in LINC mode when a Push occurs it is returned to LINC mode at the completion of a Restore command. 5-15 Table 5-1. STACK Register Location Data Stored p AC 0-11 P+l PC 0-11 P+2 MODE o; FLOW 1; LINK 2; MACHINE LEVEL 8-11 P+3 MQ 0-11 P+4 UF 1; IF 2-6; DF 7-11 P =Initial STACK address. NOTE: the subscript indicates the corresponding memory bits. 5 .2.3 Restore-"POP" (REST-IOT 6771) Every interrupt subroutine should be terminated with a Restore command. This restores the major registers and machine status from the stack and resumes programming at the memory location specified by the program counter. For every Push operation performed a Pop (restore) must be performed; however, the two operations do not have to occur in any particular sequence (see Figure 5-13). The Restore command should not be issued when the CP is in a non-interruptable state because an Interrupt Inhibit is set due to the LIP or CIF instruction, or SAVE PC is not set due to a DJR instruction. E1 EO / CORE { MEMORY 1. AN EMPTY STACK 2. PUSHING A DATUM ONTO THE STACK E2 &-i EB 4. ANOTHER PUSH ~ 3. PUSHING ANOTHER DATUM ONTO THE STACK E3 E2 ~ bd 5. POP ~ EB 6. PUSH E3 ~ bd 7, POP 12-0297 Figure 5-13. Illustration of Push and Pop Operations 5.2.4 Vectoring Each of the 15 interrupt levels has an associated vector address to specify the appropriate interrupt service routine. The vector address is transferred to the PC during the Push operation, as shown in Figure 5-14. Vector bits 0, 1, and 2 specify the memory field and are set with AC bits 3, 4, and S by an IOT. Vector bits 3 through 9 specify the seven most significant bits of the MA (0-6) and are set with AC bits 0-6 by an IOT. The interrupt level specifies memory address bits 7 through 10 with level "O" setting these bits to zero. A vector address is always an even number address; therefore, each interrupt level is allotted two memory locations. 5-16 The following are the vector address assignments, which can reside in any memory field. Vector bits 3 through 9 (MA0-6) are set to 1s by the SVEC instruction: Level Address 0 0 7740 7741 7742 7743 7744 7745 7746 7747 7750 7751 7752 7753 7754 7755 7756 7757 2 2 3 3 4 4 5 5 6 6 7 7 MEMORY FIELD Address Level 7760 7761 7762 7763 7764 7765 7766 7767 7770 7771 7772 7773 7774 7775 8 8 9 9 10 10 11 11 12 12 13 13 14 14 MEMORY ADDRESS BITS VECTOR REGISTER IOT AC 3-5 INTERRUPT LEVEL IOT 12-0298 Figure 5-14. Vector Flow Diagram 5.2.5 Maintenance Logic The maintenance logic included in the KF 12B provides the capability of checking the major portion of the option for proper operation. Two JOT instructions simulate the 15 interrupt level inputs to check the priority logic and initiate the Push operation. 5-17 Instruction Function IOT 6051 AC0-11 to LEVELS 0-11 ( 1s transfer) IOT 6052 AC 9, 10, 11 to LEVELS 12, 13, 14 ( 1s transfer) The levels remain set for only one computer cycle. This feature allows enough time to initiate a Push function when the selected level has priority and API is enabled. The KFl 2B features a new two-word instruction called push jump (PUSHJ, IOT 676X). This instruction permits jumping to subroutines across field boundaries in both Linc and PDP-8 Modes. The instruction causes the stacking of the active registers and machine status and automatically jumps to the memory location specified by the 15-bit address associated with the PUSHJ. The instruction code is (IOT) 676X and is similar to an IOT except that X defines the new memory field and the following location (P+ 1) specifies the 12-bit memory address of the subroutine. The PC, which is saved on the stack during the execution of the PUSHJ, points to the location following the twoword instruction as shown in the following example: Address 15432 15433 15434* Instruction Octal Code PUSHJ 1000 CLA 6760 1000 7200 01000 - Programming is transferred to this memory location. * Field and PC saved on stack. The program is resumed at this location following a Restore. 5. 2 .6 Programming The following is a typical example of a program to service a Teletype interrupt, which is level 5. START/CLA TAD FLDLEV SMLV CLA TAD STACK SSTK CLA TAD VEC SVEC APION NOP JMP. -1 * 6412/JMS TTYR * 6413/REST 5-18 /set stack and vector fields and machine level /set stack /set vector /enable KF 12 /wait for interrupt /go to teletype reader subroutine /restore to status prior to push *VECTOR ADDRESSES /return address saved here TTYR/XXXX CLA KRS DCA I SAVE /read keyboard buffer /save word /clear reader flag /return to restore KCC JMPITTYR FLDLEV/0017 STACK/7000 VEC/6400 5.2.7 Programming Restrictions The REST and PUSHJ commands should not be issued when the processor is in a non-interruptable state due to the following conditions: a. "Interrupt Inhibit" being set due to the execution of a CIF or LIF instruction; b. The DJR instruction is being executed or Save PC is not set due to the previous execution of a DJR instruction. If the REST command is issued and the CP is not in an interruptable condition, the Restore operation will not be performed until the condition becomes satisfactory. If the PUSHJ command is issued and the CP is not in an interruptable condition, the second word of the instruction is treated as a new instruction, and when the condition becomes satisfactory, the PUSHJ operation will not be properly executed. The ESF Disable Teletype instruction is not effective when the KF 12B is enabled (API ON (1)); the TIY and DP 12 interrupts will always be acknowledged. When the KF l 2B is not enabled (API ON (0)), the ESF instruction functions in the normal manner. Location zero is not saved on the stack; therefore, caution should be exercised when using this location in conjunction with a LINC JMP instruction. 5.2.8 Instruction List Function Octal ION Enable software interrupt system 6001 IOF Disable all interrupts 6002 APION Enable API (KF 12B) system Disable software interrupt The next instruction will be executed before an interrupt is processed. 6006 PUSH-J PUSH JUMP to 15 bit address Instruction 676X (P+l) (XXXXX) xxxx REST Restore machine to previous level 6771 SMLV* Set current machine level to AC 8-11. If AC7= 1, set stack field to AC0-2 and vector field to AC3-5. 6772 ..:-_;,.~~..~:..ti--. *The KFl 2B must be deselected to execute these instructions (i.e., API ON (0)). 5-19 Instruction Function Octal RFLD Read stack field into AC0-2, vector field into AC3-5, current level into AC8- I l (Read in complement form) 6773 RSTK Read least significant 12 bits of current stack pointer address (Read in complement form) 6774 RVEC Read vector bits 3-9 into AC bits 0-6, Trial levels into AC bits 7-10 (Read in complement form) 6775 SSTK* Set the least significant 12 stack bits to AC0-11 6776 SVEC* Set bits 309 of the vector address (MA0-6) to AC 0-6 6777 Note: When the above instructions are given in LINC mode they should be preceded by an IOB instruction. *The KF l 2B must be deselected to execute these instructions (i.e., API ON (0)). 5.2.9 DM12 The DMl 2, which is prewired' in the PDP-12, provides the capability of operating up to three data break devices in either three-cycle or single-cycle data break. Both three-cycle and single-cycle devices can be simultaneously controlled by the DM 12. The KF l 2B is a prerequisite for the DM 12 because the KF l 2B and DM 12 use the same timing and control signals, which originate in the KF l 2B. The DM 12 uses M series positive logic; all signals are clamped at 0Vand+3V. Because both options use the control and timing of the KF l 2B, the theory of operation is similar. When an external device issues a break request, the corresponding Level flip-flop is set. The three level flip-flops and the API flip-flop are decoded to determine priority. Either PRO, PR 1, or PR2 is generated and the appropriate Data Address and control signals are enabled on the bus. The EN BRK flip-flop corresponding to the device that has been decoded is set at TPl, allowing the B BREAK signal to go to the device that has control of the bus. The B BREAK signal is used to control the data on the bus for transfer between memory and the external devices. Both options use the same IOTs; thus, when testing the DM 12 the KF l 2B must be disabled using jumpers that allow only the DM 12 priorities to be enabled. The DM 12 priorities are determined by cable location. Two cables from each device are used for the data address, data bits, and status signals. The cables from the device having the highest priority are inserted in locations P20 and P2 l as illustrated in Figure 5-15. COAXIAL CABLES TOTAL LENGTH ON BUS 45ft. MAX. EM12 BAC EP 12 BMB DEVICE 0 I /0 BUS* KFl2 OM 12 P20 P21 P22 DEVICE 1 It HIGHEST PRIORITY DATA ADDRESS DATA BITS DATA ADDRESS J DEVICE 2 * LOWEST PRIORITY J DATA BITS P23 P.N DATA ADDRESS DATA BITS P25 12-0299 COAXIAL CABLES -MAX, LENGTH 25 ft. *If the priority interrupt system is used in the KF12B this cable is connected separately from each device. (ref. BS-KF12-CAB). Figure 5-15. DM12 Cable Diagram 5-20 5.3 DATA BREAK TRANSFERS The Data Break facility allows an I/O device to transfer information directly with the PDP-12 core memory on a cycle-stealing basis. The Data Break is ~articularly well suited for devices which transfer large amounts of information in block form, and can be expanded to accommodate more than one device by using the DMOI or DM04 multiplexers. The DMOI will multiplex up to seven devices and is a negative bus option. The DM04 (positive bus) will multiplex three devices and up to three DM04s may be added for a total of nine devices. Peripheral 1/0 equipment operating at high speeds can transfer information with the computer through the data break facility more efficiently than through programmed means. The combined maximum transfer rate of the data break facility is 6.5 million bits per second. Information flow to effect a Data Break transfer with an I/O device appears in Figure 5-16. MEMORY EXTENSION CONTROL TYPE MCl2 MEMORY ADDRESS REGISTER (MAI CORE MEMORY MEMORY BUFFER REGISTER !MBI EXTENDED DATA ADDRESS 11 BIT) DATA ADDRESS (12 BITS) DATA INFORMATION 112 BITS IN) DATA INFORMATION (12 BITS OUT) ADDRESS ACCEPTED WORD COUNT OVERFLOW BREAK STATE DATA BREAK FACILITY ..-- CONNECTIONS TO INPUT I OUTPUT DEVICE ......- ~BREAK REQUEST TRANSFER t-_ DIRECTION (IN l ~CYCLE SELECT --- + t- CA INHIBIT _ INCREMENT MB I"'" 12-0123 Figure 5-16. Data Break Transfer Interface Block Diagram In contrast to programmed operations, the Data Break facilities permit an external device to control information transfers. Therefore, Data Break device interfaces require more control logic circuits, causing a higher cost than programmed-transfer interfaces. Data Breaks are of two basic types: single-cycle and three-cycle. In a single-cycle Data Break, registers in the device (or device interface) specify the core memory address of each transfer and count the number of transfers to determine the end of data blocks. In the three-cycle Data Break, two computer core memory locations perform these functions, simplifying the device interface by omitting two hardware registers. 5-21 In general terms, to initiate a Data Break transfer of information, the interface control must do the following: a. Specify the affected address in core memory. b. Provide the data word by establishing the proper logic levels at the computer interface (assuming an input data transfer), or provide input gates and storage for the word (assuming an output data transfer). c. Provide a logical signal to indicate direction of data word transfer. d. Provide a logical signal to indicate single-cycle or three-cycle break operation. e. Request a Data Break by supplying a proper signal to the computer data break facility. 5 .3 .1 Single-Cycle Data Breaks Single-cycle Data Breaks are used for input data transfers to the computer, output data transfers from the computer, and memory increment data breaks. Memory increment is a special Data Break in which the content of a memory address is read, incremented by 1, and rewritten at the same address. It is useful for counting iterations or external events without disturbing the computer program counter (PC) or accumulator (AC) registers. 5.3.2 Input Data Transfers Figure 5-17 illustrates timing of an input transfer data break. The address to be affected in core is normally provided in the device interface in the form of a 12-bit flip-flop register (data break address register) which has been preset by the interface control by programmed transfer from the computer. External registers and control flip-flops supplying information and control signals to the Data Break facility and other PDP-12 interface elements are shown in Figure 5-18. The data register (DR in Figure 5-18) holds the 12-bit data word to be written into the computer core memory location specified by the address contained in the address register (AR in Figure 5-17). Appropriate output terminals of these registers are connected to the computer to supply ground potential to designate binary 1s. Since most devices that transfer data through the Data Break facility are designed to use either single-cycle or three-cycle breaks, but not both, the Cycle Select signal can usually be supplied from a stable source (such as a ground connection or a +3v clamped load resistor), rather than from a bistable device as shown in Figure 5-18. Other portions of the device interface, not shown in Figure 5-18, establish the data word in the input buffer register, set the address into the address register, set the direction flip-flop to indicate an input data transfer, and control the break request flip-flop. These operations can be performed simultaneously or sequentially, but all transients should occur before the data break request is made. When the Break Request is recognized, the computer completes the current instruction, generates an Address Accepted pulse (at TPl, the beginning of the break cycle) to acknowledge receipt of the request, then enters the Break state to effect the transfer. The Address Accepted pulse can be used on the device interface to clear the BREAK REQUEST flip-flop, increment the content of the address register, etc. If the Break Request signal is removed before TP2 time of the data break cycle, the computer performs the transfer and returns to programmed operation. 5-22 TP2 +3 BREAK REQUEST SIGlllAL lllllPUT TO PROCESSOR) BREAK SYlllC FLIP FLOP llNTERlllALI TP:S TP4 TP5 I COMPUTER TIME I Tl'Z TI'S I I I SAMPLED AT OFF-PAUSE BY PROCESSOR** ----•I D-------------' SET AT SAMPLE TIME TP4 TPI TPI I TP2 TP:S I I SIGlllAL MUST GO TOH\/ AT START Of" AOOMSS ACCEPT PULSE IF NEXT CYCLE IS TO IE A BREAK ----+ SAMPLE AT TPI ____..I 3 CYCLE CYCLE SELECT !SAMPLE TO PROCESSOR I TPI PREVIOUS ClCLE-..... - - - - - - - - I M t E A K CYCLE - - - - - - - - . - - N E X T CYCLE USED TO SELECT BREilK CYCLE AT TP I : I SAMPLED AT TPI t-"-TYPICALLY HARDWIRED FOR A GIVEN DEVICE 1 CYCLE 8-BREAK SIGlllAL IOUTPUT TO 110 OE\/ICEl Ett«l OF llM:AIC CYCLE ____, DATA ADDRESS INPUT LEVELS (INPUT TO PROCESSOR) EXT.MEM. ADDRESS READ READ AT TP I BY PROCESSOR EARLIEST TIME POSSIBLE TO REMOVE AOORESS IS AT START OF BREilK CYCLE TPI -TP:S ADDRESS ACCEPT PULSE !OUTPUT TO I 10 DEVICE I GND IN (+311) TRANSFER DIRECTION I INPUT TO PROCESSOR) lllUST BE SET UP AT TP2 SIGNAL INPUT TO MB *DATAlllllPUT TO PROCESSOR) - ----- AVAIL (+3\1) LATEST POSSIBLE TIME TO SPECIFY INPUT DATA IS TP2 NOT AVAIL (GND) "Ou TPUT DATA AVAILABLE IN MB !OUTPUT TO 110 DEVICE) r...----CANCHAlllG£ ANYTIME AFTER TP:S ~---------------------- OUT(GND) SAMPLED AT TP:S BY PROCESSOR lllVAIL(+3V) AVAILABLE AT TP 3 TIME DURING WHICM DATA MUST !IE STllOllED BY 1/0 OE\/ICE NOT AVAIL (+3\1) - - - - - - - - - - - - - - - - - - - - - - - - - - - ' BTS5 !OUTPUT TO 110 DEVICE I BTS2 !OUTPUT TO 110 DEVICE) G:: --------~~L------------------'~~-------------~- +3\/ GNO *WORD COUNT OVERFLOW !OUTPUT TO l/ODE\/ICEl +3\1 - - - - - - - - - - - - - - - - - - - - - - - - - - . OCCURS If' MEMORY INCREMENT IS FIEOUESTEO AlllD THE WORD COUNT OVERFLOWS GNO * SIGNAL NOT USED FOR INPUT TRANSFERS SHOWN FOR REFERENCE ONLY **OFF-PAUSE OCCURS 200n1 BEFORE TP5. IF OFF IOP SAMPLES BREAK REQUEST. IOP INSTRUCTION IN PROCESS, 12-0130 Figure 5-17. Single Cycle Data Break Input Transfer Timing Diagram 5.3.3 Output Data Transfers Timing of operations occurring in a single-cycle output Data Break is shown in Figure 5-19. Basic logic circuits for the device interface used in this type of transfer are shown in Figure 5-20. Address and control signal generators are similar to those discussed previously for input data transfers, except that the Transfer Direction signal must be at ground potential to specify the output transfer of computer information. An output data register (OB in Figure 5-20) is usually required in the device interface to receive the computer information. The device must supply strobe pulses for all data transfers out of the computer (programmed or data break) since circuit configuration and timing characteristics differ in each device. 5-23 ADDRESS 0 L 0 ARO ADDRESS 1 L 0 AR1 ADDRESS 11 L 0 AR11 BREAK REQUEST L 0 +3 BR ADDRESS ACCEPTED (FROM GROUND TO REQUEST BREAK CYCLE TO PDP-12 PDP-12 l DATA 0 L 0 ORO DATA 1 L 0 DR1 DATA It L 0 DR11 DIRECTION (+3 FOR INPUT) 0 D r- CYCLE SELECT NOTE: AR=ADDRESS DR= DATA REGISTER D= TRANSFER DIRECTION (FLIP-FLOP) BR= BREAK REQUEST(FLIP-FLOP) Figure 5-18. Device Interface Logic for Single-Cycle Data Break Input Transfer 5-24 12-0300 COMPUTER TIM[ TP3 T'f I I '"'2 TPI rn TPS I ~~ous.!. ,.....-----------------------------I I MEAi< CYCLE - - - - - - -.....--NEXT CYCLE +3 BREAK REQUEST SIGNAL (INPUT TO PROCESSOR! BREAK SYNC FLIP FLOP (INTERNAL) SIGNAL MUST GO TO UV AT STMT Of' AOOM:SS ACCEPT PULSE IF NEXT CYCLE IS TO BE A MEA1 ----1 0-----------SET AT SAMPLE TIME SAMPLE AT TPI : I USED TO SELECT BREAK CYCLE AT TP I 3 CYCLE CYCLE SELECT !SAMPLE TO PROCESSOR! 8-BREAK SIGNAL (OUTPUT TO 110 DEVICE I DATA ADOllESS INPUT LEVELS llNPUT TO PROCESSOR) 1 CYCLE +3V t= -----------------~ START Of' llREAll CYCLE GNO +3V GN0------- EXT. MEM ADDRESS READ READ AT TP I BY PROCESSOR EARLIEST TIME POSSIBLE TO 11£MOVE AOOll£SS IS AT START Of llllEAll CYCLE +3V TPI -TP3 ADDRESS ACCEPT PULSE !OUTPUT TO 110 DEVICE! GNO IN (+3V) TRANSFER DIRECTION !INPUT TO PROCESSOR) S!GfjAL INPUT TO MB *DATA(INPUT TO PROCESSOR! LATEST l"OSSlllLE TIME IS TP2 . .- - - - C A N 0tAHGE AHYTllllE AFTER TP 3 OOT(GNDI AVAIL (+5Vl HOT AVAIL (GNO) OUTPUT DATA AVAILABLE IN MB !OUTPUT TO 110 DEVICE) .....IL(·HV) AVAILABLE AT TP 3 TIME DlA'llNG WHICH DUA llJST Bf STR08£D BY 110 DEVICE NOT A\AllL {+311) Mii INCREMENT REQUEST llNPUT TO PROCESSOR I NO REQU£ST{+3V) MUST OCCUR EARIER THAN TP 2 REQUEST (GNO) BTS 5 !OUTPUT TO 110 DEVICE I r- ~Hit,£1/J },.m>. ......*1...._M_u_s_T_oc_c_UR_o_N_LY_WHE __ ,. _a_BRE_All_·_·_... .... kR,..,E,._.oy ... TPI +311 GRN BTS 2 !OUTPUT TO l/D DEVICE) +3V &NO +3\1 *WORD COUNT OVERFLOW (OUTPUT TO !10 DEVICE l OCCUflS IF MEMORY INCREMENT IS REQUESTED ANO THE WORD COUNT OVERFLOWS GND *SIGNAL NOT USED FOR OUTPUT TRANS FE RS SHOWN FOR REFERENCE ONLY OCCURS 200ns BEFORE TP5. IF ** OFF-PAUSE OF< IOP SAMPLES BREAK REQUEST. IOP 1~5TRUCTION 11' PROCl'SS, 12-0IZ9 Figure 5-19. Single-Cycle Data Break Output Transfer Timing Diagram 5-25 ADDRESS 0 L AR Ill ADDRESS I L 0 AR 1 ADDRESS 11 L AR 11 BREAK REQUEST L 0 +3v BR ' - - - - - - - - - - - - - - - - - - - - - - - - - - ADDRESS ACCEPTED L 0 OB~ BREAK ENABLE BTS5 B BREAI< BMBllJ 0 OBI DIRECTION (0 FOR OUTPUT! 0 BMBI DIRECTION NOTE: OB' OUTPUT BUFFER AR,ADDRESS REGISTER BR' BREAK REQUEST (FLIP-FLOP) 0811 BMBll STROBE BTS 2 +3 - - - - - - - - - CYCLE SELECT Figure 5-20. Device Interface Logic for Single-Cycle Data Break Output Transfer 5-26 When the Break Request is recognized the computer completes the current instruction and generates an Address Accepted pulse as it enters the Data Break cycle. At TPl time, the address supplied to the PDP-12 is loaded into the MA, and the Break state is entered. Not more than 900 nsec after TP 1 (at time TP3), the contents of the device-specified core memory address are read and available in the MB. (This word is automatically rewritten at the same address during the last half of the Break cycle, and is available for programmed operations when the Data Break is finished.) Data Bit signals are available as static levels of ground potential for binary Os and +3v for binary ls. The MB is changed at time TP3 of each computer cycle, so the data word is available in the MB for approximately 1.6 microseconds to be strobed by the device interface. Generation of the strobe pulse by the device interface can be synchronized with computer timing through use of timing pulses BTS2 or BTS5, which are available at the computer interface. In addition to a timing pulse (delayed or used directly from the comput~r), generation of this strobe pulse should be gated by condition signals that occur only during the Break cycle of an output transfer.' Figure 5-20 shows typical logic circuits to effect an output data transfer. In this example, BTS5 and B BREAK set the BREAK ENABLE flip-flop, which remains set for one computer cycle (unless successive cycles are requested). This enabling signal loads the buffered MB lines into the data inputs of a D type flip-flop. At BTS2 time, the data will be clocked into the Output Buffer flip-flops. Note that BTS2 can generate a strobe pulse only during a BREAK ENABLE cycle. Interface input gates are MlOl; output bus drivers are M6 23. By careful design of the input and output gating, one register can serve as both the input and the output buffer register. Most DEC options using the Data Break facility have only one data buffer register with appropriate gating to allow it to serve as an output buffer when the Transfer Direction signal is at ground potential or an input buffer when the Transfer Direction signal is +3v. 5.3 .4 Memory Increment In this type of Data Break the contents of core memory at a device-specified address are read into the MB, are incremented by 1, and are rewritten at the same address within one 1.6-microsecond cycle. This feature is particularly useful in building a histogram of a series of measurements, such as in pulse-height analysis applications. For example, in a computer-controlled experiment that counts the number of times each value of a parameter is measured, a Data Break can be requested for each measurement, and the measured value can be used as the core memory address to be incremented (counted). Signal interface for a memory increment Data Break is similar to an output transfer Data Break except that the device interface generates an Increment MB signal and does not generate a strobe pulse (no data transfer occurs between the PDP-12 and the 1/0 device). Timing of memory increment operations appear in Figure 5-21. 5-27 COMPUTER TIME TP2 TP3 TP4 I I I TP5 Tl'I I PREVIOUS Tl'! l Tl'll T""' T,., T"I TP2 TP3 I I I I I I CYCLE-•..,.. ....- - - - - - - B M A I C CYCLE --+ M +3 BREAK REOUEST SIGNAL (INPUT TD PROCESSOR) --------1+ ... --NEXT CYCLE ~-----------------------------SIGNAL MUST GO TO+:W AT START CW AOOllESS "4:CEPT PULSE IF NEXT CYCLE IS TO Bf A BREAK SAMPLED AT OFF- PAUSE BY PROCESSOR GND - - - - - - - - - - - - - - ' ' - - - - - ' " ' " ' SAMPLE_..,: : BREAK SYNC FLIP FLOP (INTERNAL I 3 CYCLE CYCLE SELECT !SAMPLE TO PROCESSOR) B-BREAK SIGNAL !OUTPUT TO 110 DEVICE) DATA ADDRESS INPUT LEVELS (INPUT TO PROCESSOR) USED TO S£LECT MCAii CYCLE AT TP I _::SE~T~A~T_S:'.A~M'._'.:P.:_L.:_E...!,T_!!IM~E;_-====:::!~ AT TP I ~SAMPLED AT TPI TYPICALLY HARDWIRED FOR A GIVEN DEVICE I 1 CYCLE I--- +3V -----------------~ GNO .. 311 GNO------- XT.MEM. ADDRESS READ -+ READ AT TP I BY PROCESSOR START Of' BREAK CYCLE ENO OF MUK CYCLE ___, EAltLl[ST TIME POSSIBLE TO REMOVE AOOR£SS IS AT START Of MEAll CYCLE +3V ADDRESS ACCEPT PULSE IOUTPUT TO I 10 DEVICE) TP I -TP 3 GND IN (+311) TRANSFER DIRECTION !INPUT TD PROCESSOR) SIGNAL INPUT TO MB *DATA(INPUT TO PROCESSOR) LATEST POSSllU: TIME IS Tl"2 OUT(GNO) LATEST POSSIBLE TIME TO SPECll'Y INPUT DATA IS TP2 f'K>T AVAIL (GNO) *OUTPUT DATA AVAILABLE IN MB !OUTPUT TO 110 DEVICE) . . - - - - - C A N OWtlGE AH'ITlllilE AFTER TP! A\IAIL (+3Vl AllAIL(+3V) AVAILABLE AT TPI TlllilE DlltlNG MOCH DATA ailJST IE STllOIED IY l/O DEVICE NOT AVAIL (+3V) - - - - - - - - - - - - - - - - - - - - - - - - - _ . Mii INCREMENT REQUEST !INPUT TO PROCESSOR) NO REQUEST(+3Vl MUST FALL EARLIER THArol TP 2 MUST OCCUR QlllLY WHEN a llflEAll • 1 REQUEST (GNO) BTS S !OUTPUT TO I 10 OE VICE) HV GRN llTS 2 (OUTPUT TO 110 DEVICE) +3V GND I.____ _ ___, +3V II WORD COUNT OVERFLOW (OUTPUT TO l/OOEVICE) OCCIMS If lilEMOl'IY INCREM£NT IS lt£0U£STED ANO THE WOl'O COUNT OVERFLOWS GND *SIGNAL NOT USEO SHOWN FOft REFERENCE OfilLY OCCURS 200ns BEFORE TP5. IF IOP INSTRUCTION ** OFF-PAUSE IN PROCESS, OFF IOP SAMPLES BREAK REQUEST. 12-0131 Figure 5-21. Memory Increment Data Break Timing Diagram An interface for a device using memory increment Data Breaks must supply twelve Data Address signals, a Transfer Direction signal, a Cycle Select signal, and a Break Request signal to the computer Data Break facility as in an output transfer data break. In addition, a ground potential increment MB signal must be provided at least 250 nanoseconds before time TP3 of the Break cycle. The signal can be generated in the device interface by ANDing the B Break Computer Output signal, the output transfer condition of the Transfer Direction signal, and the Condition signal in the device that indicates that an increment operation should take place. When the computer receives this Increment MB signal, it forces the MB control element to generate a Carry Insert signal at time TS3 to increment the contents of the MB. 5-28 5 .3 .5 Three-Cycle Data Breaks Timing of input or output three-cycle Data Breaks is shown in Figure 5-22. The three-cycle Data Break uses the block transfer control circuits of the computer. The block transfer control provides an economical method of controlling the flow of data at high speeds between PDP-12 core memory and fast peripheral devices, e.g., drum, disc, magnetic tape and line printers, allowing transfer rates in excess of 208 kHz. T T 'i. T BREAK REQUEST SIGNAL (INPUT TO PROCESSOR) GND lSAMPLED AT OFF· PAUSE BY + V PROCESSOR* 3 CYCLE SELECT (INPUT TO PROCESSOR) TP2 TP3 TP4 I I I I 14--- TP5 WORD COUNT STATE j SET AT SAMPLE TIME BREAK SYNC FLIP· FLOP (INTERNAL) TPI o------- i---b I TPI TP2 I I -+- TP3 T. . TP5 I I I CUAAENT ADOllESS STATE TPI TP2 TP3 TP4 TP5 TPI TP2 TP5 I I I I I I I I --+--- llREAK CYCLE ---t TP4 TP5 I I TPI I SAMPLW AT TPI +3V - - - - - SAMPLED AT TP t TYPICALLY HARDWIRED FOR A GIVEN DEVICE GND I EXT. MEM. ADDRESS SAMPLED DATA ADDRESS INPUT LEVELS (INPUT TO PROCESSOR\ f4- SAMPLED AT TPI IF FF REGISTER SUPPLIES THESE INPUTS TIMING IS IDENTICAL TO THAT SHOWN ON FIG 5-13 I ADORE SS ACCEPTED PULSE !OUTPUT TO 110 0£\llCE) GND TRANSFER DIRECTION (INPUT TO PROCESSOR) IN (+-3Vl OUT(GNDl l 1 L-----------------S-AMP-LE-D-AT-T-P3_0F_8R£-AK_c_vc_LE_~_....I __, AVAIL. DATA SIGNAL INPUT TO MB (INPUT TO PROCESSOR) LATEST l'OSSIBLE TIME TO SF'ECFY INPUT DlTA IS !!IOO NS llEFORE TP 2--: SAMPLED AT T~! ev PROCESSOR NOT AVAIL AVAIL. OUTPUT DATA AVAILABLE IN MB !OUTPUT TO l/O DEVICE! WORD COUNT OVERFLOW (OUTPUT TO 110 DEVICE I AVAILABLE AT T"5 LATEST POSSIBLE TIME TO SPECIFY 1. . HIBIT CA INCREMENT IS 300 NS BEORE TPl 1"4HIBIT CA INCREMENT !OUTPUT TO PROCESSOR) TP3 TP3 OCCURS ONLY DURING LAST TRANSFER OF A BLOCK TRANSFER GND +3V I ----9'4 SAlf LED AT TP3 BY PROCESSOR GND 8 BREAK SIGNAL !OUTPUT TO 110 OEVICEI +3v ~-~---~------~~--~---~---. ~-----START OF BREAK CYCLE~---------'r--ENO OF BREAK CYCLE GND BTS 5 (OUTPUT TO 110 OEVICEl + n 3 BTS 2 !OUTPUT TO 110 DEVICE) V GND _ _ __. :::1 n '---------' n *OFF-PAUSE OCCURS 20001 BEFORE n '---------' n TP5. IF IOP INSTRUCTION IN PROCESS, OFF n nSEFORSAllllPLING OUTPUT DATA .___ _ _ _ __, '--------' n IOP SAMPLES BR'-E-AK_R_E-QU-E-ST-._ 11 __. '----- 12 ·01!2 Figure 5-22. Three-Cycle Data Break Timing Diagram The three-cycle Data Break facility provides separate current address and word count registers in core memory for the connected device, thus eliminating the necessity for flip-flop registers in the device control. When several devices are connected to this facility, each is assigned a different set of core locations for word count and current address, allowing interlaced operations of all devices as long as their combined rate does not exceed 208 kHz. The device specifies the location of these registers in core memory, and thus the software remains the same, regardless of what other equipment is connected to the machine. Since these registers are located in core memory, they may be loaded and unlo-dded directly without the use of IOT instructions. In a procedure where a device request to transfer data to or from core memory, the three-cycle Data Break facility performs the following sequence of operations: a. An address is read from the device to indicate the location of the word count register. This address is always the same for a given device; thus it can be wired in and does not require a flip-flop register. b. The contents of the specified address are read from memory and I is added before rewriting. If the contents of this register become 0 as a result of the addition, a WC Overflow pulse will be transmitted to the device. To transfer a block of N words, this register is loaded with -N during programmed initialization of the device. After the block has been fully transferred this pulse is generated to signify completion of the operation. c. The next sequential location is read from memory as the current address register. Although the contents of this register are normally incremented before being rewritten, an increment CA inhibit(+ I -+ CA Inhibit) signal from the device may inhibit incrementation. To transfer a block of data beginning at location A, this register is program initialized by loading with A-1. d. The contents of the previously read current address are transferred to the MA to serve as the address for the data transfer. This transfer may go in either direction in a manner identical to the single-cycle Data Break system. The three-cycle Data Break facility uses many of the gates and transfer paths of the single-cycle Data Break system, but does not preclude the use of standard Data Break devices. Any combination of three-cycle and single-cycle Data Break devices can be used in one system, as long as a multiplexer channel is available for each. Two additional control lines are provided with the three-cycle data break. These are: Word Count Overflow - A level change from GND to +3V, from TP3 of the cycle requesting the word count to TP3 of the next cycle is transmitted to the device when the word count becomes equal to zero. Increment CA Inhibit - When ground potential, this device-supplied signal inhibits incrementation of the current address word. In summary, the three-cycle Data Break is entered similarly to the single-cycle Data Break, with the exception of supplying a ground-level Cycle Select signal to allow entry of the WC (Word Count) state to increment the fixed core memory location containing the word count. The device requesting the break supplies this address as in the single-cycle Data Break, except that this address is fixed and can be supplied by wired ground and +3V signals, rather than from a register. Following the WC state, a Current Address (CA) state is entered, in which the core memory location following the WC address is read, incremented by one, restored to memory, and used as the transfer address (by MB-+ MA). Then the normal Break (B) state is entered to effect the transfer. 5.4 INTERFACE DESIGN AND CONSTRUCTION This section describes the PDP-12 interface techniques, available modules, interface conventions, and interface connections. S.4.1 PDP-12 Interface Modules PDP-12 interfacing is constructed of Digital FLIP-CHIP modules. The Digital Logic Handbook describes more than 150 of these modules, their component circuits, and the associated acessories; i.e., power supplies and. mounting panels. The user should study this catalog carefully before beginning the design of a special interface. The interface modules of the PDP-12 are the M111, M906, MS 16, M660, and M623 modules. Interface signals to the computer use either a combination of the M111 and M906 modules or the MS 16 module. Interface signals from the computer will originate from a combination of M623 and M906 modules for data signals, and M660 modules for timing signals. S.4.1.1 M111/M906 Positive Input Circuit (See Figure 5-23) - The Ml 11 Inverter module is used in conjunction with the M906 Cable Terminator module, which clamps the input Jo prevent excursions beyond +3 volts and ground. The M906 also provides the pullup resistors to +5 volts. 5-30 -----------, I B1 I I I I I I OUTPUT SIGNAL TO PROCESSOR I I I I M 111 (161NVERTERS) ,- A1 I I -------, +5V I I M906 I (t8 CIRCUITS) I I Bt POSIT I VE BUS INPUT s I GNAL I (FROM EXTERNAL DEVICE) L __________ _ _j 12-0136 Figure 5-23. Typical Ml l l/M906 Positive Input Circuit 5.4.1.2 M516 Positive Bus Receiver Input Circuit (See Figure 5-24) - Six four-input NAND gates with overshoot and undershoot clamp on one input of each gate. Pullup resistors connected to +SV are also provided. I -----------, 8' OUTPUT s I G N AL TO PROCESSOR I I I I I ( M5t6 s Ix GATES ) I I I I I D I } USED ~: INTERNALLY +5V I Al POSITIVE BUS INPUT SIGNAL (FROM EXTERNAL DEVICE) L __________ _ I I I I I I I I I _j 12-0136 Figure 5-24. Typical MS 16 Positive Bus Receiver Input Circuit 5 .4.1.3 M623/M906 Positive Output Circuit (See Figure S-25) - The M623 Bus Driver module contains twelve circuits with negative NOR gates. Used in conjunction with the M906 Cable Terminator module, the output is clamped to prevent excursions beyond +3 volts and ground. Output can drive +5 milliamperes at the high level and sink 20 milliamperes at the low level. 5-31 , -- - - - - - - - - - - - ,I I M906 (!8 CIRCUITS) I I POSITIVE BUS OUTPUT SIGNALS I (TO EXTERNAL DEVIC£) I I I I I ---, +5V I E1 I I I I Al 81 OUTPUT SIGNALS FROM PROCESSOR L - - - - - - - - - - - _J 12.-0136 Figure 5-25. Typical M623/M906 Positive Output Circuit 5.4.1.4 M660 Bus Driver Output Circuit (See Figure S-26}° - Three circuits which provide low impedance 100-ohm tenninated cable driving capability using M Series levels or pulses of duration greater than 100 nanoseconds. The output can drive 5 ma at the high level and sink 20 ma at the low level, in addition to termination current required by the G7 l 7 termination module. The M660 module is used in the PDP-12 for the following output signals: IOP 1, IOP 2, IOP 4, TS 2, TS 5 -----------, rI I POSITIVE BUS OUTPUT SIGNAL (TO EXTERNAL DEVICE) I M660 I (3 CIRCUITS) I L - - I I 02 I I I I I I I OUTPUT SIGNAL FRO:_PROCESSOR - - - - _J IZ-0136 Figure 5-26. M660 Terminated Bus Driver Output Circuit 5.4.1.5 Module Selection for Interface Circuits of Peripheral Equipment - Two FLIP-CHIP modules are of particular interest in the design of equipment to interface with the PDP-12. Complete details on these and other FLIP CHIP modules can be found in the Digital Logic Handbook. 5-32 5.4.1.6 M103 Device Selector (See Figure 5-27) - The M103 selects an input/output device according to the code in the instruction word (being held in the memory buffer during the IOT cycle). M103 module includes diode protection clamps on input lines so that it may be used directly on the PDP-12 positive bus. H1 J1 LI N1 M1 U2 02 E2 F2 H2 J2 K2 L2 N2 >--~-O_;.Ev_1_c_E~S..;;E_L.;;...EC_T..;;E_o_.(') v 2 BMB 03(0) BMB 04(0) BMB 05(0) BMB 06(0) BMB 07(0) BMB 08(0) NOT USED NOT USED P2 A1 BIOP 1 IOTI IOT2 R 2 ~.--B_;.IO.;;...P_2_ _ _ _ _ _ __._---1 81 C1 L.---IOT 2 IOT4 BIOP 3 s20-~_:_-----------1.__ 01 E 1 ___ iOfii ~-----..nF1 FROM PROCESSOR 110 BUS .. Figure 5-27. M103 Device Selector Logic Circuit TO EXTERNAL DEVICE IZ-0138 5.4.1.7 M101 Bus Data Interface (See Figure 5-28) - Fifteen two-input NANO gates with one input of each gate tied to a common line. For use in strobing data off of the PDP-12 1/0 bus. The M 101 module includes diode protection clamps on input lines so that it may be used directly on the PDP-12 positive bus. 5-33 V 1 n-~B_A~C---=-0_7_ _ _- I U1 DEV ICE SELECTED (FROM M 1031 C1 A1 01 BAC 00 82 BAC 01 H2 BAC 08 BAC 09 J2 E1 BAC 02 K2 P1 BAC 10 L2 H1 TO EXTERNAL DEVICE J1 BAC 03 M2 BAC 11 N2 K1 L1 BAC 04 P2 n,....._ _ _ ___._-1 M1 N1 BAC 05 R2 52 n---------'"-~ P1 R1 BAC 06 T2 U2 n......-------4---1 Y2 12-0137 Figure 5-28. MlOl Bus Data Interface Logic Circuit 5 .4.2 M Series Flip Chip Modules The following is a list of M Series modules available from Digital Equipment Corporation that can be used in designing special interfaces and special devices. The majority of these modules are described in the Digital Logic Handbook. For those that cannot be found in the Handbook, contact the nearest Digital representative. 5-34 Table 5-2. M Series Module Summary Type Function Description M002 15 Loads Fifteen +3 volt sources each capable of driving ten unit loads. Can be used for tying off unused inputs. M040 Solenoid Driver Output ratings of-70 volts and 0.6 amp allow these two drivers to be used with a variety of medium current loads. M050 50 ma Indicator and Relay Driver Output of the variety also be shifters MIOI Bus Data Interface Fifteen two-input NAND gates with one input of each gate tied to a common line. For use in strobing data off of the PDP-8/I or PDP-12 1/0 bus. Pin compatible with M 111. M103 Device Selector Similar to W103, but for use with PDP-8/1 and PDP-12 options. Output pulses are not regenerated but only buffered. Mll 1 Inverter Sixteen inverter circuits with a fan-in of one unit load and fan-out of ten unit loads. Ml 12 NOR Gate Ten positive NOR gates with a fan-in of one unit load and fan-out of ten unit loads. Mll3 10 2-Input NAND Gates Ten two-input positive NAND gates with a fan-in of one unit load and fan-out of ten unit loads. Ml 15 8 3-Input NAND Gates Eight three-input positive NAND gates with a fan-in of one unit load and a fan-out of ten unit loads. Ml 17 6 4-lnput NAND Gates Six four-input positive NAND gates with a fan-in of one unit load and a fan-out of ten unit loads. M119 3 8-Input NAND Gates Three eight-input positive NAND gates with a fan-in of one unit load and a fan-out of ten unit loads. Ml21 AND/NOR Gates Six gates which perform the positive logic function AB+ CD. Fan-in on each input is one unit load and gate fan-out is ten unit loads. ratings of -20 volts and 50 ma. Allow any twelve circuits on this module to drive a of incandescent lamps. These drivers can used as slow speed open collector PNP level to -3 volt systems. 5-35 Table 5-2. M Series Module Summary (cont) Type 5-36 Function Description Ml41 NAND/OR Gates Twelve two-input positive NAND gates which can be used in a wired OR manner. Gates are grouped in a 4-4-3-1 configuration, with a fan-in of one unit load and a fan-out which depends on the number of gates ORed together. Ml60 Gate Module Three general purpose multi-input gates which can be used for system input selection. Fan-in is one unit load and fan-out is ten unit loads. Ml61 Binary to Octal/ Decimal Decoder A binary-to-eight line or BCD·to-ten line decoder. Gating is provided so that up to six binary bits can be decoded using only M 161 s. Accepts a variety of BCD codes. Ml62 Parity Circuit Two circuits, each of which can be used to generate even or odd parity signals for four bits of binary input. Ml69 Gating Module Four circuits that can be used for input selection. Each circuit is of an AND/OR configuration with four two-input AND gates. M202 Triple J.K. Flip-Flop Three J-K flip-flops with multiple input AND gates on J and K. Versatile units for many control or counter purposes. All direct set and clear inputs are available at module pins. M203 Set-Reset Flip-Flops Eight single-input set/reset flip-flops for use as buffer storage. Each circuit has a fan-in of one unit load and a fan-out of ten unit loads. M204 Counter-Buffer Four J-K flip-flops which can be interconnected as a ripple or synchronous counter or used as general control elements. M206 Six Flip-Flops Six D-type flip-flops which can be used in shift registers counters, buffer registers, and general purpose control functions. M207 Flip-Flops Six single-input J-K type flip-flops for use in shift register, ripple counters, and general purpose control functions. M208 Buffer Shift Register An internally connected 8-bit buffer or shift register. Provisions are made for gated single-ended parallel load, bipolar parallel output, and serial input. Table. 5-2. M Series Module Summary (cont) Type Function Description M211 Binary Up/Down Counter A six-bit binary up/down ripple counter with control gates for direction changes via a single control line. M212 6-Bit L-R Shift Register An internally connected left/right shift register. Provisions are made for gated single-ended parallel load, bipolar parallel output, and serial input. M213 BCD Up/Down Counter One decade of 8421 up or down counting is possible with this module. Provisions are made for parallel loading, bipolar output, and carry features. M230 Binary to BCD Shift Register Converter One decade of a modified shift register which allows high speed conversion ( 100 nsec per binary bit) of binary data to 8421 BCD code. System use of this module requires additional modules. M302 One Shot Delay Two pulse or level triggered one-shot delays with output delay adjustable from 50 nsec to 7 .5 msec. Fan-in is 2.5 unit loads and fan-out is 25 unit loads. M310 Delay Line Fixed tapped delay line with delay adjustable in 50-nsec increments from 50 nsec to 500 nsec. Two digital output amplifiers and one driver are included. M360 Variable Delay Continuously variable delay line with a range of 50 nsec to 500 nsec. Module includes delay line drivers and digital output amplifiers. M401 Clock A gateable RC clock with both positive and negative pulse outputs. The output frequency is adjustable from 10 MHz to below 100 Hz. M405 Crystal Clock Stable system clock frequencies from 5 kHz to 10 mHz are available with this module. Frequency drift at either the positive or negative pulse output is less than 0.01 % of the specified frequency. M410 Reed Clock A stable low frequency reed control clock similar to the M452. Stability in the range 0°C to 70°C is better than 0.15%. For use with communications systems and available with only standard teletype and data set frequencies. M452 Variable Clock Provides square wave output of 880 Hz, 440 Hz, and 220 Hz necessary for clocking the M706 and M707 in a 110-baud teletype system. 5-37 Table 5-2. M Series Module Summary (cont) S-38 Type Function MSOI Schmitt Trigger Provides regenerative characteristics necessary for switch filtering, pulse shaping, and contact closure sensing. This circuit can be AND/OR expanded. M502 Negative Input Converter Pulses as short as 3 5 nsec can be level shifted from -3 volt systems to standard M Series levels by the two circuits in this converter. This module can also drive low impedance terminated cables. M506 Negative Input Converter This converter will level shift pulses as short as 100 nsec from -3 volt systems to M Series levels. Each of the six circuits on this module provides a low impedance output for driving unterminated long lines. M507 Bus Converter Six inverting level shifters which accept -3 and GND, as inputs and have an open collecter NPN transistor at the output. Output rise is delayed by 100 nsec for pulse spreading. M516 Positive Bus Receiver Six four-input NOR gates with overshoot and undershoot clamps on one input of each gate. In addition, one input of each gate is tied to +3 volts with the lead brought out to a connector pin. M602 Pulse Generator The two pulse amplifiers in this module provide standard 50-nsec or 110-nsec pulses for M Series systems. M617 6-4 Input NOR Buffers Six four-input positive NOR gates with a fan-in of one unit load and a fan-out of 30 unit loads. M627 Power Amplifier Module Six four-input high speed positive NAND gates with a fan-in of 2.5 unit loads and a fan-out of 40 unit loads. M650 Negative Output Converter The three non-inverting level shifters on this module can be used to interface the positive 'levels or pulses (duration greater than 100 nsec) of Kand M Series to -3 volt logic systems. M652 Negative Output Converter These two circuits provide high-speed non-inverting level shifting for pulses as short as 3 5 nsec or levels from M Series to -3 volt systems. The output can drive low impedance terminated cables. M660 Positive Level Driver Three circuits which provide low-impedance 100-ohm terminated cable driving capability, using M Series levels or pulses of duration greater than 100 nsec. Output drive capability is 50 ma at +3 volts or ground. Description Table 5-2. M Series Module Summary (cont) Type Function M661 Positive Level Driver Three circuits which provide low-impedance unterminated cable driving. Characteristics are similar to M660 with the exception that +3 volts drive is 5 ma. M730 8/I Bus Positive Output Interfacer General Purpose positive bus output module for use in interfacing many positive level (0 to +20 volt) systems to the PDP-8/I or PDP-12. Module includes device selector, 12-bit parallel output buffer, and adjustable timing pulses. M731 8/I Bus Negative Output Interfacer Identical to M730, except outputs are level shifted for 0 to -20 volt systems to the PDP-8/I or PDP-12. Module includes device selector, 12-bit parallel input buffer, and adjustable timing pulses. M733 8/1 Bus Negative Identical to M732, except inputs are level shifted from negative voltage systems. M901 Flexprint® Cable Connector Double-sided 36-pin Flexprint cable connector. All pins are available for signals or grounds. Pins A2, B2, U 1, and V 1 have 10 n resistors in series. M902 Resistor Terminator Description Double-sided 36-pin terminator module with 100 terminations on signal leads. Alternate grounds are provided as in the M903 and M904. n M903 Connector Double-sided 36-pin Flexprint cable connector with alternate grounds for I/O bus cables. M906 Cable Terminator 18 load resistors clamped to prevent excursions beyond +3 volts and ground. It may be used in conjunction with the M623 to provide cable driving ability. 5.4 .3 Construction of I nterfaces This section provides the interface designer with information on design procedures, module layout, wiring, and cable selection. Additional help may be obtained from local DEC sales offices. 5.4.3.1 Physical - The PDP-12 was designed to provide the user maximum ease and flexibility in implementing special interfaces. External devices and interfaces are constructed and mounted outside of the basic machine, thereby eliminating the necessity for modifications to the basic processor. All signals to and from the computer are carried on coaxial or Flexprint cables. ®Flexprint is a registered trademark of Sanders Associates, Inc. 5-39 To implement several devices, the cables parallel-connect each peripheral in a serial type form (see Figure 5-29). Three dual cables are used for program interrupt cable connections in (or out). Two additional dual cables are used, for a total of five, when Data Break devices are implemented. 5.4.3.2 Module Layout - In general, module layout is based on the functional elements within a system and is primarily a matter of common sense. Digital has, however, layout conventions for 1/0 cabling to extend devices. The interface designer may wish to use these conventions as a guide. The general rule is DO NOT DEAD END THE 1/0 BUS. This means that parallel connections should always be made at each device to handle possible future expansion. 3 DUAL PROGRAM INTERRUPT CABLES 2 DUAL DATA BREAK CABLES DEVICE I DEVICE 2 PDP-12 12- 0142 Figure 5-29.\ 1/0 Bus Configuration Figure 5-30 shows the 1/0 cable connections in an option mounting panel. Module slot locations 1 through 3 (looking at the wiring pin side) are reserved for program transfer cable connections in (or out). Module slot locations 4 to 5 are reserved for data break cable connections in (or out). Slot 6 is used for Sense lines. Module slot locations 1 through 6 in the bottom half of the option mounting panel are wired in parallel with the top module slot locations 1 through 6. To continue the 1/0 cabling to the next device, the bottom slots are used, and the 1/0 cable connections are exactly the same as mentioned above. 5.4.3.3 Cable Selection - Two types of cables are recommended for 1/0 interface connections. The first is 9-conductor coaxial cable. This cable protects systems from radiated noise and cross talk between individual lines. Coax cable used and sold by Digital has the following nominal specs: z = 95 ± s n C L = 13. 75 pF/foot approx. (unterminated) 124 nH/foot approx. R = 0.095 Q/foot nominal Y = 79% of velocity oflight, approx. ( 1. 5 nsec/ft.) 5-40 = The second type is a 19-conductor (9 signals and 10 grounds), #30 gauge flat copper Flexprint. The total length of I/O cabling, from the PDP-12 to the last device, can be a maximum of 50 feet, and can be composed of 50 feet of coax or a combination of coax and Flexprint, in which case the Flexprint cannot exceed a total of 15 feet. 5.4.3.4 Connector Selection - Of the many connectors available in the module product line, several have particular application to I/O connectors. Price and ordering information is available on these and other connectors in the Digital Logic Handbook. Of particular interest are the M903 and M904 connectors described in the subsequent paragraphs. CABLE LOCATION 2 3 --- BACOOTO BAC 11 AC 00 BUS TO DATA ADD 00 TO AC11BUS DATA ADD 11 --- BIOP 1, 2, 4 4 --- SKiPB'US BRK RQST B INITIALIZE INT RQST BUS DATA IN BMB OOTO BMB 11 AC CLEAR BuS 6 32 ' DATAOo TO DATA 11 BT 53, 1 --- 5 --3 CYCLE CA INCREMENT SENSE LINES MB INCREMENT EXT DATA ADD BADO ACCEPTED B BREAK BWC OVERFLOW BRUN B INITIALIZE _) < SAME ASSIGNMENTS AS ABOVE ~ Figure 5-30. 1/0 Cable Connections 5-41 a. M903 Connector - Double sided 36-pin Flexprint cable connector with alternate grounds for I/O bus cables. (Two Flexprint cables are utilized with this connector module.) b. M904 Connector - Double-sided 36-pin coaxial cable connector with alternate grounds for I/O bus cables. (Two coax cables are utilized with this connector module). ( 1) Signals: Bl, DI, El, HI, JI, Ll, Ml, Pl, SI, D2, E2, H2, K2, M2, P2, S2, T2, V2 (2) Grounds: Al, Cl, Fl, Kl, NI, RI, Tl, C2,F2,J2,L2,N2,R2, U2 Signal Terminating - The G717 module is used for terminating the following signals: IOP 1, IOP 2, IOP 4, TS 2, TS 5. This module contains five 1DO.ohm terminating resistors and should be located in the last device of the I/O cabling scheme. Wiring Hints - These suggestions may help reduce mounting panel wiring time. They are not intended to replace • any special wiring instructions given on individual module data sheets or in application notes. For fast, neat wiring, the following order is recommended: I. All power wiring (Pins A2, B2, C2, Tl) and any horizontally bussed signal wiring. Use Horizontal Bussing Strips, Type 933. (Pin-B2 is bussed with -1 SV for modules requiring -1 SV.) 2. Vertical grounding wires interconnect chassis ground with Pins C2 and Tl grounds. Run these wires from the uppermost mounting panel to the bottom panel. On the first and last blocks of the mounting panel, connect the grounds to the chassis. 3. All other ground wires. Always use the nearest ground pin, unless a special grounding pin has been provided in the module. 4. Wire all signal wires in convenient order. Point-to-point wiring produces the shortest wire lengths, goes in fastest, is easiest to trace and change, and generally results in better appearance and performance than cabled wiring. Point-to-point wiring is strongly urged. The recommended wire size for use with H803 mounting blocks and H911 mounting panel is #30. Larger or smaller wire may be used depending on the number of connections to be made to each lug. Solid wire and a heat resistant insulation is recommended. The H803 mounting blocks are only available with wire wrap pins which necessitates the use of a wire wrap tool. (Digital can supply #30 gauge wire in I 000 foot rolls.) Adequate grounding is essential. In addition to the connections between mounting panels mentioned above, there must be continuity of grounds between cabinets and between the logic assembly and any equipment with which the logic communicates. S-42 When wire wrapping is done on a mounting panel contaimng modules, the wire wrap tool must be grounded, except when all modules are removed from the mounting panel. This procedure must be followed because, even with tools isolated from the ac power line, such as those operated by batteries or compressed air, static charges may build to sufficient amplitudes so that damage to semiconductors may result. Cooling - The low power consumption of M Series modules results in a total of about 15 watts dissipation in a typical H9 l l mounting panel containing 64 modules. Convection cooling is sufficient for a few mounting panels, but forced air cooling should be used when a very large system is built. 5.4.4 IOT Allocations IOT Option 00 01 02 03 04 05 06 07 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40 41 42 43 44 45 Interrupt High Speed Reader Type PR 12 High Speed Punch Type PP 12 Teletype Keyboard/Reader Teletype Teleprinter/Punch Displays, Types VC8/I and KV8/I Displays, Types VC8/I and KV8/I Displays, Types VC8/I, and Light Pen Type 370 Power Fail Option KPl 2 Teletype System Type PT08 Teletype System Type PT08 Real Time Clock Type KW 12 Mode Change (IOT 6141) Tape Maintenance Memory Extension Control Option Type MCI 2 Memory Extension Control Option Type MCI 2 Memory Extension Control Option Type MCI 2 Memory Extension Control Option Type MC 12 Memory Extension Control Option Type MC 12 Memory Extension Control Option Type MC 12 Memory Extension Control Option Type MC12 Memory Extension Control Option Type MCI 2 User Interfaces User Interfaces User Interfaces User Interfaces User Interfaces User Interfaces User Interfaces User Interfaces Teletype System Type DPl 2 Teletype System Type DP 12 Teletype System Type PT08 Teletype System Type PT08 Teletype System Type PT08 Teletype System Type PT08 5-43 46 47 50 51 52 53 Teletype System Type PT08 Teletype System Type PT08 Incremental Plotter Type XYl 2 Incremental Plotter Type XY 12 Incremental Plotter Type XY 12 General Purpose A/D Converters and Multiplexers, Types AFO 1A, AM02A, AM03A and AF04A Scanning Digital Voltmeter General Purpose A/D Converters and Multiplexers, Types AFOlA, AM02A, AM03A and AF04A Scanning Digital Voltmeter D/A Converter Type AAOlA D/A Converter Type AAOlA D/A Converter Type AAOlA, Sample and Hold Control Type ACOlA and AF04A Scanning Digital Voltmeter Random Access Disk File and Control Type DF32 and Synchronous Modem Interface Type DPOlA Random Access Disk File and Control Type DF32 and Synchronous Modem Interface Type DPOlA Random Access Disk File and Control Type DF32 and Synchronous Modem Interface Type DPOlA Card Reader Type CR 12 Synchronous Modem Interface Type DPOlA Synchronous Modem Interface Type DPOlA Synchronous Modem Interface Type DPOIA Card Reader Type CR 12 and Synchronous Modem Interface Type DPO l A Automatic Mag Tape Type TC5 8 Automatic Mag Tape Type TC5 8 Automatic Mag Tape Type TC58 Automatic Mag Tape Type TC58 Automatic Mag Tape Type TC58 54 55 56 57 60 61 62 63 64 65 66 67 70 71 72 73 74 75 76 DECtape Control TCOl DECtape Control TCOl 77 5.4.5 Interface Connections All interface connections to the PDP-12 are made at assigned module receptacle connectors in the Processor Mounting Frame. Capital letters designate vertical rows of modules within a mounting frame. The letters progress alphabetically from right to left when viewed from the wiring side. Module receptacles are numbered from top to bottom within a row. Terminals are assigned capital letters from right to left, with the letters G, I, 0, and Q omitted. Double-sided connectors or modules use the suffix number 1 to designate the top side of a module and the suffix number 2 to designate the bottom side. The module receptacles and assigned use for interface signal connections are: 5-44 Receptacle Use N13 N14 N15 N16 Nl7 NIB SENSE LINES AC, IOP, TIMING OUTPUTS MB OUTPUTS AC, SKIP, INT. REQUEST INPUTS DATA BREAK ADDRESS INPUTS DATA BREAK DATA INPUTS Terminals Al, Cl, Fl, Kl, NI, Rl, Tl, C2, F2, 12, L2, N2, R2, and U2 of these receptacles are grounded within the computer, and terminals Bl, Dl, El, Hl, Jl, Ll, Ml, Pl, Sl, 02, E2, H2, K2, M2, P2, S2, T2, and V2 carry signals. Terminals A2 and B2 are not used. These terminals mate with either M903 or M904 Cable Connectors. Interface connection to the PDP-12 can be established for all peripheral equipment by making series cable connections between devices. In this manner only one set of cables is connected to the computer and two sets are connected to each device; one receives the computer connection from the computer itself or the previous device, and one passes the connection to the next device. Where physical location of equipment does not make series bus connections feasible, or when cable length becomes excessive, additional interface connectors can be provided near the computer. All logic signals passing between the PDP-12 and input/output equipment are positive voltage levels, allowing direct TTL logic interface with appropriate diode clamp protection. Positive level for a low logic state is 0 to 0.4 volts. Positive level for a high logic state is +3.6 volts. The following table presents cable connections to the PDP-12 I/O Bus. A signal is true when its polarity matches the suffix character of its name (i.e., 100 BAC 00 (1) H will be high when AC 00 (1) and a program interrupt will be requested when the line EXT INT RQST BUSL is pulled low). Table 5-3. Cable Connections to the PDP-12 1/0 Bus Signal Connection Signal Connection IOB XL OOH IOB XL 01 H IOB XL 02 H IOB XL 03 H IOB XL 04 H IOB XL 05 H IOB XL 06 H IOB XL 07 H IOBXL lOH Nl3Bl Nl3Dl N13El Nl3Hl Nl3Jl N13Ll N13Ml N13Pl Nl3Sl IOB XL 11 H IOB XL 12 H IOB XL 13 H NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED Nl3D2 N13E2 N13H2 N13K2 Nl3M2 Nl3P2 Nl3S2 Nl3T2 Nl3V2 100 BAC JOO BAC JOO BAC 100 BAC 100 BAC 100 BAC JOO BAC JOO BAC 100 BAC 00 (1) H 01 (1) H 02 (1) H 03 (1) H 04 (1) H 05 (1) H 06 (1) H 07 (1) H 08 (1) H Nl4Bl Nl4Dl N14El N14Hl N14Jl Nl4Ll N14Ml Nl4Sl 100 BAC 09 (1) H 100 BAC 10 (1) H lOOBAC 11 (l)H 100 BIOP 1 H 100 BIOP 2 H 100 BIOP 4 H 100 BTS 5 (1) H JOO BTS 2 (1) H 100 BA INITIALIZE H Nl4D2 Nl4E2 N14H2 Nl4K2 Nl4M2 Nl4P2 Nl4S2 Nl4T2 Nl4V2 JOO BMB JOO BMB 100 BMB JOO BMB 100 BMB 100 BMB JOO BMB JOO BMB JOO BMB 00 01 02 03 03 04 04 05 05 Nl5Bl NlSDl N15El NISHI NI SJ I NlSLl Nl5Ml Nl5Pl Nl5Sl JOO BMB JOO BMB JOO BMB JOO BMB 100 BMB 100 BMB 100 BMB JOO BMB 100 BMB Nl5D2 Nl5E2 N15H2 N15K2 Nl5M2 Nl5P2 NISS2 Nl5T2 Nl5V2 (1) H (1) H (1) H (0) H (1) H (0) H (1) H (0) H (1) H ~14Pl 06 (0) H 06 (1) H 07 (0) H 07 (1) H 08 (0) H 08 (1) H 09 (1) H 10 (1) H 11 (1) H 5-45 Table 5-3. Cable Connections to the PDP-12 I/O Bus (cont) -- Connection Signal Connection N16Bl N16Dl N16El N16Hl N16Jl N16Ll N16Ml N16Pl N16Sl EXT IO BUS 09L EXT IO BUS 10 L EXT IO BUS 11 L EXT SKIP BUS L EXT INT RQST BUS L EXT AC CLEAR BUS L IOO B RUN (0) H NOT USED NOT USED N16D2 Nl6E2 Nl6H2 Nl6K2 Nl6M2 N16P2 N16S2 N16T2 Nl6V2 L L L L L L L N17Bl N17Dl N17El N17Hl Nl7Jl N17Ll Nl7Ml Nl7D2 Nl7E2 Nl7H2 Nl7K2 Nl7M2 N17P2 EXT DATA ADD 07 L EXT DATA ADD 08 L N17Pl N17Sl EXT DATA ADD 09 L EXT DATA ADD 10 L EXT DATA ADD 11 L EXT BREAK RQST L EXTDATAINH IOO BREAK (0) H IOOADD ACCEPTED (0) H EXT INCREMENT MB L IOO BB INITIALIZE H EXT DATA EXT DATA EXT DATA EXT DATA EXT DATA EXT DATA EXT DATA EXT DATA EXT DATA Nl8Bl N18Dl N18El Nl8Hl Nl8Jl N18Ll N18Ml N18Pl Nl8Sl EXT DATA 09 L EXT DATA IO L EXT DATA 11 L EXT 3 CYCLE L IOB CA INCREMENT H IOO WC OVERFLOW (0) H EXT EXTEND DATA ADD 02 L EXT EXTEND DATA ADD 01 L EXT EXTEND DATA ADD 00 L Nl8D2 Nl8E2 Nl8H2 Nl8K2 N18M2 N18P2 N18S2 N18T2 N18V2 Signal EXT IO EXT IO EXT IO EXT IO EXT IO EXT IO EXT IO EXT IO EXT IO EXT EXT EXT EXT EXT EXT EXT 546 BUS BUS BUS BUS BUS BUS BUS BUS BUS 00 L 01 L 02 L 03 L 04 L OS L 06 L 07 L 08L DATA ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA ADD DATA ADD 00 01 02 03 04 OS 06 07 08 L L L L L L L L L 00 01 02 03 04 05 06 Nl7S2 N17T2 N17V2 CHAPTER 6 PERIPHERAL DEVICES INTRODUCTION This chapter contains descriptions of all the standard prewired I/O bus options which are available with the PDP-12. It describes the peripheral logic expander, BAI 2, and options contained within the panel, as well as the most commonly used PDP-8 and PDP-12 family of I/O bus options. In general, most PDP-8 family of options can be operated without modification on the PDP-12 1/0 bus. The reader, therefore, should refer to the DEC Small Computer Handbook ( 1970) for additional information. Prewired options and options contained in the BAI 2 Peripheral Expander panel derive their power from the PDP-12 power supply. The Peripheral Expander contains the necessary buffering to provide the isolation and current driving requirements for 1/0 devices. The control logic for these options is contained in plug-in modules; therefore, when one of these options is added, wiring changes or additions are not needed. Separate power supplies are normally included with all the other options. Option Groupings a. Pre wired Teletype Model 33 ASR Additional Teletype or Dataphone Real-Time Interface Fixed Interval Clocks LINCtape to DECtape format converter Digital Plotter and Control Power Fail Option Type Number DPI 2-A,B KW12-A KW12-B,C TC12-F XY12 KP12 b; Peripheral Expander Type BAI 2 4-Station TTY Control Line Printer High-speed Paper Tape Reader/Punch Standard or Mark Sense Card Reader Data Buffers DC02-D,E LP12 PC12, PP12, and PR12 CR12, CM12 DBI 2-P, N 6-1 Option Groupings c. 1/0 Bus Stand Alone Peripherals 32 Station TTY Control I- and 2-Station TTY Control Line Printer Magnetic Tape Control Magnetic Tape Transport Disk Fixed Head, 3 2K Disk Fixed Head, 256K Disk Movable Head BOOK A-D Converter D-A Converter Option Type Number DC02-F,G PT08 LP08 TC58 TU20 DF32, DS32 RF08, RS08 RK8, RKOl AFOIA AAOIA The above groupings represent the physical organization of the PDP-12; however, the options will be described in the following order: Option Descriptions Teletype Controls (TTY) Real-Time Interface and Clocks Disks Tapes Line Printers Card Readers Plotters High-Speed Paper Tape Data Buffers Power Fail/Restart A-D Converter D-A Converter 6-2 Page Number 6-3 6-18 6-27 6-45 6-59 6-63 6-68 6-71 6-73 6-74 6-76 6-82 6.1 TELETYPE 6. 1.1 Model 33 ASR The Teletype Model 33 ASR is the standard Teletype device offered with the PDP-12. It may be used to type in or print out information at a rate of up to ten characters per second, or to read in or punch out perforated-paper tape at ten characters per second. Signals transferred between the Model 33 ASR and the control logic are standard, serial, 11-unit code, Teletype signals. The signals consist of marks and spaces which correspond to idle and bias current in the Teletype, and to zeros and ones in the teletype control and computer. The start mark and subsequent eight-character bits are one-unit-of-time duration, and are followed by the stop mark, which occupies two units. The 8-bit code used by the Model 33 ASR Teletype unit is the American Standard Code for Information Interchange (ASCII) modified. To convert the ASCII code to Teletype code, add 200 octal (ASCII + 200 8 Teletype). Bits are numbered from right to left, from 1 through 8, with bit 1 having the least significance. Figure 6-1 illustrates the relationship between paper tape information and the AC. SPROCKET FEED HOLES TAPE HOLE AND CHANNEL NUMBERS 0 0 0 0 0 0 0 0 ......._PAPER TAPE 0 0 AC BIT LOCATION-+ 4 5 6 7 8 9 10 11 NOTE: AC BITS 0-3 ARE NOT USED. 12-0193 Figure 6-1. Relationship Between Paper Tape and Accumulator The character (number) four (4) as it would be punched on paper tape is shown in Figure 6-2. The Model 33 ASR set generates all assigned codes except 340 through 374 and 376. Generally codes 207, 212, 215, 240 through 337, and 377 are sufficient for Teletype operation. The Model 33 ASR detects all characters, but does not interpret all of the codes that it can generate as commands. The standard number of characters printed per line is 72. The sequence for proceeding to the next line is a carriage return followed by a line feed (as opposed to a line feed followed by a carriage return). Appendix F lists the character codes for the Teletype. 6.1.2 Model 33 KSR This Teletype model is similar to the 33 ASR, except that it does not have either a paper tape reader or punch. The control logic, however, is the same as that used with the 33 ASR. 6-3 SPROCKET FEED HOLE TAPE CHANNEL 7 8 6 5 4 s 3 2 1 0 0 '---..,,---' BINARY CODE {t=PUNCH) OCTAL CODE t 2 6 4 12-0193 Figure 6-2. Punched Paper Tape Format for the Number 4 6.1.3 Model 35 KSR This unit is functionally the same as the 33 KSR. It is designed for heavy duty use and extended reliability. The control logic, however, is the same as that used in the 33 ASR. 6.1.4 Model 37 KSR This Teletype is offered as part of the LT37-AD, AE (50 Hz) option. It has an expanded character set (i.e., upper and lower case) and control functions, and operates at 15 characters per second, both transmitting and receiving. The LT3 7-AD option has a front panel switch which can effectively convert the unit to operate as a 33 ASR. Only upper case characters would then be received or transmitted. The LT37 option provides the following programmed operations: a. b. c. d. e. Horizontal tab set and clear Motor control; on and off Vertical tab; set and clear at full line increments Ribbon color shift Reverse linefeed; full and half line increments The LT37 is useful for the preparation of formal reports, business forms and graphical plots. Table F-3 in Appendix F provides the character and control codes for each mode of operation. 6.1.S Teletype Controls The basic programmed operation of the following devices is similar: Console Teletype Prewired Dataphone Option, Type DPl 2-A, B Add-on Single and Dual TTY Control, Type PT08-B, C They all transmit and receive asynchronous, full-duplex, bit-word information. These devices use control modules M706 (Receiver) and M707 (Transmitter), which are positive logic modules, or W706 (Receiver) and W707 6-4 (Transmitter), which are the negative equivalent logic control modules. These modules are fully described in the Digital Logic Handbook. The main differences in these options being controlled are: a. Source of data (e.g., Dataphone, keyboard/display terminal, Teletype, etc.) b. Speed of operation Slow speed devices such as Teletype are driven by the stabilized RC oscillator clock module (M452). Higher speed requires a high stability of the selected frequency; therefore, a crystal-controlled clock module (M4QS) is used. The frequency of operation must be specified for each separate device. c. Voltage level of inputs Typically, DEC equipment will interface directly with EIA RS-232-B industry standard devices or the standard 0, 20 mA Teletype current loop (sometimes referred to as 0, +3V logic level). As the console Teletype is typical of the three different controls discussed in this section, it will be described in detail. The differences which are noteworthy in the PT08 and DPl 2 will be further discussed. 6.1.5.1 PDP-12 Console Teletype Control - The Teletype control uses the standard M706 receiver, M707 transmitter, and M452 clock modules for basic logic. It will drive any one of the previously discussed Teletype models (the KSR-37 requires a slight adjustment of the clock to operate at 15 characters per second). Serial information read or written by the Teletype unit is assembled or disassembled by the Teletype control for parallel transfer to the accumulator (AC). The control also provides the program flags that cause a program interrupt or an instruction skip depending on the availability of the Teletype and the processor. In all programmed operation, the Teletype unit and control are considered ~s a Teletype in (TTI) for input data from the keyboard or the perforated-tape reader, and as a Teletype out (TTO) for computer output information to be printed and/or punched on tape. Therefore, two device select codes are used. Select code 03 initiates operations associated with the keyboard/reader (TTI) and select code 04 performs operations associated with the teleprinter/punch (TTO). Parallel input and output functions are performed by corresponding IOT pulses produced by the two device selectors. Pulses produced by the IOPl pulse trigger skip gates; pulses produced by the IOP2 pulse clear the control flags and/or the accumulator; and pulses produced by IOP4 initiate data transfers to and from the control. 6.1.5.2 Keyboard Reader - The keyboard and tape reader control contains an 8-bit shift register (TTI) which assembles and holds the code for the last character struck on the keyboard or read from the tape. Teletype characters from the keyboard/reader are received serially by register TTL The code of a Teletype character is loaded into the TTI so that spaces correspond to binary zeros and holes (marks) correspond to binary ones. Upon program command, the contents of the TTI are transferred in parallel to the accumulator. When a Teletype character starts to enter the TTI, the control de-energizes a relay in the Teletype unit to release the tape feed latch. When released, the latch mechanism stops tape motion only when a complete character has been sensed, and before sensing of the next character is started. A keyboard is set when an 8-bit computer character has been assembled in the TTI from a Teletype character. The program must sense the condition of this flag with a KSF instruction, and, if the flag is set, issue a KRB instruction which clears the AC, clears the keyboard flag, transfers the contents of the TII into the AC, and enables advance of the tape feed mechanism. Program interrupt can be controlled by the LINC mode instruction ESF (0004) (refer to Paragraph 3.3.16). This instruction either enables or inhibits interrupts when either the TTI or TIO flag is set. 6.1.5.3 Instructions - Instructions for use in supplying data to the computer from the Teletype are as follows: 6-5 KSF Skip on Keyboard Flag Octal code: Event time: Execution time: Operation: Symbol: KCC 4.25 µs If the keyboard flag is set, the contents of the PC are incremented by one so that the next sequential instruction is skipped. If Keyboard Flag= 1, then PC+ I -+ PC Clear Keyboard Flag Octal code: Event time: Execution time: Operation: Symbol: KRS 6031 6032 2 4.25 µs The AC and the keyboard flag are cleared. If there is tape in the reader and the reader is on, the character over the read head is loaded into the TTI and the tape advanced one frame. If there is no tape or the reader is off (STOP or FREE) the character struck on the keyboard is assembled into the TTL In either case, when the character is completely assembled in the TTI, the hardware sets the keyboard flag. 0-+AC 0-+ Keyboard flag allowing the hardware to cause: Keyboard/Tape Character-+ TTI I -+ Keyboard flag (approximately I 00 ms after issuing the instruction) Read Keyboard Buffer Static Octal code: Event time: Execution time: Operation: Symbol: 6034 3 4.25 µs The contents of the TTI are transferred into AC 4 - 11 • This is a static command in that neither the AC nor the keyboard flag is cleared. KRS can be microprogrammed with KCC. TTI V AC 4 - 11 -+AC4-11 0-+ Keyboard Flag NOTE The KRS instruction has been redefined in a later version of the PDP-12 to permit clearing of the TTI flag without advancing the paper tape and assembling the next character. KRB Read Keyboard Buffer Dynamic Octal code: Event time: Execution Time: Operation: Symbol: 6-6 6036 2, 3 4.25 µs This instruction combines the functions of the KCC and KRS. The AC and keyboard flag are both cleared and the contents of the TTI are transferred into AC 4 - 11 • Clearing the keyboard flag allows the hardware to begin assembling the next input character into the TTI (as described for KCC). When the character is completely assembled in the TTI, the hardware causes the flag to be set, indicating that TTI again has a character ready for transfer. 0-+ AC C(TTI) V C(AC4 - 11 )-+ AC 4 - 11 0-+ Keyboard Flag allowing the hardware to cause: Tape Reader to advance I character Keyboard/Tape Character -+ TTI 1 -+ Keyboard Flag when down (approximately I 00 ms after issuing instruction) KST Key Strock (LINC mode) Form: Octal code: Execution time: Condition: KSTI 0415 + 201 1.6 µs A key has been struck on the ASR-33 keyboard, the character code has been assembled in the Teletype buffer, and the Keyboard flag is raised. (The flag is cleared when the character is read into the AC.) The program example shown below will read 1 character from the keyboard. *200 INPUT, KCC JMS LISN DCA STORE HLT /CLEAR KEYBOARD FLAG LISN, 0 /SKIP ON KEYBOARD FLAG /READ KEYBOARD BUFFER STORE, KSF JMP.-1 KRB JMP I LISN 0 $ The main program begins with KCC. In general, the main program should begin by clearing the flags of all devices to be used later in the program. If the above program is started at location 200, it will proceed to the KSF, IMP. -1 loop, and stay in this loop endlessly until a key on the Teletype unit is pressed or a paper tape is loaded into the reader. When the ASCII code for the character is assembled in the keyboard/reader buffer register, the flag will be set to a 1 and the program will skip out of the loop. The contents of the buffer will be transferred into the accumulator, and the buffer and flag will be cleared. 6.1.5.4 Teleprinter/Punch - On program command, a character is transferred from the accumulator (AC) to the output shift register (TTO) for transmission to the teleprinter/punch unit. The teleprinter control generates the start space, shifts the eight character bits serially into the printer selector magnets of the teletype unit, and then generates two stop marks. Bit transfer rate from the TTO to the teleprinter/punch unit is at the normal Teletype rate of 110 baud. A character transfer requires 100 milliseconds for completion. The teleprinter flag is set when the last bit of the character code is sent to the teleprinter/punch, indicating that the TTO is ready to receive a new character from the AC. The flag activates either the program interrupt synchronization element or the instruction skip element. When using instruction skip, the program checks the flag by means of TSF instruction. If the flag is set, the program must issue a TLS instruction which clears the flag and sends a new character from the AC to the TTO. AC to TTO transfer time is short compared to the print/punch time, so the program must wait for the flag to set before issuing another TLS. Instructions for use in outputting data to the teleprinter/punch are as follows: TSF Skip on Teleprinter Flag Octal code: Event time: Execution time: Operation· 6041 4.25 µs If the teleprinter flag is set, the contents of the PC are incremented by one so that the next Symbol: sequential instruction is skipped. If Teleprinter Flag = 1, then PC + 1 ~ PC 6-7 TCF Clear Teleprinter Flag Octal code: Event time: Execution time: Operation: Symbol: TPC Load Teleprinter and Print Octal Code: Event time: Execution time: Operation: Symbol: TLS 6042 2 4.25 µs The teleprinter flag is cleared. Can be microprogrammed with TPC. 0 ~ Teleprinter Flag 6044 3 4.25 µs AC 4 - 11 are parallel transferred to the TTO, then the hardware starts shifting the character out to the printer/punch unit. When the transfer is complete (approximately 100 ns), the TTO flag is set. C(AC 4 - 11 ) ~ TTO causing: C(TTO) ~printed and (if punch is on) punched Load Teleprinter Sequence Octal Code: Event time: Execution time: Operation: Symbol: 6046 2, 3 4.25 µs This is an instruction that combines TCF and TPC. The teleprinter flag is cleared, then the contents of AC 4 - 11 are parallel transferred to the TTO, where the hardware serially shifts the character-bits out to the printer/punch unit. When the printer/punch has finished outputting the character, the hardware sets the teleprinter flag. The whole operation, from the time TLS clears the flag and TPC starts character transfer until the time the hardware finishes with the character and again sets the flag, requires 100 ms. 0 ~Teleprinter flag C(AC4 - 11 ) ~ TTO causing: C(TTO) ~ Printed and (if punch on) punched 1 ~ Teleprinter flag when done (approximately 100 ns after issuing instruction) Shown below are several programming examples illustrating the use of the TTO control. TYPE, 0 TLS TSF JMP .-1 CLA JMP I TYPE /LOAD TIO FROM AC AND PRINT /PUNCH /TEST FLAG SKIP IF = 1 /JMP BACK & TEST FLAG AGAIN AND AGAIN /CLEAR CHARACTER FROM AC /EXIT TO MAIN PROGRAM By rearranging this subroutine, the 100 ms spent waiting for the character to be output and the flag to be set is used to continue the main program, making more efficient use of program time. 6-8 TYPE, 0 TSF JMP .-1 TLS CLACLL JMP I TYPE /TEST FLAG TO SEE IF TELEPRINTER FREE, SKIP IF NOT /WAIT TILL IT IS BY TESTING AGAIN AND AGAIN /OUTPUT CHARACTER /CLEAR CHARACTER FROM AC /EXIT TO CONTINUE PROGRAM This subroutine tests the flag first, and waits only if a previous character is still being output. It clears the AC and exits immediately after sending the character to the TTO, and continues to run the user's program instead of waiting while the teleprinter (a much slower device) is off typing/punching the last character. The user must initialize the control by setting the teleprinter flag to a one. Otherwise, the subroutine will "hang-up" the first time through (in the TSF, JMP .-1 loop). The initialization can be accomplished by issuing a TLS or TPC instruction at the beginning of the mainline program. Format Routines Input and output routines are very often written in the form of subroutines, like the TYPE subroutine in the previous example. The example below is a carriage return/line feed subroutine that calls the TYPE subroutine to execute a carriage return and line feed on the printer, thus advancing to a new line for the printing of information. Carriage Return/Line Feed Subroutine: CRLF, 0 K212, K215, TYPE, TAD K212 JMS TYPE TAD K215 JMS TYPE JMP I CRLF 212 215 0 TSF JMP .-1 TLS CLACLL JMP I TYPE /ASCII FOR CARRIAGE RETURN /ASCII CODE FOR A LINE FEED Subroutines similar to the one above could be written to tab space the carriage a given number of spaces, or to ring the bell of Teletype Model 33 ASR by using the respective codes for these nonprinting control characters. 6.1.5.5 Single Teletype Control, Type DP12-A (prewired) - This internal option provides an interface which is programmed similar to the standard console Teletype. The device select codes are IOTs 40 and 41. Interrupts caused by either the transmitter or receiver flags can be disabled by the LINC mode instruction ESF (refer to Paragraph 3.3.16). 6.1.5.6 Dataphone Control, Type DP12-B - This option is a modification of the DP12-A, which permits communication to most standard Dataphone sets. An extra crystal-controlled clock permits the user to specify a baud rate from 110 to 1ObK baud in order to provide the necessary frequency stability required at higher baud rates. In addition, the option is supplied with a 25-ft cable, Type BCOlA-25, which will connect (via a 25-pin connector) to a Dataphone set. This cable has a card connector (M850), which converts the EIA standard RS-232-B signals to DEC logic levels of 0 and +3V 6-9 6.1. 5. 7 Single and Dual TTY Control Type PT08 - The PT08 is a serial-to-parallel, parallel-to-serial converter which provides full-duplex communication between an asynchronous channel and a PDP-12 computer. Two basic configurations are offered: PT08-B (one full-duplex channel) and PT08-C (two full-duplex channels). Systems may be expanded up to five duplex channels by stacking PT08 units. The PT08-B and C are designed to supply transmit and receive keying current that is intended for use with 20 mA, de-keyed devices. Digital Equipment Corporation's Model 33 or 35 teleprinter units have been modified to be compatible with the PT08. Devices equivalent to the modified teleprinter units are also compatible with the PT08. The PT08-B and C are negative bus options (0, -3V) and, therefore, a DW08-A negative-to-positive 1/0 bus converter must be used when connecting the PT08 to the PDP-12. The PT08-F option provides EIA standard RS-232-B level conversion as well as a 25-ft cable designed to connect to a Dataphone set. Another option, the PT08-X, can be installed in any channel for customer selection of character format and speed. With the PT08-F and PT08-X options combined, the bit rate can be increased to lOOK baud for driving medium-to-high-speed asynchronous modems. This combination can be used for an economical intercomputer communication channel, or for interfacing to special equipment with unique asynchronous speeds and character formats. Specifications Performance specifications are summarized in Table 6-1. Table 6-1. PT08 Specifications Specifications Speed Character Format Operating Mode Interface Transmission Distance 110 baud is standard; up to lOOK (software limited) with PT08-X option. Standard: I-unit start; 8 character bits; 2-unit stop. PT08-X Option: 5 or 8 character bits, 1- or 1.5-unit stop element at user's request. Full duplex. Supplies transmit and receive keying current that is intended for Standard: use with 20 mA, de-keyed devices. PT08-F Options: Provides interface that conforms to EIA RS-232-B devices. 1500-ft maximum (environment dependent) for local terminals. EIA interface transmission distance is limited only by characteristics of modem and associated communication facility. A 25-ft cable to the modem is supplied. Figure 6-3 illustrates the various PT08 equipment configurations for both the standard system expansion and interface provisions. Programming IOT instructions test for character-ready conditions and transfer assembled characters to and from the computer's accumulator. The same basic commands are used for all channels, with individual channels assigned different device selection codes. For PT08 channel 1, the devices codes are 40 and 41, etc. (See Table 6-2 for complete listings of PT08 device codes.) It will be noted that channel 1 IOTs are the same as assigned to the internal prewired option DPl 2-A or B. When channel 1 is implemented, the IOT for channel 1 must be revised to an unused device select code. This normally would be one of the device codes 30 through 37. The basic mnemonic plus the PT-number designator identifies the mnemonic for the specific channel. 6-10 PDP-12 (+) ·------, 1W070 ------LOCAL -I/O BUS PTOBB I TERMINAL DWOS-A .,....__ _ OR C L - - - - - i--- t- - -- ----- I l_P_!~B_F - I 1---+ .J (TELEPRINTER) (UP TO 1500 FEET MAXIMUM) 110 BAUD 'EiA Rs-=2120- -l4-+ MAXI MUM OF 5 FULL DUPLEX LINES (20mA DC- KEYING) OF SERIAL-STA RT-STOP CODE TYPE MODEM ~~~~~N!•!T~)j..... PTOSB 1 OR C 1---1 CONTINUATION OF 1/0 BUS TO OTHER PERIPHERALS I PTOBB ~- -OR C 1-1 _ __ UP TO B1 OAOUDK f"HIGH.:SPEED-i.-. 1 I 1ASYNCHRONOUS MODEM PTOs-x' 1PTOBF ----J~E_!:;L_~~~.~~l.Ji.... 12-0206 Figure 6-3. PT08 Equipment Configurations Table 6-2. PT08 Device Codes Basic Mnemonic KSF KCC KRS KRB TSF TCF TPC TLS Channel Number 1 2 3 4 s 6421 KSFPT2 6422 KCCPT2 6424 KRSPT2 6426 KRBPT2 6431 TSFPT2 6432 TCFPT2 6434 TPCPT2 6436 TLSPT2 6441 KSFPT3 6442 KCCPT3 6444 KRSPT3 6446 KRBPT3 6451 TSFPT3 6452 TCFPT3 6454 TPCPT3 6456 TLSPT3 6461 KSFPT4 6462 KCCPT4 6464 KRSPT4 6466 KRBPT4 6471 TSFPT4 6472 TCFPT4 6474 TPCPT4 6476 TLSPT4 6111 KSFPTS 6112 KCCPT5 6114 KRSPT5 6116 KRBPTS 6121 TSFPTS 6122 TCFPT5 6124 TPCPT5 6126 TLSPTS 6301 KSFPTl 6302 KCCPTI 6304 KRSPTl 6306 KRBPTl 6311 TSFPTl 6312 TCFPTI 6314 TPCPTI 6316 TLSPTl Instructions The following instructions are used with the PT08: KSF Skip on Receive Flag Event time: Indicators: Execution time: Operation: Symbol: IOT, Fetch, Pause 4.25 µs Causes the program to skip the next instruction if the receive flag is set, indicating that an assembled character is ready. If receive flag = 1, PC + 1 -+ PC 6-11 KCC Clear Receive Flag and AC Event time: Indicators: Execution time: Operation: Symbol: KRS Read Receive Buffer (Static) Event time: Indicators: Execution time: Operation Symbol: KRB 2 JOT, Fetch, Pause 4.25 µs Clears the accumulator and the receive flag. o~Ac, o~ RF 3 IOT, Fetch, Pause 4.25 µs Transfers an assembled character from the receive buffer to AC 4 - 1 1 . Does not reset AC or receive flag. RB~ AC 4 - 11 Read Receive Buffer (Dynamic) Event time: Indicators: Execution time: Operation: 2, 3 IOT, Fetch Pause 4.25 µs Performs the functions of KCC and KRS together, so that the receive flag and AC are cleared before data is transferred from the receive buffer to the AC. Symbol: o~Ac, o~RF RB~ TSF Skip on Transmit Flag Event time: Indicators: Execution time: Operation: TCF 2 IOT, Fetch, Pause 4.25 µs Resets the transmit flag. o~TF Load Transmit Character Event time: Indicators: Execution time: Operation: Symbol: 6-12 I OT, Fetch, Pause 4.25 µs Causes the program to skip the next instruction if the transmit flag is set, indicating that the transmit flag= 1, PC+ 1 ~PC Clear Transmit Flag Event time: Indicators: Execution time: Operation: Symbol: TPC AC 4 - 11 3 IOT, Fetch, Pause 4.25 µs Loads the transmit buffer from AC4 - 11 and initiates transmission of a character. AC 4 - 11 ~TB TLS Load Transmit Sequence Event time: Indicators: Execution time: Operation: Symbol: 2, 3 IOT, Fetch, Pause 4.25 µs Performs the functions of TCF and TPC together. 0-+TF AC 4 _11 -+TB Maximum Data Rates In transmitting the PT08 provides a full character cycle for the program to deliver new data. In receiving, one bit time is required to read in necessary data. However, for maximum data transfer rates, the time at which data transfer can occur is limited to an aperture equal to the stop bit time plus half a bit time. This response time is measured from the beginning of a stop bit (the time at which the transmit or receive flag is reset), and the midpoint of the next character's start bit. If the program fails to respond within this time, a character is lost. Timing is illustrated in Figure 6-4. l4-- --.i BIT TIME ( 1/BAUD RATE) ____, ~ STOP BIT TIME (BIT TIME X STOP UNITS} I I I START DATA BITS : : r-r T- - - - ---iL_j __i_ _l_ _ _ _ _ _I _ ! CHARACTER-----, TIMING STOP :sTA~- -.-DATA ~T~ - !'_ 1 I I I I I I RECEIVE TRANSMIT OR FLAG RESET _J ! _L _ _ _ _ I I I I I L LAST TIME TO RESPOND TO FLAG 81-0075 Figure 6-4. PT08 Program Response Time For example, at 110 baud (9.09 ms bit time), response time is: Stop bit time + half a data bit time = 2 x 9.09 + 9.09/2 = 22.725 ms Note that the number of bits per character need not be considered. 6.1.5.8 Multiple Teletype Control, Type DC02-E (see Table 6-3) - The DC02-E option, which is prewired in the BAI 2 Peripheral E~pander, allows the user to add up to four serial-to-parallel, parallel-to-serial asynchronous data channels. It consists of a DC02-E multiple station control and from one to four DC02-D station interfaces (each full-duplex). A Type BCOIA-25 cable is available that will connect to most Dataphones via a 25-pin connector and will convert EIA standard RS-232-B signals to DEC logic levels of 0 + 3 volts. The control will handle teletypes at their normal baud rate of 110. In addition, higher speed devices may be operated by using crystal clocks. In this case the baud rate must be specified by the user. Up to two clocks may be used and may be connected by a jumper module in any combination to control the stations' transmitters and receivers. 6-13 Table 6-3. DC02-E Specifications Characteristics Specifications Speed Character Format Operating Mode Interface Transmission Distance 110 baud is standard; up to 1OOK baud crystal controlled. Standard: I-unit start; 8 character bits; 2-unit stop. Option: 5 or 8 character bits 1- or 1.5-unit stop element at user's request. Full duplex. Standard: Supplies transmit and receiver keying current that is intended for use with 20 mA, de-keyed devices. 1500 ft maximum (environment dependent) EIA interface transmission distance is limited only by characteristics of modem and associated communication facility. A 25-ft cable to the modem is supplied. (BCOlA-25). DC02-E Control Instructions The following instructions are·used with the DC02E control: MTPF Multiple Teleprinter Flag Octal code: Event time: Execution time: Operation: Symbol: MINT 6115 3 4.25 µs Interrupt on if AC 1 1 is set (interrupt request if any flags). AC 1 1 --+ Interrupt Enable 6117 1, 2, 3 4.25 µs Transfer AC 0 _ 3 to selection register (select stations when bit is set). AC 0 _3 --+ SR Multiple Keyboard Flag Octal code: Event time: Execution time: Operation: Symbol: 6-14 0-3 . Multiple Station Select Octal code: Event time: Execution time: Operation: Symbol: MTKF 1, 2 4.25 µs Transfer status of teleprinter flags to AC Teleprinter flags--+ AC·0 - 3 • 0--+ AC 4 - 11 . Multiple Interrupt Octal code: Event time: Execution time: Operation: Symbol: MTON 6113 6123 1, 2 4.25 µs Transfer status of keyboard flags to AC 0 - 3 • KF-+ AC0 - 3 0--+ AC 4 - 11 MINS Multiple Interrupt and Skip Octal code: Event time: Execution time: Operation: Symbol: MTRS 6125 1, 4 4.25 µs Skip if the interrupt request is active (if interrupt is on and any flag is raised). If interrupt request is active, PC+ 1 ~PC Read Station Select Status Octal code: Event time: Execution time: Operation: Symbol: 6127 1, 2, 3 4.25 µs Transfer the status of the selection register to AC 0 • 3 • SR~ AC 0 • 3 0~ AC4-11 DC02-D Instructions Decoder instructions for the DC02-D are in two basic groups: receiver and transmitter. The receiver instructions are 6111, 6112, 6114, and 6116; the transmitter instructions are 6121, 6122, 6124, and 6126. The "Station Select" flip-flop is gated with each device select code; therefore, these IOTs are effective only when a particular station is selected. MKSF Skip On Keyboard Flag Octal code: Event time: Execution time: Operation: Symbol: *MKCC 6111 4.25 µs Skip if the selected keyboard flag is set. IfKF= 1, PC+ 1 ~PC Clear Keyboard Flags Octal code: Event time: Execution time: Operation: 6112 2 4.25 µ.s Clear the keyboard flag of the selected station; clear AC. If the paper tape reader is on, the tape will advance 1 character and the receiver flag will be set approximately 100 ns after issuing the instruction. Symbol: o~KF, o~RF, o~Ac MKRS Read Keyboard Register Static Octal code: Event time: Execution time: Operation: Symbol: * 6114 3 4.25 µ.s Transfer the keyboard register contents to AC 4 • 11 . AC 0 • 11 V KR to AC 0 . 11 On some systems a logic revision has been added which inhibits tape advance and consequent setting of the receiver flag. 6-15 MKRB Load Keyboard Sequence Octal code: Event time: Execution time: Operation: 6116 2,3 4.25 µs Clear the keyboard and reader flags, clear AC; transfer the keyboard register contents to AC 4 - 11 (MKCC and MKRS combined). Symbol: 0-* KF 0-* RF 0-* AC KR --"* AC 4 - 11 MTSF Skip on Teleprinter Flag Octal code: Event time: Execution time: Operation: Symbol: MTCF 6124 3 4.25 µs Load AC 4 - 11 into the teleprinted register (begin print/punch). AC 4 - 11 ~TR Load Teleprinter Sequence Octal code: Event time: Execution time: Operation: Symbol: 6122 2 4.25 µs Clear the teleprinter flag of the selected keyboard station. 0-*TF Multiple Load Teleprinter Register and Print Octal code: Event time: Execution time: Operation: Symbol: MTLS 4.25 µs Skip if the selected teleprinter flag is set. If TF = 1, PC + 1 -* PC Clear Teleprinter Flag Octal code: Event time: Execution time: Operation: Symbol: MTPC 6121 6126 2, 3 4.25 µs Clear the teleprinter flag and load AC 4 - 1 1 into the teleprinter register (MTCF and MTPC combined). o~TF AC 4 - 11 ~TR Multiple Teletype Control, Type DC02-F This control is similar to the DC02-E in operation and design. It consists of a double row of logic (10-1 /2" x 19" nominal rack space) complete with power supplies. This unit will handle up to eight stations. The DC02-F is designed so that four controls may be connected together in such a way that 32 stations total may be operated. A jumper module is used to enable selected signals when the system is expanded. As in the four-station control DC02-E, the high order bits of the' AC are used to select a station. AC 0 - 7 are used to select the stations within one control and AC 8 - 11 are used to select any one of up to four DC02-F controls. Up to 6-16 three separate clocks may be specified. In addition, two frequency divide registers are available with outputs at divide-by-8 and divide-by-128. The resultant timing pulses may be connected in any combination with jumper modules to provide timing for the transmitter and receiver modules of the stations. The specifications for this control are the same as those of the DC02-E. The program instructions are likewise identical except for the following. MTPF Multiple Teleprinter Flag Octal code: Event time: Execution time: Operation: Symbol: MTKF 6113 1, 2 4.25 µs Transfer status of teleprinter flags AC 0 - 7 • AC 8 - 11 selects one of four controls. Teleprinter flags-+ AC 0 - 7 0-+ ACs-11 Multiple Keyboard Flag Octal code: Event time: Execution time: Operation: Symbol: MTON 6123 1, 2 4.25 µs Transfer status of keyboard flags to AC 0 _7 KF-+ AC 0 _7 0-+ ACs-11 Multiple Teleprinter Octal code: Event Time: Execution time: Operation: Symbol: 6117 1, 2, 3 4.25µs Transfer AC 0 _7 to selection register select stations when bits are set. AC 8 _1 1 selects one of four controls. AC 0 _7 -+ SR 0-+ ACa-11 MINS Multiple Interrupt and SKP Octal code: Execution time: Operation: Symbol: MTRS Multiple Teleprinter Read Status Octal code: Event time: Execution time: Operation: Symbol: 6125 4.25 µs Skip if the interrupt request is active (i.e., if interrupt is on and any flag is raised) AC 8 _1 1 select one of four controls. 0-+ AC 8 - 11 6127 1, 2, 3 4.25 µs Transfer the status of the selection register to AC 0 - 7 • AC 8 - 1 1 selects one of four controls. Transfer status of interrupt enable flip-flop to AC 11 . If AC 11 = 1, the interrupt enable is set. SR-+ AC 0 - 7 Interrupt Enable-+ AC 11 0-+ AC 8 -~ 0 6-17 6.2 REAL TIME CLOCKS 6.2.1 Real Time Interface, Type KW12-A The KW 12-A (see Figures 6-5 and 6-6) is a prewired PDP-12 option with an input control panel, which mounts behind the vertical door on the left front of the PDP-12. The Real Time Interface can be used to synchronize the central processor to external events, count external events, measure intervals of time between events, or provide program interrupts at programmable intervals from 2.5 µs to over 40 seconds. Some of the above mentioned operations can be done simultaneously. Figure 6-5. KW 12-A Real Time Interface Time Base The programmable time base provides count pulses to the counter register at any of the following rates derived from a 400 kHz crystal clock: 400 kHz 100 kHz 10 kHz 6-18 1 kHz 100 Hz Input channel 1 may be used to enable an external source to drive the counter. This external source may be switch-selected to be either the power line waveform or an actual signal from a laboratory instrument. The programmable selection of the rate is accomplished with the three rate-bits of the clock control register. Input Synchronizers Three input channels are used to convert external events into a synchronized control and status signal for the clock. Each input channel consists of an input Schmitt trigger with pulse generator, five flip-flops, and associated control gating. The Schmitt trigger and pulse generator converts the preselected voltage threshold crossing by an external signal into a single event (pulse). This Schmitt trigger has level and slope selection controls available on the front panel. They provide selection of ·any threshold between ±6V and either positive or negative-going slope. The Schmitt trigger has a hysteresis of 0.3V. TO AC (12 BITS) CLOCK BUFFER PRESET REG (12 BITS) IO BUS IO AND MODE CONTROL (12 BITS) FROM AC (12 BITS) START A-0 CONVERTER PROGRAM INTERRUPT AND SKIP OVERFLOW LOGIC COUNT CLOCK COUNTER (12 BITS) INPUT 1 CLEAR CLOCK (12BITS) INPUT 2 RATE CONTROL INPUT 3 CRYSTAL 400 kHz 100 kHz 10kHz 1kHz 100 Hz 12-0110 Figure 6-6. KWI 2-A Organization The five Input Circuits flip-flops are: INPUT ENABLE, INPUT, PRE-EVENT, EVENT, and ENABLE EVENT INTERRUPT (see Figure 6-7). Figure 6-8 shows a basic timing of the Input Synchronizer. I 6-19 Not shown in Figure 6- 7 is the logic which clears the EVENT and PRE-EVENT flip-flops when the CLSA instruction is given. This logic ensures that events occurring during the execution o'r the present CLSA instruction are indicated when the next CLSA instruction is given. Input Enable Flip-Flop - Gates on and off input signals to the clock. It is set and cleared under program control. Input Flip-Flop - Set by an external signal from the Schmitt trigger input or under program control with the CLLR instruction. The INPUT flip-flop provides synchronization between external timihg and internal clock timing. Pre-Event Flip-Flop - Strobed into the EVENT flip-flop by the strobe 1 signal. This clears the INPUT flip-flop if EVENT is clear. Event Flip-Flop - Loaded with the PRE-EVENT flip-flop on the next strobe 1 and set to a 1 by the second strobe 1 following the setting of the INPUT flip-flop. Subsequent to EVENT being loaded, PRE-EVENT is cleared. Event Enable Interrupt Flip-Flop - Permits external events to cause program interrupts. It is set and cleared by the CLEN instruction. The occurrence of strobe 2 with EVENT (0) and PRE-EVENT (1) is the actual single event used by other parts of the clock logic such as counting and transfers from counter to buffer register. The status of the EVENT and PRE-EVENT flip-flops is loaded into the AC under program control. When this transfer occurs, the corresponding INPUT, PRE-EVENT, and EVENT flip-flops are cleared. If a second input occurs before the EVENT flip-flop is cleared, then both the PRE-EVENT and EVENT flip-flops will remain set, indicating an error. INPUT ~NABLE SYNC STROBE EVENT PRE EVENT c c INTER. REQ L 0 0 1A ENABLE EVENT INTER. 0 12-0194 Figure 6-7. Simplified Input Synchronizer Logic Diagram 6-20 SYNC. SYNC STROBE1~ I 100ns I I 1 ' -11- STROBE 1 I : :COUNTER I I TO 600n s BUFFER 1-IH/ INPUT FLIP-FLOP SYNC COUNTER HE RE 1 PRE-EVENT FLIP-FLOP PRE-EVENT FLIP-FLOP __J ----=r--1 _j ! INCREMENTED STROBE 2 INPUT FLIP-FLOP UUUT Ii __J I /I .....__ __ I CD r-----i- - - - 1 f _ _ ___. ® ---~ EVENT__ll_ FLIP-FLOP Timing diagram for Channel 1 only if the rote field equals 6 8 and Channel 1 input is enabled. 5 EVENT FLIP-FLOP ----C-P_....IN_T_E~RRUPT HERE NORMAL ERROR NOTES: 1 Normally PRE-EVENT is reset. If however, EVENT was already set, PRE-EVENT remains set as on error f I a g ~ ind i cat in g that more than one input occured between clearing of the EVENT flip-flop. may be used to increment the counter. For this case the timing diagram is shown below. 3. Error indication that 6135 2. EVENT is cleared only by the CPU using the 6135 (CLSA) instruction with the following exception: Inputs to Channel 1 (CLSA) instruction was not issued soon enough following an EVENT. 12 -0205 Figure 6-8. KWl 2-A Timing Diagram Counter Register The counter register is a 12-bit counter that is loaded from the buffer-preset register or can be transferred into the buffer-preset register. The counter may be used to count events, measure intervals of time between events, or provide processor interrupts at program selected intervals from 2.5 µs to over 40 seconds. OVERFLOW Flip-Flop - The OVERFLOW flip-flop is set by the most significant bit of the counter register going from I to 0. Buffer-Preset Register - Used to buffer the current coum in the clock register at the occurrence of an event when operating with Mode 1 (1). With Mode 1 (0) and Mode 2 (1), the buffer-preset register holds the number to be transferred into the counter when overflow occurs. The buffer-preset register can be loaded into the AC or the AC can be transferred into the buffer-preset register. 6. 2.1.1 Use of Interface with A-0 - With Mode 0 (1 ), the occurrence of overflow is used to start an A-D conversion if the A-D is in the Fast Sample Mode. With Clock Mode 0 ( 1), the A-D is triggered only by the clock. When a SAM instruction is given, the result of the last conversion is transferred to the AC, and a new analog channel is selected for the next conversion to be performed when the clock overflows. If the SAM instruction is given while a conversion triggered by the clock is in progress, the processor waits in timestate TS5 until the conversion is complete. 6-21 6.2.1.2 KW12-A Input Panel - The input panel for the clock is located behind the door on the left side of the front of the PDP-12. External signals (from up to three instrument/sources) are connected to the Input jacks on the front panel (see Figure 6-5) via standard 3-conductor telephone plugs. Each Input and Output jack is wired in parallel to permit convenient connection of the external input signals to the KW 12-A and, if desired, the Analog-to-Digital Converter. The input is differential, ±5V range, input resistance greater than 10,000 ohms, and protected against inputs up to ±50V. A level control and a slope control are associated with each input. The level control selects the threshold voltage at which the trigger pulse is generated. The slope determines the polarity of the input signal causing a trigger pulse. The trigger pulse sets the associated input flip-flop of the clock if that input channel is enabled. 6.2.1.3 KW12-A Real Time Interface Instructions - The KW12-A is controlled by PDP-12 IOT instructions. These instructions can be used from either 8 or LINC mode. Execution time for the IOTs is 4.25 µs when in 8 mode and 5 .9 µs when in LINC mode (using IOB). CLSK Skip On Clock Interrupt Octal code: Event time: Execution time: Operation: 6131 4.25 µs Skip if clock interrupt condition exists. The interrupt conditions are as follows: a. b. c. d. CLLR Event l Interrupt (1) and Event 1 (l ). Event 2 Interrupt ( 1) and Event 2 ( 1). Event 3 Interrupt (1) and Event 3 (l ). Overflow Interrupt ( 1) and Overflow ( 1). Load Clock Control Register Octal code: Event tjme: Execution time: Operation: 6132 2 4.25 µs The contents of the AC are transferred to the clock control register. Three bits are used to provide simulated data input to each of the three Event input channels. The AC is unchanged. Bit 00 01 02 03 04 05 06 07 08 09 10 11 6-22 Enable Enable Enable Enable Function Count Rate Register Bit 0 Count Rate Register Bit 1 Count Rate Register Bit 2 Mode Control Register Bit 0 Mode Control Register Bit 1 Mode Control Register Bit 2 Not used Simulate Input to Channel 1 Not used Simulate Input to Channel 2 Not used Simulate Input to Channel 3 The rate of the counter register input count pulses is determined by the contents of the count rate register. Count Rate Register 000 001 010 011 100 101 110 111 Frequency of Count Pulses Stop 400 kHz 100 kHz IO kHz 1 kHz 100 Hz Rate of Input Channel 1 Stop NOTE When Channel 1 is used as the time base for the counter, the Event flag is automatically cleared and Channel 1 Interrupt Enable would normally be left off. Also the clock counter is advanced one count each time an IO PRESET is performed either manually or under program control. The contents of the mode control register determine the method by which the clock system operates. Program Example The following program rings the teleprinter bell once for every 10 inputs ( 60 Hz) on external channel three. If the source knob is turned to line frequency the Teletype bell will ring once/per second on computers connected to 60 Hz power lines. /PSEUDO TO LAP6 DIAL ASSEMBLER PM ODE /CLEAR AC CLA BEGIN, /CLEAR ALL MODES CLLR /CLEAR ENABLES CLEN /NO. OF COUNTS TAD K74 CIA /FORM 25 COMP /LOAD PRESET REG CLAB CLA /CLEAR AC TAD KOIOO /SET AC05=1 CLLR /GENERATE CLEAR COUNTER /CLEAR STATUS AND POSSIBLE OVERFLOW CLSA CLA /CLEAR AC TAD K0320 /LOAD AC CLEN /LOAD BUFFER INTO COUNTER, ENABLE INTERRUPT ON OVERFLOW, AND ENABLE IN PUT CHAN 1 CLA /CLEAR AC TAD K6100 /LOAD AC CLLR /START CLOCK BY ENABLING RATE LOOP, CLSK /SKIP ON CLOCK FLAG JMP LOOP /WAIT CLSA /CLEAR STATUS CLA /CLEAR AC TAD K207 /LOAD AC TLS /RING TELEPRINTER BELL JMP LOOP /RETURN TO WAIT LOOP K74, 74 /CONSTANTS KOIOO, 100 K0320, 320 K6100, 6100 K207, 207 6-23 Mode Control Register 000 Free-run Counter runs selected rate. Overflow occurs every 4096 counts. The overflow flag remains set until cleared with CLSA instruction. 001 Preset Time Counter runs at selected rate. When overflow occurs, the contents of the Clock Buffer-Preset register are transferred automatically to the Counter which continues. The Overflow flag remains set until cleared with a CLSA instruction. When Mode is changed from XOO to XO 1, the clock counter is zeroed. 010 Time Base (measures intervals between events) Counter runs at selected rate. On the occurrence of an Input Event, the contents of the counter are transferred automatically to the Buffer Preset register, and the counter continues to count. 011 Time Base (measures intervals between events) This is identical to Mode 10, except that the Clock Counter register is cleared after its contents have been transferred to the Buffer Preset register on Event 3. Events 1 and 2 remain only to cause transfer from the clock counter to the Buffer Preset register. 100 101 110 111 When Mode bit 0 is set to a l, the occurrence of Overflow is used to trigger the A-D converter if A-D control also has the FAST-SAMPLE flip-flop set. This allows analog-to-digital conversions to take place under the automatic timing control of the clock. In this mode, A-D conversions are triggered only by the clock counter overflow. The SAM instruction reads the result of the previous conversion and sets the channel number for the next conversion. For details of the Analog-to-Digital converter, see Paragraph 6.11. The remaining two Mode Control bits are decoded exactly as above. CLAB AC to Buffer Preset Register Octal code: Event time: Execution time: Operation: CLEN Load Clock Enable Register Octal code: Event time: Execution time: Operation: 6-24 6133 2 4.25 µs Transfer AC to Buffer Preset register. The previous contents of the Buffer Preset registers are lost and the AC is unchanged. 6134 3 4.25 µs The contents of the AC are transferred to the Clock Enable register. The function of each bit is given below: Function Bit 00 01 02 03 04 05 06 07 08 09 10 11 CLSA Clock Status to AC Octal code: Event time: Execution time: Operation: 6135 1,3 4.25 µs This instruction interrogates the CLOCK INPUT and OVERFLOW STATUS flip-flops. The clock status information is inclusive ORed into the AC. Then the AC status bits which are set are cleared. This ensures that only one occurrence of an EVENT will be transferred to the program. AC Bit 00 01 02 03 04 05 06 07 08 09 10 11 CLBA Status Condition OVERFLOW Flip-Flop Not used Not used Not used Not used Not used Event 1 Pre-Event I Event 2 Pre-Event 2 Event 3 Pre-Event 3 Buffer Preset Register to AC Octal code: Event time: Execution time: Operation: CLCA Not used Not used Not used Not used Inclusive OR Clock Buffer into counter if mode= XOI and overflow= 0 Enable Interrupt when overflow ( 1) Enable Interrupt on Event 1 Enable Input Channel 1 Enable Interrupt on Event 2 Enable Input Channel 2 Enable Interrupt on Event 3 Enable Input Channel 3 6136 2,3 4.25 µs The AC is cleared and the contents of the Clock Buffer Preset register are transferred into the AC. Counter to AC Octal code: Event time: Execution time: Operation: 6137 1,2,3 4.25 µs The AC is cleared and the contents of the Clock Counter are transferred to the BUFFER-PRESET register. Then the contents are transferred into the AC. 6.2.2 KW12-B and KW12-C Fixed-Interval Clocks The KWl 2-B provides a means of interrupting the CP at intervals determined by a variable RC Oscillator. The KWl 2-C is similar to the KWl 2-B except that the RC oscillator is replaced by a crystal oscillator with a single fixed frequency. The KWl 2-B or KWl 2-C may be turned on or off under program control. However, variations in frequency require physically altering or changing the oscillator. 6-25 Instruction Set The KWl 2-B and KWl 2-C are controlled by IOT instructions. These instructions can be used from either mode. Execution time for the Simple Clock IOTs is 4.25 µs when in 8 mode and 5.9 µs when in LINC mode (using IOB). CSOF Skip on Clock Flag Octal code: Execution time: Operation: CTOC 6131 4.25 µs Skip if clock flag is set. Turn Off Clock Octal code: Execution time: Operation: 6132 4.25 µs Turn off the clock, clear the clock flag, and disable the clock interrupt. CTON Turn On Clock Octal code: 6134 4.25 µs Execution time: Turn the clock on and clear the flag. Operation: CRUN Clock Running Octal code: Execution time: Operation: 6135 4.25 µs Turn on the clock, enable the clock interrupt, clear the clock flag, skip if the clock flag was set when the instruction was issued. Frequency Range KW12-B KW12-C 6-26 The KW 12-B uses the M401 variable clock in slot F 18 for a time base. The frequency may be varied with a range by adjusting a potentiometer on the module. Five frequency ranges are available. The KW 12-B is nominally set to the 1. 7 5 kHz-to- I 7. 5 kHz frequency range by jumpering Fl8N2 to Fl8T2. Other frequency ranges may be achieved by removing the jumper from Fl 8T2 and attaching as shown below. The exact frequency may be checked by observing the signal on Fl 8D2 with an oscilloscope. Frequency Range Interconnections Required 17.5 kHz to 50 kHz 1.75 kHz to 17.5 kHz 175 Hz to 1. 7 5 kHz F18N2 - Fl8S2 F 18N2 - F 18T2 (nominal setting) F18N2 - F18P2 The KW 12-C uses the M405 crystal clock in slot F 18 for a time base. The frequencies are fixed by a series resonant crystal oscillator to obtain a frequency stability of .01 percent of the specified value between 0°C and +55°C. The frequencies available are in the range of 5 kHz to 50 kHz .and must be specified in advance by the customer. 6.3 DISK STORAGE 6.3.1 Random Access Disk File, Types DF/0$32 and DF/DS32-D The DF32 and DF32-D operate through the three-cycle data break facility to provide 32, 768 13-bit words (12 bits plus 1 parity bit) of storage, and are economically expandable to 131,072 13-bit words using the respective expander disk, DS3 2 or DS3 2-D. The DF32 and DF32-D comprise two basic assemblies: the storage unit containing the read/write circuits and the computer interface logic. The storage unit contains a nickel cobalt plated disk driven by a hysteresis synchronous motor. Data is recorded on a single disk surface by 16 read/write heads in fixed positions. The disk motor, read/write data heads, and photocell assembly (on DF32) are all mounted on a rack assembly that permits sliding the unit in and out of a DEC 19-inch Standard Cabinet. The following table summarizes the DF32 and DF32-D: DF32 DF32-D 60Hz SOHz 60Hz SO Hz Data Transfer rate (microseconds per word) 66 80 32 39 Average Access Time (milliseconds) 16.67 20 Same Same Timing and Address Track "Start & Finish" Sensing Photo-electric reflective marker on disk outer perimeter Special Start and Finish coding and decoding on timing track Type of Logic Negative DF32DP - Positive DF32DN - Negative Instructions The DF32 and DF32-D disk systems share the following instruction set: DCMA Clear Disk Memory Address Register Octal code: Event time: Execution time: Operation: Symbol: 6601 4.25 µs Clears Memory Address Register, parity error, and completion flags. This instruction clears the disk memory request flag and interrupt flags. 0 ~ completion flag 0 ~error flag 6-27 DMAR Load Disk Memory Address Register and Read Octal code: Event time: Execution time: Operation: Symbol: DMA W 1,2 4.25 µs The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begins to read information from the disk into the specified core location. Clears parity error and completion flags. Clears interrupt flags. AC 0 - 11 ~ DMA 0 - 11 0 ~ completion flag 0 ~ error flag Load Disk Memory Address Register and Write Octal code: Event time: Ex ecu ti on time: Operation: Symbol: DCEA 6603 6605 1,3 4.25 µs The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begins to write information onto the disk from the specified core location. Clears parity error and completion flags. Clears interrupt flags. Data break must be allowed to occur within 66 microseconds after issuing this instruction. ACo-11 ~ DMAo-11 0 ~ completion flag 0 ~ error flag Clear Disk Extended Address Register Octal code: Event time: Execution time: Operation: Symbol: 6611 4.25 µs Clears the Disk Extended Address and Memory Address Extension register. 0 ~ Disk Extended Address Register 0 ~ Memory Address Extension Register DSA C Skip on Address Confirmed Flag Octal code: Event time: Execution time: Operation: Symbol: 6612 2 4.25 µs Skips next instruction if address confirmed Flag is set. Flag is set for 16 µs (AC is cleared). If address confirmed flag = 1, then PC+l~PC DEAL Load Disk Extended Address Octal code: Event time: Execution time: Operation: Symbol: 6-28 6615 1,3 4.25 µs The disk Extended Address and Memory Address Extension registers are cleared and loaded with the track address data in the AC. AC 6 - 8 ~Core Memory Extension AC 1-s ~Disk Address Extension 32K, 64K, 96K, l 28K AC 0 9 - 1 1 used in DEAC instruction (See NOTE on opposite page) DEAC Read Disk Extended Address Register Octal code: Event time: Execution time: Operation: Symbol: 6616 2,3 4.25 µs Clear the AC then load the contents of the disk Extended Address register into the AC allowing program evaluation. Skip next instruction if address confirmed flag is set. Disk Address Extension 32K, 64K, 96K, 128K--+ AC 1 -s Core Memory Extension --+ AC 6 - 8 Photo-cell sync mark--+ AC0 (Available 200 µs) Data Request Late flag --+ AC 9 Non-Existent or Write Lock switch on--+ AC 10 Parity Errors --+ AC 1 1 NOTE For the DEAL and DEAC instructions, refer to the diagrams shown below. BITS 1-5 (DEAL INST) ACCUMULATOR (LOW ORDER 12 BITS) 0-11 of DMAW or DMAR DISC ADDRESS (17 BIT) CELL 7751 (CURRENT ADDRESS) CURRENT ADDRESS (MEMORY) ADDRESS (15 BIT) FIELD BITS 6-8 (DEAL INST) DFSE Skip on Zero Error Flag Octal code: Event time: Execution time: Operation: Symbol: DFSC 6621 4.25 µs Skips next instruction if parity error, data request late, and write lock switch flag are clear. Indicates no errors. If Parity Error flag = 1 and Data Request Late flag= 1, and Write Lock Switch flag = 1, then PC + 1 --+ PC Skip on Data Completion Flag Octal code: Event time: Execution time: Operation: Symbol: 6622 2 4.25 µs Skips next instruction if the completion flag is set. Indicates data transfer is complete. If Completion flag = 1, PC + I --+ PC 6-29 DMA C Read Disk Memory Address Register Octal code: Event time: Execution time: Operation: Symbol: 6626 2,3 4.25 µs Clears the AC then loads contents of the Disk Memory Address register into the AC allowing program evaluation. During read, the final address is the last one transferred. DMAo-11 ~ ACo-11 The computer can handle 12 bits; therefore, the high order bits for Disk and Memory addresses are manipulated by the DEAL and DEAC instructions. Low order bits are manipulated in the accumulator (AC). The Disk address is a 17-bit value. Bit 1 of the DEAL and DEAC instructions is the most significant bit. The Memory address is a 17-bit value. Bit 6 of the DEAL and DEAC instructions is the most significant bit. Note that the Word Count 7750 is the two's complement of the number of words to be transferred and that the Disk address is the desired starting address. The Memory or Current address (7751) is the desired address-I. NOTE Write Lock Switch status is true only when the disk module contains write instructions. The nonexistent disk condition will appear following the completion of a data transfer during read, where the address acknowledged was the last address of a disk and the next word to be addressed falls within a nonexistent disk. The completion flag for the data transfer is set by the nonexistent disk condition 16 microseconds following the data transfer. 6.3.2 Disk Memory System Type RF/RS08 The RF08 control and RS08 disk combine as a fast, low-cost, random access bulk storage package for the PDP-l 2A. One RS08 and RF08 provide 262, 144 13-bit words (12 bits plus parity) of storage. Up to four RS08 disks can be added to the RF08 control for a total of 1,048,576 words of storage. Data transfer rate on 60 Hz power is 16.2 microseconds per word or 20 microseconds per word on 50 Hz. Data transfer is accomplished through the three-cycle data break system of the PDP-l 2A. Average access time with a 60 Hz disk is 16.67 milliseconds, or 20 milliseconds at 50 Hz power. Worst case access time is 33 milliseconds on 60 Hz power, or 40 milliseconds on SO Hz power. The RS08 disk unit contains a nickel-cobalt plated disk driven by a hysteresis synchronous motor. Data is recorded on a single disk surface by 128 fixed read/write heads. The RF08 and RS08 are designed for mounting in a standard 19-inch DEC cabinet. The input-output transfer instructions for the RF /RS08 Disk Mem9ry system are identical with the input-output transfer instructions for the Type DF32 Random Access Disk file (Table 6-4). Instructions The RF/RS08 has the following DF32 Programming Compatibility: DCMA Clear Disk Memory Address Register Octal code: Event time: Execution time: Operation: 6-30 6601 4.25 µs Clear the Disk Memory Address register, and all other disk and maintenance flags except interrupt enable. DMAR Load Disk Memory Address Register and Read Octal code: Event time: Execution time Operation: 6603 1,2 4.25 µs Load the low order 12 bits of the Disk Memory Address with information (initial address) in the accumulator. Then clear the AC. Begin to read information from the disk into the specified core location. Clear parity error and completion flags. Clear interrupt flags. During Read, the final address status is the last address transferred+ 1. When reading the last address of the last available disk the nonexistent disk flag is raised in coincidence with the completion flag. DMA W Disk Memory Address Register and Write Octal code: Event time: Execution time: Operation: 6605 1,3 4.25 µs Load the low order 12 bits of the Disk Memory Address register with information (initial address) in the accumulator (AC). Then clear the AC. Begin to write information onto the disk from the specified core location. Clear parity error and completion flags. Clear interrupt flags. During Write, the final address status is the last address transferred. Write Lock Switch status is true only when disk module contains a Write Command. PROCESSOR ACCUMULATOR 0 2 4 5 6 7 8 9 DISK ADDRESS REGISTER LOW ORDER BITS - - - - - - - - - - - - - - - - - - - - LEAST SIGNIFICANT BITS It The DF32 maintenance instruction IOT 663X is not assigned to the RF08 system. DCIM Clear Interrupt Enable and Core MA Extension Registers Octal code: Event time: Execution time: Operation: DSAC 6611 4.25 µs Clears the disk interrupt enable and core memory address extension registers. Skip on Confirmed Flag Octal code: Event time: Execution time: Operation: 6612 2 4.25 µs Maintenance Instruction Skip next instruction if the Address Confirmed flag is a I. (AC is cleared.) 6-31 DIML Clear Interrupt Enable and MA Extension Register and Load Octal code: Event time: Execution time: Operation: 6615 1,3 4.25 µs Clears the interrupt enable, and memory address extension register. Then loads the interrupt enable and memory address extension registers with data held in the accumulator. Then clears AC. INT ENB CLOCK INT ENB ERR I EX EX MEM INT ENB COM PL I MEM EX MEM I ~ PROCESSOR ACCUMULATOR RF08 STATUS REG DIMA Clear AC and Load from Status Octal code: Event time: Execution time: Operation: 6616 2,3 4.25 µs Clears the accumulator. Then loads the contents of the status into the accumulator to allow program evaluation PROCESSOR ACCUMULATOR RF08 STATUS REG DFSE Skip on Zero Error Flag Octal code: Event time: Execution time: Operation: 6-32 6621 1 4.25 µs Skips the next instruction if there is a Parity Error, Data Request Late, Write Lock Status, or Nonexistent Disk flag set. DFSC Skip on Data Completion Flag Octal code: Event time: Execution time: Operation: DISK 6622 2 4.25 µs Skips next instruction if the Completion flag is a 1 (data transfer is complete). Skip on Error or Completion Flag Octal code: Event time: Execution time: Operation: 6623 1,2 4.25 µs Skips next instruction if either the Error or Completion flags or both are set. DMAC Read Disk Memory Address Register Octal code: Event time: Execution time: Operation: DCXA 4.25 µs Clears the accumulator. Then loads the contents of the Disk Memory address register into the accumulator to allow program evaluation. This instruction must be issued when the completion flag is set. Clear Address Register Octal code: Execution time: Operation: DXAL 6626 2,3 6641 4.25 µs Clears the high order 8-bit disk address register. Clear Address Register and Load from AC Octal code: Execution time: Operation: 6643 4.25 µs Clears the High Order 8 bits of the disk address register. Then loads the disk address register from the data held in the accumulator. Then clears the AC. PROCESSOR ACCUMULATOR RF08 DISK SELECT LEAST SIGNIFICANT BITS _______,. DXA C 12-0114 Clear AC and Load Octal code: Execution time: Operation: 6645 4.25 µs Clears the accumulator, then loads the contents of the High Order 8-bit disk address register into the accumulator. 6-33 PROCESSOR ACCUMULATOR RF08 LEAST SIGNIFICANT BITS ---1~- DMMT 12-0109 (Maintenance Instruction) Octal code: Execution time: Operation: 6646 4.25 µs For maintenance purposes only, with the appropriate maintenance cable connections and the disk disconnected from the RS08 logic, the following standard signals may be generated by IOT's 646 and associated AC bits. AC is cleared. The maintenance register is initiated by issuing an IOT 601 command. AC 11 (1) AC100) AC 9 (1) AC 7 (1) AC6 (1) AC 0 (1) Track A Pulse Track B Pulse Track C Pulse DATA PULSE (DAT A HEAD #0) + 1 Photocell +lDBR Setting DBR to a 1 causes Data Break Request in computer. NOTE TAP must be generated to strobe Track B signal into address comparison network. Disk Address Register - 20 bits !sfmTj r-B~S +· I TRACK POSITION .,.. a:+s TRACK SELECT Bl~S DISK EXTENDED MEMORY ADDRESS 8 BITS + DISK MEMORY ADDRESS 12 BITS I ., ~ Programming Example A programming example that writes a block of data onto the disk is shown below. For simplicity, the example assumes that all data and instructions are within the same page, but in actual practice this may not be true. 6-34 Table 6-4. DF32 Instructions Compared with RF/RS08 Instructions DF32 Mnemonic Octal Code RF08 Mnemonic RF08 to DF32 Comparison DCMA 6601 same Identical functions. DMAR 6603 same Identical functions. DMAW 6605 same Identical functions. DCEA 6611 DCIM Clears interrupt enable, does not clear EMA. On both units, clears memory address extension. DSAC 6612 same Identical functions. DEAL 6615 DIML Similar, except functions transmitted from the AC are different. EMA information not transmitted. See DXAL. DEAC 6616 DIMA Similar, except that functions transmitted to the AC are different. See DXAC. DFSE 6621 same Instruction is skip on error, rather than skip-no error. NXD added as an error. DFSC 6622 same Identical function. (none) 6623 DISK New instruction. Skips on error or data completion, or both. (DFSE and DFSC combined.) Skip enabled at IOP 2. DMAC 6626 same Identical functions. (none) 6641 DCXA Clears EMA. (none) 6643 DXAL Clear and load EMA with information in the accumulator. (none) 6645 DXAC Clear accumulator and load address in EMA into the accumulator. (none) 6646 DMMT Maintenance instruction. See description. 6-35 SUB, /CALLING SEQUENCE JMS WRT 0 0 0 0 xxx WRT, /WRITE SUBROUTINE 0 TAD IWRT DCAWC ISZ WRT TAD IWRT DCACA ISZ WRT TADIWRT DIML ISZ WRT TAD IWRT DXAL ISZ WRT TAD IWRT DMAW DISK JMP .-1 DFSE JMP .+2 JMP ERR ISZWRT JMP I WRT /JUMP TO WRITE SUBROUTINE /CONTAINS WORD COUNT /CONTAINS INITIAL CORE MEMORY ADDRESS /CONTAINS TRACK AND UNIT NUMBER /CONTAINS TRACK ADDRESS /CONTINUE WITH MAIN PROGRAM /ENTER WRITE SUBROUTINE /FETCH WORD COUNT /DEPOSIT IN WORD COUNT REGISTER /INCREMENT POINTER /FETCH INITIAL CORE MEMORY ADDRESS /DEPOSIT INTO CURRENT ADDRESS REGISTER /INCREMENT POINTER /FETCH TRACK AND UNIT NUMBER /DEPOSIT INTO REGISTER IN RF08 CONTROL /INCREMENT POINTER /FETCH TRACK ADDRESS /TRACK ADDRESS TO DMA IN DISK; /START WRITE OPERATION /WRITE OPERATION /FOR ERROR OR COMPLETE /NO, WAIT /ANY ERRORS? /NO, SKIP OVER ERROR EXIT /YES, TO ERROR SUBROUTINE /INCREMENT POINTER TO EXIT ADDRESS /EXIT PROGRAM NOTE This coding assumes no live interrupts. The calling subroutine must be set up so that the subsequent locations to SUB (SUB+ I, SUB+2, etc) contain the parameters as shown in the comments column. The JMS WRT instruction causes a subroutine jump location WRT with the contents of the PC-I (which contains symbolic address SUB-1) deposited into location WRT. Since location WRT now contains SUB+l, the first instruction of the subroutine (TAD I WRT) loads the AC with the contents of SUB+l or the word count. The word count is then deposited into the WC (Memory Address 7750) register. Similarly, the initial address is deposited into the CA (Memory Address 7751) register. The program then proceeds to set up the EMA and OMA registers and starts the write operation. After the OMAW instruction is issued, the data transfer operation begins and continues independently of the program; it operates under control of the data break facility to transfer data. When the transfer is complete, the DCF (Data Complete Flag) comes up and, when sensed by the DFSC control, passes to the DFSE instruction. DFSE then senses for errors; and if any are detected, control jumps to an error or diagnostic (not shown) routine. If no errors are found, control exits from the subroutine back to the main program to resume main processing. It should be noted that, since the data transfer operates independently of the program, the subroutine could be exited following the DMAW instruction. An interrupt subroutine could handle the post data transfer processing, since the DCF and ERROR FLAGS generated an interrupt. 6-36 An identical program could handle data transfers for a read operation, except that the DMAW instruction is replaced by the DMAR instruction. Specifications: Storage Capacity Each RS08 stores 262, 144 13-bit words (12 plus one parity bit). Disks Four RS08s may be controlled by one RF08 for 1,048,576 words. Data Transfer Path Three-Cycle Break Address Locations 7750 Word Count 77 51 Memory Address Data Transfer Rate 60 Hz Power 16.2 µs per word 50 Hz Power 20 µs per word Minimum Access Time 258 µs 320 µs Average Access Time 16.9 ms 20.3 ms Maximum Access Time 33.6 ms 40.3 ms Program Interrupt 33 ms Clock Flag Data Transmission Complete Flag Error Flag Write Lock Switches Eight switches per disk capable of locking out any combination of eight 16,384 word blocks in address 0 to 131,071. Data Tracks 128 Words Per Track 2048 Recording Method NRZI Density 1100 BPI Maximum Timing Tracks 3 plus 3 spare Operating Environment Recommended temperature 65° to 90°F. Relative humidity 20% to 80%. No condensation during storage or operating. Vibration/Shock Good isolation is provided. Vibrating, shaking, or rocking of the cabinet with large, low frequency displacements can cause data errors. For example, hand fork lift trucks operating on wooden floors cause excessive vertical displacements which could cause errors. The RS08 is not designed for aircraft or shipboard mounting. Heat Dissipation RF08: 150 watts RS08: 500 watts AC Power Requirements 115 ± 10 Vac, single phase, 50 ± 2 or 60 ± 2 Hz RS08 Motor start 5.5 amps for 20 ± 3 sec. Motor run 4.0 amps continuous. 6-37 Line Frequency Stability Maximum line frequency drift 0.1 Hz/sec. A constant frequency motor-generator set or static ac/ac inverter should be provided for installations with unstable power sources. Reliability Six recoverable errors and one nonrecoverable error in 2 x 10 9 bits transferred. A recoverable error is defined as an error that occurs only once in four successive reads. All other errors are nonrecoverable. On-off cycling of the RS08 is not recommended. The RS08 motor control operates independently of the computer power control, thus eliminating on-off cycling except for power failures. Cabinet A H950 cabinet is designed to accommodate one RF08, up to two RS08s, and power supplies. Two additional RS08s can be mounted in a second H950. Other equipment should not be mounted in disk cabinets. 6.3.3 RKB Disk Cartridge Memory System The RK08 Control and RKOl Disk Drive (RK8) are low cost, random access, removable disk storage devices. One RK08/RKO 1 provides 831,488 13-bit (12 bits plus parity) words of storage. Up to four RKO 1 disks can be operated by the RK08 Control for a total of 3,325,952 words of storage. The removable cartridge utilized is an IBM 2315 disk pack or equivalent with a single aluminimum disk platter coated on both sides with magnetic oxide. Average access time is 154 milliseconds with the read/write head at random positions. Data transfer rate is 16. 7 microseconds via the PDP-12 single-cycle data break facility. The RK8-P will operate off the positive I/O bus. An RK8-N is also available for connection to a negative I/O bus. Instructions DLDC Load Command Register Octal code: Operation: 6732 Loads the Command Register from the AC, clears the AC. AC 0 2 3 4 5 6 7 8 9 10 11 COMMAND REGISTER ENABLE CHANGE IN INTERRUPT STATUS DOUBLE DENSITY ENABLE PROGRAM INTERRUPT ON TRANSFER DONE EXTENDED MEM ADDRESS ENABLE INTERRUPT ON ERROR DISK FILE NUMBER UNUSED SEEK TRACK a SURFACE ONLY ENABLE READING OR WRITING OF 2 HEADER WORDS LOGICAL 1 =FUNCTION TRUE 6-38 12-020"3 *DLDR Load Disk Address and Read Octal code: Operation: *DLDW Load Disk Address and Write Octal code: Operation: *DCHP 6733 Loads track, surface, and sector address from AC, then clears AC and starts to read data from disk if Command Register bit 4 = 0. 6735 Loads track, surface, and sector address from AC, then clears AC. Starts to write on disk if Command Register bit 4 = 0. Load Disk Address and Check Parity Octal code: Operation: 6737 Loads track, surface, and sector address from AC, then clears AC. Reads data and checks parity if Command Register bit 4 = 0. AC TRACK ADDRESS REGISTER 0 2 3 4 5 6 7 9 8 10 11 SURFACE /SECTOR ADDRESS L-__,1,--'--~-'----'-....L.-...L...-..._jr--"-.....a..-----REGISTER '-----y----' TRACK ADDRESS SECTOR ADDRESS SURFACE BIT 12-0199 *-If command register bit 4 = 1, instruction will be executed only to seek track and surface. These three instructions start all disk operations. 6-39 DRDA Read Disk Address Octal code: Operation: 6734 Clears AC and then reads Track Address Counter and surface/sector counter into AC. DRDC Read Disk Command Register Octal code: Operation: DRDS 6736 Clears AC then reads Command Register into the AC. Read Disk Status Register Octal code: Operation: 6741 Clears the AC and then reads the Status Register into the AC. AC 2 3 4 5 6 7 8 9 10 STATUS REGISTER ERROR TRANSFER DONE CONTROL BUSY ERROR TIME OUT ERROR PARITY OR TIMING ERROR DATA RATE ERROR TRACK ADDRESS ERROR SECTOR NO GOOD ERROR WRITE LOCK ERROR TRACK CAPACITY EXCEEDED ERROR SELECT ERROR BUSY LOGICAL 1= FUNCTION TRUE DCLS Clear Status Register Octal code: Operation: 6-40 6742 Clears the Status Register. 12-0201 DMNT Load Maintenance Register Octal Code: Operation: 6743 Loads Maintenance register from AC and carries out the operation specified. Bits will remain set until DMNT is issued with AC bits= 0. AC 0 2 3 4 5 6 7 8 9 10 11 MAINTENANCE REGISTER LOGICAL 1 =FUNCTION TRUE 12-0202 AC Bit 0 I 2 3 4 5 6 7 8 9-11 DLDA Load Disk Address (Maintenance Only) Octal code: Operation: DSKD Loads the disk address register with the content of AC. 6745 Skips next instruction if the Transfer Done Flag is a 1. Skip on Error Flag= 1 Octal code: Operation: DCLA 6731 Skip on Transfer Done Flag= 1 Octal code: Operation: DSKE Transfer contents of Track address Register to Track counter Register. Transfer Data Register to Serial Register. Transfer Serial Register to Data Register. Oear AC and Read Data Register into AC. Shift a "1" into the Serial Register. Shift a "O" into the Serial Register. Unformatted Disk Sector Pulse. Index Pulse. Not used. 6747 Skip when Error flag is equal to 1. Clear All Octal code: Operation: 6751 Clears selected Disk to Track 000. Then clears all control registers and flags except disk selection. Transfer done set when disk positioned on Track 000. 6-41 DRWC Read Word Count Register Octal Code: Operation: DL WC 6753 Loads Word Count register from AC, then clears the AC. Load Current Address Register Octal code: Operation: DRCA Clears AC, then reads the contents of the Word Count register into the AC. Load Word Count Register Octal code: Operation: DLCA 6752 6755 Load Current Address register from AC; then clears the AC. Read Current Address Register Octal code: Operation: 6757 Clears the AC then reads the contents of the Current Address register into the AC. Example of 1/0 Subroutine DISKIO, 0 TAD CNT DLWC TAD CUR DLCA TAD 0000 DLDC TAD ADR DLDR DSKD JMP .-1 DSKE JMP I DISKIO JMP ERR CNT CUR ADR 0 0 0 /SUBROUTINE ENTRY POINT /FETCH# OF WORDS TO BE READ /LOAD WORD COUNT REGISTER /FETCH ADD OF MEMORY BUFFER /LOAD CUR ADDR. REGISTER /PUT COMMAND IN ACCUMULATOR /LOAD COMMAND REGISTER /FETCH TRACK, SURF ACE, & SECTOR /LOAD DISK ADR AND READ DATA /DLDW WOULD HAVE WRITTEN /DONE WITH TRANSFER? /NO - GO BACK 1 /YES - IS THERE AN ERROR? /NO ERROR - RETURN /GO TO ERROR SUBROUTINE /#WORDS TO BE READ /BEG. ADDR. OF MEMORY BUFFER /DISK ADDRESS Models* RK8-P Positive Bus System; includes RKOl and RK08-P RK8-N Negative Bus System; includes RKOl and RK08-N RKOl Consists of disk drive, interface and removable cartridge {up to 4 per RK8 system) RK08-P Positive Bus disk control RK08-N Negative Bus disk control * See RK8 Manual for details. 6-42 Specifications Disks Four RKOls per RK08 for 3,325,952 words. Storage Capacity Each RKO 1 stores 831,488, 12-bit words. Data Transfer Rate 16. 7 µs per word Transfer Pa th Single-cycle Data Break Minimum Access Time 2.35 ms Average Access Time 154 ms Maximum Access Time 477 ms Settle Time 37 ms Program Interrupt Transfer Done Flag Write lock Two words at the beginning of each track contain status information that is automatically checked for write lock of sectors. Also total disk can be write-locked. Data Tracks 200 plus 3 spare Words per Track 4096 (2048 on each of two sides) Sectors 16 per track Words per Sector 256 Min. Block Size 256 words Max. Block Size 4096 words Recording Method Double Frequency-Time plus Data Density 1026 bits/inch max. Speed 1500 rpm Environmental Requirements Operating Temp +65°F to 90° Operating Humidity 20% to 80% excluding all conditions which would cause condensation. Heat Dissipation RK08 - 150 watts RKOl per drive; 700 watts, 1 KW, surge AC Power Requirements 115 ±10 VAC, 60 ±Yi Hertz 230 ±20 VAC, 60 ±Yi Hertz 6-43 Mechanical Package One standard DEC cabinet will accommodate the RK08 and one RKOI. A second cabinet will house two RKO I units. A third cabinet will house a fourth RKOl. 6.3.4 Disk Software Mass Storage LAP6-DIAL-MS, commonly referred to as DIAL-MS or DISK-DIAL, is a modified version of LAP6-DIAL that may use a disk for the LAP6-DIAL System and/or user programs. The minimum hardware configuration required is 8K of core storage and two LINCtape transports. LAP6-DIAL-MS will support one of the following: a. One or two DF32 or FD32D Disks b. One to four RF08 Disks c. One RK8 Disk. LAP6-DIAL-MS will use only one of the above; for example, the RK8 rather than a DF32, or a RK8 rather than a RF08, if more than one are installed in the system. It is not possible to operate a DF32 and a RF08 in the same system as the IOT instructions are similar. A brief description of LAP6-D IAL-MS is provided in Paragraph 7.1.1. 6-44 6.4 MAGNETIC TAPE 6.4.1 Automatic Magnetic Tape Control, Type TC58 Functional Description The Type TC58 will control the operation of a maximum of eight digital magnetic tape transports, Types TU20 and TU20A. The Type TC5 8 interfaces with the PDP-12 three-cycle data break facility, which it uses for data transfer directly between system core memory and magnetic tape. The tape transports offer industry compatibility (or IBM compatibility) in both 7- and 9-channel tape transports with the following characteristics: Transport Tape Speed (ips) Densities (bpi) TU20 (7-channel) TU20A (9-channel) 45 45 200/556/800 800 Transfers are governed by the memory word count (WC) and current address (CA) registers associated with the assigned data channel (memory locations 32 8 and 33 8 ). Since the CA is incremented before each data transfer, its initial contents should be set to the desired initial address minus one. The WC is also incremented before each transfer and must be set to the two's complement of the desired number of data words to be transferred. In this way, the word transfer which causes the word count to overflow (WC becomes zero) is the last transfer to take place. The number of IOT instruction required for the TYPE TC58 is minimized by transferring all necessary control data (unit number, function, mode, direction, etc) from the PDP-12 accumulator (AC) to the control using IOT instructions. Similarly, all status information (status bits, error flags, etc) can be read into the AC from the control unit by IOT instructions. During normal data reading, the control assembles 12-bit computer words from successive frames read from the information channels of the tape. During normal data writing, the control disassembles 12-bit words and distributes the bits so they are recorded on successive frames of the information channels. Instructions The instructions for the Magnetic Tape Control System are as follows: MTSF Skip on Error Flag or Magnetic Tape Flag Octal code: Event time: Execution time: Operation: Symbol: MTCR 4.25 µs The status of the error flag (EF) and the magnetic tape flag (MTF) are sampled. If either or both are set, the contents of the PC are incremented by one, skipping the next instruction. If MTF or EF = I, PC + I --+ PC Skip on Tape Control Ready Octal code: Event time: Execution time: Operation: Symbol: 6701 6711 .} 4.25 µs If the tape control is ready to receive a command, the PC is incremented by one, skipping the next instruction. If Tape Control Ready, PC + 1 --+ PC 6-45 MTTR Skip on Tape Transport Ready Octal code: Event time: Execution time: Operation: Symbol: MTAF Symbol: 6724 3 4.25 µs Inclusively OR the contents of the command register into AC 0 - 11 . AC V command register-+ AC 0 - 11 Inclusive OR Contents of Accumulator Octal code: Event time: Execution time: Operation: Symbol: MTLC 6712 4.25 µs Clears the status and command registers, and the EF and MTF if tape control is ready. If tape control is not ready, clears MTF and EF flags only. If tape control is ready, 0-+ MTF, 0-+ EF, 0-+ command register If tape control not ready, 0 -+ MTF, 0 -+ EF Inclusive OR Contents of Command Register Octal code: Event time: Execution time: Operation: Symbol: MTCM 4.25 µs The next sequential instruction is skipped if the tape transport is ready. If tape unit ready, PC+ 1 -+PC Clear Regi.sters, Error Flag and Magnetic Tape Flag Octal code: Event time: Operation: MTRC 6721 6714 3 4.25 µs Inclusively OR the contents of ACo-s ,9 - 11 into the command register: JAM transfer bits 6, 7, 8 (command function). AC 0 - 5 , AC 9 - 11 V command register-+ command register AC 6 - 8 -+ command register bits 6-8 Load Command Register Octal code: Event time: Execution time: Operation: Symbol: 6716 2,3 4.25 µs Load the contents of AC 0 - 11 into the command register. AC 0 - 11 -+command register Inclusive OR Contents of Status Register Octal code: Event time: Execution time: Operation: Symbol: 6-46 6704 3 4.25 µs Inclusively OR the contents of the status register into AC 0 - 1 1 Status Register V AC-+ AC0 - 11 MTRS Read Status Register Octal code: Event time: Execution time: Operation: Symbol: MTGO Mag Tape GO Octal code: Event time: Execution time: Operation: Symbol: MCLA 6706 2,3 4.25 µs Read the contents of the status register into AC 0 - 1 1 Status Register-+ AC 0 - 11 6722 2 4.25 µs Set GO bit to execute command in the command register if command is legal. None Clear the AC Octal code: Event time: Execution time: Operation: Symbol: 6702 2 4.25 µs Clear the accumulator. 0-+AC Although any number of tapes may be rewinding simultaneously, data transfer may take place to or from only one transport at any given time. In this context, data transfer includes these functions: read or write data, write EOF (end of file), read/compare, and space. When any of these functions is in process, the tape control is in the not ready condition. A transport is said to be not ready when tape is in motion, when transport power is off, or when it is off line. Data transmission may take place in either parity mode, odd-binary or even-BCD. When reading a record in which the number of characters is not a multiple of the number of characters per word, the final characters come into memory left-justified. Ten bits in the magnetic tape status register retain error and tape status information. Some error types are combinations, such as lateral and longitudinal parity errors (parity checks occur after both reading and writing of data), or have a combined meaning, such as illegal command, to allow for the maximum use of the available bits. The magnetic tape status register reflects the state of the currently selected tape unit. Interrupts may occur only for the selected unit. Therefore, other units which may be rewinding, for example, will not interrupt when done. A special feature of this control is the Write Extended Inter-Record Gap capability. This occurs on a write operation when Command Register bit 5 is set. The effect is to cause a 3-inch inter-record gap to be produced before the record is written. The bit is automatically cleared when the writing begins. This is very useful for creating a gap of blank tape over areas where tape performance is marginal. Magnetic Tape Functions For all functions listed below, upon completion of the data operation (after the end-of-record character passes the read head), the MTF (magnetic tape flag) is set, an interrupt occurs (if enabled), and errors are checked. No Operation - A NO OP instruction defines no function in the command register. A MTGO instruction with NO OP will cause an illegal command error (set EF). 6-47 Space - There are two instructions for spacing records, SPACE FORWARD and SPACE REVERSE. The number of records to be spaced (two's complement) is loaded into the WC. CA does not need to be set. MTF (magnetic tape flag) is set, and an interrupt occurs at WC overflow, EOF (end of file), or EOT (end of tape), whichever occurs first. When issuing a space instruction, both the density and parity bits must be set to the density and parity in which the records were originally written. Load Point or Beginning of Tape (BOT) detection during a backspace terminates the function with the BOT bit set. If a SPACE REVERSE instruction is given when a transport is set at BOT, the instruction is ignored, the illegal command error and BOT bits are set, and an interrupt occurs. Read Data - Records may be read into memory in the forward mode only. Both CA and WC must be set; CA to the initial core address minus one, WC to the two's complement of the number of words to be read. Both density and parity bits must be set. If WC is set to less than the actual record length, only the desired number of words are transferred into memory. If WC is greater than or equal to the actual record length, the entire record is read into memory. In either case, both parity checks are performed, the MTF is set, and an interrupt occurs when the end-of-record mark passes the read head. If either lateral or longitudinal parity errors or bad tape have been detected, or an incorrect record length error occurs (WC not equal to the number of words in the record), the appropriate status bits are set. An interrupt occurs only when the MTF is set. To continue reading without stopping tape motion, MTAF (clear MTF) and MTGO instructions must be executed. If the MTGO command is not given before the shut down delay terminates, the transport will stop. Write Data - Data may be written on magnetic tape in the FORWARD DIRECTION ONLY. For the WRITE DAT A function, the CA and WC registers and density and parity bits must be set. WRITE DATA is controlled by the WC in such a way that, when the WC overflows, data transfer stops, and the EOR (end of record) character and IRG (inter-record gap) are written. The MTF is set after the EOR has passed the read head. To continue writing, a MTGO instruction must be issued before the shut-down delay terminates. If an error occurs, the EF will be set when the MTF is set. Write EDF - The Write EOF instruction transfers a single character ( 17 8 ) record to magnetic tape and follows it with the EOR character; CA and WC are ignored for WRITE EOF. The density bits must be set, and the command register parity bit should be set to even (BCD) parity. If it is set to odd parity, the control will automatically change it to even. When the EOF marker is written, the MTF is set and an interrupt occurs. The tape transport stops, and the EOF status bit is set, confirming the writing of EOF. If odd parity is required after a WRITE EOF, it must be specifically requested through the MTLC instruction. Read/Compare - The READ/COMPARE function compares tape data with core memory data. It can be useful for searching and positioning a magnetic tape to a specific record, such as a label or leader, whose content is known in core memory, or to check a record just written. READ/COMPARE occurs in the forward direction only; CA and WC must be set. If there is a comparison failure, incrementing of the CA ceases, and the READ/COMPARE error bit is set in the status register. Tape motion continues to the end of the record; the MTF is then set, and an interrupt occurs. If there has been a READ/COMPARE error, examination of the CA reveals the word that failed to compare. Rewind - The high speed REWIND instruction does not require setting of the CA or WC. Density and parity settings are also ignored. The REWIND instruction rewinds the tape to loadpoint (BOT) and stops. Another unit may be selected after the instruction is issued and the rewind is in process. MTF is set, and an interrupt occurs (if the unit is selected) when the unit is ready to accept a new instruction. The selected unit's status can be read to determine or verify that REWIND is in progress. 6-48 Continued Operation a. To continue operating the same mode, the MTGO instruction is given before tape motion stops. The order of instructions required for continued operation are as follows: ( 1) MTLC, if the instruction is to be changed. (2) MTAF, clears only MTF and EF flags, since tape control will be in a Not Ready state. (3) MTGO, if MTLC requested an illegal condition; the EF will be set at this time. b. To change modes of operation, either in the same or opposite direction, the MTLC instruction is given to change the mode and a MTGO instruction is given to request the continued operation of the drive. If a change in direction is ordered, the transport will stop, pause, and automatically start up again. c. If the WRITE function is being performed, the only forward change in command that can be given is WRITEEOF. d. If no MTGO instruction is given, the transport will shut down in the inter-record gap. NOTE Flags will not be set when the control or the transport becomes ready, except if the REWIND instruction is present in the command register and the selected drive reaches BOT and is ready for a new instruction. e. If a WRITE (odd parity) instruction is changed to WRITE EOF, the parity is automatically changed to even. NOTE Even parity will remain in the command register unless changed by a new command instruction, MTLC, which clears and loads the entire command register. Status or Error Conditions Twelve bits in the magnetic tape status register indicate status or error conditions. They are set by the control and cleared by the program. 6-49 The magnetic tape status register bits are: Bit Function (When Set) 0 Error flag (EF) Tape rewinding Beginning of tape (BOT) Illegal command Parity error (Lateral or Longitudinal) End of file (EOF) End of tape (EOT) Read/Compare error Record length incorrect WC= 0 (long) WC=:F= 0 (short) Data request late Bad tape Magnetic tape flag (MTF) or job done 2 3 4 5 6 7 8 9 10 11 The register bits are equivalent in position to the AC bits (i.e., SR 0 = AC 0 , etc). MTF (SR 11) - The MTF flag is set under the following conditions: a. Whenever the tape control has completed an operation (after the EOR mark passes the read head). b. When the selected transport becomes ready following a normal REWIND function. These functions will also set the EF if any errors are present. EOF (SR5) - End-of-file (EOF) is sensed and may be encountered for those functions which come under the heading of READ STATUS FUNCTION; i.e., SPACE, READ DATA, or READ/COMPARE and WRITE EOF. When EOF is encountered, the tape control sets EOF = 1. MTF is also set; hence, an interrupt* occurs and the EOF status bit may be checked. EOT (SR6) and BOT (SR2) - End-of-tape (EOT) detection occurs during any forward instruction when the EOT reflective strip is sensed. When EOT is sensed, the EOT bit is set, but the function continues to completion. At this time the MTF is set (and EF is set), and an interrupt occurs. Beginning-of-tape (BOT) deflection status bit occurs only when the beginning-of-tape reflective strip is read on the transport that is selected. When BOT detection occurs, and the unit is in reverse, the function terminates. If a tape unit is at load point when a REVERSE instruction is given, an illegal command error bit is set, causing an EF with BOT set. An interrupt then occurs. *All references to interrupts assume the tape flags have been enabled to the interrupt (command register bit 9 = 1) and the unit is selected. 6-50 Illegal Command Error (SR3) - The illegal command error bit is set under the following conditions: a. A command is issued to the tape control with the control not ready. b. A MTGO instruction is issued to a tape unit which is not ready when the tape control is ready. c. Any instruction which the tape control, although ready, cannot perform; e.g.: ( 1) WRITE with WRITE LOCK condition (2) 9-channel tape and incorrect density (3) BOT and SPACE REVERSE Parity (SR4) - Longitudinal and lateral parity checks will occur in both reading and writing. The parity bit is set for either lateral or longitudinal parity failure. A function is not interrupted, however, until MTF is set. Maintenance panel indicators are available to determine which type of parity error occurred. Read Compare Error (SR 7) - When READ/COMPARE function is underway, SR7 is set to 1 for a READ/COMPARE ERROR (see earlier section on READ/COMPARE for further details). Bad Tape (SR 10) - A BAD TAPE ERROR indicates detection of a bad spot on the tape. Bad tape is defined as three or more consecutively missing characters followed by data, within the period defined by the READ SHUTDOWN DELAY. The error bit is set by the tape control when this occurs. MTF and interrupt do not occur until the end of the record in which the error was detected. Record Length Incorrect (SR8) - During a read or read/compare, this bit is set when the WC overflow differs from the number of words in the record. The EF flag is set. Data Request Late (SR9) - This bit can be set whenever data transmission is in progress. When the DATA FLAG causes a break cycle, the data must be transmitted before a write pulse or a read pulse occurs. If it does not, this error occurs, and data transmission ceases. The EF flag and bit 9 of the status register are set when the MTF is set. Error Flag (SRO) - The ERROR FLAG (EF) is set whenever an error status bit is present at the time that MTF is set. However, when an ILLEGAL COMMAND is given, the EF is set and the MTF is not set. Command Register Contents 'Y PARITY O•EVEN 1•000 ~ WRITE EXTENDED INTERR~CORO GAP (3 OF BLANK TAPE BEFORE RECORD) 'yJ FLAGS O•DISABLE 1 •ENABLE 6-51 Unit Selection Unit 0 Bits 1 2 0 0 0 0 0 0 1 1 2 0 0 0 3 4 5 6 7 1 0 0 0 1 0 Density Selection Bits Density 10 11 200 bpi 556 bpi 800 bpi 800 bpi 9 channel 0 0 0 0 Command Selection Bits Command 6 7 8 NOOP Rewind Read Read/Compare Write Write EOF Space Forward Space Reverse 0 0 0 0 0 0 0 1 0 0 Magnetic Tape Function Summary LEGEND 6-52 CA= Current Address Register= 33 8 WC= Word Count Register= 328 F =Forward R =Reverse DS = Density Setting PR = Parity Setting EN = Enable Interrupt 1 0 1 0 Function Characteristics NO-OP CA: WC: DS: PR: EN: SPACE FORWARD CA: Ignored WC: 2's comp. of number of records to skip DS: Must be set PR: Must be set EN: Must be set Ignored Ignored Ignored Ignored Ignored SP ACE REVERSE Same as SPACE FORWARD READ DATA CA: Core Address - 1 WC: 2's comp. of number of words to be transferred DS: Must be set PR: Must be set EN: Must be set WRITE DATA Same as READ DATA WRITE EOF CA: WC: DS: PR: EN: Ignored Ignored Must be set Must be set Must be set READ/COMPARE Same as READ DATA REWIND CA: WC: DS: PR: EN: Ignored Ignored Ignored Ignored Must be set Status of Error Types Illegal BOT Tape Rewinding Illegal EOF Parity Bad Tape MTF, BOT, EOT Illegal EOF Parity Bad Tape BOT MTF Illegal EOF Parity Bad Tape MTF EOT Data Request Late Record Length Incorrect Illegal EOT Parity MTF Bad Tape Data Request Late Same as WRITE DATA plus EOF Illegal EOF Read/Compare Error Bad Tape MTF EOT Data Late Record Length Incorrect Illegal Tape Rewinding MTF BOT 6-53 6.4.2 Magnetic Tape Transports The following paragraphs describe some of the Magnetic Tape Transports that are available for the PDP- l 2A. These machines are also compatible with the automatic Tape Control Type TC58. 6.4.2.1 Magnetic Tape Transport, Type TU20 (7-Channel) - The Type TU20 is a digital magnetic tape transport designed to be compatible with the Type TC58 Magnetic Tape Control. The transport operates at a speed of 45 inches per second, and has three selectable densities: 200, 556, and 800 bpi. The maximum rate is 36,000 six-bit characters per second. Standard seven-channel IBM-compatible tape format is used. The specifications for the unit are as follows: Format: NRZI. Six data bits plus one parity bit. End and loadpoint sensing compatible with IBM 729 I-VI. Tape: Width 0.5 in., length 2400 ft. ( 1.5 mil.). Reels are 10.5 in. in diameter, IBM-compatible, with file protect (WRITE LOCK) ring. Head: Write-read gap 0.300 in., Dynamic and skew is less than 14 microseconds. Tape Specifications: 45 ips speed. Start time is less than 5 milliseconds. Start distance is 0.080 in. (+0.035, -0.025 in.). Stop time is less than 1.5 milliseconds. Stop distance is 0.045 in. (±0.05 in.). Density: 200, 556, and 800 bpi. Maximum transfer rate is 36 kHz. Transport Mechanism: Pinch roller drive; vacuum column tension. Controls: ON/OFF, ON LINE, OFF LINE, FORWARD, REVERSE, REWIND, LOAD, RESET. Physical Specifications: Width 22-1 /4 in., depth 27-1 /6 in., height 69-1 /8 in., weight 600 lbs. Read (Read/Compare) Shutdown Delay: 3.6 milliseconds. Write Shutdown Delay: Approximately 4.5 milliseconds. 9-Track Operation 9- and 7-track transports may be intermixed on the Type TC58 control. When a transport is selected, it automatically sets the control for proper operation with its number of tracks. Control of 9-track operation is identical to 7-track, except as noted below: Write: A word in memory is written on tape with the following format: fl X BIT 0 2 3 X- THESE BITS ARE IGNORED 6-54 LATERAL PARITY BIT OF CHARACTER I CHARACTER I 4 ---------------------------11 Read - A word is read into memory from tape with the following format: x BIT 0 x Ix I 2 Tl LATERAL PARITY BIT OF CHARACTER I pI 3 CHARACTER I 4-----------------------------11 Read/Compare - A direct comparison of the characters on tape is made with those in memory. The parity bit is ignored, as are bits 0-3 in each memory word. Core Dump Mode - This mode is used only with 9-track transports. It is entered by setting bit 4 of the command register. Core dump mode permits the dumping of complete memory words in the form of two six-bit characters. The format is: CHARACTER 2 CHARACTER I BIT 0--------------------5 6 --------------------11 12-0143 This is accomplished by utilizing only 7 of the 9 tracks on the tape. Tape written in CORE DUMP MODE must be READ (READ/COMPARE) in this same mode. These operations are the same as for a 7-track transport. 6.4.2.2 Magnetic Tape Transport, Type TU20A (9-Channel) - The Type TU20A is a digital magnetic tape transport designed to be compatible with the Type TC58 Magnetic Tape Control. The transport operates at a speed of 45 inches per second, and a density of 800 bpi. The maximum transfer rate is 36,000 eight-bit characters per second. Standard nine-channel IBM-compatible tape format is used. The specifications for the unit are as follows: Format: NRZI. Eight data bits plus one parity bit. End and loadpoint sensing compatible with IBM. Tape: Width 0.5 in., length 2400 ft. (1.5 mil.). Reels are 10.5 in. in diameter, IBM-compatible, with file protect (WRITE LOCK) ring. Heads: Write-read gap of 0.150 in. Dynamic and static skew is less than 14 microseconds. Tape Specifications: 45 ips speed. Rewind time is less than 5 milliseconds. Start distance is 0.080 in. (+0.035, -0.025 in.). Stop time is less than 1.5 milliseconds. Stop distance is 0.045 in. (±0.015 in.). Density: 800 bpi. Maximum transfer rate is 36 kHz. Transport Mechanism: Pinch roller drive; vacuum column tension. Controls: ON/OFF, ON LINE, OFF LINE, FORWARD, REVERSE, REWIND, LOAD, RESET. Physical Specifications: Width 22-1/4 in., depth 27-1/6 in., height 69-1/8 in. Weight 600 lbs. Read (READ/COMPARE) Shutdown Delay: 3.6 milliseconds. Write Shutdown Delay: Approximately 4.5 milliseconds. 6-55 6.4.2.3 Magnetic Tape Transport, Type TU20C General Description The TU20C connects to the PDP-12 via the TCS 8 Automatic Magnetic Tape Control. IOT instructions, issued by the PDP-12, control the operation of the tape transport; these instructions are decoded within the tape control unit to specify the type of tape transport operation. To write on tape, the tape control unit sends a motion-forward instruction and a write-enable instruction, and, for each character to be recorded, a record data pulse. For spacing and reading tape, the tape control unit sends the required motion instruction. Therefore, regardless of the operation, the tape is always being read and the data is always being transmitted to the tape control unit; this information is used for detecting end-of-record to terminate operation. The TU20C operates at 45 inches per second, and has the capability of recording in three densities, 200, 556, and 800 bpi; maximum transfer rate is, therefore, 800 x 45 = 36,000 six-bit characters per second. Standard seven-channel IBM-compatible tape format is used. A nine-channel IBM-compatible version of the TU20C, designated TU20B, is also available; remaining characteristics of the TU20B are essentially the same as those for the TU20C. Operation Either version of the Tape Transport (TU20C, TU20B) may be operated in the local mode from the control panel or in the remote mode from the PDP-12. Local operation is selected by depressing the front panel OFF LINE control; this action causes the FORWARD, RESET, REVERSE, and REWIND switches to become operable. If either the FORWARD, REVERSE, or REWIND control is depressed, the tape moves in the specified direction until RESET is depressed, the beginning of the tape is detected for rewind, or the end of the tape is detected for FORWARD. Activating the front panel ON-LINE control places the Tape Transport in the remote mode, wherein it is controlled by the PDP-12; the Tape Transport must, however, be selected by the TC58 Tape Control. Switches The following switches are located on the control panel: Switch 6-56 Function POWER Applies power to the tape transport. ON LINE Selects programmed (remote) operation by the computer. OFF LINE Selects local operation by the control panel. FWD In local operation, spaces the tape in the forward direction. REV In local operation, spaces the tape in the reverse direction. REWIND In local operation, rewinds the tape at high speed. RESET In local operation, terminates the space forward, space reverse, or rewind operation. LOAD Loads the tape into the tape column. Unit Select Switch Selects the tape transport unit by number. This number is used in the program to select the tape transport. Indicators The following indicators are provided on the control panel: Indicators Meaning When Illuminated SELECT The tape transport is selected by the tape control (or program). READY The tape transport is ready (vacuum on, and settle-down delay complete), no motion. LOAD POINT The tape is at load point. ENDPOINT The tape is at end point (end of tape). WRITE LOCK The write lock-out ring is missing from the tape reel, which prevents the write function. WRITE STATUS The program has enabled the write function in the tape transport. 9 This transport is a 9-track type. 7 This transport is a 7-track type. REWIND The tape transport is in the rewind operation. LOAD The vacuum is on and the tape is loaded into the vacuum columns. REV Reverse operation is specified. RESET No motion (forward, reverse, or rewind) is specified. FWD Forward motion of the tape is specified. LOCAL Local operation by the control panel. REMOTE Remote operation by the computer. POWER Power is applied to the tape transport. 6.4.3 LINCtape Option TC12-F The TCI 2-F option (prewired) in conjunction with the PRTCl 2-F program extends the TCI 2 LINCtape control to read and write DECtapes formatted on the PDP-8, PDP-9, PDP-10, and PDP-15 computers. It will operate on a standard PDP- l 2A system. Tape units 0 through 7 are selectable under program control. Description document DC-12-YIYA-D explains the differences between the LINCtape and DECtape formats and describes the PRTC12-F program. 6-57 Data is transferred between the tapes and the computer on the 1/0 bus. Two status flags enable the program to identify the information on tape. The BLOCK flag is set, indicating that a block mark was encountered on tape and the Block Number (BN) is in the tape accumulator. This number is then read into the PDP-12 AC and is processed to determine if the desired block has been found, or to initiate the necessary adjustments to access the desired block. The WORD flag is set after four lines of data have been assembled and are ready to store in memory when reading from the tape. When writing data on tapes, the flag indicates that a 12-bit word has been written on tape and the control is ready to accept another word from the computer. The system program PRTCI 2-F no. DC-12-YIYA-PB for this option is contained on the standard LAP6-DIAL system tape. NOTE This option does not permit the user to execute tape operations using DEC tape instruction subroutines. Instructions IOT6152 Octal code: Event time: Execution time: Operation: 6152 2 4.25 µs As shown below: AC Bit 5 (1) 5 (1) 6 (1) 7 (1) 9 (1) 10 (1) SWD 0457 STB 0414 TAPE PRESET TAPE PRESET TAPE PRESET 6-58 Function Clear Block FF Set Backward Select unit l Set forward Set motion Select DECtape & AC 11 write Skip on word flag Skip on block flag 0 ~ DECtape write o~ Motion Deselect DECtape 6.5 LINE PRINTERS 6.5.1 Line Printer and Control, Type LP12 The Line Printer and Control Type LPl 2 allows the PDP-12 computer to output data at up to 600 lines per minute (depending upon which printer is used). Either the Mohawk Data Sciences Model 4000 or 5000 series line printers can be used. Model 4000 5000 Lines Per Minute up to 300 up to 600 Columns Per Line 132 132 Total number of characters available: 64 A 6-bit line printer code is loaded into the LPl 2 buffer from AC 6 - 1 1 with the instruction Load Printer Buffer (LLB). The Print (LPR) instruction causes the lineprinter to print the characters in the lineprinter buffer. After the buffer is filled the LPR instruction should be given to print the contents of the buffer. Two status flags indicate the line printer conditions. The Error Flag is set when a printer instruction is given if an error status exists, such as power off, paper supply low, or control circuits not reset. The Done Flag is set by a BUFF AVAILABLE pulse, generated by the line printer, after the following IOT instructions are given: Load Printer Buffer (LLB) 6654, Load Format Register and Print (LPR) 6664 and Clear Printer Buffer (LCB) 6662. The BUFF AVAILABLE pulse indicates that the line printer buffer is ready to receive another character or the lineprinter is ready to print a line. The Done Flag is cleared by the IOT instruction Clear Line Printer Flags (LCF) 6652 or the status of the Done Flag can be checked by the IOT instructions. Skip on Line Printer Done Flag (LSD) 6661. A three-bit format register in the Printer is loaded from AC 9 - 11 during a print command. This register selects one of eight channels of a perforated tape in the printer to control spacing of the paper. The Print Flip-Flop is set when the print instruction is given and, when the Print Flip-Flop and the Done Flag are both set, a program interrupt request is generated, indicating that the printer has finished printing a line. The Print Flip-Flop can be cleared by an IOT instruction Clear Printer Buffer (LCB). AC 8 is loaded into the Space Flip-Flop during a print instruction. If the Space Flip-Flop is set, the paper is advanced according to the selected channel of the format tape in the line printer. If the Space Flip-Flop is clear, the paper advance is inhibited. LSE Skip on Line Printer Error Flag Octal code: Event time: Execution time: Operation: Symbol: LCF 6651 1 4.25 µs The status of the Printer Error Flag is sensed, and, if it is set, the contents of the PC are incremented by one, skipping the next sequential instruction. If Printer Error Flag= 1, then PC+ 1 -+PC Clear Line Printer Flags Octal code: Event time: Execution time: Operation: Symbol: 6652 2 4.25 µs The Line Printer Error and Done Flags are cleared. 0 -+ Line Printer Error Flag 0 -+ Done Flag 6-59 LLB Load Printer Buffer Octal code: Event time: Execution time: Operation: Symbol: LSD Symbol: 6661 4.25 µs The status of the Line Printer Done Flag is sensed, and, if it is set, the contents of the PC are incremented by one, skipping the next sequential instruction. If Line Printer Flag= 1, then PC+ 1 -+PC Clear Printer Buffer Octal code: Event time: Execution time: Operation: Symbol: LPR 4.25 µs The contents of AC6 - 11 are loaded into the Printer Buffer. AC 6 - 11 -+Printer Buffer AC 8 -+ Space Flip Flop 0-+AC Skip on Line Printer Done Flag Octal code: Event time: Execution time: Operation: LCB 6654 4 6662 2 4.25 µs The Printer Buffer is cleared. 0-+ Printer Buffer Load Format Register and Print Character Octal code: Event time: Execution time: Operation: Symbol: 6664 4 4.25 µs The contents of AC9 - 11 are loaded into the line printer format register and the line contained in the printer buffer is printed. Paper is advanced in accordance with the selected channel of the format tape. C (AC 9 - 11 )-+Format Register AC 8 -+ Space Flip-Flop Print Line 0-+AC 6.5.2 Line Printer and Control, Type LPOS The LP08 Line Printer interface allows control of the four models of Data Products Line Printers by the PDP-12 or positive bus PDP-8 family of computers through the use of IOT instructions. The printers are available in 80-column and 132-column printing widths with either a 64 or 96 visible character set. The device select code for the LP08 is 66 8 • The 80-column printer contains a 20-character (24-character in 132 column) buffer and prints 20 characters simultaneously when either the character buffer is full or a fonpat control character (carriage return, paper feed, form feed) instruction is given. A paper feed or form feed command must be given to move the paper at the end of a line or overprinting will result. Characters and commands are given by loading the AC with the appropriate setting derived from the LP08 Character Code Chart (Appendix F-4) and issuing the IOT 6664 (LPC). 6-60 The three format commands in addition to initiating the print cycle are: a. Paper Feed - Advances the paper one line. The perforation between pages is automatic. b. Carriage Return - Returns the print position to the leftmost edge of the paper. c. Form Feed - Advances the paper to a new page. Nonvisible characters are decoded as spaces if they are not control characters. Instructions LSF Skip on Demand Character Flag Octal code: Operation: Symbol: LCF Symbol: Symbol: Symbol: 6664 Load the character into the Print Buffer and print if buffer is full or character was a control function. This instruction does not clear the AC. AC-+ Print Buffer 6665 Sets the device interrupt flip-flop to initiate program interrupt when the demand character flag is set or an error condition exists. 1 -+Int Enable Load Buffer from AC and Clear Flag Octal code: Operation: Symbol: LCP The next instruction is skipped if the error status flag is set. Such errors as out-of-paper, drum gate open, paper jam, etc. will set error status flag. If Error Flag = 1, then PC + l -+ PC Set Program Interrupts Enable Octal code: Operation: LPC 6663 Load Buffer from AC Octal code: Operation: LIN 6662 The line printer character flag is cleared. 0 -+ Character Flag. Skip on Not Ready Octal code: Operation: LLC If printer is ready for the next character, this flag accounts for timing required to store character in buffer, print from buffer, and advance paper. If Character Flag = 1, then PC + 1 -+ PC Clear Character Flag Octal code: Operation: Symbol: LSR 6661 6666 The print buffer is loaded from the AC and the character flag is cleared. Microprogram cbmbination of LCF and LLC. AC-+ Print Buffer, 0-+ Character Flag. Clear Program Interrupt Enable Octal code: Operation: Symbol: 6667 The program interrupt enable is cleared. 0-+ Int Enable 6-61 Print rate 80 column model 64 character 96 character 356 Lines/minute, 460 Lines/minute, 650 Lines/minute, 1110 Lines/minute, columns columns columns columns 1-80 1-60 1-40 1-20 253 330 478 843 Lines/minute, Lines/minute, Lines/minute, Lines/minute, columns columns columns columns 1-80 1-60 1-40 1-20 64 character 245 290 356 460 650 1110 Lines/minute, Lines/minute, Lines/minute, Lines/minute, Lines/minute, Lines/minute, columns columns columns columns columns columns 1-13 2 1-110 1-88 1-66 1-44 1-22 96 character 173 205 253 330 4 78 843 Lines/minute, Lines/minute, Lines/minute, Lines/minute, Lines/minute, Lines/minute, columns columns columns columns columns columns 1-132 1-110 1-88 1-66 1-44 1-22 13 2 column model Format Top-of-form control, single line advance, and perforation step over. Paper Feed One pair of pin-feed tractors for 1/2 inch hole center, edge-punched paper. Adjustable for any paper width from 4 inches to 9-7 /8 inches on the 80 column model; or a maximum width of 14-7/8 inches for the 13 2 column model. Paper slew speed 13 inches per second 6-62 6.6 CARD READERS 6.6.1 Card Reader and Control, Type CR12 The Card Reader and Control Type CRl 2 reads 12-row, 80-column punched cards at a nominal rate of 200 cards per minute by a photoelectric process. Cards are read by column, beginning with column 1. One select instruction starts the card moving past the read station. Once a card is in motion, all 80 columns are read. Column information can be read in one of two program selectable modes, alphanumeric or binary. In the alphanumeric mode, the 12 information bits in one column are automatically decoded and transferred into the least significant half of the AC as a 6-bit Hollerith code. In the binary mode, the 12 bits of a column are transferred directly into the AC so that the top row (12) is transferred into AC 00 and the bottom row (9) is transferred into AC 11 . A punched hole is interpreted as a binary 1, and the absence of a hole is interpreted as a binary 0. Three program flags indicate card reader conditions. The data ready flag sets and a program interrupt is requested when a column of information is ready to be transferred into the AC. A read alphanumeric or read binary instruction must be issued within 1.4 milliseconds after the data ready flag is set to prevent data loss. The card done flag is set and a program interrupt is requested when the card leaves the read station. A new select instruction must be issued immediately after this flag is set to keep the reader operating at maximum speed. Sensing of this flag can eliminate the need for counting columns or, combined with column counting, can provide a check for data loss. The reader-not-ready flag can be sensed by a skip instruction to provide an indication of card reader power off, pick failure, a dark check indication, a stacker failure, hopper empty, stacker full, Sync failure, or light check indication. When the flag is set, the reader cannot be selected and select instructions are ignored. The reader-not-ready flag is not connected to the program interrupt facility, and cannot be cleared under program . control. Manual operation is required to clear the reader-not-ready flag. Instructions for the CR12 are: RCSF Skip on Data Ready Octal code: Event time: Execution time: Operation: Symbol: RCRA Symbol: 6632 2 4.25 µs The 6-bit Hollerith code for the 12 bits of a card column is transferred into AC6 - 11 and t}le data ready flag is cleared. AC 6 - 11 V Hollerith-+ AC 6 - 1 1 0 -+ Data Ready Flag Read Binary Octal code: Event time: Execution time: Operation: Symbol: 4.25 µs The status of the data ready flag is sensed, and if it is set (indicating information for one card column is ready to be read) the contents of the PC are incremented by one skipping the next sequential instruction. If Data Ready Flag = 1, then PC + 1 -+ PC Read Alphanumeric Octal code: Event time: Execution time: Operation: RCRB 6631 6634 3 4.25 µs The 12-bit binary code for a card column is transferred directly into the AC, and the data ready flag is cleared. Information from the card column is transferred into the AC so that card rows 12, 11, and 0 enter AC 0 - 2 and card rows I through 9 enter AC 3 - 11 respectively. 0 -+ Data Ready Flag 6-63 RCSD Skip on Card Done Flag Octal code: Event time: Execution time: Operation: Symbol: RCSE 4.25 µs The status of the card done flag is sensed, and if it is set (indicating that the card has passed the read station) the contents of the PC are incremented, skipping the next instruction. If Card Done Flag = 1, then PC + 1 -+ PC Select Card Reader and Skip if Ready Octal code: Event time: Execution time: Operation: Symbol: RCRD 6671 1 6672 2 4.25 µs The status of the card reader flag is sensed and if the reader is ready, the PC is incremented skipping the next sequential instruction, a card is started toward the read station from the input hopper, and the card done flag is cleared. If Reader Ready Flag = I, then PC + I -+ PC 0 -+ Card Done Flag Clear Card Done Flag Octal code: Event time: Execution time: Operation: Symbol: 6674 3 4.25 µs The card done flag is cleared. This instruction allows a program to stop reading at any point in the card deck. 0 -+ Card Done Flag A logical instruction sequence to read cards is: START, RCSE JMP NOT RDY /START CARD MOTION AND SKIP IF READY /JUMP TO SUBROUTINE THAT TYPES OUT /"CARD READER MANUAL INTERVENTION /REQUIRED" OR HALTS NEXT, RCSF JMP DONE RCRAor RCRB DCA I STR /DATA READY? /NO. CHECK FOR END OF CARD /YES. READ ONE CHARACTER OR ONE /COLUMN AND CLEAR DAT A READY FLAG /STORE DATA DONE, RCSD JMP NEXT JMPOUT /END OF CARD? /NO, READ NEXT COLUMN /YES, JUMP TO SUBROUTINE THAT CHECKS /CARD COUNT OR REPEATS AT START FOR /NEXT CARD The CRl 2 does not perform validity checking, although a programmed validity check can be made by reading each card column in both the alphanumeric and binary mode (within the 1.4 millisecond time limitation), then performing a comparison check. The following discussion and controls and indicators deal with the General Design Industries (GDI) Model 100 card reader. Other card readers can be used and will have similar controls and indicators. 6-64 Before commencing a card reading program, load the input hopper with cards and press Motor Start and Read Start pushbuttons. The functions of the manual controls and indicators are as follows (as they appear from left to right): Control or Indicator Function A - POWER switch On/Off toggle switch. Applies power to all circuits except drive motor. B - MOTOR START Momentary action pushbutton, with separate indicator. Applies power to main drive motor. Motor start is also used as a reset to clear error indicators, and therefore will not operate if there is an unremedied condition such as: 1. 2. 3. 4. Input hopper is empty. Output hopper is full. All photo cells are not illuminated. Internal power supply is not operational. C - READ START Momentary action pushbutton, with separate indicator. Causes ready line to go high, enabling card reading under control of the external read instructions. If read co mm and is open or high, card reading begins immediately at full rated speed. D-READ STOP Momentary action pushbutton with indicator. Stops card reading if depressed without stopping drive motor. However, READ STOP light can indicate a stopped motor or a ready line low condition. E - INDICATORS Several detection circuits are incorporated in the card reader. Whenever any red indicator lights, the drive motor is stopped after completion of the current card cycle. 1. PICK FAIL Indicator Lights when a card fails to enter the read station after two successive pick attempts. 2. DARK CHECK Indicator After the card enters the read station, a check is made at the hypothetical 0th and 81 st hole positions to be sure all photocells are dark. If not, the DARK CHECK indicator lights and data outputs are immediately inhibited. 3. STACKER FAIL Indicator When three cards have passed the read station and none have been stacked, a STACK FAIL is indicated. Prevents more than three cards from being in the track at once. 4. HOPPER EMPTY Indicator Indicates input hopper is empty. S. STACKER FULL Indicator When approximately 400 cards are in the stacker hopper, indicator light lights. 6-65 6. SYNC FAIL Indicator SYNC FAIL is indicated if the sync signal is lost. Internal timing signals are derived from an oscillator which is synced to the track speed. 7. LIGHT CHECK INDICATOR The photocells must always be illuminated except during the time a card is being read. The LIGHT CHECK detector is inhibited each time a card enters the read station until position (count of) 84 is reached. If a card fails to leave the read station by this time, a LIGHT CHECK is indicated. 6.6.2 Optical Mark Card Reader Type CM 12 The GDI Model 100-MS is an optical-mark card reader that reads ( 12-row Hollerith) reflective data cards of various format designs at a rate of up to 200 cards per minute by a photoelectric process. Cards are read column by column, beginning with column 1. A single select instruction will cause the reader to feed and read a card. Once a card is in motion, all columns are read. Column information is read in one of two program-selectable modes, alphanumeric or binary. In the alphanumeric mode, the 12 information bits in one column are automatically decoded and transferred into the least significant half of the AC as a 6-bit Hollerith code. In binary mode, all 12 bits of a column are transferred directly into the AC so that the top row (12) is transferred into AC 00 and the bottom row (9) is transferred into AC 11 • A punched hole or a nonreflective spot (either nonreflective ink or No. 2 pencil) is interpreted as a binary 1, and the absence of a hole or reflective spot is interpreted as a binary 0. Instructions The instruction set associated with the optical mark reader is identical to that of the CRl 2 in Paragraph 6.6. l. Characteristics Size: The complete unit is 14 in. wide, 18 in. deep, and 18 in. high. The card deck is tilted back at a 45-degree angle. Weight: Complete unit weighs 47 lbs. Card Rate: 200 per minute. Input Power: 115 VAC ± 10 VAC, 60 ±5 Hz single phase, at 300 VA maximum. Card Specification: The card reader is designed to read 7-3/8 in. x 3-1/4 in. optical mark cards conforming to the material and size requirements of EIA Standard RS-292 Media I. Format and printing requirements are specified in the DEC Mark Sense Card Specification. Card Capacity: Both input hopper and output stacker hold 450 cards. Cards may be added or removed during reader operation. Environment: Operating: Storage: 6-66 32° to l 20°F ambient 15% to 80% relative humidity 30° to l 50°F ambient 0% to 100% relative humidity Controls and Indicators Power Switch: An alternate action rocker-type switch used to apply AC power to the Card Reader. Start Switch: A momentary pushbutton switch used to condition the unit to read cards. When it is depressed, the drive motor will start, and any error indicators will be reset if the error has been cleared. When it is released and the motor has reached operating speed, the reader may accept a "read command' and process cards. Stop Switch: A momentary pushbutton switch used to stop the reader. When it is depressed, the motor will stop; if it is depressed during a time a card is in process, the card cycle will be completed before the motor stops. Power: A green indicator to verify AC power on; mounted next to the POWER switch. On Line: A green indicator to verify that the START switch has been depressed and the unit is ready to operate. Light will remain on until the STOP switch is depressed or an error condition is sensed; mounted next to START switch. Cards: A red indicator to identify an input hopper empty or an output stacker full condition. Feed Error: A red indicator to identify when a card has not been fed from the input hopper to the read station at the end of a feed cycle. Stacker Error: A red indicator to identify when a card has not been properly delivered to the output stacker. Motion Error: A red indicator to indicate a card jam in the read station. L.D. Error: A red indicator to identify when a Light or Dark Check of the read station was not met. 6-67 6.7 INCREMENTAL PLOTTERS 6.7.1 Incremental Plotter and Control, Type XY12 Calcomp (California Computer Products) Models 563 and 565 available in three step-size models and four models of the Complot (Houston Instruments) digital plotters can be operated from a Digital Equipment Corporation Type XY12 Incremental Plotter Control. The characteristics of the recorders are summarized: Name Paper Width (inches) Speed (step/minute) 563 30 12,000 .0 I-in. .005-in . . I-mm 565 12 18,000 .0 I-in. .005-in . . 1-mm 12 12 12 12 18,000 18,000 18,000 18,000 .01-in. .005-in. .25-mm .1-mm Model Calcomp DP-1-1 DP-1-5 DP-1-M2 DP-I-Ml Comp lot Step Size The principles of operation are basically the same for each of the recorders. Bidirectional rotary step motors are employed for both the X and Y axes. Recording is produced by movement of a pen relative to the surface of the graph paper, with each instruction causing an incremental step. X-axis deflection is produced by motion of the drum; Y-axis deflection, by motion of the pen carriage. Instructions are used to raise and lower the pen from the surface of the paper. Each incremental step can be in any one of eight directions through appropriate combinations of the X and Y axis instructions. All recording (discrete points, continuous curves, or symbols) is accomplished by the incremental stepping action of the paper drum and pen carriage. Front panel controls permit single-step or continuous-step manual operation of the drum and carriage, and manual control of the pen solenoid. The recorder and control are connected to the computer program interrupt and instruction skip facility. Instructions for the recorder and control are: PLSF Skip on Plotter Flag Octal code: Event time: Execution time: Operation: 4.25 µs If the Plotter Flag is set, the contents of the PC are incremented by one so that the next Symbol: sequential instruction is skipped. If Plotter Flag = l, then PC + 1 -+ PC PLCF Clear Plotter Flag Octal code: Event time: Execution time: Operation: Symbol: 6-68 6501 6502 2 4.25 µs Clear the AC and Plotter Flag 0-+AC 0 -+ Plotter Flag PLPU Pen Up Octal code: Event time: Execution time: Operation: Symbol: PLPR Pen Right Octal code: Event time: Execution time: Operation: Symbol: PLDU 6511 4.25 µs Move the plotter pen to the right in either the raised or lowered position. None Drum Up Octal code: Event time: Execution time: Operation: Symbol: PLDD 6512 2 4.25 µs Move the plotter paper drum upward. This instruction can be combined with the PLPR and PLPD commands. None Drum Down Octal code: Event time: Execution time: Operation: Symbol: PLPL 6504 3 4.25 µs Raise the plotter pen from the paper surface. None 6514 3 4.25 µs Move the plotter paper drum downward. None Pen Left Octal code: Event time: Execution time: Operation: Symbol: PLUD 4.25 µs Move the plotter pen to the left in either the raised or lowered position. None Drum Up Octal code: Event time: Execution time: Operation: Symbol: 6521 6522 2 4.25 µs Move the plotter paper drum upward. This instruction is similar to the 6512 instruction except that it can be combined with the PLPL or PLPD instructions. None 6-69 PLPD Pen Down Octal code: Event time: Execution time: Operation: Symbol: 6524 3 4.25 µs Lower plotter pen to the surface of the paper. None Program sequence assumes that the end location is known at the start of a routine since there is no means of specifying an absolute pen location in an incremental plotter. Pen location can be preset by the manual controls on the recorder. During the subroutine, the PDP-12 can track the location of the pen on the paper by counting the instructions that increment position of the pen and the drum. 6-70 6.8 PAPER TAPE 6.8. l High-Speed Paper-Tape Punch and Reader, Type PC12 The High-Speed Paper-Tape Punch and Reader Type PCl 2 provides the user with a faster means of inputting or outputting information from paper tape to the PDP-12 than that provided by the standard Teletype tape reader/punch. The PCl 2 is functionally a PPl 2, High Speed Paper Tape Punch, and a PRl 2, High Speed Paper Tape Reader, configured mechanically in the same unit. The operating characteristics are discussed in the following paragraphs. 6.8.2 High-Speed Paper-Tape Punch, Type PP12 The High-Speed Paper-Tape Punch option Type PPl 2 consists of a PC05-P paper-tape punch that perforates 8-hole fanfold paper-tape at a rate of 50 characters per second. Information to be punched in tape is loaded in an 8-bit punch buffer (PB) from AC 4 - 1 1 • The punch flag is set at the completion of the punching action, signaling that new information may be transferred into the punch buffer and punching may be initiated. The control circuitry for this device is located in the BAl 2 Peripheral Expander. The punch flag is as described for the Teletype unit. The punch instructions are: PSF Skip on Punch Flag Octal code: Event time: Execution time: Operation: Symbol: PCF Symbol: 6022 2 4.25 µs The punch flag and the punch buffer are both cleared in preparation for receiving a new character from the computer. 0 --+ Punch Flag, PB Load Punch Buffer and Punch Character Octal code: Event time: Execution time: Operation: Symbol: PLS 4.25 µs The punch flag is sensed, and, if it is set, the contents of the PC are incremented by one, skipping the next sequential instruction. If Punch Flag = 1, the PC + 1 --+ PC Clear Punch Flag Octal code: Event time: Execution time: Operation: PPC 6021 6024 3 4.25 µs An 8-bit character is transferred from AC 4 • 11 into the punch buffer, and then the character is punched. This instruction does not clear the punch flag or the punch buffer. AC 4 • 11 --+PB--+ PB Load Punch Buffer Sequence Octal code: Event time: Execution time: Operation: Symbol: 6026 2,3 4.25 µs The punch flag and punch buffer are both cleared, the contents AC4 • 1 1 are transferred into the punch buffer, the character in the PB is punched in tape, and the punch flag is set when the operation is completed. Combines PCF and PPC. 0 --+ Punch Flag, PB AC 4 • 1 1 --+ PB I --+Punch Flag when done 6-71 A program sequence loop to punch characters when the punch buffer is "free" can be written as follows: FREE, PSF JMP FREE PLS JMP FREE /SKIP WHEN FREE /LOAD PB FROM AC AND PUNCH CHARACTER 6.8.3 High-Speed Paper-Tape Reader, Type PR12 The High-Speed Paper-Tape Reader (PC05-R) option Type PR 12 senses data in a 8-hole perforated-paper tape (unoiled) photoelectrically at 300 characters per second. The reader control requests reader movement, transfers data from the reader into the reader buffer (RB), and signals the computer when incoming data is present. Reader tape movement is started by clearing the Reader Flag. Data is assembled into the Reader Buffer from the perforated tape. The Reader Buffer is transferred into AC 4 -11 under program control. The Reader Flag is connected to the program interrupt and instruction skip facilities, and is cleared by IOT pulses. Control circuitry for this device is located in the BA12 Peripheral Expander. Computer instructions for the reader are: RSF Skip on Reader Flag Octal code: Event time: Execution time: Operation: Symbol: RRB 6011 1 4.25 µs The status of the Reader Flag is sensed, and, if it is set, the contents of the PC are incremented by one, skipping the next sequential instruction. If Reader Flag = I , then PC + 1 ~ PC Read Reader Buffer Octal code: Event time: Execution time: Operation: Symbol: 6012 2 4.25 µs The contents of the reader buffer are transferred into AC 4 - 11 and the Reader Flag is cleared. This instruction does not clear the AC. RB V AC 4 - 11 ~ AC 4 - 11 0 ~ Reader Flag RFC Reader Fetch Character Octal code: Event time: Execution time: Operation: Symbol: 6014 3 4.25 µs The Reader Flag and the reader buffer are both cleared. A character is loaded into the reader buffer from tape, and the Reader Flag is set when this operation is completed. 0 ~ Reader Flag, RB Tape Data~ RB 1 ~ Reader Flag when done. A program sequence loop to read characters from perforated tape can be written as follows: LOOK, 6-72 RFC RSF JMP LOOK CLA RRB JMP LOOK /FETCH CHARACTER FROM TAPE /SKIP WHEN RB FULL /LOAD AC FROM RB 6.9 DATA BUFFERS 6.9.1 Data Buffer Type DB12-P, N The DB 12 option is an input/output transfer register, consisting of a 12-bit input bus driver and a 12-bit output buffer register. The basic logic for this option is contained on an M735 module, which is described in the Logic Handbook ( 1970). Three DB 12 options are prewired in the BAI 2 Peripheral Expander. The device select gating and data lines provide the capability for transferring data into or out of the PDP-12 accumulator. The user selects a device code by inserting jumpers in the M921 Device Code Select Jumper module located in row A, slot 19, of the BAI 2 Peripheral Expander. Two I/O cables (Flexprint®) terminating in M903 connector modules are provided to connect the DB 12 to the external I/O device. The output register is buffered to provide either positive (0, +3V) or negative (0, -3V) logic levels. The option designation is DB12-P (positive) or DB12-N (negative). ® Flexprint is a Registered Trademark of Sanders Associates Inc. 6-73 6.10 POWER FAIL/RESTART 6.10.1 Power Failure Option, Type KP12 General The KP 12 Power Failure Option protects an operating program upon failure or interruption of the computer's primary power source. In the event of a power abnormality, a program interrupt is initiated by the KPl 2 and enables continued operation of the central processor for 1 millisecond. During this interval, the interrupt routine identifies the power low condition as the initiator of the interrupt. The interrupt routine then stores the contents of active registers (AC, L, MQ, etc) and the program counter in known core memory locations. Upon restoration of power, the power low flag is cleared and a routine in the 8 mode beginning at address 0000 8 starts automatically, restoring the contents of the active registers and the program counter, and then continues the interrupted program. Operation A manual RESTART switch enables or disables the automatic restart operation upon restoration of primary power. When it is ON (down), the program counter is cleared and a signal which simulates the console START key (RCL ST ART PC) is produced 200 milliseconds after power conditions become satisfactory. Operation is restarted (always in the 8 mode) by executing the instruction contained in address 0000 8 ; this instruction is a JMP to the starting address of a subroutine which restores the contents of the active registers and the program counter to the conditions that existed prior to the power low interrupt. The 200-millisecond delay assures that slow mechanical devices, such as Teletype equipment, have completed any previous operation before the program is resumed. When the RESTART switch is OFF (up), the power low flag is cleared upon the return of normal power conditions, but the program must be manually restarted, possibly after resetting peripheral equipment. Programming SPL Skip on Power Low Octal code: Event time: Execution time: Operation: Symbol: 6102 2 4.25 µs The condition of the power low flag is sampled; if set (indicating a power failure has occurred), the contents of the PC are incremented by one, skipping the next sequential instruction. If Power Low Flag = 1, then PC + 1 ~ PC Figures 6-9 and 6-10 illustrate the Automatic Restart Program Events and Typical Power Failure Program Service Routine, respectively. 6-74 PROGRAM IN OPERATION NO YES ENTER DEVICE "SEARCH" SUBROUTINE POWER FAIL SUBROUTINE NOT ENTERED THE REGISTER CONTENTS ARE NOT SAVED. PROGRAM. HAS TO BE MANUALLY RESTARTED FROM BEGINNING. YES NO STOP THE NEXT SEQUENTIAL INSTRUCTION AND ENTER KP12 SERVICE ROUTINE THE PROGRAM CONTINUES FLAG CHECKING. NOTE WITH REAL TIME APPLICATIONS, THE TIME REQUIRED FOR CHECKING REDUCES THE TIME FOR THE REAL TIME SERVICE SUBROUTINE POSITION KP 12 INQUIRY NEAR THE BEGINNING. DCA AC RAR DCA LINK MQA DCAMQ 6~~ ~gooe TAD RESTRT X DCA 00009 HLT /INTERRUPT WAS CAUSED BY POWER LOSS FLAG /SAVE AC /GET LINK /SAVE LINK /GET MQ /SAVE MO /GET PC /SAVE PC /GET RESTART JUMP INSTRUCTION /DEPOSIT RESTART INSTRUCTION IN 00009 12-0196 Figure 6-9. Automatic Restart Program Events POWER RESTORED NO YES PROGRAM MUST BE RESTARTED MANUALLY. UPON REST ART, THE INSTRUCTION IN LOCATION 00009 IS PERFORMED LOCATION Of JMP X LOCATION X CONTAINS THE BEGINNING OF THE RESTART PROGRAM, WHICH RESTORES THE CONTENTS OF LINK,AC,PC AND ANY OTHER INFORMATION STORED BY PWR FAIL SERVICE SUBROUTINE.CONTINUATION OF THE PROGRAM AUTOMATICALLY OCCURS. CONTINUE MAIN PROGRAM 12-0039 Figure 6-10. Typical Power Failure Program Service Routine 6-75 6.11 ANALOG-TO-DIGITAL 6.11.1 General Purpose Multiplexed Analog-to-Digital Converter System, Type AF01-A The Type AFO 1-A General-Purpose Multiplexed Analog-to-Digital Converter combines a versatile, multipurpose converter with a multiplexer to provide a fast, automatic, multichannel scanning and conversion capability. It is intended for use in systems that sample and process analog data from sensors or other external signal sources at high rates of speed. The AFOl-A is used when greater accuracy than that provided by the standard AD12 A-D converter is needed. The Type AFO 1-A option is used with the PDP-12 to multiplex up to 64 analog signals and to convert the signals to binary numbers. Analog data on each of 64 channels can be accepted and converted into 12-bit digital numbers 420 times per second.* Switching point accuracy in this instance is 99.975 percent, with an additional quantization error of half the analog value of the least significant bit (LSB). A/D Converter Specifications The Type AFO 1-A has a successive approximation converter that measures a 0 to -10 volt analog input signal and provides a binary output indication of the amplitude of the input signal. The characteristics of the A/D converter are as follows: Accuracy and Conversion Times: See Table 6-6 (includes all linearity and temperature errors) Converter Recovery Time: Zero. Input and Input Impedance: 0 to -1 OV at 10 megohms standard. Input scaling may be specified using the amplifier or sample and hold options (see Table 6-5). Input Loading: ±1 µA and 125 pf for 0 to -IOV input signal. Output: Binary number of 6 to 12 bits, with negative numbers represented in two's complement notation. A OV input gives a 4000 8 ; a -5V input a 0000 8 and a -1 OV (minus 1 LSB) input gives 3777 8 number. Provision is made for using the Type A400 Sample and Hold Amplifier (AH02 option) between the multiplexer output and A/D converter input to reduce the effective aperture to less than 150 ns. The Type A400 may also be used to scale the signal input to accept ± 1OV, or 0 to + 1OV. The Type A200 amplifier (AH03 option) may be substituted for the Type A400 to accomplish the same signal scaling without reducing the effective aperture. Both the AH02 and AH03 options may be used to obtain high input impedance and small aperture. (See Table 6-4.) Multiplexer Specifications The multiplexer can include from 1 to 16 Type A 121 Switch Modules. Each module contains four single-pole, high-speed, insulated gate FET switches with appropriate gating. The Type Al 21 Switches are arranged as a 64-channel group of series-switching single-pole switches with a separate continuous ground wire for each signal input. The switched signal input wire and the continuous ground for each channel are run as twisted pairs to the input connectors mounted on the rear panel. The continuous grounds for all channels are terminated at the high quality ground of the AFOl-A System. Specifications (measured at input connector) are as follows: *Conversion rate 6-76 = [(35 +2)(10-6)(64)] -1 =420cycles/sec. = [(9 + 2) (10- 6) (64)] - 1 = 1420 cycles/sec. Input Operating Signal Voltages: +lOV to -IOV Current: 1 mA On Resistance 500 ohm (max) Voltage Offset lµV "Off Leakage'' 10 nA (max) Capacitance 10 pf (max) Speed 10% Input to within 1 LSB of output 2 µs Operate Time The time required to switch from one channel to another is 2 µ.s to within 1 LSB of the final voltage. This time is preset within the control and starts when a set or index command is received. Table 6-5. Input Signal Scaling Configuration Gain Standard Input Impedance (ohms) Input Signal Input Output Option Designation 0 -5 -10 10 meg. 10 meg. 10 meg. 4000 8 0000 8 3777 8 STD Sample & Hold -1 -1 -1 +5 0 -5 lOK lOK lOK 3777g 0000 8 4000 8 AH02 Sample & Hold -1/2 -1/2 -1/2 +IO 0 -10 lOK IOK lOK 3777 8 0000 8 4000 8 AH02 Amplifier +l +l +l +5 0 -5 >IOO meg. >100 meg. >100 meg. 4000 8 0000 8 3777 8 AH03 +1/2 +1/2 +1/2 +10 0 -10 >IOO meg. >100 meg. >100 meg. 4000 8 0000 8 3777 8 AH03 -1 or -1/2 +5 +10 0 or 0 -5 -10 >IOO meg. >IOO meg. >100 meg. 3777 8 0000 8 4000 8 AH03 & AH02 Amplifier Amplifier and Sample & Hold NOTE Unipolar signals (0 to +5, or 0to+1 Ov) may also be specified with either the AH03 or AH02 pption. 6-77 System Operation The Type AFO 1 System may be operated in either the random or sequential address modes. In the random address mode, the control routes the analog signal from any selected channel to the A/D converter input. In the sequential address mode, the multiplexer control advances its channel address by one each time an index instruction is received. After indexing through the maximum number of channels implemented, the address is returned to 0. The multiplexer switch settling time is preset within the control to initiate the conversion process automatically after a channel has been selected in either the random or sequential address mode. A separate A/D Convert I/O Transfer instruction may also initiate one or more conversions on a currently selected channel. A/D conversion times are increased by 2 microseconds when multiplexer channels are switched to allow for settling time of the analog signal at the multiplexer output. Conversion times are increased an additional 3 microseconds when AH03 is used. These items are added to the conversion times shown in Table 6-6 under selected channel conversion time, which is the only time required for each successive conversion on a selected channel. When the Type AH02 Sample and Hold option is required, the multiplexer switch settling time and the sample and hold acquisition time are overlapped. The total conversion and switching time is increased by 10 microseconds. (See A400 specifications.) A/D CONVERTER/MDLTIPLEXER CONTROLS Designation Function WORD LENGTH: Rotary switch selects digital word length or conversion accuracy. Refer to Table 6-6 for corresponding conversion times. POWER ON/OFF: Applies 117 Vac power to internal power supplies. CLR: Clears multiplexer channel-address registers; i.e., selects analog channel O for conversion. INDEX: Advances multiplexer channel-address register by one each time it is depressed, enabling manual addressing of channels (up to 64) in sequential mode. Returns address to zero when maximum value is reached. ADC: Starts conversion of the analog voltage on the selected channel to a binary number when depressed. A/D CONVERTER: Indicates binary contents of A/D converter register. MULTIPLEXER: Indicates binary contents of multiplexer channel-address register. POWER: Indicates ON/OFF status. Programming Programmed control of the converter/multiplexer by the PDP-12 is accomplished with the IOT instructions listed below. PDP-12 selects the converter/multiplexer with two device selection codes, 53 8 and 548 , depending upon whether conversion or multiplexing function is being selected. The converter/multiplexer interprets the device selection code to enable execution of the IOP command pulse generated by the IOT instruction. 6-78 Table 6-6. System Conversion Characteristics Word Length (No. of Bits) 6 7 8 9 10 11 12 Max Switching Point Error* Selected Channel (A/D) Random or Sequential (MPX & A/D) AH03 MPX A/D AH02 MPX A/D AH02 AH03 MPX &A/D Conversion Time (,us)** Conversion Time (µs)** Conversion Time {µs)** Conversion Time (µs)** Conversion Time (µs)** 9.0 10.5 12.0 13.5 18.0 25.0 35.0 11.0 (9.5) 12.5 (11.0) 14.0 (12.5) 15.5 {14.0) 20.0 {18.5) 27.0 37.0 14.0 (11.0) 15.5 (12.5) 17.0 (14.0) 18.5 {15.5) 23.0 (20.0) 30.0 40.0 19.0 (14.0) 20.5 (15.5) 22.0 (17.0) 23.5 (18.5) 28.0 (23.0) 35.0 45.0 21.0 22.5 24.0 25.5 30.0 37.0 47.0 ±1.6% ±0.8% ±0.4% ±0.2% ±0.1% ±0.05% ±0.025% (18.0) (19.5) (21.0) (22.5) (27.0) * ± 1/2 LSB for quantizing error. **If system is to operate at less than 10 bits continuously, conversion times may be reduced to times shown in parentheses. ADSF Skip on A-D Flag Octal code: Event time: Execution time: Operation: Symbol: 6531 4.25 µs The A-D converter flag is sensed, and if it is set (indicating that the conversion is complete) the contents of the PC are incremented by one, skipping the next instruction. If A-D Flag= 1, then PC+ 1-+ PC ADCV Convert Analog Voltage to DigUal Value Octal code: Event time: Execution time: Operation: Symbol: ADRB Read A-D Converter Buffer Octal code: Event time: Execution time: Operation: Symbol: 6532 2 This time is a function of the accuracy and word length switch setting as listed in Table 6-6. The A-D converter flag is cleared, the analog input voltage is converted to a digital value, and then the A-D converter flag is set. The number of binary bits in the digital-value word and the accuracy of the word are determined by the preset switch position. 0-+ A-D Flag at start of conversion, then 1-+ A-D Flag when conversion is done. 6534 3 4.25 µ.s The converted number contained in the converter buffer (ADCB) is transferred into the AC left justified; unused bits of the AC are left in a clear state, and the A-D converter flag is cleared. This instruction must be preceded by a CLA instruction. ADCB-+AC 0-+ A-D Converter Flag 6-79 ADCC Clear Multiplexer Channel Octal code: Event time: Execution time: Operation: 6541 1 4.25 µs The channel address register (CAR) of the multiplexer is cleared in preparation for setting of a new channel. Symbol: o~CAR ADSC Set Multiplexer Channel Octal code: Event time: Execution time: Operation: 6542 2 4.25 µs The channel address register of the multiplexer is set to the channel specified by AC6 - 11 . A maximum of 64 single-ended input channels can be used. ADIC Increment Multiplexer Channel Octal code: Event time: Execution time: Operation: Symbol: 6544 3 4.25 µs The contents of the channel address register of the multiplexer are incremented by one. If the maximum address is contained in the register when this instruction is given, the minimum address (00) is selected. CAR+ 1 ~cAR The converter/multiplexer may be operated by the program in either the random or sequential addressing mode. In the random addressing mode, the analog channel is selected arbitrarily by the program for digitizing and the resultant binary word is read into the accumulator. A sample program for the random addressing mode is as follows: TADADDR ADSC ADCV CLA ADSF JMP.-1 ADRB /YES-GET CHANNEL ADDRESS /AND SEND TO MULTIPLEXER /CONVERT A TOD /CLEAR AC /SKIP ON A/D DONE FLAG /WAIT FOR FLAG /AND READ INTO AC In the sequential address mode, the program advances the multiplexer channel-address register to the next channel each time an analog value is converted and read into the accumulator. Should the converter/multiplexer be operated in the interrupt mode, the computer will be signaled each time that a binary word is ready, enabling the system to use processor time more efficiently. 6-80 Amplifier, Sample and Hold Options for AFOl-A The AH03 consists of a DEC amplifier (part #1505379-10) mounted on an A990 Amplifier Board with appropriate scaling networks and gain trim and balance potentiometers. 2 x 10 6 (@ 10 ma) ±1 lV Open loop gain Rated output voltage Frequency response Unity Gain, small signal Full output voltage Slewing rate Overload recovery lOMHz 1 MHz lOOV/µs 50 µs Input voltage offset Avg vs temp Vs supply voltage Vs time Adjustable to 0 20 µv/°C 15 µv/% 10 µv/day Input current Avg vs temp Vs supply voltage 50 pAmax doubles every l 0°C 10 pA/% Input impedance (ohms) Between inputs Common mode 10 1 0 (5 pF shunt c) 10 1 0 (5 pF shunt c) Input Voltage Max common mode Common mode rejection ±l5V ±lOV 50,000V Power Voltage Current at rated load ±15 to 16V 40ma A400 (standard gain options) Acquisition time to 0.01 % (fullscale step) Aperture time Hold inaccuracy (droop) Temperature coefficient Gain (negative) Input range (volts) Output Impedance <12 µs <150 ns 0, then clear AC. Table B-4. 8 Mode Extended Arithmetic Element Microinstructions Mnemonic Symbol Octal Code Sequence MUY 7405 3 DVI 7407 3 NMI 7411 3 Operation Multiply. The number held in the MQ is multiplied by the number held in core memory location PC + 1 (or the next successive core memory location after the MUY Command). At the conclusion of this instruction the most significant 12 bits of the product are contained in the AC and the least significant 12 bits of the product are contained in the MQ. YxMQ~AC,MQ B-4 Divide. The 24-bit dividend held in the AC (most significant 12 bits) and the MQ (least significant 12 bits) is divided by the number held in core memory location PC + 1 (or the next successive core memory location following the DVI instruction). At the conclusion of this instruction the quotient is held in the MQ, the remainder is in the AC, and the L contains a 0. If the L contains a 1, divide overflow occured so the operation was concluded after the first cycle of the division. AC,MQ ..;- Y ~ MQ. Normalize. This instruction is used as part of the conversion of a binary number to a fraction and its exponent for use in floating-point arithmetic. The combined contents of the AC and the MQ are shifted left by this one instruction until the content of AC 0 is not equal to the content of AC 1 , thus forming the fraction. Zeros are shifted into vacated MQ 11 positions for each shift. Table B-4. 8 Mode Extended Arithmetic Element Microinstructions (cont) Mnemonic Symbol Octal Code Sequence SHL 7413 3 ASR 7415 3 LSR 7417 3 Operation At the conclusion of this operation, the step counter contains a number equal to the number of shifts performed. The content of Lis lost. ACj-+ ACr 1 AC 0 -+ L MQo-+ AC11 MQj-+ MQj- 1 0-+ MQ 11 until AC0 =I= AC 1 Shift left. This instruction shifts the combined contents of the AC and MQ to the left one position more than the number of positions indicated by the contents of the core memory at address PC + 1 (or the next successive core memory location following the SHL instruction). During the shifting, zeros are shifted into vacated MQ 11 positions. Shift Y + 1 positions as follows: ACj-+ ACj- 1 AC 0 -+ L MQ 0 -+ AC 11 MQj-+ MQj- 1 0-+ MQ11 Arithmetic shift right. The combined contents of the AC and the MQ are shifted right one position more than the number contained in memory location PC + 1 (or the next successive core memory location following the ASR instruction). The sign bit, contained in AC 0 , enters vacated positions, the sign bit is preserved, information shifted out of MQ 11 is lost, and the L is undisturbed during this operation. Shift Y + 1 positions as follows: AC 0 -+ AC 0 ACj-+ ACj + 1 AC 11 -+ MQo MQj-+ MQj + 1 Logical shift right. The combined contents of the AC and MQ are shifted right one position more than the number contained in memory location PC+ 1 (or the next successive core memory location following the LSR instruction). This instruction is similar to the ASR instruction except that zeros enter vacated positions instead of the sign bit. Information shifted out of MQ 11 is lost and the L is undisturbed during this operation. Shift Y + 1 positions as follows: 0-+ AC0 ACj-+ ACj + 1 AC 11 -+ MQ 0 MQj-+ MQj + 1 B-5 Table B-4. 8 Mode Extended Arithmetic Element Microinstructions (cont) Mnemonic Symbol Octal Code Sequence MQL 7421 2 SCA 7441 2 SCL 7403 3 MQA 7501 2 CLA 7601 CAM 7621 B-6 1,2 Operation Load multiplier quotient. This instruction clears the MQ, loads the contents of the AC into the MQ, then clears the AC. 0--+ MQ AC-+ MQ 0--+ AC Step counter load into accumulator. The contents of the step counter are transferred into the AC. The AC should be cleared prior to issuing this instruction or the CLA instruction may be combined with the SCA to clear the AC, then effect the transfer. SC V AC-+ AC Step counter load from memory. Loads complement of bits 7 through 11 of the word in memory following the instruction into the step counter. Two's MB 7 - 1 1 --+ SC PC+ 2--+ PC Multiplier quotient load into accumulator. The contents of the MQ are transferred into the AC. This instruction is given to load the 12 least significant bits of the product into the AC following a multiplication or to load the quotient into the AC following a division. The AC should be cleared prior to issuing this instruction or the CLA instruction can be combined with the MQA to clear the AC then effect the transfer. MQV AC--+AC Clear accumulator. The AC is cleared during sequence 1, allowing this instruction to be combined with other EAE instructions that load the AC during sequence 2 (such as SCA and MQA). 0--+ AC Clear accumulator and multiplier quotient. CAM=CLAMQL APPENDIX C 1/0 BUS INSTRUCTIONS In the 8 mode these instructions are given directly, whereas in the LINC mode they must be preceded by the instruction IOB (0500). Table C-1. IOT Instructions Mnemonic Octal Operation Program Interrupt ION 6001 IOF 6002 Turn interrupt on and enable the computer to respond to an interrupt request. When this instruction is given, the computer executes the next instruction, then enables the interrupt. The additional instruction allows exit from the interrupt subroutine before allowing another interrupt to occur. Turn interrupt off; i.e., disable the interrupt. High-Speed Perforated-Tape Reader and Control Type PR12 RSF RRB 6011 6012 RFC 6014 Skip if reader flag is a 1. Read the contents of the reader buffer and clear the reader flag. (This instruction does not clear the AC). RB V AC 4 - 1 1 _,. AC4 -1 1 Clear reader flag and reader buffer, fetch one character from tape and load it into the reader buffer, and set the reader flag when done. High-Speed Perforated-Tape Punch and Control Type PP12 PSF PCF PPC 6021 6022 6024 PLS 6026 Skip if punch flag is a 1. Clear punch flag and punch buffer. Load the punch buffer from AC 4- 11 and punch the character. (This instruction does not clear the punch flag or punch buffer). AC 4 - 11 V PB~ PB Clear the punch flag, clear the punch buffer, load the punch buffer from AC 4 - 11 , punch the character, and set the punch flag when done. C-1 Table C-1. IOT Instructions (Cont) Mnemonic Operation Octal Teletype Keyboard/Reader KSF KCC KRS 6031 6032 6034 KRB 6036 Skip if keyboard flag is a 1. Clear AC and clear keyboard flag. Read keyboard buffer static. (This is a static command in that neither the AC nor the keyboard flag is cleared.) TTI V AC4-11 ~ AC4-11 Clear AC, clear keyboard flag, and read the contents of the keyboard buffer into AC 4 - 1 1. TTO VAC 4-11 ~ AC4-11 Teletype Teleprinter/Punch TPC 6041 6042 6044 Skip if teleprinter flag is a 1. Clear teleprinter flag. Load the TTO from AC 4 - 11 and print and/or punch the character. TLS 6046 Load the TTO from AC 4-11 , clear the teleprinter flag, and print and/or punch the character. TSF TCF Power Fail/Restart Type KP 12 SPL 6102 Skip if power is low. Memory Extension Control Type MC12 CDF 62Nl CIF 62N2 RDF RIF RIB 6214 6224 6234 RMF 6244 Change to data field N. The data field register is loaded with the selected field number (0 to 7). All subsequent memory requests for operands are automatically switched to that data field until the data field number is changed by a new CDF instruction. Prepare to change to instruction field N. The instruction buffer register is loaded with the selected field number (0 to 7). The next JMP or JMS instruction causes the new field to be entered. Read data field into AC 6 _8 • Bits 0-5 and 9-11 of the AC are not affected. Same as RDF except reads the instruction field. Read interrupt buffer. The instruction field and data field stored during an interrupt are read into AC 6 - 8 and AC 9 - 11 respectively. Restore memory field. Used to exit from a program interrupt. Incremental Plotter and Control Type XY12 PLSF PLCF PLPU PLPR PLDU PLDD C-2 6501 6502 6504 6511 6512 6514 Skip if plotter flag is a 1. Clear plotter flag. Plotter pen up. Raise pen off paper. Plotter pen right. Plotter drum (paper) upward. Plotter drum (paper) downward. Table C-1. IOT Instructions (Cont) Mnemonic PLPL PLUD PLPD Octal 6521 6522 6524 Operation Plotter pen left. Plotter drum (paper) upward. (Same as 6512). Plotter pen down. Lower pen to paper. Random Access Disk File Type DF32 DCMA 6601 OMAR 6603 DMAW 6605 DCEA DSAC DEAL 6611 6612 6615 DEAC 6616 DFSE 6621 DFSC 6622 DMAC 6626 Clears memory address register, parity error and completion flags. This instruction clears the disk memory request flag and interrupt flags. The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to read information from the disk into the specified core location. Clears parity error and completion flags. Clears interrupt flags. The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to write information into the disk from the specified core location. Clears parity error and completion flags. Clears the disk extended address and memory address extension register. Skips next instruction if address confirmed flag is a 1 (AC is cleared). The disk extended address extension registers are cleared and loaded with the track data held in the AC. Clears the AC, then loads the contents of the disk extended address register into the AC to allow program evaluation. Skips next instruction if address confirmed flag is a 1. Skips next instruction if parity error, data request late, or write lock switch flag is a zero. Indicates no errors. Skips next instruction if the completion flag is a 1. Indicates data transfer is complete. Clears the AC, then loads contents of disk memory address register into the AC to allow program evaluation. Disk Control and Disk File Type RF08/RS08 DCMA 6601 DMAR 6603 DMAW 6605 DCIM DSAC DIML DIMA DFSC DFSC 6611 6612 6615 6616 6621 6622 DMAC 6626 Clears memory address register, parity error and completion flags. This instruction clears the disk memory request flag and interrupt flags. The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to read information from the disk into the specified core location. Clears parity and completion flags. Clears interrupt flags. The contents of the AC are loaded into the disk memory address register and the AC is cleared. Begin to write information into the disk from the specified core location. Clears parity error and completion flags. Clears the disk interrupt flag and memory address extension register. Skips next instruction if address confirmed flag is a 1 (AC is cleared). Accumulator to interrupt enables and memory extension register. Status to AC. Skip on error condition. Skip next instruction if the completion flag is a 1. Indicates data transfer is complete. Clears the AC then loads contents of disk memory address register into the AC to allow program evaluation. C-3 Table C-1. JOT Instructions (cont) Mnemonic Octal Operation Disk Cartridge Memory Type RK8/RKO I DLDC DLDR 6732 6733 DLDW 6735 DCHP 6737 DRDA 6734 DRDC DRDS DCLS DMNT 6736 6741 6742 6743 DLDA DSKD DSKE DCLA 6731 6745 6747 6751 DRWC 6752 DLWC 6753 DLCA 6755 DRCA 6757 Loads the command register from the AC and then clears the AC. Loads the track, surface, and sector address from the AC; the instruction then clears the AC and starts to read data from the disk if command register bit 4 is a 0. Loads the track, surface, and sector address from the AC. The instruction then clears the AC and starts to write on the disk if command register bit 4 is a 0. Loads the track, surface, and sector address from the AC. The instruction then clears the AC and reads data and checks parity if command register bit 4 is a 0. Clears the AC and then reads the Track Address Counter and surface/sector counter into the AC. Clears the AC and then reads the command register into the AC. Clears the AC and then reads the status register into the AC. Clears the status register. Load maintenance register. This instruction loads the maintenance register from the AC and carries out the operation specified. The bits will remain set until DMNT is reissued with all AC bits cleared to 0. Loads the disk address. This instruction is a maintenance operation. Skip On Transfer Done flag equal to 0. Skip when the error flag is set to I. Clear All. This instruction clears the selected disk to Track 000 and then clears all the control registers and status flags except the disk selection. Transfer Done is set when the disk is positioned on Track 000. Read word count register. This instruction clears the AC, then reads the contents of the word count register into the AC. Load word count register. This instruction loads the word count register from the AC and then clears the AC. Load current address register. This instruction loads the current address register from the AC and then clears the AC. Read current address register. This instruction clears the AC and then reads the contents of the current address register into the AC. Real Time Interface Type KW12A CLSK CLLR CLAB CLEN CLSA CLBA CLCA 6131 6132 6133 6134 6135 6136 6137 Skip if Clock Interrupt condition exists AC to Clock Control r~gister AC to Clock Buffer-Preset register AC to Clock Enable register Clock Status to AC Clock Buffer-Preset register to AC Clock Counter to Buffer Preset register and AC. Fixed-Interval Clock Type KWl 2-B, C CSOF CTOC CTON C-4 6131 6132 6134 Skip on clock flag. Turn off the clock, clears the clock flag and disables the clock interrupt. Turn the clock on and clears the flag. Mnemonic Operation Octal Fixed-Interval Clock Type KW12-B,C (cont) CRUN 6135 Clock running. Turns on the clock, enables the clock interrupt, and clears the clock flag. If the clock flag was set when the instruction was issued, it will skip. Automatic Line Printer and Control Type LP12 LSE LCF LLB LSD LCB LPR 6651 6652 6654 6661 6662 6664 Skip if the printer done flag is a 1. Clear both sections of the printing buffer. Skip if line printer error flag is a 1. Clear line printer done and error flags. Load printing buffer from the contents of AC 6 - 11 and clear the AC. Clear the format register, load the format register from the contents of AC 9 - 1 1 , print the line contained in the section of the printer buffer loaded last, clear the AC, and advance the paper in accordance with the selected channel of the format tape if the content of AC 8 = 1. If the content of ACs = 0, the line is printed and paper advance is inhibited. Line Printer Type LP08 LSF LCF LSR 6661 6662 6663 LPC 6664 LIN 6665 LLS LIF 6666 6667 Skip on character flag. Clear the character flag. Skip on error status line. (Error status line monitors interrupts caused by the printer not being ready; i.e., power error, paper jam, out of paper, etc.) Load the character into the print buffer and print if buffer is full or character was a control function. This instruction does not clear the AC. Set the program interrupts. Enable Microprogram combination of LCF and LPC. Clear the program interrupt flag. Card Reader and Control Type CRl2 RCSF RCRA 6631 6632 RCRB 6634 RCSP RCSE 6671 6672 RCRD 6674 Skip if card reader data ready flag is a 1. The alphanumeric code for the column is read into AC 6 _11 , and the data ready flag is cleared. The binary data in a card column is transferred into AC0 _1 1 , and the data ready flag is cleared. Skip if card reader card done flag is a 1. Clear the card one flag, select the card reader and start card motion towards the read station, and skip if the reader-not-ready flag is a 1. Clear card done flag. Automatic Magnetic Tape Control Type TCS8 MTSF 6701 Skip on error flag or magnetic tape flag. The status of the error flag (EF) and the magnetic tape flag (MTF) are sampled. If either or both are set to 1, the contents of the PC are incremented by one skipping the next sequential instruction. C-5 Table C-1. IOT Instructions (cont) Mnemonic Operation Octal Automatic Magnetic Tape Control Type TC58 (cont) MTCR 6711 MTTR 6721 MTAF 6712 MTRC 6724 6714 MTCM MTLC MTRS MTGO 6716 6704 6706 6722 MCLA 6702 Skip on tape control ready (TCR). If the tape control is ready to receive an instructionn, the PC is incremented by one skipping the next sequential instruction. Skip on tape transport ready (TTR). The next sequential instruction is skipped if the tape transport is ready. Clear the status and command registers, and the EF and MTF if tape control ready. If tape control not ready, clears MTF and EF flags only. Inclusively OR the contents of the command register into AC 0 - 11 . Inclusively OR the contents of ACo-s and AC 9 - 11 into the command register; JAM transfer bits 6, 7, 8 (command function). Load the contents of AC 0 - 11 into the command register. Inclusively OR the contents of the status register into AC 0 - 11 . Read the contents of the status register into AC 0 - 11 . Set "to" bit to execute instructions in the command register if instruction is legal. Clear the accumulator. General Purpose Converter and Multiplexer Control Type AFO 1A ADSF ADVC 6531 6532 ADRB ADCC ADSC 6534 6541 6542 ADIC 6544 C-6 Skip if A/D converter flag is a l. Clear A/D converter flag and convert input voltage to a digital number; flag will set at end of conversion. Number of bits in converted number determined by switch setting, 11 bits maximum. Read A/D converter buffer into AC, left justified, and clear flag. Clear multiplexer channel address register. Set up multiplexer channel as per AC 6 - 1 1 . Maximum of 64 single·ended or 32 differential input channels. Index multiplexer channel address (present address + 1). Upon reaching address limit, increment will cause channel 00 to be selected. APPENDIX D 8-MODE PERFORATED - TAPE LOADER READIN MODE LOADER The readin mode (RIM) loader is a minimum length, basic, perforated-tape reader program for the 33 ASR. It is initially stored in memory by manual use of the operator console keys and switches. The loader is permanently stored in 18 locations of page 3 7. A perforated tape to be read by the RIM loader must be in RIM format: Tape Channel 8 7 6 0 0 0 s 4 0 0 s 3 2 1 Format 0 0 0 Leader-trail code 0 Al A3 A2 A4 Absolute address to contain next 4 digits 0 0 0 0 0 XI X3 X2 X4 Contents of previous 4-digit address 0 0 I 0 Al A3 A2 X2 0 0 0 0 XI X3 (Etc.) 0 0 X2 X4 0 0 0 Address 0 0 Content (Etc.) Leader-trailer code The RIM loader can only be used in conjunction with the 33 ASR reader (not the high-speed perforated-tape reader). Because a tape in RIM format is, in effect, twice as long as it need be, it is suggested that the RIM loader be used only to read the binary loader when using the 33 ASR. (Note that some PDP-12 diagnostic program tapes are in RIM format.) D-1 The complete PDP-12 RIM loader (SA= 77 56) is as follows: Absolute Address Octal Content 7756 7757 7760, 7761, 7762, 7763, 7764, 7765, 7766, 7767, 7770, 7771, 7772, 7773, 7774, 7775, 7776, 7777, 6032 6031 5357 6036 7106 7006 7510 5357 7006 6031 5367 6034 7420 3776 3376 5356 0 5XXX Tag Instruction 1 Z BEG, KCC KSF JMP-1 KRB CLL RTL RTL SPA JMP BEG+l RTL KSF JMP-1 KRS SNL DCA 1 TEMP DCA TEMP JMP BEG 0 JMPX TEMP, Comments /CLEAR AC AND FLAG /SKIP IF FLAG = 1 /LOOKING FOR CHARACTER /READ BUFFER /CHANNEL 8 IN ACO /CHECKING FOR LEADER /FOUND LEADER /OK, CHANNEL 7 IN LINK /READ, DO NOT CLEAR /CHECKING FOR ADDRESS /STORE CONTENT /STORE ADDRESS /NEXT WORD /TEMP STORAGE /JMP START OF BIN LOADER Manually loading the RIM loader in core memory is accomplished as follows: 1. Set the starting address 7756 in the Left Switches. 2. Set the first instruction (6032) in the Right Switches. 3. Press the FILL Switch and then press the FILL STEP Switch. 4. Set the next instruction (6031) in the Right Switches. 5. Press the FILL STEP Switch. 6. Rep~at steps 4 and 5 until all 16 instructions have been deposited. 7. To ensure that RIM is in core, press Exam. The MA will = 7756, and the MB should = the first RIM instruction (6032 for low-speed reader). 8. To check sequential core locations, press Step Exam, and observe the contents of the MB. To load a tape in RIM format, place the tape in the reader, set the Left Switches to the starting address 7756 of the RIM loader (not of the program being read), press the START LS key, and start the Teletype reader. Refer to Digital Program Library document Digital-8-1-U for additional information on the Readin Mode Loader program. BINARY LOADER (8 MODE) The binary loader (BIN) is used to read machine language tapes (in binary format) produced by the program assembly language (PAL). A tape in binary format is about one half the length of a comparable RIM format tape. It can, therefore, be read about twice as fast as a RIM tape and is, for this reason, the more desirable format to use with the 10 cps 33 ASR reader or the Type PRl 2 High-Speed Perforated-Tape Reader. The format of a binary tape is as follows: LEADER: About 2 feet of leader-trailer codes. D-2 BODY: Characters representing the absolute, machine language program in easy-to-read binary (or octal) form. The selection of tape may contain characters representing instructions (channels 8 and 7 not punched) or origin resettings (channel 8 not punched, channel 7 punched), and is concluded by 2 characters (channels 8 and 7 not punched) that represent a checksum for the entire section. TRAILER: Same as leader. BODY: Characters representing the absolute, machine language program in easy-to-read binary (or octal) form. The selection of tape may contain characters representing instructions (channels 8 and 7 not punched) or origin resettings (channel 8 not punched, channel 7 punched), and is concluded by 2 characters (channels 8 and 7 not punched) that represent a checksum for the entire section. TRAILER: Same as leader. Tape Channel Memory 5 4 6 8 7 s 3 2 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 Content leader-trailer code origin setting 0200 0200 CLA 0201 TAD 277 0 0 0202 DCA 276 0 0 0 0203 HLT 0 0277 0 0 0 0 1 0 0 0 0 0277 0 0 origin setting 0053 1007 0 Comments 0 0 0 Location sum check leader-trailer code To load BIN 1. 2. 3. 4. 5. Select the 8 mode. Press the IO Preset switch twice. Put tape in the TTY reader, turn the reader on. Press Start LS (still set to 7756). When tape is read in, turn the reader off and stop the computer by pressing the Stop switch. D-3 To load binary tapes with the BIN loader 1. Place 7777 in Left Switches. 2. Set bit 0 of Right Switches to 1 for low-speed reader (TTY) or set bit 0 of Right Switches to 0 for high-speed reader. 3. Press Start LS. 4. Tape is read in and computer halts. 5. If AC unequal to 0000 a checksum error has occurred. After a BIN tape has been read in, one of the two following conditions exists: a. No checksum error: halt with AC = 0 b. Checksum error: halt with AC= (computed checksum) - (tape checksum) Operation of the BIN loader in no way depends upon or uses the RIM loader. To load a tape in BIN format place the tape in the reader, set the Left Switches to 7777 (the starting address of the BIN loader), set Right Switch register bit 0 0 up for loading via the Teletype unit or down for loading via the high-speed perforated-tape reader, then press the START LS key, and start the tape reader. Refer to Digital Program Library document Digital-8-2-U-RIM for additional information on the Binary Loader program. APPENDIX E TAPE MAINTENANCE INSTRUCTIONS E.l GENERAL In the Maintenance Mode, all signals from the tape transport are inhibited and data is simulated under program control. This mode is especially useful for troubleshooting and checking the operation of the TCl 2 Tape Control Logic. E.2 TAPE MAINTENANCE INSTRUCTIONS E.2.1 IOT 6141 This instruction is used to load the Tape Maintenance Instruction Register (used with IOT 6154) and to provide data and timing information to the TC 12 tape control unit when it is operating in the maintenance mode. It also checks the status of the Tape Done flag. This instruction is not to be microprogrammed and it should not be used to generate timing information during tape transfers, although it can be used to set the Tape Maintenance Instruction Register at any time. Any deviation from the above should be carefully checked with the logic diagrams to determine the expected result. The functions of the AC bits during this instruction are shown in Table E-1. Table E-1. AC Bit Functions AC Bit Number 00 01 02 03 04 05 06 07 08 09 10 11 Function Load into the Tape Maintenance Register (Bit Load into the Tape Maintenance Register (Bit Load into the Tape Maintenance Register (Bit Load into the Tape Maintenance Register (Bit Clear the Tape Done Flag Skip if Tape Done Flag is set Generate TTO Generate TT3 Simulate input data Mark Channel Simulate input data Data Channel 1 Simulate input data Data Channel 2 Simulate input data Data Channel 3 0) 1) 2) 3) E-1 E.2.2 IOT 6152 This instruction is used to generate various control pulses within the TC 12 Tape control unit. These control signals are used primarily for maintenance purposes. In special situations these controls are useful for handling nonstandard tape formats. The bits of instruction 6152 are gated with individual bits of AC register to generate a specific control function. These functions are intended to be used singly, and not while a tape instruction is in progress, and this instruction cannot be microprogrammed. Any deviation from the above should be carefully checked with the logic diagrams to determine the exact result. The functions of the AC bits during this instruction are shown in Table E-2. Table E-2. AC Bit Functions AC Bit Number Function 00 01 02 Tape Preset Shift RWB TB-+ RWB TB+ TAC-+ TAC Clear 8 Block Set Direction Backward Select Unit number 1 Set Direction Forward Set Write Sync Set Motion. Set Direction Forward if motion was cleared Select 8 Tape AC 11 -+ 8 Write Flip-Flop 03 04* 05* 06* 07* 08* 09* 10* 11* *These Bits are used in the TCl 2-F Tape Control E.2.3 IOT 6154 This instruction is used to load and examine the various registers of the TCl 2 Tape Control Unit. The action of this instruction is controlled by the contents of the Tape Maintenance Instruction Register and this action is shown in Table E-3. This instruction is not to be used during the operation of a tape instruction. Table E-3. JOT 6154 Effect of Tape Maintenance Instruction Register Contents Contents of bits 0, I, 2, & 3 Binary 0000 0001 0010 0011 0100 0101 E-2 Function Performed Octal 00 01 02 03 04 05 AC-+ TB AC-+ TBN AC-+ TAC AC-+ TMA TMA Setup -+ AC TBN-+AC Table E-3. IOT 6154 Effect of Tape Maintenance Instruction (cont) Register Contents Contents of bits 0, 1, 2, & 3 Binary Octal 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 06 07 10 11 12 13 14 15 16 17 Function Performed TB--+ AC RWB--+ AC Mark Window--+ AC Control States, Timing --+ AC Units & MTN --+ AC Tape Inst --+ AC Misc. Status 1 --+ AC Misc. Status 2 --+ AC TMA--+ AC E.2.4 IOT 6154 Detailed Transfer Information The Tape Maintenance Instruction Register is decoded to give a count of 00 8 to 17 8 • These count levels generate the signals necessary to enable the selected data onto the Tape Bus for a 12-bit parallel transfer between the AC and the Tape Registers. The following tables show the contents of the AC after the instruction associated with each table is given. Table E-4. Tape Maintenance Instruction Register Equal I 0 8 Mark Window --+ AC AC Bit 00 01 02 03 04 05 06 07 08 09 10 11 Data Read into AC LWN Wind LWN Wind LWN Wind LWN Wind LWN Wind LWNEM LWNCM LWNGM LWNDM LWNFM LWNBM LWNIM Shade ( 1) 00 (1) 01 (1) 02 (1) 03 (1) E-3 Table E-5. Tape Maintenance Instruction Register Equals 11 8 Control States & Timing--+ AC AC Bit Data Read Into AC 00 01 TAC= 7777 LCS Idle (1) LCS Search ( 1) LCS Block ( 1) LCS Check Word ( 1) LCS Tum Around ( 1) LCS Write (1) LCS Write Cycle ( 1) LTD ACIP LTD TTOK LTD Timing OK LTD Tape Fail Delay 02 03 04 05 06 07 08 09 IO 11 Table E-6. Tape Maintenance Instructions Register Equals 12 8 Units & Motion - AC Data Read Into AC AC Bit LTC Unit 0 (0) LTC Unit 1 (0) LTC Unit 2 (0) LTC Unit 3 (0) LTC Unit 4 (0) LTC Unit 5 (0) LTC Unit 6 (0) LTC Unit 7 (0) LMU motion ( 1) LMU Direction ( 1) LCS Tape OK (1) LTC Write EN (1) 00 01 02 03 04 05 06 07 08 09 10 11 Table -E-7. Tape Maintenance Instruction Register Equals 13 8 TINSTR--AC AC Bit 00 01 02 03 04 05 06 E-4 Data Read Into AC LIN RDC LIN RCG LIN RDE LINMTB LINWRC LINWRG LIN WRI Table E-7. Tape Maintenance Instruction Register Equals 13 8 (cont) TINSTR-AC AC Bit Data Read Into AC LIN CHK LIN I (1) LGP GP 0 (1) LGP GP 1 (1) LGP GP 2 (1) 07 08 09 10 11 Table E-8. Tape Maintenance Instruction Register Equals 14 8 MSC Status 1 AC Bit Data Read Into AC 00 01 02 03 04 05 06 07 08 09 10 11 LTS PHASE LIP IN PROGRESS (1) LTS LC 00 (1) LTS LC 01 (1) Mark Chan Write Data Chan 1 Write Data Chan 2 Write Data Chan 3 Write LGP GP= GPC (1) LGP GPCNT 0 (1) LGP GPCNT 1 (1) LGP GPCNT 2 (1) Table E-9. Tape Maintenance Instruction Register Equals 15 8 MSC Status 2 AC Bit 00 01 02 03 04 05 06 07 08 09 10 11 Data Read Into AC TC12-F WRITE SEL (1) TC12-F TAPE SEL (1) Not used E-5 APPENDIX F TABLES OF CODES Table F-1. Model 33/35 ASR/KSR Teletype Code (ASCII) in Octal Form Character 8-Bit Code Character (in octal) A B c D E F G H I J K L M N 0 p a R s T u v w x y z 301 302 303 304 305 306 307 310 311 312 313 314 315 316 317 320 321 322 323 324 32·5 326 327 330 331 332 (in octal) ! II # $ % & I { ) * + I : < = > ? @ [ \ ] t +- 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 270 271 8-Bit Code Leader!Trailer Line-Feed Carriage-A et urn Space Rub-out Blank alt-mode escape 241 242 243 244 245 246 247 250 251 252 253 254 255 256 257 272 273 274 275 276 277 300 333 334 335 336 337 200 212 215 240 377 000 375 233 F-1 Table F-2. Model 33 ASR/KSR Teletype Code (ASCII) in Binary Form 1 = HOLE PUNCHED = MARK 0 =NO HOLE PUNCHED =SPACE MOST SIGNIFICANT BIT C LEAST SIGNIFICANT BIT ) 8 7 6 5 4 r-- @ .,.....__ A ~ B s 3 2 1 0 0 0 START OF MESSAGE 0 0 0 0 END OF ADDRESS 0 0 0 1 0 1 1 I--- .._.,!_ END OF MESSAGE 0 0 0 $ I--- END OF TRANSMISSION 0 0 1 0 0 .,.....__ F .,...___ G 1--- H I--- I I--- J % t---- & I--- ' ( 1--) 1--- N r----i 0 1-----1 p 1-----1 fo- i--- w ..x i--- y ....,.__., z t--- [ ~ ....... t--- .. ] 0 0 0 0 1 0 0 0 1 0 + VERTICAL TAB 0 1 0 1 1 FORM FEED 0 l 1 0 0 r--!-- r-~ 0 1 CARRIAGE RETURN 0 1 1 0 1 SHIFT OUT 0 1 1 l 0 SHIFT IN 0 l DCO 1 0 f----1 l 1 l 0 0 0 ~ READER ON l TAPE (AUX ON) 1 0 0 1 0 1 1 0 0 0 1 1--- 3 t--4 t--- 5 t--- 6 t-7 t-- 8 1--- 9 t-- .--....:- READER OFF 1 0 0 (AUX OFF) 1 0 1 0 0 ERROR 1 0 1 0 SYNCHRONOUS IDLE 1 0 1 1 0 LOGICAL END OF MEDIA 1 0 1 1 1 so s1 1 l 0 0 0 1 l 0 0 1 S2 1 1 0 1 0 1 1 1 ~ < S3 1 l 0 S4 1 1 1 0 0 I-- = S5 1 l 1 0 > S6 1 1 1 1 0 ? S7 0: t-- '--r- ~ j~ 1 1 1 FORMAT EFFECTOR 1 1 u ....,.__., v 0 0 1 f----1 2 T BELL 1 0 Q s 1 1 0 0 1-----1 R r----i ~ 1 0 0 0 HORIZONTAL TAB 1--- M 0 0 LINE FEED 1--- ~ WHO ARE YOU ARE YOU . t--K 1--- 1 ~ i--- L F-2 0 0 NULL/IDLE 1--- D t--E f SPACE I--! I--- 1--- c RUB OUT ~ t-- 1 l t 1 1 1 1 '--v--J '--v---J ~~ ·~ 1 0 0 SAM~ ~l 0 1 SAME ...-1 1 0 SAME --1 1 1 SAME Table F-3. LT-37 Transmit and Receive Code Table 33 ASRMODE 37 KSRMODE SHIFT CHARACTER CODE A CHARACTER CODE K 101 102 303 104 305 306 107 110 311 312 113 L 3i4 M N 115 116 317 120 321 322 123 324 125 126 327 330 131 132 m n 240 41 42 243 44 245 246 47 250 251 0 B c D E F G H I J 0 p Q R s T u v w x y z SPACE ! ,, # $ % & ' ( ) 72 , < = > ? @ [ \ 273 74 275 276 77 300 333 134 a b c d e f g h i j k 1 0 p q r s t u v w x y z 1 2 3 4 5 6 7 8 9 * + ' - I ' . { NOT SHIFT SHIFT NOT SHIFT CHARACTER CODE 341 342 143 344 145 146 347 350 151 152 353 154 355 356 157 360 161 162 363 164 3(;)5 366 167 170 371 372 A B c D E F G H I J K L M N 0 p Q R s T u v w x y z 60 261 262 63 264 65 66 267 270 71 252 53 254 55 SPACE 56 > 257 140 173 374 CHARACTER ! ,, # $ % & ' ( ) ' < = ? @ [ \ 240 241 242 243 244 245 246 247 250 251 272 273 274 275 276 277 300 333 334 0 1 2 3 4 5 6 7 8 9 * + ' - I CODE 301 302 303 304 305 306 307 310 311 312 313 314 315 316 317 320 321 322 323 324 325 326 327 330 331 332 260 261 262 263 264 265 266 267 270 271 252 253 254 255 256 257 F-3 Table F-3. LT-37 Transmit and Receive Code Table (cont) 37KSRMODE CODE ] t ~ NULL SOH STX ETX EOT ENQ ACK BELL BACK SPACE ~TAB NEW LINE vTAB FORM RETURN So Si SHIFT NOT SHIFT SHIFT CHARACTER 33ASRMODE 335 336 137 000 201 202 3 204 5 6 207 210 11 12 213 14 215 216 217 CHARACTER } ,...., DEL DLE DCl DC2 DC3 DC4 NAK SYNC ETB CANCEL EM SUB ESCAPE FS GS RS QS CODE CHARACTER ] 175 176 377 220 21 22 223 24 225 226 27 30 231 232 33 234 35 36 237 t ~ NULL SOH STX EXT EOT ENQ ACK BELL BACK SPACE ~TAB NEW LINE vTAB FORM RETURN So Si NOT SHIFT CODE CHARACTER 335 336 337 200 201 202 203 204 205 206 207 210 211 212 213 214 215 216 217 ALT OR MODE DEL DLE DCl DC2 DC3 DC4 NAK SYNC ETB CANCEL EM SUB ESCAPE FS GS RS QS NOTE Letter codes transmitted from the 37 KSR keyboard in 33 mode will be upper case regardless of the position of the shift key; however, letter codes received by the KSR 37 in 33 mode will be printed in upper or lower case, as received. F-4 CODE 375 377 220 221 222 223 224 225 226 227 230 231 232 233 234 233 236 237 Table F-4. Card Reader Codes The following table gives the octal representation of the internal (binary) codes for the listed punch combinations. These internal codes are generated by the card reader and are transmitted to the PDP-12 upon execution of the appropriate IOT instruction. Any combination of punches which is not shown in the table is invalid, and the card reader can not detect invalid combinations. Card Code Num. Zone - 12 12 12 12 12 12 12 11 11 11 11 11 11 11 0 0 0 0 0 0 0 - - 12 12 12 12 12 12 - 8·2 8·3 8·4 8·5 8·6 8·7 8·2 8·3 8·4 8·5 8·6 8·7 1 8·2 8·3 8·4 8·5 8·6 8·7 8·3 8·4 8·5 8·6 8·7 1 2 3 4 5 6 Internal Code Character 00 11 11 11 11 11 11 11 10 10 10 10 10 10 10 01 01 01 01 01 01 01 00 00 00 00 00 11 Space 11 11 11 11 11 0000 1010 1011 1100 1101 1110 1111 0000 1010 1011 1100 1101 1110 1111 0000 0001 1010 1011 1100 1101 1110 1111 1011 1100 1101 1110 1111 0001 0010 0011 0100 0101 0110 Card Code Zone Num. +- 12 12 12 11 11 11 11 11 11 11 11 11 0 0 0 0 0 0 0 0 > - ? - # - [ < ( + t & ! $ * ) ' \ - I ] ' % @ - ' - = - " - A - B - c - 7 8 9 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 Internal Code 11 11 11 10 10 10 10 10 10 10 10 10 01 01 01 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 0111 1000 1001 0001 0010 0011 0100 0101 0110 0111 1000 1001 0010 0011 0100 0101 0110 0111 1000 1001 1010 0001 0010 0011 0100 0101 0110 0111 1000 1001 Character G H I J K L M N 0 p Q R s T u v w x y z 0 1 2 3 4 5 6 7 8 9 D E F ..----: F-5 Table F-5. LP08 Line Printer Code 64-Character Printer 0 AC 5 AC 6 0 AC 7 AC 8 AC 9 0 0 0 0 0 0 0 0 I I I I I I I 1 0 0 0 0 I I I I 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 0 1 1 0 1 0 1 1 0 AC10 AC11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Space ! " 0 I 0 I 0 I 0 # $ % & 1 0 I 0 I 0 I 0 1 ( ) PF * + FF CR I - I 0 I 2 3 4 @ p A B Q c s ' a b c T d t u v e u f v w R 8 D E F G H 9 I y J z , [ < = > K L M N ? 0 5 6 7 w x g h i p q r s x y j k { () 1 I ] m A n I v 0 D 96-Character Printer F-6 1 1 0 z } Table F-6. LPI 2 Automatic Line Printer Code Character (ASCII) 6-Bit Code (in octal) (cL 0 A B I c D E F G H I J K L M N 0 p Q R s T u v w x y z [ \ J 2 3 4 5 6 7 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 Character (ASCII) 6-Bit Code (in octal) II 40 41 42 43 $ 44 O/o 45 & 46 2 3 47 50 51 52 53 54 55 56 57 60 61 62 63 4 64 5 6 7 65 66 67 70 71 + I 0 l 8 9 72 < > ? 73 74 75 76 77 F-7/F-8 APPENDIX G CABLE CONNECTIONS TO PDP-12 FRONT PANEL Access to analog channels 10-17 and the extension scope socket is by means of the relay and analog input panel (see Figure 2-3). The addition of 16 channels of analog input with the AG 12 option, 16 additional preamplifiers, connects channels 20 8 to 37 8 to the analog extension panel supplied with the option. Analog knobs 0 8 to 7 8 , analog channels 10 8 to 37 8 , console scope display, and extension scope display utilize the following connectors and connect to the following module slots in the EMl 2 memory wing: Device Front Panel Connector Module Slot Analog Knobs 0 8 - 7 8 Analog Chan 10 8 -17 8 Analog Chan 20 8 -27 8 Analog Chan 30 8 -37 8 Extension Scope Display Console Display SK, 10-turn Potentiometers Switchcraft JAX # 13 B Amphenol 26-4401-32P Amphenol 26-4401-32P Amphenol 26-4401-24P Amphenol 57-30240 F33 F32 F31 F30 F39 F38 Table G-1 lists cable connections and signal names from each front panel termination to its corresponding slot in the EMI 2 memory wing. G-1 Table G-1. Cable Connections for PDP-12 Front Panel FRONT DEVICE Analog Knobs 0-7 Analog Channels 10-17 Analog Channels 20-37 Console Display and Extension Scope Display Type 503 Scope Connections G-2 SIGNAL NAME +7 volts - 7 volts Analog Chan 7 Analog Chan 6 Analog Chan 5 Analog Chan 4 Analog Chan 3 Analog Chan 2 Analog Chan 1 Analog Chan 0 PANEL PIN All Knobs All Knobs Knob 7 Knob 6 Knob 5 Knob4 Knob 3 Knob 2 Knob 1 Knob 0 - Analog Chan 20 +Analog Chan 20 DRAIN - Analog Chan 21 +Analog Chan 21 DRAIN - Analog Chan 22 + Analog Chan 22 DRAIN - Analog Chan 23 + Analog Chan 23 DRAIN - Analog Chan 24 + Analog Chan 24 DRAIN - Analog Chan 25 + Analog Chan 25 DRAIN - Analog Chan 26 + Analog Chan 26 DRAIN - Analog Chan 27 + Analog Chan 27 DRAIN I 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 DSX Chan Sel. (1) H SystemGND DRAIN DSC Intensity L System GND DRAIN XHQGND DSXXDefl. DRAIN YHQGND DSY Y Deft. DRAIN 1 2 3 4 5 6 7 8 9 10 11 12 503 Intensify System GND DRAIN 19 20 21 MODULE SIGNAL NAME - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan - Analog Chan + Analog Chan 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 I7 - Analog Chan 30 + Analog Chan 30 DRAIN - Analog Chan 31 + Analog Chan 31 DRAIN - Analog Chan 32 + Analog Chan 32 DRAIN - Analog Chan 33+Analog Chan 33 DRAIN - Analog Chan 34 + Analog Chan 34 DRAIN - Analog Chan 35 + Analog Chan 35 DRAIN - Analog Chan 36 + Analog Chan 36 DRAIN - Analog Chan 37 + Analog Chan 3 7 DRAIN FRONT PANEL PIN Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack Analog Phone Jack 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 SLOT PIN Al Bl Cl Dl El H1 Jl Kl L1 Ml NI Pl Sl Tl U1 VI Al Bl GND Cl Dl GND El H1 GND JI Kl GND L1 Ml GND Nl Pl GND Sl Tl GND U1 Vl GND Al Bl GND Cl Dl GND El H1 GND J1 Kl GND Sl Tl GND APPENDIX H MATHEMATICAL DATA Scales of Notation 2x IN Decimal 2' 0.001 0.002 0.003 0.004 0005 0.006 0.007 0.008 0.009 O.Ql 62581 11335 79633 01078 09503 38973 23785 98468 97782 1.00695 1.01395 1.02101 1.02811 1.03526 1.04246 1.04971 1.05701 1.06437 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 2' x 2' 33874 72557 16050 64359 17485 75432 38204 05803 78234 l.00069 1.00138 I.00208 l.00277 1.00347 l.00416 1.00486 1.00556 1.00625 55500 94797 21257 38266 49238 57608 66836 80405 01824 56719 90029 07193 56067 41377 41121 23067 61380 53360 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.07177 1.14869 1.23114 1.31950 1.41421 1.51571 1.62450 1.74110 1.86606 34625 83549 44133 79107 35623 65665 47927 11265 59830 36293 97035 44916 72894 73095 10398 12471 92248 73615 1o+n IN Octal 10" 1 12 144 1 750 23 420 3 46 575 346 10-· n 303 641 113 360 545 0 1 2 3 4 240 100 200 400 000 000 146 075 406 032 000 314 341 111 155 000 631 217 564 613 000 463 270 570 530 000 146 243 651 704 00 31 66 77 15 0.000 0 000 0.000 0.000 0.000 002 000 000 000 000 476 206 015 001 000 132 157 327 257 104 610 364 745 143 560 706 055 152 561 276 64 37 75 06 41 n log 0.30102 0.60205 0.90308 1.20411 1.50514 1 2 3 4 5 1 16 221 657 112 351 432 411 142 402 035 451 634 036 762 564 210 520 440 000 000 000 000 000 34 327 434 157 5 432 127 67 405 553 724 115 413 164 461 760 542 731 500 200 400 000 000 000 000 000 99957 99913 99870 99827 99783 3.32192 6.64385 9.96578 13.28771 16.60964 10 11 12 13 14 15 16 17 18 0.000 0.000 0.000 0.000 0.000 000 000 000 000 000 000 000 000 000 000 006 000 000 000 000 676 537 043 003 000 337 657 136 411 264 66 77 32 35 11 0.000 0.000 0.000 0.000 000 000 000 000 000 000 000 022 01 000 000 000 001 63 000 uoo 000 000 14 000 000 000 000 01 2, n log 2 10 IN Decimal n log2 10 n log10 2 n 10 10-· n 10" 1.000 0.063 0.005 0.000 0.000 n 80949 61898 42847 23795 04744 n log2 10 n los10 2 l.80617 2.10720 2.40823 2.70926 3.01029 6 7 8 9 10 99740 99696 99653 99610 99566 19.93156 23.25349 26.57542 29.89735 33.21928 85693 66642 47591 ~8540 09489 Addition and Multiplication Tables Addition Multiplication Binary Scale O+l=lo to= O= ol 1 I= 10 0 x 0 x 0 =0 l=lXO=O l x 1 = 1 Octal Scale 01 rr ,,.-1 = 02 03 04 05 06 06 07 02 03 04 05 04 06 10 12 14 16 06 JI 14 17 22 25 02 03 04 05 06 07 IO 2 03 04 05 06 07 10 11 3 04 OS 06 07 10 11 12 4 4 05 06 07 10 11 12 13 06 07 10 JI 12 13 14 6 07 10 11 12 13 14 15 10 11 12 13 14 15 16 6 07 10 14 20 24 30 34 12 17 24 31 36 43 14 22 30 36 44 52 16 25 34 43 52 61 Mathematical Constants in Octal Scale e = 2.55760 5213051 I = 3.11037 5524211 = 0.24276 301556, e-1 cc 0.27426 5306611 Ve= 1.51411 2307041 Vrr = 1.61337 6110671 In rr = 1.11206 4044351 logioe = 0.33626 754251' logi rr = 1.51544 163223, logi e = 1.34252 1662451 vTci = 3.12305 407267, logi 10 = 3.24464 7411361 In 1 0.44 742 147707, 0.43127 2336021 log11 -, - .0.62573 0306451 v2= 1.32404 746320, = 0.54271 027760, IO= 2.23273 067355, In 2 In H-1 Powers of Two 2 1 2 4 9 18 36 73 147 295 590 1 180 2 361 4 722 H-2 1 2 4 9 18 36 72 144 288 576 152 305 611 223 446 893 786 573 147 295 591 183 366 l 2 4 8 17 35 70 140 281 562 125 251 503 007 014 028 057 115 230 460 921 843 686 372 744 488 976 952 905 810 620 241 482 1 2 4 8 17 34 68 137 274 549 099 199 398 796 592 184 368 737 474 949 899 799 599 199 398 797 594 188 376 752 504 009 018 036 073 147 294 589 179 358 717 434 869 1 2 4 8 16 33 67 134 268 536 073 147 294 589 179 359 719 438 877 755 511 023 046 093 186 372 744 488 976 953 906 813 627 254 509 018 037 075 151 303 606 213 427 854 709 419 838 676 352 705 411 822 645 1 2 4 8 16 32 65 131 262 524 048 097 194 388 777 554 108 217 435 870 741 483 967 934 869 738 476 953 906 813 627 255 511 022 044 088 177 355 710 421 842 685 370 740 481 963 927 855 711 423 846 693 387 775 551 103 206 412 825 651 303 606 213 n 1 2 4 8 16 32 64 128 256 512 024 048 096 192 384 768 536 072 144 288 576 152 304 608 216 432 864 728 456 912 824 648 296 592 184 368 736 472 944 888 776 552 104 208 416 832 664 328 656 312 624 248 496 992 984 968 936 872 744 488 976 952 904 808 616 232 464 928 856 712 424 848 696 n 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 2 -n 1.0 0.5 0.25 0.125 0.062 0.031 0.015 0.007 0.003 0.001 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 25 625 812 906 953 976 488 244 122 061 030 015 007 003 001 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 5 25 125 562 281 140 070 035 517 258 629 814 907 953 476 238 119 059 029 014 007 003 001 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 5 25 625 312 156 578 789 394 697 348 674 837 418. 209 604 802 901 450 725 862 931 465 232 116 058 029 014 007 003 001 000 000 000 000 000 000 000 000 000 000 000 000 000 000 5 25 125 062 531 265 632 316 158 579 289 644 322 161 580 290 645 322 661 830 415 207 103 551 275 637 818 909 454 227 113 056 028 014 007 003 001 000 000 000 000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 o.ooo ooo ooo ooo poo 5 25 625 812 406 203 101 550 775 387 193 596 298 149 574 287 643 321 660 830 915 957 978 989 494 747 ~73 686 843 421 210 105 552 776 888 444 222 111 055 027 013 006 003 001 000 000 000 000 000 000 000 000 000 000 000 000 000 5 25 125 562 781 390 695 847 923 461 230 615 307 653 826 913 456 228 614 807 403 701 350 675 837 418 709 854 427 713 356 178 089 044 022 511 755 877 938 469 734 867 433 216 JOB 054 027 013 006 003 001 000 000 000 5 25 625 312 656 828 914 957 478 739 869 934 467 733 366 183 091 545 772 886 443 721 860 430 715 357 678 839 419 209 604 302 151 575 787 893 446 723 361 680 840 420 210 105 552 776 388 694 847 423 211 5 25 125 062 031 515 257 628 814 407 703 851 425 712 856 928 464 232 616 808 404 202 601 800 400 700 850 925 462 231 615 807 903 951 475 737 868 434 217 108 054 527 263 131 065 032 5.16 758 5 25 625 812 906 453 226 613 806 903 951 475 237 118 059 029 014 007 003 001 500 250 125 062 031 515 257 628 814 907 953 976 988 994 497 248 624 312 156 578 789 894 947 473 236 5 25 125 562 281 640 320 660 830 915 957 478 739 869 434 717 858 929 464 232 616 308 654 827 913 456 228 614 807 403 201 100 550 275 137 C68 034 017 508 254 627 813 5 25 625 312 156 078 039 519 759 379 689 844 422 711 355 677 338 169 084 042 021 510 755 377 188 094 547 773 886 443 221 610 805 402 201 600 300 150 575 5 25 125 062 531 765 882 941 970 485 242 621 810 905 452 726 363 181 590 295 647 823 411 205 602 801 400 700 850 425 712 356 678 339 169 084 5 25 625 812 406 703 351 675 337 668 334 667 333 166 583 791 395 697 848 924 962 981 490 745 372 186 093 546 273 136 068 534 767 5 25 125 562 781 890 945 472 236 618 809 404 702 851 925 962 481 240 120 560 280 640 320 160 580 290 645 322 161 080 5 25 625 312 656 328 164 082 541 270 135 567 783 391 695 347 173 086 043 021 010 005 002 001 500 250 625 5 25 125 062 031 015 5v7 253 626 813 906 953 976 988 994 497 748 874 437 718 359 679 339 169 5 25 625 812 906 953 476 738 369 684 342 171 085 542 271 135 567 283 641 820 910 5 25 125 562 281 140 570 285 142 571 785 392 696 848 924 962 981 490 5 25 625 312 156 578 289 644 822 411 205 102 051 025 512 5 25 125 062 531 265 132 566 783 391 695 847 5 25 625 812 406 203 601 800 900 5 25 125 562 5 781 25 390 625 Octal-Decimal Integer Conversion Table to 0000 0177 IOctol) I to 0000 0511 (Deciftlol) Octal Decimal 10000- 4096 20000- 8192 30000 - 12288 40000-1638' 50000 - 20480 60000 - 24576 70000 - 28672 .ooo to I 0512 to 1777 1023 (Octol) 10.cilftol) 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0000 0010 0020 0030 0040 0050 0060 0070 0000 0008 0016 0024 0032 0040 0048 0056 0001 0009 0017 0025 0033 0041 0049 0057 0002 0010 0018 0026 0034 0042 0050 0058 000;5 0011 0019 0027 0035 0043 0051 0059 0004 0012 0020 0028 0036 0044 0052 0060 0005 0013 0021 0029 0037 0045 0053 0061 0006 0014 0022 0030 0038 0046 0054 0062 0007 0015 0023 0031 0039 0047 0055 0063 0400 0410 0420 0430 0440 0450 0460 0470 0257 0265 0273 0281 0289 0297 0305 0313 0258 0266 0274 0282 0290 0298 0306 0314 0259 0267 0275 0283 0291 0299 0307 0315 0260 0268 0276 0284 0292 0300 0308 0316 0261 0269 0277 0285 0293 0301 0309 0317 0262 0270 0278 0286 0294 0302 0310 0318 0283 0271 0279 0287 0295 0303 0311 0319 0100 0110 0120 0130 0140 0150 0160 0170 0064 0072 0080 0088 0096 0104 0112 0120 0065 0073 0081 0089 0097 0105 0113 0121 0066 0074 0082 0090 0098 0106 0114 0122 0067 0075 0083 0091 0099 0107 0115 0123 0068 0076 0084 0092 0100 0108 0116 0124 0069 0077 0085 0093 0101 0109 0117 0125 0070 0078 0086 0094 0102 0110 0118 0126 0071 0079 0087 0095 0103 0111 0119 0127 0500 0320 0321 0510 0328 0329 05~0 0336 0337 0530 0344 0345 0540 0352 0353 0550 0360 0361 0560 0368 0369 0570 0376 0377 0322 0330 0338 0346 0354 0362 0370 0378 0323 0331 0339 0347 0355 0363 0371 0379 0324 0332 0340 0348 0356 0364 0372 0380 0325 0333 0341 0349 0357 0365 0373 0381 0326 0334 0342 0350 0358 0366 0374 0382 0327 0335 0343 0351 0359 0367 0375 0383 0200 0210 0220 0230 0240 0250 0260 0270 0128 0136 0144 0152 0160 0168 0176 0184 0129 0137 0145 0153 0161 0169 0177 0185 0130 0138 0146 0154 0162 0170 0178 0186 0131 0139 0147 0155 0163 0171 0179 0187 0132 0140 0148 0156 0164 0172 0180 0188 0133 0141 0149 0157 0165 0173 0181 0189 0134 0142 0150 0158 0166 0174 0182 0190 0135 0143 0151 0167 0175 0183 0191 0600 0610 0620 0630 0640 0650 0660 0610 0384 0392 0400 0408 0416 0424 0432 0440 0385 0393 0401 0409 0417 0425 0433 0441 0386 0394 0402 0410 0418 0426 0434 0442 0387 0395 0403 0411 0419 0427 0435 0443 0388 0396 0404 0412 0420 0428 0436 0444 0389 0397 0405 0413 0421 0429 0437 0445 0390 0398 0406 0414 0422 0430 0438 0446 0391 0399 0407 0415 0423 0431 0439 0447 0300 0310 0320 0330 0340 0350 0360 0370 0192 0200 0208 0216 0224 0232 0240 0248 0193 0201 0209 0217 0225 0233 0241 0249 0194 0202 0210 0218 0226 0234 0242 0250 0195 0203 0211 0219 0227 0235 0243 0251 0196 0204 0212 0220 0228 0236 0244 0252 01~7 0205 0213 0221 0229 0237 0245 0253 0198 0206 0214 0222 0230 0238 0246 0254 0199 0207 0215 0223 0231 0239 0247 0255 0700 0710 0720 0730 0740 0750 0760 0770 0448 0456 0464 0472 0480 0488 0496 0504 0449 0457 0465 0473 0481 0489 0497 0505 0450 0458 0466 0474 0482 0490 0498 0506 0451 0459 0467 0475 0483 0491 0499 0507 0452 0460 0468 0476 0484 0492 0500 0508 0453 0461 0469 0477 0485 0493 0501 0509 0454 0462 0470 0478 0486 0494 0502 0510 0455 0463 0471 0479 0487 0495 0503 OSI 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1000 1010 1020 1030 1040 1050 1060 1070 0512 0520 0528 0536 0544 0552 0560 0568 0513 0521 0529 0537 0545 0553 0561 0569 051<& 0522 0530 0538 0546 0554 0562 0570 0515 0523 0531 0539 0547 0555 0563 0571 0516 0524 0532 0540 0548 0556 0584 0572 0517 0525 0533 0541 0549 0557 0565 0573 0518 0526 0534 (1542 0550 0558 0566 0574 0519 0527 0535 0543 0551 0559 0567 0575 1400 1410 1420 1430 1440 1450 1460 1470 0768 0776 0784 0792 0800 0808 0816 0824 0769 0777 0785 0793 0801 080!1 0817 0825 077Q 0778 0786 0794 0802 0810 0818 0826 0771 0779 0787 0795 0803 0811 0819 0827 0772 0780 0788 0796 0804 0812 0820 0828 0773 0781 0789 0797 0805 0813 0821 0829 0774 0782 0790 0798 0808 0814 0822 0830 0775 0783 0791 0799 0807 0815 0823 0831 1100 1110 1120 1130 1140 1150 1160 1170 0576 0584 0592 0600 0608 0616 0624 0632 0577 0585 0593 0601 0609 0617 0625 0633 0578 0586 0594 0602 0610 0618 0626 0634 0579 0587 0595 0603 0611 0619 0627 0635 0580 0588 0596 0604 0612 0620 0628 0636 0581 0589 059'7 0605 0813 0621 0629 0637 0582 0590 0598 De06 IMl14 0622 0630 0638 0583 0591 0599 0607 0615 0623 0631 0639 1500 1510 1520 1530 1540 1550 1560 1570 0832 0840 0848 0856 0864 0872 0880 0888 0833 0841 0849 0857 0865 0873 0881 0889 0834 0842 0850 0858 0866 0874 0882 0890 0835 0843 0851 0859 0867 0875 0883 0891 0836 0844 0852 0860 0868 0876 0884 0892 0837 0845 0853 0861 0869 0877 0885 0893 0838 0846 0854 0862 0870 0878 0886 089~ 0839 0847 0855 0883 0871 0878 0887 0895 1200 1210 1220 1230 IZ40 1250 1260 1270 0640 0648 0656 0664 0672 0680 0688 0696 0641 0649 0657 0665 0673 0681 0689 0697 0642 0650 0658 0666 0674 0682 0690 0698 0643 0651 0659 0667 0675 0683 0691 0699 0644 0652 0660 0668 0676 0684 0692 0700 0645 0653 0661 0669 0677 0685 0693 0701 0646 0654 0662 0670 0678 0686 0694 0702 0647 0655 0663 0671 0679 0687 0695 0703 1600 1610 1620 1630 1640 1650 1660 1670 0896 0904 0912 0920 0928 0936 0944 0952 0897 0905 0913 0921 0929 0937 0945 0953 0898 09b6 0914 0922 0930 0938 0946 0954 0899 0907 0915 0923 0931 0939 0947 0955 0900 0908 0916 0924 0932 0940 0948 0956 090 I 0909 0917 0925 0933 0941 0949 0957 0902 0910 0918 0926 0934 0942 0950 0958 0903 0911 0919 0927 0935 0943 0951 0959 1300 1310 1320 1330 1340 1350 1360 1370 0704 0712 0720 0728 0736 0744 0752 0760 0705 071! 0721 0729 0737 0745 0753 0761 0706 0714 0722 0730 0738 0746 0754 0762 0707 0715 0723 0731 0739 0747 0755 0763 0708 0716 0724 0732 0740 0748 0756 0764 0709 0717 0725 0733 0741 0749 0157 0765 0710 0718 0726 0734 0742 0750 0758 0766 0711 0719 0727 0735 0743 0751 0759 0767 1700 1710 1720 1730 1740 1750 1750 1770 0960 0968 0976 0984 0992 1000 1008 1016 0961 0969 0977 0985 0993 1001 1009 1017 0962 0970 0978 0986 0994 1002 1010 1018 0963 0971 0979 0987 0995 1003 lOll IOU 0964 0972 0980 0988 0996 1004 1012 1020 0965 0973 0981 0989 0997 1005 1013 1021 0966 0974 0982 0990 0998 1008 1014 1022 0967 0975 0983 0991 0999 1007 1015 1023 01~9 0 0256 0264 0272 0280 0288 0296 0304 0312 H-3 Octal-Decimal Integer Conversion Table (Cont) 0 1 2 3 4 5 6 7 I 024 I 032 1040 1048 1056 1064 1072 1080 1025 1033 1041 1049 1057 1065 1073 1081 1026 1034 1042 1050 1058 1066 1074 1082 1027 1035 1043 1051 1059 1067 1075 1083 1028 1036 1044 1052 1060 1068 1076 1084 1029 1037 1045 1053 1061 1069 1077 1085 1030 1038 1046 1054 1062 1070 1078 1086 1031 1039 1047 1055 1063 10'11 1079 1087 1089 1097 1105 1113 1121 1129 2160 1136 II 37 2170 1144 114!'1 1090 1098 1106 1114 1122 1130 1138 114G 1091 1099 1107 1115 1123 1131 1139 1147 1092 1100 1108 1116 1124 1132 1140 1148 1093 1101 1109 1117 1125 1133 1141 1149 1094 1102 1110 1118 1126 1134 1142 1150 2200111S2 2210 1160 2220 1168 2231J 1176 2240 1'184 2250 1192 2260 1200 2270 1208 1153 1161 1169 1177 1185 1193 1201 ·1209 1154 1162 1170 1178 1186 1194 1202 1210 1155 1163 1171 1179 1187 1195 1203 1211 1156 1164 1172 1180 1188 1196 1204 1212 1157 1165 1173 1181 1189 1197 1205 1213 1216 1224 1232 1240 1248 1256 1264 1272 1217 1225 1233 1241 1249 1257 1265 1173 1218 1226 1234 1242 12SO 1258 1266 1274 1219 1227 1235 1243 1251 1259 1267 1275 1220 1228 1236 1244 1252 1260 1268 1276 0 I 2 3 3000 3010 3020 3030 3040 3050 3060 3070 1536 I 544 1552 1560 1568 1576 1584 1592 1537 1545 1553 1561 1569 1577 1585 1593 1538 I 546 1554 1562 1570 1578 1586 1594 3100 3110 3120 3130 3140 3150 3160 3170 1600 1608 1616 11124 1632 1640 1648 1656 1601 1609 1617 1625 1633 1641 1649 1657 3200 3210 3220 3230 3240 3250 3260 3270 1664 1672 1680 1688 1696 1704 1712 11720 3300 1728 3310J11J6 3320 1744 3330 1752 3340 1760 3350 1768 3360 1776 3370 1784 2000 2010 2020 2030 2040 2050 2060 2070 2100 2110 2120 2130 2140 H-4 I 2 3 4 5 6 7 2400 2410 2420 2430 2440 2450 2460 2470 1280 1288 1296 1304 1312 1320 1328 1336 1281 1289 1297 1305 1313 1321 1329 1337 1282 i290 1298 1306 1314 1322 1330 1338 1283 1291 1299 1307 1315 1323 1331 1339 1284 1292 1300 1308 1316 1324 1332 1340 1285 1293 1301 1309 1317 1325 1323 1341 1286 1294 1302 1310 1318 1326 1334 1342 1287 1295 1303 1311 1319 1327 1335 1343 1095 1103 1111 1119 1127 1135 1143 1!51 2500 2510 2520 2530 2540 2550 2560 2570 1344 1352 1360 1368 1376 1384 1392 1400 1345 1353 1361 1369 1377 1385 1393 1401 1346 1354 1362 1370 1378 1386 1394 1402 1347 1355 1363 1371 1379 1387 1395 1403 1348 1356 1364 1372 1380 1388 1396 1404 1349 1357 1365 1373 1381 1389 1397 1405 1350 1358 1366 1374 1382 1390 1398 1406 1351 1359 1367 1375 1383 1391 1399 1407 1158 1166 1174 1182 1190 1198 1206 1214 1159 1167 1175 1183 1191 1199 1207 1215 2600 2610 2620 2630 2640 2650 2660 2670 1408 1416 1424 1432 1440 1448 1456 1464 1409 1417 1425 1433 1441 1449 1457 1465 1410 1418 1426 1434 1442 1450 1458 1466 1411 1419 1427 1435 1443 1451 1459 1467 1412 1420 1428 1436 1444 1452 1460 1468 1413 1421 1429 1437 1445 1453 1461 1469 1414 1422 1430 1438 1446 1454 1462 1470 1415 1423 1431 1439 1447 1455 1463 1471 1221 1229 1237 1245 1253 1261 1269 1277 1222 1230 1238 1246 1254 1262 1270 1278 1223 1231 1239 1247 1255 1263 1271 1279 2700 2710 2720 2730 2740 2750 2760 2770 1472 1480 1488 1496 1504 1512 1520 1528 1473 1481 1489 1497 1505 1513 1521 1529 1474 1482 1490 1498 1506 1514 1522 1530 1475 1483 1491 1499 1507 1515 1523 1531 1476 1484 1492 1500 1508 1516 1524 1532 1477 1485 1493 1501 1509 1517 1525 1533 1478 1479 1486 1487 149~ 1495 1502 1503 1510 1511 1518 1519 1526 1527 1534 1535 4 5 6 7 0 I 2 3 4 5 6 7 1539 1547 1555 1563 1571 1579 1587 1595 1540 1548 1556 1564 1572 1580 1588 1596 1541 1549 1557 1565 1573 1581 1589 1597 1542 1550 1558 1566 1574 1582 1590 1598 1543 1551 1559 1567 1575 1583 1591 1599 3400 3410 3420 3430 3440 3450 3460 3470 1792 1800 1808 1816 1824 1832 1840 1848 1793 1801 1809 1817 1825 1833 1841 1849 1794 1802 1810 1818 1826 1834 1842 1850 1795 1803 1811 1819 1827 1835 1843 1851 1796 1804 1812 1820 1828 1836 1844 1852 1797 1805 1813 1821 1829 1837 1845 1853 1798 1806 1814 1822 1830 1838 1846 1854 1799 1807, 1815 1823 1831 1839 1847 1855 1602 1610 1618 1626 1634 1642 1650 1658 1603 1611 1619 1627 1635 1643 1651 1659 1604 1612 1620 1628 1636 1644 1652 1660 1605 1613 1621 1629 1637 1645 1653 1661 1606 1614 1622 1630 1638 1646 16.>4 1662 1607 1615 1623 1631 1639 1647 1655 1663 3500 3510 3520 3530 3540 3550 3560 3570 1856 1864 1872 1880 1888 1896 1904 1912 1857 1865 1873 1881 1889 1897 1905 1913 1858 1866 1874 1882 1890 1898 1859 1867 1875 1883 1891 1899 1!~06 1907 1914 1915 1860 1868 1876 1884 1892 1900 1908 1916 1861 1869 1877 1885 1893 1901 1909 1917 1862 1870 1878 1886 1894 1902 1910 1918 lBU 1871 1879 1887 1895 1903 1911 1919 1665 1673 1681 1689 1697 1705 1713 1721 1666 1674 1682 1690 1698 1706 1714 1722 1667 1675 1683 1691 1699 1707 1715 1723 1668 1676 1684 1692 1700 1708 1716 1724 1669 1677 1685 1693 1701 1709 1717 1725 1670 1678 1686 1694 1702 1710 1718 1726 1671 1679 1687 1695 1703 1711 1719 1727 3600 3610 3620 3630 3640 3650 3660 3670 1920 1928 1936 1944 1952 1960 1968 1976 1921 1929 1937 1945 1953 1961 1969 1977 1922 1930 1938 1946 1954 1962 1970 1978 1923 1931 1939 1947 19:i5 1963 1971 1979 1924 1932 1940 1948 1956 1964 1972 1980 1925 1933 1941 1949 1957 1965 1973 1981 1926 1934 1942 1950 1958 1966 1974 1982 1927 1935 1943 1951 1959 1967 1975 1983 1729 1737 1745 1753 1761 1769 1777 1785 1730 1738 1746 1754 1762 1770 1778 1786 1731 1739 1747 1755 1763 1771 1779 1787 1732 1740 1748 1756 1764 1772 1780 1788 1733 1741 1749 1757 1765 1773 1781 1789 1734 1742 1750 1758 1766 1774 1782 1790 1735 1743 1751 1759 1767 1775 1783 1791 3700 3710 3720 3730 3740 3!50 3760 3770 1984 1992 2000 2008 2016 2024 2032 2040 1985 1993 2001 2009 2017 2025 2033 2041 1986 1994 2002 2010 2018 2026 2034 2042 1987 199S 2003 2011 2019 2027 2035 2043 1988 1996 2004 2012 2020 2028 2036 2044 1989 1997 2005 2013 2021 2029 2037 2045 1990 1998 2006 2014 2022 2030 2038 2046 1991 1999 2007 2015 20Z3 2031 2039 2047 1088 1096 1104 1112 1120 "'T"' 2300 2310 2320 2330 2340 2350 2360 2370 0 2000 102• to to 2777 (Octol) 1535 (Decimal) Octal Decimal 10000. 4096 20000. 8192 30000- 12288 .coooo - 1638.C 50000 - 20.CSO 60000 • 24576 70000 • 28672 l 3000 to 1536 to 3777 20•7 COctol) (Deci111of) Octal-Decimal Integer Conversion Table (Cont) .ooo to I 2048 to 255~ •777 IOctall IDf'c;mal' Octal Decimal 10000· .. 096 20000. 8192 30000. 12288 .cooon • 1638.. 50000 • 20480 60000 • 24576 70000 . 28672 J 4 5 6 I 2 2048 2056 2064 2072 2080 40~0 2088 4060 2Q96 4070 2104 2049 2057 2065 2073 2081 2089 2097 2105 2050 2058 2066 2074 2082 2090 2098 2106 2051 2052 2053 2054 2059 2060 2061 2062 2067 2068 2069 2070 207~ 2076 2077 2078 2083 2084 20a5 2086 2091 2092 2093 2094 2099 2100 2101 2102 2107 2108 2109 2110 4100 4110 4120 4130 4140 4150 4160 4170 2112 2120 2128 2136 2144 2152 2160 2168 2113 2121 2129 2137 2145 2153 2161 2169 2114 2122 2130 2138 2146 2154 2162 2170 2115 2123 2131 2139 2147 2155 2163 2171 2116 2124 2132 2140 2148 2156 2164 2172 2117 2125 2133 2141 2149 2157 2165 2173 4200 4210 4220 4230 4240 4250 4260 4270 2176 2184 2192 2200 2208 2216 2224 2232 2177 2185 2193 2201 2209 2217 2225 2233 2178 2186 2194 2202 2210 2218 2226 2234 2179 2187 2195 2203 2211 2219 2227 2235 2180 2188 2196 2204 2212 2220 2228 2236 4300 4310 4320 4330 4340 4350 4360 4370 2240 2248 2256 2264 2272 2280 2288 2296 2241 2249 2257 2265 2273 2281 2289 2297 2242 2250 2258 2266 2274 2282 2290 2298 2243 2251 2259 2267 2275 2283 2291 2299 2244 2252 2260 2268 2276 2284 2292 2300 0 4000 4010 4020 4030 4040 7 0 1 2 3 4 5 6 1 2055 2063 2071 2079 2087 2095 2103 2111 4400 4410 4420 4430 4440 4450, 4460 4470 2304 2312 2320 2328 2336 2344 2352 2360 2305 2313 2321 2329 2337 2345 2353 2361 2306 2314 2322 2330 2338 2346 2354 2362 2307 2315 2323 2331 2339 2347 2355 2363 2308 2316 2324 2332 2340 2348 2356 2364 2309 2317 2325 2333 2341 2349 2357 2365 2310 2318 2326 2334 2342 2350 2358 2366 2311 2319 2327 2335 2343 2351 2359 2361 2118 2126 2134 2142 2150 2158 2166 2174 2119 2127 2135 2143 2151 2159 2167 2175 4500 4510 4520 4i30 4540 4550 4560 4570 2368 2376 2384 2392 2400 2408 2416 2424 2369 2377 2385 2393 2401 2409 2417 2425 2370 2378 2386 2394 2402 2410 2418 2426 2371 2379 2387 2395 2403 2411 2419 2427 2372 2380 2388 2396 2404 2412 2420 2428 2373 2381 2389 2397 2405 2413 2421 2429 2374 2382 2390 2398 2406 2414 2422 2430 2375 2383 2391 2399 2407 2415 2423 2431 2181 2189 219':' 2205 2213 2221 2229 2237 2182 2190 2198 2206 2214 2222 2230 2238 2183 2191 2199 2207 2215 2223 2231 2239 4600 4610 4620 4630 4640 4650 4660 4670 2432 2440 2448 2456 2464 2472 2480 2488 2433 2441 2449 2457 2465 2473 2481 2489 2434 2442 2450 2458 2466 2474 2482 2490 2435 2443 2451 2459 2467 2475 2483 2491 2436 2444 2452 2460 2468 2476 2184 2492 2437 2445 2453 2461 2469 2477 2485 2493 2438 2446 2454 2462 2470 2478 2486 2494 2439 2447 2455 2245 2253 2261 2269 2277 2285. 2293 2301 2246 2254 2262 2270 2278 2286 2294 2247 2255 2263 2271 2279 2287 2295 2303, 4700 2.496 4710 2504 4720 2512 4730 2520 474012528 4750 2536 4760, 25H 4770 ! 2552 2497 2505 2513 2521 2529 2537 2545 2553 2498 2506 2514 2522 2530 2538 2546 2554 2499 2507 2515 2523 2531 2539 2547 2555 2500 2508 2516 2524 2532 2540 2548 2556 2501 2509 2517 2525 2533 2541 2549 2557 2502 2510 2518 2526 2534 2542 2550 2558 2503 2511 2519 2527 2535 2543 2551 2559 ~302 I 24~3 2471 2479 2487 2495 -~, 2 3 4 5 6 7 25831 2591 2599 2607 2615 2623 54oo12s16 541012824 5420 2832 5430 2840 5440. 2848 5450 2856 5460 2864 5470 2872 2817 2825 2833 2841 2849 2851 2865 2873 2818 2826 2834 28-12 2850 2858 2866 2874 2819 2827 2835 2843 2851 2859 2867 2875 2820 2828 2836 2844 2852 2860 2868 2876 28:!1 2829 2837 2845 2853 286l 2869 2877 2822 2830 2838 2846 2854 2862 2870 2878 2123 2131 2131 2630 2638 2646 2654 2662 2670 2678 2686 2631 2639 2647 2655 2663 2671 2679 2687 5500 5510 5520 5530 5540 5550 5560 5570 2880 2688 2896 2904 2912 2920 2928 2936 2881 2889 2897 2905 2913 2921 2929 2937 2882 2890 2898 2906 2914 2922 2930 2938 2883 2891 2899 2907 2915 2923 2931 2939 2884 2892 2900 2908 2916 2924 2932 2940 2885 2893 2901 2909 2917 2925 2933 2941 2886 2894 2902 2910 2918 2928 2934 2942 2887 2895 2903 2911 2919 2927 2935 2943 2693 2701 2709 2717 2725 2733 2741 2749 2694 2702 2710 2718 2726 2734 2i42 2750 2695 2703 2711 2719 2727 2735 2743 2751 5600 2944 561012952 562012960 5630 2968 564012976 5650 298-1 5660 2992 5670 3000 2945 2946 2947 2948 2953 2954 2955 2956 2961 2962 2963 2964 ~9!i9 2970 2971 2972 2977 2978 2979 2980 2985 2986 2987 2988 2993 2994 2995 2996 3001 3002 3003 3004 2949 2957 2965 2973 2981 2989 2997 3005 2950 2958 2966 2974 2982 2990 2998 3006 2951 2959 2961 2975 2983 2991 2999 3007 2757 2765 2773 2781 2789 2797 2805 2813 2758 2766 2774 2782 2790 2798 2806 2814 2759 2767 2775 2783 2791 2799 2807 2815 :>700 5710 5720 5730 5740 5750 5760 5770 3009 3017 3025 3033 3041 3049 3057 3065 30l 3 3021 3029 3037 3045 3053 3061 3069 3014 3022 3030 3038 3046 3054 3062 3070 3015 3023 3031 3039 3047 3055 3 40 H-6 4 0 0 3 6000 to 6777 I (Octol) 3072 to 3513 (Decimal) Octal Decimal 10000- ..096 20000- 8192 30000 - 12288 "0000 - 1638.. 50000 - 20..80 60000 - 2 ..576 70000 • 28672 7000 to I 3,., to 7777 "4095 COctal) (DHimal) Octal-Decimal Fraction Conversion Table OCTAL DEC. OCTAL Dl::C. OCTAL m:c. OCTAL m:c . .000 .001 .002 .003 • 004 . 005 . 006 .007 .010 . Oll .OlZ .013 .014 .015 .016 • 017 .020 .021 .022 .023 • 024 .025 .02& .027 . 030 .031 .032 .033 .034 .035 .036 • 037 .040 . 041 .042 .043 .044 .045 . 046 .047 • 000000 • 001953 • (Jo3905 . 005859 • 007812 . 009765 • 011718 • 013671 • 015625 .017578 • 019531 • 021484 • 023437 • 025390 • 027343 • 029296 .031250 • 033203 • 035156 • 037109 • 039062 .041015 • 042968 • 044921 . 046875 • 048828 • 050781 • 052734 • 054687 • 056640 • 058593 • 060546 • 062500 • 064453 • 066406 • 068359 • 070312 • 072265 • 074218 • 076171 • 078125 • 080078 • 082031 • 083984 • 085937 • 087890 • 089843 • 091796 • 093750 • 095703 • 097656 • 099609 • 101562 .103515 • 105468 • 107421 .109375 • 111328 • 113281 • 115234 • 117187 • 119140 .121093 .123046 .100 .101 .102 .103 • 104 • 105 .106 .107 .110 • 111 .112 .113 .114 .115 .116 .117 .120 .121 .122 , 123 • 124 • 125 .126 .127 .130 • 131 .132 .133 • 134 .135 .136 • 137 .140 .141 .142 • 143 .144 .145 .146 .147 .150 .151 .152 .153 .lM • 155 • 156 .157 • 160 .161 • 162 .163 • 164 .165 .166 . 167 . 170 • 171 .172 . 173 . 174 . 175 • 176 • 177 • 125000 • 126953 . 128906 • 130859 .13:?812 • 134765 • 136718 • 138671 • 140625 • 142578 • 144531 • 146484 .148437 • 150390 .152343 • 154296 • 156250 • 158203 .160156 • 162109 • 164062 .166015 .167968 • 169921 • 171875 • 173828 .175781 • 1'17734 • 179687 • 181640 • 183593 . 185546 • 187500 . 189453 . 191406 • 193359 .195312 .197265 .199218 • 201171 • 203125 • 205078 • 207031 • 208984 • 210937 • 212890 • 214843 • 216796 • 218750 • 220703 • 222656 • 224609 • 226562 • 228515 • 230468 • 232421 • 234375 • 236328 • 238281 • 240234 • 242187 • 244140 • 246093 • 248046 . 200 • 201 • 202 .203 . 204 .205 . 206 . 207 • 210 . 211 • 212 .213 .214 .215 .216 .217 . 220 • 221 .222 .223 .224 .225 • 226 .227 .230 .231 .232 .233 .234 • 235 .236 • 237 • 240 • 241 • 242 .243 .244 .245 .246 .247 .250 • 251 • 252 .253 • 254 • 255 .256 .257 .260 • 261 .262 .263 .264 .265 .266 • 267 • 270 • 271 .272 .273 .274 .275 .276 .277 • 250000 . 251953 • 253906 • 255859 • 257812 . 259765 .261718 • 263671 . 265625 . 267578 • 269531 • 271484 • 273437 • 275390 • 277343 • 279296 • 281250 • 283203 • 285156 • 287109 • 289062 • 291015 • 292968 .294921 • 296875 • 298828 • 300781 • 302734 • 304687 • 306640 .308593 .310546 • 312500 • 314453 • 316406 • 318359 .320312 • 322265 • 324218 • 326171 • 328125 • 330078 • 332031 • 333984 • 335937 • 337890 • 339843 • 341796 • 343750 • 345703 • 347656 . 349609 • 351562 .353515 • 355468 .• 357421 • 359375 ,361328 • 363281 • 365234 • 367187 ,369140 • 371093 ,373046 . 300 . 301 . 302 . 303 . 304 . 305 . 306 . 307 . 310 . 311 . 312 • 313 . 314 .315 .316 .317 • 320 • 321 . 322 . 323 .324 . 325 . 326 .327 .330 . 331 .332 ,333 .334 .335 .336 .337 .340 . 341 .342 ,343 .344 .345 .346 .347 .350 • 351 .352 .353 ,354 ,355 .356 .357 .360 .361 .362 • 363 .364 • 365 .366 . 367 .370 • 371 .372 .373 ,374 .375 .376 .377 .375000 • 37G953 .37890(, .380859 . 382812 .3847fi5 • 386718 .388671 .390625 . 3!12578 . 394531 .396484 .398437 ,400390 • 402343 .404296 .406250 .408203 .410156 .412109 .414062 .416015 • 417968 .419921 • 421875 .423828 • 426781 .427734 .429687 .431640 .433593 ,435M6 • 437500 .439453 .441406 ,443359 ,445312 .447265 ,449218 ,451171 .453125 ,455078 • 457031 ,458984 • 460937 .462890 ,464843 • 466796 ,468750 • 470703 • 472656 • 474609 • 476562 • 478515 ,460468 .482421 • 484375 ,486328 ,488211 ,490234 ,492187 • 494140 .496093 .4990415 .oso . 051 .052 .053 .054 .055 • 056 . 057 . 060 • 061 • 062 . 063 . 064 . 0&5 .066 . 067 . 070 • 071 ,072 . 073 . 074 • 075 . 076 • 077 H-7 Octal-Decimal Fraction Conversion Table (Cont) OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC • .000000 .000001 .000002 .000003 .000004 • 000005 .000006 .000007 • 000010 • 000011 • 000012 • 000000 .000003 .000007 .000011 .000015 .000019 .000022 .000026 .000030 .000034 .000038 ,000041 ,000045 .000049 .000053 • 000057 .000061 ,000064 ,000088 .000072 • 00007' .000080 ,000083 .000087 .000091 .000095 .000099 .000102 .000106 .000110 ,000114 .000118 .000122 .000125 .000121 .000133 .000137 ,000141 • 000144 .000148 • 000152 .000158 .000180 • 000164 .000167 .000171 .000175 .000179 .000183 .000188 .000190 .000114 .000198 ,000202 .000205 ,000209 .000213 .000217 .000221 .000225 .000221 .000232 ,000238 .000140 .000100 . 000101 • 000102 • 000103 • 000104 • 000105 .000106 • 000107 ,000110 .000111 • 000112 .000113 ,000114 ,000115 .000116 .000117 .000120 ,000121 .000122 ,000123 .000124 ,000125 .000128 .000127 .000130 .000131 ,000132 .000133 ,000134 ,000135 ,000138 .000137 .000140 ,000141 .000142 .000143 .000144 ,000145 ,000148 .000147 .000150 ,000151 .000152 .000153 ,000154 ,000155 .000158 .000157 .000180 .000181 .000182 .000113 • 000184 .000165 • 000166 .000167 • 000170 ,000171 .000172 • 000173 • 000174 • 000175 ,000176 ,000171 .000244 .000247 .000251 .000255 .000259 .000213 .001)267 .000270 .000274 .000278 .000282 .000288 .000289 .0002u .000297 ,000301 .000305 .000308 .000312 .000318 .000320 .000324 .000329 .000331 .000335 ,000339 .000343 .000347 ,000350 .000354 ,000358 .000312 .000318 ,000370 .000373 .00037' .000311 .000315 .000389 .000392 .000396 ,000400 .000404 .000408 ,000411 ,000415 .000411 .000413 .000427 .000431 .000434 .OOH38 .000442 .000448 .000450 .000453 .000457 .000200 .000201 .000202 .000203 .000204 .000205 .000206 .000207 .000210 .000211 .000212 .000213 .000214 ,000215 ,000218 ,000217 • 000488 • 000492 • 000495 • 000499 • 000503 • 000507 • 000511 • 000514 • 000518 • 000522 • 000526 • 000530 • 000534 • 000537 • 000541 • 000545 • 000549 • 000553 .000551 • 000580 • 000564 . 000588 • 000572 • 000576 • 000579 • 000583 • 0005•1 .000591 • 000595 ,000598 .000802 .000808 • 000610 • 000614 • 000817 .000621 .000825 • 000629 • 000833 .000637 ,000640 .000844 .000648 .000852 ,00065' .000859 .000813 • 000187 ,000671 ,000875 .000679 • 000682 • 000686 • 000690 .00069< .000698 .000701 .000705 .000709 .000713 .000117 .000720 ,000724 • 000121 .000300 .000301 .000302 .000303 • 000304 .000305 .000306 .000307 • 000310 .000311 .000312 .000313 .000314 .000315 ,000316 ,000317 • 000320 • 000321 • 000322 • 000323 • 00032'4 .000325 • 000326 • 000327 • 000330 • 000331 • 000332 .000333 .000334 .000335 .000338 .000337 .000340 ,000341 .000342 .000343 .000344 ,000345 .OOOHt; .000347 ,000350 • 000351 .000351 ,000353 .000354 .000355 .000356 ,0003 ... .000380 .000361 .000362 .000313 .000364 .000365 .000316 .000367 .000370 .000371 • 000372 .000373 .000374 ,000375 .000376 .000377 • 000732 .000736 • 000740 • 000743 .000747 • 000751 .000755 .000759 .000762 .000766 .000710 .000714 .000718 .000782 ,000715 .000799 • 00079'3 .000797 • 000801 .000805 .000808 .000812 • 000818 • ooo8zo .000823 .000821 • 000831 .000835 .000139 .000843 .000846 .000850 .000854 .000858 .000182 .000185 .000869 ,000813 .000877 .000881 ,000885 ,000818 .Oto892 .000898 ,000900 .000904 .000907 .000911 .000915 • 000919 .000923 .000926 • 000930 • 000934 • 000938 • 0009"2 • 000946 .000949 .000953 .000957 ,000961 .000965 .000968 ,000912 .000013 .000014 ,000015 .000018 ,000017 .000020 .000021 ,000022 .000023 ,000024 .000025 ,000026 ,000027 .000030 .000031 • 000032 .000033 ,000034 .OU0035 .000038 .000037 ,000040 .000041 .000042 • 000043 .000044 .000045 .000046 .l'00047 .000050 ,000051 .000052 ,000053 ,000054 .000055 ,000058 ,000051 .000080 • 000081 .000062 .000063 .000064 .000065 .000066 ,000067 ,000070 ,000071 .000072 .000073 .000014 .000075 .000071 .000011 H-8 .000481 .000485 .000469 .000413 .000476 .000480 ,000484 .oooazo .000221 ,000222 ,000223 ,000224 .0002Z5 .000226 .000227 ,000230 .000231 .000232 .000233 ,000234 .000235 ,000238 ,000237 ,000240 .000241 .000242 .000243 .000244 ,000245 ,000248 .000241 .ooouo .000251 .000252 .000253 ,000254 .000255 .000258 .000257 .000260 .000261 .000262 .000263 .000264 .000265 .000266 .000267 .000270 .000271 ,000212 .000273 .000274 ,000275 ,000276 .000277 Octal-Decimal Fraction Conversion Table (Cont) OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC, .000400 • 000401 .000402 .000403 .000404 .000405 .000406 ,000407 .000410 .000411 .000412 ,000413 .000414 .000415 .000416 .000417 .000976 • 000980 .000984 • 000988 • 000991 • 000995 .000999 • 001003 .001007 • 001010 • 001014 • 001018 • 001022 • 001026 • 001029 .001033 • 000500 • 000501 .000502 . 000503 • 000504 • 000505 • 000506 • 000507 • 000510 • 000511 .000512 ,000513 .000514 • 000515 .000516 • 000517 • 001220 • 001224 • 001228 • 001232 • 001235 • 001239 • 001243 • 001247 . 001251 • 001255 • 001258 • 001262 • 001266 • 001270 • 001274 • 001277 • 000600 • 000601 .000602 .000603 .000604 • 000605 .000606 .000607 .000610 • 000611 • 000612 ,000613 • 000614 • 000615 • 000616 • 000617 • 001464 • 001468 • 001472 • 001476 • 001480 • 001483 • 001487 • 001491 • 001495 • 001499 • 001502 • 001506 • 001510 • 001514 ,001518 • 001522 • 000700 • 000701 • 000702 • 000703 • 000704 • 000705 • 000706 • 000707 • 000710 • 000711 • 000712 • 000713 • 000714 • 000715 • 000716 • 000717 • 001708 • 001712 • 001716 • 001720 • 001724 • 001728 .001731 • 001735 • 001739 • 001743 .0017·47 • 001750 • 001754 • 001758 • 001762 • 001766 .000420 .000421 ,000422 .000413 .000424 .000425 .000426 ,000427 .000430 .000431 .000432 ,000433 .000434 ,000435 ,0004311 .000437 .000440 .000441 .000442 .000443 .000444 .000446 .000448 .000447 .000450 .000451 .000452 .000453 .000454 .000455 .000458 .000457 .000410 .000411 .000411 .000483 .0004M .000465 • 000466 .000467 .000470 .000471 .000472 .000473 .000474 .000475 .000476 .000477 • 001037 • 001041 • 001045 • 001049 • 001052 .001056 .001060 • 001064 .001068 ,001071 .001075 • 001079 • 001083 .001087 • 001091 .001094 .000520 .000521 .000522 .000523 • 000524 .000525 .000526 .000527 .000530 .000531 .000532 ,000533 .000534 .OOOS35 .000536 .000537 .000540 .000541 .000542 .000543 .00054-4 .000545 .000546 .000541 ,000550 ,000551 .000552 .000553 .000554 ,000555 .000556 .000557 ,000560 .000561 .000562 ,000563 .000564 .000565 .000566 .000567 .000570 .000571 .000572 .000573 .000574 .000575 • 000576 • 000577 • 001281 • 001285 • 001289 • 001293 • 001296 • 001300 • 001304 • 001308 • 001312 • 001316 • 001319 • 001323 • 001327 • 001331 • 001335 • 001338 • 001342 • 001346 .001350 • 001354 • 001358 • 001361 .001365 .001369 • 001373 .001377 • 001380 .001384 • 001388 • 001392 • 001396 .001399 .001403 • 001407 • 001411 .001415 .001419 .001422 • 001426 • 001430 .001434 • 001438 • 001441 • 001445 • 001449 • 001453 • 001457 • 001461 .000620 .000621 .000622 • 000623 .000624 .000625 .000626 ,000627 .000630 • 000631 • 000632 .000633 .000634 ,000635 • 000636 .000637 • 000640 • 000641 .000642 ,000643 .000644 .000645 .000646 .000647 .000650 • 000651 .000652 .000653 .000654 .000655 .000656 ,000657 ,000660 • 000661 .000662 ,000663 000664 .000665 .000666 000667 .Ci>0670 • 000671 .000672 ,000673 .000674 .000675 .000676 • 000677 ,001525 . 001529 • 001533 • 001537 • 001541 • 001544 • 001548 • 001552 . 001556 • 001560 • 001564 • 001567 .001571 . 001575 .001579 • 001583 • 001586 . 001590 • 001594 • 001598 .001602 • 001605 • 001609 • 001613 ,001617 • 001621 • 001625 • 001628 • 001632 • 001636 • 001640 • 001644 ,001647 • 001651 • 001655 • 001659 • 001663 • 001667 • 001670 • 001674 • 001678 • 001682 • 001686 • 001689 . 001693 • 001697 . 0017.Dl • 001105 • 000720 • 000721 • 000722 . 000723 • 000724 • 000725 • 000726 • 000727 • 000730 • 000731 • 000732 • 00()733 • 000734 • 000735 • 000736 • 000737 • 000740 • 000741 • 000742 • 000743 • 000744 • 000745 • 000746 • 000747 • 000750 • 000751 • 000752 • 000753 • 000754 .000755 .000756 • 000757 • 000760 • 000761 • 000762 .000763 • 000764 .000785 • 000766 • 000767 • 000770 .000771 .000772 • 000773 • 000774 • 000775 .000776 • 000777 • 001770 • 001773 • 001777 .001781 • 001785 • 00171:19 • 001792 • 001796 • 001800 • 001804 • 001808 ,001811 .001815 • 001819 • 001823 • 001827 • 001831 .001834 • 001838 • 001842 ,001846 • 001850 .001853 • 001857 .001861 • 001865 .001869 .001873 .001876 • 001880 • 001884 .001881 .00189% .001895 .001899 .001903 • 001907 • 001911 ,001914 ,001918 ,00lt22 • 001926 ,001930 • 001934 • 001937 • 001941 ,001945 • 001949 • 001098 • 001102 • 001106 • 001110 • 001113 .001117 • 001121 • 001125 • 001129 • 001132 .001136 • 001140 • 001144 • 001148 • 00115% • 001155 • 001159 .oonu • 001167 • 001171 • 001174 .001178 • 001182 • 001186 • 001190 ,001194 • 001197 .0012 • 00120:) • 001209 • 001213 • 001216 H-9 Index B A AAOl-A Digital-To-Analog Accumulator (AC), Description Accumulator, I/O Transfers A-D Converter Controls A-D Converter Instructions AD 12 Analog-Digital Converter and Multiplexer Addressing: a-Class Addressing, Combination of Extended Memory Programming Addressing Methods, 8 Mode Addressing Methods, Memory Addressing: a-Class {3-Register {3-Register Indexing Direct Addressing, LINC mode Indirect Addressing: ~-Class AFOl-A A-D Converter Specifications AFOl-A Analog-To-Digital Converter AFOl-A Sample and Hold Options a-Class, Addressing a-Class and Non-Memory Reference Format a-Class and Others a-Class Operations Analog-To-Digital Converter AFOl-A Analog Inputs Analog Inputs, Equipment Analog Knobs and Power Switch Panel Analog-To-Digital A-D Converter Controls Analog-To-Digital Converter AFOl-A Instructions, A-D Converter Sample and Hold Options, AFOl-A Specifications, AFOl-A A-D Converter ASR-33 Character Set Display Pattern Autoindexing, Extended Memory Programming Autoindexing, 8 Mode Auxiliary Scope Connector 6-82 1-3 5-9 6-78 6-78 3-35 3-6 4-21 4-2 3-3 3-6 3-4 3-5 3-3 3-3 6-76 6-76 6-81 3-6 3-6 3-6 3-14 6-76 1-5,3-35 1-1 2-8 6-76 6-78 6-76 6-78 6-81 6-76 3-34 4-21 4-4 1-5 BA 12 Peripheral Expander {3-Class Format {3-Class Instruction Format {3-Register {3-Register Indexing Block, (LINC tape) Block Number (BM) Break Field Register, Extended Memory 1-6 3-6 3-4 3-4 3-5 3-39 3-39 4-19 c Cable Connections, Front Panel Cable Connections to I/O Bus Cable Selection Card Readers Card Reader and Control CR12 CM12 Optical Mark Card Reader CM12 Optical Mark Card Reader Instructions Controls and Indicators CMl 2 Control or Indicator, CR12 Instructions, CM12 Optical Mark Card Reader Instructions, CRl 2 Card Reader Optical Mark Card Reader, CMl 2 Card Reader and Control CRl 2 Central Processor, Logic Description Accumulator (AC), Description Instruction Field Register (IF), 5-Bits Instruction Register (IR), 12 Bits Link (L) I Bit Memory Address Register (MA) 12 Bits Memory Buffer (MB), 12 Bits Mode Status Register 1 Bit Program Counter (PC) 12 Bits Central Processor, Major State Indicators Central Processor, Miscellaneous Indicators Central Processor, Register Indicators G-1 5-45 5-40 6-63 6-63 6-66 6-66 6-67 6-65 6-66 6-63 6-66 6-63 1-1 1-3 1-4 1-3 1-3 1-3 1-3 1-3 1-3 2-3 2-4 2-3 1-1 Character Displays Character Set Character Size Checksum (CM) Check Words (CW) Classic LINC CM12 Optical Mark Card Reader Controls and Indicators CM 12 Codes, Table of Combining Group 1 Operations Combined Operations: Group 1 Combined Skips In Group II Command Register, Contents, Magnetic Tape Configuration of, PDP-12 Connections, Front Panel Cable Connections, Interface Connections, I/O Bus Cable Connector Selection Console Controls and Indicators Console Key Functions Console Switches Console Toggle Switches Console Teletype Control Controls and Indicators Control Registers Continued Operations, Magnetic Tape Construction of Interfaces Converting ASCII Code to PDP-12 Teletype Conventions, Logic CRT Display Character Size CRT Display, Equipment CRT Display, Remote CRT Display, VR12 ASR-33 Character, See Display Pattern Character Displays Character Set DIS Display (a-Class) DSC Display Character ('3-Class) DSC Display Pattern for Half-Size Characters Point Displays CR12 Card Reader and Control CR12 Card Reader, Control or Indicator CRl 2 Card Reader Instructions Counter Register, KWl 2-A Current Address, Three Cycle Data Break 3-32 3-33 1-5,3-29 3-39 3-39 1-4 6-66 6-67 F-1 4-9 4-8 4-11 6-51 1-1 G-1 5-44 5-45 5-41 2-1 2-6 3-22 3-7 6-5 2-1 3-40 6-49 5-39 6-3,F-3 5-3 1-45 1-1 3-31 2-1,3-31 3-34 3-32 3-33 3-32 3-32 3-33 3-33 3-32 6-63 6-65 6-63 6-62 5-29 D Dataphone Control, Type DP12-B Dataphone Interface DP 12-B Data Break, Input Data Transfers Input Interface Logic Memory Increment Output Data Transfers Output Interface Logic Output Transfer Timing Request for Single Cycle Single Cycle Timing Three Cycle Three Cycle Timing 1-2 6-9 1-6 5-22 5-24 5-27 5-23 5-26 5-25 5-22 5-21 5-23 5-21,5-29 5-29 5-2,5-21 Data Break Transfers 5-24 Data Break Input Interface Logic Data Break Output Interface Logic 5-26 5-25 Data Break Output Transfer Timing 5-23 Data Break Single Cycle Timing 5-21 Data Break Transfer Interface 5-30 Increment CA Inhibit, Three Cycle Data Break 5-22 Input Data Transfers, Data Break 5-27 Memory Increment, Data Break 5-28 Memory Increment, Data Break Timing Output Data Transfers, Data Break 5-23 5-29 Three Cycle Data Break Three Cycle Data Break Timing 5-29 Word Count Overflow, Three Cycle Data Break 5-30 Data Break Transfer Interface 5-21 Data Break, Types of 5-21 Data Buffer DB 12-P, N 3-1 Data Field 1-4 Data Field in Memory 4-19 Data Field Register, Extended Memory 3-2 Data Field Reserved Locations H-1 Data, Mathematical Table 3-39 Data Path 1-5,3-35 Data Terminal 2-1 Analog Extension Panel 3-37 ATR AC to Relays 2-1 Clock Input Panel 3-36 Fast Sample 2-1 Power Switch Panel 2-7 Relay and Analog Input Panel 3-36 Relay Terminals and Corresponding AC Bits 3-37 RTA Relays to AC 3-36 SAM Sample 5-2 Data Transfers, see Programmed Data Transfers 5-10 Data Transfers, Input 5-11 Data Transfers, Output 5-6 Data Transfer Timing Data Words (DM, FM) 3-39 6-73 DB12-P, N Data Buffer 6-15 DC02-D Instructions 6-14 DC02-E Control Instructions DC02-E Multiple Teletype Control 6-13 6-16 DC02-F Multiple Teletype Control 6-17 DC02-F Instructions 54 Decoding, Instruction JOT 5-7 Device Selector DF/DS32, -D Random Access Disk File, Instructions 6-27 Digital-To-Analog 6-82 Digital-To-Analog AAOl-A 6-82 Digital-To-Analog AAOl-A 6-82 Direct Address 3-6 Direct Addressing 4-2 Direct Address Format of 3-3 DIS Display (a-Class) 3-32 Disable Teletype Interrupt 3-29 6-38 Disk Cartridge Memory, RK8/RK01 6-30 Disk Memory System, RF/RS08 643 Disk, RK.8-P, RK8-N, RK.01, RKOl-K Disk Storage 6-27 bF/DS32, -D Instructions 6-27 6-38 Disk Cartridge Memory, RK8/RK01 Disk Memory System, RF/RS08 Instructions, RF 3 2 to RF /RS08 Comparison Instructions, RK08/RKO1 Programming, Disk Software Programming, RK08/RK01 1/0 Subroutine Random Access Disk File, DF/DS32 and DF/DS32-D RF /RS08 Instructions RF /RS08 Programming, Example Specifications, RF /RS08 Specifications, RK9/RK01 Display Display Scope Controls Division Division of 24-bit numbers EAE Programming DM12 DSC Display Character ({3-Class) DSC Display Pattern for, DW08A I/O and Bus Converter 6-30 6-35 6-38 6-44 6-42 6-27 6-30 6-34 6-37 6-43 1-5 2-11 4-18 4-17 5-20 3-32 3-33 1-6 RIB Read Interrupt Buffer RIF Read Instruction Field RMF Restore Memory Field Program Interrupt, Extended Memory Programming, Extended Memory Register, Extended Memory Save Field Register, Extended Memory Extended Memory, 8 Mode see also LINC mode control Extended Operations Extended Operations Buffer Extended Operations, LINCtape Extended Tape Addressing Hold-motion No-Pause Program Interrupt Tape Interrupt with Core Extended Units External Level Lines External Skips 4-20 4-20 4-20 4-22 4-21 4-19 4-19 3-22 3-45 3-41 3-40 1-4 14 1-4 14 1-4 1-4 3-47 3-20 3-20 E 4-13 EAE Instruction Format 4-13 EAE Instructions 4-16 ASR Arithmetic Shift Right 4-16 ASR, Shift Path for 4-14 CLA Clear AC 4-15 DVI Divide 4-16 LSR Logical Shift Right 4-16 LSR, Shift Path for 4-14 MQA Place MQ in AC 4-14 MQL Load MQ from AC 4-15 MUL Multiply 4-15 NMI Normalize 4-15 NMI, SHL Shift Path for, 4-14 SCA Step Counter to AC 4-14 SCL Load Step Counter 4-15 SHL Shift Left 4-4 Effective Address, 8 Mode 3-3 Effective Addressing B-1 8 Mode Instructions D-1 8 Mode Perforated Tape Loader 3-8 End-around carry 3-46 Extended Address Format Extended Arithmetic Element, 4-16 Programming for 1-6,4-13 Extended Arithmetic Element (EAE), KEl 2 4-13 Extended Arithmetic Element, KE12 4-2,4-19 Extended Memory Addressing Combination of Extended 4-21 Memory Prograir·ming 4-21 Autoindexing, Extended Memory Programming 4-19 Break Field Register, Extended Memory 4-19 Data Field Register, Extended Memory Extended Memory, Calling A Subroutine 4-21 Across Fields Instruction Field Buffer, Extended Memory 4-19 4-19 Instruction Field Register, Extended Memory Instructions, Extended Memory 4-19 4-20 CDF Change Data Field CIF Change Instruction Field 4-20 RDF Read Data Field 4-20 F Fast Sample Field Address, Use of First Word Fixed Interval Clocks Format Routines Frequency Range, KWl 2-B,C Front Panel Cable Connections Full-Word Arithmetic Full-Word Comparison Full-Word Data Transfers Full-Word Instructions Full-Word Logic Functional Description, Magnetic Tape Control 3-29 3-2 3-42 6-25 6-7 6-26 G-1 3-8 3-12 3-7 3-7 3-11 6-45 G General Description, System PDP-12 Group I, Operate Class Instruction Format Group II, Combined Skips Group II, Operate Class Guard Word (GM) 1-1 4-7 4-11 4-9 3-39 H Half-Size Characters Half-Word Addressing, defined Hold-Motion, Extended Tape Addressing Hold Unit Motion 3-33 3-13,3-14 14 3-48 I I-Bit I-Bit, Octal Value I-Bit, 8 Mode Addressing Increment CA Inhibit, Three Cycle Data Break Incremental Plotter XYl 2 34 3-7 44 5-30 1-6 1-3 Incremental Plotter and Control Type XY12 Indexing, {3-Register Indicators & Controls Analog Knobs and Power Switch Panel Central Processor Major State Indicators Central Processor Miscellaneous Indicators Central Processor Register Indicators Console Key Functions Display Scope Controls Individual Console Toggle Switches Tape Processor Major State Indicators Teletype Model 33ASR Controls Toggle Switch Registers TU55 Tape Transport Controls and Indicators Indirect Address, /3-Class Indirect Addressing Input Data Transfers Input Data Transfers, Data Break Input/Output Bus Description Input/Output Facilities and Display, LINC mode, 1/0 Bus Analog Inputs Auxiliary Scope Connector Dataphone Interface DPl 2-B Data Terminal Display Extended Arithmetic Element (EAE) KEl 2 Incremental Plotter XYl 2 Input/Output 1/0 Bus Keyboard/Printer LINCtape Programmable Real-Time Interface KWl 2A Relay Buffer Sense Lines TTY Interface, DPl 2-A Input/Output Skip Input/Output Transfer Class Interaction between Modes Switching Interface Connections Interface Construction Interface Design and Construction Cable Connections to I/O Bus Cable Selection Connector Selection Construction of Interfaces Interface Connections Interface Modules IOT Allocations, Octal Module Cooling Module Layout Module Selection for Interface Circuit of Peripheral Equipment M-Series Flip Chip Modules M-Series Module Summary MlOl Bus Data Interface Ml 03 Device Selector Ml 11 /M906 Positive Input Circuit MS 16 Positive Bus Receiver Input Circuit M623/M906 Positive Output Circuit M660 Bus Driver Output Circuit Wiring Hints 1-4 6-68 3-5 2-3 2-8 2-3 2-4 2-3 2-6 2-11 3-7 2-4 2-14 2-6 2-12 3-6 3-3,4-3 5-10 5-16 3-22,5-1 1-5 1-5 1-5 1-6 1-5 1-5 1-6 1-6 1-6 1-6 1-5 1-6 1-5 1-5 1-6 5-8 4-12 1-5 5-44 5-39 5-30 5-45 5-40 5-41 5-39 5-44 5-30 5-43 5-43 5-40 5-32 5-34 5-35 5-33 5-33 5-30 5-31 5-31 5-32 5-32 Interface Modules 5-30 Interrupt, LINC mode, data path during 3-27 Interrupt, LINC Mode Service Routine 3-29 Interrupt OFF, IOF 4-13 Interrupt ON, ION 4-12 Interrupts, LINC Mode M 3-26 Instruction Decoding, IOT 54 Instruction Descriptions, see Instructions 3-7 Instruction Field 3-1 Instruction Field Buffer (IB) 3-24 Instruction Field and Data Field Registers 3-2 Instruction Field Register (IF), 5-Bits 1-4 Instruction Field Register, Extended Memory 4-19 Instruction Field Reserved Locations 3-2 Instruction Format 3-7,3-41 Instruction Format, Group II Operate Class 4-10 Instruction Formats, Direct Address, Indirect Address {3-Class, a-Class and others 3-6 Instruction Register (IR), 12 Bits 1-3 Instruction Set, 8 Mode 3-1,4-5,B-1 4-6 AND Logical And to AC CIA Complement and Increment AC 4-9 CLA Clear Accumulator 4-10 CLL Clear Link 4-7 CMA Complement Accumulator 4-7 CML Complement Link 4-8 DCA Deposit and Clear Accumulator 4-5 GLK Set Link 4-9 HLT Halt 4-11 IAC Increment Accumulator 4-8 ISZ Increment and Skip if Zero 4-6 JMP Jump 4-6 JMS Jump to Subroutine 4-6 LAS Load Accumulator from Switches 4-10 LINC Switch to LINC mode 4-12 NOP No Operation 4-7 OSR OR Switch Register with AC 4-11 4-8 RAL Rotate Accumulator Left 4-8 RAR Rotate Accumulator Right RTL Rotate Two Places Left 4-8 RTR Rotate Two Places Right 4-8 SKP Skip Unconditionally 4-10 SMA Skip on Minus AC 4-10 SNA Skip on Non-Zero AC 4-10 SNL Skip on Non-Zero Link 4-10 SPA Skip on Plus AC 4-11 STA Set Accumulator 4-9 STL Set Link 4-9 4-10 SZA Skip on Zero AC 4-10 SZL Skip on Zero Link TAD Two's Complement Add to AC 4-5 Instruction Trap 3-29 ,3-30 ,3-49 Instructions, A-D Converter 6-78 6-66 CMl 2 Optical Mark Card Reader 6-63 CRl 2 Card Reader 6-5 Console Teletype Control DC02-D 6-15 DC02-E 6-14 3-7 Descriptions DF/DS32, -D EAE Extended Memory Format Explanation of I/O Bus IOT LINC KP12 KW12-A KW12-B,C LP08 Line Printer LPl 2 Line Printer Magnetic Tape Control PC12, PP12 Paper Tape Readers and Punch PR12 Reader PT08 RF32 to RF /RS08 Comparison RF/RS08 RK08/RK01 Tape Maintenance Two-word XYl 2 Plotter IOB 1/0 Bus Enable IOB/IOT 1/0 Bus Access I/O Bus Cable Connections 1/0 Bus External Level Lines 1/0 Bus Instructions 1/0 Control 1/0 Handler, LINC-8 Simulator Trap Processor IOP Generation IOP Generation and Timing I/O Preset Pulse I/O Program Interrupt IOS, Multiple Inputs IOS and Program Interrupts, Mul.tiple Inputs IOT Allocations, Octal IOT Command Pulse Generation IOT Instruction IOT Instruction Decoding 6-27 4-13 4-19 3-7 C-1 14 3-1,3-6,A-1 6-74 6-22 6-26 6-60 6-59 645 6-71 6-72 6-11 6-35 6-30 6-38 E-1 1-4 6-68 3-23 3-25 1-4 5-45 3-20 C-1 5-4 1-4 5-5 5-6 3-29 5-11 5-13 5-13 5-43 5-7 1-4 14 J-K Keyboard Reader Keyboard/Printer KF12B KPl 2 Instructions KPl 2 Power Failure Option KPl 2 Power Fail/Restart KW12-A Input Panel KW 12-A Instructions KW12-A Real-Time Interface KW12-A with A-D KW12-B, KW12-C KW12-B, C Instructions 6-5 1-6 5-15 6-74 6-74 6-74 6-22 6-22 6-18 6-22 6-25 6-26 L LAP6-DIAL-MS LINC Instruction Trap LINC Mode Direct Access Devices 6-44 3-24 14 3-2,A-l LINC Mode Instructions Character Size 3-29 3-22 Console Switches 3-29 Disable Teletype Interrupt Fast Sample 3-29 Full-Word Arithmetic 3-8 Full-Word Comparison 3-12 Full-Word Data Transfers 3-7 Full-Word Instructions 3-7 ADA Add to Accumulator (.6-Class) 3-9 ADD Add to Accumulator 3-8 ADM Add to Memory (.6-Class) 3-9 APO Accumulator Positive 3-19 AZE Accumulator Zero 3-19 BCL Bit Clear {/3-Class) 3-11 BCO Bit Complement (.6-Class) 3-12 BSE Bit Set (.6-Class) 3-11 CLR Clear 3-21 COM Complement AC 3-21 DJR Disable JUMP Return 3-28 ESF Enable Special Functions 3-30 FLO Overflow 3-20 HLT Halt 3-21 IBZ LINCtape Inter-Block Zone 3-20 IOB-IOF Interrupt Off 3-26 3-26 IOB-ION Interrupt On IOB-RIB Read Interrupt Buffer 3-27 IOB-RDF Read Data Fielr:l 3-26 IOB-RIF Read Instruction Field 3-25 IOB-RMF Restore Memory Fields 3-27 JMP Jump 3-15 KST Key Stuck 3-21 LAM Link Add to Memory (.6-0ass) 3-9 3-8 LDA Load Accumulator (.6-0ass) 3-25 LDF Load LINC Data Field Register LDH Load Half 3-14 LIP Load LINC Instruction Field Buffer 3-24 LINC Switch to the LINC Mode (see PDP) 3-22 LSW Left Switches 3-22 3-19 LZE Link Zero MUL Multiply (.6-Class) 3-10 NOP No Operation 3-21 PDP Switch to the 8 Mode 3-22 QAC Place MQ in AC 3-21 QLZ MQ Low-Order Bit Zero 3-19 ROL Rotate Left 3-16 ROR Rotate Right 3-17 RSW Right Switches 3-22 SAE Skip if Accumulator Equal to Operand (.6-Class) 3-12 SCR Scale Right 3-18 SET Set a-Register 3-14 SPA Place Special Function Flip-Flops in AC 3-30 SHD Skip if Half Differs 3-14 SKP Skip Unconditionally 3-20 SNS Sense Switch 3-20 SRO Skip and Rotate (ft-Class) 3-13 STA Store Accumulator (.6-Class) 3-8 STC Store and Clear (Direct Address) 3-7 STH Store Half 3-14 SXL Skip on External Level 3-20 XSK Index and Skip 3-15 1-5 Full-Word Logic Half-Word Addressing, defined LINC Mode I/O Bus Access LINC Mode IOT Instructions LINC Mode, Memory Modules LINC Mode Programming LINC Mode Program Interrupt LINC Mode Provisions of LINC Switch to LINC Mode LINCtape, Equipment Required LINCtape Formats LINCtape Instructions LINCtape Option, TC12-F LINCtape Processor Information Paths LINCtape Programming LINCtape Registers LINCtape Transport, Type TU55 LINCtape TCl 2 Block (LINCtape) Block Number (BM) Check Words (CM) Checksum Control Registers Data Path Data Words (DM, FM) Extended Address Format Extended Operations Extended Operations Buffer Extended Units First Word Guard Word (GM) Hold Unit Motion Instruction Format LINCtape Instructions AXOAC to XOB CHK Check One Tape Block IOB-LMR Load Maintenance Register MTB Move Toward Block RDC Read and Check RDE Read Tape RDG Read and Check Group STD Skip if Tape Done TAC Tape Accumulator to AC TMA Load TMA Setup Register TWC Skip on Tape Word Complete XOAXOBto AC WCG Write and Check Group WRC Write and Check WRI Write Tape LINCtape Processor Information Paths LINCtape Programming Maintenance Mode Mark Condition No Pause Condition Organization of Data Organization of LINCtape Data, Schematic Read/Write Buffer (RWB) Reverse Block Number (RBM) Second Word Subprocessor, LINCtape Tape Accumulator (TAC) Tape Block Number (TBN) 1-6 3-11 3-13,3-14 14 3-25 14 3-1 3-26 1-4 4-12 1-1,1-5 3-37 3-43 6-57 3-40 3-41 3-39 2-1 3-37 3-39 3-39 3-39 3-39 3-40 3-39 3-39 346 3-45 3-41 3-47 3-42 3-39 348 341 3-43 3-46 3-45 3-48 3-45 3-43 3-43 343 3-48 3-45 3-46 349 346 3-44 3-44 344 340 3-41 3-49 3-48 3-48 3-37 3-38 3-39 3-39 3-42 3-39 340 341 Tape Buffer (TB) Tape Interrupt Enable Tape Memory Address (TMA) Tape Motion Tape Trap Tape Word Skip LINC-8, Comparison with PDP-12 LINC-8 Programs LIN C-8 Program Changes Line Printers Instructions, LP08 Line Printer Instructions, LPI 2 Line Printer Line Printer and Control LP08 Line Printer and Control, LPI 2 LP08 Line Printer Specifications Line Printer and Control LP08 Line Printer and Control, LPI 2 Link Link (L) I Bit Logic Conventions Logic Symbols, Figure 5-1 LP08 Line Printer and Control LP08 Line Printer Instructions LP08 Line Printer Specifications LP12 Line Printer and Control LPl 2 Line Printer Instructions LT37-AD Option, Teletype 340 3-47 341 342 349 3-49 1-1 3-31,349 14 6-59 6-60 6-59 6-60 6-59 6-62 6-60 6-59 3-8,3-9 1-3 5-3 5-3 6-60 6-60 6-62 6-59 6-59 6-4,F-3 M Magnetic Tape Command Register Contents, Magnetic Tape Continued Operations, Magnetic Tape Functional Description, Magnetic Tape Control General Description, TU20C Instructions, Magnetic Tape Control LINCtape Option, TC12-F Magnetic Tape Control, TC58 Magnetic Tape Functions Magnetic Tape Transports Magnetic Tape Transports, TU20 (7 Channel, 9-Track) Magnetic Tape Transport, TU20C Magnetic Tape Control, TC58 Magnetic Tape Control Instructions Magnetic Tape Functions Magnetic Tape Transports Magnetic Tape Transports, TU20 (7 Channel, 9-Track) Magnetic Tape Transport, TU20C Maintenance Mode Mark Condition MARK 12 Program Mathematical Tables Maximum Data Rates PT08 Memory Address Control Memory Addressing Methods Autoindexing, 8 Mode Direct Addressing Indirect Addressing Memory Reference Instruction Format Summary Addressing Methods, 8 Mode, Table of 6-45 6-51 6-49 6-45 6-56 6-45 6-57 6-45 6-47 6-54 6-54 6-56 6-45 6-45 6-47 6-54 6-54 6-56 3-49 3-48 3-48 H-1 6-13 3-24 4-2 4-4 4-2 4-3 4-3 4-4 Memory Address Register (MA) 12 Bits Memory Buffer (MB), 12 Bits Memory Control Programming Memory, Description, Organization of, Segments of, Pages of Memory Extension Control Memory Increment, Data Break Memory Increment Data Break Timing Memory, Organization of Memory Reference Instructions Memory Size, PDP-12 Microprograrnma ble Microprograrnmable EAE Instructions Microprogramming Operate Class Group II Mode Control Mode Control, from 8 to LINC Mode Programming, Extended Memory Organization of Memory, 8 Mode Page 0 Mode Status Register 1 Bit Model 33ASR, Teletype Model 33KSR, Teletype Model 35KSR, Teletype Model 37KSR, Teletype Modes of Operation, LINC and 8 Module Cooling Module Layout Module Selection for Interface Circuits of Peripheral Equipment M-Series Module Summary Multiplication of 12-bit Numbers EAE Programming M-Series Flip-Chip Modules M101 Bus Data Interface MI 03 Device Selector Ml 11/M906 Positive Input Circuit M516 Positive Bus Receiver Input Circuit M623/M906 Positive Output Circuit M660 Bus Driver Output Circuit M706 Receiver, Teletype Control M707 Transmitter, Teletype Control Multi-Level Automatic Priority Interrupt Multiple Teletype Control DC02-E Multiple Teletype Control, DC02-F Multiple Use of IOS and Program Interrupt Multiplication 1-3 1-3 3-24 1-4 4-19 5-27 5-28 3-1 4-1,4-3,4-5 1-1 4-7 4-13 4-9 3-22 4-12 4-1 4-2 4-2 4-1 1-3 6-3 6-3 6-4 6-4 1-1 5-43 5-40 4-17 5-34 5-33 5-33 5-30 5-31 5-31 5-32 6-5 6-5 5-15 6-13 6-16 5-14 4-16 1-5 3-48 1-4 0 Operands Operate Class: Group I Operate Class: Group II Operate Class Instructions Operation of EAE Operating Modes Character Size, CRT Display 1-5 1-4 1-4 1-5 1-4 1-4 1-5 1-4 4-12 6-66 6-1 3-37 3-38 4-2 3-1 3-2 3-2 3-2 3-2 3-2 3-2 5-11 5-23 3-8 p 5-32 5-35 N Non-Bus I/O Devices No Pause Condition No Pause, Extended Tape Addressing CRT Display, Character Size Extended Tape Addressing with Core, Tape Interrupt, Program Interrupt, No-Pause, Hold-motion Hold-Motion, Extended Tape Addressing Interaction between Mode Switching I/O Bus Access No-Pause, Extended Tape Addressing Special Functions, LINC Programming Tape Interrupt, Extended Tape Addressing Operation, Program Interrupt Optical Mark Card Reader, CM 12 Option Groupings, Peripheral Devices Organization of Data Organization of LINCtape Data, Schematic Organization of Memory, 8 Mode Organization of Memory, General Data Field Reserved Locations Field Address, Use of Instruction Field and Data Field Registers Instruction Field Reserved Locations Program Counter, LINC mode Reserved Field Address, 8 and LINC mode Output, Data Transfers Output, Data Transfers, Data Break Overflow, defined 3-3 4-7 4-9 4-6 4-13 1-4 1-5 Page 0 Pages, Memory Paper Tape Punch and Reader PC12 Paper Tape Instructions, PCl 2, PPl 2 Paper Tape Readers and Punch Paper Tape Punch and Reader PC12 PCl 2 Paper Tape Punch and Reader PC12, PP12 Instructions PDP-8 Options used with PDP-12 Perforated Tape Loader Peripheral Devices Peripheral Equipment requirements of Peripheral Expander, BA 12 Peripheral Status Testing Point Displays PPl 2 Paper Tape Punch Prewired, Optional Groupings Power Fail/Restart Instructions, KP 12 KP 12 Power Fail/Restart KP12 Power Failure Option Program Control Program Counter, LINC mode Program Counter (PC) 12 Bits Program Interrupt Program Interrupt, see LINC Mode and 8 Mode Programming Programmed Data Transfers Conventions, Logic Data Break Transfers Logic Symbols 4-1 4-1 6-71 6-71 6-71 6-71 6-71 6-71 6-1 D-1 6-1 5-4 6-1 5-9 3-32 6-71 6-1 6-74 6-74 6-74 6-74 3-15 3-2 1-3 4-12,5-12 5-2 5-3 5-2 5-3 1-7 Program Interrupt 5-2 Signal Names 5-2 5.4 Programmed Data Transfers and I/O Control 5.9 Accumulator, 1/0 Transfers Data Transfer Timing 5-6 5-10 Data Transfers, Input 5.7 Device Selector Input Data Transfers 5-10 5-8 Input/Output Skip IOS and Program Interrupt 5.13 Multiple Inputs 5.7 IOT Command Pulse Generation IOT Instruction Decoding Multiple Use of IOS and Program Interrupt 5-14 Output Data Transfers 5-11 5.9 Peripheral Status Testing 5.5 Programmed Data Transfer Interface Diagram Programmed Data Transfer Timing 5-6 5-11 Programmed Interrupt, 1/0 5-6 Timing and IOP Generator 4-12 Program Interrupt 4-13 IOF Interrupt Off 4-12 ION Interrupt On Program Interrupt, Using the 4-13 4-22 Program Interrupt, Extended Memory Programming Program Interrupt, Extended Tape Addressing 1-4 3-26,4-13 Program Interrupt LINC mode 5.13 Program Interrupt, Multiple Inputs 5-12 Program Interrupt Request 4-13 Program Interrupt, Using the 1-6 Programmable Real-Time Interface KW12A Programmed Data Transfers description of 5-1 5.5 Programmed Data Transfer Interface Diagram Programmed Data Transfer Timing 5-6 5-11 Programmed Interrupt, 1/0 Programmed Interrupt and Instruction Trap 3-31 Programming 6-44 Disk Software 4-16 EAE 4-21 Extended Memory 6-7 Format Routine, Teletype 3-1 LINC Mode 6-10 PT08 6-42 RK8/RK01 1/0 Subroutine 6-7 Teletype 4-1 8Mode 6-72 PR12 Paper Tape Reader 6-72 PR12 Paper Tape Reader Instructions PT08 Equipment Configuration 6-11 PT08 Instructions 6-11 PT08 Programming 6-10 PT08 Specifications 6-10 Q-R Random Access Disk File, Types DF/DS32 and DF/DS32-D Read/Write Buffer (RWB) Real Time Clocks Counter Register, KW12-A Frequency Range, KW12-B, C Input Synchronizers, KW12-A I-8 6-27 3.39 6-18 6-22 6-26 6-19 KW12-A Input Panel KWl 2-A Instructions KW12-A with A-D KW12-B, KW12-C KW12-B, C Instructions Real Time Interface, KW12-A Register, Extended Memory Relays Relay Buffer Equipment Description Relay Terminals and Corresponding AC Bits Reserved Field Address, 8 and LINC Mode Reverse Block Number (RBM) RF /RS08 Disk Memory System RF /RS08 Instructions RF /RS08 Programming, Example RF /RS08 Specifications RK08/RK01 Disk Cartridge Memory RK08/RKO1 Instructions RK08/RK011/0 Subroutine Programming Example RK08/RKO1 Specifications 6-22 6-22 6-22 6-25 6-26 6-18 4-19 3-36 1-1, 1-5 3-36 3-2 3.39 6-30 6-30 6-34 6-37 6-38 6-38 6-43 6-43 s Sample and Hold Options AFOlA Save Field Register, Extended Memory Save Field Register, purpose Scaling, defined, see Shift and Rotate Operations Second Word Sense Lines Shift and Rotate Operations SHL, NMI Shift Path for Signal Names Sign-bit Single and Dual TTY Control, Type PT08 Teletype Control Single Teletype Control Type DP12-A Skip, defined Skip Instructions Skip loop programming example Skips external Skips, Miscellaneous Special Functions, LINC mode Special Functions, LINC programming Specifications, AFOl-A A-D Converter Specifications, DC02-E Specifications, RF /RS08 Specifications, RK08/RK01 Stand Alone Peripherals, list of Standard Mode Addressing, LINCtape Standard Mode, LINCtape Status or Error Conditions, Magnetic Tape Subprocessor, LINCtape Summary Addressing Methods, 8 Mode Table of Symbols and Abbreviations System Configuration Analog Inputs, Equipment CRT Display, Equipment LINCtape, Equipment Required Relay Buffer, Equipment Description 6-81 4-19 3-24 3-16 3-42 1-5 3-16 4-15 5-2 3-8 6-10 6-9 3-19 3-19 3-23 3-20 3-21 3-29 1-5 6-76 6-14 6-37 6-43 6-2 3-42 3-40 6-49 3.39 4-4 1-6 1-1 1-1 1-1 1-1 1-1 T Table of Codes Tape Accumulator (TAC) Tape Block Number (TBN) Tape Buffer (TB) Tape Interrupt Enable Tape Interrupt, Extended Tape Addressing Tape Maintenance Instructions Tape Motion Tape Memory (TMA) Tape Processor Major State Indicators Tape Trap Tape Word Skip TC12-F LINCtape Option TC58 Instructions TC58, Magnetic Tape Control Teleprinter/Punch Teletype Code, discussion Teletype C-onsole Teletype Control Dataphone Control, DPl 2-B DC02-D Instructions DC02-E Control Instructions Format Routines Instructions, Console Teletype Control Instructions, PT08 Keyboard Reader LT37-AD Option, Teletype Maximum Data Rates, PT08 Model 33ASR, Teletype Model 33KSR, Teletype Model 35KSR, Teletype Model 37KSR, Teletype Multiple Teletype Control, DC02-E Multiple Teletype Control, DC02-F Option Groupings, Peripheral Devices Prewired, Optional Groupings Programming the PT08 F-1 3-40 341 340 3-47 1-4 E-1 3-42 341 2-4 3-21,3-31,3-49 3-49 6-57 645 6-45 6-7 6-3 6-3 6-5 6-9 6-15 6-14 6-7 6-5 6-11 6-5 6-4 6-13 6-3 6-3 6-4 64 6-13 6-16 6-1 6-1 6-10 PT08 Equipment Configuration PT08 Specifications Single Teletype Control, DP12-A Specifications, DC02-E Stand Alone Peripherals, List of Teleprinter/Punch Teletype Controls Teletype Interface, DP12-A Teletype Model 33ASR Controls Teletype, Subroutine Ten Bit indexing, Program Counter Three Cycle Data Break Three Cycle Data Break Timing Timing and IOP Generator Toggle Switch Registers Transfer Class, Input/Output Transfers, Data Break Transports, Magnetic Tape Turnaround State, Tape TU20 Magnetic Tape Transport, General Description TU20C Magnetic Tape Transport TUSS Tape Transport Controls and Indicators TUSS/56 Tape Transports Two-Word EAE Instructions Two-Word Instruction 6-11 6-10 6-9 6-14 6-2 6-7 64 1-6 2-1,2-14 6-7 3-2 5-29 5-29 5-6 2-6 4-12 5-15 6-54 3-42 6-54,6-56 6-56 2-12 1-5 4-14 1-4 U-V-W Wiring Hints Word Count Overflow, Three Cycle Data Break 5-42 5-30 X-Y-Z XY Plotters Incremental Plotter and Control, XY12 Instructions XY 12 Plotter 6-68 6-68 6-68 1-9 PDP-12 COMPUTER SYSTEM REFERENCE MANUAL D EC-12-SRZB-D READER's COMMENTS Digital Equipment Corporation maintains a continuous effort to improve the quality and usefulness of its publications. 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