DEC 15 H2EB D PDP Module Manual
DEC-15-H2EB-D PDP-15 Module Manual DEC-15-H2EB-D PDP-15 Module Manual
User Manual: DEC-15-H2EB-D PDP-15 Module Manual
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Digital Equipment Corporation
Maynard, Massachusetts
PDP-15 Systems
Module Manual
DEC-lS-H2EB-D
PDP-15
MODULE MANUAL
DIGITAL
EQUIPMENT
CORPORATION • MAYNARD, MASSACHUSETTS
1st Edition July 1970
2nd Printing November 1970
3rd Printing {Rev} November 1972
Copyright© 1970, 1972 by Digital Equipment Corporation
The material in this manual is for informational purposes and is subject to change without
notice.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
PDP
FOCAL
COMPUTER LAB
PDP-15 FAMILY OF MANUALS
SOFTWARE
HARDWARE
INSTALLATION
MANUAL
ACCEPTANCE
TEST
PROCEDURES
OPERATORS
GUIDE
INTERFACE
MANUAL
UTILITY
PROGRAMS
MANUAL
..
...-.
MAN UFACTURERS
EQUIPMENT
MANUALS
MACRO -15
FORTRAN Ill:
FOCAL-15
8/15
TRANSLATOR
NOTE:
New manuals will be added
as they are developed.
*
15-0040
SYSTEMS REFERENCE MANUAL - Provides overview of PDP-IS hardware and software systems and
options, instruction repertoire, expansion features,
and descriptions of system peripherals.
(DEC-IS-BRZD)
USER'S HANDBOOK VOLUME 1, PROCESSORPrincipal guide to system hardware includes system
and subsystem features, functional descriptions,
machine-language programming considerations,
instruction repertoire, and system expansion data.
(DEC-IS-H2DC-D)
PDP-IS/40 DlSK-ORIENTED BACKGROUND/
FOREGROUND MONITOR SOFTWARE SYSTEM
- Describes Background/Foreground Monitor in
disk-oriented environment; programs include language, utility, and application types.
(DEC-IS-MR4A-D)
MAINTENANCE MANUAL VOLUME 1, PROCESSOR - Provides block diagram and functional theory
of operation of the processor logic; lists preventive
and corrective maintenance data. (DEC-IS-H2BB-D)
VOLUME 2, ENGINEERING DRAWINGS -Provides engineering drawings and signal glossary for
the basic processor and options. (DEC-IS-H2BB-D)
VOLUME 2, PERIPHERALS - Features functional
descriptions and programming considerations of
peripheral devices. (DEC-IS-H2DC-D)
OPERATOR'S GUIDE - Lists procedural data, including operator maintenance, for using the operator's console and the peripheral devices associated
with PDP-IS Systems. (DEC-IS-H2CB-D)
INST ALLA TION MANUAL - Provides power specifications, environmental considerations, cabling, and
other information pertinent to installing PDP-IS
Systems. (DEC-IS-H2AB-D)
PDP-IS/IO SYSTEM USER'S GUIDE - Features
COMPACT and Basic 1/0 Monitor operating procedures. (DEC-IS-GGIA-D)
ACCEPTANCE TEST PROCEDURES - Lists stepby-step procedures designed to insure optimum
PDP-IS Systems operation.
PDP-IS/20 SYSTEM USER'S GUIDE - Lists Advanced Monitor System operating procedures.
(DEC-IS-MG2B-D)
PDP-IS MODULE MANUAL - Provides characteristics, specifications, timing and functional descriptions
of modules used in PDP-IS Systems.
(DEC-IS-H2EB-D)
BACKGROUND/FOREGROUND MONITOR
SYSTEM USER'S GUIDE - Lists operating procedures for the DEC tape and disk-oriented Background/Foreground monitors. (DEC-lS-MG3A-D)
INTERFACE MANUAL - Provides information for
interfacing devices to a PDP-IS System.
(DEC-IS-HOAC-D)
PDP-IS/IO SOFTWARE SYSTEM - Describes COMPACT software system and Basic 1/0 Monitor
System. (DEC-IS-GR lA-D)
UTILITY PROGRAMS MANUAL - Provides utility
programs common to PDP-IS Monitor Systems.
(DEC-IS-YWZA-D)
PDP-IS/20/30/40 ADVANCED MONITOR SOFTWARE SYSTEM - Describes Advanced Monitor
System; programs include system monitor language,
utility, and application types; operation, core organization, and input/output operations within the
monitor environment are discussed.
(DEC-IS-MR2B-D)
MACRO-IS - Provides MACRO assembly language
for the PDP-IS. (DEC-IS-AMZA-D)
FORTRAN IV - Describes PDP-IS version of the
FORTRAN IV compiler language. (DEC-IS-KFZB-D)
PDP-IS/30 BACKGROUND/FOREGROUND
MONITOR SOFTWARE SYSTEM - Describes Background/Foreground Software System including the
associated language, utility, and applications program.
(DEC-IS-MR3A-D)
FOCAL-IS - Describes an algebraic interactive compiler level language developed by Digital Equipment
Corporation. (DEC-lS-KJZB-D)
iv
List of Modules
Al24
A222
A40S
A607
A708
A877
G08S
GIOO
G222
G223
G28S
G286
G290
G613
G614
G681
G711
G77S
G821
G822
G823
G82S
G827
G829
G8S8
K303
MOO2
MIOI
MI03
MI04
Mill
MI12
MI13
MilS
MI17
MI19
MI21
MI27
MI29
MI33
MI3S
MI39
MI49
MIS9
MI61
MI62
MI64
MI82
MI91
Analog Multiplexer
Selectable Gain Amplifier
Sample and Hold Amplifier
lO-Bit D/A Converter, Single Buffered
Dual Voltage Regulator
Analog-to-Digital Converter
Disk Read Amplifier
Sense Amplifier and Inhibit Driver
Memory Selector
Read/Write Driver
Series Switch
Center Tap Selector
Writer Flip-Flop
X Diode Matrix
Y Diode Matrix
Track Matrix
Terminator Board
Indicator Panel
+SV Regulator
-6V Regulator
-24V Regulator
-24V Pass Element
Power Sequence Detector and Delays
Power Connector
Teletype@ Connector
Timer
Logic I Source
Bus Data Interface
Device Selector
I/O Bus Multiplexer
Inverters
NOR Gates
NAND Gates
NAND Gates
NAND Gates
NAND Gates
AND/NOR Gates
AND/NOR Gates
AND/NOR Gates
NAND Gates
NAND Gates
NAND Gates
NAND-Wired OR Matrix
4-Bit Arithmetic Logic Unit
Binary-to-Octal/Decimal Decoder
Parity Circuit
6-Bit Parallel Adder
Parity Circuit
Carry Look-Ahead Generator
~eletype is a registered trademark of Teletype Corporation.
v
List of Modules (Cont)
M205
M206
M207
M2ll
M2l2
M2l4
M216
M2l8
M2l9
M223
M226
M227
M238
M240
M242
M248
M302
M3ll
M3l2
M40l
M402
M420
M452
M500
M5l0
M5l5
M602
M606
M6ll
M6l7
M62l
M622
M627
M628
M632
M706
M707
M7l7
M770
M77l
M772
M773
M775
M776
M90l
M902
M904
M909
M910
D Flip-Flops
D Flip-Flops
Flip-Flop
Binary Up/Down Counter
6-Bit Left/Right Shift Register
Data Storage Register (6-Bit)
D Flip-Flops
MQ Register (9-Bit)
Step Counter and Control
MA and MB Register (4-Bit)
Register (7-Bit)
AC Shifter (9-Bit)
Synchronous Up/Down Counter
R-S Flip-Flops
J-K Flip-Flops
Right Shift Parallel Load Register
Dual Delay Multivibrator
Tapped Delay Lines
Delay Lines
Variable Clock
Photo Mod Clock
Phase-Lock Clock
Variable Clock
Converter-I/O Bus Receiver
I/O Bus Receiver
Real Time Clock
Pulse Amplifiers
Pulse Generators
High-Speed Power Inverters
Power NAND Gates
Data Bus Drivers
I/O Bus Drivers
NAND Power Amplifiers
Block-Bank Address Card
Converter-I/O Bus Driver
Teletype Receiver
Teletype Transmitter
Display Control VP 15
EAE Control
Internal lOT Decoder
Console Control No.1
Console Control No.2
Time State Generator
Reader Register
Flexprint@ Cable Connector
Terminator Card
Coaxial Cable Connector
Terminator Card
CP Terminator Card
vi
List of Modules (Cont)
M911
M912
M91S
M1701
M1713
WOlD
W028
W076
W714
W8S0
Memory Bus CP Terminator Card
I/O Bus Connector
Console Cable Connector
Data Selector
16-to-l Data Selector
Clamped Loads
Cable Connector for Levels and Pulses
Teletype Connector
Switches
I/O Connector
vii
General Description
This manual provides descriptions of modules used in the PDP-IS System and its associated peripherals. A
schematic diagram is included with each module description. Parts location diagrams are supplied for those modules that have numerous discrete components.
DEC builds three series of compatible below-ground logic (the B-, R- and S-series), two series of compatible aboveground logic (K- and M-series), an extensive line of modules to interface different types of logic (W-series), a line
of special-purpose modules (G-series), and a line of support hardware for its module line (H-series).
With few exceptions, the DEC below-ground logic operates with logic levels of ground to -O.3V (upper level) and
-3.2V to -3.9V (lower level), using diode gates that draw input current at ground and supply output current at
ground. Figure I shows the voltage spectrum of negative logic systems.
UPPER LEVEL
{
ov
-O.3V
-------
,
{ - 1.3V
INDETER MINANT _ 2.2V
LOWER LEVEL{ - 3.2V
- 3.9V
~---
15-0070
Figure I Voltage Spectrum of Negative Logic Systems
The compatible above-ground logic generally operates with levels of ground to +O.4V (lower level) and +2.4 to
+3.6V (upper level), using TTL or TTL-compatible circuits with inputs that supply current at ground and outputs that sink current at ground. Figure 2 shows the TTL logic voltage spectrum.
UPPER LEVE L {
+3.6V
+2.4V
INDETERMINANT {
+ 2.0V
+O.BV
LOWER LEVEL {+O.4V
OV
~----~
~b
15-0070
Figure 2 Voltage Spectrum of TTL Logic
A set of special modules designed to operate on the PDP- 15 I/O bus is also available. Figure 3 indicates the
voltage spectrum in which these special modules operate.
The use of DEC's Digital Logic Handbook is recommended for readers of this manual who are not familiar with
the basic principles of digital logic and the type of circuits used in DEC logic modules.
UPPE R LEVEL
t
2 8V
.
+2.0V
r--r--------
INDETE RMINANT t,·6V
+1.3V
LOWE R LEVEL
to.
----- - ---
BV
+O.4V
, 5- 0070
Figure 3 Voltage Spectrum for Positive PDP-I 5 I/O Bus Logic
MEASUREMENT DEFINITIONS
Timing is measured with the input driven by a gate or pulse amplifier of the series under test and with the output
loaded with gates of the same series (unless otherwise specified). Percentages are assigned with a percent indicating the initial steady-state level and 100 percent indicating the final steady-state level, regardless of the direction of change.
Input/output delay is the time difference between input change and output change, measured from 50 percent
input change to 50 percent output change. Rise and fall delays for the same module are usually specified separately.
Risetime and falltime are measured from 10 percent to 90 percent of waveform change, either rising or falling.
WADING
Input loading and output driving are specified in "units", with one unit equivalent to 1.6 rnA. The inputs to
low-speed gates usually draw I unit of load. High-speed gates draw 1.25 units, or 2 rnA.
PARTS LOCATION
A parts location diagram is provided for those modules that contain numerous discrete components and integrated circuits. The location of parts on integrated circuit modules can be determined by visual inspection and
circuit schematic reference.
"E" designators are assigned to integrated circuits according to the following convention: looking at the component side of the module, "E" numbers are assigned from right-to-Ieft within each horizontal row, starting with
the top row. Figure 4 illustrates this convention and typical symbols used in the parts location diagrams.
2
E4
E3
E2
EI
CRLJ
8
8
QD
E6
E5
@=rl
8-.
NOTE 2
lliIJi
lliIl NOTE
E8
E7
MXXX
NOTES
c::::::IJ Indicates diode palarity
2.
-{>I-.
E 9 is an integrated circuit operational amplifier.
15-0173
Figure 4 Sample Parts Location Diagram
3
A124
Analog Multiplexer
The A 124 Analog Multiplexer consists of four MOSFET switches and four driver gates used for selection of
single-ended analog inputs in the range of ± 10V. This module is also used for gain selection with the A222
Selectable Gain Amplifier in the ADI5 Analog Subsystem.
Isolated grounds are used in the module to help prevent program noise from causing analog signal acquisition
errors. Analog and logic grounds may differ by as much as 9V without malfunction.
Each drive consists of 2-bit input decoding and a common enable input. All inputs are
is removed.
INPUTS:
de~activated
Digital: Pin H (enable) presents I unit load; pins J, K, L, M, Nand P present
1/2-unit load each.
Analog: Pins R, S, T, and U - ±lOV normal, ±20V maximum.
OUTPUTS:
Analog: Pin V series resistance < 2200 ohms, 3 rnA max. load.
Response time to logic input change < 1.2 Jl,sec.
POWER:
+15V at pin D, 25 rnA
-20V at pin E, 30 rnA
+5V at pin A, 8 rnA
A124-1
when power
•
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
-20V,E,
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A222
Selectable Gain Amplifier
The A222 is a non-inverting operational amplifier with high input impedance. A precision voltage divider is connected between output and ground with taps at ratios of 1.0, 0.5, 0.25, and 0.125. This module is used with an
A124 Analog Multiplexer in the ADlS Analog Subsystem to provide computer-controlled gain selection in the
AD 15. An lOT instruction causes two AC bits to be transferred to an AD 15 buffer register. These bits are decoded by the A 124 to select one of four available gains: 1, 2, 4, or 8.
INPUTS:
Inverting input (pin S) - Connect to the desired feedback tap through a series
resistance of 3000 ohms or less (A 124 Analog Multiplexer).
Non-inverting input (pin P) - Gain of 1, 2, 4, or 8 ±.02% with .02% linearity error
over a ± 10V output range. Input impedance greater than 1000 megohms in parallel
with 10 pF. Protected against overload up to ±20V.
OUTPUTS:
Analog Input Range
Selected Gain
±1.2SV
±2.SV
±S.OV
±lO.OV
POWER:
8
4
2
+lSV, ±l%, 20 rnA, max. (Pin D)
-lSV, ±l%, 20 rnA, max. (Pin E)
A222-l
Output Selected
Pin V
Pin U
Pin T
Pin R
I
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.... _10< .... __.... _ .. __
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A708
Dual Voltage Regulator
The A 708 Dual Voltage Regulator is used in the AD IS Analog Subsystem to provide regulated -15V and +5V output voltages.
In the -15V regulator circuit, Q3 and Q4 control the forward bias on series regulator Q5 to maintain the -15V
output within ± I %. In the +5V regulator, any change in the +5V output is sensed at the base of Q2, which controls forward bias on QI to maintain the +5V output with ±5%.
INPUTS:
Less than 20 mV ripple.
-20V, ±I%, 0.25A max. Pin N2
+15V, ±I%, 1.25A max. Pin E2, V2
OUTPUTS:
-15V, ±0.5%, 0.2A max. Pin S2
+5V, ±I%, 1.2A max. Pin A2
A 708-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION
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INDICATED:
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• • •
DUAL VOLTAGE
REGULATOR
A 708
A877
Analog-to-Digital Converter
The A877 Analog-to-Digital Converter is used in the AD 15 Analog Subsystem to convert the A405 Sample and
Hold Amplifier output to a l3-bit digital word (12 bits plus a sign bit). A comparator amplifier compares the
analog input voltage with a programmed sequence of internally-generated reference voltages to determine the
polarity and amplitude of the input signal. The result is stored in a 13-bit data register. An AID DONE signal is
provided when the conversion is complete.
MAINTENANCE NOTE
The A877 uses special matched components to achieve specified
measurement accuracy. If a fault is isolated to the A877, do not
attempt to replace components in the field. Substitute a spare
module and return the faulty module to DEC for service.
ANALOG INPUT SIGNAL:
Full scale range: ± 10V
Connections: Single-ended
Impedance: 28K ohms
Overvoltage limit: ± I 5V, maximum
Settling time: I JIS
ENCODING PROCESS:
Digitalizing resolution: I part in 8,190 (2.5 mY)
Encoding word time: 36 JIS, typical
Encoding word rate: 28,000s, typical
Code: Parallel, binary 2's complement
MEASUREMENT ACCURACY:
Full range: 0.015%
Temperature coefficient: ±0.0020%tC (over full operating
temperature range)
CONTROL SIGNALS:
Input: Command to Convert (CTC) initiates encoding process
on a logic I-to-O transition
Output: End of Conversion (EOC) pulse is 100 ns logic I pulse
DATA OUTPUTS:
13 bits, held in storage until next CTC input.
POWER REQUIREMENTS:
+ 15V, ±5%, 100 rnA, typical, pin AD
-15V, ±5%, 50 rnA, typical, pin AE
+5V, ±IO%, 400 rnA, typical, pin BA
A877-1
CONNECTOR PIN ASSIGNMENTS
Pin
Function
Pin
Function
ADI/2
AEI/2
AFI/2
AJ2
AK2
AUl
BA2
BC2
BE2
BF2
BJ2
BK2
+15V
-15V
.±.l5V Common
Analog Input
Analog Return
Command to Convert (CTC)
+5V
Logic Ground
Sign Bit, Complemented
Sign Bit
Data Bit 2
Data Bit 3
BL2
BM2
BN2
BP2
BR2
BS2
BT2
BU2
BV2
BJl
BFI
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 8
Data Bit 9
Data Bit 10
Data Bit 11
Data Bit 12
Data Bit 13 (LSB)
End of Conversion (EOC)
ADJUSTMENT AND CALmRATION
NOTE
Do not attempt to adjust any potentiometers other
than the reference, gain, and zero adjust potentiometers at the rear of the module (see illustration).
Adjust the A877 while it is installed in slot Cil of the AD 15. Remove the A405 module and allow 15 minutes
warmup.
~RED TEST POINT (+IOV)
Reference Voltage Adjustment
Use Fluke 585A voltmeter (or equivalent voltmeter with
0.005% accuracy) to measure voltage between + 1OV test
point (red) and ground (black). Adjust reference potentiometer (top) to obtain 1O.000V, ±I mY.
c:::::J
REFERENCE
c:::::J
Gain Adjustment
GAIN
Connect EDC voltage standard (or equivalent voltage
standard with 0.005% accuracy) between pins CIIJ2 and
CIIF2 (See drawing D-AD-7007029-0-0 in ADI5 manual).
ZERO ADJUST
c:::::J
Run MAINDEC-I5-D6GA-D(D), with any channel and gain
setting. Adjust the EDC to find the most positive switchb B L A C K TEST POINT (GND)
ing point (007776-007777). Record the voltage. Reverse
the polarity of the EDC connections to find the most negative switching point. Record the voltage. The difference between the voltages should be 19.9995V, ±2 mY. Adjust the gain potentiometer and repeat these measurements until the difference is within the specified tolerance.
\1-0423
Zero Adjust
Short-circuit pins CIIJ2 and CIIF2 and note the conversion value. If the reading is outside the range 77776000002, adjust the zero adjust potentiometer (bottom) to bring it within range. This adjustment interacts with
the gain adjustment and several passes may be required to bring both adjustments within their specified tolerances.
A877-2
G08S
Disk Read Amplifier
The G08S Disk Read Amplifier is a double-height module consisting of an ac-coupled amplifier with a bandwidth
(-3 dB) from 20 kHz to approximately I MHz, followed by a slicer. The G08S module is used to detect and
amplify timing tracks and data signals for the RS09 DECdisk. The maximum voltage gain (under potentiometer
control) is approximately 60 dB (1000). Common mode rejection ratio is approximately 40 dB. The amplifier
is insensitive to any power supply ripple voltage less than 5 percent. Pin AM increases the gain by approximately
20 percent when its input is low. The nonrectified slice output is gateable, and the slice point can be varied by
logic inputs. A potentiometer is provided to adjust the slice. Pins at AT and AV are provided as amplifier test
points. Proper grounding is critical in this module. G08S ground pins should not be bussed. Pins AS and AC
should be connected to analog ground, and BF and BC should be connected to logical ground. All amplifier connections must be isolated from fast rise-time signals.
INPUTS:
Voltage levels are 0 and -3V, except at the input to pins AE and AF.
Pin
Function
AE,AF
AM
BU,BV
BS,BT
BP,BR
OUTPUTS:
Load or Input Voltage
Read Head Input
Read Gain Control
Read Slice Control
Read Slice Control
Enable Output
approx. IS mV peak-to-peak
2mA
2mA
2mA
2mA
Voltage levels are 0 and -3V except at AV, which provides +20V for the
timing track center taps.
Pin
Function
Drive
BE,BD
Signal Output
10 rnA
INPUT/OUTPUT DELAY: 120 ns
POWER DISSIPATION:
2W at +20V
I.5Wat-ISV
BP
BR
AM
BD
AE
AV
AF
BE
SLI CE
BS
BT
09-0357
BU
BV
G08S Disk Read Amplifier and Slice, Block Schematic
G08S-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSlS. THE
CIRCUITS ARE PROPtUETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION
! !!
R2
22K
R8
15K
904
!
R4
10K
RIO
4.64K
1/8W
1%
R9
100
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903
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4.64K
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215K
R20
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R21,R32 ARE POTS 76 PR I K HELITRIII
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R33
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R34
1.96K
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G100
Sense Amplifier and Inhibit Driver
The G I 00 module contains four sense amplifiers and four inhibit drivers. Five of these modules are used in the
PDP-IS for each 4K memory stack. (Refer to Engineering Drawings D-BS-MM 15-0-1 0 through D-BS-MM 15-0-15).
Each inhibit driver consists of a two-input NAND gate and a high-speed current switch. One driver is used for
each bit plane of the memory array. An inhibit signal is received by all inhibit drivers only during a write operation.
CORE
AD2 AC 1
STROBE
AKI
AH1
AVl (TEST POINT)
365m A
G I 00 Simplified Diagram
Each driver also receives a signal indicating the state of the corresponding bit in the MB. Inhibit drivers that receive a signal indicating a 0 state in the MB bit are gated on and cause inhibit current to be applied to the associated
bit plane of the memory array. Each inhibit driver employs a discharge network to speed up inhibit current cutoff. The output of the inhibit driver is connected to the middle of one core sensing string, which represents one
bit plane of the memory array. The balun network at the front end of the sense amplifier ensures equal current at
all times through both sides of the core string. In addition to the balun network, the sense amplifier consists of a
differential amplifier and output driver. One sense amplifier is used for each bit plane of the memory array. During a read operation only the signal induced on the sense winding of a core plane by a core-changing state is received by the differential amplifier. The differential amplifier has a nominal threshold of 17 mY. Output pulses
of standard amplitude and duration are supplied by the output driver when the sense amplifier reads a logic I from
the associated core, which in turn is strobed by a standard positive going pulse at ACI. Propagation delay from
the input to the sense amplifier to the buffered output is 25 ns (maximum) and from strobe input to buffered
output is 15 ns (maximum). These output pulses are used to direct set the MB register.
GIOO-l
The following are the input, output, and power characteristics of the G I 00 module.
INPUTS:
Inhibit driver DATA inputs present 1.25 TTL unit loads and INHIBIT inputs present 5 unit
loads. Sense amplifier inputs are 0-9 mV for a logic 0 and 31-35 mV for a logic I.
OUTPUTS:
POWER:
Inhibit driver inhibit current is 730 rnA.
Power dissipation of the G I 00 module is +5V at 130 rnA (maximum), -6V at 60 rnA
(maximum), and -24V at 800 rnA (maximum).
GlOO-2
This page intentionally left blank.
GIOO-3
I
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R24
75
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2
~
3
UNLESS OTHERWISE INDICATED:
DIODES ARE 0672
CAPACITORS ARE .01 MFD,IOCV, 20%
RESISTORS ARE 1/4W,5%
TRANSISTORS ARE DEC3639B
EI IS DEC74HOON
8KI
BLI
RI
750
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DI9
14
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TRANSFORMERS ARE 1609478
HOUSING IS DEC.,209482
INDUCTORS LI- L4 ARE 10MH
~
L-...
~
"",""
(GND)
BRI,BKI (-24V)
BPI,BLI
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G222-3
CD
0'>
0::
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G223
Read/Write Driver
The G223 module contains two read/write drivers. Two of these modules are used in the PDP-IS for each 4K
memory stack; one provides the drive for the X plane and the other provides the drive for the Y plane. (Refer to
Engineering Drawings D-BS-MMIS-O-6 and D-BS-MMI S-O-7.) The G223 and G222 modules work together (see
illustration) in that the current path selection through the core memory is established by the G222 modules, and
..
READ CURRENT
WRITE CURRENT - - - - - - - -
~
--I
+V
~
SOURCE
I
MA
1/2 G223
\..1
{ 1
SINK
r - - ----- -+Yl
II
I
II
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I
READ------~r---l~---------------- 1
--'!l~_________
L_
\.1,'
----=-----j~--+------+--+----f------*---
rl
SINK
tEAD
WRITE ____________
•
-'
I
I
1I
-v
I
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MA
15-0133
G223 Simplified Diagram
G223-1
the drive current for reading and writing is supplied by the G223 module. Reading and writing currents travel in
opposite directions. Each read/write driver consists of two input control NAND gates and two current switches
connected in series with a common output. The read and write commands and the page select command are applied to the input control NAND gates, turning on the corresponding current switches and establishing a current
path from ground to -24V. The balun network at the output of the driver ensures equality of input and output
current through the stacks at all times.
The following are the input and output characteristics of the G223 module.
INPUTS:
The READ and WRITE inputs (pins E I and F I) each present 1.25 unit loads. The pageselect input (pin D I) presents 2.5 unit loads.
OUTPUTS:
The measured read/write voltage waveform and its current waveform for the worst
case pattern take the form shown below for an 800 ns memory cycle time.
lOOns
-I V
-12V
VOLTAGE WAVEFORM
CURRENT WAVEFORM
15 - 0121
G223 Current and Voltage Waveforms
The current-rise time to get to 400 rnA for both reading and writing is approximately 100 ns, while the fall time
is 40 ns. The stagger time (Ts) between read and write currents is approximately 130 ns.
G223-2
This page intentionally left blank.
G223-3
•
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE ANO SHOULD BE TREATEO ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CDR.f>ORATION
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TITLE
Y DIODE MATRIX G614
EQUIPMENT
CORPORATION
S~E 1~~El
............ D . . . . . . . . C .. U . .'T . . .
F'RINTEDCIRCUITR[II
NUMBER
G614
-I) -
I
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I R~V
(--p I 9!)
032
0224
064
096
0128
0160
0192
063
095
0127
0159
0191
0223
062
094
0126
0158
0190
0222
061
093
0125
0157
0189
0221
0188
0220
0255
0254
031
060
092
0124
0156
D30
059
091
0123
0155
0187
0219
029
058
090
0122
0154
0186
0218
057
089
0121
0153
0185
0217
D28
0249
D25
D22
0252
0250
D26
023
0253
0251
D27
024
0256
056
055
054
088
087
086
0184
0216
0248
0151
0183
0215
0247
0118
0150
0182
0214
0246
D181
0213
D245
0120
0119
0152
D21
053
085
0117
0149
020
D52
D84
0116
0148
0180
D212
D244
019
D51
083
D115
0147
D179
D211
D243
D18
050
D82
D114
D146
D178
D210
D242
D17
049
D81
D113
D145
DI77
0209
D241
D240
D16
015
014
D13
D12
Dl1
Dl0
09
D239
048
D80
D112
0144
D176
D208
D47
D79
DIll
D143
0175
D207
D46
078
Dl10
D142
D174
D206
D45
D77
Dl09
D141
0173
D205
D44
D76
Dl08
D140
D172
D204
043
075
D107
D139
D171
D203
D42
D74
Dl06
D138
D170
D202
041
D73
0105
0137
D169
0201
06
D5
04
D3
D2
D237
0236
D235
D234
D233
D232
D8
07
0238
040
072
Dl04
0136
D168
D200
039
071
Dl03
D135
D167
D199
038
070
Dl02
D134
D166
D198
037
069
Dl0l
D133
D165
D197
D132
D164
D196
D36
D68
Dl00
D35
D67
D99
D131
D163
D195
D162
D194
D161
D193
Dl
034
D66
D98
D130
D33
D65
097
D129
D231
D230
D229
D228
D227
0226
D225
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G681,G711,G775
OECdisk Modules
1. G681 8 TRACK MATRIX
The G681 Track Matrix is a single-height board containing the resistors and diodes for eight DECdisk read/write
heads.
2. G711 RF08 TERMINATOR BOARD
The G711 RF08 Terminator Board is a single-height board containing IS terminating resistors that present lOOn
to ground at each input pin. This board must connect to the output cable slot of the last RS09 on each DECdisk
cable bus.
INPUTS:
lOon to ground
OUTPUTS:
None
POWER DISSIPATION:
Approximately 90 mW per terminator
3. G77S INDICATOR PANEL
The G77S Indicator Panel is a connector card that provides isolation for logic levels and allows these levels to
directly drive indicator bulbs without using light drivers. The connector is designed to be used with the indicator
panel, which supplies the necessary bias voltage.
INPUTS:
All inputs are 0 and -3V with 3 units of load each.
OUTPUTS:
The output connects a Flexprint cable to the indicator board.
POWER DISSIPATION:
ISOmW
G681, G711, G77S-1
THIS SCHEMATIC IS fUR",$HfD
CIRCUITS AfH PflOPIIIEUfl¥ IN
COPYRIGHT 1969 BY DIGITAL
M.'N1E"'ANrf PUAP(J"t~ IH[
llHAll(" ,o,lCORDINGLY
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I
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G821
+5V Regulator
The G821 module contains a voltage regulator with over-voltage, under-voltage, and over-current protection
circuits. This module supplies the regulated +5V in the memory of the PDP-IS. Combinational logic circuits are
also included in the module to provide lamp driver and memory power OK signals when the memory voltages are
within set levels. The input power connections to the module are made with an 8-pin mate-in-Iock connector at
the back of the module.
The following are the input and output characteristics of the G821 module.
INPUTS:
The inputs to the G821 module are +8V, +I IV, -15V, and ground. These voltages are supplied
by the 715 power supply. The module also receives positive level power OK signals from the
G822 and G823 modules.
OUTPUTS:
The outputs of the G821 module are variable 4.5V to 5.5V at 7A (maximum)* (when set at
5V, regulation is ±2% with a ripple voltage of 25 mV peak-to-peak); + II V at 1.0 amp (maximum) with the same regulation as the input voltage; and -15V at 3.0 amps (maximum) with
the same regulation as the input voltage.
----..,
CONNECTOR
+5V
CURRENT SENSING
t------------
BRI (MEM PWR OK)
>-------
BM 1
~--+--------------------~---------=---------- GND (AC2, AHL ___ _
SEE SCHEMAT IC)
'------~----------------------------------------- BMI (+ 11 V)
' - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AB2, AE 2, AF2 (-15 V)
G821 Simplified Diagram
*The 7A rating is valid only when adequate fan cooling is used. Without additional coding, the output rating is 2A (maximum). The +5V
potentiometer must be rotated clockwise to obtain a higher output voltage.
G821-1
Additional outputs include an open collector lamp driver (output pin BMl) that is turned
on when the SV power is within set limits (by rotating the voltage detection potentiometer
CCW, the low voltage limit decreases) and an open collector driver (output pin BRI) that is
turned on only when the SV power is not within set limits. Voltage limits are usually set at
4.7SV by the voltage detection potentiometer, while the upper voltage detection level is set
at S.SV.
G821-2
~
8
- f=-cHG89 [ 53
. A3M
M38V'/nN
[81I
3000 3ZIS
THIS SCHEMAT~C IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969
+5V
BY DIGITAL EQUIPMENT CORPORATION
• • • • • • •
•
R4
.1
5W
(+SEN)
ASI
D5
D672
2
I
3
I
I
I
4
+IIV
-.,
R 22
2.2K
5
o
I
I
7
I
80--1
I
>
330
RI3
L 5K
100
R8
330
C7
56MMF
100V
5%
•
CI
100MFD
20V
10%
BM2
C5
100
MFD
20V
10%
R24
330
R25
330
+
00
N
C2
R6
47
~C3
R23
330
DI
2N
-4441
Q8
T.15MFD
35V
10%
r
RI9
IK
RI5
IK
D4
IN748
3/4W
RI8
R7
47
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(,c..c."
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>
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III
0
OJ
(/) rr
Z
Q zoo
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t
DEC FORM NO
ORB 102
-15V
C9
10MFD
20V
10%
·· .. -<>'K
Ir\(")\/
UNLESS OTHERWISE INDICATED
PIN 7 ON EI=GND
PIN 14 ON EI=f-5V
EI IS DEC740lN
E2 IS LM300
CAPACITORS ARE IMFD ,35V, 10%
DIODES ARE D664
RESISTORS ARE 1/4W 5%
R3,R17 ARE POTS #76PR
TRANSISTORS ARE DEC3009B
CONVERSIO~ ~~~~T
II"
DEC
TRANSISTOR EIA
& DIODE
0664
0672
I N74BA
DEC3009B
OEC6534B
IN3606
IN36~3
SAME
2N3009B
MPS6534
t
]
DEC
2N2904
2N3055
I
'w,,"
:
,....
RI7
IK
GND
+1
AB2
AE2
AF2
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+
II
G ND
W
Ef:p'.'
R27
330
AN2
(- SEN)
R28
IK
Q
BPI -f-----{
'VV'v
L __ J
BRI
RI6
IK
-r~
BNI
1 6
1
330
+8V
1
I
R26 lrVK
G822
-6V Regulator
The G822 module contains a voltage regulator with an over-voltage protection circuit. This module supplies the
regulated -6V in the memory of the PDP-IS. A sensing circuit is also included on the module to provide a memory
power OK signal when the output is more negative than -6.5V.
The following are the input and output characteristics of the G822 module.
INPUTS:
The G822 module operates on II V input power from the 715 power supply.
OUTPUTS:
The outputs of the G822 module are:
INPUT
TABS
a.
variable -5.0 to -7.0V at I.SA. (When set at -6V, regulation is ±2% with a ripple
voltage of 50 mV peak-to-peak. The potentiometer must be rotated clockwise
to obtain a more negative voltage setting);
b.
variable 0 to -6.0V used as the threshold voltage for the G I 00 module. (This
voltage is nominally set at -3.8V. The potentiometer must be turned clockwise
to obtain a more negative voltage setting);
c.
BN I, which is a TTL output that drops to ground when the -6V output voltage is
more negative than -6.5V.
>-__.......________..-__......._______
-6V @ 1.5A MAX
BBl. BB2,BC1,BOl
REFERENCE
VOLTAGE
>-___
CROWBAR
CIRCUITRY
'--_-1,-
BNl
OETECTOR
...._ _ _ _ _ _ _ _ _ _ BV2 (TO G100)
'---________<10---------_----------
AC2,AB2, BTl
GNO
15-0130
G822 Simplified Diagram
G822-1
tI 1 A3~3
I - 0 - Z2 8
~38~nN
91 3ao~
S3 , 8
3ZIS
I
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
~ RI7
~~R18 +5'
AA2
3
~IK
?II\ B N I
_ 2~1
I E I p-----*-----
IK
07
TAB-
~
lei
RI
820
1/2W
+-r
10%
N
f f R21~ f~~
R22
820
1/2W
10%
68
IW
5%
R6
270
'V' -
5.IV
~
Ai!l
--.J-.. C5
--.+
R10
100
4.7K
+
•
4
5
T
·2
I
•
•
•
•
•
•
04
IN753A
t
~.Ol
--.J-..C6
.-
+
•
•
•
011
RI3
330
':.7
R9
?7.5 K
R4
5.6 K
•
3
-r--
~
•
BV2
CW
C4
...L.OI
MFD
100V
20%
02
BBI, BB2,
-6V
BCI,
BDI
010
01
DEC
3790
R8
N
TAB
*09
i----~----~---------------T----~~--,-----~----------t---~-----1--------
R2
2K
114M
35V
20%
N
-CP
02
DEC
2904
01
C2
68
M'FD
00
N
.03
~D672
IW
5%
f.--______---.-~
o
-..,- 'DB
RI4
330
,<",,1/05
MFD
100V
20%
'--"
+-
••
-rD5
.0664
>
•
•
~D6
RI5
330
.0664
•
GND
AC2, BTl
UNLESS OTHERWISE INDICATED;
DIODES ARE 0662
RES I STORS ARE 1/4W, 5%
CAPACITORS ARE 20MFD,50V,-IOt75%
TRANSISTORS ARE DEC6534B
EI IS DEC740 I
PIN 7 ON EI = GND
PIN 14 ON EI = +5V
DRN
(f) or U
Zo -
Q z
0
N
"'
,.,
000
(f)",
00
00
1:
WU 0 0 0
8
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~ ~I~
DEC FORM
DRB 102
NO.
~Jn.~
DATE
l'd'-0
~~L...2
!tN~O ~",-
12 fo 6'1
PROD
DATE
DATE
;0--'"
O:lsE!
,,,.
TRANSISTOR & DIODE CONVERSION CHART
DEC
EIA
0662
IN645
0664
IN3606
114M 5.IV Ai!l NONE
IN753A
SAME
2N4441
NONE
t
DEC
OEC65:3411
OEC2904
OEC3790
IN4733A
EIA
MPS6534
2N2904
2N 3790
SAME
TITLE
REGULATOR G822
~DmDDmD -6V
I I
EQUIPMENT
CORPORATION
""' ... YN ..... O. M ........ CHU.~TT.
5
SIZE
CODE
B
CS
NUMBER
G822-0- I
PRINTED CIRCUIT REV.
VI5i, 3;) ,/, I{ 3'-1.Jt35
1R~V
IFI I I I ILl
Pm//<.....
N
N
CD
l!l
i--
,.....-
G0008
GGGG0~ G
o
0
0
00
0
0
0
G
0
'
~
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>
v
0
z
>
v
0
z
>
c
N
C>
Z
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(\J
t,!)
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t,!)
I
I
I
I
~~~~,...-........,....-.....,,----......--.
. - - - + - - - - - - - - , L I
-30V
R5
825
1/8W
1%
NI
R6
7.2K
1/8W
.1%
R9
330
1/2W
t%
00
IV
RI
1.5K
W
N
+
UNLESS OTHERWISE INDICATED:
(-SEN)
VI
RI5
1.5K
81
05
",,,,999
RI6
4.7K
07
",,,,999
RIO
.300
RI4
5K
+
02
IN758A
03
IN750A
CAPACITORS ARE .01 ",FD
RESISTORS ARE 114W,5%
EI IS MCI709CG
AI
A2
R2
330
RI3
330
1/2W
04
DEC3790
1%
R8
909
1/8W
R3
180
RI2
330
1/2W
05
0671
R7
IK
1/8W
C'}
C4
(-24V)
RI
C2
RI7
7.5K
C3
I",FD
35V
CI
6.8",FD
35V
UI
(+SEN)
04
0662
+
C5
IMFD
35V
C2,TI,MI,GNO
02
DEC3009
02 (BUS)
TRANSISTOR & DIODE CONVERSION CHART
DEC
0662
0664
0611
I 75
rN750A
£lA
IN645
IN3606
IN36!53
SAME
SAME
DEC
MM999
DEC3790
DEC6534C
DEC3009
£lA
SAME
2N 3790
MPS6534
2N3009
mamaama
EQUIPMENT
CORPORATION
...... YN .... O ...... s
.... C .... U.ETT.
TlTLr-24V REGULATOR
CONTROL G823
000 0°0 00 0
8
0
80
80
.
UJ
•
o
G823-3
G825
-24V Pass Element
The G82S module contains the power stage of the -24V regulator, which is controlled by the -24V regulator
control module G823 to supply the regulated -24V for the memory of the PDP-IS. Refer to the description
of the G823 module.
G82S-I
THIS SCHEMATIC 15 FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCDROINGL Y
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
TAB
-30V
+
-"
." :::50MFD
50V
10%
~
02
AJ 2
BASE
~"
AV2
T.P
ABI
T.P
R3
1.5K
C')
00
N
VI
R2
.1
RI
.1
"" AV ',AR', BAI, BBI,BEI
SF ',BKI,BLI,BPI,BRI
- 24V
N
~ALI
~~~D
.r. AM I, AUI, BCI,BD\BHI
BJI, BM',BN',BSI,BUI
UNL.ESS OTHERWISE INDICATED:
RESISTORS ARE 5W, 5%
TRANSISTORS ARE DEC 3790-1
I
DRN
u"
w
Q:
l--
5t - -
""i'a.-
DATE
r-.2J"'"
~~~aI~ 1~:?~
~}".c....n.
PROD
'/."lil"i
DATE
TRANSISTOR & DIODE CONVERSION CHART
DEC
DEC3790
EI.
2N3790
DEC
EI.
mamaoma
TITLE
-24V PASS ELEMENT G825
EQUIPMENT SIZE
B
CORPORATION
....... " .... ~O. "'''SSACHV SETTS
I CS
CODE,
NUMBER
G825-0-1
PRINTED CIRCUIT REV
I
REV
JEtiJJJJJJ
G827
Power Sequence Detector and Delays
The G827 module contains a level detector, three RC networks, and an open-collector driver. This module is used
in the I/O processor of the PDP-IS. (Refer to Engineering Drawing D-BS-KPIS-O-S7.) The level detector is used
to detect a power-low condition in the 11 V supply and sequence the memory power off. The RC networks are
connected to the K303 timers to establish the timer delays, and the open-collector driver is used to energize the
memory power relay in response to the memory OK signal.
Power dissipation of the G827 module is SV at 144 rnA (maximum).
G827-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
/
10
4 IIV
_~•. -_ __
v
A
2~U
30-----,
AMP. SOCKET
1-480459
DECI209340
40
50
RI
IK
il8W
1%
•
L3.
E2
•
•
7
+
~
6
N
-...I
N
6~L
If
IIBW
70
r%
•
+5V
.---
Q2
DEC6534C
10
EI
1.
8~'~OO'r±~~, f j
f
~
....LC3
'1'2.2
MFD
20V
10%
T
R9
lOOK
R4
220
j
) 13
.---
:""'C2
.:T'IOMFD
20V
10%
12
3L-14
R2
1.21K
• R5
IK
g:64~
R3
330
C)
00
• R6
330
DI
D664~1:
RS
180K
10%
f
j
....l...C4
'I'.47MFD
35V
10%
R7
12K
f
j",,,
8"" MEM. RELAY
UNLESS OTHERWISE INDICATED
CAPACITORS ARE 100V,20%
RESISTORS ARE 1/4 WI 5%
PIN70NEI·GND
PIN 140N EI'+5V
EllS DEC 740lN
E2 IS MC 1709CG
DRN
q~
DATE
"'C"
l5""? ~,p. IZ'Z),H
I'1.T tz.-- ~~/6~
PROD
DATE
TRANSISTOR & DIODE CONVERSION CHART
DEC
EI'
0664
IN3606
DEC3009C
DEC6534
I:!N3009
MPS6534
DEC
EI'
momoomo
EQUIPMENT
CORPORATION
....... "."' ..... 0
...... S!l ... CHUSItTTS
POWER SEQUENCE DELAYS
AND DECODER G8 27
I
v~
I
88
00~G~0GG0
8
L
J
G827-3
G829
Power Connector
The G829 module is a power connector with over-voltage, under-voltage, and over-current protection circuits.
This module connects the +SV to the peripherals of the PDP-IS. Combinational logic circuits are also included
in the module to provide lamp driver and power OK signals when the peripheral voltages are within set levels.
Rotating the voltage detection potentiometer CCW lowers the low voltage limit. The potentiometer is normally
set to detect voltage below 4.7SV. The input power connections to the module are made with an 8-pin matein-lock connector at the back of the module.
The following are the input, output, and power characteristics of the G829 module.
INPUTS:
The inputs to the G829 module are +SV, +IOV, -ISV, and ground. These voltages are supplied by the 721 power supply. The module also receives positive power OK signals from
associated power supplies.
OUTPUTS:
The outputs of the G829 module are:
a.
+SVat lOA (maximum) with the same regulation as the input, +lOY at 2.SA (maximum) with the same regulation as the input, and -ISV at 3.SA (maximum) with the
same regulation as the input;
CONNECTOR
---l
<5V
I O---:-I-'---=--'---iL.._FU_S_E~I------1'--------'----- ~~~!~~_'!!'_~~_
SEE SCHEMATICS
2
OVER
VOLTAGE
DETECTION
I
30---'-1-'
UNDER
VOLTAGE
DETECTION
a
CROWBAR
4 0------'-+
5
I
GND
I
o--:---,~'-'-=-------------4o----t--_-----
BNI
I
I
I
> - - - - B R I (MEM PWR OK)
BPI
> - - - - BMI (LAMP DRIVER)
67:~I~~1+~lo~v
_
r
___________________________
BM2.BJ2.BKI
I
00-----:----'-::....:...--------------------___
J
8
AC2.AH2.AK2
sEE-scHEMATics
-15V
AB2. AE2. AF2
15-0131
G829 Simplified Diagram
G829-1
•
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ,lCCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION
AMP. CONN.
1-480459
.---I
~
FI
U
b6- I--
R3
.I
5W
+
CI3 ;
~~
;,
~
7
+
_; i'C4
~ ~ ~;bu/ ~;gU/ i'C3
ISOut
ISV
15V
ISV
20%
20%
•
20%
RS
100
R6
IK
R7
R8
R9
100
AJ', AK1 ,ALI
ASI,+5V
RIO
I.SK
~
02
~
R4
47QI
OEC65348
n
C5
S6pt
'~V,5%
1
+IOV
Va
-ISV
6
BNI
L----
00
,I. 01
GNO
8
Cl
~~\:2g~e9.k
~~::t'I,~~11
I~MP
+SV
N
\0
4
s J EI
BPI
~
"
RII
IK
1~
fP
Q4
DEC6,5348
N
BRI
RI
R2
~Q2
...
RI2
47
~
12
~
RI3
~
,
R20
IK
OS
i\N4441
RI7
IK
~
RIS
47
-J
_--'I~~~k _
I+f:%__L
-ISV,AB2,AE2,AF2
~uf
g6uf
C8
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 33O,1I4W,5%
CAPACITORS ARE .alut,100V,20%
DIODES ARE 0664
TRANSISTORS ARE OEC30098
EI IS DEC 7401
PIN 7 ON EI =GNO
PIN 14 ON EI = +SV
,'Se::c:::,~
Fe
C9
~k: 50ut
1
+
CII
I uf
3SV
10%
+
CI2
;i'~~
10"1.
1
6
~~~
RI8
2.2K
~Q7
,-I)
Rl9
I.SK
R21
IK
1/2W
20%
R22
IK
:E~~28~~2
A02:BH~,BK2
BL2, BTl, AN2
GNO
CIO
i-M~
_T
+}·S.D _______
____
.-.
(JQB
RI6
+
8MI
RI4
13
EI
a ... ~
b"
Ell ....
..L.,.."
This page intentionally left blank.
G829-3
.
AMP. CONN.
1-480459
.--I
FI
~
BBI,eCI,BDI
IDAMP
+5V
BEI,AA2,BA2
ABI,6.CI,AO!
U
AEI,AFI,A.HI
R3
1
J
6- t -
+
CI3
CI
150uf
15V
20%
~ t5
'W
+
+
C2
ISOuf
ISV
20°/0
C3
150uf
15V
20%
7
~
n
01
N
\0
..
R'
C5
!56pf
j
.2
BNI-
~
,
.j,..
RI
R2
~
~
12
RI3
~
-151/, AB2,AE2,AI'"2.
f~~%
UNLESS OTHERWISE
RESISTORS ARE
}o;
A'
j\N4441
C9
50uf
C6
+
+~~~/o
BMI
06
~
03
g6ut
+'.fs%
a'
DEC65,34B
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IK
RI5
'7
2!>V
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13
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RI.
+
f?
1 \!:::,
RII
I.
EI
RI2
47
~
+F~~f
RID
1.5K
IOQV,5"fo
BPI-
00
R9
100
t : f :EI} 1 0
-15V
~02
R6
~OlOEC65348
L-
Ci
R7
'-------.,
~
tlOV
6
BRI
R.
I.
If 02
c.
GNO
~
R5
100
AJI,AKI,ALI
A51,+511
+lCII
r~~
10%
r ~I~~
+
!O%
IN748A
~T(~
j
RI6
2.2K
RI9
1.5K
R21
I.
1/2W
20%
R22
I.
•
~~~~2e~~2
:E~;:~~::~
CIO
GNO
~
8M2, BJI, BKI,+IQV
INDICATED"
330,lI4W,5%
CAPACITORS ARE .Olut, 1001/,20%
DIODES ARE 0664
TRANSISTORS ARE DEC30098
EI IS DEC7401
PIN 7 ON El ='GND
PIN 14 ON £1 = +5V
momoamo
EQUIPMENT
CORPORATION I
';;OWER CONNECTOR G829
SIZE
CODE
c I Cs I
GS29-?-1
IA
.... ~ ....... CI .......... " ......... TT.II'Allil(O CllI.CUll 11.["
DtC fORM HO
ORC 102
i'15{'c::- Fe
;~
~N
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.l..
DIS"'T, 3""Y,4~"f14~S
1
1 1
CONNECTOR
FUSE
1
I
CI
I
I
C2
I
I
I
I
I
C3
C6
C7
C9
1
I
I
I
I
GU
G
03
RI7
05
I
I
R3
RI9
G
RIB
R20
R22
88
I
CI2
RIO
R9
RII
I
G
R5
8
R6
R4
RS
I
CII
I
R7
II
0I
RI5
II
8
02
8
RI2
RI4
RI3
RI6
o01
18
EI
8
EB
RI
C'l
00
N
'P
Vl
G829
I
G858
Teletype Connector
The G858 module contains a level converter, an open-collector driver, and interconnecting wiring. The module is
used as a Teletype connector for the PDP-IS, serving as the interface between the Teletype receiver/transmitter
(M706 and M707) and the Teletype. The converter changes the OV and +30V levels received from the Teletype
to OV and +3V levels for the receiver/transmitter, and the driver provides the reader run drive current for the
Teletype.
The following are the input, output, and power characteristics of the G858 module.
INPUT:
Input pin M2 (the reader run in) presents 4 unit loads.
OUTPUT:
Output pin E2 (the Teletype keyboard in) is capable of driving 30 unit loads.
POWER:
Power dissipated in the G8S8 module is SV at 12 rnA and 30V at 30 rnA.
G8S8-1
~
~
'A3"
r ---
~----u
1-0- 898!>
S3 J~~
8
"3B~nN
3000 3ZIS
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THEJ
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
**
r
o
RI
220,10%
5 (7) (H)
~~------------------------------------------o H
•
0 A +5V
;>
R3
•
6
o
('l
00
0 M
(+RELAY) (M)
0 V +30V
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Timer
The K303 module contains three timers that are triggered by a level change from HIGH to LOW.
K303 timers provide time delays from 10 JlS to 30 sec and can be interconnected to form clocks with periods
covering the same intervals. Fixed or adjustable delays and frequencies are obtainable. Calibrated controls are
available (K371 through K378) for mounting directly on the K303. Remote controls can also be added, if desired.
When a K303 input gate steps to zero, the uninverted output falls after a controlled interval, while the inverted
output rises (see simplified illustration). The interval can be as little as 10 JlS or as long as 30 sec, depending on
the size of the Rand C connected to pin J, P, or V. Recovery begins when the input gate rises to logic 1. A
recovery time of at least 0.3 percent of the maximum delay obtainable from the capacitor is required in order to
guarantee 95 percent repeat accuracy in the delay.
A positive step at the input gate resets the K303 timer outputs. If the step occurs before a timeout is complete,
the timeout is terminated and no change appears at the outputs. This property is sometimes convenient for
establishing a pulse repetition-rate threshold (frequency setpoint).
A built-in 2.2 nF timing capacitor assures adequate noise rejection when external capacitors are mounted several
inches from the timer. Time threshold for resetting is always several percent of rated recovery time. Thus, noise
rejection time increases in proportion to the size of the timing capacitor. If remote rheostats and timing
capacitors are used, noise rejection is degraded. If several timing capacitors are to be switch selected, the smallest
capacitor is wired near the module; and the other capacitors are switched in parallel with it.
For additional information, refer to DEC's Digital Logic Handbook, 1970 edition.
RECOVERY TIME....j
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NOTE
K374, K376,K378 PROVIDE
TIMING COMPONENTS FOR
THIS CIRCUIT.
15-0128
K303 Simplified Diagram
K303-1
fHIS SCHEMATIC IS FURNISHED ONLY FOR nSf AND MAINTENANCl PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1967 BY DIGITAL EQUiPMENT CORPORATION
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15-0148
M002
Logic 1 Source
The M002 provides IS outputs at +3V (logic 1) on pins D2 through V2 to hold unused M-series TTL gate inputs
HIGH. Up to 10 unused M-series gate inputs can be connected to anyone output. If a M002 circuit is driven by
a gate, the M002 circuit appears as two TTL unit loads, or 3.2 rnA at ground.
Power dissipation of the M002 module is +5V at 16 rnA (maximum).
M002-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT
"I, BY DIGITAL EQUIPMENT CORPORATrON
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1905575
1100114
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PART NO.
M103
Device Selector
The M I 03 module is used to decode the six device bits transmitted in complement pairs on a positive bus in a
digital system. Selection codes are obtained by selective wiring of the bus signals to the code select inputs; D2, E2,
F2, H2, 12, and K2. The M I 03 module also includes pulse buffering gates for the lOP signals found on the positive bus in digital systems. Two 2-input NAND gates are also provided for any additional buffering that is required.
The following are the input, output, and power characteristics of the M I 03 mod ule.
INPUTS:
All inputs that receive positive bus signals are protected from negative voltage undershoot
of more than -0.8V. The following inputs each present one TTL unit load: D2; E2; F2; H2; 12;
K2; HI; 11; Ll; and MI. Inputs P2, R2, and S2 present 2.5 TTL unit loads. Inputs U2, L2,
and N2 each present 1.25 unit loads. These inputs do not need to be tied to a source of
logic I when they are not in use.
OUTPUTS:
Gate outputs K I and N I can each drive ten TTL unit loads. Pulse buffering outputs A I, B I,
CI, DI, EI, and FI can each drive 37 TTL unit loads. The Option Select output can drive
16 TTL unit loads.
POWER:
The power dissipation of the M 103 module is +5V at 110 rnA (maximum).
M103-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION
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PARTS
LIST
DESCRIPTION
PARTS LIST
mamaama
TITLE
DEVICE SELECTOR M 103
EQUIPMENT
CORPORATION
SIZEICODEl
""'''VNAIltD, ""'''' • • ''CHU8ETT.
PRINTED CIRCUIT REV.
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1001610
IA-PL-MI03-0-0
PART NO.
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M 103-0-1
~ST. £.1.'11'13'1 }13;--'
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M104
1/0 Bus Multiplexer
The M 104 module has been designed specifically for controllers of PDP-IS peripherals. It is used in all controllers
that make use of the API or data channel facilities in the I/O processor. It accepts a request from the controller
logic at its FLAG (1) H input and synchronizes this request to the I/O SYNC H pulses issued from the I/O processor. These pulses are fed into SYNC of the MI04 and immediately set the REQ flip-flop. The REQ flip-flop can
be monitored through pins J2 and U2. The I/O processor responds to a request with a GRANT, and ENA is set.
This flip-flop is generally used to gate any address information onto the bus; e.g., the API trap address or the word
count address of the multicycle data break. The next SYNC pulse sets ENB.
The REQ flag can be reset through pin F2 (CLR RQ) by the controller logic. Pin N 1 should be tied to power
clear or its equivalent.
The Enabling level ENABLE IN holds REQ off if ENABLE IN arrives as a negative level. When REQ is set (if
ENABLE IN is positive), ENABLE OUT goes negative; and the next peripheral on the bus receives this level as a
negative ENABLE IN. In this way, the M 104 establishes priorities among devices on the same API level or among
devices that use the data channel. See the timing diagram for additional information.
The following are the input, output, and power characteristics of the M104 module.
INPUTS:
OUTPUTS:
The inputs are standard TTL voltages and have the following input pins and loads:
Input Pin
Load (Units)
H2
S2
HI
E2
Nl
F2
K2
S2
2.S
1
6
3
1
1-1/4
68il Termination
1
The output gates can drive as follows:
Output Pin
U2
12
PI
Sl
El
Fl
M2
11
POWER:
Number of Loads Pin Can Drive
S
8
9
10
10
10
PDP-IS I/O Bus
Compatible (30 units)
7
The power dissipation of the MI04 module is lW at SV.
MI04-1
1
110 SYNC
0
REQ EN
0
REQ
1
0
GRANT H
0
----4-..1
1
-----~~~-_+-----~-~-----
1
1
•
CLR REQ
0
1
ENA
0 - - - - -....
ENB
0 - - - - - - - - -.....
1
AJI is ASSUMED TO BE WiRED TO F2
15 -0017
M 104 Timing Diagram
MI04-2
This page intentionally left blank.
Ml04-3
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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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EI,E4 ARE DEC7474
E2 IS DEC7400
E3 IS DEC74H40
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
DRN
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DATE
3-13-69
00
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COPYRIGHT I'" BY DIGITAL EQUIPMENT CORPORATION
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PARTS LIST
DESCRIPTION
PARTS LIST
1905575
1301401
1001610
A-PL-M',,-O-O
PART NO.
"O-DD'.O'TITLE
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M112
NOR Gates
The M112 module contains ten 2-input NOR gates, each performing the function NOT (A + B). Pins U I and V I
provide +3V, and each are capable of holding HIGH (logic 1) up to 40 unused M-series inputs. Propagation delay
is 22 ns (maximum).
The following are the input, output, and power characteristics of the M 112 module.
INPUT:
Each input presents one unit load.
OUTPUT:
Each output can drive up to ten unit loads.
POWER:
The power dissipated in the M 112 module is +5V at 50 rnA 6:naximum).
MI12-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION
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RI
R3
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= GND
= +5V
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RES. 750 1/4W 5% CC
PARTS LIST
----DESCRIPTION
PARTS LIST
1001610
1909004
1300295
1301401
A-PL-MI12 0-0
PART NO.
TITLE
~DmDDmD I NORGATEMI12
I
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M113, M115, M117, M119
NAND Gates
The M113, MIlS, M117, and MI19 modules provide general purpose gating for the M-series. They are most
commonly used for decoding, comparison, and control. Each module performs the NAN D function NOT
(A' B - - - - - - - - N), depending upon the number of inputs.
The modules and their descriptions are as follows:
Ml13 - Ten 2-input NAND gates that also can be used as inverters;
MIlS - Eight 3-input NAN D gates;
Ml17 - Six 4-input NAN Dgates;
Mll9 - Three 8-input NAN Dgates.
Unused inputs on any gate must be returned to a source of logic I for maximum noise immunity. In the M113,
M117, Ml19, M121, M617, and M627 modules, two pins (VI and VI) are provided as a source of +3V for noise
immunity. Each pin can supply up to 40 unit loads. Modules M103, MIll, and M002 provide additional sources
of logic I level. Typical propagation delay of these gates is 15 ns, and maximum propagation delay is 22 ns.
The following are the input, output, and power characteristics of these modules.
INPUTS:
Each input presents one unit load.
OUTPUTS:
Each output is capable of supplying 10 unit loads.
POWER:
Power dissipation for the respective modules is:
MIl3:
71 rnA }
MIlS: 41 rnA
41
rnA
+maximum current at SV
MII7:
M119: 9mA
MIl3,MlIS,MI17,M119-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIHARY IN NATURE AND SHOULD BE TREATED ACCORDINGL Y
COPYRIGHT
BY DIGITAL EQUIPMENT CORPORATION
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REFERENCE DESIGNATION
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IRES. 750 1/4W 5% CC
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PARTS LIST
DESCRIPTION
PARTS LIST
1905575
1301401
1300293
1001610
IA~PL-M"3~0-0
PART NO.
THIS SCHEMATIC IS FURr.ISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT
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BY DIGITAL lQUIPMENT CORPORATION
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1905577
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1001610
A-PL-M 117-0-0
PART NO.
Silt
CODE
B
CS
GATES MI17
NUMBER
MI17 0-1
PRINTED CIRCUIT REV
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lEI I I I I I I
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1961 BY DIGITAL EQUIPMENT CORPORATION
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TlTLEZ-Z-Z-3 AND / NOR GATE
MIZ7
SIZE
CODE
B
CS
NUMBER
101127-0-1
M129
AND/NOR Gates
The M129 module contains four general purpose AND/NOR gates that perform functions similar to the M121
module. By connecting signals to the AND inputs, these gates can be used to select and to place on a single output any of several input signals. Propagation delay of an M 129 gate is II ns (maximum).
The following are the input, output, and power characteristics of the M129 module.
INPUTS:
Inputs H2, L2, NI, and V2 present 2.5 unit loads, and the remaining inputs present
1.25 unit loads.
OUTPUTS:
Each output is capable of driving 12.5 unit loads.
POWER:
Power dissipation of the M 129 module is 5V at 50 rnA (maximum).
M129-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT . .I . BY DIGITAL EQUIPMENT CORPORATION
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
IC'S ARE DEC 74 H55N
PIN 7 ON EACH IC:GND
PIN 14 ON EACH IC: +~V
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ANO/O R I NVERT GATE
M12 9
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B
CS
M 129 - 0 - I
I:~~~~'~ I~_: • 'I 1====r====1I====1===~ =~~,;_c:.~.~;:,~~~ ~~L.=:~~=-'--l.nIITTI1
M133
NAND Gates
The M 133 module contains ten 2-input NAND gates, each performing the function NOT (A' B). The module is
used for general purpose high-speed gating. Maximum output propagation delay to a logic I or 0 is IOns. The
high-speed characteristic of these gates frequently solves tight timing problems in complex systems. Unused inputs on any gate must be returned to a source of logic I for maximum speed and noise immunity.
The following are the input, output, and power characteristics of the M 133 module.
INPUTS:
Each input presents 1.25 unit loads.
OUTPUTS:
Each output is capable of driving 12.5 unit loads.
POWER:
Power dissipated in the M 133 module is +5V at 130 rnA (maximum).
M133-1
THIS SCH~MATIC IS ~URr-.ISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION
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U2
UNLESS OTHERWISE INDICATED:
E I - E3 ARE DEC74HQON
PIN 7 ON EACH Ie = GND
PI N 14 ON EACH Ie = +5V
CAPACITORS ARE .01 MFD, fOOV, 20%
M. HALLER
~~~E.681
CHK'O
DATE
W. MULLEN
8 -9-68
ENG
0.0 'CONNOR
I~A.~E~_6E
PROD
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CORPORATION
......... N ... ~O ........... CHU.IETT.
TITLE
SIZE
B
10-2 INPUT
NAND GATES MI33
M135
NAND Gates
The M135 module contains eight high-speed 3-input NAND gates that perform the function NOT (A' B·C). These
gates are most commonly used for decoding, comparison, and control. Unused inputs on any gate must be returned to a source of logic 1 for maximum speed and immunity. Propagation delay of an M135 gate is IOns
(maximum).
The following are the input, output, and power characteristics of the Ml35 module.
INPUTS:
Each input presents 1.25 unit loads.
OUTPUTS:
Each output is capable of driving 12.5 unit loads.
POWER:
Power dissipated in the M135 module is 5V at 90 rnA (maximum).
M135-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1919 BY DIGITAL EQUIPMENT CORPORATION
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UNLESS OTHERWISE INDICATED
IC'S ARE DEC74H 10
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M139
NAND Gates
The MI39 module contains three high-speed 8-input NAND gates that perform the NAND function NOT
(A· B ... N), depending on the number of inputs. These gates are most commonly used for decoding, comparison, and control. Unused inputs on any gate must be returned to a source of logic I for maximum speed
and noise immunity. Propagation delay of an Ml39 gate is 10 ns (maximum).
The following are the input, output, and power characteristics of the MI39 module.
INPUTS:
Each input presents 1.25 unit loads.
OUTPUTS:
Each output is capable of driving 12.5 unit loads.
POWER:
Power dissipated in the M139 module is 5V at 40 rnA (maximum).
M139-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. T. HECIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
~
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IC'S ARE DECI074H30
PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC =+5V
CAPACITORS ARE .01 MFD, 100V,20%
RESISTORS ARE 1/4W,5'Yo
>R I
~
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l'C3
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MAVNAIIID. M" • • ,.,CHuaETTa
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TITLE
3-8 INPUT NAND GATE
MI39
SIZE
8
I 1
CODE
CS
PRINTED CIRCUIT REV.
Pt57.
NUM8ER
M 139 - 0 - 1
161
324, ~ 34, IiJ,>:L
1
REV
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PINK
M149
NAND Wired OR Matrix
The M 149 module contains two sets of nine open-collector NAND gates. The NAND gates are OR wired
together onto nine output pins having the standard TTL output levels. Each set of NAND gates is connected to
operate in conjunction with a separate enable gate. The M149 module is used to gate desired signals onto an
open-collector bus. (Refer to Engineering Drawings D-BS-KPlS-O-38 through D-BS-KPlS-O-43, and
D-BS-KP1S-0-60 through D-BS-KP1S-0-62).
The following are the input, output, and power characteristics of the M149 module.
INPUTS:
Each input presents 1 unit load.
OUTPUTS:
Gate outputs are all open-collector and can sink 16 rnA (maximum). The pulse amplifier
output is capable of driving 10 unit loads.
POWER:
Power dissipation of the M149 module is SV at 130 rnA (maximum).
M149-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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PIN 7 ON EACH IC ~ GND
PIN 14 ON EACH IC ~l-5V
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SIZ'
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CS
NUMBER
REV
MI49-0-1
B
1---=--'--:c-:-L:::-:=----'-::TIlirl"n1
M159
4-Bit Arithmetic Logic Unit
The M159 4-Bit Arithmetic Logic Unit (ALU) module contains a single DEC? 4181 integrated circuit. Nine of
these ALU modules are used in the FP 15 Floating-Point Processor to perform 36-bit arithmetic and logic operations, as shown on D-BS-FP 15-0-19 through -28 of the FPl 5 drawings.
The integrated circuit is capable of performing 16 4-bit arithmetic operations when the MODE control and CN
inputs are low and 16 logic functions when the MODE control input is high. The functions are selected by applying combinations of function select inputs SO through S3. For FPlS applications, the function select and
MODE control inputs are generated by the adder control logic shown on D-BS-FPlS-0-33 of the FPlS drawings.
Only two arithmetic operations, A plus B and A minus B minus 1, are selected. Five logic functions, A, -A, B,
-B, and logical 0, are performed. The combined ALU truth table for FPlS arithmetic operations and logic functions is listed as follows:
MODE
Control
Function Select Inputs
SO
S2
S3
SI
Output Function
0
1
0
0
1
A plus B (arithmetic
operation)
0
0
1
1
0
A minus B minus 1
(arithmetic operation)
0
0
0
0
0
A (logic function)
1
0
0
0
0
-A (logic function)
1
1
0
1
0
B (logic function)
1
0
1
0
1
-B (logic function)
1
0
0
1
1
Logical 0 (logic function)
In addition, a comparator output, A=B, is provided when the four A inputs are equal to the four B inputs. A full
carry look ahead capability is provided for fast, simultaneous carry generation.
INPUTS:
Each input presents 1 unit load.
OUTPUTS:
All outputs are capable of driving 10 unit loads.
POWER:
MlS9-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1970 BY DIGITAL EQUIPMENT CORPORATION
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13
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22
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CAPACITORS ARE .01 UF, 100V, 20".
IC IS A DEC74161
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TITLE
SIZE
B
4-BIT ARITHMETIC
LOGIC UNIT MI59
I CS
CODE
I
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PRINTED CIRCUIT REV.
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'1/ 1/3 ~ 'Ii!> .
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NUMBER
MI59-0-1
I
REV.
IAI I I I I I I
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M161
Binary to Octal/Decimal Decoder
The Ml61 is a functional decoding module that can be used as a binary-to-octal or binary-coded decimal-(8421 or
2421 codes)-to-decimal decoder. In the binary-to-octal configuration, up to eight M161 s can be linked together
to provide decoding of up to six bits. Three ENABLE inputs are provided for selective enabling of modules in decoders of more than one digit. In the octal mode, the bit 2* input is connected to ground, which automatically
inhibits the 8 and 9 outputs. Connections for a 5-bit binary/octal decoder (4 modules) are shown in DEC's
Digital Logic Handbook, 1970 edition. The figure assumes that the inputs to the decoder are the outputs of flipflops such as FF2° (1), 1 output side; and FF2° (0), 0 output side.
02
ENABLE 1
ENABLE 2
ENABLE 3
2"
22
21
20
U1
V2
U2
V1
2*
22
21
20
115-0169
Ml61
Simplified Diagram
The propagation delay through the decoder is typically 55 ns in the binary-to-octal mode and 75 ns in the BCDto-decimal mode. The maximum delay in the BCD-to-decimal mode is 120 ns, thereby frequency-limiting this
module to 8 MHz when used in this fashion. The ENABLE inputs can be used to strobe output data, if inputs
20 - 2* have settled at least 50 ns prior to the input pulse.
*The 2-bit input may be of decimal value 2,4,6, or 8 if illegal combinations are inhibited before connections to the inputs, and the 4-2-1 part of the
code is in binary.
M161-1
The following are the input, output, and power characteristics of the M161 module.
INPUTS:
The inputs to the M16l are: 2° through 2*,1 unit load each; ENABLE 1 through
ENABLE 3, 2 unit loads each.
OUTPUTS:
Each positive output is capable of driving 10 unit loads, and each negative output is
capable of driving 9 unit loads.
POWER:
Power dissipation of the M 161 module is 5V at 120 rnA (maximum).
*The 2-bit input may be of decimal value 2,4,6, or 8 if illegal combinations are inhibited before connections to the inputs, and the 4-2-1 part of the
code is in binary.
M16l-2
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATEO ACCOROINGLY.
COPYRIGHT 19B7 BY DIGITAL EQUIPMENT CORPORATION
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REFERENCE DESIGNATION
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INTEGRATED CKT. DEC7420N
RES
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100V 2001. DISC
PARTS LIST
DESCRIPTION
PARTS LIST
110-00-0
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190557&
1905577
1300293
1301401
1001610
A-PL-MI61-0-0
PART NO.
'BINARY TO OCTAL/DECIMAL
DECODER MI61
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SIZE
CORPORATION
C
NUMBER
MI61-~
RIV
8
M162
Parity Circuit
The M162 module is a parity detector and contains two parity circuits. Each circuit indicates whether the binary
data presented to it contains an odd or even number of Is. The requirements of the data and its complement are
shown in the illustration.
Indication of odd parity is given by a HIGH level at pins Kl and U2. Pins Ll and V2, when HIGH, indicate even
parity or no input.
The following are the input, output, and power characteristics of the M162 module.
INPUTS:
Each input presents four unit loads.
OUTPUTS:
Pins Ll and V2 can each supply up to ten unit loads. Pin Kl and U2 can each supply up to
six unit loads.
POWER:
Power dissipation of the M162 module is +5V at 102 rnA (maximum).
DATA IN
4
KI PARITY 000
1/2 MIS2
L1 PARITY 000
AI
......~"..----'
~--
DATA IN
US-OI62
Ml62 Simplified Diagram
M162-1
THIS SCHEMATIC IS fURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 11.7 BY DIGITAL EQUIPMENT CORPORATION
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFO
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
EI, E2, E4, E5, E6,E7, Ee, EIO 8
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TITLE
PARITY CIRCUIT MI62
M164
6-Bit Parallel Adder
The Ml64 module contains a 6-bit conditional sum adder. Three of these modules are connected in tandem to
form the IS-bit adder used in the central processor of the PDP-IS. (Refer to Engineering Drawings
D-BS-KPIS-O-I through D-BS-KPIS-O-IS.) The adder can generate an IS-bit sum in S2 ns. This high speed is
available because there is no carry propagated from one adder module to the next. Instead of having the carry
propagated from module to module, which takes 48 ns per module, each 6-bit sum is performed twice simultaneously (see illustration). One sum, CA (carry anticipated), is formed without a carry inserted, while the other
sum, NCA (no carry anticipated), is formed without a carry inserted. Combinational logic in each adder module
L 1 c""A'--_ _~-.r-....
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NOTE: BITS 01 THRU 04
ARE NOT SHOWN
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01
15-0111
M164 Simplified Diagram
M164-1
provides the control inputs SCA (select carry anticipated) or SNCA (select no carry anticipated) to the module
handling the next six most significant bits. The sum from the first adder module during normal addition is always
a sum without a carry inserted because the combinational logic is strapped to select the adder that has no carry
inserted.
The following are the input, output, and power characteristics of the M164 module.
INPUTS:
OUTPUTS:
The MI64 adder module is unbuffered; and all inputs must, therefore, remain stable for the
entire add cycle. The following list shows all input connections and the TTL unit loading
they present:
Name
Pin
Loading
AO
BO
Al
BI
A2
B2
A3
B3
A4
B4
A5
B5
CA
SCA
SNCA
NCA
EI
2.0
2.0
8.0
8.0
2.0
2.0
8.0
8.0
2.0
2.0
8.0
8.0
2.5
2.5
2.5
2.5
F2
H2
12
K2
L2
R2
S2
T2
U2
V2
L1
M2
N2
P2
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
The M164 adder module generates a 6-bit sum in 78 ns and a carry in 42 ns. All output connections and TTL driving capabilities are shown below.
Name
~o
~
~
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I
2
3
~4
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5
SNCA
SCA
CA
NCA
POWER:
D2
True I
Pin
Drive
True I
BI
Al
SI
CI
VI
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12.5
12.5
12.5
12.5
12.5
12.5
5.0
5.0
5.0
5.0
0.4
0.4
0.4
0.4
0.4
0.4
2.4
2.4
0.4
0.4
11
MI
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Power dissipated in the M164 module is 5V at 118 rnA (maximum).
M164-2
THIS SCHEMATIC IS FlJ.
.oJ ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT II • • BY DIGITAL EQUIPMENT CORPORATION
P2 N2
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UNLESS OTHERWISE INDICATED:
CAPACITORS ARE .01 MFD
RESISTORS ARE 1/4W; 5%
PIN 7 ON EACH IC (EXCEPT DEC7482N'S)= 6ND
PIN 14 ON EACH IC (EXCEPT DEC7482N'S)= +5V
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COPYRIGHT IS89 BY DIGITAL EQUIPMENT CORPORATION
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M191
Carry Look-Ahead Generator
The M 191 Carry Look-Ahead Generator, consisting of two DEC 74182 integrated circuits, is a high-speed
generator capable of anticipating a carry through a group of ALUs. A 13-ns delay occurs for each look-ahead
level.
Input Voltage:
5.5 volts (with respect to network grand terminal).
Supply Voltage:
4.75 - 5.25 (5 v. nominal)
Normalized Fan Out
from Each Output:
High logic level 20
Low logic level 10
Each carry look-ahead circuit in the M 191 is associated with four ALUs (16 bits). The M 191, when used in conjunction with the M 159 ALU, provides carry, generate-carry, and propagate-carry functions for 36-bit words.
Each circuit generates the anticipated carry through its respective group of ALUs, as well as providing a Generate
(G) and Propagate (P) input to a third carry look-ahead circuit associated with the last ALU; hence, the term fullcarry look-ahead in three levels (36 bits).
Depending on the selected function of the ALUs, the carry look-ahead circuitry determines whether a carry will
be propagated through the particular ALU, or whether the selected function will generate a carry. If a carry is
produced, it is directed into the next ALU in line. This sequence is continued for each of the four ALUs in the
section. The carry look-ahead circuitry then "looks" at the G and P signals of all four ALUs and determines
whether a carry should be inserted into the next four ALUs and into the third level of carry look-ahead. This
process is continued for the second section of ALUs (next 16 bits). Finally, the third level of carry look-ahead
determines whether a carry should be inserted into the final ALU by examining the resulting G and P inputs of
the other two look-ahead circuits.
The truth table for the first-stage carry is as follows:
True Carry Insert = L
POO
GOO
CNOO
CN +X
L
L
H
L
L
L
H
H
L
H
H
L
H
H
L
L
M191-1
True Carry Insert = Low
POO
GOO
CNOO
CN+X
L
H
L
H
L
H
L
H
L
L
H
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
H
L
The following are the logic equations for a carry look-ahead stage:
CNOI = CNOO * GO + GO * Po
CN02 = G I *P I + Po*G o *G I + G I *GO*C N
CN03 = P 2 *G 2 + G I *G 2 *P I +GO+G I *G 2 *PO+GO*G I *G 2 *C N
GGOO = P3 *G 3 + P 2 *G 3 *G 2 +P I *G3*G2*GI+G3*G2*GI *Go
PPOO
= P3+P 2 + PI+PO
where
CNXX = True L
GXX
=TrueH
PXX
=TrueH
GGXX =TrueH
PPXX =TrueH
FPI5-0-28
FP24 P03 L H2
FP24 003 L
J2
FP25 P02
Jl
FP25 G02
HI
FP 26 P01 L LI
FP26 GOI L KI
FP27 POO L
FP27 000 L
K2
L2
FP33 CNOO L Fl
P3
G3
P2
M191
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G
G2
Pi
G1
PO
GO
CN+Z
CN+Y
CN+X
F2
FP28 PPOO L
E2
FP28 GGOO L
02
01
FP28 CN03 H
FP28 CN02 H
EI
FP28 CNOI H
CN
15-0576
Ml91 Carry Look-Ahead Generator
M191-2
M159-ALU'S
A
15-0577
36-Bit ALU, Full-Carry Look-Ahead in Three Levels
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1:t]8~nN
THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1170 BY DIGITAL EQUIPMENT CORPORATION
H2--.:..! P3
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LOOK AHEAD LOGIC
FOR 74181
I I
CODE
NUMBER
MI91
I
REV
M205
D Flip-Flops
The M205 module contains five separate D-type flip-flops. Each flip-flop has independent DATA, CLOCK, SET,
and CLEAR inputs. Information must be present on the DATA input 20 ns (maximum) before the CLOCK pulse,
and the information should remain at the input at least 5 ns (maximum) after the CLOCK pulse has passed the
threshold voltage. Data transferred into the flip-flop by the previous CLOCK pulse will be present on the I output of the flip-flop. Typical time duration of the CLOCK pulse preset and reset pulses is 30 ns each. Maximum
delay through the flip-flop is 50 ns. Refer to the M206 description for additional details.
The following are the input, output, and power characteristics of the M205 module.
INPUTS:
D inputs present I unit load each.
C inputs present 2 unit loads each.
SET inputs present 2 unit loads each.
CLEAR inputs present 3 unit loads each.
OUTPUTS:
Each output (0 and I) is capable of driving 10 unit loads. Two +3V supplies (Ul and V I),
capable of 25 unit loads, are available.
POWER:
Power dissipation of the M205 module is +5V at 55 rnA (average), 100 rnA (maximum).
M205-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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NOTES:
PIN 7 ON EACH IC
PIN 14 ON EACH IC
HI
= GND
= +5V
EI, E2, E3
R3,R4
RI,R2
CI,C2,C3
INTEGRATED CKT. DEC7474N
RES. 750
1/4W 5% CC
RES. 330
114W 5% CC
CAP. .0IMFD 100V 20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST
REFERENCE DESIGNATION
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DEC FORM NO.
DRB 102
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PROD.
DATE
2-17-('f'
TRANSISTOR & DIODE CONVERSION CHART
DEC
EIA
D,TE
3 1~'1.1
4}'~?
DEC
EIA
~DmDDmD
EQUIPMENT
CORPORATION
DATE
MAVNA"D, MA • • ACHU • • TT.
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1905547
1301401
1300295
1001610
A-PL-M205-0-0
PART NO.
TITLE
5 "0" FLIP FLOPS M205
SIZE
CODE
B
CS
I
lAlllllll
PRINTED CIRCUIT REV.
Drs,--
-~
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NUMBER
M205-0-1
A
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M206
D Flip-Flops
The M206 contains six separate D-Type flip-flops. Each flip-flop has independently gated DATA, CLOCK, and
dc SET inputs.
Provision is made on the printed circuit board for changing the configuration of the two CLEAR lines to the flipflops. All M206 modules are supplied with the 3-3 configuration, but the grouping can be changed as follows:
Delete Jumper
Add Jumper
FF2, 3, 4, & 5
Al to FF2
K2 to FF2
FFI,2,3,4,&5
Al to FF2
Al to FFI
K2 to FF2
K2 to FFI
Configuration
CLEAR I (AI)
3-3
FFO, I, & 2
FF3, 4, & 5
4-2
FFO& I
5-1
FFO
CLEAR 2 (K2)
Information must be present on the D input 20 ns (maximum) prior to a standard CLOCK pulse and should remain at the input at least 5 ns (maximum) after the CLOCK pulse leading edge has passed the threshold voltage.
Data transferred into the flip-flop is stable at the output within 50 ns (maximum). Typical width requirement
for the CLOCK, dc RESET, and dc SET pulses is 30 ns each.
Information present on the D input is transferred to the output when the threshold is reached on the leading
(positive-going voltage) edge of the CLOCK pulse.
The following are the input, output, and power characteristics of the M206 module.
INPUTS:
D inputs present I unit load each. C inputs present 2 unit loads each. CLEAR lines present
3 unit loads per connected flip-flop. S inputs present 2 unit loads each.
OUTPUTS:
Each output is capable of driving 10 unit loads.
POWER:
Power dissipation of the M206 module is +5V at 87 rnA (maximum).
A common clear for all six flip-flops can be obtained by externally wiring pins Al and K2 together.
CAUTION
The loading of each CLEAR line is calculated on the basis of 3
unit loads per flip-flop. For example, the 4-2 configuration results in 12 unit loads at input K2 and 6 unit loads at input AI.
M206-1
THIS SCHEMATIC IS FURr.ISHED ONLY FOR TEST AND MAINTENANCt PURPUSES THE
CIRCUITS ARE PROPRIETARY IN NATUPE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1917 BY DIGITAL EQUIPMENT CORPORATION
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NOT USED -IS\' - -_ _ B2
-
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NOTES:
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +SV
EI THRU E3
CI THRU C4
REFERENCE DESIGNATION
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DEC
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INTEGRATED CKT. DEC7474N
1905547
CAP. .01 MFD 100V
1001610
20% DISC
A-PL-M206-0-0
PARTS LIST
DESCRIPTION
PART NO.
PARTS LIST
~DmDD~D
EQUIPMENT
CORPORATION
..... " ........ D
....... ss"'e'. "JSIOTH.
I
TITLE
SIX FLlP- FLOPS M206
SIZE
B
I
CODE
CS
I
NUMBER
M206-0-1
PRINTED CIRCUIT REV
J
R~V
TDI I 1 I II I
M207
Flip-Flop
The M207 Flip-Flop module contains six J-K type flip-flops that can be used as buffers, control flops, shift
registers, and counters. A truth table for clocked set and reset conditions is shown below:
INPUT
OUTPUT
Initial State
Resultant State
1
0
C
J
K
1
0
H~L
L
L
H
H
L
H
L
H
L
H
L
L
H
H
H
H
L
L
L
L
H
H
L
H
L
H
H
L
H
L
H
L
L
H
L
H
Note that when both inputs are high, the flip-flop complements on each clock pulse.
Application of a low level to an R input for at least 30 ns unconditionally resets the flip-flop. Two CLEAR inputs are provided with jumper terminals for optional clearing in groups of 3 and 3 (standard), 4 and 2, 5 and 1,
or 6 and O.
J and K inputs must be stable during the leading-edge threshold of the standard clock input, and must remain
stable during the positive state of the clock. Data transferred into the flop will be stable at the output within
30 ns (typical) of the clock pulse trailing-edge threshold (negative-going voltage).
Provision is made on the printed circuit board for changing the configuration of the two CLEAR lines to the
flip-flops. All M207 modules are supplied with the standard 3-3 configuration but the grouping can be changed
as follows:
Clear
Grouping
Delete
Jumper
Add
Jumper
FF2,FF3,FF4,
FF5
FFI-FF2
K2-FF2
FF I ,FF2,FF3,
FF4 and FF5
AI-FFI
K2-FFI
Clear 1 (Al)
Clear 2 (K2)
3-3
FFO,FF I ,FF2
FF3,FF4,FF5
4-2
FFO,FFI
5-1
FFO
M207-1
INPUTS:
Input characteristics are as follows:
J and K inputs present one unit load
C inputs present two unit loads.
CLEAR inputs present two unit loads per connected flip-flop.
OUTPUTS:
Each output is capable of driving 10 unit loads.
POWER:
+5V, 96 rnA (max.)
M207-2
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 11117 BY DIGITAL EQUIPMENT CORPORATION
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REFERENCE DESIGNATION
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DEC
DATE
-J.7 &
DATE
r,
INTEGRATED C KT. DEC7473N
CAP. ,01 MFD 100V 20% DISC
PARTS LIST
DESCRIPTION
PARTS LIST
1905587
1001610
A-PL-M207-0-0
PART NO,
-FLOP
~amDDmD IFLIP
I
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TITLE
TRANSISTOR & DIODE CONVERSION CHART
DEC
I ...
A2
A2
CI J[C2J[C3J[C4 +5V
1I I I
7
1
U2
NOTES:
PIN 4 ON EACH IC =+5V
PIN II ON EACH IC = GND
----INDiCATES JUMPER
JUMPER CAN BE INSTALLED BY
CUSTOMER BETWEEN FF2 a K2,
AND BETWEEN FFI a K2
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EQUIPMENT
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SIZE
CODE
B
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PRINTED CIRCUIT REV
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NUMBER
M207-0-\
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M207
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IE1 I I ITT I
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M211
Binary Up-Down Counter
The M2ll is a 6-bit binary UP/DOWN counter. It can switch counting mode (UP or DOWN) without disturbing
the contents of the counter. Maximum count rate is 10 MHz. SET/RESET inputs are available for each bit.
Maximum carry propagation time is 80 ns per bit.
The Enable input must be negated 100 nsec prior to an UP/DOWN
level command.
ENABLE LINE:
The Enable input must not be negated earlier than 500 nsec after the
leading edge (positive going voltage) of the clock pulse.
The Enable input must be asserted at least 60 nsec prior to the first count.
UP/DOWN Control Line:
A logical 1 on this line will yield an up count. A logical 0 on this line will
yield a down count.
CARRY OUT:
The Carry Out will yield a positive level change whenever a carry or borrow
occurs.
INPUTS:
Count In - positive transition or pulse with less than 400 nsec risetime.
Count In presents 2 unit loads. Reset - Each reset input presents 3 unit
loads. Set - Each set input presents 2 units loads. All other inputs
present 1 unit load.
OUTPUTS:
Each flip-flop output (1 or 0) can drive 8 unit loads. Carry Out can drive 10
unit loads. Each inverter output can drive 30 unit loads.
POWER:
+S.OV, 217 rnA (max.)
~
COU'lT IN 02
ENABLE At
FFO
FFl
FF2
FF3
UP/DOWN B1
POWER
+ 5 V - ' 2 ___
GRD -
C2. T1--eo
M2ll-l
FF4
FF5
H1 CARRY
OUT
•
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANC~ PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION
VI
T2
UI
R2
PI
M2
MI
JI
J2
E2
FI
CI
02
COUNT
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GND
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NOTES:
PIN 7 ON EACH Ie.: GND
PIN 14 ON EACH Ie = +5V
DEC7451N MAY BE USED IN PLACE OF DEC7450N
E8
E3
E2.£4, E5, E7, fIO.E II
EI,E6, E9
R2
RI
C 1 THR'lICrr
INTEGRATED CKT. DEC7440N
INTEGRATED CKT. DEC74QON
INTEGRATED CKT. DEC74~ON
INTEGRATED CKT. DEC7474N
RES. 3.3K
1/4W 5% CC
RES. 7.5K
1/4W ~% CC
CAP.
.01 MFD 100V 20% DISC
PARTS LIST
REFERENCE DESIGNATION
DESCRIPTION
PARTS
DRN
'"oz
in
~
?n_Jt'~
_IN
00
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00
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"R"I ......
,':91
DEC FORM NO
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..
DATE
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TRANSISTOR & DIODE CONVERSION CHART
tiEC
OITLE
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PART NO.
LIST
IIIIO"DDII!IID
1:1
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1905579
1905575
1905580
1905547
1300439
1301422
I
1001610
IA-PL-M211-0-0
BINARY UPI DOWN
COUNTER M211
("nn~
-~
1 ... _ ..
3..1't,4i'1Ji./S0
-
I_I
I I, -I
6-Bit Left/Right Shift
M212
Register
The M212 module is an internally-connected left/right shift register/buffer that consists of six edge-triggered
D-type flip-flops. The M212 features parallel selection and loading of either of two independent 6-bit sources,
or serial loading and shifting of data in either the left or right direction.
All operations of this register, with the exception of clear, are effected by the leading edge of a positive pulse
applied at pin C I. Four function enable inputs define the module operation. The enable inputs are: ENABLE
RIGHT SHIFT, ENABLE LEFT SHIFT, ENABLE INPUT A, and ENABLE INPUT B.
INPUTS:
Input characteristics are as follows:
Data inputs present one unit load, logic I is +2.8V, or greater, logic 0 is +0.8V,
or less.
Enable inputs present six unit loads, logic I is +2.8V, or greater, logic 0 is +0.8V
or less.
Data and enable inputs must be stable at the gate inputs 50 ns before the clock
threshold is attained.
Assertion of the clock input is a transition from 0 to +3.0V. The clock input
presents 12 unit loads.
A direct clear input at pin BI resets all flip-flops. A +3.0 to OV transition at least
30 ns duration is required. The direct clear input presents 12 unit loads.
OUTPUTS:
Both the 0 and I output of each flip-flop are brought to output pins. Data transferred into each flip-flop will be stable at the output within 50 ns of the leading
edge of the clock pulse.
Each 0 output will drive 10 unit loads. Each I output will drive 8 unit loads.
POWER:
+5V, 145 rnA (max.)
M212-1
+
SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCl PURPOSES THE
ARE PROPRI,TARY IN NATURE AND SHOULD BE TRlATfD ACCORDINGLY
1967 BY DIGITAL EQUIPMENT CORPORATION
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INTEGRATED CKT. DEC7453N
£3,£6,£9
NOTES:
PIN 7 ON EACH IC. GND
PIN 14 ON EACH IC' +5v
R2
INA3(fII)
UI
IN83(8)
VI
INA4(8)
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V2
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REFERENCE
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D
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V
'-~ 57'
M214
Data Storage Register
The M214 module contains a 6-bit adder and a 6-bit storage register with input gating logic. Three of these
modules are connected in tandem to form the IS-bit data storage register (DSR) used in the I/O processor of
the PDP-IS. (Refer to Engineering Drawings D-BS-KD IS-O-1 through D-BS-KD IS-0-3.) The register is used for
exchanging data between memory and I/O devices. Input gating logic is included in the module for strobing
the memory data lines (MDL), I/O buffer (lOB), and the I/O address (lOA) into the register.
The following are the input, output, and power characteristics of the M214 module.
INPUTS:
The following list shows all input connections and the TTL unit loading they present:
Name
CARRY-IN
Pin
Loading
Ul
4
lOA to DSR
R2
6
lOB to DSR
Rl
6
MDL to DSR
HI
6
DSR to DSR
M2
6
lOA
B2, Cl, K2,
11, P2, PI
1 each
lOB
H2, F2, L2,
Ll, S2, T2
1 each
MDL
AI, D2, 12,
Fl, N2, Nl
I each
STROBE
V2
6
OUTPUTS:
Each DSR output (pins E2, El, Kl, Ml, U2, and VI) is capable of driving 9 unit loads,
and the CARRY OUTPUT (pin Dl) is capable of driving S unit loads. The STROBE pulse
should occur at least 100 ns after the CARRY-IN and the input data have stabilized. DSR
outputs should occur SO ns (maximum) after the module is strobed.
POWER:
Power dissipation of the M214 module is SV at 2S0 rnA (maximum).
M214-1
•
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE I"URPOSES_ THE
CIRCUITS ARE PflOPRI[TARY IN NATURE AND SHOULD BE TREATED .... CCORDINGlY.
COPYRIGHT INt ay DIGITAL EQUIPMENT CORPORATION
DSAI2(1)
E2
SI RESET
•
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M216
D Flip-Flops
The M216 module contains six separate D-type flip-flops with independent DATA-SET and CLOCK inputs. The
CLEAR inputs to these flip-flops are connected to two clear input lines (three flip-flops to each line).
Data must be present on the D input 20 ns (maximum) before the CLOCK pulse and should remain at the input
at least 5 ns (maximum) after the CLOCK pulse leading edge has passed the threshold voltage. Data transferred
into the flip-flop is stable at the output within 50 ns (maximum). Typical width requirements for the CLOCK and
dc RESET pulses are 30 ns each.
Data present on the D input is transferred to the output when the threshold is reached on the leading (positivegoing voltage) edge of the CLOCK pulse.
The following are the input, output, and power characteristics of the M216 module.
INPUTS:
D inputs present I unit load each.
C inputs present 2 unit loads each.
CLEAR inputs present 3 unit loads per connected flip-flop.
SET inputs present 2 unit loads each.
OUTPUTS:
Each output is capable of driving 10 unit loads.
POWER:
Power dissipation of the M216 module is SV at 87 rnA (maximum).
A common clear line for all six flip-flops can be obtained by externally wiring pins Al and K2 together.
CAUTION
The loading of each CLEAR line is calculated on the basis of 3
unit loads per flip-flop.
M2l6-l
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY"
COPYRIGHT 1987 BY DIGITAL EQUIPMENT CORPORATION
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PIN 7 ON EACH IC =GND
PIN 14 ON EACH IC =+5V
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PART NO.
TITLE
SIX FLlP- FLOPS M216
B
M218
MQ Register
The M218 module contains a 9-bit storage register with input gating and shifting logic. Two M218 modules are
used in the PDP-IS central processor equipped with the EAE option to form the 18-bit MQ register. (Refer to
Engineering Drawings D-BS-KE 15-0-1 and D-BS-KE 15-0-2.) This register extends the AC shifter (M227), facilitating high-speed arithmetic operations (shifting, normalizing, division, and multiplication) and double-precision
results.
The following are the input, output, and power characteristics of the M218 module.
INPUTS:
All inputs but the CLOCK input present 1.25 TTL unit loads. The CLOCK input presents
18 unit loads.
OUTPUTS:
Each output is capable of driving 10 TTL unit loads.
POWER:
Power dissipation of the M218 module is 5V at 310 rnA (maximum).
M218-1
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M219
Step Counter and Control
The M219 module contains a 7-bit synchronous step counter with input gating and EAE control logic. One of
these modules is used in the PDP-IS central processor equipped with the EAE option. (Refer to Engineering
Drawing D-BS-KE 15-0-3.)
The following are the input, output, and power characteristics of the M219 module.
INPUTS AND OUTPUTS: Both inputs and outputs are standard TTL levels.
POWER:
Power dissipated in the M219 module is 5V at 540 rnA (maximum).
M219-1
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M223
MA and MB Registers
The M223 module contains two 4-bit registers with input gating logic. Five of these modules are used to form
the 18-bit memory buffer (MB) register and the 13-bit memory address (MA) register that are used in each
memory bank of the PDP-IS. (Refer to Engineering Drawings D-BS-MMIS-O-3 through D-BS-MMIS-O-S.) The
MA register receives the memory cell address from the central processor or the I/O processor and selects a specific
core location. The data or instruction word to be read from or written into the specified core location travels
through the MB register to or from the central processor and the I/O processor.
The following are the input, output, and power characteristics of the M223 module.
INPUTS:
All input connections and the TTL unit loading they present are shown below.
Name
Pin
MDL
MBLOAD
MBCLEAR
MALOAD
MAROLD
SA (MB D SET)
D2, E2, F2, R2
11
12
PI
P2
K2, L2, M2, N2
Loading
I each
8
12
4
4
2 each
OUTPUTS:
Each MB output (pins K I, L I, M I , and N I) is capable of driving 9 unit loads. Each MA output
(pins RI, R2, SI, S2, Ul, U2, VI, and V2) is capable of driving 10 unit loads.
POWER:
Power dissipation of the M223 module is SV at 17S rnA (maximum).
M223-1
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COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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RESISTORS ARE 1.5K I 1/4W, 5%
CAPACITORS ARE .OIMFD
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M226
Register
The M226 module contains seven storage flip-flops providing I bit of storage for each of the following registers:
1.
2.
3.
4.
5.
6.
7.
Data Switch (OS)
Index (XR)
Memory Address (MA)
Limit (LR)
Program Counter (PC)
Output Buffer to Memory (MO)
Memory Input (MI)
Eighteen M226 modules are used to form the registers in the central processor of the PDP-IS. The registers require an IS-bit capacity. (Refer to Engineering Drawings D-BS-KPIS-O-I through D-BS-KPIS-O-IS.) Mixertype logic for A bus, B bus, C bus, and I bus gating is also included on the M226 module.
The following are the input, output, and power characteristics of the M226 module.
INPUTS AND OUTPUTS: Inputs and outputs are standard TTL levels except for pin BM I, which is an
open-collector output capable of sinking 16 rnA (maximum).
POWER:
Power dissipation of the M226 module is SV at 260 rnA (maximum).
M226-1
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M227
AC Shifter
The M227 module contains 9 bits of the accumulator with input gating and shifting logic. Two of these modules
are used in the central processor of the PDP-IS to form the 18-bit accumulator (AC) shift register. (Refer to
Engineering Drawings D-BS-KP IS-O-I through D-BS-KPIS-0-18.) The register is used for manipulating data and
temporarily storing results of arithmetic/logical operations.
The following are the input, output, and power characteristics of the M227 module.
INPUTS:
All inputs but the CLOCK input present 1.2S TTL unit loads. The CLOCK input
presents 18 unit loads.
OUTPUTS:
Each output is capable of driving 10 TTL unit loads.
POWER:
Power dissipation of the M227 module is SV at 420 rnA (maximum).
M227-1
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M238
Synchronous Up/Down Counter
The M238 Synchronous Up/Down Counter consists of two DEC74193 4-bit synchronous up/down counter
integrated circuits. The M238 is used in the EPA, DIR, and DAR registers of the FPI 5 Floating-Point Processor,
where the counters are connected to provide eight bit counting capability.
Synchronous operations is provided by clocking all flip-flops in the counter simultaneously so that the outputs
change in coincidence with each other. The flip-flops are master-slave flip-flops and the outputs are triggered
by a positive-going transition of either of two clock inputs. One clock input is designated U (up count) and the
other is designated D (down count). The direction of counting is determined by pulsing one clock input while
the opposite clock input is kept high.
The outputs of the flip-flops may be preset to any state by entering the data at the data inputs while the load
input (L) is low. The output will change to reflect the input, regardless of the clock pulses. The clear input is
provided to clear all flip-flops, independent of the clock and load inputs.
Both the borrow and carry outputs are available for cascading the up-counting and down-counting operations.
When counter underflow occurs, the borrow output produces the same width pulse as the down-count input.
When counter overflow occurs, the carry output produces the same width pulse as the up-count input. Cascading
is accomplished by applying the borrow and carry inputs to the down-count and up-count inputs of the next
counter.
In the example of the DIR register, the UPCOUNT input is inhibited by +3V, indicating that the DIR can only
be decremented.
M238
H24
02
DATA INPUTS {
::::
MD 16
MD 17
LOAD
CLEAR
UP COUNT
DOWN COUNT
- LD IR H
GND
E2
F2
Kl
H2
J1
L1
01
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DIR 15 (1) H
DIR 16 (1) H
DATA OUTPUTS
DIR 17 (1) H
CLR
+3V H 19 Ul - - - - - '
K2
DlR OWN PI - - - - - '
M238-1
15-0565
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1970 BY DIGITAL EQUIf':.lENT CORPORATION
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M240
R-S Flip-Flops
The M240 module contains six R-S-type flip-flops. Each flip-flop consists of two NAND gates with crosscoupled outputs. Two inputs are provided for setting the flip-flops, and one input is provided for resetting the
flip-flops. The following truth table defines the operation of the flip-flops. When the SET output (F 1) is HIGH,
both of the SET inputs (Cl and Bl) are HIGH. When the SET output is LOW, either one or both SET inputs are
LOW.
Previous State
1
0
L
H
L
H
H
L
L
H
H
L
H
L
L
H
H
L
Input Condition
SET RESET
L
H
H
H
L
H
L
L
H
L
H
H
H
L
L
L
Result
0
1
H
L
H
L
No Change
No Change
No Change
No Change
H*
H
H*
H
'Ambiguous state: In practice, the input that stays low longest assumes control.
Propagation delay time from SET or RESET to logical 1 (HIGH) level output is 10 ns (maximum). Propagation
delay time from SET or RESET to logical 0 (LOW) level output is 20 ns (maximum).
The following are the input, output, and power characteristics of the M240 module.
INPUTS:
Each input presents 1.25 TTL unit loads.
OUTPUTS:
Each output is capable of driving 34 TTL unit loads.
POWER:
Power dissipated in the M240 module is 5V at 185 rnA.
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M248
Right Shift Parallel Load Register
The M248 Right Shift Parallel Load Register consists of two DEC7495 Right Shift, Parallel Load Register
integrated circuits. The M248 is used in the EPB, FMA, FMB, and FMQ registers in the FP 15 Floating-Point
Processor. The modules are connected to allow right-shifting between four-bit sections so that each module
is capable of handling eight bits. A sample FP 15 Floating-Point Processor application is shown in the illustration.
When a logic a input is applied to the mode control (MC) input, the output of each flip-flop is applied to the
succeeding flip-flop. The right shift operation is performed by clocking at the RS input. During this time, the
left-shift (LS) input is inhibited.
When a logic I input is applied to the mode control input, the flip-flops are decoupled to prevent right shift and
parallel inputs are loaded when the LS input is clocked. The register can be configured for left-shift operations
by connecting the output of each flip-flop to the parallel input of the preceding flip-flop.
r
23 H
ADD 22 H
DATA INPUTS
ADD 21 H
ADD 20 H
EPB 01
(1)
H
M248
E07
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2
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3
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0
V2
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DATA OUTPUTS
LS
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EPB LD H
R2
P2
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M248-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. T. HE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY
COPYRIGHT 1970 BY DIGITAL EQUlr'..1ENT CORPORATION
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M302
Dual Delay Multivibrator
The M302 contains two delays (one-shot multivibrators, see Figure A) that are triggered by a level change from
HIGH to LOW, or by a pulse to LOW whose duration is equal to or greater than 50 ns. When the input is triggered, the output changes from LOW to HIGH for a predetermined length of time and then returns to LOW. The
basic delay range is determined by an internal capacitor. The delay range can be increased by selection of additional capacitance, which is available by connecting various module pins or by the addition of external capacitance.
An internal potentiometer can be connected for fine delay adjustments within each range, or an external resistance
can be used. If an external resistance is used, the combined resistance of the internal potentiometer and the external resistance should be limited to 10,000il.
DELAY 1
112 M302
OUTPUT
F2 OUTPUT
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SEE TABLE
B
A
M302 Simplified Diagram
The fall-time of the input trigger should be less than 400 ns.
The delay time is adjustable from 50 ns to 7.5 ms using the internal capacitors and can be extended by adding an
external capacitor.
Care should be exercised in the selection of external capacitors to assure low leakage because leakage affects the
time delay.
Recovery time is determined by the size of the capacitance used. The minimum recovery time of the M302 module is 30 ns when no additional capacitance is used. Recovery time with additional capacitance can be calculated
by using the following formula:
Where T r is in seconds and C is in farads
Recovery time is defined for this module as follows: Recovery time (Tr ) is the minimum time interval that must
exist before each trigger, with all inputs HIGH and the output LOW. The table below illustrates these conditions.
M302-1
Delay Range
Capacitor Value
Interconnections Required
Delay 1
Delay 2
50 ns - 750 ns
100 pf (internal)
None
500 ns - 7.5 J.ls
1000 pf (internal)
DI - L2
NI - S2
5 J.ls - 75 J.ls
0.01 uf (internal)
HI - L2
SI - S2
50 J.ls - 750l1s
0.10 uf (internal)
11 -L2
Ul - S2
1.0
EI - L2
PI - S2
500l1s - 7.5 ms
Above 7.5 ms
uf (internal)
None
Add external
capacitors between
specified pins
For adjustable delays (D2 - E2 and V2 - R2), connect the pins to the internal adjustment potentiometer. Without
a potentiometer, the delay will not recover. An external potentiometer of less than 10 Krl can be used by connecting the potentiometer between E2 or R2 and ground pin C2. Use of an external adjustment resistor causes
some increase in jitter. It is recommended that the leads to an external potentiometer be twisted pairs and be made
as short as possible.
The following are the input, output, and power characteristics of the M302 module.
INPUTS:
Each input presents 2.5 unit loads.
OUTPUTS:
Each output is capable of driving 25 unit loads.
POWER:
Power dissipation of the M302 module is +5V at 166 rnA (maximum).
M302-2
This page intentionally left blank.
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COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION
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M311
Tapped Delay Lines
The M311 module contains two tapped delay lines. Each delay line has ten taps providing delays in 25 ns
intervals from 25 ns through 250 ns (see simplified diagram). Pin 11 supplies the minimum delay of 25 ns and
pin VI supplies the maximum delay of 250 ns. The input NAND gate of the delay line provides an additional
delay of IOns (maximum). Delay line tolerance is ±5%.
The following are the input, output, and power characteristics of the M311 module.
INPUTS:
Each input presents 1.25 TTL unit loads.
OUTPUTS:
Each output is capable of driving 1.25 unit loads. Maximum driving capability of the
delay line is 6 unit loads, with a maximum line length of 8 ns.
POWER:
Power dissipation of the M311 module is 5V at 170 rnA (maximum).
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Simplified Diagram
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M402
Photo Mod Clock
The 402 module contains a stable RC-coupled multivibrator that produces standard I OO-ns timing pulses at
adjustable repetition rates.
The module is intended for use as a source of timing signals in a digital system. Repetition rate is adjustable from
I Hz to 500 kHz in two ranges. An internal capacitance, selected by a jumper wire, facilitates coarse frequency
control; and an internal light source provides continuously variable adjustment within the selected range.
ENABLI NG
INPUTS
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Coarse Frequency Range
Frequency Range
Cap
Interconnections Required
250 Hz to 500 kHz
0.0 I IlF
None
I Hz to 6 kHz
2.001lF
N2 - P2
A 2-input OR gate input is provided for start-stop control of the pulse train. A level change from HIGH to LOW
with fall time less than 400 ns is required to enable the clock.
Fine frequency adjustment is obtained by applying a control voltage to pins L2 and M2. This voltage changes the
intensity of a lamp inside the module, which in turn adjusts the recovery time of the multivibrator. The voltage
applied between pins Land M should be limited to the range of OV to 5V.
The following are the input, output, and power characteristics of the M402 module.
INPUTS:
Each ENABLE input presents I unit load. For input characteristics of pins Land M,
refer to text above.
OUTPUTS:
Output pin D supplies positive 100 ns pulses capable of driving 10 unit loads. Output pin E
supplies pulses that are the reverse of pin D. This output is capable of driving 9 unit loads.
POWER:
Power dissipation of the M402 module is 5V at 100 rnA (maximum).
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EI IS DEC7440N
E2 IS OEC7474N
E3 IS DEC7400N
PIN 7 ON EACH IC =OND
PIN 14 ON EACH IC =+5V
R3 IS A .275P
R4
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M452-3
M500
Converter-I/O Bus Receiver
The M500 Converter - I/O Bus Receiver module is an M-series single-height module containing eight converter I/O bus receivers that can accept negative logic levels and convert them to positive levels. Each converter - bus
receiver has a negative input clamped to OV and -3V. The threshold switching level is -1.5V with an input current of 100 JlA. Inverted and noninverted outputs are supplied by each receiver.
+3V
OUTPUT NO.1
(INVERTING)
L -_ _ _ _.:....:....
-1.5 V
OUTPUT NO.2
(NON-INVERTING)
--"VV'v-H
3KA
-15V
15 - 0074
M500 Simplified Diagram
The following are the input, output, and power characteristics of the M500 module.
INPUTS:
Input characteristics are as follows:
Minimum input impedance at OV - 30 kil
Maximum current load to bus - 100 JlA
Inputs are standard negative logic levels of OV and -3V.
OUTPUTS:
Outputs are standard TTL positive logic levels with the following driving capability:
Output No. 1 - 12 unit loads
Output No.2 - 11 unit loads
DELAYS:
Input/Output No. 1 delay - 50 ns
Input/Output No.2 delay - 40 ns
POWER:
Power dissipation in the M500 module is 750 mW (maximum) from -I5V and 800 mW
(maximum) from +5V.
M500 -1
The MSOO module was designed to receive PDP-9 I/O bus signals for devices using positive logic. It provides a
high input impedance. This module is pin compatible with the MSI 0 module.
MSOQ-2
This page intentionally left blank.
MSOO-3
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AN~ MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COP'l'RIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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TRANSISTORS ARE OEC3Q09B
DIODES ARE 0664
RESISTORS ARE r/4W,IO%
IC'S ARE DEC74HQON
PIN 70N EACH IC=GND
PIN 14 ON EACH Ie = +5V
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15-0076
MSlO Simplified Diagram
MSlO-l
THISSCH['-IATIC IS FURNISHED ONLY fOfl TEST "NO '-I"INTEN"NCE PUflPOSES THE
CIRCUITS "RE PROPRIETARY IN NATURE AND SHOULD BE TR(AT[O "CCOROINGlY
COPYRIGHT III., BY DIGITAL [QUIP'-IENT COflPOR"TION
E2
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PIN 14 ON EACH IC"+!5V
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TRANSISTORS ARE DEC 500M
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MSIO-3
M515
Real Time Clock
The M5lS module contains a real time clock that converts conventional sinusoidal power waveforms into timing
gates. Complementary timing gates are available at the output pins of the module (see illustration).
The following are the input, output, and power characteristics of the MSIS module.
INPUTS:
The input is 12 Vac.
OUTPUTS:
The output at pin D2 is capable of driving 36 unit loads, and the output at pin E2 is
capable of driving 31 unit loads.
POWER:
Power dissipation of the MSIS module is SV at 55 rnA and 10V at 30 rnA.
+10V 12Vac
E2
M515
D2
15-0116
MSlS Simplified Diagram
MS1S-1
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M602
Pulse Amplifiers
The M602 contains two pulse amplifiers that provide power amplification, standardize pulse amplitude and
width, and transform level changes into a standard pulse. A negative pulse output is produced when the input is
triggered by a transition from HIGH to LOW. Propagation time between input and output thresholds is 30 ns
(maximum). An internal capacitor is brought out to pin connections to permit the standard SO ns output pulse
to be increased to lIOns (nominal). Recovery time is equal to that of the output pulse width. The input must
have a fall time (10 percent to 90 percent pOints) of less than 400 ns and must remain below 0.8V for at least
30 ns. Maximum PRF is 10 MHz.
The following are the input, output, and power characteristics of the M602 module.
INPUTS:
Each input presents 2.5 unit loads.
OUTPUTS:
Each output is capable of driving 30 unit loads.
POWER:
Power dissipation of the M602 module is 5V at 213 rnA (maximum).
PA 1
F2
E2
OUTPUT
I D2
INTERNAL CAPACITQR*
*JUMPER E2-D2 OR R2-S2 FOR
110n. PULSE WIDTH. STANDARD
PULSE WIDTH IS 50n ••
15 - 017 2
M602 Simplified Diagram
M602-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY.
COPYRIGHT 1967 BY DIGITAL EQUIPMENT CORPORATION
RI
150
PULSE
INPUTS
~~",~6
1 1 M~rO
~
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D
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150
100
112W
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INPUTS
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N
R3
330
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D7
D662
DI4
D662
F
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OUT
L
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D5
D662
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330
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10%
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D6
D662
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33
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330
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330
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D662
DI2
D662
,
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UNLESS OTHERWISE INDICATED:
TRANSISTORS ARE DEC36398
DIODES ARE D664
RESISTORS ARE 1/4W, 5%
CAPACITORS ARE .01 MFD
PIN 7 ON IC; GND
PIN 14 ON IC; +5V
IC IS DEC74H40N
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UNLESS OTHERWISE INDICATED
CAPACITORS ARE IOOV,20%
DIODES ARE D 664
RESISTORS ARE 1.5K, 1/4W, 5%
TRANSISTORS ARE DEC3009B
PIN 7 ON EACH IC =G ND
PIN 14 ON EACH IC=+5V
EI,E3,E5 ARE ()EC7440N
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M606-3
M611
High-Speed Power Inverters
The M611 module contains 14 high-speed power inverters. Each inverter has a maximum propagation delay of
12 ns.
The following are the input, output, and power characteristics of the M611 module.
INPUTS:
Each inverter input presents 1.25 TTL unit loads.
OUTPUTS:
Each inverter output is capable of driving up to 36 unit loads.
POWER:
Power dissipation of the M611 module is 5V at 240 rnA (maximum).
M611-1
~
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THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
02
•
•
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::=::::C7
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::=::::C5
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::=::::C3
C2
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C2,CI,M2
N2,T I
GND
UNLESS OTHERWISE INDICATED
PIN 7 ON EACH IC = GND
PIN 14 ON EACH IC = +5V
IC'S ARE DEC74H40
CAPACITORS ARE .0IMFD 100V
RESISTORS ARE 220 1/4W 10%
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M617
Power NAND Gates
The M617 contains six 4-input NAND gates, each capable of driving up to 30 unit loads. Gate propagation delay
is 25 ns (maximum). Physical configuration and logical operation are identical to the Mil 7.
The following are the input, output, and power characteristics of the M617 module.
INPUTS:
Each input presents I unit load.
OUTPUTS:
Each output is capable of driving 30 unit loads.
POWER:
Power dissipation of the M6l7 module is 5V at 97 rnA (maximum).
M617-1
IH<5 SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE 'UR'OSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1917 BY OIGITAL EQUIPMENT CORPORATION
I
-
-
A2
+5V
NOT USED -15V • - - - - 82
C2, TI
GND
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10
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4
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6
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N
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R3
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NOTES:
PIN 7 ON EACH IC= GND
PIN 14 ON EACH IC=+5V
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REFERENCE DESIGNATION
DINGLY
COPYRIGHT IIITB" OIGITAL EQUIPMENT CORPORATION
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PIN 7 ON EACH IC: OND
PIN 14 ON EACH IC: t5V
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Ii R3
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REFERENCE DESIGNATION
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M632 Simplified Diagram
M632-1
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- 'V
RI8
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82
I5V
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4W,5%
DIODES ARE 0664
TRANSISTORS ARE DEC36398
I C'S ARE OEC74H50
PIN 7 ON EACH Ie = GND
PIN 14 ON EACH Ie = +5V
CAPACITORS ARE .01 MFO
TRANSISTOR & DIODE CONVERSION CHART
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M706
Teletype Receiver
The M706 Teletype Receiver is a serial-to-parallel Teletype code converter self-contained on a double-height
module. This module includes all of the serial-to-parallel conversion, buffering, gating, and timing (excluding only
an external clock) necessary to transfer information in an asynchronous manner between a serial data line or Teletype device and a parallel binary device. Either a S-bit serial character consisting of 7.0, 7.5, or 8.0 units; or an
8-bit serial character of 10.0, 10.5, or 11.0 units can be assembled into parallel form by the M706 through the use
of different pin connections on the module. In the PDP-IS, the Teletype receiver is connected to assemble 8-bit
AD2
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DEVICE
SELECTOR
CODE
ENABLE OS API
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READER ON
r-- ~AU2
AV2
READER
CONTROL
BL2
7
READER
RUN
READER (I)
~
FLAG STROBE BD2 ~
CLEAR FLAG I BJ2
CLEAR FLAG 2 BDI
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BH2
STROBED FLAG
AF2
FLAG
BE2
AE2
,CLOCK"
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ENABLE
BRI
I/O
CLEAR
BF2
ANI
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BN2
ACTIVE (0)
I
CONTROL
PIN CONNECTIONS FOR 5 OR 8
BIT CODE
5 BIT - AM2 TO AJ2
AR I TO GROUND
8 BIT - AM2 TO ARI
AJ2 TO AKI
PIN CONNECTIONS FOR
1.0 UNITS - BP2 TO
BR2 TO
1.5 UNITS - BP2 TO
BR2 TO
2.0 UNITS - BP2 TO
BR2 TO
SERIAL INPUT
READ BUFFER
STOP TIME
BT2
BU2
BSI
BU2
BUI
BT2
BV2
BM2
SHIFT
REGISTER
G!
AN2
BIT I
AT2
BIT 2
AP2
BIT 3
AMI
BIT 4
ALI
BIT 5
AS2
BIT 6
AR2
BIT 7
AK2
BIT 8
AL2
M706 Simplified Diagram
M706-1
characters consisting of 11 units. When conversion is complete, the start and stop bits accompanying the serial
character are removed. The serial character is expected to be received with the start bit first, followed by bits 1
through 8 in order, and completed by the stop bits. Coincident with reception of the center of bit 8, the FLAG
output goes LOW, indicating that a new character is ready for transmission into the parallel device. The parallel
data is available at the BIT I through BIT 8 outputs until the beginning of the start bit of a new serial character
is received on the SERIAL input (see the timing diagram for additional information).
+3V
SERIAL
INPUT
STOP
0
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READER
1
lS-016!
M706 Timing Diagram
In addition to the above listed features, the M706 includes the necessary logic to provide rejection of spurious
start bits less than 1/2-unit long, and to also provide half-duplex system operation in conjunction with the M707.
Device selector gating is also provided; thus, this module can be used on the positive 1/0 bus of a digital system.
The following are the input, output, and power characteristics of the M706 Teletype Receiver.
INPUTS:
All inputs present one TTL unit load (except where noted). When input pulses are required,
they must have a width of 50 ns or greater.
CLOCK:
The clock frequency must be eight times the serial input bit rate
(baud rate). This input can be either pulses or a square wave. Input loading on the CLOCK line is three unit loads.
ENABLE:
The ENABLE input, when brought to ground, inhibits reception of
new characters. It can be grounded any time during character reception, but returned HIGH only between the time the FLAG output
goes to ground and a new character start bit is received at the serial
input. When not used, the ENABLE input should be tied to a source
of+3V.
M706-2
I/O CLEAR:
A HIGH level or positive pulse at this input clears the flag and
initializes the state of the control. When not used, or during reception, the I/O CLEAR input is grounded.
CODE SELECT Inputs: When a positive AND condition occurs at the CODE SELECT inputs, the following signals can assume their normal control functions: FLAG STROBE; READ BUFFER; and CLEAR FLAG I.
These inputs are frequently used to multiplex receiver modules
when a signal such as READ BUFFER is common to many modules. The inputs are also used for device selector inputs when the
M706 is used on the positive I/O bus of a digital system. The
CODE SELECT inputs must be present at least 50 ns prior to any
of the three signals that they enable. If it is desired to bypass the
CODE SELECT inputs, they can be left open and the ENABLE D. S.
line tied to ground.
CLEAR FLAG 1:
A HIGH level or positive pulse at the CLEAR FLAG I input while
the CODE SELECT inputs are all HIGH clears the flag. When not
used, this line should be grounded. Propagation delay from input
rise until the flag is cleared is a maximum of 100 ns. The flag cannot be set if this input is held HIGH.
CLEAR FLAG 2:
A HIGH level or positive pulse at the CLEAR FLAG 2 input, independent of the state of the CODE SELECT inputs, clears the flag.
All other characteristics are identical to those of CLEAR FLAG 1.
FLAG STROBE:
If the flag is set and the CODE SELECT inputs are all HIGH, a
positive pulse at the FLAG STROBE input generates a negativegoing pulse at the STROBED FLAG output. Propagation delay from
the strobe to output is a maximum of 30 ns.
READ BUFFER:
A HIGH level or positive pulse at the READ BUFFER input while
the CODE SELECT inputs are all HIGH transfers the state of the
shift register to outputs BIT 1 through BIT 8. Final parallel character data can be read by this input as soon as the FLAG output
goes to ground. Output data is available a maximum of 100 ns after
the rising edge of this input. See the timing diagram for additional
information.
READER ON:
A LOW level or ground at the READER ON input turns on the internal reader flip-flop. This element is turned off at the beginning
of a received character start bit. The READER ON input can also
be pulsed by tying it to one of the signals derived at output pins
AE2 or BE2.
SERIAL Input:
Serial data received on the SERIAL input has a logical 0 (space)
equal to +3V and a logical I (mark) of ground. The input receiver
on the M706 is a Schmitt trigger with hysterisis thresholds of nominal 1.0V and 1.7V. This allows the SERIAL input data to be
fIltered up to 10 percent of bit width on each transition to remove
noise. The SERIAL input is diode-protected from voltage overshoot
above +5.9V and from voltage undershoot below -0.9V. Input
loading is four unit loads.
M706-3
OUTPUTS:
All outputs can drive ten unit loads (unless otherwise specified).
BITS 1 through 8:
A READ BUFFER input signal transfers the shift register contents
to those outputs with a received logical 1 appearing as a ground
output. If the READ BUFFER input is not present, all outputs are
at logical I. When the M706 is used for reception of 5-bit character
codes, the output data appears on output lines BIT 1 through 5;
and BITS 6, 7, 8 receive logical zeros.
ACTIVE (0):
The ACTIVE (0) output goes LOW at the beginning of the start bit
of each received character and returns HIGH at the completion of
reception of bit 8 for an 8-bit character, or bit 5 for a 5-bit character. Because this signal uses from OV to +3V (at 1/2-bit time after
the FLAG output goes to ground) it can be used to clear the flag
through the CLEAR FLAG 2 input while the FLAG output, after
being inverted, can strobe parallel data out when connected to
READ BUFFER.
If an M706 and M707 are to be used in half-duplex mode, this output should be tied to the WAIT input of the M707 to inhibit M707
transmission during M706 reception. Output drive is eight unit
loads.
POWER:
FLAG:
The FLAG output falls from +3V to ground when the serial character data has been fully converted to parallel form. Relative to
serial bit positions, this occurs during the center of either bit 8 or
bit 5, depending on the respective character length. If the M706 is
receiving at a maximum character rate (i.e., one character immediately following another), the parallel output data is available for
transfer from the time the FLAG output falls to ground until the
beginning of a new start bit. This is stop-bit time plus 1/2-bit
time.
STROBED FLAG:
The STROBED FLAG output is the NAND realization of the inverted FLAG output and FLAG STROBE.
READER (1):
Whenever the internal reader flip-flop is set by the READER ON
input, the READER output rises to +3V. The flip-flop is cleared
whenever a start bit of a new character is received on the SERIAL
input.
READER RUN:
The READER RUN output is used with DEC modified 33 ASR
and 35 ASR Teletypes that have relay-controlled paper tape
readers. The READER RUN output can drive a load of 20 rnA at
+0.7V. The common end of the load can be returned to any
negative voltage not exceeding -20V.
PIN AE2:
The PIN AE2 output is the logical realization of NOT (CLEAR
FLAG 1 or CLEAR FLAG 2 or I/O CLEAR) and is a +3V-toground output level or pulse, depending on the input. The signal
is used to pulse READER ON for control of READER RUN in the
system.
PIN BE2:
The PIN BE2 output is brought from +3V to ground by an enabled
CLEAR FLAG I input. It can be connected to READER ON for a
different form of control of READER RUN.
+3 VOLTS
Pin ADI can drive ten unit loads at a +3V level.
Power dissipation of the M706 is 5V at 400 rnA (maximum).
M706-4
This page intentionally left blank.
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M707-7
M717
Display Control VP15
The M717 module contains the timing and control circuits req uired by the VP 15 point-plotting display. Since
anyone of three scopes can be used in the VP 15 display, the M717 module incorporates the necessary control
circuits for all three scopes. The scopes that can be used are the Tektronix RMS03, the DEC VRI2, and the
Tektronix 611 storage tube in both the store and nonstore modes. A simple patching arrangement selects the
required control circuits for a specific scope. The timing circuits on the module provide the necessary deflection
settling time delays and intensification pulses for all scopes. Light pen circuitry is provided for use with the
RMS03 and the VR 12. A display-done flag circuit and an erase control circuit are included for the 611. In addition, a two-bit brightness register is provided for controlling brightness on the RMS03 and the VRI2.
The power dissipation characteristics of the M717 module are:
IOVat 10
ISVat 10
SVat 130
30Vat 20
rnA
rnA
rnA
rnA
M717-1
•
THIS SCf-'EMATIC IS FURNISHED ONLY rOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATuRE AND SHOULD BE TRlATED ACCORDI"JGLY
COPYRIGHT 1969 BY DIGIlAl EQUIPMENT CORPORATION
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M770
EAE Control
The M770 module contains a 6-bit timing generator and EAE control logic. One of these modules is used in the
PDP-IS central processor equipped with the EAE option (refer to Engineering Drawing D-BS-KE 15-0-4).
The following are the input, output, and power characteristics of the M770.
INPUTS AND OUTPUTS: M770 EAE control module inputs and outputs are standard TTL levels.
POWER:
The power dissipation of the M770 module is 5V at 500 rnA (maximum).
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M771
Internal lOT Decoder
The M771 module contains combinational logic circuits to decode bits 6 through 13 of the Input/Output
Transfer (lOT) instructions of the PDP-IS.
The following are the input, output, and power characteristics of the M771 module.
INPUTS:
The table below lists all input connections and the TTL unit loading they present.
Name
Pin
NOT INT DSOO
INT DS01
INT DS02
INT DS03
INT DS04
INT DSOS
INT SDOO
INT SD01
INT IOPl
INT IOP2
INT IOP4
INT IOPI
MEM
Al
P2
D2
V2
U2
VI
M2
N1
S2
Sl
M1
D1
FI
Loading
S
4
4
6
S
S
S
4
4
4
4
1
I
OUTPUTS:
Each decoder output (except lOT 03XX pin PI) is capable of driving 10 unit loads. Pin PI
is capable of driving 7 unit loads.
POWER:
The power dissipation of the M771 module is SV at 74 rnA.
M771-1
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PIN 7 ON EACH IC: GND
PIN 14 ON EACH IC = +5V
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E3,E4,E8,EII,EI2 ARE OEC7430N
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M772
Console Control No. 1
The M772 module contains 12 storage flip-flops and output gating circuits for generating 24 register strobes in
response to a 12-position rotary switch and a slide switch. The module is used in the console of the PDP-IS to
provide the strobes required for displaying selected data (refer to Engineering Drawing D-BS-KPIS-0-44).
The following are the input, output, and power characteristics of the M772 module.
INPUTS AND OUTPUTS: M772 inputs and outputs are standard TTL levels.
POWER:
Power dissipated in the M772 module is SV at 440 rnA (maximum).
M772-1
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M773
Console Control No. 2
The M773 module decodes the console switch and key signals. A 6-count register generates timing pulses that
strobe the address, data switches, and key functions such as STOP, START, CONTINUE, EXAMINE, and
DEPOSIT) to the I/O processor. The M773 module also contains logic circuits for controlling the repeat speed
functions (refer to Engineering Drawing D-BS-KPIS-0-4S).
The following are the input, output, and power characteristics of the M773 module.
INPUTS AND OUTPUTS: M773 inputs and outputs are standard TTL levels.
POWER:
The power dissipated in the M773 module is SV at 500 rnA (maximum).
M773-1
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M775
Time State Generator
The M775 module contains a 5-18 MHz variable clock and a four-stage ring counter. This module is used in the
central processor of the PDP-IS to divide each of the three time states of each cycle into four phases. The clock
frequency is adjusted to obtain a period equivalent to one time phase.
The following are the input, output, and power characteristics of the M775 module.
INPUTS:
OUTPUTS:
The table below lists all input connections and the TTL loading they present.
Name
Pin
Loading
REPEATTS2
SING TIME LOOP
TS2
ADD*TS2*E
ADD*TS2*E
CLOCK
CLEAR
STOP CLOCK
FI
EI
CI
Al
P2
R2
T2
PI
1.25
3.75
1.25
1.25
1.25
10
10
1.25
The table below lists all output connections and their unit load-driving capabilities.
Name
TIME STATE I
TIME STATE I
TIME STATE I
TIME STATE 2
TIME STATE 2
TIME STATE 2
TIME STATE 2A
TIME STATE 2A
TIME STATE 3
TIME STATE 3
TIME STATE 3
HS CLOCK
HSCLOCK
POWER:
Pin
Drive
Jl
K2
11
H2
12
L2
DI
M2
V2
D2
N2
E2
F2
9
36
36
9
36
36
8
36
9
36
36
II
36
Power dissipated in the M775 module is 5V at 325 rnA (maximum).
M775-1
THIS SCHEMATIC IS FURNISHED ONLY fOR TEST AND "''''INTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE 1R£ ... TEO ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
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M901
Flexprint Cable Connector
The M90 I module allows 36 lines to be used as signals and/or grounds. The lOOn resistors connected in series
with the module pins A2, B2, U I, and V I are provided to afford some measure of protection if these pins are
inadvertently connected to a source of supply voltage.
The recommended current per line is 100 rnA (maximum).
M901-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIET.... RY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT
BY DIGITAL EQUIPMENT CORPORATION
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TITLE
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NUMBER
M901-0-1
PRINTED CIRCUIT REV
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M902
Terminator Card
The M902 module contains 18 terminating resistors connected to ground. Each resistor value is lOOn, 1/4W at
S%. This single-height board replaces the output cable of the last memory used on the PDP-IS memory bus.
Two of these boards are req uired for each PDP-IS system.
Ground pins are:
C2; F2; 12; L2; N2; R2; U2;
A I; C I; F I ; K I ; N I; R I ; and Tl.
The following are the input, output, and power characteristics of the M902 module.
INPUTS:
There are 18 inputs, one to each resistor.
OUTPUTS:
There are no outputs.
POWER:
The power dissipation of the M902 is 1.12SW (maximum).
M902-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULO BE TREATED ACCORDINGLY.
COPYRIGHT 191111 BY DIGITAL EQUIPMENT CORPORATION
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CODE
CS
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M902-0-1
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M904
Coaxial Cable Connector
The M904 connector is a single-size, double-sided board.
This connector provides high-density cable connections using coaxial cable. Provisions are made for connection
of two 9-conductor coaxial cables to the M904 connector. Eighteen signal leads and grounds are used.
The signal leads are:
B I; D I; E I; HI; J I; Ll; M I; PI ; S I
D2; E2; H2; K2; M2; P2; S2; T2; and V2.
The common (ground) leads are:
AI; CI; FI; KI; NI; RI; Tl;
C2; F2; 12; L2; N2; R2; and U2
M904-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 BY DIGITAL EQUIPMENT CORPORATION
I
GND
,
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GND C2
81
02
CI
E2
01
F2
EI
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J2
HI
K2
JI
L2
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KI
M2
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NI
R2
PI
S2
RI
T2
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CODE
CS
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M904-0-1
IR~V
lsi I I I I I I
M909
Terminator Card
This is a standard single-height M-series board with 18 terminating resistors connected to ground. All the resistors
are
68n, 1/4W at 5%.
GND Pins are: C2; F2; J2; L2; N2; R2; U2; AI; CI; FI; KI; NI; RI; and Tl.
The following are the input, output, and power characteristics of the M909 module.
INPUTS:
There are IS inputs; one to each resistor.
OUTPUTS:
There are no outputs.
POWER:
The power dissipation of the M909 is I.SW (maximum).
These boards replace the output cable of the last peripheral on the positive PDP-IS I/O bus.
M909-1
r'"
THIS SCHEMATIC IS FURNISH£D ONLY FOR HST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREAHD ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
C2
D2
i
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F2
H2
J2
K2
L2
M2
P2
N2
R2
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T2
(
r
RI6
U2
V2
9
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R 18
GND
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N
b
AI
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CI
DI
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FI
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HI
JI
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l
KI
b
LI
(>R7
l
MI
(> R8
(>R9
6
6
6
NI
PI
RI
SI
TI
UNLESS OTHERWISE INDICATED
RESISTORS ARE 68 1/4W 5%
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M910
M911
Memory Bus CP Terminator Card
The M911 module contains eighteen lOOn terminating resistors. Each resistor is connected to a common +5V
source. The resistors are used as load resistors to terminate all the memory bus lines at the CP end in the PDP-15.
Power dissipation is 1.25W (minimum) and 5.0W (maximum).
M9ll-l
THIS SCHEMATIC 15 FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT It •• BY DIGITAL EQUIPMENT CORPORATION
+~V
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GND
C2
C3
02
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F2
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RI
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H2
J2
R2
L2
K2
M2
N2
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R3
P2
R5
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R7
RB
R9
Ar
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....
V2
U2
RI2
RII
RI3
RI4
RI5
RI7
RI6
H~
RIB
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AI
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01
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FI
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HI
KI
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c
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MI
NI
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CAPACITORS ARE 6.BMFD
RESISTORS ARE 100 1/2W ~%
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ElA
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momoomo
EQUIPMENT
CORPORATION
...... VN ..... O
:,
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TITLE
MEMORY BUS CPTERMINATOR
M911
NUMBER
SIZE JCOOE
8
CS
M 911-0-1
PRINTED CIRCUIT REV
l
REV
IAI I I I I I I
M912
I/O Bus Connector
The M912 module is a double-height and double-sided FLIP CHIP connector card used in fabricating I/O bus
interconnect cables for peripheral devices.
Four of these cards are required to fabricate a BC09B cable, and two cards are needed to fabricate a BC09C cable.
M912-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD 8E TREATED ACCORDINGLY
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
AAI
BAI
ABla
Q)
ACI
Q)
BBI a
GND
AC2
ADla
Q)
Q)
a AD2
BDI a
Q)
<2>
a BD2
AEI a
Q)
Q)
a AE2
BEla
Q)
<2>
a BE2
BHla
Q)
Q)
a BH2
BJI a
Q)
BKI
~
Q)
a BK2
Q)
a BM2
AF2
AFI
AHla
Q)
Q)
AJI a
Q)
no.
AJ2
I])
a AK2
AKI
BFI
a AH2
BF2
~
s=\0
GND
BC2
BCI
ALI a
Q)
AMla
III
ANI
BJ2
0-----'
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~
AL2
BLI a
(J)
aAM2
BMla
(J)
AN2
B L2
BNI
BN2
N
N
API a
Q)
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a AP2
ARI
ASI a
AT!
Q)
(J)
BPI a
AR2
a BP2
Q)
BRI
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a AS2
BSI a
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a AT2
BTl
"
Q)
BR2
Q)
a BS2
Q)
a BT2
AU2
BU2
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Q)
a BV2
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a AV2
Q)
SPLIT LUGS
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DATE
1·11-11
DATE
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TRANSISTOR & DIODE CONVERSION CHART
DEC
ElA
DEC
ElA
mOmOOmD "10 I
BUS CONNECTOR CARD
I
M912
EQUIPMENT
CORPORATION
SIZE
CODE
B
CS
................ O ............ CHU • • TT.
PRINTED CIRCUIT REV
NUMBER
M912 - 0
I
JAJ J J J
I
LI
REV
J
M915
Console Cable Connector
The M915 module is used in conjunction with the M901 module and a Flexprint cable to fabricate the I bus
interconnect cable. The M915 module contains twenty-four 750n terminating resistors and twenty-four 0.01 JlF
bypass capacitors. Each resistor is connected to a common +5V source. The resistors are used as load resistors
to terminate the I bus lines in the PDP-I 5 console, and the capacitors bypass the I bus lines to ground.
Power dissipation of the M915 module is 5V at 330 rnA.
M915-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES, THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT I I I ' BY DIGITAL EQUIPMENT CORPORATION
AI
81
CI
Ll
R3
----<
01
EI
FI
JI
~
HI
l l l l
?R13
'-----<
KI
MI
LI
NI
PI
RI
51
GND
TI
UI
VI
~
t
RI7
RI9
R20
R21
R22
~
~
~
R23
\
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'------<
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t:
,----<
.<
(
(
(
V
FLEXPR INT
+~V
rs::
\0
A2
82
GND
C2
02
E2
VI
N
'-----'
R4
+H--<
'-----<
6.8~f
l l
~2
H2
J2
K2
L2
~
~
M2
N2
P2
R2
S2
~
Tcf
U2
V2
t t l: t t:
35V
20%
(
\.
(
(
)
V
FLEX PR INT
UNLESS OTHERWISE INDICATED
RES ISTORS ARE 390, 1/4 W, 5%
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DATE
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~DmDDmD
TITLE
DATA SELECTOR MI701
IMI701-0-1
EQUIPMENT
CORPORATION
SIZE! CODE
... "'y ........ o, ........... CHuSI;TT5
PRINTED CIRCUIT REV
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M1713
16-to-1 Data Selector
The M1713 16-To-1 Data Selector contains a single DEC74150 integrated circuit. It is used in the output
multiplexer section of the FPI5 Floating-Point Processor where up to 16 major register outputs are selected for
transfer to the common MPO bus. The block schematic of the output multiplexer is shown on D-BS-FP 15-0-03
of the FP15 drawings.
Data inputs are selected by combinations of data select signals MXA, MXB, MXC, and MXD, which are generated
by the multiplexer control logic shown on D-BS-FPI5-0-05. The strobe inputs are wired to ground so that each
IC is always enabled. A typical truth table for the 16-To-I Data Selector is shown in the following table.
Data Select Inputs
MXD
0
0
0
0
0
0
0
0
I
1
1
1
1
1
1
I
MXC
0
0
0
0
I
1
I
I
0
0
0
0
1
1
1
I
MXB
0
0
I
I
0
0
I
I
0
0
I
1
0
0
1
1
MXA
0
I
0
I
0
0
0
I
0
1
0
I
0
1
0
I
Data Input*
Selected
.=r
DIR12
JEAI2
ADD30
ADDI2
FMQ30
FMQI2
FMB30
FMBI2
EPBl2
FMA30
FMA12
EPAl2
IRI2
BMB30
BMBI2
MPI12
MPI 12 H
E2
BMB 12(1) H ~~
R2
17
S
16
~~~2~~)(~)HM2 :~
EPA 12(1)H~;
13
FMA 12(1)H HI
12
FMA 30 (1)H F ' "
16-TO-l
EPB 12(1)H L1
10
OATA
FMB 12 (1) H 51
07 SELECTOR
FMB 30(1)H RI
g~ M1713
FMQ 12 (1)H P1
04
D18
FMQ 30 (1) H Nl
~gg ~20 ~
JEA
Ml
12(1)H;~
DIR 12 (1) H
g~
01
00
ABC
MXA
MXB
MXC
MXD
D
L
L
L
L
'Signal mnemonics vary as shown on D-BS-FPlS-O-03.
Note that the output is the complement of the selected
input.
INPUTS:
Each input represents 1 unit load.
OUTPUTS:
The output is capable of driving up to 10 unit loads.
POWER:
Typical power dissipation is 200 mw.
M17l3-1
MPO
12 L
15-0563
om
ns,
'HIS SCHEMA'" IS FU",ISHED
FOP
AND MAINOFNANCE PU",OSES 'H
C1Rcuns ARE PROPRIUAR'I IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 19TO BY DIGITAL EQtJW,1fNT CORPORATION
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J
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+5V
S2
T2
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NI
PI
7
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W
JI
-.
KI
M2
N
L2
K2
E2
F2
H2
J2
UNLESS
OTHERWISE
CAPACITORS
INDICATED:
ARE .01 UF, IOOV, 20%
IC IS A DEC74150
N2
R2
I
5
•
3
2
EI
I
LI
HI
0
6
RI
SI
J.
8
23
8
22
21
20
19
18
17
16
15
I.
13
II
9
wb lO
10
P2
.-
II
I
I
I
I
A
8
C
0
+5V, A2
S
'---
12
C2,TI
11
1] 6.BUF
+
35V
2
3
TTl
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0
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1
3
RCUIT REV
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W010
Clamped Loads
The WO I 0 module contains fifteen identical 10 rnA clamped loads, each consisting of a resistor and a diode.
Each load resistor is connected to a common -15V source. The clamping diodes are connected to a -3V source,
which is obtained by a resistor-diode voltage divider.
Power dissipation of the WO I 0 module is 15V at 250 rnA.
WOlO-I
THIS SCHEMATIC IS FURNISHED ON" FOR TEST AND MAINTENANCE PURPOSES THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 19 •• BY DIGiTAL EQUIPMENT CORPORATION
I
B-15V
..l)
~2
~ioo
~
04
~~OO ,
,~
---<
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0
r
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1,500
;B
-
F
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RB
1,500
010
012
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M
L
K
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031
.0662
022
",0662
030
.0662
021
4.0662
029
0662
-3V
RI5
1,500
C2
.01
H
RI9
1,500
'----
'----
L-------...
L-------...
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015
RI7
1,500
MFO
020
4·0662
02B
0662
4
I
C-GND
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R3
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09
CI
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RI3
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0662
V
l' g~~2
MFO
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C3
1'.01
MFO
" g::2
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0662
g~662
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-3V
RI6
1,500
RIB
1,500
UNLESS OTHERWISE INDICATED:
RESISTORS ARE 1/4; 5%
DIODES ARE 0664
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DEC
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mamDoma
EQUIPMENT
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"""'''''''''''0, "''''SS"CHUSETTS
TITLE
CLAMPED LOADS
DEl
CS WOIO-O-I
SIZEj CO
B
PRINTED CIRCUIT REV
NUMBER
IAI
I
WOIO
I
REV
I I I I I
W028
Cable Connector for Levels and Pulses
The W028 module provides cable connections to the FLIP CHIP mounting panel. The cable is a 19-conductor
ribbon with 9 signal leads and 10 shields. The signal leads are connected to pins D, E, H, K, M, P, S, T, and V.
The shields are internally connected together and to pins C, F, J, L, N, R, and U.
W028-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY
COPYRIGHT 1968 iilY DIGITAL EQUIPMENT CORPORATION
00000
I
I
I
I
I
I
I
I
I
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I
I
I
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1
I
I
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0
I
0
P
I
?I
I
I
0
0
T
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PARTS LIST A-PL-W028-0-0
DRN
DATE
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SIZE
CODE
B
CS
NUMBER
W028-0-1
PRINTED CIRCUIT REV
C
A
W076
Teletype Connector
The W076 module is a universal interface module used in controlling a Teletype from logic using positive
voltages of +5V or + 1OV. The module is soldered to a cable that connects the Teletype to a computer.
Networks contained on the module set the current through the keyboard contacts and selector drive magnet.
Either -15V or -30V can be used across the commutator.
Power dissipation of the W076 is +5V at 25 rnA or + I OV at 25 rnA; -15V at 4 rnA or -30V at 51 rnA.
W076-1
THIS SCHEMATIC IS fURNISHED ONLY FOR TEST AND MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1967 IiiY DIGITAL EQUIPMENT CORPORATION
TYPICAL PIN ASSIGNMENTS
A
r
F
t
f
R3
6
~r 06
7
B
C4
r- C7
C3
r- C6
C
SPUT
LUGS
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00
00
"0 00
00
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ORB 102
.... "
U
Q
00 0
00 0
000
00 0
...
I;}
M. HALLER
....
+SY
C
GND
GNO
GND
LOGIC INPUT
+SV
LOGIC INPUT
-
-
LOGIC INPUT
H
M
READER ENABLE READER ENABLE READER ENABU
U
D
LOGIC OUTPUT
M
D
E
V
-
-
-
K
LOGIC OUTPUT
-
LOGIC OUTPUT
-ISY
-30V OPTIONAL -30Y OPTIONAL -30Y OPTIONAL
DATE
~-18-67
EI.
5-23-67
_eSS40
IIPSIIM
DATE
0671
IN3653
R. SOGGE
!5-ze-&?
DATE
~8
K
",C2
QI
R8
R6
R7
R3 R4
R2
RI
RS
DI-D8
C2-C7
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TRANSISTOR & DIODE CONVERSION CHART
DEC
DATE
N. PERRYMAN
PROD.
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REFERENCE DESIGNATION
CHK'O
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-ISY
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DRN.
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~'QI
R7
R2
N
+IOV
U
RS
RELAY
8
A
H
8:1:,8L
DC08
PIN
DEC
ElA
TRANSISTOR DEC65340
RES. 1.5K 1/4W S% CC
RES. I.IIK 1/2W 10% CC
RES. 10k 1/4W 10% CC
RES. 750 1/2W 5% CC
RES. 750 2W 5%
CC
RES. IK
IW
10% CC
RES. 120 1/2W 5% CC
DIODE 0671
CAP••0IMFD 100V 20% DISC
CAP. IMFD 150V 10% FOIL
PARTS LIST
DESCRIPTION
PARTS LIST
TITLE
mamlOla S'ZEjCODEl
EQUIPMENT
CORPORATION
MAVNARD, M .......C ... U • • TT.
B
1503409
1300391
1300400
1300481
1300354
1301984
1301499
1300243
1103309
1001610
1000063
A-PL-W076-0-0
PART NO.
TELETYPE
CONNECTOR W076
CS
NUMBER
W076-0-1
PRINTED CIRCUIT REV
IROV
101 1 1 1 1 1 1
I
W714
Switches
The W714 module contains two switches accessible at the back of the module. These switches are used as bank
selection switches for the MM 15 memory extension and the MX 15A multiplexer.
W714-1
THIS SCHEMATIC IS FURNISHED ONLY FOR TEST ANO MAINTENANCE PURPOSES. THE
CIRCUITS ARE PROPRIETARY IN NATURE AND SHOULD BE TREATED ACCORDINGLY.
COPYRIGHT 1969 BY DIGITAL EQUIPMENT CORPORATION
~
1
3000 3ZIS
I
0
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-..l
f"
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)(
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H38WnN
: :'
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c
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..
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UNLESS OTHERWISE INDICATED:
ARE SPLIT LUGS
SWITCHES ARE MICRO-SWITCH 6AT56-T2
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PROD.
DEC FORM NO.
ORB 102
L .f
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DATE
J-Z-7.1
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TRANSISTOR & DIODE CONVERSION CHART
DEC
EIA
Jlnl?"
DEC
EIA
mamaDma
••
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$AE?A~
TITLE
SWITCH MODULE W714
~=-r=~r--~~;;;;-----TREv~
CORPORATIONI---L_-'--:--_ _
DATE
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W850
I/O Connector
The W850 module is a double-height FLIP CHIP connector card used in fabricating I/O bus interconnect cables
for peripheral devices.
Two of these modules are used to terminate each side of a cable having 36 twisted pairs, thus forming the BL09A
cable assembly. One wire of every twisted pair is connected to ground, while the signals carried by each of the
36 signal wires are clamped to -O.6V and -3.0V by diodes.
Power dissipation of the W850 module is 15V at 250 rnA (maximum).
W850-1
THIS "CHEMA III IS I UR'
'. I ?~L" ~(1R Tf ST ANll MA;NH "A"Ct .>:~';-:,~E,S, T HE
fIRCU,TSARlPR'"
,""ATl'Hl
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,
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GND
AC
g:'2
05
0662
C2
I
J
R2
210
10""
AB,
J2A
DI1
D2.
DI.
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AD
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..,.015
D'4
AN
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AJ
... P14
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BRN
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D41
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AL
GRN
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AM
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BM
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AN
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BN
D2
AP
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BP
AR
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B/"
BR
I
06621
R4
210
ID"
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BB,-15V
BJ
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023 .....
,
I
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16
I
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g~~2 ~
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043 .....
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I
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0662 I C6
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I
I
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GND
BC
BK
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AC
GND
D4
C'
0662
H'
0662
1
0662
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I
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