DEC 9 L HMAA D Maintenance Manual PDP Volume 1
DEC-9-L-HMAA-D Maintenance Manual PDP-9-L Volume 1 DEC-9-L-HMAA-D Maintenance Manual PDP-9-L Volume 1
User Manual: DEC-9-L-HMAA-D Maintenance Manual PDP-9-L Volume 1
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Digital Equipment Corporation
Maynard, Massachusetts
~DmDD~D
Maintenance Manual
PDP-giL
Volume I
DEC-9/L-HMAA-D
~
(
1
PDP-gIL
Maintenance Manual
Volume I
DIGITAL EQUIPMENT CORPORATION d MAYNARD. MASSACHUSETTS
First Printing February 1969
Copyright
© 1969 by Digital Equipment Corporation
Instruction times, operating speeds and the like ~re included in this manual for reference only; they are not to
be taken as specifications.
The following are registered trademarks of Digital
Equipment Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
PDP
FOCAL
COMPUTER LAB
ii
)
CONTENTS
Page
CHAPTER 1
INTRODUCTION
1.1
Physical Description
1-1
1.2
Functional Description
1-1
1.3
Reference Documents and Programs
1-1
1.4
Reference Conventions
1-2
1.5
Terminology
1-4
1.6
Engineering Drawings and Circuit Schematics
1-5
1.7
System Specifications
1-5
CHAPTER 2
CONTROLS AND INDICATORS
')
2.1
Operator Console
2-1
2.2
Marginal Check Panel
2-6
2.3
Core Memory Banks
2-6
2.4
Teletype Unit
2-6
2.5
Operating Procedures
2-6
2.5.1
Manual Data Storage and Modification
2-7
2.5.2
Storing Binary Data Using READ IN Key
2-10
2.5.3
Storing Data Under Program Control
2-10
2.5.4
Assembl ing Programs
2-10
2.5.5
Teletype Code
2-11
2.5.6
Maintenance Programs
2-11
CHAPTER 3
SYSTEM DESCRIPTION
3.1
Computer Organization
3-1
3.2
Central Processor
3-1
3.2.1
Control Memory (CM)
3-1
3.2.2
Adder (ADR)
3-2
3.2.3
Accumulator (AC)
3-2
3.2.4
AC Link (Link)
3-2
3.2.5
Arithmetic Register (AR)
3-2
3.2.6
Optional Multiplier-Quotient Register (MQ)
3-2
3.2.7
Program Counter (PC)
3-2
3.2.8
Instruction Register (IR)
3-2
iii
CONTENTS (Cont)
Page
3.2.9
3.3
3-2
Memory Buffer Register (MB)
3-3
Core Memory System
3.3.1
Direct Addressing
3-3
3.3.2
Indirect Addressing
3-3
3.3.3
Autoindexing
3-3
3.3.4
Extend Mode Addressing
3-3
3.4
I/o Control
3-3
3.5
Instruction Word Formats
3-5
3.5.1
Memory Reference Instructions
3-5
3.5.2
Augmented Instructions
3-5
CHAPTER 4
CONTROL MEMORY SYSTEM
4.1
Organization
4-1
4.2
Timing and Control
4-2
4.3
Control Memory G920
4-3
4.4
Address Selectors G210
4-3
4.5
Current Sources
4-4
CHAPTER 5
CENTRAL PROCESSOR
5.1
5-1
Central Processor Logic
5.1.1
Fetch Cycle
5-1
5.1.2
Defer Cycle
5-2
5.1.3
Autoindexing
5-3
5.1.4
lAO Cycle
5-3
5.1.5
Execute Cycle
5-4
5.1.6
Memory Reference Instructions
5-4
5.1.7
Operate (OPR) Instructions
5-17
5.1.8
Input/Output Transfer (lOT) Instructions
5-25
CHAPTER 6
CORE MEMORY SYSTEM
6.1
Organization
6-1
6.2
Detailed Circuit Analysis
6-4
6.2.1
Memory Control and Timing
6-4
6.2.2
Memory Addressi ng
6-7
iv
CONTENTS (Cont)
Page
6.2.3
Address Selection
6-7
6.2.4
Bit Sensing During Read
6-8
6.2.5
Voltage Regulation and Selection Drive
6-9
6.2.6
Inhibiting During Write
6-10
CHAPTER 7
CONSOLE POWER CONTROLS
7.1
7-1
Manual Controls
7.1. 1
Power Turn-On
7-1
7.1.2
START Key
7-1
7.1.3
PROGRAM STOP Key
7-2
7.1.4
CONTINUE Key
7-3
7.1.5
DEPOSIT THIS
7-3
7.1.6
DEPOSIT NEXT
7-5
7.1.7
EXAMINE THIS
7-5
7.1.8
EXAMINE NEXT
7-5
7.1.9
READ IN Key
7-6
7.1.10
I/o
7-8
7.1.11
REPT and REPEAT SPEED Switches
7-9
7.1.12
SING INST and SING STEP Switches
7-9
7.2
RESET Key
7-9
Display Indicators
7.2.1
REGISTER Indicator
7-9
7.2.2
Link Indicator
7-10
7.2.3
MEMORY BUFFER Indicator
7-10
7.2.4
INSTRUCTION Indicator
7-10
7.2.5
PIE Indicator
7-11
7.2.6
ClK Indicator
7-11
7.2.7
SING STEP Indicator
7-11
7.2.8
SING INST Indicator
7-11
7.2.9
REPT Indicator
7-11
7.2.10
PRGM STOP Ihdic-ator
7-11
7.2.11
DAT A Ind icatbr
7"-11
7.3
7-11
Power ContrGlI
7.3.1
Primary Power Distribution
7-11
7.3.2
Power Supp Iy
7-13
v
l.
CONTENTS (Cont)
Page
CHAPTER 8
INPUT/OUTPUT CONTROL
8.1
Program-Controlled Data Transfers
8-1
8,1.1
I/O Bus Connections
8-2
8.1.2
Block Diagram Discussion
8-2
8.1.3
Device Selector WI03
8-4
8.1.4
Input Transfers
8-4
8.1.5
Output Transfers
8-6
8.1.6
I/O Skip Facility
8-6
8.1.7
Program Interrupt Facility
8-6
8.1.8
I/O Status Check Fac i I ity
8-9
8.2
Data Channel Transfers
8-10
8.2.1
I/O Bus Connections
8-12
8.2.2
Multiplexer WI04
8-12
8.2:3
Break Synchronization
8-12
8.2.4
WC Cycle
8-13
8.2.5
CA Cycle
8-14
8.2.6
Data Input Cycle
8-15
8.2.7
Data Output Cycles
8-15
8.2.8
Add-to-Memory Facil ity
8-16
8.3
API Channel Transfers
8-16
8.4
Transfer Priorities
8-17
CHAPTER 9
ASR-33 TELETYPEWRITER
9.1
Keyboard/Reader
9-1
9.1.1
Functional Description
9-1
9.1.2
Keyboard Control
9-1
9.1.3
Reader Control
9-3
9.1.4
Data Transfer Instructions
9-3
9.2
Tel epr inter/Punch
9-4
9.2.1
Functional Description
9-4
9.2.2
Teletype Load Sequence (TLS)
9-5
9.2.3
Skip on Teleprinter Flag
9-5
Hardware Read-In (HRI) Operation
9-6
9.3
vi
.'
CONTENTS (Cont)
Page
9.3.1
Functional Description
9-6
9.3.2
Reader Control
9-6
9.3.3
High Speed Read/Punch Circuitry
9-7
CHAPTER 10
MAINTENANCE
10.1
Equipment Required
10-1
10.2
Preventive Maintenance
10-1
10.2.1
Mechanical Checks
10-1
10.2.2
Electrical Checks
10-1
10.2.3
Marginal Checks
10-3
10.3
)
10-15
Corrective Maintenance
10.3.1
Module Handling
10-15
10.3.2
Built-in Checks
10-15
10.3.3
System Troubleshooting
10-16
10.3.4
Section Troubleshooting
10-16
10.3.5
Logic Troubleshooting
10-16
10.3.6
Module Troubleshooting
10-16
APPENDIX A
BASIC INSTRUCTION REPERTOIRE
ILLUSTRA nONS
1-1
Programmed Data Processor PD P-9/L
x
1-2
Basic PDP-9/L Layout, Front and Rear
1-2
1-3
PDP-9/L System Configuration and Optional Accessories Block Diagram
1-3
2-1
PDP-9/L Operator Console
2-1
2-2
Marginal Check Panel
2-7
2-3
Teletype Model ASR33 Console
2-7
3-1
PDP-9/L Functional Diagram
3-1
3-2
Memory Reference Instructions
3-4
3-3
Operation Instruction Word Format
3-6
3-4
lOT Instruction Word Format
3-7
4-1
Control Memory System, Block Diagram
4-1
4-2
CM Line Selection, Line 21
4-3
5-1
ADD Instruction Logic
5-6
5-2
AND Logic
5-7
vii
ILLUSTRATIONS (Cont)
Page
5-3
lAO Instruction Logic For: DAC, CAL, JMS, and DZM
5-10
5-4
ISZ Instruction Logic
5-11
5-5
JMP Instruction Logic
5-12
5-6
LAC Instruction Logic
5-14
5-7
SAD Instruction Logic
5-15
5-8
TAD Instruction Logic
5-16
5-9
XOR Instruction Logic
5-18
5-10
OPR Timing
5-18
5-11
lOT Timing
5-26
6-1
Typical Core Memory
6-1
6...2
Core Memory Stacking Arrangement (Theoretical)
6-2
6-3
MC71A Core Memory System Block Diagram
6-3
6-4
Core Rowand Core Column Selection
6-4
6-5
X and V-Axis Selection Scheme for 18 Planes
6...4
6-6
Core Memory Winding Scheme
6-5
6-7
MC71-A Timing Diagram
6-6
6-8
Address Selection, Simplified Schematic
6-8
6-9
X-Axis
7-1
Initial Set-Up DEPOSIT or EXAMINE Timing
7-4
7-2
READ IN Mode Timing
7-7
7-3
REGISTER DISPLAY Signal Paths
7-10
7-4
Power Supply 712, Block Diagram
7-13
7-5
Marginal Check Switch Positions, Simplified Schematic
7-14
8-1
Program-Controlled I/O Interface
8-2
8-2
I/O Device Control Logic
8-3
8-3
Device Selector Wl03, Schematic Diagram
8-5
8-4
Program Interrupt Timing
8-8
8-5
Multiplexer Wl04, Logic Diagram
8-13
9-1
Perforated Tape Format
9-2
9-2
Basic Data Transfer, Functional Diagram
9-3
10-1
Display MC Form
10-4
10-2
Tel etype Tests MC Form
10-5
10-3
ISZ MC Form
10-6
10-4
Special Options MC Form
10-7
10-5
High-Speed Reader MC Form
10-8
R/W Drive
Selection Simplified Schematic
viii
6-9
ILLUSTRATIONS (Cont)
Page
10-6
EAE MC Form
10-9
10-7
Basic Exerciser Test MC Form
10-10
10-8
MC71 Memory MC Form
10-11
10-9
Marginal Check Panel
10-13
10-10
Marginal Switch Panel
10-14
TABLES
1-1
Reference Documents
1-3
1-2
Maintenqnce Program Documents
1-5
2-1
Operator Console Controls and Indicators
2-1
2-2
Marginal Chec;:k Panel Controls and Indicators
2-7
2-3
Teletype Controls and Indicators
2-9
3-1
Reserved Core Memory Locations
3-3
6-1
W712/B09 Combi ndti ons
6-5
7-1
Input Power Adjustments
7-12
8-1
I/O Status Bit Assignments
8-10
10-1
Equipment Required
10-2
10-2
Power Supply Output Checks
10-3
ix
.'
Figure 1-1
Programmed Data Processor PDP-9/L
x
CHAPTER 1
INTRODUCTION
interrupt, and the power fa i lure detecti on opti ons .
Control logic for memory extension, memory parity,
and memory protection options is also wired in the two
wings.
This manual is one of several documents related to the
PDP-9/L. It provides the user with a basic understanding of the system capabilities and assumes that
the user is familiar with the technology of similar
computer systems. For. complete and comprehensive
coverage in his area of interest, the user should refer
to the documents listed in Table 1-1 at the end of this
chapter.
1.2 FUNCTIONAL DESCRIPTION
The PDP-9/Lis a general purpose, solid-state digital
c;:omputer designed for data handling in a scientific
laboratory, q computation center I or in a real-time
process control system. Figure 1-3 is a functi onal
block diagram of the PDP-9/L GPC. The system is a
single-address 18-bit computer using lIs complement
arithmetic which is program-convertible to 2 1s complement notation to facilitate multiple precision
operati ons. Indirect addressing to one level and
autoindexing features afford programming flexibi lity .
The 4096-word core memory provides random access to
any word within 1 .5 fJS.
Operation and maintenance information for the Programmed Data Processor PDP-9/L, manufactured by
Digital Equipment Corporation, Maynard, Massachusetts are provided in this manual. It consists of two
volumes. Volume I describes the basic computer system and discusses the logic circuits in terms of the
computer's instruction repertoire. Manual operations
and maintenance considerations are also included in
this volume. Volume II contains a complete set of
engineering drawings for the basic computer system.
The I/o bus system accommodates up to 64 low-speed
peripheral devices under program control, up to 8
high-speed devices optionally multiplexed in 8 devicecontrolled data channels (DCH), and up to 28 devices
in an optional 32-channel automatic priority interrupt
(API) system. The program-controlled transfer system
includes the Teletype printer with a reader/punch.
Program-controlled transfer operati ons inc lude program
interrupt (PI), I/o skip, and I/o status checking
faci Iiti es.
1 . 1 PHYSICAL DESCRIPTION
With the exception of the ASR33 Teletype Unit, the
basic PDP-9/L (Figure 1-1) is self-contained in a
single DEC Type CAB-31 metal cabinet. Four casters
permit cabinet mobility. No special power sources,
air conditioning or floor bracing are required. The
teletype unit is supplied with its own mounting stand.
Figure 1-2 shows the front and rear dimensi onal views
of the PDP-9/L layout.
The memory bus provides for memory expansion up to
32,768 words of memory.
Logic modules are mounted in three wings at the rear
of the cabinet. These wings, each measuring approximately 22 in. by 30 in., swing out as a single door
for module access. The wings also include self-contained cooling fans and marginal check switches. The
top wing holds the 4096-word core memory system;
the middle wing, the central processor; and the bottom
wing, the I/o control secti on. Each wing has its
own switched power-distribution system at the margina I check switches on the fan housings.
A DEC Type 712 Power Supply provides the DC voltages required for the PDP-9/L system and the optional
paper tape reader/punch. Voltages of+l0V and -15V
are supplied to the basic PDP-9/L system, -30V to
core memory, and +10V and -15V to the tape reader/
punch. A variable 0 to 20Voutput is available to
check the operdtion of the system under marginal power
supply limits. By substituting this output for the normal + 10V and -15V outpufs, an existing fault or potential system failure can be isolated.
Several commonly purchased options are prewired into
the wings. The central processor wing is prewired for
the extended arithmetic element option. The I/o
control wing is prewired for the DEC Type 34HL Osci "oscope Display Control, the automatic priority
1.3 REFERENCE DOCUMENTS AND PROGRAMS
Tables 1-1 and 1-2 list the standard maintenance documents and program tapes supplied with the basic PDP-
1-1
9/L. Others may be furnished as appropriate to customer requirements.
are numbered 01 through 40 from top to bottom.
Modules are mounted horizontally in the slots.
1.4 REFERENCE CONVENTIONS
Dual-width modules carry dual location designations;
e.g., G219-AB 16AF, where AF designates pin F in
the A slot of dual slot location AB.
a. Numerical Notation - Unless otherwise indicated,
a II number representati ons are in octa I notati on.
b. Circuit References - All references to logic signals include the module type designation, module
location code, and output pin designation; e.g.,
Pulse Amplifier B602-E26D means that module B602
is located in rack E, slot 26, and the output signal
is taken from pin D. All racks are designated alphabetically from left to right as viewed from the
module mounting side. All module mounting slots
c. Signal Mnemonics - Uncommon mnemonics are
explained parenthetically the first time that they are
menti oned in the discussi on; e.g., KDN (key deposit
next). A glossary of all signal mnemonics and their
logic drawing origins is provided in Volume II.
d. Illustrations - References to in-text illustrations
include the chapter prefix number - Figure 3-10 is
the tenth ill ustrati on in Chapter 3.
FRONT
REAR
MEMORY
II
FANS,FUSES
AND MARGI NAL
CHECK SWITCHES
/
\
MARGINAL
CHECK
PANEL
CENTRAL
PROCESSOR
OPERATOR'S
CONSOLE
71 7/16"
1\
POWE R SUPP LY
I/O
LOGIC
1-oIr-~--- 32 11 / 16,.----~.1
9L-0073
Figure 1-2
Basic PDP-9/L Layout, Front and Rear
1-2
TE"xTENoED -
r-MEMORYrAUTO-MAncl
I, EXTENSION IARITHMETIC ~ PRIORITY :
CONTROL * ' ELEMENT * I INTER RUPT*
4,096-WORD
MEMORY
,
ASR-33
TELEPRINTER
PAPER TAPE,AND
PAPER PUNCH
I/O
CONTROL
LOGIC
CENtRAL
PROCESSOR
MIOMORY BUS
---*'
I
I
r-- - I
300-CPS
I
PAPER TAPE I
READER
IL _ _
_ _ _ _ ....JI
OPERATOR'S CONSOLE
REAL TIME
...._________
L_~':.O_C~_d
I
: UP TO EIGHT
4,096-WORD
I
I
!MEMORY~BANKS
I
I
r-------;1
50-CPS
I
PAPER TAPE I
IL _ _PUNCH
_ _ _ _ - lI
I
I
I
r---L ---,
, 4,096-WORD I
r-------..,
, _______
MEMORY *JI
L
I
DECTAPE
*1
I
~ __- ' I IL _ _ _ _ _ _ _ .JI
r-------lEl
IBM
I
COMPATIBLE I
,-----,/IMAGNETIC
TAPEI
L _______
...J
'------'\ I
r-------_;I
'-----'\ I
KSR-33
I
TELEP.RINTER I
.-----,/1'- _ _ _ _ _ _ _ .JI
, - - - - ---*1
'----....J\ lAID CONVERTER I
. - - - - - . / 'I
AND
I
MULTIPLEXER
_
_ _ _ _ _ --1I
r---- - ---
*'
I OTHER OPTIONS I
OR CUSTOMER I
' - - - - - , 1 LIDESIGNED
OPTIONS:J
________
L.-_-,\
NO,.E:
OUTLINED BLOCKS REPRESENT BASIC COMPUTER.
*OPTIONAL ACCESSORIES.
9L-0072
Figure 1-3
PDP-9/L System Configuration and
Optional Accessories Block Diagram
Table 1-1
Reference Documents
Document
Number
)
Title
Publisher
C-105
Logi c Handbook
DEC
DEC-9L-GRVA-D
PDP-9/L User Handbook
DEC
Bulletin 310B
ASR33 Technical Manual
Teletype Corp.
Bulletin 1184B
KSR33 Teletype, 33 Page Printer Set, Parts
Teletype Corp.
1-3
e. Drawings - Logic drawings are identified in the
text by a literal prefix code and a single numeric;
e-.g., drawing KC20(2), where KC denotes a central
processor drawing and the parenthetic portion denotes sheet 2 of a· multiple-sheet drawing. Other
literals are: MC, core memory drawings, and KD,
I/o control drawings. Complete drawing codes appear on the drawi ngs themsel ves.
h. Computer Fetch Cycle - The 1.5 fJs period during
which a core memort;J cycle extracts and restores an
instruction word. Instruction words are addressed
sequentia Ily by an incrementing program counter
(PC) in the central processor, unless otherwise stipulated by program developments.
i. Computer Defer Cycle - The 1.5 fJs period during
which a core memory cycle extracts and restores an
effective address word. A defer cycle follows a
fetch cycle whenever the fetched instruction word
contains an indirect address. If the indirect address
refers to auto-index locations 10-17 in core memory,
the effective address is incremented by 1 during
defer; the operand is taken from the location designated by the incremented effective address during
the computer execute cycle.
1.5 TERMINOLOGY
Terms used frequently throughout the text are defined
below. Others are defined within the discussions
themse Ives .
a. Core Memory - The major storage device containing the computer program and the results of program execution. Sometimes referred to as the main
memory, as opposed to control memory.
j. Computer Execute Cycle - The 1.5 fJS period during which a core memory cycle extracts and restores
an operand addressed by a memory reference instruction word or by an effective address word. The operand is manipulated in the computer in accordance
with the op code of the instruction word. The restored word may be the original operand, or may be
an operand modified by the manipulation process.
In the latter case, the original operand is lost.
b. Core Memory Cycle - The 1.5 fJs read/restore or
read/modify/write cycle during which a word is extracted, then restored or modified, and written into
core memory. The word may be an instruction word,
an effective address word, or a data word (operand).
c. Memory Reference Instruction - An instruction
word containing a direct address or an indirect address of an operand in core memory ,as opposed to
augmented instruction.
k. Computer lAO Cycle - The 1.5 fJs execute period
for certain instructions which ignore and replace
completely the operands that they address, as opposed
to the modifying operations of the norma I computer
execute cycle.
d. Direct Address - The effective address in a memory reference instruction word of a location in core
memory which contains an operand.
I. Op Code - Operation code. A portion of a memory reference instruction word or an augmented instruction word that defines the operation to be executed.
e. Effective Address - The actual address of an operand in core memory. The effective address may be
a direct address in a memory reference instruction
word, or an address in core memory which is addressed by an indirect address in a memory reference instruction word.
m. Control Memory - The magnetic storage device
in the central processor which issues timed, sequential gating levels to process or execute the instruction. The levels are strobed out of the read-only
contro I memory in the form of 36-b it process words,
each bit representing a gate-on or gate-off condition.
Process word storage locations are addressed on the
basis of the decoded instruction word op codes and
previous processing results.
f. Ind irect Address - The address ina memory reference instruction word of a location in core memory which contains an effective address.
g. Augmented Instruction - An instruction word
(OPR,IOT) that does not contain an address of an
operand in core memory. The portion of the instruction usually reserved for an address contains microcoded computer commands. These commands are
executed during either normal (OPR) or extended
(lOT) computer fetch cycles, as opposed to memory
reference instruction.
n. Program Break - A data channel transfer request
that "break" program control at completion of the
current instruction and suspends execution of the
program in progress until the current word transfer
is completed.
1-4
Table 1-2
Maintenance Program Documents
Name
Number
Instruct ion Test Part 1
9L-DOA1-PH
Instruction Test Part 1A
9L-DOA2-PH
Instruction Test Part 2
9L-D02A-PH
ISZ Test
9L-DOBA-PH,
Memory Address Test
9L-DOCA-PH
JMP Self Test
9L-DODA-PH
JMP-Y Interrupt Test
9L-DOEA-PH
JMS-Y Interrupt Test
9L-DOFA-PH
Basic Memory Checkerboard (Low)
9L-DIB1-PH
Basic Memory Checkerboard (High)
9L..;DIB2-PH
Extended Memory Checkerboard
9L-DIBB-PH
9L ASR 33/35 Teletype Test Part 1
09-D2AB-PB
9L ASR 33/35 Teletype Test Part 2
09-D2BB-PB
o. Program Interrupt - An interruption in the program
which is caused by a device service flag. Interrupt
is granted at the completion of current instruction.
The status of the program interrupted is stored in
memory location 00000 at the grant of the interruption.
1.7 SYSTEM SPECIFICATIONS
Functional Characteristics
Word Length
18 bits
Cycle Time
1.5 tJs
1.6 ENGINEERING DRAWINGS AND CIRCUIT
SCHEMATICS
Core Memory
Operation
Read/restore or read/modify/
write cycle
A complete set of engineering drawings and module
circuit schematics is delivered with the PDP-9/L.
Volume II contains a set of engineering drawings indexed by their drawing number codes; these drawings
apply to the basic system only. Logic symbols used
on the drawings are defined in the Logic Handbook,
Document C-105.
Core Memory
Capacity
4096 words, expandable to
32,768 words
Core Memory
Access
Single direct-address in any
4096-word memory' bank;
single indirect-addressing
from one bank to another
1-5
Computation Rate
333,333 additions per second
ASR33 Teletype
10 char per second
Progra m-Contro II ed
I/O Capacity
Up to 64 devices, 4 mode
selections each device
Heat Dissipation
6830 Btu/hr
Dimensions
Cabinet Height
71-3/16 in.
Cabinet Width
32- 11/16 in.
Operating Characteristics
Cabinet Depth
30 in.
Power Requirements
Shelf Width
32-11/16 in.
Shelf Depth
22 in.
Data Channel Capacity Up to 8 devices
120V±15%, 60 cps±2%,
single-phase, 17-30A or
230V±15%, 50 cps±2%,
single-phase, 17-30A
2KW
Door Clearance
{Rear}
31 in.
Power Consumption
Power Supply Outputs
+10, -15, -30, ±20 Vdc
Cabinet Weight
750 lb.
Logic Levels
OV= logic 0, -3V= logic 1
Teletype Height
8-3/8 in.
Test Temperature
Range
55-122°F
Teletype Width
22 in.
Teletype Depth
18-1/2 in.
Relative Humidity
Range
10-95%
Teletype Weight
44 lb.
1-6
CHAPTER 2
CONTROLS AND INDICATORS
2.1 OPERATOR CONSOLE
c. Visual examination of register contents and/or
of system status.
The PDP-9/L operator console (Figure 2-1), an integral part of the main computer frame, includes a work
shelf and a control console equipped with rocker
switches, rotary switches, and indicators for operator
control and monitoring of system operation . Typical
console uses are:
a. Manual entry of instruction and/or data; start/
stop/continue control of program execution.
Table 2-1 details the functional use of items on the
control console. Indicators on the panel show the
existing binary states of specific register bits and
control flip-flops by being lighted for binary 1s and
being extinguished for binary Os. The operator console can be electrically locked by a control on the
marginal check panel to prevent undesired alteration
of the program in progress. With exception of data
switches, switch settings will not affect the system
when the console is locked.
b. Stepping through a program sequence by instruction or by machine cycle for debugging or
ma i ntenance purposes.
I
&
:t \
/1
(- - -_._- -_. - - - -- - - - - - - - - - - - - - - - - - Figure 2-1
PDP-9/L Operator Console
Table 2-1
Operator Console Controls and Indicators
Controls and Indicators
Function
ST ART and START HOLD
switches
Depressing START starts program execution at the location
specified by the ADDRESS switches. The START HOLD
switch is used for maintenance purposes.
2-1
Table 2-1 (Cont)
Operator Console Controls and Indicators
Function
Controls and Indicators
10 RESET switch
Two positions: off (center) and operate (down, springloaded return). Depressing switch clears all I/o device
flags, clears the AR, MA, AC, MQ, and the Link,
turns off the real-time clock r program interrupt facility, and API system and disables the memory protection and extended memory modes.
STOP switch
Two positions: off (center) and operate (down r springloaded return). Operate halts program execution at
completion of the current instruction.
CONT and CONT HOLD
switches
Depressing CONT resumes program execution from the
point at which it stopped. The CONT HOLD switch
facilitates use of the REPT (repeat) function for the
single instruction and single step provisions.
EXAMINE THIS and
EXAMINE NEXT switches
Depressing the EXAMINE THIS switch transfers the
contents of the memory location specified by the
ADDRESS switches from memory to the MB. After
the transfer, the contents of the ADDRESS switches
appear in the AR as the address of the memory location examined.
Depressing the EXAMINE NEXT switch increments
the contents of the AR by one and transfers the contents of the newly addressed memory location from
memory to the MB. EXAMINE NEXT facilitates
monitoring of sequential memory locations as the
ADDRESS switches need only be set to the lowest
memory location. The use of EXAMINE THIS transfers the contents of this location to the MB and enters
the lowest order address in the AR. Thereafter, use
of EXAMINE NEXT step-advances the addresses
through the sequential memory locations.
DEPOSIT THIS and DEPOSIT
NEXT switches
Depressing DEPOSIT THIS switch deposits the contents of the DATA switches in the memory location
specified by the ADDRESS switches. After the transfer, the contents of the ADDRESS switches appear in
the AR as the address of the memory location in which
the data was entered.
Depressing the DEPOSIT NEXT switch increments by
one the AR contents, and deposits the contents of
the DATA switches in the memory location specified
by the new address., DEPOSIT NEXT facilitates the
entering of data and/or instruction words in sequential memory locations as the ADDRESS switches need
only be set to the lowe~ order address.
2-2
Table 2-1 (Cont)
Operator Console Controls and Indicators
Function
Controls and Indicators
The DEPOSIT THIS function deposits the DATA
switch word in this location and transfers the
address to the AR. Thereafter, the DEPOSIT NEXT
function step-advances the addresses through the
sequential memory locations.
READ IN switch
Two positions: off (center) and operate (down,
spring-loaded return). Depress switch to initiate
read-in of paper tape punched in hardware readin format. The selected repeat speed switch should
be set to ON position on the REPT switch (each set
of three 6-bit lines read from tape forms one 18-bit
computer word). Storage of words read in begins
at the memory location specified by the ADDRESS
switches. At the completion of tape read-in, the
computer reads the Iast word from core memory and
executes it. Read-in occurs at the selected repeat
speed.
REPT (repeat) control and
system ON-OFF switch
With REPT switch and CONT HOLD up, the control
establishes one of five speeds at which single-step
or single-instruction operations repeat without
operator intervention. The repeating speeds range
from approximately 2 f..IS (ON position) to ls (position 1).
REGISTER DISPLAY control
and display control and
REGISTER DISPLAY indicators
Eleven-position switch: Each position interrogates a
specific register and displays its contents in the
REGISTER DISPLAY indicators. REGISTER DISPLAY
indicators display the contents of selected register
only when machine is stopped. Moving the selection switch while the program is running has no
effect. The functions of the positions are as
follows:
RDR
Display contents of the paper-tape reader
information buffer.
TTl
Display contents of the teleprinterkeyboard information buffer.
STA
Display status of flags for I/o devices
connected to status reading facility of
I/o system.
API
Display activity of automatic priority
interrupt system1s four device-oriented
priority levels.
2-3
Table 2-1 (Cont)
Operator Console Controls and Indicators
Controls and Indi cators
Function
DPY
Display optiona I 34Hl x-, y-buffers. The
x-buffer is displayed in the nine mostsignificant REGISTER indicators; the ybuffer is displayed in the nine leastsignificant indicators. The least significant
bit of each buffer is not displayed.
lOA
Display lS-bit address word present on address
lines of I/o bus for data channel and API
operation.
lOB
Display l8-bit data word present on data
lines of I/o bus for program controlled and
data channel data transfers.
AC
Display contents of the AC.
AR
Display contents of the AR.
PC
Display contents of the PC and status bits
as stored during this instruction.
MQ
Display contents of the MQ.
PRTC switch and indicator
The up position causes the memory protection mode to
be entered by operation of the START switch. In
either position, the mode may be enabled or disabled
by program control. While the console is locked,
the switch is electrically in the down position, regardless of its actual position. The indicator is lit
whi Ie the mode is in effect. (Memory protection
is a system option.)
EXD switch and indicator
The up position causes the extend mode of addressing
to be entered by operation of the START switch. In
either position, the mode may be enabled or disabled
by program control. While the console is locked, the
switch is electrically in the down position, regardless
of its actual position. The indicator remains lit while
the mode is in effect. (Extend mode is a system option.)
ClK switch and indicator
The up position disables the optional real-time clock
facility. The down position allows program control to
enable or disable the clock. The indicator remains
lit while the clock is enabled. While the console is
locked, the switch is electrically in the down position,
regardless of its actual position.
2-4
Table 2-1 (Cont)
Operator Console Controls and Indicators
Function
Controls and Indicators
SING STEP indicator and
switch
The indicator lights when the associated switch is up.
This enables the single-step mode which halts program execution at each machine cycle. Repetitive
depressing of the CONT HOLD switch, while the
mode is enabled, steps the program through the
sequence one cycle at a time. When the console is
locked, this switch is disabled.
SING INST indicator and
switch
The indicator lights when the associated switch is up.
This enables the single instruction mode which halts
program execution at completion of each instruction.
Repetitive depressing of the CONT HOLD switch,
while the mode is enabled, steps the program through
its sequence one instruction at a time. When the console is locked, this switch is disabled.
TTYH/TTYF switch
Determines whether Teletype operation is half or full
duplex.
REPT indicator and switch
The indicator lights when the associated switch is up.
This enables the repeat function. This function causes
operations initiated by actuation of CONT HOLD,
EXAMINE NEXT, or DEPOSIT NEXT switches to repeat
while the key remains in an operator position. The repeat speed control establ ishes the rate of repetition.
ADDRESS switches (3-17)
Establish a 15-bit core memory address to be entered
in the PC by operation of the START switch, or in the
AR by operation of the EXAMINE THIS or DEPOSIT
THIS switch. Switch is placed up for a 1 bit and down
for a 0 bit. The 15 switches to the right (3-17) set up
the address of a location within an 8192-word memory
block. The two switches to the left (0 and 0) are for
extended memory addressing of locations, in up to
three other 8192-word memory blocks of the system.
DATA switches
Establish an 18-bit data or instruction word to be
read into memory by DEPOSIT THIS or DEPOSIT NEXT
operation, or to be entered in the AC by a programmed
LAS (load DATA switches) instruction. Up position of
the switch is a binary 1; down position is a binary O.
PRGM STOP indicator
Lights when the RUN flip-flop has been cleared to
stop program execution.
INST REG
The five indicators reveal the contents of the IR,
being lit for 1 bits and extinguished for 0 bits, to
2-5
Table 2-1 (Cont)
Operator Console Controls and Indicators
Controls and Indicators
Function
show the operation code of the instruction just
executed or in progress, and indirect address
occurrence.
DCH BK
Lights to indicate that data channel activity is in
progress; i.e., data is being transferred between
core memory and a data channel I/o device via the
I/o bus.
PS ACTIVE indicators
Each indicator, relating to one of the API system's
eight priority levels, individually lights to show the
priority program interrupt request currently being
serviced. Indicators 0, 1, 2, and 3 show activity
resulting from device-initiated requests; indicators
4,5,6, and 7 show activity resulting from programinitiated requests. The priority levels for each set
decrease in rank from left to right with any device
request having higher priority than any program
request.
PI E indicator
Lights when the PI system has been enabled by program control.
API indicator
Lights when the API system has been enabled by
program control.
LINK indicator
Shows the content of the Link register.
MEMORY BUFFER indicators
Shows the contents of the MB register.
2.2 MARGINAL CHECK PANEL
2.4 TELETYPE UNIT
The marginal check panel (Figure 2-2) is concealed
behind the red hinged panel on the front of the central processor. Table 2-2 details the functions of the
panel-mounted controls and indicators.
The ASR33 Teletype Unit appears in Figure 2-3.
Table 2-3 lists the teletype controls and their functions.
2.5 OPERATING PROCEDURES
2.3 CORE MEMORY BANKS
Several methods are available for loading or unloading PDP-9/L information, as described in the PDP9/L User Handbook. The method used depends upon
the form of the information, time limitati.ons, and the
peripheral equipment connected to the computer.
The following procedures are basic to any PDP-9/L
configuration.
Two selector switches, SW3 and SW4, are located in
module slot B09 of each core memory bank. These
must be preset to the particular memory bank assignment. The down positions designate 0, while up positions designate 1. Selections are as follows: 00,
bank 0; 01, bank 1; 10, bank 2; 11, bank 3.
2-6
(II
MC
tit
MAINT
MAINTENANCE
SWITCH
(52)
NORMAL
VOL
(M2)
LOCK
MC
CONTROL
KNOB
-15MC
I
@
OFF
'*
+10MC
(T 3)
MARGINAL
HECK
ELECTOR
SWITCH (51)
~
fit
[lAPSED
TIME
METER(M1)
@
Figure 2-2
Marginal Check Panel
2.5.1 Manual Data Storage and Modification
Figure 2-3
The manual controls on the console permit storage or
modification of programs and data. These facilities
are used primarily in the manual storage of the ReadIn Mode Loader (RIM) program and other programs in
the read-in mode format.
Teletype Model ASR33 Console
in RIM format when the ADDRESS switches are set to
the RIM Loader starting address and the START key is
pressed. The RIM tape format is further described in
the PDP-9/L User Handbook and in Digital Program
Library descriptions. To store the RIM Loader manually in PDP-9/L core memory:
The stored RIM Loader program automatically reads
data into PDP-9/L memory from perforated paper tape
Table 2-2
Marginal Check Panel Controls and Indicators
Controls and Indicators
Marginal check voltmeter
(1, Figure 2-2)
Function
Indicates the selected voltage output of the marginal
check power supply. The center of the scale relates
to the reference voltage selected, either +10 or -15V
dc. Movement of the pointer to the right indicates an
increase in magnitude for the marginal check voltage.
2-7
Table 2-2 (Cont)
Marginal Check Panel Controls and Indicators
Controls and Indicators
Function
Marginal-check voltage
control (2, Figure 2-2)
Establishes the marginal check voltage level of the
selected output. Voltage is increased with clockwise
rotation.
Maintenance switch
(3, Figure 2-2)
Five positions:
LOCK - electrically locks the control console. With
the console in the locked condition, operation of any
console control cannot affect the program in progress.
Data switches can be program sensed.
NORMAL - Control console is not locked; all controls
may be used.
MAINT - With the switch in this position and the REPT
switch (control console) in the up position, the builtin maintenance test program circulates a self-incrementing count through all active CPU registers to verify
both their operation and the internal transfer paths.
The program proceeds at the rate selected by the repeat
speed control (control console). The START HOLD
switch should be selected during MAl NT •
EXAMINE - simulates the "examine" function. With the
switch in this position, the CPU responds as if the
EXAMINE THIS switch (control console) was being
actuated at the rate selected by the repeat speed control (control console). With the REPT switch in the
down (inoperative) position, each movement of the
selector switch to position EXAMINE simulates an
actuation of the EXAMINE THIS switch.
DEPOSIT - Simulates the "deposit" function. With the
switch in this position and the REPT switch (control console) in the up position (activated), the CPU responds as
if the DEPOSIT key were being actuated at the rate
selected by the repeat speed control (contrQI console).
With the REPT switch in the down (inoperative) position, each movement of the selector switch to position
DEPOSIT THIS simulates an actuation of the DEPOSIT
THIS switch.
Marginal-check selector
switch (4, Figure 2-2)
Three positions:
OFF - marginal check disabled.
+10 MC - selects the +10V output of the marginal
check power supply.
2-8
L
Table 2-2 (Cont)
Marginal Check Panel Controls and Indicators
Function
Controls and Indicators
Marginal-check selector
switch (4, Figure 2-2) (Cont)
Elapsed time meter
(5, Figure 2-2)
-15 MC - selects the -15V output of the marginal
check power supply.
Indicates, to the nearest tenth of an hour, the
cumulative number of hours in which the system has
been in the "power on" state. Meter counts from
00000.0 to 99999.9.
Table 2-3
Teletype Controls And Indicators
Control or Indi cator
Function
REL. pushbutton
Disengages the tape in the punch to allow tape
removal or tape loading.
B. SP. pushbutton
Backspaces the tape in the punch by one space,
allowing manual correction or rubout of the
character just punched.
OFF and ON pushbuttons
Control use of the tape punch with operation of
the teletype keyboard/printer.
START/STOP/FREE switch
Controls use of the tape reader with operation of
the Teletype. In the lower FREE position, the
reader is disengaged and can be loaded or unloaded. In the center STOP position, the reader
mechanism is engaged but de-energized. In the
upper START position, the reader is engaged and
operated under program control.
Keyboard
Provides a means of printing on paper in use as a
typewriter and punching tape when the operator
presses the punch ON pushbutton. The keyboard
also supplies input data to the computer when the
LINE/OFF/LOCAL switch is in the LINE position.
LINE/OFF/LOCAL switch
Controls application of primary power in the
Teletype and controls data connection to the processor. In the LINE position, the Teletype is
energized and connected as an I/O device of the
computer. In the OFF position, the Teletype is
de-energized. In the LOCAL position, the Teletype is energized for off-line operation, and signal
connections to the processor are broken. Only line
use of the Teletype requires that the computer be
energized through the POWER switch if primary
power for the Teletype is supplied from a source
other than the outlet at the back of the computer.
2-9
a. Turn the maintenance panel switch to NORMAL
and the console POWER switch ON.
the left of"the sprocket wheel to be sensed. Set
Teletype reader to start position.
b. Set the console ADDRESS switches to correspond
with the address of the first word to be stored. (In
the case of the RIM Loader program, this is 07762
for 4K, 17762 for 8K.)
c. Set the ADDRESS switches to the starting address to be used for the program as it is stored in
core memory.
d. Press the READ I N key. The tape wi II be read
automatically.
c. Set the DATA switches to correspond with the
binary equivalent of the first word. (In the case
of the RIM Loader program, this is 0.)
e. Channel 8 on binary format tapes is always
punched; channel 7 is punched only in the last
line of the last word to stop tape motion and to
conclude the read-in operation. The program just
read can be made self-starting by making this last
word a JMP instruction to the starting address of the
program. When the JMP instruction is read, it is
interpreted as the current instruction to be executed
and thus starts the program. If the tape is not selfstarting, the last instruction is a HLT. To initiate
the program, set the starting address into the ADDRESS switches and press the START key.
d. Depress the DEPOSIT THIS switch to deposit the
word in memory.
e. Display the contents of the AR in the REGISTER
indicator by turning the REGISTER DISPLAY selector
to the AR position. The contents of the MB are
automatically displayed in the MEMORY BUFFER
indicator. Observe that the MB contains the data
word just deposited, and that the AR contains the
address of the core memory cell in which the word
was deposited.
f. Store all additional data words by pressing the
DEPOSIT NEXT switch after each successive data
word has been set into the DATA switches. The
contents of the AR wi II increment by 1 duri ng each
DEPOSIT NEXT operation, thus setting up the address of the core memory cell to be used for the
next operation.
2.5.3 Storing Data Under Program Control
Information can be automatically stored or modified
in the computer by executing programs previously
stored in memory. For example, having the RIM
Loader stored in core memory a lIows the loading of
RIM format tapes, as follows.
g. To recheck the loaded program, set the ADDRESS switches to the starting address and press
the EXAMI NE switch. After the first core memory
cell has been checked at the MEMORY BUFFER
indicator, the remaining cells may be examined
in sequence by repeatedly pressing the EXAMINE
NEXT switch without regard to the ADDRESS
switch settings. By repeating steps b through d
using the address of the cell in question, it is
possible to alter the contents of any cell .
a. Turn the maintenance panel switch to NORMAL
and the console POWER switch ON.
b. Insert the tape in the tape reader.
c. Using the ADDRESS switches, set the starting
address of the RIM Loader program.
d. Press and re Iease the conso Ie START key. The
tape is read and stored automati ca lIy .
2.5.2 Storing Binary Data Using READ IN Key
2.5.4 Assembling Programs
Hardware Read-in (HRI) tapes (including the RIM
Loader tape) can be loaded directly into core memory
without the need of a presto red program, by using the
following procedure.
Programs prepared in binary format and written in
symbolic language can be assembled into binary I
machine-language program tapes as described in
appropriate Digital Program Library documents, as
follows:
a. Turn the maintenance panel switch to NORMAL
and the console POWER switch ON.
a. Turn the maintenance panel switch to NORMAL
and the console POWER switch ON.
b. Load the tape in the Teletype reader. Proper
positioning of the tape enables three channels to
2-10
g. When assembly is complete, the assembler wi II
stop with all 1s in the AC.
b. Store the RIM Loader program, either manually
or by use of the READ IN key, as previously described.
2.5.5 Teletype Code
c. Load the assembler program into core memory
by means of the assembler tape. (The assembler
tape is in RIM format.) When the tape has been
read, the AC should contain all Os. If it does not,
a checksum error has been detected, showing improper storage of the program. When this occurs,
the tape must be rerun until the AC finally contains aliOs at the conclusion of the loading process.
Repeated errors indicate defects in either the assembler tape or the PDP-9/L system.
d. Insert the symbol i c language tape to be converted into machine-language, binary-format, into
the tape reader.
e. Put the starting address of the assembly program
into the ADDRESS switches on the console. (Set
DATA switch 10 up to indicate ASCII, or down to
indicate FIODEC code.)
f. Press and release the CONTINUE key.
2-11
The 8-bit code used by the ASR33 Teletype is the
American Standard Code for Information Interchange
(ASCII), modified.
2.5.6 Maintenance Programs
Diagnostic programs are designed to test specific
functions within the computer system. These routines
are available as perforated paper tapes in hardware
read-in mode (HRI) format. Each diagnostic routine
is accompanied by a description of the program, procedures for using the program, and information on
analyzing the results to locate specific failures.
Applications of these routines are indicated in Chapter 10, as they apply to preventive or corrective
maintenance of the PDP-9/L system. To exercise
these routines the user should be familiar with the
machine programming described in the PDP-9/L User
Handbook.
CHAPTER 3
SYSTEM DESCRIPTION
3.1 COMPUTER ORGANIZATION
Fig(;te 3-1 illustrates the organization of the PDP-9/L
General Purpose Computer.
The PDP-9/L Programmed Data Processor System is a
general purpose computer, incorporating FLIP CHIP
hybrid circuits. The computer is a single address,
fixed word length (18 bits), parallel binary computer.
Minimum system configuration is 4096 words of memory, paper-tape input and output, and keyboard· input
and pri nter output.
3.2 CENTRAL PROCESSOR
3.2.1 Control Memory (CM)
The CM issues all sequences of internal processes required to fetch and execute a program1s instructions,
to effect operation of I/O channels, and to respond
to operator commands from the console. It is a readonly, prewired magnetic core storage unit. The CM
supplies new address information to the CP (Central
Processor) based on the instruction to be executed and
on the conditions sensed by the previous process levels.
Major functions of the PDP-9/L System are the central
processor, core memory, main memory, and input/output faci I ities. The system has a bus transfer network
and jam-transfers data between registers at dc levels
to minimize timing problems.
r------l
I
I
I
I
COR E MEMORY
I
I
I
Il ____ _
I
I
I
I
I
I
I
1-------,
CENTRAL
PROCESSOR
IIO
,-----~
TELEPRINTER
PUN
(OPTION)
10 BUS ON
10 BUS
DCH
10 ADDR
BUS
KBD
I
RDR
(OPTION)
B BUS
A BUS
ADDRESS
SWITCHES
DATA
SWITCHES
L
SUB COMMAND
SEQUENCES
_____ ..J
FROM MB
10 BUS (B)
'LIO
Figure 3-1
PDP-9/L Functional Diagram
3-1
9L-0048
3.2.2 Adder (ADR)
3.2.6 Optional Multiplier-Quotient Register (MQ)
The 18-bit ADR functions as a nonstoring adder for
arithmetic operations and as a common bus transfer for
all inter-register transfers and shift operations. A
19th-bit adder link (ADRL) transfers the content of the
arithmeti c register Iink (LAR) to the accumulator register link (Link) and vice-versa when those registers
are used for arithmeti c operations. The ADR operates
at a 5 Mc rate for a transfer time for 200 ns and a
carry time of less than 5 ns per stage.
The 18-bit MQ register is part of the optional extended arithmetic element (EAE). TheMQ holds the multiplier during multiply operations and receives the
.Iow-order 18-bits of the resulting product. During
divide operations, it hold~ the low-order 18-bits of
the dividend, and at the completion of the divide
operation, it contains the quotient. It can also be
used as an extension of the AC for 36-bit shift operations.
3.2.3 Accumulator (AC)
3.2.7 Program Counter (PC)
The 18-bit AC retains the result of arithmetic/logical
operations. The AC can be cleared, complemented,
rotated right, or rotated left. The contents of the
memory buffer (MB) register can be added to the contents of the AC. The contents can also be combined,
in the ADR, by logical AND or Exclusive-OR instructions and the result left in the AC. An Inclusive-OR
can be formed in the ADR between the AC and the
DATA switches on the console, and the result left in
the AC. For program-controlled input data transfers,
information is transferred from an external device to
the AC via the I/O bus.
The PC determines the program sequence in which instructions are executed. This 13-bit register contains
the address of the core memory cell from which the
next instruction is to be taken. Addition of the extended memory options adds two extended program
counter (EPC) bits to the system addressing scheme.
3.2.8 Instruction Register
0R)
The IR accepts the five most-significant bits of each
i nstructi on fetched from core memory. Of these, the
four most-significant bits constitute the instruction
operation code (op code). For a memory reference
instruction, the fifth bit indicates whether the instruction contains a direct (effective) address of an
instruction or an indirect address of a location in core
memory which contains the effective address. These
bits are decoded during the fetch cycle to determine
the CM sequence necessary to execute the instruction.
3.2.4 AC Link (Link)
This l-bit register is used to extend the arithmeti c
capability of the AC. In l's complement arithmetic,
it is an overflow indicator; in 2's complement arithmetic, it extends the AC to 19 bits and functions as a
carry register •. The program checks overflow into the
Link to greatly simplify and speed up single and multiple precision arithmetic routines. The Link can be
deared and complemented and its state sensed independent of the AC. It is included in the AC in rotate
operati ons .
3.2.9 Memory Buffer Register (MB)
All information transferred into or out of core memory
passes through the MB. During a fetch cycle, instructions are read from a memory location into the MB and
are rewritten into the location as the instruction is
retained in the MB for decoding and later execution.
During an execute cycle, the operand addressed by
the instruction is fetched from a memory location and
is placed in the MB •. The operand is then rewritten
into the memory location, in accordance with the
operation called for by the instruction. The MB also
serves as a buffer for both information transfers between core memory and an external device, and address transfers between the PC and the MA.
3.2.5 Arithmetic Register (AR)
The AR functions with the AC to perform arithmetic
and logical operations. It accepts and stores the contents of the AC for manipulation through the ADR; the
results are then deposited in the AC. The AR is not
accessible to the programmer. For program-controlled
output data transfers, information is transferred from
the AR to an external device via the I/O bus.
3-2
3.3 CORE MEMORY SYSTEM
3.3.1 Direct Addressing
The PDP-9/L core memory used a 3D design concept
for speed, compactness, and reliability; it operates
with a complete cycle time of 1.5 JJS. Each 4096word core memory package contains a core stack,
sense amplifiers, drivers, and a 13-bit memory address
(MA) register. The MA addresses the memory location
to be used for data retrieval or storage. System core
memory can be expanded from the basi c 4096 words up
to 32,768 words in 4,096-word increments. Such expansion requires the implementation of the memory
extension option to extend the PDP-9/L addressing
capability.
Directly addressed memory reference instructions (bit
04 = 0, Figure 3-2) take the 12-bit address (06 to 17)
specified in their instruction words as the effective
address of the memory register which contains the required operand. The 12-b't address allows direct addressing of up to 4096 locations in a currently addressed memory bank. Locations in memory banks other
than that currently addressed must be accessed by indirect addressing.
Indirectly addressed memory reference instructions
(bit 04 = 1, Figure 3-2) take the 12-bit address (06
to 17) specified in their instruction words, not as the
effective address of the memory register containing the
operand, but as the address of the memory register
which contains the effective address. For example,
the instruction LAC 100 directs the computer to load
the contents of memory register 100 into the AC. But
the instruction LAC * 100 (see footnote 1) directs the
computer to load the contents of the memory register
addressed by the contents of memory register 100 into
the AC. Indirect addressing adds one computer cycle
(defer) to the instruction execution time, during which
the effective address of the operand is fetched.
Table 3-1
-Reserved Core Memory Locati ons
Address
Purpose
00000
Stores the contents of the PC, Link,
opti ona I EPC, extend mode opti on
status, and memory protecti on option status during a program interrupt.
00001
Stores the first instruction to be
executed following a program interrupt, normally a JMP.
00002-00006
Currently unused
00007
Stores optional real-time clock-time
00010-00017
Autoindex registers
00020
Stores the contents of the PC, Li nk,
opti ona I EPC, extend mode opti on
status, and memory protecti on option status upon execution of a CAL
instruction.
00021
First instruction to be executed
following a CAL instruction.
3.3.2 Indirect Addressing
3.3.3 Autoindexing
When anyone of core memory locations 00010 through
00017 is indirectly addressed, the contents of that location are automatically incremented by 1, and the
result is taken as the effective address of the instruction. Incrementing is accomplished with no additional instruction execution time. Such autoindexing
operations are effective only when the locations are
indirectly addressed. When directly addressed, the
locations contain operands just as any other memory
locations.
3.3.4 Extend Mode Addressi ng
00022-00027
Currently unused
Installation of additional memory banks requires the
memory extension control option for addressing a
memory location outside the currently addressed memory bank.
00030-00037
Four pairs of word counter/current
address registers for use with data
channels 0, 1,2, and 3.
3.4 I/O CONTROL
00040-00077
The I/O control section includes logic for programcontrolled transfers between the central processor and
Store entry i nstructi ons for each of
32 optional automatic priority interrupt channels.
lIndirect addressing in'earlier softwore programs was
represented with an I symbol. The symbol * represents indirect addressing in current programs.
3-3
CLEAR
AC
PRIOR
TO EVENT
TIME 1
OPERATION
CODE 70
DEVICE
SELECTION
r~------~A~----~\
r~----------~A~----------~\
GENERATE
AN lOP 2
PULSE
AT EVENT
TIME 2
I 0 I I 2 I 3 I 41 5 16 I 7 I 8 I 9 110 1'1 1'21'31'41'51'61'71
"------y----J
UNUSED
"------y----J
'--y-J
'--y-J
SUB-DEVICE
SELECTION
GENERATE
AN lOP 4
PULSE
AT EVENT
TIME 3
GENERATE
AN lOP 1
PULSE
AT EVENT
TIME 1
9L-0049
a. Word Format
Mnemonic
Code
Cycles
Ca" subroutine
CAL
00
2
Deposit AC
DAC
04
2
Jump to subrouti ne
JMS
10
2
Deposit zero in memory
DZM
14
2
Load AC
LAC
20
2
Exclusive OR
XOR
24
2
Add, l's complement
ADD
30
2
Add, 2's complement
TAD
34
2
Execute
XCT
40
1+
Increment and skip if zero
ISZ
44
2
AND
AND
50
2
Skip if AC different from
memory
SAD
54
2
Unconditional jump
JMP
60
1
Operation
Add 1 cycle time for indirect addressing or auto indexing
b. Instruction Description
Figure 3-2
Memory Reference Instructions
3-4
as many as 64 devices. Program-controlled transfers
make use of program interrupt, I/O skip, and I/O
status checking faci I iti es. The I/O control section
also allows operation of up to 8 devices connected
to 8 dota channels (DCH), and up to 28 devices in
32 optional API channels multiplexed at 8 priority
levels.
instruction. Descriptions of the memory reference instructions are given in Appendix A.
All of the above operate off the bidirectional I/O
bus, which serially links the central processor to the
peripheral devices, Devices with high transfer rates,
such as DECtape and magneti c tape normally use DCH
access to core memory to allow operation at maximum
transfer rates. Slower asynchronous devices such as
I ine printers, teletype keyboards and punched card
equipment may operate at maximum speeds through
the use of the API option under program control.
3.5.2.1 Operate - OPR instructions (op code 74) are
used to sense and/or alter the contents of the AC and
Link. Typical functions (Figure 3-3) are: conditional
or unconditional skips; complementing, setting, clearing, or rotating the contents of the AC and Link •. A
HLT instruction is included. OPR instructions are
fetched and executed in one computer cycle, the actions being specified by the microprogramming of bits
04 to 17 in the instruction word. Each of the 14 bits
can effect a unique response; hence, they are "microinstructions" to the computer. The important feature
of the OPR class is its microprogramming capability
where two or three microinstructions can be combined
in one instruction word, and therefore be executed
sequentially during one computer cycle.
3.5.2 Augmented Instructi ons
Some timed-transfer devices can operate independently of the central processor after they have been set in
operation, These devi ces are normally connected to
th e DC H to transfer a block of data words at a time,
Once the program has suppl ied information about the
location and size of the data block, the DCH takes
over the responsibility of effecting the actual transfer.
Separate parallel buffers are provided in the device
controls interfaced to the I/O bus.
3.5.2.2 Input/Output Transfer - lOT instructions
(op code 70) initiate transmission of signals via the
I/O bus to control peripheral equipment, sense their
status, and effect information transfers between them
and the central processor, Each instruction contains
an 8-bit device selection code, bits 06 through 13,
and a command code, bits 14 through 17 (Figure 3-4).
Bits 06 through 11 of the device selection code perform the primary device selection among up to 64 devices while bits 12 and 13 select an operational mode
or subdevice. Selection logic in a peripheral's interface responds only to its preassigned code. The command code, bits 14 through 17, is capable of being
microprogrammed to clear the AC and to is~ue up to
three sequential command pulses to the peripheral
equipment via the I/O bus.
3.5 INSTRUCTION WORD FORMATS
The PDP-9/L has two general instruction groups: memory reference (single-address) instructions, and augmented (no-address) instructions. The latter group has
three subclasses: operate (OPR) instructions, input/
output transfer OOT) instructions, and optional extended arithmetic element (EAE) instructions.
3.5.1 Memory Reference Instructions
Memory reference instructions (Figure 3-2) consist of
and op code, an indirect address bit, and an address.
The op code, bits 00-03, specifies one of 13 memory
reference instructions, The indirect address bit, 04,
indicates whether the 12-bit address (06 to 17) is a
direct address (bit 04 = 0), or an indirect address (bit
04 = 1). If di rect addressing is i ndi cated, the addressed memory location contains the required operand. If
indirect addressing is indicated, the addressed memory
location contains the address of the required operand.
In either case, the address of the memory location containing the operand is the "effective address" for the
3-5
Execution of an lOT instruction requires an instruction
.fetch cycle and three execute cycles of 1.51ls duration each, designated event times 1, 2, and 3, Only
the fetch cycle contains a core memory read/write
cycle. Thereafter, core memory is idle until completion of the lOT execute cycles. Bit 17 generates an
IOP1 pulse during event time 1 while bits 16 and 15
generate IOP2 and IOP4 pulses during event times 2
and 3, respectively. lOT skip instructions are microprogrammed to produce an 10Pl pulse for testing a
Bit 7 = 0
ClA
Cll
Additional
Rotate
0= OR of
1 = AND of
SNl
SZl
5
6
7
8
9
SZA SMA
SNA SPZ
10
11
HlT
12
RARIRAl
OAS
RTR IRTl
Bit 7 = 1
15
13 I 14
Event
Time
OPR }
NOP
7
4
0
0
0
0
CMA
7
4
0
0
0
1
3
CMl
7
4
0
0
0
2
3
OAS
7
4
0
0
0
4
3
RAl
7
4
0
0
1
0
3
RAR
7
4
0
0
2
0
3
XX
HlT}
7
4
0
0
4
0
SMA
7
4
0
1
0
0
SZA
7
4
0
2
0
0
SNl}
SMl
7
4
0
4
0
0
SKP
7
4
1
0
0
0
SPA
7
4
1
1
0
0
SNA
7
4
1
2
0
0
SZl}
SPl
7
4
1
4
0
0
RTL
7
4
2
0
1
0
2,3
RTR
7
4
2
0
2
0
2,3
Cll
7
4
4
0
0
0
2
7
4
4
0
0
2
2,3
J
(Cll-CMl)
STL
CCl
(Cll-RAl)
RCl
7
4
4
0
1
0
2,3
(Cll-RAR)
RCR
7
4
4
0
2
0
2,3
ClA
7
5
0
0
0
0
2
(CLA-CMA)
ClC
7
5
0
0
0
1
2,3
(ClA-OAS)
lAS
lAT
7
5
0
0
0
4
2,3
(ClA-RAl)
GlK
7
5
0
0
1
0
2,3
J
Figure 3-3
Operation Instruction Word Format
3-6
CMl
CMA
16
17
device status flag. IOP2 pulses are normally used to
effect programmed transfers of information from a devi ce to the centra I processor. Because the AC serves
as the data register for input transfers, the "clear AC"
microinstruction (bit 14) is usually microprogrammed
with the IOP2 microinstruction; this combination clears
USED
WITH
SI92
WORD
MEMORY
OPERATION
CODE=OOS-60S
J.
0
the AC prior to the start of event time 1, then strobes
in the new information with IOP2 during event time
2. The lOP pulses trigger lOP flip-flops which remain set for the event time duration. The 10 P4 is .
usually used to transfer data from the computer to the
device.
,..--"---.
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
ADDRESS
INDIRECT
ADDRESS FLAG
(*-INDIRECT)
9L-007S
FiglJre 3-4 lOT Instruction Word Format
3-7
CHAPTER 4
CONTROL MEMORY SYSTEM
4.1 ORGANIZATION
The control memory (CM) system in the central
processor is a read-only I Iinear-select magnetic core
system which issues 36-bit "process words" to a control register (CR) composed of core-sensing flip-flops.
A 6-bit control memory address (CMA) included in
each process word addresses the next process word location in control memory. The remaining 30 bits comprise the data-path gating levels which implement the
fetching and execution of instructions and also specify the timing of control memory readout. The CMA
may be modified by conditions sensed during the processes, or by gating levels issued by the previous
process word. The CM issues up to four such process
words per computer cycle in a sequence which is
largely determined by the previous processing results.
A continue bit in the previous process word determines
if another process word shaH follow; an SM (start memory) bit determines if a main core memory cycle shall
follow, concurrent with another process word.
Figure 4-1 is a functional block diagram of the control memory system. The system consists of CM timing
logic (drawing KC16), two G210 Address Selectors
(drawing KC17), Control Memory core array (drawing
KC18) and 36 core-sensing control register flip-flops
(drawing KC19).
The importance of maintaining synchronism of the
control memory processes, and the main core memory
cycles may readi Iy be appreciated. Both the main
memory cycle and the control memory timing are
started by ClK POS pulses every 1.5 !-IS and a start
memory (SM) level from the CM sense flip-flop that is
always set during the last CM process word of a comp-
PROCESS
BITS (30)
ADDRESS BITS (6)
CONTROL REGISTER
CM STROBE
CONTROL MEMORY
MEM STROBE
CM CLK
SM(ll
CMPOO-07
CM
TIMING
KEY INIT POS
CMGOO-07
ADDRESS SELECTORS
10 RESTART
CM CURRENT PULSE
ADDRESS GATING
CMAOO-05
IROO-04
KIOA3-A5
9L-0050
Figure 4-1
Control Memory System, Block Diagram
4-1
Drawings KC3 through KC6 are the flow diagrams for
the processes. Numbers within the process word blocks
indicate the CM addresses from which the words are
taken. Note that some bits of the process word can be
operated on by hardware external to the control memory system as a result of conditional events.
puter cyc Ie (fetch, defer, execute, lAO). The last
CM process word in an execute cyc Ie, lAO execute,
and end of DCH break, always contains the SM level
and address 21 in the CM sense flip-flops. The next
computer cycle is a fetch cycle and the next CM process word will be extracted from address 21. The CM
reads out the process word from address 21, which
contains gating levels to load the PC with the address
of the next sequential instruction ,and also contains
continue, a level which retriggers the CM timing
chain. The address contained in process word 21 will
have been sent to the G210 Address Selectors, and
will always be address 12. The CM will now extract
the process word at address 12.
4.2 TIMING AND CONTROL
CM timing logic is shown on drawing KC16. Any of
the following five conditions can start the timing
chain to produce CM CURRENT and CM STROBE.
a. KEY INIT POS
The process word in CMA12 does not contain a CONT
(1) bit, so another CM extraction does not follow immediately. In this instance, the CM timing must wait
for the main core memory IS MEM STROBE for triggering.
b.IORESTART
c. CM CLK A SM (1) A AM SYNC BUS(O)
d. CM STROBE DACONT (1)
The address selectors contqin positive and negative
transistor switches operation in complementary pairs
to send drive current through 1 of 64 lines in the control memory array. Each line is threaded through all
36 cores in series; the side of the core the wire passes
through determines the state a core will assume when
the Iine is driven. Core windings on one side induce
positive voltages in their respective sense lines, setting the sense flip-flops in the control register. Core
windings on the other side Induce negative voltages,
resetti ng the fl ip-flops. The sense fl i p-flops set and
reset on the CM STROBE from the CM timing chain.
e. MEM STROBE A lAO (0)
The following is a general description of the functions
that these conditions control. Detailed descriptions
and timing diagrams are found in the referenced sections.
KEY INIT POS occurs during manual entry of address
and/or data words from 'the console switches or after
depressing 10 RESET on console. This pulse starts the
chain to extract a series of manual entry process words
from locations 00 through 07 using the KIOA3 through
5 levels for CM addressing.
The processes of the fetch cycle determine whether
the next cycle shall be a defer, lAO, or execute.
Certain instructions also demand that the next cycle
be another fetch. Whatever the case I the address in
the third process word commands the extraction of the
appropriate cycle entry word.
CM CLK A SM (1) starts the timing chain to extract
the entry word of any computer cycle concurrently
with a core memory cycle.
CM STROBE A CONT (1) starts the chain to extracnhe
second word I and MEM STROBE A lAO (0) extracts the
third, in any computer cycle. For execute cycles,
CM STROBE A CONT (1) is allowed to extract a fourth.
The determining factor for the number of words extracted is the status of the CONT flip-flop in the current process word.
As shown in Figure 4-1, the address in the control
register may be preempted by manual operations from
the console, where the levels KIOA3-AS perform the
CM addressing function. Drawing KCI8(1) is the
Control Memory Program Chart in which one process
word (LOC column) address the next (JMP column) in
the main flow of execution, with conditional branching from the main flow as a result of sampling certain
events. The BITS column lists those bits that are 1s in
each word and the JMP column lists the location in
control memory of the next sequential word. The
SYNC column contains the bits that control the initiation of the next process (CONT) or cycle (SM).
For lOT instructions, 10 RESTART extracts a process
word after an extended 4.5 fJS execute period. This
word prepares the computer for the next fetch cyc Ie.
For the manual read-in operations, 10 RESTART extracts a process word when the tape reader reads a hole
in channel 7. This word also prepares the computer
for the next fetch cycle.
4-2
EB
-15V
FB
-15V
EJ
GND
CMGl
FM
CMSLOO
016
CMSL35
EV
CM CURRENT
EU
CMAO (0)
CMAI (1)
=
ET
07
ED
B169-F21E
FV
CM CURRENT
=
FU
B169-F21D
FS
FL
-15V
B169-F22E
FE
9L-0051
Bl05-H21R
Figure 4-2
CM Line Selection, Line 21
4.3 CONTROL MEMORY G920
Control Memory G920 is a quadruple-height module
containing the linear core array. The Control Memory
Wiring Matrix, drawing KC18(2L is a practical representation of the 64 drive lines threading the cores that
induce 1s into the sense lines. In reality, all drive
lines thread all 36 cores serially in specific 1 and 0
winding patterns to produce 64 separate and distinct
36-bit words. At CM CURRENT time, the address
selectors supply drive current through one selected
line. At CM STROBE time, the core states are transferred to the sense flip-flops from the sense lines,
CMSLOO-35.
4.4 ADDRESS SELECTORS G210
Two double-height Address Selector Modules G210,
drawing KC 17, perform control memory I ine selection
by decoding the CM address and turning on line drivecurrent in response to the CM CURRENT pulse from the
CM timing logic, drawing KC16. Each module contains four positive-select and four negative-select
switches, connected together to form an 8 by 8 coordinate matrix. Input address decoding gates turn on a
pair of complementary switches to connect a ground to
one end of the selected line and a negative source to
the other. The module is similar to the G219 Address
Selector Modules in core memory.
4-3
Figure 4-2 is a simplified schematic of the drive selection circuits for line 21, containing the fetch-entry
process word. In this case, the active switch pair is
located entirely within one module, EF20. Although
selection of some lines makes use of a switch in each
module, the logic is identical.
For the fetch entry word extraction, the address in
control register bits CMA 0-5 is 21. In Figure 4-2
CMA 0 (0), CMA 1 (1), and the level from B169-F21E
are all negative. On drawing KC 17 I the output at
B169-F21 E comes from the paralleled NAND gates
controlling address bit 2. The output is negative because each of the four paralleled gates is disabled:
the IR sampling is disabled by a grounded input from
NOR gate Rl11-F24N I the DCH and API gate is
disabled by the absence of EXT (1), etc. The negative levels are applied to the input decoding gates at
transistor Q14. Likewise, the 03, 04, and 05 parallel gates are disabled and the consequent negative
levels are applied to the input decoding gates at
transistor Q5.
.
CM CURRENT enables the Q14 and Q5 gates to turn
on these transistors. The resu Iti ng current-surges
through transformers T8 and T3 turn on Q 16 and Q7.
The emitter of Q16 goes to ground and the collector
of Q7 rises to the -15V supply voltage. The Q 16
emitter output at EK is the CMP 2 connection to one
end of core drive line 21; the Q7 collector output at
FM is the CMG 1 connection to the other end. Current flows through the line from CMG 1 to CMP 2.
drive current via the address selector switches. Maximum current is limited by the inductance of the drive
lines to 200 mA, inducing positive or negative signals
of 2V (with SV flyback) in the sense lines (reference,
-2.2V bias).
4.S CURRENT SOURCES
The control memory system is powered by the +10,
-lSV computer supply. The -lSV output supplies the
4-4
CHAPTER 5
CENTRAL PROCESSOR
5.1 CENTRAL PROCESSOR lOGIC
The central processor performs the arithmetic logic,
and system control operations of the PDP-9/l System.
This chapter correlates the central processor logic
with the execution of the program instructions. Functions common to most instructions, i.e., fetch cycle,
defer cycle, autoindexing, are treated as an introduction to the individual execute descriptions.
The flow charts of drawing KC3 through KC6 and
associated timi.ng diagrams supplement the text. The
system functional diagram in Chapter 3 will also be
an aid to following the data transference described
in this chapter.
5.1.1 Fetch Cycle
The fetch cycle description is based on the fetch flow
drawing KC3 and the memory timing diagram MC7113. The computer enters the fetch cycle from the
BGN process word (10) in control memory. This is
always the last word extracted from control memory
during the current execute cycle of a running program.
The BGN word contains PCO, SM, and the "next
CM address,'l CMA21. The ground level PCO(1) is
NORed at Rll1-E22HJ to produce a negative AMB
level, drawing KC19(2). AMB is NANDed with
SM(1) of the BGN word and ClR from drawing KC10.
The NAND gate output at R111-E22N produces
1 .... MBI at pulse amplifier B602-E23D when ClK at
the end of the execute cycle occurs. The 1 .... MBI
pulse sets the MBI flip-flop. Under these conditions
PCO(1) and MBI(1) transfer the address in the PC to
the MB via the A bus, ADR, and 0 bus. At MA JAM
time the MB is transferred to the MA in core memory.
The BGN word remains in the CM sense flip-flops
unti I SM(l) and the next ClK pulse (CM ClK) generate CM STROBE to extract the fetch entry process word
at CM location 21 .
At ClK time in the BGN process, CM ClK and SM(l)
produce CM CURRENT ~ 80 ns) and CM STROBE
(:::::40 ns) in the CM timing chain, drawing KC16, to
extract the fetch entry word. This is the first of three
process words to be extracted during the 1 .5 tJS fetch
cycle period or interval between ClK pulses. ClK
and SM(1) also start the core memory cycle.
The fetch entry word 21 contains MBO, +1, PCI,
CONT, and CMA12. The address placed in the MB
by the BGN process is still there; MBO(l) gates it
onto the B bus, and the B bus contents go directly into
the ADR on drawing KC21. Process +1 (1) produces
CIl7, drawing KC14, which initiates a carry into
ADR17 on KC21(3), in effect incrementing the address
in the ADR by 1. NOSH (no shift) gates the incremented address onto the 0 bus, drawing KC20. NOSH
from KC13 is present at all times except during rotating operations. PCI(l) places the incremented address
in the PC and resets the SKIP and AUT INX flip-flops,
drawing KC14. Unless otherwise modified by the
execution of certain instructions, this is the address
(PC+1) to be entered into the MB by the next BGN
word of the impending execute cycle.
The CM STROBE that extracted the fetch entry word
also restarts the CM timing chain with CM STROBE D
on drawing KC16. This pulse triggers a 65-ns delay
in B310-EF33. When the delay recovers at B310EF33EU, its trai ling edge grounds the emitter of inverter B104-F31R. The inverter turns on because
CONT(l) of the fetch entry word is applied to the
base. The collector goes to ground, thus triggering
pulse amplifier B602-E32D. The PA output triggers
delay EF33EL. When this delay recovers, it grounds
the emitter of B104-F31F. TESTER is always negative,
turning this inverter on. The collector passes NOR
gate Rl11-F26U for CM CURRENT. The output of
B104-F31 also pulses B602-F30D for CM STROBE after
a 65-ns delay. The delay in EF29Fl extends the CM
CURRENT duration. CM CU.RRENT is turned off 80 ns
later by CM STROBE D, via R111-E24U.
The second word extracted (from location 12) contains
ACO, ARI, IRI, and CMA24. ACO(1) and ARI(1)
gate the contents of the AC (placed there by a previous
instruction) into the AR via the A bus, ADR, and 0
bus. These processes prepare for the execution of
certain logical (AND,XOR), arithmetic (ADD ,TAD) ,
lOT, and OPR instructions.
IRI(1) of the second word turns on inverter B104-F31 l
(KC16) in conjunction with MBI(O) and CM STROBE
DlYD. The inverter output goes to ground, triggering the 50-ns delay B310-EF29FU. Upon recovery,
the delay produces an IN ClR pulse and a ClR pulse.
5-1
IN C lR produces 1 -P MBI to set the MBI gate, and
generate ClR I, drawing KC19(2). ClR I resets ACI ,
ARI I PCI, MQI, and MBO. ClR resets +1 and ACO,
and sets SAO. MEM STROBE, STROBE 0-8 and
STROBE 9-17 occur in core memory, drawing MC1.
Strobes 0-8 and 9-17 strobe the sense amp Ii fi er
contents SAOO-17 out to the CP/memory interface.
The sense amplifiers contain the instruction word read
from core memory at the address specified by the
contents of the MA.
TI(l) /\ IR4(1) examines the main core memory address
bits MB05-14 for autoindexing, drawing KC14. Bits
MB05-14 are wired directly from the MB to the input
gating structure at the AUT INX flip-flop.
SAO(l) gates the sense amplifier outputs onto the B
bus and IRI(1) gates the op code portion SAOO-04
into the IR. The B bus contents I SAOO-17, go directly into the ADR, and NOSH places them on the 0 bus.
MBI(1) then gates the contents into the MB. Thus,
the entire instruction word reaches the MB for execution in accordance with the op code in the IR.
The third word remains in the CM sense flip-flops
unti I the next ClK pulse occurs. SM(l) waits for
CM ClK to start the next computer cycle. During
this waiting period, the core memory write-half-cycle
restores the instruction word in the MB to the location
specified by the MA. Neither the MB nor the MA has
changed its contents up to this point, therefore I the
instruction word is restored to the same location from
which it was fetched. When the write-half-cycle
ends, the next computer cycle begins and MA JAM
enters the address portion of the instruction word
from the MB into the MA. This sets up the core
memory address of the operand which is referenced by
the next computer cyc Ie.
If IR4 = 0, then TI(l) /\ IR4(0) examines the IR bits at
Rlll-F234 for CAl-;, JMS -;;, DAC -;;, or DZM-;;,
drawing KC17. If any of these are detected, the
address gates boost the address from 30 to 32 (lAO
entry) .
At th is ti me, a request execution phase (REP) is determined (KC12). REP results if IRI(l) detects an lOT
(R 111..:E 14HL OPR (R lll-E 14H) , XCT (R 111-E14U) I
JMP * R111-E14U), oran optional EAE instruction
(R111-E14N). IRI(l) also sets the lOT flip-flop if a
LAW I OPR, or lOT instruction is detected f or the
CAL flip-flop if a CAL instruction is detected. The
op code bits are also sampled for the ISZ instruction,
independently of IRI(l).
*"
Depending on the conditions sensed by the IR samplings
during fetch, the next computer cycle will be another
fetch in the case of REP I a defer cycle in case of indirect addressing, an lAO cycle for JMS *, CAL *,
DAC -;;, or DZM -;; I or an execute cyc Ie.
MEM STROBE and IAO(O) start the CM timing, drawing KC16, for the third CM STROBE. MEM STROBE
/\ IAO(O) triggers pulse amplifier B602-F32D via
Rll1-E31U. The PA pulse triggers the 50-ns delay
B310-EF33Fl, and the timing chain restarts.
5.1.2 Defer Cycle
REP allows the op code bits in the IR to change the
address presented to the CM address selectors from
24 to the address appropriate to the detected instruction (CMA70, 74,75,76,77). Note that, following
the REP detection for OPR, lAW or JMP instructions,
the instruction is executed within the fetch cycle
period and the next computer cycle ensues on the
fetch entry process word 21. For XCT I a quasi -fetch
cycle tagged XCT entry ensues. For lOT instructions,
the fetch cycle is extended by a 4.5-1-'5 execute period
during which the main core memory is idle, and the
next fetch cyc Ie ensues.
Assuming that there is no REP for the sake of convenience, the third word is extracted from CM location
24. Th is word conta i ns TI ISM, and CMA30. TI (1)
(test for indirect address) samp les IR4 at R111-F23H
on drawing KC17 for indirect addressing. If IR4 = 1,
then TI (1) /\ I R4(1) at R111-F23H boosts the CM
address from 30 to 31 (defer entry). At the same time,
During the third process of the fetch cyc Ie I refer to
flow drawing KC3, the address in the CMA for the
next process word is 30 (execute entry). The TI(l)
level samples the IR4 bit on drawing KC17. If IR4= 1,
the instruction word read out to the MB during fetch
does not contain a direct address of an operand, but
rather an indirect address; i.e., the address of the
effective address. In this case, TI(1)/\IR4(1) on
drawing KC17 enables the CMA5 gating at the
address selectors in control memory. SM(1) is present
in the process word to start the core memory cycle
and the control memory timing on the next ClK pulse.
The CMA5 gate boosts the existing address (30) to 31,
from which the defer entry process word is taken at
CM STROBE time.
Process word 31 contains the DEI (defer/execute initiate) process bit and CMA24. DEI(1) resets IR4 and
CAL, on drawing KC12. CM STROBE DlYD, MBI(O)
EXT(O), and DEI(l) produce an IN ClR and a ClR
5-2
pulse qfter a recovered delay, drawing KC16. IN
C lR produces 1 ... MBI to set the MBI sense fli p-flop,
drawing KC19(2), and ClR sets SAO on drawing
KC19(3), as for the fetch cycle. SM STROBE is
prevented from restarting the CM timing chain for
the next CM STROBE by the absence of a CONT(1)
bi tin the defer entry word. Therefore, the defer
entry word remains in the sense flip-flops until MEM
STROBE restarts the chain. MEM STROBE, STROBE
0-8, and STROBE 9-17 occur in core memory, as for
the fetch cycle, to read the effective address word
into the MB. Note that the op code placed in the IR
during fetch remains unchanged throughout the defer
cycle. This leaves bits MBOO-04'of the effective
address word available for addressing extended memory
systems and for use as pointer bits. Because of this
scheme, DEI(1) resets IR4 to limit indirect addressing
to one level.
autoindex location, its contents comprise an effective
address (Y) which is incremented by 1 during a defer
cycle before the instruction is executed. During
defer, the core memory write-half-cycle replaces Y
with Y+1 in the autoindex location. During execute,
therefore, the operand is fetched from location Y+1 .
Jumping repeatedly to an rnstruction which thus indirectly addresses the same autoindex location wi II
repeatedly increment Y. This simplifies a program
which performs the same arithmetic operation on
sequentially located operands.
The instruction word is read out to the MB and the IR
during fetch (Section 5.1.1) where IR4 is examined
by n(1) for indirect addressing. For indirect addressing, IR4 = 1; so, the n(l) and IR4(1) levels sample
address bits MB05-14 of the instruction word at the
AUT INX flip-flop, drawing KC14. If bits MB05-14
designate address 0001X, they set the AUT INX flipflop B213-D36. Examination of the least-significant
bits MB 15-17 is unnecessary.
~efore MEM STROBE produces CM STROBE as for
fetch, DEI(1) samples the IR bits for REP, drawing
KC12. Since DEI(l) has reset IR4, it can now sample
the IR for JMP :;; and XCT ;;.
During defer, the core memory read-half-cycle reads
out the effective address from the autoindex location.
IN ClR and ClR set SAO and MBI so that the effective
address gets to the MB via the B bus, ADR, and 0 bus.
Now, SAO(1) is gated with AUT INX(1) on drawing
KC14, to produce the ground CIl7 level. CIl7 increments the effective address by 1 as the address
passes through the ADR. NOSH takes the ADRcontents
to the 0 bus and MBI(1) places them in the MB. The
core memory write-half-cycle writes the incremented
address into the autoindex location. The incremented
address also remains in the MB in preparation for the
execute or lAO cycle. The defer processes branch to
process word 24 for most memory reference instructions to process word 70 for XCT or to 74 for JMP.
n(1) A IR4(0) resets AUT INX during process word
24 or 70, and PCI(l) resets AUT INX during process
word 74.
MEM STROBE A IAO(O) produces the CM STROBE
which extracts the next process word (CMA 24) if not
changed by REP as for fetch. Since DEI(1) has reset
IR04 and CAL, n(1) can neither enable CMA5 for
another defer cycle nor process a true GAL instruction in a subsequent lAO cycle. If a CAL * instruction is programmed, it will be treated in the defer
cycle as a JMS * fetching an effective address from
core memory location 00020. A subsequent lAO cyc Ie
will store the conditions of the program exit point at
the location reached by the effective address, and
the following fetch cycle will take its instruction
from that location +1 (see Sections 5.1.6.3 and
5.1.6.8). Similarly, an lAO cycle follows defer if
n (1) A IR4(0) detects a JMS *, DAC *, or DZM * op
code on drawing KC17. Consequently, the CM
address for the next process word can change from
30 (execute entry) to 32 (lAO entry) or can remain at
30. SM(1) and the next ClK pulse will initiate the
next computer cyc Ie to fetch the operand (or instruction) located in core memory at the effective address.
5.1.4 lAO Cycle
5.1.3 Autoindexing
The us~ of the eight autoindex core memory locations
10-17 must be predetermined by program requirements.
If an instruction word directly addresses an autoindex
location, its contents comprise an operand which is
treated like any other operand in executing the instruction. If the instruction word indirectly addresses an
5-3
The lAO cycle replaces the normal execute cycle
for CAL, JMS, DAC, and DZM instructions. These
instructions neither see nor care about the contents of
the core memory locations which they address. During
their execution, SAO(l) is absent in the operand processing, so that the cote memory read-half-cycle is
ignored and the contents of the addressed location
are, therefore, lost. The write-half-cycle stores new
information in the addressed location in accordance
with the particular instruction.
instruction fetch cycle. CONT(l) in the execute word
a 1I0ws the generation of another CM STROBE to extract
the BG N word.
5.1.5 Execute Cycle
The computer enters the execute cyc Ie from either the
fetch cycle or the defer cycle (refer to flow diagrams
KC3 and KC4). Process word 24 occurs in both
cases and remains until the next ClK pulse arrives.
SM(l) of process word 24 and the next ClK pulse
start the control memory process and the core memory
cycle. MA JAM occurs after ClK to gate the direct
address (during fetch) or the effective address (during
defer) into the MA from the MB. Now the core
memory read-half-cycle wi" fetch the operand for
execution of the instruction.
The core memory write-half-cycle starts independently
during the execute process word period. For some
memory reference instructions (lAC, XOR, ADD, TAD,
AND, SAD), the memory write-half-cycle restores the
original operand to memory while it is being manipulated elsewhere in the CP. For ISZ the operand is incremented by 1 before being written back into memory.
The remaining instructions (DAC, DZM, JMS, CAL)
replace the operand entirely in the special JAO cycle.
In ,the last two cases, the original operand is lost.
The CM address held in the control register during
process word 24 is 30 (execute entry). SM(l) and CM
ClK pulse generate the first CM STROBE in control
memory. CM STROBE extracts the execute-entry
process word at location 30, which contains CJIT I
DEI, and CMA60.
The CM STROBE DlYD produces an IN ClR and a
ClR pulse in conjunction with DEI(l) I EXT (0) , and
MBI(OL drawing KC16. IN ClR produces 1 .... MBI to
set the MBI flip-flop, drawing KC19(2), and ClR sets
SAO on drawing KC19(3). CM STROBE is prevented
from restarting the CM timing chain for the second
time because of the absence of the CONT(l) bit in the
execute entry word 30. Therefore, the execute entry
word remains in the sense flip-flops unti I MEM STROBE
/\ IAO(O) restarts the chain. STROBE 0-8 and STROBE
9-17 occur in core memory to place the operand in the
MB. While the operand is on its way through the ADR
to the MB, CJIT(1) wi II produce CI17 on drawing
KC14, if the ISZ instruction op code was detected
during fetch. CI17 then increments the operand by 1
in the ADR. If no ISZ, the operand remains unchanged.
MEM STROBE /\ IAO(O) generates the next CM STROBE
to extract the next process word from control memory.
During the execute-entry process word 30, the address
in the control register for the next word is 60 (CMAO
and CMA1 = 1). This is the starting point for the
extraction of the execute word determined by the op
code in the IR register. CMAO(l) and CMA 1(1) on
drawing KC17 allow the IR bits to address the control
memory, so that address 60 is boosted to the address
specified by the op code.
lOT I OPR, and optional non-EAE multiply and divide
instructions do not require operand access. Consequently, they do not use the computer execute cycle herein
described. During the computer execute periods for
these instructions, no core memory cycle occurs. Execution of these instructions takes place during normal
(OPR) or extended (lOT I EAE) fetch cycles.
5.1.6 Memory Reference Instructions
The following paragraphs describe the logi c functions
for execution of memory reference instructions. Whereas the preceding paragraphs cover the functions that
are common to all instructions, the following discussions cover those functions that are unique to the individual instructions. The instructions are arranged
ina Iphabeti ca I order.
5.1.6.1 1's Complement Add (ADD} - The ADD instruction (30) adds the contents of the addressed memory location (addend) to the contents of the AC (augend)
in 1's complement arithmetic. The sum is deposited in
the AC and the previous contents of the AC are lost.
The contents of the addressed memory location remain
unchanged. The Link must have been previously reset
and remains reset unless an arithmetic overflow occurs.
Under the rules of 1's complement arithmetic, the sign
bits 00 in both the addend and the augend are added
as an integra I part of the magnitude bits 01-17 during
ADD. An end carry out of the sum-sign bit 00 is endaround carried into the sum-magnitude bit 17 to establish the final magnitude. Overflow occurs if the
magnitude of the sum exceeds ±2 17 -1, or ±377777.
If so, the Link sets as an indication of an error in
magnitude. The OPR-SNl or OPR-SZl instruction
can be used to check the state of the Link following
an ADD of questionable outcome.
A" memory reference instructions (except XCT) require a sing Ie 212-ns process word for execution.
For these i nstructi ons, the execute process word contains CMA 10 as the location of the next word. This
is the BGN word which sets up the MB for the next
5-4
Close examination reveals two basic rules of lIs
complement addition:
Using a hypothetical 3-bit register and a Link bit,
the examples below demonstrate all ADD possibilities.
Since this ~ a modul0-8 register, the sum magnitude
limit is ±2 -1, = 011 2 or 1002 ,
a. In like-sign addition, overflow is possible and
the sum sign differs if overflow occurs;
b. In unlike-sign addition, no overflow is possible
and the sum sign may be plus or minus.
Positive Sign ADD
(2)
(1)
0
001
001
010
or
The fetch cycle places the ADD instruction in the
MB, the op-code portion in the IR, and the contents
of the AC (augend) in the AR. The op-code is sampled but does not a Iter the execute entry address(30} .
+1
+1
+2 (valid)
001
011
100
or
+1
+3
-3 (error)
During execute, the core memory read-half-cycle
places the contents of the addressed memory location
(add~nd) in the MB in conjunction with the execute
entry word 30. The CMA in the execute entry word
is 60. CMAO(l} and CMA 1 (1) allow the IR bits to
address control memory, drawing KC17, so that the
next process word is extracted from address 66. Process word 66 contai ns MBO, ARO, ACI, AXS, LI,
DONE, CONT, and CMAI0(BGN}.
USIGN
LINK
(3)
011
011
110
or
+3
+3
=T(error}
MBO(l} places the contents of the MB on the B bus,
while ARO (1) places the contents of the AR on the
A bus (refer to Figure 5-l}. The contents of the buses~_
-are added in the ADR, with carries resulting if an
adder stage has two or more inputs representing A 1.
A carry (COOO) out of ADROO causes ADRL on drawing KC15 to go negative. ADRL gates on CIl7 in
conjunction with AXS(l}, drawing KC14. CIl7 initiates an end-around-carry into ADR17, which propagates as necessary.
Negative Sign ADD
(4)
110
110
or
-1
110
-1
100
-3
+1
-2(valid} 1 011
or
C~
C~~
0
(5)
101
-1
-3
+2
+1
+3 {error}
The ADRL module B132-A03, drawing KC15, contains
the overflow detection circuits, producing the negative ADOF level if overflow occurs. Overflow is
detected by XOR of the carries COOO and COOl out
of ADROO and ADR01. The following functions apply
to overflow detection (see ADD examples) .
Unlike Sign ADD
(7)
(6)
011
110
0
or
TIT
+1
-1
O(valid}
0
011
110
or
(O;~
010
+3
-1
+1
+1
+2 (va lid)
COOO(O}
COOO(O}
COOO-(1}
COOO(1}
CO~~
0
011
or
= ADOF
=ADOF
=ArmF
= ADOF
(ex.
(ex.
(ex.
(ex.
1,6)
2,3)
4,7,8)
5)
ADOF A AXS(1} A LI(1} produces the OFLO level at
Rll1-D02HJ, drawing KC15. LI(1}and OFLO set
the LAR.
(8)
011
111
A COOl (O)
A C001(1}
A C001(1}
A COOl (O)
+3
0
+2
+1
+3 (va lid}
DONE(l} goes to the clock and run logic, drawing
KCI0(1}, for manual key control and to KC17 for
break and PI while CONT(l} allows the generation
of another CM STROBE. CM STROBE extracts the
5-5
BGN word (10) from control memory to set up the
MB for the next fetch cycle. At this time, LI(l) goes
to 0 and sets the Link in conjunction with LAR(l) as
an indi cation of overflow.
The fetch cycle places the AND instruction in the
MB, the op-code portion in the IR, and the contents
of the AC in the AR. The op-code is sampled but
does not alter the execute entry address (30) .
LINK SAVE, gate R111-C03N (drawing KC15) sets
the Link, if the Link was not reset previous to the
ADD instruction, by gating LINK(l) and AXS(l).
LI(l) sets the LAR under this condition, then LI(O) sets
the Link with LAR(l).
During execute entry, the core memory read-half-cycle
places the contents of the addressed memory location
in the MB, in conjunction with the execute entry process word (30). The CMA in the execute entry word
is 60. CMAO(l) and CMA 1 (1) a II ow the IR bits to
address control memory, drawing KC17, so that the
next word is extracted from location 72. Process word
72 contains MBO, ARO I AND, ACI, DONE, CONT
and CMA10 (BGN). MBO(l) gates the contents of the
MB onto the B bus, while ARO(l) gates the contents
of the AR onto the A bus. The contents of both buses
go into the ADR. Additionally, the complement of
the A bus is gated onto the B bus by the AND(l) level
(A BUS, drawing KC21). AND(l) on drawing KC13
produces CMPL, which is applied to each bit of the
5.1.6.2 Logical AND (AND) - The AND instruction
(50) logically ANDs the contents of the addressed
memory location with the contents of the AC on a bitfor-bit basis. If corresponding bits are 1s, the result
is 1. If corresponding bits differ or are Os, the result
is O. The results are stored in the AC and the previous
AC contents are lost. The contents of the Link and
the addressed memory location remain the same.
CI 17 (END AROUND CARRY)
B BUS
AXS (1)
CML66MBO,ARO, LI, ACI, AXS,
DONE,CONT.CMA 10
9L-OO~2
Figure 5-1 ADD Instruction Logi c
5-6
I
ADR
~
?
B BUS
A BUS
MBO ---.
AND ---.
'VA
ARO ---.
'VA
'VA
---.
ABUSr
I
'VA
L -_ _ _ _ _--l
MB
CML 72MBO, ARO, ACI, AND
DONE,CONT, CMA 10
AC
AR
'VA
L---J~ NOSH
9L-0053
Figure 5-2
AND Logic
ADR to complement the half-add results. Figure 5-2
illustrates the AND logic for one bit position. If the
respective MB and AR bits are ls, they appear as
ground levels on the A and B bus inputs to the ADR.
Th is results in a ground level output whi ch is then
forced to -3V by the CMPL level. NOSH gates the
negative level onto the 0 bus and ACI(l) jams a 1
into the AC.
If the respective bits differ, one of the inputs to the
ADR is at ground and the ADR output goes negative.
CMPL then forces it to ground. NOSH places a negative level on the 0 bus rand ACI(l) jams a 0 into the
AC.
DONE(l) goes to the clock and run logic (drawing
KC10(1) for manual key control and KC17 for break
and PI) while CONT(l) allows the generation of another CM STROBE. CM STROBE extracts the BGN
word (l0) from contro I memory I wh i ch sets up the MB
for the next fetch cyc Ie.
5.1.6.3 Call Subroutine (CAL) - The CAL instruction
(00) is equivalent to instruction JMS 20, Section
5.1.6.8. The contents of the PC, the Link, and the
status of the extended memory mode and memory
protect mode (on or off) are deposited in memory location 00020. The previous contents of location 00020
are lost. The next instruction is read from memory
location 00021 f breaking the previous program sequence. The contents of the AC and Link remain unchanged.
If the respective I;>its are Os, both buses go negative,
but A BUS makes the B bus go to ground to present the
ADR with the "differ" conditions above. The result is
a 0 in the AC.
5-7
The fetch cycle places the CAL instruction in the MB,
the op-code porti on in the IR, and the contents of the
AC in the AR. The op-code is detected to set the CAL
flip-flop, drawing KC12, and to extract the next process word from location 24 on the next CM STROBE.
Process word 24 contains TI, SM, and CMA30. TI(l)
on drawing KC17 samples bits IRO, IR1, and IR4 at the
CM address gating. For a CAL '* instruction (and
DAC '*, DMZ *, and JMS *, these bits are all Os,
changing the presented CM address from 30 (execute
entry) to 32 (lAO entry). TI(l) and CAl(1) from the
set CAL flip-flop place a 1 level (ground) on 0 BUS 13,
drawing KC22. SM(l) waits for ClK on drawing
KC19(2) at the 1 .... MBI gate. ClK occurs in core memory just before the next CM ClK pulse starts the lAO
cycle. At the 1 .... MBI gating, CLA(l) A SM(l) A ClK
produces the 1 .... MBI level, setting the MBI flip-flop.
MBI (l) gates address 00020 from the 0 bus to the MB.
SM(l) and CM ClK generate CM STROBE in the CM
timing, drawing KC16, to extract the lAO entry word
from location 32. Process word 32 contains PCO, ARI,
CONT, and CMA23. PCO (1) gates the current contents of the PC, EPC, the Link, memory EXD mode,
and memory protect mode status onto the A bus.
The contents on the A bus go directly through the
ADR and NOSH places them on the 0 bus. ARI(1)
transfers the contents of the 0 bus to the AR.
For any memory capacity up to fully-extended 32K
systems, the PC register uses only 13 bits of the 18
available in the normal computer word, PC05-17.
Of the five vacant bits in the address, bits 00-02 are
used for gating the Link, EXD mode and memory
protect mode status onto A BUS 00, A BUS 01, and
A BUS 02, respectively, drawing KC20(1). The remaining bits EPC03, EPC04 come from the extended
memory control option. Then ARI (l) of process word
32 gates these status bits into the AR, along with the
contents of the PC above.
Note that during this second process word (23) of the
lAO cycle, MEM STROBE, STROBE 0-8, and STROBE
9-17 occur in core memory to read out the contents
of memory location 00020. However, the SAO and
MBI gates are disabled in the absence of ClR on
drawi ng KC 16, so that the contents cannot reach the
MB and are therefore lost.
CONT(l) in process word 23 allows CM STROBE to
restart the CM timing to extract the third process word
from Iocati on 60. Process word 60 contai ns ARO, MBI I
DONE, CONT and CMA10 (BGN). ARO(l) gates the
contents of the AR onto the A bus. (The AR contains
the disrupted address from the PC, EPC, and the
status bits discussed earlier.) The contents on the A
bus go directly into the ADR and NOSH places them
on the 0 bus. MBI (1) gates the contents from the 0
bus to the MB. At this time the core memory writehalf-cycle stores this PC and status information in
location 00020.
DONE(l) goes to the clock and run logic, drawing
KC10(l) for manual key control and KC17 for break
and PI while CONT(l) allows the generation of the
fourth CM STROBE to extract the BGN word from
location 10. The BGN word gates the new address
held in the PC (00021) into the MB for the next fetch
cycle. Thus, a new sequence of instructions starts from
address 00021. A JMP * instruction can be used to
return to the sequence stored at 00020. JMP * should
be preceded by an lOT DBR instruction in order to restore the status bits to the system.
5.1.6.4 Deposit Accumulator (DAC) - The DAC
instruction (04) deposits the contents of the AC in the
addressed memory location. The previous contents of
the addressed memory location are lost and the contents
of the AC and Link remain unchanged.
The fetch cycle places the DAC instruction in the MB,
the op-code portion in the IR, and the contents of the
AC in the AR.
CONT(l) allows CM STROBE to restart the CM timing
for the extraction of the next process word from location 23. Process word 23 contains MBO, +1, CJIT,
CO NT, and CMA60. MBO (1) gates the contents of
the MB (00020) to the B bus, and then directly to the
ADR. Process +1 produces Cll7 on drawing KC14,
which increments the address as it passes through the
ADR. NOSH places the incremented address (00021)
on the 0 bus. CJIT(l) generates 1 .... PCI on drawing
KC12 in conjunction with the IROO, IR01, and IR03
bits (all Os). The 1 .... PCI level sets the PCI flip-flop,
drawing KC19(2). PCI(l) then gates address 00021
from the 0 bus into the PC.
The op code is detected to extract the next process
word from location 24 on the next CM STROBE. Process word 24 contains TI, SM, and CMA30. TI(l) on
drawing KC17 samples bits IRO, IR1, and IR4 at the
CM address gating. For a DAC 7; instruction (and
CAL *, JMS *, DZM *) these bits are all Os, changing the presented CM address from 30 (execute entry)
to 32 (lAO entry) .
SM(1) and the next CM ClK pulse generate CM
STROBE in the CM timing, drawing KC16, to extract
the lAO entry word from location 32. Process word
5-8
32 contains PCO, ARI, CONT, and CMA23. PCO(1)
gates the current contents of the PC, EPC, Link I
memory EXD mode, and memory protect mode status
onto the A bus. The contents on the A bus go directly
through the ADR, and NOSH places them on the 0
bus. ARI (1) transfers the contents of the 0 bus to the
AR. This process is common and useful only to the
CAL and JMS instructions (and to program interrupt
operations) where the current contents of the PC, EPC,
and the status bits are to be stored in core memory.
For DAC (and DZM) instructions, the contents do not
get past the AR.
program count and status storage. For DAC, I R3
so that the PCI gate does not set.
= 1,
Note that MEM STROBE, STROBE 0-8 I and STROBE
9,...17 occur in core memory to read out the contents
of the addressed memory location. However I the
SAO and MBI gates are disabled in the absence of
CLR on drawing KC16 r so that the contents cannot
reach the MB and are therefore lost. Process word
61 wi II replace these contents with the contents of
the AC.
CONT(l) allows CM STROBE to restart the CM timing
chain to extract the next process word from location
23. Process word 23 contains MBO, +1, CJIT, CONT,
and CMA60. MBO(l) gates the contents of the MB
(DAC instruction) onto the B bus, and the B bus contents go directly into the ADR. NOSH places the
ADR contents on the 0 bus. For DAC, the contents
do not get beyond the 0 bus.
CONT(1) allows CM STROBE to extract the third
process word. The CMA in process word 23 is 60.
CMAO(1) and CMA 1 (1) allow the IR bits to address the
control memory, in which case IR3(l) changes the
presented address from 60 to 61. Process word 61
contains ACO, MBI, DONE, CONT, and CMA10
(BGN). ACO (1) gates the contents of the AC onto the
A bus (refer to Figure 5-3) I the contents go from the
A bus to the ADR, and NOSH places them on the 0
bus. MBI (1) gates them from the 0 bus to the MB.
This process is useful only to the CAL and JMS instructi ons (and to proqram interrupt operati ons) where
CJIT(l) /\ IR3(0)~produce 1 ..;. PCI on drawing KC12 for
DONE(1) goes to the clock and run logic, drawing
KC10(1) for manual key control and KC17 for break
and PI, while CONT(1) allows the generation of a
DAC
CAL
JMS
DZM
CML 61
CML60
CML62
CML63
ACO, MBI,DONE,CONT,CMA 10
ARO,MBI,DONE,CONT,CMA 10
ARO,MBI,DONE,CONT,CMA 10
MBI,DONE,CONT,CMA 10
ADR
A BUS
MB
AC
AR
9L-0054
Figure 5-3
lAO Instruction Logic For:
DAC, CAL, JMS, and DZM
5-9
fourth CM STROBE to extract the BGN word(10}. The
BGN word sets up the MB for the next fetch cycle.
5.1 .6.5 Deposit Zero in Memory {DZM} - the DZM
instruction (14) deposits all Os in the addressed memory location. The previous contents of the addressed
location are lost and the contents of the AC and Link
remain unchanged.
The fetch cycle places the DZM instruction in the MB,
the op-code portion in the IR, and the contents of
the AC in the AR.
The op code is detected to extract the next process
word from location 24 on the next CM STROBE. Process word 24 contains TI, SM, and CMA30. TI(l} on
drawing KC 17 samples bits IRO, IR1, and IR4 at the
CM address gating. For a DZM; instruction (and
CAL ;, DAC;, JMS;) these bits are all Os, changi ng the next CM address from 30 {execute entry} to
32 (lAO entry) .
SM(l} and the next CM ClK pulse generate CM
STROBE in the CM timing, drawing KC16, to extract
the lAO entry word from location 32. Process word 32
contains pca, ARI, CONT, and CMA23. PCO(l}
gates the current contents of the PC, EPC, Link, memory extend mode, and memory protect mode status
onto the A bus. The contents on the A bus go directly
through the ADR and NOSH places them on the 0 bus.
ARI(l} transfers the contents of the 0 bus to the AR.
This process is common and useful only to the CAL and
JMS instructions {and program interrupt operations}
where the current contents of the PC are stored in core
memory along with the status bits. For DZM and DAC
instructions the contents do not get past the AR.
CONT(1} allows CM STROBE to restart the CM timing
chain to extract the next process word from location
23. Process word 23 contains MBO, +1, CJIT, CONT,
and CMA60. MBO(1} gates the contents of the MB
{DZM instruction} onto the B bus, and the B bus contents go directly into the ADR. NOSH places the
ADR contents on the 0 bus. For DZM, the contents
do not get beyond the 0 bus. This process is useful
only to the CAL and JMS instructions {and to program
interrupt operations} where CJIT A IR3{0} on drawing
KC12 produces 1 .. PCI for program count and status
storage. For DZM, IR3 = 1, so that the PCI gate does
not set.
Note that MEM STROBE, STROBE 0-8, and STROBE
9-17 occur in core' memory to read out the contents of
the addressed memory location. However, the SAO
and MBI gates are disabled in the absence of ClR on
drawing KC16, so that the contents cannot reach the
MB, and are therefore lost. Process word 63 wi II replace these contents with Os.
CONT{l} allows CM STROBE to extract the third process word. The CMA in process word 23 is 60.
CMAO(l} and CMA1(l} allow the IR bits to address
the control memory, in which case the presented
address is changed from 60 to 63. Process word 63
contains MBI, DONE, CONT, and CMA10 {BGN}.
MBI(1} gates the contents of the 0 bus into the MB.
Since there is nothing on the 0 bus at this time, the
MB is loaded with Os.
DONE(l} goes to the clock and run logic, drawing
KC10(l} for manual key control and KC17 for break
and PI, while CONT(1} allows the generation of a
fourth CM STROBE to extract the BGN word (10). The
BG N word sets up the MB for the next fetch cyc Ie.
5.1.6.6 Increment and Skip if Zero (ISZ) - The ISZ
instruction {44} increments the contents of the addressed memory location by 1 and tests the result. If the
result is 0, the contents of the PC are incremented by
1, so that the computer skips the next instruction. If
the result is other than 0, the computer executes the
next instructibn. The contents of the AC and Link
remain unchanged.
The fetch cycle places the ISZ instruction in the MB,
the op-code portion in the IR and the contents of the
AC in the AR.
The op code is detected to produce the ISZ level,
drawing KC12, and to extract the next process word
from locati on 24 on the next CM STROBE. TI (1) of
process word 24 tests for indirect addressing and SM{l}
waits for the next CM ClK pulse to restart the CM
timing and the core memory cycle. The CM address
in process word 24 is 30 {execute entry}. SM(l} and
CM ClK generate CM STROBE to extract the execute
entry word. This word contains CJIT, DEI, and
CMA60. During the execute entry process, the core
memory read-half-cycle places the contents of the
addressed memory location in the MB via the B bus,
ADR, and 0 bus. The absence of the CONT(l} bit
in process word 30 means that the process remains
active throughout the period normally allotted to a
second process word.
Therefore, as the contents of the addressed memory
location pass through the ADR, CJIT(l} is present,
5-10
on drawing KC14, to produce CIl7 in conjunction
with the ISZ level. CIl7 is applied to ADR17 to increment the contents.
to the jam input gate of the ADR = 0 SAVE flip-flop,
drawing KC14. ARI(l) of the process word sets the
flip-flop and gates the contents of the 0 bus into the
AR.
MEM STROBE in core memory and IAO(O) restart the
CM timing on drawing KC16. Since the CM address
in process word 30 is 60, CMAO(l) and CMA1(1) allow
the IR bits to address the control memory, drawing
KC 17. The IR bits boost the address to 71 so that
CM STROBE, initiated by MEM STROBE, extracts the
next process word from that location. Process word
71 contains MBO, ARI, SKPI, DONE, CONT ,and
CMA10 (BGN). MBO(l) gates the incremented
contents from the MB to the B bus, the B bus contents
go through the ADR directly, and NOSH places them
on the 0 bus. (Refer to Figure 5-4.) As the contents
pass through the ADR, an output bus (ADRA = 0,
ADRB = 0) goes negative if the ADR goes to all Os.
The negative ADRA = 0, ADRB = 0 levels are applied
The core memory write-half-cycle writes the incremented contents of the MB into the addressed memory location. ADR = 0 SAVE(l) and ISZ are gated on drawing
KC14 to place a ground level at the jam input gate of
the SKIP flip-flop. SKPI (1) of process word 71 sets the
flip-flop. (The flip-flop was reset by PCI(l) during
the fetch entry process word 21 .)
CONT(l) of process word 71 allows the generation of a
third CM STROBE to extract the BGN word from location 10. With the SKIP flip-flop set, PCO(l) of the
BGN word produces C1l7, drawing KC 14, so that the
current contents of the PC are incremented by 1 as they
pass through the ADR to the 0 bus and MB.
CI 17
ISZ
IRO
IR 1
IR2
IR3
(1) __ ~.r--..,
(0)
(0)
(I) ~""\...._....J
CML71MBO,ARI,SKP I, DONE,
CONT, CMA 10
9L-Q055
Figure 5-4
ISZ Instruction Logic
5-11
5.1.6.7 Jump (JMP) - The JMP instruction (60) transfers the program sequence to the address specified in
the instruction. If the JMP instruction contains a
direct address, this address is transferred during fetch
to the PC (refer to fetch flow diagram KC3). If the
JMP instruction contains an indirect address, the
computer enters a defer cycle to fetch the effective
address. REP then transfers the effective address to the
PC duri ng defer. In both cases, the previ ous contents
of the PC are lost. The computer enters another fetch
cycle from the new address in the PC. The contents of
the AC and Link remain unchanged.
During fetch, IRI(l) detects the JMP -; op code in the
IR bits to provide the REP ground level, drawing KC12.
During defer, DEI(1) resets IR4, and thus also detects
a JMP op code for REP. REP goes to the CM addressing
logic, drawing KC17, to gate the IR bits into the
address selectors. The CM STROBE derived from MEM
STROBE causes the. third process word to be extracted
from location 74 (JMP). The word in 74 contains
MBa, PCI, LI, DONE, CaNT, and CMA10 (BGN).
MBO(1) gates the address in the JMP instruction from
the MB to the B bus, where it is fed directly into the
ADR (refer to Figure 5-5). NOSH gates the address
onto the a bus and PCI(1) puts it in the PC. LI (1)
gates the Link content into the lAR via the ADRl.
DONE(1) goes to the clock and run logic, drawing
KC10(1), for manual key control and KC17 for break
and PI, while CONT(1) allows the generation of a
fourth CM STROBE. The fourth process word to be
extracted is the BGN word (10) which sets up the MB
for the coming fetch cycle. LI(l) of process word 74
goes to 0 at BGN time, strobing the content of the
tAR into the Link. This recirculation of the Link is
done mainly to restore the Link status when JMP is
preceded by DBR, Section 8.1.7.
*
B BUS
LI(O)
ADRL
CML 74
MBO,PCI,LI, DONE,
CMA 10
9L-0056
Figure 5-5
JMP Instruction logic
5-12
5.1 .6.8 Jump to Subroutine (JMS) - The JMS instruction (10) permits exit from the main program into a
subroutine. The contents of the PC, the Link, and the
status of the EPC, extended memory mode, and mem0ry protect mode are deposited in the addressed memory locotion Y. The next instruction is taken from
location Y+l, breaking the main program sequence
and starting a new sequence from Y+l. The previous
contents of Yare lost, and the contents of the AC
and Link remain unchanged.
The fetch cycle places the JMS instruction in the MB,
the op-code portion in the lR, and the contents of the
AC in the AR.
The op code is detected to extract the next process
word from location 24 on the next CM STROBE. Process word 24 contgins TI, SM, and CMA30. TI(l) on
drawing KC17 samples bits IRO, lRl, and lR4 at the
CM address gating. For a JMS instruction (and
DAC *, DZM *, CAL *) these bits are aliOs, changing the CM address from 30 (execute entry) to 32
(lAO entry) .
*
SM(l) and the next CM ClK pulse generate CM
STROBE in the CM timing, drawing KC16 1 to extract
the lAO entry word from location 32. Process word
32 contains peo, AR1, CONTI and CMA23. PCO(1)
gates the current contents of the PC onto the A ,bus.
The contents on the A bus go directly through the
ADR, and NOSH places them on the 0 bus. AR1(1)
transfers the contents of the 0 bus to the AR.
For any memory capacity up to fully extended 32K
system, the PC register uses only 13 bits of the 18
available in the normal computer word, PC05-I7.
Of the five vacant bits in the address, bits 00-02 are
used to gate the Link, EXD mode and memory protect
mode status onto A BUS 00, A BUS 01, and A BUS 02,
respectively I drawing KC20(l). The remaining bits
EPC03, EPC04, come from the extended memory control option. ARI(1) of process word 32 then gates
these status bits into the AR along with the contents
of the PC above.
CONTO) allows CM STROBE to restart the CM timing
for the extraction of the next process word from location 23. Process word 23 contains MBO I +1, CJIT I
CONT, and CMA60. MBO(1) gates the contents of
the MB (address Y) to the B busl and the contents go
from the B bus directly to the ADR. Process +1 (1)
produces CIl7, on drawing KC14, thus incrementing
the address as it passes through the ADR.
IR3 bits (a II Os). The 1 .... PCI level sets the PCI fli pflop, drawing KC19(2). PCI(1) then gates address
Y+l from the 0 bus into the Pc.
Note that during this second process word (23) of the
lAO cycle, MEM STROBEl STROBE 0-8, STROBE9-17
occur in core memory to read out the contents of
memory location Y. However, the SAO and MBI gates
are disabled in the absence of ClR on drawing KC16,
so that the contents cannot reach the MB and are
therefore lost.
CONT(l) allows CM STROBE to restart the CM timing
for the extraction of the third process word. The CM
address in process word 23 is 60 (CMAO, CMA 1 = 1) .
CMAO(l) and CMAlO) allow the IR bits to address the
control memory, in which case IR2(1) changes the
address from 60 to 62. The process word at location
62 is extracted at the third CM STROBE . Process word
62 contains ARO, MB1, DONE, CONT, and CMAIO
(BGN). ARO (1) gates the contents of the AR onto the
A bus. (The AR contains the disrupted contents of the
PC, EPC, and the Li nk I EXD mode I and memory
protect mode status discussed earlier.) The contents
on the-A bus go directly into the ADRI and NOSH
places them on the 0 bus. MBl (1) gates the contents
from the 0 bus to the MB. At this time, the core
memory write-half-cycle stores this PC and status information in location Y.
DONE(1) goes to the clock and run logic, drawing
KC10(l), for manual key control and KC17 for break
and PI, while CONT(l) allows the generation of the
fourth CM STROBE to extract the BGN word (10). The
BGN word gates the new address held in the PC (Y+l)
into the MB for the next fetch cycle. Thus a new
sequence of instructions starts from address Y+l. A
JMP * instruction can be used to return to the stored
sequence at Y. JMP * should be preceded by an lOT
DBR to restore the stored status bits to the system (Section 8.1.7).
5.1.6.9 load the Accumulator (LAC) - The LAC
instruction (20) loads the contents of the addressed
memory location into the AC. The previous contents
of the AC are lost and the Link remains unchanged.
The fetch cycle places the LAC instruction in the MB,
the op-code portion in the IRI and the contents of the
AC in the AR. The op code is sampled but does not
alter the execute entry address (30). During execute,
NOSH places the incremented address (Y+l) on the 0
bus. CJIT(1) of process word 23 generates 1 .... PCI on
drawing KC12 in conjunction with the IRO, IR1, and
5-13
the core memory read-half-cycle places the contents
of the addressed memory location in the MB in conjunction with the execute entry word 30. The CMA
in the execute entry process word is 60. CMAO(1)
and CMA1(1) allow the IR bits to address the control
memory, drawing KC17. The CM STROBE initiated
by MEM STROBE then extracts the next process word
from location 64. Process word 64 contains MBO,
ACI, DONE, CONT, and (MAlO. MBO(1) gates
the contents of the MB onto the B bus, the B bus
contents go directly through the ADR, and NOSH
places them on the 0 bus (refer to Figure 5-6). ACI(1)
gates the contents on the 0 bus into the AC.
DONE(1) goes to the clock and run logic, drawing
KC10(1) for manual key control and KC17 for break
and PI, while CONT(1) allows the generation of a
third CM STROBE to extract the BGN process word
from location 10. The BGN word sets up the MB for
the next fetch cyc Ie.
5. 1 .6.10 Skip if AC Differs (SAD) - The SAD instruction (54) compares the contents of the addressed memory location with the contents of the AC. If the contents differ, the PC is incremented by 1 and the computer skips the next instruction. If the contents are
the same, the computer executes the next instruction.
The contents of the addressed memory location and
the contents of the At and Link remain unchanged.
The fetch cycle places the SAD instruction in the MB,
the op-code portion in th.e IR, and the contents of the
AC in the AR. The op code is sampled but does not
a Iter the execute entry address 30. During execute
the core memory read-half-cycle places the contents
of the addressed memory location in the MB in conjunction with the execute entry word. The CMA in
the execute entry word is 60. CMAO(1) and CMA1(1)
allow the IR bits to address the control memory drawing KC17. The CM STROBE initiated by.MEM
STROBE then extracts the next process word from
location 73·. Process word 73 contains SUB, ACO,
AXS, SKPI, ARI, DONE, CONT, and CMA10 (BGN).
SUB(1) takes the complement of the MB to the B bus
and ACO(l) takes the direct outputs of the AC to the
A bus (see Figure 5-7). Both A bus and B bus contents
go directly to the ADR. If the output bus levels are
both at ground or are both negative for any bit position, their corresponding MB and AC inputs differ
and the half-add result out of the ADR bit is at ground.
In the ADR, CMPL complements the half-add result,
forcing the ADR bit output to go negdtive. CMPL is
derived from AXS(l) of the process word and IR3(l)
on drawing KC13. All ADR bit outputs are inverted
ADR
B BUS
MBO(ll
CML 64
MBO, ACr, DONE,CONT, CMA 10
'VA
NOSH
9L-0057
Figure 5-6
LAC Instruction Logic
5-14
ond ore placed on one of two common buses (ADRA =0,
AORB =0). Thus, a difference in any bit position
forces a bus to ground.
On drawing KC14, AXS(1) is NAND-gated with the
NORed ADRA = 0 or ADRB = 0 level at ground. This
gate (R111-E35U) places a ground level at the jam
input gate of the SKIP flip ...flop. SKPI(l) of the process word sets the SKIP flip-flop. (The SKIP flip-flop
was reset by PCI(l) of the fetch entry process word 21.)
DONE(1) goes to the ciock and run logic, drawing
KC10(1) for manual key control and KC17 for break
and PI, while CONT(1) allows the generation of a
third CM STROBE to extract the BGN process word
from location 19. With the SKIP flip-flop set, PCO(l)
of the BGN word produces CIl7, drawing KC14, so
that the contents of the PC are incremented by 1 as
they pass through the ADR to the 0 bus and MB.
5.1.6.11 2 1s Complement Add (TAD) ... The TAD instruction (34) adds the contents of the addressed memory location to the contents of the AC in 2 1s complement arithmetic. The sum is deposited in the AC and
the previous contents of the AC are lost. The contents
of the addressed memory location remain unchanged.
A carry out of the sum sign bit 00 complements the
Link.
The fetch cycle places the TAD instruction in the MB,
the op-code portion in the IR, and the contents of the
AC in the AR.
The op code is sampled but does not alter the execute
entry address 30. Duri ng execute entry, the core
memory read-half-cycle places the contents of the
addressed memory location in the MB in conjunction
with the execute entry word. The CM address in the
execute entry word is 60 (CMAO, CMA 1 = 1). CMAO(1)
and CMA1(1) allow the IR bits to address the control
CI17
CMPL
A BUS
AXS
IR3
B BUS
SUB
ACO
CML73SUB, AXS, ARI ,ACO, SKP I,
DONE,CONT,CMA 10
~L-0058
Figure 5-7
SAD Instruction Logic
5-15
memory, drawing KC17, so that the next word is extracted from location 67. Process word 67 contains
MBO, ARO, ACI, LI, DONE, CONT, and CMA10
(BGN) .
for the next fetch cycle. The LI process upon going
to 0 strobes the status of theLAR into the Link.
5. 1 .6.12 Execute (XCT) - The XCT i nstructi on (40)
causes the computer to execute the instruction contained inthe addressed memory location. If the XCT
il)struction contains a direct address, REP is detected
during fetch. The computer waits for the next ClK
pulse, then enters a quasi -fetch cycle which fetches
the instruction to be executed. If the XCT instruction
contains an indirect address, the computer goes into
a defer cycle to fetch the effective address , then
enters the quasi -fetch cycle.
MBO(l) places the contents of the MB on the B bus,
while ARO (1) places the contents of the AR on the A
bus (refer to Figure 5-8). The contents of the buses
are added in the ADR, with carries resulting where
two or more input bits are 1s.
NOSH gates the contents of the ADR to the 0 bus ,
and ACI(1) gates them into the AC. LI(1) on KC15
samples the state of ADRl at the LAR. ADRl represents the state of the Link. If the Link was set and
no carry resulted from ADROO, ADRl is negative. If
the Link was set and a carry resulted from ADROO,
COOO forces the ADRl to ground. U(l) gates the
status of ADRl into the LAR via the "normal" gating
on drawing KC15, in conjunction with the negation
levels AXS (0), SHIFT, etc.
'*
During fetch IRI(l) in process word 12 detects XCT
in the IR bits to provide a ground REP level, drawing
KC12 (IR4 = 0 at R002-E13M). During defer DEI(1)
resets IR4 and thus also detects an XCT op code for
REP. In either case, REP and CMA 1 (1) at the CM
addressing logic, drawing KC17, gate the IR bits into
the address selectors. CMA 1(1) is present because the
CMA is 24. The IR gating changes the address from
24 to 70 (XCT).
DONE(l) goes to the clock and run logic drawing
KC10(1) for manual key control and KC17 for break
and PI, while CONT(1) allows the generation of a
. third CM STROBE to extract the BGN word (10) from
control memory. The BGN processes set up the MB
The CM STROBE derived from MEM STROBE and
IAO(O) causes the next (third) fetch cyc Ie process word
ADRL
A BUS
LICO)
CML 67MBO,ARO,ACI,LI,
DONE,CONT, CMA 10
9L- 0059
Figure 5-8
TAD Instruction logic
5-16
to be extracted from location 70. The word in 70 contains SM, TI, and CMA33 (XCT entry). SM(l) waits
for the next CLK pulse to start the quasi-fetch cycle
from XCT entry. TI(1) allows XCT * to be used in the
optional extend mode addressing scheme.
For XCT entry, the CM STROBE initiated by SM(1)
and CM CLK extracts the XCT entry word in 33 which
contains IRI and CMA24. The CM STROBE that extracted the XCT entry word restarts the CM timing,
drawing KC16, but the absence of CONT(1) prevents
the extraction of the normally timed second process
word. CM STROBE, however, produces the IN CLR
and CLR pulses in conjunction with MBI(O), EXT (0) ,
and IRI(l). IN CLR produces 1 -+ MBI to set the MBI
flip-flop, drawing KC19(2), and CLR sets SAO on
drawing KC19(3). STROBE 0-7 and 8-17 occur in
core memory to strobe the sense amplifier contents out
to the CP/memory interface. The sense amplifiers
contain the instruction word addressed by the XCT
instruction. SAO(1) and MBI(1) gate the instruction
word to the MB via the B bus, ADR, and 0 bus. IRI (1)
gates the op-code portion into the IR.
From here the instruction is sampled and treated like
any other instructi on in a normal fetch or clefer cyc Ie.
MEM STROBE and IAO(O) on drawing KC16 allow the
generation of the next normally timed CM STROBE,
which extracts the next process word (from location 24)
if not changed by REP.
5.1.6.13 Exclusive OR (XOR) - The XOR instruction
(24) performs the exclusive OR function between the
contents of the addressed memory location and the
contents of the AC on a bit-for-bit basis. If corresponding bits are the same, the AC bit is set to O. If
corresponding bits differ, the AC bit is set to 1. The
previous contents of the AC are lost and the contents
of the addressed memory location and the Link remain
unchanged.
SUB, ARO, AXS, ACI, DONE, CONT, and CMA10
(BGN) .
Figure 5-9 illustrates the XOR logic for one bit position. SUB(l) takes the complement of the MB to the
B bus and ARO(l) takes the direct contents of the AC
to the A bus. Both A bus and B bus contents go to the
ADR. If the output bus levels are both at ground or are
both negative for any bit position, their corresponding
MB and AC inputs differ, and the half-add result out
of the ADR is at ground. In the ADR, CMPL complements the result, forcing the ADR bit output to go
negative. CMPL is derived from AXS(l) of the process
word and IR3(1) on drawing KC13. NOSH gates the
ADR bits to the 0 bus, and ACI(l) gates them into the
AC.
DONE(1) goes to the clock and run logic .drawing
KC10(1) for manual key control and KC17 for break
and PI, while CONT(l) allows the generation of a
third CM STROBE .to extract the BGN process word
from location 10. The BGN word sets up the MB for
the next fetch cyc Ie.
5.1.7 Operate (OPR) Instructions
OPR instructions (op codes 74, 75, 76) need no reference to an operand in core memory and are executed during the computer fetch cyc Ie. These instructions
are used to perform certain operations on the current
contents of the AC and/or Link. The operations to
be performed are encoded in bits 05-17 in the instruction word as described in Section 3.5.1 .1 .
At strobe SA time (see Figure 5-10), the op code is
sampled by IRI(1) of the process word to produce REP,
drawing KC12. REP allows the IR bits to address the
control memory, drawing KC17, for the extraction of
the third process word from location 77 on the third.
CM STROBE.
The fetch cycle places the XOR instruction in the MB,
the op-code portion in the IR, and the contents of
the AC in the AR.
The op code is sampled but does not alter the execute
entry address 30. During execute entry the core memory read-half-cycle places the contents of the addressed memory location in the MB in conjunction with
the execute entry word. The CMA in the execute
entry word is 60 (CMAO, CMAl = 1). CMAO(1) and
CMA 1(1) allow the IR bits to address the control memory, drawing KC17, so that the next process word is
extracted from location 65. Process word 65 contains
5-17
Simultaneously with op code sampling, IRI(l) samples
bits SAOO-02 of the instruction at the LOT (LAW,
OPR, IOn flip-flop, drawing KC12. Since the bits
contain octal code 7, the LOT flip-flop sets.
LOT(l) further samples other bits at the OR MBO, OR
ACI, etc., gates. If IR3-4 are ls, LOT(l) and these
bits indicate a LAW instruction (code 76), producing
OR MBO. Th'is level sets the MBO gate, drawing
KC19(3), on the third CM STROBE (which extracts
process word 77). MBO(l) gates the LAW instruction
from the MB to the B bus, and the instruction goes
AXS __-r~,
1R3
CML 65
SUB, AXS,ARO,ACI,DONE,
CONT CMA 10
Figure 5-9
o
ClK
100
200
300
400
500
600
XOR Instruction Logic
700
800
900
1000
1100
1200
1300
1400
1500
1600
c:::::J
D
STR08E SA
MEM STROBE
MEM WR ITE
CMS
CMS DlYD
!ill
Wl
0
o
0
o
ARI
lRI
AC SIGN
ADR=O SAVE
lOT
OR MBO
ARO RESTORE
OP
MBO
ARO
ACI
LI
SKPI
NOTE: TI M I NG CHART NOT FOR ADJUSTMENT
PURPOSES.
i-.AC SIGN IF ACOlil
1 - . ADR=O SAVE iF AC=O
OR MBO LAW ONLY
ARO RESTORE IF MBOSIO)
9L-0046
Figure 5-10 OPR Timing
5-18
~--------~-~~~~~---~-
into the ADR. NOSH places the ADR contents on the
bus. ACI(l) of process word 77 gates the instruction into the AC. With the LAW instruction, negative
numbers can be loaded into the AC.
The foregoing OPR instruction descriptions serve as a
foundation for the unique instruction particulars that
follow. In most instances, the instruction execution
starts with process word 77.
If IR3 is 1 and IR4-MB05 are Os, LOT(l) and these bits
indicate OPR instructions (code 74) other than LAW,
producing ARO RESTORE. For OPR instructions, ARO
RESTORE sets the ARO gate, drawing KC19(3), on the
third CM STROBE (which extracts process word 77).
ARO(l) gates the data in the AR onto the A bus and
ADR. ACI (1) of process word 77 gates the data from
the 0 bus into the AC, and LI(l) gates the content
of the ADRL into the LAR. During these processes,
other command bits in the OPR instruction operate on
the data word as it passes through the ADR onto the
o bus. The operation on the data word may also
affect the Link content.
5.1.7.1 No Operation (NOP) - The NOP instruction
(740000) is a "do nothing" instruction which delays
the computer program for the duration of one cyc Ie.
At strobe time the NOP instruction is placed in the
MB and the op-code portion in the IR. The op code
is detected to extract process word 77 on the next
CM STROBE. CM STROBE extracts the process word
and sets the OP flip-flop, drawing KC12. Process
word 77 merely recirculates the contents of the AR and
ADRL into the AC and LAR, since OP(l) does not detect any operations to be performed on the contents in
transit (MB05-17 are aliOs at the operate logic,
drawing KC13).
o
If MB05 is 1 at the ARO RESTORE gate, drawing
KC 12, it denotes a C LA i nstructi on (code 75), inhibiting the gate. ACI(l) of process word 77 wi II
transfer Os to the AC from the 0 bus, since nothing
appears on the bus in this case.
At the third CM STROBE, LOT(l), IR3(1), and IR4(0)
also set the OP flip-flop, drawing KC12. OP(l) is
the sampling gate which detects the command bits
(MB06-17) in the OPR instructions, drawing KC13.
Some of these command bits cause one-or two-place
rotation of the contents of the AR and LAR, others are
used for conditional skips in conjunction with SKPI(l)
of process word 77, and sti II others for c leari ng, complementing, or setting the Link in conjunction with
LI(1). Details are given in the instruction descriptions
that follow.
The CM STROBE that extracts process word 77 returns
to the CM timing chain to generate CM STROBE DLYD,
after 80 ns CM STROBE DLYD resets LOT. The
CONT(1) bit in the process word allows the timing
chain to extract a fourth process word. The CMA in
process word 77 is 10, from wh i ch the BG N word is
extracted to enter the new core memory address
(PC" MB) for the next fetch cyc Ie. LI (1) of process
word 77, going to 0 at BGN time, strobes the LAR
status into the Link.
Some OPR instructions may be combined (microcoded)
with others to perform two types of operations within
one instruction period. Care must be taken in programming to avoid microcoding two conflicting operations. The more commonly used combinations of microcoded instructions are described below.
5-19
5.1.7.2 Complement the Accumulator (CMA) - The
CMA instruction (740001) complements each bit of
the AC. The previous contents of the AC are lost and
the Link remains the same. The op code is detected
to extract process word 77 on the next CM STROBE.
CM STROBE extracts the process word and sets the
OP flip-flop, drawing KC12.
OP(1) 1\ MB17(1) generates CMPL, drawing KC13.
ARO(1), derived at CM STROBE time from ARO RESTORE, on drawing KC12, gates the contents of the
AR onto the A bus. The contents of the A bus go
directly into the ADR, and NOSH places them on the
o bus. As the contents pass through the ADR, CMPL
complements all bits individually.
5.1.7.3 Complement The Link (CML) - The CML
instruction (740002) complements tbe Link. The
previous state of the Link is lost. The contents of the
AC remain the same.
The CM STROBE extracts the OPR process word 77 and
sets the OP flip-flop, drawing KC12. OP(l) and
MB16(1) then enable CML to be generated (drawing
KC13). CML, in conjunction with A BUS LINK,
wi II either set or reset the LINK flip-flop.
If LINK is originally in a set condition, then A BUS
LINK is at ground. Two grounds to an exclusive OR
gate cause a grounded ADRL to be applied to the
"normal" gate. The LAR is thus set. LAR(l) and LI(O)
at CMA10 time resets the LINK. LINK(l) is thus
complemented to LINK(O) during this process. By this
same process a LINK(O) can be complemented to
LINK(l) .
ed to TEMP 3(1) B133-B03N.) The state of the ADRL
represents the state of the Link. SH L1 gates the
ADROO bit to the jam input gate of the LAR. LI(l) of
the OPR process word jam transfers the state of ADROO
into the LAR and ACI(l) transfers the shifted contents
of the 0 bus into the AC. On drawing KC13, the
positive IN.SHLl level inhibits the NOSH gate, so
that only SHLl controls the set enable input gating to
the 0 bus. At BG N ti me LI (0) strobes the state of
the LAR into the Link.
5.1.7.4 Inclusive OR the AC/DATA Switches (OAS)The OAS instruction (740004) inclusively ORs the
contents of the AC with the manual settings of the
DATA switches (switch levels DATA SWOO-17) on a
bit-for-bit basis. The results are left in the AC. The
previous contents of the AC are lost and the Link remains the same. If corresponding bits are both Os, the
AC bit is set to O. If corresponding bits differ or are
both ls, the AC bit is set to 1.
5.1 .7.6 Rotate One Position Right (RAR) - The RAR
instruction (740020) rotates the contents of the AC
and the Link one position to the right. The Link
enters ACOO, and AC17 enters the Link.
At strobe time the op code is detected to generate
ARO RESTORE, drawing KC12, and to extract the
OPR process word 77 on the next CM STROBE. The
CM STROBE extracts the process word, sets the OP
flip-flop, drawing KC12, and the ARO flip-flop in
conjunction with ARO RESTORE, drawing KC19(3).
OP(l) 1\ MB 15(1) produces DASO and LIO on drawing
KC13. DASO gates the DATA switch contents onto
the I/o bus (B) via the CP/console interface and the
input mixer, drawing KD7. The data on the I/o bus
(B) is then gated onto the 0 bus by LIO, drawing
KC20. Meanwhile, ARO(l) gates the contents of the
AR onto the A bus, the contents on the A bus go into
the ADR, and NOSH places them on the 0 bus. At
each bit position, the 0 bus will go to ground where
either or both I/o bus (B) and ADR bits are at 1 levels ,
or wi II go negative if both I/o bus (B) and ADR bits
are at 0 levels. ACI (1) of the OPR process word gates
the 0 bus results into the corresponding AC bit positions.
5.1.7.5 Rotate One Position Left (RAl) - The RAL
instruction (740010) rotates the contents of the AC
and the Link one bit position to the left. The Link
enters AC17 and ACOO enters the Link.
At strobe time, the op code is detected to generate
ARO RESTORE, drawing KC12, and to extract the
OPR process word 77 on the next CM STROBE. The
CM STROBE extracts the process word, sets the OP
flip-flop, drawing KC12, and the ARO flip-flop in
conjunction with ARO RESTORE, drawing KC19(3).
OP(l)" MB07(O) " MB14(l) produces SHLl,· drawing
KC13. ARO(1) gates the contents of the AR onto the
A bus. As the contents of the A bus pass into the
ADR directly, SHU gates ADR bits XX onto O-bus
bit positions XX+l, drawing KC20. This includes
END BIT17 onto 0 bus 17 and ADROO into the Link.
END BIT17 is derived from ADRl(B) on drawing KC15.
(When EAE is not used in the system, ADRl is connect-
At strobe time the·op code is detected to generate
ARO RESTORE, drawing KC12, and to extract the OPR
process word 77 on the next CM STROBE. .CM STROBE
extracts the process word, sets the OP flip~nop, drawing KC12, and the ARO flip-flop in conjunction with
ARO RESTORE, drawing KC19(3). OP(l) " MB07(0)
" MB13(1) produces SHR1, drawing KC13. ARO(l)
gates the contents of the AR onto the A bus. As the
contents of the A bus pass into the ADR directly, SHRl
gates ADR bits XX onto 0 bus bit positions XX-l,
drawing KC20. This includes END BITOO onto 0 BUS
00. END BITOO is derived from ADRL (B), drawing
KC15. SHRl also gates ADR17 into the LAR jam input
gate. LI(l) of the OPR process word jam transfers the
state of ADR17 into the LAR. ADR17 represents the
state of AC 17. ACI (1) of the OP R process word transfers the shifted contents of the 0 bus into the AC. On
drawing KC13, the positive IN SHLl level inhibits
NOSH gate, so that only SHRl controls the set enable
input gating to the 0 bus. At BGN time LI(O) strobes
the state of the LAR into the Link.
5.1.7.7 Halt Program (HLT) - The HlT instruction
(740040) stops program execution. The op code is
detected to generate ARO RESTORE, drawing KC12,
and to extract the OPR process word 77 on the next
CM STROBE. CM STROBE extracts the process word,
sets the OP flip-flop, drawing KC12, and the ARO
flip-flop in conjunction with ARO RESTORE, drawing
KC19(3). OP(l) " MB12(l) results in RUN(O) on
drawing KC10. RUN(O) is applied to the collector at
the set side of the RUN flip-flop, pulling it to ground
(reset). Reset RUN inhibits ClK POS pulses, stopping
the program.
5-20
5.1 .7.8 Skip on Minus Accumulator (SMA) - The SMA
instruction (740100) tests the sign (ACOO)of a data word
previously entered in the AC. If the sign is minus
(ACOO == 1) the computer skips the next instruction. If
the sign is plus (ACOO == 0) the computer executes the
next instruction. The contents of the AC and Link
remain unchanged.
During process word 12 the contents of the AC pass
through the ADR, ARI(1) of the process word samples
the ADROO bit at the AC SIGN flip-flop, drawing
KC14. ADROO represents the sign bit, ACOO. If
ADROO == 1J ARI(1) sets the AC SIGN flip-flop.
The op code 74 qualifies REP and allows IR to set up
address 77. MB05(0) gives ARO RESTORE (see Section
5.1.8). CM STROBE extracts the process word, sets
the OP flip-flop, drawing KC12, and the ARO flipflop in conjunction with ARO RESTORE, drawing
KC19(3). AC SIGN(l) AMBll(1), on drawing KC14,
applies a ground level to one of three Bl05 Inverters
connected as a positive NAND gate. The other inverters receive ground OP(l) and MB08(0) levels.
STROBE extracts the process word, sets the OP flipflop, drawing KC12, and the ARO flip-flop in conjunction with ARO RESTORE, drawing KC19(3).
ADR == 0 SAVE(1) A MB10(1), on drawing KC14, applies
a ground Ieve I to one of three B105 inverters connected
as a positive NAND gate. The other inverters receive
ground OP(l) and MB08(0) levels. This places a ground
set level at the input to the SKIP flip-flop. (The flipflop was previously reset by PCI(T) of the fetch entry
process word 21.) SKPI(l) of the OPR process word sets
the flip-flop.
ACI(1) of the OPR process word and ARO(1) recirculate
the contents of the AR to the AC. CONT(1) allows the
next process word to be extracted from control memory
(BGN, address 10). With the SKIP flip-flop set,
PCO(1) of the BGN word produces CIl7, drawing KC14
so that the current address in the PC is incremented by
1 as it passes through the ADR to the 0 bus and MB.
LI (0) rec irculates the content of the LAR into the Li nk .
This places a ground set level at the jam input gate to
the SKIP flip-flop. SKPI(l) of the OPR process word
sets the flip-flop in conjunction with the ground level.
(The flip-flop was previously reset by PCI(l) during the
fetch-entry process word 21.)
ACI (1) of the OPR process word and ARO (1) recirculate the contents of the AR into the AC. CONT(l)
a I lows the next process word to be extracted from
control memory (BGN, address 10). With the SKIP
flip-flop set, PCO(l) of the BGN word produces CIl7,
drawing KC14, so that the current address in the PC is
incremented by 1 as it goes through the ADR to the 0
bus and MB. LI(O) recirculates the content of the LAR
into the Link.
5.1.7.9 Skip on Zero Accumulator (SZA) - The SZA
instruction (740200) tests the value of a data word
previously entered in the AC. If the value in the AC
is 0, the computer skips the next instruction. If the
value is other than 0, the computer executes the next
instruction. The contents of the AC and Link remain
unchanged.
As the contents of the AC pass through the ADR during
process word 12, an output bus on the ADR (ADRA == 0,
ADRB == 0) goes negative if the ADR goes to a II Os. The
negative ADR == 0 levels are applied toOv
I I
I I
a
-v INHIBIT
,
I
LIMITING
RESISTORS
(G630'S)
A37,A381
838,839
------Figure 6-3
MATRIX
SELECTION
G61'-G610)
CD20,CD23
SWITCHES
(G211)
CDI8
H
f
MAI6(1}
L -_ _ _ _ _ _
-301/
-15V
GND
MAO,.",:J
MA151\}
f
MA17ltJ--------"
Mcn-C'-IO
VOLTAGE
REGULATOR
X V DRIVE
OEC~~~NG
~
MAO"O'
MA06(1}
MA01(0)
MA07 (1)
MA0810}
MA0810
MAO!lB(1I
T
RlW
oIOo:~~~~SCTION
MA058{\)
t--
R/W
SOURCE
X-AXIS FLO'
r--'----'-,
Y-AXIS
OIOOESELECTION
MATRIX
MA05A{0}
y
---
CORE
COLUMN
77, DO,
l>
~~~~RY
BUFFER
101917(01
18111(1)
0-
INHIBI
MC71A Core Memory System Block
Diagram
.'W
."
T T
I I
L.Ao,,,"
MAII(1)
1\1.,0(1),
'----MA09C1l
.'W
SOURCE
mation can be that which was placed there as 1s during read, or information placed there from outside the
ven i ence of manufacture, does not, however, affect
the operation of the memory as described above.
Y R/W
SOURCE
Y77 e
COLUMNS
OF
//
CORE§. /
s6~~~E ///
Y00 e. . . .
/'
/~
'*
X R/W
RETURN
X00e
I
X R/W
SOURCE
X00 e
X R/W
RETURN
X 77e
ROWS
OF
CORES
Figure 6-5
X and Y-Axis Selection Scheme for
18 Planes
X R/W
SOURCE
X77e
6.2 DETAILED CIRCUIT ANALYSIS
YR/W
RETURN
Y00e
9L-0065
6.2.1 Memory Control and Timing
Figure 6-4
Core Rowand Core Column Selection
memory. As shown in Figure 6-6, the inhibit windings
are systematically strung through each core in the
plane. Polarity of current in this winding is never
reversed and is oriented toward binary O. The value
of this current is sufficient to offset the current in the
Y line. In this way, the writing of a 1 into core is
inhibited. The inhibit drivers operate during the writehalf-cycle and are controlled by the states of bits in
the memory buffer. A 0 MB bit will permit the drivers
to inhibit the writing of a 1. A 1 MB bit will disable
the drivers allowing the normal write selection current to restore a 1 to that core.
Although this discussion has been based upon the premise that all core planes are stacked one above another, in reality they are placed side-by-side upon
several boards. A set of boards then constitutes a
"stack." This arrangement of planes, for the con-
The memory control circuits are shown in drawing
MC71-0-1. The interrelation of control waveforms
are given in drawing MC71-0-13. In this discussion,
all intermediate delays are approximations, since
they are adjustable to achieve the overall input/output timing precision.
All memory operations are initialized by the generation of a MEM START signal within the memory control (see Figure 6-7). This signal is initiated upon
receipt from the CP of a ClK pulse at the K input of
B05, provided the SM(l) level is present at pin E.
The SM(1) level is also generated in the CP. As
shown in drawing MC71-0-13, this begins at time 0
and ends at +110 ns.
MEM START, a 120 ns pulse, applied to delay line
W301 at AB01, results in MA JAM (A06N), a 50 ns
pulse occurring at +150 ns, which is applied simultaneously to all jam inputs of the MA flip-flops (draw-
6-4
EMA04. SEL wi II be present only if the states of
EMA03 and EMA04 correspond to the states of SW3
and SW4. Table 6-1 shows the switch positions for
extended memory capability.
Table 6-1
W712/ B09 Combinations
MEM BANK
SW3
SW4
0
0
o
0
1
8K-16K
1
0
16K-24K
1
1
24K-32K
-8K
When using 8K memory I these switches (located at
the rear of each memory bank) are both down (00).
Extended memory bits EMA03 and EMA04 are also 00
applying the -3V level (SEL) to the jam input A08K.
Other banks are inhibited by these same bits since
they do not match the setting of SW3 and SW4 on
those banks.
READ(l), a 440-ns wide pulse seen at A08E, is used
to initialize the memory read cycle by gating the
read transistor switches, on drawing MC71-0-10,
thereby completing both the source and return paths
for the X- and Y-read current.
9L- 0070
Figure 6-6
Core Memory Winding Scheme
ing MC71-0-2). The output at A06N is also applied
to pin AD of delay B310 at AB04. At a nominal delay
of 37.5 ns (adjustable by jumpers) the signal is inverted at A05D to produce READ ON used for jamming
at A08. If the SEL level is also present I A08 sets to
produce READ{l) at between +211.5 and +220 ns (assuming a nominal delay of 12 ns per transfer).
The SEL level is a function of memory bank selection
(Field 0 + Field 1). Inverters B104 at B07 and B08
comprise bank selection decoding by sensing coincident combinations of bank selector switches SW3/
SW4 and extended memory addressing bits EMA03 and
READ{l), seen at A08D, is used to condition the
second delay on MEM STARlat A05J to +400 ns.
From here it is further delayed and amplified to produce a basis for the SA STROBE signals (B06D)/
(B06N) which occur at +560 ns; and for the MEM
STROBE (A07V), which occurs at +600 ns. The SA
STRO BEs (O - 8 and 9 - 17) are both fed to the sense
amplifier (drawing MC71 ....0-3) where they gate the
bit amplifier chains. The MEMSTROBE is sent back
to the CP where it is used to grant access to the memory by the CP.
The third delay on MEM START at +635 ns indicates
the end of the read cycle as READ OFF at B03H which
resets the read flip-flop A08 at pin H, and brings up
READ (O).
READ{O) from A08E, which begins at +660 ns, is fed
to pulse amplifier A07F for application to delay line
6-5
AB02. This delay chain establishes the inhibit/write
timing.
(A09N) is used by Field 1 (drawing MC71-0-5) for the
same purpose.
The first tap at +825 ns is inverted to produce INH ON
(A05L) which jams A08 to produce INHIBIT 1 (1) from
pin Nand A09 to produce INHIBIT 2 (1) from pin N
simultaneously at +890 ns. INHIBIT 1 (1) (A08N), a
465 ns-wide pulse, is sent to pins U of the inhibit
drivers for Fi eld 0 (drawing MC71-0-4) as one of the
conditioning levels in its operation. INHIBIT 2 (1)
The second delay tap, at approximately +900 ns, produces WRITE ON (A05N) which jams A08 yielding
WRITE(l) at +920 ns. WRITE(l) (A09D), a 410 nswide pulse, is used to initialize the memory write
cycle by gating the write transistor switches on drawing MC71-0-10, thereby completing both the source
and return paths for the X- and V-write current.
NANOSECONDS
'~
A
(
BASE
PU~SES
,--+
CLK (IN)
0
0
0
-1
MEM START
I
0
0
+
N
0
0
rt>
0
0
+
+
+
0
0
v-
0
0
10
+
0
0
'I
U)
I"-
+
+
0
0
0
0
0
0
CD
0)
+
+
0
0
0
0
+
+
~
8N
0
0
~
+
+
-
I
I
MA JAM
(OUT)
READ ON
READ (1)
(OUT)
I
I
I
I
SA STROBE
0-8 (OUT)
SA STROBE
9-17 (OUT)
MEM STROBE
(OUT)
I
READ OFF
I
INH1 (1)
(OUT)
I
INH2(1)
(OUT)
I
WRITE (1)
(OUT)
I
9L-0071
.)
Figure 6-7
MC71-A Timing Diagram
6-6
The third delay tap, at approximately + 1330 ns, is
the WRITE OFF signal which at B03N resets both the
inhibit and write flip-flops.
flops and outputs are electromagnetic effects on a
string of cores.
Each axis selector contains two G211 decoders and a
diode selection matrix. Selection current (R/W
SOURCE), originating in the X-V drive circuits
(drawing MC71-0-1 0); flows from one decoder,
through its sele<::ted transistor switch to the matrix.
Here it finds its diode path to a selection line (depicted as a coil in the drawings), on which all cores,
in anyone row or column, for all planes in sequence
are strung; and exits through its diode path and selected switch to the R/W RETURN line, The effect
is to apply half magnetizing current to a string of
1152 cores in the X-axes and half magnetizing current to a string of 1152 cores in the V-axes, resulting in one intersected core per plane being magnetized in one of two states.
For the time that this sequence is begun by the generation of MEM START to the cpnclusion of the
WRITE(l) pulse, I/O equipment should not send information to memory. This condition is prevented by a
power clear-key initialize clear (PK ClR) from the
CPo If during this cycle, a printer key is erroneously
pressed, or if the computer is turned on or off; a pulse
is sent to inverter A05S where it will immediately
reset the read, inhibit and write flip-flops (if set)
protecting against loss of stored memory information.
The cycle will reinitiate upon the next ClK pulse
(+1500 ns), if SM(l) is present,
6.2.2 Memory Addressing
The memory address flip-flops are shown in drawing
MC71-0-2. This register functions to convert the
last 13 bits in the MB word (address field) into equivalent binary form for use in memory address selection.
Its inputs are taken from the memory buffer (MB05-17).
Its outputs are sent to the X- and V-address decoding
and selection switches (G211) on drawing MC71-0-6
and MC71-0-7, respectively. The B213 configuration used in this application functions as a jam transfer flip-flop inwhich MA JAM (a -3 Vdc, 50 ns
pulse) is applied. simultaneously to pins T and Jof all
flip-flops against either a ground (1) or -3 Vdc (0)
level at pins U and K, representing the state of each
bit. When these conditions are coincident, the flipflops are either set or reset and -3 Vdc ls and/or Os
are seen at pins Pand E. The two flip-flops MA05A
and MA05B at C12 are configured as buffered drivers
in which MB05(0) applied simultaneously to pins K
and U will yield a -3 Vdc MA05A(0) at pin E~ and
MB05(l) will produce a -3 Vdc MA05B(1) at pin P.
These pulses are used in NAN Ding operations on the
X- and V-selection switches for each field. MA05A
(0) selects Field 0 and MA05B(l) selects Field 1. The
MA JAM bus operates against 150 Otermination at pin
V of the MA 17 flip-flop at D12.
6,2.3 Address Se lecti on
)
As described previously, the address at which a set
of bits is stored is determined by the interaction of
the X- and V-axis address decoding and selection
matrices. The X-axis (Field 0) diagram is shown in
drawing MC71-0-6, and the V-axis (Field 0) in drawing MC71-0-7. Inputs are MAs from the MA flip-
6-7
NOTE
The fact that matrix lines intersect on
any single drawing has no coordinate
significance. layout of components
was dictated by drafting convenience.
Each G211 decoder contains eight 4-input logic
NAND gate inverters which control the base bias on
eight transistor switches. Each switch in turn completes a diode path between selection current source
or return and one end of a specific select line (see
Figure 6-8). Current in a read direction will flow
from R/W SOURCE through Dl, Ql, and D2; and
from there through the select line, and return through
D3, Q2, and D4. Current in a write direction will
flow from R/W RETURN through D5, Q2, D6, the
select line, D7, Ql, and D8. As can be seen from
the schematic, current cannot flow unless both Ql
and Q2 are turned on; a condition enabled by coincidence of two sets of MAs at the inputs of both
gates. Negative clamp for operation of all gates is
taken from -V DRIVE originating at drive resistors
G630(B38) for the X-axis, and at G630(B39) for the
V-axis (drawing MC71-0-10). Distribution of MA
binary states across the gates is such to produce selection of anyone of 64 lines in both axes. An additional condition is made coincident with all gates
in the same field. This is the two MA forms of MB05,
used to switch to Field 1 in extended memory operation. Field 0 utilizes the negative level form of
MA05A(0), while Field 1 is enabled by the negative
level form of MA05B(1). This latter condition is the
lifier chain operates into a termination of 150 n at
pin T. Pins K, Nand S receive closely adjusted reference voltages from the master slice control G008
at A 11 for use by the sense amp clamping and comparator stages.
only difference in operation between Field 0, just
discussed, and Field 1 as shown in drawing MC71-08 for X-axis selection, and MC71-0-9 for Y-axis
selection.
For purposes of address decoding, the X-axis gates
use both binary conditions of MA06 through MAll,
while the Y-axis gates use both conditions of MA12
through MA 17. Because all gates are NAND inverters, the -3 Vdc form of both ls and Os is used for coincidence.
The slice voltage (-4.1 Vdc reference +10 Vdc) from
All H, the second-stage clamp voltage (+6 Vdc reference -15 Vdc) at All N, and the fixed first-stage
clamp voltage at AllM are used for pulse forming,
1
01
07
05
03
_s~~w-
R/W
SOURCE
02
06
L -_ _ _ _~------~--~
04
08
9L-0067
Figure 6-8
Address Selection, .Simplified Schematic
6.2.4 Bit Sensing During Read
level referencing, and noise suppression in the sense
amplifiers.
The sense and pulse amplifiers are shown in drawing
MC71-0-3. These circuits function during the readhalf-cycle to repeat into the memory buffer all ls
sensed during the core read transition. Inputs are by
cables W990 (A31 and B31) from Field 0, and W990
(A2l and B2l) from Field 1. Sensed pulses enter their
respective dual-input sense amplifiers G014 at pins
J and H from Field 0, and F and E from Field 1. Input switching is supplied by positive levels applied
to either pins M (for JH input) or L (for FE input), one
of which is always present from sense amplifier selectors G010{A12) ,and (B12).
The voltage from All M is used as a preset reference
level against which the amplified signal, sensed by
core transition, is compared. This level is set to
reject all amplified noise generated in those bit planes
in which transitions did not occur, and transmit to
the PAs only valid ls.
The voltage from All N is used as a reference level
for the second differential amplifier stage within each
G014, the output of which is compared with the
master slice voltage from AllH at an internal rectifying slicer. If the signal voltage fed to the slicer
exceeds the master slice voltage, the output gate is
enabled producing a "slice window." This window
then is sampled at the output gate by the SA STROBE
at a time when the ratio of read 1 to read 0 is maximum.
When sensing the basic 4K stack (field 0), positive
level MA05A{O) is fed to GOl O{A 12) at pins F and R.
The G010s function as bus drivers to apply a positive
select level from pins D and N to pins M of all bit
sense amplifiers allowing only Field 0 inputs to be
available for amplification. When in extended memory mode MA05B(1) is fed to the G010 at B12, selecting Field 1 inputs at F and E. The SA STROBEs
0-8 and 9-17, occurring simultaneously at +560 ns,
turn on all amplifiers for 60 ns allowing any bit ls to
be fed from pins Vas positive pulses to their respective W612 pulse amplifers at pin F. Each sense amp-
The output positive pulse from G014{V) is applied to
pin F of its associated W612 pulse amplifier. Here it
is inverted, standardized (312 ns), and fed out via
pin L to the memory buffer through the CP/Memory
Interface (drawing MC71-0-11).
6-8
6.2.S Voltage Regulation and Selection Drive
The voltage regulator and X-V drive circuit is shown
in drawing MC71-0-10. A simplified schematic is
shown in Figure 6-9. All power required for operation
of the core memory system comes from the + 10, - lS
Vdc and the -30 Vdc supply (Section 7.3. 2). The
+10 and -lS Vdc outputs are used for transistor logic
power and the -30 Vdc supply is used for stack drive
current,
In the core memory system, a G804 control module
regulates the -30 Vdc supply and prevents operation
of the CP if any supply exceeds the limits defined in
the overall system specification. The G80S modules
deliver positive drive (-7 Vdc) and negative drive
(-30 Vdc) to the selector switches G211. The selected switch pair connects the voltage across the appropriate core drive line, and the voltage differential
creates the current through the line.
+ V DRIVE through the +X DRIVE RES, and Ql to the
R/W SOURCE bus. Arrows indicate the direction of
read current through the X-selection line (load) to
the X R/W RETURN. Drive then flows through enabled
Q2, the -X DRIVE RES to the - V DRIVE terminal of
regulator G804. During WRITE(l}, Q1 and'Q2 are
cut off and drive flows through Q3, the load (in reverse direction) and Q4. The +X and -Y drive resistors limit drive current to 340 mA during both read
and write.
The Control Module G804 at DC04 accepts the common + V (-7 Vdc) and - V (-30 Vdc) outputs from
negative regulator modules G80S-CD01 and CD03.
Zener diode D21 establishes the reference level for
differential amplifiers Q6 - Q8 and the voltage adjustment rheostat R12. The differential amplifier
output at the collector of Q8 controls the current
through transistors Q7 and Q9, whose emitter circuit
delivers the control current to the series regulator in
G80S via terminals CK,CL.
Figure 6-9 is a simplified schematic diagram of the
voltage regulator and X-V drive, drawing MC71-0-10.
Although only the X-axis components are show, the
Y-axis selection process is identical. During READ(l},
Q3 and Q4 are cut off while transistor switches Q 1
and Q2 are turned on, allowing drive to flow from
The thermistor input at the differential amplifiers provides output voltage compensation as a function of
core stack temperature. The thermistor is located
within the core stack. As the core stack temperature
rises, the thermistor resistance increases, and the dif-
READ(1)----------------------~------------------------------_,
+x
DRIVE
RES.
tV DR IVE
-7V
R/W
SOU RCE-+o------,
+10V
GND
-15V
REGULATOR
GB04
-30V
-30V
-V DRIVE
-x
WRITE (1)
DRIVE
RES.
---------------------+----------------------------------'
NOTE: REFERENCE DESIGNATIONS
ARE NOT ACTUAL,
9L-0076
Figure 6-9 X-Axis R/W Drive Selection Simplified
Schematic
6-9
ferential amplifiers cause the output voltage of the
negative regulator modules to decrease.
side of the + Y and - Y drive resistors are decoupled
to ground, while the + X and - X drive resistors are
returned to the opposite regulator terminal.
Other sensing circuits in the control module supply a
POWER OK signal to the CP whenever the transistor
logic voltage and the negative regulator voltages are
correct, The POWER OK remains negative as long as
the voltages remain within 3Y of their designated
values. If not, the level goes to ground preventing
the occurrence of spurious memory cycles and consequent disruption of stored information, particularly
during initial power turn-on.
6.2.6 Inhibiting During Write
On the module schematic, transistor Q10 goes into
conduction if +Y becomes less negative than -3 Ydc,
as governed by the 3Y reference levels set up in diode
packages E3/E4. Q 10 turns on Q 11, whi ch places
CY at ground, Likewise, transistor Q1 conducts if
the -15 and +10 Ydc supply voltages are outside the
specified limits. This causes the DR level to go to
ground. CYand DR are tied together as POWER OK
which goes to the clock and run logic via the CPj
memory interface.
NOTE
The tab terminal is ground return for
the memory voltage relay K2 on drawing 712-0-1.
In the negative regulator G805, series regulator Q1
accepts the control current from the differential amplifiers in the control module G804, Conduction in
Q1 places a proportionate voltage drop across resistor
R2. The nominal drop across R2 is 23 Ydc, so that
the lower end is at -7 Ydc and the higher end sees
the full -30 Ydc supply voltage~ The five 20 flF
capacitors filter the output ripple to less than 50 mY.
The discharge time of filter capacitors in the computer
supplies allows 10 ms of memory operation following
power interruption. Maximum output current of the
G805 is 4A. The outputs go to the drive resistor
boards G630 and the address selectors,
Four resistor boards G630 are connected between the
negative regulator outputs and the source selection
switches G219. Each resistor has a parallel peaking
capacitor which offsets the inductance of the line and
thus presents a better current rise time. The common
6-10
The negative regulator module G805 also supplies -7
and -30 Ydc voltages to the inhibit drivers shown in
drawing MC71-0-4 for Field 0 and MC71-0-5 for
Field 1. These circuits are identical except for the
source of certain control signals. For the purposes of
this discussion only Field 0 will be considered. Specific differences will be described at the end of the
discussion
0
The function of the inhibit drivers is to prevent the
writing of a 1 in a selected core by generating a
field in opposition to the field in any Y-select line.
In this way, the coincidence of current is prevented
and the selected core is left in the 0 state. To accomplish this, the MB is conditioned to disable any
bit-plane driver in which a 1 has been sensed during
read, thereby allowing the X-V drive current coincidence to rewrite the 1 in core. Conversely, if a 0
had been sensed, the MB would not disable the inhibit
driver, coincidence would be inhibited, and the core
would remain in the 0 state.
Inputs are taken from the memory buffer (MBOO-17),
the memory address register (MA05A or MA05B), and
from the X-V driver circuit (+ and - Y INH, INH 1
and INH 2). Outputs are by cable to the core stack.
The circuit comprises nine G218 modules at locations
A33 - A36 and B33 - B36. Current limiting resistors
for each half module are contained on G630 resistor
boards connected between either pins E and J or M
and R of each module. These 56 Q resistors limit the
inhibit current to 310 mA, sufficient to offset the Yaxis drive current during write.
When the particular MB bit is a 0 coincidentally with
the correct MA05 bit, an inhibit current will flow
from pin F or R through the bit-plane inhibit winding
to pin H or P for the duration of the IN H 1 (1) signal.
Should any MB bit be a 1, no output will be seen.
The operation of the inhibit drivers for Field 1 (drawing MC71-0-4) is identical except the memory address
bit required is MA05B(1) from B213jC12(N), and the
timing pulse is INH 2(1) from B213jA09(N).
CHAPTER 7
CONSOLE POWER CONTROLS
7.1 MANUAL CONTROLS
amplifier, conditioned by B(l). IND ClK produces
CM STROBE B as before, but now the CM STROBE B.
wi II set the PCO, ACO, ARO, or MQO flip-flop if
any of these has been selected by the REGISTER DISPLAY switch. The IND EN level is sti II present by
virtue of A(O) A B(l); IND EN applies PCO, ACO,
ARO, or MQO to the appropriate jam-input gate if
the respective register is selected at the REGISTER
DISPLAY switch, drawing CS-5408018.
The logic sequence to implement functions selected
on the PDP-9/l console is described in this chapter.
Timing diagrams for the console key functions, the
clock/run diagram (KC10), and key flow diagram
(KC6) supplement the text and should be referred to
while using this chapter. The marginal check (MC)
panel and maintenance check panel controls are
described in the maintenance section of the manual,
Chapter 10.
7.1.1 Power Turn-On
When the console POWER switch is turned ON, PWR
OK from the power supplies and/or the ground from
low-Voltage Detector W505 reset the RUN and REPT
flip-flops, and enables the application of PWR ClR
POS pulses from the main clock to the computer system. RUN(O) enables the REPT ClK. In addition to
initializing certain flip-flops throughout the computer
system, the PWR ClR POS pulses (KC10) generate
IND ClK and PK ClR pulses at pulse amplifiers S602J25K and W612-H32N. These in turn generate CM
STROBE A, C, D on drawing KC16. CM STROBE
clears all CM sense flip-flops, drawing KC19, because
CM CURRENT is absent.
When the 712 Power Supply is stablized, the PWRClR
POS, IND ClK, and PK ClR pulses are removed. The
next REPT ClK pulse sets flip-flop C in conjunction
with RUN(O), drawing KC10. Thereafter, flip-flop
C alternately resets and sets on the leading edge of
each REPT ClK pulse. The REPT ClK pulses remain
until the RUN flip-flop sets. These are 100-ns pulses
which occur at manually selected intervals of 2 !-Is to
1s. The five-position REPT switch on the console
selects this REPT ClK frequency.
The selected switch position thus sets the appropriate
sense flip-flop on CM STROBE B. The flip-flop in the
set state gates the contents of the selected register onto the A bus. The contents on the A bus go directly to
the ADR. 10 BUS ON(1) gates the contents from the
ADR to the I/O bus, drawing KC21 to I/O bus (B) via
the input mixer, drawing KD7, then via the CP/IO
and 10/console interfaces, drawings KC25, KD4,
and KD6 to the REGISTER indicators, drawing CS5408020.
Flip-flops C and B recycle on the REPT ClK pulses,
and the computer remains in this no operation state
unti I a console key is operated to allow flip-flop A
to set. Once flip-flop A becomes set with REPT(l),
IND EN is removed, and the REGISTER DISPLAY
circuits are thus disabled. REPT(1) is generated by
KEY DlY from DELAY flip-flop. This is true for the
operation of any console key; therefore, the register
display is meaningful only during the interval between computer no operation state and the setting of
A (and RUN) on a key operation.
7.1.2 START Key
The START key and the ADDRESS switches (3-17) on
the console operate together to start execution of a
program that has been stored in core memory. Drawing KC11 is the START timing. The operator first loads
the program's starting address in binary format into the
ADDRESS switches (switches up for binary 1s). When
he depresses the START key, the key supplies a ground
KST level to the NOR gate at R111-J33UV, drawing
KC10(1), via the CP/console interface. This level
becomes the negative KEY BUS and !,ositive KEY
BUS(B) levels. KEY BUS(B) removes KEY BUS(B) from
inverter S 107-H34F, thereby removing the collector
ground from the assertion output of the REPT flip-flop.
Upon each reset of flip-flop C, flip-flop B sets and
resets in a divide-by-two counter mode. When Bsets
for the first time, the B(l) A A(O) condition generates
IND EN at R111-J26PN. IND EN goes to the wiper
arm of the console REGISTER DISPLAY switch, drawing CS-5408018 to enable the selection of computer
registers for display at the REGISTER indicator. IND
EN also sets the 10 BUS ON flip-flop, drawing
KC 19(3). C sets on the next REPT C lK pu lse. C (1)
strobes a DCD input gate to the IND ClK pulse
7-1
the address from the 0 bus into the PC. Likewise,
MBI(l) gates the same address from the 0 bus into the
MB.
KEY BUS(B) also triggers the 50-ms delay at R320":'
J32V. The negative output recovers after 50 ms to
trigger another delay at R302-J32M, which produces
a 50-fJS negative KEY DlY.
The 50-ms delay period allows sufficient time for
settling of switch contact bounce and the 50-fJS KEY
DlY allows for execution of the longest instruction if
the START KEY (or any other key) was operated during
a running program. (In a running program the RUN
flip-flop is in the set state; an instruction DONE(l)
level issued in a control memory process word at some
point during the 50-flS KEY D lY resets RUN via
NAND gate Rl11-J28N. Resetting RU N disables
the application of ClK POS and CM ClK pulses to the
computer system, stopping all operations.)
The KEY D lY recovery sets the REPT flip-flop conditioned by KRI (READ IN key inactive). REPT(1)
conditions the DCD set gate of flip-flop A, which sets
on the next reset of B. The l,1ext REPT ClK pulse sets
C, which then strobes the IND ClK gate conditioned
by A(l). IND ClK now strobes the KEY INIT POS
gate which is conditioned by A(l) A KCT. The KCT
level is derived from the active CONTINUE key. KEY
INIT POS starts the CM timing chain, generates CM
CURRENT and CM STROBE, drawing KC16, and
generates PK ClR, drawing KC 1O.
CM CURRENT enables the CM address selectors, drawing KC17, to decode the address in the CMA register.
KEY INIT POS and PK ClR act together to clear the
MCA flip-flops, drawing KC19(l), for an address of
00. However, the KST level derived from the START
key produces levels KIOA3, KIOA4 on drawing KC10.
On drawing KC17, the cleared CMA levels CMAO(O),
CMA 1(0), and CMA2 (0) gate KIOA3, KIOA4 into the
address selectors, changing the address from 00 to 06.
At CM STROBE ti me, process word 06 is extracted from
control memory. This word contains ADSO, MBI, PCI,
SM, and CMA21. ADSO(1) goes to the input mixer on
drawing KD7(l) where it is NANDed with AUTO RESTART. This level comes from the optional Power
Failure Detection KP09A to denote that no automatic
restart is in progress. If the option is not installed,
the input to the NAND gate is disconnected, and is
therefore of no consequence. ADSO(l) produces
ADSO(G), which gates the ADDRESS switch levels
ADDR SW03-17 into the R141 mixer modules. The
outputs are buffered at I/o bus (B).
At the same time ADSO(1) generates LIO in bus driver
B213-D12, drawing KC13. LIO (load I/O) gates the
address onto the 0 bus, drawing KC20. PCI(1)gates
The next REPT ClK pulse resets C. As C resets, it
sets the RUN flip-flop in conjunction with the A(1)
condition at the input DCD gate. RUN(l) disables
the REPT ClK, resets and holds A and B in the 0 state.
The next ClK, ANDed with RUN(l) sets SEN. With
SEN(1), the following ClK RUN generates ClK POS.
ClK POS pulses are further inverted at pulse amplifiers
B602-H33N and W612-E02 for negative CM ClK and
ClK ClKD pulses, respectively. The ClK pulse starts
the core memory cyc Ie and the CM ClK pulse starts the
control memory timing in conjunction with SM(l) of
the process word 06.
The processor is now in the state in which it would be
at the end of an instruction execute cycle during a.
running program. The address in the CMA register is
21 (fetch entry), RUN is set, and the MB contains the
address of the next instruction to be fetched from core
memory. MA JAM in core memory places the address
in the MA 120 ns from ClK. The CM timing starts to
extract process word 21, and the machine thus starts
execution of the program.
ClK . RUN also set the SEN flip-flop on drawing KC10.
SEN(1) monitors the states of PCO and ARO at the
PCOS and AROS flip-flops throughout the running program. These flip-flops thus continuously reflect the
PCO and ARO states.
7.1.3 PROGRAM STOP Key
The spring-loaded down position of the PROGRAM
STOP key halts computer operations upon completion
of the current instruction. It performs the same functions as the SING INST switch.
KSP (key stop) from the PROGRAM STOP key or SW
SGl INST from the SING INST switch applies one
enabling input to gate Rl11-J28U, drawing KC10.
The other three inputs to the gate determine when the
computer can be stopped. In order to stop, the console
must be unlocked, the computer must not be operating
in a program break segment (BKO, BKl states from
F35N), and the instruction currently being executed
must finish (DONE(1) from the last CM process word
in the computer execute cycle). When all these
conditions have been met, the RUN flip-flop is
collector-pulled to the 0 state by Rll1-J28U .
RUN(O) enables the REPT ClK, and the REPT ClK
pulses start stepping flip-flops C and B. The. first REPT
7-2
CLK pulse sets Ci the next pulse resets SEN in conjunction with C(1), drawing KC10. Reset SEN removes
the jam input level to the PCOS and AROS flip-flops.
PCOS and AROS now reflect and retain the states of
PCO and ARO at the time the computer stops. PCO
and ARO are both cleared by CM STROBE Band CM
CURRENT produced from IND CLK on the next REPT
CLK pulse.
7.1.4 CONTINUE Key
The spring-loaded down position of the CONTINUE
key is used to resume the execution of a program after
a programmed HLT or after a manual program stop
condition. The KCT level produces KEY BUS, KEY
BUS (B), and KEY D LY in the same manner as the
START key. KEY DLY upon recovery sets the REPT
flip-flop.
7.1.S DEPOSIT THIS
The upper, spring-loaded DEPOSIT THIS position of
the DEPOSIT THIS/DEPOSIT NEXT key is used to store
a word in core memory. The operator first loads the
address of the intended core memory location into the
ADDRESS switches and the word itself into the DATA
switches. When he raises the DEPOSIT THIS/DEPOSIT
NEXT key, the address is gated into the MB and the AR
by successive control memory process words. A core
memory cyc Ie takes p lace as the address is jammed
into the MA. However, at STROBE 0-8,9-17 time in
the read-half-cyc Ie, the contents of the addressed
memory location are kept out of the MB by the absence
of the SAO bit. Instead, the word in the DATA switches is gated into the MB so that the write-half-cycle
replaces the original contents of the addressed location
with this DATA switch word. The original contents
are lost.
The DEPOSIT THIS function normally starts from a
computer stop condition. Figure 7-1 shows the timing
for setting up a DEPOSIT THIS, DEPOSIT NEXT,
EXAMINE THIS, or EXAMINE NEXT operation; all
require the same set-up conditions. KDP on drawing
KC10 sets the REPT flip-flop after the SO-fls KEY DLY
as for program START. The REPT ClK pulses step the
A, B, and C flip-flops, and KEY INIT POS occurs
on the A (1) 1\ IND CLK condition. KEY INIT POS
generates PK ClR, drawing KC10, and starts the CM
timing, drawing KC16. PK ClR and KEY INIT POS
act together to c lear the CMA flip-flops, drawing
KC19(1), for a CM address of 00. However, the
KDP level derived from the DEPOSIT THIS key produces
level KIOAS on drawing KC1 O. CMAO(O) , CMA 1 (0),
and CMA2(O) on drawing KC17 allow the KIOAS level
to change the address to 01. At CM STROBE time,
then, the process word 01 is extracted from control
memory.
While the computer is stopped, REPT CLK pulses are
stepping flip-flops C and B. REPT(l) now allows A to
set, conditioning the set DCD gate of the RUN flipflop. On drawing KC10, if PCOS is set, A(1) A B(O)
1\ KCT(B) at Rll1-H30HJ produces PCO RESTORE
which sets the PCO sense flip-flop, drawing KC19(3).
A similar logical flow also applies to AROS and ARO
RESTORE.
This logic is necessary in order to restore the PCO and
ARO flip-flops, since they are cleared by IND CLK
pulses when the computer is stopped. (Clearing them
enables the use of the REGISTER DISPLAY switch.)
PC OS wi II be set whenever the machine has been
stopped during execution of a program, and AROS
wi II be set whenever the mach ine is stopped at the end
of a hardware read-i n operation.
Process 01 contains ADSO, MBI, SM, and CMA2S.
ADSO(l) produces ADSO(G) to gate the ADDRESS
switch levels ADDR SW03-17 into the input mixer,
drawing KD7, via the CP/console interfac;e. The
gates place the address on the buffered I/o bus.
ADSO(l) also generates the LIO level, drawing
KC13, in bus drivers B213-D12. LIO gates the address
onto the 0 bus, drawing KC20. MBI(1) jams the
address into the MB.
The next REPT CLK pulse resets C and the transition
sets RUN via the DCD gate conditioned by A(1) •
RUN(l) clears A and B and inhibits the REPT CLK.
The next CLK, ANDed with RUN(1) sets SEN. With
SEN(l), the following CLK RUN generates CLK POS.
The first CLK POS pulse resets REPT if the REPT switch
on the console is off (down) and also starts the main
memory and control memory, since SM(l) is present in
the last eM process word. The CMA register at this
time contains address 21, causing control memory to
extract this fetch entry process word for a normal computer fetch cycle. Note that if the operator had activated 10 RESET key, SM and address 21 would not be
present and improper action of CONT would result.
The computer now waits for flip-flops A, B, and C to
step through 0, setting the RUN flip-flop. RUN(l)
disables the REPT CLKi the CLK POS (CLK and CM
ClK) pulse after RUN(l) starts the core memory cycle
and the CM timing chain in conjunction with SM(l),
7-3
IN CLR in the CM timing, drawing KC16, as the timing progresses toward CM STROBE. IN CLR produces
1 .. MBI, setting the MBI flip-flop, drawing KC19(2).
Note that KEY 1\ (KDP+KDN) on drawing KC13 goes
to the jam input of SAO, drawing KC19(3). This
level keeps SAO in the reset state on the CLR pulse.
resets RUN in conjunction with KIOA5, and resets
the REPT flip-flop. The address in the MB gets jammed into the MA at the start of the core memory cyc Ie.
The process word read out of control memory location
25 contains MBO, ARI, KEY, and CMA26. MBO(l)
gates the contents of the MB (address) onto the B bus I
the contents go directly through the ADR, and NOSH
places them on the 0 bus. ARI(1) then. gates the
contents into the AR. For DEPOSIT THIS, the address
does not get past the AR (see DEPOSIT NEXT).
DASO gates the DATA switch levels DATA SWaO-l7
into the input mixer gates, drawing KD7, via the
CP/console interface. The input mixer gates place
the data word on I/o bus (B).
STROBE 0-8, 9-17 occurs in core memory to read out
the word at the address specified by the MA. However,
this word is inhibited by the absence of SAO(l) and is
therefore lost. MEM STROBE starts another CM cyc Ie,
drawing KC16.
The KEY 1\ (KDP+KDN) level on drawing KC19(3),
also generates KDP+KDN+RI. The KDP+KDN+RI level
produces LIO on drawing KC13 in conjunctioh with
MBI(l). LIO places the data word on the 0 bus from
I/o bus (B). MBI (1) jams the word into the MB.
KEY(1) is NANDed with a KDP+KDN level on drawing KC13 to produce DASO. KEY(1) also generates
The core memory write-half-cycle stores the data word
at the preselected address. The CM STROBE produced
-1
REPT elK
r--
REPEAT SPEED (2ps - heel
I I I I I
RUN
A
KDP V KEX
KON V KEN
OlY
KEY OlY
I
REPT
KEY INIT POS
CM STROBE
CM01V
CM03
I
I
LJ
ClK
25
26
0
ClK
I
I
25
100
200
300
400
500
600
700
800 ns
l
~------------------------~~
L
26
9L-Q061
Figure 7-1
Initial Set-Up DEPOSIT or EXAMINE
Timing
7-4
by MEM STROBE extracts process word 26 from control
memory. Process word 26 contains PCO, SM, and
CMA21. Since RUN was reset by KIOA5 and the ClK
POS pulse, the computer stops and the control memory
retains process word 26 in its sense flip-flops until the
computer is made to proceed from CONTINUE,START,
DEPOSIT NEXT, or EXAMINE THIS. From CONTINUE
THIS, process word 26 accomplishes the operations performed by the BGN word at the end of an instruction.
That is, it obtains the next address from the PC for
the start of the next fetch cycle. For START, DEPOSIT NEXT, and EXAMINE THIS, the address from
the PC does not reach the MB and the CM address (21,
fetch entry) changes appropriately.
7.1.6 DEPOSIT NEXT
)
Having deposited a single word in core memory with
the DEPOSIT THIS position of the DEPOSIT THIS/
DEPOSIT NEXT key, the operator may use the DEPOSIT NEXT position to store a series of words in consecutive locations. For eac,h depression tq DEPOSIT
NEXT, the current address in the AR is incremented by
I, then placed in the MB for the start of the I')ext core
memory cycle. ADDRESS switch entries after the
initial DEPOSIT THIS function are unnecessary and
are in fact inhibited. The DATA switches must be used
to enter the new data word before each depression to
DEPOSIT NEXT.
the ADDRESS switches. When the key is raised, the
address is gated into both the MB and the AR. The
core memory cycle fetches the word and" places it in
the MB in conjunction with the control memory processes. The address remains in the AR, so that it can
be displayed in the REGISTER indicator by turning the
REGISTER DISPLAY switch to the AR position.
The EXAMINE THIS function is normally started from
a computer stop condition, e.g., following a DEPOSIT
THIS/DEPOSIT NEXT operation. On drawing KC10
and in Figure 7-1, KEX produces the same set-up
conditions as KDP to take the initial process word from
location 01. Process word 01 places the address in the
MB, and the succeeding process word (25) places it in
the AR for an EXAMINE NEXT operation.
IN ClR and ClR from the CM timing, drawing KC16,
set the MBI and SAO flip-flops during the core memory
read-half-cycle to gate the word from the sense amplifiers to the MB. IN ClR and ClR are derived from the
KEY(1) bit of process word 25 as for DEPOSIT THIS.
The computer stops until made to proceed from CONTINUE THIS, START, or EXAMINE NEXT. It is in
this stop condition that the MEMORY BUFFER indicator
and the AR selection of the REGISTER indicator can be
observed.
7.1.8 EXAMINE NEXT
On drawing KCI0 and in Figure 7-1, KDN produces
the same set-up conditions as KDP, but noW the levels
KIOA4 and KIOA5 are gated on. Thus the first process
word is taken from location 03. Process word 03 contains ARO, + I, MBI, SM, and CMA25. ARO(l) gates
the current address in the AR onto the A bus, and the
A bus contents enter the ADR. Process +1(1) produces
CIl7, drawing KC14, to initiate a carry through the
ADR. NOSH takes the incremented address of the
ADR to the 0 bus, and MBIO) places it in the MB.
Having examined a single word in core memory with
the EXAMINE THIS position of the EXAMINE THIS/
EXAMINE NEXT key, the operator may use the EXAMINE NEXT position to examine a series of consecutively stored words. For each depression to
EXAMINE NEXT, the current address in the AR is
incremented by I, then placed in the MB for the start
of the core memory cyc Ie. ADDRESS switch entries
after the initial EXAMINE TI'$IS function are unnecessary and are in fact inhibited.
The new address is thus ready in the MB for the core
memory cycle that starts with the ClK POS pulse.
Process word 25 stores the address in the AR as for
DEPOSIT THIS. The entire process repeats for each
depression to DEPOSIT NEXT.
On drawing KC10 and in Figure 7-1, KEN performs
the same set-up functions as KEX, but now the levels
KIOA4 and KIOA5 are gated on. Thus the first process word is taken from location 03. Process word 03
contains ARO, +1, MBI, SM, and CMA25. ARO(1)
places the current address in the AR on the A bus,
and the A bus contents enter the ADR. Process +1 (1)
producesCI17, drawing KC14, to initiate a carry
through the ADR. NOSH takes the incremented
address of the ADR to the 0 bus, and MBI(1) places
it in the MB.
7.1.7 EXAMINE THIS
The upper spring-loaded EXAMINE THIS position of the
EXAMINE THIS/EXAMINE NEXT key transfers a single
word from core memory to the MB for display at the
MEMORY BUFFER indicator on the console. The
address of the word to be examined is first loaded into
7-5
The new address is thus ready in the MB for the core
memory cycle that starts with the ClK POS pulse.
Process word 25 stores the address in the AR as for
EXAMINE THIS. IN ClR and ClR derived from the
KEY(1) bit of process word 25 set MBI and SAO during
the core memory read-half-cycle to gate the word
from core memory's sense amplifiers to the MB. The
entire process repeats for each depression to EXAMINE
NEXT.
7.1. 9 READ IN Key
The READ IN key stores 18-bit binary words from
punched paper tape in consecutive core memory locations. The operator first loads the address of the first
word to be stored into the ADDRESS switches. When
he depresses the READ IN key, the CP selects the
paper tape reader for binary mode operation, then
waits for the reader to read three lines of tape. The
reader control logic in the I/o control section of the
computer assembles these lines in a reader buffer (RB),
drawing KD9(2). In the binary mode tape format for
READ IN operations, tape channels 1 through 6 of
each line contain one 6-bit character of an 18-bit
word; channel 7 is punched only in the last line of the
last word to be read, and channel 8 is punched in
every line to control the gating of the 6-bit characters
into the proper RB bit positions. When the RB is full,
its contents are transferred to the MB and then are
deposited in core memory. The current address of the
core memory location is retained in the AR where it is
incremented by 1 to store successive words in consecutive memory locations. The process continues unti I the
reader encounters a line of tape in which channel 7 is
punched indicating that this is the last line of the last
word. The reader then stops and the CP executes the
instruction encoded in the last word. This last word
is usually a JMP instruction to the starting address of
the program just loaded, or a HlT instruction to afford
manual control of the start of the program.
The READ IN function normally starts from a computer
stop condition, where flip-flops C and B, on drawing
KCI0(1), are cycling on the REPT ClK pulses (Figure
7-2). When the operator depresses the READ IN key,
the KRI ground obtained from the key initiates KEY
DlYas for all other key functions. For other keys,
the trailing edge of KEY DlY sets the REPT flip-flop.
REPT(1) would then permit the initial setting of flipflop A, ultimately resulting in KEY INIT POS and in
the setting of the RUN flip-flop. For READ IN operations, however, KRI at ground prevents KEY DlY from
setting REPT so that the reader can have time to read
three lines of tape into the RB. For this reason, the
reader control logic determines when three lines of
tape have been read and when flip-flop A shall set,
as follows.
KRI and KEY DlY go to the read-in mode control,
drawing KD8, via the CP-l/O interface. Both signals
are applied to the DCD set gate of the READ IN 1
flip-flop. KRI conditions the gate and the positivegoing trailing edge of KEY DlY strobes the gate to
set the flip-flop.
READ IN 1(1) generates RSB (reader select binary)
at pulse amplifier S602-F04K, and is also inverted at
S107-H05D for a negative RIl (1)B level. RSB goes to
the reader control, drawing KD9(1), where it resets
the RDR ALPHA flip-flop and generates an IOTOI04
command at pulse amplifier S603-DI0T. The IOTOI04
command clears the RB, RDR 1, RDR 2, and RDR FlG
flip-flops, and sets RDR RUN, thereby starting the
tape reader mechanism. RDR COUNT pulses, timed
with the appearance of the tape channel 8 holes, step
the RDR 1 and RDR 2 flip-flops; the first RDR COUNT
sets flip-flop RDR 1. RDR 1(1) strobes the first line
of tape into the reader buffer, RBOO-05. The second
RDR COUNT sets RDR 2. RDR 2(1) strobes the second
line of tape into RB06-11. The third RDR COUNT sets
the RDR FlG, conditioned by RDR 2(1). RDR FlG (1)
strobes the third line into RB12-17, and resets RDR
RUN, to stop the reader.
RDR FlG (1) is buffered at S 107-E06N, drawing KD9,
for a negative RDR FtG (1)B level. RDR FlG (l)B and
RIl(l)B generate RD START RQ on drawing KCI0(1).
RD START RQ generates KIOA5 and conditions a DCD
set gate at flip-flop A. On the next reset of flip-flop
B flip-flop A sets.
A(l) conditions the KEY INIT POS gate and the RUN
set gate. The next REPT ClK pulse sets C, and C(1)
turns on IND ClK to produce the KEY INIT POS
pulse. C resets on the next REPT ClK pulse, resetting
A and setting RUN.
KEY INIT POS generates PK ClR, both pulses reset
the CMA 00,01,02 flip-flops, and KIOA5 changes
the resulting CM address from 00 to 01, drawing KC17
KEY INIT POS starts the CM timing chain, drawing
KC 16, to extract process word 01. Processes ADSO (1)
and MBI(l) transfer the ADDRESS switch contents to
the MB and SM(l) starts the core memory cycle on the
ClK pulse after RUN(l) as for the DEPOSIT THIS operation. SM(1) and CM ClK also restart the CM timing
to extract process word 25. ClK POS resets the RUN
flip-flop in conjunction with KIOA5. KEY(1) of
process word 25 sets the READ IN 2 flip-flop on drawing KD8. READ IN 1(1) A READ IN 2(1) set the
IOTOI02 flip-flop, drawing KD9(1).
IOTOI02(1) goes to the input mixer, drawing KD7(1),
where it generates the RDR ON BUS level. RDR ON
7-6
BUS gates the RBOO-17 contents into the input mixer
gates, whose outputs are NORed onto I/o bus (B).
STROBE derived from core memory's MEM STROBE at
the CM timing chain therefore extracts ptocess word
27.
Other processes evolved from process word 25 gate the
current address held in the MB into the AR, gate the
I/o bus (B) contents onto the 0 bus, and the 0 bus
into the MB, as for DEPOSIT THIS. The core memory
write-half-cycle stores the MB contents at the current
address previously transferred from the MB to the MA.
Process word 27 is a do-nothing process which merely
contains CMAOO. At this time, another RSB pulse
occurs by virtue of READ IN 1(1) and KEY(1) of process word 25, delayed 1.2 fJs in R302-F05M, drawing
KD8. RSB produces IOTOl04 to turn on the tape
reader as before. The reader control assembles the
next word in the RB.
Process word 25 contains CMA26. But now Rl2(l)B
derived from READ IN 2(1) boosts the address to 27 in
conjunction with KEY(1), drawing KC17. The CM
RIl(1)B A RDR FLG(1) generates RD START RQ and
KIOA5 as before, and additionally RI2(1)B generates
ClK POS
-1
REPT
ClK
r-
I I I I I I I II I I I I I I I
I I I I I I I I I I
LJ
LJ
2 pile - hee
~EPEAT SPEED
KRI
KEY
DlY
C
B
A
RI1
RI2
RSB
RDR
FlG
KEY
INIT
POS
CM
STROBE
RUN
RD
START
RQ
RD
HOLE
7
10
RESTART _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _' - -_ _ _ _ _ _ _ _----L_ _ _ _ _ __
DONE
9l-0062
Figure 7-2
READ IN Mode Timing
7-7
----------------~----""
---
A bus, the address on the A bus goes through the
ADR, and NOSH places it on the 0 bus. II"! additi on,
ARO(1) produces RQ MBI in conjunction with SM(l),
RUN(1), and ClK on drawing KC19(2). RQ MBI gener
ates 1 ... MBI, setting the MBI flip-flop. MBI(1) gates
the current address from the 0 bus into the MB. Note
that this is the address of the last word stored in core
memory by the previous 03, 25, and 27 processes.
KIOA4. Therefore, the CM STROBE initiated by the
next KEY INIT POS pulse extracts process word 03.
Process word 03 increments the current address in the
AR by 1 and gates the incremented address into the
MB. The computer proceeds to process word 25,
storing the new word in the next consecutive core
memory location. Process word 27 is extracted as for
the first word. These processes (03,25,27) repeat to
store all successive RB words in consecutive locations,
unti I the last word is detected by the presence of a
RD HOLE 7 level from the last line in the reader
control logic.
SM(l) waits for the next ClK pulse, at which time the
core memory cycle starts and the CM timing chain
cycles to extract the next process word from location
33. Process word 33 is the XCT entry word which
causes the computer to execute the instruction encoded in the last stored word. DONE(1) in the
succeeding instruction execute process word resets the
READ IN 2 flip-flop.
Figure 7-2 is a practical illustration of the timing
using a two-word tape record. Since the second word
is the last, the RD HOLE 7 level appears with the
third line of information at W023-Al7L, drawing
KD9(2). RD HOLE 7 becomes RD HOLE 7(B) and RD
HOLE 7(C) at inverters S107-C06T, S107-E06T. On
drawing KD8, RD HOLE 7(8) conditions the DCD reset
gate at the READ IN 1 flip-flop and the DCD gate at
the INPUT 10 RESTART pulse amplifier S602-F04U.
7.1.10
I/o
RESET Key
The I/o RESET key clears all flags in I/o devices,
control flip-flops in the I/o control logic, and all
CP registers except the PC.
KEY INIT POS occurs to extract the first of the three
process words 03, 25, 27, and RUN sets' to issue the
ClK POS pulse. ClK POS cannot reset RUN because
of RD HOLE 7(C) at the reset input gate.
KEY(1) of process word 25 resets the READ IN 1" flipflop, and triggers the 1.2 J-Is delay in R302-F05M,
drawing KD8. Reset READ IN 1 removes RI1 (1)B and
consequently RD START RQ from flip-flop A, drawing
KC10(1). The removal of RI1 (1)B also removes KIOA5
from the CM address gates. RI2(1)B remains to place
KIOA4 at the address gates.
Delayed KEY(1) recovers after 1.2 J-IS to produce
INPUT 10 RESTART. Since READ IN 1 is reset, the
delay upon recovery cannot produce another RSB
pulse. With the RUN flip-flop remaining set I the
REPT ClK is disabled, flip-flops A, B, and C cannot
recyc Ie, and KEY INIT POS cannot occur. The next
process word must be extraCted, therefore, by INPUT
10 RESTART. This pulse goes to the I/o control logic,
drawing KD3(3), where it triggers pulse amplifier
S602-H20K for 10 RESTART. The 10 RESTART pulse
triggers the CM timing chain, drawing KC16.
The next CM STROBE thus obtained wi II extract process word 02 from control memory. (The CM address
in process word 27 is 00; this is boosted to 02 by
KIOA4.)
The I/o RESET function norma lIy starts from a computer stop condition. When the operator depresses
the I/o RESET key, the ground KIO level obtained
from the key conditions input DCD gates at pulse
amplifiers S602-HllK and S603-J10F, drawing
KD3(1). These gates are strobed constantly by
positive ClK pulses from the main clock, drawing
KC10. Unlike the gated negative ClK and ClK
POS pulses, the positive ClK pulses are present independent of the RUN flip-flop status. These ungated ClK pulses, therefore, generate 10 PWR CLR
POS and lOT PWR ClR pulses at the amplifiers as
long as the KIO conditioning level is present.
The 10 PWR ClR POS pulses reset the BKO, BK1 flipflops, drawing KD3. They a Iso go to the flags of
optional I/o devices via the I/o bus, and to certain
flip-flops within the I/o control section controlling
the standard I/o equipment. The lOT PWR ClR
pulses clear the DCH SYNC, PIE, and 100, 101 flipflops, drawing KD3. 10 PWR ClR POS generates
10 ClR on KD3(2). 10 ClR resets PROG SY, PROG
SYNC, and BK fHp-flops.
The ground KIO level also produces KEY DlY on
drawing KC10 as for other manual key functions, and
generates KIOA3, KIOA5. KEY DlY upon recovery
sets the REPT flip-flop, allowing flip-flops C and B to
set A, and generating KEY INIT POS and setting RUN.
The ensuin~ ClK POS pulse resets RUN shortly there-
Process word 02 contains ARO, SM, and CMA33.
ARO(1) gates the current address in the AR onto the
7-8
after, in conjunction with KIOAS and the negation
states of RDR HO lE 7(C), RIl (l)B.
tion or one cycle at a time. If both switches are up,
the SING STEP function overrides SING INST.
The CM STROBE produced in control memory by KEY
INIT POS extracts process word OS because of the
KIOA3, KIOAS address levels at the CM address gates,
drawing KC17. Process word OS contains ACI, ARI,
MBI, MQI, LI, KEY, CONT, and CMA27. ACI(l),
ARI(1), MBI(l), and MQI(1) open their respective
registers to the contents of the 0 bus. Since the 0
bus contains nothing at this time, the AC, AR, MB,
MQ registers are filled with Os. LI(l) strobes the
jam input gate of the LAR, drawing KC1S. Since the
"normal" input gates are disabled by a ground KEY (0) ,
LI(1) resets the LAR.
If the SING STEP switch is operated during a running
program, the computer wi II ha It at the end of the
current cycle, drawing KCI0. The CONTINUE THIS
key can then be used to step the instructions one cycle
at a time, with each CONTINUE THIS depression.
The CM STROBE produced by KEY INIT POS restarts
-the CM timing in conjunction with CONT(l), to extract process word 27. Process word 27 is the donothing process which contains merely the CM address
00. LI (0) resets the Li nk .
Reset RUN allows REPT ClK pulses to recycle flipflops C and B, and th!,! computer remai ns in the 00
KEY NOP state unti I another key is operated.
The CONTINUE THIS key can also be used with the
REPT switch for continuous SING STEP or SING INST
operations. Ordinarily, turning on the SING INST
switch alone will cause the RUN flip-flop to reset
upon completion of the current execute cycle. The
CONTINUE THIS key would then be depressed for the
execution of the next instruction. If the REPT switch
is turned on (up), the REPT flip-flop remains set as
RUN resets, and the REPT ClK pulses step flip-flops
A, B, C to eventually set RUN. Thus, the program
continues one instruction at a time, at intervals determined by the REPEAT SPEED switch. This eliminates
the necessity for depressing the CONTINUE THIS key
for each advance.
7.2 DISPLAY INDICATORS
7.2.1 REGISTER Indicator
7.1.11 REPT and REPEAT SPEED Switches
The latched up position of the REPT switch disables
the DCD reset gate of the REPT flip-flop, drawing
KCI0, so that the flip-flop cannot become reset by the
ClK POS pulse after RUN(1). With the REPT flipflop always set, the REPT ClK pulses will recycle
flip-flops A, B, and C to set RUN each time RUN
resets. The recurrence rate of REPT ClK pulses
determines the time interval from RUN reset to RUN
set. The REPEAT SPEED switch determines the REPT
ClK recurrence rate. The REPT and REPEAT SPEED
switches are normally used in this manner with START,
CONTINUE THIS, READ IN, and with built-in maintenance provisions. REPEAT SPEED is a five-position
rotary switch, drawing CS-S40S01S, which selects
various capacitors to tune the REPT ClK frequency
for speeds ranging from 2 I-IS to Is. The capacitor
selected by position 1 is mounted externally, whi Ie
a II others are located within the REPT ClK module
R401. Note that READ IN operations require that
REPEAT SPEED be placed in position S (2 jJS).
The Il-position REGISTER DISPLAY switch on the
console selects the contents of the following registers
for display in the lS-bit REGISTER indicator.
AC contents
AR contents
MQ contents
PC, Li nk, memory extend mode status, memory
protect mode status ,EPC
RDR - reader buffer contents
TTl - keyboard buffer contents
API - on/off, interrupt request, and priority level
status of eight priority levels
I/o A - IS-bit address word in DCH or API
operations
I/o ~ - lS-bit data word on I/Obus from/to any
device
DPY - 9-bits each of X, Y buffers of optional··
Type 34Hl Display
The REGISTER DISPLAY switch and the REGISTER
indicator are enabled by IND EN when the computer
is in the stop condition. The IND EN level from drawing KCI0 goes to the REGISTER DISPLAY switch wiper,
drawing CS-S40S01S via the CP/console interface,
drawing KC23.
7.1.12 SING INST and SING STEP Switches
The latched up positions of the SING INST and SING
STEP switches are normally used in conjunction with
CONTINUE THIS to advance a program one instruc-
i-9
Note that the I/o BUS position of the switch is actually
the off position. In this position, the indicator displayS-whatever happens to be on the data lines of the
I/o bus.
If any of the four CP registers (AC, AR, PC, MQ) were
preselected, the appropriate enabling level (ACD, etc.)
goes from the switch contact to the respective register
gate sense flip-flop I setting the flip-flop on a CM
STROBE B generated by IND ClK. IND EN also sets
10 BUS ON at CM STROBE B time. The IND ClK
pulses are derived from the stepping of flip-flops Band
C during the RUN reset condition (computer NOP).
The sense flip-flop opens the A bus to the appropriate
register contents. As shown in Figure 7-3, a direct
signal path to the input mixer is afforded by the A bus,
ADR, and I/o bus. At the input mixer, drawing KD7,
the contents on the I/O bus are inverted (buffered) at
NOR gates R123, then fed from the 10/CP interface
(drawings KC25, KD6) to indicator driver transistors
in the console, drawing CS-5408020. The transistors
supply drive current of 30 rnA at -2V to the appropriate
REGISTER indicator lamps (REG 00-17) for all binary 1
levels received from 10 BUSOO(B) - 10 BUS17(B). The
indicator lamps remain illuminated as long as the
operator holds the computer in the stop condition.
7.2.2 Link Indicator
The set side of the Link is wired through the CP/IO
and IO/console interface to its indicator drive transistor in the console, then to the Link indicator lamp.
When the Link sets, the indicator illuminates. Although displayed continually I the Link indication is
meaningful only when the AC contents are selected
in the computer stop condition. The LINK flip-flop
is shown on drawing KC15.
7.2.3 MEMORY BUFFER Indicator
The MB register bits MBOO-17 are wired through the
CP/IO and IO/console interface to their indicator
driver transistors in the console, then to the MEMORY
BUFFER indicator lamps. Although displayed continualIy, the indication is meaningful only in the computer
stop condition.
The select levels for all other display selections go
from the REGISTER DISPLAY switch to the input mixer
via the CP/console (drawing KC23) and CP/IO interface (CP/H40 to 10/H01, drawing KC25). At the input mixer the select level (RDRD I etc.) passes a NOR
gate in Rlll-D17 to produce a RDR ON BUS etc.
signal which gates the selected information into the
input mixer modules. The information is then buffered
at 10 BUSOO(B) - 10 BUS 17(B) as for the CP registers.
7.2.4 INSTRUCTION Indicator
The five INSTRUCTION indicator lamps continually
di splay the contents of the IR. The first four lamps
KC 25
CP/F39-40
KC- 21
IO/F01-02
K D-7
K C-25
r-------l
INPUT
MIXER
10 BUS (BI
00-17
I
I
I
EOI
E02
E40
E39
RDR ON BUS ETC
KD-6
r-----,
I I
I I
I I
I
I
All
I--I--~ A I 2 I---l-c--=---o-=-l
I
I
AI3
I
I
I
I I/O
CP
I I I/O
L ________ J L ____ J
RDR
TTl
STATUS
API
1/0 ADDR
I/O BUS
DPY
KC 23
Figure 7-3
REGISTER DISPLAY Signal Paths
7-10
indicate the op code IROO-03 of the instruction being
executed. The fifth lamp illuminates when the
memory reference instruction contains an indirect
address (IR04 = 1). The IR bits are wired to their
indicator driver transistorS in the console via the
CP/console interface, then to the indicator lamps.
REPT flip-flop is normally controlled by the program,
but may be kept in the set state by the REPT switch
for maintenance purposes.
7.2.10 PRGM STOP Indicator
7.2.S PIE Indicator
The PIE indicator illuminates when the program
interrupt faci lity is enabled by an IOT0042 instruction
(ION). In the I/O control logic, drawing KD3(2),
the decoded instruction sets the PIE flip-flop. The
set side of the flip-flop is wired to its indicator driver
transistor in the console via the IO/console interface,
then to the indicator lamp. The lamp remains illumin- .
ated unti I a program interrupt occurs or until an
IOT0002 instruction (IOF) is issued. Both events reset
the PIE flip-flop, disabling the facility and extinquishing the lamp.
The PRGM STOP indicator illuminates when the RUN
flip-flop resets. The reset side of the RUN flip-flop
is wired through the CP/console interface to its
indicator driver transistor in the console, then to the
indicator lamp.
7.2. 11 DATA Indicator
The DATA indicator illuminates when a DCH break is
in progress. From drawing KD3(1) a DCH BK DlY
level goes through the I/o interface to the DATA
indi cator driver transistor in the console, then to the
indicator.
7.3 POWER CONTROL
7.2.6 ClK Indicator
The ClK indicator illuminates when an IOT0044 instruction (ClON) enables the optional real-time clock.
The ClK switch must be down before the lOT instruction can enable the clock.
7.2.7 SING STEP Indicator
The SING STEP indicator illuminates when the SING
STEP switch is turned on. The SW SG l STP level from
the switch goes via the CP/console interface to its
indicator driver transistor in the console, then to the
indicator lamp ..
7.2.8 SING INST Indicator
The SING INST indicator illuminates when the SING
INST switch is turned on. The SW SGl INST level
from the switch goes via the CP/console interface to its
indicator driver transistor in the console, then to the
indicator lamp.
7.2.9 REPT Indicator
The REPT indicator illuminates when the REPT flip-flop
is set. From drawing KCI0 the REPT(1) level goes
through the CP/console interface to its indicator driver
transistor in the console, then to the indicator. The
7-11
7.3.1 Primary Power Distribution
The PDP-9/l will accept several primary power inputs.
This flexibility permits it to be operated in many
power envi ronments. Adj ustment to di fferent conditions is done by changing various input transformer
taps in the power distribution system. Input power
"equirements are 3 KVA. For 60 Hz power sources,
adjustment can be made for either 120 or 240V. For
SO Hz sources, adjustments may be made for 100V,
IS0V, 200V, 21SV and 230V cc. Primary power
distribution is shown on drawing 9-l-3. Primary
power is applied to TBI of the main Type 712 Power
Supply located at the bottom right of the front panel
as viewed from the rear (drawing 712-0-1).
Power is applied to the system by 40A circuit breaker
CB 1, located on the 712 Power Supply between the
two distribution boards and accessible from the rear
(panel doors are not interlocked). Closing this
breaker applies power to the console and the maintenance panel and energizes the main power contactor
K1, from which power is taken for the uti lity outlets
and power supply transformers T1 and T2. Adjusted
ac voltage then is distributed by auto tap to the HighSpeed Punch PC09, the Memory Me71, the fans,
.
the Central Processor KC09-C, and the I/o Control
KD09-C. The elapsed time meter is tied across the
high-speed punch auto-tap and indicates to the
nearest tenth of an hour, the cumulative hours of
system power on .
All jumper modifications are usually made by the
manufacturer to suit a particular customer's needs.
A quick check, however, is usually in order before
applying power. There are four categories of adjustments:
line frequency, when input voltage is 110V, jumpers
must be connected between J -12 and J -13 and between
J-14 and J-15. If the input voltage is 220V, these
jumpers should be removed, allowing current limiting
resistors R3 for 11 and R9 for K1 to function.
The next check is the auto-taps, Number 1 for the
high-speed punch and Number 2 for the fans. If
operating conditions are 50 Hz, 115V, the line should
be connected between terminals 10 and 13 on both T1
and T2. With 60 Hz, 120V conditions, connect the
line from pins 11-13.
a. Power contactor current limit adjustments,
b. Auto-taps,
c. Power transformer pri mari es, and
d. Power transformer secondari es .
The power transformer primary connections and jumpers
should then be checked against Table 7-1 for the
particular line voltage and frequency conditions at
the operating site.
These various conditions are given in Table 7-1.
Check first the power contact jumpers; regardless of
Table 7-1
Input Power Adjustments
Category
Power
Contactor
Auto Taps
Transformer
Primary
Line
Frequency
Line
Voltage
Line
Connections
110
J12-J13
J14-J15
220
None
50
115
Not
Applicable
10-11
60
120.
Not
Applicable
11-13
50
100
11-14
12-13
10-12
11-15
13-14
10-14
10-15
11-14
12-13
13-14
11-12
50/60
115
60
200
215
230
120
240
Transformer
Secondary
Jumpers
50
60
Not
Applicable
Not
Applicable
7-12
Not
Applicable
Not
Applicable
Not
Applicable
11-12
11-12
11-12
11-12
11-12
11-12
50 Hz Blk.
60 Hz Blk.
Finally 1 the transformer secondary connectors should
be plugged into the proper block for the power
frequency used. These connections are changed by
removing and replacing two modular quick-disconnect
fittings. This information is repeated for quick reference in Table 7-1 .
memory voltage relay K2. Operation of K2 is from
a delayed ground from the memory contral module to
-15V in this supply,
The marginal check supplies operate in conjunction
with the Me switch S 1 to vary the voltages to the
logic, thereby determining the life expectancy of
selected logic modules. This becomes part of the
preventive maintenance schedule for the computer.
In use, certain sets of logic modules are selected by
marginal check switches located within the rack. The
marginal check switch on the maintenance panel is
then set to either + Me or - Me position and a selected diagnostic routine is run. During the routin~, the
variable supply is adjusted until the computer fails.
At this point the voltage, as indicated by the marginal
check voltmeter M2, is recorded for future reference.
The same procedure is followed for the opposite polarity. These periodically recorded failure points are
then used to forecast impending problems in modules.
7,3.2 Power Supply
The 712 Power SupplYI drawing 712-0-1 1 is a dual
50/60 Hz unit designed for ease in conversion to any
of the input and frequency combinations listed in the
drawing. The user simply matches the line frequency
and then chooses the input voltage value which most
nearly matches his nominal line voltage. He then
arranges the transformer taps to the chosen va lues.
Output voltages and current drains are as shown.
Figure 7-4 is a functional block diagram of the 712
Power Supply. Its purpose is to provide the -30 Vdc
required by the high-speed punch and the memory;
and also to supply the logic dc voltages +15 and -10,
The 712 Power Supply is made up of two groups of
heavy-duty power supply modules. One group is fed
by T1 the other by T2, The first group comprise
a fixed -15 Vdc, a fixed +10 Vdc, and an ungrounded
supply made variable between 0 and approximately
20 Vdc. The second group contains a +10, a -15,
and a -30 Vdc supply. The -30 Vdc supply feeds the
punch directly, and the memory through operation of
The function of the marginal check switch Sl is illustrated in Figure 7-5. In OFF position (Figure 7-5aL
the meter Ml is disconnected and fixed positive and
negative voltages are sent to the logic modules. Note
a Iso that a ground is placed on the output of the variable supply. In the + Me position (Figure 7-5b) the
positive voltage to the logic is varied while the negative voltage is fixed. In - Me position (Figure 7-5c)
the negative voltage is varied while the positive voltage is fixed. In either Me position the buckoff meter
o
rl
II
3KVA
IN
Lei
K1
UTIL1 TY
OUTLETS
+ 20
VARIABLE
SUPPLY
+10V
Me SUPPLY
T1
""
o TO
I
J
~~
MC
SWITCH
SI
~
END
OF
LI NE
SHORT
Jl
v MARGINAL
r------ +10
CHECK TO LOGIC
f--------
- 15 V MARGINAL
CHECK TO LOGIC
t
-15V
MC
•
SUPPLY
AC TO PUNCH
~
~
I
T2
+lOV
SUPPLY
+ 10V DC TO
-15V
SUPPLY
-30V
SUPPLY
GNO
FROM MEM
CONTROL
15 V DC TO LOGIC
11
MEM
VOLT
RELAY
30 V DC TO MEMORY
K2
30VOC TO PUNCH
AC TO FANS
Figure 7-4
Power Supply 712, Block Diagram
7-13
LOGIC
A (OFF)
<$>
:: '1 ::
METE."
:·1 -DISCONNECTED
I
,-.:+-;-.-:+.f.:..O---oO...- -...t-----4..:C=----I.~ + 10 V FIXED
T'Er-I
. POWER
IN
FROM
KI
=:J
D. . CJ~+1------04-0"
..
I
_.,d
---+-t
I
..
-15
I
Er--I'---1:IOIIII:t---.--+J=----.,0 0
0
,0° n 5
I
u
IJ
~L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
10 SYNC POS
PROG. 3Y
DONE
BK SYNC
I~--------------------------------~
BK
PROG. SYNC
PIE
DLY
IL--__
-l
10 CLR
____________________________________---ln
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
BK ENTRY (11)
lAO ENTRY(32)
------------------'L-.-J
(23)
(60)
B GN (10)
II+.------CURRENT
EXECUTE
CYGLE-------ooI.I....- - - - - -
IA0
CYCLE _ _ _ _ _ _ _ _ _......~.-FETCH
00001
9L
Figure 8-4
Program Interrupt Timing
8-8
~0080
/
CLK(B) pulse which appears at the 10 SYNC POS
gate and which triggers the B301 Delay Multivibrator
on drawing KD3(3). At the 10 SYNC POS gate 10
CLK(B) cannot generate another 10 SYNC POS pulse
because of PROG SY(O) at ground (PROG SY is still
set).
The B301 Delay Multivibrator recovers 400 ns after
10 CLK (B) so that the DLY output goes to ground
(DL Y). DLYand BK(l) trigger pulse amplifier S602H1lU for 10 CLR, drawing KD3(2). 10 CLR resets
PROG SY, PROG SYNC, and BK. The PROG SYNC
flip-flop, upon resetting, triggers pulse amplifier
S602-J09K to generate a ground going pulse. This
pulse pulls the collector of the PIE flip-flop to ground,
resetting the fl ip-flop. PIE (0) from the reset fI ip-flop
holds the PROG SY flip-flop in the reset state, so that
future PROG INT RQs cannot cause a program interrupt
unless an ION instruction has been issued.
The next computer CLK pulse starts a fetch cycle to
fetch the instruction word located at 00001. This is
usually a JMP to the flag search subroutine which
finds and services the device that requested the interrupt.
The service routine includes an lOT instruction which
resets the device flag as it performs the data transfer(s).
This removes the PROG INT RQ from the common I/O
bus line, to allow other devices to use the line. The
service routine must also include an lOT ION instruction to re-enable the PI facility for the other devices,
since PIE was reset. The ION instruction is normally
programmed just before the service routine exit.
The next computer cycle fetches the JMP * 00000 instruction from memory and places it in the MB. The
op code detection circuits recognize the indirect address, and the computer therei:;,re goes into a defer
cycle to fetch the contents (effective address) of location 00000. The interrupted PC count, the Link
status, memory extend mode status, memory protect
mode status, and extended program count comprise
the contents of location 00000, now read into the MB
by the defer entry process word (31).
Process word 31 also detects the JMP op code to produce REP, in which case the JMP execute process 74
follows. DEI going to 0 at the start of process 74 sets
the second flip-flop in S202-H10. This flip-flop then
resets DB RESTORE and produces a DBR pulse at W612E16D, which goes through the CP-IjO interface to
drawing KC15. Here DBR is NANDed with MBOO at
Rl11-D05H. If MBOO is 1, indicating that the stored
Link status was 1, a ground level A BUS LINK results.
A BUS LINK causes the ADRL to go negative.
Process word 74 takes the contents of the MB and gates
the address portion into the PC via the B bus, ADR,
and 0 bus. As this occurs, the ADRL is strobed into
LAR by LI(l) of the process. Process word 10 (BGN)
follows, during which the restored PC contents are
gated back into the MB via the A bus, ADR, and 0
bus, and the LAR state is strobed into the Link by
LI(O). The interrupted Link status is thus restored to
the Link, the interrupted program address is restored
to the PC and MB, and the computer will now resume
the program on the coming fetch cycle.
For EXD mode, PRTCT mode, and EPC status restoration, refer to the respective option manuals.
To exit from the service routine and return to the main
program, provisions must also be made to restore the
status of the Link, memory EXD mode, memory PRTCT
mode, and EPC. An lOT DBR instruction (703344)
issued before the JMP * 00000 that returns to the main
program wi II restore the status.
The lOT 10F instruction may be programmed to disable
the PI facility as necessary. In this case, IOT0002
produced as for lOT ION resets the PIE flip-flop via
its DCD reset gate because of the detected SDO
ground level.
The typical exit sequence, therefore, is:
ION
DBR
JMP
*
/RE-ENABLE PI
/pRIME SYSTEM TO RESTORE
/pC,L,EXD,PRTCT,EPC STATUS
00000
/RESTORE INTERRUPTED STATUS
On drawing KD3(l) the DBR instruction (703344} is decoded to produce an IOP4 and, consequently, an
IOT3344 pulse at R11l-F 1OUV. IOT3344 sets the DB
RESTORE flip-flop S202-H10. DB RESTORE(l) then
conditions the DCD set gate to the second flip-flop
in S202-H10.
8-9
8.1.8 I/O Status Check Facility
The lOT 10RS instruction (700314) loads the AC with
a word comprising the status of various device flags
and control flip-flops. IOT0314 is detected during
fetch to select the facility and to start the lOP generation. In this case device 03 is the ASR33 Teletype
keyboard, MB14(1) puts Os in the AC, and MB15(1)
generates IOP4 to read the status bits from the I/O
bus into the AC. This differs from the normal scheme
where IOP2 is used for input transfers. Of the 18
possible status bits thus deposited in the AC for further
examination, 11 have been preassigned as listed in
Table 8-1.
On drawing K03(l), OSO-2 are sampled by 10T(1)
from the CP detection circuits to produce OXEN. The
OXEN level is further gated with OS03P, OS04, OS05
on drawing KOll(l), turning on the KBO SEl level.
The pulse counter flip-flops 100 and 101 on K03(3)
produce IOP4P on the fourth 10 ClK POS pulse, and
IOP4P sets the RO STATUS flip-flop on KOll(l). RO
STATUS(l) generates STATUS ON BUS at the input
mixer, drawing K07(1). STATUS ON BUS becomes
RO STATUS at bus driver B213-F07, drawing KOll(1).
The RO STATUS level goes through the I/O bus to the
preassigned device flag and control flip-flop output
gates, placing their status on the bus. STATUS ON
BUS gat.es the status bits into the input mixer diode
gates, whose outputs are NORed onto I/O bus (B).
RO STATUS(l) also appears at diode mixer R141-F240,
drawing K03(3), to produce the INT RO RQ BUS signal. INT RO RQ BUS is NORed ~t Rll1-F19UV for
RO RQ(B). 400 ns after the 10 ClK POS pulse produces IOP4with 101(1), the RO RQ(B), 101(1), and
ClK OlY10 signals generate AC RO at W612-F18N.
AC RO(B) turns on LIO, drawing KC13, and 1 -ACI,
drawing 19(2) to gate the contents from I/o bus (B) to
the 0 bus and into the AC.
Table 8-1
I/o Status Bit Assignments
Bit
Status
00
Program Interrupt On
01
Tape Reader Flag
02
Tape Punch Flag
03
Teletype Keyboard Flag
04
Teletype Printer Flag
05
Oscilloscope Display Option Flag
06
Real Time Clock Option Overflow Flag
07
Clock Enable
08
Tape Reader No Tape
Table 8-1
I/O Status Bit Assignments
Bit
Status
09
Tape Punch No Tape
10
DECtape Option Flag(s)
11-14
Unassigned
15-17
Reserved for special customer devices
--
8.2 DATA CHANNEL TRANSFERS
Four data channels (DCH) provide a high-speed data
transfer path between core memory and four optional
devices for the transfer of blocks of data. Address
and control lines go through a secondary I/O bus,
and the data lines go through the primary I/O bus
which is used for program-controlled transfers.
Each of the four devices are assigned a pair of sequential channel registers in core memory:
Channel Registers
Device
o
00030
00031
00032
00033
00034
00035
2
00036
00037
3
These registers are initialized by the program before
the device begins transferring data. The first register of a pair is a word count (We) register initialized to the 2 1s complement of the number of data words
to be transferred, The second is a current address
(CA) register which is initialized to the address, -1,
of the location from/to which the first data word is
transferred. Four additional devices can be attached
to the existing configuration; however appropriate
channel register addresses must be assigned.
Once the registers have been initialized, the computer instructs the device, by means of lOT instructions, to prepare for transfer operations. The device
itself contains essentially the same control logic as
for program-controlled transfers, plus other DCH
logic. Most of the additional logic is contained in a
W104 Multiplexer.
8-10
/
When the device is ready for the input/output transfer, it issues a DCH RQ to the computer on an 10
SYNC pulse. The CP honors the request at the completion of the current instruction by issuing a BK
SYNC to the control memory logic and a DCH GR
to all four devices. The DCH GR allows the requesting device to place the address of its WC register on the secondary I/O bus; the BK SYNC
causes the computer to exit the program and as for
program interrupt to go into the BK entry process.
The next computer cycle(s) performs the actual datil
transfer. For input transfer core memory reads out
the contents of the addressed location, but they are
flocked from the MB and are therefore lost. Other
processes gate the data word from the AR to the MB,
and core memory writes the word into the addressed
location. This completes the input transfer, and a
BGN word (or another BK entry word) follows.
The BK entry process replaces the BGN process at the
end of the normal computer execute cycle. The process transfers the WC address from the secondary I/O
bus to the MB. The WC address a Iso goes from the
MB into the MA for the coming computer cycle. The
computer enters a WC cycle, incrementing the WC
ADDR by 1 and storing it in the AR. The core memory read-half-cycle reads out the contents of the addressed WC register, +1, into the MB. If the contents (word count) have incremented to 0, an 10
OFLO signal goes to the device, telling it not to
request further transfers since the last data word is
about to be transferred. If the device is also connected to the PI facility and the facility is enabled,
it may also use the 10 OFLO to issue a PROG INT RQ
to the computer. For example, the PI can be honored
to branch to a subroutine which re-initializes the WC
and CA registers.
In any case, the core memory writes the incremented
word count back into the WC register, and other processes place the incremented WC ADDR from the AR
into the MB and MA for the next computer cycle.
The incremented address is the address of the device's
CA register.
For an output transfer the core memory read-half-cycle
does place the contents of the addressed location in
the MB, since the .contents represent the data word to
be transferred to the devi ce. Other processes gate
the data word from the MB onto the primary I/O bus,
and the core memory restores the same data word to
the addressed location.
This completes one computer output cycle. An additional idle cycle ensues which gives the data word
time to settle on the primary I/O bus and the device
time to strobe it into its data register. During the
idle cycle, the device's WR RQ generates an IOP4
in the I/O control logic. IOP4 generates an lOT
XX04 pulse in the device's device selector, which
is used to strobe the data in. A BGN process (or BK
entry) word follows as for the single input transfer
cycle.
Successive DCH requests and DCH breaks can occur
from the same devi ce or another devi ce provided the
device flag has been raised at the start of the current
CA cycle. Otherwise, the program resumes and executes at least one instruction before the DCH can
cause another break entry. If the instruction is an
lOT, XCT, or optional EAE instruction, a considerable delay between OCH breaks is possible, since
these are multi -cycle instructions and their DONE(l)
levels appear in the last cycle only. For maximum
operating effi ciency, the program must be planned
with the device transfer rates and the break entry
point in mind.
The next computer cy~le is a CA cycle, in which the
address contained in the CA register is read from core
memory into the MS. On its way through the ADR
to the MB, the address is incremented by 1 (unless
searching). The incremented address is the address of
the core memory location from/to which the data word
is to be transferred. For an input transfer, the device has issued a RD RQ by this time, which generates
an IOP2 in the I/O control logic. IOP2 goes to the
device's W103 Device Selector to generate an lOT
XX02 pulse. The device uses this pulse to gate the
data word out of its data register onto the primary
I/O bus. Other processes gate the data word into the
AR as the core memory writes the incremented address
into the CA.
Priority among I/O devices making simultaneous DCH
requests is determined by their physical placement.
Devices closer to the I/O bus have priority over those
farther away. An enabling level from the computer's
I/O control section is chain-connected through the
W104 multiplexer in each device. The DCH grant to
all four devices causes the removal of the enabling
level from the lower priority devices.
For an output transfer, the processes write Os into the
AR because no RD RQ has been issuecl and, consequently, no data is placed on the primary I/O bus.
DCH operations also include an add-to-memory feature (Section 8.2.8).
8-11
8.2.1 I/O Bus Connections
The DCH uses the data, 10 SYNC, RD RQ, and 10
PWR ClR lines of the primary I/O bus, AB25, 26
drawing KD2(l), and certain address and control lines
of the secondary I/o bus, drawing KD2(2). The same
cabling considerations for the primary bus apply to
the secondary. Of the 1510 ADDR lines shown on
KD2(2) the DCH uses the six least significant for the
four assigned pairs of channel addresses.
The basic PDP-9/L allots four pairs of WC and CA registers in core memory for use with four optional devices in the data channels. Because of the time delay
encountered in propagating signals through the Wl04
modules, the number of additional devices is limited
to four (total eight) provided the total I/O bus cable
length does not exceed 50 ft. The additional pairs of
core memory registers must be assigned and protected,
and the devices must contain the W104 multiplexer or
equivalent logic interfaced to the I/O bus.
8.2.2 Multiplexer W104
Figure 8-5 is the logic diagram for the W104 module.
The device flag and 10 SYNC pulse set the REQ flipflop. The set REQ flip-flop sends a DCH RQ to the
computer and places the EN OUT level to succeeding
W104s at ground (EN IN), holding their REQ flipflops in the reset state until the currently requesting
device relinquishes control by resetting its flag.
8.2.3 Break Synchronization
The device flag raises asynchronously when the device
is ready for a data transfer. Thereafter, the DCH break
synchronizes on 10 SYNC and 10 SYNC POS pulses.
10 SYNC pulses occur on computer ClK POS pulses
where no lOT instruction is currently in progress,
drawing KD3(1). Under these conditions, 10 SYNC
occurs to set the REQ flip-flop in the W104 in conjunction with the device flag, Figure 8-5 and drawing
KC31. REQ(l) sends a ground DCH RQ to the DCH
SYNC flip-flop, drawing KD3(2), and grounds the
EN OUT signal to succeeding DCH devices. The EN
IN level is supplied by the I/O control, drawing
KD3(1) at W005-H19H, labeled DCH EN. DCH EN
goes to the first W104 from the secondary I/o bus.
Assuming that the first device has raised its flag, 10
SYNC has set its REQ flip-flop. The 0 side of REQ in
going to ground blocks the EN IN level at the R111
input gate. Thus, EN OUT goes to ground, resetting
and holding the lower priority REQ flip-flops.
8-12
The main ClK pulse, of course, starts a normal computer cycle. The DCH RQ sent to the I/O control
waits for the next ClK pulse. 10 ClK(B) derived
from the next ClK pulse (10 ClK POS) generates. 10
SYNC POS on drawing KD3(2) if the conditions lOT
(0), ClK SYNC(O), etc. are present. This means that
10 SYNC POS occurs only on an 10 ClK(B) during
which no lOT, optional API, RTC or PI, operation is
in progress~ The DCH, therefore, cannot interrupt
any of these current operati ons .
10 SYNC POS strobes a DCD gate conditioned by
DCH RQ to set the DCH SYNC flip-flop. DCH
SYNC(l) holds the optional ClK SYNC and PRE API
SYNC flip-flops in the reset state, and sets and holds
the DCH SYNC SAVE flip-flop. DCH SYNC SAVE
(1) holds the PROG SY fl ip-flop in the reset state.
Therefore, once the DCH SYNC flip-flop has set,
these operations cannot begin; DCH has the higher
priority.
DCH SYNC(l) also triggers the 100-fJs DCH BK Dl Y,
generates DCH GRANT on drawing KD3(l), and INC
+ DCH on KD3(2). DCH GRANT sets the ENA flipflop in the W104 in conjunction with REQ(l). ENA
(1) puts the device's 10 ADDR on the secondary I/O
bus. The 10 ADDR bits go to drawing KD5, where
they are buffered to 10 ADDR(B). The DCH BK DlY
illuminates the console DATA indicator.
DCH GRANT also produces a ClR FLAG pulse in the
W104. ClR FLAG resets the REQ flip-flop and the
device's data flag. EN OUT goes negative, allowing lower priority devices to make futvre DCH requests.
DCH SYNC(l) generates BK SYNC on drawing KD3(2).
BK SYNC waits for DONE(l) in the instruction being
executed. Since the device data flag was raised
asynchronously, the DCH SYNC flip-flop can set on
an 10 ClK(B) pulse which starts anyone of the four
norma I computer cycl es (fetch, defer, lAO, execute).
Assuming that the flag is raised before a normal twocycle computer instruction begins, the ClK pulse
that initiates fetch results in DCH RQ and the ClK
pulse that initiates execute results in DCH SYNC(l),
as shown in drawing KC31.
BK SYNC goes to the CP via the CP-I/O interface to
generate ODD ADDR in conjunction with DON E(l),
drawing KC17. The execute process word containing
DONE(l) also contains CMA10. Process word 10 is
the BGN word which normally places the next address
from the PC in the MB for the next computer fetch
cycle. Now ODD ADDR on drawing KC 17 boosts
CMA 10 to 11. Therefore, the last process word in
the execute cycle is taken from CM location 11.
Process word 11 is the BK entry word which starts the
DCH break operation. The word contains EXT, IRI,
SM, and CMA30. EXT(l) produces 10 ADDR ON
BUS, drawing KD7(l), and LIO, drawing KC13. 10
ADDR ON BUS gates the device's 10 ADDR 12(B)-17(B)
through the input mixer modules onto I/O bus (B).
LIO gates the address from I/O bus (B) onto the 0
bus.
EXT(l) on drawing KC19(2) produces 1 -+ MBI in conjunction with SM(l) and ClK. 1 -+ MBI sets the MBI
flip-flop, and MBI(l) then gates the address on the 0
bus into the MB.
from 30 to 34. Process word 34 wi II be extracted
from control memory on the CM STROBE that results
from the next CM ClK pulse to start the WC cycle.
Drawing KC5 shows the break flow from the BK entry'
process through completion.
8.2.4 WC Cycle
Process word 34 is extracted from control memory on
the CM ClK pulse in conjunction with SM(l) of the
BK entry word. ClK and SM(l) also start the core
memory read/wri te cyc Ie.
10 SYNC, derived from 10 ClK POS, sets ENB inthe W104, Figure 8-5. ENB(l) sends a SELECT level
to the W103 Device Selector in the DCH device.
This level is applied to W103-BD, Figure 8-3, bypassing the device select code input gates to force
selection of the device.
IRI(l) puts Os in the IR, drawing KC12. On drawing
KC17, EXT(l) and INC + DCH boost the CM address
10 AOOR 12
•
CONNECT AS NEEDED
•
}
AL
10 ADORI7
AN
AS
AU
•
~
-
'V
AP
BI63
ENA (II
o---~y~-~
6
+--+--+--__________-+-__________
~B::':M-
EN OUT
,.--_-+___________""AV'--+ ENA(OI
,.--____+-__~----------~B~V~OCHRa
W005
1- - - - - - - - -
AD -
-
- ,-1
SELECT
EN IN
--"'-'----------.j
I
REO (01
REO (I I
..."L-_ _---.-~
I
L-----'--,,/V'v
I
I
ENB (Il
, . - - - - + - - - - - "AF' - . ENB (01
I
10
ONLY USED WITH
DATA CHANNEL, NOT
NECESSARY WITH API
10 SYNC
J
RI07
ENA(OI
ENA(l1
CLR FLAG
I
l___________ ...,- ____
I
I
-.J
I-~t-----------B:..:.O--<>
I
FLAG
-"B-,,-S_ _ _ _ _ _ _ _ _ _ _.....J
OCH .:;::BE=---_ _ _ _ _ _ _ _ _ _ _-"--J
GRANT
'U
Rl07
I
II
I
I
I
I
I
I
I
I
I
I
I
PWR CLR
I
I
~-"'AE'--+
REO (I)
90-0003
Figure 8-5
Multiplexer W104, logic Diagram
8-1-3
AJ
AK
THROUGH
Process word 34 contains MBO, + 1, ARI, DCH, and
CMA10. MBO(l) gates the WC ADDR from the MB to
. the B bus. The address on the B bus goes through the
ADR, and NOSH places it on the 0 bus. As it goes
through the ADR, process + 1 (1) generates Cll7 on
drawing KC14, and CI17 increments the ADR contents
by 1. ARI(l) gates the incremented address from the
o bus into the AR.
Process word 34 remains active for two normal processword periods because the CM STROBE cannot retrigger
the CM timing chain, on drawing KC16, in the absence of a CONT(1) bit. CM STROBE does get as
far as the ClR gating, however, at which time DCH(l)
generates IN ClR and ClR. IN ClR sets MBI via
1 .. MBI and resets MBO, ARI. ClR sets SAO and
resets + 1.
DCH(1) sets BKO on drawing KD3(3) for a break
count of 10. BKO(1)' BK 1(0) generates DCH INX on
drawing KD3(3). DCH INX produces Cll7 on drawing
KC14, in conjunction with SAO(l).
The core memory read-half-cycle reads out the contents of the addressed WC regi ster. SAO (1) places
them on the B bus, the B bus contents go through the
ADR, and NOSH placed them on the 0 bus. As the
contents pass through the ADR they are incremented
by 1. MB(1) gates the contents into the MB. IAO(O)
and the MEM STRO BE that caused core memory readout retrigger the CM timing chain. If the word count
has incremented to 0, ADRA=O and ADRB=O result at
the ADR output, drawing KC21. ADR=O, SAO(1L
BKO(1), DK1(0), and the CM STROBE triggered by
MEM STROBE produce OFlO on drawing KC14.
OFlO goes through the CP-I/O interface to the 10
OFlO flip-flop on drawing KD3(2), setting the flipflop. 10 OFlO(l) goes through the I/O bus to a
control flip-flop in the device. The control flip-flop
acts to shut down the device, since the current data
transfer is the last transfer of the block of data. The
control flip-flop may also be used to send a program
interrupt request to the computer. The core memory
write-half"'cycle writes the incremented word count
into the WC register.
Process word 34 contains CMA10. On drawing KC17,
DCH(l), INC MB, and BK1(0) boost this address to
14. The negative INC MB level is present because
the add-to-memory capability (Section 8.2,8), and
optional real-time clock are inactive during normal
DCH operations.
The CM STROBE triggered by MEM STROBE extracts
process word 14. Process word 14 contains ARO, SM,
8-14
and CMA37. ARO (1) gates the contents of the AR
onto the A bus. The contents go through the ADR and
NOSH places them on the 0 bus. ARO(1) on drawing KC19(2) produces 1 ---MBI in conjunction with
SM(1) and ClK. 1 ---MBI sets the MBI flip-flop, and
MBI(l) gates the contents of the 0 bus into the MB.
The contents represent the address +1 of the WC register, incremented and stored in the AR earlier. This
incremented address is the address of the CA register;
it is jammed into the MA, at MA JAM time, for the
coming CA cycle. The CA cycle begins on the next
ClK pulse with SM(1) of process word 14.
8.2.5 CA Cycle
SM(l) and ClK start the control memory and the core
memory for the CA cycle, CM STROBE produced by
SM(1) • CM ClK extracts process word 37, whi ch contains DCH and CMA 13. DCH(1) steps the BK counter
to 11 by setting BK 1, with DKO remaining set.
If the device intended to make an input data transfer
it has placed a RD RQ and WR RQ on the I/O bus at
ENB(1) time. On drawing KD3(3), the RD RQ conditions a OCD gate so that an IOP2P pulse is generated
by S602-H21K when BK1 sets. IOP2P sets the IOP2
flip-flop. rOP2(1) then gates on an IOTXX02 pulse
in the device's W103 Device Selector in conjunction
with the force SELECT level from the W104. The lOT
XX02 pulse is used by the device to strobe the data
word from its data register onto the I/O bus.
Also, as BK1 sets, it resets the DCH SYNC flip-flop
in conjunction with WR RQ(B) on drawing KD3(2).
Reset DCHSYNC removes the BK SYNC, INC + DCH
and OCH GRANT levels, releases the reset hold on
the ClK SYNC, and optional PRE API SYNC flip-flops,
and the set hold on the DCH SYNC SAVE flip-flop.
BKO(l), BK1(1), andt1 "CAINH produce DCH INX
on drawing KD3(3). The +1 ---CA INH level is the
negation of a special signal generated in devices which
automati cally search, e. g., tape systems. The assertion level would inhibit DCH INX, preventing the CA
increment described here.
The CM STROBE that extracted process word 37 cannot produce another CM STROBE; nevertheless, it
triggers the chain to generate IN ClR and ClR in conjunction with DCH(l) on drawing KC16. IN ClR sets
MBI and ClR sets SAO as for the WC cycle, The core
memory read-half-cycle reads out the address in the
CA register and MEM STROBE retriggers the CM chain.
SAO (1) and MBI(l) gate the address in the CA register
into the MB via the B bus, ADR, and 0 bus. As the
address goes through the ADR, CIl7, resulting from
DCH INX and SAO(l) on drawing KC14, increments
the address by 1 as for the WC cycle.
The incremented address in the MB represents the address of the core memory location from which the data
word is transferred to the device (output transfer), or
to which the data word is transferred from the device
(input transfer). This address is written into the CA
register during the core memory write-half~cycle.
The CM STROBE triggered by MEM STROBE extracts
process word 13. This word contains ARI, CONT, and
CMA16. ARI(l), BKO(l), and BK1(1) produce LIO
on drawing KC13. LIO places the data word from
I/O bus(B) onto the 0 bus, and ARI(l) gates it into
the AR (input transfer). CM STROBE and CONT(l)
retrigger the CM chain to extract process word 16.
This word contains SM and CMA36. SM(l) waits for
the next ClK pulse to start the data cycle(s).
8.2.6 Data Input Cycle
SM(l) and ClK extract process word 36 and start the
core memory cycle. Process word 36 contains DCH
and CMA 17. DCH (l) steps the BK counter to 01 by
resetting BKO, with BK 1 remaining set. 10 SYNC
resets ENA.
The CM STROBE also sets CONT on drawing KC19(1)
in conjunction with the BK count, DCH(l), and WR
RQ to generate another CM STROBE. This next CM
STRO BE then extracts process word 10 (or 11). If the
data word just transferred into memory was the last,
process word 10 transfers the current program address
from the PC to the MB, resuming the interrupted program. If the DCH device flag was again set at the
ClK pulse of the CA cycle, another DCH RQ went to
the I/O control on the 10 SYNC pulse derived from
ClK. Consequently, DCH SYNC(l) occurs at ClK of
the current data cycle and the BK entry word 11 replaces BGN. The DCH break synchronization repeats
for another word transfer.
Ultimately, 10 SYNC following BGN on the last DCH
transfer resets ENB, removing the force SELECT level
from the device's W103. The 10 ClK POS pulse
developed from ClK POS resets BK 1 for a count of
00, and the program resumes on this ClK pulse. DlY
resets DCH SYNC SAVE 400 tJS later in conjunction
with BK1(0). DCH SYNC SAVE(l) has held off any
PI requests at the PROG SY flip-flop in order to give
the optional API requests the priority over the next
break.
8.2.7 Data Output Cycles
For an output transfer, the RD RQ and IOP2 levels
are absent during the CA cycle. Because of this,
ARI(l) of process word 13 merely strobes Os into the
AR, since the I/O bus (B) is disabled. During the data
cycle, the ClR pulse generated by DCH(l) of process
word 36 and CM STROBE sets SAO in addition to IN
ClR setting MBI. Thus, the contents of the addressed
memory location (data word) do get into the MB. The
ARO flip-flop remains reset in the absence of RD RQ,·
so that there is no interference from the Os in the AR.
Also, process word 36 steps the BK count to 01 as for
the input transfer, and BKO, upon resetting, resets
DCH SYNC with the WR RQ condition, drawing KD
3(2). Reset DCH SYNC removes the BK SYNC, INC
+ DCH, and DCH GRANT levels, and releases the
reset hold on the ClK SYNC and optional PRE API
SYNC flip-flops.
In the absence of CONT(l), the CM STROBE car-lnot
produce another CM STROBE; nevertheless, it retriggers the CM chain to generate IN ClR and ClR
in conjunction with DCH(l). IN ClR sets MBI as
usual, but now BKO(O), BK1 (1), and WR RQ on drawing KC 19(3) prevent ClR from setting SAO. Thus,
the STROBE 0-8, 9-17 in core memory reads out the
contents of the addressed memory location, but they
are lost because of reset SAO. The BK count and
RD RQ(B) set the ARO flip-flop. ARO(1) gates the
data word from the AR onto the A bus. The data
word on the A bus goes through the ADR, and NOSH
places it on the 0 bus. MBI(l) gates it into the MB.
MEM STROBE and IAO(O) allow the generation of
another CM STROBE. This CM STROBE extracts process word 17, which contains MBO, DONE, and
next CMA10 (BGN). MBO(l) is used for an output
transfer only. In the input transfer case, it gates the
data word onto the B bus and through the ADR, but the
data word stops there. During this period the core
memory write-half-cycle writes the data word into the
addressed memory location.
8-15
MBO (1) of process word 17 gates the data word onto
the B bus, through the ADR , and onto the I/O bus
(with 10 BUS ON). Process word 17 remains active
throughout the next ClK period, because WR RQ now
prevents CONT from setting. On the 10 ClK POS
pulse, 10 SYNC resets ENA and 10 ClK POS resets
BK 1 as for an input transfer, but the absence of an
SM(l) bit prevents ClK from starting the core memory
and control memory cycles. Thus an idle cycle follows,
during whi ch the data word has time to settle on the
I/O bus and the device has time to strobe the word
into its data register.
As BK 1 resets, it strobes a DCD gate conditioned by
WR RQ on drawing KD3(3) to generate IOP4P. IOP4P
sets the IOP4 flip-flop. IOP4(l) and the force SELECT
level from the W104 (ENB is still set) produce an lOT
XX04 pulse in the device's W103. The device uses
this pulse to strobe the data word from the I/o bus
into its data register.
IOP4(1) also conditions a DCD gate to the 10 RESTART logic on drawing KD3(3). The 10 ClK POS
pulse triggers the 400-ns delay multivibrator B301H22. The Dl Y recovers (Dl Y) to trigger 10 RESTART
400 ns later. 10 RESTART goes to the CM timing
chain to produce a CM STROBE. This CM STROBE
extracts the BGN word (or BK entry word if another
DCH RQ was present) as for an input transfer. Note
that Dl Y also resets 10P4, and DCH SYNC SAVE
as for the input transfer, 10 SYNC derived from the
next ClK pulse resets EN B.
8.2,8 Add-to-Memory Facility
This facility permits incrementing the contents of a
specified memory register (WC register) using one
DCH cycle, or permits the contents of the specified
memory register to be added to the contents of a de,.vice data buffer using all four DCH cycles. A DCH
device can request these actions through the appropriate I/O bus lines.
A device using the INC MB facility is connected to
the DCH in the usual manner. A DCH RQ is initiated
by the device flag, the flag is cleared when the request is granted, and the DCH RQ is removed from
the I/O bus as usual. The device's WC register address is gated onto the 10 ADDR lines by ENA(l)
generated in the W104. The ENA(l) level is used by
the device to issue a ground INC MB level to the I/O
bus. The WC cycle starts on the next ClK pulse after
break entry by setting EN B. DCH INX of process
word 34 in the WC cycle increments the contents of
the addressed memory register as for normal DCH operations. 10 OFlO goes to the devi ce as usual, if the
WC register increments to O. The ground INC MB
level from the device causes the control memory to
extract process word 10 (BGN) on the next CM
STROBE, INC MB and BKO(l) of the break counter
set DONE on this eM STROBE, The next ClK pulse
resets BKO with DONE(l) as the computer reverts to
8-16
the main program, BKO(O) and INC MB reset DCH
SYNC. Reset DCH SYNC removes DCH GRANT so
that the two succeeding 10 SYNC pulses reset ENA
and ENB in the W104. If the device requests another
INC MB break by again raising its flag, one instruction of the main program is executed before the next
break is honored, as the break entry word synchronizes
on the DONE bit of the executed instruction.
A device using the add-to-memory facility is connected to the DCH in the usual manner, A DCH RQ is
initiated by the device flag, the flag is cleared when
the request is granted, and the DCH RQ is removed
from the I/O bus as usual, The device's WC register
address is placed on the 10 ADDR lines by ENA(l)
generated in the W104. The WC cycle starts on the
next ClK pulse after break entry by setting ENB.
EN B(l) causes the devi ce to issue both a RD RQ and
a WR RQ to the I/O control logic.
During the CA cycle, IOP2 gates the device data onto
the I/o bus as usual, and process word 13 gates it
into the AR, During the first data cycle, process word
36 reads the contents of the addressed memory register
into the MB via the Bbus, ADR, and 0 bus. At the
same time, the device data in the AR is gated into the
MB via the A bus, ADR, and 0 bus. An ADD operation therefore takes place in the ADR and the sum is
deposited in the MB. The sum in the MB is later placed
on the I/O bus by process word 17 and may be gated
into the device data buffer with the IOP4 pulse that
occurs during the second data cycle, if desired. Successive add-to-memory DCH breaks can occur if the
device flag is up at ClK time of the current CA cycle.
During ADD, a DATA OFlO occurs when
M B + I/O Bus
> 217_ 1
or
MB
+ I/O Bus < -2
17
DATA OFlO(l) is a 200 j-lS pulse, gated onto the I/O
bus in the middle of the third add-to-memory DCH
cycle, which signals that an incorrect sum has occurred. This happens when the MB and I/O bus are of
I ike signs and their sum has the opposite sign. If the
MB and I/O bus have opposite signs DATA OFlO(l)
cannot occur.
8,3 API CHANNEL TRANSFERS
The 32-channel Automatic Priority Interrupt option
KF09A permits devi ce-initiated data transfers at four
high priority levels and program-initiated data trans-
,
)
core memory address on the I/O bus. The API SYNC
flip-flop in the option will cause a BK SYNC in the
I/O control logic as for DCH transfers. The BK
SYNC causes the control memory to enter the BK process (upon the completion of the current instruction)
as for DC H transfers. The control memory recogn izes
the BK as an API BK, and goes into the XCT instruction process on the next ClK pulse. The XCT process
causes the computer to execute the instruction contained in the core location addressed by the device.
This instruction is usually a JMS to the device service
routine. Service routine exit and return to the main
program is accomplished by a DBR/JMP * instruction.
fers at four lower priority levels. The eight priority
levels take precedence over program interrupt breaks
and the main program. API transfers take place via
the I/O bus as for DCH transfers, The API system
interface contains essentially the same logic as the
DCH, including W103 Device Selectors and Wl04
Multiplexers for each device, plus synchronization
and priority determination logi c within the option.
Up to eight I/O devices can be multiplexed by as
many Wl 04 Multiplexers for operation at the same
level of priority. Among devices on the same level
of priority, the device closest to the I/O bus has
precedence, as fGr DCH transfers.
Since the I/O devices are assigned address locations
independent of priority, the API logic affords three
different methods to change active device priorities
according to the needs of the program. Priority reallocation and determination are discussed in detail
in the KF09A option manual.
Each device is assigned an address in core memory as
for the DCH. Assignments are made independent of
priority levels; a device may be assigned more than
one priority, The four software priority levels command subroutines entered at core memory addresses
00040 through 00043. The remaining locations 00044
through 00077 are assigned to the devi ces themselves.
8.4 TRANSFER PRIORITIES
A device ready flag causes its W104 to issue an interrupt request as for DCH transfers. The interrupt request goes to the API option logic for determination
of priority. If the issuing device has a higher API
priority, the option logic interrupts a lower API interrupt in process, issues an API grant to the higher
priority W104 Multiplexer, and sets a SYNC flip-flop
in the option. The API grant defers requests from all
lower priority devices by disabling their Wl04 multiplexers, and enables the priority device to place its
8-17
The following descending order of interrupt priorities
is established where simultaneous interrupt requests
occur.
DCH
RTC (Optional)
API (Optional)
PI
Main Program
)
.'
CHAPTER 9
ASR-33 TELETYPEWRITER
The Model 33 Automatic Send-Receiver (ASR) Teletypewriter Set, the standard input/output equipment
supplied with the PDP-9/L, has two basic modes of
operation-keyboard/reader and teleprinter/punch.
During the keyboard/reader mode, data is serially
transferred from the teletype keyboard or paper-tape
reader to the PDP-9/l central processor. In the teleprinter/punch mode, the data stored in the PDP-9/L
is serially transferred to the ASR33 for printout on the
teleprinter or punching on paper tape. The data transfer rate is ten characters per second.
gister. The code of a teletype character is loaded into
the TTl so that spaces correspond with binary Os and
holes (marks) correspond to binary 1s. Upon program
command, the content of the TTl is transferred in
parallel to the accumulator.
The ASR33 has a full-duplex and half-duplex interface capability. Full-duplex operation permits the
transfer of data to proceed independently, i. e., data
can be transferred from the keyboard/reader to the
PDP-9/L while different data is being transferred and
recorded on the teleprinter/punch. Half-duplex interface does not permit independent input/output
operati ons.
A keyboard flag is set and causes a program interrupt
request when the 8-bit teletype character has been
assemb Ied in the TTl. The program senses the cond ition of this flag with a KSF instruction and issues a
KRB. This instruction clears the AC and keyboard
flag and transfers the content of the ITI into the AC.
When the teletype tape reader data is to be entered
into the TTl, the control de-energizes a relay in the
teletype unit to release the tape feed latch. When
released, the latch mechanism does not stop tape
moti on until the compl ete character has been sensed.
9. 1.2 Keyboard Control
The information transferred between the PDP-9/l and
ASR33 is assembled for parallel transfer to the accumulator by circuitry within the PDP-9/l I/O. The
control circuitry also provides program flags to enable
program interrupts, program skips, and data transfer.
When data is transferred from the ASR33 keyboard/
reader to the PDP-9/l accumulator, the Teletype-In
(TTl) data path is used in the I/O circuitry. Conversely, the Teletype-Out (TTO) data path is used to
transfer data from the PDP-9/L to the ASR33.
The keyboard control logic is shown on drawing KDll
(1). A simplified functional diagram is shown in Figure
9-2. When a key is pressed on the console, the start
space derived from the keyboard generator results in
a negative TT KBD IN level. (The switch shown at
terminals 3-4 opens.) TT KBD IN and KBD FlG(O)
. TT HD place the solenoid driver output W040-B33S
at -15V, releasing the printer solenoid, and enabling
the printing circuits for simultaneous printout.
The paper tape and reader formats are shown in Figure
9-l.
IT KBD IN becomes a ground level TT KBD IN(B) at
the output of inverter S107-C33R. This ground level
conditions the DCD reset gate at the TTl shift registerls
most significant bit TTlO, Clnd conditions the DCD set
gate at the IT IN ACT flip-flop.
9.1 KEYBOARD/READER
9.1.1 Functional Description (Refer to Figure 9-2)
)
Data from the keyboard and paper reader is transferred
to the PDP-9/L via the keyboard/reader control circuitry. Data transfer is initiated by pressing a key on
the keyboard or with programmed instructions for the
paper tape reader.
The keyboard and tape reader control contains an 8bit TTl shift register which assembles and hol.ds the
code of the last character struck on the keyboard or
read from the tape. Teletype characters from the keyboard are received serially by the 8-bit TTl shift re9-1
The central processor IS 1 .5-l-Is ClK pulses continuously
strobe the DCD gate of IT IN ACT. Once conditioned by the start space, the flip-flop sets on the next
ClK pulse.
IT IN ACT(1) generates a ITI INITlALIZE pulse at
pulse amplifier S603-C39M, starts a TTl ClK, a.nd
disables a ITO ClK on drawing KDll(2). TTl INITIAUZE resets IN LAST UNIT, and sets all TTl register flip-flops (as set TTl represents a "space"). IN
LAST UNIT(O) conditions a DCD gate at the output of
TTl ClK, enabling a TTl lOAD on the next positive
transition of the TTl ClK. This pulse resets TT RDR
RUN to assure that the paper tape does not advance.
The TTl ClK, enabled by TT IN ACT(l), is adjusted
internally to generate pulses at 110 pps after an initial
delay of 4.54 ms. The initio I delay places the pulses
o
3
2
4
5
7
6
at the center of the 9. 09-ms code units for read-in
accuracy. The first TTl ClK pulse strobes the DCD
gate conditioned by IN lAST UNIT(O) to produce
TTl lOAD. TTl lOAD then strobes the input gates
of the TTl register. IT RBD IN(B) produced by the
start space resets TTIO. All other bits remain at 1.
8
9
CHANNEL
B
CHANNEL
6
CHANNEL
4
CHANNEL
2
~
r-"----.
~
~
\10 \11 \12 \13 \14\15\16\ 17
CHANNEL
:3
CHANNEL
CHANNEL
7
UNUSED
5
1
CHANNEL
1
TAPE CHANNEL
B
FIRST LINE READ
CHANNEL
4
~
6
r-"-I
I0 I
5
FEED:3
4
\t
CHANNEL
4
~
6
..-'----,
2
r-"-I
THIRD LINE READ
1
"
CHANNEL
CHANNEL
2
READ BY ONE
lOT INSTRUCTION
SECOND LINE READ
1
CHANNEL
6
1
DIRECTION OF
TAPE MOVEMENT
I
7
CHANNEL
CHANNEL
2
6
CHANNEL
4
r-"-I
r-"-I
~
CHANNEL
r-"-I
2
12 I 3 14 I 5 6 7 I 8 I 9 110 I 11 112 1'3 1 14 115 116 117 1
'--y--'
'--y--'
L...y---'
'-v-'
'---v--'
'----v--'
'-v----'
'-v----'
CHANNEL
CHANNEL
CHANNEL
5
CHANNEL
:3
CHANNEL
1
1
5
CHANNEL
:3
'--y--'
CHANNEL
5
CHANNEL
:3
CHANNEL
1
MUST BE PUNCHED -----,
I
B
DIRECTION OF
TAPE MOVEMENT
1
TAPE CHANNEL
7
6
5
••
•
4
FEED:3
000
000
.0000
000
2
0000 } "'" ""' ""
0000
0000
0000
}
} SECOND LINE READ
BY ONE roT
INSTRUCTION
} THIRD LINE READ
9L-0074
Figure 9-1
Perforated Tape Format
9-2
)
Figure 9-2
Basic I/O Data Transfer, Functional
Diagram
9. 1 .3 Reader Control
Successive TTl lOAD pulses appear synchronously
with successive keyboard character units to serially
shift each mark or space through the TTl register. On
the eighth TTl lOAD, the start space becomes the
least significant bit, TTl7, and the seventh code unit
goes into TTIO. TTl7 (0) conditions the DCD set gates
of the KDB FlG and IN lAST UNIT flip-flops. The
ninth TTl LOAD puts the last code unit into TTlO,
shifts the first into TTl7, and sets KBD FlG and IN
lAST UNIT.
The paper tape reader data is transferred to the PDP9/l in the same manner that keyboard data is transferred. The difference between the tV\{) transfers is
the method of initiating the transfer sequence. For
keyboard operation, depressing a key enables the
transfer of teletype character codes to the TTl shift
register, whi ch in turn, sets the K BD FlG. However,
to initiate paper tape reader operation, the reader
advance relay is activated to pass one line of paper
tape through the reader. The data on the tape is then
coupled to the TTl register as TT KBD IN pulses. As
with keyboard operation, the K BD FlG is set when the
data transfer is complete.
IN LAST UNIT(l) conditions the DCD reset gate of
TT IN ACT and disables the DCD gate at TTl lOAD.
The next TTl ClK pulse cannot issue another TTl
lOAD I but resets TT I N ACT to stop the TTl C lK and
all shifting operations.
To initiate the paper tape data transfer, the PDP-9/L
issues a KRS instruction (700322) to the reader control f
drawi ng KD11 (1). Th i s KRS i nstructi on is decoded
by the Rlll-R002 gate to set the TT RDR RUN flipflop. A set TT RDR RUN grounds the solenoid driver
and activates the ASR33 reader-advance relay. As
the tape passes through the reader, TT KBD IN pulses
are generated, and the sequence described for keyboard operation is repeated. When the transfer of one
line of data is completed, the KBD FlG is set, and a
PROG INT RQ causes a PDP-9/l program interrupt.
Initially I the TTl register was set to ls, producing
TTl FULL. The negative TTl FUll level operates with
TT KBD IN(B) to reset TT IN ACT if a false start space
is created by a noisy keyboard generator. If the noi se
is sufficient, a false TT KBD IN(B) level could set the
TT IN ACT flip-flop, as for a true space, on the next
computer ClK pulse. By the time the first TTl ClK
pulse occurs (4.54 ms) the noise level has disappeared
to remove TT KBD IN(B). TT KBD IN(B) . TTl FUll
causes TT IN ACT to reset on the first TTl ClK pulse.
9.1.4 Data Transfer Instructions
KBD FlG(l) causes a ground PROG INT RQ, drawing
KD 11 (1), at inverter Rlll-D39H. , During keyboard/
reader operation KBI DIS TT RDR is negative because
of reset RDR RUN and RDR FLAG flip-flops. The
PROG INT RQ goes to the I/O control logic, drawing
KD3(2), to cause a program interrupt if the PIE flipflop is set.
During the PDP-9/l program interrupt, a flag search
subroutine is performed to determine what device
caused the interrupt and, upon detection of the device
code, jump to a service routine. The search and service instructions pertaining to the reader;1
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