DL408D_Rev_1_Motorola_8 Bit_MCU_Applications_Manual_1992 DL408D Rev 1 Motorola 8 Bit MCU Applications Manual 1992

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ItIIOTOROLA

a-bit MCU
Applications
Manual
AU products are sold on Motorola's Terms & Condhions 01 Supply. In ordering a product covered by this documenllhe CUSIomar ag_
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2

Preface

This compilation of Application Notes, Engineering Bulletins, Design Concepts, etc.
was originally published by the European Literature Centre of Motorola Ltd. in Milton
Keynes, England, and has subsequently gained worldwide acceptance.
Because of the worldwide popularity of the Application Manuals Series it is important for the reader to take note of the following:
The various Application Notes, Engineering Bulletins, Design Concepts, etc. which
are included were developed at Design Centres strategically located throughout the
global community and many were originally written to support a local need. Whilst
the basic concepts of each of the publications included may have broad global
applicability, specific Motorola semiconductor parts may be referred to that are
currently available for limited distribution in a specific region and may only be
supported by the country of origin of the document in which it is referenced.
Also included in the series for completeness and historical significance are
documents that may no longer be available individually because obsolete devices
are referenced or perhaps, simply, the original document is out of print. Such items
are marked in the Table of Contents, Cross Reference, Abstracts and on the first
page of the document with the letters 'HI' to indicate that these documents are
included for Historical Information only.
All the Application Notes, Engineering Bulletins, Design Concepts, etc. are included
to enhance the user's knowledge and understanding of Motorola's products.
However, before attempting to design-in a device referenced in this Series, the user
should contact the local Motorola supplier or sales office to confirm product
availability and if application support is available.
Thank you.

3

Other books In this series Include:
DL4091D Rev. 1

16/32-bit Applications Manual

DL4101D

Power Applications Manual

DL4111D

Communications Application Manual

DL4121D

Industrial Control Applications Manual

DL413ID

Radio, RF and Video Applications Manual

DL4141D

FET Applications Manual

4

Contents
page
Device Cross Reference ......................................................................................•....••..................................9
Abstracts of Applications Documents ..................................................................•.................................... 13
Applications Documents
AN427
MC68HC11 EEPROM Error Correction Algor~hms in C ......................................................... 21
AN431
AN432
AN433
AN434
AN436
AN440
AN441
AN442
AN446
AN448
AN452
AN459
AN890
AN900

Temperature Measurement and Display Using the MC68HC05B4 and the MCI4489 ........... 33
128K byte Addressing with the M68HCll ............................................................................... 49
TV On-Screen Display Using the MC68HC0,5Tl ..................................................................... 73
Serial Bootstrap for the RAM and EEPROMI of the MC68HC05B6 ....................................... 93
Error Detection and Correction Routines for M68HC05 Devices Containing EEPROM ........ 105
MC68HC805B6 and MC68HC705B5 SeriallParaliel Programming Module .......................... 117
MC68HC05EO EPROM Emulator .......................................................................................... 121
Driving LCDs with M6805 Microprocessors ........................................................................... 153
MCM2814 Gang-Programmer Using an MC68HC805B6 ...................................................... 169
"FLOF" Teletext using M6805 Microcontrollers ..................................................................... 181
Using the MC68HCllK4 Memory Mapping Logic ...................................................•............. 217
A Monitor for the MC68HC05EO ............................................................................................ 229
Low Vottage Inhibit (LVI) Capability of the M6805 HMOS Microcomputer Family HI ••••••••••••• 265
Using the M6805 Family On-Chip 8-Bit AID Converter ..........................•........•..•....•............. 285

AN940
AN974
AN991
AN1010

Telephone Dialling Techniques Using the MC6805 ...........................................•...•............... 305
MC68HCll Floating-Point Package ................................................................•.•................... 323
Using the Serial Peripheral Interface to Communicate Between Muttiple Microcomputers ... 365
MC68HC11 EEPROM Programming from a Personal Computer .......................................... 385

AN1050
AN1055
ANI 057
AN1058
AN1060
ANI 064
AN1065

Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers .............. 399
M6805 16-bit Support Macros ........................................................................•...................... 423
Selecting the Right Microcontroller Unit ................................................................................. 465
Reducing AID Errors in Microcontroller Applications ............................................................. 473
MC68HCll Bootstrap Mode .............•......•.•.....•..................................................................... 485
Use of Stack Simplifies M68HCll Programming .................................................................. 527
Use of the MC68HC68Tl Real-Time Clock with Muttiple Time Bases .................................. 559

AN1066
AN1067
AN1091
AN1097
ANll02

Interfacing the MC68HC05C5 SlOP to an 12C Peripheral ..................................................... 567
Pulse Generation and Detection with Microcontroller Units ................................................... 587
Low Skew Clock Drivers and their System Design Considerations ....................................... 613
Calibration-Free Pressure Sensor System ............................................................................ 619
Interfacing Power MOSFETs to Logic Devices ..................•................................................... 625

AN1120
AN1203
ANE405
ANE418

Basic Servo Loop Motor Control Using the MC68HC05B6 MCU .......................................... 635
A Software Method for Decoding the Output from the MCI4497/MC3373 Combination ...... 643
Bi-Directional Data Transfer Between MC68HCll and MC6805L3 Using SPI HI ••••••••••••••••• 649
MC68HC805B6 Low-Cost EEPROM Microcomputer Programming Module HI ••••••••••••••••••••• 659

ANE420

Monitor Program for the MC68HC05B6 Microcomputer Unit HI ••••••••••••••••••••••••••••••••••••••••••••• 661
Secure Single Chip Microcomputer Manufacture ...•.............................................•................ 683

EB400
EB401
EB404

SCAM Modules for Smart Cards ........................................................................................... 691
"Memories Are Made of This" ... a Look at Memory Considerations for Smart Card
Applications ............................................................................................•..............................693

EB405

Smart Cards: How to Deal Yourself a Winning Hand ............................................................ 705

EB408

MC68HC705T3 Bootloader ...............................................................................•................... 713

Additional Information .......•.......................................................................................................................723

5

6

Device Cross
Reference

7

8

Device Cross Reference
This quick-reference list indicates where specific
components are featured in applications documents
reproduced in this Manual.
MC68HC11A8 ............................ AN1067
MC68HC11A8P1 ....................... AN1065
MC68HC11G5 ........................... AN432
MC68HCll K4 ............................ AN452
MC68HC68T1 ............................ AN1065
MC68HC705B5 .......................... AN440
MC68HC705C8 .......................... ANl 067
MC68HC705T3 .......................... EB408
MC68HC805B6 .......................... AN440
............................................. AN446
............................................. ANE418"'
MC74LS26 ................................. ANll02
MC3373 ..................................... AN1203
MC6805L3 ................................. ANE405 ...
MC6805SC01 ............................ EB401
MC6805SC03 ............................ EB401
MC14489 ................................... AN431
MC14497 ................................... AN1203
MC68705P3 ............................... AN940
MC68705R3 ............................... AN991
MC144ll5 ................................. AN44l
MC144l15P ............................... AN442
MC145000 ................................. AN442
MC145003 ................................. AN442
MC145004 ................................. AN442
MCC68HC05SC11 ..................... EB400
MCC68HC05SC21 ..................... EB400
MCM60L256 .............................. AN441
MCM2814 .................................. AN446
M PM3004 ................................... ANl120
MPX2000 ................................... AN1097
MTP3055E ................................. ANll02
MTP3055EL ............................... ANll02
PCF8573 .................................... AN1066

M68HC05 ................................... AN431
............................................. AN436
............................................. AN442
............................................. AN1203
M68HC05EO .............................. AN459
M68HCll ................................... AN427
............................................. AN432
...... ,...................................... AN1058
............................................. AN1060
............................................. AN1064
............................................. ANll02
............................................. AN1203
M6805 ........................................ AN442
) ............................................. AN1055
MC68HC0584 ............................ AN431
MC68HC05B6 ............................ AN434
............................................. AN1097
............................................. AN1120
............................................. ANE4l8"'
............................................. ANE420"'
MC68HC05C4 ............................ AN991
..................................., ......... AN1067
MC68HC05C5 ............................ AN1 066
MC68HC05EO ............................ AN441
MC68HC05J1 ............................ AN1067
MC68HC05L6 ............................ AN442
MC68HC05SC11 ....................... EB401
MC68HC05SC2l ....................... AN436
............................................. EB401
MC68HC05Tl ............................ AN433
MC68HC05T7 ............................ AN448
MC68HC11 ................................ AN974
............................................. AN1010
............................................. ANE405"'

9

10

Abstracts of
Applications
Documents

11

12

Abstracts
AN436
Error DetectIon and Correction Routines
for M68HC05 DevIces CO{'talnlng EEPROM

AN427
MC68HC11 EEPROM E"or Co"ectlon
Algorithms In C
A modified Hamming code is used to correct one-bit
errors and detect two-bit errors in data blocks of up to 11
bits - avoiding the problem of erroneous correction of
two-bit errors. The technique is implemented entirely in
'C', and additional lunctions are provided to program
and read MC68HCli EEPROM using the encoding/
decoding algorithms.

Applications based on M68HC05 MCUs increasingly
require large amounts 01 critical data to be stored in the
on-ehip EEPROM. This note describes 'HC05 software
routines which allow stored data to be encoded so that
single bit errors in retreived data may be corrected, and
two bit errors detected. The routines use a simple linear
Block Code (Hamming Code) lor encoding the stored
data. They were written originally lor the MC68HC05SC21 Smart Card MPU, but can be modilied easily to run
on any 'HC05 MCU with EEPROM.

AN431
Temperature Measurement and Display
Using the MC68HC05B4 and the MC14489
Shows the basic building blocks 01 a temperature control
system based on the M68HC05 B-series MCUs. Software
routines provided include Look-Up Table Interpolation,
Binary to BCD Conversion, Degrees C to Degrees F
Conversion, and the basis of a real-time counter/clock.
Uses a thermistor as the sensing element to allow easy
interfacing to the AID converter 01 the MC68HC05B4,
but the software principles are easily adapted to other
sensors.

AN440
MC68HC805B6 and MC68HC705B5
SerIal/Parallel ProgrammIng Module
The MC68HC05B seriallparallel programmer module
allows the user to program MC68HC805B6 and
MC68HC705B5 MCUs. This note describes its various
operating modes, and gives details 01 its construction
and use. Includes circuit diagram and parts list.

AN441
AN432

128K byte Addressing with the M68HC11

MC68HC05EO EPROM Emulator

Unlike other members 01 the M6805 family, the
MC68HC05EO has no on-chip !,!OM but can address a
lul164K bytes 01 external memory; the external memory
may be ROM, EPROM, RAM and/or additional hardware. This EPROM emulator illustrates a typical use 01
this type 01 MCU; ~ includes a keyboard, LCD, serial
communication and 64K of paged RAM. It can replace
with RAM the program ROM or EPROM in a target
system through a cable connection to the system's
EPROM socket, and can be used to debug and mod~y
the target system software. Includes an assembled
listing 01 the emulator control program.

The 64Kbytedirect addressing capabilityofthe M68HCli
family is insuflicient for some applications. This note
describes two methods 01 memory paging - one software only, the other hardware plus software - that allow
the MCU to address a 1Mbit EPROM (128K bytes) by
manipulation 01 the address lines. The two methods
illustrate the concept of paging and the inherent compromises; the technique may be expanded to other memory
combinations. Includes full software listings.

AN433
TV On-Screen Display Using the
MC68HC05T1

AN442
Driving LCDs with 146805
MIcroprocessors

The T -series devices in the M68HC05 MCU Family
provide a convenient and cost-effective means of adding On Screen Display capability (OSD) to TVs and
VCRs. The MC68HC05Tl is atthecentreofthe T-series
price/performance range, and is used in this example.
Full software listings are provided lor a ROM-efficient
implementation of an 8-row by 16-character display,
including Programme Change, Channel Mode, Automatic Search, Analogues and Channel Name.

The MC68HC05L series 01 MCUs include circuitry lor
direct LCD drive. Other MCUs in the M6805 and
M68HC051amilies have a variety 01110 and display drive
capabilities. This comprehensive note describes alternative LCD drive arrangements lor applications with
different numbers 01 backplanes and display drive capabilities, including software-based and display driver chip
solutions. Circuits and software listings are provided.
The techniques apply equally to other MCU lamilies
such as the M6801 and M68HCll.

AN434
Serial Bootstrap for the RAM and
EEPROM1 of the MC68HC05B6
The MC68HC05B6 has 256 bytes of on-chip EEPROM,
called EEPROM 1, which can be used lor non-volatile
data storage. In many applications EEPROMI stores a,
look-up table or system set-up variables - in these cases
it is necessary to initialise the memory during system
manufacture. The RAM bootstrap program in the 'B6
mask ROM uses a simple protocol in order to save ROM
space, and cannot accept the S-records that are the
normal assembler output. This note explains how to
convert assembler output to the 'B6 bootstrap lormat,
and how to bootstrap data into EEPROMI.

AN446
MCM2814 Gang-Programmer UsIng an
MC68HC805B6
Non-volatile memories (NVM) such as the MCM2814
are widely used in consumer equipment such as television receivers to store semi-permanent, user-delined
inlormation. They may also contain data such asoptimum
sound and picture settings. In a production environment,
the initial loading 01 this data can be achieved quickly by
copyi'1g an existing NVM. This note describes a programmer based on an MC68HC805B6 which in four

13

Abstracts (continued)
AN940
Telephone Dialling Techniques Using the
MC6805

seconds can fully program eight MCM2814s in parallel
and verify them individually.

Intelligent telephones are increasing in popularity MCUs from the versatile M6805 family make ideal
controllers. This demonstration board, based on an
MC68705P3 single-chip MCU, shows two cost-effective
methods of DTMF and pulse-type dialling. Full hardware
schematic and software listings included.

AN448
"FLOF" Teletext using M6805
Mlcrocontrollers
The "-1" members of Motorola's M68HC05 MCU family
provide a cost-effective method of adding On Screen
Display (OSD) to TVs and VCRs. This note describes an
example of Full Level One Feature (FLOF) Teletext
control software written for the MC68HC0517 to control
type 5243 Teletext chips. Around 3K bytes of ROM are
used, allowing the code to fit with tuning, OSO and
stereo functions into the 7. 9K bytes olthe MC68HC0517.
The example software includes the Spanish implementation of Packet 26; Packet 26 allows for the substitution
of specific characters for a particular country.

AN974

AN452
Using the MC68HC11K4 Memory
Mapping Logic

AN991
Using the Serial Peripheral Interface to
Communicate Between Multiple
Microcomputers

The MC68HC11 K4 includes memory expansion logic
which allQws the 64 KByte addressing range of the
M68HC11 CPU to be extended to more than 1 MByte.
This note discusses the operation of this logic and
provides examples of memory maps and possible hardware configurations.

AN459

MC68HC11 Roatlng-Polnt Package

While most MC68HC11 applications can be implemented
using 16-bit integer precision, certain algorithms may be
difficult or impossible without floating-point. .This application note details an efficient floating-point package
that includes basic trig functions and square root in
addition to add, subtract, multiply and divide. It requires
just over 2k bytes of memory, with only 10 bytes of page
zero RAM in addition to stack RAM.

Communication between multiple processors can be
difficult when' different types are used. Orfe solution is
the SPI, an interface intended for communication between ICs on the same board. It can be implemented in
software, allowing communication between two MCUs
where one has SPI hardware and the other does not.
Costly expansion buses and UARTs are eliminated.
The scheme is illustrated with a temperaturellimedisplay
circuit using an MC68HC05C4 and an MC68705R3.

A Monitor for the MC68HC05EO

Development systems for single-chip MCUs can be
complex and relatively expensive. This d'an dissuade
potential users from designing them into new applications. This note describes a simple "entry level" development system suitable for debugging hardware and
software for the M6805 family of microprocessors. Includes full descriptions, circuit diagram and a listing of
the monitor software.

AN1010 MC68HC11 EEPROM Programming from
a Personal Computer
Describes a simple and reliable method of programming
the MC68HC11's internal EEPROM (or EEPROM connected to its external bus) by downloading data in
Motorola S-record format from a standard personal
computer (PC) fitted with a serial communications port.
Includes BASIC program for the PC (to Program External EEPROMlRAM, Program Internal EEPROM, or Verify
internal or External EEPROMIRAM) and the source
listing of MC68HC11 code for downloading to RAM to
receive S records.

AN890
Low Voltage Inhibit (L VI) Capability
of the M6805 HMOS Microcomputer (MCU)
Family

HI
The LVI option provides a cost effective means for the
MCU to sense a drop in supply voltage and then shut
itself down in well-defined manner. Because the option
does not require any additional external parts it provides
an overall product cost reduction. The LVI option is
provided at the time of manufacture by on-chip circuitry
contained in part of the user's ROM pattern. This
application note includes an LVI schematic diagram as
well as a'listing of the monitor and self-check programs.

AN10SO Designing for Electromagnetic
Compatibility (EMC) with HCMOS
Mlcrocontrollers
As the operating speeds of the latest HCMOS devices
increase, the MCU system designer must take more
account of the electromagnetic compatibility (EMC) of
the finished product. This discussion relates mainly to
emission control, but most of the techniques also reduce
electromagnetic susceptibility. Subjects include Legal
Requirements, RFI Problems, types of radiation, Supply
Decoupling, Grounding Techniques and PCB Layouts.
Incorporates an' article reprint from EMC Technology
describing an EMIIRFI diagnostic probe.

AN900
Using the M6805 Family On-Chip 8-Blt AI
DConverter
Factors which should be considered when using on-chip
analog-to-digital (AID) converters are covered. The
pertinent circuit elements and terminology are defined
and a self-test hardware/software technique is illustrated. An example on how to manipulate the converted
analog data from a temperature sensor is given. It is
il)tende= S

The advantage of this method, where the check bits are
interspersed in a binary manner throughout the code
word, is that the error position can be calculated algorithmically.

One way to solve for k is to just select values of k starting
at say, 1 and evaluating until the bound is reached. This
method is implemented algorithmically in function InitEncodeO in module HAMMING.C

An important point to note is that the parity check matrix
described above generates Hamming distance-3 codes,
which means that 2 errors will cause erroneous correction. This can be fixed by adding an extra parity check bit,
C5, which is the modul0-2 addition of all data and check
bits together.

For m=8, the solution is k=4. Note thatthis value exceeds
the H~mming bound, which means that additional data
bits can be added to the bit stream, thus increasing the
efficiency of the code. In fact, the maximum number of
data bits is 11 in this case.
3. A Parity matrix, H is created from a 'horizontally orientated' binary table.The number of columns (b1 to b12) in
the matrix correspond to the total number of data and
check bits, and the number of rows (r1 to r4) to the
number of check bits.

i.e.CS-C1+C2+01+C3+02+03+04+C4+0S+D6+07+0S
The code word then becomes:

C1 C2 01 C3 02 03 04 C4 OS 06 07 OS CS

i.e. b1 b2 b3 b4 bS b6 b7 bS b9 b10 bll b12
r1
1 0 1 a 1 a 1 a 1
a 1 a
r2
a 1 1 a a 1 1 a a 1 1 a
r3
a a a 1 1 1 1 a a a a 1
r4
a a a a a a a 1 1 1 1 1

To determine if an uncorrectable error has occurred (i.e.
2 errors) in the received word, the extra parity bit is
tested. If the syndrome is non-zero and the parity bit is
wrong, then a correctable error has occurred. If the syndrome is non-zero and the parity bit is correct, then an
uncorrectable error has occurred.

Because the H matrix in this form, is simply a truncated
4 bit binary table, it can easily be generated algorithmically.

EFFICIENCY
The following table lists the relative efficiencies of this
algorithm, against data size.

4. The position of all the check bits (C1 to C4) within the
encoded word is the position of the single 1s in the
columns of H. The remaining bits correspond to the data
bits (01 to OSI.
iae. C1 C2 01 C3 02 03 04 C4 OS

1

a

1
1

a 1 a
a a 1

1
1
1

a 1
a a a 1 1 1
a a a a a a a

a 1
a a
a a

1

1

C1-01+02+04+0S+07
C2-01+03+04+06+07
C3-02+03+04+0S
C4-0S+06+07+0S

Data bits
1
2
3
4
5

06 07 OS
a 1 a
1 1 a
a a 1
1 1 1

6
7
S
9·
10
11

5. Each check bit is generated by taking each row of H in
turn, and modul0-2 adding all bits with a 1 in them except
the check bit positions.

22

Encoded bits Efficiency %
4

25

6
7

33

S
10
11
12
13
14
15
16

43
50
50
55
58
62
64
67
69

The implementation of the above techniques are given in
the module HAMMING.C.

the required new data size. The global variables used by
all the encoding, decoding and EEPROM programming
and reading functions are automatically updated. This
anows the encoding and error correction process to be
virtually transparent to the user. In addition, the functions
 and  will automatically increment the
address pointer by the correct encoded data size set up
by . This simplifies the structure of loops to
program and read back data. Example code is provided in
module EECOR1.C.

In order to maintain orthogonality in the EEPROM algo.rithms, the encoded data used by the functions in module
EEPROG.C are forced to either 1 byte or 2 byte (word)
sizes. This also eliminates the complexities of packing
and unpacking data in partially filled bytes.

CONCLUSIONS

The encoding and decoding algorithms listed here may
be applied to other forms of data, such as that used in
serial communications, or for parallel data transfers.

In this application note, the encoding algorithm's generator matrix is the same as the parity check matrix.
The C functions  and  in the module
HAMMING.C return a status value - 0, 1 or 2 - which
indicates whether the data has no errors, 1 corrected
error, or 2 erroneously corrected errors. This means that
if the status value is 0 or 1, then the data can be assumed
good. If the status value is 2, then the data will be bad.

By incorporating the error correction or detection-only
schemes described in this application note, the integrity
of data storage and transfer can be greatly improved. The
impact on EEPROM usage is to increase its effective reliability and extend its useful life beyond the manufacturers' guaranteed specifications.

Altematively the functions can be used for error detection
only, without correction. In this case, a status value of 1
corresponds tb.either 1 or 3 bit errors, while a status value
of 2 indicates that 2 bit errors have occurred.

REFERENCES
[1) Carlson, 'Communication Systems', Chapter 9,
McGraw-Hili.

By using the C functions listed in this application note, the
encoded data size can easily be chsnged dynamically. To
do this, the function  must be called with

[21

23

Harman, 'Principles of the Statistical Theory of Communication', Chapter 5, McGraw-Hili

MODULE EECOR1.C;:
\

.

.

Tests EEPROM error detection using a modified hamming encoding scheme.
typedef unlligned char byte;
typedef'unsigned int word;

/* Global variables used by main 0 *f

byte *,ee aqd.r, * start addr, *end addr, i, Error;
word dat~;
,

/***********************~**********~****~~********************************~**/

/* External global variables
extern byte CodeSize;

*i

1*

number of bits in encoded data *1

1* External Functions,*,!
extern, byte, read{word *data,byte *'*addr);
1* Function returns ,error status *1
extern byte write (wqrd data,byte **'addr);
1* ~'
1* Table of Status returned by read and write functions
'Returned Status
Condition
,
0
No errors detected or corrected.
1
One error detected and corrected.
2
Two errors detected, but correction is erroneous.
Notes:
II When the returned value is 2, the function  will returned a bad value in variable
 due to the inability to correctly correct two errors.  also automatically increments
the address pointer passed to it, to the next memory space. The incremented value takes into
account the actu!!'l size of the encoded data. i.e. either 1 or 2 byte increment.

21 Function  also performs a read to update and return an error status. This gives an
immediate indication of whether the write was successful.  also automatically increments
the address pointer passed to it, to the next free memory space. The incremented value tak.!s into
account the actual size of the encoded data. i.e. either 1 or 2 byte increment.

*1
/***************************************************************************/

int mainO
(

CodeSize=InitEncode(11);

1* Get code size (less 1) needed
1* by 11 data bits

*1
*1

ee_addr=(byte *)Oxb600;
for (i=l;i<-Oxl0;i++)
Error=write(Ox7ff,&ee_addr);

1* Initialise 'EEPROM start address
1* and 'erase' EEPROM
1* Function successful if Error<>2

*1
*1
*1

ee_addr= (byte *) Oxb600;

1* Reset EEPROM address

*1

Error=write(Ox5aa,&ee addr);
Error=write(0x255,&ee=addr);

1* Write Ox5aa & increment ee addr
1* Write Ox255 at next available address

*1
*1

CodeSize=InitEncode(4);

1* Change number of data bits to
1* Save start address for this data

*1
*1

1* Program 'walking

*1

start_ addr=ee_ addr;

for (i-I; i good if Error=O or 1

*/
*/

I 1* main *1

24

Is~

MODULE HAMMING.C
I*Modules to Generate hamming codes of distance 4, for data sizes in the range 1 bit to 11 bits.
The upper bound is limited by the encoded word type bit range (16 bits) .
Corrects 1 bit error in any position (check or data), and detects 2 bit errors in any position.
After execution of the  function, the global variable  is updated to indicate
level of error correction.
ErrFlag

i.e.

o

1
2

Condition
No errors detected or corrected.
One error detected and corrected.
Two errors detected, but correction is erroneous.

Note that when ErrFlag is 2, function  will return a bad value, due to its inability to
correctly correct two errors.

*1
'define
'define
typedef
typedef

TRIlE 1
FALSE 0
unsigned char byte;
unsigned int word;

byte DataSize,CodeSize,EncodedWord,ErrFlag;

1* Function prototypes *1
byte
word
byte
word
word
word

OcIdParity(word Code);
Power2(byte e);
InitEncode(byte DataLength);
MakeCheck(word Data);
Encode(word Data);
Decode(word Code);

byte OddParity(Code)
word Code;

1*
Returns TRUE if Code is odd parity, otherwise returns FALSE

*1
byte p;
p-TRUE;

while (Code!-O)
(

if (Code & 1) p-!p;
Code>>-1;
return(p) ;
word Power2 (e)
byte e;

1*
Returns 2 A e

*1
(

word P2;
signed char i;
P2-1;
if «signed char) (e). This value also updates global variable .
i.e. finds the minimum solution of (k+m) for the inequality:
2 A k 2: k + m + 1
In addition, updates global variable  to reflect number of bytes
per encoded data.  will be either 0 or 1.

*1

byte CheckLength,i;
DataSize-DataLength; /* DataSize used by other functions in this module .*/
CheckLength-l;
while «Power2(CheckLength)-CheckLength-1)
and . The H parity matrix is generated by a simple for loop.
*/

byte i,H,CheckSize,CheckVa1ue,Check,CheckMask;
word DataMask;
Check-O;
CheckMask=1;
CheckSize=CodeSize-DataSize;
for (i-l;i<-CheckSize;i++)
{

CheckValue-FALSE;
DataMask-1;
for (H=l;H<-CodeSize;H++)
{

if «Ox8000 % H) !=O)

1* Column with single bit set

(

i f C(H

& CheckMask)! =0)
CheckVa1ue A -«DataMask & Data)!-O~;
DataMask«-l;

i f (CheckValue) Check I =CheckMask;
CheckMask«=1;

return (Check) ;

26

*1

word Encode (Data)
word Data;
/*
Returns an encoded word, consisting of the check bits
concatenated on to the most significant bit of .
A single odd parity bit is concatenated on to the Encoded word to
increase the hamming bound from 3 to 4, and provide 2 bit error
detection as well as 1 bit correction.
Uses global variables  and  to determine the
concatenating positions.
*/
word Code;
Code=Data I (MakeCheck(Data)<.
Uses global variable  to determine position of the
check bits in .
Updates global variable  to indicate error status i.e.:
ErrFlag
Status
o
No errors found
1
Single error corrected
2
Double error - invalid correction
*/
word ParityBit,Data,Check,ErrorCheck,Syndrome,DataMask;
byte DataPos,CheckSize,CheckPos,H,DataBit;
ErrFlag-O;
ParityBit-COde & Power2(CodeSize);
DataMask-Power2(DataSize)-1;
Data-Code & DataMask;
CheckSize-CodeSize-DataSize;
Check-(Code»DataSize) & (Power2(CheckSize)-1);
ErrorCheck=MakeCheck(Data);
Syndrome=Check A ErrorCheck;
if (Syndrome>O) ErrFlag++;
H=O;
DataPos=O;
CheckPos=DataSize;
DataBit=TRUE;
while «H!=Syndrome)

&

(DataPos and  functions to encode and decode data
formatted by modified hanmi.ng scheme.

*1
'include 
.define regbase (*(struct HCllIO *) OxlOOO)
'define
.define
typedef
typedef

eras Oxl6
writ Ox02
unsigned chaJi byte;
unsigned int word;

union twobytes
{

word w:
byte b[2];
} udata;

1* Word stored as MSB,LSB

*1

extern byte EncodedWord,ErrFlag;

1* Function prototypes * 1
extern word Encode (word Data);
extern word Decode (word Code);
void
void
void
byte
byte

delay(word count);
eeprog(byte val,byte byt,byte *addr,word count);
program(byte byt,byte *addr);
read (word *data,byte **addr);
write(word data,byte **addr);

void delay(count)
word count;
{

1* Set timeout period on OCl and
1* clear any pending OCl flag.
1* Wait for timeout flag.

regbase.TOCI-regbase.TCNT+count;
regbase.TFLGI-Ox80;
do;while «regbase.TFLGI , Ox80)-O);

void
byte
byte
byte
word

eeprog (val, byt. addr, connt)
val;
byt;
*addr;
count;

*1
*1
*1

1*· val determines Erase or Write operation
*/
/* byt is byte to be progrlUlllllld
*1
1* addr i . address of encoded byte in EEPROM *1
1* count is number of E clock delays
*1

{

1* Enable address/data latches

regbase.PPROG-val;
*addr-byt;
++regbase.PPROG;
i f (count,
1* and return ErJ:Flag

*1
*1

1*
1*
1*
1*

*1
*1
*1
*1

byte write(data,addr)
word data;
byte **addr;
(

byte *oldaddr;
·udata. _Encode (data) ;
oldaddr-*addr;
proqram(udata.b{l), (*addrl++);
if (EncodedWord)
program(udata.b[O), (*addr)++);
return(read(&udata.w,&oldaddr));

Encode data.
Save initial address for verification.
Program LSB first to allow for either
1 or 2 byte encoded data
1* MSB of word sized data,& inc address
1* Return  to calling seglllent

29

*1

*1

HC11REG.H
/*

HCll structure - I/O registers for MC68HCll */

struct HCllIO {
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
c

/*

PORTCL;

/*
/*
/*
/*

Parallel I/O control
Port C */
Port B - Output only
Alternate port C latch

Reservedl;
OORC;
PORTO;
OORD;
PORTE;

/*
/*
/*
/*

Data
Port
Data
Port

/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*

Compare force
Ocl mask
Ocl data
Timer counter
Input capture 1
Input capture 2
Input capture 3
Output compare 1
Output compare 2
Output compare 3
Output COl!plre 4
Output col!plre 5
Timer control register 1
Timer control register 2
Main timer interrupt mask
Main timer interrupt flag
Main timer interrupt mask
Main timer interrupt flag

c

*/

c,

*/

*1
*1

c

po~C

*1

direction for port 0

*/
*/

E

*/

direction for
0

Timer Section */

unsigned char

~signed char

unsigned
int
int
int
int
int
int
int
int
int
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned

/*

/* Port A - 3 input only. 5 Out;put o~iy

PORTA;
Reserved;
PIOC;
PORTe;
PORTS;

char

CFORC;
OClM;
OClO;
TCNT;

TICl;
TIC2;
TIC3;
TOCl;
TOC2;
TOC3;
'i'oc;::4;

TOCS;
char
char
char
char
char
char

TCT~l;

TCTL2;
TMSK1;
TFLGl;
TMSK2;
TFLG2;

/*

/*
/*
/*
/*

*/
*/

*/

*/

*1

"/

*1

*/
*/
*/

,*1
*1
*/

c

1
1
2
2

*1
*1

*/

*/

*1

Pulse Accumulator Timer Control */

unsigned char
unsigned char

/* Pulse Acc control
/* Pulse Acc count

PACTL;

PACNT;

30

*/
*/

/*

SPI registers */

unsigned char
unsigned char
unsigned char
/*

char
char
char
char
char

BAUD;
SCCRl;
SCCR2;
SCSR;
SCDR;

ADCTL;

ADR[4];

adrl
adr2
adr3
adr4

unsigned char

*/
*/
*/
*/
*/

/* AD control register
/* Array of AD result registers

*/
*/

/* Reserved for A to D expansion

*/

/* System configuration options
/* ADn/Reset COP timer circuitry
/* EEPROM programming control reg
/* Highest priority i-bit int , misc
/* RAM - I/O mapping register
/* Factory TEST control register
/* EEPROM cell - COP,ROM,' EEPROM en

*/
*/
*/
*/

SCI
SCI
SCI
SCI
SCI

ADR[O]
ADR[l]
ADR[2]
ADR[3]

Rsrv[4] ;

System Configuration */

unsigned
unsigned
unsigned
unsigned
unsigned
unsigned
unsigned

char
char
char
char
char
char
char

OPTION;
COPRST;
PPROG;
HPRIO;
INIT;
TESTl;
CONFIG;

};
/*

baud rate control
control register 1
control register 2
status register
register
data

/*
/*
/*
/*
/*

Define each result register */

itdefine
itdefine
itdefine
itdefine

/*

*/
*/
*/

A to D registers */

unsigned char
unsigned char
/*

/* SPI control register
/* SPI status register
register
/* SPI data

SCI registers */

unsigned
unsigned
unsigned
unsigned
un·signed
/*

SPCR;
SPSR;
SPDR;

End of structure HCll */

31

*/

*/
*/

32

AN431
Temperature measurement and display
using the MC68HC05B4 and the MC14489
By Jeff Wright.
Motorola Ltd.• East, Kilbride

INTRODUCTION

TEMPERATURE MEASUREMENT

This application note is intended to show the basic
building blocks of a temperature control system based
on the MC68HC05Bx family of MCUs. Software routines
in the application include look-up table interpolation,
binary to BCD conversion, DegC to DegF conversion and
the' basis of a real time counter/clock. For temperature
display the Multi-character LED display driver MC14489
is used, driven from the B4's SCI, resulting in simple
hardware with a low component count. The temperature
sensing element used here is a thermistor to allow easy
interfacing to the NO converter of the HC05B4, but the
software principles shown would be the same for many
other types of sensors. A software listing is included at
the{lnd of this application note.

A pre-calibrated thermisto,r was chosen as the
temperature sensing element. Its characteristic curve
over the temperature range of -40 to 80°C is shown in
Figure 1. To get the best accuracy from the HC05B4's
on-board AID, the input signal shbuld be scaled to use
as much of the available VRH-VRL range as possible.
Here VRH is connected to Vdd and VRL is tied to Vss.
In this case, using the thermistor as potential divider
with a 201dl resistor results in a signal range of
approximately 0.3V to 4.7V over the -40 to 80°C
~emperature range The voltage across the thermistor
(input to the NO), plotted against temperature, is
shown in Figure 2.

Resistance (K )
350
325
300
275

1\
\

1\

\

\
'\

"

I.........

250
225
200
175
150
125
100
75
"0

~

-f-

10
-40

-30

-20

-10

o

10

20

30

40

50

60

70

80

Temperature (OC)
Figurl! 1, Thermistor resistance vs Temperature

33

VAID (V)
,---,----r-----,-,---.-----,-~.O ,.-...,.-,--,,---.,--,----,,---.,---,-----.-T"l

f-1""'--T='""-k::-+--+--+--l---l4.S +--+--+--+--+--+-+--+--l-+--+I

r-r---..

r-~-+--~-F~--+--44

AID

1'-.....

r-~~--+-~~~~~3.Sr-1-~--+--r~r-~-+--r-1---H

input

~~~r-~~~i'~~+-+-+-+-+-+-+-~~
'",

2.S

.........

r-+--r-;-+--r-;~2. ~~-+-~'~--+--r-4-~~-+I

.........

r-+--r-;-+--r-;~1.Sr-i--t~~i--t~~+--r-i--tL---------~

r---.. . . . . .

1----11----11----1!--1----11----1---11

-40

-30

-20

o

-10

10.

20

30

40

so

60

70

Figure 2. AID input voltage vs Temperature (inset: circuit used)

As can be seen from Figure 2, the response is non-linear
and so a look-up table approach is the simplest way of
obtaining the required accuracy. The thermistor characteristics are stored as aseries of points in a table in ROM
and a linear interpolation between adjacent points is
used to obtain the temperature that corresponds to a
given ND reading. The number of points that must be
storep depends on how non-linear the response is and
the required accuracy of the result. In this case 16 points
were chosen; in order to keep the software simple (and

therefore fast), they are spread at intervals of 16 through
the AID result range of 0-255. For each point (16, 32, 48
etc.), the voltage on the AID input was calculated and
the corresponding temperature was obtained from the
graph of Figure 2. These points were then used to form
the look-up table shown in Figure 3, resulting in a temperature range of -40 to 79°C. Figure 4 shows the reconstructed response of the thermistor obtained by linear
interpolation of the points in the look-up table.

AID RESULT AID (volts) TEMP (0C) TEMP (OC 2s Campi)
0
16
32
48
64
80
96
112
128
144
160
176
192
208
224
240
255

0
0.31
0.63
0.94
1.26
1.57
1.88
2.20
2.51
2.82
3.14
3.45
3.77
4.08
4.39
4.71
5.0

-

-

79
56
43
34
27
21
15
10
5
-1
-6
-11
-18
-26
-40

4F
38
2B
22
1B
15
OF
OA
05
FF
FA
F5
EE
E6
08

-

-

Figure 3. Interpolated AID input voltage vs Temperature

34

VAID (V)
5.0

---

4.5

r--- r--..... fI'-.a I'.....

4

..

3.5

~
2.5

'),

r--....
...........

2
1.5

~

~ .....
~

1

...........
~

0.5

r- r--

0
·40

·30

·20

·10

o

10

20

30

40

50

- .......

60

70

Figure 4. Interpolated AID input voltage vs Temperature

The temperature reading is updated every second; the
software to accomplish this is relatively simple:
The timer is set to overflow every 125 mS with a 4.1934
MHz crystal. The timer overflow interrupt routine updates the real time counters TICKS, SECS, MINS & HRS
and sets the flag bit SEC every time a second has
elapsed.
The main program loop is executed every second (via
the SEC flag bit) and after checking the metric/imperial
selector switch the temperature is measured by the
subroutine AOCONV. This routine starts by reading the
thermistor selector switch and setting up the NO control register accordingly. An NO conversion is then carried out four times on the selected channel and the
results accumulated in the accumulator and the temporary register TEMP. This result is then divided by 4 by
rotating, to obtain the average NO result. The averaging
technique is employed to try and reduce the effect of
noise on the NO input. The number of conversions to
average is determined by time constraints and the noise
levels in'the surrounding environment. The upper nibble
of the result is then used to access the look-up table to
obtain the 'base' temperature value. If the temperature
limit is exceeded then the TLiMIT flag is set before
exiting from the routine.

35

Temperature table entries are stored in 2's complement
form so that the interpolation between positive and
negative values will work successfully. The interpolation is carried out by obtaining the difference between
the base value and the next in the table, multiplying this
by the lower nibble ofthe NO result and then dividing by
16. This result is then subtracted from the base value to
obtain the real temperature in 2's complement °C which
is stored in the register NEWTMP before exiting from
the routine. The difference information is subtracted
from the base value rather than added because the
thermistor has a negative temperature co-efficient
(NTC) so that an increase in the NO result corresponds
to a drop in temperature.
If the imperial mode is selected (OF) then the next stage
before updating the display is to convert from °c to OF
and this is carried out in the subroutine CTOF.
Converting from °C to OF is accomplished by multiplying
by 1.8 and adding 32. First the sign of the temperature
in °C is stored via the flag bit NEGNUM, then the
maximum OF limit (53°C) is checked before the magnitude is multiplied by 1.8 (multiply by 115 and divide by
64). Again, use is made of rotating to do the dividing, in
order to increase execution speed. The sign of the result
is then restored and 32 added to obtain the temperature
in 2's complement OF.

TEMPERATURE DISPLAY
Figures 5a and 5b show the 14489 data format and the
corresponding bit positions in the B4 registers DISP1,
2, 3 & C. The sign of the temperature is restored and
the numeric display registers are configured to display
'-' if the temperature limit has been exceeded before
exiting from the SETDISP routine.

An MCl4489 multi-character display driver was chosen for this purpose as it can be easily interfaced to a
wide range of Motorola MCUs, requires almost no
external components and has a character set that
includes the degree symbol (0). The MCl4489 can also
be cascaded if the application was expanded to require
a 'Iarger display. The MCl4489 would normally be
driven from an SPI on the MCU but here, since the the
68HC05B family does not have an SPI, use is made of
the SCI clock output feature that is available on this
family.

The main program loop then calls the subroutine
DISPL which actually transmits the contents of the
display registers to the MCl4489 via the SCI. The
MCl4489 contains special Bit Grabber circuitry that
allows either the internal display registers or the configuration register to be updated without address or
steering bits so that updating the display involves a
simple transmission of either 3 bytes for the display
registers or 1 byte for the configuration register. Even
for cascaded 14489s there is no need for address bits
- see the MCl4489 data sheet for more details.

Before the temperature can be written to the display
driver it has to be converted into the correct data
format.
The first stage of this is to convert from 2's complement binary to BCD. This is carried out in the routine
CONBCD which is called from SETDISP. The sign of
the temperature is stored in the flag bit NEGNUM
before SETDISP is called; then, after first checking if
the TLIMIT flag is set, the temperature is converted to
BCD in DEC()'Zby CONBCD. This is accomplished by
rotating left the binary number followed immediately
by a rotate left of the BCD result; this has the effect of
multiplying the current BCD result by 2 and adding in
the new binary bit at the same time. After each rotate
the BCD registers are checked and adjusted for overflow (>$09) before the bit counter contained in the
index register is decremented. This process of rotate
then adjust is continued until all the binary bits have
been used; the BCD result will then be resident in the
registers DECO, 1 & 2.

The MC 14489 can be clocked at up to 4 MHz 'at 5 volts
so here the maximum transmit baud rate of the SCI is
used-131.072 KHz with a 4.19304 MHz crystal. The
transmission of the display data only takes place if
there has been a change in the data since the last time.
If there has been a change, the 3 data registerS are
transmitted in turn starting with DISP3 and the OLD
registers are updated ready for the change check next
time round. After the last byte has gone. the SCI and
14489 are disabled before returning to the main loop.
The last subroutine called from the main program is
the 14489 configuration update routine DISCON. This
routine operates in a similar manner to DISPL. checking to see if there has been a change to the config .. data
. before transmitting it.

The rest of the routine SETDISP is concerned with
setting up the display registers DISP1, 2, 3 and the
display control register DISPC. The MC14489 data
format is msb first whereas the 68HC05B4 SCI transmits Isb first; this means that the bit order of the data
stream has to be stored in reverse in the display
registers. This can be confusing when trying to work
out the codes that have to be stored in the B4 to
generate a specific character.

This completes the operation of the program which
now jumps back to the start of the main loop and waits
for the SEC bit to be set again before repeating the
temperature measurement and display sequence.

Isb

msb
C7

C6

l

C5

C4 1 C3.1 C2

l

Cl

MCl4489 configuration data

CO

l

I DCO 1 DCl I DC2 I DC3 I DC4 I DC5 I DC6 I DC7 1
Isb

MC68HC05B4 display register DISPC

msb

Figure Sa. MC14489 to MC68HC05B4 display register mapping

36

MC 14489 display data

msb

19b

DISP3

msb 19b

DISP2

msb 19b

19b

DISP1

msb

Display registers on MC68HC05B4

Figure Sb. MC14489 to MC68HCOSB4 display register mappinp

HARDWARE

Asalready mentioned, the use ofthe MCl4489 results
in a very low component count for the application; the
hardware schematic can be seen in Figure 6. The only
I/O pins required are for reading the option switches
and for controlling the enable of the MC14489. PuUdowns are required on the clock and data pins as these
become high impedance when the SCt is disabled.
The LED displays are common cathode; a single external resistor is aU that is required to set the brightness

level of the displays. In this case though, a light
dependent resistor, R12 (ORP12), has beenused to
control the display brightness for a variety of background lighting conditions. The resistance of R12
decreases with increasing light and so Rll must be
incorporated to ensure that the maximum source
current spec. of the MCl4489 is not exceeded in very
bright lighting conditions. R13 ensures there is still
enough drive current for the LEOs in dark conditions.

APPLICATION AREAS

As mentioned in the introduction, this application note
is designed only to show some fundamental building
blocks of a temperature control system based on the
68HC05Bx family of MCUs. Where possible, the software has been written in a modular fashion, so that the
routines can easily be transported to another application and the binary to BCD routine could be expanded
to handle larger numbers. The large number of 1/0,

PWMs and timer functions unused show that the
68HC05B family has plenty of functionality left to
perform other control functions. For example, in process control. fluid flow or speed sensors could be
connected to the timer input capture pins, pressure
sensors to the other NO pins, a keypad to the I/O lines
and the other I/O & PWMs used to perform output
control functions.

37

...,
1..

A7

I-

I-

CI

P-oAn.,

,_"

I

la

III!l
i6Ef

I.

asc,

I ..

'1-CRi:mE~
~
+',1-

a

-

OSCO

NC

TCU'l
TCMPI

-

PC?

Pea

PC5

t!r!~

-1 ~
.!-

f!L

.
LJ --

poo lI
pool

PIG

'

-'

--

I]v..
e-.!!

L----.!:
~

-1 ~

POS·

Pel

_w

1'07 •
ADI

,AlO

TCOPI

~.F

• 7

••
••
••

a-II

··..

"-1
,_,

.r.;
_

f I

"..

IJ DOUr

--;

•

II

OON ~

A•
EN

CLK II

T"" 51

,.----

PAl

.....

PM

-

.....

.-

SCU<

PAl

.

=;::::=~

--

~

1'01_ I>

I

TCAP:!

/

~,,:

f!!..-

.....
....
... ...,. II ...... f!!-f!!-.....
... ... 8•• _"
....• ,.....
..
..
....
. .....
.... ...
.... .....
PC>

B:
8 ae~
.

. £,'~

I.
VOD

II

/

At>

PC2 D

PC,1.oo

PM

PA7

vss

VAL

y7

-N~

--

AI •

.....

R>

1M

"*0
~.!-

~.!-

...., "RI.

OAPt2

T-I"F)

./

MET

Figure 6. Hardware schematic

38

RO'''''

TTl
1'2

*********************************** •••• * •••••••••• *******.*****.*****

,.
..,.,"""""""""""""""""""""""""""~"~it"~"~"~"~·
,
,.

2
3
5
6
1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

68HC05B4

.,

TEMPERATURE MEASUREMENT

~

DISPLAY

,.
,.

.,
.,

.,

Jeff Wright, Motorola East Kilbride.

22/02/90

,,..

.,
•,

This software was written by Motorola for demonstration
purposes only. Motorola does not assume any liability arising

, •
,.

.*',

out of the application or use of this software and does not
guarantee its functionality

*'

Last Updated

'*

,, ..

."""""""""""""""""""""""""'"""""""".
************* •• ***********.*.*.**************************************

I/O and INTERNAL registers definition

1/0 registers

00000000
00000001
00000002
00000003
00000004
00000005
00000006

PORTA
PORTB
PORTC
PORTO
DORA
DDRB
DDRC

EOU
EOU
EOU
EOU
EOU
EOU
EOU

$00
$01
S02
$03
S04
$05
$06

port
port
port
port
port
port
port

A.
B.
C.
D.
A DDR.
B DDR.
C DDR.

AID registers
00000008
00000009
00000007

ADDATA
ADSTC.'
COCO

EOU
EOU
EOU

$08
$09
7

A/D data register.
AID status and control register.
Conversion complete flag.

SCI registers
OOOOOOOd
OOOOOOOe
OOOOOOOf
00000010
00000007
00000006
00000011

BAUD
SCCR1
SCCR2
SCSR
TORE
TC
SCOAT

EOU
EOU
EOU
EOU
EOU
EOU
EOU

$00
SOE
$OF
S10
7
6
$11

·SCI
SCI
SCI
SCI

baud register.
control register lcontrol register 2.
status register.

SCI data register.

TIMER registers
00000012
00000005
00000006
00000007

TCR
TOlE
OCIE
ICIE

EOU
EOU
EOU
EOU

$12
5

Timer
Timer
Timer
Timer

00000013
00000003
00000004
00000005
00000006
00000007

TSR
OCF2
ICF2
TOF
OCFl
ICFl

EOU
EOU
EOU
EOU
EOU
EOU

$13
3
4
5
6
7

Timer status register.
Timer output compare 2 flag.
Timer input capture 2 flag.
Timer overflow flag.
Timer output compare 1 flag.
Timer input capture 1 flag.

39

control register.
overflow interrupt enable.
output compares interrupt enable.
input captures interrupt enable.

65
66
67
68
69
70
71

72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
:00
101
:02
103
104
105
106
107
108
109
l10

00000014
00000015
00000016
00000016
00000018
00000019
000000la
0000001b
0000001c
0000001d
0000001e
0009001£

TIC1HI
TIC1LO
TOC1HI
TOC1LO
TIMHI
TIMLO
TIMAHI
TIMALO
nC2HI
TIC2LO
TOC2HI
TOC2LO

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

00000020
00000020
00000050
OOOOOfOO

TEST
ROMO
RAM
UROM

EOU
EOU
EOU
EOU

$20
$0020
$0050
$OFOO

*******************

Timer output compare register 1 (16-bit) .
Timer free running counter (l6-bit) •
Timer alternate counter register (16-bit) •
Timer input capture register 2 (16-blt) .
Timer output compare register 2

(16-bit).

TEST register
Start address of ROMO.
Start address of RAM.

Start address of main user .ROM.

RAM ALLOCATION

*****************************

SECTION.S .RAM,ADDR=$50

TICKS
SECS
MINS
HRS

RMB
RMB
RMB
RMB

00000054
00000000
00000001
00000002
00000003

FLAG
OVERFL
NEGNUM
TLIMIT
SEC

RMB
EOU
EOU
EOU
EOU

00000055
00000000

MODE
IMP

RMB
EOU

00000056
:12 00000057
:13 00000058
114 00000059
115
116 0000005a
117 0000005b
118 0000005c
119 0000005d
120
121 0000005e
122 0000005f
123 00000060
124 00000061
125 00000062
126 00000063

BINO
DEC2
DEC1
DECO

RMB
RMB
RMB
RMB

NEWTMP
TEMP
TEMP 1
TEMP2

RMB
RMB
RMB
RMB

DISP1
DISP2
DISP3
DISPC
OLDD1
OLDD2

RMB
RMB
RMB
RMB
RMB
RMB

..

Timer input capture register 1 (l6-bit.) •

MEMORY MAP DEFINITION

00000050
00000051
00000052
00000053

~

$14
$15
$16
$16
$18
$19
$lA
$11i
$lC
$lD
$lE
$lF

0
1
2
3

40

127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189

00000064
00000065

OLDD3
OLDDC

RMB
RMB

SECTION .PAGEO,ADDR=$020
00000020 004 n82b221b150f
00000028 Oa05fffaf5eee6d8

ADTAB

FCB
FCB

$00,$4F,$38,$2B,$22,$lB,$15,$OF
$OA,$05,$FF,$FA,$F5,$EE,$E6,$D8

*********************************************************

START OF CODE
*********************************************************

SECTION . USROM,ADDR=$FOO
oooootOO
OOOOotOO
00000t02
00000t04
00000f06
00000t08
OOOOOtOa
OOOOOfOe
OOOOOfOd
OOOOOfOe
OOOOOflO

a600
b700
b701
b704
b705
ae65
f7
Sa
a350
26fa

RESET

00000fl2
00000fl4
00000fl6
00000fl8

a604
b702
a604
b706

OOOOOfla
OOOOOfle
OOOOOfle
00000f20
00000f22

b613
b619
a620
b712
9a

INlRAM

TIMINT

EQU
LDA
STA
STA
STA
STA
LDX
STA
DEC X
CPX
BNE

1$0
PORTA
PORTB
DDRA
DDRB
*OLDDC
,X

Initialise Ports.

Initialise all used RAM locations.

tRAM
INIRAM

LOA
STA
LDA
STA

1$04
PORTC
1$04
DDRC

LOA
LDA
LDA
STA
CLI

TSR
TIMLO
1$20
TCR

PC2 output high.

e1r any pending flags.
Enable timer overflow
interrupt.

* - - - - START OF MAIN PROGRAM LOOP
00000f23
00000f23
00000f26
00000f28
00000f2a
00000f2d
00000f2f
OOOOOnl
00000n4
00000n7
OOOOOna
ooooo·nc
OOOOOne
OOOOOnf
00000f41
00000f43
00000f46
00000f49
00000f4c

0754fd
1754
1155
010202
1055
1354
cdOffd
015503
cdOf4e
b65a
2a03
40
1254
b756
edOf78
cd1085
cd10ca
20d5

MAINLUP EQU
BRCLR
BCLR
BCLR
BRCLR
BSET
NOIMP
BCLR
JSR
BRCLR
JSR
GOMETR LOA
BPL
NEGA
BSET
GOMORE STA
GODISP JSR
JSR
JSR
BRA

SEC,FLAG,MAINLUP
SEC,FLAG
IMP,MODE
Check metric/imperial selector.
O,PORTC, NOIMP
Check degC/degF switch.
IMP,MODE
NEGNUM,FLAG
Clear sign indicator.
ADCONV
Go measure temperature
IMP,MOOE,GOMETR
(in degC - 2s eomp1)
Convert to degF.
CTOF
NEWTMP·
GOMORE
Only use magnitude to do BCD conY.
NEGNUM,FLAG
Remember the sign of the number.
BINO
Store temperature for con v to BCD.
SETDISP
Set-up display bytes.
DISPL
Update display if neeeessary.
DISCON
Update 14489 con fig if neccessary.
MAINLUP

41

190
191
192
193
194
195
196
191
198
1'99
200
20:
202
203
204
205
206
201
208
209
210
211
212
2Ii
214
2:5
2:6
211
218
219
220

*=
*=
*=

-*
-*

- Converts NEWTMP from deqC to degF

CTOF

.*

00000f4e
00000f4e
OOOOOf50
00000f52
00000f54
OOOOOf55
OOOOOf51
00000f59
00000f5b
00000f5d

b65a
2a05
1254
40
2001
a135
2503
1454
81

00000f5e
00000f60
00000f61
00000t62
00000f63
00000f64
00000f65
OOOOOf66
00000f61
00000f68
00000f69
00000f6a
00000f6b
COOOOf6c

ae13
42
56
46
56
46
56
46
56
46
56
46
56
46

MUL1P8

035401
40
1354
ab20
b15a
81

BRCLR
NEGA
NONEGl BCLR
ADD
STA
.RTS

CTOF

EQU
LDA
BPL
BSET
NEGA

NEWTMP
NONEG
NEGNUM,FLAG
MUL1P8
.53
MUL1P8
TLIMIT, FLAG

BRA

NONEG

Remember if No is negative or not.

CMP
BLO
BSET
RTS
LDX
MUL
RORX
RORA
RORX
RORA
RORX
RORA
RORX
RORA
RORX
RORA
RORX
RORA

Check for max degF limit of 127F.
Set limit and return if over

range~

.115

Mu1tiply·by 115 and divide by 64.
(same as multiplying by 1.8)

221

222
223
224
225

OOQCOf6d
00000f10
OOOOOfl1
OOOCOn3
226 oeocon5
221 ceccon1

NEGNUM,FLAG,NONEG1
Return sign of number.
NEGNUM,FLAG
Add 32 to get degF.
132
NEWTMP

228
229

*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX'
'X
X'
SETOISP
- Sets up display registers with BCD
X·
'X
*X
x*
'XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX'

2"

23:
232

233
23~

235
236
231
238
239
24C
2H
242
243
244
245
246
241
248
249
250
251
252

00000n8
ooooon8
ooooonb
00000 nd
00000f80
OOOOOf82
00000f83
00000f85
OOOOOf86
00COOt81
00000f89
DOOOOf8b
OOOOOf8d
OOOOOf8f
OOOOOf91
00000f94
OOOOOf96

04543e
ae08
cd1052
ae04
4f

3458
49
Sa
26fa
be51
2104
aa80
2005
035402
aabO
b15e

SETOISP EQU
BRSET
LDX
JSR
LOX
CLRA
LUPDISl LSR
ROLA
DECX
BNE
LOX
BEQ
ORA

TSTNEG
STDl

BRA
BRCLR
ORA
STA

TLIMIT,FLAG,FORCE

If temp out of ranqe, force to -

1$8

CONBCD

Convert 8 bit binary to 3 digit BCD.

.4
DECI

Shuffle bit order of digits to allow
for SCI lsb first and 14489 msb first
incompatability.

LUPDISl
DEC2
TSTNEG
1S80
If over 10Ddeg, add the 100 digit.
STOl
NEGNUM,FLAG,STOl
'$BO
Add code for a - if temp is negaive.
DISPl
Store in 1st display register.

42

253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289

00000f98
00000f9_
00000f9b
00000f9d
00000fge
00000f9f
00000f_1
00000f_3
00000f_5
00000f_7
OOOOOf_.
OOOOOf_c
OOOOOf_e
OOOOOfbO
00000fb2
00000fb4
00000fb6
00000fb8
00000fb9
OOOOOfbb
OOOOOfbd
OOOOOfbf
00000fe1
00OOOfe3
00000fc6
00000fe8
OOOOOfea
OOOOOfee
OOOOOfce

_e08
4f
3459
49
5_
26f_
aaOf
b75f
_631

015502
_6El
b760
_6eb
be57
2702
_68b
b761
81
_6bb
b75e.
_6bf
b75f
a631
015502
a6El
b760
a6fb
b761
81

LDX
CLRA
LUPDIS2 LSR
ROLA
DECX
BNE
ORA
STA
LOA
BRCLR
LDA
STOIS3 STA
LOA
LOX
BEQ
LOA
STOISC STA
RTS
LOA
FORCE
STA
LOA
STA
LOA
BRCLR
LDA
STA
STDI3
LOA
STA
RTS

~8

DECO
Shuffle bit order of digits as above.

LUPDIS2
DISP2

add code for the deg symbol.
Store in second display register.

~$31

Big C,

~$OF

_11 d.ps off.

IMP,MODE,STDIS3
Big F, _11 d.ps off.

~$F1

OISP3
I$CB
OEC2
STDISC
1$8B
DISPC
HBB
DISP1
HBF
OISP2
1$31
IMP, MODE, STDI3
HFl
DISP3
H$FB
DISPC

FORCE DISPLAY TO _AC
or -"F

*0000000000000000000000000000000000000000000000000000000000000000000*
0*
*0
0*
- Timer Overflow IRQ routine
TOVINT
*0
0*
*0
*0000000000000000000000000000000000000000000000000000000000000000000*

290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305

306
307

308
309

OOOOOfef
00000fd2
00000fd4
00000fd6
000OOfd8
OOOOOfd_
OOOOOfde
OOOOOfde
OOOOOfeO
00000fe2
00000fe4
00000fe6
00000fe8
OOOOOfe_
OOOOOfee
OOOOOfee
OOOOOffO
00000ff2
00000ff4
00000ff6
00000ff8

310
311
312
313 OOOOOff_
314 OOOOOffe
315

Ob132_
3e50
b650
a108
2520
3 f50
3e51
1654
b651
a13c
2514
3f51
3e52
b652
a13e
250a
3f52
b653
aUf
2702
3e53

TOVINT

b619
80

NOINC
NOOVF

BRCLR
INC
LOA
CMP
BLO
CLR
INC
BSET
LOA
CMP
BLO
CLR
INC
LOA
CMP
BLO
CLR
LOA
CMP
BEQ
INC
LOA
RTI

TOF,TSR,NOOVF
TICKS
TICKS

Check Tim overflow has really happened.
UPDATE REAL TIME CLOCK COUNTERS

H8
NO INC
TICKS
SECS
SEC,FLAG
SECS
860
NOINC
SECS
MINS
MINS
860
NOINC
MINS
HRS
H$FF
NOINC
HRS
Clear TOF fl_g.

TIMLO

43

316
317

318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
,.l57
358

359
360
361
362
363
364
365
366
361
368
369
310
311
372
313
314
375
316
311

*~

OOOOOffd
OOOOOffd
OOOOOfff
00001001
00001004
00001006
00001008
0000100a
'0000100e
0000100e
0000100f
00001012
00001014
00001016
00001018

AOCONV
155'
3f5b
020204
a621
2002
a620
bl09
ae04

CONTI
SETAO

4f

ADl.UPl

Sa

DECCX

0000101b
0000101d
0000101e
00001020
00001021
00001023
00001024
00001025
00001026
00001027
00001028
0000102a
0000102e
0000102e
00001030
00001032
00001033
00001035
00001031
00001039
0000103b
0000103d
0000103e
0000103£
00001040
00001041
00001042
00001043
00001044
00001045
00001046
00001048
0000104a
0000104e
0000104e
000010H
00001051

44
44
44
44
91
e620
2123
a1d8
27lt
b15e
5e
e020
b15d
b65b
a40f
be5d
42
49
59
49
59
49
59
49
59
bf5d
b65e
b05d
b15a
81
1454
81

EQU
BCL,R
CLR

Of09fd
bb08
2402
3e5b
26f4
365b
46
365b
46
b75b

000~1019

ADCONV - AID Conversion' Temperature table

TABL

TRANGE

BRSET
LOA
BRA
LOA
STA
LOX
CLRA
BRCLR
ADD
BCC
INC
DECX
BNE
ROR
RORA
ROR
RORA
STA
LSRA
LSRA
LSRA
LSRA
TAX
LOA
BEQ
CMP
BEQ
STA
INCX
SUB
STA
LOA
AND
LOX
MUL
ROLA
ROLX
ROLA
ROLX
ROLA
ROLX
ROLA
ROLX
STX
LOA
SUB
STA
RTS
BSET
RTS

TLIMIT,FLAG
TEMP
1,PORTC,CONT1
1$21
SETAD
1$20
ADSTCT
t4

interpolation.~*

Check Thermistor selector switch.

Start first conversion.
lnit counter.

Wait for end of conversion.
COCO,ADSTCT,ADLUPI
ADOATA
times and accumulate to help
DECCX
Convert
eliminate noise.
TEMP

ADLUP1
TEMP
Now divide by 4 to get average and

TEMP
store in TEMP.
TEMP

Isolate upper 4 bits of result,

ADTAB,X
TRANGE
1$08
TRANGE
TEMPI

and use them to access the look-up table

AOTAB,X
TEMP 2
TEMP

Get the diff between the base and next entry.

nOF

Now get the lower 4 bits of the AID result.

Check table entry limits.
Store ·base" value.

TEMP 2
Multiply by the difference.

Divide answer by 16 and leave in TEMP2.

TEMP 2
TEMPI
TEMP2
NEWTMP

Retrieve base value,
subtract the difference value
and store answer in NEWTMP.

TLIMIT,FLAG

318

44

379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415

*"""""""""""""""""""""""""'"""""""",,*
CONBCD

- Converts Binary in BINO to BCD in DECO-2

EOU
CLRA
STA
STA
STA

DECO
DECI
DEC2

Clear BCD result bytes.

BINO
DECO
DECI
DEC2
DECO
ISOA
TSTDI
DECO
DECI
DECI
tsOA
TSTD2
DEC 1
DEC2
DEC2
ISOA
NOOVR

Put the next binary bit in carry.
Multiply current result by 2 and

*,
*"""""""""""""""""""""""""'"""""""",,*
00001052
00001052
00001053
00001055
00001057

4f
b759
b758
b757

CONBCD

00001059
0000105b
0000105d
0000105f
00001061
00001063
00001065
00001067
00001069
0000106b
0000106d
0000106f
00001071
00001073
00001075
00001077
00001079
0000107b
0000107d
0000107f
00001081
00001082
00001084

3956
3959
3958
3957
b659
aOOa
2b04
b759
3c58
b658
aOOa
2b04
b758
3c57
b657
aOOa
2b06
a609
b757
1054
5a
26d5
81

LUPBCD

TSTDI

TSTD2

ROL
ROL
ROL
ROL
LOA
SUB
BMI
STA
INC
LOA
SUB
BMI
STA
INC
LOA
SUB
BMI
LOA
STA
BSET
. NOOVR
BNE
RTS

add in new bit at same time.

Now check the BCD bytes
for overflow.

.9
BCD number has overflowed so set flag

DEC2
OVERFL, FLAG
DECX
LUPBCD

and set upper digit to 9.

Any more bits to do?

416
411
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442

*@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@*
*@
@*
DISPL
Updates 14489 Display registers via SCI
*@
@*
*@
@*
*@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@*
00001085
00001085
00001087
00001089
0000108b
0000108d
0000108f
00001091
00001093
00001095
00001097

b65e
b162
260d
b65f
b163
2607
b660
b164
2601
81

DISPL

00001098
0000109a
0000109c
0000109d
0000109f
000010al
000010a3
000010a6

a601
b70e
4a
b70d
a608
b70f
OdlOfd
1502

UPDATE

PREAM

EOU
LOA
CMP
BNE
LOA
CMP
BNE
LOA
CMP
BNE
RTS
LOA
STA
DECA
STA
LOA
STA
BRCLR
BCLR

DISPI
OLDDI
UPDATE
DISP2
OLDD2
UPDATE
DISP3
OLDD3
UPDATE

Only update display registers if any
of them have changed since the last
time.

.SOl
SCCRI

Clock idle low, edge in mid data, last clk.

BAUD
1$08
SCCR2
TC,SCSR,PREAM
2,PORTC

45

131.072KHz baud with 4.1getc XTAL.
Transmit enabled.
Wait for preamble to finish.
Enable transmission to 14489.

443
444
445
,46
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
~77

478
479
48C
481
482
483
484
485
486
487
~88
~89

490
49:

000010a8 ·b660
OOOOlOaa b764
OOOOlOae b711
OOOOlOae OflOfd
OOOOlObl b65f
000010b3 b763
000010b5 b71l
000010b7 OflOfd
OOOOlOba b65e
OOOOlObe b762
OOOOlObe b711
OOOOlOeO OdlOfd
000010e3 a600
000010e5 b70f
000010e7 1402
000010e9 81

DWAITl

DWAIT2

DWAITl

LOA
STA
STA
BRCLR
LOA
STA
STA
BRCLR
LOA
STA
STA
BRCLR
LOA
STA
BSET
RTS

OISP3
OLOOl
SCDAT
Send first byte.
TDRE,SCSR,DWAITI Wait until it has been transfered
OISP2
- then load second.
OLDD2
SCDAT
TORE,SCSR,OWAIT2
DISPI
OLDOI
SCDAT
TC,SCSR,OWAIT3 Wait until 3rd byte has actually gone
1$00
SCCR2
Dissable SCI transmissions,
2,PORTC
then disable 14489.

*1111111111711111111111111111111111111111111111111111111??11111????1?*
*?
?*
*?
OISCON
Updates 14489 Config register via SCI
?*
*?
?*
*1??111?????1????????????111????1?????????11??????????111111111111111*

OOOOlOea
OOOOlOea
OOOOlOee
OOCOIOee
OOOOlOdO

b661
b165
2601
81

DISCON

OOOOlOdl
000010d3
OCOOIOd5
OOCOIOd6
000CICd8
OOOOIOda
OOCCIOde
COOOIOdf
OOOOlOel
OOOOlOe3
OOOOlOe5
OOOOlOe7
OOOOlOea
OOOOlOee
OOOCIOee
OCOOIOn
OOOOlOfJ

a601
b70e
4a
b70d
a608
b70f
OrllOfd
1502
b66l
b765
b711
onOfd
a600
b70f
OdlOfd
1402
81

UPDCON

PREAMI
DOCONF

DWAIT4

DWAIT5

EQU
LOA
CMP
BNE
RTS
LOA
STA
DECA
STA
LOA
STA
BRCLR
BCLR
LOA
STA
STA
BRCLR
LOA
STA
BRCLR
BS!;:T
RTS

Only update eonfig register if it has

DISPC
OLDDC
UPDCON

changed since last time.

ISOI
SCCRI

Clock idle low, edge in mid data, last elk.

l31.072KHz baud with 4.1gete XTAL.
BAUD
1$08
SCCR2
Transmit enabled.
TC,SCSR,PREAM1 Wait for preamble to finish.
2,PORTC
Enable transmission to 14489.
OISPC
OLDDC
SCDAT
TDRE,SCSR,OWAIT4 Wait until eonfig byte has transfered.
1$00
SCCR2
Now disable SCI transmission.
TC,SCSR,DWAIT5 Wait until con fig byte has actually gone.
2,PORTC
Disable 14489 , return.

492

493
494
495
496
497
498
499
500
501
502
503
504
505
506

-************************************************************************

VECTOR ADDRESSES
*************************************************************************

SECTION .VECT,ADDR=$lFF2
0000lff2
0000lff4
0000lff6
00001ff8
OOOOlffa
OOOOlffe
OOOOlffe

Of 00
Ofef
Of 00
Of 00
Of 00
Of 00
Of 00

SCIINT
TOVFLW
TOCMP
TICAP
EXTINT
SOFTI
POR

FOB
FOB
FOB
FOB
FOB
FOB
FOB

RESET
TOVINT
RESET
RESET
RESET
RESET
RESET

46

Section synopsis

1 00000016
2 00000010
00000lf4
OOOOOOOe

22)
16)
500)
14)

.RAM
.PAGEO
.USROM
. VECT

Symbol table
.PAGEO
• RAM
.USROM
.VECT
ADLUP1
ADTAB
BINO
CONTI
DECO
DEC1
DEC2
DECCX
DISP1
DISP2
DISP3

00000000
00000000
3 00000000
00000000
3 0000100f
2 00000020
00000056
00001008
00000059
00000058
00000057
00001018
0000005e
0000005f
00000060

DISPC
DOCONF
DWAIT1
DWAIT2
DWAIT3
DWAIT4
DWAIT5
EXTINT
FLAG
FORCE
GODISP
GOMETR
GOMORE
HRS
INIRAM

00000061
000010df
000010ae
000010b7
000010eO
000010e7
000010ee
00001ffa
00000054
3 00000fb9
00000f43
3 ooooona
00000f41
00000053
OOOOOfOe

LUPBCD
LUPDIS1
LUPDIS2
MINS
MODE
MUL1P8
NEWTMP
NOIMP
NOINC
NONEG
NONEG1
NOOVF
NOOVR
OLDD1
OLDD2

3 00001059
00000f83
3 00000f9b
00000052
00000055
3 00000f5e
1 0000005a
00000f2f
3 OOOOOffa
00000f51
OOOOOfll
OOOOOffe
00001081
00000062
00000063

OLDD3
OLDDC
POR
PREAM
PREAM1
SCIINT
SECS
SETAD
SOFTI
STD1
STOI3
STDIS3
STDISC
TABL
TEMP

00000064
00000065
4 OOOOlffe
3 000010a3
000010de
0000lff2
00000051
0000100a
OOOOlffe
00000f96
00000fe8
OOOOOfae
00000fb6
00001023
0000005b

TEMP
TEMPI
TEMP2
TICAP
TICKS
TIMINT
TOCMP
TOVFLW
TOVINT
TRANGE
TSTD1
TSTD2
TSTNEG
UPDATE

0000005b
0000005e
0000005d
0000lff8
00000050
OOOOOfla
0000lff6
0000lff4
3 OOOOOfef
3 0000104f
0000106b
00001015
00000f91
00001098

Symbol cross-reference

.PAGEO
. RAM
.USROM
.VECT
ADLUP1
ADTAB
BINO
CONTI
DECO
DEC1
DEC2
DECCX
DISP1
DISP2
DISP3
DISPC
DOCONF
DWAITl
DWAIT2
DWAIT3
DWAIT4
DWAIT5
EXTINT
FLAG
FORCE
GODISP
GOMETR
GOMORE
HRS
INIRAM
LUPBCD
LUPDIS1
LUPDIS2
MINS
MODE

'131
'94
'142
'498
*334
*133
*111
327
'114
*113
'll2
336
'121
*122
*123
'124
*481
'446
'450
'454
*485
'488
*504
'102
237
*184

334
351
183
*330
255
242
246
*338
252
260
264
269

339
357
392
387
388
266

393
394
389

396
400
395

272

424

451

274
278
280

427

447

430
469

443
482

171

175

399
401
405

404
406

410

182

199

204

222

262

216

446
450
454
485
488

170
*271

177

*179

180
'100
*151
*392
'242
'255
*99
*108

*183
308
154
413
245
258
303

172

311

304

307

174

177

47

224

231

250

298

325

316

4ll

MUL1P8
NEWTMP
NOIMP
NOINC
NONEG
NONEG1
NOOVF
NOOVR
OL001
OLD02
OL003
OLDOC
POR
PREAM
PREAM1
SCIINT
SECS
SETAO
SOFTI
STD1
STOI3
STOIS3
STOISC
TABL

201
*116
173
295
198
222
291
408
*125
*126
*127
*128
*506
*441
*480
*500
*98
329
*505
249
276
262
267
*346

*207
197

226

374

306

310

*313

452
448
444
470

483

297
*331

299

302

250
*278
*264

*252

203
179
*175
301
*202
*224
*314
*412
425
428
431
150
441
480

*269

Symbol cross-reference

TEMP
TEMPI
TEMP2
TICAP
TICKS
TIMINT
TOCMP
TOVFLW
TOVINT'
TRANGE
T5T01
TSTD2
TSTNEG
UPDATE
UPDCON

*117
*118
*119
*503
*97
*161
*502
*501
*291
352
398
403
247
426
471

326
355
358

337
372
361

340

342

371

373

292

293

296

501
354
*401
*406
*250
429
*474

344

359

*376

432

"435

48

AN432
128K byte addressing with the M68HC11
By Ross Mitchell
MCU Applications Engineering
Motorola Ltd., East Kilbride, Scotland

OVERVIEW
The maximum direct addressing capability of the M68HC11
device is 64K bytes. but this can be insufficient for some
applications. This application note describes two methods of
memory paging that allow the MCU to fully address a single
1 megabit EPROM (128K bytes) by manipulation of the
address lines.

The two methods illustrate the concept of paging and the
.inherent compromises. The technique may be expanded to
allow addressing of several EPROM, RAM or EEPROM
memories or several smaller memories by using both addre~s lines and chip enables.

PAGING SCHEME
The M68HC11 8-bit MCU is capable of addressing up to 64K
bytes of contiguous address space. Addressing greater than
64K bytes requires that a section of the memory be replaced
with another block of memory at the same address range.
This technique of swapping memory is known as paging and
is simply a method of overlaying blocks of data over each
other such that only one of the blocks or pages is visible to
the CPU at a given time.
In a system requiring more than 64K bytes of user code and
tables. it is possible to use the port lines to extend the
memory addressing range ofthe M68HCll device. This has
certain restrictions but these can be minimised by careful
consideration of the user code implementation.
There are two basic configurations; method A uses only software plusa single port line to control the high address bit A 16;
method B isa combination of a small amount of hardware and
software controlling thetop3 address bits A 14, A 15 and A 16.

In the examples below, the MC68HC11 G5 device is used to
demonstrate the paging techniques since this device has a
non-multiplexed data and address bus; any M68HCll device
may be used in a similar way.
Method A has the advantage of no additional hardware and
very few limitations in the software. The user code main loop
can be up to 64K bytes long and remain in the same page but
this is at the expense of longer interrupt latency. The vector
table and a small amount of code must be present in both
pages of memory to allow correct swapping of the pages.
Method B has the advantage of not affecting the interrupt
latency and has just one copy of the vector table. The
maximum length of the user code main loop in this example
is 48K bytes with a further 5 paged areas of 16K bytes for
subroutines and tables.

49

METHOD A - SOFTWARE TECHNIQUE
Address.A16 of the EPROM is directly controlled by port 0(5)
of the M68HC11 as shown in figure 1. This port is automatically configured to be in the input state following reset. It is vital
that the state of the port line controlling address A 16 is known
following reset and so there is a 1OKn pull-up resistor on this
port line to force the A 16 address bit to·a logic high state
following reset. This port bit is then made an output during the
set-up code execution but care must be taken in ensuring that
the data register is written to a logic one before the data
direction register is written with a one to make the port line
output a high state.

I-bit in the CCR (interrupt inhibit) is set during this time for the
example code to run correctly, otherwise the return page may
be altered. This limitation can be overcome by using the stack
to maintain a copy of the last page prior to the current interrupt.
The latency for an interrupt routine in a different page from the
currently running user code is increased by 21 cycles on
entering the interrupt routine and 18 cycles on leaving the
interrupt routine. Any interrupt code that could not tolerate any
such latency could be repeated in both pages of memory.

Other routines

This port bit allows the M68HCll to access the 128K byte
EPROM as two memories of 64K bytes each which are paged
by changing the state of the address A 161ine on the EPROM.
It important-to make sure that the port timing enables the port
line to change state at least the setup and hold time before the
address strobe (E clock rising edge on the MC68HCll G5),
otherwise there could be problems with address timing.

Jumping from one page to another may be done at any time
by using the same change of page routine but there is no need
to store the current page in RAM and so these two lines of code
become redundant. In the example, the change page routine
could be started at the BCLR or BSET command and save 4
cycles. This would therefore reduce the page change delay to
17 cycles. Note that it is not possible to ·perform a JSR
command to move into the other page with the method shown
in the example since the RTS would not return to the original
page, however, a modification to the return from interrupt
routine would allow an equivalent function for a return from
subroutine. In this case the stack should be used to maintain
the correct return page or the I-bit in the CCR should be set to
prevent interrupts.

Figure 2 shows a schematic representation of the paging
techf1ique for this method where there are two separate 64K
byte pages of memory which may only be addressed individually.
This paging scheme means that code cannot directly jump
from one 64K page to another without running some common
area of code during the page switch. This may be accomplished
in 2 basic ways. The user code could build a routine in RAM
(which is common to both pages since it is internal and
therefore unaffected by the port 0(5) line) or have the same
location in both pages devoted to a page change routine. The
example software listing in appendix A uses the latter approach.

Important conditions
The state of the port line controlling address A 16 after reset is
very important. In the example, port 0(5) is used which is an
input after reset and has a pull-up resistor to force a logic high
on A 16. If an output only port line was used then it could be
reset such that A 16 is a logic zero (no pull-up resistor required)
which has an important consequence. The initialisation routine
which sets up the ports must be in the default page dictated
by the state of address A 16 following reset otherwise the user
code may not be ableto correctly configure the ports and hence
be unable to manipulate address A 16. Similarly, a bidirectional
port line could have a pull-down resistor to determine the
address A 16 line after reset with the same implications.

Interrupt routines
The change of page routine stores the current page before
setting or clearing the port 0(5) line and then has a jump
command which must be at exactly the same address in both
pages of memory. This is because the setting or clearing of the
port 0(5) line will immediately change the page of memory but
the program counter will increment normally. Thus a change
from page 0 to page 1 will result in the BSET PORTO command
from page 0 followed by the JMP O,X instruction from page 1
(the new Pllge). To enable II jump to work, the X index register
has been loaded with the aadress of the routine to be run in the
new page. Figure 3 shows the execution of code to perform
a change of page from page 1 to page O.

The assembler generates two blocks of code with identical
address ranges used by the user code. This could not be
programmed directly into an EPROM since the second page
would simply attempt to overwrite the first page. The code
must therefore be split into two blocks and programmed into
the correct half of the EPROM. Some linkers may be capable
of performing this function automatically. Figure 2 illustrates
the expansion of the pages into the 128K byte EPROM
memory.

Returning from the interrupt routine requires the RTI command to be replaced with a return from interrupt routine that
checks the RAM location containing the memory page number prior to the interrupt routine execution. The routine then
either performs an RTI command immediately if it is to remain
in the same page or otherwise changes the state of the port
0(5) line and then performs an RTI command in the correct
page. Note that as with the JMP O,X command, the RTI must
be at the same address in both pages. It is important that the

The RAM and registers, and internal EEPROM if available and
enabled, will all appear in the memory map in preference to
external memory so care must be taken to avoid these
addresses or move the RAM or registers away to different
addresses by writing to the INIT register.

50

1M bit EPROM

68HC11

-------t A16

PD5t---....

AD - A 1 5 1 - - - - - - - -...~AO - A15

DO-D7~1_------------~~DO-D7

EI------j

RIW 1 - - - - - - 1

u---~OE

CS
Figure 1. Software Paging Schematic Diagram

128K byte EPROM

$00000

64K byte map

Page 0

$0000

$0000

$OFFFF
Page 0

$10000
Page 1

$FFFF

Page 1
Default Page

$FFFF
$1FFFF
Figure 2. Software Paging Representation

51

128K byte EPROM

$00000
TOGGLE PORT A-4
JUMP TO CHANGE PAGE ROUTINE

Page 0

$OF800

VECTORS

$OFFFF

r-------------------------~

$10000

TOGGLE PORT A-3
JUMP TO CHANGE PAGE ROUTINE

Page 1

$1F800
Default
page

VECTORS
~------------------------~

$1FFFF

1 - Jump to change page routine
2 - Page changes to page 0
3 - Jump to address in X register (in page 0)

Figure 3. Flow of program changing from Page 1 to Page 0

52

1M bit EPROM

68HC11

A14 1---+-1-+------<.---1

1---.-1 A14

PD31--~-+~~~___I

A 15 f----+---f--4i>--+---l
PD41--~-4>---+-I---I

1--+--+1 A15

~>---~

A16

PD51--~-------~

74HC27
AO - A131------------~ AO - A13
DO - D7

~-----------~

DO - D7

74HCOO
Ef-------------I

R/W 1---------------1

D - - - + I OE

CS

Figure 4. Hardware and Software Paging Schematic Diagram

53

METHOD B - COMBINED HARDWARE AND SOFTWARE TECHNIQUE
The basic approach to this method is the same as above
except that hardware replaces some of the software. A port
line together with M68HCll addresses A14 and A15 are
NOR'd to control the address A161ine ofthe EPROM. This
signal is also used to select between the port line and address
line for A14 and A15 (see figure 4). The hardware between
the port lines controlling the A 14 and A 15 addresses enables
64K bytes of user code to be addressed at all times with 48K
bytes common to all the pages and then selecting one of five
16K byte pages of EPROM memory.

with the first part an example of using in-line code and the
second part calling a function. The short example shows the
assembly code on the left, generated by the 'C' code on the
right. This is very similar to the assembly code example in
appendix B and so it is possible to extend the memory
addressing beyond 64K bytes with the 'C' language just as
with assembly language.

Interrupt conditions
The interrupt routines have normal latency when they reside
in the main 48K bytes page since this is always visible to the
CPU. The 25 cycle delay for changing pages may cause
problems for interrupt routines in a paged area of memory.

In the example, port D(3) and address A 14 are connected to
the input of a 2 channel multiplexer such that port D(5),
address A 14 and address A 15 control which of these two
signals reaches the A 14 pin of the EPROM. If addressesA14
or A 15 are logic 1, the NOR gate outputs a logic 0 state,
ensuring the A 16 pin of the EPROM is a logic O. In this case
address A 14comrols theA 14 pinofthe EPROM and similarly
A 15 and port D(4) are selected such that address A 15
controls the A15 pin of the EPROM. Thus the main 48K byte
portion ofthe EPROM memory may be addressed at all times
at addresses $4000 up to $FFFF. With Port D(5) and address
A 14 and A 15 all at logic 0 (addfess range $0000 to $3FFF),
the port lines Port D(3) and Port D(4) are selected in place of
address lines A14 and A15. Page 0 is always selected
whenever Port D(5) is a logic 1 . This makes it possible to have
one of the five pages of 16 K bytes paged into the 64 K
addressing range of the HCll while always maintaining the
main 48K bytes of user code in the memory map.

Important conditions
There are few special conditions for this method. The vectors
must point to the main page of memory where the page
changing routine must also reside. Routines in a paged area
can only move to another page via the main 48K page unless
the technique in method Ais utilised (i.e. page change routine
duplicated at identical addresses in both pages).
As with method A. the RAM and registers, and internal
EEPROM if available and enabled, will all appear in the
memory map in preference to external memory so care must
be taken to avoid these addresses or move the RAM or
registers away to different addresses.

There are few restrictions on the user code since the
hardware provides the switching logic. Code can be made to
run from one paged area to another by jumping to an
intermediate routine in the main page. Port D is configured
to be in the input state following reset which results in the
main page plus page 0 of the paged memory in the 64K byte
address map since the port D lines each have a pull-up
resistor to maintain a logic high state after reset. A simple
change memory map routine can then bring in the desired
page at any time. Appendix B shows the assembly code for
a program that toggles different port pins in each of the 5
pages controlled from a main routine in the main page.
Figure 5 shows the 5 overlaid pages expanded to a 128K map
with the flow of the program demonstrating a change from
page 0 to page 1 by running the change page subroutine
shown in bold type.

The assembler generates 5 blocks of code with identical
address ranges used by the user code plus the main 48K byte
section. This could not be programmed directly into an
EPROM since the second and subsequent pages would
simply attempt to overwrite the first page. The code must
therefore be split into blocks and programmed into the correct
part of the EPROM. Some linkers may be capable of performing this function automatically.
Figure 6 illustrates the expansion of the pages into a single
128K byte EPROM memory.

Customisation
Clearly the size of the paged areas may be made to suit the
application with for example a 32K byte main page and three
32K bytes of paged memory simply by not implementing
control over the A 14 address of the EPROM and not including Port D(3) control. Similarly by adding another port line to
control address A 13, the main program can be 56K bytes with
9 pages of 8K bytes each.

Implementation in 'C' language
The demonstration code was originally written in assembly
language but it may also be implemented in 'C' as shown in
appendix C. The change of page routines were written in 'C'

54

$00000
Page 0

~~~~~~~~~~~~~ $04000

Main Page
JSR TO PAGE 2 CHANGE SUBROUTINE
JSR TO PAGE 2
etc
CHANG~ TO PAGE 0 AND RETURN
CHANGE TO PAGE 1 AND RETURN
CHANGE TO PAGE 2 AND RETURN

$10000
Page 1

$14000
TOGGLE PORT A-5
AND RETURN TO MAIN
PROGRAM

Page 2

$18000

TOGGLE PORT A-6
AND RETURN TO MAIN
PROGRAM

Page 3

$1COOO

TOGGLE PORT A-7
AND RETURN TO MAIN
PROGRAM

Page 4

' - - - - - - - - - - - - - - - - ' $1FFFF
1 - Return from page 0
2 - Jump to page 1 routine
3 - Return from page 1 to main page

Figure 5. Illustration of changing from Page 0 to Page 1

55

$00000
Page 0

$04000
$0000

$3FFF

Main Page

$4000

$10000
Page 1
Main Page

$14000
$FFFF

1--_ _ _ _ _ _---..

Page 2
$18000
Page 3

$1COOO
Page 4
' - - - - - - - - - - ' $1FFFF

Figure 6. Hardware and software paging representation

56

Method A

$0000

Method B

I

Page 0

$0000

Page 0

1

Page 1
$3FFF

$4000

Page 2

-

Page 3

,--

-

I

I

Page 4
'--

Page 1

~

Main Page
$FFFF

'--

$FFFF

Figure 7. Comparison of paging schemes

Beyond 128K bytes

IN GENERAL

Both techniques may be scaled up with several port lines
controlling address lines beyond address A 15 with the
addition of further change page routines and enhancing the
return from interrupt routine to allow a return to a specific
page in method A or the addition of further multiplexing logic
in method B.

In both methods, the registers may be moved to more
appropriate addresses. If the usage of RAM is not critical the
registers may be moved to address $0000 by writing $00 to
the INIT register immediately after reset. For the
MC68HC11 G5 this means losing 128 bytes of RAM but
results in a clean memory map above $1 FF .In the examples,
the registers and RAM remain at the default addresses and
so care must be taken not to have user code from address
$0000 to $01 FF and $1 000 to $1 07F for the MC68HC11 G5.
Note thatthe MC68HC11 E9 andMC68HC11 AS have slightly
different RAM and register address ranges plus the internal
EEPROM which should be disabled if not used.

IN CONCLUSION
The two methods described in detail are the basis for many
other ways of controlling paging on a single large EPROM
memory device or several smaller EPROMs. It is a simple
matter to scale up or modifythe techniques to suita particular
application or EPROM. The software approach is the cheapest and allows for a main program of up to the full size of the
EPROM while the combined hardware and software approach has a maximum main program size of 48K bytes (in
this examplel and no additional interrupt latency.

Figure 7 demonstrates the differences between the paging
techniques by showing the overlap of the pages. The number and size of the pages can easily be modified by small
changes to the page change routines and hardware.

57

APPENDIX A • SOFTWARE PAGING SCHEME
**** EXTENDA.ASC **********************************************************
2
3
4
5
6
7
8
9
10

TESTS EXTENDED MEMORY CONTROL
For a single 1M bit (128K byte) EPROM split into 2 x 64K byte pages.
A16 is connected to Port 0(5) which then selects which half of
the EPROM is being accessed. PD5 • 1 after reset since it is in

the input state with a pull-up resistor to Vdd.
This code is written for the 68HCIIG5 MCU but can be easily modified
to run on any 68HCli device. The 68HClIG5 has a non-multiplexed

11

12
13

address and data bus in expanded modea

14

15
16
**************************.************************************************

17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

00000060
00000001
00000004
00000006
00000007
00000008
00000009
00000024
00000025
00000040
00000040
00000026
00000080
00001000

PORTA
DORA
PORTB
PORTC
DDRC
PORTO
DDRD
TMSK2
TFLG2
RTII
RTIF
PACTL
DDRA7
REGS

EOU
EOU
EOll'
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

SOO
SOl
S04
S06
S07
S08
S09
S24
S25
S40
S40
S26
S80
S1000

-**************************************************************************

RAM definitions (from SOOOO to SOIFF)
***************.***********************************************************

00000000
00000001

PAGE
TIME

00000020

NPAGE
ROMBASE
CHANGE
VECTORS

44 00000200

45 0000f800
46 OOOOffcc
47
48
49
50
51
52
53
54
55
56
57
58
59
60

ORG
RMB
RMB

SOOOO
I
2

EOU
EOU
EOU
EOU

S20
S0200
SF800
SFFCC

page number prior to interrupt
counter value for real time interrupt routine
PORT 0-5 page control line
Avoid RAM (from SO to SIFF)

**********************************************************-****************

START OF MAIN PROGRAM
*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

page 0 (1st half of EPROM)

*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

org

ROMBASE

***************************************************************************

Redirect reset vector to page 1

61

62

************************************.**** •• ********************************

58

63
64
65
66
61
68
69
10
11
12
13
14
15
16

00000200
00000203

ce0200
1ef800

RESETO LDX
JMP

.RESET
CHGPAGEO

***************************************************************************
2nd half of page 0 loop running in page 1
********************************.******************************************

00000206
0000020a
0000020e
00000211

181c0010
181d0010
ce0216
1ef800

LOOPPO BSET
BCLR
LOX
JMP

PORTA,'t,U10
PORTA,'t,'$10
• LOOPP1
CHGPAGEO

Toggle bit
get return address in page 1
jump to change page routine

11

18
19
80
81
82
83
84
85
86
81
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103

Real time interrupt service routine
***************************************************************************

00000214
00000219

181e254001
3b

0000021a
0000021a
0000021c
000002lf
00000221
00000222
00000225
00000221
00000228
0000022a

8640
18a125
9602
4c
b11004
deOl
08
dfOl
1ef80a

TFLG2,'t,tRTIF,RTISERV
return if not correct interrupt source
This is an RTI because interrupt vector
only points here when in pa'ge 1

RTISERV
LOAA
STAA
LOAA
INCA
STAA
LOX
INX
STX
JMP

nOl000000
TFLG2, 't
TIME+l

page

a

interrupt starts here

clear RTI flag
get the time counter
increment counter
store time in port B

PORTB+REGS
TIME

and copy back into RAM

TIME
RETRTIO

jump to RTI routine

*************************-*************************************************

CHANGE PAGE ROUTINE
This code must be executed with the I-bit set to prevent interrupts
during the change if it is a jump for an interrupt routine.
Otherwise PAGE could be updated and then another interrupt could
occur before the PAGE was changed causing the first interrupt
routine to return to· the wrong page.
The PAGE variable is not required for a normal jump and so it does
not require the I-bit to be set (only the SSET is important).

104

105
106
101
108
109
110
111
112
113
114
115 0000f800
116 0000f800
1f1 OOOOf802
118 00OOf804
119 00POf808
120
121
122
123
124
125
126
121
128

RTISRV BRSET
RTI

This code is repeated for the same position in both pages
***************************************************************************
jump routine
ORG
CHANGE
Address for this routine is fixed
cycles

8600
9100
181c0820
6eOO

CHGPAGEO
LDAA
STAA
BSET
JMP

.0
PAGE
PORTO,'t,'NPAGE
O,X

2
2
8

set current page number = a
store page page number
change page by setting PD-5
This code is the same in both pages

***************************************************************************
return from interrupt routine running in page a

check if interrupt occurred while code was running in page

and return to page 1 before the RTI command is performed
***************************************************************************

59

129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170

.cycles

0000f80a
OOOOf80a
OOOOf80e
0000f80e
OOOOf810
0000f8ll
0000f8ll
0000f815

9600
8101
2701
3b
181e0820
3b

RETRTIO
LDAA
CMPA
BEQ
RTI
RTIPAGEO
BSET
RTI

PAGE

2
2
3
12

U

RTIPAGEO
PORTD,Y,'NPAGE

8
12

get paqe the interrupt occured in

is it page 1
if yes then change page
otherwise, return from interrupt
change page and return from interrupt
This codes is the same in both pages

***********************************************************************

VECTORS
**~*~************************************************* *****************

MOOffee
OOOOffee
OOOOffdO
0000ffd2
0000ffd4
0000ffd6
0000ffd8
OOOOffda
OOOOffde
0000 ffde
OOOOffeO
0000ffe2
0000ffe4
0000ffe6
0000ffe8
OOOOffea
OOOOffee
OOOOffee
OOOOfffO
0000fff2
OOOOff!4
OOOOff!6
0000ff!8
OOOOfffa
OOOOfffe
OOOOfffe

0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0214
0200
0200
0200
0200
0200
0200
0200

ORG
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB

VECTORS
RESETO
RESETO
RESET a
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RTISRV
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO
RESETO

EVENT 2
EVENT
TIMER OVERFLOW 2
INPUT CAPTURE 6 I OUTPUT COMPARE 7
INPUT .CAPTURE 5 I OUTPUT COMPARE 6
SCI
SPI
PULSE ACC INPUT
PULSE ACC OVERFLOW
TIMER OVERFLOW 1
INPUT .CAPTURE 4 I OUTPUT COMPARE 5
OUTPUT COMPARE 4
OUTPUT COMPARE 3
OUTPUT COMPARE 2
OUTPUT COMPARE 1
INPUT CAPTURE 3
INPUT CAPTURE 2
INPUT CAPTURE 1
REAL TIME INTRRUPT
IRQ
XIRQ
Sill
ILLEGAL OPCODE
COP
CLOCK MONITOR
RESET

111
172

***********************************************************************

173

*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

174

175

page 1 (2nd half of EPROM)

176

177
118

*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197

***********************************************************************

MAIN ROUTINE NOT UNDER INTERRUPT CONTROL
***********************************************************************

00000200
00000203
00000206
00000208
0000020e
00000210
00000213
00000216
00000216
00000217
00000219

8eOlff
bd021b
86f!
181eOO08
181dOO08
ee0206
7ef800
4a
26ef
20eb

ORG
RESET LOS
JSR
LooP1 LDAA
LOOP BSET
BCLR
LDX
JMP
LooPPl
DECA
BNE
BRA

ROMBASE
H01FF
SETUP
ISFF
PORTA, Y, 1$08
PORTA, Y, 1$08
.LOOPPO
CHGPAGE1

set up jump to other page
go to other page

LOOP
LOOP 1

return point from other page
toggle port A
start loop again

60

initialise RTI interrupt and OORs

Toggle bit 3

198
199
200
201
202
203
204
205
206
207
208
209
210
211
212

***********************************************************************

INITIALISATION ROUTINE

000OO21b
0000021c
00000220
00000222
00000225
00000228
0000022b
0000022d
00000230
00000233
00000234

Of
18cel000
86ff
b71001
b71008
b71009
8640
b71025
b71024
Oe
39

SETUP

SEI
LDY
LDAA
STAA
STAA
STAA
LDAA
STAA
STAA
CLI
RTS

1$1000
'$FF
DDRA+REGS
PORTD+REGS
DDRD+REGS
1\01000000
TFLG2+REGS
THSK2+REGS

Register address offset

make port A all outputs
make sure port 0-5 is written a 1
and only then make al1 outputs

clear RTI flag
enable RTI interrupt

213

214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
251
258
259

Redirect to the Real time interrupt service routine
Page 1 routine for service routine located in page 0
***********************************************************************

00000235
0000023a

181e254001
3b

0000023b
0000023b
0000023e

ce021a
7ef800

INTRTI BRSET
RTI

TFLG2,Y,IRTIF,GOODINT

return if. not correct interrupt source
This is an RTI because interrupt vector
only points here when in page 1

GOODINT
LDX

JHP

iRTISERV
CHGPAGE1

cycles
3
get the interrupt entry point in page 0
jump to change page routine

**************.************************************************** •.• * ••••

CHANGE PAGE ROUTINE
This code must be executed with the I-bit set to prevent interrupts
during the change if it is a jump for an interrupt routine~
Otherwise PAGE could be updated and then another interrupt could
occur before the PAGE was changed causing the first interrupt
routine to return to the wrong page.
The"PAGE variable is not required for a normal jump and so it does
not require the I-bit to be set (only the BCLR is important).
This code is repeated for the same position in both pages
.**.***********************.*******************************************

jump routine
ORG
CHANGE

Address for this routine is fixed
cycles

0000f800
0000f800
0000f802
0000f804
0000f808

8601
9700
181d0820
6eOO

CHGPAGE1
LDAA
STAA
BCLR

JHP

1$1
PAGE
PORTD,Y,iNPAGE
O,X

2
2

set current page number - 1
store page page number
change page by clearing PD-5
This code is the same in both pages

return from interrupt routine running in page

a

check if interrupt occurred while code was running in page
and return to page 0 before the RTI command is performed
*************~***************************.************ *-***************

61

260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
28.4
285
286
281
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303

cycles

OOOOf80a
000Of80a
0000f80e
0000l80e
oOoOtalO
OOOOfS11
0000t8ll
000Ofa15

9600
8100
2701
3b
18ld0820
3b

RETRTIl
LDAA
CMPA
BEQ
RTI
RTIPAGE1
BCLR
RTI

PAGE
10
RTIPAGE1

2
2
3
12

get page the interrupt occured in
is it page 0
if yes then, change page
otherwise, return from interrupt

PORTD,Y,tNPAGE

8
12

change page and return from interrupt
This codes is the same in both pages

*********.*******************************************************.*****

VECTORS
***********************************************************************

OOOOffee
OOOOffee
OOOOffdO
0000ffd2
0000ffd4
0000ffd6
0000ffd8
OOOOffda
OOOOffde
OOOOffde
OOOOffeO
0000ffe2
000Offe4
00OOffe6
OOOOffe8
OOOOffea
OOOOffee
OOOOffee
OOOOfftO
0000fff2
0000fff4
0000fff6
000Cfft8
OOOOfffa
OOOOfffe
OOOOfffe

0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0200
0235
0200
0200
0200
0200
0200
0200
0200

ORG
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB

VECTORS
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
INTRTI
RESET
RESET
RESET
RESET
RESET
RESET
RESET

EVENT 2
EVENT
TIMER OVERFLOW 2
INPUT CAPTURE 6 I OUTPUT COMPARE
INPUT CAPTURE 5 I OUTPUT COMPARE
SCI
SPI
PULSE ACC INPUT
PULSE ACC OVERFLOW
TIMER OVERFLOW 1
INPUT CAPTURE 4 / OUTPUT COMPARE 5
OUTPUT COMPARE
OUTPUT COMPARE 3
OUTPUT COMPARE 2
OUTPUT COMPARE
INPUT CAPTURE
INPUT CAPTURE 2
INPUT CAPTURE 1
REAL TIME INTRRUPT
IRQ
XIRQ
SWI
ILLEGAL OPCODE
COP
CLOCK MONITOR
RESET

***********************************************************************

END

62

APPENDIX B - HARDWARE AND SOFTWARE PAGING SCHEME
.******* EXTENDB.ASC ******************************************************
2
3
5
6
7
8

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

TESTS EXTENQEQ MEMORY CONTROL
for a single 1M bit (128K byte) EEPROM split into 48KB + 5 x 16KB
$4000 - $FFFF
48K
COMMON PAGE
S0200 - S3FFF
16K
PAGES 0,1,2,3,4
A multiplexer is used to switch between address and port 0 lines
controlled by PD5 and A16 is controlled by /(PD5+A14+A15)
This ensures that Address A16 is a logic 1 whenever A14 or A15 are
high and that all three lines must be low for the paged memory between
addresses SOOOOO and SOFFFF.

SOURCE CODE
EPROM
ADDRESS
ADDRESS
0000
+-----------------------+ 00000
PAGE a
+ 04000
4000
~ - - - -

---

MAIN PAGE

0000
0000
0000
0000
3FFF

+----------------------+
PAGE 1
+----------------------+
PAGE 2
+----------------------+
PAGE 3
+-----------------------+
PAGE 4
+----------------------+

(Continued overleaf)

63

10000
HOOO
18000
1COOO
1FFFF

36
37
38

39
40

41
42

43
44
45

+-

*

*
*

46

47
48

*

.R_+
A14
I
------1 A
1
I MUX 1------------+
PD3
1
1
1
-----1 B
I
I
-+
1
1
+-··1
1
I
1
+--------+
1

+------+

A14

1-----------------+

A15

49
50

51
52

53
54
55
56
51
58

A15

+1

------1

""-+
A

1

I
PD4

MUX

1

------1 B

1

59
60

+---------------

1

I

I

1
-+

1

I

I

+-""'

1M BIT
EPROM

I
1

+----------+-------+

61
62

63
64
65
66

61
68
69
10
11
12

13
74

PD5

\

---------\
A14

\
\

\

----------1
AI5
"
---------/

\
NOR >0----------+------+ AI6
1

' _ _I

,

+--------------

PD3.PD4 AND PD5 • I AFTER RESET
SINCE PULL-UP RESISTORS FORCE HIGH STATE WITH PORT D AS INPUTS
WHICH DEFAULTS TO MAIN PROGRAM PLUS PAGE 0

15
16
11
18
79
80

********.*.****************************************************************

64

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127

00000000
00000001
00000004
00000006
00000007
00000008
00000009
00000024
00000025
00000040
00000040
00000026
00000080
00001000

PORTA
DORA
PORTS
PORTC
DDRC
PORTO
DDRD
TMSK2
TFLG2
RTII
RTIF
PACTL
DDRA7
REGS

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$00
$01
$04
$06
$07
$08
$09
$24
$25
$40
$40
$26
$80
$1000

68HCllG5 only

68HC11E9 only

****************************************************.~***.P~***************

RAM definitions

00000000

************************************************** •..• *~**~~~*~***********~*
ORG $0000
Real time in~r."',:,up~ !"outine counter
TIME
RMB
2

00000200
00004000
OOOOffcc

ROMBASEO
ROMBASE1
VECTORS

EQU
EQU
EQU

Avoid RAM (fron

$0200
$4000
$FFCC

$'= to SlFF)

_*** __________________ ._. _________________________ ••• ___ w••• ______________ _
$00000 - $03FFF
PAGE 0
$04000 - $OFFFF
MAIN
PAGE
- $10000 - $13FFF
PAGE 2 • $14000 - $17FFF
PAGE 3 = $18000 - $1SFFF
PAGE
SlCOOO - SlFFFF

(A16=0.A15=0.A14=0;
(A16=0)
(A16=1.A15=0.A14=O,
(A16=1.A15=0.A14=:'
(A16=1.A15=1.A14=O)
(A16=1.A15=1.A14=::

=> PAGEC='00100000
=> START='001XXOOO
.> PAGE1='00000000
=> PAGE2='00001000
=> PAGE3='00010000
=> PAGE4=\0001100O

PAGEn is added to 'xxOOOxxx to give the state of port
0(3) • 0(4) and 0(5) •
00000000
00000020
00000000
00000008
00000010
00000018

START
EQU
$00
PAGEO
EQU
$20
PAGEl
EQU
SOO
EQU
$08
PAGE2
$10
PAGE3
EQU
EQU
$18
PAGE4
ww** __ wwwwwwwww _____________ • ___________________________ w*. ____ * __________ _

65

128
129
130
131
132
133
134
135 00000200
13~ 00000204
137 00000208
138
139
140
141
142
l43
144
145
146
147
148 00004000
149 00004003
150 00004006
151 0000400a
152 0000400e
153 00004011
154 00004014
155 00004017
156 0000401a
157 0000401d
158 00004020
159 00004023
160 00004026
161 00004029
162 0000402c
163
164
165
166
167
168 0000402e
169 0000402f
170 00004033
171 00004035
172 00004038
173 0000403b
174 0000403e
175 00004041
176 00004042
177 00004045
178 00004048
179 0000404a
180 0000404d
181 00004050
182 00004051
183

*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

page 0 (lst half of EPROM)

*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

181cOO08
181dOO08
7e4014

org
LooPPO SSET
SCLR
JMP

ROMBASEO
PORTA, Y,IS08
PORTA, Y,I$08
MAINO

Toggle Port A-3
return to main page

*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

START OF MAIN PROGRAM
***********.*.**************************************** **************~*****

MAIN ROUTINE NOT UNDER INTERRUPT CONTROL
**************************************************************************

8eOlff
bd402e
181c0840
181d0840
bd4062
7e0200
bd406d
bd0200
bd4078
bd0200
bd4083
7e0200
bd408e
7e0200
20d8

RESET
LOOP

MAINO

MltIN3
MAIN4

ORG
LOS
JSR
SSET
SCLR
JSR
JMP
JSR
JSR
JSR
JSR
JSR
JMP
JSR
JMP
BRA

ROMBASE1
1$01FF
SETUP
PORTO, Y, 1$40
PORTO, Y, 1$40
CHGPAGEO
LOOPPO
CHGPAGEl
LOOPPl
CHGPAGE2
LOOPP2
CHGPAGE3
LooPP3
CHGPAGE4
LooPP4
LOOP

initialise RTI interrupt and OORs
main routine toggles port 0-2
select page 0
Toggle Port A-3
select page 1

Toggle Port A-4
select page 2
Toggle Port A-5
select page 3
Toggle Port A-6
select page
Toggle Port A-7
start loop again

**************************************************************************

INITIALISATION ROUTINE
**************************************************************************

Of
18ce1000
86ff
b71001
bH009
7fOOOO
7fOO01
4f

bHOOO
b71008
8640
bH025
bH024
Oe
39

SETUP

SEI
LOY
LOAA
STAA
STAA
CLR
CLR
CLRA
STAA
STAA
LOAA
STAA
STAA
CLI
RTS

'$1000
t$FF
ODRA+REGS
DDRD+REGS
TIME
TIME+1

Register address offset

make port A all outputs (68HCllG5)
make port 0 all outputs

PORTA+REGS
PORTO+REGS
n01000000
TFLG2+REGS
TMSK2+REGS

66

clear the RTI flag
enable RTI interrupt

184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228

**************************************************************************

Real time interrupt service routine

00004052
00004054
00004057
00004059
0000405c
0000405e
0000405f
00004061

8640
b71025
9601
b71004
deOO
08
dfOO
3b

RTISRV LDAA
STAA
LDAA
STAA
LOX
INX
STX
RTI

n01000000
TFLG2+REGS
TIME+l
PORTB+REGS
TIME

clear RTI flag
store counter in port B
get time counter
increment co·unter
save counter value in RAM

TIME

Return from interrupt

**************************************************************************

CHANGE PAGE
ace B (bits 3-5) contains the l's complement of new page number address

SOURCE CODE
ADDRESS
0000
4000

EPROM
ADDRESS
00000

+----------------------+
PAGE 0
+ 04000
+ - - - - - - - MAIN PAGE

0000
0000
00,00
0000
3FFF

+-----------------------+
PAGE 1
+----------------------+
PAGE 2
+--------------------+
PAGE 3
+---------------------+
PAGE 4
+----------------------+

PAGE 0
$00000 MAIN
$04000 $10000 PAGE
PAGE 2 - $14000 PAGE 3
$18000 PAGE
$lCODO -

$03FFF
$OFFFF
$13FFF
$ 17FFF
$lBFFF
$lFFFF

10000
14000
18000
lCOOO
IFFFF

(AI6=O,A15=O,A14=0)
(A16=0)
(A16=l,A15=O,A14=0)
(A16=l,A15=O,A14=1)
(A16=l,A15=l,A14=0)
(A16=l,A15=l,A14=1)

=>
=>
=>
=>
=>
=>

PAGEO=\OOlOOOOO
START=\OOlXXOOO
PAGEl=\OOOOOOOO
PAGE2=\000DIDOO
PAGE3=\00010000
PAGE4=\0001l000

**************************************************************************

67

229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
241
248
249

'"

00004062
00004062
00004065
00004067
00004069
0000406';

b61008
84c7
8b20
b11008
39

CHGPAGEO
LDAA
ANDA
ADDA
STAA
RTS

PORTD+REGS
1'11000111
IPAGEO
PORTD+REGS

0000406<1
0000406d
00004070
00004072
0000407.
00004077

b61008
84c1
8bOO
b11008
39

CHGPAGEI
LDAA
ANDA
ADDA
STAA
RTS

PORTO+REGS
"11000111
IPAGEl
PORTD+REGS

get port 0 data
make middle 3 bits low state
add PAGE descriptor to this

CHGPAGE2
LDAA
ANDA
ADDA
STAA
RTS

PORTD+REGS
''11000111
'PAGE2
PORTD+REGS

get port D data
make middle 3 bits low state
add PAGE descriptor to this

00004082

b6l008
84c1
8b08
b11008
39

00004083
00004083
00004086
00004088
0000408a
0000408d

b61008
84c1
8blO
b11008
39

CHGPAGE3
LOAA
ANOA
AOOA
STAA
RTS

PORTO+REGS
"11000111
'PAGE3
PORTD+REGS

get port D data

0000408e
0000408e
00004091
00004093
00004095
00004098

b6l008
84c1
8b18
b11008
39

CHGPAGE4
LOAA
ANOA
ADOA
STAA
RTS

PORTO+REGS
1%11000111
'PAGE4
PORTD+REGS

get port D data
make middle 3 bits low state
add PAGE descriptor to this
write back to port 0
(only bits 3, 4 and 5 are changed)

00004078
00004018
0000407b
0000407d
0000407f

·get port D data
make middle 3 bits low state
add PAGE descriptor to this
write back to port 0

(only bits 3, 4 and 5 are changed)

write back to port 0
(only bits 3, 4 and 5 are changed)

write back to port 0
(only bits 3, 4 and 5 are changed)

250

251
252
2S3
254
255
256
251
258
259
260
261
262
263
264
265
266
267
268
269
270
211
272
273
214
275
216
217
278
279
280
281
282
283

make middle 3 bits low state
add PAGE descriptor to this
write back to port 0
(only bits 3, 4 and 5 are changed)

**********.*****************************.*********************************

VECTORS
*********w****·************************************************************

OOOOffcc
OOOOffce
OOOOffdO
0000ffd2
0000ffd4
0000ffd6
0000ffd8
OOOOffda
OOOOffdc
OOOOffde
OOOOffeO
0000ffe2
0000ffe4
0000ffe6

4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000
4000

ORG
FDB
FOB
FOB
FDB
FOB
FOB
FDB
FOB
FOB
FOB
FOB
FOB
FOB
FOB

VECTORS
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET
RESET

EVENT 2
EVENT
TIMER OVERFLOW 2
INPUT CAPTURE 6 I OUTPUT COMPARE 7
INPUT CAPTURE 5 I OUTPUT COMPARE 6
SCI
SPI
PULSE ACC INPUT
PULSE ACC OVERFLOW
TIMER OVERFLOW 1
INPUT CAPTURE 4 I OUTPUT COMPARE 5
OUTPUT COMPARE 4
OUTPUT COMPARE
OUTPUT COMPARE 2

68

284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339

0000ffe8
OOOOffea
OOOOffec
OOOOffee
OOOOfffO
0000fff2
0000fff4
0000fff6
0000fff8
OOOOfffa
OOOOfffc
OOOOfffe

4000
4000
4000
4000
4052
4000
4000
4000
4000
4000
4000
4000

FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB
FOB

RESET
RESET
RESET
RESET
RTISRV
RESET
RESET
RESET
RESET
RESET
RESET
RESET

OUTPUT COMPARE 1
INPUT CAPTURE 3
INPUT CAPTURE 2
INPUT CAPTURE 1
REAL TIME INTRRUPT
IRQ
XIRQ
SNI
ILLEGAL OPCODE
COP
CLOCK MONITOR
RESET

*******************.******************************************************
-+t+++++++++++++++++++++++++++++++++++++++++++++++++++ +++~++++++++++++++++

page 1 (2nd half of EPROM)

-+t++++++++++++++++++++++++++++++++++++++++++++++++++++t++++++++++++++++++

00000200
00000204
00000208

181eOOl0
181d0010
39

org
LOOPPI BSET
BCLR
RTS

ROMBASEO
PORTA,Y, 1$10
PORTA,Y, 1$10

Toggle Port A-4

-+t++++++++++++++++++++++++++++++++++++++++++++++++++++t++++++++++++++++++

page 2 (2nd half of EPROM)

-+t++++++++++++++++++++++++++++++++++++++++++++++++++++t++++++++++++++++++

00000200
00000204
00000208

181c0020
181d0020
39

org
LOOPP2 BSET
BCLR
RTS

ROMBASEO
PORTA,Y, 1$20
PORTA,Y,'$20

Toggle Port A-5

*++++++++++++++++++++++++++++++++++++++++++++++++++++++t++++++++++++++++++

page 3 (2nd half of EPROM)

*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

00000200
00000204
00000208

18100040
181d0040
7e4026

org
LOOPP3 BSET
BCLR
JMP

ROMBASEO
PORTA, Y,U40
PORTA,Y,'$40
MAIN3

Toggle Port A-6
return to main page

*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++T++++++++++++

page 4 (2nd half of EPROM)

*+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

00000200
00000204
00000208

181c0080
181d0080
7e402e

org
LOOPP4 BSET
BCLR
JMP

ROMBASEO
PORTA,Y,'$80
PORTA,Y,'$80
MAIN4

Toggle Port A-7
return to main page

*****************~************************************ ********************

END

69

APPENDIX C -'C' LANGUAGE ROUTINES FOR METHOD B
1* CHGPAGE.C

*

C coded extended memory control for 68HCII

*1
*********************.*************.************* •• *** ••• **********.******

'*

HCII structure - 1/0 registers for MC68HCII *1

struct HCllIO (
unsigned char
unsigned char
unsigned char
uns igned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char
unsigned char

unsigned char

PORTA;
Reserved;

Reservedl;

OORC;
PORTO;
OORO;
PORTE;

End of structure HCIIIO

Port A - 3 input only. 5 output only *1

/*
/*
/*
1*
/*

Motorola's unknown register 2 *1
Data direction for port C *1
Port 0 */
Data direction for port D *1
Port E *1

Motorola's unknown register */
1* Parallel I/O control */
/* Port C */
/* Port B - Output only *1
/* Alternate port C latch *1

PIOC;
PORTC;
PORTS;
PORTCL;

);

1*

'*1*

*'

*********.*****************.**************.**.*****************.***-******

'define regbase (*(struct HCllIO *) OxIOOO)
typedef unsigned char byte;
/* Some arbitrary user defined values

'define
'define
'define
Idefine

pageD Ox20
pagel OxOO
page2 Ox08
pagemask Oxc7

*'

1* Macro to generate in line code *1

'define chgpage(a) regbase.PORTO

=

(r~gbase.PORTO

, pagemask) + a

*'

1* Function prototype
void func_chgpage(byte pI;
1* Externally defined functions in separate pages */
/* Dummy function in page 0 *1

extern void func_in_pageO();

extern void func_in_page2();

1* Dummy function in page 2 *1

70

* ---------------- compiled assembly code ---------- C source code -----------------mainO
6 0000

main:

fbegin
chgpage(page2),
1* Change page using inline code *f

8 0000
0003
10 0005
11 0007

f61008
c4c7
cb08
f71008

1dab
andb
addb
stab

S1008
1199
*8
S1008

jsr

func_in_page2

func_in_page2(),
f* Call function in page 2 *f
13 OOOa >bdOOOO

func_chgpage(pageO),
/* Change page using function call *f

15 OOOd
16 0010

cc0020
8d04

1dd
bsr

*32
func_chgpage
func _ in _pageO 0 ;
1* Call function in page 0 *f

18 0012 >bdOOOO

jsr

20 0015
21 0016

rts
fend

39

func_in_pageO

void func_chgpage (p)
byte p;

24 0016
25 0016

37

func_chgpage:
pshb

fbegin

27
28
29
30
31

f61008
c4c7
30
ebOO
f71008

1dab
andb
tsx
addb
stab

S1008
E99

31
39

ins
rts
fend
func ... in_paqe2
func_in_pageO

chgpage (p) ,
0017
001a
001c
001d
OOlf

33 0022
34 0023
35 0024
36
37
38

impor.t
import
end

O,X
S1008

71

72

AN433
TV on-screen display using the MC68HC05T1
By Peter Topping
Motorola Ltd .• East Kilbride. Scotland

INTRODUCTION
The "'T"' membersofthe MC68HC05familyof MCUs provide
a convenient and cost effective method of addi ng on-screendisplay (OSD)1o "TVsandVCRs. As well as the OSDcapability,
they include 8 Kbytes of ROM (adequate for Teletext,
frequency-synthesis, stereo and OS D), 320 bytes of RAM, a
16-bit timer and 8 pulse-width-modulated D/A converters.
The MC68HC(7)05T7/8 also includes IIC hardware and, by
uSing a 56/64 pin package, 4 ports of I/O independent of the
OSD, serial and D/A outputs. It is thus suitable for large full-

feature chassis. The MC68HC05Tl is in the middle of the
price/performance range and includes most of the features
ofthe MC68HC05T8 but in a40-pin p'ackage. This is achieved
by sharing I/O with the other pin functions (SPI, OSD, D/Al.
Even if all these features are used there IS sufficient I/O for
most applications. The low cost MC68HC05T4 has 5 Kbytes
of ROM and 96 bytes of RAM making it suitable for simpler
(mono, non-Teletext) applications.

68HC05T1 OSD FEATURES
Programmable display of 10 rows of 18 characters
•

•

Character colour selectable from 4 colours/row

•

4 character sizes (normal, double height and/or width)

•

Selectable half-dot black outline.

24 byte (18 data + 6 control) single row architecture
Sellable in software to anyone of four standards

•

Zero inter-row and inter-column spacing

•

64 user-defined mask-programmable 8 x 13 characters

Software programmable (start, stop and colo~r) window

Half-dot character rounding

Programmable horizontal position

OSD CHARACTERISTICS
The HC05TX series have an OSD capability of 10 rows of 18
characters. Each row can contain characters of four colours
selected from the eight available colours (black, blue, green,
cyan, red, magenta, yellow and white). The rows can independently select double height and/or double width and the
start and stop positions of a background window of any
colour. The signals sent to the "TV are Red, Green, Blue, fastblanking and half-tone. Separate horizontal and vertical synchronisation inputs are required.

are 18 data registers (one for each character) and 6 control
registers arranged as shown below. The table is for the Tl ,
some of the control bits are different in the T4/7/8.
$20-$31

Read: status, Write: colours 1 & 2 and
outline enable.

$33 C34

Colours3&4.

$34
The OSD architecture employed includes only a single line of
display RAM. This makes the software more complicated but
reduces the silicon area required to implement the OSD
function. The software is required to update the display RAM
on a regular basis. When operating in the 625-line PAL
standard the updates must occur at 1.66 ms (26 lines)
intervals in order to display adjacent lines. TheOSD hardware
can generate an interrupt when an update is required. There

OSD Data registers.

$32 CAS

RAD Row address, character size, into enable,
RGBinvert.

$35 WCR OSD & PLL enable, Window enable and
start column.
$36 CCP Window colour and end column.
$37

73

HPD Horizontal position, standard selection.

The OSD display is timed from an on-chip 14 MHz oscillator
which is phase locked to the lY's line synchronisation pulses.
The vertical synchronisation depends on the standard in use.
Four standards are available (15.75 kHz/60 Hz, 31.5 kHz/120
Hz, 15.625 kHz/50 Hz and 31.25 kHz/100Hz). The standard is
selected by control bits in the Tl/2 but is automatic in the T4 and
the T7/8.

8 x 13 (for 625-line standard). This allows continuous graphics.
Half-dot interpolation hardware doubles the apparent resolution to produce smoother characters. A software selectable
black outline (a half-dot wide) is also implemented in the
hardware. Because the half-dot circuitry has to know the
information for the next line of pixels, a 14th line is available in
the character generator ROM to facilitate look ahead. The
vertical height of a character is 26 lines (52 induding interlace)
and the horizontal width is 2 2/7 jI.S 11/7 jI.S per half pixel).

64 OSD characters are mask programmed along with the user
ROM. The spacing and full size of the characters is the same at

SOFTWARE
There are several approaches to writing OSD software to
operate with the single line architecture. The choice will affect
the amount of ROM and RAM used. One principle is to have a
separate interrupt routi ne for each type of row to be displayed.
This method will use little RAM but will be inefficient in its use
of ROM. The other approach is to write a single interrupt
routine which transfers display information from a block of
normal RAM to the display RAM as it is required for each new
line. This method will be more ROM efficient but requires a
RAM location for every display character. The amount of RAM
used depends on the maximum amount of data which has to be
displayed at anyone time. The choice between these two
methods will depend on the type of data to be displayed. The
first method may be better if much of the displayed data is
fixed. This could be, for example, a series of menus. The
second method will however be more appropriate if the data is
mostly variable. This will usually be the case in conventionallY
applications.
This application note describes an implementation of the
second of the above approaches. A block of RAM is used to
contain a copy of all the data to be displayed. The size of this
block can be changed to reflect the number of rows and the
numberof characters perrow. The choice made in the example
described here is 8 rows of 1·6 characters. This is slightly less

than the maximum available and was chosen because the total
numberof characters (128) corresponds to the available page 1
RAM in the MC68HC05Tl. The choice of 16characters perrow
also slightly simplifies the software. The software allows any
eight of the ten available rows to be used but only the first 16 of
the 18 available characters. This choice does not prevent
access to the right-hand-side of the screen as the display can
be moved to the right under software control. The use of page 1
for the RAM does not incur any significant compromise in
execution time. It also leaves free the page 0 RAM for the rest
of the lY control software, Which would be made less efficient
if it had to use page 1 RAM, where direct addressing and bit
manipulation instructions cannot be used. This choice slightly
increases the ROM used by the OSDcode, as3-byte extended
store instructions sometimes need to be used to write data to
the RAM used for OSD characters.
The l-byte indexed addressing mode can however be used in
page 1 . This addressing mode can access up to address $1 FE
and is made use of in the example software. For example the
OSDCLR routine used to initialise RAM locations used for OSD
employs.a CLR DRAM-l,X instruction. DRAM is the start of
page 1 RAM at $100 so DRAM-l evaluates as $FF a 1-byte
offset.

INTERRU PT ROUTINE
To save RAM only three (RAD, CAS _& CCR) of the six control
registers are loaded in this way. The pointer OSDL is multiplied
by 3 using the table M3, as this is quicker than shifting and
adding. In this example the other registers are loaded by the
main program and therefore have fixed val ues for each display.
The fixed registers are Colour 3/4 ($33), Window enable/start
column ($35) and Horizontal position delay($37). As this choice
would not allow windows to be enabled on individual rows,
window enable is controlled by the un-used bit (6) in the RAM
byte used to update the Colour 1/2 register (CAS). This choice
offixed registers limits the flexibility of thedisplay but clearly all
registers can be updated on a line-by-line basis if more RAM is
used. The limitations imposed by this choice are that colours 3
& 4, the window start column and the horizontal position apply
to a whole display rather than to individual lines. In practice
these constraints were not found to be significant restrictions
for the displays required for lY use.

The OSD update interrupt routine (NLlNE) shown in the
program listing transfers data from page 1 RAM to display RAM
each time an interrupt occurs. The first operation is to increment the pointer which selects the next row number. This
pointer (OSDU is subsequently used to transfer the appropriate data from page 1 RAM to the OSD RAM. So that any row
number can be used the pointer selects the number from a
table unique to each type of display. The appropriate table is
determined by the value of UNO. The pointer is incremented
until the corresponding row number is zero when the pointer is
reset to zero. This allows any sub-set of up to 8 of the 10
available rows to be used. The next row number (ORed with
the character size information contained in RAM) is written into
the appropriate register ($34). The row number in this register
is compared by the OSD hardware with the current position of
the raster. When they match, an interrupt is generated and the
next interrupt routine is performed. Theothercontrol registers
are then updated from the page 0 RAM locations, which are
used for this purpose.

74

The interrupt routine then transfers the relevant OSD data from
page 1 RAM into the OSD data registers. This is done using
linear, repetitive code in order to minimise the time taken by
the interrupt routine. The code used uses 8 cycles (4 jlS) for
each byte transferred. Less ROM space would be utilised if a
loop was employed but this would use 28 cycles per byte. The
best choice depends on whether time or ROM use is more
critical. The example code includes a cycle count to calculate
the length of the interrupt routine. The time taken is 121 ± 41-1s.
This includes the time taken by the interrupt itself. An alternative method of OSD data transfer (TOSD2) using a loop is

included as comments in the listing. It would take an additional
1651-1s.
The last task performed by the interrupt routine is to control any
character or window flashing. The software allows one or two
characters (on a selected row) and one window (on the same or
a different row) to be flashed at a rate determined by the MCU' s
timer. This function could be performed outwith the interrupt
routine in the main program and the time taken to perform it is
not included in the figure given above.

MAIN OSD PROGRAM
The remainder of the OSD control program does not write
directly to most of the display registers. It simply puts the
required display and control information into the blocks of RAM
allocated for this purpose, together with supplying the coordinates of ·any required flashing characters or windows. It
must, however, write to the display" control registers not
updated by the interrupt routine; in this example these are $33,
$35 and $37. The program has 4 main parts. These are the idle,
channel name table, program/channel number and analogue
displays. The idle display applies when no transient display (eg
program number and channel number or name) is on. The OSD
idle condition is selectable between blank and a small program
number at the bottom right hand corner of the screen.
The OSD example program (assembler listing included) is just
part of the code required to control a TV set. This program was
incorporated in HC05Tl software along with four other modules. These were the base module (idle loop, transient control.
local keyboard, IR, IIC and resetl. the tuning module (PLL,
analogue and NVM control), the stereo module (stereoton and
Nicam) and the Teletext module (FLOF level 1 .5).

The microprocessor in a TV application will usually need to
handle the reception of IR commands. Polled methods of IR
reception are most effective if the time made unavailable to
them by interrupts is minimised. It is for this reason that the
illustrated OSD interrupt routine was written to execute as fast
as possible. This is, however, not so much of a problem if the
TCAP facility is used for IR reception. When a falling edge
occurs, the timer value is saved and it does not matter if the
interrupt which processes this information is not serviced until
several hundred microseconds later. The allowable size of this
delay will of course depend on the IR protocol in use. The bi:
phase protocol used with the example OSD software (transmitter chip: MC144105) has a minimum spacing of 1 ms
between consecutive edges.
The next section describes the OSD features of this software.
Some of the data used in the OSD is passed from other
modules (particularly the tuning module) The same RAM
allocation file was used in all modules so this part of the listing
shows the locations used to pass data between them.

OSD FEATURES PROVIDED INTHE EXAMPLE PROGRAM
Program change

Channel mode

When keys 0-9, PC- or PC+ are pressed, the new program
number appears (in cyan) at the bottom-right-hand corner of
the screen in double height/double width characters and stays
for 5 seconds after the last change. Above this display either
the channel name (if one has been defined) or the channel
number is shown (normal size). After 5 seconds this display
times out and there is either no display or a permanent normal
size program number display. This is selectable using the
Teletext MIX key.

When the PIC key is pressed, the program number and channel
name (or number) is displayed for 5 seconds as an indication of
the current status. If it is pressed again during this period, the
TV changes to channel mode. This will remain for 30 seconds
after the last key-press. The display (in yellow) shows the
program number as in program mode along with the channel
number. The channel number flashes to show that it will be
changed if a number or PC- or PC+ key is pressed. New
channels can be selected. If the STORE key is pressed then the
current channel is stored against the current program number.
If no key is pressed for 30 seconds, the TV returns to program
mode. If the channel has been changed but STORE not
pressed then the TV will retune back to the channel stored
against the current program number.

For program numbers of 10 and over, three keys are required.
They are selected by first pressing" -". Two flashing dashes
are displayed, the first 0-9 key (only 0-4 valid) will be taken as
the tensdigitandthe second as the units digit. If a new program
number has not been selected within 30 seconds, the TV
returns to the previous display (nothing or the old program
number).

75

Automatic ..arch

lines is displayed. Each line (identified by a .. station" number
in the leftmost column) contains a channel number, standard
and the associated name. All ofthis data is user definable.

When SEARCH is pressed the lV goes into the channel
mode and the on screen display is as described above. The
channel number is incremented at a rate of 2 per second until
a signal is found. The search then stops. A press of STORE
returns the lV to program mode, storing the new channel
against the current program number.

One character on the screen flashes to indicate the current
position of the cursor. The character at the cursor position
can be changed through 0-9, A-Zand space by pressing PC+
or PC- (0-9 for channel number digits and PAlISECAM for
standard). When a character (or the standard) is changed, its
colour changes fromyellowto red. The cursor is moved to the
left and right by the Teletext REDand GREEN keys and up and
down by the BLUE and YELLOW keys. The current line
appears in a light blue (cyan) window as opposed to the dark
blue window used for the other lines. The whole table scrolls
when the cursor is required to go beyond the bottom (or top)
of the current display.

Analogues
When any of the analogues are selected the appropriate logo
is displayed along with a horizontal bar indicating the current
value in the DIA convertor (full-scale 63). Display returns to
default (nothing or program number) 5 seconds after the last
change. If no analogue is selected the volume'is shown (and
adjusted) when the ANALOG UE +1- keys are used.

To save a name the STORE key is pressed. This will save the
name and standard on the current line against its channel
number. This is indicated by the colour. of any changed
characters returning to yellow. Any changes which have
been made to lines other than the one being stored are lost.
Channel 00 cannot have a name. The procedure for removing
a name from the table is to set the channel number to zero
and then to save the line. Any name left on the line will not be
used. The table display is exited by pressing the Teletext
INDEX key. The function of each key is shown at the bottom
ofthe display.

Channel name table
Up to 24 channels can have a 4 character name and standard
bit associated withthem.lf the channel number and standard
of one of these entries in the table correspond to those
selected by the current program number then the name is
displayed along with the program number when the program
is selected or when PIC is pressed. Entry of names is done
using the Teletext I NDEX key When itis pressed a table of six

76

EXAMPLE PROGRAM
1
2
3

****************************************************************************

4

TV/Teletext/OSD/Stereo program (MC68HC05Tl/8).

5
6
7
8
9

On-Screen-Display module

* This software was developed by Motorola Ltd. for demonstration purposes. *
No liability can be accepted for its use in any specific application.
Original software copyright Motorola - all rights reserved.

10
11
12
13
14
15
16
17
18
19
20
21

25th May' 90

P. Topping

IMPORT

CHEX, CBeO, READ, WRITE, CDISP2

EXPORT
EXPORT

NLINE, pease, DRAM, ANOSD I PROSP, CHST
CUP, COWN, CLFT, CRGT, PLUS, MINUS, SAVE, OSDLE, OSDEF

LIB

RAMTl . 505

22

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

SECTION.S .RAM,COHN
********************************************************

*

Teletext RAM allocation.

00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007
00000008
00000009
OOOOOOOa
OOOOOOOb
OOOOOOOc
OOOOOOOd
OOOOOOOe
OOOOOOOf
00000010
00000011
00000012
00000013
00000014
00000015
00000016
00000017
00000020
00000027
0000002a
0000002d
00000030
00000033
00000036
OQOOO039
0000003a
00OOO03e
0000003f
00000040
00000041
00000042
00000046

00000047
00000048

SUBl

Rl
R2
R3
Cl
C2
C3
c4
c5
C6
SUB2
R4
R5
R6
R7
SUB3
R8
R9
Rl0
Rll
PH
PT
PU
LIFO
PAGE
PAGO
PAGl
PAG2
PAG3
PAGC
PAGI
PDP
ACC
WACC
ADDR
DPNT
SUBADR
IOBUF
STAT2

LINKC
STAT3

RMB
RMB

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
9
7
3
3
3
3
3
3
1
4
1
1
1
1
4
1

mode register
page request address register
~age r: q . data r: g . col. ~

;:f':

3
4

pgu.
ht.
hUe

5
6

mt.
rou.

2

display
display
display
display

chapter register
control register (normal)
control register (news/sub)
mode register

active chapter register
active row register
active column register
active d:ta re9 !ster

2nd
3rd
4th
LINKED PAGE No. LIFO BUFFER
PAGE No. INPUT BUFFER
ACO PAGE No.

ACl PAGE No.
AC2 PAGE No.
AC3 PAGE No.
CYAN PAGE No.

INDEX PAGE No.
PAGE DIGIT POINTER
DISP, RED,

GREEN,

YELLOW AC. eIR.

WORKING ACC No.
IIC ADDRESS
IIC DATA POINTER FOR WRITE
IIC SUB-ADDRESS
IIC BUFFER, +2 , +3 RSaVD FOR PLL
0: ROW24 FETCH FLAG

1: REMOTE REPEAT ING
2: SEARCH/STANDBY IIC LOCK
3: STANDBY STATUS
4: UPDATE PENDING
5: DIFFERENCE FOUND
6: NO TELETEXT TRANSMISSION
7: MIXED
LINK OPTIONS
0: CYAN
LINK ON
1: YELLOW LINK ON
2: GREEN LINK ON
3: LINKS/ROW24 ON

RMB
RMB

77

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

* '* * * * * * * * * * * * * '* * * * * * * * * * ** '* * * * * * * * * * * * * * '* * '* * '* ** * * * * * * * * *
General RAM allocation ..

**-*****************************************************
00000049
0000004a
0000004b
0000004c
0000004d
0000004e
0000004f
00000050
00000051
00000052
00000053
00000054
00000055
00000056

W1

ItMB
ItMB
ItMB

W2
W3

RMB
RMB

COUNT
KOUNT
CNT
CNT1
*CNT2
CNT3
CNT4
CNT5

ItMB

PLLHI
PLLOW

Tim

STAT

RMB
RMB
RMB

RHB
RMB
RMB
RMB
RMB
RMB

1
1

1
1
1
1
1
1
1
1
1
1
1
1
1

PLL DIVIDE RATIO MSB
PLL DIVIDE RATIO LSB
WORKING
LOOP COUNTER
LOCAL KEYBOARD COUNTER

12 .. SmS (itlo, free running)
12.SmS (ino, reset every is during transient)
3.25 S (inc, store timeout)
3.25 S (dec, automatic standby timeout)
12.SmS (cleared for row24 delay when page arrives)
12. ems (inc, transient mute)
TRANSIENT DISPLAY SECONDS COUNTER
0: TV!TELETEXT

1:
2:
3:
4:

00000057

STAN

RMB

00000058
00000059
0000005a
0000005b
0000005c
0000005d
0000005e
0000005!
00000063
00000064
00000065
00000066
00000067
00000068
00000069
0000006a
0000006b
0000006c
0000006d
0000006e

PWR

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

PROG
CHAN
DISP
FTUNE
AVOL
KEY
NOMO
IRRA1
IRRA2

IRRA3
IRRA4
DIFFH
DIFFL
IRK
IRL

IRCODE
IRCNT
IRCKCT
OLOIR

1
1
1
1
1
1
1
4
1
1
1

lIC R/W

BOLO
IR REPEAT INHIBIT
TRANSIENT DISPLAY ON
5: TIME BOLO
6: SUB-PAGE MODE
7: IR TASK PENDING
0: KEY FUNCTION PERFORMED
1: LOCAL REPEATING
2: PIc PROG : 0, CHAN :
3: MUTE (TRANSIENT)
4: OSD STATUS TRANSIENT
5: MUTE (BUTTON)
6: COINCIDENCE MUTE
7: SEARCH
$55 AT RESET, $AA NORMALLY
CURRENT PROGRAM NUMBER
CURRENT CHANNEL NUMBER
CURRENT DISPLAY NUMBER
FINE TUNING REGISTER
VOLUME LEVEL
CODE OF PRESSED l\:EY (LOCAL)
LED DISPLAY RAM
IR INTERRUPT TEMP.

i.

1
1
1
1
1
1
1
1

IR TIME DIFFERENCE
IR CODE BIT
COLLECTION

********************************************************
RAM allocation for Stereoton.

********************************************************
0000006!
00000070
00000071
00000072
00000073
00000074
00000075
00000076
00000077
00000078
00000079
0000007a

POI;LTM
TONEA

RMB
RMB

LBAL

RMB

0000007b

VAV

RMB

0000007c
0000007d
0000007e
0000007!
00000080
00000081

MONCNT
STECNT
DULCNT
ElU\CNT
RCOUNT
RANGE

RMB
RMB

00000082

TEMP

RMB

LVL
LVR
HVL
HVR
TONE
MATRIX
MATNO
WS1
WS2

RMB
RMB
RMB
RMB

RMB
RMB
RMB
RMB
RMB

RMB
RMB

RMB
RMB

1
1
1
1
1
1
1
1
1
1
1
1

Poll timer
Tone (unadjusted for loudness)
Loudspeaker balance variable
Loudspeaker left volume
(reg 1)
Loudspeaker right volume
(req 2)
Headphone volume left
(reg 3)
Headpbone volume riqht
(req 4)
Tone variable (Bass/Treble)
(req 5)
Current matrix
(reg 6)
Present mode (mono/stereo/lan 1/11.12/12.11)
Workspace 1
(no interrupt useaqe
Workspace 2
for these .please .. )

1
1
1
1
1

Mono ident count
stereo ident count
Dual lang ident count
Error ident count
Ident countdown
Total ident poll number

i

78

Ident detection
variables

23
23 00000083
23

STAT5

o

rum

23

23

VCR
OSD NAME TABLE
OSD DEFAULT PIC NUMBER
ANALOGUE OSD ON
NAME-TABLE STANDARD
STANDARD CHANGED
RE-INITIALISE TELETEXT

4
5

23

23

6
7

23

23

LOUDNESS

1
2
3

23

23 00000084
23
23 00000085

STAT6

rum

0: 2-DIGIT PROGRAM ENTRY

THPRG

rum

TEMPORARY PROGRAM NUMBER

23

********************************************************

23

osc RAM allocation.

23

23
********************************************************

23

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

00000086
00000087
00000088
00000089
0000008a
0000008b
0000008c
0000008d
0000008e
0000008f
00000090
00000091
00000092
00000093
00000094
00000095
00000096
00000097
00000098
00000099
0000009a
0000009b
0000009c
0000009d

000000ge
0000009f
OOOOOOaO
23 OOOOOOal
23 000000a2
23
23
23 000000a3
23 000000a4
23
23 000000a5
23
23 000000a6

RAU5

ROW 1, colour
Row address ,
Window colour
ROW 2, colour
Row address ,
Window colour
ROW 3, colour
Row address ,
Window colour
ROW 4, colour
Row address ,
Window colour
ROW 5, colour
Row address ,

CCR5

Window colour

CAS 6

ROW 6, colour
Row address ,
Window colour
ROW 7, colour
Row address ,
Window colour
ROW 8, colour
Row address ,
Window colour

CAS 1

RAUl
CCRl
CAS2

RAU2
CCR2
CAS3

RAU3
CCR3
CAS4

RAU4
CCR4
CAS 5

RAU6
CCR6
CAS7

RAU7
CCR7
CAS8

RAU8
CCR8

1/2 , outline enable
character size
, end column
1/2 , outline enable
character size
, end column
1/2 , outline enable
character size
, end column
1/2 , outline enable
character size
, end column
1/2 , outline enable
character size
, end column
1/2 , outl.ine enable
character size
, end column
1/2 , outline enable
character size
, end column
1/2 , outline enable
character size
, end column

OSDL
LIND
BROW
BCOL
WROW
*ROWl

rum
rum
rum
rum
rum
rum

ANAL
ANAF

rum
rum

TEHP2

rum

000000a9
OOOOOObf

STACK
SP

rum
rum

22

00000000
00000000
00000000
00000003

KEYI
KEYO
KEYIO
SERO

EQU
EQU
EQU
EQU

$00
$00
$00
$03

OOOOOOOa
OOOOOOOb
OOOOOOOc
OOOOOOOd

VOLU
CONT
BRIL
SATU

EQU
EQU
EQU
EQU

$OA
SOB
SOC
SOD

D/A 2
D/A 3
D/A 4
D/A 5

00000005
00000006
00000004
00000005
00000006
00000005
00000003

Ll
L2
WIDE
PST
VCR
LOUD
HUT

EQU
EQU
EQU
EQU
EQU
EQU
EQU

$05

Lang. 1 indicator bit
Lang_ 2 indicator bit
Wide matrix bit
Pseudo-stereo matrix bit
VCR. active bit
LOUDness effect active bit
Mute indicator bit

00000080
00000019

STADR
EQU
NORMVOL EQU

$80

CURRENT OSD ROW POINTER
ROW TABLE INDEX
CHARACTER FLASH ROW
CHATACTER FLASH COLUMNS
WINDOW FLASH ROW
FIRST ROW No. (NAME TABLE)

UNUSED

23

23
23
23
23
23
23
23
23

1

23

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

$06

$04
$05
$06

$05
$03
&25

79

23 BYTES USED FOR STACK
(1 INTERRUPT AND 9 NESTED SUBS)

JPoe
JP09
JPl0
JPll

IN
IN
IN
IN

EVB
EVB
EVB
EVB

Stereoton address
(lIe)
normal volume (mid bal.ance)

(LEDOUT)
(LEDOUT)
(MATRIX+LEDOUT)
(.
.)
(STAT3+LEDOUT)
(STAT3)
(MATRIX+LEDOUT)

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Equates.

********************************************************

OORB
DDRC
DDRD

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$00
$01
$02
$03
$04
$05
$06
$07

Port
Port
Port
Port
Port

TCR
TSR
ICRH
ICRL
OCRH
OCRL
TDRH
TDRL
MISC

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$12
$13
$14
$15
$16
$17
$18
$19
$lC

Timer control register.
Timer status register ..
Input capture register, hi9h.
Input capture register, low.
Output compare register, high.
Output compare register, low.
Timer data register, hi9h.
Timer data reqister, low.
Misc. register

OSO

EQU
EQU
EQU
EQU
EQU
EQU
EQU

$20
$32
$33
$34
$35
$36
$37

18 OSD data registers
Color , status register
Color 3/4 register
Row address , character size

$39
$3A
$3B
$3C
$3D
$3E
$3F

00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007

PORTA
PORTB
PORTC
PORTO

00000012
00000013
00000014
00000015
00000016
00000017
00000018
00000019
00000010

~ORA

00000020
00000032
00000033
00000034
00000035
00000036
00000037

CAS

C34
RAe

WCR
CCR
HPD

00000039
0000003a
00000031;>
00000030
0000003d
0000003e
0000003f

MAD

MFD
MCR
MSR
MCR
TR1
TRZ

EQU
EQU
EQU
EQU
EQU
EQU
EQU

00000000

DRAM

RMB

71

72
73

Port A address
Port B
Port C
0

A data direction
B
C
0

r:q .

Window/Column register
Column/color register
Horizontal position delay
M-bus
M-bus
H-bus
M-bus

address register
frequency divider
control register
status register
H-buB data reqiater
Test 1, OSD/Timer/PLM
Test 2, EPROM

SECTION .RAM2

41

42
43
44
45
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

.

********************************************************

128

SECTION .ROM2

•• w• • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

AAAA~AAAAAAAA AA

OSD update routine - row number , data.
********************************************************

00000000
00000002
00000003
00000005
00000007
00000008
OOOOOOOb
OOOOOOOd
OOOOOOOf
00000012
00000014
00000016
00000018
0000001a
00000010
OOOOOO"ld
0000001e
00000020
00000022
00000024
00000026
00000028

74
75
76 0000002b
77 0000002d
78 0000002f
79 00000031
80 00000033
81 00000035
82 00000037

>b600
40
>b700
>bbOO
97
>d60000
27f6
>beOO
>deOOOO

NLINE
STAG

>eaOO

b734

>e6£0

b720
>e6fl
b721
>e6f2
b722
>e6f3

SKIPW
LLOK
TOSD1

OSDL

ADD

TAX
LDA
BEQ
LOX

LTABO,'x
STAG
OSDL

ORA
STA
LOA
STA
BCLR
ROLA
ROLA
BCC
BSET
LOA
STA
LOX
LOX
LOA
STA
LOA
STA
LDA
STA
LOA

3
3

OSOL
LIND

r.cx

>e600

b732
If35
49
49
2402
1e35
>e600
b736
>beOO
>deOOOO

LOA
INCA
STA

M3,X
RADl,X
RAe
CASl,X
CAS

7,WCR
SKIPW
7,WeB.
CCR1,X

CCR
OSDL
H16,X

4
3
2
5
3
3
5
4
4
4
4
5
3
3
3
5
4
4
3
5

6
10
13
15
20
23
8
12
16
20
24
29
32
35
38
43
47
51
7
12

e6f4
0000003d b724
0000003f >e6£5
oooooon b725
00000043 >e6f6
00000045 b726
00000047 >86f7
00000049 b727
0000004b >86f8
0000004d b728
0000004f >e6f9
00000051 b729
00000053 >e6fa
00000055 b72a
00000057 >e6fb
00000059 b72b
0000005b >.6£0
0000005d b72c
0000005f >e6fd
00000061 b72d
00000063 >e6fe
00000.065 b72e

106 00000067 >e6ff
107 00000069 b72f

108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163

STX
LOX
STX
*OSDOOP LDX
LOA
DEC
LDX
STA
DEC
BNE
'*TOSD2

OSO+3
09001£
>b600
2719
b634
a40f
>bl00
2611
>b600

CHSLK

CMP

BNE
LDA
AND
TAX
BSR
LOX
LSRX
LSRX
LSRX
LSRX
BEQ
BSR

a40£

97
adlb
>beOO
54
54
54
54
2702
ad11
200e

>b600

.620
a43f
2609
e620

RAD

t$OF
BROW
NCHBK
BCOL
t$OF
SPFL
BCOL

NCHBK
SPFL

BRA

NOBLK

WBLK

LOA
BEQ
LDA
AND

WROW
NOBLK

CMP

NOBLK
SPFL

&4cO

abOe
e720
81
6f20
81

4,CNT,WBLK
BROW
NCHBK

NCHBK

270a

b634
&40f
>bl00
2602
If35
80

BRCLR
LOA
BEQ
LDA
AND

NTSP

BNE
BCLR
RTI
LDA
AND
BNE
LDA
AND
ADD
STA
RTS
CLR
RTS

5
3
j

3
2
3
3
3
3
2
34
3
3
3
3
3
3
34
3

25
28
31
34
36
39
42
45
48
50
84
87
90
93
96
99
102
136
139

CHARACTER BLINK

1st CHARACTER

(LS NIBBLE)

IF MS NIBBLE ZERO THEN NO
2nd CHARACTER
WINDOW BLINK

RAD

t$OF
WROW
NOBLK
7,$35
148
OSD,X

t$3F
NTSP
OSD,X
f$CO
t$OE
OSD,X
OSD,X

81

6 + 4
2
3
4
2
2
5
6

10
12
15
19
21
23
28
34

371 +/- 8
with INT 381 +/- 8 cycles
ie 190.5 +/- 4 us

165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220

********************************************************
aso idle condition.

************************.*******************************
OOOOOO&e >060004
000000b1 >1600
000000b3 2002

OSDEF

3,STATS,DOFF

BRSET
BSET
BRA

3,STAT5
OSDLE

000000b5 >1700

DOFF

BCLR

3,STAT5

000000b7 9b
000000b8 >1900
OOOOOOba >1500

OSDLE

SEI
BCLR
BCLR

4,STAT5
2,STAT5

NOT ANALOGS
NOT NAME TABLE

LOX
CLR
DECX
BNE

.29
CAS1-1,X

CLEAR PAGE 0
OSD CONTROL
BYTES

JSR

CDISP2
$30
$31
3, STAT5, SICPDEF
DRAM+12
$30
DRAM+14
$3'1

OOOOOObo aeld
OOOOOObe >6fff
00000000 Sa
00000001 26fb
00000003 >odOOOO
00000006' 3f30
00000008 3£31
OOOOOOoa >06000a
OOOOOOod >c60000
OOOOOOdO b730
000000d2 >c6000e
000000d5 b731
000000d7-' 5f
000000d8 a67f
OOOOOOda ad1b
OOOOOOdo a620
OOOOOOde b737
OOOOOOeO a6a3
000000e2 >050002
000000e5 a6a6
000000e7 >b700
000000e9 a610
OOOOOOeb >b700

DooP

CLR

SICPDEF

PHD

OOCOOOed a60c
OOOOOOe£ >b700
000000£1 >a600
000000£3 >b700
000000£5 9a
000000f6 81

000000f7 40
000000£8 >b700
OOOOOOfa 50
OOOOOOfb >6fff
OOOOOOfd >b300
OOOOOOff 26f9
00000101 81

OSDCLR
DCLR

CLR
BRSET
LOA
STA
LOA
STA
CLRX
LOA
BSR

DOOP

'127
OSDCLR

LDA
S,TA
LDA
BRCLR
LOA
STA
LOA
STA

1\00100000
HPD
1'10100011

LOA
STA
LOA
STA
eLI
RTS

t$OC
ANAL
,AVOL
ANAF

INCA
STA
INCX
CLR
CPX
BNE
RTS

PROGRAM NllMBER

2, STAT4, PHD
1\10100110
CAS1
1%00010000
RAD1

W1
DRAH-l,X

W1
DCLR

82

HORI~ONTAL

COLOR 1,0 -

POSITION : ZERO
RED,

CYAN, EDGE ON

PROGRAM MODE ?
NO, COLOR 0 - YELLOW
SINGLE WIDTH/HIGHT
DEFAULT TO VOLUME

222
223
224
225
226
221
228
229
230
231
232
233
234
235
236
231
238
239
240
241
242
243
244
245
246
241
248
249
250
251
252
253
254
255
256
251
258
259
260
261
262
263
210
211
212
213
274
215
276
211
278
279
280
281
282·
283
284
285
286
281
288
289
290
291
292
293
294
295
296
291
298
299
300

.**************************************************.**.*
Program/Channel/Name display.
**************************.*****************************

00000102
0000010a
00000113
0000011b

3334002328003334
240eOOO02e212d25
005c00ge003cOOfe
008b008d006dOOa9

00000124 >040090
00000121 >1400
00000129 a61a
0000012b b133
0000012d a6e1
0000012f b135
00000131 a621
00000133 b131
00000135 3f30
00000131 3f31

BNTAB
MTAB
PRDSP

00000139 .. 6e5
0000013b >b100
0000013d a6e6
0000013f >b100
00000141 a610
00000143 ae18
00000145 >e7fd
00000141 5a
00000148 5a
00000149 5a
0000014a 26f9
0000014c a6e6
0000014e ae12
00000150 >e1fd
00000152 5a
00000153 Sa
00000154 5a
00000155 26f9

STLP

FCB
FCB
FCB
FCB

$33, $34,0, $23, $28, 0, $33, $34
$24, $OE, 0, 0, $2E, $21, $20, $25, $CO
0, $se, 0, $9£, 0, $3C, 0, $FE

BRSET
BSET

2,STATS,OSDLE
2,STAT5

LOA
STA
LOA
STA
LOA
STA
CLR
CLR

1\00011010
C34
tHll00001
WCR
1%00100001
HPO
$30
$31

LOA
STA
LOA
STA

tUll00101
CAS 1
1\11100110
CAS8

LOA
LOX
STA
OECX

1%00010000
t24
RADl-3,X

O,$8B,O,$8D,O,$6D,O,$A9,$CO

00000151 >3fOO
00000159 a609
0000015b >b100

CLR
LOA
STA

OSOL
tLTAB3-LTABO
LINO

0000015d
0000015f
00000161
00000163
00000165
00000161
00000169
0000016b

LOA
STA
LOA
STA
LOA
STA
LOA
STA

t3
BROW
1$03

STLP2

a603
>b700
a603
>b700
a600

>b100
a601
>b700

00000182 ae10
00000184 >ldOO
00000186 >b600
00000188 >b700

OSO ,

PLL ON,

WINDOW ON (COLUMN 1)
HORIZONTAL POSITION

ONE

PUT A SPACE AT 11th ANO 18th
CHARACTERS

COLOR 1,0 -

RED, MAGENTA, EOGE ON

AND WINDOW ON

(U~ING

S INGLE WIDTH/HIGHT,

BIT 6)
INTERRUPTS ON

STLP
tUll00ll0
U8
CAS2-3,X

00000174 5f
00000115 >d60000
00000178 aleO
0000017a 2106
0000017c >d70000
0000017f 5c
00000180 20f3

COLOR 2 - GREEN
COLOR 3 - CYAN

DECX

OECX
BNE
LOA
LOX
STA
OECX
OECX
OECX
BNE

0000016d ae80
OOOOO16f >6fff
00000111 Sa
00000112 26fb

ST CH ST
O. NAME
> < Y •
+ - M I

ACLR

BNPL

FINBN

THIRD TABLE
START AT ROW
START AT COLUMN 3

to
WROW
U
COUNT

ACLR
BNTAB,X

LOX
BCLR
LOA
STA

YELLOW, EOGE ON

seOL

CLRX
LOA
CMP

RED,

STLP2

LOX
CLR
OECX
BNE

BEQ
STA
INCX
BRA

COLOR. 1,0 -

1128

CLEAR 1st THRU 8th ROWS

DRAM-1,X

t$CO
FINBN

DRAM, X
BNPL
116
6,STAT5
COUNT
W2

83

CLEAR STANDARD CHANGE FLAG

302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381

•• *.*******k.**,. __ * ____ • ____ * ____ ** _____ * __________ *_ **

Program/Channel/Name main loop.
kk*kk*kkkk*kk._**_*_*** ___________ * __ * __ * ____ * ___ • ___ * __
0OOOO18a >b600
0000018e >bfOO

BNLP

OOOOO18e >cdDQOO

00000191 >b700
00000193 a40f
00000195 ab10
00000197 >beDa
00000199 >d70QOl

000001ge >b60Q
OaOOO1ge 44
0000019f 44
000001aO 44
000001a1 44
000001a2 2602
000001a4 a6fO
OOOOOla6 ab10
000001a8 >d70000
000001ab >b600
OOOOOlad abdf
000001af >b700
000001bl a6aO
00000lb3 >b700
000001b5 >cdOOOO
00000lb8 >b60l
000001ba a47f
000001be >cdDQOO
000001bf >b70Q
OOOOOlel a40f
000001e3 ab10

NOTZR
STLSN

000001c5 >beDa

000001e7 >d70004
oaoaOlca >b600
44
000001ed 44
OOOOOlce
44
oooaOlcf 44
000001dO ab10
000001d2 >d70Q03
000001cc

LOA
STX
JSR
STA
AND
ADD
LOX
STA
LDA
LSRA
LSRA
LSRA
LSRA
BNE
LOA
ADD
STA
LOA
ADD
STA
LDA
STA
JSR
LOA
AND
JSR
STA
AND
ADD
LOX
STA
LOA
LSRA
LSRA
LSRA
LSRA
ADD
STA

W2
w3
CBCO
W1
'$OF
'$10
W3

STATION No.

DRAM+l, X

W1

NOTZR
'$FO
'$10

DRAM, X
W2
'$OF
SUBADR
'$AO
ADOR
READ
IOBOF+l

LEADING ZERO BLANK
STATION No.

CHANNEL No.

f$7F
CBCO
W1
'$OF
1$10
w3
DRAM+4, X

MSO

W1

'$10

DRAM+3,x
LSD
.kkkkkk*k,kkkk*,.,.,.,, ___ ._ ••• ' . " " "

__ •• __ •• ' ••• * •• **

Standard and bottom line.
___ * __ *_"****_*_* ___ * _________ * **

• • kkkkkkkk'kk' ____ **_*

000001d5 >laDO
000001d7 >OeOlO2
000001da >lbOO
OOOOOlde >edOOOO

PALS

OOOOOldf >b600
000OOle1 >edOOOO
000OOle4
9f
000001e5 ab10
000001e7 97
000001e8 >3c:00
OOOOOlea a360
OOOOOlec 2203
0OOOO1: ee >ccOOOO

000001£1 5f
00000lf2 >d60000
00000lf5 aleO
00000lf7 2706
00000lf9 >d70070
OOOOOlfe 5e
OOOOOlfd 20f3

NOJMP
MTL

OOOOOlff >edOOOO
00000202 >1800
00000204 a6le
00000206 >b700
00000208 81

ANFlN
SEC30

BSET

5, STAT5

BRSET
BeLR

5, STAT5

JSR

CHGST

LOA
JSR
TXA
ADD
TAX
INC
CPX
BHI
JMP

W2
GNAME2

CLRX
LOA
CMP
BEQ
STA
INCX
BRA
JSR
BSET
LOA
STA
RTS

7, IOBUF+l, PALS

116
W2
'96
NOJMP
BNLP
MTAB,X

'$CO
ANFIN
ORAH+ll2,X

MTL
WIND
4, STAT

'30
TMR

84

383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
4-12
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
'466
467

********************************************************
Look for channel name ..
***********************************************.******--

00000209 >04002f
0000020c a6aO
0000020e >b700
00000210 a6eO
00000212 >b700

FNAME

0000Q214
00000216
00000219
0000021b
0000021e
00000221

>b600
>cdOOOO
>b700
030205
Ob0202

00000223
00000226
00000228
0000022b
0000022d
0000022f
00000231
00000233
00000235
00000237
00000239
0OOO023b
0000023d
0000023f
00000242
00000244
00000247
00000249
0000024a
0000024b
00000240
0000024d
0000024f
00000252
00000254
00000256
000002'58

>cdOOOO
>b601
020202
a47f
2704
>bl00
274d
>3000
>b600
alf7
23e8

OLOOP

>beOO

NONAHE

0000025b
0000025d
00000260
00000262
00000265
00000267
0000026a
0000026d
00000270
00000272
00000275
00000277
0000027a
0000027c
0000027f

a630
>d7000d
a621
>d7000e

00000280
00000282
00000284
00000285
00000286
00000288
0000028a
0000028d
0000028f
00000291
00000294
00000296
00000299
0000029b
0000029d
000002aO
000002a2
000002a4
000002a7
000002a9
000002ao

>1eOO

IF38

>beOO

>b601
>d7000c
>b600
>d7000d
>3000
>3000
>odOOOO
>beOO
>b601
>d7000e
>b600
>d7000f
81

JSR
LOA
BRSET
AND
BEQ

READ

ClIP

4620

>b600
aOdf
48
48
ab70
>b700
>cdOOOO

CHAN
CHEX
COUNT

BEQ
INC
LOA

SPAL
NOFND
GNAME2

BLS
LOX
LOA
STA
LOA
'STA
LOA
LSRA
LSRA
LSRA
LSRA
ADD
STA
LOA
AND
ADD
STA
LOA
STA
LOA
STA
LOA
STA
BRCLR
BRSET
LOA
STA
LOA
STA
LOA
STA
RTS
LOA
SUB
LSLA
LSLA
ADD
STA
JSR
LOX
LOA
STA
LOA
STA
INC
INC
JSR
LOX
LOA
STA
LOA
STA
RTS

CHANNEL HODE

2 r STAT4, NONAME

I$AO
ADDR
I$EO
SOBADR

LOA
JSR
STA
BRCLR
BRCLR
BSET

ClIP

CRO

a623
>d70008
a628
>d70009
>b600
44
44
44
44
ab10
>d7000a
>b600
a40f
ab10
>d7000b

>d7000f
030212
Oa020f
a633
>d7000d
a625
>d7000e
a623
>d7000f
81

BRSET
LOA
STA
LOA
STA

38.9 MHz ?
NO, SECAM ?
NO, PAL

1, PORTe, OLOOP
5, PORTe, OLOOP

7,COUNT
IOBUF+l
1,PORTC, IF38

38.9 MHz ?
SO IGNORE STANDARD

t$7F

YES,

COUNT
NOFND
SOBADR
SOBADR
'$F7
OLOOP
w3
1$23

CHAN

eso

NO NAME SO DISPLAY Ch. No.

DRAH+8,X

1$28
DRAH+9,X

CHAN

1$10
3rd CHAR (NAME)

DRAM+I0,X

CHAN
t$OF
' '$10
DRAM+11,X
1$30

4th CHAR (NAME)
P

DRAM+13,X

1$21
DRAM+14,X
1$2C

A
L

DllAM+15,X
1, POR.Te, SPAL
5, PORTe, SPA!.

1$33

38.9 MHz ?
NO, PAL ?

S

NO, SECAM

ORAH+13,x

f$25
DRAM+14,X
'$23
ORAM+15,X

E
C

SUBADR
I$DF
x2
x4
1$7C
SOBADR
READ
W3
IOBUF+1
DRAM+12,X
IOBUF
DRAM+13,X
SOBADR
SOBADR
READ
W3
IOBUF+1
DRAM+14,X
IOBUF
DRAH+lS,X'

85

1st CHAR (NAME)
2nd CHAR (NAME)

3rd CHAR (NAME)
4th CHAR (NAME)

468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551

********************************************************

Cursor control (left

&;

right).

********************************************************'

000002ad

03040cOdOeOf

000002b3 ad19
000002b5 a305
000002b7 2502
000002b9 aeff
000002bb 5e
000002be >d60000
000002b£ >b700

CURTAB

FCB

3,4,12,13,14,15

CLFT

BSR
CPX
BLO
LOX

FCUR

15
NRAP1
t$FF

NRAP1

INCX

NEWC

LOA
STA

000002e1 >ccOOOO

SEC32

JMP

SEc30

000002e4
000002e6
000002e7

adOS

CRGT

FCUR

000002c9

ae06

000002eb

5a
20ee

BSR
TSTX
BNE
LOX
OECX
BRA

0000020c

5d
2602

OOOQ02ce >b600

000002dO >b700
000002d2 aeff
000002d4 5e
000002d5 >d60000
000002d8 >b100
0OOOO2da 26f8
000002de 81
000002dd

a631

000002d£

ae12

NRAP2
FCUR
CRNF

WI
CRNF
HOOllOOOl
U8

000002e8

a611

LOA

0OOOO2ea >b700
000002ec >b700
0OOOO2ee >beOO

STA
LOX

STJ;\.

WINDOW BLUE,

OFF AT 1-'

CCR2-3, X

STLP3
1%00010001
CCR1
CCR8

WINDOW BLACK,

OFF AT 17

BROW

DECX

OECX
LOX
LOA
STA
BSET
LOA
STA
RTS

000002f5 >e600

000002£1
000002 £9
000002£b
000002£d
000002££

CURTAB,X

LOA

5a
5a
5a
26£9

000002£0 5a
000002£1 5a
000002£2 >deOOOO

NEWC

CMP

000002e3
000002e4
000002e5
000002e6

STLP3

NRAP2
t6

BCOL
WI
t$FF

LOX
STA
DECX
DECX
DECX
BNE

OOOD02el >e7fd

BCOL

LOA
STA
LOX
INCX
LOA
BNE
RTS

WIND

CURTAB,X

>b700
>1cOO
>b600
>e700

81

M3,x

CCR1,X

W2
6,W2

W2
CCR1,X

**-*****************************************************
Cursor control (up & down) .
********************************************************

00000300 >b600
00000302 alO3
00000304 2304
00000306 >3aOO
00000308 20d3
0000030a >b600
0OOOO30c

cup

CMP

TOOSM

alOl

0000030e 27b1
00000310 >3aOO
00000312 2012

SEC31

00000314
00000316
00000318
000003la
0000031e
0000031e
00000320
00000322
00000324
00000326
00000329

COWN

>b600
al08
2404

>3cOO
>cdOOOO
>ccOOOO

BLS
DEC
BRA
LOA
CMF
BEQ
DEC
BRA
LOA
CMP

>3cOO

20b£
>b600
a1l3
27ea

LOA

TOOBG

BHS
INC
BRA
LOA
CMP

FIN30

BEQ
INC
JSR
JMP

BROW
t3
TOOSM
BROW
WIND

COUNT
fl
SEC32
COUNT
FIN30
BROW
t8
TOOBG
BROW
WIND
COUNT
t19
SEC31
COUNT
SEC30
FINBN

86

553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638

--*********-***--*--*--------********--******----*-*-***

*

Standard change.

_***ttt*t*tttt_*** __ ** __ *_*_*****_***_*_**_*_* ___ * __ **-*
0000032c
0OOOO32e
00000330
00000331
00000332
00000333
00000336
00000339
0OOOO33b

>lbOO
Sa
Sa
Sa
>d60006
a43f

a630
>d70006
a621
>d70007

0000037£
00000380
00000382
00000384
00000387
00000389
0000038c
0000038d
0000038f

9f
ab05
>b700
>d60006
ab40
>d70006
5c
>b300
26f3

SZER

CHGST

>d70008
a60D
>d70009

>d7000a
03021c

81

M16,X

AND

'$3F
'$30
SZER

BSET

JSR

a62c

>OaOO19
a633
>d70006
a625
>d70007
a623
>d70008
a621
>d70009
a62d
>d7000a
>OdOO12

5,STAT5
BROW

LOX
LOA
CMP
BEQ
BSET

a130

00000346
00000348
0000034b
0000034d
00000350
00000352
00000355
00000357
0000035a
0000035d
00000360
00000363
00000365
00000368
0000036a
0000036d
0000036f
00q00372
00000374
00000377
00000379
0OOOO37c

BCLR
LOX
OECX

DEFAULT TO SECAM

OEex
OEex

>deOOOO

0000033d 2702
0000033f >laOO
00000341 >lcOO
00000343 >cdOOOO

00000391

eRST

>beOO

SECAM

PAL

LOA
STA
LOA
STA
LOA
STA
LOA
STA
STA
BRCLR
BRSET
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
BRCLR

TXA

ADD
XLP

NSTCH

STA
LOA

DRAM+6, X

5, STAT5

6, STAT5
SEC30

PAL ?
NO, MAKE IT PAL
STANDARD CHANGED

'$30
DRAM+6,X

'$21
DRAM+7 / X

'$2C
DRAM+B, X

'0
DRAM+9,X

DRAH+IO,X

1, PORTC, PAL

38.9MHz ?

5,STAT5,PAL
'$33

NO, PAL ?
NO, SECAH

DRAM+6,X

'$25
DRAM+7,X

'$23
DRAM+8,X

'$21
DRAM+9,X

1$20
DRAM+IO,X
G,STAT5,NSTCH

'5

COUNT
DRAM+6,X

ADD

.540

STA
INCX
CPX
BNE

DRAH+6,x
COUNT

XLP

RTS

*t**t*t****tt*y_*_**_* __ *_******************************

Character change.

********************************************************
00000392
00000394
00000395

ad40
4c
a43f

00000397
00000399
0000039b
0000039d
0000039f
000003al
000003a3
000003a5
000003a7
000003a9
000003ab
000003ad

all9
2208
allO
2410
a610
200c
a121
2202
a621
a13a
2302
a600

PLUS

BSR

GETIT

INCA

AND

'$3F

CMF
BRI
CMP
BRS
LOA
BRA
CMP
BRI
LOA

MTA

CMP

SPACE

BLS
LOA

1$19
MT9
'$10
NLTO
+$10
NLTO
1$21
MTA
1$21
'$3A
NLTO
'$00

ORA
STA

'$40
DRAM, X

JMP

SEC30

4a

BSR
OECA

GETIT

a43f

AND

'$3F

LTE9

MT9

000003af aa40
000003b1 >d70000
000003b4 >ccOOOO

NLTO

000003b7
000003b9
000003ba

MINUS

adlb

87

A
A
Z

SPACE

639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
UO

000003bc
000003be
0OOO03cO
000003c2
00OOO3c4
000003c6
000003c8

a121

0OOOO3ca

000003cc

2302
a619

0OOOO3ce

allO

000003dO
000003d2

24dd
20d9

2508
a13a
23eb

CMP

BLO
GTEA

BLS
LOA
BRA

a63a

20e7
al19

000003d4 >b600
000003d6 a002
000003d8 48
0OOO03d9 48
000003da 48
000003db 48

CMP

LTA

CMP

LT9

BLS
LOA
CHP
BRS
BRA

GETIT

0OOOO3dc >bbOO

000003de 97
000003d£ >d60000
000003e2 81

LOA
SUB
LSLA
LSLA
LSLA
LSLA
lIDO
TAX
LOA
RTS

t$21
LTA
f$3A
NLTO
f$3A
NLTO
1$19
LT9
1$19
1$10
NLTO
SPACE

A
Z
Z

9
0

BROW
t2
x2
x4
x8
x16
BeOL
DRAM,X

.

********************************************************

Name store.

********************************************************

000003e3 a6aO
000003e5 >b700
000003e7 >b600
000003e9, >bbOO
00OO03eb 48
0OOOO3ec 48
000003ed ab70
000003e£ >b700
000003£1 a603
000003£3 >b700
000003£5 >b700
000003£7 >beOO
000003£9 5a
000003£& 5a
000003fb 58
000003£c 58
000003£d 58
000003£e 58
000003££ >b£OO
00000401 >d6000c
00000404 a43£
00000406 >b700
00000408 >d6000d
0000040b a43£
0000040d >b701
0000040£ >aeOO
00000411 >cdOOOO
00000414
00000416
00000418
0000041a
0000041c
0000041e
00000420
00000423
00000425
00000427
0000042&
0000042c
0000042e
00000430

>3cOO
>3cOO

>beOO
a603
>b700
>b700
>d6000e
&43£
>b700
>d6000£
a43£
>b701
>aeOO

>cdOOOO

SAVE

LOA
STA
LOA
lIDO
LSLA
LSLA
ADD
STA
LOA
STA
STA
LOX
OECX
DECX
LSLX
LSLX
LSLX
LSLX
STX
LOA
AND
STA
LOA
AND
STA
LOX
JSR
INC
INC
LOX
LOA
STA
STA
LOA
AND
STA
LOA
AND
STA
LOX
JSR

f$AO
lIDDR
COUNT
BROW
t$70
SUBADR
t3
Wl
W2
BROW

W3
DRAM+l2,X
f$3F
IOBUF
DR.AM+13,X
f$3F
IOBOFH.
tSUBADR
WRITE
SUBADR

SUBADR
W3
t3
WI
W2
DRAM+l4,X
t$3F
IOBUF
ORAM+15,X

f$3F
IOBOF+l
tsUBADR
WRITE

88

712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763

.

--*_.*-_. __ ._----*-----_. __ .---------------------_.*--**
Name store (continued) .

------------------------------------------------------*00000433
00000435
00000438
00000439
0000043a
0000043b
0000043c
0000043e
00000441
00000443
00000445
00000448

>beOO
>d60003
48
48
48
48
>b700
>d60004
a40f
>bbOO
>cdOOOO
>b700

0000044a >beOO
0000044c >d60006
0000044f a43f
00000451 al'33
00000453 2702
00000455 >1eOO
00000457
00000459
0000045b
0000045d
0000045f
00000461
00000463
00000465
00000467

>b600
>bbOO
abdc
>b700
a602
>b700
>b700
>aeOO
>cdOOOO

LOX
LOA
LSLA
LSLA
LSLA
LSLA
STA
LOA
AND
ADD
JSR
STA

W3

LOX
LOA
AND

W3

0000046a >cdOOOO
0000046d >000000

W1
DRAM+4,X

HOF
W1
CHEX
IOBUF
DRAM+6,X

BEQ
BSET

t$3F
1$33
STSEC
7,IOBUF

LOA
ADD
ADD
STA
LOA
STA
STA
LOX
JSR

COUNT
BROW
t$DC
SUBADR
'2
W1
W2_
tsUBADR
WRITE

JSR

SEC30
FINBN

CMP

STSEC

DRAM+3,X

JMP

.

----*--------------------------------------------.-._-**
OSD line number tables.
_a __ aw** ________ * __ • __ * ____ * _______________ • __________ **

00000470
00000472
00000475
00000479,

OaOO
090800
07080aOO
0203040506070809

LTABO
LTAB1
LTAB2
LTAB3

FCB
FCB
FCB
FCB

10,0
9,8,0
7,8,10,0
2,3,4,5,6,7,8,9,0

00000482
0000048a

1020304050607080
000306090cOfl215

H16
H3

FCB
FCB

$10,$20,$30,$40,$50,$60,$70,$80
0,3,6,9,12, 1S, 18,21

89

IDLE DISPLAY
PR/CH DISPLAY
ANALOGUE OISPLAY
PR/CH/STO/NAME TABLE
MOLT ,x 16
MOLT x 3

765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782'
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802

-_.** •. *.** ••••• *-_ ...... * •• _•••

**k*****k********.***** __ *_**_*_****_*****_******_**_* **
00000492
00000494
00000496
00000498
0000049a

a60c
>b700
>a600
>b700

0000049c

a60a
b733

000004ge
OOaOD4aO
000004a2
000004a4
000004a6
000004a8
000004aa
QOQOO4ac
000004.ad
000004af
000004b2
000004b4
000004b6
000004b9
000004bb
000004bd
000004bf
000004c1
000004c4
000004c6
000004c8

peOSD

>1900

a670

b735
a622
b737
3f30
3f31
Sf
a609
>cdOOOO
aelO
a61f

>cdOOOO
a610
>b700
>b600
2703
>cdOOOO
a60l
>b700

PNAME

SKPGN

a602

0OOOO4ca >b700
a6a3
QOQOO4ce >050002

000004cc

000004d1 a6a6
000004d3 >b700
000004d7
000004d9
000004db
000004dd
000004df
000004e1
000004e3

PMD2

a6dO
>b700
a610

>b700
a612
>b700
>b700

000004e5 >1800
000004e7 a61e

SEC5

0OOO04e9 >040005
000004ec >000002
0OOOO4ef
a606

000004fl >b700
000004£3 81

LDA
STA
LDA
STA
BCLR
LDA
STA
LDA
STA
LDA
STA
CLR
CLR
CLRX
LDA
JSR
LDX
LDA
JSR
LDA
STA
LDA
BEQ
JSR
LDA
STA
LDA
STA
LDA
BRCLR

803 0OOOO4dS >b700

804
805
806
807
808
809
810
811
812
813
814
815
816
817
818

-***.**.-*** •• **.**.*.**

Bottom corner Program/Channel no. display.

LDA
STA
STA
LOA
STA
LDA
STA
LDA
STA
STA
BSET
LDA
BRSET

S30

BRSET
LDA
STA
RTS

t$OC
ANAL
IAVOL
ANAF
4,STATS
1%00001010
C34
1%01110000
WCR
1%00100010
HPD
$30
$31

NOT ANALOGS
COLOR 2 - GREEN
COLOR 3 -

aso

BLUE

& PLL ON,
WINDOW OFF (COLUMN 16)

HORIZONTAL POSITION : TWO
POT A SPACE AT 17th AND 18th
CHARACTERS

19
OSDCLR

CLEAR UNUSED CHARACTERS

116
131
OSDCLR

CLEAR UNUSED CHARACTERS

116
W3
PROG
SKPGN

FNAME
11
OSDL
ILTAB1-LTABO
LIND
1%10100011
2, STAT4, PMD2
1%10100110

START AT 1 TO PREVENT

DOUBLE-HIGHT-LINE-SHIFT FLASH
FIRST TABLE
COLOR 1,0 - RED, CYAN,
PROGRAM MODE ?
NO, COLOR 0 - YELLOW

EDGE ON

CAsl
CAs2

1%11010000
RAD1
1%00010000
RAD2
1%00010010
CCR1
CCR2

DOUBLE WIDTH/RIGHT
SINGLE WIDTH/HIGHT
WINDOW CYAN

4, STAT

130
2, STAT4, S30
0, STAT6, S30

16
TMR

90

CHANNEL MODE ?

NO, 2-DIGIT PROG No. ENTRY
NO, SO 6 SECONDS ONLY

820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887

******************************************************--

Bottom row analoque bar.
********************************************************

BARGRAPH CHARACTERS

000004f4

Oe121113

CHAR

FCB

$OE,$12,$11,$13

000004f8
00000500

636f6e74a2b2a9ac
63b321fH6efecf5

ANCH

FCB
FCB

$63,$6F,$6E,$74,$A2,$B2,$A9,$AC
$63, $B3, $21, $F4, $F6, $EF, $EC, $F5

STA
BRSET

W3

00000508
0000050a
0000050d
0000050f
00000510
00000512
00000515
00000517
00000519
OOOOOSla
0000051c
0000051e
00000520
00000522
00000524
00000526
00000528
0000052a
0000052c
0000052.
00000530
00000532
00000534
00000536
00000538
0000053a
0000053c
0000053e
00000540
00000542
00000544
00000546

>b700
>080041
>1800
5f

ANOSD

BSET

a67f

>cdOOOO
aeld
>6fff
5a
26fb

COOP

CLRX
LOA
JSR
LOX
CLR
DECX
BNE

4,STAT5,LOGO
4,STAT5

ANALOGS
SET-UP SKIP FLAG

1127
OSDCLR
129

CLEAR ALL CHARACTERS

CASl-l, X

COOP

>b700
>b700
a611
>b700

LOA
STA
LOA
STA
LOA
STA
CLR
CLR
LOA
STA
STA
LOA
STA
LOA
STA
STA
STA
LOA
STA
STA
LOA
STA

1'00001010
C34
1\11100001
WCR
1'00100010
HPD
$30
$31
1%11100110
CASl
CAS2
1'10100110
CAS3
1'00010000
RADl
RAD2
RAD3
1\11100011
CCRl
CCR2
1'00010001
CCR3

00000548 >3fOO
0000054a &605
0000054c >b700

CLR

LOA
STA

OSDL
ILTAB2-LTABO
LIND

860a

b733
a6el
b735
&622
b737
3f30
3f31
a6e6

>b700
>b700
a6a6
>b700
a610
>b700
>b700
>b700
86e3

ANALOG
LOGOS

COLOR 2 - GREEN
COLOR 3 - BLUE
OSO , PLL ON,

WINDOW ON (COLUMN 1)
HORIZONTAL POSITION : TWO
PUT A SPACE AT 17th AND 18th
CHARACTERS
COLOR 1,0 - RED, YELLOW, EDGE ON
AND WINDOW ON (USING BIT 6)
COLOR 1,0 - RED, rELLOW, WINDOW OFF
SINGLE WIDTH/HIGHT, INTERRUPTS ON

WINDOW WHITE, OFF AT 3
WINDOW BLACK,

SECOND TABLE

OFF AT 17

.

********************************************************

.

Analoque logos.

********************************************************

0000054e
00000550
00000553
00000556
00000557
0000055&
0000055d
0000055e
00000561
00000564
00000565
00000568

>beOO
>d60000
>c10000

5c
>d60000
>c70001
5c
>d60000
>c70010
5c
>d60000
>c70011

LOGO

LOX
LOA
STA
INCX
LOA
STA
INCX
LOA
STA
INCX
r.OA
STA

ANAL
ANCH,X

DRAM
ANCH,X
DRAM+l
ANCH,X

DRAM+l6
ANCH,X

DRAM+l7

91

888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
901
908
909

.

******************************************************-Anal.oque bar.

*******************************************************-

0OOOO56b >b600
0Q()005~d >3fOO
00OO056f 44
00000570 >3900
00000512 44
00000573 >3900
00000575 >b700
00000577 aelO
00000579 5a
0OOOO57a >b300
0000057c 270a
0OOO057e 2204
00000580 a614
00000582 200d
00000584 a60e
00000586 2009
00000588 >bfOO
0000058a >beOO
0000058c >d60000
0000058f >beOO
00000591 >d70020
00000594 5d
00000595 26e2

910
911
912
913
914
915
916
917
918 00000597 >ccQOOO
919
920

LOA
CLR

LRAN

DOT
STAR

SKST

W3
W2

LSRA
ROL
LSRA
ROL
STA
LOX
DECX
CPX
SEQ
8HI
LOA
BRA
LOA
BRA
STX
LOX
LOA
LOX
STA
TSTX
SNE'

LRAN

JMP

SEC5

W2
W2
W3

116
W3
STAR
DOT

ISH
SKST
f$OE
SKST
Wl
W2

CHAR, X
Wl
DR.AH+32, X

END

92

-, 1, 2 OR 3

AN434
Serial bootstrap for the RAM and
EEPROM1 of the MC68HC0586
By Jeff Wright.
Motorola ltd .• East Kilbride

INTRODUCTION
the manufacture of the application. In addition, loading
small programs into RAM and executing them is an
easy way of trying out new software routines. This
application note describes one method for serially
loading (bootstrapping) the EEPROM1 via a program
executing in the RAM of the MC68HCOSB6.

The MC68HCOSB6 has 2S6 bytes of on chip EEPROM,
called EEPROM1, which can be used to store variable
data in a non-volatile manner. In many applications this
EEPROMl will be used to hold a look-up table or
system set up variables. In these cases it is usually a
requirement that the EEPROMl be initialised during

BUILT IN BOOTSTRAP
The MC68HCOSB6 has a built in RAM serial bootstrap
program contained in the mask RO M ofthe device that
uses the SCI. It would therefore seem a simple task to
load programs into RAM; however, as ROM space on
the device is obviously critical, a very simple protocol
has been implemented. This means that the bootloader on the 'B6' does not accept S-records which are
the normal output from an assembler; instead, the
protocol expects pure binary data preceded by a count
byte that holds the size of the program to be downloaded. No address information is contained in the
download; instead, the bootloader always starts the
program load at address $SO in RAM. The first byte
(the count byte) is stored here and then as the subsequent bytes are received via the SCI they are stored at
incrementing RAM locations and the count byte is

decremented for each· byte received. When the count
byte reaches zero the bootstrap program jumps to
address $S1 and starts to execute the program that
has just been loaded. No built in bootstrap routine is
provided for the EEPROMl array.
These restrictions present two problems:
i)

How to convert assembler output to the format accepted by the 68HCOSB6 RAM bootstrap routine?

ii) How to bootstrap the EEPROM 1 of the
68HCOSB6?
This application note provides a solution for each of
these problems.

93

11 CONVERTING S-RECORDS FOR RAM BOOTSTRAP
To use the built in RAM bootstrap program on the
MC68HC05B6 the device must be configured as shown
in Figure 1. If these conditions are met when the reset
pin is released. then the serial bootstrap program described above will start to execute and a program cao be
downloaded via a 9600 baud RS-232 source. Personal
computers usually have one or more R5-232 ports
referred to as COM ports. To overcome the format
difference between S-records and that accepted by the
bootloader. a conversion program is required. There is
also an additional problem when using a PC -when a file
is copied to a COM port to transfer it. it is the ascii
characters that are transmitted. not the binary data. This
means for example that if a file containing the typed data
byte $A5 was copied via the COM port to the B6. the B6
would in fact receive two bytes: $41 and $35. which
represent the ascii characters A and 5 respectively.

output file. After this each 5-record in the input file is
read and converted to binary data and stored in a
temporary file. As each 5-record is read it is echoed to
the screen; when they have all been processed a
'message prompts the user and asks if a count byte is
required. When used with the 68HC05B6RAM bootloader the answer will always be yes. in which case the
count value is written to the output file before the rest
of the data is copied from the temporary file to the
output file. Finally the value of the count byte is displayed for user confirmation - remember that the count
byte is equal to the number of bytes in the program
being converted plus 1 for the count byte itself. The
program will only accept standard 5-record format and
will trap and abort if any non-valid character or format is
detected.
With the PC COM port set for 9600 baud and the
68HC05B6 configured as in Figure 1 the binarY file can
be transferred and executed as follows:

This means that the conversion program has to strip out
the S-record format and convert the resultant data to
binary format for transfer to the HC05B6. It must also
insert the count byte at the beginning of the output file.

i)

The pascal program BINCONV performs these three
tasks; a listing of the source code is given at the end of
thiS application note. A flow diagram of BINCONV can
be seen in Figure 2. The inclusion of the count byte has
been left as an option to increase the flexibility of the
program. but it could easily be standardised to include
the count byte for the B6 RAM bootloader. When
BINCONV is invoked it prompts for the name of the 5record input file and the name required for the binary

Release Reset on the HC05B6

ii) Enter the command "COPYXXXX.YVYCOM1\B" on
the PC.
The program will then be transferred to the B6 and
execution started automatically. Note that the \B option
is used to denote a binary file transfer so that the copy
procedure does not abort'if it finds an end of file (EOF)
character in the middle of the file.

94

+9V
+5V

IOKn

IOKn
RESET

~:m"

19
tRQ
18

16
17

10
VDD

REsET

15
IOKn

OSCI

TCAPI

OSC2
PD3
PD4

22P~

22P~

20
21

PLMA
PLMB
TCMP2

2

TCMPI

23

TCAP2

39
38

Connect
as desired

RS 232 level
translator:
MC145407 or similar

ROt

SCLK
PDQ/ANO 14

3:
0
en
CI
:::t

PBO
PBl

37

PB2

36

PB3

35

PB4

34

PBS

33

PB6

32

PB7

3t

PAD

30

PAl

29

PA2

28

PA3

27

PA4

26

PAS

PDlIANI
PD2

13
12

PD5 5

0
0
en
aJ
en
.....

P07

"'"

VRH

PD6

4
3

VRL 7

aJ

VPPI

8
40

NC

25

PAS

PCl

24

PA7

PCO ~

48

VSS
41

Figure 1. RAM bootstrap schematic

95

Connect
as desired

RS232

9600 baud

2) BOOTSTRAPPING THE EEPROM1
To bootstrap the EEPROMl on the MC68HC05B6 in
the absence of a built in loader program. use must be
made of the RAM bootloader described above. The
idea is that an EEPROM 1 loader can be written to the
users exact requirements then assembled and downloaded into the RAM of the HC05B6 where it will
execute and in turn download data and program it into
the EEPROM 1.

Then the address in the routine is modified as the next
address to be programmed is received. When the data
byte is received the opcode of EXTSUB is incremented
so that it becomes "STA bbbb" before the erase and
program routines are called. After programming the
opcode is decremented back to LDA before the main
loop is repeated.
Note that the EEPROMl location is always erased
before programming. The timer output compare function is used to provide a 1Oms delay for erasing and
programming and the programming step is skipped to
save time if the data presented to that location is $FF.
The sequence of events to bootstrap the EEPROM 1 of
the 68HC05B6 is therefore as follows:

The 6K EEPROM emulation part. the MC68HC805B6.
does have a built in EEPROM bootloader in place of the
RAM bootloader and there is an accompanying PC
program available from Motorola called E2B6 that
downloads S-records to the device for programming.
The following is an explanation of an example
EEPROM 1 bootstrap program for the B6 that has been
written to be compatible with the 805B6 PC program
E2B6 thus eliminating the need to develop another PC
program.

1) Configure the 68HC05B6 as in Figure 1.
2) Assemble the program EEl BOOT and convert it to
binary using BINCONV as described in section 1.

A listing of this program (EE 1BOOT) is given at the end
of this application note. The MC68HC05B6 haS 176
bytes of RAM that can be used for the EEPROMl
bootstrap program. so the protocol must be kept
simple and the code written efficiently. The format of
the E2B6 program is a transfer of 2 address bytes
followed by the data byte that is to be programmed at
that location. At the same time the B6 returns the data
from the previously programmed location for verification by E2B6. The program EE 1BOOT has 4 main
sections: a main loop. an erase routine. a program
routine and an SCI service routine. The core of both the
erase and program subroutines is the extended addressing subroutine EXTSUB which is used to access
the EEPROM 1 array. This subroutine is built in RAM by
the main loop as the address information for the next
byte to be programmed is received from the SCI. E2B6
always sends a null character during initialisation
which could throw the EEl BOOT program out of
synchronisation. as it is already executing before E2B6
is invoked. For this reason EE 1BOOT ignores the first
character received and treats the second as the first
address byte.

3) Set up PC COM port to 9600 baud then release
Reset on the HC05B6.
4) Use the command "COpy EE1BOOT.BIN COM11
B" to download EElBOOT into the RAM of the
HC05B6. EE 1BOOT will now start to execute.

5)

Start the program E2B6 on the PC and follow the
instructions to download the desired S-records to
the EEPROMl of the 68HC05B6.

Note:
i) Only the download procedure of E2B6 will work in
conjunction with EEl BOOT.
ii) Once the EEPROMl security bit has been set. the
RAM bootloader on the 68HC05B6 will no longer operate. This means that after the device has been reset
it will be impossible to download any more data into
the EEPROMl until selfcheck has been executed selfcheck performs an erase of the entire EEPROMl
array. This means that if the EEPROMl is to be programmed in several steps. the one that will set the
security bit should be done last.

The EXTSUB routine is first called as an "LDA $aaaa"
to retrieve the last byte programmed for verification.

FURTHER POSSIBILITIES
enough space. If enough space is available (117
bytes). then EEl BOOT could be incorporated in the
application software. thus saving steps 2. 3 &4 in the
procedure above.

This application note has shown a method for initialising the EEPROMl on the 68HC05B6 by using the
RAM bootloader. It would of course be much simpler
to incorporate a EEPR'OMl bootloader in the ROM
space of the user program, but often there is not

96

PROCEDURE
BINWRITE

MAIN
PROGRAM

aUIT=TRUE
WRITE ERROR MESSAGE

WRITE BEGIN
OR END MESSAGE 1---+-1

aUIT=TRUE
WRITE ERROR MESSAGE

Figure 2. Flow diagram of BINCONV

97

0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017

.*"''''''
, \;"" "'"'' """""" '" "" u,," '" "~,,'"l"~ "'" "'" """""'",.*
.,
bootloader
'",.
..,,
., bootloader. The program will then start t.o execute. The format ,,EElBOOT - 68HC0586 EEPROM! Serial

.,
.,
.,*'
..,,
..,,

- This prog. is loaded into the RAM of the HC05B6 via the RAM

\.

has been selected to be the same as that on the 80586 so that

, •

the program £286 can be used to program the EEPROMl.

Note: £286 sends a null character during initlalis.aton so this prog

ignores the first character received on the SCI.

Jeff Wright

Last Updated

10/5/90

\*

,.

,.
,.
,.
,.
,",

. ,,"""" n"" '" "t"" "'" "" "'" "'"'''''''''''''' """'" "~"~,"l"~'"~"~"~ *

0018
0019

110 and INTERNAL registers definition

0020

•••••••• * •• * •• **.*.*.

0021
0022

I/O registers

0023
0024
00250000

PORTA

EQU

SOO

port A.

0026 0001

PORTS

EQU

SOl

port B.

00270002

PORTC

EOU

S02

port C.

0028 0003

PORTO

EQU

S03

port O.

0029 0004

DORA

EQU

S04

port A OoR.

0030 0005

DDKB

EQU

S05

port B DDR.

0031 0006

OORC

EQU

S06

port C DOR.

00330007

EECONT

EQU

507

0034 0002

EIERA

EQU

0035 0001

E1LAT

EOU

0036 0000

ElPGM

EOU

0032

0037
0038 DODd

BAUD

EOO

SOD

0039 OOOe

SCeRl

EQU

SOE

00400004

~B!T

EOU

4

004l OOOf

SCCR2

EQU

SOF

00420010

SCSR

EOU

S10

00430005

R!)RF

EOU

5

0044 0011

SOAT

EQU

Sl1

0045

TIMER'registers

0046
0047
00480012

TCR

Timer -control regist-er.

TorE

EOU
EOU

S12

0049000S

5

Timer overflow interrupt -enable.

0050 0006

OCIE

EQU

6

Timer output compares interrupt enable.

0051 0007

ICIE

EQU

Timer input captures interrupt enable.

0052

98

0053 0013

TSR

EQU

0054 0003

OCF2

EQU

Timer output compare 2 flag.

0055 0004

ICF2

ECU

Timer input capture 2 flag.

0056 0005

TOr

ECU

Timer overflow flag.

0057 0006

OCFl

ECU

Timer output compare 1 flag.

0058 0007

leFI

ECU

Timer input capture 1 flag.

0060 0016

TOCIHI

ECU

$16

0061 0017

TOCILO

ECU

$17

0062 0018

TIMHI

ECU

$18

0063 0019

TIMLO

ECU

$19

$13

Timer status register.

0059
Timer output compare register 1 (l6-bit).
Timer free running counter (16-blt).

0064
0065

""'"".. MIse DEFINITIONS -:--

0066
0067 00c6

LDAEXT

ECU

$C6

OP-Code for LDA extended.

0068 0014

HSIO

EQU

$14

IOmS delay constant.

0069
0070
0071
0072
0073
0074

START or CODE

0075

0076
0077
00780051

ORG

$51

0079
0080 0051 a6 00

LOA

1$00

0081 0053 b7 04

STA

DORA

0082 0055 b7 05

STA

DDRB

0083 0057 b7 06

STA

DDRC

BeLR

HBIT, seeRl

LOA

.SCO

0087 005d b7 Od

STA

BAUD

9600 baud at 4KHz.

0088 OOSt a6 Dc

LOA

'SOC

Enable t.ransmit and receive.

0089 0061 b7 Of

STA

SCCR2

0090 0063 b7 10

STA

SCSR'

Clear pending flags.

0091 0065 a6 c6

LOA

• LOAEXT

Inlt extended addressing subroutine to LOA .

0092 0067 c7 00 8f

STA

OPCDE

0093 006a ad Id

BSR

SCREAD

RESET

\11 Ports inputs.

0084
0085 0059 19 Oe

selINT

0086 005b a6 cO

Initialise SCI - 8 data bits.

Wait here and ignore 1st char (E2B6 init).

0094
BSR

EXTSUB

Load Ace with data from last programmed addr

0096 D06e b7 11

STA

SCDAT

Send it back for host to veri fy.
Get high address

0095 D06e ad 21

LOOP

0097 0070 ad 1 '1

BSR

SCREAD

00980072 c7 00 90

STA

ADDHI

- and store it ..

0099 0075 ad 12

BSR

SCREAD

Get low address

0100' 0071 c7 00 91

STA

ADDLO

- and store it.

0101 D07a ad Cd

BSR

SCREAD

Get the dat a to be programmed

0102 007c c7 00 93

STA

DATA

Store it temporarily.

0103 007f 3c 8f

INC

OPCDE

Change the ext addr subroutine to STA aaaa.

0104 0081 ad 11

BSR

ERASEE

Erase the selected address for lOms.

0105 0083 ad 27

BSR

PROGEE

Now prog the data for lOmS.

0106 0085 3a 8f

DEC

OPCDE

Restote ext addr subroutine to LDA aaaa ..

0107 0087 20 e3

BRA

LOOP

0108

99

0109

.................. - •••••• SUBROUTINE TO SERVICE SCI····· .. • •••••••• -,._ •••••••••••••

0110
SRCLR

RDRF, SCSR, ..

0112 008e b6 11

LDA

SCDAT

0113 008e 81

RTS

0111 0089 Ob 10 fd

SCREAD

0114
0115
0116

* "' ... III

..........

EXTENDED ADDRESSING SUBROUTINE TO ACCESS FULL MEMORY MAP ••• _.- -- _ •••

0117
0118008f

EXTSUB

EOO

0119 008f 00

OPCOE

rCB

0120 0090 00

ADDHI

rCB

0121 0091 00

ADDLO

rCB

0122 0092 81

RTS

0123
0124 0093 00

DATA

Reserved Byte for data during erasing.

rCB

0125
0126

. . . . . . . . . . . . . . . . . . . . . . . . . . . . EEl ERASING SUBROUTINE ...... "' . . . . . . . . . . . . . . . . . . _ •••••••

0127
0128 0094 12 07

ERASEE

BSET

E1LAT, EECONT

01290096 14 07

SSET

EIERA, EECONT

0130 0098 ad [5

BSR

EXTSUB

LOA

IMslO

BSET

E1PGM, EECONT

0133 00ge b7 19

STA

TIMLO

0134 0000 b7 16

STA

Toe1HI

0135 00a2 b7 13

STA

TSR

0136 0004 b7 17

STA

TOC1LO

0131 009a a6 14

0132 00ge 10 07

DELi.

Set up timer for a lOms count
- using output compare 1 function.

0137 0006 Od 13 fd

BRCLR

OCFl, TSR,·

Wait here for end of erase time

0138 OOa9 3f 07

CLR

EECONT

- erase finsished.

0139 OOab 81

RTS

0140
0141

........................ EEl PROGRAMMING SUBROUTINE .................................... **** ••••

0142
BSET

EHAT, [ECONT

LOA

DATA

0145 OObO ad dd

BSR

[XTSUB

0146 Dab2 4c

INCA

0147 DOb3 27 Of

BEQ

SKIP

0148 00b5 a6 14

LOA

'MS10

0143 OOac 12 07

PROGEE

0144 OOoe b6 93

014900b7 10 07

Skip programming if data" $FF

BSET

ElPGM, EECONT

0150 00b9 b7 19

STA

TIMLO

0151 OObb b1 16

STA

TOC1HI

0152 OObd b7 13

STA

TSR

0153 OObf b7 11

STA

TOC1LO

BRCLR

OCFl, TSR,·

CLR

EECONT

DE:'

0154 OOel Od 13 fd
0155 OOc4 3f 07

0156 00e6 81

SKI?

Set-up timer for lOmS count
- using output compare 1 function.

RTS

100

Wait here for programming to finish.

{************************* •• *********************************************1
program BINCONV; {Proqram to convert Motorola S-record files to
binary format. Optional inclusion of a count byte for
HC05B6
boot loader etc}
{ Programmer - Jeff Wright, NCU applications
Motorola
East Kilbride}

RAM

Last Updated 10/5/90}

{************************************************************************}
var
SrecFile
text;
BinFile
file;
Tempf
file;
srec
string[lOO);
Transfer: arrayil. .20000) of char;
numread, numwritten : word;
answer
: char;
fnamei
: string(15);
fnameo : string(15);
bytout : char;
countbyt : integer;
datcnt
integer;
datval
integer;
point
integer;
cntl
integer;
cnt2
integer:
quit
boolean;
boolean;
Count

Procedure Calc_hex (chrl, chr2 : integer);
{Combines 2 characters into a single byte value i.e A5->l65, error
signaled if non hex character detected}
Begin
Case chrl of
48 .. 57
chrl:- chrl - 48;
65 .. 70 : chrl := chrl - 55;
{Is this a valid hex character?}
else
begin
writeln ('invalid data - conversion aborted');
quit :- true
end
end;
Case chr2 of
48 .• 57
chr2: - chr2 - 48;
65 .. 70 : chr2 : = chr2 - 55;
else
begin
writeln ('invalid data - conversion aborted');
quit := true
end

101

end:
datval :- chrl*16 + chr2:
end:

{Convert to single byte}

Procedure Binwrite(length,dpoint : integer):
{Converts an S-record line to hex and stores it in a temporary file}
begin
length :- length-J-;
{Allow for address and checksum bytes}
countbyt :- countbyt+length;
{Update running byte total}
length :- length*2;
{Twice as many characters as bytes}
while length > 0 do
begin
cntl :- Ord(srec[dpoint]);
{Get the next two characters}
cnt2 :- Ord(srec[dpoint+l]);
dpoint :- dpoint+2;
{Update pointer and length}
length :- length-2;
Calc_hex(cntl,cnt2);
{Convert two characters into single byte}
bytout :- Chr(datval);
{- now convert that single byte into a }
blockwrite (tempf,bytout,l)
(character and save it in temporary file)

end
end;

{******** ••••• *****

MAIN PROGRAM STARTS BELOW

*********.*********'!1!'.*:*.**}

begin
writeln ('S-record to Binary conversion utility');
writeln;

writeln;
write('Input S-record file name? -> 'I;
readln(fnamei);
assign (SrecFile, fnamei};
write(' Binary output file name? -> 'I;
readln(fnameo);
assign (BinFile, fnameo);
assign (tempf, 'temp. tmp');
quit :- false;
countbyt := 1;
Reset(SrecFile);
{open the two}
Rewrite(BinFile,l);
{ -selected files}
Rewrite(tempf,l);
+ a temporary file}

102

while not Eof(SrecFile) and not quit do
begin
{read S-rec into char string srec}
readln(SrecFile, srec);
writeln (srec);
If srec[I]='S'then
{If string does not start with S then quit]
begin
CASE srec[2] of
{If not SI record then loop back}
'I'
begin
{get the 2 record length}
cntl :- Ord(srec(3]);
{characters}
cnt2 := Ord(srec[4]);
calc_hex(cntl,cnt2); {func to produce hex in
datcnt from cntl , 2}
datcnt :- datval;
point :- 9;
{point to first data character}
binwrite (datcnt, point)
{convert the data in this s-rec
line to binary and store in temp file}
end;
'0'
writeln ('Gonversion started');
'g' : writeln ('last S-record done');
else

begin

(If not SO,S1orS9 record then abort]
quit :- true;

writeln ('Non standard S-record detected - Conversion aborted')
end
end
end
else
begin

(If 1st char not an S then abort)
quit :- true;

writeln ('Non standard S-record detected - Conversion aborted')
end
end;

If quit - false then
{If no errors then copy the temporary file to the output file and add in
a count byte if required}
begin
Reset (tempf,I);
writeln;
write ('Do you want a count byte added to start of output file? -> ');
readln (answer);
If upcase(answer) = 'Y' then
Begin
wrJ.teln ('Total size. including count byte
',countbyt) ;
by tout :- chr(countbyt);
blockwrite (binfile, bytout , 1)
end;
repeat
blockread (tempf,transfer,sizeof(transfer) ,numread);
blockwrite (binfile,transfer,numread,numwritten);
until (numread-O) or (numwritten <> numread)
end;

close(tempf);
erase(tempf);
{Finished with temporary file so erase it}
close(SrecFile);
close'(BinFile)
{Close files before quiting}
end.

103

104

AN436
Error Detection and Correction Routines
for M68HC05 devices containing EEPROM
By Ken Terry
MCU Applications Group
Motorola Ltd
East Kilbride

A codeword consists of k data digits to which are added
r check digits to produce an n digit codeword In k+r).
The r data digits are redundant. in that they carry no
additional data. and the code efficiency is defined as kin.
This is an indication of the amount of information
transferred. relative to the total number of bits.

INTRODUCTION

=

An increasing number of applications involving
MC68HC05 MCUs require large amounts of critical
data to be stored in EEPROM memory. This application
note describes software routines. generated for the
HC05. which allow stored data to be encoded so that
single bit errors existing in retrieved data may be
corrected and two bit errors detected. The routines
use a simple Linear Block Code for the encoding of
stored data.

For a linear block code the general codeword can be
written in the form:
al~8a·······atclc2·····C,

where a, to ak are the k data digits and c, to c, are the r
check digits.

SINGLE BIT ERROR CORRECTION

The check digits are chosen to satisfy the r linear equations:
All methods of error detection/correction involve the
use of extra check bits added to the data bits to
produce some form of codeword. To allow the
detection of a single bit error in a specific codeword it
is necessary that each word differs from any other
word by at least two digits. A one bit error will then
produce an invalid word. The number of digits by
which two words. of the same length. differ is defined
as the Hamming Distance. For the correction of up to
t errors a minimum Hamming Distance of 2t + 1 is
required between each codeword. Single bit error
correction and double bit error detection requires a
minimum"distance of 3. The problem is to decide what
an original codeword was if an invalid codeword has
been detected. One means of doing this is to use a
Linear Block Code. as described below. Linear Block
Codes for the correction of single bit errors are referred
to as Hamming Codes. The following describes a
systematic method for single bit error correction.

0= h'la, $ h'2a2$ .........$ h'~k$

c,

0= h"a, $ h,282 $ .........$ hrJllk $ c,
Each element in the above equations is either a one or a
zero and all addition is modulo 2.
These equations can be more conveniently expressed in
terms of the matrix equation:

(HIITI = 0

105

where [T) is an n x 1 column vector representing the
stored codeword:

lSI is an (xl column matrix and can consists of anyone
of 2' sequen~s. (EI is an n x 1 matrix and can consist
of anyone of 2n sequences. As n> (there is no unique
solution to the above equation. However, in this case
it is assumed that only one error has occurred and
therefore (EI contains only one non zero element.
Multiplying (EI by (HI yields a syndrome which will be
equal to one column within (HI. The position of this
column will indicate where the non ~ro element
exists in (EI and hence the position of the single bit
error in (R]. In the case of two or more non-zero
elements in (E] error correction is not possible.

c,

HAMMING BOUND AND
CODE EFFICIENCY

and (H] is an (X n matrix, referred to as the parity check
matrix.
(H] = [h11h12 ............... h1k 1

h21h22 ............... h 2k O

01 ..............
. . . . . . 0]0

h,1h,2 ............... h,kO 0 ............. 1
A second column vector (R], with same dimensions as
ITI. is used to represent the retrieved codeword. This
mayor may not be equal to the original stored codeword
[T), depending on whether or not an error exists. If (H]
(RI = 0, then (R] is most likely to be the original stored
codeword. If (H] (R] gives a non zero value then at least
one error has occurred. If an n x 1 error matrix (EI is
introduced, then the retrieved codeword (R] can be
written as:
(R]

=(T] + (E]

If (E] consists totally of zeros then no, error has
occurred. For any error that does occur in (R], (E] will
contain a '1' in the corresponding position. The problem
is then to determine where in (E] the non zero elements
are, once the codeword (R] has been retrieved. A
matrix (51. referred to as the syndrome, is defined
such that:

The Hamming Bound is defined as: 2' <:: k + (+ 1
where k is the number of data bits and (is the number
of check bits.
This must be satisfied for single bit error correction. To
allow double bit error detection a further check bit
must be added. Table 1 shows the number of check
bits required, along with the corresponding code rate,
for single bit error correction and double bit error
detection in different numbers of data bits.
It can be seen from the table that. in general, the
greater the number of data bits the greater the code
efficiency. However as the size of the codeword
increases the calculations involved in detecting an
error become increasingly more cumbersome. It can
also be seen that for both 8 and 11 data bits, the
number of check bits required is 5. By using 11 data
bits and 5 check bits the Hamming bound can be
satisfied exactly. There is no exact solution when 8
data bits are used. However, this is a more convenient
data size for an 8-bit MCU and is therefore used in this
application, despite the lower code efficiency.

(5] =(H] (R]

This can be expanded to
(5]

= (H] (T] + (H] (E]

giving
(5]

No. of
Data Bits (k)

No. of
Check Bits

4

4

50%

8

5

61.5%

Code
Efficiency

11

5

68.7%

26

6

83.9%

Table 1. Check Bit Requirements and Code
Efficiency for Single Error Correction

=(HI(E]
106

CODEWORD GENERATION
AND STORAGE

DATA
DATA EEPROM

For one byte of data, 4 check bits are required for
single bit error correction. The parity check matrix will
consist of 12 columns of 4 bits and can be simply
generated by taking the binary values $1 to $C
(represented as binary column vectors) to generate 12
columns as shown. The check bits. c1 to c4, are
assigned to the columns containing a single non zero
entry and the data bits, b7 to bO, are assigned to the
remaining columns. The order of assignment is
completely arbitrary.
[H) =

o

o
o

o
o

o
0

000

o

000

o

000
0

0

o
o

0

CHECK EEPROM
160 BYTES
DATA + $190

DATA RETRIEVAL AND CORRECTION

0

0

To allow a retrieved codeword to be checked it is
necessary to generate the syndrome [5). To do this
the retrieved data byte is used to generate a new set
of check bits, c1'- c4f, using the same set of equations
asabove. The syndrome is then generated by exclusive
ORing c1' to c4' with c1 to c4. An non zero result will
indicate the presence of an error. The parity check cst
is calculated from the retrieved data and check bits
and compared with c5. If they are the same, and the
syndrome indicates the presence of an error, then it is
assumed that a double error has occurred and can
therefore not be corrected. If the error is correctable
then the syndrome can be compared with values
corresponding to the columns of [H) (in this case, a
simple lookup table in ROM) to determine the error
position.

The following equations can then be derived from the
parity check matrix and used to calculate c1 to c4.
c1 = b7 ED b6 ED b4 ED b3 ED b1
c2 = b7 ED b5 ED b4 ED b2 ED b1
c3

DATA + $100

Figure 1. Data Organisation in Memory

c1 c2 b7 c3 b6 b5 b4 c4 b3 b2 b1 bO

o

256 BYTES

= b6 ED b5 ED b4 ED bO

c4 = b3 ED b2 ED b1 ED bO
At no time is the application software required to carry
out any mat;ix multiplication. This is done implicitly by
the use of the above equations. A fifth check digit, c5.
is used to detect the occurence of a double bit error
and is a simple parity check (even parity) for the 12 bit
codeword formed by concatenating b7-bO and c1-c4.

SOFTWARE

Figure 1 shows the data organisation in memory. The
data oytes (bD-b7) and the corresponding check bits
(c1-<:5) are stored separately in adjoining blocks of
EEPROM. This allows executable code to be stored in
the EEPROM and protected using error checking. The
dataEEPROMbiockis256byteslong.ltisimmediately
followed by the check EEPROM block. The minimum
size possible for the check EEPROM is 160 bytes (256
x 5 bits). lri order that all check bits can be
accommodated within this, software routines are
required for the 'packing' and 'unpacking' of check
bits.

An assembled listing of the software is included at the
end of this application note.
The software has been written to run on the
MC68HC05SC21 but can be easily modified to run on
any HC05 MCU with EEPROM. It comprises 2 main
routines. The first routine is CHECKPROG and this
generates the codeword from the data and programs
the data and the appropriate check bits into EEPROM.

107

The second routine. GETCHECK. retrieves the data
and check bits from the EEPROM. calculates the
syndrome and. if any error is detected. returns with
the error position indicated in the accumulator. The
detection of a double bit errorbyGETCHECK is indicated
by the carry bit being set on return from the routine.
The data and check EEPROM blocks can be placed
anywhere within the device EEPROM memory. the
start address of the data EEPROM being determined
by an address held in RAM registers EPSTHI and
EPSTLO.

The total ROM requirement for the routines is 301
bytes with a further 56 bytes required for the EEPROM
write/erase routines. Execution time for the routine
GETCHECK is approximately 0.6 ms (with 2 MHz
internal bus frequency). The execution time for
CHECKPROG is dependant on the EEPROM
programming time. The time required for the calculation
and packing ofthe check bits amounts to approximately
0.6ms.

REFERENCES

Four further subroutines are called by the the main
routines. PAKCHK and UNPAKCHK are used for the
packing and unpacking of the check bits in the check
EEPROM block. CHECKBIT is used to calculate the
check bits c 1 to c4 and cl ' to c.v. CALC5 calculates the
parity checks c5 and cs'.

Carlson. 'Communication Systems'. McGraw Hill.

108

0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067

*************************************************************************
*************************************************************************
MC68HC05SC21 - EEPROM ERROR CHECK CODING ROUTINES
*********-**************** •• ******************************************.**

This software was developed by Motorola Ltd. for demonstration
purposes only. Motorola does not assume liability arising out of
the application or use of this software and does, not guarantee

its functionality.
Original software copyright Motorola - all rights reserved.
*************************************************************************
16/10/90
*********************************************************************** ••
These routines use a modified (12,8) Hamming code to provide
single bit error correction and double bit error detection for
data stored in EEPROM. The data is segemented into blocks of 256
bytes. Each 256 block of 'data' EEPROM is immediately followed
by 160 bytes of 'check' EEPROM which contains the parity check
bitsa
** ••• *** •••••••• **.** ••••••• * •• ** •• *.**.**** •••• **** •• ***.*** ••• * ••• ** •• *
BYTE EQUATES
••••• ** •• * ••• ***.** •• **.* •• ***********.* •• **********.***.** •• *.**********

0004
0000
0001
0005
0008
0009

$04
DORA
EQU
PORTA
EQU
$00
PORTB
PORTB
EQU
$01
DDRB
EQU
$05
PORT B DATA DIRECTION REGISTER
EQU
$08
MIse register
MISC
Program Control Register
PCR
EQU
$09
••••••••• ****.************.*******.********.*****************************
USER EQUATES'
********************.*.**************** •• *.***** •• ******* •• * •••••••••••••

0080

ADSTA

EQU

$80

Start adda of RAM subroutine area for STA inst.
or LDA inst.

0081
0082
0090
0091

EPRADH
EPRADL
SAVA
SAVX

EQU
EQU
EQU
EQU

$81
$82
$90
$91

Adr. EEPROM high for EEPROM write routine
Adr. EEPROM low for EERPOM write routine
General purpose RAM reg. to store acc.
General purpose RAM reg. to store x-reg.

0092
0093
0094
0095
0096
0097
0098
0099
009a
009b

DATA
INDEX
CHECKO
CHECK1
CHECK3
CHECK4
REM
EPSTHI
EPSTLO
SYNDROME

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$92
$93
$94
$95
$96
$97
$98
$99
$9A
$9B

Data reg. contains data word to be encoded

1100

ERRCOR

EQU

$1100

Holds check bits c1 to c5 for byte in DATA
Used to generate check pits

•• ******.**.***.*********************.*** •••• **.*.*****.*.***.*******.***
BIT EQUATES
.****.***************************************************** ••• ***********

0000

SERIO

PORT A SERIAL I/O PORT
EQU
Serial i/o port - port A bit 0
0

0007
0006
0004

ROMPG
INTFF
DCTST

MISC Register
EQU
7
EQU
6
EQU

109

0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
,0093
0094
0095
0096
0097
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135

*

0007
0002
0001
0000

lIE

VPON
PGE
PLE

Program Control Register

EQU
EQU
EQU
EQU

7
2
0

*

*************************************************************************

ORG

1100

ERRCOR

*

**********************.*************.******************************************

*
*

CHKPROG - This routine programs a byte of data held in acc. into a
block of data EEPROM. Data EEPROM is 256 bytes long and starts from
an address held in EPSTHI and EPSTLO. Location of data byte within
data EEPROM is determined by X-reg value. Check bits Cl to C4 are
calculated for the data byte, using a (12,8) block code, to allow
the correction of a sinqle bit error by the routine GETCHECK. A

further simple parity check bitr CS, is generated to allow the
detection of double bit errors. The check bits are programmed as a
5 bit block into the check EEPROM, which is 160 byte long and starts
from location EPSTHI,EPSTLO + $100.

Enter with data to be programmed in acc."

*

start add. of data EEPROM

in EPSTHI and EPSTLO and index value for data address in X-reg.
Returns with X-reg. value saved.

*******************************************************************************

1100 b7 92
1102 bf 93
1104
1106
1108
110a
110e

b6
b7
b6
b7
b6

CHKPROG

99
81
9a
82
92

110e cd 12 33

*

1111 cd 11 c1

1114 cd 11 e4
1117 cd 12 09

*
*

STA
STX

DATA
INDEX

LDA
STA
LDA
STA
LDA

EPSTHI
EPRADH
EPSTLO
EPRADL
DATA

JSR

EPRNRT

Store data byte in EEPROM at address
specified by EPSTHI,EPSTLO + x reg.

JSR

CHECKBIT

Calculate check bits C1 to C4.
Returns Cl to C4 in CHECKO (bits 0 - 3)

JSR

CALeS

Calculate C5 and return with C5 in CHECKO(4)

JSR

PAKCHK

Calculate otfset req'd to give byte location

ll1c
111e
1121
1123
1124

b6
cd
b6
5c
cd

94
12 33
95
12 33

1127 be 93
1129 81

*
*
*

Set up address offset for EPRNRT
- (EEPROM write routine)

Restore data byte into ace.

for Cl to CS and store in X-reg. and rotate
CHECKO, and CHECK 1 so that C1 to C5 will be
programmed into appropriate part of check
EEPROM

*

111a 3c 81

Store data byte
Save data address index value

INC

EPRADH

LDA
JSR
LDA
INCX
JSR

CHECKO
EPRNRT
CHECKl

LDX
RTS

Increment start add. of data EEPROM by $100
to get start add. of check EEPROM

Program CHECKO into Check EEPROM

EPRilRT

INC X-reg. to get add. for CHECK1
Program CHECK 1 into EEPROM

INDEX

Restore X-reg. value

*******************************~***.****************** *************************

110

0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
0178
0179
0180
0181
0182
0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203

*

GETCHECK - Retrieves a data byte from location EPSTHI,EPSTLO + x
along with corresponding check bits C1 to C5. The data, and Cl to C4,
are used to calculate the SYNDROME value which is used to indicate
the position of a single bit error. The SYNDROME value is generated
by calculating new check bit values ell to C4' from the retrieved
data and adding these (modulo 2) to the original check bit values
retrieved from the Check EEPROM. CS and C5 1 are simple parity check
bits used to indicate the occurance of a 2 bit error.
Enter with start address of data block in EPSTHI and EPSTLO and index

value for data byte in X-reg.
Returns with the uncorrected data byte in RAM location DATA. Error

status is indicated by the following:
No errors - carry

*

=

0, ace.

= o.

= 0, ace. has one bit set to
indicate the posit ion of the error in the da"ta byte.

Single bit error in data byte - carry

Single bit error in check bits - carry ~ 0, ace has upper nybble = $F
and one bit set in lower nybble to indicate check bit error position.
(bO indicates error in Cl, b3 indicates error in C4).
Double hit error - carry

=

1.

X-reg. contents are saved.
*******************************************************************************

112a

GETCHECK

EQU

*

STX

INDEX

Store data address offset

LDA
STA
LDA
STA

EPSTHI
EPRADH
EPSTLO
EPRADL

Set up address offset for GETBYTE

1134 cd 11 71
1137 b7 92

JSR
STA

GETBYTE
DATA

Get data byte from loc'n EPSTHT,EPSTLO + X
Store retrieved data byte

1139 cd 11 88

JSR

UNPAKCHK

let check bits and return with Cl to CS


11.12

PC3 46

All

PC2 47
..

Al0
AS

:49 A8

r"

VSS

VAL

Figure 1. MC68HCS05B6 and MC68HC705B5 Serial/Parallel Bootstrap Programmer
PARTS LIST
RESISTORS
Rl
R2
R3-R5
R6
R7,R8
R9
Rl0
Rl1
R12.R13
R14
R15-R37
R39
R40
R41
R42

CAPACITORS
3K
3K
lOOK
lK
470
10M
4K7
10K
lK
4K7
lOOK
10K
lK
12K
4K7

Cl-C4
C5
C6
C7,C8
C9
Cl0,Cl1
C12
C13

INTEGRATED CIRCUITS AND SOCKETS

22~F
O.Q1~F
1.0~F

ICl
IC2
IC3

52 Pin PLCC ZIF
28 Pin OIL ZIF
16 Pin OIL LlF

22pF
100~F

CONNECTORS

47~F

1.0nF
O.l~F

Jl
J2,J3,J4
Pl

25 Way AMP Female
3 Way Jumper
4 Way Terminal Connector

DIODES
SWITCHES
01.02
03
04
05.06
07
08

lN914
LR3160
LG3160
lN5822
lN914
lN5818

Sl,S2,S3

2 Way, Toggle Switch (SPOT)

MISC
CRl

TRANSISTORS (All in T092 Package)
01,02
03
04

68HC805B6
INT27C64
MAX232CPE

BC337-25
BC239C
BC309C

118

MK04000A

4MHz Crystal
Package HC-18U

During the programming operation the green LED
should flash with a period of approximately 1 second
to indicate normal programming mode.

SERIAL PROGRAMMING MODE

After the programming operation has been completed,
the programmed contents of the MCU are verified
against the external EPROM. Any failure to verify will
result in illumination of the red LED. Successful
verification will result in illumination of the green LED.

This mode allows the user to program and read the
MCU EEPROM or EPROM via the serial port on the
programmer module. By using a host computer and a
control program such as E2B6, data can be downloaded
and programmed onto the MCU, or uploaded from the
MCU back to the host computer.

The 6BHC705B5 device can be checked for the EPROM
in the erased state by placing the jumpers in the
SERIALand ERASE+BOOT positions with +5voltson
the Vpp supply for 6BHC705B5. In this case follow the
instructions below for parallel programming ignoring
steps 4 and 5, but there is no need for a 27C64
EPROM in socket IC2. The green LED turned on
indicates success, the red LED indicates that the
EPROM is not in the erased state.

Programming in serial mode consists of the MCU
reading a byte ofdata from the serial port, programming
it into the internal 6 Kbyte EEPROM or EPROM array,
reading the data back from programmed location and
sending it to the serial port. The host computer should
verify programming by checking the data returned
from the programming module for differences from
the programmed data, which would indicate incorrect
programming or erasure.
As in parallel mode, bytes to be programmed with $FF
for EEPROM devices and $00 for EPROM devices are
skipped, reducing the overall programming time and
allowing the memory upload feature to be
implemented. This involves the host computer reading
the data programmed in the MCU by attempting to
program these values and examining the retumed
verification data.

PARALLEL PROGRAMMING OPERATION
To program the MCU from an EPROM using parallel
mode, perform the following steps:
1. With power to the module removed install MCU
and EPROM devices into the programming module.
2. With the power switches S1 and S2 both off, and
switch S3 in the RESET position, connect both
the +5V supply and appropriate Vpp supply
(6BHC705B5 or 6BHCBOSB6) to the module.

MC68HC805B6
A program called E2B6 is available forthe IBM PC and
similar machines that communicate via R5-232 with
the programmer board serial connector. This program
allows upload (data transfer from 6BHCB05B6 to IBM
PC) to read the EEPROM and can also program the
EEPROM by downloading S1 record files to the
68HCB05B6 device.

3. Set jumper J4 to the appropriate setting for the
MCU being programmed (705B5 or B05B6).
4. Set jumper J3 to the 'ERASE + BOOT' position.
5. Set jumper J2 to the 'PARALLEL' position.
6. Turn the +5V power supply switch, S1, ON.

As in the parallel programming mode, the internal
EEPROM areas can be automatically erased before
progr'lmming.ln serial mode, however, this operation
is optional, and is selected by setting jumper J3 to the
ERASE + BOOT position. An exception is if the
EEPROM security bit isactive, in which case the erase
will be carried out regardless of the setting on J3. A
'read' or 'upload' of the EEPROM will also cause the
EEPROM to be erased if J3 is set to 'ERASE + BOOT'
or if the security bit is active.

7. Turn the Vpp power supply switch, S2, ON.
B. Place switch S3 in the RUN position.
9. Once the green LED has stopped flashing, and
remains continuously illuminated, place switch S3
to the RESET position.
10. Place the Vpp power supply switch, S2, in the OFF
position.
11. Place the +5V power supply switct!, S1, in the OFF
position.

MC68HC05B6
Note: To avoid possible damage to the MCU it is
essential that power to the programming module is
applied and removed in the sequence specified above.

The 6BHC05B6 (ROM device) 256 byte EEPROM may
also be programmed using this board as described in

119

application note AN434. In this case the jumpers
should be set as for, the 68HC805B6, ERASE+BOOT
and SERIAL but the Vpp supply for the 805B6 power
socket should be connected to +5 volts.

MC68HC705B5
A program called EPB5 for the IBM pC co~municates
via RS-232 with the programmer board serial connector.
This program allows upload (data transfer from
68HC705B5 to IBM PC) to read the EPROM and can
also program the EPROM by downloading S1 record
files to the 68HC705B5 device.
The 68HC705B5 EPROM means that the jumpers J2
and J3 have slightly different meaning. See table 1 for
details of operating modes.

4. Set jumper J4 to the appropriate setting for the
MCU being programmed (705B5 or 80586).
5. Jumper J3 should be set to the desired setting,
e.g., BOOT ONLY if reading data from the MCU or
ERASE + BOOT if re-programming a device
(68HC80SB6 only).
6. Set jumper J2 to the 'SERIAL' position.
7. Turn the +5V power supply switch, S1, ON.
8. Turn the Vpp power supply switch, S2, ON.
9. Place switch S3 in the RUN position when prompted
by the host computer control program.
10. Follow the instructions of the upload/download
program to initiate the data transfer.
11.When the operation has been completed, place
switch S3 to the RESET position.

SERIAL PROGRAMMING OPERATION

12. Place the Vpp power supply switch, S2, in the OFF
position.

1. Run the _program E2B6 (68HC805B6) or EPB5
(68HC705B5) on an IBM PC to communicate with
the device to be programmed.

13.Placethe +SV power supply switch, S1, in the OFF
position.

2. With power to the module removed install the
MCU and connect the serial line between the host
computer and the serial port on the module.

For programming several devices, leave the IBM PC
program running and repeat instructions 2 to 13
inclusive.

3. With the power switches S1 and S2 both off and
switch S3 in the RESET position, connect both the
+5V supply and appropriate Vpp supply (705B5 or
805B6) to the module.

Note: The documentation of the host computer control
program being used should be consulted for further
details on the use of serial programming mode.

120

AN441
MC68HC05EO EPROM Emulator
By Peter Topping
MCU Applications Group
Motorola Ltd, East Kilbride

INTRODUCTION
The MC68HC05EOisaversatilememberoftheM6805
family of microprocessors. Unlike most other versions
it has no on-chip ROM but instead can address a full
64K of external memory. This memory could simply be
a ROM or EPROM containing the required program
but can also include RAM and/or additional hardware.
In addition to the external busses required to support
this capability, the MC68HC05EO has the usual I/O,
timers etc. found on single-chip microprocessors.
The EPROM emulator described here illustrates a
typical application of this type of microprocessor. In
addition tothe program EPROM it employs a keyboard,
LCD, serial communication and 64K of paged RAM.
The emulator can replace with RAM the program
EPROM or ROM (up to 64K x 8) in a microprocessor
based target system. This is done by connecting
the emulator to the target system via a cable to its
EPROM socket.
The object code, which can be loaded serially or from
an EPROM, can be inspected and modified with the
use of a local keyboard and LCD display. The new or
modified code can then be used by the target system
without having to go through the procedure of erasing
and re-programming an EPROM after each software
change. A selectable offset in $01 00 steps is available
in order to position the code correctly in the target
system's memory map.

121

The emulator facilitates the debugging of hardware
and software for any system whose control program
is to be contained in a 27(C)16(.32/64/128(.256/512
type EPROM. The control software includes branch
offset calculation for 6805 code and is thus particularly
suitable for debugging systems using one of the
microprocessors from the M68(HC)05/01/11 ranges.
Two basic methods of loading a program are available.
The first is applicable when the code is available in an
existing EPROM. The contents of this EPROM can be
transferred by the microprocessor into the RAM. This
method requires an existing EPROM but will prove
useful in applications where a small change to an
existing program has to be checked before committing
to an updated EPROM. This can be done without
access to the source or object code. An EPROM can
be read from the target system interface (through the
emulator's buffers) or from a separate socket wired
directly to the microprocessor. The former method
allows one socketto be used for both EPROM reading
and the target cable. The second method saves
having to remove the target cable to read an EPROM
but requires an additional socket.
Alternatively, data can be serially loaded in the form of
Motorola S-records via an RS232 link. This code can
come from a "COM" port of a PC (using the COpy
command) or by tapping into the link between a
computer and its terminal on a system using an
RS232 connection between terminal and host. In this
case a TYPE or LIST to the terminal should be used.
A verify facility which compares the contents of RAM
with serial S-records is also available, 'as is a routine to
dump the current contents of the emulation RAM out
on the RS232 interface.

PRINCIPLE OF OPERATION

There are three modes of operation:

Figure 1 shows a block diagram of the emulator in
each of its three main modes of operation. The datal
address flow is controlled by MC74HC245 bidirectional
tri-statable 8-bit buffers. They constitute two 18-bit
buffers for address and control signals and two 8-bit
buffers for data. The enabling and direction control
signals are supplied by the MC68HC05EO
microprocessor.

Microprocessor

Target
System

Figure 1a. Mode A:
direct access to the target system's interface

Microprocessor

Target
System

a) Mode A allows the microprocessor to read the
contents of an EPROM on the target system
interface (this is most easily arranged by connecting
the cable to the target system via a zero or low
insertion force socket) by enabling buffers Bland
B2 to drive from left to right to supply addresses to
the socket (the RAM also receives these addresses
but its data outputs are disabled). Buffers B3 and
B4 are enabled from right to left to return the data
from the EPROM to the MC68HC05EO. The RAM
is disabled via its chip-enable pin and so does not
affect the data bus between buffers B3 and B4.
b) Mode B enables the buffers in such a way that the
microprocessor can read from and write to the
RAM. Bl is enabled to supply addresses to the
RAM from the microprocessor (MC74HC245s were
used throughout although a bidirectional buffer is
not strictly necessary in this position as B 1, if
enabled, always drives from left to right). B3 is
enabled to allow data to be written to or read from
the RAM. The direction control for B3 is by the AI
W signal from the MC68HC05EO (gated with the
RAM's chip enable). This mode is used during use
of -the memory modify facilities. Buffer B4 is
disabled so that there is not a bus contention on
either of its busses even if the target system is still
connected. Buffer B2 is also disabled. The routine
(L 1) which loads RAM from an EPROM on the
target system interface switches between modes
A and B for each byte transferred.
c) In the emulation mode (Clthe target system plugged
into the socket is required to have access to the
RAM so buffers B2 and B4 are enabled. B2 passes
the addresses from right to left and B4 the data
from left to right (as the emulation is for an EPROM,
the target system is not allowed to write to the
RAM). Buffers Bland B3 are disabled.

Figure 1b. Mode B:
access to the emulator's RAM

MODE
Microprocessor

Target
System

Figure 1c. Mode C:
gives the target system access to the RAM

122

Control line

A

B

C

4,PortB

1

1

0

5,PortB.

0

0

1

6,PortB

0

1

0

7,PortB

1

0

0

CIRCUIT

any parallel LOAD keys fitted to be placed away from
the front panel or protected by requiring two keys,
connected in series, to be pressed. An accidental
press of the serial LOAD key can be aborted by
pressing RESET.

Figure 2 shows the main circuit. An MC74HC138 is
used to provide the chip enables. The emulator
hardware is enabled in the address range $4000 $7FFF and the EM64K program EPROM (27(C)64) at
$COOO - $FFFF. If the EM64K program is contained in
a 27(C)16 its pin 21 (Vpp) should be held high.

As the circuit, except for the RS232 interface, is all
CMOS the supply current is very low when the
microprocessor is in STOP mode. This is a low power
mode in which all processing, even the clock, is
stopped. In the emulation mode (C) the MC68HC05EO
is in stop mode. In this mode and with no bus activity
from the target system (or its interface open circuit)
the supply current should be less than 1 J.IA (this does
not include the current taken by the RS232 interface
which, if present, can be switched off when not in use,
or the 70-80 J.IA taken by the LCD driver).

An additional socket is shown at address $8000 $BFFF. This is for the optional LOAD2 facility which
alioiNs code to be loaded from EPROM without having
to disconnect the cable to the target system. The
emulation RAM occupies the address range $4000$7FFF. As this is only a 16K address space the RAM
is paged. The four pages are selected by I/O lines
(port B, bits 0 and 1) from the microprocessor. The
memory map of the emulator is shown in figure 7.

It is worth checking that a low supply current is
achieved as any excess can be a useful pointer to a
wiring fault. particularly open circuit pins. The supply
current may be affected by the choice of RAM but the
MCM60L256 selected has a specified standby ICC of
2 J.IA and is typically well below this figure. In many
applications the full 64K of RAM will not be required.
If this is the case, only the required RAM need be
included. 6116 2K RAMs could be used for 2-4K
applications and MCM60L64s or equivalents for
8-16K. If using 6064s, their second chip enable pin
(E2) should be held high. One MCM60L256 provides
32K. The serial load routine includes a read-back check
on each byte sent to RAM so an attempt to write to
non-existent RAM will generate an error message
indicating the first faulty address. If 16K or less is
required then the two 74HC245s handling addresses,
A 14andA15, can also be omitted. These buffers have
unused pins. The simplest way to ensure that no pins
are left open circuit is to wire up the buffers in a
manner similar to those actually used. Pins 2-7 of the
left-hand buffers are held high while pins 13-18 are
connected to the right-hand buffers whose other pins
have pull-ups. This arrangement means that there will
be no open circuits or bus contentions regardless of
the levels of the control lines. If only one memory chip
is used, the 74HCOO can be omitted (connect pin 3 of
the 74HC32 directly to the RAM's chip enable).

The control lines (port B, bits 4-7) are biased by
resistors. This holds the system in mode B if the
MC68HC05EO is held in reset and prevents bus
contention resulting from an illegal combination of
control signals. During hardware debug of the emulator
it is advisable to·use a current limited power supply (in
the range 50-100 mAl as a bus contention can cause
sufficiently high currents to damage the buffers.
The display is a 6-digit 4-backplane LCD (eg Hamlin
type 4200 or the 8-digit GE type LXD69D3F09KG)
which is driven by an MC145000 display driver. The
driver is controlled by a 2-1ine serial link from the
microprocessor. Asingle-backplane (or "static") display
can be used as an alternative as ,shown in Figure 3.
Three M C144115 driver chips are used. This circuit
requires many more connections to the LCD but
allows the use of a more readily available display. A
third line (port B bit 3) from the microprocessor is used
to supply the enable pins of the MC144115s. The
single-backplane display drivers can be supplied directly
from the main 5 volt supply but the multiplexed display
requires a lower voltage. Figure 2 shows the MC145000
supplied via a 20k potentiometer which serves as a
contrast control.
The keyboard uses an MC14028 decoder to minimise
the number of I/O pins used. Note that port A bit 6 is
used for both the keyboard and the display driver. The
LOAD1 and LOAD2 keys overwrite the contents of
emulation RAM and should thus not be pressed
accidentally. It may therefore be useful for only those
LOAD keys actually required to be fitted (usually
LOAD 1 and LOAD2 will not both be required) and for

The optional RS232 interface can most easily be
implemented using the single-supply MC145407
driver-receiver chip. If outputting of 5-records is not
required then a simple transistor inverter with a pullup resistor and a reverse polarity protection diode can
be used. This interface is shown in Figure 4.

123

.,

i1

$V

~

m

~ !~

::II

3l:
3
c:

~

~

i0

..

£!,

ac:

::.:
a.

ii'

-

IRQ

"41(0,

r:T.:.. I

3

5V

,-

.

Veri.

C I12

ENT.

2

17."",

II,At.Ii

B

5

I

"FfJ:'

A

7

Offu,

3

15·PAf

c
.....
,

I I I I

I I ll~
0

AI2

sv

""'.
• • ........
•
•
L1

RESET

M III

IQ

;

...ljo

I"~QI

.~::..

V I A7

P - - ' - I ,. A8

I
I

'AS
• A4

r--,

.'AO

,.....-~,

", AD

F--, . ,:'

•

I~

Q1CSAOM8

HI PI:!

,,'""
MC74
HC138

.....

.-

I.HHC241i

."

CD

-

~A1S
~A1'

::!!
IQ
c:

0

'"

sv

r - BP
~

'---

6-digit Static LCD

Cl
C2

abcefoed abc-' ged BP • be. f g. d • be. f g. d

22

•

8

•

0

Segment Outputs
PAS

EO

2!2!On

V...

PA7 ,.
PB3

MC144115P

:t

EN

•

0

Oaut

111

23

V..
,.C2 ;J,..,

D.
1

MC144115P

BKP
V...

241

C2

•

13

1

Dout .!!!! On
1

V...

;L,

:!

J

EN

C2

•

23

Figure 3. Alternative static LCD display

5V

EO
(PB2)

RS232

2N3904

Data

Figure 4. Simple input-only RS232 interface

125

I.

•

"

Oaut

MC144115P

BKP

V..

1

'511

• i

f 9 • d

Segment Outputs

OSC

EN

22

1

Segment Outputs

OSC

...l BKP

•

22

abc-fged .be

P-

OSC~
V..

;L,

,Eo.

100 Monitor

Address trap

It is often useful with CMOS circuits to provide a
simple 100 monitor which shows via an LED whether
or not the 100 is above or below a set value. In this
application it shows whether or not the microprocessor
is in the STOP mode. The required circuit is shown in
Figure 5. The current threshold can be chosen by
selecting the value of R1. A value of 1kO sets the limit
at about 500 J.IA which means the LED should be off
in the emulation mode but on otherwise. The 500 J.IA
limit allows the LCD and perhaps an emulator-supplied
CM OS target system to be supplied without switching
on the LED. When the microprocessor is not in STOP
(emulator not in mode C), its 100 is several milliamps
and the LED should be lit. In a battery application this
circuit would also serve as a useful reminder that the
RS232 interface has been left on. If a multiplexed LCD
is used it may be preferable not to supply it via this
type of monitor circuit as a significant change in
contrast may occur when the microprocessor goes
into its STOP mode (see Figure 5).The monitor drops
about 600mV when the microprocessor is running so
the supply voltage should be chosen accordingly; four
zinc-carbon or five Ni-Cad cells were found to be
satisfactory.

The emulator allows memory locations to be examined
and changed, but does not provide the breakpoint and
trace features normally found in development systems.
A limited capability can be made available if address
comparators of the type shown in Figure 6 are added.
This circuit gives an LED indication if the address
.selected on the bank of switches is encountered by
the program running in the target system. An address
coincidence is latched by the 74HC74. To indicate the
occurrence of a repetitive event, a one-shot chip could
be added.

5.5 - 6.0V

SERIAL LOAD
To load external Motorola $-records the serial load key
(LOAD) should be pressed. The LCD will display
"LOAd". S-records should then be supplied at 9600
baud (8-bit, no parity) on the RS232 interface. When an
S9 termination record is received, the prompt returns.
If an error is detected during a serial load, the load
routine stops and displays the address at which the
error occurred and the error type.

-..._-------.---1
50k

R1

4-backplane
LCD

lk*
BC307

Emulator
(including static LCD)

Figure 5. Simple 100 monitor

126

* see text

*

The following error types are possible:
1: Checksum error, transmitted data or interface faulty.
2: RAM rea(}back error, RAM faulty or non-existent.
3: ASCII character less than $30 (0) received.
4: ASCII character between $39 (9) and $41 (AI
received.
5: ASCII character more than $46 (F) received.
7: Verify error when comparing S-records with
emulation RAM.
If, when using the emulator, the target system ceases
to function properly, then the verify function can be
used to check that the emulation RAM has not been
corrupted. The VERIFY function is used exactly like
LOAD except that RAM is compared with, rather than
loaded by, the S-records.

The address atthe start of each Sl-record determines
the address at which the code will reside in the target
system. This address will sometimes be different
from that at which the code is required to be loaded
into the emulation RAM so an offset may need to be
used. The offset byte is entered using the appropriate
key and allows an offset of any multiple of $01 00. The
offset is subtracted from the MSB of the 5-record
address and this modified address is the physical
address at which the data is loaded into the emulation
RAM. The S-record output routine adds the offset
before transmitting the records. At reset or power-up
the offset is initialised to zero.
All addresses entered while using the MEMORYMODIFY, BRAOFF and DUMP routine use the actual
address in the target system. These addresses will
only be the same as the physical RAM address if the
offset is zero.

5V

o

Target System Address Bus
AO 1 2 3 4

5 6 7

100k

A8 9 10 11 12 13 14 15

.... Reset

-.-

5V
2 4 6 8 11 13 15 17
A012345 6 7

Vet:
A=

MC74HC688

20

B 19

CASr!----

20
1

2 4 6 8 11 13 1517
AO 1 2 3 4 5 6 7

Vet:
CAS

r~ r~ r~ r~ r~ \. \

r\.n~

19

A=B

Vee; R
S
0
MC74HC74

-Is
Q.

GN

Dr!!!-

BO 1 2 3 4 5 6 7
3 5 7 9 12 14 16 18

r\ r\ 1\ 1\ ~\ i\ \\

~

~5

oJ0~ ~ 0[ 0 ,.,,16 000 JJ JJJ ~~
Figure 6. Address Trap

127

Q~

3 C

MC74HC688

GN O~
BO 1 2 3 4 5 6 7
3 5 7 9 12 14 16 18

~

GNO
1111217110113

nk-

1kO

PARALLEL LOAD

TARGET SYSTEM INTERFACE

When the parallel load functions (LOAD 1 and LOAD2)
are used, OFFSET has no effect on the transfer of
code into RAM. It can, however, still be used to offset
the RAM addresses to correspond with the actual
address in the target system program when using the
memory-modify facilities.

Vdd can be connected to the interface by the link
shown. The simplest method of use is to malee this
connection and to use a common supply for the
emulator and the target system. If, however, separate
supplies are used, then pin 28 should not be connected.
If separate supplies are used, care should be taleen
that they do not differ by more than O.5V. A delta
greater than this may cause a malfunction as a result
of the logic level on an input pin being in excess of the
chip'sVdd.

27(C)64/128/256 EMULATION
When emulating a 27(C)512 EPROM, all the RAM is
used. For emulation of smaller EPROMS, less RAM is
required. The memory used will be at the beginning
of RAM (starting at address zero) only if the unused
high-order address lines are heldlow. It may, however,
be more convenient to allow one Or more of
these addresses to be high. The pull-ups included in
Figure 2 will hold any uncommitted lines high. For
example, a 27 (C)64 can be emulated with no hardware
change as long as the code is loaded between SEOOO
and $FFFF. This will often be appropriate as it allows
the vectors at the top of the target system's memory
to be included. It makes little difference if the target
microprocessor has an address space smaller t!;lan
64K as the high order addresses will not be present
and will be held high. Clearly, the code must still be
assembled at the appropriate addresses and the
emulator'S offset feature used to load the S-records
between $EOOO and $FFFF. Alternatively, the S-records
can be loaded lower in the emulator'S address space
and the relevant high-order addresses held low. When
loading from a smaller EPROM, with a VPP or PRG pin,
these pins should be configured correctly for reading
(high) and not driven by the emulator. See Figure 9
for the industry-standard EPROM pinouts. As the
software does not behave differently for smaller
EPROMs, a full64K transfer will still be made, copying
the EPROM several times into the 64K RAM. The
actual copy used depends on the levels of the high
order addresses as outlined above.

In emulation mode the target system has total control
of the RAM exceptfor its RN-J line. It can thus use the
RAM exactly as if it were a ROM or EPROM. Before
IRQ (or RESET) is pressed to exit from the emulation
mode the target system should be stopped so that it
no longer expects the" EPROM" to be there. This will
normally be done by holding the target system in
reset. If the target system is an M68(HC)05 (eg
MC68HC05EO or MCl 46805E2) or M68HCl 1, then it
can alternatively be put into its STOP mode. If this is
its normal idle condition, then nothing need be done
prior to exiting emulation.

EM64K PROGRAM
The EM64K control program is less than 2K bytes long
and can thus reside in a 27C64 or 27C16. The circuit
is shown for a 27C64 and assumes that the program
starts atthe beginning of the EPROM. This EPROM is
enabled at $COOO (and $EOOO as A 13 is not used). An
assembled listing of the control program is included at
the end of this application note.

128

EM64K KEY FUNCTIONS
Function

KEV

Description of function

LOAD 1

L1

Load RAM from target system interface ($4000-$7FFFI.

LOAD2

L2

Load RAM from secondary socket ($8000-$BFFFI.

SERIAL
LOAD

LOAD

Load emulation RAM with S-records via the RS232 interface,
during loading LCD shows "LOAd".

VERIFY

Verf

Compare emulation RAM with S-records via the RS232 interface,
LCD displays "UErIFy".

EMULATE

EM

Emulator mode. Prompts: "EP ?" for the removal of an EPROM (if presentl
and connection of the target system (press again if OKI and put micro into
EMULATE mode.

MEMORY
MODIFY

M

Display/change a RAM location. When pressed the last address is displayed.
Press ENTER to display the contents of this address or input a new address
followed by ENTER. To change, input new data followed by ENTER.
ENTER moves to next address, M moves to previous address, ESCAPE exits.

ENTER

Ent

Enter keyed-in address or data
(and move to next address in MEMORY MODIFYI.

ESCAPE

Esc

Exit from current function (OFFSET, BRAOFF, DUMP or MEMORY MODIFYI.

BRAOFF

A

calculate branch offset. The address of the branch instruction and of the
destination are requested. If a valid branch is calculated it is written into
memory and displayed. If not valid then "or" for out of range is displayed.
A branch of -128 through + 127 relative to the start address of the next
instruction is allowed. Esc ret\lrns to the normal prompt.

OFFSET

B

Allows entry of an offset to the emulation RAM address. It is subtracted from
the most significant byte of the address specified by the incoming $-records.
The offset is added to the address by the DUMP function.

DUMP

C

Output emulation RAM contents as S-records via RS232 interface.
RAM start and finish addresses are requested. They should be entered
followed by ENTER. After the second ENT,ER, the $-record output starts.

IRQ

IRQ

Abort emulation and return to emulator monitor.

RESET

RESET

Resets emulator, displays prompt (0 I. Should be used after power-up or if
the emulator malfunctions. can be used instead of IRQ, with the difference
that the OFFSET is reset to zero. RESET provides the only exit from a LOAD
or VERIFY which has not been terminated correctly by the reception of an
S9 reco~d.

129

.-----------------,0000
MC68HC05EO 1/0 timers
MC68HC05EO RAM (480 bytes

The only other register used (apart from the I/O data
and DDR registers) is the interrupt control register
($OE). It is written to $01 on lines 82 and 83 of the
listing. This operation clears the interrupt flag (bit 3)
but keeps the INTMX bit set. This bit enables external
interrupts. The registers associated with unused onchip resources are left at their reset conditions. An
important bit in the MC68HC05EO is the XROM bit
(2,$0C). It defaults to a 1 which is appropriate in this
application. When it is cleared it constrains the data
bus to be input only thus preventing any unnecessary
activity in sensitive applications when writing to
external memory is not required,

001F
0020

_ _including
_ _ _ _ _ stack
_ _ _ _at_ _OOFF)
_ _ _ _ _ _ _ _ _ _ 01 FF
0200
Not used.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 3FFF
Emulator RAM
4000
(64k in 4 x 16k Pages)

7FFF
8000

Load2 EPROM Socket

BFFF
cooo

Figure 7. Memory Map

The MC68HC05EO has the 8-bitindex register common
to all M6805 microprocessors. It is thus not able to
contain a 16-bit extended address. For this reason,
loading and storing in the emulator'S RAM is carried
out using a small program in the micro's RAM. This
program consists of an extended LOA or STA
instruction followed by a two byte address which can
be built in software and an RTS instruction. The fourbyte program resides in RAM at locations W2, ADDEH,
ADDRL and W3. It allows the full 64K map to be
accessed using addresses generated within the
program. Address generation is further complicated
by the requirement that the emulation RAM is in four
16K pages. The two most significant addresses thus
have to be transferred to port lines PBO and PB 1.

SOFTWARE

SERIAL INTERFACE

A listing of the control program used in the emulator
is included in this application note. Some points specific
to the MC68HC05EO are discussed below.

Figure 8 shows a suggested method of wiring up the
RS232 sockets in an emulator with both loading and
dumping capabilities. This arrangement facilitates use
ofthe serial LOAD and DUMP routines ofthe emulator
either via a PC COM port or between a host and
terminal connected by an RS232 link. When using a
PC the "host" socket should be used. As only one pin
on the MC68HC05EO is used, switching is required to
make the required connections. S2 can be eliminated
(or left at "L") if only loading is required, as will often
be the case. To save power in battery applications, the
RS232 interface chip can be switched off usingS1.
The following table shows possible methods of use.

EM64k Control Program

______________________________________________________________________ FFF5
FFF6
MC68HC05EO Vectors
L--_ _ _ _ _ _ _ _ _ _ _ _------'

FFFF

Port D on the MC68HC05EO can be used as a normal
I/O port or can selectively supply special signals. In
this application five of the special function are used.
These function are selected using the register at
address $12. The function used are P02, RtN, A13,
A 14 and A 15. By default only addresses AO through
A 12 are available as this will be sufficient in many
applications. In this application, however, all the
addresses are required. The clock (P02) is used to
qualify the chip selects generated by the MC74HC138
and RtN for control of the emulation RAM. The other
three pins are leftas I/O pins but are not used in this
application. The initialisation of $12 can be seen on
lines 93 and 94 of the software listing.

130

Set-up

Function

S1

S2

Host & terminal

Load

On

L

Terminal and host connected.
Micro looks at data sent from host to terminal (pins 3).

Dump

On

D

Connection between terminal and host broken.
S-records sent to both host (2) and terminal (3).

Load

On

L

S-records loaded from pin 3.

Dump

On

D

S-records sent to pin 2 on "host" socket
(and pin 3 on "terminal" socket).

PC "COM" port

Comments

I
I
I
I

3

I

3

RS232 2
2
RS232
(terminal) ~7~+-.!:.S-~~7~ (host)

Figure 8. RS232 circuit with LOAD/DUMP switching

131

Pin

2
3
4
5
6

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
'28

27512

27256

27128

2764

A15
A12
A7
A6
AS
A4
A3
A2
A1
AO
00
01
02

Vpp

Vpp

Vpp

A13
A14

A13

NC

PGM

PGM

Vss

03
04
05
I
06
07
Chip enable

A10
Output enable

A11
A9
A8
A13
A14
Vee

Figure 9. 27(C) 512. 256. 128 and 64 pin-outs
(Table shows the standard 28-pin EPROMs.
Blank entries indicate that the pin is the same as for the 27(C) 512.)

132

ASSEMBLED LISTING OF THE EM64K CONTROL PROGRAM
* •••••••••••••••••••••••.•••••••••••••••••••••••••••••
MC6BHCOSEO EPROM Ernul ator.
A 6BHCOSEO Is used to ernul ate an EPROM
of up to 64K (27(C)S12) with SRAM which
can be loaded from an EPROM or serially
by S'records via an RS232 Interface and
changed If requl red for de' bug etc.
10
11
12

•• ****** •••••••••••••••••• ***.* ••••••• **.***.****.***

i3
14
15
16
17
1B
19
20
21
22
23
24
25
26
27
2B
29
30
31
32
33
34
35
36
37
3B
39
40
41
42
43
44
45
46
47
4B
49
50
51
52
53
54
55
56
S7

11·Jan·91

P. Topping

00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007
OOOOOOOB
00000009
OOOOOOOe
00000012

PORTA
PORTB
PORTC
PORTO
PORTE
PORTAD
PORTBD
PDRTCD
PORTDD
PORTED
ICR
PORTDSF

PORT A ADDRESS

EaU
EaU
Eau
Eau
Eau
Eau
Eau
Eau
Eau
Eau
Eau
Eau

SOD
SOl
S02
S03
S04
SOS
S06
S07
S08
S09
SOE
$12

I NTERRUPT CONTROL REGI STER
PORTO ALTERNATIVE FUNCTION REGISTER

ORG

S0020

RAM ALLOCATION

RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB
RMB

6

LCD BUFFER

00000020
00000026
0000002B
00000029
0000002a
0000002b
0000002c
0000002d
0000002e
0000002f
00000030
00000031

DTABL
TEMP
WI
W2
ADDEH
ADDRL
W3
W4
W5
W6
ADDRH
STAT

00000032
00000033
00000034
00000035
00000036
00000037
0000003B
00000039
0000003a
OOOOOOfJ
OOOOOOff

CHKSUM RMB
COUNT
RMB
TMP1
RMB
TMP2
RMB
BCNT
RMB
ERTYP
RMB
ERDAT
RMB
OFF
,RMB
'RMB
STACK
RMB
SP
RMB

•

B

•
•

C
0

•
PORT
•
•
•

•

E
A DATA DIRECTION REG.
B •
C •
0 •

E •

2
RAM SUBROUTINE

LOA or STA
ADDRESS MSB
LSB
RTS

STATUS BYTE:'
2: REAL ADDRESS (OFFSET)
4' INVALID ADDRESS (BLDRNG)
S: VERYFING (HOAD)
6: INDIVIDUAL REG. (MEMEX)
7: PUNCH END
CHECKSUM
BIT COUNTER

1
1
1BS
12

em64k.as5

133

S·RECORD BYTE COUNT
ERROR TYPE
ERROR DATA
S-RECORD OFFSET
UNUSED
13 BYTES USED (1 INTERRUPT
AND 4 NESTED SUBROUTINES)

59
60
61
62
63
64
65
66
67
68·0000eOOO
69 000Oe003
70 0000e005
71 0000eOO6
72 OOOOe008
73 OOOOeOOb
74 OOOOeOOd
75 OOOOeOOf
76 00OOeOl2
77 OOOOe014
7B OOOOeOl5
79 0000eOl6
BO 000OeOl7
Bl OOOOeOl8
B2 OOOOeOl_
83 OOOOeOlc
84 OOOOeOle
85 OOOOeOlf

••• ***.******************** ••• *****************.* •••
Idle loop and routIne to decIde whIch
key has been pressed.

.*.*********************••••• ******.*.*.************

cde05f
24fb
5f
b728
d6e09f
bl28
270b
cleObf
273_
5c
5c
5c
5c
20ee
_601
b70e
5c
dce09f

SCAN

RJ

PJ

ORG

SEOOO

JSR
8CC
CLRX
STA
LOA
CMP
BEQ
CMP
BEQ
INCX
INCX
INCX
INCX
BRA
LOA
STA
INCX
JMP

KEYSCN
SCAN

KEY FOUND?
NO. TRY AGAIN

WI
CTAB.X
WI
PJ
LAST
GETCMD

COOE OF PRESSED KEY
FETCH KEYCOOE
THIS ONE 1
YES
NO. LAST CHANCE
YES. ABORT
NO
TRY
THE
NEXT
KEY

RJ
#1
ICR

CLEAR IRQX FLAG

CTAB.X

em64k._sS
87
88
89
90
91
92
93 00OOe022
94 OOOOe024
95
96 OOOOeD26
97 OOOOeOlS
98 OOOOe02.
99
100 OOOOeOl c
101 OOOOeD2 e
102 OOOOeOJO
103 OOOOeD32
104
105 OOOOe034
106 OOOOe036
107 OOOOe038
108.'
109 OOOOe03a
110 OOOOe03c
III OODOe03e
112
113 OOOOe040
114 OOOOe042
115 OOOOe044
116
11 7 OOOOe046
11 B OOOOe048
11 9 OOOOe04a
120 OOOOe04c
121
122 OOOOe04e

*********** •• *.*********************.*********** ••••
Reset rout 1ne.

***********.************************.***************
_tie3
b1l2

LOA
ST"

/lSEJ
PORTOSF

EHABLE PORTO SPECIAL FUNCTIONS
P02. R/W. A13. AI4 & A15

3fOO
_6fO
b705

CLR
LOA
STA

PORTA
/lSFO
PORTAO

01 SPLAY IKEYBOARD
110

_658
blOI
_6fb
blD6

LOA
STA
LOA
.STA

#$58
PORTB
'SFB
PORTBO

3f02
a6ff
b707

ClR
LOA
STA

lUFF

3f03
_tile
b708

CLR
LOA
STA

PORTO
/ISle
PORTOD

BiTS 2. 3 & 4 OUT. NOT USED

3f04
a60f
b709

CLR
lOA
STA

PORTE
/lSOF
PORT EO

BITS 0 - 3 OUT • NOT USED

3f31
3f2b
3f30
3f39

eLR
eLR
CLR
ClR

STAT
ADDRL
ADDRH
OFF

INlTIALlSE
ADDRESS

LOA

#S58

MODE 2. ENABLE {l44115) HIGH

a658

START

GETCMD

MODE 2. ENABLE (144115) HIGH
BITS O. 1. 3·7 OUTPUTS
BIT 2 INPUT

PORTe
ALL OUT. NOT USED

PORTCO

134

123
124
125
126
127
128
129

0000e050
0000e052
0000e055
0000e057
0000e059
0000e05c
0000e05d

b701
cde235
.633
b720
cde1ec
9c
20.1

DSCN

STA
JSR
LOA
STA
JSR
RSP
8RA

PORTB
CLRTAB
I/S33
DTABL
DISTAB

PRI NT
PROMPT

SCAN

em64k .• s5
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
14B
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
J 66
167
168
169
170
171
172
173

....................................................
The keybo. rd rout i ne returns the code
of the pressed key in the .ccumul.tor.

.......................................... .........
."

0000e05f
0000e060
0000.062
0000e064
0000e066
0000e06B
0000e06.
0000e06c
0000e06e
0000.070
OOOOe072
0000e074
0000e076
OOOOe077
0000e079
0000e07b
0000007d
OOOOoOlf
OOOOoOBI
0000eOB3
00000085
00000087
00000DB9
OOOOoOB.
OOOOoOBc

4f
.e06
.b10
b700
b600
b72c
.50f
2719
.dld
b600
b12c
2611
99
b600
.sOf
26f.
.dOo
b600
.50f
26f2
b62c
2503
5.
26d6
81

0000e08d
OOOOoOBf
00000091
0000e093
0000e095
00000097
0000e098
0000009.
0000e09c
0000e090

.60.
b7U
.6H
21fe
2lfe
4.
26f9
3.2f
26f3
81

KEYSCN
KEY!
COLUMN

COLI

COLRET

KEY2
DBOUNC
DlP
DLOOP

CLRA
LOX
ADO
STA
LOA
STA
BIT
BEQ
BSR
lOA
CMP
BNE
SEC
LOA
BIT
BNE
BSR
lOA
BIT
BNE
LOA
BCS
DECX
BNE
RTS
LOA
STA
LOA
BRN
BRN
DECA
8NE
DEC
BNE
RTS

116
I/SlO
PORTA
PORTA
W3
IISOF
COLRET
OBOUNC
PORTA
W3
COL RET
PORTA
I/S0F
COLI
DBOUNC
PORTA
I/S0F
COLI
W3
KEY2
KEY!

/110
W6
/lSFF

DU)OP
W6
DLP

em64k •• 55

135

SETUP
ROW
READ KEYBOARD
STORE IT
KEY CLOSED?
NO GET OUT
ELSE DEBOUNCE
RE· READ KEYPAD
SAME KEY CLOSED
NO. GET OUT
KEY
RELEASED
NO TRY AGAI N
YES DEBOUNC E
STI LL
RELEASED?
NO TRY AGAI N
RETURN CHAR INA· REG
I F VAll 0 GET OUT
ELSE TRY
NEXT ROW

40mS
PAUSE
256XI2
CYCLES

175
176
177
17B
179
1BO
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1BB
1B9
190
191
192
193
194
195
196
197
19B
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
21B
219
220
221
222
223

**** •••• *** ••••••• **** •••• **.11 •••••• ***** •••• ** •••••
Keyboard tabl es.

.................... ******.* •••••••••••• *** •••••••• **
0000e09f
ODOOeOaO
0000eOa3
0000eOa4
0000eOa7
OOOOeOaB
OOOOeOab
OOOOeOae
OOOOeOa f
OOOOeObO
0000eOb3
0000eOb4
0000eOb7
0000eOb8
OOOOeObb
OOOOeObe
OOOOeObf
OOOOeOeO

51
eee27b
6B
eee2db
2B
eee3fB
52
eee321
54
eee31b
62
eee23d
64
eee4fd
3B
eee2eO
48
eee13e

CTAB

0000eOe3
0000eOe4
0000eOe5
0000eOe6
0000eOe7
OOOOeOeB
0000eOe9
OOOOeOea
OOOOeOeb
OOOOeOee
OOOOeOed
OOOOeOee
OOOOeOef
OOOOeOdO
OOOOeOdl
0000eOd2
0000eOd3
OOOOeOd4
0000eOd5
0000eOd6
0000eOd7
OOOOeOdB
OOOOeOd9
OOOOeOda

11

STABl

21
22
24
31
32
34
41
42
44
4B
38
28
1B
14
12
61
5B
68
64
62
54
52
51

lAST

FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP

$51
DUMP1
$6B
DUMP9
$2B
PUNCH
$52
HOAD
$54
VERI FY
$62
MODEJ
$64
MEMEX
S3B
OFFSET
$4B
BRAOFF

FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FC8
FCB
FCB
FCB
FCB
FC8
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB

511
521
522
524
$31
S32
$34
S41
542
544
$4B
$3B
$2B
SIB
$14
512
$61
55B
$6B
564
$62
$54
552
551

em64k. as5

136

lOAD FROM EPROM ( $4000)
lOAD FROM EPROM ($BOOO)
S-RECORD OUTPUT
lOAD S- RECORO
VERI FY (S- RECORD)
GO INTO EMULATOR MOOE
M

READ/CHANGE MEMORY
ADDRESS OFFSET

A

BRANCH OFFSET CALC.

A

BRANCH OFFSET
lOAD OFFSET
OUTPUT S- RECORDS

B
C

10
11
12
13
14
15
16
17

Esc
E
S

CANCEL COMMAND
ENTER COMMAND
lOAO FROM 5BOOO
MEMORY EXAMI NE/CHANGE
EMULATE
VERIFY RAM
LOAD RAM
lOAO FROM $4000

225
226
227
22B
229
230
231
232 OOOOeOdb
233 OOOOeOdd
234 OOOOeOdf
235 0000eOe2
236 0000eOe4
237 0000eOe6
23B,000000eB
239 OOOOeOea
240 OOOOeOed
241 OOOOeOfO
242 0000eOf2
243 0000eOf4
244 0000eOf6
245 OOOOeOfB
246 OOOOeOf.
247 OOOOeOfd
24B OOOOeOff
249 0000el02
250 0000el04
251 0000el06
252 0000el0B
253 0000el0.
254 0000el0d
255 OOOOellO
256 0000ell2
257 0000ell4
25B 0000ell5
259 OOOOe 117
260
261
262
263
264
265
266
267 00000118
26B OOOOell.
269 OOOOelle
270 OOOOelle
271 0000e121
272 0000e123
273 0000e125
274 OOOOel27
275 0000e129
276 0000e12b
277 0000e12d
27B OOOOelU
279
2BO 0000e132
2Bl 0000e138

...................__ ...............................
Build a beginning and ending address
in TEMP. TEMP+ I & AOORH. AOORL resp.

•••••• ****.* •• * ••• ************* •••••• ***** •••••• ****
1931
1531
cde235
a6f4
b724
a677
b725
cdelec
cde5be
2423
b630
b726
b62b
b727
ede570
b7U
ede235
.6fJ
b724
a677
b725
edelee
ede5be
2403
b630
BI
IB31
Bl

BLORNG

BCLR
BCLR
JSR
LOA
STA
LOA
STA
JSR
JSR
BCC
LOA
STA
LOA
STA
JSR
STA
JSR
LOA
STA
LOA
STA
JSR
JSR
B~C

BLORNI

LOA
RTS
BSET
RTS

4.STAT
2.STAT
CLRTAB
IISF4
OTABL +4
liS 77
OTABL +5
I STAB
BLOAOR
BLORNI
AOORH
TEMP
AOORL
TEMP+I
LOAD
W6
CLRTAB
IISn
OTABL +4
liS 77
OTABL +S
OISTAB
BLOAOR
BLORNI
AOORH

EMU LA TI ON ADDRESS
PRI NT
'BA'

o

4. STAT

GET SOURCE AOOR.
VALID?
YES
SAVE IT

FETCH OPCOOE OF I NSTR.
SAVE IT
PRI NT • EA'

GET DESTINATION AOOR
VALID?
YES
INVALID

**.** ••••••••• ***** •• *******.** ••••••• **** •••• * •• * ••
Display message.

••• ****.** •• ***.*;.*** ••••••• ** ••••••••• *** •••••••• **
bf2f
3f33
be2f
d6e132
be33
e720

OISP
01 SLP

3eU
3e33
b633
al06
25ed

ceelec
0000dOd777e6
d6f1600671b6

OLOAO
VERF

STX
CLR
LOX
LOA
LOX
STA
INC
INC
LOA
CMP
BLO
JMP

W6
COUNT
W6
OLOAO. X
COUNT
OTABL.X
W6
COUNT
COUNT
116
01 SLP
OISTAB

FCB
FCB

0.0.SOO.S07 .S77 .SE6
S06 .SFl. S60 .S06. S71.SB6

em64k •• s5

137

283
284
285
286
287
2B8
289
290
291
292
293
294
295
296
297
29B
299

******* •••• *****************************************
Cal cul ate branch offset.

*********** ••• **••• ****.****************************
0000_13_
0000e140
0000_143
00000145
0000_147
0000_149
00OO_14b
000O_14d
0000_14f
0000_ 15 I
0000_153

ad9b
OB313_
b62b
a002
b72b
b630
a200
b730
b62b
b027
b72b
b630
b226
b730
b62f
all f
234.
b630
alff
270b
4d
2674
b62b
al7f
226_
200a

BRAOFF

000~_172

b62b

OFFST2

LOA

AOORL

0000_174
0000_176

alff
2766

eMP
BEQ

#SFf
OVRERR

00000178
0000e17.
0000_17c
0000_17_

a180
2562
ad06
cceOOO

CMP
8LO
BSR
JMP

I/S80
OVRERR
USE
SCAN

0000_181

cce04_

ORET

JMP

GETCMO

cde235
a6d6
b720
a6b5
b721
a6f1
b7U
a6_6
b723
b62b
cde5f2
97
b627
abOl
b72b
b626
a900
b730

USE

JSR
LDA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
JSR
TAX
LOA
ADO
STA
LOA
AOC
STA
TXA
BCLR

CLRTA8
I/S06
OTABL
/lS85
OTABL+l
I/SF1
OTABL+Z
I/$E6
OTABL+3
AOORL
PRTDAT

300 0000.155
301 0000_157
302
303
304
305
306
307
30B
309

0000.159
0000_15b
0000_15d
0000_15f
0000_161
0000_163
0000_165
00000167

310 0000_168
311
312
313
314
315
316
317
31B
319
320
321
322
323
324
325
326

0000_16a
0000016c
0000016_
00000170

OKI

BSR
BRSET
LOA
SUB
STA
LOA
SBC
STA
LOA
SUB
STA
LOA
SBC
STA
LOA
eMP
BLS
LOA
CMP
BEQ
TSTA
8NE
LOA
CM?
8HI
BRA

BLORNG
4.STAT.ORH
... OORL
/12
AOORL
AOORH
/10
AOORH
AOORL
TEMP+l
AOORL
AOORH
TEMP
AOORH
W6
/J$l F
OFFSTl
AOORH
#SFF
OffST2
OVRERR
AOORL
1/$7F
OVRERR
OKI

NO FI NO APPARENT

OFfSET

CHECK OPCOOE
FOR BIT BRANCH

+ OR - OFFSET?
CHECK OFFSET
FOR +/- 0

PRINT IT IF VAllO

om64k .• s5
328
329 0000e184

330 0000_187
331
332
333
334
335
336
337
33B
339
340
341
342
343
344
345
346
347
34B

00000189
0000e18b
OOOO_IBd
oooo_IBi
0000_191
00000193
0000_195
0000_197
0000_"199
0000_19c
0000_19d
0000_19f
OOOO_lal
0000_la3
000001a5
0000_la7
0000_la9
OOOO_laa

9f
1531

TEMP+l
#1
AOORL
TEMP
#0
AOORH
2. STAT

138

PRI NT • USED'

PRI NT' OFFSET

PUT INTO
INSTRUCTION

349
350
351
352
353
354
355
356
357
35B
359
360
361
362
363
364
365
366
367
36B
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383

JMP

STORE

LOA
SUB
STA
LOA
SBC
STA
CMP
BEQ
TSTA
BNE
LOA
CMP
BHI
BRA

AOORL
1/1
AOORL
AOORH

OOOOelac

cce56Z

OOOOelaf
OOOOelbl
0000elb3
OOOOe I b5
0000elb7
OOOOe I b9
OOOOelbb
OOOOelbd
OOOOelbf
OOOOelcO
0000elc2
0000elc4
0000elc6
OOOOeleB

b6Zb
aOOI
b7Zb
b630
a200
b730
alff
270b
4d
261c
b62b
.17f
2216
200a

OFFSTl

OMOeica
OOOOelee
OOOOelee
OOOOeldO
0000eld2

b62b
alfe
240e
alBO
250a

OFFST3

LOA
CMP
BHS
CMP
BLO

AOORL
IISH
OVRERR
IISBO
OVRERR

0000eld4
0000eld6
OOOOeldB
OOOOelda
OOOOeldc

3c27
2602
3c26
adaB
200b

OK2

INC
BNE
INC
BSR
BRA

TEMP+I
OFFITS
TEMP
USE
SCJMP

OOOOelde
OOOOeleO
0000ele2
0000ele4
0000ele6
0000ele9

a6d7
b7Z4
a660
b7Z5
cde616
cceOOO

LOA
STA
LOA
STA
JSR
JMP

IIS07
OTABL+4
I/S60
OTABL +5
PRTAOR
SCAN

OFFITS

OVRERR

SCJMP

ADJUST FOR
BIT BRANCH

110
AOORH
IISFF
OFFST3
CHECK FOR
OVRERR
AOORL
US7F
OVRERR
OK2

NEG OFFSET?
YES
+/-

o AND

-I

PRINT IF VALID

PRI NT "OR"

em64k.as5
385
3B6
387
388
389
390
391
392
393
394
395
396
397
39B
399
400
401
402
403
404
405
406
407
408
409
410
411

****.************.******.**************************.
Oisplay table contents.

*-*---_._._. __.-.-.-.-. __ ._ .. _._._._._._... _-------OOOOelec
OOOOelee
OOOOel fO

1701
ae05
e620

OISTAB

0000elf2
OOOOel f4
OOOOe I f6
OOOOel fB
0000elf9
OOOOelfb
OOOOelfd
OOOOel ff
0000e201
0000e203
0000e204
0000e206
0000e208
0000e209
OOOOe20b
0000e20d

of28
IdOO
ae08
48
2402
IcOO
leOO
!f00
IdOO
Sa
26f2
be28
Sa
2ae5
1601
81

NT!

01 SCHR

OISI

0lS2

BCLR
LOX
LOA

3. PORTB
1/5
OTAPL.X

ENABLE (144115) LOW

STX
BCLR
LOX
LSLA
BCC
BSET
BSET
BCLR
BCLR
OECX
BNE
LOX
OECX
BPL
BSH
RTS

WI
6.PORTA
1/8

SAVE INDEX
CLEAR DATA

LOAD 01 SPLAY

OISI
WI

SET UP
8IT OF
ACCUMULATOR
CLOCK
IT
CLEAR DATA
COMPLETE?
NO
RESTORE I NOH

OISCHR
3.P01HB

ENABLE (144115) HIGH

0lS2
6.PORTA
7.PORTA
7. PORTA
6.PORTA

139

412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
42B
429
430
431
432
433
434
435
436
437

* •••• *.*********.**.**********.******************* •• ** ..
S-record Input RAM access I ng.

*********************************.*********** ••• * .......
8SET
BRSET
BCLR
BSET
BRSET
BCLR
LOX
STX
BSET
BCLR

I. PORTB
7 .ADDRH .AI5H
I. PORTB
O. PORTB
6 .ADDRH .AI4H
O. PORTB
ADDRH
ADDEH
6.AODEH
7.AODEH

bf29

BRSET
LOX
STX
JSR
STA
LOX
STX

5.STAT.L3
IISC7
W2
W2
W4
#SC6
W2

be29

JMP

W2

0000e20e
0000e210
0000e213
0000e215
0000e217
0000e21a
0000e21e
0000e21e
0000e220
0000e222

1201
Oe3002
1301
IDOl
Oe3002
1101
be30
bf2a
le2a
I f2a

0000e224
0000e227
0000e229
0000e22b
0000e22d
0000e22f
0000e231

Oa3108
bf29
bd29
b72d

ODOOe233

RAMACC

AI5H

AI4H

aec7

aec6

L3

XFER AI4 & AI5 TO PORTB
AI5 HIGH
NO
YES
AI4 HIGH
NO
YES

10
15
20
25
30
33
37
42
47

AI4 HIGH
AI5 LOW

16
4
2
13

52
54
5B
74
78
80
93

READING
NO. WRITING (STA)
STA IN
RAM SUBROUTINE
SAVE FOR READBACK CHECK
READING (LOA)
LOA IN RAM

14

107

5
3

121 (89 FOR READ) WITH JSR

em64k .as5
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477

*********************.*********************,..********
Clear dIsplay table.

*************************«***;rr********* •• ****.*,,* •••
0000e235
0000e237
0000e239
0000e23.
0000e23e

ae05
6f20
5a
2.fb
81

CLRTAB
CLRLOC

LOX
CLR
DECX
BPL
RTS

115
DTABL. X
CLRLOC

CLEAR SIX
LOCATIONS IN
DISPLAY TA8LE

****************************************************
Emul.tor mode.

.***************************************************
0000e23d
0000e240
0000e242
0000e244
0000e246
0000e248
0000e24.
0000e24e
0000e24f
0000e252
0000e254
0000e256
000(}e258

ede235
.6f1
b720
.673
b721
.663
b723

MOOEJ

ede05f
24fb
.162
2703
eee04e

KSC

0000e25b
0000e25d
0000e25f
0000e261
0000e263
0000e265
0000e267

a62B
b701
a6f1
b720
a6d6
b721
.6dO

CONF

cdelec

JSR
LOA
STA
LOA
STA
LOA
STA
JSR
JSR
BCC
CMP
BEQ
JMP

CLRTAB
#$F1
OTABL
11$73
DTABL+I
#$63
DTABL+3
DISTAB
KEYSCN
KSC
#$62
CONF
GETCMD

LOA
STA
LOA
STA
LOA
STA
LOA

#$28
PORTB
#SFI
DTABL
I/S06
DTABL+l
IISDO

140

WAIT UNTI L EPROM REMOVED
EMULATION CONFIRMED?

MODE 3. ENABLE (144115) HIGH

478
479
480
481
482
483
484
485
486
487

0000e269
0000e26b
0000e26d
0000e26f
0000e271
0000e273
0000e275
0000e277

b722
a677
b723
a6fO
b724
a6f1
b725
edelee

0000e27 a

8e

STA
LOA
STA
LOA
STA
LOA
STA
JSR
STP

DTABL+2
#S77
DTA8L +3
IISFO
OTABL +4
IISF!
OTABL +5
DISTAB

A

STOP

em64k.as5
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
SID
511
512
513
514
515
516
517
518
519
520

521
522
523
524
525
526

* ** ** ** ** *. ****** '* '* * * ** ** ** ** ** ** ** ** *. ** ** ** ** ** ** '*
Her EPROM contents to RAM from emulation
socket (S4000).

.

***** ** ** ** ** ******** '* '*.* **.*.* ** * •• "11 **** .*.", **",* ** *
OOOOe27b
OOOOe27e
0000e281
0000e283
0000e285
0000e287
0000e289
0000e28b
0000e28d
0000e290
0000e292
0000e294
0000e297
0000e299
0000e29b
0000e29d
0000e29f
0000e2al
0000e2a3
0000e2a5
0000e2a8
0000e2aa
0000e2ae
0000e2af
0000e2bl
0000e2b3
0000e2b5
0000e2b7
0000e2b9
000Oe2bb
DOOOe2bd

ede235
edelee
a658
b701
1431
3f2b
3f30
1201
Oe3002
1301
IDOl
Oe3002
1101
be30
bf2a
!f2a
le2a
IdOl
leOI
ede570
leOI
!f01
ede562
3e2b
2602
3e30
b630
26d2
b62b
26ee
cce04e

DUMPI

LLPI

ADI5H

ADI4H

SKPH

JSR
JSR
LOA
STA
BSET
CLR
CLR
BSET
BRSET
BCLR
BSET
BRSET
BCLR
LOX
STX
BCLR
BSET
BCLR
BSET
JSR
BSET
BCLR
JSR
INC
BNE
INC
LOA
BNE
LOA
BNE
JMP

CLRTAB
OISTAB
#S58
PORTB
2.STAT
ADDRL
AODRH
I • PORTB
7 .AODRH .ADI5H
I, PORTB
O. PORTB
6.ADDRH.ADI4H
O. PORTB
ADDRH
ADOEH
7.ADDEH
6.ADDEH
6. PORTB
7. PORTB
LOAD
6. PORTB
7. PORTB
STORE
ADDRL
SKPH
AOO'RH
AODRH
LLPI
AOORL
LLPI
GETCMD

527

141

MODE 2. ENABLE (144115) HIGH
REAL ADDRESS (NO OFFSET)

10
15
20
25
30
33
37
42
47

XFER AI4 & AI5 TO PORTB
AI5 HIGH
NO
YES
AI4 HIGH
NO
YES
AI5 LOW
AI4 HIGH

READ FROM EMULATOR SOCKET
LOAD BYTE
WRITE TO RAM
STORE BYTE

MSB ZERO?
YES. LSB ZERO
IF SO. FINISHED

528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546

••••••••••••••••• **.**** •••••• ** ••••• ** •••••• *******
Offset for S- record 1 oad/~end_

** ••• **.* •••••• ** •••• ** •••••••••••••••••••••• ** ••• **
0000e2eO
0000e2e2
0000e2e4
0000e2e6
0000e2e8
0000e2ea
0000e2ee
0000e2ee
0000e2dO
0000e2d2
0000e2d4
0000e2d6
0000e2dB

le31
1431
a6d7
b720
a671
b721
b722
3f23
3f2a
3f30
a639
b72b
cce506

OFFSET

8SET
BSET
LDA
STA
LDA
STA
STA
CLR
CLR
CLR
LDA
STA
JMP

6.STAT
2.STAT
/lS07
DTABL
/lS71
OTABL+I
OTABL+2
OTABL+3
AODEH
AODRH
1I0FF
AODRL
MEMEX3

NO ADDRESS INC/DEC
REAL ADDRESS
0

em64k.as5
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
'56B
569
570
571
572
573
574
575
576
577
57B
579
580
581
5B2
583
584
585
586
5B7
588

•••• ** ••• *** •••• ** ••••••••• **** •• ** ••••• ** ••• ** •••••
Xfer EPROM contents to RAM from auxiliary
socket (S8000)_

.

• **** ••• *. * •••••• *.******** **** **** ••• * **** •••••••••
JSR
JSR
LDA
STA
BSET

CLRTAB
01 STAB
/lS58
PORTB
2.STAT

BSR
INC
LDA
AND
CMP
BLO
BSR
JMP

Tl9
PORTB
PORTB
113
113
HOP
Tl9
GETCMD

Tl9

CLR
CLR

ADDRL
ADDRH

LLP9

LDX
STX
BSET
BCLR
JSR
BCLR
BSET
JSR
INC
BNE
INC
LDA
CMP
BNE

AODRH
ADDEH
7.ADDEH
6.AODEH
LOAD
7.AODEH
6.AOOEH
STORE
AOORL
SKPH9
AODRH
ADDRH
I/S40
LLP9

0000e2db
0000e2de
0000e2el
0000e2e3
0000e2e5

ede235
cdelec
a658
b701
1431

OUMP9

0000e2e7
0000e2e9
0000e2eb
0000e2ed
0000e2ef
0000e2f I
0000e2f3
0000e2f5

adOf
3cOI
b601
a403
al03
25f4
ad03
cce04e

HOP

0000e2f8
OOOOelfa

3f2b
3f30

0000e2fe
OOOOelfe
0000e300
0000e302
0000e304
0000e307
0000e309
0000e30b
0000e30e
0000e310
0000e312
0000e314
0000e316
0000e318

be30
bf2a
le2a
Id2a
cde570
!f2a
le2a
cde562
3c2b
2602
3c30
b630
al40
26e2

0000e31 a

81

SKPH9

RTS

em64k.as5

142

MODE 2. ENABLE (144115) HIGH
REAL ADDRESS (NO OFFSET)

NEXT PAGE

LAST PAGE
YES

YES
AI5 HIGH
AI4 LOW
READ FROM AUX I LlAIU' SOCKET
AI5 LOW
AI4 HIGH
WRITE TO EMULATION RAM

LAS} ADDRESS $3FFF
FINISHED 1

590
591
592
593
594
595
596
597
59B
599
600
601
602
603

604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639

******** •• ***** •• *******.*.*.***.************ ••• ****
RS232 (9600) S-Record receiver (4MHz).

•••••• **** •• ** ••••• *** ••• ** ••• ***** .......... **.** ••••
VERI FY

0000e31b
0000e31d
0000e31 f
0000e321
0000e323
0000e324
DOOOe326
0000e328

la31
ae06
2003
Ib31
Sf
a681
b72c
cde1l8

0000e32b
0000e32d
0000e32f
0000e331

INPUT

0000e333
0000e335
0000e337
0000e339

ad5f
al53
26fa
ad.59
al39
276f
al31
26fO

0000e33b
0000e33d
0000e33f
0000e342

3f32
3f35
cde3bd
b736

LNGTH

0000e344
0000e347
0000e349
0000e34b
0000e34e

cde3bd
b039
b730
cde3bd
b72b

ADOR

0000e350
0000e:Y.i3
0000e355
0000e358
0000e35a
0000e35d
0000e35f
0000e361
0000e363
0000e366
0000e368
0000e36a
0000e36c
0000e36e
0000e370

cde3bd
271d
Ob310b
b72f
cde20e
bl2f
2658
2007
cde20e
bl2d
263f
3c2b
2602
3c30
20de

DLOP

TLOAD
L4

L5

L6

NOOVR

BSET
LOX
BRA
BCLR
CLRX
LOA
STA
JSR

5. STAT
116
L4
5.STAT

BSR
CMP
BNE
BSR
CMP
BEQ
CMP
BNE

I NCHD
II' S'
INPUT
I NCHD

//$81
W3
DISP

SERIAL VERI FY

SERIAL LOAD
RTS
DISPLAY -LOAd OR UErI Fy-

INPUT

7 BIT ASCII INTO A
S ?
NO. TRY AGAIN
YES. GET NEXT CHARACTER
9 ?
YES. FI NI SH
NO. I ?
NO. TRY AGAIN

CLR
CLR
JSR
STA

CHKSUM
TMP2
BYTE!
BCNT

YES. CLEAR CHECKSUM
AND TEMP. STORE
AND GET BYTE COUNT
AND SAVE IT

JSR
SUB
STA
JSR
STA

BYTEI
OFF
ADDRH
BYTEI
ADORL

ADDRESS HIGH
OFFSET

JSR
BEQ
BRCLR
STA
JSR
CMP
BNE
BRA
JSR
CMP
BNE
INC
BNE
INC
BRA

BYTEI
CHCK
5.STAT.L5
W6
RAMACC
W6
ERR7
L6
RAMACC
W4
ERR2
AOORL
NOOVR
ADDRH
OLOP

1/'9'
NINE

1/'1'

em64k.as5

143

ADORE SS LOW

75

66

67

78
83
B7
153
156
159
162
150
153
156
161
164
169
172

GET A BYTE
LAST BYTE ?
NO. VERIFYING
YES
READ RAM
SAME

167
170
175
178

NO. WRITE TO RAM
READBAC K
OK ?
INCREMENT LS ADDRESS
OVERFLOW?
YES. INC. HIGH BYTE

641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
6B2
683
684
6B5
686
687
688
689
690
691
692
693
694
695

************* •• *********** •• **.********.********* •• ****
Checksum byte & error routine.

*.************.****************.*.*****.*****.*****.* ••
0000e372
0000e374
0000e376
0000e378

bb32
b732
al ff
27bl

0000e37a
0000e37e
0000e37e
0000e380
0000e381
0000e3B4
0000e3B6
0000e3B9

aeOI
b73B
bf37
9f
ede5f2
3f24
ede616
eeeOOO

CHCK

ERR

ADD
STA
CMP
BEQ

CHKSUM
CHKSUM
II$FF
INPUT

DEBUG
I S CHECKSUM BYTE OK
YES. AND AGAIN

LOX
STA
STX
TXA
JSR
CLR
JSR
JMP

III
ERDAT
ERTYP

DEBUG
DEBUG

PRTDAT
DTABL+4
PRTADR
SCAN

********************* •• ********* •• *********************
Input routine. MC68HC05EO : 0.5 uS.
Cyel es per bi t at 9600 baud : 208

*****************.************.*.*************.*.******
BSR
BRCLR
BRSET
LOX
STX
BSR

DELl91
2. PORTB.·
2. PORTB.·
1/7
COUNT
DELlIO

4
110

BSR
BRCLR
RORA
DEC
BNE

DELl91
2.PORTB.ZER

191
5

0000e3Be
0000e3Be
0000e391
0000e394
0000e396
0000e39B

ad60
050lfd
0401 fd
ae07
bf33
ad58

I NCHD
INCH

0000e39a
0000e3ge
0000e39f
000003aO
000003a2

ad52
050100
46
3a33
26f6

I NBT

0000e3a4
000003a5

44
81

0000e3a6

eee04e

NI NE

JMP

GETCMO

0000e3a9
0000e3ab
0000e3ad
0000e3a f
0000e3bl
OOOOe3b3
0000e3b5
OOOOe3b7
00OOe3b9
0000e3bb

ae02
20ef
ae03
20eb
ae04
20e7
ae05
20e3
ae07
20bf

ERR2

LOX
BRA
LOX
BRA
LOX
BRA
LOX
BRA
LOX
BRA

112
ERR
113
ERR
114
ERR
115
ERR
117
ERR

ZER

COUNT
I NBT

LSRA
RTS

ERR3
ERR4
ERRS
ERR7

191
5

5
3

6
10
120

144

+/·3

OF 1st BIT

+ 120·208-103

196
199
204
207
16
22

em64k.as5

GET OUT OF BIT
IS LINE HIGH 1
YES. WAIT FOR START
7 DATA BITS TO READ

CYC 2 (lOS) READ
SAVE BIT

MSB A ZERO

REAOBAC K FROM RAM
LESS THAN ASC I I
BETWEEN ASC I I 9
MORE THAN ASC I I
VERI FY ERROR

A

697
69B
699
700
701
702
703
704
705
706
707
70B
709
710
711
712
713
714
715
716
717
71B
719
720
721
722
723
724
725
726
727
72B
729
730
731
732
733
734
735
736
737
73B
739

.***.** •••• * •• *.**.** ••••• *•• * •• *.*.*.*.*.**.*.*.*.* •• "*
Byte input sub- rout ines_

* * * ** ** ** * * ** ** * * ** ** ** ** ** * * * * ** ** ** * * * * * * ** ****** ***"*
0000e3bd
0000e3bf
0000e30 I
0000e302
0000e303
0000e304
0000e305
0000e307
0000e309
0000e30b
0000e30d
0000e3cf
0000e3dl
0000e3d3
0000e3d5
0000e3d7

adod
adl7
4B
4B
4B
48
b734
b635
bb32
b732
adbd
ad07
bb34
b735
3a36
BI

BYTE I

0000e3dB
0000e3da
0000e3do
0000e3de
0000e3eO
0000e3e2

a 130
25dl
al39
2203
a030
BI

ASC I I

0000e3e3
0000e3e5
0000e3e7
0000e3e9
0000e3eb
0000e3ed

al41
250a
al46
220a
a037
BI

MT9

0000e3ee
0000e3fO
0000e3f2
0000e3f4
0000e3f5
0000e3f7

ael d
2002
aelO
5a
26fd
81

OE1l91

NFNO

OElllO
DELAY

I NCHO
ASC I I

BSR
BSR
LSLA
LSLA
LSLA
LSLA
STA
LOA
ADD
STA
BSR
BSR
ADD
STA
DEC
RTS

TMPI
TMP2
CHKSUM
CHKSUM
INCHD
ASC I I
TMPI
TMP2
BCNT

CMP
BLO
CMP
BHI
SUB
RTS

/1$30
ERR3
11$39
MT9
11$30

CMP
BLO
CMP
BHI
SUB
RTS

11$41
ERR4
11$46
ERR5
/1$37

LOX
BRA
LOX
OECX
BNE
RTS

1129
DELAY
1116

22
35

57

4

69
71
74
79
B3

22
35

3

57
60
64
69
75

10
13
19
12
15
17
20
23
29

MS NI BBLE
WHAT WAS IT
YES
SHI FT
IT
UP
AND SAVE IT
RESTORE BYTE
ACCUMULATE
I N CHECKSUM BYTE
LS NI BBLE
WHAT WAS IT
ADD TO MS NIBBLE
SAVE BYTE
DECREMENT BYTE COUNT

BEFORE ZERO?
YES. NOT LEGAL
AFTER NINE
YES TRY A·F
0·9. CONVERT TO HEX

BEFORE A ?
YES. NOT LEGAL
AFTER F )
YES, NOT LEGAL
A·F, CONVERT TO HEX

6xX
12+6X (INC BSR)

DELAY

em64k.as5
741
742
743
744
745
746
747
74B
749
750
751
752
753
754
755
756
757
75B
759
760
761

*** ** ** ** ** ** ** *. **.* **.* ** ** ** **** ** ** ** **** *'* **** *
RS232 (9600

0000e3fB
0000e3fa
0000e3fd
0000e400
0000e402
0000e404
0000e406
0000e40B
0000e40a
0000e400
0000e40e
0000e410

1406
odeOdb
0831a6
be26
b726
bf30
b62b
be27
bf2b
b727
I f31
1531

PUNCH

0000e412
0000e414

b627
b02b

LOOPI

@

4MHz) S'Reoord transmitter.

BIT 2 OUTPUT
BUI LD RANGE
NEW ADDRESS ENTERED
NO, SWAP .AOORESSES

BSET
JSR
BRSET
LOX
STA
STX
LOA
LOX
STX
STA
BCLR
BCLR

2, PORTBO
BLORNG
4.STAT.NINE
TEMP
TEMP
AOORH
AODRL
TEMP+I
ADORL
TEMP+I
7, STAT
2, STAT

CLEAR END FLAG
EMULATION ADDRESS

LOA
SUB

TEMP+I
AODRL

END LSB
CURRENT LSB

145

762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
7B6
787
788
789
790
791
792
793
794

0000e416
0000e418
0000e41a
0000e41 c
0000e41e
0000.420
0000e421
0000e423
0000e425
0000e427
0000e429

b72f
b626
b230
260d
b62f
4c
270B
a120
2204
le31
2002

0000e42b
0000e42d
0000e42f
0000e431
0000e433
0000e436
0000e438
0000e43.
0000e43c
0000e43e
0000e440
0000e442
0000e444
0000e446

a620
ab03
b736
a653
cde484
a631
ad4a
3f32
b636
ad72
b630
ad6e
b62b
ad6a

LOTS
LTE20

0000.448
000Oe44b
000Oe44d
00OOe44f
0000e451
0000e453

cde570
3c2b
2602
3c30
ad5f
26f3

LOOP2

NOVR

STA
LOA
SSC
SNE
LOA
INCA
8EQ
CMP
BHI
BSET
BRA

116
TEMP
ADDRH
LOTS

LOA
ADO
STA
LOA
JSR
LOA
BSR
CLR
LOA
BSR
LOA
8SR
LOA
aSR

/lS20
#S03
BCNT
#'S'
OUCH
#T
OUCH
CHKSUM
8CNT
BYTEO
AODRH
BYTEO
ADDRL
BYTEO

JSR
INC
SNE
INC
8SR
BNE

LOAD
AODRL
NOVR
AODRH
8YTEO
LOOP2

116
LOTS
1/$20
LOTS
7,STAT
LTE20

01 FFERENCE LSS
END MSS
CURRENT MSB
MSB ZERO?
YES, LOOK AT LSB
ADJUST
WAS $FF ?
MORE THAN 23
IF SO USE 23
NO, LAST SI RECORD
LESS THAN OR EQUAL TO 20

AOo 8YTE CqUNT & ADDRESS
No, BYTES THIS SI RECORD
S

BYTE COUNT
ADDRESS HIGH

ADDRESS LOW
GET BYTE
INCREMENT APORESS
OV"ERFLOW ?
YES, INC, HIGH BYTE
SEND BYTE
LAST BYTE ?

em64k .as5
796
791
79B
799
800
SOl
802 0000e455
803 ODOOe457
804 0000e458
805 0000e45a
806 OOOOe45c
807

".'11: ** ** **.*.* ** **.* .*** * .. ****** ****.* ** *.** ** ****** ••• *
Checksum byte.

******************* ••••••• * •• *.* •• **.*** •• *** ••• * •••• **
b632
43
ad58
ad22
0f31b3

CHKSUM
BYTEO
CRLF
7 ,STAT ,LOOPI

CHECKSUM
REOUIRED CHECKSUM BYTE
SEND IT
CRLf
Fl NI SHE'O

* .*** ** ** * * ** ** ** * ••• ** * ••• ** ** *. **.* ** ** ** * ••• ** ** ** ••

BOa
809
810
811
812
813
814
815
816
817
818
B19
820
821
822
823
824
825
826
827

LOA
COMA
BSR
BSR
BRCLR

S9 record,

.* .................. * ••••• * ••• ** ••••••••••• * ...... * •• * •••
0000e4Sf
00000461
0000e463
0000e465
0000e467
0000e469
OOOOe4Gb
000Oe46d
0000.46 f
OOO0e471
0000e473
0000e415
0000.477
0000e479

0653
ad21
a639
ad1d
a603
ad47
a600
ad43
a600

adlf
a6fc
ad3b
adOS
1506

LOA
8SR
LOA
BSR
LOA
BSR
LOA
8SR
LOA
85R
LOA
BSR
8SR
BeLR

#'S'
OUCH

11'9'
OUCH
#$03
QYTEO
#$00
SYrEO
IISOO
BYTEO
#SFC
BYTEO
CRlF
2,PORTBO

146

BYTES

DUMMY (0)
ADDRESS
CHECKSUM
BIT 2 INPUT

828
829
830
831
832

0000e47b

cce04e

0000e47e
0000e480
0000e482

a60d
ad02
a60a

CRLF

JMP

GETCMO

LOA
8SR
LOA

USOO
OUCH
#SOA

CR
LF

em64k.as5
834
835
836
837
838
839
840
841
B42
843
844
845
846
847
84B
849
850
851
B52
853
854
855
B56
B57
B5B
859
B60
B61
862
863
B64
865
B66
867
86B
B69
B70
871
B72
873
B74
875
876
B77
B7B
B79
BBO
BBI
BB2
BB3
8B4
BB5
BB6
B87
8BB
BB9
890

* **.* ** ** ** ** ** ** * .. **. * ** * * ** ** ••• * *. *_ * •• *

*.

1<

* * .. * 1< ** "".

Output routine. 208 cycles per bit.
* * •••• * * *.*
0000e484
0000e486
0000e4B8
0000e48a
0000e48b
0000e48c
0000e48f
0000e490

1401
aeOa
bf33
9d
9d
cde3f4
98
2008

OUCH

0000e492
0000e494
0000e497
0000e498
0000e499
0000e49a
0000e49c
0000e4ge
0000e4aO
00000402
0000e4a4
0000e4a6
0000e40B

aele

OUTBT

0000e4a9
0000e4a b
0000e4ad
0000e4af
0000e4bl

ab30
a139
2302
ab07
BI

cde3f4
9d
99
46
2504
1501
2004
1401
2000
3a33
26ea
Bl

OEL3
STAR

OUI
OBO

ASC 10

NMT9

*_ .. **. * •• * •••• * *. -* •• * * •• **. * '" '" *. *. *. ** ** **

BSET
LOX
STX
NOP
NOP
JSR
CLC
BRA

2. PORTB
#10
COUNT

LOX
JSR
NOP
SEC
RORA
BCS
BCLR
BRA
BSET
BRA
DEC
BNE
RTS

1128
DELAY

ADD
CMP
BLS
ADD
RTS

IIS30
IIS39
NMT9
#S07

***. * **** ** **

11

72
2

83
85
B8

180
2

182
IB4
186
189
192
197
200

OELAY
STAR

OUI
2.PORTB
OBD
2.PORTB
OBD
COUNT
OUTBT

MAKE SURE IT' S HIGH
10 BITS TO SEND
START. B DATA. STOP

START A ZERO

FILL WITH ONES FOR STOP
GET A BIT
1 ?
NO
YES

205
20B

DONE

CONVERT TO ASCII
0- 9
NO. A-F
14

._*_.* ** **.* ** ** * * *_ *. * * * * *. * .. *. * ** ** * * __
1<

Byte output sub-routine.

*. ---*

*. *.". * * ** * *** *.;. *. ** *. *. **
0000e4b2
0000e4b4
0000e4b5
0000e4b6
0000e4b7
0000e4bB
0000e4ba
0000e4bc
0000e4be
0000e4eO
0000e4e2
0000e4e4
0000e4e6
0000e4e8
0000e4ea
0000e4ee

b734
44
44
44
44
adef
adeB
b634
bb32
b732
b634
a40f
adel
adba
3a36
81

BYTEO

STA
LSRA
LSRA
LSRA
LSRA
BSR
BSR
LOA
ADD
STA
LOA
AND
BSR
BSR
DEC
RTS

** * ..... * ** ** *. **. '" * * •• "'. * *

TMPI
SHI FT
DOWN TO
GET MSB
ASCIO
OUCH
TMPI
CHKSUM
CHKSUM
TMPI
IlsOF
ASCIO
OUCH
BCNT

em64k.as5

147

& CONVERT

RESTORE BYTE
ACCUMULATE
IN CHECKSUM BYTE
lSB
CONVERT IT
DEC REMENT BYTE COUNT

892
893
894
895
896
897
89B
899
900
901
902
903
904
905
906
907
90B
969
910
911
912
913
914
915
916
917
91B
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
93B
939

.._-......._................_.......................
Segment codes for the MC14S000.

** •• ******* ••• ***************.* •••• *.***** •• ***** •••
0000e4cd
0000e4ce
0000e4cf
0000e4dO
0000e4dl
0000e4d2
0000e4d3
0000e4d4
0000e4dS
0000e4d6
0000e4d7
0000e4d8
0000e4d9
0000e4da
0000e4db
0000e4dc

d7
06
e3
a7
36
b5
fS
07
f7
b7
77
f4
dl
e6
f1

0000e4dd
0000e4eO
0000e4e2
0000e4e4
0000e4e6
0000e4e8
0000e4ea

cde235
a6f1
b721
0660
b722
b723
ceeOS9

71
ERROR

FCB
FCB
FCB
FCB
FCB
FCB
FCB
FC8
FC8
FCB
FCB
FCB
FCB
FCB
FCB
FCB

S07
S06
$E3
SA7
S36
SB5
SFS
S07
SF7
SB7
S77
SF4
SOl
H6
HI
$71

JSR
LOA
STA
LOA
STA
STA
JMP

CLRTAB
I/SFI
OTABL+I
I/S60
OTABL+2
OTABL+3
OSCN

4
S

A
B

*** •• ***.***.****************************
I NPUT ONE CHARACTER
A REGISTER CONTAINS HEX VALUE
X REGISTER CONTAINS HEX VALUE

_._.. -.-.*-_ •. _._._._._.-.••• _._._._._ ••0000e4ed
0000e4fO
0000e4f2
0000e4f3
0000e4f6
0000e4fB
0000e4f9
0000e4fb
0000e4fe

ede05f
24fb
Sf
dleOe3
2703
Se
20fB
9f
BI

em64k. a 55
941
942
943
944
945
946
947
948
949
950
9S1
952
953
9S4
955
956
957

CTABL

CHRI N

CHRI NI

CHRIN2

JSR
BCC
CLRX
CMP
BEQ
I NCX
BRA
TXA
RTS

KEYSCN
CHRI N

GET KEY
I F NOT VAll 0 RETRY

STABL .X
CHRI N2

CONVERT
TO HEX

CHRINI
I F CANCEL

..._._. __ ._._ ....._._--_... _---_._._._....-._-_._ ..Memory examine/change.

--_......._-_ .. *._.* .......__ ...*-_.................
0000e4fd
0000e4ff
0000eS02
0000e504

1531
edeSb9
a110
2752

MEMEX

BCLR
JSR
CMP
BEQ

2. STAT
GETADR
1/$10
MEMEX4

EMULATION ADDRESS
GET ADDRESS
ESCAPE ?

0000e506
0000e508
0000e50b
0000e50e
0000e510
0000e512

ad6B
edeSf2
ede5a f
a110
2746
all1

MEMEX3

BSR
JSR
JSR
CMP
BEQ
CMP

LOAD
PRTOAT
GETNYB
1/$10
MEMEX4
1/$11

LOAD DATA
PRI NT IT
GET NEW NIBBLE
ESCAPE ?

148

ENTER ?

95B
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
9B1
982
983
984
985
986
987
988
989
990
991
992
993
994

0000e514
0000e516
0000e51B

271a
a113
272e

BEQ
CMP
BEQ

AORI NC
11$13
AOROEC

0000e51a
0000e51c

alOf
2208

CMP
BHI

IISOF
CMOMOL

0000e51e
0000e521
0000e524
0000e526
0000e52B
0000e52a
0000e52c
0000e52e
0000e530
0000e533
0000e535
0000e537
0000e539
0000e53c
0000e53e
0000e540
0000e542
0000e544
0000e546
0000e548
0000e54b
0000e54d
0000e54f
0000e551
0000e553
0000e556
0000e558
0000e55b
0000e55d
0000e55f

cde5f2
cde59d
25f8
a III
2614
b629
ad34
25d6
Oc3125
3c2b
2602
3c30
cde616
20c8
a113
2616
b629
adlc
25be
Oc310d
3d2b
2602
3a30
3a2b
cde616
20ae
Od3102
3f2b
1d31
cce04e

JSR
JSR
BCS
CMP
BNE
LDA
BSR
BCS
BRSET
INC
BNE
INC
JSR
BRA
CMP
BNE
LDA
BSR
BCS
BRSET
TST
BNE
OEC
DEC
JSR
BRA
BRCLR
CLR
BCLR
JMP

PRTOAT
GETBY2
MEMEXI
1/$11
MEMEX2
W2
STORE
MEMEX3
6.STAT.MEMEX4
AOORL
MEMEX5
AOORH
PRT ADR
MEMEX3
I/SI3
MEMEX4
W2
STORE
MEMEX3
6.STAT.MEMEX4
ADORL
CMOMB2
AODRH
ADORL
PRT AOR
MEMEX3
6.STAT.NORM2
ADORL
6.STAT
GETCMO

MEMEX I

CMDMOL

AORINC

MEMEX5
MEMEX2

AOROEC

CMDMB2

MEMEX4
NORM2

MEMORY

VAll D HEX
PRI NT IT
SHI FT IN NEXT
IF VALID TRY AGAI N
ENTER?
NO
RESTORE ACCA
YES STORE IT
STORE VAllO
YES GOTO
NEXT
PRI NT IT
REPEAT
M?
NO

YES THEN
GET PREVIOUS
AOORESS
PRI NT IT
REPEAT

em64k.as5
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023

'" ** ** ** * '* '" * **** ** **** '" '" ** ** ** ** ** ** ** ** **** **
LOAD/STORE AT AOORH(EH). ADORL

*********************************************
0000e562
0000e564
0000e566
0000e568
0000e56a
0000e56c
0000e56e
0000e56f

aec7
adOc
b72d
ad06
bl2d
2701
99
81

STORE

0000e570
0000e572
0000e574
0000e576
0000e578

aec6
bf29
aeBI
bf2c
043120

LOAD
LDSTCM

0000e57b
0000e57d
0000e57f
0000e5BI
0000e5B3

b72d
b630
b039
b72e
b62d

0000e5B5

1201

STRTS

RMCC

LOX
BSR
STA
BSR
CMP
BED
SEC
RTS

IISC7
LOSTCM
W4
LOAD
W4
STRTS

SET· UP
ROUT! NE
TO 00
TWO BYTE
STORE

LOX
STX
LOX
STX
BRSET

1/$C6
W2
//$81
W3
2 .STAT. NORM

SET ·UP ROUTINE
TO 00
TWO BYTE
LOAD
REAL ADDRESS

STA
LOA
SUB
STA
LOA

W4
ADDRH
OFF
W5
W4

BSET

1. PORTB

149

XFER A14 & A15 TO PORTS

1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
103B
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050

00O~587

OOOOe58a
000~58c
000~58e
000~591

0000e593
0000e595
0000e597
000~599

o.oOOe59b

Oe2e02
1301
1001
Oe2e02
1101
be2e
bf2a
le2a
1f2a
be29

AI5HI

A14HI

NORM

BRSH
BeLR
BSET
BRSH
BeLR
LOX
STX
BSET
BeLR
JMP

7.W5.AI5HI
l.PORTB
O.PORTB
6.W5.AI4HI
O.PORTB
W5
AOI1EH
6.AOOEH
7.AOOEH
W2

5
5
5
5
5
3
4
5
4
14

10
15
20
25
30
33
37
42
47
61

A15 HIGH
NO
YES
AI4 HIGH
NO
YES
AI4 HIGH
A15 LOW
67 (66 FOR LOA) WITH JSR

**************** •• ***.* ••• ******* •••• ********
Build a byte.

******** •• ***********************************
0000e59d
0000e59f
0000e5al
0000e5a3
0000e5a5
0000e5a7
0000e5a9
0000e5ab
0000e5ad
0000e5ae

b729
adOe
240b
3829
3829
3829
3829
ba29
99

GETBY2

81

GETBRT

STA
BSR
BeC
ASL
ASL
ASL
ASL
ORA
SEC
RTS

W2
GHNYB
GETBRT
W2
W2
W2
W2
W2

em64k .as5
1052
1053
1054
lOSS
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
107B
1079
1080
1081
1082
1083
1084

************************.**"'********.* •• *****
Get one character into ACCA
X destroyed. C set i f hex.

*****************************************.*.*
GOOOe5af
0000e5b2
0000e5b3
0000e5b5
0000e5b7
0000e5b8

ede4ed
98
alOf
2201
99
81

GETNY8

GETRET

JSR
CLC
CMP
BHI
SEC
RTS

CHRIN

GET CHARACTER

USOF
GETRET

VALID HEX?
NO
YES

************r.*.********* ••• ******************
Build address A.X dest .• add res 5
in ADDRL/AllDRH. C set if new.

**********************************************
0000e5b9
0000e5be
DODOeS be
0000e5eO
0000e5c2
0000e5c4
0000e5c6
0000e5e8
000Oe5ea
000Oe5ec
0000e5ee
0000e5dO

ede235
od58
adef
250a
a110

GETADR
8LDADR

272b
alII
2727
20eo
3f30
b7lb
ad44

GETAOI

JSR
BSR
BSR
BCS
CMP
BEO
CMP
8EQ
BRA
CLR
STA
8SR

CLRTAB
PRTADR
GETNYB
GETADI
1/$10
GETRTS
USlI
GETRTS
GETADR
AOORH
ADDRL
PRTADR

150

BLANK DISPLAY
GET CHARACTER
VALID HEX?

NO ENTER?
NO TRY AGAIN
INIT HIGH ADDRESS
PUT CHAR AWAY
PRI NT NEW ADDRESS

1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
11 00
1101
1102
1103
1104

0000e5d2
0000e5d4
0000e5d6
0000e5d7
0000e5d8
0000e5d9
0000e5da
0000e5de
0000e5dd
0000e5df
0000e5e 1
0000e5e2
0000e5e4
0000e5e6
0000e5e8
0000e5ea
0000e5ee
0000e5ee
0000e5fO
0000e5f!

addb
2412
48
48
48
48
ae04
48
392b
3930
5a
26f8
ad30
20.a
a110
2705
a111
26e2
99
81

GETALP 8SR
8CC
ASLA
ASLA
ASLA
ASLA
LDX
GETASF ASLA
ROL
ROL
DECX
BNE
BSR
8RA
GETARG CHP
BEQ
CHP
BNE
SEC
GETRTS RTS

GETNY8
GETARG

GET ANOTHER CHAR
VAll D?
YES
SHI FT IT IN

1/4
ADDRL
AODRH
GET ASF
PRTADR
GETALP
11$10
GETRTS
1/$11
GET AL P

PRINT NEW ADOR
GET ANOTHER CHAR
ESCAPE ?
ENTER?
NO TRY AGAI N
YES SET FLAG

em64k.as5
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
112B
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146

* ** ** ** It. ** *. * '*

*. *.

** .ltltlt 1t1t.1t ** .. * *It *It *It *. *** * * * * * * * *

Pri nt one byte (from A).

Pr; nt address ADDRH .AOORL.

•. **-_._-*-----------*-*-*----*---*-*-**-*-.-.---***
0000e5f2
0000e5f4
0000e5f6
0000e5f8
0000e5f9
0000e5fa
0000e5fb
0000e5fe
0000e5fd
0000e600
0000e602
0000e604
0000e606
0000e608
0000e609
0000e60e
0000e60e
0000e610
0000e613
0000e615

ae04
bf28
b72d
44
44
44
44
97
d6e4ed
be28
e720
b62d
a40f
97
d6e4ed
be28
e721

0000e616
0000e618
0000e61a
0000e61e
0000e61d
0000e6lf
0000e621
0000e623
0000e625
0000e627
0000e629

b72e
bf2e
b630
5f
addS
b62b
ae02
adef
b62e
be2e
81

PRTOAT
PRTBYT

cdelec
b62d
Bl
PRTAOR

LOX
STX
STA
LSRA
LSRA
LSRA
LSRA
TAX
LDA
LDX
STA
LDA
AND
TAX
LDA
LDX
STA
JSR
LDA
RTS

1/4
WI
W4

STA
STX
LDA
CLRX
BSR
LOA
LDX
BSR
LDA
LDX
RTS

W5
W3
ADDRH

PRI NT I N LAST TWO LCD DIGITS

CTABL.X
WI
DTABL.X
W4
IISOF
CTABL.X
WI
OTABL+1.X
OISTAB
W4

PRT8YT
ADORL
1/2
PRTBYT
W5
W3

151

PRINT AODRESS (FIRST 4 DIGITS)

1147
1148
1149
1150
1151
1152
1153
1154
1155 0000fff4
1156 0000fff6
1157 0000fff8
11580000fffa
1159 OOOOfffc
1160 OOOOfffe
1161

*.*.******.*"'**,,***********************.* ••• ********
MC68HC05EO Vectors.

*******.*.*.*.*************.*.**********************

e022
e022
e022
e04e
e022
e022

ORG

SFFF4

F08
FOB
FOB
FOB
F08
FOB
END

START
START
START
GETCMO
START
START

152

SERIAL
TIMER B
TIMER A
EXTERNAL INTERRUPT
SWI
RESET

AN442
Driving LeOs with M6805 Microprocessors
By Peter Topping
MCU Applications Group
Motorola Ltd, East Kilbride

INTRODUCTION

SINGLE-BACKPLANE DISPLAVS

M6805 microprocessors include a wide range of parts
with a large diversity of on-chip featu~es. Thesejnclude
NO and O/A convertors, serial interfaces, timers and
display drivers. The display drive capability of the
microprocessors range from none beyond I/O pins,
through high current ports, to specialised display drivers
for LCOs and vacuum fluorescent displays.

Single-backplane displays are commonly used where
the number of segments required is limited, usually
using the 7-segment format. They have the advantages over multiplexed displays of superior contrast
and viewing angle and a wider range of operating
voltage and temperature. They can be driven directly
by microprocessors with the number of segments
limited simply by the number of available pins which
are (or can be configured as) outputs. An output pin is
required for the backplane together with one for each
segment. The ports are loaded with the segment data
corresponding to the required display, as with any other
peripheral being directly driven by I/O lines. In this case,
however, the microprocessor must complement the
signals (backplane and frontplanes) at regular intervals,
thus satisfying the requirement that the display receives an AC waveform with only a small DC component. It is possible for interrupts to alter the timing
of these voltage reversals and the programmer must
ensure that the resultant DC component does not
exceed that above which the life of the display is
reduced.

The MC68HC05M series have vacuum fluorescent
drive capabilities up to 4OV. The MC68HC05L series
include LCD drivers with capabilities rang,ing from the
MC68HC05L6 (3 or 4 backplanes and 24frontplanes)
through the MC68HC05L7/9 with 8 or 16 backplanes
and 60/40 frontplanes. The L9's 40 frontplanes can be
expanded to 205 with three MC68HC68L9 expanders.
Microprocessors without special LCD circuitry can be
used to drive single backplane LCOs directly but
require regular software intervention if the requirement
that the display receives only AC drive is to be met.
Alternatively display driver chips can be used to
interface microprocessors with single and multiple
backplane displays.

An alternative method of driving single-backplane
displays ·from microprocessors is to use· an LCD
driver. Figure 1 shows a lHIigit 7-segment circuit
using 3 MCl44115P LCD drivers. These chips are
driven serially and constitute a simple shift register
giving the programmer full control over the display.

This application note gives hardware and software
examples for these different arrangements. The same
methods also apply to other families of
microprocessors, eg M680l and M68HCll. The
examples are arranged in the order of the number of
backplanes.

153

They can also be simply cascaded to drive a display of
any required size. Clearly. the number of chips and
interconnections increases directly as the number of
segments. This limits the practical size of a display
using this arrangement. The output pin to segment
connections can be chosen to suit the application. The
arrangement used here has been chosen to be
compatible with the 4-backplane MC145000 driver
used in a later example.

-

BP

t---

Cl

-

6-digit Static LCD

C2
abc-fged abc-tged BP " be· f g e dab c • f g e d

15 6, ,

9

,22 3 4

, 6., • •Ix

6 7 8 9 '0

Segment Output.
PA6 ~

68
(HC)
05
PA7
PB3

D'N

...2 BKP
Voo

,.

The MC144115 has a three-line serial interface
consisting of clock. data. and chip enable. The clock
and data lines can be shared with other peripherals.
provided that each peripheral has a separate enable
line. The enable line can. however. be derived from
the clock if no other chips share the clock and data.
This method of saving an I/O line is used in application
note ANE416. The MC144'115 software example
(listing 1) has been modified from the routine used in
ANE41f).

MC144115P

-EN
2

2)

5V

,[22

3

5

, , , , , Ix

7 B 9 0

Segment Outputs
DIN "

os C 23
Cl

Vss

"1

;L

14

D'N
, BKP
Voo

24,

MC144115P
EN

Cl

2

1

,22 3 •

.I.

1 • 9 '0

Segment Outputs

1':J."

D'N !2.l

o,e
Vss

", ;:L,

5V

f g ed

abc-tged abc

~N MC144115P
Voo

-EN
2

Cl

osc~
Vss
~ .011'1'

"/;:L,

5V.

23

Figure 1. Single-backplane LCD display with MC144115P display drivers

154

"
DIN~

0

LISTING 1
*** ••• * ••• **.******* •••• ******** •••••••••• *** ••••• **
4
5
7
8
9 00000000
10 00000001

Exampl e program for MC144115 driven
single backplane display.

.***********.*.*•••• ***.****.*.* ••• **********.* •••••
PORTA
PORT8

EQU
EOU

sao

ORG

S0050

SOl

PORT A AOORESS
B

11
12
13
14 00000050
15
16 00000056
17 00000057
18 00000058
19 00000059
20
21
22
23
24
25
26
27
28
29
30
31
32 00001000 .605
33 00001002 b758
34 00001004 be56
35 00001006 f6
36 00001007 bf59
37 00001009 97
38 0000100. d6103c
39 00OO100d beSS
40 0000100f e750
41 00001011 3.58
42 00001013 be59
43 00001015 5.
44 00001016 b357
45 00001018 26ec

TMP1
TMP2
TMP3
THP4

RMB

WORKING NUMBER

RMB
RHB
RMB
RHB

POSITION OF LSB
POSITION OF MSB

ORG

S1000

.**.**•••• ** •••••••••••••••••••• ********* •• ** ••••• **
First part of the display subroutine
gets the segment codes correspondi ng to
the BCD data for di spl ay.

OISP

03

LOA
STA
LOX
LOA
STX
TAX
LOA
LOX
STA
DEC
LOX
OECX
CPX
BNE

I/S05
THP3
THP1
a .X
TMP4

LSB

STABL .X
TMP3
R.X
TMP3
THP4

FI NO 7 SEGMENT CODE

TMP2
03

FI NI SHED

155

PUT IN DISPLAY TABLE

60
61
62
63
64
65
66
67
68 0000101a
69
70 0000101e
71 0000101e
72 00001020
73 00001022
74 00001024
75 00001026
76 00001027
77 00001029
78 0000102b
79 0000102d
80 0000102f
81 00001031
82 00001032
83 00001034
84 00001036
85 00001037
86
87 00001039
88 0000103b
89
90
91
92
93
94
95
96 0000103c
97 0000103d
9B 0000103e
99 0000103f
10000001040
101 00001041
102 00001042
103 00001043
104 00001044
105 00001045

•• **** •• ** ••••••••••••••••••••• *******.** •••• *** •• **
The second part of the display routine
sends the 48 bits required by the
display driver.

.... "' ........... * .......... * * •• *. ** ••• *.* •••••••• *. * •••• *.
1701

oun

ae05
e650
bf58
IdOO
ae08
44
2402
leOO
leOO
1 fOO
1dOO
Sa
26f2
be58
5a
2ae5

DI SCHR LDA
01 SPL Y STX
BCLR
LOX
OISI
LSRA
BCC
BSET
0lS2
BSET
BCLR
BCLR
OECX
BNE
LOX
OECX
BPL

1601
81

BSET
RTS

8CLR

3.PORT8

ENABLE LOW

LOX

US
R.X
TMP3
6.PORTA
UB

SEND DISPLAY TABLE TO 144115

0lS2
6.PORTA
7.PORTA
7.PORTA
6.PORTA
OISI
TMP3

SAVE INDEX
CLEAR DATA
SET UP
BIT or
ACCUMULATOR
CLOCK
IT
CLEAR DATA
COMPLETE ?
NO
RESTORE INDEX

OISCHR
3.PORTB

ENABLE HIGH

.... *"' ... ** ...... *. * •••• * •• * ..... * * ....... * .... * * •• *.* ** * ...
LCD segment tab Ie.

eb
60
c7
e5
6c
ad
af
eO
ef
ed

STABL

FCB
FCB
FCB
FCB
FCB
FeB
FeB
FeB
FCB
FCB

SEB

SEGMENT

S60
SC7

CODES

SE5
S6C
SAD
SAF

4
5
6

SEO
SEF
SED

7

156

8

FOR THE
MCI450001144115
LCD DRIVER

THREE-BACKPLANE OISPLAVS
The table which translates the required character into
segments contains 2 bytes per character, the middle
nibble of the 3 required being repeated. This simplifies
the code required to write to the display RAM by using
one nibble if the character is intended for an even
position in the display and the otherfor an odd position.
Figure 3 shows the L6 - LCD segment arrangement
used in this example.

The MC68HC05L6 can drive 24 frontplanes and either
3 or 4 backplanes, the number of backplanes being
selectable in software. The data to be displayed is
arranged in the display RAM as shown in figure 2.
Note that data sheet for the MC68HC05L6 (A011254)
shows this relationship wrongly.
It can be seen that each frontplane occupies a nibble
in the 12-byte RAM. There is thus a simple relationship
between RAM location and displayed digit on a
4-backplane 7-segment display (each 2 frontplane
digit corresponds to one byte). With a 3-backplane
display, however, each digit corresponds to 3 nibbles
(1.5 bytes) so the software required to translate the
required segments into display RAM data is more
complex. Listing 2 shows a suggested method of
doing this.

LCD data
latch 00
($00)

7

5

6

Bp1

4

3

2

Bp2 Bp3 Bp4 Bpl

When using a microprocessor without an LCD drive
capability a separate display driver can be used to drive
a multiplexed display. The example shown in figure 4
and listing 3 uses the ICM7231 B 3-backplane driver.
The ICM7231 B requires each character to be addressed
through pins AO, Aland A2 and the appropriate data
written to pins 00,01,02 and 03. This parallel control
uses more I/O lines than the serial arrangement
employed in MC145000/1 and MCl44115 drivers.
The fact that data is accepted in HEX and encoded into
segments by the driver simplifies the software but
reduces the versiltility of the display as only the
driver's 16 characters are available., The ICM7231 B
driver displays 0-9,-, E, H, L, P and'blank while the
ICM7231A displays 0-9, A, B, C, 0, E and F.

0

1

Bp2 Bp3 Bp4

Fp 01

Fp 02

As with any multiplexed LCD drive, the contrast is
dependent on the supply voltage to the driver's
multiplexer circuitry. In the case ,of the ICM7231,
contrast can be adjusted using the potentiometer on
pin 2 (figure 4).

Figure 2. MC68HC05L6 back/frontplane
pin to LCD data latch bit relationship

I

I

I

I

I

C3

8-digit Triplexed LCD
x

y

1

2

3

58 57 58
1

FP 24 23 22

'-r--

Voo

I~

VLL

10 k

32

r--

4

S

6

5554 53
21 20 19

I

I

1

Z

7

8

9

52 51 50
18 17 16

10 11

12

13 14

I

I

is

16 17 18

48 4S 44

4948 47
15 14 13

12 11

C2 -

10

Cl f--19 20 21

43 42 41
9

8

7

S

4

MC68HC05L6FN

vss

n.m
Figure 3. MC68HC05L6 with a 3-backplane LCD

157

37 36 35

40 39 38
6

N.C,

22 23 24

3

2

1

61

62

BPI

2

J59
3

4

LISTING 2
.**************** ••• **************** • ., •• ************
Examp Ie pr09ram us i ng the MC68HC05L6
to directly drive a 3-backplane display.

10 00000009
II 00000008
12
13
14
15
16 00000050
17 00000058
18 00000059
19
20
21
22
23
24
25
26
27
28
29 00000100
30 00000102
31 COOool04
32 00000 I 06
33 OOOOOIOB
34 OOOOOIOa
35 OOOOOIOe
36 00000 I De
3700000110
38 000001]2
39 00000114
40 00000116
4] 000C0118
42 00000 II a
43 OCOoOll c
44 ODGC~lle

LAOO
LOAT

a
WI
W2

EaU
EaU

SOO09
SOO08

ORG

S0050

RMB
RM8
RM8

ORG

LCD ADDRESS REGISTER
LCD DATA REGISTER

01 SPLAY REGI STER

SOlDO

* **.* ****.* ** *. ** ** ••• * ** ** ** * * ** **** ** ** * * **** **** *
LCD segment look-up table.

... ** ** ... * ** ** ... * **.* *_ •• "'II * * * * **.* * * •• * •• 'fIr .*.*** ** •••• *
acca
OOcO
e4Be
eOce
4Bc4
eB4e
ee4e
80c8

ecce
e8ce
4004
ecoc
4cc4

2c02

cc8c
OOCO

L6TA8

FeB
FeB
FCB
FeB
FeB
FeB
FCB
FeB
FeB
FeB
FeB
FeB
FCB
FeB
FCB
FCB

SAC. seA
SOD. SCO
SE4. S8E
SE~. seE
S48. se4
SE8.S4E
SEC.S4E
S80. seB
SEC. SCE
SE8.seE
S40. S04
SEC.SOE
S4C • SC4
S2e. S02
SCC. S8e
SOD. SOD

4
5
6
7
8
9
(A: ee CC l
(8: 6C 46 l
(C: AC OAl
( D: 64 C6 l
(E: EC DE l
(F: CC DC>

158

60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
B3
B4
B5
B6
B7
BB
B9
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111

*** ** .. * ** ** **.* '* * **** * * **** * * ** ** * * ** ** ** * * ** ** '* * ** ** * * * * * * ** **
Main loop for L6 directly driven LCD.

a

This subroutine assumes that
contains
HEX data for display. As each character

requires lObytes (9 bits contained in
3 nibbles with 1 bit (backplane) in
each nibble not used) each execution
of the loop handles 2 characters.

*******************************************************.*_.**.*
00000120
00000122
00000124
00000126
00000128
0000012a
0000012c
0000012d
0000012e
00000131
00000133
00000135
0000013B
00000139
0000013a
0000013b
0000013c
0000013e
00000140
00000142
00000144
00000146
00000147
0000014B
0000014b
0000014c
0000014d
0000014e
0000014f
00000151
00000153
00000155
00000158
0000015a
0000015c
000001Se
00000160
00000162
00000164

3f59
a680
b709
be59
e650
a40f
48
97
d60 100
b708
3c09
d60101
44
44
44
44
b75B
3c59
be59
e650
a40f
48
97
d60100
4B
48
4B
4~

bb5B
b70B
3c09
d60101
b70B
3c09
3c59
b609
alOe

26c2
Bl

START

L60P

CLR
LDA
STA
LDX
LDA
AND
LSLA
TAX
LDA
STA
INC
LDA
LSRA
LSRA
LSRA
LSRA
STA
INC
LDX
LDA
AND
LSLA
TAX
LDA
LSLA
LSLA
LSLA
LSLA
ADD
STA
INC
LDA
STA
INC
INC
LDA
CMP
BNE
RTS

W2

Initialise digit pointer.

11580
LADD

First write to S09: Bus/l.CD ratio - 256.
4-backplane. fast charge enabled.

W2

a. X

Get HEX data.

Only lower nibble ;s relevant.

IlsOF

x 2 (two bytes per digit in table).
L6TA8.X
LDAT
LADD
L6TAB+1.X

Get firs t byte f rom segment table.
Send it to LCD data latch.
Keep LCD on. move to next latch.
Get second byte of segment data.
From this byte only the

upper nibble ;s relevant. lower
nibble is lost as upper nibble
;s shifted down.
Save nibble. to be combined with first

WI
W2
W2

a.X

nibble of next digit.
Address of next digit in
Get HEX data.

IlsDF

only lower nibble ;s relevant.

a.

x 2 (two bytes per digit in table).
Get first byte from segment table.
From thi s byte anI y the

L6TAB.X

lower nibble is relevant. upper
nibble is lost as lower nibble
is shifted up.
Combine nibble with last nibble

WI
LDAT
LADD
L6TAB+l.X
LDAT
LADD

W2

of previous digit and send byte to LCD.
Next LCD data 1 atch.
Get second byte from segment tabl e.
and send it to LCD.
Next 1 atch (three per loop).
Next digit (two per loop).

LADD

Finished?
If not. do next two di gits.

1112
L60P

159

I

I

I

I

I

'r1

C3

8-digit Triplexed LCD
x v
1

5V

Il~V+

10

2

I

Z
3

4

I
789

6

2625 24

2929 'r1
X

5

V Z

X

V Z

23 22 21
X

V Z

?GND

otv~

471<

10 11

I

I

I

12

13 14 15

16 17 18

20 19 18
X

V Z

17 18 15
X

V Z

V Z

V Z

Cl

-

25

876

11 10 9
X

-

22 23 24

19 20 21

14 13 12
X

26

C2

V Z

X

3
Cl

4

5

C2 C3

ICM7231B
cs
1

1{2

Al

138

11lF
P03

AD

AN

39

P02

POI

\30

37

1

PDQ

PCS

MC68(HC)05

Figure 4. 3-backplane LCD driven by an ICM7321

160

DP

31

PC4

03
35

PC3

02

\34
PC2

01

DO

33

32

1
PCl

PCO

LISTING 3
****************************************************

I
2
3
4
5
6
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41

Example program using the I.CM7231
driver and a 3-backplane dlsplay_

********* •• **********.*****.***************.*.******
OOOOOOOt
00000002

PORTO
PORTC

00000050

0

EOU
EOU

SOOOI
SOO02

ORG

S0050

RM8

8

ORG

SOIOO

PORT 'B DATA
PORT C DATA

01 SPLAY REG I STER

*******.*.*****************************************.
Display contents of O.

******.*********************.*.*************** ••••••
00000100
00000102
00000104

b601
a4fO
b701

DI5P

00000106

ae08

00000108
OOOOOIOa
00000 lac
OOOaOIOe
00000110
00000111
00000113
00000115

e64f
b702
1701
1601
5a
2704
3cOI
20n

AGAIN

00000117
0000QI19

3f02
81

OUT

LOA
AND
STA

PORTD
IUFO
PORTO

LOX

118

LOA
5T"
BCLR
BSH
OECX
8EO
INC
BRA

0-1. X
PORTC
3.PORTD
3.PORTO

CLR
RTS

PORTC

OUT
PORTO
AGAIN

161

CLEAR
LS NIBBLE OF PORTO
IE DIGIT ADDRESS - 0

LATCH
OIGIT
DONE?
NO. GOTO NEXT DIGIT

FOUR-BACKPLANE DISPLAYS
As mentioned above, the MC68HC05L6 can drive
a 4-backplane display with up to 24 frontplanes
directly. The resultant 96 pixels could be used to drive
2 digits of an 5x8 dot matrix display, but with this
number of segments most applications will use
7-segment or customised displays. A 7-segment
display of up to 12 digits can be used. The software
required is similar to, and simpler than, that shown for
the L6 with a 3-backplane display. When it is required
to drive a 4-backplane display using a microprocessor
without an LCD drive capability, the MC145000 offers
aversatile solution. Up to 6 digits (12 frontplanes) can
be driven directly and more can be driven by the
addition of one or more of the 18-pin MC145001
expanders, each adding 11 frontplanes. The example
shown in figure 5 and listing 4 drives 6 digits, the
software being very similar to that shown' for the
MC144115 single-backplane driver. This is the result
of both chips having the same shift-register/latch
architecture despite the actual output signals being
quite different. The listing also shows a routine using
an SCI rather than port lines,
A difference between the MC145000 and the
MCl44115 is that the MC145000 has no chip-enable
input. It can share its data line with other peripherals
but must have a dedicated clock so that the controller
can supply data independently of other chips.
For applications requiring more than the 12 frontplanes
made available by the MC145000, the MC145003/4
may be appropriate. They provide 32 frontplanes for
use with a 4-backplane display, allowing up to 128

segments. The MC145003and MC145004are identical
except for their serial protocol. The MC145004 has an
IIC bus interface incorporating the usual acknowledge
procedure associated with the IIC standard. The
MC145003 is the same, except that there is no
acknowledge and hence no associated clock cycle.
The incoming data is automatically latched after
128 bits have been received. If, however, it is required
that the data be latched at other times, an enable pin
is available.
For applications where Vdd and Vlcd are connected
together, the LCD contrast is adjusted by adjusting
Vdd. If the data is coming from a chip with a higher
supply voltage, the input pins may go higher than the
supply voltage of the MC145003/4. This is allowed for
the clock and data pins, but not recommended for the
enable pin as its input protection circuitry may clamp
the input voltage. It is therefore not advisable to use
the enable pin if the MC145003/4 has a differentVdd
from the chip supplying it with data. In applications not
using this pin it can be left floating or tied high.
The example shown in figure 6 does not use the
enable pin; the example software sends all 128 bits
every time it is executed. The latching is thus performed
automatically. The circuit shows 2 6-digit displays,
each with 12 frontplanes. Any display or combination
of displays with up to 32 frontplanes. can be used with
the software shown in listing 6, as all 128 bits are
always sent. The 6 lines of code (45-50) are
commented out for use with the MC145003; they are
required for the MC145004.

162

1

120gS

22

~

0

~

4

PA7

r--U!- Clock

2

7

9 13 12 16 15 20 19

6 10

13 11 10 9 8 7 6 5 4 3 2 1
FP12 11 10 9 8 7 6 5 4 3 2 1

14 15 16 17
BP43

3

1

MC145000

MC68(HCIOS

PA6 ~ Data
22l

....-----!-

23J

12

5V~
10::
50k

22m<

21-u1

10iJF

Figure 5. MC145000 driving a 4-backplane LCD

44
23

4-backplane LCD

~

,!3

48 47 46 45
2 3 4

I BP1

~
~

4

6

7

9

4-backplane LCD

r---E

r----l

10 12 13 15 16 19 20

3

36 35 34 33 32 31 30 29 28 27 25 24
FP1 2 3 4 5 6 7 8 9 10 11 12

4

6

7

9

N.C.

10 12 13 15 16 19 20

23 22 19 18 17 16 15 13 12 11 10 9
13 14 15 16 17 18 19 20 21 22 23 24

8-1
25-32

I
I

I

MC145003/4
Data

39

Clock
38

VLce Voe Vss
20 491 21

10J1F~
PA7

PA6

MC68CHC)05

AO
44
.J>-

~Ok

'"

A1
43

A2
42

EN FS
41

37

5V

eSC2
501
470K

N.C. N.C. N.C. N.C. N.C.

Figure 6. MC145003/4 driving 4-backplane LCOs

163

eSC1
511

LISTING 4
* ...... **.*.* ** ** *** .. ** ........ *. ** **

** ** ** **"* .. ** ..

Exampl e program for MC145000 drl ven
four-backplane dispiay_

4
5
7
8
9
10
II
12
13
14
IS
16
17
18
19
20
2I
22
23
24
25
26
27
28

*. * .. ** * ..

••••• * ••••• **.**** ••••••• ** •• ****.**** •• ******* •••••
PORTA
BAUD
SCRI
SCR2
SCSR
SDAT

00000000
OOODOOOd
OOOOOOOe
OOOOOOOf
00000010
00000011

00000050
W2
W3
W4
W5
W6

000000?6
00000057
OOOOOOSB
00000059
0000005a

PORT A DATA
SC I BAUD RATE REGISTER
CONTROL REG. No. 1
2
STATUS
DATA

[aU
EaU
EOU
EaU
EaU
EaU

SOD
SOD
SOE
SOF
SIO
SII

ORG

SOOSO

-

RMB

WORKING NUMBER

RMB
RMB
RMB
RMB
RMB

POSITION OF lSB

ORG

POSIJION OF MSB

SIOOO

.. *. -* ** ........ ** .... * •• * ........ ** * ... * *. ** _•• * ** ** ......... * .. * ** ..

29
30
31
32
33
34

First part of
repl aces BCD

the display subrout; ne
with 5 egment codes.

**********.********.************ •••• **********.***.*

35
36
37
38
39
4C
41
42
43
44
45
46
47
48
49

00001000
00001002
00001004
00001006
00001007
00001009
0000100a
OOOOIOOd
OOOOIOOf
00001011
00001013
00001015
00001016
0000101B

a60S
b758
be56
f6
bf59
97
d61 04 7
be5B
e7S0
3aS8
be59
Sa.
b35a
26ec

DI SP

03

LOA
STA
LOX
LOA
STX
TAX
LDA
LOX
STA
DEC
lOX
DECX
CPX
BNE

#S05
W4
W2
O. X
W5

LSB

STABl.X
W4
R.X
W4
W5

FI NO 7 SEGMENT CODE
PUT IN DISPLAY TABLE

FINISHED

W6
03

164

60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91

................................ .....................
.,.

The second part of the display routine
sends the 48 bits required by the
display driver.
For comparison two
routines are included. one using port A
1 ;nes and a second using the SCI.

•••• * •• * ••••• * * * •••• * ** •• * *.* *. ***. * * .***.*.* *. * .* ••
OOOOIOla
OOOOIOlc
OOOOIOle
00001020
00001022
00001024
00001025
00001027
00001029
0000102b
0000102d
0000102f
00001030
00001032
00001034
00001035

ae05
e650
bf57
I dOO
ae08
44
2402
lcOO
leOO
1 fOO
ldOO
Sa
26f2
be57
Sa
2ae5

oun

LOX
DISCHR LOA
DISPLY STX
BC LR
LOX
DISI
LSRA
BCC
BSET
BSET
01 S2
BC LR
BCLR
DECX
BNE
LOX
DECX
BPL

115
R.X
W3
6.P'ORTA
118
DIS2
6. PORTA
7.PORTA
7.PORTA
6.PDRTA
DISI
W3

SEND DISPLAY TABLE TO 1441151145000
SAVE INDEX
CLEAR DATA
SET UP
BIT OF
ACCUMU LA TOR
CLOCK
IT
CLEAR DATA
COMPLETE ?
NO
RESTORE INDEX

DISCHR

* ** ** ** *. **** ** •• ** * * *. *. "" ••• * * *. ** ** **.*.* * *"" * ** ***
SCI LCD driver interface.

92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
1 il

00001037
00001039
0000103b
0000103e
00001040
00001041
00001043
00001046

ae05
e650
Of! Ofd
b711
Sa
2af6
OdlOfd
BI

00001047
00001048
00001049
0000104a
0000104b
0000104c
0000104d
0000104e
0000104f
00001050

eb
60
c7
e5
6c
ad
af
eO
ef
ed

MORE

STABL

LOX
LOA
BRCLR
STA
DECX
BPL
BRCLR
RTS

115
R.X
7.SCSR.*
SDAT

INITIALISE X
FETCH DIGIT
WAIT UNTIL TORE - I
WRITE IT TO SCI TX REG.
NEXT DIGIT
MORE
DONE
6.SCSR.* WAIT UNTIL TC~1

FC8
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FC8

SEB

SEGMENT

S60
$C7

CODES

SE5
S6C
SAD
SAF

SEO
SEF
SED

165

FOR TH E
Me 145000 fMCI44115
LCD DRIVER

LISTING 5
•••••••• **.****.*** ••••••••••• ***.** •••••••• **** •••••••

_*-

Exampl e program us Ing MCI45003/4 LCD Dri vers •

•• *.* ••••••••••••••• "" •••••••••••••••••••••••••••••••••••••
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

IlCP
IICDD
SCL
SDA
DIN
OOUT

00000002
00000006
ocrOOOO06
00000007
00000040
OOOOOOeO

WI
DPNT
ADDR
IlC

00000050
00000051
00000052
00000053

$02

EOU
EOU
EOU
EOU
EOU
EOU

S06
S06
S07
S40
SCO

ORG

S0050

RMB
RMB
RMB
RMB

16

ORG

SOBOO

LOA
STA
LOA
STA
LOX
STX
BCLR
BCLR

liSlE

PORTC
PORTCD
IlC - clock lIne
IIC - data line
INPUT DATA
OUTPUT OATA

IIC WRITE POINTER
IIC ADDRESS
IIC BUFFER (l2B BITS)

22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

OOOOObOO
00000b02
00000b04
00000b06
OOOOObOB
OOOOObOa
OOOOObOe
OOOOObOe

a67e
b752
a611
b750
ae52
bf51
!f02
Id02

START

OOOOOblO
OOOOOb12
000110b13
ODOOOb15
00000b16
00000bl8
OOOOObla
OOOOOblc
OOOOOble
000OOb20
00000b21

be51
f6
ae08
49
2402
le02
le02
Id02
!f02
Sa
26f2

SLOOP

00000b23
00000b25
OOOOOb27

3c51
3a50
26e7

00000b29
00000b2b
00000b2d

I cO2
le02
81

SEN02

SLOP

DlERO

12CEND

LOX
LOA
LOX
ROLA
BCC
BSET
BSET
BCLR
BCLR
OECX
BNE

ADDR
/117
WI
/lADDR
DPNT
SOA. IlCP
SCL.IICP

START CONDITION
DATA GOES LOW WHILE CLOCK HIGH

1/8

DATA BUFFER POINTER
GET A BYTE
B BITS TO SHIFT

DlERO
SDA.IICP
SCL.IICP
SCL.IICP
SOA.IICP

BIT = 0 ?
NO. BIT - 1
CLOCK HIGH
CLOCK LOW
DATA LOW

DPNT

o.X

SLOP

LOA
STA
8SET
8CLR
LOA
STA
INC
DEC
8NE

IIDIN
IICDD
SCL.IICP
SCL.IICP
IIDOUT
IICDD
DPNT
WI
SLOOP

BSET
BSET
RTS

SCL.IICP
SDA.IICP

166

DATA LINE AN INPUT
CLOCK
ACKNOWL EDGE BIT
8ACK TO AN OUTPUT
NEXT BYTE
LAST BYTE
STOP CONDITION
DATA GOES HIGH WHILE CLOCK HIGH

8/16-B,,-CKPLANE DISPLAYS
For dot-matrix displays, 8 or 16 backplanes are
common. This is the result of the large number of
pixels required. A compromise between pin-count
and contrast is made to decide the number of
backplanes. The minimum pin requirementfor a display
with N segments would require the number of
backplanes to be the square root of N, but with typical
requirements of many hundred or thousands of pixels
this is not practical as the resultant contrast would not
be acceptable. Typical compromises are 8 or 16
backplanes, as this gives acceptable contrast and fits
in conveniently with the 8x5 dot-matrix format
commonly used for this type of display.
The MC68HC05L7 and L9 are designed to directly
drive this type of display. The Li has 16 backplanes
and 60 frontplanes allowing it to drive up to 960 pixels
or 24 8x5 dot matrix digits (12 with x 8 multiplexing).
The L9 has only 40 frontplanes (16 8x5 digits) but is

capable of being used with MC68HC68L9 LCD drive
expanders. Each MC68HC68L9, up to 3 of which may
be added, contributes 55 frontplanes. An L9 and 3
expanders has thus 205 frontplanes allowing then to
drive up to 3280 pixels or 82 8x5 dot matrix digits.
The display RAM contains a 5-bit word for each row of
dots in the 8x5 format; thus, 8 locations are used for
each digit, allowing easy addressing. The RAM
corresponding to the digits driven by expanders is
contained in the expanders, but appears in the L9's
memory map as the data and address buses from the
L9 to external memory are also used by the
MC68HC68L9s.
Application note ANHK10/D shows an application
using the L9 and also describes a method of extending
the display size beyond that normally available using
this device.

APPLICATION NOTES
The following application notes give complete applications using the type(s) of display indicated.
ANE404 An extended MC146805E2 CBUG05
system using the MC68HC25.

ANE425 Use of the MC68HC68T1 RTC with
M6805 Microprocessors.

MC14500().fdriven 4-backplane, 6-digit
and ICM7231 B-driven 3-backplane, 8-digit
display.
ANE416 MC68HC05B4 Radio Synthesizer.

ICM7231 B-driven 3-backplane, 8-digit
display.
ANHK10 The summary of the MC68HC05L9 Micro.
App. Demo. Board.

MC14500D-driven 4-backplane, 6-digit and
MCl44115-driven 1-backplane, 6-digit
display.

MC68HC05L9/MC68HC68L9-driven dot
matrix display.

167

DRIVER CHIPS
The following list shows some·LCD driver devices. They are most suitable for 7-segrnent, 16-segment and
custom displays. The 7SD column shows how many 7-s~nt digits each device can drive. With the possible
exceptions of the MC145000/1 and the MC145003/4, they are not generally suitable for dot-matrix displays which
have 35-40 segments per digit.

Device

Back

Front

7SD

Drive

Expan.

Pins

MC14543

7

parallel

parallel

16

BCD

MC14544

7

parallel

parallel

18

ripple blank

MC144115

16

2

3-line

yes

24

MCl44117

2

16

4

3-line

no

24

MC145000

4

12

6

2-line

MC145001

24

MC145001

(4)

11

5.5

2-line

n/a

18

expander

MC145003

4

32

16

2- or 3-1ine

parallel

52

2- or 3-line

MC145004

4

32

16

2-line

parallel

52

IIC

33

4

2-line

parallel

40

also44-pin

24

8

parallel

no

40

BCD

MC145453
ICM7231

3

168

AN446

MCM2814 Gang-programmer
using an MC68HC805B6
By Peter Topping
MCU Applications Group
Motorola Ltd. East Kilbride

INTRODUCTION

PRINCIPLE OF OPERATION

Non-volatile memories of the type MCM2814 are
widely used in consumer equipment to store semipermanent. user-definable information. One of the
most common applications is TVs. In a TV the NVM is
used to store the channel number or frequency
associated with each' program number and may also
store other information about the program (for example.
fine-tuning and transmission standard). The NVM will
also contain the optimum settings for the sound and
picture analogue values. In some sets other data may
be stored. for example. user-defined names for some
or all of the available channels. In a production
environment the initial loading ofthis type of information
can be done quickly by copying an existing NVM. This
application note describes a programmer. shown in
Figure 1. which can perform this function. In four
seconds it can fully program 8 MCM2814s in parallel
and verify them individually. The programmer is
controlled by an MC68HC805B6 microprocessor.

The programmer has been designed with an emphasis on
ease of use and consequel)tly has as few controls as
possible. The only control which is used regularly is the
"RUN" button Sl. When it is pressed. the NVMs are
powered-up and programmer operation starts. When it is
released. power is disconnected from the NVMs but
remains on within the programmer so that the LED
indicators remain.

The B6 is ideally suited to this application as it has a
256 byte NVEEPROM. the same size as the MCM2814.
The contents of a master MCM2814 can thus be
loaded into the 86 and will remain there until a change
of data is required. Both the B6 and the MCM2814
have a byte in which some bits I;lre dedicated to data
protection so. in fact. only 255 bytes are used.

Three different-operations are available.
The first requirement is to load data into the programmer.
This procedure is selected by pressing and holding button
S3. and started by pressing. and holding. the button Sl.
The contents of a master NVM in socket #0 will be loaded
into t~e programmer; this takes about 12 seconds. The
MC68HC805B6 in the programmer retains this data in its
non-volatile EEPROM. DUfing loading both LEDs at socket
#0 are on and the rest are off. Once the B6's EEPROM is
written it is verified against the NVM in socket #0. a green
LED indicating a pass and a red LED a fail. Sockets 1-7
should be empty during this procedure but if they contain
an NVM they will also be checked. An attempt to perform
this routine without an NVM in socket #0 will not destroy
the data in lhe programmer as the software checks for an
IIC acknowledge before overwriting the contents of the
EEPROM within the MCM68HC05B6. If S3 is pressed.
the position of the slide switch S2 (program and verify or
verify only) is not relevant. As S1 supplies power to the
NVM sockets. it is important that it is held until the
procedure is complete. Reliable resultS will not be obtained
if Sl is released before the verification has finished.

169

---"

+fN

Gnd

CD

f5W

:-"

3:
0
3:
N
0

....
.,..

CO

M

0

.,-

C

r-~csll
'4 M

~

t---~

CSI
M

~
4 C~
~D~

GI1!en ~,

n~

n.

'"i-

-

J;
0111f

-

~

-

s---

C
DB

'-~ cso-+:-

t---~ CSI
~M 5
~-

-;;--

2

5

~ CSI

2

----:- M
4

C -:-D 5

..---4 CSI
.....;. M

J;

~-

6

-;;-C!.D~

'----

O.I~F

2

r-I----r CSI

5

l~B
~ CSO
+ -

-

-;;-C!.D~

f)

Ik

j~

Lr;-:-e

L~~

l~~

r-

'4
5
'"i~8
'-~ CSO
+ - r-

3300

47~f~ Ol~f±

4k7,2

L-;-:-~
2

J,

.

330

~~ CSI

::n
co
c

.....
.....,

:'"+1"

1

Is

3

r-:- M
4

C

1500

r.:-5

tt~18
+

'-f-;;- CSO
2 CSI
~M

L...

J;

~-

O.I~f

r.:-

7

Red

C ~t-

D~

~

'----

n

G')
I»

::I
CO

,;

a

co
iil

3
3
CD

.

34 35 39
B5 84 SO

~

121111 91 41 3 $r
D2 D3 D4 00 07

39

32 33
8786

81

zzI

23 501 7 ,J,.
TCI TC2 RD VRl

37
82

36
83

5
05

lOOk

RESET~

VDD

8
VRH
19 _
>-- IRD
15

MC68HC80586

~

>-- VpPl

Green

AO AI A2 A3 A4 AS A6 A7
31 30 29 28 27 26 25 24

.

.~ .~ .~ .~
~ .~
~ ~ ~~2 ~~3 ~: ~: ~~ ~ ~

)
..

[ I

..

CO
49

Red

4700.16

DO
14

Cl C2 C3 C4 CS C6 C7
48 47 46 45 44 43 42

.:

~ .~
~
:

.

4

)

)
.... L

.. _

--

-

OSC2

=

--~

1;1

r---

1sz

~I

PNV.

IOkJ.

lot

---------------

10k
+
lO~f

~

4M7

131

.~ .~ . ~r~~ ~~ ~~ ~t
~: :~
3

00

DI ascI

V"
41

~

0

4MHz

T~33pF,22T

....
10k

0111fT

~~

The main programming sequence is selected by putting
52 in position PN (program and verify). The NVMs
should be placed in the sockets and button 51 pressed.
and held. until programming and verification are
complete (4 seconds). During programming. both red
and green LEOs are. on. The procedure clears the
write-protect bytes and programs the NVMs in parallel
using the data stored within the B6 in the programmer.
It then verifies the NVMs individually. the results
being shown on the LEOs (green for pass. red for fail
and neither for no acknowledge).
Running only the verify routine can be selected by
placing 52 in position "V". The procedure is otherwise
similar to programming. 51 should be held in until
verification is finished (up to 1 second depending on
results).

CIRCUIT
The NVMs are arranged in a matrix using their IIC
chip-selects (pins 1 and 2). These pins configure the
two least significant bits (1 and 2) of the recognised
IIC address. Bit 0 determines if the device is
receiving or transmitting. The software uses only the
address 101 OOOOx and so an NVM will only be
addressed if both its chip-select pins are low. The
matrix thus allows each NVM to be addressed
individually by I/O lines using common software. 5ix
port B I/O lines ((H») are used for this purpose.
The NVMs (and the IIC pullups) are only powered up
when 51 is closed. allowing them to be inserted and
removed when they are powered down. When 51 is
pressed. 5 volts is also applied lo the RC circuit
connected to the base of the BC107 NPN transistor.
This supplies a base current to the transistor while the
10j1F capacitor is charging. During this transient the
transistor is on and the MC68HC05B6 is in reset. The
program starts when the capacitor is charged and the
transistor switches off. The MC34064 also connected
to the reset pin ensures that the microprocessor is
held in reset if the supply is below 4. 75V. This will be
the case during power-up and power-down. This is
advisable in any system with EEPROM in order to
prevent the possibility of it being corrupted during the
rise or fall of Vdd.

171

The 33 ohm resistor in series with the supply to the
NVMs limits the current if a device is plugged in the
wrong way round. If this happens. the BC327 PNP
transistor is turned on and the RED fault LED lit. The
actual voltage on the VOO pins of the NVMs is
monitored by bit 5 on port O. Thus the microprocessor
can tell if there is a short or a device inserted the wrong
way round. If this is the case the software aborts any
attempt to program or verify NVMs.
Ports A and C are used for the pass and fail LEOs
respectively. while the input-only port 0 has two pins
used to read the positions of 52 and 53.

SOFTWARE
On reset, the program initialises the ports.IIC
addresses and the RAM location (5TAT) which is used
for status flags. The state of bit 0 on port 0 is then
checked. This will be low unless the button (53).
which selects the loading of data into the programmer.
is pressed. If it is low. either program and verify or
verify only is executed according to the level of bit 1 on
port 0 which is connected to switch 52.
The programming routine (PROG) switches on all the
LEOs. enables all the NVMs and clears their writeprotect by writing $00 to address $FF. A loop which
reads a byte from the B6 within the programmer and
writes ·it to the NVMs is then performed 255 times.
Writing to the NVMs is carried out without checking
for an acknowledge. so the full procedure will take
place even if all the NVM sockets are empty. This is
the only routine which does not check for an
acknowledge.
Only 255 bytes are transferred. as the last byte in the
MCM2814 is reserved for the write-protect status.
The B6 also has a reserved byte. but it is the first byte.
so the correspondence of the addresses between the
B6 and the NVMs is offset by one.
The verify routine (VERF) switches off all the LEOs and
compares the data in the B6 with the data in each of
the NVMs. It immediately fails a socket which does
not return an IIC acknowledge. The RAM location
COUNT contains the number of the socket being
checked and is used to switch on the appropriate LED
once each verify is complete.

The NVM sockets are arranged in a 2 x 4 matrix using
their two IIC chip selects. The IIC address used is
always $Al ($AO for writing) and thus an MCM2814
will only respond if both its chip-selects are low.
During the programming routine all lines in the matrix
are low, but during verification each chip is individually
selected by a low on one row and one column. The
required value to be sent to port B to achieve this is
derived from the value in COUNT using the table
TAB1.

If the LOAD routine is selected it performs a loop
which does the opposite of the program loop. It
transfers the contents of an MCM2814 into the
EEPROM of the MC68HC805B6 within the
programmer. It only looks at socket #0 and checks for
an acknowledge before it proceeds to over-write the
data in the B6.
The three routines WRT, RDAlL and WRTAl were
used during de-bug, are self-explanatory, and have
been left in the program for interest and for future use
if required. They are not used by the MC68HC805B6
butcan be used ifthe program is run on a development
system (eg an M68HC05EVM).
The IIC READ, SEND and WRITE routines are self
contained and, by using ordinary I/O lines, could be
used on any 68(HC)05 microprocessor. The READ
sub-routine reads one byte using the IIC address in
ADDR and ttie sub.address in SUBARD .. The
commented out lines (382-385) provide a simple
method of also reading a second byte. Data is returned
in IOBUF (and IOBUF+ 1 in the case of a 2-byte read).
Clearly, the number of bytes can be increased by
including more in-line code or by executing a loop.

The SEND sub-routine writes data on the IIC bus at IIC
address AD DR starting at the address in RAM contained
in the· index register. The number of bytes sent is
determined by the value stored the accumulator. If, as
in this example, a sub-address has to be sent, then it
should be in the RAM location pointed to by the index
register with subsequent locations containing the
data. SEND is suitable for most IIC peripherals. The
WRITE subroutine constitutes a SEND followed by a
delay and a READ. This is what is required to write a
byte to an MCM2814, EEPROM programming is
started by an IIC write and continues until the chip is
addressed again by READ.
The IIC routines use simple BClR and BSET
instructions on the data registers so that an active
high level is generated. This is not strictly what should
be done on an IIC bus but is OK in the case where
there are no other possible masters in the system. A
passive high can be obtained by keeping the data bit
of the I/O lines used for the IIC bus at a zero and using
BCLR and BSET instructions on the corresponding
data direction bits. If this is done care must be taken
to ensure that these zeros are not lost by any other
read-modify-write operations carried out on the data
register. A BCLR or BSET on another bit on the same
port will read the whole port, modify the required bit
and then write the whole port. The data bit on an IIC
line which was pulled high by the external pull-up
would thus become a· one. This would cause a
malfunction the next time the corresponding DDR bit
was set to a one, as the pin would output a high
instead of a low. This can be avoided by using other
types of instructions (eg STA) or by making sure the
relevant data bit is a zero before enabling an output.

172

0001
0002
0003
0004
0005
0006
OOO?
0008
0009
0010
0011
0012
0013
0014
0015
0016
00l?
oOlli
0019
0020
0021
0022
0023
0024
0025
0026
002?
0028
0029
0030
0031
0032
0033
0034
0035
0036
003?
0038
0039
0040
0041
0042
0043
0044
0045
0046
004?
0048
0049
0050
0051
0052
0.053
0054
0055
0056

****************************************************************************

MC68HC05B6 controlled MCM44182 programmer.

* This software was developed by Motorola Ltd. for demonstration purposes. *
No liability can be accepted for its use in any specific application.
Original software copyright Motorola - all rights reserved.

14th M_y '91

P. Topping

****************************************************************************

0000
0001
0002
0003
0004
0005
0006
OOO?
0100
Of 00

PORTA
PORTB
PORTC
PORTD
PORTAD
PORTBD
PORTCD
EECTL
E2PR
BUFF

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

$00
$01
$02
$03
$04
$05
$06
SO?
$0100
$OFOO

PORT A ADDRESS
B
C
D
PORT A DATA DIRE<;TION REG.
B
C
EEPROM CONTROL REGISTER
EEPROM
DEBUG USE ONLY

******************************************************-RAM allocation.

____ *** _______________________________________________ w_
0050

ORG

0050
005i
0052
0053

ADDR
DPNT
SUBADR
roBUF

RMB
RMB

0055
0056
005?
0058
0059
005_
005b
005c

W1
W2
W3
W4
W5
W6
W?
COUNT

RMB
RMB
RMB
RMB
RMB
RMB
RMB

005d

STAT

RMB

DOSe
00f8
OOff

STACK
SP

RMB

lIC
IIC
IIC
IIC

RMB
RMB

RMB

RMB

0800

NVM.AS5
0058
0059
0060
0061
0062
0063
0064
0065 0800
0066 0802
006? 0804
0068 0806
0069 0808
OO?O 080_

$0050

1
1
1
1
1
1
1
1

W
0

R
K
N
G
LOOP COUNTER
STATUS BYTE :0: not used
1: lIC R/W l:READ, O:WRITE
2: ACKNOWLEDGE OK

154

Ii

RMB
ORG

ADDRESS
DATA POINTER
SUB-ADDRESS
BUFFER

not used
BYTES USED (0 INTERRUPTS
AND 4 NESTED SUBROUTINES)

$0800
page

2

********************************************************

Main program.
********************************************************

_6
b?
_6
b?
b?
b?

cO
01
ff
00
02
04

START

LOA
STA
LOA
STA
STA
STA

tSCO
PORTB
'$FF

CONTROL LINES LOW

PO~TA

LEOS OFF

PORTC
PORTAD

ALL OUT - GREEN LEDS

173

0011
0072
0013
0074
0015
0076

!ron
0018
0079
0·080
0081
0082
0083
0084
0085
0086
0087
0088
0089
0090
0091
0092
0093
0094
00"95
0096
0-097
0098
0099
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0111

OBOe
OBOe
0810
0812
0814
0817
081a

b1
a6
hi
ae
cd
Oa
20

06
3f
05
64

081c
081e
0820
0822
0824
0826
0827
082a
082d

a6
b7
3f
3f
3f
Sf
00
cc
02

aD
50
01
52
5d

Oa 35
03 02
fe

03 03
09 08
03 2e

CONT

STA
LDA
STA
LDX
JSR
BRSET
BRA

PORTCo
ts3F
PORTBD
nOD
PN
5,PORTD,CONT

LDA
STA

I$AO
ADOR
EECTL
SUBADR
STAT

CLR

CLR
CLR
CLRX
BRSET
SKLO

ALL ooT - RED LEOS
6,7 IN - IIC BUS
0-5 OUT - NVM SELECTION
WAIT 230mS FOR MCM2814 SUPPLY
TO SETTLE
NVMs POWERED UP ?
NO, 00 NOT PROCEED
YES, INITIALISE IIC ADDRESS
READ FROM EEPROM (B6)

O,PORTD,SKLD

JMP

LOAD

BRSET

l,PORTD,VERF

LOAD B6 EEPROM 1
YES
NO, VERIFY ONLY 1

.*******************************************************

B6 EEPROM (SIOl-SIFF) -> 8 NVMs ($00 - SFE).
********************************************************

0830
0832
0834
0836
0838·
083a
083e
083f
0840
0842
0844

3f
3f
a6
b1
a6
b1
cd
4f
ad
3f
5f

00
02
cO
01
ff
52
09 92

08A5
0848
084 ..
084c

d6
ad
a3
26

01 01
06

PROG

Oe
52

OLOOP

ff

f7

084e· 20 Oe

0850
0852
0854
0856
01l~ 0859
0119 085b
0120 085d
NVM.AS5
0122
0123
0124
0125
0126
0121
G1.28
0129
0130
0131 OS5e
0132 0860
0.133 0862
0134 0864
0'135
0136 0866
0131 0868
0138 086b
0139 086d
0140 086f

b1
a6
ae
cd
3c
be
81

53
02
52
09 89
52
52

WR1

GREEN LEDS ON
RED LEDS ON

CLR
CLR
LOA
STA
LDA
STA
JSR
CLRA
BSR
CLR
CLRX

PORTA
PORTC
iSCO
PORTB
i$FF
SUBADR
READ

LOA
BSR
CPX
BNE

E2PR+I,X
WR1
1255
OLooP

GET BYTE AND
SEND IT TO NVM
DONE 1

BRA

VERF

YES. VERIFY

STA
LDA
LDX
JSR
INC
LDX
RTS

IOBUF

ENABLE ALL NVMS
SUBADR = SFF
CLEAR POR WRITE PROTECT
DATA = $00
CLEAR WRITE PROTECT BYTE

WR1
SUBADR

.2

No. BYTES TO SEND (INC. SUB-ADDRESS)

ISUBADR
WRITE
SUBADR
SUBADR

!IC WRITE
NEXT LOCATION

page

3

****************************t***************************

Verify.

B6 EEPROM (S0101-S0lFF) v. NVMs (SOO - SFE).
********************************************************

a6
b1
b1
3f

ff
02
00
5c

VERF

be
d6
b1
ad
24

5c
09 00
01
13
35

VLP

LDA
STA
STA
CLR

ISFF
PORTC
PORTA
COUNT

LDX
LDA
STA
BSR
BCC

COUNT
TAB1, X
PORTB
VRFl

PO

174

ALL LEOS OFF
START AT SOCKET

SELECT NVM
ACC. TO COUNT

.0

0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
015S
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170

0871 04 5d 30
0874
0876
0878
087a
087e
087e
0880
0882
08S4
OS86
088S
08Sa
08Se
08Se
0890
0892
Q894
OS96
0898
089a
08ge
08ge
OSaO
OSa2

be
26
11
a3
26
13
a3
26
15
a3
26
17
a3
26
19
a3
26
1b
a3
26
1d
a3
26

5e
02
02
01
02
02
02
02
02
03
02
02
04
02
02
05
02
02
06
02
02
07
02
l f 02

08a4 20 30

NVM;AS5
0172
0173
0174
0175
0176
0177
0178
0179
01S0
01Sl 08a6
0182 OSa8
0183 OSaa
0184 08ae
01S5 08ae
01S6 OSbO
0187 08b2
0188 OSb4
0189 08b6
0190 OSbS
0191 OSba
0192 OSbe
0193 OSbe
0194 OSeO
0195 08e2
0196 08e4
0197 08e6
0198 OSe8
0199 08ea
0200 08ee
0201 OSee
0202 OSdO
0203 OSd2
0204 OSd4
0205
0206 OSd6
0207 08dS
020S OSda
0209 OSde
0210 OSde

FO

F1

F2

F3

F4

F5

F6

F7

FINP

BRSET

2,STAT,FINP

LOX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR

COUNT
Fl
O,PORTC
tl
F2
1,PORTC

BRA

IF NO ACK. THEN NO LED

'2

F3
2,PORTC

n
F4
3,PORTC

'4

F5
4,PORTC

'5
F6
S,PORTC

'6

F7
6,PORTC

'7

FINP
7,PORTC
OUT

page

********************************************************

Verify (continued).

B6 EPROM ($OlOl-$OlFF) v. NVM ($00 - $FE).
********************************************************

be
26
11
a3
26
13
a3
26
15
a3
26
17
a3
26
19
a3
26
lb
a3
26
ld
a3
26

Se
02
00
01
02
00
02
02
00
03
02
00
04
02
00
05
02
00
06
02
00
07
02
l f 00

3e
b6
al
23
3f

5e
5e
07
SS
01

PO

P1

P2

P3

P4

P5

P6

P7

OUT

COUNT
P1
O,PORTA

LOX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR
CPX
BNE
BCLR

OUT
7,PORTA

INC
LOA

COUNT
COUNT

n
P2
1,PORTA

'2

P3
2,PORTA

'3

P4
3, PORTA
H
P5
4,PORTA

'5

P6
5., PORTA

16
P7
6,PORTA

'7

CMP

n

BLS
CLR

VLP
PORTB

175

NEXT SOCKET

FINISHED
YES, ALL CONTROL LINE LOW

0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230

08eO 20 fe
08e2
08e4
08e5
08e8
08eb
08ed
08ef
08f2
08f4
08f6
08f8
08fa
08fe
08fd
08fe
08ff

3f
Sf
cd
04
b6
be

d1
26
3e
be
a3
26
98
81
99
81

VRFl

09 92
5d 13
53
52
01 01
Oa
52
52
ff
e9

VLOOP

FAIL

0900 ee ed eb e7 de dd
db d7

NVM.AS5
0232
0233
0234
0235
0236
0237
0238
0239 0908
0240 090a
0241 -090e
0242 090e
0243 0910
0244
0245 0912
0246 0915
0241 0918
0248 09la
0249 091e
0250 091e
0251 0920
0252 0923
0253 0925
0254 0927
0255 0929
0256 092b
0251 092d
0258
0259 092f
0260
0261 0932
0262 0934
0263 0937
0264 0939
0265 093e
0266 093e

AND IlAIT HERE

BRA

52

TAB1

CLR
CLRX
JSR
BRSET
LDA
LDX
CMP
BNE
INC
LDX
CPX
BNE
CLC
RTS
SEC
RTS
FCB

SUBADR
READ
2, STAT,FA-IL
IOBUF
SUBADR
E2PR+1,X
FAIL
SUBADR
SUBADR
.255
VLOOP

GET A BYTE FROM NVM
ACKNOWLEDGE OK ?
YES, CHECK DATA
COMPARE NITH B6 EEPROM BYTE
SAME
YES, CONTINUE
FINISHED (255 BYTES) ?
PASS, EXIT NITH C CLEAR
FAIL, EXIT NITH C SET

SEE,SED,SEB,SE7,SDE,SDD,SDB,$D7
page

5

********************************************************

NVM ItO, $OO-$FE) -> B6 EEPROM ($101-$lFF).
*****.**************.***~*********.********************

a6
b7
al>
b7
b7

ee
01
fe
00
02

LOAD

cd
04
b6
12

09 92
5d 17
53
07
07
12
Oa 2d
07
Ob
52
52
ff
e3

SELECT POSITION 0

LDA
STA
LDA
STA
STA

t$EE
PORTB
tSFE
PORTA
PORTC

ILOOP

JSR
BRSET
LDA
BSET
BSET
BSR
JSR
BSET
BSR
INC
LDX
CPX
BNE

READ
2,STAT,SKIP
IOBUF
l,EECTL
2,EECTL
DOlT
P10
l,EECTL
DOlT
SUBADR
SUBADR
.255
lLOOP

ee 08 5e

SKIP

JMP

VERF

be 52

DOlT

LDX
STA
BSET
JSR
CLR
RTS

SUBADR
E2PR+1,X
O,EECTL
P20
EECTL

14

ad
cd
12
ad
3c
be
a3
26

d7
10
cd
3f
81

01 01
07
Oa 33
07

NVM.AS5
0268
0269
0270
0271
0272
0273
0214
0275
0276
0277
0278 093f 3f 52

POSITION 0 LEDS ON

GET BYTE FROM NVM
ACKNONLEDGE OK
YES, GET DATA
SET E1LAT
SET E1ERA
ERASE BYTE
NAIT 9.2 mS
SET E1LAT TO WRITE BYTE

GET ADDRESS
LATCH DATA
START PROGRAMMING
NAIT 18.4 m$
STOP

6

page

************************************.*******************

Debug routines for use with EVM, not used
in 805B6.
RAM ($FOO - $FFE) -> B6 EEPROM ($101 - SlFF).
**************************************.*.************.**

WRT

CLR

SUBADR

176

0279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295
0296
0297
0298
0299
0300
0301
0302
0303
0304
0305
0306
0307
0308
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320
()321
0322
0323
0324
0325
0326
0327
0328
0329

0941 Sf
0942
0945
0947
0949
094b
094e
0950
0952
0954
0956
0958

d6
12
14
ad
cd
12
ad
3c
be
a3
26

CLRX
Of 00
07
07
e7
Oa 33
07
eO
52
52
ff
e8

LOOP2

095a 20 fe

LOA
BSET
BsET
BSR
JSR
BSET
BSR
INC
LOX
CPX
BNE

BUFF,X
1,EECTL
2,EECTL
DOlT
P20
1,EECTL
DOlT
SUBADR
SUBADR
.255
LOOP2

SET ElLAT
SET E1ERA
ERASE BYTE
SET ElLAT TO WRITE BYTE

BRA
***********************************.*.******************

NVM ($00 - $FF) -> RAM ($OFOO - $OFFF).
*******************************************************-

095c 3f 52
095e a6 ee
0960 b7 01

RDALL

0962
0965
0967
0969
096c
096e

RLOOP

cd
be
b6
d7
3c
26

09 92
52
53
Of 00
52
f2

0970 20 fe

CLR
LOA
STA

SUBADR
UEE
PORTB

JSR
LOX
LOA
STA
INC
BNE

READ
SUBADR
IOBUF
BUFF,X
SUBADR
RLOOP

SELECT POSITION 0

BRA
********************************************************

RAM ($OFOO - $OFFF) -> NVM ($00 - $FF).
********************************************************

0972
0974
0976
0978

3f 52
a6 ee
b7 01
Sf

0979 d6 Of 00
097c cd 08 50
097f 26 f8

WRTAL

WLOOP

0981 20 fe

NVM.AS5
0331
0332
0333
0334
0335
0336
0337
0338 0001
0339 0005
0340
0341 0006
0342 0007
0343 007f
0344 OOff
0345 003f
0346
0347 0983 13 5d
0348 0985 b7 55

CLR
LOA
STA
CLRX

SUBADR
UEE
PORTB

LOA
JSR
BNE

BUFF,X
WR1
WLOOP

SELECT POSITION 0

BRA
page
******************************************************w_

IIC routines.
***************************.**************************--

IlCP
IlCDD

EOU
EOU

$01
$05

PORTB
DDRB

SCL
SDA
DIN
DOUT
OPEN

EOU
EOU
EOU
EQU
EOU

$06
$07
$7F
$FF
$3F

IlC - clock line
lIC - data line
INPUT DATA
OUTPUT DATA
TRI-STATE BOTH

SEND

BCLR
STA

1,STAT

WI

WRITE lIC DATA
SAVE No. BYTES TO SEND

177

0349
0350
0351
0352
0353
0354
0355
0356
0357
0358
0359
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
0370
0371
0372
0373

0987 20 Ob
0989
098b
098d
098f

13
b7
ad
ed

5d
55
05
Oa 2d

WRITE

BRA

IICBUS

BCLR
STA
BSR
JSR

I,STAT
WI
IICBIlS
PI0

WRITE TO NVM
SAVE No. BYTES TO SEND
9.2 mS NVM WRITE TIME

0992 12 5d

READ

BSET

I,STAT

READ IIC DATA

0994 Id 01
0996 Ie 01
0998 Ie 01

IICBUS

BCLR
BSET
BSET

SCL, IICP
SDA,IICP
SCL, IICP

CLOCK LOW
DATA HIGH
CLOCK HIGH

099a a6 ff
09ge b7 05

LOA
STA

IDOUT
IICDD

DRIVE
BOTH

09ge 11 50
09aO b6 50

BCLR
LOA

O,ADDR
ADDR

RW = 0 ALWAYS WRITE (SUB-ADDRESS)
SEND CHIP ADDRESS

BCLR
BCLR
STX
BSR

SDA,IICP
SCL,IICP
DPNT
SHIFT

START CONDITION
DATA GOES LOW WHILE CLOCK HIGH
CHIP ADDRESS OUT

BRCLR

I,STAT,WRBUS

READ. OR WR I TE ?

09a2
09a4
09a6
09a8

1f 01

IICD3

Id 01
bf 51
ad 57

09aa 03 5d 40

NVM.AS5
0375
0376
0377
0378
0379
0380
0381
0382 09ad
0383 09af
0384 09bl
0385 09b3
0386 09b5
0387 09b7
0388 09b9
0389 09bb
0390 09bd
0391
0392 09bf
0393 0ge1
0394 09c3
0395
8396
0397
0398
0399
0400
0401 0ge5
0402 0ge7
0403
0404 0ge9
0405 0geb
0406 0ged
0407 09dO
0408 09d2
0409 09d4
0410 09d5
0411 09d7
0412
0413 09d8
0414 09da
0415 09de
0416 09de
0417 0geO
0418 0ge2

page

8

********************************************************
Send sub-address and read data from bus.
**************.***.*.**** ••• *** ••• **********************

b6
ad
10
b6
Ie
Ie

52
50
50
50
01
01
I f 01
Id 01
ad 42

RDBUSI

a6 7f
b7 05
ad 04

RDBUS3

RDBUSQ

ad 11
20 2f
ae
Ie
Oe
Id
39
Sa
26
81

08
01
01 00
01
53

Ie
a6
b7
Ie
Id
1f

01
ff
05
01
01
01

ROB
RDBUS2

f4

RACK
RA2

LOA
BSR
BSET
LOA
BSET
BSET
BCLR
BCLR
BSR

SUBADR
SHIFT
O,ADDR
ADDR
SDA, IICP
SCL, IICP
SDA,IICP
SCL, IICP
SHIFT

LOA
STA
BSR

.DIN
IlCDD
RDB

DATA IN FROM BUS

BSR
LOA
STA
BSR

RACKF
IOBUF
IOBUF+I
ROB

DUMMY ACKNOWLEDGE
MOVE
UP
AND READ 8 MORE

BSR
BRA

RACK
IICEND

LOX
BSET
BRSET
BCLR
ROL
DECX
BNE
RTS

18
SCL,IICP
SDA,IICP,*+3
SCL,IICP
IOBUF

BSET
LOA
STA
BSET
BCLR
BCLR

WRITE SUB-ADDRESS
SET BIT 0 FOR READ
CHIP ADDRESS
BOTH HIGH, NO
STOP CONDITION
START CONDITION
RE-SEND CHIP ADDRESS

READ 8 BITS

CLOCK HIGH
DATA LINE (RESULT IN CARRY)
CLOCK LOW

RDBUS2

SDA, IICP
IDOUT
IlCDD
SCL,IICP
SCL, IICP
SDA, IICP

178

LAST BYTE READ : SDA HIGH
SDA OUT
DUMMY ACKNOWLEDGE
CLOCK

0419
0420
0421
0422
0423
0424

0ge4 a6 7f
0ge6 b7 05
0ge8 81
0ge9 I f 01
0geb 20 ed

NVM.AS5
0426
0427
0428
0429
0430
0431
0432
0433 0ged
0434 0gef
0435 09fO
0436 09f2
0437 09f4
0438 09f6
0439
0440 09f8
0441 09fa
0442 09fe
0443 09fe
0444 OaOO
0445
0446
0447
0448
0449
0450
0451
0452 Oa01
0453 Oa03
0454 Oa04
0455 Oa06
0456 Oa08
0457 OaOa
0458 OaOe
0459 OaOe
0460 Oa10
0461 Oa12
0462 Oa14
0463 Oal5
0464
0465 Oa17
0466 Oa19
0467 Oa1b
0468 Oa1d
0469
0470 Oalf
0471 Oa22
0472
0473 Oa24
0474 Oa26
0475 Oa28
0476 Oa2a
0477 Oa2e

RACKF

LDA
STA
RTS

to IN
IICDD

SDA IN

BCLR
BRA

SDA,IICP
RA2

ACKN. WITH FOLLOWING BYTE

9

page

********************************************************
Send sub-address and write data onto bus.
*******************************************************.

be
f6
ad
3e
3a
26
1e
1e
a6
b7
81

51

WRBUS

Of
51
55
f5
01
01
3f
05

IICEND

DATA BUFFER POINTER
DATA

LOX
LOA
BSR
INC
DEC
BNE

DPNT
O,X
SHIFT
DPNT
W1
WRBUS

BSET
BSET
LOA
STA
RTS

SCL,IICP
SDA,IICP
.OPEN
IICDD

No. BYTES

STOP CONDITION
DATA GOES HIGH WHILE CLOCK HIGH
TRI-STATE

********************************************************

Shift out 8 bits and check acknowledge bit.
********.***********************************************

ae
49
24
Ie
20
lf
20
1e
Id
If
Sa
26

08

ee

a6
b7
15
1e

7f
05
5d
01

04
01
04
01
00
01
01
01

SHIFT
SHIFT1

SHIFT2
SHIFT3

WACK

Of 01 02
14 5d
1d
lf
a6
b7
81

01
01
ff
05

NVM.AS5
0479
0480
0481
0482
0483
0484
0485
0486 Oa2d ae 04

ACOK

.a

LOX
ROLA
BCC
BSET
BRA
BCLR
BRA
BSET
BCLR
BCLR
DECX
BNE

SHIFT2
SDA, lICP
SHIFT3
SDA,IICP
SHIFT3
SCL,lICP
SCL,lICP
SDA, IICP

LOA
STA
BCLR
BSET

to IN
IICDD
2,STAT
SCL, lICP

CLEAR FLAG
CLOCK

BRCLR
BSET

SDA, IICP, ACOK
2,STAT

ACKNOWLEDGE OK
NO, SET FLAG

BCLR
BCLR
LOA
STA
RTS

SCL,lICP
SDA,lICP
.DOUT
lICDD

SHIFT OUT 8 BITS
NO, DA~A - 1
DATA = 0
DELAY
CLOCK HIGH
CLOCK LOW
DATA LOW

SHIFT1

page

WRITE ACKNOWLEDGE

10

********************************************************

Delay (W2 x 2.3mS with a 2MHz bus).

***************'***********.******************************
P10

LOX

t4

179

9.2 mS

0487
0488
0489
0490
0491
0492
0493
0494
0495
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506
0507
0508
0509
0510
0511
0512
0513
0514
0515
0516
0517
0518

Oa2f
Oa31
Oa33
Oa35
Oa37
Oa38
Oa3a
Oa3b
Oa3d
Oa3f
Oa41

bf
20
ae
bf
Sf
ad
5a
26
3a
26
81

56
04
08
56
07

P20
PN
TPAU
DLOOP

fb
56
f6
DALLY

STX
BRA
LOX
STX
CLRX
BSR
DECX
BNE
DEC
BNE
RTS

112
TPAU
.8
112

18.4 mS

DALLY

12
3
3

DLOOP
112
TPAU

15
18

18x256/2-2304uS

****************************************************
86 reset and interrupt vectors.
****************************************************

lff2
lff2
lff4
lff6
lff8
lffa
Hfe
Iffe

08
08
08
08
08
08
08

00
00
00
00
00
00
00

ORG

$lFF2

FOB
FOB
FOB
FOB
FOB
FOB
FOB

START
START
START
START
START
START
START

SCI
TIMER (OVER)
TIMER (OUT CMP)
TIMER (IN CAP)
IRQ
Sill
RESET

END

180

AN448

IIFLOF" Teletext using M6805 Microcontrollers
By Peter Topping
MCU Applications
Motorola Ltd, East Kilbride

1. INTRODUCTION
The "T" members of the MC68HC05 family of MCUs provide a convenient and cost effective method of adding
on-screen-display (OSO) to TVs and VCRs. As well as the 64-character OSO capability, they include 8 Kbytes of
ROM (adequate for Teletext, frequency-synthesis, stereo and OS D) ,320 bytes of RAM, a 16-bit timer and 8 pulsewidth-modulated O/A converters. The MC68HC05T7 also includes IIC hardware and, by using a 56-pin package,
4 ports of I/O independent of the OSO, serial and O/A outputs. It is thus suitable for large full-feature chassis.
The MC68HC05Tl is in the middle of the price/performance range and includes most of the features of
the MC68HC05T7 but in a 40-pin package. This is achieved by sharing I/O with the other pin functions (SPI, OSO,
O/Al. Even if all these features are used, there is sufficient I/O for most applications.
The MC68HC05T2 is a 16K upgrade of the MC68HC05T1 and the MC68HC05T3 a 24K version with increased
RAM (512 bytes) and enhanced OSO (112 characters and 2 rows of OSO buffer). The low cost MC68HC05T4
has 5 Kbytes of ROM and 96 bytes of RAM making it suitable in simpler (eg mono, non-Teletext! applications.
The T4 and T7 also include a 14-bit O/A converter to facilitate voltage synthesis tuning. There are EPROM (and
OTP) versions of the T3 (including T1 and T2 emulation), T4 and T7.
This application note describes an example of Teletext control software written for the MC68HC05T7 which
directly controls Teletext chips of the type 5243. Spanish FLOF Teletext (level 1.5) is handled using packet X/26.
If no CCT teletext chip is present on the IIC bus (as indicated by the lack of an acknowledge), all Teletext functions
are disabled in software. About 3Kbytes of ROM are used allowing the code to fit into the 7.9K bytes available
in an MC68HC05T7 along with tuning, OSO and stereo functions.
The software in the included listing has been written for the MC68HC05T7 but could, with a little modification,
be implemented on other M6805 microcontrollers. A microcontroller without IIC hardware can be used as long
as additional software is included to facilitate the IIC bus using I/O pins. An example of IIC master I/O driven
software can be found in application note AN446.

2. uFLOF TELETEXT FEATURES
R

Full Level One Feature (FLOF) Teletext utilises "ghost" packets to provide features in addition to those available
with the original CCT Teletext. The primary enhancement is the provision of a menu with a choice of four linked
pages selectable by the user with a single press of one of four coloured buttons on the remote control. The menu
itself is sent in the ghost page using packet 24 while the linked page numbers are contained in packet 27. In
addition to linked pages, packets 26 and 30 are used. Packet 26 allows for the substitution af selected characters
in the display by special characters specific to a particular country.' This example application includes the Spanish
implementation of packet 26. The broadcast service data packet (8130) is used to get the initial (index) page for·
each channel and to display station identification information.

181

MGhost- packets handled
X/24 :
The FLOF menu information contained in this page extension packet is transferred by the microcomputer to
row 24 of the display chapter. When links are disabled because there is no packet 27 (destination code 0) or when
bit 4 of byte 43 is O. row 24 is blank.

X/26 :
Optional handling of modes 1xxxx. 01111 and 00010 in accordance with the Spanish Teletext specification. All
the additional characters which are available in the 5243 CCT chip are handled. The feature can be disabled with
a hardware link on an I/O pin (see figure 1) so that the software can be used at level 1.0 in non-Spanish countries
also using packet 26.

X/27 :
This packet contains the linked page numbers for the red. green yellow. blue and index (black) keys. Bit 4 on the
link control byte (byte 43) is used to determine if these links are enabled (1) or disabled (0). When enabled. the
Spanish specification requires that bits 1. 2 and 3 be used to enable the green. yellow and blue links respectively.
This use of these bits is not defined in the World Teletext Specification. For this reason their use is selectable by
a hardware link (see figure 1). If these bits are not used. all links (if enabled by bit 4) will be taken from packet 27
but will be automatically disabled if the broadcast links are default (FF3F7F) or invalid.

8/30:
The broadcast service packet is used to supply the index page number on exit from standby and (if teletext is not
stopped) after a channel change. Bytes 10-30 of this packet are displayed for 5 seconds on exit from standby and
(if teletext is not stopped) after a channel change.

3. IMPLEMENTATION
The software listing is in two parts. The first part contains the "idle" loop and IIC routines from the main TV control
part of the MC68HC05T7 application. The idle loop controls the timing of everything performed by the
microprocessor. scans the local keyboard. checks whether or not an IR command has been received. etc. It also
monitors the relevant flags in the Teletext chip and performs the tasks (eg fetching linked pages) which have to
be performed independently of requests for the user.
The second and main listing is the Teletext module itself. It contains all the subroutines required to carry out
automatic and user requested Teletext activity. Both modules use the same RAM allocation file (RAMT8.S05)
which is included in the listing of the Teletext module. This listing also includes a symbol cross-reference table.
Figure 1 shows a simplified Circuit diagram of the application. Most of the MC68HCQ!)T7's I/O is used for purposes
other that Teletext and is not shown in detail. Communication with the 5243 Teletext chip is via an IIC bus in which
the T7 is always the master. The function ofthe three 1/0 pins used for Teletext is described under" Ghost packets
handled" and "Inputs and Outputs".
A version of this Teletext software has been implemented on an MC68HC05C4 for use in a TV where the other
control functions were handled by a separate microcontroller. The signal from the IR pre-amp was fed into the
C4 which used Teletext commands to control a 5243 via a software IIC bus. Non-Teletext commands were regenerated by the C4 and sent to the other microcontroller. This arrangement allows Teletext to be added to a
chassis which was originally deSigned without considering Teletext.

182

O.S.D., Local keyboard,
Analogues, Standby, Mute,
Stereo, AV, etc.

5V
Contrast Reduction
Fast Blank

R
G
2 x4k7
I/O

2 x 22pf

~ ':"OM
I. A.
Pre-amp

OSC1

SCL

SCL

SDA

SDA

5243

8kx8
RAM
(eg.
MCM6264)

OSC2

MC68HC(7)05T7
PB3

TCAP

Picture
Control
5231

PB6

PB7

5V
Video

Figure 1. MC68HC(7)05T7 - Teletext application circuit

4. IDLE LOOP
In the example application the idle loop code is in the main TV control software module rather than in the teletext
module. Listing 1 shows the relevant parts of this module. The loop time is 12.8mS and it is at this rate that the
timing counters used by Teletext (CNTl and CNT4) are incremented. The standby condition is checked first; if
the TV set is in standby then there is no IIC activity and hence no reading from, or writing to, the 5243. If the TV
has just exited from standby, as indicated by the flag 3,STAT2, then Teletext is initialised using the sub-routine
RESTRT. This sulrroutine writes to the 5243's control and mode registers (RS, R6 and R7) and checks that the
IIC acknowledge is present. If there was no acknowledge, as indicated by flag 6,STAT7, then no further Teletext
activity is attempted.
If an acknowledge is present, Teletext polling goes ahead, although it is suspended if there is a mute or time
display. A mute indicates that the channel has just been changed, or no channel is tuned. During time display,
all other Teletext activity is suspended. Re-initialisation using sulrroutine START2 is performed if flag 7,STAT5
is set by a change of the tuned frequency.

183

Counter CNT4 is used to delay the transfer of packets 24 (page extension - FLOF menu), 27 (links), 26 (enhanced
display characters) and the control bits from row 25 (display page) after the initial arrival of a page. When row 24
is read the 5243 FOUND flag is setto indicate that the arrival has been acted upon. If UPDATE is on then an update
indicator appears if the update control bit (C9) is set or if the sub-page has changed or if it is the first arrival of the
page. The update display is performed by the sub-routine ARRVD which clears the transient flags and enables
the required display, i.e. page no. in normal mode and the whole of row 0 in sub-page mode. Any boxed
information (eg sub-titles or newsflash) in the current page is also displayed. The last Teletext function performed
by the idle loop is the checking of the FOUND flag in the 5243. This is accessed via the IIC bus; it is on the last
(not displayed) row of the display page along with the current page and sup-page numbers and the control bits.
If there is a current Teletext transient (time, row 0 box or packet 8/30), the transient control branch from the idle
loop is executed. This routine checks to see if it is time to end the transient. If it is, the subroutine OSDLE is
executed. It resets transients for both the OSD generated by the MC68HC05T7 and Teletext. The sub-routine
RSTMD2 performs this function for Teletext. It is called from within the sub-routine OSDLE (not listed).

5. REMOTE CONTROL FUNCTIONS
TV(fXT
Toggle between TV & Teletext mode.

0-9
Number keys for entry of page and sub-page numbers

Red, Green, Yellow, Blue
Linked page access keys. The decoder stores four pages of text. These are the display page and the three pages
corresponding to the red, green and yellow links. The blue linked page is not acquired in advance. In the absence
of FLOF data or if the links are disabled by the control bit in packet 27, the red key is page+ 1 and the green key
page-l. Under these circumstances the requested page and the next three pages are acquired.

PC+iThese keys always sele<..t page+ l/page-l regardless of the availability of FLOF information. As with the red, green
and yellow keys, the page is displayed immediately if it is already in RAM.

INDEX
This key operates as ail additional link with the difference that if the link is invalid the initial page from packet 8/
30 is selected.

SUB-PAGEff/ME
Text mode: Enter sub-page mode, (max. 3979). TV mode: Display time in top-right-hand corner for 5 seconds.
Pressing this key during a station identification display (packet 8/30 bytes 10-30) can be used to extend this display
beyond the five seconds it appears for, after a channel change.

STOP
Halt acquisition, "STOP" is displayed instead of page number. Press again to restart. If acquisition has been
stopped by partially entering a new page number then this key can be used to return to the original page.

184

MIX/NO-MIX

Toggle between Teletext and mixed display. Use ofthis key causes the display ofthe top status row for 5 seconds
if it is not being displayed because the current page is a newsflash or a sub-title. 5243 contrast reduction is enabled
in mixed mode.
FULL./T'OP/BOT
Selects one of the three display formats, normal. top half enlarged, bottom half enlarged.
REVEAL
Reveal hidden text, toggle action.
UPDATE.
Return to picture until a new version of the requested page arrives. When it arrives, its page no. is displayed in
the top-right-hand corner, the key operates in both TV and Teletext mode, set is put into TV mode. Any boxed
information (alarm clock, newsflash or sub-title) will be displayed. In sub-page mode the complete header is
displayed so that both page & sub-page numbers can be seen. Cancel update by entering Teletext mode and then
going back to TV mode by pressing the TV{Text key twice.

6. TELETEXT SUBROUTINES
6a. Subroutines:

TVTX, UPDATE, DIGITO and GETIT

The Teletext module (listing 2) comprises various sub-routines which are used both by the idle loop and to perform
any Teletext actions initiated by commands from the IR remote control. They are described in the order in which
they appear in the listing.
TVTX is executed when the TV/TEXT button is pressed. Its function is to toggle between TV mode and Teletext
mode. The flag 0,STAT indicates the current mode. This flag routes the microprocessor to execute either TXTOFF
or TXTON according to the current mode. TXTON checks that Teletext hardware is present and does nothing if
there has been no IIC acknowledge. If, however, a 5243 is present in the TV, it clears all transients (OSDLE) and
sets up the Teletext mode. It initialises the control registers (R5 and R6) to display text and background both in
and out of boxes. For newsflashes the set-up is text and background within boxes and picture outside. TXTOFF
also resets transients but forces TV mode and sync. Polling and updating continue as a background activity.
When the UPDATE key is pressed the update flag 4,STAT2 is set and TXTOFF executed so the TV is forced to
TV mode. If there is a current transient hold (eg time), the hold is cleared before TXTOFF is executed.
The number entry sub-routine DIGITO branches to DIGITS in sub-page mode but otherwise accepts any number
key as a page number input. Three digits are required, the pointer PDP holding the current position (0, 1 or 2 for
hundreds, tens or units). During entry the flag 2,STAT is set to stop Teletext activity. The numbers have to be
written to the top-left-hand corner of the display page as well as saved in RAM. Once all three digits have been
entered the page is requested and page acquisition restarted.
The code at label GETIT makes this request after first checking whether or not the selected page has already been
requested (it could be the current display page or an already requested linked page). If it has, then a switch is made
to the chapter associated with the appropriate acquisition circuit and no new request is generated. If not, the new
request is made and the FOUND flag set.

185

6b. Subroutines:

Colours, INDEX, NPAGE and PPAGE

The four colour keys (Red. Green. Yellow and Blue) are primarily intended for selecting Teletext linked pages.
When pressed the chapter which corresponds to the apl)ropriate acquisition circuit is selected for display. If links
are disabled (by the link control bit or because there is no packet 27). then the RED and GREEN keys select current
page + 1and -1 respectively. This choice is taken according to the state offlag 3.STAT3 which reflects the condition
of the link control bit in packet 27. The code executed by RED. if links are not in use. is the same as that executed
by the "+" function (NPAGE) which always selects the next page. Similarly the alternative GREEN function
(PPAGE) is the same as for the "-" key. The YEllOW and BLUE keys do nothing under these circumstances. In
Spanish Teletext the GREEN. YELLOW and BLUE links can be individually inhibited. but the RED link is only
inhibited if all links are off.
The chapter associated with the selected page is displayed immediately if it has already been requested. This will
normally be the case if a linked page (red. green or yellow) has been selected. The code at label LPT is executed
if the page has already been requested. If not. a jump to CLRPD is performed. CLRPD is a label within DIG ITO;
the code at CLRPD requests a new page just as if the page number had been entered manually. If the required
acquisition circuit is the one already current, then the "unstop" code is executed. This causes the green pagebeing-looked-for header to roll as though the page number had just beer:"' entered. This means that something can
be seen to happen in the case where the linked page differs only from the current page in its sub-page number.
Linked sub-pages are not fully supported in this implementation as they are rarely used by broadcasters and would
significantly increase the size of the software. When the chapter is changed the Teletext PBLF (page being looked
for) flag is checked. If it is low the FOUND flag is cleared. This forces the fetching of the links associated with
the new display page. If the page is not already in. this will automatically happen when it arrives so the FOUND
flag does not need to be cleared.
The BLUE (or cyan) key is different in that its page will not normally be immediately available (the four pages:
display. red. green and yellow occupy the four acquisition circuits and RAM chapters).
The INDEX {or black link) function is similar to BLUE except that if its link is not valid i,t defaults to the initial (index)
page number supplied by packet 8/30 (see sub-routine GIP).

6c. Subroutines:

LINK, GLP1, GLP2, SRCH, CHCK1 and NOTOKx

The sub-routine LINK allocates the three linked pages (RED. YELLOW and GREEN) to the three free acquisition
circuits (not in use by the display page). To do this it checks the page numbers in turn to see if they have already
been requested. If so they are left in their current acquisition circuit. If they have not already been requested the
page number is put into a LIFO. Only 0-9 are regarded as acceptable digits for page numbers; this is consistent
with the Spanish specification although the additional HEX numbers (A-F) may be used experimentally or by
Teletext page generators. Within this first loop the sub-routine GlP1 is used to getthe linked page numbers from
packet 27. perform a decode of the Hamming encoded data and calculate the new magazine number (page
hundreds) if different from that of the display page. GLP1 uses sub-routine SRCH to check if the page has already
been requested. If there are no links. or if links are disabled. then displayed page + 1. +2 and +3 are requested.
The second loop in LI NK allocates new page numbers to the remaining unused acquisition circuits. It uses GLP2
to clear the relevant chapters in the Teletext memory and make the new requests. Subroutine CHCK1 is used
to check whether or not an acquisition circuit is in use before it is loaded with a new page number from the LIFO.
This method of organising new page requests prevents unnecessary requests being made for pages already
requested. This is particularly important when links are disabled and pages are being requested using the" +"
or "-" functions. Under these Circumstances when the page number is incremented (or decremented) only one
new page has to be requested (new display page+31. while page. page+ 1 and page+2 do not need to change and
can be left in their current acquisition circuits.

186

NOTOK3 and NOTOK2 handle the RED and GREEN functions when links are disabled. They are disabled if the
link control bit (packet 27 bit3, byte 43) is zero or ifthere is no packet 27. These subroutines respectively increment
and decrement the current page number (units and tens). The current magazine number (page hundreds) is
not affected.

6d. Subroutines:

ROW24, W28, R28, GCYI, CUNK and DECODE

ROW24 is used to transfer ghost row 20 (packet 24) into the display chapter. This has to be done via the IIC bus.
The loop reads two bytes via the IIC (sub-routine R2B) bus from the ghost page and writes it to the display page
(sub-routine W2B). The FOUND flag is then set to indicate that the arrival of the page has been recognised and
acted upon. This sub-routine is only called by the idle loop and is used along with the other sub-routines which
get information from the ghost page (CLINK, LINK and GET25).
R2B and W2B use IIC routines READ and SEND which are outwith the Teletext module. These subroutines will
differ according to the microprocessor in use. An MC68HC05C8 implementation would need to use I/O lines (see
reference for suitable software) while the MC68HC05T7 can use its IIC hardware. The routines used in this
example are included in the listing extract from the 1V control software module (listing 1).
The sub-routine GCYI is used by LINK to store the data associated with the BLUE an INDEX links. As explained
above, these pages will not be acquired in advance, the page number only being sent to an acquisition circuit if
requested by an I R command.
CLI NK fetches the link control byte from packet 27 if the destination code is OK and, after decoding the Hamming
encoded data, transfers the bits to STAT3.
The Hamming decode sub-routine DECODE corrects for single bit errors. This is done with in-line code using the
table HAM (at the end of listing 2) as this uses less ROM than an algorithmic method.

6e. Subroutines:

MIX, TRANx, TXTx, HOLD, and NOHOLD

The mixed display capability ofthe Teletext chip (5243) is toggled using an IR key which calls the sub-routine MIX.
When mixed mode is entered, interlaced broadcast sync. (312/313) is selected because the non-interlaced sync.
used for teletext is not suitable if a 1V picture is present on the screen. This is set up via the 5243 mode register R1.
The control registers R5 and R6 are updated to provide the mixed display.
When returning to a non-mixed display, the code at NOM IX is used to re-configure the control registers and to set
up a Teletext only 312/312 non-interlaced sync. This sync. reduces adjacent line flicker in a pure Teletext display.
The subroutine TRAN2 sets up a transient which retains a black background on the top row so that the page
number, time etc. can be seen clearly. This type oftransient isalso started ifthe page number or sub-page number
is being entered in mixed mode. Sub-routines TRAN1, TRAN2 and TRAN3 are used to initialise the various
transient displays. These displays are cancelled as discussed above by actions taken within the idle loop controlled
by the free-running timer within the MC68HC05T7.
The TXTx sub-routines are used in conjunction with the IIC SEND routine to write to various sub-sets of the
registers within the 5243.
If the Teletext STOP function is requested by an IR command the routine HOLD is executed. This is a toggled
function when requested in this way. HOLD displays the word "STOP" in place of the page number and stops
the display acquisition circuit by clearing the 5243 HOLD flag accessed via its page request register R3.
NOHOLD is executed to restart the display acquisition circuit. It returns the page number to the top-left-hand
corner. If a new page number has been partially entered, a press of STOP (executing an UNHOLD) will allow a
return to the most recent page request. This takes only a single press as the start of the entry of a new page
number cause a HOLD. The completion of a page number entry (3 digits) causes a NOHOLD.

187

6f. Subroutines:

REVEAL EXPTB and TIME

The REVEAL function causes any hidden display information to appear. It is controlled by a bit in the display mode
register (R7). The software example leaves any revealed information permanently displayed. If. however, it is
required that such information disappear when the page is updated (this may be better for a quiz page), then the
two commented out lines (80 and 81) in the idle loop should be enabled.
The display expand facility is controlled by another two bits in R7. The EXPTB sub-routine cycles through normal,
top-half double height and bottom-half double height.
The example application uses a single IR key (subroutine TIME) for both the display of the Teletext clock and the
entry into sub-page mode. IF the set is in TV mode then the time is displayed for 5 seconds. If the TV is in Text
mode then sub-page mode is selected. Sub-page number entry is described in the following section. When the
Teletext clock is requested it appears (boxed) at the top-right-hand corner. It is removed by the idle loop 5 seconds
after the last press of the time button. When the time is being displayed all other Teletext activity is stopped
using UCHOlD.

69. Subroutines:

DIGITS, SUBPG, GET25 and GET26

DIGITS is the sub-page version of DIG ITO and uses similar code. More checks on the input data are required as
the four digits of the sub-page number have different maximum values. These maximums are 3 for thousands,
7 for the tens and 9 for the hundreds and units. These values reflect the sub-page number's original use as a time
(24hr format). For tens and thousands a keyed 8 becomes a 0 and a 9 becomes a 1; for thousands only 4,5,6
and 7 become 0, 1, 2 and 3 respectively.
The code at the label SETIT is the sub-page equivalent of GETIT, described above. It requests the new sub-page
and sets the FOUND flag.
The sub-routine SUBPG is called when the TIME (or clock) key is pressed (TV in Teletext mode). It toggles
between normal mode and sub-page mode. When sub-page mode is entered the page number display (P-) is
replaced with ........ to indicate the mode change and to prompt for the entry of a sub-page number. Once all four
digits have been entered the new sub-page is requested by SETIT. The code at the label RSTR is used to exit from
this mode back tothe normal (page number) mode, restoring the page number display to the top-left-hand corner.
GET25 is used by the idle loop to get the information stored in row 25 of the display chapter. This row is not
displayed but contains various information used by the control microprocessor. The current page number,
magazine number, sub-page number, Teletext control bits and the FOUND and PBlF flags are available. GET25
gets the required information and stores it in the RAM of the MC68HC05T7.
At the end of this sub-routine the I/O line 7,portB is checked. If it is low, packet 26 is handled. If it is high, this
packet is disabled. This would be required if this application were to be used in a country other than Spain which
used packet 26. It would require to be switched off as the enhanced display feature uses different characters
depending on the country. In countries which do not use packet 26 (eg the UK) it does not matter whether or not
packet 26 is enabled.
If packet 26 is enabled, GET26 processes all packet 26 data present in the ghost page. The tables G2TAB, G3TAB
and CTAB contain the characters used to replace the character at the display location defined by each packet.

188

6h. Subroutines:

GIP, R24T and SR24T

The sub-routine GIP gets the initial (index) page from packet 8130. It will be doing this as the set is brought
out of standby or just after a channel change. It may thus initially get a poor signal (or there may be no
Teletext) so it tries repeatedly until it finds a valid packet 8(.30 format 1. If this is not found after 96 tries it
gives up and sets the flag 6,STAT2 to indicate that there is no packet 8(.30 (or no Teletext). In this
circumstance it defaults to an index page number of 100.
R24Ttransfers bytes 10-30 ofthe broadcasting service data packet (8130) into the display chapter. It is called once
a second for five seconds after power-on or a channel change. The data is transferred to row 0 of the display page
which can be displayed either at the bottom or, as in this example, the top of the screen. This transient display
is setup using the sub-routine SR24T ifTeletext is present. If the flag6,STAT2 has been set by GIP as described
above then SR24T does nothing. The transient display is terminated by code executed at the appropriate time
from within the idle loop.

7. INPUT AND OUTPUTS
Apart from the IIC bus, only three pins on the controlling microprocessor are relevant to Teletext. Two inputs
select the usage of packets 26 and 27 and one output can be used to control any hardware which requires to be
changed according to whether or not there is a lV picture currently being displayed. In many applications some
or all of these functions will not be required and could be eliminated from the software thus freeing up the pins
for other uses.

PB3}
This pin is active (high) during a pure (no-mixed, no-boxed) teletext display, otherwise it is low.

PB6}
When this pin is low, Spanish use of link control bits 1, 2 and 3 is enabled. When it is high, these bits are ignored.

PB7}
Packet 26 control. When low, packet 26 is enabled and handles all the Spanish alternate characters which are
available in the 5243. When PB7 is high, packet 26 is ignored.

8. REFERENCES
Application note AN446, MCM2814 Gang-programmer using an MC68HC05B6.

189

USTING 1

.........................................................
........................................................

3.

31

Idle loop.

'2

,."

l5
36 00000000

Od13fd
37 0(1000003 >JeDD

ILP

INC

J.'

olD 00000009 >cdOOOO

41 OOCOOOOe

03010.

U DODOOOOt >1600
43 00000011 20St
44 00000013 >070009

45 00000016 >1100
46 00000018 >lSon
.f7 0000001. >lfOD
48 DaOOOOle >cdOOOO
U COOODOl! >cdOOOD

BReLR
BSBT

roN

ALAON

sO 00000022 >02004d
51 00000025 >D20Ch
52 00000'021 >OeOO",'
53 0000002b >040044
54 0000002e >Oa0041

55 00000031 >06003.
56
57
5.
59
60
61
62

00000034
00000037
0000003.
0000003e

>Qc003b
>Ofooes
>lfOO
>cdoaoo

OODOODl! >OIOOle
00000042 >b60D
00000044 a130

63 00000046

DNTRS

LOA

64 00000041 >cdOODO
65 0000004b >cdOO-oO
'6 00000048 >cdOOOO
00000G51 >cdOOOD
, . 00000054 >090005
69 00000057 >ObOOOZ'
70 0000005. ad6.
>b60D
>blOC
aiOI
>b100
ai19
>cdOOOO
>080104
>1000

JSR
JS.
JS,
BRCLR
BReLR

NCUP
N024

00

81
12 00000010 >3fOO

....'7
.'0

83 00000012 >04001b
14 00000015 >0600 ...
IS 00000018 >090015

BReLA
BeLA
BeLA
BeLA
JS'
JS'
BRSET
BRSET
BRSET
B.SET
BRSET
BRSET
BRSET
BReLR
BeLA
JS'
BReLR
BLO
JS'

n

72 0000005.
73 00000060
14' 00000062
15 00000064
" 00000066
" 00000068
18 0000006b
'9 00000068

BRA

CMP

252.

n OOOOOOS<=. >1100

BRCI.R
INC

IN<:

3. 00000005 )oleOD
39 00000007 >leOO

Fl

...

BeLA
LOA
STA
LOA
STA
LDA
JS.
BRSET
BSET
BeLA
JS'
eLA
BRSET
BRUT
BReLA

OUTPUT COMPARE FLAG
nLlTBXT TRANSIENT
ROIl' 24 DELAY

6.TSR.·

eNTl
CIIT.
CNT'S
XBD
1.PORTB.FON
J.STAT2
F1
3, STAT2.ALRON
3,STAT2
2.STA"r2
7,.STATS
RES'l'RT
VCRPOLL
1, STAT2,Fl
l,STAT4,Fl
" S'l'AT7,Fl
2,STAT2,Fl
S,STAT,Fl
3,STAT4.Fl
',STAT4,F1
7. STATS, DNTRS
7,STATS
ST.\R1'2
0, STAT2, N024
CNT4

MUTE TRANS IBN'

RYBOAR.D .. TIMERS
STANDBY 1
MAKB SURE FLAG AGREES
AND lOLl WITH NO IIC ACTIVITY
NO, JUST ON 1
YES, RUTART
CLEAR THIS FLAG ALSO 1
RE-INITIALlSA'l'ION NOT NECESSARY
POLL SCART LINES
REMOTE REPEATING 1
LOCAL REPEATING ?
TELETEX'!' CHIP ON BUS ?
SEARCH/STANDBY ?
TIME DISPLAY HOLD
TRANSIENT MUTE ?
COINCIDENCIS MUTE ?
TO BE RE-ITIALISED ?
YES, CLEAR FLAG ..
RE-INITIALISE TELETEXT
PAUSE WHILE PACKET 24
(PAGE EXT. I ARRIVES

•••

F1
CLINJ(
LINK

RON24
GET2S
4, STAT2,Jl'OUP
5,STAT2.NOUP
MRVD
O,STAT2

CHECK LINK CONTROL BYTE
FETCH LINKS
nTCH ROM 24 AND SET FOUNDB
GET ROIl 25 .. PACKET 26
UPDATE ENABLED ?
DIFFERENC!S .,

.

ACe
RI

COLUMN 8 (FOUNDB" pau)

RIO

125
.2B
4,IOBUF+1,Fl
O,STAT2
S.R7
TXT2
CNT4
2,STAT2,ILP
3.5TAT2,ILP
4. STAT, ILl

"'"'

FOUNDB FLAG SET .,
NO, so FETCH GHOST ROIl'S
J:ILL REVEAL

SEARCHING?
STANDBY 1
TRANSIENT 1

Transient control •

91

.2

LOA

93 0000001b >b600

94
95
9'
"
'8
99
100
101
102
103
104

0000001d
0000001f
00000081
00000084
00000086
00000018
OOOOOOIa
OOOOOOld
0000001f
000000'1
00000093

alSO
2403
>ccOOOO
>b600
alOt
2603
>cdOOOO
>3f00

NILP

tlO
NIL>
IL>
R4

JMP
LOA
CMP

BNE
NOTE

>3~00

2103
>ccOOOO

YES

CNTl

CMP

BHS

1S TIMER

••

BEQ
JMP

DRILP

IF" PAGE 4 THEN IT'S
THE 1/30 TRANSIENT
CLEAR 15 TIMER
DECREMENT SECONDS COUNTER
TRANSIENT FINISHED 1

JSR
JMP

OaDLE

OSD TIMEOUT (INC RSTKO)

JSR
CLR.

NOTE
R24T
CNTl

DEC

TMR

ILP

NO

105
106 00000096 >cdOOOO
101 000000" >ccOOOO

DNILP

10'
10.
110
111
112
113
114
115
11.
117

End Taletext transients.

Clear mode bits (channel mode, 2-diqit
proq. no. entry etc.)

118 0000009c >010003
119 OOOOOO'f >cdOOOO
120 000000a2 >1500

121
122 000000." >1900
123
124
125
126
121
121
129
130
131
132
133
134
135
136
131

ILP

000000a6 >1900
000000a8 >ObOOll
OOOOOOab >lbOO
OOOOOO~d
d03
OOOOOO~f >b100
OOOOOOb1 >b100
OOOOOOb3 >cdOOOO
OOOOOOb6 >040003
000000b9 >cdOOOO
OOOOOObc >1100
OOOOOObe >000006
000000c1 >b600
000000c3 >b100
000000c5 >3fOO
OOOOOOc7 >ccOOOO

RSTHO
S052
RSTH02
RSTH03

BReLR
JSR
BCLR

0, STATS,SOS2
RES
2,STAT4

2-DIGIT Pr. No. ENTRY 1
YES, RESTORE DISP
MAKE SURE ITS PROGRAM MOD!

BeLR
BeLR
BRCLR
BeLA

4,STAT4
4. STAT
S,STAT.TXTRl
S. STAT
UOJ
R5

RESET CSD TRANSIENT FLAG
RESET MAIN TRAJI'SI!NT FLAG
TIME HOLD ?
YES, CLEAR IT

TXT2
2, STAT, TXTRl
NOTTH
O,R7
0, STAT, TXTR2
Ace
R4
R7
TXT2

STOP TIME EXIT FLASH
OTHER HOLD 1
NO, SO CLEAR HOLD
BOX OFP ROW 0
TELETEXT 'I

LDA

TXTRl

TXTR2

STA
STA
JSR
BRSET
JSR
BeLR
BRSET
LDA
STA
eLR
JMP

••

190

NO, ALL BOXES orF
YES

13.
140
141
142
143
144
14 5 OOOOOOca >b600

..........................................................
Updated paV. ha. arrived.
.......................................................... II.a •••••••

AARVD

loll ODOOOOcc >b100
149 DOOODOd2

"

150 DOOOOOd) >cdOOOO
lSI DQOOOOd' >OcOOO5
152 DOOODOd' al06
153 OOOOOOdb >cdOOQD
154 DOOOOOd•
.&46

LOA

JS.
SPHD

155 000000.0 >b70Q
156 000000.2 >b100
157 000000... d03
lSI 00000086 >050002
159 000000.' d02
160 OOOOOOeb >b100
161 OOOOOOed >ccOOOO
,.2
163
164 OOOOOOfO dID
165 000000(2 >b100

•••
REStRT

LOA

STA

JMP

ACe

••

f.. STAT
S.ST"T

."oil
..••

aoxoOH
'.STAT.SPND

aoxoar

"03
2.C3.HNF
1$02

.,

.,IUD

OOOOOO!.. >3!00
OOOOOO!c >edOOOO

TXT2

SWITCH PICTURIt ON

OOOOOO!! 013e03
00000102 >lcOO
00000104 U

BRCLR
as.T
.TS

O.MSR.ACKOK
6.STAT7

ACKNOII'LItDGE "I
NO. SET FLAG

BROADCAST SYNC.

••••
R7

AC_

JMP

INI1'XT

'ES

LOA

P.OG
DISP
0.STAT5

00000101 >b600
0000010 .. >b700
0000010c >1100
0000010e 11

,..

11.

116
117

STA

ac ...

YES. RESTORE PROG. NO.

........................................................
........................................................
ASS

.TS

lIC write.

,.1

190
191
192
193
194
US

0000010!

197
191
199
200
201
202
203
204
205
206
207
20.
209
210
211
212
213
2"
215
216
217
211
219
220
221
222
223
224
2"
226
221
22.
229

000001U >b600
0000011b a1l0
0000011d 2606
000001lf >b600
00000121 a.dlb
00000123 >3eOO

".

nWSrLASH 2
YES. NO ROlf 0

f.

'"
""

11'

SUB-PACE MODE 2
NO. SMALL BOX

TXT2

176 00000105 >ceOOOO
179
110
111
112
,.3

KILL TRANSIENTS

LOA
STA
LOA
STA
ITA
e1.O
JS.

161 DQDOQOn >b100

,,.

LOA

ITA
• TA
LOA
BlteLR

166 000000(4 d06
167 oooooon >b100
169
170
171
172
173
174

LOA

STA
BCLR
BCLR
eLOA
JS.
BRSlT

14'1 OOOOOOce >UOO
141 OOOOOOdO >lbOO

ad23

SitKO

00000111 >b!OO
00000113 >1100
00000115 >b600
00000117 .d25

00000125 >beOO
00000127 to
00000121 .. d14
0000012 .. >3cOO
0000012e >3.00
0000012. 26e9

as.

IICSU

...

DPNT
O,ADDR
ADD.
SHIFT

LOA

ADD.
1$10

STERECTON! "I

SUJMJ)R
SHIFT
SUMDR

YBS. SO !NABLE AUTO
SUB-ADDRESS INCREMENTING

DPNT
0,'
SHIFT
DINT
W1

SEND DATA

STX

ac ...
LOA

IIR.U

CMP

&NE
LOA

as.

I.e

IIR.

LDX
LDA

as.

I.e
DEC
&NO

00000130
00000132
00000133

11

00000114
00000135
00000137
00000139
OOOOO13b
0000013d

.b
3!3c
3!3a
.. 6bO
b73b
11

lICSU

0000013e
00000140
00000143

b73d
0!3c!d
11

SHIFT

00000144 adc9
00000146 al02
00000148 >cdOOOO

WRITE

1b3b

BeLR
eLI
.T.

••

.BI
CL.
CLR
LOA
STA
RTS
STA
aRe1.O
RTS

as.

LOA
JS.

...a

SAW X
SET-UP TO WRITE
SEND CHIP ADDRESS

DATA BUFFER POINTER

"".U

DONE "I

5.MCR

STOP

...

IIC SET-UP
90 KHz
ENABLE IIC AS MASTER
TRANSMITTER , START

MSR

UBO

NC.

MD.

7,MSR, •

SEND
'2
TPAU

WAIT 10rnS (EEPROM WRITE)

191

.: j~l

231
232
233

234
:35
236
23"
238
239
240
241
2<102

'0
244

0000014b
OODOOHd
OODOOIH
0000.0151
00000153
0000.0155
00000151

adOc
:>b600
:>b701
>b600
alaI
26.02
)oJeOO

00000159 add'
245 000.o01Sb >110.0
246 000C')l5d,:>b6o.0
241 OODOCIS! addd
248 00000161 >b600
249 00.00.0163 adel'
H.o .00000165 1b3b

B.R
LOA
STA

LOA
CMP

....
READ.

READ.
IOBUF
I08UF+l
ADDR

GET FIRST BYTE
"MOVE IT UP

..,AI
READ •

NVM ?

INC

SUBADR

YES, NEXT SUB-ADDRESS

BSR
BeL>
LOA
BSR
LOA
BSR
BeLR

IIC5U
C,ADDR
ADDR
SHIFT
SUMDR
SHIFT
S,HCR

SEND CHIP-ADDRESS

SEND SUB-ADDRESS
NO STOP 8UT

BSET
BSET
LOA
BSR
BeLR
BSET
LDA

S,MeR
O.ADeR

A RESTART
SET BIT 0 FOR READ

ADDR
SHIFT
4,HCR
J,HCR
MDR

RE-SEND CHIP ADDRESS
CHANGE TO RECEIVER
SWITCH OFF ACIC.
INITIATE RECEPTION

BRCL>
BSET
LOA
STA

MDR
IOBUF+l

RW .. .0 ALWAYS WRITE (SUB-ADDRESS)

211

252 00000161
laJb
253 .00000169 :>10-0.0
254 OOC-OC16b >b6CO
2SS 0000016d -ade!
.2 56 OOOOOU! UJb
257 .00.0.00111
16lb
~ S8 0000.0173
bUd

219

2"
26:'
262
263

7,MSR,3.NeR

WAIT FOR IT
SECOND LAST SO SWITCH OFF ACK.
GET FIRST BYTE
AND SAVE IT

264
265
266
261
268
269
21.0
211

00000175 O!3c!d
0000.0178
Ib3b
00.00011. bUd
OOD0011c :>b7.o.o
OCOO.o11e 9a
.o.oOO.ol7f 81

BRCLR
BCLR
LOA
STA
CLI
RTS

1,MSR.S,MCR
MDR
IOBur

WAIT rOR IT
LAST B'tT!. SO STOP
GET BYTE
AND SAVE IT

272
273

ItC interrupt.

274
275
2"

'""
;:~8

~;C~C:IO

r~

~::OCC:12

3!3c
10

MBINT
RETURN

CLR
RTI

MSR

192

LISTING 2
1

2
3

TV/Teletext/OSD/Stereo pro9ram (MC68HCOST7).

7

Used with RAMT8.S0S. OST.50S , TMT7.S0S

•,
•
••

CCT Teletext control module (spain).

10

.. This software va. developed by Motorola Ltd. for demonstration purposes.
.. No l1.a.bllity can be accepted for its use 1n any specific application.

tl

ori9in.al softw.are copyright Hotorola - all rights reserved.

12
13

,.""

P. Topping

19th October '90

EXPORT
EXPORT
EXPORT

DIGITO,RED,GREEN, YELLOIf, CYAN
NPAGE, PPAGE, REVEAL, EXPTS, UPDATE, TVTX, GIP
TIME, MIX, INDEX, HOLD, SR24T. START2. INITXT

EXPORT
EXPORT

CLINK, LINK, ROW24. GET2S. R2B, TXT2
R24T,NOTTH,80XOON,BOXOOF

2'

IMPORT

SEND, READ, OSDLE. TPAU2

27
27
27
27
27
27
27
27
27
27
27
27
27
27

LIS

RAMT8. 50S

17

18
19
20
21

22
23

"2.

RAM

allocation for OST.SOS. TMT1.S0S ,

TXT7.S0S.

SECTION.S . RAM. COKM

Equates.

27
27

27
27
27
27
27
21
27
21

00000000
00000001
00000002
00000003
00000004
00000005
00000006
00000007

_OU
EOU
EOU
EOU
EOU
EOU
EOU
EOU

$00
$01
$02
$03
$0'
$0'
$0.
$07

Port A address
Port B
"Port C
Port 0
Port A data direction reg.
Port S . .
..
..
Port C
Port ·0

DDRS
oORC
DORD

27 00000008
27 00000009

LE01
LE02

27
27
27
27
27
27

ODOOOOOa

LEo3

EOU
EQU
EQU

$0'
$0'
$OA

OIA 0
DIA 1
OIA 2

OOOOOOOb
OOOODOOc
OOOOQOQd

27 OOOOOOOe

·VOLU
CaNT
BRILL
SATU
VOLU

EOU
EOU
EOU
EQU
EQU

$OA
$0.
'OC
$00
$OE

O/A
D/A
CIA
CIA
O/A

27
27 00000012
27 00000013

TCR
TSR

EOU
EOU
EOU
EQU
EOU
EQU
EQU
EQU
EQU

PORTA
PORTS
PORTC
PORTO
DORA

27

27
27
27
27
27
27

00000014
00000015
00000016
00000017
00000018
00000019

27 OOOOOOlc

ICRH
ICRL
OCRH
oeRL

TDRH
TORL
MIse

2
3

4
5

STEREO LED
BILINGUAL LED
FM -1- MICAM LED
JP08
JPQ9
JPIO
JPll

IN
IN
IN
IN

Tl
Tl
Tl
Tl

Eva
Eva
Eva
EVB

6

ii=:~ ~~~~~:l r!:I;:;~~'

$12
$13
$14
$1.
$17
$1'
$19
$lC

Input capture register. high..
Input capture register. low.
OUtput compare register. high.
output compare register, low.
Timer data register. high.
Timer data register. low.
Misc. register

$20
$32
$33
$34
$3'
$3.
$37

18 050 data registers
Color , status register
Color 3/4 register
ROW address' character size
WindOW/Column register
Column/color register
Horizontal position delay

$1'

27

27 00000020
27 00000032
27 00000033

OSO
CAS
C34

21 00000034

ItAD

27 00000035
21 00000036
21 00000031

WCR
CCR
HPO

EQU
EOU
EOU
EOU
EOU
EOU
EOU

MADR
FOR
MCR
MSR
MDR

EOU
EQU
EQU
EQU
EQU

$39
$3A
$3.
$3C
$30

TR1
TR2

EQU
EQU

$3E

Test 1, 05C/Timer/PLM

$3F

Test 2,

27

21 00000039
27 OODOOD3a

27 OOOOOOJb

21 0000003c
27 0000003d
27

21 0000003e
27 DOOOOD3!

193

EPROM

27
27
27
27
27
27

Teletext RAM allocation.

27 00000000

27 00000001
27 00000002
27 00000003

27 00000004
27 00000005
2700000006

27 00000007

.,

SUSI

.2

.3

C1
C2
C3
C.
C,
C6
sUe2

27 ODOOODOc

..

27 OOOOOOOd
2? OOOOOOOe

.7

2700000008
2700000009
27 QCOODOOa
27 OOOOOOOb

27

DeOODCO!

27 00000010

2700000011
2700000012
2700000013
27 00000014

2700000015
27 00000016
2700000017

2700000020
2700000027
27 0000002a
27 OQ00002d
2700000030

R5
.6

..".,0••

SUBJ

PH

pr

PU

LIFO
PAGE
PAGO
PAGI
PAG2
PAG3

27 ooooa033

PAGe

27 00000036
27 00000039
27 0000003a

PAGI

27 0000003e
27 aOOOOD)!

2700000040
2700000041
27 00000042

27 00000046

PDP

27 oaOOOQ·lc
:1.7 oooonC4d

display
display.
display
display
active
active
active
active
2nd

RMB
RHB
RK8
RMB
RMB
RMB
RMB
RK8
RMB
RMB

3r.
'th

LINKED PAGE No. LIFO BUFFER
PAGE No. INPUT BUFFER
ACO PAGE No.
ACl PAGE No.
}>'C2 P}>'GE No.
AC3 PAGE No.
CYAN PAGE No.
INDEX PAGE No.
P}>.GE DIGIT POINTER
DISP, REO, GREEN, YELLOW ItC. eIR.
WORKING ACe No.
IIC ADDRESS
I Ie DATA POINTER FOR WRITE
IIC SUB-ADDRESS
lIe BUFFER, +2 , +3 RSRVD FOR PLL
0: R:}W24 FETCH FLAG
1: REMOTE REPEATING
2: SEARCH/STANDBY IIC LOCI(
3: STANDBY STATUS
4; UPDATE PENDING
5: DIFFERENCE FOUND
6: NO TELETEXT TRMlSMISSION
7: MIXED

RMB

RMB
RMB
Rl'.B
RMB

RJIB

. .

.

IR TIME DIFFERENCE

RMB
RMB

IR CODE BIT
COLLECTION

....
"'"
RKB

RMB
RMB

194

21
21
2'
2·/
21
2?

RAM allocation for Stereoton.

27 0000006c
21 OQOOQ06d
27 0000006e

27
21
27
27
27

0000006f
00000010
00000071
00000072

SHADMAT
LBAL
SNDHD
ABAV

TEMPORARY

RMB
RMB
RMB
RMB

kl

RMB

LVI.
LVR

~TRIX

Loudspeaker bal.ince variable
SOUND MODE 0:5T,

1:0". 2:D8,

SCART SOUND MODE 0: STEREO,

3:W, 4:M.

1: DUAL A.

In level

(req 0)

Loudspeaker left volume

(reg 1)
(req 2)

00000074
00000075
00000076
00000011

HVR

RMB
RMB
RMB
RMB

TONE
MATRIX

RMB
RMB

Current matrix

(req 5)
(req 6)

.2

RHB

K2 level

(req 1)

00000078

STATS

RMB

27 00000073

HVL

27
27
27
27
21
21
27
21
21
21
21
21
21
21
21
27
21
21
21
21
21
21
21
21

Loudspeaker right volume
Headphone volume left
Headphone volume right
Tone v.;r,riable (Bass/Treble)

(req J)
(req 41

0: 2-DIGIT PROGRAM ENTRY
1: ANY HUTE REQUIRED?

2:

aso

NIIME TABLE

3: aso DEFAULT pIc NUMBER
t: ANALOGUE aso ON
5: NAME-TABLE STANDARD
6: STANDARD CHANGED

7: AE-INITIALISE TELETEXT
00000079

STAT6

0: AV MODE BIT 0
1: AV MODE. BIT 1

RMB

(O:TV, 1 :S-VHS)
(2:SCRTl, 3:SCADT11

.,
2,

3,

5,
6:

7

21 aOOOOO7a

STAT?

RMB

=

SCAAT INPUT .1
SCART INPUT .2

0; AV MOD!'; CHANGE
1 = FORCE FM SOUND
C~ : T8LETEXT NEWSFLASH
3: C6 : TELE'!,:".:nd c;olwnn
ROW 6, colour 1"! & ~'ut] ine enable

'MS

.....
RMB

"ROW 5,

RMB

RMB
RMB
RMB

Row atjdlE:::Ol> ')

:il;,r;).C'tel

s.i ze

Window colour • 000031

TVTX

31 00000003 >OcOO74

TXTON

Teletext/TV .v1tchinq.
• • • • • • • • • • • • 111 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

39 00000006 >10-00
40 00000001 >cdOOOO
41 OOOOOOOb

.616

42 DOaOODOd >b100

43 0000000: >1900

44 00000011 >1900
45 00000013 >1fOQ
U DODDoalS >ObOOOI
47
48
49
SO

00000011 >lbOO
0000001. >040003
OOOOOOld >cdOOOO
00000020 a6cc

NOTT

51 00000022 >b700
52 00000024 _646
53 0000002& >b700
54
55
56
51
51
S9
60
61
6.2
6J
64
65
66
61
68
69
10

n

12
73
74
15
7i
11
,.
19
8081
'2
.)
.4
'5
.6
17
81
89-

90
91
92
93
94
95

00000028 >b600
0000002-. >b700
00000D2e >ceOOOO
0000002!
00000032
00000034
00000031
0000003a
0000003c
000000l!
00000041
00000043
00000045
00000041
00000049
00000D4b
0000004d
OOOOOOH
oOOOOOSl
00000054
00000056

>OcOO41
>1100
>090003
>edOOOO
>1100
>cdOOOO
>1100
4610
>b'700
>1900
>lbOO
4603
>b700
>b700
>3!00
>cdOOOO
.1.602
>ccOOOO

00000059
0000005b
0000005d
OOOOOOS!
00000061
000000.63
00000065
00000067
00000069
0000006b
0000006d
0OOOO06!
00:0000'71
00000073
00000075
00000077
00000079
0000007 •
00OOO01b

>e602
a139
221b
.130
2517
>e601
8600
a1l7
2207
a130
2503
>b700
II

.
II

UPDATE

BRSET
BRSET
asET
JO,
LDA
OTA
BeLR
BeLR
BeLR
DReLR
BeLR

BRIET
J.'
LDA
.TA
LOA
OTA
LOA
• TA
JMP

BRSET
. .IT

BRCLR
TXTOyr
TXTOF

OST

TEST

J ••
BeLR
JO,
BCLR
LOA
OTA
BeLR.
BeLR
LDA
OTA
'TA
eLR
J.,
LOA
JMP
LDA
eMP

&HI
eHP
Bto
LDA
CHP

&HI
eHP
Bto
LOA
eMP

&HI

ABC

PAMIC

eHP
Bto
OTA
'T'
.Ie
'TO

0, STAT, TXTOFF
6. STAT1, PANIC
0, STAT

TELETEXT CHIP ON BUS 1
TELETEXT MODE

OSDLE

CCT. 312/312 SYNC
ENABLING GHOST ROWS
ABORT TRANSIENTS
lULL UPDATSS
NOT MIXED

1$16
R1
4, STAT
4,STAT2
',STAT2

5. 51'''1, N01'T
5, STAT
2, STAT, lfOTT
NOTTH

uce

,S
f$46

,.

ACe

••

TRAIl'

6, STAT1, PANIC
4 .. STA12
4, STAT, lXTOf'
NOTTH
O,STAT

TELETEXT CHIP '1
UPDATE ON
TRANSIENT HOLD '1
YES, RESTART
TV MODE

OSC ...
O,ST1.T
t$10

TV MODE
BROADCAST, 312/313 SYNC
ENABLING GHOST ROlfS
ABORT TRANSIENTS
ABORT TIME TIMEOUT
,06 FOR TRANSIENTS

".,STAT
5, STAT
t$03

.s

.6

,7

TXT2
f2
,PH
PAGO+2,X
f$39
PNnc
1$30
PANIC
PAGO+1,X

'U9

PANIC
f$30
PANIC
PAGO,X
1$37
PANIC
f$30
PANIC
PAGE
OK .. CARRY CLIAR
NOT OK, CARRY SET

196

·7

••••

100
101
102
103
104
105
106
101
108
109
110
III
112
113
114
115
116
11 7
lla
119
120
121
122
123
124
125
126

NWIlber entry routines .

OOOOOO'c >OdDeD3
0000001! >ccOOOO

DIGITO

00000082 >1700
00000084 >b6DD

DIGIT

LOA

00000016 >cdOOQO

00000019

JSR

dOt

LOA

0000008b >cdOOOD

0000008. >1400
.00000090 >b600
00000092 a010
00000094 >beDD
00000096 2606

00000091
0000009a

al01
2302

OD00009c

aOOa

00000098 abJO
00000040 >e100
000000a2 4302
000000&4

270e

00000046
00000048

a62d
a301

OOOOOOaa
2102
OOOODOac >bJOl
OOOOOOa8 >b702

LDO

NOCH

TEN

127 OOOOOObO >JeDD

128
129
130
131
132
133
134
135
136
137
138
139
140
141

142
143

144
145
146

141
148
149
150

OOOOOOb2
QOOOOOb4
QOOOOOb6
OOOOOOb8
DaDOOOba
QOOOOObc
OOOOOObe
OOOOOOcO
OOOOOOc2
OOOOOOe4
OOOOOOc6
OOOOOOcB
OOOOOOea
OOOODOcc
OOOOOOce
OOOOOOdO
000000d3
000000d6
000000d8
OOOOOOd...
OOOOOOdc
OOOOOOd!
000000e1

2002
>3[00
>b600
>b100
>3fOO
a602
>b700
4650
>b100
>b6DD
>b700
>biOI
>b100
>b602
>b100
>cdOOOO
>cdOOOO
>b600
2Ei9!
a606
>cdOOOO
>b600
>b700

BRCLR
JMP
BeLR

CLRPD
OPGN

JSR
BSET
LOA
SUB
LOX

....

CMP
BLS
SUB
ADD
ST.
CPX
B'e
LD.
CPX
.Ee
ST.
ST.
INC
B"
CLR
LO.
ST.
CLR
LOA
ST.
LOA
STA
LO,
STA
LD'
ST.
LO.
STA
JSR
JSR
LOA
B••
LOA
JSR

LO.

ST.

',STAT, DIGIT
DIGITS
l,R3
ACC
UP

HOLD DURING
ENTRY

SPM
2, STAT

SET HOLD FLAG

.

W2
fl.
PDP
NOCH

NOT HUNDREDS SO DON'T CHANGE
YES, MORE THAN 1 '1
NO, SO DON'T CHANGE
'rES, 8->0 , 9->1
CONVERT TO ASCII

t7
NOCH

fI
t$30
PAGE,X

UNITS?

'2.

YES, SO CLEAR PDP
DASH
TENS?
YES, SO LEAVE TENS
CLEAR TENS
CLEAR UNITS

CLRPD

'$20
fl
TEN
PAGE+1
PAGEi-2
PDP
OPGN
PDP
R'
R8
R'

ROW 0

'2

COLUMN 2
P

R10
1$50
Rll
PAGE
PH
PAGEi-l
PT
PAGE+2
PU
TXT)8
TRAJcdOOOO
2545
... d23
>b600
:>e700
:>b601
>e701
>b700
>b602
:>e102
>b100
:>b600
a018
>b700
>b600
>cdOOOO
>cdOOOO
:>1500
>ceOOOO

GET!T

JS'
BLO
BS.
LDA
ST.
LD.
STA
ST'
LD.
ST.
STA
LD'
SUB
STA
LOA
JS'
JS'
BCLR
JMP

SRCH
LP'1'2
INDX
PAGE
PAGO,X
PAGE+1
PAGO+1,X
C1
PAGE+2
PAGO+2, X
C2
PAGE

'$18
.3

IS PAGE ALREADY IN "?
YES
DISPLAY CHAPTER
PAGE HUNDREDS
SAVE IN RAM
PAGE TENS
SAVE IN RAM
PAGE REQUEST TENS
PAGE UNITS
SAVE IN RAM
PAGE REQUEST UNITS
PAGE HUNDREDS
PAGE REQUEST HUNDREDS

.4
UP
TXT1
2, STAT
SFNO

REQUEST IT
RESET HOLD FLAG
WRITE ONE '1'0 FOUND

117
178
179
180
181
182
183

0000010d >b600
OOOOOIO! 48
00000110 >bbOO
00000112
91
00000113
81

INDX

LD'
LSLA
ADD
TAX

YIP

ACC
x2
x3

'CC

RTS

18.
185
186
181
. 188
189
190

00000114
48
00000115
48
00000116 48
00000111
48
00000118 >b700
0000011a
81

UP

LSLA
LSLA
LSLA

LSLA
ST.
'TS

.2

197

............. ................".. .. ..... .......".....

..

"

,,,.3
192

" "

""

Red, Green , Yallow key ••

190
197

198 OOOOOllb >3(00
199 OOOOOlld >06000b

RED

CLR

BRSET

3,STAT3,RED2

NPAGE

JSR
JSR
BLO
JMP
LD/.

PDP

INDXP
MOTOK3

LINKS ON ?

200

201 00000120 >cdOOOQ
202 00000123 >cdOOOO
203 00000126

Z52c

204 00000121 >ccOOOO
205
206
207
20.
209

NO. SO FORC! AN INCREMENT
ALREADY REQUBSTED ?
NO. GETIT

LPT
CLRPD

0000012b >b60r
DOOD012d 2025

LPT2

BRA

LPT

DOOOOl2! 'lo3t'OD

GREBN'

CLR
BRSBT

PDP

!'PAGE

JSR
JSR
BID
JMP

INDXP

215 OOODOllf OcOlO]
216 00000142 >010061

GLO'

BRSET

217 OOOOOlU >b602
218 00000141 zoeb
21.

IGO

BRCLR
LDA

CLRPD
',PORTS,IGO
O.STATl,ABC
ACC+2

BRA

LPT

220 00000149 >01005.

YELLOW

BRCLR

3,STATl,ABC
6, PORTB, IG1
1, STAT3~A8C
ACC+l

RED2

00000131 >06000b

210
211 00000134 >cdOQDO

212 00000137 >cdOOOO
213 0000013a 2511
214 0000013c >ccOOOO

221 0000014c

BRSIT

OcOl03

222 OODOOH! >030054
223 00000152 >b603

224 00000154 >b100
225 00000156 U

IGl
LPT

226 00000157 'lobbOD

227 00000159 97
228 0000015. >cdOODO
229 0000015d

ZS47

230 DOOOOlS! >b600
231 00000161 >blOO
232
233
234
235
236
237
238

00000163
00000165
00000167
00000169
OOODOtic
OaDOOU!
0000(1112

239 00000174
240
241
242
243
2t4
2&5
2&6
247
2&8

2"
2"

00000177
0000017.
0000017c
0000017e
00000180
00000182
00000184
00000187
00000119

2604
>1400
2009
>OdOOOJ
>cdOOOO
>cdOODO
>3fDa
>050003
:>cdOOOO
dO!
>b700
>b600
>b700
>b700
>cdOOOO
>1500
>ccOOClO

NTSAC
SKOSP
CARO
COR

HOTHLD

aRCLR
LOA
STA
LSLA
ADD
TAX
J.O
BCS
LDA
CMP
BHE
BSET

"0

.3

NO, SO FORCE A DECUMENT
ALREADY REQUESTED 1
NO, GETIT
CYC BITS ENABLED ?
GREEN LIB ON 1

LINKS ON ?
GYC BITS ENABLED?
YELLOW LINkS ON ?

IS PAGE NO. OX ?
IF NOT ABORT
ACC No
IF SAME ACC CCT
THEN FORCE UNSTOP

ABC

.3
ACC

NTSAC
2,STAT
CARO

JSR
LDA
STA
LOA
STA
STA
JSR
BCLR

?

X3 FOR PAGE POINTER

TEST

6, STAT, SKOSP
OUTSP
RSTR

BRCLR

OM

.2

.3

BRA

SUB-PAGE MODE 1
YES, ABANDON IT
PUT PAGE No. BACK

PDP

2,STAT,NOTHLD
NOHOLD

I$or

IF OLD PAGE ON HOLD
CANCEL HOLD
CORRUPT C6 FOR UPDATE

CO

.3
R4
ACC
CFHD

CHECK paL!", IF HIGH DO NOTHING
IF LOll (PAGE FOUND) CLEAR FOUNDB
TO FORCE FETCHING OF LINKS~

2, STAT
TXT2

IndOll(, ,

Cyan key ••

." .. " •••••• "* ••••••• " ••• " ••• " ••••••• "",, ••••••••• ,, •••• ,," ••

2.5

270
211
272
273
274
27S
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295

N0T0JI2
LPT

LINItS

................ " ••• " ••••• *" •• "."."" •• * •• " ........... " •••••

2"
25'
25<

2.'
269

3,STATl,GLOK

aRCLR
JSO
JSO
CLR

JMp

2"

256
257
258
259
260
261
262
263
2Ei4
26S
266
267

ACC+1

0000018c uO!
0000018e >cdOOOO
00000191 2414
00000193 >ccOOOO

INDEX

00000196 >01000d
00000199 Oc0103
0000019c >050007
OaOOaU! aeOc
OOOOOlal >cdOOOO
000001.4 2401
000001.6 11

CY,",

000001a7
OOOOOld
000001.b
000001.d
OOOOOla!
000001b1
000001b3
OOOOOlbS
OOOOOlb7
000001b9
000001bb
OOOOOlbd
OOOOOlb(
OOOOOlc2
00000le4
OOOOOlc6
OOOOOle'
OOODOle.
OOOOOlee
OOOOOlce
OOOOOldO
00000ld2
OOOOOldS
OOOOOld1
00000ld9
000001db
OOOOOldd

>ldOO
>3(00
>8602
>b700
>b700
>8601
>b700
>b700
>e600
>b700
.011
>b700
>cdOOOO
>b600
>.700
>b600
>e701
>))600
>e102
>))600
>b700
>edOOOO
a650
>b700
>3fOO

IG2

TEST

JMP

lAC
GIP

BRCLR
BRSET
BRCLR
LOX
JSR

ace

ABC

"TS

lAC

BeLR
CLK
LOA
STA

STA
LOA
STA
STA
LDA
STA
SUB
STA
JSR
LOA
STA
LOA
STA
LOA
STA
LOA
STA
JSO
LOA
STA
CLR
LOA
STA

.&02
>b700

297 OOOOOld! >1500
298 000001e1 >cdOOOO
299 000001e4 >cdOOOO
300 000001e7 >cdOOaO
301 000001ea >ceOOOO

CYOK

U.

LOX
JSK

ace

BeLR
JSO
J.O
J.O
JMP

3.STATl,ABC
6, PORTB, IG2
2, STATl, ABC

LINKS ON ?
GYC BITS ENItBLED ?
CYAN LINK ON ?

'12

TEST
lAC

6, STAT

RESET PAGE MODE

PDP

PAGO+2,X
PU
C2

PAGO+l, X
PT
C1

PAGO,X
PH

tU8

03
INDX
PH

PAGO,X
PT

PAGO+l,X
PU

PAGO+2,X
ACC
O.
UP

USO
OIl
R'

"

RIO

2,ST.\T
TXT38

RESET HOLD FLAG

TRAHl

DISPLAY TOP ROM
SET FOUNDB

SFaD
TXTl

198

303
30.
30.
300
307
301
309 DOOOOled >b600

310
311
312
313
314
315
316
311
311
319

GOODOle!
OOOOOltl
000001(3
OOOOOltS
GOaDOH1
OOOOOlU
OOOOOlfb
OOOOOUd
OOOOOlU
00000201

LUI"

>3tOO

aiOl
>b100
.. iff
>b101
>b102
>b103
>cdOOOO

320 00000204 >3cOO
321 00000206 >b600

LOA

STA

LLOP

322 0000020' >b100
323 0000020... adU
324 Q000020c

2406

325 0000020. >beOO
326 00000210 >.,00
321 00000212 2003
321 00000214 >cdOQOO

329 00000211 >btiOO
330 00000219 abOi
331 0000021b >b100

NOTFND
NEXTC

332 ODOODZld >b60Q
333 000002lf a103

334 00000221
335

25e1

336 00000223 >cdOOOO

337
33.
339
340
341

LLOOP

342 0000022e >beOO

343 00000230 >.600
344 00000232 a1ft
345 00000234 2612
346 00000236 >cdOOOO
348 0000023b >cdOOOO

349 0000023. >beOO
350 00000240 >e700

351 00000242 >c:dOOOO
352
151
354
355

00000245 >c:110000
000002 . . >b600
000002401. al01
0000024c 2211e

ALOe

CHAPTER
ADD 4 FOR GHOST ROWS

ACC

COUNT
fl
.3
t$FF

STA
STA
STA
JSR
INC
LOA
STA
"R
8.S
LOX
STA
BRA
JS.
LOA
ADD
STA
LOA
CMF
8LO

ACC+l
ACC.2
ACC.3
INDXP
COUNT
.3
.,0
GLPl
NOTFND
COUNT
ACC,X

DEC
LOX
LOA

341 00000239 >b600

..

LOA

JS'
CLR
LOA
STA

00000226 >3[00
00000221 ...-604
0000022a >b100
0000022c >3.00

LOA

ADD
STA
CLa

abOt
>b700

CMP
BME
JS'
LOA
JS'
LOX
STA
JS'
JS'
LOA
CMF
BHI

.

LOOP ROUND RED. GREEN , YELLOW
GET LINKED PAGE No.
ALREADY IN RAM ?
YES. SAVE ACC No.
AGAINST COLOUR

NEXTC
NOT IN RAM, SO SAVE
PAGE NUMBER IN LIFO

.PUSH

.3

NEXT LINI(

.3
COUNT
f3
LLOP

ALL DONE ?
GET CYAN AND INDEX LINKS

GCYI
"ACC

.4

COUNT
COUNT

COUNT
ACC,X
t$FF
ALOe
PULL
WACC
CHCK1
COUNT
ACC.X
UP
GLP2
COUNT
t$01
LLOOP

IF STILL AN Ace AT !;iFF THEN
RECOVER PAGE No _ FROM LIFO
ALREADY USED "1 IF SO INCREMENT

35<
357 0000024e

81

RTS

351

35,
360

Fetch linked paqe , Illaqazine number._

361

362
363
364
365
366
367
361
369
370
171
372
373
314
375
376
377
371
379
310
311

0000024!
00000251
00000253
00000255
000002S1
0000025 ...
0000025d
0000025t
00000262
00000264
00000266
00000269
0000026b
0000026d
0000026f
00000272
00000274

>b600
41.113
2203
>07006c
41.610
>cdOOOO
>b601
>cdOOOO
>b700
>b600
>cd1)OOO
>b100
>b600
>b700
>cdOOOO
>.600
>b100

383 00000276
384 00000219
315 0000027c
316 0000027!
387 00000281
388 00000283
389 00000285
390 00000288
391 0000021b
392 0000028e
393 00000290
394 00000292
395 00000294
396 000002"
391 0000029&
398 0000029c
399 0000029.
400 000002 ... 0

>cdOOOO
>070009
>000004
>1000
2002
>1100
>cdOOOO
>050009
>020004
>1200
2002
>1300
>010009
>040004
>1400
2002

GLPl

CO.

LOA
CMP
BHI
BRCLR
LOA
JS'
LOA
JS'
STA
LOA
JS'
STA
LOA
STA
JS,
LOA
STA

.,0
.19

IF INDEX IGNORE LIKI( CONTROL

COR

3, 51AT3,N0101(

fl'
'2B
IOBUF+1
DECODE
.2
IOBUr
DECODE
PT
'2
PU
INDX
PAGO,X
PH

LINKS OK 1
YES, ROW 16 FOR LINKEO PAGES
FETCH 2 LINI( BYTES
DECODE 11NITS
DECODE TENS

CHECK FOR ZERO 1
FETCH CURRENT HAG_ HO.
PAGE HUNDREDS

302

>1500
>ccOOOO

R2BJ1

.,
OKO

JS.
BRCLR
BRSET
85ET

BRSET
"ET
BRA
BCLR
BRCLR
DRS!T
SSET
BRA
BeLR
JMP

RADIO
3. IOBUr, OKO
O,PH,H1
O,PH
OKO
O,PH
RADIO
2,IOBUr,OK1
l,PH,PT1
l,PH
OKl
l,PH
3,IOBUF,OK2
2,PH.PU1
2,P8
OK2
2,P8
SRCH

JS'
LOA
JS'
STA
LOA
JS'
STA
BRA

'2B
IOBUr+1
DECODE
PU
IOBUr
DECODE
PT
R2BJ1

JS'
SUB
STA
LOA
JMP

.3

BRA
BCLR

JS'

BRCLR

PTl
OKl

PUl
OK2

MAG BIT ZERO OK 1

NO, SO TOGGLE

MAG BIT ONE OK 1
NO, SO TOGGLE

MAG BIT TWO OK 1

NO,

SO TOGGLE

401
402
403
404
405
406
407
401
409
410
411
412
413
414
415

>cdOOOO
>b60l
>cdOOOO
>b700
>b600
>cdOOOO
>b700
20cO

R2BJ2

000002b6 >cdOOOO
000002b9 01.018
.o00002bb >b700
000002bd 01.604
000002b( >ccOOOO

NOTTH

00000201.3
00000201.6
000002&8
OOOOOZab
000002ad
000002a(
000002b2
000002b4

RELI
1$11

••

SPH

199

FETCH 2 LINK BYTES
DECODE UNITS
DECODE TENS

U1

• • • • 111 • • • • • • • • • • • •

** ................. "' ••••••••••••••••••••

411

u.

a." bit. ·for default tH , -1) linb4

42.

U,

422
4.23

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .III

~O'01Ul2c2

>ld.OO

424 OOOD02e4 >cdOD-OO

42$
426
421
U'
-429
43-0
431
432
43.3
43"
US

OtI0002c7
OO.oOO2C'
000002CD
OOeOOiccl
000002ce
OO-OOOldO
OOOOO.2d2
OOOQD2dt
GOOOO2d'
000002d'
000002d.

>86<10
>b780
>&602

1IO'l'OIt.

"""""

LDA
INCA

.........•••.,,

n.

.'0
411
492
.91
494
49S
496
.97
49•
4"
$00
SOl
502
S03
S04
S05
506
507
508
S"09
510
511
51Z
513
514
515
S16
511
S11
U9
520
521

PAGE+2

"U'

PACI.2

'LDA
STA

B...
INC

.n,

loDA
011'

'V
PAGa+2
PAGI+l
rAGS+!

'U9

IIOIIt

Il0'l'

SrA
LOA
ITA
lIRA

'T
OK.

IIOTOK.

BeLlI

',STAT

LOA
IrA
LOA
OBCA
STA
STA
CNt
80S
LOA
STA
.'fA
DEC
LOA
011'
80S
LDA
lIRA

PAGO,X
PH

LOA

IIOV9A

>e600
>b70D
>bfiOZ

••

>b100
>b102
a130
24.,
-'39
>b700
>b1GZ
>3a01
>baD1

-.UO
24db
dl9
20dS

..

....,."
.no

8L1

23"

000002 •• )oldOe

,.,0

PAGEH
PA1Z+1

'CANCE.L SVB"'PAC!.

PAGE+Z

P.

PAGE+2
"30

NOV'

tt39
PO

PAGE+!
PAG&+l
PAOS+'

'$30

.•.NOV."

.............................................................
...............................................................
IIO'IfA

"_qu..t ne.. link" paq•.

U.
410

41:'
472
·Ul
4'H
US
.76
471
47"
47t
410
411
412
eu
484
415
.. "
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, ..

••

.OA
ClIP
8LS

442 000002 •• >blOI

000002 fa
000002 tz
0000021..
OOOOOZf6
OOOOOZt1
000002(9
OOOOOZfb
GaODOHd
0OOOO2U
000003'01
00000303
OOOOUOS
DOoono,
0000030"
0OOOO30b
DOOO030d
COOOa30f

ITA

CANCEL!. SUB-fAQB

IJIDX

PV

443 OOOOG2 •• >b70D
444 OOOOGZec 20bZ

446
44"
..4 I
449
450
451
452
453
454
455
456
457
45.
4St
4'0
461
04 62
463

.AGO,X

ITA

440 0000028•
.-630
4t 1 000002d >b101

...

6.STA'r

loDA

••

>b700
>b702

2312
.630
>blOG
>b702
436 000002dc :>lcOl
43' DOOOOZde >biG1
UI DOOOOUO

U9 OODD02.e2

8CLS

"..

..
.

00000311 >1)'0.0

OOlU~Ol13

OOOOOll4
DaOOO3U
OGOD0316
0000031 •
aOaa03lt
OO-O-oOllb
00000,31c
0000031e
00000320
0000-0322
OD000324
1)0000326
00000321
000.o03.2a
OOOO032c
0000032.

>b100
>bbOO

t7

>b600
>b'100
>.112
>0600
>b70G
>.701
>b6'00
>.100
a018
>b100

00000330
00000332
00000334
00000336
0000033'
0000033 •
OO'00033c
0000'033.
.00000340
00000342
00000344
00-000146
00000348
O.DODOl4a
aOOOOl4c
0000034.
00-000350

a309
221c
anD
"'blOG
>b600

OOOOO~11

>edOOOO
d06
>edOOOO
>1700
>cd:OOOO
>cdOOOO
>ceOOOO

0000<)354
OOOOUS6
OOO(M)3U
'OOOO1J3Sb
000003Se
00'0:003-61

OOODOl&)
80000),6d

••

C.

LDA

.T
C1
PAGO+l.X

.

PH

,AGO .. X

1$18

U

80l
LOA
STA

"-T
USO
All
1fACC
f.OI

loDA
BTA

LOA
STA
LOA
CHI'

lilt.
LOA

"""
BLS
An

>SA
LOA

3"

BeLlI
'S.

3. .
3M>

LOX

a.....

.
.

TXT'

-CLBAR CHAPTBR

FOR. IT
OON'T CLIJUt THU TIME
PUT PAGE Nt1NHR IIi CHAPTER
SET FOUHD FlAG
AND 1mQU£St' IT

Ptt.. -X

1.IFO.. "

~1

ATS

ROIl •
COLUMN 2

'PAUZ
3 ... 1
TXT)'
SFHD
TXTllo

LOA

BtL

ACC
CLEAR CHAf'TBR
INTO lIe

A"
C,
f$3J
AIIOItT
C'
I$3!J
LOX

STA
OBCK

btt

••
.3
X <- 3 x ACC No.

PAGO+2~X

CPX

Ct.R

ItUSH
PlHL

C.
P.

"""

LOK

C,

loDA

STA

AIIOItT

.

STA
$fA

sua

....
"

STA
LIRA
LIRA
LSRA
STA
LIRA
l\DU
TAX

SrA
STA
LOA
STA

>b100
>lfOO
al02
>b100
>b6DO
-1139
2206
>b600
all'
.2301

00000364 ••01
000'0036fi >41"600
00000361 ,.100
0OOO-O3~

Gr.. .

WAIT

PSHL

200

...

* ..........................................................

>23

sa

..........................................................
19 page already in RAM 1

526

S21
521

.

5Z9 0000036e >3fOQ

SitCH

530
531
!il2
533
534
535
536
537
538
539
540

LOOPS

00000310
00000312
00000373
00000315
00000316
000Q0371
0000037.
OOOD031c
0000031e
00000380
00000382

>b6GO
>bbOO

'7

>.600
>blOO
260e
>e601
>blOO
2606

....

LOA
CMP
BNE

>8602

541 00000314 )oblOO

542 00000386 210.
543 0000038. >3eDa
544 0000038a >b600
545 ODOOO38c al04
S46 0000038. 25eO

S41
548 00000390 >b60Q
549 00000392 al04
550 00000394 81
551

55'
553

.

".
,

FIIIl'

557

00000395 >3cOO
(J0000397 Sf
00000391 >b'OQ
000003'.1. >e100
0000039c 27n
000003ge So
0OOOO3'! a304
000003al 25(5
000003a3 81
000003a4
000003a6
000G03a'
000003ab
ODD003ad
000003bO
00OO03b2

>3cOO
>3cOQ
>cdOOOO
>b600
>edOOOD
>bfOO
11

S77

sn

57'
SI.
SIl
58.

PAGO.X
PH
FIN!

PAGO-+l.X
PT
FIN!

PAGO+2.X
PU
FND2

INC
LOA
CMP
BLe

.ACe

WA
CMf
RTS

"Ace

WACe

••

LOOPS

IF MATCH THEN CHECK FOR
SUB-PAGE HATCH (SHOULD

••

............................................................
................................................................

DISPlAY PAGE. BB DIFFERENT)

SIoM

CHCKl
CHCK2

INe
CLRlC
LOA
CMP

..",0

BEQ
INCX

SlUI

CPX
BLe
RT.

U
CHCK2

INC
INC
JSR
LOA

001

",,"C

.....CC
ACC,X

JSR
STX
RTS

.,0

.lD
R28N'
IOBUF
DECODE
IOBU.

..............................................................
Tran.fer ;host row 20 to display row 24.
, .et found naq.

................................... ".............................

51]
584
585
586
587
588

OOOOOJb3 >3fOO
OQ0003bS >b600
00OOO3b7 ab04
00o.003b9 >b700
0OOO03bb .1.614
000003bd ad5a

590
591
592
593

0OOOO3bf a620
00000le1 >b700
MOD03e3 >b700
OOQD03e5 >07000'

...

WAee

CHP

567
568
569
570
571
572
573
574
,7S
S70

MAce

LOA
BEQ
FIN1

....ee

Is Accqui8ition circuit in use '1

55S

551
559
560
561
562
563
564
56')
566

eLK
WA
LSLA
.,,0
TAX
LOA
eMP

ROW24

MR.

CLR

LOA

Al.
ACe

...

CJU\PTER
ADD 4 FOR GHOST ROWS

t$20

SPACE

.,,0
S"

W.

••••

BSR

A'8

ROW 20

LOA
STA
STA

A"
PH

eReLR

3. STAT3, B~K

ROW24 ENABLED ?

LOA
STA
LOA
STA

IOBUF+l

YE.S, so lJS! DATA

R"
lOBUli'
PH
ACC

••
N'.
MRE

BACK

4~Rll

SET FOUND FLAG
WRITE IT

SO.
595 000003c8
59~ 000003ca
597 000003cc
598 000003ee
599 000003dO
600 000003d2
601 COOOO3d4
602 0OOOO3d6
603 ODOO03d'
0 ••
60S 00001l3da
6~6 0OOOO3dc
601 000003de
60' 000003eO
609 000003e2
610 000003e4
611 000003e6

61'

113
614
615
616

>b601
>blnO
>b600
>b700
>b60Q.
>b700
.1.618
ad3l
23db
>1800
.1.619
>b700
a60a

BLANk

BLS
SFHD
SFHD2

BSET
LOA
STA
LOA

~b700

S"
LOA
JMl'

a60S
>ceOOOO

000003e9 >cdDOOO
ODOO03ec 250f
000003ee >1900
000003fO 20ea

LOA
STA
LOA
85R

crND

...

...

•• S

ROIl

COLUMN

RlO

ts
TXT32
CPBL!'

JSR
BCS

ABcr

Be. .
BRA

SFND2

"~Rll

CLEAR FOUND FLAG

617
611 000003f2 >cdOOOO
619 000003f5 >e601
620 000003(7 >))701
'2~ 000003n >e602
622 OOOOO"3tb >b102
623 00OOO3fd 11

52.

625
626
627
628
629
630
U1

01l0003f. Sf
000003ff >dOO
00000401 >.100
00000403 Sc
00000404 .1.309
00000406 2St?
0000040. 11

IHDXP

ABCF

PULL
PLLL

JSR
LOA
STA
LOA
STA
RTS
CLRX

LOA
STA
lHCX
CP.

BID

to

DISPLAY CHAPTER

IIIDX

PAGO+1,X
PAGE+1
PAGO+2,X
PAG&+2

.

LIFO. X
PHrX
PLLL

ATS

201

............................................................

633
634
6,.
636
631
638

R."d and writ. sUbroutin••.

63.

'40
641 0000040' >b700
642
643
644
64S
6c:dOOOO
)o3eDO
>JeDD
>b6DD
647 00000416 a126
648 oeOOCtu 11

...

650
651
6S:2
653
654
iSS
656
657
658
659
660
'61
U2

.................................... "...........................
ey.n , Index l1nt. , link control byte-.

00000419
aOO-DOUb
OOD0041d
QOOOO4lf
00000421
00000423
00000425
Oo.OOOUI
00000429
0000042011
OOD0042c
0000042.
00-000430

>b700
a.60a

>b100
,,604
>b700
" ... 00
>cdOOOO
42
42
.. 60b
>b700
4622
>b700

K'B

V5
"B

R2BN9

READ22

"5
666
667
6"
6"
670
671
672
UJ
614

00000435
00000437
00000439
0000043<::
0000043.
00000441
00000443
00000445
00000441
000004401

.. 613
>b700
>c:dOOOO
d40
>edOOOO
a6lf
>b100
>c:dOOOO
a6S0
><::cOOOO

GCYI

616
611
678
619
680

0000044d
0OOO044f
00000451
00000453
00000455
00000457
000004590000045c
0000045.
00000460
00000462
00000U4
00000466
00000468
0000046&
0000046c
OOOOOUe

>b600
ilb04
>b100
>3fOO

CLINK

61'
611

612
683
614
685

61,
687
6S1
689
690
691
692

...

>3!00
d10
>cdOOOO
>b601
260.
d25
>b700
d10
adbl
>b601
ad03
>bfOO
11

693

'.5
6.'
601

LOA
STA
JS,
LOA
JS.
LOA
STA
JS,
LOA
JMP
LOA
ADD
STA
CLR
CLR
LOA
'S.
LOA
BNE
LOA
orA
LDA
85.
LOA
SS'
STX
RTS

""" ,.

R.

.,.
13.

.••.

'011

SUB3

Wl
UUB3
S!HD22
DELAY TO SATISFY

lIe TIMING

'"

SUBADR

1$22

ADD.

.IW>

.,.

CYAW

131

INDEX

fl.

GLP1
1$40
GLP'

'10

GLPl
1$50
GLP2

ACC

••••

STAT3

.10
.16

'2B
IOBUr+1
HPK27

DESTIHATIOH BYTE
IF NOT ZERO,. NO PK21
CHAIN CONTROL BYTE

".
.31

flO

"B
IOBOP'+1

DECODE
STAT3

........................................................
.......................................................
NPK21

000004&! >b100
00000471
5f
00000472 >d60000
00000415 >bl00
00000411 2132

DECODE

00000479
OOOOOUb
0000047.
00000410
00000482
00000484
00000481

>b700
>000004
>1000
2002
>1100
>cdOOOO
2122

TRZE

ODODn489
Oo.00048c
ODo.0048e
ODOOo.U1
Oo.Oo.OU3
00000495
00000497
00000499

>d600DD
>b7o.o.
>0.20.004
>1200
2002
>130.0
ad7a
2714

DOOOOUb
OOOOOUe
000004 .. 0
0.00.0.04013
DOODOh5
00D004a7
00.0004019
OO!)DOhb

>d60000
>b700
>0.40.00.4
>1400
2002
>150.0.
.ad68
2762

132 nn0004ad >d60DOO
733 o.D0004bO >b700
734 '000o.4b2 >0-60004
13~ ODOOD4bS >1600
736 0OOO04b7 200.2
737 o.o.OOD4b9 >1100.
738 00OO04bb ad 56
739 DOOo.D4bd 2750.

TilTH

TRA

105
706
107
108
709
710
111
112

STA
LOA
STA
JMP

.
.,.

TXT32
Rl.

H"JMlinq decode.

6 ..
,.,
100
101
702
103
104

STA
LnA
STA
LOA
STA
LDX
JS.
MUL
MUL

LOA

663 00000432 >ccOOOO

'64

STA
LOA
JSR
lHC
lHC
LJ)A
CM>
'TS

5TA
CLRX
LDA
eMP
BEQ

HAM,X

FNDJ

SU82
O,SU82,ZE1
O,SU82
ZE1+2
O,SU82
SSUB

STA
8RSET
BSET
BAA
BCLR
JS.
BEQ

FNDJ

LOA
STA
BaSET
BSET
BRA
BCLR
BS.
BEQ

HAM, X
SUB2
l,SU82,ONI
I,SU82
ON1+2
1.5U82
SSU8
rND

TRTM'

LOA
STA
BaSET
8SET
BRA

HAM,X
SU82

TWl

BCLR
BS.
BEQ

2,5UB2
TWl+2
2.5UB2
SSUB
rND

LOA
STA
BR.SET
SSET
BRA
BeLR
BS.
BEQ

HAM,X
SUB2
3,5UB2,T81
3,5U82
T81+2
3,5UB2
SSUB
rND

lEl

"

.,
.,

113
114
115
716
717
718
719
720
121

TROH

ONl

122
723
724
125
726
727
728
129
730

FNDJ

2,SUB2~TW1

131

THl

202

. . . . . . . . . . . . . . . . . . . . . . . . . . 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

741
7<2
743
7',
7.S
706

...........................................................
More Hallllllinqo decode.

741
741
10
150
751

000004bf
OOODOte2
ODODOte"
000004e7
DOOOOtct

753
154
7SS
756
751
751
759
160
'61

DODOOted
aDDOOte!

>d60000
>b7QD
>010004
>1100

2002
752 OOOOOtcb >1900

000004d1
000004d4
000004d6
000004d9
OOOOOtdb

>d60000
>b7QO
>0 ... 0004
>1.00

BRUT
BRA

.. 1£32

'63 DOOO04e1

272c

'65 000004e3 >d60000
766 000004.6 >bl00
767 00000 .. "
>OcOO04

..... X
SUB>

4.SUBI.FOl
4,5UB2
FOl+2
4.SUB2

FO'

BCLR
BSO
BBO

55UB
'NO

TRYI

LOA
STA

..... X
SUBZ

BRS!T

2002

162 aOaOOed!

LOA
STA
as.T

.d44
273e

000004dd >lbOO

".

TAFO

F11

TOSI

as.T
BRA
BCLR
. .0
B£Q
LOA
STA
BRSET

5,SUB2,FIl
S.SU82

FI1+2
5,5VB2
55UB
FNO
HAM.X
SUB2

' " OOOOOteb >1cOO

85ET

'69 OOOOO"ed

SI1

BI\A

BCLR
aso
B£Q

',SU82,Sll
6,SUB2
5Il+2
6.SUB2
SSUB
FND

TRSE

LOA
STA

HAM. X
SUB>

BRSET
BSET
BRA
BCLR
as.

7,SUB2,SE1
1,SUB2
5£1+2
1,SUB2
SSUB

BEO

FOD

Z002
710 000 DOe., >ldOO
711 00000er1 ad20
772 000004t3 271.
773

774
715
176
717
778
719
180
111

000004n
OQ0004n
OOOootta
000004fd
000004(t
00000501
00000503
0OOO05{)5

>d60000
>b700
>OeOO04
>leOO
2002
>ltOO
adOe
2708

S<1

712

783
184
185
'86
'17
18.

00000507 Sc
00000508 aJOt
OOOOOSOa 2203
D000050c loccOOOO
0000050f >d60000
00000512 01

INCX

FNO

FND
TAR

LOA

NUM,X

OTS

7"

190 00000513 >b600
791 00000515 >b100
792 00000511 11
793
7',
7,S
7 ••
797
7"
799

100
801
802
103
804
80S
806
807
808
809
810

SSUB

"

.................................................................
Mix/nOJllix.

00000530
00000532
00000534
00000536
00000S38
0000053.
0000053c
0000053.

lolfOO
a616
>b700
a6cc
>bl00
a6U
>b700
2005

NOMIX

00000540
00000542
00000545
00000547
0000054&
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135
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1011
1011
1.019
1020
1021
1022
1023
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1.025
1026
10"21
1028
1029
1030
1031
1032

1033
1034
1035
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10.40
1041
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1059
1060
1061
1062
1063
1064
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1069
1010
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1072
1073
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1075
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1019
1010
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1014
1015
1086
1087
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1089
1090
10'1
1092
1093
10'4
10'5
1096
1091
1098
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1100
1101
1102
1103
1104
1105
1106
1101
1101
1109
1110
1111
1112
1113
1114
1115
1116
1117
1111
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1120
1121
1122
1123
1124
1125
1126
1127
1121
1129

··········.··................·••···fII·· •.................•.
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nuMber entry routine.

• *•••••••••••••• *........................................
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PAGE+5
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CLEAR 1'E.,
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TXT3
TXT32

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HOLD DURING
S11B-PAGE NUMBER
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UP

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206

1131
1132
1133
1134
1135
113&
1131
113.
1139
1140
1141
1142
1143
11U
1145
1146
1147
1141
114.9
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11S3
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1157
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1159
1160
1161
1162
1163
1164
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........................................................
........................................................
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....
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.SR
CLR
JSR
LDA
STA
LOA
STA
LOA
STA
LOA
STA
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ITA
STA
LOA
STA
CLK
LOA
STA
BSR
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6. STAT. OUTS.
I. STAT

usn

PDP
INDX
PAGO.X
PAGE
'AGO+l~X

PAGE+l
PAGO+2.X
PAGE+2
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PH
PT
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ACC
UP
2. STAT
TXT1
TRAM1

RUET HOLD FLAG

1167
lUI
1169
1170
1171
1112
1173
1174
1115
1116
1111
1111
1179
1110
1111
1112
Ull
1114
1115
111'
1111
1111
1119
1190
U91
1192
11'93
1194
1195
11"
1197
1191
1199
1200
1201
1202
1203
1204
12-0S
120-6
1107
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1209
1210
1211
1212
12-ll
1214
1215
1216
1211
1211
1219'
1220
1221
1222
1223
1224
1225
1226
1227
1221
122'
1230
1231
1232
1233
123&
1235
1236
1237
123-8
1239
1240
1241
1242
1243
1244
124S

BeLK
CLK
LOA

ITA
JSR
LOA

STA
SUB
ITA
LOA

STA
STA
LOA
ITA
STA
CLR
LOA

STA
LOA
ITA
JHP

'~STAT

PDP
"SO
R11
IHOX

PAGO,X
PH
1$11
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PT
C1
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PU
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RI
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• • • • • • • • • • • 411 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

R.ad in ROW 25 inforftlation.

.........................................................
000007dl
000007da
000007de
0OOOO7de
000001.0
00000182
000001.4
000007e7
000007e9
000007.b
000001ed
000007ef
000001f1
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>blOO
>b700
>lbOO
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>b700
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>b601
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2704
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>b600
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00000715
00000lf1
000007f9
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000001(.
00.000100
00000102
00000804
00000106
00000101
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... 504
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2104
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000 001 Dc 2704
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000-00112
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00000116
00000118
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00000120
00000122
00000825
00000821
0000012a
0000012e
0000012.
00000130
00000132
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a40e
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aG06
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2104
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00000136
000001l'

Of0101
11

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......

STA
BeLK
l.DA

STA
LOA

JSR
LOA

....
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STA
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....

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BUT
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SN3

ABD
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LOA
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....
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....

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aRCLR
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ACC
RI
5-,STAT2
U
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ROOf

MINUTES UNITS

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CLEAR N£1fSf'LASH BIT
CLEAR SUBTITLE BIT
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3,SUB2
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TO BIT 3 Of' MIIIUTES TENS
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C.
CGET26
5,STAT2
CS
1·, PORTB. GETU

207

PACKET 26 ENABLED 1

........................................................................
........................................................................

un

1241

120
IUD
1251
1252
1253
1254
1255
1251
1257
1251
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1211
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1265
126'
1261
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116'
1210
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1212
1273
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000001,7
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ITA
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STA
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1213
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121'
12'0
12-91
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1295
1291
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1301
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1303
1304
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13.07
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13101311
13-12
1313
1314
1315
1311
1317
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1321
1322
1323
U24
1325
1326
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2002

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1330
1331
133-2
1333
1334
133-5
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133'1
1331
1339
1340
U41
1342
13.43
1344
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Uti
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1341
1349
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1352
1.353
1354
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000001.1 >blO2
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000001.' Z'75b
000001.' • 1Ot
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00000'e« alO.
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LIF0+5
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aW24
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SKIP

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ACC

••

LlF0+5

.,0

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LOA
CMP

t. LlFO+2. HorD
LIF0+2
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8SQ

NULD

CLOX
BeLO
LOA
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TXA.
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TAX
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BLI
BRA
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loaur

LlFO+4
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STA

YlS. BLOW AllAY ROlf
CORRU." SEQUENCE No.

••8

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....

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1329

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8LS

-

NULL '!
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LlF0+2
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SUB

DIACRITICAL 1

7.LIFO+I
CTAa.. X
LlFO+I
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8SQ

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1.11'0+1

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ACC

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LOA
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ITA
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LOA
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f3

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208

1351
1359
136D
1361
1362
1363
1364
1365
1366
1361
1361
1369
1370
1311
1372
1373
1374
1315
1376
1371
1371
1379
13,0
lJl1
1312
1313
1314
lJlS
1386
1317
1381
1319
1390
1391
1392
lJ93
1394
1395
1396
1391
1391
1399
1400
1401
1402
140J
1404
1405
1406
1401
1401
1409
1410
1411
1412
1413
1414
IUS
1416
1411
lUI
1419
1420
1421
1422
1423
1424
1425
1426
1427
1421
1429
1430
1431
1432
1433
1434
1435
143-6
1431
lUI
1439
1440
1441
1<442
1443
14U
1445
1446
1441
lUI
I ..... '
1450
1451
1452
1453
14S4
1455
1456
1451
1451
1459
1460

DDDDOln al0b
00DOOU7 2702
OODOOln 20U
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00000900 >bb03
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00000906 203e

NOTCF
CEDI

uoc

GTT

00000912
00000914
00000915
00000911
0000091a
D000091d
00000'l!
00000921
00000922
00000923
00000925
00000921

G3atT

0000092a
0000092c
0000092d
00000930
00000932
00000935
00000931
00000939
000009Ja
0000093b
000009Jd
00000940

00000942 >le06
00000944 >b606
00000946 >b100

11

LlFO+3

TAX
LOA

CT-'B~X

LIFO+2
t$OF
G2aIT
1$02
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BNE

STOM

G32r

....

TN32

I LLEGAL MODE

GOTCH

LOA
eMP

.eLA
eLAX
LOA
.NE
JHP
eHP

1,LIFO+6
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LlFO+6
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IHCX

G2aIT
TH23
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....

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G3T-'B+1,X
GOTCH

BCLA
eloRX
LOA
.NE
JMP
CHP

1.LIFO+6

LOA

G2TAB,X
ST"
LOOP'2
LIFO+6
G23F

BEQ

IHex
INCX

....

G23F

....

TN23
G2TAB+l.x

NULD
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8SET
LOA
STA

" LIFO+6
LlrO+6
a"

LOA
J.a
JIIP

'S
TXT32
lOOP62

00000948 4605
0000094a >cdOOOO
0000094d >ccOOOO
00000950

ADD

ClIP

Sf

>d60000
2603
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>b106
2104
So
So
20fO
>d60001
2004

.U.
STA
TXA

.EQ

Sf

>lf06

CEDI
CNNF
'S
LlFO+3

....

NOTO

>d6000D
2603
>ccOOOO
>b106
2104
So
So
20!0
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201c

eMP

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00000901 >b602
0000090a alOt
0000090c 271c
0000090e a102
00000910 263.
>1f06

.11

....

END26

LOA

GOTCH

aTS

.............................. .... .... .... " .. ......................... "...... """ .... " .. "
~

~

~

~ ~

....... "....... "...... "......... "... "...... .................. "... "..... .....
Packet 2-6 character laak-up table.
~

00000951
00000'51
0000095d
00000963
00000969
0000096f
00000915
00OOO91b
00000981
00000911
0000098-d

202021e02383
248426932140
219429a12 ... 2
2cbc2d5e2ebe
2f1630cbJ7e7
311i139a1Jaa2
3cl23dlc3el9
3fe16lf963.S
Utd6be66cfe
11f119fc7ctt
1f1tOO

G2TAB

Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.

$20, $20, $21, $EO, $23, $13
$24, $14, $26, $93, $21, $40
$21, $94, $29, $A1, $2A, $A2
$2C, $Be, $20, $5E, $2E, $BE
$2F, '76, $30, $ea, $37 .. $e1
,31,$IA. $39, $A1. $lA,$A2
$le. $12. $30, $Ie, $32, $89
$3F, ,131, '61, SF9 .. '63, $135
$69, $rD, $68 .. $E6. S6C, $FE
$71,srl, $19, $Fe, $1C, $FF
$1F, $1F, $00

00000990
00000996

511l5bldSclb
Sdle5t2000

G3TAB

Fe.
Fe.

$5i, $11, $58, $10, $SC, $18
$SD, $IE, $~F, $20, $00

0000099b
000009a2
000009a9
0OOOO9bO
000009b1
000009be
0OOO0ge5
000009cc
000009d3
000009da
00000981
0000-09.1
000a-0ge!
000009n

6leaebd2c'S9261
4lflf041dS9b41
65egeede6Sdb65
4Sf2904S454545
696gedde69d4"
4949f349Uf449
6feleedld916!
4 !f6!5d_d69c4!
15clefd97Se215
5S55!15555ge55
6e6e6e6eel6e6e
4e4e4e4 •• '4e4.
636363636363e3
4343U434343d1

eTAB

Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
Fe.
FeB
FeB
Fe.
Fe.

$61, 'EA, $EB, $D2, $C5, $92, $61
$41, SFl, $FO, $41, $D5, $9B, $41
$65, $E9, $EC, $DC, $65 .. $DB, $65
$45 .. $Fl, $90, $45, $4S~ $45, $45
$'9 .. $69, $ED. $DE, $69~ $D4~ $'9
$49, $49, 'F3, $U, $49, $F4, $49
$6F, $CI, $EE, $DI, $e6, $98, $6F
$4F, $F6, $F5, $DI, $D6, $9C. $4F
"5~ $el, $EF, $D9, $15. $E2 .. '75
$55, $55, $F1, $55, $55, $tE, $55
$6E. $6E, $6E, $fiE, $EI, $6E, $6E
'4E, $42, ,4E, $4E, $E1, $4E. $4&
$63, $63, $63, $63. $63, $63, 'E3
$43 .. $43, $43, $43, $43, '43, $D1

eLA
BitCLR
BSET
aaCLR

Llro+s
I.LIFO+1,N032
5,LlFO+S
0,LlFO+1,N016
4, LIFO+5
6, LIFO+I, NOI
3 .. LIFOH
5,LlFO+t,N04
2, LlFO+5
4. LIFD+I .. N02
I,LIFO+S
2, LlrO+I,NOI
0, LlFO+S

000009!d
000009!!
00000a02
00000a04
00000a01
00000a09
OOOOOaOe
OOOOOaOe
OOOOOall
OOOOOa13
OOOOOa16
DOOOOdl
00000a1b
OOOOOald

>3!05
>030702
>la05
>010102
>1105
>Od0102
>1605
>Ob0802
>1405
>090102
>1205
>050102
>1005

11

EXAD

N032

BS£r
N016
NO'

NO.
N02
NOl

""eloR
BSET
""eLA
85ET
BReLa
BSET
""eLA
BSET
aTS

209

~

.
A

0

0

........ ..... .... ......................''''''''' .......
... "'."'''' ... ........ .. ... .......... ..................
"''''''''''

1462
1463
1464
1466
1461
146.
14"
1470
1-411
14 7Z
1473
1474
1475
1476
1411
1418
Hn
1480
1481
1482
:483
~"84

1415
1486
1481
1 ... 8
1489
:490
:491
:492
:01,93
1494
149S
lU6
1491
1498
14 99
1500
1501
1502
1503
! 504
1505
1506
1501
1508
150'
151:0
1511
151-2
1"513
1514
H1S
1516
Hi7
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1S31
1532
1533
1534
1535
1536
I S37
1538
1539
1540
1541
1542
1543
IS44
1545
1546
1 541
1548
1549
1550
1551
1552
1553
1S54
1555
1556
1551
1558
1559
1560
1561
1562
1563
1564
1565
156'
1561
1568
1569
1510

''

"''''

''

Fetch initial p.aqe frcma 8/30 for.at L

U65

''

OOOOOale
00000a20
00000a22
00000.a24
00000.a26
OOOOOa21
OOOOOa2b
OOOOOa2d
OOOOO.a2!
OOOOOa31
00000a33
00000a35
OOOOOa37
0000Da3'
00000a3e
000OO.a3e
MOOOa40
OOOOOa43
00000.a45
00000.a4 '7
OOOOOa49
00000a4b
OOOOOa4d
OaOOCa4!
00000a51
00000aS4
00000~S6

>lbOO
>ldOO
>ldOO
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d02
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a604
>b700
a&iO
>b100
>3aOO
2135
a601
>cdOOOO
>3fOO
a611
>edOOOO
>b:601
26ee
dOl
>b100
a630
>b700
a617
>edODOO
>b60a
>b7QO
>b700
>b600
>b701
>b600
>b102
>b600
>b100
>cdOOOO
>ceOOOO
>1:1601
alIa
2502
>leOD
.1.631
>b100

00000aS8
OOOOOaSa
OOOOOa5e
OOOOO.aSe
00000.1.60
OOOnOa62
00000.1.64
00000.1.66
OOOOO-a69
00000a6c
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00000.1.10
00000.1.72
00000.1.74
00000a76
00000a18
00000.1.19 >b700
00000.a1b >b700
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..

GIP

TRYAG

BeLA
BeLA
BCLA
CLA
LOA
JSO
LOA
STA
LOA
STA
DEC
B£O
LOA
JSH

CLA

GETIND

LOA
JSH
LOA
8NE
LOA
STA
LOA
STA
LOA
JSR
LDA
STA
STA
LDA
STO
LDA
STA

LOA

IPNF

STA
JSR
JMP
LOA
CMP
SLO

BSET
1;>83001(

LOA
STA

'''.'''

''

''

5# STAT
6. STAT
6,STAT2

CLEAR SUB-PAGE MODE
CLEAR NO TXT FLAG

.....

PDP

'2

SPM

TXTI 1 BYTE ONLY

HI

CHAPTER. "

(GHOST)

96 TAYS

.3
.3

AGAIN 1

IPNF

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AN452

Using the MC68HC11 K4 Memory Mapping Logic
By Steven McAslan
MCU Applications Engineering
Motorola Ltd,
East Kilbride, Scotland

INTRODUCTION

such a way that the CPU itself is unable to distinguish
more than 64K Bytes of memory. The extra capacity
is provided by switching banks of the extra memory in
and out of the 64K Byte range provided. To maximise
the flexibility of this approach the size and number of
the switched banks is user programmable.

The MC68HCl 1K4 is providedwith memory expansion
logic which allows the 64K Byte addressing range of
the 68HCl 1 CPU to be extended to more than 1Mbyte.
This application note discusses the operation of this
logic and provides examples of memory maps and
possible hardware configurations.

To use extended memory, the programmer must first
allocate a range (called a windoW, within the CPU 64K
Byte addressing range which will be used when
banks are switched in and out. The memory expansion
logic allows windows of 8K, 16K or 32K Bytes to be
defined and placed at programmable points in the
CPU 64K Byte memory. At any time only one bank
may be displayed in the defined window and therefore
the CPU may only have access to the memory contents
of one bank at a time. The bank which is displayed in
the window is selected by the additional address lines
provided by the memory expansion logic. The process
of replacing the active bank with a new bank is called
bank-switching.

THE MC68HC11K4
MEMORY EXPANSION LOGIC
The memory expansion logic extends the addressing
range of the 68HCl 1 CPU by providing two new onchip blocks. The first new block implements additional
address lines which are only made active when required
by the CPU. The second block eases interfacing to
external memory chips by providing chip select signals.
Both of these blocks are fully user programmable.

A useful analogy is that of photographic transparencies
and a projector. The viewer may have many
transparencies but is only able to view one at a time
in the projector. If the photographs are numbered
then the viewer is able to select precisely which one
to view without having to go through all of them. Here
the memory banks are akin to the. transparencies many are available but only one is accessible at any
time. The number on the transparency can be thought
of here as an address. Any transparency which is not
being displayed at anyone time is still accessible but
only when the current one is removed and it is put in
its place.

ADDITIONAL ADDRESS CAPABILITY
Ifthe addressing capability ofthe 68HCl 1 CPU is to be
extended then the first step involved is to provide
additional address lines. The CPU itself provides 16
lines (AO to 15) which allow up to 64K Bytes of
memory to be accessed. Each new address line
provided will double that total.
To maintain compatibility with other members of the
68HCl 1 family the CPU used in the K4 isnotfunctionally
changed. The extra addressing capability is provided in

217

To extend the addressing capability of the CPU, six
address lines were added. These are termed XA13,
XA14,XA15, XA16, XA 17 andXA 18. To allow flexibility
in the size of the windows, the lower three address
lines are only used when determined by the size ofthe
window and replace the CPU's equivalent addresses.

The basic function of a chip select is to provide a logic
signal to indicate that the CPU is accessing a certain
area of memory. For example, the Program Chip
Select is intended to be active in the range of memory
where the main program exists. Other chip selects
will be active when their respective memory areas
are used.

To understand the need for the XA13 to XA15
addresses consider the case when an 8K Byte window
is being used. Address lines XA16 to XA 18 are only
active when the CPU is accessing memory within the
window and they provide an extra 8 (23) times the
memory provided by the CPU within that window. If
an 8K Byte window is used then a maximum of 8 x 8K
Bytes is available. However, for the CPU to uniquely
distinguish each location in the 8K Byte window it only
requires to use addresses AO to A 12. Changes in
address lines A 13 to A 15 take it outside of the window
and are therefore never valid within the window
except to identify the starting address of the window.
The three new addresses XA 13 to XA 15 are provided
so that a full 512K Byte (8 x 8 x 8K Byte} range is
realised. For a 16K Byte window only addresses XA 14
and XA 15 can be used and for 32K Byte only XA 15 is
usable. Note that the size of the memory window to
be used need not necessarily be defined at the
hardware design stage since the additional addresses
XA 13 to XA 15 can be programmed to carry the CPU
A 13 to A 15 signals. The situation may be complicated
by the need to use differently sized windows (see
example 2}.

The General Purpose Chip Selects are the most flexible
of those provided and their function is closely linked to
the memory expansion logiC. They can be programmed
to be active on an area either within the CPU 64K Byte
memory or within either window's 512K Byte range.
In both cases the size of memory selected is fully
programmable from 2K Bytes to 512K Bytes.
The above paragraphs outline the method by which
the memory expansion logic extends the addressing
range of the CPU. A detailed description of the internal
registers used to implement the new logic is now
required. Finally a series of examples are considered.

MEMORY EXPANSION AND CHIP
SELECT REGISTERS
This discussion describes the functionality of the
internal registers relating to the memory expansion
logic and chipselects. Further details on their addresses
and specific bit operations may be found in the
Technical Summary (1).
The following registers perform the memory
expansion function.

The memory expansion logic actually allows the user
to define two independent windows and so more than
1M Byte of memory is accessible.

The MMWBR register allows the starting address of
each of the two windows within the CPU 64K Byte
address range to be defined; The windows will normally
start on a boundary related to their size, for example
an 8K Byte window may start on any 8K Byte boundary
starting at $0000, that is, $2000$4000 ... $EOOO.
A 16K Byte window can only start on 16K Byte
boundaries, $0000 $4000 ... $COOO. An exception is
made for the 32K Byte window. This would normally
start at either $0000 or $8000. However, the window
is also allowed to start at $4000.

The hardware required to implement such a large
memory range is greatly simplified by the use of the
memory expansion's chip select block.

CHIP SELECTS
The memory expansion chip selects are provided to
help the user interface the K4 with external memories.
Four are provided but only three are of direct importance
to the memory expansion logic. These are the two
General Purpose Chip Selects and the Program Chip
Select. The fourth, I/O Chip Select, is used to simplify
the addition of external peripheral chips.

The MMSIZ register sets the size of the windows in
use and selects whether the chip selects are active for
only CPU addresses or for extended addresses.

218

Each General Purpose Chip Select has two registers
called GP1CSC, GP1CSAand GP2CSCand GP2CSA.

EXTENDED MEMORY EXAMPLES

The contra/register (GP7CSC) determines the logical
output required when an area of memory is selected
(with possible logic combinations with other chip
selects) and the range of memory over which the chip
select is to be active. Each chip select can be
programmed to become active whenever the CPU
address enters an memory expansion window
(regardless of the actual bank selected); this is known
as following a window.

The best way to grasp the implications of the K4
extended memory function is to consider some
examples. Each example consists of two figures.
Figures a are the logical arrangement of the memory
and Figures b are a possible hardware configuration.
Example 1 shows one window in use. This is an 8K
Byte window scheme and provides 8 banks from a
single 64K Byte EPROM chip. Note that the logical
address of each bank is derived from address lines AO
toA 12 then XA 13 to XA 15. Chip select 1 is used.

The address register (GP7CSA) allows the starting
address of the chip select to be programmed. The bits
in this register which are active are determined by the
size of the chip select range selected by the control
register.

Example 2 shows two windows in use. The first window
is of 8K Bytes and is organised as in example 1.
The second window is of 16K Bytes and is organised
as 16 banks in two 128K Byte RAM chips. The logical
addresses of the Window 2 banks are determined by
AO to A 13 then XA 14 to XA 17 (XA 18 determines start
address). Chip select 2 is used for window 2.

The program and I/O chip selects are programmable
via the CSCTL register.
Two window registers, MM 1CRand MM2CR, are used
to indicate which bank is active in a window. Each
contains the values of XA 13 to XA 18 to be output
when the CPU selects addresses within the extended
memory window. To change banks the user writes
the address of the new bank into the appropriate
window register.

Example 3 shows the same two windows as in
example 2 except that the logical addressing of the
windows are changed. Now Window l's logical
address is determined by AO to A 12 then XA 15 to
XA17 (XA13 and XA14 ignored) and Window 2's
logical address is determined by AO to A 13 then XA 15
to XA 18 (XA 14 ignored), Note that in both windows
every bank will be duplicated due to the lack of
decoding on certain address lines. In Window 1 each
bank is duplicated four times. In Window 2 each bank
is duplicated twice.

The actual memory expansion address lines are
multiplexed with PORT G I/O pins. Selecting an address
line on one of these pins means that a PORT G pin is
lost. For this reason the user need only select those
address lines which are needed by the expansion
logic. This allows unused lines to be used as general
purpose I/O. The register which defines which
extended address lines are used is PGAR. If an
address line is not required then the appropriate bit in
PGAR should be cleared to O. A special case exists for
two address lines which overlap the CPU address
lines (XA 13 and XA 14). If XA 13 or XA 14 are selected
as address lines in PGAR, but are not used in either
window, then the appropriate CPU address line will be
output on the port.

Example 4 shows the maximum 1Mbyte extended
memory possibility in use. Window 1 is 16K Bytes
starting at $0000 and Window 2 is 32K Bytes starting
at $4000. Note that the internal RAM and registers of
the K4 are echoed in every page of window 1, but that
the internal EPROM in window 2 only occurs in the
first 64K Bytes of extended memory. That is, for
addresses below $10000, the internal EPROM is
present in the memory map at the relevant address.
This currently applies to all window sizes and
configurations, however, the user should avoid
referring to EPROM at any address beyond page 0 to
ensure compatibility with any future upgrades.
Logical addresses of both windows are given by AO to
A 13 then XA 14 to XA 18. Window 2 uses XA 14 because
it does not start on a 32K Byte boundary and so
reqUires that the XA 14 is inverted. Both chip selects
ale us~;d and follow a window each.

219

PGAR $3F - XA13 .. XA18
MMSIZ $42 - Window 1 8K
MMWBR $04 - window at $4000
CSCll $00 - no 1/0 or program chip select
GPCS 1A $00 - from $00000
GPCS 1C $06 - 64K range (8 x 8KI
GPCS2A $00 - not relevant
GPCS2C $00 - disabled

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GPCS1A $00 - from $00000
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Figure 6. RS232 serial interface with Load/Dump switching

Table 2.
Set-up

Function

S1

S2

Load

On

L

Dump

On

D

Load

On

L

S-records loaded from pin 3.

Dump

On

D

S-records sent to pin 2 on "host" socket
(and pin 3 on "terminal" socket).

Terminal and host connected. Micro looks at data
sent from host tp terminal (pins 3).

Host &
terminal

PC "COM"
port

Comments

Connection between terminal and host broken,
. S-records sent to both host (2) and terminal (3).

REFERENCES
1)

AN441/D, An EPROM Emulator using the MC68HC05EO.

2)

AN460/D, An RDS Decoder using the MC68HC05EO.

238

APPENDIX - EBUG05 EO monitor listing
0001
0002
0003
0004
0005
0006
0007
0008
0009
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040

EBl.X;05 EO monitor.

P. Topping

0020

ORG

'91

$0020
PORT A ADDRESS
B

0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
aODe
0012
0003

PORTA
PORTB
PORTe
PORTO
PORTE
PORTAD
PORTBD
PORTeD
PORTDD
PORTED
TeR
PORTDSF
NBKPT

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0020

STAT

RMB

0: Not first SWI after RESET
1, PROCEED (0, GO)
4: No address entered (BLDRNG)
5: Veri fying (TLOAD)
6: Register contents being changed
7: Last 51 record (PUNCH)

WORK2
ADORH
ADDRL
WORK3
WORKS
WORK6
TEMP
PNCNT

RMB
RMB
RMB
RMB
RMB
RMB
RMB
Rl>U3

RAM SUB-ROUTINE LDA/STA
ADDRESS H
ADDRESS L
RTS

CHKSUM
COUNT

RMB
RMB

TMP1

RMB

0021
0022
0023
0024
0025
0026
0027
0029
0041 C02 a
0042 002b
0043 D02e

0044 C02d

TMP2

RMB

0045
0046
0047
0048
0049
0050

BCNT

RMB

.002e
0200

0200
0203

0051 0206
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062

18th November

0209
020e
0212
0213
0214
0215
0216

eOOO

ORG

IRQ
TIRQA
TIRQB
SIRQ
DTABL

C

D
E
PORT A DATA DIRECTION REX;.
B
C
D
E
TIMER CONTROL REGISTER
PORT D ALTERNATIVE FUNCTION REG.

4

5
6

7
8
9
SOC
$12

3

TEMP. ADDRESS
No. BREAKPOINTS
CHECKSUM (SERIAL)
BIT COUNTER
TEMP (SERIAL)

BYTE COUNT
$0200

DE-BUG RAM VEC'IDR,

RMB
RMB
RMB
RMB
RMB

IRQ
TIMER A
TIMER B
SERIAL

DISPLAY TABLE

WORKl

RMB

WORK4
TMPTCR
PROP
BKPTBL

RMB
RMB
RMB
RMB

3'*NBKPT

ORG

$EOOO

TEMP. TCR (XHOM USED BY MONITOR)
INSTRUCTION (PROCEED)
B.P. TABLE

239

*.*.* . . *.* ** .*** *. '* ** '*

0063
0064
0065
0066
0067
0068

.~

0069 eOGO a6 fO

RESET

~

. . "'.* ** .....

*.-

** * "'* *** *

Reset.

.. '* ..... **,.. ........... *. * .... '" **

0070 e002 b7 05

STA
LOA
STA

0071 e004 a6 f(
0072 e006 b7 12

TUP PORT
_JR KEYPAD

'SFO

PORTi

SEWP PORTO
FOR ADDRESSES ETC.

P

0073
0074 e008 a6 cc
0075 eDOa c7 02 00

0076 eOad c7
0077 eOl0 c7
0078 e013 c7
0079 e016 c6
0080 e019 c7
0081 eOlc c6
0082 e01 f c7
0083 e022 c6
0084 e025 c7
0085 e028 c6
0086 e02b c7
0087 e02e c6
0088 e031 c7
0089
0090
0091
0092
009)
0094

e034
e037
e03a
e03d
e040
e043

c6
c7
c6
c7

c6
c7

02
02
02
eO
02
eO
02
eO
02
eO
02
eO
02
eO
02
eO
02
eO
02

e046
e048
e049'
e04a
e04c

ae

.-?O

e04e
e051
e053
e056
e057
eOSB
e059
eOSb
eOSd

cd
a6
d7
5c
5c
Sc
3a
26
8J

LOA
STA
STA
STA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA
LOA
STA

03
06
09
ac
01
ad
02
oe
07
af
OB
bO
04
b1
05
b2
00
b}
Ob

VEC'IORS IN RAM

i$Ce
IRQ
TIRQA
TIRQB
SIRQ

VECTOR
IRQ+l
VEC'roR+l

IRQ+2
VEC'IOR+2

TIRQB+l
VEC'IDR+3
TIRQB+2
VECTOR+4.

TIRQA+l
VEC'IDR+5

TIRQA+2
VEC'IDR~

6

SIRQ+l
VEC'IOR+ 7

SIRQ+2

0095
0096
0097
0098
0099
0100

7f
5c
a3 2e
23 fa

INIT

LOX
CLR
INCX
ePX
BLS

"STAT
0, X

JSR
LOA
STA
INCX
INCX
INCX
DEC

SCNBKP
*$FF
BKPTBL, X

CLEAR
WORKING
STORAGE

I BeNT
INIT

0101
0102
0103
0104
0105
0106
0107
0108
0109
0110

e6 1f
ff

02 16

29
[6

REBCLR

BNE

CLEAR
ALL
BREAKPOINTS

PNCNT
REBCLR

SWI

0111
0112

240

0113
0114
0115
0116
0117
0118
0119
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0149
0150
0151
0152
0153
0154
0155
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167

'" '* '* '" ** '" '" '* '" '" '" '* ** '" '" "' ... *. '" "' . . '* **

WW ...

'/L'

** ...... "' ..... ** ***.* '*.w ... ** '*

SWI.

'" _. '" ** *** '" ** '" '" '" "'.* '* •• *.* "'.- "'.* . . ** .*.* •• '" '" '" '" '" '" '" *. '" '* '" '"
eOSe
e061
e063
e065

00
10
20
b6

e067
e069
e06b
e06e
e0'71
e074
e077
e079
e07b
e07e
e080
eGa3
e086
e087
e088
e089
e08b
e08d
e090
e092
e094
e096
e098
e09a
e09c
e0ge

ae
bf
c7
cd
cd
d6
2b
b7
d6
b7
d6
cd
5c
5c
5c
3a
26
cd
e6
aD
e7
b7
e6
a2
e7
b7

20
20
4f
Oc
Dc
Oc
02
e6
e6
02
Od
22
02
23
02
e7

04

SWI

SWICHK

14
74
1f
16

STAY
SWIREP

17
18
57
SWINOB

29
e7
e1 23
08

01
08
23
07
00
07
22

NOPRQ

'" "'* ... '" '" '"

O,STAT,SWICHK

a,STAT

FROM RESET?

YES

GETCMO
TCR
ISOC
TCR

GET CURRENT TCR
SET XROM SO THAT EXTERNAL RAM
CAN BE WRI'M'EN' 'It)
SAVE CURRENT TCR

'IMP~R

KEYSCN
SCNBKP

REMOVE
BREAKPOI NTS

BKPTBL,X
SWINOB
ADORH
BKP'mL+l,X
AODRL

BKP'IBL+2 , X
STORE
GET NEXT B.P.

PNCNT

SWIREP
LOCSTK
8,X

FIND STACK
ADJUST PC
(MINUS 1)

11
8,X
AOORL
7,X
.0
7,X
ADORH

1, STAT, NOPRO
PROP
STORE

PROCEED

LOA
JSR
JMP

PCOUNT

PRINT P.C.

BRCLR

eOaD 03 20 06
eOa3 c6 02 15
eOa6 cd e7 57

eOa9 cc el 35

BRSET
BSET
BRA
LOA
LOX
STX
STA
JSR
JSR
LOA
8MI
STA
LOA
STA
LOA
JSR
INCX
INCX
INCX
OEC
BNE
JSR
LOA
SUB
STA
STA
LOA
SSC
STA
STA

'/I' '" '"

** ..... '" '" * .. '" "' ..... '" ** '" '" "' ... *. "' ........ '" * ••• ** * '" 11 "' . . . . .

Default interrupt vectors.
...... '* .. '* .... '* ............ 1""" * '* '* 1" ** '*1" '* * *** *1"*1"1" * .... *1"1" 1""" * ** * **'It
eOac
eOae
eObO
eOb2

e8
e8
e8
e8

9c
9c
9c
9c

VECroR

FOB
FOB
FOB
FOB

IRQV
TIRQBV
TIRQAV
SIRQV

IRQ
TIMER B
TIMER A
SERIAL

241

0168
0169
0170
0171
0172
0173
0174
0175
0176
0177
017B

Print logo

...... * ... ** . . ** ***
eOb4 cd e6 42
eOb? a6 e4

GETCMD

eOb9 c7 02 Dc
eObc cd e6 4c

DSCN

eOb! cd e6 74

CMDSCN

0179 eOc2 24 fb
0180 eOc4 Sf
01B1
0182
0183
0184

*._ .... * **** ** ** * ... ** ...... _. **** *** *** **

* ... '* ""* *** * ... *

eOcS c7 02 12

eOc8 d6 eO df
eOcb cl 02 12

RJUMP

eOce 27 Ob

0185 eadO cl e1 l f
0186 eOd3 27 df
0187 eOdS 5c
0188 eOd6 5c
0189 eOd? 5c
0190 eOdS 5c
0191 eOd9 20 ed
0192 eOdb 5c
0193 eOde de eO df

0194
0195 eOdf 11

P3UMP

PTABL

0196 eOeO cc e1 35
0197 eOe3 12
0198 eOe4 cc e1 4f

0199 eOe7 14
0200 eOe8 cc e1 6d
0201 eOeb 18
0202 eOec cc e1 8d

0203 eOef,28
0204 eOfO ee e8 9d
0205 eDD 24
0206 eOt4 ce e8 a3
0207 eDt? 32
0208 eOt8 ee e2 cf

0209 eOfb 34
0210 eOte cc
0211 eOft 38
0212 e100 ·cc
0213 e103 41
0214 e104 cc
0215 e107 48
0216 el08 cc
0217 e10b 51
0218 elOe ec

e3 46
e3 a7
e8 16

e2 19
e4 c5

0219 e10f 52

0220 ella
0221 e113
0222 e114
0223 e1l7
0224 el18
0225 e1lb
0226 e11-:
0227 ell f
0228 e120

cc e3 f1
54

cc e3 eb
62

cc e5
64
cc e6 e3
68
cc e6 25

0229
0230
0231
0232
0233
0234
0235
0236
0237 e123 ad 01
0238 OOel
0239 0025

0240 e125
0241 e126
0242 e128
0243 e12a

81
ae
a6
Sa
0244 e12b f1
0245 e12c 26
0246 e12e a6

7f
e1

fc
25
0247 e130 e1 01
0248 e132 26 f4
0249 e134 81
0250

LAST

"It

.*.

&

r**"

scan for keypress.

'* ... ** ** ... ** . . ** . . ** ... ** .. ** . . ****** ** ........

'It _ ....

JSR
LDA
STA
JSR
JSR
BCC
CLRX
STA
LDA
CMP
BEQ
CMP
BEQ
INCX
INCX
INCX
INCX
BRA
INCX
JMP

CLRTAB
I$E4
DTABL
DISTAB
KEYSCN
CMDSCN

FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP
FCB
JMP

$11
PCOUNT
$12

0

PROGRAM COUNTER

MEG

F

ACCUMlJLA TOR

$14
XREG
$18
CCODE
$28
PWRrMN
$24

S

INDEX REGISTER

D

CONDITION CODE

PRINT
PROMPT

CHECK KEYPAD

WORK1
M'ABL,X
WORK1
PJUMP
LAST
GETCMD

RJUMP
PTABL, X

THIS COMMAND?

YES

NO
GC TO
NEXT
POSSIBLE
TRY AGAIN
GO TO
COMMAND

WDWN

C

STOP

3

WAIT

9

CLEAR BP

$32

DISPLAY /SET BP

BPDIS
$34

BPCLR
$38
PROC
$41
XFER
$48

B

PROCEED 'ID NEXT INSTRUCTION
TRANSFER FROM EPROM TO RAM (OFFSET, $3COO I

OFFSET
$51
PUNCH
$52
TLOAD
$54
VERIFY
$62
NEWGC
$64
MEMEX
$68
STACK

A

OFFSET CALCULATION

P

OUTPUT S-RECORDS

L

LOAD S- RECORDS

V

VERIFY S-RECORDS

G

NEW GO (SKIP CURRENT BPI

M

MEMORY INSPECT/MODIFY

S

STACK

*** ** * **"* ** * ** * * * .. **.". * * * *"* * ** * *** ** * *** ** * ** * 1"1,, * 1,,* *
Search for stack

pointe~1

X <- SP-3

.. ** * .. * * ** * ** * ** * ** * **"*"It* * *"*"* * * * * ** ** * ** * * * * ** *** .. ** *
LOCSTK
STKHI
STKJ..CA<
LOCST2
LOCLOP
LOCDWN

BSR
EQU
EQU
RTS
LDX
LOA
DECX
CMP
BNE
LOA
CMP
BNE
RTS

IDCST2

-$8000+* /256+$80
-256*STKHI+*
1$7F
ISTKHI
O,X
IDCrMN

.STKLOW
l,X

lDelDP

242

0251
0252
0253
0254
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282
0283
0284

Display program counter.

e135 a6 73
e137 c7 02 10

PCOUNT

e13a a6 dl
e13c c7 02 11

eDf ad e2
e141 e6 07
e143 b7 22
e145 e6 OS

e147 b7 23
e149 cd e8 02
e14c cc eO bf

LOA
STA
LDA
STA
BSR
LDA
STA
LDA
STA
JSR
JMP

PRINT
'PC'

'$73

DTABL+4
.$01

DTABL+5
weSTK
7,X
ADORH
8,X
ADDRL
PRTAOR
CMDSCN

FIND USER PC
HIGH BYTE
LOW BYTE

PRINT IT

Accumulator examine/change.

e14f a6 77
e151 c7 02 Oc
e154 c7 02 Of

AREG

e157 a6 dl
e159 c7 02 Od

elSe c7 02 Oe
elSf ad c2
e161 9f
e162 ab 05

e164 3f 22

0285 e166 b7 23

0286 e16B Ie 20
0287 e16a cc e6 ea
0288
0289
0290
0291

LDA
STA
STA
LDA
STA
STA
BSR
TXA
ADD
CLR
STA
BSE:]'
JMP

PRINT 'ACCA'

.$77
DTABL

DTABL+3
'$D1

DTABL+l
DTABL+2
WCSTK

FIND ACCUM. VALUE

.5
ADORL

ADDRH

SEWP FOR
EXAMINE/CHANGE

6, STAT
MEMEX3

USING MEMORY ROUTINE

Index reg. examine/change.

0292
0293
0294

0295
0296 e16d
0297 e170
0298 .e172
0299 e175
0300 e177
0301 el7a
0302 e17e
0303 el7f

cd
a6
c7
a6
c7

e6
06
02
e6
02
a6 60
c7 02

42

XREG

Od
Oe
Of

ad a2

0304 e181 9f

0305 e182 ab 06
0306 e184 3f 22
0307 e186 b7 23

0308 e188 Ie 20
0309 elBa cc e6 ea
0310
0311
0312
0313
0314
0315
0316

CLRTAB
PRINT'Idr'

.6

DTABL+l
#$E6

DTABL+2
.$60

DTABL+3
LOCSTK

FIND INDEX
REGISTER VALUE

16
ADDRH
ADDRL
6, STAT

SE'IUP FOR
EXAMINE/CHANGE

MEMEX3

USING MEMORY ROUTINE

CC reg. examine/change.

0317 elBd cd e6 42
e190 a6 dl

0318
0319
0320
0321
0322
0323
0324
0325
0326
0327
0328
0329
0330
0331
0332
0333
0334

JSR
LDA
STA
LDA
STA
LuA
STA
BSR
TXA
ADD
CLR
STA
BSE:]'
JMP

e192
e195
e197
e19a

02 Oc
d7
02 Od
e6
e19c c7 02 Oe
e19f a6 f1

elal
ela4
ela?
elaS
elaa
elac
elae
elbO

c7
a6
c7
a6

c7
cd
9f
ab
3f
b7
Ie
cc

02 Of
e1 23
04
22
23

20
e6 ea

CCODE

JSR
LDA
STA
LDA
STA
LOA
STA
LDA
STA
JSR
TXA
ADD
CLR
STA
BSE:]'
JMP

CLRTAB
'$D1
DTABL
'$D7

DTABL+l
'$E6

DTABL+2
I$F1

DTABL+3
LOCSTK

FIND CONDITION
CODES

14
ADDRH
ADDRL
6,STAT
MEMEX3

SEWP FOR
EXAMINE/CHANGE

USING MEM:JRY ROUTINE

243

0335
0336
0337
0338
0339
0340
0341
0342
0)43 elb3 19 20
0344 e1b5 cd e6 42
0345 elba a6 f4
0346 elba c7 02 10
0347 elbd a6 77
0348 e1bf c7 02 11
0349 elc2 cd e6 4c
0350 elc5 cd e7 .0
0351 e1c8 24 25

'* ...................... w* ... ** . . * .... ** * ** * ** ... "' ... '* ** * ... '*"'.'It" •• * ** ... 1<* ...
Build a beginning and ending

address range.
TEMP, TEMP+ 1 - ADDRH, ADORL .

... ** .. ** ... ** .. ** ... *,.. * ... * * * ... * * ...... * ... * ... * * ** ... * * * ** . . **
BLDRN:;

0352 elca b6 22
0353 elcc b7 27
0354 elce b6 23
0355
0356
0357
0358
0359
0360
0)61
0)62
0363
0) 64
0365
0366

e1dO
e1d2
eld5
eld7
elda
eldc
eldf

b7
cd
b7
cd
a6
c7
a6

28
e7 46
26
e6 42
f1
02 10
77

e1e1 c7 02 11
e1e4 cd e6 4c
e1e7 cd e7 .0

elea
elec
0367 elee
0368 e1ef
0369 elfl
0370
0371
0372
0373
0374
0375
0376
0377 elt2
0378 e1t4
0379 elf6
0380 e1t8
0]81 e1 fb
0382 e1 fd
0383 e200
0384 e202
0385 e204
0386 e206
0387 e208
0388 e20a
0389
0390 e20d

24 03
b6 22
81
18 20
81

BLDRNl

BeLR
JSR
LOA
STA
LOA
STA
JSR
JSR
BCC
LOA
STA
LDA
STA
JSR
STA
JSR
LOA
STA
LOA
STA
JSR
JSR
BCC
LOA
RTS
BSE:]'
RTS

PRINT
'SA'

CLRTAB
1$F4

DTABL+4
1$77
DTABL+5
DISTAB
GET SOURCE ADDR.

BLDADR
BLORN1
ADORH
TEMP
ADORL
TEMP+l
LOAD

VALID?

YES
NO SAVE IT

FE'I':H OPCODE OF INSTR.
SAVE IT

WJRK6
CLRTAB

PRINT 'EA'

1$F1
DTABL+4
1$77
DTABL+5
OISTAB
BLDRNI

GET DESTINATION ADDR
VALID?

ADORH

YES

4.STAT

INVALID

BLDADR

Display message,

bf
3t
be
d6
be
d7
3c
3c
b6
a1
25
cc

26
2b
26
e2 Od
2b
02 OC
26
2b
2b
06
ec
e6 4c

00 00 dO d7 77 e6
0391 e213 d6 f1 60 06 71 b6
0392
0393

DISP

DISLP

DLOAD

VERF

STX
CLR
LOX
LOA
LOX
STA
INC
INC
LOA
CMP
BLO
JMP
FCB
FCB

*.-,.,. ** * ** *

4,STAT

~RK6

COUNT
I>.DRK6
DLOAD,X
COUNT
DTABL, X
~RK6

COUNT
COUNT
16
DISLP
DISTAB
0,0,$00, $07, $77, $E6
$06, $F1, $60, $06, $71, $B6

244

0394
0395
0396
0397
0398
0399
0400 e219 ad 98
0401 e21b 08 20 3e
0402 e21e b6 23
0403

.... "' .. "''It'" ** ** .... ** '" ** * ** "'.'* .... "' .. ** '" ** .. ** *** fr "' .. *'* '" * ** ........
Calculate branch of fset.

.. '* * .... ** ** .. * .. * ** ...... *** * ...... * ... * ........ * * ** * '1<*" ** .. ** ..............
OFFSET

0404 e220 aD 02

0405 e222 b7 23
0406 e224 b6 22
0407 e226 a2 00
0409 e228 b7 22

0409 e22a b6 23
0410 e22c bO 28

BSR

BLDRNG

BRSET

4, STAT,ORE"!'

LOA

ADORL

SUB
STA
LOA
SBC
STA
LOA
SUB

12
ADORL
ADORH
10
ADORH
ADORL
TEMP+l

OFFSET

STA
LOA
SBC
STA
LOA
CMP
BLS
LOA
CMP
BEQ
TSTA
BNE

ADDRL
ADORH
TEMP
ADORH
WJRK6
1$1F

CHECK OPCODE
FOR BIT BRANCH

NO FIND APPARENT

0411
0412 e22e b7 23

0413 e230 b6 22
0414 e232 b2 27
0415 e234 b7 22
0416 e236 b6 26
0417 e238 at 1f
0418 e23a 23 50
0419 e23c b6 22
0420 e23e al ff
0421 e240 27 Ob
0422 e242 4d
0423 e243 26 7a
0424
0425 e245 b6 23
0426 e247 a1 7f
0427 e249 22 74
0428 e24b 20 Oa
0429
0430 e24d b6 23
0431 e24f at ff
0432 e251 27 6c
0433
0434 e253 at 80
0435 e255 25 68
0436
0437 e257 ad 06
0438 e259 cc eO
0439 e2Se cc eO
0440
0441 e25f cd e6
0442 e262 a6 d6
0443' e264 c7 02
0444 e267 a6 b5
0445
0446

LOA
CMP
BHI
BRA
OFFST2

OKl
bf
b4

ORET

42

USE

Oc

OFFSTl
ADORH
I$FF
OFFST2
OVRERR

+ OR - OFFSET?

CHECK OFFSET
FOR +/- a

ADORL
1$7F
OVRERR

OK1

LOA
CMP
BEQ

OVRERR

ADDRL
I$FF

CMP
BLO

OVRERR

1$80

BSR
JMP
JMP

CMoseN

USE

JSR
LOA
STA
LDA

CLRTAB
*$06
OTABL
*$B5

PRINT IT IF VALID

GETCMO

PRINT 'USED'

245

0447
0448
0449
0450
0451
0452
0453 e269

If

Branch offset
.. 11 ... " • • '"

7 02 Od

0454 e26·
0455 e26.

,6 f1

0456 e27)

6 e6

e278
e27b
e27,
e27.
e280
e2B

d
7
06
,b
07
06

02 Df
23
e7 d6

28
01
23
27
e2BQ .9 00
e281J 07 22
e288
f
e289 cc e7 57

0469
0470 e2Se D6
04n e2Se .0
0472 e290 07
0473 e292 06
0474 e294 .2
0475 e296 07
0476 e298 dl
0477 e29a 27
0478 e29c 4d
0479 e29d 26
0480 e29t 06

23

OFFSTI

SUB

23
22
00

STA

LOA
SBC
STA
CMP
BEQ
TSTA
BNE
LDA
CMP
BHI
BRA

if
Db
20
23

0481 e2al al 7f
0482 e2a3 22 la
0483 e2aS 20 De

0484
0485 e2a7 b6 23
0486
0487
0498
0489
0490
0491
0492
0493
0494
0495
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506

e2a9
e2ab
e2ad
e2af
e2bl
e2b3

a1
27
a1
27

LDA

01

22

OFFST3

ff

12
te
De

al 80
25 0.

e2b5
e2b7
e2b9
e2bb
e2bd

3c
26
3c
ad
20

28
02
27
a2
Od

e2bf
e2cl
e2c4
e2c6
e2c9
e2cc

a6 d7
c7 02
a6 60
c7 02
cd e8
cc eO

0K2

OFFITS
OVRERR
10

11
02
bf

CMDJMP

(continued) .

** ....... '* •• '" 'fI_", 1,,,* .'11 •• _** ** ... ** ••• * _.... **,...* ....... ** ...
STA
LDA
STA
LOA
STA
LDA
JSR
TAX
LDA
ADD
STA
LDA
ADC
STA
TXA
JMP

'7 02 De

0457 e273
0458 e276
0459
0460
0461
0462
0463
0464
0465
0466
0467
0468

** ... ** ... ** * ** "'._ ........... ** ..... '* ........ 1\> .. "' .. ** ... ** ... * .... _* .. ** ... ** .... '* '"

DTABL+l
ISFI
DTABL+2
ISE6
DTABL+3

PRINT OFFSET

ADDRL
?RTDAT
TEMP+l

11
ADDRL
1EM?
10
ADDRH

PUT IN'ro

INSTRUCTION

STORE
ADDRL
U
ADDRL
ADDRH
10
ADDRH
ISFF

OFFST3

A[}J1JST FOR
BIT BRANCH

NEG OFFSET?
YES
CHECK FOR

+/- 0 AND -1

OVRERR
ADDRL
1$7F
OVRERR

OK2

ADDRL
i$FF

LOA
CM?
BEQ
CMP
SEQ
CM?
BLO

OVRERR
*$FE
OVRERR

INC
BNE
INC
BSR
BRA

TEMP+ 1
OFFITS
!EM?
USE
CMDJMP

LDA
STA
LOA
STA
JSR
JM?

DTABL+4
1$60
DTABL+5
PRTADR
CMDSCN

BHI ?

'$80
OVRERR

PRINT IF VALID

.$07

PRINT OR

246

............... * ...........................................................

0507

050B
0509
0510

Display/set breakpoints.

........ fr.""" * .. * '* .... '* .... '* '* '* .......... fr .......... '* ........... '* ..............

0511

0512
0513
0514
0515
0516
0517

e2cf 3f 26
e2d1 3a 26
e2d3 cd e6 1f

e2d6 bf 21
e2dB 4f

0518
0519
0520
0521
0522
0523
0524
0525
0526
0527

e2d9
e2dc
e2df
e2e1
e2e3
e2e6
e2e8
e2eb
e2ed
e2fO
0528 e2 f3

c7
d6
2a
a6
c7
a6
c7
a6
c7
c7

0530
0531
0532
0533
0534

d6
b7
cd
3c
be

02
02
14
f4
02
d7
02
71
02
02

BPDIS1

10
16

Oc
Od
De
Of

20 Oa
0529 e2f5 b7 22
e2f7
e2fa
e2 fc
e2ft
e301

B~DIS

BPOIS2

02 17
23
e8 02
26
26

BPDIS4

0535 e303 d6 e7 6e
0536 e30S c7 02 11
0537 e309 cd e6 4c
0538 e30c cd e7 aD
0539 e30f be 21
0540 e311 25 08
0541 1>313 al 10
0542 e315 27 19
0543 e317 al 11
0544 e319 27 Oa

0545
0546
0547
054B

e31b
e31d
e320
e322

b6
d7
b6
d7

22
02 16
23
02 17

0549 e325 5c
0550 e326 5c
0551 e327 5c

BPOIS7

BPDISS

INCX

BPRET

INCX
INCX
STX
OEC
BNE
BRA
JMP

0552 e32B bf 21
0553 e32a 3a 29
0554.e32c 26 aa

0555 e32e 20 9f
0556 e330 cc eO b4

0557
0558
0559
0560
0561
0562
0563
0564
0565
0566

e333
e336
e338
e33b
e33d
e340
e343

cd
a6
c7
a6
c7
c7
cc

e6 42

f1
02
60
02
02
eO

Od
Oe
Of
be

CLR
OEC
JSR
STX
CLRA
STA
LOA
BPL
LOA
STA
LOA
STA
LOA
STA
STA
BRA
STA
LDA
STA
JSR
INC
LOX
LOA
STA
JSR
JSR
LOX
BCS
CMP
BEQ
CMP
BEQ
LOA
STA
LOA
STA

ERROR

JSR
LOA
STA
LOA
STA
STA
JMP

>ORK6
>ORK6
SCNBKP

FIND B.P. TABLE

>ORK2
DTABL+4
BKP'IBL. X
BPOIS2
.SF4
DTABL
IS07
DTABL+1
IS71
DTABL+2
DTABL+3
BPOIS4
ADORH
BKPTBL+1,X
ADORL
PRTAOR
>ORK6
w)RK6
CTABL. X
DTABL+5
DISTAB
BLOADR
>ORK2
SPDIS7
ISI0
BPRET
IS11
.BPOIS5
ADORH
BKPTBL.X
ADORL
BKPTBL+1, X

GET B.P.
VALID?
NO

PR INT • BOFF'

PRINT B. P.

PRINTS.P.

I

NEW B.P.

YES
NO,ESC?
GET 0lrI'
ENTER?

GET NEXT B.P.
S'KlRE NEW B.P.

GET NEXT B.P.

>oRK2
PNCNT
BPOISI
BPOIS
GETCMO

DONE?

YES STA~T OVER

CLRTAB

iSFI
DTABL+l

IS60
DTABL+2
DTABL+3

OSCN

247

0567
0568
0569
0570
0571
0572
0573
0574
0575
0576
0577
0578
0579
0580
0581
0582
0583

0584
0585
0586
0587
0588
0589
0590
0591
0592
0593
0594
0595
0596
0597

***********._*******_***'IIr***********"".**********W"'**
Breakpoint clear.

.. * .... ** ..... _..... * .... 'It * *""""_ 'It • • * 'It _* .... *_ . . *. ,*.t'" * ................. 'It * *.
e346
e349
e34b
e)4e
e350
e353
e355
e358
e3Sa
e35d
e360
e363
e365
e368

a6
c7
a6
c7
a6
c7
cd
cd

bf
cd
25

BPCLR

dl
02 Od
dO
02
60
02
e6
e6
21
e7
14

De

Of
4c
1f
90

e36a alII
e36c
e36e
e370
e372
e375
e376
e377
e378
e37a
e37c

0598 e37e
0599 e3S0
·0600 e382

0601 e383
0602 e386
0603 e389
0604
0605
0606
0607

cd e6 42
a6 f4
c7 02 Dc

e3Ba
e3Sc
e38e
e38t
0608 e391
0609 e393
0610 e396

26
a6
be
d7
5c
Sc

36

if
21
02 16

BPCLR2

Sc
3a 29
26 f6
20 26
al 03
24 b1
97
46 e7 6e
c7 02 11
4f
aO 03
ab 03
Sa

BPCLR1

BPCLR3

2a fb
b7 26
cd e6 4c
cd e6 bb

0611 e399 alII
0612 e39b 26 07
0613 e39d be 26
0614 e39f a6 ff

0615 e3aI d7 02 16
0616 e3a4 cc eO b4

BPCRET

JSR
LOA
STA
LOA
STA
LDA
STA
LOA
STA
JSR
JSR
STX
JSR
BCS
CMP
BNE
LDA
LOX
STA
INCX
INCX
lNCX
DEC
BNE
BRA
CMP
BHS
TAX
LOA
STA
CLRA
SUB
ADD
OECX
BPL
STA
JSR
JSR
CMP
BNE
LOX
LDA
STA
JMP

CLRTAB
I$F4
DTABL
1$01
DTABL+l
1$00
DTABL+2
1$60
DTABL+3
OISTAB
SCNBKP
IDRK2
GETNYB
BPCLR1
1$11
BPCRET
I$FF
IDRK2
BKPTBL.X

PNCNT
BPCLR2
BPCRET
13
ERROR
CTABL.X

PRINT 'BCLR'

FIND B.P. TABLE

ENTER?

NO
YES. CLEAR ALL

VALID B.P. I?
NO
YES
PRINT B. P .

•

DTABL+5
FIND IT
i3

13
BPCLR3
IDRK6
DISTAB
CHRIN
1$11
BPCRET
IDRK6
'$FF
BKPTBL.X
GETCMO

PRINT B.P.
CLEAR IT?
NO
YES

0617
0618

248

0619
0620
0621
0622
0623
0624
0625
0626
0621
0628
0629
0630
0631
0632
0633
0634
0635
0636
0637
0638
0639
0640
0641
0642
0643
0644
0645
0646
0647
0648
0649
0650
0651
0652
0653

'* '*. '* ** '* *** ** •••••• *..,.'* ** .. It. '* *** ** ... *** ** .** *** '* ** '* •• '*

Proceed.

'* ** '* •• '* ••• *** ••• ***.* .. *** ....... *** *** .*.*** ••• **'*** ...
e3a7 12 20

PROC

1.STAT
LOCSTK
7.X
ADORH
TEMP
8.X
ADDRL

e3cb b7 22

BSsr
JSR
LOA
STA
STA
LOA
STA
STA
JSR
LSRA
LSRA
LSRA
LSRA
TAX
LOA
ADD
STA
LOA
ADC
STA

e3ed
e3dO
e3d3
e3d5

JSR
STA
LOA
JSR

LOAD
PROP
1$83
STORE

JHP

NeONI'

FCB

3.2.2.2.1.1.2.1.1.1.2.2.3.3.2.1

e3a9 cd el 23
e3ac
e3ae
e3bO
e3b2
e3b4
e3b6
e3b8
e3bb
e3bc
e3bd
e3be
e3bf
e3cO
e3c3
e3c5
e3c7

e6
b7
b7
e6
b7
b7
cd

07
22
27
08
23
28
e7 46

44
44

44
44
97
d6
bb
b7
b6

e3 db
23
23
22

e3c9 a9 00

cd
c7
a6
cd

e7 46
02 15
83
e7 57

e3d8 cc e5 d3

e3db 03 02 02 02 01 01
02 01 01 01 02 02
03 03 02 01

MAT

SET PROCEED FLAG
FIND S.P.

TEMP... 1

LOAD

GET OPCODE

MAT. X
ADDRL
ADDRL
ADDRH

NUMBER OF BYTES THIS INSTRUCTION
CALCULATE NEXT ADDRESS AND HOVE
CURRENT BREAKPOINT TO IT

X <- MSB

to
ADDRH

0654
0655

249

0656
0657
0658
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679
0680
0681
0682
0683
0684
0685
0686
0687
068B
06B9
0690
0691
0692
0693
0694
0695
0696
0697
0698
0699
0700
0701
0702
0703
0704
0705
0706
0707
070B
0709
0710
0711
0712
0713
0714
0715
0716
0717
071B
0719
0720
0721
0722
0723
0724
0725

... ", '* ............ '"

fI W

RS232

** .. '*. '* ****'*. ** 'If ** * ** ... w* * ** * ** ............ it ... * ........... *
(9600) S-Record receiver (EO at 4MHz).

.. ** .... 1o"'''' **w ** ..... ",* ... ****** ** .. ** ... ** * ** ... ** *** ... ** ... **._ .. *
e3eb la 20
e3ed
e3ef
e3fl
e3f3
e3f4
e3!6
e3t8

ae

20
1b
Sf
a6
b7

06
03
20

81
24
cd e1 f2

e3tb ad 5c
e3fd al 53

VERIFY

TLOAD
L4

INPUT

e3ft 26 fa
e401 ad 56
e40) 01 39
e405 27 60
e407 01 31
e409 26 fO
e40b
e40d
e40 f
e412

3f
3f
cd
b7

2a
2d
e4 Ba
2e

LNGTH

e414
e417
e419
e41c

cd
b7
cd
b7

e4 Sa
22
e4 Ba
23

ADOR

e41e
e421
e423
e426
e428

cd
27
Db
b7
cd

e4 Ba
Ie
20 Ob
26
e5 4b

DLOP

e42b bl 26
e42d
e42f
e431
e434
e437
e439
e43b
e43d
e43f

26
20
cd
c1

57
08
e5 4b
02 13

L5

26 3d
3c
26
3c
20

23
02
22
dd

L6

NOOVR

BSE'!'
LDX
BRA
BCLR
CLRX
LDA
STA
JSR
BSR
CMP
BNE
BSR
CMP
BEQ
CMP
BNE

5,STAT

SERIAL VERIFY

16
L4
5, STAT

SERIAL LOAD

1$81
..:lRlO
DISP

INCHD
• 'S'
INPt.rI'
INCHD
. ' 9'
NINE

• 'I'
INPUT

CLR
CLR
JSR
STA

CHKSUM
TMP2
BYTEI
BeNT

JSR
STA
JSR
STA

BYTEI
ADDRH
BYTEI
AODRL

JSR
BEQ
BRCLR
STA
JSR
CMP
BNE
BRA
JSR
CMP
BNE
INC
BNE
INC
BRA

BYTEI
CHCK
5, STAT, L5
..:lRK6
RAMACC
..:lRK6
ERR?

L6
RAMACC
WORK4
ERR2

ADDRL
NOOVR
ADDRH
DLOP

7 BIT ASCII IN'ro A
S ?
NO, TRY AGAIN
YES, GET NEXT CHARACTER
9 ?
YES, FINISH
NO, 1 ?
NO, TRY AGAIN
YES, CLEAR CHECKSUM
AND TEMP. S'IDRE

AND GET BYTE COUNT
AND SAVE IT

ADDRESS HIGH
ADDRESS LOW

3
5
4
30
3
3
3
56
3
3
5
3
5
3

75
7B
B3
B7
117
120
123
126
139
142
145
150
153
15B
161

GET A BYTE
LAST BYTE ?
NO, VERIFYING ?
YES
READ RAM
SAME

NO, WRITE

'It)

* 'II" * * 'II" * * '11"'11" * ** 'II" ** 'II" ** ... ** ... ** 'II" *fI * * * * ... * * ** * ** * ** * ** * *** ** w
Checksum byte & error rout ine.

* * fI * * * * w* * ** '* * * * ** * w* * '* * * * ww* w* ** * *'11" '* fI fI,* '** * '** w** * '* * *
e441
e443
e445
e447

bb
b7
a1
27

e449
e44b
e44c
e44f
e450
e453
e456

ae
9t
cd
4f
c7
cd
cc

2a
2a
ff
b2

CHCK

01

ERR
e7 d6

02 10
e8 02
eO bl

ADD
STA
CMP
BEQ

CHKSUM
CHKSUM
*$FF

LOX

11

TXA
JSR
CLRA
STA
JSR
JMP

DTABL+4
PRTADR
CMDSCN

INPtlI'

DEBUG
IS CHECKSUM BYTE OK ?
YES, AND AGAIN

PRTDAT

250

RAM

READ-BACK OK ?
5 131
INCREMENT LS ADDRESS
3 134
OVERFLCW ?
5 139
YES, INC. HIGH BYTE
3 142

0726
0727
0728
0729
0730
0731
0732
0733
0734
073S
0736
0737
0738
0739
0740
0741
0742
0743
0744
0745
0746
0747
0748
0749
0750
0751
0752
0753
0754
0755
0756
0757
0758
0759
0760
0761
0762

,...* ................ * •••••• * •• ** '* ...... * ....... * .... " '* * ..... *
Input routine, MC68HCOSEO : 0.5 uS.
Cycles per hi t at 9600 baud : 208.
........... * ... * .. *** _'II''' ** ••••••• ** .. ** .. * ...... * .... * * * .. * ..... ** ... '* ..
e459
e4Sb
e4Se
e461
e463

ad
OS
04
ae
bf
e465 ad

60
01 fd
01 fd
07
2b
58

e467 ad 52

e469
e46c
e46d
e46f

INCHD
INCH

OS 01 00
46
3a 2b
26 f6

INBT
ZER

e471 44
e472 81

BSR
BRCLR
BRSET
LOX
STX
BSR
BSR
BRCLR
RORA
DEC
BNE

DEL191
2. PORTB,

COUNT
DEL11 0

DEL191
2. PORTB. ZER
COUNT
INBT

6
10
120

191
S
3
5
3

196
199
204
207
16
22

NINE

JMP

GETCMD

e476
e478
e47a
e47c
e47e

ERR2

LOX
BRA
LOX
BRA
LOX
BRA
LOX
BiV\
LOX
BRA

12
ERR
*3
ERR
t4
ERR
*5
ERR
17
ERR

02
d1
03
cd
04

ERR3
ERR4

e480 20 c9

e482 ae as

ERRS

e484 20 c5
e486 ae 07
e488 20 cl

ERR?

GET OUT OF BIT 7
IS LINE HIGH ?

191
S
S
2
4
110

LSRA
RTS

e473 cc eO b4
ae
20
ae
20
ae

'*

2. PORTB.'"
17

YES. WAIT FOR START
7 DATA BITS 'l\) READ
WAIT TILL MIDDLE OF 1st BIT
+/-3

+120-208=103
eYe 2 (lOS) READ
SAVE BIT

MSB A ZERO

RAM REAOBACK
LESS 'lHJ\N ASCII 0
BETWEEN ASCII 9

&

MORE '!HAN ASC I I F
VERIFY ERROR

251

A

0763
0764
0765
0766
0767
0768
0769
0770
0771
0772
0773
0774
0775
0776
0777
0778
0779
0780
0781
0782
0783
0784
0785
0786
0787
0788
0789
0790

*** '" * ** *** ** '*

w. '* * * ... ** '* * .. * ** ... ** '" ** ... _* ***.* _'II"'. ** ... ** '*

Byte input sub-routines.

* .... * * ••• * '* * ..... * ....... * '* * * .. * * * * * '* * * .". * * ... " * .... * * ** * * '" * * .. '* *
e48a ad cd

BYTE I

e48c ad 17
e48e 48
e48t 48
e490 48
e491 48
e492 b7 2c
e494 b6 2d
e496 bb 2a

e498 b7 2a
e49a ad bd
e49c ad 07

e4ge bb 2c
e4aO b7 2d
e4a2 )a 2e
e4a4 81

e4a5
e4a7
e4a9
e4ab
e4ad

al 30
25 dl
al 39
22 03
aD 30
0791 e4af 81
0792
0793 e4bO al 41
0794 e4b2 25 ca
0795 e4h4 al 46
0796 e4b~ 22 ca
0797 e4bS a0 )7
0798 e4pa 81
0799
0800 e4bb ae Id
0801 e4bd 20 02
0802 e4bf ae 10
0803 e4cl Sa
0804 e4c2 26 td
0805 e4c4 81

ASCII

MT9

BSR
BSR
LSLA
LSLA
LSLA
LSf,.A
STA
LDA
ADD
STA
BSR
BSR
ADO
STA
DEC
RTS
CMP
BUl
CMP
BHI
SUB
RTS

TI>1Pl
TI>1P2

22
35
3
3
3
3
4
3

CHKSUM

CHKSUM

INCHD
ASCII
TI>1Pl
TI>1P2
BeNT

)5
)

4
5
6

MS NIBBLE

69
73
76
79
83
22
57
60
64
69
75

1$30

BEFORE ZERO '?

MTSt

10

#$30

13

*$41

YES, NOT LEGAL
AFTER NINE
YES TRY A-F
0-9, CONVERT TO HEX

19

SUB

'$37

23

LOX
BRA
LOX
DECX
BNE

ADO TO MS NIBBLE
SAVE BYTE
DECREMENT BYTE COUNT

.$39

ERR5

DEL191

WHAT WAS IT

ERR)

12
15
17
20

RTS

WHAT WAS IT
OK
SHIFT
IT
UP
AND SAVE IT
RESTORE BYTE
ACCUMULATE
IN CHECKSUM BYTE
LS NIBBLE

57

eMP
BUl
CMP
BHI

NF1JD

DELllO
DELAY

INCHD

ASCII

ERR4
.$46

BEFORE A ?
YES,

NOT LEGAL

AFTER F ?
YES, NOT LEGAL
A-F, CONVERT TO HEX

29

#29
DELAY

.16

x

DELAY

X

12+6X (INC BSR)

~TS

0806
Oa07

252

0808
0809
0810
0811
0812
0813
0814 e4cS 14 06

'* ** * ** '* *** .** ** .** * '* ** *** ** **** *** ** '* *** ** *** '* ** '* •• *
RS232

PUNCH

0815 e4c7 cd e1 b3
0816 e4ca 08 20 a6
0817
0818
0819
0820
0821
0822
0823
0824
0825
0826
0827
0828
0829
0830
0831
0832
0833
0834
0835
0836
0837
0838
0839
0840
0841
0842
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856

e4cd
e4cf
e4d1
e4d3
e4d5
e4d7
e4d9
e4db

be
b7
bf
b6
be
bf
b7

e4dd
e4df
e4e1
e4e3

b6 28
bO 23

27
27
22
23
28
23
28
1f 20
LOOP1

b7 26
b6 27
e4e5 b2 22

e4e7 26 Od
e4e9 b6 26
e4eb 4c
e4ec 27 08
e4ee a1 20
e4f0 22 04

e4f2 Ie 20
e4f4 20 02
e4f6
e4f8
e4fa
e4fc

a6
ab
b7
a6

e4fe
e501
e503
e505
e507
e509

cd e5 63
a6 31
ad se

3f
b6
cd
e50c b6
e50e cd
e511 b6
e513 ad

20
03
2e
53

LOTS
LTE20

2a
2e
e5 8f
22
e5 8f

23
7a

9515 cd e7 46

LOOP2

e518 3c 23

0857 e51a 26 02
0858 eSlc 3c 22
0859 e51e ad
0860 e520 26
0861
0862
0863
0864
0865
0866
0867
0868
0869 e522 b6
0870 e524 43
0871 e525 ad
0872 e527 ad
0873 e529 Of
0874

6f
f3

(9600 Q 411Hz) S-Record output.

******************* •• *******,****.,**********iI********

NOVR

BSET
JSR
BRSET
LDX
STA
STX
LOA
LDX
STX
STA
BCLR

2, PORTBD
BLDRNG
4, STAT,NlNE
TEMP
TEMP
ADDRH
ADDRL

BIT 2 OUTPUT
BUILD RANGE
NEW ADDRESS ENTERED ?
NO, SWAP ADDRESSES

7,STAT

CLEAR END FLAG

LOA
SUB
STA
LDA
SBC
BNE
LDA
INCA
BEQ
CMP
BHI
BSET
BRA

TEMP+l
ADDRL

END LSB
CURRENT [sB
DIFFERENCE LSB
END MSB
CURRENT MSB
MSB ZERO?
YES, LOOK AT LSB
ADJUST
WAS $FF ?
MORE 'mAN 23 ?
IF SO USE 23
NO, LAST S 1 RECORD
LESS THAN OR EQUAL TO 20

TEMP+l
ADDRL

TEMP+l

~RK6

TEMP
ADDRH
LOTS
'-ORK6
LOTS
1$20
LOTS
7,STAT
LTE20

LOA
ADD
STA
LDA
JSR
LOA
BSR
CLR
LDA
JSR
LOA
JSR
LOA
BSR

1$20
1$03
BeNT
1 'S'
OUCH
I' l'
OUCH
CHKSUM
BeNT
BYTEO
ADORH
BYTEO
ADDRL
BYTEO

JSR
INC
BNE
INC
BSR
BNE

LOAD
ADDRL
NOVR
ADDRH
BYTEO
LOOP2

ADD BYTE COUNT & ADDRESS
No. BYTES THIS Sl RECORD
S

BYTE COUNT
ADDRESS HIGH

ADDRESS LOW
GET BYTE
INCREMENT ADDRESS

OVERFlDW ?
YES, INC. HIGH BYTE
SEND BYTE
LAST BYTE ?

............. ** .. ** .. ** ..... tr .. ** * .... 11" W*'I' ** .. *fr. ft"" ** .** .. ** *.w .. *" ...
Checksum byte.

• 'II"
2a

68
34
20 b1

'II

** * ** .. _* '" ** ......... ** .. ** .... 97
e699
e69b
e69d

26
99
b6
as
26
ad

12
00
Of
fa
Oa

COLI

e69f b6 00

e6al a5 Of
eGa3 26 f2
e6a5 c6 02 12
e6aS 81

COLRET

LDA
STA
BIT
BEQ
BSR
LOA
CMP
BNE
SEC
LOA
BIT
BNE
BSR
LOA
BIT
BNE
LOA
RTS

*_ . ** * ** .. ** ... _...

READ KEYPAD
STORE IT
KEY CLOSED?
NO GET OUT
ELSE DEBOUNCE
RE-READ KEYPAD
SAME KEY CLOSED?
NO GET OUT
SET FLAG FOR VALID
KEY

PORTA
w:lRKI
ISOF
COLRET
DSOUNC
PORTA
w:lRKI
COLRET
pORTA
I$OF
COLI
DSOUNC
pORTA
I$OF
COLI
w:lRKI

RELEASED?

NO TRY AGAIN
YES DEBOUNCE
STILL
RELEASED?

NO TRY AGAIN
RE'IURN CHAR IN A-REG
YES GO HOME

1166

1167
116B
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
llB1
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200

.. 'fr . . . . . ,.. ........

** .. ** .. ** .. * .... fIo .. ** 1: .. ,.. .. ** ......... ** ....... * .. 11""'" ** *

Pause tor 3075 cycles.

.... .., ......................... ** ........ * .. "' ...................... *fr .. **"'''''''.1r .. '''' *
e6a9 a6 Oa
e6ab
e6ad
e6af
e6bl
.6b3
e6b4
e6b6

e6b8
e6ba

b7
a6
21
21
4a
26
3a
26
81

25
ff
fe
fe

DSOUNC
DLP
DLOOP

f9
25
f3

"'.* .. ** ....

LOA
STA
LOA
BRN
BRN
DECA
BNE
DEC
BNE
RTS

11" . . .

110
w:lRK5
I$FF

40mS
PAUSE
256XI2
CYCLES
OR AT
LEAST 3 .7mS

DLOOP
w:lRK5
DLP

* ......... *. * ....... ** * ... *** _** "' .... ** .. *** ** ... _..

Input one character, A contains value.
.. ** ........... "' ...... ** .. * .... 'II' *"'* .. t
e6bb
e6be
e6cO
e6cl
e6c4

e6c6
e6c7
e6c9
e6ca

cd
24
5f
dl
27
5c
20
9f
81

e6 74
fb

CHRIN

e6 cb
03

CHRINI

f8
CHRIN2

JSR
BCC
CLRX
CMP
BEQ
INCX
BRA

....

** .. ** "'_** •• '" ** .... ** ** .. ** *

KEYSCN
CHRIN

GET KEY
IF NOT VALID RETRY

STAHL, X

CONVERT

CHRIN2

TO HEX

CHRIN1
IF CANCEL

TXA

RTS

258

1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214

'* 'II '* 'It ** *** *** ... ** '* ** '* '* '* *** '* '* '* .. ** '* ** '* ... _* ** '* '* '* ... '* ... * .. 11'''' * * *
Conversion table for keypad.

* ** * ** *****_ * ** * ** '*
e6cb 11

STABL

e6ee 21
e6ed 22

e6ee
e6ef
e6dO
e6d1
e6d2

24
31
32

34
41

1215 e6d3 42

1216
1217
1218
1219
1220
1221

e6d4
e605
e6d6
e6d7
e6d8
e6d9

44
48
38
28
18
14

1222 e6da 12
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235

e6db
e6dc
e6dd
e6de
e6df
e6eO

e6e1
e6e2

61
58
68
64
62
54
52
51

11"

FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB

*.*._

$11
$21
$22
$24
$31
$32
$34
$41
$42
$44
$48
$38
$28
$18
$14
$12
$61
$58
$68
$64
$62
$54
$52
$51

* ** '/I' '* '* '* ... * '* ** ... '* '* ... ** ... '* '* '* ** * '* * *

A
B
C
D
E
F
10
11
12
13
14
15

16

CANCEL COMMAND
ENTER COMMAND
STACK POINTER
MEMJR'f
GO
VERIFY TAPE
LOAD TAPE

17

PUNCH TAPE

* ** '* ** *** ** 11' ** '* '* ..... ** ........ '* '* * ... '* '* .. 'It", *** '* ** * ... '* *** .. * '*"''''''' *

Memory location examine/change.

1236
1237
1238
1239 e6e3 cd e7 9a
1240 e6e6 al 10
1241 e6e8 27 57
1242 e6ea c7 02 12
1243 e6ed cd e7 46
1244 e6fO cd e7 d6
1245 e6f3 cd e7 90

'* '* ** ** * *** ** '* ** ..... '* '* '* * *** .. ** 11' * '* .. ** *** '* ** '* ... * '* ... '* '* •• * ** 'It
MEMEX

MEMEX3

1246 e6f6 at 10
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284

e6f8
·e6fa
e6fc
e6fe
e700
e702
e704
e706
e709
e70c

27
at
27
a1
27
a1
22
cd
cd
25

47
11
Ib
13
2f
Of
08
e7 d6
e7 7e
fa

e70e
e710
e712
e714
e717
e719
e71c
e71e
e720
e722
e725
e727
e729
e72b
e72d
e72f
e731
e734
e736
e738
e73a
e73c
e73f
e741
e743

a1
26
b6
cd
25
Oc
3c
26
3c
cd
20
a1
26
b6
ad
25
Oc
3d
26
3a
3a
cd
20
1d
cc

11
15
21
e7
dl
20
23
02
22
e8
c3
13
16
21
28
b9
20
23
02
22
23
e8
a9
20
eO

MEMEXl

CMDMDL

57
25

02

ADRINC

MEMEX5
MEMEX2

Od

ADRDEC

CMDMB2
02
MEMEX4
b4

JSR
CMP
BEQ
STA
JSR
JSR
JSR
CMP
BEQ
CMP
BEQ
CMP
BEQ
CMP
BHI
JSR
JSR
BCS

GETADR
t$10
MEMEX4
I<.DRKI
LOAD
PRTDAT
GETNYB
t$10
MEMEX4
1$11
ADRINC
1$13
ADRDEC
I$OF
CMDMDL
PRTDAT
GETBY2
MEMEXI

CMP
BNE
LOA
JSR
BCS
BRSET
INC
BNE
INC
JSR
BRA
CMP
BNE
LOA
BSR
BCS
BRSET
TST
BNE
DEC
DEC
JSR
BRA
BCLR
JMP

*$11
MEMEX2
I<.DRK2
STORE

BUILD ADDRESS

LOAD DATA

PRINT IT
GET NEW NI BBLE

IF VALID
PRINT IT
SHIFT IN NEXT
IF VALID TRY AGAIN
EN'IER?
NO
RESTORE ACCA
YES STORE IT
STORE VALI D?

MEMEX3

6,STAT,MEMEX4
ADDRL
MEMEX5
ADDRH
PRTADR
MEMEX3
*$13
MEMEX4
I<.DRK2
STORE
MEMEX3
6,STAT,MEMEX4
ADDRL
CMDMB2
ADDRH
ADDRL
PRTADR
MEMEX3
6, STAT
GETCMD

259

YES GOTO
NEXT
PRINT IT
REPEAT
NO

YES THEN
GET PREVIOUS
ADDRESS
PRINT IT
REPEAT
INVALID CHAR

1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1309
1309
1310

Load byte at ADDRH,ADORL into A.

e746
e749
e74b
e74d
e741
e751
e753
e756

cf
ae
bl
oe
bl
bd
ce
81

LOAD
LDSTCM

e757 c! 02 12
e75a ae c7
e75c ad ed

e761
e770
e771
e772

S'lURE

02 13

e7 46
02 13
01

02 12

STRTS

1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1349
1349
1350
1351
1352
1353

w::lRKI
I$C6
w::lRK2
1$81
w::lRK3
w::lRK2
w::lRK!

SEWP
ROUTINE
TO DO
'lWO BYTE

LOAD

e774
e775
e776
e777
e77B
e779
e77a

w::lRK!
I$C7
LOSTCM
V«:>RK4
LOAO

SEWP
ROUTINE
TO DO
'lWO BYTE
S'lURE

~RK4

STRTS
w::lRK1

Hex. to mux. display conversion.

CTABL

06
e3
a7
36
15
07
f7
b7
77
[4
dl

e77b e6
e77c f1

e77d 71

e77e
e780
e782
e784
e786
e788
e78a
1354 e78c
1355 e7Be

STX
LOX
BSR
STA
JSR
CMP
BBQ
SEC
LOX
R.TS

1328 e773 b5

1329
1330
1331
1332
1333
1334
1335

STX
LOX
STX
LOX
STX
JSR
LOX
RTS

Store byte in A at ADDRH,ADDRL.

e75e c7
e761 cd
1311 e764 cl
1312 e767 27
1313 e769 99
1314 e76a ce
1315 e76d 91
1316
1317
1318
1319
1320
1321
1322
1323 e76e d7

1324
1325
1326
1327

02 12
c6
21
81
24
21
02 12

FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FeB
FCB
FCB
FCB
FCB
FCB
FCB
FCB

S07
$06
SE3
SA7
S36
SB5
SF5
S07
$F7
$B7
$77
$F4
$O!
$E6
$F!
$71

0
1

2
3
4
5
6
7

B
9
A
B
C
D
E
F

Build a byte in accumulator.

b7
ad
24
38
38
38
38

21
Oe
Ob
21
21
21
21

GETBY2

ba 21
99

1356 e7ar 81
1357

GETBRT

STA
BSR
BCC
ASL
ASL
ASL
ASL
ORA
SEC
RTS

w::lRK2
GETNYB
GETBRT

w::lRK2
w::lRK2
w::lRK2
w::lRK2
w::lRK2

260

1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1369
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1395
1396
1397
1399
1389
1390
1391
1392
1393
1394
1395
1396
1397
1399
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1419
1419
1420
1421
1422
1423
1424
1425
1426
1427
1429
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443

...... * .. ** ... ** ... *** '** ... ** ......... *.* ... 'It'II''''.'II' *.* 11 • • • _* •• * ........... * ....

Get one character and check for val id
hex, A contains output, carry set if
valid.
.......... * ...... ** ... *. 11' • • '" * ....... * ............... * ..... *.* ......................... * ............ *. 11
e790 cd e6 bb
e793 98
e794 al Of
e796
01
e798 99
e799 81

GETNYB

--

GETRET

JSR
CLC
CMP
BHI
SEC
RTS

CHRIN

GET CHARACTER

'$OF
GETRET

VALID HEX?
NO
YES

... * .... "'* ................ * ......... * * ........... ", ** * ........................ _'II'''' '* ...... ** *
Build address in ADDRH,ADDRL. carry set
if new address.

... * * ......... '* ** ._. *** * ** ••• *.*. * .... ** ** ...... ** * ** .... * .......... **.w ......
e79a cd e6 42

GETADR

e79d cd e8 02

BLDA2

e7aO ad ee
e7a2 25 Oa
e7a4 al 11
e7a6 27 2d

BLOADR

e7a8 al 10
e7aa
e7ac
e7ae
e7bO
e7b2
e7b5
e7b7
e7b9
e7ba
e7bb
e7bc
e7bd
e7bf
e7cQ
e7c2
e7c4
e7c5
·e7c7
e7ca
e7cc
e7ce
e7dO
e7d2
e7d4
e7d5

27
20
3f
h7
cd
ad
24
49
48
49
48
ae
49
39
39
5a
26
cd
20
al
27
a1
26
99
81

29
ec
22
23
e8 02
d9
13

GE'l'ADl

GETALP

04
GETASF
23
22
f9
e8 02
e9
10
05

GETARG

11
el
GETRTS

JSR
JSR
BSR
BCS
CMP
BEQ
CMP
BEQ
BRA
CLR
STA
JSR
BSR
BCC
ASLA
ASLA
ASLA
ASLA
LDX
ASLA
ROL
ROL
DECX
BNE
JSR
BRA
CMP
BEQ
CMP
BNE
SEC
RTS

BLANK DISPLAY

CLRTAB
PRTADR

GET CHARACTER

GETNYB
GETADI
1$11
GETRTS
1$10

VALID HEX?
EN'IER ?

NO, CANCEL ?
NO, TRY AGAIN

GETRTS

GETADR
ADDRH
ADORL
PRTADR
GETNYB
GETARG

INIT HIGH ADDRESS
PUT CHAR AWAY
PRINT NEW ADDRESS
GET ANOTHER CHAR
VALID?
YES
SHIFT IT IN

*4
ADDRL
ADDRH
GETASF
PRTADR
GETALP
'$10
GETRTS
1$11
GETALP

PRINT NEW ADDR
GET ANOTHER CHAR
NOT VALID HEX, CANCEL?
ENTER?
NO TRY AGAIN
YES SET FLAG

........................................................................................................
Print one byte into· pair of display
digits, A contains byte, X points to
first diget.

............................................... ** .... _........... * ........ * •••• *. *
e7d6
e7d8
e7db
e7de
e7df
e7eO
e7e1
e7e2
e7e3
e7e6
e7e9
e7ec
e7ef
e7fl
e7f2

ae
cf·
c7
44
44
44
44
97
d6
ce
d7
c6
a4
97
d6

e7f5
e7f8
e7fb
e7fe
e901

ce
d7
cd
c681

04
02 12
02 13

e7
02
02
02
Of

6e
12
Oc
13

e7 6e
02
02
e6
02

12
Od
4c
13

PRTDAT
PRTBYT

LOX
STX
STA
LSRA
LSRA
LSRA
LSRA
TAX
LOA
LOX
STA
LOA
AND
TAX
LOA

14
WJRKI
WJRK4

LOX
STA
JSR
LOA
RTS

hORKl
DTABL+1.X
01 STAB
w:lRK4

PRINT IN LAST 'TWO DIGITS

CTABL.X
WJRK1
DTABL,X
WJRK4
'$OF
CTABL,X

261

1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454

.... '" 1<""""" 11 1r" '*
'/<

* .... * ** 11 if"' .. ** '" ** * ** .. ** .. ** .. '* * '* .... *
I

.... 1<"''''''''''' '" '" "' .. '" * '" ** '" '" "' ..... * * 11''
e802 b7 25
e804 bf 24
e806 b6 22

PRTAOR

e80S Sf

1456 eaOb b6 23
1457 e80d ae 02
1458 eSOf ad c7
1459 e81l b6 25
1460 e813 be 24
1461 e8lS 81
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473 e816 a6 8)
1474 e818 b7 24
1475 e81a a6 f4
1476 e81c c7 02
1477 e8H a6 77
1478 e8n c7 02
1479 e824 cd e6
'!..480 e827 a6 04
1481 e829 b7 22
1482 e82b a6 00
1483 e82d b7 23
1484 e82 f cd e7
1485 e832 25 04
i486 e834 a1 11
1487 e8::'6 26 61
1488 e838 h6 22
1489 e23a h7 27

BSR
LOA
LOX
BSR
LOA

LOX

11 'II '"

* "' ..... * ... '" *

WORKS
WORIG

ADDRH
PRTBYT

ADDRL
i2
PRTBYT
I-.DRK5
W'JRK3

RTS

1r*****1r1r*******

**************** ******************** *

Trans fer code from EPROM to RAM, default
destination address: ~ $0400-$lFFF , from
EPROM at $4400 - $5FFF .
(TEMP, TEMP+! .> ADDRH,ADDRL) .
*********"-'1<'1<'1<***..-**************1<***1<1<**.,,*****:0-******

XFER

10
11
4c

9d

SKf'Cl

~

4 90 e83c b6 23
~ 4 91 e83e b7 28
1412 e840 a6 fl
: 4~3 02842 c7 02 H!
e8~5

STA
STX
LOA

*._ . . ** '" * * * ** "' ..

CLRX

1455 e809 ad cd

:~'j4

I< "' ........ 1r ..

Print address ADDRH ADDRl..

i$81
WORK3

STA

a6

: 4~S e847 c7
11
14'16 e8~a cd e6 4c
: 4,;'7 e84d a6 1f
:4S<2 e84 f b7 22
14~9 e851 a6 ff
1500 '2853 b7 22
: 501 e8SS cd 07 Sd
1502 eaS8 25 04
1503 e8Sa a1 11
1504 e8Se 26 3b
1505 eSSe b6 22
150£ e8eO be 27
1507 e862 b7 27
1508 e864 bf 22
1509 e866 b6 23
1510 e868 be 28
1511 e86a bf 23
1512 e86c b7 28
1513
1514

LDA
STA
LOA
STA
LOA
STA
JSR
LOA
STA
LOA
STA
JSR
BCS
CMP
BNE
LOA
STh
LOA

SKPC2

i$F4

RTS

'BA'

DTABL+4

i$77
DTABL+5

DISTAB
i$04

DEFAULT 'TO $0400

ADDRH

i$OO
ADDRL
BLDA2
SKPCl

i$11
MB

GET SOURCE ADDR.
VALID?
NO, ENTER ?
I F NOT THEN ABORT

ADDRH

YES

TEMP

NO SAVE IT

ADDRL
TEMP+1

LOA

*$F1

STA

DTABL+4

LOA

*$77

STA
JSR

DTABL ... :'
DISTAB

LOA
STA
LOA

ADDRH

STA

ADDRL

JSR
BCS
eMP
BNE
LOA
LDX
STA
STX
LOA
LOX
STX
STA

BLOAl

'$lF

PRINT '£A'

DEFAULT 'TO $lFFF

i$FF

SKPC2

.$11
MB
ADORH
TEMP
TEMP

GET DESTINATION ADDR
VALID ?
NO, ENTER ?
IF NOT THEN ABORT
SWAP ADDRESSES

ADDRH
ADORL

TEMP ... 1
ADDRL
TEMP ... 1

262

1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542

Transfer code from EPROM to RAM.

e86e
e870
e872
e874
e877
e878
e870
e87c
eB7e
e87f
e882
eB84
eB87
e889
e88b
e88d
e88f
e891
e893
e895
e897

b6
ob
b7
cd
97
b6
00
b7
9f
cd
24
cc
3c
26
3c
b6
b1
26
b6
b1
26

22
40
22
e7 46
22
40
22

LDA
ADD
STA
JSR
TAX
LOA
SUB
STA

e7 57
03
e4 76
23
02
22
22
27
db
23
28
d5

JSR
BeC
JMP
INC
BNE
INC
LDA
CMP
BNE
LOA
CMP
BNE

STORE
RBOK
ERR2
ADDRL
XSKP
ADDRH
ADDRH
TEMP
XLOOP
AODRL
TEMP+l
XLOOP

JMP

GETCMD

XLOOP

ADDRH
'$40
ADDRH
LOAD
ADDRH
'$40
ADDRH

TXA

1543 e899 cc eO b4

ROOK

XSKP

XAB

1544
1545
1546
1547

Vectors etc.

1548

1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573

SIRQV
TIRQAV
TIRQBV
IRQV

e89c 80
e89d cd e6 57

PWRDWN
STP

RTI
JSR
STOP
BRA

STP

e807 20 fd

JSR
WAIT
BRA

WIT

ftf4

ORG

$FFF4

FOB
FOB
FOB
FOB
FOB
FOB

RESET
TIRQB
TIRQA
IRQ
SWI
RESET

eBaD Be

e801 20 fd
e8a3 cd e6 57
e8a6 8f

fff4
fff6
fff8
ffto

eO
02
02
02

00
06
03
00

fffe eO Se

ftte eO 00

WDWN
WIT

CLRDIS

CLRDiS

SERIAL
TIMER B

TIMER A
EXTERNAL INTERRUPT
SWI
RESET

END

263

264

AN·890

H IInformallon
Historical

LOW VOLTAGE INHIBIT (LVI)
CAPABILITY OF THE M680S HMOS
MICROCOMPUTER (MCU) FAMILY
Prepared by
Ed Edwards
Microprocessor Applications Engineering
Austin, Texas

INTRODUCTION

The low voltage inhibit (L VI) option, as used with many of
the M6805 HMOS Family Microcomputer (MCU) devices
(EPROM MCUs excluded), provides a means for the MCU
to sense a drop in supply voltage (V CC) and then shut itself
down in a well-defined manner, The LVI option may be used
in applications which require the correct-output during normal operation and no-output during loss of power. The LVI
option is also useful in fail-safe and/or fall-back operating
modes for minimum systems operation.
An example of this no-output control scheme is in heightpositioning applications, With correct-output control signals
from the MCU, the position of "cherry-picker" platforms
could be controlled and maintained. With inadvertant lo~s of
power due to power supply/battery deterioration and/or
cable disconnects, the no-output signal would permit locking
methods to be initiated within microseconds, This would
allow the "cherry-picker" to maintain its "last position"
(thUS preventing disasterous falls for personnel or on-board
equipment) or to start a predetermined (hydraulic selflocking or hydraulic bleed-off valves) controlled descent,
This LVI capability of transition from correct-output to nooutput (Le., high-Z, 3-state) without an intermediate uncontrolled region is defined in the On-Chip Operation
paragraph.
Another example of this correct-output usefulness is in
starter-controls of multi-horsepower electric motors. During
normal power transitions, the controller signals will start up
the motor at prescribed voltage and current versus time relationships, and maintain specified shaft RPM and shaft output power afterwards. At low power conditions (Le"
brownout), the electric current required to maintain this
same motor-rpm and shaft output power increases proportional to the voltage decrease; e.g., a 20.,. drop in powerline
voltage causes an equivalent 20.,. increase in motor current,
this 20.,. increase in motor current produces a 44.,. increase
in internal 12R loss, The internal 12R loss may cause the
motor to overheat or even burn out. The M6805 HMOS

MCU can detect this "brownout" (low voltage) condition
and immediately place the MCU output control lines (normally used to turn on the motor controller) in the highimpedance state. Bipolar driver devices with built-in pulldown resistors are usually used in these applications to turn
themselves off when the control input is open-circuited.
Restart can be then prohibited until normal power conditions
return and the original current versus time relationships are
reestablished, within the controller.
The LVI option is provided at the time of manufacture by
on-chip circuitry, as a mask option, contained in part of the
users ROM pattern. When the LVI option is provided, no
additional external parts are required for normal operation.
The LVI option will usually provide for an overall product
cost reduction by eliminating the external components required to implement this feature off-chip.
ON-CHIP RESET/LVI OPERATION

A simplified equivalent of the internal reset and LVI circuitry is shown in Figure I, The circuit consists of three basic
sections: (I) internal reset generator, (2) an internal Schmitt
trigger which is externally activated, plus bias circuits, clamping diodes and current limiting, and (3) a low voltage detector with gating logic.
LVI DISABLED

Without the LVI option (Le" LVI disabled), the internal
reset generator is only actuated by the external RESET pin
via the Schmitt trigger. In this case during power-on reset
(POR) , external capacitor CR (0, I to 1.0 microfarad) is
charged through an on-chip resistor (Rc) and the current
source from Vec. When the RESET pin voltage rises to the
Schmitt trigger positive threshold (VIRES +), the on-chip
reset generator allows the CPU to begin executing from
ROM. The RC delay (tRHO allows the on-chip oscillator to
stabilize prior to start of program execution. During normal
power turn-off, the on-chip reset generator is actuated by the

265

Vee

-------

--\----

Pin
+5V

RC

Internal

RESET

-,
Reset GfJnerator

*

k~,

:
.-'

Os:.::: Substrate Diode
D 1 ~ V CC ClAmping Diad"
RC~IN+12 k +25%

Mask Option
(Open CirCUit
for LVI Option 1

RD ~ (Polyl 300 :': 50% (l
RON = 100 ± 50% (l

FIGURE 1 - M6805 HMOS Family LVI Simplified Schematic Diagram

Schmitt trigger after the decreasing voltage on the RESET
pin falls to the negative threshold voltage (VIRES-). The individual M6805 HMOS Family data sheet and Figure 2 (of
this application note) contain information concerning the
reset and LVI timing waveforms, and Vee voltage spectrum.

reaching the Schmitt trigger VIRES _ threshold. The only requirement is that VLVI remains at its threshold for one tcyc
(minimum). In typical applications, the Vee bus filter
capacitor will eliminate negative-going voltage glitches of less
than one tcyc. Once the VLVI threshold is reached for one
tcyc , the low voltage detect circuit outputs a logic I which is
gated to the on-chip reset generator, resetting the epu
within the next tcyc period.
Simultaneous to the activation of the on-chip reset
generator, the low voltage detecto,r turns on the internal Ron
device. With the Ron device turned on, the external reset
capacitor discharges through internal current limiter RD and
continues until the RESET pin voltage falls below the minimum reset voltage, holding the epu in reset. This condition
remains until recovery of Vee, at which time normal poweron reset resumes.

LVI ENABLED
With the LVI mask option (i.e., LVI enabled), the poweron sequence is exactly the same as described above. However, in the power-down condition (resulting from normal
power turn off, brownout, or voltage "dip"), the on-chip
reset generator is triggered by the low voltage detector before
power falls below the reset level. In this case (as shown in
Figure I), the second input to the reset generator OR gate
becomes functional and the low voltage detect circuit causes
a reset at a voltage point (VL vO prior to the RESET pin

266

+5V
vee

o
I

o

VIRES-

PLIIIIL~_\..----J..------J'.r--

Vee
Vlnternal Reset

o

*

*

LVI discharge effect

lal Reset/LVI Timing Diagram

Typical
VLVI
Threshold
Range
Guard --.l

.. 5 25± 05 V
1
I~--s-p--'e::'ci-fl-ed--l·~ -

-

-

-

Operating
Range

-

--.l
~

Vee
IMaxl

LGuard
~ Sand

Band~

-I-I-I~~~--~--~+-+---+-~~--~~~~--~
2.5 2.75 3.0

40

6.0

50

7.0

so

Vee IVoltsl
Ibl Vee Voltage Spectrum Diagram

FIGURE 2 -

M6805 HMOS .Family Reset/LVI Timing and
Vee Voltage Spectrum Diagrams

normal value (S.2S Vdc) to the point where the TEST P
square wave disappears (i.e., PBO switches to high impedance). This is the VLVI value for this particular device.
When VL VI is attained by reducing VCC' the three-state
leakage current (ITSJ) can then be measured to check that all
110 port pins are in the high-impedance state.
Increase VCC in smal1 increments (1(}'IOO millivolt steps)
and reinitiate the test pattern TEST P by keying the Execute
address $040 into the RS-232-C terminal. This determines the
VLVR value for the device being tested. (Note that the TEST
P program will be retained in the on-chip RAM at the VL VI
voltage level.)

LVI TESTING
Figure 3 shows an LVI test circuit connection for the
MC6805P4L1 (or PI). Similar connections for other M680S
HMOS Family MCUs could be made to corresponding pins
for LVI testing. This circuit, together with the software in
Figure 4, is used to determine the VL VI and VL VR for the
MCU under test.
Figure 4 is the test pattern (TEST P) software routine to be
entered into RAM in order to generate a continuous output
square wave on the PBO pin. By utilizing the on-chip monitor
capability of the MC6805P4L1 demonstration program, the
TEST P program can be loaded into on-chip RAM via an
RS-232-C terminal. This connection is shown schematical1y
in Figure 3. In typical lab applications, the 15 k pul1up
resistor is adequate to provide the required operating frequency. Alternatively, an adjustable resistor may be used to
set the frequency at 3.S8 MHz.
In order to activate the LVI state, the supply voltage
(V CC) must drop below VLVI and remain there for one tcyc
(internal clock period) plus 2S0 nanoseconds. The M680S
HMOS Family VCC voltage spectrum is shown in Figure 2b.
To determine the VLVI trip point, reduce the VCC from the

TYPICAL APPLICATION
A circuit that can be used to directly control a Darlington
bipolar solenoid driver is shown in Figure S. The
MC680SP4L1 was chosen for the circuit because of its larger
RAM area (112 bytes versus 64 bytes on other masked ROM
devices). As shown in this figure, the port B (PBO) high current drive capability is used for this circuit. When the LVI
capability is utilized, the solenoid immediately turns off with
loss of power or brownout condition.

267

5V

Baud Rate Switch

10k

28

mIT

S2

,,=1

9

PCl

See Table

Reset
Switch
S3

0

Rate

300

1

1200

1

0
1

4800
9600

33k

MC6805P4Ll

To Terminal

10

PC2
51

PCO

o
o

1 - switch open
0- switch closed

+5V

+5V

PCI

6.8k

6
VSB

2N2222

2

10k
TIMER
IN914
15 k

5

5

To/From
RS·232·C

6

Terminal

XTAL
8

*

+ 12 V

4

EX TAL

11

PC3

AOM·3
lor Equiv.1

20
3

3

-12V

Vss

OB·25 Connector
12

Test P
Output

* If crystal option is used, delete 15 k resistor and connect crystal per data sheet.
FIGURE 3 -

040
040
042

044
046
048

A6
B7

10
11
Be

FF
05
01
01

MC6805P4 LVI Test Circuit Schematic Diagram

TEST P

44

ORG
LOA
STA
BSET
BClR
JMP

$040
#$FF
$005
0, PORT B
0, PORT B
TEST P

Resulting Test Pattern at PBO

FIGURE 4 -

Test Pattern Routine (TEST PI

268

Set Port B As Output
Set PBO
Clear PBO
Do It Again

5V

Baud Rate Switch
PCI
PCO
Rate

See Table

28

RmT

9

PCl

Reset
Switch
S3

o
o

0
1

1

0

4800

1

9600

300
1200

1 - switch open

0- switch closed

+5V
3.3 k

MC6805P4Ll
PC2

+5 V

-

To Terminal

10

51
6
....-"I/\,'V---I VSB

10k

J~t o:".u
1
"L-o:

3.58 MHz

0

TIMER

5
4

EXTAL

S4

XT AL

TermInal
ADM-3
lor Equlv.1

8
+ 12V

~I0-__5--1

To/From
RS-232-C

6

11

PC3

(RC)

20

3

3

-12 V

7
15 k
+5V

1

10k

VSS
19

PB7
PBO

DB-25 Connector

+ 12V

[@

12

IN4001

3

r

I

I

L __

-.J

MJ3001

2

FIGURE 5 - MC6805P4 With Darlington Connected Solenoid Driver

269

Allied Control
#306X-32
112 Vdc@ 11 WI

four baud rates which allows the user to enter and execute
small software programs directly from on-chip RAM, as is
done in this application note .

S"ftware to control the solenoid (via port B, PBO) is shown
in Figure 6. This software routine may be entered into on.:hi!, RAM via the RS-232-C terminal with the MC680SP4L1
in the tn,'nitor mode. The on-time of the solenoid (Allied
Controls #306X-32) is set by the value entered (by the RS232-C terminal) in RAM location $04F. The on/off times for
this particular solenoid and software timing loops are shown
below.

PORT I/O CHARACTERISTICS WITH LVI OPTION
The device operates successfully down to the VLVI threshold. During a lowering of VCC voltage, due to a brownout
condition of electrical power or other reason, the LVI option
provides the user with reduced drive capability but a stable
port configuration. A discussion of these characteristics is
provided below.
The LVI threshold r81:lge may be between + 2.7 V and
+ 4.7 Vdc. The exact level could be determined as described
above for the LVI Testing. Between the range of + 4.7 Vdc
and the actual VLVI voltage, each I/O port configuration remains as programmed. However, the drive capabilities (as a
percentage of the specified port dc electrical characteristics)
between the 4.7 Vdc and the actual VLVI voltage are as
follows:
(I) ILOAD Sink - 100070 of specified current sinking capability for ports A and C, and 50070 of specified sinking
capability for port B.
(2) ILOAD Source - 0% of specified drive current. That
is, do not depend upon the M680S HMOS Family
MCV to source current below the lower VCC limit of
+4.75 Vdc.

$04F=04; 9.6 ms/9.6 ms
=OF; 36 ms/36 ms
=4F; 188 ms/188 ms
= FF; 620 ms/620 ms
The minimum on/ off time of the solenoid shown in Figure
5 is I3 milliseconds. The 9.6 millisecond value (RAM
S04F = 04 in Figure 6) only caused the solenoid to chatter;
therefore, a higher hexadecimal value may be required in
location S04F.
MONITOR SOFfW ARE
A listing of the monitor (and self-check) program in the
MC680SP4L1 (PI) is attached to this application note. This
monitor program permits selection (via switch positions) of

00001
00002
oooo3A
00004A
oooo5A
00006A
oooo7A
OOOOBA
00009A
ooolOA
ooo11A
ooo12A
ooo13A
ooo14A
ooo15A
ooo16A
ooo17A
00018

.

0005

0001
0040
0040
0042
0044
0046

004B
OO4A
OO4C
OO4E
0050
0052
0053
0055
0056
0056

AG
B7

10
AD
11
AD
BC
AE
A6
4A
26
5A
26
81

A
A

FF
05
01
06
01
02
40
04
FF

A
A
A
OO4E
A
OO4E
A
A
A

FD

0052

F8

0050

DDRB
PORT B
TESTOl

DELAY
DELAY1
DELAY2

EOU
EOU
ORG
LDA
STA
BSET
BSR
BCLR
BSR
JMP
LDX
LDA
DECA
BNE
DEX
BNE
RTS
END

FIGURE 6 - Software Listing for Controlling Solenoid via PBO

270

$05
$01
$040
#$FF
DDRB
O.PORT B
DELAY
O.PORT B
DELAY
TESTOl
#$04
#$FF
DELAY2
DELAYl

LOAD FROM RS·232

PAGE 001

MONIT

.P4:1

.
*
*
*
*

*
*

*
*
*
*
*
*

*
*
*
*
*
*
*

*

MC 6 8 0 5 P 4

ROM

PAT T ERN

THIS ROM CONTAINS A CUSTOMER PROGRAM, THE STANDBY MONITOR
AND A NEW VERSION OF THE SELFCHECK.
THE CUSTOMER ROM
OCCUPIES $80-$FF AND $3CO-$5Da. THIS LEAVES $509-$783
FOR THE MONITOR. MOST OF THE MONITOR COMMANDS HAVE BEEN
DELETED TO MAKE IT FIT WITHIN THIS AREA. THE SELFCHECK
IS DIFFERENT FROM THE P2 PATTERN SINCE THERE IS MORE RAM
ON THIS PART.
THE OLD P2 SELFCHECK WAS VERY TIGHTLY
CODED AND DEPENDED ON THERE BEING EXACTLY 64 BYTES OF
RAM.
THE P4 HAS 112 BYTES OF RAM AND REQUIRES A NEW
TEST. THIS MESSES THINGS UP SOMEWHAT SINCE THE SAME GOOD
TEST CANNOT BE APPLIED TO THE P4.
THE MONITOR IS SELECTED WHEN BIT 7 OF PORT B IS HIGH
DURING RESET.
OTHERWISE,
THE CUSTOMER PROGRAM WILL BE
SELECTED. THE MONITOR MODE IS AN ENHANCED VERSION OF THE
ORIGINAL P2 VERSION.
SERIAL I/O IS HANDLED ON PORT C. BIT 3 IS THE SERIAL
OUTPUT LINE AND BIT 2 IS THE SERIAL INPUT LINE. THE
LOWER TWO BITS OF PORT C SELECT THE BAUD RATE FOR ALL
SERIAL I/O.
Cl CO
BIT RATE/SEC

..*
.
.*

0
0
1
1

------------

0
1
0
1

300
1200
4800
9600

ED RUPP MAY 11,1981

*

*-----------------------------------------------------------------0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

0000
0000
0000
0000
0000

00
00
00
00
00
00
00
00
03
08
05
05

00
00
00
00
00

00
01
02
04
08
09
10
80
CO
00
09
B3

00
OA
20
07
00

*
*

I/O REGISTER ADDRESSES

PORTA
PORTB
PORTC
DDR
TIMER
TCR
RAM
ZROM
ROM
MEMSIZ
MONST
CENTRY

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

*
..

CHARACTER CONSTANTS

CR
LF
BL
BEEP
EOS

EQU
EQU
EQU
EQU
EQU

$000
$001
$002
4
$008
$009
$010
$080
$3CO
$800
$509
$5B3

$00
$OA
$20
$07
$00

.

*

271

I/O PORT 0
I/O PORT 1
I/O PORT 2
DATA DIRECTION REGISTER OFFSET
a-BIT TIMER REGISTER
TIMER CONTROL REGISTER
START OF ON-CHIP RAM AREA
START OF PAGE ZERO ROM
START OF MAIN ROM AREA
MEMORY ADDRESS SPACE SIZE
START OF MONITOR
ENTRY POINT TO CUSTOMER PROGRAM

CARRIAGE RETURN
LINE FEED
BLANK
CONTROL-G (BELL)
END OF STRING

PAGE 002

MONIT

.P4:1

*

ROM

M 0 NIT 0 R

FOR THE

6 8 0 5 P 4

*
*

*

THE MONITOR HAS THE FOLLOWING COMMANDS:

*

M --

MEMORY EXAMINE/CHANGE.
TYPE M AAA TO BEGIN,
THEN TYPE:
TO RE-EXAMINE CURRENT
~
TO EXAMINE PREVIOUS
CR -- TO EXAMINE NEXT
DO -- NEW DATA
ANYTHING ELSE EXITS MEMORY COMMAND.

E --

EXECUTE FROM ADORERS. FORMAT IS
E AAA. AAA IS ANY VALID MEMORY ADDRESS.

'*

*

*
*

*j,

0000
0000
0000
0000

*
*
*
*
*
*

00 2E
00 00
DOSE
00 2E

PROMPT
FWD
BACK
SAME

*

*
*

0000 00 7F
0000 00 7A

0000

EQU
EQU
EQU
EQU

PROMPT CHARACTER
GO TO NEXT BYTE
GO TO PREVIOUS BYTE
RE-EXAMINE SAME BYTE

CR
'~

OTHER

INITSP
STACK

EQU
EQU

*
*

RAM VARIABLES

GET
ATEMP
XTEMP
CHAR
COUNT

0010
0014
0015
0016
0017

SPECIAL EQUATES

$7F
INITIAL STACK POINTER VALUE
INITSP-S TOP OF STACK

ORG

RAM

ON-CHIP RAM (64 BYTES)

RMB
RMB
RMB
RMB
RMB

4
1
1
1
1

NO-MANS LAND, SEE PICK AND DROP SUBROUTINES
ACCA TEMP FOR GETC,PUTC
IX TEMP FOR GETC,PUTC
CURRENT INPUT/OUTPUT CHARACTER
NUMBER OF BITS LEFT TO GET/SEND

ORG

MONST

*
0018

0509
OsDC
OSDE
OSEI
OSE4
OSE6
OSE9
OSEB
OSED
OsEF
OsFl
0.'5F3
OsF6

CD
A6
CD
CD
A4
CD
Al
27
Al
27
A6
CD
20

06
2E
07
06
7F
06
45
DB
40
17
3F
07
El

B1
28
F6
BE

28

*
*
*

MAIN

MAIN --- PRINT PROMPT AND DECODE COMMANDS
JSR
LOA
JSR
JSR
AND
JSR
CMP
BEQ
CMP
BEQ
LOA
JSR
BRA

CRLF
GO TO NEXT LINE
#PROMPT
PUTC
PRINT THE PROMPT
GETC
GET THE COMMAND CHARACTER
#%1111111 MASK PARITY
PUTS
PRINT SPACE (WON'T DESTROY A)
# 'E
EXECUTE
EXEC
t'M
MEMORY
MEMORY
#'?
NONE OF THE ABOVE
PUTC
~~IN
LOOP AROUND

272

PAGE 003

MONIT

05F8
05FB
05FD
05FE
0601
0603
0605
0607

CD
25
97
CD
25
B7
BF
80

06 08
DC

0608
060B
0600
060F
0612
0614
0616
0619
061B
061E
0620
0623
0626
0628
062B
062E
0631
0633
0635
0637
0639
063B
0630
063F
0641
0643
0645
0647
0649
064B
0640
064F
0651
0653
0655
0657
0659

CD
25
B7
CD
25
B7
CD
B6
CD
B6
CD
CD
AD
CD
CD
CD
25

06
CC
11
06
C5
12
06
11
06
12
06
06
33
06
06
06
06
2C
3A
DO
2E
09
00
F4
5E
94
12
12
FF
C9
11

.P4:1

*
*
*

EXEC

EXEC --- EXECUTE FROM GIVEN ADDRESS
GETNYB
MAIN

GET HIGH NYBBLE
BAD DIGIT
SAVE FOR A SECOND
GETBYT NOW THE LOW BYTE
MAIN
BAD ADDRESS
STACK+5 PROGRAM COUNTER LOW
STACK+4 PROGRAM COUNTER HIGH

JSR
BCS
TAX

JSR
BCS
STA
STX
RTI

06 C7
06
7F
7E

MEMORY --- MEMORY EXAMINE/CHANGE

AD
AD
20
Al
27
Al
27
Al
26
3A
B6
Al
26
3A
B6
Al
26
A6
B7
20

08

*

MEMORY

C7
Bl

MEM2

AO
93
BE
93
BE
C7
MEM4
MEM3

11

FF
Cl
07
11
BB

*
*

*

*

*
*

JSR
BCS
STA
JSR
BCS
STA
JSR
LOA
JSR
LOA
JSR
JSR
BSR
JSR
JSR
JSR
BCS
BSR
BSR
BRA
CMP
BEQ
CMP
BEQ
CMP
BNE
DEC
LOA
CMP
BNE
DEC
LOA
CMP
BNE
LOA
STA
BRA

GETNYB
MAIN
GET+l
GETBYT
MAIN
GET+2
CRLF
GET+l
PUTNYB
GET+2
PUTBYT
PUTS
PICK
PUTBYT
PUTS
GETBYT
MEM3
DROP
BUMP
MEM2
# SAME
MEM2
#FWD
MEM4
#BACK
MAIN
GET+2
GET+2
#$FF
MEM2
GET+l
GET+l
#$FF
MEM2
#$7
GET+l
MEM2

BUILD ADDRESS
BAD HEX CHARACTER
BAD HEX CHARACTER
ADDRESS IS NOW IN GET+l&2
BEGIN NEW LINE
PRINT CURRENT LOCATION

A BLJI.NK, THEN
GET THAT BYTE
AND PRINT IT
ANOTHER BLANK,
TRY TO GET A BYTE
MIGHT BE A SPECIAL CHARACTER
OTHERWISE, PUT IT AND CONTINUE
GO TO NEXT ADDRESS
AND REPEAT
RE-EXAMINE SAME?
YES, RETURN WITHOUT BUMPING
GO TO NEXT?
YES, BUMP THEN LOOP
GO BACK ONE BYTE?
NO, EXIT MEMORY COMMAND
DECREMENT LOW BYTE
CHECK FOR UNDERFLOW
NO UNDERFLOW
SAME FOR HIGH NYBBLE
TO WRAP AROUND
HIGHEST ADDRESS IS $7FF

UTILITIES
PICK --- GET BYTE FROM ANYWHERE IN MEMORY
THIS IS A HORRIBLE ROUTINE (NOT MERELY
SELF-MODIFYING, BUT SELF-CREATING)

273

PAGE 004

MONIT

.P4:1

*

*

*
065B BF IS
065D AE D6
065F 20 04

*

PICK

*
*
*
*
*
*
0661 BF IS
0663 AE D7

*
*
*

DROP

GET+1&2 POINT TO ADDRESS TO READ,
BYTE IS RETURNED IN A
X IS UNCHANGED AT EXIT
STX
LDX
BRA

XTEMP
#$D6
COMMON

SAVE X
D6=LDA 2-BYTE INDEXED

DROP --- PUT BYTE TO ANY MEMORY LOCATION.
HAS THE SAME UNDESIRABLE PROPERTIES
AS PICK
A HAS BYTE TO STORE, AND GET+l&2 POINTS
TO LOCATION TO STORE
A AND X UNCHANGED AT EXIT
STX
LDX

XTEMP
#$D7

SAVE X
D7=STA 2-BYTE INDEXED

STX
LDX
STX
CLRX
JSR
LDX
RTS

GET
#$81
GET+3

PUT OPCODE IN PLACE
81=RTS
NOW THE RETURN
WE WANT ZERO OFFSET
EXECUTE THIS MESS
RESTORE X
AND EXIT

*
0665
0667
0669
066B
066C
066E
0670

BF
AE
BF
SF
BD
BE
81

10
81
13

*

COMMON

10
IS

*
•

*

*

0671
0673
0675
0677

3C 12
26 02
3C 11
81

*

BUMP
BUMP2

GET
XTEMP

BUMP --- ADD ONE TO CURRENT MEMORY POINTER
A AND X UNCHANGED
INC
BNE
INC
RTS

GET+2
BUMP2
GET+l

INCREMENT LOW BYTE
NON-ZERO MEANS NO CARRY
INCREMENT HIGH NYBBLE

*

*

0678
067A
067C
067E

AD
A4
AD
AD

El
07
22
Fl

*
*

OUT3HS

*
0680
0682
0684
0685
0686
0687
06BB
06BA
06BC

AD
B7
44
44
44
44
AD
B6
AD

D9
10

16
10
12

OUT3HS
BSR
AND
BSR
BSR

*
*

OUT2HS

OUT2HS

BSR
STA
LSRA
LSRA
LSRA
LSRA
BSR
LDA
BSR

*

PRINT WORD POINTED TO AS AN ADDRESS, BUMP POINTER
X IS UNCHANGED AT EXIT
PICK
#%111
PUTNYB
BUMP

GET HIGH NYBBLE
MASK UNUSED BITS
AND PRINT IT
GO TO NEXT ADDRESS

PRINT BYTE POINTED TO, THEN A SPACE. BUMP POINTER
X IS UNCHANGED AT EXIT
PICK
GET

GET THE BYTE
SAVE A

SHIFT HIGH TO LOW
PUTNYB
GET
PUTNYB

274

PAGE 005

MONIT

.P4:1

068E AD El
0690 AD 2C
0692 81

0693
0695
0696
0697
0698
0699
069B
069D
069F

B7
44
44
44
44
AD
B6
AD
81

10

BSR
BSR
RTS

B7
A4
AB
Al
23
AB
AD
B6
81

PUTBYT --- PRINT A IN HEX
A AND X UNCHANGED

PUTBYT

STA
LSRA
LSRA
LSRA
LSRA
BSR
LDA
BSR
RTS

*
*

05
10
01

13
OF
30
39
02
07
7A
13

*

PUTNYB

PUTNY2

*
*
*

06Bl
06B3
06B5
06B7
06B9
06BB
06BD

B7
A6
AD
A6
AD
B6
81

10
OD
71
OA
6D
10

*

CRLF

*

06BE
06CO
06C2
06C4
06C6

B7
A6
AD
B6
81

10
20
64
10

GO TO NEXT
FINISH UP WITH A BLANK

*

*
*
*
06AO
06A2
06A4
06A6
06A8
06AA
06AC
06AE
06BO

BUMP
PUTS

*
*
*

PUTS

*
*
*
*

*
*
*

GET

PUTNYB
GET
PUTNYB

SAVE A

SHIFT HIGH NYBBLE DOWN
PRINT IT
PRINT LOW NYBBLE

PUTNYB --- PRINT LOWER NYBBLE OF A IN HEX
A AND X UNCHANGED, HIGH NYBBLE
OF A IS IGNORED.
STA
AND
ADD
CMP
BLS
ADD
BSR
LDA
RTS
CRLF
STA
LDA
BSR
LDA
BSR
LDA
RTS

SAVE A IN YET ANOTHER TEMP
GET+3
MASK OFF HIGH NYBBLE
t$F
t'O
ADD ASCII ZERO
t'9
CHECK FOR A-F
PUTNY2
t'A-'9-1 ADJUSTMENT FOR HEX A-F
PUTC
GET+3
RESTORE A
PRINT CARRIAGE RETURN, LINE FEED
A AND X UNCHANGED
GET
tCR
PUTC
tLF
PUTC

SAVE

GET

RESTORE

PUTS --- PRINT A BLANK (SPACE)
A AND X UNCHANGED
STA
LDA
BSR
LDA
RTS
GETBYT

GET
tBL
PUTC
GET

SAVE
RESTORE

GET A HEX BYTE FROM TERMINAL

A GETS THE BYTE TYPED IF IT WAS A VALID HEX NUMBER,
OTHERWISE A GETS THE LAST CHARACTER TYPED.
THE C-BIT IS
SET ON NON-HEX CHARACTERS;
CLEARED
OTHERWISE.
X
UNCHANGED IN ANY CASE.

*

275

PAGE 006
06C7
06C9
06CB
06CC
06CD
06CE
06CF
06D1
06D3
06D5
06D7

06D8
06DA
06DC
06DE
06EO
06E2
06E4
06E6
06E8
06EA
06EC
06EE
06FO
06F1
06F2
06F4
06F5

AD
25
48
48
48
48
B7
AD
25
BB
81

AD
A4
B7
AD
2B
Al
23
AO
Al
22
Al
23
98
81
B6
99
81

MONIT
OF
OC

.P4:1
GETBYT

10

as

02
10
NOBYT

1C
7F
13
30
10
09
OA
07
OF
06
09
02

GETNYB
NOBYT

BUILD BYTE FROM 2 NYBBLES
BAD CHARACTER IN INPUT

GET
GETNYB
NOBYT
GET

SHIFT NYBBLE TO HIGH NYBBLE
SAVE IT
GET LOW NYBBLE NOW
BAD CHARACTER
C-BIT CLEARED

•

GETNYB

•
•
•

A GETS THE NYBBLE TYPED IF IT WAS IN THE RANGE O-F.
OTHERWISE A GETS THE CHARACTER TYPED. THE C-BIT IS SET
ON NON-HEX CHARACTERS;
CLEARED
OTHERWISE.
X
IS
UNCHANGED.

GETNYB

GOTIT
13

BSR
BCS
ASLA
ASLA
ASLA
ASLA
STA
BSR
BCS
ADD
RTS

NOTHEX

BSR
AND
STA
SUB
BMI
CMP
BLS
SUB
CMP
BHI
CMP
BLS
CLC
RTS
LDA
SEC
RTS

GET HEX NYBBLE FROM TERMINAL

GETC
GET THE CHARACTER
#%1111111 MASK PARITY
GET+3
SAVE IT JUST IN CASE
#'0
SUBTRACT ASCII ZERO
NOT HEX WAS LESS THAN '0'
#9
GOTIT
#'A-'9-1 FUNNY ADJUSTMENT
#SF
TOO BIG?
NOT HEX WAS GREATER THAN 'F'
#9
CHECK BETWEEN 9 AND A
NOTHEX
C=O MEANS GOOD HEX CHAR

RETURN WITH ERROR

SERIAL

06F6 00 02
06F6 00 02
06F6 00 03

06F6
06F8
06FA
06FC

BF
A6
B7
04

15
08
17
02 FD

GET SAVED CHARACTER

GET+3

I/O

ROUTINES

*

DEFINITION OF SERIAL I/O LINES

PUT
IN
OUT

EQU
EQU
EQU

•
•

A GETS THE CHARACTER TYPED. X IS UNCHANGED.

PORTC
2
3

SERIAL I/O PORT
SERIAL INPUT LINE#
SERIAL OUTPUT LINE#

GETC --- GET A CHARACTER FROM THE TERMINAL

•
•

INTERRUPTS ARE MASKED ON ENTRY
AND UNMASKED ON EXIT.

GETC
GETC4

STX
LDA
STA
BRSET

*

DELAY 1/2 BIT TIME

•

XTEMP
SAVE X
#8
NUMBER OF BITS TO READ
COUNT
IN.PUT.GETC4 WAIT FOR HILO TRANSITION

276

PAGE 007
06FF
0701
0703
0704
0707
0709
070A
070C
070D
070E

B6
A4
97
DE
A6
4A
26
4D
SA
26

MONIT
02
03
07 6D
04

AD
OS
7D
36
3A
26

*

GETC3
GETC2

FD
F7

0710 04 02 E9
0713 7D
0714 7D

0715
0717
071A
071B
071D
071F

.P4,1

3E
02 00

*
*
*
*
*
*

GETC7
GETC6

16
17
F4

0721 AD 32
0723 B6 16
0725 BE IS

*
*

0727 81

*
*
*
*
*
*
0728
072A
072C
072E
0730
0732
0733
0734
0735

0737
0739
073B
073D
073F
0741
0743

B7
B7
BF
A6
B7
SF
98
9B.
20

36
24
16
20
17
20
DD

16
14
IS
09
17

PUTC

02

16
04
02
04
02
00
07 55

*
*
*

PUTC5
PUTC2
PUTC3
PUTC4

LDA
AND
TAX
LDX
LDA
DECA
BNE
TSTA
DECX
BNE

PUT
#Ul

GET CURRENT BAUD RATE

DELAYS, X GET LOOP CONSTANT
#4
GETC2
LOOP PAD
GETC3

MAJOR LOOP TEST

NOW WE SHOULD BE IN THE MIDDLE OF THE START BIT
BRSET
TST
TST

IN,PUT,GETC4 FALSE START BIT TEST
,X
MORE TIMING DELAYS
,X

MAIN LOOP FOR GETC
BSR
BRCLR
TST
ROR
DEC
BNE

DELAY
COMMON DELAY ROUTINE
TEST INPUT AND SET C-BIT
IN,PUT,GETC6
,X
TIMING EQUALIZER
ADD THIS BIT TO THE BYTE
CHAR
COUNT
STILL MORE BITS TO GET(SEE?)
GETC7

BSR
LDA
LDX

DELAY
CHAR
XTEMP

RTS

WAIT OUT THE 9TH BIT
GET ASSEMBLED BYTE
RESTORE X
AND RETURN

PUTC --- PRINT A ON THE TERMINAL
X AND A UNCHANGED
SAME GAMES ARE PLAYED WITH THE I-BIT AS IN GETC
STA
STA
STX
LDA
STA
CLRX
CLC
SEI
BRA

CHAR
ATEMP
XTEMP
.9
COUNT

PUTC2

SAVE IT IN BOTH PLACES
DON'T FORGET ABOUT X
GOING TO PUT OUT
9 BITS THIS TIME
FOR VERY OBSCURE REASONS
THIS IS THE START BIT
MASK INTERRUPTS WHILE SENDING
JUMP IN THE MIDDLE OF THINGS

MAIN LOOP FOR PUTC
ROR
BCC
BSET
BRA
BCLR
BRA
JSR

CHAR
PUTC3
OUT,PUT
PUTC4
OUT,PUT
PUTC4
DELAY ,X

277

GET NEXT BIT FROM MEMORY
NOW SET OR CLEAR PORT BIT

EQUALIZE TIMING AGAIN
MUST BE 2-BYTE INDEXED JSR

PAGE (1(18

MONIT

0746
0748
074A
074C

3A
26
14
16

17
ED
02
02

074E
0750
0752
0754

AD 05
BE 15
B6 14
81

.P4:1

*

*

*
*
0755
0757
0759
075A
075D
075F
0761
0762
0764
0765
0767
0768
076A
076C

B6
A4
97
DE
A6
AB
4A
26
5D
14
5A
26
A6
81

02
03
07 6D
F8
09

DELAY

DEL3
DEL2

FD
02
F5
00

*

076D
076E
076F
0770

0771
0771
0774
0777
0777
0779
077B
077D
077F
0780

*
*
*
*

20
08
02
01

DELAYS

*
*
*
*
*
*

DEC
BNE
BSET
BSET

THIS IS WHY X MUST BE ZERO
COUNT
PUTCS
STILL MORE BITS
IN,PUT
7 CYCLE DELAY
SEND STOP BIT
OUT,PUT

BSR
LDX
LDA
RTS

DELAY
XTEMP
ATEMP

DELAY FOR THE STOP BIT
RESTORE X AND
OF COURSE A

DELAY --- PRECISE DELAY FOR GETC/PUTC
LDA
AND
TAX
LDX
LDA
ADD
DECA
BNE
TSTX
BSET
DECX
BNE
LDA
RTS

PUT
11%11

FIRST, FIND OUT
WHAT THE BAUD RATE IS

---

DELAYS,X LOOP CONSTANT FROM TABLE
FUNNY ADJUSTMENT FOR SUBROUTINE OVERHEAD
t$F8
#$09
DEL2
IN,PUT
DEL3

LOOP PADDING
DITTO
MAIN LOOP
FINAL TINY DELAY
WITH X STILL EQUAL TO ZERO

to

DELAYS FOR BAUD RATE CALCULATION
THIS TABLE MUST NOT BE PUT ON PAGE ZERO SINCE
THE ACCESSING MUST TAKE 6 CYCLES.
FCB
FCB
FCB
FCB
RESET

300 BAUD
1200 BAUD
4800 BAUD
9600 BAUD

32
8
2
1

POWER ON RESET ROUTINE

CHECK FOR CUSTOMER
ACCORDINGLY.

OR

MONITOR

MODE

AND

BRANCH

RESET

OE 01 03
CC 05 B3

BRSET
JMP

7,PORTB,MONIT
CENTRY CUSTOMER PROGRAM ENTRY POINT

LDA
STA
STA
LDA
SWI
BRA

n1000 SETUP PORT FOR SERIAL 10
PUT
SET OUTPUT TO MARK LEVEL
PUT+DDR SET DDR TO HAVE ONE OUTPUT
PUT
GO TO MONITOR ROUTINE
RESET LOOP AROUND

MONIT
A6
B7
B7
B6
83
20

08
02
06
02
EF

*

*.**.****************.~********.********************** *************

*
*

680 5

278

SELFTEST

PAGE 009

MONIT

.P4.1

•
•
•

GENERAL.
SELFTEST PERFORMS THE FOLLOWING TESTS.

•*
•
•

PORTC -- TEST PORTC FOR GOOD INPUT
I/O -- PORT A AND B FOR INPUT AND OUTPUT
RAM -- WALKING BIT MEMORY TEST
ROM -- EXCLUSIVE OR WITH ODD l'S PARITY RESULT
INTERRUPT -- INT AND TIMER INTERRUPTS

•
•
•
•
•
•
•
•
•
•
•
•

PORTC TEST IS DONE ONLY ONCE JUST AFTER RESET.
ARE REPEATED AS LONG AS NO ERRORS ARE FOUND.

THE TEST STATUS IS AVAILABLE ON PORTC.
AFTER THE PORTC
TEST, PORTC IS USED AS AN OUTPUT TO INDICATE WHICH TEST IS
RUNNING.
IF ANY TEST FAILS, THE OUTPUT LINES REMAIN
STABLE AND THE LOWER 2 BITS OF PORTC INDICATE THE TEST
THAT FAILED (ASSUMING PORTC WORKSI). SINCE THERE ARE ONLY
4 'CHECKPOINTS'
IN THE MAIN LOOP, IT IS NOT POSSIBLE TO
ALWAYS DETERMINE EXACTLY WHAT IS WRONG WITH THE PART.
HERE ARE THE PROBABLE ERRORS IF THE TEST HAS STOPPED.

•
•
•
•
•
•
•
•
•*
•
•

•
•
•

*

•
•*
•

0782

B1 BO

PROBLEM

o
o

0

1

0

1

1

INTERRUPT FAILURE
BAD PORTA OR PORTB
BAD RAM
BAD ROM

1

THE TIME REQUIRED FOR ONE CYCLE OF THE PROGRAM IS
APPROXIMATELY 800 MILLISECONDS. AFTER EACH TEST, PORTC IS
INCREMENTED. THEREFORE, BIT 1 SHOULD APPEAR TO OSCILLATE
WITH A 'PERIOD OF ABOUT 800MS.
IT MAY BE DIFFICULT TO
DISCERN THIS SINCE THE DUTY CYCLE ON BIT 1 IS NOT ANYWHERE
NEAR A SQUARE WAVE.
BIT 2 AND BIT 3 WILL HOWEVER HAVE
SQUARE WAVE OUTPUTS. BIT 2'S PERIOD WILL BE TWICE AS LONG
AS BIT I, AND BIT 3 SHOULD BLINK AT ABOUT 0.3HZ.

*

*
*
*
*
*
*

THROUGHOUT THIS PROGRAM, IT MAY SEEM THAT THE PROGRAMMERS
HAVE GONE OUT OF THEIR WAY TO USE STRANGE INSTRUCTIONS AND
UNUSUAL TECHNIQUES. THIS IS TRUE.
THE PURPOSE OF ALL
THIS IS TO 1) REDUCE THE PROGRAM SIZE AS MUCH AS POSSIBLE
AND 2) TO EXECUTE A BROAD RANGE OF INSTRUCTION TYPES AND
ADDRESSING MODES.
PAG

*
*
*

EQUATES

0782 00 00

ANY

EQU

o

RANDOM BIT IN A BYTE

0782
0782
0782
0782

RAMSUB
LOC
STACKA
STACIOC

EQU
EQU
EQU
EQU

$3F
$20
$7C
$70

START OF BUILT SUBROUTINE
USED IN INTERRUPT TEST
A WHEN STACKED BY INTERRUPT
X THE SAME

00
00
00
00

3F
20
7C
70

•

THE OTHERS

*
*

279

PAGE 010

MONIT

.P4:1

0782

ORG

0784 9C
0785 33 02
0787 26 FE

0789 10 06

*
*
*
START

*
•
*

•
•

078B 3F 09
0780 83

078E
0790
0792
0794
0796
0798
0799
079B

AE
A6
AD
A9
AD
SA
27
4F

01
FO
44
BA
40

*

LOOP

•
•
*
•

IOTST
IOTST2

FS

079C 83

•
*
*
*
•

*
*
*
*
•

*
*

0790
0790
079F
07110
07Al
07A3
07A4

*
*

MEMSIZ-1l6-8

BEGIN OF SELF TEST
RSP
COM
BNE

PORTC

•

RESET JUST IN CASE (AVOID STACK INIT PR08LEM)
SHOULD HAVE READ $FF
PORTC BAD ON INPUT

COM SET PORTC TO ZERO
BSET

ANY.PORTC+DDR AND PROGRAM DATA DIRECTION

MAIN LOOP (REPEATED)
CLR

TIMER+l RESET TIMER INTERRUPTS

SWI

PASSED FIRST TEST

INPUT/OUTPUT PORT TESTS
LDX
LDA
BSR
ADC
BSR
DECX
BEQ
CLRA

tPORTB

POINT TO PORTB FIRST

UFO

IOSUB
RETURNS WITH A=$54
#$OF-$54-1 A IS SET TO $OF
IOSUB
AGAIN WITH NYBBLES REVERSED
IOTST2

SWI

AGAIN FOR PORTA
CLEAR A FOR NEXT TEST
PASSED I/O TEST

RAM TEST
ENTER WITH C=l. A=O.
THIS TEST IS MODIFIED FROM THE ORIGINAL P2 RAM TEST.
A
NEW TEST IS NECESSARY BECAUSE THERE ARE 112 BYTES OF RAM
ON THE P4. THE OLD RAM TEST WORKED BECAUSE THE TEST
SEQUENCE WAS 9 BYTES LONG. AND THERE WERE 64 BYTES OF
RAM. 64 MOD 9 IS 1. SO A SINGLE ROTATE WAS SUFFICIENT TO
RESTORE THE SEED. 112 MOD 9 IS 4 WHICH REQUIRES 4
ROTATES TO GET BACK TO THE INITIAL PATTERN.
THIS
EXCEEDES THE AVAILABLE ROM.
THE NEW RAM TEST IS MUCH SIMPLER. BUT WILL TEST ALL THE
BYTES.
THIS CHANGE AFFECTS THE SUBSEQUENT TESTS SINCE
THEY MUST NOW INITIALIZE THEIR OWN VARIABLES INSTEAD OF
RELYING ON THE RAM TEST TO DO IT FOR THEM.
RAM WILL BE ALL ZEROES AFTER THIS TEST.

RAMTST
AE 10
F7
Fl
26 FE
4C
7C

RAM2
RAM 3

LDX
STA
CMP
BNE
INCA
INC

tRAM
.X
.X

*

CLEAR OUT A BYTE
COMPARE WITH ACCUMULATOR VALUE
MEMORY MISMATCH

.X

BUMP BOTH VALUES

280

PAGE 011

MONIT

.P4:1

07A5 26 F9
07A7 5C
07AB 2A F5

BNE
INCX
BPL

*

*

*

07AA 83

*
*
*
*

*

07AB
07AB
07AD
07AF
07Bl
07B3
07B5
07B7
0789
07BB
07BD
07CO
07Cl

ADVANCE TO NEXT RAM BYTE
CONTINUE TILL ALL TESTED

RAM2

EXIT WITH A=O, X=$80
SWI

PASSED RAM TEST

ROM TEST
FORCE A RESULT OF $FF (l'S PARITY). THE CHECKSUM HAS BEEN
CHOSEN TO FORCE THIS RESULT IF THE ROM ITSELF IS GOOD.
ADDRESS AND DATA LINES STUCK HIGH, LOW OR TO EACH OTHER
ARE DETECTED WITH HIGH PROBABILITY.

*
*

FOR A DISCUSSION OF THE RELIABILITY OF THIS METHOD OF
TESTING THE ROM, SEE "MICROPROCESSOR BASED DESIGN" BY DR.
J. B. PEATMAN, PAGES 315-316.

*

ENTER WITH A=$OO,X=$80,RAM=OO

ROMTST
BF
AE
BF
AE
BF
BD
3C
22
3C
07
43
26

41
CB
3F
Bl
42
3F
41
FA
40
40 F5

SUM

FE

07C3 B3

STX
LDX
STX
LDX
STX
JSR
INC
BHI
INC
BRCLR
COMA
BNE

RAMSUB+2
tSC8
=EOR EXTENDED
RAMSUB
#$81
=RTS
RAMSUB+3
RAMSUB
RAMSUB+2 ADVANCE TO NEXT ADDRESS
SUM
RAMSUB+l
3,RAMSUB+l,SUM LOOK FOR S8 IN RAMSUB+l
A SHOULD HAVE BEEN $FF,
*
HANG HERE FOR BAD ROM

SWI

PASSED ROM TEST

*

INTERRUPTS TEST

*

ENTER WITH: X=S81
A=$OO
LOC=$80

*
*
*
*

*
*

*
*
*
*

*

*
*
07C4

RAM3

INTERRUPT TEST ALLOWS INTERRUPTS LONG ENOUGH TO GET ONE
TIMER INTERRUPT AND ONE INT INTERRUPT.
THE INTERRUPT
SERVICE ROUTINES SHIFT A BYTE IN MEMORY TO A KNOWN PATTERN
WHICH IS CHECKED AFTER THE INTERRUPTS SHOULD HAVE OCCURED.
FURTHER, THE A AND X REGISTER ARE COMPARED WITH WHAT WAS
STACKED DURING THE INTERRUPTS.
A TIMER INTERRUPT IS GUARANTEED PENDING BY ALLOWING ENOUGH
TIME TO ELAPSE DURING THE OTHER TESTS TO UNDERFLOW THE
COUNTER (EVEN WITH MAXIMUM PRE-SCALE). THE INT INTERRUPT
IS ALSO GUARANTEED SINCE THE INT LINE IS TIED TO THE PORTA
LINE WHICH WIGGLES UP AND DOWN DURING THE I/O TEST.

*

INTTST

281

PAGE 012
07C4
07C6
07C7
07C8
07CA
07CC
07CE
0700
0702

IE
9A
9B
2C
BO
26
B3
26
OB

MONIT

.P4.1

20

BSET
CLI
SEI
BMC
SUB
BNE
CPX
BNE
BRCLR

FE
7C
FE
70
FE
20 FD

NOTE THE USE OF A 2-BYTE ,INDEXED JUMP WHICH FORCES A CARRY
FROM THE LOWER BYTE IN COMPUTING THE JUMP ADDRESS.

•
•

I/O TEST SUBROUTINE

*

ENTERED WITH X POINTING TO THE PORT
TO TEST. A HAS THE DDR PATTERN TO USE.

*
*

IOSUB

AGAIN

Fl

26 FE
48
2B F9
81

•*
*

**
*
*

SOFT

•
•

07E7 IF 09
07E9 37 20
07EB 80
07EC 00 00 00
07EF 9B

07FO 07 E7
07F2 07 E9
07F4 07 E4

JMP LOOP-$81,X DO IT AGAIN

•

*

07E4 3C 02
07E6 80

*

5,LOC,· BIT SHOULD SHIFT HERE

*

•

E7 04
A6 55
F7

*

STACKX

END OF TESTS, DO IT AGAIN

•

0708
07DA
07DC
0700
07DE
07EO
07E1
07E3

*
STACKA

SET FLAG BIT IN LOC
ALLOW INT AND TIMER INTERRUPT
INTERRUPTS SHOULD BE DONE NOW
I-BIT NOT WORKING
COMPARE A WITH STACKED VALUE
INTERRUPT FAILED
ALSO CHECK X

*
*

•
0705 DC 07 OA

7,LOC

*

TIMEUP
INTR

*
CHKSUM

*
*
*

RETURNS WITH A=$54 AND C=l.
STA
LDA
STA
CMP
BNE
LSLA
BMI
RTS

DDR,X
11$55

,X
,X

•

AGAIN

SETUP DATA DIRECTION
ALTERNATE l'S AND O'S
SAVE IT AND SEE
IF IT STAYS THERE
BAD I/O PORT(S)
SHIFT PATTERN TO $AA
AND REPEAT ·TEST

INTERRUPT ROUTINES
SOFTWARE INTERRUPT IS RESPONSIBLE FOR ADVANCING THE
STORED IN PORTC.
INC
RTI

PORTC

ADVANCE TO NEXT TEST
AND EXIT

INT AND TIMER INTERRUPTS
SHIFT LOC ONE PLACE TO THE RIGHT.
BCLR
ASR
RTI

7,TIMER+1 HANDLE INTERRUPT
LOC
SHIFT FLAG AROUND

FCB
FCB

0,0,0
$9B

SPARE BYTES
ROM CHECKSUM (ODD 1'5 PARITY)

SELFTEST ALTERNATE INTERRUPT VECTORS
FOB
FOB
FDB

TIMEUP
INTR
SOFT

282

VALUE

PAGE 013

MONIT

.P4:1

07F6 07 84

FOB

*

07FR

*
07FR
07F8
07FA
07FC
07FE

05
05
05
07

6C
83
09
71

*

START

END RESET WAZU
INTERRUPT VECTORS
ORG

MEMSIZ-R START OF VECTORS

FOB
FOB
FOB
FOB

$56C
$5B3
MAIN
RESET

283

CUSTOMER TIMER INTERRUPT
CUSTOMER INT VECTOR
SWI TO MAIN ENTRY POINT OF MONITOR
POWER ON VECTOR

284

AN900

USING THE M6805 FAMILY
ON·CHIP 8·BIT AID CONVERTER
Prepared By:
Microcontroller Unit (MCUI Systems Application Engineering
Austin, Texas

should never exceed the VCC of the MCV. If VRH-VRL is
below 4.000 volts, the specification accuracy can not be
maintained. Operating below the minimum VRH limit of
4,000 volts may cause the converter to miss steps or lose
accuracy.

INTRODUCTION
This application note covers some factors which should be
considered when using on-chip analog-to-digital (AID) converters. It is intended for the digital designer with little or no
programming experience.
The task of converting analog signals into digital information is becoming easier using today's technology. The
MC6805R3 and MC680SS2 microcomputer (MCVs) have an
on-chip 8-bit AID converter with four user channels to help
accomplish this task. These versatile MCV devices are easy to
use and serve well in automotive, industrial, medical or environmental systems where analog information is monitored,
controlled, or stored.
The merging of analog and digital circuits does present a
problem to the designer who is most familiar and comfortable using only one of the two disciplines. The problem
arises when the analog designer needs to write a program to
process the analog information or the digital designer has to
contend with the analog hardware characteristics with which
he is not totally familiar.
This application note defines the terminology used when
discussing AID converters, describes the circuit elements pertinent to the user, illustrates a self-test hardware/software
technique, and gives an example on how to manipulate the
converted analog .data from a temperature sensor. Program
listings are provided at the end of this application note.

Conversion Time
The AID converter in an M6805 Family MCV is a successive approximation type. A hardware binary-search
method is used to determine the unknown input voltage. This
method significantly reduces the time (total of 30 machine
cycles) needed .to analyze the input voltage and generate a
hexadecimal value accurately. An M6805 Family MCV with
a full-speed, 4-MHz crystal has a I-microsecond machine
cycle, and thus a 30 microsecond conversion time.

DEFINITION OF TERMS
For a better understanding of the characteristics of the
M6805 Family 8-bit AID converter, the key terms used to
describe the capabilities and limitations of an AID converter,
are presented first. Also included in this presentation is a
brief interpretation of the specifications in the current
MC6805R2 data sheet.

Monotonicity IMissing Codes
Monotonicity is a function of the integral non-linearity of
the converter. An AID converter is monotonic if the output
digital value always increases or remains the same when the
analog input voltage is increasing. A non-monotonic AID
converter is one that skips steps or decreases in output digital
value when the input is increasing.
Non-Linearity
Studying the relationship of the analog input voltage with
respect to the digital value that is derived after a conversion
on an ideal AID converter, yields a linear graph similar to the
one shown in Figure 1. Integral non-linearity is defined as the
deviation from an ideal straight-line, transfer function. Differential non-linearity is the amount that a particular step
differs from one least significant bit (LSB). An ideal AID
converter has equal steps, and thus no differential nonlinearity. Total non-linearity error is then the sum of the differential and integral errors.

Conversion Range
The voltage reference high (VRH) and the voltage
reference low (VRO pins establish the voltage range that is
recognized by the converter. The sum of V'RH and VRL

Quantizing Error
The converter's inability to recognize voltage changes of
less than one quantum step is referred to as the quantizing error. Since one increment or quantum is the smallest voltage

285

Ideal
Full Scale

$FF

Input

$FE

8 $FD
2:

I-

:::J
Cl.
I-

:::J

o


The voltage reference high and voltage reference low pins
provide the voltage limits to the digital-to-analog (DI A) converter resistor I capacitor chain in the A/D circuit. The
nominal resistance value between these two pins is approx-

286

At the comparator. the DAC output is compared with the
input voltage stored in the sample and hold capacitor. The
comparator then signals the SAR whether the DAC value is
greater than the sampled value. If the sampled voltage is
greater than the DAC voltage, the SAR binary value is increased to $CO by setting the bit that is adjacent to the
already set MSB. In turn. t)lis increased value increases the
DAC output voltage. If the input voltage is less than the
DAC voltage, the SAR MSD is cleared and the bit adjacent
to the MSB is set. resulting in less DAC voltage to the comparator. This binary-search method continues until all eight
SAR bits have been determined.
At the end of the conversion. the SAR value is transferred
to the AID result register (ARR). This binary value is the approximate digital representation of the analog input within
one LSB of error. A conversion complete flag is set in the
ACR indicating to the user program that a new result may be
retrieved.
The equivalent analog input circuit for one channel entering the multiplexer is illustrated in Figure 3. The worst case
instantaneous current draw is at the beginning of the sample
period. Since the RC time constant of the sample and hold
circuit is approximately 500 nanoseconds. the five machinecycle sample time is more than sufficient to charge the sample and hold capacitor.
The average analog channel input current is less than one
microampere. Thus. no additional buffering of external
transducer signals is required. The analog channel input impedance should not be greater than I K ohms to prevent
capacitor leakage currents from producing unwanted voltage
drops.

$FF represents an analog input voltage of 5.100 to 5.120
volts, provided VRH = 5.120 volts and VRL =0.000 volts. A
dollar sign ($) in front of a symbol identifies it in this document as a hexidecimal number (base 16 number).
Sample TimelSample and Hold Capacitance
The sample time of the M6805 Family AID converter is the
first five machine cycles. This is the actual aperature window
during which the selected analog channel coupler connects
the sample and hold capacitor to the input voltage. The internal sample and hold capacitor charges for five machine
cycles. and then holds that charge on the comparator input
during the remaining 25 cycles of the conversion period.
The analog input voltage ideally should stay constant during the sample period. Any variation contributes to the conversion error. It is desirable to hold the input voltage within
0.5 LSB variation during the sample window. Under extreme
operating conditions. the first conversion obtained after
selecting a new channel may be less accurate than later conversions of the channel. Input channel changes can affect the
stored sample and charge.
The input voltage on the channel coupler should not exceed VRH nor be less than VRL. A voltage greater than VRH
converts to $FF, but no overflow indication is provided.
Since the maximum rate of change of the input signal is
dependent upon the converter sample time, the maximum

frequency of a sine wave input is: F=I(TSxpix2(N+I»
where TS is the sample time and N is the number of bits.
With this equation, the slew rate of the signal does not exceed
0.5 LSB during a sample of the input voltage.
Zero Input Reading/Offset Error
The input offset voltage of the AID comparator causes a
shift in its transfer function. The quantizing error inherent in
the design of the converter causes the 0.5 LSB shift In the
step function. Since a 0.5 LSB error is also allowed in linearity error. an input of 0.000 volts can convert to $00 or $01.

AID CONVERTER SELF-TEST

Designing a test capability into a system simplifies
maintenance, decreases the need for costly test equipment in
the field. and provides an excellent way to learn the system
characteristics. Using a minimum amount of hardware an'
M6805 Family MCU can test its own AID converter in less
than one second for 8-bit accuracy. The objective of this example is to self-adjust the AID converter under test for full
scale error within two LSD and then to test for a correct conversion at the center of each step. The MCU used in this example is an MC68705R3.
The hardware schematic for the AID converter self-test
shown in Figure 4 consists of a voltage stimulus. a programmable voltage reference. and a program storage unit. A
12-bit resolution monolithic current output DAC (U2)
presents the voltages to the MCU AID converter input I An
operational amplifier converts the DAC current output to a
voltage and is fed into the device under test (DUT).
In order to download the test program to the MCU RAM.
a 12-bit binary counter (U7) is used to address an EPROM
(U3). Another 12-bit counter (UI) addresses the DAC in
order to ramp the test voltages to the DUT. The two 12-bit
counters are used to minimize the MCU pins needed for
calibration in user systems. A variable-precision voltage
reference (U5) and a quad analog switch (U6) are used to
derive the voltage reference to the DUT.

THE M6805 FAMILY AID CONVERTER
Figure 2 is a block diagram of the successive approximation AID converter implemented in an M6805 Family MeU.
There are two unique registers which are addressed under
program control. They are used to select a channel. start a
conversion, and read the 8-bit result after a conversion has
been completed.
There are four separate external input channels which can
be individually coupled to the comparator input by writing to
the three lower order bits in the AID control register (ACR).
There are also four internal input channels which are coupled
to the VRH/VRL resistor chain and can be used as calibration references. Also shown in Figure 2 are the address locations for the external and internal channels.
The converter operates continuously producing a new
result every 30 machine cycles. Bit 7 of the ACR flags the
user when a conversion has been completed and the digital
value of the analog input can be read from the AID result
register (ARR).
When the aperture window closes, the successive approximation register (SAR) addresses the DI A converter (DAC)
with a binary word value of $80. Thus, only the most significant bit (MSB) of the word is set. This value causes the DAC
to generate an analog voltage equal to the midway value of
the conversion range.

BOOTSTRAP PROGRAM (BOOT)
To minimize the amount of ROM occupied by the self-test
program. a 28-byte bootstrap loader routine is suggested.
The bootstrap loader is a short program which is executed

287

D I A Converter
DAC

Successive
Approximation
Logic

6 k !TVP.1

Successive
Approximation
Register

Input
Select
Multiplexer

AID

AID

Control

Result
'---''---L_c..J.._..L.._'-_'---'_..J Register
IARRI

Register L...;:...Jc.......IC-...L_-"_..L..::::..J""'::c..J..";::;'.J
IACRI

AID INPUT MUX SELECTION
Input Selected

Control Status Register

ACR2

ACR1

ACRO

a
a
a
a

a
a

1

0

a
I
a
1
a
1
a

1
1

a

1
1

1.
1

1

ANa
ANI
AN2
AN3
VRH"
VRL'
VRH!4'
VRH!2'

1

"InternallCalibrationl Levels

FIGURE 2 - AID Converter Block Diagram and Input Select Code

Digital Input
Port

~
L

To Comparator
Input

To Input Select
Control

Input Protection

Devices

FIGURE 3 -

Analog Channel Input Circuit

288

VCC= +5 V±0.25 V
VCC

+15V-

VCC

~

116
01 9
7
02
6
03
5
Ul 04
3
05
0
3.... 06 24
U 07 13
::;; 08
12
09
14
010
15
011
VSS 012 16
RST ClK
.------J 11 110

-t-

VCCI16
VCC VSS 8

~

§
U
::;;

RST ClK
11
10

13 12

5
U6

1

1,14
+ 15
R4
390

>--

1

19\

3 16 T9 h2 TlO 14
MCl40668

F

8

4-::!1

11
Rl

R2
390

R3
390

R8
i J l lC 9
C3 C2Cl CO
20k
VRH
XTAl ~
7
Vpp

~*

VCC
C6
C7 17

390

3

VCC

U7

I

M~l404 5

7
6
5
3
2
4
13
12
14
15

13 VCC
14
15
16
17
18
19
20
21
22
23
24

~:

50k 20 turn
R5

\j
U2
MC3412

22 ~~
19 AlO

MC68706R3
MCU

l

Ai

r:-::--

~~6

U3

!e

r,
N

-&

lo.D1I'F

4 1

-=

-15V

ANO
23
ANl
22 AN2
Lll AN3

C5

15

S2~

VCC

14

DAC
Full

~ ,~.'"

4.7k

C4

Sl~

30 pF

OAC
Zero Cal.

R11

9
10
11
13
14
15
16
17
18
E 20

33 AO
3435 Al
36 A2
37 A3
38 A4
39 A5
40 A6
25 A7
BO
26 Bl

00
01
02
03
04
05
06
07

G
VSS

lli
kb.

47 k

U4
3M
9RT ~ lMl08
~
6
12
3 +
8

VC'itm
24 21
VCC VPP
8 AO
7 Al
6 A2
5 A3
4 A4
3
2 A5
1 A6
23 A7

grounds.

100
R15

-15VR6 +15V
20 k
7

VEE
-15V17

and digital

n

10

Single Tie POint

between analog

1l-Ll-=1=-

~CC
4.7 k

17T2 VRESET
-

-::~
.... ( ' 11'F

FIGURE 4 - On-Chip AID Converter Self-Test
and Self-Calibration-Schematic Diagram

289

"Bad
~VCC

Good

B5

27

*-&

R12
300

~, ~
~

I--

B4tSS INTVRl
-.1 1-.1 3 j20

~

300

~"l~

B2
R13

(

83

28

~VCC
4.7 k

when a particular condition is met after the MCU comes out
of reset. The bootstrap program loads a short test program
from an external memory device into on-chip RAM and executes the program.
The condition selected in order to execute the bootstrap
loader program is a logic low level on the interrupt pin when'
coming out of reset. When the interrupt pin has a logic high
level, the user main program is entered. The address of the
label "load" in the bootstrap program is used in the self-test
program to jump back to load new routines. The bootstrap
loader approach is not limited to the AID converter self-test
program. It can be used to examine or test other system
features.

output a value of $FE since the analog input switch pOint
from SFE to SFF would he 5.140 volts using this reference
value. Table I represents the voltage inputs that cause a
switch in the digital output of the AID converter when using
a VRH+ VRL of 5.120 V.
The analog switch is controlled by the four lower order bits
of port C. As port C is incremented, it causes a decrease of 10
millivolts on the output of the voltage reference, US. An
AID conversion is done after each port C increment to check
for a value of $FF.
When the AID converter recognizes the input voltage as
an $FF, port C is left constant at that value for the next test.
This self-adjusting routine compensates for the variation of
full-scale error from one device to another and eliminates
having to manually adjust each unit before test.

SELF-TEST SOFTWARE (AiDTST)
The self-test software consists of three sequential loads.
This requires the bootstrap loader to jump to RAM after
downloading, execute a program from RAM, then return to
the bootstrap loader to download the next routine. When the
MCU comes out of reset, the interrupt pin is held low in
order to enter the bootstrap loader routine.
The bootstrap program uses port B bit I to clear the
counter and port B bit 0 to increment the count on a negative
transition. The program is fed into port A and stored to
RAM.
The index register is used as the RAM pointer and is tested
for a negative value after each RAM byte load. Since the
negative status bit in the condition code register is set when
the accumulator holds a value between $SO and $FF, the
loading routine ends when the index register reaches a value
of $80. The Figure 5 flow chart illustrates the interaction between the bootstrap loader routine (BOOT) and the AID
converter self-test routines (A/DTST).

AID Linearity Test
The third and last routine is the actual AID converter
voltage ramp test. The 12-bit DAC is cleared then ramped in
20-millivolt increments to check the center of each AID step
for a correct conversion. At the end of the 256 voltage steps,
the program outputs a logic low level on the port B bit 2 to
turn on an LED, indicating a good device.
If at any point during the 256 voltage steps a conversion is
incorrect, testing is stopped and the program outputs a logic
low on port B bit 3 to signal that the AID converter failed the
test. The AID converter linearity is thus confirmed to be
within one LSB (20 millivolts) of the proper reading.
TEMPERATURE SENSOR CONVERSION
Monitoring temperature for display or control is a key factor for energy conservation or process control in closed loop
systems. The objective in this portion of the application note
is to demonstrate how to manipulate the converted an'alog
signal from a temperature sensor for display.
By monitoring the base-emitter voltage variations on the
Motorola MTS-102 silicon temperature sensor, the MCU
converts that analog information into an equivalent digital
value in degrees fahrenheit and displays it on three 7-segment
displays.
Many tasks can be performed after the conversion is complete. One typical application for this circuit is a ceiling fan
control to increase room air flow for a period of time before
turning on the main central air conditioning unit. If the
temperature does not decrease after a timeout period, then
the central air is turned on for a period of time.
The Figure 6 schematic shows how the sensor voltage is
amplified to give 20-millivolt steps per degree fahrenheit. A
dual differential amplifier (U2) buffers the sensor voltage
and then inverts and amplifies the signal before entering the
AID converter on the MCU. An amplifier gain of eight produces 10 millivolts per degree fahrenheit, and a gain of 4.444
produces to millivolts per degree centigrade.
In order for the AID converter to recognize one degree
steps, the gain must be doubled. The maximum output
voltage on the -differential amplifier is approximately 3.8
volts using a VCC of 5 volts. Therefore, the temperature
sensing range is from - 40 degrees to + 140 degrees fahrenheit.
The Monsanto LED displays have a common anode and
are driven directly by the MCU port B. To update the
displays, port C bits 0, I and 2 enable ,each display sequentially every 2048 machine cycles. The regulated voltage from
U 1 is tied to the MCU VCC as well as to the displays and is
used ratiometrically with respect to the VRH pin and the

12-Bit DAC Calibration
The first routine is used to calibrate the 12-bit DAC (U2)
and the precision voltage reference (U5). The ideal VRH level
selected is 5.120 volts for 0.020-volt steps. Therefore, the
first step is to preset U5 with R5 to 5.160 volts (2 LSB above
the ideal VRH) while the MCU is held in reset.
The next step is to calibrate the 12-bit DAC zero output
for 0.000 volts and the full scale output for 5.100 volts. This
routine is executed only if port C bits 4 and 5 are held low.
This is done by closing SI (zero calibrate select) and S2 (full
scale calibrate select) before bringing the MCU under test out
of reset.
The 12-bit DAC zero offset adjustment is set by varying
R6 while monitoring the DAC output for a value of 0.000
volts. Opening the bit 4 switch causes the DAC to be incremented to $FFO and held there for the full-scale error adjust provided the bit 5 switch is closed.
The DAC should then be calibrated to 5.100 volts by varying R15. Opening the bit 5 switch causes the calibration
routine to terminate, and the second routine is then downloaded. The DAC calibration routine is normally done once
after initial power-up and is skipped if the port C switches
are open.
On-Line AID Calibration
The second routine in the self-test exercise is the AID converter automatic full-scale error adjust. The DAC is incremented to $FES (5.090 V), which is the AID converter
switch point between $FE and $FF. All analog switches on
U6 are off at this time so the voltage reference to the DUT is
5.160 volts (VRH ideal+2 LSB). The AID converter should

290

Segment 1 of AID Test

Boot Program
I Bootstrap Loader)

$81

$83

$99

Clear EPROM
Address
Counter

Watt

$8B

Load Program
from EPROM
to MCU RAM

$97

Jump to
Program
in RAM
Walt

Note:
Segments 1. 2. and 3 of the AID test reside in RAM starting
at address $40 after being loaded by the Boot program.

FIGURE 5 -

Boot and AID TST Program Flow Chart
(Sheet 1 of 21

291

Segment 2 of

AI D

Segment 3 of AID Test

Test

$40

$40

Reset 12
Bit DAC

Reset 12
Bit DAC

Preset X-Reg
for Correct
ConversIon
Value

Increment

DAC to
$FE8

Do an

AID
ConversIon

Increment

Port C to

Set Flag
for Bad

\

No

AID

Increment

X-Reg and
DAC to Next

Set Flag
for Bad

AID

Set Flag
for Good

AID

FIGURE 5 - Boot and AID TST Program Flow Chan
(Sheet 2 of 21

292

I
O>----I~.....O-ol-I'-F-+~--------f~~1-51'-F---I

9-15Vdc

lN4003

"1
Ul

~-f""-=>--l-I'~-e-,'co' " " "

I
14

T7

Vec

Vpp

-=

~ VRH

RESET

407 k

~

11'F =~

~~

47 k

t

MTS102

100 k
Vce

50k

2N 2907

Vee
\14
A

-Common
Anode

FI

- 1
G

8

E/_ Ic
D

U4

G FEDC8A
11 2 7 8 0~311

J

,~

L~

t,~

OoOO1 1'F

-=

MAN 81
LED
Displays

R3
15 k 1%

3V

-=-

Temperature
Senso r

1

14

-=7

fO

XTAL
24 ANO

o01 1'F
INT
TMR

240

11
C2
10
el
9 eo
U3
MC68705R3

14

I-- I
I-- I

U5

G F E De 8 A

U6

G FED C 8 A

11

I 1 100

1

1

FIGURE 6 - Temperature Sensing AID
Demonstration-Schematic Diagram

293

-=-

VSS

-

-I- I

I-- I

~

10 turn

ve~

tll'F

~ VRL

R2
240 k 1%

U2
LM358

Vee

25
80
26
81
27
82
28
83
29
84
30 85
31 86

6

20 k

tr

Ve e

1

sensor supply. Thus, any variation on the aJl1plifiers also occurs on the VRH pin.
Since the MC68705R3 has an EPROM erasing window. it
is necessary to cover it after prQgramrning so that the AID
convener will maintain its a-bit accuracy. It is also recommended that the MTS 102 sensor leads be moistured-sealed
with epOllY. About 12 to 18 inches of twisted. stranded,
22-gauge wire was used to connect the sensor to the amplifier
input.
The Figure 7 flow chart describes the sequence of events in
the temperature sensor program (TMPSNS). After port initialization, the timer is enabled to periodically update the
7-segment displays. An AID conversion is performed and the
r~ult is converted to binary-coded-decimal (BCD) format
for the display routine.
Zero degrees fahrenheit is equal to a conversion of $30 so
the AID conversion result must be offset before converting
to a BCD number. Since the displays are updated during a
timer interrupt, the MCV goes into a wait loop before doing

another AID conversion. This is a good entrypoint for appending new tasks to the basic program such as time of day
or controlling a heater or air conditioner.
Calibration of the temperature sensor is performed by
varying the 50 kilohms potentiometer (Rl) on the differential
amplifier fora reading of 32 degrees after a piece of ice has
been placed on the sensor for approximatiey one minute.
Refer to the MTS-102 specification for further details.
SUMMARY
The terminology used to describe an AID converter
characteristics has been discussed and related to the electrical
characteristics in the M680S Family AID converter specifications. A circuit and program which tests the on-chip AID
converter was also discussed to familiarize the reader with a
method of calibrating the AID converter. A typical
temperature sensor application was covered with the intent
of showing the sequence of events that take place when converting the AID result to a displayable value.

TABLE 1 - Voltage Versus Output for 8-Bit AID Convener
VRH =5.120 V
VRl =0.000 V
Hillo

0

1

2

3

4

5

6

7

8

9

A

B

C

0

E

F

°0
1
2
3
4
5
6
7
8
9
A
B
C

0.010
0.030
0.050
0.070
0.090
0.110
0.130
0.150
0.170
0.190
0.210
0.230
0.250
0.270
0.290
0.310

0.330
0.350
0.370
0.390
0.410
0.430
0.450
0.470
0.490
0.510
0.530
0.550
0.570
0.590
0.610
0.630

0.650
0.670
0.690
0.710
0.730
0.750
0.770
0.790
0.810
0.830
0.850
0.870
0.890
0.910
0.930
0.950

0.970
0.990
1.010
1.030
1.050
1070
1.090
1.110
1.130
1.150
1.170
1.190
1.210
1.230
1.250
1.270

1.290
1.310
1.330
1.350
1.370
1.390
1.410
1.430
1.450
1.470
1.490
1.510
1.530
1.550
1.570
1.590

1.1,10
1.630
1.650
1.670
1.690
1.710
1.730
1.750
1.770
1.790

1.930
1.950
1.970
1.990
2.010
2.030
2.050
2.070
2.090
2.110
2.130
2.150
2.170
2.190
2.210
2.230

2.250
.2.270
2.290
2.310
2.330
2.350
2.370
2.390
2.410
2.430
2.450
2.470
2.490
2.510
2.530
2.550

2.570
2.590
2.610
2.630
2.650
2.670
2.690
2.710
2.730
2.750
2.770
2.790
2.810
2.830
2.850
2.870

2.890
2.910
2.830
2.950
2.970
2.990
3.010
3.030
3.050
3.070
3.090
3.110
3.130
3.150
3.170
3.190

3.210
3.230
3.250
3.270
3.290
3.310
3.330
3.350
3.370
3.390
3.410
3.430
3.450
3.470
3.490
3.510

3.530
3.550
3.570
3.590
3.610
3.630
3.650
3.670
3.690
3.710
3.730
3.750
3.770
3.790
3.810
3.630

3.850
3.870
3.890
3.910
3.930
3.950
3.970
3.990
4.010
4.030
4.050
4.070
4.090
4.110
4.130
4.150

5.170
4.190
4.210
4.230
4.250
4.270
4.290
4.310
4.330
4.350
4.370
4.390
4.410
4.430
4.450
4.470

4.490
4.510
4.530
4.550
4.570
4.590
4.610
4.630
4.650
4.670
4.690
4.710
4.730
4.750
4.770
4.790

4.810
4.830
4.850
4.870
4.890
4.910
4.930
4.950
4.970
4.990
5.010
5.030
5.050
5.070
5.090
5.110°

D

E
F

uno
1.830
1.850
1.870
1.890
1.910

NOTES: II) Voltages in the chart represent the switch point between steps. For example, 0.010 volts is the switch point belween $00 and $01.
121 Due to quantiZIng error. the center of each step is the chart value minus 10 millivolts. The last step does not overflow.
(3) The first step {oJ equals 10 minivolts; the lasl step 1°) equals 30 millivolts.

294

Binary to BCD

Main Program Flow

Subroutine Conversion

S90

Initialize
Ports, Slack
Enable Timer

SC5

Interrupt

SA7

Ttmer In1.
and Clear
BCDLO Reg.

Do an

AID Conversion
$C8

SBq,

Subtract
30 Hex
from AID
Result

,CB

SB6

$CE

SB8

Negate
Result &
Put a Minus
Sign in BCDLO

SBD

Transfer
Result to
X-Reg.

$D4
No

$D6

Add S06
to BCDLO
Register

SDE

SBE

No

SC 1

Branch
Subroutine
Delay
Clear
BCDLO
Register

NOTE:
When the timer interrupts the main program flow, go to the
timer interrupt routine {next pagel. When the timer interrupt
routine is finished, the MCU will automatically return to the
next operation in the main program flow.

Increment
BCD Hi
Register

FIGURE 7 - Temperature Sensor (TEMPSNSI·Program Flow Chan
(Sheet 1 of 21

295

TIMER INTERRUPT ROUTINE
tBCD to 7-Segment Displayl

Set the
SF2

Carry

High Nibble
of Value
To Be DIsplayed

SIll

BIt

SF3

Turn Off
DIsplay

Dnvers

SF7

$104

ShIft High
Nibble of
BCDLO Byte

Select
the Next

Transfer
Valve to
X-Reg.

S113

Load X-Reg.
from Table

$114
SI08

Turn
$116

SlOB

Fetch
BCDHI
Byte

Select Most
SFB

Display
Drivers on
with New Valve

$118

Significant

Enable
Selected
Display

DIsplay to
Update
SlOD

SFF

Sl1C

Fetch
BCDLD
Byte

Reset TImer
for Next
Interrupt

SlOF

Load Acc.
WIth Table
$124

FIGURE 7 - Temperature Sensor (TEMPSNS) Program Flow Chan
(Sheet 2 of 2)

296

PAGE

001

.SA, I

BOOT

00001
00002
0000]
00004
0000;
00006
00007
0000
A
00008
0001
A
000;
00009
A
00010
00011
00012
OOOl3A 0080
00014A 0080 9C
0001 ;A 0081 2F 16
0099
00016A 008] A6 0]
A
00017A 008; B7 01
A
A
00Ol8A 0087 B7
OOOl9A 0089 13 01
A
A
00020A 008B AE 40
A
00021A 008U 86 00
00022A 0080' n
A
OD023A 0090 11 01
00024A 0092 10 01
A
;c
0094
0OO2:'>A
0080
00026A 009; 2A f"6
00027A 0097 BC 40
A
00028A 0099 CC 0100
A
00029
TOTAL ERRORS 00000--00000

BOOT
NAM
OPT

BOOT
LLEN-IOO

iIr****LABEL DEFINITION***·*
PORTA
PORTB
DDRB

EOU
EOU
EQU

a

iIr****GENERAL PURPOSE BOOTSTRAP LOADER ROUTINE*****

A"

LOAD

EXIT

ORG
RSP
BIH
LOA
STA
STA
BCLa
LOX
LOA
STA
BCLR
BSET
INCX
BPL
JMP
JMP
END

$80
EXIT
U$O]

PORTB
ODRB
I.PORTB

NORMALLY THE START LOCATION WILL BE
THE USER RESJ::T VECTOR.
TEST INTERRUP PIN FOR BOOTSTRAP ENTRY.
HAKE PORTB BITS 0 AND I OUTPUTS.
RESET 12-BIT COUNTER.
ENABLE 12-BIT COUNTER.

U$40

PORTA

.x
a,PORTH
O.PORTB
LOAD+2
540
$100

PORTA IS INPU'r WHEN COMING OUT OF RESET.
STOR~ CONTENTS OF PORTA TO RAM.
INCREMENT 1 2 - BIT COUNTER.

CONTIN-UE LOADING TILL X REG .. 80.
JUMP TO RAM AND EXECUTE PROGRAM.
JUMP TO USER MAIN PROGRAM OR EXECUTE FROM HERE.

297

PAGE

001

SLFTST

.SA; 1

A/DTST

00001

NAM
A/DTSl
OPT
LLEN-l00
ORG
SOD
1I****LABEL DEFINITION**·*·
PORTA
0
EO"
PORTS
EO"
PORTe
EQU
PORTO
EO"
DORA
EO"

00002

00003A 0000
0000 ..
0000;

00006

0000
0001

C111t)(l;

0002

CICll10S
,1t1 (),,1\l

0003
000 ..

,'ll\'i,l

ClOOS

(11)\'1. .
lllh112

Ol106

000;
0(108
0009
OOOA
UOOB
OOOC
0000

00013
0001 ..
00015

00016
00017
00018
00019
00020
00021
00022
00023

OOOE

OOOF
008B

A
A
A
A
A
A ODR8
A OORC
A !'JC7

A MSR

EOU
EOU
EOU
EOL
EOU
EQli

A peR

EQU

NC2

EO"
EOU
EQU
EOU
EQU

A TOR
A TCR

A
A
A
A
A

NC3
ACR

ARR
LOAD

10
II
12

13
14

15
EXAMPLE LOCATION OF BOOTSTRAP lOADER

S8B

...... ·**SEGMENT 1 OAC CALIBRATION ROUTINE·*··*

0002 ..
0OO2SA
00026A
00027A
0002BA
00029A
0OO30A
OQ031A
00032A
00033A
0003 .. A
00035A
00036A
00037A
0003BA
(JOO39A
0OO40A
(JOO41A
0OO42A
OOOol43A
OOO .... A
000 .. 5;\
00046A
(JOO47A

0000
0001
0003
0005
0007
0009
0008
0000
OOOF

9C
AE
BF
3F
AE
BF
AE
BF
lA

FO
01
02
OF
06
3F
05

01
0011 lB 01
0013 09 02 FO
0016 OA 02 14
0019 AE FF
OOlS A6 10
0010 19 01
OOlF 18 01
0021 .A
0022 26 F9
0024 SA
002S 26 F4
0027 08 02 FO
002A 09 02 E2
0020 BC 88

A
A
A
A
A
A
A
A CAL

RSP
LOX
STX
CLR
LOX
STX
LOX
STX
BSET

IISFO
PORT8

INITIALIZE STACK
INITIALIZE PORTB BUT INSURE
BITS 0 AND 1 DO NOT CHANGE

PORTC
II$OF

PORTC 0- 3"OUTPUTS

OORC
IIS3F

PORTS

OORB
S. PORT8

BClR

'). PORTS

BRCLR

... PORTC,

0020
A
A
A

BRSET

S.PORTC.ENDI
fl$FF

001])

001B
0027
oaOF
A ENOl

OECX
BNE
BRCLR
BRCLR
JMP

A

... OUTPUTS

CLEAR DAC 12-RIT COUNTER

.

A
0013

LOX
LOA
BCLR
BSET
DECA
Sr-;E

o-~

STOP HERE AND CAL.
EXIT CAL.

O.OOOV IF PC4:::0

ROUTINE IF PCS-1

11$10
4. PORTS

TOGGLE DAC 12-BIT COUNTER

4, PORTB

16 X

2~~

TIMES

... _;
*-lO

.

S, PORTC,
STOP HERE AND CAL. ~.lOOV IF pcs-o
4. PORTC,CAL RECAL. ZERO OFFSET?
RETURN TO BOOTSTRAP TO LOAD NEXT ROUTINE
LOAU

000 .. 8

298

PAGE

002

SLFTST

.SA: 1

A/DTST

00050
OOO~I

****SEGMENT 2

FULL SCALE ERROR ADJUST·**··

000~2
000~3
000~4A

0040

ORG

S40

SECOND ROUTINE MUST START 64 BYTES LATF.R

~, PORTB
5, PORTB
US08
4, PORTB
4,PORTB

RESET DAe 12-BIT COUNTER

OOO~~

OQOS6A 0040 IA 01
000~7A 0042 IB 01
000~8A 0044 AE 08
000~9A 0046 19 01
00060A 0048 18 01

00061A
00062A
00063A
OOQ64A
00065A
00066A
00067A
00068A
00069A
00070A
00071A
00072A
00073A
00074A
00075A
00076A
00077A
00078A
00079A
00080A
00081A
00082A
00083A
00084

004A
004B
0040
004F
OOS!

5A
26
AE
A6
19
00~3 18
OO~~ 4A
0056 26
0058 5A
00~9 26
005B ~A
Dose 3F
005E B6
0060 2A
0062 B3
0064 27
0066 3C
0068 B3
OOM 26
006C 17
006E 20
0070 3A
0072 BC

F9
FE
10
01
01
F9
F4
OE
OE
FC
OF
OA
02
02
FO
01
FE
02
8B

A
A
A
A
A

BSET
BCLR
LOX
BCLR
BSET
DECX
0046
BNE
A
LOX
A LOO!' I
LOA
A
BCLR
A
BSET
DECA
0051
BNE
DECX
004F
BNE
DECX
A ADJUST CLR
A
LOA
OO~E
BPL
A
CPX
0070
BEQ
A
INC
CPX
A
005C
BNE
A FAILl
BCLR
006E
BRA
A END2
DEC
A
JMP

*-5
USFE
OSlO
4, PORTB
4,PORTB

INCREMENT DAC 12-BIT COUNTER
UP TO FEB (5.090V)

*-~

LOOP I
ACR
ACR
*-2
ARR
END2
PORTC
PORTC
ADJUST
3,PORTB
PORTC
LOAD

MAKE X-REGcFF
CLEAR CONVERSION COMPLETE FLAG
WAIT FOR CONVERSION OOCYCLES)
TEST RESULT FOR FF
AND EXIT ADJUST ROUTINE WHEN ARR=FF
ELSE DECREMENT VRH VOLTAGE
CONTINUE SEARCH TILL PORTC=OF
IF UNSUCCESSFUL THEN STOP
AFTER SETTI NG FLAG
READJUST FOR LAST PORTC INCREMENT
RETURN TO BOOTSTRAP LOADER

299

PAGE
U0086
00087
00088
00089A
00090
00091A
00092A
0009]A

UO]

SLFTST

.. SA: 1

AlDTST

*****SEGMENT 1153
0080
0080
0082
008.
0086
0088
008A
008e
t)OSE
0090
0092
0094
0096
0098
0099
009B
0090
009F
OOAI
00A3
00A5
00A6
00A8
OOAA
OOAC
aOAE

AE
lA
IB
3F
B6
2A
83
Al
25
A6
19
18
4A
26
3F
B6
2A
83
26
;C
26
15
20
17
20

01
01
vi
OE
OE
FC
OF
01
lA
10
01
01

A
A
A
A
A
0088
A
A
l1()AC
A LOOP2
A
A

0009.A
00095A
00096A
-O009iA
00098A
00099A
00100A
00101A
00102A
00103A
F9
0094
00104A
DE
A
00105A
OE
A
OOIOM
00107A
FC
0090
00108A
OF
A
07
00109A
OOAC
oo110A
0092
OOIlIA
EA
01
A
00112A
FE
OOAA
00113A
01
A FAIL2
00114/\
OOAE
0011 SA
FE
00116
TOTAL ERRORS 00000--00000

AID TEST ROUTINE****·

ORC

580

LOX
BSET
BCLR
CLR
LOA
BPL
CPX
CMP
BLO
LOA
BCLR
8SET
DECA
BNE
CLR
LOA
BPL
CPX
BNE
INCX
BNE
BCLR
BRA
BCLR
BRA
END

USOI
5,PORTB
5,PORTB
ACR
ACR
*-2
ARR
"Sal
FAIL2

uSia
4.PORTB
'-,PORTS
°-5
ACR
ACR
°-2
ARR
FAIL2

CLEAR CONVERSION FLAG
WAIT FOR END OF CONVERSION
TEST FOR ZERO INPUT REAOING OF
00 OR 01 AND STOP IF ARR-REG > X-REG
INCREMENT OAC BY 16 STEPS
TO STAY IN CENTER OF 8-BIT STEP

CLEAR CONVERSION FLAG AND
WAIT FOR END OF CONVERS ION
TEST FOR CORRECT CONVERSION AND
STOP IF ARR-REG. NOT EQUAL TO X-REG.

LOOPl

2,PORT8
3,rORTB
·0

INITIALIZE X-REG AS COUNTER
RESET OAC 12-BIT COUNTER

CONTINUE TESTING TI LL X-REG. -00
TURN LEO ON FOR TEST PASS
AND STor
TURN LEO ON FOR TEST FAIL
AND STor

300

PAGE

001

TMPSNS

00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018

.SA: I

TEMPSN
NAM

OPT

TEMPSNS
LLEN-120

**"'··TEMPERATURE DISPLAY PROGRAM"'****
*****REGISTER ADDRESS DEFINITION****'"
0001
0002
OOO~

0006
0008
0009
OOOE
OOOF
0040
0041
0042

00019
00020A 0080
00021
00022
00023
00024

A
A
A
A
A
A
A
A
A
A
A

PORTB
PORTe
DORa
OORe
TOR
TCR
ACR
ARR
BCDHI
BCDLa
SEGMNT

EQU
EQU
EQl1

EQU
EQU
EQU
EQU
EQU

14
I~

EQlJ
EQU
EQU

540
$41
$42

ORG

580

**"'**7-SEGMENT DISPLAY LOOKUP TABLE***"''''
0080

A SEVSEG EQU

40
79
24

A
A
A
A
A

0002~

0002M
0OO27A
0002M
00029A
00030A
OOGlIA
00032A
OOOJJA

0080
0081
0082
0083
0084
008~

0086
0087
00034A 0088
0OO3~A 0089
OOOlbA 008A
00037A 008B
00038
00039
OQ040A 0090
00041
0OO42A 0090
00043A 0091
0OO44A 0093
0OO45A 009~
00046A 0097
0OO47A 0099
00048A 009B
00049A 0090
00050A 009F
OOO~ lA OOAI
000~2A

OOOHA

30
19
12
02
78
00
18
3F
7F

9C
A6
B7
B7
A6
B7
A6
B7
B7
B7

A
A
A
A
A
A
A

START
F7
02
42
07
06
FF
01
O~

08
00A3 A6 OF
OOA~ B7 09

A
A
A
A

A
A
A
A
A

A
A

FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB
FCB

%01000000
7.01111001
7.00100100
7.00110000
7.00011001
7.00010010
7.00000010
7.01111000
7.00000000
tOOOllOOO
7.00111111
7.01111111

ORG

$90

PROGRAM START

RSP
LOA
STA
STA
LOA
STA
LOA
STA
STA
STA
LOA
STA

U$F]
PORTe
SEGMNT
11$07
OORe
OSFF
PORTB
OORB
TOR
IISOF
TCR

INlTIALIZE PORTC TO SELECT THE
MOST SIGNIFICANT DISPLAY FIRST

0

4
6

BLANK

MAKE PORTCO- 2 OUTPUTS
INITIALIZE PORTB TO
TURN OFF AL"L DISPLAYS

PRESET TIMER FOR PRESCALE OF 128
AND UNMASK TIMER INTERRUPT

301

PAGE

002

OOOSSA
000S6A
000S7A
000S8A
00059'"
00060A
00061A
00062A
00063A
00064A
0006SA
00066A
00067A

TMPSNS

00A7
00A8
OOAA
OOAC
OOAE
OOBO
0082
0084
00B6
0088
00B9
008B
OOBO

98
3F
86
2A
86
A2
3F
Al
25
40

TEMPSN
ADC

OE
DE
FC
OF
30
~o

CF
OS

A~

OA
8F 40
97

OOO&8A OOBE AD OS
00069
00070
00071
00012
000 i 3A
00074A
0007SA
000;-6
00077
00078
00079
00080
00081
00082
0008]
0008't
00085
00086A
00087A
00088A
00089A
00090A
00091A
00092A
00093A

• SA: 1

SEI
CLR
LOA
8PL
LOA
S8C
CLR
CMP
8LO
NEGA
A
LOX
A
STX
CONVRT TAX
oocS
BSR

A
A
OOAA
A
A
A
A
OOBD

11$30

CLEAR CONVERSION COMPLETE FLAG
AND SELECT CltANNEL 0
CHECK FOR A CONVERSION COMPLETE
ADJUST THE RESULT REGISTER
SO ZERO DEGREES F-30 HEX

BCDHI
#$CF
CONVRT

CHECK FOR NEGATI VE NUMBER

#$OA
BCDHI
BCD

STORE A MINUS SIGN IN BCDHI

LOAD X REG WITH VALUE
AND BRANCH TO CONVERSION ROUTINE

NOTE: MANY OTHER TASKS CAN BE PERFORMED BEFORE
DOING ANOTHER CONVERSION.

ooeo

9A
OOCI AD 24
00C3 20 E2

CLI
OOE7

BSR
BRA

OOAi

DELAY
ADC

KILL TIME BEFORE DOING ANOTHER CONVERSION
GO CHECK THE TEMPERATURE AGAIN

*****BINARY TO BCD ROUTINE*·""·""

*

THE X REGISTER ENTERS WITH TilE BINARY VALUE

* AND EXITS WITH 00. THE CONVERTED BINARY TO

*

OOCS
OOC6
00C8
00C9
OOCB
OOCC
DaCE

98
3F
SO
2i
SA
]C
A6
Blot

A BCD

,-1

A

1B

00E6

LOOP

.1

A
A

00094A 0002 Al OA

A
00C8
A
A
A
A
OOC8
A
A
00C8

aoua
OOU4
0006
00IJ8
OOOA
OODC
OOOE

26
B6
A8
87
Al
26

f'2
41
06
't 1
AO
E8

00101A OOEO 3}o' .. 1

OOlOZA 00£2 3C ... 0
OOIOlA ODE ... 20 £2

OOl04A 00£6 81
0010i

BCD VALUES ARE PLACED IN RAM FOR THE DISPLAY ROUTINE.

OOCS

OF
.. 1

00095A
00090...
00097 A
00098A
00099A
0010!)A

ACR
ACR
*-2
ARR

A

C;XIT

EOU
SEI
CLR
TSTX
BEQ
DECX
INC
LOA
AND
CMf
BNE
LOA
ADD
STA
CMP
BNE
CLR
INC
BRA
RTS

BCDLO

MASK INTERRUPS TILL YOU EXIT
BCD LOW BYTE INITIALIZE

EXIT

LOOP ENDS WHEN X REC-OO

BCDLO
#$OF
BCDLO
#SOA
LOOP
BCDLO
OS06
BCDLO
OSAO
LOOP
BCOLO
BCDHI
LOOP

MOVE X CONTENTS TO LOW BYTE BCD
MASK OFF HIGH NY88LE OF LOW BYTE BCD

CHECK IF LOW BYTE BCD NEEDS ADJUSTING

ADJU?'f

fo~OR

A BCD VAl.UE

CHECK IF HIGH BYTE BCV NEEDS ADJUSTING
IT AGAIN
CLEAR LOW BYTE BCD
AND INCREMENT HIGH 8YTE BCD
GO DO IT AGAIN
END OF BCD ADJUST

GO DO

302

PAGE
00107
00108A
00109A
OOIIOA
OOIIlA
OOl12A
OOIl3A
OOl14A
00115
00116
00117
00118
00119
00120
00121
00122
00123
00124A
00125A
00126A
00127A
OOl28A
00129A
00130A
00131A
00132A
00133A
00134A
0013SA
00136A
00l37A
00138A
00l39A
00140A
00141A
00142A
00143A
OOl44A
OOl4SA
00146A
00147A
00148A
OOl49A
00150A
OOISIA
00152

003

TMPSNS

00E7
00E9
00E8
OOEC
OOEE
OOE.·
OOFI

00E7
AE FF
A6 FF
4A
26 FO

.SA, I

TEMPSN

A DELAY
A
A
OOEB

~A

26 F8
81

00E9

EQU
LOX
LOA
DECA
8NE
DECX
8NE
RTS

THIS LOOP IS JUST TO KILL TIME
U$FF
U$FF

DELAY+4
DELAY+2

**···BCO TO 7-SEGMEN1' DISPLAY ROUTINE···*·
DISPLAYS ARE REFRESHED EVERY 30MSEC WHEN
A TIMER INTERRUP OCCURS.
THE MOST SIGNIFICANT DIGIT
IS DISPLAYED FIRST.
THE ROUTINE 15 FOR DISPLAYS WITH
COMMON ANODE LEOS.

oon
oon
OOFS
00F7
00F9
00F8
OOFO
OOFF
0101
0104
0105
0106
0107
0108
0108
0100
OIOF
0111
0113
0114
0116
0118
OIlA
Olle
OIlE
0120
0122
0124

oon

99
A6
87
36
25
A6
87
86
02
44
44
44
44
04
86
26
A6
A4
97
EE
8F
86
87
A6
87
A6
87
80

A TMRINT EQU
SEC
FF
A
1.DA
01
A
STA
42
A
ROR
04
OOFF
8es
F8
A
LOA
42
A
STA
41
A L08YTE LOA
42 04. 0108
8RSET
LSRA
LSRA
LSRA
LSRA
42 06 0111 HI8YTE 8RSET
40
A
LOA
02
0111
8NE
A
LOA
08
OF
A OISPLY AND
TAX
80
A
LOX
01
A
STX
42
A
LDA
A
STA
02
10
A
LOA
08
A
STA
OF
A
LDA
09
A
STA
RTI

SET THE CARRY BIT
U$FF
TURN 7-SEGMENT DRIVERS Of'F
PORTS
SEGMNT
SELECT NEXT DISPLAY
LOBYTE
CHECK CARRY BIT FOR RESTART
U$F8
RESTART WITH MOST SIGNIFICANT DIGIT
SEGMNT
8COLO
I.SEGHNT,HIBYTE
SHIFT HIGH NY88LE OF BCDLO
TO LOW NYB8LE FOR DISPLAY

2,SEGMNT.DISPLY
8COHI
DlSPLY
U$08
8 LANK I F ZERO
USOF
SEVSEG,X
PORTB
SEGMNT
PORTC
USIO
TOR
USOF
TeR

303

ENABLE DISPLAY DRIVERS
ENABLE DISPLAY
LOAD TIMER FOR 2048 MACHINE CYCLES
RESET TIMER INTERRUPT F.LAG

PAGE
oonoA
00155A
00156
00157A
001;8
00159A
00160A
tl0161A
00162A

004
OF38
0.-38

TMPSNS

80

• SA: 1

TEMPSN

A

OFF8
OFF8
OFFA
OFFC
OFFE

OOF2
0090
0090
0090

A
A
A
A

00163

TMRVEC
IROVEC
SWIVEC
RESET

ORG
FCB

SF38

sao

PROGRAM MASK OPTION REGISTER
FOR RC CLOCK AND PROGRAMMABLE PRESCALER

ORG

SFF8

RESET VECTORS USING AN MC68705R3

FOB
FOB
FOB
FOB
FoND

TMRINT
START
START
START

TOTAL ERRORS 00000--00000

Motorola, Inc. MC68(7)05R/U tJ;.Bil Microcomputers Advance Information (ADI-977J. Phoenix, AZ: Motorola
Literature Distribution Center, 1984.
Motorola, Inc. MTSIOl Silicon Temperature Sensor Data
Sheet. Phoenix, AZ: Motorola Literature Distribution
Center. 1981.
Sheingold. Daniel H .• ed. Transducer Interfacing Handbook-A Guide to Analog Signal Conditioning. Norwood,
MA: Analog Devices. 1980.
Titus. Jonathan A. Microcomputer-Analog Converter Software & Hardware Interfacing. Indianapolis, IN: Howard W.
Sams & Co .• 1979.

REFERENCES AND ADDITIONAL READING

Clayton, G.B. Data Converters. New York, NY: Halsted
Press Books, 1982.
Jung, Walter G. IC Converter Cookbook. Indianapolis, IN:
Howard W. Sams & Co., 1978.
Motorola, Inc. MC3411 Laser Trimmed High-Speed I1-Bit
D/A Converter Data Sheet. Phoenix, AZ: Motorola
Literature Distribution Center, 1982.
Motorola, Inc. M6805 HMOS MI46805 CMOS Family
Microcomputer/Microprocessor User's Manual. Phoenix,
AZ: Motorola Literature Distribution Center, 1983.

304

AN940

TELEPHONE DIALING TECHNIQUES
USING THE MC680S
Prepared by
Robert Fischer
Downsview, Ontario, Canada

Subroutine PDIAL provides the proper timing sequences
for pulse dialing. The routine is called with the digit to be
dialed resident in the accumulator. Because the timing is not
particularly critical, interrupts that can be quickly serviced
are permissible.

INTRODUCTION
Telephones and associated ancillary equipment providing
intelligent features are fast becoming commonplace. Often,
it is necessary for the microprocessor providing the intelligence to also dial a telephone number.
The M6805 Family microcomputers (MCV), with their
proven hardware/software versatility, are ideal candidates
for such applications. Illustrated here are two cost-effective
methods of telephone dialing. Hardware and software is
given for both Dual Tone Multi-Frequence (DTMF) and
rotary-pulse type dialing.

DTMF DIALING
Dual tone multi-frequency tone dialing is considerably
more complex in terms of ROM usage and external hardware. The M6805 MCV is required to generate two
simultaneous sine waves of different frequencies. Table I
shows the key pad digit and the frequencies of the corresponding tone pairs. Note that the tones fall into two groups:

DEMONSTRATION BOARD DESCRIPTION
Figure I shows the schematic of the demonstration board
designed around a MC68705P3 single-chip MCV. This board
is capable of pulse or DTMF dialing. The type of dialing is
selected by switch S1. A 12-contact keyboard is used for
input. While this is an extravagant use of 110, it is acceptable
for the purposes of a demonstration board.
Pulse dialing requires a direct connection to the telephone
line. Interface to the line is made by a 600-ohm, I: I line
transformer and a relay that provides on/off hook capability. An indicator light (LED #1) shows the current hook
status.
After a power-on reset, the board is in an on-hook state
(LED #1 off). The pressing of any key will result in an offhook state without the digit being dialed. Subsequent key
presses will result in the dialing of the corresponding digit.
Pressing of the cancel button (S2) returns the board to the
on-hook state.
The hardware and software to accomplish either form of
dialing is readily applicable to any number of the M6805
Family.

Frequency (Hz)

Group

697, 770, 852, 941
1209, 1336, 1477, 1633

Low Tones
High Tones

TABLE 1 -

ROTARY PULSE DIALING
From both a hardware and software viewpoint, pulse dialing is by far the simplest form of dialing to implement.
Pulse dialing requires that the telephone line circuit receive
a make/break sequence at a IO-pulse-per-second (PPS) rate
(see Figure 2). The dialing of the digit 3, for example, requires three make/break sequences. The 10-PPS rate requires the use of either a transistor or high speed relay for
line looping. Note that if a low current reed relay is used,
port B may be capable of driving the relay directly
(eliminating the 2N3904 driver).

Keypad Digit and Frequencies for Tone Pairs

Keypad Digit

DTONE Entry

0
1
2
3
4
5
6
7
8
9
A
B
C
D

$0
$1
$2
$3
$4
$5
$6
$7
$8
$9

.,

$A

$8
$C
$D
$E
$F

Tone Pair (Hz)

941
697
697
697
770
770
770
852
852
852
697
770
852
941
941
941

1336
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
1209
1477

Also note that if the seldom used keys A, B, C, and 0 are not
required, it is not necessary to generate a 1633-Hz tone.
The method used to generate the tones uses a series-of 3-bit
look-up tables. Consider a sine wave that has been sampled

305

RESET

VSS

+5V

=

INT
PA7

VCC

O.lk~

Open~

DTMF Dialing
Closed'" Pulse Dialing

EXTAL

PA6

XTAL

PA5

Vpp

PA4

TIMER

PA3

PCO

PA2

PCl

PAB

Sl

1

PAl

S2.-L
0

Cancel
+5V
240 k
120 k
60k

PC2

PB7

PC3

PB6

PBO

PB5

PBl

PB4

PB2

PB3

=

12x4.7k
MC6B705P3

~

30k
4 x 4.7 k

A. B, C~ Yo LM324
Low Pass Filter

Hi Pass Filter

•

+ 12 V

Rx Test Point

".'.~
'" II~;',~ '"
10 k

-=-

=

+5V

+5V

LED 1
(Hook Status)

=

I

I
+5V

Reed
Relay

10 k

10 k

2N1B004

FIGURE 1

Ring

1:1

at a constant interval, starting at the posItive peak (see
Figure 3). Sampling is continued until the next positive peak
is encountered. There is, of course, some quantization error
associated with this next found peak. If this group of samples
were to be continuously cycled, a frequency error would
result.

1 Pulse

the OTMF digit (see Table 1) is resident in the accumulator.
Note that interrupts cannot be tolerated by this routine.
The first task of this routine is to convert the digit into the
table start addresses for the high and low tones. This routine
requires that the tables be resident in page 0 ROM to allow
use of indexed addressing with 0 offset. The structure chosen
for the tables puts the high group tones in the right nibble
and the low group tones in the left nibble. Because the tables
are all of different lengths, the table end is marked by an entry of SF. In defiance of Murphy's Law, the OTMF tables fit
exactly into page 0 ROM.
Generation of the tones involves cycling around a loop
which plucks a 3-bit low tone sample and adds it to the 3-bit
high tone sample. The 4-bit sum is then output to a Of A converter. If the end of the table marker is encountered for
either sample, the pointer must be reset to the table start.
This loop also keeps track of the duration of the tone burst
by counting loops in TIMEH and TIMEL.
Notice that every program path through the loop takes a
constant time (122 microseconds). The actual sequence of
program development was to first write the loop, determine
the execution time, and then, with the sample interval defined, generate the tone tables.
The 4-bit Of A converter is economically implemented with
standard 5070 resistors (60 kilohms = 30 kilohms + 30
kilohms). Port B was used because of its slightly superior
high output voltage drive. It is still necessary to supplement
the high drive with pull-up resistors.
One unfortunate by-product of this tone generation technique is the production of subharmonics (and, of course,
harmonics). This necessitates the use of an active bandpass
filter. This filter consists of separate high pass and low pass
sections. The filter response is shown in Figure 4.
The output level to the telephone line is adjusted with a
47().ohm resistor in series with the line transformer primary.
This also provides the RX point, where received audio can be
obtained for duplex communication.
Using the BASIC software at the end of this application
note, the generation of custom tone groups is readily accomplished. Single tone generation is also possible by using
the table entry TNOFF at the end of the given OTMF tables.
This allows the muting of either the high or low
group tones.

Digit Dialed = 3

FIGURE 2 - TIming for Rotary Pulse Dialing

To cure this, continue sampling until the next peak is encountered and determine if the resultant frequency error falls
within acceptable limits. Figure 3 is actually the output of a
program written in BASIC for the EXORciser. This listing is
included at the end of this application note. This program is
used to design the look-up table for incorporation into the
M6805 program according to the error rates acceptable in the
end equipment.
This program prompts the user for the sample interval and
the frequency of the tone which is to be generated. Sampling
of the tone is thus automated and after a peak is encountered, the cumulative frequency error is calculated and
displayed along with the sample count. If the user is satisfied
with the percentage error, a table of the samples is generated.
If the error is still unacceptable, the program continues
sampling until the next peak is encountered. Note that the
samples have all been "dc shifted".
This program was used to generate the look-up tables for
all the tones given in Table 1 with a criteria of 1070 maximum
frequency error.
The subroutine OTONE actually operates on these tables
to generate the OTMF tone pairs. The routine is entered with

EXORciser is a registered trademark of Motorola Inc.

307

7·

:01.

_

6 :
5
...
4 :

...

"''''

'"
'"

...

...

'"
...

...

'"

3'"
:2
......
1

...
...

...

...

'"
'"

...
...

'"

...

...

II.::::::1:::::::::::::::::::::::::::::::::::::::::::::
-

HORIZONTAL = 122.0f/J0 uSEC
;: 697.011111 Hz
FREQUENCY
ERROR
= 0.800 "
NO. SAMPLES = 35.000
3.000
NO. CYCLES
SAMPLE 2 = 5
SAMPLE 1 = 7
SAMPLE 4
2
SAMPLE 3
3
SAMPLE 6 = II
II
SAMPLE 5
SAMPLE 8
2
SAMPLE 7 = 1
SAMPLE 10 = 6
4
SAMPLE 9
SAMPLE 12 = 7
SAMPLE 11 = 7
SAMPLE 14
5
SAMPLE 13 = 6
1
SAMPLE 16
3
SAMPLE 15
0
SAMPLE 18
SAMPLE 17
0
SAMPLE 20
2
SAMPLE 19
1
SAMPLE 22 = 6
SAMPLE 21 = 4
SAMPLE 24
7
7
SAMPLE 23
SAMPLE 26 = 4
SAMPLE 25 = 6
SAMPLE 28
1
SAMPLE 27
3
SAMPLE 30
0
SAMPLE 29 =0
SAMPLE 32 = 3
1
SAMPLE 31
SAMPLE 34
6
SAMPLE 33 = 5
SAMPLE 35 = 7

.

FIGURE 3 - Sine Wave Sampling

+2
0

-2

)

-4
-6

iii

-8

illc:

-10

:!2

.
0

-12

lit
a: -14

-16
-18

~""

..........

low Tone Group
Hi h Tone Group I

I

"'\.'\.
\

I

I
I

,
i\

\

-20

\

-22
-24

\

-26
100

1000
Frequency (Hzl

AGURE 4 - Cumulative High·Pass. Low·P_. and Un. Traneformer R8lPClll1e

308

10.000

"'AGE

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O:A~ER

21001215

*******Jt:**:****..T:*****'+:IT:~;~***************";-:****

00006

*'*'
**'
OIAi..:::rt DE:i"iO,'\,STRATlO." P~CGRA.,,:
*'
MCS8705P3 VERSION
*'
~OBER7 FISC;;ER
,.,
*' MOTOROLA SE"!ICONDUCTORP~ODUCTS INC.
'"
*'
~ORONTO. CANADA
*'
11/23/83
*'**********a+:******************~;·H+a.:************

00007
00008
00009
1210010
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1210013

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1210016
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12101218
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121001
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A ,': ·"lE'- RMB
A STPR"·~i-· R"IB
A START:.. ~;"!B
A TONEh R:1B

A TONEL R"'oB
A SCRTCH R:V:B
A LSTKEY ~MB

309

$40

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AN974
MC68HC11 Floating-Point Package
The mantissa consists of three bytes (24 bits) and is
used to hold both the integer and fractional portion of
the floating-point number. The mantissa is always assumed to be "normalized" (i.e., most-significant bit of
the most-significant byte a one). A 24-bit mantissa will
provide slightly more than seven decim~1 digits of precision.
A separate byte is used to indicate the sign of the mantissa rather than keeping it in twos complement form so
that unsigned arithmetic operations may be used when
manipulating the mantissa. A positive mantissa is indicated by this byte being equal to zero ($00). A negative
mantissa is indicated by this byte beil)g equal to minus
one ($FF).
82 C90FDB 00
+3.1415927
FPACC1
-3.1415927
82 C90FDB FF
FPACC2

INTRODUCTION
The MC68HC11 is a very powerful and capable singlechip microcomputer. Its concise instruction set combined
with six powerful addressing modes, true bit manipulation, 16-bit arithmetic operations and a second 16-bit index register make it ideal for control applica,tions requiring
both high-speed 110 and high-speed calculations.
While most applications can be implemented by using
the 16-bit integer precision of the MC68HC11, certain applications or algorithms may be difficult or impossible to
implement without floating-point math. The goal in writing the MC68HC11 floating-point package was to provide
a fast, flexible way to do floating-point math for just such
applications.
The HC11 floating-point package (HC11FP) itnplements
more than just the four basic math functions (add, subtract, multiply, and divide); it also provides routines to
convert from ASCII to floating point and from floating
point to ASCII. For those applications that require it, the
three basic trig functions SINe, COSine, and TANgent are
provided along with some trig utility functions for converting to and from both radians and degrees. The square
root function is also included.

MEMORY FORMAT

For those applications that can benefit by using both
integer and floating-point operations, there are routines
to convert to and from integer and floating-point format.
The entire floating-point package requires just a little
over 2k bytes of memory and only requires ten bytes of
page-zero RAM in addition to stack RAM. All temporary
variables needed by the floating-point routines, reside on
the stack. This feature makes the routines completely reentrant as long as the ten bytes of page zero RAM are
saved before using any of the routines. This will allow
both interrupt routines an.d main line programs to use
the"floating-point package without interfering with one
another.

FLOATING·POINT FORMAT
FLOAnNG·POINT ACCUMULATOR FORMAT
The ten bytes of page-zero RAM are used for two software floating-point accumulators FPACC1 and FPACC2.
Each five-byte accumulator consists of a one-byte exponent, a three-byte mantissa, and one byte that is used
to indicate the mantissa sign.
The exponent byte is used to indicate the position of
the binary point and is biased by decimal 128 ($80) to
make floating-point comparisons easier. This one-byte
exponent gives a dynamic range of about 1 x 10 ± 38.

323

The way that floating-point numbers are stored in
memory or the "memory format" of a floating-point number is slightly different than its floating-point accumulator
format. In order to save memory, floating-point numbers
are stored in memory in a format called "hidden bit normalized form".
In this format, the number is stored into four consecutive bytes with the exponent residing at the lowest address. The mantissa is stored in the next three consecutive
bytes with the most-significant byte stored in the lowest
address. Since the most-significant bit of the mantissa in
a normalized floating-point number is always a one, this
bit can be used to store the sign of the mantissa. This
results in positive numbers having the most-significant
bit of the mantissa cleared (zero) and negative numbers
having their most-significant bit set (one). An example
follows:
82 490FDB
+3.1415927
-3.1415927
82 C90FDS
There are four routines that can be used to save and
load the floating-point accumulators and at the same time
convert between the floating-point accumulator and
memory format. These routines are discussed in detail
in FLOATING·POINT ROUTINES.

ERRORS
There are seven error conditions that may be returned
by the He11 floating-point package. When an error occurs, the condition is indicated to the calling program by
setting the carry bit in the condition code register and
returning an error code in the A-accumulator. The error
codes and their meanings are explained below.

FLOATING-POINT ROUTINES
Meaning

Error #
1

Format Error in ASCII to Floating-Point Conversion

2

Floating-Point Overflow

3

floating-Point Underflow

4

Division by Zero (0)

5

Floating-Point Number too Large or Small to
Convert to Inleger

6

Square Rool of a Negative Number

7

TAN of

,,:1

{90 I

NOTE
None of the routines check for valid floating-point
numbers in either fPACC1 or fPACC2. Having illegal
floating-point values in the floating-point. accumulators will produce unpredictable results.

The following paragraphs provide a description of each
routine in the floating-point package. The information
provided indudes the subroutine name, operation performed, subroutine size, stack space required, other subroutines that are caJled, input, output, and possible error
conditions.
The Stack Space required by the subroutine includes
not only that required for the particular routines local
variables, but also stack space that is used bV any other
subroutines that are called including return addresses.
Note that the trig functions require a good deaf of stack
space.
Since some applications may not require all the routines provided in the floating-point package, the description of each routine includes the names of other
subroutines that it calls. This makes it easy to determine
exactly which subroutines are required for a particular
function.

ASCII-TO-FLOATING-POINT CONVERSION
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:
Notes:

ASCFLT
ASCII (X) • FPACC1
352 Bytes (includes NUMERIC subroutine)
14 Bytes
NUMERIC, FPNORM, FL TMUL, PSHFPAC2, PULFPAC2
X register points to ASCII string to convert.
FPACCI contains the floating-point number.
Floating-point format error may be returned.
This routine converts an ASCII floating-point number to the format required by all of the
floating-point routines. Conversion stops either when a non-decimal character is encountered before the exponent or after one or two exponent digits have been converted. The
input format is very flexible. Some examples are shown below.
20.095
0.125
7.2984E + 10
167.824E5
005.9357E ·7
500

FLOATING-POINT MULTIPLY
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

FLTMUL
FPACCI x FPACC2 • FPACCI
169 Bytes
10 Bytes
PSHFPAC2,PULFPAC2,CHCKO
FPACCI and FPACC2 contain the numbers to be multiplied.
FPACCI contains the product of the two floating-point accumulators. FPACC2 remains
unchanged.
Overflow, Underflow.

324

FLOATING-POINT ADD
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:
Notes:

FLTADD
FPACC1 + FPACC2 • FPACC1
194 Bytes
6 Bytes
PSHFPAC2.PULFPAC2.CHCKO
FPACC1 and FPACC2 contain the numbers to be added.
FPACC1 contains the sum of the two numbers. FPACC2 remains unchanged.
Overflow. Underflow.
The floating-point add routine performs full signed addition. Both floating-point accumulators may have ,nantissas with the same or different sign.

FLOATING-POINT SUBTRACT
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:
Notes:

FLTSUB
FPACC1 - FPACC2 • FPACC1
12 Bytes
8 Bytes
FLTADD
FPACC1 and FPACC2 contain the numbers to be subtracted.
FPACC1 contains the difference of the two numbers (FPACC1-FPACC21. FPACC2 remains
unchanged.
Overflow. Underflow.
Since FLTADD performs full signed addition. the floating-point subtract routine inverts the
sign byte of FPACC2. calls FLTADD. and then changes the sign of FPACC2 back to what it
was originally.

FLOATING-POINT DIVIDE
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

FLTDIV
FPACC1 .;- FPACC2 • FPACC1
209 Bytes
11 Bytes
PSHFPAC2. PULFPAC2
FPACC1 and FPACC2 contain the divisor and dividend respectively.
FPACC1 contains the quotient. FPACC2 remains unchanged.
Divide by zero. Overflow. Underflow

FLOATING-POINT-TO-ASCII CONVERSION
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:

Error Conditions:

FLTASC
. FPACC1 • (XI
370 Bytes
28 Bytes
FLTMUL. FLTCMP, PSHFPAC2. PULFPAC2
FPACC1 contains the number to be converted to an ASCII string. The index register X points
to a 14 byte string buffer.
The buffer pointed to by the X index register contains an ASCII string that represents the
number in FPACC1. The string is terminated with a zero (01 byte and the X register points
to the start of the string.
None

325

FLOATING POINT COMPARE
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

FLTCMP
FPACC1 - FPACC2
42 Bytes
None
None
FPACC1 and FPACC2 contain the numbers to be compared.
Condition codes are properly set so that all branch instructions may be used to alter program
flow. FPACC1 and FPACC2 remain unchanged.
None

UNSIGNED INTEGER TO FLOATING POINT
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

UINT2FLT
(16-bit unsigned integer). FPACC1
18 Bytes
6 Bytes
FPNORM. CHCKO
The lower 16-bits of the FPACC1 mantissa contain an unsigned 16-bit integer.
FPACC1 contains the floating·point representation of the 16-bit unsigned integer.
None

SIGNED INTEGER TO FLOATING POINT
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

SINT2FLT
116-bit signed integer}. FPACC1
24 Bytes
7 Bytes
UINT2FLT
The lower 16·bits of the FPACC1 mantissa contain a Signed 16-bit integer.
FPACC1 contains the floating-point representation of the 16-bit signed integer.
None

FLOATING POINT TO INTEGER
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:
Notes:

FLT21NT
FPACC1 • 116-bit signed or unsigned integer)
74 Bytes
2 Bytes
CHCKO
FPACC1 may contain a floating-point number in the range 65535",FPACC1;;. - 32767.
The lower 16·bits of the FPACC1 mantissa will contain a 16·bit signed or unsigned number.
None
If the floating-point number in FPACCl is positive. it will be converted to an unsigned
integer. If the number is negative it will be converted to a Signed twos complement integer.
This type of conversion will allow 16-bit addresses to be represented as positive numbers
in floating-point format. Any fractional part of the floating-point number is discarded.

TRANSFER FPACCl TO FPACC2
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

TFRlT02
FPACC1 • FPACC2
13 Bytes
o Bytes
None
FPACC1 contains a floating-point number.
FPACC2 contains the same number as FPACC1.
None

326

To reduce the number of factors in the Taylor expansion series all angles are reduced to fall between 00 and
450 by the ANGRED subroutine. This subroutine returns
the reduced angle in FPACCl along with the quad number
that the original angle was in. and a flag that tells the
calling routine whether it actually needs to calculate the
sine or the cosine of the reduced angle to obtain the
proper answer.

FLOATING·POINT fUNCTIONS
The following paragraphs describe the supplied floating-point functions. returned results. and possible error
conditions. Note that even though the Taylor series which
is used to calculate the trig functions requires that the
input angle be expressed in radians; less precision is lost
through angle reduction if the angle being reduced is
expressed in degrees. Once the angle is reduced. the
DEG2RAD subroutine is called to convert the angle to
radians.

SQUARE ROOT
Subroutine Name:
Operation:
Size:
Stack Space:
Calls:
Input:
Output:
Error Conditions:

FLTSOR
\  FPACC2?

0485 C26A 2A OF

BPL

FLTADD3

0486 C26C 40

NEGA

0480 C260 20 E5
0481 C262 96 00

FLT ADD2

MOVE LOWER 16 BITS OF MANTISSA.
MOVE FPACC2 MANTISSA SIGN INTO FPACC1.

YES. GO CHECK RANGE.
NO. FPACCI < FPACC2. MAKE DIFFERENCE POSITIVE.

0487 C260 81 17

CMPA

#23

ARE THE NUMBERS UITHIN RANGE?

0488 C26F 22 E3

BHI

FL TADD4

NO. FPACC2 IS LARGER. GO MOVE IT INTO FPACCI.

0489 C271 16

TAB

0490 C272 DB 00

ADDB

FPACC1EX

0491 C274 07 00

STAB

FPACC1EX

SAVE THE RESULT.

0492 C276 CE 00 01

LOX

#FPACCIMN

POINT TO FPACCI MANTISSA.
GO DENORMALI ZE FPACCI FOR THE ADD.

0493 C279 20 07

PUT DIFFERENCE IN B.
CORRECT FPACCI EXPONENT.

BRA

FL TADD5

CMPA

#23

FPACCI > FPACC2. ARE THE NUMBERS UITHIN RANGE?

BHI

FL TADD6

NO. ANSWER ALREADY IN FPACCI. JUST RETURN.

LOX

#FPACC2MN

POINT TO THE MANTISSA TO DENORMALIZE.

LSR

O,X

SHIFT THE FIRST BYTE OF THE MANTISSA.

I,X

0499 C286 66 02

RDR
RDR

THE SECOND.
AND THE THIRD.

0500 C288 4A

DECA

0501 C289 26 F7

BNE

FLTADD5

LDAA

MANTSGNI

GET FPACCI MANTISSA SIGN.

0503 C280 91 09

CMPA

MANTSGN2

ARE THE SIGNS THE SAME?

0494 C27B 81 17

FLTADD3

0495 C270 22 C8
0496 C27F CE 00 06
0497 C282 64 00

Fl TADD5

0498 C284 66 01

0502 C28B 96 04

Fl TADD7

2,X

DONE YET?
NO. KEEP SHIFTING.

0504 C28F 27 4B

BEQ

FL TADDll

YES. JUST GO ADD THE TWO MANTISSAS.

0505 C291 70 00 04

TST

MANTSGNI

NO. IS FPACCI THE NEGATIVE NUMBER?
NO. GO DO FPACC1·FPACC2.

0506 C294 2A 14

BPL

FL TADD8

0507 C296 DE 06

LOX

FPACC2MN

0508 C298 3C

PSHX

0509 C299 DE 01

LOX

FPACCIMN

GET PART OF FPACCI.

0510 C29B OF 06

STX

FPACC2MN

PUT IT IN FPACC2.

0511 C290 38

PULX

0512 C29E OF 01

STX

YES. EXCHANGE FPACCI & FPACC2 BEFORE THE SUB.
SAVE IT.

GET SAVED PORTION OF FPACC2
FPACCIMN

338

PUT IT IN FPACC1.

•

0513 C2AO DE 08
0514 C2A2 3C

PSHX

0515 C2A3 DE 03

LOX

FPACC1MN+2

GET LOIIER 8 BITS & SIGN OF FPACe1.

0516 C2A5 OF 08

STX

FPACC2MN+2

PUT IT IN FPACC2.

0517 C2A7 38

PULX

0518 C2A8 OF 03

STX

FPACC1MN+2

PUT IT IN FPACC1.

0519 e2M DC 02

LOX

GET LOIIER 8 BITS & SIGN OF FPACC2.
SAVE IT.

GET SAVED PART OF FPACC2.

LDD

FPACC1MN+1

GET LOI/ER 16 BITS OF FPACC1.

0520 C2AC 93 07

SUBD

FPACC2MN+1

SUBTRACT LOI/ER 16 BITS OF FPACC2.

0521 C2AE DO 02

STO

FPACC1MN+1

SAVE RESULT.

0522 C2BO 96 01

LOAA

FPACC1MN

GET HIGH 8 BITS OF FPACC1 MANTISSA.

0523 C2B2 92 06

SBCA

FPACC2MN

SUBTRACT HIGH 8 BITS OF FPACC2.

0524 C2B4 97 01

STAA

FPACC1MN

SAVE THE RESULT. IS THE RESULT NEGATIVE?

0525 e2B6 24 16

BCC

FLTAOD9

NO. GO NORMALIZE THE RESULT.

0526 e2B8 96 01

LOAA

FPACC1MN

YES. NEGATE THE MANTISSA.

0527 e2BA 43
0528 C2BB 36

COMA
PSHA

0529 C2Be DC 02

LOO

0530 C2BE 53

COMB

0531 C2BF 43

COMA

0532 C2eo e3 00 01

AOOO

#1

FORM THE T\JO'S COMPLEMENT.

0533 C2C3 DO 02

STO

FPACC1MN+'

SAVE THE RESULT.

0534 C2C5 32
0535 e2C6 89" 00

PULA
AOCA

#0

ADD IN POSS I BLE CARRY.

0536 e2e8 97 01

STAA

FPACC1MN

SAVE RESULT.

0537 e2CA 86 FF

LOAA

ilSFF

SHOll THAT FPACC1 IS NEGATIVE.

0538 e2ec 97 04

STAA

MANTSGN1

0539 e2CE BO e1 61

FLTAD08

FPACC2MN+2

GET LOIIER 16 BITS.
FORM THE ONE'S COMPLEMENT.

GET UPPER 8 BITS BACK.

JSR

FPNORM

GO NORMALI ZE THE RESULT.

BCC

FL TADD12

EVERYTHING'S OK SO RETURN.

0541 C203 86 03

LOAA

#UNFERR

0542 e205 00

SEC

UNDERFLOII OCCURED OUR I NG NORMALlIAT I ON.
FLAG ERROR.

0540 e201 24 06

FLTAD09

SAVE THE RESULT.
FPACC1MN+1

0543 e206 7E C2 48

JMP

FL TADDlO

RETURN.

0544 C209 7E e2 47

FLTADD12 JMP

FL TADD6

CAN'T BRANCH THAT FAR FROM HERE.

FLTADD11 LDD

FPACC1MN+1

GET LOI/ER 16 BITS OF FPACC1.

0545
0546 C20C DC 02
0547 C20E 03 07

ADDD

FPACC2MN+1

ADO IT TO THE LOI/ER 16 BITS OF FPACC2.

0548 C2EO DO 02

STD

FPACC1MN+1

SAVE RESULT IN FPACC1.

0549 C2E2 96 01

LDAA

FPACC1MN

GET UPPER 8 BITS OF FPACC1.

0550 C2E4 99 06

ADCA

FPACC2MN

ADD IT (IiITH CARRY) TO UPPER 8 BITS OF FPACC2.

0551 C2E6 97 01

STM

FPACC1MN

SAVE THE RESULT.

0552 e2E8 24 EF

BCC

FLTADD12

NO OVEIHLOII SO JUST RETURN.

0553 C2EA 76 00 01

ROR

FPACC1MN

PUT THE CARRY INTO THE MANTISSA.

0554 C2ED 76 00 02

ROR

FPACC1MN+1

PROPIGATE THROUGH MANTISSA.

FPACC1MN+2

0555 C2FO 76 00 03

ROR

0556 C2F3 7C 00 00

INC

FPACC1EX

UP THE MANT I SSA BY 1.

0557 C2F6 26 E1

BNE

FLTADD12

EVERYTHING'S OK JUST RETURN.

0558 C2F8 86 02

LDAA

#OVFERR

RESULT liAS TOO LARGE. OVERFLOII.

0559 C2FA 00

SEC

0560 C2FB 7E C2 48

JMP

FLTADD10

RETURN.

FLAG ERROR.

0561
0562
0563

339

0564

Fl TSUB

0565
0566
0567

flOATING POINT SUBTRACT SUBROUTINE

0568
0569

This subroutine performs floating point subtraction ( FPACC1·FPACCZ> ..

0570

by inverting the sign of FPACC2 and then calling FlTADD since
FLTADD performs complete signed addition. Upon returning from
FLTADO the sign' of FPACC2 is again inverted to leave it unchanged
from its original value.

0571
0572
0573
0574
0575

WORSE CASE

= 1062

CYCLES

= 531

0576
0577
0578
0579
0580 C2FE

Fl TSUB

EQU

0581 C2FE SO 03

BSR

fL TSUB1

INVERT SIGN.

0582 C300 BO C2 3C

JSR

Fl TAOO

GO DO FLOATING POINT ADD.
GET FPACC2 MANTISSA SIGN.

0583 C303 96 09

LOAA

MANTSGN2

0584 C305 88 F F

Fl TSUB1

EORA

#SFf

0585 C307 97 09

STAA

MANTSGN2

0586 C309 39

RTS

INVERT THE SIGN.
PUT BACK.
RETURN.

0587
0588
0589

340

uS @ 2MHz

TTL

0590
0591

FLTDIV

•• *• .,. ••••••••••• _••••••• _•••••••••••••••••••••• ,. ••••• -.******** •• ***.********.

0592
0593

FLOATING POINT DIVIDE

0594

This subroutine performs signed floating point divide. The

0595

The divisor (FPACCZ) is left *

0596

operation performed is FPACC1/FPACC2.

0597

unaltered aAd the answer is placed in FPACCL There are several
error conditions that can be returned by this routine. They are:
a) division by zero. b) overflow. c) underflow. As with all
other routines, an error is indicated by the carry being set and
the error code being in the A-reg.

0598
0599
0600
0601
0602

IIORSE CASE = 2911 CYCLES = 1455 uS ~ 2MHz

0603
0604
0605

***.****.***************************************.*** ••• - •••• _._ ••• __ •••••• _•• -

0606
0607
0608 C30A

FLTDIV

EQU

0609 C30A CE 00 05

LOX

#FPACC2EX

POINT TO FPACC2.

0610 C30D BD Cl 80
0611 C310 26 04

JSR
BNE

CHCKO
FLTDIVI

IS THE DIVISOR O?
NO. GO SEE IF THE DIVIDEND IS ZERO.

0612 C312 86 04

LDAA

#DIVOERR

YES. RETURN A DIVIDE BY ZERO ERROR.

0613 C314 00
0614 C315 39

SEC

FLAG ERROR.

RTS

RETURN.

0615 C316 CE 00 00

LOX

#FPACC1EX

0616 C319 BO Cl 80

JSR

CHCKO

IS THE DIVIDEND O?

0617 C31C 26 02

BNE

FLTDIV2

NO. GO PERFORM THE DIVIDE.

0618 C31E DC

CLC

YES. ANSIIER IS ZERO. NO ERRORS.

0619 C31F 39

RTS

RETURN.

0620 C320 BO C8 39

FLTDIVI

FLTDIV2

POINT TO FPACC1.

JSR

PSHFPAC2

SAVE FPACC2.

0621 C323 96 09

LDAA

MANTSGN2

GET FPACC2 MANTI SSA SIGN.

0622 C325 98 04

EORA

MANTSGNl

SET THE SIGN OF THE RESULT.

0623 C327 97 04

STAA

MANTSGNl

SAVE THE RESULT.

0624 C329 CE 00 00

LOX

#D

SET UP 1I0RK SPACE ON THE STACK.

0625 e32C 3C

PSHX

#24

PUT Leep COUNT ON STACK.

0626 e32D 3e

PSHX

0627 C32E 3C

PSHX

0628 C32F 86 18

LDAA

0629 C331 36

PSHA

0630 C332 30

TSX

0631 CH3 DC 01

FPACCIMN

0632 C335 lA 93 06

LDD
CPO

FPACC2MN

COMPARE FPACCI & FPACC2 MANTISSAS.
ARE THE UPPER 16 BITS THE SAME?

0633 C338 26 04

BNE

FLTOIV3

NO.

0634 C33A 96 03

LDAA

FPACC1MN+2

YES. COMPARE THE LOIIER 8 BITS.

0635 C33C 91 08

CMPA

FPACC2MN+2

0636 CHE 24 10

SET UP POI NTER TO IIORK SPACE.

BHS

FLTDIV4

IS FPACC2 MANTISSA> FPACCI MANTISSA? NO.

0637 C340 7C 00 05

INC

FPACC2EX

ADD 1 TO THE EXPONENT TO KEEP NUMBER THE SAME.

0638
0639 C343 26 19

BNE

FLTDIV14

NO. GO SHIFT THE MANTISSA RIGHT 1 BIT.

LDAA

#DVFERR

YES. GET ERROR CODE.

0640 t345 86 02

FLTDIV3

DID OVERFLOII OCCUR?
FLTDIV8

0641 C347 00
0642 C348 38

FLTDIV6

SEC

FLAG ERROR.

PULX

REMOVE IIORKSPACE FROM STACK.

0643 C349 38

PULX

0644 C34A 38

PULX

0645 C34B 31
0646 C34C BD C8 43

INS
JSR

0647 C34f 39

RTS

PULFPAC2

RESTORE FPACC2.

LDD

FPACC1MN+l

RETURN.
DO AN INITIAL SUBTRACT IF DIVIDEND MANTISSA IS

0649 C352 93 07

SUBD

FPACC2MN+l

GREATER THAN DIVISOR MANTISSA.

0650 C354 DO 02

STD

FPACC1MN+l

0648 C350 DC 02

FLTD I V4

0651 C356 96 01

LDAA

FPACCIMN

0652 C358 92 06

SBCA

FPACC2MN

0653 C3SA 97 01

STAA

FPACCIMN

0654 e3SC 6A 00

DEC

O,X

SUBTRACT 1 FROM THE LOOP COUNT.

341

SHIFT THE DIVISO~ TO THE RIGHT 1 BIT.

0655 C35E 74 00 06

FLTDIV14 LSR

0656 C361 76 00 07

ROR

FPACC2MN+l

FPACC2MN

0657 C364 76 00 08

ROR

FPACC2MN.2

0658 C367 96 00

LDAA

FPACC1EX

GET FPACCl EXPONENT.

0659 C369 D6 OS

LDAB

FPACC2EX

GET FPACC2 EXPONENT.

0660 C368 50

NEGB

0661 C36C 1B

ABA

0662 C36D 2B 06

BMI

ADD THE TWO'S COMPLEMENT TO SET FLAGS PROPERLY.
FLTDIV5

I.F RESULT MINUS CHECK CARRY FOR POSS. OVERFLOW.

0663 C36F 25 06

BCS

FLTDIV7

IF PLUS & CARRY SET All IS OK.

0664 C371 86 03

LDAA

IlUNFERR

IF NOT, UNDERFLOW ERROR.
RETURN WITH ERROR.

0665 C373 20 03

BRA

FLTDIV6

0666 C375 25 CE

FLTDIV5

BCS

FLTDIV8

IF MINUS & CARRY SET OVERFLOW ERROR.

0667 C377 8B 81

FLTDIV7

ADDA

1/$81

ADO BACK BIAS+' (THE '1' COMPENSATES fOR ALGOR.

STAA

FPACC1EX

SAVE RESULT.

lOO

FPACC1MN

SAVE DIVIDEND IN CASE SUBTRACTION DOESN'T GO.

0670 C37D EO 04

STD

4,X

0671 C37F 96 03

LDAA

FPACC1MN+2

0672 C381 A7 06

STAA

6, X

0673 C3E3 DC 02

LOD

FPACC1MN+'

0674 C385 93 07

sueD

FPACC2~N+

0675 087 DO 02

STD

FPACC1M~+'

SAvE RESULT.

0676 C389 96 01

LOAA

FPACC1MN

GET riIGH 8 BITS.

0677 :38B 92 06

SBCA

FPACC2MN

0668 C379 97 00
0669 C37B DC 01

FL TDIV9

GET LOWER 16 BITS FOR St;BTRACTION.

1

0678 C38D 97 01

STAA

FPACC1MN

D679 C38F 2A 08

BPL

FLTDIV10

SUBTRACTION WENT OK. GO CO SHIFTS.

0680 C391 EC D4

LDD

4,X

RESTORE OLD D I VIDENO.

0681 C393 DO Dl

STD

FPACC1MN

D682 0395 A6 D6

LDAA

6,X

Q683 0397 97 03
0684 0399 69 03

STAA
FUD I ',111) ROL

FPACC1MN+2

3,X

ROTATE CARRY INTO QUOTIENT.

ROL

2,x

0686 O39D 69 01
']687 :39~ 78 00 C,3

ROL

1,X

LSL

FPACC1MN+2

0688 C3A2 79 00 S2

ROL

FPACC1MN+'

0685 O39B 69 02

SHIFT DIVIDEND TO LEFT FOR NEXT SUBTRACT.

':.689 C3A5 79 C'O . . ·1

ROL

FPACC1MN

C69:, C3A8 6A OJ

DEC

O,X

DONE YE T?

CJ691 C3AA 26 CF

BNE

FL TO !v9

NO. KEEP GOING.

1,X

RESUL T MUST BE COMPLEMENTED.

:::;692 OAC 63 01

C693 C3AE 63 02

COM

2.x

D6C;4 :3BO 63 03

COM

3, x

0695 C3B2 DC 02

LDD

FPACC1MN+'

DO 1 MORE SUBTRACT FOR ROUN:JING.

')696 (3B4 93 07

SUBD

FPACC2MN+'

OONtT NEED TO SA'JE THE RES01...T,

0697 C3B6 96 01

LDAA

FPPoCC1MN

0698 O3B8 92 06

seCA

FPACC2MN

0699 USJl EC 02

LDD

2, X

C700 03BC 24 03

BCC

FL TOIV1

0701 USE

ac

CJ7C2 C38F 20 03

1

IF iT DIDNT CO RESulT 01( AS IS.
CLEAR THE CARRY.

CLC
BRA

NO NEED TO SA'JE THE RES'.... ,-;.

GET LOW 16 BI TS.

FLTDIV13

07C3 C3C' C3 0']

FLTDIV11 ACDD

.,

ROUND UP Bl' 1.

0704 O3C4 DO 02

FLT:JIV13 STD

GO SAVE THE NUMBER.

FPACC1MN+l

puT IT IN FPACC1.

n705 03C6 A6 01

LDAA

1, X

GET HIGH 8 BITS.

0706 (3(8 e9 OC

ADCA

'0

C707 c3eA 97 01

STAA

FPACC1MN

OlG8 (3eC 24 09

BCC

FL TDI"2

! F CARRY CLEAR ANS\.JER OK.

0709 UCE 76 00 C1

ROR

FPACC ~MN

IF NOT OVERFLOW. ROTATE CARRY IN.

0710 C301 76 00 02

ROR

FPACC1MN+l

0711 C3D4 76 00 03

ROR

FPACC1MN+2

0712 C3D7 DC
0713 C3D8 7E 03 48

FLTOiV12 ClC

JMP

SAvE RESULT.

NO ERRORS.

Fl TOIV6

0714
0715
0716

342

RETURN.

0717

TTL
FL TASC
• ______ • __
•• _______
•• _____ ••• _____ ._._._ ••• _._ ••••• ____ ", .. e ___ ",_. _____________ _

0718
0719
0720

FLOATING POINT TO ASCII CONVERSION SUBROUTINE

0721

This subroutine performs floating point to ASCI I conversion of
the nl.Mnber in FPACC1. The asci i string is placed in a buffer
pointed to by the )( index register. The buffer must be at least
14 bytes long to contain the ASCII conversion. The resulting
ASCII string is terminated by a zero (0) byte. Upon exit the
X Index register will be pointing to the first character of the
string. FPACCl and FPACC2 wi It remain unchanged.

0722
0723
0724
0725
0726
0727
0728
0729
0730
0731
0732
0733 e30B

FLTASC

EOU
BUF~ER.

0734 C3DB 3C

PSHX

0735 C3DC CE 00 00

LOX

'FPACC1EX

0736 ClDF BD Cl 80

JSR

CHCKO

IS FPACCl O?

0737 C3E2 26 07

BNE

FL lASCl

NO. GO CONVERT THE NUMBER.

0738 C3E4 38

PULX

0739 C3E5 CC 30 00

LOO

"3000

GET ASCII CHARACTER + TERMINATING BYTE.

0740 C3E8 ED 00

STD

O,X

PUT IT IN THE BUFFER.

0741 C3EA 39

SAVE THE POINTER TO THE STRING

RESTORE POI NTER.

RTS

0742 C3EB DE 00

FLTASCl

0743 C3EO 3C

LOX

POINT TO FPACC1.

RETURN.
FPACC1EX

SAVE FPACC1.

PSHX

0744 C3EE DE 02

LOX

0745 C3FO 3C

PSHX

0746 C3Fl 96 04

LOAA

0747 C3F3 36

PSHA

FPACC1MN+1
MANTSGNl

0748 e3F4 BO e8 39

JSR

PSHfPAC2

0749 C3FT CE 00 00

LOX

.0

SAVE FPACC2.

0750 C3FA 3C

PSHX

0751 C3FB 3C

PSHX

ALLOCATE LOCALS.

0752 C3FC 3C

PSHX

SAVE SPACE FOR STR! NG BUffER POI NTER.

0753 C3FD 18 30

TSY

POINT TO LOCALS.

0754 C3FF CD EE OF

LOX

15, Y

lifT POI NTER FROM STACX.

0755 C402 86 20

I.DAA

PUT A SPACE IN THE BUFFER IF NUMBER NOT NEGATIVE.

TST

"20
MANTSGNl

0757 C407 27 05

BEQ

FLTASC2

NO. GO PUT SPACE.

0758 C~09 7F 00 04

CLR

MANTSGNl

MAKE NUMBER POSITIVE FOR REST OF CONVERSION.

LDAA

#'

YES. PUT MINUS SIGN IN BUFFER.

STAA

O,X

0756 C404

0759 C40C

TO 00 04

86 20

0760 C40E A7 00

FLTASC2

0761 C410 08

POINT TO NEXT LOCATION.

INX

EF 00

IS IT NEGATIVE?

STX

0, Y

SAVE POINTER.

LOX

#.9999999

POINT TO CONSTANT 9999999.

0764 C417 BD C8 66

JSR

GETFPAC2

GET INTO FPACC2.

0765 C41A BO C5 40

JSR

FLTCMP

COMPARE THE NUMBERS. IS FPACCl > 9999999 7

0766 C410 22 19

SHI

FL TASC3

YES. GO OIVIDE FPACCl BY 10.

0767 C41F CE C5 41

LOX

'P9999999

POINT TO CONSTANT 999999.9

0768 C422 BD C8 66

JSR

GET.FPAC2

MOVE

0769 C42S BD C5 40

JSR

FLTCMP

COMPARE NUMBERS. IS FPACCl > 999999.9?

0770 C428· 22 16

BHI

FLTASC4

YES. GO CONTINUE THE CONVERSION.

0771 C42A 18 6A 02

OEC

2, Y

DECREMENT THE MUL T./DIV. COUNT.

LOX

#CONST10

NO. MULTiPLY BY 10. POINT TO CONSTANT.

JSR

GETFPAC2

MOVE IT INTO FPACC2.

JSR

flTMUL

0762 C411 CD

0763 C414 CE C5 45

fL IASCS

0772 C42D CE Cl 8F
0773 C430 BO C8 66

fLTASC6

0774 C433 BD Cl 93

IT INTO FPACC2.

GO DO COMPARE AGAIN.

SRA

FLTASCS

INC

Z, Y

INCREMENT THE HULT./DIV. COUNT.

LOX

NCONSIPI

POINT TO CONSTANT ".'11.

BRA

F.lTASC6

GO DIVIDE FPACCl BY 10.

LOX

'CONSTP5

POINT TO CONSTANT Of u.5".

0780 C443 Bo C8 66

JSR

GETFPAC2

MOVE

0781 C446 Bo C2 3C

JSR

fL TAOO

AOO .5 TO NUMBER IN FPACCl TO ROUND IT.

0775 C436 20 DC
0.776 C438 18 6C 02

FLTASC3

0777 C43B CE C1 8B
0778 C43E 20 FO
0779 C440 CE C5 49

FLTASC4

343

IT INTO FPACC2.

0782 C449 06 00

LOl.l

FI'ACCIEX

GET fPACCl EXPONENT.

0783
0784

C448 CO 81

SUB8

11181

c4t.o

NEGI

TAKE· OUT 81AS " .
MAKE IT NEGATIVE.

AOOB

'23

BRA

fLTASC17

ADD IN THE NUMBER OF IWITISSA BITS .,.
GO CHECK TO SEE If WE NEED TO SHIFT AT ALl.

LSR

FPACCIMN

SHIFT MANTISSA TO THE RIGHT BY THE RESULT (MAKE

ROR

FPACC1MN+'

THE NUMBER AN INTEGER).

ROR

110. KEEP GOING.

50

0785 C44E CB 17
D786 C450 20

OA

0787 C452 74 00 01

FLTASC7

0788 C455 76 00 02

0792 C45E 86 01

LDAA

0793 C460 18 1.7 03

SfAI.

.,
3,Y

INITIALIZE IT.

D2

LOM

2,Y

GET DECIMAL eXPONENT.

ADD TilE NUMBER OF DECIMAL +1 TO THE EXPONENT.

0789 C458 76

110

03

0790 C458 SA

DEca

D791 C45C 26 F4

0794 C463 18 1.6

FLTASC17 BHE

0795 C466 8B 08

FPACC1MN+2
DONE SHifTING?

FLTASC7

GET INITIAL VALUE OF "DIGITS AFTER D.P." COUNT •

ADDA

18

0797 C468 28 OA

8MI

fLTASCB

Yes. MUST Ie REPRESENTED IN SCIENTIFIC NOTATION.

0798

eMPA

18

WAS THE ORIGINAL NIMBER < I?

0799 C46C 24 06

BlIS

fUASCS

0800 C46E 41.

DECA

0801 C46F 18 A7 03

STM

3, T

MAKE THE DECIMAL EXPONENT THE DIGIT COUNT BEFORE

LOA"
suaA

'2

SETUP TO ZERO THE DECIMAL EXPONENT.

'2

SUBTRACT 2 fROM THE DECIMAL EXPONENT.

0805 C476 18 1.7 02

STM

2,Y

SAVE THE DECIMAL eXPONENT.

0806 C479 18 60 03

TST

3,Y

DOES THE NUMBER HAVE AN INTEGER PART? (EXP • • 0)

0807 C47C 2E 15

BGT

0808 C47E 86 2E

lDM

0809 C480 CO EE 00
0810 C483 A7 00

0796

liAS THE ORIGINAL NUMBER. 9999999?
C46A 81 08

YES. MUST IE REPRESENTED IN SCIENTIFIC NOTATION.
NO. UBER CAN 8E REPRESENTED IN 7 DIGITS.

0802

THE DECIMAL POllY.

0803 C4n

86 02

0804 C474 80 02

FLTASC8

flTASC9

YES. GO PUT IT OUT. 9

tDX

".

O,Y

GET POINTER TO BUffER.

SlM

O,X

PUT THE DECIMAL POINT IN THE BUffER.

NO. GET DECIMAL POINT.

0811 C485 08

INX

0812 C486 18 60 03

TST

3,Y

POINT TO NEXT BUfFER lOCATION.
IS THE DIGIT COUNT Till EXPONENT =o?

0813 C489 27 05

BEQ

fLTASC18

NO. NUMBER IS <.1

30

LOM

#'0

YES. FORMAT NUMBER AS .OXXXXXXX

0815 C480 1.7 00

STM

D,X

PUT THE 0 IN THE BUFFU.

0814 C48B 86
0816 C48F 08

INX

POINT TO THE NEXT LOCATION.

0817 C490 CO Ef 00

HTASC!8 SlX

O,T

SAVE NEW POINTER VALUE.

0818 C493 CE C5 2C

fLTASC9

IDJ:CDIG

POIlIT TO THE TABU Of DECIMAL DIGITS.

LOX

0819 C496 86 07

LDAA

0820 C498 18 1.7 05

STM

'75, Y

INITIALIZe THE THE MaER Of DIGITS· COUNT.

0821 C498 18 6f 04

fl TASC10 ClR

4,Y

CLEAR THE DECIMAL DIGIT ACCUMULATOR.

0822 C49£ DC 02

fl lASCH LOO

fPACC1MN+l

GET LOWER 16 BITS Of MANTISSA.

0823

1.3

SU80

l,X

SUBTRACT LOWER 16 BITS OF CONSTANT.

0824 (41.2 00 02

STD

fPACC1MN+l

SAVE RESULT.

0825

C4AO

01

C4A4 96 01

LUM

fPACC1MN

GET UPPER 8 BITS.

0826 C4A6 1.2 00

SBCA

O,X

SUBTRACT UPPU II ·BITS.

0827

fPACCIMN

SAVE RESULT. UNDERFLOW?

0828 C4M 25 05

STA"
BCS

fLTASC12

0829 C4AC 18 6C 04

INC

4,Y

YES. GO ADD DECIMAL HUMBeR BACK IN.
_
1 TO DECIMAL NUMBER.

C4AS 97

0I

0830 C4AF 20 EO

SRA

0831 C411 DC 02

fL lASC12 Loo

fLTASC11

TRY ANOTHER SUBTRACTlai.

FPACC1MH+1

-GET fPACCl MANTISSA lOW 16 BITS.

0832 C483 E3 01

_0

I,X

ADO 1.011 16 IITS BACK IN.

0833 C485 00 02

STO

FPAC~IMN"

SAVE THE RESULT.

0834 C4a7 96 01

lIlAA

FPACCIMN

0835 C4B9 1.9 00

ADCA

O,X

GET HIGH 8 BITS.

0836 C48B 97 01

STM

fPAtC1MN

SAVE RESULT.

0837 C480 Ie A6 04

LOM

4,1
1/S3D

GET OIGIT.

.ADD IN HIGH 8 BITS Of CONSTANT.

MAKE IT ASCII.

0838 C4CO 88 30

ADDA

0839 C4C2 3C

PSNX

0840 C4C3 COEE 00

LOX

0841 C4C6 1.7 00
0842 C4C8 08

STAll
IIIl!

0843 C4C9 186A 03

DEC

3,'

SHOULD

0844 C4CC 26 05

SHE

FLTASC16

110. CONTINUE ritE CONVERSION.

0845 C4CE 86 2E

0846 C400 A7 00

LOM
S1AA

O,X

PUT IT III TilE auf.fER.

0847 C402 08

IIIX

SAVE POl1l1ER TO cONSTANTS.

O,Y
0,.

GET POINTEIt 10 BUffER.
pur DIGIT

'IN BUffER.

POINt TO NEXT BUffER LOCAHON.

".

\1£ PUT A DECIMAL POUlT IN THE 'BUfHR YET?

YES. GET DECIMAL POINT.
POIU TO TlIE lI£lIT BUffERL-OCATiON.

344

084B C4D3 CD H 00
0849 C4D6 3B
OB50 C4D7 DB
OB51 C4DB DB
OB52 C4D9 DB
OB53 C4DA IB 6A OS
OB54 C4DD 26 BC

Fl TASC16 STX

0855 C4DF CD EE 00

SAVE UPDATED POINTER.

0, Y

PULX

RESTORE POINTER TO CONSTANTS.

INX

POINT TO NEXT CONSTANT.

INX
INX
DEC

5, Y

DONE YET?

BNE

FL TASCI0

NO. CONTINUE CONVERSION OF "MANTlSSA".

LOX

0, Y

YES. POINT TO BUFFER STRING BUFFER.

OB56 C4E2 09
OB57 C4E3 A6 00
OB58 C4E5 81 30

FLTASC13 DEX

lDAA

O,X

GET IT.

CMPA

#$30

liAS IT AN ASC II O?

FLTASC13

0859 C4E7 27 F9

BEQ

OB60 C4E9 OB

INX

POINT TO LAST CHARACTER PUT IN THE BUFFER.

YES. REMOVE TRA I LI NG ZEROS.
POINT TO NEXT AVAILABLE LOCATION IN BUFFER.

0861 C4EA 18 E6 02

LDAB

2, Y

DO liE NEED TO PUT OUT AN EXPONENT?

0862 C4ED 27 2A

BEQ

FL TASC15

NO. WE'RE DONE.

0863 C4EF 86 45

LDAA

#'E

YES. PUT AfI: IE' IN THE BUFFER.

0864 C4F1 A7 00

STAA

O,X

0865 C4F3 08

INX

OB66 C4F4 86 2B

lOAA

#'+

ASSUME EXPONENT IS POS I TI VE.

0867 C4F6 A7 00

SlAA

O,X

PUT PLUS SIGN IN THE BUFFER.

086B C4F8 SO

TSTB

0869 C4F9 2A OS

BPL

FLTASC14

NO. IS'S OK AS IS.

0870 C4FB SO

NEGB

0871 C4FC 86 20

LDAA

#,.

0872 C4FE A7 00

STAA

O,X

OB73 C500 OB

POINT TO NEXT BUFFER LOCATION.

IS IT REALLY MINUS?
YES. MAKE IT POSITIVE.
PUT THE MINUS SIGN IN THE BUFFER.

FLTASC14 INX

0874 C501 CD EF 00

STX

0815 C504 4F

CLRA

0876 C505 CE 00 OA

LOX

POINT TO NEXT BUFFER LOCATION.
0, Y

SAVE POINTER TO STRING BUFFER.

#10

DIVIDE DECIMAL EXPONENT BY 10.

SET UP FOR DIVIDE.

0877 C508 02

IDIV

0878 C509 37

PSHB

SAVE REMAINDER.

0879 C50A 8F

XGDX

PUT QUOTIENT IN D.

0880 C50B CB 30

ADDB

#$30

MAKE IT ASC I I.

0881 C50D CD EE 00

LOX

0, Y

GET POINTER.

0882 C510 E7 00

STAB

O,X

0883
0884
0885
0886
0887
0888

INX

C51-2
C513
C514
C516
C51B
C519

08
33

PULB

CB 30

AODB

#$30

E7 00

STAB

O,X

OB

INX

6F 00

FLTASC15 CLR

0889 C51B 38

PUT NUMBER IN BUFFER.
POINT TO NEXT LOCATION.
GET SECOND DIGIT.
MAKE IT ASCII.
PUT

TERMINATE STRING IIITH A ZERO BYTE.

O,X

PULX

0890 C51C 3B

PULX

0891 C51D 38

PULX

\1 TIN THE BUF FER.

POINT TO NEXT LOCATION.
CLEAR LOCALS FROM STACK.

0892 C51E BD C8 43

JSR

0893 C521 32
0894 C522 97 04

PULA

0895 C524 38

PULX

0896 C525 OF 02

STX

0897 C527 38
OB98 C528 OF 00

PULX

0899 C52A 38

PULX

POINT TO THE START OF THE ASCI I STRING.

0900 C52B 39

RTS

RETURN.

STAA

STX

PULFPAC2

RESTORE FPACC2.

MANTSGNI
RESTORE FPACCI.
FPACC1MN+'

FPACCIEX

0901
0902

0903 C52C
0904 C52C OF 42 40

DECDIG

EQU
FCB

SOf,S42,$40

DECIMAL 1,000,000

86 AO

FCB

SOI,S86,SAO

DECIMAL

100,000

0906 C532 00 27 10

FCB

SOO,S27,S10

DECIMAL

10,000

0907 C535 00 03 E8
0908 C538 00 00 64

FCB

SOO,S03,$E8

DECIMAL

1,000

FCB

SOO,SOO,$64

DECIMAL

100

0909 C53B 00 00 OA

FCB

SOO,SOO,SOA

DECIMAL

10

0910 C53E 00 00 01

FCB

SOO,SOO,SOl

DECIMAL

0905 C52F 01

0911
0912

0913 C541

CONSTANT 999999.9

P9999999 EQU

345

0914 e54! 94 74 23 FE

fca

0915
0916 e545
0917 C545 98 18 96 71

M9999999 EQ\/
FeB

194, '74, '23, .FE
eOMSUNT 9999999.
'98,'!8,596,57F

0918

0919 C549

CONSIPS EQU

09Z0 e549 80 00 00 00

COMSTANI

FeB

sao, '00, '00, SOO

EQ\/
TST

MANTSGN!

BPl
TST

Fl TCMP2
MANTSGNZ

aPl
lOD
CPO
BNE

fLTCMP2
FPACC2EX
FPACCIEX
FlTCHP!

lOO
CPO
RTS

FPACC2MN-l

.5

0921
092Z

0923 C54D

Fl TCMP

0924 C540 7D 00 04
0925 e550 2A 12
0926 C552 7D 00 09
0927 C555 2A 00

e92S C557 DC D5
0929 C559 lA 93 00
0930 C5)C 26 05
0931 C55E DC 07
0932 C560 1A 93 02
0933 C563 39
0934 C564 96 04
0935
0936
0937
0938

C566
C568
C56A
C56C

91
Z6
DC
1A

09
F9
00
93 05

0939 C56f 26 fZ
0940 C571 DC 02
0941 C573 IA 93 07
0942 C576 39
0943
0944

FLTCHPI
FL TCMP2

LDM
CMPA
BNE
LDD
CPO
BHE
lOD
CPO

IS FPACCI MEGATIVE?
NO. COMTINUE IIIlH COMPARE.
IS FPACC2 MEGATI VE?
NO. CONTINUE IIITH COMPARE.
YES. BDTH ARE NEGATIVE SO COMPARE MUST 8E DONE
UCKIIARDS. ARE THEY EQUAL SO FAR?
NO. RETURN IIITH CONDITION COOES SET.
YES. COMPARE lOllER 16 8ITS OF MANTISSAS.

FPACC!HN-!
RETURIIIIITH CONDITION COOES SET.
MANTSGNI
HANTSGN2
FLTCMP!
FPACC1EX
FPACC2EX
FLTCHPI
FPACCIHN-I
FPACCZMN-!

GET "ACC! MANTISSA SIGN.
80TH POSI Tlvn
NO. RETURM IIITH CONDITION COOES seT.
GET FPACC! EXPOMENT & UPPER 8 BITS OF MANTISSA.
SAME AS FPACCZ?
NO. RETURN IIITH CONDITIOM COOES SET.
GET FPACCI lOllER 16 BITS OF MANTISSA.
COMPARE IIlTH FPACCZ LOIIER 16 BITS OF MANTISSA.
RETURM 1I11H CONDITIOM CODES SET.

RTS

0945

346

0946

TTL

INT2FLT

0947
0948
0949

UNSIGNED INTEGER TO flOATING POINT

0950
0951
0952

This subroutine performs "unsignedu integer to floating point
conversion of a 16 bit word. The 16 bit integer rust be in the

0953

lower 16 bits of FPACCl mantissa.

0954

number' is returned in fPACC1.

The resuLting floating point

0955
0956
0957
0958
0959 C577

UINT2FlT EQU

0960 C577 CE 00 00

LOX

#FPACC1EX

0961 C57A BO Cl 80

JSR

CHCKO

IS IT ALREADY O?

0962 C570 26 01

BNE

UINTFL T1

NO. GO CONVERT.

#$98

GET BIAS + NUMBER OF BITS IN MANTISSA.

0963 C57F 39

POI NT TO FPACC1.

YES. JUST RETURN.

RTS

0964 C580 86 98

UINTFLT1 LOAA

0965 C582 97 00

STAA

FPACC1EX

INITIALIZE THE EXPONENT.

0966 C584 BO Cl 61

JSR

FPNORM

GO MAKE IT A NORMALIZED FLOATING POINT VALUE.

0967 C587 OC

CLC

NO ERRORS.

0968 C588 39

RTS

RETURN.

0969
0970
0971
0972
0973
SIGNED INTEGER TO FLOATING POINT

0974
0975
0976

This I"outine works just like the unsigned integer to floating

0977

point routine except the the 16 bit integer in the FPACC1

0978

mantissa is considered to be in two'S complement format. This
wilt return a floating point number in the range -32768 to +32767.

0979
0980
0981
0982
0983
0984 C589

SINT2FLT EQU

0985 C589 DC 02

LOO

0986 C58B 36

PSHA

0987 C58C 2A 07

BPL

0988 C58E 43

COMA

FPACC1MN+l

GET THE LOI/ER 16 BITS OF FPACC1 MANT I SSA.
SAVE SIGN OF NUMBER.

SINTFLT1

IF POSITIVE JUST GO CONVERT.
MAKE POS IT I VE •

0989 C58F S3

COMB

0990 C590 C3 00 01

AOOO

#1

TWO'S COMPLEMENT.

0991 C593 00 02

STO

FPACC1MN+'

PUT IT BACK IN FPACC1 MANTISSA.

0992 C595 80 EO

SINTFL T1 BSR

UINT2FLT

GO CONVERT.

0993 C597 32

PULA

0994 C598 C6 FF

LOAB

0995 C59A 40

TSTA

0996 C59B 2A 02
0997 C590 07 04

GET SIGN OF ORIGINAL INTEGER.
#$FF

GET "MI NUS SI GNU.

BPL

SINTfl T2

NO. RETURN.

STAB

HANTSGNl

0998 C59F DC

SINTFLT2 CLC

0999 C5AO 39

RTS

WAS THE NUMBER NEGATIVE?
YES. SET FPACCl SIGN BYTE.
NO ERRORS.
RETURN.

1000
1001
1002

347

1003

TTL

FU21NT

**.**.*...***'*••**.********.*.*.*****~*** ••**.** •• ** •• * e •• _"' •••••••••••••••••

1004

•

1005

1006

fLOATING POIMY TO INTEGEI CONVERSION

1007

1008

This subroutine will perfor. A"""ignecP' floating point to integer
The floating point .....r if positive. will be
converted to .an unsigned 16 b.it integer ( 0 <= X c= 65535). If
the rn.i1Oer is negative it will be converted to.a twos cOIf1)tement

1009

conversion.

1010

lOll
1012

16 bit integer.

1013

addresses to be represented as positive nunbers when in float ing
point formaL Any fractional rnRber part is disguarded

1014

This type of conversion will allow 16 bit

--_... _............................-..............._--_._-*._.. _._._-----._.-*

lOIS
1016
1017
1018

FLT21NT

1019 C5AI

EQU

1020 C5AI CE 00 00

LOX

'fPACC1EX

1021 C5A4 aD Cl aD

JSR

CHCKO

POINT TO FPACCI.
IS IT 07

1022 C5A7 27 41

BEQ

FLT21NT3

YES. JUST RETURN.

1023 C5A9 06 00

LOAI

FPACCIEX

GET FPACCI EXPONENT.

1024 C5A8 Cl 81

CMP8

1025 C5AO 25 34

IlO

ISSI
fL T21NT2

NO. GO PUT A 0 IN FPACCI.

1026 C5AF

70 00 04

1027 C582 21 16
1028 C5B4 CI 90
1029 C586

22

27

1030 C588 CO 98

IS THERE AN INTEGER PART?

TST

MANTSGNI

IS THE NUMBER NEGATIVE?

aMI
CMPI

FU21NTI

YES. GO CONVERT NEGATIVE NUMBER.

1$90

IS TNE NUMBER TOO LARGE TO BE MAOE AN INTEGER?

8NI

FL T21NT4

YES. RETURN WITH AN ERROR.

SUBS

1$98

SUBTRACT THE BIAS PLUS THE NUMBER OF BITS.

FPACCINN

MAKE THE NUMBER AN INTEGER.

1031 C58A 74 00 01

FLTZIHT5 LSR

1032C5aD 76 00 02

ROR

fPACCIMN+I

1033 C5CO 76 00 03

lOR

FPACCIMN+2

1034 C5C3 SC

INCI

1035 C5C4 26 F4

.NE

FLT21NT5

NO. KEEP GOING.

1036 C5C6 7F 00 00

CLR

FPACCIEX

ZERO THE EXPONENT (ALSO CLEARS THE CARRY).

1037 C5C9 39

RTS

DONE SHIFTING?

ISSF

IS THE IiUM8ER TOO SMAll TO BE MADE AN INTEGER?

8HI

FL T21NT4

YES. RETURN ERROR.

1040 CSCE CO 98

SUSI

1$98

SUBTRACT 811.5 PLUS NUM8ER OF 8ITS.

1041 C500 80 E8

BSR

FU21NT5

GO 00 SHIFT.

1042 C502 OC 02

LOO

FPACCIMN+I

1043 C504 43

COMA

1044 C505 53

COMa

1045 C506 C3 00 01

AOOO

.,

TIIO'S COMPLEMENT.

1046 C509 00 02

STO

FPACCIMN+l

SAVE RESULT.

1047 C508 7F 00 04

ClI

MANTSGNl

1048 C50E 39

ITS

1038 C5CA Cl 8F
1039 C5CC 22 11

1049 C50F
1050 C5El

86
00

05

1051 C5E2 39
1052 C5E3 CC 00 00

FLTZINTI CMPI

FLT21NT4 LOM

CLEAR MANTISSA SIGN. (ALSO CLEARS THE CARRy)
RETURN.

ITOLGSMER

NUM8ER TOO LARGE OR TOO $~ALL TO CONVERT TO INT.

SEC

FLAG ERROR.

RTS

RETURN.

FLT21NT2 LOO

10

1053 C5E6 00 00

STO

FPACCIEX

1054 C5E8 00 02

STO

fPACCIMN+I

1055 C5EA 39

GET RESULTING INTEGER.
MAKE IT NEGATIVE.

fL T21 N13 ITS

ZERO fPACCI.
(ALSO CLEARS THE CARRY)
RETURN.

1056
1057
1058

348

TTL

1059

FLTSQR

***.* •• ****.*********** •••••• *********.****************************.********.*

1060
1061

1062

SQUARE ROOT SUBROUTI NE

1063

1064

This routine is used to calculate the square root of the floating

1065

point nunber in FPACC1.

1066

error is returned.

If the nunber in FPACCl is negative an

1067
1068

I«lRSE CASE

= 16354 CYCLES

= 8177

uS iI 2MHz

1069
1070
1071
1072
1073 C5EB

FLTseR

EQU

1074 C5EB CE 00 00

LOX

tFPACC1EX

1075 C5EE BD Cl 80

JSR

CHCKO

IS IT ZERO?

1076 C5Fl 26 01

BNE

FLTSQRl

NO. CHECK FOR NEGATIVE.

1077 C5F3 39

RTS

1078 C5F4 70 00 04

YES. RETURN.

TST

MANTSGNl

IS THE NUMBER NEGATIVE?

1079 C5F7 2A 04

BPL

FLTSQR2

NO. GO TAKE lTS SQUARE ROOT.

1080 C5F9 86 06

LDAA

#NSORTERR

YES. ERROR.

1081 C5FB 00

SEC

FLAG ERROR.

1082 C5FC 39

RTS

RETURN.

1083 C5FD BD C8 39

FLTSQRl

POINT TO FPACC1.

FLTSQR2

1084 C600 86 04

JSR

PSHFPAC2

SAVE [PACC2.

LDAA

#4

GET lTERATlON LOOP COUNT.

1085 C602 36

PSHA

1086 C603 DE 02

LOX

lOB7 C605 3C

PSHX

1088 C606 DE 00

LOX

1089 C60S 3C

PSHX

SAVE IT ON THE STACK.
FPACC1MN<1

SAVE INIT IAL NUMBER.

FPACC 1EX
POINT TO IT.

1090 C609 18 30

TSY

1091 C60B 80 39

BSR

TFRlT02

TRANSFER FPACCl TO fPACe2.

1092 C60D 96 05

LDAA

FPACC2EX

GET FPACCI EXPONENT.

1093 C60F 80 80

SUBA

#S80

REMOVE BIAS FROM EXPONENT.

1094 C611 4C

INCA

1095 C612 2A 03

BPt

1096 C614 44

LSRA

1097 C615 20 03

BRA

1098 C617 44

fLTSeR3

1099 C618 8B 80

COMPENSATE fOR ODD ExPONENTS (GIVES CLOSER GUESS)
FLTSOR3

If NUMBER >1 DIVIDE EXPONENT BY 2 & ADD BIAS.

FL TSQR4

GO CIILCULATE THE SOUARE ROOT.

IF <1 JUST DIVIDE IT BY 2.

LSRA

DIVIDE ExPONENT BY 2.

ADDA

#S80

ADD BIAS BACK IN.

1100 C61A 97 O~

FL TSQR4

STAA

FPACC2EX

SAVE ExPONENT /2.

"01 C61C BD e3 OA

FuseR5

JSR

FL TDIV

DIVIDE THE ORIGINAL NUMBER BY THE GUESS.

1102 C61F BD C2 3e

JSR

FL TADD

ADD THE "GUESS" TO THE OUOTIENT.

1103 C622 7A 00 00

DEC

FPACC1EX

DIVIDE THE RESULT BY 2 TO PRODUCE A NEW GUESS.

1104 C625 80 IF

BSR

TFRlT02

PUT THE NEW GUESS INTO FPAee2.

1105 C627 18 EC 00

LOO

0, Y

GET THE ORIGINAL NUMBER.

1106 C62A DO 00

STD

FPACC1EX

PUT IT BACK IN FPACCl.

1107 C62C 18 EC 02

LDD

2, Y

GET MANTISSA LOWER 16 BlTS.

1108 C62F DO 02

STO

FPACC1MN+1

DEC

4, Y

BEEN THROUGH THE LOOP 4 TIMES?

BNE

FL TSaR5

NO. KEEP GOING.

1109 C631 18

6A 04

1110 C634 26 E6
"11 C636 DC 05

LDD

FPACC2EX

THE FINAL GUESS IS THE ANSWER.

1112 C638 DO 00

STD

fPACC1EX

PUT IT IN fPACCI.

1113 C63A DC 07

LDD

FPACe2MN<1

1114 C63C DO 02

STD

fPACC1MN<1

1115 C63E 38

PULX

1"6 C63F 38

PULx

1117 C640 31

INS

1118 C641 BD C843

JSR

1119 C644 OC

CLC

1120 C645 39

RIS

GET RID OF ORIGINAL NUMBER.
GET RID OF LOOP COUNT VARIABLE.
PULFPAe2

NO ERRORS.

1121
1122
1123 C646

TFRlT02

RESTORE FPACC2.

EOU

349

1124 C646 OC 00
1125 C648 00 05
1126 C64A DC 02
1127
1128
1129
1130

C64C
C64E
C650
C652

00 07
9604
97 09
39

LOP
STO

LOG

sro
lDM
STM
RTS

FPACC1EX
FPACC2EX
FPACC1H11+1
FPACC2HH+l
MANTSGN!
MANTSGN2

co£T FPACCI EXPOIIEIIT & HIGH 8 IU Of MANTISSA.
PUT IT III FPACC2.
GET fPACCl LOll 16 IITS OF MANTISSA.
PUT IT IN fPACC2.
TRANSfER THE SIGII.
RETURN.

1131
1132
1133

350

1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159

TTL
FLTSIN
*********.**************** •••• ******.**********************.********* •••• *.***
FLOATING POINT SINE

C653
C653
C656
C659
C65A
C65B
C65E
C65F
C662
e663
e665
C667
C66A
C66B
e66E

FL TSIN

BD
BD
37
36
BD
32
BD
32
81
23
73
OC
BD
39

C8 39
C7 59

EQU
JSR

PSHFPAe2

SAVE FPACe2 ON THE STACK.

JSR

ANGRED

GO REDUCE THE ANGLE TO BETWEEN. + /. PI.

PSHB

SAVE THE QUAD COUNT.

PSHA

C8 13

JSR

SAVE THE SINE/COSINE FLAG.
DEG2RAO

PULA

C6 8F

FL TSINI

JSR

SINCOS

PULA

02
03
00 04
FLTSIN2

C8 43

CONVERT DEGREES TO RADIANS.
RESTORE THE SINE/COSINE FLAG.
GO GET THE SINE OF THE ANGLE.
RESTORE THE QUAO COUNT.
WAS THE ANGLE IN QUAOS 1 OR 21

CMPA

112

BLS

FLTSIN2

YES. SIGN OF THE ANSWER IS OK.

COM

MANTSGNI

NO. SINE IN QUAOS 3 & 4 IS NEGATIVE.
SHOW NO ERRORS.

CLC
JSR

PULFPAC2

RESTORE FPACC2
RETURN.

RTS

351

.-_......._.._....._."--_ ...-.-------------------.----_.-_._------_.__._ ....._..

lt6G

ITl

1161

FllCOS

lf62
t163
1164

FLOATING POINT COSINE
***.*****************.~*.*****.********

1165
1166

....**•• *******.*_._. __ ._._------_._••_-

1167
tl68
1169
1170
1171

un

C66F
C66F BO C8 39
C6n BO C7 S9
C67S 37
C67636

U73 C677 BO
1174 C67A 32
a7S C678 88
1176 e671l BO
lln C680 32
1178 C681 81
1179 C683 27
1180 e6BS 81
1181 C6B7 27
1182 C689 73
1183 C68C 7E
1184
1185

FL TCOS

C8 13

01
C6 8F
01
07
04
03
00 04
C6 6A

FHCOSI

EQU
JSlt
JSlt
PSH.
PSNA
JSR
PULA
EORA
JSR
PULA
CMPA
BEQ
CMPA
BEQ
COM
JMP

PSHFPAC2
ANGUD

DEG2RAD
ISOI
SINCOS

.,
FLTCOSI

14
FLTCOSI
MANTSGNI
FLTSIN2

SAVE FPACC2 ON TIlE STACK.
GO REDUCE THE ANGLE TO .ETWEEN +,·PI.
SAVE THE QUAI) COJIIT.
SAVE TIlE SINE/COSllIE FLAG.
CONYERT TO RADIANS.
RESTORE THE SIIIE/COSINE FLAG.
COMPLIMENT 90'S COPMllMENT FLAG FOR COSINE.
GO GET THE COSINE OF THE ANGLE.
RESTORE TIlE QlJAD COUNT.
WAS THE ORIGINAL ANGLE IN QUAD 11
YES. SIGN IS OK.
WAS IT IN QUAD 41
YES. SIGN IS OK.
NO. COSINE IS NEGATIVE IN OUADS 2 & 3.
FLAG NO ERRORS, RESTORE FPACC2, & RETURN.

U86

352

TTL
_._e ... ________
._. ___ ._._._ .. ___ .__ ._ ..".."_.__ ."" ........._._._._. ___ ._ .... __

1187

SINCOS

1188
1189
1190

FLOATING POINT SINE AND COSINE SUBROUTINE

1191
1192
1193
1194
1195 C68F

SINCOS

Eau

1196 C68F 36

PSHA

1197 C690 DE 02

LOX

1198 C692 3C

PSHX

1199 C693 DE 00

LOX

1200 C695 3C

PSHX

1201 C696 96 04

LOAA

1202 C698 36

PSHA

1203 C699 CE C7 C3

LOX

1204 C69C 3C

PSHX

1205 C690 3C

PSHX

1206 C69E

86 04

LDAA

SAVE SINE/COSINE FLAG ON STACK.
FPACC1MN+l

SAVE THE VALUE OF THE ANGLE.

FPACC1EX
MANTSGN 1
~SINFACT

POINT TO THE FACTORIAL TABLE.
SAVE POINTER TO THE SINE FACTORIAL TABLE.
JUST AllOCATE ANOTHER LOCAL (VALUE NOT IMPORTANT)

K4

GET INITIAL LOOP COUNT.

1207 C6AO 36

PSHA

SAVE AS LOCAL ON STACK

1208 C6Al 18 30

TSY

POINT TO LOCALS.

1209 C6A3 BD C6 46

JSR

TFRlT02

TRANSFER FPACCI TO FPACC2.

1210 C6A6 BD Cl 93

JSR

FLTMUL

GET X'2 IN FPACCI.
ARE liE DOING THE SINE?

1211 C6A9 18 60 OA

TST

10,Y

1212 C6AC 27 DB

BEQ

SINCOS7

YES. GO DO IT.

1213 C6AE CE C7 03

LOX

#COSFACT

NO. GET POINTER TO COSINE FACTORIAL TABLE.

1214 C6Bl CD EF 01

STX

I, Y

SAVE IT.

1215 C6B4 BD C6 46

JSR

TFRlT02

copy

1216 C6B7 20 06

BRA

SINCOS4

GENERATE EVEN POWERS OF

JSR

EXG1AND2

PUT X'2 IN fPACC2 & X IN FPACCI.

X'2 INTO FPACC2.
IIXII

FOR COSINE.

1217 C6B9 BO C7 AA

SINCOS7

1218 C6BC BO Cl 93

SINCOSI

JSR

FL TMUL

CREATE X'3,5.7,9 OR X'2,4,6,8.

1219 C6BF DE 02

SINCOS4

LOX

FPACC1MN+l

SAVE EACH ONE ON THE STACK.

1220 C6Cl 3C

PSHX

1221 C6C2 DE 00

LOX

1222 C6C4 3C

PSHX

FPACC1EX

1223 C6C5 96 04

LDAA

1224 C6C7 36

PSHA

1225 C6C8 18 6A 00

DEC

0, Y

HAVE lIE GENERATED ALL THE POIIERS YET?

1226 C6CB 26 EF

BNE

SINCOSI

NO.\GQ 00 SOME MORE.

LDAA

tlS4

SET UP LOOP COUNT.

STAA

0, Y

1227 C6CO

86 04

1228 C6CF 18 A7 00
1229 C6D2 30
1230 C603

co

MANTSGNI
SAVE THE MANTISSA SIGN.

TSX

H

03

SINCOS2

POINT TO POIIERS ON THE STACK.
SAVE THE POINTER.

STX

3,Y

1231 C606 CD EE 01

LDX

I, Y

GET THE POINTER TO THE FACTORIAL CONSTANTS.

1232 C6D9 BD C8 66

JSR

GETFPAC2

PUT THE NUMBER IN FPACC2.

1233 C6DC 08

INX

1234 C6DD 08

INX

1235 C6DE 08

INX

POINT TO THE NEXT CONSTANT.

1236 C6Df 08

INX

1237 C6EO CD EF 01

STX

I, Y

SAVE THE POINTER.

1238 C6E3 CD EE 03

LDX

3, Y

GET POINTER TO POI/ERS.

1239 C6E6 A6 00

LOAA

O,X

GET NUMBER SIGN.

1240 C6E8 97 04

STAA

MANTSGNI

PUT IN FPACCI MANTISSA SIGN.

1241 C6EA EC 01

LDD

I,X

GET LOIIER 16·BITS Of THE MANTISSA.

1242 C6EC DO DO

STD

FPACC1EX

PUT IN FPACCI MANTISSA.

1243 C6EE EC 03

LDD

3,x

GET HIGH 8 BITS OF THE MANTISSA & EXPONENT.

1244 C6FO DO 02

STD

FPACC1MN+l

PUT IT IN FPACCI EXPONENT & MANTISSA.

1245 C6f2 SO Cl 93

JSR

fLTMUL

MUL TlPL Y THE TIIO.

1246 C6f5 CD EE 03

LOX

3,Y

GET POINTER TO POIIERS 8ACK.

1247 C6f8 DC 02

LDD

FPACC1MN+l

SAVE RESUL T IIHERE THE POIIER OF X liAS.

1248 C6FA ED 03

STD

3,X

1249 C6fC DC DO

LOD

fPACC1EX

1250 C6FE ED 01

STD

I,X

1251 C700 96 04

LDAA

MANTSGNI

353

SAVE SIGN.

1252 C702 A7 00

SlM

1253 C704 08

INX

1254 C705 08

INK

1255 C106 98

INX
INX

1256 t707 08

O;K
POINT TO TilE NEXT POWER.

1257 C708 08

INX

1258 C709 18 6A 00

DEC

O,Y

DONE?

1259 e70e 26 e5

8NE

SINeOSl

NO. GO DO ANOTHER MULTIPLICATION.

1260 C70E 86 03

LOM

#$3

GET LOOP COUNT.

1261 e710 18 A7 00

STAA

0, Y

SAVE IT.

LOX

3, Y

1262 e713 co EE 03

SINCOS3

1263 C716 09

DEX

1264 e717 09

OEX

1265 C718 09

OEX

1266 e719 09

OEX

1267 e71A 09

OEX

POINT TO RESULTS ON THE STACK.
POINT TO PREVIOUS RESULT.

1268 e718 co Ef 03

STX·

3, Y

1269 e71E A6 00

LOAA

O,X

GET NUMBERS SIGN.

1270 e720 97 09

SlAA

MANISGN2

PUT IT IN FPAce2.

SAVE THE NEW POI NTER.

1271 C122 Ee 01

LOO

l,X

GET LOll 16 SITS OF THE MANTISSA.

1272 e724 00 05

510

FPACC2EX

PUT IN FPAee2.
GET HIGH 8 BIT & EXPONENT.

1273 C726 Ee 03

LOO

1274 C728 DO 07

STO

fPAee2MN.l

1275 e72A BD e2 3C

JSR

fL TADO

GO ADO THE TIIO NUMBERS.

HI 6A 00

DEC

O,Y

DONE?

1277 e730 26 El

SNE

51 NeOS3

NO. GO ADO THE NEXT TERM IN.

1278 C732 18 60 OA

lSI

la, Y

ARE lie DOING THE SINE?

1276 C720

PUT IN FPACC2.

1279 C735 27 08

SEQ

SI14COS5

YES. GO PUT THE ORIGINAL ANGLE INTO FPAeC2.

1280 C737 CE C7 E3

LOX

IIOHE

NO. FOR COSINE PUT THE CONSTANT 1 INTO FPACC2.

1281 C73A 80 C8 66

JSR

GETfPAC2

1282 (730 20 OF

BRA

SINCOS6

LOM

5, Y

GET THE VALUE Of THE ORIGINAL ANGLE.

1284 C742 97 09

STAA

MANTSGN2

PUT IT IN FPACC2.

1283 C73F 18 A6 05

S I NCOS5

GO ADO IT TO THE SUH OF THE TERMS.

1285 C144 18 EC 06

LOO

6,Y

1286 C747 DO 05

SID

FPAeC2EX

1287 C749 18 EC 08

LOD

8,Y

12~ e74C 00 07

STO

fPACC2MN.l

JSR

fllAOO

1289 e74E SO C2 3C

SI NCOS6

1290 C751 3D

ISX

1291 C752 8F

XGOX

1292 C753 C3 00 lF

AOOD

1293 C756 8F

XGOX

GO ADO IT TO THE SUM OF THE TERMS.
NOW CLEAN UP THE STACK.
PUT STACK IN O.
CLEAR ALL THE TERMS & TEMPS OFf THE STACK.

.31

1294 C757 35

TXS

UPDATE THE STACK POINTER.

1295 C758 39

RTS

RETURN.

1296
1297
1298 C759

ANGRED

EQU

1299 C759 4F

eLRA

INITIALIZE THE 45'S COMPLIMENT fLAG.

1300 C75A 36

PSHA

PUT IT ON THE STACK.

1301 C75B 4C

INCA

INITIALIZE THE QUAD COUNT TO 1-

1302 C15C 36

PSHA

PUT IT ON THE STACK.
POINT TO IT.

1303 C750 18 30

TSY

1304 C75F CE C1 E8

LOX

.THREE60

POINT TO THE CONSTANT 360.

1305 C762 80 C8 66

JSR

GETfPAC2

GET IT INTO fPACC.

1306 C765 7D 00 04

TSI

HANTSGNl

IS THE INPUT ANGLE NEGATIVE:

1307 C168 2A 03

8PL

ANGREDl

NO. SKIP THE ADD.

1308 C76A BO C2 3C
1309 C760 7A 00 05

1310

cno

ANGREDl

7A 00 05

JSR

fL TAPD

YES. MAKE THE ANGLE POSITIVE BY ADDING 360 DEG.

DEC

FPACC2EX

MAKE THE CONSTANT IN fPACC2 90 DEGREES.

DEC

fPACC2EX

JSR

FLTCHP

IS THE ANGLE LESS THAN 90 DEGREES ALREADY?

1312 e776 23 08

BLS

ANGRED3

YES. RETURN WITH QUAD COUNT.
NO. REDUCE ANGLE BY 90 DEGREES.

1311 C773 SO C5 40

ANCRE02

1313 e778 80 e2 FE

JSR

FL TSUB

1314 C778 18 6C 00

INC

0, Y

INCREMENT THE QUAD COUNT.

1315 C77E 20 F3

BRA

ANGRED2

GO SEE If IT'S LESS THAN 90 NOlI.

LOM

0, Y

GET THE QUAD COUNT.

eMPA

.1

WAS THE ORIGINAL ANGLE IN QUAD"

1316 C780 18 A6 DO
1317 C783 81 01

ANGRED3

354

1318 eT85 27 OB

BEQ

ANGRED4

YES. COMPUTE TRIG FUNCTION AS IS.

1319 C787 81 03

CHPA

#3

NO. liAS THE ORIGINAL ANGLE IN QUAD 3>

1320 C789 27 07

BEQ

ANGRE04

YES. COMPUTE THE TRIG FUNCTION AS IF IN QUAD 1.

1321 C78B 86 FF

LDAA

nFF

NO. MUST COMPUTE THE TRIG FUNCTION Of THE 90'S

1322 C780 97 04

STAA

MANTSGNl

COMPLIMENT ANGLE.

1323 C78F BO C2 3C

JSR

FLTAOD

ADD 90 DEGREES TO THE NEGATED ANGLE.

DEC

FPACC2EX

MAKE THE ANGLE IN FPACC2 45 DEGREES.

1324 C792 7A 00 05

ANGRED4

1325 C795 BO C5 40

JSR

FL TCMP

IS THE ANGLE < 45 DEGREES?

1326 C798 23 00

BLS

ANGRED5

YES. IT'S OK AS IT IS.

1327 C79A 7C 00 05

INC

FPACC2EX

NO. MUST GET THE 90'S COMPLIMENT.

1328 C790 86 FF

LDAA

nFF

MAKE FPACCl NEGAT I VE.

1329 C79F 97 04

STAA

MANTSGNl

JSR

FLTADD

1330 C7Al BO C2 3C
1331 C7A4 18 6C 01
1332 C7A7 33

INC
ANGRED5

PULB

GET THE 90'S COMPLIMENT.
SET THE FLAG.

" Y

GET THE QUAD COUNT.

1333 C7A8 32

PULA

GET THE COMPLIMENT FLAG.

1334 C7A9 39

RTS

RETURN IIITH THE QUAD COUNT & COMPLIMENT fLAG.

1335
1336
1337 C7AA

EXG lAND2 EOU

1338 C7AA DC 00

LDD

FPACC 1EX

1339 C7AC DE 05

LOX

fPACC2EX

1340 C7AE DO 05

STO

fPACC2EX

1341 C7BO Of 00

STX

fPACC1EX

1342 C7B2 DC 02

LOO

fPACC1MN+l
FPACC2MN+l

1343 C7B4 DE 07

LOX

1344 C7B6 DO 07

STO

FPACC2MN+1

1345 C7B8 Of 02

STX

FPACC1MN+l

1346 C7BA 96 04

LOAA

MANTSGNl

1347 C7BC 06 09

LOAB

MANTSGN2

1348 C7BE 97 09

STAA

MANTSGN2

1349 C7CO 07 04

STAB

MANTSGNl

1350 C7C2 39

RTS

RETURN.

1351
1352
1353 C7C3

SINfACT

EOU

1354 C7C3 6E 38 EF 10

fCB

$6E,S38,SEf, S10

1355 C7C7 74 DO 00 01

fCB

S74, SOD, SOD, SOl

• <1/7!)

1356 C7CB 7A 08 88 89

fCB

S7A, S08, S88, S89

+(1/5! )

1357 Clef 7E AA AA AB

fCB

S7E, SAA, SAA, SAB

. (1/3!)

+(1/8' )

+(1I9! )

1358
1359
1360 ClO3

COSfACT

Eau

1361 ClO3 71 50 00 01

fCB

S71, S50, SOD, SOl

1362 ClO7 77 B6 DB 61

fCB

S77, SB6, SOB, S61

'(1I6! )

1363 ClOB 7C 2A AA AB

feB

$le, S2A, SAA, SAB

+(1/4! )

1364 ClOF 80 80 00 00

feB

S80, S80, SOD, SOD

-(1/2' )

1365
1366
1367 C7E3 81 00 00 00

ONE

feB

S81,SOO,SOO,SOO

1.0

1368 C7E7 82 49 Of DB

PI

feB

S82, S49, SOf, SOB

3.1415927

1369 C7EB 89 34 00 00

THREE60

feB

S89, S34, SOD, SOD

360.0

1370
1371
1372

355

1373

HL
_._.*. __ .•..
_._ ..•. _---_._-_._..... _--_ .•. _-------------•••.. _....... -. __ ......FLllAN

1374
1375
Il76

flOATING POINT TANGENT

1377

_••• ** •• _.-._._._---_.-.-••••••

1378

-.-_.-.-._._-_._._-----**---_ .. -.---_._._--_ ...

1319
1380
1381 C7Ef

fL TTAN

EQIJ

1382 C7Ef BD C8 39

JSR

PSHfPAC2

1383 C7F2 80 C6 46

JSR

TFRIT02

PUT A COPY Of THE ANGLE IN FPACC2.

1384 C7F5 80 C6 6F

JSR

FLTCOS

GET COSINE Of THE ANGLE.
PUT RESUL TIN FPACC2 & PUT ANGLE IN fPACC1.

SAVE FPACC2 ON THE STACK.

1385 C7F8 BD C7 AA

JSR

EXG1AND2

1386 C7FB 80 C6 S3

JSR

fLTSIN

GET SIN OF THE ANGLE.

1387 C7FE 80 C3 OA

JSR

fLTOIV

GET TANGENT Of ANGLE BY DOING SIN/COS.

1388 C8Dl 24
1389 C8D3

ce

08

BCC

FLllANl

IF CARRY CLEAR, ANSWER OK.

C8 OF

LOX

tlMAXNUM

TANGENT Of 90 WAS ATTEMPTED. PUT LARGEST

1390 C806 8D C8 SO
1391 C809

86 07

1392 C808 BD C8 43

FlllANl

1393 C80E 39

JSR

GETFPACI

NUMBER IN fPACC1.

LDAA

#lAN90ERR

GET ERROR CODE IN A.

JSR

PULFPAC2

RIS

RESTORE FPACC2.
RETURN.

1394
1395
1396 C80F
1397 C80f FE 7F Ff FF

MAXNUM

EQU
FCB

SFE,S7F,SFF,SFf

1398
1399
1400

356

LARGEST POSITIVE NUMBER WE CAN HAVE.

1401
1402

TTL

TRIGUTIL

*** •••••• ***** •••••••••• **** •••• * ••• ***.*** •• *.********.* •••• ************.**.*

1403
1404

TRIG UTILITIES

1405
1406

The routines "OEG2RAO" and "RA02DEG" are used to con....ert angles

1407

from degrees-to-radians and radians-to-degrees respectively. The

1408
1409

routine "GElPI" will place the value of PI into FPACC1. This
routine should be used if the value of PI is needed in calculations '*

1410

since it is accurate to the full 24-bits of the mantissa.

1411
1412
1413
1414
1415 C813

OEG2RAO

EQU

1416 C813 BO C8 39

JSR

PSHfPAC2

SAVE fPACC2.

1417 C816 CE C8 31

LOX

lIPIOV180

POINT TO CONVERSION CONSTANT P1/180.

1418 C819 80 C8 66

DEG2RADI JSR

GETfPAC2

PUT IT INTO fPACC2.

1419 C81C BD Cl 93

JSR

fLTMUL

CONVERT DEGREES TO RADIANS.

1420 C81F 8D C8 43

JSR

PULfPAC2

RESTORE fPACC2.

1421 C822 39

RTS

RETURN. (NOTE! DON'T REPLACE THE IIJSR/RTSII \011 TH

1422

A "JMP" IT WILL NOT WORK.)

1423
1424
1425 C823

RAD2DEG

EQU

1426 C823 BD C8 39

JSR

PSHfPAC2

SAVE fPACC2.

1427 C826 CE C8 35

LOX

'CI800VPI

POINT TO CONVERSION

1428 C829 20 EE

BRA

DEG2RADI

GO DO CONVERSION & RETURN.

'PI
GETfPACl

PUT IT IN fPACCl AND RETURN.

CONSTA~T

1429
1430
1431 C82B

GETPI

EQU

1432 C82B CE C7 E7

lOX

1433 C82E 7E C8 50

JMP

POINT TO CONSTANT "PIII.

1434
1435
1436 C831
1437 Cal I 7B OE fA 35

PIOVI80

EQU
fCB

S7B,SOE ,Sf A, S35

1438
1439 C835
1440 C835 86 65 2E E I

C1800VPI EQU
fCB

S86,S65,S2E, SEI

1441
1442
1443

357

lao/PI.

_.•......••TTL,. ••.•_----*.•••_•••••••••••••••_--_••••••-.---------_._._•••••-••_.

1444
1445
1446

PSHPUlFPAC2

1447
1448

The following two subroutines, PSHFPAC2 & PUlPFAC2, push FPACC2
onto and pull fPACC2 off of the herdware stock respectively.

The m..aar is stored in the "memoty for.t".

1449

................ ---........_.._----_.....--..--_....._-----_.-._--_._._._.....-

1450
1451
1452
1453
1454 C839

PSHFPAC2 EQU

1455
1456
1457
1458
1459

C839
C8lA
C83B
C83C
C830

1460
1461
1462
1463
1464
1465
1466
1467
1468
1469

C83E 37
C83F 36
C840 7E C8 8C

C843
C843
C844
C845
C846

38
3C

3C
8F
30.

PULX
PSHX
PSHX
XGDX
TSX
PSHB
PSHA
JMP

GET THE RETURN ADDRESS OFF OF THE STACK.
ALLOCATE fOUR BYTES OF STACK SPACE.
PUT THE RETURN ADDRESS IN D.
POINT TO THE STORAGE AREA.
PUT THE RETURN ADDRESS BACK ON THE STACK.
PUTFPAC2

GO PUT FPACC2 ON THE STACK & RETURN.

PUL FPAC2 EQU
30
08
08
SO C8 66

1470 C849 38
1471 C84A 31
1472 C84B 31
1473 C84C 31
1474 C84D 31
1475 C84E 6E 00
1476
14n
1478

TSX·
INX
INX
JSR

POINT TO THE RETURN ADDRESS.
POINT TO THE SAVED NUMBER.
GETFPAC2

PULX
INS
INS
INS
INS
JMP

R.ESTORE FPACCZ.
GET THE RETURN ADDRESS OF F THE STACK.
REMOVE THE NUMBER FROM THE STACK.

RETURN.

D,X

358

1479
1480
1481

TTL

GETFPAC

******************************************************--_ •••• _._---------_ ••• -

1482

GETFPACx SUBROUTINE

1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500

The GETFPAC1 and GETFPAC2 subroutines get a floating point nurtber
stored in memory and put it into either FPACC1 or FPACC2 in a format ..
that is expected by all the floating point math routines. These
routines may easi Ly be replaced to convert any binary floating point ..
format (i.e. IEEE format) to the format required by the math
routines. The "memory" format converted by these routines is shown ..

below:
31 _ _ 24 23 22 _ _ _.,--_ _ _ '

The exponent is biased by '~8 to facilitate floating point
coqliIr i sons. The sign bit is 0 for positive nlnbers and 1

for negative rureefS. The mantissa is stored in hidden bit
normalized format so that 24 bits of precision can be obtained.
Since a normal ized floating point nutber always has its most
significant bit set, we can use the 24th bit to hold the mantissa
sign. This allows us to get 24 bits of precision in the mantissa
and store the entire nunber in just 4 bytes. The format required by ..
the math routines uses a seperatt: byte for the sign. therfore each
floating point accunulator requires five bytes.

1501
1502
1503
1504
1505
1506
1507
1508

1509 C850
1510
1511
1512
1513
1514
ISIS
1516
1517
1518
1519
1520
1521
1522

ltant i 5sa

exponent

C850
C852
CBS4
C857
C858
C85A
C850
C85F
C861
C863
C865

.EC
27
7F
5D
2A
73
CA
00
EC
DO
39

00
OB
00 04
03
00 04
80
00
02
02

1.523 C866
1524 C866 EC 00
1525 C868 27 DB
1526 C86A 7F 00 09
1527 C86D 50
1528 C86E 2A 03
1529 C870 73 00 09
1530 C873 CA80
1531 C875 DO 05
1532 C877 EC 02
1533 C879 00 07
1534 C878 39

GETFPACI EQU
LOO
BEQ
CLR
TSTS
BPL
COM
GETFP11 ORAB
GETFP12 STO
LOO
STD
RTS

O,X
GETFP12
MANTSGNI
GETFP11
MANTSGNI
t/S80
FPACC1EX
2,X
FPACC1MN+l

GET THE EXPONENT & HIGH BYTE OF THE MANTISSA.
IF NUMBER IS ZERO, SKIP SETTING THE MS BIT.
SET UP FOR POSIT IVE NUMBER.
IS NUMBER NEGATIVE?
NO. LEAVE SIGN ALONE.
YES. SET SIGN TO NEGATIVE.
RESTORE MOST SIGNIFICANT BIT IN MANTISSA.
,PUT IN fPACC1.
GET LOll 16-BITS OF THE MANTISSA.
PUT IN FPACC1.
RETURN.

GETFPAC2 EQU

GETFP21
GETFPZZ

LOD
BEQ
CLR
TSTB

O,X
GETFP22
MANTSGN2

BPl

GETfP21
MANTSGN2
t/S80
FPACC2EX

COM
ORAS
STO
LOD
STD
RTS

2,X
FPACC2MN+l

1535
1536
lS31

359

GET THE EXPONENT & HIGH BYTE OF THE MANTISSA,
IF NUMBER IS 0, SI(JP SETTING THE MS SIT.
SET UP FOR POSITIVE NUMBER.
IS NUMBER NEGATIVE?
NO. LEAVE SIGN ALONE.
YES. SET SIGN TO NEGATIVE.
RESTORE MOST SIGNIFICANT BIT IN MANTISSA.
PUT IN FPACCI.
GET LOll 16·BITS OF THE MANTISSA.
PUT IN FPACC1.
RETURN.

-_._...-.-------._._--------_._-----_._---_._........_.-------_._--_._-_....---

1538
1539
1540
1541

TTL

f'UTFPACl( SUBROUTINE

1542
1543
1544
1545

These two slAlroutines perforll to _ i t e function of GETfPACl and

GETFPAC2. Again 6 these routines .re used to convert from the
internal format used by the floating point package to a "memory"
fonnat. See the GETFPACI and GETFPAC2, docunentation for a

1546
1547
1548

description of the I'memory' fOMMt.

-------_..._-------_._ .._---------------------_._._-------_..._----------_._.-

1549
1550
1551
1552 C87C
1553 C87C DC 00
1554 C87E 7D 00 04
1555 C881 2B 02
1556 C883 C4 7F
1557 C885 ED 00
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567

f'UTfPAC

C887 DE 02
C889 ED 02
C888 39

C88C
C88C
C88E
C891
C893

DC 05
7D 00 09
2B 02
C4 7F

1568 C895 ED 00
1569 C897 DC 07
1570 C899 EO 02
1571 C89B 39

PUT FPAC 1 EQU
lDD
TST

8M1
PUTFPll

ANDB
STD
LOD
STD
RTS

PUTFPAC2 EQU
lDD
TST
BMI
ANOB
PUTFP21 STD
Loo
STD
RTS

FPACC1EX
MANTSGNI

GET FPACCI EXPONEHT & UPPER 8 BITS OF

PUTfPll
tS7F

YES. LEAVE THE M.S. BIT SET.
NO. CLEAR THE M.S. BIT.
SAVE IT IN MEMORY
GET L.S. 16 BITS OF THE MANTISSA.

MA~T.

IS TilE NUMBER NEGATIVE?

O,X
FPACC1MN+l
2,X

GET FPACCI EXPONENT & UPPER 8 B ITS OF MANT.

FPACC2EX
MANTSGN2
PUTFP21
tS7F

O,X
fPACC2MN+l

IS THE NUMBER NEGATIVE?
YES. LEAVE THE M.S. BIT SET.
NO. CLEAR THE M.S. BIT.
SAVE IT IN MEMORY
GET L.S. 16 BITS Of THE MANTISSA.

2,X

15n
1573
1574

360

AOONXTO

C002 '0229 0145 0221

AOONXTOl

Cl0E '0261 0235 0238 0246 0250 0258

ANGRED

C759 '1298 1144 1170

ANGREDI

C760 '1309 1307

ANGRED2

C773 '1311 1315

ANGRE03

Cl80 '1316 1312

ANGRED4

C792 '1324 1318 1320

ANGRED5

e7A7 '*1332 1326

ASCFL T

COOD '0095

ASCFLTl

C014 '0105

ASCFL Tl0

COBC '0212 0144

ASCFLTll

COCl '0218 0128 0225

ASCFL Tl2

COB6 '0206 0204

ASCFL T 13

C070 *0172 0167

ASCFL T14

eOAD *0202 0191

ASCFLT15

C082 ·0181 0177

ASCFLT16

C085 '0182 0179

ASCFL T2

C01B '0111

ASCFL T3

C02A '0122 0112

ASCFL T4

C043 '0142 010701170147

ASCFL T5

C039 '0132 0123 0127 0180 0185 0201

ASCfL T6

COSO '0151 0155

ASCFL T7

C069 '0166 G157 0163 0213 0220

ASCFl T8

C05F '0161 0165 0223

ASCFL T9

C080 '0186 0175

C1800VP I

C835 '1439 1427

CHCKO

C180 '0331 0277 0315 0361 0364 0466 0472 0610 0616 0736

CHeKOl

C188 '0337 0335

CONSTlO

C18F '0342 0291 0772

CONSTPl

C188 '0341 0287 0777

0961 1021 1075

CONSTP5

C549 '0919 0779

COSFACT

Cl03 *1360 1213

DECO I G

C52C '0903 0818

DEG2RAD

C813 '1415 1147 1173

DEG2RAOl

C819 *1418 1428

01 VOERR

0004 '0041 0612

EXG1AN02

C7AA '1337 1217 1385

EXPS I GN

0000 '0089 0181 0203

FINISH

C117 '0274 0168 0208

F INISHI

C140 '0291 0286

FINI SH2

C146 '0293 0290 0295

FINI SH3

c14E '0296 0278 0285

FLT21NT

C5Al *'019

FL T21NTI

C5CA '1038 1027

FLT21NT2

C5E3 '1052 1025

FLT2INT3

C5EA '1055 1022

FL T21NT4

e50F ·1049 1029 1039

FLT21 NT5

e5BA '1031 1035 1041

FLT ADD

C23C *0463 0582 0781 1102 1275 1289 1308 1323 1330

FLTAOOl

C24C '0471 0467

FLTADD10

C248 '0469 0543 0560

FLTAD011

C20e '0546 0504

FLTADD12

C209 '0544 0540 0552 0557

FLTADD2

C262 '0481 0473

FLTADD3

C27B '0494 0485

FUADD4

C254 '0474 0488

FL TADD5

C282 '0497 0493 0501

FL TADD6

C247 '0468 0480 0495 0544

FLTADD7

C28B '0502 0483

FL TA008

C2AA '0519 0506

FLTADD9

C2CE '0539 0525

FLTASC

C3DB '0733

FlTAscl

c3EB ·0742 0737

FL TAsel0

C49B '0821 0854

FLTASC11

C49E '0822 0830

361

FlTASC12
FLTASC13
Fl TAse14
FLTASC15
FlfASC16
FlTASC17
FlTASC18
Fl fASC2
FL fASC3
Fl TASC4
FlTASC5
F1 TASC6
FL TASC7
FL TASC8
Fl TAse9
Fl TeMP

FL TCMPI
FL TCMP2
FL TCOS
FL TCOSI
FLTDIV
FLTDIVI
FLTDIV10
FL TDIV11
FL TDIV12
FL TOIV13
FLTOIV14
FLTOIV2
FLTOIV3
Fl TOIV4
FLTOIV5
Fl TOIV6
FL TDIV7
FLTOIV8
FL TOIV9
FL TFMTER
fL TMUL.

FLTS I N
FlTSINl
fLTSIN2
Fl TSQR
FL TSQRl
FL TSQR2
FL TSQR3
fLTSQR4
fl TSQR5
fl TSUB
Fl TSUBl
fl TTAN
fl TTANl
FPACC1EX

fPACC1MN

fPACC2EX

C4Bl
C4EZ
C500
C519
C403
C1,5C
C490
C40E
C438
C440
C414
C430
C452
C474
C493
C540
C563
C564
C66F
C68C
C30A
C316
C399
C3Cl
C307
C3C4
C35E
C320
C33E
C350
C375
C348
C377
C345
C37B
0001
C193
C653
C65f
C66A
C5EB
C5f4
C5fO
C617
C61A
C61C
C2fE
C303
C7Ef
C80B
0000

'0831
*0856
*0873
'0888
'0848
'0791
'0817
'0760
'0776
'0779
'0763
'0773
'0787
'0804
'0818
'0923
'0933
~0934

'1168
'1183
'0608
'0615
'0684
'0703
'0712
'0704
'0655
'0620
'0636
'0648
'0666
'0642
'0667
'0640
'0669
'0038
'0358
'1142
'1149
'1154
'1073
'1078
'1083
'1098
'lIDO
'1101
'0580
*0583
'1381
*1392
'0030

0828
0859
0869
0862
0844
0786
0813
0757
0766
0770
0775
0778
0791
0797
0807
0765
0930
0925
1384
1179
1101
0611
0679
0700
0708
0702
0639
0617
0633
0636
0662
0665
0663
0666
0691
0136
0293
1386

0799
0769 1311 13Z5
0936 0939
0927
1181
1387

0713

0774 1210 1218 1245 1419

1152 1183
1076
1079
1095
1097
1110
1313
0581

1388
0100
0314
0481
0929
1106
0001 '0031 0229
0255
0408
0522
0554
0675
0707
0827
1032
1244
0005 '0033 0363

0101
0320
0490
0937
1112
0231
0256
0441
0524
0555
0676
0709
0831
1033
1247
0375

0151
0360
0491
0960
1124
0234
0259
0443
0526
0631
0678
0710
0833
1042
1342
0465

0206
0368
0556
0965
1199
0237
0262
0477
0529
0634
0681
0711
0834
1046
1345
0474

0207
0374
0615
1020
1221
0?41
0264
0492
0533
0648
0683
0744
0836
1054
1519
0482

0224
0386
0658
1023
1242
0244
0317
0509
0536
0650
0687
0787
0896
1086
1558
0484

0276
0388
0668
1036
1249
0248
0319
0512
0546
0651
0688
0788
0932
1108

0279
0425
0735
1053
1338
0249
0323
0515
0548
0653
0689
0789
0940
1114

0282
0438 0471 0475
0742 0782 0898
1074 1088 1103
1341 15171553
0254
0325 0369 0405
0518 0519 0521
0549 0551 0553
0669 0671 0673
0695 0697 0704
0822 0824 0825
0985 0991 1031
112611971219

0609 0637 0659

362

09280938
1327 1339
0230 0232
0416 0421
0547 0550
0696 0698
1569
0376
0377 0381
0362 0370
0365
0389
0380 0384
0283 0539

FPACC2MN

0006 *0034

FPMULTI
FPMULT2
FPMULT3
FPMULT4
FPMULT5
FPMULT6
FPNORM
FPNORMI
FPNORM2
FPNORM3
FPNORM4
GETFPll
GETFP12
GETFP21
GETFP22
GETFPACI
GETFPAC2

C1Cl "0381
C1C8 *0385
C1CF "0388
CIAE '*0371
Cl BC *0378
Cl05 *0391
C16l *0313
CI6D *0319
C16F *0320
C17e "0326
C17E *0328
C850 "1516
C85F *1517
C873 *1530
C875 *1531
C850 *1509
C866 "1523

GETPI
MANTSGNI

C82B "1431
0004 "0032 0102
0623
1128
1349
0009 *0035 0372
1270
C80F *1396 1389
C545 "0916 0763
0006 *0043 1080
C155 *0303 0106
0219
C15F "0310 0305
C7E3 *1367 1280
0002 "0039 0378
C541 *0913 0767
C7E7 "1368 1432
C831 "1436 1417
C839 "1454 0097
1416
C843 *1465 0134
1420
C885 "1557 1555
C895 *1568 1566
C87C *1552
C88C *1563 1462
0001 "0090 0187
C823 "1425
C68F *1195 1149
C6BC "1218 1226
C6D3 *1230 1259
C713 *1262 1277
C6BF *1219 1216
C73F *1283 1279
C74E *1289 1282
C689 *1217 1212
C7C3 *1353 1203
C589 *0984
C595 *0992 0987
C59F *0998 0996
0007 *0044 1391

MANTSGN2
MAXNUM
N9999999
NSQRTERR
NUMERIC
NUMERICI
ONE
OVFERR
P9999999
PI
PIOV180
PSHFPAC2
PULFPAC2
PUTFPll
PUTFP21
PUTFPACI
PUTFPAC2
PWRIOEXP
RA020EG
SINCOS
SINCOSI
S I NCOS2
SINCOS3
SINCOS4
SINCOS5
SINCOS6
SINCOS7
SINFACT
SINT2FLT
SINTFLTI
S I NTFL T2
TAN90ERR

0324
0316
0321
1514
1511
1528
1525
1390
0288
1418

1092
1340
0239
0426
0632
0931

1100
1531
0243
0476
0635
0941

1111
1564
0261
0496
0649
1113

1125 1272 1286 1309 1310 1324
0263
0507
0652
1127

0402
0510
0655
1274

0414
0513
0656
1288

0415
0516 0520 0523
0657 0674 0677
1343 1344 1533

0966

0318

1433
0292 0764 0768 0773 0780 1232 1281 1305
1469
0113
0746
1153
',512
0.• 78
1,'84

0371
0756
1182
1515
0503
1347

0373
0758
1201
1554
0583
1348

0479 0502 0505 0538 0622
0894 0924 0934 0997 1026 1047 1078
1223 ,1240 1251 1306 1322 1329 1346
0585 0621 0926 0935 1129
1526 1529 1565

0116 0126 0143 0154 0162 0174 0184 0190
0307
0558 0640

0359 0464 0620 0748 1083 1143 1169 1382
1426
0298 0391 0469 0646 0892 1118 1155 1392

0192 0195 0199 0202 0280 0284 0289 0294
1176

363

TFR1T02
TNREE60
TOlGSMER
UINT2FLT
UINTFLTI
UllJl.T
UllJl.f1
UllJl.T2
IllULT3
IllULT4
UNFEIR

C646
e7EB
0005
e577
C580
C1D9
C1E3
C1F4
C217
C234
0003

*1123
*1369
·0042
*0959
·0964
*0395
*0402
*0411
*0426
*0439
*0040

1091 1104 1209 1215 1383
1304
1049
0992
0962
0387
0418
0404
0420
0427 0434
0382 0541 0664

364

AN991
Using the Serial Peripheral Interface to
Communicate Between Multiple Microcomputers
As the complexity of user applications increases, many designers find themselves needing multiple microprocessors to
provide necessary functionality in a circuit. Communication
between multiple processors can often be difficult, especially
when differing processors are used. A possible solution to this
problem is usage of the serial peripheral interface (SPH, an
interface intended for communication between integrated circuits on the same printed wire board. The MC68HC06C4 is
one of the first single-chip microcomputers to incorporate SPI
into hardware. One advantage of the SPI is that it can be
provided in software, allowing communication between two
microcomputers where one has SPl hardware and one does
not. Special interfacing is necessary when using the hardware
SPI to communicate with a microcomputer that does not include SPI hardware. This interface can be illustrated with a
circuit used to display either temperature or time, that incor·
porates both a MC68HC06C4 and a MC68706R3. The
MC68HC06C4 monitors inputs from a keypad and controls the
SPI data exchange, while the MC68706R3 determines temperature by performing an analog-to-digital conversion on inputs from a temperature sensor and controls the LED display.
Communication between the microcomputers is handled via
SPI, with the MC68HC06C4 handling exchanges in hardware,
and the MC68706R3 handling them in software.
Usage of software SPI can be expanded to include circuits
where the single-chip implementing the SPI in software controls the data exchange, and those in which neither singlechip has hardware SPI capability. Minor modifications to the
SPI code are necessary when data exchanges are controlled
by the software.
Debugging designs including multiple processors can often
be confusing. Some of the confusion can be alleviated by
careful planning of both the physical debugging environment
and the order in which software is checked.

SIGNALS
The MOSI pin is configured as a data output on the master
and a data input on the slave. This pin is used to transfer data
serially from the master to a slave, in this case the
MC68HC06C4 to the MC68706R3. Data is transferred most
significent bit first.
Data transfer from slave to master is carried out across the
MISO, master-in/slave-out, line. The MISO pin is configured
as an input on the master device and an output on the slave
device. As with data transfers across the MOSI line, data is
transmitted most significant bit first.
All data transfers are synchronized by the serial clock. One
bit of data is transferred every clock pulse, and one byte can
be exchanged in eight clock cycles. Since the serial clock is
generated by tha master, it is an input on the slave. The serial
clock is derived from the master's intemal processor clock,
and clock rate is selected by setting bits 0 and 1 of the serial
peripheral control register to choose one of four divide-by
values. Values for the MCUs crystal oscillators and the SPI
divide-by must be chosen so that the SPI clock is no faster
than the intemal processor clock on the slave.
The last of the four SPI signals is the slave select (551.
Slave select is an active low signal, and the 55 pin is a fixed
input which is used to enable a slave to receive data. A master
will become a slave when it detects a low level on its 55 line.
In this design, the MC68HC06C4 is always the master, so its
55 line is tied to VDD through a pull-up resistor.

REGISTERS
Three registers unique to the serial peripheral interface provide control, status, and date storage.
The Serial Peripheral Control Register (SPCRI, shown below, provides control for the SPI.

SERIAL PERIPHERAL INTERFACE
7

Communication between the two processors is handled via
the serial peripheral interface (SPH. Every SPI system consists
of one master and one or more slaves, where a master is
defined as the microcomputer that provides the SPI clock,
and a slave is any integrated circuit that receives the SPI clock
from the master. It is possible to have a system where more
than one IC can be master, but there can only be one master
at any given time. In this design, the MC68HC06C4 is the
master and the MC68706R3 is the slave. Four basic signals,
master-out/slave-in (MaSH, master-in/slave-out (MISOI, serial clock (SCKI, and slave select (551, are needed for an SPI.
These four signals are provided on the MC68HC06C4 on port
D, pins 2-5.

tOA
RESET

6

43210

I SPiE I SPE I - IMSTR ICPoll CPHA ISPA 1ISPRO ISPCR
0

000

SPIE- Serial Peripheral Interrupt Enable
0= SPIF interrupts disabled
1 = SPI interrupt if SPIF= 1
SPE-Serial Peripheral System Enable
0= SPI system off
1 = SPI system on
MSTR-Master Mode Select
0= Slave mode
1 = Master mode

365

U

U

Bl~

______________________________

~rB

SCK

SCK

SCK
(CPOL = 1. CPHA = D)

SCK

ZZA

MS8

4

LSB

I

VI

I
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)

Figure 1. Data Clock nming Diagram

CPOL-Ciock Polarity
When the clock polarity bit is cleared and data is not being
transferred. a steady stata low value is produced at the
SCK pin of the master device. Conversely, if this bit is
ist, the SCK pin will idle high. This bit is also used in
conjunction with the clock phase control bit to produce
the desired clock-data relationship between master and
slave. See Figure 1.

Data for the SPI is transmitted and received via the Serial
Peripheral Data Register (SPORI. A data transfer is initiated
by the master writing to its SPOR. If the master is sending
data to a slave, it first loads the data into the SPOR and then
transfers it to the slave. When reading data, the data bits are
gathered in the SPOR and then the complete byte can be
accessed by reading the SPOR.

CPHA-Ciock Phase
The clock phase bit, in conjunction with the CPOL bit,
controls the clock-data relationship between master and
slave. The CPOL bit can be thought of as simply inserting
an inverter in series with the SCK line. The CPHA bit
selects one of two fundamentally different clocking protocols. When CPHA 0, the shift clock is the OR of SCK
with SS. As soon as SS goes low the transaction begins
and the first edge on SCK involves the first data sample.
When CPHA = I, the SS pin may be thought of as a simple
output enable control. Refer to Figure 1.

DEMONSTRATION BOARD DESCRIPTION
A keypad input from the user is used to choose the output
display function. The MC68HC05C4 monitors the keypad, decodes any valid inputs, and sends the data to the MC68706R3.
If the user has requested a temperature display, the
MC68706R3 sends a binary value of temperature in degrees
farenheit to the MC68HC05C4, where the velue is converted
to a celcius binary coded decimal value and returned to the
MC68706R3 to be displayed. The LEOs are common anode
displays and are driven directly off of port B on the MC68706R3.
If the user desires the circuit to function as a real-time clock,
a starting time must be entered and transmitted from the
MC68HC06C4 to the MC68706R3. Once the clock has been
initialized, the MC68706R3 updates the clock every minute.
Clock values are stored in memory, and when the circuit is
functioning as a thermometer, the values in memory are updated as required to maintain clock accuracy.

=

SPRI and SPRO-SPI Clock Rate Selects
These two serial peripheral rate bits select one of four
baud rates (Table 11 to be used as SCK if the device is a
master; however, they have no effect in the slave mode.
Tabla 1. Serial Peripheral
Rata Selection

SPRl

SPRO

Internel Proceuor
Clcick Divide By

0

0

2

0

1

4

1

0

16

1

1

32

USING THE AID CONVERTOR TO
MONITOR TEMPERATURE
Temperature monitoring is performed by the Motorola
MTS102 silicon temperature sensor and the LM358 Dual LowPower Operational Amplifier, as shown in the schematic in

366

the three function keys, display tempereture, eat time, or display time, are preseed, the MC68HC05C4, as master, sends
the MC68705R3 an interrupt on the MC88706R3's INT pin.
The MC68HC05C4 writes the kay value to ita serial peripheral
data register, thereby initieting the SPI. It then waits for the
SPIF bit to go high and returns to scanning the keypad.
At the same time the MC68HC05C4 is writing to its SPDR,
the MC68705R3 sets a bit counter to eight and waits for the
first SCK from the MC68HC05C4. After each clock pulse, the
MC68705R3 checks the status of the data bit, sets the carry
bit equal to the data bit, and rotates the carry bit left into a
result register. The bit counter is decremented, compared to
zero, and if not zero, the MC88706R3 waits for the next clock
pulse and repeats the cycle.
To ensure proper data transfers, the internal processor clock
of the MC68705R3 must be suffICiently faster than the SPI
clock of the MC68HC05C4 to allow the MC68705R3 time to
complete this routine before the MC68HC05C4 can send another bit. This requires the user to first write the code to handle
the software SPI, count machine cycles, and then choose MCU
oscillator values that allow the additional machine cycles required in a software SPI to be completed before the master
can send another clock pulse to the slave.
For example, consider the following piece of code for the
MC68705R3. a slave receiving data from the master.

Figure 2. Variations in the beae-emitter voltage of the Motorola
MTS102 silicon temper8tUre seneor are monitored by the
MC88706R3, which converts these anelog inputs to equivalent
digital values in degrees ferenheit. The sensor voltage is buffered, inverted, and amplified by a dual differential amplifier
before entering the AID converter. An amplifier gain of 16 is
ueed, resulting in 2O-millivolt steps per degree farenheit. Using
a V CC of 5 volts, the maximum differential amplifier output is
3.8 volts, resulting ;n a tempereture sensing range from - 40
degrees to + 140 degrees ferenheit.
The output from the differential amplifier is connected to
the AID converter on the MC68706R3. A block diagram of
the successive approximation .A/D converter is shown in Figure 3. Provision is mada for four separate external inputs and
four internal analog channels.
Two different registers associated with the converter control
channel selection, initiate a conversion, and store the result
of a completed conversion. Both the external and the internel
input channels are chosen by setting the lower 3 bits of the
AID Control Register (ACR). The internal input channels are
connected to the VRHIVRL resistor chain and may be ueed
for calibration purposes.
The converter operates continuously, requiring 30 machine
cycles per conversion. Upon completion of a conversion, the
digital value of the analog input is placed in the AID result
register (ARR) and the conversion complete flag, bit 7 of the
ACR, is set. Another sample of the selected input is taken,
and a new conversion is started.
Conversions are performed internally in hardware by a simple
bisection algorithm. The 01 A converter (DAC) is initially set
to $80, the midpoint of the available conversion range. This
value is compared with the input value and, if the input value
is larger., $80 becomes the new minimum conversion value
and the DAC is once again set to the midpoint of the conversion
range, which is now $CO. If the input value is less than $80,
$80 becomes the maximum conversion value and the DAC is
set to the midpoint of the new conversion range, in this case
$40. This process is repeated until all eight bits of the conversion are detennined.
Quantizing errors are reduced to + 1/2 LSB, rather than
+0, -1 LSB, through usage of a built-in 1/2 LSB offset.
Ignoring errors, the transition between 00 and 01-will occur at
1/2 LSB above the voltage referance low, and the transition
between $FE and $FF will occur 1-1/2 LSBs below voltage
reference high.
The AID convertor returns a value of $30 when given an
input of zero degrees farenheit, so $30 must be subtracted
from the result before converting to celcius. This offset must
also be considered when calibrating the sensor. Calibration of
the temperature sensor can be perfonned by adjusting the
variable resistor to produce a display of $00 after a piece of
ice has been placed on the temperature sensor for approximately one minute. A 00 display results from a value of $50
in the ARR, so the variable resistor should be adjusted until
this value is reached.

PORTC pin 5
PORTC pin 4

DATA IN
SCK

Cye....

Inetructlon

2
5

10
10
6
6
4

NXT
STR

LDA
STA
BRSET
BRSET
ROL
DEC
BNE

1$08
BITCT
4. PORTC.
5.PORTC.STR
RESULT
BITCT
NXT

*

Set bit counter
Wait for clock transition
Check data status
Stora in rasult
Check for end of byte
Get next bit

43
Execution of this code requires 43 machine cycles. The maximum oscillator speed for an MC68705R3 is 1 MHz, requiring
an SPI clock no greater than 1/43 MHz. One way of obtaining
this rate for the SPI clock is to run the MC68HC05C4 at 0.5
MHz and choose a divide-by 32 to generate the SPI clock.
If the user has selected a temperature display, it is necessary
for the MC68705R3, as a slave, to send data to the
MC68HC05C4 master. When the MC68705R3 is ready to send
data, it interrupts the MC68HC05C4 via the MC68HC05C4's
IRQ line. The MC68HC05C4 then writes to its serial peripheral
data register to initiate the transfer and shifts in data bits sent
from the MC68705R3 until the SPIF bit goes high. While the
MC68HC05C4 is writing to its SPDR, the MC68705R3 program
is setting a bit counter to 8. When it detects a clock pulse on
the SCK pin, the data register is rotated left one bit, placing
the MSB in the carry. The MOSI pin is then eat equal to the
carry bit, the bit counter is decremented and, if it is greater
than zero, the process is repeated.

COMMUNICATION CONSIDERATIONS
In this application, an SPI read or write is initiated via an
interrupt from the MCU desiring to write data. When any of

367

MC63HC05C4

rl I
_

Voo
39

II

-

T
Vee

12

7

PA3 8

8

10

PA2 9
10
PAl

9

11

6

PCI-.....2

i1ili

28 PCO

IIOSI

Vss

Yee

J
~

"~

20
1

24

Yee
VRH

VAl
Vss

MlSO

7

XTAl

----

----

,.-A
.
----

---

----

_._--

33

~
~

2N2907

e~

Vee

~~
.".

2

MANSI

14

vce~'4

Vpp RESET

e8 ~

e5~

~

AIiO

-

e3 12

co

so

9
25

----

81

28

F

G

111

100

2

----

7
E

D e 8 A
8 12 13 1

G

f

E D C B A

54

E D e

1

29
30

H2

Vee

240 k "
4

nnt ..

,_L-

8

7~h

R3
15 k III

1

U2e

0058

Yee

-

47k

+ 3

n=:.. 1...

50 k
10 TURN

Figure 2. Serial Paripheral Interface Demonstration Schematic

B A

G F

I

27

85
88 31

----

---G F

83 28

3 00

----

e4 13

B2

8 TIIR

~-A.

LED
DISI'lAYS
ellllllQN
ANODE

C2 11

4.Hr
Vee

8

12

CliO

III'

r~7~::
""

5

5

~O

CD

9

~t2!-vee
SCK

(,0)
CJ)

15 k 15 k 15 k

4 6

PA4 7

PAD

4.7 k

TO P1N 16.

15 k

10

PA5 6
asc2

Vss
4
1

PA6 5
10M

lMHzO

l30F1

~Voo

PA7 4

asci

~

E D C B A

8

O/A
CONTROL
LII6IC

15 k{J tTYPl

COUNT

POD/AND
I.(JF·8
SELECT

POI/ANI
P02/AN2

MULTIPlEXER

P03/AN3

8

A/D
CONTROL
REGISTER

AID
RESULT

'-'
C

~-L

__

~~

__

~~~

__

~~

'----'-_-'---'-_-'----'-_-'----'-_-' REGISTER

Figure 3. AID Block Dlegram

ADDITIONAL USES OF SPI
Many variations of this usage of the SPI are possible. The
three possibilities are hardware SPI at both master and slave,
software SPI at the master and hardware at the slave, and
software SPI at both master and slave. Table 1 shows the
various MCUs that have SPI implemented in hardware.
SPI is fairly straightforward in a circuit where both master
and slave have hardware SPI capability. In this case, the MCUs
are connected as shown in f'lgure 4. Figure 4a illustrates a
single master system, and Figure 4b shows a system where
either MCU can be system master. When both master and
slave have SPI capability in hardware, data transfers can be
.handled full duplex. For a single master system, both master
and slave write the data to be transferred to their respective
serial peripheral data registers. A data transfer is initiated when
the master writes to its serial peripheral data register. A slave
device cen shift data at a maximum rate equal to the CPU
clock, so clock values must be chosen that allow the slave to
transfer data at a rate equal to the master's transfer rate. In
a multiple master system, the master must pull the slave's SS
line low prior to writing to its serial peripheral data register
and initiatirill the transfer.

PROGRAMMING A MASTER FOR SOFJWARE SPI

One possible software implementation for a write from the
master to the slave is shown below.
DATA OUT

scI(

PORTC pin 0
PORTC pin 1
lOX 1$08
lOA DATA
RPT ROLA
BCS SET
BClR D,PORTC
ClK BSET I,PORTC
BClR I,PORTC
DECX
BNE RPT
SET

BSET O,PORTC
BRA ClK

Bit counter
Put data in register A
Shift a data bit into carry
Check for a 1
Set data out line to 0
Toggle clock pin
Check for end of byte
If not, repeat
Set data out line to 1
Go to clock

Full duplex operation requires a second data line. One port
pin is then devoted to data-out and one to date-in. Data transfer
from slave to master is accomplished immediately before the
SCK pin is toggled. The state of the data-in pin is tested, and
the carry is then set equal to the data-in pin. This value is then
rotated in to a result register. The modified code is shown
below.
DATA OUT
SCK
DATA IN

When the master in an SPI system does not have hardware
'SPI cepabilities, the resulting system is quite different. An SPI
system with a master providing th8 SPI in software is shown
in Figure 5. This system only requires two lines between the
microcomputers; data and clock. A slave select line can be
added for use with multiple slaves. If operated with one data
line, the SPI will function half-duplex only. Data is stored in
register, rotated left one bit at a time, and a port pin is set
equal to the data bit. The master then provides the serial clock
by toggling a different port pin. A bit counter must also be
used to count the eight bits in. the byte. Bit manipulation
instructions are very us8tu1 for implementing SPI in software.

a

PORTC pin 0
PORTC pin 1
PORTC pin 2
lOX 1$08
lOA DATA
BClR I,PORTC
RPT ROLA
BCS SET
BClR D,PORTC
BSET I, PORTC
DIN BRClR3,PORTC,ClK
ClK ROl DATAIN

SET

369

Bit counter
Put data in register A
Clear clock pin
Shift a data bit Into carry
Check for a 1
Set data out line to 0
Set clock pin
Check _
of data
Rotate input data one bit

DECX
BNE RPT

Check for end of byte
If not, repeat

BSET D,PORTC
BRA DIN

Set data out line to 1
Go to data input

CLOCK

SPt

DATA OUT

SPt OUTPUT
PERl'llERAL IC

DATA II
MC8811C05C4

SPt

t--

MASTER

PORT

I

SLAVE SElECT 1
SlAVE SElECT 2
SlAVE SELECT 3

I

SPlINPUT
PERIPHERAL IC

..
ANOTHER IICU
SPt SLAVE

SlAVE PERIPHERAL PROCESSOR MAY IE
ANOT HER IICII8HC04C,
4 OR PERHAPS }
AN 118804 FAMILY SlNBlE-CIlP IICU

h>
V'~

~

~

Flilure .... Slnlll. M••t.r SPI
CLOCK
DATA
SPI

¢)

MC88I1C05C4
SPI
MASTERISlAVE

SPI

DATA
SLAVESEL

SlAVE SEL

-

rr

PORT
SYNC

r----

IIC88HC05C4
SPI
MASTER/SlAVE

PORT

SPI
SLAVE S£L

lle8811C06C4

f-PORT

Flilur. 4b. Multlpl. Mut.r SPI

CLOCK
SPI
MASTER IICU

SPt
MASTERISlAVE

OTHER PROCESSORS MAY IE
'----<
USED. SOME FOIITIICOMIN6
118801,118805, AND 118804
FAIlILY VERSIONS HAVE SPt FACIUTIES.

DATA

Flilur. 6. Software SPI

370

SPI SLAVE
lieU

One of the easiest methods to debug a circuit of this type
is to use two emulator stations, comp/ata with separats ter-

PROGRAMMING A SLAVE FOR SOFTWARE SPI
If the eI8ve in the systam is a MCU with hardware SPI
capabHity, the data trensfer will happen automatically, ona bit
par clock pu.... If the slave is a MCU that does not have SPI
implemented in hardware, a read requires the following actions. A bit countar is eat to aight, the slave polls its SCK pin
waiting for a clock trensition, once it parcaives a clock it checks
its data-in pin, sets the carry equal to the data and rotataB the
carry into a results register. One possible code implemantation
is shown in the previous timing e x a m p l e . ,
Converting this to full duplex oparation requires the addition
of a write from eI8ve to mastar. The slave rolls a data register
to placa the data bit to be sant into the carry, and the dataout pin i8 eat equal to the carry. These actions occur prior to
the read of data from the master. With these modifications,
the code looks as shown below.
DATA OUT
DATA IN
SCK

minals. Any emulators can be used, but user confusion is
reduced If the emulators have similar commanda and syntax.
Physical separetion also helps reduce confusion. It is s0mewhat eesier to keep track of the concurrent oparations if one
side of the prototype board is devoted to each single-chip and
the majority of paripherals they each must interface with, and
the emulator for that microcomputer is placed to that side of
the printed circuit board.
Before starting simultaneous debugging, it is best to individually debug the code for each microcomputer wheraver
possible. Once it becornas necessary for the microcomputers
to communicate with one another, halt ona of the microcomputers anytime they ara not actually tllking and work with the
remsining microcomputer. As the debugging progresses, keep
in mind that an error in the function of one single-chip does
not necessarily indicate an error in the corresponding code for
that single-chip, but rather, the error may have been caused
by an incorrect or unintended transmission from the· other
single-chip.
Although the aforemantioned suggestions reduce debugging problems, soma will remain. Long pariods of debug can
result in an obscuring of the separation of the functions of the
two programs. It helps to teke pariodic breaks to gat away
from the system and clear the thought processes. Expect to
occasionally be confused, be willing to ratrace sections of code
multiple numbers of times, and the debugging will proceed
fairly smoothly.

PORTC pin 6
PORTC pin 5
PORTC piri4

LDA
STA
AGN BRSET
ROL
BCS
BCLR
BRCLR
BRSET
STR ROL
DEC
BNE

1$08

BITCT
4,PORTC,
RESl
SETl
6.PORTC
4,PORTC,
5,PORTC,STR
RESULT
BITCT
AGN

*

*

Set bit counter
Wait for clock
Shift data to send
Check data status
If 0, clear data out
Wait for clock transition
Check input data status
Stors in rssult
Check for end of byte

CONCLUSION
DEBUGGING TIPS

The Serial Peripheral Interface cen be used as a tool to
innerconnect to MCU with various other MCUs or paripherals,
and can be used with any microcomputer. A spacial case
occurs when one, or more, of the MCUs in a circuit do not
have SPI capsbility in hardware. In this case, a simple software
routine can be written to perform the SPI. Used in this manner,
the SPI eliminatas the need for costly, inconvenient parallel
expansion buses and Universal Asynchronous Receiver ITransmitters (UARTs) and simplifies the design effort.

Debugging a circuit containing two microcomputers presenti various problems not evidant when working with a single
microcomputer circuit. The first problem is simultaneously providing emulation for both microcomputers. Once emulation
capability is arranged, the designer needs to keep track of the
progress of each single-chip, and monitor how the actions of
one affects the actions of the other.

371

0001
0002
0003
0004
0005
0006
0007
00 De
0009
0010
0011
0012
0013
0014
0015
0016
0017
DOle
0019
0020
0021
0022
0023
0024
0025
0026
0027
002e
0029
0030
0031
0032
0033
0034
0035
0036
0037
003e
0039
0040
0041
0042
0043
0044
0045
0046
0047
004e
0049
0050
0051
0052
0053
0054
DOSS
005&
0057
Dose
0059
0060
0061
0062

nam spicnt

********** REGISTER ADDRESS DEFINITION ***********
pOl"ta
POl"tc
pOl"td
ddl"a
ddl"c
SPCI"
SPSI"
spdl"
tcr

0000
0002
0003
0004
0006
OOOA
OOOB
00 DC
0012

equ
equ
equ
equ
equ
equ
equ
equ
equ

0

Z
3

4
6
SOa
SOb
SOc
S12

01"9 SbO

OOBO

I"wno
tmpa
dctl"
ctl
base
Isb
msb

OOBO
OOBl
00B2
00£\3
00B4
OOBe
00B9

I"mb
rmb
I"mb
I"mb
I"mb
I"mb
I"mb

1
1

1
1
4

01"9

0020

1
1

S20

******* KEYPAD LOOKUP TABLE ********
kypd

0020
0020
0021
0022
0023
0024
0025
0026
0027
002e
0029
002A
002B
002C
0020
002E
002F

07
04
01
00
De
05
02
OA
09
06
03
DE
00
DC
OF
DB

*

fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb
fcb

S07
S04
SOl
SOD
soe
S05
S02
SOa
S09
S06
S03
SOe
SOd
SOc
SOt
SOb

d i lip. temp.

set time
am
pm
disp. time
blank

01"9 S100 pl"091"am stal"t

0100
0100
0101
0103
010S
0107
0109
010B
0100
OlOF
0111
0113

equ

9C
3F
AE
BF
AE
BF
BF
3F
A6
B7
9B

stal"t
12
7B
02
7F
OA
06
00
FO
04

I"Sp
cll"
Idx
stx
Idx
stx
stx
ell"
Ida
sta
sel

372

tCI"
#$7b
pOl"tc
#.7f
SpCI"
ddl"c
pOl"ta
#$fO
ddl"a

mask timel" intel"rupts
initial ize port c
set spi cant. re9.
set cO as output
clear keypad inputs
.et up port a
a7-.4 out . • • 0-.3 in

0063

0064
J065
0066
0067
0068
0069
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
00B5
0086
D087
0088
8089
0090
D091
0092
0093
0094
0095
0096
0097
DD9B
OD99
01DD
Dl0l
D1D2
01D3
0104
D1D5
01D6
D1D7
0108
0109
OllO
Dl11
0112
0113
::J114
0115
J116
Dl17
0118
G119
G120

1111 check

0114
0117
0119
011B
0110
011F
0121
0123
0125
0127

CO
Al
27
Al
27
Al
27
Al
27
20

01 67
OA
DE
DE
2B
OF
06
DB
02
EB

key

keypad 1111
jsr
cmp
beq
cmp
beq
cmp
beq
cmp
beq
bra

keypad
#$Oa
dtmp
#SOe
sttm
#SOt
dtmp
UOb
dtmp
key

check for disp.

temp

check tor set time
check tor disp.

time

check for disp.

sec

wait for next input

1111 display temp 1111

0129
012B
012E
0130
0132

11
CO
Al
27
20

02
01 59
OA
02
EO

0134 9A
0135 20 DO

dtmp

bclr O.portc send interrupt for spi
jsr spiwr
send byte
cmp #$Oa
check for disp. temp.
beq clr
bra key

clr

eli
bra key

*11 set

0137
013A
013C
013E
0140
0142
0144
0146
0148
D14A
014C
014F
0151
D153
D155
D157

CD
Al
27
Al
27
Al
27
A1
27
11
CD
Al
27
Al
27
2D

01 67
OA
F9
DB
F5
DE
Fl
OF
ED
D2
Dl 59
DC
C1
DO
BO
DE

nudig

sttm

1111 spi

0159
0159
015B
015E
0160

spiwr
B7 DC
OF DB FO
10 D2
81

spiflg
1111 spi

0161
D161 BF DC
0163 DF DB FD
0166 Bl

sp i rd
rdend

time 1111
jsr keypad
cmp #$Oa
beq nudig
cmp UOb
beq nudig
cmp #SOe
ceq nudig
cmp #$Df
beq nudig
bclr D.portc
jsr spiwr
cmp #$Oc
beq key
cmp UOd
beq key
bra nudig

look for va lid digit

send into for
send value
check for pm
yes. wait tor
check for am
yes, wait for
get next time

write subroutine

spi
next

input

next input
digit

III!

equ II
put data in data reg.
sta spdr
brclr 7.spsr.1I
wait for end of byte
bset O.portc
rts
done
read subroutine 1111
equ I!
stx spdr
initiate transfer
brclr 7.spsr.1! wait for end ot byte
rts

373

0121
[J122
0123
0124
0125
0126
0127
0128
0129
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
0140
0141
0142
0143
0144
0145
0146
0147
0148
0.149
0150
0151
0152
0153
0154
0155
01!::6
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
8169
0170
0171
0172
0173
0174
::1175
0176
0177
0178
0179
::180
J181
0182

** keypad scannins routine **
0167

keypad

equ *

** 32 msec delay **
0167
0169
0168
0160
016E
0170
0172
.0174
0175
0177
0179
0178
0170
017F
0181
0183
0184
0186
0188

A6
87
A6
4A
26
3A
26
5F
Ab
87
S6
A4
A1
26
37
5C
A3
23
20

20
83
32

wtlp
otlp
inlp

FO
83
F7
80
00
00
OF
00
09
00

nxtr

Ida #$20
sta ctl
Ida #$32
dec a
dec.
bne inlp
de.c ctl
bne otlp
clrx
Ida #$80
sta porta
Ida porta
and #$Ot
cmp #$00
bne debnc
asr porta
inc:x

03
Fl
DO

inval

cpx #$03
bls nxtr
bra wtlp

set up outer loop
counter
set up inner loop
inner loop
when 0,
decrement outer loop
set UP row counter
check tirst rOw
check tor key
mask upper nibble
look tor zero
branch it have a key
try next row
decrement rOw counter
check tor zerO
test next raw
nO key pressed

** debounce key input **
018A
018C
018E
0190
0191
0193
0195
0197
0199

87
8F
A6
4A
26
86
A4
81
26

81
80
FF

debnc
loop

FO
00
OF
81
CC

sta tmpa
stx rwno
Ida #$tf
deca
bne loop
Ida porta
and #$Of
cmp tmpa
bne wtlp

save value
save rOw number
set UP delay
wait
check row asain
mask upper nibble
check tor same key
return it i nval id

** wait tor key release **
0198
0190
019F
01Al

86
A4
Al
26

DO
OF
00
F8

wtr

Ida
and
cmp
bne

porta
#$Ot
#$00
wtr

check value
mask upper nibble
look tor zerO
wait tor release

** decode key value **
01A3
01A5
01A6
01A7
01A9
01AA
01AC
01AO
01AE
OlAF
0181
0182
C184
CIB6

86
SF
44
25
5C
20
58
58
9F
88
97
E6

81
nxtc
03

restore value
set up column ctr.
shift columns
branch it have column

inc:x

FA
col
80
20

87 81

81

Ida tmpa
clrx
Isra
bcs col
bra nxtc
Islx
Islx
txa
add rwno
tax
Ida kypd,x
sta tmpa
rts

374

try next column
x=4*col. nO.
place x in a
key value =4*col + row
place a in x
convert to decimal

0183
0184
0185
0186
0187
0188
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0226
0227
0228
0229
0230
0231
0232
0233
0234
0235
0236
0237
[J238
0239
0240
0241
0242
0243
0244

****** t.emperat.ure conversion routine ********
*
* farenheit. value is rec:eived from 705r3 i a
* spi and rec:eived in t.he a register. the value
* is c:onverted t.o c:elc:ius and the leftmost.
* led is blanked.
',J

01B7
01B7
01BA
01BC
01BE
01CO
01Cl
01C3

r3int
CO
B6
AD
24
40
AE
BF

01 61
DC
20
05
OA
B6

equ *
jsr spird
Ida spcr
sub #$20
bhs conv
nega
Idx #$Oa
stx base+2

read value
transter value to register
subtrac:t 32
if pos. convert
negate
I_I

pattern

*** temperature conversion ***
** a 16-bit multiply by 5 is pertormed on the
** value rec:eived from the r3. this number
**. is then divided by 9.
01C5
01C7
01C9
01CB
01CC
01CE
01CF
0101
0103
0105
0107
0109
o10B
010C
010E
OlEO
01E2
olE4
olE6
olE8
OlEA
olEC
olEE

3F
3F
B7
48
39
48
39
BB
24
3C
3F
B7
98
3C
B7
B6
A2
B7
B6
AD
24
3D
26

B9
B8
B8

c:onv

B9
B9
B8
02
B9
B2
B8

div

AB
Ai
22
3A
96

c:lear

counters

multiply by 2
load overflow into msb
multipiy by 2
load overfiow into msb
a c:ontains value x5
it overfiow,

inc: msb

cit:

B2
B8
B9
00
B9
B8
09
FO
B9
EC

nxt9

09
04
02
B2
92

01FA AE DB
olFC 9F B7

inc

sta
Ida
sbc:
sta
Ida
sub
bc:c:
tst
bne

***
***
olFO
01F2
01F4
01F6
olFB

c:lr msb
c:lr Isb
sta Isb
Isla
rol msb
Isla
rol msb
add Isb
bc:c: div
inc msb
c:lr dc:tr
sta Isb

done
pos

dc:tr
Isb
msb
#$00
msb
Isb
#$09
nxt9
msb
nxt9

subtrac:t borrow trom msb
c:ount tac:tors ot 9
it nO borrow, repeat
c:hec:k tor end
repeat it not end
it borrow,

end ot divide, add last 9 bac:k
c:hec:k remainder tor rounding
add
c:mp
bhi
dec:
Ida

#$09
#$04
done
dc:tr
dc:t.r

Idx #$ob
stx base+3

in and

tind remainder
it greater
than 4, round up

blank pattern
blank most s i g. digit

**** convert binary value to bc:d value ****
*
* the x regis~ers begins with t.he binary value
* and exits with zero. eac:h dig it. units, tens

375

D245
D246
D247
D248
D249
D25D
D251
D252
0253
D254
0255
D256
C257
0258
0259
D26D
0261
0262
0263
0264
0265
0266
0267
0268
0269
0270
0271
D272
D273
D274
0275
D276
C277
D278
D279
0280
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295

*
*
D1FE
D1FF
D2DD
C2C2
C2D4
02C5
02D7
D2C8
02D9
02D8
0200
D2DF
D211
0213
0215
0216
0218
021A
021C

97
4F
3F
3F
50
27
SA
4C
Ai
26
3C
86
Ai
27
4F
20
3F
3C
2C

87
86
27
E6
CO
5C
A3
26
80
A6
87
20

tax
c I ra
clr base+l
clr base+2
tstx
beq send
dec x

85
86
st
17

inca

cmp #$Ca
bne st
inc base+l
Ida base+l
cmp #$Oa
beq hund
clra
bra st
c"l r base+l
inc: base+2
bra zero

DA
F7
85
85
OA
03
zero

EC
85
86
F7

hund

*
*
*
D21E
D22D
0222
0224
0226
0229
022A
022C
022E
022F
0231
0233

and hund ... eds, is stored separately and checked
tor a value equal to lD.

84
86
08
84
01 59

send
nxtdg

sta
Ida
beq
Ida
Jsr

clear values
check tor end
i t complete, send to r3
decrement hex number
increment decimal number
equal to lC?
no, keep going
increment tens
test for 1D
it equa I, set hundreds
clear ones
count next 10
clear tens
increment hundreds

store Ones

base
base+2
blk
base,x
spiwr

start at base
send to r3

#$03
nxtdg

look for end
i t nO, next digit

inc:x

cpx
bne
rti
Ida
sta
bra

03
F6
08
86
EF

blk

#SOb
base+2
nX t dg

initialize interrupt vectors
org $ltt4

lFF4
01
01
01
01
01
01

into x

send a I I digits to 705r3 via spi
start by interrupting r3 and then
sequent i a I I y sending tour values

***
lFF4
1FF6
1FF8
1FFA
1FFC
1FFE

place a

00
DO
00
87
00
00

spivec
sc:ivec:

tmrvec:
i rqvec:

swivec
reset

tdb
fdb
tdb
tdb
tdb
tdb

376

start
start
start
r3int
start
start

***

0001
0002
0003
0004
0005
0006
0007
0006
0009
0010
0011
0012
0013
0014
0015
0016
0017
0016
0019
0020
0021
0022
0023
0024
0025
0026
0027
0026
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041
0042
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
DOSS
0056
0057
0056
0059
0060
0061
0062

nam r3disp

**********
0001
0002
0005
0006
0006
0009
OOOE
OOOF

equ
equ
equ
equ
equ
equ
equ
equ

portb
porte:
ddrb
ddre:
tdr
te:r
ae:r
arr

0040
wrdat
timtmp
e:t
e:tl
result
resl
bite:t
see:
segmnt
pm
base

1

2
5
6
6
9

14
15

rmb
rmb
rmb
rmb
rmb
rmb
rmb
rmb
rmb
rmb
rmb

1
1
1
1
1
1
1
1
1
1
4

org $80

0060

display

****

segtab equ
te:b
te:b
te:b
te:b
te:b
te:b
te:b
te:b
te:b
fe:b
te:b
te:b
te:b
fe:b

01
4F
12
06
4C
24
20
OF
00
DC
7E
7F
7F
18

0090

look-up table

*

".00000001
".01001111
1.00010010
1.00000110
".01001100
1.00100100
1.00100000
1.00001111
1.00000000
1.00001100
1.01111110
1.01111111
1.01111111
1.00011000

org .$90

***
0090
0090
0092
0095
0097
0099
009B
0090

*******

org $40

0040
0041
0042
0043
0044
0045
0046
0047
0046
0049
004A

0060
0080
0081
0082
0083
00840085
0086
0087
0088
0089
OOSA
008B
OOSC
0080

REGISTER DEFINITION

07
OF 38
FF
OS
08
4A
48

0
1
2
3
4
5
6
7
8
9
blank
pm
p

program start

in i t i a Ii ze variables

start
A6
C7
A6
B7
B7
B7
B7

equ
Ida
sta
Ida
sta
sta
sta
sta

****

***

*#$07
$t38
#$tt
ddrb
tdr
base
base+l

377

set MOR
set UP port b as output
set timer for prese:ale of 128
blank time display

00~3
00~4
OO~S

OD~~
00~7
OO~B

0069
0070
0071
0072
0073
0074
007S
0076
0077
007B
0079
OOBO
OOBl
00B2
00B3
00B4
OOBS
00B6
OOB?
OOBa
00B9
0090
0091
0092
0093
0.094
009S

00'1F
OOAl
00A3
OOAS
00A7
00A9
OOAB
OOAD
OOAF
OOBl
00B3
OOBS
00B7
DOB9
OOBB
OOBD
OOBF

B7 4C
B7 40
A~ EF
B7 02
B7 4B
A~ CF
B7 06
A6 OF
B7 09
3F 41
3F 47
3F 49
A6 3B
B7 42
A6 DB
B7 43
9A

*
OOCO
00C2
00C4
DOCS
00C7
ooca

AE FF
A~ FF
4A
26 FD
SA
2~ Fa

dlay

3F
B6
2A
B6
A2
B7

DE
DE
FC
OF
3D
4S
B~ 41
Al 07
26 E4

OODC
DODD
OODF
00E2

*
*

*
9B
lF 02
CD 01 18
AE 04

00E4 A6
B7
011~ 00E8 A~
0117 OOEA 4A
011a OOEB 2~
0119
0120
0121
0122
0123 ODED CD
0124 OOFO B~

DB
51
DE
timlp
FD

*
*
01 01
44

set. up cb-3.c6.c7 as outputs
unma.k timer int.errupt.
st.art. with time disp.
set. seconds t.o zero
st.art. wit.h am
set. up t.iming loops

I dx ISH
I da ISH

t.emperat.ure measurement.
ac;r
acr

*-2

arr
IS30
re.l
tillt.mp
IS07
dlay

*

clear conv. complet.e tlag
get. result.
adjust. so 0 deg -S30
store in spi dat.a regist.er
check tor temp. updat.e

send t.emperat.ure value to hc05c4 tor
conversion into celcius. st.art by
int.errupt.ing the hc05c4 and then t.ransmit.
dat.a via t.he spi.
sei
bclr 7.port.c int.errupt. hc05c4
jsr .plwr
write data t.o hc05c4
Idx 1S04

*
OOE~

set. port.c t.o choose msd

delay tor

clr
Ida
bpi
Ida
sbc
sta
Ida
cmp
bne

***

010~

bas.+2
base+3
ISet
portc
segllnt.
ISet
ddrc
ISOt
t.cr
t.iRlt.IIP
sec
pm
IS3b
ct
IS DB
ct.l

deca
bne dlay+4
decx
bne dlay+2

*

OOCA
OOCC
OOCE
DODD
009~ 0002
0097 0004
009B OOD~
0099 OODa
0100 OODA
0101
0102
01.03
0104
010S
0107
010B
0109
0110
0111
0112
0113
0114
0115

sta
sta
Ida
sta
sta
Ida
st.a
Ida
st.a
clr
clr
clr
Ida
st.a
Ida
st.a
c Ii

nxtdg

wait. tor ret.urn data - 140 cycle.
Ida ISOb
st.a base+7
Ida ISOe
deca
bne t.imlp
get. decimal values in celcius trom
hc05c4
jsr spird
Ida result.

378

get value

*

0125
0126
0127
0126
0129
0130
0131
0132
0133
0134
0135
0136
0137
0136
0139
0140
0141
0142
0143
0144
0145
0146
0147
0146
0149
0150
0151
0152
0153
0154
0155
0156
0157
0156
0159
0160
0161
0162
0163
0164
0165
0166
0167
0166
0169
0170
0171
0172
0173
0174
0175
0176
0177
0176
0179
0160
0161
D162
0163
0164
0165
0166

00F2
00F4
00F5
00F7
00F9
OOFA

E7
5C
A3
26
9A
20

4A

sta base,x
e:px U07
bne nxtdg
e:1 i
bra dial'

07
F4
C4
**

OOFC A6 07
OOFE B7 41
0100 60

0101
0101
0103
0105
0106

010B
0100
010F
0110
0112
0113
0115
0117

temp

39
A6
4A
26
90
3A
26
61

06
46
02 FD
02 00

44
02

nxt
*
*
*
*
*
str
stal I

46
EE

1~

90
90
06 02 FO

e:hoose temp. displal'

spi

FO

06
46
45
12
02
02
02

Ida #S07
sta timtmp
rti

*

spi", ..
A6
B7
39
25
10
lE

selee:t temperature displal' **

spi rout intis *****
the thrtie pins used for thti spi are
miso
bit 6, porte:
mos i
bit 5, porte:
se:k
bit 4, po .. te:
the r3 waits to .. a high-to-Iow
t .. ansition ot the spi e:loe:k, whie:h
is provided bl' the he:05e:4 and sent.
on porte: pin 4.
a bit. ot data is
transferred on eae:h high-to-Iow
transition ot the e:loe:k.

*
*
*
D116
0116
011A
011C
011E
0120
0122
0124
0126
0127
Oi26

e:hee:k for end

*****
*
*
*
*
*
*
*
*
*
*

sp i .. d
A6
B7
06
OA

store

inc:x

agn

t.t

rtiad *

tiqU *
Ida #S06
sta bite:t
set bit count ...
brstit 4,p'ortc,* wait to .. clock t .. ansit.lon
brset 5,portc,.t .. ch.ck data .t.atu.
note:
the brset command automat i cal I y
Stits the carry bit to b. .qual to the
bit unde .. t..st
rol result
Ida #S02
deca
bne sta I I
nop
dec bitc:t
bne nxt
rts

store in r •• ult
d.lay loop

ch.ck to .. .nd ot byt..
get n.xt bit.

spi write *
data to be sent i. in .... ult. at.
sta .. t ot w.. ite
equ *
Ida #S06
sta bit.ct
rol .. esl
bcs s.tl
bcl .. 6,po .. tc
bset 7.porte:
bcl .. 4.portc
nop
nap
brs.t 4.portc,*

379

•• t bit. counte ..
sh i tt data
ch.ck data statu •
it D. cl.ar • i.o
cl.ar int. ... rtJPt
ti.ln!l d.lay.
",ait tor clock t.rans.

0187
0188
0189
0190
0191
0192
0193
0194
0195
0190
0197
0198
0199
0200
0201
0202
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220
0221
0222
0223
0224
0225
0220
0227
0228
0229
0230
0231
0232
0233
0234
0235
0230
0237
0238
0239
0240
0241
0242
0243
0244
0245
0246
02·47
0248

0129
0120
012F
0131

3A 40
20 ED
lE 02
81

0132
0134
0136
0138

lC
lE
18
20

02
02
02
EE

dec: bit.c:t.
bne agn
bset. 7,port.c
rt.s
set.l

**
*
*
*
*
*
*
*
013A
0130
013F
0141
0143
0145
0147
0149
0148
0140
014F
0151
0153
0155
0157
0159
0158
0150

CO
A6
87
86
Al
27
A1
27
Al
27
Al
27
Al
27
Al
20
A6
87

01 01
03
41
44
OA
85
OF
3C
OE
39
00
OC
08
oA
OC
39
FF
49

c4int.

**
015F
0161
01b3
01b5
01b7
01b"f
Dlb8
0160
016F
0171
0173

86
27
Al
27
Al
2b
Ab
87
86
Al
22

40
08
01
40
08
48
08
40
48
05
3E

am

blhr
mtn

*
0175
0177
0179
0178
0170
017F
0181
0183

A6
87
A6
87
A6
87
3F
3F

OF
09
43
42
00
43
47
52

but. o,port.c:
b"et. 7,port.c:
bset. 4,port.c:
bra t.st.

check tor end at byt.e
clear int.errupt.
it 1, set. miso
clear int.errupt.

init.ial izat.ion at data read via spi

**

a dat.a read is init.iat.ed via an interrupt.
tram t.he hc05c4. the value received is
test.ed t.o determine which tunction is
requested and t.he processor jumps to the
proper rout.ine.
jsr
Ida
st.a
Ida
c:mp
beq
c:mp
beq
c:mp
beq
cmp
beq
cmp
beq
cmp
bne
Ida
sta

spi rd
.503
t.imt.mp
result
.SOa
t.emp
#SOt
rt.ry
.SOe
clrtm
.SOd
aIR
.SOb
dsec
ItSOc
dig
.Stf
pm

get value
choose time
check tor disp temp
check tor display time
c:heck tor set. t.ime
c:heck tor am
check tor secs
c:heck tor pm
no, set. digit.
set. pm address

c:heclt- tor val i d input.
Ida
beq
cmp
beq
cmp
bne
Ida
st.a
Ida
cmp
bhi

base+3
blhr
.501
twoc
.SOb
blank
ItSOb
base+3
base+l
ItS05
blank

**

check t.ens at hours
it zero, blank digit.
look tor b.1 ank
it not, blank display
blank t.ens ot hours
check t.ens at minut.es
c:heck against 5
it great.er, blank display

val i d input., set. timer count.er
Ida
st.a
Ida
st.a
Ida
st.a
c:lr
clr

.SOf
t.cr
.543
c:t.
ItSOo
c:tl
sec
base+8

380

*

unmask t.imer int.errupt.
load inner loop c:ounter
load out.er loop count.er

0249
0250
0251
0252
0253
0254
0255
0256
0257
0256
0259
0260
0261
0262
0263
0264
0265
0266
0267
0266
0269
0270
0271
0272
0273
0274
0275
0276
0277
0276
0279
0260
0261
0262
0263
0264
0265
0266
0267
0266
0269
0290
0291
0292
0293
0294
0295
0296
0297
0296
0299
0300
0301
0302
0303
0304
0305
0306
0307
0306
0309
0310

0165 3F 53
0167 60

rtry

*
0166
016A
016C
016E
0190
0192

A6
B7
B7
B7
B7
20

llr~

-:)

0194
0195
0197
0199
019B
0190
Ol9F
OlAl
01A3
01A5
01A7
01A9
OlAB

DB
4A
4B
4C
40
F3

9A
B6
B7
B6
B7
B6
B7
B6
B7
Al
22
B7
20

clrtm

*
***
*
*
*
*
*
*
*
*
dig

4C
40
4B
4C
4A
4B
44
4A
09
DE
4A
OA

*
*
OlAO
OlAF
01Bl
01B3
01B5
01B7
01B9
01BB
01BO
OlBF

01Cl
01C3
01CS
01C7

B6
Al
23
3F
3F
A6
B7
A6
B7
20

4C
02
BC
40
4C
DO
4B
05
4A
C6

B7 41
B7 55
B7 54
60

twoc
blank

clr base+9
rti
clear displays

*

Ida .SOb
sta base
sta base+l
sta base+2
sta base+3
bra rtry
input

digit

*

time setting routine ***
time is inputted left to right.
and the end of input is indicated
be pressing either the am Dr pm
pm is denot.ed on the
but.t.on.
display by light i ng the decimal
point. counters are set to zerO out.
atter each second.

c Ii
Ida
sta
Ida
sta
Ida
sta
Ida
sta
cmp
bhi
sta
bra

base+2
base+3
base-+;l
base+2
base
base+l
result.
base
#$09
rtry
base
rtry

sh i ft dat.a left one
digit
enter digit 1
check tor va lid digit
get. next number

check it time less than 12 o'clock
blank display it not
Ida
cmp
bls
clr
clr
Ida
sta
Ida
sta
bra

base+2
#$02
mtn
base+3
base+2
#$Od
base+l
#$05
base
rt.ry

check hours units
okay. check tens of min.

send errOr message

**** seconds display *****
* blank first two leds
*
dsec

sta timtmp
sta base+Sb
sta base+Sa
rti

381

set timtmp to SOb
blank 1st two leds

0311
0312
0313
0314
0315
0316
0317
0316
0319
0320
0321
0322
0323
0324
0325
0326
0327
0326
0329
0330
0331
0332
0333
0334
0335
0336
0337
0336
0339
0340
0341
03/.2
0343
0344
0345
03,46
0347
0346
0349
0350
0351
0352
0353
03S4
0355
0356
0357
035B
0359
0360
0361
036.2
0363
0364
0365
0366
0367
036B
0369
0370
0371
0372

*****
*
*
*
*
*
*
*
01C6
99
BE
A6
B7
36
25

0103
0105
0107
0109
010A
0100
010F
OlEO
01E3
01ES
01E6
01E9
01EB
OlEO
01EE
OlFO
01F2
01F4

A6
B7
E6
SA
02
E6
SA
04
E6
SA
06
E6
A4
97
EE
BF
B6
B7

sec
Idx
Ida
sta
roO"
bcs

41
FF
01
48
04
F7
46
4A

min2

46 02
4A
hrsl
46 02
4A
hrs2
48 02
4A
OF

disp

60
01
46
02

**
*
*
*
A6
97
A6
B7
3A
26
A6
97
3A
27
60

10
08
OF
09
42
DB
39
42
43
01
ret

*****
*
*

*
*
*

*****

displays are refreshed every
msec
when a timer interrupt occur-so
the
most significant digit is displayed
fir st.
at the conclusion of each
minute, the time is updated

tmrint equ

01C6
01C9
01CB
01CO
01CF
0101

01F6
01F8
01FA
01FC
OlFE
0200
0202
0204
0206
0208
020A

display routine

*
timtmp
#$tt
portb
segmnt
min2

choose time Or temp
blank displays
send to leds
select display
look for restart

Ida #$f7
restart with msd
sta sl!gmnt
Ida basl!,x
load a with minutes
point to next digit
decx
brset 1,segmnt,hrsl check hours units
Ida basl!,x
load a with tens ot min.
point to next digit
decx
brset 2,segmnt,hrs2 check tens ot hrs.
Ida base,x
load a with hours units
decx
point to next digit
brset 3,segmnt,disp display value
Ida base,x
load a with tens ot hrs
and #$Ot
mask upper nibble
tax
set x equal to a
Idx segtab,x
display value table
stx portb
enable display drivers
Ida segmnt
enable display
sta portc
count display refreshes.
402 ,.etreshes
equals one second.
atter 402 refreshes,
update clock

Ida
sta
Ida
sta
dec
bnl!
Ida
sta
dec
beq
rti

#$10
tdr
#$Of
tcr
ct
ret
#$3b
ct
ct1
tmchg

set timer to interrupt
after 2048 cycles
reset timer interrupt flag
decreml!nt inner loop
rl!Sl!t

innl!r

loop

decrement outer loop
if One sec. ) to timl! changl!

*****

time change rout i nl!.
when 60 seconds are counted,
increase minutes by one, if
necessary, blank minutes and incrl!ase
hours.
change am/pm it needed.

382

0373
0374
0375
0376
0377
0376

020B
020B
0200
020F
0211
037~ 0213
0360 0215
0361 0217
0362 021~
0363 021B
0364 0210
0365 021F
0366 0221
0367 0223
0366 0225
036~ 0227
03~0

022~

022B
0220
0393 022F
03~4 0231
0395 0233
03~6 0235
03~7 0237
03~1
03~2

03~6
03~9

0400
0401
0402
0403
0404
0405
0406
0407
0406
0409
0410
0411
0412
0413
0414
0415
0416
0417
0416
041~

0420
0421
0422
0423
0424
0425
0426
0427
0426
0429
0430
0431
0432
0433
0434

023~

023B
0230
023F
OZ41
0243
0245
0247
0249
024B

tme h 9
3C
3C
B6
Al
27
A6
Bl
26
3F
3F
B6
A1
26
3F
B6
A1
26
3F
B6
A1
27
B6
A1
26
A6
97
A6
97
20
3C
20
3C
20

47
52
52
OA
36
3C
47
54
47
53
4A
09
20
4A
4B
05
1C
4B
40
DB
1E
4C
02
2A
09
40
01
4C
2A
4A
26
4B
2Z

0240 3F 52
024F 3C 53
0251 20 C2

inc
inc

minck

inml
inmZ
tens

*
0253
0255
0257
0259
025B
0250
025F
0261
0263
0265
0267
026~

026B
0260
026F
0271
0273
0275
0277

B6
A1
26
3F
3F
3C
20
3C
20
3C
B6
A1
26
33
A6
B7
A6
B7
60

4C
09
08
4C
40
40
DE
4C
OA
4C
4C
02
90
49
3B
42
08
43

equ

hrck

Ida
cmp
beq
Ida
cmp
bne
clr
clr
Ida
emp
bne
clr
Ida
cmp
bne
clr
Ida
cmp
beq
Ida
cmp
bne
Ida
sta
Ida
sta
bra

base+8
base+8
#$Oa
tens
#$3e
sec
ret1
base+9
base
#$O~

elr base+8
i ne base+9
bra minck
increase hours
Ida
cmp
bne
clr
clr
inc
inc

bra
inhr1a

inc

retl

Ida
cmp
bne
com
Ida
sta
Ida
5ta
rti

incr-ease seconds
inc. secs. units

look for ten
it yes, inc::. tens
look tor a minute
wait tor next second

SI!C

inm1
base
base+1
#$05
i nm2
base+1
base+3
#$Ob
hrck
base+2
#$OZ
inhr1a
#$Ob
base+3
#$01
base+Z
ret1
inc: base
bra ret1
inc base+1
bra ret!

bra
inhr1

*sec

base+Z
#$09
inhrl
base+2
base+3
base+3
ret1
base+2
ret1
base+2
base+2
#$02
ret
pm
#$3b
ct
#$06
ctl

383

zero display
check min. units
less than ~?
increase
min. units

=0
check tens ot min.
less than 5?
increase

tens of min =[]
check tens of hrs.
look tor blank
less than 10:00
check hrs. units
less than 2?
increase

set time to 1:00
done
increase min. units
done
increase ten5 ot min.
zero sec. unit.
inc sec. tens

*
check· hour 5 units
less than 9?
increase
hour5 units =0
tens of hour. "1
done
increase hour. unit.
done
increase hou,.s unit.
check value
for 12·00
no. done
switch pm indicator
reset inner

loop counter

reset outer

loop counter

0435
043b
0437
043e
0439
0440
0441
0442
0443

in it i a i i ze interrupt vec:tQrs

***
DFFe
DFFe
OFFA
OFFC
OFFE

01
01
00
00

ce
3A
90
90

tmrvec
intveq
swiveq
reset

01"9

SHe

tdb
tdb
tdb
tdb

tmrint
c:4int
start
start

384

***

AN1010
MC68HC11 EEPROM Programming from
a Personal Computer
This application note describes a simple and reliable
method of programming either the MC68HC11's internal
EEPROM, or EEPROM connected to the MCU's external
bus. The data to be programmed is downloaded from
any standard personal computer (PC) fitted with a serial
communications port. In addition to the programming
procedure, the software incorporates the facility to verify
the contents of the MCU's internal or external memory
against code held on a PC disc. Both program and verify
options use data supplied in S record format, which is
downloaded from the PC to the MC68HC11 using the
RS232 protocol supported bv the MCU's SCI port.
The minimum MCU configuration required to program
the MC68HC11's internal EEPROM is shown in Figure 1.
This consists onlv of the MCU, an RS232 level shifting
circuit, plus an 8 MHz crystal and a few passive components.
To initiate the download, the PC is connected to the
MC68HC11 SCI transmit and receive lines via a level shifter. The circuit of Figure 1 uses a Maxim MAX232 to

eliminate the need for additional :!: 12 V supplies. The
MCU's special bootstrap mode is invoked bV applving a
logic zero to the MODA and MODB pins, followed bV a
hardware RESET.
Removing the RESET condition causes the MCU to start
execution of its bootloader program, located in internal
ROM, between addresses $BF40 and $BFFF. In normal
single-chip or expanded modes, the boot ROM is not
accessible, and reads from these memory locations will
result respectivelv in irrelevant data or external memory
fetches.
An additional consequence of bootstrap operation is
that all vectors are relocated to the boot ROM area. With
the exception of the RESET vector, which points to the
start of the boot ROM, the remaining interrupt vectors all
point to an uninitialized jump table in RAM. Three bytes
are reserved for each entry in the jump table, to allow
for an extended jump instruction. Tables 1 and 2 detail
the memory map of the bootstrap vectors and an example RAM jump table.

-5V
RS2~2

CONNECTOR

VSS

16
RxO
TxO
CTS
OSR
OCO
OTR

14

11

21

13

12

20 POO (RXI

EXTAL

POI fTXI

MAX232

MC68HCl1Al
52·PIN PLCC

XTAL
22 pF

MOOA

OV
GNO

MOOB
VOO
26

C4

OV

RESET

17
~_-OV

4.7k
L---------------~~~~~----+5V

Cl, C2. C3. C4 - 22 folF 25 V Aluminium or Tantalum
NOTE: To improve reliability of the MCU, all its unused inputs should be connected to VSS or VOO

Figure 1. MC68HC11 Bootstrap Mode Connection to RS232 Line

385

Table 1. Bootstrap Vector Assignments

Note also that erasing the CON FIG register disables the
secu rity featu re.
The bootstrap program then issues a break condition
on the SCI transmit line, and waits for the reception of
the first byte. In this application, no use is made of the
break transmitted by the SCI.
At this point, it is necessary to initiate the PC S record
down loader program, called EELOAD.BAS (written in
BASIC). It will display a header message, and prompt the
user for the number of the COM channel (either one or
two) which is connected to the MC68HC11. A listing of
EELOAD.BAS is given at the back of this application note.
The PC-resident program will now configure the appropriate COM channel to 1200 baud, one stop bit, no
parity, and download the binary file EEPROGIX.BOO from
the PC to the MC68HC11.
The MC68HC1.1's bootloader will automatically detect
the fact that the first incoming character is received at a
different baud rate, and change its SCI rate to 1200 baud.
It will then proceed to load the binary file into all 256
RAM locations and then jump to address $0000 (i.e., the
first RAM location).
EEPROGIX.BOO consists of the MC68HC11 executable
code shown in the source listing at the back of this application note, with the addition of $FF at the head of the
file, and $00 appended up to the 256tl1 byte. This program
is designed to receive S records from the PC and program
the data fields into the appropriate EEPROM memory
locations.
.
A point to note is that the initial $FF byte in EEPROGIX.BOO is only used to detect the baud rate of the PC,
and is not echoed back, while the remaining 256 bytes
are echoed by the MC68HC11 's SCI transmitter. However,
during download of EEPROGIX.BOO, the PC does not
detect the echo, as this feature is unnecessary at this
stage.
Once the newly downloaded S record programmer
starts execution in the MC68HC11, it configures the SCI
to 9600 baud, then waits for a control character from the
PC. This character will determine the operating mode of
the S record programmer. The options available are shown
in Table 3. Note that these programming utilities can be
used to load and verify external RAM as well as external
EEPROM.

Boot ROM

1-.

Address

Vector

BFFE

BF40

Bootstrap Reset
Clock Monitor

Description

BFFC

OOFD

BFFA

OOFA

COP Fail

BFF8

00F7

Illegal Opcode

BFF6

00F4

SWI

BFF4

00F1

XIRQ

BFF2

OOEE

IRO

BFFO

OOEB

Real Time Interrupt

BFEE

OOE8

Timer Input Capture 1

BFEC

00E5

Timer Input Capture 2

BFEA

00E2

Timer Input Capture 3

BFE8

OOOF

Timer Output Compare 1

BFE6

OOOC

Timer Output Compare 2

BFE4

0009

Timer Output Compare 3

BFE2

0006

Timer Output Compare 4

BFEO

0003

Timer Output Compare 5

BFOE

0000

Timer Overflow

BFOC

OOCO

Pulse Accumulator Overflow

BFDA

OOCA

Pulse Accumulator Input Edge

BFD8

00C7

SPI

BF06

OOC4

SCI

Table 2. RAM Jump Table
Internal RAM
Address

Typical Instruction

OOFO

JMP CLKMON

OOFA

JMP COPFL

.... etc

Note that, before any interrupts are enabled in bootstrap mode, it is the software designer's responsibility to
initialize all appropriate entries in the jump table.
As this application note does not make use of the
MC68HC11 's interrupt system, the jump table is not set
up.
The bootstrap program continues by initializing the SCI
transmitter and receiver to 7812 baud and proceeds to
examine the state of the NOSEC bit in the CONFIG register. If this is at logic zero (security enabled) the bootloader will erase the entire contents of internal EEPROM
and also the CONFIG register.

Table 3. 5 Record Downloader Operating Mode Options
Control Character
X

Operating Mode
Program External EEPROM RAM

I

Program Internal EEPROM

V

Verify Internal or External EEPROM/RAM

Ifthe S record programmer has been downloaded successfully, the PC resident program will now 1. Request whether the downloaded data must be
echoed to the screen.
2. Prompt the user for the required operating mode.
3. Request the name of the S record file to be downloaded from the PC.

This feature is particularly useful for security conscious
applications, where the internal EEPROM contains information of a proprietary or confidential nature. Ifthe NOSEC bit is at logic one, then the erasing sequence is not
carried out.

386

programming voltage is applied. Also, the programming
time delay must be implemented or initiated by software.
In this application, a software timing loop is used, but
one of the internal MC68HCll timer functions could
equally well be used to provide the time delay.
Figures 2 and 3 show the flowcharts of the internal
EEPROM erase and write sequences.

Once the download starts, every character in the S record file is immediately echoed back to the PC. This ensures synchronism between the PC and the MC68HC11,
and at the same time, removes some of the overhead
associated with the EEPROM programming delay time.
It also removes the need for a hardware handshake.

VERIFY OPTION
If a verify error occurs, the actual stored byte value is
returned to the PC, where it is displayed with a preceding
colon delimiter. In this way, EEPROM data and address
faults can be quickly identified by inspection. At the end
of the verify download, the total number of errors is displayed.

INTERNAL OR EXTERNAL OPTION
If a programming error occurs in either internal or external programming mode, i.e., if the read back data after
programming does not correspond to the expected data,
the MC68HCll-resident software will hang up. This condition is detected by the PC-resident program, which will
then abort the download and display an error message.
This same error message is displayed if a fault or incorrect connection exists on the serial link between the PC
and MC68HC11.
There is one exception to this operation. It stems from
the fact that changes to the MC68HC11 's CON FIG register
can only be detected after a subsequent hardware RESET.
If the CONFIG register address ($103F) is detected, then
the CONFIG register is not read directly after programming. This prevents premature termination of the download.
To allow programming of the CONFIG register in all
mask set versions of the MC68HCllA series, and to permit expanded mode operation, the MCU resident program switches from bootstrap mode to special test mode,
by setting the MDA bit (bit 5) in the HPRIO register (address $103C).
If the user wishes to maintain operation in bootstrap
mode, (to verify internal ROM code, for instance!. then
the 'BSET HPRIO,X,#MDA' instruction on the 8th line of
program code in EEPROGIX.ASC should be removed, and
the program reassembled.

PROGRAMMING INTERNAL EEPROM
The techniques for programming internal and external
EEPROM are quite different.
With internal EEPROM, it is first generally necessary to
erase the required byte (erased state is $FF), and follow
with a write of data to the same address.
The internal programming sequence involves accessing the PPROG register (address $103B) to latch the EEPROM address and data buses for the duration that the

Figure 2. Internal EEPROM Erase Sequence

387

dition of the MC68HC24 gives a minimal component count
implementation of a circuit which accurately emulates
the MC68HC11A8 single-chip MCU. The added benefit of
using the 2864 is that the software designer's program
andlor data can be modified without removing the emulator from the target system. This can be particularly
useful in applications where the emulator may be enclosed in a confined space or in an environmental chamber.
To program the 2864 from the PC, the external operating mode option (X) must be selected from the EElOAD
menu.
Programming the 2864 involves fewer operations than
are needed for internal EEPROM, as the former has no
equivalent of the PPROG control register. In addition, the
erase sequence and delay time are handled automatically
by the 2864 on'chip logic.
A data polling technique is used to determine the end
of the programming delay time. This involves examining
the most significant bit of the data programmed, by reading from the address just written to, until the data becomes true. (During the programming delay time, the M5
bit will read as the complement of the expected data).
This means that the same software algorithm can be
used to download code or data to external RAM as well
-as external EEPROM.

EMULATOR ADDRESS DECODING

Figure 3. Internal

EEPROM Write Sequence

PROGRAMMING EXTERNAL EEPROM
Figure 4 shows the hardware needed to interface the
MC68HC11 to an external 2864 EEPROM, which provides
a total of 8K bytes of reprogrammable memory. The ad-

The emulator circuit in Figure 4 shows the MC68HC11's
address line A 13 connected to pin 26 of the 2864. Though
this pin is actually unused by the 2864, its inclusion permits the replacement of the 2864 with a 27128 16K byte
EEPROM memory.
An important outcome of this is that, when a 2864 is
used, the memory range $COOo-$DFFF is mapped. over
the normally used 8K byte range of $EOOo-$FFFF.ln practice, this should never pose a problem. When a 27128
memory is used, its full 16K byte address range of
$COOo-$FFFF is available to the MCU.
Included in the 5 record programmer, irrespective of
the selected programming mode, is a feature to force
program execution at the address specified in the 59, 5
record address field, provided the address is not $0000.
Figure 5 shows the general format of 5 record files.

388

18
XIRQ

h '

I II
IRQ

19

28 IRO
J9

1/

RS: !I

41

srRA 4

11
VOO

43
MODE

'DO

T

TOlf

..L.Cl
VSS

AlJ.OD

~~~

~ AOI
3~ :~~

3]

AD~

:

:::

PB6r

PSl

A>O

::

STRB

p---o

P.:----o

p!---o

r;-- } ::::

PC3~

'A14

PC4

m::::::

PORT C

PC5~

ItS

II

MC68HCWN

PC1~

.! Al~

_

SIIIA

pbJL-

A13

~:~

lel

'CO

!lA12

AI4

Hf--o

pa4

PB5~JPORTB

33 AD4

All

-

J8 ADO

A4 04

~;:

Ll!.--.

m---o

PBO I26
PBl

40 ROW

AJ OJ

A~D!t

122334

~:~ ~

42 AS

SIRB 6

1

Nt Ne Nt Ne

~ST

JOTfST

VSS

:Hi---o
r--o

'-'---1"
lelO
HCOO

'DO

~vss

'14 le3A
~HCOO
1

'DO

r

"""l"
Tillf
AD
A'

Ai
Ai

:r.

'-----v-----"

As

Ai"
Ai

PORI'

Vss

'DO

'ss

'"
'R3"

R1

....""''""
'"
A_

jff

'"

"'"

Figure 4. MC68HCllA8 Emulator Using 2864 EEPROM

~

RECORD TYPE: 50,51, OR

S~

so -

HEADER RECORO: LOAD ADDRESS fiELD $0000. CODE/DATA
fiELD CONTAINS OPTIONAL DESCRIPTIVE INFORMATION.
51 - CODE/DATA RECORD. CODE/DATA FIELD CONTAINS EXECUTABLE CODE OR DATA.
S9 - TERMINATION RECORD: LOAD ADDRESS FiElD CONTAINS OPTIONAL EXECUTION ADDRESS. THERE IS NO
CODE/DATA HElD, JUST A CHECKSUM.
/NUMBER OF HEX CHARACTERS FOllOWING. ILenl $14

-

_I/MEMORY LOAD ADDRESS FiElD. ILdhi, Ldlol" SCOIE
5114 C01EOB2~BOC02A18386A3B6F3B39180926FC39 DE

v-------:~CHECKSUM
o

BYTE

TO N BYTES OF CODE/DATA

APART FROM THE LETTER S AT THE START, ALL CHARACTERS IN THE RECORDS ARE HEXADECIMAL DIGITS REPRESENTED IN ASCII FORMAT.

CHECKSUM ALGORITHM: LSB OF

NOTE' The S-record programmer

In

[Lerr. Ldh"

Ldlo' kiO bytek]

thIS application Ignores the checksum byte.

Figure 5. S-Record Format

390

10 ' ******* EElDAD.BAS 20/3/87
Version 1.0
20 ' I/ritten by R.Soja, Motorola East Kilbride'

*******,

30 ' Motorola Copyright 1987'
40 ' This program downloads S record tile to the MC68HCII through special'
50 ' bootstrap program, designed to program either internal or external'
60 ' EEPROM in the 68HCll's memory map'
70 ' The loader can also verify memory against an S record file.'
80 ' Downloaded data is optionally echoed on terminal.'
90 ' ==================================
100 CRS=CHRS( 13)
110 MINS=CHRS(32)
120 MAXS=CHRS( 127)
130 ERMS="Can't find "
140 LOADERS="EEPROGIX.BOO"
150 CLRLNS=SPACES(80)
160 VERS="1.0": 'Version nunber of EElOAD'
170 ERRTOTX=O: 'Nunber of errors found by verify operation'
180 CLS
190 PRINT"

«~«~ecce

200 PRINT"

«««« 68HCII Internal/External EEPROM loader/verifier >>>>>>>>"

EELOAD Version

It;VERS;~'

»»»»"

210 PRINT

mode,"

220 PRINT "==>

Before continuing, ensure 68HCII is in bootstrap

230 PRINT"

RESET is off, and COMI or COM2 is connected to the SCI"

240 PRINT
250 ' first make sure loader program is available'
260 ON ERROR GOTO 880
270 OPEN LOADERS fOR I NPUT AS 112
280 CLOSE 112
290 ON ERROR GOTO 0
300 CHANS="O"
310 ROII=CSRLIN: 'Store current line nunber'
320 IIHILE CHANS<>"I" AND CHANSo"2"
330

GOSUB 1070

340

LINE INPUT "Enter COM channel nunber (1!2):",CHANS

350 \/END
360 CMS="COM"+CHANS
370 ' Now set baud rate to 1200 and load EEPROG through boot loader'
380 ' by execut i ng DOS MOOE and copy commands'
390 SHELL "MOOE "+CMS+":1200,N,8,1"
400 SHELL "COPY "+lOADERS+" "+C"'S
401 GOSUB 1070
402 fOR 1"=1 TO 4:PRINT CLRLNS;:NEXT I":PRINT: 'Clear DOS commands from screen'
4 10 ECHOS=" 11
420 IIHllE ECHOS<>"Y" AND ECHOSo"N"
430

GOSUB 1070

440

LINE INPUT "Do you want echo to screen (Y/N):",ECHOS

450 IlEND
470 ROII=CSRLlN: 'Store current-line nunber'
480 EEOPTS=u ": 'Initialise option char'

490 IIHILE EEOPTS<>"X" AND EEOPTS<>"I" AND EEOPTS<>"V"
500
SID

GOSUB 1070
LINE INPUT "Select Internal,eXternal or Verify EEPROM option O/X/V):",EEOPTS

520 IlEND
530 OPTS="Ver i fy"
540 If EEOPTS="I" THEN OPTS="lnternal"
550 If EEOPTS="X" THEN OPTS="External"
560 ROII=CSRLlN: 'Store current line position in case of file error'
570 RXERR=O:

'Initialise nunber of RX errors allowed'

580 ON ERROR GOTO 910
590 GOSUB 1070

391

600 IF OPTS--DYerify· THEN INPUT "Enter filename to verify: ",fS ELSE INPUT "Enter filename to download:",FS
610 CLOSE
620 OPEN fS fOR INPUT AS .2
630 ON ERROR GOTO 0
640
650

'cOIn

or 2 connected to SCIon HCll'

OPEN CMS+":9600,N,8,1" AS 111

660 'Establish contact with HCll by sending CR char & waiting for echo'
670 ON ERROR GOTO 860: 'Clear potential RX error'
680 PRINT 'I,CRS;
690 GOSUB 990: 'Read char into as'
700 'Transmit Internal,External or Verify EEPROM option char to 68HC11'
710 PRINT 1I1,EEOPTS;:GOSUB 990:

'No echo to screen'

720 ON ERROR GOTO 930

730 PRINT "Starting download of <";FS;"> to: ";OPTSi" Eeprom"
732 If ECHOS="Y" THEN EX=1 elSE EX=O
734 If EEOPTS="Y" THEN VX=1 ELSE VX=O
740 IIHILE NOT EOf(2)
750

INPUT '2,SS

751

LX=LEN(SS)

752

fOR IX=1 TO LX

760

PRINT 'I,MIDS(SS,IX,I);:GOSUB 990:lf EX THEN PRINT as;

770

If VX THEN GOSUa 1030:lf CS<>"" THEN PRINT ":";HEXS(ASC(CS»;

785

NEXT IX

787

If EX THEN PRINT

790 IIEND
795 PRINT
800 PRINT "Download Complete"
810 If VX THEN PRINT ERRTOTX;" error(s) found"
820 CLOSE 112
830 SYSTEM
840 END
850 ' -----------------,
860 If RXERR>5 THEN 940 ELSE RXERR=RXERR+l:RESUME 610
870 ' -----------------,
880 PRINT:PRINT ERMS;LOADERS:PRINT "Program aborted"
890 GOTO 830
900 ' -----------------,
910 PRINT ERMS;fS;SPACES(40)
920 RESUME 580
930 ,-----------------,
940 PRINT:PRINT "Communication breakdown: Download aborted"
950 GOTO 820
960 ,--------------------,
970 '--SUB waits for received character, with time limit'
returns with char in BS, .or aborts if time limit exceeded'
990 TOX=O:IIHILE LOC(I)=O:lf TOX>100 THEN 940 ELSE TOX=TOX+l:WEND
980 ,--

1000 as=INPUTS(l,1I1):RETURN
1010 ,--------------------,
1020 '--sua waits for received character, with time limit'
1025 ,--

returns with char in CS, or null in CS if time limit exceeded'

1030 TOX=O:CS='''':WHILE LOC(I)=O AND TOXlete reading 59 record before terminat ing

116 A 0040 17

TBA
II of bytes to read including checks ....

11'9

117 A 0041 8002

SUBA

112

118 A 0043 806B

BSR

GETADR

Get execut i on address in Y

BSR

RDBYTE

Now discard remaining bytes,

119 A 0045 8058

LOA09

120 A 0047 4A

DECA

121 A 0048 26FB

BNE

L0AD9

122 A 004A 188COOOO

CPY

110

123 A 004E 27FE

BEQ

124 A 0050 186EOO

JIIP

including checks ....
If execut i on address =0 then
hang up else

j"", to it!

,Y

125 A
EQU

*

127 A 0053 804A

BSR

RDBYTE

Read byte count of SI record into Acca

128 A 0055 17

TBA

129' A 0056 8003

SUBA

113

Remove load address & checks ... bytes from count

GETADR

126 A

0053

LOADI

130 A 0058 8056

BSR

131 A 005A 1809

DEY

132 A 005C 2017

BRA

and store in ACCA
Get load address into X register.
Adjust it for first time thru' LOAD2 loop.
LOADIB

133 A
134 A 005E 0600

LOADIA

Update CC register

LDAB

EEOPT

135 A 0060 2B25

Bill

VERI FY

I f not veri fyi ng EEPROM then

136 A 0062 2705

BEQ

OATAPOLL

If programming external EEPROM

LOAB

I/uS500

137 A 0064 C6A6
138 A 0066 SA

WAITI

139 A 0067 26FD
140 A 0069 18E600

BNE
OATAPOL L

then wait 500uS max.

DECB
WAITI

Now either wait for completion of programming

LDAB

,Y

141 A 006C 0803

EORB

9 then asserne its A· F

RTS

195 A
196 A

00C3

PROG

Eeu

197 A 00C3 36

PSHA

198 A 00C4 8616

LDAA

#S16

Defaul t to byte erase mode

199 A 00C6 188C103F

CPY

#CONFIG

I f byte's address is CONF I G then use

200 A OOCA 2602

SNE

PROGA

LDAA

#S06

bulk erase, to allow for Al & A8 as well as A2.

BSR

PROGRAM

Now erase byte, or entire memory + CONFIG.

203 A OODO 8602

LDAA

#2

204 A 0002 800C

BSR

PROGRAM

Now program byte.

205 A 0004 188C103F

CPY

#CONFIG

If byte was CONFIG register then

206 A 0008 2603

BNE

PROGX

LOAB

,Y

201 A OOCC 8606
202 A OOCE 80 10

PROGA

207 A OOOA 18E600
208 A OODO 32

PROGX

209 A OOOE 20A3

Save ACCA.

PULA
BRA

load ACCB with old value,to prevent hangup later.
Restore ACCA

LOADID

and return to main bit.

210 A
211 A

OOEO

PROGRAM

EeU

212 A OOEO A73B

STAA

PPROG,X

Enable internal addr/data latches.

213 A 00E2 18E700

STA8

,Y

IIr i te to requi red address

214 A 00E5 6C38

INC

PPROG,X

Enable internal programming vol tage

215 A 00E7 3C

PSHX
1ImS10

and wait 10mS

216 A 00E8 CEOO05
217 A OOEB 09

LOX
IIAIT2

DEX

218 A OOEC 26FD

BNE

219 A OOEE 38

PULX

220 A OOE F 6A3B

DEC

PPROG,X

Disable internal programming vol tage

221 A OOF 1 6F3B

CLR

PPROG,X

Release internal addr/data latches

222 A 00F3 39

RTS

223 A
224 A

IIAIT2

and return

•
END

396

SYMBOL TABLE:

Total Entries=

41

BALO

002B

PROGA

OOCE

COMFIG

103F

PROGRAM

ODED

OATAPOLL

0069

PROGX

0000

EEOPT

0000

ROBYTE

009f
0020

GETADR

OOBO

RORF

HEXBIN

OOBA

READC

0092

HEXNUM

ooeo

ReadOpt

0012

HPRIO

003C

SCCRl

002C

LASTBYTE

0003

SCCR2

0020

LOAD

002E

SCOR

002F

LOAD 1

0053

SCSR

002E

L0AD1A

DOSE

SMOO

0040

LOAD1B

0075

TORE

0080

LOAD 10

0083

TEMP

0002

L0AD1E

0072

VERI FY

0087

L0AD9

0045

IIAlTl

0066

MASK

0001

IIAlT2

OOEB

MOA

0020

IIRlTEC

0098

OptVerf

0027

mSl0

0005

PPROG

003B

uSSOO

00A6

PROG

00C3

397

398

AN1050
DESIGNING FOR, ELECTROMAGNETIC COMPATIBILITY
(EMC) WITH HCMOS MICROCONTROLLERS
by
Mike Catherwood
Motorola Inc.
Austin, Tx.

INTRODUCTION
The operating speed of present HCMOS devices is approaching that of the fastest
bipolar logic families of only a few years ago. Associated with this increase in
performance are some new design challenges for the MCU-based system designer.
This application note addresses one of these issues, the electromagnetic compatibility (EMC) of the finished product. EMC may be considered from either an emission or a susceptibility point of view. Although the following discussion relates
primarily to emission control (in particular, radiated emission), most techniques to
limit emission also reduce susceptibility. Futhermore, minimizing electromagnetic
interference (EMI) will reduce overall system noise, the benefits of which are higher
digital noise immunity and accurate operation of local analog subsystems - Le.,
better design margin and a more reliable end product.
EMC can only exist when the system functions correctly within the intended electromagnetic environment and does not exceed the EMI levels specified in the appropriate standards documents. EMI, which encompasses interference in a
bandwidth of 'dc to daylight' is a generalization of a much older term, radio frequency interference (RFI), which is now defined to encompass 10 kHz to 3 GHz.
Failure to consider EMC during early phases of the design process may result in
expensive modifications (possibly with many additional components), printed circuit board (PCB) re-Iayout, product introduction delays, and EMC consultant fees
to conform to the required standards.

399

LEGAL REQUIREMENTS
The Federal Communications Commission (FCC) have a set of standards to regulate
EMI in electronic equipment and systems for use in the United States. Compliance
with the appropriate sections of these regulations is mandatory to market or sell
a product except for certain subclasses of digital devices that are temporarily exempt. Engineering models (including field-trial prototypes which are not sold) are
also exempt; however" the display of a product at an electronics show is considered
a marketing function subject to regulations.
FCC rules and regulations (part 15, subpart J of Title 47 of The Federal Regulations)
apply to almost all digital devices (see Reference 1), defining standards and operational requirements for all devices capable of emitting RF energy within the
range 450 kHz to 1 GHz.
Equipment for use within West Germany must comply with a different set of standards defined and administered by the Verland Deutcher Electro-Techniker (VDE).
Digital equipment is generally required to meet both VDE0871 standards. In other
countries, compliance to a standard is not always mandatory, however, the European Economic Community (EEC) member states intend to introduce a mandatory
RFI performance standard after 1st January 1992. The current proposal is based on
International Special Committee on Radio Interference specification CISPR22 and
is referred to as European norm EN55022. As the FCC is a member of the CISPR,
and has voted in f5'vor of the CISPR22 standard, it is likely that the FCC will utimately
adopt the same standards. CISPR22 is somewhat more stringent than FCC part 15,
subpart J in the 88 to 230 MHz frequency range, though it is less stringent than
some aspects of the VDE0871.

RFI PROBLEM OVERVIEW
The frequency spectrum of a periodic waveform has been shown, through Fourier
analysis, to be composed of discrete frequency components that include the fundamental (fo) and multiple harmonics (n x fo). For a typical trapezoidal waveform,
the relative amplitude of each frequency component is related to the fundamental
frequency, the rise time, and mark-to-space ratio (duty cycle) of the waveform (see
Reference 2). Doubling the frequency, halving the rise time, or halving the markto-space ratio will double ( + 6 dB) the amplitude of a specific harmonic frequency.

400

It

It is pO,ssible to graphically predict the harmonic spectrum of a specific trapezoidal
waveform by plotting the amplitude of two corner frequencies and a reference (0
dB) point. This plot is referred to as a Fourier envelope, a Bode plot, or a nomogram.
An example is shown in Figure 1 where:

o dB reference
f1
f2
where:
V = amplitude
P = pulse width
tr = rise time
T = period
8 = (P - t r ) T

=

=
=

20 log(2A8)
1 'lTP
1 'lTtr

dB
Hz
Hz

V
s
s
s

At frequencies beyond f1 (' r;Pl. the amplitude of the harmonics falls off at - 20
dB decade, Above f2 (1 r;trl. the amplitude of the harmonics falls off at -40 dBI
decade, For many applications, these latter harmonics are considered small enough
to be ignored; thus, the bandwidth of a system is generally defined to be lI'lTtr' For
example, an HCMOS device which can produce an external periodic signal with
edge times on the order of 2 ns can generate significant harmonics (Le., have a
bandwidth) of up to 160 MHz. Any PCB tracks, component leads, cables, or connectors attached directly or capacitively to signal sources, such as those previously
described, can act as antennas and radiate the harmonics with varying degrees of
efficiency. Radiated emission from a system may be either differential-mode or
common-mode radiation; common-mode radiation is typically more difficult to
reduce.

DIFFERENTIAL-MODE RADIATION
Differential-mode radiation is caused by the flow of RF current loops around the
system conductors. For a small loop area, the far-field electric term, when operating
in an field above a ground plane (free space is not a typical environment). can be
shown to be approximately (see Reference 3):

E= 2.6(A ILf2)/R
where:
A = loop area
IL = loop current
f = frequency
R = distance

cm 2
A
MHz
m

401

fJ. V/m

(1)

!1i=(P+I,)1T
20 LOG (2AO)

!

t----.....,.------

20 LOG (2AI,IP)

LOG FREOUENCY (Hz)

(a) Nomogram

-

90'10

P

v
I

-10%

I

~II..-I'
I

I

T

(b) Trapezoidal Waveform

Figure 1. Nomogram of a Trapezoidal Waveform

402

..

,

For a constant current and loop area, the electric field at a prescribed distance is
proportional to the square of the frequency (i.e., it increases at 40 dB/decade).
Adding this term to the Fourier envelope indicates that the differential-mode radiated emission increases at 20 dB/decade up to f2, after which it remains flat. R
is fixed by both the FCC and VDE rules and regulations, and f is usually not a
system variable; however, A and IL can be reduced through thoughtful board layout
and careful circuit design.

COMMON-MODE RADIATION
Common-mode (CM) radiation is caused by unintentional voltage drops in a circuit,
which cause some grounded parts of the circuit to rise above the real ground
potential (see Figure 2). Cables connected to the affected ground act like antennas
and radiate the components of the CM potential. The far-field electric term can be
shown as follows (see Reference 3):
E "" (f ICM L)/R
where:
L = antenna length
ICM = common-mode current
f = frequency
R = distance

Vim

(2)

m
A
Hz
m

For a constant current and antenna length, the electric field at a prescribed distance
is proportional to 'the frequency (i.e., it increases at 20 dB/decade). Adding this term
to the Fourier envelope indicates that the CM radiated emission remains flat up to
f2, then decreases at - 20 dB/decade for frequencies above f2. Unlike differentialmode radiation, which is relatively easy to reduce through careful product design,
CM radiation is more difficult to control since the only variables available to the
designer are typically the common path impedances and CM current. Obviously,
to eliminate the radiation, the CM current must approach zero, which can be achieved
through a sensible grounding scheme and the addition of inductors or capacitors
to increase the cable (antenna) impedance.

SUPPLY DECOUPLING
Inadequate decoupling decreases system noise margins and ultimately leads to
incorrect, unreliable, or unstable operation. For example, the MC68HC11A8 can
generate peak supply-current transients of approximately 100 mA, which is typical
of an HCMOS microcontroller. Although the average supply current is only a few
milliamps, the power supply must be able to source the peak supply-current levels

403

•
MCU

(a) Poor Supply Decoupling

LPCB

RPCB

L CAP (3 nH)
BOND WIRES
AND PIN
4nH/1 mQ

MCU

LCAP (3nH)

RPCB

LPCB

FOR TOTAl PCB TRACK LENGTH OF 15 em: L.89 nH. R.
(ASSUMING 5 nHIcm AND 5 mQ tem)

(b) Equivalent Circuit of (a)

Figure 2. PCB Layout

404

n mQ

to guarantee correct operation. Also, for fast digital logic, the peak supply-current
transients are large enough to create an EMI problem if the decouplinglayout is
poor.
A decoupling network is used to reduce the supply impedance at the device. To
calculate the value of a decoupling capacitor, the acceptable supply ripple must
first be determined. An appropriate goal is to achieve a maximum ripple of 20% of
the minimum noise immunity voltage - e.g., for the MC68HCllA8 with VOO = 5 V
and no loads:
VIL - VOL = (0.2xVOO)-0.1 = 0.9 V
VOH - VIH = 4.9-(0.7xVDD) = 1.4 V
Therefore,
Minimum noise immunity = 0.9 V
Maximum ripple=0.2 x 0.9 = 180 mV
Transient period = 10 ns
Now,
C = IDD I (dv/dt)
= 100 mAl(180 mVI10 ns)
= 0.006 f-lF
Rounding up to the nearest preferred value gives 0.01 f-lF. When operating the
device in expanded mode, the transient currents generated by bus switching can
be significantly larger. Consequently, the recommended decoupling configuration
is a 1 f-lF tantalum in parallel with a high-frequency 0.01 f-lF multilayer ceramic (or
similar) capacitor. The parallel 0.01 f-lF capacitor extends the upper frequency response of the network which migh otherwise be reduced due to the internal inductance of the 1 f-lF capacitor. However, with the exception of VLSI devices,
decoupling capacitors rarely need to exceed 0.01 f-lF per device. It is also recommended to bulk decouple the board at the supply-line entry point with a 10-100
f-lF capacitor, depending upon the total board-supply requirements. Because it is
desirable to prevent unwanted supply noise from going off-board and radiating
from the connecting cables, a ferrite bead can be added between the decoupling
capacitor and the connector. Care must be taken to ensure that the DC current will
not saturate the ferrite, making it ineffective.
For a decoupling network to operate successfully, the impe9ance between the
network and its load must be very low, and, to reduce EMI, its loop area must be
as small as possible. Consider the PCB layout of Figure 2(a); the equivalent circuit
is shown in Figure 2(b).

405

For DC current,
Vdrop = (77)xO.1 mV
= 7.7 mV
For AC current, assuming 100 mA peak current with a minimum rise time of 10 ns,
Total inductance = 89 nH
V drop = L di/dt
= 89 nH(100 mAl10 ns)
= 890 mV
A drop of 0.9 V between the decoupling network and the MCU exceeds the maximum acceptable ripple, even if the recommended network is used. As shown in
this example, for fast current transients containing many high-frequency components, the circuit inductance is by far the most critical factor when considering
decoupling effectiveness.
Parasitic loop impedance can be effectively reduced through the use of thicker PCB
tracks, ground/supply planes, and more direct routing. Decoupling networks should
be located as close as possible to the device supply pins. Surface-mount capacitors,
which have lower inductance than their leaded counterparts, may be used to the
full advantage as decouplers if mounted on the noncomponent side of a PCB across
a component, which is the closest possible location. Reducing loop impedance also
tends to reduce loop area, which has been previously shown (see Equation (1)) to
be directly proportional to radiated field strength.

SELF-RESONANCE
The inductance and capacitance within the decoupling loop, essentially results in
a series-resonant tuned circuit where:
resonant frequency, f= 1/ 2n VLC

Hz

(3)

At frequencies above f, the impedance of the circuit becomes inductive an" results
in a less effective decoupler. At resonance, f, the impedance is purely resistive and
at a minimum, which can be used to advantage in solving narrow-band RFI problems by tuning suspect decoupling networks to resonate at the problem frequency.
For example, to reduce harmonics in the area of 100 MHz (the FM radio band) for
a total loop inductance of 10 nH, equate Equation (3) to 100 MHz and solve for C.
In this example, C would equal approximately 250 pF.

406

LINE TERMINATION
A signal will propagate down a PCB track at approximately 0.6 the speed of light
(0.6 ft ns) until it reaches a load. If the line is unterminated (e.g., a high-impedance
input). then the degree of impedance mismatch between the load and the line will
cause a proportional amount of the signal to be reflected back down the line toward
the source. These reflections can induce ringing and overshoot, causing significant
EMI problems. If the load equals the characteristic impedance of the line, ZO, then
from viewpoint of the line, the load looks like an infinite line and nothing will be
reflected.
In the cas~ of a mismatched line, if the source-signal rise time is sufficiently slow
with respect to the line propagation time, then the reflections will be absorbed by
the'source during the signal rise time. In all other cases, the line should be treated
as a transmission line and terminated accordingly (see Reference 3). As a general
guide, there should be no need to terminate a line ifthe one-way propagation delay
of a line is less than one-fourth of the signal rise time. For example, for HCMOS
with a rise time of 10 ns, the maximum unterminated line length can be estimated
as follows:
t delay < 0.25 x 10 ns
< 2.5 ns
length < velocity x t delay
< 0.6 x 2.5
< 1.5 ft
Therefore, for the majority of cases, termination will not be necessary when using
HCMOS devices. Applying the same criteria to Schottky TTL, which has rise times
on the order of 3 ns, provides a maximum length of 5.5 in.

FERRITE BEADS
Ferrite beads have excellent high-frequency characteristics and are especially effective in damping high-frequency switching transients or parasitic ringing due to
line reflections. Their low impedance (usually below 100 ill makes them particularly
suitable to filter out supply noise above approximately 1 MHz, preventing the noise
from going off-board or into another circuit. However, care must be taken to ensure
that the DC current does not saturate the ferrite if it is to be an effective filter.
Ferrite~ having a variety of characteristics are available in many different packages,
including surface mount.

407

GROUNDING TECHNIQUES
A ground is supposed to be an equipotential point or plane used as a reference
potential within a system. In reality, this is untrue due to inevitable parasitic inductance and high ground currents causing significant voltage drops, which can
result in common-mode radiation problems. To design a successful grounding
scheme, the designer must be aware of the paths that ground currents will take to
identify possible common-mode impedance problems, reduce loop areas, and prevent noisy return currents from interfering with low-level circuits.
Signal grounds can be classified as single-point, multipoint, or hybrid grounds (see
Figure 3). Single-point is acceptable for low frequencies but may have too much
impedance at higher frequencies to operate correctly. The ground wire length should
be kept as short as possible to reduce inductance and radiating ability. A multipoint
ground is used in high-frequency systems, such as digital circuitry, in which each
element is connected to the nearest low-impedance ground plane. A hybrid ground
looks like a single-point ground at low frequencies and a multipoint ground at high
frequencies. A typical system is often a mixture of grounding techniques.
Figure 4 shows a typical MCU application grounding scheme, categorized into lowlevel analog, digital, input/output (110) buffer, high-current switching, and hardware
grounds. A single-point ground is located at the source of primary power, which
is typically the power supply. The on-board digital logic has a multipoint ground,
though it is grounded off-board through a single-point ground. To prevent radiation,
no high-frequency components of digital return current should be allowed offboard; thus, the board power-supply lines should only carry DC current, which is
suitable for single-point grounding. A block diagram, such as the one shown in
Figure 4, is a useful starting point for the design of a good grounding scheme.

ANALOG-DIGITAL MIX
Combining analog and digital circuitry onto a single board requires special attention
to PCB layout. Figure 5(a) demonstrates how common-mode impedance ground
coupling can superimpose noise on an analog input signal. For example, if the
analog section were a 12-bit A/D converter, the added digital noise would significantly reduce the achievable accuracy of the measurements, possibly by several
bits. In Figure 5(a), the analog circuit shares its ground and supply with the noisy
digital section and is therefore within the digital supply loop. The PCB tracks are
also very thin, increasing the parasitic inductance and voltage drop. A better layout
of the board is shown in Figure 5(b) in which the digital supply and ground tracks
are substantially wider and the analog circuitry is provided with its own supply and
ground reference. Any voltage drop occurring on the digital ground track no longer
affects the analog input signal because the digital current no longer passes through
the analog input loop.

408

(a) Single Point

(b) Multipoint

(c) Hybrid

Figure 3. Grounding Techniques

409

ENCLOSURE

DIGITAL

ov • •~"",.-POWER
SUPPLY
TO,fROM 1.0

Figure 4. Typical MCU Application Grounding Example

410

DIGITAL

OV

Vnoise

t

(a) Poor Scheme

DIGITAL
SUPPLY

DIGITAL

DIGITAL
GROUND
ANALOG
SUPPLY

ANALOG
GROUND

(b) Improved Scheme

Figure 5. Analog Circuit Grounding

411

Adequate supply decoupling is also a prerequisite to minimizing noise in an analog
subsystem. With regard to the MC68HC11 on-chip AID converter, the recommended
decoupling network for the analog reference inputs is shown in Figure 6.
VDD

T

1----1...---.

lK

I

Vreth

O'l~F

......: - - - - - - - - - - - - - - + - - - - ;..~Vren
• Vre!1 SHOULD NOT GO BELOW VSS-O.6 V

Figure 6. Recommended AID Reference Voltage Decoupling for the MC68HC11

1/0 CABLES AND SHIELDING
Providing a low-noise ground for I/O enables I/O shunt filters to be used to remove
common-mode voltages from I/O cables that extend beyond the enclosure (see
Figure 4). In addition, externally shielding I/O cables is ineffective if the termination
grounds are themselves noisy. Alternatively, an inductor (choke) may also be used
to increase I/O cable impedance and reduce radiation.
Generally, the shield surrounding low-frequency signals should be grounded at
one end, and that for high-frequency signals, at both ends. For example, in Figure
4 where the analog section is grounded, an input cable shield would only be grounded
at the analog circuitry end. Shielded cables carrying digital signals (e.g., MC68HCll
SCI data) should be grounded at both ends to ensure that the shield be as close
as possible to ground potential throughout its length. If this configuration is not
practical, the next best configuration is to ground only the signal source end of the
shield. Caution, grounding at both ends of a long cable can cause large powerfrequency ground-loop currents to flow due to potential differences between the
shield grounding points. This problem can also be removed through filtering or
the addition of a common-mode choke or balun (see Reference 3).

412

PCB LAYOUT GUIDELINES
A successful EMI design starts with good board design. As discussed earlier, the
two criteria of m;)st concern are signal-path inductance and loop area. The inductance of a flat conductor (e.g., a PCB track) above a current-return path is as
follows:
L= 2 In(2

11'

h/w)

nH/cm

(4)

where:
h = height above current-return path
w = track width
Evaluating Equation (4) for a height above a current-return path of 1 mm and a
track width of 0.5 mm, L = 5.1 nH/cm. The relationship is logarithmic, so doubling
the track width will not halve the inductance, however, it will make a significant
difference and is always worth doing. For example, doubling the track width to 1
mm makes L=3.7 nH/cm. A track width of 5 mm makes L=0.5 nH/cm, which is of
the order required for effective decoupling loops and reducing common-mode
radiation problems.
Use of a multilayer PCB will provide low-inductance supplies, though at an additional cost. The recommended arrangement is to place the supply and ground
planes on the outside, sandwiching the signal lines between them. This arrangement will also provide some shielding. To minimize crosstalk, signals on adjacent
layers should be routed perpendicular to each other wherever possible. If a multilayer board is not used, fill all unused area with ground plane; avoid creating
ground loops that can cause EMI problems. For example, a ground loop is discovered and subsequently broken with a small gap. This technique is acceptable at
DC, but at high frequencies the gap capacitance may effectively close the loop and
create a large loop antenna. Apart from the radiation problems, large ground loops
can also make a system more susceptible to malfunction when subjected to an
electrostatic discharge (e.g., through a membrane keypad) or other external EMI
source.
Reducing loop area through decoupling and careful layout will reduce RFI. The
smaller footprint of surface-mount components can be used advantageously in
reducing loop area. For PCBs without a ground plane, signal lines should ideally
have a ground-return path as close as possible to them to minimize loop area. In
the case of address/data lines, this arrangement may be impractical; thus, routing
at least one ground-return track adjacent to each of the eight lines and keeping the
lines as short as possible is a good compromise': For the address lines, route the
ground return next to AO (in the case of a word-sized bus, A 1), since this line is
likely to be the most active. Ground and supply loops with long or thin tracks can

413

be easily identified by tracing them on a printed copy of the PCB artwork using
colored marker pens. As previously mentioned, any unused area should be filled
with ground plane.
The system clock is oftet:' a primary source of radiation. The clock components
shou1d be closely grouped, and all clock lines should be as short as possible and
have adjacent ground tracks or ground plane. To avoid crosstalk contamination
and subsequent radiation problems, the clock circuitry should be located away or
shielded from any I/O signal lines or Circuitry. For example, mixing clock and I/O
buffers in one package is not good practice.
Anoth~r source of RFI is an abrupt change of direction of a PCB track which effectively look like impedance discontinuities and will radiate accordingly. For HCMOS
designs, it is important to ensure that 90-degree track-direction changes do not
occur (see Figure 7).

(a) Incorrect

(b) Correct

Figure 1. Incorrect (a) and Correct (b)
PCB Track Layout for HCMOS Designs

414

Finally, all unused inputs to HCMOS devices should be terminated to prevent unintentional random switching and noise generation. Also, unterminated CMOS inputs tend to self-bias into the linear region of operation, which can significantly
increase DC current drawn. They are also more susceptible to electrostratic discharge damage.

SIMPLE RFI DIAGNOSTIC TOOL
An article (reprinted by permission of EMC Technology magazine, Reference 5)
detailing the construction of a set of RFI diagnostic tweezers is included with this
application note. After applying the previously discussed techniques to attain EMC,
if a radiated EMI problem exists, this simple tool may be used to speed up the
identification of potential problem areas on a PCB.

CONCLUSION
EMI control has left the specialized realms of electronic design (e.g., military) and
is rapidly becoming an industry-wide phenomenon. Although the application of
good system design will alway be a prerequisite to achieving EMC, it is reasonable
to suppose that similar design concepts could also be applied to the source of most
of the radiation, the VLSI HCMOS device. To respond to these and other customer
demands for higher performance machines, Motorola is investigating new system
and circuit design, layout, and alternative packaging techniques. This research may
help to reduce the likelihood of problematic RFI when using HCMOS MCU devices;
however, the user's awareness and understanding of the problem will remain the
most vital step towards product EMC.

REVIEW OF KEY POINTS
Differential-mode radiation features are as follows:
1. The system clock is often the primary source of radiation. Avoid ground loops
and long tracks (always take the most direct route). Wherever possible, clock
tracks (or any other signal) should have adjacent ground-return tracks. Minimize the number of devices requiring the system clock. Ensure that clock
circuitry and associated lines are located well away or shielded from PCB 1/0
tracks or circuitry. Never mix clock and bus or 1/0 drivers in the same package
- use separate buffer drivers for clock and buses.

415

2. Ensure that decoupling capacitors are as close as possible to the device supply
pins to reduce the loop area through the capacitor. Always parallel decouple
large-value (DC ballast) capacitors with one or more smaller high-frequency
capacitors (check their equivalent series inductance (ESL) and maximum frequency rating).
3. In addition to local device decoupling, decouple the power supply where it
enters the PCB. A ferrite bead (e.g., Z>50 n at 100 MHz) will also help prevent
switching transients from going off-board.
4. For PCBs without a ground plane, minimize addressldata line loop areas by
routing a minimum of one ground-return track adjacent to each of the eight
lines and by keeping the lines as short as possible. For the address lines, route
the ground return next to AO ,because this line is likely to be the most active.
Note also that long address lines will ring, which is another potential source
of RFI. These lines may need to be individually terminated (see Reference 4).
Operating an MCU in single-chip mode will almost eliminate radiation from
addressldata lines (still exists internally, of course).
5. Avoid ground loops. Remember that breaking a loop with a small gap may
be fine at DC but gap capacitance may effectively close the loop at RF frequencies, creating a large loop antenna. Apart from the radiation problems,
large ground loops can make a system more susceptible to malfunction when
subjected to external EMI sources.
6. Using a printed copy of the PCB artwork and a marker pen, trace the ground
and supply tracks. Long, thin, or looped tracks can then be easily identified
and subsequently modified.
7. Terminate all unused inputs to prevent unintentional random switching and
noise generation (in addition, unterminated CMOS inputs tend to self-bias into
the linear region of operation, significantly increasing the DC current drawn).
8. The smaller footprint of surface-mount components may be used advantageously to reduce loop areas.
Common-mode radiation features are as follows:
1. Ensure a good ground plane and choose the external ground connection to
minimize the overall common-mode voltage drop (see Reference 4). Increase
both supply and return-supply track widths (as a general rule, cover as much
as possible of the unused part of a PCB).
2. A grounding scheme that isolates digital and 110 (including any analog sections) reduces radiation from liD cables. Shielding these cables is ineffective
ifthe shield termination grounds are noisy. In digital systems, the shield should
be connected to notse-free grounds at both ends. If this configuration is not
possible, then ground only the source end.

416

3. A choke may be effective in reducing the radiation from an liD cable. Also
available are a variety of other passive RFI filter elements which shunt the
common-mode current to ground. The effectiveness of these devices will depend upon the condition of the shunt ground.

REFERENCES
FCC. "Understanding the FCC Regulations Concerning Computing Devices."
OST Bulletin, vol. 62, 1984.
2. Mardiguian, Michel. Interference Control in Computers and MPU-Based Equipment, Gainesville, Va.: Don White Consultants Inc., 1984.
3. Ott. Henry W. Noise Reduction in Electronic Systems. 2nd Edition. New York:
Wiley Interscience, 1988.
4. Ott, Henry W. "Digital Circuit Grounding and Interconnection," IEEE Internatronal Symposium on Electromagnetic Compatibility, August 1984.
5. EMC Technology and Interference Control News magazine, Gainesville, Va:
Don White

417

IMI/RFI, Diagnostic 1Weezer
Probes: A COnsllVction Article
by Frank Moriarty
General DataComm, Inc
Middlebury, CT 06762

T

he RF bypassing tweezer probes described in this article will
give their users the ability to quickly and conveniently locate
EM! trouble spots at which a permanent suppression component would likely lower the overall EM!. Equally important, these
probes will quickly eliminate those circuit points at which a permanent bypassing fix would not be effective. Though simple
(isolated tweezer blades spanned with a capacitive element), their
effectiveness greatly reduces EM! troubleshooting time.
This article includes three different models of the basic idea, i.e.,
a fIXed, broadband, non-tuning probe; a tunable model; and a bandswitching (three bands) model. The practical performance of each
probe was initially tested in both active square wave and coaxial
sine wave test circuits. Also, these probes have been used for several
years in "on the job" RF suppression work. The time saved has
been priceless, and head scratching is held to a minimum. ! am
sure that the tweezer probe will also become an indispensable suppression tool in your bag of EM! tricks.
While the usefulness of these probes is perhaps priceless, the
material count and cost will be extremely low-under 5S.00-as
shown in Thble I. These probes are also available pre-built.
To help in choosing which probe would be best suited to your
particular situation, see Thble 2. It lists the frequency bandwidths
and average attenuation for each of the three types of probes investigated. The Thble 2 data was derived from comparing sine wave
(SO ~ coaxial) and active circuit probe frequency/attenuation
signatures, and it reflects the most conservative data produced from
these two test methods. The active circuit chosen, a S.376 MHz,

TTL, square-wave hybrid oscillator, produced an output rich in harmonics, The controlled impedance data (sinewave, SO 0 coaxial)
was, of course, much more predictable. Though different circuits
will produce different data, it is felt that 1llble 2 can be considered
a general guide in probe frequency selection and can also be used
as an aid in bypass selection.
The base for either of these RF bypassing probes is a simple pair
of special tweezers, 1Weezers enable quick, one-hand, firm
mechanical connection to circuit points. They can be spread to reach
circuit points as much as 9 em (3.S in) apart, which will cover most
applications. Longer tweezers could be substituted for greater spans;
however, the increased blade inductance would have to be taken
into consideration as the bandwidth parameters would change. The
tweezer blades' inherent low impedance over the frequency range
tested (82 nH average) is low enough for them to be of practigaJ
use in this application, over the frequency range covered in this article. Figure I illustrates the tweezer assembly, and Fig. 2 is a photo
of a completed assembly.

G........ Ceutructl.........
I. The first problem is to split a pair of tweezer blades into two
halves. High-quality, spot-welded tweezers are very difficult to
split. The lower-quality type, listed in the 1llble 2 parts list, are
very easy to split as they are the unwelded, single-piece, foldover type. These are quite adequate for this application. If you
choose to split the high-quality variety, ! recommend drilling

Table 2-Tweezer Performance Chart

Table 1-Parts List
Qty.

Item

Part /I

Cost

1 ea

Tweezers

7948

S1.97

Epoxy. shrink tubing.

NIA

SO.10

NR

Vendor

(3/16 & 112").

Insulator. Wire
GENERAL, (an typee)

Fixed Probes
NR

CapaCitors. (Fixed)
. 220. 47, 20 10 pF

C40

Span In
MHz

Bandwidth
In MHz

Average
AIIen.,dB

220 pF

31·85

54

17

47 pF

70·129

59

13

Fixed

20 pF

108·150

42

11

Fixed

10 pF

140·220

80

11

Band·Swltching
(Low Band)

220 pF

21· 71

44

12

Bandswitching
(Mid Band)

39 pF

68·120

52

12

Bandswilching
(High Band)

20 pF

105·140

35

11

Tuning

25/150 pF

30·140

110

14

Higheat
'Freq.
X

Moat •
Convenient

Probe Type

Bypeas
Element

Fixed
Fixed

$0.43

SUMMARY

series

Beat BW
Tunable Probe
Tuning Capacitor
ARGO
(25 tp ,50 pF)

Probe
Arco 424

$1.20

Any

$1.95

CapaCitor 220, 39,
20 pF

C40

$0.43

Beat Allen.
In dB'

Fixed
X
X
Bandsw.
Tuning
X
• Based on 30 to 140 MHz Span
•• Evaluation based on a set of four fixed probes.
NOTE: Tweezer parameters derived from sine, and TTL square wave
. test Circuits, (worst case listed), and ar subject to variations from
circuit to circuit

BanctswHchlng Probe
Toggle Switch.
SPOT, Center Off

In MHz"

series

418

2.

3.

4.
.

out the spot welds first. After splitting the blades, you may want
to shape the tips on a grinding stone. For getting between narrow chip pins, these tips should be thin. Sharp points are also
helpful for good probe contact.
The next task will be to electrically isolate each tweezer blade
from the other and then to bond the two blades together. Sandwich a piece of thin insulator (a piece of wooden ice cream stick
25 mm [I inJlong will suffice) at the upper portion of and between the tweezer halves as shown in Fig. I. Secure the assembly
with alligator clips or shrink tubing. Be sure to keep the tweezer
tips parallel. Cover the top 3 mm (0.125 in) portion of the
assembly with a small piece of shrink tubing so that you will
have an epoxy-free area for soldering the capacitor later on.
Liberally coat all sides of the top 33 mm (1.3 in) of your
assembly with a generous amount of epoxy. Allow 24 bours
bardeninl time to ensure • lood set.
Choose the assembly you wish to build; i.e., fixed, tunable or
band-switching probe per llIble 2. Each probe type has its advantages and disadvantages in bandwidth covered, attenuation
characteristics and convenience. The chief advantage of the
band-switching and fixed probes are their non-tuning convenience. The chief disadvantage of the fixed probes is the need
to have more than one probe to cover a wider frequency range.
On the other hand, the tunable probe covers a wide range of
frequencies but requires tuning. Overall, the band-switching
probe offers the most convenience with a slight loss in attenuation capability. Personally, I have made good use of all three
types. Your situation, bandwidth of interest, etc. will be major
factors in this decision.
If you choose to build the single-element probe and, depending on the frequency range you wish to cover, you may want
to build three or more with different capacitive elements to cover
a wider frequency range. Please note that there is an upper frequency limit in the practicality of any of these probes, as covered
later in this article.

Power
Supply
14 Vdc

Arc to Too Le" CO'''e'

01 TNeeze'

Ground Blade Bemg Arced

Tweezers

-Caution If your power supply cannot Withstand a dlrecl snort yOu 'T'Jst ooe'"
5·' before arCing 10 the tweezer blades

Plxed......... P......, ...... Aue_1IIy
I. Referring to Fig. I as a general guideline, choose the capacitor
element you wish to solder to the tweezer blades. Note that the
upper frequency limit is roughly 300 MHz here, due to hand
capacitance, the basic tweezer capacitance of 10 pF average and
the tweezer blades' inductance of 82 nH average. The author
limited testing and use to 220 MHz.

Figure 3-Electro-Flux

Toggle Switch or Vanable Capacitor (if applicable)

Receiver Analyzer

..~~~

30-220 MHz

Apply Tweezers Across Center
Terminal and Common

Insulator Dimensions:
length - Approx. 25 mm (1 In)
Width - 6.4 mm (0.250 In) mm
Thickness· 3.6 mm (0.142 m)·
Malerial . Wood• Authors choice. Different thicknesses or dielectriCS (wood In thiS case) Will
alter the parameters given in Table 2. If you do not Wish to experiment, use
a wooden coffee stirrer
"C": capacitive Element on Fixed Probes

Figure 1-Tweezer Assembly (Typical)

Figure 4-Probe Testing Setup

419

2. Solder the capacitor across the top of each of the tweezer halves
as in Fig. 1. Keep capacitor lead lengths short and use heat sinks
on them.
Note: Soldering to stainless steel tweezers requires a special
flux. ! tried several fluxes, induding ammonia, with no success. If you do not have the proper flux available, then try a
method ! call "electro flux:' Figure 3 shows a schematic for
the electrical part of this method. With this hookup, alternately
charge and then discharge the large electrolytic capacitor,
through a length of solder, to the top left corners of each tweezer
half. The arcing between the solder element and the tweezer
will eventually cause a solder buildup at this point. This buildup
will not be readily obvious, but it will be quite adequate when
tinned. For tinning, use a good electronic grade of rosin core
solder. A paste flux would also aid in this tinning.
3. Decide on the desired spread of the tweezer blades. For instance,
if the largest spread you will require is for a 4O-pin chip, then
spread your tweezer blades equally for a 50 mm (2 in) gap. Caution: when bending the tweezer blades, avoid putting excessive
stress on the epoxy bond.
4. Finish off the probe with shrink tubing on each blade and on
the top portion of the tweezer assembly to help reduce hand
capacitance effects and possible PC card shorts (should you
happen to drop the probe into a circuit card). Note: this top
covering could be of a removable type which would enable the
removal and soldering of different capacitors for experimental
purposes or to avoid building two or more probes to cover wider
frequency ranges.

1. Make the 50

Shvuld probing show little or no decrease in the observed EM I
at a particular circuit point, or be seen to increase the EMI at this
point, is generally an indication that this circuit point would not
yield to a successful, permanent EM! bypass fix. However, the points
which indicate a small decrease (3 or 4 dB) may be part of a dual
EM! problem, i.e., a circuit which has two or more problem areas.
Keep these points in mind if later probing is inconclusive. Such a
condition may require two or more permanent fixes. In any event,
with experience your probing analysis will keep time-consuming
"cut and try" methods to a minimum.
Any circuit point which indicates a moderate or large decrease
due to probing should be noted as a likely point for a permanent
EM! bypass fix. As will all things. experience will bring more
knowledge. As you use your probes more often, you will be able
to quickly determine those areas at which a permanent fix would
be successful. Also, you will be able to more accurately choose the
type and size of fix to use, i.e., a series or bypassing fix. Other types
of EM! fixes which might be required, such as shielding or grounding improvements, will also be determined by these methods.

Tuning Probe
I. Refer to the previous "general construction" and applicable

"fixed probe" paragraphs to create a completed tweezer
assembly, minus the capacitive element. One exception here
would be to apply the shrink tubing on the tweezer blades before
joining them. Shrink tubing should stop approximately 25 mm
(1 in) from the top of each blade for bonding purposes.
Remove any unneeded mounting parts from the bottom of
the variable capacitor so that it will fit as closely as possible
to the tweezer blade. You may also want to consider a clearance
hole in the tweezer blades for the bottom of the capacitor's adjustment screw. Be sure the variable capacitor's active paris do
not come in contact with either of the tweezer blades.
Solder the variable capacitor to the upper half of the tweezer
blades. Solder one element of the variable capacitor directly
to a tweezer blade. The other half of the capacitor element will
have to be soldered through a short length of wire. Keep this
wire as short as possible to hold your usable bandwidth as wide
as possible.
It is good practice to have the movable portion of the variable
capacitor (rotor) as the circuit ground connection. The rotor
part of the tweezer assembly can easily be identified by stripping back a longer piece of the shrink tubing on the tip portion of the rotor's tweezer blade.
2. Carefully epoxy the variable capacitor to a tweezer blade.. Be
sure not to get epoxy on any of the capacitor's moving parts.
Allow ample hardening time, then cover the assembly with
shrink tubing. Be sure the shrink tubing allows for free move··
ment of the capacitor's moving parts. The minimum movement
of the assembly must allow for three full turns on the variable
capacitor's adjustment screw.

n coaxial test setup shown in Fig. 4.

2. Connect your probe across the open end of the coaxial "Tee"
connector.

3. Your readings, being in a controlled impedafice test circuit, will
only approximate the data listed in Table 2, which was derived
by comparing data from differing circuits and indicates the
worst-case effects of that comparison.
4. Of course, if you are testing the tunable probe, you will have
to tune for each frequency being tested to get maximum
attenuation.

U.e .f the Single.Ele... en. Probe
As a typical use of the probe would be in chasing down radiated
EM! signals, the following will cover that aspect of its use. Adjustments can be made for other situations.
Caution: Do not use these probes in circuits containing
voltages in excess of 50 Vdc.
I. Begin by tuning in the EM! signal in question. Determine its
exact frequency. A schematic analysis of various EM! harmonic
frequencies or circuit probing with a "sniffer probe" (see Table
1) will determine the location of suspected circuit points which
might be generating the offending frequencies.
2. Assuming a typical radiated test setup using an antenna for
a pickup device and a receiver/analyzer to observe the EM!,
tune in the EM! signal to be investigated and use your tweezer
probe to probe the suspected circuit "hot spots" as determined
in stell I, above.
Note: As you are using a bypass device, one blade of the
tweezer must be in firm contact with a circuit common point,
and the other blade should be in contact with the circuit point
under investigation. The best common point is generally the
common pin on the chip being probed.

Using the Tuning Probe
1. With your radiated test setup intact, place a "Tee" coaxial adap-

tor at the input of the receiver/analyzer.
2. Tune in the EM! signal to be investigated.
3. Connect your tuning probe across the open end of the coaxial
"1ee" and tune the variable capacitor for a minimum signal
as observed on your receiver. For maximum attenuation due
to circuit detuning, an optional, additional in-circuit tweak
might be desirable.
Note: Resonant tuning begins at approximately 60 MHz and
ends around 130 MHz. Frequencies below 50 MHz are probed
with the adjusting screw fuliy clockwise (tight). Likewise, fre-

420

quencies above 130 MHz are probed with mlmmum capacitance (three turns
counterciock;wise on the adjustment screw). The frequencies from 60 to 130 MHz
should be tuned to resonance (minimum amplitude as seen on your receiver/analyzer).
Of course, different assemblies will vary somewhat from these parameters.
Your tuning probe is now tuned for optimum attenuation at the EMf frequency
under investigation.
4. Refer to the preceding section, "Using the Single-Element Probe!' for a guide to
probing .

.......w ..............
The band-switching probe was the next obvious step in the evolution of these probes.
It performs quite well and is very convenient to use.
I. Proceed with the basic construction steps as outlined in the "general construction"
paragraphs, with the exception of leaving an epoxy-free area for mounting the band
switch and applying the shrink tubing on the tweezer blades before bonding.
2. Mount, secure and epoxy the band switch to on!: of the tweezer blades (see Fig. I).
Allow ample hardening time for the epoxy.
3. Referring to Fig. 5, mount the three capacitors as shown and wire the band switch.
Use the capacitor leads for wiring, keep lead lengths short and apply heat sinks to
the capacitors before soldering. Note that capacitor logic is single capacitor, series,
hand series parallel (moving toggle from left to right). This method was chosen to
obtain closer overlapping bands and to take advantage of the band switch's terminals
for mounting the capacitors.
4. Cover the capacitors and exposed band switch terminals with heat shrink tubing.

u......... B....-SwIkhIIIw .......
Use this probe as with the fIXed probes, with the exception of the band-switching feature.
If wired as shown in Fig. S (pictorial view), and if you are using a typical toggle switch,
the low band will be with 'the toggle left of center, the high band will be with the toggle
in mid position (oft), and the mid band will be with the toggle in the far-right position.
Note: If it is desired to know the actual capacitance involved in a particular fixedprobe effect, simply add IS pF (residual capacitance of the tweezers when constructed as per Fig. I) to the probe's capacitive element value. The capacitance of
the tuning probe, however, would have to be measured. For the band-switching
probe, being series and series parallel wired, add the IS pF to the following:
Low band, 220 pF
Mid band, 47 pF
High band, 19 pF
This information is useful when looking for a minimum capacitance for a permanent bypass fix when working with a circuit which cannot drive a large
capacitance without unacceptable distortion of the wave shape. III

cSd

Blade

Ic"

Blade

Mid Band

C-3

To One
Tweezer Blade

.

C,2

Low Band

5·' Spot Center Oft
Center

= High Band

C1 = 220 pF
C2 ; 39 pF
C3;;:;20pF

Figure 5-Bandswitching Wiring
Note: the probes discussed in this anicle are also available in pre-built fonn. For a price list and
ordering informatinn, contact F&M Electronics, 41 Chestnut St., Seymour, cr 06483, (203) 888-4847.

421

422

AN1055
M6805 16-Bit Support Macros

If your mlcrocontroller (MCU) application requires a small
amount of program memory and not much raw computing
power, the M6805 MCU Family IS a most logical choice, given
their low cost. But do not cross the M6805 Family off your selection list Just because you need some 16-bit indexing and/or
16-bit operations, such as the higher cost M68HC 11 Family
provides. While the 8-bit X index register of the M6805 Family
cannot access the entire M6805 12/13-bit address space and
its single 8-bit accumulator cannot directly do 16-bit operations, advanced software techniques can be employed to work
around the limitations of the M6805 Family. This application
note gives specific details and examples of these techniques.
The code samples given here are available in source code
form on the Motorola FREEWARE Bulletin Board Service
(BBS), by telephoning 512/891-FREE (512/891-3733). The
FREEWARE line operates continuously (except for maintenance) at 300-2400 baud, 8 data bits, 1 stop bit, and no parity.
Sample test files are also included. Download the arclllVe file,
MACROS05.ARC, to get all the files. All files are suitable for
use with the Motorola Development Systems M6805 Portable
Assembler for MS-DOS, known as PASM05. Other assemblers may also be supported, but consult the BBS for details.
The techniques used here involve a combination of macros
and RAM-based subroutines which use instruction modification. Macros allow programming on a higher level of thought
with less chance for Introducing errors.
Instruction modification is a technique of altering an instruction just prior to its execution. The modification requires that
the instruction be in RAM and can involve the opcode and/or
the operand portion of the instruction. By determining the exact Instruction/operand needed in advance of execution,
greater efficiency in execution speed and code size can be obtained. There is a significant risk in uSing the instruction modification technique because if used improperly, the program will
either fail to work properly at best, or crash at worst. When the
technique is used, great care must be exercised to ensure correct operation in all possible cases.
To illustrate the instruction modification technique, consider
the following instruction at location $0050 In RAM memory.
0050

C6

04FF

LOA

0870
0872
0874
0872

A6
B7

A6
B7

05
51
2C
52

LOA
STA
LDA
STA

#$05
$51
#$2C

$52

These Instructions store $05 into location $0051 and $2C
into location $0052. which IS the operand address of the opcode byte at Illcatlon $0050. This has the effect of changing
the instruction at location $0050 to the following
0050

C6

052C

LOA

$52C

When location $0050 is executed. the A accumulator Will
now be loaded With the contents of location $052C. i.e .. the Instruction at location $0050 has been modified I Note that the
original source listing Will only show "LOA $4FF". as the instruction is only changed at execution time. not assembly time.
When instruction modification is used in a ROM-based system, the RAM code must be initialized (from the ROM) before
being used. This can be as Simple as a few LOAD/STORE In
structions for a small routine. or a MOVE BLOCK routine may
be required for larger routines.
As with all things of value, there is a price to be paid The
price for using these macros IS rather smali, namely, 23 bytes
(16 for RAM subroutines and 7 for local storage) of direct addressing memory, :.e .. In the range of $O-$OOFF. The macros
have a small size/execution speed penalty assOCiated with
them that varies from zero to 50 percent, depending on the frequency and type of macros used. An estimated tYPical cost for
an entire program With moderate macro usage would be In the
5to 20 percent range. Butthis is small cost to pay for error-free
code generation in areas of the program where speed is not
critical. By judicious usage/choice of macros, the cost can be
held closer to the 5 percent range.
Part of this cost is associated with the structured code technique of preserving registers and another part IS involved witi~
setting up the proper condition codes. The rest of the cost is
inherent in the fact that M6805 MCUs must do extra work in
software to simulate the hardware capabilities built in
M68HCll MCUs.
Because these macros have been
fine-tuned for size and speed effiCiencies. the overhead cost of
register preservation is typically 4 bytes and the overhead cost
of condition code setting is typically 2 to 4 bytes, per macro invocation. It can be as high as 200 percent. as IS the case of the
MOV B macro for extended addreSSing operands (16 versus 8
bytes if no register preservation!conditl~,r· code initialization IS
done) or as low as zero percent for direct addreSSing operands.

$4FF

The LOA instruction consists of three bytes: an opcode byte
($C6) and two bytes that hold the extended address ($04FF) of
the operand. When executed, the A 'accumulator will be
loaded with the contents of location $04FF. Now consider what
happens when the following instructions at location $870 are
executed and ho·.· the' previous memory locations are
changed.

423

4. Write your source code using the example shown in the
Notes header of the MACROS05.MAC file, as illustrated
in Listing 1. lines 1030-1460. If the two ORG statements,
lines 1130 and 1180. are not valid for your application's
memory map. change them to the appropriate values.
Notice especially how the initialization of the RAM subroutines is accomplished by the MOVE macro in line
1200 using the ROM code generated by the INCLUDE
statement in line 1400. Or you can expand the BBS EXAMPLE.S file into your source file by first making a copy
of it and then editing the copy as shown below (PE is the
IBM Personal Editor command, but you can use any editor you feel comfortable with).

The DREG macros have almost no overhead associated
with them since the DREG is implemented using the already
existing A and X registers. The overhead price for DREG macros is only 2 bytes of local storage (TEMPA$. TESTA$). because the RAM subroutines are only needed for XREG and
YREG support. The Add and Subtract DREG macros (ADDD.
SUBD) have the most overhead because they must save and
restore a working register (A). but even this is rather minimal. If
only DREG macros are used. it is estimated that the code size
could expand from zero to 5 percent over straight assembly
language. depending on how many and which type of DREG
macros are used.
The XREG and YREG macros have the most overhead.
since they are implemented using RAM memory locations.
The Load and Store via XREGIYREG macros (LDAXY.
STAXY) have the most overhead when nonzero offset values
are used (26 bytes versus 2 bytes for zero offset. or 1300 percent). Thus. nonzero offset usages should be avoided unless
absolutely necessary. There is also some inefficiency associated with internally maintaining two copies of each register.
but it actually helps in the overall implementation.
The Increment. Decrement. and Move macros (INC.B.
INC.W. DEC.B. DEC.W. MOV.B. MOVEW. MOVE) have zero
to high overhead. The DEC.B and INC.B macros have zero
overhead when used with direct addressing operands, while
the INCW and DEC.W macros have high overhead due to setting the proper condition code based on the resultant 16-bit
value.
To use these 16-bit macros. here is a quick summary of the
steps involved for use on an IBM-PC with the Development
Systems PASM05 macro assembler, which should already
have been installed perthe instructions supplied with the product. The sample MS-DOS commands are shown in upper
case for clarity only (except as noted). as MS-DOS accepts either upper or lower case.

C>COPY EXAMPLE.S MYFILE.S
C>PE MYFlLE.S

5. Invoke PASM05 to assemble your new source file as
shown below. Because the options for PASM05 are case
sensitive. be sure to enter them just as shown.
C>PASM05 -eq -1 MYFlLE.LST MYFlLE.S

This produces listing file MYFILE.LST and a COFF relocatable object file MYFILE.O.
6. To produce an absolute S-record object file suitable for
programming an EPROM, the COFF relocatable object
file must first be linked to an absolute object file (MYFILE.OUT) and then converted to an S-record file (MYFILE.MX), which many commercial EPROM programmers, such as Data 110, recognize. Enter the commands
shown below to create the S-record file.
C>PLD -0 MYFILE.OUT MYFILE.O
C>UBUILDS MYFlLE. OUT

1. Create a new directory for your project and change directory to it as shown below.

Steps 5 and 6 can be simplified by copying and editing the
BBS batch file, MAKE1.BAT, in a manner similar to that
shown in Step 4, except here we want the new batch file,
MAKE.BAT, to process MYFILE instead of TESTI. The
resultant MAKE. BAT file should be similar to the text
shown below. The two DEL commands at the end are optional, as these files are no longer needed.

C>MKDIR PROJ
C>CD PROJ

2. Download the archive file, MACROS05.ARC, from the
Motorola FREEWARE Bulletin Board to your project directory and then de-archive it as shown below. See the
FREEWARE bulletin file, archive.bul, for de-archiving information.
C>PKARC

pasm05 -eq -1 myfile.lst myfile.s
pld -0 myfile.out myfile.o
ubuilds myfile.out
del myfile.o
del myfile.out

MACROS05. ARC

To accomplish Steps 5 and 6, invoke the batch file
MAKE.BAT by simply typing its name as shown below.
MS-DOS will execute each line of the file as if you had
typed it on the keyboard.

3. Read the READ.ME file first, and then read the Notes
header in the MACROS05.MAC and RAMSBR.INI files.
In the MACROS05.MAC file, study the individual macro
headers of the macros you intend to use, especially the
examples shown.

C>MARE

424

7 Consult your EPROM programmer's user manual
for how to load the resultant S-record object file
(MYFILE.MX) and program your chosen device
Because of the length of the source listings Involved and because these listings are intended to be self-explanatory, the
rest of thiS diSCUSSion will only deal with salient points which
might need clarification for the reader. Line numbers have
been added at the beginning of each line for Identification purposes In thiS Application Note, I.e., they are not present In the
actual source file.
These macros have been written so that any syntax error will
result In failing to the end of the macro where the FAIL directive
will force a "Macro syntax error detected I" message. Proper
usage results in eXiting the macro early via the MEXIT directive
and thus aVOids the FAIL directive at the end
The file header of Listing 1 (lines 20-1800) gives speCific
details of the macros supported and their general operation
and restrictions. Line 1810 defines where a seven byte block
of low memory will be allocated for support of these macros
(see lines 20430-20490) line 1830 disables the output listing
to avoid repetitious output. while line 19630 re-enables the listing.
A lot of conditionals (IFxx) Involve testing to see if direct addreSSing can be used, as It is more efficient (one less byte and
one less execution cycle per instruction) than extended addressing, as Illustrated by lines 2090-2210. Also, conditionals
check to see if shorter instruction forms can be used, like
"CLRA" instead of "LDA #0", as in these same lines. For this
same reason, it IS most effiCient to place the RAM subroutines,
and thus the XREG and YREG, into direct addressing space
($OOOO-$OOBF) Remember that the M6805 uses a fixed stack
area In direct addressing space of $OOCO-$OOFF
The COMPARE macros (CPD, CPXR, CPYR) use a shortened form when Immediate addressing is specified and either

425

of the halves is zero, i.e., no "CMP #0" instruction is generated.
lines 3480-3660 are typical of thiS technique. As always, testing for zero is most efficient in computel architecture
The 16-BIT INDEXING macros (LDAXY, STAXY) are most
effiCient when used with a zero offset, as typified In lines
3980-4060, but will' function With any sized offset (lInes
4070-4210). Nonzero offsets must first be added to the indexIng register (XREG or YREG), the operation performed via the
appropriate RAM subroutine, and lastly, the Indexing register
must be restored to its original value.
Lines 19640-20410 comprise the RAM subroutines which
are the keystone of the macros using the XREG and YREG
pseudo 16-bit index registers. It is here that the XREG and
YREG pseudo-registers are defined and stored as the second
and third bytes of extended addressing LDA and STA instructions using EQU directives (lines 19910-19920,20060-20070.
20210-20220, and 20360-20370). Instructions that store values to XREG or YREG will thus modify the instruction's effective address, hence the name Instruction modification. These
RAM subroutines must be initialized before they can be used.
and so a mirror Image of this code With altered labels is provided In the RAMSBR.INI file (as seen in Listing 2). ThiS file
can then be simply INCLUDED in the ROM section of the
user's code and copied to RAM via the MOVE macro, as diScussed in lines 19660-19760 of Listing 1.

Listing 2 is the RAM subroutine Initialization file and is essentially a copy of the RAM subroutines defined in lines
19640-20410 of Listing 1, but the labels have all been prefixed
with a period (.). This allows using the MOVE macro to copy
this RAM initialization code from a ROM to RAM (see lines
370-410).
Lines 1070-1 090 verify that the number of RAM subroutine
initialization bytes is identical.

Listing 1 - MACROS05.MAC File
00010
00020
00030
00040
00050
00060
00070
00080
00090
00100
00110
00120
00130
00140
00150
00160
00170
00180

PAGE
**************************************************************************************
* macrosOS.rnac
1.0
• Module Name;

* Description:
Th1S file conta~ns macros and subroutines to support pseudo-registers
on the 6805 that s1mulate registers and addressing modes available on
the 68HCll.
It is suitable for "black box" operation, i.e., the
macros may be used without knowledge of how they work. A list of the
supported macros follows.
Consult the individual macro headers for
usage datal.Is and see the "Notes" below.
LDD
STD
ADDD
SUBD
CPD
LDAXY
STAXY
LDXR
STXR
INCXR
DECXR
CPXR
LDYR
STYR
INCYR
DECYR
CPYR
DEC.B
DEC.W
INC.B
INC.W
MOV.B
MOV.W
MOVE

CO::" 90

20220
00230
00240
00250
00260

::290
00300
00310
00320
00330
00340
00350
00360
00370
00380
00390
00400
00410
00420
00430
00440
00450
00460
00470
00480
00490
00500
00510
00520
00530
00540
00550
00560
00570
00580
00590
00600
00610
00620

MACROS05 - M6805 Macros

Load DREG
Store DREG
Add
DREG
Add
DREG
Compare DREG
Load A via 16-bit pseudo-register (XREG or YREG)
Store A via 16-bit pseudo-register (XREG or YREG)
Load XREG
Store XREG

Inc.rement XREG
Decrement XREG
Compare XREG
Load YREG
Store YREG
Increment YREG
Decrement YREG
Compare YREG
Decrement byte
Decrement word
Increment byte
Increment word
Move byte
Move word
Move block of memory

* General Information:
The following pseudo-reg~sters are supported.
DREG
pseudo 16-·bit accumulator (A, X registers, A is MS half)
XREG
pseudo 16-bit index reg1ster
YREG
pseudo 16-bit index register
The follow1ng terms are used.
#
specifies ~mmediate addressing mode
address/value operand (absolute or immediate) unsigned IS-bit offset for indexed addressing * Notes: I.Motorola reserves the right to make changes to this file. Although this file has been carefully reviewed and is believed to be reliable, Motorola does not assume any liability arising out of its use. This code may be freely used and/or modified at no cost Ol~ obligation by the user. 2. This fiJ.e was made for use with the Motorola Development Systems MC6805 Portable Assembler/Linker for MS-DOS, known as PASM05 and PLD, as released on 82HCVBASM B* and 82HCVBLNK B* Consult the PASM and PLD reference manuals, part numbers M68HASM/D1 and M68HLINK/Dl for more details. 426 00630 00640 00650 00660 00670 00680 00690 00700 00710 00720 00730 00740 00750 00760 00770 00780 00790 00800 00810 00820 00830 00840 00850 00860 00870 00880 00890 00900 00910 00920 00930 00940 00950 00960 00970 00980 00990 01000 01010 01020 01030 01040 01050 01060 01070 01080 01090 01100 01110 01120 3 These macros were made for ABSOLUTE assemblies only, i.e., for use with ORG directives. While most of the macro concepts will work in relocatable assemblies (BSeT, DSCT, PSCT, ASeT, XDEF, and XREF) , errors will be generated because PASM limits the use of external symbols in expressions and because the value of an expression must be known at assembly time for IFxx d~rectives to assemble the proper code. The first restriction is a resu.lt of limitations in the COFF object file format. If it is desired to have these macros work with relocatable assemblies, modifications sirnJ..lar t.o below should be made, but be forewarned of the increased inefficiencies in size and speed. Consider the following code to change the LDD macro so that an XREF parameter, \1, can be loaded as an immediate value. LDA \. 8 LDX \ 8+1 \.9 BRA \.8 FDB \1 \.9 EQU 4. In order to efficiently support both LOAD and STORE operations for the pseudo 16-bit index registers, there are actually two such "registers", i.e., one for LOAD and one for STORE as defined below. These routines maintain both "registers" with the same value, and so the programmer may think of them as one register. XREG1$ 16-bit XREG for LOAD operat~ons XREG2$ 16-bit XREG for STORE operations YREGl$ 16-bit YREG for LOAD operations YREG2$ 16-bit YREG for STORE operations 5 These macros can be used to create in-line code (speed effiCient) or they be placed in a subroutine (byte efficient) 6. Instruction modified code is used here and is denoted by use of the un~que string "0-0" (RAM subroutines) . 7. Some macros use temporary storage locations (TEMPA$, TESTA$, etc ), so these macros should not be used in any interrupt routine in order to avoid corrupted values! B.The user must ensure that the code is appropriately placed ~n the target M680S's memory map, i.e., the RAM subroutines MUST be located in RAM but must not overlap the stack area ($OOCOSee OOFF) unless it can be GUARANTEED there is no conflict~ LO$MEM below to set low memory data storage area' 9.To use thl.s file, either use an INCLUDE statement or just merge this file into your source code file. Consult your assembler's user's manual for the details specific to your situatior~. When using a ROM controlled system, the MOVE macro should be used to copy the RAM subroutines from ROM to RAM (see the comments after where RAMSBR$ is def:!..ned below and note the INCLUDE statement for the RAMSBR.INI f~le) Reference the code segment example below for usage ideas (shown in PASM05 for MS-DOS syntax). 01130 01140 01150 01160 01170 01180 01190 01200 01210 01220 01230 01240 01250 01260 TOTAL RTABL~: ORG $50 RMB RMB 2 5 Ml\.CROS05 MAC INCLUDE RESET START ORG RSP MOVE M07.W LDD ACDD SUBD $400 # .RAMSBR$,#,RAMSBR$,#,RAMSZ$ #,O,TOTAL COST !I,~OOO # AD.JUST TOTAL i STDD 427 Init ram. 01270 01280 01290 01300 01310 01320 01330 01340 01350 01360 01370 01380 01390 01400 01410 01420 01430 01440 01450 01460 01470 01480 01490 01500 01510 01520 01530 01540 01550 01560 01570 01580 01590 01600 01610 01620 01630 01640 01650 01660 01670 01680 01690 01700 01710 01720 01730 01740 01750 01760 01770 01780 01790 * * * * * * * LOOP * * * * * * CPD BEQ #,1500 MATCH LDXR LDYR LDAXY STAXY INCXR INCYR CPY BNE #,0 #,0 TABLE,XREG RTABLE,YREG INCLUDE FCB FDB FDB RAMSBR.INI 1,2,3,4,5 150 859 #,5 LOOP * * * TABLE ADJUST COST * * * * * * * END 10. * * 11. * * * * * * * assembler generates a unique label to avoid 12. * * * * * * * * To assemble, use the following sample invocation lines: pasm05 -eq -1 filename. 1st filename.s (debug= expanded) or pasm05 -bf -1 filename. 1st filename.s (black box) Notations used by PASM05 are as follows: OPERATORS: Special two character operators used are ... 1 . Logical AND 2. Shift Right (0 fill on left) ,> MACROS: Special notations used are . .. 1. Parameters are positionally named using \0, \1, \2, etc. 2. Labels within macros are designated via \.a, where "an is an alphanumeric character. The multiply defined label problems. Some macros access 16-bit values as LS byte then MS byte in order to be more efficient for condition code (CC) setting. This is the reverse order that the 68HC11 would access the two byte halves. This difference would only be a concern in accessing hardware registers, as normal RAM makes no difference. Those macros with this difference have an entry in their Notes section. 13. The latest version of this file is maintained on the Motorola FREEWARE Bulletin Board, 512/891-FREE (512/891-3733). It operates continuously (except for maintenance) at 1200-2400 baud, 8 bits, no parity. Sample test files for PASM05 are also included. Download the archive file, MACROS05.ARC, to get all the files. ************************************************************************************** * REVISION HISTORY (add new changes to top) : * 05/16/90 P.S. Gilmour 1. Created for Application Note AN1055. * 01800 ******************************************************* •• ********* •••••••••••• ******** 01810 01820 LO$MEM EQU $00CO-7 Low memory ($OOOO-OOFF) storage (7 bytes) 428 01830 OPT NOL 01840 ************************************************************************************** 01850 • LDD = load DREG 01860 LDD [#,]
01870 01880 • Examples: 01890 1. "LDD I,START" puts the value of symbol 'START' into 01900 the DREG (=A, X) . 2. "LDD START" 01910 puts the contents of location 'START' and 'START'+l into the DREG (=A,X). 01920 • 01930 01940 * Register Usage: 01950 A,X = loaded with new value (DREG). 01960 • CC = reflects MS half (=A). 01970 All other registers preserved. 01980 01990 * Notes: 02000 1.Byte access order is LS, then MS (reversed from 6aRell). 02010 02020 LDD MACR 02030 IFEQ NARG-l 02040 LOX (\0)+1 LOA 02050 (\0) 02060 MEXIT 02070 ENDC NARG-2 IFEQ 02080 IFC 02090 '\0' , 'I' IFEQ (\1) 1 • $FF 02100 02110 CLRX 02120 ENDC IFNE (\1) 1 • $FF 02130 02140 LOX #(\l)I.$FF ENDC 02150 (\1) 1 >8 IFEQ 02160 02170 CLRA ENDC 02180 IFNE (\1) !>8 02190 LOA 02200 #(\1)'>8 02210 ENDC MEXIT 02220 02230 ENDC 02240 ENDC 02250 FAIL Macro syntax error detected! 02260 ENDM 02270 02280 ********************************************************************.***************** 02290 * STD = store DREG 02300 * STD
02310 02320 * Examples: 02330. 1. "STD START" stores the DREG (=A,X) into locations 'START' and 'START'+l. 02340 • 02350 02360 * Register Usage: 02370 CC = reflects MS half (=A). 02380 All other registers preserved. 02390 02400 • Notes: 02410 1. Byte access order is LS, then MS (reversed from 68HCll). 02420 • 02430 STD MACR 02440 STX (\0) +1 02450 STA (\0) 02460 ENDM 02470 • • 429 02480 02490 02500 02510 02520 02530 02540 02550 02560 02570 02580 02590 02600 02610 02620 02630 02640 02650 02660 02670 02680 02690 02700 02710 02720 02730 02740 02750 02760 02770 02780 02790 02800 02810 02820 02830 02840 02850 02860 02870 02880 02890 02900 02910 02920 02930 02940 02950 02960 02970 C2980 02990 03000 03010 03020 03030 03040 03050 03060 03070 03080 03090 03100 03110 ********************************************~***~***** ******************************** * ADDD = add * ADDD * * Examples: * 1. "ADDD * 2. "ADDD DREG [#, ]
n,. STAR'f" START" adds the value of synmol 'START' to the DREG (=A, X) . adds the contents of locat~on 'START' and 'START'+l to the DREG (=A,X). * Register Usage: A,X = contains new value (DREG). CC = reflects MS half (=A). All other registers preserved. * ADDD MACR IFEQ NARG-1 STA TEMPA$ TXA ADD (\0) +l TAX LOA TEMPA$ (\0) ADC MEXIT ENDC IFEQ NARG-2 IFC '\0' , '#' STA TEMPA$ TXA ADD #(\1) '.$FF TAX LOA TEMPA$ ADC #(\1)'>8 MEXIT ENDC ENDC FAIL Macro syntax error detected! ENDM ************************************************************************************** * * SUBD SUBD add DREG [#,]
* Examples: * * I. "SUBD #,START" 2. "SUBD START" subtracts the value of synmol 'START' from the DREG (=A,X). subtracts the contents of location 'START' and 'START'+1 from the DREG (=A,X). * Register Usage: * A,X = contains new value (DREG). CC = reflects MS half (=A). All other registers preserved. SUBD MACR IFEQ NARG-l STA TEMPA$ TXA SUB (\0)+1 TAX LOA TEMPA$ SBC (\0) MEXIT ENDC 430 03120 03130 03140 03150 03160 03170 03180 03190 03200 03210 03220 03230 03240 03250 03260 03270 03280 03290 03300 03310 03320 03330 03340 03350 03360 03370 03380 03390 03400 03410 03420 03430 03440 03450 03460 03470 03480 03490 03500 03510 03520 03530 03540 03550 03560 03570 '03580 03590 03600 03610 03620 03630 03640 03650 03660 03670 03680 03690 IFEQ NARG-2 IFC '\0' , 'I' STA TEMPA$ TXA SUB #(\1)' .$FF TAX LDA TEMPA$ SBC #(\1) !>8 MEXIT ENDC ENDC FAIL Macro syntax error detected! ENDM ************************************************************************************** compare DREG * CPD [I, ]
* CPD * Examples: 1. "CPD #, BLOCKSZ" 2. "CPD START" compares the value of symbol 'BLOCKSZ' with the DREG (=A,X). compares the contents of location 'START' and 'START'+l with the DREG. * Register Usage: * CC = reflects DREG comparison (Z-bit only) . All other registers preserved. * CPD MACR IFEQ NARG-1 (\0)+1 CPX BNE \.0 \.0 CMP (\0) EQU MEXIT * ENDC NARG-2 IFEQ IFC '\0' , 'I' IFEQ (\1) ! . $FF TSTX ENDC IFNE (\1) ! . $FF CPX #(\1) !.$FF ENDC BNE \.0 IFEQ (\1) !>8 TSTA ENDC IFNE (\1) '>8 CMP #(\1)!>8 ENDC \.0 EQU * MEXIT ENDC ENDC FAIL Macro syntax error detected! ENDM 431 03700 03710 03720 03730 03740 03750 03760 03770 03780 03790 03800 03810 0382.0 03830 03840 03850 03860 03870 03880 03890 03900 03910 03920 03930 03940 03950 03960 03970 03980 03990 04000 04010 04020 04030 04040 04050 04060 04070 04080 04090 04100 04110 04120 04130 04140 04150 04160 04170 04180 04190 04200 04210 04220 04230 04240 04250 04260 .*.................................................... * * * * * * * * * * * * * * * * * * * ******************************** LDAXY = load A via l6-bit pseudo-register (XREG or YREG) LDAXY ,XREG LDAXY ,YREG Examples: 1. "LDAXY O,XREG" loads the contents of the memory location specified by XREG+O into the A accumulator. 2. "LDAXY ,XREG" loads the contents of the memory location specified by XREG+O into the accumulator. 3. "LDAXY TBL,XREG" loads the contents of the memory location specified by XREG+'TBL' into the A accumulator. 4. Above examples can be repeated with substituting YREG for XREG. Register Usage: A loaded with new value. DREG = destroyed. CC = reflects value loaded. All other registers preserved. LDAXY MACR '\1', 'XREG' IFNC IFNC '\1' , 'YREG' FAIL Macro syntax MEXIT ENDC ENDC '\0' , •• IFC JSR LDA\l MEXIT ENDC IFNC '\0' I I ' IFEQ \0 JSR LDA\l MEXIT ENDC IFNE \0 LDA \11$+1 ADD I/(\O)!.$FF STA \11$+1 LDA \11$ ADC 1/(\0)!>8 STA \11$ JSR LDA\l STA TEMPA$ LDA \12$ STA \11$ LDA \12$+1 \11$+1 STA LDA TEMPA$ MEXIT ENDC ENDC FAIL Macro syntax ENDM error detected! Default offset= 0 Offset= 0 Set nREG= offset + nREG Offset= 0 Restore nREG error detected! 432 04270 04280 04290 04300 04310 04320 04330 04340 04350 04360 04370 04380 04390 04400 04410 04420 04430 04440 04450 04460 04470 04480 04490 04500 04510 04520 04530 04540 04550 04560 04570 04580 04590 04600 04610 04620 04630 04640 04650 04660 04670 04680 04690 04700 04710 04720 04730 04740 04750 04760 04770 04780 04790 04800 04810 **************************************.*.********************************* * STAXY = store A via l6-bit pseudo-register (XREG or YREG) * STAXY ,XREG STAXY ,YREG * * Examples: * 1. "STAXY 0, XREG" * * * * * * * * * stores the accumulator (=A) into the memory location specified by XREG+O. 2. "STAXY ,XREG" stores the accumulator (=A) into the memory location specified by XREG+O. 3. "STAXY TBL,XREG" stores the accumulator (=A) into the memory specified by XREG+'TBL' 4. Above examples can be repeated with substituting YREG for XREG. Register Usage: CC = reflects value stored. All other registers preserved. STAXY MACR IFNC '\1' , 'XREG' IFNC '\1', 'YREG' FAIL Macro syntax error detected! MEXIT ENDC ENDC IFC '\0' ," JSR STA\1 Default offset= 0 MEXIT ENDC IFNC '\0'," IFEQ \0 JSR STA\1 Offset= 0 MEXIT ENDC IFNE \0 STA TENPA$ LDA Set nREG= offset + nREG \12$+1 ADD !t(\0) ! . $FF STA \12$+1 LDA \12$ ADC #(\0) !>8 STA \12$ LOA TENPA$ JSR STA\1 Offset= 0 LOA \11$ Restore nREG STA \12$ LOA \11$+1 STA \12$+1 LOA TENPA$ MEXIT ENDC ENDC FAIL Macro syntax error detected! ENDM 433 04820 * * * * * * * * * ** * ** * * */* * * ** .. ** * * ** * * * * * * *: *.* * **** * * ** * ** * * * ** * * * * ** * ** * * ** ** **** ** * *.• * ** * * * * 04830 * LOXR = load XREG 04840 * LDXR [#, 1
04850 * 04860 * Examples: puts the value of symbol 'START' into the 04870 * 1. "LOXR #, START" XREG. 04880 * puts the contents of location 'START' and 2. "LDXR START" 04890 * 'START'+l into the XREG. 04900 * 04910 * 04920 * Reqister. Usaqe: 04930 * CC = reflects MS half (=A). 04940 * All other reqisters preserved. 04950 * 04960 * Notes: 04970 * 1. Byte access order is LS, then MS (reversed from 68RCll) . 04980 * 04990 LOXR MACR 05000 IFEQ NARG-l 05010 STA TENPA$ 05020 LOA (\0)+1 05030 STA XREG1$+1 05040 STA XREG2$+1 05050 LOA (\0) 05060 STA XREG1$ 05070 STA XREG2$ IFEQ XREG1$! .$FFOO 05080 LOA TENPA$ 05090 TST XREG1$ 05100 05110 ENDC 05120 IFNE XREGl$ ! . $FFOO STA TESTA$ 05130 LOA TENPA$ 05140 05150 TST TESTA$ 05160 ENDC 05170 MEXIT ENDC 05180 IFEQ NARG-2 05190 05200 IFC '\0' , '/I' ! XREG in low memory? 05210 IFEQ XREG1$!. $FFOO 05220 'IFEQ \1 ! #0 value? CLR XREG1$+1 05230 CLR XREG2$+1 05240 CLR XREG1$ 05250 CLR XREG2$ 05260 05270 MEXIT ENOC 05280 ! not #0 value? \1 05290 IFNE TENPA$ 05300 STA (\l)!.$FF IFEQ 05310 CLR XREG1$+1 05320 CLR XREG2$.+1 05330 05340 ENDC IFNE (\1) ! . $FF 05350 #(\1)! .$FF LOA 05360 XREG1$+l 05370 STA STA XREG2$+1 05380 05390 ENOC (\1) !>8 05400 IFEQ CLR XREG1$ 05410 CLR XREG2$ 05420 05430 ENDC 434 05440 05450 05460 05470 05480 05490 05500 05510 05520 05530 05540 05550 05560 05570 05580 05590 05600 05610 05620 05630 05640 05650 05660 05670 05680 05690 05700 05710 05720 05730 05740 05750 05760 05770 05780 05790 05800 05810 05820 05830 05840 05850 05860 05870 05880 05890 05900 05910 05920 05930 05940 05950 IFNE (\1) '>8 LOA #(\1)'>8 STA XREG1$ STA XREG2$ ENOC LOA TEMPA$ TST XREG1$ MEXIT ENOC ENOC I XREG in high memory? IFNE XREG1$' $FFO ! #0 value? IFEQ \1 STA TEMI?A$ CLRA STA XREG1$+1 STA XREG2$+1 STA XREG1$ STA XREG2$ CLR TESTA$ LOA TEMI?A$ TST TESTA$ MEXIT ENOC ! not #0 value? IFNE \1 STA TEMI?A$ IFEQ (\1)' .$FF CLRA ENDC (\1) , . $FF IFNE # (\1) , . $FF LOA ENOC XREG1$+1 STA STA XREG2$+1 IFEQ (\1) '>8 CLRA ENOC IFNE (\1) '>8 LOA #(\1)'>8 ENOC STA XREG1$ STA XREG2$ TESTA$ STA LOA TEMI?A$ TST TESTA$ MEXIT ENOC ENOC ENOC ENOC FAIL Macro syntax error detected! ENDM 435 05960 05970 05980 05990 06000 06010 06020 06030 06040 06050 06060 06070 06080 06090 06100 06110 06120 06130 06140 06150 06160 06170 06180 06190 06200 06210 06220 06230 06240 06250 06260 06270 06280 06290 06300 06310 06320 06330 06340 06350 06360 06370 06380 06390 06400 06410 06420 06430 06440 06450 06460 06470 06480 06490 06500 06510 06520 06530 06540 06550 06560 06570 06580 06590 06600 ****************************************************** ***************************~**** * * STXR STXR store XREG
* * Examples: 1. "STXa ~ START" stores the XREG into locations 'START' and 'START'+l. * * * * * * * * Register Usage: CC = reflects MS half (=A). All other registers preserved. Notes: 1. Byte access order is LS, then MS (reversed from 68HCl1). STXR MACR STA TEMPA$ LOA XREGl$+l STA (\0)+1 LOA XREGl$ STA (\0) IFEQ XREGl$! . $FFOO LDA TEMPA$ TST XREGl$ ENDC IFNE XREG1$! . $FFOO STA TESTA$ LDA TEMPA$ TST TESTA$ ENDC ENDM *************************************************************************** •• ********* * INCXR = increment XREG * INCXR I II, ) 8 STA XREGl$ XREG2$ STA ORA XREG1$+1 STA TESTA$ LOA TENPAS TST TESTA$ MEXIT ENDC ENDC FAIL Macro syntax error detected! ENDM 437 07150 *****************.************************************ *****~.**************~********** 07160 .. DECXR,. deer_nt XREG 07170" OECXR nj/, I 8 STA XREGl$ STA XREG2$ ORA XREG1$+1 STA TESTA$ LDA TENPA$ TST TESTA$ MEXIT ENOC ENDC FAIL ENDM Macro syntax error detected! ************************************************************************************** * CPXR = compare XREG * CPXR [1/, )
* * * Examples: 1. "CPXR 1/, BLOCKSZ" * * * 2. "CPXR START" compares the value of symbol 'BLOCKSZ' with the XREG. compares the contents of location 'START' and 'START'+l with the XREG. * * Reqister Usaqe: * * CC = reflects XREG comparison (Z-bit only) . All other registers preserved. * CPXR MACR IFEQ NAaG-l STA TENPA$ BSET O,TESTA$ LDA XREG1$+1 CMP (\0)+1 BNE \.0 LOA XREGl$ CMP (\0) BNE \.0 CLR TESTA$ \.0 LOA TENPA$ TST TESTA$ MEXIT ENDC Preset for .NE. condition! Branch if LS half is .NE. Branch if MS half is .NE. Set for .EQ. condition! Set proper Z-bit (.EQ. or .NE.)! 439 08200 08210 08220 08230 08240 08250 08260 08270 08280 08290 08300 08310 08320 08330 08340 08350 08360 08370 08380 08390 08400 08410 08420 08430 08440 08450 08460 08470 08480 08490 08500 08510 08520 08530 08540 08550 08560 08570 08580 08590 08600 08610 08620 08630 IFEQ NAJlG-2 IFC '\0' , 'I' IFEQ \1 IFEQ XREGl$! . $FFOO TST XREGl$+l BNE \.0 XREGl$ TST \.0 EQU * MEXIT ENDC IFNE XREG1$! . $FFOO STA TEMPA$ BSET O,TESTA$ LOA XREGl$+l BNE \.0 LDA XREGl$ BNE \.0 CLR TESTA$ \.0 LDA TEMPA$ TST TESTA$ MEXIT ENDC ENOC STA TEMPA$ O,TESTA$ BSET LOA XREGl$+l IFNE (\1) ! . $FF CMP #(\1)! .$FF ENDC BNE \.0 LOA XREGl$ IFNE (\1) !>8 CMP #(\1) !>8 ENDC BNE \.0 CLR TESTA$ \.0 LOA TEMPA$ TST TESTA$ MEXIT ENOC ENOC FAIL Macro syntax ENOM Branch if LS half is .NE. Preset for .NE. condition' Branch if MS half is .NE. Branch if MS half is .NE. Set for .EQ. condition! Set proper Z-bit (.EQ. or .NE.)! Preset for .NE. condition! Branch if LS half is .NE. Branch if MS half is .NE. Set for .EQ. condition! Set proper Z-bit (.EQ. or .NE.)! error detected! 440 08640 *.*.*.*.* •••• ************************************************************************* 08650 • LDYR = load YREG 08660· LDYR [#,J
08670 • 08680 • Examples: 08690. 1. "LDYR #, START" puts the value of symbol 'START' into the YREG 08700 • 2. "LDYR START" puts the contents of location 'START' and 08710 • 'START'+l into the YREG. 08720 • 08730 • 08740 • Register Usage: 08750. CC = reflects MS half. 08760· All other registers preserved. 08770 08780 LDYR MACR NARG-1 08790 IFEQ 08800 STA TEMPA$ LDA (\0) 08810 08820 STA YREGl$ YREG2$ STA 08830 LDA (\0)+1 08840 STA YREG1$+1 08850 YREG2$+1 08860 STA YREGl$!.$FFOO 08870 IFEQ LDA TEMPA$ 08880 TST YREG1$ 08890 ENDC 08900 IFNE YREGl$!.$FFOO 08910 08920 STA TESTA$ 08930 LDA TEMPA$ TST TESTA$ 08940 08950 ENDC 08960 MEXIT 08970 ENDC IFEQ NARG-2 08980 IFC '\0', '#' 08990 ! YREG in low memory? IFEQ YREG1$! .$FFOO 09000 #0 value? IFEQ \1 09010 CLR YREG1$+1 09020 CLR YREG2$+1 09030 CLR YREG1$ 09040 CLR YREG2$ 09050 MEXIT 09060 09010 ENDC not #0 value? IFNE \1 09080 STA TEMPA$ 09090 IFEQ (\1) ! . $FF 09100 CLR YREGl$+1 09110 CLR llREG2$+1 09120 09130 ENDC (\l)!.$FF IFNE 09140 LDA • (I)! .$FF 09150 STA YREGl$+l 09160 STA YREG2$+1 09170 ENDC 09180 IFEQ (\1) !>8 0!H90 CLR YREGl$ 09200 CLR 09210 YREG2$ ENDC 09220 IFNE (\1) !>8 09230 09240 LDA 11(\1) !>8 STA YREG1$ 09250 STA YREG2$ 09260 09270 ENDC • 441 -----~------- 09280 09290 09300 09310 09320 09330 09340 09350 09360 09370 09380 09390 09400 09410 09420 09430 09440 09450 09460 09470 09480 09490 09500 09510 09520 09530 09540 09550 09560 09570 09580 09590 09600 09610 09620 09630 09640 09650 09660 09670 09680 09690 09700 09710 09720 09730 09740 09750 09760 09770 09780 09790 09800 09810 09820 09830 09840 09850 09860 09870 09880 09890 09900 09910 09920 LDA TST MEXIT TEMPA$ YREG1$ ENDC ENDC IFNE YREG1$' .$FFOO , YREG in high memory? IFEQ \1 1#0 value? STA TEMPA$ CLRA STA YREG1$+1 STA YREG2$+1 STA YREGl$ YREG2$ STA CLR TESTA$ LDA TEMPA$ TST TESTA$ MEXIT ENDC IFNE \1 not #0 value? STA TEMPA$ (\1) , . $FF IFEQ CLRA ENDC (\1) , . $FF IFNE # (\1) , . $FF LDA ENDC STA YREGl$+l STA YREG2$+1 IFEQ (\1) '>8 CLRA ENDC IFNE (\1) '>8 LDA #(\1) !>8 ENDC STA YREGl$ STA YREG2$ STA TESTA$ LDA TEMPA$ TST TESTA$ MEXIT ENDC ENDC ENDC ENDC FAIL Macro syntax error detected! ENDM ***********************************************.******.******************************* STYR = store YREG STYR
Examples: I . "STYR START" stores the YREG into locations 'START' and 'START'+l. Register Usage: CC = reflects MS half. All other registers preserved. STYR MACR STA LDA STA LDA STA TEMPA$ YREGl$ (\0) YREGl$+l (\0) +1 442 09930 09940 09950 09960 09970 09980 09990 10000 10010 10020 10030 10040 10050 10060 10070 10080 10090 1.0100 10110 10120 10130 10140 10150 10160 10170 . 10180 10190 10200 10210 10220 10230 10240 10250 10260 10270 10280 10290 10300 10310 10320 10330 10340 10350 10360 10370 10380 10390 10400 10410 10420 10430 10440 10450 10460 10470 10480 10490 10500 10510 10520 10530 IRQ LDA TST YREG1$! .$FFOO TENPA$ YREG1$ STA LOA TST YREGl$! . $FFOO TESTA$ TENPA$ TESTA$ ENDC IFNE ENDC ENDM ********************************************************* •• *************************** * INCYR = increment YREG * INCYR [ [/I, I I * * Examples: * * 1. "INCYR" 2. "INCYR /I,START" * 3. "INCYR START" * * adds one (1) to the YREG. adds the value of symbol 'START' to the YREG. adds the contents of location 'START' and 'START'+l to the YREG. adds one (1) to the YREG (comment present'). * 4."INCYR! comment" * * Register Usage: * CC = reflects value incremented (Z-bit only) . * All other registers preserved. * * * * * * * Notes: 1. Explicit comment character (') MUST be used when comment field is present' 2. Assumes YREGl$ YREG2$. 3. When parameters are present, this macro becomes "ADD to YREG". = INCYR MACR IFEQ NARG IFEQ YREG1$! . $FFOO INC YREG1$+1 INC YREG2$+1 BNE \.0 INC YREG1$ INC YREG2$ \.0 EQU * MEXIT ENDC IFNE YREG1$! .$FFOO STA TENPA$ LOA YREG1$+1 ADD 111 STA YREGl$+l STA YREG2$+1 LDA YREGl$ ADC /10 STA YREGl$ STA YREG2$ ORA YREG1$+1 STA TESTA$ LOA TENPA$ TST TESTA$ MEXIT ENDC ENDC 443 10540 lFEQ NARG-1 STA 10550 TEMPA$ 10560 LOA YREGl$+1 10570 (\0)+1 ADD 10580 STA YREGl$+1 10590 YREG2$+1 STA 10600 LOA YREGl$ 10610 ADC \0 10620 STA YREG1$ STA 10630 YREG2$ ORA 10640 YREGl$+1 10650 STA TESTA$ LOA 10660 TEMPA$ 10670 TST TESTA$ 10680 MEXIT 10690 ENDC 10700 IFEQ NARG-2 IFC 10710 '\0' , 'I' 10720 STA TEMPA$ 10730 LOA YREGl$+1 10740 ADD #(\1) !.$FF 10750 STA YREG1$+1 10760 STA YREG2$+1 10770 LOA YREGl$ 10780 ADC #(\1) !>8 10790 STA YREGl$ 10800 STA YREG2$ 10810 ORA XREG1$+1 10820 STA TESTA$ 10830 LOA TEMPA$ 10840 TST TESTA$ 10850 MEXIT 10860 ENDC 10870 ENDC 10880 FAIL Macro syntax error detected! 10890 ENDM 10900 10910 ************************************************************************************** 10920 * OECYR = decrement YREG 10930 * OECYR [[#, ) 8 STA YREG1$ STA YREG2$ ORA YREG1$+1 STA TESTA$ LOA TENPA$ TST TESTA$ MEXIT ENOC ENOC FAIL Macro syntax error detected! ENDM 445 11670 ************************************************************************************** 11680 * CPYR = compare YREG 11690 * CPYR [II, I
11700 • 11710 • Examples: 11720· 1. "CPYR II,BLOCKSZ" compares the value of symbol 'BLOCKSZ' 11730 * with the YREG. 2. "CPYR START" compares the contents of location 11740 • 'START' and 'START'+l with the YREG. 11750 • 11760 • Register Usage: 11770 * 11780 * CC reflects YREG comparison (Z-bit only) . All other registers preserved. 11790 * 11800 11810 CPYR MACR 11820 IFEO NARG-l 11830 STA TENPA$ 11840 BSET O,TESTA$ Preset for .NE. eondition~ 11850 LDA YREG1$+l 11860 CNP (\0) +1 11870 BNE \.0 Branch if LS half is .NE. 11880 LDA YREG1$ 11890 CNP (\0) 11900 BNE \.0 Branch if MS half is .NE. 11910 CLR TESTA$ Set for .EO. condition! 11920 \.0 LDA TENPA$ 11930 TST TESTA$ Set proper Z-bit (.EO. or .NE.) ! 11940 MEXIT ENDC 11950 IFEO NARG-2 11960 11970 IFC '\0', '/I' 11980 IFEO \1 11990 IFEO YREG1$ , . $FFOO 12000 TST YREG1$+1 12010 BNE \ .0 Branch if LS half is . NE. 12020 TST YREG1$ 12030 \.0 EOU * 12040 MEXIT 12050 ENDC 12060 IFNE YREG1$' .$FFOO 12070 STA TENPA$ 12080 BSET 0, TESTA$ Preset for .NE. condition! 12090 LDA YREGl$+l 12100 BNE \.0 Branch if MS half is .NE. 12110 LDA YREGl$ 12120 BNE \.0 Branch if MS half is .NE. 12130 CLR TESTA$ Set for .EO. condition! 12140 \.0 LDA TENPA$ TST TESTA$. 12150 Set proper Z-bit (.EO. or .NE.)! 12160 MEXIT 12170 ENDC ENDC 12180 12190 STA TENPA$ BSET O,TESTA$ Preset for .NE. condition! 12200 12210 LDA YREG1$+1 12220 IFNE (\1) ! . $FF 12230 CNP /I (\1) ! . $FF 12240 ENDC \.0 Branch if LS half is .NE. 12250 BNE 12260 LDA YREG1$ 12270 IFNE (\1) '>8 12280 CMP /1(\1) !>8 12290 ENDC = 446 Branch if MS half is .NE. 12300 BNE \.0 Set for .EQ. condition~ 12310 CLR TESTA$ 12320 \.0 LDA TEMPA$ TESTA$ Set proper Z-bit (.EQ. or .NE.) , 12330 TST MEXIT 12340 12350 ENDC 12360 ENDC Macro syntax error detected! 12370 FAIL 12380 ENDM 12390 12400 ****.*****************************************************.*************.************* 12410 * DEC.B = decrement byte DEC.B [[#, ] , ]
12420 * 12430 * 12440 * where: value to decrement the contents of the
12450 * location by; immediate ("#," present) or absolute 12460 * addressing ("#," not present). If only
is 12470 * specified, a default immediate value of one is used. 12480 * 12490 * 12500 * Examples: 12510 * 1. "DEC.B·START" subtracts one from the contents of 12520 location 'START'. 12530 2. "DEC.B#,5,START" subtracts five from the contents of location 'START'. 12540 * 3. "DEC. B CNT, START" subtracts the contents of location 'CNT' 12550 * 12560 from the contents of location 'START'. 12570 * 12580 * Register Usage: 12590 CC = reflects value decremented (N and Z-bits) . 12600 All other registers preserved. 12610 * 12620 * Notes: 1.
may be direct or extended! 12630 2. This macro essentially performs a "SUB n" function. 12640 * 12650 * 12660 DEC.B MACR 12670 IFEQ NARG-1 12680 IFEQ (\O)'.$FFOO 12690 DEC \0 12700 MEXIT 12710 ENDC 12720 STA TEMPA$ LDA 12730 \0 12740 SUB #1 12750 STA \0 STA TESTA$ 12760 LDA TEMPA$ 12770 TESTA$ 12780 TST 12790 MEXIT 12800 ENDC NARG-2 IFEQ 12810 12820 STA TEMPA$ 12830 LDA \1 '12840 SUB \0 12850 STA \1 12860 IFEQ (\1) ! . $FFOO 12870 TEMPA$ LDA TST \1 12880 12890 MEXIT 12900 ENDC 447 12910 IFIfE (\1) ! . $FFOO 12920 STA TESTA$ 12930 LDA TEMPA$ 12940 TST TESTA$ MEXIT 12950 12960 ENDC 12970 ENOC NARG-3 12980 IFEQ 12990 '\0' , 'II' IFC 13000 STA TEMPA$ 13010 LDA \2 13020 SUB 11\1 13030 STA \2 13040 IFEQ (\2) ! . $FFOO 13050 LOA TEMPA$ 13060 TST \2 13070 MEXIT 13080 ENDC IFNE (\2) ! . $FFOO 13090 STA TESTA$ 13100 13110 LDA TEMPA$ 13120 TST TESTA$ 13130 MEXIT 13140 ENDC 13150 ENDC 13160 ENDC 13170 FAIL Macro syntax error detected! ENDM 13180 13190 13200 ***********************************************~****** ******************************** 13210 * DEC.W decrement word 13220 * DEC.W [[II,),}
13230 * 13240 * where: 13250 * value to decrement the contents of the
and
+1 locations by: immediate (",," present) or 13260 * 13270 * absolute addressing ("II," not present). If only
is specified, a default immediate. value of 13280 * 13290 one is used. 13300 * 13310 * Examples: 13320 1 . "DEC. W START" subtracts one from the contents of loca13330 * tions 'START' and 'START'+l. 2. "DEC. W CNT, START" subtracts the contents of locations 'CNT' 13340 * and 'CNT'+l from the contents of locations 13350 * 'START' and 'START'+l. 13360 * 13370 3. "DEC.wlI,5,START" subtracts five from the contents of locations 'START' and 'START'+l. 13380 * 13390 * 13400 * Register Usage: 13410 * CC reflects value incremented (Z-bit only) . 13420 * All other registers preserved. 13430 * 13440 .. Notes: 1.
may be direct or extended! 13450 * 2. This macro essentially performs a "SUB n" function. 13460 * 13470 * = = 448 13480 OEC.W MACR 13490 IFEQ NARG-1 13500 STA TEMPA$ 13510 LOA (\0) +1 13520 SUB #1 13530 STA (\0) +1 13540 LOA \0 13550 SBC #0 13560 STA \0 13570 ORA (\0) +1 13580 STA TESTA$ 13590 LOA TEMPA$ 13600 TST TESTA$ MEXIT 13610 13620 ENDC NARG-2 13630 IFEQ STA TEMPA$ 13640 (\1)+1 LOA 13650 13660 SUB (\0)+1 13670 (\1)+1 STA \1 13680 LOA SBC \0 13690 13700 STA \1 13710 ORA (\1)+1 13720 STA TESTA$ 13730 TEMPA$ LOA 13740 TST TESTA$ 13750 MEXIT 13760 ENDC 13770 IFEQ NARG-3 13780 IFC '\0' , 'I' 13790 STA TEMPA$ LOA (\2)+1 13800 13810 #(\1)! .$FF SUB 13820 STA (\2)+1 13830 LOA \2 13840 SBC #(\1) !>8 13850 STA \2 13860 ORA (\2) +1 STA TESTA$ 13870 13880 LOA TEMPA$ 13890 TST TESTA$ 13900 MEXIT 13910 ENDC 13920 ENDC 13930 FAIL Macro syntax error detected! 13940 ENOM 13950 449 13960 ************************************************************************************** 13970 * INC.B increment byte 13980" INC.B lIl, ] , j
13990 " 14000 "where: 14010" value to decrement the contents of the
location by; immediate ("I," present) or absolute 14020 * addressing ("I," not present). If only
is 14030 * specified, a default immediate value of one is used. 14040 * 14050 " 14060 "Examples: 14070 * 1. "INC.B START" adds one to the contenta of location 'START' . 14080 * 2. "INC.B #,5,START" adds five to the contents of location 14090 " 'START' . 14100 " 3. "INC.B CNT,START" adds the contents of location 'CNT' to 14110 " the contents of location 'START'. 14120 * 14130 * 14140 * Register Usage: 14150 * CC= reflects value incremented (N and Z-bits) . 14160 * All other registers preserved. 14170 * 14180 * Notes: 14190 * 1.
may be direct or extended! 14200 * 2. This macro essentially performs an "ADD n" function. 14210 * 14220 INC.B MACR 14230 IFEQ NARG-1 14240 IFEQ (\0) ! . $FFOO INC 14250 \0 14260 MEXIT 14270 ENDC 14280 STA TENPA$ 14290 LOA \0 14300 ADO #1 14310 STA \0 14320 STA TESTA$ 14330 LOA TENPA$ 14340 TST TESTA$ 14350 MEXIT 14360 ENDC 14310 NARG-2 IFEQ STA TENPA$ 14380 14390 LOA \1 14400 ADO \0 14410 STA \1 14420 IFEQ (\1) ! . $FFOO 14430 LOA TENPA$ 14440 TST \1 MEXIT 14450 14460 ENDC 14470 IFNE (\1)! .$FFOO 14480 STA TESTA$ LOA TENPA$ 14490 TESTA$ 14500 TST 14510 MEXIT ENDC 14520 14530 ENDC = 450 14540 14550 14560 14570 14580 14590 14600 14610 14620 14630 14640 14650 14660 14670 14680 14690 14700 14710 14720 14730 14740 14750 14760 14770 14780 14790 14800 14810 14820 14830 14840 14850 14860 14870 14880 14890 14900 14910 14920 14930 14940 14950 14960 14970 14980 14990 15000 15010 15020 15030 15040 15050 15060 15070 15080 15090 15100 15110 IFEQ IFC NARG-3 '\0' , '#' STA TENPA$ \2 LOA ADD #l \2 STA (\2) , . $FFOO IFEQ TENPA$ LDA \2 TST MEXIT ENDC IFNE (\2) ! . $FFOO TESTA$ STA LOA TENPA$ TESTA$ TST MEXIT ENOC ENOC ENDC FAIL Macro syntax error detected' ENDM ************************************************************************************** * INC.W = increment word * INC.W [[#,], ]
* * * * * * * * * * where: value to increment the contents o~ the
and
+1 locations by; immediate ("#," present) or absolute addressing ("#," not present). If only
is specified, a default immediate value of one is used. Examples: 1. ·'INC.W START" 2. "INC.W CNT,START" * * * * * * * * * * 3. "INC.W #,5,START" adds one to the contents of locations 'START' and 'START'+1. adds the value of 'CNT' to the contents of locations 'START' and 'START'+L adds five to the contents of locations 'START' and 'START'+1. Register Usage: CC = reflects value incremented (Z-bit only) . All other registe.rs preserved. Notes: 1.
may be direct or extended' 2. This macro essentially performs an "ADD n" function. * INC.W MACR IFEQ NARG-1 (\0) ! . $FFOO IFEQ INC (\0)+1 BNE \.0 INC \0 EQU \.0 * MEXIT ENDC 451 15120 15130 15140 15150 15160 15170 15180 15190 15200 15210 15220 15230 15240 15250 15260 15270 15280 15290 15300 15310 15320 15330 15340 15350 15360 15370 15380 15390 15400 15410 1542{) 15430 15440 15450 15460 15470 15480 15490 15500 15510 15520 15530 15540 15550 15560 15570 15580 15590 IFNE (\0) ! . $FFOO TENPA$ (\0)+1 #1 (\0)+1 \0 #0 \0 ORA (\0)+1 STA TESTA$ LOA TENPA$ TST TESTA$ MEXIT STA LOA ADO STA LOA ADC STA ENOC ENDC IFEQ ENOC IFEQ IFC NARG-2 STA TENPA$ LOA (\1)+1 (\0)+1 ADO STA (\1)+1 LOA \1 ADC \0 STA \1 ORA (\1) +1 STA TESTA$ LOA TENPA$ TESTA$ TST MEXIT NARG-3 '\0', 'I' STA TENPA$ LOA (\2)+1 ADO # (\1) ! . $E'F STA (\2)+1 LOA \2 ADC #(\1)!>8 STA \2 ORA (\2)+1 STA TESTA$ LOA TENPA$ TST TESTA$ MEXIT ENOC ENOC FAIL ENDM Macro syntax error detected~ 452 15600 ***************************************************.*.******************************** move byte 15610 * NOV.B NOV:B [I,),
15620 15630 * 15640 * where: byte value to move to the
location, using 15650 * 15660 * immediate ("I," present) or absolute addressing ("lI," 15670 * not present) . 15680 * 15690 * Examples: 15700 1. "NOV.B CNT, TNP" puts the contents of location 'CNT' into location 'TMP'. 15710 * 2. "MOV. B I, 5, START" puts 5 into location 'START'. 15720 * 15730 * 15740 * Register Usage: 15750 CC reflects value moved. All other registers preserved. 15760 15770 * 15780 NOV.B MACR 15790 IFEQ NARG-2 15800 STA TENPA$ LDA \0 15810 15820 STA \1 15830 IFEQ (\1) ! . $FFOO TENPA$ 15840 LDA 15850 TST \1 MEXIT 15860 15870 ENDC 15880 IFNE (\1) ! . $FFOO (\0) I . $FFOO 15890 IFEQ 15900 TENPA$ LDA 15910 TST \0 MEXIT 15920 15930 ENDC 15940 IFNE (\0) ! . $FFOO 15950 STA TESTA$ 15960 LDA TENPA$ 15970 TST TESTA$ 15980 MEXIT 15990 ENDC 16000 ENDC 1.6010 ENDC 16020 IFEQ NARG-3 16030 IFC '\0' , 'lI' 16040 IFEQ (\2) ! . $FFOO 16050 IFEQ \1 16060 CLR \2 16070 MEXIT 16080 ENDC 16090 ENDC 16100 STA TENPA$ 16110 IFEQ \1 16120 CLRA 16130 ENDC 16140 IFNE \1 16150 LDA #l 16160 ENDC 16110 STA \2 16180 IFEQ (\2) ! . $FFOO 16190 LDA TENPA$ 16200 TST \2 16210 MEXIT 16220 ENDC = = 453 16230 IF1IE (\2) '.$FFOO 16240 STA TESTA$ 16250 LOA TENPA$ 16260 TST TESTA$ 16270 MEXIT 16280 ENDC 16290 ENDC 16300 ENDC 16310 FAIL Macro syntax error detected' 16320 ENDM 16330 16340 ******************************************************************************** 16350 * NOV.1f = move word 16360 * NOV.1f [I, ] ,
16370 * 16380 * where: 16390 * word (16-bit) value to move to the
and 16400 *
+l locations, using immediate ("I," present) 16410 * or absolute addressing ("I," not present) . 16420 * 16430 * Examples: 16440 * 1. "HOV.1f 1,5, START" puts $0005 into location 'START' and 'START'+l·. 16450 * 2. "NOV.1f I,CNT,TMP" puts the value of symbol 'CNT' into 16460 * locationa 'T.MP' and 'TMP'+l. 16470 * 3. "HOV.1f CNT,TMP n copies the contents of location 'CNT' 16480 * and 'CNT'+l into locations 'TMP' and 16490 * . 'TMP'+1. 16500 * 16510 * 16520 * Register Usage: 16530 * CC reflects MS half of value moved. 16540 * All other registers preserved. 16550 * 16560 HOV.1f MACR IFEQ 16570 NARG-2 16580 STA TENPA$ 16590 LOA (\0) +:l 16600 STA (\1)+1 16610 LOA \0 16620 STA \1 !FEQ 16630 (\1)' .$FFOO 16640 LOA TENPA$ 16650 TST \1 16660 MEXIT 16670 ENDC (\1) , . $FFOO 16680 IFNE (\0) , . $FFOO IFEQ 16690 16700 LOA TENPA$ 16710 TST \0 16720 MEXIT 16730 ENDC 16140 IF1IE (\0) ! . $FFOO 16750 STA TESTA$ 16760 LOA TENPA$ 16770 TST TESTA$ 16780 MEXIT 16790 ENDC 16800 ENDC 16810 ENDC = = 454 16820 16830 16840 16850 16860 16870 16880 16890 16900 16910 16920 1u930 16940 16950 16960 16970 16980 16990 17000 17010 17020 17030 17040 17050 17060 17070 17080 17090 17100 17110 17120 17130 17140 17150 171UO 17170 17180 17190 17200 17210 17220 17230 NARG-3 IFEO '\0- _ 'IIFC «\2) +1) ! . $.1'1'00 IFEO IFEO \1 \2 CLR \2+1 CLR MEXIT ENDC ENDC STA IFEQ TENPA$ (\1)! .$001'1' CLRA ENDC IFNE LOA (\1)1.$001'1' • (\1) ! . $001'1' ENDC STA (\2)+1 (\1) !>8 IFEO IFNE (\1) ! . $001'1' CLRA ENOC ENDC IFNE (\1) !>8 LDA I(\1)!>8 ENOC STA \2 (\2) ! . $1'1'00 IFEO LDA TENPA$ TST \2 MEXIT ENOC IFNE STA LllA TST (\2) !.$FFOO TESTA$ TENPA$ TESTA$ MEXlor ENDC ENDC ENDC FAIL Macro syntax error detected! ENDM 455 17240 ******************~*********************************** **************** 17250 * MOVE = 1I\Ove block of II\eIIIOry 17260 * MOVE [.], , {'], , [I], 17270 * 17280 * where: 17290 * is the address of the source memory block. 17300 * is the address of the destination block. 17310 * is the length of the block to move, in bytes. Maximul1l of 65,536 bytes can be moved. 17320 * 17330 * is optional character to denote immediate II 17340 * addressinq for the next parameter 17350 * Examples: 1. "MOVE ., ROM, ., RAM, II, CNT moves the block of memory startinq at 17360 * 17370 * location 'ROM' for 'CRT' bytes, to 17380 * location 'RAM'. 17390 * 2. "MOVE II,ABC,II,xrZ"CNT moves the block of memory startinq at 17400 * location 'ABC' for the number of bytes in locations 'CRT' and 'CRT'+l, to 17410 * 17420 * location 'xrz'. 17430 * 17440 * Reqister Usaqe: 17450 * CC = unknown. 17460 * All other reqisters preserved. 17470 * 17480 * Subr. used: 17490 * LDAXREG, STAXREG 17500 * 17510 • Macros used: 17520 * None, because this macro was written to be .s efficient as 17530 * possible. 17540 * 17550 * Notes: 17560 1. If all immediate addressinq operands (Ill and the move count is <= 256, then a special 'short form' is qenerated which DOES NOT 17570 * 17580 * contain any subroutine calls! 17590 * 2. Dependinq on the exact parameters passed, not all reqisters, 17600 * subroutines and/or macros may be used. 17610 * 3.This macro takes advantaqe of the fact that there are in fact 17620 * two XREGs, one for LOAD (XREG1$) and one for STORE (XREG2$). 4. The INClCR macro cannot be used here, because it ass_s t·hat 17630 * 17640 * XREGl$ = XREG2$. 17650 * ------------------------------------------------------------------------17660 MOVE MACR 17S70 IFNE NARG-6 17680 FAIL ** 'move' macro requires six arguments! 17690 ENDC 17700 If all immediate operands (I) and move IFC '\4', 'I' 17710 IFC count <=256, use short form! '.''I' 17720 IFe '\2', '\0', 17730 IFLE 5-256 NO subr. calls! 17740 STA TEMPA$ STX 17750 TEMPX$ 17760 LDX 1(\5) 17770 \.0 LDA (\l)-l,x 17780 STA (\3)-1,x 17790 DEX 17800 BNE \.0 17810 LDA TEMPA$ 17820 LDX TEMPX$ 17830 MEXIT 17840 ENDC 17850 ENDC 17860 ENDC 17870 ENDC 17880 456 STA TEMPA$ 17890 TEMPX$ 17900 STX 17910 LOA XREG1$ STA 17920 TEMPXR$ XREG1$+l LOA 17930 17940 STA TEMPXR$+l '\0' , '1/' 17950 IFC 17960 LOA 1/(\l)!.$FF 17970 STA XREG1$+l 17980 LOA 1/ (\1) '>8 STA XREG1$ 17990 ENDC 18000 18010 IFNC '\0' • '1/ LOA (\1) +1 18020 18030 STA XREG1$+1 LOA (\1) 18040 18050 STA XREG1$ ENDC 18060 IFC '\2' , '1/' 18070 1/(\3) I.$FF 18080 LOA 18090 STA XREG2$+l LOA 18100 1/(\3) '>8 STA XREG2$ 18110 ENDC 18120 IFNC '2' , '1/' 18130 LOA (\3)+1 18140 XREG2$+1 STA 18150 18160 LOA (\3) STA XREG2$ 18170 18180 ENDC 18190 18200 IFC '\4' , '1/' 18210 IFLE \5-256 LOX 1/(\5) 18220 18230 \.0 JSR LOAXREG JSR STAXREG 18240 XREG1$ I . $FFOO IFEQ 18250 INC XREG1$+l 18260 18270 BNE \.1 INC XREG1$ 18280 18290 .\.1 INC XREG2$+l BNE \.2 18300 INC XREG2$ 18310 18320 \.2 EQU * ENDC 18330 XREG1$ ! . $FFOO 18340 IFNE XREG1$+1 18350 LOA 18360 ADD III STA XREG1$+l 18370 XREG1$ 18380 LOA 18390 ADC I/O STA XREG1$ 18400 LOA XREG2$+l 18410 18420 ADD III 18430 STA XREG2$+l 18440 LOA XREG2$ 18450 ADC I/O XREG2$ 18460 STA 18470 ENDC 18480 OEX 18490 BNE \.0 18500 LOA TEMPXR$ 18510 STA XREGl$ 18520 STA XREG2$ TEMPXR$+l 18530 LOA I immediate type 'from' address? I Set XREG1$ = 'from' address I not immediate type 'from' address? ! Set XREG1$ = 'from' address I immediate type 'to' address? I Set XREG2$ = 'to' address ! not immediate type 'to' address? ! Set XREG2$ = 'to' address ! immediate type length? I yes: 8-bit size= use X reg. 457 18540 18550 18560 18570 18580 18590 18600 18610 18620 18630 18640 18650 18660 18670 18680 18690 18700 18710 18720 18730 18740 18750 18760 18770 18780 18790 18800 18810 18820 18830 18840 18850 18860 18870 18880 18890 18900 18910 18920 18930 18940 18950 18960 18970 18980 18990 19000 19010 19020 19030 19040 19050 19060 19070 19080 19090 19100 STA STA LDA LDX MEXIT • XREG1$+l XREG2$+l TEMPA$ TEMPX$ ENDC IFGT \5-256 LDA 11(\5) I . $OOFF STA LENGTH$+l LDA /I (\5) !>8 STA LENGTH$ \.0 JSR LDAXREG JSR STAXREG IFEQ XREG1$!.$FFOO INC XREG1$+l BNE \.1 INC XREG1$ \.1 INC XREG2$+l BNE \.2 INC XREG2$ \.2 EQU ENDC IFNE XREG1$! .$FFOO XREG~$+l LDA ADD #l STA XREG1$+l LOA XREG1$ ADC #0 STA XREG1$ LOA XREG2$+l ADO #l STA XREG2$+l LOA XREG2$ ADC 110 STA XREG2$ ENDC LOA LENGTH$+l SUB 111 STA LENGTH$+l LOA LENGTH $ SBC 110 STA LENGTH$ ORA LENGTH$+l BNE \.0 LOA TEMPXR$ STA XREG1$ STA XREG2$ LOA TEMPXR$+l XREG1$+1 STA STA XREG2$+1 LOA TEMPA$ LOX TEMPX$ MEXIT ENDC ENOC no: 16-bit size= use 'length' 458 19110 19120 19130 19140 19150 19160 19170 19180 19190 19200 19210 19220 19230 19240 19250 19260 19270 19280 19290 19300 19310 19320 19330 19340 19350 19360 19370 19380 19390 19400 19410 19420 19430 19440 19450 19460 19470 19480 19490 19500 19510 19520 19530 19540 19550 19560 19570 19580 19590 19600 19610 19620 , nonimmediate type length '\4' , '/I' LOA (\5)! .$OOFF STA LENGTH$+1 LOA (\5) '>8 STA LENGTH$ \.0 JSR LDAXREG JSR STAXREG IFEQ XREGl$' . $FFOO XREGl$+1 INC \.1 BNE INC XREGl$ XREG2$+l \.1 INC \.2 BNE XREG2$ INC \.2 EQU * ENDC IFNE XREGl$! . $FFOO LDA XREGl$+1 ADD III XREGl$+l STA XREGl$ LOA ADC /10 STA XREGl$ LOA XREG2$+1 ADD III XREG2$+l STA XREG2$ LOA ADC '0 STA XREG2$ ENDC LOA LENGTH$+l SUB #1 LENGTH$+l STA LENGTH$ LOA SBC 110 STA LENGTH$ LENGTH$+1 ORA \.0 BNE TEMPXR$ LOA STA XREGl$ STA XREG2$ LDA TEMPXR$+1 STA XREGl$+1 XREG2$+l STA TEMPA$ LOA TEMPX$ LOX MEXIT ENDC Macro syntax error detected! FAIL ENDM IFNC 459 19630 19640 19650 19660 19670 19680 19690 19700 19710 19720 19730 19740 19750 19760 19170 19780 19790 19800 19810 19820 19830 19840 19850 19860 19870 19880 19890 19900 19910 19920 19930 19940 19950 19960 19970 19980 19990 20000 20010 20020 20030 20040 20050 20060 20070 20080 20090 20100 20110 20120 20130 20140 20150 20160 20170 20180 2019Q 20200 20210 20220 20230 20240 OPT L RAMSBR$ EQU Start of RAM based subroutines! * *****************************************************************************.******** ** ** The following RAM subroutines MUST BE INITIALIZED from ROM upon ** startup (from 'RAMSBR$' for 'RAMSZ$' number of bytes). If changes "* ** ** are to be made to the RAM subroutines, make them here. Then copy ** the source below to the ROM area and insert a '.' in front of all "* ** the labels (leading '.' will be used to denote ROM). This has ** ** ** already been done for you in the RAMSBR.INI file. Just include ** this file into your ROM data area and add the following line in ** ** ** your RESET routine to initialize the RAM subroutines from the ROM. ** MOVE II, .RAMSBR,II,RAMSBR,II, ** It is more efficient if the RAM subroutines are placed in DIRECT ** ** addressing memory, i.e., $OOOO-$OOFF, but it is not required. ** ************************************************.************************************* "" *-- start of RAM subroutines ----------------------------------------------* ************************************************************************************** " LDAXREG = load A via XREG subr. * * Register Usage: * CC = reflects value loaded. • All other registers preserved. * * NOTE: * 1. Instruction modified code here must he located in RAMr • LDAXREG EQU LDA XREG1$ EQU RTS * O-O+$FFFF *-2 Pseudo XREG 1/1 ***************** •• *** ••• **********.******.*****************************.************* * STAXREG store A via XREG subr. = * * Register Usage: * CC = reflects value stored. * All other registers preser"Jed. * NOTE: * 1. Instruction modified code here must be located in RAM! * STAXREG XREG2$ EQU STA EQU RTS * O-O+$FFFF *-2 Pseudo XREG '2 ************************************************************************************** * LDAYREG = load A via YREG subr. * • Register Usage: * CC = reflects value loaded. * All other registers preserved. • * NOTE: * 1. Instruction modified code here must be located in RAM! * LDAYREG EQU * LOA O-O+$FFFF YREG1$ EQU *-2 Pseudo YREG III RTS 460 20250 20260 20270 20280 20290 20300 20310 20320 20330 20340 20350 20360 20370 20380 20390 20400 20410 20420 20430 20440 20450 20460 20470 20480 20490 20500 20510 ************.************************************************************************* * STAYREG store A via YREG subr. = * * * * Register Osage: CC reflects value stored. All other registers preserved. = * * NOTE: * 1. Instruction modified code here must be located in RAM! * EgO * STA O-O+$FFFI' YREG2$ EgO *-2 Pseudo YREG ,2 RTS *-- end of RAM subroutines ------------------------------------------------STAYREG RAMSZ$ EgO *-RAMSBR$ Size of ram subroutines (in ~ytes) * . ORG LO$MEM * NOTE: TENPA$ and TESTA$ must always be in low memory $0000-001'1'. TENPA$ RMB 1 Temporary storage for A accumulator. TENPX$ 1 Temporary storage for X register. RMB TENPXR$ RMB 2 Temporary storage for XREG register. TESTA$ 1 Temporary operand storage for setting CC bits. RMB LENGTH$ RMB 2 Temporary operand length. ************************************************************************************** 461 listing 2 - RAMSBR,INI File 00010 00020 00030 00040 00050 00060 00070 00080 00090 00100 00110 00120 00130 00140 00150 00160 00170 00180 00190 00200 00210 00220 00230 00240 00250 00260 00270 00280 00290 00300 00310 00320 00330 00340 00350 00360 00370 00380 00390 00400 00410 OO~20 00430 00440 00450 00460 00470 00480 00490 00500 00510 00520 00530 00540 0055"0 00560 00570 00580 00590 *.***********.*****************.*.*.*********************************_.*************** * ramsbr. ini 1.0 * -------------------------------------------------------------------* Module Name: "RAMSBR - RAM Subroutine Initialization * -------------------------------------------------------------------* Description: * * * * This file contains the initialization code for the RAM subroutine area needed to support the MACROS05.MAC file. It MUST be placed in the ROM data area and then copied to RAM for properoperatiQn. Consult the MACROS05.MAC file for more details: * **************************.**** ••• *******************. *****.*.*.**.*~****** •••• ***.*** * * * * * * * * * Notes: 1.Motorola reserves the right to make changes"to this file. Although this file has been carefully reviewed and is believed to be reliable, Motorola does not assume any liability arising out of it"s use. This code Jliay be freely used and/or modified at no"cost or obligation by the user. 2.The latest version of this file is maintained on the Motorola FREEWARE Bulletin Board, 512l891-FREE (512/891-3733). It operat.es continuously (except for maintenance) at 1200-2400 baud, 8 bits, no parity. Sample test files for PASM05 are also included. Download the archive file, MACROS05.ARC, to get all the files. ** •• ********************************************************************************** * REVISION HISTORY (add new changes to top) : * * 05/16/90 P.S. Gilmour * 1. Original entry generated from MACROS05.MAC version 1.0. ****************************.***********************************************-******.** Start of RAM based subroutines! .RAMSBR$ EQU * .*******.************.***********-*****--*******-*-*-*************************.******* ** The followinq RAM subroutines MUST BE INITIALIZED from ROM upon ** startup (from 'RAMSBR$' for 'RAMSZ$' number of bytes). If changes ** ** are to be made to the RAM subroutines, make them in the MACROSOS.MAC ** ** file and then copy the source here (ROM area) and insert a '.' in ** ** front of all the labels (leading '.' will be used to denote ROM). ** *****--*-*******-.**********.*.*****.******** ••• ***.********.** •• ****.***.**--******** *-- start of RAM subroutines -----------------------------------------------* ****.*****-****** •• *.* •• *******.* •• * •• *.********.***.********************************* * LDAXREG load A via XREG subr. = * * Register Usage: CC reflects value loaded. All other registers preserved. * = * * NOTE: * 1: Instruction modified code here must be located in RAM! * .LDAXREG .XREGl$ EQU LOA EQU RTS * O-O+$FFFF *-2 Pseudo XREG #1 462 00600 00610 00620 00630 00640 00650 00660 00670 00680 00690 00700 00710 00720 00730 00740 00750 00760 00770 00780 00790 00800 00810 00820 00830 00840 00850 00860 00870 00880 00890 00900 ************************************************************************************** • STA$X store A via XREG subr. = • • Register Usage: • CC reflects value stored. • All other registers preserved. = • • NOTE: • 1. Instruction modified code here must be located in RAM! • . STA$X EQU STA O-O+$FFFF .XREG2$ EQU *-2 Pseudo XREG '2 RTS • ************************************************************************************** • LOAYREG = load A via YREG subr. * • Register Usage: * CC = reflects value loaded. * All other registers preserved. * * NOTE: * 1. Instruction modified code here must be located in RAM! * . LDAYREG . YREGl$ EQU LOA EQU RTS * O-O+$FFFF *-2 Pseudo YREG ,1 ************************************************************************************** 00910 * STA$Y = store A via YREG subr. 00920 * 00930 • Register Usage: 00940 * CC = reflects value stored. 00950· All other registers preserved. 00960 • 00970 • NOTE: 00980 * 1. Instruction modified code here must be located in RAM! 00990 • 01000 .STA$Y EQU 01010 STA O-O+$FFFF 01020 . YREG2$ EQU ·-2 Pseudo YREG '2 01030 RTS 01040 .-- end of RAM subroutines --------------------------------------------------01050 01060 .RAMSZ$ EQU .-.RAMSBR$ .Size of ram subroutines (in bytes) . 01070 FNE RAMSZ$-.RAMSZ$ 01080 FAIL Size mismatch between RAM/ROM subroutine areas! ENDC 01090 • 463 • 464 AN1057 Selecting the Right Microcontroller Unit INTRODUCTION SELECTION CRITERIA Selecting the proper microcontroller unit (MCU) for your application is one olthe critical decisions which control the success or failure of your project. There are numerous criteria to consider when choosing an MCU and this Application Note will enumerate most of them and presents an outline of the thought process guiding this decision. The reader must attach their own grading scale to the selection criteria presented and then evaluate the total to make the correct decision. The general outline of the main criteria in selecting a microcontroller is listed below, in the order of importance. Each criteria is explained in greater detail later on. 1. Suitability for the application system, i.e., can it be done with a single-chip MCU or at most a few additional chips? A. Does it have the required number of I/O pins/ports, i.e., too few = can't do the job and too many = excessive cost? B. Does it have all the other required peripherals, such as serial I/O, RAM, ROM, AID, D/A, etc.? C. Does it have other peripherals that are not needed? D. Does the CPU core have the correct throughput, i.e., computing power, to handle the system requirements over the life of the system for the chosen implementation language? Too much is wasteful and too little will never work. E. Is the MCU affordable, i.e., does the project budget allocate enough funds to permit using this MCU? A budgeting quotation from the manulacturer is usually required to answer this question. II the MCU is not affordable for the project, all the other questions become irrelevant and you must start looking for another MCU. 2. Availability? A. Is the device available in sufficient quantities? B. Is the device in production today? C. What about the future? 3. Development support available? A. Assemblers. B. Compilers. C. Debugging tools. 1. Evaluation Module (EVM). 2. In-circuit emulators. 3. Logic analyzer pods 4. Debug monitors 5. Source level debug monitors. D. On-line bulletin board service (BBS). 1. Real time executives. 2. Application examples. 3. Bug reports. 4. Utility software, including "free'" assemblers. 5. Sample source code. PURPOSE The main goal is to select the least expensive MCU that minimizes the overall cost of the system while still fulfilling the system specification, i.e., performance, reliability, environmental, etc. The overall cost of the system includes everything, such as Engineering Research and Development (R&D), manufacturing (parts and labor), warranty repairs, updates, field service, upward compatibility, ease of use, etc. SELECTION PROCESS To start the selection process, the designer must first ask the question, "What does the MCU need to do in my system?" The answer to this one simple question dictates the required MCU features for the system and thus is the controlling agent in the selection process. The second step is to conduct a search for MCUs which meet all 01 the system reqUirements. This usually involves searching the literature, primarily data books, data sheets, and technical trade journals, but also includes peer consultations. These days, recent trade journals seem to contain the most up to date information for the newer MCUs. If the fit is good enough, a single-chip MCU solution has been found, otherwise a second search must be conducted to find an MCU which best fits the requirements with a minimum of extra circuitry, including considerations of cost and board space. Obviously, a single-chip solution is preferred for cost as well as reliability reasons. Of course, ilthere is a company policy dictating which MCU manufacturer to use, this will narrow your search considerably. The last step has several parts, all of which attempt to reduce the list of acceptable MCUs to a single choice. These parts include pricing, availability, development tools, manufacturer support, stability, and sole-sourcing. The whole process may need to be iterated several times to arrive at the optimum decision. 465 E. Applications support. and indexing operations? The choice of implementation language (high level vs assembler) can greatly affect system throughput, which can then dictate the choice of 8I16/32-bit architectures, but system cost restraints may override this, Clock speed, or more accurately, bus speed, determines how much processing can be accomplished in a given amount of time by the MCU. Some MCUs have a narrow clock speed range. whereas others can operate down to zero. Sometimes a specific clock frequency is chosen in order to generate another clock required in the system, e.g., for serial baud rates. In general, computational power, power consumption and system cost increase with higher clock frequencies. System costs increase with frequency because not only does the MCU cost more, but so do all the support chips required. such as RAMs. ROMs. PLDs. and bus drivers. Consider also the processing technology of the MPU; Nchannel metal-oxide semiconductor (NMOS) vs high-density complementary metal-oxide semiconductor (HCMOS). In HCMOS. signals drive from rail-to-rail. unlike earlier NMOS processors. Since these criteria can significantly affect noise issues in system design. HCMOS processors are usually preferred. Also. HCMOS uses less power and thus generates less heat. The design geometries in HCMOS are smaller which permit denser designs for a given size. and thus allow higher bus speeds. The denser designs also allow lower cost. for more units can be processed on the same sized silicon wafer. For these reasons. most MCUs today are produced using HCMOS technology. 1. Specific group who does nothing but applications support? 2. Application engineers, technicians, or marketers? 3. How knowledgeable are the support personnel? Are they truly interested in helping you with your problem? 4. Telephone and/or FAX support? 4. Manufacturer's history, Le., "track record." A. Demonstrated competence in design. B. Reliability of silicon, i.e., manufacturing excellence. C. On-time delivery performance. D. Years in business. E. Financial report. SYSTEM REQUIREMENTS Applying system analysis to ihe current project will determine the MCU requirements for the system. What peripheral devices are required? Is the application to be bit manipulating or number crunching? Once data is received, how much manipulation is required? Is the system to be driven by interrupt, polled, or human-responses? How many devices/bits (I/O pin!?) need to be controlled? Among the many possible types of I/O devices to be controlled/monitored are RS-232C terminals, switches, relays, keypads, sensors (temperature, pressure, light, voltage, etc.), audible alarms, visual indicators (LCD displays, LEOs), analog to digital (AID), and digital to analog (D/A). Is a single or multiple voltage power supply required for the system? What is the power supply tolerance? Is the device characterized for operation at your system supply vo~age? Are the voltages to be held to a small fixed percent variation or are they to operate over a wider range? What is the operating current? Is the product to be ac or battery operated? If battery operated, should rechargables be used, and if so, what is the operational time required before recharging and the required time for recharging? Are there size am;! weight restrictions or aesthetic considerations such as shape and/or color? Is there anything special about the operating environment, such as military specification, temperature, humidity, atmosphere (explosive, corrosive, particulates, etc.), pressure/altitude? Is the application to be disk-based or ROM-based? Is it a real time application, and if so, are you going to build or purchase a real time kernel program or maybe a public domain version will suffice? Does your schedule contain enough time and personnel to develop your own? What about roya~y payments and bug support? Much more investigation is required for real time applications in order to evaluate their special requirements. MCU RESOURCES By definition. all MCUs have on-Chip resources to achieve a higher level of integration and reliability at a lower cost. An on-Chip resource is a block of circuitry built into the MCUwhich performs some useful function under control of the MCU. Built-in resources increase reliability because they do not require any external circuitry to be working for the resource to function. They are pre-tested by' the manufacturer and conserve board space by integrating the circuitry into the MCU. Some of the more popular on,chip resources are memory devices. timers. system clock/oscillator. and I/O. Memory devices include readiwrite memory (RAM). read-onlymernory (ROM). erasabte programmable ROM (EPROM). electrically erasabte programmable ROM (EEPROM) and electrically erasable memory (EEM). The term EEM actually refers to an engineering development version of an MCU where EEPROM is substituted for the ROM in order to reduce development time. Timers include both real time clocks and periodic inlerrupttimers. Be sure to consider the range andresolution of the timer as well as any subfunctions. such timer compare and/ or input capture lines. I/O includes serial communication ports. parallel ports (I/O lines). analog-to-digital (AID) converters. digital-to-analog (D/A) converters. liquid crystal display drivers (LCD). and vacuum fluorescent display drivers (VFD). Other less common built-in resources are internal/external bus capabiHty. computer operating properly (COP) watchdog system. clock operating property detection. selectabte memory configurations. and system integration module (SIM). The SIM replaces the external "glue" logic usually required to interface to external devices via chip select pins. On most MCUs with on-chip resources. a configuration register block is included to control these resources. Sometimes the configuration register block itself can be set up to appear at a different location in the memory map. Sometimes a user as GENERAL MCU ATTRIBUTES MCUs can generally be classified into S-bit. 16-bit, and 32-bit groups based upon the size of their arithmetic and index register(s), although some designers argue that bus access size determines the SI16/32-bit architecture. Is a lower-cost 8-bit MCU able to handle the requirements 01 the system, or is a higher-cost 16-bit or 32'bit MCU required? Can S-bit software simulation of features found on the 16-bit or 32-bit MCUs permit using the lower-cost S-bit MCU by sacrificing some code size and speed? For example, can an 8-bit MCU be used with software macros to implement 16-bil accumulator 466 contractors? Is your company satisfied with your current MCU manufacturer's product line and services? and/or factory test register is present, which indicates concern for quality by the manufacturer. With configuration registers also comes the possibility of errant code altering the desired configuration, so check for "Iock-our' mechanisms, Le., before a register can be changed. a bit in another register must first be altered in a certain sequence. Although configuration registers can at first be very confusing and intimidating because of their complexity, they are extremely valuable because of the flexibility they offer at a low cost so that a single MCU can serve many applications. SUPPLIER ATTRIBUTES The third step is pruning the list of technically acceptable MCUs by examining the MCU manulacturer and supplier. Le., the companies with which you plan to enter into a long-term relationship for mutual benefit. A supplier can either be the MCU manufacturer itself, or it can be a lull-service dealer who is the authorized representative for several manufacturers. A supplier with a broader range of products and a reputation for quality, reliability, service, and on-time deliverability at a fair price can best serve your needs_ Additionally, the more products you purchase from one supplier, the more leverage you obtain for pricing, service, and support. Always keep in mind that although your dollar volume may seem high to you, it is always a relative amounttothe total business of the supplier. Suppliers who can furnish not only MCUs, but memories (RAM and ROM), discrete devices (transistors. diodes, etc.), standard digital logic devices (7400, 74HCOO, etc.), specialty chips, customer specific devices (CSIC), application specific devices (ASIC), and programmable logic devices (PLDs), will be better suited to serve your growing needs. Has the manufacturer and/ or supplier won any awards for quality, reliability, service, and/ or deliverability? Be suspicious of self-bestowed awards. MCU INSTRUCTION SET The instruction set and registers of each MCU should be carefully considered, as they play critical roles in the capability of the system. Have software engineers study the indexed addressing modes versus the anticipated needs of your system. Are there any specialty instructions available which could be used in your system. such as multiply, divide, and table lookupl interpolate? Are there any low power modes for battery conservation, such as stop, low power stop, and/or wait? Are there any bit manipulation instructions (bit set, bit clear, bit test, bit change, branch on bit set, branch on bit clear) to allow easier implementation of controller applications? How about bit field instructions? Be dubious of fancy instructions which seem to do a lot in one instruction. The real measure of performance is how many clock cycles it takes to accomplish the task at hand, not how many instructions were executed. A fair comparison is to code the same routine and compare the tota/number of clock cycles executed and bytes used. Are there any unimplemented instructions in the opcode map and what happens if they are accidently executed? Does the system handle this gracefully with an exception handler or does the system crash? MANUFACTURER ATTRIBUTES Other criteria to consider in selecting the MCU manufacturer/supplier are stability, sole-supplier status, literature, and support. Stability can best be ascertained by considering the number of years in business and obtaining a Dunn & Bradstreet rating piUS copies of past Annual and Quarterly Financial Reports. Your company's PurchaSing and Credit Departments can greatly assist you in these areas. listing on a major stock exchange is another sign of stability. A local stock broker can assist you in obtaining up-tO-date information for those manufacturers listed on stock exchanges, or you can visit your local library to check the Periodical Guide for pertinent information. The Wall Street Journal is another excellent source of up-to-date financial news. Sole-supplier status is unfortunately usually the norm, as most MCU manufacturers do not often cross license their products to other manufacturers. If the manufacturer has a good track record for supply, delivery, and pricing, sole-supplier status should not be a problem. MCU INTERRUPTS Examining the interrupt structure is a necessity when constructing areal time system. How many interrupt lines or levels are there versus now many does your system require? Is there an interrupt level mask? Once an interrupt level is acknowledged, are there individual vectors to the interrupt handler routines or must each possible interrupt source be polled to determine the source of the interrupt? In speed critical applications, such as contrOlling a printer, the interrupt response time, Le., the time from the start of the interrupt (worst case phasing relative to the MCU clock) until the first instruction in the appropriate interrupt handler is executed, can be the selection criterion in determining the right MCU. MANUFACTURER SUPPORT Direct manufacturer support includes Marketing/Sales, FieldApplication Engineers (FAEs), and Application Engineering. Are the FAEs near your Site? When telephoning for support, can you reach the support person directly or do you play "telephone tag"? Are calls returned promptly? Is there a toll-free 800 number? Is there a FAX number? How many phone lines are available? Are the phone lines always busy? Do they have an individual Voice Mail answering system or does a secretary in another office take "While You Were Out" messages which must be physically relayed to the support person? Voice Mail is a state of the art computer controlled answering system whereby each user effectively has their own password protected answering machine with enhanced capabilities, such as message forwarding. What hours do the support personnel work? Do they have other duties and/or responsibilities besides support? How many support personnel are COMPANY ATTRIBUTES Examine the assets of your own company with a little truthful introspection. Does your company have a significant investmentin knowledgeltraining 01 existing personnel with a particular MCU manufacturer and in the development tools for those MCUs? Does your company own enough development tools or will you have to buyor rent more? If a new MCU is under consideration, are there development toots available, such as high level language compilers, assembler/linkers, evaluation modules, and debuggerslemulators? Are your present development tools easily expandable for new MCUs? Will additional personnel have to be hired and trained for this project? Can you hire an expert to train/lead the rest of your team? Does your budget permit hiring additional permanent staff and/or 467 there? Are factory personnel. such as Product Engineers. Manufacturing Engineers. Quality Engineers. Hardware Engineers. and Software Engineers. readily available to assist the support personnel? Are the factory people on-site with the support personnel? Are the support personnel knowledgeable. have a helpful attitude. and do they "follow through" in a timely manner when they promise to do something. such as research your problem or send you something? Does it come via regular mail. UPS. or Overnight Express? Were you charged for fast delivery? Does the Manufacturer have an Electronic Bulletin Board Service (BBS) where information such as application programs. product news. software updates. source code. bug lists. electronic mail. and conferencing are available? What baud rates are supported? How many phone lines are available? What are the hours of operation? Do you need any special brand of computer and/or modem to access it? Is there a system operator (sysop) assigned to manage it? system requirements can you predict that will be needed in possible future iterations of this product? And lastly. consider value. for if two MCUs cost the same but one offers a few more features which are not required today but would make future expansion easier for no additional cost. chose that MCU. CUSTOM MCU SOLUTION If there is no commercially available single-chip MCU that meets your system requirements and your anticipated production volume is high enough. you should consider using a custom CSIC MCU. In a custom CSIC MCU. you choose the core processor type and the exact peripherals needed for your system from a list of standard cells available. This gives you the benefits of a single-chip solution for slightly more cost. so the production volume must be high enough to justify it. Additionally. some manufacturers will not even start production unless the ordervolume is around one million units. However. if your production volume can be combined with others to reach the one million level. production could be started. Or. if the desired unit is judged to be have a broad enough market appeal. the manufacturer may proceed with production anyway because they plan to offer it as a standard product. As the deSign initiator you may be able to obtain an exclusivity clause whereby you have sole rights to the CSIC MCU for a specific period of time. Then the manufacturer can start marketing it to everyone. LITERATURE SUPPORT Literature covers a wide selection of printed material which can assist you in the selection process. This includes items from the Manufacturer. such as Data Sheets. Data Books. and Application Notes. as well as items available at the local bookstore and/or library. Items from the local bookstore and/or library indicate not only the popularity of the manufacturersl MCUs under consideration. but also offer unbiased opinions when written by non'manufacturer related authors. TEAMWORK Finally. as project leader you can do all this investigative work yourself. or you can start involving your team by assigning investigative tasks to them. such as having the software engineers evaluate the instruction sets of each MPU under consideration. By involving your team early in the decision process. you not only build team spirit. but gain individual commitment to the project via active participation. This approach undoubtedly generates some conflict. as everyone has their own opinion. but your job as project leader is to be a mediator. Alter listening to all opinions. it is still your choice as project leader. As in political elections. once the winner of the primary has emerged. all party members are expected to fully support the winner. and so should all project team members support the decisions of the project leader in order to ensure a successful project. . FINALIZING THE SELECTION As a final step to help in the selection process. build a table listing each MCU under consideration on one axis and the important attributes on the other axis. Then fill in the blanks from the manufacturer's data sheets in order to obtain a fair side-by-side comparison. Some manufacturers have pre-made comparison sheets of their MCUproduct line which makes this task much easier. but as with all data sheets. be sure they are up to date with current production units. Among the possible attributes are price (for the anticipated production volume. including predictions of future pricing. i.e.• will the price be decreasing as you move into production?). RAM. ROM. EPROM. EEPROM. timer(s). AID. D/A. serial ports. parallel ports (1/0 control lines). bus speed (minimum/maximum). special instructions (multiply. divide. etc.). number of available interrupts. interrupt response time (time from start of interrupt to execution of the first interrupt handler instruction). package sizeltype (ceramic DIP or LCC. plastic OY DIP or O.6 DIP. shrink DIP (.071Hpin spacing). PLCC. PQFP. EIAJ QFP. SOIC; some involve surlace mount technology). power supply requirements. and any other items important to your system design. The tables at the end of this application note detail the attributes of Motorola's MCU product line. II alter all this. you still have more than one MCU on your list. consider expandability and value. What expansions in the CONCLUSION In conclusion. selecting the right MCU for your project is not an easy decision. as MCUs have become more complex devices since on-Chip resources were added. And since the trend is towards more on-chip integration 01 off-chip resources to reduce system costs. the decision will become increasingly complex with time. This application note is not intended to make the choice for the designer. but to serve as a thought provoking guideline as to all the possible selection criteria that should be considered in this important decision process. H 468 MOTOROLA 8-BIT M68HC11 MICROCONTROLLER FAMILY MOTOROLA MICROCONTROLLER COMPARISON GUIDE Motorola maintains a comparison guide on our most popular M68HC05, M68HCll, and M68300 Families of microcontroliers (MCUs). For a copy, please contact the Motorola Literature Distribution Center nearest you' and request the current MICROCONTROLLER (MCU) QUARTERLY UPDATE FOLDER, Motorola part number SGI48/D. Programming Model The M68HCll Family of MCUs has eight central processing unit (CPU) registers available to the programmer as shown in Figure 2 below. MOTOROLA 16·/32·BIT M68300 MICROCONTROLLER FAMILY MOTOROLA 8·BIT M68HC05 MICROCONTROLLER FAMILY Programming Model The M68300 Family of MCUs has 23 central processing unit (CPU) registers available to the programmer as shown in Figures 3 and 4 below, organized inlo User and Supervisor models. Programming Model The M68HC05 Family of MCUs has five central processing unit (CPU) registers available to the programmer as shown in Figure 1 below. 7 0 7 0 ~I______________~'A L . I_ _ _ _ _ _ _- - - ' , 15 ! x o 11 I PCl I --------~--------------------------~ 15 r-- 11 I0 0 0 0 1 o I 7 0 1111111HIIINlzlcicCR 1. Length depends on the address/memory size of the individual M68HC05, e.g., a 2K memory map requires an II-bit program counter and stack pOinter as shown. Current length ranges from 11 to 14 bits (2K to 16K). Figure 1. M68HC05 Programming Model o7 A , 0 B I~:B 15 0 15 0 15 0 15 0 15 0 IIX I· IIV I PC I I sp L . -_ _ _ _ _ _ _ _ _ _ _ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - ' 7 0 I sl xl Hili NI zl vi CICCR Figure 2. M68HCll Programming Model 469 31 1615 o 87 ~__----------------------------~--------------~--------------~OO ~-__----__--------------------~--------------~----~--------~01 ______________________________ ______________-+______________-402 ~ ~ 03 r---------------------------~------------_r------------~ 04 r---------------------------~------------_r------------~ ~--------~~------------------~--------------~--------------~05 r---------------------------~------------_r----~------~ ~--------------------------~------------~------------~ 31 1615 o r---------------------------~--------------------------~ r-______________________________ ;-______________________________ 06 07 AD ~A1 ~------------------------------~------------------------------~A2 ~------------------------------~------------------------------~A3 ~------------------------------~------------------------------~A4 r-____ ________________________;-______________________________ ~ ~A5 ~------------------------------~------------------------------~A6 L -______________________________...L.______________________________--J A7 (USP) ~ ~I 0 ______________________________________________---JlpC 15 87 0 1<--_ _..;;..0_ _. . 11_ _ _ _ _---11 CCR Figure 3. M68300 User Programming Model 31 1615 0 1....__________________________..1.-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---11 15 87 ~ 0 ______LI_____(~CC~R~)__~1~1 0 ________________________________________________ 1~ ~I AT (SSP) ~IVBR 31 [~- ..-----------------------------------------r------; ,_.,_ ..'.____._ . ___".,_""'~,_._. __,, ___ ,,_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ -'-_ _ _.J 1. The Status Register (SR) consists of two halves as shown below. SYSTEM BYTE 15 14 13 12 11 10 USER BYTE 9 8 0 7 I~T_1~IT~0~I~s~I~0~1~01~1~2~1~11~1~lo~I________~CC~R~,________~ISR 7 0 1 0 1 0 I 0 1 X 1 N 1 z 1 vic I CCR Figure 4. M68300 Supervisor Programming Model Supplement 470 SFC OFC Factory Applications Support Group which has a highly trained staff 01 engineers to relentlessly pursue the answers in both hardware and software. Additionally, the Aps Group has the backup support of the entire on-site Factory staff to ensure answers to your questions. DEVELOPMENT SUPPORT Development support for Motorola MCUs is available from Motorola in the form of low cost Educational Computer Boards (ECBs), Evaluation Boards (EVBs), and Evaluation Modules (EVMs), and higher priced emulator systems with bus analysis (CDS Jewelbox and HDS-300 systems). EVBs and EVMs are on the order of hundreds of dollars, whereas emulators are on the order of thousands of dollars. Simple assemblers are available for no charge on the Freeware BBS, whereas more powerful assemblers with such features as macros, structured assembly, conditional assembly, and relocatable modules (for linking) are available for a few hundred dollars for popular PCs. Additionally, the Freeware BBS contains the most up to date information on Motorola MCUs and has a wealth of free software. Also available are literature and Application Notes on many subjects, including a title index, from Motorola's Literature Distribution Centers. MOTOROLA LITERATURE DISTRIBUTION CENTERS Motorola has several Literature Distribution Centers (LDCs) worldwide with the main one located in Phoenix, Arizona, U.S.A. They carry all Motorola literature, including Data Books, Data Reference Manuals, User Manuals, Application Notes, brochures, books on Motorola products, etc. Contact your local Motorola representative or the LDC office nearest you and they will be most happy to serve you. The LDC addresses are listed on the back cover of this application note. The phone numbers are listed below or consult your local telephone directory book. MOTOROLA FREEWARE ELECTRONIC BULLETIN BOARD SYSTEM Motorola Literature Distribution Center Phone: (602) 994-6561 "Freeware" is the name olthe electronic bulletin board system (BBS) dedicated to support Motorola Microprocessor Units (MPUs) and Microcontroller Units (MCUs). The Freeware BBS contains the most up to date information, including support software for EVMs, PCs, and MACs, development software for MCUs and MPUs, confidential electronic mail service, file downloads/uploads, distributor directory and sales offices by state, press news, development support, literature, mask set erratas, devices/packages being phased out, ECBI EVB/EVM product literature, and contest/promotion/seminar information. Freeware is on-line 24 hours a day, everyday except for maintenance. To use the BBS, you need a 300-2400 baud modem, and a terminal or personal computer (PC) with communications software (e.g., Kermit, ProComm, etc.). Set your character format to 8-bit, no par~y, 1 stop bit and dial the Freeware number (512) 891-FREE (891-3733). Press RETURN and then enter the requested information to log on. You are now a registered user. Follow the menus for the desired functions (e.g., download, upload, mail, conferences, etc.). On-line help is available. For most up to date information, please contact the Motorola Literature Distribution Center nearest you and request the MeU "FREEWARE brochure, Motorola part number BR5681D. Motorola Semiconductors H.K. Ltd. Phone: 480-8333 Motorola Ltd.; European Literature Center Phone: (908) 61 4614 Nippon Motorola Ltd. Phone: 03-440-3311 ABOUT MOTOROLA Motorola was founded in 1928 by Paul V. Galvin and has continuously been in the electronics business since then. Motorola moved up to number 48 on the 1989 Fortune 500 list of the largest U.S. industrial corporations with $9.62 billion in sales and is the #3 in electronics in the U.S., behind General Electric and Westinghouse Electric. In terms of semiconductor market share, Motorola is #1 in North America and #4 in the world. Motorola'S Microcontroller Division is the world's #1 supplier of 8-bit MCUs, with more than SOO million in use around the globe. Motorola was ranked #3 by Fortune Magazine's poll of America's Most Admired Corporations. Motorola has consistently demonstrated product and technology leadership along with the global capability and teamwork to get the job done for the lowest possible price. Motorola is driven by Total Customer Satisfaction, which means global design and manufacturing facilities, on-time delivery, and above all, a dedication to quality that is unsurpassed in the industry. Motorola'S relentless pursuit of perfection is the ~ey in achieving Six Sigma Quality by 1992. This translates to virtual perfection (3.4 defects per million parts). There Is only one goal: zero defects in everything Motorola does. APPLICATIONS SUPPORT Application support for Motorola products is provided by the same local salesperson and Field Application Engineer (FAE) that made the sale. If a technical question can not be answered locally by the salesman or FAE, the FAE will contact the 471 the Reagan Administration. It is awarded to companies that demonstrate superior company-wide management of quality processes. A panel of judges examines the quality standards in eight critical business areas for each company applying for the award. Six prizes are offered each year - two each for manufacturing companies and service companies, and two for small businesses. In the two years the award has been offered, only five companies out of a potential 12 winners have met the rigid standards required to capture the prize. In 1988, Motorola was one of only three Baldrige winners out of 66 applicants. Winners of the Malcolm Baldrige National Quality Award must wait five years before they can apply again. Therefore, Motorola will be eligible to compete again in 1993. RECENT AWARDS PRESENTED TO MOTOROLA 1990 GM Mark of Excellence Award This award was presented by Del<;o Electronics for outstanding performance as a supplier in all five areas covered by GM's supplier monitoring program - quality, cost, delivery, technology and management. Currently, less than 30 suppliers have earned the GM Mark of Excellence award. 1990 Computer Design s Vendor Preference Survey reported Motorola Microcontrollers as #1 in the three measured categories of Response Time, Documentation, and Applications Support. 1989 Texas Instruments Information Technology Group Supplier Excellence Award Presented to less than one percent of Tl's suppliers worldwide for quality and on-time delivery performance. 1988 Dataquest Supplier of the Year 1989 Chrysler Motor Company Pentastar Award Presented to select group of Chrysler's suppliers worldwide for quality, price, delivery, and technology. 1988 Texas Instruments Data Systems Group Supplier Excellence Award Presented for demonstrated excellence in meeting Texas Instrument's requirements. 1989 Ford Motor Company QI Preferred Quality Award A total quality supplier award; requires consistent high quality coupled with excellent pricing and delivery. 1987/1988 Bosch Group Re<;ognition Award Presented for quality and special performance as a supplier to the Bosch Group. 1988 Malcolm Baldrige National Quality Award This award was created by Congress in 1987, named after the late Malcolm Baldrige, Secretary of Commerce during 1987 Delco Electronics Award of Excellence Presented for superior quality and delivery performance. 472 AN1058 Reducing AID Errors in Microcontroller Applications Many significant benefits can be realized in an electronic product by converting analog signals into the digital domain. From drift-free signal filtering to extremely reliable signal detection. the digital domain offers a level of performance many times only approximated by its analog circuit-based counterpart. Once cost prohibitive. converting analog signals into the digital domain has become more cost effective. These decreasing costs, increasing digital semiconductor speeds. and the benefits of digital processing have contributed significantly to the increasing popularity of digital systems and to the rise of the digital system with built-in analog interfaces. One such popular system on silicon is the single-chip microcontroller unit (MCU). Now available from many manufacturers and in many forms. MCUs with resident analog interfaces like analogto-digital converters (ADCs) and other on-chip peripherals can provide unsurpassed cost effectiveness to a product's design. The MCU with integral ADC may easily be used to convert analog signals in the digital domain with the convenience of an already defined on-chip ADC-to-CPU interface. In addition, the MCU offers the flexibility afforded to all software-based systems. MCUs have liberated many board-level designers from selecting. designing. and debugging microprocessor peripherals in multichip assemblies. This type of highly integrated solution is becoming more popular than the multichip solution. Consequently. it is reasonable to expect that the practicing design engineer will eventually work with an MCLJ-based system. Yet, despite the advantages of the MCU system, some integrated peripherals such as the ADC offer new challenges to the designer. By incorporating a wide bandwidth linear system, such as an ADC, on the same die with a high-speed digital central processor unit (CPU), ADC performance can be adversely affected. Noisy ADC readings functionally manifest themselves in a range from merely annoying and relatively benign glitches to more catastrophiC hard failures. In any case, an MCU-based system does not have to be at the mercy of poor MCU/ADC performance. Fortunately, by following some fairly rudimentary systems-level. guidelines in the design phase of the MCU-based product, potential ADC performance problems can be avoided. To resolve ADC performance issues, it is necessary to understand a little about the nature of the MCU and the various areas of susceptibility of several ADC types. Although much information presented in this application note assumes that the ADC is resident on-chip with the CPU, other converter types not typically found on-Chip with MCUs are discussed for those instances in which a multichip combination is encountered. The following paragraphs also apply to these less frequent hardware combinations. ADCTYPES Even when the ADC is available on-Chip with an MCU where the unpleasant task of interfacing and debugging the ADC-to-CPU interface is done, obtaining maximum performance from the ADC requires attention to application details of the given MCUlADC combination. The type of design precautions and applications details needed to avoid problems varies as a function of the type of ADC used. Understanding the mechanics of the given ADC is crucial to improving performance. ADCs may be categorized into five main categories: integrating, servo, flash, successive approximation, and hybrid. Although each type has unique capabilities and traits, each has surprisingly similar points of vulnerability. The integrating converter has appeal for applications requiring high resolution (16-bit or higher) and low cost. Because the basic converter is simply implemented (see Figure I (a)), hardware is minimized while high resolution is obtained. In addition, the integrating ADC may provide some noise immunity that is not feasible with higher speed designs. Although it is possible to build the integrating converter onto MCU chips (there is nothing technologically impeding such a construct), its lower speed has apparently been discouraged by MCU designers since it is currently not offered on an MCU by a major manufacturer. Whereas the integrating converter tends to be the slowest of ADC types, the servo converter tends to have the highest resolution and fastest conversion times in its most recent advancement-the sigma-delta converter. The more traditional servo converter tries to balance the charge or voltage on an input comparator by using a feedback configuration (see Figure I (b)) to force slewing from a previous charge or voltage to the current input signal level applied to the other input of the same comparator. This process is followed by appropriately changing a digital counter up or down (in this form, the converter is often called a tracking converter). Before the sigma-delta variation, the servo converter was less popular than other convertertypes primarily due to its slew-rate limitation. Nothing about the servo converter would prevent its inclusion onto an MCU die; once BiCMOS processes improve, this converter type will probably become a popular feature of future MCUs (particularly the sigma-delta variation, most of which is linear circuitry). Although the sigma-delta variation of the servo converter provides high-resolution conversions and maintains a relatively high throughput rate, the fastest type is the flash converter. By stringing together several voltage comparators (one per desired level to be detected), conversion bandwidths in excess of 100 MHz are now quite commonplace (see Figure 1(c)), albeit at lower resolutions (4-6 bits are common). As the input voltage is applied to one input of all the comparators, a set of 473 OUT VIN --------i (a) Integrating ADC VIN --------i (b) Tracking/Servo AOC COMBINATIONAL LOGIC OUT . . 1v-rJ reference voltages are applied to the other comparator inputs. After a period of time has elapsed, determined primarily by the propagation delays through the comparators, the discrete-level representation olthe input voltage is available at the comparator outputs. Flash conversion, although incredibly fast, requires a tremendous number of devices to implement even modest-resolution converters. In addition to the number of transistors necessary to implement each comparator, the outputs of each comparator are typically input to a combinationallogic array to form a desired output code. Consequently, this converter, which consumes much silicon area when compared to other converter types, has not been widely accepted by MCU designers and users. The fourth ADC type is the successive-approximation converter (SAC). Of all current converter types, SAC is the most popular (see Figure 1(d». This popularity is primarily due tl) its applicability to smaller circuit requirements, medium to fast conversion speeds, and medium- to high-resolution applications (8-16 bits). Like other converter types, the SAC uses a differential voltage comparator to compare the input signal with a reference voltage. By performing a binary search, conversion rates of one bit per clock are possible. Because only one comparator is typically required and the output code is inherent in the conversion process, circuitry and silicon surface area are reduced when compared with other conversion methods. Although the exact implementation varies from siliconchromium-based to charge-redistribution, this ADC is currently the most prevalent type found on MCUs. The fifth ADC category is the hybrid converter. In this case, the term "hybrid" is not used to reference a specific implementation approach, but rather implies combining one or more AOC types to form an ADC with different performance characteristics. Forexample, some olthe faster and higher resolution AOCs now employ a hybridized technique which utilizes flash-conversion prescaling followed by an SAC. In this case, almost instantaneous prescaling is accomplished and easily interfaced to an existing SAC design. Hybrid converters are a very viable alternative as an MCU peripheral and may find eventual popularity in MCU deSigns when higher resolution converters are needed. ADC NOISE SUSCEPTIBILITY The comparator is the cornerstone of the AID conversion process. The ability of the comparator to announce the presence·of small voltage/current differentials with large changes in its output voltage make the comparator invaluable to the AID conversion process. Yet, this same feature also accounts for the largest potential source of ADC malfunction. Of course, degradation of the comparator's desired action, and hence the ADC, is most usually caused by unwanted noise. Two basic characteristics of the comparator affect noise susceptibility: bandwidth and power supply connections. Wide bandwidth comparators easily respond to noise as well as to signals. Even in the low-speed integrating converter, the accuracy of measurement is heavily contingent upon the comparator's speed of operation. To illustrate, imagine that a (c) Flash ADC V IN - - - - - - - ; (d) Successive Approximation AOe Figure 1. AOC types 474 very slowly varying input signal has been applied to an input of such a comparator. For a single-slope integrating converter, the other comparator input will have a linearly increasing voltage (or other convenient shape) applied to it. As this voltage ramp increases, an independent digital counter (started at the same time the voltage ramp began) will count clock pulses provided by some timebase. When the voltage ramp finally exceeds the input voltage, the comparator will change state. If the comparator fails to respond to the voltage ramp in a timely fashion, the digital counter will register an incorrect count when compared to the results obtained by a perfectly fast comparator, implying that the response time (characterized by bandwidth) must be reasonably fast even in the slowest ADC types. Consequently, a wide bandwidth comparator will appropriately respond not only to input/reference signals but also to any other signal present at the comparator input terminals (including noise components superimposed upon the signals of interest). The typical comparator uses some form of differential front end. The operation of the differential front end is dependent upon biasing networks that are ultimately connected to the supply terminals of the comparator. Therefore, the comparator should be considered as a five-terminal device - two differential inputs, one output, and two inputs to the biasing networks - for the purposes of deSigning with the ADC. The implication is that signals present at the supply terminals of an ADC, particularly the high-frequency signals typically superimposed on the power supply in digital systems, can affect comparator and ADC operation. Due to the high bandwidth olthe comparator found in ADCs, the designer of a given system should be extremely careful about the type and amount of signals allowed to reach the comparator stage of the ADC, particularly the power supply terminals. For this reason, some of the more mundane and overlooked aspects of electrical product deSign, such as printed circuit design and circuit interconnection, become increasingly critical to.the success of the MCUlADC system. APPROPRIATE DESIGN TECHNIQUES Most of the MCU is digital. As seen in Figure 2, a major portion of the MC68HCli E9, a representative MCU, is digital circuitry. Thus, it is reasonable to assume that digital design practices will generally be employed when designing with the MCU. With an analog-based subsystem, such as the M68HCli ADC, normally accepted digital design practices may not be sufficient to ensure satisfactory performance of the converter. As an illustration, consider noise levels normally found on the power supply of a typical high-speed HCMOS digital system. It is not unusual to find 100 mVpp broadband noise riding on top of the positive voltage rail. With a nominal S V HCMOS system, the resulting voltage drop, down to 4.9 V, is above the VOH for HCMOS. Thus, the 100 mV signal will probably not upset circuit operation. When present in such a· robust digital system (HCMOS), this 100 mV noise signal is a mere visual nuisance on the OSCilloscope. Because of the theoretically infinite signal-to-noise ratio of digital gates, the presence of the 100 mV noise poses no practical threat. 475 However, when such a noise signal is inserted into an ADC system, the results can be much more dramatic. In an 8-bit ADC system with a nominalS V reference, this same 100 mV noise can result in a greater than S-bit error in the ADC reading. Thus, an MCU system utilizing an ADC assumes a different electrical character that requires application of design practices not traditionally used in the design of digital systems. What design practices should be used? To correct or avoid a noisy ADC/MCU design, separate the noisy signals from the sensitive ones. The challenge is to design a system in which this separation is practically realized. The closer to the ideal of completely separating the noisy signals from the sensitive ones, the better. For situations where the noisy and sensitive circuits cannot be completely separated, reduce the noise coupling as much as possible. Since it is difficult to axiomatically specify how to implement both concepts in all cases, a illustration will aid understanding and provide an analogy by which individual situations may be gauged. Motorola tests 100% olthe ADCs found on their MCUs. Before any M68HCli ADCs leave the factory, they have been tested and verified for specified ADC performance. Even so, it is possible to operate the M68HCli in an environment that causes the M68HCli ADC to subsequently malfunction. These two scenarios in the life of such an MCU indicate not, strictly speaking, a parts-related anamoly, but rather a significant interaction of the part's characteristics with the electrical environment. Typically, a large contributor to malfunction is the printed circuit board (PCB) layout. Since the PCB can influence many of the circuit parametrics (reactance, voltage, etc.), the PCB layout can help or hinder ADC performance. Yet, the PCB layout is not typically done by the circuit's designer. More importantly, laying out the PCB artwork, up to and including the width and placementoftraces, is often performed by people without adetailed knowledge of correct electrical circuit design practices. Many PCB designers are only concerned with ensuring that they have connected all the points connected in the schematic. Although this has its economic advantages, this can be a dangerous proposition with regard to ADC performance. Figure 3 shows an example of such a PCB layout which, although it manages to distribute the power to all of the devices, provides several potential sources of ADC/MCU performance problems. First, the MCUlADC is placed farthest from the powerterminal, meaning that the MCU return currents will be mixed with the digital circuit currents between the MCU and the powerterminal. Although the MCU may not produce large return currents in the power return, high-speed digital circuits typically do. The inductance of PCB traces at high frequencies can be significant enough to produce large noise spikes when measured between the ground pin of the MCU and the ground terminal of the board. Second, the opamp, which buffers the Signals to the ADC inputs on the MCU, is physically located close to the MCU but is electrically located in a very poor place. As with the MCU, the opamp power supply return will be corrupted with high-frequency spikes. However, the voltage drops measured PULSE ACCUMULATOR r I g ROM -12K BYTES ~~:1C1f+---f ~ TIMER PERIODIC INTERRUPT RAM - 512 BYTES PA7 PA6 PAS PAl OC2 1----,100/ OC3t--+! 1C2f+---f 1C3~---I COP WATCHDOG PM PAl PA2 PAl PAO PD5 P04 P03 SPI EEPROM - 512 BYTES PD2 PE7 PE6 PES POI SCI PDO PE4 PE3 PE2 PEl PEO M68HCll CPU VRH - - - - - + ! VRL-----~ RESET XIRO IRO IVpPBULK) INTERRUPTS SELECT SINGLE CHIP MODS IV STBY ) o ~ ~ EXPANDED o > Figure 2. MC68HC11 E9 Block Diagram 476 between the opamp and the MCU will be even worse than those measured between the MCU and power terminal. When deciding which parts are to be jointly located on the PCB. the electrical impact of conductor distance and tolerance to any induced noise must be considered. Third. the bypass capacitors. as shown. are ineffectual in reducing high-frequency noise on VDD. To perform the decoupling function properly. bypass capacitors should be attached as close as possible to the IC power pins they are intended to bypass. In addition. PCB trace inductance should be minimized between the leads of the capacitor and the power pins. Figure 3 illustrates a few of the PCB-related errors that can degrade ADC performance. Specific PCB designs involving MCUlADCs should be carefully engineered. A better PCB layout is depicted in Figure 4. which corrects the defects shown in Figure 3. Figure 3. Poor Layout Design Figure 4. Improved Layout Design 477 A SPECIFIC MCU WITH ADC Other factors involving a more specific ADC system contribute to reduced ADC performance. Thus, this discussion will focus on the ADC system found on the Motorola M68HCll Family of MCUs. A unique implementation of an SAC, the standard M68HC 11 (2 MHz bus) ADC provides a 161-1s 8-bit AID conversion with the convenience of an on-chip MCU peripheral. The ADC is a charge· redistribution SAC. The digital-to-analog converter (DAC) is implemented with capacitors rather than the usual R-2R silicon-chromium (SiCr) thin-film resistors. Although the SiCr resistor has the advantage over the commonly used diffused resistor in improved temperature stability and tracking, laser trimming is necessary to obtain ADC accuracies compatible with even medium-resolution converters. Processing this R-2R ladder presents a challenge since trimming one resistor in the network will change the current in the previously trimmed bit, requiring an iterative trimming process. Furthermore, the R-2R ladder requires careful control of the ON resistance in the MOS switches because the switches also determine the current flow through the R-2R network. The M68HCll capacitive DAC avoids these shortcomings. The charge-redistribution method is easily fabricated using poly-poly capacitors. No trimming of the poly capacitors or MOS switches is required to obtain medium-resolution accuracies. As an added benefit, a sample-hold function, which extends the effective conversion bandwidth of the ADC, is an inherent byproduct of the redistribution technique. The internal operatives olthe M68HC 11 converter are relevant to preventing or reducing ADC errors. For converters using SiCr R-2R ladders, the impact of parametric phenomena may be different than for the M68HC11. It is necessary to understand the nature and implementation of the ADC to realize the highest performance from it. To understand the M68HC 11 conversion process, a 2-bit example is presented (see Figure 5). A conversion is accomplished by a sequence ofthree operations. In the sample mode (see Figure 5(a)), the top plate is connected to VL (0 V), and the bottom plates are connected to the input voltage, VX, resulting in a stored charge on the top plate that is proportional to the input voltage. In the hold mode (see Figure 5(b)), the top switch is then opened, and the bottom plates are connected to VL. Since the charge on the top plate is conserved, its potential goes to -VX, which is the initial voltage at the input of the comparator. The approximation mode (see Figure 5(c)), begins by testing the value olthe most significant bit by raising the bottom plate of the largest capacitor to the reference voltage, VH. The equivalent circuit is now actually a voltage divider between two equal capacitances. The output of the comparator, after each capacitor is switched, determines whether the bottom plate of that capacitor will remain at VH or be returned to VL before the next capacitor is switched. Conversion proceeds in this manner until all bits have been deter-mined and the result is stored in the successive-approximation register (SAR). The following major sources of M68HC 11 ADC errors controllable by external circuit parameters are discussed in the following paragraphs. (a) Sample Mode "7- 1 1 I~: ~ II IT" VRL (b) Hold Mode 1 " I I -Y' ,?#! RL I' BITI I BIT 0 I SAR (c) Approximation Mode Figure 5. ADC Conversion Modes 478 Leakage Current on AOC Input Pin Charge Time on Sample Capacitor The electrical model of an M68HC II ADC inpul pin is shown in Figure 6. The problem is caused by n-channel device junction leakages at this node (there are no p-channel devices used here). which are worse at high temperatures. Consequently. the leakage current is (I) unidirectional and (2) bound by the maximum speCification of 400 nA. This leakageinduced error would tend to only cause a static lowering of ADC results. To avoid leakage effects. the external circuit network feeding the ADC pin(s) should maintain impedances. which. in the presence of maximum leakage. would guarantee a maximum desired error. For example. if the maximum error (due to leakage) is desired to be 5:1 LSB with a 5 V reference voltage. then the maximum source impedance (resistance) feeding this pin should be 50 kn = (~19.5 mV/400 nA). By lengthening the resistance-capacitance (RC) time constant. comprised of the source resistance feeding the ADC pin and the DAC capacitance evidenced at the pin during the sample mode. errors may result. However. given the size of the DAC input capacitance. the size of the source resistance necessary to induce these RC time-constant errors will probably be inundated by the effects of pin leakage described previously. VOOlVss and Input Terminal Noise The differential comparator used in the M68HCII ADC derives its power from VDD and VSS. the power pins that supply the rest of the M68HCII (see Figure 7). The M68HCII • INPUT PROTECTION DEVICE DIFFUSION AND POLY COUPLER S4KU + -20V <2pF --O.7V 400nA JUNCTION LEAKAGE (SEE NOTE) ~-20PF I CAC CAPACITANCE VRL NOTE: This analog switch is closed on~ dunng me 12·cycle sample lime. Figure 6. Electrical Model of an M68HCll AOC Input Pin f I 1111 ~I 1111 Illy Figure 7. MC68HCll AOC In Sample Mode 479 VTRIP 16 REAL-WORLD EXAMPLE when considered with respect to ADC performance, is a source of noise, partially due to the waveshape and harmonics associated with square waves. In addition, the complex relationship between the primary M68HCII clock and related noise voltages are further complicated by dependance of the M68HC II upon many software combinations, each sufficiently changing the noise characteristics eminating from the M68HCII. Therefore, AOC performance degradation, which is linked to noise generated on VDONSS by the M68HCII, can often appear related to execution of specific software combinations. As established earlier, this is due to the AOC wide bandwidth comparator. When discussing the mechanics of noise phenomena in MCU/AOC systems, it is very difficult to understand how large the noise problem is, how well it is expected to respond to correctiVe action, and how closely the analysis matches the real world. To help resolve these problems, an actualtroubleshooting session involving an M68HCll-based assembly is presented. The subject assembly, an industrial controller, is a typical MCU/CPU installation utilizing the M68HCll in expanded multiplexed (CPU) mode. The customer designed the program memory to expand to 32K x 8, RAM to 2K x 8, an external address decoder, some additional digital 1/0 lines, and analog buffers feeding the ADC inputs. Built on a six-layer PCB, the assembly had the benefit of separate ground and voltage planes, and was designed to be placed in a Faraday shield providing electromagnetic compatability. This assembly was designed without the aid of any of the concepts presented in this applcation note. Understandably, the customer was having difficulty with ADC performance. NOTE Because the M68HCII AOC uses a very wide bandwidth comparator capable of responding to noise components in excess of 20 MHz, it must be guarded against unwanted noise at its input terminals and VOONSS pins. The reference to input terminal noise must be distinguished between noise externally superimposed on the input signal lines that is measured between a system reference and a given input signal (occurs from capacitive coupling between high-impedance ADC inputs and noisy signal sources or electro-magnetic interference) and voltage differentials experienced by different comparator inputs when referenced to each other. The importance of input terminal noise in this context is the presence of non-common-mode differential noise between the biasing networks in the comparator and the input lines. If, under noisy conditions, the same noise is presented to an input to the comparator and one of the supply (or other input) terminals, the common-mode rejection ratio (CMRR) capabilities of the comparator may prevent performance perturbations; whereas, noise presented to either terminal, with respect to system ground, may cause havoc (see Wide Bandwidth Input Signals). Efforts should be made to ensure that noise, if it cannot be reduced further, is also seen by the other comparator inputs to take advantage of the CMRR. Of the ADC error sources, this is one of the most challenging to control in a practical and effective manner. The Problem Functionally, the ADC noise problem manifested itself as an extreme shutdown condition in the final product. Since this assembly provides control to industrial equipment, conditions sensed by this controller could indicate dangerous conditions, which must be dealt with by severe and swift action, including functional shutdown of the controlled equipment. To achieve the safest response times and largest safety margins to such stimUli, the software designers of this system required 64 ~s continuous conversions (> 15 kHz sampling frequency). Once they were run through part of the designer's algorithmn, the conversion results could not deviate more than ±2 counts from the actual system ADC measurements. The M68HCli was selected for this application because of its high level of integration as well as the ±1 LSB 8-bit ADC performance. Errors many times this specification were encountered in the application. Unfortunately, evaluation of the extent of the ADC errors concerned only functional operation of the assembly and manual inspection of ADC values read with an in-circuit emulator, making the problem more serious. An attempt by the hardware engineers to reduce the noise by changing the bypassing scheme yielded no apparent Change in the pattern of product shutdown. In this case, the lack of quantitative data convinced the engineers that they had no control over the problem, diverting attention from the actual cause. When dealing with these types of problems, always instrument the problem correctlythat is, ensure measuring techniques LJsed to observe the malfunction follow these guidelines: Wide Bandwidth Input Signals A certain way to disrupt ADC function is to give the wide bandwidth comparator something to respond to other than the input signal of interest. By designing the electronics feeding the ADC inputs to pass input signals having frequencies that range from DC to purple, ADC problems are usually guaranteed. Thus, this fourth area is a common source of ADC malfunction. 1. Quantify the AlO conversion process with regard to frequency of occurrence and magnitude of error. 2. Ensure that the measurements are with sufficient resolution so that minute improvements or degradations in performance may be monitored and evaluated. 3. Ensure that the number of observed conversions are similar to product usage or are statistically significant to allow inference from the measured sample to actual product operation. Other Error Sources Although occurring less frequently and more subtlely, other error sources can also impact ADC performance: rate of conversion requests to a particular channel and interchannel charge-sharing. These sources and an estimate olthe impact on a given M68HCl1 system are presented in detail in M68HCl1 RM/AD, M68HCl1 Reference Manual. 480 Ha~ the assembly been properly monitored. an improvement 10 AOC performance with the different bypassing scheme would have been evident (see Figure 8). These two histograms display ranges of NO conversion values on the vertical axis and ~he hit rate (percent of total readings landing within the boundanes olthe selected AOC reading range) on the horizontal axis. As shown. there was approximately a 3% improvement in the number of correct NO conversions with new bypassing. To detect these changes. the EPROM on the controll~r PCB was probed with a fairly simple logic analyzer. The logiC analyzer was then configured to trigger on accesses to a location in memory containing the results of NO conversions. By utilizing the simple statistics options given by the analyzer. each quantitative improvement in AOC performance was observed. ADC READING (HEX) FREO.: CONDITIONS: I 0·90 0% i 91·98 95% gg·AO 1% Al·AS 1% 1% 0 D 0 0 2% 0% M68HCll INDUSTRIAL CONTROLLER P 0% , I NO BYPASSING I A9·BO CHF After sufficiently instrumenting the offending assembly. the next step is to attempt to duplicate ideal operating conditions for the MCUlADC. Since every M68HCt 1 is 100% tested for AOC performance before leaving the factory. in the absence of externally induced failure. the M68HCll should maintain factory performance given identical operating conditions. Byoperating the M68HCll in near perfect conditions. the engineer leams if the failure is or is not parts related. The motivating factor for this case. however. concerned 1 Vpp noise (spaced in time at approximately the E-clock rate of the M68HCll) found when measuring VOO at the pins of the M68HC 11. Given what is known about the AOC comparator. it was best for system performance to reduce this VOO noise as much as possible. The noise was reduced by isolating the power bussIng to the M6BHCll only. The PCB foil was cut to VOO. VSS. VRL. TOTAL SAMPlES = 8192 Bl·BS B9·CO The Perfect Circuit : 0 5 10 ! '- (EXPANDED SCALE) .-J ~o 20 ~ ~ I 70 100 PERCENT OCCURRENCE (8) No Bypassing ADC CONDITIONS: 0.1 !IF CERAMIC BYPASS READING I! FREO.!i (HEX) i TOTAL SAMPLES = 8192 i M68HCll INDUSTRIAL CONTROLLER I ! 0·90 I 0% 91·98 i 98% gg.AQ i 1% ::J M·AS I 0% ] Ag.BO 0% ] Bl·BS 0% B9-CO 0% CHF 0% b b ~ ~ I (EXPANDED SCALEi OJ T 20 ~ I I 40 30 PERCENT OCCURRENCE I T 60 70 (b) Improved Bypassing NOTE: Readings are rounded to nearest 1% value. Columns with 0% and a grey bar imply >0% and <0.5%. Figure 8. Effect of Bypassing Only 481 ~ ~ 100 and VRH leading to the M68HC 11. Discrete wires were then run directly to an external laboratory-grade power supply. With this configuration, measurements were taken as before. The results of these measurements are shown in Figure 9. As the graph shows, an improvement was made over the nonbypassed assembly. Instead of a 5% error in the ADC readings, less than 0.5% of the readings were outside of the expected range. Also evident in Figure 9 is the presence of full-scale errors as before. At this point, a bypass capacitor was soldered between the M68HC 11 VDD and VSS pins. The resulting measurements, shown in Figure 10, are an apparent improvement over the previous non-bypassed assembly. However, due to the granularity of the measurement reported by the logic analyzer, it cannot be stated quantitatively how ADC READING (HEX) 0·80 much the bypassing improved the condition. Further manipulation of the bypassing network failed to improve the readings in a discernible manner. At this point, only power distribution busses had been manipulated to reduce ADC errors. Another part of the ADC circuit manipulated to yield some improvement was the linear portion interfacing the MCU to the various input signals. Consisting of 324-type opamps operated at unity gain, this linear buffer provided a low-impedance source for the ADC input multiplexer. Although not usually considered a wideband opamp, it proved too wideband forthis system. Most data comi~g from the devices feeding the 324 buffers were slowly varying DC or signals with frequencies below 500 Hz. Yet, the full bandwidth of signals allowed by the buffer passed unaltered to , , CONDITIONS: FREO. SEPARATE MCU POWER SUPPLY M68HCll INDUSTRIAL CONTROLLER TOTAL SAMPLES = 16384 0% 81·98 100% [". 99·AO 0% r~ Al·A8 0% C A9-BO 0% [' Bl·B8 0% [J B9·CO 0% [1 CHF 0% rL. . .- _ .. _. 10 5 (EXPANDED SCALE) 0 20 --.----.~- .. 30 40 50 PERCENT OCCURRENCE 60 70 80 90 100 NOTE: Readings are rounded to nearest 1% value. Columns with 0% and a grey bar imply >0% and <0.5%. Figure 9. Separate MCU Power Supply ADC READING (HEX) 0·80 81·98 CONDITIONS: FREO SEPARATE MCU POWER SUPPLY &BYPASS M68HCll INDUSTRIAL CONTROLLER TOTAL SAMPLES = 16384 0% 100% L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- , 99·AO 0% AH8 0% C 0 A9-BO 0% 0 Bl·B8 0% 0 B9·CO 0% CHF O%j o ;.- ..-.. - , - --.-, -----.,-,- - - , - - - r - - - , - - - - , - ,--~-----__1 10 (EXPANDED SCALE) --I 20 30 40 50 PERCENT OCCURRENCE 60 70 NOTE:.Readings are rounded to nearest 1% value. Columns with 0% and a grey bar imply >0% and <0.5%. Figure 10. Separate MCU Power Supply with O.lI1F Bypass 482 80 90 100 the ADC inputs. This manipulation violated a design guideline that urges the designer to tailor the bandwidth of. each ADC channel to the bandwidth olthe input signal. By properly filtering the input to the ADC, frequencies that may prove troublesome if left unfiltered will not be allowed to pass to the ADC input. To test the affect of this guideline on this specific industrial controller, 0.01 ~F capacitors were soldered to the ADC input pins althe M68HC11. The measurements taken with this configuration (see Figure 11) showed significant improvement. As shown in Figure 11 , there were still occasional occurrences of out-of-spec ADC reading